From 44dc1e0baae7c4b8a02ba06dcf396d3d452aa873 Mon Sep 17 00:00:00 2001
From: Alexey Bataev <a.bataev@outlook.com>
Date: Fri, 8 Dec 2023 13:46:25 -0800
Subject: [PATCH 001/349] [SLP]Improve findReusedOrderedScalars processing,
 NFCI.

Tries to simplify structural complexity of the findReusedOrderedScalars function.
---
 .../Transforms/Vectorize/SLPVectorizer.cpp    | 110 +++++++++++-------
 1 file changed, 68 insertions(+), 42 deletions(-)

diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 5e37e1eab95c..fe2aac78e5ab 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -3758,7 +3758,40 @@ BoUpSLP::findReusedOrderedScalars(const BoUpSLP::TreeEntry &TE) {
   OrdersType CurrentOrder(NumScalars, NumScalars);
   SmallVector<int> Positions;
   SmallBitVector UsedPositions(NumScalars);
-  const TreeEntry *STE = nullptr;
+  DenseMap<const TreeEntry *, unsigned> UsedEntries;
+  DenseMap<Value *, std::pair<const TreeEntry *, unsigned>> ValueToEntryPos;
+  for (Value *V : TE.Scalars) {
+    if (!isa<LoadInst, ExtractElementInst, ExtractValueInst>(V))
+      continue;
+    const auto *LocalSTE = getTreeEntry(V);
+    if (!LocalSTE)
+      continue;
+    unsigned Lane =
+        std::distance(LocalSTE->Scalars.begin(), find(LocalSTE->Scalars, V));
+    if (Lane >= NumScalars)
+      continue;
+    ++UsedEntries.try_emplace(LocalSTE, 0).first->getSecond();
+    ValueToEntryPos.try_emplace(V, LocalSTE, Lane);
+  }
+  if (UsedEntries.empty())
+    return std::nullopt;
+  const TreeEntry &BestSTE =
+      *std::max_element(UsedEntries.begin(), UsedEntries.end(),
+                        [](const std::pair<const TreeEntry *, unsigned> &P1,
+                           const std::pair<const TreeEntry *, unsigned> &P2) {
+                          return P1.second < P2.second;
+                        })
+           ->first;
+  UsedEntries.erase(&BestSTE);
+  const TreeEntry *SecondBestSTE = nullptr;
+  if (!UsedEntries.empty())
+    SecondBestSTE =
+        std::max_element(UsedEntries.begin(), UsedEntries.end(),
+                         [](const std::pair<const TreeEntry *, unsigned> &P1,
+                            const std::pair<const TreeEntry *, unsigned> &P2) {
+                           return P1.second < P2.second;
+                         })
+            ->first;
   // Try to find all gathered scalars that are gets vectorized in other
   // vectorize node. Here we can have only one single tree vector node to
   // correctly identify order of the gathered scalars.
@@ -3766,53 +3799,46 @@ BoUpSLP::findReusedOrderedScalars(const BoUpSLP::TreeEntry &TE) {
     Value *V = TE.Scalars[I];
     if (!isa<LoadInst, ExtractElementInst, ExtractValueInst>(V))
       continue;
-    if (const auto *LocalSTE = getTreeEntry(V)) {
-      if (!STE)
-        STE = LocalSTE;
-      else if (STE != LocalSTE)
-        // Take the order only from the single vector node.
-        return std::nullopt;
-      unsigned Lane =
-          std::distance(STE->Scalars.begin(), find(STE->Scalars, V));
-      if (Lane >= NumScalars)
-        return std::nullopt;
-      if (CurrentOrder[Lane] != NumScalars) {
-        if (Lane != I)
-          continue;
-        UsedPositions.reset(CurrentOrder[Lane]);
-      }
-      // The partial identity (where only some elements of the gather node are
-      // in the identity order) is good.
-      CurrentOrder[Lane] = I;
-      UsedPositions.set(I);
+    const auto [LocalSTE, Lane] = ValueToEntryPos.lookup(V);
+    if (!LocalSTE || (LocalSTE != &BestSTE && LocalSTE != SecondBestSTE))
+      continue;
+    if (CurrentOrder[Lane] != NumScalars) {
+      if ((CurrentOrder[Lane] >= BestSTE.Scalars.size() ||
+           BestSTE.Scalars[CurrentOrder[Lane]] == V) &&
+          (Lane != I || LocalSTE == SecondBestSTE))
+        continue;
+      UsedPositions.reset(CurrentOrder[Lane]);
     }
+    // The partial identity (where only some elements of the gather node are
+    // in the identity order) is good.
+    CurrentOrder[Lane] = I;
+    UsedPositions.set(I);
   }
   // Need to keep the order if we have a vector entry and at least 2 scalars or
   // the vectorized entry has just 2 scalars.
-  if (STE && (UsedPositions.count() > 1 || STE->Scalars.size() == 2)) {
-    auto &&IsIdentityOrder = [NumScalars](ArrayRef<unsigned> CurrentOrder) {
-      for (unsigned I = 0; I < NumScalars; ++I)
-        if (CurrentOrder[I] != I && CurrentOrder[I] != NumScalars)
-          return false;
-      return true;
-    };
-    if (IsIdentityOrder(CurrentOrder))
-      return OrdersType();
-    auto *It = CurrentOrder.begin();
-    for (unsigned I = 0; I < NumScalars;) {
-      if (UsedPositions.test(I)) {
-        ++I;
-        continue;
-      }
-      if (*It == NumScalars) {
-        *It = I;
-        ++I;
-      }
-      ++It;
+  if (BestSTE.Scalars.size() != 2 && UsedPositions.count() <= 1)
+    return std::nullopt;
+  auto IsIdentityOrder = [&](ArrayRef<unsigned> CurrentOrder) {
+    for (unsigned I = 0; I < NumScalars; ++I)
+      if (CurrentOrder[I] != I && CurrentOrder[I] != NumScalars)
+        return false;
+    return true;
+  };
+  if (IsIdentityOrder(CurrentOrder))
+    return OrdersType();
+  auto *It = CurrentOrder.begin();
+  for (unsigned I = 0; I < NumScalars;) {
+    if (UsedPositions.test(I)) {
+      ++I;
+      continue;
+    }
+    if (*It == NumScalars) {
+      *It = I;
+      ++I;
     }
-    return std::move(CurrentOrder);
+    ++It;
   }
-  return std::nullopt;
+  return std::move(CurrentOrder);
 }
 
 namespace {
-- 
GitLab


From 9810fe1a91eb9ce18246fb1528232a539dbd37fc Mon Sep 17 00:00:00 2001
From: Fangrui Song <i@maskray.me>
Date: Fri, 8 Dec 2023 15:09:22 -0800
Subject: [PATCH 002/349] [MCSchedule] Simplify and remove a C++20-deprecated
 is_pod call. NFC

---
 llvm/include/llvm/CodeGen/TargetSchedule.h | 2 +-
 llvm/include/llvm/MC/MCInstrItineraries.h  | 4 ++--
 llvm/include/llvm/MC/MCSchedule.h          | 1 -
 llvm/lib/MC/MCSchedule.cpp                 | 6 +++---
 llvm/lib/MC/MCSubtargetInfo.cpp            | 4 ++--
 5 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/TargetSchedule.h b/llvm/include/llvm/CodeGen/TargetSchedule.h
index 3d39798790cd..bfe4234abf8e 100644
--- a/llvm/include/llvm/CodeGen/TargetSchedule.h
+++ b/llvm/include/llvm/CodeGen/TargetSchedule.h
@@ -46,7 +46,7 @@ class TargetSchedModel {
   unsigned computeInstrLatency(const MCSchedClassDesc &SCDesc) const;
 
 public:
-  TargetSchedModel() : SchedModel(MCSchedModel::GetDefaultSchedModel()) {}
+  TargetSchedModel() : SchedModel(MCSchedModel::Default) {}
 
   /// Initialize the machine model for instruction scheduling.
   ///
diff --git a/llvm/include/llvm/MC/MCInstrItineraries.h b/llvm/include/llvm/MC/MCInstrItineraries.h
index d1c2e788ee81..6b29686d8c4f 100644
--- a/llvm/include/llvm/MC/MCInstrItineraries.h
+++ b/llvm/include/llvm/MC/MCInstrItineraries.h
@@ -110,8 +110,8 @@ struct InstrItinerary {
 class InstrItineraryData {
 public:
   MCSchedModel SchedModel =
-      MCSchedModel::GetDefaultSchedModel(); ///< Basic machine properties.
-  const InstrStage *Stages = nullptr;       ///< Array of stages selected
+      MCSchedModel::Default;               ///< Basic machine properties.
+  const InstrStage *Stages = nullptr;      ///< Array of stages selected
   const unsigned *OperandCycles = nullptr; ///< Array of operand cycles selected
   const unsigned *Forwardings = nullptr; ///< Array of pipeline forwarding paths
   const InstrItinerary *Itineraries =
diff --git a/llvm/include/llvm/MC/MCSchedule.h b/llvm/include/llvm/MC/MCSchedule.h
index 98ebe42cfd13..5a6471ac1c89 100644
--- a/llvm/include/llvm/MC/MCSchedule.h
+++ b/llvm/include/llvm/MC/MCSchedule.h
@@ -390,7 +390,6 @@ struct MCSchedModel {
                                            unsigned WriteResourceIdx = 0);
 
   /// Returns the default initialized model.
-  static const MCSchedModel &GetDefaultSchedModel() { return Default; }
   static const MCSchedModel Default;
 };
 
diff --git a/llvm/lib/MC/MCSchedule.cpp b/llvm/lib/MC/MCSchedule.cpp
index 990a693559a7..4f7125864c5a 100644
--- a/llvm/lib/MC/MCSchedule.cpp
+++ b/llvm/lib/MC/MCSchedule.cpp
@@ -20,8 +20,8 @@
 
 using namespace llvm;
 
-static_assert(std::is_pod<MCSchedModel>::value,
-              "We shouldn't have a static constructor here");
+static_assert(std::is_trivial_v<MCSchedModel>,
+              "MCSchedModel is required to be a trivial type");
 const MCSchedModel MCSchedModel::Default = {DefaultIssueWidth,
                                             DefaultMicroOpBufferSize,
                                             DefaultLoopMicroOpBufferSize,
@@ -30,7 +30,7 @@ const MCSchedModel MCSchedModel::Default = {DefaultIssueWidth,
                                             DefaultMispredictPenalty,
                                             false,
                                             true,
-                                            false /*EnableIntervals*/,
+                                            /*EnableIntervals=*/false,
                                             0,
                                             nullptr,
                                             nullptr,
diff --git a/llvm/lib/MC/MCSubtargetInfo.cpp b/llvm/lib/MC/MCSubtargetInfo.cpp
index 8ee823e0377b..cf3aba17fc3d 100644
--- a/llvm/lib/MC/MCSubtargetInfo.cpp
+++ b/llvm/lib/MC/MCSubtargetInfo.cpp
@@ -214,7 +214,7 @@ void MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef TuneCPU,
   if (!TuneCPU.empty())
     CPUSchedModel = &getSchedModelForCPU(TuneCPU);
   else
-    CPUSchedModel = &MCSchedModel::GetDefaultSchedModel();
+    CPUSchedModel = &MCSchedModel::Default;
 }
 
 void MCSubtargetInfo::setDefaultFeatures(StringRef CPU, StringRef TuneCPU,
@@ -319,7 +319,7 @@ const MCSchedModel &MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
       errs() << "'" << CPU
              << "' is not a recognized processor for this target"
              << " (ignoring processor)\n";
-    return MCSchedModel::GetDefaultSchedModel();
+    return MCSchedModel::Default;
   }
   assert(CPUEntry->SchedModel && "Missing processor SchedModel value");
   return *CPUEntry->SchedModel;
-- 
GitLab


From 3791b3fca6eac5e403b91550ed0f774866cf3ede Mon Sep 17 00:00:00 2001
From: Owen Pan <owenpiano@gmail.com>
Date: Fri, 8 Dec 2023 15:23:01 -0800
Subject: [PATCH 003/349] [clang-format][NFC] Clean up the driver and
 getStyle() in Format.cpp (#74794)

---
 clang/lib/Format/Format.cpp              | 95 ++++++++++++------------
 clang/tools/clang-format/ClangFormat.cpp | 40 +++++-----
 2 files changed, 65 insertions(+), 70 deletions(-)

diff --git a/clang/lib/Format/Format.cpp b/clang/lib/Format/Format.cpp
index b09487435adb..8feee7457fc3 100644
--- a/clang/lib/Format/Format.cpp
+++ b/clang/lib/Format/Format.cpp
@@ -3955,10 +3955,7 @@ llvm::Expected<FormatStyle> getStyle(StringRef StyleName, StringRef FileName,
                                      StringRef FallbackStyleName,
                                      StringRef Code, llvm::vfs::FileSystem *FS,
                                      bool AllowUnknownOptions) {
-  if (!FS)
-    FS = llvm::vfs::getRealFileSystem().get();
   FormatStyle Style = getLLVMStyle(guessLanguage(FileName, Code));
-
   FormatStyle FallbackStyle = getNoStyle();
   if (!getPredefinedStyle(FallbackStyleName, Style.Language, &FallbackStyle))
     return make_string_error("Invalid fallback style: " + FallbackStyleName);
@@ -3974,14 +3971,18 @@ llvm::Expected<FormatStyle> getStyle(StringRef StyleName, StringRef FileName,
                                AllowUnknownOptions)) {
       return make_string_error("Error parsing -style: " + ec.message());
     }
-    if (Style.InheritsParentConfig) {
-      ChildFormatTextToApply.emplace_back(
-          llvm::MemoryBuffer::getMemBuffer(StyleName, Source, false));
-    } else {
+
+    if (!Style.InheritsParentConfig)
       return Style;
-    }
+
+    ChildFormatTextToApply.emplace_back(
+        llvm::MemoryBuffer::getMemBuffer(StyleName, Source, false));
   }
 
+  if (!FS)
+    FS = llvm::vfs::getRealFileSystem().get();
+  assert(FS);
+
   // User provided clang-format file using -style=file:path/to/format/file.
   if (!Style.InheritsParentConfig &&
       StyleName.starts_with_insensitive("file:")) {
@@ -4015,18 +4016,12 @@ llvm::Expected<FormatStyle> getStyle(StringRef StyleName, StringRef FileName,
       return Style;
   }
 
-  // Reset possible inheritance
-  Style.InheritsParentConfig = false;
-
-  // Look for .clang-format/_clang-format file in the file's parent directories.
-  SmallString<128> UnsuitableConfigFiles;
   SmallString<128> Path(FileName);
   if (std::error_code EC = FS->makeAbsolute(Path))
     return make_string_error(EC.message());
 
-  llvm::SmallVector<std::string, 2> FilesToLookFor;
-  FilesToLookFor.push_back(".clang-format");
-  FilesToLookFor.push_back("_clang-format");
+  // Reset possible inheritance
+  Style.InheritsParentConfig = false;
 
   auto dropDiagnosticHandler = [](const llvm::SMDiagnostic &, void *) {};
 
@@ -4040,9 +4035,14 @@ llvm::Expected<FormatStyle> getStyle(StringRef StyleName, StringRef FileName,
     }
   };
 
+  // Look for .clang-format/_clang-format file in the file's parent directories.
+  llvm::SmallVector<std::string, 2> FilesToLookFor;
+  FilesToLookFor.push_back(".clang-format");
+  FilesToLookFor.push_back("_clang-format");
+
+  SmallString<128> UnsuitableConfigFiles;
   for (StringRef Directory = Path; !Directory.empty();
        Directory = llvm::sys::path::parent_path(Directory)) {
-
     auto Status = FS->status(Directory);
     if (!Status ||
         Status->getType() != llvm::sys::fs::file_type::directory_file) {
@@ -4055,50 +4055,51 @@ llvm::Expected<FormatStyle> getStyle(StringRef StyleName, StringRef FileName,
       llvm::sys::path::append(ConfigFile, F);
       LLVM_DEBUG(llvm::dbgs() << "Trying " << ConfigFile << "...\n");
 
-      Status = FS->status(ConfigFile.str());
-
-      if (Status &&
-          (Status->getType() == llvm::sys::fs::file_type::regular_file)) {
-        llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text =
-            loadAndParseConfigFile(ConfigFile, FS, &Style, AllowUnknownOptions);
-        if (auto EC = Text.getError()) {
-          if (EC == ParseError::Unsuitable) {
-            if (!UnsuitableConfigFiles.empty())
-              UnsuitableConfigFiles.append(", ");
-            UnsuitableConfigFiles.append(ConfigFile);
-            continue;
-          }
+      Status = FS->status(ConfigFile);
+      if (!Status ||
+          Status->getType() != llvm::sys::fs::file_type::regular_file) {
+        continue;
+      }
+
+      llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text =
+          loadAndParseConfigFile(ConfigFile, FS, &Style, AllowUnknownOptions);
+      if (auto EC = Text.getError()) {
+        if (EC != ParseError::Unsuitable) {
           return make_string_error("Error reading " + ConfigFile + ": " +
                                    EC.message());
         }
-        LLVM_DEBUG(llvm::dbgs()
-                   << "Using configuration file " << ConfigFile << "\n");
+        if (!UnsuitableConfigFiles.empty())
+          UnsuitableConfigFiles.append(", ");
+        UnsuitableConfigFiles.append(ConfigFile);
+        continue;
+      }
 
-        if (!Style.InheritsParentConfig) {
-          if (ChildFormatTextToApply.empty())
-            return Style;
+      LLVM_DEBUG(llvm::dbgs()
+                 << "Using configuration file " << ConfigFile << "\n");
 
+      if (!Style.InheritsParentConfig) {
+        if (!ChildFormatTextToApply.empty()) {
           LLVM_DEBUG(llvm::dbgs() << "Applying child configurations\n");
           applyChildFormatTexts(&Style);
-
-          return Style;
         }
+        return Style;
+      }
 
-        LLVM_DEBUG(llvm::dbgs() << "Inherits parent configuration\n");
+      LLVM_DEBUG(llvm::dbgs() << "Inherits parent configuration\n");
 
-        // Reset inheritance of style
-        Style.InheritsParentConfig = false;
+      // Reset inheritance of style
+      Style.InheritsParentConfig = false;
 
-        ChildFormatTextToApply.emplace_back(std::move(*Text));
+      ChildFormatTextToApply.emplace_back(std::move(*Text));
 
-        // Breaking out of the inner loop, since we don't want to parse
-        // .clang-format AND _clang-format, if both exist. Then we continue the
-        // inner loop (parent directories) in search for the parent
-        // configuration.
-        break;
-      }
+      // Breaking out of the inner loop, since we don't want to parse
+      // .clang-format AND _clang-format, if both exist. Then we continue the
+      // outer loop (parent directories) in search for the parent
+      // configuration.
+      break;
     }
   }
+
   if (!UnsuitableConfigFiles.empty()) {
     return make_string_error("Configuration file(s) do(es) not support " +
                              getLanguageName(Style.Language) + ": " +
diff --git a/clang/tools/clang-format/ClangFormat.cpp b/clang/tools/clang-format/ClangFormat.cpp
index 829f85b93bc7..d2e3d8d43aef 100644
--- a/clang/tools/clang-format/ClangFormat.cpp
+++ b/clang/tools/clang-format/ClangFormat.cpp
@@ -398,8 +398,8 @@ class ClangFormatDiagConsumer : public DiagnosticConsumer {
 };
 
 // Returns true on error.
-static bool format(StringRef FileName) {
-  if (!OutputXML && Inplace && FileName == "-") {
+static bool format(StringRef FileName, bool IsSTDIN) {
+  if (!OutputXML && Inplace && IsSTDIN) {
     errs() << "error: cannot use -i when reading from stdin.\n";
     return false;
   }
@@ -423,7 +423,7 @@ static bool format(StringRef FileName) {
   if (InvalidBOM) {
     errs() << "error: encoding with unsupported byte order mark \""
            << InvalidBOM << "\" detected";
-    if (FileName != "-")
+    if (!IsSTDIN)
       errs() << " in file '" << FileName << "'";
     errs() << ".\n";
     return true;
@@ -432,7 +432,7 @@ static bool format(StringRef FileName) {
   std::vector<tooling::Range> Ranges;
   if (fillRanges(Code.get(), Ranges))
     return true;
-  StringRef AssumedFileName = (FileName == "-") ? AssumeFileName : FileName;
+  StringRef AssumedFileName = IsSTDIN ? AssumeFileName : FileName;
   if (AssumedFileName.empty()) {
     llvm::errs() << "error: empty filenames are not allowed\n";
     return true;
@@ -544,28 +544,23 @@ static void PrintVersion(raw_ostream &OS) {
 }
 
 // Dump the configuration.
-static int dumpConfig() {
-  StringRef FileName;
+static int dumpConfig(bool IsSTDIN) {
   std::unique_ptr<llvm::MemoryBuffer> Code;
-  if (FileNames.empty()) {
-    // We can't read the code to detect the language if there's no
-    // file name, so leave Code empty here.
-    FileName = AssumeFileName;
-  } else {
-    // Read in the code in case the filename alone isn't enough to
-    // detect the language.
+  // We can't read the code to detect the language if there's no file name.
+  if (!IsSTDIN) {
+    // Read in the code in case the filename alone isn't enough to detect the
+    // language.
     ErrorOr<std::unique_ptr<MemoryBuffer>> CodeOrErr =
         MemoryBuffer::getFileOrSTDIN(FileNames[0]);
     if (std::error_code EC = CodeOrErr.getError()) {
       llvm::errs() << EC.message() << "\n";
       return 1;
     }
-    FileName = (FileNames[0] == "-") ? AssumeFileName : FileNames[0];
     Code = std::move(CodeOrErr.get());
   }
   llvm::Expected<clang::format::FormatStyle> FormatStyle =
-      clang::format::getStyle(Style, FileName, FallbackStyle,
-                              Code ? Code->getBuffer() : "");
+      clang::format::getStyle(Style, IsSTDIN ? AssumeFileName : FileNames[0],
+                              FallbackStyle, Code ? Code->getBuffer() : "");
   if (!FormatStyle) {
     llvm::errs() << llvm::toString(FormatStyle.takeError()) << "\n";
     return 1;
@@ -596,8 +591,11 @@ int main(int argc, const char **argv) {
     return 0;
   }
 
+  if (FileNames.empty())
+    FileNames.push_back("-");
+
   if (DumpConfig)
-    return dumpConfig();
+    return dumpConfig(FileNames[0] == "-");
 
   if (!Files.empty()) {
     std::ifstream ExternalFileOfFiles{std::string(Files)};
@@ -610,11 +608,6 @@ int main(int argc, const char **argv) {
     errs() << "Clang-formating " << LineNo << " files\n";
   }
 
-  bool Error = false;
-  if (FileNames.empty()) {
-    Error = clang::format::format("-");
-    return Error ? 1 : 0;
-  }
   if (FileNames.size() != 1 &&
       (!Offsets.empty() || !Lengths.empty() || !LineRanges.empty())) {
     errs() << "error: -offset, -length and -lines can only be used for "
@@ -623,12 +616,13 @@ int main(int argc, const char **argv) {
   }
 
   unsigned FileNo = 1;
+  bool Error = false;
   for (const auto &FileName : FileNames) {
     if (Verbose) {
       errs() << "Formatting [" << FileNo++ << "/" << FileNames.size() << "] "
              << FileName << "\n";
     }
-    Error |= clang::format::format(FileName);
+    Error |= clang::format::format(FileName, FileName == "-");
   }
   return Error ? 1 : 0;
 }
-- 
GitLab


From 18f0da26b292341f84f91d4ce731b046315cd0a1 Mon Sep 17 00:00:00 2001
From: Justin Bogner <mail@justinbogner.com>
Date: Thu, 7 Dec 2023 22:24:49 -0800
Subject: [PATCH 004/349] [HLSL][DirectX] Avoid some unnecessary casting. NFC

---
 llvm/include/llvm/Frontend/HLSL/HLSLResource.h | 2 +-
 llvm/lib/Frontend/HLSL/HLSLResource.cpp        | 9 +++++----
 llvm/lib/Target/DirectX/DXILResource.cpp       | 5 ++---
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/llvm/include/llvm/Frontend/HLSL/HLSLResource.h b/llvm/include/llvm/Frontend/HLSL/HLSLResource.h
index ba08ee519351..997ddccd687a 100644
--- a/llvm/include/llvm/Frontend/HLSL/HLSLResource.h
+++ b/llvm/include/llvm/Frontend/HLSL/HLSLResource.h
@@ -67,7 +67,7 @@ public:
 
   GlobalVariable *getGlobalVariable();
   StringRef getSourceType();
-  uint32_t getResourceKind();
+  ResourceKind getResourceKind();
   uint32_t getResourceIndex();
   uint32_t getSpace();
   MDNode *getMetadata() { return Entry; }
diff --git a/llvm/lib/Frontend/HLSL/HLSLResource.cpp b/llvm/lib/Frontend/HLSL/HLSLResource.cpp
index 59f730d8a495..a3a7d0b8696c 100644
--- a/llvm/lib/Frontend/HLSL/HLSLResource.cpp
+++ b/llvm/lib/Frontend/HLSL/HLSLResource.cpp
@@ -27,10 +27,11 @@ StringRef FrontendResource::getSourceType() {
   return cast<MDString>(Entry->getOperand(1))->getString();
 }
 
-uint32_t FrontendResource::FrontendResource::getResourceKind() {
-  return cast<ConstantInt>(
-             cast<ConstantAsMetadata>(Entry->getOperand(2))->getValue())
-      ->getLimitedValue();
+ResourceKind FrontendResource::getResourceKind() {
+  return static_cast<ResourceKind>(
+      cast<ConstantInt>(
+          cast<ConstantAsMetadata>(Entry->getOperand(2))->getValue())
+          ->getLimitedValue());
 }
 uint32_t FrontendResource::getResourceIndex() {
   return cast<ConstantInt>(
diff --git a/llvm/lib/Target/DirectX/DXILResource.cpp b/llvm/lib/Target/DirectX/DXILResource.cpp
index 0390a3f0a558..041b8fafcd6a 100644
--- a/llvm/lib/Target/DirectX/DXILResource.cpp
+++ b/llvm/lib/Target/DirectX/DXILResource.cpp
@@ -233,9 +233,8 @@ void ResourceBase::print(raw_ostream &OS, StringRef IDPrefix,
 }
 
 UAVResource::UAVResource(uint32_t I, FrontendResource R)
-    : ResourceBase(I, R),
-      Shape(static_cast<ResourceBase::Kinds>(R.getResourceKind())),
-      GloballyCoherent(false), HasCounter(false), IsROV(false), ExtProps() {
+    : ResourceBase(I, R), Shape(R.getResourceKind()), GloballyCoherent(false),
+      HasCounter(false), IsROV(false), ExtProps() {
   parseSourceType(R.getSourceType());
 }
 
-- 
GitLab


From 8615ead9a6d37e6353df1b652aadebe71ec6c242 Mon Sep 17 00:00:00 2001
From: Jan Svoboda <jan_svoboda@apple.com>
Date: Sat, 9 Dec 2023 00:43:00 +0100
Subject: [PATCH 005/349] [clang] NFCI: Make `ModuleFile::File` non-optional
 (#74892)

AFAICT, `ModuleFile::File` can be `std::nullopt` only for PCM files
loaded from the standard input. This patch starts setting that variable
to `FileManager::getSTDIN()` in that case, which makes it possible to
remove the optionality, and also simplifies code that actually reads the
file.

This is part of an effort to get rid of
`Optional{File,Directory}EntryRefDegradesTo{File,Directory}EntryPtr`.
---
 .../include/clang/Serialization/ModuleFile.h  |  6 +--
 clang/lib/Serialization/ASTReader.cpp         |  2 +-
 clang/lib/Serialization/ASTWriter.cpp         |  2 +-
 clang/lib/Serialization/GlobalModuleIndex.cpp |  4 +-
 clang/lib/Serialization/ModuleManager.cpp     | 54 ++++++++-----------
 5 files changed, 29 insertions(+), 39 deletions(-)

diff --git a/clang/include/clang/Serialization/ModuleFile.h b/clang/include/clang/Serialization/ModuleFile.h
index 48be8676cc26..70ab61dec8b6 100644
--- a/clang/include/clang/Serialization/ModuleFile.h
+++ b/clang/include/clang/Serialization/ModuleFile.h
@@ -123,8 +123,8 @@ public:
 /// other modules.
 class ModuleFile {
 public:
-  ModuleFile(ModuleKind Kind, unsigned Generation)
-      : Kind(Kind), Generation(Generation) {}
+  ModuleFile(ModuleKind Kind, FileEntryRef File, unsigned Generation)
+      : Kind(Kind), File(File), Generation(Generation) {}
   ~ModuleFile();
 
   // === General information ===
@@ -176,7 +176,7 @@ public:
   bool DidReadTopLevelSubmodule = false;
 
   /// The file entry for the module file.
-  OptionalFileEntryRefDegradesToFileEntryPtr File;
+  FileEntryRef File;
 
   /// The signature of the module file, which may be used instead of the size
   /// and modification time to identify this particular file.
diff --git a/clang/lib/Serialization/ASTReader.cpp b/clang/lib/Serialization/ASTReader.cpp
index f22da838424b..49f25d6648c8 100644
--- a/clang/lib/Serialization/ASTReader.cpp
+++ b/clang/lib/Serialization/ASTReader.cpp
@@ -5786,7 +5786,7 @@ llvm::Error ASTReader::ReadSubmoduleBlock(ModuleFile &F,
                 PartialDiagnostic(diag::err_module_file_conflict,
                                   ContextObj->DiagAllocator)
                 << CurrentModule->getTopLevelModuleName() << CurFile->getName()
-                << F.File->getName();
+                << F.File.getName();
             return DiagnosticError::create(CurrentImportLoc, ConflictError);
           }
         }
diff --git a/clang/lib/Serialization/ASTWriter.cpp b/clang/lib/Serialization/ASTWriter.cpp
index 6df815234e23..38e8b8ccbe05 100644
--- a/clang/lib/Serialization/ASTWriter.cpp
+++ b/clang/lib/Serialization/ASTWriter.cpp
@@ -1413,7 +1413,7 @@ void ASTWriter::WriteControlBlock(Preprocessor &PP, ASTContext &Context,
 
       // If we have calculated signature, there is no need to store
       // the size or timestamp.
-      Record.push_back(M.Signature ? 0 : M.File->getSize());
+      Record.push_back(M.Signature ? 0 : M.File.getSize());
       Record.push_back(M.Signature ? 0 : getTimestampForOutput(M.File));
 
       llvm::append_range(Record, M.Signature);
diff --git a/clang/lib/Serialization/GlobalModuleIndex.cpp b/clang/lib/Serialization/GlobalModuleIndex.cpp
index fb80a1998d0e..dd4fc3e00905 100644
--- a/clang/lib/Serialization/GlobalModuleIndex.cpp
+++ b/clang/lib/Serialization/GlobalModuleIndex.cpp
@@ -342,8 +342,8 @@ bool GlobalModuleIndex::loadedModuleFile(ModuleFile *File) {
   //  If the size and modification time match what we expected, record this
   // module file.
   bool Failed = true;
-  if (File->File->getSize() == Info.Size &&
-      File->File->getModificationTime() == Info.ModTime) {
+  if (File->File.getSize() == Info.Size &&
+      File->File.getModificationTime() == Info.ModTime) {
     Info.File = File;
     ModulesByFile[File] = Known->second;
 
diff --git a/clang/lib/Serialization/ModuleManager.cpp b/clang/lib/Serialization/ModuleManager.cpp
index de4cd3d05853..d1ded6cd8ee2 100644
--- a/clang/lib/Serialization/ModuleManager.cpp
+++ b/clang/lib/Serialization/ModuleManager.cpp
@@ -108,7 +108,7 @@ ModuleManager::addModule(StringRef FileName, ModuleKind Type,
 
   // Look for the file entry. This only fails if the expected size or
   // modification time differ.
-  OptionalFileEntryRefDegradesToFileEntryPtr Entry;
+  OptionalFileEntryRef Entry;
   if (Type == MK_ExplicitModule || Type == MK_PrebuiltModule) {
     // If we're not expecting to pull this file out of the module cache, it
     // might have a different mtime due to being moved across filesystems in
@@ -123,7 +123,7 @@ ModuleManager::addModule(StringRef FileName, ModuleKind Type,
     return OutOfDate;
   }
 
-  if (!Entry && FileName != "-") {
+  if (!Entry) {
     ErrorStr = "module file not found";
     return Missing;
   }
@@ -150,7 +150,7 @@ ModuleManager::addModule(StringRef FileName, ModuleKind Type,
   };
 
   // Check whether we already loaded this module, before
-  if (ModuleFile *ModuleEntry = Modules.lookup(Entry)) {
+  if (ModuleFile *ModuleEntry = Modules.lookup(*Entry)) {
     if (implicitModuleNamesMatch(Type, ModuleEntry, *Entry)) {
       // Check the stored signature.
       if (checkSignature(ModuleEntry->Signature, ExpectedSignature, ErrorStr))
@@ -163,10 +163,9 @@ ModuleManager::addModule(StringRef FileName, ModuleKind Type,
   }
 
   // Allocate a new module.
-  auto NewModule = std::make_unique<ModuleFile>(Type, Generation);
+  auto NewModule = std::make_unique<ModuleFile>(Type, *Entry, Generation);
   NewModule->Index = Chain.size();
   NewModule->FileName = FileName.str();
-  NewModule->File = Entry;
   NewModule->ImportLoc = ImportLoc;
   NewModule->InputFilesValidationTimestamp = 0;
 
@@ -198,21 +197,15 @@ ModuleManager::addModule(StringRef FileName, ModuleKind Type,
     Entry->closeFile();
     return OutOfDate;
   } else {
-    // Open the AST file.
-    llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Buf((std::error_code()));
-    if (FileName == "-") {
-      Buf = llvm::MemoryBuffer::getSTDIN();
-    } else {
-      // Get a buffer of the file and close the file descriptor when done.
-      // The file is volatile because in a parallel build we expect multiple
-      // compiler processes to use the same module file rebuilding it if needed.
-      //
-      // RequiresNullTerminator is false because module files don't need it, and
-      // this allows the file to still be mmapped.
-      Buf = FileMgr.getBufferForFile(*NewModule->File,
-                                     /*IsVolatile=*/true,
-                                     /*RequiresNullTerminator=*/false);
-    }
+    // Get a buffer of the file and close the file descriptor when done.
+    // The file is volatile because in a parallel build we expect multiple
+    // compiler processes to use the same module file rebuilding it if needed.
+    //
+    // RequiresNullTerminator is false because module files don't need it, and
+    // this allows the file to still be mmapped.
+    auto Buf = FileMgr.getBufferForFile(NewModule->File,
+                                        /*IsVolatile=*/true,
+                                        /*RequiresNullTerminator=*/false);
 
     if (!Buf) {
       ErrorStr = Buf.getError().message();
@@ -232,7 +225,7 @@ ModuleManager::addModule(StringRef FileName, ModuleKind Type,
     return OutOfDate;
 
   // We're keeping this module.  Store it everywhere.
-  Module = Modules[Entry] = NewModule.get();
+  Module = Modules[*Entry] = NewModule.get();
 
   updateModuleImports(*NewModule, ImportedBy, ImportLoc);
 
@@ -441,22 +434,19 @@ void ModuleManager::visit(llvm::function_ref<bool(ModuleFile &M)> Visitor,
 bool ModuleManager::lookupModuleFile(StringRef FileName, off_t ExpectedSize,
                                      time_t ExpectedModTime,
                                      OptionalFileEntryRef &File) {
-  File = std::nullopt;
-  if (FileName == "-")
+  if (FileName == "-") {
+    File = expectedToOptional(FileMgr.getSTDIN());
     return false;
+  }
 
   // Open the file immediately to ensure there is no race between stat'ing and
   // opening the file.
-  OptionalFileEntryRef FileOrErr =
-      expectedToOptional(FileMgr.getFileRef(FileName, /*OpenFile=*/true,
-                                            /*CacheFailure=*/false));
-  if (!FileOrErr)
-    return false;
-
-  File = *FileOrErr;
+  File = FileMgr.getOptionalFileRef(FileName, /*OpenFile=*/true,
+                                    /*CacheFailure=*/false);
 
-  if ((ExpectedSize && ExpectedSize != File->getSize()) ||
-      (ExpectedModTime && ExpectedModTime != File->getModificationTime()))
+  if (File &&
+      ((ExpectedSize && ExpectedSize != File->getSize()) ||
+       (ExpectedModTime && ExpectedModTime != File->getModificationTime())))
     // Do not destroy File, as it may be referenced. If we need to rebuild it,
     // it will be destroyed by removeModules.
     return true;
-- 
GitLab


From 437b4f1c2e2478381073bd8ae82fdb556e51b10e Mon Sep 17 00:00:00 2001
From: Lang Hames <lhames@gmail.com>
Date: Fri, 8 Dec 2023 15:56:56 -0800
Subject: [PATCH 006/349] [ORC-RT][ORC][MachO] Refactor dlsym to extract a
 reusable bulk-lookup API.

MachOPlatformRuntimeState::lookupSymbols encapsulates the approach used in
dlsym in bb41fc682ee, but generalizes it to multiple symbols:
  1. try to resolve symbols locally
  2. issue a push-request for any unresolved symbols
  3. re-try local resolution

In the future lookupSymbols can serve as the basis for a public bulk lookup
API in the ORC runtime.
---
 compiler-rt/lib/orc/macho_platform.cpp | 141 ++++++++++++-------------
 1 file changed, 69 insertions(+), 72 deletions(-)

diff --git a/compiler-rt/lib/orc/macho_platform.cpp b/compiler-rt/lib/orc/macho_platform.cpp
index 02da8a58b1c6..24c08cc00dd1 100644
--- a/compiler-rt/lib/orc/macho_platform.cpp
+++ b/compiler-rt/lib/orc/macho_platform.cpp
@@ -352,36 +352,13 @@ private:
   Error requestPushSymbols(JITDylibState &JDS,
                            span<std::pair<std::string_view, bool>> Symbols);
 
-  /// Visits the symbol table for the JITDylib associated with DSOHandle.
-  /// Visitor should be callable as
-  ///
-  ///   void (size_t,
-  ///         std::optional<std::pair<ExecutorAddr, MachOExecutorSymbolFlags>>)
-  ///
-  /// The visitor function will be called for each element of the Symbols, but
-  /// in an arbitrary order. The first argument of the callback will indicate
-  /// the index of the result. The second argument will be std::nullopt (if the
-  /// symbol at the given index was not present in the symbol table), or a
-  /// pair containing the symbol's address and flags.
-  ///
-  /// This function will remove all elements of Symbols that are found, leaving
-  /// only the symbols that were not. This allows it to dovetail with
-  /// requestPushSymbols, enabling the following idiom:
-  ///
-  /// ...
-  /// visitSymbolAddrs(DSO, Symbols);
-  /// if (!Symbols.empty()) {
-  ///   requestPushSymbols(DSO, Symbols);
-  ///   visitSymbolAddrs(DSO, Symbols);
-  ///   for (auto &Sym : Symbols) {
-  ///     -- handle symbols that were not found --
-  ///   }
-  /// }
-  ///
-  template <typename VisitorFn>
-  void visitSymbolAddrs(JITDylibState &JDS,
-                        std::vector<std::pair<std::string_view, bool>> &Symbols,
-                        VisitorFn &&Visit);
+  /// Attempts to look up the given symbols locally, requesting a push from the
+  /// remote if they're not found. Results are written to the Result span, which
+  /// must have the same size as the Symbols span.
+  Error
+  lookupSymbols(JITDylibState &JDS, std::unique_lock<std::mutex> &JDStatesLock,
+                span<std::pair<ExecutorAddr, MachOExecutorSymbolFlags>> Result,
+                span<std::pair<std::string_view, bool>> Symbols);
 
   bool lookupUnwindSections(void *Addr, unw_dynamic_unwind_sections &Info);
 
@@ -839,43 +816,16 @@ void *MachOPlatformRuntimeState::dlsym(void *DSOHandle, const char *Symbol) {
     return nullptr;
   }
 
-  std::string MangledName("_");
-  MangledName += Symbol;
-  std::vector<std::pair<std::string_view, bool>> Symbols;
-  Symbols.push_back({MangledName, false});
+  std::string MangledName = std::string("_") + Symbol;
+  std::pair<std::string_view, bool> Lookup(MangledName, false);
+  std::pair<ExecutorAddr, MachOExecutorSymbolFlags> Result;
 
-  ExecutorAddr Result;
-  using ElemResult =
-      std::optional<std::pair<ExecutorAddr, MachOExecutorSymbolFlags>>;
-
-  // Try to resolve the symbol in the local symbol tables.
-  visitSymbolAddrs(*JDS, Symbols, [&](size_t Idx, ElemResult E) {
-    if (E)
-      Result = E->first;
-  });
-
-  // Return early if we found it.
-  if (Symbols.empty())
-    return Result.toPtr<void *>();
-
-  // Otherwise call back to the controller to try to request that the symbol
-  // be materialized.
-  Lock.unlock();
-  if (auto Err = requestPushSymbols(*JDS, {Symbols.data(), Symbols.size()})) {
+  if (auto Err = lookupSymbols(*JDS, Lock, {&Result, 1}, {&Lookup, 1})) {
     DLFcnError = toString(std::move(Err));
     return nullptr;
   }
-  Lock.lock();
-
-  // Try another local resolution.
-  visitSymbolAddrs(*JDS, Symbols, [&](size_t Idx, ElemResult E) {
-    if (E)
-      Result = E->first;
-  });
 
-  // At this point Result has either been set (if we found the symbol) or is
-  // still null (if we didn't). Either way it's the right value.
-  return Result.toPtr<void *>();
+  return Result.first.toPtr<void *>();
 }
 
 int MachOPlatformRuntimeState::registerAtExit(void (*F)(void *), void *Arg,
@@ -967,22 +917,69 @@ Error MachOPlatformRuntimeState::requestPushSymbols(
   return OpErr;
 }
 
-template <typename VisitorFn>
-void MachOPlatformRuntimeState::visitSymbolAddrs(
-    JITDylibState &JDS, std::vector<std::pair<std::string_view, bool>> &Symbols,
-    VisitorFn &&Visit) {
-
-  std::vector<std::pair<std::string_view, bool>> RemainingSymbols;
-
+Error MachOPlatformRuntimeState::lookupSymbols(
+    JITDylibState &JDS, std::unique_lock<std::mutex> &JDStatesLock,
+    span<std::pair<ExecutorAddr, MachOExecutorSymbolFlags>> Result,
+    span<std::pair<std::string_view, bool>> Symbols) {
+  assert(JDStatesLock.owns_lock() &&
+         "JDStatesLock should be locked at call-site");
+  assert(Result.size() == Symbols.size() &&
+         "Results and Symbols span sizes should match");
+
+  // Make an initial pass over the local symbol table.
+  std::vector<size_t> MissingSymbolIndexes;
   for (size_t Idx = 0; Idx != Symbols.size(); ++Idx) {
     auto I = JDS.SymbolTable.find(Symbols[Idx].first);
     if (I != JDS.SymbolTable.end())
-      Visit(Idx, I->second);
+      Result[Idx] = I->second;
     else
-      RemainingSymbols.push_back(Symbols[Idx]);
+      MissingSymbolIndexes.push_back(Idx);
   }
 
-  Symbols = std::move(RemainingSymbols);
+  // If everything has been resolved already then bail out early.
+  if (MissingSymbolIndexes.empty())
+    return Error::success();
+
+  // Otherwise call back to the controller to try to request that the symbol
+  // be materialized.
+  std::vector<std::pair<std::string_view, bool>> MissingSymbols;
+  MissingSymbols.reserve(MissingSymbolIndexes.size());
+  printdbg("requesting push of %i missing symbols...\n",
+           MissingSymbolIndexes.size());
+  for (auto MissingIdx : MissingSymbolIndexes)
+    MissingSymbols.push_back(Symbols[MissingIdx]);
+
+  JDStatesLock.unlock();
+  if (auto Err = requestPushSymbols(
+          JDS, {MissingSymbols.data(), MissingSymbols.size()}))
+    return Err;
+  JDStatesLock.lock();
+
+  // Try to resolve the previously missing symbols locally.
+  std::vector<size_t> MissingRequiredSymbols;
+  for (auto MissingIdx : MissingSymbolIndexes) {
+    auto I = JDS.SymbolTable.find(Symbols[MissingIdx].first);
+    if (I != JDS.SymbolTable.end())
+      Result[MissingIdx] = I->second;
+    else {
+      if (Symbols[MissingIdx].second)
+        MissingRequiredSymbols.push_back(MissingIdx);
+      else
+        Result[MissingIdx] = {ExecutorAddr(), {}};
+    }
+  }
+
+  // Error out if any missing symbols could not be resolved.
+  if (!MissingRequiredSymbols.empty()) {
+    std::ostringstream ErrStream;
+    ErrStream << "Lookup could not find required symbols: [ ";
+    for (auto MissingIdx : MissingRequiredSymbols)
+      ErrStream << "\"" << Symbols[MissingIdx].first << "\" ";
+    ErrStream << "]";
+    return make_error<StringError>(ErrStream.str());
+  }
+
+  return Error::success();
 }
 
 // eh-frame registration functions.
-- 
GitLab


From a5bdc4a4604272fa2b2c60fa9dde7aee05456162 Mon Sep 17 00:00:00 2001
From: Florian Mayer <fmayer@google.com>
Date: Fri, 8 Dec 2023 17:16:56 -0800
Subject: [PATCH 007/349] [scudo] do not store size inside ring buffer (#74541)

---
 compiler-rt/lib/scudo/standalone/combined.h   | 51 +++++++++++--------
 .../standalone/fuzz/get_error_info_fuzzer.cpp |  9 ++--
 .../scudo/standalone/wrappers_c_bionic.cpp    |  5 +-
 3 files changed, 35 insertions(+), 30 deletions(-)

diff --git a/compiler-rt/lib/scudo/standalone/combined.h b/compiler-rt/lib/scudo/standalone/combined.h
index 25ad11dbf7ee..65ddc488370a 100644
--- a/compiler-rt/lib/scudo/standalone/combined.h
+++ b/compiler-rt/lib/scudo/standalone/combined.h
@@ -14,6 +14,7 @@
 #include "flags.h"
 #include "flags_parser.h"
 #include "local_cache.h"
+#include "mem_map.h"
 #include "memtag.h"
 #include "options.h"
 #include "quarantine.h"
@@ -935,8 +936,7 @@ public:
 
   uptr getRingBufferSize() {
     initThreadMaybe();
-    auto *RingBuffer = getRingBuffer();
-    return RingBuffer ? ringBufferSizeInBytes(RingBuffer->Size) : 0;
+    return RingBufferElements ? ringBufferSizeInBytes(RingBufferElements) : 0;
   }
 
   static bool setRingBufferSizeForBuffer(char *Buffer, size_t Size) {
@@ -966,8 +966,9 @@ public:
   static void getErrorInfo(struct scudo_error_info *ErrorInfo,
                            uintptr_t FaultAddr, const char *DepotPtr,
                            const char *RegionInfoPtr, const char *RingBufferPtr,
-                           const char *Memory, const char *MemoryTags,
-                           uintptr_t MemoryAddr, size_t MemorySize) {
+                           size_t RingBufferSize, const char *Memory,
+                           const char *MemoryTags, uintptr_t MemoryAddr,
+                           size_t MemorySize) {
     *ErrorInfo = {};
     if (!allocatorSupportsMemoryTagging<Config>() ||
         MemoryAddr + MemorySize < MemoryAddr)
@@ -986,7 +987,7 @@ public:
     // Check the ring buffer. For primary allocations this will only find UAF;
     // for secondary allocations we can find either UAF or OOB.
     getRingBufferErrorInfo(ErrorInfo, NextErrorReport, FaultAddr, Depot,
-                           RingBufferPtr);
+                           RingBufferPtr, RingBufferSize);
 
     // Check for OOB in the 28 blocks surrounding the 3 we checked earlier.
     // Beyond that we are likely to hit false positives.
@@ -1051,15 +1052,15 @@ private:
       atomic_u32 DeallocationTid;
     };
 
-    MemMapT MemMap;
     atomic_uptr Pos;
-    u32 Size;
     // An array of Size (at least one) elements of type Entry is immediately
     // following to this struct.
   };
   // Pointer to memory mapped area starting with AllocationRingBuffer struct,
   // and immediately followed by Size elements of type Entry.
   char *RawRingBuffer = {};
+  u32 RingBufferElements = 0;
+  MemMapT RawRingBufferMap;
 
   // The following might get optimized out by the compiler.
   NOINLINE void performSanityChecks() {
@@ -1267,7 +1268,7 @@ private:
                             u32 DeallocationTid) {
     uptr Pos = atomic_fetch_add(&getRingBuffer()->Pos, 1, memory_order_relaxed);
     typename AllocationRingBuffer::Entry *Entry =
-        getRingBufferEntry(RawRingBuffer, Pos % getRingBuffer()->Size);
+        getRingBufferEntry(RawRingBuffer, Pos % RingBufferElements);
 
     // First invalidate our entry so that we don't attempt to interpret a
     // partially written state in getSecondaryErrorInfo(). The fences below
@@ -1408,17 +1409,19 @@ private:
                                      size_t &NextErrorReport,
                                      uintptr_t FaultAddr,
                                      const StackDepot *Depot,
-                                     const char *RingBufferPtr) {
+                                     const char *RingBufferPtr,
+                                     size_t RingBufferSize) {
     auto *RingBuffer =
         reinterpret_cast<const AllocationRingBuffer *>(RingBufferPtr);
-    if (!RingBuffer || RingBuffer->Size == 0)
+    size_t RingBufferElements = ringBufferElementsFromBytes(RingBufferSize);
+    if (!RingBuffer || RingBufferElements == 0)
       return;
     uptr Pos = atomic_load_relaxed(&RingBuffer->Pos);
 
-    for (uptr I = Pos - 1;
-         I != Pos - 1 - RingBuffer->Size && NextErrorReport != NumErrorReports;
+    for (uptr I = Pos - 1; I != Pos - 1 - RingBufferElements &&
+                           NextErrorReport != NumErrorReports;
          --I) {
-      auto *Entry = getRingBufferEntry(RingBufferPtr, I % RingBuffer->Size);
+      auto *Entry = getRingBufferEntry(RingBufferPtr, I % RingBufferElements);
       uptr EntryPtr = atomic_load_relaxed(&Entry->Ptr);
       if (!EntryPtr)
         continue;
@@ -1508,9 +1511,8 @@ private:
                 getPageSizeCached()),
         "scudo:ring_buffer");
     RawRingBuffer = reinterpret_cast<char *>(MemMap.getBase());
-    auto *RingBuffer = reinterpret_cast<AllocationRingBuffer *>(RawRingBuffer);
-    RingBuffer->MemMap = MemMap;
-    RingBuffer->Size = AllocationRingBufferSize;
+    RawRingBufferMap = MemMap;
+    RingBufferElements = AllocationRingBufferSize;
     static_assert(sizeof(AllocationRingBuffer) %
                           alignof(typename AllocationRingBuffer::Entry) ==
                       0,
@@ -1520,16 +1522,23 @@ private:
   void unmapRingBuffer() {
     auto *RingBuffer = getRingBuffer();
     if (RingBuffer != nullptr) {
-      MemMapT MemMap = RingBuffer->MemMap;
-      MemMap.unmap(MemMap.getBase(), MemMap.getCapacity());
+      RawRingBufferMap.unmap(RawRingBufferMap.getBase(),
+                             RawRingBufferMap.getCapacity());
     }
     RawRingBuffer = nullptr;
   }
 
-  static constexpr size_t ringBufferSizeInBytes(u32 AllocationRingBufferSize) {
+  static constexpr size_t ringBufferSizeInBytes(u32 RingBufferElements) {
     return sizeof(AllocationRingBuffer) +
-           AllocationRingBufferSize *
-               sizeof(typename AllocationRingBuffer::Entry);
+           RingBufferElements * sizeof(typename AllocationRingBuffer::Entry);
+  }
+
+  static constexpr size_t ringBufferElementsFromBytes(size_t Bytes) {
+    if (Bytes < sizeof(AllocationRingBuffer)) {
+      return 0;
+    }
+    return (Bytes - sizeof(AllocationRingBuffer)) /
+           sizeof(typename AllocationRingBuffer::Entry);
   }
 
   inline AllocationRingBuffer *getRingBuffer() {
diff --git a/compiler-rt/lib/scudo/standalone/fuzz/get_error_info_fuzzer.cpp b/compiler-rt/lib/scudo/standalone/fuzz/get_error_info_fuzzer.cpp
index 74456450a476..5b01ebe11c09 100644
--- a/compiler-rt/lib/scudo/standalone/fuzz/get_error_info_fuzzer.cpp
+++ b/compiler-rt/lib/scudo/standalone/fuzz/get_error_info_fuzzer.cpp
@@ -46,14 +46,11 @@ extern "C" int LLVMFuzzerTestOneInput(uint8_t *Data, size_t Size) {
   }
 
   std::string RingBufferBytes = FDP.ConsumeRemainingBytesAsString();
-  // RingBuffer is too short.
-  if (!AllocatorT::setRingBufferSizeForBuffer(RingBufferBytes.data(),
-                                              RingBufferBytes.size()))
-    return 0;
 
   scudo_error_info ErrorInfo;
   AllocatorT::getErrorInfo(&ErrorInfo, FaultAddr, StackDepot.data(),
-                           RegionInfo.data(), RingBufferBytes.data(), Memory,
-                           MemoryTags, MemoryAddr, MemorySize);
+                           RegionInfo.data(), RingBufferBytes.data(),
+                           RingBufferBytes.size(), Memory, MemoryTags,
+                           MemoryAddr, MemorySize);
   return 0;
 }
diff --git a/compiler-rt/lib/scudo/standalone/wrappers_c_bionic.cpp b/compiler-rt/lib/scudo/standalone/wrappers_c_bionic.cpp
index f203615ab360..21694c3f17fe 100644
--- a/compiler-rt/lib/scudo/standalone/wrappers_c_bionic.cpp
+++ b/compiler-rt/lib/scudo/standalone/wrappers_c_bionic.cpp
@@ -44,10 +44,9 @@ INTERFACE void __scudo_get_error_info(
     const char *ring_buffer, size_t ring_buffer_size, const char *memory,
     const char *memory_tags, uintptr_t memory_addr, size_t memory_size) {
   (void)(stack_depot_size);
-  (void)(ring_buffer_size);
   Allocator.getErrorInfo(error_info, fault_addr, stack_depot, region_info,
-                         ring_buffer, memory, memory_tags, memory_addr,
-                         memory_size);
+                         ring_buffer, ring_buffer_size, memory, memory_tags,
+                         memory_addr, memory_size);
 }
 
 INTERFACE const char *__scudo_get_stack_depot_addr() {
-- 
GitLab


From f1e3e8a14f056a0929f62e29c51667aa7dbe4db8 Mon Sep 17 00:00:00 2001
From: Jan Svoboda <jan_svoboda@apple.com>
Date: Fri, 8 Dec 2023 18:09:44 -0800
Subject: [PATCH 008/349] [ORC-RT][ORC][MachO] Fix build after 437b4f1c

---
 compiler-rt/lib/orc/macho_platform.cpp | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/compiler-rt/lib/orc/macho_platform.cpp b/compiler-rt/lib/orc/macho_platform.cpp
index 24c08cc00dd1..e3a1cdf3c4fc 100644
--- a/compiler-rt/lib/orc/macho_platform.cpp
+++ b/compiler-rt/lib/orc/macho_platform.cpp
@@ -944,8 +944,10 @@ Error MachOPlatformRuntimeState::lookupSymbols(
   // be materialized.
   std::vector<std::pair<std::string_view, bool>> MissingSymbols;
   MissingSymbols.reserve(MissingSymbolIndexes.size());
-  printdbg("requesting push of %i missing symbols...\n",
-           MissingSymbolIndexes.size());
+  ORC_RT_DEBUG({
+    printdbg("requesting push of %i missing symbols...\n",
+             MissingSymbolIndexes.size());
+  });
   for (auto MissingIdx : MissingSymbolIndexes)
     MissingSymbols.push_back(Symbols[MissingIdx]);
 
-- 
GitLab


From 0cb0a48cdea730e885e8c955ba1687a8191f824c Mon Sep 17 00:00:00 2001
From: Jan Svoboda <jan_svoboda@apple.com>
Date: Sat, 9 Dec 2023 03:22:41 +0100
Subject: [PATCH 009/349] [clang] NFC: Remove
 `OptionalFileEntryRefDegradesToFileEntryPtr` (#74899)

---
 .../ExpandModularHeadersPPCallbacks.cpp       |  2 +-
 clang/include/clang/Basic/FileEntry.h         | 66 -------------------
 clang/include/clang/Basic/Module.h            |  2 +-
 clang/include/clang/Basic/SourceManager.h     | 14 ++--
 clang/include/clang/Lex/PreprocessorLexer.h   |  2 +-
 .../include/clang/Serialization/ModuleFile.h  |  2 +-
 clang/lib/Frontend/CompilerInstance.cpp       |  2 +-
 clang/lib/Lex/ModuleMap.cpp                   |  4 +-
 clang/lib/Lex/PPDirectives.cpp                |  3 +-
 clang/lib/Lex/Pragma.cpp                      |  2 +-
 clang/lib/Lex/PreprocessorLexer.cpp           |  3 +-
 clang/lib/Serialization/ASTReader.cpp         |  6 +-
 clang/lib/Serialization/ASTWriter.cpp         |  6 +-
 clang/lib/Serialization/ModuleManager.cpp     |  4 +-
 .../DependencyScanning/ModuleDepCollector.cpp |  2 +-
 clang/tools/libclang/CXIndexDataConsumer.cpp  |  8 +--
 clang/tools/libclang/CXIndexDataConsumer.h    |  4 +-
 clang/unittests/Basic/FileEntryTest.cpp       | 25 -------
 18 files changed, 33 insertions(+), 124 deletions(-)

diff --git a/clang-tools-extra/clang-tidy/ExpandModularHeadersPPCallbacks.cpp b/clang-tools-extra/clang-tidy/ExpandModularHeadersPPCallbacks.cpp
index 52cc2e6569b0..0b1e9f59e1a7 100644
--- a/clang-tools-extra/clang-tidy/ExpandModularHeadersPPCallbacks.cpp
+++ b/clang-tools-extra/clang-tidy/ExpandModularHeadersPPCallbacks.cpp
@@ -171,7 +171,7 @@ void ExpandModularHeadersPPCallbacks::InclusionDirective(
   if (Imported) {
     serialization::ModuleFile *MF =
         Compiler.getASTReader()->getModuleManager().lookup(
-            Imported->getASTFile());
+            *Imported->getASTFile());
     handleModuleFile(MF);
   }
   parseToLocation(DirectiveLoc);
diff --git a/clang/include/clang/Basic/FileEntry.h b/clang/include/clang/Basic/FileEntry.h
index 6351aeae92e2..35efa147950f 100644
--- a/clang/include/clang/Basic/FileEntry.h
+++ b/clang/include/clang/Basic/FileEntry.h
@@ -279,72 +279,6 @@ template <> struct DenseMapInfo<clang::FileEntryRef> {
 
 namespace clang {
 
-/// Wrapper around OptionalFileEntryRef that degrades to 'const FileEntry*',
-/// facilitating incremental patches to propagate FileEntryRef.
-///
-/// This class can be used as return value or field where it's convenient for
-/// an OptionalFileEntryRef to degrade to a 'const FileEntry*'. The purpose
-/// is to avoid code churn due to dances like the following:
-/// \code
-/// // Old code.
-/// lvalue = rvalue;
-///
-/// // Temporary code from an incremental patch.
-/// OptionalFileEntryRef MaybeF = rvalue;
-/// lvalue = MaybeF ? &MaybeF.getFileEntry() : nullptr;
-///
-/// // Final code.
-/// lvalue = rvalue;
-/// \endcode
-///
-/// FIXME: Once FileEntryRef is "everywhere" and FileEntry::LastRef and
-/// FileEntry::getName have been deleted, delete this class and replace
-/// instances with OptionalFileEntryRef.
-class OptionalFileEntryRefDegradesToFileEntryPtr : public OptionalFileEntryRef {
-public:
-  OptionalFileEntryRefDegradesToFileEntryPtr() = default;
-  OptionalFileEntryRefDegradesToFileEntryPtr(
-      OptionalFileEntryRefDegradesToFileEntryPtr &&) = default;
-  OptionalFileEntryRefDegradesToFileEntryPtr(
-      const OptionalFileEntryRefDegradesToFileEntryPtr &) = default;
-  OptionalFileEntryRefDegradesToFileEntryPtr &
-  operator=(OptionalFileEntryRefDegradesToFileEntryPtr &&) = default;
-  OptionalFileEntryRefDegradesToFileEntryPtr &
-  operator=(const OptionalFileEntryRefDegradesToFileEntryPtr &) = default;
-
-  OptionalFileEntryRefDegradesToFileEntryPtr(std::nullopt_t) {}
-  OptionalFileEntryRefDegradesToFileEntryPtr(FileEntryRef Ref)
-      : OptionalFileEntryRef(Ref) {}
-  OptionalFileEntryRefDegradesToFileEntryPtr(OptionalFileEntryRef MaybeRef)
-      : OptionalFileEntryRef(MaybeRef) {}
-
-  OptionalFileEntryRefDegradesToFileEntryPtr &operator=(std::nullopt_t) {
-    OptionalFileEntryRef::operator=(std::nullopt);
-    return *this;
-  }
-  OptionalFileEntryRefDegradesToFileEntryPtr &operator=(FileEntryRef Ref) {
-    OptionalFileEntryRef::operator=(Ref);
-    return *this;
-  }
-  OptionalFileEntryRefDegradesToFileEntryPtr &
-  operator=(OptionalFileEntryRef MaybeRef) {
-    OptionalFileEntryRef::operator=(MaybeRef);
-    return *this;
-  }
-
-  /// Degrade to 'const FileEntry *' to allow  FileEntry::LastRef and
-  /// FileEntry::getName have been deleted, delete this class and replace
-  /// instances with OptionalFileEntryRef
-  operator const FileEntry *() const {
-    return has_value() ? &(*this)->getFileEntry() : nullptr;
-  }
-};
-
-static_assert(
-    std::is_trivially_copyable<
-        OptionalFileEntryRefDegradesToFileEntryPtr>::value,
-    "OptionalFileEntryRefDegradesToFileEntryPtr should be trivially copyable");
-
 inline bool operator==(const FileEntry *LHS, const OptionalFileEntryRef &RHS) {
   return LHS == (RHS ? &RHS->getFileEntry() : nullptr);
 }
diff --git a/clang/include/clang/Basic/Module.h b/clang/include/clang/Basic/Module.h
index d29cc0b45d58..23f263c89511 100644
--- a/clang/include/clang/Basic/Module.h
+++ b/clang/include/clang/Basic/Module.h
@@ -672,7 +672,7 @@ public:
   }
 
   /// The serialized AST file for this module, if one was created.
-  OptionalFileEntryRefDegradesToFileEntryPtr getASTFile() const {
+  OptionalFileEntryRef getASTFile() const {
     return getTopLevelModule()->ASTFile;
   }
 
diff --git a/clang/include/clang/Basic/SourceManager.h b/clang/include/clang/Basic/SourceManager.h
index 985ea6354b82..d2ece14da0b1 100644
--- a/clang/include/clang/Basic/SourceManager.h
+++ b/clang/include/clang/Basic/SourceManager.h
@@ -143,7 +143,7 @@ public:
   ///
   /// FIXME: Make non-optional using a virtual file as needed, remove \c
   /// Filename and use \c OrigEntry.getNameAsRequested() instead.
-  OptionalFileEntryRefDegradesToFileEntryPtr OrigEntry;
+  OptionalFileEntryRef OrigEntry;
 
   /// References the file which the contents were actually loaded from.
   ///
@@ -1064,8 +1064,8 @@ public:
 
   /// Returns the FileEntry record for the provided FileID.
   const FileEntry *getFileEntryForID(FileID FID) const {
-    if (auto *Entry = getSLocEntryForFile(FID))
-      return Entry->getFile().getContentCache().OrigEntry;
+    if (auto FE = getFileEntryRefForID(FID))
+      return *FE;
     return nullptr;
   }
 
@@ -1083,9 +1083,11 @@ public:
   std::optional<StringRef> getNonBuiltinFilenameForID(FileID FID) const;
 
   /// Returns the FileEntry record for the provided SLocEntry.
-  const FileEntry *getFileEntryForSLocEntry(const SrcMgr::SLocEntry &sloc) const
-  {
-    return sloc.getFile().getContentCache().OrigEntry;
+  const FileEntry *
+  getFileEntryForSLocEntry(const SrcMgr::SLocEntry &SLocEntry) const {
+    if (auto FE = SLocEntry.getFile().getContentCache().OrigEntry)
+      return *FE;
+    return nullptr;
   }
 
   /// Return a StringRef to the source buffer data for the
diff --git a/clang/include/clang/Lex/PreprocessorLexer.h b/clang/include/clang/Lex/PreprocessorLexer.h
index eebaad7d50db..d71fe708ab20 100644
--- a/clang/include/clang/Lex/PreprocessorLexer.h
+++ b/clang/include/clang/Lex/PreprocessorLexer.h
@@ -157,7 +157,7 @@ public:
 
   /// getFileEntry - Return the FileEntry corresponding to this FileID.  Like
   /// getFileID(), this only works for lexers with attached preprocessors.
-  OptionalFileEntryRefDegradesToFileEntryPtr getFileEntry() const;
+  OptionalFileEntryRef getFileEntry() const;
 
   /// Iterator that traverses the current stack of preprocessor
   /// conditional directives (\#if/\#ifdef/\#ifndef).
diff --git a/clang/include/clang/Serialization/ModuleFile.h b/clang/include/clang/Serialization/ModuleFile.h
index 70ab61dec8b6..9a14129d72ff 100644
--- a/clang/include/clang/Serialization/ModuleFile.h
+++ b/clang/include/clang/Serialization/ModuleFile.h
@@ -104,7 +104,7 @@ public:
     return File;
   }
 
-  OptionalFileEntryRefDegradesToFileEntryPtr getFile() const {
+  OptionalFileEntryRef getFile() const {
     if (auto *P = Val.getPointer())
       return FileEntryRef(*P);
     return std::nullopt;
diff --git a/clang/lib/Frontend/CompilerInstance.cpp b/clang/lib/Frontend/CompilerInstance.cpp
index e5f8c0746a99..56bbef9697b6 100644
--- a/clang/lib/Frontend/CompilerInstance.cpp
+++ b/clang/lib/Frontend/CompilerInstance.cpp
@@ -2260,7 +2260,7 @@ GlobalModuleIndex *CompilerInstance::loadGlobalModuleIndex(
     for (ModuleMap::module_iterator I = MMap.module_begin(),
         E = MMap.module_end(); I != E; ++I) {
       Module *TheModule = I->second;
-      const FileEntry *Entry = TheModule->getASTFile();
+      OptionalFileEntryRef Entry = TheModule->getASTFile();
       if (!Entry) {
         SmallVector<std::pair<IdentifierInfo *, SourceLocation>, 2> Path;
         Path.push_back(std::make_pair(
diff --git a/clang/lib/Lex/ModuleMap.cpp b/clang/lib/Lex/ModuleMap.cpp
index 1d67e275cb47..268b72c966ab 100644
--- a/clang/lib/Lex/ModuleMap.cpp
+++ b/clang/lib/Lex/ModuleMap.cpp
@@ -1067,9 +1067,7 @@ Module *ModuleMap::inferFrameworkModule(DirectoryEntryRef FrameworkDir,
     if (!canInfer)
       return nullptr;
   } else {
-    OptionalFileEntryRefDegradesToFileEntryPtr ModuleMapRef =
-        getModuleMapFileForUniquing(Parent);
-    ModuleMapFile = ModuleMapRef;
+    ModuleMapFile = getModuleMapFileForUniquing(Parent);
   }
 
   // Look for an umbrella header.
diff --git a/clang/lib/Lex/PPDirectives.cpp b/clang/lib/Lex/PPDirectives.cpp
index 956e2276f25b..14003480d7fa 100644
--- a/clang/lib/Lex/PPDirectives.cpp
+++ b/clang/lib/Lex/PPDirectives.cpp
@@ -1934,7 +1934,8 @@ Preprocessor::getIncludeNextStart(const Token &IncludeNextTok) const {
     // Start looking up in the directory *after* the one in which the current
     // file would be found, if any.
     assert(CurPPLexer && "#include_next directive in macro?");
-    LookupFromFile = CurPPLexer->getFileEntry();
+    if (auto FE = CurPPLexer->getFileEntry())
+      LookupFromFile = *FE;
     Lookup = nullptr;
   } else if (!Lookup) {
     // The current file was not found by walking the include path. Either it
diff --git a/clang/lib/Lex/Pragma.cpp b/clang/lib/Lex/Pragma.cpp
index 35ab42cb6b5e..499813f8ab7d 100644
--- a/clang/lib/Lex/Pragma.cpp
+++ b/clang/lib/Lex/Pragma.cpp
@@ -548,7 +548,7 @@ void Preprocessor::HandlePragmaDependency(Token &DependencyTok) {
     return;
   }
 
-  const FileEntry *CurFile = getCurrentFileLexer()->getFileEntry();
+  OptionalFileEntryRef CurFile = getCurrentFileLexer()->getFileEntry();
 
   // If this file is older than the file it depends on, emit a diagnostic.
   if (CurFile && CurFile->getModificationTime() < File->getModificationTime()) {
diff --git a/clang/lib/Lex/PreprocessorLexer.cpp b/clang/lib/Lex/PreprocessorLexer.cpp
index 23c80d375214..7551ba235fe9 100644
--- a/clang/lib/Lex/PreprocessorLexer.cpp
+++ b/clang/lib/Lex/PreprocessorLexer.cpp
@@ -47,7 +47,6 @@ void PreprocessorLexer::LexIncludeFilename(Token &FilenameTok) {
 
 /// getFileEntry - Return the FileEntry corresponding to this FileID.  Like
 /// getFileID(), this only works for lexers with attached preprocessors.
-OptionalFileEntryRefDegradesToFileEntryPtr
-PreprocessorLexer::getFileEntry() const {
+OptionalFileEntryRef PreprocessorLexer::getFileEntry() const {
   return PP->getSourceManager().getFileEntryRefForID(getFileID());
 }
diff --git a/clang/lib/Serialization/ASTReader.cpp b/clang/lib/Serialization/ASTReader.cpp
index 49f25d6648c8..ac9bddb5c36b 100644
--- a/clang/lib/Serialization/ASTReader.cpp
+++ b/clang/lib/Serialization/ASTReader.cpp
@@ -2531,8 +2531,7 @@ InputFile ASTReader::getInputFile(ModuleFile &F, unsigned ID, bool Complain) {
     Overridden = false;
   }
 
-  OptionalFileEntryRefDegradesToFileEntryPtr File = OptionalFileEntryRef(
-      expectedToOptional(FileMgr.getFileRef(Filename, /*OpenFile=*/false)));
+  auto File = FileMgr.getOptionalFileRef(Filename, /*OpenFile=*/false);
 
   // For an overridden file, create a virtual file with the stored
   // size/timestamp.
@@ -2559,7 +2558,8 @@ InputFile ASTReader::getInputFile(ModuleFile &F, unsigned ID, bool Complain) {
   // PCH.
   SourceManager &SM = getSourceManager();
   // FIXME: Reject if the overrides are different.
-  if ((!Overridden && !Transient) && !SkipChecks && SM.isFileOverridden(File)) {
+  if ((!Overridden && !Transient) && !SkipChecks &&
+      SM.isFileOverridden(*File)) {
     if (Complain)
       Error(diag::err_fe_pch_file_overridden, Filename);
 
diff --git a/clang/lib/Serialization/ASTWriter.cpp b/clang/lib/Serialization/ASTWriter.cpp
index 38e8b8ccbe05..91eb2af8f8ad 100644
--- a/clang/lib/Serialization/ASTWriter.cpp
+++ b/clang/lib/Serialization/ASTWriter.cpp
@@ -2182,8 +2182,8 @@ void ASTWriter::WriteSourceManagerBlock(SourceManager &SourceMgr,
                "Writing to AST an overridden file is not supported");
 
         // The source location entry is a file. Emit input file ID.
-        assert(InputFileIDs[Content->OrigEntry] != 0 && "Missed file entry");
-        Record.push_back(InputFileIDs[Content->OrigEntry]);
+        assert(InputFileIDs[*Content->OrigEntry] != 0 && "Missed file entry");
+        Record.push_back(InputFileIDs[*Content->OrigEntry]);
 
         Record.push_back(getAdjustedNumCreatedFIDs(FID));
 
@@ -4695,7 +4695,7 @@ void ASTWriter::collectNonAffectingInputFiles() {
 
     if (!isModuleMap(File.getFileCharacteristic()) ||
         AffectingModuleMaps.empty() ||
-        AffectingModuleMaps.find(Cache->OrigEntry) != AffectingModuleMaps.end())
+        llvm::is_contained(AffectingModuleMaps, *Cache->OrigEntry))
       continue;
 
     IsSLocAffecting[I] = false;
diff --git a/clang/lib/Serialization/ModuleManager.cpp b/clang/lib/Serialization/ModuleManager.cpp
index d1ded6cd8ee2..51b642941296 100644
--- a/clang/lib/Serialization/ModuleManager.cpp
+++ b/clang/lib/Serialization/ModuleManager.cpp
@@ -52,8 +52,8 @@ ModuleFile *ModuleManager::lookupByFileName(StringRef Name) const {
 
 ModuleFile *ModuleManager::lookupByModuleName(StringRef Name) const {
   if (const Module *Mod = HeaderSearchInfo.getModuleMap().findModule(Name))
-    if (const FileEntry *File = Mod->getASTFile())
-      return lookup(File);
+    if (OptionalFileEntryRef File = Mod->getASTFile())
+      return lookup(*File);
 
   return nullptr;
 }
diff --git a/clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp b/clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
index 1058ddb8254c..f65da413bb87 100644
--- a/clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
+++ b/clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
@@ -521,7 +521,7 @@ ModuleDepCollectorPP::handleTopLevelModule(const Module *M) {
 
   serialization::ModuleFile *MF =
       MDC.ScanInstance.getASTReader()->getModuleManager().lookup(
-          M->getASTFile());
+          *M->getASTFile());
   MDC.ScanInstance.getASTReader()->visitInputFileInfos(
       *MF, /*IncludeSystem=*/true,
       [&](const serialization::InputFileInfo &IFI, bool IsSystem) {
diff --git a/clang/tools/libclang/CXIndexDataConsumer.cpp b/clang/tools/libclang/CXIndexDataConsumer.cpp
index 5ca484fbc8cd..c1022263a512 100644
--- a/clang/tools/libclang/CXIndexDataConsumer.cpp
+++ b/clang/tools/libclang/CXIndexDataConsumer.cpp
@@ -1074,8 +1074,8 @@ CXIndexDataConsumer::getClientContainerForDC(const DeclContext *DC) const {
   return DC ? ContainerMap.lookup(DC) : nullptr;
 }
 
-CXIdxClientFile CXIndexDataConsumer::getIndexFile(const FileEntry *File) {
-  return File ? FileMap.lookup(File) : nullptr;
+CXIdxClientFile CXIndexDataConsumer::getIndexFile(OptionalFileEntryRef File) {
+  return File ? FileMap.lookup(*File) : nullptr;
 }
 
 CXIdxLoc CXIndexDataConsumer::getIndexLoc(SourceLocation Loc) const {
@@ -1104,8 +1104,8 @@ void CXIndexDataConsumer::translateLoc(SourceLocation Loc,
 
   if (FID.isInvalid())
     return;
-  
-  OptionalFileEntryRefDegradesToFileEntryPtr FE = SM.getFileEntryRefForID(FID);
+
+  OptionalFileEntryRef FE = SM.getFileEntryRefForID(FID);
   if (indexFile)
     *indexFile = getIndexFile(FE);
   if (file)
diff --git a/clang/tools/libclang/CXIndexDataConsumer.h b/clang/tools/libclang/CXIndexDataConsumer.h
index afa2239ed653..54a3add3a9c8 100644
--- a/clang/tools/libclang/CXIndexDataConsumer.h
+++ b/clang/tools/libclang/CXIndexDataConsumer.h
@@ -460,8 +460,8 @@ private:
 
   const DeclContext *getEntityContainer(const Decl *D) const;
 
-  CXIdxClientFile getIndexFile(const FileEntry *File);
-  
+  CXIdxClientFile getIndexFile(OptionalFileEntryRef File);
+
   CXIdxLoc getIndexLoc(SourceLocation Loc) const;
 
   void getEntityInfo(const NamedDecl *D,
diff --git a/clang/unittests/Basic/FileEntryTest.cpp b/clang/unittests/Basic/FileEntryTest.cpp
index dcd196417da7..f8a0b4a4edcd 100644
--- a/clang/unittests/Basic/FileEntryTest.cpp
+++ b/clang/unittests/Basic/FileEntryTest.cpp
@@ -92,24 +92,6 @@ TEST(FileEntryTest, FileEntryRef) {
   EXPECT_EQ(CE1, &R1.getFileEntry());
 }
 
-TEST(FileEntryTest, OptionalFileEntryRefDegradesToFileEntryPtr) {
-  FileEntryTestHelper Refs;
-  OptionalFileEntryRefDegradesToFileEntryPtr M0;
-  OptionalFileEntryRefDegradesToFileEntryPtr M1 = Refs.addFile("1");
-  OptionalFileEntryRefDegradesToFileEntryPtr M2 = Refs.addFile("2");
-  OptionalFileEntryRefDegradesToFileEntryPtr M0Also = std::nullopt;
-  OptionalFileEntryRefDegradesToFileEntryPtr M1Also =
-      Refs.addFileAlias("1-also", *M1);
-
-  EXPECT_EQ(M0, M0Also);
-  EXPECT_EQ(StringRef("1"), M1->getName());
-  EXPECT_EQ(StringRef("2"), M2->getName());
-  EXPECT_EQ(StringRef("1-also"), M1Also->getName());
-
-  const FileEntry *CE1 = M1;
-  EXPECT_EQ(CE1, &M1->getFileEntry());
-}
-
 TEST(FileEntryTest, equals) {
   FileEntryTestHelper Refs;
   FileEntryRef R1 = Refs.addFile("1");
@@ -126,13 +108,6 @@ TEST(FileEntryTest, equals) {
   EXPECT_NE(R1, R2);
   EXPECT_EQ(R1, R1Redirect);
   EXPECT_EQ(R1, R1Redirect2);
-
-  OptionalFileEntryRefDegradesToFileEntryPtr M1 = R1;
-
-  EXPECT_EQ(M1, &R1.getFileEntry());
-  EXPECT_EQ(&R1.getFileEntry(), M1);
-  EXPECT_NE(M1, &R2.getFileEntry());
-  EXPECT_NE(&R2.getFileEntry(), M1);
 }
 
 TEST(FileEntryTest, isSameRef) {
-- 
GitLab


From cb92511c4d967df758819a21a7d5cf83e5ce65ae Mon Sep 17 00:00:00 2001
From: Jan Svoboda <jan_svoboda@apple.com>
Date: Sat, 9 Dec 2023 03:22:53 +0100
Subject: [PATCH 010/349] [clang] NFC: Remove
 `OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr` (#74900)

---
 .../clang-tidy/misc/IncludeCleanerCheck.cpp   |  2 +-
 clang-tools-extra/clangd/IncludeCleaner.cpp   |  8 +-
 .../include-cleaner/lib/Analysis.cpp          |  6 +-
 clang/include/clang/Basic/DirectoryEntry.h    | 74 -------------------
 clang/include/clang/Basic/Module.h            |  2 +-
 clang/include/clang/Lex/ModuleMap.h           | 14 ++--
 clang/lib/Serialization/ASTReader.cpp         |  2 +-
 7 files changed, 15 insertions(+), 93 deletions(-)

diff --git a/clang-tools-extra/clang-tidy/misc/IncludeCleanerCheck.cpp b/clang-tools-extra/clang-tidy/misc/IncludeCleanerCheck.cpp
index e336ba1ee1fa..5ae6caedb7f4 100644
--- a/clang-tools-extra/clang-tidy/misc/IncludeCleanerCheck.cpp
+++ b/clang-tools-extra/clang-tidy/misc/IncludeCleanerCheck.cpp
@@ -124,7 +124,7 @@ void IncludeCleanerCheck::check(const MatchFinder::MatchResult &Result) {
     MainFileDecls.push_back(D);
   }
   llvm::DenseSet<include_cleaner::Symbol> SeenSymbols;
-  const DirectoryEntry *ResourceDir =
+  OptionalDirectoryEntryRef ResourceDir =
       PP->getHeaderSearchInfo().getModuleMap().getBuiltinDir();
   // FIXME: Find a way to have less code duplication between include-cleaner
   // analysis implementation and the below code.
diff --git a/clang-tools-extra/clangd/IncludeCleaner.cpp b/clang-tools-extra/clangd/IncludeCleaner.cpp
index b0a3c290bad6..dda7c9f581f6 100644
--- a/clang-tools-extra/clangd/IncludeCleaner.cpp
+++ b/clang-tools-extra/clangd/IncludeCleaner.cpp
@@ -397,10 +397,10 @@ IncludeCleanerFindings computeIncludeCleanerFindings(ParsedAST &AST) {
   std::vector<MissingIncludeDiagInfo> MissingIncludes;
   llvm::DenseSet<IncludeStructure::HeaderID> Used;
   trace::Span Tracer("include_cleaner::walkUsed");
-  const DirectoryEntry *ResourceDir = AST.getPreprocessor()
-                                .getHeaderSearchInfo()
-                                .getModuleMap()
-                                .getBuiltinDir();
+  OptionalDirectoryEntryRef ResourceDir = AST.getPreprocessor()
+                                              .getHeaderSearchInfo()
+                                              .getModuleMap()
+                                              .getBuiltinDir();
   include_cleaner::walkUsed(
       AST.getLocalTopLevelDecls(), /*MacroRefs=*/Macros,
       AST.getPragmaIncludes().get(), AST.getPreprocessor(),
diff --git a/clang-tools-extra/include-cleaner/lib/Analysis.cpp b/clang-tools-extra/include-cleaner/lib/Analysis.cpp
index 09365c36f9f2..450c4c796c14 100644
--- a/clang-tools-extra/include-cleaner/lib/Analysis.cpp
+++ b/clang-tools-extra/include-cleaner/lib/Analysis.cpp
@@ -87,7 +87,7 @@ analyze(llvm::ArrayRef<Decl *> ASTRoots,
   llvm::StringSet<> Missing;
   if (!HeaderFilter)
     HeaderFilter = [](llvm::StringRef) { return false; };
-  const DirectoryEntry *ResourceDir =
+  OptionalDirectoryEntryRef ResourceDir =
       PP.getHeaderSearchInfo().getModuleMap().getBuiltinDir();
   walkUsed(ASTRoots, MacroRefs, PI, PP,
            [&](const SymbolReference &Ref, llvm::ArrayRef<Header> Providers) {
@@ -95,7 +95,7 @@ analyze(llvm::ArrayRef<Decl *> ASTRoots,
              for (const Header &H : Providers) {
                if (H.kind() == Header::Physical &&
                    (H.physical() == MainFile ||
-                    H.physical().getDir() == ResourceDir)) {
+                    (ResourceDir && H.physical().getDir() == *ResourceDir))) {
                  Satisfied = true;
                }
                for (const Include *I : Inc.match(H)) {
@@ -114,7 +114,7 @@ analyze(llvm::ArrayRef<Decl *> ASTRoots,
   for (const Include &I : Inc.all()) {
     if (Used.contains(&I) || !I.Resolved ||
         HeaderFilter(I.Resolved->getFileEntry().tryGetRealPathName()) ||
-        I.Resolved->getFileEntry().getDir() == ResourceDir)
+        (ResourceDir && I.Resolved->getFileEntry().getDir() == *ResourceDir))
       continue;
     if (PI) {
       if (PI->shouldKeep(*I.Resolved))
diff --git a/clang/include/clang/Basic/DirectoryEntry.h b/clang/include/clang/Basic/DirectoryEntry.h
index 5d083e68facd..906c2e9af23b 100644
--- a/clang/include/clang/Basic/DirectoryEntry.h
+++ b/clang/include/clang/Basic/DirectoryEntry.h
@@ -245,78 +245,4 @@ template <> struct DenseMapInfo<clang::DirectoryEntryRef> {
 
 } // end namespace llvm
 
-namespace clang {
-
-/// Wrapper around OptionalDirectoryEntryRef that degrades to 'const
-/// DirectoryEntry*', facilitating incremental patches to propagate
-/// DirectoryEntryRef.
-///
-/// This class can be used as return value or field where it's convenient for
-/// an OptionalDirectoryEntryRef to degrade to a 'const DirectoryEntry*'. The
-/// purpose is to avoid code churn due to dances like the following:
-/// \code
-/// // Old code.
-/// lvalue = rvalue;
-///
-/// // Temporary code from an incremental patch.
-/// OptionalDirectoryEntryRef MaybeF = rvalue;
-/// lvalue = MaybeF ? &MaybeF.getDirectoryEntry() : nullptr;
-///
-/// // Final code.
-/// lvalue = rvalue;
-/// \endcode
-///
-/// FIXME: Once DirectoryEntryRef is "everywhere" and DirectoryEntry::LastRef
-/// and DirectoryEntry::getName have been deleted, delete this class and
-/// replace instances with OptionalDirectoryEntryRef.
-class OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr
-    : public OptionalDirectoryEntryRef {
-public:
-  OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr() = default;
-  OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr(
-      OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr &&) = default;
-  OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr(
-      const OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr &) = default;
-  OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr &
-  operator=(OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr &&) = default;
-  OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr &
-  operator=(const OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr &) = default;
-
-  OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr(std::nullopt_t) {}
-  OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr(DirectoryEntryRef Ref)
-      : OptionalDirectoryEntryRef(Ref) {}
-  OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr(
-      OptionalDirectoryEntryRef MaybeRef)
-      : OptionalDirectoryEntryRef(MaybeRef) {}
-
-  OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr &
-  operator=(std::nullopt_t) {
-    OptionalDirectoryEntryRef::operator=(std::nullopt);
-    return *this;
-  }
-  OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr &operator=(DirectoryEntryRef Ref) {
-    OptionalDirectoryEntryRef::operator=(Ref);
-    return *this;
-  }
-  OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr &
-  operator=(OptionalDirectoryEntryRef MaybeRef) {
-    OptionalDirectoryEntryRef::operator=(MaybeRef);
-    return *this;
-  }
-
-  /// Degrade to 'const DirectoryEntry *' to allow  DirectoryEntry::LastRef and
-  /// DirectoryEntry::getName have been deleted, delete this class and replace
-  /// instances with OptionalDirectoryEntryRef
-  operator const DirectoryEntry *() const {
-    return has_value() ? &(*this)->getDirEntry() : nullptr;
-  }
-};
-
-static_assert(std::is_trivially_copyable<
-                  OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr>::value,
-              "OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr should be "
-              "trivially copyable");
-
-} // end namespace clang
-
 #endif // LLVM_CLANG_BASIC_DIRECTORYENTRY_H
diff --git a/clang/include/clang/Basic/Module.h b/clang/include/clang/Basic/Module.h
index 23f263c89511..62786e3ac865 100644
--- a/clang/include/clang/Basic/Module.h
+++ b/clang/include/clang/Basic/Module.h
@@ -156,7 +156,7 @@ public:
   /// The build directory of this module. This is the directory in
   /// which the module is notionally built, and relative to which its headers
   /// are found.
-  OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr Directory;
+  OptionalDirectoryEntryRef Directory;
 
   /// The presumed file name for the module map defining this module.
   /// Only non-empty when building from preprocessed source.
diff --git a/clang/include/clang/Lex/ModuleMap.h b/clang/include/clang/Lex/ModuleMap.h
index 32e7e8f899e5..867cb6eab42f 100644
--- a/clang/include/clang/Lex/ModuleMap.h
+++ b/clang/include/clang/Lex/ModuleMap.h
@@ -82,7 +82,7 @@ class ModuleMap {
 
   /// The directory used for Clang-supplied, builtin include headers,
   /// such as "stdint.h".
-  OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr BuiltinIncludeDir;
+  OptionalDirectoryEntryRef BuiltinIncludeDir;
 
   /// Language options used to parse the module map itself.
   ///
@@ -408,16 +408,12 @@ public:
   /// Set the target information.
   void setTarget(const TargetInfo &Target);
 
-  /// Set the directory that contains Clang-supplied include
-  /// files, such as our stdarg.h or tgmath.h.
-  void setBuiltinIncludeDir(DirectoryEntryRef Dir) {
-    BuiltinIncludeDir = Dir;
-  }
+  /// Set the directory that contains Clang-supplied include files, such as our
+  /// stdarg.h or tgmath.h.
+  void setBuiltinIncludeDir(DirectoryEntryRef Dir) { BuiltinIncludeDir = Dir; }
 
   /// Get the directory that contains Clang-supplied include files.
-  OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr getBuiltinDir() const {
-    return BuiltinIncludeDir;
-  }
+  OptionalDirectoryEntryRef getBuiltinDir() const { return BuiltinIncludeDir; }
 
   /// Is this a compiler builtin header?
   bool isBuiltinHeader(FileEntryRef File);
diff --git a/clang/lib/Serialization/ASTReader.cpp b/clang/lib/Serialization/ASTReader.cpp
index ac9bddb5c36b..5b51ac40000d 100644
--- a/clang/lib/Serialization/ASTReader.cpp
+++ b/clang/lib/Serialization/ASTReader.cpp
@@ -3152,7 +3152,7 @@ ASTReader::ReadControlBlock(ModuleFile &F,
         if (!bool(PP.getPreprocessorOpts().DisablePCHOrModuleValidation &
                   DisableValidationForModuleKind::Module) &&
             F.Kind != MK_ExplicitModule && F.Kind != MK_PrebuiltModule) {
-          auto BuildDir = PP.getFileManager().getDirectory(Blob);
+          auto BuildDir = PP.getFileManager().getOptionalDirectoryRef(Blob);
           if (!BuildDir || *BuildDir != M->Directory) {
             if (!canRecoverFromOutOfDate(F.FileName, ClientLoadCapabilities))
               Diag(diag::err_imported_module_relocated)
-- 
GitLab


From b88b480640f173582ffbfd2faae690f2bc895d14 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@sifive.com>
Date: Fri, 8 Dec 2023 18:43:08 -0800
Subject: [PATCH 011/349] [RISCV] Remove Type::isRVVType() and replace with
 isRVVSizelessBuiltinType(). NFC

These both do the same thing, but some profiling on a
Releast+Asserts build suggests isRVVSizelessBuiltinType() is the
more efficient version so lets keep that one.
---
 clang/include/clang/AST/Type.h             | 10 ----------
 clang/lib/Analysis/UninitializedValues.cpp |  2 +-
 clang/lib/Sema/Sema.cpp                    |  2 +-
 clang/lib/Sema/SemaChecking.cpp            |  2 +-
 clang/lib/Sema/SemaDecl.cpp                |  2 +-
 5 files changed, 4 insertions(+), 14 deletions(-)

diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h
index 6c147eb8f640..b14184afe584 100644
--- a/clang/include/clang/AST/Type.h
+++ b/clang/include/clang/AST/Type.h
@@ -2384,8 +2384,6 @@ public:
 
   bool isRVVType(unsigned ElementCount) const;
 
-  bool isRVVType() const;
-
   bool isRVVType(unsigned Bitwidth, bool IsFloat, bool IsBFloat = false) const;
 
   /// Return the implicit lifetime for this type, which must not be dependent.
@@ -7284,14 +7282,6 @@ inline bool Type::isOpenCLSpecificType() const {
          isQueueT() || isReserveIDT() || isPipeType() || isOCLExtOpaqueType();
 }
 
-inline bool Type::isRVVType() const {
-#define RVV_TYPE(Name, Id, SingletonId) \
-  isSpecificBuiltinType(BuiltinType::Id) ||
-  return
-#include "clang/Basic/RISCVVTypes.def"
-    false; // end of boolean or operation.
-}
-
 inline bool Type::isRVVType(unsigned ElementCount) const {
   bool Ret = false;
 #define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned,   \
diff --git a/clang/lib/Analysis/UninitializedValues.cpp b/clang/lib/Analysis/UninitializedValues.cpp
index b796f7674cc1..e9111ded64eb 100644
--- a/clang/lib/Analysis/UninitializedValues.cpp
+++ b/clang/lib/Analysis/UninitializedValues.cpp
@@ -64,7 +64,7 @@ static bool isTrackedVar(const VarDecl *vd, const DeclContext *dc) {
     QualType ty = vd->getType();
     if (const auto *RD = ty->getAsRecordDecl())
       return recordIsNotEmpty(RD);
-    return ty->isScalarType() || ty->isVectorType() || ty->isRVVType();
+    return ty->isScalarType() || ty->isVectorType() || ty->isRVVSizelessBuiltinType();
   }
   return false;
 }
diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp
index 2c7ecf4610de..22929aa6316d 100644
--- a/clang/lib/Sema/Sema.cpp
+++ b/clang/lib/Sema/Sema.cpp
@@ -2077,7 +2077,7 @@ void Sema::checkTypeSupport(QualType Ty, SourceLocation Loc, ValueDecl *D) {
         targetDiag(D->getLocation(), diag::note_defined_here, FD) << D;
     }
 
-    if (TI.hasRISCVVTypes() && Ty->isRVVType())
+    if (TI.hasRISCVVTypes() && Ty->isRVVSizelessBuiltinType())
       checkRVVTypeSupport(Ty, Loc, D);
 
     // Don't allow SVE types in functions without a SVE target.
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index a729cff53fc1..5c9734618447 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5983,7 +5983,7 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
     ValType = ValType.getUnqualifiedType();
     if (!ValType->isIntegerType() && !ValType->isAnyPointerType() &&
         !ValType->isBlockPointerType() && !ValType->isFloatingType() &&
-        !ValType->isVectorType() && !ValType->isRVVType()) {
+        !ValType->isVectorType() && !ValType->isRVVSizelessBuiltinType()) {
       Diag(DRE->getBeginLoc(),
            diag::err_nontemporal_builtin_must_be_pointer_intfltptr_or_vector)
           << PointerArg->getType() << PointerArg->getSourceRange();
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index e3c122de39df..7650589608c5 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -8914,7 +8914,7 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
     }
   }
 
-  if (T->isRVVType())
+  if (T->isRVVSizelessBuiltinType())
     checkRVVTypeSupport(T, NewVD->getLocation(), cast<Decl>(CurContext));
 }
 
-- 
GitLab


From ab20f23e7e65c7b19469e7d6e438ea14e22b9fff Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu@google.com>
Date: Fri, 8 Dec 2023 22:07:29 -0800
Subject: [PATCH 012/349] [DebugInfo] Use llvm::to_underlying (NFC)

---
 llvm/include/llvm/DebugInfo/CodeView/CodeView.h     | 11 ++++++-----
 llvm/include/llvm/DebugInfo/PDB/Native/FormatUtil.h |  4 ++--
 llvm/lib/DebugInfo/PDB/Native/FormatUtil.cpp        |  5 ++---
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/llvm/include/llvm/DebugInfo/CodeView/CodeView.h b/llvm/include/llvm/DebugInfo/CodeView/CodeView.h
index 62e559e2ceba..0bfd06e05bd8 100644
--- a/llvm/include/llvm/DebugInfo/CodeView/CodeView.h
+++ b/llvm/include/llvm/DebugInfo/CodeView/CodeView.h
@@ -16,6 +16,7 @@
 #include <cinttypes>
 #include <type_traits>
 
+#include "llvm/ADT/STLForwardCompat.h"
 #include "llvm/Support/Endian.h"
 
 namespace llvm {
@@ -51,15 +52,15 @@ enum SymbolKind : uint16_t {
 
 #define CV_DEFINE_ENUM_CLASS_FLAGS_OPERATORS(Class)                            \
   inline Class operator|(Class a, Class b) {                                   \
-    return static_cast<Class>(static_cast<std::underlying_type_t<Class>>(a) |  \
-                              static_cast<std::underlying_type_t<Class>>(b));  \
+    return static_cast<Class>(llvm::to_underlying(a) |                         \
+                              llvm::to_underlying(b));                         \
   }                                                                            \
   inline Class operator&(Class a, Class b) {                                   \
-    return static_cast<Class>(static_cast<std::underlying_type_t<Class>>(a) &  \
-                              static_cast<std::underlying_type_t<Class>>(b));  \
+    return static_cast<Class>(llvm::to_underlying(a) &                         \
+                              llvm::to_underlying(b));                         \
   }                                                                            \
   inline Class operator~(Class a) {                                            \
-    return static_cast<Class>(~static_cast<std::underlying_type_t<Class>>(a)); \
+    return static_cast<Class>(~llvm::to_underlying(a));                        \
   }                                                                            \
   inline Class &operator|=(Class &a, Class b) {                                \
     a = a | b;                                                                 \
diff --git a/llvm/include/llvm/DebugInfo/PDB/Native/FormatUtil.h b/llvm/include/llvm/DebugInfo/PDB/Native/FormatUtil.h
index 01de8b49dd78..0adbd25cb369 100644
--- a/llvm/include/llvm/DebugInfo/PDB/Native/FormatUtil.h
+++ b/llvm/include/llvm/DebugInfo/PDB/Native/FormatUtil.h
@@ -10,6 +10,7 @@
 #define LLVM_DEBUGINFO_PDB_NATIVE_FORMATUTIL_H
 
 #include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/STLForwardCompat.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/DebugInfo/CodeView/CodeView.h"
 #include "llvm/Support/Endian.h"
@@ -34,8 +35,7 @@ namespace pdb {
     return Ret;
 
 template <typename T> std::string formatUnknownEnum(T Value) {
-  return formatv("unknown ({0})", static_cast<std::underlying_type_t<T>>(Value))
-      .str();
+  return formatv("unknown ({0})", llvm::to_underlying(Value)).str();
 }
 
 std::string formatSegmentOffset(uint16_t Segment, uint32_t Offset);
diff --git a/llvm/lib/DebugInfo/PDB/Native/FormatUtil.cpp b/llvm/lib/DebugInfo/PDB/Native/FormatUtil.cpp
index 9c05d585831a..c5999bffc021 100644
--- a/llvm/lib/DebugInfo/PDB/Native/FormatUtil.cpp
+++ b/llvm/lib/DebugInfo/PDB/Native/FormatUtil.cpp
@@ -9,6 +9,7 @@
 #include "llvm/DebugInfo/PDB/Native/FormatUtil.h"
 
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/STLForwardCompat.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/BinaryFormat/COFF.h"
 #include "llvm/DebugInfo/CodeView/CodeView.h"
@@ -119,9 +120,7 @@ std::string llvm::pdb::formatTypeLeafKind(TypeLeafKind K) {
     return #EnumName;
 #include "llvm/DebugInfo/CodeView/CodeViewTypes.def"
   default:
-    return formatv("UNKNOWN RECORD ({0:X})",
-                   static_cast<std::underlying_type_t<TypeLeafKind>>(K))
-        .str();
+    return formatv("UNKNOWN RECORD ({0:X})", llvm::to_underlying(K)).str();
   }
 }
 
-- 
GitLab


From 9e3b1f7cfc1522b7a4863a25a3c6ec8d93c227e1 Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu@google.com>
Date: Fri, 8 Dec 2023 22:32:43 -0800
Subject: [PATCH 013/349] [Bitcode] Remove an unnecessary include (NFC)

---
 llvm/lib/Bitcode/Reader/ValueList.cpp | 1 -
 1 file changed, 1 deletion(-)

diff --git a/llvm/lib/Bitcode/Reader/ValueList.cpp b/llvm/lib/Bitcode/Reader/ValueList.cpp
index b9dbf904c89e..f5568a923b11 100644
--- a/llvm/lib/Bitcode/Reader/ValueList.cpp
+++ b/llvm/lib/Bitcode/Reader/ValueList.cpp
@@ -7,7 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 #include "ValueList.h"
-#include "llvm/ADT/SmallVector.h"
 #include "llvm/IR/Argument.h"
 #include "llvm/IR/Constant.h"
 #include "llvm/IR/Constants.h"
-- 
GitLab


From 74f6b2d0d747cd49864b1f6163d293c9524ee180 Mon Sep 17 00:00:00 2001
From: Brad Smith <brad@comstyle.com>
Date: Sat, 9 Dec 2023 02:10:14 -0500
Subject: [PATCH 014/349] [CMake] Make ELF library handling path default for
 libLLVM (#74698)

Invert the logic and choose the ELF path by default as a fallback. Move
check for Darwin to the top.
---
 llvm/tools/llvm-shlib/CMakeLists.txt | 15 +++------------
 1 file changed, 3 insertions(+), 12 deletions(-)

diff --git a/llvm/tools/llvm-shlib/CMakeLists.txt b/llvm/tools/llvm-shlib/CMakeLists.txt
index 5079316533d3..64d6f631ffad 100644
--- a/llvm/tools/llvm-shlib/CMakeLists.txt
+++ b/llvm/tools/llvm-shlib/CMakeLists.txt
@@ -36,16 +36,9 @@ if(LLVM_BUILD_LLVM_DYLIB)
   add_llvm_library(LLVM SHARED DISABLE_LLVM_LINK_LLVM_DYLIB SONAME ${INSTALL_WITH_TOOLCHAIN} ${SOURCES})
 
   list(REMOVE_DUPLICATES LIB_NAMES)
-  if((MINGW) OR (HAIKU)
-     OR ("${CMAKE_SYSTEM_NAME}" STREQUAL "Linux")
-     OR ("${CMAKE_SYSTEM_NAME}" STREQUAL "GNU")
-     OR ("${CMAKE_SYSTEM_NAME}" STREQUAL "FreeBSD")
-     OR ("${CMAKE_SYSTEM_NAME}" STREQUAL "NetBSD")
-     OR ("${CMAKE_SYSTEM_NAME}" STREQUAL "OpenBSD")
-     OR ("${CMAKE_SYSTEM_NAME}" STREQUAL "DragonFly")
-     OR ("${CMAKE_SYSTEM_NAME}" STREQUAL "Fuchsia")
-     OR ("${CMAKE_SYSTEM_NAME}" STREQUAL "Android")
-     OR ("${CMAKE_SYSTEM_NAME}" STREQUAL "SunOS")) # FIXME: It should be "GNU ld for elf"
+  if("${CMAKE_SYSTEM_NAME}" STREQUAL "Darwin")
+    set(LIB_NAMES -Wl,-all_load ${LIB_NAMES})
+  else()
     configure_file(
     ${CMAKE_CURRENT_SOURCE_DIR}/simple_version_script.map.in
     ${LLVM_LIBRARY_DIR}/tools/llvm-shlib/simple_version_script.map)
@@ -63,8 +56,6 @@ if(LLVM_BUILD_LLVM_DYLIB)
       # inside and outside libLLVM.so.
       target_link_options(LLVM PRIVATE LINKER:-Bsymbolic-functions)
     endif()
-  elseif("${CMAKE_SYSTEM_NAME}" STREQUAL "Darwin")
-    set(LIB_NAMES -Wl,-all_load ${LIB_NAMES})
   endif()
 
   target_link_libraries(LLVM PRIVATE ${LIB_NAMES})
-- 
GitLab


From 57eb2054e308da7fb394375dedf8d7b627d1b528 Mon Sep 17 00:00:00 2001
From: Vlad Serebrennikov <serebrennikov.vladislav@gmail.com>
Date: Sat, 9 Dec 2023 11:09:07 +0300
Subject: [PATCH 015/349] [clang][NFC] Fill in historical data on when C++ DRs
 2000-2799 were fixed

---
 clang/test/CXX/drs/dr2390.cpp |  2 +-
 clang/test/CXX/drs/dr2406.cpp |  2 +-
 clang/test/CXX/drs/dr26xx.cpp |  6 +++---
 clang/www/cxx_dr_status.html  | 10 +++++-----
 4 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/clang/test/CXX/drs/dr2390.cpp b/clang/test/CXX/drs/dr2390.cpp
index d8ab1e9a1b38..3931365b568c 100644
--- a/clang/test/CXX/drs/dr2390.cpp
+++ b/clang/test/CXX/drs/dr2390.cpp
@@ -1,6 +1,6 @@
 // RUN: %clang_cc1 -E -P %s -o - | FileCheck %s
 
-// dr2390: yes
+// dr2390: 14
 
 namespace PR48462 {
 // Test that macro expansion of the builtin argument works.
diff --git a/clang/test/CXX/drs/dr2406.cpp b/clang/test/CXX/drs/dr2406.cpp
index 7ea0870fb70b..0ab198e6f149 100644
--- a/clang/test/CXX/drs/dr2406.cpp
+++ b/clang/test/CXX/drs/dr2406.cpp
@@ -1,6 +1,6 @@
 // RUN: %clang_cc1 -x c++ %s  -verify
 
-// dr2406: yes
+// dr2406: 5
 
 void fallthrough(int n) {
   void g(), h(), i();
diff --git a/clang/test/CXX/drs/dr26xx.cpp b/clang/test/CXX/drs/dr26xx.cpp
index 8517cd5872b1..1d702e66bf8c 100644
--- a/clang/test/CXX/drs/dr26xx.cpp
+++ b/clang/test/CXX/drs/dr26xx.cpp
@@ -2,7 +2,7 @@
 // RUN: %clang_cc1 -std=c++2b -triple x86_64-unknown-unknown %s -verify
 
 
-namespace dr2621 { // dr2621: yes
+namespace dr2621 { // dr2621: 16
 enum class E { a };
 namespace One {
 using E_t = E;
@@ -101,7 +101,7 @@ int y = dr2640_a\N{LOTUS}); // expected-error {{character <U+1FAB7> not allowed
 
   // dr2642: na
 
-namespace dr2644 { // dr2644: yes
+namespace dr2644 { // dr2644: 8
 
 auto z = [a = 42](int a) { // expected-error {{a lambda parameter cannot shadow an explicitly captured entity}} \
                            // expected-note {{variable 'a' is explicitly captured here}}
@@ -111,7 +111,7 @@ auto z = [a = 42](int a) { // expected-error {{a lambda parameter cannot shadow
 }
 
 #if __cplusplus >= 202302L
-namespace dr2650 { // dr2650: yes
+namespace dr2650 { // dr2650: 17
 template <class T, T> struct S {};
 template <class T> int f(S<T, T{}>*); // expected-note {{type 'X' of non-type template parameter is not a structural type}}
 class X {
diff --git a/clang/www/cxx_dr_status.html b/clang/www/cxx_dr_status.html
index 3f519ff06742..d09cf616899a 100755
--- a/clang/www/cxx_dr_status.html
+++ b/clang/www/cxx_dr_status.html
@@ -14147,7 +14147,7 @@ and <I>POD class</I></td>
     <td><a href="https://cplusplus.github.io/CWG/issues/2390.html">2390</a></td>
     <td>CD5</td>
     <td>Is the argument of <TT>__has_cpp_attribute</TT> macro-expanded?</td>
-    <td class="full" align="center">Yes</td>
+    <td class="full" align="center">Clang 14</td>
   </tr>
   <tr id="2391">
     <td><a href="https://cplusplus.github.io/CWG/issues/2391.html">2391</a></td>
@@ -14243,7 +14243,7 @@ and <I>POD class</I></td>
     <td><a href="https://cplusplus.github.io/CWG/issues/2406.html">2406</a></td>
     <td>CD5</td>
     <td><TT>[[fallthrough]]</TT> attribute and iteration statements</td>
-    <td class="full" align="center">Yes</td>
+    <td class="full" align="center">Clang 5</td>
   </tr>
   <tr id="2407">
     <td><a href="https://cplusplus.github.io/CWG/issues/2407.html">2407</a></td>
@@ -15533,7 +15533,7 @@ and <I>POD class</I></td>
     <td><a href="https://cplusplus.github.io/CWG/issues/2621.html">2621</a></td>
     <td>C++23</td>
     <td>Kind of lookup for <TT>using enum</TT> declarations</td>
-    <td class="full" align="center">Yes</td>
+    <td class="full" align="center">Clang 16</td>
   </tr>
   <tr id="2622">
     <td><a href="https://cplusplus.github.io/CWG/issues/2622.html">2622</a></td>
@@ -15671,7 +15671,7 @@ and <I>POD class</I></td>
     <td><a href="https://cplusplus.github.io/CWG/issues/2644.html">2644</a></td>
     <td>C++23</td>
     <td>Incorrect comment in example</td>
-    <td class="full" align="center">Yes</td>
+    <td class="full" align="center">Clang 8</td>
   </tr>
   <tr id="2645">
     <td><a href="https://cplusplus.github.io/CWG/issues/2645.html">2645</a></td>
@@ -15707,7 +15707,7 @@ and <I>POD class</I></td>
     <td><a href="https://cplusplus.github.io/CWG/issues/2650.html">2650</a></td>
     <td>C++23</td>
     <td>Incorrect example for ill-formed non-type template arguments</td>
-    <td class="full" align="center">Yes</td>
+    <td class="full" align="center">Clang 17</td>
   </tr>
   <tr id="2651">
     <td><a href="https://cplusplus.github.io/CWG/issues/2651.html">2651</a></td>
-- 
GitLab


From 312cb34da6a5529fbfaa1be62f1aa9bbb26ce506 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333@gmail.com>
Date: Sat, 9 Dec 2023 16:45:48 +0800
Subject: [PATCH 016/349] [Reassociate] Preserve NUW flags after expr tree
 rewriting (#72360)

Alive2: https://alive2.llvm.org/ce/z/38KiC_
---
 .../llvm/Transforms/Scalar/Reassociate.h      |  3 +-
 llvm/lib/Transforms/Scalar/Reassociate.cpp    | 31 +++++++++-----
 llvm/test/Transforms/Reassociate/local-cse.ll | 40 +++++++++----------
 .../Transforms/Reassociate/reassoc-mul-nuw.ll | 34 ++++++++++++++++
 4 files changed, 78 insertions(+), 30 deletions(-)
 create mode 100644 llvm/test/Transforms/Reassociate/reassoc-mul-nuw.ll

diff --git a/llvm/include/llvm/Transforms/Scalar/Reassociate.h b/llvm/include/llvm/Transforms/Scalar/Reassociate.h
index 28794d27325a..7e47f8ae5d81 100644
--- a/llvm/include/llvm/Transforms/Scalar/Reassociate.h
+++ b/llvm/include/llvm/Transforms/Scalar/Reassociate.h
@@ -102,7 +102,8 @@ private:
   void canonicalizeOperands(Instruction *I);
   void ReassociateExpression(BinaryOperator *I);
   void RewriteExprTree(BinaryOperator *I,
-                       SmallVectorImpl<reassociate::ValueEntry> &Ops);
+                       SmallVectorImpl<reassociate::ValueEntry> &Ops,
+                       bool HasNUW);
   Value *OptimizeExpression(BinaryOperator *I,
                             SmallVectorImpl<reassociate::ValueEntry> &Ops);
   Value *OptimizeAdd(Instruction *I,
diff --git a/llvm/lib/Transforms/Scalar/Reassociate.cpp b/llvm/lib/Transforms/Scalar/Reassociate.cpp
index 42e979db24d2..818c7b40d489 100644
--- a/llvm/lib/Transforms/Scalar/Reassociate.cpp
+++ b/llvm/lib/Transforms/Scalar/Reassociate.cpp
@@ -466,7 +466,8 @@ using RepeatedValue = std::pair<Value*, APInt>;
 /// type and thus make the expression bigger.
 static bool LinearizeExprTree(Instruction *I,
                               SmallVectorImpl<RepeatedValue> &Ops,
-                              ReassociatePass::OrderedSet &ToRedo) {
+                              ReassociatePass::OrderedSet &ToRedo,
+                              bool &HasNUW) {
   assert((isa<UnaryOperator>(I) || isa<BinaryOperator>(I)) &&
          "Expected a UnaryOperator or BinaryOperator!");
   LLVM_DEBUG(dbgs() << "LINEARIZE: " << *I << '\n');
@@ -515,6 +516,9 @@ static bool LinearizeExprTree(Instruction *I,
     std::pair<Instruction*, APInt> P = Worklist.pop_back_val();
     I = P.first; // We examine the operands of this binary operator.
 
+    if (isa<OverflowingBinaryOperator>(I))
+      HasNUW &= I->hasNoUnsignedWrap();
+
     for (unsigned OpIdx = 0; OpIdx < I->getNumOperands(); ++OpIdx) { // Visit operands.
       Value *Op = I->getOperand(OpIdx);
       APInt Weight = P.second; // Number of paths to this operand.
@@ -657,7 +661,8 @@ static bool LinearizeExprTree(Instruction *I,
 /// Now that the operands for this expression tree are
 /// linearized and optimized, emit them in-order.
 void ReassociatePass::RewriteExprTree(BinaryOperator *I,
-                                      SmallVectorImpl<ValueEntry> &Ops) {
+                                      SmallVectorImpl<ValueEntry> &Ops,
+                                      bool HasNUW) {
   assert(Ops.size() > 1 && "Single values should be used directly!");
 
   // Since our optimizations should never increase the number of operations, the
@@ -814,14 +819,20 @@ void ReassociatePass::RewriteExprTree(BinaryOperator *I,
   if (ExpressionChangedStart) {
     bool ClearFlags = true;
     do {
-      // Preserve FastMathFlags.
+      // Preserve flags.
       if (ClearFlags) {
         if (isa<FPMathOperator>(I)) {
           FastMathFlags Flags = I->getFastMathFlags();
           ExpressionChangedStart->clearSubclassOptionalData();
           ExpressionChangedStart->setFastMathFlags(Flags);
-        } else
+        } else {
           ExpressionChangedStart->clearSubclassOptionalData();
+          // Note that it doesn't hold for mul if one of the operands is zero.
+          // TODO: We can preserve NUW flag if we prove that all mul operands
+          // are non-zero.
+          if (HasNUW && ExpressionChangedStart->getOpcode() == Instruction::Add)
+            ExpressionChangedStart->setHasNoUnsignedWrap();
+        }
       }
 
       if (ExpressionChangedStart == ExpressionChangedEnd)
@@ -1175,7 +1186,8 @@ Value *ReassociatePass::RemoveFactorFromExpression(Value *V, Value *Factor) {
     return nullptr;
 
   SmallVector<RepeatedValue, 8> Tree;
-  MadeChange |= LinearizeExprTree(BO, Tree, RedoInsts);
+  bool HasNUW = true;
+  MadeChange |= LinearizeExprTree(BO, Tree, RedoInsts, HasNUW);
   SmallVector<ValueEntry, 8> Factors;
   Factors.reserve(Tree.size());
   for (unsigned i = 0, e = Tree.size(); i != e; ++i) {
@@ -1217,7 +1229,7 @@ Value *ReassociatePass::RemoveFactorFromExpression(Value *V, Value *Factor) {
 
   if (!FoundFactor) {
     // Make sure to restore the operands to the expression tree.
-    RewriteExprTree(BO, Factors);
+    RewriteExprTree(BO, Factors, HasNUW);
     return nullptr;
   }
 
@@ -1229,7 +1241,7 @@ Value *ReassociatePass::RemoveFactorFromExpression(Value *V, Value *Factor) {
     RedoInsts.insert(BO);
     V = Factors[0].Op;
   } else {
-    RewriteExprTree(BO, Factors);
+    RewriteExprTree(BO, Factors, HasNUW);
     V = BO;
   }
 
@@ -2354,7 +2366,8 @@ void ReassociatePass::ReassociateExpression(BinaryOperator *I) {
   // First, walk the expression tree, linearizing the tree, collecting the
   // operand information.
   SmallVector<RepeatedValue, 8> Tree;
-  MadeChange |= LinearizeExprTree(I, Tree, RedoInsts);
+  bool HasNUW = true;
+  MadeChange |= LinearizeExprTree(I, Tree, RedoInsts, HasNUW);
   SmallVector<ValueEntry, 8> Ops;
   Ops.reserve(Tree.size());
   for (const RepeatedValue &E : Tree)
@@ -2547,7 +2560,7 @@ void ReassociatePass::ReassociateExpression(BinaryOperator *I) {
              dbgs() << '\n');
   // Now that we ordered and optimized the expressions, splat them back into
   // the expression tree, removing any unneeded nodes.
-  RewriteExprTree(I, Ops);
+  RewriteExprTree(I, Ops, HasNUW);
 }
 
 void
diff --git a/llvm/test/Transforms/Reassociate/local-cse.ll b/llvm/test/Transforms/Reassociate/local-cse.ll
index 1609cb1b36fd..4d0467e263f5 100644
--- a/llvm/test/Transforms/Reassociate/local-cse.ll
+++ b/llvm/test/Transforms/Reassociate/local-cse.ll
@@ -26,16 +26,16 @@ define void @chain_spanning_several_blocks(i64 %inv1, i64 %inv2, i64 %inv3, i64
 ; LOCAL_CSE-LABEL: define void @chain_spanning_several_blocks
 ; LOCAL_CSE-SAME: (i64 [[INV1:%.*]], i64 [[INV2:%.*]], i64 [[INV3:%.*]], i64 [[INV4:%.*]], i64 [[INV5:%.*]]) {
 ; LOCAL_CSE-NEXT:  bb1:
-; LOCAL_CSE-NEXT:    [[CHAIN_A0:%.*]] = add i64 [[INV2]], [[INV1]]
+; LOCAL_CSE-NEXT:    [[CHAIN_A0:%.*]] = add nuw i64 [[INV2]], [[INV1]]
 ; LOCAL_CSE-NEXT:    br label [[BB2:%.*]]
 ; LOCAL_CSE:       bb2:
 ; LOCAL_CSE-NEXT:    [[VAL_BB2:%.*]] = call i64 @get_val()
-; LOCAL_CSE-NEXT:    [[CHAIN_A1:%.*]] = add i64 [[CHAIN_A0]], [[INV4]]
-; LOCAL_CSE-NEXT:    [[CHAIN_A2:%.*]] = add i64 [[CHAIN_A1]], [[VAL_BB2]]
-; LOCAL_CSE-NEXT:    [[CHAIN_B1:%.*]] = add i64 [[CHAIN_A0]], [[INV5]]
-; LOCAL_CSE-NEXT:    [[CHAIN_B2:%.*]] = add i64 [[CHAIN_B1]], [[VAL_BB2]]
-; LOCAL_CSE-NEXT:    [[CHAIN_C0:%.*]] = add i64 [[INV3]], [[INV1]]
-; LOCAL_CSE-NEXT:    [[CHAIN_C1:%.*]] = add i64 [[CHAIN_C0]], [[VAL_BB2]]
+; LOCAL_CSE-NEXT:    [[CHAIN_A1:%.*]] = add nuw i64 [[CHAIN_A0]], [[INV4]]
+; LOCAL_CSE-NEXT:    [[CHAIN_A2:%.*]] = add nuw i64 [[CHAIN_A1]], [[VAL_BB2]]
+; LOCAL_CSE-NEXT:    [[CHAIN_B1:%.*]] = add nuw i64 [[CHAIN_A0]], [[INV5]]
+; LOCAL_CSE-NEXT:    [[CHAIN_B2:%.*]] = add nuw i64 [[CHAIN_B1]], [[VAL_BB2]]
+; LOCAL_CSE-NEXT:    [[CHAIN_C0:%.*]] = add nuw i64 [[INV3]], [[INV1]]
+; LOCAL_CSE-NEXT:    [[CHAIN_C1:%.*]] = add nuw i64 [[CHAIN_C0]], [[VAL_BB2]]
 ; LOCAL_CSE-NEXT:    call void @keep_alive(i64 [[CHAIN_A2]])
 ; LOCAL_CSE-NEXT:    call void @keep_alive(i64 [[CHAIN_B2]])
 ; LOCAL_CSE-NEXT:    call void @keep_alive(i64 [[CHAIN_C1]])
@@ -47,11 +47,11 @@ define void @chain_spanning_several_blocks(i64 %inv1, i64 %inv2, i64 %inv3, i64
 ; CSE-NEXT:    br label [[BB2:%.*]]
 ; CSE:       bb2:
 ; CSE-NEXT:    [[VAL_BB2:%.*]] = call i64 @get_val()
-; CSE-NEXT:    [[CHAIN_A0:%.*]] = add i64 [[VAL_BB2]], [[INV1]]
-; CSE-NEXT:    [[CHAIN_A1:%.*]] = add i64 [[CHAIN_A0]], [[INV2]]
+; CSE-NEXT:    [[CHAIN_A0:%.*]] = add nuw i64 [[VAL_BB2]], [[INV1]]
+; CSE-NEXT:    [[CHAIN_A1:%.*]] = add nuw i64 [[CHAIN_A0]], [[INV2]]
 ; CSE-NEXT:    [[CHAIN_A2:%.*]] = add nuw nsw i64 [[CHAIN_A1]], [[INV4]]
 ; CSE-NEXT:    [[CHAIN_B2:%.*]] = add nuw nsw i64 [[CHAIN_A1]], [[INV5]]
-; CSE-NEXT:    [[CHAIN_C1:%.*]] = add i64 [[CHAIN_A0]], [[INV3]]
+; CSE-NEXT:    [[CHAIN_C1:%.*]] = add nuw i64 [[CHAIN_A0]], [[INV3]]
 ; CSE-NEXT:    call void @keep_alive(i64 [[CHAIN_A2]])
 ; CSE-NEXT:    call void @keep_alive(i64 [[CHAIN_B2]])
 ; CSE-NEXT:    call void @keep_alive(i64 [[CHAIN_C1]])
@@ -90,19 +90,19 @@ define void @chain_spanning_several_blocks_no_entry_anchor() {
 ; LOCAL_CSE-NEXT:    br label [[BB1:%.*]]
 ; LOCAL_CSE:       bb1:
 ; LOCAL_CSE-NEXT:    [[INV1_BB1:%.*]] = call i64 @get_val()
-; LOCAL_CSE-NEXT:    [[CHAIN_A0:%.*]] = add i64 [[INV1_BB1]], [[INV2_BB0]]
+; LOCAL_CSE-NEXT:    [[CHAIN_A0:%.*]] = add nuw i64 [[INV1_BB1]], [[INV2_BB0]]
 ; LOCAL_CSE-NEXT:    br label [[BB2:%.*]]
 ; LOCAL_CSE:       bb2:
 ; LOCAL_CSE-NEXT:    [[INV3_BB2:%.*]] = call i64 @get_val()
 ; LOCAL_CSE-NEXT:    [[INV4_BB2:%.*]] = call i64 @get_val()
 ; LOCAL_CSE-NEXT:    [[INV5_BB2:%.*]] = call i64 @get_val()
 ; LOCAL_CSE-NEXT:    [[VAL_BB2:%.*]] = call i64 @get_val()
-; LOCAL_CSE-NEXT:    [[CHAIN_A1:%.*]] = add i64 [[CHAIN_A0]], [[INV4_BB2]]
-; LOCAL_CSE-NEXT:    [[CHAIN_A2:%.*]] = add i64 [[CHAIN_A1]], [[VAL_BB2]]
-; LOCAL_CSE-NEXT:    [[CHAIN_B1:%.*]] = add i64 [[CHAIN_A0]], [[INV5_BB2]]
-; LOCAL_CSE-NEXT:    [[CHAIN_B2:%.*]] = add i64 [[CHAIN_B1]], [[VAL_BB2]]
-; LOCAL_CSE-NEXT:    [[CHAIN_C0:%.*]] = add i64 [[VAL_BB2]], [[INV1_BB1]]
-; LOCAL_CSE-NEXT:    [[CHAIN_C1:%.*]] = add i64 [[CHAIN_C0]], [[INV3_BB2]]
+; LOCAL_CSE-NEXT:    [[CHAIN_A1:%.*]] = add nuw i64 [[CHAIN_A0]], [[INV4_BB2]]
+; LOCAL_CSE-NEXT:    [[CHAIN_A2:%.*]] = add nuw i64 [[CHAIN_A1]], [[VAL_BB2]]
+; LOCAL_CSE-NEXT:    [[CHAIN_B1:%.*]] = add nuw i64 [[CHAIN_A0]], [[INV5_BB2]]
+; LOCAL_CSE-NEXT:    [[CHAIN_B2:%.*]] = add nuw i64 [[CHAIN_B1]], [[VAL_BB2]]
+; LOCAL_CSE-NEXT:    [[CHAIN_C0:%.*]] = add nuw i64 [[VAL_BB2]], [[INV1_BB1]]
+; LOCAL_CSE-NEXT:    [[CHAIN_C1:%.*]] = add nuw i64 [[CHAIN_C0]], [[INV3_BB2]]
 ; LOCAL_CSE-NEXT:    call void @keep_alive(i64 [[CHAIN_A2]])
 ; LOCAL_CSE-NEXT:    call void @keep_alive(i64 [[CHAIN_B2]])
 ; LOCAL_CSE-NEXT:    call void @keep_alive(i64 [[CHAIN_C1]])
@@ -120,11 +120,11 @@ define void @chain_spanning_several_blocks_no_entry_anchor() {
 ; CSE-NEXT:    [[INV4_BB2:%.*]] = call i64 @get_val()
 ; CSE-NEXT:    [[INV5_BB2:%.*]] = call i64 @get_val()
 ; CSE-NEXT:    [[VAL_BB2:%.*]] = call i64 @get_val()
-; CSE-NEXT:    [[CHAIN_A0:%.*]] = add i64 [[VAL_BB2]], [[INV1_BB1]]
-; CSE-NEXT:    [[CHAIN_A1:%.*]] = add i64 [[CHAIN_A0]], [[INV2_BB0]]
+; CSE-NEXT:    [[CHAIN_A0:%.*]] = add nuw i64 [[VAL_BB2]], [[INV1_BB1]]
+; CSE-NEXT:    [[CHAIN_A1:%.*]] = add nuw i64 [[CHAIN_A0]], [[INV2_BB0]]
 ; CSE-NEXT:    [[CHAIN_A2:%.*]] = add nuw nsw i64 [[CHAIN_A1]], [[INV4_BB2]]
 ; CSE-NEXT:    [[CHAIN_B2:%.*]] = add nuw nsw i64 [[CHAIN_A1]], [[INV5_BB2]]
-; CSE-NEXT:    [[CHAIN_C1:%.*]] = add i64 [[CHAIN_A0]], [[INV3_BB2]]
+; CSE-NEXT:    [[CHAIN_C1:%.*]] = add nuw i64 [[CHAIN_A0]], [[INV3_BB2]]
 ; CSE-NEXT:    call void @keep_alive(i64 [[CHAIN_A2]])
 ; CSE-NEXT:    call void @keep_alive(i64 [[CHAIN_B2]])
 ; CSE-NEXT:    call void @keep_alive(i64 [[CHAIN_C1]])
diff --git a/llvm/test/Transforms/Reassociate/reassoc-mul-nuw.ll b/llvm/test/Transforms/Reassociate/reassoc-mul-nuw.ll
new file mode 100644
index 000000000000..682fad8d222b
--- /dev/null
+++ b/llvm/test/Transforms/Reassociate/reassoc-mul-nuw.ll
@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt < %s -passes=reassociate -S | FileCheck %s
+
+; We cannot preserve nuw flags for mul
+define i4 @nuw_preserve_negative(i4 %a, i4 %b, i4 %c) {
+; CHECK-LABEL: define i4 @nuw_preserve_negative(
+; CHECK-SAME: i4 [[A:%.*]], i4 [[B:%.*]], i4 [[C:%.*]]) {
+; CHECK-NEXT:    [[V0:%.*]] = mul i4 [[B]], [[A]]
+; CHECK-NEXT:    [[V1:%.*]] = mul i4 [[V0]], [[C]]
+; CHECK-NEXT:    ret i4 [[V1]]
+;
+  %v0 = mul nuw i4 %a, %c
+  %v1 = mul nuw i4 %v0, %b
+  ret i4 %v1
+}
+
+; TODO: we can add nuw flags if we know all operands are non-zero.
+define i4 @nuw_preserve_non_zero(i4 %a, i4 %b, i4 %c) {
+; CHECK-LABEL: define i4 @nuw_preserve_non_zero(
+; CHECK-SAME: i4 [[A:%.*]], i4 [[B:%.*]], i4 [[C:%.*]]) {
+; CHECK-NEXT:    [[A0:%.*]] = add nuw i4 [[A]], 1
+; CHECK-NEXT:    [[B0:%.*]] = add nuw i4 [[B]], 1
+; CHECK-NEXT:    [[C0:%.*]] = add nuw i4 [[C]], 1
+; CHECK-NEXT:    [[V0:%.*]] = mul i4 [[B0]], [[A0]]
+; CHECK-NEXT:    [[V1:%.*]] = mul i4 [[V0]], [[C0]]
+; CHECK-NEXT:    ret i4 [[V1]]
+;
+  %a0 = add nuw i4 %a, 1
+  %b0 = add nuw i4 %b, 1
+  %c0 = add nuw i4 %c, 1
+  %v0 = mul nuw i4 %a0, %c0
+  %v1 = mul nuw i4 %v0, %b0
+  ret i4 %v1
+}
-- 
GitLab


From 6ed9a81f7ebd23f125867dd270785dd0e63043c6 Mon Sep 17 00:00:00 2001
From: Vlad Serebrennikov <serebrennikov.vladislav@gmail.com>
Date: Sat, 9 Dec 2023 12:53:48 +0400
Subject: [PATCH 017/349] [clang][NFC] Refactor expected directives in C++ DRs
 2000-2799 (#74921)

This patch continues the work started with ea5b1ef016d020c37f903d6c7d4f623be975dab8. See that commit and its
corresponding PR for details.
---
 clang/test/CXX/drs/dr20xx.cpp | 219 +++++++++++++++++++++-------------
 clang/test/CXX/drs/dr21xx.cpp | 141 ++++++++++++++--------
 clang/test/CXX/drs/dr22xx.cpp |  37 +++---
 clang/test/CXX/drs/dr2354.cpp |  10 --
 clang/test/CXX/drs/dr23xx.cpp |  57 ++++++---
 clang/test/CXX/drs/dr2406.cpp |  30 -----
 clang/test/CXX/drs/dr24xx.cpp |  51 +++++++-
 clang/test/CXX/drs/dr25xx.cpp | 106 ++++++++--------
 clang/test/CXX/drs/dr26xx.cpp | 121 ++++++++++++-------
 clang/test/CXX/drs/dr27xx.cpp |  25 +++-
 10 files changed, 499 insertions(+), 298 deletions(-)
 delete mode 100644 clang/test/CXX/drs/dr2354.cpp
 delete mode 100644 clang/test/CXX/drs/dr2406.cpp

diff --git a/clang/test/CXX/drs/dr20xx.cpp b/clang/test/CXX/drs/dr20xx.cpp
index 4f81b0b413d4..60ee7684440f 100644
--- a/clang/test/CXX/drs/dr20xx.cpp
+++ b/clang/test/CXX/drs/dr20xx.cpp
@@ -1,13 +1,14 @@
-// RUN: %clang_cc1 -std=c++98 -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors \
-// RUN:            -Wno-variadic-macros -Wno-c11-extensions
-// RUN: %clang_cc1 -std=c++11 -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors
-// RUN: %clang_cc1 -std=c++14 -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors
-// RUN: %clang_cc1 -std=c++17 -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors
-// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors
-// RUN: %clang_cc1 -std=c++23 -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors
-
-#if __cplusplus < 201103L
-#define static_assert(...) _Static_assert(__VA_ARGS__)
+// RUN: %clang_cc1 -std=c++98 -triple x86_64-unknown-unknown %s -verify=expected,cxx98 -fexceptions -fcxx-exceptions -pedantic-errors
+// RUN: %clang_cc1 -std=c++11 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11,cxx11 -fexceptions -fcxx-exceptions -pedantic-errors
+// RUN: %clang_cc1 -std=c++14 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11,since-cxx14 -fexceptions -fcxx-exceptions -pedantic-errors
+// RUN: %clang_cc1 -std=c++17 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11,since-cxx14 -fexceptions -fcxx-exceptions -pedantic-errors
+// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11,since-cxx14,since-cxx20 -fexceptions -fcxx-exceptions -pedantic-errors
+// RUN: %clang_cc1 -std=c++23 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11,since-cxx14,since-cxx20 -fexceptions -fcxx-exceptions -pedantic-errors
+// RUN: %clang_cc1 -std=c++2c -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11,since-cxx14,since-cxx20 -fexceptions -fcxx-exceptions -pedantic-errors
+
+#if __cplusplus == 199711L
+#define static_assert(...) __extension__ _Static_assert(__VA_ARGS__)
+// cxx98-error@-1 {{variadic macros are a C99 feature}}
 #endif
 
 namespace dr2007 { // dr2007: 3.4
@@ -15,8 +16,12 @@ template<typename T> struct A { typename T::error e; };
 template<typename T> struct B { };
 B<A<void> > b1;
 B<A<void> > b2 = b1;
-int a = b2[0]; // expected-error {{does not provide a subscript operator}}
-int b = __builtin_addressof(b2)->foo; // expected-error {{no member}}
+int a = b2[0];
+// cxx98-error@-1 {{type 'B<A<void> >' does not provide a subscript operator}}
+// since-cxx11-error@-2 {{type 'B<A<void>>' does not provide a subscript operator}}
+int b = __builtin_addressof(b2)->foo;
+// cxx98-error@-1 {{no member named 'foo' in 'dr2007::B<dr2007::A<void> >'}}
+// since-cxx11-error@-2 {{no member named 'foo' in 'dr2007::B<dr2007::A<void>>'}}
 }
 
 // dr2009: na
@@ -24,45 +29,69 @@ int b = __builtin_addressof(b2)->foo; // expected-error {{no member}}
 namespace dr2026 { // dr2026: 11
   template<int> struct X {};
 
-  const int a = a + 1; // expected-warning {{uninitialized}} expected-note {{here}} expected-note 0-1{{outside its lifetime}}
-  X<a> xa; // expected-error {{constant expression}} expected-note {{initializer of 'a'}}
+  const int a = a + 1; // #dr2026-a
+  // expected-warning@-1 {{variable 'a' is uninitialized when used within its own initialization}}
+  X<a> xa; // #dr2026-xa
+  // cxx98-error@-1 {{non-type template argument of type 'int' is not an integral constant expression}}
+  //   cxx98-note@-2 {{initializer of 'a' is not a constant expression}}
+  //   cxx98-note@#dr2026-a {{declared here}}
+  // since-cxx11-error@#dr2026-xa {{non-type template argument is not a constant expression}}
+  //   since-cxx11-note@#dr2026-xa {{initializer of 'a' is not a constant expression}}
+  //   since-cxx11-note@#dr2026-a {{declared here}}
 
 #if __cplusplus >= 201103L
-  constexpr int b = b; // expected-error {{constant expression}} expected-note {{outside its lifetime}}
-  [[clang::require_constant_initialization]] int c = c; // expected-error {{constant initializer}} expected-note {{attribute}}
-#if __cplusplus == 201103L
-  // expected-note@-2 {{read of non-const variable}} expected-note@-2 {{declared here}}
-#else
-  // expected-note@-4 {{outside its lifetime}}
-#endif
+  constexpr int b = b;
+  // since-cxx11-error@-1 {{constexpr variable 'b' must be initialized by a constant expression}}
+  //   since-cxx11-note@-2 {{read of object outside its lifetime is not allowed in a constant expression}}
+  [[clang::require_constant_initialization]] int c = c;
+  // since-cxx11-error@-1 {{variable does not have a constant initializer}}
+  //   since-cxx11-note@-2 {{required by 'require_constant_initialization' attribute here}}
+  //   cxx11-note@-3 {{read of non-const variable 'c' is not allowed in a constant expression}}
+  //   cxx11-note@-4 {{declared here}}
+  //   since-cxx14-note@-5 {{read of object outside its lifetime is not allowed in a constant expression}}
 #endif
 
-#if __cplusplus > 201703L
-  constinit int d = d; // expected-error {{constant initializer}} expected-note {{outside its lifetime}} expected-note {{'constinit'}}
+#if __cplusplus >= 202002L
+  constinit int d = d;
+  // since-cxx20-error@-1 {{variable does not have a constant initializer}}
+  //   since-cxx20-note@-2 {{required by 'constinit' specifier here}}
+  //   since-cxx20-note@-3 {{read of object outside its lifetime is not allowed in a constant expression}}
 #endif
 
   void f() {
-    static const int e = e + 1; // expected-warning {{suspicious}} expected-note {{here}} expected-note 0-1{{outside its lifetime}}
-    X<e> xe; // expected-error {{constant expression}} expected-note {{initializer of 'e'}}
+    static const int e = e + 1; // #dr2026-e
+    // expected-warning@-1 {{static variable 'e' is suspiciously used within its own initialization}}
+    X<e> xe; // #dr2026-xe
+    // cxx98-error@-1 {{non-type template argument of type 'int' is not an integral constant expression}}
+    //   cxx98-note@-2 {{initializer of 'e' is not a constant expression}}
+    //   cxx98-note@#dr2026-e {{declared here}}
+    // since-cxx11-error@#dr2026-xe {{non-type template argument is not a constant expression}}
+    //   since-cxx11-note@#dr2026-xe {{initializer of 'e' is not a constant expression}}
+    //   since-cxx11-note@#dr2026-e {{declared here}}
 
 #if __cplusplus >= 201103L
-    static constexpr int f = f; // expected-error {{constant expression}} expected-note {{outside its lifetime}}
-    [[clang::require_constant_initialization]] static int g = g; // expected-error {{constant initializer}} expected-note {{attribute}}
-#if __cplusplus == 201103L
-    // expected-note@-2 {{read of non-const variable}} expected-note@-2 {{declared here}}
-#else
-    // expected-note@-4 {{outside its lifetime}}
-#endif
+    static constexpr int f = f;
+    // since-cxx11-error@-1 {{constexpr variable 'f' must be initialized by a constant expression}}
+    //   since-cxx11-note@-2 {{read of object outside its lifetime is not allowed in a constant expression}}
+    [[clang::require_constant_initialization]] static int g = g;
+    // since-cxx11-error@-1 {{variable does not have a constant initializer}}
+    //   since-cxx11-note@-2 {{required by 'require_constant_initialization' attribute here}}
+    //   cxx11-note@-3 {{read of non-const variable 'g' is not allowed in a constant expression}}
+    //   cxx11-note@-4 {{declared here}}
+    //   since-cxx14-note@-5 {{read of object outside its lifetime is not allowed in a constant expression}}
 #endif
 
-#if __cplusplus > 201703L
-    static constinit int h = h; // expected-error {{constant initializer}} expected-note {{outside its lifetime}} expected-note {{'constinit'}}
+#if __cplusplus >= 202002L
+    static constinit int h = h;
+    // since-cxx20-error@-1 {{variable does not have a constant initializer}}
+    //   since-cxx20-note@-2 {{required by 'constinit' specifier here}}
+    //   since-cxx20-note@-3 {{read of object outside its lifetime is not allowed in a constant expression}}
 #endif
   }
 }
 
 namespace dr2049 { // dr2049: 18 drafting
-#if __cplusplus > 202002L
+#if __cplusplus >= 202302L
 template <int* x = {}> struct X {};
 X<> a;
 X<nullptr> b;
@@ -120,8 +149,8 @@ namespace dr2076 { // dr2076: 13
     operator string_view() const;
   };
 
-  void foo(const string &); // expected-note {{cannot convert initializer list}}
-  void bar(string_view); // expected-note 2{{cannot convert initializer list}}
+  void foo(const string &); // #dr2076-foo 
+  void bar(string_view); // #dr2076-bar
 
   void func(const string &arg) {
     // An argument in one set of braces is subject to user-defined conversions;
@@ -130,11 +159,17 @@ namespace dr2076 { // dr2076: 13
     foo(arg);
     foo({arg});
     foo({{arg}});
-    foo({{{arg}}}); // expected-error {{no matching function}}
+    foo({{{arg}}});
+    // since-cxx11-error@-1 {{no matching function}}
+    //   since-cxx11-note@#dr2076-foo  {{cannot convert initializer list}}
     bar(arg);
     bar({arg});
-    bar({{arg}}); // expected-error {{no matching function}}
-    bar({{{arg}}}); // expected-error {{no matching function}}
+    bar({{arg}});
+    // since-cxx11-error@-1 {{no matching function}}
+    //   since-cxx11-note@#dr2076-bar {{cannot convert initializer list}}
+    bar({{{arg}}});
+    // since-cxx11-error@-1 {{no matching function}}
+    //   since-cxx11-note@#dr2076-bar {{cannot convert initializer list}}
   }
 #endif
 }
@@ -172,18 +207,20 @@ namespace dr2083 { // dr2083: partial
   // treatment in C++11 onwards. We continue to apply that even after DR2083.
   void ref_to_non_const() {
     int c;
-    const int &ra = a; // expected-note 0-1{{here}}
-    int &rb = b; // expected-note 0-1{{here}}
-    int &rc = c; // expected-note {{here}}
+    const int &ra = a; // #dr2083-ra
+    int &rb = b; // #dr2083-rb
+    int &rc = c; // #dr2083-rc
     struct A {
       int f() {
         int a = ra;
+        // cxx98-error@-1 {{reference to local variable 'ra' declared in enclosing function 'dr2083::ref_to_non_const'}}
+        //   cxx98-note@#dr2083-ra {{'ra' declared here}}
         int b = rb;
-#if __cplusplus < 201103L
-        // expected-error@-3 {{in enclosing function}}
-        // expected-error@-3 {{in enclosing function}}
-#endif
-        int c = rc; // expected-error {{in enclosing function}}
+        // cxx98-error@-1 {{reference to local variable 'rb' declared in enclosing function 'dr2083::ref_to_non_const'}}
+        //   cxx98-note@#dr2083-rb {{'rb' declared here}}
+        int c = rc;
+        // expected-error@-1 {{reference to local variable 'rc' declared in enclosing function 'dr2083::ref_to_non_const'}}
+        //   expected-note@#dr2083-rc {{'rc' declared here}}
         return a + b + c;
       }
     };
@@ -207,18 +244,24 @@ namespace dr2083 { // dr2083: partial
     constexpr NoMut1 nm1 = {1, 2};
     constexpr NoMut2 nm2 = {1, 2};
     constexpr NoMut3 nm3 = {1, 2};
-    constexpr Mut1 m1 = {1, 2}; // expected-note {{declared here}}
-    constexpr Mut2 m2 = {1, 2}; // expected-note {{declared here}}
-    constexpr Mut3 m3 = {1, 2}; // expected-note {{declared here}}
+    constexpr Mut1 m1 = {1, 2}; // #dr2083-m1
+    constexpr Mut2 m2 = {1, 2}; // #dr2083-m2
+    constexpr Mut3 m3 = {1, 2}; // #dr2083-m3
     struct A {
       void f() {
         static_assert(nm1.a == 1, "");
         static_assert(nm2.m.a == 1, "");
         static_assert(nm3.a == 1, "");
         // Can't even access a non-mutable member of a variable containing mutable fields.
-        static_assert(m1.a == 1, ""); // expected-error {{enclosing function}}
-        static_assert(m2.m.a == 1, ""); // expected-error {{enclosing function}}
-        static_assert(m3.a == 1, ""); // expected-error {{enclosing function}}
+        static_assert(m1.a == 1, "");
+        // since-cxx11-error@-1 {{reference to local variable 'm1' declared in enclosing function 'dr2083::mutable_subobjects'}}
+        //   since-cxx11-note@#dr2083-m1 {{'m1' declared here}}
+        static_assert(m2.m.a == 1, "");
+        // since-cxx11-error@-1 {{reference to local variable 'm2' declared in enclosing function 'dr2083::mutable_subobjects'}}
+        //   since-cxx11-note@#dr2083-m2 {{'m2' declared here}}
+        static_assert(m3.a == 1, "");
+        // since-cxx11-error@-1 {{reference to local variable 'm3' declared in enclosing function 'dr2083::mutable_subobjects'}}
+        //   since-cxx11-note@#dr2083-m3 {{'m3' declared here}}
       }
     };
   }
@@ -231,14 +274,16 @@ namespace dr2083 { // dr2083: partial
 #if __cplusplus >= 201103L
     constexpr
 #endif
-      A a = {}; // expected-note {{here}}
+      A a = {}; // #dr2083-a
     struct B {
       void f() {
         ellipsis(n);
         // Even though this is technically modelled as an lvalue-to-rvalue
         // conversion, it calls a constructor and binds 'a' to a reference, so
         // it results in an odr-use.
-        ellipsis(a); // expected-error {{enclosing function}}
+        ellipsis(a);
+        // expected-error@-1 {{reference to local variable 'a' declared in enclosing function 'dr2083::ellipsis'}}
+        //   expected-note@#dr2083-a {{'a' declared here}}
       }
     };
   }
@@ -246,7 +291,7 @@ namespace dr2083 { // dr2083: partial
 #if __cplusplus >= 201103L
   void volatile_lval() {
     struct A { int n; };
-    constexpr A a = {0}; // expected-note {{here}}
+    constexpr A a = {0}; // #dr2083-a2
     struct B {
       void f() {
         // An lvalue-to-rvalue conversion of a volatile lvalue always results
@@ -254,7 +299,9 @@ namespace dr2083 { // dr2083: partial
         int A::*p = &A::n;
         int x = a.*p;
         volatile int A::*q = p;
-        int y = a.*q; // expected-error {{enclosing function}}
+        int y = a.*q;
+        // since-cxx11-error@-1 {{reference to local variable 'a' declared in enclosing function 'dr2083::volatile_lval'}}
+        //   since-cxx11-note@#dr2083-a2 {{'a' declared here}}
       }
     };
   }
@@ -262,32 +309,45 @@ namespace dr2083 { // dr2083: partial
 
   void discarded_lval() {
     struct A { int x; mutable int y; volatile int z; };
-    A a; // expected-note 1+{{here}}
-    int &r = a.x; // expected-note {{here}}
+    A a; // #dr2083-a-3
+    int &r = a.x; // #dr2083-r
     struct B {
       void f() {
-        a.x; // expected-warning {{unused}}
-        a.*&A::x; // expected-warning {{unused}}
-        true ? a.x : a.y; // expected-warning {{unused}}
+        // FIXME: We emit more errors than we should be. They are explictly marked below.
+        a.x;
+        // expected-warning@-1 {{expression result unused}}
+        // expected-error@-2 {{reference to local variable 'a' declared in enclosing function 'dr2083::discarded_lval'}} FIXME
+        //   expected-note@#dr2083-a-3 {{'a' declared here}}
+        a.*&A::x;
+        // expected-warning@-1 {{expression result unused}}
+        // expected-error@-2 {{reference to local variable 'a' declared in enclosing function 'dr2083::discarded_lval'}} FIXME
+        //   expected-note@#dr2083-a-3 {{'a' declared here}}
+        true ? a.x : a.y; // #dr2083-ternary
+        // expected-warning@-1 {{expression result unused}}
+        // expected-error@#dr2083-ternary {{reference to local variable 'a' declared in enclosing function 'dr2083::discarded_lval'}} FIXME
+        //   expected-note@#dr2083-a-3 {{'a' declared here}}
+        // expected-error@#dr2083-ternary {{reference to local variable 'a' declared in enclosing function 'dr2083::discarded_lval'}} FIXME
+        //   expected-note@#dr2083-a-3 {{'a' declared here}}
         (void)a.x;
-        a.x, discarded_lval(); // expected-warning {{left operand of comma operator has no effect}}
-#if 1 // FIXME: These errors are all incorrect; the above code is valid.
-      // expected-error@-6 {{enclosing function}}
-      // expected-error@-6 {{enclosing function}}
-      // expected-error@-6 2{{enclosing function}}
-      // expected-error@-6 {{enclosing function}}
-      // expected-error@-6 {{enclosing function}}
-#endif
+        // expected-error@-1 {{reference to local variable 'a' declared in enclosing function 'dr2083::discarded_lval'}} FIXME
+        //   expected-note@#dr2083-a-3 {{'a' declared here}}
+        a.x, discarded_lval();
+        // expected-warning@-1 {{left operand of comma operator has no effect}}
+        // expected-error@-2 {{reference to local variable 'a' declared in enclosing function 'dr2083::discarded_lval'}} FIXME
+        //   expected-note@#dr2083-a-3 {{'a' declared here}}
 
         // 'volatile' qualifier triggers an lvalue-to-rvalue conversion.
-        a.z; // expected-error {{enclosing function}}
-#if __cplusplus < 201103L
-        // expected-warning@-2 {{assign into a variable}}
-#endif
+        a.z;
+        // cxx98-warning@-1 {{expression result unused; assign into a variable to force a volatile load}}
+        // expected-error@-2 {{reference to local variable 'a' declared in enclosing function 'dr2083::discarded_lval'}}
+        //   expected-note@#dr2083-a-3 {{'a' declared here}}
 
         // References always get "loaded" to determine what they reference,
         // even if the result is discarded.
-        r; // expected-error {{enclosing function}} expected-warning {{unused}}
+        r;
+        // expected-warning@-1 {{expression result unused}}
+        // expected-error@-2 {{reference to local variable 'r' declared in enclosing function 'dr2083::discarded_lval'}}
+        //   expected-note@#dr2083-r {{'r' declared here}}
       }
     };
   }
@@ -295,12 +355,11 @@ namespace dr2083 { // dr2083: partial
   namespace dr_example_1 {
     extern int globx;
     int main() {
-      const int &x = globx;
+      const int &x = globx; // #dr2083-x
       struct A {
-#if __cplusplus < 201103L
-        // expected-error@+2 {{enclosing function}} expected-note@-3 {{here}}
-#endif
         const int *foo() { return &x; }
+        // cxx98-error@-1 {{reference to local variable 'x' declared in enclosing function 'dr2083::dr_example_1::main'}}
+        //   cxx98-note@#dr2083-x {{'x' declared here}}
       } a;
       return *a.foo();
     }
diff --git a/clang/test/CXX/drs/dr21xx.cpp b/clang/test/CXX/drs/dr21xx.cpp
index a1b8fe3f2a9b..a7e50df3f374 100644
--- a/clang/test/CXX/drs/dr21xx.cpp
+++ b/clang/test/CXX/drs/dr21xx.cpp
@@ -1,13 +1,14 @@
-// RUN: %clang_cc1 -std=c++98 -triple x86_64-unknown-unknown %s -verify -fexceptions -Wno-deprecated-builtins -fcxx-exceptions -pedantic-errors
-// RUN: %clang_cc1 -std=c++11 -triple x86_64-unknown-unknown %s -verify -fexceptions -Wno-deprecated-builtins -fcxx-exceptions -pedantic-errors
-// RUN: %clang_cc1 -std=c++14 -triple x86_64-unknown-unknown %s -verify -fexceptions -Wno-deprecated-builtins -fcxx-exceptions -pedantic-errors
-// RUN: %clang_cc1 -std=c++17 -triple x86_64-unknown-unknown %s -verify -fexceptions -Wno-deprecated-builtins -fcxx-exceptions -pedantic-errors
-// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-unknown %s -verify -fexceptions -Wno-deprecated-builtins -fcxx-exceptions -pedantic-errors
-// RUN: %clang_cc1 -std=c++23 -triple x86_64-unknown-unknown %s -verify -fexceptions -Wno-deprecated-builtins -fcxx-exceptions -pedantic-errors
-
-#if __cplusplus < 201103L
-// expected-error@+1 {{variadic macro}}
+// RUN: %clang_cc1 -std=c++98 -triple x86_64-unknown-unknown %s -verify=expected,cxx98-14,cxx98 -fexceptions -Wno-deprecated-builtins -fcxx-exceptions -pedantic-errors
+// RUN: %clang_cc1 -std=c++11 -triple x86_64-unknown-unknown %s -verify=expected,cxx98-14,since-cxx11 -fexceptions -Wno-deprecated-builtins -fcxx-exceptions -pedantic-errors
+// RUN: %clang_cc1 -std=c++14 -triple x86_64-unknown-unknown %s -verify=expected,cxx98-14,since-cxx11 -fexceptions -Wno-deprecated-builtins -fcxx-exceptions -pedantic-errors
+// RUN: %clang_cc1 -std=c++17 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11 -fexceptions -Wno-deprecated-builtins -fcxx-exceptions -pedantic-errors
+// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11 -fexceptions -Wno-deprecated-builtins -fcxx-exceptions -pedantic-errors
+// RUN: %clang_cc1 -std=c++23 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11 -fexceptions -Wno-deprecated-builtins -fcxx-exceptions -pedantic-errors
+// RUN: %clang_cc1 -std=c++2c -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11 -fexceptions -Wno-deprecated-builtins -fcxx-exceptions -pedantic-errors
+
+#if __cplusplus == 199711L
 #define static_assert(...) __extension__ _Static_assert(__VA_ARGS__)
+// cxx98-error@-1 {{variadic macros are a C99 feature}}
 #endif
 
 namespace dr2100 { // dr2100: 12
@@ -18,15 +19,14 @@ namespace dr2100 { // dr2100: 12
       return X<&n>::n; // ok, value-dependent
     }
     int g() {
-      static const int n = 2;
+      static const int n = 2; // #dr2100-n
       return X<&n>::n; // ok, value-dependent
-#if __cplusplus < 201702L
-      // expected-error@-2 {{does not have linkage}} expected-note@-3 {{here}}
-#endif
+      // cxx98-14-error@-1 {{non-type template argument refers to object 'n' that does not have linkage}}
+      //   cxx98-14-note@#dr2100-n {{non-type template argument refers to object here}}
     }
   };
   template<const int *P> struct X<P> {
-#if __cplusplus < 201103L
+#if __cplusplus == 199711L
     static const int n = 0;
 #else
     static const int n = *P;
@@ -40,11 +40,13 @@ namespace dr2100 { // dr2100: 12
   template<typename T> struct B {
     static const int n = 1;
     int f() {
-      return Y<n>::declared_later; // expected-error {{no member named 'declared_later'}}
+      return Y<n>::declared_later;
+      // expected-error@-1 {{no member named 'declared_later' in 'dr2100::Y<1>'}}
     }
     int g() {
       static const int n = 2;
-      return Y<n>::declared_later; // expected-error {{no member named 'declared_later'}}
+      return Y<n>::declared_later;
+      // expected-error@-1 {{no member named 'declared_later' in 'dr2100::Y<2>'}}
     }
   };
   template<int N> struct Y<N> {
@@ -55,10 +57,12 @@ namespace dr2100 { // dr2100: 12
 namespace dr2103 { // dr2103: yes
   void f() {
     int a;
-    int &r = a; // expected-note {{here}}
+    int &r = a; // #dr2103-r
     struct Inner {
       void f() {
-        int &s = r; // expected-error {{enclosing function}}
+        int &s = r;
+        // expected-error@-1 {{reference to local variable 'r' declared in enclosing function 'dr2103::f'}}
+        //   expected-note@#dr2103-r {{'r' declared here}}
         (void)s;
       }
     };
@@ -84,28 +88,46 @@ namespace dr2126 { // dr2126: 12
   A &b = (A &)(const A &)A{1};   // const temporary
   A &&c = (A &&)(const A &)A{1}; // const temporary
 
-  A &&d = {1};                   // non-const temporary expected-note {{here}}
-  const A &e = (A &)(A &&) A{1}; // non-const temporary expected-note {{here}}
-  A &&f = (A &&)(A &&) A{1};     // non-const temporary expected-note {{here}}
+  A &&d = {1};                   // non-const temporary #dr21260-d
+  const A &e = (A &)(A &&) A{1}; // non-const temporary #dr21260-e
+  A &&f = (A &&)(A &&) A{1};     // non-const temporary #dr21260-f
 
   constexpr const A &g = {1};    // const temporary
-  constexpr A &&h = {1};         // non-const temporary expected-note {{here}}
+  constexpr A &&h = {1};         // non-const temporary #dr21260-h
 
   struct B { const A &a; };
-  B i = {{1}};           // extending decl not usable in constant expr expected-note {{here}}
-  const B j = {{1}};     // extending decl not usable in constant expr expected-note {{here}}
+  B i = {{1}};           // extending decl not usable in constant expr #dr21260-i
+  const B j = {{1}};     // extending decl not usable in constant expr #dr21260-j
   constexpr B k = {{1}}; // extending decl usable in constant expr
 
   static_assert(a.n == 1, "");
   static_assert(b.n == 1, "");
   static_assert(c.n == 1, "");
-  static_assert(d.n == 1, ""); // expected-error {{constant}} expected-note {{read of temporary}}
-  static_assert(e.n == 1, ""); // expected-error {{constant}} expected-note {{read of temporary}}
-  static_assert(f.n == 1, ""); // expected-error {{constant}} expected-note {{read of temporary}}
+  static_assert(d.n == 1, "");
+  // since-cxx11-error@-1 {{static assertion expression is not an integral constant expression}}
+  //   since-cxx11-note@-2 {{read of temporary is not allowed in a constant expression outside the expression that created the temporary}}
+  //   since-cxx11-note@#dr21260-d {{temporary created here}}
+  static_assert(e.n == 1, "");
+  // since-cxx11-error@-1 {{static assertion expression is not an integral constant expression}}
+  //   since-cxx11-note@-2 {{read of temporary is not allowed in a constant expression outside the expression that created the temporary}}
+  //   since-cxx11-note@#dr21260-e {{temporary created here}}
+  static_assert(f.n == 1, "");
+  // since-cxx11-error@-1 {{static assertion expression is not an integral constant expression}}
+  //   since-cxx11-note@-2 {{read of temporary is not allowed in a constant expression outside the expression that created the temporary}}
+  //   since-cxx11-note@#dr21260-f {{temporary created here}}
   static_assert(g.n == 1, "");
-  static_assert(h.n == 1, ""); // expected-error {{constant}} expected-note {{read of temporary}}
-  static_assert(i.a.n == 1, ""); // expected-error {{constant}} expected-note {{read of non-constexpr variable}}
-  static_assert(j.a.n == 1, ""); // expected-error {{constant}} expected-note {{read of temporary}}
+  static_assert(h.n == 1, "");
+  // since-cxx11-error@-1 {{static assertion expression is not an integral constant expression}}
+  //   since-cxx11-note@-2 {{read of temporary is not allowed in a constant expression outside the expression that created the temporary}}
+  //   since-cxx11-note@#dr21260-h {{temporary created here}}
+  static_assert(i.a.n == 1, "");
+  // since-cxx11-error@-1 {{static assertion expression is not an integral constant expression}}
+  //   since-cxx11-note@-2 {{read of non-constexpr variable 'i' is not allowed in a constant expression}}
+  //   since-cxx11-note@#dr21260-i {{declared here}}
+  static_assert(j.a.n == 1, "");
+  // since-cxx11-error@-1 {{static assertion expression is not an integral constant expression}}
+  //   since-cxx11-note@-2 {{read of temporary is not allowed in a constant expression outside the expression that created the temporary}}
+  //   since-cxx11-note@#dr21260-j {{temporary created here}}
   static_assert(k.a.n == 1, "");
 #endif
 }
@@ -128,19 +150,27 @@ struct B{};
 
 void foo() {
   struct A *b = (1 == 1) ? new struct A : new struct A;
-  struct S *a = (1 == 1) ? new struct S : new struct S; // expected-error 2{{allocation of incomplete type}} // expected-note 2{{forward}}
+  struct S *a = (1 == 1) ? new struct S : new struct S;
+  // expected-error@-1 {{allocation of incomplete type 'struct S'}}
+  //   expected-note@-2 {{forward declaration of 'S'}}
+  // expected-error@-3 {{allocation of incomplete type 'struct S'}}
+  //   expected-note@-4 {{forward declaration of 'S'}}
 
 #if __cplusplus >= 201103L
   A *aa = new struct A{};
   B<int> *bb = new struct B<int>{};
-  (void)new struct C{}; // expected-error {{allocation of incomplete type }} // expected-note {{forward}}
+  (void)new struct C{};
+  // since-cxx11-error@-1 {{allocation of incomplete type 'struct C'}}
+  //   since-cxx11-note@-2 {{forward declaration of 'C'}}
 
   struct A *c = (1 == 1) ? new struct A {} : new struct A {};
 
-  alignof(struct D{}); // expected-error {{cannot be defined in a type specifier}}
+  alignof(struct D{});
+  // since-cxx11-error@-1 {{'D' cannot be defined in a type specifier}}
 #endif
 
-  sizeof(struct E{}); // expected-error {{cannot be defined in a type specifier}}
+  sizeof(struct E{});
+  // expected-error@-1 {{'E' cannot be defined in a type specifier}}
 
 }
 }
@@ -149,7 +179,8 @@ namespace dr2157 { // dr2157: 11
 #if __cplusplus >= 201103L
   enum E : int;
   struct X {
-    enum dr2157::E : int(); // expected-error {{only allows ':' in member enumeration declaration to introduce a fixed underlying type}}
+    enum dr2157::E : int();
+    // since-cxx11-error@-1 {{ISO C++ only allows ':' in member enumeration declaration to introduce a fixed underlying type, not an anonymous bit-field}}
   };
 #endif
 }
@@ -159,11 +190,13 @@ namespace dr2157 { // dr2157: 11
 namespace dr2170 { // dr2170: 9
 #if __cplusplus >= 201103L
   void f() {
-    constexpr int arr[3] = {1, 2, 3}; // expected-note {{here}}
+    constexpr int arr[3] = {1, 2, 3}; // #dr2170-arr
     struct S {
       int get(int n) { return arr[n]; }
-      const int &get_ref(int n) { return arr[n]; } // expected-error {{enclosing function}}
-      // FIXME: expected-warning@-1 {{reference to stack}}
+      const int &get_ref(int n) { return arr[n]; }
+      // since-cxx11-warning@-1 {{reference to stack memory associated with local variable 'arr' returned}} FIXME
+      // since-cxx11-error@-2 {{reference to local variable 'arr' declared in enclosing function 'dr2170::f'}}
+      //   since-cxx11-note@#dr2170-arr {{'arr' declared here}}
     };
   }
 #endif
@@ -198,22 +231,32 @@ static_assert(!__is_trivially_assignable(NonConstCopy &&, NonConstCopy &&), "");
 
 namespace dr2180 { // dr2180: yes
   class A {
-    A &operator=(const A &); // expected-note 0-2{{here}}
-    A &operator=(A &&); // expected-note 0-2{{here}} expected-error 0-1{{extension}}
+    A &operator=(const A &); // #dr2180-A-copy
+    A &operator=(A &&); // #dr2180-A-move
+    // cxx98-error@-1 {{rvalue references are a C++11 extension}}
   };
 
-  struct B : virtual A {
+  struct B : virtual A { // #dr2180-B
     B &operator=(const B &);
-    B &operator=(B &&); // expected-error 0-1{{extension}}
+    B &operator=(B &&);
+    // cxx98-error@-1 {{rvalue references are a C++11 extension}}
     virtual void foo() = 0;
   };
-#if __cplusplus < 201103L
-  B &B::operator=(const B&) = default; // expected-error {{private member}} expected-error {{extension}} expected-note {{here}}
-  B &B::operator=(B&&) = default; // expected-error {{private member}} expected-error 2{{extension}} expected-note {{here}}
-#else
-  B &B::operator=(const B&) = default; // expected-error {{would delete}} expected-note@-9{{inaccessible copy assignment}}
-  B &B::operator=(B&&) = default; // expected-error {{would delete}} expected-note@-10{{inaccessible move assignment}}
-#endif
+  B &B::operator=(const B&) = default; // #dr2180-B-copy
+  // cxx98-error@-1 {{defaulted function definitions are a C++11 extension}}
+  // cxx98-error@-2 {{'operator=' is a private member of 'dr2180::A'}}
+  //   cxx98-note@-3 {{in defaulted copy assignment operator for 'dr2180::B' first required here}}
+  //   cxx98-note@#dr2180-A-copy {{implicitly declared private here}}
+  // since-cxx11-error@#dr2180-B-copy {{defaulting this copy assignment operator would delete it after its first declaration}}
+  //   since-cxx11-note@#dr2180-B {{copy assignment operator of 'B' is implicitly deleted because base class 'A' has an inaccessible copy assignment operator}}
+  B &B::operator=(B&&) = default; // #dr2180-B-move
+  // cxx98-error@-1 {{rvalue references are a C++11 extension}}
+  // cxx98-error@-2 {{defaulted function definitions are a C++11 extension}}
+  // cxx98-error@-3 {{'operator=' is a private member of 'dr2180::A'}}
+  //   cxx98-note@-4 {{in defaulted move assignment operator for 'dr2180::B' first required here}}
+  //   cxx98-note@#dr2180-A-move {{implicitly declared private here}}
+  // since-cxx11-error@#dr2180-B-move {{defaulting this move assignment operator would delete it after its first declaration}}
+  //   since-cxx11-note@#dr2180-B {{move assignment operator of 'B' is implicitly deleted because base class 'A' has an inaccessible move assignment operator}}
 }
 
 namespace dr2199 { // dr2199: 3.8
diff --git a/clang/test/CXX/drs/dr22xx.cpp b/clang/test/CXX/drs/dr22xx.cpp
index cd849443b111..19518247b528 100644
--- a/clang/test/CXX/drs/dr22xx.cpp
+++ b/clang/test/CXX/drs/dr22xx.cpp
@@ -1,14 +1,19 @@
-// RUN: %clang_cc1 -std=c++98 -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors
-// RUN: %clang_cc1 -std=c++11 -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors
-// RUN: %clang_cc1 -std=c++14 -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors
-// RUN: %clang_cc1 -std=c++1z -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors
+// RUN: %clang_cc1 -std=c++98 -triple x86_64-unknown-unknown %s -verify=expected -fexceptions -fcxx-exceptions -pedantic-errors
+// RUN: %clang_cc1 -std=c++11 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11 -fexceptions -fcxx-exceptions -pedantic-errors
+// RUN: %clang_cc1 -std=c++14 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11 -fexceptions -fcxx-exceptions -pedantic-errors
+// RUN: %clang_cc1 -std=c++17 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11 -fexceptions -fcxx-exceptions -pedantic-errors
+// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11 -fexceptions -fcxx-exceptions -pedantic-errors
+// RUN: %clang_cc1 -std=c++23 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11 -fexceptions -fcxx-exceptions -pedantic-errors
+// RUN: %clang_cc1 -std=c++2c -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11 -fexceptions -fcxx-exceptions -pedantic-errors
+
 
 #if __cplusplus >= 201103L
 namespace dr2211 { // dr2211: 8
 void f() {
   int a;
-  auto f = [a](int a) { (void)a; }; // expected-error {{a lambda parameter cannot shadow an explicitly captured entity}}
-  // expected-note@-1{{variable 'a' is explicitly captured here}}
+  auto f = [a](int a) { (void)a; };
+  // since-cxx11-error@-1 {{a lambda parameter cannot shadow an explicitly captured entity}}
+  //   since-cxx11-note@-2 {{variable 'a' is explicitly captured here}}
   auto g = [=](int a) { (void)a; };
 }
 }
@@ -24,9 +29,12 @@ struct A<int, U>;
 
 namespace dr2229 { // dr2229: 7
 struct AnonBitfieldQualifiers {
-  const unsigned : 1; // expected-error {{anonymous bit-field cannot have qualifiers}}
-  volatile unsigned : 1; // expected-error {{anonymous bit-field cannot have qualifiers}}
-  const volatile unsigned : 1; // expected-error {{anonymous bit-field cannot have qualifiers}}
+  const unsigned : 1;
+  // expected-error@-1 {{anonymous bit-field cannot have qualifiers}}
+  volatile unsigned : 1;
+  // expected-error@-1 {{anonymous bit-field cannot have qualifiers}}
+  const volatile unsigned : 1;
+  // expected-error@-1 {{anonymous bit-field cannot have qualifiers}}
 
   unsigned : 1;
   const unsigned i1 : 1;
@@ -98,7 +106,8 @@ namespace MultilevelSpecialization {
     template <T... V> void f(int i = 0, int (&... arr)[V]);
   };
   template<> template<int a, int b>
-    void B<int, int>::f(int i, int (&arr1)[a], int (&arr2)[b]) {} // expected-error {{does not match}}
+    void B<int, int>::f(int i, int (&arr1)[a], int (&arr2)[b]) {}
+    // since-cxx11-error@-1 {{out-of-line definition of 'f' does not match any declaration in 'dr2233::MultilevelSpecialization::B<int, int>'}}
   template<> template<>
     void B<int, int>::f<1, 1>(int i, int (&arr1a)[1], int (&arr2a)[1]) {}
 }
@@ -134,10 +143,10 @@ struct C { explicit operator D(); } c;
 B b1(a);
 const B &b2{a}; // FIXME ill-formed
 const B &b3(a);
-// expected-error@-1 {{no viable conversion from 'struct A' to 'const B'}}
-// expected-note@#dr2267-struct-B {{candidate constructor (the implicit copy constructor) not viable: no known conversion from 'struct A' to 'const B &' for 1st argument}}
-// expected-note@#dr2267-struct-B {{candidate constructor (the implicit move constructor) not viable: no known conversion from 'struct A' to 'B &&' for 1st argument}}
-// expected-note@#dr2267-struct-B {{explicit constructor is not a candidate}}
+// since-cxx11-error@-1 {{no viable conversion from 'struct A' to 'const B'}}
+//   since-cxx11-note@#dr2267-struct-B {{candidate constructor (the implicit copy constructor) not viable: no known conversion from 'struct A' to 'const B &' for 1st argument}}
+//   since-cxx11-note@#dr2267-struct-B {{candidate constructor (the implicit move constructor) not viable: no known conversion from 'struct A' to 'B &&' for 1st argument}}
+//   since-cxx11-note@#dr2267-struct-B {{explicit constructor is not a candidate}}
 
 D d1(c);
 const D &d2{c}; // FIXME ill-formed
diff --git a/clang/test/CXX/drs/dr2354.cpp b/clang/test/CXX/drs/dr2354.cpp
deleted file mode 100644
index 3efb0ba55566..000000000000
--- a/clang/test/CXX/drs/dr2354.cpp
+++ /dev/null
@@ -1,10 +0,0 @@
-// RUN: %clang_cc1 -x c++ -verify %s 
-
-// dr2354: 15
-
-namespace DR2354 {
-
-enum alignas(64) A {};        // expected-error {{'alignas' attribute cannot be applied to an enumeration}}
-enum struct alignas(64) B {}; // expected-error {{'alignas' attribute cannot be applied to an enumeration}}
-
-} // namespace DR2354
diff --git a/clang/test/CXX/drs/dr23xx.cpp b/clang/test/CXX/drs/dr23xx.cpp
index 6cb10067739f..9ced61d2aae3 100644
--- a/clang/test/CXX/drs/dr23xx.cpp
+++ b/clang/test/CXX/drs/dr23xx.cpp
@@ -1,9 +1,10 @@
-// RUN: %clang_cc1 -std=c++98 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors 2>&1
-// RUN: %clang_cc1 -std=c++11 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors 2>&1 | FileCheck %s
-// RUN: %clang_cc1 -std=c++14 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors 2>&1 | FileCheck %s
-// RUN: %clang_cc1 -std=c++17 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors 2>&1 | FileCheck %s
-// RUN: %clang_cc1 -std=c++20 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors 2>&1 | FileCheck %s
-// RUN: %clang_cc1 -std=c++23 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors 2>&1 | FileCheck %s
+// RUN: %clang_cc1 -std=c++98 %s -verify=expected -fexceptions -fcxx-exceptions -pedantic-errors 2>&1 | FileCheck %s
+// RUN: %clang_cc1 -std=c++11 %s -verify=expected,since-cxx11 -fexceptions -fcxx-exceptions -pedantic-errors 2>&1 | FileCheck %s
+// RUN: %clang_cc1 -std=c++14 %s -verify=expected,since-cxx11,since-cxx14 -fexceptions -fcxx-exceptions -pedantic-errors 2>&1 | FileCheck %s
+// RUN: %clang_cc1 -std=c++17 %s -verify=expected,since-cxx11,since-cxx14,since-cxx17 -fexceptions -fcxx-exceptions -pedantic-errors 2>&1 | FileCheck %s
+// RUN: %clang_cc1 -std=c++20 %s -verify=expected,since-cxx11,since-cxx14,since-cxx17,since-cxx20 -fexceptions -fcxx-exceptions -pedantic-errors 2>&1 | FileCheck %s
+// RUN: %clang_cc1 -std=c++23 %s -verify=expected,since-cxx11,since-cxx14,since-cxx17,since-cxx20 -fexceptions -fcxx-exceptions -pedantic-errors 2>&1 | FileCheck %s
+// RUN: %clang_cc1 -std=c++2c %s -verify=expected,since-cxx11,since-cxx14,since-cxx17,since-cxx20 -fexceptions -fcxx-exceptions -pedantic-errors 2>&1 | FileCheck %s
 
 #if __cplusplus >= 201103L
 namespace dr2303 { // dr2303: 12
@@ -14,8 +15,14 @@ struct A<> {};
 template <typename T, typename... Ts>
 struct A<T, Ts...> : A<Ts...> {};
 struct B : A<int, int> {};
-struct C : A<int, int>, A<int> {}; // expected-warning {{direct base 'A<int>' is inaccessible}}
-struct D : A<int>, A<int, int> {}; // expected-warning {{direct base 'A<int>' is inaccessible}}
+struct C : A<int, int>, A<int> {};
+/* since-cxx11-warning@-1 {{direct base 'A<int>' is inaccessible due to ambiguity:
+    struct dr2303::C -> A<int, int> -> A<int>
+    struct dr2303::C -> A<int>}} */
+struct D : A<int>, A<int, int> {};
+/* since-cxx11-warning@-1 {{direct base 'A<int>' is inaccessible due to ambiguity:
+    struct dr2303::D -> A<int>
+    struct dr2303::D -> A<int, int> -> A<int>}} */
 struct E : A<int, int> {};
 struct F : B, E {};
 
@@ -32,7 +39,10 @@ void g() {
   f2(&b);
   f(C{});
   f(D{});
-  f(F{}); // expected-error {{ambiguous conversion from derived class}}
+  f(F{});
+  /* since-cxx11-error@-1 {{ambiguous conversion from derived class 'const F' to base class 'const A<int, int>':
+    struct dr2303::F -> B -> A<int, int>
+    struct dr2303::F -> E -> A<int, int>}} */
 }
 } //namespace dr2303
 #endif
@@ -65,8 +75,10 @@ namespace dr2352 { // dr2352: 10
   int *const *const &f2() { return p; }
   int **const &f3() { return p; }
 
-  const int **const &f4() { return p; } // expected-error {{reference to type 'const int **const' could not bind to an lvalue of type 'int **'}}
-  const int *const *&f5() { return p; } // expected-error {{binding reference of type 'const int *const *' to value of type 'int **' not permitted due to incompatible qualifiers}}
+  const int **const &f4() { return p; }
+  // expected-error@-1 {{reference to type 'const int **const' could not bind to an lvalue of type 'int **'}}
+  const int *const *&f5() { return p; }
+  // expected-error@-1 {{binding reference of type 'const int *const *' to value of type 'int **' not permitted due to incompatible qualifiers}}
 
   // FIXME: We permit this as a speculative defect resolution, allowing
   // qualification conversions when forming a glvalue conditional expression.
@@ -76,7 +88,8 @@ namespace dr2352 { // dr2352: 10
   // FIXME: Should we compute the composite pointer type here and produce an
   // lvalue of type 'const int *const * const'?
   const int * const * r;
-  void *y = &(true ? p : r); // expected-error {{rvalue of type 'const int *const *'}}
+  void *y = &(true ? p : r);
+  // expected-error@-1 {{rvalue of type 'const int *const *'}}
 
   // FIXME: We order these as a speculative defect resolution.
   void f(const int * const * const &r);
@@ -124,12 +137,22 @@ namespace dr2353 { // dr2353: 9
 #pragma clang __debug dump not_use_2
 }
 
+namespace dr2354 { // dr2354: 15
+#if __cplusplus >= 201103L
+enum alignas(64) A {};
+// since-cxx11-error@-1 {{'alignas' attribute cannot be applied to an enumeration}}
+enum struct alignas(64) B {};
+// since-cxx11-error@-1 {{'alignas' attribute cannot be applied to an enumeration}}
+#endif
+} // namespace dr2354
+
 #if __cplusplus >= 201402L
 namespace dr2358 { // dr2358: 16
   void f2() {
     int i = 1;
     void g1(int = [xxx=1] { return xxx; }());  // OK
-    void g2(int = [xxx=i] { return xxx; }());  // expected-error {{default argument references local variable 'i' of enclosing function}}
+    void g2(int = [xxx=i] { return xxx; }());
+    // since-cxx14-error@-1 {{default argument references local variable 'i' of enclosing function}}
   }
 }
 #endif
@@ -148,7 +171,7 @@ class C {
 };
 } // namespace dr2370
 
-#if __cplusplus >= 201707L
+#if __cplusplus >= 201702L
 // Otherwise, if the qualified-id std::tuple_size<E> names a complete class
 // type **with a member value**, the expression std::tuple_size<E>::value shall
 // be a well-formed integral constant expression
@@ -165,7 +188,8 @@ template <> struct std::tuple_size<dr2386::Bad2> {
 } // namespace std
 namespace dr2386 {
 void no_value() { auto [x, y] = Bad1(); }
-void wrong_value() { auto [x, y] = Bad2(); } // expected-error {{decomposes into 42 elements}}
+void wrong_value() { auto [x, y] = Bad2(); }
+// since-cxx17-error@-1 {{type 'Bad2' decomposes into 42 elements, but only 2 names were provided}}
 } // namespace dr2386
 #endif
 
@@ -177,7 +201,8 @@ namespace dr2387 { // dr2387: 9
   extern template int a<0>; // ok
 
   template<int> static int b = 0;
-  extern template int b<0>; // expected-error {{internal linkage}}
+  extern template int b<0>;
+  // since-cxx14-error@-1 {{explicit instantiation declaration of 'b<0>' with internal linkage}}
 
   template<int> const int c = 0;
   extern template const int c<0>; // ok, has external linkage despite 'const'
diff --git a/clang/test/CXX/drs/dr2406.cpp b/clang/test/CXX/drs/dr2406.cpp
deleted file mode 100644
index 0ab198e6f149..000000000000
--- a/clang/test/CXX/drs/dr2406.cpp
+++ /dev/null
@@ -1,30 +0,0 @@
-// RUN: %clang_cc1 -x c++ %s  -verify
-
-// dr2406: 5
-
-void fallthrough(int n) {
-  void g(), h(), i();
-  switch (n) {
-  case 1:
-  case 2:
-    g();
-    [[fallthrough]];
-  case 3: // warning on fallthrough discouraged
-    do {
-      [[fallthrough]]; // expected-error {{fallthrough annotation does not directly precede switch label}}
-    } while (false);
-  case 6:
-    do {
-      [[fallthrough]]; // expected-error {{fallthrough annotation does not directly precede switch label}}
-    } while (n);
-  case 7:
-    while (false) {
-      [[fallthrough]]; // expected-error {{fallthrough annotation does not directly precede switch label}}
-    }
-  case 5:
-    h();
-  case 4: // implementation may warn on fallthrough
-    i();
-    [[fallthrough]]; // expected-error {{fallthrough annotation does not directly precede switch label}}
-  }
-}
diff --git a/clang/test/CXX/drs/dr24xx.cpp b/clang/test/CXX/drs/dr24xx.cpp
index 3fd8539be53d..b34ceb420788 100644
--- a/clang/test/CXX/drs/dr24xx.cpp
+++ b/clang/test/CXX/drs/dr24xx.cpp
@@ -1,9 +1,52 @@
-// RUN: %clang_cc1 -std=c++20 %s -verify
-// RUN: %clang_cc1 -std=c++23 %s -verify
+// RUN: %clang_cc1 -std=c++98 %s -verify=expected
+// RUN: %clang_cc1 -std=c++11 %s -verify=expected
+// RUN: %clang_cc1 -std=c++14 %s -verify=expected
+// RUN: %clang_cc1 -std=c++17 %s -verify=expected,since-cxx17
+// RUN: %clang_cc1 -std=c++20 %s -verify=expected,since-cxx17
+// RUN: %clang_cc1 -std=c++23 %s -verify=expected,since-cxx17
+// RUN: %clang_cc1 -std=c++2c %s -verify=expected,since-cxx17
+
+#if __cplusplus <= 201402L
 // expected-no-diagnostics
+#endif
+
+namespace dr2406 { // dr2406: 5
+#if __cplusplus >= 201703L
+void fallthrough(int n) {
+  void g(), h(), i();
+  switch (n) {
+  case 1:
+  case 2:
+    g();
+    [[fallthrough]];
+  case 3: // warning on fallthrough discouraged
+    do {
+      [[fallthrough]];
+      // since-cxx17-error@-1 {{fallthrough annotation does not directly precede switch label}}
+    } while (false);
+  case 6:
+    do {
+      [[fallthrough]];
+      // since-cxx17-error@-1 {{fallthrough annotation does not directly precede switch label}}
+    } while (n);
+  case 7:
+    while (false) {
+      [[fallthrough]];
+      // since-cxx17-error@-1 {{fallthrough annotation does not directly precede switch label}}
+    }
+  case 5:
+    h();
+  case 4: // implementation may warn on fallthrough
+    i();
+    [[fallthrough]];
+    // since-cxx17-error@-1 {{fallthrough annotation does not directly precede switch label}}
+  }
+}
+#endif
+}
 
 namespace dr2450 { // dr2450: 18 drafting
-#if __cplusplus > 202002L
+#if __cplusplus >= 202302L
 struct S {int a;};
 template <S s>
 void f(){}
@@ -17,7 +60,7 @@ f<{.a= 0}>();
 }
 
 namespace dr2459 { // dr2459: 18 drafting
-#if __cplusplus > 202002L
+#if __cplusplus >= 202302L
 struct A {
   constexpr A(float) {}
 };
diff --git a/clang/test/CXX/drs/dr25xx.cpp b/clang/test/CXX/drs/dr25xx.cpp
index 0204ecaf6361..8c34b03c22d5 100644
--- a/clang/test/CXX/drs/dr25xx.cpp
+++ b/clang/test/CXX/drs/dr25xx.cpp
@@ -1,12 +1,12 @@
-// RUN: %clang_cc1 -std=c++98 -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors
-// RUN: %clang_cc1 -std=c++11 -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors
-// RUN: %clang_cc1 -std=c++14 -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors
-// RUN: %clang_cc1 -std=c++17 -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors
-// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors
-// RUN: %clang_cc1 -std=c++23 -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors
-// RUN: %clang_cc1 -std=c++2c -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors
-
-#if __cplusplus < 201103L
+// RUN: %clang_cc1 -std=c++98 -triple x86_64-unknown-unknown %s -verify=expected -fexceptions -fcxx-exceptions -pedantic-errors
+// RUN: %clang_cc1 -std=c++11 -triple x86_64-unknown-unknown %s -verify=expected,cxx11-14,since-cxx11 -fexceptions -fcxx-exceptions -pedantic-errors
+// RUN: %clang_cc1 -std=c++14 -triple x86_64-unknown-unknown %s -verify=expected,cxx11-14,since-cxx11 -fexceptions -fcxx-exceptions -pedantic-errors
+// RUN: %clang_cc1 -std=c++17 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11 -fexceptions -fcxx-exceptions -pedantic-errors
+// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11,since-cxx20 -fexceptions -fcxx-exceptions -pedantic-errors
+// RUN: %clang_cc1 -std=c++23 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11,since-cxx20,since-cxx23 -fexceptions -fcxx-exceptions -pedantic-errors
+// RUN: %clang_cc1 -std=c++2c -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11,since-cxx20,since-cxx23 -fexceptions -fcxx-exceptions -pedantic-errors
+
+#if __cplusplus == 199711L
 // expected-no-diagnostics
 #endif
 
@@ -17,7 +17,7 @@ template <typename T> struct S {
   typedef char I;
 };
 enum E2 : S<E2>::I { e };
-// expected-error@-1 {{use of undeclared identifier 'E2'}}
+// since-cxx11-error@-1 {{use of undeclared identifier 'E2'}}
 #endif
 } // namespace dr2516
 
@@ -27,24 +27,24 @@ namespace dr2518 { // dr2518: 17
 template <class T>
 void f(T t) {
   if constexpr (sizeof(T) != sizeof(int)) {
-#if __cplusplus < 201703L
-// expected-error@-2 {{constexpr if is a C++17 extension}}
-#endif
-    static_assert(false, "must be int-sized"); // expected-error {{must be int-size}}
+  // cxx11-14-error@-1 {{constexpr if is a C++17 extension}}
+    static_assert(false, "must be int-sized");
+    // since-cxx11-error@-1 {{static assertion failed: must be int-sized}}
+    //   since-cxx11-note@#dr2518-f-c {{in instantiation of function template specialization 'dr2518::f<char>' requested here}}
   }
 }
 
 void g(char c) {
   f(0);
-  f(c); // expected-note {{requested here}}
+  f(c); // #dr2518-f-c
 }
 
 template <typename Ty>
 struct S {
-  static_assert(false); // expected-error {{static assertion failed}}
-#if __cplusplus < 201703L
-// expected-error@-2 {{'static_assert' with no message is a C++17 extension}}
-#endif
+  static_assert(false);
+  // cxx11-14-error@-1 {{'static_assert' with no message is a C++17 extension}}
+  // since-cxx11-error@-2 {{static assertion failed}}
+  //   since-cxx11-note@#dr2518-S-double {{in instantiation of template class 'dr2518::S<double>' requested here}}
 };
 
 template <>
@@ -56,7 +56,7 @@ struct S<float> {};
 int test_specialization() {
   S<int> s1;
   S<float> s2;
-  S<double> s3; // expected-note {{in instantiation of template class 'dr2518::S<double>' requested here}}
+  S<double> s3; // #dr2518-S-double
 }
 #endif
 
@@ -67,16 +67,16 @@ namespace dr2521 { // dr2521: 17
 #pragma clang diagnostic push
 #pragma clang diagnostic warning "-Wdeprecated-literal-operator"
 long double operator""      _\u03C0___(long double);
-// expected-warning@-1 {{identifier '_π___' preceded by whitespace in a literal operator declaration is deprecated}}
-// expected-warning@-2 {{user-defined literal suffixes containing '__' are reserved}}
+// since-cxx11-warning@-1 {{identifier '_π___' preceded by whitespace in a literal operator declaration is deprecated}}
+// since-cxx11-warning@-2 {{user-defined literal suffixes containing '__' are reserved}}
 
 template <char... Chars> decltype(sizeof 0)
 operator""  _div();
-// expected-warning@-1 {{identifier '_div' preceded by whitespace in a literal operator declaration is deprecated}}
+// since-cxx11-warning@-1 {{identifier '_div' preceded by whitespace in a literal operator declaration is deprecated}}
 
 using ::dr2521::operator"" _\u03C0___;
 using ::dr2521::operator""_div;
-// expected-warning@-2 {{identifier '_π___' preceded by whitespace in a literal operator declaration is deprecated}}
+// since-cxx11-warning@-2 {{identifier '_π___' preceded by whitespace in a literal operator declaration is deprecated}}
 #pragma clang diagnostic pop
 #endif
 } // namespace dr2521
@@ -85,12 +85,16 @@ using ::dr2521::operator""_div;
 #if __cplusplus >= 202302L
 namespace dr2553 { // dr2553: 18
 struct B {
-  virtual void f(this B&);   // expected-error {{an explicit object parameter cannot appear in a virtual function}}
-  static void f(this B&);   // expected-error {{an explicit object parameter cannot appear in a static function}}
-  virtual void g(); // expected-note {{here}}
+  virtual void f(this B&); 
+  // since-cxx23-error@-1 {{an explicit object parameter cannot appear in a virtual function}}
+  static void f(this B&);
+  // since-cxx23-error@-1 {{an explicit object parameter cannot appear in a static function}}
+  virtual void g(); // #dr2553-g
 };
 struct D : B {
-  void g(this D&); // expected-error {{an explicit object parameter cannot appear in a virtual function}}
+  void g(this D&);
+  // since-cxx23-error@-1 {{an explicit object parameter cannot appear in a virtual function}}
+  //   since-cxx23-note@#dr2553-g {{overridden virtual function is here}}
 };
 
 }
@@ -99,19 +103,25 @@ struct D : B {
 #if __cplusplus >= 202302L
 namespace dr2554 { // dr2554: 18 review
 struct B {
-  virtual void f(); // expected-note 3{{here}}
+  virtual void f(); // #dr2554-g
 };
 
 struct D : B {
-  void f(this D&); // expected-error {{an explicit object parameter cannot appear in a virtual function}}
+  void f(this D&);
+  // since-cxx23-error@-1 {{an explicit object parameter cannot appear in a virtual function}}
+  //   since-cxx23-note@#dr2554-g {{overridden virtual function is here}}
 };
 
 struct D2 : B {
-  void f(this B&); // expected-error {{an explicit object parameter cannot appear in a virtual function}}
+  void f(this B&);
+  // since-cxx23-error@-1 {{an explicit object parameter cannot appear in a virtual function}}
+  //   since-cxx23-note@#dr2554-g {{overridden virtual function is here}}
 };
 struct T {};
 struct D3 : B {
-  void f(this T&); // expected-error {{an explicit object parameter cannot appear in a virtual function}}
+  void f(this T&);
+  // since-cxx23-error@-1 {{an explicit object parameter cannot appear in a virtual function}}
+  //   since-cxx23-note@#dr2554-g {{overridden virtual function is here}}
 };
 
 }
@@ -153,48 +163,48 @@ namespace dr2565 { // dr2565: 16
   static_assert(is_referenceable<int>::value);
 
   template<typename T, typename U>
-  concept TwoParams = requires (T *a, U b){ true;}; // #TPC
+  concept TwoParams = requires (T *a, U b){ true;}; // #dr2565-TPC
 
   template<typename T, typename U>
-    requires TwoParams<T, U> // #TPSREQ
+    requires TwoParams<T, U> // #dr2565-TPSREQ
   struct TwoParamsStruct{};
 
   using TPSU = TwoParamsStruct<void, void>;
-  // expected-error@-1{{constraints not satisfied for class template 'TwoParamsStruct'}}
-  // expected-note@#TPSREQ{{because 'TwoParams<void, void>' evaluated to false}}
-  // expected-note@#TPC{{because 'b' would be invalid: argument may not have 'void' type}}
+  // since-cxx20-error@-1 {{constraints not satisfied for class template 'TwoParamsStruct'}}
+  //   since-cxx20-note@#dr2565-TPSREQ {{because 'TwoParams<void, void>' evaluated to false}}
+  //   since-cxx20-note@#dr2565-TPC {{because 'b' would be invalid: argument may not have 'void' type}}
 
   template<typename T, typename ...U>
-  concept Variadic = requires (U* ... a, T b){ true;}; // #VC
+  concept Variadic = requires (U* ... a, T b){ true;}; // #dr2565-VC
 
   template<typename T, typename ...U>
-    requires Variadic<T, U...> // #VSREQ
+    requires Variadic<T, U...> // #dr2565-VSREQ
   struct VariadicStruct{};
 
   using VSU = VariadicStruct<void, int, char, double>;
-  // expected-error@-1{{constraints not satisfied for class template 'VariadicStruct'}}
-  // expected-note@#VSREQ{{because 'Variadic<void, int, char, double>' evaluated to false}}
-  // expected-note@#VC{{because 'b' would be invalid: argument may not have 'void' type}}
+  // since-cxx20-error@-1 {{constraints not satisfied for class template 'VariadicStruct'}}
+  //   since-cxx20-note@#dr2565-VSREQ {{because 'Variadic<void, int, char, double>' evaluated to false}}
+  //   since-cxx20-note@#dr2565-VC {{because 'b' would be invalid: argument may not have 'void' type}}
 
   template<typename T>
-  // expected-error@+1 {{unknown type name 'ErrorRequires'}}
   concept ErrorRequires = requires (ErrorRequires auto x) {
+  // since-cxx20-error@-1 {{unknown type name 'ErrorRequires'}}
     x;
   };
   static_assert(ErrorRequires<int>);
-  // expected-error@-1{{static assertion failed}}
-  // expected-note@-2{{because substituted constraint expression is ill-formed: constraint depends on a previously diagnosed expression}}
+  // since-cxx20-error@-1 {{static assertion failed}}
+  //   since-cxx20-note@-2 {{because substituted constraint expression is ill-formed: constraint depends on a previously diagnosed expression}}
 
   template<typename T>
-  // expected-error@+2 {{unknown type name 'NestedErrorInRequires'}}
   concept NestedErrorInRequires = requires (T x) {
     requires requires (NestedErrorInRequires auto y) {
+    // since-cxx20-error@-1 {{unknown type name 'NestedErrorInRequires'}}
       y;
     };
   };
   static_assert(NestedErrorInRequires<int>);
-  // expected-error@-1{{static assertion failed}}
-  // expected-note@-2{{because substituted constraint expression is ill-formed: constraint depends on a previously diagnosed expression}}
+  // expected-error@-1 {{static assertion failed}}
+  //   expected-note@-2 {{because substituted constraint expression is ill-formed: constraint depends on a previously diagnosed expression}}
 
 #endif
 }
diff --git a/clang/test/CXX/drs/dr26xx.cpp b/clang/test/CXX/drs/dr26xx.cpp
index 1d702e66bf8c..dd4bb1ff6ae2 100644
--- a/clang/test/CXX/drs/dr26xx.cpp
+++ b/clang/test/CXX/drs/dr26xx.cpp
@@ -1,8 +1,14 @@
-// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-unknown %s -verify
-// RUN: %clang_cc1 -std=c++2b -triple x86_64-unknown-unknown %s -verify
+// RUN: %clang_cc1 -std=c++98 -triple x86_64-unknown-unknown %s -verify=expected
+// RUN: %clang_cc1 -std=c++11 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11,cxx11
+// RUN: %clang_cc1 -std=c++14 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11
+// RUN: %clang_cc1 -std=c++17 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11
+// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11,since-cxx20
+// RUN: %clang_cc1 -std=c++23 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11,since-cxx20,since-cxx23
+// RUN: %clang_cc1 -std=c++2c -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11,since-cxx20,since-cxx23
 
 
 namespace dr2621 { // dr2621: 16
+#if __cplusplus >= 202002L
 enum class E { a };
 namespace One {
 using E_t = E;
@@ -12,33 +18,39 @@ auto v = a;
 namespace Two {
 using dr2621::E;
 int E; // we see this
-using enum E; // expected-error {{unknown type name E}}
+using enum E;
+// since-cxx20-error@-1 {{unknown type name E}}
 }
+#endif
 }
 
 namespace dr2628 { // dr2628: no open
                    // this was reverted for the 16.x release
                    // due to regressions, see the issue for more details:
                    // https://github.com/llvm/llvm-project/issues/60777
-
+#if __cplusplus >= 202002L
 template <bool A = false, bool B = false>
 struct foo {
   // The expected notes below should be removed when dr2628 is fully implemented again
-  constexpr foo() requires (!A && !B) = delete; // expected-note {{candidate function [with A = false, B = false]}} #DR2628_CTOR
-  constexpr foo() requires (A || B) = delete; // expected-note {{candidate function [with A = false, B = false]}}
+  constexpr foo() requires (!A && !B) = delete; // #dr2628-ctor-1
+  constexpr foo() requires (A || B) = delete; //  #dr2628-ctor-2
 };
 
 void f() {
   // The FIXME's below should be the expected errors when dr2628 is
   // fully implemented again.
-  // FIXME-expected-error {{call to deleted}}
-  foo fooable; // expected-error {{ambiguous deduction for template arguments of 'foo'}}
-  // FIXME-expected-note@#DR2628_CTOR {{marked deleted here}}
+  foo fooable; // #dr2628-fooable
+  // since-cxx20-error@-1 {{ambiguous deduction for template arguments of 'foo'}}
+  //   since-cxx20-note@#dr2628-ctor-1 {{candidate function [with A = false, B = false]}}
+  //   since-cxx20-note@#dr2628-ctor-2 {{candidate function [with A = false, B = false]}}
+  // FIXME-since-cxx20-error@#dr2628-fooable {{call to deleted}} 
+  //   FIXME-since-cxx20-note@#dr2628-ctor {{marked deleted here}} 
 }
-
+#endif
 }
 
 namespace dr2631 { // dr2631: 16
+#if __cplusplus >= 202002L
   constexpr int g();
   consteval int f() {
     return g();
@@ -52,9 +64,11 @@ namespace dr2631 { // dr2631: 16
   int test() {
     return k();
   }
+#endif
 }
 
 namespace dr2635 { // dr2635: 16
+#if __cplusplus >= 202002L
 template<typename T>
 concept UnaryC = true;
 template<typename T, typename U>
@@ -67,66 +81,79 @@ template<typename T>
 T get_T();
 
 void use() {
-  // expected-error@+1{{decomposition declaration cannot be declared with constrained 'auto'}}
   UnaryC auto [a, b] = get_S();
-  // expected-error@+1{{decomposition declaration cannot be declared with constrained 'auto'}}
+  // since-cxx20-error@-1 {{decomposition declaration cannot be declared with constrained 'auto'}}
   BinaryC<int> auto [c, d] = get_S();
+  // since-cxx20-error@-1 {{decomposition declaration cannot be declared with constrained 'auto'}}
 }
 
 template<typename T>
 void TemplUse() {
-  // expected-error@+1{{decomposition declaration cannot be declared with constrained 'auto'}}
   UnaryC auto [a, b] = get_T<T>();
-  // expected-error@+1{{decomposition declaration cannot be declared with constrained 'auto'}}
+  // since-cxx20-error@-1 {{decomposition declaration cannot be declared with constrained 'auto'}}
   BinaryC<T> auto [c, d] = get_T<T>();
+  // since-cxx20-error@-1 {{decomposition declaration cannot be declared with constrained 'auto'}}
 }
+#endif
 }
 
-  // dr2636: na
+// dr2636: na
 
 namespace dr2640 { // dr2640: 16
 
-int \N{Λ} = 0; //expected-error {{'Λ' is not a valid Unicode character name}} \
-               //expected-error {{expected unqualified-id}}
-const char* emoji = "\N{🤡}"; // expected-error {{'🤡' is not a valid Unicode character name}} \
-                              // expected-note 5{{did you mean}}
+int \N{Λ} = 0;
+// expected-error@-1 {{'Λ' is not a valid Unicode character name}}
+// expected-error@-2 {{expected unqualified-id}}
+const char* emoji = "\N{🤡}";
+// expected-error@-1 {{'🤡' is not a valid Unicode character name}}
+// expected-note@-2 {{did you mean OX ('🐂' U+1F402)?}}
+// expected-note@-3 {{did you mean ANT ('🐜' U+1F41C)?}}
+// expected-note@-4 {{did you mean ARC ('⌒' U+2312)?}}
+// expected-note@-5 {{did you mean AXE ('🪓' U+1FA93)?}}
+// expected-note@-6 {{did you mean BAT ('🦇' U+1F987)?}}
 
 #define z(x) 0
 #define dr2640_a z(
-int x = dr2640_a\N{abc}); // expected-error {{'abc' is not a valid Unicode character name}}
-int y = dr2640_a\N{LOTUS}); // expected-error {{character <U+1FAB7> not allowed in an identifier}} \
-                     // expected-error {{use of undeclared identifier 'dr2640_a🪷'}} \
-                     // expected-error {{extraneous ')' before ';'}}
+int x = dr2640_a\N{abc});
+// expected-error@-1 {{'abc' is not a valid Unicode character name}}
+int y = dr2640_a\N{LOTUS});
+// expected-error@-1 {{character <U+1FAB7> not allowed in an identifier}}
+// expected-error@-2 {{use of undeclared identifier 'dr2640_a🪷'}}
+// expected-error@-3 {{extraneous ')' before ';'}}
 }
 
-  // dr2642: na
+// dr2642: na
 
 namespace dr2644 { // dr2644: 8
-
-auto z = [a = 42](int a) { // expected-error {{a lambda parameter cannot shadow an explicitly captured entity}} \
-                           // expected-note {{variable 'a' is explicitly captured here}}
+#if __cplusplus >= 201103L
+auto z = [a = 42](int a) {
+// cxx11-warning@-1 {{initialized lambda captures are a C++14 extension}}
+// since-cxx11-error@-2 {{a lambda parameter cannot shadow an explicitly captured entity}}
+//   since-cxx11-note@-3 {{variable 'a' is explicitly captured here}}
      return 1;
 };
-
+#endif
 }
 
 #if __cplusplus >= 202302L
 namespace dr2650 { // dr2650: 17
 template <class T, T> struct S {};
-template <class T> int f(S<T, T{}>*); // expected-note {{type 'X' of non-type template parameter is not a structural type}}
+template <class T> int f(S<T, T{}>*); // #dr2650-f
 class X {
   int m;
 };
-int i0 = f<X>(0);   //expected-error {{no matching function for call to 'f'}}
+int i0 = f<X>(0);
+// since-cxx23-error@-1 {{no matching function for call to 'f'}}
+//   since-cxx23-note@#dr2650-f {{type 'X' of non-type template parameter is not a structural type}}
 }
 #endif
 
 #if __cplusplus >= 202302L
 namespace dr2653 { // dr2653: 18
   struct Test { void f(this const auto& = Test{}); };
-  // expected-error@-1 {{the explicit object parameter cannot have a default argument}}
+  // since-cxx23-error@-1 {{the explicit object parameter cannot have a default argument}}
   auto L = [](this const auto& = Test{}){};
-  // expected-error@-1 {{the explicit object parameter cannot have a default argument}}
+  // since-cxx23-error@-1 {{the explicit object parameter cannot have a default argument}}
 }
 #endif
 
@@ -141,6 +168,7 @@ void f() {
 }
 
 namespace dr2681 { // dr2681: 17
+#if __cplusplus >= 202002L
 using size_t = decltype(sizeof(int));
 
 template<class T, size_t N>
@@ -152,7 +180,7 @@ struct I {
   volatile T array[N];
 };
 template<size_t N>
-struct J {  // expected-note 3{{candidate}}
+struct J { // #dr2681-J
   unsigned char array[N];
 };
 
@@ -161,15 +189,24 @@ I i = { "def" };
 static_assert(__is_same(decltype(h), H<char, 4>));  // Not H<const char, 4>
 static_assert(__is_same(decltype(i), I<char, 4>));
 
-J j = { "ghi" };  // expected-error {{no viable constructor or deduction guide}}
+J j = { "ghi" };
+// since-cxx20-error@-1 {{no viable constructor or deduction guide}}
+//   since-cxx20-note@#dr2681-J {{candidate template ignored: could not match 'J<N>' against 'const char *'}}
+//   since-cxx20-note@#dr2681-J {{candidate template ignored: could not match 'const unsigned char' against 'const char'}}
+//   since-cxx20-note@#dr2681-J {{candidate function template not viable: requires 0 arguments, but 1 was provided}}
+#endif
 }
 
 namespace dr2672 { // dr2672: 18 open
+#if __cplusplus >= 202002L
 template <class T>
-void f(T) requires requires { []() { T::invalid; } (); }; // expected-error{{type 'int' cannot be used prior to '::'}}
-                                                          // expected-note@-1{{while substituting into a lambda expression here}}
-                                                          // expected-note@-2{{in instantiation of requirement here}}
-                                                          // expected-note@-3{{while substituting template arguments into constraint expression here}}
+void f(T) requires requires { []() { T::invalid; } (); };
+// since-cxx20-error@-1 {{type 'int' cannot be used prior to '::' because it has no members}}
+//   since-cxx20-note@-2 {{while substituting into a lambda expression here}}
+//   since-cxx20-note@-3 {{in instantiation of requirement here}}
+//   since-cxx20-note@-4 {{while substituting template arguments into constraint expression here}}
+//   since-cxx20-note@#dr2672-f-0 {{while checking constraint satisfaction for template 'f<int>' required here}}
+//   since-cxx20-note@#dr2672-f-0 {{in instantiation of function template specialization 'dr2672::f<int>' requested here}}
 void f(...);
 
 template <class T>
@@ -179,11 +216,12 @@ void bar(T) requires requires {
 void bar(...);
 
 void m() {
-  f(0); // expected-note {{while checking constraint satisfaction for template 'f<int>' required here}}
-        // expected-note@-1 {{in instantiation of function template specialization}}
+  f(0); // #dr2672-f-0
   bar(0);
 }
+#endif
 }
+
 #if __cplusplus >= 202302L
 namespace dr2687 { // dr2687: 18
 struct S{
@@ -193,7 +231,8 @@ struct S{
 };
 
 void test() {
-    (&S::f)(1); // expected-error {{called object type 'void (dr2687::S::*)(int)' is not a function or function pointer}}
+    (&S::f)(1);
+    // since-cxx23-error@-1 {{called object type 'void (dr2687::S::*)(int)' is not a function or function pointer}}
     (&S::g)(1);
     (&S::h)(S(), 1);
 }
diff --git a/clang/test/CXX/drs/dr27xx.cpp b/clang/test/CXX/drs/dr27xx.cpp
index 5c7ce98f878d..4f7d0d6b44a8 100644
--- a/clang/test/CXX/drs/dr27xx.cpp
+++ b/clang/test/CXX/drs/dr27xx.cpp
@@ -1,6 +1,17 @@
-// RUN: %clang_cc1 -std=c++2c -verify %s
+// RUN: %clang_cc1 -std=c++98 -verify=expected %s
+// RUN: %clang_cc1 -std=c++11 -verify=expected %s
+// RUN: %clang_cc1 -std=c++14 -verify=expected %s
+// RUN: %clang_cc1 -std=c++17 -verify=expected %s
+// RUN: %clang_cc1 -std=c++20 -verify=expected %s
+// RUN: %clang_cc1 -std=c++23 -verify=expected,since-cxx23 %s
+// RUN: %clang_cc1 -std=c++2c -verify=expected,since-cxx23,since-cxx26 %s
+
+#if __cplusplus <= 202002L
+// expected-no-diagnostics
+#endif
 
 namespace dr2789 { // dr2789: 18 open
+#if __cplusplus >= 202302L
 template <typename T = int>
 struct Base {
     constexpr void g(); // #dr2789-g1
@@ -23,11 +34,12 @@ struct S : Base<T>, Base2<T> {
 void test() {
     S<> s;
     s.f();
-    s.g(); // expected-error {{call to member function 'g' is ambiguous}}
-           // expected-note@#dr2789-g1 {{candidate function}}
-           // expected-note@#dr2789-g2 {{candidate function}}
+    s.g();
+    // since-cxx23-error@-1 {{call to member function 'g' is ambiguous}}
+    //   since-cxx23-note@#dr2789-g1 {{candidate function}}
+    //   since-cxx23-note@#dr2789-g2 {{candidate function}}
 }
-
+#endif
 }
 
 namespace dr2798 { // dr2798: 17 drafting
@@ -49,7 +61,8 @@ struct X {
 };
 consteval X f() { return {}; }
 
-static_assert(false, f().s); // expected-error {{static assertion failed: Hello}}
+static_assert(false, f().s);
+// since-cxx26-error@-1 {{static assertion failed: Hello}}
 #endif
 } // namespace dr2798
 
-- 
GitLab


From b3000ecb3c165b7b14d997ee4ae96feed4e5e767 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad@amd.com>
Date: Sat, 9 Dec 2023 10:12:32 +0000
Subject: [PATCH 018/349] [SelectionDAG] Fix typo in comment

---
 llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index ed1c96a87374..4fd76d012a16 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -7123,7 +7123,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
         EVT::getIntegerVT(*Context, 8), MachinePointerInfo(I.getArgOperand(0)),
         /* align */ std::nullopt, Flags);
 
-    // Chain the prefetch in parallell with any pending loads, to stay out of
+    // Chain the prefetch in parallel with any pending loads, to stay out of
     // the way of later optimizations.
     PendingLoads.push_back(Result);
     Result = getRoot();
-- 
GitLab


From b3e6ff331925dde24a4707452d657da0fdf7f588 Mon Sep 17 00:00:00 2001
From: Richard Dzenis <dzenis@richard.lv>
Date: Sat, 9 Dec 2023 12:35:38 +0200
Subject: [PATCH 019/349] [clang-cl] Add support for [[msvc::constexpr]] C++11
 attribute (#71300)

This commit introduces support for the MSVC-specific C++11-style
attribute `[[msvc::constexpr]]`, which was introduced in MSVC 14.33.
The semantics of this attribute are enabled only under
MSVC compatibility (`-fms-compatibility-version`) 14.33 and higher.
Additionally, the default value of `_MSC_VER` has been raised to 1433.

The current implementation lacks support for:
- `[[msvc::constexpr]]` constructors (see #72149);
  at the time of this implementation, such support would have required
  an unreasonable number of changes in Clang.
- `[[msvc::constexpr]] return ::new` (constexpr placement new) from
  non-std namespaces (see #74924).

Relevant to: #57696
---
 clang/docs/ReleaseNotes.rst                   |  2 +
 clang/docs/UsersManual.rst                    |  4 +-
 clang/include/clang/Basic/Attr.td             |  8 +++
 clang/include/clang/Basic/AttrDocs.td         | 15 ++++++
 .../clang/Basic/DiagnosticSemaKinds.td        |  2 +
 clang/include/clang/Basic/LangOptions.h       |  1 +
 clang/lib/AST/ExprConstant.cpp                | 34 +++++++++---
 clang/lib/Basic/Targets/OSTargets.cpp         |  3 ++
 clang/lib/Driver/ToolChains/MSVC.cpp          |  4 +-
 clang/lib/Sema/SemaDecl.cpp                   |  4 +-
 clang/lib/Sema/SemaDeclAttr.cpp               | 25 +++++++++
 clang/lib/Sema/SemaStmtAttr.cpp               | 12 +++++
 clang/test/AST/ms-constexpr.cpp               | 28 ++++++++++
 clang/test/Driver/cl-options.c                |  4 +-
 ...a-attribute-supported-attributes-list.test |  1 +
 clang/test/SemaCXX/ms-constexpr-invalid.cpp   | 52 +++++++++++++++++++
 clang/test/SemaCXX/ms-constexpr-new.cpp       | 16 ++++++
 clang/test/SemaCXX/ms-constexpr.cpp           | 37 +++++++++++++
 18 files changed, 239 insertions(+), 13 deletions(-)
 create mode 100644 clang/test/AST/ms-constexpr.cpp
 create mode 100644 clang/test/SemaCXX/ms-constexpr-invalid.cpp
 create mode 100644 clang/test/SemaCXX/ms-constexpr-new.cpp
 create mode 100644 clang/test/SemaCXX/ms-constexpr.cpp

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 28f9393e2843..b4b5352a306c 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -238,6 +238,8 @@ Non-comprehensive list of changes in this release
   except that it returns the size of a type ignoring tail padding.
 * ``__builtin_classify_type()`` now classifies ``_BitInt`` values as the return value ``18``
   and vector types as return value ``19``, to match GCC 14's behavior.
+* The default value of `_MSC_VER` was raised from 1920 to 1933.
+* Since MSVC 19.33 added undocumented attribute ``[[msvc::constexpr]]``, this release adds the attribute as well.
 
 * Added ``#pragma clang fp reciprocal``.
 
diff --git a/clang/docs/UsersManual.rst b/clang/docs/UsersManual.rst
index 9d64195ee338..f1b344ef5109 100644
--- a/clang/docs/UsersManual.rst
+++ b/clang/docs/UsersManual.rst
@@ -3359,8 +3359,8 @@ default for Windows targets.
 
 For compatibility with existing code that compiles with MSVC, clang defines the
 ``_MSC_VER`` and ``_MSC_FULL_VER`` macros. When on Windows, these default to
-either the same value as the currently installed version of cl.exe, or ``1920``
-and ``192000000`` (respectively). The ``-fms-compatibility-version=`` flag
+either the same value as the currently installed version of cl.exe, or ``1933``
+and ``193300000`` (respectively). The ``-fms-compatibility-version=`` flag
 overrides these values.  It accepts a dotted version tuple, such as 19.00.23506.
 Changing the MSVC compatibility version makes clang behave more like that
 version of MSVC. For example, ``-fms-compatibility-version=19`` will enable
diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td
index 121ed203829c..b0a8ef10c500 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -3646,6 +3646,14 @@ def : MutualExclusions<[Owner, Pointer]>;
 
 // Microsoft-related attributes
 
+def MSConstexpr : InheritableAttr {
+  let LangOpts = [MicrosoftExt];
+  let Spellings = [CXX11<"msvc", "constexpr">];
+  let Subjects = SubjectList<[Function, ReturnStmt], ErrorDiag,
+                             "functions and return statements">;
+  let Documentation = [MSConstexprDocs];
+}
+
 def MSNoVTable : InheritableAttr, TargetSpecificAttr<TargetMicrosoftCXXABI> {
   let Spellings = [Declspec<"novtable">];
   let Subjects = SubjectList<[CXXRecord]>;
diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td
index 88f7c65e6e84..1a98196834ce 100644
--- a/clang/include/clang/Basic/AttrDocs.td
+++ b/clang/include/clang/Basic/AttrDocs.td
@@ -3657,6 +3657,21 @@ an error:
 }];
 }
 
+def MSConstexprDocs : Documentation {
+  let Category = DocCatStmt;
+  let Content = [{
+The ``[[msvc::constexpr]]`` attribute can be applied only to a function
+definition or a ``return`` statement. It does not impact function declarations.
+A ``[[msvc::constexpr]]`` function cannot be ``constexpr`` or ``consteval``.
+A ``[[msvc::constexpr]]`` function is treated as if it were a ``constexpr`` function
+when it is evaluated in a constant context of ``[[msvc::constexpr]] return`` statement.
+Otherwise, it is treated as a regular function.
+
+Semantics of this attribute are enabled only under MSVC compatibility
+(``-fms-compatibility-version``) 19.33 and later.
+  }];
+}
+
 def MSNoVTableDocs : Documentation {
   let Category = DocCatDecl;
   let Content = [{
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index ea08fa84d022..28d95ca9b138 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -2884,6 +2884,8 @@ def warn_cxx11_compat_constexpr_body_multiple_return : Warning<
   InGroup<CXXPre14Compat>, DefaultIgnore;
 def note_constexpr_body_previous_return : Note<
   "previous return statement is here">;
+def err_ms_constexpr_cannot_be_applied : Error<
+  "attribute 'msvc::constexpr' cannot be applied to the %select{constexpr|consteval|virtual}0 function %1">;
 
 // C++20 function try blocks in constexpr
 def ext_constexpr_function_try_block_cxx20 : ExtWarn<
diff --git a/clang/include/clang/Basic/LangOptions.h b/clang/include/clang/Basic/LangOptions.h
index 2d167dd2bdf1..c4979b9a38c0 100644
--- a/clang/include/clang/Basic/LangOptions.h
+++ b/clang/include/clang/Basic/LangOptions.h
@@ -152,6 +152,7 @@ public:
     MSVC2019 = 1920,
     MSVC2019_5 = 1925,
     MSVC2019_8 = 1928,
+    MSVC2022_3 = 1933,
   };
 
   enum SYCLMajorVersion {
diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp
index 986302e1fd22..9bef70770a54 100644
--- a/clang/lib/AST/ExprConstant.cpp
+++ b/clang/lib/AST/ExprConstant.cpp
@@ -641,6 +641,10 @@ namespace {
       return false;
     }
 
+    /// Whether we're in a context where [[msvc::constexpr]] evaluation is
+    /// permitted. See MSConstexprDocs for description of permitted contexts.
+    bool CanEvalMSConstexpr = false;
+
   private:
     APValue &createLocal(APValue::LValueBase Base, const void *Key, QualType T,
                          ScopeKind Scope);
@@ -674,6 +678,19 @@ namespace {
   private:
     llvm::TimeTraceScope TimeScope;
   };
+
+  /// RAII object used to change the current ability of
+  /// [[msvc::constexpr]] evaulation.
+  struct MSConstexprContextRAII {
+    CallStackFrame &Frame;
+    bool OldValue;
+    explicit MSConstexprContextRAII(CallStackFrame &Frame, bool Value)
+        : Frame(Frame), OldValue(Frame.CanEvalMSConstexpr) {
+      Frame.CanEvalMSConstexpr = Value;
+    }
+
+    ~MSConstexprContextRAII() { Frame.CanEvalMSConstexpr = OldValue; }
+  };
 }
 
 static bool HandleDestruction(EvalInfo &Info, const Expr *E,
@@ -5546,11 +5563,14 @@ static EvalStmtResult EvaluateStmt(StmtResult &Result, EvalInfo &Info,
   case Stmt::LabelStmtClass:
     return EvaluateStmt(Result, Info, cast<LabelStmt>(S)->getSubStmt(), Case);
 
-  case Stmt::AttributedStmtClass:
-    // As a general principle, C++11 attributes can be ignored without
-    // any semantic impact.
-    return EvaluateStmt(Result, Info, cast<AttributedStmt>(S)->getSubStmt(),
-                        Case);
+  case Stmt::AttributedStmtClass: {
+    const auto *AS = cast<AttributedStmt>(S);
+    const auto *SS = AS->getSubStmt();
+    MSConstexprContextRAII ConstexprContext(
+        *Info.CurrentCall, hasSpecificAttr<MSConstexprAttr>(AS->getAttrs()) &&
+                               isa<ReturnStmt>(SS));
+    return EvaluateStmt(Result, Info, SS, Case);
+  }
 
   case Stmt::CaseStmtClass:
   case Stmt::DefaultStmtClass:
@@ -5621,7 +5641,9 @@ static bool CheckConstexprFunction(EvalInfo &Info, SourceLocation CallLoc,
   }
 
   // Can we evaluate this function call?
-  if (Definition && Definition->isConstexpr() && Body)
+  if (Definition && Body &&
+      (Definition->isConstexpr() || Info.CurrentCall->CanEvalMSConstexpr &&
+                                        Definition->hasAttr<MSConstexprAttr>()))
     return true;
 
   if (Info.getLangOpts().CPlusPlus11) {
diff --git a/clang/lib/Basic/Targets/OSTargets.cpp b/clang/lib/Basic/Targets/OSTargets.cpp
index 627bc912fa23..899aefa6173a 100644
--- a/clang/lib/Basic/Targets/OSTargets.cpp
+++ b/clang/lib/Basic/Targets/OSTargets.cpp
@@ -224,6 +224,9 @@ static void addVisualCDefines(const LangOptions &Opts, MacroBuilder &Builder) {
       else if (Opts.CPlusPlus14)
         Builder.defineMacro("_MSVC_LANG", "201402L");
     }
+
+    if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2022_3))
+      Builder.defineMacro("_MSVC_CONSTEXPR_ATTRIBUTE");
   }
 
   if (Opts.MicrosoftExt) {
diff --git a/clang/lib/Driver/ToolChains/MSVC.cpp b/clang/lib/Driver/ToolChains/MSVC.cpp
index 8a4a174c90ea..6d925555b7bb 100644
--- a/clang/lib/Driver/ToolChains/MSVC.cpp
+++ b/clang/lib/Driver/ToolChains/MSVC.cpp
@@ -787,11 +787,11 @@ VersionTuple MSVCToolChain::computeMSVCVersion(const Driver *D,
   if (MSVT.empty() &&
       Args.hasFlag(options::OPT_fms_extensions, options::OPT_fno_ms_extensions,
                    IsWindowsMSVC)) {
-    // -fms-compatibility-version=19.20 is default, aka 2019, 16.x
+    // -fms-compatibility-version=19.33 is default, aka 2022, 17.3
     // NOTE: when changing this value, also update
     // clang/docs/CommandGuide/clang.rst and clang/docs/UsersManual.rst
     // accordingly.
-    MSVT = VersionTuple(19, 20);
+    MSVT = VersionTuple(19, 33);
   }
   return MSVT;
 }
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index 7650589608c5..19d972ed8ab2 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -16221,7 +16221,9 @@ Decl *Sema::ActOnFinishFunctionBody(Decl *dcl, Stmt *Body,
         ActivePolicy = &WP;
       }
 
-      if (!IsInstantiation && FD && FD->isConstexpr() && !FD->isInvalidDecl() &&
+      if (!IsInstantiation && FD &&
+          (FD->isConstexpr() || FD->hasAttr<MSConstexprAttr>()) &&
+          !FD->isInvalidDecl() &&
           !CheckConstexprFunctionDefinition(FD, CheckConstexprKind::Diagnose))
         FD->setInvalidDecl();
 
diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp
index a345978bb870..59e456fd9f72 100644
--- a/clang/lib/Sema/SemaDeclAttr.cpp
+++ b/clang/lib/Sema/SemaDeclAttr.cpp
@@ -7372,6 +7372,28 @@ static void handleDeclspecThreadAttr(Sema &S, Decl *D, const ParsedAttr &AL) {
   D->addAttr(::new (S.Context) ThreadAttr(S.Context, AL));
 }
 
+static void handleMSConstexprAttr(Sema &S, Decl *D, const ParsedAttr &AL) {
+  if (!S.getLangOpts().isCompatibleWithMSVC(LangOptions::MSVC2022_3)) {
+    S.Diag(AL.getLoc(), diag::warn_unknown_attribute_ignored)
+        << AL << AL.getRange();
+    return;
+  }
+  auto *FD = cast<FunctionDecl>(D);
+  if (FD->isConstexprSpecified() || FD->isConsteval()) {
+    S.Diag(AL.getLoc(), diag::err_ms_constexpr_cannot_be_applied)
+        << FD->isConsteval() << FD;
+    return;
+  }
+  if (auto *MD = dyn_cast<CXXMethodDecl>(FD)) {
+    if (!S.getLangOpts().CPlusPlus20 && MD->isVirtual()) {
+      S.Diag(AL.getLoc(), diag::err_ms_constexpr_cannot_be_applied)
+          << /*virtual*/ 2 << MD;
+      return;
+    }
+  }
+  D->addAttr(::new (S.Context) MSConstexprAttr(S.Context, AL));
+}
+
 static void handleAbiTagAttr(Sema &S, Decl *D, const ParsedAttr &AL) {
   SmallVector<StringRef, 4> Tags;
   for (unsigned I = 0, E = AL.getNumArgs(); I != E; ++I) {
@@ -9477,6 +9499,9 @@ ProcessDeclAttribute(Sema &S, Scope *scope, Decl *D, const ParsedAttr &AL,
   case ParsedAttr::AT_Thread:
     handleDeclspecThreadAttr(S, D, AL);
     break;
+  case ParsedAttr::AT_MSConstexpr:
+    handleMSConstexprAttr(S, D, AL);
+    break;
 
   // HLSL attributes:
   case ParsedAttr::AT_HLSLNumThreads:
diff --git a/clang/lib/Sema/SemaStmtAttr.cpp b/clang/lib/Sema/SemaStmtAttr.cpp
index eae1eaa2f956..725d8efe3828 100644
--- a/clang/lib/Sema/SemaStmtAttr.cpp
+++ b/clang/lib/Sema/SemaStmtAttr.cpp
@@ -397,6 +397,16 @@ static void CheckForDuplicateCodeAlignAttrs(Sema &S,
   }
 }
 
+static Attr *handleMSConstexprAttr(Sema &S, Stmt *St, const ParsedAttr &A,
+                                   SourceRange Range) {
+  if (!S.getLangOpts().isCompatibleWithMSVC(LangOptions::MSVC2022_3)) {
+    S.Diag(A.getLoc(), diag::warn_unknown_attribute_ignored)
+        << A << A.getRange();
+    return nullptr;
+  }
+  return ::new (S.Context) MSConstexprAttr(S.Context, A);
+}
+
 #define WANT_STMT_MERGE_LOGIC
 #include "clang/Sema/AttrParsedAttrImpl.inc"
 #undef WANT_STMT_MERGE_LOGIC
@@ -600,6 +610,8 @@ static Attr *ProcessStmtAttribute(Sema &S, Stmt *St, const ParsedAttr &A,
     return handleUnlikely(S, St, A, Range);
   case ParsedAttr::AT_CodeAlign:
     return handleCodeAlignAttr(S, St, A);
+  case ParsedAttr::AT_MSConstexpr:
+    return handleMSConstexprAttr(S, St, A, Range);
   default:
     // N.B., ClangAttrEmitter.cpp emits a diagnostic helper that ensures a
     // declaration attribute is not written on a statement, but this code is
diff --git a/clang/test/AST/ms-constexpr.cpp b/clang/test/AST/ms-constexpr.cpp
new file mode 100644
index 000000000000..e85af8494f33
--- /dev/null
+++ b/clang/test/AST/ms-constexpr.cpp
@@ -0,0 +1,28 @@
+// RUN: %clang_cc1 -fms-compatibility -fms-compatibility-version=19.33 -std=c++20 -ast-dump -verify %s | FileCheck %s
+// expected-no-diagnostics
+
+// CHECK: used f1 'bool ()'
+// CHECK: MSConstexprAttr 0x{{[0-9a-f]+}} <col:3, col:9>
+[[msvc::constexpr]] bool f1() { return true; }
+
+// CHECK: used constexpr f2 'bool ()'
+// CHECK-NEXT: CompoundStmt 0x{{[0-9a-f]+}} <col:21, col:56>
+// CHECK-NEXT: AttributedStmt 0x{{[0-9a-f]+}} <col:23, col:53>
+// CHECK-NEXT: MSConstexprAttr 0x{{[0-9a-f]+}} <col:25, col:31>
+// CHECK-NEXT: ReturnStmt 0x{{[0-9a-f]+}} <col:43, col:53>
+constexpr bool f2() { [[msvc::constexpr]] return f1(); }
+static_assert(f2());
+
+struct S1 {
+    // CHECK: used vm 'bool ()' virtual
+    // CHECK: MSConstexprAttr 0x{{[0-9a-f]+}} <col:7, col:13>
+    [[msvc::constexpr]] virtual bool vm() { return true; }
+
+    // CHECK: used constexpr cm 'bool ()'
+    // CHECK-NEXT: CompoundStmt 0x{{[0-9a-f]+}} <col:25, col:60>
+    // CHECK-NEXT: AttributedStmt 0x{{[0-9a-f]+}} <col:27, col:57>
+    // CHECK-NEXT: MSConstexprAttr 0x{{[0-9a-f]+}} <col:29, col:35>
+    // CHECK-NEXT: ReturnStmt 0x{{[0-9a-f]+}} <col:47, col:57>
+    constexpr bool cm() { [[msvc::constexpr]] return vm(); }
+};
+static_assert(S1{}.cm());
diff --git a/clang/test/Driver/cl-options.c b/clang/test/Driver/cl-options.c
index 6d929b19e7e2..81d1b907eced 100644
--- a/clang/test/Driver/cl-options.c
+++ b/clang/test/Driver/cl-options.c
@@ -747,7 +747,7 @@
 
 // Validate that the default triple is used when run an empty tools dir is specified
 // RUN: %clang_cl -vctoolsdir "" -### -- %s 2>&1 | FileCheck %s --check-prefix VCTOOLSDIR
-// VCTOOLSDIR: "-triple" "{{[a-zA-Z0-9_-]*}}-pc-windows-msvc19.20.0"
+// VCTOOLSDIR: "-triple" "{{[a-zA-Z0-9_-]*}}-pc-windows-msvc19.33.0"
 
 // Validate that built-in include paths are based on the supplied path
 // RUN: %clang_cl --target=aarch64-pc-windows-msvc -vctoolsdir "/fake" -winsdkdir "/foo" -winsdkversion 10.0.12345.0 -### -- %s 2>&1 | FileCheck %s --check-prefix FAKEDIR
@@ -787,7 +787,7 @@
 
 // RUN: %clang_cl -vctoolsdir "" /arm64EC /c -### -- %s 2>&1 | FileCheck --check-prefix=ARM64EC %s 
 // ARM64EC-NOT: /arm64EC has been overridden by specified target
-// ARM64EC: "-triple" "arm64ec-pc-windows-msvc19.20.0"
+// ARM64EC: "-triple" "arm64ec-pc-windows-msvc19.33.0"
 
 // RUN: %clang_cl -vctoolsdir "" /arm64EC /c -target x86_64-pc-windows-msvc  -### -- %s 2>&1 | FileCheck --check-prefix=ARM64EC_OVERRIDE %s
 // ARM64EC_OVERRIDE: warning: /arm64EC has been overridden by specified target: x86_64-pc-windows-msvc; option ignored
diff --git a/clang/test/Misc/pragma-attribute-supported-attributes-list.test b/clang/test/Misc/pragma-attribute-supported-attributes-list.test
index 707fc8875089..bdfda430eea8 100644
--- a/clang/test/Misc/pragma-attribute-supported-attributes-list.test
+++ b/clang/test/Misc/pragma-attribute-supported-attributes-list.test
@@ -90,6 +90,7 @@
 // CHECK-NEXT: LoaderUninitialized (SubjectMatchRule_variable_is_global)
 // CHECK-NEXT: Lockable (SubjectMatchRule_record)
 // CHECK-NEXT: MIGServerRoutine (SubjectMatchRule_function, SubjectMatchRule_objc_method, SubjectMatchRule_block)
+// CHECK-NEXT: MSConstexpr (SubjectMatchRule_function)
 // CHECK-NEXT: MSStruct (SubjectMatchRule_record)
 // CHECK-NEXT: MaybeUndef (SubjectMatchRule_variable_is_parameter)
 // CHECK-NEXT: MicroMips (SubjectMatchRule_function)
diff --git a/clang/test/SemaCXX/ms-constexpr-invalid.cpp b/clang/test/SemaCXX/ms-constexpr-invalid.cpp
new file mode 100644
index 000000000000..e5bec0c7119b
--- /dev/null
+++ b/clang/test/SemaCXX/ms-constexpr-invalid.cpp
@@ -0,0 +1,52 @@
+// RUN: %clang_cc1 -fms-compatibility -fms-compatibility-version=19.33 -std=c++20 -verify %s
+// RUN: %clang_cc1 -fms-compatibility -fms-compatibility-version=19.33 -std=c++17 -verify %s
+
+// Check explicitly invalid code
+
+void runtime() {} // expected-note {{declared here}}
+
+[[msvc::constexpr]] void f0() { runtime(); } // expected-error {{constexpr function never produces a constant expression}} \
+                                             // expected-note {{non-constexpr function 'runtime' cannot be used in a constant expression}}
+[[msvc::constexpr]] constexpr void f1() {} // expected-error {{attribute 'msvc::constexpr' cannot be applied to the constexpr function 'f1'}}
+#if __cplusplus >= 202202L
+[[msvc::constexpr]] consteval void f2() {} // expected-error {{attribute 'msvc::constexpr' cannot be applied to the consteval function 'f1'}}
+#endif
+
+struct B1 {};
+struct D1 : virtual B1 { // expected-note {{virtual base class declared here}}
+    [[msvc::constexpr]] D1() {} // expected-error {{constexpr constructor not allowed in struct with virtual base class}}
+};
+
+struct [[msvc::constexpr]] S2{}; // expected-error {{'constexpr' attribute only applies to functions and return statements}}
+
+// Check invalid code mixed with valid code
+
+[[msvc::constexpr]] int f4(int x) { return x > 1 ? 1 + f4(x / 2) : 0; } // expected-note {{non-constexpr function 'f4' cannot be used in a constant expression}} \
+                                                                        // expected-note {{declared here}} \
+                                                                        // expected-note {{declared here}} \
+                                                                        // expected-note {{declared here}}
+constexpr bool f5() { [[msvc::constexpr]] return f4(32) == 5; } // expected-note {{in call to 'f4(32)'}}
+static_assert(f5()); // expected-error {{static assertion expression is not an integral constant expression}} \
+                     // expected-note {{in call to 'f5()'}}
+
+int f6(int x) { [[msvc::constexpr]] return x > 1 ? 1 + f6(x / 2) : 0; } // expected-note {{declared here}} \
+                                                                        // expected-note {{declared here}}
+constexpr bool f7() { [[msvc::constexpr]] return f6(32) == 5; } // expected-error {{constexpr function never produces a constant expression}} \
+                                                                // expected-note {{non-constexpr function 'f6' cannot be used in a constant expression}} \
+                                                                // expected-note {{non-constexpr function 'f6' cannot be used in a constant expression}}
+static_assert(f7()); // expected-error {{static assertion expression is not an integral constant expression}} \
+                     // expected-note {{in call to 'f7()'}}
+
+constexpr bool f8() { // expected-error {{constexpr function never produces a constant expression}}
+    [[msvc::constexpr]] f4(32); // expected-error {{'constexpr' attribute only applies to functions and return statements}} \
+                                // expected-note {{non-constexpr function 'f4' cannot be used in a constant expression}} \
+                                // expected-note {{non-constexpr function 'f4' cannot be used in a constant expression}}
+    [[msvc::constexpr]] int i5 = f4(32); // expected-error {{'constexpr' attribute only applies to functions and return statements}}
+    return i5 == 5;
+}
+static_assert(f8()); // expected-error {{static assertion expression is not an integral constant expression}} \
+                     // expected-note {{in call to 'f8()'}}
+
+#if __cplusplus == 201702L
+struct S1 { [[msvc::constexpr]] virtual bool vm() const { return true; } }; // expected-error {{attribute 'msvc::constexpr' ignored, it only applies to function definitions and return statements}}
+#endif
diff --git a/clang/test/SemaCXX/ms-constexpr-new.cpp b/clang/test/SemaCXX/ms-constexpr-new.cpp
new file mode 100644
index 000000000000..05ee5c5b4e15
--- /dev/null
+++ b/clang/test/SemaCXX/ms-constexpr-new.cpp
@@ -0,0 +1,16 @@
+// RUN: %clang_cc1 -fms-compatibility -fms-compatibility-version=19.33 -std=c++20 -verify=supported %s
+// RUN: %clang_cc1 -fms-compatibility -fms-compatibility-version=19.32 -std=c++20 -verify=unsupported %s
+// supported-no-diagnostics
+
+[[nodiscard]]
+[[msvc::constexpr]] // unsupported-warning {{unknown attribute 'constexpr' ignored}}
+inline void* __cdecl operator new(decltype(sizeof(void*)), void* p) noexcept { return p; }
+
+namespace std {
+  constexpr int* construct_at(int* p, int v) {
+    [[msvc::constexpr]] return ::new (p) int(v); // unsupported-warning {{unknown attribute 'constexpr' ignored}}
+  }
+}
+
+constexpr bool check_construct_at() { int x; return *std::construct_at(&x, 42) == 42; }
+static_assert(check_construct_at());
diff --git a/clang/test/SemaCXX/ms-constexpr.cpp b/clang/test/SemaCXX/ms-constexpr.cpp
new file mode 100644
index 000000000000..79f71a34cb7d
--- /dev/null
+++ b/clang/test/SemaCXX/ms-constexpr.cpp
@@ -0,0 +1,37 @@
+// RUN: %clang_cc1 -fms-compatibility -fms-compatibility-version=19.33 -std=c++20 -verify %s
+
+[[msvc::constexpr]] int log2(int x) { [[msvc::constexpr]] return x > 1 ? 1 + log2(x / 2) : 0; }
+constexpr bool test_log2() { [[msvc::constexpr]] return log2(32) == 5; }
+static_assert(test_log2());
+
+[[msvc::constexpr]] int get_value(int x)
+{
+  switch (x)
+  {
+    case 42: return 1337;
+    default:
+             if (x < 0) [[msvc::constexpr]] return log2(-x);
+             else return x;
+  }
+}
+
+constexpr bool test_complex_expr() {
+  [[msvc::constexpr]] return get_value(get_value(42) - 1337 + get_value(-32) - 5 + (get_value(1) ? get_value(0) : get_value(2))) == get_value(0);
+}
+static_assert(test_complex_expr());
+
+constexpr bool get_constexpr_true() { return true; }
+[[msvc::constexpr]] bool get_msconstexpr_true() { return get_constexpr_true(); }
+constexpr bool test_get_msconstexpr_true() { [[msvc::constexpr]] return get_msconstexpr_true(); }
+static_assert(test_get_msconstexpr_true());
+
+// TODO (#72149): Add support for [[msvc::constexpr]] constructor; this code is valid for MSVC.
+struct S2 {
+    [[msvc::constexpr]] S2() {}
+    [[msvc::constexpr]] bool value() { return true; }
+    static constexpr bool check() { [[msvc::constexpr]] return S2{}.value(); } // expected-error {{constexpr function never produces a constant expression}} \
+                                                                               // expected-note {{non-literal type 'S2' cannot be used in a constant expression}} \
+                                                                               // expected-note {{non-literal type 'S2' cannot be used in a constant expression}}
+};
+static_assert(S2::check()); // expected-error {{static assertion expression is not an integral constant expression}} \
+                            // expected-note {{in call to 'check()'}}
-- 
GitLab


From fa981f57dde30fdae3c169182f5a354f375cff7a Mon Sep 17 00:00:00 2001
From: Benjamin Kramer <benny.kra@googlemail.com>
Date: Sat, 9 Dec 2023 11:38:56 +0100
Subject: [PATCH 020/349] [bazel] Port 46708a5bcba28955b2ddeddf5c0e64398223642b

---
 utils/bazel/llvm-project-overlay/mlir/unittests/BUILD.bazel | 1 +
 1 file changed, 1 insertion(+)

diff --git a/utils/bazel/llvm-project-overlay/mlir/unittests/BUILD.bazel b/utils/bazel/llvm-project-overlay/mlir/unittests/BUILD.bazel
index c4881383b5c5..d20bd403e8f8 100644
--- a/utils/bazel/llvm-project-overlay/mlir/unittests/BUILD.bazel
+++ b/utils/bazel/llvm-project-overlay/mlir/unittests/BUILD.bazel
@@ -101,6 +101,7 @@ cc_test(
         "//llvm:Support",
         "//llvm:TestingSupport",
         "//mlir:Analysis",
+        "//mlir:Debug",
         "//mlir:FuncDialect",
         "//mlir:IR",
         "//mlir:Pass",
-- 
GitLab


From 3ec6c72551846b8f4143c8c101a1a6203e85a2aa Mon Sep 17 00:00:00 2001
From: Jie Fu <jiefu@tencent.com>
Date: Sat, 9 Dec 2023 19:13:30 +0800
Subject: [PATCH 021/349] [AST] Fix -Wlogical-op-parentheses in
 ExprConstant.cpp (NFC)

llvm-project/clang/lib/AST/ExprConstant.cpp:5645:74: error: '&&' within '||' [-Werror,-Wlogical-op-parentheses]
 5645 |       (Definition->isConstexpr() || Info.CurrentCall->CanEvalMSConstexpr &&
      |                                  ~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~
 5646 |                                         Definition->hasAttr<MSConstexprAttr>()))
      |                                         ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
llvm-project/clang/lib/AST/ExprConstant.cpp:5645:74: note: place parentheses around the '&&' expression to silence this warning
 5645 |       (Definition->isConstexpr() || Info.CurrentCall->CanEvalMSConstexpr &&
      |                                                                          ^
      |                                     (
 5646 |                                         Definition->hasAttr<MSConstexprAttr>()))
      |
      |                                                                               )
1 error generated.
---
 clang/lib/AST/ExprConstant.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp
index 9bef70770a54..f035c1419f4c 100644
--- a/clang/lib/AST/ExprConstant.cpp
+++ b/clang/lib/AST/ExprConstant.cpp
@@ -5642,8 +5642,8 @@ static bool CheckConstexprFunction(EvalInfo &Info, SourceLocation CallLoc,
 
   // Can we evaluate this function call?
   if (Definition && Body &&
-      (Definition->isConstexpr() || Info.CurrentCall->CanEvalMSConstexpr &&
-                                        Definition->hasAttr<MSConstexprAttr>()))
+      (Definition->isConstexpr() || (Info.CurrentCall->CanEvalMSConstexpr &&
+                                        Definition->hasAttr<MSConstexprAttr>())))
     return true;
 
   if (Info.getLangOpts().CPlusPlus11) {
-- 
GitLab


From e3f154d8733928fa725584736a18b75832db30db Mon Sep 17 00:00:00 2001
From: Mark de Wever <koraq@xs4all.nl>
Date: Sat, 9 Dec 2023 12:32:17 +0100
Subject: [PATCH 022/349] [libc++] Implements Runtime format strings. (#73353)

This change requires quite a number of changes in the tests; this is not
code I expect people to use in the wild. So I don't expect breakage for
users.

Implements:
- P2905R2 Runtime format strings, as a Defect Report
---
 libcxx/docs/ReleaseNotes/18.rst                   |  1 +
 libcxx/docs/Status/Cxx2cPapers.csv                |  2 +-
 libcxx/docs/Status/FormatIssues.csv               |  2 +-
 libcxx/include/__format/format_arg_store.h        |  6 +++---
 libcxx/include/__format/format_functions.h        |  8 ++++----
 libcxx/include/format                             |  4 ++--
 .../print.fun/no_file_description.pass.cpp        |  6 ++++--
 .../print.fun/vprint_nonunicode.sh.cpp            |  8 ++++++--
 .../print.fun/vprint_unicode.sh.cpp               |  8 ++++++--
 .../format.arg.store/make_format_args.pass.cpp    | 15 +++++++++++++--
 .../format.arg.store/make_format_args.sh.cpp      |  3 ++-
 .../format.arg.store/make_wformat_args.pass.cpp   | 15 +++++++++++++--
 .../format.args/ctad.compile.pass.cpp             |  5 +++--
 .../format.arguments/format.args/ctor.pass.cpp    |  9 ++++++---
 .../format.context/format.context/arg.pass.cpp    |  6 ++++--
 .../format.context/format.context/ctor.pass.cpp   |  5 ++++-
 .../format.context/format.context/locale.pass.cpp |  5 ++++-
 .../formatter.string.pass.cpp                     |  3 +--
 18 files changed, 78 insertions(+), 33 deletions(-)

diff --git a/libcxx/docs/ReleaseNotes/18.rst b/libcxx/docs/ReleaseNotes/18.rst
index abefe4c28ca9..9e509db6359c 100644
--- a/libcxx/docs/ReleaseNotes/18.rst
+++ b/libcxx/docs/ReleaseNotes/18.rst
@@ -50,6 +50,7 @@ Implemented Papers
 - P0053R7 - C++ Synchronized Buffered Ostream (in the experimental library)
 - P2467R1 - Support exclusive mode for fstreams
 - P0020R6 - Floating Point Atomic
+- P2905R2 - Runtime format strings
 - P2918R2 - Runtime format strings II
 - P2871R3 - Remove Deprecated Unicode Conversion Facets from C++26
 - P2870R3 - Remove basic_string::reserve()
diff --git a/libcxx/docs/Status/Cxx2cPapers.csv b/libcxx/docs/Status/Cxx2cPapers.csv
index 1d071b7ebcb4..ff83648aa768 100644
--- a/libcxx/docs/Status/Cxx2cPapers.csv
+++ b/libcxx/docs/Status/Cxx2cPapers.csv
@@ -30,7 +30,7 @@
 "`P0543R3 <https://wg21.link/P0543R3>`__","LWG","Saturation arithmetic","Kona November 2023","","",""
 "`P2407R5 <https://wg21.link/P2407R5>`__","LWG","Freestanding Library: Partial Classes","Kona November 2023","","",""
 "`P2546R5 <https://wg21.link/P2546R5>`__","LWG","Debugging Support","Kona November 2023","","",""
-"`P2905R2 <https://wg21.link/P2905R2>`__","LWG","Runtime format strings","Kona November 2023","","","|format| |DR|"
+"`P2905R2 <https://wg21.link/P2905R2>`__","LWG","Runtime format strings","Kona November 2023","|Complete|","18.0","|format| |DR|"
 "`P2918R2 <https://wg21.link/P2918R2>`__","LWG","Runtime format strings II","Kona November 2023","|Complete|","18.0","|format|"
 "`P2909R4 <https://wg21.link/P2909R4>`__","LWG","Fix formatting of code units as integers (Dude, where’s my ``char``?)","Kona November 2023","|Complete|","18.0","|format| |DR|"
 "`P0952R2 <https://wg21.link/P0952R2>`__","LWG","A new specification for ``std::generate_canonical``","Kona November 2023","","",""
diff --git a/libcxx/docs/Status/FormatIssues.csv b/libcxx/docs/Status/FormatIssues.csv
index 005de97405f7..efb3e484f357 100644
--- a/libcxx/docs/Status/FormatIssues.csv
+++ b/libcxx/docs/Status/FormatIssues.csv
@@ -17,7 +17,7 @@ Number,Name,Standard,Assignee,Status,First released version
 "`P2510R3 <https://wg21.link/P2510R3>`__","Formatting pointers","C++26","Mark de Wever","|Complete|",17.0
 "`P2757R3 <https://wg21.link/P2757R3>`__","Type-checking format args","C++26","","",
 "`P2637R3 <https://wg21.link/P2637R3>`__","Member ``visit``","C++26","","",
-"`P2905R2 <https://wg21.link/P2905R2>`__","Runtime format strings","C++26 DR","Mark de Wever","|In Progress|"
+"`P2905R2 <https://wg21.link/P2905R2>`__","Runtime format strings","C++26 DR","Mark de Wever","|Complete|",18.0
 "`P2918R2 <https://wg21.link/P2918R2>`__","Runtime format strings II","C++26","Mark de Wever","|Complete|",18.0
 "`P2909R4 <https://wg21.link/P2909R4>`__","Fix formatting of code units as integers (Dude, where’s my ``char``?)","C++26 DR","Mark de Wever","|Complete|",18.0
 `P1361 <https://wg21.link/P1361>`_,"Integration of chrono with text formatting","C++20",Mark de Wever,|In Progress|,
diff --git a/libcxx/include/__format/format_arg_store.h b/libcxx/include/__format/format_arg_store.h
index 2962962ab5d1..64ee12440b62 100644
--- a/libcxx/include/__format/format_arg_store.h
+++ b/libcxx/include/__format/format_arg_store.h
@@ -206,8 +206,8 @@ _LIBCPP_HIDE_FROM_ABI basic_format_arg<_Context> __create_format_arg(_Tp& __valu
 }
 
 template <class _Context, class... _Args>
-_LIBCPP_HIDE_FROM_ABI void __create_packed_storage(uint64_t& __types, __basic_format_arg_value<_Context>* __values,
-                                                   _Args&&... __args) noexcept {
+_LIBCPP_HIDE_FROM_ABI void
+__create_packed_storage(uint64_t& __types, __basic_format_arg_value<_Context>* __values, _Args&... __args) noexcept {
   int __shift = 0;
   (
       [&] {
@@ -224,7 +224,7 @@ _LIBCPP_HIDE_FROM_ABI void __create_packed_storage(uint64_t& __types, __basic_fo
 }
 
 template <class _Context, class... _Args>
-_LIBCPP_HIDE_FROM_ABI void __store_basic_format_arg(basic_format_arg<_Context>* __data, _Args&&... __args) noexcept {
+_LIBCPP_HIDE_FROM_ABI void __store_basic_format_arg(basic_format_arg<_Context>* __data, _Args&... __args) noexcept {
   ([&] { *__data++ = __format::__create_format_arg<_Context>(__args); }(), ...);
 }
 
diff --git a/libcxx/include/__format/format_functions.h b/libcxx/include/__format/format_functions.h
index 164592d2ec15..8b2111f0e287 100644
--- a/libcxx/include/__format/format_functions.h
+++ b/libcxx/include/__format/format_functions.h
@@ -63,15 +63,15 @@ using wformat_args = basic_format_args<wformat_context>;
 #endif
 
 template <class _Context = format_context, class... _Args>
-_LIBCPP_NODISCARD_EXT _LIBCPP_HIDE_FROM_ABI __format_arg_store<_Context, _Args...> make_format_args(_Args&&... __args) {
-  return std::__format_arg_store<_Context, _Args...>(__args...);
+_LIBCPP_NODISCARD_EXT _LIBCPP_HIDE_FROM_ABI __format_arg_store<_Context, _Args...> make_format_args(_Args&... __args) {
+  return _VSTD::__format_arg_store<_Context, _Args...>(__args...);
 }
 
 #  ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS
 template <class... _Args>
 _LIBCPP_NODISCARD_EXT _LIBCPP_HIDE_FROM_ABI __format_arg_store<wformat_context, _Args...>
-make_wformat_args(_Args&&... __args) {
-  return std::__format_arg_store<wformat_context, _Args...>(__args...);
+make_wformat_args(_Args&... __args) {
+  return _VSTD::__format_arg_store<wformat_context, _Args...>(__args...);
 }
 #  endif
 
diff --git a/libcxx/include/format b/libcxx/include/format
index 7b8d5922cb49..ab9b336d0cda 100644
--- a/libcxx/include/format
+++ b/libcxx/include/format
@@ -177,10 +177,10 @@ namespace std {
 
   template<class Context = format_context, class... Args>
     format-arg-store<Context, Args...>
-      make_format_args(Args&&... args);
+      make_format_args(Args&... args);
   template<class... Args>
     format-arg-store<wformat_context, Args...>
-      make_wformat_args(Args&&... args);
+      make_wformat_args(Args&... args);
 
   // [format.error], class format_error
   class format_error;
diff --git a/libcxx/test/std/input.output/iostream.format/print.fun/no_file_description.pass.cpp b/libcxx/test/std/input.output/iostream.format/print.fun/no_file_description.pass.cpp
index c9297318cd5d..f502616b677b 100644
--- a/libcxx/test/std/input.output/iostream.format/print.fun/no_file_description.pass.cpp
+++ b/libcxx/test/std/input.output/iostream.format/print.fun/no_file_description.pass.cpp
@@ -69,7 +69,8 @@ static void test_vprint_unicode() {
   FILE* file = fmemopen(buffer.data(), buffer.size(), "wb");
   assert(file);
 
-  std::vprint_unicode(file, "hello world{}", std::make_format_args('!'));
+  char c = '!';
+  std::vprint_unicode(file, "hello world{}", std::make_format_args(c));
   long pos = std::ftell(file);
   std::fclose(file);
 
@@ -83,7 +84,8 @@ static void test_vprint_nonunicode() {
   FILE* file = fmemopen(buffer.data(), buffer.size(), "wb");
   assert(file);
 
-  std::vprint_nonunicode(file, "hello world{}", std::make_format_args('!'));
+  char c = '!';
+  std::vprint_nonunicode(file, "hello world{}", std::make_format_args(c));
   long pos = std::ftell(file);
   std::fclose(file);
 
diff --git a/libcxx/test/std/input.output/iostream.format/print.fun/vprint_nonunicode.sh.cpp b/libcxx/test/std/input.output/iostream.format/print.fun/vprint_nonunicode.sh.cpp
index 63e1d2ad82b7..c1a690f559b1 100644
--- a/libcxx/test/std/input.output/iostream.format/print.fun/vprint_nonunicode.sh.cpp
+++ b/libcxx/test/std/input.output/iostream.format/print.fun/vprint_nonunicode.sh.cpp
@@ -35,8 +35,12 @@
 
 int main(int, char**) {
   // The data is passed as-is so it does not depend on the encoding of the input.
-  std::vprint_nonunicode("{} {} ", std::make_format_args(1234, "一二三四"));
-  std::vprint_nonunicode("{} {}", std::make_format_args(true, nullptr));
+  int i         = 1234;
+  const char* s = "一二三四";
+  bool b        = true;
+  nullptr_t p   = nullptr;
+  std::vprint_nonunicode("{} {} ", std::make_format_args(i, s));
+  std::vprint_nonunicode("{} {}", std::make_format_args(b, p));
 
   return 0;
 }
diff --git a/libcxx/test/std/input.output/iostream.format/print.fun/vprint_unicode.sh.cpp b/libcxx/test/std/input.output/iostream.format/print.fun/vprint_unicode.sh.cpp
index a9bcc33d2e01..198e71b55d9b 100644
--- a/libcxx/test/std/input.output/iostream.format/print.fun/vprint_unicode.sh.cpp
+++ b/libcxx/test/std/input.output/iostream.format/print.fun/vprint_unicode.sh.cpp
@@ -35,8 +35,12 @@
 
 int main(int, char**) {
   // The data is passed as-is so it does not depend on the encoding of the input.
-  std::vprint_unicode("{} {} ", std::make_format_args(1234, "一二三四"));
-  std::vprint_unicode("{} {}", std::make_format_args(true, nullptr));
+  int i         = 1234;
+  const char* s = "一二三四";
+  bool b        = true;
+  nullptr_t p   = nullptr;
+  std::vprint_unicode("{} {} ", std::make_format_args(i, s));
+  std::vprint_unicode("{} {}", std::make_format_args(b, p));
 
   return 0;
 }
diff --git a/libcxx/test/std/utilities/format/format.arguments/format.arg.store/make_format_args.pass.cpp b/libcxx/test/std/utilities/format/format.arguments/format.arg.store/make_format_args.pass.cpp
index 72184bbd3920..62fd0f25ae3a 100644
--- a/libcxx/test/std/utilities/format/format.arguments/format.arg.store/make_format_args.pass.cpp
+++ b/libcxx/test/std/utilities/format/format.arguments/format.arg.store/make_format_args.pass.cpp
@@ -10,7 +10,7 @@
 // <format>
 
 // template<class Context = format_context, class... Args>
-// format-arg-store<Context, Args...> make_format_args(const Args&... args);
+// format-arg-store<Context, Args...> make_format_args(Args&... args);
 
 #include <cassert>
 #include <format>
@@ -20,8 +20,19 @@
 #include "test_basic_format_arg.h"
 #include "test_macros.h"
 
+template <class... Args>
+concept can_make_format_args = requires(Args&&... args) { std::make_format_args(std::forward<Args>(args)...); };
+
+static_assert(can_make_format_args<int&>);
+static_assert(!can_make_format_args<int>);
+static_assert(!can_make_format_args<int&&>);
+
 int main(int, char**) {
-  [[maybe_unused]] auto store = std::make_format_args(42, nullptr, false, 'x');
+  int i                       = 1;
+  char c                      = 'c';
+  nullptr_t p                 = nullptr;
+  bool b                      = false;
+  [[maybe_unused]] auto store = std::make_format_args(i, p, b, c);
 
   LIBCPP_STATIC_ASSERT(
       std::same_as<decltype(store), std::__format_arg_store<std::format_context, int, nullptr_t, bool, char>>);
diff --git a/libcxx/test/std/utilities/format/format.arguments/format.arg.store/make_format_args.sh.cpp b/libcxx/test/std/utilities/format/format.arguments/format.arg.store/make_format_args.sh.cpp
index 95a94b0bff5d..2d5ee8349b74 100644
--- a/libcxx/test/std/utilities/format/format.arguments/format.arg.store/make_format_args.sh.cpp
+++ b/libcxx/test/std/utilities/format/format.arguments/format.arg.store/make_format_args.sh.cpp
@@ -24,6 +24,7 @@
 #include "test_macros.h"
 
 void test() {
+  char c = 'c';
   TEST_IGNORE_NODISCARD
-  std::make_format_args<std::basic_format_context<std::back_insert_iterator<std::basic_string<wchar_t>>, wchar_t>>('c');
+  std::make_format_args<std::basic_format_context<std::back_insert_iterator<std::basic_string<wchar_t>>, wchar_t>>(c);
 }
diff --git a/libcxx/test/std/utilities/format/format.arguments/format.arg.store/make_wformat_args.pass.cpp b/libcxx/test/std/utilities/format/format.arguments/format.arg.store/make_wformat_args.pass.cpp
index 22c6f031efc6..73c4395a4a63 100644
--- a/libcxx/test/std/utilities/format/format.arguments/format.arg.store/make_wformat_args.pass.cpp
+++ b/libcxx/test/std/utilities/format/format.arguments/format.arg.store/make_wformat_args.pass.cpp
@@ -12,7 +12,7 @@
 
 // template<class... Args>
 //   format-arg-store<wformat_context, Args...>
-//   make_wformat_args(const Args&... args);
+//   make_wformat_args(Args&... args);
 
 #include <cassert>
 #include <format>
@@ -20,8 +20,19 @@
 #include "test_basic_format_arg.h"
 #include "test_macros.h"
 
+template <class... Args>
+concept can_make_wformat_args = requires(Args&&... args) { std::make_wformat_args(std::forward<Args>(args)...); };
+
+static_assert(can_make_wformat_args<int&>);
+static_assert(!can_make_wformat_args<int>);
+static_assert(!can_make_wformat_args<int&&>);
+
 int main(int, char**) {
-  [[maybe_unused]] auto store = std::make_wformat_args(42, nullptr, false, 'x');
+  int i                       = 1;
+  char c                      = 'c';
+  nullptr_t p                 = nullptr;
+  bool b                      = false;
+  [[maybe_unused]] auto store = std::make_wformat_args(i, p, b, c);
 
   LIBCPP_STATIC_ASSERT(
       std::same_as<decltype(store), std::__format_arg_store<std::wformat_context, int, nullptr_t, bool, char>>);
diff --git a/libcxx/test/std/utilities/format/format.arguments/format.args/ctad.compile.pass.cpp b/libcxx/test/std/utilities/format/format.arguments/format.args/ctad.compile.pass.cpp
index 7cadd4e76c74..b87b5c774ef7 100644
--- a/libcxx/test/std/utilities/format/format.arguments/format.args/ctad.compile.pass.cpp
+++ b/libcxx/test/std/utilities/format/format.arguments/format.args/ctad.compile.pass.cpp
@@ -18,12 +18,13 @@
 #include "test_macros.h"
 
 void test() {
+  int i = 1;
   // Note the Standard way to create a format-arg-store is by using make_format_args.
-  static_assert(std::same_as<decltype(std::basic_format_args(std::make_format_args(42))),
+  static_assert(std::same_as<decltype(std::basic_format_args(std::make_format_args(i))),
                              std::basic_format_args<std::format_context>>);
 
 #ifndef TEST_HAS_NO_WIDE_CHARACTERS
-  static_assert(std::same_as<decltype(std::basic_format_args(std::make_wformat_args(42))),
+  static_assert(std::same_as<decltype(std::basic_format_args(std::make_wformat_args(i))),
                              std::basic_format_args<std::wformat_context>>);
 
 #endif
diff --git a/libcxx/test/std/utilities/format/format.arguments/format.args/ctor.pass.cpp b/libcxx/test/std/utilities/format/format.arguments/format.args/ctor.pass.cpp
index c2d2d19d978b..c0575c545bde 100644
--- a/libcxx/test/std/utilities/format/format.arguments/format.args/ctor.pass.cpp
+++ b/libcxx/test/std/utilities/format/format.arguments/format.args/ctor.pass.cpp
@@ -20,6 +20,9 @@
 
 template <class CharT>
 void test() {
+  int i         = 1;
+  char c        = 'c';
+  nullptr_t p   = nullptr;
   using Context = std::basic_format_context<CharT*, CharT>;
   {
     ASSERT_NOEXCEPT(std::basic_format_args<Context>{});
@@ -28,14 +31,14 @@ void test() {
     assert(!format_args.get(0));
   }
   {
-    auto store = std::make_format_args<Context>(1);
+    auto store = std::make_format_args<Context>(i);
     ASSERT_NOEXCEPT(std::basic_format_args<Context>{store});
     std::basic_format_args<Context> format_args{store};
     assert(format_args.get(0));
     assert(!format_args.get(1));
   }
   {
-    auto store = std::make_format_args<Context>(1, 'c');
+    auto store = std::make_format_args<Context>(i, c);
     ASSERT_NOEXCEPT(std::basic_format_args<Context>{store});
     std::basic_format_args<Context> format_args{store};
     assert(format_args.get(0));
@@ -43,7 +46,7 @@ void test() {
     assert(!format_args.get(2));
   }
   {
-    auto store = std::make_format_args<Context>(1, 'c', nullptr);
+    auto store = std::make_format_args<Context>(i, c, p);
     ASSERT_NOEXCEPT(std::basic_format_args<Context>{store});
     std::basic_format_args<Context> format_args{store};
     assert(format_args.get(0));
diff --git a/libcxx/test/std/utilities/format/format.formatter/format.context/format.context/arg.pass.cpp b/libcxx/test/std/utilities/format/format.formatter/format.context/format.context/arg.pass.cpp
index 153f8bbaa4b3..824813d33a51 100644
--- a/libcxx/test/std/utilities/format/format.formatter/format.context/format.context/arg.pass.cpp
+++ b/libcxx/test/std/utilities/format/format.formatter/format.context/format.context/arg.pass.cpp
@@ -23,9 +23,11 @@
 
 template <class OutIt, class CharT>
 void test() {
+  bool b                          = true;
+  CharT c                         = CharT('a');
+  int a                           = 42;
   std::basic_string<CharT> string = MAKE_STRING(CharT, "string");
-  auto store = std::make_format_args<std::basic_format_context<OutIt, CharT>>(
-      true, CharT('a'), 42, string);
+  auto store                      = std::make_format_args<std::basic_format_context<OutIt, CharT>>(b, c, a, string);
   std::basic_format_args args = store;
 
   std::basic_string<CharT> output;
diff --git a/libcxx/test/std/utilities/format/format.formatter/format.context/format.context/ctor.pass.cpp b/libcxx/test/std/utilities/format/format.formatter/format.context/format.context/ctor.pass.cpp
index 4384f7b0fe68..40720105060f 100644
--- a/libcxx/test/std/utilities/format/format.formatter/format.context/format.context/ctor.pass.cpp
+++ b/libcxx/test/std/utilities/format/format.formatter/format.context/format.context/ctor.pass.cpp
@@ -36,11 +36,14 @@
 
 template <class OutIt, class CharT>
 void test() {
+  int a                           = 42;
+  bool b                          = true;
+  CharT c                         = CharT('a');
   std::basic_string<CharT> string = MAKE_STRING(CharT, "string");
   // The type of the object is an exposition only type. The temporary is needed
   // to extend the lifetime of the object since args stores a pointer to the
   // data in this object.
-  auto format_arg_store = std::make_format_args<std::basic_format_context<OutIt, CharT>>(true, CharT('a'), 42, string);
+  auto format_arg_store       = std::make_format_args<std::basic_format_context<OutIt, CharT>>(b, c, a, string);
   std::basic_format_args args = format_arg_store;
 
   {
diff --git a/libcxx/test/std/utilities/format/format.formatter/format.context/format.context/locale.pass.cpp b/libcxx/test/std/utilities/format/format.formatter/format.context/format.context/locale.pass.cpp
index 5533fe1b9f28..14bdc1426098 100644
--- a/libcxx/test/std/utilities/format/format.formatter/format.context/format.context/locale.pass.cpp
+++ b/libcxx/test/std/utilities/format/format.formatter/format.context/format.context/locale.pass.cpp
@@ -34,7 +34,10 @@ void test() {
   // The type of the object is an exposition only type. The temporary is needed
   // to extend the lifetime of the object since args stores a pointer to the
   // data in this object.
-  auto format_arg_store = std::make_format_args<std::basic_format_context<OutIt, CharT>>(true, CharT('a'), 42, string);
+  int a                       = 42;
+  bool b                      = true;
+  CharT c                     = CharT('a');
+  auto format_arg_store       = std::make_format_args<std::basic_format_context<OutIt, CharT>>(b, c, a, string);
   std::basic_format_args args = format_arg_store;
 
   {
diff --git a/libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.string.pass.cpp b/libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.string.pass.cpp
index 292de0cdd845..e99deb2db553 100644
--- a/libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.string.pass.cpp
+++ b/libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.string.pass.cpp
@@ -53,8 +53,7 @@ void test(StringT expected, StringViewT fmt, StringT a, std::size_t offset) {
   using FormatCtxT = std::basic_format_context<decltype(out), CharT>;
 
   ArgumentT arg = a;
-  FormatCtxT format_ctx = test_format_context_create<decltype(out), CharT>(
-      out, std::make_format_args<FormatCtxT>(std::forward<ArgumentT>(arg)));
+  FormatCtxT format_ctx = test_format_context_create<decltype(out), CharT>(out, std::make_format_args<FormatCtxT>(arg));
   formatter.format(arg, format_ctx);
   assert(result == expected);
 }
-- 
GitLab


From a17671084db17bbe45d96024af30e172b350c66d Mon Sep 17 00:00:00 2001
From: Benjamin Maxwell <benjamin.maxwell@arm.com>
Date: Sat, 9 Dec 2023 11:39:14 +0000
Subject: [PATCH 023/349] [mlir][ArmSME] Update `-allocate-arm-sme-tiles`
 description (NFC) (#74871)

---
 mlir/include/mlir/Dialect/ArmSME/Transforms/Passes.td | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/mlir/include/mlir/Dialect/ArmSME/Transforms/Passes.td b/mlir/include/mlir/Dialect/ArmSME/Transforms/Passes.td
index 7b9c74e0b8f6..02238f0a18ba 100644
--- a/mlir/include/mlir/Dialect/ArmSME/Transforms/Passes.td
+++ b/mlir/include/mlir/Dialect/ArmSME/Transforms/Passes.td
@@ -87,8 +87,9 @@ def TileAllocation
   let summary = "Allocate SME tiles";
   let description = [{
     This pass does tile allocation for SME "virtual tiles". It is run at the
-    'func.func' op level, replacing 'arm_sme.get_tile_id' ops with (i32) tile
-    ids. An error will be emitted when there's no tiles left.
+    'func.func' op level, and assigns tile IDs (via an attribute) to all ops
+    that implement the `ArmSMETileOpInterface`. An error will be emitted when
+    there's no tiles left.
   }];
   let constructor = "mlir::arm_sme::createTileAllocationPass()";
   let dependentDialects = ["func::FuncDialect"];
-- 
GitLab


From 600462a2db7c044896122acfb347ce2d4d88271f Mon Sep 17 00:00:00 2001
From: Mark de Wever <koraq@xs4all.nl>
Date: Sat, 9 Dec 2023 13:51:50 +0100
Subject: [PATCH 024/349] [libc++][modules] Adds std.compat module. (#71438)

This adds the std.compat module. The patch contains a bit of refactoring
to avoid code duplication between the std and std.compat module.

Implements parts of
- P2465R3 Standard Library Modules std and std.compat
---
 libcxx/modules/CMakeLists.txt                 |  41 ++-
 libcxx/modules/CMakeLists.txt.in              |  28 ++
 libcxx/modules/std.compat.cppm.in             | 208 ++++++++++++
 libcxx/modules/std.compat/cassert.inc         |  12 +
 libcxx/modules/std.compat/cctype.inc          |  25 ++
 libcxx/modules/std.compat/cerrno.inc          |  12 +
 libcxx/modules/std.compat/cfenv.inc           |  29 ++
 libcxx/modules/std.compat/cfloat.inc          |  12 +
 libcxx/modules/std.compat/cinttypes.inc       |  25 ++
 libcxx/modules/std.compat/climits.inc         |  12 +
 libcxx/modules/std.compat/clocale.inc         |  17 +
 libcxx/modules/std.compat/cmath.inc           | 268 ++++++++++++++++
 libcxx/modules/std.compat/csetjmp.inc         |  13 +
 libcxx/modules/std.compat/csignal.inc         |  17 +
 libcxx/modules/std.compat/cstdarg.inc         |  10 +
 libcxx/modules/std.compat/cstddef.inc         |  22 ++
 libcxx/modules/std.compat/cstdint.inc         |  50 +++
 libcxx/modules/std.compat/cstdio.inc          |  61 ++++
 libcxx/modules/std.compat/cstdlib.inc         |  72 +++++
 libcxx/modules/std.compat/cstring.inc         |  36 +++
 libcxx/modules/std.compat/ctime.inc           |  28 ++
 libcxx/modules/std.compat/cuchar.inc          |  28 ++
 libcxx/modules/std.compat/cwchar.inc          |  80 +++++
 libcxx/modules/std.compat/cwctype.inc         |  35 ++
 libcxx/modules/std.cppm.in                    |  46 +--
 libcxx/test/libcxx/module_std.gen.py          | 246 +-------------
 libcxx/test/libcxx/module_std_compat.gen.py   |  62 ++++
 libcxx/test/lit.local.cfg                     |  14 +
 libcxx/test/std/modules/std.compat.pass.cpp   |  18 ++
 .../header_exportable_declarations.cpp        | 134 +++++++-
 .../header_exportable_declarations.hpp        |  34 +-
 libcxx/utils/CMakeLists.txt                   |  13 +-
 ..._cppm_in.py => generate_libcxx_cppm_in.py} |  71 ++--
 libcxx/utils/libcxx/test/modules.py           | 302 ++++++++++++++++++
 34 files changed, 1775 insertions(+), 306 deletions(-)
 create mode 100644 libcxx/modules/std.compat.cppm.in
 create mode 100644 libcxx/modules/std.compat/cassert.inc
 create mode 100644 libcxx/modules/std.compat/cctype.inc
 create mode 100644 libcxx/modules/std.compat/cerrno.inc
 create mode 100644 libcxx/modules/std.compat/cfenv.inc
 create mode 100644 libcxx/modules/std.compat/cfloat.inc
 create mode 100644 libcxx/modules/std.compat/cinttypes.inc
 create mode 100644 libcxx/modules/std.compat/climits.inc
 create mode 100644 libcxx/modules/std.compat/clocale.inc
 create mode 100644 libcxx/modules/std.compat/cmath.inc
 create mode 100644 libcxx/modules/std.compat/csetjmp.inc
 create mode 100644 libcxx/modules/std.compat/csignal.inc
 create mode 100644 libcxx/modules/std.compat/cstdarg.inc
 create mode 100644 libcxx/modules/std.compat/cstddef.inc
 create mode 100644 libcxx/modules/std.compat/cstdint.inc
 create mode 100644 libcxx/modules/std.compat/cstdio.inc
 create mode 100644 libcxx/modules/std.compat/cstdlib.inc
 create mode 100644 libcxx/modules/std.compat/cstring.inc
 create mode 100644 libcxx/modules/std.compat/ctime.inc
 create mode 100644 libcxx/modules/std.compat/cuchar.inc
 create mode 100644 libcxx/modules/std.compat/cwchar.inc
 create mode 100644 libcxx/modules/std.compat/cwctype.inc
 create mode 100644 libcxx/test/libcxx/module_std_compat.gen.py
 create mode 100644 libcxx/test/std/modules/std.compat.pass.cpp
 rename libcxx/utils/{generate_std_cppm_in.py => generate_libcxx_cppm_in.py} (51%)
 create mode 100644 libcxx/utils/libcxx/test/modules.py

diff --git a/libcxx/modules/CMakeLists.txt b/libcxx/modules/CMakeLists.txt
index 395226fb3728..fae6448a7eec 100644
--- a/libcxx/modules/CMakeLists.txt
+++ b/libcxx/modules/CMakeLists.txt
@@ -118,6 +118,30 @@ set(LIBCXX_MODULE_STD_SOURCES
   std/version.inc
 )
 
+set(LIBCXX_MODULE_STD_COMPAT_SOURCES
+  std.compat/cassert.inc
+  std.compat/cctype.inc
+  std.compat/cerrno.inc
+  std.compat/cfenv.inc
+  std.compat/cfloat.inc
+  std.compat/cinttypes.inc
+  std.compat/climits.inc
+  std.compat/clocale.inc
+  std.compat/cmath.inc
+  std.compat/csetjmp.inc
+  std.compat/csignal.inc
+  std.compat/cstdarg.inc
+  std.compat/cstddef.inc
+  std.compat/cstdint.inc
+  std.compat/cstdio.inc
+  std.compat/cstdlib.inc
+  std.compat/cstring.inc
+  std.compat/ctime.inc
+  std.compat/cuchar.inc
+  std.compat/cwchar.inc
+  std.compat/cwctype.inc
+)
+
 # TODO MODULES the CMakeLists.txt in the install directory is only temporary
 # When that is removed the configured file can use the substitution
 # LIBCXX_GENERATED_INCLUDE_TARGET_DIR avoiding this set.
@@ -154,10 +178,25 @@ configure_file(
   @ONLY
 )
 
+set(LIBCXX_MODULE_STD_COMPAT_INCLUDE_SOURCES)
+foreach(file ${LIBCXX_MODULE_STD_COMPAT_SOURCES})
+  set(
+    LIBCXX_MODULE_STD_COMPAT_INCLUDE_SOURCES
+    "${LIBCXX_MODULE_STD_COMPAT_INCLUDE_SOURCES}#include \"${file}\"\n"
+  )
+endforeach()
+
+configure_file(
+  "std.compat.cppm.in"
+  "${LIBCXX_GENERATED_MODULE_DIR}/std.compat.cppm"
+  @ONLY
+)
+
 set(_all_modules)
 list(APPEND _all_modules "${LIBCXX_GENERATED_MODULE_DIR}/CMakeLists.txt")
 list(APPEND _all_modules "${LIBCXX_GENERATED_MODULE_DIR}/std.cppm")
-foreach(file ${LIBCXX_MODULE_STD_SOURCES})
+list(APPEND _all_modules "${LIBCXX_GENERATED_MODULE_DIR}/std.compat.cppm")
+foreach(file ${LIBCXX_MODULE_STD_SOURCES} ${LIBCXX_MODULE_STD_COMPAT_SOURCES})
   set(src "${CMAKE_CURRENT_SOURCE_DIR}/${file}")
   set(dst "${LIBCXX_GENERATED_MODULE_DIR}/${file}")
   add_custom_command(OUTPUT ${dst}
diff --git a/libcxx/modules/CMakeLists.txt.in b/libcxx/modules/CMakeLists.txt.in
index dca3b25155a5..b02b68915b8f 100644
--- a/libcxx/modules/CMakeLists.txt.in
+++ b/libcxx/modules/CMakeLists.txt.in
@@ -29,6 +29,8 @@ macro(compile_define_if condition def)
   endif()
 endmacro()
 
+### STD
+
 add_library(std)
 target_sources(std
   PUBLIC FILE_SET cxx_modules TYPE CXX_MODULES FILES
@@ -52,3 +54,29 @@ set_target_properties(std
   PROPERTIES
     OUTPUT_NAME   "c++std"
 )
+
+### STD.COMPAT
+
+add_library(std.compat)
+target_sources(std.compat
+  PUBLIC FILE_SET cxx_modules TYPE CXX_MODULES FILES
+    std.compat.cppm
+)
+
+target_include_directories(std.compat SYSTEM PRIVATE @LIBCXX_CONFIGURED_INCLUDE_DIRS@)
+
+if (NOT @LIBCXX_ENABLE_EXCEPTIONS@)
+  target_compile_options(std.compat PUBLIC -fno-exceptions)
+endif()
+
+target_compile_options(std.compat
+  PUBLIC
+    -nostdinc++
+    -Wno-reserved-module-identifier
+    -Wno-reserved-user-defined-literal
+    @LIBCXX_COMPILE_FLAGS@
+)
+set_target_properties(std.compat
+  PROPERTIES
+    OUTPUT_NAME   "c++std.compat"
+)
diff --git a/libcxx/modules/std.compat.cppm.in b/libcxx/modules/std.compat.cppm.in
new file mode 100644
index 000000000000..f199e194e60b
--- /dev/null
+++ b/libcxx/modules/std.compat.cppm.in
@@ -0,0 +1,208 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+// WARNING, this entire header is generated by
+// utils/generate_libcxx_cppm_in.py
+// DO NOT MODIFY!
+
+module;
+
+#include <__config>
+
+// The headers of Table 24: C++ library headers [tab:headers.cpp]
+// and the headers of Table 25: C++ headers for C library facilities [tab:headers.cpp.c]
+#include <algorithm>
+#include <any>
+#include <array>
+#if !defined(_LIBCPP_HAS_NO_ATOMIC_HEADER)
+#  include <atomic>
+#endif
+#if !defined(_LIBCPP_HAS_NO_THREADS)
+#  include <barrier>
+#endif
+#include <bit>
+#include <bitset>
+#include <cassert>
+#include <cctype>
+#include <cerrno>
+#include <cfenv>
+#include <cfloat>
+#include <charconv>
+#include <chrono>
+#include <cinttypes>
+#include <climits>
+#if !defined(_LIBCPP_HAS_NO_LOCALIZATION)
+#  include <clocale>
+#endif
+#include <cmath>
+#if !defined(_LIBCPP_HAS_NO_LOCALIZATION)
+#  include <codecvt>
+#endif
+#include <compare>
+#include <complex>
+#include <concepts>
+#include <condition_variable>
+#include <coroutine>
+#include <csetjmp>
+#include <csignal>
+#include <cstdarg>
+#include <cstddef>
+#include <cstdint>
+#include <cstdio>
+#include <cstdlib>
+#include <cstring>
+#include <ctime>
+#include <cuchar>
+#if !defined(_LIBCPP_HAS_NO_WIDE_CHARACTERS)
+#  include <cwchar>
+#endif
+#if !defined(_LIBCPP_HAS_NO_WIDE_CHARACTERS)
+#  include <cwctype>
+#endif
+#include <deque>
+#include <exception>
+#include <execution>
+#include <expected>
+#include <filesystem>
+#include <format>
+#include <forward_list>
+#if !defined(_LIBCPP_HAS_NO_LOCALIZATION)
+#  include <fstream>
+#endif
+#include <functional>
+#if !defined(_LIBCPP_HAS_NO_THREADS)
+#  include <future>
+#endif
+#include <initializer_list>
+#if !defined(_LIBCPP_HAS_NO_LOCALIZATION)
+#  include <iomanip>
+#endif
+#if !defined(_LIBCPP_HAS_NO_LOCALIZATION)
+#  include <ios>
+#endif
+#include <iosfwd>
+#if !defined(_LIBCPP_HAS_NO_LOCALIZATION)
+#  include <iostream>
+#endif
+#if !defined(_LIBCPP_HAS_NO_LOCALIZATION)
+#  include <istream>
+#endif
+#include <iterator>
+#if !defined(_LIBCPP_HAS_NO_THREADS)
+#  include <latch>
+#endif
+#include <limits>
+#include <list>
+#if !defined(_LIBCPP_HAS_NO_LOCALIZATION)
+#  include <locale>
+#endif
+#include <map>
+#include <mdspan>
+#include <memory>
+#include <memory_resource>
+#include <mutex>
+#include <new>
+#include <numbers>
+#include <numeric>
+#include <optional>
+#if !defined(_LIBCPP_HAS_NO_LOCALIZATION)
+#  include <ostream>
+#endif
+#include <print>
+#include <queue>
+#include <random>
+#include <ranges>
+#include <ratio>
+#if !defined(_LIBCPP_HAS_NO_LOCALIZATION)
+#  include <regex>
+#endif
+#include <scoped_allocator>
+#if !defined(_LIBCPP_HAS_NO_THREADS)
+#  include <semaphore>
+#endif
+#include <set>
+#if !defined(_LIBCPP_HAS_NO_THREADS)
+#  include <shared_mutex>
+#endif
+#include <source_location>
+#include <span>
+#if !defined(_LIBCPP_HAS_NO_LOCALIZATION)
+#  include <sstream>
+#endif
+#include <stack>
+#include <stdexcept>
+#if !defined(_LIBCPP_HAS_NO_THREADS)
+#  include <stop_token>
+#endif
+#if !defined(_LIBCPP_HAS_NO_LOCALIZATION)
+#  include <streambuf>
+#endif
+#include <string>
+#include <string_view>
+#if !defined(_LIBCPP_HAS_NO_LOCALIZATION)
+#  include <strstream>
+#endif
+#if !defined(_LIBCPP_HAS_NO_LOCALIZATION)
+#  include <syncstream>
+#endif
+#include <system_error>
+#if !defined(_LIBCPP_HAS_NO_THREADS)
+#  include <thread>
+#endif
+#include <tuple>
+#include <type_traits>
+#include <typeindex>
+#include <typeinfo>
+#include <unordered_map>
+#include <unordered_set>
+#include <utility>
+#include <valarray>
+#include <variant>
+#include <vector>
+#include <version>
+
+// *** Headers not yet available ***
+#if __has_include(<debugging>)
+#  error "please update the header information for <debugging> in headers_not_available in utils/libcxx/header_information.py"
+#endif // __has_include(<debugging>)
+#if __has_include(<flat_map>)
+#  error "please update the header information for <flat_map> in headers_not_available in utils/libcxx/header_information.py"
+#endif // __has_include(<flat_map>)
+#if __has_include(<flat_set>)
+#  error "please update the header information for <flat_set> in headers_not_available in utils/libcxx/header_information.py"
+#endif // __has_include(<flat_set>)
+#if __has_include(<generator>)
+#  error "please update the header information for <generator> in headers_not_available in utils/libcxx/header_information.py"
+#endif // __has_include(<generator>)
+#if __has_include(<hazard_pointer>)
+#  error "please update the header information for <hazard_pointer> in headers_not_available in utils/libcxx/header_information.py"
+#endif // __has_include(<hazard_pointer>)
+#if __has_include(<linalg>)
+#  error "please update the header information for <linalg> in headers_not_available in utils/libcxx/header_information.py"
+#endif // __has_include(<linalg>)
+#if __has_include(<rcu>)
+#  error "please update the header information for <rcu> in headers_not_available in utils/libcxx/header_information.py"
+#endif // __has_include(<rcu>)
+#if __has_include(<spanstream>)
+#  error "please update the header information for <spanstream> in headers_not_available in utils/libcxx/header_information.py"
+#endif // __has_include(<spanstream>)
+#if __has_include(<stacktrace>)
+#  error "please update the header information for <stacktrace> in headers_not_available in utils/libcxx/header_information.py"
+#endif // __has_include(<stacktrace>)
+#if __has_include(<stdfloat>)
+#  error "please update the header information for <stdfloat> in headers_not_available in utils/libcxx/header_information.py"
+#endif // __has_include(<stdfloat>)
+#if __has_include(<text_encoding>)
+#  error "please update the header information for <text_encoding> in headers_not_available in utils/libcxx/header_information.py"
+#endif // __has_include(<text_encoding>)
+
+export module std.compat;
+
+@LIBCXX_MODULE_STD_INCLUDE_SOURCES@
+@LIBCXX_MODULE_STD_COMPAT_INCLUDE_SOURCES@
\ No newline at end of file
diff --git a/libcxx/modules/std.compat/cassert.inc b/libcxx/modules/std.compat/cassert.inc
new file mode 100644
index 000000000000..ac0533d14e9a
--- /dev/null
+++ b/libcxx/modules/std.compat/cassert.inc
@@ -0,0 +1,12 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+export {
+  // This module exports nothing.
+} // export
diff --git a/libcxx/modules/std.compat/cctype.inc b/libcxx/modules/std.compat/cctype.inc
new file mode 100644
index 000000000000..56fb45a374a5
--- /dev/null
+++ b/libcxx/modules/std.compat/cctype.inc
@@ -0,0 +1,25 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+export {
+  using ::isalnum;
+  using ::isalpha;
+  using ::isblank;
+  using ::iscntrl;
+  using ::isdigit;
+  using ::isgraph;
+  using ::islower;
+  using ::isprint;
+  using ::ispunct;
+  using ::isspace;
+  using ::isupper;
+  using ::isxdigit;
+  using ::tolower;
+  using ::toupper;
+} // export
diff --git a/libcxx/modules/std.compat/cerrno.inc b/libcxx/modules/std.compat/cerrno.inc
new file mode 100644
index 000000000000..ac0533d14e9a
--- /dev/null
+++ b/libcxx/modules/std.compat/cerrno.inc
@@ -0,0 +1,12 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+export {
+  // This module exports nothing.
+} // export
diff --git a/libcxx/modules/std.compat/cfenv.inc b/libcxx/modules/std.compat/cfenv.inc
new file mode 100644
index 000000000000..50128463d6a9
--- /dev/null
+++ b/libcxx/modules/std.compat/cfenv.inc
@@ -0,0 +1,29 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+export {
+  // types
+  using ::fenv_t;
+  using ::fexcept_t;
+
+  // functions
+  using ::feclearexcept;
+  using ::fegetexceptflag;
+  using ::feraiseexcept;
+  using ::fesetexceptflag;
+  using ::fetestexcept;
+
+  using ::fegetround;
+  using ::fesetround;
+
+  using ::fegetenv;
+  using ::feholdexcept;
+  using ::fesetenv;
+  using ::feupdateenv;
+} // export
diff --git a/libcxx/modules/std.compat/cfloat.inc b/libcxx/modules/std.compat/cfloat.inc
new file mode 100644
index 000000000000..ac0533d14e9a
--- /dev/null
+++ b/libcxx/modules/std.compat/cfloat.inc
@@ -0,0 +1,12 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+export {
+  // This module exports nothing.
+} // export
diff --git a/libcxx/modules/std.compat/cinttypes.inc b/libcxx/modules/std.compat/cinttypes.inc
new file mode 100644
index 000000000000..a64c088d0d6f
--- /dev/null
+++ b/libcxx/modules/std.compat/cinttypes.inc
@@ -0,0 +1,25 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+export {
+  using ::imaxdiv_t;
+
+  using ::imaxabs;
+  using ::imaxdiv;
+  using ::strtoimax;
+  using ::strtoumax;
+  using ::wcstoimax;
+  using ::wcstoumax;
+
+  // abs is conditionally here, but always present in cmath.cppm. To avoid
+  // conflicing declarations omit the using here.
+
+  // div is conditionally here, but always present in cstdlib.cppm. To avoid
+  // conflicing declarations omit the using here.
+} // export
diff --git a/libcxx/modules/std.compat/climits.inc b/libcxx/modules/std.compat/climits.inc
new file mode 100644
index 000000000000..ac0533d14e9a
--- /dev/null
+++ b/libcxx/modules/std.compat/climits.inc
@@ -0,0 +1,12 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+export {
+  // This module exports nothing.
+} // export
diff --git a/libcxx/modules/std.compat/clocale.inc b/libcxx/modules/std.compat/clocale.inc
new file mode 100644
index 000000000000..d9785a737943
--- /dev/null
+++ b/libcxx/modules/std.compat/clocale.inc
@@ -0,0 +1,17 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+export {
+#ifndef _LIBCPP_HAS_NO_LOCALIZATION
+  using ::lconv;
+
+  using ::localeconv;
+  using ::setlocale;
+#endif // _LIBCPP_HAS_NO_LOCALIZATION
+} // export
diff --git a/libcxx/modules/std.compat/cmath.inc b/libcxx/modules/std.compat/cmath.inc
new file mode 100644
index 000000000000..de5379275c5f
--- /dev/null
+++ b/libcxx/modules/std.compat/cmath.inc
@@ -0,0 +1,268 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+export {
+  using ::double_t;
+  using ::float_t;
+
+  using ::acos;
+  using ::acosf;
+  using ::acosl;
+
+  using ::asin;
+  using ::asinf;
+  using ::asinl;
+
+  using ::atan;
+  using ::atanf;
+  using ::atanl;
+
+  using ::atan2;
+  using ::atan2f;
+  using ::atan2l;
+
+  using ::cos;
+  using ::cosf;
+  using ::cosl;
+
+  using ::sin;
+  using ::sinf;
+  using ::sinl;
+
+  using ::tan;
+  using ::tanf;
+  using ::tanl;
+
+  using ::acosh;
+  using ::acoshf;
+  using ::acoshl;
+
+  using ::asinh;
+  using ::asinhf;
+  using ::asinhl;
+
+  using ::atanh;
+  using ::atanhf;
+  using ::atanhl;
+
+  using ::cosh;
+  using ::coshf;
+  using ::coshl;
+
+  using ::sinh;
+  using ::sinhf;
+  using ::sinhl;
+
+  using ::tanh;
+  using ::tanhf;
+  using ::tanhl;
+
+  using ::exp;
+  using ::expf;
+  using ::expl;
+
+  using ::exp2;
+  using ::exp2f;
+  using ::exp2l;
+
+  using ::expm1;
+  using ::expm1f;
+  using ::expm1l;
+
+  using ::frexp;
+  using ::frexpf;
+  using ::frexpl;
+
+  using ::ilogb;
+  using ::ilogbf;
+  using ::ilogbl;
+
+  using ::ldexp;
+  using ::ldexpf;
+  using ::ldexpl;
+
+  using ::log;
+  using ::logf;
+  using ::logl;
+
+  using ::log10;
+  using ::log10f;
+  using ::log10l;
+
+  using ::log1p;
+  using ::log1pf;
+  using ::log1pl;
+
+  using ::log2;
+  using ::log2f;
+  using ::log2l;
+
+  using ::logb;
+  using ::logbf;
+  using ::logbl;
+
+  using ::modf;
+  using ::modff;
+  using ::modfl;
+
+  using ::scalbn;
+  using ::scalbnf;
+  using ::scalbnl;
+
+  using ::scalbln;
+  using ::scalblnf;
+  using ::scalblnl;
+
+  using ::cbrt;
+  using ::cbrtf;
+  using ::cbrtl;
+
+  // [c.math.abs], absolute values
+  using ::abs;
+
+  using ::fabs;
+  using ::fabsf;
+  using ::fabsl;
+
+  using ::hypot;
+  using ::hypotf;
+  using ::hypotl;
+
+  // [c.math.hypot3], three-dimensional hypotenuse
+
+  using ::pow;
+  using ::powf;
+  using ::powl;
+
+  using ::sqrt;
+  using ::sqrtf;
+  using ::sqrtl;
+
+  using ::erf;
+  using ::erff;
+  using ::erfl;
+
+  using ::erfc;
+  using ::erfcf;
+  using ::erfcl;
+
+  using ::lgamma;
+  using ::lgammaf;
+  using ::lgammal;
+
+  using ::tgamma;
+  using ::tgammaf;
+  using ::tgammal;
+
+  using ::ceil;
+  using ::ceilf;
+  using ::ceill;
+
+  using ::floor;
+  using ::floorf;
+  using ::floorl;
+
+  using ::nearbyint;
+  using ::nearbyintf;
+  using ::nearbyintl;
+
+  using ::rint;
+  using ::rintf;
+  using ::rintl;
+
+  using ::lrint;
+  using ::lrintf;
+  using ::lrintl;
+
+  using ::llrint;
+  using ::llrintf;
+  using ::llrintl;
+
+  using ::round;
+  using ::roundf;
+  using ::roundl;
+
+  using ::lround;
+  using ::lroundf;
+  using ::lroundl;
+
+  using ::llround;
+  using ::llroundf;
+  using ::llroundl;
+
+  using ::trunc;
+  using ::truncf;
+  using ::truncl;
+
+  using ::fmod;
+  using ::fmodf;
+  using ::fmodl;
+
+  using ::remainder;
+  using ::remainderf;
+  using ::remainderl;
+
+  using ::remquo;
+  using ::remquof;
+  using ::remquol;
+
+  using ::copysign;
+  using ::copysignf;
+  using ::copysignl;
+
+  using ::nan;
+  using ::nanf;
+  using ::nanl;
+
+  using ::nextafter;
+  using ::nextafterf;
+  using ::nextafterl;
+
+  using ::nexttoward;
+  using ::nexttowardf;
+  using ::nexttowardl;
+
+  using ::fdim;
+  using ::fdimf;
+  using ::fdiml;
+
+  using ::fmax;
+  using ::fmaxf;
+  using ::fmaxl;
+
+  using ::fmin;
+  using ::fminf;
+  using ::fminl;
+
+  using ::fma;
+  using ::fmaf;
+  using ::fmal;
+
+  // [c.math.lerp], linear interpolation
+  // [support.c.headers.other]/1
+  // ...  placed within the global namespace scope, except for the functions
+  // described in [sf.cmath], the std::lerp function overloads ([c.math.lerp])
+  // ...
+
+  // [c.math.fpclass], classification / comparison functions
+  using ::fpclassify;
+  using ::isfinite;
+  using ::isgreater;
+  using ::isgreaterequal;
+  using ::isinf;
+  using ::isless;
+  using ::islessequal;
+  using ::islessgreater;
+  using ::isnan;
+  using ::isnormal;
+  using ::isunordered;
+  using ::signbit;
+
+  // [sf.cmath], mathematical special functions
+} // export
diff --git a/libcxx/modules/std.compat/csetjmp.inc b/libcxx/modules/std.compat/csetjmp.inc
new file mode 100644
index 000000000000..1fc42ea3ee03
--- /dev/null
+++ b/libcxx/modules/std.compat/csetjmp.inc
@@ -0,0 +1,13 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+export {
+  using ::jmp_buf;
+  using ::longjmp;
+} // export
diff --git a/libcxx/modules/std.compat/csignal.inc b/libcxx/modules/std.compat/csignal.inc
new file mode 100644
index 000000000000..33af6a9f2b73
--- /dev/null
+++ b/libcxx/modules/std.compat/csignal.inc
@@ -0,0 +1,17 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+export {
+  using ::sig_atomic_t;
+
+  // [support.signal], signal handlers
+  using ::signal;
+
+  using ::raise;
+} // export
diff --git a/libcxx/modules/std.compat/cstdarg.inc b/libcxx/modules/std.compat/cstdarg.inc
new file mode 100644
index 000000000000..3efb34617a8b
--- /dev/null
+++ b/libcxx/modules/std.compat/cstdarg.inc
@@ -0,0 +1,10 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+export { using ::va_list; } // export
diff --git a/libcxx/modules/std.compat/cstddef.inc b/libcxx/modules/std.compat/cstddef.inc
new file mode 100644
index 000000000000..94ad036fd8f4
--- /dev/null
+++ b/libcxx/modules/std.compat/cstddef.inc
@@ -0,0 +1,22 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+export {
+  using ::max_align_t;
+  using ::nullptr_t;
+  using ::ptrdiff_t;
+  using ::size_t;
+
+  // [support.c.headers]/1
+  // ...  placed within the global namespace scope, except for ... the
+  // declaration of std::byte ([cstddef.syn]), and the functions and
+  // function templates described in [support.types.byteops]. ...
+
+  // [support.types.byteops], byte type operations
+} // export
diff --git a/libcxx/modules/std.compat/cstdint.inc b/libcxx/modules/std.compat/cstdint.inc
new file mode 100644
index 000000000000..1a74efc70cea
--- /dev/null
+++ b/libcxx/modules/std.compat/cstdint.inc
@@ -0,0 +1,50 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+export {
+  // signed
+  using ::int8_t _LIBCPP_USING_IF_EXISTS;
+  using ::int16_t _LIBCPP_USING_IF_EXISTS;
+  using ::int32_t _LIBCPP_USING_IF_EXISTS;
+  using ::int64_t _LIBCPP_USING_IF_EXISTS;
+
+  using ::int_fast16_t;
+  using ::int_fast32_t;
+  using ::int_fast64_t;
+  using ::int_fast8_t;
+
+  using ::int_least16_t;
+  using ::int_least32_t;
+  using ::int_least64_t;
+  using ::int_least8_t;
+
+  using ::intmax_t;
+
+  using ::intptr_t _LIBCPP_USING_IF_EXISTS;
+
+  // unsigned
+  using ::uint8_t _LIBCPP_USING_IF_EXISTS;
+  using ::uint16_t _LIBCPP_USING_IF_EXISTS;
+  using ::uint32_t _LIBCPP_USING_IF_EXISTS;
+  using ::uint64_t _LIBCPP_USING_IF_EXISTS;
+
+  using ::uint_fast16_t;
+  using ::uint_fast32_t;
+  using ::uint_fast64_t;
+  using ::uint_fast8_t;
+
+  using ::uint_least16_t;
+  using ::uint_least32_t;
+  using ::uint_least64_t;
+  using ::uint_least8_t;
+
+  using ::uintmax_t;
+
+  using ::uintptr_t _LIBCPP_USING_IF_EXISTS;
+} // export
diff --git a/libcxx/modules/std.compat/cstdio.inc b/libcxx/modules/std.compat/cstdio.inc
new file mode 100644
index 000000000000..1ec3015c9e2a
--- /dev/null
+++ b/libcxx/modules/std.compat/cstdio.inc
@@ -0,0 +1,61 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+export {
+  using ::FILE;
+  using ::fpos_t;
+  using ::size_t;
+
+  using ::clearerr;
+  using ::fclose;
+  using ::feof;
+  using ::ferror;
+  using ::fflush;
+  using ::fgetc;
+  using ::fgetpos;
+  using ::fgets;
+  using ::fopen;
+  using ::fprintf;
+  using ::fputc;
+  using ::fputs;
+  using ::fread;
+  using ::freopen;
+  using ::fscanf;
+  using ::fseek;
+  using ::fsetpos;
+  using ::ftell;
+  using ::fwrite;
+  using ::getc;
+  using ::getchar;
+  using ::perror;
+  using ::printf;
+  using ::putc;
+  using ::putchar;
+  using ::puts;
+  using ::remove;
+  using ::rename;
+  using ::rewind;
+  using ::scanf;
+  using ::setbuf;
+  using ::setvbuf;
+  using ::snprintf;
+  using ::sprintf;
+  using ::sscanf;
+  using ::tmpfile;
+  using ::tmpnam;
+  using ::ungetc;
+  using ::vfprintf;
+  using ::vfscanf;
+  using ::vprintf;
+  using ::vscanf;
+  using ::vsnprintf;
+  using ::vsprintf;
+  using ::vsscanf;
+
+} // export
diff --git a/libcxx/modules/std.compat/cstdlib.inc b/libcxx/modules/std.compat/cstdlib.inc
new file mode 100644
index 000000000000..9333d8487071
--- /dev/null
+++ b/libcxx/modules/std.compat/cstdlib.inc
@@ -0,0 +1,72 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+export {
+  using ::div_t;
+  using ::ldiv_t;
+  using ::lldiv_t;
+  using ::size_t;
+
+  // [support.start.term], start and termination
+  using ::_Exit;
+  using ::abort;
+  using ::at_quick_exit;
+  using ::atexit;
+  using ::exit;
+  using ::quick_exit;
+
+  using ::getenv;
+  using ::system;
+
+  // [c.malloc], C library memory allocation
+  using ::aligned_alloc;
+  using ::calloc;
+  using ::free;
+  using ::malloc;
+  using ::realloc;
+
+  using ::atof;
+  using ::atoi;
+  using ::atol;
+  using ::atoll;
+  using ::strtod;
+  using ::strtof;
+  using ::strtol;
+  using ::strtold;
+  using ::strtoll;
+  using ::strtoul;
+  using ::strtoull;
+
+  // [c.mb.wcs], multibyte / wide string and character conversion functions
+  using ::mblen;
+#ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS
+  using ::mbstowcs;
+  using ::mbtowc;
+  using ::wcstombs;
+  using ::wctomb;
+#endif
+  // [alg.c.library], C standard library algorithms
+  using ::bsearch;
+  using ::qsort;
+
+  // [c.math.rand], low-quality random number generation
+  using ::rand;
+  using ::srand;
+
+  // [c.math.abs], absolute values
+  using ::abs;
+
+  using ::labs;
+  using ::llabs;
+
+  using ::div;
+  using ::ldiv;
+  using ::lldiv;
+
+} // export
diff --git a/libcxx/modules/std.compat/cstring.inc b/libcxx/modules/std.compat/cstring.inc
new file mode 100644
index 000000000000..090350ae8147
--- /dev/null
+++ b/libcxx/modules/std.compat/cstring.inc
@@ -0,0 +1,36 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+export {
+  using ::size_t;
+
+  using ::memchr;
+  using ::memcmp;
+  using ::memcpy;
+  using ::memmove;
+  using ::memset;
+  using ::strcat;
+  using ::strchr;
+  using ::strcmp;
+  using ::strcoll;
+  using ::strcpy;
+  using ::strcspn;
+  using ::strerror;
+  using ::strlen;
+  using ::strncat;
+  using ::strncmp;
+  using ::strncpy;
+  using ::strpbrk;
+  using ::strrchr;
+  using ::strspn;
+  using ::strstr;
+  using ::strtok;
+  using ::strxfrm;
+
+} // export
diff --git a/libcxx/modules/std.compat/ctime.inc b/libcxx/modules/std.compat/ctime.inc
new file mode 100644
index 000000000000..92e3403a5e58
--- /dev/null
+++ b/libcxx/modules/std.compat/ctime.inc
@@ -0,0 +1,28 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+export {
+  using ::clock_t;
+  using ::size_t;
+  using ::time_t;
+
+  using ::timespec;
+  using ::tm;
+
+  using ::asctime;
+  using ::clock;
+  using ::ctime;
+  using ::difftime;
+  using ::gmtime;
+  using ::localtime;
+  using ::mktime;
+  using ::strftime;
+  using ::time;
+  using ::timespec_get;
+} // export
diff --git a/libcxx/modules/std.compat/cuchar.inc b/libcxx/modules/std.compat/cuchar.inc
new file mode 100644
index 000000000000..d1a511cadef1
--- /dev/null
+++ b/libcxx/modules/std.compat/cuchar.inc
@@ -0,0 +1,28 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+export {
+  // Note the Standard does not mark these symbols optional, but libc++'s header
+  // does. So this seems strictly not to be conforming.
+
+  // mbstate_t is conditionally here, but always present in cwchar.cppm. To avoid
+  // conflicing declarations omit the using here.
+
+  // size_t is conditionally here, but always present in cstddef.cppm. To avoid
+  // conflicing declarations omit the using here.
+
+#if !defined(_LIBCPP_HAS_NO_C8RTOMB_MBRTOC8)
+  using ::mbrtoc8 _LIBCPP_USING_IF_EXISTS;
+  using ::c8rtomb _LIBCPP_USING_IF_EXISTS;
+#endif
+  using ::mbrtoc16 _LIBCPP_USING_IF_EXISTS;
+  using ::c16rtomb _LIBCPP_USING_IF_EXISTS;
+  using ::mbrtoc32 _LIBCPP_USING_IF_EXISTS;
+  using ::c32rtomb _LIBCPP_USING_IF_EXISTS;
+} // export
diff --git a/libcxx/modules/std.compat/cwchar.inc b/libcxx/modules/std.compat/cwchar.inc
new file mode 100644
index 000000000000..8905aecbdfec
--- /dev/null
+++ b/libcxx/modules/std.compat/cwchar.inc
@@ -0,0 +1,80 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+export {
+#ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS
+  using ::mbstate_t;
+  using ::size_t;
+  using ::wint_t;
+
+  using ::tm;
+
+  using ::btowc;
+  using ::fgetwc;
+  using ::fgetws;
+  using ::fputwc;
+  using ::fputws;
+  using ::fwide;
+  using ::fwprintf;
+  using ::fwscanf;
+  using ::getwc;
+  using ::getwchar;
+  using ::putwc;
+  using ::putwchar;
+  using ::swprintf;
+  using ::swscanf;
+  using ::ungetwc;
+  using ::vfwprintf;
+  using ::vfwscanf;
+  using ::vswprintf;
+  using ::vswscanf;
+  using ::vwprintf;
+  using ::vwscanf;
+  using ::wcscat;
+  using ::wcschr;
+  using ::wcscmp;
+  using ::wcscoll;
+  using ::wcscpy;
+  using ::wcscspn;
+  using ::wcsftime;
+  using ::wcslen;
+  using ::wcsncat;
+  using ::wcsncmp;
+  using ::wcsncpy;
+  using ::wcspbrk;
+  using ::wcsrchr;
+  using ::wcsspn;
+  using ::wcsstr;
+  using ::wcstod;
+  using ::wcstof;
+  using ::wcstok;
+  using ::wcstol;
+  using ::wcstold;
+  using ::wcstoll;
+  using ::wcstoul;
+  using ::wcstoull;
+  using ::wcsxfrm;
+  using ::wctob;
+  using ::wmemchr;
+  using ::wmemcmp;
+  using ::wmemcpy;
+  using ::wmemmove;
+  using ::wmemset;
+  using ::wprintf;
+  using ::wscanf;
+
+  // [c.mb.wcs], multibyte / wide string and character conversion functions
+  using ::mbrlen;
+  using ::mbrtowc;
+  using ::mbsinit;
+  using ::mbsrtowcs;
+  using ::wcrtomb;
+  using ::wcsrtombs;
+#endif // _LIBCPP_HAS_NO_WIDE_CHARACTERS
+} // export
diff --git a/libcxx/modules/std.compat/cwctype.inc b/libcxx/modules/std.compat/cwctype.inc
new file mode 100644
index 000000000000..13aa2b7f3fb7
--- /dev/null
+++ b/libcxx/modules/std.compat/cwctype.inc
@@ -0,0 +1,35 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+export {
+#ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS
+  using ::wctrans_t;
+  using ::wctype_t;
+  using ::wint_t;
+
+  using ::iswalnum;
+  using ::iswalpha;
+  using ::iswblank;
+  using ::iswcntrl;
+  using ::iswctype;
+  using ::iswdigit;
+  using ::iswgraph;
+  using ::iswlower;
+  using ::iswprint;
+  using ::iswpunct;
+  using ::iswspace;
+  using ::iswupper;
+  using ::iswxdigit;
+  using ::towctrans;
+  using ::towlower;
+  using ::towupper;
+  using ::wctrans;
+  using ::wctype;
+#endif // _LIBCPP_HAS_NO_WIDE_CHARACTERS
+} // export
diff --git a/libcxx/modules/std.cppm.in b/libcxx/modules/std.cppm.in
index ecb060126032..b46c52e781f8 100644
--- a/libcxx/modules/std.cppm.in
+++ b/libcxx/modules/std.cppm.in
@@ -8,7 +8,7 @@
 //===----------------------------------------------------------------------===//
 
 // WARNING, this entire header is generated by
-// utils/generate_std_cppm_in.py
+// utils/generate_libcxx_cppm_in.py
 // DO NOT MODIFY!
 
 module;
@@ -169,38 +169,38 @@ module;
 
 // *** Headers not yet available ***
 #if __has_include(<debugging>)
-#  error "update the header information for <debugging> in libcxx/utils/generate_std_cppm_in.py"
-#endif //   __has_include(<debugging>)
+#  error "please update the header information for <debugging> in headers_not_available in utils/libcxx/header_information.py"
+#endif // __has_include(<debugging>)
 #if __has_include(<flat_map>)
-#  error "update the header information for <flat_map> in libcxx/utils/generate_std_cppm_in.py"
-#endif //   __has_include(<flat_map>)
+#  error "please update the header information for <flat_map> in headers_not_available in utils/libcxx/header_information.py"
+#endif // __has_include(<flat_map>)
 #if __has_include(<flat_set>)
-#  error "update the header information for <flat_set> in libcxx/utils/generate_std_cppm_in.py"
-#endif //   __has_include(<flat_set>)
+#  error "please update the header information for <flat_set> in headers_not_available in utils/libcxx/header_information.py"
+#endif // __has_include(<flat_set>)
 #if __has_include(<generator>)
-#  error "update the header information for <generator> in libcxx/utils/generate_std_cppm_in.py"
-#endif //   __has_include(<generator>)
+#  error "please update the header information for <generator> in headers_not_available in utils/libcxx/header_information.py"
+#endif // __has_include(<generator>)
 #if __has_include(<hazard_pointer>)
-#  error "update the header information for <hazard_pointer> in libcxx/utils/generate_std_cppm_in.py"
-#endif //   __has_include(<hazard_pointer>)
+#  error "please update the header information for <hazard_pointer> in headers_not_available in utils/libcxx/header_information.py"
+#endif // __has_include(<hazard_pointer>)
 #if __has_include(<linalg>)
-#  error "update the header information for <linalg> in libcxx/utils/generate_std_cppm_in.py"
-#endif //   __has_include(<linalg>)
+#  error "please update the header information for <linalg> in headers_not_available in utils/libcxx/header_information.py"
+#endif // __has_include(<linalg>)
 #if __has_include(<rcu>)
-#  error "update the header information for <rcu> in libcxx/utils/generate_std_cppm_in.py"
-#endif //   __has_include(<rcu>)
+#  error "please update the header information for <rcu> in headers_not_available in utils/libcxx/header_information.py"
+#endif // __has_include(<rcu>)
 #if __has_include(<spanstream>)
-#  error "update the header information for <spanstream> in libcxx/utils/generate_std_cppm_in.py"
-#endif //   __has_include(<spanstream>)
+#  error "please update the header information for <spanstream> in headers_not_available in utils/libcxx/header_information.py"
+#endif // __has_include(<spanstream>)
 #if __has_include(<stacktrace>)
-#  error "update the header information for <stacktrace> in libcxx/utils/generate_std_cppm_in.py"
-#endif //   __has_include(<stacktrace>)
+#  error "please update the header information for <stacktrace> in headers_not_available in utils/libcxx/header_information.py"
+#endif // __has_include(<stacktrace>)
 #if __has_include(<stdfloat>)
-#  error "update the header information for <stdfloat> in libcxx/utils/generate_std_cppm_in.py"
-#endif //   __has_include(<stdfloat>)
+#  error "please update the header information for <stdfloat> in headers_not_available in utils/libcxx/header_information.py"
+#endif // __has_include(<stdfloat>)
 #if __has_include(<text_encoding>)
-#  error "update the header information for <text_encoding> in libcxx/utils/generate_std_cppm_in.py"
-#endif //   __has_include(<text_encoding>)
+#  error "please update the header information for <text_encoding> in headers_not_available in utils/libcxx/header_information.py"
+#endif // __has_include(<text_encoding>)
 
 export module std;
 
diff --git a/libcxx/test/libcxx/module_std.gen.py b/libcxx/test/libcxx/module_std.gen.py
index d8198cc70583..8e03d6e5b5b5 100644
--- a/libcxx/test/libcxx/module_std.gen.py
+++ b/libcxx/test/libcxx/module_std.gen.py
@@ -21,241 +21,17 @@
 import sys
 
 sys.path.append(sys.argv[1])
-from libcxx.header_information import module_headers
-from libcxx.header_information import header_restrictions
-
-BLOCKLIT = (
-    ""  # block Lit from interpreting a RUN/XFAIL/etc inside the generation script
+from libcxx.test.modules import module_test_generator
+
+generator = module_test_generator(
+    "%t",
+    "%{module}",
+    "%{clang-tidy}",
+    "%{test-tools}/clang_tidy_checks/libcxx-tidy.plugin",
+    "%{cxx}",
+    "%{flags} %{compile_flags}",
 )
 
-# Ignore several declarations found in the includes.
-#
-# Part of these items are bugs other are not yet implemented features.
-SkipDeclarations = dict()
-
-# See comment in the header.
-SkipDeclarations["cuchar"] = ["std::mbstate_t", "std::size_t"]
-
-# Not in the synopsis.
-SkipDeclarations["cwchar"] = ["std::FILE"]
-
-# The operators are added for private types like __iom_t10.
-SkipDeclarations["iomanip"] = ["std::operator<<", "std::operator>>"]
-
-SkipDeclarations["iosfwd"] = ["std::ios_base", "std::vector"]
-
-# This header also provides declarations in the namespace that might be
-# an error.
-SkipDeclarations["filesystem"] = [
-    "std::filesystem::operator==",
-    "std::filesystem::operator!=",
-]
-
-# This is a specialization for a private type
-SkipDeclarations["iterator"] = ["std::pointer_traits"]
-
-# TODO MODULES
-# This definition is declared in string and defined in istream
-# This declaration should be part of string
-SkipDeclarations["istream"] = ["std::getline"]
-
-# P1614 (at many places) and LWG3519 too.
-SkipDeclarations["random"] = [
-    "std::operator!=",
-    # LWG3519 makes these hidden friends.
-    # Note the older versions had the requirement of these operations but not in
-    # the synopsis.
-    "std::operator<<",
-    "std::operator>>",
-    "std::operator==",
-]
-
-# Declared in the forward header since std::string uses std::allocator
-SkipDeclarations["string"] = ["std::allocator"]
-# TODO MODULES remove zombie names
-# https://libcxx.llvm.org/Status/Cxx20.html#note-p0619
-SkipDeclarations["memory"] = [
-    "std::return_temporary_buffer",
-    "std::get_temporary_buffer",
-]
-
-# TODO MODULES this should be part of ios instead
-SkipDeclarations["streambuf"] = ["std::basic_ios"]
-
-# include/__type_traits/is_swappable.h
-SkipDeclarations["type_traits"] = [
-    "std::swap",
-    # TODO MODULES gotten through __functional/unwrap_ref.h
-    "std::reference_wrapper",
-]
-
-# Add declarations in headers.
-#
-# Some headers have their defines in a different header, which may have
-# additional declarations.
-ExtraDeclarations = dict()
-# This declaration is in the ostream header.
-ExtraDeclarations["system_error"] = ["std::operator<<"]
-
-# Adds an extra header file to scan
-#
-#
-ExtraHeader = dict()
-# locale has a file and not a subdirectory
-ExtraHeader["locale"] = "v1/__locale$"
-ExtraHeader["thread"] = "v1/__threading_support$"
-ExtraHeader["ranges"] = "v1/__fwd/subrange.h$"
-
-# The extra header is needed since two headers are required to provide the
-# same definition.
-ExtraHeader["functional"] = "v1/__compare/compare_three_way.h$"
-
-# newline needs to be escaped for the module partition output.
-nl = '\\\\n'
-
-# Create empty file with all parts.
-print(
-    f"""\
-//--- module_std.sh.cpp
-// UNSUPPORTED{BLOCKLIT}: c++03, c++11, c++14, c++17
-// UNSUPPORTED{BLOCKLIT}: libcpp-has-no-std-modules
-// UNSUPPORTED{BLOCKLIT}: clang-modules-build
-
-// REQUIRES{BLOCKLIT}: has-clang-tidy
-
-// The GCC compiler flags are not always compatible with clang-tidy.
-// UNSUPPORTED{BLOCKLIT}: gcc
-
-// RUN{BLOCKLIT}: echo -n > %t.all_partitions
-"""
-)
-
-# Validate all module parts.
-for header in module_headers:
-    # Some headers cannot be included when a libc++ feature is disabled.
-    # In that case include the header conditionally. The header __config
-    # ensures the libc++ feature macros are available.
-    if header in header_restrictions:
-        include = (
-            f"#include <__config>{nl}"
-            + f"#if {header_restrictions[header]}{nl}"
-            + f"#  include <{header}>{nl}"
-            + f"#endif{nl}"
-        )
-    elif header == "chrono":
-        # When localization is disabled the header string is not included.
-        # When string is included chrono's operator""s is a named declaration
-        #   using std::chrono_literals::operator""s;
-        # else it is a named declaration
-        #   using std::operator""s;
-        # TODO MODULES investigate why
-        include = f"#include <string>{nl}#include <chrono>{nl}"
-    else:
-        include = f"#include <{header}>{nl}"
-
-    # Generate a module partition for the header module includes. This
-    # makes it possible to verify that all headers export all their
-    # named declarations.
-    print(
-        f"// RUN{BLOCKLIT}: echo -e \""
-        f"module;{nl}"
-        f"{include}"
-        f"{nl}"
-        f"// Use __libcpp_module_<HEADER> to ensure that modules {nl}"
-        f"// are not named as keywords or reserved names.{nl}"
-        f"export module std:__libcpp_module_{header};{nl}"
-        f'#include \\"%{{module}}/std/{header}.inc\\"{nl}'
-        f"\" > %t.{header}.cppm")
-
-    # Dump the information as found in the module's cppm file.
-    print(
-        f"// RUN{BLOCKLIT}: %{{clang-tidy}} %t.{header}.cppm "
-        "  --checks='-*,libcpp-header-exportable-declarations' "
-        "  -config='{CheckOptions: [ "
-        "    {"
-        "      key: libcpp-header-exportable-declarations.Filename, "
-        f"     value: {header}.inc"
-        "    }, {"
-        "      key: libcpp-header-exportable-declarations.FileType, "
-        "      value: ModulePartition"
-        "    }, "
-        "  ]}' "
-        "  --load=%{test-tools}/clang_tidy_checks/libcxx-tidy.plugin "
-        "  -- %{flags} %{compile_flags} "
-        f"| sort > %t.{header}.module"
-    )
-    print(f"// RUN{BLOCKLIT}: cat  %t.{header}.module >> %t.all_partitions")
-
-    # Dump the information as found in the module by using the header file(s).
-    skip_declarations = " ".join(SkipDeclarations.get(header, []))
-    if skip_declarations:
-        skip_declarations = (
-            "{"
-            "  key: libcpp-header-exportable-declarations.SkipDeclarations, "
-            f' value: "{skip_declarations}" '
-            "}, "
-        )
-
-    extra_declarations = " ".join(ExtraDeclarations.get(header, []))
-    if extra_declarations:
-        extra_declarations = (
-            " {"
-            "  key: libcpp-header-exportable-declarations.ExtraDeclarations, "
-            f' value: "{extra_declarations}" '
-            "}, "
-        )
-
-    extra_header = ExtraHeader.get(header, "")
-    if extra_header:
-        extra_header = (
-            "{"
-            "  key: libcpp-header-exportable-declarations.ExtraHeader, "
-            f' value: "{extra_header}" '
-            "}, "
-        )
-
-    # Clang-tidy needs a file input
-    print(f'// RUN{BLOCKLIT}: echo -e "' f"{include}" f'" > %t.{header}.cpp')
-    print(
-        f"// RUN{BLOCKLIT}: %{{clang-tidy}} %t.{header}.cpp "
-        "  --checks='-*,libcpp-header-exportable-declarations' "
-        "  -config='{CheckOptions: [ "
-        f"   {{key: libcpp-header-exportable-declarations.Filename, value: {header}}}, "
-        "    {key: libcpp-header-exportable-declarations.FileType, value: Header}, "
-        f"   {skip_declarations} {extra_declarations} {extra_header}, "
-        "  ]}' "
-        "  --load=%{test-tools}/clang_tidy_checks/libcxx-tidy.plugin "
-        "  -- %{flags} %{compile_flags} "
-        f" | sort > %t.{header}.include"
-    )
-
-    # Compare the cppm and header file(s) return the same results.
-    print(f"// RUN{BLOCKLIT}: diff -u %t.{header}.module %t.{header}.include")
-
-
-# Merge the data of the parts
-print(f"// RUN{BLOCKLIT}: sort -u -o %t.all_partitions %t.all_partitions")
-
-# Dump the information as found in std.cppm.
-print(
-    f"// RUN{BLOCKLIT}: %{{clang-tidy}} %{{module}}/std.cppm "
-    "  --checks='-*,libcpp-header-exportable-declarations' "
-    "  -config='{CheckOptions: [ "
-    "    {key: libcpp-header-exportable-declarations.Header, value: std.cppm}, "
-    "    {key: libcpp-header-exportable-declarations.FileType, value: Module}, "
-    "  ]}' "
-    f" --load=%{{test-tools}}/clang_tidy_checks/libcxx-tidy.plugin "
-    "  -- %{flags} %{compile_flags} "
-    "  | sort > %t.module"
-)
-
-
-# Compare the sum of the parts with the main module.
-print(f"// RUN{BLOCKLIT}: diff -u %t.all_partitions %t.module")
 
-# Basic smoke test. Import a module and try to compile when using all
-# exported names. This validates the clang-tidy script does not accidentally
-# add named declarations to the list that are not available.
-print(f"// RUN{BLOCKLIT}: echo 'import std;' > %t.compile.pass.cpp")
-print(f"// RUN{BLOCKLIT}: cat %t.all_partitions >> %t.compile.pass.cpp")
-print(f"// RUN{BLOCKLIT}: %{{cxx}} %{{flags}} %{{compile_flags}} -fsyntax-only %t.compile.pass.cpp")
+print("//--- module_std.sh.cpp")
+generator.write_test("std")
diff --git a/libcxx/test/libcxx/module_std_compat.gen.py b/libcxx/test/libcxx/module_std_compat.gen.py
new file mode 100644
index 000000000000..c4792db3d71e
--- /dev/null
+++ b/libcxx/test/libcxx/module_std_compat.gen.py
@@ -0,0 +1,62 @@
+# ===----------------------------------------------------------------------===##
+#
+# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+# See https://llvm.org/LICENSE.txt for license information.
+# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+#
+# ===----------------------------------------------------------------------===##
+
+# Test that all named declarations with external linkage match the
+# exported declarations in their associated module partition.
+# Then it tests the sum of the exported declarations in the module
+# partitions matches the export of the std.compat module.
+
+# Note the test of the std.compat module requires all partitions to be tested
+# first. Since lit tests have no dependencies, this means the test needs
+# to be one monolitic test. Since the test doesn't take very long it's
+# not a huge issue.
+
+# RUN: %{python} %s %{libcxx}/utils
+
+import sys
+
+sys.path.append(sys.argv[1])
+from libcxx.test.modules import module_test_generator
+
+generator = module_test_generator(
+    "%t",
+    "%{module}",
+    "%{clang-tidy}",
+    "%{test-tools}/clang_tidy_checks/libcxx-tidy.plugin",
+    "%{cxx}",
+    "%{flags} %{compile_flags}",
+)
+
+
+print("//--- module_std_compat.sh.cpp")
+generator.write_test(
+    "std.compat",
+    [
+        "cassert",
+        "cctype",
+        "cerrno",
+        "cfenv",
+        "cfloat",
+        "cinttypes",
+        "climits",
+        "clocale",
+        "cmath",
+        "csetjmp",
+        "csignal",
+        "cstdarg",
+        "cstddef",
+        "cstdint",
+        "cstdio",
+        "cstdlib",
+        "cstring",
+        "ctime",
+        "cuchar",
+        "cwchar",
+        "cwctype",
+    ],
+)
diff --git a/libcxx/test/lit.local.cfg b/libcxx/test/lit.local.cfg
index 4116553b6f7a..1ee9086ee22e 100644
--- a/libcxx/test/lit.local.cfg
+++ b/libcxx/test/lit.local.cfg
@@ -67,3 +67,17 @@ if (
         "%{link_flags}",
         os.path.join(build, "libc++std.a"),
     )
+
+    config.substitutions = appendToSubstitution(
+        config.substitutions,
+        "%{compile_flags}",
+        "-fprebuilt-module-path="
+        + os.path.join(
+            config.test_exec_root, "__config_module__/CMakeFiles/std.compat.dir"
+        ),
+    )
+    config.substitutions = appendToSubstitution(
+        config.substitutions,
+        "%{link_flags}",
+        os.path.join(build, "libc++std.compat.a"),
+    )
diff --git a/libcxx/test/std/modules/std.compat.pass.cpp b/libcxx/test/std/modules/std.compat.pass.cpp
new file mode 100644
index 000000000000..a33ed3b6b645
--- /dev/null
+++ b/libcxx/test/std/modules/std.compat.pass.cpp
@@ -0,0 +1,18 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+// UNSUPPORTED: c++03, c++11, c++14, c++17
+
+// UNSUPPORTED: libcpp-has-no-std-modules
+// UNSUPPORTED: clang-modules-build
+
+// A minimal test to validate import works.
+
+import std.compat;
+
+int main(int, char**) { return !(::strlen("Hello modular world") == 19); }
diff --git a/libcxx/test/tools/clang_tidy_checks/header_exportable_declarations.cpp b/libcxx/test/tools/clang_tidy_checks/header_exportable_declarations.cpp
index fba48d5984ea..fcb5865adf0d 100644
--- a/libcxx/test/tools/clang_tidy_checks/header_exportable_declarations.cpp
+++ b/libcxx/test/tools/clang_tidy_checks/header_exportable_declarations.cpp
@@ -26,7 +26,10 @@ struct clang::tidy::OptionEnumMapping<libcpp::header_exportable_declarations::Fi
     static constexpr std::pair<libcpp::header_exportable_declarations::FileType, llvm::StringRef> Mapping[] = {
         {libcpp::header_exportable_declarations::FileType::Header, "Header"},
         {libcpp::header_exportable_declarations::FileType::ModulePartition, "ModulePartition"},
-        {libcpp::header_exportable_declarations::FileType::Module, "Module"}};
+        {libcpp::header_exportable_declarations::FileType::Module, "Module"},
+        {libcpp::header_exportable_declarations::FileType::CHeader, "CHeader"},
+        {libcpp::header_exportable_declarations::FileType::CompatModulePartition, "CompatModulePartition"},
+        {libcpp::header_exportable_declarations::FileType::CompatModule, "CompatModule"}};
     return ArrayRef(Mapping);
   }
 };
@@ -39,6 +42,7 @@ header_exportable_declarations::header_exportable_declarations(
       file_type_(Options.get("FileType", header_exportable_declarations::FileType::Unknown)),
       extra_header_(Options.get("ExtraHeader", "")) {
   switch (file_type_) {
+  case header_exportable_declarations::FileType::CHeader:
   case header_exportable_declarations::FileType::Header:
     if (filename_.empty())
       llvm::errs() << "No filename is provided.\n";
@@ -46,10 +50,12 @@ header_exportable_declarations::header_exportable_declarations(
       extra_header_ = "$^"; // Use a never matching regex to silence an error message.
     break;
   case header_exportable_declarations::FileType::ModulePartition:
+  case header_exportable_declarations::FileType::CompatModulePartition:
     if (filename_.empty())
       llvm::errs() << "No filename is provided.\n";
     [[fallthrough]];
   case header_exportable_declarations::FileType::Module:
+  case header_exportable_declarations::FileType::CompatModule:
     if (!extra_header_.empty())
       llvm::errs() << "Extra headers are not allowed for modules.\n";
     if (Options.get("SkipDeclarations"))
@@ -70,7 +76,7 @@ header_exportable_declarations::header_exportable_declarations(
     auto b             = s.begin();
     auto e             = std::find(b, s.end(), ' ');
     while (b != e) {
-      decls_.emplace(b, e);
+      skip_decls_.emplace(b, e);
       if (e == s.end())
         break;
       b = e + 1;
@@ -82,9 +88,10 @@ header_exportable_declarations::header_exportable_declarations(
     for (auto decl : std::views::split(*list, ' ')) {
       std::string s;
       std::ranges::copy(decl, std::back_inserter(s)); // use range based constructor
-      decls_.emplace(std::move(s));
+      skip_decls_.emplace(std::move(s));
     }
 #endif // defined(__clang_major__) && __clang_major__ < 16
+  decls_ = skip_decls_;
 
   list = Options.get("ExtraDeclarations");
   // TODO(LLVM-17) Remove clang 15 work-around.
@@ -94,7 +101,7 @@ header_exportable_declarations::header_exportable_declarations(
     auto b             = s.begin();
     auto e             = std::find(b, s.end(), ' ');
     while (b != e) {
-      std::cout << "using " << std::string_view{b, e} << ";\n";
+      std::cout << "using ::" << std::string_view{b, e} << ";\n";
       if (e == s.end())
         break;
       b = e + 1;
@@ -104,10 +111,16 @@ header_exportable_declarations::header_exportable_declarations(
 #else  // defined(__clang_major__) && __clang_major__ < 16
   if (list)
     for (auto decl : std::views::split(*list, ' '))
-      std::cout << "using " << std::string_view{decl.data(), decl.size()} << ";\n";
+      std::cout << "using ::" << std::string_view{decl.data(), decl.size()} << ";\n";
 #endif // defined(__clang_major__) && __clang_major__ < 16
 }
 
+header_exportable_declarations::~header_exportable_declarations() {
+  for (const auto& name : global_decls_)
+    if (!skip_decls_.contains("std::" + name) && decls_.contains("std::" + name))
+      std::cout << "using ::" << name << ";\n";
+}
+
 void header_exportable_declarations::registerMatchers(clang::ast_matchers::MatchFinder* finder) {
   // there are no public names in the Standard starting with an underscore, so
   // no need to check the strict rules.
@@ -129,10 +142,22 @@ void header_exportable_declarations::registerMatchers(clang::ast_matchers::Match
             .bind("header_exportable_declarations"),
         this);
     break;
+  case FileType::CHeader:
+    // For C headers of the std.compat two matchers are used
+    // - The cheader matcher; in libc++ these are never split in multiple
+    //   headers so limiting the declarations to that header works.
+    // - The header.h; where the declarations of this header are provided
+    //   is not specified and depends on the libc used. Therefore it is not
+    //   possible to restrict the location in a portable way.
+    finder->addMatcher(namedDecl().bind("cheader_exportable_declarations"), this);
+
+    [[fallthrough]];
   case FileType::ModulePartition:
+  case FileType::CompatModulePartition:
     finder->addMatcher(namedDecl(isExpansionInFileMatching(filename_)).bind("header_exportable_declarations"), this);
     break;
   case FileType::Module:
+  case FileType::CompatModule:
     finder->addMatcher(namedDecl().bind("header_exportable_declarations"), this);
     break;
   case header_exportable_declarations::FileType::Unknown:
@@ -156,6 +181,9 @@ void header_exportable_declarations::registerMatchers(clang::ast_matchers::Match
 /// * cstddef has bitwise operators for the type \c byte
 /// * exception has equality operators for the type \c exception_ptr
 /// * initializer_list has the functions \c begin and \c end
+///
+/// \warning In some cases the returned name can be an empty string.
+/// The cause has not been investigated.
 static std::string get_qualified_name(const clang::NamedDecl& decl) {
   std::string result = decl.getQualifiedNameAsString();
 
@@ -166,10 +194,6 @@ static std::string get_qualified_name(const clang::NamedDecl& decl) {
 }
 
 static bool is_viable_declaration(const clang::NamedDecl* decl) {
-  // Declarations nested in records are automatically exported with the record itself.
-  if (!decl->getDeclContext()->isNamespace())
-    return false;
-
   // Declarations that are a subobject of a friend Declaration are automatically exported with the record itself.
   if (decl->getFriendObjectKind() != clang::Decl::FOK_None)
     return false;
@@ -199,13 +223,21 @@ static bool is_viable_declaration(const clang::NamedDecl* decl) {
 /// Returns the name is a reserved name.
 ///
 /// Detected reserved names are names starting with __ or _[A-Z].
-/// These names can be in the namespace std or any namespace inside std. For
-/// example std::ranges contains reserved names to implement the Niebloids.
+/// These names can be in the global namespace, std namespace or any namespace
+/// inside std. For example, std::ranges contains reserved names to implement
+/// the Niebloids.
 ///
-/// This test misses 2 candidates which are not used in libc++
+/// This test misses candidates which are not used in libc++
 /// * any identifier with two underscores not at the start
-/// * a name with a leading underscore in the global namespace
-bool is_reserved_name(const std::string& name) {
+bool is_reserved_name(std::string_view name) {
+  if (name.starts_with("_")) {
+    // This is a public name declared in cstdlib.
+    if (name == "_Exit")
+      return false;
+
+    return name.size() > 1 && (name[1] == '_' || std::isupper(name[1]));
+  }
+
   std::size_t pos = name.find("::_");
   if (pos == std::string::npos)
     return false;
@@ -213,27 +245,73 @@ bool is_reserved_name(const std::string& name) {
   if (pos + 3 > name.size())
     return false;
 
+  // This is a public name declared in cstdlib.
+  if (name == "std::_Exit")
+    return false;
+
   return name[pos + 3] == '_' || std::isupper(name[pos + 3]);
 }
 
+/// Some declarations in the global namespace are exported from the std module.
+static bool is_global_name_exported_by_std_module(std::string_view name) {
+  static const std::set<std::string_view> valid{
+      "operator delete", "operator delete[]", "operator new", "operator new[]"};
+  return valid.contains(name);
+}
+
+static bool is_valid_declaration_context(
+    const clang::NamedDecl& decl, std::string_view name, header_exportable_declarations::FileType file_type) {
+  if (decl.getDeclContext()->isNamespace())
+    return true;
+
+  if (is_global_name_exported_by_std_module(name))
+    return true;
+
+  return file_type != header_exportable_declarations::FileType::Header;
+}
+
+static bool is_module(header_exportable_declarations::FileType file_type) {
+  switch (file_type) {
+  case header_exportable_declarations::FileType::Module:
+  case header_exportable_declarations::FileType::ModulePartition:
+  case header_exportable_declarations::FileType::CompatModule:
+  case header_exportable_declarations::FileType::CompatModulePartition:
+    return true;
+
+  case header_exportable_declarations::FileType::Header:
+  case header_exportable_declarations::FileType::CHeader:
+    return false;
+
+  case header_exportable_declarations::FileType::Unknown:
+    llvm::errs() << "This should be unreachable.\n";
+    break;
+  }
+}
+
 void header_exportable_declarations::check(const clang::ast_matchers::MatchFinder::MatchResult& result) {
   if (const auto* decl = result.Nodes.getNodeAs<clang::NamedDecl>("header_exportable_declarations"); decl != nullptr) {
     if (!is_viable_declaration(decl))
       return;
 
     std::string name = get_qualified_name(*decl);
+    if (name.empty())
+      return;
+
     if (is_reserved_name(name))
       return;
 
     // For modules only take the declarations exported.
-    if (file_type_ == FileType::ModulePartition || file_type_ == FileType::Module)
+    if (is_module(file_type_))
       if (decl->getModuleOwnershipKind() != clang::Decl::ModuleOwnershipKind::VisibleWhenImported)
         return;
 
+    if (!is_valid_declaration_context(*decl, name, file_type_))
+      return;
+
     if (decls_.contains(name)) {
       // For modules avoid exporting the same named declaration twice. For
       // header files this is common and valid.
-      if (file_type_ == FileType::ModulePartition)
+      if (file_type_ == FileType::ModulePartition || file_type_ == FileType::CompatModulePartition)
         // After the warning the script continues.
         // The test will fail since modules have duplicated entries and headers not.
         llvm::errs() << "Duplicated export of '" << name << "'.\n";
@@ -241,8 +319,30 @@ void header_exportable_declarations::check(const clang::ast_matchers::MatchFinde
         return;
     }
 
-    std::cout << "using " << std::string{name} << ";\n";
+    // For named declarations in std this is valid
+    //   using std::foo;
+    // for named declarations it is invalid to use
+    //   using bar;
+    // Since fully qualifying named declarations in the std namespace is valid
+    // using fully qualified names unconditionally.
+    std::cout << "using ::" << std::string{name} << ";\n";
     decls_.insert(name);
+  } else if (const auto* decl = result.Nodes.getNodeAs<clang::NamedDecl>("cheader_exportable_declarations");
+             decl != nullptr) {
+    if (decl->getDeclContext()->isNamespace())
+      return;
+
+    if (!is_viable_declaration(decl))
+      return;
+
+    std::string name = get_qualified_name(*decl);
+    if (is_reserved_name(name))
+      return;
+
+    if (global_decls_.contains(name))
+      return;
+
+    global_decls_.insert(name);
   }
 }
 
diff --git a/libcxx/test/tools/clang_tidy_checks/header_exportable_declarations.hpp b/libcxx/test/tools/clang_tidy_checks/header_exportable_declarations.hpp
index 119bcd3f6f2f..5d9e0f3ef9c3 100644
--- a/libcxx/test/tools/clang_tidy_checks/header_exportable_declarations.hpp
+++ b/libcxx/test/tools/clang_tidy_checks/header_exportable_declarations.hpp
@@ -18,15 +18,47 @@ namespace libcpp {
 class header_exportable_declarations : public clang::tidy::ClangTidyCheck {
 public:
   explicit header_exportable_declarations(llvm::StringRef, clang::tidy::ClangTidyContext*);
+  ~header_exportable_declarations();
   void registerMatchers(clang::ast_matchers::MatchFinder*) override;
   void check(const clang::ast_matchers::MatchFinder::MatchResult&) override;
 
-  enum class FileType { Header, ModulePartition, Module, Unknown };
+  enum class FileType {
+    // std module specific
+    Header,
+    CompatModulePartition,
+    Module,
+    // std.compat module specific
+    CHeader,
+    ModulePartition,
+    CompatModule,
+    // invalid value
+    Unknown
+  };
 
 private:
   llvm::StringRef filename_;
   FileType file_type_;
   llvm::StringRef extra_header_;
   std::set<std::string> decls_;
+  std::set<std::string> global_decls_;
+
+  // The named declarations in .h C headers are "tricky". On POSIX
+  // systems these headers contain POSIX specific functions that do not
+  // use a reserved name. For example, fmemopen is provided by stdio.h.
+  // We filter the names that should be provided by the headers as follows:
+  // - record all named declarations the global namespace
+  // - wait until the header is completely processed
+  // - every named declaration in the global namespace that has a matching
+  //   "export" in the std namespace is exported.
+  //
+  // The only place where we can do the above while ensuring that all
+  // the declarations in the header have been seen is in the clang tidy
+  // plugin's destructor.
+  //
+  // It is possible to skip some declarations in the std namespace,
+  // these are added to decls_ before processing. To differentiate
+  // between a skipped declaration and a real declaration the skipped
+  // declarations are recorded in an extra variable.
+  std::set<std::string> skip_decls_;
 };
 } // namespace libcpp
diff --git a/libcxx/utils/CMakeLists.txt b/libcxx/utils/CMakeLists.txt
index 7e597f632b6c..19bb9851c867 100644
--- a/libcxx/utils/CMakeLists.txt
+++ b/libcxx/utils/CMakeLists.txt
@@ -7,9 +7,19 @@ add_custom_target(libcxx-generate-std-clang-module-header
   COMMENT "Generate the <__std_clang_module> header")
 
 add_custom_target(libcxx-generate-std-cppm-in-file
-  COMMAND "${Python3_EXECUTABLE}" "${CMAKE_CURRENT_SOURCE_DIR}/generate_std_cppm_in.py"
+  COMMAND
+        "${Python3_EXECUTABLE}"
+		"${LIBCXX_SOURCE_DIR}/utils/generate_libcxx_cppm_in.py"
+		"std"
   COMMENT "Generate the std.cppm.in file")
 
+add_custom_target(libcxx-generate-std-compat-cppm-in-file
+  COMMAND
+        "${Python3_EXECUTABLE}"
+		"${LIBCXX_SOURCE_DIR}/utils/generate_libcxx_cppm_in.py"
+		"std.compat"
+  COMMENT "Generate the std.compat.cppm.in file")
+
 add_custom_target(libcxx-generate-extended-grapheme-cluster-tables
     COMMAND
         "${Python3_EXECUTABLE}"
@@ -48,6 +58,7 @@ add_custom_target(libcxx-generate-files
     DEPENDS libcxx-generate-feature-test-macros
             libcxx-generate-std-clang-module-header
             libcxx-generate-std-cppm-in-file
+            libcxx-generate-std-compat-cppm-in-file
             libcxx-generate-extended-grapheme-cluster-tables
             libcxx-generate-extended-grapheme-cluster-tests
             libcxx-generate-escaped-output-table
diff --git a/libcxx/utils/generate_std_cppm_in.py b/libcxx/utils/generate_libcxx_cppm_in.py
similarity index 51%
rename from libcxx/utils/generate_std_cppm_in.py
rename to libcxx/utils/generate_libcxx_cppm_in.py
index 242134773e68..f957406778d3 100644
--- a/libcxx/utils/generate_std_cppm_in.py
+++ b/libcxx/utils/generate_libcxx_cppm_in.py
@@ -7,20 +7,22 @@
 # ===----------------------------------------------------------------------===##
 
 import os.path
+import sys
 
 from libcxx.header_information import module_headers
 from libcxx.header_information import header_restrictions
 from libcxx.header_information import headers_not_available
 
 
-libcxx_module_directory = os.path.join(
-    os.path.dirname(os.path.dirname(os.path.realpath(__file__))), "modules"
-)
-with open(
-    os.path.join(libcxx_module_directory, "std.cppm.in"), "w"
-) as std_module_cpp_in:
-    std_module_cpp_in.write(
-        """\
+def write_file(module):
+    libcxx_module_directory = os.path.join(
+        os.path.dirname(os.path.dirname(os.path.realpath(__file__))), "modules"
+    )
+    with open(
+        os.path.join(libcxx_module_directory, f"{module}.cppm.in"), "w"
+    ) as module_cpp_in:
+        module_cpp_in.write(
+            """\
 // -*- C++ -*-
 //===----------------------------------------------------------------------===//
 //
@@ -31,7 +33,7 @@ with open(
 //===----------------------------------------------------------------------===//
 
 // WARNING, this entire header is generated by
-// utils/generate_std_cppm_in.py
+// utils/generate_libcxx_cppm_in.py
 // DO NOT MODIFY!
 
 module;
@@ -41,33 +43,46 @@ module;
 // The headers of Table 24: C++ library headers [tab:headers.cpp]
 // and the headers of Table 25: C++ headers for C library facilities [tab:headers.cpp.c]
 """
-    )
-    for header in module_headers:
-        if header in header_restrictions:
-            std_module_cpp_in.write(
-                f"""\
+        )
+        for header in module_headers:
+            if header in header_restrictions:
+                module_cpp_in.write(
+                    f"""\
 #if {header_restrictions[header]}
 #  include <{header}>
 #endif
 """
-            )
-        else:
-            std_module_cpp_in.write(f"#include <{header}>\n")
+                )
+            else:
+                module_cpp_in.write(f"#include <{header}>\n")
 
-    std_module_cpp_in.write("\n// *** Headers not yet available ***\n")
-    for header in sorted(headers_not_available):
-        std_module_cpp_in.write(
-            f"""\
+        module_cpp_in.write("\n// *** Headers not yet available ***\n")
+        for header in sorted(headers_not_available):
+            module_cpp_in.write(
+                f"""\
 #if __has_include(<{header}>)
-#  error "update the header information for <{header}> in libcxx/utils/generate_std_cppm_in.py"
-#endif //   __has_include(<{header}>)
+#  error "please update the header information for <{header}> in headers_not_available in utils/libcxx/header_information.py"
+#endif // __has_include(<{header}>)
 """
-        )
+            )
 
-    std_module_cpp_in.write(
-        """
-export module std;
+        module_cpp_in.write(
+            f"""
+export module {module};
 
 @LIBCXX_MODULE_STD_INCLUDE_SOURCES@
+{'@LIBCXX_MODULE_STD_COMPAT_INCLUDE_SOURCES@' if module == 'std.compat' else ''}"""
+        )
+
+
+if __name__ == "__main__":
+    if len(sys.argv) != 2 or (sys.argv[1] != "std" and sys.argv[1] != "std.compat"):
+        sys.stderr.write(
+            f"""\
+Usage:
+{os.path.basename(__file__)} (std|std.compat)
 """
-    )
+        )
+        sys.exit(1)
+
+    write_file(sys.argv[1])
diff --git a/libcxx/utils/libcxx/test/modules.py b/libcxx/utils/libcxx/test/modules.py
new file mode 100644
index 000000000000..deaac450381c
--- /dev/null
+++ b/libcxx/utils/libcxx/test/modules.py
@@ -0,0 +1,302 @@
+# ===----------------------------------------------------------------------===##
+#
+# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+# See https://llvm.org/LICENSE.txt for license information.
+# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+#
+# ===----------------------------------------------------------------------===##
+
+from libcxx.header_information import module_headers
+from libcxx.header_information import header_restrictions
+from dataclasses import dataclass
+
+### SkipDeclarations
+
+# Ignore several declarations found in the includes.
+#
+# Part of these items are bugs other are not yet implemented features.
+SkipDeclarations = dict()
+
+# See comment in the header.
+SkipDeclarations["cuchar"] = ["std::mbstate_t", "std::size_t"]
+
+# Not in the synopsis.
+SkipDeclarations["cwchar"] = ["std::FILE"]
+
+# The operators are added for private types like __iom_t10.
+SkipDeclarations["iomanip"] = ["std::operator<<", "std::operator>>"]
+
+SkipDeclarations["iosfwd"] = ["std::ios_base", "std::vector"]
+
+# This header also provides declarations in the namespace that might be
+# an error.
+SkipDeclarations["filesystem"] = [
+    "std::filesystem::operator==",
+    "std::filesystem::operator!=",
+]
+
+# This is a specialization for a private type
+SkipDeclarations["iterator"] = ["std::pointer_traits"]
+
+# TODO MODULES
+# This definition is declared in string and defined in istream
+# This declaration should be part of string
+SkipDeclarations["istream"] = ["std::getline"]
+
+# P1614 (at many places) and LWG3519 too.
+SkipDeclarations["random"] = [
+    "std::operator!=",
+    # LWG3519 makes these hidden friends.
+    # Note the older versions had the requirement of these operations but not in
+    # the synopsis.
+    "std::operator<<",
+    "std::operator>>",
+    "std::operator==",
+]
+
+# Declared in the forward header since std::string uses std::allocator
+SkipDeclarations["string"] = ["std::allocator"]
+# TODO MODULES remove zombie names
+# https://libcxx.llvm.org/Status/Cxx20.html#note-p0619
+SkipDeclarations["memory"] = [
+    "std::return_temporary_buffer",
+    "std::get_temporary_buffer",
+]
+
+# TODO MODULES this should be part of ios instead
+SkipDeclarations["streambuf"] = ["std::basic_ios"]
+
+# include/__type_traits/is_swappable.h
+SkipDeclarations["type_traits"] = [
+    "std::swap",
+    # TODO MODULES gotten through __functional/unwrap_ref.h
+    "std::reference_wrapper",
+]
+
+### ExtraDeclarations
+
+# Add declarations in headers.
+#
+# Some headers have their defines in a different header, which may have
+# additional declarations.
+ExtraDeclarations = dict()
+# This declaration is in the ostream header.
+ExtraDeclarations["system_error"] = ["std::operator<<"]
+
+### ExtraHeader
+
+# Adds extra headers file to scan
+#
+# Some C++ headers in libc++ are stored in multiple physical files. There is a
+# pattern to find these files. However there are some exceptions these are
+# listed here.
+ExtraHeader = dict()
+# locale has a file and not a subdirectory
+ExtraHeader["locale"] = "v1/__locale$"
+ExtraHeader["thread"] = "v1/__threading_support$"
+ExtraHeader["ranges"] = "v1/__fwd/subrange.h$"
+
+# The extra header is needed since two headers are required to provide the
+# same definition.
+ExtraHeader["functional"] = "v1/__compare/compare_three_way.h$"
+
+
+# newline needs to be escaped for the module partition output.
+nl = "\\\\n"
+
+
+@dataclass
+class module_test_generator:
+    tmp_prefix: str
+    module_path: str
+    clang_tidy: str
+    clang_tidy_plugin: str
+    compiler: str
+    compiler_flags: str
+
+    def write_lit_configuration(self):
+        print(
+            f"""\
+// UNSUPPORTED: c++03, c++11, c++14, c++17
+// UNSUPPORTED: libcpp-has-no-std-modules
+// UNSUPPORTED: clang-modules-build
+
+// REQUIRES: has-clang-tidy
+
+// The GCC compiler flags are not always compatible with clang-tidy.
+// UNSUPPORTED: gcc
+
+// RUN: echo -n > {self.tmp_prefix}.all_partitions
+"""
+        )
+
+    def process_module_partition(self, header, is_c_header):
+        # Some headers cannot be included when a libc++ feature is disabled.
+        # In that case include the header conditionally. The header __config
+        # ensures the libc++ feature macros are available.
+        if header in header_restrictions:
+            include = (
+                f"#include <__config>{nl}"
+                f"#if {header_restrictions[header]}{nl}"
+                f"#  include <{header}>{nl}"
+                f"#endif{nl}"
+            )
+        elif header == "chrono":
+            # When localization is disabled the header string is not included.
+            # When string is included chrono's operator""s is a named declaration
+            #   using std::chrono_literals::operator""s;
+            # else it is a named declaration
+            #   using std::operator""s;
+            # TODO MODULES investigate why
+            include = f"#include <string>{nl}#include <chrono>{nl}"
+        else:
+            include = f"#include <{header}>{nl}"
+
+        module_files = f'#include \\"{self.module_path}/std/{header}.inc\\"{nl}'
+        if is_c_header:
+            module_files += (
+                f'#include \\"{self.module_path}/std.compat/{header}.inc\\"{nl}'
+            )
+
+        # Generate a module partition for the header module includes. This
+        # makes it possible to verify that all headers export all their
+        # named declarations.
+        print(
+            '// RUN: echo -e "'
+            f"module;{nl}"
+            f"{include}{nl}"
+            f"{nl}"
+            f"// Use __libcpp_module_<HEADER> to ensure that modules{nl}"
+            f"// are not named as keywords or reserved names.{nl}"
+            f"export module std:__libcpp_module_{header};{nl}"
+            f"{module_files}"
+            f'" > {self.tmp_prefix}.{header}.cppm'
+        )
+
+        # Extract the information of the module partition using lang-tidy
+        print(
+            f"// RUN: {self.clang_tidy} {self.tmp_prefix}.{header}.cppm "
+            "  --checks='-*,libcpp-header-exportable-declarations' "
+            "  -config='{CheckOptions: [ "
+            "    {"
+            "      key: libcpp-header-exportable-declarations.Filename, "
+            f"     value: {header}.inc"
+            "    }, {"
+            "      key: libcpp-header-exportable-declarations.FileType, "
+            f"     value: {'CompatModulePartition' if is_c_header else 'ModulePartition'}"
+            "    }, "
+            "  ]}' "
+            f"--load={self.clang_tidy_plugin} "
+            f"-- {self.compiler_flags} "
+            f"| sort > {self.tmp_prefix}.{header}.module"
+        )
+        print(
+            f"// RUN: cat  {self.tmp_prefix}.{header}.module >> {self.tmp_prefix}.all_partitions"
+        )
+
+        return include
+
+    def process_header(self, header, include, is_c_header):
+        # Dump the information as found in the module by using the header file(s).
+        skip_declarations = " ".join(SkipDeclarations.get(header, []))
+        if skip_declarations:
+            skip_declarations = (
+                "{"
+                "  key: libcpp-header-exportable-declarations.SkipDeclarations, "
+                f' value: "{skip_declarations}" '
+                "}, "
+            )
+
+        extra_declarations = " ".join(ExtraDeclarations.get(header, []))
+        if extra_declarations:
+            extra_declarations = (
+                "{"
+                "  key: libcpp-header-exportable-declarations.ExtraDeclarations, "
+                f' value: "{extra_declarations}" '
+                "}, "
+            )
+
+        extra_header = ExtraHeader.get(header, "")
+        if extra_header:
+            extra_header = (
+                "{"
+                "  key: libcpp-header-exportable-declarations.ExtraHeader, "
+                f' value: "{extra_header}" '
+                "}, "
+            )
+
+        # Clang-tidy needs a file input
+        print(f'// RUN: echo -e "' f"{include}" f'" > {self.tmp_prefix}.{header}.cpp')
+        print(
+            f"// RUN: {self.clang_tidy} {self.tmp_prefix}.{header}.cpp "
+            "  --checks='-*,libcpp-header-exportable-declarations' "
+            "  -config='{CheckOptions: [ "
+            "    {"
+            "      key: libcpp-header-exportable-declarations.Filename, "
+            f"     value: {header}"
+            "    }, {"
+            "      key: libcpp-header-exportable-declarations.FileType, "
+            f"     value: {'CHeader' if is_c_header else 'Header'}"
+            "    }, "
+            f"   {skip_declarations} {extra_declarations} {extra_header}, "
+            "  ]}' "
+            f"--load={self.clang_tidy_plugin} "
+            f"-- {self.compiler_flags} "
+            f"| sort > {self.tmp_prefix}.{header}.include"
+        )
+        print(
+            f"// RUN: diff -u {self.tmp_prefix}.{header}.module {self.tmp_prefix}.{header}.include"
+        )
+
+    def process_module(self, module):
+        # Merge the data of the parts
+        print(
+            f"// RUN: sort -u -o {self.tmp_prefix}.all_partitions {self.tmp_prefix}.all_partitions"
+        )
+
+        # Dump the information as found in top-level module.
+        print(
+            f"// RUN: {self.clang_tidy} {self.module_path}/{module}.cppm "
+            "  --checks='-*,libcpp-header-exportable-declarations' "
+            "  -config='{CheckOptions: [ "
+            "    {"
+            "      key: libcpp-header-exportable-declarations.Header, "
+            f"     value: {module}.cppm"
+            "    }, {"
+            "      key: libcpp-header-exportable-declarations.FileType, "
+            "      value: Module"
+            "    }, "
+            "  ]}' "
+            f"--load={self.clang_tidy_plugin} "
+            f"-- {self.compiler_flags} "
+            f"| sort > {self.tmp_prefix}.module"
+        )
+
+        # Compare the sum of the parts with the top-level module.
+        print(
+            f"// RUN: diff -u {self.tmp_prefix}.all_partitions {self.tmp_prefix}.module"
+        )
+
+    # Basic smoke test. Import a module and try to compile when using all
+    # exported names. This validates the clang-tidy script does not
+    # accidentally add named declarations to the list that are not available.
+    def test_module(self, module):
+        print(
+            f"""\
+// RUN: echo 'import {module};' > {self.tmp_prefix}.compile.pass.cpp
+// RUN: cat {self.tmp_prefix}.all_partitions >> {self.tmp_prefix}.compile.pass.cpp
+// RUN: {self.compiler} {self.compiler_flags} -fsyntax-only {self.tmp_prefix}.compile.pass.cpp
+"""
+        )
+
+    def write_test(self, module, c_headers=[]):
+        self.write_lit_configuration()
+
+        # Validate all module parts.
+        for header in module_headers:
+            is_c_header = header in c_headers
+            include = self.process_module_partition(header, is_c_header)
+            self.process_header(header, include, is_c_header)
+
+        self.process_module(module)
+        self.test_module(module)
-- 
GitLab


From 4cfdef76a2228b1b52df82fc83f58b9453397d98 Mon Sep 17 00:00:00 2001
From: Richard Dzenis <dzenis@richard.lv>
Date: Sat, 9 Dec 2023 16:40:04 +0200
Subject: [PATCH 025/349] [clang] Fix '__cdecl' CC is not supported for this
 target (#74932)

Fixes regression introduced in b3e6ff331925dde24a4707452d657da0fdf7f588
Fixes bot failure https://lab.llvm.org/buildbot/#/builders/60/builds/15037
```
    .---command stderr------------
    | error: 'supported-warning' diagnostics seen but not expected:
    | File C:\buildbot\as-builder-1\x-armv7l\llvm-project\clang\test\SemaCXX\ms-constexpr-new.cpp Line 7: '__cdecl' calling convention is not supported for this target
    | 1 error generated.
    `-----------------------------
```
---
 clang/test/SemaCXX/ms-constexpr-new.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clang/test/SemaCXX/ms-constexpr-new.cpp b/clang/test/SemaCXX/ms-constexpr-new.cpp
index 05ee5c5b4e15..30567740b2ec 100644
--- a/clang/test/SemaCXX/ms-constexpr-new.cpp
+++ b/clang/test/SemaCXX/ms-constexpr-new.cpp
@@ -4,7 +4,7 @@
 
 [[nodiscard]]
 [[msvc::constexpr]] // unsupported-warning {{unknown attribute 'constexpr' ignored}}
-inline void* __cdecl operator new(decltype(sizeof(void*)), void* p) noexcept { return p; }
+inline void* operator new(decltype(sizeof(void*)), void* p) noexcept { return p; }
 
 namespace std {
   constexpr int* construct_at(int* p, int v) {
-- 
GitLab


From b5a6e8a433e9ecc0e3a05fc428d515f3a12413cf Mon Sep 17 00:00:00 2001
From: Mark de Wever <koraq@xs4all.nl>
Date: Sat, 9 Dec 2023 15:50:18 +0100
Subject: [PATCH 026/349] [NFC][libc++] Rewrites a return statement.

This fixes a clang-tidy diagnostic when building libc++ with RTTI
disabled. This was originally part of #65518.
---
 libcxx/include/any | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/libcxx/include/any b/libcxx/include/any
index 516fd6ddb23c..7dcffc46a60d 100644
--- a/libcxx/include/any
+++ b/libcxx/include/any
@@ -194,9 +194,7 @@ namespace __any_imp
       if (__id && *__id == typeid(_Tp))
           return true;
 #endif
-      if (!__id && __fallback_id == __any_imp::__get_fallback_typeid<_Tp>())
-          return true;
-      return false;
+      return !__id && __fallback_id == __any_imp::__get_fallback_typeid<_Tp>();
   }
 
   template <class _Tp>
-- 
GitLab


From 54e2749609d7114f4a48f4146cddeecf76d935a4 Mon Sep 17 00:00:00 2001
From: Nathan Sidwell <nathan@acm.org>
Date: Sat, 9 Dec 2023 10:13:27 -0500
Subject: [PATCH 027/349] [clang] Adjust TargetInfo bitfield (#74893)

An 8 bit bitfield should not have a preferred type of bool.
---
 clang/include/clang/Basic/TargetInfo.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/clang/include/clang/Basic/TargetInfo.h b/clang/include/clang/Basic/TargetInfo.h
index 41f3c2e403cb..ec0189627dfb 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -266,7 +266,6 @@ protected:
   LLVM_PREFERRED_TYPE(bool)
   unsigned AllowAMDGPUUnsafeFPAtomics : 1;
 
-  LLVM_PREFERRED_TYPE(bool)
   unsigned ARMCDECoprocMask : 8;
 
   unsigned MaxOpenCLWorkGroupSize;
-- 
GitLab


From 08cb64034f17d50a660ec78ce8ea81a025b0ba71 Mon Sep 17 00:00:00 2001
From: Kiran Chandramohan <kiran.chandramohan@arm.com>
Date: Sat, 9 Dec 2023 16:27:33 +0000
Subject: [PATCH 028/349] [NFC] Remove an unused decl to avoid warning

---
 clang/lib/Driver/ToolChains/WebAssembly.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clang/lib/Driver/ToolChains/WebAssembly.cpp b/clang/lib/Driver/ToolChains/WebAssembly.cpp
index f04018179a5d..f131b6cf3baf 100644
--- a/clang/lib/Driver/ToolChains/WebAssembly.cpp
+++ b/clang/lib/Driver/ToolChains/WebAssembly.cpp
@@ -143,7 +143,7 @@ void wasm::Linker::ConstructJob(Compilation &C, const JobAction &JA,
 
   // When optimizing, if wasm-opt is available, run it.
   std::string WasmOptPath;
-  if (Arg *A = Args.getLastArg(options::OPT_O_Group)) {
+  if (Args.getLastArg(options::OPT_O_Group)) {
     WasmOptPath = ToolChain.GetProgramPath("wasm-opt");
     if (WasmOptPath == "wasm-opt") {
       WasmOptPath = {};
-- 
GitLab


From 7a13e410fd40d4ee2c89355f3d2f9a309cdff2c7 Mon Sep 17 00:00:00 2001
From: Justin Bogner <mail@justinbogner.com>
Date: Sat, 9 Dec 2023 10:42:45 -0800
Subject: [PATCH 029/349] [DirectX] Move ROV info into HLSL metadata. NFC

Pull Request: https://github.com/llvm/llvm-project/pull/74896
---
 clang/include/clang/Basic/Attr.td             |  3 ++-
 clang/lib/CodeGen/CGHLSLRuntime.cpp           |  9 ++++++---
 clang/lib/CodeGen/CGHLSLRuntime.h             |  2 +-
 clang/lib/Sema/HLSLExternalSemaSource.cpp     |  4 ++--
 .../builtins/RWBuffer-annotations.hlsl        | 12 +++++------
 clang/test/CodeGenHLSL/cbuf.hlsl              |  4 ++--
 .../include/llvm/Frontend/HLSL/HLSLResource.h |  5 +++--
 llvm/lib/Frontend/HLSL/HLSLResource.cpp       | 14 +++++++++----
 llvm/lib/Target/DirectX/DXILResource.cpp      |  4 +---
 llvm/test/CodeGen/DirectX/UAVMetadata.ll      | 20 +++++++++----------
 llvm/test/CodeGen/DirectX/cbuf.ll             |  2 +-
 .../CodeGen/DirectX/legacy_cb_layout_0.ll     |  2 +-
 .../CodeGen/DirectX/legacy_cb_layout_1.ll     |  2 +-
 .../CodeGen/DirectX/legacy_cb_layout_2.ll     |  4 ++--
 .../CodeGen/DirectX/legacy_cb_layout_3.ll     |  2 +-
 15 files changed, 49 insertions(+), 40 deletions(-)

diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td
index b0a8ef10c500..0d94ea2851c9 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -4258,7 +4258,8 @@ def HLSLResource : InheritableAttr {
                             "StructuredBuffer", "CBuffer", "Sampler",
                             "TBuffer", "RTAccelerationStructure",
                             "FeedbackTexture2D", "FeedbackTexture2DArray"],
-                           /*opt=*/0, /*fake=*/0, /*isExternalType=*/1>
+                           /*opt=*/0, /*fake=*/0, /*isExternalType=*/1>,
+              DefaultBoolArgument<"isROV", /*default=*/0>
               ];
   let Documentation = [InternalOnly];
 }
diff --git a/clang/lib/CodeGen/CGHLSLRuntime.cpp b/clang/lib/CodeGen/CGHLSLRuntime.cpp
index c239bc17ef26..3e8a40e7540b 100644
--- a/clang/lib/CodeGen/CGHLSLRuntime.cpp
+++ b/clang/lib/CodeGen/CGHLSLRuntime.cpp
@@ -184,7 +184,8 @@ void CGHLSLRuntime::finishCodeGen() {
                                       : llvm::hlsl::ResourceKind::TBuffer;
     std::string TyName =
         Buf.Name.str() + (Buf.IsCBuffer ? ".cb." : ".tb.") + "ty";
-    addBufferResourceAnnotation(GV, TyName, RC, RK, Buf.Binding);
+    addBufferResourceAnnotation(GV, TyName, RC, RK, /*IsROV=*/false,
+                                Buf.Binding);
   }
 }
 
@@ -196,6 +197,7 @@ void CGHLSLRuntime::addBufferResourceAnnotation(llvm::GlobalVariable *GV,
                                                 llvm::StringRef TyName,
                                                 llvm::hlsl::ResourceClass RC,
                                                 llvm::hlsl::ResourceKind RK,
+                                                bool IsROV,
                                                 BufferResBinding &Binding) {
   llvm::Module &M = CGM.getModule();
 
@@ -219,7 +221,7 @@ void CGHLSLRuntime::addBufferResourceAnnotation(llvm::GlobalVariable *GV,
          "ResourceMD must have been set by the switch above.");
 
   llvm::hlsl::FrontendResource Res(
-      GV, TyName, RK, Binding.Reg.value_or(UINT_MAX), Binding.Space);
+      GV, TyName, RK, IsROV, Binding.Reg.value_or(UINT_MAX), Binding.Space);
   ResourceMD->addOperand(Res.getMetadata());
 }
 
@@ -236,10 +238,11 @@ void CGHLSLRuntime::annotateHLSLResource(const VarDecl *D, GlobalVariable *GV) {
 
   llvm::hlsl::ResourceClass RC = Attr->getResourceClass();
   llvm::hlsl::ResourceKind RK = Attr->getResourceKind();
+  bool IsROV = Attr->getIsROV();
 
   QualType QT(Ty, 0);
   BufferResBinding Binding(D->getAttr<HLSLResourceBindingAttr>());
-  addBufferResourceAnnotation(GV, QT.getAsString(), RC, RK, Binding);
+  addBufferResourceAnnotation(GV, QT.getAsString(), RC, RK, IsROV, Binding);
 }
 
 CGHLSLRuntime::BufferResBinding::BufferResBinding(
diff --git a/clang/lib/CodeGen/CGHLSLRuntime.h b/clang/lib/CodeGen/CGHLSLRuntime.h
index 67413fbd4a78..bb500cb5c979 100644
--- a/clang/lib/CodeGen/CGHLSLRuntime.h
+++ b/clang/lib/CodeGen/CGHLSLRuntime.h
@@ -92,7 +92,7 @@ private:
   void addBufferResourceAnnotation(llvm::GlobalVariable *GV,
                                    llvm::StringRef TyName,
                                    llvm::hlsl::ResourceClass RC,
-                                   llvm::hlsl::ResourceKind RK,
+                                   llvm::hlsl::ResourceKind RK, bool IsROV,
                                    BufferResBinding &Binding);
   void addConstant(VarDecl *D, Buffer &CB);
   void addBufferDecls(const DeclContext *DC, Buffer &CB);
diff --git a/clang/lib/Sema/HLSLExternalSemaSource.cpp b/clang/lib/Sema/HLSLExternalSemaSource.cpp
index 8ed6480a9f5c..d0e4ab8ba857 100644
--- a/clang/lib/Sema/HLSLExternalSemaSource.cpp
+++ b/clang/lib/Sema/HLSLExternalSemaSource.cpp
@@ -119,8 +119,8 @@ struct BuiltinTypeDeclBuilder {
                                                 ResourceKind RK) {
     if (Record->isCompleteDefinition())
       return *this;
-    Record->addAttr(
-        HLSLResourceAttr::CreateImplicit(Record->getASTContext(), RC, RK));
+    Record->addAttr(HLSLResourceAttr::CreateImplicit(Record->getASTContext(),
+                                                     RC, RK, /*IsROV=*/false));
     return *this;
   }
 
diff --git a/clang/test/CodeGenHLSL/builtins/RWBuffer-annotations.hlsl b/clang/test/CodeGenHLSL/builtins/RWBuffer-annotations.hlsl
index 77091f8390a1..a70e224b81e4 100644
--- a/clang/test/CodeGenHLSL/builtins/RWBuffer-annotations.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/RWBuffer-annotations.hlsl
@@ -16,9 +16,9 @@ void main() {
 }
 
 // CHECK: !hlsl.uavs = !{![[Single:[0-9]+]], ![[Array:[0-9]+]], ![[SingleAllocated:[0-9]+]], ![[ArrayAllocated:[0-9]+]], ![[SingleSpace:[0-9]+]], ![[ArraySpace:[0-9]+]]}
-// CHECK-DAG: ![[Single]] = !{ptr @"?Buffer1@@3V?$RWBuffer@M@hlsl@@A", !"RWBuffer<float>", i32 10, i32 -1, i32 0}
-// CHECK-DAG: ![[Array]] = !{ptr @"?BufferArray@@3PAV?$RWBuffer@T?$__vector@M$03@__clang@@@hlsl@@A", !"RWBuffer<vector<float, 4> >", i32 10, i32 -1, i32 0}
-// CHECK-DAG: ![[SingleAllocated]] = !{ptr @"?Buffer2@@3V?$RWBuffer@M@hlsl@@A", !"RWBuffer<float>", i32 10, i32 3, i32 0}
-// CHECK-DAG: ![[ArrayAllocated]] = !{ptr @"?BufferArray2@@3PAV?$RWBuffer@T?$__vector@M$03@__clang@@@hlsl@@A", !"RWBuffer<vector<float, 4> >", i32 10, i32 4, i32 0}
-// CHECK-DAG: ![[SingleSpace]] = !{ptr @"?Buffer3@@3V?$RWBuffer@M@hlsl@@A", !"RWBuffer<float>", i32 10, i32 3, i32 1}
-// CHECK-DAG: ![[ArraySpace]] = !{ptr @"?BufferArray3@@3PAV?$RWBuffer@T?$__vector@M$03@__clang@@@hlsl@@A", !"RWBuffer<vector<float, 4> >", i32 10, i32 4, i32 1}
+// CHECK-DAG: ![[Single]] = !{ptr @"?Buffer1@@3V?$RWBuffer@M@hlsl@@A", !"RWBuffer<float>", i32 10, i1 false, i32 -1, i32 0}
+// CHECK-DAG: ![[Array]] = !{ptr @"?BufferArray@@3PAV?$RWBuffer@T?$__vector@M$03@__clang@@@hlsl@@A", !"RWBuffer<vector<float, 4> >", i32 10, i1 false, i32 -1, i32 0}
+// CHECK-DAG: ![[SingleAllocated]] = !{ptr @"?Buffer2@@3V?$RWBuffer@M@hlsl@@A", !"RWBuffer<float>", i32 10, i1 false, i32 3, i32 0}
+// CHECK-DAG: ![[ArrayAllocated]] = !{ptr @"?BufferArray2@@3PAV?$RWBuffer@T?$__vector@M$03@__clang@@@hlsl@@A", !"RWBuffer<vector<float, 4> >", i32 10, i1 false, i32 4, i32 0}
+// CHECK-DAG: ![[SingleSpace]] = !{ptr @"?Buffer3@@3V?$RWBuffer@M@hlsl@@A", !"RWBuffer<float>", i32 10, i1 false, i32 3, i32 1}
+// CHECK-DAG: ![[ArraySpace]] = !{ptr @"?BufferArray3@@3PAV?$RWBuffer@T?$__vector@M$03@__clang@@@hlsl@@A", !"RWBuffer<vector<float, 4> >", i32 10, i1 false, i32 4, i32 1}
diff --git a/clang/test/CodeGenHLSL/cbuf.hlsl b/clang/test/CodeGenHLSL/cbuf.hlsl
index 92c883943d03..5dee1feb902a 100644
--- a/clang/test/CodeGenHLSL/cbuf.hlsl
+++ b/clang/test/CodeGenHLSL/cbuf.hlsl
@@ -24,5 +24,5 @@ float foo() {
 
 // CHECK: !hlsl.cbufs = !{![[CBMD:[0-9]+]]}
 // CHECK: !hlsl.srvs = !{![[TBMD:[0-9]+]]}
-// CHECK: ![[CBMD]] = !{ptr @[[CB]], !"A.cb.ty", i32 13, i32 0, i32 2}
-// CHECK: ![[TBMD]] = !{ptr @[[TB]], !"A.tb.ty", i32 15, i32 2, i32 1}
+// CHECK: ![[CBMD]] = !{ptr @[[CB]], !"A.cb.ty", i32 13, i1 false, i32 0, i32 2}
+// CHECK: ![[TBMD]] = !{ptr @[[TB]], !"A.tb.ty", i32 15, i1 false, i32 2, i32 1}
diff --git a/llvm/include/llvm/Frontend/HLSL/HLSLResource.h b/llvm/include/llvm/Frontend/HLSL/HLSLResource.h
index 997ddccd687a..eedecaea4e58 100644
--- a/llvm/include/llvm/Frontend/HLSL/HLSLResource.h
+++ b/llvm/include/llvm/Frontend/HLSL/HLSLResource.h
@@ -59,15 +59,16 @@ class FrontendResource {
 
 public:
   FrontendResource(MDNode *E) : Entry(E) {
-    assert(Entry->getNumOperands() == 5 && "Unexpected metadata shape");
+    assert(Entry->getNumOperands() == 6 && "Unexpected metadata shape");
   }
 
   FrontendResource(GlobalVariable *GV, StringRef TypeStr, ResourceKind RK,
-                   uint32_t ResIndex, uint32_t Space);
+                   bool IsROV, uint32_t ResIndex, uint32_t Space);
 
   GlobalVariable *getGlobalVariable();
   StringRef getSourceType();
   ResourceKind getResourceKind();
+  bool getIsROV();
   uint32_t getResourceIndex();
   uint32_t getSpace();
   MDNode *getMetadata() { return Entry; }
diff --git a/llvm/lib/Frontend/HLSL/HLSLResource.cpp b/llvm/lib/Frontend/HLSL/HLSLResource.cpp
index a3a7d0b8696c..709fe3212623 100644
--- a/llvm/lib/Frontend/HLSL/HLSLResource.cpp
+++ b/llvm/lib/Frontend/HLSL/HLSLResource.cpp
@@ -33,25 +33,31 @@ ResourceKind FrontendResource::getResourceKind() {
           cast<ConstantAsMetadata>(Entry->getOperand(2))->getValue())
           ->getLimitedValue());
 }
-uint32_t FrontendResource::getResourceIndex() {
+bool FrontendResource::getIsROV() {
   return cast<ConstantInt>(
              cast<ConstantAsMetadata>(Entry->getOperand(3))->getValue())
       ->getLimitedValue();
 }
-uint32_t FrontendResource::getSpace() {
+uint32_t FrontendResource::getResourceIndex() {
   return cast<ConstantInt>(
              cast<ConstantAsMetadata>(Entry->getOperand(4))->getValue())
       ->getLimitedValue();
 }
+uint32_t FrontendResource::getSpace() {
+  return cast<ConstantInt>(
+             cast<ConstantAsMetadata>(Entry->getOperand(5))->getValue())
+      ->getLimitedValue();
+}
 
 FrontendResource::FrontendResource(GlobalVariable *GV, StringRef TypeStr,
-                                   ResourceKind RK, uint32_t ResIndex,
-                                   uint32_t Space) {
+                                   ResourceKind RK, bool IsROV,
+                                   uint32_t ResIndex, uint32_t Space) {
   auto &Ctx = GV->getContext();
   IRBuilder<> B(Ctx);
   Entry = MDNode::get(
       Ctx, {ValueAsMetadata::get(GV), MDString::get(Ctx, TypeStr),
             ConstantAsMetadata::get(B.getInt32(static_cast<int>(RK))),
+            ConstantAsMetadata::get(B.getInt1(IsROV)),
             ConstantAsMetadata::get(B.getInt32(ResIndex)),
             ConstantAsMetadata::get(B.getInt32(Space))});
 }
diff --git a/llvm/lib/Target/DirectX/DXILResource.cpp b/llvm/lib/Target/DirectX/DXILResource.cpp
index 041b8fafcd6a..92306d907e05 100644
--- a/llvm/lib/Target/DirectX/DXILResource.cpp
+++ b/llvm/lib/Target/DirectX/DXILResource.cpp
@@ -234,7 +234,7 @@ void ResourceBase::print(raw_ostream &OS, StringRef IDPrefix,
 
 UAVResource::UAVResource(uint32_t I, FrontendResource R)
     : ResourceBase(I, R), Shape(R.getResourceKind()), GloballyCoherent(false),
-      HasCounter(false), IsROV(false), ExtProps() {
+      HasCounter(false), IsROV(R.getIsROV()), ExtProps() {
   parseSourceType(R.getSourceType());
 }
 
@@ -258,8 +258,6 @@ void UAVResource::print(raw_ostream &OS) const {
 // information we need to remove the source type string from here (See issue:
 // https://github.com/llvm/llvm-project/issues/57991).
 void UAVResource::parseSourceType(StringRef S) {
-  IsROV = S.startswith("RasterizerOrdered");
-
   S = S.substr(S.find("<") + 1);
 
   constexpr size_t PrefixLen = StringRef("vector<").size();
diff --git a/llvm/test/CodeGen/DirectX/UAVMetadata.ll b/llvm/test/CodeGen/DirectX/UAVMetadata.ll
index e86d53cd7afc..3d95723d6e49 100644
--- a/llvm/test/CodeGen/DirectX/UAVMetadata.ll
+++ b/llvm/test/CodeGen/DirectX/UAVMetadata.ll
@@ -37,16 +37,16 @@ target triple = "dxil-pc-shadermodel6.0-library"
 
 !hlsl.uavs = !{!0, !1, !2, !3, !4, !5, !6, !7, !8, !9}
 
-!0 = !{ptr @Zero, !"RWBuffer<half>", i32 10, i32 0, i32 0}
-!1 = !{ptr @One, !"Buffer<vector<float,4>>", i32 10, i32 1, i32 0}
-!2 = !{ptr @Two, !"Buffer<double>", i32 10, i32 2, i32 0}
-!3 = !{ptr @Three, !"Buffer<bool>", i32 10, i32 3, i32 0}
-!4 = !{ptr @Four, !"ByteAddressBuffer<int16_t>", i32 11, i32 5, i32 0}
-!5 = !{ptr @Five, !"StructuredBuffer<uint16_t>", i32 12, i32 6, i32 0}
-!6 = !{ptr @Six, !"RasterizerOrderedBuffer<int32_t>", i32 10, i32 7, i32 0}
-!7 = !{ptr @Seven, !"RasterizerOrderedStructuredBuffer<uint32_t>", i32 12, i32 8, i32 0}
-!8 = !{ptr @Eight, !"RasterizerOrderedByteAddressBuffer<int64_t>", i32 11, i32 9, i32 0}
-!9 = !{ptr @Nine, !"RWBuffer<uint64_t>", i32 10, i32 10, i32 2}
+!0 = !{ptr @Zero, !"RWBuffer<half>", i32 10, i1 false, i32 0, i32 0}
+!1 = !{ptr @One, !"Buffer<vector<float,4>>", i32 10, i1 false, i32 1, i32 0}
+!2 = !{ptr @Two, !"Buffer<double>", i32 10, i1 false, i32 2, i32 0}
+!3 = !{ptr @Three, !"Buffer<bool>", i32 10, i1 false, i32 3, i32 0}
+!4 = !{ptr @Four, !"ByteAddressBuffer<int16_t>", i32 11, i1 false, i32 5, i32 0}
+!5 = !{ptr @Five, !"StructuredBuffer<uint16_t>", i32 12, i1 false, i32 6, i32 0}
+!6 = !{ptr @Six, !"RasterizerOrderedBuffer<int32_t>", i32 10, i1 true, i32 7, i32 0}
+!7 = !{ptr @Seven, !"RasterizerOrderedStructuredBuffer<uint32_t>", i32 12, i1 true, i32 8, i32 0}
+!8 = !{ptr @Eight, !"RasterizerOrderedByteAddressBuffer<int64_t>", i32 11, i1 true, i32 9, i32 0}
+!9 = !{ptr @Nine, !"RWBuffer<uint64_t>", i32 10, i1 false, i32 10, i32 2}
 
 ; CHECK: !dx.resources = !{[[ResList:[!][0-9]+]]}
 
diff --git a/llvm/test/CodeGen/DirectX/cbuf.ll b/llvm/test/CodeGen/DirectX/cbuf.ll
index 6640654f730e..d07cc1e880b1 100644
--- a/llvm/test/CodeGen/DirectX/cbuf.ll
+++ b/llvm/test/CodeGen/DirectX/cbuf.ll
@@ -34,4 +34,4 @@ attributes #1 = { nocallback nofree nosync nounwind readnone speculatable willre
 
 !hlsl.cbufs = !{!1}
 
-!1 = !{ptr @A.cb., !"A.cb.ty", i32 13, i32 2, i32 1}
+!1 = !{ptr @A.cb., !"A.cb.ty", i32 13, i1 false, i32 2, i32 1}
diff --git a/llvm/test/CodeGen/DirectX/legacy_cb_layout_0.ll b/llvm/test/CodeGen/DirectX/legacy_cb_layout_0.ll
index 50821467d5dd..0cfb839746b9 100644
--- a/llvm/test/CodeGen/DirectX/legacy_cb_layout_0.ll
+++ b/llvm/test/CodeGen/DirectX/legacy_cb_layout_0.ll
@@ -11,4 +11,4 @@ target triple = "dxil-unknown-shadermodel6.7-library"
 
 !hlsl.cbufs = !{!1}
 
-!1 = !{ptr @A.cb., !"A.cb.ty", i32 13, i32 2, i32 0}
+!1 = !{ptr @A.cb., !"A.cb.ty", i32 13, i1 false, i32 2, i32 0}
diff --git a/llvm/test/CodeGen/DirectX/legacy_cb_layout_1.ll b/llvm/test/CodeGen/DirectX/legacy_cb_layout_1.ll
index 8a38ccd8ef78..b6d29f8d18d7 100644
--- a/llvm/test/CodeGen/DirectX/legacy_cb_layout_1.ll
+++ b/llvm/test/CodeGen/DirectX/legacy_cb_layout_1.ll
@@ -34,4 +34,4 @@ target triple = "dxil-unknown-shadermodel6.7-library"
 
 !hlsl.cbufs = !{!0}
 
-!0 = !{ptr @B.cb., !"B.cb.ty", i32 13, i32 1, i32 0}
+!0 = !{ptr @B.cb., !"B.cb.ty", i32 13, i1 false, i32 1, i32 0}
diff --git a/llvm/test/CodeGen/DirectX/legacy_cb_layout_2.ll b/llvm/test/CodeGen/DirectX/legacy_cb_layout_2.ll
index b669538846ab..d023d7906fdc 100644
--- a/llvm/test/CodeGen/DirectX/legacy_cb_layout_2.ll
+++ b/llvm/test/CodeGen/DirectX/legacy_cb_layout_2.ll
@@ -47,5 +47,5 @@ target triple = "dxil-unknown-shadermodel6.7-library"
 
 !hlsl.cbufs = !{!0, !1}
 
-!0 = !{ptr @B.cb., !"B.cb.ty", i32 13, i32 1, i32 0}
-!1 = !{ptr @B.cb..1, !"B.cb.ty", i32 13, i32 2, i32 0}
+!0 = !{ptr @B.cb., !"B.cb.ty", i32 13, i1 false, i32 1, i32 0}
+!1 = !{ptr @B.cb..1, !"B.cb.ty", i32 13, i1 false, i32 2, i32 0}
diff --git a/llvm/test/CodeGen/DirectX/legacy_cb_layout_3.ll b/llvm/test/CodeGen/DirectX/legacy_cb_layout_3.ll
index afd46d08b5c7..38c2cd18b5ca 100644
--- a/llvm/test/CodeGen/DirectX/legacy_cb_layout_3.ll
+++ b/llvm/test/CodeGen/DirectX/legacy_cb_layout_3.ll
@@ -78,4 +78,4 @@ target triple = "dxil-unknown-shadermodel6.7-library"
 @D.cb. = external local_unnamed_addr constant { i32, %struct.B, half, %struct.C, double }
 
 !hlsl.cbufs = !{!0}
-!0 = !{ptr @D.cb., !"D.cb.ty", i32 13, i32 1, i32 0}
+!0 = !{ptr @D.cb., !"D.cb.ty", i32 13, i1 false, i32 1, i32 0}
-- 
GitLab


From 84b907d217776efcfca5c7d2cce7b279f09265a6 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@sifive.com>
Date: Sat, 9 Dec 2023 11:32:19 -0800
Subject: [PATCH 030/349] [RISCV] Remove Name and OverloadedName from
 RVVIntrinsicDef. NFC (#74907)

These names are never used so just waste a lot of memory. If do need
them ever, it would be better to store pointers to the StringMapEntry
objects that store the same strings.
---
 clang/lib/Sema/SemaRISCVVectorLookup.cpp | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/clang/lib/Sema/SemaRISCVVectorLookup.cpp b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
index 9a5aecf669a0..0d411fca0f9c 100644
--- a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -34,12 +34,6 @@ namespace {
 
 // Function definition of a RVV intrinsic.
 struct RVVIntrinsicDef {
-  /// Full function name with suffix, e.g. vadd_vv_i32m1.
-  std::string Name;
-
-  /// Overloaded function name, e.g. vadd.
-  std::string OverloadName;
-
   /// Mapping to which clang built-in function, e.g. __builtin_rvv_vadd.
   std::string BuiltinName;
 
@@ -393,7 +387,7 @@ void RISCVIntrinsicManagerImpl::InitRVVIntrinsic(
 
   // Put into IntrinsicList.
   size_t Index = IntrinsicList.size();
-  IntrinsicList.push_back({Name, OverloadedName, BuiltinName, Signature});
+  IntrinsicList.push_back({BuiltinName, Signature});
 
   // Creating mapping to Intrinsics.
   Intrinsics.insert({Name, Index});
-- 
GitLab


From 9596676e6586767e7ae412ed26fbd8e3a16a4c18 Mon Sep 17 00:00:00 2001
From: Nathan Sidwell <nathan@acm.org>
Date: Sat, 9 Dec 2023 14:39:57 -0500
Subject: [PATCH 031/349] [BOLT] Determine address size from binary (#74870)

Query the executable for address size.
---
 bolt/lib/Core/Exceptions.cpp         | 3 ++-
 bolt/lib/Rewrite/RewriteInstance.cpp | 4 +++-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/bolt/lib/Core/Exceptions.cpp b/bolt/lib/Core/Exceptions.cpp
index 993f3a7770aa..ab1885f6bb58 100644
--- a/bolt/lib/Core/Exceptions.cpp
+++ b/bolt/lib/Core/Exceptions.cpp
@@ -108,7 +108,8 @@ void BinaryFunction::parseLSDA(ArrayRef<uint8_t> LSDASectionData,
   DWARFDataExtractor Data(
       StringRef(reinterpret_cast<const char *>(LSDASectionData.data()),
                 LSDASectionData.size()),
-      BC.DwCtx->getDWARFObj().isLittleEndian(), 8);
+      BC.DwCtx->getDWARFObj().isLittleEndian(),
+      BC.DwCtx->getDWARFObj().getAddressSize());
   uint64_t Offset = getLSDAAddress() - LSDASectionAddress;
   assert(Data.isValidOffset(Offset) && "wrong LSDA address");
 
diff --git a/bolt/lib/Rewrite/RewriteInstance.cpp b/bolt/lib/Rewrite/RewriteInstance.cpp
index 8cda0b7fcca9..1e8ca569682f 100644
--- a/bolt/lib/Rewrite/RewriteInstance.cpp
+++ b/bolt/lib/Rewrite/RewriteInstance.cpp
@@ -623,7 +623,9 @@ void RewriteInstance::parseBuildID() {
 
   // Reading notes section (see Portable Formats Specification, Version 1.1,
   // pg 2-5, section "Note Section").
-  DataExtractor DE = DataExtractor(Buf, true, 8);
+  DataExtractor DE =
+      DataExtractor(Buf,
+                    /*IsLittleEndian=*/true, InputFile->getBytesInAddress());
   uint64_t Offset = 0;
   if (!DE.isValidOffset(Offset))
     return;
-- 
GitLab


From 02e02b9a8f0e22ffc0d6c070b132a88e94f02861 Mon Sep 17 00:00:00 2001
From: Justin Bogner <mail@justinbogner.com>
Date: Sat, 9 Dec 2023 12:33:32 -0800
Subject: [PATCH 032/349] [HLSL] Define RasterizerOrderedBuffer resource

Define HLSL's RasterizerOrderedBuffer resource type through the
external sema source. This doesn't fully work as is, but defining it
allows us to exercise the ROV logic in the DirectX backend from HLSL
rather than having to manually edit metadata, so it's useful for
further testing and development.

Pull Request: https://github.com/llvm/llvm-project/pull/74897
---
 clang/lib/Sema/HLSLExternalSemaSource.cpp     | 23 ++++++++++++++-----
 .../RasterizerOrderedBuffer-annotations.hlsl  | 20 ++++++++++++++++
 2 files changed, 37 insertions(+), 6 deletions(-)
 create mode 100644 clang/test/CodeGenHLSL/builtins/RasterizerOrderedBuffer-annotations.hlsl

diff --git a/clang/lib/Sema/HLSLExternalSemaSource.cpp b/clang/lib/Sema/HLSLExternalSemaSource.cpp
index d0e4ab8ba857..1a1febf7a352 100644
--- a/clang/lib/Sema/HLSLExternalSemaSource.cpp
+++ b/clang/lib/Sema/HLSLExternalSemaSource.cpp
@@ -116,11 +116,11 @@ struct BuiltinTypeDeclBuilder {
   }
 
   BuiltinTypeDeclBuilder &annotateResourceClass(ResourceClass RC,
-                                                ResourceKind RK) {
+                                                ResourceKind RK, bool IsROV) {
     if (Record->isCompleteDefinition())
       return *this;
     Record->addAttr(HLSLResourceAttr::CreateImplicit(Record->getASTContext(),
-                                                     RC, RK, /*IsROV=*/false));
+                                                     RC, RK, IsROV));
     return *this;
   }
 
@@ -478,12 +478,12 @@ void HLSLExternalSemaSource::defineTrivialHLSLTypes() {
 
 /// Set up common members and attributes for buffer types
 static BuiltinTypeDeclBuilder setupBufferType(CXXRecordDecl *Decl, Sema &S,
-                                              ResourceClass RC,
-                                              ResourceKind RK) {
+                                              ResourceClass RC, ResourceKind RK,
+                                              bool IsROV) {
   return BuiltinTypeDeclBuilder(Decl)
       .addHandleMember()
       .addDefaultHandleConstructor(S, RC)
-      .annotateResourceClass(RC, RK);
+      .annotateResourceClass(RC, RK, IsROV);
 }
 
 void HLSLExternalSemaSource::defineHLSLTypesWithForwardDeclarations() {
@@ -493,7 +493,18 @@ void HLSLExternalSemaSource::defineHLSLTypesWithForwardDeclarations() {
              .Record;
   onCompletion(Decl, [this](CXXRecordDecl *Decl) {
     setupBufferType(Decl, *SemaPtr, ResourceClass::UAV,
-                    ResourceKind::TypedBuffer)
+                    ResourceKind::TypedBuffer, /*IsROV=*/false)
+        .addArraySubscriptOperators()
+        .completeDefinition();
+  });
+
+  Decl =
+      BuiltinTypeDeclBuilder(*SemaPtr, HLSLNamespace, "RasterizerOrderedBuffer")
+          .addSimpleTemplateParams({"element_type"})
+          .Record;
+  onCompletion(Decl, [this](CXXRecordDecl *Decl) {
+    setupBufferType(Decl, *SemaPtr, ResourceClass::UAV,
+                    ResourceKind::TypedBuffer, /*IsROV=*/true)
         .addArraySubscriptOperators()
         .completeDefinition();
   });
diff --git a/clang/test/CodeGenHLSL/builtins/RasterizerOrderedBuffer-annotations.hlsl b/clang/test/CodeGenHLSL/builtins/RasterizerOrderedBuffer-annotations.hlsl
new file mode 100644
index 000000000000..ce7d84ecf5b1
--- /dev/null
+++ b/clang/test/CodeGenHLSL/builtins/RasterizerOrderedBuffer-annotations.hlsl
@@ -0,0 +1,20 @@
+// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.0-pixel -x hlsl -emit-llvm -disable-llvm-passes -o - %s | FileCheck %s
+
+RasterizerOrderedBuffer<float> Buffer1;
+RasterizerOrderedBuffer<vector<float, 4> > BufferArray[4];
+
+RasterizerOrderedBuffer<float> Buffer2 : register(u3);
+RasterizerOrderedBuffer<vector<float, 4> > BufferArray2[4] : register(u4);
+
+RasterizerOrderedBuffer<float> Buffer3 : register(u3, space1);
+RasterizerOrderedBuffer<vector<float, 4> > BufferArray3[4] : register(u4, space1);
+
+void main() {}
+
+// CHECK: !hlsl.uavs = !{![[Single:[0-9]+]], ![[Array:[0-9]+]], ![[SingleAllocated:[0-9]+]], ![[ArrayAllocated:[0-9]+]], ![[SingleSpace:[0-9]+]], ![[ArraySpace:[0-9]+]]}
+// CHECK-DAG: ![[Single]] = !{ptr @"?Buffer1@@3V?$RasterizerOrderedBuffer@M@hlsl@@A", !"RasterizerOrderedBuffer<float>", i32 10, i1 true, i32 -1, i32 0}
+// CHECK-DAG: ![[Array]] = !{ptr @"?BufferArray@@3PAV?$RasterizerOrderedBuffer@T?$__vector@M$03@__clang@@@hlsl@@A", !"RasterizerOrderedBuffer<vector<float, 4> >", i32 10, i1 true, i32 -1, i32 0}
+// CHECK-DAG: ![[SingleAllocated]] = !{ptr @"?Buffer2@@3V?$RasterizerOrderedBuffer@M@hlsl@@A", !"RasterizerOrderedBuffer<float>", i32 10, i1 true, i32 3, i32 0}
+// CHECK-DAG: ![[ArrayAllocated]] = !{ptr @"?BufferArray2@@3PAV?$RasterizerOrderedBuffer@T?$__vector@M$03@__clang@@@hlsl@@A", !"RasterizerOrderedBuffer<vector<float, 4> >", i32 10, i1 true, i32 4, i32 0}
+// CHECK-DAG: ![[SingleSpace]] = !{ptr @"?Buffer3@@3V?$RasterizerOrderedBuffer@M@hlsl@@A", !"RasterizerOrderedBuffer<float>", i32 10, i1 true, i32 3, i32 1}
+// CHECK-DAG: ![[ArraySpace]] = !{ptr @"?BufferArray3@@3PAV?$RasterizerOrderedBuffer@T?$__vector@M$03@__clang@@@hlsl@@A", !"RasterizerOrderedBuffer<vector<float, 4> >", i32 10, i1 true, i32 4, i32 1}
-- 
GitLab


From f0c0116c4896fe50a77ca72942b05d06f14841c7 Mon Sep 17 00:00:00 2001
From: Daniil Kovalev <dkovalev@accesssoftek.com>
Date: Sat, 9 Dec 2023 23:51:59 +0300
Subject: [PATCH 033/349] [test][llvm-objdump][AArch64] Add tests for ELF AUTH
 constants (#74298)

This patch introduces llvm-objdump tests for new `AARCH64_AUTH_RELR`,
`AARCH64_AUTH_RELRSZ` and `AARCH64_AUTH_RELRENT` dynamic tags.

Depends on https://github.com/llvm/llvm-project/pull/74874
---
 .../ELF/dynamic-section-machine-specific.test            | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/llvm/test/tools/llvm-objdump/ELF/dynamic-section-machine-specific.test b/llvm/test/tools/llvm-objdump/ELF/dynamic-section-machine-specific.test
index 20219dd4893b..203c210eb46a 100644
--- a/llvm/test/tools/llvm-objdump/ELF/dynamic-section-machine-specific.test
+++ b/llvm/test/tools/llvm-objdump/ELF/dynamic-section-machine-specific.test
@@ -268,6 +268,9 @@ ProgramHeaders:
 # AARCH64:      Dynamic Section:
 # AARCH64-NEXT:  AARCH64_BTI_PLT      0x0000000000000001
 # AARCH64-NEXT:  AARCH64_PAC_PLT      0x0000000000000002
+# AARCH64-NEXT:  AARCH64_AUTH_RELR    0x0000000000000003
+# AARCH64-NEXT:  AARCH64_AUTH_RELRSZ  0x0000000000000004
+# AARCH64-NEXT:  AARCH64_AUTH_RELRENT 0x0000000000000005
 
 --- !ELF
 FileHeader:
@@ -283,6 +286,12 @@ Sections:
         Value: 1
       - Tag:   DT_AARCH64_PAC_PLT
         Value: 2
+      - Tag:   DT_AARCH64_AUTH_RELR
+        Value: 3
+      - Tag:   DT_AARCH64_AUTH_RELRSZ
+        Value: 4
+      - Tag:   DT_AARCH64_AUTH_RELRENT
+        Value: 5
       - Tag:   DT_NULL
         Value: 0
 ProgramHeaders:
-- 
GitLab


From b5b250b6ff58acfbd7f0c70ea186b416d3b0d7d7 Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu@google.com>
Date: Sat, 9 Dec 2023 13:24:26 -0800
Subject: [PATCH 034/349] [ADT] Remove StringRef::{starts,ends}with_insensitive
 (#74918)

These functions have been deprecated since:

  commit 1117d806ca4d9b5b04263456dcb1ced76ade78cb
  Author: Kazu Hirata <kazu@google.com>
  Date:   Mon Jun 5 13:18:07 2023 -0700
---
 llvm/include/llvm/ADT/StringRef.h | 12 ------------
 1 file changed, 12 deletions(-)

diff --git a/llvm/include/llvm/ADT/StringRef.h b/llvm/include/llvm/ADT/StringRef.h
index 235a7b27c384..4e69d5b63354 100644
--- a/llvm/include/llvm/ADT/StringRef.h
+++ b/llvm/include/llvm/ADT/StringRef.h
@@ -264,12 +264,6 @@ namespace llvm {
 
     /// Check if this string starts with the given \p Prefix, ignoring case.
     [[nodiscard]] bool starts_with_insensitive(StringRef Prefix) const;
-    [[nodiscard]] LLVM_DEPRECATED(
-        "Use starts_with_insensitive instead",
-        "starts_with_insensitive") bool startswith_insensitive(StringRef Prefix)
-        const {
-      return starts_with_insensitive(Prefix);
-    }
 
     /// Check if this string ends with the given \p Suffix.
     [[nodiscard]] bool ends_with(StringRef Suffix) const {
@@ -283,12 +277,6 @@ namespace llvm {
 
     /// Check if this string ends with the given \p Suffix, ignoring case.
     [[nodiscard]] bool ends_with_insensitive(StringRef Suffix) const;
-    [[nodiscard]] LLVM_DEPRECATED(
-        "Use ends_with_insensitive instead",
-        "ends_with_insensitive") bool endswith_insensitive(StringRef Suffix)
-        const {
-      return ends_with_insensitive(Suffix);
-    }
 
     /// @}
     /// @name String Searching
-- 
GitLab


From cd4067af3645f5b3d80cf012e3ae1ead1d6a30ad Mon Sep 17 00:00:00 2001
From: Florian Hahn <flo@fhahn.com>
Date: Sat, 9 Dec 2023 21:27:42 +0000
Subject: [PATCH 035/349] [LAA] Remove duplicated test.

depend_diff_types.ll already covers the same tests afer it hs been
converted to opaque pointersj, so remove the redundant
depend_diff_types_opaque_ptr.ll
---
 .../depend_diff_types_opaque_ptr.ll           | 179 ------------------
 1 file changed, 179 deletions(-)
 delete mode 100644 llvm/test/Analysis/LoopAccessAnalysis/depend_diff_types_opaque_ptr.ll

diff --git a/llvm/test/Analysis/LoopAccessAnalysis/depend_diff_types_opaque_ptr.ll b/llvm/test/Analysis/LoopAccessAnalysis/depend_diff_types_opaque_ptr.ll
deleted file mode 100644
index e424683bbef3..000000000000
--- a/llvm/test/Analysis/LoopAccessAnalysis/depend_diff_types_opaque_ptr.ll
+++ /dev/null
@@ -1,179 +0,0 @@
-; RUN: opt -S -disable-output -passes='print<access-info>' < %s 2>&1 | FileCheck %s
-
-; In the function below some of the accesses are done as float types and some
-; are done as i32 types. When doing dependence analysis the type should not
-; matter if it can be determined that they are the same size.
-
-%int_pair = type { i32, i32 }
-
-; CHECK-LABEL: function 'backdep_type_size_equivalence':
-; CHECK-NEXT:    loop:
-; CHECK-NEXT:      Memory dependences are safe with a maximum safe vector width of 3200 bits
-; CHECK-NEXT:      Dependences:
-; CHECK-NEXT:        Forward:
-; CHECK-NEXT:            %ld.f32 = load float, ptr %gep.iv, align 8 ->
-; CHECK-NEXT:            store i32 %indvars.iv.i32, ptr %gep.iv, align 8
-; CHECK-EMPTY:
-; CHECK-NEXT:        Forward:
-; CHECK-NEXT:            %ld.f32 = load float, ptr %gep.iv, align 8 ->
-; CHECK-NEXT:            store float %val, ptr %gep.iv.min.100, align 8
-; CHECK-EMPTY:
-; CHECK-NEXT:        BackwardVectorizable:
-; CHECK-NEXT:            store float %val, ptr %gep.iv.min.100, align 8 ->
-; CHECK-NEXT:            store i32 %indvars.iv.i32, ptr %gep.iv, align 8
-; CHECK-EMPTY:
-; CHECK-NEXT:        Run-time memory checks:
-; CHECK-NEXT:        Grouped accesses:
-
-define void @backdep_type_size_equivalence(ptr nocapture %vec, i64 %n) {
-entry:
-  br label %loop
-
-loop:
-  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %loop ]
-
-  ;; Load from vec[indvars.iv].x as float
-  %gep.iv = getelementptr inbounds %int_pair, ptr %vec, i64 %indvars.iv, i32 0
-  %ld.f32 = load float, ptr %gep.iv, align 8
-  %val = fmul fast float %ld.f32, 5.0
-
-  ;; Store to vec[indvars.iv - 100].x as float
-  %indvars.iv.min.100 = add nsw i64 %indvars.iv, -100
-  %gep.iv.min.100 = getelementptr inbounds %int_pair, ptr %vec, i64 %indvars.iv.min.100, i32 0
-  store float %val, ptr %gep.iv.min.100, align 8
-
-  ;; Store to vec[indvars.iv].x as i32, creating a backward dependency between
-  ;; the two stores with different element types but the same element size.
-  %indvars.iv.i32 = trunc i64 %indvars.iv to i32
-  store i32 %indvars.iv.i32, ptr %gep.iv, align 8
-
-  ;; Store to vec[indvars.iv].y as i32, strided accesses should be independent
-  ;; between the two stores with different element types but the same element size.
-  %gep.iv.1 = getelementptr inbounds %int_pair, ptr %vec, i64 %indvars.iv, i32 1
-  store i32 %indvars.iv.i32, ptr %gep.iv.1, align 8
-
-  ;; Store to vec[indvars.iv + n].y as i32, to verify no dependence in the case
-  ;; of unknown dependence distance.
-  %indvars.iv.n = add nuw nsw i64 %indvars.iv, %n
-  %gep.iv.n = getelementptr inbounds %int_pair, ptr %vec, i64 %indvars.iv.n, i32 1
-  store i32 %indvars.iv.i32, ptr %gep.iv.n, align 8
-
-  ;; Loop condition.
-  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
-  %cond = icmp eq i64 %indvars.iv.next, %n
-  br i1 %cond, label %exit, label %loop
-
-exit:
-  ret void
-}
-
-; In the function below one of the accesses is done as i19 type, which has a
-; different store size than the i32 type, even though their alloc sizes are
-; equivalent. This is a negative test to ensure that they are not analyzed as
-; in the tests above.
-;
-; CHECK-LABEL: function 'backdep_type_store_size_equivalence':
-; CHECK-NEXT:    loop:
-; CHECK-NEXT:      Report: unsafe dependent memory operations in loop.
-; CHECK-NEXT:      Unknown data dependence.
-; CHECK-NEXT:      Dependences:
-; CHECK-NEXT:        Unknown:
-; CHECK-NEXT:            %ld.f32 = load float, ptr %gep.iv, align 8 ->
-; CHECK-NEXT:            store i19 %indvars.iv.i19, ptr %gep.iv, align 8
-; CHECK-EMPTY:
-; CHECK-NEXT:        Run-time memory checks:
-; CHECK-NEXT:        Grouped accesses:
-
-define void @backdep_type_store_size_equivalence(ptr nocapture %vec, i64 %n) {
-entry:
-  br label %loop
-
-loop:
-  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %loop ]
-
-  ;; Load from vec[indvars.iv].x as float
-  %gep.iv = getelementptr inbounds %int_pair, ptr %vec, i64 %indvars.iv, i32 0
-  %ld.f32 = load float, ptr %gep.iv, align 8
-  %val = fmul fast float %ld.f32, 5.0
-
-  ;; Store to vec[indvars.iv].x as i19.
-  %indvars.iv.i19 = trunc i64 %indvars.iv to i19
-  store i19 %indvars.iv.i19, ptr %gep.iv, align 8
-
-  ;; Loop condition.
-  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
-  %cond = icmp eq i64 %indvars.iv.next, %n
-  br i1 %cond, label %exit, label %loop
-
-exit:
-  ret void
-}
-
-; In the function below some of the accesses are done as double types and some
-; are done as i64 and i32 types. This is a negative test to ensure that they
-; are not analyzed as in the tests above.
-
-; CHECK-LABEL: function 'neg_dist_dep_type_size_equivalence':
-; CHECK-NEXT:    loop:
-; CHECK-NEXT:      Report: unsafe dependent memory operations in loop.
-; CHECK-NEXT:      Unknown data dependence.
-; CHECK-NEXT:      Dependences:
-; CHECK-NEXT:        Unknown:
-; CHECK-NEXT:            %ld.f64 = load double, ptr %gep.iv, align 8 ->
-; CHECK-NEXT:		         store i32 %ld.i64.i32, ptr %gep.iv.n, align 8
-; CHECK-EMPTY:
-; CHECK-NEXT:        Unknown:
-; CHECK-NEXT:            %ld.i64 = load i64, ptr %gep.iv, align 8 ->
-; CHECK-NEXT:		         store i32 %ld.i64.i32, ptr %gep.iv.n, align 8
-; CHECK-EMPTY:
-; CHECK-NEXT:        BackwardVectorizableButPreventsForwarding:
-; CHECK-NEXT:            %ld.f64 = load double, ptr %gep.iv, align 8 ->
-; CHECK-NEXT:            store double %val, ptr %gep.iv.101, align 8
-; CHECK-EMPTY:
-; CHECK-NEXT:        ForwardButPreventsForwarding:
-; CHECK-NEXT:            store double %val, ptr %gep.iv.101, align 8 ->
-; CHECK-NEXT:            %ld.i64 = load i64, ptr %gep.iv, align 8
-; CHECK-EMPTY:
-; CHECK-NEXT:        Unknown:
-; CHECK-NEXT:            store double %val, ptr %gep.iv.101, align 8 ->
-; CHECK-NEXT:		         store i32 %ld.i64.i32, ptr %gep.iv.n, align 8
-; CHECK-EMPTY:
-; CHECK-NEXT:      Run-time memory checks:
-; CHECK-NEXT:      Grouped accesses:
-
-define void @neg_dist_dep_type_size_equivalence(ptr nocapture %vec, i64 %n) {
-entry:
-  br label %loop
-
-loop:
-  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %loop ]
-
-  ;; Load from vec[indvars.iv] as double
-  %gep.iv = getelementptr i64, ptr %vec, i64 %indvars.iv
-  %ld.f64 = load double, ptr %gep.iv, align 8
-  %val = fmul fast double %ld.f64, 5.0
-
-  ;; Store to vec[indvars.iv + 101] as double
-  %indvars.iv.101 = add nsw i64 %indvars.iv, 101
-  %gep.iv.101 = getelementptr i64, ptr %vec, i64 %indvars.iv.101
-  store double %val, ptr %gep.iv.101, align 8
-
-  ;; Read from vec[indvars.iv] as i64 creating
-  ;; a forward but prevents forwarding dependence
-  ;; with different types but same sizes.
-  %ld.i64 = load i64, ptr %gep.iv, align 8
-
-  ;; Different sizes
-  %indvars.iv.n = add nuw nsw i64 %indvars.iv, %n
-  %gep.iv.n = getelementptr inbounds i64, ptr %vec, i64 %indvars.iv.n
-  %ld.i64.i32 = trunc i64 %ld.i64 to i32
-  store i32 %ld.i64.i32, ptr %gep.iv.n, align 8
-
-  ;; Loop condition.
-  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
-  %cond = icmp eq i64 %indvars.iv.next, %n
-  br i1 %cond, label %exit, label %loop
-
-exit:
-  ret void
-}
-- 
GitLab


From 5c8755f9f40e5b5f4e26a9a0fdb4993cb8a57202 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@sifive.com>
Date: Sat, 9 Dec 2023 14:02:11 -0800
Subject: [PATCH 036/349] [RISCV] Use Triple::isRISCV64(). NFC

---
 clang/lib/Basic/Targets/RISCV.cpp | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
index 13f934e99472..1a4300e16ce7 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -131,7 +131,7 @@ static unsigned getVersionValue(unsigned MajorVersion, unsigned MinorVersion) {
 void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
                                        MacroBuilder &Builder) const {
   Builder.defineMacro("__riscv");
-  bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;
+  bool Is64Bit = getTriple().isRISCV64();
   Builder.defineMacro("__riscv_xlen", Is64Bit ? "64" : "32");
   StringRef CodeModel = getTargetOpts().CodeModel;
   unsigned FLen = ISAInfo->getFLen();
@@ -281,7 +281,7 @@ bool RISCVTargetInfo::initFeatureMap(
 
   unsigned XLen = 32;
 
-  if (getTriple().getArch() == llvm::Triple::riscv64) {
+  if (getTriple().isRISCV64()) {
     Features["64bit"] = true;
     XLen = 64;
   } else {
@@ -336,7 +336,7 @@ RISCVTargetInfo::getVScaleRange(const LangOptions &LangOpts) const {
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
 bool RISCVTargetInfo::hasFeature(StringRef Feature) const {
-  bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;
+  bool Is64Bit = getTriple().isRISCV64();
   auto Result = llvm::StringSwitch<std::optional<bool>>(Feature)
                     .Case("riscv", true)
                     .Case("riscv32", !Is64Bit)
-- 
GitLab


From cc4ecfd68b79a44f101fe9924d088a83477797c0 Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu@google.com>
Date: Sat, 9 Dec 2023 14:28:45 -0800
Subject: [PATCH 037/349] [ADT] Rename SmallString::{starts,ends}with to
 {starts,ends}_with (#74916)

This patch renames {starts,ends}with to {starts,ends}_with for
consistency with std::{string,string_view}::{starts,ends}_with in
C++20.  Since there are only a handful of occurrences, this patch
skips the deprecation phase and simply renames them.
---
 clang-tools-extra/clang-doc/Mapper.cpp            |  2 +-
 clang-tools-extra/modularize/ModuleAssistant.cpp  |  2 +-
 clang/lib/AST/MicrosoftMangle.cpp                 |  8 ++++----
 clang/lib/Basic/Module.cpp                        |  2 +-
 clang/lib/CrossTU/CrossTranslationUnit.cpp        |  2 +-
 clang/lib/Driver/Driver.cpp                       |  2 +-
 clang/lib/Driver/ToolChains/Darwin.cpp            |  2 +-
 clang/lib/Lex/ModuleMap.cpp                       |  2 +-
 clang/lib/Sema/SemaCodeComplete.cpp               |  2 +-
 lld/COFF/PDB.cpp                                  |  2 +-
 lld/MachO/InputFiles.cpp                          |  2 +-
 lldb/source/Commands/CommandCompletions.cpp       |  2 +-
 llvm/include/llvm/ADT/SmallString.h               | 12 ++++--------
 llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp |  2 +-
 llvm/lib/Support/Windows/Path.inc                 |  4 ++--
 llvm/tools/dsymutil/DebugMap.cpp                  |  2 +-
 llvm/tools/llvm-cov/CodeCoverage.cpp              |  2 +-
 llvm/tools/llvm-cov/CoverageReport.cpp            |  2 +-
 llvm/tools/llvm-cov/SourceCoverageViewHTML.cpp    |  2 +-
 llvm/tools/llvm-ml/llvm-ml.cpp                    |  2 +-
 llvm/unittests/Support/Path.cpp                   | 12 ++++++------
 21 files changed, 33 insertions(+), 37 deletions(-)

diff --git a/clang-tools-extra/clang-doc/Mapper.cpp b/clang-tools-extra/clang-doc/Mapper.cpp
index 5264417748a1..bb8b7952980a 100644
--- a/clang-tools-extra/clang-doc/Mapper.cpp
+++ b/clang-tools-extra/clang-doc/Mapper.cpp
@@ -103,7 +103,7 @@ llvm::SmallString<128> MapASTVisitor::getFile(const NamedDecl *D,
                                   .getPresumedLoc(D->getBeginLoc())
                                   .getFilename());
   IsFileInRootDir = false;
-  if (RootDir.empty() || !File.startswith(RootDir))
+  if (RootDir.empty() || !File.starts_with(RootDir))
     return File;
   IsFileInRootDir = true;
   llvm::SmallString<128> Prefix(RootDir);
diff --git a/clang-tools-extra/modularize/ModuleAssistant.cpp b/clang-tools-extra/modularize/ModuleAssistant.cpp
index 0d4c09987eb1..5c11ffdb8589 100644
--- a/clang-tools-extra/modularize/ModuleAssistant.cpp
+++ b/clang-tools-extra/modularize/ModuleAssistant.cpp
@@ -175,7 +175,7 @@ static bool addModuleDescription(Module *RootModule,
   llvm::SmallString<256> NativePath, NativePrefix;
   llvm::sys::path::native(HeaderFilePath, NativePath);
   llvm::sys::path::native(HeaderPrefix, NativePrefix);
-  if (NativePath.startswith(NativePrefix))
+  if (NativePath.starts_with(NativePrefix))
     FilePath = std::string(NativePath.substr(NativePrefix.size() + 1));
   else
     FilePath = std::string(HeaderFilePath);
diff --git a/clang/lib/AST/MicrosoftMangle.cpp b/clang/lib/AST/MicrosoftMangle.cpp
index 50ab6ea59be9..c59a66e103a6 100644
--- a/clang/lib/AST/MicrosoftMangle.cpp
+++ b/clang/lib/AST/MicrosoftMangle.cpp
@@ -3809,14 +3809,14 @@ void MicrosoftMangleContextImpl::mangleCXXRTTICompleteObjectLocator(
   llvm::raw_svector_ostream Stream(VFTableMangling);
   mangleCXXVFTable(Derived, BasePath, Stream);
 
-  if (VFTableMangling.startswith("??@")) {
-    assert(VFTableMangling.endswith("@"));
+  if (VFTableMangling.starts_with("??@")) {
+    assert(VFTableMangling.ends_with("@"));
     Out << VFTableMangling << "??_R4@";
     return;
   }
 
-  assert(VFTableMangling.startswith("??_7") ||
-         VFTableMangling.startswith("??_S"));
+  assert(VFTableMangling.starts_with("??_7") ||
+         VFTableMangling.starts_with("??_S"));
 
   Out << "??_R4" << VFTableMangling.str().drop_front(4);
 }
diff --git a/clang/lib/Basic/Module.cpp b/clang/lib/Basic/Module.cpp
index e4ac1abf12a7..7523e509a471 100644
--- a/clang/lib/Basic/Module.cpp
+++ b/clang/lib/Basic/Module.cpp
@@ -89,7 +89,7 @@ static bool isPlatformEnvironment(const TargetInfo &Target, StringRef Feature) {
   // where both are valid examples of the same platform+environment but in the
   // variant (2) the simulator is hardcoded as part of the platform name. Both
   // forms above should match for "iossimulator" requirement.
-  if (Target.getTriple().isOSDarwin() && PlatformEnv.endswith("simulator"))
+  if (Target.getTriple().isOSDarwin() && PlatformEnv.ends_with("simulator"))
     return PlatformEnv == Feature || CmpPlatformEnv(PlatformEnv, Feature);
 
   return PlatformEnv == Feature;
diff --git a/clang/lib/CrossTU/CrossTranslationUnit.cpp b/clang/lib/CrossTU/CrossTranslationUnit.cpp
index 540c22d07865..94c10e50d7d0 100644
--- a/clang/lib/CrossTU/CrossTranslationUnit.cpp
+++ b/clang/lib/CrossTU/CrossTranslationUnit.cpp
@@ -551,7 +551,7 @@ CrossTranslationUnitContext::ASTLoader::load(StringRef Identifier) {
   // Normalize by removing relative path components.
   llvm::sys::path::remove_dots(Path, /*remove_dot_dot*/ true, PathStyle);
 
-  if (Path.endswith(".ast"))
+  if (Path.ends_with(".ast"))
     return loadFromDump(Path);
   else
     return loadFromSource(Path);
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index e241706b9082..f392f6794f85 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -1522,7 +1522,7 @@ bool Driver::getCrashDiagnosticFile(StringRef ReproCrashFilename,
   // (or /Library/Logs/DiagnosticReports for root) and has the filename pattern
   // clang-<VERSION>_<YYYY-MM-DD-HHMMSS>_<hostname>.crash.
   path::home_directory(CrashDiagDir);
-  if (CrashDiagDir.startswith("/var/root"))
+  if (CrashDiagDir.starts_with("/var/root"))
     CrashDiagDir = "/";
   path::append(CrashDiagDir, "Library/Logs/DiagnosticReports");
   int PID =
diff --git a/clang/lib/Driver/ToolChains/Darwin.cpp b/clang/lib/Driver/ToolChains/Darwin.cpp
index f09bc27d7d2c..692b3a3f285d 100644
--- a/clang/lib/Driver/ToolChains/Darwin.cpp
+++ b/clang/lib/Driver/ToolChains/Darwin.cpp
@@ -1281,7 +1281,7 @@ void MachO::AddLinkRuntimeLib(const ArgList &Args, ArgStringList &CmdArgs,
   // rpaths. This is currently true from this place, but we need to be
   // careful if this function is ever called before user's rpaths are emitted.
   if (Opts & RLO_AddRPath) {
-    assert(DarwinLibName.endswith(".dylib") && "must be a dynamic library");
+    assert(DarwinLibName.ends_with(".dylib") && "must be a dynamic library");
 
     // Add @executable_path to rpath to support having the dylib copied with
     // the executable.
diff --git a/clang/lib/Lex/ModuleMap.cpp b/clang/lib/Lex/ModuleMap.cpp
index 268b72c966ab..d35c282543c5 100644
--- a/clang/lib/Lex/ModuleMap.cpp
+++ b/clang/lib/Lex/ModuleMap.cpp
@@ -1864,7 +1864,7 @@ void ModuleMapParser::diagnosePrivateModules(SourceLocation ExplicitLoc,
       continue;
 
     SmallString<128> FullName(ActiveModule->getFullModuleName());
-    if (!FullName.startswith(M->Name) && !FullName.endswith("Private"))
+    if (!FullName.starts_with(M->Name) && !FullName.ends_with("Private"))
       continue;
     SmallString<128> FixedPrivModDecl;
     SmallString<128> Canonical(M->Name);
diff --git a/clang/lib/Sema/SemaCodeComplete.cpp b/clang/lib/Sema/SemaCodeComplete.cpp
index 6169144ef1c2..143968b4ab04 100644
--- a/clang/lib/Sema/SemaCodeComplete.cpp
+++ b/clang/lib/Sema/SemaCodeComplete.cpp
@@ -10112,7 +10112,7 @@ void Sema::CodeCompleteIncludedFile(llvm::StringRef Dir, bool Angled) {
     const StringRef &Dirname = llvm::sys::path::filename(Dir);
     const bool isQt = Dirname.startswith("Qt") || Dirname == "ActiveQt";
     const bool ExtensionlessHeaders =
-        IsSystem || isQt || Dir.endswith(".framework/Headers");
+        IsSystem || isQt || Dir.ends_with(".framework/Headers");
     std::error_code EC;
     unsigned Count = 0;
     for (auto It = FS.dir_begin(Dir, EC);
diff --git a/lld/COFF/PDB.cpp b/lld/COFF/PDB.cpp
index f77ff0d4eab8..8b81a71e8fb6 100644
--- a/lld/COFF/PDB.cpp
+++ b/lld/COFF/PDB.cpp
@@ -268,7 +268,7 @@ void PDBLinker::pdbMakeAbsolute(SmallVectorImpl<char> &fileName) {
   // decide that it's a unix path if we're fairly certain.  Specifically, if
   // it starts with a forward slash.
   SmallString<128> absoluteFileName = ctx.config.pdbSourcePath;
-  sys::path::Style guessedStyle = absoluteFileName.startswith("/")
+  sys::path::Style guessedStyle = absoluteFileName.starts_with("/")
                                       ? sys::path::Style::posix
                                       : sys::path::Style::windows;
   sys::path::append(absoluteFileName, guessedStyle, fileName);
diff --git a/lld/MachO/InputFiles.cpp b/lld/MachO/InputFiles.cpp
index 31ed24149e78..7d0cdce9de7d 100644
--- a/lld/MachO/InputFiles.cpp
+++ b/lld/MachO/InputFiles.cpp
@@ -1535,7 +1535,7 @@ std::string ObjFile::sourceFile() const {
   StringRef sep = sys::path::get_separator();
   // We don't use `path::append` here because we want an empty `dir` to result
   // in an absolute path. `append` would give us a relative path for that case.
-  if (!dir.endswith(sep))
+  if (!dir.ends_with(sep))
     dir += sep;
   return (dir + unitName).str();
 }
diff --git a/lldb/source/Commands/CommandCompletions.cpp b/lldb/source/Commands/CommandCompletions.cpp
index 4d7e3d7f2497..0b69ce098195 100644
--- a/lldb/source/Commands/CommandCompletions.cpp
+++ b/lldb/source/Commands/CommandCompletions.cpp
@@ -333,7 +333,7 @@ static void DiskFilesOrDirectories(const llvm::Twine &partial_name,
   llvm::StringRef SearchDir;
   llvm::StringRef PartialItem;
 
-  if (CompletionBuffer.startswith("~")) {
+  if (CompletionBuffer.starts_with("~")) {
     llvm::StringRef Buffer = CompletionBuffer;
     size_t FirstSep =
         Buffer.find_if([](char c) { return path::is_separator(c); });
diff --git a/llvm/include/llvm/ADT/SmallString.h b/llvm/include/llvm/ADT/SmallString.h
index 0052c86fb37b..02fa28fc856d 100644
--- a/llvm/include/llvm/ADT/SmallString.h
+++ b/llvm/include/llvm/ADT/SmallString.h
@@ -120,15 +120,11 @@ public:
   /// @name String Predicates
   /// @{
 
-  /// startswith - Check if this string starts with the given \p Prefix.
-  bool startswith(StringRef Prefix) const {
-    return str().startswith(Prefix);
-  }
+  /// starts_with - Check if this string starts with the given \p Prefix.
+  bool starts_with(StringRef Prefix) const { return str().starts_with(Prefix); }
 
-  /// endswith - Check if this string ends with the given \p Suffix.
-  bool endswith(StringRef Suffix) const {
-    return str().endswith(Suffix);
-  }
+  /// ends_with - Check if this string ends with the given \p Suffix.
+  bool ends_with(StringRef Suffix) const { return str().ends_with(Suffix); }
 
   /// @}
   /// @name String Searching
diff --git a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
index 16cc83b8881f..9827bd3ff4f1 100644
--- a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
@@ -1048,7 +1048,7 @@ MCSection *TargetLoweringObjectFileELF::getSectionForMachineBasicBlock(
     } else {
       Name += FunctionSectionName;
       if (TM.getUniqueBasicBlockSectionNames()) {
-        if (!Name.endswith("."))
+        if (!Name.ends_with("."))
           Name += ".";
         Name += MBB.getSymbol()->getName();
       } else {
diff --git a/llvm/lib/Support/Windows/Path.inc b/llvm/lib/Support/Windows/Path.inc
index e4563fd6ed9e..168a63bb2d96 100644
--- a/llvm/lib/Support/Windows/Path.inc
+++ b/llvm/lib/Support/Windows/Path.inc
@@ -76,7 +76,7 @@ std::error_code widenPath(const Twine &Path8, SmallVectorImpl<wchar_t> &Path16,
 
   // If the path is a long path, mangled into forward slashes, normalize
   // back to backslashes here.
-  if (Path8Str.startswith("//?/"))
+  if (Path8Str.starts_with("//?/"))
     llvm::sys::path::native(Path8Str, path::Style::windows_backslash);
 
   if (std::error_code EC = UTF8ToUTF16(Path8Str, Path16))
@@ -96,7 +96,7 @@ std::error_code widenPath(const Twine &Path8, SmallVectorImpl<wchar_t> &Path16,
   const char *const LongPathPrefix = "\\\\?\\";
 
   if ((Path16.size() + CurPathLen) < MaxPathLen ||
-      Path8Str.startswith(LongPathPrefix))
+      Path8Str.starts_with(LongPathPrefix))
     return std::error_code();
 
   if (!IsAbsolute) {
diff --git a/llvm/tools/dsymutil/DebugMap.cpp b/llvm/tools/dsymutil/DebugMap.cpp
index dcdecdfe8210..8724b70422f3 100644
--- a/llvm/tools/dsymutil/DebugMap.cpp
+++ b/llvm/tools/dsymutil/DebugMap.cpp
@@ -287,7 +287,7 @@ MappingTraits<dsymutil::DebugMapObject>::YamlDMO::denormalize(IO &IO) {
   }
 
   uint8_t Type = MachO::N_OSO;
-  if (Path.endswith(".dylib")) {
+  if (Path.ends_with(".dylib")) {
     // FIXME: find a more resilient way
     Type = MachO::N_LIB;
   }
diff --git a/llvm/tools/llvm-cov/CodeCoverage.cpp b/llvm/tools/llvm-cov/CodeCoverage.cpp
index b5d763d8643c..c1e3e2c4d1e2 100644
--- a/llvm/tools/llvm-cov/CodeCoverage.cpp
+++ b/llvm/tools/llvm-cov/CodeCoverage.cpp
@@ -502,7 +502,7 @@ void CodeCoverageTool::remapPathNames(const CoverageMapping &Coverage) {
       SmallString<128> NativeFilename;
       sys::path::native(Filename, NativeFilename);
       sys::path::remove_dots(NativeFilename, true);
-      if (NativeFilename.startswith(RemapFrom)) {
+      if (NativeFilename.starts_with(RemapFrom)) {
         RemappedFilenames[Filename] =
             RemapTo + NativeFilename.substr(RemapFrom.size()).str();
       }
diff --git a/llvm/tools/llvm-cov/CoverageReport.cpp b/llvm/tools/llvm-cov/CoverageReport.cpp
index 060733b2d5d6..eae2653b85c8 100644
--- a/llvm/tools/llvm-cov/CoverageReport.cpp
+++ b/llvm/tools/llvm-cov/CoverageReport.cpp
@@ -211,7 +211,7 @@ void CoverageReport::render(const FileCoverageSummary &File,
   sys::path::native(FileName);
 
   // remove_dots will remove trailing slash, so we need to check before it.
-  auto IsDir = FileName.endswith(sys::path::get_separator());
+  auto IsDir = FileName.ends_with(sys::path::get_separator());
   sys::path::remove_dots(FileName, /*remove_dot_dot=*/true);
   if (IsDir)
     FileName += sys::path::get_separator();
diff --git a/llvm/tools/llvm-cov/SourceCoverageViewHTML.cpp b/llvm/tools/llvm-cov/SourceCoverageViewHTML.cpp
index 79a0494815c2..d0a2e44be252 100644
--- a/llvm/tools/llvm-cov/SourceCoverageViewHTML.cpp
+++ b/llvm/tools/llvm-cov/SourceCoverageViewHTML.cpp
@@ -639,7 +639,7 @@ struct CoveragePrinterHTMLDirectory::Reporter : public DirectoryCoverageReport {
     sys::path::native(LinkTextStr);
 
     // remove_dots will remove trailing slash, so we need to check before it.
-    auto IsDir = LinkTextStr.endswith(sys::path::get_separator());
+    auto IsDir = LinkTextStr.ends_with(sys::path::get_separator());
     sys::path::remove_dots(LinkTextStr, /*remove_dot_dot=*/true);
 
     SmallString<128> LinkTargetStr(LinkTextStr);
diff --git a/llvm/tools/llvm-ml/llvm-ml.cpp b/llvm/tools/llvm-ml/llvm-ml.cpp
index 4d6bd90d13ad..1c713304e4ea 100644
--- a/llvm/tools/llvm-ml/llvm-ml.cpp
+++ b/llvm/tools/llvm-ml/llvm-ml.cpp
@@ -83,7 +83,7 @@ static Triple GetTriple(StringRef ProgName, opt::InputArgList &Args) {
   StringRef DefaultBitness = "32";
   SmallString<255> Program = ProgName;
   sys::path::replace_extension(Program, "");
-  if (Program.endswith("ml64"))
+  if (Program.ends_with("ml64"))
     DefaultBitness = "64";
 
   StringRef TripleName =
diff --git a/llvm/unittests/Support/Path.cpp b/llvm/unittests/Support/Path.cpp
index 35a01aa27667..a7b7e6a0f504 100644
--- a/llvm/unittests/Support/Path.cpp
+++ b/llvm/unittests/Support/Path.cpp
@@ -882,7 +882,7 @@ TEST_F(FileSystemTest, TempFiles) {
   int FD2;
   SmallString<64> TempPath2;
   ASSERT_NO_ERROR(fs::createTemporaryFile("prefix", "temp", FD2, TempPath2));
-  ASSERT_TRUE(TempPath2.endswith(".temp"));
+  ASSERT_TRUE(TempPath2.ends_with(".temp"));
   ASSERT_NE(TempPath.str(), TempPath2.str());
 
   fs::file_status A, B;
@@ -908,7 +908,7 @@ TEST_F(FileSystemTest, TempFiles) {
 
   SmallString<64> TempPath3;
   ASSERT_NO_ERROR(fs::createTemporaryFile("prefix", "", TempPath3));
-  ASSERT_FALSE(TempPath3.endswith("."));
+  ASSERT_FALSE(TempPath3.ends_with("."));
   FileRemover Cleanup3(TempPath3);
 
   // Create a hard link to Temp1.
@@ -1515,13 +1515,13 @@ TEST(Support, NormalizePath) {
   const char *Path7a = "~/aaa";
   SmallString<64> Path7(Path7a);
   path::native(Path7, path::Style::windows_backslash);
-  EXPECT_TRUE(Path7.endswith("\\aaa"));
-  EXPECT_TRUE(Path7.startswith(PathHome));
+  EXPECT_TRUE(Path7.ends_with("\\aaa"));
+  EXPECT_TRUE(Path7.starts_with(PathHome));
   EXPECT_EQ(Path7.size(), PathHome.size() + strlen(Path7a + 1));
   Path7 = Path7a;
   path::native(Path7, path::Style::windows_slash);
-  EXPECT_TRUE(Path7.endswith("/aaa"));
-  EXPECT_TRUE(Path7.startswith(PathHome));
+  EXPECT_TRUE(Path7.ends_with("/aaa"));
+  EXPECT_TRUE(Path7.starts_with(PathHome));
   EXPECT_EQ(Path7.size(), PathHome.size() + strlen(Path7a + 1));
 
   const char *Path8a = "~";
-- 
GitLab


From bf9125294da1f3cf03a88356e068725c6f88bea6 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@sifive.com>
Date: Sat, 9 Dec 2023 14:16:09 -0800
Subject: [PATCH 038/349] [RISCV] Remove unnecessary call to
 isSupportedExtensionFeature.

hasExtension already checks if the extension is supported.
---
 clang/lib/Basic/Targets/RISCV.cpp | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
index 1a4300e16ce7..b1733b878e88 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -347,10 +347,7 @@ bool RISCVTargetInfo::hasFeature(StringRef Feature) const {
   if (Result)
     return *Result;
 
-  if (ISAInfo->isSupportedExtensionFeature(Feature))
-    return ISAInfo->hasExtension(Feature);
-
-  return false;
+  return ISAInfo->hasExtension(Feature);
 }
 
 /// Perform initialization based on the user configured set of features.
-- 
GitLab


From 2ec95c19a267b5e58033701b12f55e0870bd3e6a Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu@google.com>
Date: Sat, 9 Dec 2023 17:08:48 -0800
Subject: [PATCH 039/349] [clang] Use llvm::to_underlying (NFC)

---
 clang/include/clang/AST/Type.h |  3 ++-
 clang/lib/CodeGen/CGCall.h     | 11 +++++------
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h
index b14184afe584..b3ae66e6e769 100644
--- a/clang/include/clang/AST/Type.h
+++ b/clang/include/clang/AST/Type.h
@@ -36,6 +36,7 @@
 #include "llvm/ADT/FoldingSet.h"
 #include "llvm/ADT/PointerIntPair.h"
 #include "llvm/ADT/PointerUnion.h"
+#include "llvm/ADT/STLForwardCompat.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/ADT/iterator_range.h"
@@ -7514,7 +7515,7 @@ inline const Type *Type::getPointeeOrArrayElementType() const {
 /// spaces into a diagnostic with <<.
 inline const StreamingDiagnostic &operator<<(const StreamingDiagnostic &PD,
                                              LangAS AS) {
-  PD.AddTaggedVal(static_cast<std::underlying_type_t<LangAS>>(AS),
+  PD.AddTaggedVal(llvm::to_underlying(AS),
                   DiagnosticsEngine::ArgumentKind::ak_addrspace);
   return PD;
 }
diff --git a/clang/lib/CodeGen/CGCall.h b/clang/lib/CodeGen/CGCall.h
index aee86a3242fd..1c0d15dc932a 100644
--- a/clang/lib/CodeGen/CGCall.h
+++ b/clang/lib/CodeGen/CGCall.h
@@ -20,6 +20,7 @@
 #include "clang/AST/CanonicalType.h"
 #include "clang/AST/GlobalDecl.h"
 #include "clang/AST/Type.h"
+#include "llvm/ADT/STLForwardCompat.h"
 #include "llvm/IR/Value.h"
 
 namespace llvm {
@@ -406,15 +407,13 @@ enum class FnInfoOpts {
 };
 
 inline FnInfoOpts operator|(FnInfoOpts A, FnInfoOpts B) {
-  return static_cast<FnInfoOpts>(
-      static_cast<std::underlying_type_t<FnInfoOpts>>(A) |
-      static_cast<std::underlying_type_t<FnInfoOpts>>(B));
+  return static_cast<FnInfoOpts>(llvm::to_underlying(A) |
+                                 llvm::to_underlying(B));
 }
 
 inline FnInfoOpts operator&(FnInfoOpts A, FnInfoOpts B) {
-  return static_cast<FnInfoOpts>(
-      static_cast<std::underlying_type_t<FnInfoOpts>>(A) &
-      static_cast<std::underlying_type_t<FnInfoOpts>>(B));
+  return static_cast<FnInfoOpts>(llvm::to_underlying(A) &
+                                 llvm::to_underlying(B));
 }
 
 inline FnInfoOpts operator|=(FnInfoOpts A, FnInfoOpts B) {
-- 
GitLab


From c60ac509399da5cba533b9b6cc5b983c59f7d7b3 Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu@google.com>
Date: Sat, 9 Dec 2023 17:34:10 -0800
Subject: [PATCH 040/349] [clang-tools-extra] Use llvm::to_underlying (NFC)

---
 .../readability/FunctionCognitiveComplexityCheck.cpp  | 11 +++++------
 clang-tools-extra/pseudo/include/clang-pseudo/Token.h |  5 +++--
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/clang-tools-extra/clang-tidy/readability/FunctionCognitiveComplexityCheck.cpp b/clang-tools-extra/clang-tidy/readability/FunctionCognitiveComplexityCheck.cpp
index 831614148c7c..759cdd44fd65 100644
--- a/clang-tools-extra/clang-tidy/readability/FunctionCognitiveComplexityCheck.cpp
+++ b/clang-tools-extra/clang-tidy/readability/FunctionCognitiveComplexityCheck.cpp
@@ -20,6 +20,7 @@
 #include "clang/Basic/DiagnosticIDs.h"
 #include "clang/Basic/LLVM.h"
 #include "clang/Basic/SourceLocation.h"
+#include "llvm/ADT/STLForwardCompat.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/ErrorHandling.h"
@@ -167,15 +168,13 @@ static const std::array<const StringRef, 4> Msgs = {{
 // Criteria is a bitset, thus a few helpers are needed.
 CognitiveComplexity::Criteria operator|(CognitiveComplexity::Criteria LHS,
                                         CognitiveComplexity::Criteria RHS) {
-  return static_cast<CognitiveComplexity::Criteria>(
-      static_cast<std::underlying_type_t<CognitiveComplexity::Criteria>>(LHS) |
-      static_cast<std::underlying_type_t<CognitiveComplexity::Criteria>>(RHS));
+  return static_cast<CognitiveComplexity::Criteria>(llvm::to_underlying(LHS) |
+                                                    llvm::to_underlying(RHS));
 }
 CognitiveComplexity::Criteria operator&(CognitiveComplexity::Criteria LHS,
                                         CognitiveComplexity::Criteria RHS) {
-  return static_cast<CognitiveComplexity::Criteria>(
-      static_cast<std::underlying_type_t<CognitiveComplexity::Criteria>>(LHS) &
-      static_cast<std::underlying_type_t<CognitiveComplexity::Criteria>>(RHS));
+  return static_cast<CognitiveComplexity::Criteria>(llvm::to_underlying(LHS) &
+                                                    llvm::to_underlying(RHS));
 }
 CognitiveComplexity::Criteria &operator|=(CognitiveComplexity::Criteria &LHS,
                                           CognitiveComplexity::Criteria RHS) {
diff --git a/clang-tools-extra/pseudo/include/clang-pseudo/Token.h b/clang-tools-extra/pseudo/include/clang-pseudo/Token.h
index 22b72c71cbba..859fd7d2b3df 100644
--- a/clang-tools-extra/pseudo/include/clang-pseudo/Token.h
+++ b/clang-tools-extra/pseudo/include/clang-pseudo/Token.h
@@ -32,6 +32,7 @@
 #include "clang/Basic/LangStandard.h"
 #include "clang/Basic/TokenKinds.h"
 #include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/STLForwardCompat.h"
 #include "llvm/Support/raw_ostream.h"
 #include <cstdint>
 #include <limits>
@@ -71,10 +72,10 @@ struct Token {
   Index OriginalIndex = Invalid;
   // Helpers to get/set Flags based on `enum class`.
   template <class T> bool flag(T Mask) const {
-    return Flags & uint8_t{static_cast<std::underlying_type_t<T>>(Mask)};
+    return Flags & uint8_t{llvm::to_underlying(Mask)};
   }
   template <class T> void setFlag(T Mask) {
-    Flags |= uint8_t{static_cast<std::underlying_type_t<T>>(Mask)};
+    Flags |= uint8_t{llvm::to_underlying(Mask)};
   }
 
   /// Returns the next token in the stream. this may not be a sentinel.
-- 
GitLab


From e79ef93c8361f78f50f8c37a955c87131f7c60cf Mon Sep 17 00:00:00 2001
From: James Y Knight <jyknight@google.com>
Date: Sat, 9 Dec 2023 18:08:40 -0500
Subject: [PATCH 041/349] [X86] Rearrange a few atomics tests. NFC.

---
 llvm/test/CodeGen/X86/atomic-nocx16.ll        |  49 ++
 .../CodeGen/X86/atomic-non-integer-fp128.ll   | 152 ++++-
 llvm/test/CodeGen/X86/atomic-non-integer.ll   | 491 +++++++--------
 llvm/test/CodeGen/X86/atomic128.ll            | 576 +-----------------
 llvm/test/CodeGen/X86/atomicf128.ll           |  46 --
 llvm/test/CodeGen/X86/nocx16.ll               |  21 -
 6 files changed, 407 insertions(+), 928 deletions(-)
 create mode 100644 llvm/test/CodeGen/X86/atomic-nocx16.ll
 delete mode 100644 llvm/test/CodeGen/X86/atomicf128.ll
 delete mode 100644 llvm/test/CodeGen/X86/nocx16.ll

diff --git a/llvm/test/CodeGen/X86/atomic-nocx16.ll b/llvm/test/CodeGen/X86/atomic-nocx16.ll
new file mode 100644
index 000000000000..5677541242a2
--- /dev/null
+++ b/llvm/test/CodeGen/X86/atomic-nocx16.ll
@@ -0,0 +1,49 @@
+; RUN: llc < %s -mtriple=x86_64-- -verify-machineinstrs -mcpu=corei7 -mattr=-cx16 | FileCheck %s
+; RUN: llc < %s -mtriple=i386-linux-gnu -verify-machineinstrs -mattr=cx16 | FileCheck -check-prefix=CHECK %s
+
+;; Verify that 128-bit atomics emit a libcall without cx16
+;; available.
+;;
+;; We test 32-bit mode with -mattr=cx16, because it should have no
+;; effect for 32-bit mode.
+
+; CHECK-LABEL: test:
+define void @test(ptr %a) nounwind {
+entry:
+; CHECK: __sync_val_compare_and_swap_16
+  %0 = cmpxchg ptr %a, i128 1, i128 1 seq_cst seq_cst
+; CHECK: __sync_lock_test_and_set_16
+  %1 = atomicrmw xchg ptr %a, i128 1 seq_cst
+; CHECK: __sync_fetch_and_add_16
+  %2 = atomicrmw add ptr %a, i128 1 seq_cst
+; CHECK: __sync_fetch_and_sub_16
+  %3 = atomicrmw sub ptr %a, i128 1 seq_cst
+; CHECK: __sync_fetch_and_and_16
+  %4 = atomicrmw and ptr %a, i128 1 seq_cst
+; CHECK: __sync_fetch_and_nand_16
+  %5 = atomicrmw nand ptr %a, i128 1 seq_cst
+; CHECK: __sync_fetch_and_or_16
+  %6 = atomicrmw or ptr %a, i128 1 seq_cst
+; CHECK: __sync_fetch_and_xor_16
+  %7 = atomicrmw xor ptr %a, i128 1 seq_cst
+; CHECK: __sync_val_compare_and_swap_16
+  %8 = load atomic i128, ptr %a seq_cst, align 16
+; CHECK: __sync_lock_test_and_set_16
+  store atomic i128 %8, ptr %a seq_cst, align 16
+  ret void
+}
+
+; CHECK-LABEL: test_fp:
+define void @test_fp(fp128* %a) nounwind {
+entry:
+; CHECK: __sync_lock_test_and_set_16
+  %0 = atomicrmw xchg fp128* %a, fp128 0xL00000000000000004000900000000000 seq_cst
+; Currently fails to compile:
+;  %1 = atomicrmw fadd fp128* %a, fp128 0xL00000000000000004000900000000000 seq_cst
+;  %2 = atomicrmw fsub fp128* %a, fp128 0xL00000000000000004000900000000000 seq_cst
+; CHECK: __sync_val_compare_and_swap_16
+  %1 = load atomic fp128, fp128* %a seq_cst, align 16
+; CHECK: __sync_lock_test_and_set_16
+  store atomic fp128 %1, fp128* %a seq_cst, align 16
+  ret void
+}
diff --git a/llvm/test/CodeGen/X86/atomic-non-integer-fp128.ll b/llvm/test/CodeGen/X86/atomic-non-integer-fp128.ll
index 6c4d112330f2..9555c45086d6 100644
--- a/llvm/test/CodeGen/X86/atomic-non-integer-fp128.ll
+++ b/llvm/test/CodeGen/X86/atomic-non-integer-fp128.ll
@@ -1,35 +1,139 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-linux-generic -verify-machineinstrs -mattr=-sse | FileCheck %s --check-prefix=X64-NOSSE
-; RUN: llc < %s -mtriple=x86_64-linux-generic -verify-machineinstrs | FileCheck %s --check-prefix=X64-SSE
+; RUN: llc < %s -mtriple=x86_64-linux-generic -verify-machineinstrs -mattr=sse2,cx16 | FileCheck %s --check-prefixes=X64-SSE
+; RUN: llc < %s -mtriple=x86_64-linux-generic -verify-machineinstrs -mattr=avx,cx16 | FileCheck %s --check-prefixes=X64-AVX
+; RUN: llc < %s -mtriple=x86_64-linux-generic -verify-machineinstrs -mattr=avx512f,cx16 | FileCheck %s --check-prefixes=X64-AVX
 
-; Note: This test is testing that the lowering for atomics matches what we
-; currently emit for non-atomics + the atomic restriction.  The presence of
-; particular lowering detail in these tests should not be read as requiring
-; that detail for correctness unless it's related to the atomicity itself.
-; (Specifically, there were reviewer questions about the lowering for halfs
-;  and their calling convention which remain unresolved.)
+; Codegen of fp128 without cx16 is tested in atomic-nocx16.ll
 
 define void @store_fp128(ptr %fptr, fp128 %v) {
-; X64-NOSSE-LABEL: store_fp128:
-; X64-NOSSE:       # %bb.0:
-; X64-NOSSE-NEXT:    pushq %rax
-; X64-NOSSE-NEXT:    .cfi_def_cfa_offset 16
-; X64-NOSSE-NEXT:    callq __sync_lock_test_and_set_16@PLT
-; X64-NOSSE-NEXT:    popq %rax
-; X64-NOSSE-NEXT:    .cfi_def_cfa_offset 8
-; X64-NOSSE-NEXT:    retq
-;
 ; X64-SSE-LABEL: store_fp128:
 ; X64-SSE:       # %bb.0:
-; X64-SSE-NEXT:    subq $24, %rsp
-; X64-SSE-NEXT:    .cfi_def_cfa_offset 32
-; X64-SSE-NEXT:    movaps %xmm0, (%rsp)
-; X64-SSE-NEXT:    movq (%rsp), %rsi
-; X64-SSE-NEXT:    movq {{[0-9]+}}(%rsp), %rdx
-; X64-SSE-NEXT:    callq __sync_lock_test_and_set_16@PLT
-; X64-SSE-NEXT:    addq $24, %rsp
+; X64-SSE-NEXT:    pushq %rbx
+; X64-SSE-NEXT:    .cfi_def_cfa_offset 16
+; X64-SSE-NEXT:    .cfi_offset %rbx, -16
+; X64-SSE-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
+; X64-SSE-NEXT:    movq -{{[0-9]+}}(%rsp), %rbx
+; X64-SSE-NEXT:    movq -{{[0-9]+}}(%rsp), %rcx
+; X64-SSE-NEXT:    movq (%rdi), %rax
+; X64-SSE-NEXT:    movq 8(%rdi), %rdx
+; X64-SSE-NEXT:    .p2align 4, 0x90
+; X64-SSE-NEXT:  .LBB0_1: # %atomicrmw.start
+; X64-SSE-NEXT:    # =>This Inner Loop Header: Depth=1
+; X64-SSE-NEXT:    lock cmpxchg16b (%rdi)
+; X64-SSE-NEXT:    jne .LBB0_1
+; X64-SSE-NEXT:  # %bb.2: # %atomicrmw.end
+; X64-SSE-NEXT:    popq %rbx
 ; X64-SSE-NEXT:    .cfi_def_cfa_offset 8
 ; X64-SSE-NEXT:    retq
+;
+; X64-AVX-LABEL: store_fp128:
+; X64-AVX:       # %bb.0:
+; X64-AVX-NEXT:    pushq %rbx
+; X64-AVX-NEXT:    .cfi_def_cfa_offset 16
+; X64-AVX-NEXT:    .cfi_offset %rbx, -16
+; X64-AVX-NEXT:    vmovaps %xmm0, -{{[0-9]+}}(%rsp)
+; X64-AVX-NEXT:    movq -{{[0-9]+}}(%rsp), %rbx
+; X64-AVX-NEXT:    movq -{{[0-9]+}}(%rsp), %rcx
+; X64-AVX-NEXT:    movq (%rdi), %rax
+; X64-AVX-NEXT:    movq 8(%rdi), %rdx
+; X64-AVX-NEXT:    .p2align 4, 0x90
+; X64-AVX-NEXT:  .LBB0_1: # %atomicrmw.start
+; X64-AVX-NEXT:    # =>This Inner Loop Header: Depth=1
+; X64-AVX-NEXT:    lock cmpxchg16b (%rdi)
+; X64-AVX-NEXT:    jne .LBB0_1
+; X64-AVX-NEXT:  # %bb.2: # %atomicrmw.end
+; X64-AVX-NEXT:    popq %rbx
+; X64-AVX-NEXT:    .cfi_def_cfa_offset 8
+; X64-AVX-NEXT:    retq
   store atomic fp128 %v, ptr %fptr unordered, align 16
   ret void
 }
+
+define fp128 @load_fp128(ptr %fptr) {
+; X64-SSE-LABEL: load_fp128:
+; X64-SSE:       # %bb.0:
+; X64-SSE-NEXT:    pushq %rbx
+; X64-SSE-NEXT:    .cfi_def_cfa_offset 16
+; X64-SSE-NEXT:    .cfi_offset %rbx, -16
+; X64-SSE-NEXT:    xorl %eax, %eax
+; X64-SSE-NEXT:    xorl %edx, %edx
+; X64-SSE-NEXT:    xorl %ecx, %ecx
+; X64-SSE-NEXT:    xorl %ebx, %ebx
+; X64-SSE-NEXT:    lock cmpxchg16b (%rdi)
+; X64-SSE-NEXT:    movq %rdx, -{{[0-9]+}}(%rsp)
+; X64-SSE-NEXT:    movq %rax, -{{[0-9]+}}(%rsp)
+; X64-SSE-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm0
+; X64-SSE-NEXT:    popq %rbx
+; X64-SSE-NEXT:    .cfi_def_cfa_offset 8
+; X64-SSE-NEXT:    retq
+;
+; X64-AVX-LABEL: load_fp128:
+; X64-AVX:       # %bb.0:
+; X64-AVX-NEXT:    pushq %rbx
+; X64-AVX-NEXT:    .cfi_def_cfa_offset 16
+; X64-AVX-NEXT:    .cfi_offset %rbx, -16
+; X64-AVX-NEXT:    xorl %eax, %eax
+; X64-AVX-NEXT:    xorl %edx, %edx
+; X64-AVX-NEXT:    xorl %ecx, %ecx
+; X64-AVX-NEXT:    xorl %ebx, %ebx
+; X64-AVX-NEXT:    lock cmpxchg16b (%rdi)
+; X64-AVX-NEXT:    movq %rdx, -{{[0-9]+}}(%rsp)
+; X64-AVX-NEXT:    movq %rax, -{{[0-9]+}}(%rsp)
+; X64-AVX-NEXT:    vmovaps -{{[0-9]+}}(%rsp), %xmm0
+; X64-AVX-NEXT:    popq %rbx
+; X64-AVX-NEXT:    .cfi_def_cfa_offset 8
+; X64-AVX-NEXT:    retq
+  %v = load atomic fp128, ptr %fptr unordered, align 16
+  ret fp128 %v
+}
+
+define fp128 @exchange_fp128(ptr %fptr, fp128 %x) {
+; X64-SSE-LABEL: exchange_fp128:
+; X64-SSE:       # %bb.0:
+; X64-SSE-NEXT:    pushq %rbx
+; X64-SSE-NEXT:    .cfi_def_cfa_offset 16
+; X64-SSE-NEXT:    .cfi_offset %rbx, -16
+; X64-SSE-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
+; X64-SSE-NEXT:    movq -{{[0-9]+}}(%rsp), %rbx
+; X64-SSE-NEXT:    movq -{{[0-9]+}}(%rsp), %rcx
+; X64-SSE-NEXT:    movq (%rdi), %rax
+; X64-SSE-NEXT:    movq 8(%rdi), %rdx
+; X64-SSE-NEXT:    .p2align 4, 0x90
+; X64-SSE-NEXT:  .LBB2_1: # %atomicrmw.start
+; X64-SSE-NEXT:    # =>This Inner Loop Header: Depth=1
+; X64-SSE-NEXT:    lock cmpxchg16b (%rdi)
+; X64-SSE-NEXT:    jne .LBB2_1
+; X64-SSE-NEXT:  # %bb.2: # %atomicrmw.end
+; X64-SSE-NEXT:    movq %rax, -{{[0-9]+}}(%rsp)
+; X64-SSE-NEXT:    movq %rdx, -{{[0-9]+}}(%rsp)
+; X64-SSE-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm0
+; X64-SSE-NEXT:    popq %rbx
+; X64-SSE-NEXT:    .cfi_def_cfa_offset 8
+; X64-SSE-NEXT:    retq
+;
+; X64-AVX-LABEL: exchange_fp128:
+; X64-AVX:       # %bb.0:
+; X64-AVX-NEXT:    pushq %rbx
+; X64-AVX-NEXT:    .cfi_def_cfa_offset 16
+; X64-AVX-NEXT:    .cfi_offset %rbx, -16
+; X64-AVX-NEXT:    vmovaps %xmm0, -{{[0-9]+}}(%rsp)
+; X64-AVX-NEXT:    movq -{{[0-9]+}}(%rsp), %rbx
+; X64-AVX-NEXT:    movq -{{[0-9]+}}(%rsp), %rcx
+; X64-AVX-NEXT:    movq (%rdi), %rax
+; X64-AVX-NEXT:    movq 8(%rdi), %rdx
+; X64-AVX-NEXT:    .p2align 4, 0x90
+; X64-AVX-NEXT:  .LBB2_1: # %atomicrmw.start
+; X64-AVX-NEXT:    # =>This Inner Loop Header: Depth=1
+; X64-AVX-NEXT:    lock cmpxchg16b (%rdi)
+; X64-AVX-NEXT:    jne .LBB2_1
+; X64-AVX-NEXT:  # %bb.2: # %atomicrmw.end
+; X64-AVX-NEXT:    movq %rax, -{{[0-9]+}}(%rsp)
+; X64-AVX-NEXT:    movq %rdx, -{{[0-9]+}}(%rsp)
+; X64-AVX-NEXT:    vmovaps -{{[0-9]+}}(%rsp), %xmm0
+; X64-AVX-NEXT:    popq %rbx
+; X64-AVX-NEXT:    .cfi_def_cfa_offset 8
+; X64-AVX-NEXT:    retq
+  %v = atomicrmw xchg ptr %fptr, fp128 %x monotonic, align 16
+  ret fp128 %v
+}
+
diff --git a/llvm/test/CodeGen/X86/atomic-non-integer.ll b/llvm/test/CodeGen/X86/atomic-non-integer.ll
index 7d2810e57a25..9e6f584d8311 100644
--- a/llvm/test/CodeGen/X86/atomic-non-integer.ll
+++ b/llvm/test/CodeGen/X86/atomic-non-integer.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i386-linux-generic -verify-machineinstrs -mattr=sse | FileCheck %s --check-prefixes=X86,X86-SSE,X86-SSE1
-; RUN: llc < %s -mtriple=i386-linux-generic -verify-machineinstrs -mattr=sse2 | FileCheck %s --check-prefixes=X86,X86-SSE,X86-SSE2
+; RUN: llc < %s -mtriple=i386-linux-generic -verify-machineinstrs -mattr=sse | FileCheck %s --check-prefixes=X86,X86-SSE1
+; RUN: llc < %s -mtriple=i386-linux-generic -verify-machineinstrs -mattr=sse2 | FileCheck %s --check-prefixes=X86,X86-SSE2
 ; RUN: llc < %s -mtriple=i386-linux-generic -verify-machineinstrs -mattr=avx | FileCheck %s --check-prefixes=X86,X86-AVX
 ; RUN: llc < %s -mtriple=i386-linux-generic -verify-machineinstrs -mattr=avx512f | FileCheck %s --check-prefixes=X86,X86-AVX
 ; RUN: llc < %s -mtriple=i386-linux-generic -verify-machineinstrs | FileCheck %s --check-prefixes=X86,X86-NOSSE
@@ -131,94 +131,6 @@ define void @store_double(ptr %fptr, double %v) {
   ret void
 }
 
-define void @store_fp128(ptr %fptr, fp128 %v) {
-; X86-SSE-LABEL: store_fp128:
-; X86-SSE:       # %bb.0:
-; X86-SSE-NEXT:    subl $36, %esp
-; X86-SSE-NEXT:    .cfi_adjust_cfa_offset 36
-; X86-SSE-NEXT:    leal {{[0-9]+}}(%esp), %eax
-; X86-SSE-NEXT:    pushl {{[0-9]+}}(%esp)
-; X86-SSE-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-SSE-NEXT:    pushl {{[0-9]+}}(%esp)
-; X86-SSE-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-SSE-NEXT:    pushl {{[0-9]+}}(%esp)
-; X86-SSE-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-SSE-NEXT:    pushl {{[0-9]+}}(%esp)
-; X86-SSE-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-SSE-NEXT:    pushl {{[0-9]+}}(%esp)
-; X86-SSE-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-SSE-NEXT:    pushl %eax
-; X86-SSE-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-SSE-NEXT:    calll __sync_lock_test_and_set_16
-; X86-SSE-NEXT:    .cfi_adjust_cfa_offset -4
-; X86-SSE-NEXT:    addl $56, %esp
-; X86-SSE-NEXT:    .cfi_adjust_cfa_offset -56
-; X86-SSE-NEXT:    retl
-;
-; X86-AVX-LABEL: store_fp128:
-; X86-AVX:       # %bb.0:
-; X86-AVX-NEXT:    subl $60, %esp
-; X86-AVX-NEXT:    .cfi_def_cfa_offset 64
-; X86-AVX-NEXT:    vmovaps {{[0-9]+}}(%esp), %xmm0
-; X86-AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-AVX-NEXT:    movl %eax, {{[0-9]+}}(%esp)
-; X86-AVX-NEXT:    vmovups %xmm0, {{[0-9]+}}(%esp)
-; X86-AVX-NEXT:    leal {{[0-9]+}}(%esp), %eax
-; X86-AVX-NEXT:    movl %eax, (%esp)
-; X86-AVX-NEXT:    calll __sync_lock_test_and_set_16
-; X86-AVX-NEXT:    addl $56, %esp
-; X86-AVX-NEXT:    .cfi_def_cfa_offset 4
-; X86-AVX-NEXT:    retl
-;
-; X86-NOSSE-LABEL: store_fp128:
-; X86-NOSSE:       # %bb.0:
-; X86-NOSSE-NEXT:    subl $36, %esp
-; X86-NOSSE-NEXT:    .cfi_adjust_cfa_offset 36
-; X86-NOSSE-NEXT:    leal {{[0-9]+}}(%esp), %eax
-; X86-NOSSE-NEXT:    pushl {{[0-9]+}}(%esp)
-; X86-NOSSE-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-NOSSE-NEXT:    pushl {{[0-9]+}}(%esp)
-; X86-NOSSE-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-NOSSE-NEXT:    pushl {{[0-9]+}}(%esp)
-; X86-NOSSE-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-NOSSE-NEXT:    pushl {{[0-9]+}}(%esp)
-; X86-NOSSE-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-NOSSE-NEXT:    pushl {{[0-9]+}}(%esp)
-; X86-NOSSE-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-NOSSE-NEXT:    pushl %eax
-; X86-NOSSE-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-NOSSE-NEXT:    calll __sync_lock_test_and_set_16
-; X86-NOSSE-NEXT:    .cfi_adjust_cfa_offset -4
-; X86-NOSSE-NEXT:    addl $56, %esp
-; X86-NOSSE-NEXT:    .cfi_adjust_cfa_offset -56
-; X86-NOSSE-NEXT:    retl
-;
-; X64-SSE-LABEL: store_fp128:
-; X64-SSE:       # %bb.0:
-; X64-SSE-NEXT:    subq $24, %rsp
-; X64-SSE-NEXT:    .cfi_def_cfa_offset 32
-; X64-SSE-NEXT:    movaps %xmm0, (%rsp)
-; X64-SSE-NEXT:    movq (%rsp), %rsi
-; X64-SSE-NEXT:    movq {{[0-9]+}}(%rsp), %rdx
-; X64-SSE-NEXT:    callq __sync_lock_test_and_set_16@PLT
-; X64-SSE-NEXT:    addq $24, %rsp
-; X64-SSE-NEXT:    .cfi_def_cfa_offset 8
-; X64-SSE-NEXT:    retq
-;
-; X64-AVX-LABEL: store_fp128:
-; X64-AVX:       # %bb.0:
-; X64-AVX-NEXT:    subq $24, %rsp
-; X64-AVX-NEXT:    .cfi_def_cfa_offset 32
-; X64-AVX-NEXT:    vmovaps %xmm0, (%rsp)
-; X64-AVX-NEXT:    movq (%rsp), %rsi
-; X64-AVX-NEXT:    movq {{[0-9]+}}(%rsp), %rdx
-; X64-AVX-NEXT:    callq __sync_lock_test_and_set_16@PLT
-; X64-AVX-NEXT:    addq $24, %rsp
-; X64-AVX-NEXT:    .cfi_def_cfa_offset 8
-; X64-AVX-NEXT:    retq
-  store atomic fp128 %v, ptr %fptr unordered, align 16
-  ret void
-}
 
 define half @load_half(ptr %fptr) {
 ; X86-SSE1-LABEL: load_half:
@@ -393,220 +305,273 @@ define double @load_double(ptr %fptr) {
   ret double %v
 }
 
-define fp128 @load_fp128(ptr %fptr) {
-; X86-SSE1-LABEL: load_fp128:
+define half @exchange_half(ptr %fptr, half %x) {
+; X86-SSE1-LABEL: exchange_half:
+; X86-SSE1:       # %bb.0:
+; X86-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-SSE1-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; X86-SSE1-NEXT:    xchgw %ax, (%ecx)
+; X86-SSE1-NEXT:    retl
+;
+; X86-SSE2-LABEL: exchange_half:
+; X86-SSE2:       # %bb.0:
+; X86-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-SSE2-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
+; X86-SSE2-NEXT:    xchgw %cx, (%eax)
+; X86-SSE2-NEXT:    pinsrw $0, %ecx, %xmm0
+; X86-SSE2-NEXT:    retl
+;
+; X86-AVX-LABEL: exchange_half:
+; X86-AVX:       # %bb.0:
+; X86-AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-AVX-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
+; X86-AVX-NEXT:    xchgw %cx, (%eax)
+; X86-AVX-NEXT:    vpinsrw $0, %ecx, %xmm0, %xmm0
+; X86-AVX-NEXT:    retl
+;
+; X86-NOSSE-LABEL: exchange_half:
+; X86-NOSSE:       # %bb.0:
+; X86-NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-NOSSE-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; X86-NOSSE-NEXT:    xchgw %ax, (%ecx)
+; X86-NOSSE-NEXT:    retl
+;
+; X64-SSE-LABEL: exchange_half:
+; X64-SSE:       # %bb.0:
+; X64-SSE-NEXT:    pextrw $0, %xmm0, %eax
+; X64-SSE-NEXT:    xchgw %ax, (%rdi)
+; X64-SSE-NEXT:    pinsrw $0, %eax, %xmm0
+; X64-SSE-NEXT:    retq
+;
+; X64-AVX-LABEL: exchange_half:
+; X64-AVX:       # %bb.0:
+; X64-AVX-NEXT:    vpextrw $0, %xmm0, %eax
+; X64-AVX-NEXT:    xchgw %ax, (%rdi)
+; X64-AVX-NEXT:    vpinsrw $0, %eax, %xmm0, %xmm0
+; X64-AVX-NEXT:    retq
+  %v = atomicrmw xchg ptr %fptr, half %x monotonic, align 2
+  ret half %v
+}
+
+define float @exchange_float(ptr %fptr, float %x) {
+; X86-SSE1-LABEL: exchange_float:
 ; X86-SSE1:       # %bb.0:
-; X86-SSE1-NEXT:    pushl %edi
+; X86-SSE1-NEXT:    pushl %eax
+; X86-SSE1-NEXT:    .cfi_def_cfa_offset 8
+; X86-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-SSE1-NEXT:    xchgl %ecx, (%eax)
+; X86-SSE1-NEXT:    movl %ecx, (%esp)
+; X86-SSE1-NEXT:    flds (%esp)
+; X86-SSE1-NEXT:    popl %eax
+; X86-SSE1-NEXT:    .cfi_def_cfa_offset 4
+; X86-SSE1-NEXT:    retl
+;
+; X86-SSE2-LABEL: exchange_float:
+; X86-SSE2:       # %bb.0:
+; X86-SSE2-NEXT:    pushl %eax
+; X86-SSE2-NEXT:    .cfi_def_cfa_offset 8
+; X86-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-SSE2-NEXT:    xchgl %ecx, (%eax)
+; X86-SSE2-NEXT:    movd %ecx, %xmm0
+; X86-SSE2-NEXT:    movd %xmm0, (%esp)
+; X86-SSE2-NEXT:    flds (%esp)
+; X86-SSE2-NEXT:    popl %eax
+; X86-SSE2-NEXT:    .cfi_def_cfa_offset 4
+; X86-SSE2-NEXT:    retl
+;
+; X86-AVX-LABEL: exchange_float:
+; X86-AVX:       # %bb.0:
+; X86-AVX-NEXT:    pushl %eax
+; X86-AVX-NEXT:    .cfi_def_cfa_offset 8
+; X86-AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-AVX-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-AVX-NEXT:    xchgl %ecx, (%eax)
+; X86-AVX-NEXT:    vmovd %ecx, %xmm0
+; X86-AVX-NEXT:    vmovd %xmm0, (%esp)
+; X86-AVX-NEXT:    flds (%esp)
+; X86-AVX-NEXT:    popl %eax
+; X86-AVX-NEXT:    .cfi_def_cfa_offset 4
+; X86-AVX-NEXT:    retl
+;
+; X86-NOSSE-LABEL: exchange_float:
+; X86-NOSSE:       # %bb.0:
+; X86-NOSSE-NEXT:    pushl %eax
+; X86-NOSSE-NEXT:    .cfi_def_cfa_offset 8
+; X86-NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-NOSSE-NEXT:    xchgl %ecx, (%eax)
+; X86-NOSSE-NEXT:    movl %ecx, (%esp)
+; X86-NOSSE-NEXT:    flds (%esp)
+; X86-NOSSE-NEXT:    popl %eax
+; X86-NOSSE-NEXT:    .cfi_def_cfa_offset 4
+; X86-NOSSE-NEXT:    retl
+;
+; X64-SSE-LABEL: exchange_float:
+; X64-SSE:       # %bb.0:
+; X64-SSE-NEXT:    movd %xmm0, %eax
+; X64-SSE-NEXT:    xchgl %eax, (%rdi)
+; X64-SSE-NEXT:    movd %eax, %xmm0
+; X64-SSE-NEXT:    retq
+;
+; X64-AVX-LABEL: exchange_float:
+; X64-AVX:       # %bb.0:
+; X64-AVX-NEXT:    vmovd %xmm0, %eax
+; X64-AVX-NEXT:    xchgl %eax, (%rdi)
+; X64-AVX-NEXT:    vmovd %eax, %xmm0
+; X64-AVX-NEXT:    retq
+  %v = atomicrmw xchg ptr %fptr, float %x monotonic, align 4
+  ret float %v
+}
+
+define double @exchange_double(ptr %fptr, double %x) {
+; X86-SSE1-LABEL: exchange_double:
+; X86-SSE1:       # %bb.0:
+; X86-SSE1-NEXT:    pushl %ebx
 ; X86-SSE1-NEXT:    .cfi_def_cfa_offset 8
 ; X86-SSE1-NEXT:    pushl %esi
 ; X86-SSE1-NEXT:    .cfi_def_cfa_offset 12
-; X86-SSE1-NEXT:    subl $20, %esp
-; X86-SSE1-NEXT:    .cfi_def_cfa_offset 32
+; X86-SSE1-NEXT:    subl $12, %esp
+; X86-SSE1-NEXT:    .cfi_def_cfa_offset 24
 ; X86-SSE1-NEXT:    .cfi_offset %esi, -12
-; X86-SSE1-NEXT:    .cfi_offset %edi, -8
+; X86-SSE1-NEXT:    .cfi_offset %ebx, -8
 ; X86-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %esi
-; X86-SSE1-NEXT:    subl $8, %esp
-; X86-SSE1-NEXT:    .cfi_adjust_cfa_offset 8
-; X86-SSE1-NEXT:    leal {{[0-9]+}}(%esp), %eax
-; X86-SSE1-NEXT:    pushl $0
-; X86-SSE1-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-SSE1-NEXT:    pushl $0
-; X86-SSE1-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-SSE1-NEXT:    pushl $0
-; X86-SSE1-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-SSE1-NEXT:    pushl $0
-; X86-SSE1-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-SSE1-NEXT:    pushl $0
-; X86-SSE1-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-SSE1-NEXT:    pushl $0
-; X86-SSE1-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-SSE1-NEXT:    pushl $0
-; X86-SSE1-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-SSE1-NEXT:    pushl $0
-; X86-SSE1-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-SSE1-NEXT:    pushl {{[0-9]+}}(%esp)
-; X86-SSE1-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-SSE1-NEXT:    pushl %eax
-; X86-SSE1-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-SSE1-NEXT:    calll __sync_val_compare_and_swap_16
-; X86-SSE1-NEXT:    .cfi_adjust_cfa_offset -4
-; X86-SSE1-NEXT:    addl $44, %esp
-; X86-SSE1-NEXT:    .cfi_adjust_cfa_offset -44
-; X86-SSE1-NEXT:    movl (%esp), %eax
+; X86-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %ebx
 ; X86-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X86-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; X86-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %edi
-; X86-SSE1-NEXT:    movl %edi, 8(%esi)
-; X86-SSE1-NEXT:    movl %edx, 12(%esi)
-; X86-SSE1-NEXT:    movl %eax, (%esi)
-; X86-SSE1-NEXT:    movl %ecx, 4(%esi)
-; X86-SSE1-NEXT:    movl %esi, %eax
-; X86-SSE1-NEXT:    addl $20, %esp
+; X86-SSE1-NEXT:    movl (%esi), %eax
+; X86-SSE1-NEXT:    movl 4(%esi), %edx
+; X86-SSE1-NEXT:    .p2align 4, 0x90
+; X86-SSE1-NEXT:  .LBB8_1: # %atomicrmw.start
+; X86-SSE1-NEXT:    # =>This Inner Loop Header: Depth=1
+; X86-SSE1-NEXT:    lock cmpxchg8b (%esi)
+; X86-SSE1-NEXT:    jne .LBB8_1
+; X86-SSE1-NEXT:  # %bb.2: # %atomicrmw.end
+; X86-SSE1-NEXT:    movl %eax, (%esp)
+; X86-SSE1-NEXT:    movl %edx, {{[0-9]+}}(%esp)
+; X86-SSE1-NEXT:    fldl (%esp)
+; X86-SSE1-NEXT:    addl $12, %esp
 ; X86-SSE1-NEXT:    .cfi_def_cfa_offset 12
 ; X86-SSE1-NEXT:    popl %esi
 ; X86-SSE1-NEXT:    .cfi_def_cfa_offset 8
-; X86-SSE1-NEXT:    popl %edi
+; X86-SSE1-NEXT:    popl %ebx
 ; X86-SSE1-NEXT:    .cfi_def_cfa_offset 4
-; X86-SSE1-NEXT:    retl $4
+; X86-SSE1-NEXT:    retl
 ;
-; X86-SSE2-LABEL: load_fp128:
+; X86-SSE2-LABEL: exchange_double:
 ; X86-SSE2:       # %bb.0:
-; X86-SSE2-NEXT:    pushl %esi
+; X86-SSE2-NEXT:    pushl %ebx
 ; X86-SSE2-NEXT:    .cfi_def_cfa_offset 8
-; X86-SSE2-NEXT:    subl $24, %esp
-; X86-SSE2-NEXT:    .cfi_def_cfa_offset 32
-; X86-SSE2-NEXT:    .cfi_offset %esi, -8
+; X86-SSE2-NEXT:    pushl %esi
+; X86-SSE2-NEXT:    .cfi_def_cfa_offset 12
+; X86-SSE2-NEXT:    subl $12, %esp
+; X86-SSE2-NEXT:    .cfi_def_cfa_offset 24
+; X86-SSE2-NEXT:    .cfi_offset %esi, -12
+; X86-SSE2-NEXT:    .cfi_offset %ebx, -8
 ; X86-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %esi
-; X86-SSE2-NEXT:    subl $8, %esp
-; X86-SSE2-NEXT:    .cfi_adjust_cfa_offset 8
-; X86-SSE2-NEXT:    leal {{[0-9]+}}(%esp), %eax
-; X86-SSE2-NEXT:    pushl $0
-; X86-SSE2-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-SSE2-NEXT:    pushl $0
-; X86-SSE2-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-SSE2-NEXT:    pushl $0
-; X86-SSE2-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-SSE2-NEXT:    pushl $0
-; X86-SSE2-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-SSE2-NEXT:    pushl $0
-; X86-SSE2-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-SSE2-NEXT:    pushl $0
-; X86-SSE2-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-SSE2-NEXT:    pushl $0
-; X86-SSE2-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-SSE2-NEXT:    pushl $0
-; X86-SSE2-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-SSE2-NEXT:    pushl {{[0-9]+}}(%esp)
-; X86-SSE2-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-SSE2-NEXT:    pushl %eax
-; X86-SSE2-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-SSE2-NEXT:    calll __sync_val_compare_and_swap_16
-; X86-SSE2-NEXT:    .cfi_adjust_cfa_offset -4
-; X86-SSE2-NEXT:    addl $44, %esp
-; X86-SSE2-NEXT:    .cfi_adjust_cfa_offset -44
-; X86-SSE2-NEXT:    movaps (%esp), %xmm0
-; X86-SSE2-NEXT:    movaps %xmm0, (%esi)
-; X86-SSE2-NEXT:    movl %esi, %eax
-; X86-SSE2-NEXT:    addl $24, %esp
-; X86-SSE2-NEXT:    .cfi_def_cfa_offset 8
+; X86-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %ebx
+; X86-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-SSE2-NEXT:    movl (%esi), %eax
+; X86-SSE2-NEXT:    movl 4(%esi), %edx
+; X86-SSE2-NEXT:    .p2align 4, 0x90
+; X86-SSE2-NEXT:  .LBB8_1: # %atomicrmw.start
+; X86-SSE2-NEXT:    # =>This Inner Loop Header: Depth=1
+; X86-SSE2-NEXT:    lock cmpxchg8b (%esi)
+; X86-SSE2-NEXT:    jne .LBB8_1
+; X86-SSE2-NEXT:  # %bb.2: # %atomicrmw.end
+; X86-SSE2-NEXT:    movd %eax, %xmm0
+; X86-SSE2-NEXT:    movd %edx, %xmm1
+; X86-SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; X86-SSE2-NEXT:    movq %xmm0, (%esp)
+; X86-SSE2-NEXT:    fldl (%esp)
+; X86-SSE2-NEXT:    addl $12, %esp
+; X86-SSE2-NEXT:    .cfi_def_cfa_offset 12
 ; X86-SSE2-NEXT:    popl %esi
+; X86-SSE2-NEXT:    .cfi_def_cfa_offset 8
+; X86-SSE2-NEXT:    popl %ebx
 ; X86-SSE2-NEXT:    .cfi_def_cfa_offset 4
-; X86-SSE2-NEXT:    retl $4
+; X86-SSE2-NEXT:    retl
 ;
-; X86-AVX-LABEL: load_fp128:
+; X86-AVX-LABEL: exchange_double:
 ; X86-AVX:       # %bb.0:
-; X86-AVX-NEXT:    pushl %esi
+; X86-AVX-NEXT:    pushl %ebx
 ; X86-AVX-NEXT:    .cfi_def_cfa_offset 8
-; X86-AVX-NEXT:    subl $72, %esp
-; X86-AVX-NEXT:    .cfi_def_cfa_offset 80
-; X86-AVX-NEXT:    .cfi_offset %esi, -8
+; X86-AVX-NEXT:    pushl %esi
+; X86-AVX-NEXT:    .cfi_def_cfa_offset 12
+; X86-AVX-NEXT:    subl $12, %esp
+; X86-AVX-NEXT:    .cfi_def_cfa_offset 24
+; X86-AVX-NEXT:    .cfi_offset %esi, -12
+; X86-AVX-NEXT:    .cfi_offset %ebx, -8
 ; X86-AVX-NEXT:    movl {{[0-9]+}}(%esp), %esi
-; X86-AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-AVX-NEXT:    vxorps %xmm0, %xmm0, %xmm0
-; X86-AVX-NEXT:    vmovups %ymm0, {{[0-9]+}}(%esp)
-; X86-AVX-NEXT:    movl %eax, {{[0-9]+}}(%esp)
-; X86-AVX-NEXT:    leal {{[0-9]+}}(%esp), %eax
-; X86-AVX-NEXT:    movl %eax, (%esp)
-; X86-AVX-NEXT:    vzeroupper
-; X86-AVX-NEXT:    calll __sync_val_compare_and_swap_16
-; X86-AVX-NEXT:    subl $4, %esp
-; X86-AVX-NEXT:    vmovaps {{[0-9]+}}(%esp), %xmm0
-; X86-AVX-NEXT:    vmovaps %xmm0, (%esi)
-; X86-AVX-NEXT:    movl %esi, %eax
-; X86-AVX-NEXT:    addl $72, %esp
-; X86-AVX-NEXT:    .cfi_def_cfa_offset 8
+; X86-AVX-NEXT:    movl {{[0-9]+}}(%esp), %ebx
+; X86-AVX-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-AVX-NEXT:    movl (%esi), %eax
+; X86-AVX-NEXT:    movl 4(%esi), %edx
+; X86-AVX-NEXT:    .p2align 4, 0x90
+; X86-AVX-NEXT:  .LBB8_1: # %atomicrmw.start
+; X86-AVX-NEXT:    # =>This Inner Loop Header: Depth=1
+; X86-AVX-NEXT:    lock cmpxchg8b (%esi)
+; X86-AVX-NEXT:    jne .LBB8_1
+; X86-AVX-NEXT:  # %bb.2: # %atomicrmw.end
+; X86-AVX-NEXT:    vmovd %eax, %xmm0
+; X86-AVX-NEXT:    vpinsrd $1, %edx, %xmm0, %xmm0
+; X86-AVX-NEXT:    vmovq %xmm0, (%esp)
+; X86-AVX-NEXT:    fldl (%esp)
+; X86-AVX-NEXT:    addl $12, %esp
+; X86-AVX-NEXT:    .cfi_def_cfa_offset 12
 ; X86-AVX-NEXT:    popl %esi
+; X86-AVX-NEXT:    .cfi_def_cfa_offset 8
+; X86-AVX-NEXT:    popl %ebx
 ; X86-AVX-NEXT:    .cfi_def_cfa_offset 4
-; X86-AVX-NEXT:    retl $4
+; X86-AVX-NEXT:    retl
 ;
-; X86-NOSSE-LABEL: load_fp128:
+; X86-NOSSE-LABEL: exchange_double:
 ; X86-NOSSE:       # %bb.0:
-; X86-NOSSE-NEXT:    pushl %edi
+; X86-NOSSE-NEXT:    pushl %ebx
 ; X86-NOSSE-NEXT:    .cfi_def_cfa_offset 8
 ; X86-NOSSE-NEXT:    pushl %esi
 ; X86-NOSSE-NEXT:    .cfi_def_cfa_offset 12
-; X86-NOSSE-NEXT:    subl $20, %esp
-; X86-NOSSE-NEXT:    .cfi_def_cfa_offset 32
+; X86-NOSSE-NEXT:    subl $12, %esp
+; X86-NOSSE-NEXT:    .cfi_def_cfa_offset 24
 ; X86-NOSSE-NEXT:    .cfi_offset %esi, -12
-; X86-NOSSE-NEXT:    .cfi_offset %edi, -8
+; X86-NOSSE-NEXT:    .cfi_offset %ebx, -8
 ; X86-NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %esi
-; X86-NOSSE-NEXT:    subl $8, %esp
-; X86-NOSSE-NEXT:    .cfi_adjust_cfa_offset 8
-; X86-NOSSE-NEXT:    leal {{[0-9]+}}(%esp), %eax
-; X86-NOSSE-NEXT:    pushl $0
-; X86-NOSSE-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-NOSSE-NEXT:    pushl $0
-; X86-NOSSE-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-NOSSE-NEXT:    pushl $0
-; X86-NOSSE-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-NOSSE-NEXT:    pushl $0
-; X86-NOSSE-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-NOSSE-NEXT:    pushl $0
-; X86-NOSSE-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-NOSSE-NEXT:    pushl $0
-; X86-NOSSE-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-NOSSE-NEXT:    pushl $0
-; X86-NOSSE-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-NOSSE-NEXT:    pushl $0
-; X86-NOSSE-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-NOSSE-NEXT:    pushl {{[0-9]+}}(%esp)
-; X86-NOSSE-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-NOSSE-NEXT:    pushl %eax
-; X86-NOSSE-NEXT:    .cfi_adjust_cfa_offset 4
-; X86-NOSSE-NEXT:    calll __sync_val_compare_and_swap_16
-; X86-NOSSE-NEXT:    .cfi_adjust_cfa_offset -4
-; X86-NOSSE-NEXT:    addl $44, %esp
-; X86-NOSSE-NEXT:    .cfi_adjust_cfa_offset -44
-; X86-NOSSE-NEXT:    movl (%esp), %eax
+; X86-NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %ebx
 ; X86-NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X86-NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; X86-NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %edi
-; X86-NOSSE-NEXT:    movl %edi, 8(%esi)
-; X86-NOSSE-NEXT:    movl %edx, 12(%esi)
-; X86-NOSSE-NEXT:    movl %eax, (%esi)
-; X86-NOSSE-NEXT:    movl %ecx, 4(%esi)
-; X86-NOSSE-NEXT:    movl %esi, %eax
-; X86-NOSSE-NEXT:    addl $20, %esp
+; X86-NOSSE-NEXT:    movl (%esi), %eax
+; X86-NOSSE-NEXT:    movl 4(%esi), %edx
+; X86-NOSSE-NEXT:    .p2align 4, 0x90
+; X86-NOSSE-NEXT:  .LBB8_1: # %atomicrmw.start
+; X86-NOSSE-NEXT:    # =>This Inner Loop Header: Depth=1
+; X86-NOSSE-NEXT:    lock cmpxchg8b (%esi)
+; X86-NOSSE-NEXT:    jne .LBB8_1
+; X86-NOSSE-NEXT:  # %bb.2: # %atomicrmw.end
+; X86-NOSSE-NEXT:    movl %eax, (%esp)
+; X86-NOSSE-NEXT:    movl %edx, {{[0-9]+}}(%esp)
+; X86-NOSSE-NEXT:    fldl (%esp)
+; X86-NOSSE-NEXT:    addl $12, %esp
 ; X86-NOSSE-NEXT:    .cfi_def_cfa_offset 12
 ; X86-NOSSE-NEXT:    popl %esi
 ; X86-NOSSE-NEXT:    .cfi_def_cfa_offset 8
-; X86-NOSSE-NEXT:    popl %edi
+; X86-NOSSE-NEXT:    popl %ebx
 ; X86-NOSSE-NEXT:    .cfi_def_cfa_offset 4
-; X86-NOSSE-NEXT:    retl $4
+; X86-NOSSE-NEXT:    retl
 ;
-; X64-SSE-LABEL: load_fp128:
+; X64-SSE-LABEL: exchange_double:
 ; X64-SSE:       # %bb.0:
-; X64-SSE-NEXT:    subq $24, %rsp
-; X64-SSE-NEXT:    .cfi_def_cfa_offset 32
-; X64-SSE-NEXT:    xorl %esi, %esi
-; X64-SSE-NEXT:    xorl %edx, %edx
-; X64-SSE-NEXT:    xorl %ecx, %ecx
-; X64-SSE-NEXT:    xorl %r8d, %r8d
-; X64-SSE-NEXT:    callq __sync_val_compare_and_swap_16@PLT
-; X64-SSE-NEXT:    movq %rdx, {{[0-9]+}}(%rsp)
-; X64-SSE-NEXT:    movq %rax, (%rsp)
-; X64-SSE-NEXT:    movaps (%rsp), %xmm0
-; X64-SSE-NEXT:    addq $24, %rsp
-; X64-SSE-NEXT:    .cfi_def_cfa_offset 8
+; X64-SSE-NEXT:    movq %xmm0, %rax
+; X64-SSE-NEXT:    xchgq %rax, (%rdi)
+; X64-SSE-NEXT:    movq %rax, %xmm0
 ; X64-SSE-NEXT:    retq
 ;
-; X64-AVX-LABEL: load_fp128:
+; X64-AVX-LABEL: exchange_double:
 ; X64-AVX:       # %bb.0:
-; X64-AVX-NEXT:    subq $24, %rsp
-; X64-AVX-NEXT:    .cfi_def_cfa_offset 32
-; X64-AVX-NEXT:    xorl %esi, %esi
-; X64-AVX-NEXT:    xorl %edx, %edx
-; X64-AVX-NEXT:    xorl %ecx, %ecx
-; X64-AVX-NEXT:    xorl %r8d, %r8d
-; X64-AVX-NEXT:    callq __sync_val_compare_and_swap_16@PLT
-; X64-AVX-NEXT:    movq %rdx, {{[0-9]+}}(%rsp)
-; X64-AVX-NEXT:    movq %rax, (%rsp)
-; X64-AVX-NEXT:    vmovaps (%rsp), %xmm0
-; X64-AVX-NEXT:    addq $24, %rsp
-; X64-AVX-NEXT:    .cfi_def_cfa_offset 8
+; X64-AVX-NEXT:    vmovq %xmm0, %rax
+; X64-AVX-NEXT:    xchgq %rax, (%rdi)
+; X64-AVX-NEXT:    vmovq %rax, %xmm0
 ; X64-AVX-NEXT:    retq
-  %v = load atomic fp128, ptr %fptr unordered, align 16
-  ret fp128 %v
+  %v = atomicrmw xchg ptr %fptr, double %x monotonic, align 8
+  ret double %v
 }
 
 
diff --git a/llvm/test/CodeGen/X86/atomic128.ll b/llvm/test/CodeGen/X86/atomic128.ll
index d5600b54a169..1f7c2254bc79 100644
--- a/llvm/test/CodeGen/X86/atomic128.ll
+++ b/llvm/test/CodeGen/X86/atomic128.ll
@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-apple-macosx10.9 -verify-machineinstrs -mattr=cx16 | FileCheck %s
-; RUN: llc < %s -mtriple=i386-linux-gnu -verify-machineinstrs -mattr=cx16 | FileCheck %s -check-prefixes=CHECK32
-; RUN: llc < %s -mtriple=i386-linux-gnu -verify-machineinstrs -mattr=-cx16 | FileCheck %s -check-prefixes=CHECK32
+
+; Codegen of i128 without cx16 is tested in atomic-nocx16.ll
 
 @var = global i128 0
 
@@ -20,61 +20,6 @@ define i128 @val_compare_and_swap(ptr %p, i128 %oldval, i128 %newval) {
 ; CHECK-NEXT:    lock cmpxchg16b (%rdi)
 ; CHECK-NEXT:    popq %rbx
 ; CHECK-NEXT:    retq
-;
-; CHECK32-LABEL: val_compare_and_swap:
-; CHECK32:       # %bb.0:
-; CHECK32-NEXT:    pushl %edi
-; CHECK32-NEXT:    .cfi_def_cfa_offset 8
-; CHECK32-NEXT:    pushl %esi
-; CHECK32-NEXT:    .cfi_def_cfa_offset 12
-; CHECK32-NEXT:    subl $20, %esp
-; CHECK32-NEXT:    .cfi_def_cfa_offset 32
-; CHECK32-NEXT:    .cfi_offset %esi, -12
-; CHECK32-NEXT:    .cfi_offset %edi, -8
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %esi
-; CHECK32-NEXT:    subl $8, %esp
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 8
-; CHECK32-NEXT:    leal {{[0-9]+}}(%esp), %eax
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl %eax
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    calll __sync_val_compare_and_swap_16
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset -4
-; CHECK32-NEXT:    addl $44, %esp
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset -44
-; CHECK32-NEXT:    movl (%esp), %eax
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %edi
-; CHECK32-NEXT:    movl %edi, 8(%esi)
-; CHECK32-NEXT:    movl %edx, 12(%esi)
-; CHECK32-NEXT:    movl %eax, (%esi)
-; CHECK32-NEXT:    movl %ecx, 4(%esi)
-; CHECK32-NEXT:    movl %esi, %eax
-; CHECK32-NEXT:    addl $20, %esp
-; CHECK32-NEXT:    .cfi_def_cfa_offset 12
-; CHECK32-NEXT:    popl %esi
-; CHECK32-NEXT:    .cfi_def_cfa_offset 8
-; CHECK32-NEXT:    popl %edi
-; CHECK32-NEXT:    .cfi_def_cfa_offset 4
-; CHECK32-NEXT:    retl $4
   %pair = cmpxchg ptr %p, i128 %oldval, i128 %newval acquire acquire
   %val = extractvalue { i128, i1 } %pair, 0
   ret i128 %val
@@ -94,24 +39,6 @@ define void @cmpxchg16b_global_with_offset() nounwind {
 ; CHECK-NEXT:    lock cmpxchg16b _cmpxchg16b_global+16(%rip)
 ; CHECK-NEXT:    popq %rbx
 ; CHECK-NEXT:    retq
-;
-; CHECK32-LABEL: cmpxchg16b_global_with_offset:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    subl $36, %esp
-; CHECK32-NEXT:    leal {{[0-9]+}}(%esp), %eax
-; CHECK32-NEXT:    pushl $0
-; CHECK32-NEXT:    pushl $0
-; CHECK32-NEXT:    pushl $0
-; CHECK32-NEXT:    pushl $0
-; CHECK32-NEXT:    pushl $0
-; CHECK32-NEXT:    pushl $0
-; CHECK32-NEXT:    pushl $0
-; CHECK32-NEXT:    pushl $0
-; CHECK32-NEXT:    pushl $cmpxchg16b_global+16
-; CHECK32-NEXT:    pushl %eax
-; CHECK32-NEXT:    calll __sync_val_compare_and_swap_16
-; CHECK32-NEXT:    addl $72, %esp
-; CHECK32-NEXT:    retl
 entry:
   %0 = load atomic i128, ptr getelementptr inbounds ({i128, i128}, ptr @cmpxchg16b_global, i64 0, i32 1) acquire, align 16
   ret void
@@ -142,46 +69,6 @@ define void @fetch_and_nand(ptr %p, i128 %bits) {
 ; CHECK-NEXT:    movq %rdx, _var+8(%rip)
 ; CHECK-NEXT:    popq %rbx
 ; CHECK-NEXT:    retq
-;
-; CHECK32-LABEL: fetch_and_nand:
-; CHECK32:       # %bb.0:
-; CHECK32-NEXT:    pushl %esi
-; CHECK32-NEXT:    .cfi_def_cfa_offset 8
-; CHECK32-NEXT:    subl $24, %esp
-; CHECK32-NEXT:    .cfi_def_cfa_offset 32
-; CHECK32-NEXT:    .cfi_offset %esi, -8
-; CHECK32-NEXT:    subl $8, %esp
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 8
-; CHECK32-NEXT:    leal {{[0-9]+}}(%esp), %eax
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl %eax
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    calll __sync_fetch_and_nand_16
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset -4
-; CHECK32-NEXT:    addl $28, %esp
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset -28
-; CHECK32-NEXT:    movl (%esp), %eax
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %esi
-; CHECK32-NEXT:    movl %esi, var+8
-; CHECK32-NEXT:    movl %edx, var+12
-; CHECK32-NEXT:    movl %eax, var
-; CHECK32-NEXT:    movl %ecx, var+4
-; CHECK32-NEXT:    addl $24, %esp
-; CHECK32-NEXT:    .cfi_def_cfa_offset 8
-; CHECK32-NEXT:    popl %esi
-; CHECK32-NEXT:    .cfi_def_cfa_offset 4
-; CHECK32-NEXT:    retl
   %val = atomicrmw nand ptr %p, i128 %bits release
   store i128 %val, ptr @var, align 16
   ret void
@@ -210,46 +97,6 @@ define void @fetch_and_or(ptr %p, i128 %bits) {
 ; CHECK-NEXT:    movq %rdx, _var+8(%rip)
 ; CHECK-NEXT:    popq %rbx
 ; CHECK-NEXT:    retq
-;
-; CHECK32-LABEL: fetch_and_or:
-; CHECK32:       # %bb.0:
-; CHECK32-NEXT:    pushl %esi
-; CHECK32-NEXT:    .cfi_def_cfa_offset 8
-; CHECK32-NEXT:    subl $24, %esp
-; CHECK32-NEXT:    .cfi_def_cfa_offset 32
-; CHECK32-NEXT:    .cfi_offset %esi, -8
-; CHECK32-NEXT:    subl $8, %esp
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 8
-; CHECK32-NEXT:    leal {{[0-9]+}}(%esp), %eax
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl %eax
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    calll __sync_fetch_and_or_16
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset -4
-; CHECK32-NEXT:    addl $28, %esp
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset -28
-; CHECK32-NEXT:    movl (%esp), %eax
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %esi
-; CHECK32-NEXT:    movl %esi, var+8
-; CHECK32-NEXT:    movl %edx, var+12
-; CHECK32-NEXT:    movl %eax, var
-; CHECK32-NEXT:    movl %ecx, var+4
-; CHECK32-NEXT:    addl $24, %esp
-; CHECK32-NEXT:    .cfi_def_cfa_offset 8
-; CHECK32-NEXT:    popl %esi
-; CHECK32-NEXT:    .cfi_def_cfa_offset 4
-; CHECK32-NEXT:    retl
   %val = atomicrmw or ptr %p, i128 %bits seq_cst
   store i128 %val, ptr @var, align 16
   ret void
@@ -278,46 +125,6 @@ define void @fetch_and_add(ptr %p, i128 %bits) {
 ; CHECK-NEXT:    movq %rdx, _var+8(%rip)
 ; CHECK-NEXT:    popq %rbx
 ; CHECK-NEXT:    retq
-;
-; CHECK32-LABEL: fetch_and_add:
-; CHECK32:       # %bb.0:
-; CHECK32-NEXT:    pushl %esi
-; CHECK32-NEXT:    .cfi_def_cfa_offset 8
-; CHECK32-NEXT:    subl $24, %esp
-; CHECK32-NEXT:    .cfi_def_cfa_offset 32
-; CHECK32-NEXT:    .cfi_offset %esi, -8
-; CHECK32-NEXT:    subl $8, %esp
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 8
-; CHECK32-NEXT:    leal {{[0-9]+}}(%esp), %eax
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl %eax
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    calll __sync_fetch_and_add_16
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset -4
-; CHECK32-NEXT:    addl $28, %esp
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset -28
-; CHECK32-NEXT:    movl (%esp), %eax
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %esi
-; CHECK32-NEXT:    movl %esi, var+8
-; CHECK32-NEXT:    movl %edx, var+12
-; CHECK32-NEXT:    movl %eax, var
-; CHECK32-NEXT:    movl %ecx, var+4
-; CHECK32-NEXT:    addl $24, %esp
-; CHECK32-NEXT:    .cfi_def_cfa_offset 8
-; CHECK32-NEXT:    popl %esi
-; CHECK32-NEXT:    .cfi_def_cfa_offset 4
-; CHECK32-NEXT:    retl
   %val = atomicrmw add ptr %p, i128 %bits seq_cst
   store i128 %val, ptr @var, align 16
   ret void
@@ -346,46 +153,6 @@ define void @fetch_and_sub(ptr %p, i128 %bits) {
 ; CHECK-NEXT:    movq %rdx, _var+8(%rip)
 ; CHECK-NEXT:    popq %rbx
 ; CHECK-NEXT:    retq
-;
-; CHECK32-LABEL: fetch_and_sub:
-; CHECK32:       # %bb.0:
-; CHECK32-NEXT:    pushl %esi
-; CHECK32-NEXT:    .cfi_def_cfa_offset 8
-; CHECK32-NEXT:    subl $24, %esp
-; CHECK32-NEXT:    .cfi_def_cfa_offset 32
-; CHECK32-NEXT:    .cfi_offset %esi, -8
-; CHECK32-NEXT:    subl $8, %esp
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 8
-; CHECK32-NEXT:    leal {{[0-9]+}}(%esp), %eax
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl %eax
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    calll __sync_fetch_and_sub_16
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset -4
-; CHECK32-NEXT:    addl $28, %esp
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset -28
-; CHECK32-NEXT:    movl (%esp), %eax
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %esi
-; CHECK32-NEXT:    movl %esi, var+8
-; CHECK32-NEXT:    movl %edx, var+12
-; CHECK32-NEXT:    movl %eax, var
-; CHECK32-NEXT:    movl %ecx, var+4
-; CHECK32-NEXT:    addl $24, %esp
-; CHECK32-NEXT:    .cfi_def_cfa_offset 8
-; CHECK32-NEXT:    popl %esi
-; CHECK32-NEXT:    .cfi_def_cfa_offset 4
-; CHECK32-NEXT:    retl
   %val = atomicrmw sub ptr %p, i128 %bits seq_cst
   store i128 %val, ptr @var, align 16
   ret void
@@ -417,46 +184,6 @@ define void @fetch_and_min(ptr %p, i128 %bits) {
 ; CHECK-NEXT:    movq %rdx, _var+8(%rip)
 ; CHECK-NEXT:    popq %rbx
 ; CHECK-NEXT:    retq
-;
-; CHECK32-LABEL: fetch_and_min:
-; CHECK32:       # %bb.0:
-; CHECK32-NEXT:    pushl %esi
-; CHECK32-NEXT:    .cfi_def_cfa_offset 8
-; CHECK32-NEXT:    subl $24, %esp
-; CHECK32-NEXT:    .cfi_def_cfa_offset 32
-; CHECK32-NEXT:    .cfi_offset %esi, -8
-; CHECK32-NEXT:    subl $8, %esp
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 8
-; CHECK32-NEXT:    leal {{[0-9]+}}(%esp), %eax
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl %eax
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    calll __sync_fetch_and_min_16
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset -4
-; CHECK32-NEXT:    addl $28, %esp
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset -28
-; CHECK32-NEXT:    movl (%esp), %eax
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %esi
-; CHECK32-NEXT:    movl %esi, var+8
-; CHECK32-NEXT:    movl %edx, var+12
-; CHECK32-NEXT:    movl %eax, var
-; CHECK32-NEXT:    movl %ecx, var+4
-; CHECK32-NEXT:    addl $24, %esp
-; CHECK32-NEXT:    .cfi_def_cfa_offset 8
-; CHECK32-NEXT:    popl %esi
-; CHECK32-NEXT:    .cfi_def_cfa_offset 4
-; CHECK32-NEXT:    retl
   %val = atomicrmw min ptr %p, i128 %bits seq_cst
   store i128 %val, ptr @var, align 16
   ret void
@@ -488,46 +215,6 @@ define void @fetch_and_max(ptr %p, i128 %bits) {
 ; CHECK-NEXT:    movq %rdx, _var+8(%rip)
 ; CHECK-NEXT:    popq %rbx
 ; CHECK-NEXT:    retq
-;
-; CHECK32-LABEL: fetch_and_max:
-; CHECK32:       # %bb.0:
-; CHECK32-NEXT:    pushl %esi
-; CHECK32-NEXT:    .cfi_def_cfa_offset 8
-; CHECK32-NEXT:    subl $24, %esp
-; CHECK32-NEXT:    .cfi_def_cfa_offset 32
-; CHECK32-NEXT:    .cfi_offset %esi, -8
-; CHECK32-NEXT:    subl $8, %esp
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 8
-; CHECK32-NEXT:    leal {{[0-9]+}}(%esp), %eax
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl %eax
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    calll __sync_fetch_and_max_16
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset -4
-; CHECK32-NEXT:    addl $28, %esp
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset -28
-; CHECK32-NEXT:    movl (%esp), %eax
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %esi
-; CHECK32-NEXT:    movl %esi, var+8
-; CHECK32-NEXT:    movl %edx, var+12
-; CHECK32-NEXT:    movl %eax, var
-; CHECK32-NEXT:    movl %ecx, var+4
-; CHECK32-NEXT:    addl $24, %esp
-; CHECK32-NEXT:    .cfi_def_cfa_offset 8
-; CHECK32-NEXT:    popl %esi
-; CHECK32-NEXT:    .cfi_def_cfa_offset 4
-; CHECK32-NEXT:    retl
   %val = atomicrmw max ptr %p, i128 %bits seq_cst
   store i128 %val, ptr @var, align 16
   ret void
@@ -559,46 +246,6 @@ define void @fetch_and_umin(ptr %p, i128 %bits) {
 ; CHECK-NEXT:    movq %rdx, _var+8(%rip)
 ; CHECK-NEXT:    popq %rbx
 ; CHECK-NEXT:    retq
-;
-; CHECK32-LABEL: fetch_and_umin:
-; CHECK32:       # %bb.0:
-; CHECK32-NEXT:    pushl %esi
-; CHECK32-NEXT:    .cfi_def_cfa_offset 8
-; CHECK32-NEXT:    subl $24, %esp
-; CHECK32-NEXT:    .cfi_def_cfa_offset 32
-; CHECK32-NEXT:    .cfi_offset %esi, -8
-; CHECK32-NEXT:    subl $8, %esp
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 8
-; CHECK32-NEXT:    leal {{[0-9]+}}(%esp), %eax
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl %eax
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    calll __sync_fetch_and_umin_16
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset -4
-; CHECK32-NEXT:    addl $28, %esp
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset -28
-; CHECK32-NEXT:    movl (%esp), %eax
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %esi
-; CHECK32-NEXT:    movl %esi, var+8
-; CHECK32-NEXT:    movl %edx, var+12
-; CHECK32-NEXT:    movl %eax, var
-; CHECK32-NEXT:    movl %ecx, var+4
-; CHECK32-NEXT:    addl $24, %esp
-; CHECK32-NEXT:    .cfi_def_cfa_offset 8
-; CHECK32-NEXT:    popl %esi
-; CHECK32-NEXT:    .cfi_def_cfa_offset 4
-; CHECK32-NEXT:    retl
   %val = atomicrmw umin ptr %p, i128 %bits seq_cst
   store i128 %val, ptr @var, align 16
   ret void
@@ -630,46 +277,6 @@ define void @fetch_and_umax(ptr %p, i128 %bits) {
 ; CHECK-NEXT:    movq %rdx, _var+8(%rip)
 ; CHECK-NEXT:    popq %rbx
 ; CHECK-NEXT:    retq
-;
-; CHECK32-LABEL: fetch_and_umax:
-; CHECK32:       # %bb.0:
-; CHECK32-NEXT:    pushl %esi
-; CHECK32-NEXT:    .cfi_def_cfa_offset 8
-; CHECK32-NEXT:    subl $24, %esp
-; CHECK32-NEXT:    .cfi_def_cfa_offset 32
-; CHECK32-NEXT:    .cfi_offset %esi, -8
-; CHECK32-NEXT:    subl $8, %esp
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 8
-; CHECK32-NEXT:    leal {{[0-9]+}}(%esp), %eax
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl %eax
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    calll __sync_fetch_and_umax_16
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset -4
-; CHECK32-NEXT:    addl $28, %esp
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset -28
-; CHECK32-NEXT:    movl (%esp), %eax
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %esi
-; CHECK32-NEXT:    movl %esi, var+8
-; CHECK32-NEXT:    movl %edx, var+12
-; CHECK32-NEXT:    movl %eax, var
-; CHECK32-NEXT:    movl %ecx, var+4
-; CHECK32-NEXT:    addl $24, %esp
-; CHECK32-NEXT:    .cfi_def_cfa_offset 8
-; CHECK32-NEXT:    popl %esi
-; CHECK32-NEXT:    .cfi_def_cfa_offset 4
-; CHECK32-NEXT:    retl
   %val = atomicrmw umax ptr %p, i128 %bits seq_cst
   store i128 %val, ptr @var, align 16
   ret void
@@ -688,61 +295,6 @@ define i128 @atomic_load_seq_cst(ptr %p) {
 ; CHECK-NEXT:    lock cmpxchg16b (%rdi)
 ; CHECK-NEXT:    popq %rbx
 ; CHECK-NEXT:    retq
-;
-; CHECK32-LABEL: atomic_load_seq_cst:
-; CHECK32:       # %bb.0:
-; CHECK32-NEXT:    pushl %edi
-; CHECK32-NEXT:    .cfi_def_cfa_offset 8
-; CHECK32-NEXT:    pushl %esi
-; CHECK32-NEXT:    .cfi_def_cfa_offset 12
-; CHECK32-NEXT:    subl $20, %esp
-; CHECK32-NEXT:    .cfi_def_cfa_offset 32
-; CHECK32-NEXT:    .cfi_offset %esi, -12
-; CHECK32-NEXT:    .cfi_offset %edi, -8
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %esi
-; CHECK32-NEXT:    subl $8, %esp
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 8
-; CHECK32-NEXT:    leal {{[0-9]+}}(%esp), %eax
-; CHECK32-NEXT:    pushl $0
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl $0
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl $0
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl $0
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl $0
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl $0
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl $0
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl $0
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl %eax
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    calll __sync_val_compare_and_swap_16
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset -4
-; CHECK32-NEXT:    addl $44, %esp
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset -44
-; CHECK32-NEXT:    movl (%esp), %eax
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %edi
-; CHECK32-NEXT:    movl %edi, 8(%esi)
-; CHECK32-NEXT:    movl %edx, 12(%esi)
-; CHECK32-NEXT:    movl %eax, (%esi)
-; CHECK32-NEXT:    movl %ecx, 4(%esi)
-; CHECK32-NEXT:    movl %esi, %eax
-; CHECK32-NEXT:    addl $20, %esp
-; CHECK32-NEXT:    .cfi_def_cfa_offset 12
-; CHECK32-NEXT:    popl %esi
-; CHECK32-NEXT:    .cfi_def_cfa_offset 8
-; CHECK32-NEXT:    popl %edi
-; CHECK32-NEXT:    .cfi_def_cfa_offset 4
-; CHECK32-NEXT:    retl $4
    %r = load atomic i128, ptr %p seq_cst, align 16
    ret i128 %r
 }
@@ -760,61 +312,6 @@ define i128 @atomic_load_relaxed(ptr %p) {
 ; CHECK-NEXT:    lock cmpxchg16b (%rdi)
 ; CHECK-NEXT:    popq %rbx
 ; CHECK-NEXT:    retq
-;
-; CHECK32-LABEL: atomic_load_relaxed:
-; CHECK32:       # %bb.0:
-; CHECK32-NEXT:    pushl %edi
-; CHECK32-NEXT:    .cfi_def_cfa_offset 8
-; CHECK32-NEXT:    pushl %esi
-; CHECK32-NEXT:    .cfi_def_cfa_offset 12
-; CHECK32-NEXT:    subl $20, %esp
-; CHECK32-NEXT:    .cfi_def_cfa_offset 32
-; CHECK32-NEXT:    .cfi_offset %esi, -12
-; CHECK32-NEXT:    .cfi_offset %edi, -8
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %esi
-; CHECK32-NEXT:    subl $8, %esp
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 8
-; CHECK32-NEXT:    leal {{[0-9]+}}(%esp), %eax
-; CHECK32-NEXT:    pushl $0
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl $0
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl $0
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl $0
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl $0
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl $0
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl $0
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl $0
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl %eax
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    calll __sync_val_compare_and_swap_16
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset -4
-; CHECK32-NEXT:    addl $44, %esp
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset -44
-; CHECK32-NEXT:    movl (%esp), %eax
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %edi
-; CHECK32-NEXT:    movl %edi, 8(%esi)
-; CHECK32-NEXT:    movl %edx, 12(%esi)
-; CHECK32-NEXT:    movl %eax, (%esi)
-; CHECK32-NEXT:    movl %ecx, 4(%esi)
-; CHECK32-NEXT:    movl %esi, %eax
-; CHECK32-NEXT:    addl $20, %esp
-; CHECK32-NEXT:    .cfi_def_cfa_offset 12
-; CHECK32-NEXT:    popl %esi
-; CHECK32-NEXT:    .cfi_def_cfa_offset 8
-; CHECK32-NEXT:    popl %edi
-; CHECK32-NEXT:    .cfi_def_cfa_offset 4
-; CHECK32-NEXT:    retl $4
    %r = load atomic i128, ptr %p monotonic, align 16
    ret i128 %r
 }
@@ -837,29 +334,6 @@ define void @atomic_store_seq_cst(ptr %p, i128 %in) {
 ; CHECK-NEXT:  ## %bb.2: ## %atomicrmw.end
 ; CHECK-NEXT:    popq %rbx
 ; CHECK-NEXT:    retq
-;
-; CHECK32-LABEL: atomic_store_seq_cst:
-; CHECK32:       # %bb.0:
-; CHECK32-NEXT:    subl $36, %esp
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 36
-; CHECK32-NEXT:    leal {{[0-9]+}}(%esp), %eax
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl %eax
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    calll __sync_lock_test_and_set_16
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset -4
-; CHECK32-NEXT:    addl $56, %esp
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset -56
-; CHECK32-NEXT:    retl
    store atomic i128 %in, ptr %p seq_cst, align 16
    ret void
 }
@@ -882,29 +356,6 @@ define void @atomic_store_release(ptr %p, i128 %in) {
 ; CHECK-NEXT:  ## %bb.2: ## %atomicrmw.end
 ; CHECK-NEXT:    popq %rbx
 ; CHECK-NEXT:    retq
-;
-; CHECK32-LABEL: atomic_store_release:
-; CHECK32:       # %bb.0:
-; CHECK32-NEXT:    subl $36, %esp
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 36
-; CHECK32-NEXT:    leal {{[0-9]+}}(%esp), %eax
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl %eax
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    calll __sync_lock_test_and_set_16
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset -4
-; CHECK32-NEXT:    addl $56, %esp
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset -56
-; CHECK32-NEXT:    retl
    store atomic i128 %in, ptr %p release, align 16
    ret void
 }
@@ -927,29 +378,6 @@ define void @atomic_store_relaxed(ptr %p, i128 %in) {
 ; CHECK-NEXT:  ## %bb.2: ## %atomicrmw.end
 ; CHECK-NEXT:    popq %rbx
 ; CHECK-NEXT:    retq
-;
-; CHECK32-LABEL: atomic_store_relaxed:
-; CHECK32:       # %bb.0:
-; CHECK32-NEXT:    subl $36, %esp
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 36
-; CHECK32-NEXT:    leal {{[0-9]+}}(%esp), %eax
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl {{[0-9]+}}(%esp)
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    pushl %eax
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset 4
-; CHECK32-NEXT:    calll __sync_lock_test_and_set_16
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset -4
-; CHECK32-NEXT:    addl $56, %esp
-; CHECK32-NEXT:    .cfi_adjust_cfa_offset -56
-; CHECK32-NEXT:    retl
    store atomic i128 %in, ptr %p unordered, align 16
    ret void
 }
diff --git a/llvm/test/CodeGen/X86/atomicf128.ll b/llvm/test/CodeGen/X86/atomicf128.ll
deleted file mode 100644
index 3b0bba403aa5..000000000000
--- a/llvm/test/CodeGen/X86/atomicf128.ll
+++ /dev/null
@@ -1,46 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-apple-macosx10.9 -verify-machineinstrs -mattr=cx16 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-apple-macosx10.9 -verify-machineinstrs -mattr=cx16 -mattr=-sse | FileCheck %s --check-prefix=NOSSE
-
-; FIXME: This test has a fatal error in 32-bit mode
-
-@fsc128 = external global fp128
-
-define void @atomic_fetch_swapf128(fp128 %x) nounwind {
-; CHECK-LABEL: atomic_fetch_swapf128:
-; CHECK:       ## %bb.0:
-; CHECK-NEXT:    pushq %rbx
-; CHECK-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT:    movq -{{[0-9]+}}(%rsp), %rbx
-; CHECK-NEXT:    movq -{{[0-9]+}}(%rsp), %rcx
-; CHECK-NEXT:    movq _fsc128@GOTPCREL(%rip), %rsi
-; CHECK-NEXT:    movq (%rsi), %rax
-; CHECK-NEXT:    movq 8(%rsi), %rdx
-; CHECK-NEXT:    .p2align 4, 0x90
-; CHECK-NEXT:  LBB0_1: ## %atomicrmw.start
-; CHECK-NEXT:    ## =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    lock cmpxchg16b (%rsi)
-; CHECK-NEXT:    jne LBB0_1
-; CHECK-NEXT:  ## %bb.2: ## %atomicrmw.end
-; CHECK-NEXT:    popq %rbx
-; CHECK-NEXT:    retq
-;
-; NOSSE-LABEL: atomic_fetch_swapf128:
-; NOSSE:       ## %bb.0:
-; NOSSE-NEXT:    pushq %rbx
-; NOSSE-NEXT:    movq %rsi, %rcx
-; NOSSE-NEXT:    movq %rdi, %rbx
-; NOSSE-NEXT:    movq _fsc128@GOTPCREL(%rip), %rsi
-; NOSSE-NEXT:    movq (%rsi), %rax
-; NOSSE-NEXT:    movq 8(%rsi), %rdx
-; NOSSE-NEXT:    .p2align 4, 0x90
-; NOSSE-NEXT:  LBB0_1: ## %atomicrmw.start
-; NOSSE-NEXT:    ## =>This Inner Loop Header: Depth=1
-; NOSSE-NEXT:    lock cmpxchg16b (%rsi)
-; NOSSE-NEXT:    jne LBB0_1
-; NOSSE-NEXT:  ## %bb.2: ## %atomicrmw.end
-; NOSSE-NEXT:    popq %rbx
-; NOSSE-NEXT:    retq
-  %t1 = atomicrmw xchg ptr @fsc128, fp128 %x acquire
-  ret void
-}
diff --git a/llvm/test/CodeGen/X86/nocx16.ll b/llvm/test/CodeGen/X86/nocx16.ll
deleted file mode 100644
index ec8e6b2c8c6a..000000000000
--- a/llvm/test/CodeGen/X86/nocx16.ll
+++ /dev/null
@@ -1,21 +0,0 @@
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=corei7 -mattr=-cx16 | FileCheck %s
-define void @test(ptr %a) nounwind {
-entry:
-; CHECK: __sync_val_compare_and_swap_16
-  %0 = cmpxchg ptr %a, i128 1, i128 1 seq_cst seq_cst
-; CHECK: __sync_lock_test_and_set_16
-  %1 = atomicrmw xchg ptr %a, i128 1 seq_cst
-; CHECK: __sync_fetch_and_add_16
-  %2 = atomicrmw add ptr %a, i128 1 seq_cst
-; CHECK: __sync_fetch_and_sub_16
-  %3 = atomicrmw sub ptr %a, i128 1 seq_cst
-; CHECK: __sync_fetch_and_and_16
-  %4 = atomicrmw and ptr %a, i128 1 seq_cst
-; CHECK: __sync_fetch_and_nand_16
-  %5 = atomicrmw nand ptr %a, i128 1 seq_cst
-; CHECK: __sync_fetch_and_or_16
-  %6 = atomicrmw or ptr %a, i128 1 seq_cst
-; CHECK: __sync_fetch_and_xor_16
-  %7 = atomicrmw xor ptr %a, i128 1 seq_cst
-  ret void
-}
-- 
GitLab


From a16429365c400e4364dd9278d3e8a84c1d341704 Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu@google.com>
Date: Sat, 9 Dec 2023 18:23:06 -0800
Subject: [PATCH 042/349] [Transforms] Remove unnecessary includes (NFC)

---
 llvm/include/llvm/Transforms/IPO/BlockExtractor.h             | 1 -
 llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp       | 1 -
 llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp        | 1 -
 llvm/lib/Transforms/Scalar/ConstraintElimination.cpp          | 2 --
 llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp | 1 -
 llvm/lib/Transforms/Scalar/SCCP.cpp                           | 1 -
 llvm/lib/Transforms/Utils/LowerSwitch.cpp                     | 1 -
 llvm/lib/Transforms/Utils/SimplifyCFG.cpp                     | 1 -
 llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp         | 1 -
 9 files changed, 10 deletions(-)

diff --git a/llvm/include/llvm/Transforms/IPO/BlockExtractor.h b/llvm/include/llvm/Transforms/IPO/BlockExtractor.h
index 6211027bd672..cf6b1666b4fc 100644
--- a/llvm/include/llvm/Transforms/IPO/BlockExtractor.h
+++ b/llvm/include/llvm/Transforms/IPO/BlockExtractor.h
@@ -16,7 +16,6 @@
 
 #include <vector>
 
-#include "llvm/ADT/SmallVector.h"
 #include "llvm/IR/PassManager.h"
 
 namespace llvm {
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
index e42e011bd436..91642e3babce 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
@@ -23,7 +23,6 @@
 #include "llvm/Analysis/VectorUtils.h"
 #include "llvm/IR/ConstantRange.h"
 #include "llvm/IR/DataLayout.h"
-#include "llvm/IR/GetElementPtrTypeIterator.h"
 #include "llvm/IR/IntrinsicInst.h"
 #include "llvm/IR/PatternMatch.h"
 #include "llvm/Support/KnownBits.h"
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp b/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp
index 513b185c83a4..afa0bc716aa0 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp
@@ -43,7 +43,6 @@
 #include <cassert>
 #include <cstdint>
 #include <functional>
-#include <tuple>
 #include <type_traits>
 #include <utility>
 
diff --git a/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp b/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
index a6fbddca5cba..43d9883fcfd4 100644
--- a/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+++ b/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
@@ -26,7 +26,6 @@
 #include "llvm/IR/DataLayout.h"
 #include "llvm/IR/Dominators.h"
 #include "llvm/IR/Function.h"
-#include "llvm/IR/GetElementPtrTypeIterator.h"
 #include "llvm/IR/IRBuilder.h"
 #include "llvm/IR/InstrTypes.h"
 #include "llvm/IR/Instructions.h"
@@ -36,7 +35,6 @@
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/DebugCounter.h"
-#include "llvm/Support/KnownBits.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Transforms/Utils/Cloning.h"
 #include "llvm/Transforms/Utils/ValueMapper.h"
diff --git a/llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp b/llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp
index 5f82af1ca46d..9df28747570c 100644
--- a/llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp
+++ b/llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp
@@ -89,7 +89,6 @@
 #include <algorithm>
 #include <cassert>
 #include <iterator>
-#include <limits>
 #include <optional>
 #include <utility>
 
diff --git a/llvm/lib/Transforms/Scalar/SCCP.cpp b/llvm/lib/Transforms/Scalar/SCCP.cpp
index 69679b608f8d..8a491e74b91c 100644
--- a/llvm/lib/Transforms/Scalar/SCCP.cpp
+++ b/llvm/lib/Transforms/Scalar/SCCP.cpp
@@ -46,7 +46,6 @@
 #include "llvm/Transforms/Scalar.h"
 #include "llvm/Transforms/Utils/Local.h"
 #include "llvm/Transforms/Utils/SCCPSolver.h"
-#include <cassert>
 #include <utility>
 
 using namespace llvm;
diff --git a/llvm/lib/Transforms/Utils/LowerSwitch.cpp b/llvm/lib/Transforms/Utils/LowerSwitch.cpp
index 227de425ff85..d1cdab7599c4 100644
--- a/llvm/lib/Transforms/Utils/LowerSwitch.cpp
+++ b/llvm/lib/Transforms/Utils/LowerSwitch.cpp
@@ -42,7 +42,6 @@
 #include <cassert>
 #include <cstdint>
 #include <iterator>
-#include <limits>
 #include <vector>
 
 using namespace llvm;
diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index c09cf9c2325c..89494a7f6497 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -15,7 +15,6 @@
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/MapVector.h"
 #include "llvm/ADT/STLExtras.h"
-#include "llvm/ADT/ScopeExit.h"
 #include "llvm/ADT/Sequence.h"
 #include "llvm/ADT/SetOperations.h"
 #include "llvm/ADT/SetVector.h"
diff --git a/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp b/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
index c0dbd52acbab..fa2459d1ca02 100644
--- a/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
@@ -108,7 +108,6 @@
 #include <cstdint>
 #include <cstdlib>
 #include <iterator>
-#include <limits>
 #include <numeric>
 #include <optional>
 #include <tuple>
-- 
GitLab


From b85f1f9b182234ba366d78ae2174a149e44d08c1 Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu@google.com>
Date: Sat, 9 Dec 2023 18:34:57 -0800
Subject: [PATCH 043/349] [Target] Include bitset (NFC)

These files are relying on the transitive include of <bitset> from
GIMatchTableExecutor.h, which doesn't actually use std::bitset.
---
 llvm/lib/Target/ARM/ARMSubtarget.h     | 1 +
 llvm/lib/Target/RISCV/RISCVSubtarget.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h
index aa8bea103dd6..43b4123a1b55 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -32,6 +32,7 @@
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/TargetParser/Triple.h"
+#include <bitset>
 #include <memory>
 #include <string>
 
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 52f00f1f0990..40720826b90b 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -25,6 +25,7 @@
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/Target/TargetMachine.h"
+#include <bitset>
 
 #define GET_SUBTARGETINFO_HEADER
 #include "RISCVGenSubtargetInfo.inc"
-- 
GitLab


From 2f69dc21876669a8252a0773001ba73781085ac7 Mon Sep 17 00:00:00 2001
From: Fangrui Song <i@maskray.me>
Date: Sat, 9 Dec 2023 22:19:07 -0800
Subject: [PATCH 044/349] [docs] Add missing quotation mark after #73774

---
 llvm/docs/GettingStarted.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/docs/GettingStarted.rst b/llvm/docs/GettingStarted.rst
index 24ed7118ee81..da9cc8aea6d3 100644
--- a/llvm/docs/GettingStarted.rst
+++ b/llvm/docs/GettingStarted.rst
@@ -43,7 +43,7 @@ Getting the Source Code and Building LLVM
    * You are likely only interested in the main branch moving forward, if
      you don't want `git fetch` (or `git pull`) to download user branches, use:
 
-     ``sed 's#fetch = +refs/heads/\*:refs/remotes/origin/\*#fetch = +refs/heads/main:refs/remotes/origin/main# -i llvm-project/.git/config``
+     ``sed 's#fetch = +refs/heads/\*:refs/remotes/origin/\*#fetch = +refs/heads/main:refs/remotes/origin/main#' -i llvm-project/.git/config``
 
 #. Configure and build LLVM and Clang:
 
-- 
GitLab


From a3a346c2037f4547985d4c2e199e65a25aa42d55 Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu@google.com>
Date: Sun, 10 Dec 2023 00:09:07 -0800
Subject: [PATCH 045/349] [llvm] Adjust inlucdes of ArrayRef.h (NFC)

Without this patch, CallingConvLower.h is relying on the transitive
include of ArrayRef.h in TypeSize.h, which doesn't need ArrayRef.h.
---
 llvm/include/llvm/CodeGen/CallingConvLower.h | 1 +
 llvm/include/llvm/Support/TypeSize.h         | 1 -
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/include/llvm/CodeGen/CallingConvLower.h b/llvm/include/llvm/CodeGen/CallingConvLower.h
index 0989fae54b3a..932a2a94ab1f 100644
--- a/llvm/include/llvm/CodeGen/CallingConvLower.h
+++ b/llvm/include/llvm/CodeGen/CallingConvLower.h
@@ -14,6 +14,7 @@
 #ifndef LLVM_CODEGEN_CALLINGCONVLOWER_H
 #define LLVM_CODEGEN_CALLINGCONVLOWER_H
 
+#include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/Register.h"
 #include "llvm/CodeGen/TargetCallingConv.h"
diff --git a/llvm/include/llvm/Support/TypeSize.h b/llvm/include/llvm/Support/TypeSize.h
index 4d9d4f400e92..b00ebf9e8c45 100644
--- a/llvm/include/llvm/Support/TypeSize.h
+++ b/llvm/include/llvm/Support/TypeSize.h
@@ -15,7 +15,6 @@
 #ifndef LLVM_SUPPORT_TYPESIZE_H
 #define LLVM_SUPPORT_TYPESIZE_H
 
-#include "llvm/ADT/ArrayRef.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
 
-- 
GitLab


From 073cc40a343bdb87b43a45598c947de52f6f2de5 Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu@google.com>
Date: Sun, 10 Dec 2023 00:17:26 -0800
Subject: [PATCH 046/349] [Support] Remove unnecessary includes (NFC)

---
 llvm/include/llvm/Support/LLVMDriver.h         | 2 --
 llvm/unittests/Support/Chrono.cpp              | 1 -
 llvm/unittests/Support/CommandLineTest.cpp     | 1 -
 llvm/unittests/Support/InstructionCostTest.cpp | 1 -
 llvm/unittests/Support/MemoryTest.cpp          | 1 -
 5 files changed, 6 deletions(-)

diff --git a/llvm/include/llvm/Support/LLVMDriver.h b/llvm/include/llvm/Support/LLVMDriver.h
index 1c68f5070777..0b2e265d50b4 100644
--- a/llvm/include/llvm/Support/LLVMDriver.h
+++ b/llvm/include/llvm/Support/LLVMDriver.h
@@ -9,8 +9,6 @@
 #ifndef LLVM_SUPPORT_LLVMDRIVER_H
 #define LLVM_SUPPORT_LLVMDRIVER_H
 
-#include "llvm/ADT/SmallVector.h"
-
 namespace llvm {
 
 struct ToolContext {
diff --git a/llvm/unittests/Support/Chrono.cpp b/llvm/unittests/Support/Chrono.cpp
index daf8a8a350f0..7dfc5dd2c293 100644
--- a/llvm/unittests/Support/Chrono.cpp
+++ b/llvm/unittests/Support/Chrono.cpp
@@ -7,7 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm/Support/Chrono.h"
-#include "llvm/ADT/SmallVector.h"
 #include "llvm/Support/FormatVariadic.h"
 #include "gtest/gtest.h"
 
diff --git a/llvm/unittests/Support/CommandLineTest.cpp b/llvm/unittests/Support/CommandLineTest.cpp
index a7db564e5fa2..762ac0ea9c36 100644
--- a/llvm/unittests/Support/CommandLineTest.cpp
+++ b/llvm/unittests/Support/CommandLineTest.cpp
@@ -28,7 +28,6 @@
 #include <fstream>
 #include <stdlib.h>
 #include <string>
-#include <tuple>
 
 using namespace llvm;
 using llvm::unittest::TempDir;
diff --git a/llvm/unittests/Support/InstructionCostTest.cpp b/llvm/unittests/Support/InstructionCostTest.cpp
index 2f634110bd51..4e2842d8ada9 100644
--- a/llvm/unittests/Support/InstructionCostTest.cpp
+++ b/llvm/unittests/Support/InstructionCostTest.cpp
@@ -8,7 +8,6 @@
 
 #include "llvm/Support/InstructionCost.h"
 #include "gtest/gtest.h"
-#include <limits>
 
 using namespace llvm;
 
diff --git a/llvm/unittests/Support/MemoryTest.cpp b/llvm/unittests/Support/MemoryTest.cpp
index 019ece9c1725..0164492829cc 100644
--- a/llvm/unittests/Support/MemoryTest.cpp
+++ b/llvm/unittests/Support/MemoryTest.cpp
@@ -9,7 +9,6 @@
 #include "llvm/Support/Memory.h"
 #include "llvm/Support/Process.h"
 #include "gtest/gtest.h"
-#include <cassert>
 #include <cstdlib>
 
 #if defined(__NetBSD__)
-- 
GitLab


From 95e500808d96bece0edfedb70d9ecdf16c375656 Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu@google.com>
Date: Sun, 10 Dec 2023 00:41:27 -0800
Subject: [PATCH 047/349] [GlobalISel] Add a missing include

---
 llvm/include/llvm/CodeGen/GlobalISel/LegacyLegalizerInfo.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegacyLegalizerInfo.h b/llvm/include/llvm/CodeGen/GlobalISel/LegacyLegalizerInfo.h
index 0b167ce9650d..e423e48fd31e 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegacyLegalizerInfo.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegacyLegalizerInfo.h
@@ -19,6 +19,7 @@
 #include "llvm/CodeGen/LowLevelType.h"
 #include "llvm/CodeGen/TargetOpcodes.h"
 #include <unordered_map>
+#include <vector>
 
 namespace llvm {
 struct LegalityQuery;
-- 
GitLab


From 78623b079b3be841e96ce968ae5156fe26f6c565 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko <atrosinenko@accesssoftek.com>
Date: Sun, 10 Dec 2023 13:25:11 +0300
Subject: [PATCH 048/349] [GISel][TableGen] Fix accidental operand name clashes
 in patterns (#74492)

When importing instruction selection patterns into GlobalISel, the
operands matched in the "source" DAG are copied into corresponding
operands of the "destination" DAG according to their names (such as Rd).
If multiple operands in the source DAG share the same name, a
GIM_CheckIsSameOperand predicate makes instruction selector check the
corresponding operands for equality (at compiler run-time) as part of
matching the source pattern.

The Def operands of the root node of the destination DAG are handled
specially. The operands of the instruction corresponding to the root
node are taken and GIM_CheckRegBankForClass predicates are
tablegen-erated accordingly. If by coincidence the Def operand in
question has the same name as one of the named operands in the pattern,
a GIM_CheckIsSameOperand predicate is automatically added that is likely
to prevent matching the source of otherwise applicable selection pattern
at compiler run-time.

This patch mangles the Def operand names taken from the instruction
corresponding to the root of the destination DAG (for example, "Rd"
becomes "DstI[Rd]") preventing unexpected name clashes with pattern's
named operands.

The patch consists of three sets of changes:
* changes to the GlobalISelEmitter.cpp file are the actual fix
* a test case is added to GlobalISelEmitter.td file as a regression test
* everything else is the biggest and least interesting part - updates to
  the existing test cases: renames of the form Rd -> DstI[Rd] inside the
  inline comments in tablegen-erated code
---
 llvm/test/TableGen/ContextlessPredicates.td   |   2 +-
 llvm/test/TableGen/DefaultOpsGlobalISel.td    |  18 +--
 .../GlobalISelEmitter-input-discard.td        |   2 +-
 ...obalISelEmitter-multiple-output-discard.td |   8 +-
 .../GlobalISelEmitter-multiple-output.td      |  12 +-
 .../GlobalISelEmitter-nested-subregs.td       |   4 +-
 .../GlobalISelEmitter-output-discard.td       |   2 +-
 .../TableGen/GlobalISelEmitter-zero-reg.td    |   4 +-
 llvm/test/TableGen/GlobalISelEmitter.td       | 131 +++++++++++-------
 .../GlobalISelEmitterCustomPredicate.td       |  10 +-
 .../test/TableGen/GlobalISelEmitterHwModes.td |   8 +-
 .../GlobalISelEmitterMatchTableOptimizer.td   |   2 +-
 ...rMatchTableOptimizerSameOperand-invalid.td |   4 +-
 .../TableGen/GlobalISelEmitterRegSequence.td  |   4 +-
 llvm/test/TableGen/GlobalISelEmitterSubreg.td |  16 +--
 llvm/test/TableGen/gisel-physreg-input.td     |   8 +-
 llvm/utils/TableGen/GlobalISelEmitter.cpp     |  56 ++++----
 17 files changed, 163 insertions(+), 128 deletions(-)

diff --git a/llvm/test/TableGen/ContextlessPredicates.td b/llvm/test/TableGen/ContextlessPredicates.td
index 7f081e9a0ec0..0f4c4d0c450e 100644
--- a/llvm/test/TableGen/ContextlessPredicates.td
+++ b/llvm/test/TableGen/ContextlessPredicates.td
@@ -26,7 +26,7 @@ def : Pat<(test_atomic_op_frag GPR32:$ptr, GPR32:$val) ,
 // CHECK_NOPT-NEXT:      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 // CHECK_NOPT-NEXT:      GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ATOMICRMW_XCHG,
 // CHECK_NOPT-NEXT:      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
-// CHECK_NOPT-NEXT:      // MIs[0] dst
+// CHECK_NOPT-NEXT:      // MIs[0] DstI[dst]
 // CHECK_NOPT-NEXT:      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // CHECK_NOPT-NEXT:      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // CHECK_NOPT-NEXT:      // MIs[0] ptr
diff --git a/llvm/test/TableGen/DefaultOpsGlobalISel.td b/llvm/test/TableGen/DefaultOpsGlobalISel.td
index 13ee2631ecb0..c997467c570a 100644
--- a/llvm/test/TableGen/DefaultOpsGlobalISel.td
+++ b/llvm/test/TableGen/DefaultOpsGlobalISel.td
@@ -35,7 +35,7 @@ def clamp : OperandWithDefaultOps <i1, (ops (i1 0))>;
 // CHECK: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_SelectSrcMods,
 // CHECK: GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_SelectSrcMods,
 // CHECK: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FMAX,
-// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // mods0
 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // mods1
@@ -48,7 +48,7 @@ def clamp : OperandWithDefaultOps <i1, (ops (i1 0))>;
 // CHECK: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_SelectClampOMod,
 // CHECK: // (ffloor:{ *:[f32] } (SelectClampOMod:{ *:[f32] } f32:{ *:[f32] }:$src0, omod:{ *:[i32] }:$omod, i1:{ *:[i1] }:$clamp))  =>  (FLOMP:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, omod:{ *:[i32] }:$omod)
 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FLOMP,
-// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // omod
@@ -56,7 +56,7 @@ def clamp : OperandWithDefaultOps <i1, (ops (i1 0))>;
 
 // CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FCANONICALIZE,
 // CHECK: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FMAX,
-// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // mods
 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src
 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // mods
@@ -68,7 +68,7 @@ def clamp : OperandWithDefaultOps <i1, (ops (i1 0))>;
 // CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FCOS,
 // CHECK: // (fcos:{ *:[f32] } (SelectOMod:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$omod))  =>  (FLAMP:{ *:[f32] } FPR32:{ *:[f32] }:$src0, omod:{ *:[i32] }:$omod)
 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FLAMP,
-// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // omod
 // CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/0,
@@ -84,7 +84,7 @@ def clamp : OperandWithDefaultOps <i1, (ops (i1 0))>;
 // CHECK-NEXT: GIR_AddImm, /*InsnID*/1, /*Imm*/0,
 // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FEEPLE,
-// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
@@ -95,7 +95,7 @@ def clamp : OperandWithDefaultOps <i1, (ops (i1 0))>;
 // CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FSIN,
 // CHECK: // (fsin:{ *:[f32] } (SelectClamp:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp))  =>  (FFOO:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp)
 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FFOO,
-// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
 // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
@@ -104,7 +104,7 @@ def clamp : OperandWithDefaultOps <i1, (ops (i1 0))>;
 // CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FSQRT,
 // CHECK: // (fsqrt:{ *:[f32] } (SelectClamp:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp))  =>  (FLAMP:{ *:[f32] } FPR32:{ *:[f32] }:$src0, 93:{ *:[i32] }, clamp:{ *:[i1] }:$clamp)
 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FLAMP,
-// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
 // CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/93,
 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
@@ -113,7 +113,7 @@ def clamp : OperandWithDefaultOps <i1, (ops (i1 0))>;
 // CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC_ROUND,
 // CHECK: // (fround:{ *:[f32] } f32:{ *:[f32] }:$src0)  =>  (FBAR:{ *:[f32] } f32:{ *:[f32] }:$src0)
 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FBAR,
-// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
 // CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/0,
 // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
@@ -121,7 +121,7 @@ def clamp : OperandWithDefaultOps <i1, (ops (i1 0))>;
 // CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC_TRUNC,
 // CHECK: // (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$src0)  =>  (FFOO:{ *:[f32] } FPR32:{ *:[f32] }:$src0)
 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FFOO,
-// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
 // CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/0,
 // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
diff --git a/llvm/test/TableGen/GlobalISelEmitter-input-discard.td b/llvm/test/TableGen/GlobalISelEmitter-input-discard.td
index 6d0d1de5d06c..68a9553a8b73 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-input-discard.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-input-discard.td
@@ -21,7 +21,7 @@ def FOO : I<(outs GPR32:$dst), (ins GPR32Op:$src0, GPR32Op:$src1), []>;
 // GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
 // GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
 // GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FOO,
-// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
 // GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
 // GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0,
diff --git a/llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td b/llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td
index 5f442b067d9c..64cf31f3772e 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td
@@ -22,10 +22,10 @@ def : GINodeEquiv<G_TWO_OUT, two_out>;
 def : Pat<(two_out GPR32:$val), (THREE_OUTS GPR32:$val)>;
 
 // CHECK:      GIM_CheckOpcode, /*MI*/0, MyTarget::G_TWO_OUT,
-// CHECK-NEXT: // MIs[0] out1
+// CHECK-NEXT: // MIs[0] DstI[out1]
 // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
-// CHECK-NEXT: // MIs[0] out2
+// CHECK-NEXT: // MIs[0] DstI[out2]
 // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 // CHECK-NEXT: // MIs[0] val
@@ -34,8 +34,8 @@ def : Pat<(two_out GPR32:$val), (THREE_OUTS GPR32:$val)>;
 // CHECK-NEXT: // (two_out:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$val)  =>  (THREE_OUTS:{ *:[i32] }:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$val)
 // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::THREE_OUTS,
-// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out1
-// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // out2
+// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[out1]
+// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // DstI[out2]
 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
 // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val
 // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
diff --git a/llvm/test/TableGen/GlobalISelEmitter-multiple-output.td b/llvm/test/TableGen/GlobalISelEmitter-multiple-output.td
index c98ac73c61af..85ac3ace0364 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-multiple-output.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-multiple-output.td
@@ -30,10 +30,10 @@ def : Pat<(loadpost (p0 GPR32:$addr), (i32 GPR32:$off)),
 >;
 
 // CHECK:      GIM_CheckOpcode, /*MI*/0, MyTarget::G_POST_LOAD,
-// CHECK-NEXT: // MIs[0] val
+// CHECK-NEXT: // MIs[0] DstI[val]
 // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
-// CHECK-NEXT: // MIs[0] ptr_out
+// CHECK-NEXT: // MIs[0] DstI[ptr_out]
 // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_p0s32,
 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 // CHECK-NEXT: // MIs[0] addr
@@ -64,10 +64,10 @@ def : GINodeEquiv<G_TWO_IN, two_in>;
 def : Pat<(two_in GPR32:$i1, GPR32:$i2), (TWO_INS GPR32:$i2, GPR32:$i1)>;
 
 // CHECK:      GIM_CheckOpcode, /*MI*/0, MyTarget::G_TWO_IN,
-// CHECK-NEXT: // MIs[0] out1
+// CHECK-NEXT: // MIs[0] DstI[out1]
 // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
-// CHECK-NEXT: // MIs[0] out2
+// CHECK-NEXT: // MIs[0] DstI[out2]
 // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 // CHECK-NEXT: // MIs[0] i1
@@ -78,8 +78,8 @@ def : Pat<(two_in GPR32:$i1, GPR32:$i2), (TWO_INS GPR32:$i2, GPR32:$i1)>;
 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/MyTarget::GPR32RegClassID,
 // CHECK-NEXT: // (two_in:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$i1, GPR32:{ *:[i32] }:$i2)  =>  (TWO_INS:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$i2, GPR32:{ *:[i32] }:$i1)
 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::TWO_INS,
-// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out1
-// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // out2
+// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[out1]
+// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // DstI[out2]
 // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // i2
 // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // i1
 // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
diff --git a/llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td b/llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td
index c48c82aa142a..61f79bc04b27 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td
@@ -32,7 +32,7 @@ def A0  : RegisterClass<"MyTarget", [i32], 32, (add a0)>;
 
 // CHECK: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ANYEXT,
-// CHECK-NEXT: // MIs[0] dst
+// CHECK-NEXT: // MIs[0] DstI[dst]
 // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::A0RegClassID,
 // CHECK-NEXT: // MIs[0] src
@@ -52,7 +52,7 @@ def A0  : RegisterClass<"MyTarget", [i32], 32, (add a0)>;
 // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, MyTarget::A0RegClassID,
 // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, MyTarget::A0bRegClassID,
 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
-// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // CHECK-NEXT: GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, MyTarget::lo16,
 // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
 // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, MyTarget::A0wRegClassID,
diff --git a/llvm/test/TableGen/GlobalISelEmitter-output-discard.td b/llvm/test/TableGen/GlobalISelEmitter-output-discard.td
index c755d8377e61..1cfe49dee097 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-output-discard.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-output-discard.td
@@ -15,7 +15,7 @@ def ADD_CO : I<(outs GPR32:$dst, GPR8:$flag),
 // GISEL-NEXT: // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (ADD_CO:{ *:[i32] }:{ *:[i8] } GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1)
 // GISEL-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
 // GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::ADD_CO,
-// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
 // GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
 // GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
diff --git a/llvm/test/TableGen/GlobalISelEmitter-zero-reg.td b/llvm/test/TableGen/GlobalISelEmitter-zero-reg.td
index 374430bc427e..63ad5d5cd03d 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-zero-reg.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-zero-reg.td
@@ -24,7 +24,7 @@ def INST : PredI<(outs GPR32:$dst), (ins GPR32:$src), []>;
 // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LOAD,
 // CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
 // CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
-// CHECK-NEXT: // MIs[0] dst
+// CHECK-NEXT: // MIs[0] DstI[dst]
 // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // CHECK-NEXT: // MIs[0] src
@@ -32,7 +32,7 @@ def INST : PredI<(outs GPR32:$dst), (ins GPR32:$src), []>;
 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 // CHECK-NEXT: // (ld:{ *:[i32] } GPR32:{ *:[i32] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (INST:{ *:[i32] } GPR32:{ *:[i32] }:$src)
 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::INST,
-// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
 // CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, MyTarget::NoRegister, /*AddRegisterRegFlags*/0,
 // CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
diff --git a/llvm/test/TableGen/GlobalISelEmitter.td b/llvm/test/TableGen/GlobalISelEmitter.td
index 176db59a1f41..d1e79604887e 100644
--- a/llvm/test/TableGen/GlobalISelEmitter.td
+++ b/llvm/test/TableGen/GlobalISelEmitter.td
@@ -247,7 +247,7 @@ def HasC : Predicate<"Subtarget->hasC()"> { let RecomputePerFunction = 1; }
 // R19O-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 // R19N-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
 // R19N-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SELECT,
-// R19N-NEXT:    // MIs[0] dst
+// R19N-NEXT:    // MIs[0] DstI[dst]
 // R19N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // R19N-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // R19N-NEXT:    // MIs[0] src1
@@ -290,7 +290,7 @@ def HasC : Predicate<"Subtarget->hasC()"> { let RecomputePerFunction = 1; }
 // R19C-NEXT:    GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/2, /*SubOperand*/1, // src5b
 // R19C-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
 // R19C-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::INSN3,
-// R19C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// R19C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // R19C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
 // R19C-NEXT:    GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src2b
 // R19C-NEXT:    GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src2a
@@ -341,7 +341,7 @@ def : Pat<(select GPR32:$src1, (complex_rr GPR32:$src2a, GPR32:$src2b),
 // R21O-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 // R21N-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
 // R21N-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SELECT,
-// R21N-NEXT:    // MIs[0] dst
+// R21N-NEXT:    // MIs[0] DstI[dst]
 // R21N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // R21N-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // R21N-NEXT:    // MIs[0] src1
@@ -359,7 +359,7 @@ def : Pat<(select GPR32:$src1, (complex_rr GPR32:$src2a, GPR32:$src2b),
 // R21C-NEXT:    // (select:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src2, complex:{ *:[i32] }:$src3)<<P:Predicate_frag>> => (INSN2:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src3, complex:{ *:[i32] }:$src2)
 
 // R21C-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::INSN2,
-// R21C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// R21C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // R21C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
 // R21C-NEXT:    GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/1,
 // R21C-NEXT:    GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0,
@@ -397,7 +397,7 @@ def : Pat<(select GPR32:$src1, (complex_rr GPR32:$src2a, GPR32:$src2b),
 //
 // R20N-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 // R20N-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SUB,
-// R20N-NEXT:    // MIs[0] dst
+// R20N-NEXT:    // MIs[0] DstI[dst]
 // R20N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // R20N-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // R20N-NEXT:    // MIs[0] src1
@@ -410,7 +410,7 @@ def : Pat<(select GPR32:$src1, (complex_rr GPR32:$src2a, GPR32:$src2b),
 // R20C-NEXT:    GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_complex,
 // R20C-NEXT:    // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src2) => (INSN1:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src2)
 // R20C-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::INSN1,
-// R20C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// R20C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // R20C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
 // R20C-NEXT:    GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0,
 // R20C-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
@@ -462,7 +462,7 @@ def : Pat<(frag GPR32:$src1, complex:$src2, complex:$src3),
 // R00C-NEXT:    GIM_CheckFeatures, GIFBS_HasA,
 // R00N-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 // R00N-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SUB,
-// R00N-NEXT:    // MIs[0] dst
+// R00N-NEXT:    // MIs[0] DstI[dst]
 // R00N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // R00N-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // R00N-NEXT:    // MIs[0] Operand 1
@@ -501,7 +501,7 @@ def : Pat<(frag GPR32:$src1, complex:$src2, complex:$src3),
 // R00C-NEXT:    GIM_CheckIsSafeToFold, /*InsnID*/2,
 // R00C-NEXT:    // (sub:{ *:[i32] } (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2), (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src3, GPR32:{ *:[i32] }:$src4)) => (INSNBOB:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src3, GPR32:{ *:[i32] }:$src4)
 // R00C-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::INSNBOB,
-// R00C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// R00C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // R00C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
 // R00C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
 // R00C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src3
@@ -517,7 +517,7 @@ def : Pat<(frag GPR32:$src1, complex:$src2, complex:$src3),
 // R00O-NEXT:  GIM_Reject,
 // R00O:       // Label [[DEFAULT_NUM]]: @[[DEFAULT]]
 // R00O-NEXT:  GIM_Reject,
-// R00O-NEXT:  }; // Size: 9784 bytes
+// R00O-NEXT:  }; // Size: 9880 bytes
 
 def INSNBOB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3, GPR32:$src4),
                  [(set GPR32:$dst,
@@ -544,7 +544,7 @@ def INSNBOB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3, G
 // R01O-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 //
 // R01N-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
-// R01N-NEXT:    // MIs[0] dst
+// R01N-NEXT:    // MIs[0] DstI[dst]
 // R01N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // R01N-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // R01N-NEXT:    // MIs[0] Operand 1
@@ -555,7 +555,7 @@ def INSNBOB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3, G
 // R01C-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
 // R01C-NEXT:    // (intrinsic_wo_chain:{ *:[i32] } [[ID:[0-9]+]]:{ *:[iPTR] }, GPR32:{ *:[i32] }:$src1) => (MOV:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
 // R01C-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOV,
-// R01C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// R01C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // R01C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
 // R01C-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 // R01C-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
@@ -591,7 +591,7 @@ def MOV : I<(outs GPR32:$dst), (ins GPR32:$src1),
 //
 // R02N-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 // R02N-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_XOR,
-// R02N-NEXT:    // MIs[0] dst
+// R02N-NEXT:    // MIs[0] DstI[dst]
 // R02N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // R02N-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // R02N-NEXT:    // MIs[0] src1
@@ -603,7 +603,7 @@ def MOV : I<(outs GPR32:$dst), (ins GPR32:$src1),
 // R02C-NEXT:    GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -2
 // R02C-NEXT:    // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -2:{ *:[i32] }) => (XORI:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
 // R02C-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::XORI,
-// R02C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// R02C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // R02C-NEXT:    GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
 // R02C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
 // R02C-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
@@ -624,7 +624,7 @@ def XORI : I<(outs GPR32:$dst), (ins m1:$src2, GPR32:$src1),
 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_XOR,
-// NOOPT-NEXT:    // MIs[0] dst
+// NOOPT-NEXT:    // MIs[0] DstI[dst]
 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // NOOPT-NEXT:    // MIs[0] src1
@@ -635,7 +635,7 @@ def XORI : I<(outs GPR32:$dst), (ins m1:$src2, GPR32:$src1),
 // NOOPT-NEXT:    GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -3
 // NOOPT-NEXT:    // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -3:{ *:[i32] }) => (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::XOR,
-// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // NOOPT-NEXT:    GIR_AddRegister, /*InsnID*/0, MyTarget::R0,
 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
@@ -653,7 +653,7 @@ def XOR : I<(outs GPR32:$dst), (ins Z:$src2, GPR32:$src1),
 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_XOR,
-// NOOPT-NEXT:    // MIs[0] dst
+// NOOPT-NEXT:    // MIs[0] DstI[dst]
 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // NOOPT-NEXT:    // MIs[0] src1
@@ -664,7 +664,7 @@ def XOR : I<(outs GPR32:$dst), (ins Z:$src2, GPR32:$src1),
 // NOOPT-NEXT:    GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -4
 // NOOPT-NEXT:    // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -4:{ *:[i32] }) => (XORlike:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::XORlike,
-// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // NOOPT-NEXT:    GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
 // NOOPT-NEXT:    GIR_AddRegister, /*InsnID*/0, MyTarget::R0,
 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
@@ -683,7 +683,7 @@ def XORlike : I<(outs GPR32:$dst), (ins m1Z:$src2, GPR32:$src1),
 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_XOR,
-// NOOPT-NEXT:    // MIs[0] dst
+// NOOPT-NEXT:    // MIs[0] DstI[dst]
 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // NOOPT-NEXT:    // MIs[0] src1
@@ -694,7 +694,7 @@ def XORlike : I<(outs GPR32:$dst), (ins m1Z:$src2, GPR32:$src1),
 // NOOPT-NEXT:    GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -5,
 // NOOPT-NEXT:    // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -5:{ *:[i32] }) => (XORManyDefaults:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::XORManyDefaults,
-// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // NOOPT-NEXT:    GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
 // NOOPT-NEXT:    GIR_AddRegister, /*InsnID*/0, MyTarget::R0,
 // NOOPT-NEXT:    GIR_AddRegister, /*InsnID*/0, MyTarget::R0,
@@ -717,7 +717,7 @@ def XORManyDefaults : I<(outs GPR32:$dst), (ins m1Z:$src3, Z:$src2, GPR32:$src1)
 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_XOR,
-// NOOPT-NEXT:    // MIs[0] dst
+// NOOPT-NEXT:    // MIs[0] DstI[dst]
 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // NOOPT-NEXT:    // MIs[0] Wm
@@ -728,7 +728,7 @@ def XORManyDefaults : I<(outs GPR32:$dst), (ins m1Z:$src3, Z:$src2, GPR32:$src1)
 // NOOPT-NEXT:    GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
 // NOOPT-NEXT:    // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Wm, -1:{ *:[i32] }) => (ORN:{ *:[i32] } R0:{ *:[i32] }, GPR32:{ *:[i32] }:$Wm)
 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::ORN,
-// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // NOOPT-NEXT:    GIR_AddRegister, /*InsnID*/0, MyTarget::R0,
 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Wm
 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
@@ -746,7 +746,7 @@ def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>;
 // NOOPT-NEXT:    GIM_CheckFeatures, GIFBS_HasA,
 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL,
-// NOOPT-NEXT:    // MIs[0] dst
+// NOOPT-NEXT:    // MIs[0] DstI[dst]
 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // NOOPT-NEXT:    // MIs[0] Operand 1
@@ -768,7 +768,7 @@ def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>;
 // NOOPT-NEXT:    GIM_CheckIsSafeToFold, /*InsnID*/1,
 // NOOPT-NEXT:    // (mul:{ *:[i32] } (add:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2), GPR32:{ *:[i32] }:$src3)  =>  (MULADD:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src3)
 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MULADD,
-// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src3
@@ -784,7 +784,7 @@ def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>;
 // NOOPT-NEXT:    GIM_CheckFeatures, GIFBS_HasA,
 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL,
-// NOOPT-NEXT:    // MIs[0] dst
+// NOOPT-NEXT:    // MIs[0] DstI[dst]
 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // NOOPT-NEXT:    // MIs[0] src3
@@ -806,13 +806,13 @@ def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>;
 // NOOPT-NEXT:    GIM_CheckIsSafeToFold, /*InsnID*/1,
 // NOOPT-NEXT:    // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src3, (add:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2))  =>  (MULADD:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src3)
 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MULADD,
-// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src3
 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
-// NOOPT-NEXT:    // GIR_Coverage, 26,
+// NOOPT-NEXT:    // GIR_Coverage, 27,
 // NOOPT-NEXT:    GIR_Done,
 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 
@@ -826,14 +826,14 @@ def MULADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3),
 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_CONSTANT,
-// NOOPT-NEXT:    // MIs[0] dst
+// NOOPT-NEXT:    // MIs[0] DstI[dst]
 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // NOOPT-NEXT:    // MIs[0] Operand 1
 // NOOPT-NEXT:    GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, 1,
 // NOOPT-NEXT:    // 1:{ *:[i32] }  =>  (MOV1:{ *:[i32] })
 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOV1,
-// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 // NOOPT-NEXT:    // GIR_Coverage, 7,
@@ -848,14 +848,14 @@ def MOV1 : I<(outs GPR32:$dst), (ins), [(set GPR32:$dst, 1)]>;
 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_CONSTANT,
 // NOOPT-NEXT:    GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GICXXPred_I64_Predicate_simm8,
-// NOOPT-NEXT:    // MIs[0] dst
+// NOOPT-NEXT:    // MIs[0] DstI[dst]
 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // NOOPT-NEXT:    // MIs[0] Operand 1
 // NOOPT-NEXT:    // No operand predicates
 // NOOPT-NEXT:    // (imm:{ *:[i32] })<<P:Predicate_simm8>>:$imm => (MOVimm8:{ *:[i32] } (imm:{ *:[i32] }):$imm)
 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOVimm8,
-// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // NOOPT-NEXT:    GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
@@ -872,14 +872,14 @@ def MOVimm8 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, simm8:$i
 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_CONSTANT,
 // NOOPT-NEXT:    GIM_CheckAPIntImmPredicate, /*MI*/0, /*Predicate*/GICXXPred_APInt_Predicate_simm9,
-// NOOPT-NEXT:    // MIs[0] dst
+// NOOPT-NEXT:    // MIs[0] DstI[dst]
 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // NOOPT-NEXT:    // MIs[0] Operand 1
 // NOOPT-NEXT:    // No operand predicates
 // NOOPT-NEXT:    // (imm:{ *:[i32] })<<P:Predicate_simm9>>:$imm =>  (MOVimm9:{ *:[i32] } (imm:{ *:[i32] }):$imm)
 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOVimm9,
-// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // NOOPT-NEXT:    GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
@@ -896,14 +896,14 @@ def MOVimm9 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, simm9:$i
 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_CONSTANT,
 // NOOPT-NEXT:    GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GICXXPred_I64_Predicate_cimm8,
-// NOOPT-NEXT:    // MIs[0] dst
+// NOOPT-NEXT:    // MIs[0] DstI[dst]
 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // NOOPT-NEXT:    // MIs[0] Operand 1
 // NOOPT-NEXT:    // No operand predicates
 // NOOPT-NEXT:    // (imm:{ *:[i32] })<<P:Predicate_cimm8>><<X:cimm8_xform>>:$imm  =>  (MOVcimm8:{ *:[i32] } (cimm8_xform:{ *:[i32] } (imm:{ *:[i32] }):$imm))
 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOVcimm8,
-// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // NOOPT-NEXT:    GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GICR_renderImm, // imm
 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
@@ -919,14 +919,14 @@ def MOVcimm8 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, cimm8:$
 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FCONSTANT,
 // NOOPT-NEXT:    GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GICXXPred_APFloat_Predicate_fpimmz,
-// NOOPT-NEXT:    // MIs[0] dst
+// NOOPT-NEXT:    // MIs[0] DstI[dst]
 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::FPR32RegClassID,
 // NOOPT-NEXT:    // MIs[0] Operand 1
 // NOOPT-NEXT:    // No operand predicates
 // NOOPT-NEXT:    // (fpimm:{ *:[f32] })<<P:Predicate_fpimmz>>:$imm =>  (MOVfpimmz:{ *:[f32] } (fpimm:{ *:[f32] }):$imm)
 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOVfpimmz,
-// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // NOOPT-NEXT:    GIR_CopyFConstantAsFPImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
@@ -941,7 +941,7 @@ def MOVcimm8 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, cimm8:$
 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LOAD,
 // NOOPT-NEXT:    GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
 // NOOPT-NEXT:    GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
-// NOOPT-NEXT:    // MIs[0] dst
+// NOOPT-NEXT:    // MIs[0] DstI[dst]
 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // NOOPT-NEXT:    // MIs[0] src1
@@ -964,7 +964,7 @@ def LOAD : I<(outs GPR32:$dst), (ins GPR32:$src1),
 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LOAD,
 // NOOPT-NEXT:    GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
 // NOOPT-NEXT:    GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
-// NOOPT-NEXT:    // MIs[0] dst
+// NOOPT-NEXT:    // MIs[0] DstI[dst]
 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_p0s32,
 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // NOOPT-NEXT:    // MIs[0] src
@@ -987,7 +987,7 @@ def : Pat<(load GPR32:$src),
 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SEXTLOAD,
 // NOOPT-NEXT:    GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
 // NOOPT-NEXT:    GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
-// NOOPT-NEXT:    // MIs[0] dst
+// NOOPT-NEXT:    // MIs[0] DstI[dst]
 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // NOOPT-NEXT:    // MIs[0] src1
@@ -1008,7 +1008,7 @@ def SEXTLOAD : I<(outs GPR32:$dst), (ins GPR32:$src1),
 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD,
-// NOOPT-NEXT:    // MIs[0] dst
+// NOOPT-NEXT:    // MIs[0] DstI[dst]
 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // NOOPT-NEXT:    // MIs[0] src1
@@ -1032,7 +1032,7 @@ def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2),
 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD,
-// NOOPT-NEXT:    // MIs[0] dst
+// NOOPT-NEXT:    // MIs[0] DstI[dst]
 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // NOOPT-NEXT:    // MIs[0] src{{$}}
@@ -1042,7 +1042,7 @@ def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2),
 // NOOPT-NEXT:    GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
 // NOOPT-NEXT:    // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src) => (DOUBLE:{ *:[i32] } GPR32:{ *:[i32] }:$src)
 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::DOUBLE,
-// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
@@ -1052,12 +1052,41 @@ def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2),
 
 def DOUBLE : I<(outs GPR32:$dst), (ins GPR32:$src), [(set GPR32:$dst, (add GPR32:$src, GPR32:$src))]>;
 
+//===- Test a pattern with unintended operand name clash. ----------------===//
+
+// Check that using the same name for
+// - Def operand of the instruction corresponding to the root node of the
+//   pattern's destination
+// - one of operands in the pattern itself
+// does not introduce unexpected GIM_CheckIsSameOperand predicate.
+
+// NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
+// NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
+// NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD,
+// NOOPT-NEXT:    // MIs[0] DstI[samename]
+// NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+// NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
+// NOOPT-NEXT:    // MIs[0] samename
+// NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+// NOOPT-NEXT:    // MIs[0] othername
+// NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+// NOOPT-NEXT:    // (add:{ *:[i32] } i32:{ *:[i32] }:$samename, i32:{ *:[i32] }:$othername)  =>  (InsnWithSpeciallyNamedDef:{ *:[i32] } i32:{ *:[i32] }:$samename, i32:{ *:[i32] }:$othername)
+// NOOPT-NEXT:    GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::InsnWithSpeciallyNamedDef,
+// NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+// NOOPT-NEXT:    // GIR_Coverage, 24,
+// NOOPT-NEXT:    GIR_Done,
+// NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
+
+def InsnWithSpeciallyNamedDef : I<(outs GPR32:$samename), (ins GPR32:$src1, GPR32:$src2), []>;
+def : Pat<(add i32:$samename, i32:$othername),
+          (InsnWithSpeciallyNamedDef i32:$samename, i32:$othername)>;
+
 //===- Test a simple pattern with ValueType operands. ----------------------===//
 //
 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD,
-// NOOPT-NEXT:    // MIs[0] dst
+// NOOPT-NEXT:    // MIs[0] DstI[dst]
 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // NOOPT-NEXT:    // MIs[0] src1
@@ -1067,7 +1096,7 @@ def DOUBLE : I<(outs GPR32:$dst), (ins GPR32:$src), [(set GPR32:$dst, (add GPR32
 // NOOPT-NEXT:    // (add:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) => (ADD:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
 // NOOPT-NEXT:    GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::ADD,
 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
-// NOOPT-NEXT:    // GIR_Coverage, 24,
+// NOOPT-NEXT:    // GIR_Coverage, 25,
 // NOOPT-NEXT:    GIR_Done,
 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 
@@ -1080,7 +1109,7 @@ def : Pat<(add i32:$src1, i32:$src2),
 // NOOPT-NEXT:    GIM_CheckFeatures, GIFBS_HasA_HasB_HasC,
 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL,
-// NOOPT-NEXT:    // MIs[0] dst
+// NOOPT-NEXT:    // MIs[0] DstI[dst]
 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // NOOPT-NEXT:    // MIs[0] src1
@@ -1091,7 +1120,7 @@ def : Pat<(add i32:$src1, i32:$src2),
 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
 // NOOPT-NEXT:    // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) => (MUL:{ *:[i32] } GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src1)
 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MUL,
-// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
@@ -1110,7 +1139,7 @@ def MUL : I<(outs GPR32:$dst), (ins GPR32:$src2, GPR32:$src1),
 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_BITCAST,
-// NOOPT-NEXT:    // MIs[0] dst
+// NOOPT-NEXT:    // MIs[0] DstI[dst]
 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // NOOPT-NEXT:    // MIs[0] src1
@@ -1119,7 +1148,7 @@ def MUL : I<(outs GPR32:$dst), (ins GPR32:$src2, GPR32:$src1),
 // NOOPT-NEXT:    // (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$src1) => (COPY_TO_REGCLASS:{ *:[i32] } FPR32:{ *:[f32] }:$src1, GPR32:{ *:[i32] })
 // NOOPT-NEXT:    GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
 // NOOPT-NEXT:    GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, MyTarget::GPR32RegClassID,
-// NOOPT-NEXT:    // GIR_Coverage, 25,
+// NOOPT-NEXT:    // GIR_Coverage, 26,
 // NOOPT-NEXT:    GIR_Done,
 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 
@@ -1131,14 +1160,14 @@ def : Pat<(i32 (bitconvert FPR32:$src1)),
 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_CONSTANT,
-// NOOPT-NEXT:    // MIs[0] dst
+// NOOPT-NEXT:    // MIs[0] DstI[dst]
 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // NOOPT-NEXT:    // MIs[0] Operand 1
 // NOOPT-NEXT:    // No operand predicates
 // NOOPT-NEXT:    // (imm:{ *:[i32] }):$imm =>  (MOVimm:{ *:[i32] } (imm:{ *:[i32] }):$imm)
 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOVimm,
-// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // NOOPT-NEXT:    GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
@@ -1169,5 +1198,5 @@ def BR : I<(outs), (ins unknown:$target),
             [(br bb:$target)]>;
 
 // NOOPT-NEXT:    GIM_Reject,
-// NOOPT-NEXT:  }; // Size: 11160 bytes
+// NOOPT-NEXT:  }; // Size: 11408 bytes
 // NOOPT-NEXT:  return MatchTable0;
diff --git a/llvm/test/TableGen/GlobalISelEmitterCustomPredicate.td b/llvm/test/TableGen/GlobalISelEmitterCustomPredicate.td
index d07ef4e300ee..5a75cb129eec 100644
--- a/llvm/test/TableGen/GlobalISelEmitterCustomPredicate.td
+++ b/llvm/test/TableGen/GlobalISelEmitterCustomPredicate.td
@@ -76,7 +76,7 @@ def and_or_pat : PatFrag<
 // CHECK: GIM_Try, /*On fail goto*//*Label 0*/ 99, // Rule ID 7 //
 // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_AND,
-// CHECK-NEXT: // MIs[0] dst
+// CHECK-NEXT: // MIs[0] DstI[dst]
 // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Test::DRegsRegClassID,
 // CHECK-NEXT: // MIs[0] src2
@@ -106,7 +106,7 @@ def and_or_pat : PatFrag<
 // CHECK: GIM_Try, /*On fail goto*//*Label 1*/ 198, // Rule ID 3 //
 // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_AND,
-// CHECK-NEXT: // MIs[0] dst
+// CHECK-NEXT: // MIs[0] DstI[dst]
 // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Test::DRegsRegClassID,
 // CHECK-NEXT: // MIs[0] Operand 1
@@ -151,7 +151,7 @@ def mul_pat : PatFrag<
 // CHECK: GIM_Try, /*On fail goto*//*Label 2*/ 293, // Rule ID 4 //
 // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL,
-// CHECK-NEXT: // MIs[0] dst
+// CHECK-NEXT: // MIs[0] DstI[dst]
 // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Test::DRegsRegClassID,
 // CHECK-NEXT: // MIs[0] Operand 1
@@ -180,7 +180,7 @@ def mul_pat : PatFrag<
 // CHECK: GIM_Try, /*On fail goto*//*Label 3*/ 388, // Rule ID 8 //
 // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL,
-// CHECK-NEXT: // MIs[0] dst
+// CHECK-NEXT: // MIs[0] DstI[dst]
 // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Test::DRegsRegClassID,
 // CHECK-NEXT: // MIs[0] src2
@@ -226,7 +226,7 @@ def sub3_pat : PatFrag<
 // CHECK: GIM_Try, /*On fail goto*//*Label 4*/ 475, // Rule ID 0 //
 // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SUB,
-// CHECK-NEXT: // MIs[0] dst
+// CHECK-NEXT: // MIs[0] DstI[dst]
 // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Test::DRegsRegClassID,
 // CHECK-NEXT: // MIs[0] Operand 1
diff --git a/llvm/test/TableGen/GlobalISelEmitterHwModes.td b/llvm/test/TableGen/GlobalISelEmitterHwModes.td
index b185feaf009f..04f33648313b 100644
--- a/llvm/test/TableGen/GlobalISelEmitterHwModes.td
+++ b/llvm/test/TableGen/GlobalISelEmitterHwModes.td
@@ -133,7 +133,7 @@ class I<dag OOps, dag IOps, list<dag> Pat>
 // CHECK-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LOAD,
 // CHECK-NEXT:    GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
 // CHECK-NEXT:    GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
-// CHECK-NEXT:    // MIs[0] dst
+// CHECK-NEXT:    // MIs[0] DstI[dst]
 // CHECK-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
 // CHECK-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPRRegClassID,
 // CHECK-NEXT:    // MIs[0] src1
@@ -151,7 +151,7 @@ class I<dag OOps, dag IOps, list<dag> Pat>
 // CHECK-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LOAD,
 // CHECK-NEXT:    GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
 // CHECK-NEXT:    GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
-// CHECK-NEXT:    // MIs[0] dst
+// CHECK-NEXT:    // MIs[0] DstI[dst]
 // CHECK-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // CHECK-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPRRegClassID,
 // CHECK-NEXT:    // MIs[0] src1
@@ -175,7 +175,7 @@ def LOAD : I<(outs GPR:$dst), (ins GPR:$src1),
 // CHECK-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LOAD,
 // CHECK-NEXT:    GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
 // CHECK-NEXT:    GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
-// CHECK-NEXT:    // MIs[0] dst
+// CHECK-NEXT:    // MIs[0] DstI[dst]
 // CHECK-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_p0s64,
 // CHECK-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPRRegClassID,
 // CHECK-NEXT:    // MIs[0] src
@@ -193,7 +193,7 @@ def LOAD : I<(outs GPR:$dst), (ins GPR:$src1),
 // CHECK-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LOAD,
 // CHECK-NEXT:    GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
 // CHECK-NEXT:    GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
-// CHECK-NEXT:    // MIs[0] dst
+// CHECK-NEXT:    // MIs[0] DstI[dst]
 // CHECK-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_p0s32,
 // CHECK-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPRRegClassID,
 // CHECK-NEXT:    // MIs[0] src
diff --git a/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizer.td b/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizer.td
index cd7a177b8426..6a369b6a7b88 100644
--- a/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizer.td
+++ b/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizer.td
@@ -61,7 +61,7 @@ def LOAD16Imm : I<(outs GPR16:$dst), (ins GPR16:$src), []>;
 // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1,
 // CHECK-NEXT: // (ld:{ *:[i16] } (add:{ *:[i16] } GPR16:{ *:[i16] }:$src, 10:{ *:[i16] }))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LOAD16Imm:{ *:[i16] } GPR16:{ *:[i16] }:$src)
 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::LOAD16Imm,
-// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
 // CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
 // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
diff --git a/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td b/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td
index 44e1b08bdd82..2423c3bd32d5 100644
--- a/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td
+++ b/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td
@@ -33,7 +33,7 @@ def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32:
 // CHECK-NEXT:          GIM_CheckIsSafeToFold, /*InsnID*/2,
 // CHECK-NEXT:          // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$cond, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2), GPR32:{ *:[i32] }:$src2)  =>  (InstThreeOperands:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2)
 // CHECK-NEXT:          GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::InstThreeOperands,
-// CHECK-NEXT:          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT:          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // CHECK-NEXT:          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // cond
 // CHECK-NEXT:          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
 // CHECK-NEXT:          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
@@ -61,7 +61,7 @@ def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32:
 // CHECK-NEXT:          GIM_CheckIsSafeToFold, /*InsnID*/2,
 // CHECK-NEXT:          // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$cond, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2), GPR32:{ *:[i32] }:$src2)  =>  (InstThreeOperands:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2)
 // CHECK-NEXT:          GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::InstThreeOperands,
-// CHECK-NEXT:          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT:          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // CHECK-NEXT:          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // cond
 // CHECK-NEXT:          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
 // CHECK-NEXT:          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
diff --git a/llvm/test/TableGen/GlobalISelEmitterRegSequence.td b/llvm/test/TableGen/GlobalISelEmitterRegSequence.td
index 1b7391497f12..34783e688399 100644
--- a/llvm/test/TableGen/GlobalISelEmitterRegSequence.td
+++ b/llvm/test/TableGen/GlobalISelEmitterRegSequence.td
@@ -32,7 +32,7 @@ def SUBSOME_INSN : I<(outs SRegs:$dst), (ins SOP:$src), []>;
 
 // CHECK: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SEXT,
-// CHECK-NEXT: // MIs[0] dst
+// CHECK-NEXT: // MIs[0] DstI[dst]
 // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Test::DRegsRegClassID,
 // CHECK-NEXT: // MIs[0] src
@@ -50,7 +50,7 @@ def SUBSOME_INSN : I<(outs SRegs:$dst), (ins SOP:$src), []>;
 // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
 // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
-// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
 // CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1,
 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
diff --git a/llvm/test/TableGen/GlobalISelEmitterSubreg.td b/llvm/test/TableGen/GlobalISelEmitterSubreg.td
index c8405735aaea..af3db1590368 100644
--- a/llvm/test/TableGen/GlobalISelEmitterSubreg.td
+++ b/llvm/test/TableGen/GlobalISelEmitterSubreg.td
@@ -72,7 +72,7 @@ def : Pat<(sub (complex DOP:$src1, DOP:$src2), 77),
 // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, Test::SRegsRegClassID,
 // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, Test::DRegsRegClassID,
 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::SOME_INSN2,
-// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
 // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
@@ -87,7 +87,7 @@ def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SOP:$src
 // CHECK-NEXT:            GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
 // CHECK-NEXT:            GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
 // CHECK-NEXT:            GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
-// CHECK-NEXT:            GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT:            GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // CHECK-NEXT:            GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
 // CHECK-NEXT:            GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
 // CHECK-NEXT:            GIR_AddImm, /*InsnID*/0, /*Imm*/1,
@@ -115,7 +115,7 @@ def : Pat<(i32 (anyext i16:$src)), (SOME_INSN (INSERT_SUBREG (i32 (IMPLICIT_DEF)
 // CHECK-NEXT:            GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, Test::DRegsRegClassID,
 // CHECK-NEXT:            GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, Test::SRegsRegClassID,
 // CHECK-NEXT:            GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::SOME_INSN,
-// CHECK-NEXT:            GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT:            GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // CHECK-NEXT:            GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
 // CHECK-NEXT:            GIR_EraseFromParent, /*InsnID*/0,
 // CHECK-NEXT:            GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
@@ -145,7 +145,7 @@ def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (IMPLICIT_DEF)), (SUBSOME
 // CHECK-NEXT:          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
 // CHECK-NEXT:          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
 // CHECK-NEXT:          GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
-// CHECK-NEXT:          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT:          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // CHECK-NEXT:          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
 // CHECK-NEXT:          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
 // CHECK-NEXT:          GIR_AddImm, /*InsnID*/0, /*Imm*/1,
@@ -182,7 +182,7 @@ def : Pat<(i16 (trunc (bitreverse DOP:$src))),
 // CHECK-NEXT:  GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src
 // CHECK-NEXT:  GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
 // CHECK-NEXT:  GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
-// CHECK-NEXT:  GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT:  GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // CHECK-NEXT:  GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, sub0,
 // CHECK-NEXT:  GIR_EraseFromParent, /*InsnID*/0,
 // CHECK-NEXT:  GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Test::SRegsRegClassID,
@@ -207,7 +207,7 @@ def : Pat<(i16 (trunc (bitreverse DOP:$src))),
 // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, Test::SRegsRegClassID,
 // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, Test::DRegsRegClassID,
 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::SUBSOME_INSN2,
-// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
 // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
 // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
@@ -219,7 +219,7 @@ def : Pat<(i16 (trunc DOP:$src)),
            (EXTRACT_SUBREG DOP:$src, sub0)>;
 // CHECK-LABEL: // (trunc:{ *:[i16] } DOP:{ *:[i32] }:$src)  =>  (EXTRACT_SUBREG:{ *:[i16] } DOP:{ *:[i32] }:$src, sub0:{ *:[i32] })
 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
-// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // CHECK-NEXT: GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/1, // src
 // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
 // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Test::SRegsRegClassID,
@@ -236,7 +236,7 @@ def : Pat<(i32 (zext SOP:$src)),
 // CHECK-NEXT:        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
 // CHECK-NEXT:        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
 // CHECK-NEXT:        GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
-// CHECK-NEXT:        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT:        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // CHECK-NEXT:        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
 // CHECK-NEXT:        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
 // CHECK-NEXT:        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
diff --git a/llvm/test/TableGen/gisel-physreg-input.td b/llvm/test/TableGen/gisel-physreg-input.td
index e700141c203e..3dbd57bc45b7 100644
--- a/llvm/test/TableGen/gisel-physreg-input.td
+++ b/llvm/test/TableGen/gisel-physreg-input.td
@@ -27,7 +27,7 @@ class I<dag OOps, dag IOps, list<dag> Pat>
 // GISEL: GIM_Try,
 // GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 // GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD,
-// GISEL-NEXT: // MIs[0] dst
+// GISEL-NEXT: // MIs[0] DstI[dst]
 // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // GISEL-NEXT: // MIs[0] src0
@@ -41,7 +41,7 @@ class I<dag OOps, dag IOps, list<dag> Pat>
 // GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, MyTarget::SPECIAL, /*AddRegisterRegFlags*/RegState::Define,
 // GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // SPECIAL
 // GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::ADD_PHYS,
-// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
 // GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0,
 // GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
@@ -55,7 +55,7 @@ def ADD_PHYS : I<(outs GPR32:$dst), (ins GPR32:$src0),
 // GISEL: GIM_Try,
 // GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 // GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL,
-// GISEL-NEXT: // MIs[0] dst
+// GISEL-NEXT: // MIs[0] DstI[dst]
 // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // GISEL-NEXT: // MIs[0] SPECIAL
@@ -69,7 +69,7 @@ def ADD_PHYS : I<(outs GPR32:$dst), (ins GPR32:$src0),
 // GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, MyTarget::SPECIAL, /*AddRegisterRegFlags*/RegState::Define,
 // GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // SPECIAL
 // GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MUL_PHYS,
-// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // SPECIAL
 // GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0,
 // GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index 8d9ded1b2ac5..f1b2ff68e343 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -282,6 +282,10 @@ static std::string getScopedName(unsigned Scope, const std::string &Name) {
   return ("pred:" + Twine(Scope) + ":" + Name).str();
 }
 
+static std::string getMangledRootDefName(StringRef DefOperandName) {
+  return ("DstI[" + DefOperandName + "]").str();
+}
+
 //===- GlobalISelEmitter class --------------------------------------------===//
 
 static Expected<LLTCodeGen> getInstResultType(const TreePatternNode *Dst) {
@@ -1499,8 +1503,13 @@ Expected<action_iterator> GlobalISelEmitter::importExplicitDefRenderers(
   if (DstNumDefs == 0)
     return InsertPt;
 
-  for (unsigned I = 0; I < SrcNumDefs; ++I)
-    DstMIBuilder.addRenderer<CopyRenderer>(DstI->Operands[I].Name);
+  for (unsigned I = 0; I < SrcNumDefs; ++I) {
+    std::string OpName = getMangledRootDefName(DstI->Operands[I].Name);
+    // CopyRenderer saves a StringRef, so cannot pass OpName itself -
+    // let's use a string with an appropriate lifetime.
+    StringRef PermanentRef = M.getOperandMatcher(OpName).getSymbolicName();
+    DstMIBuilder.addRenderer<CopyRenderer>(PermanentRef);
+  }
 
   // Some instructions have multiple defs, but are missing a type entry
   // (e.g. s_cc_out operands).
@@ -2013,16 +2022,17 @@ Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
     const TypeSetByHwMode &VTy = Src->getExtType(I);
 
     const auto &DstIOperand = DstI.Operands[OpIdx];
-    Record *DstIOpRec = DstIOperand.Rec;
+    PointerUnion<Record *, const CodeGenRegisterClass *> MatchedRC =
+        DstIOperand.Rec;
     if (DstIName == "COPY_TO_REGCLASS") {
-      DstIOpRec = getInitValueAsRegClass(Dst->getChild(1)->getLeafValue());
+      MatchedRC = getInitValueAsRegClass(Dst->getChild(1)->getLeafValue());
 
-      if (DstIOpRec == nullptr)
+      if (MatchedRC.isNull())
         return failedImport(
             "COPY_TO_REGCLASS operand #1 isn't a register class");
     } else if (DstIName == "REG_SEQUENCE") {
-      DstIOpRec = getInitValueAsRegClass(Dst->getChild(0)->getLeafValue());
-      if (DstIOpRec == nullptr)
+      MatchedRC = getInitValueAsRegClass(Dst->getChild(0)->getLeafValue());
+      if (MatchedRC.isNull())
         return failedImport("REG_SEQUENCE operand #0 isn't a register class");
     } else if (DstIName == "EXTRACT_SUBREG") {
       auto InferredClass = inferRegClassFromPattern(Dst->getChild(0));
@@ -2032,7 +2042,7 @@ Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
 
       // We can assume that a subregister is in the same bank as it's super
       // register.
-      DstIOpRec = (*InferredClass)->getDef();
+      MatchedRC = (*InferredClass)->getDef();
     } else if (DstIName == "INSERT_SUBREG") {
       auto MaybeSuperClass = inferSuperRegisterClassForNode(
           VTy, Dst->getChild(0), Dst->getChild(2));
@@ -2042,34 +2052,30 @@ Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
       // Move to the next pattern here, because the register class we found
       // doesn't necessarily have a record associated with it. So, we can't
       // set DstIOpRec using this.
-      OperandMatcher &OM = InsnMatcher.getOperand(OpIdx);
-      OM.setSymbolicName(DstIOperand.Name);
-      M.defineOperand(OM.getSymbolicName(), OM);
-      OM.addPredicate<RegisterBankOperandMatcher>(**MaybeSuperClass);
-      ++OpIdx;
-      continue;
+      MatchedRC = *MaybeSuperClass;
     } else if (DstIName == "SUBREG_TO_REG") {
       auto MaybeRegClass = inferSuperRegisterClass(VTy, Dst->getChild(2));
       if (!MaybeRegClass)
         return failedImport(
             "Cannot infer register class for SUBREG_TO_REG operand #0");
-      OperandMatcher &OM = InsnMatcher.getOperand(OpIdx);
-      OM.setSymbolicName(DstIOperand.Name);
-      M.defineOperand(OM.getSymbolicName(), OM);
-      OM.addPredicate<RegisterBankOperandMatcher>(**MaybeRegClass);
-      ++OpIdx;
-      continue;
-    } else if (DstIOpRec->isSubClassOf("RegisterOperand"))
-      DstIOpRec = DstIOpRec->getValueAsDef("RegClass");
-    else if (!DstIOpRec->isSubClassOf("RegisterClass"))
+      MatchedRC = *MaybeRegClass;
+    } else if (MatchedRC.get<Record *>()->isSubClassOf("RegisterOperand"))
+      MatchedRC = MatchedRC.get<Record *>()->getValueAsDef("RegClass");
+    else if (!MatchedRC.get<Record *>()->isSubClassOf("RegisterClass"))
       return failedImport("Dst MI def isn't a register class" +
                           to_string(*Dst));
 
     OperandMatcher &OM = InsnMatcher.getOperand(OpIdx);
-    OM.setSymbolicName(DstIOperand.Name);
+    // The operand names declared in the DstI instruction are unrelated to
+    // those used in pattern's source and destination DAGs, so mangle the
+    // former to prevent implicitly adding unexpected
+    // GIM_CheckIsSameOperand predicates by the defineOperand method.
+    OM.setSymbolicName(getMangledRootDefName(DstIOperand.Name));
     M.defineOperand(OM.getSymbolicName(), OM);
+    if (MatchedRC.is<Record *>())
+      MatchedRC = &Target.getRegisterClass(MatchedRC.get<Record *>());
     OM.addPredicate<RegisterBankOperandMatcher>(
-        Target.getRegisterClass(DstIOpRec));
+        *MatchedRC.get<const CodeGenRegisterClass *>());
     ++OpIdx;
   }
 
-- 
GitLab


From 67c4033358f39adcba53e9b70bdd4799c5a306ac Mon Sep 17 00:00:00 2001
From: "Stephan T. Lavavej" <stl@nuwen.net>
Date: Sun, 10 Dec 2023 02:52:14 -0800
Subject: [PATCH 049/349] [libc++] LWG-4021 "`mdspan::is_always_meow()` should
 be `noexcept`", use `LIBCPP_STATIC_ASSERT` for `noexcept` strengthening
 (#74254)

Found while running libc++'s test suite with MSVC's STL.

* I've filed [LWG-4021](https://cplusplus.github.io/LWG/issue4021)
"`mdspan::is_always_meow()` should be `noexcept`" and implemented this
in libc++'s product and test code.
* Use `LIBCPP_STATIC_ASSERT` to avoid issues with `noexcept`
strengthening in MSVC's STL.
+ As permitted by the Standard, MSVC's STL conditionally strengthens
`mdspan` construction/`is_meow`/`stride` and `elements_view` iterator
`base() &&`, and always strengthens `basic_stringbuf` `swap`.
+ In `mdspan/properties.pass.cpp`, this also upgrades runtime `assert`s
to `static_assert`s.
* Improvement: Upgrade `assert` to `static_assert` when inspecting the
`noexcept`ness of `std::ranges::iter_move`. (These `!noexcept` tests
weren't causing issues for MSVC's STL, so I didn't change them to be
libc++-specific.)
---
 libcxx/include/__mdspan/mdspan.h              | 11 ++++++--
 libcxx/include/mdspan                         |  7 +++--
 .../mdspan/mdspan/ctor.dh_array.pass.cpp      |  2 +-
 .../mdspan/mdspan/ctor.dh_extents.pass.cpp    |  2 +-
 .../views/mdspan/mdspan/ctor.dh_map.pass.cpp  |  2 +-
 .../mdspan/mdspan/ctor.dh_map_acc.pass.cpp    |  2 +-
 .../views/mdspan/mdspan/ctor.dh_span.pass.cpp |  2 +-
 .../views/mdspan/mdspan/properties.pass.cpp   | 28 ++++++++++---------
 .../member_swap_noexcept.pass.cpp             |  2 +-
 .../nonmember_swap_noexcept.pass.cpp          |  2 +-
 .../iterator.cust.move/iter_move.pass.cpp     |  6 ++--
 .../range.elements/iterator/base.pass.cpp     |  2 +-
 12 files changed, 38 insertions(+), 30 deletions(-)

diff --git a/libcxx/include/__mdspan/mdspan.h b/libcxx/include/__mdspan/mdspan.h
index 58f3b9cf1b18..684828eb90ec 100644
--- a/libcxx/include/__mdspan/mdspan.h
+++ b/libcxx/include/__mdspan/mdspan.h
@@ -244,9 +244,14 @@ public:
   _LIBCPP_HIDE_FROM_ABI constexpr const mapping_type& mapping() const noexcept { return __map_; };
   _LIBCPP_HIDE_FROM_ABI constexpr const accessor_type& accessor() const noexcept { return __acc_; };
 
-  _LIBCPP_HIDE_FROM_ABI static constexpr bool is_always_unique() { return mapping_type::is_always_unique(); };
-  _LIBCPP_HIDE_FROM_ABI static constexpr bool is_always_exhaustive() { return mapping_type::is_always_exhaustive(); };
-  _LIBCPP_HIDE_FROM_ABI static constexpr bool is_always_strided() { return mapping_type::is_always_strided(); };
+  // per LWG-4021 "mdspan::is_always_meow() should be noexcept"
+  _LIBCPP_HIDE_FROM_ABI static constexpr bool is_always_unique() noexcept { return mapping_type::is_always_unique(); };
+  _LIBCPP_HIDE_FROM_ABI static constexpr bool is_always_exhaustive() noexcept {
+    return mapping_type::is_always_exhaustive();
+  };
+  _LIBCPP_HIDE_FROM_ABI static constexpr bool is_always_strided() noexcept {
+    return mapping_type::is_always_strided();
+  };
 
   _LIBCPP_HIDE_FROM_ABI constexpr bool is_unique() const { return __map_.is_unique(); };
   _LIBCPP_HIDE_FROM_ABI constexpr bool is_exhaustive() const { return __map_.is_exhaustive(); };
diff --git a/libcxx/include/mdspan b/libcxx/include/mdspan
index d55cdc4a4df5..c13d9eef001a 100644
--- a/libcxx/include/mdspan
+++ b/libcxx/include/mdspan
@@ -334,11 +334,12 @@ namespace std {
     constexpr const mapping_type& mapping() const noexcept { return map_; }
     constexpr const accessor_type& accessor() const noexcept { return acc_; }
 
-    static constexpr bool is_always_unique()
+    // per LWG-4021 "mdspan::is_always_meow() should be noexcept"
+    static constexpr bool is_always_unique() noexcept
       { return mapping_type::is_always_unique(); }
-    static constexpr bool is_always_exhaustive()
+    static constexpr bool is_always_exhaustive() noexcept
       { return mapping_type::is_always_exhaustive(); }
-    static constexpr bool is_always_strided()
+    static constexpr bool is_always_strided() noexcept
       { return mapping_type::is_always_strided(); }
 
     constexpr bool is_unique() const
diff --git a/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_array.pass.cpp b/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_array.pass.cpp
index bbf8137a7cb8..0e0c7667da30 100644
--- a/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_array.pass.cpp
+++ b/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_array.pass.cpp
@@ -65,7 +65,7 @@ test_mdspan_ctor_array(const H& handle, const M& map, const A&, std::array<typen
     }
   }
 
-  static_assert(!noexcept(MDS(handle, exts)));
+  LIBCPP_STATIC_ASSERT(!noexcept(MDS(handle, exts)));
 
   static_assert(check_mdspan_ctor_implicit<MDS, decltype(exts)> == (N == MDS::rank_dynamic()));
 
diff --git a/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_extents.pass.cpp b/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_extents.pass.cpp
index 0a8918028d13..40e82db98635 100644
--- a/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_extents.pass.cpp
+++ b/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_extents.pass.cpp
@@ -51,7 +51,7 @@ constexpr void test_mdspan_types(const H& handle, const M& map, const A&) {
         assert((H::move_counter() == 1));
       }
     }
-    static_assert(!noexcept(MDS(handle, map.extents())));
+    LIBCPP_STATIC_ASSERT(!noexcept(MDS(handle, map.extents())));
     assert(m.extents() == map.extents());
     if constexpr (std::equality_comparable<H>)
       assert(m.data_handle() == handle);
diff --git a/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_map.pass.cpp b/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_map.pass.cpp
index 75b7722b445e..fa65848ac69b 100644
--- a/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_map.pass.cpp
+++ b/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_map.pass.cpp
@@ -48,7 +48,7 @@ constexpr void test_mdspan_types(const H& handle, const M& map, const A&) {
         assert((H::move_counter() == 1));
       }
     }
-    static_assert(!noexcept(MDS(handle, map)));
+    LIBCPP_STATIC_ASSERT(!noexcept(MDS(handle, map)));
     assert(m.extents() == map.extents());
     if constexpr (std::equality_comparable<H>)
       assert(m.data_handle() == handle);
diff --git a/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_map_acc.pass.cpp b/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_map_acc.pass.cpp
index c2210f1dba90..65d32f3d7a7f 100644
--- a/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_map_acc.pass.cpp
+++ b/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_map_acc.pass.cpp
@@ -43,7 +43,7 @@ constexpr void test_mdspan_types(const H& handle, const M& map, const A& acc) {
       assert((H::move_counter() == 1));
     }
   }
-  static_assert(!noexcept(MDS(handle, map, acc)));
+  LIBCPP_STATIC_ASSERT(!noexcept(MDS(handle, map, acc)));
   assert(m.extents() == map.extents());
   if constexpr (std::equality_comparable<H>)
     assert(m.data_handle() == handle);
diff --git a/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_span.pass.cpp b/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_span.pass.cpp
index 980619795b5d..f4fb5e681d95 100644
--- a/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_span.pass.cpp
+++ b/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_span.pass.cpp
@@ -65,7 +65,7 @@ test_mdspan_ctor_span(const H& handle, const M& map, const A&, std::span<typenam
     }
   }
 
-  static_assert(!noexcept(MDS(handle, exts)));
+  LIBCPP_STATIC_ASSERT(!noexcept(MDS(handle, exts)));
 
   static_assert(check_mdspan_ctor_implicit<MDS, decltype(exts)> == (N == MDS::rank_dynamic()));
 
diff --git a/libcxx/test/std/containers/views/mdspan/mdspan/properties.pass.cpp b/libcxx/test/std/containers/views/mdspan/mdspan/properties.pass.cpp
index 35534fa87954..ba1fef1df677 100644
--- a/libcxx/test/std/containers/views/mdspan/mdspan/properties.pass.cpp
+++ b/libcxx/test/std/containers/views/mdspan/mdspan/properties.pass.cpp
@@ -27,11 +27,12 @@
 //     constexpr const data_handle_type& data_handle() const noexcept { return ptr_; }
 //     constexpr const mapping_type& mapping() const noexcept { return map_; }
 //     constexpr const accessor_type& accessor() const noexcept { return acc_; }
-//     static constexpr bool is_always_unique()
+//     /* per LWG-4021 "mdspan::is_always_meow() should be noexcept" */
+//     static constexpr bool is_always_unique() noexcept
 //       { return mapping_type::is_always_unique(); }
-//     static constexpr bool is_always_exhaustive()
+//     static constexpr bool is_always_exhaustive() noexcept
 //       { return mapping_type::is_always_exhaustive(); }
-//     static constexpr bool is_always_strided()
+//     static constexpr bool is_always_strided() noexcept
 //       { return mapping_type::is_always_strided(); }
 //
 //     constexpr bool is_unique() const
@@ -141,15 +142,16 @@ constexpr void test_mdspan_types(const H& handle, const M& map, const A& acc) {
   ASSERT_SAME_TYPE(decltype(m.is_unique()), bool);
   ASSERT_SAME_TYPE(decltype(m.is_exhaustive()), bool);
   ASSERT_SAME_TYPE(decltype(m.is_strided()), bool);
-  assert(!noexcept(MDS::is_always_unique()));
-  assert(!noexcept(MDS::is_always_exhaustive()));
-  assert(!noexcept(MDS::is_always_strided()));
-  assert(!noexcept(m.is_unique()));
-  assert(!noexcept(m.is_exhaustive()));
-  assert(!noexcept(m.is_strided()));
-  assert(MDS::is_always_unique() == M::is_always_unique());
-  assert(MDS::is_always_exhaustive() == M::is_always_exhaustive());
-  assert(MDS::is_always_strided() == M::is_always_strided());
+  // per LWG-4021 "mdspan::is_always_meow() should be noexcept"
+  static_assert(noexcept(MDS::is_always_unique()));
+  static_assert(noexcept(MDS::is_always_exhaustive()));
+  static_assert(noexcept(MDS::is_always_strided()));
+  LIBCPP_STATIC_ASSERT(!noexcept(m.is_unique()));
+  LIBCPP_STATIC_ASSERT(!noexcept(m.is_exhaustive()));
+  LIBCPP_STATIC_ASSERT(!noexcept(m.is_strided()));
+  static_assert(MDS::is_always_unique() == M::is_always_unique());
+  static_assert(MDS::is_always_exhaustive() == M::is_always_exhaustive());
+  static_assert(MDS::is_always_strided() == M::is_always_strided());
   assert(m.is_unique() == map.is_unique());
   assert(m.is_exhaustive() == map.is_exhaustive());
   assert(m.is_strided() == map.is_strided());
@@ -159,7 +161,7 @@ constexpr void test_mdspan_types(const H& handle, const M& map, const A& acc) {
     if (m.is_strided()) {
       for (typename MDS::rank_type r = 0; r < MDS::rank(); r++) {
         ASSERT_SAME_TYPE(decltype(m.stride(r)), typename MDS::index_type);
-        assert(!noexcept(m.stride(r)));
+        LIBCPP_STATIC_ASSERT(!noexcept(m.stride(r)));
         assert(m.stride(r) == map.stride(r));
       }
     }
diff --git a/libcxx/test/std/input.output/string.streams/stringbuf/stringbuf.assign/member_swap_noexcept.pass.cpp b/libcxx/test/std/input.output/string.streams/stringbuf/stringbuf.assign/member_swap_noexcept.pass.cpp
index 0a0128e44658..63e2293c530b 100644
--- a/libcxx/test/std/input.output/string.streams/stringbuf/stringbuf.assign/member_swap_noexcept.pass.cpp
+++ b/libcxx/test/std/input.output/string.streams/stringbuf/stringbuf.assign/member_swap_noexcept.pass.cpp
@@ -84,7 +84,7 @@ static void test() {
   {
     std::basic_stringbuf<CharT, std::char_traits<CharT>, test_alloc_not_empty<CharT>> buf1;
     std::basic_stringbuf<CharT, std::char_traits<CharT>, test_alloc_not_empty<CharT>> buf;
-    static_assert(!noexcept(buf.swap(buf1)));
+    LIBCPP_STATIC_ASSERT(!noexcept(buf.swap(buf1)));
   }
   {
     std::basic_stringbuf<CharT, std::char_traits<CharT>, test_alloc_propagate_on_container_swap_not_empty<CharT>> buf1;
diff --git a/libcxx/test/std/input.output/string.streams/stringbuf/stringbuf.assign/nonmember_swap_noexcept.pass.cpp b/libcxx/test/std/input.output/string.streams/stringbuf/stringbuf.assign/nonmember_swap_noexcept.pass.cpp
index 4f41e3a4d716..a3706116f409 100644
--- a/libcxx/test/std/input.output/string.streams/stringbuf/stringbuf.assign/nonmember_swap_noexcept.pass.cpp
+++ b/libcxx/test/std/input.output/string.streams/stringbuf/stringbuf.assign/nonmember_swap_noexcept.pass.cpp
@@ -83,7 +83,7 @@ static void test() {
   {
     std::basic_stringbuf<CharT, std::char_traits<CharT>, test_alloc_not_empty<CharT>> buf1;
     std::basic_stringbuf<CharT, std::char_traits<CharT>, test_alloc_not_empty<CharT>> buf;
-    static_assert(!noexcept(swap(buf, buf1)));
+    LIBCPP_STATIC_ASSERT(!noexcept(swap(buf, buf1)));
   }
   {
     std::basic_stringbuf<CharT, std::char_traits<CharT>, test_alloc_propagate_on_container_swap_not_empty<CharT>> buf1;
diff --git a/libcxx/test/std/iterators/iterator.requirements/iterator.cust/iterator.cust.move/iter_move.pass.cpp b/libcxx/test/std/iterators/iterator.requirements/iterator.cust/iterator.cust.move/iter_move.pass.cpp
index 566638263e88..9f293ff483cd 100644
--- a/libcxx/test/std/iterators/iterator.requirements/iterator.cust/iterator.cust.move/iter_move.pass.cpp
+++ b/libcxx/test/std/iterators/iterator.requirements/iterator.cust/iterator.cust.move/iter_move.pass.cpp
@@ -158,15 +158,15 @@ constexpr bool test() {
 
   auto unscoped = check_unqualified_lookup::unscoped_enum::a;
   assert(std::ranges::iter_move(unscoped) == check_unqualified_lookup::unscoped_enum::a);
-  assert(!noexcept(std::ranges::iter_move(unscoped)));
+  static_assert(!noexcept(std::ranges::iter_move(unscoped)));
 
   auto scoped = check_unqualified_lookup::scoped_enum::a;
   assert(std::ranges::iter_move(scoped) == nullptr);
-  assert(noexcept(std::ranges::iter_move(scoped)));
+  static_assert(noexcept(std::ranges::iter_move(scoped)));
 
   auto some_union = check_unqualified_lookup::some_union{0};
   assert(std::ranges::iter_move(some_union) == 0);
-  assert(!noexcept(std::ranges::iter_move(some_union)));
+  static_assert(!noexcept(std::ranges::iter_move(some_union)));
 
   // Check noexcept-correctness
   static_assert(noexcept(std::ranges::iter_move(std::declval<WithADL<true>>())));
diff --git a/libcxx/test/std/ranges/range.adaptors/range.elements/iterator/base.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.elements/iterator/base.pass.cpp
index 3729c8e54311..79c4e1f41837 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.elements/iterator/base.pass.cpp
+++ b/libcxx/test/std/ranges/range.adaptors/range.elements/iterator/base.pass.cpp
@@ -33,7 +33,7 @@ using ElementsIter = std::ranges::iterator_t<std::ranges::elements_view<BaseView
 static_assert(IsBaseNoexcept<const ElementsIter&>);
 static_assert(IsBaseNoexcept<ElementsIter&>);
 static_assert(IsBaseNoexcept<const ElementsIter&&>);
-static_assert(!IsBaseNoexcept<ElementsIter&&>);
+LIBCPP_STATIC_ASSERT(!IsBaseNoexcept<ElementsIter&&>);
 
 constexpr bool test() {
   std::tuple<int> t{5};
-- 
GitLab


From cd6e462d012f289cc4ec12927ca8198f9ed1469e Mon Sep 17 00:00:00 2001
From: paperchalice <liujunchang97@outlook.com>
Date: Sun, 10 Dec 2023 19:15:51 +0800
Subject: [PATCH 050/349] [CodeGen] Port `InterleavedAccess` to new pass
 manager (#74904)

---
 .../include/llvm/CodeGen/CodeGenPassBuilder.h |  1 +
 llvm/include/llvm/CodeGen/InterleavedAccess.h | 34 +++++++
 .../llvm/CodeGen/MachinePassRegistry.def      |  2 +-
 llvm/lib/CodeGen/InterleavedAccessPass.cpp    | 98 ++++++++++++-------
 llvm/lib/Passes/PassBuilder.cpp               |  1 +
 llvm/lib/Passes/PassRegistry.def              |  1 +
 .../AArch64/binopshuffles-inseltpoison.ll     |  1 +
 .../AArch64/binopshuffles.ll                  |  1 +
 .../AArch64/fixed-deinterleave-intrinsics.ll  |  2 +
 ...aved-accesses-extract-user-inseltpoison.ll |  1 +
 .../interleaved-accesses-extract-user.ll      |  1 +
 .../interleaved-accesses-inseltpoison.ll      |  2 +
 .../AArch64/interleaved-accesses.ll           |  2 +
 .../scalable-deinterleave-intrinsics.ll       |  1 +
 .../AArch64/sve-interleaved-accesses.ll       |  1 +
 ...aved-accesses-extract-user-inseltpoison.ll |  1 +
 .../ARM/interleaved-accesses-extract-user.ll  |  1 +
 .../ARM/interleaved-accesses-inseltpoison.ll  |  3 +
 .../ARM/interleaved-accesses.ll               |  3 +
 .../RISCV/interleaved-accesses.ll             |  2 +
 .../InterleavedAccess/RISCV/zve32x.ll         |  2 +
 .../InterleavedAccess/RISCV/zvl32b.ll         |  2 +
 ...interleave-load-extract-shuffle-changes.ll |  1 +
 ...leaved-accesses-64bits-avx-inseltpoison.ll |  1 +
 .../X86/interleaved-accesses-64bits-avx.ll    |  1 +
 .../X86/interleavedLoad-inseltpoison.ll       |  2 +
 .../InterleavedAccess/X86/interleavedLoad.ll  |  2 +
 .../X86/interleavedStore-inseltpoison.ll      |  1 +
 .../InterleavedAccess/X86/interleavedStore.ll |  1 +
 29 files changed, 138 insertions(+), 34 deletions(-)
 create mode 100644 llvm/include/llvm/CodeGen/InterleavedAccess.h

diff --git a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
index 076719abd035..94a2d0c6477b 100644
--- a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
@@ -24,6 +24,7 @@
 #include "llvm/Analysis/TypeBasedAliasAnalysis.h"
 #include "llvm/CodeGen/CallBrPrepare.h"
 #include "llvm/CodeGen/ExpandReductions.h"
+#include "llvm/CodeGen/InterleavedAccess.h"
 #include "llvm/CodeGen/MachinePassManager.h"
 #include "llvm/CodeGen/PreISelIntrinsicLowering.h"
 #include "llvm/CodeGen/ReplaceWithVeclib.h"
diff --git a/llvm/include/llvm/CodeGen/InterleavedAccess.h b/llvm/include/llvm/CodeGen/InterleavedAccess.h
new file mode 100644
index 000000000000..31bd19a3191a
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/InterleavedAccess.h
@@ -0,0 +1,34 @@
+//===---- llvm/CodeGen/InterleavedAccess.h ----------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// This file contains the declaration of the InterleavedAccessPass class,
+/// its corresponding pass name is `interleaved-access`.
+///
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_INTERLEAVEDACCESS_H
+#define LLVM_CODEGEN_INTERLEAVEDACCESS_H
+
+#include "llvm/IR/PassManager.h"
+
+namespace llvm {
+
+class TargetMachine;
+
+class InterleavedAccessPass : public PassInfoMixin<InterleavedAccessPass> {
+  const TargetMachine *TM;
+
+public:
+  explicit InterleavedAccessPass(const TargetMachine *TM) : TM(TM) {}
+  PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM);
+};
+
+} // namespace llvm
+
+#endif // LLVM_CODEGEN_INTERLEAVEDACCESS_H
diff --git a/llvm/include/llvm/CodeGen/MachinePassRegistry.def b/llvm/include/llvm/CodeGen/MachinePassRegistry.def
index 1e9e5838841b..ceca04cd5ba3 100644
--- a/llvm/include/llvm/CodeGen/MachinePassRegistry.def
+++ b/llvm/include/llvm/CodeGen/MachinePassRegistry.def
@@ -43,6 +43,7 @@ FUNCTION_PASS("expand-large-div-rem", ExpandLargeDivRemPass, ())
 FUNCTION_PASS("expand-large-fp-convert", ExpandLargeFpConvertPass, ())
 FUNCTION_PASS("expand-reductions", ExpandReductionsPass, ())
 FUNCTION_PASS("expandvp", ExpandVectorPredicationPass, ())
+FUNCTION_PASS("interleaved-access", InterleavedAccessPass, (TM))
 FUNCTION_PASS("lower-constant-intrinsics", LowerConstantIntrinsicsPass, ())
 FUNCTION_PASS("lowerinvoke", LowerInvokePass, ())
 FUNCTION_PASS("mergeicmps", MergeICmpsPass, ())
@@ -127,7 +128,6 @@ DUMMY_FUNCTION_PASS("expandmemcmp", ExpandMemCmpPass, ())
 DUMMY_FUNCTION_PASS("gc-info-printer", GCInfoPrinterPass, ())
 DUMMY_FUNCTION_PASS("gc-lowering", GCLoweringPass, ())
 DUMMY_FUNCTION_PASS("indirectbr-expand", IndirectBrExpandPass, ())
-DUMMY_FUNCTION_PASS("interleaved-access", InterleavedAccessPass, ())
 DUMMY_FUNCTION_PASS("select-optimize", SelectOptimizePass, ())
 DUMMY_FUNCTION_PASS("shadow-stack-gc-lowering", ShadowStackGCLoweringPass, ())
 DUMMY_FUNCTION_PASS("sjljehprepare", SjLjEHPreparePass, ())
diff --git a/llvm/lib/CodeGen/InterleavedAccessPass.cpp b/llvm/lib/CodeGen/InterleavedAccessPass.cpp
index 65a6859a006a..2a0daf404c97 100644
--- a/llvm/lib/CodeGen/InterleavedAccessPass.cpp
+++ b/llvm/lib/CodeGen/InterleavedAccessPass.cpp
@@ -48,6 +48,7 @@
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/SmallVector.h"
+#include "llvm/CodeGen/InterleavedAccess.h"
 #include "llvm/CodeGen/TargetLowering.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
@@ -82,22 +83,14 @@ static cl::opt<bool> LowerInterleavedAccesses(
 
 namespace {
 
-class InterleavedAccess : public FunctionPass {
-public:
-  static char ID;
-
-  InterleavedAccess() : FunctionPass(ID) {
-    initializeInterleavedAccessPass(*PassRegistry::getPassRegistry());
-  }
+class InterleavedAccessImpl {
+  friend class InterleavedAccess;
 
-  StringRef getPassName() const override { return "Interleaved Access Pass"; }
-
-  bool runOnFunction(Function &F) override;
-
-  void getAnalysisUsage(AnalysisUsage &AU) const override {
-    AU.addRequired<DominatorTreeWrapperPass>();
-    AU.setPreservesCFG();
-  }
+public:
+  InterleavedAccessImpl() = default;
+  InterleavedAccessImpl(DominatorTree *DT, const TargetLowering *TLI)
+      : DT(DT), TLI(TLI), MaxFactor(TLI->getMaxSupportedInterleaveFactor()) {}
+  bool runOnFunction(Function &F);
 
 private:
   DominatorTree *DT = nullptr;
@@ -141,10 +134,60 @@ private:
                             LoadInst *LI);
 };
 
+class InterleavedAccess : public FunctionPass {
+  InterleavedAccessImpl Impl;
+
+public:
+  static char ID;
+
+  InterleavedAccess() : FunctionPass(ID) {
+    initializeInterleavedAccessPass(*PassRegistry::getPassRegistry());
+  }
+
+  StringRef getPassName() const override { return "Interleaved Access Pass"; }
+
+  bool runOnFunction(Function &F) override;
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.addRequired<DominatorTreeWrapperPass>();
+    AU.setPreservesCFG();
+  }
+};
+
 } // end anonymous namespace.
 
+PreservedAnalyses InterleavedAccessPass::run(Function &F,
+                                             FunctionAnalysisManager &FAM) {
+  auto *DT = &FAM.getResult<DominatorTreeAnalysis>(F);
+  auto *TLI = TM->getSubtargetImpl(F)->getTargetLowering();
+  InterleavedAccessImpl Impl(DT, TLI);
+  bool Changed = Impl.runOnFunction(F);
+
+  if (!Changed)
+    return PreservedAnalyses::all();
+
+  PreservedAnalyses PA;
+  PA.preserveSet<CFGAnalyses>();
+  return PA;
+}
+
 char InterleavedAccess::ID = 0;
 
+bool InterleavedAccess::runOnFunction(Function &F) {
+  auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
+  if (!TPC || !LowerInterleavedAccesses)
+    return false;
+
+  LLVM_DEBUG(dbgs() << "*** " << getPassName() << ": " << F.getName() << "\n");
+
+  Impl.DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
+  auto &TM = TPC->getTM<TargetMachine>();
+  Impl.TLI = TM.getSubtargetImpl(F)->getTargetLowering();
+  Impl.MaxFactor = Impl.TLI->getMaxSupportedInterleaveFactor();
+
+  return Impl.runOnFunction(F);
+}
+
 INITIALIZE_PASS_BEGIN(InterleavedAccess, DEBUG_TYPE,
     "Lower interleaved memory accesses to target specific intrinsics", false,
     false)
@@ -228,7 +271,7 @@ static bool isReInterleaveMask(ShuffleVectorInst *SVI, unsigned &Factor,
   return false;
 }
 
-bool InterleavedAccess::lowerInterleavedLoad(
+bool InterleavedAccessImpl::lowerInterleavedLoad(
     LoadInst *LI, SmallVector<Instruction *, 32> &DeadInsts) {
   if (!LI->isSimple() || isa<ScalableVectorType>(LI->getType()))
     return false;
@@ -334,7 +377,7 @@ bool InterleavedAccess::lowerInterleavedLoad(
   return true;
 }
 
-bool InterleavedAccess::replaceBinOpShuffles(
+bool InterleavedAccessImpl::replaceBinOpShuffles(
     ArrayRef<ShuffleVectorInst *> BinOpShuffles,
     SmallVectorImpl<ShuffleVectorInst *> &Shuffles, LoadInst *LI) {
   for (auto *SVI : BinOpShuffles) {
@@ -367,7 +410,7 @@ bool InterleavedAccess::replaceBinOpShuffles(
   return !BinOpShuffles.empty();
 }
 
-bool InterleavedAccess::tryReplaceExtracts(
+bool InterleavedAccessImpl::tryReplaceExtracts(
     ArrayRef<ExtractElementInst *> Extracts,
     ArrayRef<ShuffleVectorInst *> Shuffles) {
   // If there aren't any extractelement instructions to modify, there's nothing
@@ -431,7 +474,7 @@ bool InterleavedAccess::tryReplaceExtracts(
   return true;
 }
 
-bool InterleavedAccess::lowerInterleavedStore(
+bool InterleavedAccessImpl::lowerInterleavedStore(
     StoreInst *SI, SmallVector<Instruction *, 32> &DeadInsts) {
   if (!SI->isSimple())
     return false;
@@ -457,7 +500,7 @@ bool InterleavedAccess::lowerInterleavedStore(
   return true;
 }
 
-bool InterleavedAccess::lowerDeinterleaveIntrinsic(
+bool InterleavedAccessImpl::lowerDeinterleaveIntrinsic(
     IntrinsicInst *DI, SmallVector<Instruction *, 32> &DeadInsts) {
   LoadInst *LI = dyn_cast<LoadInst>(DI->getOperand(0));
 
@@ -476,7 +519,7 @@ bool InterleavedAccess::lowerDeinterleaveIntrinsic(
   return true;
 }
 
-bool InterleavedAccess::lowerInterleaveIntrinsic(
+bool InterleavedAccessImpl::lowerInterleaveIntrinsic(
     IntrinsicInst *II, SmallVector<Instruction *, 32> &DeadInsts) {
   if (!II->hasOneUse())
     return false;
@@ -498,18 +541,7 @@ bool InterleavedAccess::lowerInterleaveIntrinsic(
   return true;
 }
 
-bool InterleavedAccess::runOnFunction(Function &F) {
-  auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
-  if (!TPC || !LowerInterleavedAccesses)
-    return false;
-
-  LLVM_DEBUG(dbgs() << "*** " << getPassName() << ": " << F.getName() << "\n");
-
-  DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
-  auto &TM = TPC->getTM<TargetMachine>();
-  TLI = TM.getSubtargetImpl(F)->getTargetLowering();
-  MaxFactor = TLI->getMaxSupportedInterleaveFactor();
-
+bool InterleavedAccessImpl::runOnFunction(Function &F) {
   // Holds dead instructions that will be erased later.
   SmallVector<Instruction *, 32> DeadInsts;
   bool Changed = false;
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index a5f9b5424358..f26450e94187 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -77,6 +77,7 @@
 #include "llvm/CodeGen/ExpandLargeDivRem.h"
 #include "llvm/CodeGen/ExpandLargeFpConvert.h"
 #include "llvm/CodeGen/HardwareLoops.h"
+#include "llvm/CodeGen/InterleavedAccess.h"
 #include "llvm/CodeGen/SafeStack.h"
 #include "llvm/CodeGen/TypePromotion.h"
 #include "llvm/CodeGen/WasmEHPrepare.h"
diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def
index 7462704ec2df..c1641ea8b5b1 100644
--- a/llvm/lib/Passes/PassRegistry.def
+++ b/llvm/lib/Passes/PassRegistry.def
@@ -318,6 +318,7 @@ FUNCTION_PASS("inject-tli-mappings", InjectTLIMappings())
 FUNCTION_PASS("instcount", InstCountPass())
 FUNCTION_PASS("instnamer", InstructionNamerPass())
 FUNCTION_PASS("instsimplify", InstSimplifyPass())
+FUNCTION_PASS("interleaved-access", InterleavedAccessPass(TM))
 FUNCTION_PASS("invalidate<all>", InvalidateAllAnalysesPass())
 FUNCTION_PASS("irce", IRCEPass())
 FUNCTION_PASS("jump-threading", JumpThreadingPass())
diff --git a/llvm/test/Transforms/InterleavedAccess/AArch64/binopshuffles-inseltpoison.ll b/llvm/test/Transforms/InterleavedAccess/AArch64/binopshuffles-inseltpoison.ll
index dd08172be1b8..22df002dd62c 100644
--- a/llvm/test/Transforms/InterleavedAccess/AArch64/binopshuffles-inseltpoison.ll
+++ b/llvm/test/Transforms/InterleavedAccess/AArch64/binopshuffles-inseltpoison.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -interleaved-access -S | FileCheck %s
+; RUN: opt < %s -passes=interleaved-access -S | FileCheck %s
 
 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64--linux-gnu"
diff --git a/llvm/test/Transforms/InterleavedAccess/AArch64/binopshuffles.ll b/llvm/test/Transforms/InterleavedAccess/AArch64/binopshuffles.ll
index 2e8a7cf42ac5..399fa5298b7c 100644
--- a/llvm/test/Transforms/InterleavedAccess/AArch64/binopshuffles.ll
+++ b/llvm/test/Transforms/InterleavedAccess/AArch64/binopshuffles.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -interleaved-access -S | FileCheck %s
+; RUN: opt < %s -passes=interleaved-access -S | FileCheck %s
 
 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64--linux-gnu"
diff --git a/llvm/test/Transforms/InterleavedAccess/AArch64/fixed-deinterleave-intrinsics.ll b/llvm/test/Transforms/InterleavedAccess/AArch64/fixed-deinterleave-intrinsics.ll
index ab70d623470c..224a0693bf21 100644
--- a/llvm/test/Transforms/InterleavedAccess/AArch64/fixed-deinterleave-intrinsics.ll
+++ b/llvm/test/Transforms/InterleavedAccess/AArch64/fixed-deinterleave-intrinsics.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
 ; RUN: opt < %s -interleaved-access -S | FileCheck %s --check-prefix=NEON
 ; RUN: opt < %s -interleaved-access -mtriple=aarch64-linux-gnu -mattr=+sve -force-streaming-compatible-sve -S | FileCheck %s --check-prefix=SVE-FIXED
+; RUN: opt < %s -passes=interleaved-access -S | FileCheck %s --check-prefix=NEON
+; RUN: opt < %s -passes=interleaved-access -mtriple=aarch64-linux-gnu -mattr=+sve -force-streaming-compatible-sve -S | FileCheck %s --check-prefix=SVE-FIXED
 
 target triple = "aarch64-linux-gnu"
 
diff --git a/llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses-extract-user-inseltpoison.ll b/llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses-extract-user-inseltpoison.ll
index db031ed12b7e..e48dc5d3051b 100644
--- a/llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses-extract-user-inseltpoison.ll
+++ b/llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses-extract-user-inseltpoison.ll
@@ -1,4 +1,5 @@
 ; RUN: opt < %s -interleaved-access -S | FileCheck %s
+; RUN: opt < %s -passes=interleaved-access -S | FileCheck %s
 
 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64--linux-gnu"
diff --git a/llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses-extract-user.ll b/llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses-extract-user.ll
index af472630b951..ea33590cb241 100644
--- a/llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses-extract-user.ll
+++ b/llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses-extract-user.ll
@@ -1,4 +1,5 @@
 ; RUN: opt < %s -interleaved-access -S | FileCheck %s
+; RUN: opt < %s -passes=interleaved-access -S | FileCheck %s
 
 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64--linux-gnu"
diff --git a/llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses-inseltpoison.ll b/llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses-inseltpoison.ll
index 77fbb8e7f2ca..14986d9eb85c 100644
--- a/llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses-inseltpoison.ll
+++ b/llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses-inseltpoison.ll
@@ -1,5 +1,7 @@
 ; RUN: opt < %s -interleaved-access -S | FileCheck %s -check-prefix=NEON
 ; RUN: opt < %s -mattr=-neon -interleaved-access -S | FileCheck %s -check-prefix=NO_NEON
+; RUN: opt < %s -passes=interleaved-access -S | FileCheck %s -check-prefix=NEON
+; RUN: opt < %s -mattr=-neon -passes=interleaved-access -S | FileCheck %s -check-prefix=NO_NEON
 
 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64--linux-gnu"
diff --git a/llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses.ll b/llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses.ll
index 77fbb8e7f2ca..14986d9eb85c 100644
--- a/llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses.ll
+++ b/llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses.ll
@@ -1,5 +1,7 @@
 ; RUN: opt < %s -interleaved-access -S | FileCheck %s -check-prefix=NEON
 ; RUN: opt < %s -mattr=-neon -interleaved-access -S | FileCheck %s -check-prefix=NO_NEON
+; RUN: opt < %s -passes=interleaved-access -S | FileCheck %s -check-prefix=NEON
+; RUN: opt < %s -mattr=-neon -passes=interleaved-access -S | FileCheck %s -check-prefix=NO_NEON
 
 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64--linux-gnu"
diff --git a/llvm/test/Transforms/InterleavedAccess/AArch64/scalable-deinterleave-intrinsics.ll b/llvm/test/Transforms/InterleavedAccess/AArch64/scalable-deinterleave-intrinsics.ll
index c04464b2ca9d..6353bf10d57c 100644
--- a/llvm/test/Transforms/InterleavedAccess/AArch64/scalable-deinterleave-intrinsics.ll
+++ b/llvm/test/Transforms/InterleavedAccess/AArch64/scalable-deinterleave-intrinsics.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
 ; RUN: opt < %s -interleaved-access -S | FileCheck %s
+; RUN: opt < %s -passes=interleaved-access -S | FileCheck %s
 
 target triple = "aarch64-linux-gnu"
 
diff --git a/llvm/test/Transforms/InterleavedAccess/AArch64/sve-interleaved-accesses.ll b/llvm/test/Transforms/InterleavedAccess/AArch64/sve-interleaved-accesses.ll
index 94f63e5921f8..feb22aa1a376 100644
--- a/llvm/test/Transforms/InterleavedAccess/AArch64/sve-interleaved-accesses.ll
+++ b/llvm/test/Transforms/InterleavedAccess/AArch64/sve-interleaved-accesses.ll
@@ -1,4 +1,5 @@
 ; RUN: opt < %s -interleaved-access -S | FileCheck %s
+; RUN: opt < %s -passes=interleaved-access -S | FileCheck %s
 
 target triple = "aarch64-linux-gnu"
 
diff --git a/llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses-extract-user-inseltpoison.ll b/llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses-extract-user-inseltpoison.ll
index 3ea00de0dcb1..77b376b3580c 100644
--- a/llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses-extract-user-inseltpoison.ll
+++ b/llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses-extract-user-inseltpoison.ll
@@ -1,4 +1,5 @@
 ; RUN: opt < %s -mattr=+neon -interleaved-access -S | FileCheck %s
+; RUN: opt < %s -mattr=+neon -passes=interleaved-access -S | FileCheck %s
 
 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64"
 target triple = "arm---eabi"
diff --git a/llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses-extract-user.ll b/llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses-extract-user.ll
index 0c56f71cc369..893494167872 100644
--- a/llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses-extract-user.ll
+++ b/llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses-extract-user.ll
@@ -1,4 +1,5 @@
 ; RUN: opt < %s -mattr=+neon -interleaved-access -S | FileCheck %s
+; RUN: opt < %s -mattr=+neon -passes=interleaved-access -S | FileCheck %s
 
 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64"
 target triple = "arm---eabi"
diff --git a/llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses-inseltpoison.ll b/llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses-inseltpoison.ll
index 9ea1c5e94a98..aed843723189 100644
--- a/llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses-inseltpoison.ll
+++ b/llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses-inseltpoison.ll
@@ -2,6 +2,9 @@
 ; RUN: opt < %s -mattr=+neon -interleaved-access -S | FileCheck %s --check-prefix=CHECK-NEON
 ; RUN: opt < %s -mattr=+mve.fp -interleaved-access -S | FileCheck %s --check-prefix=CHECK-MVE
 ; RUN: opt < %s -interleaved-access -S | FileCheck %s --check-prefix=CHECK-NONE
+; RUN: opt < %s -mattr=+neon -passes=interleaved-access -S | FileCheck %s --check-prefix=CHECK-NEON
+; RUN: opt < %s -mattr=+mve.fp -passes=interleaved-access -S | FileCheck %s --check-prefix=CHECK-MVE
+; RUN: opt < %s -passes=interleaved-access -S | FileCheck %s --check-prefix=CHECK-NONE
 
 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64"
 target triple = "arm---eabi"
diff --git a/llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses.ll b/llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses.ll
index c84d759ae0fb..8123ea5bbe9f 100644
--- a/llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses.ll
+++ b/llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses.ll
@@ -2,6 +2,9 @@
 ; RUN: opt < %s -mattr=+neon -interleaved-access -S | FileCheck %s --check-prefix=CHECK-NEON
 ; RUN: opt < %s -mattr=+mve.fp -interleaved-access -S | FileCheck %s --check-prefix=CHECK-MVE
 ; RUN: opt < %s -interleaved-access -S | FileCheck %s --check-prefix=CHECK-NONE
+; RUN: opt < %s -mattr=+neon -passes=interleaved-access -S | FileCheck %s --check-prefix=CHECK-NEON
+; RUN: opt < %s -mattr=+mve.fp -passes=interleaved-access -S | FileCheck %s --check-prefix=CHECK-MVE
+; RUN: opt < %s -passes=interleaved-access -S | FileCheck %s --check-prefix=CHECK-NONE
 
 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64"
 target triple = "arm---eabi"
diff --git a/llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll b/llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll
index 736a7ce4ecf0..ea2d1ca722ca 100644
--- a/llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll
+++ b/llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -mtriple=riscv32 -mattr=+v -interleaved-access -S | FileCheck %s --check-prefix=RV32
 ; RUN: opt < %s -mtriple=riscv64 -mattr=+v -interleaved-access -S | FileCheck %s --check-prefix=RV64
+; RUN: opt < %s -mtriple=riscv32 -mattr=+v -passes=interleaved-access -S | FileCheck %s --check-prefix=RV32
+; RUN: opt < %s -mtriple=riscv64 -mattr=+v -passes=interleaved-access -S | FileCheck %s --check-prefix=RV64
 
 define void @load_factor2(ptr %ptr) {
 ; RV32-LABEL: @load_factor2(
diff --git a/llvm/test/Transforms/InterleavedAccess/RISCV/zve32x.ll b/llvm/test/Transforms/InterleavedAccess/RISCV/zve32x.ll
index e7b7ec052f45..ac3cab6638b8 100644
--- a/llvm/test/Transforms/InterleavedAccess/RISCV/zve32x.ll
+++ b/llvm/test/Transforms/InterleavedAccess/RISCV/zve32x.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -mtriple=riscv64 -mattr=+zve32x,+zvl128b -interleaved-access -S | FileCheck %s -check-prefix=ZVE32X
 ; RUN: opt < %s -mtriple=riscv64 -mattr=+zve64x,+zvl128b -interleaved-access -S | FileCheck %s -check-prefix=ZVE64X
+; RUN: opt < %s -mtriple=riscv64 -mattr=+zve32x,+zvl128b -passes=interleaved-access -S | FileCheck %s -check-prefix=ZVE32X
+; RUN: opt < %s -mtriple=riscv64 -mattr=+zve64x,+zvl128b -passes=interleaved-access -S | FileCheck %s -check-prefix=ZVE64X
 
 define <4 x i1> @load_large_vector(ptr %p) {
 ; ZVE32X-LABEL: @load_large_vector(
diff --git a/llvm/test/Transforms/InterleavedAccess/RISCV/zvl32b.ll b/llvm/test/Transforms/InterleavedAccess/RISCV/zvl32b.ll
index 9c896796760f..a94e6a70e79e 100644
--- a/llvm/test/Transforms/InterleavedAccess/RISCV/zvl32b.ll
+++ b/llvm/test/Transforms/InterleavedAccess/RISCV/zvl32b.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -mtriple=riscv32 -mattr=+zve32x,+zvl32b -interleaved-access -S | FileCheck %s -check-prefix=ZVL32B
 ; RUN: opt < %s -mtriple=riscv32 -mattr=+zve32x,+zvl128b -interleaved-access -S | FileCheck %s -check-prefix=ZVL128B
+; RUN: opt < %s -mtriple=riscv32 -mattr=+zve32x,+zvl32b -passes=interleaved-access -S | FileCheck %s -check-prefix=ZVL32B
+; RUN: opt < %s -mtriple=riscv32 -mattr=+zve32x,+zvl128b -passes=interleaved-access -S | FileCheck %s -check-prefix=ZVL128B
 
 ; Make sure that we don't lower interleaved loads that won't fit into the minimum vlen
 
diff --git a/llvm/test/Transforms/InterleavedAccess/X86/interleave-load-extract-shuffle-changes.ll b/llvm/test/Transforms/InterleavedAccess/X86/interleave-load-extract-shuffle-changes.ll
index a4b4e3748b46..167d282edb3e 100644
--- a/llvm/test/Transforms/InterleavedAccess/X86/interleave-load-extract-shuffle-changes.ll
+++ b/llvm/test/Transforms/InterleavedAccess/X86/interleave-load-extract-shuffle-changes.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -interleaved-access -S %s | FileCheck %s
+; RUN: opt -passes=interleaved-access -S %s | FileCheck %s
 
 target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.15.0"
diff --git a/llvm/test/Transforms/InterleavedAccess/X86/interleaved-accesses-64bits-avx-inseltpoison.ll b/llvm/test/Transforms/InterleavedAccess/X86/interleaved-accesses-64bits-avx-inseltpoison.ll
index b4128dda7cee..13076c7ffec9 100644
--- a/llvm/test/Transforms/InterleavedAccess/X86/interleaved-accesses-64bits-avx-inseltpoison.ll
+++ b/llvm/test/Transforms/InterleavedAccess/X86/interleaved-accesses-64bits-avx-inseltpoison.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -mtriple=x86_64-pc-linux  -mattr=+avx -interleaved-access -S | FileCheck %s
+; RUN: opt < %s -mtriple=x86_64-pc-linux  -mattr=+avx -passes=interleaved-access -S | FileCheck %s
 
 ; This file tests the function `llvm::lowerInterleavedLoad/Store`.
 
diff --git a/llvm/test/Transforms/InterleavedAccess/X86/interleaved-accesses-64bits-avx.ll b/llvm/test/Transforms/InterleavedAccess/X86/interleaved-accesses-64bits-avx.ll
index ec905a999dca..6972afe486bd 100644
--- a/llvm/test/Transforms/InterleavedAccess/X86/interleaved-accesses-64bits-avx.ll
+++ b/llvm/test/Transforms/InterleavedAccess/X86/interleaved-accesses-64bits-avx.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -mtriple=x86_64-pc-linux  -mattr=+avx -interleaved-access -S | FileCheck %s
+; RUN: opt < %s -mtriple=x86_64-pc-linux  -mattr=+avx -passes=interleaved-access -S | FileCheck %s
 
 ; This file tests the function `llvm::lowerInterleavedLoad/Store`.
 
diff --git a/llvm/test/Transforms/InterleavedAccess/X86/interleavedLoad-inseltpoison.ll b/llvm/test/Transforms/InterleavedAccess/X86/interleavedLoad-inseltpoison.ll
index 9b38f2dfbabd..327a1d2c6a66 100644
--- a/llvm/test/Transforms/InterleavedAccess/X86/interleavedLoad-inseltpoison.ll
+++ b/llvm/test/Transforms/InterleavedAccess/X86/interleavedLoad-inseltpoison.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -mtriple=x86_64-pc-linux -mattr=+avx2 -interleaved-access -S | FileCheck %s
 ; RUN: opt < %s -mtriple=x86_64-pc-linux -mattr=+avx512f -mattr=+avx512bw -mattr=+avx512vl -interleaved-access -S | FileCheck %s
+; RUN: opt < %s -mtriple=x86_64-pc-linux -mattr=+avx2 -passes=interleaved-access -S | FileCheck %s
+; RUN: opt < %s -mtriple=x86_64-pc-linux -mattr=+avx512f -mattr=+avx512bw -mattr=+avx512vl -passes=interleaved-access -S | FileCheck %s
 
 define <32 x i8> @interleaved_load_vf32_i8_stride3(ptr %ptr){
 ; CHECK-LABEL: @interleaved_load_vf32_i8_stride3(
diff --git a/llvm/test/Transforms/InterleavedAccess/X86/interleavedLoad.ll b/llvm/test/Transforms/InterleavedAccess/X86/interleavedLoad.ll
index 86c186276258..68d8b9475517 100644
--- a/llvm/test/Transforms/InterleavedAccess/X86/interleavedLoad.ll
+++ b/llvm/test/Transforms/InterleavedAccess/X86/interleavedLoad.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -mtriple=x86_64-pc-linux -mattr=+avx2 -interleaved-access -S | FileCheck %s
 ; RUN: opt < %s -mtriple=x86_64-pc-linux -mattr=+avx512f -mattr=+avx512bw -mattr=+avx512vl -interleaved-access -S | FileCheck %s
+; RUN: opt < %s -mtriple=x86_64-pc-linux -mattr=+avx2 -passes=interleaved-access -S | FileCheck %s
+; RUN: opt < %s -mtriple=x86_64-pc-linux -mattr=+avx512f -mattr=+avx512bw -mattr=+avx512vl -passes=interleaved-access -S | FileCheck %s
 
 define <32 x i8> @interleaved_load_vf32_i8_stride3(ptr %ptr){
 ; CHECK-LABEL: @interleaved_load_vf32_i8_stride3(
diff --git a/llvm/test/Transforms/InterleavedAccess/X86/interleavedStore-inseltpoison.ll b/llvm/test/Transforms/InterleavedAccess/X86/interleavedStore-inseltpoison.ll
index 301abda5708c..d1eea7a0d1bf 100644
--- a/llvm/test/Transforms/InterleavedAccess/X86/interleavedStore-inseltpoison.ll
+++ b/llvm/test/Transforms/InterleavedAccess/X86/interleavedStore-inseltpoison.ll
@@ -1,6 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 
 ; RUN: opt < %s -mtriple=x86_64-pc-linux -mattr=+avx2 -interleaved-access -S | FileCheck %s
+; RUN: opt < %s -mtriple=x86_64-pc-linux -mattr=+avx2 -passes=interleaved-access -S | FileCheck %s
 
 define void @interleaved_store_vf32_i8_stride4(<32 x i8> %x1, <32 x i8> %x2, <32 x i8> %x3, <32 x i8> %x4, ptr %p) {
 ; CHECK-LABEL: @interleaved_store_vf32_i8_stride4(
diff --git a/llvm/test/Transforms/InterleavedAccess/X86/interleavedStore.ll b/llvm/test/Transforms/InterleavedAccess/X86/interleavedStore.ll
index 75595463c740..3e7bc4130a8c 100644
--- a/llvm/test/Transforms/InterleavedAccess/X86/interleavedStore.ll
+++ b/llvm/test/Transforms/InterleavedAccess/X86/interleavedStore.ll
@@ -1,6 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 
 ; RUN: opt < %s -mtriple=x86_64-pc-linux -mattr=+avx2 -interleaved-access -S | FileCheck %s
+; RUN: opt < %s -mtriple=x86_64-pc-linux -mattr=+avx2 -passes=interleaved-access -S | FileCheck %s
 
 define void @interleaved_store_vf32_i8_stride4(<32 x i8> %x1, <32 x i8> %x2, <32 x i8> %x3, <32 x i8> %x4, ptr %p) {
 ; CHECK-LABEL: @interleaved_store_vf32_i8_stride4(
-- 
GitLab


From 9930f3e2982cd590b75f1252ea5253e53401b605 Mon Sep 17 00:00:00 2001
From: Oskar Wirga <10386631+oskarwirga@users.noreply.github.com>
Date: Sun, 10 Dec 2023 08:01:29 -0500
Subject: [PATCH 051/349] [AArch64] Fix case of 0 dynamic alloc when stack
 probing (#74877)

 I accidentally closed
https://github.com/llvm/llvm-project/pull/74806

If the dynamic allocation size is 0, then we will still probe the
current sp value despite not decrementing sp! This results in
overwriting stack data, in my case the stack canary.

The fix here is just to load the value of [sp] into xzr which is
essentially a no-op but still performs a read/probe of the new page.
---
 llvm/lib/Target/AArch64/AArch64InstrInfo.cpp     |  6 +++---
 llvm/test/CodeGen/AArch64/stack-probing-64k.ll   |  2 +-
 .../CodeGen/AArch64/stack-probing-dynamic.ll     | 16 ++++++++--------
 llvm/test/CodeGen/AArch64/stack-probing-sve.ll   | 10 +++++-----
 llvm/test/CodeGen/AArch64/stack-probing.ll       |  2 +-
 5 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 93b8295f4f3e..50cbd3672fbd 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -9532,9 +9532,9 @@ AArch64InstrInfo::probedStackAlloc(MachineBasicBlock::iterator MBBI,
       .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0))
       .setMIFlags(Flags);
 
-  //   STR XZR, [SP]
-  BuildMI(*ExitMBB, ExitMBB->end(), DL, TII->get(AArch64::STRXui))
-      .addReg(AArch64::XZR)
+  //   LDR XZR, [SP]
+  BuildMI(*ExitMBB, ExitMBB->end(), DL, TII->get(AArch64::LDRXui))
+      .addReg(AArch64::XZR, RegState::Define)
       .addReg(AArch64::SP)
       .addImm(0)
       .setMIFlags(Flags);
diff --git a/llvm/test/CodeGen/AArch64/stack-probing-64k.ll b/llvm/test/CodeGen/AArch64/stack-probing-64k.ll
index 945c271d3750..2f15e317a7f5 100644
--- a/llvm/test/CodeGen/AArch64/stack-probing-64k.ll
+++ b/llvm/test/CodeGen/AArch64/stack-probing-64k.ll
@@ -313,7 +313,7 @@ define void @static_16_align_131072(ptr %out) #0 {
 ; CHECK-NEXT:    b .LBB9_1
 ; CHECK-NEXT:  .LBB9_3: // %entry
 ; CHECK-NEXT:    mov sp, x9
-; CHECK-NEXT:    str xzr, [sp]
+; CHECK-NEXT:    ldr xzr, [sp]
 ; CHECK-NEXT:    mov x8, sp
 ; CHECK-NEXT:    str x8, [x0]
 ; CHECK-NEXT:    mov sp, x29
diff --git a/llvm/test/CodeGen/AArch64/stack-probing-dynamic.ll b/llvm/test/CodeGen/AArch64/stack-probing-dynamic.ll
index d247ed1b5997..a3b8df487ed4 100644
--- a/llvm/test/CodeGen/AArch64/stack-probing-dynamic.ll
+++ b/llvm/test/CodeGen/AArch64/stack-probing-dynamic.ll
@@ -28,7 +28,7 @@ define void @dynamic(i64 %size, ptr %out) #0 {
 ; CHECK-NEXT:    b .LBB0_1
 ; CHECK-NEXT:  .LBB0_3:
 ; CHECK-NEXT:    mov sp, x8
-; CHECK-NEXT:    str xzr, [sp]
+; CHECK-NEXT:    ldr xzr, [sp]
 ; CHECK-NEXT:    str x8, [x1]
 ; CHECK-NEXT:    mov sp, x29
 ; CHECK-NEXT:    .cfi_def_cfa wsp, 16
@@ -72,7 +72,7 @@ define void @dynamic_fixed(i64 %size, ptr %out1, ptr %out2) #0 {
 ; CHECK-NEXT:    b .LBB1_1
 ; CHECK-NEXT:  .LBB1_3:
 ; CHECK-NEXT:    mov sp, x8
-; CHECK-NEXT:    str xzr, [sp]
+; CHECK-NEXT:    ldr xzr, [sp]
 ; CHECK-NEXT:    str x8, [x2]
 ; CHECK-NEXT:    mov sp, x29
 ; CHECK-NEXT:    .cfi_def_cfa wsp, 16
@@ -122,7 +122,7 @@ define void @dynamic_align_64(i64 %size, ptr %out) #0 {
 ; CHECK-NEXT:    b .LBB2_1
 ; CHECK-NEXT:  .LBB2_3:
 ; CHECK-NEXT:    mov sp, x8
-; CHECK-NEXT:    str xzr, [sp]
+; CHECK-NEXT:    ldr xzr, [sp]
 ; CHECK-NEXT:    str x8, [x1]
 ; CHECK-NEXT:    mov sp, x29
 ; CHECK-NEXT:    .cfi_def_cfa wsp, 32
@@ -167,7 +167,7 @@ define void @dynamic_align_8192(i64 %size, ptr %out) #0 {
 ; CHECK-NEXT:    mov sp, x9
 ; CHECK-NEXT:    add x9, x0, #15
 ; CHECK-NEXT:    mov x8, sp
-; CHECK-NEXT:    str xzr, [sp]
+; CHECK-NEXT:    ldr xzr, [sp]
 ; CHECK-NEXT:    and x9, x9, #0xfffffffffffffff0
 ; CHECK-NEXT:    mov x19, sp
 ; CHECK-NEXT:    sub x8, x8, x9
@@ -181,7 +181,7 @@ define void @dynamic_align_8192(i64 %size, ptr %out) #0 {
 ; CHECK-NEXT:    b .LBB3_4
 ; CHECK-NEXT:  .LBB3_6:
 ; CHECK-NEXT:    mov sp, x8
-; CHECK-NEXT:    str xzr, [sp]
+; CHECK-NEXT:    ldr xzr, [sp]
 ; CHECK-NEXT:    str x8, [x1]
 ; CHECK-NEXT:    mov sp, x29
 ; CHECK-NEXT:    .cfi_def_cfa wsp, 32
@@ -221,7 +221,7 @@ define void @dynamic_64k_guard(i64 %size, ptr %out) #0 "stack-probe-size"="65536
 ; CHECK-NEXT:    b .LBB4_1
 ; CHECK-NEXT:  .LBB4_3:
 ; CHECK-NEXT:    mov sp, x8
-; CHECK-NEXT:    str xzr, [sp]
+; CHECK-NEXT:    ldr xzr, [sp]
 ; CHECK-NEXT:    str x8, [x1]
 ; CHECK-NEXT:    mov sp, x29
 ; CHECK-NEXT:    .cfi_def_cfa wsp, 16
@@ -265,7 +265,7 @@ define void @no_reserved_call_frame(i64 %n) #0 {
 ; CHECK-NEXT:    b .LBB5_1
 ; CHECK-NEXT:  .LBB5_3: // %entry
 ; CHECK-NEXT:    mov sp, x0
-; CHECK-NEXT:    str xzr, [sp]
+; CHECK-NEXT:    ldr xzr, [sp]
 ; CHECK-NEXT:    sub sp, sp, #1104
 ; CHECK-NEXT:    str xzr, [sp]
 ; CHECK-NEXT:    bl callee_stack_args
@@ -344,7 +344,7 @@ define void @dynamic_sve(i64 %size, ptr %out) #0 "target-features"="+sve" {
 ; CHECK-NEXT:    b .LBB7_1
 ; CHECK-NEXT:  .LBB7_3:
 ; CHECK-NEXT:    mov sp, x8
-; CHECK-NEXT:    str xzr, [sp]
+; CHECK-NEXT:    ldr xzr, [sp]
 ; CHECK-NEXT:    str x8, [x1]
 ; CHECK-NEXT:    mov sp, x29
 ; CHECK-NEXT:    .cfi_def_cfa wsp, 32
diff --git a/llvm/test/CodeGen/AArch64/stack-probing-sve.ll b/llvm/test/CodeGen/AArch64/stack-probing-sve.ll
index 4dad104e66f2..03a9220ebfdd 100644
--- a/llvm/test/CodeGen/AArch64/stack-probing-sve.ll
+++ b/llvm/test/CodeGen/AArch64/stack-probing-sve.ll
@@ -115,7 +115,7 @@ define void @sve_17_vector(ptr %out) #0 {
 ; CHECK-NEXT:    b .LBB3_1
 ; CHECK-NEXT:  .LBB3_3: // %entry
 ; CHECK-NEXT:    mov sp, x9
-; CHECK-NEXT:    str xzr, [sp]
+; CHECK-NEXT:    ldr xzr, [sp]
 ; CHECK-NEXT:    .cfi_def_cfa_register wsp
 ; CHECK-NEXT:    addvl sp, sp, #17
 ; CHECK-NEXT:    .cfi_def_cfa wsp, 16
@@ -351,7 +351,7 @@ define void @sve_16v_1p_csr(<vscale x 4 x float> %a) #0 {
 ; CHECK-NEXT:    b .LBB9_1
 ; CHECK-NEXT:  .LBB9_3: // %entry
 ; CHECK-NEXT:    mov sp, x9
-; CHECK-NEXT:    str xzr, [sp]
+; CHECK-NEXT:    ldr xzr, [sp]
 ; CHECK-NEXT:    .cfi_def_cfa_register wsp
 ; CHECK-NEXT:    str p8, [sp, #7, mul vl] // 2-byte Folded Spill
 ; CHECK-NEXT:    str z23, [sp, #1, mul vl] // 16-byte Folded Spill
@@ -467,7 +467,7 @@ define void @sve_1_vector_4096_arr(ptr %out) #0 {
 ; CHECK-NEXT:    b .LBB11_1
 ; CHECK-NEXT:  .LBB11_3: // %entry
 ; CHECK-NEXT:    mov sp, x9
-; CHECK-NEXT:    str xzr, [sp]
+; CHECK-NEXT:    ldr xzr, [sp]
 ; CHECK-NEXT:    .cfi_def_cfa_register wsp
 ; CHECK-NEXT:    addvl sp, sp, #31
 ; CHECK-NEXT:    .cfi_escape 0x0f, 0x0f, 0x8f, 0x00, 0x11, 0x90, 0xe0, 0x00, 0x22, 0x11, 0x88, 0x02, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 12304 + 264 * VG
@@ -516,7 +516,7 @@ define void @sve_1_vector_16_arr_align_8192(ptr %out) #0 {
 ; CHECK-NEXT:    b .LBB12_1
 ; CHECK-NEXT:  .LBB12_3: // %entry
 ; CHECK-NEXT:    mov sp, x9
-; CHECK-NEXT:    str xzr, [sp]
+; CHECK-NEXT:    ldr xzr, [sp]
 ; CHECK-NEXT:    mov sp, x29
 ; CHECK-NEXT:    .cfi_def_cfa wsp, 16
 ; CHECK-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload
@@ -616,7 +616,7 @@ define void @sve_1028_64k_guard(ptr %out) #0 "stack-probe-size"="65536" {
 ; CHECK-NEXT:    b .LBB14_1
 ; CHECK-NEXT:  .LBB14_3: // %entry
 ; CHECK-NEXT:    mov sp, x9
-; CHECK-NEXT:    str xzr, [sp]
+; CHECK-NEXT:    ldr xzr, [sp]
 ; CHECK-NEXT:    .cfi_def_cfa_register wsp
 ; CHECK-NEXT:    addvl sp, sp, #31
 ; CHECK-NEXT:    .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x90, 0x0e, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 1808 * VG
diff --git a/llvm/test/CodeGen/AArch64/stack-probing.ll b/llvm/test/CodeGen/AArch64/stack-probing.ll
index 5c5d9321a56e..df5408de5bab 100644
--- a/llvm/test/CodeGen/AArch64/stack-probing.ll
+++ b/llvm/test/CodeGen/AArch64/stack-probing.ll
@@ -400,7 +400,7 @@ define void @static_16_align_8192(ptr %out) #0 {
 ; CHECK-NEXT:    b .LBB13_1
 ; CHECK-NEXT:  .LBB13_3: // %entry
 ; CHECK-NEXT:    mov sp, x9
-; CHECK-NEXT:    str xzr, [sp]
+; CHECK-NEXT:    ldr xzr, [sp]
 ; CHECK-NEXT:    mov x8, sp
 ; CHECK-NEXT:    str x8, [x0]
 ; CHECK-NEXT:    mov sp, x29
-- 
GitLab


From 2ca101f4b019adafe5fe3545420eaec160bd6e79 Mon Sep 17 00:00:00 2001
From: "Stephan T. Lavavej" <stl@nuwen.net>
Date: Sun, 10 Dec 2023 05:19:55 -0800
Subject: [PATCH 052/349] [libc++][test] Fix `MaybePOCCAAllocator` to finally
 meet the allocator requirements (#74960)

Found while running libc++'s test suite with MSVC's STL.

After @CaseyCarter's [LLVM-D118279](https://reviews.llvm.org/D118279)
https://github.com/llvm/llvm-project/commit/c5ba46ea1804dfefb22e6d2bb65ff1636d2cc8cd
"\[libcxx\]\[test\] `MaybePOCCAAllocator` should meet the
*Cpp17Allocator* requirements" followed by @philnik777's
[LLVM-D68365](https://reviews.llvm.org/D68365)
https://github.com/llvm/llvm-project/commit/98d3d5b5da66e3cf7807c23a0294280bb796466b
"\[libc++\] Implement [P1004R2](https://wg21.link/P1004R2) (`constexpr
std::vector`)", one more change is necessary.

MSVC's `constexpr vector` implementation noticed this because we always
rebind allocators.
---
 libcxx/test/support/allocators.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libcxx/test/support/allocators.h b/libcxx/test/support/allocators.h
index 2b987ad87278..02436fd9c35e 100644
--- a/libcxx/test/support/allocators.h
+++ b/libcxx/test/support/allocators.h
@@ -209,7 +209,7 @@ public:
         : id_(id), copy_assigned_into_(copy_assigned_into) {}
 
     template <class U>
-    MaybePOCCAAllocator(const MaybePOCCAAllocator<U, POCCAValue>& that)
+    TEST_CONSTEXPR MaybePOCCAAllocator(const MaybePOCCAAllocator<U, POCCAValue>& that)
         : id_(that.id_), copy_assigned_into_(that.copy_assigned_into_) {}
 
     MaybePOCCAAllocator(const MaybePOCCAAllocator&) = default;
-- 
GitLab


From 184290e579ccb909faf9a03e35266ed23cf26e23 Mon Sep 17 00:00:00 2001
From: Florian Hahn <flo@fhahn.com>
Date: Sun, 10 Dec 2023 13:56:53 +0000
Subject: [PATCH 053/349] [LAA] Add tests with dependencies may preventing
 st-to-ld forwarding.

Add test cases with varying distances between stores and loads that may
prevent store-to-load forwarding.
---
 .../num-iters-for-store-load-conflict.ll      | 310 ++++++++++++++++++
 1 file changed, 310 insertions(+)
 create mode 100644 llvm/test/Analysis/LoopAccessAnalysis/num-iters-for-store-load-conflict.ll

diff --git a/llvm/test/Analysis/LoopAccessAnalysis/num-iters-for-store-load-conflict.ll b/llvm/test/Analysis/LoopAccessAnalysis/num-iters-for-store-load-conflict.ll
new file mode 100644
index 000000000000..d3eda21dee27
--- /dev/null
+++ b/llvm/test/Analysis/LoopAccessAnalysis/num-iters-for-store-load-conflict.ll
@@ -0,0 +1,310 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 4
+; RUN: opt -passes='print<access-info>' -disable-output  < %s 2>&1 | FileCheck %s
+
+define void @forward_dist_7(ptr %A, ptr noalias %B) {
+; CHECK-LABEL: 'forward_dist_7'
+; CHECK-NEXT:    loop:
+; CHECK-NEXT:      Report: unsafe dependent memory operations in loop. Use #pragma clang loop distribute(enable) to allow loop distribution to attempt to isolate the offending operations into a separate loop
+; CHECK-NEXT:  Forward loop carried data dependence that prevents store-to-load forwarding.
+; CHECK-NEXT:      Dependences:
+; CHECK-NEXT:        ForwardButPreventsForwarding:
+; CHECK-NEXT:            store i32 0, ptr %gep.2, align 4 ->
+; CHECK-NEXT:            %l = load i32, ptr %gep.1, align 4
+; CHECK-EMPTY:
+; CHECK-NEXT:      Run-time memory checks:
+; CHECK-NEXT:      Grouped accesses:
+; CHECK-EMPTY:
+; CHECK-NEXT:      Non vectorizable stores to invariant address were not found in loop.
+; CHECK-NEXT:      SCEV assumptions:
+; CHECK-EMPTY:
+; CHECK-NEXT:      Expressions re-written:
+;
+entry:
+  br label %loop
+
+loop:
+  %iv = phi i64 [ 0, %entry ], [ %next, %loop ]
+  %gep.1  = getelementptr i32, ptr %A, i64 %iv
+  %gep.2  = getelementptr i32, ptr %gep.1, i64 7
+  store i32 0, ptr %gep.2, align 4
+  %l = load i32, ptr %gep.1
+  store i32 %l, ptr %B
+  %next = add nuw nsw i64 %iv, 1
+  %ec = icmp eq i64 %iv, 1000
+  br i1 %ec, label %exit, label %loop
+
+exit:
+  ret void
+}
+
+define void @forward_dist_9(ptr %A, ptr noalias %B) {
+; CHECK-LABEL: 'forward_dist_9'
+; CHECK-NEXT:    loop:
+; CHECK-NEXT:      Report: unsafe dependent memory operations in loop. Use #pragma clang loop distribute(enable) to allow loop distribution to attempt to isolate the offending operations into a separate loop
+; CHECK-NEXT:  Forward loop carried data dependence that prevents store-to-load forwarding.
+; CHECK-NEXT:      Dependences:
+; CHECK-NEXT:        ForwardButPreventsForwarding:
+; CHECK-NEXT:            store i32 0, ptr %gep.2, align 4 ->
+; CHECK-NEXT:            %l = load i32, ptr %gep.1, align 4
+; CHECK-EMPTY:
+; CHECK-NEXT:      Run-time memory checks:
+; CHECK-NEXT:      Grouped accesses:
+; CHECK-EMPTY:
+; CHECK-NEXT:      Non vectorizable stores to invariant address were not found in loop.
+; CHECK-NEXT:      SCEV assumptions:
+; CHECK-EMPTY:
+; CHECK-NEXT:      Expressions re-written:
+;
+entry:
+  br label %loop
+
+loop:
+  %iv = phi i64 [ 0, %entry ], [ %next, %loop ]
+  %gep.1  = getelementptr i32, ptr %A, i64 %iv
+  %gep.2  = getelementptr i32, ptr %gep.1, i64 9
+  store i32 0, ptr %gep.2, align 4
+  %l = load i32, ptr %gep.1
+  store i32 %l, ptr %B
+  %next = add nuw nsw i64 %iv, 1
+  %ec = icmp eq i64 %iv, 1000
+  br i1 %ec, label %exit, label %loop
+
+exit:
+  ret void
+}
+
+define void @forward_dist_11(ptr %A, ptr noalias %B) {
+; CHECK-LABEL: 'forward_dist_11'
+; CHECK-NEXT:    loop:
+; CHECK-NEXT:      Report: unsafe dependent memory operations in loop. Use #pragma clang loop distribute(enable) to allow loop distribution to attempt to isolate the offending operations into a separate loop
+; CHECK-NEXT:  Forward loop carried data dependence that prevents store-to-load forwarding.
+; CHECK-NEXT:      Dependences:
+; CHECK-NEXT:        ForwardButPreventsForwarding:
+; CHECK-NEXT:            store i32 0, ptr %gep.2, align 4 ->
+; CHECK-NEXT:            %l = load i32, ptr %gep.1, align 4
+; CHECK-EMPTY:
+; CHECK-NEXT:      Run-time memory checks:
+; CHECK-NEXT:      Grouped accesses:
+; CHECK-EMPTY:
+; CHECK-NEXT:      Non vectorizable stores to invariant address were not found in loop.
+; CHECK-NEXT:      SCEV assumptions:
+; CHECK-EMPTY:
+; CHECK-NEXT:      Expressions re-written:
+;
+entry:
+  br label %loop
+
+loop:
+  %iv = phi i64 [ 0, %entry ], [ %next, %loop ]
+  %gep.1  = getelementptr i32, ptr %A, i64 %iv
+  %gep.2  = getelementptr i32, ptr %gep.1, i64 9
+  store i32 0, ptr %gep.2, align 4
+  %l = load i32, ptr %gep.1
+  store i32 %l, ptr %B
+  %next = add nuw nsw i64 %iv, 1
+  %ec = icmp eq i64 %iv, 1000
+  br i1 %ec, label %exit, label %loop
+
+exit:
+  ret void
+}
+
+define void @forward_dist_13(ptr %A, ptr noalias %B) {
+; CHECK-LABEL: 'forward_dist_13'
+; CHECK-NEXT:    loop:
+; CHECK-NEXT:      Report: unsafe dependent memory operations in loop. Use #pragma clang loop distribute(enable) to allow loop distribution to attempt to isolate the offending operations into a separate loop
+; CHECK-NEXT:  Forward loop carried data dependence that prevents store-to-load forwarding.
+; CHECK-NEXT:      Dependences:
+; CHECK-NEXT:        ForwardButPreventsForwarding:
+; CHECK-NEXT:            store i32 0, ptr %gep.2, align 4 ->
+; CHECK-NEXT:            %l = load i32, ptr %gep.1, align 4
+; CHECK-EMPTY:
+; CHECK-NEXT:      Run-time memory checks:
+; CHECK-NEXT:      Grouped accesses:
+; CHECK-EMPTY:
+; CHECK-NEXT:      Non vectorizable stores to invariant address were not found in loop.
+; CHECK-NEXT:      SCEV assumptions:
+; CHECK-EMPTY:
+; CHECK-NEXT:      Expressions re-written:
+;
+entry:
+  br label %loop
+
+loop:
+  %iv = phi i64 [ 0, %entry ], [ %next, %loop ]
+  %gep.1  = getelementptr i32, ptr %A, i64 %iv
+  %gep.2  = getelementptr i32, ptr %gep.1, i64 13
+  store i32 0, ptr %gep.2, align 4
+  %l = load i32, ptr %gep.1
+  store i32 %l, ptr %B
+  %next = add nuw nsw i64 %iv, 1
+  %ec = icmp eq i64 %iv, 1000
+  br i1 %ec, label %exit, label %loop
+
+exit:
+  ret void
+}
+
+define void @forward_dist_15(ptr %A, ptr noalias %B) {
+; CHECK-LABEL: 'forward_dist_15'
+; CHECK-NEXT:    loop:
+; CHECK-NEXT:      Report: unsafe dependent memory operations in loop. Use #pragma clang loop distribute(enable) to allow loop distribution to attempt to isolate the offending operations into a separate loop
+; CHECK-NEXT:  Forward loop carried data dependence that prevents store-to-load forwarding.
+; CHECK-NEXT:      Dependences:
+; CHECK-NEXT:        ForwardButPreventsForwarding:
+; CHECK-NEXT:            store i32 0, ptr %gep.2, align 4 ->
+; CHECK-NEXT:            %l = load i32, ptr %gep.1, align 4
+; CHECK-EMPTY:
+; CHECK-NEXT:      Run-time memory checks:
+; CHECK-NEXT:      Grouped accesses:
+; CHECK-EMPTY:
+; CHECK-NEXT:      Non vectorizable stores to invariant address were not found in loop.
+; CHECK-NEXT:      SCEV assumptions:
+; CHECK-EMPTY:
+; CHECK-NEXT:      Expressions re-written:
+;
+entry:
+  br label %loop
+
+loop:
+  %iv = phi i64 [ 0, %entry ], [ %next, %loop ]
+  %gep.1  = getelementptr i32, ptr %A, i64 %iv
+  %gep.2  = getelementptr i32, ptr %gep.1, i64 13
+  store i32 0, ptr %gep.2, align 4
+  %l = load i32, ptr %gep.1
+  store i32 %l, ptr %B
+  %next = add nuw nsw i64 %iv, 1
+  %ec = icmp eq i64 %iv, 1000
+  br i1 %ec, label %exit, label %loop
+
+exit:
+  ret void
+}
+
+define void @forward_dist_17(ptr %A, ptr noalias %B) {
+; CHECK-LABEL: 'forward_dist_17'
+; CHECK-NEXT:    loop:
+; CHECK-NEXT:      Report: unsafe dependent memory operations in loop. Use #pragma clang loop distribute(enable) to allow loop distribution to attempt to isolate the offending operations into a separate loop
+; CHECK-NEXT:  Forward loop carried data dependence that prevents store-to-load forwarding.
+; CHECK-NEXT:      Dependences:
+; CHECK-NEXT:        ForwardButPreventsForwarding:
+; CHECK-NEXT:            store i32 0, ptr %gep.2, align 4 ->
+; CHECK-NEXT:            %l = load i32, ptr %gep.1, align 4
+; CHECK-EMPTY:
+; CHECK-NEXT:      Run-time memory checks:
+; CHECK-NEXT:      Grouped accesses:
+; CHECK-EMPTY:
+; CHECK-NEXT:      Non vectorizable stores to invariant address were not found in loop.
+; CHECK-NEXT:      SCEV assumptions:
+; CHECK-EMPTY:
+; CHECK-NEXT:      Expressions re-written:
+;
+entry:
+  br label %loop
+
+loop:
+  %iv = phi i64 [ 0, %entry ], [ %next, %loop ]
+  %gep.1  = getelementptr i32, ptr %A, i64 %iv
+  %gep.2  = getelementptr i32, ptr %gep.1, i64 17
+  store i32 0, ptr %gep.2, align 4
+  %l = load i32, ptr %gep.1
+  store i32 %l, ptr %B
+  %next = add nuw nsw i64 %iv, 1
+  %ec = icmp eq i64 %iv, 1000
+  br i1 %ec, label %exit, label %loop
+
+exit:
+  ret void
+}
+
+define void @forward_dist_19(ptr %A, ptr noalias %B) {
+; CHECK-LABEL: 'forward_dist_19'
+; CHECK-NEXT:    loop:
+; CHECK-NEXT:      Report: unsafe dependent memory operations in loop. Use #pragma clang loop distribute(enable) to allow loop distribution to attempt to isolate the offending operations into a separate loop
+; CHECK-NEXT:  Forward loop carried data dependence that prevents store-to-load forwarding.
+; CHECK-NEXT:      Dependences:
+; CHECK-NEXT:        ForwardButPreventsForwarding:
+; CHECK-NEXT:            store i32 0, ptr %gep.2, align 4 ->
+; CHECK-NEXT:            %l = load i32, ptr %gep.1, align 4
+; CHECK-EMPTY:
+; CHECK-NEXT:      Run-time memory checks:
+; CHECK-NEXT:      Grouped accesses:
+; CHECK-EMPTY:
+; CHECK-NEXT:      Non vectorizable stores to invariant address were not found in loop.
+; CHECK-NEXT:      SCEV assumptions:
+; CHECK-EMPTY:
+; CHECK-NEXT:      Expressions re-written:
+;
+entry:
+  br label %loop
+
+loop:
+  %iv = phi i64 [ 0, %entry ], [ %next, %loop ]
+  %gep.1  = getelementptr i32, ptr %A, i64 %iv
+  %gep.2  = getelementptr i32, ptr %gep.1, i64 19
+  store i32 0, ptr %gep.2, align 4
+  %l = load i32, ptr %gep.1
+  store i32 %l, ptr %B
+  %next = add nuw nsw i64 %iv, 1
+  %ec = icmp eq i64 %iv, 1000
+  br i1 %ec, label %exit, label %loop
+
+exit:
+  ret void
+}
+
+@A = global [37 x [37 x double]] zeroinitializer, align 8
+
+define void @unknown_loop_bounds(i64 %x, i64 %y) {
+; CHECK-LABEL: 'unknown_loop_bounds'
+; CHECK-NEXT:    inner:
+; CHECK-NEXT:      Report: unsafe dependent memory operations in loop. Use #pragma clang loop distribute(enable) to allow loop distribution to attempt to isolate the offending operations into a separate loop
+; CHECK-NEXT:  Backward loop carried data dependence that prevents store-to-load forwarding.
+; CHECK-NEXT:      Dependences:
+; CHECK-NEXT:        BackwardVectorizableButPreventsForwarding:
+; CHECK-NEXT:            %l = load double, ptr %gep.0, align 8 ->
+; CHECK-NEXT:            store double %l, ptr %gep.1, align 8
+; CHECK-EMPTY:
+; CHECK-NEXT:      Run-time memory checks:
+; CHECK-NEXT:      Grouped accesses:
+; CHECK-EMPTY:
+; CHECK-NEXT:      Non vectorizable stores to invariant address were not found in loop.
+; CHECK-NEXT:      SCEV assumptions:
+; CHECK-EMPTY:
+; CHECK-NEXT:      Expressions re-written:
+; CHECK-NEXT:    outer.header:
+; CHECK-NEXT:      Report: loop is not the innermost loop
+; CHECK-NEXT:      Dependences:
+; CHECK-NEXT:      Run-time memory checks:
+; CHECK-NEXT:      Grouped accesses:
+; CHECK-EMPTY:
+; CHECK-NEXT:      Non vectorizable stores to invariant address were not found in loop.
+; CHECK-NEXT:      SCEV assumptions:
+; CHECK-EMPTY:
+; CHECK-NEXT:      Expressions re-written:
+;
+entry:
+  br label %outer.header
+
+outer.header:
+  %outer.iv = phi i64 [ 0, %entry ], [ %outer.iv.next, %outer.latch ]
+  %outer.iv.next = add nuw nsw i64 %outer.iv, 1
+  br label %inner
+
+inner:
+  %inner.iv = phi i64 [ 0, %outer.header ], [ %inner.iv.next, %inner ]
+  %gep.0 = getelementptr inbounds [37 x [37 x double]], ptr @A, i64 0, i64 %outer.iv, i64 %inner.iv
+  %l = load double, ptr %gep.0, align 8
+  %gep.1 = getelementptr inbounds [37 x [37 x double]], ptr @A, i64 0, i64 %outer.iv.next, i64 %inner.iv
+  store double %l, ptr %gep.1, align 8
+  %inner.iv.next = add nuw nsw i64 %inner.iv, 1
+  %inner.ec = icmp eq i64 %inner.iv.next, %y
+  br i1 %inner.ec, label %outer.latch, label %inner
+
+outer.latch:
+  %outer.ec = icmp eq i64 %outer.iv.next, %x
+  br i1 %outer.ec, label %exit, label %outer.header
+
+exit:
+  ret void
+}
-- 
GitLab


From 99eb843c8bda5d636338edfd4f67728b6573a2a9 Mon Sep 17 00:00:00 2001
From: "Stephan T. Lavavej" <stl@nuwen.net>
Date: Sun, 10 Dec 2023 06:52:48 -0800
Subject: [PATCH 054/349] [libc++][test] `concat_macros.h`: Fix
 `TEST_HAS_NO_WIDE_CHARACTERS` syntax damage (#74987)

@mordante This was introduced by #73395 a couple of days ago.

This is causing PR checks to fail, [stage3 (generic-no-wide-characters,
libcxx-runners-8-set,
OFF)](https://github.com/llvm/llvm-project/actions/runs/7154839054/job/19484723909?pr=74254#logs):

```
In file included from /home/runner/_work/llvm-project/llvm-project/libcxx/test/std/utilities/format/format.tuple/format.functions.vformat.pass.cpp:29:
/home/runner/_work/llvm-project/llvm-project/libcxx/test/support/concat_macros.h:86:1: error: expected ')'
   86 | OutIt test_transcode(InIt first, InIt last, OutIt out_it) {
      | ^
/home/runner/_work/llvm-project/llvm-project/libcxx/test/support/concat_macros.h:80:11: note: to match this '('
   80 |   requires(std::output_iterator<OutIt, const char&> &&
      |           ^
/home/runner/_work/llvm-project/llvm-project/libcxx/test/std/utilities/format/format.tuple/format.functions.vformat.pass.cpp:63:2: error: expected unqualified-id
   63 | }
      |  ^
```
---
 libcxx/test/support/concat_macros.h | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/libcxx/test/support/concat_macros.h b/libcxx/test/support/concat_macros.h
index bc1306fbdb53..57c5f5e0632e 100644
--- a/libcxx/test/support/concat_macros.h
+++ b/libcxx/test/support/concat_macros.h
@@ -80,9 +80,9 @@ template <class InIt, class OutIt>
   requires(std::output_iterator<OutIt, const char&> &&
            (std::same_as<std::iter_value_t<InIt>, char16_t>
 #    ifndef TEST_HAS_NO_WIDE_CHARACTERS
-            || (std::same_as<std::iter_value_t<InIt>, wchar_t> && sizeof(wchar_t) == 2))
+            || (std::same_as<std::iter_value_t<InIt>, wchar_t> && sizeof(wchar_t) == 2)
 #    endif
-               )
+                ))
 OutIt test_transcode(InIt first, InIt last, OutIt out_it) {
   while (first != last) {
     char32_t value = *first++;
@@ -118,11 +118,11 @@ OutIt test_transcode(InIt first, InIt last, OutIt out_it) {
 
 template <class InIt, class OutIt>
   requires(std::output_iterator<OutIt, const char&> &&
-           (std::same_as<std::iter_value_t<InIt>, char32_t> ||
+           (std::same_as<std::iter_value_t<InIt>, char32_t>
 #    ifndef TEST_HAS_NO_WIDE_CHARACTERS
-            (std::same_as<std::iter_value_t<InIt>, wchar_t> && sizeof(wchar_t) == 4))
+            || (std::same_as<std::iter_value_t<InIt>, wchar_t> && sizeof(wchar_t) == 4)
 #    endif
-               )
+                ))
 OutIt test_transcode(InIt first, InIt last, OutIt out_it) {
   while (first != last) {
     char32_t value = *first++;
-- 
GitLab


From 69a10e0e6af8ce4b4db88e307a21c8ca87add4af Mon Sep 17 00:00:00 2001
From: "Stephan T. Lavavej" <stl@nuwen.net>
Date: Sun, 10 Dec 2023 07:28:17 -0800
Subject: [PATCH 055/349] [libc++][test] Consistently use `TEST_SHORT_WCHAR`
 (#74958)

Found while running libc++'s test suite with MSVC's STL.

* In `escaped_output.unicode.pass.cpp`, replace `_LIBCPP_SHORT_WCHAR`
with `TEST_SHORT_WCHAR`.
+ This was the only test that was directly using the `_LIBCPP` macro.
`libcxx/test/support/test_macros.h` performs this mapping:
https://github.com/llvm/llvm-project/blob/c60ac509399da5cba533b9b6cc5b983c59f7d7b3/libcxx/test/support/test_macros.h#L442-L444
* In `msvc_stdlib_force_include.h`, define `TEST_SHORT_WCHAR`.
---
 .../format.functions/escaped_output.unicode.pass.cpp | 12 ++++++------
 libcxx/test/support/msvc_stdlib_force_include.h      |  2 ++
 2 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/libcxx/test/std/utilities/format/format.functions/escaped_output.unicode.pass.cpp b/libcxx/test/std/utilities/format/format.functions/escaped_output.unicode.pass.cpp
index 5c6f86f742ba..23b26722d7be 100644
--- a/libcxx/test/std/utilities/format/format.functions/escaped_output.unicode.pass.cpp
+++ b/libcxx/test/std/utilities/format/format.functions/escaped_output.unicode.pass.cpp
@@ -515,7 +515,7 @@ static void test_ill_formed_utf8() {
 }
 
 #ifndef TEST_HAS_NO_WIDE_CHARACTERS
-#  ifdef _LIBCPP_SHORT_WCHAR
+#  ifdef TEST_SHORT_WCHAR
 static void test_ill_formed_utf16() {
   using namespace std::literals;
 
@@ -543,7 +543,7 @@ static void test_ill_formed_utf16() {
               L"\xdbff"
               "a");
 }
-#  else // _LIBCPP_SHORT_WCHAR
+#  else // TEST_SHORT_WCHAR
 static void test_ill_formed_utf32() {
   using namespace std::literals;
 
@@ -552,7 +552,7 @@ static void test_ill_formed_utf32() {
   test_format(LR"("\x{ffffffff}")"sv, L"{:?}", L"\xffffffff"); // largest encoded code point
 }
 
-#  endif // _LIBCPP_SHORT_WCHAR
+#  endif // TEST_SHORT_WCHAR
 #endif   // TEST_HAS_NO_WIDE_CHARACTERS
 
 int main(int, char**) {
@@ -563,11 +563,11 @@ int main(int, char**) {
 
   test_ill_formed_utf8();
 #ifndef TEST_HAS_NO_WIDE_CHARACTERS
-#  ifdef _LIBCPP_SHORT_WCHAR
+#  ifdef TEST_SHORT_WCHAR
   test_ill_formed_utf16();
-#  else  // _LIBCPP_SHORT_WCHAR
+#  else  // TEST_SHORT_WCHAR
   test_ill_formed_utf32();
-#  endif // _LIBCPP_SHORT_WCHAR
+#  endif // TEST_SHORT_WCHAR
 #endif   // TEST_HAS_NO_WIDE_CHARACTERS
 
   return 0;
diff --git a/libcxx/test/support/msvc_stdlib_force_include.h b/libcxx/test/support/msvc_stdlib_force_include.h
index b5ba33bd281c..5742bbf4f557 100644
--- a/libcxx/test/support/msvc_stdlib_force_include.h
+++ b/libcxx/test/support/msvc_stdlib_force_include.h
@@ -100,6 +100,8 @@ const AssertionDialogAvoider assertion_dialog_avoider{};
 #  define TEST_STD_VER 14
 #endif
 
+#define TEST_SHORT_WCHAR
+
 #define _LIBCPP_AVAILABILITY_THROW_BAD_ANY_CAST
 
 #ifdef __clang__
-- 
GitLab


From fde04e61cb7393f0ca982d7fc905a17767d93e6e Mon Sep 17 00:00:00 2001
From: "Stephan T. Lavavej" <stl@nuwen.net>
Date: Sun, 10 Dec 2023 07:33:54 -0800
Subject: [PATCH 056/349] [libc++][test] Cleanup
 `LIBCPP_ONLY(meow_assert(...))` to `LIBCPP_MEOW_ASSERT(...)` (#74967)

This is a syntax cleanup, not needed for running libc++'s tests with
MSVC's STL.

While changing
`libcxx/test/std/input.output/filesystems/fs.enum/enum.path.format.pass.cpp`
in #74965, I noticed that libc++'s tests almost always use the
special-purpose macros for "this is a libc++-specific `static_assert`
etc." defined by:

https://github.com/llvm/llvm-project/blob/b85f1f9b182234ba366d78ae2174a149e44d08c1/libcxx/test/support/test_macros.h#L240-L253

However, there were a very small number of occurrences that were using
the general-purpose `LIBCPP_ONLY` macro when they could have been using
the special-purpose macros. I believe that they should be cleaned up, to
make it easier to search for usage, and to make it clearer when the full
power of `LIBCPP_ONLY` is necessary.

This is a pure regex replacement from
`LIBCPP_ONLY\((assert|static_assert|ASSERT_NOEXCEPT|ASSERT_NOT_NOEXCEPT)\((.*)\)\);`
to `LIBCPP_\U$1($2);` using the power of [VSCode's case changing in
regex
replace](https://code.visualstudio.com/docs/editor/codebasics#_case-changing-in-regex-replace).

To avoid merge conflicts, this isn't changing the line in
`libcxx/test/std/input.output/filesystems/fs.enum/enum.path.format.pass.cpp`
that #74965 is already changing to use `LIBCPP_STATIC_ASSERT`.
---
 .../class.path/path.member/path.assign/source.pass.cpp        | 2 +-
 .../filesystems/fs.enum/enum.copy_options.pass.cpp            | 2 +-
 .../filesystems/fs.enum/enum.directory_options.pass.cpp       | 2 +-
 .../input.output/filesystems/fs.enum/enum.file_type.pass.cpp  | 2 +-
 .../filesystems/fs.enum/enum.perm_options.pass.cpp            | 2 +-
 .../std/input.output/filesystems/fs.enum/enum.perms.pass.cpp  | 2 +-
 .../filesystems/fs.op.funcs/fs.op.absolute/absolute.pass.cpp  | 2 +-
 .../fs.op.funcs/fs.op.canonical/canonical.pass.cpp            | 4 ++--
 .../fs.op.funcs/fs.op.permissions/permissions.pass.cpp        | 2 +-
 .../fs.op.temp_dir_path/temp_directory_path.pass.cpp          | 4 ++--
 10 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/libcxx/test/std/input.output/filesystems/class.path/path.member/path.assign/source.pass.cpp b/libcxx/test/std/input.output/filesystems/class.path/path.member/path.assign/source.pass.cpp
index 893d09221fce..e969aa4e8d66 100644
--- a/libcxx/test/std/input.output/filesystems/class.path/path.member/path.assign/source.pass.cpp
+++ b/libcxx/test/std/input.output/filesystems/class.path/path.member/path.assign/source.pass.cpp
@@ -230,7 +230,7 @@ void RunStringMoveTest(const fs::path::value_type* Expect) {
   assert(p == Expect);
   {
     // Signature test
-    LIBCPP_ONLY(ASSERT_NOEXCEPT(p = std::move(ss)));
+    LIBCPP_ASSERT_NOEXCEPT(p = std::move(ss));
   }
 }
 
diff --git a/libcxx/test/std/input.output/filesystems/fs.enum/enum.copy_options.pass.cpp b/libcxx/test/std/input.output/filesystems/fs.enum/enum.copy_options.pass.cpp
index 56322575fef2..4ef28ee01d8d 100644
--- a/libcxx/test/std/input.output/filesystems/fs.enum/enum.copy_options.pass.cpp
+++ b/libcxx/test/std/input.output/filesystems/fs.enum/enum.copy_options.pass.cpp
@@ -30,7 +30,7 @@ int main(int, char**) {
   typedef std::underlying_type<E>::type UT;
   static_assert(!std::is_convertible<E, UT>::value, "");
 
-  LIBCPP_ONLY(static_assert(std::is_same<UT, unsigned short>::value, "")); // Implementation detail
+  LIBCPP_STATIC_ASSERT(std::is_same<UT, unsigned short>::value, ""); // Implementation detail
 
   typedef check_bitmask_type<E, E::skip_existing, E::update_existing> BitmaskTester;
   assert(BitmaskTester::check());
diff --git a/libcxx/test/std/input.output/filesystems/fs.enum/enum.directory_options.pass.cpp b/libcxx/test/std/input.output/filesystems/fs.enum/enum.directory_options.pass.cpp
index 2597457ed747..4480b1e4e335 100644
--- a/libcxx/test/std/input.output/filesystems/fs.enum/enum.directory_options.pass.cpp
+++ b/libcxx/test/std/input.output/filesystems/fs.enum/enum.directory_options.pass.cpp
@@ -29,7 +29,7 @@ int main(int, char**) {
   // Check that E is a scoped enum by checking for conversions.
   typedef std::underlying_type<E>::type UT;
   static_assert(!std::is_convertible<E, UT>::value, "");
-  LIBCPP_ONLY(static_assert(std::is_same<UT, unsigned char>::value, ""));
+  LIBCPP_STATIC_ASSERT(std::is_same<UT, unsigned char>::value, "");
 
   typedef check_bitmask_type<E, E::follow_directory_symlink, E::skip_permission_denied> BitmaskTester;
   assert(BitmaskTester::check());
diff --git a/libcxx/test/std/input.output/filesystems/fs.enum/enum.file_type.pass.cpp b/libcxx/test/std/input.output/filesystems/fs.enum/enum.file_type.pass.cpp
index 63db8892b092..6062935126dd 100644
--- a/libcxx/test/std/input.output/filesystems/fs.enum/enum.file_type.pass.cpp
+++ b/libcxx/test/std/input.output/filesystems/fs.enum/enum.file_type.pass.cpp
@@ -29,7 +29,7 @@ int main(int, char**) {
   typedef std::underlying_type<E>::type UT;
   static_assert(!std::is_convertible<E, UT>::value, "");
 
-  LIBCPP_ONLY(static_assert(std::is_same<UT, signed char>::value, "")); // Implementation detail
+  LIBCPP_STATIC_ASSERT(std::is_same<UT, signed char>::value, ""); // Implementation detail
 
   // The standard doesn't specify the numeric values of the enum.
   LIBCPP_STATIC_ASSERT(
diff --git a/libcxx/test/std/input.output/filesystems/fs.enum/enum.perm_options.pass.cpp b/libcxx/test/std/input.output/filesystems/fs.enum/enum.perm_options.pass.cpp
index afc64f6f00b4..0bdae4870238 100644
--- a/libcxx/test/std/input.output/filesystems/fs.enum/enum.perm_options.pass.cpp
+++ b/libcxx/test/std/input.output/filesystems/fs.enum/enum.perm_options.pass.cpp
@@ -32,7 +32,7 @@ int main(int, char**) {
   typedef std::underlying_type<E>::type UT;
   static_assert(!std::is_convertible<E, UT>::value, "");
 
-  LIBCPP_ONLY(static_assert(std::is_same<UT, unsigned char >::value, "")); // Implementation detail
+  LIBCPP_STATIC_ASSERT(std::is_same<UT, unsigned char >::value, ""); // Implementation detail
 
   typedef check_bitmask_type<E, E::replace, E::nofollow> BitmaskTester;
   assert(BitmaskTester::check());
diff --git a/libcxx/test/std/input.output/filesystems/fs.enum/enum.perms.pass.cpp b/libcxx/test/std/input.output/filesystems/fs.enum/enum.perms.pass.cpp
index 27aa5e29de20..d1893847f01b 100644
--- a/libcxx/test/std/input.output/filesystems/fs.enum/enum.perms.pass.cpp
+++ b/libcxx/test/std/input.output/filesystems/fs.enum/enum.perms.pass.cpp
@@ -30,7 +30,7 @@ int main(int, char**) {
   typedef std::underlying_type<E>::type UT;
   static_assert(!std::is_convertible<E, UT>::value, "");
 
-  LIBCPP_ONLY(static_assert(std::is_same<UT, unsigned >::value, "")); // Implementation detail
+  LIBCPP_STATIC_ASSERT(std::is_same<UT, unsigned >::value, ""); // Implementation detail
 
   typedef check_bitmask_type<E, E::group_all, E::owner_all> BitmaskTester;
   assert(BitmaskTester::check());
diff --git a/libcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.absolute/absolute.pass.cpp b/libcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.absolute/absolute.pass.cpp
index 68fc09157c4b..7a60d1ab29f4 100644
--- a/libcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.absolute/absolute.pass.cpp
+++ b/libcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.absolute/absolute.pass.cpp
@@ -51,7 +51,7 @@ static void basic_test()
         assert(!ec);
         assert(ret.is_absolute());
         assert(PathEqIgnoreSep(ret, TC.expect));
-        LIBCPP_ONLY(assert(PathEq(ret, TC.expect)));
+        LIBCPP_ASSERT(PathEq(ret, TC.expect));
     }
 }
 
diff --git a/libcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.canonical/canonical.pass.cpp b/libcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.canonical/canonical.pass.cpp
index 6e947a355a54..0098fe8ee698 100644
--- a/libcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.canonical/canonical.pass.cpp
+++ b/libcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.canonical/canonical.pass.cpp
@@ -104,7 +104,7 @@ static void test_exception_contains_paths()
     } catch (filesystem_error const& err) {
         assert(err.path1() == p);
         // libc++ provides the current path as the second path in the exception
-        LIBCPP_ONLY(assert(err.path2() == current_path()));
+        LIBCPP_ASSERT(err.path2() == current_path());
     }
     fs::current_path(static_env.Dir);
     try {
@@ -112,7 +112,7 @@ static void test_exception_contains_paths()
         assert(false);
     } catch (filesystem_error const& err) {
         assert(err.path1() == p);
-        LIBCPP_ONLY(assert(err.path2() == static_env.Dir));
+        LIBCPP_ASSERT(err.path2() == static_env.Dir);
     }
 #endif
 }
diff --git a/libcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.permissions/permissions.pass.cpp b/libcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.permissions/permissions.pass.cpp
index 0f5a7692bb70..f009befa49c3 100644
--- a/libcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.permissions/permissions.pass.cpp
+++ b/libcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.permissions/permissions.pass.cpp
@@ -40,7 +40,7 @@ static void test_signatures()
     ASSERT_NOT_NOEXCEPT(fs::permissions(p, pr));
     ASSERT_NOT_NOEXCEPT(fs::permissions(p, pr, opts));
     ASSERT_NOEXCEPT(fs::permissions(p, pr, ec));
-    LIBCPP_ONLY(ASSERT_NOT_NOEXCEPT(fs::permissions(p, pr, opts, ec)));
+    LIBCPP_ASSERT_NOT_NOEXCEPT(fs::permissions(p, pr, opts, ec));
 }
 
 static void test_error_reporting()
diff --git a/libcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.temp_dir_path/temp_directory_path.pass.cpp b/libcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.temp_dir_path/temp_directory_path.pass.cpp
index c0a98a62e6f9..aed87b73121d 100644
--- a/libcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.temp_dir_path/temp_directory_path.pass.cpp
+++ b/libcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.temp_dir_path/temp_directory_path.pass.cpp
@@ -95,7 +95,7 @@ static void basic_tests()
         PutEnv(TC.name, dne);
         ec = GetTestEC();
         ret = temp_directory_path(ec);
-        LIBCPP_ONLY(assert(ErrorIs(ec, expect_errc)));
+        LIBCPP_ASSERT(ErrorIs(ec, expect_errc));
         assert(ec != GetTestEC());
         assert(ec);
         assert(ret == "");
@@ -104,7 +104,7 @@ static void basic_tests()
         PutEnv(TC.name, file);
         ec = GetTestEC();
         ret = temp_directory_path(ec);
-        LIBCPP_ONLY(assert(ErrorIs(ec, expect_errc)));
+        LIBCPP_ASSERT(ErrorIs(ec, expect_errc));
         assert(ec != GetTestEC());
         assert(ec);
         assert(ret == "");
-- 
GitLab


From 00441733da76e59ed7440145b7d17750d3a75b77 Mon Sep 17 00:00:00 2001
From: Animcogn <corbanvilla@gmail.com>
Date: Sun, 10 Dec 2023 11:52:47 -0500
Subject: [PATCH 057/349] [llvm][docs] Fix typo in `CoverageMappingFormat.rst`
 (#71189)

A small typographical fix in `CoverageMappingFormat.rst`.
---
 llvm/docs/CoverageMappingFormat.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/docs/CoverageMappingFormat.rst b/llvm/docs/CoverageMappingFormat.rst
index cbabad7a332c..c5cd1f795aab 100644
--- a/llvm/docs/CoverageMappingFormat.rst
+++ b/llvm/docs/CoverageMappingFormat.rst
@@ -178,7 +178,7 @@ defined inside macros, like this example demonstrates:
 Counter:
 ^^^^^^^^
 
-A coverage mapping counter can represents a reference to the profile
+A coverage mapping counter can represent a reference to the profile
 instrumentation counter. The execution count for a region with such counter
 is determined by looking up the value of the corresponding profile
 instrumentation counter.
-- 
GitLab


From 8b1181133d5029f8bb4b40f8706d6c3e3fe3598c Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu@google.com>
Date: Sun, 10 Dec 2023 10:07:12 -0800
Subject: [PATCH 058/349] [Transforms] Remove unused forward declarations (NFC)

---
 llvm/include/llvm/Transforms/HipStdPar/HipStdPar.h         | 1 -
 llvm/include/llvm/Transforms/IPO/EmbedBitcodePass.h        | 1 -
 llvm/include/llvm/Transforms/Instrumentation/MemProfiler.h | 2 --
 llvm/include/llvm/Transforms/Scalar/Scalarizer.h           | 1 -
 llvm/include/llvm/Transforms/Scalar/SimpleLoopUnswitch.h   | 1 -
 llvm/include/llvm/Transforms/Utils/ValueMapper.h           | 1 -
 llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp     | 2 --
 llvm/lib/Transforms/Vectorize/VPlanAnalysis.h              | 3 ---
 llvm/lib/Transforms/Vectorize/VPlanTransforms.h            | 2 --
 9 files changed, 14 deletions(-)

diff --git a/llvm/include/llvm/Transforms/HipStdPar/HipStdPar.h b/llvm/include/llvm/Transforms/HipStdPar/HipStdPar.h
index 9df093d8d5d5..5ff38bdf0481 100644
--- a/llvm/include/llvm/Transforms/HipStdPar/HipStdPar.h
+++ b/llvm/include/llvm/Transforms/HipStdPar/HipStdPar.h
@@ -23,7 +23,6 @@
 namespace llvm {
 
 class Module;
-class ModuleAnaysisManager;
 
 class HipStdParAcceleratorCodeSelectionPass
   : public PassInfoMixin<HipStdParAcceleratorCodeSelectionPass> {
diff --git a/llvm/include/llvm/Transforms/IPO/EmbedBitcodePass.h b/llvm/include/llvm/Transforms/IPO/EmbedBitcodePass.h
index c35048c91aba..2bb7d5f1fcf1 100644
--- a/llvm/include/llvm/Transforms/IPO/EmbedBitcodePass.h
+++ b/llvm/include/llvm/Transforms/IPO/EmbedBitcodePass.h
@@ -22,7 +22,6 @@
 
 namespace llvm {
 class Module;
-class ModulePass;
 class Pass;
 
 /// Pass embeds a copy of the module optimized with the provided pass pipeline
diff --git a/llvm/include/llvm/Transforms/Instrumentation/MemProfiler.h b/llvm/include/llvm/Transforms/Instrumentation/MemProfiler.h
index 293133b29cd9..f92c6b4775a2 100644
--- a/llvm/include/llvm/Transforms/Instrumentation/MemProfiler.h
+++ b/llvm/include/llvm/Transforms/Instrumentation/MemProfiler.h
@@ -17,9 +17,7 @@
 
 namespace llvm {
 class Function;
-class FunctionPass;
 class Module;
-class ModulePass;
 
 namespace vfs {
 class FileSystem;
diff --git a/llvm/include/llvm/Transforms/Scalar/Scalarizer.h b/llvm/include/llvm/Transforms/Scalar/Scalarizer.h
index c2d9151b4971..45e25cbf2821 100644
--- a/llvm/include/llvm/Transforms/Scalar/Scalarizer.h
+++ b/llvm/include/llvm/Transforms/Scalar/Scalarizer.h
@@ -24,7 +24,6 @@
 namespace llvm {
 
 class Function;
-class FunctionPass;
 
 struct ScalarizerPassOptions {
   // These options correspond 1:1 to cl::opt options defined in
diff --git a/llvm/include/llvm/Transforms/Scalar/SimpleLoopUnswitch.h b/llvm/include/llvm/Transforms/Scalar/SimpleLoopUnswitch.h
index 417e9668527b..b97ee23fc0e6 100644
--- a/llvm/include/llvm/Transforms/Scalar/SimpleLoopUnswitch.h
+++ b/llvm/include/llvm/Transforms/Scalar/SimpleLoopUnswitch.h
@@ -17,7 +17,6 @@ namespace llvm {
 
 class LPMUpdater;
 class Loop;
-class Pass;
 class StringRef;
 class raw_ostream;
 
diff --git a/llvm/include/llvm/Transforms/Utils/ValueMapper.h b/llvm/include/llvm/Transforms/Utils/ValueMapper.h
index eedd25f898c0..e1f2796d97ce 100644
--- a/llvm/include/llvm/Transforms/Utils/ValueMapper.h
+++ b/llvm/include/llvm/Transforms/Utils/ValueMapper.h
@@ -22,7 +22,6 @@
 namespace llvm {
 
 class Constant;
-class DIBuilder;
 class DPValue;
 class Function;
 class GlobalVariable;
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp b/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp
index afa0bc716aa0..62e49469cb01 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp
@@ -47,9 +47,7 @@
 #include <utility>
 
 namespace llvm {
-class AssumptionCache;
 class DataLayout;
-class DominatorTree;
 class LLVMContext;
 } // namespace llvm
 
diff --git a/llvm/lib/Transforms/Vectorize/VPlanAnalysis.h b/llvm/lib/Transforms/Vectorize/VPlanAnalysis.h
index 473a7c28e48a..7276641551ae 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanAnalysis.h
+++ b/llvm/lib/Transforms/Vectorize/VPlanAnalysis.h
@@ -16,12 +16,9 @@ namespace llvm {
 class LLVMContext;
 class VPValue;
 class VPBlendRecipe;
-class VPInterleaveRecipe;
 class VPInstruction;
-class VPReductionPHIRecipe;
 class VPWidenRecipe;
 class VPWidenCallRecipe;
-class VPWidenCastRecipe;
 class VPWidenIntOrFpInductionRecipe;
 class VPWidenMemoryInstructionRecipe;
 struct VPWidenSelectRecipe;
diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.h b/llvm/lib/Transforms/Vectorize/VPlanTransforms.h
index e8a6da8c3205..3bf91115debb 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.h
+++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.h
@@ -22,11 +22,9 @@ class InductionDescriptor;
 class Instruction;
 class PHINode;
 class ScalarEvolution;
-class Loop;
 class PredicatedScalarEvolution;
 class TargetLibraryInfo;
 class VPBuilder;
-class VPRecipeBuilder;
 
 struct VPlanTransforms {
   /// Replaces the VPInstructions in \p Plan with corresponding
-- 
GitLab


From 55531e715faabc6edfcba574e4861c97f989850d Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu@google.com>
Date: Sun, 10 Dec 2023 10:38:55 -0800
Subject: [PATCH 059/349] [Target] Remove unused forward declarations (NFC)

---
 llvm/lib/Target/AMDGPU/AMDGPU.h                    | 1 -
 llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h | 1 -
 llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h     | 1 -
 llvm/lib/Target/AMDGPU/Utils/AMDGPUMemoryUtils.h   | 2 --
 llvm/lib/Target/Hexagon/HexagonTargetMachine.h     | 2 --
 llvm/lib/Target/LoongArch/LoongArchISelLowering.h  | 1 -
 llvm/lib/Target/RISCV/RISCV.h                      | 5 -----
 7 files changed, 13 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 323560a46f31..fc32a3dc434b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -17,7 +17,6 @@
 namespace llvm {
 
 class AMDGPUTargetMachine;
-class GCNTargetMachine;
 class TargetMachine;
 
 // GlobalISel passes
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h b/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h
index 18a7b5d7a963..6d6bd86711b1 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h
@@ -30,7 +30,6 @@ class MDNode;
 class Module;
 struct SIProgramInfo;
 class Type;
-class GCNSubtarget;
 
 namespace AMDGPU {
 
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h b/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h
index 25c0b4953ab7..248ee26a47eb 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h
@@ -20,7 +20,6 @@
 namespace llvm {
 
 class AMDGPUSubtarget;
-class GCNSubtarget;
 
 class AMDGPUMachineFunction : public MachineFunctionInfo {
   /// A map to keep track of local memory objects and their offsets within the
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUMemoryUtils.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUMemoryUtils.h
index 7c6ed01a1cd4..e42b27f8e09e 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUMemoryUtils.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUMemoryUtils.h
@@ -14,12 +14,10 @@ namespace llvm {
 struct Align;
 class AAResults;
 class DataLayout;
-class Function;
 class GlobalVariable;
 class LoadInst;
 class MemoryDef;
 class MemorySSA;
-class Module;
 class Value;
 
 namespace AMDGPU {
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
index 4ffd0fd89de6..dddd79ad1fcf 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
+++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
@@ -21,8 +21,6 @@
 
 namespace llvm {
 
-class Module;
-
 class HexagonTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<HexagonSubtarget>> SubtargetMap;
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
index ec1e3351ac87..2d73a7394946 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
@@ -21,7 +21,6 @@
 
 namespace llvm {
 class LoongArchSubtarget;
-struct LoongArchRegisterInfo;
 namespace LoongArchISD {
 enum NodeType : unsigned {
   FIRST_NUMBER = ISD::BUILTIN_OP_END,
diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
index ad1713cad64c..9eb18099894b 100644
--- a/llvm/lib/Target/RISCV/RISCV.h
+++ b/llvm/lib/Target/RISCV/RISCV.h
@@ -18,13 +18,8 @@
 #include "llvm/Target/TargetMachine.h"
 
 namespace llvm {
-class AsmPrinter;
 class FunctionPass;
 class InstructionSelector;
-class MCInst;
-class MCOperand;
-class MachineInstr;
-class MachineOperand;
 class PassRegistry;
 class RISCVRegisterBankInfo;
 class RISCVSubtarget;
-- 
GitLab


From fdd1da3f36e2a6911c0beea1d69c62bc77d8cb98 Mon Sep 17 00:00:00 2001
From: Daniil Kovalev <dkovalev@accesssoftek.com>
Date: Sun, 10 Dec 2023 22:28:48 +0300
Subject: [PATCH 060/349] [NFC][test][llvm-readobj] Use single `#` for
 FileCheck directives (#74985)

Comments use `##`. Lit and FileCheck directives should use single `#`.
See
https://github.com/llvm/llvm-project/pull/72713#discussion_r1398788122.
---
 .../llvm-readobj/ELF/broken-dynamic-reloc.test     | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/llvm/test/tools/llvm-readobj/ELF/broken-dynamic-reloc.test b/llvm/test/tools/llvm-readobj/ELF/broken-dynamic-reloc.test
index f4899f6df651..9f18248e7921 100644
--- a/llvm/test/tools/llvm-readobj/ELF/broken-dynamic-reloc.test
+++ b/llvm/test/tools/llvm-readobj/ELF/broken-dynamic-reloc.test
@@ -102,7 +102,7 @@ ProgramHeaders:
 # RUN: llvm-readelf --dyn-relocations %t3 2>&1 | \
 # RUN:   FileCheck %s -DFILE=%t3 --check-prefix=INVALID-DT-RELAENT --implicit-check-not=warning:
 
-## INVALID-DT-RELAENT: warning: '[[FILE]]': invalid DT_RELASZ value (0x18) or DT_RELAENT value (0xff)
+# INVALID-DT-RELAENT: warning: '[[FILE]]': invalid DT_RELASZ value (0x18) or DT_RELAENT value (0xff)
 
 ## Show we print a warning for an invalid relocation table size stored in a DT_RELSZ entry.
 
@@ -112,7 +112,7 @@ ProgramHeaders:
 # RUN: llvm-readobj --dyn-relocations %t4a 2>&1 | FileCheck %s -DFILE=%t4a --check-prefix=INVALID-DT-RELSZ1
 # RUN: llvm-readelf --dyn-relocations %t4a 2>&1 | FileCheck %s -DFILE=%t4a --check-prefix=INVALID-DT-RELSZ1
 
-## INVALID-DT-RELSZ1: warning: '[[FILE]]': invalid DT_RELSZ value (0xff) or DT_RELENT value (0x18)
+# INVALID-DT-RELSZ1: warning: '[[FILE]]': invalid DT_RELSZ value (0xff) or DT_RELENT value (0x18)
 
 ## Case B: the DT_RELSZ has value of 0x251, what is too large, because the relocation table goes past the EOF.
 
@@ -127,7 +127,7 @@ ProgramHeaders:
 # RUN: llvm-readobj --dyn-relocations %t5 2>&1 | FileCheck %s -DFILE=%t5 --check-prefix=INVALID-DT-RELENT
 # RUN: llvm-readelf --dyn-relocations %t5 2>&1 | FileCheck %s -DFILE=%t5 --check-prefix=INVALID-DT-RELENT
 
-## INVALID-DT-RELENT: warning: '[[FILE]]': invalid DT_RELSZ value (0x18) or DT_RELENT value (0xff)
+# INVALID-DT-RELENT: warning: '[[FILE]]': invalid DT_RELSZ value (0x18) or DT_RELENT value (0xff)
 
 ## Show we print a warning for an invalid relocation table size stored in a DT_RELRSZ/DT_ANDROID_RELRSZ entry.
 # RUN: yaml2obj --docnum=2 -DRELTYPE=RELR -DTAG1=DT_RELRSZ -DTAG1VAL=0xFF -DTAG2=DT_RELRENT %s -o %t6
@@ -138,8 +138,8 @@ ProgramHeaders:
 # RUN: llvm-readobj --dyn-relocations %t7 2>&1 | FileCheck %s -DFILE=%t7 --check-prefix=INVALID-DT-ANDROID-RELRSZ
 # RUN: llvm-readelf --dyn-relocations %t7 2>&1 | FileCheck %s -DFILE=%t7 --check-prefix=INVALID-DT-ANDROID-RELRSZ
 
-## INVALID-DT-RELRSZ:         warning: '[[FILE]]': invalid DT_RELRSZ value (0xff) or DT_RELRENT value (0x18)
-## INVALID-DT-ANDROID-RELRSZ: warning: '[[FILE]]': invalid DT_ANDROID_RELRSZ value (0xff) or DT_ANDROID_RELRENT value (0x18)
+# INVALID-DT-RELRSZ:         warning: '[[FILE]]': invalid DT_RELRSZ value (0xff) or DT_RELRENT value (0x18)
+# INVALID-DT-ANDROID-RELRSZ: warning: '[[FILE]]': invalid DT_ANDROID_RELRSZ value (0xff) or DT_ANDROID_RELRENT value (0x18)
 
 ## Show we print a warning for an invalid relocation table entry size stored in a DT_RELRENT/DT_ANDROID_RELRENT entry.
 # RUN: yaml2obj --docnum=2 -DRELTYPE=RELR -DTAG1=DT_RELRSZ -DTAG2=DT_RELRENT -DTAG2VAL=0xFF %s -o %t8
@@ -149,8 +149,8 @@ ProgramHeaders:
 # RUN: llvm-readobj --dyn-relocations %t9 2>&1 | FileCheck %s -DFILE=%t9 --check-prefix=INVALID-DT-ANDROID-RELRENT
 # RUN: llvm-readelf --dyn-relocations %t9 2>&1 | FileCheck %s -DFILE=%t9 --check-prefix=INVALID-DT-ANDROID-RELRENT
 
-## INVALID-DT-RELRENT:         invalid DT_RELRSZ value (0x18) or DT_RELRENT value (0xff)
-## INVALID-DT-ANDROID-RELRENT: invalid DT_ANDROID_RELRSZ value (0x18) or DT_ANDROID_RELRENT value (0xff)
+# INVALID-DT-RELRENT:         invalid DT_RELRSZ value (0x18) or DT_RELRENT value (0xff)
+# INVALID-DT-ANDROID-RELRENT: invalid DT_ANDROID_RELRSZ value (0x18) or DT_ANDROID_RELRENT value (0xff)
 
 ## Show we print a warning for an invalid value of DT_PLTRELSZ, which describes the total size
 ## of the relocation entries associated with the procedure linkage table.
-- 
GitLab


From 2b019a785fb4cb921150a85d3616090287550d46 Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu@google.com>
Date: Sun, 10 Dec 2023 11:41:48 -0800
Subject: [PATCH 061/349] [ADT] Include bit.h instead of MathExtras.h (NFC)

---
 llvm/include/llvm/ADT/SparseBitVector.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/include/llvm/ADT/SparseBitVector.h b/llvm/include/llvm/ADT/SparseBitVector.h
index 1e00c1386187..7151af6146e6 100644
--- a/llvm/include/llvm/ADT/SparseBitVector.h
+++ b/llvm/include/llvm/ADT/SparseBitVector.h
@@ -15,8 +15,8 @@
 #ifndef LLVM_ADT_SPARSEBITVECTOR_H
 #define LLVM_ADT_SPARSEBITVECTOR_H
 
+#include "llvm/ADT/bit.h"
 #include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
 #include <cassert>
 #include <climits>
-- 
GitLab


From d57a26a71480454959e90715453407ef2084b141 Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu@google.com>
Date: Sun, 10 Dec 2023 11:58:52 -0800
Subject: [PATCH 062/349] [ARM] Include bit.h instead of MathExtras.h (NFC)

---
 llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp
index 62404f7add48..c62d17fd427a 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp
@@ -12,9 +12,9 @@
 //===----------------------------------------------------------------------===//
 
 #include "ARMUnwindOpAsm.h"
+#include "llvm/ADT/bit.h"
 #include "llvm/Support/ARMEHABI.h"
 #include "llvm/Support/LEB128.h"
-#include "llvm/Support/MathExtras.h"
 #include <cassert>
 
 using namespace llvm;
-- 
GitLab


From 65a18412ab26f92df133ca1ef3ff7ff7dbf3c5f8 Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu@google.com>
Date: Sun, 10 Dec 2023 12:12:54 -0800
Subject: [PATCH 063/349] [DirectoryWatcher] Include limits.h instead of
 MathExtras.h (NFC)

---
 clang/lib/DirectoryWatcher/linux/DirectoryWatcher-linux.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clang/lib/DirectoryWatcher/linux/DirectoryWatcher-linux.cpp b/clang/lib/DirectoryWatcher/linux/DirectoryWatcher-linux.cpp
index 9b3d2571f29f..beca9586988b 100644
--- a/clang/lib/DirectoryWatcher/linux/DirectoryWatcher-linux.cpp
+++ b/clang/lib/DirectoryWatcher/linux/DirectoryWatcher-linux.cpp
@@ -14,7 +14,6 @@
 #include "llvm/Support/AlignOf.h"
 #include "llvm/Support/Errno.h"
 #include "llvm/Support/Error.h"
-#include "llvm/Support/MathExtras.h"
 #include "llvm/Support/Path.h"
 #include <atomic>
 #include <condition_variable>
@@ -25,6 +24,7 @@
 #include <vector>
 
 #include <fcntl.h>
+#include <limits.h>
 #include <optional>
 #include <sys/epoll.h>
 #include <sys/inotify.h>
-- 
GitLab


From ac640c627c4ed4a9a89cb57f3f661c25bf38ed07 Mon Sep 17 00:00:00 2001
From: Nishant Mittal <nishantwrp@google.com>
Date: Mon, 11 Dec 2023 02:18:31 +0530
Subject: [PATCH 064/349] [libc][math] Ensure fputil::nextafter is called with
 correct type args (#75009)

Follow up to
https://github.com/llvm/llvm-project/pull/73698#discussion_r1411134482
---
 libc/src/__support/FPUtil/ManipulationFunctions.h | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/libc/src/__support/FPUtil/ManipulationFunctions.h b/libc/src/__support/FPUtil/ManipulationFunctions.h
index 9d3fd075be47..08adb074b121 100644
--- a/libc/src/__support/FPUtil/ManipulationFunctions.h
+++ b/libc/src/__support/FPUtil/ManipulationFunctions.h
@@ -144,10 +144,11 @@ LIBC_INLINE T ldexp(T x, int exp) {
   return normal;
 }
 
-template <
-    typename T, typename U,
-    cpp::enable_if_t<cpp::is_floating_point_v<T> && cpp::is_floating_point_v<U>,
-                     int> = 0>
+template <typename T, typename U,
+          cpp::enable_if_t<cpp::is_floating_point_v<T> &&
+                               cpp::is_floating_point_v<U> &&
+                               (sizeof(T) <= sizeof(U)),
+                           int> = 0>
 LIBC_INLINE T nextafter(T from, U to) {
   FPBits<T> from_bits(from);
   if (from_bits.is_nan())
@@ -157,6 +158,9 @@ LIBC_INLINE T nextafter(T from, U to) {
   if (to_bits.is_nan())
     return static_cast<T>(to);
 
+  // NOTE: This would work only if `U` has a greater or equal precision than
+  // `T`. Otherwise `from` could loose its precision and the following statement
+  // could incorrectly evaluate to `true`.
   if (static_cast<U>(from) == to)
     return static_cast<T>(to);
 
-- 
GitLab


From 8410ee4f0047a8f3760db01d2af1b8168a4e69f4 Mon Sep 17 00:00:00 2001
From: Daniil Kovalev <dkovalev@accesssoftek.com>
Date: Mon, 11 Dec 2023 00:28:23 +0300
Subject: [PATCH 065/349] [NFC][AArch64][ELF][PAC] Update AUTH relocation IDs
 (#74986)

https://github.com/ARM-software/abi-aa/pull/227 changes IDs of
`R_AARCH64_AUTH_ABS64` and `R_AARCH64_AUTH_RELATIVE` in PAuth ABI
specification from draft ones (`0xe100` and `0xe200`) to final ones
(`0x244` and `0x411`).

This patch changes the values in llvm correspondingly.
---
 .../llvm/BinaryFormat/ELFRelocs/AArch64.def      |  4 ++--
 llvm/test/MC/AArch64/elf-reloc-ptrauth.s         | 16 ++++++++--------
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/llvm/include/llvm/BinaryFormat/ELFRelocs/AArch64.def b/llvm/include/llvm/BinaryFormat/ELFRelocs/AArch64.def
index b8ab5113bedf..30375de420e3 100644
--- a/llvm/include/llvm/BinaryFormat/ELFRelocs/AArch64.def
+++ b/llvm/include/llvm/BinaryFormat/ELFRelocs/AArch64.def
@@ -121,6 +121,7 @@ ELF_RELOC(R_AARCH64_TLSLE_LDST128_TPREL_LO12,        0x23a)
 ELF_RELOC(R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC,     0x23b)
 ELF_RELOC(R_AARCH64_TLSLD_LDST128_DTPREL_LO12,       0x23c)
 ELF_RELOC(R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC,    0x23d)
+ELF_RELOC(R_AARCH64_AUTH_ABS64,                      0x244)
 // Dynamic relocations start
 ELF_RELOC(R_AARCH64_COPY,                            0x400)
 ELF_RELOC(R_AARCH64_GLOB_DAT,                        0x401)
@@ -134,8 +135,7 @@ ELF_RELOC(R_AARCH64_TLS_DTPREL64,                    0x405)
 ELF_RELOC(R_AARCH64_TLS_TPREL64,                     0x406)
 ELF_RELOC(R_AARCH64_TLSDESC,                         0x407)
 ELF_RELOC(R_AARCH64_IRELATIVE,                       0x408)
-ELF_RELOC(R_AARCH64_AUTH_ABS64,                      0xe100)
-ELF_RELOC(R_AARCH64_AUTH_RELATIVE,                   0xe200)
+ELF_RELOC(R_AARCH64_AUTH_RELATIVE,                   0x411)
 
 // ELF_RELOC(R_AARCH64_P32_NONE,                         0)
 ELF_RELOC(R_AARCH64_P32_ABS32,                       0x001)
diff --git a/llvm/test/MC/AArch64/elf-reloc-ptrauth.s b/llvm/test/MC/AArch64/elf-reloc-ptrauth.s
index 1ce008117ac3..3bd8f5c19932 100644
--- a/llvm/test/MC/AArch64/elf-reloc-ptrauth.s
+++ b/llvm/test/MC/AArch64/elf-reloc-ptrauth.s
@@ -5,14 +5,14 @@
 
 // RELOC: Relocation section '.rela.test' at offset 0x230 contains 8 entries:
 // RELOC-NEXT:  Offset Info Type Symbol's Value Symbol's Name + Addend
-// RELOC-NEXT: 0000000000000000 000000010000e100 R_AARCH64_AUTH_ABS64 0000000000000000 .helper + 0
-// RELOC-NEXT: 0000000000000010 000000080000e100 R_AARCH64_AUTH_ABS64 0000000000000000 _g1 + 0
-// RELOC-NEXT: 0000000000000020 000000090000e100 R_AARCH64_AUTH_ABS64 0000000000000000 _g2 + 0
-// RELOC-NEXT: 0000000000000030 0000000a0000e100 R_AARCH64_AUTH_ABS64 0000000000000000 _g3 + 0
-// RELOC-NEXT: 0000000000000040 0000000b0000e100 R_AARCH64_AUTH_ABS64 0000000000000000 _g4 + 7
-// RELOC-NEXT: 0000000000000050 0000000c0000e100 R_AARCH64_AUTH_ABS64 0000000000000000 _g5 - 3
-// RELOC-NEXT: 0000000000000060 000000020000e100 R_AARCH64_AUTH_ABS64 0000000000000000 _g 6 + 0
-// RELOC-NEXT: 0000000000000070 0000000d0000e100 R_AARCH64_AUTH_ABS64 0000000000000000 _g 7 + 7
+// RELOC-NEXT: 0000000000000000 0000000100000244 R_AARCH64_AUTH_ABS64 0000000000000000 .helper + 0
+// RELOC-NEXT: 0000000000000010 0000000800000244 R_AARCH64_AUTH_ABS64 0000000000000000 _g1 + 0
+// RELOC-NEXT: 0000000000000020 0000000900000244 R_AARCH64_AUTH_ABS64 0000000000000000 _g2 + 0
+// RELOC-NEXT: 0000000000000030 0000000a00000244 R_AARCH64_AUTH_ABS64 0000000000000000 _g3 + 0
+// RELOC-NEXT: 0000000000000040 0000000b00000244 R_AARCH64_AUTH_ABS64 0000000000000000 _g4 + 7
+// RELOC-NEXT: 0000000000000050 0000000c00000244 R_AARCH64_AUTH_ABS64 0000000000000000 _g5 - 3
+// RELOC-NEXT: 0000000000000060 0000000200000244 R_AARCH64_AUTH_ABS64 0000000000000000 _g 6 + 0
+// RELOC-NEXT: 0000000000000070 0000000d00000244 R_AARCH64_AUTH_ABS64 0000000000000000 _g 7 + 7
 
 // RELOC: Hex dump of section '.test':
 //                VVVVVVVV addend, not needed for rela
-- 
GitLab


From 774295ca1d5ff752cb478b61f22a5b1dbe33074f Mon Sep 17 00:00:00 2001
From: "Stephan T. Lavavej" <stl@nuwen.net>
Date: Sun, 10 Dec 2023 13:41:30 -0800
Subject: [PATCH 066/349] [libc++][test] Fix MSVC warnings with `static_cast`s
 (#74962)

Found while running libc++'s tests with MSVC's STL.

*
`libcxx/test/std/algorithms/alg.modifying.operations/alg.unique/ranges_unique_copy.pass.cpp`
  + Fix MSVC "warning C4389: '`==`': signed/unsigned mismatch".
+ This was x86-specific for me. The LHS is `int` and the RHS is
`size_t`. We know the `array`'s size, so `static_cast<int>` is certainly
safe, and this matches the following `numberOfProj` comparisons.
*
`libcxx/test/std/containers/sequences/insert_range_sequence_containers.h`
+ Fix MSVC "warning C4267: 'argument': conversion from '`size_t`' to
'`const int`', possible loss of data".
+ `test_case.index` is `size_t`:
https://github.com/llvm/llvm-project/blob/b85f1f9b182234ba366d78ae2174a149e44d08c1/libcxx/test/std/containers/insert_range_helpers.h#L65-L68
+ But the container's `difference_type` is `int`:
https://github.com/llvm/llvm-project/blob/b85f1f9b182234ba366d78ae2174a149e44d08c1/libcxx/test/support/test_allocator.h#L65-L76
  + I introduced an alias `D` to make the long line more readable.
*
`libcxx/test/std/containers/unord/unord.map/eq.different_hash.pass.cpp`
*
`libcxx/test/std/containers/unord/unord.multimap/eq.different_hash.pass.cpp`
*
`libcxx/test/std/containers/unord/unord.multiset/eq.different_hash.pass.cpp`
*
`libcxx/test/std/containers/unord/unord.set/eq.different_hash.pass.cpp`
+ Fix MSVC "warning C6297: Arithmetic overflow. Results might not be an
expected value."
+ This warning is almost annoying enough to outright disable, but we use
similar `static_cast`s to deal with sign/truncation warnings elsewhere,
because there's some value in ensuring that product code is clean with
respect to these warnings. If there were many more occurrences, then
disabling the warning would be appropriate.
+ Cleanup: Change 2 inconsistently unqualified occurrences of `size_t`
to `std::size_t`.
*
`libcxx/test/std/containers/views/mdspan/layout_stride/index_operator.pass.cpp`
+ Fix MSVC "warning C4244: 'initializing': conversion from '`__int64`'
to '`size_t`', possible loss of data".
+ This was x86-specific for me. The `args` are indeed `int64_t`, and
we're storing the result in `size_t`, so we should cast.
* `libcxx/test/std/ranges/range.utility/range.utility.conv/container.h`
+ Fix MSVC "warning C4244: 'initializing': conversion from '`ptrdiff_t`'
to '`int`', possible loss of data".
+ Fix MSVC "warning C4267: 'initializing': conversion from '`size_t`' to
'`int`', possible loss of data".
+ We're initializing `int size_`, so we should explicitly cast from
pointer subtraction and `std::ranges::size`.
*
`libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.create/allocate_shared_for_overwrite.pass.cpp`
*
`libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.create/make_shared_for_overwrite.pass.cpp`
*
`libcxx/test/std/utilities/smartptr/unique.ptr/unique.ptr.create/make_unique_for_overwrite.default_init.pass.cpp`
+ Fix MSVC "warning C4309: 'initializing': truncation of constant
value".
+ MSVC emits this warning because `0xDE` is outside the range of `char`
(signed by default in our implementation).
* `libcxx/test/support/concat_macros.h`
+ Fix MSVC "warning C4244: 'argument': conversion from '`char16_t`' to
'`const char`', possible loss of data".
+ Fix MSVC "warning C4244: 'argument': conversion from '`unsigned int`'
to '`const char`', possible loss of data".
  + This code was very recently introduced by @mordante in #73395.
---
 .../alg.unique/ranges_unique_copy.pass.cpp    |  4 ++--
 .../insert_range_sequence_containers.h        |  3 ++-
 .../unord.map/eq.different_hash.pass.cpp      |  4 ++--
 .../unord.multimap/eq.different_hash.pass.cpp |  4 ++--
 .../unord.multiset/eq.different_hash.pass.cpp |  4 ++--
 .../unord.set/eq.different_hash.pass.cpp      |  8 ++++----
 .../layout_stride/index_operator.pass.cpp     | 10 +++++-----
 .../range.utility.conv/container.h            |  6 +++---
 .../allocate_shared_for_overwrite.pass.cpp    |  2 +-
 .../make_shared_for_overwrite.pass.cpp        |  2 +-
 ...unique_for_overwrite.default_init.pass.cpp |  2 +-
 libcxx/test/support/concat_macros.h           | 20 +++++++++----------
 12 files changed, 35 insertions(+), 34 deletions(-)

diff --git a/libcxx/test/std/algorithms/alg.modifying.operations/alg.unique/ranges_unique_copy.pass.cpp b/libcxx/test/std/algorithms/alg.modifying.operations/alg.unique/ranges_unique_copy.pass.cpp
index b84600b92c2b..a4cf97069c96 100644
--- a/libcxx/test/std/algorithms/alg.modifying.operations/alg.unique/ranges_unique_copy.pass.cpp
+++ b/libcxx/test/std/algorithms/alg.modifying.operations/alg.unique/ranges_unique_copy.pass.cpp
@@ -418,7 +418,7 @@ constexpr bool test() {
       assert(std::ranges::equal(out, expected));
       assert(base(result.in) == in.end());
       assert(base(result.out) == out.end());
-      assert(numberOfComp == in.size() - 1);
+      assert(numberOfComp == static_cast<int>(in.size() - 1));
       assert(numberOfProj <= static_cast<int>(2 * (in.size() - 1)));
     }
     // range overload
@@ -434,7 +434,7 @@ constexpr bool test() {
       assert(std::ranges::equal(out, expected));
       assert(base(result.in) == in.end());
       assert(base(result.out) == out.end());
-      assert(numberOfComp == in.size() - 1);
+      assert(numberOfComp == static_cast<int>(in.size() - 1));
       assert(numberOfProj <= static_cast<int>(2 * (in.size() - 1)));
     }
   }
diff --git a/libcxx/test/std/containers/sequences/insert_range_sequence_containers.h b/libcxx/test/std/containers/sequences/insert_range_sequence_containers.h
index b77b2510eae2..352ee474cae7 100644
--- a/libcxx/test/std/containers/sequences/insert_range_sequence_containers.h
+++ b/libcxx/test/std/containers/sequences/insert_range_sequence_containers.h
@@ -427,7 +427,8 @@ template <> constexpr TestCase<int> FullContainer_End_LongRange<bool> {
 template <class Container, class Iter, class Sent, class Validate>
 constexpr void test_sequence_insert_range(Validate validate) {
   using T = typename Container::value_type;
-  auto get_pos = [](auto& c, auto& test_case) { return std::ranges::next(c.begin(), test_case.index); };
+  using D      = typename Container::difference_type;
+  auto get_pos = [](auto& c, auto& test_case) { return std::ranges::next(c.begin(), static_cast<D>(test_case.index)); };
 
   auto test = [&](auto& test_case) {
     Container c(test_case.initial.begin(), test_case.initial.end());
diff --git a/libcxx/test/std/containers/unord/unord.map/eq.different_hash.pass.cpp b/libcxx/test/std/containers/unord/unord.map/eq.different_hash.pass.cpp
index 52a806f04d72..94de7589eb06 100644
--- a/libcxx/test/std/containers/unord/unord.map/eq.different_hash.pass.cpp
+++ b/libcxx/test/std/containers/unord/unord.map/eq.different_hash.pass.cpp
@@ -36,7 +36,7 @@ std::size_t hash_neg(T val) {
 }
 template <class T>
 std::size_t hash_scale(T val) {
-  return val << 1;
+  return static_cast<std::size_t>(val << 1);
 }
 template <class T>
 std::size_t hash_even(T val) {
@@ -57,7 +57,7 @@ std::size_t hash_neg(T* val) {
 }
 template <class T>
 std::size_t hash_scale(T* val) {
-  return *val << 1;
+  return static_cast<std::size_t>(*val << 1);
 }
 template <class T>
 std::size_t hash_even(T* val) {
diff --git a/libcxx/test/std/containers/unord/unord.multimap/eq.different_hash.pass.cpp b/libcxx/test/std/containers/unord/unord.multimap/eq.different_hash.pass.cpp
index 2644c9657644..0aafb401d42c 100644
--- a/libcxx/test/std/containers/unord/unord.multimap/eq.different_hash.pass.cpp
+++ b/libcxx/test/std/containers/unord/unord.multimap/eq.different_hash.pass.cpp
@@ -37,7 +37,7 @@ std::size_t hash_neg(T val) {
 }
 template <class T>
 std::size_t hash_scale(T val) {
-  return val << 1;
+  return static_cast<std::size_t>(val << 1);
 }
 template <class T>
 std::size_t hash_even(T val) {
@@ -58,7 +58,7 @@ std::size_t hash_neg(T* val) {
 }
 template <class T>
 std::size_t hash_scale(T* val) {
-  return *val << 1;
+  return static_cast<std::size_t>(*val << 1);
 }
 template <class T>
 std::size_t hash_even(T* val) {
diff --git a/libcxx/test/std/containers/unord/unord.multiset/eq.different_hash.pass.cpp b/libcxx/test/std/containers/unord/unord.multiset/eq.different_hash.pass.cpp
index 9f53e8d79e86..5b8f11e92927 100644
--- a/libcxx/test/std/containers/unord/unord.multiset/eq.different_hash.pass.cpp
+++ b/libcxx/test/std/containers/unord/unord.multiset/eq.different_hash.pass.cpp
@@ -36,7 +36,7 @@ std::size_t hash_neg(T val) {
 }
 template <class T>
 std::size_t hash_scale(T val) {
-  return val << 1;
+  return static_cast<std::size_t>(val << 1);
 }
 template <class T>
 std::size_t hash_even(T val) {
@@ -57,7 +57,7 @@ std::size_t hash_neg(T* val) {
 }
 template <class T>
 std::size_t hash_scale(T* val) {
-  return *val << 1;
+  return static_cast<std::size_t>(*val << 1);
 }
 template <class T>
 std::size_t hash_even(T* val) {
diff --git a/libcxx/test/std/containers/unord/unord.set/eq.different_hash.pass.cpp b/libcxx/test/std/containers/unord/unord.set/eq.different_hash.pass.cpp
index a763c7fee623..3cb4815a5bcb 100644
--- a/libcxx/test/std/containers/unord/unord.set/eq.different_hash.pass.cpp
+++ b/libcxx/test/std/containers/unord/unord.set/eq.different_hash.pass.cpp
@@ -36,7 +36,7 @@ std::size_t hash_neg(T val) {
 }
 template <class T>
 std::size_t hash_scale(T val) {
-  return val << 1;
+  return static_cast<std::size_t>(val << 1);
 }
 template <class T>
 std::size_t hash_even(T val) {
@@ -56,11 +56,11 @@ std::size_t hash_neg(T* val) {
   return std::numeric_limits<T>::max() - *val;
 }
 template <class T>
-size_t hash_scale(T* val) {
-  return *val << 1;
+std::size_t hash_scale(T* val) {
+  return static_cast<std::size_t>(*val << 1);
 }
 template <class T>
-size_t hash_even(T* val) {
+std::size_t hash_even(T* val) {
   return *val & 1 ? 1 : 0;
 }
 
diff --git a/libcxx/test/std/containers/views/mdspan/layout_stride/index_operator.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_stride/index_operator.pass.cpp
index 01278e907671..30281a8d922d 100644
--- a/libcxx/test/std/containers/views/mdspan/layout_stride/index_operator.pass.cpp
+++ b/libcxx/test/std/containers/views/mdspan/layout_stride/index_operator.pass.cpp
@@ -53,10 +53,10 @@ constexpr void iterate_stride(M m, const std::array<int, M::extents_type::rank()
   constexpr int r = static_cast<int>(M::extents_type::rank()) - 1 - static_cast<int>(sizeof...(Args));
   if constexpr (-1 == r) {
     ASSERT_NOEXCEPT(m(args...));
-    size_t expected_val = [&]<size_t... Pos>(std::index_sequence<Pos...>) {
+    std::size_t expected_val = static_cast<std::size_t>([&]<std::size_t... Pos>(std::index_sequence<Pos...>) {
       return ((args * strides[Pos]) + ... + 0);
-    }(std::make_index_sequence<M::extents_type::rank()>());
-    assert(expected_val == static_cast<size_t>(m(args...)));
+    }(std::make_index_sequence<M::extents_type::rank()>()));
+    assert(expected_val == static_cast<std::size_t>(m(args...)));
   } else {
     for (typename M::index_type i = 0; i < m.extents().extent(r); i++) {
       iterate_stride(m, strides, i, args...);
@@ -73,7 +73,7 @@ constexpr void test_iteration(std::array<int, E::rank()> strides, Args... args)
 }
 
 constexpr bool test() {
-  constexpr size_t D = std::dynamic_extent;
+  constexpr std::size_t D = std::dynamic_extent;
   test_iteration<std::extents<int>>(std::array<int, 0>{});
   test_iteration<std::extents<unsigned, D>>(std::array<int, 1>{2}, 1);
   test_iteration<std::extents<unsigned, D>>(std::array<int, 1>{3}, 7);
@@ -102,7 +102,7 @@ constexpr bool test() {
 }
 
 constexpr bool test_large() {
-  constexpr size_t D = std::dynamic_extent;
+  constexpr std::size_t D = std::dynamic_extent;
   test_iteration<std::extents<int64_t, D, 8, D, D>>(std::array<int, 4>{2000, 2, 20, 200}, 7, 9, 10);
   test_iteration<std::extents<int64_t, D, 8, 1, D>>(std::array<int, 4>{2000, 20, 20, 200}, 7, 10);
   return true;
diff --git a/libcxx/test/std/ranges/range.utility/range.utility.conv/container.h b/libcxx/test/std/ranges/range.utility/range.utility.conv/container.h
index fafccacd456d..ca89e3757aff 100644
--- a/libcxx/test/std/ranges/range.utility/range.utility.conv/container.h
+++ b/libcxx/test/std/ranges/range.utility/range.utility.conv/container.h
@@ -38,7 +38,7 @@ struct Container {
 
   constexpr explicit Container(std::ranges::input_range auto&& in)
     requires(Rank >= CtrChoice::DirectCtr)
-      : ctr_choice(CtrChoice::DirectCtr), size_(std::ranges::size(in)) {
+      : ctr_choice(CtrChoice::DirectCtr), size_(static_cast<int>(std::ranges::size(in))) {
     std::ranges::copy(in, begin());
   }
 
@@ -54,7 +54,7 @@ struct Container {
 
   constexpr Container(std::from_range_t, std::ranges::input_range auto&& in)
     requires(Rank >= CtrChoice::FromRangeT)
-      : ctr_choice(CtrChoice::FromRangeT), size_(std::ranges::size(in)) {
+      : ctr_choice(CtrChoice::FromRangeT), size_(static_cast<int>(std::ranges::size(in))) {
     std::ranges::copy(in, begin());
   }
 
@@ -70,7 +70,7 @@ struct Container {
   template <class Iter>
   constexpr Container(Iter b, Iter e)
     requires(Rank >= CtrChoice::BeginEndPair)
-      : ctr_choice(CtrChoice::BeginEndPair), size_(e - b) {
+      : ctr_choice(CtrChoice::BeginEndPair), size_(static_cast<int>(e - b)) {
     std::ranges::copy(b, e, begin());
   }
 
diff --git a/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.create/allocate_shared_for_overwrite.pass.cpp b/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.create/allocate_shared_for_overwrite.pass.cpp
index 27ff3cd56374..e6e063304453 100644
--- a/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.create/allocate_shared_for_overwrite.pass.cpp
+++ b/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.create/allocate_shared_for_overwrite.pass.cpp
@@ -156,7 +156,7 @@ void testAllocatorOperationsCalled() {
 
 template <class T>
 struct AllocatorWithPattern {
-  constexpr static char pattern = 0xDE;
+  constexpr static char pattern = static_cast<char>(0xDE);
 
   using value_type = T;
 
diff --git a/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.create/make_shared_for_overwrite.pass.cpp b/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.create/make_shared_for_overwrite.pass.cpp
index 21e1786f0158..459b5a708cd4 100644
--- a/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.create/make_shared_for_overwrite.pass.cpp
+++ b/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.create/make_shared_for_overwrite.pass.cpp
@@ -56,7 +56,7 @@ static_assert(!HasMakeSharedForOverwrite<Foo[]>);
 static_assert(!HasMakeSharedForOverwrite<int[], std::size_t, int>);
 static_assert(!HasMakeSharedForOverwrite<Foo[], std::size_t, int>);
 
-constexpr char pattern = 0xDE;
+constexpr char pattern = static_cast<char>(0xDE);
 
 void* operator new(std::size_t count) {
   void* ptr = std::malloc(count);
diff --git a/libcxx/test/std/utilities/smartptr/unique.ptr/unique.ptr.create/make_unique_for_overwrite.default_init.pass.cpp b/libcxx/test/std/utilities/smartptr/unique.ptr/unique.ptr.create/make_unique_for_overwrite.default_init.pass.cpp
index 8011a37be08e..a1373ac3ac80 100644
--- a/libcxx/test/std/utilities/smartptr/unique.ptr/unique.ptr.create/make_unique_for_overwrite.default_init.pass.cpp
+++ b/libcxx/test/std/utilities/smartptr/unique.ptr/unique.ptr.create/make_unique_for_overwrite.default_init.pass.cpp
@@ -23,7 +23,7 @@
 #include <cstdlib>
 #include <memory>
 
-constexpr char pattern = 0xDE;
+constexpr char pattern = static_cast<char>(0xDE);
 
 void* operator new(std::size_t count) {
   void* ptr = std::malloc(count);
diff --git a/libcxx/test/support/concat_macros.h b/libcxx/test/support/concat_macros.h
index 57c5f5e0632e..d7340b8faf6e 100644
--- a/libcxx/test/support/concat_macros.h
+++ b/libcxx/test/support/concat_macros.h
@@ -52,14 +52,14 @@ template <class OutIt>
   requires std::output_iterator<OutIt, const char&>
 void test_encode(OutIt& out_it, char16_t value) {
   if (value < 0x80)
-    *out_it++ = value;
+    *out_it++ = static_cast<char>(value);
   else if (value < 0x800) {
-    *out_it++ = 0b11000000 | (value >> 6);
-    *out_it++ = 0b10000000 | (value & 0b00111111);
+    *out_it++ = static_cast<char>(0b11000000 | (value >> 6));
+    *out_it++ = static_cast<char>(0b10000000 | (value & 0b00111111));
   } else {
-    *out_it++ = 0b11100000 | (value >> 12);
-    *out_it++ = 0b10000000 | ((value) >> 6 & 0b00111111);
-    *out_it++ = 0b10000000 | (value & 0b00111111);
+    *out_it++ = static_cast<char>(0b11100000 | (value >> 12));
+    *out_it++ = static_cast<char>(0b10000000 | ((value) >> 6 & 0b00111111));
+    *out_it++ = static_cast<char>(0b10000000 | (value & 0b00111111));
   }
 }
 
@@ -69,10 +69,10 @@ void test_encode(OutIt& out_it, char32_t value) {
   if ((value & 0xffff0000) == 0)
     test_encode(out_it, static_cast<char16_t>(value));
   else {
-    *out_it++ = 0b11100000 | (value >> 18);
-    *out_it++ = 0b10000000 | ((value) >> 12 & 0b00111111);
-    *out_it++ = 0b10000000 | ((value) >> 6 & 0b00111111);
-    *out_it++ = 0b10000000 | (value & 0b00111111);
+    *out_it++ = static_cast<char>(0b11100000 | (value >> 18));
+    *out_it++ = static_cast<char>(0b10000000 | ((value) >> 12 & 0b00111111));
+    *out_it++ = static_cast<char>(0b10000000 | ((value) >> 6 & 0b00111111));
+    *out_it++ = static_cast<char>(0b10000000 | (value & 0b00111111));
   }
 }
 
-- 
GitLab


From b2cc4b994e5fb85053b1acedec5ea0d1d42e5ec4 Mon Sep 17 00:00:00 2001
From: "Stephan T. Lavavej" <stl@nuwen.net>
Date: Sun, 10 Dec 2023 13:46:40 -0800
Subject: [PATCH 067/349] [libc++][test] Fix more MSVC and Clang warnings
 (#74965)

Found while running libc++'s tests with MSVC's STL.

*
`libcxx/test/std/algorithms/alg.sorting/alg.heap.operations/sort.heap/ranges_sort_heap.pass.cpp`
+ Fix Clang `-Wunused-variable`, because `LIBCPP_ASSERT` expands to
nothing for MSVC's STL.
+ This is the same "always void-cast" change that #73437 applied to the
neighboring `complexity.pass.cpp`. I missed that
`ranges_sort_heap.pass.cpp` was also affected because we had disabled
this test.
*
`libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/buffered_reads.pass.cpp`
*
`libcxx/test/std/input.output/file.streams/fstreams/ofstream.members/buffered_writes.pass.cpp`
+ Fix MSVC "warning C4244: '`=`': conversion from '`__int64`' to
'`_Ty`', possible loss of data".
+ This is a valid warning, possibly the best one that MSVC found in this
entire saga. We're accumulating a `std::vector<std::streamsize>` and
storing the result in `std::streamsize total_size` but we actually have
to start with `std::streamsize{0}` or we'll truncate.
*
`libcxx/test/std/input.output/filesystems/fs.enum/enum.path.format.pass.cpp`
+ Fix Clang `-Wunused-local-typedef` because the following usage is
libc++-only.
+ I'm just expanding it at the point of use, and using the dedicated
`LIBCPP_STATIC_ASSERT` to keep the line length down.
*
`libcxx/test/std/input.output/syncstream/syncbuf/syncstream.syncbuf.assign/swap.pass.cpp`
+ Fix MSVC "warning C4242: 'argument': conversion from '`int`' to
'`const _Elem`', possible loss of data".
+ This is a valid warning (possibly the second-best) as `sputc()`
returns `int_type`. If `sputc()` returns something unexpected, we want
to know, so we should separately say `expected.push_back(CharT('B'))`.
*
`libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_align_nothrow.pass.cpp`
*
`libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_nothrow.pass.cpp`
  + Fix MSVC "warning C6001: Using uninitialized memory '`x`'."
  + [N4964](https://wg21.link/N4964) \[new.delete.single\]/12:
> *Effects:* The deallocation functions
(\[basic.stc.dynamic.deallocation\]) called by a *delete-expression*
(\[expr.delete\]) to render the value of `ptr` invalid.
  + \[basic.stc.general\]/4:
> When the end of the duration of a region of storage is reached, the
values of all pointers representing the address of any part of that
region of storage become invalid pointer values (\[basic.compound\]).
Indirection through an invalid pointer value and passing an invalid
pointer value to a deallocation function have undefined behavior. Any
other use of an invalid pointer value has implementation-defined
behavior.
+ In certain configurations, after `delete x;` MSVC will consider `x` to
be radioactive (and in other configurations, it'll physically null out
`x` as a safety measure). We can copy it into `old_x` before deletion,
which the implementation finds acceptable.
*
`libcxx/test/std/ranges/range.adaptors/range.elements/general.pass.cpp`
*
`libcxx/test/std/ranges/range.adaptors/range.elements/iterator/deref.pass.cpp`
+ Fix MSVC "warning C4242: 'initializing': conversion from '`_Ty`' to
'`_Ty`', possible loss of data".
+ This was being emitted in `pair` and `tuple`'s perfect forwarding
constructors. Passing `short{1}` allows MSVC to see that no truncation
is happening.
*
`libcxx/test/std/ranges/range.adaptors/range.elements/iterator/member_types.compile.pass.cpp`
+ Fix MSVC "warning C4242: 'initializing': conversion from '`_Ty`' to
'`_Ty2`', possible loss of data".
+ Similarly, this was being emitted in `pair`'s perfect forwarding
constructor. After passing `short{1}`, I reduced repetition by relying
on CTAD. (I can undo that cleanup if it's stylistically undesirable.)
*
`libcxx/test/std/utilities/function.objects/refwrap/refwrap.const/type_conv_ctor.pass.cpp`
+ Fix MSVC "warning C4930: '`std::reference_wrapper<int> purr(void)`':
prototyped function not called (was a variable definition intended?)".
+ There's no reason for `purr()` to be locally declared (aside from
isolating it to a narrow scope, which has minimal benefits); it can be
declared like `meow()` above. :smile_cat:
*
`libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.create/make_shared_for_overwrite.pass.cpp`
*
`libcxx/test/std/utilities/smartptr/unique.ptr/unique.ptr.create/make_unique_for_overwrite.default_init.pass.cpp`
  + Fix MSVC static analysis warnings when replacing `operator new`:
    ```
warning C28196: The requirement that '(_Param_(1)>0)?(return!=0):(1)' is
not satisfied. (The expression does not evaluate to true.)
warning C6387: 'return' could be '0': this does not adhere to the
specification for the function 'new'.
warning C6011: Dereferencing NULL pointer 'reinterpret_cast<char
*>ptr+i'.
    ```
+ All we need is a null check, which appears in other `operator new`
replacements:
https://github.com/llvm/llvm-project/blob/b85f1f9b182234ba366d78ae2174a149e44d08c1/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size.replace.pass.cpp#L27-L28
---
 .../sort.heap/ranges_sort_heap.pass.cpp       |  2 +-
 .../ifstream.members/buffered_reads.pass.cpp  |  4 ++--
 .../ofstream.members/buffered_writes.pass.cpp |  4 ++--
 .../fs.enum/enum.path.format.pass.cpp         |  4 +---
 .../syncstream.syncbuf.assign/swap.pass.cpp   |  3 ++-
 .../new.size.replace.indirect.pass.cpp        |  4 +++-
 .../new.size.replace.pass.cpp                 |  4 +++-
 ...new.size_nothrow.replace.indirect.pass.cpp |  4 +++-
 .../new.size.replace.pass.cpp                 |  4 +++-
 .../new.size_align_nothrow.pass.cpp           |  3 ++-
 .../new.size_nothrow.pass.cpp                 |  3 ++-
 ...new.size_nothrow.replace.indirect.pass.cpp |  4 +++-
 .../range.elements/general.pass.cpp           |  2 +-
 .../range.elements/iterator/deref.pass.cpp    |  4 ++--
 .../iterator/member_types.compile.pass.cpp    |  4 +---
 .../thread.thread.constr/F.pass.cpp           |  4 +++-
 .../refwrap.const/type_conv_ctor.pass.cpp     | 20 +++++++++----------
 .../make_shared_for_overwrite.pass.cpp        |  3 +++
 ...unique_for_overwrite.default_init.pass.cpp |  3 +++
 19 files changed, 49 insertions(+), 34 deletions(-)

diff --git a/libcxx/test/std/algorithms/alg.sorting/alg.heap.operations/sort.heap/ranges_sort_heap.pass.cpp b/libcxx/test/std/algorithms/alg.sorting/alg.heap.operations/sort.heap/ranges_sort_heap.pass.cpp
index 1153ed573d63..1e636ea9afac 100644
--- a/libcxx/test/std/algorithms/alg.sorting/alg.heap.operations/sort.heap/ranges_sort_heap.pass.cpp
+++ b/libcxx/test/std/algorithms/alg.sorting/alg.heap.operations/sort.heap/ranges_sort_heap.pass.cpp
@@ -238,6 +238,7 @@ void test_complexity() {
     const int debug_elements = std::min(100, n);
     // Multiplier 2 because of comp(a,b) comp(b, a) checks.
     const int debug_comparisons = 2 * (debug_elements + 1) * debug_elements;
+    (void)debug_comparisons;
     std::shuffle(first, last, g);
     std::make_heap(first, last, &MyInt::Comp);
     // The exact stats of our current implementation are recorded here.
@@ -247,7 +248,6 @@ void test_complexity() {
     LIBCPP_ASSERT(stats.moved <= 2 * n + n * logn);
 #if _LIBCPP_HARDENING_MODE != _LIBCPP_HARDENING_MODE_DEBUG
     LIBCPP_ASSERT(stats.compared <= n * logn);
-    (void)debug_comparisons;
 #else
     LIBCPP_ASSERT(stats.compared <= 2 * n * logn + debug_comparisons);
 #endif
diff --git a/libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/buffered_reads.pass.cpp b/libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/buffered_reads.pass.cpp
index d57b7c20a2da..ecc11f4999ff 100644
--- a/libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/buffered_reads.pass.cpp
+++ b/libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/buffered_reads.pass.cpp
@@ -44,7 +44,7 @@
 
 template <class BufferPolicy>
 void test_read(BufferPolicy policy, const std::vector<std::streamsize>& payload_sizes) {
-  std::streamsize total_size = std::accumulate(payload_sizes.begin(), payload_sizes.end(), 0);
+  std::streamsize total_size = std::accumulate(payload_sizes.begin(), payload_sizes.end(), std::streamsize{0});
   std::vector<char> data(total_size);
   for (std::size_t i = 0; i < data.size(); ++i) {
     data[i] = static_cast<char>(i % (1 << 8 * sizeof(char)));
@@ -99,7 +99,7 @@ void test_read(BufferPolicy policy, const std::vector<std::streamsize>& payload_
 #ifndef TEST_HAS_NO_WIDE_CHARACTERS
 template <class BufferPolicy>
 void test_read_codecvt(BufferPolicy policy, const std::vector<std::streamsize>& payload_sizes) {
-  std::streamsize total_size = std::accumulate(payload_sizes.begin(), payload_sizes.end(), 0);
+  std::streamsize total_size = std::accumulate(payload_sizes.begin(), payload_sizes.end(), std::streamsize{0});
   std::vector<wchar_t> data(total_size);
   for (std::size_t i = 0; i < data.size(); ++i) {
     data[i] = static_cast<wchar_t>(i);
diff --git a/libcxx/test/std/input.output/file.streams/fstreams/ofstream.members/buffered_writes.pass.cpp b/libcxx/test/std/input.output/file.streams/fstreams/ofstream.members/buffered_writes.pass.cpp
index e78207395051..b5bbb0ca2ee4 100644
--- a/libcxx/test/std/input.output/file.streams/fstreams/ofstream.members/buffered_writes.pass.cpp
+++ b/libcxx/test/std/input.output/file.streams/fstreams/ofstream.members/buffered_writes.pass.cpp
@@ -45,7 +45,7 @@
 template <class BufferPolicy>
 void test_write(BufferPolicy policy, const std::vector<std::streamsize>& payload_sizes) {
   std::size_t previously_written = 0;
-  std::streamsize total_size     = std::accumulate(payload_sizes.begin(), payload_sizes.end(), 0);
+  std::streamsize total_size     = std::accumulate(payload_sizes.begin(), payload_sizes.end(), std::streamsize{0});
   std::vector<char> data(total_size);
   for (std::size_t i = 0; i < data.size(); ++i) {
     data[i] = static_cast<char>(i % (1 << 8 * sizeof(char)));
@@ -97,7 +97,7 @@ void test_write(BufferPolicy policy, const std::vector<std::streamsize>& payload
 template <class BufferPolicy>
 void test_write_codecvt(BufferPolicy policy, const std::vector<std::streamsize>& payload_sizes) {
   std::size_t previously_written = 0;
-  std::streamsize total_size     = std::accumulate(payload_sizes.begin(), payload_sizes.end(), 0);
+  std::streamsize total_size     = std::accumulate(payload_sizes.begin(), payload_sizes.end(), std::streamsize{0});
   std::vector<wchar_t> data(total_size);
   for (std::size_t i = 0; i < data.size(); ++i) {
     data[i] = static_cast<wchar_t>(i);
diff --git a/libcxx/test/std/input.output/filesystems/fs.enum/enum.path.format.pass.cpp b/libcxx/test/std/input.output/filesystems/fs.enum/enum.path.format.pass.cpp
index 7f3022a3ce9b..ad0cdb092def 100644
--- a/libcxx/test/std/input.output/filesystems/fs.enum/enum.path.format.pass.cpp
+++ b/libcxx/test/std/input.output/filesystems/fs.enum/enum.path.format.pass.cpp
@@ -25,9 +25,7 @@ int main(int, char**) {
   typedef fs::path::format E;
   static_assert(std::is_enum<E>::value, "");
 
-  typedef std::underlying_type<E>::type UT;
-
-  LIBCPP_ONLY(static_assert(std::is_same<UT, unsigned char>::value, "")); // Implementation detail
+  LIBCPP_STATIC_ASSERT(std::is_same<std::underlying_type<E>::type, unsigned char>::value, ""); // Implementation detail
 
   static_assert(
           E::auto_format   != E::native_format &&
diff --git a/libcxx/test/std/input.output/syncstream/syncbuf/syncstream.syncbuf.assign/swap.pass.cpp b/libcxx/test/std/input.output/syncstream/syncbuf/syncstream.syncbuf.assign/swap.pass.cpp
index ba007da5a054..a236bf4752a0 100644
--- a/libcxx/test/std/input.output/syncstream/syncbuf/syncstream.syncbuf.assign/swap.pass.cpp
+++ b/libcxx/test/std/input.output/syncstream/syncbuf/syncstream.syncbuf.assign/swap.pass.cpp
@@ -75,7 +75,8 @@ static void test_short_write_after_swap() {
     sync_buf2.sputn(expected.data(), expected.size());
 
     sync_buf1.swap(sync_buf2);
-    expected.push_back(sync_buf1.sputc(CharT('B')));
+    sync_buf1.sputc(CharT('B'));
+    expected.push_back(CharT('B'));
     sync_buf2.sputc(CharT('Z'));
 
     assert(sstr1.str().empty());
diff --git a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size.replace.indirect.pass.cpp b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size.replace.indirect.pass.cpp
index 172b6cc2f294..f6f586a2b547 100644
--- a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size.replace.indirect.pass.cpp
+++ b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size.replace.indirect.pass.cpp
@@ -29,7 +29,9 @@ TEST_WORKAROUND_BUG_109234844_WEAK
 void* operator new(std::size_t s) TEST_THROW_SPEC(std::bad_alloc) {
     ++new_called;
     void* ret = std::malloc(s);
-    if (!ret) std::abort(); // placate MSVC's unchecked malloc warning
+    if (!ret) {
+      std::abort(); // placate MSVC's unchecked malloc warning (assert() won't silence it)
+    }
     return  ret;
 }
 
diff --git a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size.replace.pass.cpp b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size.replace.pass.cpp
index e352c00b4d0a..29e739d8515f 100644
--- a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size.replace.pass.cpp
+++ b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size.replace.pass.cpp
@@ -27,7 +27,9 @@ int delete_called = 0;
 void* operator new[](std::size_t s) TEST_THROW_SPEC(std::bad_alloc) {
     ++new_called;
     void* ret = std::malloc(s);
-    if (!ret) std::abort(); // placate MSVC's unchecked malloc warning
+    if (!ret) {
+      std::abort(); // placate MSVC's unchecked malloc warning (assert() won't silence it)
+    }
     return  ret;
 }
 
diff --git a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_nothrow.replace.indirect.pass.cpp b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_nothrow.replace.indirect.pass.cpp
index 8ad0292dcb5c..b26eec0324af 100644
--- a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_nothrow.replace.indirect.pass.cpp
+++ b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_nothrow.replace.indirect.pass.cpp
@@ -33,7 +33,9 @@ TEST_WORKAROUND_BUG_109234844_WEAK
 void* operator new[](std::size_t s) TEST_THROW_SPEC(std::bad_alloc) {
     ++new_called;
     void* ret = std::malloc(s);
-    if (!ret) std::abort(); // placate MSVC's unchecked malloc warning
+    if (!ret) {
+      std::abort(); // placate MSVC's unchecked malloc warning (assert() won't silence it)
+    }
     return ret;
 }
 
diff --git a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size.replace.pass.cpp b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size.replace.pass.cpp
index a03313e5872e..ab1cf5ea4644 100644
--- a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size.replace.pass.cpp
+++ b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size.replace.pass.cpp
@@ -25,7 +25,9 @@ int delete_called = 0;
 void* operator new(std::size_t s) TEST_THROW_SPEC(std::bad_alloc) {
     ++new_called;
     void* ret = std::malloc(s);
-    if (!ret) std::abort(); // placate MSVC's unchecked malloc warning
+    if (!ret) {
+      std::abort(); // placate MSVC's unchecked malloc warning (assert() won't silence it)
+    }
     return ret;
 }
 
diff --git a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_align_nothrow.pass.cpp b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_align_nothrow.pass.cpp
index 4e5d36cd7c6d..1c575729678d 100644
--- a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_align_nothrow.pass.cpp
+++ b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_align_nothrow.pass.cpp
@@ -60,8 +60,9 @@ int main(int, char**) {
         assert(reinterpret_cast<std::uintptr_t>(x) % alignof(TrackLifetimeOverAligned) == 0);
         assert(info.address_constructed == x);
 
+        const auto old_x = x;
         delete x;
-        assert(info.address_destroyed == x);
+        assert(info.address_destroyed == old_x);
     }
 
     return 0;
diff --git a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_nothrow.pass.cpp b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_nothrow.pass.cpp
index 398de0068aba..56ae8df43f66 100644
--- a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_nothrow.pass.cpp
+++ b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_nothrow.pass.cpp
@@ -50,8 +50,9 @@ int main(int, char**) {
         assert(x != nullptr);
         assert(info.address_constructed == x);
 
+        const auto old_x = x;
         delete x;
-        assert(info.address_destroyed == x);
+        assert(info.address_destroyed == old_x);
     }
 
     return 0;
diff --git a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_nothrow.replace.indirect.pass.cpp b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_nothrow.replace.indirect.pass.cpp
index 2ae0dfa4f1ab..35a601339ddd 100644
--- a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_nothrow.replace.indirect.pass.cpp
+++ b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_nothrow.replace.indirect.pass.cpp
@@ -28,7 +28,9 @@ TEST_WORKAROUND_BUG_109234844_WEAK
 void* operator new(std::size_t s) TEST_THROW_SPEC(std::bad_alloc) {
     ++new_called;
     void* ret = std::malloc(s);
-    if (!ret) std::abort(); // placate MSVC's unchecked malloc warning
+    if (!ret) {
+      std::abort(); // placate MSVC's unchecked malloc warning (assert() won't silence it)
+    }
     return ret;
 }
 
diff --git a/libcxx/test/std/ranges/range.adaptors/range.elements/general.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.elements/general.pass.cpp
index 78792ae54bdb..d5318ced73dc 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.elements/general.pass.cpp
+++ b/libcxx/test/std/ranges/range.adaptors/range.elements/general.pass.cpp
@@ -70,7 +70,7 @@ int main(int, char**) {
 
   // tuple
   {
-    std::tuple<short> tps[] = {{1}, {2}, {3}};
+    std::tuple<short> tps[] = {{short{1}}, {short{2}}, {short{3}}};
     auto ev                 = tps | std::views::elements<0>;
     auto expected           = {1, 2, 3};
     assert(std::ranges::equal(ev, expected));
diff --git a/libcxx/test/std/ranges/range.adaptors/range.elements/iterator/deref.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.elements/iterator/deref.pass.cpp
index d87a3e533920..f88091f42699 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.elements/iterator/deref.pass.cpp
+++ b/libcxx/test/std/ranges/range.adaptors/range.elements/iterator/deref.pass.cpp
@@ -50,7 +50,7 @@ constexpr void testValue(T t) {
 constexpr bool test() {
   // test tuple
   {
-    std::tuple<int, short, long> ts[] = {{1, 2, 3}, {4, 5, 6}};
+    std::tuple<int, short, long> ts[] = {{1, short{2}, 3}, {4, short{5}, 6}};
     testReference<0>(ts);
     testReference<1>(ts);
     testReference<2>(ts);
@@ -61,7 +61,7 @@ constexpr bool test() {
 
   // test pair
   {
-    std::pair<int, short> ps[] = {{1, 2}, {4, 5}};
+    std::pair<int, short> ps[] = {{1, short{2}}, {4, short{5}}};
     testReference<0>(ps);
     testReference<1>(ps);
     testValue<0>(ps[0]);
diff --git a/libcxx/test/std/ranges/range.adaptors/range.elements/iterator/member_types.compile.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.elements/iterator/member_types.compile.pass.cpp
index 9a76c2fcb70c..70d49c1304b5 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.elements/iterator/member_types.compile.pass.cpp
+++ b/libcxx/test/std/ranges/range.adaptors/range.elements/iterator/member_types.compile.pass.cpp
@@ -64,9 +64,7 @@ static_assert(std::same_as<ElementsIter<Range<contiguous_iterator<std::tuple<int
 static_assert(std::same_as<ElementsIter<Range<std::tuple<int>*>>::iterator_category, //
                            std::random_access_iterator_tag>);
 
-using Generator = decltype(std::views::iota(0, 1) | std::views::transform([](int) {
-                             return std::pair<int, short>{1, 1};
-                           }));
+using Generator = decltype(std::views::iota(0, 1) | std::views::transform([](int) { return std::pair{1, short{1}}; }));
 static_assert(std::ranges::random_access_range<Generator>);
 
 static_assert(std::same_as<ElementsIter<Generator>::iterator_category, //
diff --git a/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.constr/F.pass.cpp b/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.constr/F.pass.cpp
index fc3d5c122274..1c520652ba22 100644
--- a/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.constr/F.pass.cpp
+++ b/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.constr/F.pass.cpp
@@ -36,7 +36,9 @@ void* operator new(std::size_t s) TEST_THROW_SPEC(std::bad_alloc)
     } while (!throw_one.compare_exchange_weak(expected, expected - 1));
     ++outstanding_new;
     void* ret = std::malloc(s);
-    if (!ret) std::abort(); // placate MSVC's unchecked malloc warning
+    if (!ret) {
+      std::abort(); // placate MSVC's unchecked malloc warning (assert() won't silence it)
+    }
     return ret;
 }
 
diff --git a/libcxx/test/std/utilities/function.objects/refwrap/refwrap.const/type_conv_ctor.pass.cpp b/libcxx/test/std/utilities/function.objects/refwrap/refwrap.const/type_conv_ctor.pass.cpp
index 2759b921fabe..48c62ae7d45b 100644
--- a/libcxx/test/std/utilities/function.objects/refwrap/refwrap.const/type_conv_ctor.pass.cpp
+++ b/libcxx/test/std/utilities/function.objects/refwrap/refwrap.const/type_conv_ctor.pass.cpp
@@ -37,8 +37,9 @@ struct convertible_from_int {
 void meow(std::reference_wrapper<int>) {}
 void meow(convertible_from_int) {}
 
-int main(int, char**)
-{
+std::reference_wrapper<int> purr();
+
+int main(int, char**) {
   {
     convertible_to_int_ref t;
     std::reference_wrapper<convertible_to_int_ref> r(t);
@@ -54,21 +55,18 @@ int main(int, char**)
     ASSERT_NOEXCEPT(Ref(nothrow_convertible<true>()));
     ASSERT_NOT_NOEXCEPT(Ref(nothrow_convertible<false>()));
   }
-  {
-    meow(0);
-  }
-  {
-    extern std::reference_wrapper<int> purr();
-    ASSERT_SAME_TYPE(decltype(true ? purr() : 0), int);
-  }
+  meow(0);
+  ASSERT_SAME_TYPE(decltype(true ? purr() : 0), int);
 #if TEST_STD_VER > 14
   {
     int i = 0;
     std::reference_wrapper ri(i);
-    static_assert((std::is_same<decltype(ri), std::reference_wrapper<int>>::value), "" );
+    static_assert((std::is_same<decltype(ri), std::reference_wrapper<int>>::value), "");
+  }
+  {
     const int j = 0;
     std::reference_wrapper rj(j);
-    static_assert((std::is_same<decltype(rj), std::reference_wrapper<const int>>::value), "" );
+    static_assert((std::is_same<decltype(rj), std::reference_wrapper<const int>>::value), "");
   }
 #endif
 
diff --git a/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.create/make_shared_for_overwrite.pass.cpp b/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.create/make_shared_for_overwrite.pass.cpp
index 459b5a708cd4..96363060a7be 100644
--- a/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.create/make_shared_for_overwrite.pass.cpp
+++ b/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.create/make_shared_for_overwrite.pass.cpp
@@ -60,6 +60,9 @@ constexpr char pattern = static_cast<char>(0xDE);
 
 void* operator new(std::size_t count) {
   void* ptr = std::malloc(count);
+  if (!ptr) {
+    std::abort(); // placate MSVC's unchecked malloc warning (assert() won't silence it)
+  }
   for (std::size_t i = 0; i < count; ++i) {
     *(reinterpret_cast<char*>(ptr) + i) = pattern;
   }
diff --git a/libcxx/test/std/utilities/smartptr/unique.ptr/unique.ptr.create/make_unique_for_overwrite.default_init.pass.cpp b/libcxx/test/std/utilities/smartptr/unique.ptr/unique.ptr.create/make_unique_for_overwrite.default_init.pass.cpp
index a1373ac3ac80..3ac0ce962cfa 100644
--- a/libcxx/test/std/utilities/smartptr/unique.ptr/unique.ptr.create/make_unique_for_overwrite.default_init.pass.cpp
+++ b/libcxx/test/std/utilities/smartptr/unique.ptr/unique.ptr.create/make_unique_for_overwrite.default_init.pass.cpp
@@ -27,6 +27,9 @@ constexpr char pattern = static_cast<char>(0xDE);
 
 void* operator new(std::size_t count) {
   void* ptr = std::malloc(count);
+  if (!ptr) {
+    std::abort(); // placate MSVC's unchecked malloc warning (assert() won't silence it)
+  }
   for (std::size_t i = 0; i < count; ++i) {
     *(reinterpret_cast<char*>(ptr) + i) = pattern;
   }
-- 
GitLab


From 9bd32d78a9c8c51929f200ceefe735dc687ab10d Mon Sep 17 00:00:00 2001
From: paperchalice <liujunchang97@outlook.com>
Date: Mon, 11 Dec 2023 09:26:01 +0800
Subject: [PATCH 068/349] [CodeGen] Update DwarfEHPreparePass references in
 `CodeGenPassBuilder.h` (#74068)

Forgot to update the counterpart in `CodeGenPassBuilder.h`. Also Rename `dwarfehprepare` -> `dwarf-eh-prepare`.
---
 llvm/include/llvm/CodeGen/CodeGenPassBuilder.h               | 5 +++--
 llvm/include/llvm/CodeGen/MachinePassRegistry.def            | 2 +-
 llvm/lib/CodeGen/DwarfEHPrepare.cpp                          | 2 +-
 llvm/lib/Passes/PassRegistry.def                             | 2 +-
 llvm/test/CodeGen/Generic/opt-codegen-no-target-machine.ll   | 2 +-
 .../Mips/compactbranches/beqc-bnec-register-constraint.ll    | 4 ++--
 llvm/test/CodeGen/X86/dwarf-eh-prepare-dbg.ll                | 4 ++--
 llvm/test/CodeGen/X86/dwarf-eh-prepare.ll                    | 4 ++--
 llvm/test/CodeGen/X86/dwarf_eh_resume.ll                     | 4 ++--
 llvm/tools/opt/opt.cpp                                       | 3 ++-
 10 files changed, 17 insertions(+), 15 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
index 94a2d0c6477b..bb139ef2eb35 100644
--- a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
@@ -23,6 +23,7 @@
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Analysis/TypeBasedAliasAnalysis.h"
 #include "llvm/CodeGen/CallBrPrepare.h"
+#include "llvm/CodeGen/DwarfEHPrepare.h"
 #include "llvm/CodeGen/ExpandReductions.h"
 #include "llvm/CodeGen/InterleavedAccess.h"
 #include "llvm/CodeGen/MachinePassManager.h"
@@ -678,14 +679,14 @@ void CodeGenPassBuilder<Derived>::addPassesToHandleExceptions(
   case ExceptionHandling::DwarfCFI:
   case ExceptionHandling::ARM:
   case ExceptionHandling::AIX:
-    addPass(DwarfEHPass(getOptLevel()));
+    addPass(DwarfEHPreparePass(&TM));
     break;
   case ExceptionHandling::WinEH:
     // We support using both GCC-style and MSVC-style exceptions on Windows, so
     // add both preparation passes. Each pass will only actually run if it
     // recognizes the personality function.
     addPass(WinEHPreparePass());
-    addPass(DwarfEHPass(getOptLevel()));
+    addPass(DwarfEHPreparePass(&TM));
     break;
   case ExceptionHandling::Wasm:
     // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs
diff --git a/llvm/include/llvm/CodeGen/MachinePassRegistry.def b/llvm/include/llvm/CodeGen/MachinePassRegistry.def
index ceca04cd5ba3..e6e979a4582c 100644
--- a/llvm/include/llvm/CodeGen/MachinePassRegistry.def
+++ b/llvm/include/llvm/CodeGen/MachinePassRegistry.def
@@ -38,6 +38,7 @@ FUNCTION_ANALYSIS("targetir", TargetIRAnalysis,
 #endif
 FUNCTION_PASS("callbrprepare", CallBrPreparePass, ())
 FUNCTION_PASS("consthoist", ConstantHoistingPass, ())
+FUNCTION_PASS("dwarf-eh-prepare", DwarfEHPreparePass, (TM))
 FUNCTION_PASS("ee-instrument", EntryExitInstrumenterPass, (false))
 FUNCTION_PASS("expand-large-div-rem", ExpandLargeDivRemPass, ())
 FUNCTION_PASS("expand-large-fp-convert", ExpandLargeFpConvertPass, ())
@@ -123,7 +124,6 @@ DUMMY_FUNCTION_PASS("atomic-expand", AtomicExpandPass, ())
 DUMMY_FUNCTION_PASS("cfguard-check", CFGuardCheckPass, ())
 DUMMY_FUNCTION_PASS("cfguard-dispatch", CFGuardDispatchPass, ())
 DUMMY_FUNCTION_PASS("codegenprepare", CodeGenPreparePass, ())
-DUMMY_FUNCTION_PASS("dwarfehprepare", DwarfEHPass, ())
 DUMMY_FUNCTION_PASS("expandmemcmp", ExpandMemCmpPass, ())
 DUMMY_FUNCTION_PASS("gc-info-printer", GCInfoPrinterPass, ())
 DUMMY_FUNCTION_PASS("gc-lowering", GCLoweringPass, ())
diff --git a/llvm/lib/CodeGen/DwarfEHPrepare.cpp b/llvm/lib/CodeGen/DwarfEHPrepare.cpp
index a44aaf33c6a4..e7eb34d8e651 100644
--- a/llvm/lib/CodeGen/DwarfEHPrepare.cpp
+++ b/llvm/lib/CodeGen/DwarfEHPrepare.cpp
@@ -42,7 +42,7 @@
 
 using namespace llvm;
 
-#define DEBUG_TYPE "dwarfehprepare"
+#define DEBUG_TYPE "dwarf-eh-prepare"
 
 STATISTIC(NumResumesLowered, "Number of resume calls lowered");
 STATISTIC(NumCleanupLandingPadsUnreachable,
diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def
index c1641ea8b5b1..bf9622670ba5 100644
--- a/llvm/lib/Passes/PassRegistry.def
+++ b/llvm/lib/Passes/PassRegistry.def
@@ -302,7 +302,7 @@ FUNCTION_PASS("dot-dom-only", DomOnlyPrinter())
 FUNCTION_PASS("dot-post-dom", PostDomPrinter())
 FUNCTION_PASS("dot-post-dom-only", PostDomOnlyPrinter())
 FUNCTION_PASS("dse", DSEPass())
-FUNCTION_PASS("dwarfehprepare", DwarfEHPreparePass(TM))
+FUNCTION_PASS("dwarf-eh-prepare", DwarfEHPreparePass(TM))
 FUNCTION_PASS("expand-large-div-rem", ExpandLargeDivRemPass(TM))
 FUNCTION_PASS("expand-large-fp-convert", ExpandLargeFpConvertPass(TM))
 FUNCTION_PASS("fix-irreducible", FixIrreduciblePass())
diff --git a/llvm/test/CodeGen/Generic/opt-codegen-no-target-machine.ll b/llvm/test/CodeGen/Generic/opt-codegen-no-target-machine.ll
index 413f09ba55dd..b7f0e7d02a21 100644
--- a/llvm/test/CodeGen/Generic/opt-codegen-no-target-machine.ll
+++ b/llvm/test/CodeGen/Generic/opt-codegen-no-target-machine.ll
@@ -1,3 +1,3 @@
-; RUN: not --crash opt %s -dwarfehprepare -o - 2>&1 | FileCheck %s
+; RUN: not --crash opt %s -dwarf-eh-prepare -o - 2>&1 | FileCheck %s
 
 ; CHECK: Trying to construct TargetPassConfig without a target machine. Scheduling a CodeGen pass without a target triple set?
diff --git a/llvm/test/CodeGen/Mips/compactbranches/beqc-bnec-register-constraint.ll b/llvm/test/CodeGen/Mips/compactbranches/beqc-bnec-register-constraint.ll
index 4c8674d46e29..13e30676aa6f 100644
--- a/llvm/test/CodeGen/Mips/compactbranches/beqc-bnec-register-constraint.ll
+++ b/llvm/test/CodeGen/Mips/compactbranches/beqc-bnec-register-constraint.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mips -mcpu=mips32r6 -O1 -start-after=dwarfehprepare < %s | FileCheck %s
-; RUN: llc -march=mips64 -mcpu=mips64r6 -O1 -start-after=dwarfehprepare < %s | FileCheck %s
+; RUN: llc -march=mips -mcpu=mips32r6 -O1 -start-after=dwarf-eh-prepare < %s | FileCheck %s
+; RUN: llc -march=mips64 -mcpu=mips64r6 -O1 -start-after=dwarf-eh-prepare < %s | FileCheck %s
 
 
 ; beqc/bnec have the constraint that $rs < $rt && $rs != 0 && $rt != 0
diff --git a/llvm/test/CodeGen/X86/dwarf-eh-prepare-dbg.ll b/llvm/test/CodeGen/X86/dwarf-eh-prepare-dbg.ll
index 651e196a4ed7..0345b736e9e6 100644
--- a/llvm/test/CodeGen/X86/dwarf-eh-prepare-dbg.ll
+++ b/llvm/test/CodeGen/X86/dwarf-eh-prepare-dbg.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -mtriple=x86_64-linux-gnu -dwarfehprepare < %s | FileCheck %s
-; RUN: opt -S -mtriple=x86_64-linux-gnu -passes=dwarfehprepare < %s | FileCheck %s
+; RUN: opt -S -mtriple=x86_64-linux-gnu -dwarf-eh-prepare < %s | FileCheck %s
+; RUN: opt -S -mtriple=x86_64-linux-gnu -passes=dwarf-eh-prepare < %s | FileCheck %s
 
 ; PR57469: If _Unwind_Resume is defined in the same module and we have debug
 ; info, then the inserted _Unwind_Resume calls also need to have a dummy debug
diff --git a/llvm/test/CodeGen/X86/dwarf-eh-prepare.ll b/llvm/test/CodeGen/X86/dwarf-eh-prepare.ll
index 6778601cfbf6..dd27e7fe1411 100644
--- a/llvm/test/CodeGen/X86/dwarf-eh-prepare.ll
+++ b/llvm/test/CodeGen/X86/dwarf-eh-prepare.ll
@@ -1,5 +1,5 @@
-; RUN: opt -mtriple=x86_64-linux-gnu -dwarfehprepare -simplifycfg-require-and-preserve-domtree=1 -run-twice < %s -S | FileCheck %s
-; RUN: opt -mtriple=x86_64-linux-gnu -passes=dwarfehprepare -codegen-opt-level=2 -simplifycfg-require-and-preserve-domtree=1 -run-twice < %s -S | FileCheck %s
+; RUN: opt -mtriple=x86_64-linux-gnu -dwarf-eh-prepare -simplifycfg-require-and-preserve-domtree=1 -run-twice < %s -S | FileCheck %s
+; RUN: opt -mtriple=x86_64-linux-gnu -passes=dwarf-eh-prepare -codegen-opt-level=2 -simplifycfg-require-and-preserve-domtree=1 -run-twice < %s -S | FileCheck %s
 
 ; Check basic functionality of IR-to-IR DWARF EH preparation. This should
 ; eliminate resumes. This pass requires a TargetMachine, so we put it under X86
diff --git a/llvm/test/CodeGen/X86/dwarf_eh_resume.ll b/llvm/test/CodeGen/X86/dwarf_eh_resume.ll
index 90fad00b68bd..d66d89d16a39 100644
--- a/llvm/test/CodeGen/X86/dwarf_eh_resume.ll
+++ b/llvm/test/CodeGen/X86/dwarf_eh_resume.ll
@@ -1,5 +1,5 @@
-; RUN: opt -mtriple=x86_64-linux-gnu -dwarfehprepare -S %s | FileCheck %s
-; RUN: opt -mtriple=x86_64-linux-gnu -passes=dwarfehprepare -S %s | FileCheck %s
+; RUN: opt -mtriple=x86_64-linux-gnu -dwarf-eh-prepare -S %s | FileCheck %s
+; RUN: opt -mtriple=x86_64-linux-gnu -passes=dwarf-eh-prepare -S %s | FileCheck %s
 
 declare i32 @hoge(...)
 
diff --git a/llvm/tools/opt/opt.cpp b/llvm/tools/opt/opt.cpp
index 5e5e5ce233f3..50b36dc74267 100644
--- a/llvm/tools/opt/opt.cpp
+++ b/llvm/tools/opt/opt.cpp
@@ -339,7 +339,8 @@ static bool shouldPinPassToLegacyPM(StringRef Pass) {
       "nvptx-",  "mips-",  "lanai-", "hexagon-", "bpf-",    "avr-",
       "thumb2-", "arm-",   "si-",    "gcn-",     "amdgpu-", "aarch64-",
       "amdgcn-", "polly-", "riscv-", "dxil-"};
-  std::vector<StringRef> PassNameContain = {"ehprepare"};
+  // TODO: remove "ehprepare"
+  std::vector<StringRef> PassNameContain = {"-eh-prepare", "ehprepare"};
   std::vector<StringRef> PassNameExact = {
       "safe-stack",
       "cost-model",
-- 
GitLab


From 1d608fc755a3e15d0020f61c9535c9b730ab9dec Mon Sep 17 00:00:00 2001
From: Mircea Trofin <mtrofin@google.com>
Date: Sun, 10 Dec 2023 18:03:08 -0800
Subject: [PATCH 069/349] [NFC][InstrProf] Refactor InstrProfiling lowering
 pass (#74970)

Akin other passes - refactored the name to `InstrProfilingLoweringPass` to better communicate what it does, and split the pass part and the transformation part to avoid needing to initialize object state during `::run`.

A subsequent PR will move `InstrLowering` to the .cpp file and rename it to `InstrLowerer`.
---
 clang/lib/CodeGen/BackendUtil.cpp             |   2 +-
 clang/test/CodeGen/pgo-instrumentation.c      |   4 +-
 .../include/llvm/Transforms/Instrumentation.h |   3 +-
 .../Instrumentation/InstrProfiling.h          |  46 ++++---
 llvm/lib/Passes/PassBuilderPipelines.cpp      |   4 +-
 llvm/lib/Passes/PassRegistry.def              |   2 +-
 .../Instrumentation/InstrProfiling.cpp        | 126 ++++++++----------
 .../Instrumentation/Instrumentation.cpp       |   2 +-
 8 files changed, 97 insertions(+), 92 deletions(-)

diff --git a/clang/lib/CodeGen/BackendUtil.cpp b/clang/lib/CodeGen/BackendUtil.cpp
index 8c666e2cb463..77455c075cab 100644
--- a/clang/lib/CodeGen/BackendUtil.cpp
+++ b/clang/lib/CodeGen/BackendUtil.cpp
@@ -982,7 +982,7 @@ void EmitAssemblyHelper::RunOptimizationPipeline(
             getInstrProfOptions(CodeGenOpts, LangOpts))
       PB.registerPipelineStartEPCallback(
           [Options](ModulePassManager &MPM, OptimizationLevel Level) {
-            MPM.addPass(InstrProfiling(*Options, false));
+            MPM.addPass(InstrProfilingLoweringPass(*Options, false));
           });
 
     // TODO: Consider passing the MemoryProfileOutput to the pass builder via
diff --git a/clang/test/CodeGen/pgo-instrumentation.c b/clang/test/CodeGen/pgo-instrumentation.c
index a65c6712291b..c01658065497 100644
--- a/clang/test/CodeGen/pgo-instrumentation.c
+++ b/clang/test/CodeGen/pgo-instrumentation.c
@@ -3,7 +3,7 @@
 // Ensure Pass PGOInstrumentationGenPass is invoked.
 // RUN: %clang_cc1 -O2 -fprofile-instrument=llvm %s  -fdebug-pass-manager -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-PGOGENPASS-INVOKED-INSTR-GEN --check-prefix=CHECK-INSTRPROF
 // CHECK-PGOGENPASS-INVOKED-INSTR-GEN: Running pass: PGOInstrumentationGen on
-// CHECK-INSTRPROF: Running pass: InstrProfiling on
+// CHECK-INSTRPROF: Running pass: InstrProfilingLoweringPass on
 //
 // Ensure Pass PGOInstrumentationGenPass is not invoked.
 // RUN: %clang_cc1 -O2 -fprofile-instrument=clang %s -fdebug-pass-manager -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-PGOGENPASS-INVOKED-INSTR-GEN-CLANG
@@ -11,7 +11,7 @@
 
 // RUN: %clang_cc1 -O2 -fprofile-instrument=clang %s -fdebug-pass-manager -emit-llvm -o - 2>&1 | FileCheck %s --check-prefix=CHECK-CLANG-INSTRPROF
 // RUN: %clang_cc1 -O0 -fprofile-instrument=clang %s -fdebug-pass-manager -emit-llvm -o - 2>&1 | FileCheck %s --check-prefix=CHECK-CLANG-INSTRPROF
-// CHECK-CLANG-INSTRPROF: Running pass: InstrProfiling on
+// CHECK-CLANG-INSTRPROF: Running pass: InstrProfilingLoweringPass on
 
 // Ensure Pass PGOInstrumentationUsePass is invoked.
 // RUN: llvm-profdata merge -o %t.profdata %S/Inputs/pgotestir.profraw
diff --git a/llvm/include/llvm/Transforms/Instrumentation.h b/llvm/include/llvm/Transforms/Instrumentation.h
index bb1a0d446aa2..ea97ab2562a5 100644
--- a/llvm/include/llvm/Transforms/Instrumentation.h
+++ b/llvm/include/llvm/Transforms/Instrumentation.h
@@ -52,7 +52,8 @@ Comdat *getOrCreateFunctionComdat(Function &F, Triple &T);
 // Place global in a large section for x86-64 ELF binaries to mitigate
 // relocation overflow pressure. This can be be used for metadata globals that
 // aren't directly accessed by code, which has no performance impact.
-void setGlobalVariableLargeSection(Triple &TargetTriple, GlobalVariable &GV);
+void setGlobalVariableLargeSection(const Triple &TargetTriple,
+                                   GlobalVariable &GV);
 
 // Insert GCOV profiling instrumentation
 struct GCOVOptions {
diff --git a/llvm/include/llvm/Transforms/Instrumentation/InstrProfiling.h b/llvm/include/llvm/Transforms/Instrumentation/InstrProfiling.h
index c106e1651e80..89fa08685692 100644
--- a/llvm/include/llvm/Transforms/Instrumentation/InstrProfiling.h
+++ b/llvm/include/llvm/Transforms/Instrumentation/InstrProfiling.h
@@ -31,31 +31,46 @@ using LoadStorePair = std::pair<Instruction *, Instruction *>;
 /// Instrumentation based profiling lowering pass. This pass lowers
 /// the profile instrumented code generated by FE or the IR based
 /// instrumentation pass.
-class InstrProfiling : public PassInfoMixin<InstrProfiling> {
+class InstrProfilingLoweringPass
+    : public PassInfoMixin<InstrProfilingLoweringPass> {
+  const InstrProfOptions Options;
+  // Is this lowering for the context-sensitive instrumentation.
+  const bool IsCS = false;
+
 public:
-  InstrProfiling() : IsCS(false) {}
-  InstrProfiling(const InstrProfOptions &Options, bool IsCS = false)
+  InstrProfilingLoweringPass() = default;
+  InstrProfilingLoweringPass(const InstrProfOptions &Options, bool IsCS = false)
       : Options(Options), IsCS(IsCS) {}
 
   PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
-  bool run(Module &M,
-           std::function<const TargetLibraryInfo &(Function &F)> GetTLI);
+};
+
+class InstrProfiling final {
+public:
+  InstrProfiling(Module &M, const InstrProfOptions &Options,
+                 std::function<const TargetLibraryInfo &(Function &F)> GetTLI,
+                 bool IsCS)
+      : M(M), Options(Options), TT(Triple(M.getTargetTriple())), IsCS(IsCS),
+        GetTLI(GetTLI) {}
+
+  bool lower();
 
 private:
-  InstrProfOptions Options;
-  Module *M;
-  Triple TT;
+  Module &M;
+  const InstrProfOptions Options;
+  const Triple TT;
+  // Is this lowering for the context-sensitive instrumentation.
+  const bool IsCS;
+
   std::function<const TargetLibraryInfo &(Function &F)> GetTLI;
   struct PerFunctionProfileData {
-    uint32_t NumValueSites[IPVK_Last + 1];
+    uint32_t NumValueSites[IPVK_Last + 1] = {};
     GlobalVariable *RegionCounters = nullptr;
     GlobalVariable *DataVar = nullptr;
     GlobalVariable *RegionBitmaps = nullptr;
     uint32_t NumBitmapBytes = 0;
 
-    PerFunctionProfileData() {
-      memset(NumValueSites, 0, sizeof(uint32_t) * (IPVK_Last + 1));
-    }
+    PerFunctionProfileData() = default;
   };
   DenseMap<GlobalVariable *, PerFunctionProfileData> ProfileDataMap;
   /// If runtime relocation is enabled, this maps functions to the load
@@ -64,11 +79,8 @@ private:
   std::vector<GlobalValue *> CompilerUsedVars;
   std::vector<GlobalValue *> UsedVars;
   std::vector<GlobalVariable *> ReferencedNames;
-  GlobalVariable *NamesVar;
-  size_t NamesSize;
-
-  // Is this lowering for the context-sensitive instrumentation.
-  bool IsCS;
+  GlobalVariable *NamesVar = nullptr;
+  size_t NamesSize = 0;
 
   // vector of counter load/store pairs to be register promoted.
   std::vector<LoadStorePair> PromotionCandidates;
diff --git a/llvm/lib/Passes/PassBuilderPipelines.cpp b/llvm/lib/Passes/PassBuilderPipelines.cpp
index e7f88680655c..5c6c391049a7 100644
--- a/llvm/lib/Passes/PassBuilderPipelines.cpp
+++ b/llvm/lib/Passes/PassBuilderPipelines.cpp
@@ -810,7 +810,7 @@ void PassBuilder::addPGOInstrPasses(ModulePassManager &MPM,
   Options.DoCounterPromotion = true;
   Options.UseBFIInPromotion = IsCS;
   Options.Atomic = AtomicCounterUpdate;
-  MPM.addPass(InstrProfiling(Options, IsCS));
+  MPM.addPass(InstrProfilingLoweringPass(Options, IsCS));
 }
 
 void PassBuilder::addPGOInstrPassesForO0(
@@ -837,7 +837,7 @@ void PassBuilder::addPGOInstrPassesForO0(
   Options.DoCounterPromotion = false;
   Options.UseBFIInPromotion = IsCS;
   Options.Atomic = AtomicCounterUpdate;
-  MPM.addPass(InstrProfiling(Options, IsCS));
+  MPM.addPass(InstrProfilingLoweringPass(Options, IsCS));
 }
 
 static InlineParams getInlineParamsFromOptLevel(OptimizationLevel Level) {
diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def
index bf9622670ba5..56449906eb65 100644
--- a/llvm/lib/Passes/PassRegistry.def
+++ b/llvm/lib/Passes/PassRegistry.def
@@ -77,7 +77,7 @@ MODULE_PASS("inliner-wrapper-no-mandatory-first",
             ModuleInlinerWrapperPass(getInlineParams(), false))
 MODULE_PASS("insert-gcov-profiling", GCOVProfilerPass())
 MODULE_PASS("instrorderfile", InstrOrderFilePass())
-MODULE_PASS("instrprof", InstrProfiling())
+MODULE_PASS("instrprof", InstrProfilingLoweringPass())
 MODULE_PASS("internalize", InternalizePass())
 MODULE_PASS("invalidate<all>", InvalidateAllAnalysesPass())
 MODULE_PASS("iroutliner", IROutlinerPass())
diff --git a/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp b/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
index d3282779d9f5..adb4ffd4c812 100644
--- a/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
+++ b/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
@@ -407,13 +407,15 @@ enum class ValueProfilingCallType {
 
 } // end anonymous namespace
 
-PreservedAnalyses InstrProfiling::run(Module &M, ModuleAnalysisManager &AM) {
+PreservedAnalyses InstrProfilingLoweringPass::run(Module &M,
+                                                  ModuleAnalysisManager &AM) {
   FunctionAnalysisManager &FAM =
       AM.getResult<FunctionAnalysisManagerModuleProxy>(M).getManager();
   auto GetTLI = [&FAM](Function &F) -> TargetLibraryInfo & {
     return FAM.getResult<TargetLibraryAnalysis>(F);
   };
-  if (!run(M, GetTLI))
+  InstrProfiling Lowerer(M, Options, GetTLI, IsCS);
+  if (!Lowerer.lower())
     return PreservedAnalyses::all();
 
   return PreservedAnalyses::none();
@@ -535,17 +537,7 @@ static bool containsProfilingIntrinsics(Module &M) {
          containsIntrinsic(llvm::Intrinsic::instrprof_value_profile);
 }
 
-bool InstrProfiling::run(
-    Module &M, std::function<const TargetLibraryInfo &(Function &F)> GetTLI) {
-  this->M = &M;
-  this->GetTLI = std::move(GetTLI);
-  NamesVar = nullptr;
-  NamesSize = 0;
-  ProfileDataMap.clear();
-  CompilerUsedVars.clear();
-  UsedVars.clear();
-  TT = Triple(M.getTargetTriple());
-
+bool InstrProfiling::lower() {
   bool MadeChange = false;
   bool NeedsRuntimeHook = needsRuntimeHookUnconditionally(TT);
   if (NeedsRuntimeHook)
@@ -678,12 +670,12 @@ void InstrProfiling::lowerValueProfileInst(InstrProfValueProfileInst *Ind) {
   Ind->getOperandBundlesAsDefs(OpBundles);
   if (!IsMemOpSize) {
     Value *Args[3] = {Ind->getTargetValue(), DataVar, Builder.getInt32(Index)};
-    Call = Builder.CreateCall(getOrInsertValueProfilingCall(*M, *TLI), Args,
+    Call = Builder.CreateCall(getOrInsertValueProfilingCall(M, *TLI), Args,
                               OpBundles);
   } else {
     Value *Args[3] = {Ind->getTargetValue(), DataVar, Builder.getInt32(Index)};
     Call = Builder.CreateCall(
-        getOrInsertValueProfilingCall(*M, *TLI, ValueProfilingCallType::MemOp),
+        getOrInsertValueProfilingCall(M, *TLI, ValueProfilingCallType::MemOp),
         Args, OpBundles);
   }
   if (auto AK = TLI->getExtAttrForI32Param(false))
@@ -705,18 +697,18 @@ Value *InstrProfiling::getCounterAddress(InstrProfCntrInstBase *I) {
   if (!isRuntimeCounterRelocationEnabled())
     return Addr;
 
-  Type *Int64Ty = Type::getInt64Ty(M->getContext());
+  Type *Int64Ty = Type::getInt64Ty(M.getContext());
   Function *Fn = I->getParent()->getParent();
   LoadInst *&BiasLI = FunctionToProfileBiasMap[Fn];
   if (!BiasLI) {
     IRBuilder<> EntryBuilder(&Fn->getEntryBlock().front());
-    auto *Bias = M->getGlobalVariable(getInstrProfCounterBiasVarName());
+    auto *Bias = M.getGlobalVariable(getInstrProfCounterBiasVarName());
     if (!Bias) {
       // Compiler must define this variable when runtime counter relocation
       // is being used. Runtime has a weak external reference that is used
       // to check whether that's the case or not.
       Bias = new GlobalVariable(
-          *M, Int64Ty, false, GlobalValue::LinkOnceODRLinkage,
+          M, Int64Ty, false, GlobalValue::LinkOnceODRLinkage,
           Constant::getNullValue(Int64Ty), getInstrProfCounterBiasVarName());
       Bias->setVisibility(GlobalVariable::HiddenVisibility);
       // A definition that's weak (linkonce_odr) without being in a COMDAT
@@ -724,7 +716,7 @@ Value *InstrProfiling::getCounterAddress(InstrProfCntrInstBase *I) {
       // data word from every TU but one. Putting it in COMDAT ensures there
       // will be exactly one data slot in the link.
       if (TT.supportsCOMDAT())
-        Bias->setComdat(M->getOrInsertComdat(Bias->getName()));
+        Bias->setComdat(M.getOrInsertComdat(Bias->getName()));
     }
     BiasLI = EntryBuilder.CreateLoad(Int64Ty, Bias);
   }
@@ -740,9 +732,9 @@ Value *InstrProfiling::getBitmapAddress(InstrProfMCDCTVBitmapUpdate *I) {
       Bitmaps->getValueType(), Bitmaps, 0, I->getBitmapIndex()->getZExtValue());
 
   if (isRuntimeCounterRelocationEnabled()) {
-    LLVMContext &Ctx = M->getContext();
+    LLVMContext &Ctx = M.getContext();
     Ctx.diagnose(DiagnosticInfoPGOProfile(
-        M->getName().data(),
+        M.getName().data(),
         Twine("Runtime counter relocation is presently not supported for MC/DC "
               "bitmaps."),
         DS_Warning));
@@ -763,12 +755,12 @@ void InstrProfiling::lowerTimestamp(
     InstrProfTimestampInst *TimestampInstruction) {
   assert(TimestampInstruction->getIndex()->isZeroValue() &&
          "timestamp probes are always the first probe for a function");
-  auto &Ctx = M->getContext();
+  auto &Ctx = M.getContext();
   auto *TimestampAddr = getCounterAddress(TimestampInstruction);
   IRBuilder<> Builder(TimestampInstruction);
   auto *CalleeTy =
       FunctionType::get(Type::getVoidTy(Ctx), TimestampAddr->getType(), false);
-  auto Callee = M->getOrInsertFunction(
+  auto Callee = M.getOrInsertFunction(
       INSTR_PROF_QUOTE(INSTR_PROF_PROFILE_SET_TIMESTAMP), CalleeTy);
   Builder.CreateCall(Callee, {TimestampAddr});
   TimestampInstruction->eraseFromParent();
@@ -813,10 +805,10 @@ void InstrProfiling::lowerCoverageData(GlobalVariable *CoverageNamesVar) {
 void InstrProfiling::lowerMCDCTestVectorBitmapUpdate(
     InstrProfMCDCTVBitmapUpdate *Update) {
   IRBuilder<> Builder(Update);
-  auto *Int8Ty = Type::getInt8Ty(M->getContext());
-  auto *Int8PtrTy = PointerType::getUnqual(M->getContext());
-  auto *Int32Ty = Type::getInt32Ty(M->getContext());
-  auto *Int64Ty = Type::getInt64Ty(M->getContext());
+  auto *Int8Ty = Type::getInt8Ty(M.getContext());
+  auto *Int8PtrTy = PointerType::getUnqual(M.getContext());
+  auto *Int32Ty = Type::getInt32Ty(M.getContext());
+  auto *Int64Ty = Type::getInt64Ty(M.getContext());
   auto *MCDCCondBitmapAddr = Update->getMCDCCondBitmapAddr();
   auto *BitmapAddr = getBitmapAddress(Update);
 
@@ -865,7 +857,7 @@ void InstrProfiling::lowerMCDCTestVectorBitmapUpdate(
 void InstrProfiling::lowerMCDCCondBitmapUpdate(
     InstrProfMCDCCondBitmapUpdate *Update) {
   IRBuilder<> Builder(Update);
-  auto *Int32Ty = Type::getInt32Ty(M->getContext());
+  auto *Int32Ty = Type::getInt32Ty(M.getContext());
   auto *MCDCCondBitmapAddr = Update->getMCDCCondBitmapAddr();
 
   // Load the MCDC temporary value from the stack.
@@ -1047,8 +1039,8 @@ static bool needsRuntimeRegistrationOfSectionRange(const Triple &TT) {
 
 void InstrProfiling::maybeSetComdat(GlobalVariable *GV, Function *Fn,
                                     StringRef VarName) {
-  bool DataReferencedByCode = profDataReferencedByCode(*M);
-  bool NeedComdat = needsComdatForCounter(*Fn, *M);
+  bool DataReferencedByCode = profDataReferencedByCode(M);
+  bool NeedComdat = needsComdatForCounter(*Fn, M);
   bool UseComdat = (NeedComdat || TT.isOSBinFormatELF());
 
   if (!UseComdat)
@@ -1056,7 +1048,7 @@ void InstrProfiling::maybeSetComdat(GlobalVariable *GV, Function *Fn,
 
   StringRef GroupName =
       TT.isOSBinFormatCOFF() && DataReferencedByCode ? GV->getName() : VarName;
-  Comdat *C = M->getOrInsertComdat(GroupName);
+  Comdat *C = M.getOrInsertComdat(GroupName);
   if (!NeedComdat)
     C->setSelectionKind(Comdat::NoDeduplicate);
   GV->setComdat(C);
@@ -1141,8 +1133,8 @@ InstrProfiling::createRegionBitmaps(InstrProfMCDCBitmapInstBase *Inc,
                                     StringRef Name,
                                     GlobalValue::LinkageTypes Linkage) {
   uint64_t NumBytes = Inc->getNumBitmapBytes()->getZExtValue();
-  auto *BitmapTy = ArrayType::get(Type::getInt8Ty(M->getContext()), NumBytes);
-  auto GV = new GlobalVariable(*M, BitmapTy, false, Linkage,
+  auto *BitmapTy = ArrayType::get(Type::getInt8Ty(M.getContext()), NumBytes);
+  auto GV = new GlobalVariable(M, BitmapTy, false, Linkage,
                                Constant::getNullValue(BitmapTy), Name);
   GV->setAlignment(Align(1));
   return GV;
@@ -1167,7 +1159,7 @@ GlobalVariable *
 InstrProfiling::createRegionCounters(InstrProfCntrInstBase *Inc, StringRef Name,
                                      GlobalValue::LinkageTypes Linkage) {
   uint64_t NumCounters = Inc->getNumCounters()->getZExtValue();
-  auto &Ctx = M->getContext();
+  auto &Ctx = M.getContext();
   GlobalVariable *GV;
   if (isa<InstrProfCoverInst>(Inc)) {
     auto *CounterTy = Type::getInt8Ty(Ctx);
@@ -1175,13 +1167,13 @@ InstrProfiling::createRegionCounters(InstrProfCntrInstBase *Inc, StringRef Name,
     // TODO: `Constant::getAllOnesValue()` does not yet accept an array type.
     std::vector<Constant *> InitialValues(NumCounters,
                                           Constant::getAllOnesValue(CounterTy));
-    GV = new GlobalVariable(*M, CounterArrTy, false, Linkage,
+    GV = new GlobalVariable(M, CounterArrTy, false, Linkage,
                             ConstantArray::get(CounterArrTy, InitialValues),
                             Name);
     GV->setAlignment(Align(1));
   } else {
     auto *CounterTy = ArrayType::get(Type::getInt64Ty(Ctx), NumCounters);
-    GV = new GlobalVariable(*M, CounterTy, false, Linkage,
+    GV = new GlobalVariable(M, CounterTy, false, Linkage,
                             Constant::getNullValue(CounterTy), Name);
     GV->setAlignment(Align(8));
   }
@@ -1201,10 +1193,10 @@ InstrProfiling::getOrCreateRegionCounters(InstrProfCntrInstBase *Inc) {
   PD.RegionCounters = CounterPtr;
 
   if (DebugInfoCorrelate) {
-    LLVMContext &Ctx = M->getContext();
+    LLVMContext &Ctx = M.getContext();
     Function *Fn = Inc->getParent()->getParent();
     if (auto *SP = Fn->getSubprogram()) {
-      DIBuilder DB(*M, true, SP->getUnit());
+      DIBuilder DB(M, true, SP->getUnit());
       Metadata *FunctionNameAnnotation[] = {
           MDString::get(Ctx, InstrProfCorrelator::FunctionNameAttributeName),
           MDString::get(Ctx, getPGOFuncNameVarInitializer(NamePtr)),
@@ -1255,7 +1247,7 @@ void InstrProfiling::createDataVariable(InstrProfCntrInstBase *Inc) {
   if (PD.DataVar)
     return;
 
-  LLVMContext &Ctx = M->getContext();
+  LLVMContext &Ctx = M.getContext();
 
   Function *Fn = Inc->getParent()->getParent();
   GlobalValue::LinkageTypes Linkage = NamePtr->getLinkage();
@@ -1271,8 +1263,8 @@ void InstrProfiling::createDataVariable(InstrProfCntrInstBase *Inc) {
     Visibility = GlobalValue::DefaultVisibility;
   }
 
-  bool DataReferencedByCode = profDataReferencedByCode(*M);
-  bool NeedComdat = needsComdatForCounter(*Fn, *M);
+  bool DataReferencedByCode = profDataReferencedByCode(M);
+  bool NeedComdat = needsComdatForCounter(*Fn, M);
   bool Renamed;
 
   // The Data Variable section is anchored to profile counters.
@@ -1292,7 +1284,7 @@ void InstrProfiling::createDataVariable(InstrProfCntrInstBase *Inc) {
       !needsRuntimeRegistrationOfSectionRange(TT)) {
     ArrayType *ValuesTy = ArrayType::get(Type::getInt64Ty(Ctx), NS);
     auto *ValuesVar = new GlobalVariable(
-        *M, ValuesTy, false, Linkage, Constant::getNullValue(ValuesTy),
+        M, ValuesTy, false, Linkage, Constant::getNullValue(ValuesTy),
         getVarName(Inc, getInstrProfValuesVarPrefix(), Renamed));
     ValuesVar->setVisibility(Visibility);
     setGlobalVariableLargeSection(TT, *ValuesVar);
@@ -1309,7 +1301,7 @@ void InstrProfiling::createDataVariable(InstrProfCntrInstBase *Inc) {
   uint64_t NumBitmapBytes = PD.NumBitmapBytes;
 
   // Create data variable.
-  auto *IntPtrTy = M->getDataLayout().getIntPtrType(M->getContext());
+  auto *IntPtrTy = M.getDataLayout().getIntPtrType(M.getContext());
   auto *Int16Ty = Type::getInt16Ty(Ctx);
   auto *Int16ArrayTy = ArrayType::get(Int16Ty, IPVK_Last + 1);
   Type *DataTypes[] = {
@@ -1342,7 +1334,7 @@ void InstrProfiling::createDataVariable(InstrProfCntrInstBase *Inc) {
     Visibility = GlobalValue::DefaultVisibility;
   }
   auto *Data =
-      new GlobalVariable(*M, DataTy, false, Linkage, nullptr, DataVarName);
+      new GlobalVariable(M, DataTy, false, Linkage, nullptr, DataVarName);
   // Reference the counter variable with a label difference (link-time
   // constant).
   auto *RelativeCounterPtr =
@@ -1413,7 +1405,7 @@ void InstrProfiling::emitVNodes() {
   if (NumCounters < INSTR_PROF_MIN_VAL_COUNTS)
     NumCounters = std::max(INSTR_PROF_MIN_VAL_COUNTS, (int)NumCounters * 2);
 
-  auto &Ctx = M->getContext();
+  auto &Ctx = M.getContext();
   Type *VNodeTypes[] = {
 #define INSTR_PROF_VALUE_NODE(Type, LLVMType, Name, Init) LLVMType,
 #include "llvm/ProfileData/InstrProfData.inc"
@@ -1422,12 +1414,12 @@ void InstrProfiling::emitVNodes() {
 
   ArrayType *VNodesTy = ArrayType::get(VNodeTy, NumCounters);
   auto *VNodesVar = new GlobalVariable(
-      *M, VNodesTy, false, GlobalValue::PrivateLinkage,
+      M, VNodesTy, false, GlobalValue::PrivateLinkage,
       Constant::getNullValue(VNodesTy), getInstrProfVNodesVarName());
   setGlobalVariableLargeSection(TT, *VNodesVar);
   VNodesVar->setSection(
       getInstrProfSectionName(IPSK_vnodes, TT.getObjectFormat()));
-  VNodesVar->setAlignment(M->getDataLayout().getABITypeAlign(VNodesTy));
+  VNodesVar->setAlignment(M.getDataLayout().getABITypeAlign(VNodesTy));
   // VNodesVar is used by runtime but not referenced via relocation by other
   // sections. Conservatively make it linker retained.
   UsedVars.push_back(VNodesVar);
@@ -1445,10 +1437,10 @@ void InstrProfiling::emitNameData() {
     report_fatal_error(Twine(toString(std::move(E))), false);
   }
 
-  auto &Ctx = M->getContext();
+  auto &Ctx = M.getContext();
   auto *NamesVal =
       ConstantDataArray::getString(Ctx, StringRef(CompressedNameStr), false);
-  NamesVar = new GlobalVariable(*M, NamesVal->getType(), true,
+  NamesVar = new GlobalVariable(M, NamesVal->getType(), true,
                                 GlobalValue::PrivateLinkage, NamesVal,
                                 getInstrProfNamesVarName());
   NamesSize = CompressedNameStr.size();
@@ -1472,9 +1464,9 @@ void InstrProfiling::emitRegistration() {
     return;
 
   // Construct the function.
-  auto *VoidTy = Type::getVoidTy(M->getContext());
-  auto *VoidPtrTy = PointerType::getUnqual(M->getContext());
-  auto *Int64Ty = Type::getInt64Ty(M->getContext());
+  auto *VoidTy = Type::getVoidTy(M.getContext());
+  auto *VoidPtrTy = PointerType::getUnqual(M.getContext());
+  auto *Int64Ty = Type::getInt64Ty(M.getContext());
   auto *RegisterFTy = FunctionType::get(VoidTy, false);
   auto *RegisterF = Function::Create(RegisterFTy, GlobalValue::InternalLinkage,
                                      getInstrProfRegFuncsName(), M);
@@ -1487,7 +1479,7 @@ void InstrProfiling::emitRegistration() {
       Function::Create(RuntimeRegisterTy, GlobalVariable::ExternalLinkage,
                        getInstrProfRegFuncName(), M);
 
-  IRBuilder<> IRB(BasicBlock::Create(M->getContext(), "", RegisterF));
+  IRBuilder<> IRB(BasicBlock::Create(M.getContext(), "", RegisterF));
   for (Value *Data : CompilerUsedVars)
     if (!isa<Function>(Data))
       IRB.CreateCall(RuntimeRegisterF, Data);
@@ -1515,13 +1507,13 @@ bool InstrProfiling::emitRuntimeHook() {
     return false;
 
   // If the module's provided its own runtime, we don't need to do anything.
-  if (M->getGlobalVariable(getInstrProfRuntimeHookVarName()))
+  if (M.getGlobalVariable(getInstrProfRuntimeHookVarName()))
     return false;
 
   // Declare an external variable that will pull in the runtime initialization.
-  auto *Int32Ty = Type::getInt32Ty(M->getContext());
+  auto *Int32Ty = Type::getInt32Ty(M.getContext());
   auto *Var =
-      new GlobalVariable(*M, Int32Ty, false, GlobalValue::ExternalLinkage,
+      new GlobalVariable(M, Int32Ty, false, GlobalValue::ExternalLinkage,
                          nullptr, getInstrProfRuntimeHookVarName());
   Var->setVisibility(GlobalValue::HiddenVisibility);
 
@@ -1538,9 +1530,9 @@ bool InstrProfiling::emitRuntimeHook() {
       User->addFnAttr(Attribute::NoRedZone);
     User->setVisibility(GlobalValue::HiddenVisibility);
     if (TT.supportsCOMDAT())
-      User->setComdat(M->getOrInsertComdat(User->getName()));
+      User->setComdat(M.getOrInsertComdat(User->getName()));
 
-    IRBuilder<> IRB(BasicBlock::Create(M->getContext(), "", User));
+    IRBuilder<> IRB(BasicBlock::Create(M.getContext(), "", User));
     auto *Load = IRB.CreateLoad(Int32Ty, Var);
     IRB.CreateRet(Load);
 
@@ -1561,15 +1553,15 @@ void InstrProfiling::emitUses() {
   // and ensure this GC property as well. Otherwise, we have to conservatively
   // make all of the sections retained by the linker.
   if (TT.isOSBinFormatELF() || TT.isOSBinFormatMachO() ||
-      (TT.isOSBinFormatCOFF() && !profDataReferencedByCode(*M)))
-    appendToCompilerUsed(*M, CompilerUsedVars);
+      (TT.isOSBinFormatCOFF() && !profDataReferencedByCode(M)))
+    appendToCompilerUsed(M, CompilerUsedVars);
   else
-    appendToUsed(*M, CompilerUsedVars);
+    appendToUsed(M, CompilerUsedVars);
 
   // We do not add proper references from used metadata sections to NamesVar and
   // VNodesVar, so we have to be conservative and place them in llvm.used
   // regardless of the target,
-  appendToUsed(*M, UsedVars);
+  appendToUsed(M, UsedVars);
 }
 
 void InstrProfiling::emitInitialization() {
@@ -1578,13 +1570,13 @@ void InstrProfiling::emitInitialization() {
   // LTO/ThinLTO linking. Pass PGOInstrumentationGenCreateVar should
   // have already create the variable before LTO/ThinLTO linking.
   if (!IsCS)
-    createProfileFileNameVar(*M, Options.InstrProfileOutput);
-  Function *RegisterF = M->getFunction(getInstrProfRegFuncsName());
+    createProfileFileNameVar(M, Options.InstrProfileOutput);
+  Function *RegisterF = M.getFunction(getInstrProfRegFuncsName());
   if (!RegisterF)
     return;
 
   // Create the initialization function.
-  auto *VoidTy = Type::getVoidTy(M->getContext());
+  auto *VoidTy = Type::getVoidTy(M.getContext());
   auto *F = Function::Create(FunctionType::get(VoidTy, false),
                              GlobalValue::InternalLinkage,
                              getInstrProfInitFuncName(), M);
@@ -1594,9 +1586,9 @@ void InstrProfiling::emitInitialization() {
     F->addFnAttr(Attribute::NoRedZone);
 
   // Add the basic block and the necessary calls.
-  IRBuilder<> IRB(BasicBlock::Create(M->getContext(), "", F));
+  IRBuilder<> IRB(BasicBlock::Create(M.getContext(), "", F));
   IRB.CreateCall(RegisterF, {});
   IRB.CreateRetVoid();
 
-  appendToGlobalCtors(*M, F, 0);
+  appendToGlobalCtors(M, F, 0);
 }
diff --git a/llvm/lib/Transforms/Instrumentation/Instrumentation.cpp b/llvm/lib/Transforms/Instrumentation/Instrumentation.cpp
index 199afbe966dd..7a03ee46d6fd 100644
--- a/llvm/lib/Transforms/Instrumentation/Instrumentation.cpp
+++ b/llvm/lib/Transforms/Instrumentation/Instrumentation.cpp
@@ -85,7 +85,7 @@ Comdat *llvm::getOrCreateFunctionComdat(Function &F, Triple &T) {
   return C;
 }
 
-void llvm::setGlobalVariableLargeSection(Triple &TargetTriple,
+void llvm::setGlobalVariableLargeSection(const Triple &TargetTriple,
                                          GlobalVariable &GV) {
   if (TargetTriple.getArch() == Triple::x86_64 &&
       TargetTriple.getObjectFormat() == Triple::ELF) {
-- 
GitLab


From 9406ea3fe32e59a7d28de0dcbd0317b4cdfa4c62 Mon Sep 17 00:00:00 2001
From: Chuanqi Xu <yedeng.yd@linux.alibaba.com>
Date: Thu, 7 Dec 2023 17:01:06 +0800
Subject: [PATCH 070/349] [NFC] [Serialization] Packing more bits

This patch tries to reduce the size of the BMIs by packing more bits
into an unsigned integer.
---
 clang/lib/Serialization/ASTReaderDecl.cpp     |  21 ++-
 clang/lib/Serialization/ASTReaderStmt.cpp     |  72 ++++----
 clang/lib/Serialization/ASTWriterDecl.cpp     | 155 ++++++++----------
 clang/lib/Serialization/ASTWriterStmt.cpp     |  36 ++--
 clang/test/Modules/decl-params-determinisim.m |  16 +-
 5 files changed, 162 insertions(+), 138 deletions(-)

diff --git a/clang/lib/Serialization/ASTReaderDecl.cpp b/clang/lib/Serialization/ASTReaderDecl.cpp
index bc16cfc67a24..7140a14aefbf 100644
--- a/clang/lib/Serialization/ASTReaderDecl.cpp
+++ b/clang/lib/Serialization/ASTReaderDecl.cpp
@@ -583,6 +583,9 @@ void ASTDeclReader::Visit(Decl *D) {
 }
 
 void ASTDeclReader::VisitDecl(Decl *D) {
+  BitsUnpacker DeclBits(Record.readInt());
+  bool HasStandaloneLexicalDC = DeclBits.getNextBit();
+
   if (D->isTemplateParameter() || D->isTemplateParameterPack() ||
       isa<ParmVarDecl, ObjCTypeParamDecl>(D)) {
     // We don't want to deserialize the DeclContext of a template
@@ -592,7 +595,8 @@ void ASTDeclReader::VisitDecl(Decl *D) {
     // return type of the function).  Use the translation unit DeclContext as a
     // placeholder.
     GlobalDeclID SemaDCIDForTemplateParmDecl = readDeclID();
-    GlobalDeclID LexicalDCIDForTemplateParmDecl = readDeclID();
+    GlobalDeclID LexicalDCIDForTemplateParmDecl =
+        HasStandaloneLexicalDC ? readDeclID() : 0;
     if (!LexicalDCIDForTemplateParmDecl)
       LexicalDCIDForTemplateParmDecl = SemaDCIDForTemplateParmDecl;
     Reader.addPendingDeclContextInfo(D,
@@ -601,7 +605,8 @@ void ASTDeclReader::VisitDecl(Decl *D) {
     D->setDeclContext(Reader.getContext().getTranslationUnitDecl());
   } else {
     auto *SemaDC = readDeclAs<DeclContext>();
-    auto *LexicalDC = readDeclAs<DeclContext>();
+    auto *LexicalDC =
+        HasStandaloneLexicalDC ? readDeclAs<DeclContext>() : nullptr;
     if (!LexicalDC)
       LexicalDC = SemaDC;
     // If the context is a class, we might not have actually merged it yet, in
@@ -618,7 +623,6 @@ void ASTDeclReader::VisitDecl(Decl *D) {
   }
   D->setLocation(ThisDeclLoc);
 
-  BitsUnpacker DeclBits(Record.readInt());
   D->InvalidDecl = DeclBits.getNextBit();
   bool HasAttrs = DeclBits.getNextBit();
   D->setImplicit(DeclBits.getNextBit());
@@ -765,7 +769,7 @@ ASTDeclReader::RedeclarableResult ASTDeclReader::VisitTagDecl(TagDecl *TD) {
   TD->setCompleteDefinitionRequired(TagDeclBits.getNextBit());
   TD->setBraceRange(readSourceRange());
 
-  switch (Record.readInt()) {
+  switch (TagDeclBits.getNextBits(/*Width=*/2)) {
   case 0:
     break;
   case 1: { // ExtInfo
@@ -1089,7 +1093,8 @@ void ASTDeclReader::VisitFunctionDecl(FunctionDecl *FD) {
   FD->setCachedLinkage((Linkage)FunctionDeclBits.getNextBits(/*Width=*/3));
 
   FD->EndRangeLoc = readSourceLocation();
-  FD->setDefaultLoc(readSourceLocation());
+  if (FD->isExplicitlyDefaulted())
+    FD->setDefaultLoc(readSourceLocation());
 
   FD->ODRHash = Record.readInt();
   FD->setHasODRHash(true);
@@ -1703,7 +1708,7 @@ void ASTDeclReader::VisitParmVarDecl(ParmVarDecl *PD) {
   unsigned isObjCMethodParam = ParmVarDeclBits.getNextBit();
   unsigned scopeDepth = ParmVarDeclBits.getNextBits(/*Width=*/7);
   unsigned scopeIndex = ParmVarDeclBits.getNextBits(/*Width=*/8);
-  unsigned declQualifier = Record.readInt();
+  unsigned declQualifier = ParmVarDeclBits.getNextBits(/*Width=*/7);
   if (isObjCMethodParam) {
     assert(scopeDepth == 0);
     PD->setObjCMethodScopeInfo(scopeIndex);
@@ -1716,7 +1721,9 @@ void ASTDeclReader::VisitParmVarDecl(ParmVarDecl *PD) {
   PD->ParmVarDeclBits.HasInheritedDefaultArg = ParmVarDeclBits.getNextBit();
   if (ParmVarDeclBits.getNextBit()) // hasUninstantiatedDefaultArg.
     PD->setUninstantiatedDefaultArg(Record.readExpr());
-  PD->ExplicitObjectParameterIntroducerLoc = Record.readSourceLocation();
+
+  if (ParmVarDeclBits.getNextBit()) // Valid explicit object parameter
+    PD->ExplicitObjectParameterIntroducerLoc = Record.readSourceLocation();
 
   // FIXME: If this is a redeclaration of a function from another module, handle
   // inheritance of default arguments.
diff --git a/clang/lib/Serialization/ASTReaderStmt.cpp b/clang/lib/Serialization/ASTReaderStmt.cpp
index d7d0c0e5bb21..865322ec0782 100644
--- a/clang/lib/Serialization/ASTReaderStmt.cpp
+++ b/clang/lib/Serialization/ASTReaderStmt.cpp
@@ -108,7 +108,7 @@ namespace clang {
 
     /// The number of record fields required for the Expr class
     /// itself.
-    static const unsigned NumExprFields = NumStmtFields + 4;
+    static const unsigned NumExprFields = NumStmtFields + 2;
 
     /// Read and initialize a ExplicitTemplateArgumentList structure.
     void ReadTemplateKWAndArgsInfo(ASTTemplateKWAndArgsInfo &Args,
@@ -524,9 +524,13 @@ void ASTStmtReader::VisitCapturedStmt(CapturedStmt *S) {
 void ASTStmtReader::VisitExpr(Expr *E) {
   VisitStmt(E);
   E->setType(Record.readType());
-  E->setDependence(static_cast<ExprDependence>(Record.readInt()));
-  E->setValueKind(static_cast<ExprValueKind>(Record.readInt()));
-  E->setObjectKind(static_cast<ExprObjectKind>(Record.readInt()));
+  BitsUnpacker ExprBits(Record.readInt());
+  E->setDependence(
+      static_cast<ExprDependence>(ExprBits.getNextBits(/*Width=*/5)));
+  E->setValueKind(
+      static_cast<ExprValueKind>(ExprBits.getNextBits(/*Width=*/2)));
+  E->setObjectKind(
+      static_cast<ExprObjectKind>(ExprBits.getNextBits(/*Width=*/3)));
   assert(Record.getIdx() == NumExprFields &&
          "Incorrect expression field count");
 }
@@ -995,14 +999,19 @@ void ASTStmtReader::VisitOMPIteratorExpr(OMPIteratorExpr *E) {
 
 void ASTStmtReader::VisitCallExpr(CallExpr *E) {
   VisitExpr(E);
-  unsigned NumArgs = Record.readInt();
-  bool HasFPFeatures = Record.readInt();
+
+  BitsUnpacker CallExprBits = Record.readInt();
+
+  unsigned NumArgs = CallExprBits.getNextBits(/*Width=*/16);
+  bool HasFPFeatures = CallExprBits.getNextBit();
+  E->setADLCallKind(
+      static_cast<CallExpr::ADLCallKind>(CallExprBits.getNextBit()));
   assert((NumArgs == E->getNumArgs()) && "Wrong NumArgs!");
   E->setRParenLoc(readSourceLocation());
   E->setCallee(Record.readSubExpr());
   for (unsigned I = 0; I != NumArgs; ++I)
     E->setArg(I, Record.readSubExpr());
-  E->setADLCallKind(static_cast<CallExpr::ADLCallKind>(Record.readInt()));
+
   if (HasFPFeatures)
     E->setStoredFPFeatures(
         FPOptionsOverride::getFromOpaqueInt(Record.readInt()));
@@ -2013,14 +2022,15 @@ ASTStmtReader::VisitCXXUnresolvedConstructExpr(CXXUnresolvedConstructExpr *E) {
 void ASTStmtReader::VisitOverloadExpr(OverloadExpr *E) {
   VisitExpr(E);
 
-  unsigned NumResults = Record.readInt();
-  bool HasTemplateKWAndArgsInfo = Record.readInt();
+  BitsUnpacker OverloadExprBits = Record.readInt();
+  unsigned NumResults = OverloadExprBits.getNextBits(/*Width=*/14);
+  bool HasTemplateKWAndArgsInfo = OverloadExprBits.getNextBit();
   assert((E->getNumDecls() == NumResults) && "Wrong NumResults!");
   assert((E->hasTemplateKWAndArgsInfo() == HasTemplateKWAndArgsInfo) &&
          "Wrong HasTemplateKWAndArgsInfo!");
 
   if (HasTemplateKWAndArgsInfo) {
-    unsigned NumTemplateArgs = Record.readInt();
+    unsigned NumTemplateArgs = OverloadExprBits.getNextBits(/*Width=*/14);
     ReadTemplateKWAndArgsInfo(*E->getTrailingASTTemplateKWAndArgsInfo(),
                               E->getTrailingTemplateArgumentLoc(),
                               NumTemplateArgs);
@@ -3024,8 +3034,9 @@ Stmt *ASTReader::ReadStmtFromStream(ModuleFile &F) {
 
     case EXPR_CALL:
       S = CallExpr::CreateEmpty(
-          Context, /*NumArgs=*/Record[ASTStmtReader::NumExprFields],
-          /*HasFPFeatures=*/Record[ASTStmtReader::NumExprFields + 1], Empty);
+          Context, /*NumArgs=*/Record[ASTStmtReader::NumExprFields] & 0xffff,
+          /*HasFPFeatures=*/
+          ((Record[ASTStmtReader::NumExprFields] >> 16) & 0x1), Empty);
       break;
 
     case EXPR_RECOVERY:
@@ -3766,14 +3777,16 @@ Stmt *ASTReader::ReadStmtFromStream(ModuleFile &F) {
 
     case EXPR_CXX_OPERATOR_CALL:
       S = CXXOperatorCallExpr::CreateEmpty(
-          Context, /*NumArgs=*/Record[ASTStmtReader::NumExprFields],
-          /*HasFPFeatures=*/Record[ASTStmtReader::NumExprFields + 1], Empty);
+          Context, /*NumArgs=*/Record[ASTStmtReader::NumExprFields] & 0xffff,
+          /*HasFPFeatures=*/
+          ((Record[ASTStmtReader::NumExprFields] >> 16) & 0x1), Empty);
       break;
 
     case EXPR_CXX_MEMBER_CALL:
       S = CXXMemberCallExpr::CreateEmpty(
-          Context, /*NumArgs=*/Record[ASTStmtReader::NumExprFields],
-          /*HasFPFeatures=*/Record[ASTStmtReader::NumExprFields + 1], Empty);
+          Context, /*NumArgs=*/Record[ASTStmtReader::NumExprFields] & 0xffff,
+          /*HasFPFeatures=*/
+          ((Record[ASTStmtReader::NumExprFields] >> 16) & 0x1), Empty);
       break;
 
     case EXPR_CXX_REWRITTEN_BINARY_OPERATOR:
@@ -3948,23 +3961,21 @@ Stmt *ASTReader::ReadStmtFromStream(ModuleFile &F) {
     case EXPR_CXX_UNRESOLVED_MEMBER:
       S = UnresolvedMemberExpr::CreateEmpty(
           Context,
-          /*NumResults=*/Record[ASTStmtReader::NumExprFields],
-          /*HasTemplateKWAndArgsInfo=*/Record[ASTStmtReader::NumExprFields + 1],
-          /*NumTemplateArgs=*/
-          Record[ASTStmtReader::NumExprFields + 1]
-              ? Record[ASTStmtReader::NumExprFields + 2]
-              : 0);
+          /*NumResults=*/Record[ASTStmtReader::NumExprFields] & ((1 << 14) - 1),
+          /*HasTemplateKWAndArgsInfo=*/
+              (Record[ASTStmtReader::NumExprFields] >> 14) & (0x1),
+          /*NumTemplateArgs=*/Record[ASTStmtReader::NumExprFields] >> 14 &
+              ((1 << 14) - 1));
       break;
 
     case EXPR_CXX_UNRESOLVED_LOOKUP:
       S = UnresolvedLookupExpr::CreateEmpty(
           Context,
-          /*NumResults=*/Record[ASTStmtReader::NumExprFields],
-          /*HasTemplateKWAndArgsInfo=*/Record[ASTStmtReader::NumExprFields + 1],
-          /*NumTemplateArgs=*/
-          Record[ASTStmtReader::NumExprFields + 1]
-              ? Record[ASTStmtReader::NumExprFields + 2]
-              : 0);
+          /*NumResults=*/Record[ASTStmtReader::NumExprFields] & ((1 << 14) - 1),
+          /*HasTemplateKWAndArgsInfo=*/
+              (Record[ASTStmtReader::NumExprFields] >> 14) & (0x1),
+          /*NumTemplateArgs=*/Record[ASTStmtReader::NumExprFields] >> 14 &
+              ((1 << 14) - 1));
       break;
 
     case EXPR_TYPE_TRAIT:
@@ -4026,8 +4037,9 @@ Stmt *ASTReader::ReadStmtFromStream(ModuleFile &F) {
 
     case EXPR_CUDA_KERNEL_CALL:
       S = CUDAKernelCallExpr::CreateEmpty(
-          Context, /*NumArgs=*/Record[ASTStmtReader::NumExprFields],
-          /*HasFPFeatures=*/Record[ASTStmtReader::NumExprFields + 1], Empty);
+          Context, /*NumArgs=*/Record[ASTStmtReader::NumExprFields] & 0xffff,
+          /*HasFPFeatures=*/
+          ((Record[ASTStmtReader::NumExprFields] >> 16) & 0x1), Empty);
       break;
 
     case EXPR_ASTYPE:
diff --git a/clang/lib/Serialization/ASTWriterDecl.cpp b/clang/lib/Serialization/ASTWriterDecl.cpp
index bf082e5b8eac..a5035d500281 100644
--- a/clang/lib/Serialization/ASTWriterDecl.cpp
+++ b/clang/lib/Serialization/ASTWriterDecl.cpp
@@ -320,13 +320,8 @@ void ASTDeclWriter::Visit(Decl *D) {
 }
 
 void ASTDeclWriter::VisitDecl(Decl *D) {
-  Record.AddDeclRef(cast_or_null<Decl>(D->getDeclContext()));
-  if (D->getDeclContext() != D->getLexicalDeclContext())
-    Record.AddDeclRef(cast_or_null<Decl>(D->getLexicalDeclContext()));
-  else
-    Record.push_back(0);
-
   BitsPacker DeclBits;
+  DeclBits.addBit(D->getDeclContext() != D->getLexicalDeclContext());
   DeclBits.addBit(D->isInvalidDecl());
   DeclBits.addBit(D->hasAttrs());
   DeclBits.addBit(D->isImplicit());
@@ -337,6 +332,10 @@ void ASTDeclWriter::VisitDecl(Decl *D) {
   DeclBits.addBits((uint64_t)D->getModuleOwnershipKind(), /*BitWidth=*/3);
   Record.push_back(DeclBits);
 
+  Record.AddDeclRef(cast_or_null<Decl>(D->getDeclContext()));
+  if (D->getDeclContext() != D->getLexicalDeclContext())
+    Record.AddDeclRef(cast_or_null<Decl>(D->getLexicalDeclContext()));
+
   if (D->hasAttrs())
     Record.AddAttributes(D->getAttrs());
 
@@ -450,19 +449,18 @@ void ASTDeclWriter::VisitTagDecl(TagDecl *D) {
   TagDeclBits.addBit(D->isEmbeddedInDeclarator());
   TagDeclBits.addBit(D->isFreeStanding());
   TagDeclBits.addBit(D->isCompleteDefinitionRequired());
+  TagDeclBits.addBits(
+      D->hasExtInfo() ? 1 : (D->getTypedefNameForAnonDecl() ? 2 : 0),
+      /*BitWidth=*/2);
   Record.push_back(TagDeclBits);
 
   Record.AddSourceRange(D->getBraceRange());
 
   if (D->hasExtInfo()) {
-    Record.push_back(1);
     Record.AddQualifierInfo(*D->getExtInfo());
   } else if (auto *TD = D->getTypedefNameForAnonDecl()) {
-    Record.push_back(2);
     Record.AddDeclRef(TD);
     Record.AddIdentifierRef(TD->getDeclName().getAsIdentifierInfo());
-  } else {
-    Record.push_back(0);
   }
 }
 
@@ -702,7 +700,8 @@ void ASTDeclWriter::VisitFunctionDecl(FunctionDecl *D) {
   Record.push_back(FunctionDeclBits);
 
   Record.AddSourceLocation(D->getEndLoc());
-  Record.AddSourceLocation(D->getDefaultLoc());
+  if (D->isExplicitlyDefaulted())
+    Record.AddSourceLocation(D->getDefaultLoc());
 
   Record.push_back(D->getODRHash());
 
@@ -1176,15 +1175,18 @@ void ASTDeclWriter::VisitParmVarDecl(ParmVarDecl *D) {
   ParmVarDeclBits.addBit(D->isObjCMethodParameter());
   ParmVarDeclBits.addBits(D->getFunctionScopeDepth(), /*BitsWidth=*/7);
   ParmVarDeclBits.addBits(D->getFunctionScopeIndex(), /*BitsWidth=*/8);
+  // FIXME: stable encoding
+  ParmVarDeclBits.addBits(D->getObjCDeclQualifier(), /*BitsWidth=*/7);
   ParmVarDeclBits.addBit(D->isKNRPromoted());
   ParmVarDeclBits.addBit(D->hasInheritedDefaultArg());
   ParmVarDeclBits.addBit(D->hasUninstantiatedDefaultArg());
+  ParmVarDeclBits.addBit(D->getExplicitObjectParamThisLoc().isValid());
   Record.push_back(ParmVarDeclBits);
 
-  Record.push_back(D->getObjCDeclQualifier()); // FIXME: stable encoding
   if (D->hasUninstantiatedDefaultArg())
     Record.AddStmt(D->getUninstantiatedDefaultArg());
-  Record.AddSourceLocation(D->getExplicitObjectParamThisLoc());
+  if (D->getExplicitObjectParamThisLoc().isValid())
+    Record.AddSourceLocation(D->getExplicitObjectParamThisLoc());
   Code = serialization::DECL_PARM_VAR;
 
   // If the assumptions about the DECL_PARM_VAR abbrev are true, use it.  Here
@@ -2038,13 +2040,12 @@ void ASTWriter::WriteDeclAbbrevs() {
   Abv = std::make_shared<BitCodeAbbrev>();
   Abv->Add(BitCodeAbbrevOp(serialization::DECL_FIELD));
   // Decl
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
+                           12)); // Packed DeclBits: HasStandaloneLexicalDC,
+                                 // isInvalidDecl, HasAttrs, isImplicit, isUsed,
+                                 // isReferenced, TopLevelDeclInObjCContainer,
+                                 // AccessSpecifier, ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // DeclContext
-  Abv->Add(BitCodeAbbrevOp(0));                       // LexicalDeclContext
-  Abv->Add(BitCodeAbbrevOp(
-      BitCodeAbbrevOp::Fixed,
-      11)); // Packed DeclBits: isInvalidDecl, HasAttrs, isImplicit, isUsed,
-            // isReferenced, TopLevelDeclInObjCContainer, AccessSpecifier,
-            // ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // SubmoduleID
   // NamedDecl
   Abv->Add(BitCodeAbbrevOp(0));                       // NameKind = Identifier
@@ -2068,13 +2069,12 @@ void ASTWriter::WriteDeclAbbrevs() {
   Abv = std::make_shared<BitCodeAbbrev>();
   Abv->Add(BitCodeAbbrevOp(serialization::DECL_OBJC_IVAR));
   // Decl
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
+                           12)); // Packed DeclBits: HasStandaloneLexicalDC,
+                                 // isInvalidDecl, HasAttrs, isImplicit, isUsed,
+                                 // isReferenced, TopLevelDeclInObjCContainer,
+                                 // AccessSpecifier, ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // DeclContext
-  Abv->Add(BitCodeAbbrevOp(0));                       // LexicalDeclContext
-  Abv->Add(BitCodeAbbrevOp(
-      BitCodeAbbrevOp::Fixed,
-      11)); // Packed DeclBits: isInvalidDecl, HasAttrs, isImplicit, isUsed,
-            // isReferenced, TopLevelDeclInObjCContainer, AccessSpecifier,
-            // ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // SubmoduleID
   // NamedDecl
   Abv->Add(BitCodeAbbrevOp(0));                       // NameKind = Identifier
@@ -2103,13 +2103,12 @@ void ASTWriter::WriteDeclAbbrevs() {
   // Redeclarable
   Abv->Add(BitCodeAbbrevOp(0));                       // No redeclaration
   // Decl
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
+                           12)); // Packed DeclBits: HasStandaloneLexicalDC,
+                                 // isInvalidDecl, HasAttrs, isImplicit, isUsed,
+                                 // isReferenced, TopLevelDeclInObjCContainer,
+                                 // AccessSpecifier, ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // DeclContext
-  Abv->Add(BitCodeAbbrevOp(0));                       // LexicalDeclContext
-  Abv->Add(BitCodeAbbrevOp(
-      BitCodeAbbrevOp::Fixed,
-      11)); // Packed DeclBits: isInvalidDecl, HasAttrs, isImplicit, isUsed,
-            // isReferenced, TopLevelDeclInObjCContainer, AccessSpecifier,
-            // ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // SubmoduleID
   // NamedDecl
   Abv->Add(BitCodeAbbrevOp(0));                       // NameKind = Identifier
@@ -2122,11 +2121,11 @@ void ASTWriter::WriteDeclAbbrevs() {
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // IdentifierNamespace
   Abv->Add(BitCodeAbbrevOp(
       BitCodeAbbrevOp::Fixed,
-      7)); // Packed Tag Decl Bits: getTagKind, isCompleteDefinition,
-           // EmbeddedInDeclarator, IsFreeStanding, isCompleteDefinitionRequired
+      9)); // Packed Tag Decl Bits: getTagKind, isCompleteDefinition,
+           // EmbeddedInDeclarator, IsFreeStanding,
+           // isCompleteDefinitionRequired, ExtInfoKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // SourceLocation
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // SourceLocation
-  Abv->Add(BitCodeAbbrevOp(0));                         // ExtInfoKind
   // EnumDecl
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // AddTypeRef
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // IntegerType
@@ -2145,13 +2144,12 @@ void ASTWriter::WriteDeclAbbrevs() {
   // Redeclarable
   Abv->Add(BitCodeAbbrevOp(0));                       // No redeclaration
   // Decl
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
+                           12)); // Packed DeclBits: HasStandaloneLexicalDC,
+                                 // isInvalidDecl, HasAttrs, isImplicit, isUsed,
+                                 // isReferenced, TopLevelDeclInObjCContainer,
+                                 // AccessSpecifier, ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // DeclContext
-  Abv->Add(BitCodeAbbrevOp(0));                       // LexicalDeclContext
-  Abv->Add(BitCodeAbbrevOp(
-      BitCodeAbbrevOp::Fixed,
-      11)); // Packed DeclBits: isInvalidDecl, HasAttrs, isImplicit, isUsed,
-            // isReferenced, TopLevelDeclInObjCContainer, AccessSpecifier,
-            // ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // SubmoduleID
   // NamedDecl
   Abv->Add(BitCodeAbbrevOp(0));                       // NameKind = Identifier
@@ -2164,11 +2162,11 @@ void ASTWriter::WriteDeclAbbrevs() {
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // IdentifierNamespace
   Abv->Add(BitCodeAbbrevOp(
       BitCodeAbbrevOp::Fixed,
-      7)); // Packed Tag Decl Bits: getTagKind, isCompleteDefinition,
-           // EmbeddedInDeclarator, IsFreeStanding, isCompleteDefinitionRequired
+      9)); // Packed Tag Decl Bits: getTagKind, isCompleteDefinition,
+           // EmbeddedInDeclarator, IsFreeStanding,
+           // isCompleteDefinitionRequired, ExtInfoKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // SourceLocation
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // SourceLocation
-  Abv->Add(BitCodeAbbrevOp(0));                         // ExtInfoKind
   // RecordDecl
   Abv->Add(BitCodeAbbrevOp(
       BitCodeAbbrevOp::Fixed,
@@ -2194,13 +2192,12 @@ void ASTWriter::WriteDeclAbbrevs() {
   // Redeclarable
   Abv->Add(BitCodeAbbrevOp(0));                       // No redeclaration
   // Decl
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
+                           12)); // Packed DeclBits: HasStandaloneLexicalDC,
+                                 // isInvalidDecl, HasAttrs, isImplicit, isUsed,
+                                 // isReferenced, TopLevelDeclInObjCContainer,
+                                 // AccessSpecifier, ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // DeclContext
-  Abv->Add(BitCodeAbbrevOp(0));                       // LexicalDeclContext
-  Abv->Add(BitCodeAbbrevOp(
-      BitCodeAbbrevOp::Fixed,
-      11)); // Packed DeclBits: isInvalidDecl, HasAttrs, isImplicit, isUsed,
-            // isReferenced, TopLevelDeclInObjCContainer, AccessSpecifier,
-            // ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // SubmoduleID
   // NamedDecl
   Abv->Add(BitCodeAbbrevOp(0));                       // NameKind = Identifier
@@ -2221,10 +2218,9 @@ void ASTWriter::WriteDeclAbbrevs() {
   // ParmVarDecl
   Abv->Add(BitCodeAbbrevOp(
       BitCodeAbbrevOp::Fixed,
-      19)); // Packed Parm Var Decl bits: IsObjCMethodParameter, ScopeDepth,
-            // ScopeIndex, KNRPromoted, HasInheritedDefaultArg
-  Abv->Add(BitCodeAbbrevOp(0));                       // ObjCDeclQualifier
-  Abv->Add(BitCodeAbbrevOp(0));                   // HasUninstantiatedDefaultArg
+      27)); // Packed Parm Var Decl bits: IsObjCMethodParameter, ScopeDepth,
+            // ScopeIndex, ObjCDeclQualifier, KNRPromoted,
+            // HasInheritedDefaultArg, HasUninstantiatedDefaultArg
   // Type Source Info
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Array));
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // TypeLoc
@@ -2236,13 +2232,12 @@ void ASTWriter::WriteDeclAbbrevs() {
   // Redeclarable
   Abv->Add(BitCodeAbbrevOp(0));                       // No redeclaration
   // Decl
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
+                           12)); // Packed DeclBits: HasStandaloneLexicalDC,
+                                 // isInvalidDecl, HasAttrs, isImplicit, isUsed,
+                                 // isReferenced, TopLevelDeclInObjCContainer,
+                                 // AccessSpecifier, ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // DeclContext
-  Abv->Add(BitCodeAbbrevOp(0));                       // LexicalDeclContext
-  Abv->Add(BitCodeAbbrevOp(
-      BitCodeAbbrevOp::Fixed,
-      11)); // Packed DeclBits: isInvalidDecl, HasAttrs, isImplicit, isUsed,
-            // isReferenced, TopLevelDeclInObjCContainer, AccessSpecifier,
-            // ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // SubmoduleID
   // NamedDecl
   Abv->Add(BitCodeAbbrevOp(0));                       // NameKind = Identifier
@@ -2262,13 +2257,12 @@ void ASTWriter::WriteDeclAbbrevs() {
   // Redeclarable
   Abv->Add(BitCodeAbbrevOp(0));                       // No redeclaration
   // Decl
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
+                           12)); // Packed DeclBits: HasStandaloneLexicalDC,
+                                 // isInvalidDecl, HasAttrs, isImplicit, isUsed,
+                                 // isReferenced, TopLevelDeclInObjCContainer,
+                                 // AccessSpecifier, ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // DeclContext
-  Abv->Add(BitCodeAbbrevOp(0));                       // LexicalDeclContext
-  Abv->Add(BitCodeAbbrevOp(
-      BitCodeAbbrevOp::Fixed,
-      11)); // Packed DeclBits: isInvalidDecl, HasAttrs, isImplicit, isUsed,
-            // isReferenced, TopLevelDeclInObjCContainer, AccessSpecifier,
-            // ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // SubmoduleID
   // NamedDecl
   Abv->Add(BitCodeAbbrevOp(0));                       // NameKind = Identifier
@@ -2303,13 +2297,12 @@ void ASTWriter::WriteDeclAbbrevs() {
   // FIXME: Implement abbreviation for other template kinds.
   Abv->Add(BitCodeAbbrevOp(FunctionDecl::TK_NonTemplate)); // TemplateKind
   // Decl
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
+                           12)); // Packed DeclBits: HasStandaloneLexicalDC,
+                                 // isInvalidDecl, HasAttrs, isImplicit, isUsed,
+                                 // isReferenced, TopLevelDeclInObjCContainer,
+                                 // AccessSpecifier, ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // DeclContext
-  Abv->Add(BitCodeAbbrevOp(0));                         // LexicalDeclContext
-  Abv->Add(BitCodeAbbrevOp(
-      BitCodeAbbrevOp::Fixed,
-      11)); // Packed DeclBits: isInvalidDecl, HasAttrs, isImplicit, isUsed,
-            // isReferenced, TopLevelDeclInObjCContainer, AccessSpecifier,
-            // ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // SubmoduleID
   // NamedDecl
   Abv->Add(BitCodeAbbrevOp(DeclarationName::Identifier)); // NameKind
@@ -2353,9 +2346,8 @@ void ASTWriter::WriteDeclAbbrevs() {
   //Stmt
   // Expr
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // Type
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, ExprDependenceBits));
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 3)); //GetValueKind
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 3)); //GetObjectKind
+  // DependenceKind, ValueKind, ObjectKind
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 10));
   //DeclRefExpr
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 1)); //HasQualifier
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 1)); //GetDeclFound
@@ -2374,9 +2366,8 @@ void ASTWriter::WriteDeclAbbrevs() {
   //Stmt
   // Expr
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // Type
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, ExprDependenceBits));
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 3)); //GetValueKind
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 3)); //GetObjectKind
+  // DependenceKind, ValueKind, ObjectKind
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 10));
   //Integer Literal
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // Location
   Abv->Add(BitCodeAbbrevOp(32));                      // Bit Width
@@ -2389,9 +2380,8 @@ void ASTWriter::WriteDeclAbbrevs() {
   //Stmt
   // Expr
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // Type
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, ExprDependenceBits));
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 3)); //GetValueKind
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 3)); //GetObjectKind
+  // DependenceKind, ValueKind, ObjectKind
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 10));
   //Character Literal
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // getValue
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // Location
@@ -2404,9 +2394,8 @@ void ASTWriter::WriteDeclAbbrevs() {
   // Stmt
   // Expr
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // Type
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, ExprDependenceBits));
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 3)); //GetValueKind
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 3)); //GetObjectKind
+  // DependenceKind, ValueKind, ObjectKind
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 10));
   // CastExpr
   Abv->Add(BitCodeAbbrevOp(0)); // PathSize
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 1)); // HasFPFeatures
diff --git a/clang/lib/Serialization/ASTWriterStmt.cpp b/clang/lib/Serialization/ASTWriterStmt.cpp
index 59be6828fafa..8524484ea8a0 100644
--- a/clang/lib/Serialization/ASTWriterStmt.cpp
+++ b/clang/lib/Serialization/ASTWriterStmt.cpp
@@ -549,9 +549,14 @@ void ASTStmtWriter::VisitCapturedStmt(CapturedStmt *S) {
 void ASTStmtWriter::VisitExpr(Expr *E) {
   VisitStmt(E);
   Record.AddTypeRef(E->getType());
-  Record.push_back(E->getDependence());
-  Record.push_back(E->getValueKind());
-  Record.push_back(E->getObjectKind());
+
+  BitsPacker ExprBits;
+
+  ExprBits.addBits(E->getDependence(), /*BitsWidth=*/5);
+  ExprBits.addBits(E->getValueKind(), /*BitsWidth=*/2);
+  ExprBits.addBits(E->getObjectKind(), /*BitsWidth=*/3);
+
+  Record.push_back(ExprBits);
 }
 
 void ASTStmtWriter::VisitConstantExpr(ConstantExpr *E) {
@@ -866,14 +871,20 @@ void ASTStmtWriter::VisitOMPIteratorExpr(OMPIteratorExpr *E) {
 
 void ASTStmtWriter::VisitCallExpr(CallExpr *E) {
   VisitExpr(E);
-  Record.push_back(E->getNumArgs());
-  Record.push_back(E->hasStoredFPFeatures());
+
+  BitsPacker CallExprBits;
+  // 16 bits should be sufficient to store the number args;
+  CallExprBits.addBits(E->getNumArgs(), /*BitsWidth=*/16);
+  CallExprBits.addBit(E->hasStoredFPFeatures());
+  CallExprBits.addBit(static_cast<bool>(E->getADLCallKind()));
+  Record.push_back(CallExprBits);
+
   Record.AddSourceLocation(E->getRParenLoc());
   Record.AddStmt(E->getCallee());
   for (CallExpr::arg_iterator Arg = E->arg_begin(), ArgEnd = E->arg_end();
        Arg != ArgEnd; ++Arg)
     Record.AddStmt(*Arg);
-  Record.push_back(static_cast<unsigned>(E->getADLCallKind()));
+
   if (E->hasStoredFPFeatures())
     Record.push_back(E->getFPFeatures().getAsOpaqueInt());
   Code = serialization::EXPR_CALL;
@@ -1938,14 +1949,19 @@ ASTStmtWriter::VisitCXXUnresolvedConstructExpr(CXXUnresolvedConstructExpr *E) {
 void ASTStmtWriter::VisitOverloadExpr(OverloadExpr *E) {
   VisitExpr(E);
 
-  Record.push_back(E->getNumDecls());
-  Record.push_back(E->hasTemplateKWAndArgsInfo());
+  BitsPacker OverloadExprBits;
+  // 14 Bits should enough to store the number of decls.
+  OverloadExprBits.addBits(E->getNumDecls(), /*BitWidth=*/14);
+  OverloadExprBits.addBit(E->hasTemplateKWAndArgsInfo());
   if (E->hasTemplateKWAndArgsInfo()) {
     const ASTTemplateKWAndArgsInfo &ArgInfo =
         *E->getTrailingASTTemplateKWAndArgsInfo();
-    Record.push_back(ArgInfo.NumTemplateArgs);
+    // 14 Bits should enough to store the number of template args.
+    OverloadExprBits.addBits(ArgInfo.NumTemplateArgs, /*BitWidth=*/14);
+    Record.push_back(OverloadExprBits);
     AddTemplateKWAndArgsInfo(ArgInfo, E->getTrailingTemplateArgumentLoc());
-  }
+  } else
+    Record.push_back(OverloadExprBits);
 
   for (OverloadExpr::decls_iterator OvI = E->decls_begin(),
                                     OvE = E->decls_end();
diff --git a/clang/test/Modules/decl-params-determinisim.m b/clang/test/Modules/decl-params-determinisim.m
index 351403d9af94..9cf37ac4334c 100644
--- a/clang/test/Modules/decl-params-determinisim.m
+++ b/clang/test/Modules/decl-params-determinisim.m
@@ -28,23 +28,23 @@
 
 // CHECK: <TYPE_FUNCTION_PROTO
 // CHECK-NEXT: <DECL_PARM_VAR
-// CHECK-SAME: op6=2
+// CHECK-SAME: op5=2
 // CHECK-NEXT: <DECL_PARM_VAR
-// CHECK-SAME: op6=3
+// CHECK-SAME: op5=3
 // CHECK-NEXT: <DECL_PARM_VAR
-// CHECK-SAME: op6=4
+// CHECK-SAME: op5=4
 // CHECK-NEXT: <DECL_PARM_VAR
-// CHECK-SAME: op6=5
+// CHECK-SAME: op5=5
 
 /// Decl records start at 43
 // CHECK: <DECL_RECORD
-// CHECK-SAME: op6=43
+// CHECK-SAME: op5=43
 // CHECK-NEXT: <DECL_RECORD
-// CHECK-SAME: op6=44
+// CHECK-SAME: op5=44
 // CHECK-NEXT: <DECL_RECORD
-// CHECK-SAME: op6=45
+// CHECK-SAME: op5=45
 // CHECK-NEXT: <DECL_RECORD
-// CHECK-SAME: op6=46
+// CHECK-SAME: op5=46
 
 //--- headers/a.h
 void f(struct A0 *a0,
-- 
GitLab


From af999c4be9f5643724c6f379690ecee4346b2b48 Mon Sep 17 00:00:00 2001
From: wanglei <wanglei@loongson.cn>
Date: Mon, 11 Dec 2023 10:37:22 +0800
Subject: [PATCH 071/349] [LoongArch] Add codegen support for
 [X]VF{MSUB/NMADD/NMSUB}.{S/D} instructions (#74819)

This is similar to single and double-precision floating-point
instructions.
---
 .../LoongArch/LoongArchLASXInstrInfo.td       |  26 +
 .../Target/LoongArch/LoongArchLSXInstrInfo.td |  26 +
 llvm/test/CodeGen/LoongArch/lasx/fma-v4f64.ll | 804 ++++++++++++++++++
 llvm/test/CodeGen/LoongArch/lasx/fma-v8f32.ll | 804 ++++++++++++++++++
 llvm/test/CodeGen/LoongArch/lsx/fma-v2f64.ll  | 804 ++++++++++++++++++
 llvm/test/CodeGen/LoongArch/lsx/fma-v4f32.ll  | 804 ++++++++++++++++++
 6 files changed, 3268 insertions(+)
 create mode 100644 llvm/test/CodeGen/LoongArch/lasx/fma-v4f64.ll
 create mode 100644 llvm/test/CodeGen/LoongArch/lasx/fma-v8f32.ll
 create mode 100644 llvm/test/CodeGen/LoongArch/lsx/fma-v2f64.ll
 create mode 100644 llvm/test/CodeGen/LoongArch/lsx/fma-v4f32.ll

diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
index 8559baa0e525..ec6983d0f487 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
@@ -1455,6 +1455,32 @@ def : Pat<(fma v8f32:$xj, v8f32:$xk, v8f32:$xa),
 def : Pat<(fma v4f64:$xj, v4f64:$xk, v4f64:$xa),
           (XVFMADD_D v4f64:$xj, v4f64:$xk, v4f64:$xa)>;
 
+// XVFMSUB_{S/D}
+def : Pat<(fma v8f32:$xj, v8f32:$xk, (fneg v8f32:$xa)),
+          (XVFMSUB_S v8f32:$xj, v8f32:$xk, v8f32:$xa)>;
+def : Pat<(fma v4f64:$xj, v4f64:$xk, (fneg v4f64:$xa)),
+          (XVFMSUB_D v4f64:$xj, v4f64:$xk, v4f64:$xa)>;
+
+// XVFNMADD_{S/D}
+def : Pat<(fneg (fma v8f32:$xj, v8f32:$xk, v8f32:$xa)),
+          (XVFNMADD_S v8f32:$xj, v8f32:$xk, v8f32:$xa)>;
+def : Pat<(fneg (fma v4f64:$xj, v4f64:$xk, v4f64:$xa)),
+          (XVFNMADD_D v4f64:$xj, v4f64:$xk, v4f64:$xa)>;
+def : Pat<(fma_nsz (fneg v8f32:$xj), v8f32:$xk, (fneg v8f32:$xa)),
+          (XVFNMADD_S v8f32:$xj, v8f32:$xk, v8f32:$xa)>;
+def : Pat<(fma_nsz (fneg v4f64:$xj), v4f64:$xk, (fneg v4f64:$xa)),
+          (XVFNMADD_D v4f64:$xj, v4f64:$xk, v4f64:$xa)>;
+
+// XVFNMSUB_{S/D}
+def : Pat<(fneg (fma v8f32:$xj, v8f32:$xk, (fneg v8f32:$xa))),
+          (XVFNMSUB_S v8f32:$xj, v8f32:$xk, v8f32:$xa)>;
+def : Pat<(fneg (fma v4f64:$xj, v4f64:$xk, (fneg v4f64:$xa))),
+          (XVFNMSUB_D v4f64:$xj, v4f64:$xk, v4f64:$xa)>;
+def : Pat<(fma_nsz (fneg v8f32:$xj), v8f32:$xk, v8f32:$xa),
+          (XVFNMSUB_S v8f32:$xj, v8f32:$xk, v8f32:$xa)>;
+def : Pat<(fma_nsz (fneg v4f64:$xj), v4f64:$xk, v4f64:$xa),
+          (XVFNMSUB_D v4f64:$xj, v4f64:$xk, v4f64:$xa)>;
+
 // XVFSQRT_{S/D}
 defm : PatXrF<fsqrt, "XVFSQRT">;
 
diff --git a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
index 5947f241bb59..e468176885d7 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
@@ -1555,6 +1555,32 @@ def : Pat<(fma v4f32:$vj, v4f32:$vk, v4f32:$va),
 def : Pat<(fma v2f64:$vj, v2f64:$vk, v2f64:$va),
           (VFMADD_D v2f64:$vj, v2f64:$vk, v2f64:$va)>;
 
+// VFMSUB_{S/D}
+def : Pat<(fma v4f32:$vj, v4f32:$vk, (fneg v4f32:$va)),
+          (VFMSUB_S v4f32:$vj, v4f32:$vk, v4f32:$va)>;
+def : Pat<(fma v2f64:$vj, v2f64:$vk, (fneg v2f64:$va)),
+          (VFMSUB_D v2f64:$vj, v2f64:$vk, v2f64:$va)>;
+
+// VFNMADD_{S/D}
+def : Pat<(fneg (fma v4f32:$vj, v4f32:$vk, v4f32:$va)),
+          (VFNMADD_S v4f32:$vj, v4f32:$vk, v4f32:$va)>;
+def : Pat<(fneg (fma v2f64:$vj, v2f64:$vk, v2f64:$va)),
+          (VFNMADD_D v2f64:$vj, v2f64:$vk, v2f64:$va)>;
+def : Pat<(fma_nsz (fneg v4f32:$vj), v4f32:$vk, (fneg v4f32:$va)),
+          (VFNMADD_S v4f32:$vj, v4f32:$vk, v4f32:$va)>;
+def : Pat<(fma_nsz (fneg v2f64:$vj), v2f64:$vk, (fneg v2f64:$va)),
+          (VFNMADD_D v2f64:$vj, v2f64:$vk, v2f64:$va)>;
+
+// VFNMSUB_{S/D}
+def : Pat<(fneg (fma v4f32:$vj, v4f32:$vk, (fneg v4f32:$va))),
+          (VFNMSUB_S v4f32:$vj, v4f32:$vk, v4f32:$va)>;
+def : Pat<(fneg (fma v2f64:$vj, v2f64:$vk, (fneg v2f64:$va))),
+          (VFNMSUB_D v2f64:$vj, v2f64:$vk, v2f64:$va)>;
+def : Pat<(fma_nsz (fneg v4f32:$vj), v4f32:$vk, v4f32:$va),
+          (VFNMSUB_S v4f32:$vj, v4f32:$vk, v4f32:$va)>;
+def : Pat<(fma_nsz (fneg v2f64:$vj), v2f64:$vk, v2f64:$va),
+          (VFNMSUB_D v2f64:$vj, v2f64:$vk, v2f64:$va)>;
+
 // VFSQRT_{S/D}
 defm : PatVrF<fsqrt, "VFSQRT">;
 
diff --git a/llvm/test/CodeGen/LoongArch/lasx/fma-v4f64.ll b/llvm/test/CodeGen/LoongArch/lasx/fma-v4f64.ll
new file mode 100644
index 000000000000..af18c52b096c
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lasx/fma-v4f64.ll
@@ -0,0 +1,804 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx --fp-contract=fast < %s \
+; RUN:   | FileCheck %s --check-prefix=CONTRACT-FAST
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx --fp-contract=on < %s \
+; RUN:   | FileCheck %s --check-prefix=CONTRACT-ON
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx --fp-contract=off < %s \
+; RUN:   | FileCheck %s --check-prefix=CONTRACT-OFF
+
+define void @xvfmadd_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: xvfmadd_d:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfmadd.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: xvfmadd_d:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-ON-NEXT:    xvfmul.d $xr0, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-ON-NEXT:    xvfadd.d $xr0, $xr0, $xr1
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: xvfmadd_d:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfmul.d $xr0, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-OFF-NEXT:    xvfadd.d $xr0, $xr0, $xr1
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x double>, ptr %a0
+  %v1 = load <4 x double>, ptr %a1
+  %v2 = load <4 x double>, ptr %a2
+  %mul = fmul<4 x double> %v0, %v1
+  %add = fadd<4 x double> %mul, %v2
+  store <4 x double> %add, ptr %res
+  ret void
+}
+
+define void @xvfmsub_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: xvfmsub_d:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfmsub.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: xvfmsub_d:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-ON-NEXT:    xvfmul.d $xr0, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-ON-NEXT:    xvfsub.d $xr0, $xr0, $xr1
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: xvfmsub_d:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfmul.d $xr0, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-OFF-NEXT:    xvfsub.d $xr0, $xr0, $xr1
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x double>, ptr %a0
+  %v1 = load <4 x double>, ptr %a1
+  %v2 = load <4 x double>, ptr %a2
+  %mul = fmul<4 x double> %v0, %v1
+  %sub = fsub<4 x double> %mul, %v2
+  store <4 x double> %sub, ptr %res
+  ret void
+}
+
+define void @xvfnmadd_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: xvfnmadd_d:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfnmadd.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: xvfnmadd_d:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-ON-NEXT:    xvfmul.d $xr0, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-ON-NEXT:    xvfadd.d $xr0, $xr0, $xr1
+; CONTRACT-ON-NEXT:    xvbitrevi.d $xr0, $xr0, 63
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: xvfnmadd_d:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfmul.d $xr0, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-OFF-NEXT:    xvfadd.d $xr0, $xr0, $xr1
+; CONTRACT-OFF-NEXT:    xvbitrevi.d $xr0, $xr0, 63
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x double>, ptr %a0
+  %v1 = load <4 x double>, ptr %a1
+  %v2 = load <4 x double>, ptr %a2
+  %mul = fmul<4 x double> %v0, %v1
+  %add = fadd<4 x double> %mul, %v2
+  %negadd = fneg<4 x double> %add
+  store <4 x double> %negadd, ptr %res
+  ret void
+}
+
+define void @xvfnmadd_d_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: xvfnmadd_d_nsz:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfnmadd.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: xvfnmadd_d_nsz:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-ON-NEXT:    xvbitrevi.d $xr1, $xr1, 63
+; CONTRACT-ON-NEXT:    xvfmul.d $xr0, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-ON-NEXT:    xvfsub.d $xr0, $xr0, $xr1
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: xvfnmadd_d_nsz:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-OFF-NEXT:    xvbitrevi.d $xr1, $xr1, 63
+; CONTRACT-OFF-NEXT:    xvfmul.d $xr0, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-OFF-NEXT:    xvfsub.d $xr0, $xr0, $xr1
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x double>, ptr %a0
+  %v1 = load <4 x double>, ptr %a1
+  %v2 = load <4 x double>, ptr %a2
+  %negv0 = fneg nsz<4 x double> %v0
+  %negv2 = fneg nsz<4 x double> %v2
+  %mul = fmul nsz<4 x double> %negv0, %v1
+  %add = fadd nsz<4 x double> %mul, %negv2
+  store <4 x double> %add, ptr %res
+  ret void
+}
+
+;; Check that xvfnmadd.d is not emitted.
+define void @not_xvfnmadd_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: not_xvfnmadd_d:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvbitrevi.d $xr2, $xr2, 63
+; CONTRACT-FAST-NEXT:    xvfmsub.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: not_xvfnmadd_d:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-ON-NEXT:    xvbitrevi.d $xr1, $xr1, 63
+; CONTRACT-ON-NEXT:    xvfmul.d $xr0, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-ON-NEXT:    xvfsub.d $xr0, $xr0, $xr1
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: not_xvfnmadd_d:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-OFF-NEXT:    xvbitrevi.d $xr1, $xr1, 63
+; CONTRACT-OFF-NEXT:    xvfmul.d $xr0, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-OFF-NEXT:    xvfsub.d $xr0, $xr0, $xr1
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x double>, ptr %a0
+  %v1 = load <4 x double>, ptr %a1
+  %v2 = load <4 x double>, ptr %a2
+  %negv0 = fneg<4 x double> %v0
+  %negv2 = fneg<4 x double> %v2
+  %mul = fmul<4 x double> %negv0, %v1
+  %add = fadd<4 x double> %mul, %negv2
+  store <4 x double> %add, ptr %res
+  ret void
+}
+
+define void @xvfnmsub_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: xvfnmsub_d:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfnmsub.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: xvfnmsub_d:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-ON-NEXT:    xvfmul.d $xr0, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-ON-NEXT:    xvfsub.d $xr0, $xr0, $xr1
+; CONTRACT-ON-NEXT:    xvbitrevi.d $xr0, $xr0, 63
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: xvfnmsub_d:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfmul.d $xr0, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-OFF-NEXT:    xvfsub.d $xr0, $xr0, $xr1
+; CONTRACT-OFF-NEXT:    xvbitrevi.d $xr0, $xr0, 63
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x double>, ptr %a0
+  %v1 = load <4 x double>, ptr %a1
+  %v2 = load <4 x double>, ptr %a2
+  %negv2 = fneg<4 x double> %v2
+  %mul = fmul<4 x double> %v0, %v1
+  %add = fadd<4 x double> %mul, %negv2
+  %neg = fneg<4 x double> %add
+  store <4 x double> %neg, ptr %res
+  ret void
+}
+
+define void @xvfnmsub_d_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: xvfnmsub_d_nsz:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfnmsub.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: xvfnmsub_d_nsz:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-ON-NEXT:    xvfmul.d $xr0, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-ON-NEXT:    xvfsub.d $xr0, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: xvfnmsub_d_nsz:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfmul.d $xr0, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-OFF-NEXT:    xvfsub.d $xr0, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x double>, ptr %a0
+  %v1 = load <4 x double>, ptr %a1
+  %v2 = load <4 x double>, ptr %a2
+  %negv0 = fneg nsz<4 x double> %v0
+  %mul = fmul nsz<4 x double> %negv0, %v1
+  %add = fadd nsz<4 x double> %mul, %v2
+  store <4 x double> %add, ptr %res
+  ret void
+}
+
+;; Check that xvfnmsub.d is not emitted.
+define void @not_xvfnmsub_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: not_xvfnmsub_d:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvbitrevi.d $xr2, $xr2, 63
+; CONTRACT-FAST-NEXT:    xvfmadd.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: not_xvfnmsub_d:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-ON-NEXT:    xvfmul.d $xr0, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-ON-NEXT:    xvfsub.d $xr0, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: not_xvfnmsub_d:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfmul.d $xr0, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-OFF-NEXT:    xvfsub.d $xr0, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x double>, ptr %a0
+  %v1 = load <4 x double>, ptr %a1
+  %v2 = load <4 x double>, ptr %a2
+  %negv0 = fneg<4 x double> %v0
+  %mul = fmul<4 x double> %negv0, %v1
+  %add = fadd<4 x double> %mul, %v2
+  store <4 x double> %add, ptr %res
+  ret void
+}
+
+define void @contract_xvfmadd_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: contract_xvfmadd_d:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfmadd.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: contract_xvfmadd_d:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-ON-NEXT:    xvfmadd.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: contract_xvfmadd_d:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfmadd.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x double>, ptr %a0
+  %v1 = load <4 x double>, ptr %a1
+  %v2 = load <4 x double>, ptr %a2
+  %mul = fmul contract <4 x double> %v0, %v1
+  %add = fadd contract <4 x double> %mul, %v2
+  store <4 x double> %add, ptr %res
+  ret void
+}
+
+define void @contract_xvfmsub_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: contract_xvfmsub_d:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfmsub.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: contract_xvfmsub_d:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-ON-NEXT:    xvfmsub.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: contract_xvfmsub_d:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfmsub.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x double>, ptr %a0
+  %v1 = load <4 x double>, ptr %a1
+  %v2 = load <4 x double>, ptr %a2
+  %mul = fmul contract <4 x double> %v0, %v1
+  %sub = fsub contract <4 x double> %mul, %v2
+  store <4 x double> %sub, ptr %res
+  ret void
+}
+
+define void @contract_xvfnmadd_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: contract_xvfnmadd_d:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfnmadd.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: contract_xvfnmadd_d:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-ON-NEXT:    xvfnmadd.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: contract_xvfnmadd_d:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfnmadd.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x double>, ptr %a0
+  %v1 = load <4 x double>, ptr %a1
+  %v2 = load <4 x double>, ptr %a2
+  %mul = fmul contract <4 x double> %v0, %v1
+  %add = fadd contract <4 x double> %mul, %v2
+  %negadd = fneg contract <4 x double> %add
+  store <4 x double> %negadd, ptr %res
+  ret void
+}
+
+define void @contract_xvfnmadd_d_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: contract_xvfnmadd_d_nsz:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfnmadd.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: contract_xvfnmadd_d_nsz:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-ON-NEXT:    xvfnmadd.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: contract_xvfnmadd_d_nsz:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfnmadd.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x double>, ptr %a0
+  %v1 = load <4 x double>, ptr %a1
+  %v2 = load <4 x double>, ptr %a2
+  %negv0 = fneg contract nsz<4 x double> %v0
+  %negv2 = fneg contract nsz<4 x double> %v2
+  %mul = fmul contract nsz<4 x double> %negv0, %v1
+  %add = fadd contract nsz<4 x double> %mul, %negv2
+  store <4 x double> %add, ptr %res
+  ret void
+}
+
+;; Check that xvfnmadd.d is not emitted.
+define void @not_contract_xvfnmadd_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: not_contract_xvfnmadd_d:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvbitrevi.d $xr2, $xr2, 63
+; CONTRACT-FAST-NEXT:    xvfmsub.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: not_contract_xvfnmadd_d:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-ON-NEXT:    xvbitrevi.d $xr2, $xr2, 63
+; CONTRACT-ON-NEXT:    xvfmsub.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: not_contract_xvfnmadd_d:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-OFF-NEXT:    xvbitrevi.d $xr2, $xr2, 63
+; CONTRACT-OFF-NEXT:    xvfmsub.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x double>, ptr %a0
+  %v1 = load <4 x double>, ptr %a1
+  %v2 = load <4 x double>, ptr %a2
+  %negv0 = fneg contract <4 x double> %v0
+  %negv2 = fneg contract <4 x double> %v2
+  %mul = fmul contract <4 x double> %negv0, %v1
+  %add = fadd contract <4 x double> %mul, %negv2
+  store <4 x double> %add, ptr %res
+  ret void
+}
+
+define void @contract_xvfnmsub_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: contract_xvfnmsub_d:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfnmsub.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: contract_xvfnmsub_d:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-ON-NEXT:    xvfnmsub.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: contract_xvfnmsub_d:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfnmsub.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x double>, ptr %a0
+  %v1 = load <4 x double>, ptr %a1
+  %v2 = load <4 x double>, ptr %a2
+  %negv2 = fneg contract <4 x double> %v2
+  %mul = fmul contract <4 x double> %v0, %v1
+  %add = fadd contract <4 x double> %mul, %negv2
+  %neg = fneg contract <4 x double> %add
+  store <4 x double> %neg, ptr %res
+  ret void
+}
+
+define void @contract_xvfnmsub_d_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: contract_xvfnmsub_d_nsz:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfnmsub.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: contract_xvfnmsub_d_nsz:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-ON-NEXT:    xvfnmsub.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: contract_xvfnmsub_d_nsz:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfnmsub.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x double>, ptr %a0
+  %v1 = load <4 x double>, ptr %a1
+  %v2 = load <4 x double>, ptr %a2
+  %negv0 = fneg contract nsz<4 x double> %v0
+  %mul = fmul contract nsz<4 x double> %negv0, %v1
+  %add = fadd contract nsz<4 x double> %mul, %v2
+  store <4 x double> %add, ptr %res
+  ret void
+}
+
+;; Check that xvfnmsub.d is not emitted.
+define void @not_contract_xvfnmsub_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: not_contract_xvfnmsub_d:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvbitrevi.d $xr2, $xr2, 63
+; CONTRACT-FAST-NEXT:    xvfmadd.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: not_contract_xvfnmsub_d:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-ON-NEXT:    xvbitrevi.d $xr2, $xr2, 63
+; CONTRACT-ON-NEXT:    xvfmadd.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: not_contract_xvfnmsub_d:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-OFF-NEXT:    xvbitrevi.d $xr2, $xr2, 63
+; CONTRACT-OFF-NEXT:    xvfmadd.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x double>, ptr %a0
+  %v1 = load <4 x double>, ptr %a1
+  %v2 = load <4 x double>, ptr %a2
+  %negv0 = fneg contract <4 x double> %v0
+  %mul = fmul contract <4 x double> %negv0, %v1
+  %add = fadd contract <4 x double> %mul, %v2
+  store <4 x double> %add, ptr %res
+  ret void
+}
+
+define void @xvfmadd_d_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: xvfmadd_d_contract:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfmadd.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: xvfmadd_d_contract:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-ON-NEXT:    xvfmadd.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: xvfmadd_d_contract:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfmadd.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x double>, ptr %a0
+  %v1 = load <4 x double>, ptr %a1
+  %v2 = load <4 x double>, ptr %a2
+  %mul = fmul contract <4 x double> %v0, %v1
+  %add = fadd contract <4 x double> %mul, %v2
+  store <4 x double> %add, ptr %res
+  ret void
+}
+
+define void @xvfmsub_d_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: xvfmsub_d_contract:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfmsub.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: xvfmsub_d_contract:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-ON-NEXT:    xvfmsub.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: xvfmsub_d_contract:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfmsub.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x double>, ptr %a0
+  %v1 = load <4 x double>, ptr %a1
+  %v2 = load <4 x double>, ptr %a2
+  %mul = fmul contract <4 x double> %v0, %v1
+  %sub = fsub contract <4 x double> %mul, %v2
+  store <4 x double> %sub, ptr %res
+  ret void
+}
+
+define void @xvfnmadd_d_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: xvfnmadd_d_contract:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfnmadd.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: xvfnmadd_d_contract:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-ON-NEXT:    xvfnmadd.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: xvfnmadd_d_contract:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfnmadd.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x double>, ptr %a0
+  %v1 = load <4 x double>, ptr %a1
+  %v2 = load <4 x double>, ptr %a2
+  %mul = fmul contract <4 x double> %v0, %v1
+  %add = fadd contract <4 x double> %mul, %v2
+  %negadd = fneg contract <4 x double> %add
+  store <4 x double> %negadd, ptr %res
+  ret void
+}
+
+define void @xvfnmsub_d_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: xvfnmsub_d_contract:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfnmsub.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: xvfnmsub_d_contract:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-ON-NEXT:    xvfnmsub.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: xvfnmsub_d_contract:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfnmsub.d $xr0, $xr2, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x double>, ptr %a0
+  %v1 = load <4 x double>, ptr %a1
+  %v2 = load <4 x double>, ptr %a2
+  %mul = fmul contract <4 x double> %v0, %v1
+  %negv2 = fneg contract <4 x double> %v2
+  %add = fadd contract <4 x double> %negv2, %mul
+  %negadd = fneg contract <4 x double> %add
+  store <4 x double> %negadd, ptr %res
+  ret void
+}
diff --git a/llvm/test/CodeGen/LoongArch/lasx/fma-v8f32.ll b/llvm/test/CodeGen/LoongArch/lasx/fma-v8f32.ll
new file mode 100644
index 000000000000..b7b3cb3a2e66
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lasx/fma-v8f32.ll
@@ -0,0 +1,804 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx --fp-contract=fast < %s \
+; RUN:   | FileCheck %s --check-prefix=CONTRACT-FAST
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx --fp-contract=on < %s \
+; RUN:   | FileCheck %s --check-prefix=CONTRACT-ON
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx --fp-contract=off < %s \
+; RUN:   | FileCheck %s --check-prefix=CONTRACT-OFF
+
+define void @xvfmadd_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: xvfmadd_s:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfmadd.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: xvfmadd_s:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-ON-NEXT:    xvfmul.s $xr0, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-ON-NEXT:    xvfadd.s $xr0, $xr0, $xr1
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: xvfmadd_s:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfmul.s $xr0, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-OFF-NEXT:    xvfadd.s $xr0, $xr0, $xr1
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <8 x float>, ptr %a0
+  %v1 = load <8 x float>, ptr %a1
+  %v2 = load <8 x float>, ptr %a2
+  %mul = fmul<8 x float> %v0, %v1
+  %add = fadd<8 x float> %mul, %v2
+  store <8 x float> %add, ptr %res
+  ret void
+}
+
+define void @xvfmsub_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: xvfmsub_s:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfmsub.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: xvfmsub_s:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-ON-NEXT:    xvfmul.s $xr0, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-ON-NEXT:    xvfsub.s $xr0, $xr0, $xr1
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: xvfmsub_s:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfmul.s $xr0, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-OFF-NEXT:    xvfsub.s $xr0, $xr0, $xr1
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <8 x float>, ptr %a0
+  %v1 = load <8 x float>, ptr %a1
+  %v2 = load <8 x float>, ptr %a2
+  %mul = fmul<8 x float> %v0, %v1
+  %sub = fsub<8 x float> %mul, %v2
+  store <8 x float> %sub, ptr %res
+  ret void
+}
+
+define void @xvfnmadd_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: xvfnmadd_s:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfnmadd.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: xvfnmadd_s:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-ON-NEXT:    xvfmul.s $xr0, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-ON-NEXT:    xvfadd.s $xr0, $xr0, $xr1
+; CONTRACT-ON-NEXT:    xvbitrevi.w $xr0, $xr0, 31
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: xvfnmadd_s:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfmul.s $xr0, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-OFF-NEXT:    xvfadd.s $xr0, $xr0, $xr1
+; CONTRACT-OFF-NEXT:    xvbitrevi.w $xr0, $xr0, 31
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <8 x float>, ptr %a0
+  %v1 = load <8 x float>, ptr %a1
+  %v2 = load <8 x float>, ptr %a2
+  %mul = fmul<8 x float> %v0, %v1
+  %add = fadd<8 x float> %mul, %v2
+  %negadd = fneg<8 x float> %add
+  store <8 x float> %negadd, ptr %res
+  ret void
+}
+
+define void @xvfnmadd_s_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: xvfnmadd_s_nsz:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfnmadd.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: xvfnmadd_s_nsz:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-ON-NEXT:    xvbitrevi.w $xr1, $xr1, 31
+; CONTRACT-ON-NEXT:    xvfmul.s $xr0, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-ON-NEXT:    xvfsub.s $xr0, $xr0, $xr1
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: xvfnmadd_s_nsz:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-OFF-NEXT:    xvbitrevi.w $xr1, $xr1, 31
+; CONTRACT-OFF-NEXT:    xvfmul.s $xr0, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-OFF-NEXT:    xvfsub.s $xr0, $xr0, $xr1
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <8 x float>, ptr %a0
+  %v1 = load <8 x float>, ptr %a1
+  %v2 = load <8 x float>, ptr %a2
+  %negv0 = fneg nsz<8 x float> %v0
+  %negv2 = fneg nsz<8 x float> %v2
+  %mul = fmul nsz<8 x float> %negv0, %v1
+  %add = fadd nsz<8 x float> %mul, %negv2
+  store <8 x float> %add, ptr %res
+  ret void
+}
+
+;; Check that fnmadd.s is not emitted.
+define void @not_xvfnmadd_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: not_xvfnmadd_s:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvbitrevi.w $xr2, $xr2, 31
+; CONTRACT-FAST-NEXT:    xvfmsub.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: not_xvfnmadd_s:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-ON-NEXT:    xvbitrevi.w $xr1, $xr1, 31
+; CONTRACT-ON-NEXT:    xvfmul.s $xr0, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-ON-NEXT:    xvfsub.s $xr0, $xr0, $xr1
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: not_xvfnmadd_s:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-OFF-NEXT:    xvbitrevi.w $xr1, $xr1, 31
+; CONTRACT-OFF-NEXT:    xvfmul.s $xr0, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-OFF-NEXT:    xvfsub.s $xr0, $xr0, $xr1
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <8 x float>, ptr %a0
+  %v1 = load <8 x float>, ptr %a1
+  %v2 = load <8 x float>, ptr %a2
+  %negv0 = fneg<8 x float> %v0
+  %negv2 = fneg<8 x float> %v2
+  %mul = fmul<8 x float> %negv0, %v1
+  %add = fadd<8 x float> %mul, %negv2
+  store <8 x float> %add, ptr %res
+  ret void
+}
+
+define void @xvfnmsub_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: xvfnmsub_s:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfnmsub.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: xvfnmsub_s:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-ON-NEXT:    xvfmul.s $xr0, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-ON-NEXT:    xvfsub.s $xr0, $xr0, $xr1
+; CONTRACT-ON-NEXT:    xvbitrevi.w $xr0, $xr0, 31
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: xvfnmsub_s:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfmul.s $xr0, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-OFF-NEXT:    xvfsub.s $xr0, $xr0, $xr1
+; CONTRACT-OFF-NEXT:    xvbitrevi.w $xr0, $xr0, 31
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <8 x float>, ptr %a0
+  %v1 = load <8 x float>, ptr %a1
+  %v2 = load <8 x float>, ptr %a2
+  %negv2 = fneg<8 x float> %v2
+  %mul = fmul<8 x float> %v0, %v1
+  %add = fadd<8 x float> %mul, %negv2
+  %neg = fneg<8 x float> %add
+  store <8 x float> %neg, ptr %res
+  ret void
+}
+
+define void @xvfnmsub_s_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: xvfnmsub_s_nsz:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfnmsub.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: xvfnmsub_s_nsz:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-ON-NEXT:    xvfmul.s $xr0, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-ON-NEXT:    xvfsub.s $xr0, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: xvfnmsub_s_nsz:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfmul.s $xr0, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-OFF-NEXT:    xvfsub.s $xr0, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <8 x float>, ptr %a0
+  %v1 = load <8 x float>, ptr %a1
+  %v2 = load <8 x float>, ptr %a2
+  %negv0 = fneg nsz<8 x float> %v0
+  %mul = fmul nsz<8 x float> %negv0, %v1
+  %add = fadd nsz<8 x float> %mul, %v2
+  store <8 x float> %add, ptr %res
+  ret void
+}
+
+;; Check that fnmsub.s is not emitted.
+define void @not_xvfnmsub_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: not_xvfnmsub_s:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvbitrevi.w $xr2, $xr2, 31
+; CONTRACT-FAST-NEXT:    xvfmadd.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: not_xvfnmsub_s:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-ON-NEXT:    xvfmul.s $xr0, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-ON-NEXT:    xvfsub.s $xr0, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: not_xvfnmsub_s:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfmul.s $xr0, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a3, 0
+; CONTRACT-OFF-NEXT:    xvfsub.s $xr0, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <8 x float>, ptr %a0
+  %v1 = load <8 x float>, ptr %a1
+  %v2 = load <8 x float>, ptr %a2
+  %negv0 = fneg<8 x float> %v0
+  %mul = fmul<8 x float> %negv0, %v1
+  %add = fadd<8 x float> %mul, %v2
+  store <8 x float> %add, ptr %res
+  ret void
+}
+
+define void @contract_xvfmadd_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: contract_xvfmadd_s:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfmadd.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: contract_xvfmadd_s:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-ON-NEXT:    xvfmadd.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: contract_xvfmadd_s:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfmadd.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <8 x float>, ptr %a0
+  %v1 = load <8 x float>, ptr %a1
+  %v2 = load <8 x float>, ptr %a2
+  %mul = fmul contract <8 x float> %v0, %v1
+  %add = fadd contract <8 x float> %mul, %v2
+  store <8 x float> %add, ptr %res
+  ret void
+}
+
+define void @contract_xvfmsub_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: contract_xvfmsub_s:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfmsub.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: contract_xvfmsub_s:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-ON-NEXT:    xvfmsub.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: contract_xvfmsub_s:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfmsub.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <8 x float>, ptr %a0
+  %v1 = load <8 x float>, ptr %a1
+  %v2 = load <8 x float>, ptr %a2
+  %mul = fmul contract <8 x float> %v0, %v1
+  %sub = fsub contract <8 x float> %mul, %v2
+  store <8 x float> %sub, ptr %res
+  ret void
+}
+
+define void @contract_xvfnmadd_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: contract_xvfnmadd_s:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfnmadd.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: contract_xvfnmadd_s:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-ON-NEXT:    xvfnmadd.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: contract_xvfnmadd_s:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfnmadd.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <8 x float>, ptr %a0
+  %v1 = load <8 x float>, ptr %a1
+  %v2 = load <8 x float>, ptr %a2
+  %mul = fmul contract <8 x float> %v0, %v1
+  %add = fadd contract <8 x float> %mul, %v2
+  %negadd = fneg contract <8 x float> %add
+  store <8 x float> %negadd, ptr %res
+  ret void
+}
+
+define void @contract_xvfnmadd_s_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: contract_xvfnmadd_s_nsz:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfnmadd.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: contract_xvfnmadd_s_nsz:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-ON-NEXT:    xvfnmadd.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: contract_xvfnmadd_s_nsz:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfnmadd.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <8 x float>, ptr %a0
+  %v1 = load <8 x float>, ptr %a1
+  %v2 = load <8 x float>, ptr %a2
+  %negv0 = fneg contract nsz<8 x float> %v0
+  %negv2 = fneg contract nsz<8 x float> %v2
+  %mul = fmul contract nsz<8 x float> %negv0, %v1
+  %add = fadd contract nsz<8 x float> %mul, %negv2
+  store <8 x float> %add, ptr %res
+  ret void
+}
+
+;; Check that fnmadd.s is not emitted.
+define void @not_contract_xvfnmadd_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: not_contract_xvfnmadd_s:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvbitrevi.w $xr2, $xr2, 31
+; CONTRACT-FAST-NEXT:    xvfmsub.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: not_contract_xvfnmadd_s:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-ON-NEXT:    xvbitrevi.w $xr2, $xr2, 31
+; CONTRACT-ON-NEXT:    xvfmsub.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: not_contract_xvfnmadd_s:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-OFF-NEXT:    xvbitrevi.w $xr2, $xr2, 31
+; CONTRACT-OFF-NEXT:    xvfmsub.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <8 x float>, ptr %a0
+  %v1 = load <8 x float>, ptr %a1
+  %v2 = load <8 x float>, ptr %a2
+  %negv0 = fneg contract <8 x float> %v0
+  %negv2 = fneg contract <8 x float> %v2
+  %mul = fmul contract <8 x float> %negv0, %v1
+  %add = fadd contract <8 x float> %mul, %negv2
+  store <8 x float> %add, ptr %res
+  ret void
+}
+
+define void @contract_xvfnmsub_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: contract_xvfnmsub_s:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfnmsub.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: contract_xvfnmsub_s:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-ON-NEXT:    xvfnmsub.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: contract_xvfnmsub_s:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfnmsub.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <8 x float>, ptr %a0
+  %v1 = load <8 x float>, ptr %a1
+  %v2 = load <8 x float>, ptr %a2
+  %negv2 = fneg contract <8 x float> %v2
+  %mul = fmul contract <8 x float> %v0, %v1
+  %add = fadd contract <8 x float> %mul, %negv2
+  %neg = fneg contract <8 x float> %add
+  store <8 x float> %neg, ptr %res
+  ret void
+}
+
+define void @contract_xvfnmsub_s_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: contract_xvfnmsub_s_nsz:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfnmsub.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: contract_xvfnmsub_s_nsz:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-ON-NEXT:    xvfnmsub.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: contract_xvfnmsub_s_nsz:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfnmsub.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <8 x float>, ptr %a0
+  %v1 = load <8 x float>, ptr %a1
+  %v2 = load <8 x float>, ptr %a2
+  %negv0 = fneg contract nsz<8 x float> %v0
+  %mul = fmul contract nsz<8 x float> %negv0, %v1
+  %add = fadd contract nsz<8 x float> %mul, %v2
+  store <8 x float> %add, ptr %res
+  ret void
+}
+
+;; Check that fnmsub.s is not emitted.
+define void @not_contract_xvfnmsub_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: not_contract_xvfnmsub_s:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvbitrevi.w $xr2, $xr2, 31
+; CONTRACT-FAST-NEXT:    xvfmadd.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: not_contract_xvfnmsub_s:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-ON-NEXT:    xvbitrevi.w $xr2, $xr2, 31
+; CONTRACT-ON-NEXT:    xvfmadd.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: not_contract_xvfnmsub_s:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-OFF-NEXT:    xvbitrevi.w $xr2, $xr2, 31
+; CONTRACT-OFF-NEXT:    xvfmadd.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <8 x float>, ptr %a0
+  %v1 = load <8 x float>, ptr %a1
+  %v2 = load <8 x float>, ptr %a2
+  %negv0 = fneg contract <8 x float> %v0
+  %mul = fmul contract <8 x float> %negv0, %v1
+  %add = fadd contract <8 x float> %mul, %v2
+  store <8 x float> %add, ptr %res
+  ret void
+}
+
+define void @xvfmadd_s_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: xvfmadd_s_contract:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfmadd.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: xvfmadd_s_contract:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-ON-NEXT:    xvfmadd.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: xvfmadd_s_contract:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfmadd.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <8 x float>, ptr %a0
+  %v1 = load <8 x float>, ptr %a1
+  %v2 = load <8 x float>, ptr %a2
+  %mul = fmul contract <8 x float> %v0, %v1
+  %add = fadd contract <8 x float> %mul, %v2
+  store <8 x float> %add, ptr %res
+  ret void
+}
+
+define void @xvfmsub_s_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: xvfmsub_s_contract:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfmsub.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: xvfmsub_s_contract:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-ON-NEXT:    xvfmsub.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: xvfmsub_s_contract:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfmsub.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <8 x float>, ptr %a0
+  %v1 = load <8 x float>, ptr %a1
+  %v2 = load <8 x float>, ptr %a2
+  %mul = fmul contract <8 x float> %v0, %v1
+  %sub = fsub contract <8 x float> %mul, %v2
+  store <8 x float> %sub, ptr %res
+  ret void
+}
+
+define void @xvfnmadd_s_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: xvfnmadd_s_contract:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfnmadd.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: xvfnmadd_s_contract:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-ON-NEXT:    xvfnmadd.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: xvfnmadd_s_contract:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfnmadd.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <8 x float>, ptr %a0
+  %v1 = load <8 x float>, ptr %a1
+  %v2 = load <8 x float>, ptr %a2
+  %mul = fmul contract <8 x float> %v0, %v1
+  %add = fadd contract <8 x float> %mul, %v2
+  %negadd = fneg contract <8 x float> %add
+  store <8 x float> %negadd, ptr %res
+  ret void
+}
+
+define void @xvfnmsub_s_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: xvfnmsub_s_contract:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-FAST-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-FAST-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-FAST-NEXT:    xvfnmsub.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-FAST-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: xvfnmsub_s_contract:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-ON-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-ON-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-ON-NEXT:    xvfnmsub.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-ON-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: xvfnmsub_s_contract:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    xvld $xr0, $a3, 0
+; CONTRACT-OFF-NEXT:    xvld $xr1, $a2, 0
+; CONTRACT-OFF-NEXT:    xvld $xr2, $a1, 0
+; CONTRACT-OFF-NEXT:    xvfnmsub.s $xr0, $xr2, $xr1, $xr0
+; CONTRACT-OFF-NEXT:    xvst $xr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <8 x float>, ptr %a0
+  %v1 = load <8 x float>, ptr %a1
+  %v2 = load <8 x float>, ptr %a2
+  %mul = fmul contract <8 x float> %v0, %v1
+  %negv2 = fneg contract <8 x float> %v2
+  %add = fadd contract <8 x float> %negv2, %mul
+  %negadd = fneg contract <8 x float> %add
+  store <8 x float> %negadd, ptr %res
+  ret void
+}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/fma-v2f64.ll b/llvm/test/CodeGen/LoongArch/lsx/fma-v2f64.ll
new file mode 100644
index 000000000000..8e0459b4afab
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lsx/fma-v2f64.ll
@@ -0,0 +1,804 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx --fp-contract=fast < %s \
+; RUN:   | FileCheck %s --check-prefix=CONTRACT-FAST
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx --fp-contract=on < %s \
+; RUN:   | FileCheck %s --check-prefix=CONTRACT-ON
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx --fp-contract=off < %s \
+; RUN:   | FileCheck %s --check-prefix=CONTRACT-OFF
+
+define void @vfmadd_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: vfmadd_d:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfmadd.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: vfmadd_d:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-ON-NEXT:    vfmul.d $vr0, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-ON-NEXT:    vfadd.d $vr0, $vr0, $vr1
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: vfmadd_d:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-OFF-NEXT:    vfmul.d $vr0, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-OFF-NEXT:    vfadd.d $vr0, $vr0, $vr1
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <2 x double>, ptr %a0
+  %v1 = load <2 x double>, ptr %a1
+  %v2 = load <2 x double>, ptr %a2
+  %mul = fmul<2 x double> %v0, %v1
+  %add = fadd<2 x double> %mul, %v2
+  store <2 x double> %add, ptr %res
+  ret void
+}
+
+define void @vfmsub_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: vfmsub_d:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfmsub.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: vfmsub_d:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-ON-NEXT:    vfmul.d $vr0, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-ON-NEXT:    vfsub.d $vr0, $vr0, $vr1
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: vfmsub_d:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-OFF-NEXT:    vfmul.d $vr0, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-OFF-NEXT:    vfsub.d $vr0, $vr0, $vr1
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <2 x double>, ptr %a0
+  %v1 = load <2 x double>, ptr %a1
+  %v2 = load <2 x double>, ptr %a2
+  %mul = fmul<2 x double> %v0, %v1
+  %sub = fsub<2 x double> %mul, %v2
+  store <2 x double> %sub, ptr %res
+  ret void
+}
+
+define void @vfnmadd_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: vfnmadd_d:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfnmadd.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: vfnmadd_d:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-ON-NEXT:    vfmul.d $vr0, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-ON-NEXT:    vfadd.d $vr0, $vr0, $vr1
+; CONTRACT-ON-NEXT:    vbitrevi.d $vr0, $vr0, 63
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: vfnmadd_d:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-OFF-NEXT:    vfmul.d $vr0, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-OFF-NEXT:    vfadd.d $vr0, $vr0, $vr1
+; CONTRACT-OFF-NEXT:    vbitrevi.d $vr0, $vr0, 63
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <2 x double>, ptr %a0
+  %v1 = load <2 x double>, ptr %a1
+  %v2 = load <2 x double>, ptr %a2
+  %mul = fmul<2 x double> %v0, %v1
+  %add = fadd<2 x double> %mul, %v2
+  %negadd = fneg<2 x double> %add
+  store <2 x double> %negadd, ptr %res
+  ret void
+}
+
+define void @vfnmadd_d_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: vfnmadd_d_nsz:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfnmadd.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: vfnmadd_d_nsz:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-ON-NEXT:    vbitrevi.d $vr1, $vr1, 63
+; CONTRACT-ON-NEXT:    vfmul.d $vr0, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-ON-NEXT:    vfsub.d $vr0, $vr0, $vr1
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: vfnmadd_d_nsz:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-OFF-NEXT:    vbitrevi.d $vr1, $vr1, 63
+; CONTRACT-OFF-NEXT:    vfmul.d $vr0, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-OFF-NEXT:    vfsub.d $vr0, $vr0, $vr1
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <2 x double>, ptr %a0
+  %v1 = load <2 x double>, ptr %a1
+  %v2 = load <2 x double>, ptr %a2
+  %negv0 = fneg nsz<2 x double> %v0
+  %negv2 = fneg nsz<2 x double> %v2
+  %mul = fmul nsz<2 x double> %negv0, %v1
+  %add = fadd nsz<2 x double> %mul, %negv2
+  store <2 x double> %add, ptr %res
+  ret void
+}
+
+;; Check that vfnmadd.d is not emitted.
+define void @not_vfnmadd_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: not_vfnmadd_d:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vbitrevi.d $vr2, $vr2, 63
+; CONTRACT-FAST-NEXT:    vfmsub.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: not_vfnmadd_d:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-ON-NEXT:    vbitrevi.d $vr1, $vr1, 63
+; CONTRACT-ON-NEXT:    vfmul.d $vr0, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-ON-NEXT:    vfsub.d $vr0, $vr0, $vr1
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: not_vfnmadd_d:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-OFF-NEXT:    vbitrevi.d $vr1, $vr1, 63
+; CONTRACT-OFF-NEXT:    vfmul.d $vr0, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-OFF-NEXT:    vfsub.d $vr0, $vr0, $vr1
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <2 x double>, ptr %a0
+  %v1 = load <2 x double>, ptr %a1
+  %v2 = load <2 x double>, ptr %a2
+  %negv0 = fneg<2 x double> %v0
+  %negv2 = fneg<2 x double> %v2
+  %mul = fmul<2 x double> %negv0, %v1
+  %add = fadd<2 x double> %mul, %negv2
+  store <2 x double> %add, ptr %res
+  ret void
+}
+
+define void @vfnmsub_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: vfnmsub_d:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfnmsub.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: vfnmsub_d:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-ON-NEXT:    vfmul.d $vr0, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-ON-NEXT:    vfsub.d $vr0, $vr0, $vr1
+; CONTRACT-ON-NEXT:    vbitrevi.d $vr0, $vr0, 63
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: vfnmsub_d:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-OFF-NEXT:    vfmul.d $vr0, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-OFF-NEXT:    vfsub.d $vr0, $vr0, $vr1
+; CONTRACT-OFF-NEXT:    vbitrevi.d $vr0, $vr0, 63
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <2 x double>, ptr %a0
+  %v1 = load <2 x double>, ptr %a1
+  %v2 = load <2 x double>, ptr %a2
+  %negv2 = fneg<2 x double> %v2
+  %mul = fmul<2 x double> %v0, %v1
+  %add = fadd<2 x double> %mul, %negv2
+  %neg = fneg<2 x double> %add
+  store <2 x double> %neg, ptr %res
+  ret void
+}
+
+define void @vfnmsub_d_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: vfnmsub_d_nsz:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfnmsub.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: vfnmsub_d_nsz:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-ON-NEXT:    vfmul.d $vr0, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-ON-NEXT:    vfsub.d $vr0, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: vfnmsub_d_nsz:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-OFF-NEXT:    vfmul.d $vr0, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-OFF-NEXT:    vfsub.d $vr0, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <2 x double>, ptr %a0
+  %v1 = load <2 x double>, ptr %a1
+  %v2 = load <2 x double>, ptr %a2
+  %negv0 = fneg nsz<2 x double> %v0
+  %mul = fmul nsz<2 x double> %negv0, %v1
+  %add = fadd nsz<2 x double> %mul, %v2
+  store <2 x double> %add, ptr %res
+  ret void
+}
+
+;; Check that vfnmsub.d is not emitted.
+define void @not_vfnmsub_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: not_vfnmsub_d:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vbitrevi.d $vr2, $vr2, 63
+; CONTRACT-FAST-NEXT:    vfmadd.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: not_vfnmsub_d:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-ON-NEXT:    vfmul.d $vr0, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-ON-NEXT:    vfsub.d $vr0, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: not_vfnmsub_d:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-OFF-NEXT:    vfmul.d $vr0, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-OFF-NEXT:    vfsub.d $vr0, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <2 x double>, ptr %a0
+  %v1 = load <2 x double>, ptr %a1
+  %v2 = load <2 x double>, ptr %a2
+  %negv0 = fneg<2 x double> %v0
+  %mul = fmul<2 x double> %negv0, %v1
+  %add = fadd<2 x double> %mul, %v2
+  store <2 x double> %add, ptr %res
+  ret void
+}
+
+define void @contract_vfmadd_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: contract_vfmadd_d:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfmadd.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: contract_vfmadd_d:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-ON-NEXT:    vfmadd.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: contract_vfmadd_d:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-OFF-NEXT:    vfmadd.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <2 x double>, ptr %a0
+  %v1 = load <2 x double>, ptr %a1
+  %v2 = load <2 x double>, ptr %a2
+  %mul = fmul contract <2 x double> %v0, %v1
+  %add = fadd contract <2 x double> %mul, %v2
+  store <2 x double> %add, ptr %res
+  ret void
+}
+
+define void @contract_vfmsub_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: contract_vfmsub_d:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfmsub.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: contract_vfmsub_d:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-ON-NEXT:    vfmsub.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: contract_vfmsub_d:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-OFF-NEXT:    vfmsub.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <2 x double>, ptr %a0
+  %v1 = load <2 x double>, ptr %a1
+  %v2 = load <2 x double>, ptr %a2
+  %mul = fmul contract <2 x double> %v0, %v1
+  %sub = fsub contract <2 x double> %mul, %v2
+  store <2 x double> %sub, ptr %res
+  ret void
+}
+
+define void @contract_vfnmadd_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: contract_vfnmadd_d:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfnmadd.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: contract_vfnmadd_d:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-ON-NEXT:    vfnmadd.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: contract_vfnmadd_d:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-OFF-NEXT:    vfnmadd.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <2 x double>, ptr %a0
+  %v1 = load <2 x double>, ptr %a1
+  %v2 = load <2 x double>, ptr %a2
+  %mul = fmul contract <2 x double> %v0, %v1
+  %add = fadd contract <2 x double> %mul, %v2
+  %negadd = fneg contract <2 x double> %add
+  store <2 x double> %negadd, ptr %res
+  ret void
+}
+
+define void @contract_vfnmadd_d_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: contract_vfnmadd_d_nsz:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfnmadd.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: contract_vfnmadd_d_nsz:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-ON-NEXT:    vfnmadd.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: contract_vfnmadd_d_nsz:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-OFF-NEXT:    vfnmadd.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <2 x double>, ptr %a0
+  %v1 = load <2 x double>, ptr %a1
+  %v2 = load <2 x double>, ptr %a2
+  %negv0 = fneg contract nsz<2 x double> %v0
+  %negv2 = fneg contract nsz<2 x double> %v2
+  %mul = fmul contract nsz<2 x double> %negv0, %v1
+  %add = fadd contract nsz<2 x double> %mul, %negv2
+  store <2 x double> %add, ptr %res
+  ret void
+}
+
+;; Check that vfnmadd.d is not emitted.
+define void @not_contract_vfnmadd_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: not_contract_vfnmadd_d:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vbitrevi.d $vr2, $vr2, 63
+; CONTRACT-FAST-NEXT:    vfmsub.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: not_contract_vfnmadd_d:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-ON-NEXT:    vbitrevi.d $vr2, $vr2, 63
+; CONTRACT-ON-NEXT:    vfmsub.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: not_contract_vfnmadd_d:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-OFF-NEXT:    vbitrevi.d $vr2, $vr2, 63
+; CONTRACT-OFF-NEXT:    vfmsub.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <2 x double>, ptr %a0
+  %v1 = load <2 x double>, ptr %a1
+  %v2 = load <2 x double>, ptr %a2
+  %negv0 = fneg contract <2 x double> %v0
+  %negv2 = fneg contract <2 x double> %v2
+  %mul = fmul contract <2 x double> %negv0, %v1
+  %add = fadd contract <2 x double> %mul, %negv2
+  store <2 x double> %add, ptr %res
+  ret void
+}
+
+define void @contract_vfnmsub_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: contract_vfnmsub_d:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfnmsub.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: contract_vfnmsub_d:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-ON-NEXT:    vfnmsub.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: contract_vfnmsub_d:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-OFF-NEXT:    vfnmsub.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <2 x double>, ptr %a0
+  %v1 = load <2 x double>, ptr %a1
+  %v2 = load <2 x double>, ptr %a2
+  %negv2 = fneg contract <2 x double> %v2
+  %mul = fmul contract <2 x double> %v0, %v1
+  %add = fadd contract <2 x double> %mul, %negv2
+  %neg = fneg contract <2 x double> %add
+  store <2 x double> %neg, ptr %res
+  ret void
+}
+
+define void @contract_vfnmsub_d_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: contract_vfnmsub_d_nsz:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfnmsub.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: contract_vfnmsub_d_nsz:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-ON-NEXT:    vfnmsub.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: contract_vfnmsub_d_nsz:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-OFF-NEXT:    vfnmsub.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <2 x double>, ptr %a0
+  %v1 = load <2 x double>, ptr %a1
+  %v2 = load <2 x double>, ptr %a2
+  %negv0 = fneg contract nsz<2 x double> %v0
+  %mul = fmul contract nsz<2 x double> %negv0, %v1
+  %add = fadd contract nsz<2 x double> %mul, %v2
+  store <2 x double> %add, ptr %res
+  ret void
+}
+
+;; Check that vfnmsub.d is not emitted.
+define void @not_contract_vfnmsub_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: not_contract_vfnmsub_d:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vbitrevi.d $vr2, $vr2, 63
+; CONTRACT-FAST-NEXT:    vfmadd.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: not_contract_vfnmsub_d:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-ON-NEXT:    vbitrevi.d $vr2, $vr2, 63
+; CONTRACT-ON-NEXT:    vfmadd.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: not_contract_vfnmsub_d:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-OFF-NEXT:    vbitrevi.d $vr2, $vr2, 63
+; CONTRACT-OFF-NEXT:    vfmadd.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <2 x double>, ptr %a0
+  %v1 = load <2 x double>, ptr %a1
+  %v2 = load <2 x double>, ptr %a2
+  %negv0 = fneg contract <2 x double> %v0
+  %mul = fmul contract <2 x double> %negv0, %v1
+  %add = fadd contract <2 x double> %mul, %v2
+  store <2 x double> %add, ptr %res
+  ret void
+}
+
+define void @vfmadd_d_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: vfmadd_d_contract:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfmadd.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: vfmadd_d_contract:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-ON-NEXT:    vfmadd.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: vfmadd_d_contract:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-OFF-NEXT:    vfmadd.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <2 x double>, ptr %a0
+  %v1 = load <2 x double>, ptr %a1
+  %v2 = load <2 x double>, ptr %a2
+  %mul = fmul contract <2 x double> %v0, %v1
+  %add = fadd contract <2 x double> %mul, %v2
+  store <2 x double> %add, ptr %res
+  ret void
+}
+
+define void @vfmsub_d_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: vfmsub_d_contract:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfmsub.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: vfmsub_d_contract:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-ON-NEXT:    vfmsub.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: vfmsub_d_contract:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-OFF-NEXT:    vfmsub.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <2 x double>, ptr %a0
+  %v1 = load <2 x double>, ptr %a1
+  %v2 = load <2 x double>, ptr %a2
+  %mul = fmul contract <2 x double> %v0, %v1
+  %sub = fsub contract <2 x double> %mul, %v2
+  store <2 x double> %sub, ptr %res
+  ret void
+}
+
+define void @vfnmadd_d_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: vfnmadd_d_contract:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfnmadd.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: vfnmadd_d_contract:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-ON-NEXT:    vfnmadd.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: vfnmadd_d_contract:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-OFF-NEXT:    vfnmadd.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <2 x double>, ptr %a0
+  %v1 = load <2 x double>, ptr %a1
+  %v2 = load <2 x double>, ptr %a2
+  %mul = fmul contract <2 x double> %v0, %v1
+  %add = fadd contract <2 x double> %mul, %v2
+  %negadd = fneg contract <2 x double> %add
+  store <2 x double> %negadd, ptr %res
+  ret void
+}
+
+define void @vfnmsub_d_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: vfnmsub_d_contract:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfnmsub.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: vfnmsub_d_contract:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-ON-NEXT:    vfnmsub.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: vfnmsub_d_contract:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-OFF-NEXT:    vfnmsub.d $vr0, $vr2, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <2 x double>, ptr %a0
+  %v1 = load <2 x double>, ptr %a1
+  %v2 = load <2 x double>, ptr %a2
+  %mul = fmul contract <2 x double> %v0, %v1
+  %negv2 = fneg contract <2 x double> %v2
+  %add = fadd contract <2 x double> %negv2, %mul
+  %negadd = fneg contract <2 x double> %add
+  store <2 x double> %negadd, ptr %res
+  ret void
+}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/fma-v4f32.ll b/llvm/test/CodeGen/LoongArch/lsx/fma-v4f32.ll
new file mode 100644
index 000000000000..7efbd61c0c4f
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lsx/fma-v4f32.ll
@@ -0,0 +1,804 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx --fp-contract=fast < %s \
+; RUN:   | FileCheck %s --check-prefix=CONTRACT-FAST
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx --fp-contract=on < %s \
+; RUN:   | FileCheck %s --check-prefix=CONTRACT-ON
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx --fp-contract=off < %s \
+; RUN:   | FileCheck %s --check-prefix=CONTRACT-OFF
+
+define void @vfmadd_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: vfmadd_s:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfmadd.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: vfmadd_s:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-ON-NEXT:    vfmul.s $vr0, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-ON-NEXT:    vfadd.s $vr0, $vr0, $vr1
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: vfmadd_s:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-OFF-NEXT:    vfmul.s $vr0, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-OFF-NEXT:    vfadd.s $vr0, $vr0, $vr1
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x float>, ptr %a0
+  %v1 = load <4 x float>, ptr %a1
+  %v2 = load <4 x float>, ptr %a2
+  %mul = fmul<4 x float> %v0, %v1
+  %add = fadd<4 x float> %mul, %v2
+  store <4 x float> %add, ptr %res
+  ret void
+}
+
+define void @vfmsub_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: vfmsub_s:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfmsub.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: vfmsub_s:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-ON-NEXT:    vfmul.s $vr0, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-ON-NEXT:    vfsub.s $vr0, $vr0, $vr1
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: vfmsub_s:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-OFF-NEXT:    vfmul.s $vr0, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-OFF-NEXT:    vfsub.s $vr0, $vr0, $vr1
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x float>, ptr %a0
+  %v1 = load <4 x float>, ptr %a1
+  %v2 = load <4 x float>, ptr %a2
+  %mul = fmul<4 x float> %v0, %v1
+  %sub = fsub<4 x float> %mul, %v2
+  store <4 x float> %sub, ptr %res
+  ret void
+}
+
+define void @vfnmadd_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: vfnmadd_s:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfnmadd.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: vfnmadd_s:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-ON-NEXT:    vfmul.s $vr0, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-ON-NEXT:    vfadd.s $vr0, $vr0, $vr1
+; CONTRACT-ON-NEXT:    vbitrevi.w $vr0, $vr0, 31
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: vfnmadd_s:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-OFF-NEXT:    vfmul.s $vr0, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-OFF-NEXT:    vfadd.s $vr0, $vr0, $vr1
+; CONTRACT-OFF-NEXT:    vbitrevi.w $vr0, $vr0, 31
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x float>, ptr %a0
+  %v1 = load <4 x float>, ptr %a1
+  %v2 = load <4 x float>, ptr %a2
+  %mul = fmul<4 x float> %v0, %v1
+  %add = fadd<4 x float> %mul, %v2
+  %negadd = fneg<4 x float> %add
+  store <4 x float> %negadd, ptr %res
+  ret void
+}
+
+define void @vfnmadd_s_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: vfnmadd_s_nsz:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfnmadd.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: vfnmadd_s_nsz:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-ON-NEXT:    vbitrevi.w $vr1, $vr1, 31
+; CONTRACT-ON-NEXT:    vfmul.s $vr0, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-ON-NEXT:    vfsub.s $vr0, $vr0, $vr1
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: vfnmadd_s_nsz:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-OFF-NEXT:    vbitrevi.w $vr1, $vr1, 31
+; CONTRACT-OFF-NEXT:    vfmul.s $vr0, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-OFF-NEXT:    vfsub.s $vr0, $vr0, $vr1
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x float>, ptr %a0
+  %v1 = load <4 x float>, ptr %a1
+  %v2 = load <4 x float>, ptr %a2
+  %negv0 = fneg nsz<4 x float> %v0
+  %negv2 = fneg nsz<4 x float> %v2
+  %mul = fmul nsz<4 x float> %negv0, %v1
+  %add = fadd nsz<4 x float> %mul, %negv2
+  store <4 x float> %add, ptr %res
+  ret void
+}
+
+;; Check that vfnmadd.s is not emitted.
+define void @not_vfnmadd_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: not_vfnmadd_s:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vbitrevi.w $vr2, $vr2, 31
+; CONTRACT-FAST-NEXT:    vfmsub.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: not_vfnmadd_s:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-ON-NEXT:    vbitrevi.w $vr1, $vr1, 31
+; CONTRACT-ON-NEXT:    vfmul.s $vr0, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-ON-NEXT:    vfsub.s $vr0, $vr0, $vr1
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: not_vfnmadd_s:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-OFF-NEXT:    vbitrevi.w $vr1, $vr1, 31
+; CONTRACT-OFF-NEXT:    vfmul.s $vr0, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-OFF-NEXT:    vfsub.s $vr0, $vr0, $vr1
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x float>, ptr %a0
+  %v1 = load <4 x float>, ptr %a1
+  %v2 = load <4 x float>, ptr %a2
+  %negv0 = fneg<4 x float> %v0
+  %negv2 = fneg<4 x float> %v2
+  %mul = fmul<4 x float> %negv0, %v1
+  %add = fadd<4 x float> %mul, %negv2
+  store <4 x float> %add, ptr %res
+  ret void
+}
+
+define void @vfnmsub_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: vfnmsub_s:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfnmsub.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: vfnmsub_s:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-ON-NEXT:    vfmul.s $vr0, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-ON-NEXT:    vfsub.s $vr0, $vr0, $vr1
+; CONTRACT-ON-NEXT:    vbitrevi.w $vr0, $vr0, 31
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: vfnmsub_s:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-OFF-NEXT:    vfmul.s $vr0, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-OFF-NEXT:    vfsub.s $vr0, $vr0, $vr1
+; CONTRACT-OFF-NEXT:    vbitrevi.w $vr0, $vr0, 31
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x float>, ptr %a0
+  %v1 = load <4 x float>, ptr %a1
+  %v2 = load <4 x float>, ptr %a2
+  %negv2 = fneg<4 x float> %v2
+  %mul = fmul<4 x float> %v0, %v1
+  %add = fadd<4 x float> %mul, %negv2
+  %neg = fneg<4 x float> %add
+  store <4 x float> %neg, ptr %res
+  ret void
+}
+
+define void @vfnmsub_s_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: vfnmsub_s_nsz:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfnmsub.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: vfnmsub_s_nsz:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-ON-NEXT:    vfmul.s $vr0, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-ON-NEXT:    vfsub.s $vr0, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: vfnmsub_s_nsz:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-OFF-NEXT:    vfmul.s $vr0, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-OFF-NEXT:    vfsub.s $vr0, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x float>, ptr %a0
+  %v1 = load <4 x float>, ptr %a1
+  %v2 = load <4 x float>, ptr %a2
+  %negv0 = fneg nsz<4 x float> %v0
+  %mul = fmul nsz<4 x float> %negv0, %v1
+  %add = fadd nsz<4 x float> %mul, %v2
+  store <4 x float> %add, ptr %res
+  ret void
+}
+
+;; Check that vfnmsub.s is not emitted.
+define void @not_vfnmsub_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: not_vfnmsub_s:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vbitrevi.w $vr2, $vr2, 31
+; CONTRACT-FAST-NEXT:    vfmadd.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: not_vfnmsub_s:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-ON-NEXT:    vfmul.s $vr0, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-ON-NEXT:    vfsub.s $vr0, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: not_vfnmsub_s:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a1, 0
+; CONTRACT-OFF-NEXT:    vfmul.s $vr0, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a3, 0
+; CONTRACT-OFF-NEXT:    vfsub.s $vr0, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x float>, ptr %a0
+  %v1 = load <4 x float>, ptr %a1
+  %v2 = load <4 x float>, ptr %a2
+  %negv0 = fneg<4 x float> %v0
+  %mul = fmul<4 x float> %negv0, %v1
+  %add = fadd<4 x float> %mul, %v2
+  store <4 x float> %add, ptr %res
+  ret void
+}
+
+define void @contract_vfmadd_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: contract_vfmadd_s:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfmadd.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: contract_vfmadd_s:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-ON-NEXT:    vfmadd.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: contract_vfmadd_s:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-OFF-NEXT:    vfmadd.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x float>, ptr %a0
+  %v1 = load <4 x float>, ptr %a1
+  %v2 = load <4 x float>, ptr %a2
+  %mul = fmul contract <4 x float> %v0, %v1
+  %add = fadd contract <4 x float> %mul, %v2
+  store <4 x float> %add, ptr %res
+  ret void
+}
+
+define void @contract_vfmsub_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: contract_vfmsub_s:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfmsub.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: contract_vfmsub_s:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-ON-NEXT:    vfmsub.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: contract_vfmsub_s:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-OFF-NEXT:    vfmsub.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x float>, ptr %a0
+  %v1 = load <4 x float>, ptr %a1
+  %v2 = load <4 x float>, ptr %a2
+  %mul = fmul contract <4 x float> %v0, %v1
+  %sub = fsub contract <4 x float> %mul, %v2
+  store <4 x float> %sub, ptr %res
+  ret void
+}
+
+define void @contract_vfnmadd_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: contract_vfnmadd_s:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfnmadd.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: contract_vfnmadd_s:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-ON-NEXT:    vfnmadd.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: contract_vfnmadd_s:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-OFF-NEXT:    vfnmadd.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x float>, ptr %a0
+  %v1 = load <4 x float>, ptr %a1
+  %v2 = load <4 x float>, ptr %a2
+  %mul = fmul contract <4 x float> %v0, %v1
+  %add = fadd contract <4 x float> %mul, %v2
+  %negadd = fneg contract <4 x float> %add
+  store <4 x float> %negadd, ptr %res
+  ret void
+}
+
+define void @contract_vfnmadd_s_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: contract_vfnmadd_s_nsz:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfnmadd.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: contract_vfnmadd_s_nsz:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-ON-NEXT:    vfnmadd.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: contract_vfnmadd_s_nsz:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-OFF-NEXT:    vfnmadd.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x float>, ptr %a0
+  %v1 = load <4 x float>, ptr %a1
+  %v2 = load <4 x float>, ptr %a2
+  %negv0 = fneg contract nsz<4 x float> %v0
+  %negv2 = fneg contract nsz<4 x float> %v2
+  %mul = fmul contract nsz<4 x float> %negv0, %v1
+  %add = fadd contract nsz<4 x float> %mul, %negv2
+  store <4 x float> %add, ptr %res
+  ret void
+}
+
+;; Check that vfnmadd.s is not emitted.
+define void @not_contract_vfnmadd_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: not_contract_vfnmadd_s:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vbitrevi.w $vr2, $vr2, 31
+; CONTRACT-FAST-NEXT:    vfmsub.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: not_contract_vfnmadd_s:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-ON-NEXT:    vbitrevi.w $vr2, $vr2, 31
+; CONTRACT-ON-NEXT:    vfmsub.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: not_contract_vfnmadd_s:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-OFF-NEXT:    vbitrevi.w $vr2, $vr2, 31
+; CONTRACT-OFF-NEXT:    vfmsub.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x float>, ptr %a0
+  %v1 = load <4 x float>, ptr %a1
+  %v2 = load <4 x float>, ptr %a2
+  %negv0 = fneg contract <4 x float> %v0
+  %negv2 = fneg contract <4 x float> %v2
+  %mul = fmul contract <4 x float> %negv0, %v1
+  %add = fadd contract <4 x float> %mul, %negv2
+  store <4 x float> %add, ptr %res
+  ret void
+}
+
+define void @contract_vfnmsub_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: contract_vfnmsub_s:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfnmsub.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: contract_vfnmsub_s:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-ON-NEXT:    vfnmsub.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: contract_vfnmsub_s:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-OFF-NEXT:    vfnmsub.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x float>, ptr %a0
+  %v1 = load <4 x float>, ptr %a1
+  %v2 = load <4 x float>, ptr %a2
+  %negv2 = fneg contract <4 x float> %v2
+  %mul = fmul contract <4 x float> %v0, %v1
+  %add = fadd contract <4 x float> %mul, %negv2
+  %neg = fneg contract <4 x float> %add
+  store <4 x float> %neg, ptr %res
+  ret void
+}
+
+define void @contract_vfnmsub_s_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: contract_vfnmsub_s_nsz:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfnmsub.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: contract_vfnmsub_s_nsz:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-ON-NEXT:    vfnmsub.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: contract_vfnmsub_s_nsz:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-OFF-NEXT:    vfnmsub.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x float>, ptr %a0
+  %v1 = load <4 x float>, ptr %a1
+  %v2 = load <4 x float>, ptr %a2
+  %negv0 = fneg contract nsz<4 x float> %v0
+  %mul = fmul contract nsz<4 x float> %negv0, %v1
+  %add = fadd contract nsz<4 x float> %mul, %v2
+  store <4 x float> %add, ptr %res
+  ret void
+}
+
+;; Check that vfnmsub.s is not emitted.
+define void @not_contract_vfnmsub_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: not_contract_vfnmsub_s:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vbitrevi.w $vr2, $vr2, 31
+; CONTRACT-FAST-NEXT:    vfmadd.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: not_contract_vfnmsub_s:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-ON-NEXT:    vbitrevi.w $vr2, $vr2, 31
+; CONTRACT-ON-NEXT:    vfmadd.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: not_contract_vfnmsub_s:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-OFF-NEXT:    vbitrevi.w $vr2, $vr2, 31
+; CONTRACT-OFF-NEXT:    vfmadd.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x float>, ptr %a0
+  %v1 = load <4 x float>, ptr %a1
+  %v2 = load <4 x float>, ptr %a2
+  %negv0 = fneg contract <4 x float> %v0
+  %mul = fmul contract <4 x float> %negv0, %v1
+  %add = fadd contract <4 x float> %mul, %v2
+  store <4 x float> %add, ptr %res
+  ret void
+}
+
+define void @vfmadd_s_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: vfmadd_s_contract:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfmadd.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: vfmadd_s_contract:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-ON-NEXT:    vfmadd.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: vfmadd_s_contract:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-OFF-NEXT:    vfmadd.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x float>, ptr %a0
+  %v1 = load <4 x float>, ptr %a1
+  %v2 = load <4 x float>, ptr %a2
+  %mul = fmul contract <4 x float> %v0, %v1
+  %add = fadd contract <4 x float> %mul, %v2
+  store <4 x float> %add, ptr %res
+  ret void
+}
+
+define void @vfmsub_s_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: vfmsub_s_contract:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfmsub.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: vfmsub_s_contract:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-ON-NEXT:    vfmsub.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: vfmsub_s_contract:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-OFF-NEXT:    vfmsub.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x float>, ptr %a0
+  %v1 = load <4 x float>, ptr %a1
+  %v2 = load <4 x float>, ptr %a2
+  %mul = fmul contract <4 x float> %v0, %v1
+  %sub = fsub contract <4 x float> %mul, %v2
+  store <4 x float> %sub, ptr %res
+  ret void
+}
+
+define void @vfnmadd_s_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: vfnmadd_s_contract:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfnmadd.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: vfnmadd_s_contract:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-ON-NEXT:    vfnmadd.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: vfnmadd_s_contract:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-OFF-NEXT:    vfnmadd.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x float>, ptr %a0
+  %v1 = load <4 x float>, ptr %a1
+  %v2 = load <4 x float>, ptr %a2
+  %mul = fmul contract <4 x float> %v0, %v1
+  %add = fadd contract <4 x float> %mul, %v2
+  %negadd = fneg contract <4 x float> %add
+  store <4 x float> %negadd, ptr %res
+  ret void
+}
+
+define void @vfnmsub_s_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
+; CONTRACT-FAST-LABEL: vfnmsub_s_contract:
+; CONTRACT-FAST:       # %bb.0: # %entry
+; CONTRACT-FAST-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-FAST-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-FAST-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-FAST-NEXT:    vfnmsub.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-FAST-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-FAST-NEXT:    ret
+;
+; CONTRACT-ON-LABEL: vfnmsub_s_contract:
+; CONTRACT-ON:       # %bb.0: # %entry
+; CONTRACT-ON-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-ON-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-ON-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-ON-NEXT:    vfnmsub.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-ON-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-ON-NEXT:    ret
+;
+; CONTRACT-OFF-LABEL: vfnmsub_s_contract:
+; CONTRACT-OFF:       # %bb.0: # %entry
+; CONTRACT-OFF-NEXT:    vld $vr0, $a3, 0
+; CONTRACT-OFF-NEXT:    vld $vr1, $a2, 0
+; CONTRACT-OFF-NEXT:    vld $vr2, $a1, 0
+; CONTRACT-OFF-NEXT:    vfnmsub.s $vr0, $vr2, $vr1, $vr0
+; CONTRACT-OFF-NEXT:    vst $vr0, $a0, 0
+; CONTRACT-OFF-NEXT:    ret
+entry:
+  %v0 = load <4 x float>, ptr %a0
+  %v1 = load <4 x float>, ptr %a1
+  %v2 = load <4 x float>, ptr %a2
+  %mul = fmul contract <4 x float> %v0, %v1
+  %negv2 = fneg contract <4 x float> %v2
+  %add = fadd contract <4 x float> %negv2, %mul
+  %negadd = fneg contract <4 x float> %add
+  store <4 x float> %negadd, ptr %res
+  ret void
+}
-- 
GitLab


From fdb13cf531d35fa4c6aa71ce23898aa3942ed482 Mon Sep 17 00:00:00 2001
From: sinan <sinan.lin@linux.alibaba.com>
Date: Mon, 11 Dec 2023 10:38:28 +0800
Subject: [PATCH 072/349] [BOLT] Fix local out-of-range stub issue in LongJmp
 (#73918)

If a local stub is out-of-range, at LongJmp we will try to find another
local stub first. However, The original implementation do not work as
expected and it leads to an infinite loop between replaceTargetWithStub
and fixBranches.

After this patch, we first convert the target of BB back to the target
of the local stub, and then look up for other valid local stubs and so
on.
---
 bolt/lib/Passes/LongJmp.cpp | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/bolt/lib/Passes/LongJmp.cpp b/bolt/lib/Passes/LongJmp.cpp
index a81689bc3746..ded0db2cd30b 100644
--- a/bolt/lib/Passes/LongJmp.cpp
+++ b/bolt/lib/Passes/LongJmp.cpp
@@ -202,10 +202,23 @@ LongJmpPass::replaceTargetWithStub(BinaryBasicBlock &BB, MCInst &Inst,
     }
   } else if (LocalStubsIter != Stubs.end() &&
              LocalStubsIter->second.count(TgtBB)) {
-    // If we are replacing a local stub (because it is now out of range),
-    // use its target instead of creating a stub to jump to another stub
+    // The TgtBB and TgtSym now are the local out-of-range stub and its label.
+    // So, we are attempting to restore BB to its previous state without using
+    // this stub.
     TgtSym = BC.MIB->getTargetSymbol(*TgtBB->begin());
-    TgtBB = BB.getSuccessor(TgtSym, BI);
+    assert(TgtSym &&
+           "First instruction is expected to contain a target symbol.");
+    BinaryBasicBlock *TgtBBSucc = TgtBB->getSuccessor(TgtSym, BI);
+
+    // TgtBB might have no successor. e.g. a stub for a function call.
+    if (TgtBBSucc) {
+      BB.replaceSuccessor(TgtBB, TgtBBSucc, BI.Count, BI.MispredictedCount);
+      assert(TgtBB->getExecutionCount() >= BI.Count &&
+             "At least equal or greater than the branch count.");
+      TgtBB->setExecutionCount(TgtBB->getExecutionCount() - BI.Count);
+    }
+
+    TgtBB = TgtBBSucc;
   }
 
   BinaryBasicBlock *StubBB = lookupLocalStub(BB, Inst, TgtSym, DotAddress);
-- 
GitLab


From a52ac7f93a31c664d8943242bdafd719d38f2ffa Mon Sep 17 00:00:00 2001
From: Mircea Trofin <mtrofin@google.com>
Date: Sun, 10 Dec 2023 18:37:34 -0800
Subject: [PATCH 073/349] Fix uninitialized field post PR #74970

---
 llvm/include/llvm/Transforms/Instrumentation/InstrProfiling.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/include/llvm/Transforms/Instrumentation/InstrProfiling.h b/llvm/include/llvm/Transforms/Instrumentation/InstrProfiling.h
index 89fa08685692..95eb3019eab0 100644
--- a/llvm/include/llvm/Transforms/Instrumentation/InstrProfiling.h
+++ b/llvm/include/llvm/Transforms/Instrumentation/InstrProfiling.h
@@ -33,7 +33,7 @@ using LoadStorePair = std::pair<Instruction *, Instruction *>;
 /// instrumentation pass.
 class InstrProfilingLoweringPass
     : public PassInfoMixin<InstrProfilingLoweringPass> {
-  const InstrProfOptions Options;
+  const InstrProfOptions Options = {};
   // Is this lowering for the context-sensitive instrumentation.
   const bool IsCS = false;
 
-- 
GitLab


From 10951050b5f371eb3e7cacce1691c4eb2fe2eab5 Mon Sep 17 00:00:00 2001
From: Jie Fu <jiefu@tencent.com>
Date: Mon, 11 Dec 2023 10:45:56 +0800
Subject: [PATCH 074/349] [clang] Remove unused variable 'ExprDependenceBits'
 in ASTWriterDecl.cpp (NFC)

llvm-project/clang/lib/Serialization/ASTWriterDecl.cpp:2342:12:
 error: unused variable 'ExprDependenceBits' [-Werror,-Wunused-variable]
 2342 |   unsigned ExprDependenceBits = llvm::BitWidth<ExprDependence>;
      |            ^~~~~~~~~~~~~~~~~~
1 error generated.
---
 clang/lib/Serialization/ASTWriterDecl.cpp | 1 -
 1 file changed, 1 deletion(-)

diff --git a/clang/lib/Serialization/ASTWriterDecl.cpp b/clang/lib/Serialization/ASTWriterDecl.cpp
index a5035d500281..43169b2befc6 100644
--- a/clang/lib/Serialization/ASTWriterDecl.cpp
+++ b/clang/lib/Serialization/ASTWriterDecl.cpp
@@ -2339,7 +2339,6 @@ void ASTWriter::WriteDeclAbbrevs() {
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));
   DeclCXXMethodAbbrev = Stream.EmitAbbrev(std::move(Abv));
 
-  unsigned ExprDependenceBits = llvm::BitWidth<ExprDependence>;
   // Abbreviation for EXPR_DECL_REF
   Abv = std::make_shared<BitCodeAbbrev>();
   Abv->Add(BitCodeAbbrevOp(serialization::EXPR_DECL_REF));
-- 
GitLab


From d860710905d77e496b579c8aa6d3f36695cf14cf Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN <sunshaoce@outlook.com>
Date: Mon, 11 Dec 2023 10:55:27 +0800
Subject: [PATCH 075/349] [NFC][VPlan] Simplify VPValue::removeUser (#74708)

Replaced explicit loops with find + erase.
---
 llvm/lib/Transforms/Vectorize/VPlanValue.h | 13 +++----------
 1 file changed, 3 insertions(+), 10 deletions(-)

diff --git a/llvm/lib/Transforms/Vectorize/VPlanValue.h b/llvm/lib/Transforms/Vectorize/VPlanValue.h
index e5ca52755dd2..116acad8e8f3 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanValue.h
+++ b/llvm/lib/Transforms/Vectorize/VPlanValue.h
@@ -121,18 +121,11 @@ public:
 
   /// Remove a single \p User from the list of users.
   void removeUser(VPUser &User) {
-    bool Found = false;
     // The same user can be added multiple times, e.g. because the same VPValue
     // is used twice by the same VPUser. Remove a single one.
-    erase_if(Users, [&User, &Found](VPUser *Other) {
-      if (Found)
-        return false;
-      if (Other == &User) {
-        Found = true;
-        return true;
-      }
-      return false;
-    });
+    auto *I = find(Users, &User);
+    if (I != Users.end())
+      Users.erase(I);
   }
 
   typedef SmallVectorImpl<VPUser *>::iterator user_iterator;
-- 
GitLab


From 9d3ea5a06abe08fa37053b825b3a1510d96bb7fb Mon Sep 17 00:00:00 2001
From: Nathan Ridge <zeratul976@hotmail.com>
Date: Sun, 10 Dec 2023 22:05:51 -0500
Subject: [PATCH 076/349] [clangd] Initialize HighlightingsBuilder::Resolver
 (#74971)

---
 clang-tools-extra/clangd/SemanticHighlighting.cpp | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/clang-tools-extra/clangd/SemanticHighlighting.cpp b/clang-tools-extra/clangd/SemanticHighlighting.cpp
index 49e479abf456..37939d36425a 100644
--- a/clang-tools-extra/clangd/SemanticHighlighting.cpp
+++ b/clang-tools-extra/clangd/SemanticHighlighting.cpp
@@ -418,7 +418,8 @@ class HighlightingsBuilder {
 public:
   HighlightingsBuilder(const ParsedAST &AST, const HighlightingFilter &Filter)
       : TB(AST.getTokens()), SourceMgr(AST.getSourceManager()),
-        LangOpts(AST.getLangOpts()), Filter(Filter) {}
+        LangOpts(AST.getLangOpts()), Filter(Filter),
+        Resolver(AST.getHeuristicResolver()) {}
 
   HighlightingToken &addToken(SourceLocation Loc, HighlightingKind Kind) {
     auto Range = getRangeForSourceLocation(Loc);
@@ -589,7 +590,7 @@ private:
   HighlightingFilter Filter;
   std::vector<HighlightingToken> Tokens;
   std::map<Range, llvm::SmallVector<HighlightingModifier, 1>> ExtraModifiers;
-  const HeuristicResolver *Resolver = nullptr;
+  const HeuristicResolver *Resolver;
   // returned from addToken(InvalidLoc)
   HighlightingToken InvalidHighlightingToken;
 };
-- 
GitLab


From fc715e4cd942612a091097339841733757b53824 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ningning=20Shi=28=E5=8F=B2=E5=AE=81=E5=AE=81=29?=
 <shiningning@iscas.ac.cn>
Date: Mon, 11 Dec 2023 11:08:07 +0800
Subject: [PATCH 077/349] [CodeGen][MachineScheduler][NFC]Update some comments
 of scheduler (#74705)

The member functions of ScheduleDAGMI are called back from
PostMachineScheduler::runOnMachineFunction, instead of
MachineScheduler::runOnMachineFunction.
---
 llvm/include/llvm/CodeGen/SchedulerRegistry.h |  2 +-
 llvm/lib/CodeGen/MachineScheduler.cpp         | 12 ++++++------
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/SchedulerRegistry.h b/llvm/include/llvm/CodeGen/SchedulerRegistry.h
index 0c356e62ae4e..cf648d1316c9 100644
--- a/llvm/include/llvm/CodeGen/SchedulerRegistry.h
+++ b/llvm/include/llvm/CodeGen/SchedulerRegistry.h
@@ -63,7 +63,7 @@ public:
 ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
                                                CodeGenOptLevel OptLevel);
 
-/// createBURRListDAGScheduler - This creates a bottom up list scheduler that
+/// createSourceListDAGScheduler - This creates a bottom up list scheduler that
 /// schedules nodes in source code order when possible.
 ScheduleDAGSDNodes *createSourceListDAGScheduler(SelectionDAGISel *IS,
                                                  CodeGenOptLevel OptLevel);
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index c51ef33bfe54..886137d86f87 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -747,9 +747,9 @@ void ScheduleDAGMI::finishBlock() {
   ScheduleDAGInstrs::finishBlock();
 }
 
-/// enterRegion - Called back from MachineScheduler::runOnMachineFunction after
-/// crossing a scheduling boundary. [begin, end) includes all instructions in
-/// the region, including the boundary itself and single-instruction regions
+/// enterRegion - Called back from PostMachineScheduler::runOnMachineFunction
+/// after crossing a scheduling boundary. [begin, end) includes all instructions
+/// in the region, including the boundary itself and single-instruction regions
 /// that don't get scheduled.
 void ScheduleDAGMI::enterRegion(MachineBasicBlock *bb,
                                      MachineBasicBlock::iterator begin,
@@ -793,9 +793,9 @@ bool ScheduleDAGMI::checkSchedLimit() {
 }
 
 /// Per-region scheduling driver, called back from
-/// MachineScheduler::runOnMachineFunction. This is a simplified driver that
-/// does not consider liveness or register pressure. It is useful for PostRA
-/// scheduling and potentially other custom schedulers.
+/// PostMachineScheduler::runOnMachineFunction. This is a simplified driver
+/// that does not consider liveness or register pressure. It is useful for
+/// PostRA scheduling and potentially other custom schedulers.
 void ScheduleDAGMI::schedule() {
   LLVM_DEBUG(dbgs() << "ScheduleDAGMI::schedule starting\n");
   LLVM_DEBUG(SchedImpl->dumpPolicy());
-- 
GitLab


From d1a83ff3e0274f26746e874d480c866bec3818d6 Mon Sep 17 00:00:00 2001
From: paperchalice <liujunchang97@outlook.com>
Date: Mon, 11 Dec 2023 13:55:27 +0800
Subject: [PATCH 078/349] [CodeGen] Rename `winehprepare` -> `win-eh-prepare`
 (#75024)

Forgot to rename `winehprepare` for legacy pass when port this pass to
new passmanager.
---
 llvm/lib/CodeGen/WinEHPrepare.cpp                | 4 ++--
 llvm/test/CodeGen/WebAssembly/wasm-eh-prepare.ll | 4 ++--
 llvm/test/CodeGen/WinEH/wineh-asm.ll             | 2 +-
 llvm/test/CodeGen/WinEH/wineh-cloning.ll         | 2 +-
 llvm/test/CodeGen/WinEH/wineh-demotion.ll        | 2 +-
 llvm/test/CodeGen/WinEH/wineh-no-demotion.ll     | 2 +-
 6 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/llvm/lib/CodeGen/WinEHPrepare.cpp b/llvm/lib/CodeGen/WinEHPrepare.cpp
index 347bada6f69d..bd14e8104a6a 100644
--- a/llvm/lib/CodeGen/WinEHPrepare.cpp
+++ b/llvm/lib/CodeGen/WinEHPrepare.cpp
@@ -120,8 +120,8 @@ PreservedAnalyses WinEHPreparePass::run(Function &F,
 }
 
 char WinEHPrepare::ID = 0;
-INITIALIZE_PASS(WinEHPrepare, "winehprepare", "Prepare Windows exceptions",
-                false, false)
+INITIALIZE_PASS(WinEHPrepare, DEBUG_TYPE, "Prepare Windows exceptions", false,
+                false)
 
 FunctionPass *llvm::createWinEHPass(bool DemoteCatchSwitchPHIOnly) {
   return new WinEHPrepare(DemoteCatchSwitchPHIOnly);
diff --git a/llvm/test/CodeGen/WebAssembly/wasm-eh-prepare.ll b/llvm/test/CodeGen/WebAssembly/wasm-eh-prepare.ll
index e3de25101738..bd577e387c72 100644
--- a/llvm/test/CodeGen/WebAssembly/wasm-eh-prepare.ll
+++ b/llvm/test/CodeGen/WebAssembly/wasm-eh-prepare.ll
@@ -1,5 +1,5 @@
-; RUN: opt < %s -winehprepare -demote-catchswitch-only -wasm-eh-prepare -S | FileCheck %s
-; RUN: opt < %s -winehprepare -demote-catchswitch-only -wasm-eh-prepare -S --mattr=+atomics,+bulk-memory | FileCheck %s
+; RUN: opt < %s -win-eh-prepare -demote-catchswitch-only -wasm-eh-prepare -S | FileCheck %s
+; RUN: opt < %s -win-eh-prepare -demote-catchswitch-only -wasm-eh-prepare -S --mattr=+atomics,+bulk-memory | FileCheck %s
 ; RUN: opt < %s -passes='win-eh-prepare<demote-catchswitch-only>,wasm-eh-prepare' -S | FileCheck %s
 ; RUN: opt < %s -passes='win-eh-prepare<demote-catchswitch-only>,wasm-eh-prepare' -S --mattr=+atomics,+bulk-memory | FileCheck %s
 
diff --git a/llvm/test/CodeGen/WinEH/wineh-asm.ll b/llvm/test/CodeGen/WinEH/wineh-asm.ll
index 00bb6ccb0a26..7aa29bb2be45 100644
--- a/llvm/test/CodeGen/WinEH/wineh-asm.ll
+++ b/llvm/test/CodeGen/WinEH/wineh-asm.ll
@@ -1,4 +1,4 @@
-; RUN: opt -winehprepare < %s
+; RUN: opt -win-eh-prepare < %s
 ; RUN: opt -passes=win-eh-prepare < %s
 
 target triple = "x86_64-pc-windows-msvc"
diff --git a/llvm/test/CodeGen/WinEH/wineh-cloning.ll b/llvm/test/CodeGen/WinEH/wineh-cloning.ll
index 9a006326fed6..5df2eb26ead9 100644
--- a/llvm/test/CodeGen/WinEH/wineh-cloning.ll
+++ b/llvm/test/CodeGen/WinEH/wineh-cloning.ll
@@ -1,4 +1,4 @@
-; RUN: opt -mtriple=x86_64-pc-windows-msvc -S -winehprepare  < %s | FileCheck %s
+; RUN: opt -mtriple=x86_64-pc-windows-msvc -S -win-eh-prepare  < %s | FileCheck %s
 ; RUN: opt -mtriple=x86_64-pc-windows-msvc -S -passes=win-eh-prepare  < %s | FileCheck %s
 
 declare i32 @__CxxFrameHandler3(...)
diff --git a/llvm/test/CodeGen/WinEH/wineh-demotion.ll b/llvm/test/CodeGen/WinEH/wineh-demotion.ll
index 326bb2d5f874..36a21e29f9c3 100644
--- a/llvm/test/CodeGen/WinEH/wineh-demotion.ll
+++ b/llvm/test/CodeGen/WinEH/wineh-demotion.ll
@@ -1,4 +1,4 @@
-; RUN: opt -mtriple=x86_64-pc-windows-msvc -S -winehprepare  < %s | FileCheck %s
+; RUN: opt -mtriple=x86_64-pc-windows-msvc -S -win-eh-prepare  < %s | FileCheck %s
 ; RUN: opt -mtriple=x86_64-pc-windows-msvc -S -passes=win-eh-prepare  < %s | FileCheck %s
 
 declare i32 @__CxxFrameHandler3(...)
diff --git a/llvm/test/CodeGen/WinEH/wineh-no-demotion.ll b/llvm/test/CodeGen/WinEH/wineh-no-demotion.ll
index eebaf6d1c5be..d4667db97cc1 100644
--- a/llvm/test/CodeGen/WinEH/wineh-no-demotion.ll
+++ b/llvm/test/CodeGen/WinEH/wineh-no-demotion.ll
@@ -1,4 +1,4 @@
-; RUN: opt -mtriple=x86_64-pc-windows-msvc -S -winehprepare -disable-demotion -disable-cleanups < %s | FileCheck %s
+; RUN: opt -mtriple=x86_64-pc-windows-msvc -S -win-eh-prepare -disable-demotion -disable-cleanups < %s | FileCheck %s
 ; RUN: opt -mtriple=x86_64-pc-windows-msvc -S -passes=win-eh-prepare -disable-demotion -disable-cleanups < %s | FileCheck %s
 
 declare i32 @__CxxFrameHandler3(...)
-- 
GitLab


From 8c334627818437180176b16b1932b2a26372d8ae Mon Sep 17 00:00:00 2001
From: Chuanqi Xu <yedeng.yd@linux.alibaba.com>
Date: Mon, 11 Dec 2023 14:06:13 +0800
Subject: [PATCH 079/349] Revert "[NFC] [Serialization] Packing more bits"

This reverts commit 9406ea3fe32e59a7d28de0dcbd0317b4cdfa4c62.

There are build bots complaining this. Revert it first to try to keep
the bots green.
---
 clang/lib/Serialization/ASTReaderDecl.cpp     |  21 +--
 clang/lib/Serialization/ASTReaderStmt.cpp     |  72 ++++----
 clang/lib/Serialization/ASTWriterDecl.cpp     | 155 ++++++++++--------
 clang/lib/Serialization/ASTWriterStmt.cpp     |  36 ++--
 clang/test/Modules/decl-params-determinisim.m |  16 +-
 5 files changed, 138 insertions(+), 162 deletions(-)

diff --git a/clang/lib/Serialization/ASTReaderDecl.cpp b/clang/lib/Serialization/ASTReaderDecl.cpp
index 7140a14aefbf..bc16cfc67a24 100644
--- a/clang/lib/Serialization/ASTReaderDecl.cpp
+++ b/clang/lib/Serialization/ASTReaderDecl.cpp
@@ -583,9 +583,6 @@ void ASTDeclReader::Visit(Decl *D) {
 }
 
 void ASTDeclReader::VisitDecl(Decl *D) {
-  BitsUnpacker DeclBits(Record.readInt());
-  bool HasStandaloneLexicalDC = DeclBits.getNextBit();
-
   if (D->isTemplateParameter() || D->isTemplateParameterPack() ||
       isa<ParmVarDecl, ObjCTypeParamDecl>(D)) {
     // We don't want to deserialize the DeclContext of a template
@@ -595,8 +592,7 @@ void ASTDeclReader::VisitDecl(Decl *D) {
     // return type of the function).  Use the translation unit DeclContext as a
     // placeholder.
     GlobalDeclID SemaDCIDForTemplateParmDecl = readDeclID();
-    GlobalDeclID LexicalDCIDForTemplateParmDecl =
-        HasStandaloneLexicalDC ? readDeclID() : 0;
+    GlobalDeclID LexicalDCIDForTemplateParmDecl = readDeclID();
     if (!LexicalDCIDForTemplateParmDecl)
       LexicalDCIDForTemplateParmDecl = SemaDCIDForTemplateParmDecl;
     Reader.addPendingDeclContextInfo(D,
@@ -605,8 +601,7 @@ void ASTDeclReader::VisitDecl(Decl *D) {
     D->setDeclContext(Reader.getContext().getTranslationUnitDecl());
   } else {
     auto *SemaDC = readDeclAs<DeclContext>();
-    auto *LexicalDC =
-        HasStandaloneLexicalDC ? readDeclAs<DeclContext>() : nullptr;
+    auto *LexicalDC = readDeclAs<DeclContext>();
     if (!LexicalDC)
       LexicalDC = SemaDC;
     // If the context is a class, we might not have actually merged it yet, in
@@ -623,6 +618,7 @@ void ASTDeclReader::VisitDecl(Decl *D) {
   }
   D->setLocation(ThisDeclLoc);
 
+  BitsUnpacker DeclBits(Record.readInt());
   D->InvalidDecl = DeclBits.getNextBit();
   bool HasAttrs = DeclBits.getNextBit();
   D->setImplicit(DeclBits.getNextBit());
@@ -769,7 +765,7 @@ ASTDeclReader::RedeclarableResult ASTDeclReader::VisitTagDecl(TagDecl *TD) {
   TD->setCompleteDefinitionRequired(TagDeclBits.getNextBit());
   TD->setBraceRange(readSourceRange());
 
-  switch (TagDeclBits.getNextBits(/*Width=*/2)) {
+  switch (Record.readInt()) {
   case 0:
     break;
   case 1: { // ExtInfo
@@ -1093,8 +1089,7 @@ void ASTDeclReader::VisitFunctionDecl(FunctionDecl *FD) {
   FD->setCachedLinkage((Linkage)FunctionDeclBits.getNextBits(/*Width=*/3));
 
   FD->EndRangeLoc = readSourceLocation();
-  if (FD->isExplicitlyDefaulted())
-    FD->setDefaultLoc(readSourceLocation());
+  FD->setDefaultLoc(readSourceLocation());
 
   FD->ODRHash = Record.readInt();
   FD->setHasODRHash(true);
@@ -1708,7 +1703,7 @@ void ASTDeclReader::VisitParmVarDecl(ParmVarDecl *PD) {
   unsigned isObjCMethodParam = ParmVarDeclBits.getNextBit();
   unsigned scopeDepth = ParmVarDeclBits.getNextBits(/*Width=*/7);
   unsigned scopeIndex = ParmVarDeclBits.getNextBits(/*Width=*/8);
-  unsigned declQualifier = ParmVarDeclBits.getNextBits(/*Width=*/7);
+  unsigned declQualifier = Record.readInt();
   if (isObjCMethodParam) {
     assert(scopeDepth == 0);
     PD->setObjCMethodScopeInfo(scopeIndex);
@@ -1721,9 +1716,7 @@ void ASTDeclReader::VisitParmVarDecl(ParmVarDecl *PD) {
   PD->ParmVarDeclBits.HasInheritedDefaultArg = ParmVarDeclBits.getNextBit();
   if (ParmVarDeclBits.getNextBit()) // hasUninstantiatedDefaultArg.
     PD->setUninstantiatedDefaultArg(Record.readExpr());
-
-  if (ParmVarDeclBits.getNextBit()) // Valid explicit object parameter
-    PD->ExplicitObjectParameterIntroducerLoc = Record.readSourceLocation();
+  PD->ExplicitObjectParameterIntroducerLoc = Record.readSourceLocation();
 
   // FIXME: If this is a redeclaration of a function from another module, handle
   // inheritance of default arguments.
diff --git a/clang/lib/Serialization/ASTReaderStmt.cpp b/clang/lib/Serialization/ASTReaderStmt.cpp
index 865322ec0782..d7d0c0e5bb21 100644
--- a/clang/lib/Serialization/ASTReaderStmt.cpp
+++ b/clang/lib/Serialization/ASTReaderStmt.cpp
@@ -108,7 +108,7 @@ namespace clang {
 
     /// The number of record fields required for the Expr class
     /// itself.
-    static const unsigned NumExprFields = NumStmtFields + 2;
+    static const unsigned NumExprFields = NumStmtFields + 4;
 
     /// Read and initialize a ExplicitTemplateArgumentList structure.
     void ReadTemplateKWAndArgsInfo(ASTTemplateKWAndArgsInfo &Args,
@@ -524,13 +524,9 @@ void ASTStmtReader::VisitCapturedStmt(CapturedStmt *S) {
 void ASTStmtReader::VisitExpr(Expr *E) {
   VisitStmt(E);
   E->setType(Record.readType());
-  BitsUnpacker ExprBits(Record.readInt());
-  E->setDependence(
-      static_cast<ExprDependence>(ExprBits.getNextBits(/*Width=*/5)));
-  E->setValueKind(
-      static_cast<ExprValueKind>(ExprBits.getNextBits(/*Width=*/2)));
-  E->setObjectKind(
-      static_cast<ExprObjectKind>(ExprBits.getNextBits(/*Width=*/3)));
+  E->setDependence(static_cast<ExprDependence>(Record.readInt()));
+  E->setValueKind(static_cast<ExprValueKind>(Record.readInt()));
+  E->setObjectKind(static_cast<ExprObjectKind>(Record.readInt()));
   assert(Record.getIdx() == NumExprFields &&
          "Incorrect expression field count");
 }
@@ -999,19 +995,14 @@ void ASTStmtReader::VisitOMPIteratorExpr(OMPIteratorExpr *E) {
 
 void ASTStmtReader::VisitCallExpr(CallExpr *E) {
   VisitExpr(E);
-
-  BitsUnpacker CallExprBits = Record.readInt();
-
-  unsigned NumArgs = CallExprBits.getNextBits(/*Width=*/16);
-  bool HasFPFeatures = CallExprBits.getNextBit();
-  E->setADLCallKind(
-      static_cast<CallExpr::ADLCallKind>(CallExprBits.getNextBit()));
+  unsigned NumArgs = Record.readInt();
+  bool HasFPFeatures = Record.readInt();
   assert((NumArgs == E->getNumArgs()) && "Wrong NumArgs!");
   E->setRParenLoc(readSourceLocation());
   E->setCallee(Record.readSubExpr());
   for (unsigned I = 0; I != NumArgs; ++I)
     E->setArg(I, Record.readSubExpr());
-
+  E->setADLCallKind(static_cast<CallExpr::ADLCallKind>(Record.readInt()));
   if (HasFPFeatures)
     E->setStoredFPFeatures(
         FPOptionsOverride::getFromOpaqueInt(Record.readInt()));
@@ -2022,15 +2013,14 @@ ASTStmtReader::VisitCXXUnresolvedConstructExpr(CXXUnresolvedConstructExpr *E) {
 void ASTStmtReader::VisitOverloadExpr(OverloadExpr *E) {
   VisitExpr(E);
 
-  BitsUnpacker OverloadExprBits = Record.readInt();
-  unsigned NumResults = OverloadExprBits.getNextBits(/*Width=*/14);
-  bool HasTemplateKWAndArgsInfo = OverloadExprBits.getNextBit();
+  unsigned NumResults = Record.readInt();
+  bool HasTemplateKWAndArgsInfo = Record.readInt();
   assert((E->getNumDecls() == NumResults) && "Wrong NumResults!");
   assert((E->hasTemplateKWAndArgsInfo() == HasTemplateKWAndArgsInfo) &&
          "Wrong HasTemplateKWAndArgsInfo!");
 
   if (HasTemplateKWAndArgsInfo) {
-    unsigned NumTemplateArgs = OverloadExprBits.getNextBits(/*Width=*/14);
+    unsigned NumTemplateArgs = Record.readInt();
     ReadTemplateKWAndArgsInfo(*E->getTrailingASTTemplateKWAndArgsInfo(),
                               E->getTrailingTemplateArgumentLoc(),
                               NumTemplateArgs);
@@ -3034,9 +3024,8 @@ Stmt *ASTReader::ReadStmtFromStream(ModuleFile &F) {
 
     case EXPR_CALL:
       S = CallExpr::CreateEmpty(
-          Context, /*NumArgs=*/Record[ASTStmtReader::NumExprFields] & 0xffff,
-          /*HasFPFeatures=*/
-          ((Record[ASTStmtReader::NumExprFields] >> 16) & 0x1), Empty);
+          Context, /*NumArgs=*/Record[ASTStmtReader::NumExprFields],
+          /*HasFPFeatures=*/Record[ASTStmtReader::NumExprFields + 1], Empty);
       break;
 
     case EXPR_RECOVERY:
@@ -3777,16 +3766,14 @@ Stmt *ASTReader::ReadStmtFromStream(ModuleFile &F) {
 
     case EXPR_CXX_OPERATOR_CALL:
       S = CXXOperatorCallExpr::CreateEmpty(
-          Context, /*NumArgs=*/Record[ASTStmtReader::NumExprFields] & 0xffff,
-          /*HasFPFeatures=*/
-          ((Record[ASTStmtReader::NumExprFields] >> 16) & 0x1), Empty);
+          Context, /*NumArgs=*/Record[ASTStmtReader::NumExprFields],
+          /*HasFPFeatures=*/Record[ASTStmtReader::NumExprFields + 1], Empty);
       break;
 
     case EXPR_CXX_MEMBER_CALL:
       S = CXXMemberCallExpr::CreateEmpty(
-          Context, /*NumArgs=*/Record[ASTStmtReader::NumExprFields] & 0xffff,
-          /*HasFPFeatures=*/
-          ((Record[ASTStmtReader::NumExprFields] >> 16) & 0x1), Empty);
+          Context, /*NumArgs=*/Record[ASTStmtReader::NumExprFields],
+          /*HasFPFeatures=*/Record[ASTStmtReader::NumExprFields + 1], Empty);
       break;
 
     case EXPR_CXX_REWRITTEN_BINARY_OPERATOR:
@@ -3961,21 +3948,23 @@ Stmt *ASTReader::ReadStmtFromStream(ModuleFile &F) {
     case EXPR_CXX_UNRESOLVED_MEMBER:
       S = UnresolvedMemberExpr::CreateEmpty(
           Context,
-          /*NumResults=*/Record[ASTStmtReader::NumExprFields] & ((1 << 14) - 1),
-          /*HasTemplateKWAndArgsInfo=*/
-              (Record[ASTStmtReader::NumExprFields] >> 14) & (0x1),
-          /*NumTemplateArgs=*/Record[ASTStmtReader::NumExprFields] >> 14 &
-              ((1 << 14) - 1));
+          /*NumResults=*/Record[ASTStmtReader::NumExprFields],
+          /*HasTemplateKWAndArgsInfo=*/Record[ASTStmtReader::NumExprFields + 1],
+          /*NumTemplateArgs=*/
+          Record[ASTStmtReader::NumExprFields + 1]
+              ? Record[ASTStmtReader::NumExprFields + 2]
+              : 0);
       break;
 
     case EXPR_CXX_UNRESOLVED_LOOKUP:
       S = UnresolvedLookupExpr::CreateEmpty(
           Context,
-          /*NumResults=*/Record[ASTStmtReader::NumExprFields] & ((1 << 14) - 1),
-          /*HasTemplateKWAndArgsInfo=*/
-              (Record[ASTStmtReader::NumExprFields] >> 14) & (0x1),
-          /*NumTemplateArgs=*/Record[ASTStmtReader::NumExprFields] >> 14 &
-              ((1 << 14) - 1));
+          /*NumResults=*/Record[ASTStmtReader::NumExprFields],
+          /*HasTemplateKWAndArgsInfo=*/Record[ASTStmtReader::NumExprFields + 1],
+          /*NumTemplateArgs=*/
+          Record[ASTStmtReader::NumExprFields + 1]
+              ? Record[ASTStmtReader::NumExprFields + 2]
+              : 0);
       break;
 
     case EXPR_TYPE_TRAIT:
@@ -4037,9 +4026,8 @@ Stmt *ASTReader::ReadStmtFromStream(ModuleFile &F) {
 
     case EXPR_CUDA_KERNEL_CALL:
       S = CUDAKernelCallExpr::CreateEmpty(
-          Context, /*NumArgs=*/Record[ASTStmtReader::NumExprFields] & 0xffff,
-          /*HasFPFeatures=*/
-          ((Record[ASTStmtReader::NumExprFields] >> 16) & 0x1), Empty);
+          Context, /*NumArgs=*/Record[ASTStmtReader::NumExprFields],
+          /*HasFPFeatures=*/Record[ASTStmtReader::NumExprFields + 1], Empty);
       break;
 
     case EXPR_ASTYPE:
diff --git a/clang/lib/Serialization/ASTWriterDecl.cpp b/clang/lib/Serialization/ASTWriterDecl.cpp
index 43169b2befc6..a6fc41fdb4ce 100644
--- a/clang/lib/Serialization/ASTWriterDecl.cpp
+++ b/clang/lib/Serialization/ASTWriterDecl.cpp
@@ -320,8 +320,13 @@ void ASTDeclWriter::Visit(Decl *D) {
 }
 
 void ASTDeclWriter::VisitDecl(Decl *D) {
+  Record.AddDeclRef(cast_or_null<Decl>(D->getDeclContext()));
+  if (D->getDeclContext() != D->getLexicalDeclContext())
+    Record.AddDeclRef(cast_or_null<Decl>(D->getLexicalDeclContext()));
+  else
+    Record.push_back(0);
+
   BitsPacker DeclBits;
-  DeclBits.addBit(D->getDeclContext() != D->getLexicalDeclContext());
   DeclBits.addBit(D->isInvalidDecl());
   DeclBits.addBit(D->hasAttrs());
   DeclBits.addBit(D->isImplicit());
@@ -332,10 +337,6 @@ void ASTDeclWriter::VisitDecl(Decl *D) {
   DeclBits.addBits((uint64_t)D->getModuleOwnershipKind(), /*BitWidth=*/3);
   Record.push_back(DeclBits);
 
-  Record.AddDeclRef(cast_or_null<Decl>(D->getDeclContext()));
-  if (D->getDeclContext() != D->getLexicalDeclContext())
-    Record.AddDeclRef(cast_or_null<Decl>(D->getLexicalDeclContext()));
-
   if (D->hasAttrs())
     Record.AddAttributes(D->getAttrs());
 
@@ -449,18 +450,19 @@ void ASTDeclWriter::VisitTagDecl(TagDecl *D) {
   TagDeclBits.addBit(D->isEmbeddedInDeclarator());
   TagDeclBits.addBit(D->isFreeStanding());
   TagDeclBits.addBit(D->isCompleteDefinitionRequired());
-  TagDeclBits.addBits(
-      D->hasExtInfo() ? 1 : (D->getTypedefNameForAnonDecl() ? 2 : 0),
-      /*BitWidth=*/2);
   Record.push_back(TagDeclBits);
 
   Record.AddSourceRange(D->getBraceRange());
 
   if (D->hasExtInfo()) {
+    Record.push_back(1);
     Record.AddQualifierInfo(*D->getExtInfo());
   } else if (auto *TD = D->getTypedefNameForAnonDecl()) {
+    Record.push_back(2);
     Record.AddDeclRef(TD);
     Record.AddIdentifierRef(TD->getDeclName().getAsIdentifierInfo());
+  } else {
+    Record.push_back(0);
   }
 }
 
@@ -700,8 +702,7 @@ void ASTDeclWriter::VisitFunctionDecl(FunctionDecl *D) {
   Record.push_back(FunctionDeclBits);
 
   Record.AddSourceLocation(D->getEndLoc());
-  if (D->isExplicitlyDefaulted())
-    Record.AddSourceLocation(D->getDefaultLoc());
+  Record.AddSourceLocation(D->getDefaultLoc());
 
   Record.push_back(D->getODRHash());
 
@@ -1175,18 +1176,15 @@ void ASTDeclWriter::VisitParmVarDecl(ParmVarDecl *D) {
   ParmVarDeclBits.addBit(D->isObjCMethodParameter());
   ParmVarDeclBits.addBits(D->getFunctionScopeDepth(), /*BitsWidth=*/7);
   ParmVarDeclBits.addBits(D->getFunctionScopeIndex(), /*BitsWidth=*/8);
-  // FIXME: stable encoding
-  ParmVarDeclBits.addBits(D->getObjCDeclQualifier(), /*BitsWidth=*/7);
   ParmVarDeclBits.addBit(D->isKNRPromoted());
   ParmVarDeclBits.addBit(D->hasInheritedDefaultArg());
   ParmVarDeclBits.addBit(D->hasUninstantiatedDefaultArg());
-  ParmVarDeclBits.addBit(D->getExplicitObjectParamThisLoc().isValid());
   Record.push_back(ParmVarDeclBits);
 
+  Record.push_back(D->getObjCDeclQualifier()); // FIXME: stable encoding
   if (D->hasUninstantiatedDefaultArg())
     Record.AddStmt(D->getUninstantiatedDefaultArg());
-  if (D->getExplicitObjectParamThisLoc().isValid())
-    Record.AddSourceLocation(D->getExplicitObjectParamThisLoc());
+  Record.AddSourceLocation(D->getExplicitObjectParamThisLoc());
   Code = serialization::DECL_PARM_VAR;
 
   // If the assumptions about the DECL_PARM_VAR abbrev are true, use it.  Here
@@ -2040,12 +2038,13 @@ void ASTWriter::WriteDeclAbbrevs() {
   Abv = std::make_shared<BitCodeAbbrev>();
   Abv->Add(BitCodeAbbrevOp(serialization::DECL_FIELD));
   // Decl
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
-                           12)); // Packed DeclBits: HasStandaloneLexicalDC,
-                                 // isInvalidDecl, HasAttrs, isImplicit, isUsed,
-                                 // isReferenced, TopLevelDeclInObjCContainer,
-                                 // AccessSpecifier, ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // DeclContext
+  Abv->Add(BitCodeAbbrevOp(0));                       // LexicalDeclContext
+  Abv->Add(BitCodeAbbrevOp(
+      BitCodeAbbrevOp::Fixed,
+      11)); // Packed DeclBits: isInvalidDecl, HasAttrs, isImplicit, isUsed,
+            // isReferenced, TopLevelDeclInObjCContainer, AccessSpecifier,
+            // ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // SubmoduleID
   // NamedDecl
   Abv->Add(BitCodeAbbrevOp(0));                       // NameKind = Identifier
@@ -2069,12 +2068,13 @@ void ASTWriter::WriteDeclAbbrevs() {
   Abv = std::make_shared<BitCodeAbbrev>();
   Abv->Add(BitCodeAbbrevOp(serialization::DECL_OBJC_IVAR));
   // Decl
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
-                           12)); // Packed DeclBits: HasStandaloneLexicalDC,
-                                 // isInvalidDecl, HasAttrs, isImplicit, isUsed,
-                                 // isReferenced, TopLevelDeclInObjCContainer,
-                                 // AccessSpecifier, ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // DeclContext
+  Abv->Add(BitCodeAbbrevOp(0));                       // LexicalDeclContext
+  Abv->Add(BitCodeAbbrevOp(
+      BitCodeAbbrevOp::Fixed,
+      11)); // Packed DeclBits: isInvalidDecl, HasAttrs, isImplicit, isUsed,
+            // isReferenced, TopLevelDeclInObjCContainer, AccessSpecifier,
+            // ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // SubmoduleID
   // NamedDecl
   Abv->Add(BitCodeAbbrevOp(0));                       // NameKind = Identifier
@@ -2103,12 +2103,13 @@ void ASTWriter::WriteDeclAbbrevs() {
   // Redeclarable
   Abv->Add(BitCodeAbbrevOp(0));                       // No redeclaration
   // Decl
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
-                           12)); // Packed DeclBits: HasStandaloneLexicalDC,
-                                 // isInvalidDecl, HasAttrs, isImplicit, isUsed,
-                                 // isReferenced, TopLevelDeclInObjCContainer,
-                                 // AccessSpecifier, ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // DeclContext
+  Abv->Add(BitCodeAbbrevOp(0));                       // LexicalDeclContext
+  Abv->Add(BitCodeAbbrevOp(
+      BitCodeAbbrevOp::Fixed,
+      11)); // Packed DeclBits: isInvalidDecl, HasAttrs, isImplicit, isUsed,
+            // isReferenced, TopLevelDeclInObjCContainer, AccessSpecifier,
+            // ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // SubmoduleID
   // NamedDecl
   Abv->Add(BitCodeAbbrevOp(0));                       // NameKind = Identifier
@@ -2121,11 +2122,11 @@ void ASTWriter::WriteDeclAbbrevs() {
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // IdentifierNamespace
   Abv->Add(BitCodeAbbrevOp(
       BitCodeAbbrevOp::Fixed,
-      9)); // Packed Tag Decl Bits: getTagKind, isCompleteDefinition,
-           // EmbeddedInDeclarator, IsFreeStanding,
-           // isCompleteDefinitionRequired, ExtInfoKind
+      7)); // Packed Tag Decl Bits: getTagKind, isCompleteDefinition,
+           // EmbeddedInDeclarator, IsFreeStanding, isCompleteDefinitionRequired
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // SourceLocation
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // SourceLocation
+  Abv->Add(BitCodeAbbrevOp(0));                         // ExtInfoKind
   // EnumDecl
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // AddTypeRef
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // IntegerType
@@ -2144,12 +2145,13 @@ void ASTWriter::WriteDeclAbbrevs() {
   // Redeclarable
   Abv->Add(BitCodeAbbrevOp(0));                       // No redeclaration
   // Decl
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
-                           12)); // Packed DeclBits: HasStandaloneLexicalDC,
-                                 // isInvalidDecl, HasAttrs, isImplicit, isUsed,
-                                 // isReferenced, TopLevelDeclInObjCContainer,
-                                 // AccessSpecifier, ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // DeclContext
+  Abv->Add(BitCodeAbbrevOp(0));                       // LexicalDeclContext
+  Abv->Add(BitCodeAbbrevOp(
+      BitCodeAbbrevOp::Fixed,
+      11)); // Packed DeclBits: isInvalidDecl, HasAttrs, isImplicit, isUsed,
+            // isReferenced, TopLevelDeclInObjCContainer, AccessSpecifier,
+            // ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // SubmoduleID
   // NamedDecl
   Abv->Add(BitCodeAbbrevOp(0));                       // NameKind = Identifier
@@ -2162,11 +2164,11 @@ void ASTWriter::WriteDeclAbbrevs() {
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // IdentifierNamespace
   Abv->Add(BitCodeAbbrevOp(
       BitCodeAbbrevOp::Fixed,
-      9)); // Packed Tag Decl Bits: getTagKind, isCompleteDefinition,
-           // EmbeddedInDeclarator, IsFreeStanding,
-           // isCompleteDefinitionRequired, ExtInfoKind
+      7)); // Packed Tag Decl Bits: getTagKind, isCompleteDefinition,
+           // EmbeddedInDeclarator, IsFreeStanding, isCompleteDefinitionRequired
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // SourceLocation
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // SourceLocation
+  Abv->Add(BitCodeAbbrevOp(0));                         // ExtInfoKind
   // RecordDecl
   Abv->Add(BitCodeAbbrevOp(
       BitCodeAbbrevOp::Fixed,
@@ -2192,12 +2194,13 @@ void ASTWriter::WriteDeclAbbrevs() {
   // Redeclarable
   Abv->Add(BitCodeAbbrevOp(0));                       // No redeclaration
   // Decl
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
-                           12)); // Packed DeclBits: HasStandaloneLexicalDC,
-                                 // isInvalidDecl, HasAttrs, isImplicit, isUsed,
-                                 // isReferenced, TopLevelDeclInObjCContainer,
-                                 // AccessSpecifier, ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // DeclContext
+  Abv->Add(BitCodeAbbrevOp(0));                       // LexicalDeclContext
+  Abv->Add(BitCodeAbbrevOp(
+      BitCodeAbbrevOp::Fixed,
+      11)); // Packed DeclBits: isInvalidDecl, HasAttrs, isImplicit, isUsed,
+            // isReferenced, TopLevelDeclInObjCContainer, AccessSpecifier,
+            // ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // SubmoduleID
   // NamedDecl
   Abv->Add(BitCodeAbbrevOp(0));                       // NameKind = Identifier
@@ -2218,9 +2221,10 @@ void ASTWriter::WriteDeclAbbrevs() {
   // ParmVarDecl
   Abv->Add(BitCodeAbbrevOp(
       BitCodeAbbrevOp::Fixed,
-      27)); // Packed Parm Var Decl bits: IsObjCMethodParameter, ScopeDepth,
-            // ScopeIndex, ObjCDeclQualifier, KNRPromoted,
-            // HasInheritedDefaultArg, HasUninstantiatedDefaultArg
+      19)); // Packed Parm Var Decl bits: IsObjCMethodParameter, ScopeDepth,
+            // ScopeIndex, KNRPromoted, HasInheritedDefaultArg
+  Abv->Add(BitCodeAbbrevOp(0));                       // ObjCDeclQualifier
+  Abv->Add(BitCodeAbbrevOp(0));                   // HasUninstantiatedDefaultArg
   // Type Source Info
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Array));
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // TypeLoc
@@ -2232,12 +2236,13 @@ void ASTWriter::WriteDeclAbbrevs() {
   // Redeclarable
   Abv->Add(BitCodeAbbrevOp(0));                       // No redeclaration
   // Decl
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
-                           12)); // Packed DeclBits: HasStandaloneLexicalDC,
-                                 // isInvalidDecl, HasAttrs, isImplicit, isUsed,
-                                 // isReferenced, TopLevelDeclInObjCContainer,
-                                 // AccessSpecifier, ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // DeclContext
+  Abv->Add(BitCodeAbbrevOp(0));                       // LexicalDeclContext
+  Abv->Add(BitCodeAbbrevOp(
+      BitCodeAbbrevOp::Fixed,
+      11)); // Packed DeclBits: isInvalidDecl, HasAttrs, isImplicit, isUsed,
+            // isReferenced, TopLevelDeclInObjCContainer, AccessSpecifier,
+            // ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // SubmoduleID
   // NamedDecl
   Abv->Add(BitCodeAbbrevOp(0));                       // NameKind = Identifier
@@ -2257,12 +2262,13 @@ void ASTWriter::WriteDeclAbbrevs() {
   // Redeclarable
   Abv->Add(BitCodeAbbrevOp(0));                       // No redeclaration
   // Decl
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
-                           12)); // Packed DeclBits: HasStandaloneLexicalDC,
-                                 // isInvalidDecl, HasAttrs, isImplicit, isUsed,
-                                 // isReferenced, TopLevelDeclInObjCContainer,
-                                 // AccessSpecifier, ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // DeclContext
+  Abv->Add(BitCodeAbbrevOp(0));                       // LexicalDeclContext
+  Abv->Add(BitCodeAbbrevOp(
+      BitCodeAbbrevOp::Fixed,
+      11)); // Packed DeclBits: isInvalidDecl, HasAttrs, isImplicit, isUsed,
+            // isReferenced, TopLevelDeclInObjCContainer, AccessSpecifier,
+            // ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // SubmoduleID
   // NamedDecl
   Abv->Add(BitCodeAbbrevOp(0));                       // NameKind = Identifier
@@ -2297,12 +2303,13 @@ void ASTWriter::WriteDeclAbbrevs() {
   // FIXME: Implement abbreviation for other template kinds.
   Abv->Add(BitCodeAbbrevOp(FunctionDecl::TK_NonTemplate)); // TemplateKind
   // Decl
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
-                           12)); // Packed DeclBits: HasStandaloneLexicalDC,
-                                 // isInvalidDecl, HasAttrs, isImplicit, isUsed,
-                                 // isReferenced, TopLevelDeclInObjCContainer,
-                                 // AccessSpecifier, ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // DeclContext
+  Abv->Add(BitCodeAbbrevOp(0));                         // LexicalDeclContext
+  Abv->Add(BitCodeAbbrevOp(
+      BitCodeAbbrevOp::Fixed,
+      11)); // Packed DeclBits: isInvalidDecl, HasAttrs, isImplicit, isUsed,
+            // isReferenced, TopLevelDeclInObjCContainer, AccessSpecifier,
+            // ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // SubmoduleID
   // NamedDecl
   Abv->Add(BitCodeAbbrevOp(DeclarationName::Identifier)); // NameKind
@@ -2345,8 +2352,9 @@ void ASTWriter::WriteDeclAbbrevs() {
   //Stmt
   // Expr
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // Type
-  // DependenceKind, ValueKind, ObjectKind
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 10));
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, ExprDependenceBits));
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 3)); //GetValueKind
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 3)); //GetObjectKind
   //DeclRefExpr
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 1)); //HasQualifier
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 1)); //GetDeclFound
@@ -2365,8 +2373,9 @@ void ASTWriter::WriteDeclAbbrevs() {
   //Stmt
   // Expr
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // Type
-  // DependenceKind, ValueKind, ObjectKind
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 10));
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, ExprDependenceBits));
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 3)); //GetValueKind
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 3)); //GetObjectKind
   //Integer Literal
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // Location
   Abv->Add(BitCodeAbbrevOp(32));                      // Bit Width
@@ -2379,8 +2388,9 @@ void ASTWriter::WriteDeclAbbrevs() {
   //Stmt
   // Expr
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // Type
-  // DependenceKind, ValueKind, ObjectKind
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 10));
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, ExprDependenceBits));
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 3)); //GetValueKind
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 3)); //GetObjectKind
   //Character Literal
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // getValue
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // Location
@@ -2393,8 +2403,9 @@ void ASTWriter::WriteDeclAbbrevs() {
   // Stmt
   // Expr
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // Type
-  // DependenceKind, ValueKind, ObjectKind
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 10));
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, ExprDependenceBits));
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 3)); //GetValueKind
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 3)); //GetObjectKind
   // CastExpr
   Abv->Add(BitCodeAbbrevOp(0)); // PathSize
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 1)); // HasFPFeatures
diff --git a/clang/lib/Serialization/ASTWriterStmt.cpp b/clang/lib/Serialization/ASTWriterStmt.cpp
index 8524484ea8a0..59be6828fafa 100644
--- a/clang/lib/Serialization/ASTWriterStmt.cpp
+++ b/clang/lib/Serialization/ASTWriterStmt.cpp
@@ -549,14 +549,9 @@ void ASTStmtWriter::VisitCapturedStmt(CapturedStmt *S) {
 void ASTStmtWriter::VisitExpr(Expr *E) {
   VisitStmt(E);
   Record.AddTypeRef(E->getType());
-
-  BitsPacker ExprBits;
-
-  ExprBits.addBits(E->getDependence(), /*BitsWidth=*/5);
-  ExprBits.addBits(E->getValueKind(), /*BitsWidth=*/2);
-  ExprBits.addBits(E->getObjectKind(), /*BitsWidth=*/3);
-
-  Record.push_back(ExprBits);
+  Record.push_back(E->getDependence());
+  Record.push_back(E->getValueKind());
+  Record.push_back(E->getObjectKind());
 }
 
 void ASTStmtWriter::VisitConstantExpr(ConstantExpr *E) {
@@ -871,20 +866,14 @@ void ASTStmtWriter::VisitOMPIteratorExpr(OMPIteratorExpr *E) {
 
 void ASTStmtWriter::VisitCallExpr(CallExpr *E) {
   VisitExpr(E);
-
-  BitsPacker CallExprBits;
-  // 16 bits should be sufficient to store the number args;
-  CallExprBits.addBits(E->getNumArgs(), /*BitsWidth=*/16);
-  CallExprBits.addBit(E->hasStoredFPFeatures());
-  CallExprBits.addBit(static_cast<bool>(E->getADLCallKind()));
-  Record.push_back(CallExprBits);
-
+  Record.push_back(E->getNumArgs());
+  Record.push_back(E->hasStoredFPFeatures());
   Record.AddSourceLocation(E->getRParenLoc());
   Record.AddStmt(E->getCallee());
   for (CallExpr::arg_iterator Arg = E->arg_begin(), ArgEnd = E->arg_end();
        Arg != ArgEnd; ++Arg)
     Record.AddStmt(*Arg);
-
+  Record.push_back(static_cast<unsigned>(E->getADLCallKind()));
   if (E->hasStoredFPFeatures())
     Record.push_back(E->getFPFeatures().getAsOpaqueInt());
   Code = serialization::EXPR_CALL;
@@ -1949,19 +1938,14 @@ ASTStmtWriter::VisitCXXUnresolvedConstructExpr(CXXUnresolvedConstructExpr *E) {
 void ASTStmtWriter::VisitOverloadExpr(OverloadExpr *E) {
   VisitExpr(E);
 
-  BitsPacker OverloadExprBits;
-  // 14 Bits should enough to store the number of decls.
-  OverloadExprBits.addBits(E->getNumDecls(), /*BitWidth=*/14);
-  OverloadExprBits.addBit(E->hasTemplateKWAndArgsInfo());
+  Record.push_back(E->getNumDecls());
+  Record.push_back(E->hasTemplateKWAndArgsInfo());
   if (E->hasTemplateKWAndArgsInfo()) {
     const ASTTemplateKWAndArgsInfo &ArgInfo =
         *E->getTrailingASTTemplateKWAndArgsInfo();
-    // 14 Bits should enough to store the number of template args.
-    OverloadExprBits.addBits(ArgInfo.NumTemplateArgs, /*BitWidth=*/14);
-    Record.push_back(OverloadExprBits);
+    Record.push_back(ArgInfo.NumTemplateArgs);
     AddTemplateKWAndArgsInfo(ArgInfo, E->getTrailingTemplateArgumentLoc());
-  } else
-    Record.push_back(OverloadExprBits);
+  }
 
   for (OverloadExpr::decls_iterator OvI = E->decls_begin(),
                                     OvE = E->decls_end();
diff --git a/clang/test/Modules/decl-params-determinisim.m b/clang/test/Modules/decl-params-determinisim.m
index 9cf37ac4334c..351403d9af94 100644
--- a/clang/test/Modules/decl-params-determinisim.m
+++ b/clang/test/Modules/decl-params-determinisim.m
@@ -28,23 +28,23 @@
 
 // CHECK: <TYPE_FUNCTION_PROTO
 // CHECK-NEXT: <DECL_PARM_VAR
-// CHECK-SAME: op5=2
+// CHECK-SAME: op6=2
 // CHECK-NEXT: <DECL_PARM_VAR
-// CHECK-SAME: op5=3
+// CHECK-SAME: op6=3
 // CHECK-NEXT: <DECL_PARM_VAR
-// CHECK-SAME: op5=4
+// CHECK-SAME: op6=4
 // CHECK-NEXT: <DECL_PARM_VAR
-// CHECK-SAME: op5=5
+// CHECK-SAME: op6=5
 
 /// Decl records start at 43
 // CHECK: <DECL_RECORD
-// CHECK-SAME: op5=43
+// CHECK-SAME: op6=43
 // CHECK-NEXT: <DECL_RECORD
-// CHECK-SAME: op5=44
+// CHECK-SAME: op6=44
 // CHECK-NEXT: <DECL_RECORD
-// CHECK-SAME: op5=45
+// CHECK-SAME: op6=45
 // CHECK-NEXT: <DECL_RECORD
-// CHECK-SAME: op5=46
+// CHECK-SAME: op6=46
 
 //--- headers/a.h
 void f(struct A0 *a0,
-- 
GitLab


From 9a46518630869e7fcb495e72378abdbedf68d40d Mon Sep 17 00:00:00 2001
From: Chuanqi Xu <yedeng.yd@linux.alibaba.com>
Date: Mon, 11 Dec 2023 14:11:09 +0800
Subject: [PATCH 080/349] Revert "[clang] Remove unused variable
 'ExprDependenceBits' in ASTWriterDecl.cpp (NFC)"

This reverts commit 10951050b5f371eb3e7cacce1691c4eb2fe2eab5.
This should be part of 8c334627818437180176b16b1932 to revert
9406ea3fe32e59a7d2 completely.
---
 clang/lib/Serialization/ASTWriterDecl.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/clang/lib/Serialization/ASTWriterDecl.cpp b/clang/lib/Serialization/ASTWriterDecl.cpp
index a6fc41fdb4ce..bf082e5b8eac 100644
--- a/clang/lib/Serialization/ASTWriterDecl.cpp
+++ b/clang/lib/Serialization/ASTWriterDecl.cpp
@@ -2346,6 +2346,7 @@ void ASTWriter::WriteDeclAbbrevs() {
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));
   DeclCXXMethodAbbrev = Stream.EmitAbbrev(std::move(Abv));
 
+  unsigned ExprDependenceBits = llvm::BitWidth<ExprDependence>;
   // Abbreviation for EXPR_DECL_REF
   Abv = std::make_shared<BitCodeAbbrev>();
   Abv->Add(BitCodeAbbrevOp(serialization::EXPR_DECL_REF));
-- 
GitLab


From ef112833e11e94ea049f98bec4a29b4fe96a25dd Mon Sep 17 00:00:00 2001
From: Thomas Raoux <thomas.raoux@openai.com>
Date: Sun, 10 Dec 2023 22:32:11 -0800
Subject: [PATCH 081/349] [MLIR][SCF] Add support for pipelining dynamic loops
 (#74350)

Support loops without static boundaries. Since the number of iteration
is not known we need to predicate prologue and epilogue in case the
number of iterations is smaller than the number of stages.

This patch includes work from @chengjunlu
---
 .../mlir/Dialect/SCF/Transforms/Transforms.h  |   7 +
 .../Dialect/SCF/Transforms/LoopPipelining.cpp | 137 ++++++++++++++----
 .../NVGPU/transform-pipeline-shared.mlir      |  26 ++--
 mlir/test/Dialect/SCF/loop-pipelining.mlir    |  47 ++++++
 mlir/test/lib/Dialect/SCF/TestSCFUtils.cpp    |   1 +
 5 files changed, 173 insertions(+), 45 deletions(-)

diff --git a/mlir/include/mlir/Dialect/SCF/Transforms/Transforms.h b/mlir/include/mlir/Dialect/SCF/Transforms/Transforms.h
index 347beb9e4c64..cad517359945 100644
--- a/mlir/include/mlir/Dialect/SCF/Transforms/Transforms.h
+++ b/mlir/include/mlir/Dialect/SCF/Transforms/Transforms.h
@@ -128,6 +128,13 @@ struct PipeliningOption {
   /// lambda to generate the predicated version of operations.
   bool peelEpilogue = true;
 
+  /// Control whether the transformation checks that the number of iterations is
+  /// greater or equal to the number of stages and skip the transformation if
+  /// this is not the case. If the loop is dynamic and this is set to true and
+  /// the loop bounds are not static the pipeliner will have to predicate
+  /// operations in the the prologue/epilogue.
+  bool supportDynamicLoops = false;
+
   // Callback to predicate operations when the prologue or epilogue are not
   // peeled. This takes the original operation, an i1 predicate value and the
   // pattern rewriter. It is expected to replace the given operation with
diff --git a/mlir/lib/Dialect/SCF/Transforms/LoopPipelining.cpp b/mlir/lib/Dialect/SCF/Transforms/LoopPipelining.cpp
index 20fa8089201a..6c36600975a5 100644
--- a/mlir/lib/Dialect/SCF/Transforms/LoopPipelining.cpp
+++ b/mlir/lib/Dialect/SCF/Transforms/LoopPipelining.cpp
@@ -44,9 +44,10 @@ protected:
   unsigned maxStage = 0;
   DenseMap<Operation *, unsigned> stages;
   std::vector<Operation *> opOrder;
-  int64_t ub;
-  int64_t lb;
-  int64_t step;
+  Value ub;
+  Value lb;
+  Value step;
+  bool dynamicLoop;
   PipeliningOption::AnnotationlFnType annotateFn = nullptr;
   bool peelEpilogue;
   PipeliningOption::PredicateOpFn predicateFn = nullptr;
@@ -96,25 +97,41 @@ bool LoopPipelinerInternal::initializeLoopInfo(
     ForOp op, const PipeliningOption &options) {
   LDBG("Start initializeLoopInfo");
   forOp = op;
-  auto upperBoundCst =
-      forOp.getUpperBound().getDefiningOp<arith::ConstantIndexOp>();
-  auto lowerBoundCst =
-      forOp.getLowerBound().getDefiningOp<arith::ConstantIndexOp>();
-  auto stepCst = forOp.getStep().getDefiningOp<arith::ConstantIndexOp>();
+  ub = forOp.getUpperBound();
+  lb = forOp.getLowerBound();
+  step = forOp.getStep();
+
+  dynamicLoop = true;
+  auto upperBoundCst = getConstantIntValue(ub);
+  auto lowerBoundCst = getConstantIntValue(lb);
+  auto stepCst = getConstantIntValue(step);
   if (!upperBoundCst || !lowerBoundCst || !stepCst) {
-    LDBG("--no constant bounds or step -> BAIL");
-    return false;
+    if (!options.supportDynamicLoops) {
+      LDBG("--dynamic loop not supported -> BAIL");
+      return false;
+    }
+  } else {
+    int64_t ubImm = upperBoundCst.value();
+    int64_t lbImm = lowerBoundCst.value();
+    int64_t stepImm = stepCst.value();
+    int64_t numIteration = ceilDiv(ubImm - lbImm, stepImm);
+    if (numIteration > maxStage) {
+      dynamicLoop = false;
+    } else if (!options.supportDynamicLoops) {
+      LDBG("--fewer loop iterations than pipeline stages -> BAIL");
+      return false;
+    }
   }
-  ub = upperBoundCst.value();
-  lb = lowerBoundCst.value();
-  step = stepCst.value();
   peelEpilogue = options.peelEpilogue;
   predicateFn = options.predicateFn;
-  if (!peelEpilogue && predicateFn == nullptr) {
+  if ((!peelEpilogue || dynamicLoop) && predicateFn == nullptr) {
     LDBG("--no epilogue or predicate set -> BAIL");
     return false;
   }
-  int64_t numIteration = ceilDiv(ub - lb, step);
+  if (dynamicLoop && peelEpilogue) {
+    LDBG("--dynamic loop doesn't support epilogue yet -> BAIL");
+    return false;
+  }
   std::vector<std::pair<Operation *, unsigned>> schedule;
   options.getScheduleFn(forOp, schedule);
   if (schedule.empty()) {
@@ -128,10 +145,6 @@ bool LoopPipelinerInternal::initializeLoopInfo(
     stages[opSchedule.first] = opSchedule.second;
     opOrder.push_back(opSchedule.first);
   }
-  if (numIteration <= maxStage) {
-    LDBG("--fewer loop iterations than pipeline stages -> BAIL");
-    return false;
-  }
 
   // All operations need to have a stage.
   for (Operation &op : forOp.getBody()->without_terminator()) {
@@ -204,10 +217,31 @@ void LoopPipelinerInternal::emitPrologue(RewriterBase &rewriter) {
     setValueMapping(arg, operand.get(), 0);
   }
   auto yield = cast<scf::YieldOp>(forOp.getBody()->getTerminator());
+  Location loc = forOp.getLoc();
+  SmallVector<Value> predicates(maxStage);
   for (int64_t i = 0; i < maxStage; i++) {
+    if (dynamicLoop) {
+      Type t = ub.getType();
+      // pred = ub > lb + (i * step)
+      Value iv = rewriter.create<arith::AddIOp>(
+          loc, lb,
+          rewriter.create<arith::MulIOp>(
+              loc, step,
+              rewriter.create<arith::ConstantOp>(
+                  loc, rewriter.getIntegerAttr(t, i))));
+      predicates[i] = rewriter.create<arith::CmpIOp>(
+          loc, arith::CmpIPredicate::slt, iv, ub);
+    }
+
     // special handling for induction variable as the increment is implicit.
-    Value iv =
-        rewriter.create<arith::ConstantIndexOp>(forOp.getLoc(), lb + i * step);
+    // iv = lb + i * step
+    Type t = lb.getType();
+    Value iv = rewriter.create<arith::AddIOp>(
+        loc, lb,
+        rewriter.create<arith::MulIOp>(
+            loc, step,
+            rewriter.create<arith::ConstantOp>(loc,
+                                               rewriter.getIntegerAttr(t, i))));
     setValueMapping(forOp.getInductionVar(), iv, i);
     for (Operation *op : opOrder) {
       if (stages[op] > i)
@@ -220,6 +254,12 @@ void LoopPipelinerInternal::emitPrologue(RewriterBase &rewriter) {
               newOperand->set(replacement);
             }
           });
+      int predicateIdx = i - stages[op];
+      if (predicates[predicateIdx]) {
+        newOp = predicateFn(rewriter, newOp, predicates[predicateIdx]);
+        assert(newOp && "failed to predicate op.");
+      }
+      rewriter.setInsertionPointAfter(newOp);
       if (annotateFn)
         annotateFn(newOp, PipeliningOption::PipelinerPart::Prologue, i);
       for (unsigned destId : llvm::seq(unsigned(0), op->getNumResults())) {
@@ -326,9 +366,16 @@ scf::ForOp LoopPipelinerInternal::createKernelLoop(
   // `numStages - 1` iterations. Then we adjust the upper bound to remove those
   // iterations.
   Value newUb = forOp.getUpperBound();
-  if (peelEpilogue)
-    newUb = rewriter.create<arith::ConstantIndexOp>(forOp.getLoc(),
-                                                    ub - maxStage * step);
+  if (peelEpilogue) {
+    Type t = ub.getType();
+    Location loc = forOp.getLoc();
+    // newUb = ub - maxStage * step
+    Value maxStageValue = rewriter.create<arith::ConstantOp>(
+        loc, rewriter.getIntegerAttr(t, maxStage));
+    Value maxStageByStep =
+        rewriter.create<arith::MulIOp>(loc, step, maxStageValue);
+    newUb = rewriter.create<arith::SubIOp>(loc, ub, maxStageByStep);
+  }
   auto newForOp =
       rewriter.create<scf::ForOp>(forOp.getLoc(), forOp.getLowerBound(), newUb,
                                   forOp.getStep(), newLoopArg);
@@ -358,9 +405,17 @@ LogicalResult LoopPipelinerInternal::createKernel(
   SmallVector<Value> predicates(maxStage + 1, nullptr);
   if (!peelEpilogue) {
     // Create a predicate for each stage except the last stage.
+    Location loc = newForOp.getLoc();
+    Type t = ub.getType();
     for (unsigned i = 0; i < maxStage; i++) {
-      Value c = rewriter.create<arith::ConstantIndexOp>(
-          newForOp.getLoc(), ub - (maxStage - i) * step);
+      // c = ub - (maxStage - i) * step
+      Value c = rewriter.create<arith::SubIOp>(
+          loc, ub,
+          rewriter.create<arith::MulIOp>(
+              loc, step,
+              rewriter.create<arith::ConstantOp>(
+                  loc, rewriter.getIntegerAttr(t, int64_t(maxStage - i)))));
+
       Value pred = rewriter.create<arith::CmpIOp>(
           newForOp.getLoc(), arith::CmpIPredicate::slt,
           newForOp.getInductionVar(), c);
@@ -383,8 +438,14 @@ LogicalResult LoopPipelinerInternal::createKernel(
       // version incremented based on the stage where it is used.
       if (operand->get() == forOp.getInductionVar()) {
         rewriter.setInsertionPoint(newOp);
-        Value offset = rewriter.create<arith::ConstantIndexOp>(
-            forOp.getLoc(), (maxStage - stages[op]) * step);
+
+        // offset = (maxStage - stages[op]) * step
+        Type t = step.getType();
+        Value offset = rewriter.create<arith::MulIOp>(
+            forOp.getLoc(), step,
+            rewriter.create<arith::ConstantOp>(
+                forOp.getLoc(),
+                rewriter.getIntegerAttr(t, maxStage - stages[op])));
         Value iv = rewriter.create<arith::AddIOp>(
             forOp.getLoc(), newForOp.getInductionVar(), offset);
         nestedNewOp->setOperand(operand->getOperandNumber(), iv);
@@ -508,8 +569,24 @@ LoopPipelinerInternal::emitEpilogue(RewriterBase &rewriter) {
   // Emit different versions of the induction variable. They will be
   // removed by dead code if not used.
   for (int64_t i = 0; i < maxStage; i++) {
-    Value newlastIter = rewriter.create<arith::ConstantIndexOp>(
-        forOp.getLoc(), lb + step * ((((ub - 1) - lb) / step) - i));
+    Location loc = forOp.getLoc();
+    Type t = lb.getType();
+    Value minusOne =
+        rewriter.create<arith::ConstantOp>(loc, rewriter.getIntegerAttr(t, -1));
+    // number of iterations = ((ub - 1) - lb) / step
+    Value totalNumIteration = rewriter.create<arith::DivUIOp>(
+        loc,
+        rewriter.create<arith::SubIOp>(
+            loc, rewriter.create<arith::AddIOp>(loc, ub, minusOne), lb),
+        step);
+    // newLastIter = lb + step * ((((ub - 1) - lb) / step) - i)
+    Value minusI =
+        rewriter.create<arith::ConstantOp>(loc, rewriter.getIntegerAttr(t, -i));
+    Value newlastIter = rewriter.create<arith::AddIOp>(
+        loc, lb,
+        rewriter.create<arith::MulIOp>(
+            loc, step,
+            rewriter.create<arith::AddIOp>(loc, totalNumIteration, minusI)));
     setValueMapping(forOp.getInductionVar(), newlastIter, maxStage - i);
   }
   // Emit `maxStage - 1` epilogue part that includes operations from stages
diff --git a/mlir/test/Dialect/NVGPU/transform-pipeline-shared.mlir b/mlir/test/Dialect/NVGPU/transform-pipeline-shared.mlir
index 42b072374261..e959949babd9 100644
--- a/mlir/test/Dialect/NVGPU/transform-pipeline-shared.mlir
+++ b/mlir/test/Dialect/NVGPU/transform-pipeline-shared.mlir
@@ -1,4 +1,4 @@
-// RUN: mlir-opt %s --transform-interpreter --split-input-file --verify-diagnostics | FileCheck %s
+// RUN: mlir-opt %s --transform-interpreter -canonicalize --split-input-file --verify-diagnostics | FileCheck %s
 
 func.func @simple_depth_2_unpeeled(%global: memref<?xf32>, %result: memref<?xf32> ) {
   %c0 = arith.constant 0 : index
@@ -78,15 +78,19 @@ module attributes {transform.with_named_sequence} {
 
 // CHECK-LABEL: @async_depth_2_predicated
 // CHECK-SAME: %[[GLOBAL:.+]]: memref
-func.func @async_depth_2_predicated(%global: memref<?xf32>) {
+func.func @async_depth_2_predicated(%global: memref<?xf32>, %alloc_size: index) {
   %c0 = arith.constant 0 : index
   %c98 = arith.constant 98 : index
   %c100 = arith.constant 100 : index
-  %c200 = arith.constant 200 : index
-  // CHECK: %[[C4:.+]] = arith.constant 4
+  // CHECK-DAG: %[[C4:.+]] = arith.constant 4
+  // CHECK-DAG:   %[[C90:.+]] = arith.constant 90
+  // CHECK-DAG:   %[[C96:.+]] = arith.constant 96
+  // CHECK-DAG:   %[[C8:.+]] = arith.constant 8
+  // CHECK-DAG:   %[[C2:.+]] = arith.constant 2
+  // CHECK-DAG:   %[[C0:.+]] = arith.constant 0
   %c4 = arith.constant 4 : index
   // CHECK: %[[SHARED:.+]] = memref.alloc{{.*}} #gpu.address_space<workgroup>
-  %shared = memref.alloc(%c200) : memref<?xf32, #gpu.address_space<workgroup>>
+  %shared = memref.alloc(%alloc_size) : memref<?xf32, #gpu.address_space<workgroup>>
   %c0f = arith.constant 0.0 : f32
   // CHECK: %[[TOKEN0:.+]] = nvgpu.device_async_copy
   // CHECK: %[[TOKEN1:.+]] = nvgpu.device_async_copy
@@ -95,16 +99,11 @@ func.func @async_depth_2_predicated(%global: memref<?xf32>) {
   // CHECK-SAME: %[[ITER_ARG1:.+]] = %[[TOKEN1]]
   scf.for %i = %c0 to %c98 step %c4 {
     // Condition for the predication "select" below.
-    // CHECK:   %[[C90:.+]] = arith.constant 90
     // CHECK:   %[[CMP0:.+]] = arith.cmpi slt, %[[I]], %[[C90]]
     // CHECK:   nvgpu.device_async_wait %[[ITER_ARG0]] {numGroups = 1
-
     // Original "select" with updated induction variable.
-    // CHECK:   %[[C96:.+]] = arith.constant 96
-    // CHECK:   %[[C8:.+]] = arith.constant 8
     // CHECK:   %[[I_PLUS_8:.+]] = arith.addi %[[I]], %[[C8]]
     // CHECK:   %[[CMP1:.+]] = arith.cmpi slt, %[[I_PLUS_8]], %[[C96]]
-    // CHECK:   %[[C2:.+]] = arith.constant 2
     // CHECK:   %[[SELECTED0:.+]] = arith.select %[[CMP1]], %[[C4]], %[[C2]]
     %c96 = arith.constant 96 : index
     %cond = arith.cmpi slt, %i, %c96 : index
@@ -113,14 +112,11 @@ func.func @async_depth_2_predicated(%global: memref<?xf32>) {
 
     // Updated induction variables (two more) for the device_async_copy below.
     // These are generated repeatedly by the pipeliner.
-    // CHECK:   %[[C8_2:.+]] = arith.constant 8
-    // CHECK:   %[[I_PLUS_8_2:.+]] = arith.addi %[[I]], %[[C8_2]]
-    // CHECK:   %[[C8_3:.+]] = arith.constant 8
-    // CHECK:   %[[I_PLUS_8_3:.+]] = arith.addi %[[I]], %[[C8_3]]
+    // CHECK:   %[[I_PLUS_8_2:.+]] = arith.addi %[[I]], %[[C8]]
+    // CHECK:   %[[I_PLUS_8_3:.+]] = arith.addi %[[I]], %[[C8]]
 
     // The second "select" is generated by predication and selects 0 for
     // the two last iterations.
-    // CHECK:   %[[C0:.+]] = arith.constant 0
     // CHECK:   %[[SELECTED1:.+]] = arith.select %[[CMP0]], %[[SELECTED0]], %[[C0]]
     // CHECK:   %[[ASYNC_TOKEN:.+]] = nvgpu.device_async_copy %[[GLOBAL]][%[[I_PLUS_8_3]]], %[[SHARED]][%[[I_PLUS_8_2]]], 4, %[[SELECTED1]]
     %token = nvgpu.device_async_copy %global[%i], %shared[%i], 4, %read_size
diff --git a/mlir/test/Dialect/SCF/loop-pipelining.mlir b/mlir/test/Dialect/SCF/loop-pipelining.mlir
index 4cd686d2cdb8..8a57ddccfee6 100644
--- a/mlir/test/Dialect/SCF/loop-pipelining.mlir
+++ b/mlir/test/Dialect/SCF/loop-pipelining.mlir
@@ -723,3 +723,50 @@ func.func @stage_0_value_escape(%A: memref<?xf32>, %result: memref<?xf32>) {
   memref.store %r, %result[%c1] : memref<?xf32>
   return
 }
+
+// -----
+
+// NOEPILOGUE-LABEL: dynamic_loop(
+//  NOEPILOGUE-SAME:   %[[A:.*]]: memref<?xf32>, %[[R:.*]]: memref<?xf32>, %[[LB:.+]]: index, %[[UB:.+]]: index, %[[STEP:.+]]: index) {
+//  NOEPILOGUE-DAG: %[[C2:.+]] = arith.constant 2 : index
+//  NOEPILOGUE-DAG: %[[CSTF:.+]] = arith.constant 1.000000e+00 : f32
+// Prologue:
+//      NOEPILOGUE: %[[P_I0:.+]] = arith.cmpi slt, %[[LB]], %[[UB]] : index
+//      NOEPILOGUE: %[[L0:.+]] = scf.if %[[P_I0]] -> (f32) {
+// NOEPILOGUE-NEXT:   memref.load %[[A]][%[[LB]]] : memref<?xf32>
+//      NOEPILOGUE: %[[IV1:.+]] = arith.addi %[[LB]], %[[STEP]] : index
+//      NOEPILOGUE: %[[P_I1:.+]] = arith.cmpi slt, %[[IV1]], %[[UB]] : index
+//      NOEPILOGUE: %[[IV1_2:.+]] = arith.addi %[[LB]], %[[STEP]] : index
+//      NOEPILOGUE: %[[V0:.+]] = scf.if %[[P_I0]] -> (f32) {
+// NOEPILOGUE-NEXT:   arith.addf %[[L0]], %[[CSTF]] : f32
+//      NOEPILOGUE: %[[L1:.+]] = scf.if %[[P_I1]] -> (f32) {
+// NOEPILOGUE-NEXT:   memref.load %[[A]][%[[IV1_2]]] : memref<?xf32>
+//  NOEPILOGUE: scf.for %[[IV2:.+]] = %[[LB]] to %[[UB]] step %[[STEP]] iter_args(%[[V1:.+]] = %[[V0]], %[[L2:.+]] = %[[L1]]) -> (f32, f32) {
+//  NOEPILOGUE-DAG:   %[[S2:.+]] = arith.muli %[[STEP]], %[[C2]] : index
+//  NOEPILOGUE-DAG:   %[[IT2:.+]] = arith.subi %[[UB]], %[[S2]] : index
+//  NOEPILOGUE-DAG:   %[[P_I2:.+]] = arith.cmpi slt, %[[IV2]], %[[IT2]] : index
+//  NOEPILOGUE-DAG:   %[[IT3:.+]] = arith.subi %[[UB]], %[[STEP]] : index
+//  NOEPILOGUE-DAG:   %[[P_I3:.+]] = arith.cmpi slt, %[[IV2]], %[[IT3]] : index
+//      NOEPILOGUE:   memref.store %[[V1]], %[[R]][%[[IV2]]] : memref<?xf32>
+//      NOEPILOGUE:   %[[V2:.+]] = scf.if %[[P_I3]] -> (f32) {
+//      NOEPILOGUE:     arith.addf %[[L2]], %[[CSTF]] : f32
+//      NOEPILOGUE:   %[[IT4:.+]] = arith.muli %[[STEP]], %[[C2]] : index
+//      NOEPILOGUE:   %[[IV3:.+]] = arith.addi %[[IV2]], %[[IT4]] : index
+//      NOEPILOGUE:   %[[L3:.+]] = scf.if %[[P_I2]] -> (f32) {
+//      NOEPILOGUE:     memref.load %[[A]][%[[IV3]]] : memref<?xf32>
+//      NOEPILOGUE:   scf.yield %[[V2]], %[[L3]] : f32, f32
+
+// In case dynamic loop pipelining is off check that the transformation didn't
+// apply.
+// CHECK-LABEL: dynamic_loop(
+//   CHECK-NOT:   memref.load
+//       CHECK:   scf.for
+func.func @dynamic_loop(%A: memref<?xf32>, %result: memref<?xf32>, %lb: index, %ub: index, %step: index) {
+  %cf = arith.constant 1.0 : f32
+  scf.for %i0 = %lb to %ub step %step {
+    %A_elem = memref.load %A[%i0] { __test_pipelining_stage__ = 0, __test_pipelining_op_order__ = 2 } : memref<?xf32>
+    %A1_elem = arith.addf %A_elem, %cf { __test_pipelining_stage__ = 1, __test_pipelining_op_order__ = 1 } : f32
+    memref.store %A1_elem, %result[%i0] { __test_pipelining_stage__ = 2, __test_pipelining_op_order__ = 0 } : memref<?xf32>
+  } { __test_pipelining_loop__ }
+  return
+}
diff --git a/mlir/test/lib/Dialect/SCF/TestSCFUtils.cpp b/mlir/test/lib/Dialect/SCF/TestSCFUtils.cpp
index 565d07669792..a8a808424b69 100644
--- a/mlir/test/lib/Dialect/SCF/TestSCFUtils.cpp
+++ b/mlir/test/lib/Dialect/SCF/TestSCFUtils.cpp
@@ -217,6 +217,7 @@ struct TestSCFPipeliningPass
     if (annotatePipeline)
       options.annotateFn = annotate;
     if (noEpiloguePeeling) {
+      options.supportDynamicLoops = true;
       options.peelEpilogue = false;
       options.predicateFn = predicateOp;
     }
-- 
GitLab


From 18959c46e3ced1f7ad12a82e9f30bafe9d1f1733 Mon Sep 17 00:00:00 2001
From: Serge Pavlov <sepavloff@gmail.com>
Date: Mon, 11 Dec 2023 00:07:06 +0700
Subject: [PATCH 082/349] [NFC] Modify test to use autogenerated assertions

---
 llvm/test/CodeGen/AArch64/fpenv.ll | 89 ++++++++++++++----------------
 1 file changed, 42 insertions(+), 47 deletions(-)

diff --git a/llvm/test/CodeGen/AArch64/fpenv.ll b/llvm/test/CodeGen/AArch64/fpenv.ll
index 14bf7888918e..3a307f773103 100644
--- a/llvm/test/CodeGen/AArch64/fpenv.ll
+++ b/llvm/test/CodeGen/AArch64/fpenv.ll
@@ -1,70 +1,65 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
 ; RUN: llc -mtriple=aarch64-none-linux-gnu %s -o - | FileCheck %s
 
-define void @func_02(i32 %rm) {
+define void @func_set_rounding_dyn(i32 %rm) {
+; CHECK-LABEL: func_set_rounding_dyn:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sub w9, w0, #1
+; CHECK-NEXT:    mrs x8, FPCR
+; CHECK-NEXT:    and w9, w9, #0x3
+; CHECK-NEXT:    and x8, x8, #0xffffffffff3fffff
+; CHECK-NEXT:    lsl w9, w9, #22
+; CHECK-NEXT:    orr x8, x8, x9
+; CHECK-NEXT:    msr FPCR, x8
+; CHECK-NEXT:    ret
   call void @llvm.set.rounding(i32 %rm)
   ret void
 }
 
-; CHECK-LABEL: func_02:
-; CHECK:       sub   w9, w0, #1
-; CHECK:       mrs   x8, FPCR
-; CHECK:       and   w9, w9, #0x3
-; CHECK:       and   x8, x8, #0xffffffffff3fffff
-; CHECK:       lsl   w9, w9, #22
-; CHECK:       orr   x8, x8, x9
-; CHECK:       msr   FPCR, x8
-; CHECK:       ret
-
-
-define void @func_03() {
+define void @func_set_rounding_toward_zero() {
+; CHECK-LABEL: func_set_rounding_toward_zero:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mrs x8, FPCR
+; CHECK-NEXT:    orr x8, x8, #0xc00000
+; CHECK-NEXT:    msr FPCR, x8
+; CHECK-NEXT:    ret
   call void @llvm.set.rounding(i32 0)
   ret void
 }
 
-; CHECK-LABEL: func_03
-; CHECK:       mrs   x8, FPCR
-; CHECK:       orr   x8, x8, #0xc00000
-; CHECK:       msr   FPCR, x8
-; CHECK:       ret
-
-
-define void @func_04() {
+define void @func_set_rounding_tonearest_even() {
+; CHECK-LABEL: func_set_rounding_tonearest_even:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mrs x8, FPCR
+; CHECK-NEXT:    and x8, x8, #0xffffffffff3fffff
+; CHECK-NEXT:    msr FPCR, x8
+; CHECK-NEXT:    ret
   call void @llvm.set.rounding(i32 1)
   ret void
 }
 
-; CHECK-LABEL: func_04
-; CHECK:       mrs   x8, FPCR
-; CHECK:       and   x8, x8, #0xffffffffff3fffff
-; CHECK:       msr   FPCR, x8
-; CHECK:       ret
-
-
-define void @func_05() {
+define void @func_set_rounding_upward() {
+; CHECK-LABEL: func_set_rounding_upward:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mrs x8, FPCR
+; CHECK-NEXT:    and x8, x8, #0xffffffffff3fffff
+; CHECK-NEXT:    orr x8, x8, #0x400000
+; CHECK-NEXT:    msr FPCR, x8
+; CHECK-NEXT:    ret
   call void @llvm.set.rounding(i32 2)
   ret void
 }
 
-
-; CHECK-LABEL: func_05
-; CHECK:       mrs   x8, FPCR
-; CHECK:       and   x8, x8, #0xffffffffff3fffff
-; CHECK:       orr   x8, x8, #0x400000
-; CHECK:       msr   FPCR, x8
-; CHECK:       ret
-
-
-define void @func_06() {
+define void @func_set_rounding_downward() {
+; CHECK-LABEL: func_set_rounding_downward:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mrs x8, FPCR
+; CHECK-NEXT:    and x8, x8, #0xffffffffff3fffff
+; CHECK-NEXT:    orr x8, x8, #0x800000
+; CHECK-NEXT:    msr FPCR, x8
+; CHECK-NEXT:    ret
   call void @llvm.set.rounding(i32 3)
   ret void
 }
 
-; CHECK-LABEL: func_06
-; CHECK:       mrs   x8, FPCR
-; CHECK:       and   x8, x8, #0xffffffffff3fffff
-; CHECK:       orr   x8, x8, #0x800000
-; CHECK:       msr   FPCR, x8
-; CHECK:       ret
-
-
 declare void @llvm.set.rounding(i32)
-- 
GitLab


From bd3e8eb6e325081bf7cfbe93652aa825de3170e5 Mon Sep 17 00:00:00 2001
From: Tobias Hieta <tobias@hieta.se>
Date: Mon, 11 Dec 2023 09:35:26 +0100
Subject: [PATCH 083/349] code-format: Improve the code-format-helper to be
 able to run as a git hook (#73957)

As part of #73798 there was some discussion about using the format
helper to run from a git-hook. That was not possible for a number of
reasons, but with these changes it can now be installed as a hook and
then run on the local cache in git instead of a diff between revisions.

This also checks for two environment variables DARKER_FORMAT_PATH and
CLANG_FORMAT_PATH where you can specify the path to the program you want
to use.
---
 llvm/utils/git/code-format-helper.py | 219 ++++++++++++++++++++-------
 1 file changed, 166 insertions(+), 53 deletions(-)
 mode change 100644 => 100755 llvm/utils/git/code-format-helper.py

diff --git a/llvm/utils/git/code-format-helper.py b/llvm/utils/git/code-format-helper.py
old mode 100644
new mode 100755
index f89f060b3fe5..aa78bc4f0ba9
--- a/llvm/utils/git/code-format-helper.py
+++ b/llvm/utils/git/code-format-helper.py
@@ -1,21 +1,56 @@
 #!/usr/bin/env python3
 #
-# ====- code-format-helper, runs code formatters from the ci --*- python -*--==#
+# ====- code-format-helper, runs code formatters from the ci or in a hook --*- python -*--==#
 #
 # Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 # See https://llvm.org/LICENSE.txt for license information.
 # SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 #
-# ==-------------------------------------------------------------------------==#
+# ==--------------------------------------------------------------------------------------==#
 
 import argparse
 import os
 import subprocess
 import sys
-from functools import cached_property
+from typing import List, Optional
 
-import github
-from github import IssueComment, PullRequest
+"""
+This script is run by GitHub actions to ensure that the code in PR's conform to
+the coding style of LLVM. It can also be installed as a pre-commit git hook to
+check the coding style before submitting it. The canonical source of this script
+is in the LLVM source tree under llvm/utils/git.
+
+For C/C++ code it uses clang-format and for Python code it uses darker (which
+in turn invokes black).
+
+You can learn more about the LLVM coding style on llvm.org:
+https://llvm.org/docs/CodingStandards.html
+
+You can install this script as a git hook by symlinking it to the .git/hooks
+directory:
+
+ln -s $(pwd)/llvm/utils/git/code-format-helper.py .git/hooks/pre-commit
+
+You can control the exact path to clang-format or darker with the following
+environment variables: $CLANG_FORMAT_PATH and $DARKER_FORMAT_PATH.
+"""
+
+
+class FormatArgs:
+    start_rev: str = None
+    end_rev: str = None
+    repo: str = None
+    changed_files: List[str] = []
+    token: str = None
+    verbose: bool = True
+
+    def __init__(self, args: argparse.Namespace = None) -> None:
+        if not args is None:
+            self.start_rev = args.start_rev
+            self.end_rev = args.end_rev
+            self.repo = args.repo
+            self.token = args.token
+            self.changed_files = args.changed_files
 
 
 class FormatHelper:
@@ -31,9 +66,10 @@ class FormatHelper:
     def instructions(self) -> str:
         raise NotImplementedError()
 
-    def format_run(
-        self, changed_files: list[str], args: argparse.Namespace
-    ) -> str | None:
+    def has_tool(self) -> bool:
+        raise NotImplementedError()
+
+    def format_run(self, changed_files: List[str], args: FormatArgs) -> Optional[str]:
         raise NotImplementedError()
 
     def pr_comment_text_for_diff(self, diff: str) -> str:
@@ -63,17 +99,18 @@ View the diff from {self.name} here.
 </details>
 """
 
-    def find_comment(
-        self, pr: PullRequest.PullRequest
-    ) -> IssueComment.IssueComment | None:
+    # TODO: any type should be replaced with the correct github type, but it requires refactoring to
+    # not require the github module to be installed everywhere.
+    def find_comment(self, pr: any) -> any:
         for comment in pr.as_issue().get_comments():
             if self.comment_tag in comment.body:
                 return comment
         return None
 
-    def update_pr(
-        self, comment_text: str, args: argparse.Namespace, create_new: bool
-    ) -> None:
+    def update_pr(self, comment_text: str, args: FormatArgs, create_new: bool) -> None:
+        import github
+        from github import IssueComment, PullRequest
+
         repo = github.Github(args.token).get_repo(args.repo)
         pr = repo.get_issue(args.issue_number).as_pull_request()
 
@@ -85,17 +122,25 @@ View the diff from {self.name} here.
         elif create_new:
             pr.as_issue().create_comment(comment_text)
 
-    def run(self, changed_files: list[str], args: argparse.Namespace) -> bool:
+    def run(self, changed_files: List[str], args: FormatArgs) -> bool:
         diff = self.format_run(changed_files, args)
+        should_update_gh = args.token is not None and args.repo is not None
+
         if diff is None:
-            comment_text = f"""
-:white_check_mark: With the latest revision this PR passed the {self.friendly_name}.
-"""
-            self.update_pr(comment_text, args, create_new=False)
+            if should_update_gh:
+                comment_text = f"""
+    :white_check_mark: With the latest revision this PR passed the {self.friendly_name}.
+    """
+                self.update_pr(comment_text, args, create_new=False)
             return True
         elif len(diff) > 0:
-            comment_text = self.pr_comment_text_for_diff(diff)
-            self.update_pr(comment_text, args, create_new=True)
+            if should_update_gh:
+                comment_text = self.pr_comment_text_for_diff(diff)
+                self.update_pr(comment_text, args, create_new=True)
+            else:
+                print(
+                    f"Warning: {self.friendly_name}, {self.name} detected some issues with your code formatting..."
+                )
             return False
         else:
             # The formatter failed but didn't output a diff (e.g. some sort of
@@ -118,7 +163,7 @@ class ClangFormatHelper(FormatHelper):
     def should_include_extensionless_file(self, path: str) -> bool:
         return path.startswith("libcxx/include")
 
-    def filter_changed_files(self, changed_files: list[str]) -> list[str]:
+    def filter_changed_files(self, changed_files: List[str]) -> List[str]:
         filtered_files = []
         for path in changed_files:
             _, ext = os.path.splitext(path)
@@ -128,32 +173,49 @@ class ClangFormatHelper(FormatHelper):
                 filtered_files.append(path)
         return filtered_files
 
-    def format_run(
-        self, changed_files: list[str], args: argparse.Namespace
-    ) -> str | None:
+    @property
+    def clang_fmt_path(self) -> str:
+        if "CLANG_FORMAT_PATH" in os.environ:
+            return os.environ["CLANG_FORMAT_PATH"]
+        return "git-clang-format"
+
+    def has_tool(self) -> bool:
+        cmd = [self.clang_fmt_path, "-h"]
+        proc = None
+        try:
+            proc = subprocess.run(cmd, stdout=subprocess.PIPE, stderr=subprocess.PIPE)
+        except:
+            return False
+        return proc.returncode == 0
+
+    def format_run(self, changed_files: List[str], args: FormatArgs) -> Optional[str]:
         cpp_files = self.filter_changed_files(changed_files)
         if not cpp_files:
             return None
-        cf_cmd = [
-            "git-clang-format",
-            "--diff",
-            args.start_rev,
-            args.end_rev,
-            "--",
-        ] + cpp_files
-        print(f"Running: {' '.join(cf_cmd)}")
+
+        cf_cmd = [self.clang_fmt_path, "--diff"]
+
+        if args.start_rev and args.end_rev:
+            cf_cmd.append(args.start_rev)
+            cf_cmd.append(args.end_rev)
+
+        cf_cmd.append("--")
+        cf_cmd += cpp_files
+
+        if args.verbose:
+            print(f"Running: {' '.join(cf_cmd)}")
         self.cf_cmd = cf_cmd
-        proc = subprocess.run(cf_cmd, capture_output=True)
+        proc = subprocess.run(cf_cmd, stdout=subprocess.PIPE, stderr=subprocess.PIPE)
         sys.stdout.write(proc.stderr.decode("utf-8"))
 
         if proc.returncode != 0:
             # formatting needed, or the command otherwise failed
-            print(f"error: {self.name} exited with code {proc.returncode}")
-            # Print the diff in the log so that it is viewable there
-            print(proc.stdout.decode("utf-8"))
+            if args.verbose:
+                print(f"error: {self.name} exited with code {proc.returncode}")
+                # Print the diff in the log so that it is viewable there
+                print(proc.stdout.decode("utf-8"))
             return proc.stdout.decode("utf-8")
         else:
-            sys.stdout.write(proc.stdout.decode("utf-8"))
             return None
 
 
@@ -165,7 +227,7 @@ class DarkerFormatHelper(FormatHelper):
     def instructions(self) -> str:
         return " ".join(self.darker_cmd)
 
-    def filter_changed_files(self, changed_files: list[str]) -> list[str]:
+    def filter_changed_files(self, changed_files: List[str]) -> List[str]:
         filtered_files = []
         for path in changed_files:
             name, ext = os.path.splitext(path)
@@ -174,29 +236,48 @@ class DarkerFormatHelper(FormatHelper):
 
         return filtered_files
 
-    def format_run(
-        self, changed_files: list[str], args: argparse.Namespace
-    ) -> str | None:
+    @property
+    def darker_fmt_path(self) -> str:
+        if "DARKER_FORMAT_PATH" in os.environ:
+            return os.environ["DARKER_FORMAT_PATH"]
+        return "darker"
+
+    def has_tool(self) -> bool:
+        cmd = [self.darker_fmt_path, "--version"]
+        proc = None
+        try:
+            proc = subprocess.run(cmd, stdout=subprocess.PIPE, stderr=subprocess.PIPE)
+        except:
+            return False
+        return proc.returncode == 0
+
+    def format_run(self, changed_files: List[str], args: FormatArgs) -> Optional[str]:
         py_files = self.filter_changed_files(changed_files)
         if not py_files:
             return None
         darker_cmd = [
-            "darker",
+            self.darker_fmt_path,
             "--check",
             "--diff",
-            "-r",
-            f"{args.start_rev}...{args.end_rev}",
-        ] + py_files
-        print(f"Running: {' '.join(darker_cmd)}")
+        ]
+        if args.start_rev and args.end_rev:
+            darker_cmd += ["-r", f"{args.start_rev}...{args.end_rev}"]
+        darker_cmd += py_files
+        if args.verbose:
+            print(f"Running: {' '.join(darker_cmd)}")
         self.darker_cmd = darker_cmd
-        proc = subprocess.run(darker_cmd, capture_output=True)
-        sys.stdout.write(proc.stderr.decode("utf-8"))
+        proc = subprocess.run(
+            darker_cmd, stdout=subprocess.PIPE, stderr=subprocess.PIPE
+        )
+        if args.verbose:
+            sys.stdout.write(proc.stderr.decode("utf-8"))
 
         if proc.returncode != 0:
             # formatting needed, or the command otherwise failed
-            print(f"error: {self.name} exited with code {proc.returncode}")
-            # Print the diff in the log so that it is viewable there
-            print(proc.stdout.decode("utf-8"))
+            if args.verbose:
+                print(f"error: {self.name} exited with code {proc.returncode}")
+                # Print the diff in the log so that it is viewable there
+                print(proc.stdout.decode("utf-8"))
             return proc.stdout.decode("utf-8")
         else:
             sys.stdout.write(proc.stdout.decode("utf-8"))
@@ -205,7 +286,39 @@ class DarkerFormatHelper(FormatHelper):
 
 ALL_FORMATTERS = (DarkerFormatHelper(), ClangFormatHelper())
 
+
+def hook_main():
+    # fill out args
+    args = FormatArgs()
+    args.verbose = False
+
+    # find the changed files
+    cmd = ["git", "diff", "--cached", "--name-only", "--diff-filter=d"]
+    proc = subprocess.run(cmd, stdout=subprocess.PIPE, stderr=subprocess.PIPE)
+    output = proc.stdout.decode("utf-8")
+    for line in output.splitlines():
+        args.changed_files.append(line)
+
+    failed_fmts = []
+    for fmt in ALL_FORMATTERS:
+        if fmt.has_tool():
+            if not fmt.run(args.changed_files, args):
+                failed_fmts.append(fmt.name)
+        else:
+            print(f"Couldn't find {fmt.name}, can't check " + fmt.friendly_name.lower())
+
+    if len(failed_fmts) > 0:
+        sys.exit(1)
+
+    sys.exit(0)
+
+
 if __name__ == "__main__":
+    script_path = os.path.abspath(__file__)
+    if ".git/hooks" in script_path:
+        hook_main()
+        sys.exit(0)
+
     parser = argparse.ArgumentParser()
     parser.add_argument(
         "--token", type=str, required=True, help="GitHub authentiation token"
@@ -232,7 +345,7 @@ if __name__ == "__main__":
         help="Comma separated list of files that has been changed",
     )
 
-    args = parser.parse_args()
+    args = FormatArgs(parser.parse_args())
 
     changed_files = []
     if args.changed_files:
-- 
GitLab


From 86763a8cc499baa0328ea485d3823875946de023 Mon Sep 17 00:00:00 2001
From: Quinton Miller <nicetas.c@gmail.com>
Date: Mon, 11 Dec 2023 16:47:33 +0800
Subject: [PATCH 084/349] [LLVM-C] Support operand bundles (#73914)

Added the following functions for manipulating operand bundles, as well as
building ``call`` and ``invoke`` instructions that use operand bundles:

  * LLVMBuildCallWithOperandBundles
  * LLVMBuildInvokeWithOperandBundles
  * LLVMCreateOperandBundle
  * LLVMDisposeOperandBundle
  * LLVMGetNumOperandBundles
  * LLVMGetOperandBundleAtIndex
  * LLVMGetNumOperandBundleArgs
  * LLVMGetOperandBundleArgAtIndex
  * LLVMGetOperandBundleTag

Fixes #71873.
---
 llvm/docs/ReleaseNotes.rst        | 13 +++++
 llvm/include/llvm-c/Core.h        | 95 +++++++++++++++++++++++++++++++
 llvm/include/llvm-c/Types.h       |  5 ++
 llvm/lib/IR/Core.cpp              | 69 ++++++++++++++++++++++
 llvm/test/Bindings/llvm-c/echo.ll | 11 ++++
 llvm/tools/llvm-c-test/echo.cpp   | 46 ++++++++++++---
 6 files changed, 232 insertions(+), 7 deletions(-)

diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index fcb671cf1dfa..6b70146efe82 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -206,6 +206,19 @@ Changes to the C API
   on zext instructions, and ``LLVMGetIsDisjoint`` and ``LLVMSetIsDisjoint``
   for getting/setting the new disjoint flag on or instructions.
 
+* Added the following functions for manipulating operand bundles, as well as
+  building ``call`` and ``invoke`` instructions that use operand bundles:
+
+  * ``LLVMBuildCallWithOperandBundles``
+  * ``LLVMBuildInvokeWithOperandBundles``
+  * ``LLVMCreateOperandBundle``
+  * ``LLVMDisposeOperandBundle``
+  * ``LLVMGetNumOperandBundles``
+  * ``LLVMGetOperandBundleAtIndex``
+  * ``LLVMGetNumOperandBundleArgs``
+  * ``LLVMGetOperandBundleArgAtIndex``
+  * ``LLVMGetOperandBundleTag``
+
 Changes to the CodeGen infrastructure
 -------------------------------------
 
diff --git a/llvm/include/llvm-c/Core.h b/llvm/include/llvm-c/Core.h
index a575ec3709fe..7cb809d378c9 100644
--- a/llvm/include/llvm-c/Core.h
+++ b/llvm/include/llvm-c/Core.h
@@ -3000,6 +3000,74 @@ LLVMValueRef LLVMMDNodeInContext(LLVMContextRef C, LLVMValueRef *Vals,
 /** Deprecated: Use LLVMMDNodeInContext2 instead. */
 LLVMValueRef LLVMMDNode(LLVMValueRef *Vals, unsigned Count);
 
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LLVMCCoreOperandBundle Operand Bundles
+ *
+ * Functions in this group operate on LLVMOperandBundleRef instances that
+ * correspond to llvm::OperandBundleDef instances.
+ *
+ * @see llvm::OperandBundleDef
+ *
+ * @{
+ */
+
+/**
+ * Create a new operand bundle.
+ *
+ * Every invocation should be paired with LLVMDisposeOperandBundle() or memory
+ * will be leaked.
+ *
+ * @param Tag Tag name of the operand bundle
+ * @param TagLen Length of Tag
+ * @param Args Memory address of an array of bundle operands
+ * @param NumArgs Length of Args
+ */
+LLVMOperandBundleRef LLVMCreateOperandBundle(const char *Tag, size_t TagLen,
+                                             LLVMValueRef *Args,
+                                             unsigned NumArgs);
+
+/**
+ * Destroy an operand bundle.
+ *
+ * This must be called for every created operand bundle or memory will be
+ * leaked.
+ */
+void LLVMDisposeOperandBundle(LLVMOperandBundleRef Bundle);
+
+/**
+ * Obtain the tag of an operand bundle as a string.
+ *
+ * @param Bundle Operand bundle to obtain tag of.
+ * @param Len Out parameter which holds the length of the returned string.
+ * @return The tag name of Bundle.
+ * @see OperandBundleDef::getTag()
+ */
+const char *LLVMGetOperandBundleTag(LLVMOperandBundleRef Bundle, size_t *Len);
+
+/**
+ * Obtain the number of operands for an operand bundle.
+ *
+ * @param Bundle Operand bundle to obtain operand count of.
+ * @return The number of operands.
+ * @see OperandBundleDef::input_size()
+ */
+unsigned LLVMGetNumOperandBundleArgs(LLVMOperandBundleRef Bundle);
+
+/**
+ * Obtain the operand for an operand bundle at the given index.
+ *
+ * @param Bundle Operand bundle to obtain operand of.
+ * @param Index An operand index, must be less than
+ * LLVMGetNumOperandBundleArgs().
+ * @return The operand.
+ */
+LLVMValueRef LLVMGetOperandBundleArgAtIndex(LLVMOperandBundleRef Bundle,
+                                            unsigned Index);
+
 /**
  * @}
  */
@@ -3451,6 +3519,24 @@ LLVMTypeRef LLVMGetCalledFunctionType(LLVMValueRef C);
  */
 LLVMValueRef LLVMGetCalledValue(LLVMValueRef Instr);
 
+/**
+ * Obtain the number of operand bundles attached to this instruction.
+ *
+ * This only works on llvm::CallInst and llvm::InvokeInst instructions.
+ *
+ * @see llvm::CallBase::getNumOperandBundles()
+ */
+unsigned LLVMGetNumOperandBundles(LLVMValueRef C);
+
+/**
+ * Obtain the operand bundle attached to this instruction at the given index.
+ * Use LLVMDisposeOperandBundle to free the operand bundle.
+ *
+ * This only works on llvm::CallInst and llvm::InvokeInst instructions.
+ */
+LLVMOperandBundleRef LLVMGetOperandBundleAtIndex(LLVMValueRef C,
+                                                 unsigned Index);
+
 /**
  * Obtain whether a call instruction is a tail call.
  *
@@ -3815,6 +3901,10 @@ LLVMValueRef LLVMBuildInvoke2(LLVMBuilderRef, LLVMTypeRef Ty, LLVMValueRef Fn,
                               LLVMValueRef *Args, unsigned NumArgs,
                               LLVMBasicBlockRef Then, LLVMBasicBlockRef Catch,
                               const char *Name);
+LLVMValueRef LLVMBuildInvokeWithOperandBundles(
+    LLVMBuilderRef, LLVMTypeRef Ty, LLVMValueRef Fn, LLVMValueRef *Args,
+    unsigned NumArgs, LLVMBasicBlockRef Then, LLVMBasicBlockRef Catch,
+    LLVMOperandBundleRef *Bundles, unsigned NumBundles, const char *Name);
 LLVMValueRef LLVMBuildUnreachable(LLVMBuilderRef);
 
 /* Exception Handling */
@@ -4121,6 +4211,11 @@ LLVMValueRef LLVMBuildPhi(LLVMBuilderRef, LLVMTypeRef Ty, const char *Name);
 LLVMValueRef LLVMBuildCall2(LLVMBuilderRef, LLVMTypeRef, LLVMValueRef Fn,
                             LLVMValueRef *Args, unsigned NumArgs,
                             const char *Name);
+LLVMValueRef
+LLVMBuildCallWithOperandBundles(LLVMBuilderRef, LLVMTypeRef, LLVMValueRef Fn,
+                                LLVMValueRef *Args, unsigned NumArgs,
+                                LLVMOperandBundleRef *Bundles,
+                                unsigned NumBundles, const char *Name);
 LLVMValueRef LLVMBuildSelect(LLVMBuilderRef, LLVMValueRef If,
                              LLVMValueRef Then, LLVMValueRef Else,
                              const char *Name);
diff --git a/llvm/include/llvm-c/Types.h b/llvm/include/llvm-c/Types.h
index 4e9967372d79..d5474d986309 100644
--- a/llvm/include/llvm-c/Types.h
+++ b/llvm/include/llvm-c/Types.h
@@ -132,6 +132,11 @@ typedef struct LLVMOpaquePassManager *LLVMPassManagerRef;
  * @see llvm::Use */
 typedef struct LLVMOpaqueUse *LLVMUseRef;
 
+/**
+ * @see llvm::OperandBundleDef
+ */
+typedef struct LLVMOpaqueOperandBundle *LLVMOperandBundleRef;
+
 /**
  * Used to represent an attributes.
  *
diff --git a/llvm/lib/IR/Core.cpp b/llvm/lib/IR/Core.cpp
index 7832028bf367..96629de8a753 100644
--- a/llvm/lib/IR/Core.cpp
+++ b/llvm/lib/IR/Core.cpp
@@ -43,6 +43,8 @@
 
 using namespace llvm;
 
+DEFINE_SIMPLE_CONVERSION_FUNCTIONS(OperandBundleDef, LLVMOperandBundleRef)
+
 #define DEBUG_TYPE "ir"
 
 void llvm::initializeCore(PassRegistry &Registry) {
@@ -2567,6 +2569,34 @@ void LLVMRemoveGlobalIFunc(LLVMValueRef IFunc) {
   unwrap<GlobalIFunc>(IFunc)->removeFromParent();
 }
 
+/*--.. Operations on operand bundles........................................--*/
+
+LLVMOperandBundleRef LLVMCreateOperandBundle(const char *Tag, size_t TagLen,
+                                             LLVMValueRef *Args,
+                                             unsigned NumArgs) {
+  return wrap(new OperandBundleDef(std::string(Tag, TagLen),
+                                   ArrayRef(unwrap(Args), NumArgs)));
+}
+
+void LLVMDisposeOperandBundle(LLVMOperandBundleRef Bundle) {
+  delete unwrap(Bundle);
+}
+
+const char *LLVMGetOperandBundleTag(LLVMOperandBundleRef Bundle, size_t *Len) {
+  StringRef Str = unwrap(Bundle)->getTag();
+  *Len = Str.size();
+  return Str.data();
+}
+
+unsigned LLVMGetNumOperandBundleArgs(LLVMOperandBundleRef Bundle) {
+  return unwrap(Bundle)->inputs().size();
+}
+
+LLVMValueRef LLVMGetOperandBundleArgAtIndex(LLVMOperandBundleRef Bundle,
+                                            unsigned Index) {
+  return wrap(unwrap(Bundle)->inputs()[Index]);
+}
+
 /*--.. Operations on basic blocks ..........................................--*/
 
 LLVMValueRef LLVMBasicBlockAsValue(LLVMBasicBlockRef BB) {
@@ -2858,6 +2888,16 @@ LLVMTypeRef LLVMGetCalledFunctionType(LLVMValueRef Instr) {
   return wrap(unwrap<CallBase>(Instr)->getFunctionType());
 }
 
+unsigned LLVMGetNumOperandBundles(LLVMValueRef C) {
+  return unwrap<CallBase>(C)->getNumOperandBundles();
+}
+
+LLVMOperandBundleRef LLVMGetOperandBundleAtIndex(LLVMValueRef C,
+                                                 unsigned Index) {
+  return wrap(
+      new OperandBundleDef(unwrap<CallBase>(C)->getOperandBundleAt(Index)));
+}
+
 /*--.. Operations on call instructions (only) ..............................--*/
 
 LLVMBool LLVMIsTailCall(LLVMValueRef Call) {
@@ -3140,6 +3180,20 @@ LLVMValueRef LLVMBuildInvoke2(LLVMBuilderRef B, LLVMTypeRef Ty, LLVMValueRef Fn,
                                       ArrayRef(unwrap(Args), NumArgs), Name));
 }
 
+LLVMValueRef LLVMBuildInvokeWithOperandBundles(
+    LLVMBuilderRef B, LLVMTypeRef Ty, LLVMValueRef Fn, LLVMValueRef *Args,
+    unsigned NumArgs, LLVMBasicBlockRef Then, LLVMBasicBlockRef Catch,
+    LLVMOperandBundleRef *Bundles, unsigned NumBundles, const char *Name) {
+  SmallVector<OperandBundleDef, 8> OBs;
+  for (auto *Bundle : ArrayRef(Bundles, NumBundles)) {
+    OperandBundleDef *OB = unwrap(Bundle);
+    OBs.push_back(*OB);
+  }
+  return wrap(unwrap(B)->CreateInvoke(
+      unwrap<FunctionType>(Ty), unwrap(Fn), unwrap(Then), unwrap(Catch),
+      ArrayRef(unwrap(Args), NumArgs), OBs, Name));
+}
+
 LLVMValueRef LLVMBuildLandingPad(LLVMBuilderRef B, LLVMTypeRef Ty,
                                  LLVMValueRef PersFn, unsigned NumClauses,
                                  const char *Name) {
@@ -3878,6 +3932,21 @@ LLVMValueRef LLVMBuildCall2(LLVMBuilderRef B, LLVMTypeRef Ty, LLVMValueRef Fn,
                                     ArrayRef(unwrap(Args), NumArgs), Name));
 }
 
+LLVMValueRef
+LLVMBuildCallWithOperandBundles(LLVMBuilderRef B, LLVMTypeRef Ty,
+                                LLVMValueRef Fn, LLVMValueRef *Args,
+                                unsigned NumArgs, LLVMOperandBundleRef *Bundles,
+                                unsigned NumBundles, const char *Name) {
+  FunctionType *FTy = unwrap<FunctionType>(Ty);
+  SmallVector<OperandBundleDef, 8> OBs;
+  for (auto *Bundle : ArrayRef(Bundles, NumBundles)) {
+    OperandBundleDef *OB = unwrap(Bundle);
+    OBs.push_back(*OB);
+  }
+  return wrap(unwrap(B)->CreateCall(
+      FTy, unwrap(Fn), ArrayRef(unwrap(Args), NumArgs), OBs, Name));
+}
+
 LLVMValueRef LLVMBuildSelect(LLVMBuilderRef B, LLVMValueRef If,
                              LLVMValueRef Then, LLVMValueRef Else,
                              const char *Name) {
diff --git a/llvm/test/Bindings/llvm-c/echo.ll b/llvm/test/Bindings/llvm-c/echo.ll
index 0775cbb673e4..2e195beebd7b 100644
--- a/llvm/test/Bindings/llvm-c/echo.ll
+++ b/llvm/test/Bindings/llvm-c/echo.ll
@@ -269,6 +269,17 @@ exit:
   ret void
 }
 
+define void @operandbundles() personality ptr @personalityFn {
+  call void @decl() [ "foo"(), "bar\00x"(i32 0, ptr null, token none) ]
+  invoke void @decl() [ "baz"(label %bar) ] to label %foo unwind label %bar
+foo:
+  ret void
+bar:
+  %1 = landingpad { ptr, i32 }
+          cleanup
+  ret void
+}
+
 define void @with_debuginfo() !dbg !4 {
   ret void, !dbg !7
 }
diff --git a/llvm/tools/llvm-c-test/echo.cpp b/llvm/tools/llvm-c-test/echo.cpp
index e2617583ff9b..bfc14e85a12b 100644
--- a/llvm/tools/llvm-c-test/echo.cpp
+++ b/llvm/tools/llvm-c-test/echo.cpp
@@ -548,16 +548,26 @@ struct FunCloner {
         break;
       case LLVMInvoke: {
         SmallVector<LLVMValueRef, 8> Args;
-        int ArgCount = LLVMGetNumArgOperands(Src);
-        for (int i = 0; i < ArgCount; i++)
+        SmallVector<LLVMOperandBundleRef, 8> Bundles;
+        unsigned ArgCount = LLVMGetNumArgOperands(Src);
+        for (unsigned i = 0; i < ArgCount; ++i)
           Args.push_back(CloneValue(LLVMGetOperand(Src, i)));
+        unsigned BundleCount = LLVMGetNumOperandBundles(Src);
+        for (unsigned i = 0; i < BundleCount; ++i) {
+          auto Bundle = LLVMGetOperandBundleAtIndex(Src, i);
+          Bundles.push_back(CloneOB(Bundle));
+          LLVMDisposeOperandBundle(Bundle);
+        }
         LLVMTypeRef FnTy = CloneType(LLVMGetCalledFunctionType(Src));
         LLVMValueRef Fn = CloneValue(LLVMGetCalledValue(Src));
         LLVMBasicBlockRef Then = DeclareBB(LLVMGetNormalDest(Src));
         LLVMBasicBlockRef Unwind = DeclareBB(LLVMGetUnwindDest(Src));
-        Dst = LLVMBuildInvoke2(Builder, FnTy, Fn, Args.data(), ArgCount,
-                               Then, Unwind, Name);
+        Dst = LLVMBuildInvokeWithOperandBundles(
+            Builder, FnTy, Fn, Args.data(), ArgCount, Then, Unwind,
+            Bundles.data(), Bundles.size(), Name);
         CloneAttrs(Src, Dst);
+        for (auto Bundle : Bundles)
+          LLVMDisposeOperandBundle(Bundle);
         break;
       }
       case LLVMUnreachable:
@@ -764,14 +774,25 @@ struct FunCloner {
       }
       case LLVMCall: {
         SmallVector<LLVMValueRef, 8> Args;
-        int ArgCount = LLVMGetNumArgOperands(Src);
-        for (int i = 0; i < ArgCount; i++)
+        SmallVector<LLVMOperandBundleRef, 8> Bundles;
+        unsigned ArgCount = LLVMGetNumArgOperands(Src);
+        for (unsigned i = 0; i < ArgCount; ++i)
           Args.push_back(CloneValue(LLVMGetOperand(Src, i)));
+        unsigned BundleCount = LLVMGetNumOperandBundles(Src);
+        for (unsigned i = 0; i < BundleCount; ++i) {
+          auto Bundle = LLVMGetOperandBundleAtIndex(Src, i);
+          Bundles.push_back(CloneOB(Bundle));
+          LLVMDisposeOperandBundle(Bundle);
+        }
         LLVMTypeRef FnTy = CloneType(LLVMGetCalledFunctionType(Src));
         LLVMValueRef Fn = CloneValue(LLVMGetCalledValue(Src));
-        Dst = LLVMBuildCall2(Builder, FnTy, Fn, Args.data(), ArgCount, Name);
+        Dst = LLVMBuildCallWithOperandBundles(Builder, FnTy, Fn, Args.data(),
+                                              ArgCount, Bundles.data(),
+                                              Bundles.size(), Name);
         LLVMSetTailCallKind(Dst, LLVMGetTailCallKind(Src));
         CloneAttrs(Src, Dst);
+        for (auto Bundle : Bundles)
+          LLVMDisposeOperandBundle(Bundle);
         break;
       }
       case LLVMResume: {
@@ -935,6 +956,17 @@ struct FunCloner {
     return VMap[Src] = Dst;
   }
 
+  LLVMOperandBundleRef CloneOB(LLVMOperandBundleRef Src) {
+    size_t TagLen;
+    const char *Tag = LLVMGetOperandBundleTag(Src, &TagLen);
+
+    SmallVector<LLVMValueRef, 8> Args;
+    for (unsigned i = 0, n = LLVMGetNumOperandBundleArgs(Src); i != n; ++i)
+      Args.push_back(CloneValue(LLVMGetOperandBundleArgAtIndex(Src, i)));
+
+    return LLVMCreateOperandBundle(Tag, TagLen, Args.data(), Args.size());
+  }
+
   LLVMBasicBlockRef DeclareBB(LLVMBasicBlockRef Src) {
     // Check if this is something we already computed.
     {
-- 
GitLab


From 65b12a8af37ffa390ff45c8215904513eb75659e Mon Sep 17 00:00:00 2001
From: Chuanqi Xu <yedeng.yd@linux.alibaba.com>
Date: Thu, 7 Dec 2023 17:01:06 +0800
Subject: [PATCH 085/349] Recommit [NFC] [Serialization] Packing more bits

This patch tries to reduce the size of the BMIs by packing more bits
into an unsigned integer.

This patch was reverted due to buildbot failure report. But it should be
irrevelent after I took a double look. So I tried to recommit this NFC
change again.
---
 clang/include/clang/Serialization/ASTReader.h |   7 +-
 clang/lib/Serialization/ASTReaderDecl.cpp     |  21 ++-
 clang/lib/Serialization/ASTReaderStmt.cpp     |  95 ++++++-----
 clang/lib/Serialization/ASTWriterDecl.cpp     | 156 ++++++++----------
 clang/lib/Serialization/ASTWriterStmt.cpp     |  36 ++--
 clang/test/Modules/decl-params-determinisim.m |  16 +-
 6 files changed, 178 insertions(+), 153 deletions(-)

diff --git a/clang/include/clang/Serialization/ASTReader.h b/clang/include/clang/Serialization/ASTReader.h
index 7eefdca6815c..9bb89ec94109 100644
--- a/clang/include/clang/Serialization/ASTReader.h
+++ b/clang/include/clang/Serialization/ASTReader.h
@@ -2415,12 +2415,7 @@ public:
   BitsUnpacker(BitsUnpacker &&) = delete;
   BitsUnpacker operator=(const BitsUnpacker &) = delete;
   BitsUnpacker operator=(BitsUnpacker &&) = delete;
-  ~BitsUnpacker() {
-#ifndef NDEBUG
-    while (isValid())
-      assert(!getNextBit() && "There are unprocessed bits!");
-#endif
-  }
+  ~BitsUnpacker() = default;
 
   void updateValue(uint32_t V) {
     Value = V;
diff --git a/clang/lib/Serialization/ASTReaderDecl.cpp b/clang/lib/Serialization/ASTReaderDecl.cpp
index bc16cfc67a24..7140a14aefbf 100644
--- a/clang/lib/Serialization/ASTReaderDecl.cpp
+++ b/clang/lib/Serialization/ASTReaderDecl.cpp
@@ -583,6 +583,9 @@ void ASTDeclReader::Visit(Decl *D) {
 }
 
 void ASTDeclReader::VisitDecl(Decl *D) {
+  BitsUnpacker DeclBits(Record.readInt());
+  bool HasStandaloneLexicalDC = DeclBits.getNextBit();
+
   if (D->isTemplateParameter() || D->isTemplateParameterPack() ||
       isa<ParmVarDecl, ObjCTypeParamDecl>(D)) {
     // We don't want to deserialize the DeclContext of a template
@@ -592,7 +595,8 @@ void ASTDeclReader::VisitDecl(Decl *D) {
     // return type of the function).  Use the translation unit DeclContext as a
     // placeholder.
     GlobalDeclID SemaDCIDForTemplateParmDecl = readDeclID();
-    GlobalDeclID LexicalDCIDForTemplateParmDecl = readDeclID();
+    GlobalDeclID LexicalDCIDForTemplateParmDecl =
+        HasStandaloneLexicalDC ? readDeclID() : 0;
     if (!LexicalDCIDForTemplateParmDecl)
       LexicalDCIDForTemplateParmDecl = SemaDCIDForTemplateParmDecl;
     Reader.addPendingDeclContextInfo(D,
@@ -601,7 +605,8 @@ void ASTDeclReader::VisitDecl(Decl *D) {
     D->setDeclContext(Reader.getContext().getTranslationUnitDecl());
   } else {
     auto *SemaDC = readDeclAs<DeclContext>();
-    auto *LexicalDC = readDeclAs<DeclContext>();
+    auto *LexicalDC =
+        HasStandaloneLexicalDC ? readDeclAs<DeclContext>() : nullptr;
     if (!LexicalDC)
       LexicalDC = SemaDC;
     // If the context is a class, we might not have actually merged it yet, in
@@ -618,7 +623,6 @@ void ASTDeclReader::VisitDecl(Decl *D) {
   }
   D->setLocation(ThisDeclLoc);
 
-  BitsUnpacker DeclBits(Record.readInt());
   D->InvalidDecl = DeclBits.getNextBit();
   bool HasAttrs = DeclBits.getNextBit();
   D->setImplicit(DeclBits.getNextBit());
@@ -765,7 +769,7 @@ ASTDeclReader::RedeclarableResult ASTDeclReader::VisitTagDecl(TagDecl *TD) {
   TD->setCompleteDefinitionRequired(TagDeclBits.getNextBit());
   TD->setBraceRange(readSourceRange());
 
-  switch (Record.readInt()) {
+  switch (TagDeclBits.getNextBits(/*Width=*/2)) {
   case 0:
     break;
   case 1: { // ExtInfo
@@ -1089,7 +1093,8 @@ void ASTDeclReader::VisitFunctionDecl(FunctionDecl *FD) {
   FD->setCachedLinkage((Linkage)FunctionDeclBits.getNextBits(/*Width=*/3));
 
   FD->EndRangeLoc = readSourceLocation();
-  FD->setDefaultLoc(readSourceLocation());
+  if (FD->isExplicitlyDefaulted())
+    FD->setDefaultLoc(readSourceLocation());
 
   FD->ODRHash = Record.readInt();
   FD->setHasODRHash(true);
@@ -1703,7 +1708,7 @@ void ASTDeclReader::VisitParmVarDecl(ParmVarDecl *PD) {
   unsigned isObjCMethodParam = ParmVarDeclBits.getNextBit();
   unsigned scopeDepth = ParmVarDeclBits.getNextBits(/*Width=*/7);
   unsigned scopeIndex = ParmVarDeclBits.getNextBits(/*Width=*/8);
-  unsigned declQualifier = Record.readInt();
+  unsigned declQualifier = ParmVarDeclBits.getNextBits(/*Width=*/7);
   if (isObjCMethodParam) {
     assert(scopeDepth == 0);
     PD->setObjCMethodScopeInfo(scopeIndex);
@@ -1716,7 +1721,9 @@ void ASTDeclReader::VisitParmVarDecl(ParmVarDecl *PD) {
   PD->ParmVarDeclBits.HasInheritedDefaultArg = ParmVarDeclBits.getNextBit();
   if (ParmVarDeclBits.getNextBit()) // hasUninstantiatedDefaultArg.
     PD->setUninstantiatedDefaultArg(Record.readExpr());
-  PD->ExplicitObjectParameterIntroducerLoc = Record.readSourceLocation();
+
+  if (ParmVarDeclBits.getNextBit()) // Valid explicit object parameter
+    PD->ExplicitObjectParameterIntroducerLoc = Record.readSourceLocation();
 
   // FIXME: If this is a redeclaration of a function from another module, handle
   // inheritance of default arguments.
diff --git a/clang/lib/Serialization/ASTReaderStmt.cpp b/clang/lib/Serialization/ASTReaderStmt.cpp
index d7d0c0e5bb21..d9eedb2e1089 100644
--- a/clang/lib/Serialization/ASTReaderStmt.cpp
+++ b/clang/lib/Serialization/ASTReaderStmt.cpp
@@ -108,7 +108,7 @@ namespace clang {
 
     /// The number of record fields required for the Expr class
     /// itself.
-    static const unsigned NumExprFields = NumStmtFields + 4;
+    static const unsigned NumExprFields = NumStmtFields + 2;
 
     /// Read and initialize a ExplicitTemplateArgumentList structure.
     void ReadTemplateKWAndArgsInfo(ASTTemplateKWAndArgsInfo &Args,
@@ -524,9 +524,13 @@ void ASTStmtReader::VisitCapturedStmt(CapturedStmt *S) {
 void ASTStmtReader::VisitExpr(Expr *E) {
   VisitStmt(E);
   E->setType(Record.readType());
-  E->setDependence(static_cast<ExprDependence>(Record.readInt()));
-  E->setValueKind(static_cast<ExprValueKind>(Record.readInt()));
-  E->setObjectKind(static_cast<ExprObjectKind>(Record.readInt()));
+  BitsUnpacker ExprBits(Record.readInt());
+  E->setDependence(
+      static_cast<ExprDependence>(ExprBits.getNextBits(/*Width=*/5)));
+  E->setValueKind(
+      static_cast<ExprValueKind>(ExprBits.getNextBits(/*Width=*/2)));
+  E->setObjectKind(
+      static_cast<ExprObjectKind>(ExprBits.getNextBits(/*Width=*/3)));
   assert(Record.getIdx() == NumExprFields &&
          "Incorrect expression field count");
 }
@@ -995,14 +999,19 @@ void ASTStmtReader::VisitOMPIteratorExpr(OMPIteratorExpr *E) {
 
 void ASTStmtReader::VisitCallExpr(CallExpr *E) {
   VisitExpr(E);
-  unsigned NumArgs = Record.readInt();
-  bool HasFPFeatures = Record.readInt();
+
+  BitsUnpacker CallExprBits = Record.readInt();
+
+  unsigned NumArgs = CallExprBits.getNextBits(/*Width=*/16);
+  bool HasFPFeatures = CallExprBits.getNextBit();
+  E->setADLCallKind(
+      static_cast<CallExpr::ADLCallKind>(CallExprBits.getNextBit()));
   assert((NumArgs == E->getNumArgs()) && "Wrong NumArgs!");
   E->setRParenLoc(readSourceLocation());
   E->setCallee(Record.readSubExpr());
   for (unsigned I = 0; I != NumArgs; ++I)
     E->setArg(I, Record.readSubExpr());
-  E->setADLCallKind(static_cast<CallExpr::ADLCallKind>(Record.readInt()));
+
   if (HasFPFeatures)
     E->setStoredFPFeatures(
         FPOptionsOverride::getFromOpaqueInt(Record.readInt()));
@@ -2013,14 +2022,15 @@ ASTStmtReader::VisitCXXUnresolvedConstructExpr(CXXUnresolvedConstructExpr *E) {
 void ASTStmtReader::VisitOverloadExpr(OverloadExpr *E) {
   VisitExpr(E);
 
-  unsigned NumResults = Record.readInt();
-  bool HasTemplateKWAndArgsInfo = Record.readInt();
+  BitsUnpacker OverloadExprBits = Record.readInt();
+  unsigned NumResults = OverloadExprBits.getNextBits(/*Width=*/14);
+  bool HasTemplateKWAndArgsInfo = OverloadExprBits.getNextBit();
   assert((E->getNumDecls() == NumResults) && "Wrong NumResults!");
   assert((E->hasTemplateKWAndArgsInfo() == HasTemplateKWAndArgsInfo) &&
          "Wrong HasTemplateKWAndArgsInfo!");
 
   if (HasTemplateKWAndArgsInfo) {
-    unsigned NumTemplateArgs = Record.readInt();
+    unsigned NumTemplateArgs = OverloadExprBits.getNextBits(/*Width=*/14);
     ReadTemplateKWAndArgsInfo(*E->getTrailingASTTemplateKWAndArgsInfo(),
                               E->getTrailingTemplateArgumentLoc(),
                               NumTemplateArgs);
@@ -3022,11 +3032,13 @@ Stmt *ASTReader::ReadStmtFromStream(ModuleFile &F) {
                                        Record[ASTStmtReader::NumExprFields]);
       break;
 
-    case EXPR_CALL:
-      S = CallExpr::CreateEmpty(
-          Context, /*NumArgs=*/Record[ASTStmtReader::NumExprFields],
-          /*HasFPFeatures=*/Record[ASTStmtReader::NumExprFields + 1], Empty);
+    case EXPR_CALL: {
+      BitsUnpacker CallExprBits(Record[ASTStmtReader::NumExprFields]);
+      auto NumArgs = CallExprBits.getNextBits(/*Width=*/16);
+      auto HasFPFeatures = CallExprBits.getNextBit();
+      S = CallExpr::CreateEmpty(Context, NumArgs, HasFPFeatures, Empty);
       break;
+    }
 
     case EXPR_RECOVERY:
       S = RecoveryExpr::CreateEmpty(
@@ -3764,17 +3776,23 @@ Stmt *ASTReader::ReadStmtFromStream(ModuleFile &F) {
       break;
     }
 
-    case EXPR_CXX_OPERATOR_CALL:
-      S = CXXOperatorCallExpr::CreateEmpty(
-          Context, /*NumArgs=*/Record[ASTStmtReader::NumExprFields],
-          /*HasFPFeatures=*/Record[ASTStmtReader::NumExprFields + 1], Empty);
+    case EXPR_CXX_OPERATOR_CALL: {
+      BitsUnpacker CallExprBits(Record[ASTStmtReader::NumExprFields]);
+      auto NumArgs = CallExprBits.getNextBits(/*Width=*/16);
+      auto HasFPFeatures = CallExprBits.getNextBit();
+      S = CXXOperatorCallExpr::CreateEmpty(Context, NumArgs, HasFPFeatures,
+                                           Empty);
       break;
+    }
 
-    case EXPR_CXX_MEMBER_CALL:
-      S = CXXMemberCallExpr::CreateEmpty(
-          Context, /*NumArgs=*/Record[ASTStmtReader::NumExprFields],
-          /*HasFPFeatures=*/Record[ASTStmtReader::NumExprFields + 1], Empty);
+    case EXPR_CXX_MEMBER_CALL: {
+      BitsUnpacker CallExprBits(Record[ASTStmtReader::NumExprFields]);
+      auto NumArgs = CallExprBits.getNextBits(/*Width=*/16);
+      auto HasFPFeatures = CallExprBits.getNextBit();
+      S = CXXMemberCallExpr::CreateEmpty(Context, NumArgs, HasFPFeatures,
+                                         Empty);
       break;
+    }
 
     case EXPR_CXX_REWRITTEN_BINARY_OPERATOR:
       S = new (Context) CXXRewrittenBinaryOperator(Empty);
@@ -3948,23 +3966,21 @@ Stmt *ASTReader::ReadStmtFromStream(ModuleFile &F) {
     case EXPR_CXX_UNRESOLVED_MEMBER:
       S = UnresolvedMemberExpr::CreateEmpty(
           Context,
-          /*NumResults=*/Record[ASTStmtReader::NumExprFields],
-          /*HasTemplateKWAndArgsInfo=*/Record[ASTStmtReader::NumExprFields + 1],
-          /*NumTemplateArgs=*/
-          Record[ASTStmtReader::NumExprFields + 1]
-              ? Record[ASTStmtReader::NumExprFields + 2]
-              : 0);
+          /*NumResults=*/Record[ASTStmtReader::NumExprFields] & ((1 << 14) - 1),
+          /*HasTemplateKWAndArgsInfo=*/
+          (Record[ASTStmtReader::NumExprFields] >> 14) & (0x1),
+          /*NumTemplateArgs=*/Record[ASTStmtReader::NumExprFields] >> 14 &
+              ((1 << 14) - 1));
       break;
 
     case EXPR_CXX_UNRESOLVED_LOOKUP:
       S = UnresolvedLookupExpr::CreateEmpty(
           Context,
-          /*NumResults=*/Record[ASTStmtReader::NumExprFields],
-          /*HasTemplateKWAndArgsInfo=*/Record[ASTStmtReader::NumExprFields + 1],
-          /*NumTemplateArgs=*/
-          Record[ASTStmtReader::NumExprFields + 1]
-              ? Record[ASTStmtReader::NumExprFields + 2]
-              : 0);
+          /*NumResults=*/Record[ASTStmtReader::NumExprFields] & ((1 << 14) - 1),
+          /*HasTemplateKWAndArgsInfo=*/
+          (Record[ASTStmtReader::NumExprFields] >> 14) & (0x1),
+          /*NumTemplateArgs=*/Record[ASTStmtReader::NumExprFields] >> 14 &
+              ((1 << 14) - 1));
       break;
 
     case EXPR_TYPE_TRAIT:
@@ -4024,11 +4040,14 @@ Stmt *ASTReader::ReadStmtFromStream(ModuleFile &F) {
       S = new (Context) OpaqueValueExpr(Empty);
       break;
 
-    case EXPR_CUDA_KERNEL_CALL:
-      S = CUDAKernelCallExpr::CreateEmpty(
-          Context, /*NumArgs=*/Record[ASTStmtReader::NumExprFields],
-          /*HasFPFeatures=*/Record[ASTStmtReader::NumExprFields + 1], Empty);
+    case EXPR_CUDA_KERNEL_CALL: {
+      BitsUnpacker CallExprBits(Record[ASTStmtReader::NumExprFields]);
+      auto NumArgs = CallExprBits.getNextBits(/*Width=*/16);
+      auto HasFPFeatures = CallExprBits.getNextBit();
+      S = CUDAKernelCallExpr::CreateEmpty(Context, NumArgs, HasFPFeatures,
+                                          Empty);
       break;
+    }
 
     case EXPR_ASTYPE:
       S = new (Context) AsTypeExpr(Empty);
diff --git a/clang/lib/Serialization/ASTWriterDecl.cpp b/clang/lib/Serialization/ASTWriterDecl.cpp
index bf082e5b8eac..43169b2befc6 100644
--- a/clang/lib/Serialization/ASTWriterDecl.cpp
+++ b/clang/lib/Serialization/ASTWriterDecl.cpp
@@ -320,13 +320,8 @@ void ASTDeclWriter::Visit(Decl *D) {
 }
 
 void ASTDeclWriter::VisitDecl(Decl *D) {
-  Record.AddDeclRef(cast_or_null<Decl>(D->getDeclContext()));
-  if (D->getDeclContext() != D->getLexicalDeclContext())
-    Record.AddDeclRef(cast_or_null<Decl>(D->getLexicalDeclContext()));
-  else
-    Record.push_back(0);
-
   BitsPacker DeclBits;
+  DeclBits.addBit(D->getDeclContext() != D->getLexicalDeclContext());
   DeclBits.addBit(D->isInvalidDecl());
   DeclBits.addBit(D->hasAttrs());
   DeclBits.addBit(D->isImplicit());
@@ -337,6 +332,10 @@ void ASTDeclWriter::VisitDecl(Decl *D) {
   DeclBits.addBits((uint64_t)D->getModuleOwnershipKind(), /*BitWidth=*/3);
   Record.push_back(DeclBits);
 
+  Record.AddDeclRef(cast_or_null<Decl>(D->getDeclContext()));
+  if (D->getDeclContext() != D->getLexicalDeclContext())
+    Record.AddDeclRef(cast_or_null<Decl>(D->getLexicalDeclContext()));
+
   if (D->hasAttrs())
     Record.AddAttributes(D->getAttrs());
 
@@ -450,19 +449,18 @@ void ASTDeclWriter::VisitTagDecl(TagDecl *D) {
   TagDeclBits.addBit(D->isEmbeddedInDeclarator());
   TagDeclBits.addBit(D->isFreeStanding());
   TagDeclBits.addBit(D->isCompleteDefinitionRequired());
+  TagDeclBits.addBits(
+      D->hasExtInfo() ? 1 : (D->getTypedefNameForAnonDecl() ? 2 : 0),
+      /*BitWidth=*/2);
   Record.push_back(TagDeclBits);
 
   Record.AddSourceRange(D->getBraceRange());
 
   if (D->hasExtInfo()) {
-    Record.push_back(1);
     Record.AddQualifierInfo(*D->getExtInfo());
   } else if (auto *TD = D->getTypedefNameForAnonDecl()) {
-    Record.push_back(2);
     Record.AddDeclRef(TD);
     Record.AddIdentifierRef(TD->getDeclName().getAsIdentifierInfo());
-  } else {
-    Record.push_back(0);
   }
 }
 
@@ -702,7 +700,8 @@ void ASTDeclWriter::VisitFunctionDecl(FunctionDecl *D) {
   Record.push_back(FunctionDeclBits);
 
   Record.AddSourceLocation(D->getEndLoc());
-  Record.AddSourceLocation(D->getDefaultLoc());
+  if (D->isExplicitlyDefaulted())
+    Record.AddSourceLocation(D->getDefaultLoc());
 
   Record.push_back(D->getODRHash());
 
@@ -1176,15 +1175,18 @@ void ASTDeclWriter::VisitParmVarDecl(ParmVarDecl *D) {
   ParmVarDeclBits.addBit(D->isObjCMethodParameter());
   ParmVarDeclBits.addBits(D->getFunctionScopeDepth(), /*BitsWidth=*/7);
   ParmVarDeclBits.addBits(D->getFunctionScopeIndex(), /*BitsWidth=*/8);
+  // FIXME: stable encoding
+  ParmVarDeclBits.addBits(D->getObjCDeclQualifier(), /*BitsWidth=*/7);
   ParmVarDeclBits.addBit(D->isKNRPromoted());
   ParmVarDeclBits.addBit(D->hasInheritedDefaultArg());
   ParmVarDeclBits.addBit(D->hasUninstantiatedDefaultArg());
+  ParmVarDeclBits.addBit(D->getExplicitObjectParamThisLoc().isValid());
   Record.push_back(ParmVarDeclBits);
 
-  Record.push_back(D->getObjCDeclQualifier()); // FIXME: stable encoding
   if (D->hasUninstantiatedDefaultArg())
     Record.AddStmt(D->getUninstantiatedDefaultArg());
-  Record.AddSourceLocation(D->getExplicitObjectParamThisLoc());
+  if (D->getExplicitObjectParamThisLoc().isValid())
+    Record.AddSourceLocation(D->getExplicitObjectParamThisLoc());
   Code = serialization::DECL_PARM_VAR;
 
   // If the assumptions about the DECL_PARM_VAR abbrev are true, use it.  Here
@@ -2038,13 +2040,12 @@ void ASTWriter::WriteDeclAbbrevs() {
   Abv = std::make_shared<BitCodeAbbrev>();
   Abv->Add(BitCodeAbbrevOp(serialization::DECL_FIELD));
   // Decl
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
+                           12)); // Packed DeclBits: HasStandaloneLexicalDC,
+                                 // isInvalidDecl, HasAttrs, isImplicit, isUsed,
+                                 // isReferenced, TopLevelDeclInObjCContainer,
+                                 // AccessSpecifier, ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // DeclContext
-  Abv->Add(BitCodeAbbrevOp(0));                       // LexicalDeclContext
-  Abv->Add(BitCodeAbbrevOp(
-      BitCodeAbbrevOp::Fixed,
-      11)); // Packed DeclBits: isInvalidDecl, HasAttrs, isImplicit, isUsed,
-            // isReferenced, TopLevelDeclInObjCContainer, AccessSpecifier,
-            // ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // SubmoduleID
   // NamedDecl
   Abv->Add(BitCodeAbbrevOp(0));                       // NameKind = Identifier
@@ -2068,13 +2069,12 @@ void ASTWriter::WriteDeclAbbrevs() {
   Abv = std::make_shared<BitCodeAbbrev>();
   Abv->Add(BitCodeAbbrevOp(serialization::DECL_OBJC_IVAR));
   // Decl
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
+                           12)); // Packed DeclBits: HasStandaloneLexicalDC,
+                                 // isInvalidDecl, HasAttrs, isImplicit, isUsed,
+                                 // isReferenced, TopLevelDeclInObjCContainer,
+                                 // AccessSpecifier, ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // DeclContext
-  Abv->Add(BitCodeAbbrevOp(0));                       // LexicalDeclContext
-  Abv->Add(BitCodeAbbrevOp(
-      BitCodeAbbrevOp::Fixed,
-      11)); // Packed DeclBits: isInvalidDecl, HasAttrs, isImplicit, isUsed,
-            // isReferenced, TopLevelDeclInObjCContainer, AccessSpecifier,
-            // ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // SubmoduleID
   // NamedDecl
   Abv->Add(BitCodeAbbrevOp(0));                       // NameKind = Identifier
@@ -2103,13 +2103,12 @@ void ASTWriter::WriteDeclAbbrevs() {
   // Redeclarable
   Abv->Add(BitCodeAbbrevOp(0));                       // No redeclaration
   // Decl
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
+                           12)); // Packed DeclBits: HasStandaloneLexicalDC,
+                                 // isInvalidDecl, HasAttrs, isImplicit, isUsed,
+                                 // isReferenced, TopLevelDeclInObjCContainer,
+                                 // AccessSpecifier, ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // DeclContext
-  Abv->Add(BitCodeAbbrevOp(0));                       // LexicalDeclContext
-  Abv->Add(BitCodeAbbrevOp(
-      BitCodeAbbrevOp::Fixed,
-      11)); // Packed DeclBits: isInvalidDecl, HasAttrs, isImplicit, isUsed,
-            // isReferenced, TopLevelDeclInObjCContainer, AccessSpecifier,
-            // ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // SubmoduleID
   // NamedDecl
   Abv->Add(BitCodeAbbrevOp(0));                       // NameKind = Identifier
@@ -2122,11 +2121,11 @@ void ASTWriter::WriteDeclAbbrevs() {
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // IdentifierNamespace
   Abv->Add(BitCodeAbbrevOp(
       BitCodeAbbrevOp::Fixed,
-      7)); // Packed Tag Decl Bits: getTagKind, isCompleteDefinition,
-           // EmbeddedInDeclarator, IsFreeStanding, isCompleteDefinitionRequired
+      9)); // Packed Tag Decl Bits: getTagKind, isCompleteDefinition,
+           // EmbeddedInDeclarator, IsFreeStanding,
+           // isCompleteDefinitionRequired, ExtInfoKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // SourceLocation
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // SourceLocation
-  Abv->Add(BitCodeAbbrevOp(0));                         // ExtInfoKind
   // EnumDecl
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // AddTypeRef
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // IntegerType
@@ -2145,13 +2144,12 @@ void ASTWriter::WriteDeclAbbrevs() {
   // Redeclarable
   Abv->Add(BitCodeAbbrevOp(0));                       // No redeclaration
   // Decl
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
+                           12)); // Packed DeclBits: HasStandaloneLexicalDC,
+                                 // isInvalidDecl, HasAttrs, isImplicit, isUsed,
+                                 // isReferenced, TopLevelDeclInObjCContainer,
+                                 // AccessSpecifier, ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // DeclContext
-  Abv->Add(BitCodeAbbrevOp(0));                       // LexicalDeclContext
-  Abv->Add(BitCodeAbbrevOp(
-      BitCodeAbbrevOp::Fixed,
-      11)); // Packed DeclBits: isInvalidDecl, HasAttrs, isImplicit, isUsed,
-            // isReferenced, TopLevelDeclInObjCContainer, AccessSpecifier,
-            // ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // SubmoduleID
   // NamedDecl
   Abv->Add(BitCodeAbbrevOp(0));                       // NameKind = Identifier
@@ -2164,11 +2162,11 @@ void ASTWriter::WriteDeclAbbrevs() {
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // IdentifierNamespace
   Abv->Add(BitCodeAbbrevOp(
       BitCodeAbbrevOp::Fixed,
-      7)); // Packed Tag Decl Bits: getTagKind, isCompleteDefinition,
-           // EmbeddedInDeclarator, IsFreeStanding, isCompleteDefinitionRequired
+      9)); // Packed Tag Decl Bits: getTagKind, isCompleteDefinition,
+           // EmbeddedInDeclarator, IsFreeStanding,
+           // isCompleteDefinitionRequired, ExtInfoKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // SourceLocation
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // SourceLocation
-  Abv->Add(BitCodeAbbrevOp(0));                         // ExtInfoKind
   // RecordDecl
   Abv->Add(BitCodeAbbrevOp(
       BitCodeAbbrevOp::Fixed,
@@ -2194,13 +2192,12 @@ void ASTWriter::WriteDeclAbbrevs() {
   // Redeclarable
   Abv->Add(BitCodeAbbrevOp(0));                       // No redeclaration
   // Decl
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
+                           12)); // Packed DeclBits: HasStandaloneLexicalDC,
+                                 // isInvalidDecl, HasAttrs, isImplicit, isUsed,
+                                 // isReferenced, TopLevelDeclInObjCContainer,
+                                 // AccessSpecifier, ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // DeclContext
-  Abv->Add(BitCodeAbbrevOp(0));                       // LexicalDeclContext
-  Abv->Add(BitCodeAbbrevOp(
-      BitCodeAbbrevOp::Fixed,
-      11)); // Packed DeclBits: isInvalidDecl, HasAttrs, isImplicit, isUsed,
-            // isReferenced, TopLevelDeclInObjCContainer, AccessSpecifier,
-            // ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // SubmoduleID
   // NamedDecl
   Abv->Add(BitCodeAbbrevOp(0));                       // NameKind = Identifier
@@ -2221,10 +2218,9 @@ void ASTWriter::WriteDeclAbbrevs() {
   // ParmVarDecl
   Abv->Add(BitCodeAbbrevOp(
       BitCodeAbbrevOp::Fixed,
-      19)); // Packed Parm Var Decl bits: IsObjCMethodParameter, ScopeDepth,
-            // ScopeIndex, KNRPromoted, HasInheritedDefaultArg
-  Abv->Add(BitCodeAbbrevOp(0));                       // ObjCDeclQualifier
-  Abv->Add(BitCodeAbbrevOp(0));                   // HasUninstantiatedDefaultArg
+      27)); // Packed Parm Var Decl bits: IsObjCMethodParameter, ScopeDepth,
+            // ScopeIndex, ObjCDeclQualifier, KNRPromoted,
+            // HasInheritedDefaultArg, HasUninstantiatedDefaultArg
   // Type Source Info
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Array));
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // TypeLoc
@@ -2236,13 +2232,12 @@ void ASTWriter::WriteDeclAbbrevs() {
   // Redeclarable
   Abv->Add(BitCodeAbbrevOp(0));                       // No redeclaration
   // Decl
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
+                           12)); // Packed DeclBits: HasStandaloneLexicalDC,
+                                 // isInvalidDecl, HasAttrs, isImplicit, isUsed,
+                                 // isReferenced, TopLevelDeclInObjCContainer,
+                                 // AccessSpecifier, ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // DeclContext
-  Abv->Add(BitCodeAbbrevOp(0));                       // LexicalDeclContext
-  Abv->Add(BitCodeAbbrevOp(
-      BitCodeAbbrevOp::Fixed,
-      11)); // Packed DeclBits: isInvalidDecl, HasAttrs, isImplicit, isUsed,
-            // isReferenced, TopLevelDeclInObjCContainer, AccessSpecifier,
-            // ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // SubmoduleID
   // NamedDecl
   Abv->Add(BitCodeAbbrevOp(0));                       // NameKind = Identifier
@@ -2262,13 +2257,12 @@ void ASTWriter::WriteDeclAbbrevs() {
   // Redeclarable
   Abv->Add(BitCodeAbbrevOp(0));                       // No redeclaration
   // Decl
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
+                           12)); // Packed DeclBits: HasStandaloneLexicalDC,
+                                 // isInvalidDecl, HasAttrs, isImplicit, isUsed,
+                                 // isReferenced, TopLevelDeclInObjCContainer,
+                                 // AccessSpecifier, ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // DeclContext
-  Abv->Add(BitCodeAbbrevOp(0));                       // LexicalDeclContext
-  Abv->Add(BitCodeAbbrevOp(
-      BitCodeAbbrevOp::Fixed,
-      11)); // Packed DeclBits: isInvalidDecl, HasAttrs, isImplicit, isUsed,
-            // isReferenced, TopLevelDeclInObjCContainer, AccessSpecifier,
-            // ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // SubmoduleID
   // NamedDecl
   Abv->Add(BitCodeAbbrevOp(0));                       // NameKind = Identifier
@@ -2303,13 +2297,12 @@ void ASTWriter::WriteDeclAbbrevs() {
   // FIXME: Implement abbreviation for other template kinds.
   Abv->Add(BitCodeAbbrevOp(FunctionDecl::TK_NonTemplate)); // TemplateKind
   // Decl
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
+                           12)); // Packed DeclBits: HasStandaloneLexicalDC,
+                                 // isInvalidDecl, HasAttrs, isImplicit, isUsed,
+                                 // isReferenced, TopLevelDeclInObjCContainer,
+                                 // AccessSpecifier, ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // DeclContext
-  Abv->Add(BitCodeAbbrevOp(0));                         // LexicalDeclContext
-  Abv->Add(BitCodeAbbrevOp(
-      BitCodeAbbrevOp::Fixed,
-      11)); // Packed DeclBits: isInvalidDecl, HasAttrs, isImplicit, isUsed,
-            // isReferenced, TopLevelDeclInObjCContainer, AccessSpecifier,
-            // ModuleOwnershipKind
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));   // SubmoduleID
   // NamedDecl
   Abv->Add(BitCodeAbbrevOp(DeclarationName::Identifier)); // NameKind
@@ -2346,16 +2339,14 @@ void ASTWriter::WriteDeclAbbrevs() {
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));
   DeclCXXMethodAbbrev = Stream.EmitAbbrev(std::move(Abv));
 
-  unsigned ExprDependenceBits = llvm::BitWidth<ExprDependence>;
   // Abbreviation for EXPR_DECL_REF
   Abv = std::make_shared<BitCodeAbbrev>();
   Abv->Add(BitCodeAbbrevOp(serialization::EXPR_DECL_REF));
   //Stmt
   // Expr
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // Type
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, ExprDependenceBits));
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 3)); //GetValueKind
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 3)); //GetObjectKind
+  // DependenceKind, ValueKind, ObjectKind
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 10));
   //DeclRefExpr
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 1)); //HasQualifier
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 1)); //GetDeclFound
@@ -2374,9 +2365,8 @@ void ASTWriter::WriteDeclAbbrevs() {
   //Stmt
   // Expr
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // Type
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, ExprDependenceBits));
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 3)); //GetValueKind
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 3)); //GetObjectKind
+  // DependenceKind, ValueKind, ObjectKind
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 10));
   //Integer Literal
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // Location
   Abv->Add(BitCodeAbbrevOp(32));                      // Bit Width
@@ -2389,9 +2379,8 @@ void ASTWriter::WriteDeclAbbrevs() {
   //Stmt
   // Expr
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // Type
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, ExprDependenceBits));
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 3)); //GetValueKind
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 3)); //GetObjectKind
+  // DependenceKind, ValueKind, ObjectKind
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 10));
   //Character Literal
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // getValue
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // Location
@@ -2404,9 +2393,8 @@ void ASTWriter::WriteDeclAbbrevs() {
   // Stmt
   // Expr
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // Type
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, ExprDependenceBits));
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 3)); //GetValueKind
-  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 3)); //GetObjectKind
+  // DependenceKind, ValueKind, ObjectKind
+  Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 10));
   // CastExpr
   Abv->Add(BitCodeAbbrevOp(0)); // PathSize
   Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 1)); // HasFPFeatures
diff --git a/clang/lib/Serialization/ASTWriterStmt.cpp b/clang/lib/Serialization/ASTWriterStmt.cpp
index 59be6828fafa..8524484ea8a0 100644
--- a/clang/lib/Serialization/ASTWriterStmt.cpp
+++ b/clang/lib/Serialization/ASTWriterStmt.cpp
@@ -549,9 +549,14 @@ void ASTStmtWriter::VisitCapturedStmt(CapturedStmt *S) {
 void ASTStmtWriter::VisitExpr(Expr *E) {
   VisitStmt(E);
   Record.AddTypeRef(E->getType());
-  Record.push_back(E->getDependence());
-  Record.push_back(E->getValueKind());
-  Record.push_back(E->getObjectKind());
+
+  BitsPacker ExprBits;
+
+  ExprBits.addBits(E->getDependence(), /*BitsWidth=*/5);
+  ExprBits.addBits(E->getValueKind(), /*BitsWidth=*/2);
+  ExprBits.addBits(E->getObjectKind(), /*BitsWidth=*/3);
+
+  Record.push_back(ExprBits);
 }
 
 void ASTStmtWriter::VisitConstantExpr(ConstantExpr *E) {
@@ -866,14 +871,20 @@ void ASTStmtWriter::VisitOMPIteratorExpr(OMPIteratorExpr *E) {
 
 void ASTStmtWriter::VisitCallExpr(CallExpr *E) {
   VisitExpr(E);
-  Record.push_back(E->getNumArgs());
-  Record.push_back(E->hasStoredFPFeatures());
+
+  BitsPacker CallExprBits;
+  // 16 bits should be sufficient to store the number args;
+  CallExprBits.addBits(E->getNumArgs(), /*BitsWidth=*/16);
+  CallExprBits.addBit(E->hasStoredFPFeatures());
+  CallExprBits.addBit(static_cast<bool>(E->getADLCallKind()));
+  Record.push_back(CallExprBits);
+
   Record.AddSourceLocation(E->getRParenLoc());
   Record.AddStmt(E->getCallee());
   for (CallExpr::arg_iterator Arg = E->arg_begin(), ArgEnd = E->arg_end();
        Arg != ArgEnd; ++Arg)
     Record.AddStmt(*Arg);
-  Record.push_back(static_cast<unsigned>(E->getADLCallKind()));
+
   if (E->hasStoredFPFeatures())
     Record.push_back(E->getFPFeatures().getAsOpaqueInt());
   Code = serialization::EXPR_CALL;
@@ -1938,14 +1949,19 @@ ASTStmtWriter::VisitCXXUnresolvedConstructExpr(CXXUnresolvedConstructExpr *E) {
 void ASTStmtWriter::VisitOverloadExpr(OverloadExpr *E) {
   VisitExpr(E);
 
-  Record.push_back(E->getNumDecls());
-  Record.push_back(E->hasTemplateKWAndArgsInfo());
+  BitsPacker OverloadExprBits;
+  // 14 Bits should enough to store the number of decls.
+  OverloadExprBits.addBits(E->getNumDecls(), /*BitWidth=*/14);
+  OverloadExprBits.addBit(E->hasTemplateKWAndArgsInfo());
   if (E->hasTemplateKWAndArgsInfo()) {
     const ASTTemplateKWAndArgsInfo &ArgInfo =
         *E->getTrailingASTTemplateKWAndArgsInfo();
-    Record.push_back(ArgInfo.NumTemplateArgs);
+    // 14 Bits should enough to store the number of template args.
+    OverloadExprBits.addBits(ArgInfo.NumTemplateArgs, /*BitWidth=*/14);
+    Record.push_back(OverloadExprBits);
     AddTemplateKWAndArgsInfo(ArgInfo, E->getTrailingTemplateArgumentLoc());
-  }
+  } else
+    Record.push_back(OverloadExprBits);
 
   for (OverloadExpr::decls_iterator OvI = E->decls_begin(),
                                     OvE = E->decls_end();
diff --git a/clang/test/Modules/decl-params-determinisim.m b/clang/test/Modules/decl-params-determinisim.m
index 351403d9af94..9cf37ac4334c 100644
--- a/clang/test/Modules/decl-params-determinisim.m
+++ b/clang/test/Modules/decl-params-determinisim.m
@@ -28,23 +28,23 @@
 
 // CHECK: <TYPE_FUNCTION_PROTO
 // CHECK-NEXT: <DECL_PARM_VAR
-// CHECK-SAME: op6=2
+// CHECK-SAME: op5=2
 // CHECK-NEXT: <DECL_PARM_VAR
-// CHECK-SAME: op6=3
+// CHECK-SAME: op5=3
 // CHECK-NEXT: <DECL_PARM_VAR
-// CHECK-SAME: op6=4
+// CHECK-SAME: op5=4
 // CHECK-NEXT: <DECL_PARM_VAR
-// CHECK-SAME: op6=5
+// CHECK-SAME: op5=5
 
 /// Decl records start at 43
 // CHECK: <DECL_RECORD
-// CHECK-SAME: op6=43
+// CHECK-SAME: op5=43
 // CHECK-NEXT: <DECL_RECORD
-// CHECK-SAME: op6=44
+// CHECK-SAME: op5=44
 // CHECK-NEXT: <DECL_RECORD
-// CHECK-SAME: op6=45
+// CHECK-SAME: op5=45
 // CHECK-NEXT: <DECL_RECORD
-// CHECK-SAME: op6=46
+// CHECK-SAME: op5=46
 
 //--- headers/a.h
 void f(struct A0 *a0,
-- 
GitLab


From a3a8acd9a60b762ba0fb1194f7c26d5322b21d03 Mon Sep 17 00:00:00 2001
From: Tobias Hieta <tobias@hieta.se>
Date: Mon, 11 Dec 2023 09:49:30 +0100
Subject: [PATCH 086/349] [NFC] Missing argument for the PR issue number in the
 code format helper

---
 llvm/utils/git/code-format-helper.py | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/utils/git/code-format-helper.py b/llvm/utils/git/code-format-helper.py
index aa78bc4f0ba9..697a27ab82a7 100755
--- a/llvm/utils/git/code-format-helper.py
+++ b/llvm/utils/git/code-format-helper.py
@@ -43,6 +43,7 @@ class FormatArgs:
     changed_files: List[str] = []
     token: str = None
     verbose: bool = True
+    issue_number: int = 0
 
     def __init__(self, args: argparse.Namespace = None) -> None:
         if not args is None:
@@ -51,6 +52,7 @@ class FormatArgs:
             self.repo = args.repo
             self.token = args.token
             self.changed_files = args.changed_files
+            self.issue_number = args.issue_number
 
 
 class FormatHelper:
-- 
GitLab


From 99430c589fda65817119aa6b83fc24813fa78e25 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad@amd.com>
Date: Mon, 11 Dec 2023 09:02:00 +0000
Subject: [PATCH 087/349] [AMDGPU] Update sendmsg types for GFX12 (#74888)

---
 llvm/lib/Target/AMDGPU/SIDefines.h            |   5 +-
 .../Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp    |   7 +-
 llvm/test/MC/AMDGPU/gfx12_asm_sop1.s          |   3 +
 llvm/test/MC/AMDGPU/sopp-err.s                | 107 ++++++++++--------
 .../Disassembler/AMDGPU/gfx12_dasm_sop1.txt   |   3 +
 5 files changed, 71 insertions(+), 54 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h
index 47dc59e77dc4..29397e109706 100644
--- a/llvm/lib/Target/AMDGPU/SIDefines.h
+++ b/llvm/lib/Target/AMDGPU/SIDefines.h
@@ -413,8 +413,8 @@ enum Id { // Message ID, width(4) [3:0].
   ID_DEALLOC_VGPRS_GFX11Plus = 3, // reused in GFX11
 
   ID_SAVEWAVE = 4,           // added in GFX8, removed in GFX11
-  ID_STALL_WAVE_GEN = 5,     // added in GFX9
-  ID_HALT_WAVES = 6,         // added in GFX9
+  ID_STALL_WAVE_GEN = 5,     // added in GFX9, removed in GFX12
+  ID_HALT_WAVES = 6,         // added in GFX9, removed in GFX12
   ID_ORDERED_PS_DONE = 7,    // added in GFX9, removed in GFX11
   ID_EARLY_PRIM_DEALLOC = 8, // added in GFX9, removed in GFX10
   ID_GS_ALLOC_REQ = 9,       // added in GFX9
@@ -428,6 +428,7 @@ enum Id { // Message ID, width(4) [3:0].
   ID_RTN_GET_REALTIME = 131,
   ID_RTN_SAVE_WAVE = 132,
   ID_RTN_GET_TBA = 133,
+  ID_RTN_GET_SE_AID_ID = 134,
 
   ID_MASK_PreGFX11_ = 0xF,
   ID_MASK_GFX11Plus_ = 0xFF
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
index 403efd6ffed3..23434d2de0fc 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
@@ -36,14 +36,15 @@ namespace SendMsg {
 
 // Disable lint checking for this block since it makes the table unreadable.
 // NOLINTBEGIN
+// clang-format off
 const CustomOperand<const MCSubtargetInfo &> Msg[] = {
   {{""}},
   {{"MSG_INTERRUPT"},           ID_INTERRUPT},
   {{"MSG_GS"},                  ID_GS_PreGFX11,             isNotGFX11Plus},
   {{"MSG_GS_DONE"},             ID_GS_DONE_PreGFX11,        isNotGFX11Plus},
   {{"MSG_SAVEWAVE"},            ID_SAVEWAVE,                isGFX8_GFX9_GFX10},
-  {{"MSG_STALL_WAVE_GEN"},      ID_STALL_WAVE_GEN,          isGFX9Plus},
-  {{"MSG_HALT_WAVES"},          ID_HALT_WAVES,              isGFX9Plus},
+  {{"MSG_STALL_WAVE_GEN"},      ID_STALL_WAVE_GEN,          isGFX9_GFX10_GFX11},
+  {{"MSG_HALT_WAVES"},          ID_HALT_WAVES,              isGFX9_GFX10_GFX11},
   {{"MSG_ORDERED_PS_DONE"},     ID_ORDERED_PS_DONE,         isGFX9_GFX10},
   {{"MSG_EARLY_PRIM_DEALLOC"},  ID_EARLY_PRIM_DEALLOC,      isGFX9_GFX10},
   {{"MSG_GS_ALLOC_REQ"},        ID_GS_ALLOC_REQ,            isGFX9Plus},
@@ -59,7 +60,9 @@ const CustomOperand<const MCSubtargetInfo &> Msg[] = {
   {{"MSG_RTN_GET_REALTIME"},    ID_RTN_GET_REALTIME,        isGFX11Plus},
   {{"MSG_RTN_SAVE_WAVE"},       ID_RTN_SAVE_WAVE,           isGFX11Plus},
   {{"MSG_RTN_GET_TBA"},         ID_RTN_GET_TBA,             isGFX11Plus},
+  {{"MSG_RTN_GET_SE_AID_ID"},   ID_RTN_GET_SE_AID_ID,       isGFX12Plus},
 };
+// clang-format on
 // NOLINTEND
 
 const int MSG_SIZE = static_cast<int>(
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_sop1.s b/llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
index 494b8399a26f..db166e8ffc10 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
@@ -3648,6 +3648,9 @@ s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_SAVE_WAVE)
 s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_TBA)
 // GFX12: encoding: [0x85,0x4c,0x80,0xbe]
 
+s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_SE_AID_ID)
+// GFX12: encoding: [0x86,0x4c,0x80,0xbe]
+
 s_ctz_i32_b32 s5, s1
 // GFX12: encoding: [0x01,0x08,0x85,0xbe]
 
diff --git a/llvm/test/MC/AMDGPU/sopp-err.s b/llvm/test/MC/AMDGPU/sopp-err.s
index c7f28faa5576..bd044cb74340 100644
--- a/llvm/test/MC/AMDGPU/sopp-err.s
+++ b/llvm/test/MC/AMDGPU/sopp-err.s
@@ -2,7 +2,8 @@
 // RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck --check-prefixes=GCN,PREGFX11,SICI,SICIVI --implicit-check-not=error: %s
 // RUN: not llvm-mc -triple=amdgcn -mcpu=fiji %s 2>&1 | FileCheck --check-prefixes=GCN,PREGFX11,VI,SICIVI --implicit-check-not=error: %s
 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck --check-prefixes=GCN,PREGFX11,GFX10 --implicit-check-not=error: %s
-// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck --check-prefixes=GCN,GFX11 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck --check-prefixes=GCN,GFX11PLUS,GFX11 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 %s 2>&1 | FileCheck --check-prefixes=GCN,GFX11PLUS,GFX12 --implicit-check-not=error: %s
 
 //===----------------------------------------------------------------------===//
 // sendmsg
@@ -22,30 +23,30 @@ s_sendmsg sendmsg(MSG_INTERRUPT, 0, 0)
 
 s_sendmsg sendmsg(MSG_GS)
 // PREGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: missing message operation
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
 
 s_sendmsg sendmsg(MSG_GS, GS_OP_NOP)
 // PREGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operation id
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
 
 s_sendmsg sendmsg(MSG_GS, SYSMSG_OP_ECC_ERR_INTERRUPT)
 // GCN: :[[@LINE-1]]:{{[0-9]+}}: error: expected an operation name or an absolute expression
 
 s_sendmsg sendmsg(MSG_GS, 0)
 // PREGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operation id
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
 
 s_sendmsg sendmsg(MSG_GS, -1)
 // PREGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operation id
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
 
 s_sendmsg sendmsg(MSG_GS, 4)
 // PREGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operation id
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
 
 s_sendmsg sendmsg(MSG_GS, 8)
 // PREGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operation id
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
 
 s_sendmsg sendmsg(15, -1)
 // GCN: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operation id
@@ -67,7 +68,7 @@ s_sendmsg sendmsg(MSG_GS, 1 -)
 
 s_sendmsg sendmsg(MSG_GS, GS_OP_CUT, 4)
 // PREGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid message stream id
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
 
 s_sendmsg sendmsg(MSG_GS, GS_OP_CUT, 1 -)
 // GCN: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression
@@ -86,11 +87,11 @@ s_sendmsg sendmsg(2, 2, 0, 0)
 
 s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP, 0)
 // PREGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: message operation does not support streams
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
 
 s_sendmsg sendmsg(MSG_GS_DONE, 0, 0)
 // PREGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: message operation does not support streams
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
 
 s_sendmsg sendmsg(MSG_HS_TESSFACTOR)
 // SICI: :[[@LINE-1]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
@@ -104,25 +105,27 @@ s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 
 s_sendmsg sendmsg(MSG_SAVEWAVE)
 // SICI: :[[@LINE-1]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
 
 s_sendmsg sendmsg(MSG_STALL_WAVE_GEN)
 // SICI: :[[@LINE-1]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
 // VI: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
+// GFX12: :[[@LINE-3]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
 
 s_sendmsg sendmsg(MSG_HALT_WAVES)
 // SICI: :[[@LINE-1]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
 // VI: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
+// GFX12: :[[@LINE-3]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
 
 s_sendmsg sendmsg(MSG_ORDERED_PS_DONE)
 // SICI: :[[@LINE-1]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
 // VI: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
-// GFX11: :[[@LINE-3]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
+// GFX11PLUS: :[[@LINE-3]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
 
 s_sendmsg sendmsg(MSG_EARLY_PRIM_DEALLOC)
 // SICI: :[[@LINE-1]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
 // VI: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
-// GFX11: :[[@LINE-3]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
+// GFX11PLUS: :[[@LINE-3]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
 
 s_sendmsg sendmsg(MSG_GS_ALLOC_REQ)
 // VI: :[[@LINE-1]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
@@ -132,17 +135,17 @@ s_sendmsg sendmsg(MSG_GS_ALLOC_REQ, 0)
 // VI: :[[@LINE-1]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
 // SICI: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
 // GFX10: :[[@LINE-3]]:{{[0-9]+}}: error: message does not support operations
-// GFX11: :[[@LINE-4]]:{{[0-9]+}}: error: message does not support operations
+// GFX11PLUS: :[[@LINE-4]]:{{[0-9]+}}: error: message does not support operations
 
 s_sendmsg sendmsg(MSG_GET_DOORBELL)
 // SICI: :[[@LINE-1]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
 // VI: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
-// GFX11: :[[@LINE-3]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
+// GFX11PLUS: :[[@LINE-3]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
 
 s_sendmsg sendmsg(MSG_GET_DDID)
 // SICI: :[[@LINE-1]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
 // VI: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
-// GFX11: :[[@LINE-3]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
+// GFX11PLUS: :[[@LINE-3]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
 
 s_sendmsg sendmsg(MSG_RTN_GET_DOORBELL)
 // SICI: :[[@LINE-1]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
@@ -174,6 +177,10 @@ s_sendmsg sendmsg(MSG_RTN_GET_TBA)
 // VI: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
 // GFX10: :[[@LINE-3]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
 
+s_sendmsg sendmsg(MSG_RTN_GET_SE_AID_ID)
+// PREGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
+// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU
+
 s_sendmsg sendmsg(-1)
 // GCN: :[[@LINE-1]]:{{[0-9]+}}: error: invalid message id
 
@@ -252,12 +259,12 @@ s_waitcnt vmcnt(0
 
 s_waitcnt_depctr 65536
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr -32769
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_hold_cnt(0)
@@ -266,162 +273,162 @@ s_waitcnt_depctr depctr_hold_cnt(0)
 
 s_waitcnt_depctr depctr_sa_sdst(-1)
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_sa_sdst
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: invalid value for depctr_sa_sdst
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: invalid value for depctr_sa_sdst
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_va_vdst(-1)
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_va_vdst
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: invalid value for depctr_va_vdst
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: invalid value for depctr_va_vdst
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_va_sdst(-1)
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_va_sdst
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: invalid value for depctr_va_sdst
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: invalid value for depctr_va_sdst
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_va_ssrc(-1)
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_va_ssrc
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: invalid value for depctr_va_ssrc
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: invalid value for depctr_va_ssrc
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_va_vcc(-1)
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_va_vcc
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: invalid value for depctr_va_vcc
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: invalid value for depctr_va_vcc
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_vm_vsrc(-1)
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_vm_vsrc
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: invalid value for depctr_vm_vsrc
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: invalid value for depctr_vm_vsrc
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_sa_sdst(2)
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_sa_sdst
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: invalid value for depctr_sa_sdst
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: invalid value for depctr_sa_sdst
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_va_vdst(16)
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_va_vdst
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: invalid value for depctr_va_vdst
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: invalid value for depctr_va_vdst
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_va_sdst(8)
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_va_sdst
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: invalid value for depctr_va_sdst
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: invalid value for depctr_va_sdst
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_va_ssrc(2)
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_va_ssrc
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: invalid value for depctr_va_ssrc
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: invalid value for depctr_va_ssrc
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_va_vcc(2)
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_va_vcc
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: invalid value for depctr_va_vcc
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: invalid value for depctr_va_vcc
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_vm_vsrc(8)
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_vm_vsrc
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: invalid value for depctr_vm_vsrc
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: invalid value for depctr_vm_vsrc
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_vm_(8)
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid counter name depctr_vm_
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: invalid counter name depctr_vm_
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: invalid counter name depctr_vm_
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_sa_sdst(0) depctr_sa_sdst(0)
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: duplicate counter name depctr_sa_sdst
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: duplicate counter name depctr_sa_sdst
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: duplicate counter name depctr_sa_sdst
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_va_vdst(0) depctr_va_vdst(0)
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: duplicate counter name depctr_va_vdst
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: duplicate counter name depctr_va_vdst
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: duplicate counter name depctr_va_vdst
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_va_sdst(0) depctr_va_sdst(0)
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: duplicate counter name depctr_va_sdst
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: duplicate counter name depctr_va_sdst
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: duplicate counter name depctr_va_sdst
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_va_ssrc(0) depctr_va_ssrc(0)
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: duplicate counter name depctr_va_ssrc
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: duplicate counter name depctr_va_ssrc
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: duplicate counter name depctr_va_ssrc
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_va_vcc(0) depctr_va_vcc(0)
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: duplicate counter name depctr_va_vcc
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: duplicate counter name depctr_va_vcc
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: duplicate counter name depctr_va_vcc
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_vm_vsrc(0) depctr_vm_vsrc(0)
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: duplicate counter name depctr_vm_vsrc
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: duplicate counter name depctr_vm_vsrc
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: duplicate counter name depctr_vm_vsrc
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_sa_sdst(0) depctr_va_sdst(0) depctr_sa_sdst(0)
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: duplicate counter name depctr_sa_sdst
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: duplicate counter name depctr_sa_sdst
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: duplicate counter name depctr_sa_sdst
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_va_ssrc(0) depctr_va_sdst(0) depctr_va_ssrc(0)
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: duplicate counter name depctr_va_ssrc
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: duplicate counter name depctr_va_ssrc
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: duplicate counter name depctr_va_ssrc
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_va_vcc(0) depctr_va_vcc(0) depctr_va_sdst(0)
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: duplicate counter name depctr_va_vcc
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: duplicate counter name depctr_va_vcc
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: duplicate counter name depctr_va_vcc
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_vm_vsrc(0) depctr_vm_vsrc(0) depctr_va_sdst(0)
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: duplicate counter name depctr_vm_vsrc
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: duplicate counter name depctr_vm_vsrc
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: duplicate counter name depctr_vm_vsrc
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_va_sdst(0) depctr_vm_vsrc 0)
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: expected a left parenthesis
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: expected a left parenthesis
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: expected a left parenthesis
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_va_sdst(0) 0depctr_vm_vsrc(0)
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: expected a counter name
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: expected a counter name
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: expected a counter name
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_va_sdst(0) depctr_vm_vsrc(x)
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: expected absolute expression
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: expected absolute expression
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: expected absolute expression
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_va_sdst(0) depctr_vm_vsrc(0; & depctr_va_sdst(0)
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing parenthesis
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: expected a closing parenthesis
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: expected a closing parenthesis
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_vm_vsrc 0) depctr_vm_vsrc(0) depctr_va_sdst(0)
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: expected absolute expression
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: expected absolute expression
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: expected absolute expression
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_vm_vsrc(0) ,
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: expected a counter name
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: expected a counter name
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: expected a counter name
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_vm_vsrc(0) , &
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: expected a counter name
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: expected a counter name
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: expected a counter name
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_vm_vsrc(0) &
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: expected a counter name
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: expected a counter name
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: expected a counter name
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 s_waitcnt_depctr depctr_vm_vsrc(0) & &
 // GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: expected a counter name
-// GFX11: :[[@LINE-2]]:{{[0-9]+}}: error: expected a counter name
+// GFX11PLUS: :[[@LINE-2]]:{{[0-9]+}}: error: expected a counter name
 // SICIVI: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 //===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
index 7029f090faa4..c061462339b6 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
@@ -3219,6 +3219,9 @@
 # GFX12: s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_TBA) ; encoding: [0x85,0x4c,0x80,0xbe]
 0x85,0x4c,0x80,0xbe
 
+# GFX12: s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_SE_AID_ID) ; encoding: [0x86,0x4c,0x80,0xbe]
+0x86,0x4c,0x80,0xbe
+
 # GFX12: s_setpc_b64 s[0:1]                      ; encoding: [0x00,0x48,0x80,0xbe]
 0x00,0x48,0x80,0xbe
 
-- 
GitLab


From 75193b192ad92e69236930dc35c262786a95f472 Mon Sep 17 00:00:00 2001
From: Yingchi Long <i@lyc.dev>
Date: Mon, 11 Dec 2023 17:10:39 +0800
Subject: [PATCH 088/349] [BPF] use target triple for pattern predicates
 (#74998)

This is used for eliminate uses of "CurDAG", which is SelectionDAG-spec,
and not compatible with GIsel algorithms.

(NFC)
---
 llvm/lib/Target/BPF/BPFInstrInfo.td  | 4 ++--
 llvm/lib/Target/BPF/BPFSubtarget.cpp | 4 +++-
 llvm/lib/Target/BPF/BPFSubtarget.h   | 4 ++++
 3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.td b/llvm/lib/Target/BPF/BPFInstrInfo.td
index 5972c9d49c51..7d443a344901 100644
--- a/llvm/lib/Target/BPF/BPFInstrInfo.td
+++ b/llvm/lib/Target/BPF/BPFInstrInfo.td
@@ -49,8 +49,8 @@ def BPFWrapper      : SDNode<"BPFISD::Wrapper", SDT_BPFWrapper>;
 def BPFmemcpy       : SDNode<"BPFISD::MEMCPY", SDT_BPFMEMCPY,
                              [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
                               SDNPMayStore, SDNPMayLoad]>;
-def BPFIsLittleEndian : Predicate<"CurDAG->getDataLayout().isLittleEndian()">;
-def BPFIsBigEndian    : Predicate<"!CurDAG->getDataLayout().isLittleEndian()">;
+def BPFIsLittleEndian : Predicate<"Subtarget->isLittleEndian()">;
+def BPFIsBigEndian    : Predicate<"!Subtarget->isLittleEndian()">;
 def BPFHasALU32 : Predicate<"Subtarget->getHasAlu32()">;
 def BPFNoALU32 : Predicate<"!Subtarget->getHasAlu32()">;
 def BPFHasLdsx : Predicate<"Subtarget->hasLdsx()">;
diff --git a/llvm/lib/Target/BPF/BPFSubtarget.cpp b/llvm/lib/Target/BPF/BPFSubtarget.cpp
index ce02c831828e..5e79142ea9e1 100644
--- a/llvm/lib/Target/BPF/BPFSubtarget.cpp
+++ b/llvm/lib/Target/BPF/BPFSubtarget.cpp
@@ -93,4 +93,6 @@ BPFSubtarget::BPFSubtarget(const Triple &TT, const std::string &CPU,
                            const std::string &FS, const TargetMachine &TM)
     : BPFGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
       FrameLowering(initializeSubtargetDependencies(CPU, FS)),
-      TLInfo(TM, *this) {}
+      TLInfo(TM, *this) {
+  IsLittleEndian = TT.isLittleEndian();
+}
diff --git a/llvm/lib/Target/BPF/BPFSubtarget.h b/llvm/lib/Target/BPF/BPFSubtarget.h
index 6e81daa4d955..a55ae618f4d1 100644
--- a/llvm/lib/Target/BPF/BPFSubtarget.h
+++ b/llvm/lib/Target/BPF/BPFSubtarget.h
@@ -43,6 +43,8 @@ protected:
   // unused
   bool isDummyMode;
 
+  bool IsLittleEndian;
+
   // whether the cpu supports jmp ext
   bool HasJmpExt;
 
@@ -81,6 +83,8 @@ public:
   bool hasGotol() const { return HasGotol; }
   bool hasStoreImm() const { return HasStoreImm; }
 
+  bool isLittleEndian() const { return IsLittleEndian; }
+
   const BPFInstrInfo *getInstrInfo() const override { return &InstrInfo; }
   const BPFFrameLowering *getFrameLowering() const override {
     return &FrameLowering;
-- 
GitLab


From 13c648f6bda9a4b6c9cd1ee5f0c21c72acec1320 Mon Sep 17 00:00:00 2001
From: Victor Perez <victor.perez@codeplay.com>
Date: Mon, 11 Dec 2023 10:36:03 +0100
Subject: [PATCH 089/349] [MLIR][IntegerRangeAnalysis] Avoid crash reached when
 loop bound is uninitialized (#74832)

If the loop bound is not initialized, the analysis crashed, as it only checked for nullity. Also checking for initialization fixes the issue.

Signed-off-by: Victor Perez <victor.perez@codeplay.com>
Co-authored-by: Tsang, Whitney <whitney.tsang@intel.com>
---
 .../DataFlow/IntegerRangeAnalysis.cpp         |  2 +-
 .../Dialect/Arith/int-range-interface.mlir    | 26 +++++++++++++++++++
 .../lib/Transforms/TestIntRangeInference.cpp  |  2 ++
 3 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/mlir/lib/Analysis/DataFlow/IntegerRangeAnalysis.cpp b/mlir/lib/Analysis/DataFlow/IntegerRangeAnalysis.cpp
index 39b3a0996396..a82c30717e27 100644
--- a/mlir/lib/Analysis/DataFlow/IntegerRangeAnalysis.cpp
+++ b/mlir/lib/Analysis/DataFlow/IntegerRangeAnalysis.cpp
@@ -180,7 +180,7 @@ void IntegerRangeAnalysis::visitNonControlFlowArguments(
       } else if (auto value = llvm::dyn_cast_if_present<Value>(*loopBound)) {
         const IntegerValueRangeLattice *lattice =
             getLatticeElementFor(op, value);
-        if (lattice != nullptr)
+        if (lattice != nullptr && !lattice->getValue().isUninitialized())
           return getUpper ? lattice->getValue().getValue().smax()
                           : lattice->getValue().getValue().smin();
       }
diff --git a/mlir/test/Dialect/Arith/int-range-interface.mlir b/mlir/test/Dialect/Arith/int-range-interface.mlir
index 4c5f4095225d..02a9827d19d8 100644
--- a/mlir/test/Dialect/Arith/int-range-interface.mlir
+++ b/mlir/test/Dialect/Arith/int-range-interface.mlir
@@ -730,3 +730,29 @@ func.func @extui_uses_unsigned(%arg0 : i32) -> i1 {
     %4 = arith.andi %2, %3 : i1
     func.return %4 : i1
 }
+
+/// Catch a bug that caused a crash in getLoopBoundFromFold when
+/// SparseConstantPropagation is loaded in the solver.
+
+// CHECK-LABEL:   func.func @caller(
+// CHECK-SAME:                      %[[VAL_0:.*]]: memref<?xindex, 4>) {
+// CHECK:           call @callee(%[[VAL_0]]) : (memref<?xindex, 4>) -> ()
+// CHECK:           return
+// CHECK:         }
+func.func @caller(%arg0: memref<?xindex, 4>) {
+  call @callee(%arg0) : (memref<?xindex, 4>) -> ()
+  return
+}
+
+// CHECK-LABEL:   func.func private @callee(
+// CHECK-SAME:                              %[[VAL_0:.*]]: memref<?xindex, 4>) {
+// CHECK:           return
+// CHECK:         }
+func.func private @callee(%arg0: memref<?xindex, 4>) {
+  %c1 = arith.constant 1 : index
+  %c0 = arith.constant 0 : index
+  %0 = affine.load %arg0[0] : memref<?xindex, 4>
+  scf.for %arg1 = %c0 to %0 step %c1 {
+  }
+  return
+}
diff --git a/mlir/test/lib/Transforms/TestIntRangeInference.cpp b/mlir/test/lib/Transforms/TestIntRangeInference.cpp
index d1978b6099f0..2f6dd5b8095d 100644
--- a/mlir/test/lib/Transforms/TestIntRangeInference.cpp
+++ b/mlir/test/lib/Transforms/TestIntRangeInference.cpp
@@ -9,6 +9,7 @@
 // functionality has been integrated into SCCP.
 //===----------------------------------------------------------------------===//
 
+#include "mlir/Analysis/DataFlow/ConstantPropagationAnalysis.h"
 #include "mlir/Analysis/DataFlow/DeadCodeAnalysis.h"
 #include "mlir/Analysis/DataFlow/IntegerRangeAnalysis.h"
 #include "mlir/Interfaces/SideEffectInterfaces.h"
@@ -107,6 +108,7 @@ struct TestIntRangeInference
     Operation *op = getOperation();
     DataFlowSolver solver;
     solver.load<DeadCodeAnalysis>();
+    solver.load<SparseConstantPropagation>();
     solver.load<IntegerRangeAnalysis>();
     if (failed(solver.initializeAndRun(op)))
       return signalPassFailure();
-- 
GitLab


From ea2e83af55e76540d69f9efcc341d321b4c0fd06 Mon Sep 17 00:00:00 2001
From: Adrian Kuegel <akuegel@google.com>
Date: Mon, 11 Dec 2023 09:43:08 +0000
Subject: [PATCH 090/349] [mlir][Python] Apply ClangTidy findings.

move constructors should be marked noexcept
---
 mlir/lib/Bindings/Python/ExecutionEngineModule.cpp | 2 +-
 mlir/lib/Bindings/Python/IRInterfaces.cpp          | 2 +-
 mlir/lib/Bindings/Python/IRModule.h                | 6 ++++--
 mlir/lib/Bindings/Python/Pass.cpp                  | 3 ++-
 4 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/mlir/lib/Bindings/Python/ExecutionEngineModule.cpp b/mlir/lib/Bindings/Python/ExecutionEngineModule.cpp
index 3f834259622f..b3df30583fc9 100644
--- a/mlir/lib/Bindings/Python/ExecutionEngineModule.cpp
+++ b/mlir/lib/Bindings/Python/ExecutionEngineModule.cpp
@@ -20,7 +20,7 @@ class PyExecutionEngine {
 public:
   PyExecutionEngine(MlirExecutionEngine executionEngine)
       : executionEngine(executionEngine) {}
-  PyExecutionEngine(PyExecutionEngine &&other)
+  PyExecutionEngine(PyExecutionEngine &&other) noexcept
       : executionEngine(other.executionEngine) {
     other.executionEngine.ptr = nullptr;
   }
diff --git a/mlir/lib/Bindings/Python/IRInterfaces.cpp b/mlir/lib/Bindings/Python/IRInterfaces.cpp
index c3aac0b092bc..54cfa56066eb 100644
--- a/mlir/lib/Bindings/Python/IRInterfaces.cpp
+++ b/mlir/lib/Bindings/Python/IRInterfaces.cpp
@@ -326,7 +326,7 @@ public:
       : shape(std::move(shape)), elementType(elementType), attribute(attribute),
         ranked(true) {}
   PyShapedTypeComponents(PyShapedTypeComponents &) = delete;
-  PyShapedTypeComponents(PyShapedTypeComponents &&other)
+  PyShapedTypeComponents(PyShapedTypeComponents &&other) noexcept
       : shape(other.shape), elementType(other.elementType),
         attribute(other.attribute), ranked(other.ranked) {}
 
diff --git a/mlir/lib/Bindings/Python/IRModule.h b/mlir/lib/Bindings/Python/IRModule.h
index d99b87d19bbe..79b7e0c96188 100644
--- a/mlir/lib/Bindings/Python/IRModule.h
+++ b/mlir/lib/Bindings/Python/IRModule.h
@@ -4,6 +4,7 @@
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //===----------------------------------------------------------------------===//
 
 #ifndef MLIR_BINDINGS_PYTHON_IRMODULES_H
@@ -53,7 +54,7 @@ public:
            "cannot construct PyObjectRef with null referrent");
     assert(this->object && "cannot construct PyObjectRef with null object");
   }
-  PyObjectRef(PyObjectRef &&other)
+  PyObjectRef(PyObjectRef &&other) noexcept
       : referrent(other.referrent), object(std::move(other.object)) {
     other.referrent = nullptr;
     assert(!other.object);
@@ -484,7 +485,8 @@ public:
       mlirDialectRegistryDestroy(registry);
   }
   PyDialectRegistry(PyDialectRegistry &) = delete;
-  PyDialectRegistry(PyDialectRegistry &&other) : registry(other.registry) {
+  PyDialectRegistry(PyDialectRegistry &&other) noexcept
+      : registry(other.registry) {
     other.registry = {nullptr};
   }
 
diff --git a/mlir/lib/Bindings/Python/Pass.cpp b/mlir/lib/Bindings/Python/Pass.cpp
index 588a8e25414c..a68421b61641 100644
--- a/mlir/lib/Bindings/Python/Pass.cpp
+++ b/mlir/lib/Bindings/Python/Pass.cpp
@@ -23,7 +23,8 @@ namespace {
 class PyPassManager {
 public:
   PyPassManager(MlirPassManager passManager) : passManager(passManager) {}
-  PyPassManager(PyPassManager &&other) : passManager(other.passManager) {
+  PyPassManager(PyPassManager &&other) noexcept
+      : passManager(other.passManager) {
     other.passManager.ptr = nullptr;
   }
   ~PyPassManager() {
-- 
GitLab


From 276a024b497e025aa7484ae9aa1513675ca03dda Mon Sep 17 00:00:00 2001
From: Dominik Adamski <dominik.adamski@amd.com>
Date: Mon, 11 Dec 2023 10:45:21 +0100
Subject: [PATCH 091/349] [NFC][AMDGPU] Unify AMDGPU address space enum
 (#73944)

Types of AMDGPU address space were defined not only in Clang-specific class
but also in LLVM header.

If we unify the AMD GPU address space enumeration, then we can reuse it in
Clang, Flang and LLVM.
---
 clang/lib/Basic/Targets/AMDGPU.cpp          | 80 ++++++++++----------
 clang/lib/Basic/Targets/AMDGPU.h            | 19 ++---
 flang/lib/Frontend/FrontendActions.cpp      | 11 +--
 llvm/include/llvm/Support/AMDGPUAddrSpace.h | 83 +++++++++++++++++++++
 llvm/lib/Target/AMDGPU/AMDGPU.h             | 67 +----------------
 5 files changed, 134 insertions(+), 126 deletions(-)
 create mode 100644 llvm/include/llvm/Support/AMDGPUAddrSpace.h

diff --git a/clang/lib/Basic/Targets/AMDGPU.cpp b/clang/lib/Basic/Targets/AMDGPU.cpp
index 409ae32ab424..719fc51bfc28 100644
--- a/clang/lib/Basic/Targets/AMDGPU.cpp
+++ b/clang/lib/Basic/Targets/AMDGPU.cpp
@@ -37,50 +37,50 @@ static const char *const DataLayoutStringAMDGCN =
     "-ni:7:8";
 
 const LangASMap AMDGPUTargetInfo::AMDGPUDefIsGenMap = {
-    Generic,  // Default
-    Global,   // opencl_global
-    Local,    // opencl_local
-    Constant, // opencl_constant
-    Private,  // opencl_private
-    Generic,  // opencl_generic
-    Global,   // opencl_global_device
-    Global,   // opencl_global_host
-    Global,   // cuda_device
-    Constant, // cuda_constant
-    Local,    // cuda_shared
-    Global,   // sycl_global
-    Global,   // sycl_global_device
-    Global,   // sycl_global_host
-    Local,    // sycl_local
-    Private,  // sycl_private
-    Generic,  // ptr32_sptr
-    Generic,  // ptr32_uptr
-    Generic,  // ptr64
-    Generic,  // hlsl_groupshared
+    llvm::AMDGPUAS::FLAT_ADDRESS,     // Default
+    llvm::AMDGPUAS::GLOBAL_ADDRESS,   // opencl_global
+    llvm::AMDGPUAS::LOCAL_ADDRESS,    // opencl_local
+    llvm::AMDGPUAS::CONSTANT_ADDRESS, // opencl_constant
+    llvm::AMDGPUAS::PRIVATE_ADDRESS,  // opencl_private
+    llvm::AMDGPUAS::FLAT_ADDRESS,     // opencl_generic
+    llvm::AMDGPUAS::GLOBAL_ADDRESS,   // opencl_global_device
+    llvm::AMDGPUAS::GLOBAL_ADDRESS,   // opencl_global_host
+    llvm::AMDGPUAS::GLOBAL_ADDRESS,   // cuda_device
+    llvm::AMDGPUAS::CONSTANT_ADDRESS, // cuda_constant
+    llvm::AMDGPUAS::LOCAL_ADDRESS,    // cuda_shared
+    llvm::AMDGPUAS::GLOBAL_ADDRESS,   // sycl_global
+    llvm::AMDGPUAS::GLOBAL_ADDRESS,   // sycl_global_device
+    llvm::AMDGPUAS::GLOBAL_ADDRESS,   // sycl_global_host
+    llvm::AMDGPUAS::LOCAL_ADDRESS,    // sycl_local
+    llvm::AMDGPUAS::PRIVATE_ADDRESS,  // sycl_private
+    llvm::AMDGPUAS::FLAT_ADDRESS,     // ptr32_sptr
+    llvm::AMDGPUAS::FLAT_ADDRESS,     // ptr32_uptr
+    llvm::AMDGPUAS::FLAT_ADDRESS,     // ptr64
+    llvm::AMDGPUAS::FLAT_ADDRESS,     // hlsl_groupshared
 };
 
 const LangASMap AMDGPUTargetInfo::AMDGPUDefIsPrivMap = {
-    Private,  // Default
-    Global,   // opencl_global
-    Local,    // opencl_local
-    Constant, // opencl_constant
-    Private,  // opencl_private
-    Generic,  // opencl_generic
-    Global,   // opencl_global_device
-    Global,   // opencl_global_host
-    Global,   // cuda_device
-    Constant, // cuda_constant
-    Local,    // cuda_shared
+    llvm::AMDGPUAS::PRIVATE_ADDRESS,  // Default
+    llvm::AMDGPUAS::GLOBAL_ADDRESS,   // opencl_global
+    llvm::AMDGPUAS::LOCAL_ADDRESS,    // opencl_local
+    llvm::AMDGPUAS::CONSTANT_ADDRESS, // opencl_constant
+    llvm::AMDGPUAS::PRIVATE_ADDRESS,  // opencl_private
+    llvm::AMDGPUAS::FLAT_ADDRESS,     // opencl_generic
+    llvm::AMDGPUAS::GLOBAL_ADDRESS,   // opencl_global_device
+    llvm::AMDGPUAS::GLOBAL_ADDRESS,   // opencl_global_host
+    llvm::AMDGPUAS::GLOBAL_ADDRESS,   // cuda_device
+    llvm::AMDGPUAS::CONSTANT_ADDRESS, // cuda_constant
+    llvm::AMDGPUAS::LOCAL_ADDRESS,    // cuda_shared
     // SYCL address space values for this map are dummy
-    Generic, // sycl_global
-    Generic, // sycl_global_device
-    Generic, // sycl_global_host
-    Generic, // sycl_local
-    Generic, // sycl_private
-    Generic, // ptr32_sptr
-    Generic, // ptr32_uptr
-    Generic, // ptr64
-    Generic, // hlsl_groupshared
+    llvm::AMDGPUAS::FLAT_ADDRESS, // sycl_global
+    llvm::AMDGPUAS::FLAT_ADDRESS, // sycl_global_device
+    llvm::AMDGPUAS::FLAT_ADDRESS, // sycl_global_host
+    llvm::AMDGPUAS::FLAT_ADDRESS, // sycl_local
+    llvm::AMDGPUAS::FLAT_ADDRESS, // sycl_private
+    llvm::AMDGPUAS::FLAT_ADDRESS, // ptr32_sptr
+    llvm::AMDGPUAS::FLAT_ADDRESS, // ptr32_uptr
+    llvm::AMDGPUAS::FLAT_ADDRESS, // ptr64
+    llvm::AMDGPUAS::FLAT_ADDRESS, // hlsl_groupshared
 
 };
 } // namespace targets
diff --git a/clang/lib/Basic/Targets/AMDGPU.h b/clang/lib/Basic/Targets/AMDGPU.h
index 300d9691d8a0..1819ba544ccf 100644
--- a/clang/lib/Basic/Targets/AMDGPU.h
+++ b/clang/lib/Basic/Targets/AMDGPU.h
@@ -17,6 +17,7 @@
 #include "clang/Basic/TargetInfo.h"
 #include "clang/Basic/TargetOptions.h"
 #include "llvm/ADT/StringSet.h"
+#include "llvm/Support/AMDGPUAddrSpace.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/TargetParser/TargetParser.h"
 #include "llvm/TargetParser/Triple.h"
@@ -29,13 +30,6 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : public TargetInfo {
 
   static const char *const GCCRegNames[];
 
-  enum AddrSpace {
-    Generic = 0,
-    Global = 1,
-    Local = 3,
-    Constant = 4,
-    Private = 5
-  };
   static const LangASMap AMDGPUDefIsGenMap;
   static const LangASMap AMDGPUDefIsPrivMap;
 
@@ -106,7 +100,8 @@ public:
       return 32;
     unsigned TargetAS = getTargetAddressSpace(AS);
 
-    if (TargetAS == Private || TargetAS == Local)
+    if (TargetAS == llvm::AMDGPUAS::PRIVATE_ADDRESS ||
+        TargetAS == llvm::AMDGPUAS::LOCAL_ADDRESS)
       return 32;
 
     return 64;
@@ -376,7 +371,7 @@ public:
   }
 
   std::optional<LangAS> getConstantAddressSpace() const override {
-    return getLangASFromTargetAS(Constant);
+    return getLangASFromTargetAS(llvm::AMDGPUAS::CONSTANT_ADDRESS);
   }
 
   const llvm::omp::GV &getGridValue() const override {
@@ -392,7 +387,7 @@ public:
 
   /// \returns Target specific vtbl ptr address space.
   unsigned getVtblPtrAddressSpace() const override {
-    return static_cast<unsigned>(Constant);
+    return static_cast<unsigned>(llvm::AMDGPUAS::CONSTANT_ADDRESS);
   }
 
   /// \returns If a target requires an address within a target specific address
@@ -405,9 +400,9 @@ public:
   getDWARFAddressSpace(unsigned AddressSpace) const override {
     const unsigned DWARF_Private = 1;
     const unsigned DWARF_Local = 2;
-    if (AddressSpace == Private) {
+    if (AddressSpace == llvm::AMDGPUAS::PRIVATE_ADDRESS) {
       return DWARF_Private;
-    } else if (AddressSpace == Local) {
+    } else if (AddressSpace == llvm::AMDGPUAS::LOCAL_ADDRESS) {
       return DWARF_Local;
     } else {
       return std::nullopt;
diff --git a/flang/lib/Frontend/FrontendActions.cpp b/flang/lib/Frontend/FrontendActions.cpp
index b114c552b552..0b6708f47951 100644
--- a/flang/lib/Frontend/FrontendActions.cpp
+++ b/flang/lib/Frontend/FrontendActions.cpp
@@ -58,6 +58,7 @@
 #include "llvm/Passes/PassBuilder.h"
 #include "llvm/Passes/PassPlugin.h"
 #include "llvm/Passes/StandardInstrumentations.h"
+#include "llvm/Support/AMDGPUAddrSpace.h"
 #include "llvm/Support/Error.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/FileSystem.h"
@@ -166,12 +167,6 @@ static void addAMDGPUSpecificMLIRItems(mlir::ModuleOp &mlirModule,
   const llvm::Triple triple(targetOpts.triple);
   const llvm::StringRef codeObjectVersionGlobalOpName = "__oclc_ABI_version";
 
-  // TODO: Share address spaces enumeration between Clang and Flang.
-  // Currently this enumeration is defined in Clang specific class
-  // defined in file: clang/lib/Basic/Targets/AMDGPU.h .
-  // and we need to move it to LLVM directory.
-  const int constantAddressSpace = 4;
-
   if (!triple.isAMDGPU()) {
     return;
   }
@@ -202,7 +197,7 @@ static void addAMDGPUSpecificMLIRItems(mlir::ModuleOp &mlirModule,
     originalGVOp.setValueAttr(
         builder.getIntegerAttr(int32Type, oclcABIVERsion));
     originalGVOp.setUnnamedAddr(mlir::LLVM::UnnamedAddr::Local);
-    originalGVOp.setAddrSpace(constantAddressSpace);
+    originalGVOp.setAddrSpace(llvm::AMDGPUAS::CONSTANT_ADDRESS);
     originalGVOp.setVisibility_(mlir::LLVM::Visibility::Hidden);
     return;
   }
@@ -213,7 +208,7 @@ static void addAMDGPUSpecificMLIRItems(mlir::ModuleOp &mlirModule,
       /* Name */ codeObjectVersionGlobalOpName,
       /* Value */ builder.getIntegerAttr(int32Type, oclcABIVERsion));
   covInfo.setUnnamedAddr(mlir::LLVM::UnnamedAddr::Local);
-  covInfo.setAddrSpace(constantAddressSpace);
+  covInfo.setAddrSpace(llvm::AMDGPUAS::CONSTANT_ADDRESS);
   covInfo.setVisibility_(mlir::LLVM::Visibility::Hidden);
   builder.setInsertionPointToStart(mlirModule.getBody());
   builder.insert(covInfo);
diff --git a/llvm/include/llvm/Support/AMDGPUAddrSpace.h b/llvm/include/llvm/Support/AMDGPUAddrSpace.h
new file mode 100644
index 000000000000..72caf8d458c7
--- /dev/null
+++ b/llvm/include/llvm/Support/AMDGPUAddrSpace.h
@@ -0,0 +1,83 @@
+//===---------------- AMDGPUAddrSpace.h -------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+/// \file
+/// AMDGPU address space definition
+///
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_SUPPORT_AMDGPUADDRSPACE_H
+#define LLVM_SUPPORT_AMDGPUADDRSPACE_H
+
+namespace llvm {
+/// OpenCL uses address spaces to differentiate between
+/// various memory regions on the hardware. On the CPU
+/// all of the address spaces point to the same memory,
+/// however on the GPU, each address space points to
+/// a separate piece of memory that is unique from other
+/// memory locations.
+namespace AMDGPUAS {
+enum : unsigned {
+  // The maximum value for flat, generic, local, private, constant and region.
+  MAX_AMDGPU_ADDRESS = 8,
+
+  FLAT_ADDRESS = 0,   ///< Address space for flat memory.
+  GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
+  REGION_ADDRESS = 2, ///< Address space for region memory. (GDS)
+
+  CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2).
+  LOCAL_ADDRESS = 3,    ///< Address space for local memory.
+  PRIVATE_ADDRESS = 5,  ///< Address space for private memory.
+
+  CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory.
+
+  BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers.
+                          ///< Not used in backend.
+
+  BUFFER_RESOURCE = 8, ///< Address space for 128-bit buffer resources.
+
+  /// Internal address spaces. Can be freely renumbered.
+  STREAMOUT_REGISTER = 128, ///< Address space for GS NGG Streamout registers.
+  /// end Internal address spaces.
+
+  /// Address space for direct addressable parameter memory (CONST0).
+  PARAM_D_ADDRESS = 6,
+  /// Address space for indirect addressable parameter memory (VTX1).
+  PARAM_I_ADDRESS = 7,
+
+  // Do not re-order the CONSTANT_BUFFER_* enums.  Several places depend on
+  // this order to be able to dynamically index a constant buffer, for
+  // example:
+  //
+  // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
+
+  CONSTANT_BUFFER_0 = 8,
+  CONSTANT_BUFFER_1 = 9,
+  CONSTANT_BUFFER_2 = 10,
+  CONSTANT_BUFFER_3 = 11,
+  CONSTANT_BUFFER_4 = 12,
+  CONSTANT_BUFFER_5 = 13,
+  CONSTANT_BUFFER_6 = 14,
+  CONSTANT_BUFFER_7 = 15,
+  CONSTANT_BUFFER_8 = 16,
+  CONSTANT_BUFFER_9 = 17,
+  CONSTANT_BUFFER_10 = 18,
+  CONSTANT_BUFFER_11 = 19,
+  CONSTANT_BUFFER_12 = 20,
+  CONSTANT_BUFFER_13 = 21,
+  CONSTANT_BUFFER_14 = 22,
+  CONSTANT_BUFFER_15 = 23,
+
+  // Some places use this if the address space can't be determined.
+  UNKNOWN_ADDRESS_SPACE = ~0u,
+};
+} // end namespace AMDGPUAS
+} // end namespace llvm
+
+#endif // LLVM_SUPPORT_AMDGPUADDRSPACE_H
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index fc32a3dc434b..1b75607e1dc3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -12,6 +12,7 @@
 
 #include "llvm/IR/PassManager.h"
 #include "llvm/Pass.h"
+#include "llvm/Support/AMDGPUAddrSpace.h"
 #include "llvm/Support/CodeGen.h"
 
 namespace llvm {
@@ -389,72 +390,6 @@ enum TargetIndex {
   TI_SCRATCH_RSRC_DWORD2,
   TI_SCRATCH_RSRC_DWORD3
 };
-}
-
-/// OpenCL uses address spaces to differentiate between
-/// various memory regions on the hardware. On the CPU
-/// all of the address spaces point to the same memory,
-/// however on the GPU, each address space points to
-/// a separate piece of memory that is unique from other
-/// memory locations.
-namespace AMDGPUAS {
-enum : unsigned {
-  // The maximum value for flat, generic, local, private, constant and region.
-  MAX_AMDGPU_ADDRESS = 8,
-
-  FLAT_ADDRESS = 0,   ///< Address space for flat memory.
-  GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
-  REGION_ADDRESS = 2, ///< Address space for region memory. (GDS)
-
-  CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2).
-  LOCAL_ADDRESS = 3,    ///< Address space for local memory.
-  PRIVATE_ADDRESS = 5,  ///< Address space for private memory.
-
-  CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory.
-
-  BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers.
-                          ///< Not used in backend.
-
-  BUFFER_RESOURCE = 8, ///< Address space for 128-bit buffer resources.
-
-  /// Internal address spaces. Can be freely renumbered.
-  STREAMOUT_REGISTER = 128, ///< Address space for GS NGG Streamout registers.
-  /// end Internal address spaces.
-
-  /// Address space for direct addressable parameter memory (CONST0).
-  PARAM_D_ADDRESS = 6,
-  /// Address space for indirect addressable parameter memory (VTX1).
-  PARAM_I_ADDRESS = 7,
-
-  // Do not re-order the CONSTANT_BUFFER_* enums.  Several places depend on
-  // this order to be able to dynamically index a constant buffer, for
-  // example:
-  //
-  // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
-
-  CONSTANT_BUFFER_0 = 8,
-  CONSTANT_BUFFER_1 = 9,
-  CONSTANT_BUFFER_2 = 10,
-  CONSTANT_BUFFER_3 = 11,
-  CONSTANT_BUFFER_4 = 12,
-  CONSTANT_BUFFER_5 = 13,
-  CONSTANT_BUFFER_6 = 14,
-  CONSTANT_BUFFER_7 = 15,
-  CONSTANT_BUFFER_8 = 16,
-  CONSTANT_BUFFER_9 = 17,
-  CONSTANT_BUFFER_10 = 18,
-  CONSTANT_BUFFER_11 = 19,
-  CONSTANT_BUFFER_12 = 20,
-  CONSTANT_BUFFER_13 = 21,
-  CONSTANT_BUFFER_14 = 22,
-  CONSTANT_BUFFER_15 = 23,
-
-  // Some places use this if the address space can't be determined.
-  UNKNOWN_ADDRESS_SPACE = ~0u,
-};
-}
-
-namespace AMDGPU {
 
 // FIXME: Missing constant_32bit
 inline bool isFlatGlobalAddrSpace(unsigned AS) {
-- 
GitLab


From 2ce9a799f950678cef844706ecb55a483d3c225b Mon Sep 17 00:00:00 2001
From: Chuanqi Xu <yedeng.yd@linux.alibaba.com>
Date: Mon, 11 Dec 2023 18:22:48 +0800
Subject: [PATCH 092/349] [Serialization] Use packed bits to initialize
 UserDefinedLiteral

UserDefinedLiteral is also a sub class of CallExpr but we forgot to
initialize it in the same way as other sub classes of CallExpr.
---
 clang/lib/Serialization/ASTReaderStmt.cpp | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/clang/lib/Serialization/ASTReaderStmt.cpp b/clang/lib/Serialization/ASTReaderStmt.cpp
index d9eedb2e1089..b3a6f619372b 100644
--- a/clang/lib/Serialization/ASTReaderStmt.cpp
+++ b/clang/lib/Serialization/ASTReaderStmt.cpp
@@ -3851,11 +3851,14 @@ Stmt *ASTReader::ReadStmtFromStream(ModuleFile &F) {
       S = new (Context) BuiltinBitCastExpr(Empty);
       break;
 
-    case EXPR_USER_DEFINED_LITERAL:
-      S = UserDefinedLiteral::CreateEmpty(
-          Context, /*NumArgs=*/Record[ASTStmtReader::NumExprFields],
-          /*HasFPFeatures=*/Record[ASTStmtReader::NumExprFields + 1], Empty);
+    case EXPR_USER_DEFINED_LITERAL: {
+      BitsUnpacker CallExprBits(Record[ASTStmtReader::NumExprFields]);
+      auto NumArgs = CallExprBits.getNextBits(/*Width=*/16);
+      auto HasFPFeatures = CallExprBits.getNextBit();
+      S = UserDefinedLiteral::CreateEmpty(Context, NumArgs, HasFPFeatures,
+                                          Empty);
       break;
+    }
 
     case EXPR_CXX_STD_INITIALIZER_LIST:
       S = new (Context) CXXStdInitializerListExpr(Empty);
-- 
GitLab


From dd32d26a37e22a3bce15ed8c21145b17ff5e1401 Mon Sep 17 00:00:00 2001
From: Pierre van Houtryve <pierre.vanhoutryve@amd.com>
Date: Mon, 11 Dec 2023 11:38:27 +0100
Subject: [PATCH 093/349] [AMDGPU] Form V_MAD_U64_U32 from mul24 (#72393)

Fixes SWDEV-421067
---
 llvm/lib/Target/AMDGPU/VOP3Instructions.td    |  15 +-
 .../CodeGen/AMDGPU/integer-mad-patterns.ll    | 197 +++++++++++++++---
 ...ne-sink-temporal-divergence-swdev407790.ll |  39 ++--
 3 files changed, 194 insertions(+), 57 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index 114d33b07786..a73042f2e411 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -678,11 +678,22 @@ multiclass IMAD32_Pats <VOP3_Pseudo inst> {
         >;
 }
 
+// Handle cases where amdgpu-codegenprepare-mul24 made a mul24 instead of a normal mul.
+// We need to separate this because otherwise OtherPredicates would be overriden.
+class IMAD32_Mul24_Pat<VOP3_Pseudo inst>: GCNPat <
+    (i64 (add (i64 (AMDGPUmul_u24 i32:$src0, i32:$src1)), i64:$src2)),
+    (inst $src0, $src1, $src2, 0 /* clamp */)
+    >;
+
 // exclude pre-GFX9 where it was slow
-let OtherPredicates = [HasNotMADIntraFwdBug], SubtargetPredicate = isGFX9Plus in
+let OtherPredicates = [HasNotMADIntraFwdBug], SubtargetPredicate = isGFX9Plus in {
   defm : IMAD32_Pats<V_MAD_U64_U32_e64>;
-let OtherPredicates = [HasMADIntraFwdBug], SubtargetPredicate = isGFX11Only in
+  def : IMAD32_Mul24_Pat<V_MAD_U64_U32_e64>;
+}
+let OtherPredicates = [HasMADIntraFwdBug], SubtargetPredicate = isGFX11Only in {
   defm : IMAD32_Pats<V_MAD_U64_U32_gfx11_e64>;
+  def : IMAD32_Mul24_Pat<V_MAD_U64_U32_gfx11_e64>;
+}
 
 def VOP3_PERMLANE_Profile : VOP3_Profile<VOPProfile <[i32, i32, i32, i32]>, VOP3_OPSEL> {
   let InsVOP3OpSel = (ins IntOpSelMods:$src0_modifiers, VRegSrc_32:$src0,
diff --git a/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll b/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
index 40939ee69f67..e2a3749c7c47 100644
--- a/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
+++ b/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
@@ -8,8 +8,8 @@
 ; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx803 < %s | FileCheck -check-prefixes=GFX8,GFX8-SDAG %s
 ; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx803 < %s | FileCheck -check-prefixes=GFX8,GFX8-GISEL %s
 
-; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX900,GFX9-SDAG,GFX900-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX900,GFX9-GISEL,GFX900-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG,GFX900-SDAG,GFX900 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL,GFX900-GISEL,GFX900 %s
 
 ; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX9,GFX90A,GFX9-SDAG,GFX90A-SDAG %s
 ; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX9,GFX90A,GFX9-GISEL,GFX90A-GISEL %s
@@ -5482,23 +5482,41 @@ define i32 @v_multi_use_mul_chain_add_other_use_all(i32 %arg, i32 %arg1, i32 %ar
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v5, v1
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX900-LABEL: v_multi_use_mul_chain_add_other_use_all:
-; GFX900:       ; %bb.0: ; %bb
-; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT:    v_add_u32_e32 v0, 1, v0
-; GFX900-NEXT:    v_mul_lo_u32 v2, v0, v1
-; GFX900-NEXT:    v_add_u32_e32 v0, v2, v0
-; GFX900-NEXT:    v_mul_lo_u32 v0, v0, v1
-; GFX900-NEXT:    v_add_u32_e32 v1, 1, v2
-; GFX900-NEXT:    v_mul_lo_u32 v5, v0, v1
-; GFX900-NEXT:    global_store_dword v[3:4], v2, off
-; GFX900-NEXT:    s_waitcnt vmcnt(0)
-; GFX900-NEXT:    global_store_dword v[3:4], v0, off
-; GFX900-NEXT:    s_waitcnt vmcnt(0)
-; GFX900-NEXT:    global_store_dword v[3:4], v5, off
-; GFX900-NEXT:    s_waitcnt vmcnt(0)
-; GFX900-NEXT:    v_add_u32_e32 v0, v5, v1
-; GFX900-NEXT:    s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_multi_use_mul_chain_add_other_use_all:
+; GFX900-SDAG:       ; %bb.0: ; %bb
+; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT:    v_add_u32_e32 v0, 1, v0
+; GFX900-SDAG-NEXT:    v_mul_lo_u32 v2, v0, v1
+; GFX900-SDAG-NEXT:    v_add_u32_e32 v0, v2, v0
+; GFX900-SDAG-NEXT:    v_mul_lo_u32 v0, v0, v1
+; GFX900-SDAG-NEXT:    v_add_u32_e32 v1, 1, v2
+; GFX900-SDAG-NEXT:    v_mul_lo_u32 v5, v0, v1
+; GFX900-SDAG-NEXT:    global_store_dword v[3:4], v2, off
+; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0)
+; GFX900-SDAG-NEXT:    global_store_dword v[3:4], v0, off
+; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0)
+; GFX900-SDAG-NEXT:    global_store_dword v[3:4], v5, off
+; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0)
+; GFX900-SDAG-NEXT:    v_add_u32_e32 v0, v5, v1
+; GFX900-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_multi_use_mul_chain_add_other_use_all:
+; GFX900-GISEL:       ; %bb.0: ; %bb
+; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT:    v_add_u32_e32 v0, 1, v0
+; GFX900-GISEL-NEXT:    v_mul_lo_u32 v2, v0, v1
+; GFX900-GISEL-NEXT:    v_add_u32_e32 v0, v2, v0
+; GFX900-GISEL-NEXT:    v_mul_lo_u32 v0, v0, v1
+; GFX900-GISEL-NEXT:    v_add_u32_e32 v1, 1, v2
+; GFX900-GISEL-NEXT:    v_mul_lo_u32 v5, v0, v1
+; GFX900-GISEL-NEXT:    global_store_dword v[3:4], v2, off
+; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX900-GISEL-NEXT:    global_store_dword v[3:4], v0, off
+; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX900-GISEL-NEXT:    global_store_dword v[3:4], v5, off
+; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX900-GISEL-NEXT:    v_add_u32_e32 v0, v5, v1
+; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX90A-SDAG-LABEL: v_multi_use_mul_chain_add_other_use_all:
 ; GFX90A-SDAG:       ; %bb.0: ; %bb
@@ -5686,21 +5704,37 @@ define i32 @v_multi_use_mul_chain_add_other_use_some(i32 %arg, i32 %arg1, i32 %a
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX900-LABEL: v_multi_use_mul_chain_add_other_use_some:
-; GFX900:       ; %bb.0: ; %bb
-; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT:    v_add_u32_e32 v0, 1, v0
-; GFX900-NEXT:    v_mul_lo_u32 v2, v0, v1
-; GFX900-NEXT:    v_add_u32_e32 v0, v2, v0
-; GFX900-NEXT:    v_mul_lo_u32 v0, v0, v1
-; GFX900-NEXT:    v_add_u32_e32 v1, 1, v2
-; GFX900-NEXT:    v_mul_lo_u32 v0, v0, v1
-; GFX900-NEXT:    global_store_dword v[3:4], v2, off
-; GFX900-NEXT:    s_waitcnt vmcnt(0)
-; GFX900-NEXT:    global_store_dword v[3:4], v0, off
-; GFX900-NEXT:    s_waitcnt vmcnt(0)
-; GFX900-NEXT:    v_add_u32_e32 v0, v0, v1
-; GFX900-NEXT:    s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_multi_use_mul_chain_add_other_use_some:
+; GFX900-SDAG:       ; %bb.0: ; %bb
+; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT:    v_add_u32_e32 v0, 1, v0
+; GFX900-SDAG-NEXT:    v_mul_lo_u32 v2, v0, v1
+; GFX900-SDAG-NEXT:    v_add_u32_e32 v0, v2, v0
+; GFX900-SDAG-NEXT:    v_mul_lo_u32 v0, v0, v1
+; GFX900-SDAG-NEXT:    v_add_u32_e32 v1, 1, v2
+; GFX900-SDAG-NEXT:    v_mul_lo_u32 v0, v0, v1
+; GFX900-SDAG-NEXT:    global_store_dword v[3:4], v2, off
+; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0)
+; GFX900-SDAG-NEXT:    global_store_dword v[3:4], v0, off
+; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0)
+; GFX900-SDAG-NEXT:    v_add_u32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_multi_use_mul_chain_add_other_use_some:
+; GFX900-GISEL:       ; %bb.0: ; %bb
+; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT:    v_add_u32_e32 v0, 1, v0
+; GFX900-GISEL-NEXT:    v_mul_lo_u32 v2, v0, v1
+; GFX900-GISEL-NEXT:    v_add_u32_e32 v0, v2, v0
+; GFX900-GISEL-NEXT:    v_mul_lo_u32 v0, v0, v1
+; GFX900-GISEL-NEXT:    v_add_u32_e32 v1, 1, v2
+; GFX900-GISEL-NEXT:    v_mul_lo_u32 v0, v0, v1
+; GFX900-GISEL-NEXT:    global_store_dword v[3:4], v2, off
+; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX900-GISEL-NEXT:    global_store_dword v[3:4], v0, off
+; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX900-GISEL-NEXT:    v_add_u32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX90A-SDAG-LABEL: v_multi_use_mul_chain_add_other_use_some:
 ; GFX90A-SDAG:       ; %bb.0: ; %bb
@@ -8291,7 +8325,102 @@ entry:
   ret <2 x i16> %add0
 }
 
+define i64 @mul_u24_add64(i32 %x, i32 %y, i64 %z) {
+; GFX67-LABEL: mul_u24_add64:
+; GFX67:       ; %bb.0:
+; GFX67-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX67-NEXT:    v_mul_hi_u32_u24_e32 v4, v0, v1
+; GFX67-NEXT:    v_mul_u32_u24_e32 v0, v0, v1
+; GFX67-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GFX67-NEXT:    v_addc_u32_e32 v1, vcc, v4, v3, vcc
+; GFX67-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: mul_u24_add64:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_mul_hi_u32_u24_e32 v4, v0, v1
+; GFX8-NEXT:    v_mul_u32_u24_e32 v0, v0, v1
+; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
+; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, v4, v3, vcc
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-SDAG-LABEL: mul_u24_add64:
+; GFX9-SDAG:       ; %bb.0:
+; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], v0, v1, v[2:3]
+; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-GISEL-LABEL: mul_u24_add64:
+; GFX9-GISEL:       ; %bb.0:
+; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT:    v_mul_hi_u32_u24_e32 v4, v0, v1
+; GFX9-GISEL-NEXT:    v_mul_u32_u24_e32 v0, v0, v1
+; GFX9-GISEL-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v1, vcc, v4, v3, vcc
+; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: mul_u24_add64:
+; GFX10-SDAG:       ; %bb.0:
+; GFX10-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT:    v_mad_u64_u32 v[0:1], null, v0, v1, v[2:3]
+; GFX10-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: mul_u24_add64:
+; GFX10-GISEL:       ; %bb.0:
+; GFX10-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT:    v_mul_u32_u24_e32 v4, v0, v1
+; GFX10-GISEL-NEXT:    v_mul_hi_u32_u24_e32 v1, v0, v1
+; GFX10-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, v4, v2
+; GFX10-GISEL-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
+; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
+  %mul = call i64 @llvm.amdgcn.mul.u24.i64(i32 %x, i32 %y)
+  %add = add i64 %mul, %z
+  ret i64 %add
+}
+
+define i64 @mul_u24_zext_add64(i32 %x, i32 %y, i64 %z) {
+; GFX67-LABEL: mul_u24_zext_add64:
+; GFX67:       ; %bb.0:
+; GFX67-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX67-NEXT:    v_mul_u32_u24_e32 v0, v0, v1
+; GFX67-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GFX67-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; GFX67-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: mul_u24_zext_add64:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_mul_u32_u24_e32 v0, v0, v1
+; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
+; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: mul_u24_zext_add64:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_u32_u24_e32 v0, v0, v1
+; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: mul_u24_zext_add64:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_u32_u24_e32 v0, v0, v1
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v0, v2
+; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0, v3, vcc_lo
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %mul = call i32 @llvm.amdgcn.mul.u24(i32 %x, i32 %y)
+  %mul.zext = zext i32 %mul to i64
+  %add = add i64 %mul.zext, %z
+  ret i64 %add
+}
+
+declare i64 @llvm.amdgcn.mul.u24.i64(i32, i32)
+declare i32 @llvm.amdgcn.mul.u24(i32, i32)
+
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
 ; GFX6: {{.*}}
 ; GFX7: {{.*}}
+; GFX900: {{.*}}
 ; GFX90A: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll b/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
index d9c6fbb31901..cf5886010160 100644
--- a/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
+++ b/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
@@ -444,31 +444,28 @@ define protected amdgpu_kernel void @kernel_round1(ptr addrspace(1) nocapture no
 ; CHECK-NEXT:    s_xor_b32 s4, exec_lo, s4
 ; CHECK-NEXT:    s_cbranch_execz .LBB0_31
 ; CHECK-NEXT:  ; %bb.30: ; in Loop: Header=BB0_28 Depth=1
-; CHECK-NEXT:    v_xor_b32_e32 v5, v60, v58
-; CHECK-NEXT:    v_lshrrev_b64 v[3:4], 16, v[56:57]
-; CHECK-NEXT:    v_mul_u32_u24_e32 v11, 0x180, v73
-; CHECK-NEXT:    v_lshlrev_b32_e32 v0, 5, v0
-; CHECK-NEXT:    v_lshrrev_b64 v[1:2], 16, v[45:46]
-; CHECK-NEXT:    v_lshlrev_b32_e32 v7, 16, v5
+; CHECK-NEXT:    v_xor_b32_e32 v4, v60, v58
+; CHECK-NEXT:    v_lshrrev_b64 v[2:3], 16, v[56:57]
+; CHECK-NEXT:    v_mad_u64_u32 v[6:7], null, 0x180, v73, s[46:47]
+; CHECK-NEXT:    v_lshlrev_b32_e32 v10, 5, v0
+; CHECK-NEXT:    v_lshlrev_b32_e32 v1, 16, v4
 ; CHECK-NEXT:    v_lshlrev_b32_e32 v8, 6, v72
-; CHECK-NEXT:    v_add_co_u32 v11, vcc_lo, s46, v11
-; CHECK-NEXT:    v_lshlrev_b32_e32 v10, 12, v63
-; CHECK-NEXT:    v_or_b32_e32 v4, v7, v4
-; CHECK-NEXT:    v_mul_hi_u32_u24_e32 v7, 0x180, v73
-; CHECK-NEXT:    v_xor_b32_e32 v6, v61, v59
-; CHECK-NEXT:    v_lshlrev_b32_e32 v9, 16, v56
-; CHECK-NEXT:    v_or3_b32 v10, v8, v10, v62
+; CHECK-NEXT:    v_lshlrev_b32_e32 v9, 12, v63
+; CHECK-NEXT:    v_xor_b32_e32 v5, v61, v59
+; CHECK-NEXT:    v_lshlrev_b32_e32 v11, 16, v56
+; CHECK-NEXT:    v_or_b32_e32 v3, v1, v3
+; CHECK-NEXT:    v_lshrrev_b64 v[0:1], 16, v[45:46]
+; CHECK-NEXT:    v_add_co_u32 v6, vcc_lo, v6, v10
+; CHECK-NEXT:    v_or3_b32 v8, v8, v9, v62
+; CHECK-NEXT:    v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
+; CHECK-NEXT:    v_lshrrev_b64 v[4:5], 16, v[4:5]
+; CHECK-NEXT:    v_or_b32_e32 v1, v11, v1
 ; CHECK-NEXT:    ; implicit-def: $vgpr42
 ; CHECK-NEXT:    ; implicit-def: $vgpr43
 ; CHECK-NEXT:    ; implicit-def: $vgpr44
-; CHECK-NEXT:    v_add_co_ci_u32_e32 v12, vcc_lo, s47, v7, vcc_lo
-; CHECK-NEXT:    v_add_co_u32 v7, vcc_lo, v11, v0
-; CHECK-NEXT:    v_lshrrev_b64 v[5:6], 16, v[5:6]
-; CHECK-NEXT:    v_add_co_ci_u32_e32 v8, vcc_lo, 0, v12, vcc_lo
-; CHECK-NEXT:    v_or_b32_e32 v2, v9, v2
-; CHECK-NEXT:    global_store_dword v[7:8], v10, off offset:4
-; CHECK-NEXT:    global_store_dwordx4 v[7:8], v[1:4], off offset:8
-; CHECK-NEXT:    global_store_dwordx2 v[7:8], v[5:6], off offset:24
+; CHECK-NEXT:    global_store_dword v[6:7], v8, off offset:4
+; CHECK-NEXT:    global_store_dwordx4 v[6:7], v[0:3], off offset:8
+; CHECK-NEXT:    global_store_dwordx2 v[6:7], v[4:5], off offset:24
 ; CHECK-NEXT:  .LBB0_31: ; %Flow
 ; CHECK-NEXT:    ; in Loop: Header=BB0_28 Depth=1
 ; CHECK-NEXT:    s_andn2_saveexec_b32 s4, s4
-- 
GitLab


From 162248c22dcfa0674efd339f35717ea711b8e025 Mon Sep 17 00:00:00 2001
From: Felipe de Azevedo Piovezan <fpiovezan@apple.com>
Date: Mon, 11 Dec 2023 08:01:04 -0300
Subject: [PATCH 094/349] [SymbolFileDWARF][NFC] Remove duplicated code
 checking for type tags (#74773)

There was duplicated (and complex) code querying whether tags were
type-like tags (i.e. class or struct); this has been factored out into a
helper function.

There was also a comment about not comparing identical DIEs without ever
performing that check; this comment has been removed. It was likely a
result of copy paste from another function in this same file which
actually does that check.
---
 .../SymbolFile/DWARF/SymbolFileDWARF.cpp      | 60 +++++--------------
 1 file changed, 15 insertions(+), 45 deletions(-)

diff --git a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
index d4cc26a3c329..d4c573ecd468 100644
--- a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
+++ b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
@@ -132,6 +132,11 @@ public:
 
 } // namespace
 
+bool IsStructOrClassTag(llvm::dwarf::Tag Tag) {
+  return Tag == llvm::dwarf::Tag::DW_TAG_class_type ||
+         Tag == llvm::dwarf::Tag::DW_TAG_structure_type;
+}
+
 static PluginProperties &GetGlobalPluginProperties() {
   static PluginProperties g_settings;
   return g_settings;
@@ -2947,29 +2952,18 @@ TypeSP SymbolFileDWARF::FindCompleteObjCDefinitionTypeForDIE(
 
   m_index->GetCompleteObjCClass(
       type_name, must_be_implementation, [&](DWARFDIE type_die) {
-        bool try_resolving_type = false;
-
         // Don't try and resolve the DIE we are looking for with the DIE
         // itself!
-        if (type_die != die) {
-          switch (type_die.Tag()) {
-          case DW_TAG_class_type:
-          case DW_TAG_structure_type:
-            try_resolving_type = true;
-            break;
-          default:
-            break;
-          }
-        }
-        if (!try_resolving_type)
+        if (type_die == die || !IsStructOrClassTag(type_die.Tag()))
           return true;
 
         if (must_be_implementation &&
-            type_die.Supports_DW_AT_APPLE_objc_complete_type())
-          try_resolving_type = type_die.GetAttributeValueAsUnsigned(
+            type_die.Supports_DW_AT_APPLE_objc_complete_type()) {
+          const bool try_resolving_type = type_die.GetAttributeValueAsUnsigned(
               DW_AT_APPLE_objc_complete_type, 0);
-        if (!try_resolving_type)
-          return true;
+          if (!try_resolving_type)
+            return true;
+        }
 
         Type *resolved_type = ResolveType(type_die, false, true);
         if (!resolved_type || resolved_type == DIE_IS_BEING_PARSED)
@@ -3128,36 +3122,12 @@ SymbolFileDWARF::FindDefinitionTypeForDWARFDeclContext(const DWARFDIE &die) {
       if (type_system &&
           !type_system->SupportsLanguage(GetLanguage(*type_die.GetCU())))
         return true;
-      bool try_resolving_type = false;
 
-      // Don't try and resolve the DIE we are looking for with the DIE
-      // itself!
       const dw_tag_t type_tag = type_die.Tag();
-      // Make sure the tags match
-      if (type_tag == tag) {
-        // The tags match, lets try resolving this type
-        try_resolving_type = true;
-      } else {
-        // The tags don't match, but we need to watch our for a forward
-        // declaration for a struct and ("struct foo") ends up being a
-        // class ("class foo { ... };") or vice versa.
-        switch (type_tag) {
-        case DW_TAG_class_type:
-          // We had a "class foo", see if we ended up with a "struct foo
-          // { ... };"
-          try_resolving_type = (tag == DW_TAG_structure_type);
-          break;
-        case DW_TAG_structure_type:
-          // We had a "struct foo", see if we ended up with a "class foo
-          // { ... };"
-          try_resolving_type = (tag == DW_TAG_class_type);
-          break;
-        default:
-          // Tags don't match, don't event try to resolve using this type
-          // whose name matches....
-          break;
-        }
-      }
+      // Resolve the type if both have the same tag or {class, struct} tags.
+      const bool try_resolving_type =
+          type_tag == tag ||
+          (IsStructOrClassTag(type_tag) && IsStructOrClassTag(tag));
 
       if (!try_resolving_type) {
         if (log) {
-- 
GitLab


From 35ebd92d3d13925c1a4c61424a7be21cf32dc4c1 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad@amd.com>
Date: Mon, 11 Dec 2023 11:06:50 +0000
Subject: [PATCH 095/349] [GlobalISel] Add G_PREFETCH (#74863)

---
 .../CodeGen/GlobalISel/MachineIRBuilder.h     |  5 ++
 llvm/include/llvm/Support/TargetOpcodes.def   |  3 +
 llvm/include/llvm/Target/GenericOpcodes.td    |  9 +++
 llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp  | 15 +++++
 .../CodeGen/GlobalISel/MachineIRBuilder.cpp   | 12 ++++
 llvm/lib/CodeGen/MachineVerifier.cpp          | 23 +++++++
 llvm/lib/IR/Verifier.cpp                      |  2 +-
 llvm/lib/Target/AArch64/AArch64InstrGISel.td  |  4 +-
 .../AArch64/GISel/AArch64LegalizerInfo.cpp    | 55 ++++++++--------
 .../AArch64/GISel/AArch64LegalizerInfo.h      |  1 +
 .../GlobalISel/legalizer-info-validation.mir  |  3 +
 .../GlobalISel/irtranslator-prefetch.ll       | 32 ++++++++++
 llvm/test/MachineVerifier/test_g_prefetch.mir | 40 ++++++++++++
 .../builtins/match-table-replacerreg.td       | 20 +++---
 .../match-table-imms.td                       | 28 ++++-----
 .../match-table-patfrag-root.td               |  2 +-
 .../GlobalISelCombinerEmitter/match-table.td  | 62 +++++++++----------
 llvm/test/TableGen/GlobalISelEmitter.td       |  2 +-
 18 files changed, 233 insertions(+), 85 deletions(-)
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-prefetch.ll
 create mode 100644 llvm/test/MachineVerifier/test_g_prefetch.mir

diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index 3d36d06a7e9d..1387a0a37561 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -1529,6 +1529,11 @@ public:
   /// Build and insert `G_FENCE Ordering, Scope`.
   MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope);
 
+  /// Build and insert G_PREFETCH \p Addr, \p RW, \p Locality, \p CacheType
+  MachineInstrBuilder buildPrefetch(const SrcOp &Addr, unsigned RW,
+                                    unsigned Locality, unsigned CacheType,
+                                    MachineMemOperand &MMO);
+
   /// Build and insert \p Dst = G_FREEZE \p Src
   MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src) {
     return buildInstr(TargetOpcode::G_FREEZE, {Dst}, {Src});
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index 16a747d23e73..3824b1c66951 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -415,6 +415,9 @@ HANDLE_TARGET_OPCODE_MARKER(GENERIC_ATOMICRMW_OP_END, G_ATOMICRMW_UDEC_WRAP)
 // Generic atomic fence
 HANDLE_TARGET_OPCODE(G_FENCE)
 
+/// Generic prefetch
+HANDLE_TARGET_OPCODE(G_PREFETCH)
+
 /// Generic conditional branch instruction.
 HANDLE_TARGET_OPCODE(G_BRCOND)
 
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index 9a9c09d3c20d..73e38b15bf67 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -1209,6 +1209,15 @@ def G_FENCE : GenericInstruction {
   let hasSideEffects = true;
 }
 
+// Generic opcode equivalent to the llvm.prefetch intrinsic.
+def G_PREFETCH : GenericInstruction {
+  let OutOperandList = (outs);
+  let InOperandList = (ins ptype0:$address, i32imm:$rw, i32imm:$locality, i32imm:$cachetype);
+  let hasSideEffects = true;
+  let mayLoad = true;
+  let mayStore = true;
+}
+
 //------------------------------------------------------------------------------
 // Variadic ops
 //------------------------------------------------------------------------------
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 14a4e72152e7..27a53e55f32f 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -2435,6 +2435,21 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
     MIRBuilder.buildInstr(TargetOpcode::G_RESET_FPMODE, {}, {});
     return true;
   }
+  case Intrinsic::prefetch: {
+    Value *Addr = CI.getOperand(0);
+    unsigned RW = cast<ConstantInt>(CI.getOperand(1))->getZExtValue();
+    unsigned Locality = cast<ConstantInt>(CI.getOperand(2))->getZExtValue();
+    unsigned CacheType = cast<ConstantInt>(CI.getOperand(3))->getZExtValue();
+
+    auto Flags = RW ? MachineMemOperand::MOStore : MachineMemOperand::MOLoad;
+    auto &MMO = *MF->getMachineMemOperand(MachinePointerInfo(Addr), Flags,
+                                          LLT(), Align());
+
+    MIRBuilder.buildPrefetch(getOrCreateVReg(*Addr), RW, Locality, CacheType,
+                             MMO);
+
+    return true;
+  }
 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC)  \
   case Intrinsic::INTRINSIC:
 #include "llvm/IR/ConstrainedOps.def"
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index 80e9c08e850b..6e1c0e907e8e 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -1051,6 +1051,18 @@ MachineIRBuilder::buildFence(unsigned Ordering, unsigned Scope) {
     .addImm(Scope);
 }
 
+MachineInstrBuilder MachineIRBuilder::buildPrefetch(const SrcOp &Addr,
+                                                    unsigned RW,
+                                                    unsigned Locality,
+                                                    unsigned CacheType,
+                                                    MachineMemOperand &MMO) {
+  auto MIB = buildInstr(TargetOpcode::G_PREFETCH);
+  Addr.addSrcToMIB(MIB);
+  MIB.addImm(RW).addImm(Locality).addImm(CacheType);
+  MIB.addMemOperand(&MMO);
+  return MIB;
+}
+
 MachineInstrBuilder
 MachineIRBuilder::buildBlockAddress(Register Res, const BlockAddress *BA) {
 #ifndef NDEBUG
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index aaf9bd740d13..a015d9bbd2d3 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1812,6 +1812,29 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
     }
     break;
   }
+  case TargetOpcode::G_PREFETCH: {
+    const MachineOperand &AddrOp = MI->getOperand(0);
+    if (!AddrOp.isReg() || !MRI->getType(AddrOp.getReg()).isPointer()) {
+      report("addr operand must be a pointer", &AddrOp, 0);
+      break;
+    }
+    const MachineOperand &RWOp = MI->getOperand(1);
+    if (!RWOp.isImm() || (uint64_t)RWOp.getImm() >= 2) {
+      report("rw operand must be an immediate 0-1", &RWOp, 1);
+      break;
+    }
+    const MachineOperand &LocalityOp = MI->getOperand(2);
+    if (!LocalityOp.isImm() || (uint64_t)LocalityOp.getImm() >= 4) {
+      report("locality operand must be an immediate 0-3", &LocalityOp, 2);
+      break;
+    }
+    const MachineOperand &CacheTypeOp = MI->getOperand(3);
+    if (!CacheTypeOp.isImm() || (uint64_t)CacheTypeOp.getImm() >= 2) {
+      report("cache type operand must be an immediate 0-1", &CacheTypeOp, 3);
+      break;
+    }
+    break;
+  }
   case TargetOpcode::G_ASSERT_ALIGN: {
     if (MI->getOperand(2).getImm() < 1)
       report("alignment immediate must be >= 1", MI);
diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index f137f0468c3c..c87f164bdd0f 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -5374,7 +5374,7 @@ void Verifier::visitIntrinsicCall(Intrinsic::ID ID, CallBase &Call) {
     Check(cast<ConstantInt>(Call.getArgOperand(1))->getZExtValue() < 2,
           "rw argument to llvm.prefetch must be 0-1", Call);
     Check(cast<ConstantInt>(Call.getArgOperand(2))->getZExtValue() < 4,
-          "locality argument to llvm.prefetch must be 0-4", Call);
+          "locality argument to llvm.prefetch must be 0-3", Call);
     Check(cast<ConstantInt>(Call.getArgOperand(3))->getZExtValue() < 2,
           "cache type argument to llvm.prefetch must be 0-1", Call);
     break;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrGISel.td b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
index 1711360779bf..1c88456560d3 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrGISel.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
@@ -209,7 +209,7 @@ def G_FCMLTZ : AArch64GenericInstruction {
   let hasSideEffects = 0;
 }
 
-def G_PREFETCH : AArch64GenericInstruction {
+def G_AARCH64_PREFETCH : AArch64GenericInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins type0:$imm, ptype0:$src1);
   let hasSideEffects = 1;
@@ -287,7 +287,7 @@ def : GINodeEquiv<G_SDOT, AArch64sdot>;
 
 def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;
 
-def : GINodeEquiv<G_PREFETCH, AArch64Prefetch>;
+def : GINodeEquiv<G_AARCH64_PREFETCH, AArch64Prefetch>;
 
 // These are patterns that we only use for GlobalISel via the importer.
 def : Pat<(f32 (fadd (vector_extract (v2f32 FPR64:$Rn), (i64 0)),
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 21a412e9360d..a35957c34a59 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -1127,6 +1127,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
 
   getActionDefinitionsBuilder(G_IS_FPCLASS).lower();
 
+  getActionDefinitionsBuilder(G_PREFETCH).custom();
+
   getLegacyLegalizerInfo().computeTables();
   verify(*ST.getInstrInfo());
 }
@@ -1176,6 +1178,8 @@ bool AArch64LegalizerInfo::legalizeCustom(LegalizerHelper &Helper,
     return legalizeExtractVectorElt(MI, MRI, Helper);
   case TargetOpcode::G_DYN_STACKALLOC:
     return legalizeDynStackAlloc(MI, Helper);
+  case TargetOpcode::G_PREFETCH:
+    return legalizePrefetch(MI, Helper);
   }
 
   llvm_unreachable("expected switch to return");
@@ -1349,30 +1353,6 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
     Value.setReg(ExtValueReg);
     return true;
   }
-  case Intrinsic::prefetch: {
-    MachineIRBuilder MIB(MI);
-    auto &AddrVal = MI.getOperand(1);
-
-    int64_t IsWrite = MI.getOperand(2).getImm();
-    int64_t Locality = MI.getOperand(3).getImm();
-    int64_t IsData = MI.getOperand(4).getImm();
-
-    bool IsStream = Locality == 0;
-    if (Locality != 0) {
-      assert(Locality <= 3 && "Prefetch locality out-of-range");
-      // The locality degree is the opposite of the cache speed.
-      // Put the number the other way around.
-      // The encoding starts at 0 for level 1
-      Locality = 3 - Locality;
-    }
-
-    unsigned PrfOp =
-        (IsWrite << 4) | (!IsData << 3) | (Locality << 1) | IsStream;
-
-    MIB.buildInstr(AArch64::G_PREFETCH).addImm(PrfOp).add(AddrVal);
-    MI.eraseFromParent();
-    return true;
-  }
   case Intrinsic::aarch64_prefetch: {
     MachineIRBuilder MIB(MI);
     auto &AddrVal = MI.getOperand(1);
@@ -1387,7 +1367,7 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
                      (Target << 1) |     // Cache level bits
                      (unsigned)IsStream; // Stream bit
 
-    MIB.buildInstr(AArch64::G_PREFETCH).addImm(PrfOp).add(AddrVal);
+    MIB.buildInstr(AArch64::G_AARCH64_PREFETCH).addImm(PrfOp).add(AddrVal);
     MI.eraseFromParent();
     return true;
   }
@@ -1986,3 +1966,28 @@ bool AArch64LegalizerInfo::legalizeDynStackAlloc(
   MI.eraseFromParent();
   return true;
 }
+
+bool AArch64LegalizerInfo::legalizePrefetch(MachineInstr &MI,
+                                            LegalizerHelper &Helper) const {
+  MachineIRBuilder &MIB = Helper.MIRBuilder;
+  auto &AddrVal = MI.getOperand(0);
+
+  int64_t IsWrite = MI.getOperand(1).getImm();
+  int64_t Locality = MI.getOperand(2).getImm();
+  int64_t IsData = MI.getOperand(3).getImm();
+
+  bool IsStream = Locality == 0;
+  if (Locality != 0) {
+    assert(Locality <= 3 && "Prefetch locality out-of-range");
+    // The locality degree is the opposite of the cache speed.
+    // Put the number the other way around.
+    // The encoding starts at 0 for level 1
+    Locality = 3 - Locality;
+  }
+
+  unsigned PrfOp = (IsWrite << 4) | (!IsData << 3) | (Locality << 1) | IsStream;
+
+  MIB.buildInstr(AArch64::G_AARCH64_PREFETCH).addImm(PrfOp).add(AddrVal);
+  MI.eraseFromParent();
+  return true;
+}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
index 6fd859d334cd..19f77baa77f8 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
@@ -64,6 +64,7 @@ private:
   bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
                                 LegalizerHelper &Helper) const;
   bool legalizeDynStackAlloc(MachineInstr &MI, LegalizerHelper &Helper) const;
+  bool legalizePrefetch(MachineInstr &MI, LegalizerHelper &Helper) const;
   const AArch64Subtarget *ST;
 };
 } // End llvm namespace.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index ae15e74a4327..178db852e35b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -258,6 +258,9 @@
 # DEBUG-NEXT: G_FENCE (opcode {{[0-9]+}}): 0 type indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: G_PREFETCH (opcode {{[0-9]+}}): 1 type index, 0 imm indices
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: G_BRCOND (opcode {{[0-9]+}}): 1 type index, 0 imm indices
 # DEBUG-NEXT: .. the first uncovered type index: 1, OK
 # DEBUG-NEXT: .. the first uncovered imm index: 0, OK
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-prefetch.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-prefetch.ll
new file mode 100644
index 000000000000..b53610a0f22e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-prefetch.ll
@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -global-isel -mtriple=amdgcn -verify-machineinstrs -stop-after=irtranslator < %s | FileCheck %s
+
+define void @prefetch_read(ptr %ptr) {
+  ; CHECK-LABEL: name: prefetch_read
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $vgpr0, $vgpr1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; CHECK-NEXT:   [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+  ; CHECK-NEXT:   G_PREFETCH [[MV]](p0), 0, 0, 0 :: (load unknown-size from %ir.ptr, align 1)
+  ; CHECK-NEXT:   SI_RETURN
+  call void @llvm.prefetch.p0(ptr %ptr, i32 0, i32 0, i32 0)
+  ret void
+}
+
+define void @prefetch_write(ptr %ptr) {
+  ; CHECK-LABEL: name: prefetch_write
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $vgpr0, $vgpr1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; CHECK-NEXT:   [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+  ; CHECK-NEXT:   G_PREFETCH [[MV]](p0), 1, 1, 1 :: (store unknown-size into %ir.ptr, align 1)
+  ; CHECK-NEXT:   SI_RETURN
+  call void @llvm.prefetch.p0(ptr %ptr, i32 1, i32 1, i32 1)
+  ret void
+}
+
+declare void @llvm.prefetch.p0(ptr, i32, i32, i32)
diff --git a/llvm/test/MachineVerifier/test_g_prefetch.mir b/llvm/test/MachineVerifier/test_g_prefetch.mir
new file mode 100644
index 000000000000..a08b0803fc35
--- /dev/null
+++ b/llvm/test/MachineVerifier/test_g_prefetch.mir
@@ -0,0 +1,40 @@
+# RUN: not --crash llc -o - -mtriple=aarch64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: aarch64-registered-target
+
+---
+name: test_fcmp
+legalized: true
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+liveins:
+body: |
+  bb.0:
+    liveins: $x0, $w0, $q0
+    %s32:_(s32) = COPY $w0
+    %ptr:_(p0) = COPY $x0
+
+    G_PREFETCH %ptr
+    ; CHECK: *** Bad machine code: Too few operands ***
+    ; CHECK: 4 operands expected, but 1 given.
+
+    G_PREFETCH %ptr, 0, 0, 0, 0
+    ; CHECK: *** Bad machine code: Extra explicit operand on non-variadic instruction ***
+    ; CHECK: operand 4:
+
+    G_PREFETCH %s32, 0, 0, 0
+    ; CHECK: *** Bad machine code: addr operand must be a pointer ***
+    ; CHECK: operand 0:
+
+    G_PREFETCH %ptr, 10, 0, 0
+    ; CHECK: *** Bad machine code: rw operand must be an immediate 0-1 ***
+    ; CHECK: operand 1:
+
+    G_PREFETCH %ptr, 0, 10, 0
+    ; CHECK: *** Bad machine code: locality operand must be an immediate 0-3 ***
+    ; CHECK: operand 2:
+
+    G_PREFETCH %ptr, 0, 0, 10
+    ; CHECK: *** Bad machine code: cache type operand must be an immediate 0-1 ***
+    ; CHECK: operand 3:
+...
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td
index 2d968977701f..6ae1305aa1aa 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td
@@ -28,11 +28,11 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
 
 // CHECK:      const int64_t *GenMyCombiner::getMatchTable() const {
 // CHECK-NEXT:   constexpr static int64_t MatchTable0[] = {
-// CHECK-NEXT:     GIM_SwitchOpcode, /*MI*/0, /*[*/65, 180, /*)*//*default:*//*Label 2*/ 192,
-// CHECK-NEXT:     /*TargetOpcode::G_UNMERGE_VALUES*//*Label 0*/ 120, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-// CHECK-NEXT:     /*TargetOpcode::G_FNEG*//*Label 1*/ 165,
-// CHECK-NEXT:     // Label 0: @120
-// CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 3*/ 164, // Rule ID 1 //
+// CHECK-NEXT:     GIM_SwitchOpcode, /*MI*/0, /*[*/65, 181, /*)*//*default:*//*Label 2*/ 193,
+// CHECK-NEXT:     /*TargetOpcode::G_UNMERGE_VALUES*//*Label 0*/ 121, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+// CHECK-NEXT:     /*TargetOpcode::G_FNEG*//*Label 1*/ 166,
+// CHECK-NEXT:     // Label 0: @121
+// CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 3*/ 165, // Rule ID 1 //
 // CHECK-NEXT:       GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule1Enabled,
 // CHECK-NEXT:       GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 // CHECK-NEXT:       // MIs[0] a
@@ -57,10 +57,10 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
 // CHECK-NEXT:       GIR_EraseFromParent, /*InsnID*/0,
 // CHECK-NEXT:       GIR_ReplaceRegWithTempReg, /*OldInsnID*/0, /*OldOpIdx*/1, /*TempRegID*/0,
 // CHECK-NEXT:       GIR_Done,
-// CHECK-NEXT:     // Label 3: @164
+// CHECK-NEXT:     // Label 3: @165
 // CHECK-NEXT:     GIM_Reject,
-// CHECK-NEXT:     // Label 1: @165
-// CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 4*/ 191, // Rule ID 0 //
+// CHECK-NEXT:     // Label 1: @166
+// CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 4*/ 192, // Rule ID 0 //
 // CHECK-NEXT:       GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled,
 // CHECK-NEXT:       // MIs[0] dst
 // CHECK-NEXT:       // No operand predicates
@@ -75,9 +75,9 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
 // CHECK-NEXT:       GIR_ReplaceReg, /*OldInsnID*/0, /*OldOpIdx*/0, /*NewInsnId*/1, /*NewOpIdx*/1,
 // CHECK-NEXT:       GIR_EraseFromParent, /*InsnID*/0,
 // CHECK-NEXT:       GIR_Done,
-// CHECK-NEXT:     // Label 4: @191
+// CHECK-NEXT:     // Label 4: @192
 // CHECK-NEXT:     GIM_Reject,
-// CHECK-NEXT:     // Label 2: @192
+// CHECK-NEXT:     // Label 2: @193
 // CHECK-NEXT:     GIM_Reject,
 // CHECK-NEXT:     };
 // CHECK-NEXT:   return MatchTable0;
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td
index 0495a66a7c57..fd5f7db0b4f1 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td
@@ -34,12 +34,12 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
 
 // CHECK:      const int64_t *GenMyCombiner::getMatchTable() const {
 // CHECK-NEXT:   constexpr static int64_t MatchTable0[] = {
-// CHECK-NEXT:     GIM_SwitchOpcode, /*MI*/0, /*[*/19, 126, /*)*//*default:*//*Label 3*/ 194,
-// CHECK-NEXT:     /*TargetOpcode::COPY*//*Label 0*/ 112, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-// CHECK-NEXT:     /*TargetOpcode::G_CONSTANT*//*Label 1*/ 138, 0, 0, 0, 0, 0,
-// CHECK-NEXT:     /*TargetOpcode::G_ZEXT*//*Label 2*/ 165,
-// CHECK-NEXT:     // Label 0: @112
-// CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 4*/ 137, // Rule ID 0 //
+// CHECK-NEXT:     GIM_SwitchOpcode, /*MI*/0, /*[*/19, 127, /*)*//*default:*//*Label 3*/ 195,
+// CHECK-NEXT:     /*TargetOpcode::COPY*//*Label 0*/ 113, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+// CHECK-NEXT:     /*TargetOpcode::G_CONSTANT*//*Label 1*/ 139, 0, 0, 0, 0, 0,
+// CHECK-NEXT:     /*TargetOpcode::G_ZEXT*//*Label 2*/ 166,
+// CHECK-NEXT:     // Label 0: @113
+// CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 4*/ 138, // Rule ID 0 //
 // CHECK-NEXT:       GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled,
 // CHECK-NEXT:       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 // CHECK-NEXT:       // MIs[0] a
@@ -51,10 +51,10 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
 // CHECK-NEXT:       GIR_AddImm, /*InsnID*/0, /*Imm*/0,
 // CHECK-NEXT:       GIR_EraseFromParent, /*InsnID*/0,
 // CHECK-NEXT:       GIR_Done,
-// CHECK-NEXT:     // Label 4: @137
+// CHECK-NEXT:     // Label 4: @138
 // CHECK-NEXT:     GIM_Reject,
-// CHECK-NEXT:     // Label 1: @138
-// CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 5*/ 164, // Rule ID 2 //
+// CHECK-NEXT:     // Label 1: @139
+// CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 5*/ 165, // Rule ID 2 //
 // CHECK-NEXT:       GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule2Enabled,
 // CHECK-NEXT:       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 // CHECK-NEXT:       // MIs[0] a
@@ -66,10 +66,10 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
 // CHECK-NEXT:       GIR_AddCImm, /*InsnID*/0, /*Type*/GILLT_s32, /*Imm*/42,
 // CHECK-NEXT:       GIR_EraseFromParent, /*InsnID*/0,
 // CHECK-NEXT:       GIR_Done,
-// CHECK-NEXT:     // Label 5: @164
+// CHECK-NEXT:     // Label 5: @165
 // CHECK-NEXT:     GIM_Reject,
-// CHECK-NEXT:     // Label 2: @165
-// CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 6*/ 193, // Rule ID 1 //
+// CHECK-NEXT:     // Label 2: @166
+// CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 6*/ 194, // Rule ID 1 //
 // CHECK-NEXT:       GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule1Enabled,
 // CHECK-NEXT:       // MIs[0] a
 // CHECK-NEXT:       // No operand predicates
@@ -83,9 +83,9 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
 // CHECK-NEXT:       GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
 // CHECK-NEXT:       GIR_EraseFromParent, /*InsnID*/0,
 // CHECK-NEXT:       GIR_Done,
-// CHECK-NEXT:     // Label 6: @193
+// CHECK-NEXT:     // Label 6: @194
 // CHECK-NEXT:     GIM_Reject,
-// CHECK-NEXT:     // Label 3: @194
+// CHECK-NEXT:     // Label 3: @195
 // CHECK-NEXT:     GIM_Reject,
 // CHECK-NEXT:     };
 // CHECK-NEXT:   return MatchTable0;
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td
index 5cb9206ca5f2..b62ebcf24687 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td
@@ -28,7 +28,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
 
 // CHECK:      const int64_t *GenMyCombiner::getMatchTable() const {
 // CHECK-NEXT:   constexpr static int64_t MatchTable0[] = {
-// CHECK-NEXT:     GIM_SwitchOpcode, /*MI*/0, /*[*/118, 181, /*)*//*default:*//*Label 3*/ 152,
+// CHECK-NEXT:     GIM_SwitchOpcode, /*MI*/0, /*[*/119, 182, /*)*//*default:*//*Label 3*/ 152,
 // CHECK-NEXT:     /*TargetOpcode::G_TRUNC*//*Label 0*/ 68, 0, 0, 0, 0, 0, 0,
 // CHECK-NEXT:     /*TargetOpcode::G_ZEXT*//*Label 1*/ 93, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 // CHECK-NEXT:     /*TargetOpcode::G_FPEXT*//*Label 2*/ 127,
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td
index 3b0f65692432..6777089f846f 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td
@@ -132,15 +132,15 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
 // Verify match table.
 // CHECK:      const int64_t *GenMyCombiner::getMatchTable() const {
 // CHECK-NEXT:   constexpr static int64_t MatchTable0[] = {
-// CHECK-NEXT:     GIM_SwitchOpcode, /*MI*/0, /*[*/19, 126, /*)*//*default:*//*Label 6*/ 267,
-// CHECK-NEXT:     /*TargetOpcode::COPY*//*Label 0*/ 112, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-// CHECK-NEXT:     /*TargetOpcode::G_AND*//*Label 1*/ 141, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-// CHECK-NEXT:     /*TargetOpcode::G_STORE*//*Label 2*/ 181, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-// CHECK-NEXT:     /*TargetOpcode::G_TRUNC*//*Label 3*/ 216, 0, 0, 0, 0,
-// CHECK-NEXT:     /*TargetOpcode::G_SEXT*//*Label 4*/ 231, 0,
-// CHECK-NEXT:     /*TargetOpcode::G_ZEXT*//*Label 5*/ 239,
-// CHECK-NEXT:     // Label 0: @112
-// CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 7*/ 133, // Rule ID 4 //
+// CHECK-NEXT:     GIM_SwitchOpcode, /*MI*/0, /*[*/19, 127, /*)*//*default:*//*Label 6*/ 268,
+// CHECK-NEXT:     /*TargetOpcode::COPY*//*Label 0*/ 113, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+// CHECK-NEXT:     /*TargetOpcode::G_AND*//*Label 1*/ 142, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+// CHECK-NEXT:     /*TargetOpcode::G_STORE*//*Label 2*/ 182, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+// CHECK-NEXT:     /*TargetOpcode::G_TRUNC*//*Label 3*/ 217, 0, 0, 0, 0,
+// CHECK-NEXT:     /*TargetOpcode::G_SEXT*//*Label 4*/ 232, 0,
+// CHECK-NEXT:     /*TargetOpcode::G_ZEXT*//*Label 5*/ 240,
+// CHECK-NEXT:     // Label 0: @113
+// CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 7*/ 134, // Rule ID 4 //
 // CHECK-NEXT:       GIM_CheckFeatures, GIFBS_HasAnswerToEverything,
 // CHECK-NEXT:       GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule3Enabled,
 // CHECK-NEXT:       // MIs[0] a
@@ -155,8 +155,8 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
 // CHECK-NEXT:       // Combiner Rule #3: InstTest1
 // CHECK-NEXT:       GIR_CustomAction, GICXXCustomAction_CombineApplyGICombiner0,
 // CHECK-NEXT:       GIR_Done,
-// CHECK-NEXT:     // Label 7: @133
-// CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 8*/ 140, // Rule ID 3 //
+// CHECK-NEXT:     // Label 7: @134
+// CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 8*/ 141, // Rule ID 3 //
 // CHECK-NEXT:       GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule2Enabled,
 // CHECK-NEXT:       // MIs[0] a
 // CHECK-NEXT:       // No operand predicates
@@ -165,10 +165,10 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
 // CHECK-NEXT:       // Combiner Rule #2: InstTest0
 // CHECK-NEXT:       GIR_CustomAction, GICXXCustomAction_CombineApplyGICombiner1,
 // CHECK-NEXT:       GIR_Done,
-// CHECK-NEXT:     // Label 8: @140
+// CHECK-NEXT:     // Label 8: @141
 // CHECK-NEXT:     GIM_Reject,
-// CHECK-NEXT:     // Label 1: @141
-// CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 9*/ 180, // Rule ID 6 //
+// CHECK-NEXT:     // Label 1: @142
+// CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 9*/ 181, // Rule ID 6 //
 // CHECK-NEXT:       GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule5Enabled,
 // CHECK-NEXT:       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 // CHECK-NEXT:       // MIs[0] dst
@@ -186,10 +186,10 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
 // CHECK-NEXT:       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // z
 // CHECK-NEXT:       GIR_EraseFromParent, /*InsnID*/0,
 // CHECK-NEXT:       GIR_Done,
-// CHECK-NEXT:     // Label 9: @180
+// CHECK-NEXT:     // Label 9: @181
 // CHECK-NEXT:     GIM_Reject,
-// CHECK-NEXT:     // Label 2: @181
-// CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 10*/ 215, // Rule ID 5 //
+// CHECK-NEXT:     // Label 2: @182
+// CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 10*/ 216, // Rule ID 5 //
 // CHECK-NEXT:       GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule4Enabled,
 // CHECK-NEXT:       // MIs[0] tmp
 // CHECK-NEXT:       GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
@@ -207,32 +207,32 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
 // CHECK-NEXT:       GIR_EraseFromParent, /*InsnID*/0,
 // CHECK-NEXT:       GIR_CustomAction, GICXXCustomAction_CombineApplyGICombiner2,
 // CHECK-NEXT:       GIR_Done,
-// CHECK-NEXT:     // Label 10: @215
+// CHECK-NEXT:     // Label 10: @216
 // CHECK-NEXT:     GIM_Reject,
-// CHECK-NEXT:     // Label 3: @216
-// CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 11*/ 223, // Rule ID 0 //
+// CHECK-NEXT:     // Label 3: @217
+// CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 11*/ 224, // Rule ID 0 //
 // CHECK-NEXT:       GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled,
 // CHECK-NEXT:       // Combiner Rule #0: WipOpcodeTest0; wip_match_opcode 'G_TRUNC'
 // CHECK-NEXT:       GIR_CustomAction, GICXXCustomAction_CombineApplyGICombiner0,
 // CHECK-NEXT:       GIR_Done,
-// CHECK-NEXT:     // Label 11: @223
-// CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 12*/ 230, // Rule ID 1 //
+// CHECK-NEXT:     // Label 11: @224
+// CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 12*/ 231, // Rule ID 1 //
 // CHECK-NEXT:       GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule1Enabled,
 // CHECK-NEXT:       // Combiner Rule #1: WipOpcodeTest1; wip_match_opcode 'G_TRUNC'
 // CHECK-NEXT:       GIR_CustomAction, GICXXCustomAction_CombineApplyGICombiner0,
 // CHECK-NEXT:       GIR_Done,
-// CHECK-NEXT:     // Label 12: @230
+// CHECK-NEXT:     // Label 12: @231
 // CHECK-NEXT:     GIM_Reject,
-// CHECK-NEXT:     // Label 4: @231
-// CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 13*/ 238, // Rule ID 2 //
+// CHECK-NEXT:     // Label 4: @232
+// CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 13*/ 239, // Rule ID 2 //
 // CHECK-NEXT:       GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule1Enabled,
 // CHECK-NEXT:       // Combiner Rule #1: WipOpcodeTest1; wip_match_opcode 'G_SEXT'
 // CHECK-NEXT:       GIR_CustomAction, GICXXCustomAction_CombineApplyGICombiner0,
 // CHECK-NEXT:       GIR_Done,
-// CHECK-NEXT:     // Label 13: @238
+// CHECK-NEXT:     // Label 13: @239
 // CHECK-NEXT:     GIM_Reject,
-// CHECK-NEXT:     // Label 5: @239
-// CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 14*/ 266, // Rule ID 7 //
+// CHECK-NEXT:     // Label 5: @240
+// CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 14*/ 267, // Rule ID 7 //
 // CHECK-NEXT:       GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule6Enabled,
 // CHECK-NEXT:       // MIs[0] dst
 // CHECK-NEXT:       // No operand predicates
@@ -247,10 +247,10 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
 // CHECK-NEXT:       GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
 // CHECK-NEXT:       GIR_EraseFromParent, /*InsnID*/0,
 // CHECK-NEXT:       GIR_Done,
-// CHECK-NEXT:     // Label 14: @266
+// CHECK-NEXT:     // Label 14: @267
 // CHECK-NEXT:     GIM_Reject,
-// CHECK-NEXT:     // Label 6: @267
+// CHECK-NEXT:     // Label 6: @268
 // CHECK-NEXT:     GIM_Reject,
-// CHECK-NEXT:     }; // Size: 2144 bytes
+// CHECK-NEXT:     }; // Size: 2152 bytes
 // CHECK-NEXT:   return MatchTable0;
 // CHECK-NEXT: }
diff --git a/llvm/test/TableGen/GlobalISelEmitter.td b/llvm/test/TableGen/GlobalISelEmitter.td
index d1e79604887e..562fdefcd3d6 100644
--- a/llvm/test/TableGen/GlobalISelEmitter.td
+++ b/llvm/test/TableGen/GlobalISelEmitter.td
@@ -517,7 +517,7 @@ def : Pat<(frag GPR32:$src1, complex:$src2, complex:$src3),
 // R00O-NEXT:  GIM_Reject,
 // R00O:       // Label [[DEFAULT_NUM]]: @[[DEFAULT]]
 // R00O-NEXT:  GIM_Reject,
-// R00O-NEXT:  }; // Size: 9880 bytes
+// R00O-NEXT:  }; // Size: 9888 bytes
 
 def INSNBOB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3, GPR32:$src4),
                  [(set GPR32:$dst,
-- 
GitLab


From 51e5f677c8d174e56bd0a312f71f248ba4cd0348 Mon Sep 17 00:00:00 2001
From: Rik Huijzer <github@huijzer.xyz>
Date: Mon, 11 Dec 2023 12:07:41 +0100
Subject: [PATCH 096/349] [mlir][vector] Fix crash on invalid `permutation_map`
 (#74925)

Without this patch, MLIR crashes with
```
Assertion failed: (getNumDims() == map.getNumResults() && "Number of results mismatch"), function compose, file AffineMap.cpp, line 537.
```
during parsing.
---
 mlir/lib/Dialect/Vector/IR/VectorOps.cpp | 10 ++++++++++
 mlir/test/Dialect/Vector/invalid.mlir    | 22 ++++++++++++++++++++++
 2 files changed, 32 insertions(+)

diff --git a/mlir/lib/Dialect/Vector/IR/VectorOps.cpp b/mlir/lib/Dialect/Vector/IR/VectorOps.cpp
index c462b23e1133..540959b486db 100644
--- a/mlir/lib/Dialect/Vector/IR/VectorOps.cpp
+++ b/mlir/lib/Dialect/Vector/IR/VectorOps.cpp
@@ -3815,6 +3815,11 @@ ParseResult TransferReadOp::parse(OpAsmParser &parser, OperationState &result) {
     if (llvm::dyn_cast<VectorType>(shapedType.getElementType()))
       return parser.emitError(
           maskInfo.location, "does not support masks with vector element type");
+    if (vectorType.getRank() != permMap.getNumResults()) {
+      return parser.emitError(typesLoc,
+                              "expected the same rank for the vector and the "
+                              "results of the permutation map");
+    }
     // Instead of adding the mask type as an op type, compute it based on the
     // vector type and the permutation map (to keep the type signature small).
     auto maskType = inferTransferOpMaskType(vectorType, permMap);
@@ -4181,6 +4186,11 @@ ParseResult TransferWriteOp::parse(OpAsmParser &parser,
     if (llvm::dyn_cast<VectorType>(shapedType.getElementType()))
       return parser.emitError(
           maskInfo.location, "does not support masks with vector element type");
+    if (vectorType.getRank() != permMap.getNumResults()) {
+      return parser.emitError(typesLoc,
+                              "expected the same rank for the vector and the "
+                              "results of the permutation map");
+    }
     auto maskType = inferTransferOpMaskType(vectorType, permMap);
     if (parser.resolveOperand(maskInfo, maskType, result.operands))
       return failure();
diff --git a/mlir/test/Dialect/Vector/invalid.mlir b/mlir/test/Dialect/Vector/invalid.mlir
index edb2689364a9..ad248d1e14e7 100644
--- a/mlir/test/Dialect/Vector/invalid.mlir
+++ b/mlir/test/Dialect/Vector/invalid.mlir
@@ -332,6 +332,28 @@ func.func @test_vector.transfer_read(%arg0: memref<?x?xf32>) {
 
 // -----
 
+#map1 = affine_map<(d0, d1, d2) -> (d0, 0, 0)>
+func.func @main(%m:  memref<1xi32>, %2: vector<1x32xi1>) -> vector<1x32xi32> {
+  %0 = arith.constant 1 : index
+  %1 = arith.constant 1 : i32
+  // expected-error@+1 {{expected the same rank for the vector and the results of the permutation map}}
+  %3 = vector.transfer_read %m[%0], %1, %2 { permutation_map = #map1 } : memref<1xi32>, vector<1x32xi32>
+  return %3 : vector<1x32xi32>
+}
+
+// -----
+
+#map1 = affine_map<(d0, d1, d2) -> (d0, 0, 0)>
+func.func @test_vector.transfer_write(%m:  memref<1xi32>, %2: vector<1x32xi32>) -> vector<1x32xi32> {
+  %0 = arith.constant 1 : index
+  %1 = arith.constant 1 : i32
+  // expected-error@+1 {{expected the same rank for the vector and the results of the permutation map}}
+  %3 = vector.transfer_write %2, %m[%0], %1 { permutation_map = #map1 } : vector<1x32xi32>, memref<1xi32>
+  return %3 : vector<1x32xi32>
+}
+
+// -----
+
 func.func @test_vector.transfer_read(%arg0: vector<4x3xf32>) {
   %c3 = arith.constant 3 : index
   %f0 = arith.constant 0.0 : f32
-- 
GitLab


From 21be9114ab78348cf0cdb59df90192a5a8d2b0e7 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Mon, 11 Dec 2023 11:05:21 +0000
Subject: [PATCH 097/349] [X86] evex-to-vex-compress.mir - strip trailing
 whitespace

---
 .../test/CodeGen/X86/evex-to-vex-compress.mir | 1576 ++++++++---------
 1 file changed, 788 insertions(+), 788 deletions(-)

diff --git a/llvm/test/CodeGen/X86/evex-to-vex-compress.mir b/llvm/test/CodeGen/X86/evex-to-vex-compress.mir
index 9c49ff8e573e..dc19b2aa8afa 100644
--- a/llvm/test/CodeGen/X86/evex-to-vex-compress.mir
+++ b/llvm/test/CodeGen/X86/evex-to-vex-compress.mir
@@ -4,8 +4,8 @@
 
 --- |
    define void @evex_z256_to_vex_test() { ret void }
-   define void @evex_z128_to_vex_test() { ret void }   
-   define void @evex_scalar_to_vex_test() { ret void }   
+   define void @evex_z128_to_vex_test() { ret void }
+   define void @evex_scalar_to_vex_test() { ret void }
    define void @evex_z256_to_evex_test() { ret void }
    define void @evex_z128_to_evex_test() { ret void }
    define void @evex_scalar_to_evex_test() { ret void }
@@ -14,141 +14,141 @@
   # CHECK-LABEL: name: evex_z256_to_vex_test
   # CHECK: bb.0:
 
-name: evex_z256_to_vex_test                    
-body: |                                        
-  bb.0:                                        
+name: evex_z256_to_vex_test
+body: |
+  bb.0:
   ; CHECK: VMOVAPDYmr                          $rdi, 1, $noreg, 0, $noreg, $ymm0
-  VMOVAPDZ256mr                                $rdi, 1, $noreg, 0, $noreg, $ymm0                        
+  VMOVAPDZ256mr                                $rdi, 1, $noreg, 0, $noreg, $ymm0
   ; CHECK: $ymm0 = VMOVAPDYrm                  $rip, 1, $noreg, 0, $noreg
   $ymm0 = VMOVAPDZ256rm                        $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VMOVAPDYrr                  $ymm0
-  $ymm0 = VMOVAPDZ256rr                        $ymm0                                          
+  $ymm0 = VMOVAPDZ256rr                        $ymm0
   ; CHECK: VMOVAPSYmr                          $rdi, 1, $noreg, 0, $noreg, $ymm0
-  VMOVAPSZ256mr                                $rdi, 1, $noreg, 0, $noreg, $ymm0                        
+  VMOVAPSZ256mr                                $rdi, 1, $noreg, 0, $noreg, $ymm0
   ; CHECK: $ymm0 = VMOVAPSYrm                  $rip, 1, $noreg, 0, $noreg
   $ymm0 = VMOVAPSZ256rm                        $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VMOVAPSYrr                  $ymm0
-  $ymm0 = VMOVAPSZ256rr                        $ymm0                                          
+  $ymm0 = VMOVAPSZ256rr                        $ymm0
   ; CHECK: $ymm0 = VMOVDDUPYrm                 $rip, 1, $noreg, 0, $noreg
   $ymm0 = VMOVDDUPZ256rm                       $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VMOVDDUPYrr                 $ymm0
-  $ymm0 = VMOVDDUPZ256rr                       $ymm0                                          
+  $ymm0 = VMOVDDUPZ256rr                       $ymm0
   ; CHECK: VMOVDQAYmr                          $rdi, 1, $noreg, 0, $noreg, $ymm0
-  VMOVDQA32Z256mr                              $rdi, 1, $noreg, 0, $noreg, $ymm0                        
+  VMOVDQA32Z256mr                              $rdi, 1, $noreg, 0, $noreg, $ymm0
   ; CHECK: $ymm0 = VMOVDQAYrm                  $rip, 1, $noreg, 0, $noreg
   $ymm0 = VMOVDQA32Z256rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VMOVDQAYrr                  $ymm0
-  $ymm0 = VMOVDQA32Z256rr                      $ymm0                                          
+  $ymm0 = VMOVDQA32Z256rr                      $ymm0
   ; CHECK: VMOVDQAYmr                          $rdi, 1, $noreg, 0, $noreg, $ymm0
-  VMOVDQA64Z256mr                              $rdi, 1, $noreg, 0, $noreg, $ymm0                        
+  VMOVDQA64Z256mr                              $rdi, 1, $noreg, 0, $noreg, $ymm0
   ; CHECK: $ymm0 = VMOVDQAYrm                  $rip, 1, $noreg, 0, $noreg
   $ymm0 = VMOVDQA64Z256rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VMOVDQAYrr                  $ymm0
-  $ymm0 = VMOVDQA64Z256rr                      $ymm0                                          
+  $ymm0 = VMOVDQA64Z256rr                      $ymm0
   ; CHECK: VMOVDQUYmr                          $rdi, 1, $noreg, 0, $noreg, $ymm0
-  VMOVDQU16Z256mr                              $rdi, 1, $noreg, 0, $noreg, $ymm0                        
+  VMOVDQU16Z256mr                              $rdi, 1, $noreg, 0, $noreg, $ymm0
   ; CHECK: $ymm0 = VMOVDQUYrm                  $rip, 1, $noreg, 0, $noreg
   $ymm0 = VMOVDQU16Z256rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VMOVDQUYrr                  $ymm0
-  $ymm0 = VMOVDQU16Z256rr                      $ymm0                                          
+  $ymm0 = VMOVDQU16Z256rr                      $ymm0
   ; CHECK: VMOVDQUYmr                          $rdi, 1, $noreg, 0, $noreg, $ymm0
-  VMOVDQU32Z256mr                              $rdi, 1, $noreg, 0, $noreg, $ymm0                        
+  VMOVDQU32Z256mr                              $rdi, 1, $noreg, 0, $noreg, $ymm0
   ; CHECK: $ymm0 = VMOVDQUYrm                  $rip, 1, $noreg, 0, $noreg
   $ymm0 = VMOVDQU32Z256rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VMOVDQUYrr                  $ymm0
-  $ymm0 = VMOVDQU32Z256rr                      $ymm0                                          
+  $ymm0 = VMOVDQU32Z256rr                      $ymm0
   ; CHECK: VMOVDQUYmr                          $rdi, 1, $noreg, 0, $noreg, $ymm0
-  VMOVDQU64Z256mr                              $rdi, 1, $noreg, 0, $noreg, $ymm0                        
+  VMOVDQU64Z256mr                              $rdi, 1, $noreg, 0, $noreg, $ymm0
   ; CHECK: $ymm0 = VMOVDQUYrm                  $rip, 1, $noreg, 0, $noreg
   $ymm0 = VMOVDQU64Z256rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VMOVDQUYrr                  $ymm0
-  $ymm0 = VMOVDQU64Z256rr                      $ymm0                                          
+  $ymm0 = VMOVDQU64Z256rr                      $ymm0
   ; CHECK: VMOVDQUYmr                          $rdi, 1, $noreg, 0, $noreg, $ymm0
-  VMOVDQU8Z256mr                               $rdi, 1, $noreg, 0, $noreg, $ymm0                        
+  VMOVDQU8Z256mr                               $rdi, 1, $noreg, 0, $noreg, $ymm0
   ; CHECK: $ymm0 = VMOVDQUYrm                  $rip, 1, $noreg, 0, $noreg
   $ymm0 = VMOVDQU8Z256rm                       $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VMOVDQUYrr                  $ymm0
-  $ymm0 = VMOVDQU8Z256rr                       $ymm0                                          
+  $ymm0 = VMOVDQU8Z256rr                       $ymm0
   ; CHECK: $ymm0 = VMOVNTDQAYrm                $rip, 1, $noreg, 0, $noreg
   $ymm0 = VMOVNTDQAZ256rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: VMOVNTDQYmr                         $rdi, 1, $noreg, 0, $noreg, $ymm0
-  VMOVNTDQZ256mr                               $rdi, 1, $noreg, 0, $noreg, $ymm0                        
+  VMOVNTDQZ256mr                               $rdi, 1, $noreg, 0, $noreg, $ymm0
   ; CHECK: VMOVNTPDYmr                         $rdi, 1, $noreg, 0, $noreg, $ymm0
-  VMOVNTPDZ256mr                               $rdi, 1, $noreg, 0, $noreg, $ymm0                        
+  VMOVNTPDZ256mr                               $rdi, 1, $noreg, 0, $noreg, $ymm0
   ; CHECK: VMOVNTPSYmr                         $rdi, 1, $noreg, 0, $noreg, $ymm0
   VMOVNTPSZ256mr                               $rdi, 1, $noreg, 0, $noreg, $ymm0
   ; CHECK: $ymm0 = VMOVSHDUPYrm                $rip, 1, $noreg, 0, $noreg
   $ymm0 = VMOVSHDUPZ256rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VMOVSHDUPYrr                $ymm0
-  $ymm0 = VMOVSHDUPZ256rr                      $ymm0                                          
+  $ymm0 = VMOVSHDUPZ256rr                      $ymm0
   ; CHECK: $ymm0 = VMOVSLDUPYrm                $rip, 1, $noreg, 0, $noreg
   $ymm0 = VMOVSLDUPZ256rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VMOVSLDUPYrr                $ymm0
-  $ymm0 = VMOVSLDUPZ256rr                      $ymm0                                          
+  $ymm0 = VMOVSLDUPZ256rr                      $ymm0
   ; CHECK: VMOVUPDYmr                          $rdi, 1, $noreg, 0, $noreg, $ymm0
-  VMOVUPDZ256mr                                $rdi, 1, $noreg, 0, $noreg, $ymm0                        
+  VMOVUPDZ256mr                                $rdi, 1, $noreg, 0, $noreg, $ymm0
   ; CHECK: $ymm0 = VMOVUPDYrm                  $rip, 1, $noreg, 0, $noreg
   $ymm0 = VMOVUPDZ256rm                        $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VMOVUPDYrr                  $ymm0
-  $ymm0 = VMOVUPDZ256rr                        $ymm0                                          
+  $ymm0 = VMOVUPDZ256rr                        $ymm0
   ; CHECK: VMOVUPSYmr                          $rdi, 1, $noreg, 0, $noreg, $ymm0
-  VMOVUPSZ256mr                                $rdi, 1, $noreg, 0, $noreg, $ymm0                                              
+  VMOVUPSZ256mr                                $rdi, 1, $noreg, 0, $noreg, $ymm0
   ; CHECK: $ymm0 = VPANDYrm                    $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPANDDZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $ymm0 = VPANDYrr                    $ymm0, $ymm1  
-  $ymm0 = VPANDDZ256rr                         $ymm0, $ymm1                                   
+  ; CHECK: $ymm0 = VPANDYrr                    $ymm0, $ymm1
+  $ymm0 = VPANDDZ256rr                         $ymm0, $ymm1
   ; CHECK: $ymm0 = VPANDYrm                    $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPANDQZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPANDYrr                    $ymm0, $ymm1
-  $ymm0 = VPANDQZ256rr                         $ymm0, $ymm1                                   
+  $ymm0 = VPANDQZ256rr                         $ymm0, $ymm1
   ; CHECK: $ymm0 = VPANDNYrm                    $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPANDNDZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $ymm0 = VPANDNYrr                    $ymm0, $ymm1  
-  $ymm0 = VPANDNDZ256rr                         $ymm0, $ymm1                                   
+  ; CHECK: $ymm0 = VPANDNYrr                    $ymm0, $ymm1
+  $ymm0 = VPANDNDZ256rr                         $ymm0, $ymm1
   ; CHECK: $ymm0 = VPANDNYrm                    $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPANDNQZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPANDNYrr                    $ymm0, $ymm1
-  $ymm0 = VPANDNQZ256rr                         $ymm0, $ymm1                                   
+  $ymm0 = VPANDNQZ256rr                         $ymm0, $ymm1
   ; CHECK: $ymm0 = VPAVGBYrm                   $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPAVGBZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPAVGBYrr                   $ymm0, $ymm1
-  $ymm0 = VPAVGBZ256rr                         $ymm0, $ymm1                                   
+  $ymm0 = VPAVGBZ256rr                         $ymm0, $ymm1
   ; CHECK: $ymm0 = VPAVGWYrm                   $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPAVGWZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPAVGWYrr                   $ymm0, $ymm1
-  $ymm0 = VPAVGWZ256rr                         $ymm0, $ymm1                                   
+  $ymm0 = VPAVGWZ256rr                         $ymm0, $ymm1
   ; CHECK: $ymm0 = VPADDBYrm                   $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPADDBZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $ymm0 = VPADDBYrr                   $ymm0, $ymm1  
-  $ymm0 = VPADDBZ256rr                         $ymm0, $ymm1                                   
+  ; CHECK: $ymm0 = VPADDBYrr                   $ymm0, $ymm1
+  $ymm0 = VPADDBZ256rr                         $ymm0, $ymm1
   ; CHECK: $ymm0 = VPADDDYrm                   $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPADDDZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPADDDYrr                   $ymm0, $ymm1
-  $ymm0 = VPADDDZ256rr                         $ymm0, $ymm1                                   
+  $ymm0 = VPADDDZ256rr                         $ymm0, $ymm1
   ; CHECK: $ymm0 = VPADDQYrm                   $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPADDQZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPADDQYrr                   $ymm0, $ymm1
-  $ymm0 = VPADDQZ256rr                         $ymm0, $ymm1                                   
+  $ymm0 = VPADDQZ256rr                         $ymm0, $ymm1
   ; CHECK: $ymm0 = VPADDSBYrm                  $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPADDSBZ256rm                        $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPADDSBYrr                  $ymm0, $ymm1
-  $ymm0 = VPADDSBZ256rr                        $ymm0, $ymm1                                   
+  $ymm0 = VPADDSBZ256rr                        $ymm0, $ymm1
   ; CHECK: $ymm0 = VPADDSWYrm                  $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPADDSWZ256rm                        $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPADDSWYrr                  $ymm0, $ymm1
-  $ymm0 = VPADDSWZ256rr                        $ymm0, $ymm1                                   
+  $ymm0 = VPADDSWZ256rr                        $ymm0, $ymm1
   ; CHECK: $ymm0 = VPADDUSBYrm                 $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPADDUSBZ256rm                       $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPADDUSBYrr                 $ymm0, $ymm1
-  $ymm0 = VPADDUSBZ256rr                       $ymm0, $ymm1                                   
+  $ymm0 = VPADDUSBZ256rr                       $ymm0, $ymm1
   ; CHECK: $ymm0 = VPADDUSWYrm                 $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPADDUSWZ256rm                       $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPADDUSWYrr                 $ymm0, $ymm1
-  $ymm0 = VPADDUSWZ256rr                       $ymm0, $ymm1                                   
+  $ymm0 = VPADDUSWZ256rr                       $ymm0, $ymm1
   ; CHECK: $ymm0 = VPADDWYrm                   $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPADDWZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPADDWYrr                   $ymm0, $ymm1
-  $ymm0 = VPADDWZ256rr                         $ymm0, $ymm1                                   
+  $ymm0 = VPADDWZ256rr                         $ymm0, $ymm1
   ; CHECK: $ymm0 = VMULPDYrm                   $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   $ymm0 = VMULPDZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $ymm0 = VMULPDYrr                   $ymm0, $ymm1, implicit $mxcsr
@@ -160,143 +160,143 @@ body: |
   ; CHECK: $ymm0 = VORPDYrm                    $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VORPDZ256rm                          $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VORPDYrr                    $ymm0, $ymm1
-  $ymm0 = VORPDZ256rr                          $ymm0, $ymm1                                   
+  $ymm0 = VORPDZ256rr                          $ymm0, $ymm1
   ; CHECK: $ymm0 = VORPSYrm                    $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VORPSZ256rm                          $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VORPSYrr                    $ymm0, $ymm1
-  $ymm0 = VORPSZ256rr                          $ymm0, $ymm1                                   
+  $ymm0 = VORPSZ256rr                          $ymm0, $ymm1
   ; CHECK: $ymm0 = VPMADDUBSWYrm               $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMADDUBSWZ256rm                     $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMADDUBSWYrr               $ymm0, $ymm1
-  $ymm0 = VPMADDUBSWZ256rr                     $ymm0, $ymm1                                   
+  $ymm0 = VPMADDUBSWZ256rr                     $ymm0, $ymm1
   ; CHECK: $ymm0 = VPMADDWDYrm                 $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMADDWDZ256rm                       $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMADDWDYrr                 $ymm0, $ymm1
-  $ymm0 = VPMADDWDZ256rr                       $ymm0, $ymm1                                   
+  $ymm0 = VPMADDWDZ256rr                       $ymm0, $ymm1
   ; CHECK: $ymm0 = VPMAXSBYrm                  $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMAXSBZ256rm                        $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMAXSBYrr                  $ymm0, $ymm1
-  $ymm0 = VPMAXSBZ256rr                        $ymm0, $ymm1                                   
+  $ymm0 = VPMAXSBZ256rr                        $ymm0, $ymm1
   ; CHECK: $ymm0 = VPMAXSDYrm                  $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMAXSDZ256rm                        $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMAXSDYrr                  $ymm0, $ymm1
-  $ymm0 = VPMAXSDZ256rr                        $ymm0, $ymm1                                   
+  $ymm0 = VPMAXSDZ256rr                        $ymm0, $ymm1
   ; CHECK: $ymm0 = VPMAXSWYrm                  $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMAXSWZ256rm                        $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMAXSWYrr                  $ymm0, $ymm1
-  $ymm0 = VPMAXSWZ256rr                        $ymm0, $ymm1                                   
+  $ymm0 = VPMAXSWZ256rr                        $ymm0, $ymm1
   ; CHECK: $ymm0 = VPMAXUBYrm                  $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMAXUBZ256rm                        $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMAXUBYrr                  $ymm0, $ymm1
-  $ymm0 = VPMAXUBZ256rr                        $ymm0, $ymm1                                   
+  $ymm0 = VPMAXUBZ256rr                        $ymm0, $ymm1
   ; CHECK: $ymm0 = VPMAXUDYrm                  $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMAXUDZ256rm                        $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMAXUDYrr                  $ymm0, $ymm1
-  $ymm0 = VPMAXUDZ256rr                        $ymm0, $ymm1                                   
+  $ymm0 = VPMAXUDZ256rr                        $ymm0, $ymm1
   ; CHECK: $ymm0 = VPMAXUWYrm                  $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMAXUWZ256rm                        $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMAXUWYrr                  $ymm0, $ymm1
-  $ymm0 = VPMAXUWZ256rr                        $ymm0, $ymm1                                   
+  $ymm0 = VPMAXUWZ256rr                        $ymm0, $ymm1
   ; CHECK: $ymm0 = VPMINSBYrm                  $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMINSBZ256rm                        $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMINSBYrr                  $ymm0, $ymm1
-  $ymm0 = VPMINSBZ256rr                        $ymm0, $ymm1                                   
+  $ymm0 = VPMINSBZ256rr                        $ymm0, $ymm1
   ; CHECK: $ymm0 = VPMINSDYrm                  $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMINSDZ256rm                        $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMINSDYrr                  $ymm0, $ymm1
-  $ymm0 = VPMINSDZ256rr                        $ymm0, $ymm1                                   
+  $ymm0 = VPMINSDZ256rr                        $ymm0, $ymm1
   ; CHECK: $ymm0 = VPMINSWYrm                  $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMINSWZ256rm                        $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMINSWYrr                  $ymm0, $ymm1
-  $ymm0 = VPMINSWZ256rr                        $ymm0, $ymm1                                   
+  $ymm0 = VPMINSWZ256rr                        $ymm0, $ymm1
   ; CHECK: $ymm0 = VPMINUBYrm                  $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMINUBZ256rm                        $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMINUBYrr                  $ymm0, $ymm1
-  $ymm0 = VPMINUBZ256rr                        $ymm0, $ymm1                                   
+  $ymm0 = VPMINUBZ256rr                        $ymm0, $ymm1
   ; CHECK: $ymm0 = VPMINUDYrm                  $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMINUDZ256rm                        $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMINUDYrr                  $ymm0, $ymm1
-  $ymm0 = VPMINUDZ256rr                        $ymm0, $ymm1                                   
+  $ymm0 = VPMINUDZ256rr                        $ymm0, $ymm1
   ; CHECK: $ymm0 = VPMINUWYrm                  $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMINUWZ256rm                        $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMINUWYrr                  $ymm0, $ymm1
-  $ymm0 = VPMINUWZ256rr                        $ymm0, $ymm1                                   
+  $ymm0 = VPMINUWZ256rr                        $ymm0, $ymm1
   ; CHECK: $ymm0 = VPMULDQYrm                  $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMULDQZ256rm                        $ymm0, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $ymm0 = VPMULDQYrr                  $ymm0, $ymm1  
-  $ymm0 = VPMULDQZ256rr                        $ymm0, $ymm1                                   
+  ; CHECK: $ymm0 = VPMULDQYrr                  $ymm0, $ymm1
+  $ymm0 = VPMULDQZ256rr                        $ymm0, $ymm1
   ; CHECK: $ymm0 = VPMULHRSWYrm                $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMULHRSWZ256rm                      $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMULHRSWYrr                $ymm0, $ymm1
-  $ymm0 = VPMULHRSWZ256rr                      $ymm0, $ymm1                                   
+  $ymm0 = VPMULHRSWZ256rr                      $ymm0, $ymm1
   ; CHECK: $ymm0 = VPMULHUWYrm                 $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMULHUWZ256rm                       $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMULHUWYrr                 $ymm0, $ymm1
-  $ymm0 = VPMULHUWZ256rr                       $ymm0, $ymm1                                   
+  $ymm0 = VPMULHUWZ256rr                       $ymm0, $ymm1
   ; CHECK: $ymm0 = VPMULHWYrm                  $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMULHWZ256rm                        $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMULHWYrr                  $ymm0, $ymm1
-  $ymm0 = VPMULHWZ256rr                        $ymm0, $ymm1                                   
+  $ymm0 = VPMULHWZ256rr                        $ymm0, $ymm1
   ; CHECK: $ymm0 = VPMULLDYrm                  $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMULLDZ256rm                        $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMULLDYrr                  $ymm0, $ymm1
-  $ymm0 = VPMULLDZ256rr                        $ymm0, $ymm1                                   
+  $ymm0 = VPMULLDZ256rr                        $ymm0, $ymm1
   ; CHECK: $ymm0 = VPMULLWYrm                  $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMULLWZ256rm                        $ymm0, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $ymm0 = VPMULLWYrr                  $ymm0, $ymm1  
-  $ymm0 = VPMULLWZ256rr                        $ymm0, $ymm1                                   
+  ; CHECK: $ymm0 = VPMULLWYrr                  $ymm0, $ymm1
+  $ymm0 = VPMULLWZ256rr                        $ymm0, $ymm1
   ; CHECK: $ymm0 = VPMULUDQYrm                 $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMULUDQZ256rm                       $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMULUDQYrr                 $ymm0, $ymm1
-  $ymm0 = VPMULUDQZ256rr                       $ymm0, $ymm1                                   
+  $ymm0 = VPMULUDQZ256rr                       $ymm0, $ymm1
   ; CHECK: $ymm0 = VPORYrm                     $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPORDZ256rm                          $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPORYrr                     $ymm0, $ymm1
-  $ymm0 = VPORDZ256rr                          $ymm0, $ymm1                                   
+  $ymm0 = VPORDZ256rr                          $ymm0, $ymm1
   ; CHECK: $ymm0 = VPORYrm                     $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPORQZ256rm                          $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPORYrr                     $ymm0, $ymm1
-  $ymm0 = VPORQZ256rr                          $ymm0, $ymm1                                   
+  $ymm0 = VPORQZ256rr                          $ymm0, $ymm1
   ; CHECK: $ymm0 = VPSUBBYrm                   $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPSUBBZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPSUBBYrr                   $ymm0, $ymm1
-  $ymm0 = VPSUBBZ256rr                         $ymm0, $ymm1                                   
+  $ymm0 = VPSUBBZ256rr                         $ymm0, $ymm1
   ; CHECK: $ymm0 = VPSUBDYrm                   $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPSUBDZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPSUBDYrr                   $ymm0, $ymm1
-  $ymm0 = VPSUBDZ256rr                         $ymm0, $ymm1                                   
+  $ymm0 = VPSUBDZ256rr                         $ymm0, $ymm1
   ; CHECK: $ymm0 = VPSUBQYrm                   $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPSUBQZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPSUBQYrr                   $ymm0, $ymm1
-  $ymm0 = VPSUBQZ256rr                         $ymm0, $ymm1                                   
+  $ymm0 = VPSUBQZ256rr                         $ymm0, $ymm1
   ; CHECK: $ymm0 = VPSUBSBYrm                  $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPSUBSBZ256rm                        $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPSUBSBYrr                  $ymm0, $ymm1
-  $ymm0 = VPSUBSBZ256rr                        $ymm0, $ymm1                                   
+  $ymm0 = VPSUBSBZ256rr                        $ymm0, $ymm1
   ; CHECK: $ymm0 = VPSUBSWYrm                  $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPSUBSWZ256rm                        $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPSUBSWYrr                  $ymm0, $ymm1
-  $ymm0 = VPSUBSWZ256rr                        $ymm0, $ymm1                                   
+  $ymm0 = VPSUBSWZ256rr                        $ymm0, $ymm1
   ; CHECK: $ymm0 = VPSUBUSBYrm                 $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPSUBUSBZ256rm                       $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPSUBUSBYrr                 $ymm0, $ymm1
-  $ymm0 = VPSUBUSBZ256rr                       $ymm0, $ymm1                                   
+  $ymm0 = VPSUBUSBZ256rr                       $ymm0, $ymm1
   ; CHECK: $ymm0 = VPSUBUSWYrm                 $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPSUBUSWZ256rm                       $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPSUBUSWYrr                 $ymm0, $ymm1
-  $ymm0 = VPSUBUSWZ256rr                       $ymm0, $ymm1                                   
+  $ymm0 = VPSUBUSWZ256rr                       $ymm0, $ymm1
   ; CHECK: $ymm0 = VPSUBWYrm                   $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPSUBWZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPSUBWYrr                   $ymm0, $ymm1
-  $ymm0 = VPSUBWZ256rr                         $ymm0, $ymm1                                   
+  $ymm0 = VPSUBWZ256rr                         $ymm0, $ymm1
   ; CHECK: $ymm0 = VPXORYrm                    $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPXORDZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPXORYrr                    $ymm0, $ymm1
-  $ymm0 = VPXORDZ256rr                         $ymm0, $ymm1                                   
+  $ymm0 = VPXORDZ256rr                         $ymm0, $ymm1
   ; CHECK: $ymm0 = VPXORYrm                    $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPXORQZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $ymm0 = VPXORYrr                    $ymm0, $ymm1  
-  $ymm0 = VPXORQZ256rr                         $ymm0, $ymm1                                   
+  ; CHECK: $ymm0 = VPXORYrr                    $ymm0, $ymm1
+  $ymm0 = VPXORQZ256rr                         $ymm0, $ymm1
   ; CHECK: $ymm0 = VADDPDYrm                   $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   $ymm0 = VADDPDZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $ymm0 = VADDPDYrr                   $ymm0, $ymm1, implicit $mxcsr
@@ -308,19 +308,19 @@ body: |
   ; CHECK: $ymm0 = VANDNPDYrm                  $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VANDNPDZ256rm                        $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VANDNPDYrr                  $ymm0, $ymm1
-  $ymm0 = VANDNPDZ256rr                        $ymm0, $ymm1                                   
+  $ymm0 = VANDNPDZ256rr                        $ymm0, $ymm1
   ; CHECK: $ymm0 = VANDNPSYrm                  $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VANDNPSZ256rm                        $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VANDNPSYrr                  $ymm0, $ymm1
-  $ymm0 = VANDNPSZ256rr                        $ymm0, $ymm1                                   
+  $ymm0 = VANDNPSZ256rr                        $ymm0, $ymm1
   ; CHECK: $ymm0 = VANDPDYrm                   $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VANDPDZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VANDPDYrr                   $ymm0, $ymm1
-  $ymm0 = VANDPDZ256rr                         $ymm0, $ymm1                                   
+  $ymm0 = VANDPDZ256rr                         $ymm0, $ymm1
   ; CHECK: $ymm0 = VANDPSYrm                   $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VANDPSZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VANDPSYrr                   $ymm0, $ymm1
-  $ymm0 = VANDPSZ256rr                         $ymm0, $ymm1                                   
+  $ymm0 = VANDPSZ256rr                         $ymm0, $ymm1
   ; CHECK: $ymm0 = VDIVPDYrm                   $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   $ymm0 = VDIVPDZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $ymm0 = VDIVPDYrr                   $ymm0, $ymm1, implicit $mxcsr
@@ -364,43 +364,43 @@ body: |
   ; CHECK: $ymm0 = VXORPDYrm                   $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VXORPDZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VXORPDYrr                   $ymm0, $ymm1
-  $ymm0 = VXORPDZ256rr                         $ymm0, $ymm1                                   
+  $ymm0 = VXORPDZ256rr                         $ymm0, $ymm1
   ; CHECK: $ymm0 = VXORPSYrm                   $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VXORPSZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VXORPSYrr                   $ymm0, $ymm1
-  $ymm0 = VXORPSZ256rr                         $ymm0, $ymm1                                   
+  $ymm0 = VXORPSZ256rr                         $ymm0, $ymm1
   ; CHECK: $ymm0 = VPACKSSDWYrm                $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPACKSSDWZ256rm                      $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPACKSSDWYrr                $ymm0, $ymm1
-  $ymm0 = VPACKSSDWZ256rr                      $ymm0, $ymm1                                   
+  $ymm0 = VPACKSSDWZ256rr                      $ymm0, $ymm1
   ; CHECK: $ymm0 = VPACKSSWBYrm                $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPACKSSWBZ256rm                      $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPACKSSWBYrr                $ymm0, $ymm1
-  $ymm0 = VPACKSSWBZ256rr                      $ymm0, $ymm1                                   
+  $ymm0 = VPACKSSWBZ256rr                      $ymm0, $ymm1
   ; CHECK: $ymm0 = VPACKUSDWYrm                $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPACKUSDWZ256rm                      $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPACKUSDWYrr                $ymm0, $ymm1
-  $ymm0 = VPACKUSDWZ256rr                      $ymm0, $ymm1                                   
+  $ymm0 = VPACKUSDWZ256rr                      $ymm0, $ymm1
   ; CHECK: $ymm0 = VPACKUSWBYrm                $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPACKUSWBZ256rm                      $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPACKUSWBYrr                $ymm0, $ymm1
-  $ymm0 = VPACKUSWBZ256rr                      $ymm0, $ymm1                                   
+  $ymm0 = VPACKUSWBZ256rr                      $ymm0, $ymm1
   ; CHECK: $ymm0 = VUNPCKHPDYrm                $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VUNPCKHPDZ256rm                      $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VUNPCKHPDYrr                $ymm0, $ymm1
-  $ymm0 = VUNPCKHPDZ256rr                      $ymm0, $ymm1                                   
+  $ymm0 = VUNPCKHPDZ256rr                      $ymm0, $ymm1
   ; CHECK: $ymm0 = VUNPCKHPSYrm                $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VUNPCKHPSZ256rm                      $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VUNPCKHPSYrr                $ymm0, $ymm1
-  $ymm0 = VUNPCKHPSZ256rr                      $ymm0, $ymm1                                   
+  $ymm0 = VUNPCKHPSZ256rr                      $ymm0, $ymm1
   ; CHECK: $ymm0 = VUNPCKLPDYrm                $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VUNPCKLPDZ256rm                      $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VUNPCKLPDYrr                $ymm0, $ymm1
-  $ymm0 = VUNPCKLPDZ256rr                      $ymm0, $ymm1                                   
+  $ymm0 = VUNPCKLPDZ256rr                      $ymm0, $ymm1
   ; CHECK: $ymm0 = VUNPCKLPSYrm                $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VUNPCKLPSZ256rm                      $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VUNPCKLPSYrr                $ymm0, $ymm1
-  $ymm0 = VUNPCKLPSZ256rr                      $ymm0, $ymm1                                   
+  $ymm0 = VUNPCKLPSZ256rr                      $ymm0, $ymm1
   ; CHECK: $ymm0 = VSUBPDYrm                   $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   $ymm0 = VSUBPDZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $ymm0 = VSUBPDYrr                   $ymm0, $ymm1, implicit $mxcsr
@@ -412,35 +412,35 @@ body: |
   ; CHECK: $ymm0 = VPUNPCKHBWYrm               $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPUNPCKHBWZ256rm                     $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPUNPCKHBWYrr               $ymm0, $ymm1
-  $ymm0 = VPUNPCKHBWZ256rr                     $ymm0, $ymm1                                   
+  $ymm0 = VPUNPCKHBWZ256rr                     $ymm0, $ymm1
   ; CHECK: $ymm0 = VPUNPCKHDQYrm               $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPUNPCKHDQZ256rm                     $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPUNPCKHDQYrr               $ymm0, $ymm1
-  $ymm0 = VPUNPCKHDQZ256rr                     $ymm0, $ymm1                                   
+  $ymm0 = VPUNPCKHDQZ256rr                     $ymm0, $ymm1
   ; CHECK: $ymm0 = VPUNPCKHQDQYrm              $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPUNPCKHQDQZ256rm                    $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPUNPCKHQDQYrr              $ymm0, $ymm1
-  $ymm0 = VPUNPCKHQDQZ256rr                    $ymm0, $ymm1                                   
+  $ymm0 = VPUNPCKHQDQZ256rr                    $ymm0, $ymm1
   ; CHECK: $ymm0 = VPUNPCKHWDYrm               $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPUNPCKHWDZ256rm                     $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPUNPCKHWDYrr               $ymm0, $ymm1
-  $ymm0 = VPUNPCKHWDZ256rr                     $ymm0, $ymm1                                   
+  $ymm0 = VPUNPCKHWDZ256rr                     $ymm0, $ymm1
   ; CHECK: $ymm0 = VPUNPCKLBWYrm               $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPUNPCKLBWZ256rm                     $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPUNPCKLBWYrr               $ymm0, $ymm1
-  $ymm0 = VPUNPCKLBWZ256rr                     $ymm0, $ymm1                                   
+  $ymm0 = VPUNPCKLBWZ256rr                     $ymm0, $ymm1
   ; CHECK: $ymm0 = VPUNPCKLDQYrm               $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPUNPCKLDQZ256rm                     $ymm0, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $ymm0 = VPUNPCKLDQYrr               $ymm0, $ymm1 
-  $ymm0 = VPUNPCKLDQZ256rr                     $ymm0, $ymm1                                   
+  ; CHECK: $ymm0 = VPUNPCKLDQYrr               $ymm0, $ymm1
+  $ymm0 = VPUNPCKLDQZ256rr                     $ymm0, $ymm1
   ; CHECK: $ymm0 = VPUNPCKLQDQYrm              $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPUNPCKLQDQZ256rm                    $ymm0, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $ymm0 = VPUNPCKLQDQYrr              $ymm0, $ymm1 
-  $ymm0 = VPUNPCKLQDQZ256rr                    $ymm0, $ymm1                                   
+  ; CHECK: $ymm0 = VPUNPCKLQDQYrr              $ymm0, $ymm1
+  $ymm0 = VPUNPCKLQDQZ256rr                    $ymm0, $ymm1
   ; CHECK: $ymm0 = VPUNPCKLWDYrm               $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPUNPCKLWDZ256rm                     $ymm0, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $ymm0 = VPUNPCKLWDYrr               $ymm0, $ymm1                               
-  $ymm0 = VPUNPCKLWDZ256rr                     $ymm0, $ymm1                                                
+  ; CHECK: $ymm0 = VPUNPCKLWDYrr               $ymm0, $ymm1
+  $ymm0 = VPUNPCKLWDZ256rr                     $ymm0, $ymm1
   ; CHECK: $ymm0 = VFMADD132PDYm               $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
   $ymm0 = VFMADD132PDZ256m                     $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $ymm0 = VFMADD132PDYr               $ymm0, $ymm1, $ymm2, implicit $mxcsr
@@ -586,97 +586,97 @@ body: |
   ; CHECK: $ymm0 = VFNMSUB231PSYr              $ymm0, $ymm1, $ymm2, implicit $mxcsr
   $ymm0 = VFNMSUB231PSZ256r                    $ymm0, $ymm1, $ymm2, implicit $mxcsr
   ; CHECK: $ymm0 = VPSRADYri                   $ymm0, 7
-  $ymm0 = VPSRADZ256ri                         $ymm0, 7                                       
+  $ymm0 = VPSRADZ256ri                         $ymm0, 7
   ; CHECK: $ymm0 = VPSRADYrm                   $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPSRADZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPSRADYrr                   $ymm0, $xmm1
-  $ymm0 = VPSRADZ256rr                         $ymm0, $xmm1                                   
+  $ymm0 = VPSRADZ256rr                         $ymm0, $xmm1
   ; CHECK: $ymm0 = VPSRAVDYrm                  $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPSRAVDZ256rm                        $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPSRAVDYrr                  $ymm0, $ymm1
-  $ymm0 = VPSRAVDZ256rr                        $ymm0, $ymm1                                   
+  $ymm0 = VPSRAVDZ256rr                        $ymm0, $ymm1
   ; CHECK: $ymm0 = VPSRAWYri                   $ymm0, 7
-  $ymm0 = VPSRAWZ256ri                         $ymm0, 7                                       
+  $ymm0 = VPSRAWZ256ri                         $ymm0, 7
   ; CHECK: $ymm0 = VPSRAWYrm                   $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPSRAWZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPSRAWYrr                   $ymm0, $xmm1
-  $ymm0 = VPSRAWZ256rr                         $ymm0, $xmm1                                   
+  $ymm0 = VPSRAWZ256rr                         $ymm0, $xmm1
   ; CHECK: $ymm0 = VPSRLDQYri                  $ymm0, 7
   $ymm0 = VPSRLDQZ256ri                        $ymm0, 7
   ; CHECK: $ymm0 = VPSRLDYri                   $ymm0, 7
-  $ymm0 = VPSRLDZ256ri                         $ymm0, 7                                       
+  $ymm0 = VPSRLDZ256ri                         $ymm0, 7
   ; CHECK: $ymm0 = VPSRLDYrm                   $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPSRLDZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPSRLDYrr                   $ymm0, $xmm1
-  $ymm0 = VPSRLDZ256rr                         $ymm0, $xmm1                                   
+  $ymm0 = VPSRLDZ256rr                         $ymm0, $xmm1
   ; CHECK: $ymm0 = VPSRLQYri                   $ymm0, 7
-  $ymm0 = VPSRLQZ256ri                         $ymm0, 7                                       
+  $ymm0 = VPSRLQZ256ri                         $ymm0, 7
   ; CHECK: $ymm0 = VPSRLQYrm                   $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPSRLQZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPSRLQYrr                   $ymm0, $xmm1
-  $ymm0 = VPSRLQZ256rr                         $ymm0, $xmm1                                   
+  $ymm0 = VPSRLQZ256rr                         $ymm0, $xmm1
   ; CHECK: $ymm0 = VPSRLVDYrm                  $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPSRLVDZ256rm                        $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPSRLVDYrr                  $ymm0, $ymm1
-  $ymm0 = VPSRLVDZ256rr                        $ymm0, $ymm1                                   
+  $ymm0 = VPSRLVDZ256rr                        $ymm0, $ymm1
   ; CHECK: $ymm0 = VPSRLVQYrm                  $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPSRLVQZ256rm                        $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPSRLVQYrr                  $ymm0, $ymm1
-  $ymm0 = VPSRLVQZ256rr                        $ymm0, $ymm1                                   
+  $ymm0 = VPSRLVQZ256rr                        $ymm0, $ymm1
   ; CHECK: $ymm0 = VPSRLWYri                   $ymm0, 7
-  $ymm0 = VPSRLWZ256ri                         $ymm0, 7                                       
+  $ymm0 = VPSRLWZ256ri                         $ymm0, 7
   ; CHECK: $ymm0 = VPSRLWYrm                   $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPSRLWZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $ymm0 = VPSRLWYrr                   $ymm0, $xmm1                               
-  $ymm0 = VPSRLWZ256rr                         $ymm0, $xmm1                                               
+  ; CHECK: $ymm0 = VPSRLWYrr                   $ymm0, $xmm1
+  $ymm0 = VPSRLWZ256rr                         $ymm0, $xmm1
   ; CHECK: $ymm0 = VPMOVSXBDYrm                $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMOVSXBDZ256rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMOVSXBDYrr                $xmm0
-  $ymm0 = VPMOVSXBDZ256rr                      $xmm0                                          
+  $ymm0 = VPMOVSXBDZ256rr                      $xmm0
   ; CHECK: $ymm0 = VPMOVSXBQYrm                $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMOVSXBQZ256rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMOVSXBQYrr                $xmm0
-  $ymm0 = VPMOVSXBQZ256rr                      $xmm0                                          
+  $ymm0 = VPMOVSXBQZ256rr                      $xmm0
   ; CHECK: $ymm0 = VPMOVSXBWYrm                $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMOVSXBWZ256rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMOVSXBWYrr                $xmm0
-  $ymm0 = VPMOVSXBWZ256rr                      $xmm0                                          
+  $ymm0 = VPMOVSXBWZ256rr                      $xmm0
   ; CHECK: $ymm0 = VPMOVSXDQYrm                $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMOVSXDQZ256rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMOVSXDQYrr                $xmm0
-  $ymm0 = VPMOVSXDQZ256rr                      $xmm0                                          
+  $ymm0 = VPMOVSXDQZ256rr                      $xmm0
   ; CHECK: $ymm0 = VPMOVSXWDYrm                $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMOVSXWDZ256rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMOVSXWDYrr                $xmm0
-  $ymm0 = VPMOVSXWDZ256rr                      $xmm0                                          
+  $ymm0 = VPMOVSXWDZ256rr                      $xmm0
   ; CHECK: $ymm0 = VPMOVSXWQYrm                $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMOVSXWQZ256rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMOVSXWQYrr                $xmm0
-  $ymm0 = VPMOVSXWQZ256rr                      $xmm0                                          
+  $ymm0 = VPMOVSXWQZ256rr                      $xmm0
   ; CHECK: $ymm0 = VPMOVZXBDYrm                $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMOVZXBDZ256rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMOVZXBDYrr                $xmm0
-  $ymm0 = VPMOVZXBDZ256rr                      $xmm0                                          
+  $ymm0 = VPMOVZXBDZ256rr                      $xmm0
   ; CHECK: $ymm0 = VPMOVZXBQYrm                $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMOVZXBQZ256rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMOVZXBQYrr                $xmm0
-  $ymm0 = VPMOVZXBQZ256rr                      $xmm0                                          
+  $ymm0 = VPMOVZXBQZ256rr                      $xmm0
   ; CHECK: $ymm0 = VPMOVZXBWYrm                $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMOVZXBWZ256rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMOVZXBWYrr                $xmm0
-  $ymm0 = VPMOVZXBWZ256rr                      $xmm0                                          
+  $ymm0 = VPMOVZXBWZ256rr                      $xmm0
   ; CHECK: $ymm0 = VPMOVZXDQYrm                $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMOVZXDQZ256rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMOVZXDQYrr                $xmm0
-  $ymm0 = VPMOVZXDQZ256rr                      $xmm0                                          
+  $ymm0 = VPMOVZXDQZ256rr                      $xmm0
   ; CHECK: $ymm0 = VPMOVZXWDYrm                $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMOVZXWDZ256rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMOVZXWDYrr                $xmm0
-  $ymm0 = VPMOVZXWDZ256rr                      $xmm0                                          
+  $ymm0 = VPMOVZXWDZ256rr                      $xmm0
   ; CHECK: $ymm0 = VPMOVZXWQYrm                $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPMOVZXWQZ256rm                      $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $ymm0 = VPMOVZXWQYrr                $xmm0                                      
-  $ymm0 = VPMOVZXWQZ256rr                      $xmm0                                                 
+  ; CHECK: $ymm0 = VPMOVZXWQYrr                $xmm0
+  $ymm0 = VPMOVZXWQZ256rr                      $xmm0
   ; CHECK: $ymm0 = VBROADCASTF128              $rip, 1, $noreg, 0, $noreg
   $ymm0 = VBROADCASTF32X4Z256rm                $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VBROADCASTSDYrm             $rip, 1, $noreg, 0, $noreg
@@ -686,23 +686,23 @@ body: |
   ; CHECK: $ymm0 = VBROADCASTSDYrm             $rip, 1, $noreg, 0, $noreg
   $ymm0 = VBROADCASTSDZ256rm                   $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VBROADCASTSDYrr             $xmm0
-  $ymm0 = VBROADCASTSDZ256rr                   $xmm0                                          
+  $ymm0 = VBROADCASTSDZ256rr                   $xmm0
   ; CHECK: $ymm0 = VBROADCASTSSYrm             $rip, 1, $noreg, 0, $noreg
   $ymm0 = VBROADCASTSSZ256rm                   $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VBROADCASTSSYrr             $xmm0
-  $ymm0 = VBROADCASTSSZ256rr                   $xmm0                                          
+  $ymm0 = VBROADCASTSSZ256rr                   $xmm0
   ; CHECK: $ymm0 = VPBROADCASTBYrm             $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPBROADCASTBZ256rm                   $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPBROADCASTBYrr             $xmm0
-  $ymm0 = VPBROADCASTBZ256rr                   $xmm0                                          
+  $ymm0 = VPBROADCASTBZ256rr                   $xmm0
   ; CHECK: $ymm0 = VPBROADCASTDYrm             $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPBROADCASTDZ256rm                   $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPBROADCASTDYrr             $xmm0
-  $ymm0 = VPBROADCASTDZ256rr                   $xmm0                                          
+  $ymm0 = VPBROADCASTDZ256rr                   $xmm0
   ; CHECK: $ymm0 = VPBROADCASTWYrm             $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPBROADCASTWZ256rm                   $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPBROADCASTWYrr             $xmm0
-  $ymm0 = VPBROADCASTWZ256rr                   $xmm0                                          
+  $ymm0 = VPBROADCASTWZ256rr                   $xmm0
   ; CHECK: $ymm0 = VBROADCASTI128              $rip, 1, $noreg, 0, $noreg
   $ymm0 = VBROADCASTI32X4Z256rm                $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPBROADCASTQYrm             $rip, 1, $noreg, 0, $noreg
@@ -711,66 +711,66 @@ body: |
   $ymm0 = VBROADCASTI32X2Z256rr                $xmm0
   ; CHECK: $ymm0 = VPBROADCASTQYrm             $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPBROADCASTQZ256rm                   $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $ymm0 = VPBROADCASTQYrr             $xmm0                                      
-  $ymm0 = VPBROADCASTQZ256rr                   $xmm0                                               
+  ; CHECK: $ymm0 = VPBROADCASTQYrr             $xmm0
+  $ymm0 = VPBROADCASTQZ256rr                   $xmm0
   ; CHECK: $ymm0 = VPABSBYrm                   $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPABSBZ256rm                         $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPABSBYrr                   $ymm0
-  $ymm0 = VPABSBZ256rr                         $ymm0                                          
+  $ymm0 = VPABSBZ256rr                         $ymm0
   ; CHECK: $ymm0 = VPABSDYrm                   $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPABSDZ256rm                         $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPABSDYrr                   $ymm0
-  $ymm0 = VPABSDZ256rr                         $ymm0                                          
+  $ymm0 = VPABSDZ256rr                         $ymm0
   ; CHECK: $ymm0 = VPABSWYrm                   $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPABSWZ256rm                         $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $ymm0 = VPABSWYrr                   $ymm0                                      
-  $ymm0 = VPABSWZ256rr                         $ymm0                                               
+  ; CHECK: $ymm0 = VPABSWYrr                   $ymm0
+  $ymm0 = VPABSWZ256rr                         $ymm0
   ; CHECK: $ymm0 = VPSADBWYrm                  $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPSADBWZ256rm                        $ymm0, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $ymm0 = VPSADBWYrr                  $ymm0, $ymm1                               
-  $ymm0 = VPSADBWZ256rr                        $ymm0, $ymm1                                               
+  ; CHECK: $ymm0 = VPSADBWYrr                  $ymm0, $ymm1
+  $ymm0 = VPSADBWZ256rr                        $ymm0, $ymm1
   ; CHECK: $ymm0 = VPERMDYrm                   $ymm0, $rdi, 1, $noreg, 0, $noreg
-  $ymm0 = VPERMDZ256rm                         $ymm0, $rdi, 1, $noreg, 0, $noreg                        
+  $ymm0 = VPERMDZ256rm                         $ymm0, $rdi, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPERMDYrr                   $ymm1, $ymm0
-  $ymm0 = VPERMDZ256rr                         $ymm1, $ymm0                                   
+  $ymm0 = VPERMDZ256rr                         $ymm1, $ymm0
   ; CHECK: $ymm0 = VPERMILPDYmi                $rdi, 1, $noreg, 0, $noreg, 7
   $ymm0 = VPERMILPDZ256mi                      $rdi, 1, $noreg, 0, $noreg, 7
   ; CHECK: $ymm0 = VPERMILPDYri                $ymm0, 7
-  $ymm0 = VPERMILPDZ256ri                      $ymm0, 7                                       
+  $ymm0 = VPERMILPDZ256ri                      $ymm0, 7
   ; CHECK: $ymm0 = VPERMILPDYrm                $ymm0, $rdi, 1, $noreg, 0, $noreg
-  $ymm0 = VPERMILPDZ256rm                      $ymm0, $rdi, 1, $noreg, 0, $noreg                        
+  $ymm0 = VPERMILPDZ256rm                      $ymm0, $rdi, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPERMILPDYrr                $ymm1, $ymm0
-  $ymm0 = VPERMILPDZ256rr                      $ymm1, $ymm0                                   
+  $ymm0 = VPERMILPDZ256rr                      $ymm1, $ymm0
   ; CHECK: $ymm0 = VPERMILPSYmi                $rdi, 1, $noreg, 0, $noreg, 7
   $ymm0 = VPERMILPSZ256mi                      $rdi, 1, $noreg, 0, $noreg, 7
   ; CHECK: $ymm0 = VPERMILPSYri                $ymm0, 7
-  $ymm0 = VPERMILPSZ256ri                      $ymm0, 7                                       
+  $ymm0 = VPERMILPSZ256ri                      $ymm0, 7
   ; CHECK: $ymm0 = VPERMILPSYrm                $ymm0, $rdi, 1, $noreg, 0, $noreg
-  $ymm0 = VPERMILPSZ256rm                      $ymm0, $rdi, 1, $noreg, 0, $noreg                        
+  $ymm0 = VPERMILPSZ256rm                      $ymm0, $rdi, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPERMILPSYrr                $ymm1, $ymm0
-  $ymm0 = VPERMILPSZ256rr                      $ymm1, $ymm0                                   
+  $ymm0 = VPERMILPSZ256rr                      $ymm1, $ymm0
   ; CHECK: $ymm0 = VPERMPDYmi                  $rdi, 1, $noreg, 0, $noreg, 7
   $ymm0 = VPERMPDZ256mi                        $rdi, 1, $noreg, 0, $noreg, 7
   ; CHECK: $ymm0 = VPERMPDYri                  $ymm0, 7
-  $ymm0 = VPERMPDZ256ri                        $ymm0, 7                                       
+  $ymm0 = VPERMPDZ256ri                        $ymm0, 7
   ; CHECK: $ymm0 = VPERMPSYrm                  $ymm0, $rdi, 1, $noreg, 0, $noreg
-  $ymm0 = VPERMPSZ256rm                        $ymm0, $rdi, 1, $noreg, 0, $noreg                        
+  $ymm0 = VPERMPSZ256rm                        $ymm0, $rdi, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPERMPSYrr                  $ymm1, $ymm0
-  $ymm0 = VPERMPSZ256rr                        $ymm1, $ymm0                                   
+  $ymm0 = VPERMPSZ256rr                        $ymm1, $ymm0
   ; CHECK: $ymm0 = VPERMQYmi                   $rdi, 1, $noreg, 0, $noreg, 7
   $ymm0 = VPERMQZ256mi                         $rdi, 1, $noreg, 0, $noreg, 7
-  ; CHECK: $ymm0 = VPERMQYri                   $ymm0, 7                                   
-  $ymm0 = VPERMQZ256ri                         $ymm0, 7                                               
+  ; CHECK: $ymm0 = VPERMQYri                   $ymm0, 7
+  $ymm0 = VPERMQZ256ri                         $ymm0, 7
   ; CHECK: $ymm0 = VPSLLDQYri                  $ymm0, 14
-  $ymm0 = VPSLLDQZ256ri                        $ymm0, 14                                      
+  $ymm0 = VPSLLDQZ256ri                        $ymm0, 14
   ; CHECK: $ymm0 = VPSLLDYri                   $ymm0, 7
-  $ymm0 = VPSLLDZ256ri                         $ymm0, 7                                       
+  $ymm0 = VPSLLDZ256ri                         $ymm0, 7
   ; CHECK: $ymm0 = VPSLLDYrm                   $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPSLLDZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPSLLDYrr                   $ymm0, $xmm0
   $ymm0 = VPSLLDZ256rr                         $ymm0, $xmm0
   ; CHECK: $ymm0 = VPSLLQYri                   $ymm0, 7
-  $ymm0 = VPSLLQZ256ri                         $ymm0, 7                                       
+  $ymm0 = VPSLLQZ256ri                         $ymm0, 7
   ; CHECK: $ymm0 = VPSLLQYrm                   $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPSLLQZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPSLLQYrr                   $ymm0, $xmm0
@@ -784,7 +784,7 @@ body: |
   ; CHECK: $ymm0 = VPSLLVQYrr                  $ymm0, $ymm0
   $ymm0 = VPSLLVQZ256rr                        $ymm0, $ymm0
   ; CHECK: $ymm0 = VPSLLWYri                   $ymm0, 7
-  $ymm0 = VPSLLWZ256ri                         $ymm0, 7                                       
+  $ymm0 = VPSLLWZ256ri                         $ymm0, 7
   ; CHECK: $ymm0 = VPSLLWYrm                   $ymm0, $rip, 1, $noreg, 0, $noreg
   $ymm0 = VPSLLWZ256rm                         $ymm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPSLLWYrr                   $ymm0, $xmm0
@@ -792,7 +792,7 @@ body: |
   ; CHECK: $ymm0 = VCVTDQ2PDYrm                $rdi, 1, $noreg, 0, $noreg
   $ymm0 = VCVTDQ2PDZ256rm                      $rdi, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VCVTDQ2PDYrr                $xmm0
-  $ymm0 = VCVTDQ2PDZ256rr                      $xmm0                                          
+  $ymm0 = VCVTDQ2PDZ256rr                      $xmm0
   ; CHECK: $ymm0 = VCVTDQ2PSYrm                $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
   $ymm0 = VCVTDQ2PSZ256rm                      $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $ymm0 = VCVTDQ2PSYrr                $ymm0, implicit $mxcsr
@@ -841,26 +841,26 @@ body: |
   $ymm0 = VPALIGNRZ256rmi                      $ymm0, $rdi, 1, $noreg, 0, $noreg, 1
   ; CHECK: $ymm0 = VPALIGNRYrri                $ymm0, $ymm1, 1
   $ymm0 = VPALIGNRZ256rri                      $ymm0, $ymm1, 1
-  ; CHECK: $ymm0 = VMOVUPSYrm                  $rdi, 1, $noreg, 0, $noreg       
-  $ymm0 = VMOVUPSZ256rm                        $rdi, 1, $noreg, 0, $noreg                               
+  ; CHECK: $ymm0 = VMOVUPSYrm                  $rdi, 1, $noreg, 0, $noreg
+  $ymm0 = VMOVUPSZ256rm                        $rdi, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VMOVUPSYrr                  $ymm0
-  $ymm0 = VMOVUPSZ256rr                        $ymm0                                          
+  $ymm0 = VMOVUPSZ256rr                        $ymm0
   ; CHECK: $ymm0 = VPSHUFBYrm                  $ymm0, $rdi, 1, $noreg, 0, $noreg
   $ymm0 = VPSHUFBZ256rm                        $ymm0, $rdi, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPSHUFBYrr                  $ymm0, $ymm1
-  $ymm0 = VPSHUFBZ256rr                        $ymm0, $ymm1                                   
+  $ymm0 = VPSHUFBZ256rr                        $ymm0, $ymm1
   ; CHECK: $ymm0 = VPSHUFDYmi                  $rdi, 1, $noreg, 0, $noreg, -24
   $ymm0 = VPSHUFDZ256mi                        $rdi, 1, $noreg, 0, $noreg, -24
   ; CHECK: $ymm0 = VPSHUFDYri                  $ymm0, -24
-  $ymm0 = VPSHUFDZ256ri                        $ymm0, -24                                     
+  $ymm0 = VPSHUFDZ256ri                        $ymm0, -24
   ; CHECK: $ymm0 = VPSHUFHWYmi                 $rdi, 1, $noreg, 0, $noreg, -24
   $ymm0 = VPSHUFHWZ256mi                       $rdi, 1, $noreg, 0, $noreg, -24
   ; CHECK: $ymm0 = VPSHUFHWYri                 $ymm0, -24
-  $ymm0 = VPSHUFHWZ256ri                       $ymm0, -24                                     
+  $ymm0 = VPSHUFHWZ256ri                       $ymm0, -24
   ; CHECK: $ymm0 = VPSHUFLWYmi                 $rdi, 1, $noreg, 0, $noreg, -24
   $ymm0 = VPSHUFLWZ256mi                       $rdi, 1, $noreg, 0, $noreg, -24
   ; CHECK: $ymm0 = VPSHUFLWYri                 $ymm0, -24
-  $ymm0 = VPSHUFLWZ256ri                       $ymm0, -24                                     
+  $ymm0 = VPSHUFLWZ256ri                       $ymm0, -24
   ; CHECK: $ymm0 = VSHUFPDYrmi                 $ymm0, $rdi, 1, $noreg, 0, $noreg, -24
   $ymm0 = VSHUFPDZ256rmi                       $ymm0, $rdi, 1, $noreg, 0, $noreg, -24
   ; CHECK: $ymm0 = VSHUFPDYrri                 $ymm0, $ymm1, -24
@@ -904,137 +904,137 @@ name: evex_z128_to_vex_test
 body: |
   bb.0:
   ; CHECK: VMOVAPDmr                           $rdi, 1, $noreg, 0, $noreg, $xmm0
-  VMOVAPDZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm0                             
+  VMOVAPDZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm0
   ; CHECK: $xmm0 = VMOVAPDrm                   $rip, 1, $noreg, 0, $noreg
   $xmm0 = VMOVAPDZ128rm                        $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VMOVAPDrr                   $xmm0
-  $xmm0 = VMOVAPDZ128rr                        $xmm0                                               
+  $xmm0 = VMOVAPDZ128rr                        $xmm0
   ; CHECK: VMOVAPSmr                           $rdi, 1, $noreg, 0, $noreg, $xmm0
-  VMOVAPSZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm0                             
+  VMOVAPSZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm0
   ; CHECK: $xmm0 = VMOVAPSrm                   $rip, 1, $noreg, 0, $noreg
   $xmm0 = VMOVAPSZ128rm                        $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm0 = VMOVAPSrr                   $xmm0  
-  $xmm0 = VMOVAPSZ128rr                        $xmm0                                               
+  ; CHECK: $xmm0 = VMOVAPSrr                   $xmm0
+  $xmm0 = VMOVAPSZ128rr                        $xmm0
   ; CHECK: VMOVDQAmr                           $rdi, 1, $noreg, 0, $noreg, $xmm0
-  VMOVDQA32Z128mr                              $rdi, 1, $noreg, 0, $noreg, $xmm0                             
+  VMOVDQA32Z128mr                              $rdi, 1, $noreg, 0, $noreg, $xmm0
   ; CHECK: $xmm0 = VMOVDQArm                   $rip, 1, $noreg, 0, $noreg
   $xmm0 = VMOVDQA32Z128rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VMOVDQArr                   $xmm0
-  $xmm0 = VMOVDQA32Z128rr                      $xmm0                                               
+  $xmm0 = VMOVDQA32Z128rr                      $xmm0
   ; CHECK: VMOVDQAmr                           $rdi, 1, $noreg, 0, $noreg, $xmm0
-  VMOVDQA64Z128mr                              $rdi, 1, $noreg, 0, $noreg, $xmm0                             
+  VMOVDQA64Z128mr                              $rdi, 1, $noreg, 0, $noreg, $xmm0
   ; CHECK: $xmm0 = VMOVDQArm                   $rip, 1, $noreg, 0, $noreg
   $xmm0 = VMOVDQA64Z128rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VMOVDQArr                   $xmm0
-  $xmm0 = VMOVDQA64Z128rr                      $xmm0                                               
+  $xmm0 = VMOVDQA64Z128rr                      $xmm0
   ; CHECK: VMOVDQUmr                           $rdi, 1, $noreg, 0, $noreg, $xmm0
-  VMOVDQU16Z128mr                              $rdi, 1, $noreg, 0, $noreg, $xmm0                             
+  VMOVDQU16Z128mr                              $rdi, 1, $noreg, 0, $noreg, $xmm0
   ; CHECK: $xmm0 = VMOVDQUrm                   $rip, 1, $noreg, 0, $noreg
   $xmm0 = VMOVDQU16Z128rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VMOVDQUrr                   $xmm0
-  $xmm0 = VMOVDQU16Z128rr                      $xmm0                                               
+  $xmm0 = VMOVDQU16Z128rr                      $xmm0
   ; CHECK: VMOVDQUmr                           $rdi, 1, $noreg, 0, $noreg, $xmm0
-  VMOVDQU32Z128mr                              $rdi, 1, $noreg, 0, $noreg, $xmm0                             
+  VMOVDQU32Z128mr                              $rdi, 1, $noreg, 0, $noreg, $xmm0
   ; CHECK: $xmm0 = VMOVDQUrm                   $rip, 1, $noreg, 0, $noreg
   $xmm0 = VMOVDQU32Z128rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VMOVDQUrr                   $xmm0
-  $xmm0 = VMOVDQU32Z128rr                      $xmm0                                               
+  $xmm0 = VMOVDQU32Z128rr                      $xmm0
   ; CHECK: VMOVDQUmr                           $rdi, 1, $noreg, 0, $noreg, $xmm0
-  VMOVDQU64Z128mr                              $rdi, 1, $noreg, 0, $noreg, $xmm0                             
+  VMOVDQU64Z128mr                              $rdi, 1, $noreg, 0, $noreg, $xmm0
   ; CHECK: $xmm0 = VMOVDQUrm                   $rip, 1, $noreg, 0, $noreg
   $xmm0 = VMOVDQU64Z128rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VMOVDQUrr                   $xmm0
-  $xmm0 = VMOVDQU64Z128rr                      $xmm0                                               
+  $xmm0 = VMOVDQU64Z128rr                      $xmm0
   ; CHECK: VMOVDQUmr                           $rdi, 1, $noreg, 0, $noreg, $xmm0
-  VMOVDQU8Z128mr                               $rdi, 1, $noreg, 0, $noreg, $xmm0                             
+  VMOVDQU8Z128mr                               $rdi, 1, $noreg, 0, $noreg, $xmm0
   ; CHECK: $xmm0 = VMOVDQUrm                   $rip, 1, $noreg, 0, $noreg
   $xmm0 = VMOVDQU8Z128rm                       $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VMOVDQUrr                   $xmm0
-  $xmm0 = VMOVDQU8Z128rr                       $xmm0                                               
+  $xmm0 = VMOVDQU8Z128rr                       $xmm0
   ; CHECK: $xmm0 = VMOVNTDQArm                 $rip, 1, $noreg, 0, $noreg
   $xmm0 = VMOVNTDQAZ128rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: VMOVUPDmr                           $rdi, 1, $noreg, 0, $noreg, $xmm0
-  VMOVUPDZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm0                             
+  VMOVUPDZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm0
   ; CHECK: $xmm0 = VMOVUPDrm                   $rip, 1, $noreg, 0, $noreg
   $xmm0 = VMOVUPDZ128rm                        $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VMOVUPDrr                   $xmm0
-  $xmm0 = VMOVUPDZ128rr                        $xmm0                                               
+  $xmm0 = VMOVUPDZ128rr                        $xmm0
   ; CHECK: VMOVUPSmr                           $rdi, 1, $noreg, 0, $noreg, $xmm0
-  VMOVUPSZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm0                             
+  VMOVUPSZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm0
   ; CHECK: $xmm0 = VMOVUPSrm                   $rip, 1, $noreg, 0, $noreg
   $xmm0 = VMOVUPSZ128rm                        $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VMOVUPSrr                   $xmm0
-  $xmm0 = VMOVUPSZ128rr                        $xmm0                                               
+  $xmm0 = VMOVUPSZ128rr                        $xmm0
   ; CHECK: VMOVNTDQmr                          $rdi, 1, $noreg, 0, $noreg, $xmm0
-  VMOVNTDQZ128mr                               $rdi, 1, $noreg, 0, $noreg, $xmm0                             
+  VMOVNTDQZ128mr                               $rdi, 1, $noreg, 0, $noreg, $xmm0
   ; CHECK: VMOVNTPDmr                          $rdi, 1, $noreg, 0, $noreg, $xmm0
-  VMOVNTPDZ128mr                               $rdi, 1, $noreg, 0, $noreg, $xmm0                             
+  VMOVNTPDZ128mr                               $rdi, 1, $noreg, 0, $noreg, $xmm0
   ; CHECK: VMOVNTPSmr                          $rdi, 1, $noreg, 0, $noreg, $xmm0
-  VMOVNTPSZ128mr                               $rdi, 1, $noreg, 0, $noreg, $xmm0                             
+  VMOVNTPSZ128mr                               $rdi, 1, $noreg, 0, $noreg, $xmm0
   ; CHECK: $xmm0 = VPMOVSXBDrm                 $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMOVSXBDZ128rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMOVSXBDrr                 $xmm0
-  $xmm0 = VPMOVSXBDZ128rr                      $xmm0                                               
+  $xmm0 = VPMOVSXBDZ128rr                      $xmm0
   ; CHECK: $xmm0 = VPMOVSXBQrm                 $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMOVSXBQZ128rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMOVSXBQrr                 $xmm0
-  $xmm0 = VPMOVSXBQZ128rr                      $xmm0                                               
+  $xmm0 = VPMOVSXBQZ128rr                      $xmm0
   ; CHECK: $xmm0 = VPMOVSXBWrm                 $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMOVSXBWZ128rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMOVSXBWrr                 $xmm0
-  $xmm0 = VPMOVSXBWZ128rr                      $xmm0                                               
+  $xmm0 = VPMOVSXBWZ128rr                      $xmm0
   ; CHECK: $xmm0 = VPMOVSXDQrm                 $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMOVSXDQZ128rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMOVSXDQrr                 $xmm0
-  $xmm0 = VPMOVSXDQZ128rr                      $xmm0                                               
+  $xmm0 = VPMOVSXDQZ128rr                      $xmm0
   ; CHECK: $xmm0 = VPMOVSXWDrm                 $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMOVSXWDZ128rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMOVSXWDrr                 $xmm0
-  $xmm0 = VPMOVSXWDZ128rr                      $xmm0                                               
+  $xmm0 = VPMOVSXWDZ128rr                      $xmm0
   ; CHECK: $xmm0 = VPMOVSXWQrm                 $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMOVSXWQZ128rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMOVSXWQrr                 $xmm0
-  $xmm0 = VPMOVSXWQZ128rr                      $xmm0                                               
+  $xmm0 = VPMOVSXWQZ128rr                      $xmm0
   ; CHECK: $xmm0 = VPMOVZXBDrm                 $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMOVZXBDZ128rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMOVZXBDrr                 $xmm0
-  $xmm0 = VPMOVZXBDZ128rr                      $xmm0                                               
+  $xmm0 = VPMOVZXBDZ128rr                      $xmm0
   ; CHECK: $xmm0 = VPMOVZXBQrm                 $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMOVZXBQZ128rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMOVZXBQrr                 $xmm0
-  $xmm0 = VPMOVZXBQZ128rr                      $xmm0                                               
+  $xmm0 = VPMOVZXBQZ128rr                      $xmm0
   ; CHECK: $xmm0 = VPMOVZXBWrm                 $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMOVZXBWZ128rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMOVZXBWrr                 $xmm0
-  $xmm0 = VPMOVZXBWZ128rr                      $xmm0                                               
+  $xmm0 = VPMOVZXBWZ128rr                      $xmm0
   ; CHECK: $xmm0 = VPMOVZXDQrm                 $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMOVZXDQZ128rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMOVZXDQrr                 $xmm0
-  $xmm0 = VPMOVZXDQZ128rr                      $xmm0                                               
+  $xmm0 = VPMOVZXDQZ128rr                      $xmm0
   ; CHECK: $xmm0 = VPMOVZXWDrm                 $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMOVZXWDZ128rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMOVZXWDrr                 $xmm0
-  $xmm0 = VPMOVZXWDZ128rr                      $xmm0                                               
+  $xmm0 = VPMOVZXWDZ128rr                      $xmm0
   ; CHECK: $xmm0 = VPMOVZXWQrm                 $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMOVZXWQZ128rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMOVZXWQrr                 $xmm0
-  $xmm0 = VPMOVZXWQZ128rr                      $xmm0                                               
+  $xmm0 = VPMOVZXWQZ128rr                      $xmm0
   ; CHECK: VMOVHPDmr                           $rdi, 1, $noreg, 0, $noreg, $xmm0
-  VMOVHPDZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm0                             
+  VMOVHPDZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm0
   ; CHECK: $xmm0 = VMOVHPDrm                   $xmm0,  $rdi, 1, $noreg, 0, $noreg
-  $xmm0 = VMOVHPDZ128rm                        $xmm0,  $rdi, 1, $noreg, 0, $noreg                            
+  $xmm0 = VMOVHPDZ128rm                        $xmm0,  $rdi, 1, $noreg, 0, $noreg
   ; CHECK: VMOVHPSmr                           $rdi, 1, $noreg, 0, $noreg, $xmm0
-  VMOVHPSZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm0                             
+  VMOVHPSZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm0
   ; CHECK: $xmm0 = VMOVHPSrm                   $xmm0,  $rdi, 1, $noreg, 0, $noreg
-  $xmm0 = VMOVHPSZ128rm                        $xmm0,  $rdi, 1, $noreg, 0, $noreg                            
+  $xmm0 = VMOVHPSZ128rm                        $xmm0,  $rdi, 1, $noreg, 0, $noreg
   ; CHECK: VMOVLPDmr                           $rdi, 1, $noreg, 0, $noreg, $xmm0
-  VMOVLPDZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm0                             
+  VMOVLPDZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm0
   ; CHECK: $xmm0 = VMOVLPDrm                   $xmm0,  $rdi, 1, $noreg, 0, $noreg
-  $xmm0 = VMOVLPDZ128rm                        $xmm0,  $rdi, 1, $noreg, 0, $noreg                            
+  $xmm0 = VMOVLPDZ128rm                        $xmm0,  $rdi, 1, $noreg, 0, $noreg
   ; CHECK: VMOVLPSmr                           $rdi, 1, $noreg, 0, $noreg, $xmm0
-  VMOVLPSZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm0                             
-  ; CHECK: $xmm0 = VMOVLPSrm                   $xmm0,  $rdi, 1, $noreg, 0, $noreg                
-  $xmm0 = VMOVLPSZ128rm                        $xmm0,  $rdi, 1, $noreg, 0, $noreg                                               
+  VMOVLPSZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm0
+  ; CHECK: $xmm0 = VMOVLPSrm                   $xmm0,  $rdi, 1, $noreg, 0, $noreg
+  $xmm0 = VMOVLPSZ128rm                        $xmm0,  $rdi, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VMAXCPDrm                   $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   $xmm0 = VMAXCPDZ128rm                        $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $xmm0 = VMAXCPDrr                   $xmm0, $xmm1, implicit $mxcsr
@@ -1078,183 +1078,183 @@ body: |
   ; CHECK: $xmm0 = VORPDrm                     $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VORPDZ128rm                          $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VORPDrr                     $xmm0, $xmm1
-  $xmm0 = VORPDZ128rr                          $xmm0, $xmm1                                        
+  $xmm0 = VORPDZ128rr                          $xmm0, $xmm1
   ; CHECK: $xmm0 = VORPSrm                     $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VORPSZ128rm                          $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VORPSrr                     $xmm0, $xmm1
-  $xmm0 = VORPSZ128rr                          $xmm0, $xmm1                                        
+  $xmm0 = VORPSZ128rr                          $xmm0, $xmm1
   ; CHECK: $xmm0 = VPADDBrm                    $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPADDBZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPADDBrr                    $xmm0, $xmm1
-  $xmm0 = VPADDBZ128rr                         $xmm0, $xmm1                                        
+  $xmm0 = VPADDBZ128rr                         $xmm0, $xmm1
   ; CHECK: $xmm0 = VPADDDrm                    $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPADDDZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPADDDrr                    $xmm0, $xmm1
-  $xmm0 = VPADDDZ128rr                         $xmm0, $xmm1                                        
+  $xmm0 = VPADDDZ128rr                         $xmm0, $xmm1
   ; CHECK: $xmm0 = VPADDQrm                    $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPADDQZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPADDQrr                    $xmm0, $xmm1
-  $xmm0 = VPADDQZ128rr                         $xmm0, $xmm1                                        
+  $xmm0 = VPADDQZ128rr                         $xmm0, $xmm1
   ; CHECK: $xmm0 = VPADDSBrm                   $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPADDSBZ128rm                        $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPADDSBrr                   $xmm0, $xmm1
-  $xmm0 = VPADDSBZ128rr                        $xmm0, $xmm1                                        
+  $xmm0 = VPADDSBZ128rr                        $xmm0, $xmm1
   ; CHECK: $xmm0 = VPADDSWrm                   $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPADDSWZ128rm                        $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPADDSWrr                   $xmm0, $xmm1
-  $xmm0 = VPADDSWZ128rr                        $xmm0, $xmm1                                        
+  $xmm0 = VPADDSWZ128rr                        $xmm0, $xmm1
   ; CHECK: $xmm0 = VPADDUSBrm                  $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPADDUSBZ128rm                       $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPADDUSBrr                  $xmm0, $xmm1
-  $xmm0 = VPADDUSBZ128rr                       $xmm0, $xmm1                                        
+  $xmm0 = VPADDUSBZ128rr                       $xmm0, $xmm1
   ; CHECK: $xmm0 = VPADDUSWrm                  $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPADDUSWZ128rm                       $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPADDUSWrr                  $xmm0, $xmm1
-  $xmm0 = VPADDUSWZ128rr                       $xmm0, $xmm1                                        
+  $xmm0 = VPADDUSWZ128rr                       $xmm0, $xmm1
   ; CHECK: $xmm0 = VPADDWrm                    $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPADDWZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPADDWrr                    $xmm0, $xmm1
-  $xmm0 = VPADDWZ128rr                         $xmm0, $xmm1                                        
+  $xmm0 = VPADDWZ128rr                         $xmm0, $xmm1
   ; CHECK: $xmm0 = VPANDrm                     $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPANDDZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPANDrr                     $xmm0, $xmm1
-  $xmm0 = VPANDDZ128rr                         $xmm0, $xmm1                                        
+  $xmm0 = VPANDDZ128rr                         $xmm0, $xmm1
   ; CHECK: $xmm0 = VPANDrm                     $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPANDQZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm0 = VPANDrr                     $xmm0, $xmm1  
-  $xmm0 = VPANDQZ128rr                         $xmm0, $xmm1                                        
+  ; CHECK: $xmm0 = VPANDrr                     $xmm0, $xmm1
+  $xmm0 = VPANDQZ128rr                         $xmm0, $xmm1
   ; CHECK: $xmm0 = VPANDNrm                    $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPANDNDZ128rm                        $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPANDNrr                    $xmm0, $xmm1
-  $xmm0 = VPANDNDZ128rr                        $xmm0, $xmm1                                        
+  $xmm0 = VPANDNDZ128rr                        $xmm0, $xmm1
   ; CHECK: $xmm0 = VPANDNrm                    $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPANDNQZ128rm                        $xmm0, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm0 = VPANDNrr                    $xmm0, $xmm1  
-  $xmm0 = VPANDNQZ128rr                        $xmm0, $xmm1                                        
+  ; CHECK: $xmm0 = VPANDNrr                    $xmm0, $xmm1
+  $xmm0 = VPANDNQZ128rr                        $xmm0, $xmm1
   ; CHECK: $xmm0 = VPAVGBrm                    $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPAVGBZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm0 = VPAVGBrr                    $xmm0, $xmm1  
-  $xmm0 = VPAVGBZ128rr                         $xmm0, $xmm1                                        
+  ; CHECK: $xmm0 = VPAVGBrr                    $xmm0, $xmm1
+  $xmm0 = VPAVGBZ128rr                         $xmm0, $xmm1
   ; CHECK: $xmm0 = VPAVGWrm                    $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPAVGWZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPAVGWrr                    $xmm0, $xmm1
-  $xmm0 = VPAVGWZ128rr                         $xmm0, $xmm1                                        
+  $xmm0 = VPAVGWZ128rr                         $xmm0, $xmm1
   ; CHECK: $xmm0 = VPMAXSBrm                   $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMAXSBZ128rm                        $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMAXSBrr                   $xmm0, $xmm1
-  $xmm0 = VPMAXSBZ128rr                        $xmm0, $xmm1                                        
+  $xmm0 = VPMAXSBZ128rr                        $xmm0, $xmm1
   ; CHECK: $xmm0 = VPMAXSDrm                   $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMAXSDZ128rm                        $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMAXSDrr                   $xmm0, $xmm1
-  $xmm0 = VPMAXSDZ128rr                        $xmm0, $xmm1                                        
+  $xmm0 = VPMAXSDZ128rr                        $xmm0, $xmm1
   ; CHECK: $xmm0 = VPMAXSWrm                   $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMAXSWZ128rm                        $xmm0, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm0 = VPMAXSWrr                   $xmm0, $xmm1  
-  $xmm0 = VPMAXSWZ128rr                        $xmm0, $xmm1                                        
+  ; CHECK: $xmm0 = VPMAXSWrr                   $xmm0, $xmm1
+  $xmm0 = VPMAXSWZ128rr                        $xmm0, $xmm1
   ; CHECK: $xmm0 = VPMAXUBrm                   $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMAXUBZ128rm                        $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMAXUBrr                   $xmm0, $xmm1
-  $xmm0 = VPMAXUBZ128rr                        $xmm0, $xmm1                                        
+  $xmm0 = VPMAXUBZ128rr                        $xmm0, $xmm1
   ; CHECK: $xmm0 = VPMAXUDrm                   $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMAXUDZ128rm                        $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMAXUDrr                   $xmm0, $xmm1
-  $xmm0 = VPMAXUDZ128rr                        $xmm0, $xmm1                                        
+  $xmm0 = VPMAXUDZ128rr                        $xmm0, $xmm1
   ; CHECK: $xmm0 = VPMAXUWrm                   $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMAXUWZ128rm                        $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMAXUWrr                   $xmm0, $xmm1
-  $xmm0 = VPMAXUWZ128rr                        $xmm0, $xmm1                                        
+  $xmm0 = VPMAXUWZ128rr                        $xmm0, $xmm1
   ; CHECK: $xmm0 = VPMINSBrm                   $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMINSBZ128rm                        $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMINSBrr                   $xmm0, $xmm1
-  $xmm0 = VPMINSBZ128rr                        $xmm0, $xmm1                                        
+  $xmm0 = VPMINSBZ128rr                        $xmm0, $xmm1
   ; CHECK: $xmm0 = VPMINSDrm                   $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMINSDZ128rm                        $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMINSDrr                   $xmm0, $xmm1
-  $xmm0 = VPMINSDZ128rr                        $xmm0, $xmm1                                        
+  $xmm0 = VPMINSDZ128rr                        $xmm0, $xmm1
   ; CHECK: $xmm0 = VPMINSWrm                   $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMINSWZ128rm                        $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMINSWrr                   $xmm0, $xmm1
-  $xmm0 = VPMINSWZ128rr                        $xmm0, $xmm1                                        
+  $xmm0 = VPMINSWZ128rr                        $xmm0, $xmm1
   ; CHECK: $xmm0 = VPMINUBrm                   $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMINUBZ128rm                        $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMINUBrr                   $xmm0, $xmm1
-  $xmm0 = VPMINUBZ128rr                        $xmm0, $xmm1                                        
+  $xmm0 = VPMINUBZ128rr                        $xmm0, $xmm1
   ; CHECK: $xmm0 = VPMINUDrm                   $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMINUDZ128rm                        $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMINUDrr                   $xmm0, $xmm1
-  $xmm0 = VPMINUDZ128rr                        $xmm0, $xmm1                                        
+  $xmm0 = VPMINUDZ128rr                        $xmm0, $xmm1
   ; CHECK: $xmm0 = VPMINUWrm                   $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMINUWZ128rm                        $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMINUWrr                   $xmm0, $xmm1
-  $xmm0 = VPMINUWZ128rr                        $xmm0, $xmm1                                        
+  $xmm0 = VPMINUWZ128rr                        $xmm0, $xmm1
   ; CHECK: $xmm0 = VPMULDQrm                   $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMULDQZ128rm                        $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMULDQrr                   $xmm0, $xmm1
-  $xmm0 = VPMULDQZ128rr                        $xmm0, $xmm1                                        
+  $xmm0 = VPMULDQZ128rr                        $xmm0, $xmm1
   ; CHECK: $xmm0 = VPMULHRSWrm                 $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMULHRSWZ128rm                      $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMULHRSWrr                 $xmm0, $xmm1
-  $xmm0 = VPMULHRSWZ128rr                      $xmm0, $xmm1                                        
+  $xmm0 = VPMULHRSWZ128rr                      $xmm0, $xmm1
   ; CHECK: $xmm0 = VPMULHUWrm                  $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMULHUWZ128rm                       $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMULHUWrr                  $xmm0, $xmm1
-  $xmm0 = VPMULHUWZ128rr                       $xmm0, $xmm1                                        
+  $xmm0 = VPMULHUWZ128rr                       $xmm0, $xmm1
   ; CHECK: $xmm0 = VPMULHWrm                   $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMULHWZ128rm                        $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMULHWrr                   $xmm0, $xmm1
-  $xmm0 = VPMULHWZ128rr                        $xmm0, $xmm1                                        
+  $xmm0 = VPMULHWZ128rr                        $xmm0, $xmm1
   ; CHECK: $xmm0 = VPMULLDrm                   $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMULLDZ128rm                        $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMULLDrr                   $xmm0, $xmm1
-  $xmm0 = VPMULLDZ128rr                        $xmm0, $xmm1                                        
+  $xmm0 = VPMULLDZ128rr                        $xmm0, $xmm1
   ; CHECK: $xmm0 = VPMULLWrm                   $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMULLWZ128rm                        $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMULLWrr                   $xmm0, $xmm1
-  $xmm0 = VPMULLWZ128rr                        $xmm0, $xmm1                                        
+  $xmm0 = VPMULLWZ128rr                        $xmm0, $xmm1
   ; CHECK: $xmm0 = VPMULUDQrm                  $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMULUDQZ128rm                       $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMULUDQrr                  $xmm0, $xmm1
-  $xmm0 = VPMULUDQZ128rr                       $xmm0, $xmm1                                        
+  $xmm0 = VPMULUDQZ128rr                       $xmm0, $xmm1
   ; CHECK: $xmm0 = VPORrm                      $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPORDZ128rm                          $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPORrr                      $xmm0, $xmm1
-  $xmm0 = VPORDZ128rr                          $xmm0, $xmm1                                        
+  $xmm0 = VPORDZ128rr                          $xmm0, $xmm1
   ; CHECK: $xmm0 = VPORrm                      $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPORQZ128rm                          $xmm0, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm0 = VPORrr                      $xmm0, $xmm1  
-  $xmm0 = VPORQZ128rr                          $xmm0, $xmm1                                        
+  ; CHECK: $xmm0 = VPORrr                      $xmm0, $xmm1
+  $xmm0 = VPORQZ128rr                          $xmm0, $xmm1
   ; CHECK: $xmm0 = VPSUBBrm                    $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPSUBBZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPSUBBrr                    $xmm0, $xmm1
-  $xmm0 = VPSUBBZ128rr                         $xmm0, $xmm1                                        
+  $xmm0 = VPSUBBZ128rr                         $xmm0, $xmm1
   ; CHECK: $xmm0 = VPSUBDrm                    $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPSUBDZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPSUBDrr                    $xmm0, $xmm1
-  $xmm0 = VPSUBDZ128rr                         $xmm0, $xmm1                                        
+  $xmm0 = VPSUBDZ128rr                         $xmm0, $xmm1
   ; CHECK: $xmm0 = VPSUBQrm                    $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPSUBQZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPSUBQrr                    $xmm0, $xmm1
-  $xmm0 = VPSUBQZ128rr                         $xmm0, $xmm1                                        
+  $xmm0 = VPSUBQZ128rr                         $xmm0, $xmm1
   ; CHECK: $xmm0 = VPSUBSBrm                   $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPSUBSBZ128rm                        $xmm0, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm0 = VPSUBSBrr                   $xmm0, $xmm1  
-  $xmm0 = VPSUBSBZ128rr                        $xmm0, $xmm1                                        
+  ; CHECK: $xmm0 = VPSUBSBrr                   $xmm0, $xmm1
+  $xmm0 = VPSUBSBZ128rr                        $xmm0, $xmm1
   ; CHECK: $xmm0 = VPSUBSWrm                   $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPSUBSWZ128rm                        $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPSUBSWrr                   $xmm0, $xmm1
-  $xmm0 = VPSUBSWZ128rr                        $xmm0, $xmm1                                        
+  $xmm0 = VPSUBSWZ128rr                        $xmm0, $xmm1
   ; CHECK: $xmm0 = VPSUBUSBrm                  $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPSUBUSBZ128rm                       $xmm0, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm0 = VPSUBUSBrr                  $xmm0, $xmm1  
-  $xmm0 = VPSUBUSBZ128rr                       $xmm0, $xmm1                                        
+  ; CHECK: $xmm0 = VPSUBUSBrr                  $xmm0, $xmm1
+  $xmm0 = VPSUBUSBZ128rr                       $xmm0, $xmm1
   ; CHECK: $xmm0 = VPSUBUSWrm                  $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPSUBUSWZ128rm                       $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPSUBUSWrr                  $xmm0, $xmm1
-  $xmm0 = VPSUBUSWZ128rr                       $xmm0, $xmm1                                        
+  $xmm0 = VPSUBUSWZ128rr                       $xmm0, $xmm1
   ; CHECK: $xmm0 = VPSUBWrm                    $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPSUBWZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm0 = VPSUBWrr                    $xmm0, $xmm1                            
-  $xmm0 = VPSUBWZ128rr                         $xmm0, $xmm1                                        
+  ; CHECK: $xmm0 = VPSUBWrr                    $xmm0, $xmm1
+  $xmm0 = VPSUBWZ128rr                         $xmm0, $xmm1
   ; CHECK: $xmm0 = VADDPDrm                    $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   $xmm0 = VADDPDZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $xmm0 = VADDPDrr                    $xmm0, $xmm1, implicit $mxcsr
@@ -1266,19 +1266,19 @@ body: |
   ; CHECK: $xmm0 = VANDNPDrm                   $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VANDNPDZ128rm                        $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VANDNPDrr                   $xmm0, $xmm1
-  $xmm0 = VANDNPDZ128rr                        $xmm0, $xmm1                                        
+  $xmm0 = VANDNPDZ128rr                        $xmm0, $xmm1
   ; CHECK: $xmm0 = VANDNPSrm                   $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VANDNPSZ128rm                        $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VANDNPSrr                   $xmm0, $xmm1
-  $xmm0 = VANDNPSZ128rr                        $xmm0, $xmm1                                        
+  $xmm0 = VANDNPSZ128rr                        $xmm0, $xmm1
   ; CHECK: $xmm0 = VANDPDrm                    $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VANDPDZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm0 = VANDPDrr                    $xmm0, $xmm1  
-  $xmm0 = VANDPDZ128rr                         $xmm0, $xmm1                                        
+  ; CHECK: $xmm0 = VANDPDrr                    $xmm0, $xmm1
+  $xmm0 = VANDPDZ128rr                         $xmm0, $xmm1
   ; CHECK: $xmm0 = VANDPSrm                    $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VANDPSZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VANDPSrr                    $xmm0, $xmm1
-  $xmm0 = VANDPSZ128rr                         $xmm0, $xmm1                                        
+  $xmm0 = VANDPSZ128rr                         $xmm0, $xmm1
   ; CHECK: $xmm0 = VDIVPDrm                    $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   $xmm0 = VDIVPDZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $xmm0 = VDIVPDrr                    $xmm0, $xmm1, implicit $mxcsr
@@ -1290,11 +1290,11 @@ body: |
   ; CHECK: $xmm0 = VPXORrm                     $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPXORDZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPXORrr                     $xmm0, $xmm1
-  $xmm0 = VPXORDZ128rr                         $xmm0, $xmm1                                        
+  $xmm0 = VPXORDZ128rr                         $xmm0, $xmm1
   ; CHECK: $xmm0 = VPXORrm                     $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPXORQZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPXORrr                     $xmm0, $xmm1
-  $xmm0 = VPXORQZ128rr                         $xmm0, $xmm1                                        
+  $xmm0 = VPXORQZ128rr                         $xmm0, $xmm1
   ; CHECK: $xmm0 = VSUBPDrm                    $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   $xmm0 = VSUBPDZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $xmm0 = VSUBPDrr                    $xmm0, $xmm1, implicit $mxcsr
@@ -1306,83 +1306,83 @@ body: |
   ; CHECK: $xmm0 = VXORPDrm                    $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VXORPDZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VXORPDrr                    $xmm0, $xmm1
-  $xmm0 = VXORPDZ128rr                         $xmm0, $xmm1                                        
+  $xmm0 = VXORPDZ128rr                         $xmm0, $xmm1
   ; CHECK: $xmm0 = VXORPSrm                    $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VXORPSZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VXORPSrr                    $xmm0, $xmm1
-  $xmm0 = VXORPSZ128rr                         $xmm0, $xmm1                                        
+  $xmm0 = VXORPSZ128rr                         $xmm0, $xmm1
   ; CHECK: $xmm0 = VPMADDUBSWrm                $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMADDUBSWZ128rm                     $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPMADDUBSWrr                $xmm0, $xmm1
-  $xmm0 = VPMADDUBSWZ128rr                     $xmm0, $xmm1                                        
+  $xmm0 = VPMADDUBSWZ128rr                     $xmm0, $xmm1
   ; CHECK: $xmm0 = VPMADDWDrm                  $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPMADDWDZ128rm                       $xmm0, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm0 = VPMADDWDrr                  $xmm0, $xmm1                            
-  $xmm0 = VPMADDWDZ128rr                       $xmm0, $xmm1                                                 
+  ; CHECK: $xmm0 = VPMADDWDrr                  $xmm0, $xmm1
+  $xmm0 = VPMADDWDZ128rr                       $xmm0, $xmm1
   ; CHECK: $xmm0 = VPACKSSDWrm                 $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPACKSSDWZ128rm                      $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPACKSSDWrr                 $xmm0, $xmm1
-  $xmm0 = VPACKSSDWZ128rr                      $xmm0, $xmm1                                        
+  $xmm0 = VPACKSSDWZ128rr                      $xmm0, $xmm1
   ; CHECK: $xmm0 = VPACKSSWBrm                 $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPACKSSWBZ128rm                      $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPACKSSWBrr                 $xmm0, $xmm1
-  $xmm0 = VPACKSSWBZ128rr                      $xmm0, $xmm1                                        
+  $xmm0 = VPACKSSWBZ128rr                      $xmm0, $xmm1
   ; CHECK: $xmm0 = VPACKUSDWrm                 $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPACKUSDWZ128rm                      $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPACKUSDWrr                 $xmm0, $xmm1
-  $xmm0 = VPACKUSDWZ128rr                      $xmm0, $xmm1                                        
+  $xmm0 = VPACKUSDWZ128rr                      $xmm0, $xmm1
   ; CHECK: $xmm0 = VPACKUSWBrm                 $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPACKUSWBZ128rm                      $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPACKUSWBrr                 $xmm0, $xmm1
-  $xmm0 = VPACKUSWBZ128rr                      $xmm0, $xmm1                                        
+  $xmm0 = VPACKUSWBZ128rr                      $xmm0, $xmm1
   ; CHECK: $xmm0 = VPUNPCKHBWrm                $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPUNPCKHBWZ128rm                     $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPUNPCKHBWrr                $xmm0, $xmm1
-  $xmm0 = VPUNPCKHBWZ128rr                     $xmm0, $xmm1                                        
+  $xmm0 = VPUNPCKHBWZ128rr                     $xmm0, $xmm1
   ; CHECK: $xmm0 = VPUNPCKHDQrm                $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPUNPCKHDQZ128rm                     $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPUNPCKHDQrr                $xmm0, $xmm1
-  $xmm0 = VPUNPCKHDQZ128rr                     $xmm0, $xmm1                                        
+  $xmm0 = VPUNPCKHDQZ128rr                     $xmm0, $xmm1
   ; CHECK: $xmm0 = VPUNPCKHQDQrm               $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPUNPCKHQDQZ128rm                    $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPUNPCKHQDQrr               $xmm0, $xmm1
-  $xmm0 = VPUNPCKHQDQZ128rr                    $xmm0, $xmm1                                        
+  $xmm0 = VPUNPCKHQDQZ128rr                    $xmm0, $xmm1
   ; CHECK: $xmm0 = VPUNPCKHWDrm                $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPUNPCKHWDZ128rm                     $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPUNPCKHWDrr                $xmm0, $xmm1
-  $xmm0 = VPUNPCKHWDZ128rr                     $xmm0, $xmm1                                        
+  $xmm0 = VPUNPCKHWDZ128rr                     $xmm0, $xmm1
   ; CHECK: $xmm0 = VPUNPCKLBWrm                $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPUNPCKLBWZ128rm                     $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPUNPCKLBWrr                $xmm0, $xmm1
-  $xmm0 = VPUNPCKLBWZ128rr                     $xmm0, $xmm1                                        
+  $xmm0 = VPUNPCKLBWZ128rr                     $xmm0, $xmm1
   ; CHECK: $xmm0 = VPUNPCKLDQrm                $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPUNPCKLDQZ128rm                     $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPUNPCKLDQrr                $xmm0, $xmm1
-  $xmm0 = VPUNPCKLDQZ128rr                     $xmm0, $xmm1                                        
+  $xmm0 = VPUNPCKLDQZ128rr                     $xmm0, $xmm1
   ; CHECK: $xmm0 = VPUNPCKLQDQrm               $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPUNPCKLQDQZ128rm                    $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPUNPCKLQDQrr               $xmm0, $xmm1
-  $xmm0 = VPUNPCKLQDQZ128rr                    $xmm0, $xmm1                                        
+  $xmm0 = VPUNPCKLQDQZ128rr                    $xmm0, $xmm1
   ; CHECK: $xmm0 = VPUNPCKLWDrm                $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPUNPCKLWDZ128rm                     $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPUNPCKLWDrr                $xmm0, $xmm1
-  $xmm0 = VPUNPCKLWDZ128rr                     $xmm0, $xmm1                                        
+  $xmm0 = VPUNPCKLWDZ128rr                     $xmm0, $xmm1
   ; CHECK: $xmm0 = VUNPCKHPDrm                 $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VUNPCKHPDZ128rm                      $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VUNPCKHPDrr                 $xmm0, $xmm1
-  $xmm0 = VUNPCKHPDZ128rr                      $xmm0, $xmm1                                        
+  $xmm0 = VUNPCKHPDZ128rr                      $xmm0, $xmm1
   ; CHECK: $xmm0 = VUNPCKHPSrm                 $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VUNPCKHPSZ128rm                      $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VUNPCKHPSrr                 $xmm0, $xmm1
-  $xmm0 = VUNPCKHPSZ128rr                      $xmm0, $xmm1                                        
+  $xmm0 = VUNPCKHPSZ128rr                      $xmm0, $xmm1
   ; CHECK: $xmm0 = VUNPCKLPDrm                 $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VUNPCKLPDZ128rm                      $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VUNPCKLPDrr                 $xmm0, $xmm1
-  $xmm0 = VUNPCKLPDZ128rr                      $xmm0, $xmm1                                        
+  $xmm0 = VUNPCKLPDZ128rr                      $xmm0, $xmm1
   ; CHECK: $xmm0 = VUNPCKLPSrm                 $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VUNPCKLPSZ128rm                      $xmm0, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm0 = VUNPCKLPSrr                 $xmm0, $xmm1                            
-  $xmm0 = VUNPCKLPSZ128rr                      $xmm0, $xmm1                                                                                              
+  ; CHECK: $xmm0 = VUNPCKLPSrr                 $xmm0, $xmm1
+  $xmm0 = VUNPCKLPSZ128rr                      $xmm0, $xmm1
   ; CHECK: $xmm0 = VFMADD132PDm                $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
   $xmm0 = VFMADD132PDZ128m                     $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $xmm0 = VFMADD132PDr                $xmm0, $xmm1, $xmm2, implicit $mxcsr
@@ -1528,13 +1528,13 @@ body: |
   ; CHECK: $xmm0 = VFNMSUB231PSr               $xmm0, $xmm1, $xmm2, implicit $mxcsr
   $xmm0 = VFNMSUB231PSZ128r                    $xmm0, $xmm1, $xmm2, implicit $mxcsr
   ; CHECK: $xmm0 = VPSLLDri                    $xmm0, 7
-  $xmm0 = VPSLLDZ128ri                         $xmm0, 7                                            
+  $xmm0 = VPSLLDZ128ri                         $xmm0, 7
   ; CHECK: $xmm0 = VPSLLDrm                    $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPSLLDZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPSLLDrr                    $xmm0, $xmm0
   $xmm0 = VPSLLDZ128rr                         $xmm0, $xmm0
   ; CHECK: $xmm0 = VPSLLQri                    $xmm0, 7
-  $xmm0 = VPSLLQZ128ri                         $xmm0, 7                                            
+  $xmm0 = VPSLLQZ128ri                         $xmm0, 7
   ; CHECK: $xmm0 = VPSLLQrm                    $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPSLLQZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPSLLQrr                    $xmm0, $xmm0
@@ -1548,13 +1548,13 @@ body: |
   ; CHECK: $xmm0 = VPSLLVQrr                   $xmm0, $xmm0
   $xmm0 = VPSLLVQZ128rr                        $xmm0, $xmm0
   ; CHECK: $xmm0 = VPSLLWri                    $xmm0, 7
-  $xmm0 = VPSLLWZ128ri                         $xmm0, 7                                            
+  $xmm0 = VPSLLWZ128ri                         $xmm0, 7
   ; CHECK: $xmm0 = VPSLLWrm                    $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPSLLWZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPSLLWrr                    $xmm0, $xmm0
   $xmm0 = VPSLLWZ128rr                         $xmm0, $xmm0
   ; CHECK: $xmm0 = VPSRADri                    $xmm0, 7
-  $xmm0 = VPSRADZ128ri                         $xmm0, 7                                            
+  $xmm0 = VPSRADZ128ri                         $xmm0, 7
   ; CHECK: $xmm0 = VPSRADrm                    $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPSRADZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPSRADrr                    $xmm0, $xmm0
@@ -1563,22 +1563,22 @@ body: |
   $xmm0 = VPSRAVDZ128rm                        $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPSRAVDrr                   $xmm0, $xmm0
   $xmm0 = VPSRAVDZ128rr                        $xmm0, $xmm0
-  ; CHECK: $xmm0 = VPSRAWri                    $xmm0, 7 
-  $xmm0 = VPSRAWZ128ri                         $xmm0, 7                                            
+  ; CHECK: $xmm0 = VPSRAWri                    $xmm0, 7
+  $xmm0 = VPSRAWZ128ri                         $xmm0, 7
   ; CHECK: $xmm0 = VPSRAWrm                    $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPSRAWZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPSRAWrr                    $xmm0, $xmm0
   $xmm0 = VPSRAWZ128rr                         $xmm0, $xmm0
   ; CHECK: $xmm0 = VPSRLDQri                   $xmm0, 14
-  $xmm0 = VPSRLDQZ128ri                        $xmm0, 14                                           
-  ; CHECK: $xmm0 = VPSRLDri                    $xmm0, 7 
-  $xmm0 = VPSRLDZ128ri                         $xmm0, 7                                            
+  $xmm0 = VPSRLDQZ128ri                        $xmm0, 14
+  ; CHECK: $xmm0 = VPSRLDri                    $xmm0, 7
+  $xmm0 = VPSRLDZ128ri                         $xmm0, 7
   ; CHECK: $xmm0 = VPSRLDrm                    $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPSRLDZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPSRLDrr                    $xmm0, $xmm0
   $xmm0 = VPSRLDZ128rr                         $xmm0, $xmm0
-  ; CHECK: $xmm0 = VPSRLQri                    $xmm0, 7 
-  $xmm0 = VPSRLQZ128ri                         $xmm0, 7                                            
+  ; CHECK: $xmm0 = VPSRLQri                    $xmm0, 7
+  $xmm0 = VPSRLQZ128ri                         $xmm0, 7
   ; CHECK: $xmm0 = VPSRLQrm                    $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPSRLQZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPSRLQrr                    $xmm0, $xmm0
@@ -1592,7 +1592,7 @@ body: |
   ; CHECK: $xmm0 = VPSRLVQrr                   $xmm0, $xmm0
   $xmm0 = VPSRLVQZ128rr                        $xmm0, $xmm0
   ; CHECK: $xmm0 = VPSRLWri                    $xmm0, 7
-  $xmm0 = VPSRLWZ128ri                         $xmm0, 7                                            
+  $xmm0 = VPSRLWZ128ri                         $xmm0, 7
   ; CHECK: $xmm0 = VPSRLWrm                    $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPSRLWZ128rm                         $xmm0, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPSRLWrr                    $xmm0, $xmm0
@@ -1600,27 +1600,27 @@ body: |
   ; CHECK: $xmm0 = VPERMILPDmi                 $rdi, 1, $noreg, 0, $noreg, 9
   $xmm0 = VPERMILPDZ128mi                      $rdi, 1, $noreg, 0, $noreg, 9
   ; CHECK: $xmm0 = VPERMILPDri                 $xmm0, 9
-  $xmm0 = VPERMILPDZ128ri                      $xmm0, 9                                            
+  $xmm0 = VPERMILPDZ128ri                      $xmm0, 9
   ; CHECK: $xmm0 = VPERMILPDrm                 $xmm0, $rdi, 1, $noreg, 0, $noreg
-  $xmm0 = VPERMILPDZ128rm                      $xmm0, $rdi, 1, $noreg, 0, $noreg                             
+  $xmm0 = VPERMILPDZ128rm                      $xmm0, $rdi, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPERMILPDrr                 $xmm0, $xmm1
-  $xmm0 = VPERMILPDZ128rr                      $xmm0, $xmm1                                        
+  $xmm0 = VPERMILPDZ128rr                      $xmm0, $xmm1
   ; CHECK: $xmm0 = VPERMILPSmi                 $rdi, 1, $noreg, 0, $noreg, 9
   $xmm0 = VPERMILPSZ128mi                      $rdi, 1, $noreg, 0, $noreg, 9
   ; CHECK: $xmm0 = VPERMILPSri                 $xmm0, 9
-  $xmm0 = VPERMILPSZ128ri                      $xmm0, 9                                            
+  $xmm0 = VPERMILPSZ128ri                      $xmm0, 9
   ; CHECK: $xmm0 = VPERMILPSrm                 $xmm0, $rdi, 1, $noreg, 0, $noreg
-  $xmm0 = VPERMILPSZ128rm                      $xmm0, $rdi, 1, $noreg, 0, $noreg                             
-  ; CHECK: $xmm0 = VPERMILPSrr                 $xmm0, $xmm1                            
-  $xmm0 = VPERMILPSZ128rr                      $xmm0, $xmm1                                               
+  $xmm0 = VPERMILPSZ128rm                      $xmm0, $rdi, 1, $noreg, 0, $noreg
+  ; CHECK: $xmm0 = VPERMILPSrr                 $xmm0, $xmm1
+  $xmm0 = VPERMILPSZ128rr                      $xmm0, $xmm1
   ; CHECK: $xmm0 = VCVTPH2PSrm                 $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
   $xmm0 = VCVTPH2PSZ128rm                      $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $xmm0 = VCVTPH2PSrr                 $xmm0, implicit $mxcsr
   $xmm0 = VCVTPH2PSZ128rr                      $xmm0, implicit $mxcsr
   ; CHECK: $xmm0 = VCVTDQ2PDrm                 $rdi, 1, $noreg, 0, $noreg
   $xmm0 = VCVTDQ2PDZ128rm                      $rdi, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm0 = VCVTDQ2PDrr                 $xmm0     
-  $xmm0 = VCVTDQ2PDZ128rr                      $xmm0                                               
+  ; CHECK: $xmm0 = VCVTDQ2PDrr                 $xmm0
+  $xmm0 = VCVTDQ2PDZ128rr                      $xmm0
   ; CHECK: $xmm0 = VCVTDQ2PSrm                 $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
   $xmm0 = VCVTDQ2PSZ128rm                      $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $xmm0 = VCVTDQ2PSrr                 $xmm0, implicit $mxcsr
@@ -1657,34 +1657,34 @@ body: |
   $xmm0 = VSQRTPSZ128m                         $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $xmm0 = VSQRTPSr                    $xmm0, implicit $mxcsr
   $xmm0 = VSQRTPSZ128r                         $xmm0, implicit $mxcsr
-  ; CHECK: $xmm0 = VMOVDDUPrm                  $rdi, 1, $noreg, 0, $noreg     
-  $xmm0 = VMOVDDUPZ128rm                       $rdi, 1, $noreg, 0, $noreg                                    
-  ; CHECK: $xmm0 = VMOVDDUPrr                  $xmm0    
-  $xmm0 = VMOVDDUPZ128rr                       $xmm0                                               
-  ; CHECK: $xmm0 = VMOVSHDUPrm                 $rdi, 1, $noreg, 0, $noreg    
-  $xmm0 = VMOVSHDUPZ128rm                      $rdi, 1, $noreg, 0, $noreg                                    
-  ; CHECK: $xmm0 = VMOVSHDUPrr                 $xmm0    
-  $xmm0 = VMOVSHDUPZ128rr                      $xmm0                                               
-  ; CHECK: $xmm0 = VMOVSLDUPrm                 $rdi, 1, $noreg, 0, $noreg     
-  $xmm0 = VMOVSLDUPZ128rm                      $rdi, 1, $noreg, 0, $noreg                                    
-  ; CHECK: $xmm0 = VMOVSLDUPrr                 $xmm0                                   
-  $xmm0 = VMOVSLDUPZ128rr                      $xmm0                                                                  
+  ; CHECK: $xmm0 = VMOVDDUPrm                  $rdi, 1, $noreg, 0, $noreg
+  $xmm0 = VMOVDDUPZ128rm                       $rdi, 1, $noreg, 0, $noreg
+  ; CHECK: $xmm0 = VMOVDDUPrr                  $xmm0
+  $xmm0 = VMOVDDUPZ128rr                       $xmm0
+  ; CHECK: $xmm0 = VMOVSHDUPrm                 $rdi, 1, $noreg, 0, $noreg
+  $xmm0 = VMOVSHDUPZ128rm                      $rdi, 1, $noreg, 0, $noreg
+  ; CHECK: $xmm0 = VMOVSHDUPrr                 $xmm0
+  $xmm0 = VMOVSHDUPZ128rr                      $xmm0
+  ; CHECK: $xmm0 = VMOVSLDUPrm                 $rdi, 1, $noreg, 0, $noreg
+  $xmm0 = VMOVSLDUPZ128rm                      $rdi, 1, $noreg, 0, $noreg
+  ; CHECK: $xmm0 = VMOVSLDUPrr                 $xmm0
+  $xmm0 = VMOVSLDUPZ128rr                      $xmm0
   ; CHECK: $xmm0 = VPSHUFBrm                   $xmm0, $rdi, 1, $noreg, 0, $noreg
   $xmm0 = VPSHUFBZ128rm                        $xmm0, $rdi, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPSHUFBrr                   $xmm0, $xmm1
-  $xmm0 = VPSHUFBZ128rr                        $xmm0, $xmm1                                        
+  $xmm0 = VPSHUFBZ128rr                        $xmm0, $xmm1
   ; CHECK: $xmm0 = VPSHUFDmi                   $rdi, 1, $noreg, 0, $noreg, -24
   $xmm0 = VPSHUFDZ128mi                        $rdi, 1, $noreg, 0, $noreg, -24
   ; CHECK: $xmm0 = VPSHUFDri                   $xmm0, -24
-  $xmm0 = VPSHUFDZ128ri                        $xmm0, -24                                          
+  $xmm0 = VPSHUFDZ128ri                        $xmm0, -24
   ; CHECK: $xmm0 = VPSHUFHWmi                  $rdi, 1, $noreg, 0, $noreg, -24
   $xmm0 = VPSHUFHWZ128mi                       $rdi, 1, $noreg, 0, $noreg, -24
   ; CHECK: $xmm0 = VPSHUFHWri                  $xmm0, -24
-  $xmm0 = VPSHUFHWZ128ri                       $xmm0, -24                                          
+  $xmm0 = VPSHUFHWZ128ri                       $xmm0, -24
   ; CHECK: $xmm0 = VPSHUFLWmi                  $rdi, 1, $noreg, 0, $noreg, -24
   $xmm0 = VPSHUFLWZ128mi                       $rdi, 1, $noreg, 0, $noreg, -24
   ; CHECK: $xmm0 = VPSHUFLWri                  $xmm0, -24
-  $xmm0 = VPSHUFLWZ128ri                       $xmm0, -24                                          
+  $xmm0 = VPSHUFLWZ128ri                       $xmm0, -24
   ; CHECK: $xmm0 = VPSLLDQri                   $xmm0, 7
   $xmm0 = VPSLLDQZ128ri                        $xmm0, 7
   ; CHECK: $xmm0 = VSHUFPDrmi                  $xmm0, $rip, 1, $noreg, 0, $noreg, -24
@@ -1697,28 +1697,28 @@ body: |
   $xmm0 = VSHUFPSZ128rri                       $xmm0, $xmm1, -24
   ; CHECK: $xmm0 = VPSADBWrm                   $xmm0, $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPSADBWZ128rm                        $xmm0, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm0 = VPSADBWrr                   $xmm0, $xmm1                            
-  $xmm0 = VPSADBWZ128rr                        $xmm0, $xmm1                                               
+  ; CHECK: $xmm0 = VPSADBWrr                   $xmm0, $xmm1
+  $xmm0 = VPSADBWZ128rr                        $xmm0, $xmm1
   ; CHECK: $xmm0 = VBROADCASTSSrm              $rip, 1, $noreg, 0, $noreg
   $xmm0 = VBROADCASTSSZ128rm                   $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VBROADCASTSSrr              $xmm0
-  $xmm0 = VBROADCASTSSZ128rr                   $xmm0                                               
+  $xmm0 = VBROADCASTSSZ128rr                   $xmm0
   ; CHECK: $xmm0 = VPBROADCASTBrm              $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPBROADCASTBZ128rm                   $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPBROADCASTBrr              $xmm0
-  $xmm0 = VPBROADCASTBZ128rr                   $xmm0                                               
+  $xmm0 = VPBROADCASTBZ128rr                   $xmm0
   ; CHECK: $xmm0 = VPBROADCASTDrm              $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPBROADCASTDZ128rm                   $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPBROADCASTDrr              $xmm0
-  $xmm0 = VPBROADCASTDZ128rr                   $xmm0                                               
+  $xmm0 = VPBROADCASTDZ128rr                   $xmm0
   ; CHECK: $xmm0 = VPBROADCASTQrm              $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPBROADCASTQZ128rm                   $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPBROADCASTQrr              $xmm0
-  $xmm0 = VPBROADCASTQZ128rr                   $xmm0                                               
+  $xmm0 = VPBROADCASTQZ128rr                   $xmm0
   ; CHECK: $xmm0 = VPBROADCASTWrm              $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPBROADCASTWZ128rm                   $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm0 = VPBROADCASTWrr              $xmm0                                   
-  $xmm0 = VPBROADCASTWZ128rr                   $xmm0                                                                                             
+  ; CHECK: $xmm0 = VPBROADCASTWrr              $xmm0
+  $xmm0 = VPBROADCASTWZ128rr                   $xmm0
   ; CHECK: $xmm0 = VPBROADCASTQrm              $rip, 1, $noreg, 0, $noreg
   $xmm0 = VBROADCASTI32X2Z128rm                $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPBROADCASTQrr              $xmm0
@@ -1730,15 +1730,15 @@ body: |
   ; CHECK: $xmm0 = VPABSBrm                    $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPABSBZ128rm                         $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPABSBrr                    $xmm0
-  $xmm0 = VPABSBZ128rr                         $xmm0                                               
+  $xmm0 = VPABSBZ128rr                         $xmm0
   ; CHECK: $xmm0 = VPABSDrm                    $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPABSDZ128rm                         $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPABSDrr                    $xmm0
-  $xmm0 = VPABSDZ128rr                         $xmm0                                               
+  $xmm0 = VPABSDZ128rr                         $xmm0
   ; CHECK: $xmm0 = VPABSWrm                    $rip, 1, $noreg, 0, $noreg
   $xmm0 = VPABSWZ128rm                         $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VPABSWrr                    $xmm0
-  $xmm0 = VPABSWZ128rr                         $xmm0                                               
+  $xmm0 = VPABSWZ128rr                         $xmm0
   ; CHECK: $xmm0 = VPALIGNRrmi                 $xmm0, $rip, 1, $noreg, 0, $noreg, 15
   $xmm0 = VPALIGNRZ128rmi                      $xmm0, $rip, 1, $noreg, 0, $noreg, 15
   ; CHECK: $xmm0 = VPALIGNRrri                 $xmm0, $xmm1, 15
@@ -2074,38 +2074,38 @@ body: |
   $xmm0 = VFNMSUB231SSZr                       $xmm0, $xmm1, $xmm2, implicit $mxcsr
   ; CHECK: $xmm0 = VFNMSUB231SSr_Int           $xmm0, $xmm1, $xmm2, implicit $mxcsr
   $xmm0 = VFNMSUB231SSZr_Int                   $xmm0, $xmm1, $xmm2, implicit $mxcsr
-  ; CHECK: VPEXTRBmr                           $rdi, 1, $noreg, 0, $noreg, $xmm0, 3       
-  VPEXTRBZmr                                   $rdi, 1, $noreg, 0, $noreg, $xmm0, 3                              
-  ; CHECK: $eax = VPEXTRBrr                    $xmm0, 1    
-  $eax = VPEXTRBZrr                            $xmm0, 1                                                
-  ; CHECK: VPEXTRDmr                           $rdi, 1, $noreg, 0, $noreg, $xmm0, 3      
-  VPEXTRDZmr                                   $rdi, 1, $noreg, 0, $noreg, $xmm0, 3                              
-  ; CHECK: $eax = VPEXTRDrr                    $xmm0, 1     
-  $eax = VPEXTRDZrr                            $xmm0, 1                                                
-  ; CHECK: VPEXTRQmr                           $rdi, 1, $noreg, 0, $noreg, $xmm0, 3       
-  VPEXTRQZmr                                   $rdi, 1, $noreg, 0, $noreg, $xmm0, 3                              
-  ; CHECK: $rax = VPEXTRQrr                    $xmm0, 1      
-  $rax = VPEXTRQZrr                            $xmm0, 1                                                
-  ; CHECK: VPEXTRWmr                           $rdi, 1, $noreg, 0, $noreg,  $xmm0, 3       
-  VPEXTRWZmr                                   $rdi, 1, $noreg, 0, $noreg,  $xmm0, 3                             
-  ; CHECK: $eax = VPEXTRWrr                    $xmm0, 1                                                     
-  $eax = VPEXTRWZrr                            $xmm0, 1                                                    
-  ; CHECK: $xmm0 = VPINSRBrm                   $xmm0, $rsi, 1, $noreg, 0, $noreg, 3      
-  $xmm0 = VPINSRBZrm                           $xmm0, $rsi, 1, $noreg, 0, $noreg, 3                              
-  ; CHECK: $xmm0 = VPINSRBrr                   $xmm0, $edi, 5      
-  $xmm0 = VPINSRBZrr                           $xmm0, $edi, 5                                          
-  ; CHECK: $xmm0 = VPINSRDrm                   $xmm0, $rsi, 1, $noreg, 0, $noreg, 3      
-  $xmm0 = VPINSRDZrm                           $xmm0, $rsi, 1, $noreg, 0, $noreg, 3                              
-  ; CHECK: $xmm0 = VPINSRDrr                   $xmm0, $edi, 5            
-  $xmm0 = VPINSRDZrr                           $xmm0, $edi, 5                                          
-  ; CHECK: $xmm0 = VPINSRQrm                   $xmm0, $rsi, 1, $noreg, 0, $noreg, 3      
-  $xmm0 = VPINSRQZrm                           $xmm0, $rsi, 1, $noreg, 0, $noreg, 3                              
-  ; CHECK: $xmm0 = VPINSRQrr                   $xmm0, $rdi, 5            
-  $xmm0 = VPINSRQZrr                           $xmm0, $rdi, 5                                          
-  ; CHECK: $xmm0 = VPINSRWrm                   $xmm0, $rsi, 1, $noreg, 0, $noreg, 3      
-  $xmm0 = VPINSRWZrm                           $xmm0, $rsi, 1, $noreg, 0, $noreg, 3                              
-  ; CHECK: $xmm0 = VPINSRWrr                   $xmm0, $edi, 5                                               
-  $xmm0 = VPINSRWZrr                           $xmm0, $edi, 5                                              
+  ; CHECK: VPEXTRBmr                           $rdi, 1, $noreg, 0, $noreg, $xmm0, 3
+  VPEXTRBZmr                                   $rdi, 1, $noreg, 0, $noreg, $xmm0, 3
+  ; CHECK: $eax = VPEXTRBrr                    $xmm0, 1
+  $eax = VPEXTRBZrr                            $xmm0, 1
+  ; CHECK: VPEXTRDmr                           $rdi, 1, $noreg, 0, $noreg, $xmm0, 3
+  VPEXTRDZmr                                   $rdi, 1, $noreg, 0, $noreg, $xmm0, 3
+  ; CHECK: $eax = VPEXTRDrr                    $xmm0, 1
+  $eax = VPEXTRDZrr                            $xmm0, 1
+  ; CHECK: VPEXTRQmr                           $rdi, 1, $noreg, 0, $noreg, $xmm0, 3
+  VPEXTRQZmr                                   $rdi, 1, $noreg, 0, $noreg, $xmm0, 3
+  ; CHECK: $rax = VPEXTRQrr                    $xmm0, 1
+  $rax = VPEXTRQZrr                            $xmm0, 1
+  ; CHECK: VPEXTRWmr                           $rdi, 1, $noreg, 0, $noreg,  $xmm0, 3
+  VPEXTRWZmr                                   $rdi, 1, $noreg, 0, $noreg,  $xmm0, 3
+  ; CHECK: $eax = VPEXTRWrr                    $xmm0, 1
+  $eax = VPEXTRWZrr                            $xmm0, 1
+  ; CHECK: $xmm0 = VPINSRBrm                   $xmm0, $rsi, 1, $noreg, 0, $noreg, 3
+  $xmm0 = VPINSRBZrm                           $xmm0, $rsi, 1, $noreg, 0, $noreg, 3
+  ; CHECK: $xmm0 = VPINSRBrr                   $xmm0, $edi, 5
+  $xmm0 = VPINSRBZrr                           $xmm0, $edi, 5
+  ; CHECK: $xmm0 = VPINSRDrm                   $xmm0, $rsi, 1, $noreg, 0, $noreg, 3
+  $xmm0 = VPINSRDZrm                           $xmm0, $rsi, 1, $noreg, 0, $noreg, 3
+  ; CHECK: $xmm0 = VPINSRDrr                   $xmm0, $edi, 5
+  $xmm0 = VPINSRDZrr                           $xmm0, $edi, 5
+  ; CHECK: $xmm0 = VPINSRQrm                   $xmm0, $rsi, 1, $noreg, 0, $noreg, 3
+  $xmm0 = VPINSRQZrm                           $xmm0, $rsi, 1, $noreg, 0, $noreg, 3
+  ; CHECK: $xmm0 = VPINSRQrr                   $xmm0, $rdi, 5
+  $xmm0 = VPINSRQZrr                           $xmm0, $rdi, 5
+  ; CHECK: $xmm0 = VPINSRWrm                   $xmm0, $rsi, 1, $noreg, 0, $noreg, 3
+  $xmm0 = VPINSRWZrm                           $xmm0, $rsi, 1, $noreg, 0, $noreg, 3
+  ; CHECK: $xmm0 = VPINSRWrr                   $xmm0, $edi, 5
+  $xmm0 = VPINSRWZrr                           $xmm0, $edi, 5
   ; CHECK: $xmm0 = VSQRTSDm                    $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
   $xmm0 = VSQRTSDZm                            $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $xmm0 = VSQRTSDm_Int                $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
@@ -2135,9 +2135,9 @@ body: |
   ; CHECK: $xmm0 = VCVTSD2SSrr_Int             $xmm0, $xmm1, implicit $mxcsr
   $xmm0 = VCVTSD2SSZrr_Int                     $xmm0, $xmm1, implicit $mxcsr
   ; CHECK: $xmm0 = VCVTSI2SDrm                 $xmm0, $rdi, 1, $noreg, 0, $noreg
-  $xmm0 = VCVTSI2SDZrm                         $xmm0, $rdi, 1, $noreg, 0, $noreg                                 
+  $xmm0 = VCVTSI2SDZrm                         $xmm0, $rdi, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VCVTSI2SDrm_Int             $xmm0, $rdi, 1, $noreg, 0, $noreg
-  $xmm0 = VCVTSI2SDZrm_Int                     $xmm0, $rdi, 1, $noreg, 0, $noreg                                 
+  $xmm0 = VCVTSI2SDZrm_Int                     $xmm0, $rdi, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VCVTSI2SDrr                 $xmm0, $edi
   $xmm0 = VCVTSI2SDZrr                         $xmm0, $edi
   ; CHECK: $xmm0 = VCVTSI2SDrr_Int             $xmm0, $edi
@@ -2214,10 +2214,10 @@ body: |
   $edi = VCVTTSS2SIZrr                         $xmm0, implicit $mxcsr
   ; CHECK: $edi = VCVTTSS2SIrr_Int             $xmm0, implicit $mxcsr
   $edi = VCVTTSS2SIZrr_Int                     $xmm0, implicit $mxcsr
-  ; CHECK: $xmm0 = VMOV64toSDrr                $rdi    
-  $xmm0 = VMOV64toSDZrr                        $rdi                                                    
+  ; CHECK: $xmm0 = VMOV64toSDrr                $rdi
+  $xmm0 = VMOV64toSDZrr                        $rdi
   ; CHECK: $xmm0 = VMOVDI2SSrr                 $eax
-  $xmm0 = VMOVDI2SSZrr                         $eax                                                    
+  $xmm0 = VMOVDI2SSZrr                         $eax
   ; CHECK: VMOVSDmr                            $rdi, 1, $noreg, 0, $noreg, $xmm0
   VMOVSDZmr                                    $rdi, 1, $noreg, 0, $noreg, $xmm0
   ; CHECK: $xmm0 = VMOVSDrm                    $rip, 1, $noreg, 0, $noreg
@@ -2239,15 +2239,15 @@ body: |
   ; CHECK: $eax = VMOVSS2DIrr                  $xmm0
   $eax = VMOVSS2DIZrr                          $xmm0
   ; CHECK: $xmm0 = VMOV64toPQIrr               $rdi
-  $xmm0 = VMOV64toPQIZrr                       $rdi                                                    
+  $xmm0 = VMOV64toPQIZrr                       $rdi
   ; CHECK: $xmm0 = VMOV64toPQIrm               $rdi, 1, $noreg, 0, $noreg
   $xmm0 = VMOV64toPQIZrm                       $rdi, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm0 = VMOV64toSDrr                $rdi 
-  $xmm0 = VMOV64toSDZrr                        $rdi                                                    
+  ; CHECK: $xmm0 = VMOV64toSDrr                $rdi
+  $xmm0 = VMOV64toSDZrr                        $rdi
   ; CHECK: $xmm0 = VMOVDI2PDIrm                $rip, 1, $noreg, 0, $noreg
   $xmm0 = VMOVDI2PDIZrm                        $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm0 = VMOVDI2PDIrr                $edi
-  $xmm0 = VMOVDI2PDIZrr                        $edi                                                    
+  $xmm0 = VMOVDI2PDIZrr                        $edi
   ; CHECK: $xmm0 = VMOVLHPSrr                  $xmm0, $xmm1
   $xmm0 = VMOVLHPSZrr                          $xmm0, $xmm1
   ; CHECK: $xmm0 = VMOVHLPSrr                  $xmm0, $xmm1
@@ -2261,13 +2261,13 @@ body: |
   ; CHECK: VMOVPQI2QImr                        $rdi, 1, $noreg, 0, $noreg, $xmm0
   VMOVPQI2QIZmr                                $rdi, 1, $noreg, 0, $noreg, $xmm0
   ; CHECK: $rdi = VMOVPQIto64rr                $xmm0
-  $rdi = VMOVPQIto64Zrr                        $xmm0                                                   
+  $rdi = VMOVPQIto64Zrr                        $xmm0
   ; CHECK: VMOVPQIto64mr                       $rdi, 1, $noreg, 0, $noreg, $xmm0
   VMOVPQIto64Zmr                               $rdi, 1, $noreg, 0, $noreg, $xmm0
   ; CHECK: $xmm0 = VMOVQI2PQIrm                $rip, 1, $noreg, 0, $noreg
   $xmm0 = VMOVQI2PQIZrm                        $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm0 = VMOVZPQILo2PQIrr            $xmm0                                               
-  $xmm0 = VMOVZPQILo2PQIZrr                    $xmm0                                                   
+  ; CHECK: $xmm0 = VMOVZPQILo2PQIrr            $xmm0
+  $xmm0 = VMOVZPQILo2PQIZrr                    $xmm0
   ; CHECK: VCOMISDrm_Int                       $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
   VCOMISDZrm_Int                               $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
   ; CHECK: VCOMISDrr_Int                       $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
@@ -2335,137 +2335,137 @@ name: evex_z256_to_evex_test
 body: |
   bb.0:
   ; CHECK: VMOVAPDZ256mr                       $rdi, 1, $noreg, 0, $noreg, $ymm16
-  VMOVAPDZ256mr                                $rdi, 1, $noreg, 0, $noreg, $ymm16                      
+  VMOVAPDZ256mr                                $rdi, 1, $noreg, 0, $noreg, $ymm16
   ; CHECK: $ymm16 = VMOVAPDZ256rm              $rip, 1, $noreg, 0, $noreg
   $ymm16 = VMOVAPDZ256rm                       $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VMOVAPDZ256rr              $ymm16
-  $ymm16 = VMOVAPDZ256rr                       $ymm16                                        
+  $ymm16 = VMOVAPDZ256rr                       $ymm16
   ; CHECK: VMOVAPSZ256mr                       $rdi, 1, $noreg, 0, $noreg, $ymm16
-  VMOVAPSZ256mr                                $rdi, 1, $noreg, 0, $noreg, $ymm16                      
+  VMOVAPSZ256mr                                $rdi, 1, $noreg, 0, $noreg, $ymm16
   ; CHECK: $ymm16 = VMOVAPSZ256rm              $rip, 1, $noreg, 0, $noreg
   $ymm16 = VMOVAPSZ256rm                       $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VMOVAPSZ256rr              $ymm16
-  $ymm16 = VMOVAPSZ256rr                       $ymm16                                        
+  $ymm16 = VMOVAPSZ256rr                       $ymm16
   ; CHECK: $ymm16 = VMOVDDUPZ256rm             $rip, 1, $noreg, 0, $noreg
   $ymm16 = VMOVDDUPZ256rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VMOVDDUPZ256rr             $ymm16
-  $ymm16 = VMOVDDUPZ256rr                      $ymm16                                        
+  $ymm16 = VMOVDDUPZ256rr                      $ymm16
   ; CHECK: VMOVDQA32Z256mr                     $rdi, 1, $noreg, 0, $noreg, $ymm16
-  VMOVDQA32Z256mr                              $rdi, 1, $noreg, 0, $noreg, $ymm16                      
+  VMOVDQA32Z256mr                              $rdi, 1, $noreg, 0, $noreg, $ymm16
   ; CHECK: $ymm16 = VMOVDQA32Z256rm            $rip, 1, $noreg, 0, $noreg
   $ymm16 = VMOVDQA32Z256rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VMOVDQA32Z256rr            $ymm16
-  $ymm16 = VMOVDQA32Z256rr                     $ymm16                                        
+  $ymm16 = VMOVDQA32Z256rr                     $ymm16
   ; CHECK: VMOVDQA64Z256mr                     $rdi, 1, $noreg, 0, $noreg, $ymm16
-  VMOVDQA64Z256mr                              $rdi, 1, $noreg, 0, $noreg, $ymm16                      
+  VMOVDQA64Z256mr                              $rdi, 1, $noreg, 0, $noreg, $ymm16
   ; CHECK: $ymm16 = VMOVDQA64Z256rm            $rip, 1, $noreg, 0, $noreg
   $ymm16 = VMOVDQA64Z256rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VMOVDQA64Z256rr            $ymm16
-  $ymm16 = VMOVDQA64Z256rr                     $ymm16                                        
+  $ymm16 = VMOVDQA64Z256rr                     $ymm16
   ; CHECK: VMOVDQU16Z256mr                     $rdi, 1, $noreg, 0, $noreg, $ymm16
-  VMOVDQU16Z256mr                              $rdi, 1, $noreg, 0, $noreg, $ymm16                      
+  VMOVDQU16Z256mr                              $rdi, 1, $noreg, 0, $noreg, $ymm16
   ; CHECK: $ymm16 = VMOVDQU16Z256rm            $rip, 1, $noreg, 0, $noreg
   $ymm16 = VMOVDQU16Z256rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VMOVDQU16Z256rr            $ymm16
-  $ymm16 = VMOVDQU16Z256rr                     $ymm16                                        
+  $ymm16 = VMOVDQU16Z256rr                     $ymm16
   ; CHECK: VMOVDQU32Z256mr                     $rdi, 1, $noreg, 0, $noreg, $ymm16
-  VMOVDQU32Z256mr                              $rdi, 1, $noreg, 0, $noreg, $ymm16                      
+  VMOVDQU32Z256mr                              $rdi, 1, $noreg, 0, $noreg, $ymm16
   ; CHECK: $ymm16 = VMOVDQU32Z256rm            $rip, 1, $noreg, 0, $noreg
   $ymm16 = VMOVDQU32Z256rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VMOVDQU32Z256rr            $ymm16
-  $ymm16 = VMOVDQU32Z256rr                     $ymm16                                        
+  $ymm16 = VMOVDQU32Z256rr                     $ymm16
   ; CHECK: VMOVDQU64Z256mr                     $rdi, 1, $noreg, 0, $noreg, $ymm16
-  VMOVDQU64Z256mr                              $rdi, 1, $noreg, 0, $noreg, $ymm16                      
+  VMOVDQU64Z256mr                              $rdi, 1, $noreg, 0, $noreg, $ymm16
   ; CHECK: $ymm16 = VMOVDQU64Z256rm            $rip, 1, $noreg, 0, $noreg
-  $ymm16 = VMOVDQU64Z256rm                     $rip, 1, $noreg, 0, $noreg                           
+  $ymm16 = VMOVDQU64Z256rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VMOVDQU64Z256rr            $ymm16
-  $ymm16 = VMOVDQU64Z256rr                     $ymm16                                        
+  $ymm16 = VMOVDQU64Z256rr                     $ymm16
   ; CHECK: VMOVDQU8Z256mr                      $rdi, 1, $noreg, 0, $noreg, $ymm16
-  VMOVDQU8Z256mr                               $rdi, 1, $noreg, 0, $noreg, $ymm16                      
+  VMOVDQU8Z256mr                               $rdi, 1, $noreg, 0, $noreg, $ymm16
   ; CHECK: $ymm16 = VMOVDQU8Z256rm             $rip, 1, $noreg, 0, $noreg
   $ymm16 = VMOVDQU8Z256rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VMOVDQU8Z256rr             $ymm16
-  $ymm16 = VMOVDQU8Z256rr                      $ymm16                                        
+  $ymm16 = VMOVDQU8Z256rr                      $ymm16
   ; CHECK: $ymm16 = VMOVNTDQAZ256rm            $rip, 1, $noreg, 0, $noreg
   $ymm16 = VMOVNTDQAZ256rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: VMOVNTDQZ256mr                      $rdi, 1, $noreg, 0, $noreg, $ymm16
-  VMOVNTDQZ256mr                               $rdi, 1, $noreg, 0, $noreg, $ymm16                      
+  VMOVNTDQZ256mr                               $rdi, 1, $noreg, 0, $noreg, $ymm16
   ; CHECK: VMOVNTPDZ256mr                      $rdi, 1, $noreg, 0, $noreg, $ymm16
-  VMOVNTPDZ256mr                               $rdi, 1, $noreg, 0, $noreg, $ymm16                      
+  VMOVNTPDZ256mr                               $rdi, 1, $noreg, 0, $noreg, $ymm16
   ; CHECK: VMOVNTPSZ256mr                      $rdi, 1, $noreg, 0, $noreg, $ymm16
-  VMOVNTPSZ256mr                               $rdi, 1, $noreg, 0, $noreg, $ymm16                      
+  VMOVNTPSZ256mr                               $rdi, 1, $noreg, 0, $noreg, $ymm16
   ; CHECK: $ymm16 = VMOVSHDUPZ256rm            $rip, 1, $noreg, 0, $noreg
-  $ymm16 = VMOVSHDUPZ256rm                     $rip, 1, $noreg, 0, $noreg                           
+  $ymm16 = VMOVSHDUPZ256rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VMOVSHDUPZ256rr            $ymm16
-  $ymm16 = VMOVSHDUPZ256rr                     $ymm16                                        
+  $ymm16 = VMOVSHDUPZ256rr                     $ymm16
   ; CHECK: $ymm16 = VMOVSLDUPZ256rm            $rip, 1, $noreg, 0, $noreg
   $ymm16 = VMOVSLDUPZ256rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VMOVSLDUPZ256rr            $ymm16
-  $ymm16 = VMOVSLDUPZ256rr                     $ymm16                                        
+  $ymm16 = VMOVSLDUPZ256rr                     $ymm16
   ; CHECK: VMOVUPDZ256mr                       $rdi, 1, $noreg, 0, $noreg, $ymm16
-  VMOVUPDZ256mr                                $rdi, 1, $noreg, 0, $noreg, $ymm16                      
+  VMOVUPDZ256mr                                $rdi, 1, $noreg, 0, $noreg, $ymm16
   ; CHECK: $ymm16 = VMOVUPDZ256rm              $rip, 1, $noreg, 0, $noreg
   $ymm16 = VMOVUPDZ256rm                       $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VMOVUPDZ256rr              $ymm16
-  $ymm16 = VMOVUPDZ256rr                       $ymm16                                        
-  ; CHECK: VMOVUPSZ256mr                       $rdi, 1, $noreg, 0, $noreg, $ymm16  
-  VMOVUPSZ256mr                                $rdi, 1, $noreg, 0, $noreg, $ymm16                                               
+  $ymm16 = VMOVUPDZ256rr                       $ymm16
+  ; CHECK: VMOVUPSZ256mr                       $rdi, 1, $noreg, 0, $noreg, $ymm16
+  VMOVUPSZ256mr                                $rdi, 1, $noreg, 0, $noreg, $ymm16
   ; CHECK: $ymm16 = VPANDDZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPANDDZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $ymm16 = VPANDDZ256rr               $ymm16, $ymm1  
-  $ymm16 = VPANDDZ256rr                        $ymm16, $ymm1                                 
+  ; CHECK: $ymm16 = VPANDDZ256rr               $ymm16, $ymm1
+  $ymm16 = VPANDDZ256rr                        $ymm16, $ymm1
   ; CHECK: $ymm16 = VPANDQZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPANDQZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPANDQZ256rr               $ymm16, $ymm1
-  $ymm16 = VPANDQZ256rr                        $ymm16, $ymm1                                 
+  $ymm16 = VPANDQZ256rr                        $ymm16, $ymm1
   ; CHECK: $ymm16 = VPANDNDZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPANDNDZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $ymm16 = VPANDNDZ256rr               $ymm16, $ymm1  
-  $ymm16 = VPANDNDZ256rr                        $ymm16, $ymm1                                 
+  ; CHECK: $ymm16 = VPANDNDZ256rr               $ymm16, $ymm1
+  $ymm16 = VPANDNDZ256rr                        $ymm16, $ymm1
   ; CHECK: $ymm16 = VPANDNQZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPANDNQZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPANDNQZ256rr               $ymm16, $ymm1
-  $ymm16 = VPANDNQZ256rr                        $ymm16, $ymm1                                 
+  $ymm16 = VPANDNQZ256rr                        $ymm16, $ymm1
   ; CHECK: $ymm16 = VPAVGBZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPAVGBZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPAVGBZ256rr               $ymm16, $ymm1
-  $ymm16 = VPAVGBZ256rr                        $ymm16, $ymm1                                 
+  $ymm16 = VPAVGBZ256rr                        $ymm16, $ymm1
   ; CHECK: $ymm16 = VPAVGWZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPAVGWZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPAVGWZ256rr               $ymm16, $ymm1
-  $ymm16 = VPAVGWZ256rr                        $ymm16, $ymm1                                 
+  $ymm16 = VPAVGWZ256rr                        $ymm16, $ymm1
   ; CHECK: $ymm16 = VPADDBZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPADDBZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $ymm16 = VPADDBZ256rr               $ymm16, $ymm1  
-  $ymm16 = VPADDBZ256rr                        $ymm16, $ymm1                                 
+  ; CHECK: $ymm16 = VPADDBZ256rr               $ymm16, $ymm1
+  $ymm16 = VPADDBZ256rr                        $ymm16, $ymm1
   ; CHECK: $ymm16 = VPADDDZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPADDDZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPADDDZ256rr               $ymm16, $ymm1
-  $ymm16 = VPADDDZ256rr                        $ymm16, $ymm1                                 
+  $ymm16 = VPADDDZ256rr                        $ymm16, $ymm1
   ; CHECK: $ymm16 = VPADDQZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPADDQZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPADDQZ256rr               $ymm16, $ymm1
-  $ymm16 = VPADDQZ256rr                        $ymm16, $ymm1                                 
+  $ymm16 = VPADDQZ256rr                        $ymm16, $ymm1
   ; CHECK: $ymm16 = VPADDSBZ256rm              $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPADDSBZ256rm                       $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPADDSBZ256rr              $ymm16, $ymm1
-  $ymm16 = VPADDSBZ256rr                       $ymm16, $ymm1                                 
+  $ymm16 = VPADDSBZ256rr                       $ymm16, $ymm1
   ; CHECK: $ymm16 = VPADDSWZ256rm              $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPADDSWZ256rm                       $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPADDSWZ256rr              $ymm16, $ymm1
-  $ymm16 = VPADDSWZ256rr                       $ymm16, $ymm1                                 
+  $ymm16 = VPADDSWZ256rr                       $ymm16, $ymm1
   ; CHECK: $ymm16 = VPADDUSBZ256rm             $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPADDUSBZ256rm                      $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPADDUSBZ256rr             $ymm16, $ymm1
-  $ymm16 = VPADDUSBZ256rr                      $ymm16, $ymm1                                 
+  $ymm16 = VPADDUSBZ256rr                      $ymm16, $ymm1
   ; CHECK: $ymm16 = VPADDUSWZ256rm             $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPADDUSWZ256rm                      $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPADDUSWZ256rr             $ymm16, $ymm1
-  $ymm16 = VPADDUSWZ256rr                      $ymm16, $ymm1                                 
+  $ymm16 = VPADDUSWZ256rr                      $ymm16, $ymm1
   ; CHECK: $ymm16 = VPADDWZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPADDWZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPADDWZ256rr               $ymm16, $ymm1
-  $ymm16 = VPADDWZ256rr                        $ymm16, $ymm1                                 
+  $ymm16 = VPADDWZ256rr                        $ymm16, $ymm1
   ; CHECK: $ymm16 = VMULPDZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   $ymm16 = VMULPDZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $ymm16 = VMULPDZ256rr               $ymm16, $ymm1, implicit $mxcsr
@@ -2477,143 +2477,143 @@ body: |
   ; CHECK: $ymm16 = VORPDZ256rm                $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VORPDZ256rm                         $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VORPDZ256rr                $ymm16, $ymm1
-  $ymm16 = VORPDZ256rr                         $ymm16, $ymm1                                 
+  $ymm16 = VORPDZ256rr                         $ymm16, $ymm1
   ; CHECK: $ymm16 = VORPSZ256rm                $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VORPSZ256rm                         $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VORPSZ256rr                $ymm16, $ymm1
-  $ymm16 = VORPSZ256rr                         $ymm16, $ymm1                                 
+  $ymm16 = VORPSZ256rr                         $ymm16, $ymm1
   ; CHECK: $ymm16 = VPMADDUBSWZ256rm           $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMADDUBSWZ256rm                    $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMADDUBSWZ256rr           $ymm16, $ymm1
-  $ymm16 = VPMADDUBSWZ256rr                    $ymm16, $ymm1                                 
+  $ymm16 = VPMADDUBSWZ256rr                    $ymm16, $ymm1
   ; CHECK: $ymm16 = VPMADDWDZ256rm             $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMADDWDZ256rm                      $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMADDWDZ256rr             $ymm16, $ymm1
-  $ymm16 = VPMADDWDZ256rr                      $ymm16, $ymm1                                 
+  $ymm16 = VPMADDWDZ256rr                      $ymm16, $ymm1
   ; CHECK: $ymm16 = VPMAXSBZ256rm              $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMAXSBZ256rm                       $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMAXSBZ256rr              $ymm16, $ymm1
-  $ymm16 = VPMAXSBZ256rr                       $ymm16, $ymm1                                 
+  $ymm16 = VPMAXSBZ256rr                       $ymm16, $ymm1
   ; CHECK: $ymm16 = VPMAXSDZ256rm              $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMAXSDZ256rm                       $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMAXSDZ256rr              $ymm16, $ymm1
-  $ymm16 = VPMAXSDZ256rr                       $ymm16, $ymm1                                 
+  $ymm16 = VPMAXSDZ256rr                       $ymm16, $ymm1
   ; CHECK: $ymm16 = VPMAXSWZ256rm              $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMAXSWZ256rm                       $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMAXSWZ256rr              $ymm16, $ymm1
-  $ymm16 = VPMAXSWZ256rr                       $ymm16, $ymm1                                 
+  $ymm16 = VPMAXSWZ256rr                       $ymm16, $ymm1
   ; CHECK: $ymm16 = VPMAXUBZ256rm              $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMAXUBZ256rm                       $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMAXUBZ256rr              $ymm16, $ymm1
-  $ymm16 = VPMAXUBZ256rr                       $ymm16, $ymm1                                 
+  $ymm16 = VPMAXUBZ256rr                       $ymm16, $ymm1
   ; CHECK: $ymm16 = VPMAXUDZ256rm              $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMAXUDZ256rm                       $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMAXUDZ256rr              $ymm16, $ymm1
-  $ymm16 = VPMAXUDZ256rr                       $ymm16, $ymm1                                 
+  $ymm16 = VPMAXUDZ256rr                       $ymm16, $ymm1
   ; CHECK: $ymm16 = VPMAXUWZ256rm              $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMAXUWZ256rm                       $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMAXUWZ256rr              $ymm16, $ymm1
-  $ymm16 = VPMAXUWZ256rr                       $ymm16, $ymm1                                 
+  $ymm16 = VPMAXUWZ256rr                       $ymm16, $ymm1
   ; CHECK: $ymm16 = VPMINSBZ256rm              $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMINSBZ256rm                       $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMINSBZ256rr              $ymm16, $ymm1
-  $ymm16 = VPMINSBZ256rr                       $ymm16, $ymm1                                 
+  $ymm16 = VPMINSBZ256rr                       $ymm16, $ymm1
   ; CHECK: $ymm16 = VPMINSDZ256rm              $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMINSDZ256rm                       $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMINSDZ256rr              $ymm16, $ymm1
-  $ymm16 = VPMINSDZ256rr                       $ymm16, $ymm1                                 
+  $ymm16 = VPMINSDZ256rr                       $ymm16, $ymm1
   ; CHECK: $ymm16 = VPMINSWZ256rm              $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMINSWZ256rm                       $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMINSWZ256rr              $ymm16, $ymm1
-  $ymm16 = VPMINSWZ256rr                       $ymm16, $ymm1                                 
+  $ymm16 = VPMINSWZ256rr                       $ymm16, $ymm1
   ; CHECK: $ymm16 = VPMINUBZ256rm              $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMINUBZ256rm                       $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMINUBZ256rr              $ymm16, $ymm1
-  $ymm16 = VPMINUBZ256rr                       $ymm16, $ymm1                                 
+  $ymm16 = VPMINUBZ256rr                       $ymm16, $ymm1
   ; CHECK: $ymm16 = VPMINUDZ256rm              $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMINUDZ256rm                       $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMINUDZ256rr              $ymm16, $ymm1
-  $ymm16 = VPMINUDZ256rr                       $ymm16, $ymm1                                 
+  $ymm16 = VPMINUDZ256rr                       $ymm16, $ymm1
   ; CHECK: $ymm16 = VPMINUWZ256rm              $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMINUWZ256rm                       $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMINUWZ256rr              $ymm16, $ymm1
-  $ymm16 = VPMINUWZ256rr                       $ymm16, $ymm1                                 
+  $ymm16 = VPMINUWZ256rr                       $ymm16, $ymm1
   ; CHECK: $ymm16 = VPMULDQZ256rm              $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMULDQZ256rm                       $ymm16, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $ymm16 = VPMULDQZ256rr              $ymm16, $ymm1  
-  $ymm16 = VPMULDQZ256rr                       $ymm16, $ymm1                                 
+  ; CHECK: $ymm16 = VPMULDQZ256rr              $ymm16, $ymm1
+  $ymm16 = VPMULDQZ256rr                       $ymm16, $ymm1
   ; CHECK: $ymm16 = VPMULHRSWZ256rm            $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMULHRSWZ256rm                     $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMULHRSWZ256rr            $ymm16, $ymm1
-  $ymm16 = VPMULHRSWZ256rr                     $ymm16, $ymm1                                 
+  $ymm16 = VPMULHRSWZ256rr                     $ymm16, $ymm1
   ; CHECK: $ymm16 = VPMULHUWZ256rm             $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMULHUWZ256rm                      $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMULHUWZ256rr             $ymm16, $ymm1
-  $ymm16 = VPMULHUWZ256rr                      $ymm16, $ymm1                                 
+  $ymm16 = VPMULHUWZ256rr                      $ymm16, $ymm1
   ; CHECK: $ymm16 = VPMULHWZ256rm              $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMULHWZ256rm                       $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMULHWZ256rr              $ymm16, $ymm1
-  $ymm16 = VPMULHWZ256rr                       $ymm16, $ymm1                                 
+  $ymm16 = VPMULHWZ256rr                       $ymm16, $ymm1
   ; CHECK: $ymm16 = VPMULLDZ256rm              $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMULLDZ256rm                       $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMULLDZ256rr              $ymm16, $ymm1
-  $ymm16 = VPMULLDZ256rr                       $ymm16, $ymm1                                 
+  $ymm16 = VPMULLDZ256rr                       $ymm16, $ymm1
   ; CHECK: $ymm16 = VPMULLWZ256rm              $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMULLWZ256rm                       $ymm16, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $ymm16 = VPMULLWZ256rr              $ymm16, $ymm1  
-  $ymm16 = VPMULLWZ256rr                       $ymm16, $ymm1                                 
+  ; CHECK: $ymm16 = VPMULLWZ256rr              $ymm16, $ymm1
+  $ymm16 = VPMULLWZ256rr                       $ymm16, $ymm1
   ; CHECK: $ymm16 = VPMULUDQZ256rm             $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMULUDQZ256rm                      $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMULUDQZ256rr             $ymm16, $ymm1
-  $ymm16 = VPMULUDQZ256rr                      $ymm16, $ymm1                                 
+  $ymm16 = VPMULUDQZ256rr                      $ymm16, $ymm1
   ; CHECK: $ymm16 = VPORDZ256rm                $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPORDZ256rm                         $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPORDZ256rr                $ymm16, $ymm1
-  $ymm16 = VPORDZ256rr                         $ymm16, $ymm1                                 
+  $ymm16 = VPORDZ256rr                         $ymm16, $ymm1
   ; CHECK: $ymm16 = VPORQZ256rm                $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPORQZ256rm                         $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPORQZ256rr                $ymm16, $ymm1
-  $ymm16 = VPORQZ256rr                         $ymm16, $ymm1                                 
+  $ymm16 = VPORQZ256rr                         $ymm16, $ymm1
   ; CHECK: $ymm16 = VPSUBBZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPSUBBZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPSUBBZ256rr               $ymm16, $ymm1
-  $ymm16 = VPSUBBZ256rr                        $ymm16, $ymm1                                 
+  $ymm16 = VPSUBBZ256rr                        $ymm16, $ymm1
   ; CHECK: $ymm16 = VPSUBDZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPSUBDZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPSUBDZ256rr               $ymm16, $ymm1
-  $ymm16 = VPSUBDZ256rr                        $ymm16, $ymm1                                 
+  $ymm16 = VPSUBDZ256rr                        $ymm16, $ymm1
   ; CHECK: $ymm16 = VPSUBQZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPSUBQZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPSUBQZ256rr               $ymm16, $ymm1
-  $ymm16 = VPSUBQZ256rr                        $ymm16, $ymm1                                 
+  $ymm16 = VPSUBQZ256rr                        $ymm16, $ymm1
   ; CHECK: $ymm16 = VPSUBSBZ256rm              $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPSUBSBZ256rm                       $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPSUBSBZ256rr              $ymm16, $ymm1
-  $ymm16 = VPSUBSBZ256rr                       $ymm16, $ymm1                                 
+  $ymm16 = VPSUBSBZ256rr                       $ymm16, $ymm1
   ; CHECK: $ymm16 = VPSUBSWZ256rm              $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPSUBSWZ256rm                       $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPSUBSWZ256rr              $ymm16, $ymm1
-  $ymm16 = VPSUBSWZ256rr                       $ymm16, $ymm1                                 
+  $ymm16 = VPSUBSWZ256rr                       $ymm16, $ymm1
   ; CHECK: $ymm16 = VPSUBUSBZ256rm             $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPSUBUSBZ256rm                      $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPSUBUSBZ256rr             $ymm16, $ymm1
-  $ymm16 = VPSUBUSBZ256rr                      $ymm16, $ymm1                                 
+  $ymm16 = VPSUBUSBZ256rr                      $ymm16, $ymm1
   ; CHECK: $ymm16 = VPSUBUSWZ256rm             $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPSUBUSWZ256rm                      $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPSUBUSWZ256rr             $ymm16, $ymm1
-  $ymm16 = VPSUBUSWZ256rr                      $ymm16, $ymm1                                 
+  $ymm16 = VPSUBUSWZ256rr                      $ymm16, $ymm1
   ; CHECK: $ymm16 = VPSUBWZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPSUBWZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPSUBWZ256rr               $ymm16, $ymm1
-  $ymm16 = VPSUBWZ256rr                        $ymm16, $ymm1                                 
+  $ymm16 = VPSUBWZ256rr                        $ymm16, $ymm1
   ; CHECK: $ymm16 = VPXORDZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPXORDZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPXORDZ256rr               $ymm16, $ymm1
-  $ymm16 = VPXORDZ256rr                        $ymm16, $ymm1                                 
+  $ymm16 = VPXORDZ256rr                        $ymm16, $ymm1
   ; CHECK: $ymm16 = VPXORQZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPXORQZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $ymm16 = VPXORQZ256rr               $ymm16, $ymm1  
-  $ymm16 = VPXORQZ256rr                        $ymm16, $ymm1                                 
+  ; CHECK: $ymm16 = VPXORQZ256rr               $ymm16, $ymm1
+  $ymm16 = VPXORQZ256rr                        $ymm16, $ymm1
   ; CHECK: $ymm16 = VADDPDZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   $ymm16 = VADDPDZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $ymm16 = VADDPDZ256rr               $ymm16, $ymm1, implicit $mxcsr
@@ -2625,19 +2625,19 @@ body: |
   ; CHECK: $ymm16 = VANDNPDZ256rm              $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VANDNPDZ256rm                       $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VANDNPDZ256rr              $ymm16, $ymm1
-  $ymm16 = VANDNPDZ256rr                       $ymm16, $ymm1                                 
+  $ymm16 = VANDNPDZ256rr                       $ymm16, $ymm1
   ; CHECK: $ymm16 = VANDNPSZ256rm              $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VANDNPSZ256rm                       $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VANDNPSZ256rr              $ymm16, $ymm1
-  $ymm16 = VANDNPSZ256rr                       $ymm16, $ymm1                                 
+  $ymm16 = VANDNPSZ256rr                       $ymm16, $ymm1
   ; CHECK: $ymm16 = VANDPDZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VANDPDZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VANDPDZ256rr               $ymm16, $ymm1
-  $ymm16 = VANDPDZ256rr                        $ymm16, $ymm1                                 
+  $ymm16 = VANDPDZ256rr                        $ymm16, $ymm1
   ; CHECK: $ymm16 = VANDPSZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VANDPSZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VANDPSZ256rr               $ymm16, $ymm1
-  $ymm16 = VANDPSZ256rr                        $ymm16, $ymm1                                 
+  $ymm16 = VANDPSZ256rr                        $ymm16, $ymm1
   ; CHECK: $ymm16 = VDIVPDZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   $ymm16 = VDIVPDZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $ymm16 = VDIVPDZ256rr               $ymm16, $ymm1, implicit $mxcsr
@@ -2681,43 +2681,43 @@ body: |
   ; CHECK: $ymm16 = VXORPDZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VXORPDZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VXORPDZ256rr               $ymm16, $ymm1
-  $ymm16 = VXORPDZ256rr                        $ymm16, $ymm1                                 
+  $ymm16 = VXORPDZ256rr                        $ymm16, $ymm1
   ; CHECK: $ymm16 = VXORPSZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VXORPSZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VXORPSZ256rr               $ymm16, $ymm1
-  $ymm16 = VXORPSZ256rr                        $ymm16, $ymm1                                 
+  $ymm16 = VXORPSZ256rr                        $ymm16, $ymm1
   ; CHECK: $ymm16 = VPACKSSDWZ256rm            $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPACKSSDWZ256rm                     $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPACKSSDWZ256rr            $ymm16, $ymm1
-  $ymm16 = VPACKSSDWZ256rr                     $ymm16, $ymm1                                 
+  $ymm16 = VPACKSSDWZ256rr                     $ymm16, $ymm1
   ; CHECK: $ymm16 = VPACKSSWBZ256rm            $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPACKSSWBZ256rm                     $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPACKSSWBZ256rr            $ymm16, $ymm1
-  $ymm16 = VPACKSSWBZ256rr                     $ymm16, $ymm1                                 
+  $ymm16 = VPACKSSWBZ256rr                     $ymm16, $ymm1
   ; CHECK: $ymm16 = VPACKUSDWZ256rm            $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPACKUSDWZ256rm                     $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPACKUSDWZ256rr            $ymm16, $ymm1
-  $ymm16 = VPACKUSDWZ256rr                     $ymm16, $ymm1                                 
+  $ymm16 = VPACKUSDWZ256rr                     $ymm16, $ymm1
   ; CHECK: $ymm16 = VPACKUSWBZ256rm            $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPACKUSWBZ256rm                     $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPACKUSWBZ256rr            $ymm16, $ymm1
-  $ymm16 = VPACKUSWBZ256rr                     $ymm16, $ymm1                                 
+  $ymm16 = VPACKUSWBZ256rr                     $ymm16, $ymm1
   ; CHECK: $ymm16 = VUNPCKHPDZ256rm            $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VUNPCKHPDZ256rm                     $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VUNPCKHPDZ256rr            $ymm16, $ymm1
-  $ymm16 = VUNPCKHPDZ256rr                     $ymm16, $ymm1                                 
+  $ymm16 = VUNPCKHPDZ256rr                     $ymm16, $ymm1
   ; CHECK: $ymm16 = VUNPCKHPSZ256rm            $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VUNPCKHPSZ256rm                     $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VUNPCKHPSZ256rr            $ymm16, $ymm1
-  $ymm16 = VUNPCKHPSZ256rr                     $ymm16, $ymm1                                 
+  $ymm16 = VUNPCKHPSZ256rr                     $ymm16, $ymm1
   ; CHECK: $ymm16 = VUNPCKLPDZ256rm            $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VUNPCKLPDZ256rm                     $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VUNPCKLPDZ256rr            $ymm16, $ymm1
-  $ymm16 = VUNPCKLPDZ256rr                     $ymm16, $ymm1                                 
+  $ymm16 = VUNPCKLPDZ256rr                     $ymm16, $ymm1
   ; CHECK: $ymm16 = VUNPCKLPSZ256rm            $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VUNPCKLPSZ256rm                     $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VUNPCKLPSZ256rr            $ymm16, $ymm1
-  $ymm16 = VUNPCKLPSZ256rr                     $ymm16, $ymm1                                 
+  $ymm16 = VUNPCKLPSZ256rr                     $ymm16, $ymm1
   ; CHECK: $ymm16 = VSUBPDZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   $ymm16 = VSUBPDZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $ymm16 = VSUBPDZ256rr               $ymm16, $ymm1, implicit $mxcsr
@@ -2729,35 +2729,35 @@ body: |
   ; CHECK: $ymm16 = VPUNPCKHBWZ256rm           $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPUNPCKHBWZ256rm                    $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPUNPCKHBWZ256rr           $ymm16, $ymm1
-  $ymm16 = VPUNPCKHBWZ256rr                    $ymm16, $ymm1                                 
+  $ymm16 = VPUNPCKHBWZ256rr                    $ymm16, $ymm1
   ; CHECK: $ymm16 = VPUNPCKHDQZ256rm           $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPUNPCKHDQZ256rm                    $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPUNPCKHDQZ256rr           $ymm16, $ymm1
-  $ymm16 = VPUNPCKHDQZ256rr                    $ymm16, $ymm1                                 
+  $ymm16 = VPUNPCKHDQZ256rr                    $ymm16, $ymm1
   ; CHECK: $ymm16 = VPUNPCKHQDQZ256rm          $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPUNPCKHQDQZ256rm                   $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPUNPCKHQDQZ256rr          $ymm16, $ymm1
-  $ymm16 = VPUNPCKHQDQZ256rr                   $ymm16, $ymm1                                 
+  $ymm16 = VPUNPCKHQDQZ256rr                   $ymm16, $ymm1
   ; CHECK: $ymm16 = VPUNPCKHWDZ256rm           $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPUNPCKHWDZ256rm                    $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPUNPCKHWDZ256rr           $ymm16, $ymm1
-  $ymm16 = VPUNPCKHWDZ256rr                    $ymm16, $ymm1                                 
+  $ymm16 = VPUNPCKHWDZ256rr                    $ymm16, $ymm1
   ; CHECK: $ymm16 = VPUNPCKLBWZ256rm           $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPUNPCKLBWZ256rm                    $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPUNPCKLBWZ256rr           $ymm16, $ymm1
-  $ymm16 = VPUNPCKLBWZ256rr                    $ymm16, $ymm1                                 
+  $ymm16 = VPUNPCKLBWZ256rr                    $ymm16, $ymm1
   ; CHECK: $ymm16 = VPUNPCKLDQZ256rm           $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPUNPCKLDQZ256rm                    $ymm16, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $ymm16 = VPUNPCKLDQZ256rr           $ymm16, $ymm1 
-  $ymm16 = VPUNPCKLDQZ256rr                    $ymm16, $ymm1                                 
+  ; CHECK: $ymm16 = VPUNPCKLDQZ256rr           $ymm16, $ymm1
+  $ymm16 = VPUNPCKLDQZ256rr                    $ymm16, $ymm1
   ; CHECK: $ymm16 = VPUNPCKLQDQZ256rm          $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPUNPCKLQDQZ256rm                   $ymm16, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $ymm16 = VPUNPCKLQDQZ256rr          $ymm16, $ymm1 
-  $ymm16 = VPUNPCKLQDQZ256rr                   $ymm16, $ymm1                                 
+  ; CHECK: $ymm16 = VPUNPCKLQDQZ256rr          $ymm16, $ymm1
+  $ymm16 = VPUNPCKLQDQZ256rr                   $ymm16, $ymm1
   ; CHECK: $ymm16 = VPUNPCKLWDZ256rm           $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPUNPCKLWDZ256rm                    $ymm16, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $ymm16 = VPUNPCKLWDZ256rr           $ymm16, $ymm1   
-  $ymm16 = VPUNPCKLWDZ256rr                    $ymm16, $ymm1                                                
+  ; CHECK: $ymm16 = VPUNPCKLWDZ256rr           $ymm16, $ymm1
+  $ymm16 = VPUNPCKLWDZ256rr                    $ymm16, $ymm1
   ; CHECK: $ymm16 = VFMADD132PDZ256m           $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
   $ymm16 = VFMADD132PDZ256m                    $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $ymm16 = VFMADD132PDZ256r           $ymm16, $ymm1, $ymm2, implicit $mxcsr
@@ -2903,97 +2903,97 @@ body: |
   ; CHECK: $ymm16 = VFNMSUB231PSZ256r          $ymm16, $ymm1, $ymm2, implicit $mxcsr
   $ymm16 = VFNMSUB231PSZ256r                   $ymm16, $ymm1, $ymm2, implicit $mxcsr
   ; CHECK: $ymm16 = VPSRADZ256ri               $ymm16, 7
-  $ymm16 = VPSRADZ256ri                        $ymm16, 7                                     
+  $ymm16 = VPSRADZ256ri                        $ymm16, 7
   ; CHECK: $ymm16 = VPSRADZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPSRADZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPSRADZ256rr               $ymm16, $xmm1
-  $ymm16 = VPSRADZ256rr                        $ymm16, $xmm1                                 
+  $ymm16 = VPSRADZ256rr                        $ymm16, $xmm1
   ; CHECK: $ymm16 = VPSRAVDZ256rm              $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPSRAVDZ256rm                       $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPSRAVDZ256rr              $ymm16, $ymm1
-  $ymm16 = VPSRAVDZ256rr                       $ymm16, $ymm1                                 
+  $ymm16 = VPSRAVDZ256rr                       $ymm16, $ymm1
   ; CHECK: $ymm16 = VPSRAWZ256ri               $ymm16, 7
-  $ymm16 = VPSRAWZ256ri                        $ymm16, 7                                     
+  $ymm16 = VPSRAWZ256ri                        $ymm16, 7
   ; CHECK: $ymm16 = VPSRAWZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPSRAWZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPSRAWZ256rr               $ymm16, $xmm1
-  $ymm16 = VPSRAWZ256rr                        $ymm16, $xmm1                                 
+  $ymm16 = VPSRAWZ256rr                        $ymm16, $xmm1
   ; CHECK: $ymm16 = VPSRLDQZ256ri              $ymm16, 7
   $ymm16 = VPSRLDQZ256ri                       $ymm16, 7
   ; CHECK: $ymm16 = VPSRLDZ256ri               $ymm16, 7
-  $ymm16 = VPSRLDZ256ri                        $ymm16, 7                                     
+  $ymm16 = VPSRLDZ256ri                        $ymm16, 7
   ; CHECK: $ymm16 = VPSRLDZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPSRLDZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPSRLDZ256rr               $ymm16, $xmm1
-  $ymm16 = VPSRLDZ256rr                        $ymm16, $xmm1                                 
+  $ymm16 = VPSRLDZ256rr                        $ymm16, $xmm1
   ; CHECK: $ymm16 = VPSRLQZ256ri               $ymm16, 7
-  $ymm16 = VPSRLQZ256ri                        $ymm16, 7                                     
+  $ymm16 = VPSRLQZ256ri                        $ymm16, 7
   ; CHECK: $ymm16 = VPSRLQZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPSRLQZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPSRLQZ256rr               $ymm16, $xmm1
-  $ymm16 = VPSRLQZ256rr                        $ymm16, $xmm1                                 
+  $ymm16 = VPSRLQZ256rr                        $ymm16, $xmm1
   ; CHECK: $ymm16 = VPSRLVDZ256rm              $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPSRLVDZ256rm                       $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPSRLVDZ256rr              $ymm16, $ymm1
-  $ymm16 = VPSRLVDZ256rr                       $ymm16, $ymm1                                 
+  $ymm16 = VPSRLVDZ256rr                       $ymm16, $ymm1
   ; CHECK: $ymm16 = VPSRLVQZ256rm              $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPSRLVQZ256rm                       $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPSRLVQZ256rr              $ymm16, $ymm1
-  $ymm16 = VPSRLVQZ256rr                       $ymm16, $ymm1                                 
+  $ymm16 = VPSRLVQZ256rr                       $ymm16, $ymm1
   ; CHECK: $ymm16 = VPSRLWZ256ri               $ymm16, 7
-  $ymm16 = VPSRLWZ256ri                        $ymm16, 7                                     
+  $ymm16 = VPSRLWZ256ri                        $ymm16, 7
   ; CHECK: $ymm16 = VPSRLWZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPSRLWZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $ymm16 = VPSRLWZ256rr               $ymm16, $xmm1  
-  $ymm16 = VPSRLWZ256rr                        $ymm16, $xmm1                                               
+  ; CHECK: $ymm16 = VPSRLWZ256rr               $ymm16, $xmm1
+  $ymm16 = VPSRLWZ256rr                        $ymm16, $xmm1
   ; CHECK: $ymm16 = VPMOVSXBDZ256rm            $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMOVSXBDZ256rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMOVSXBDZ256rr            $xmm0
-  $ymm16 = VPMOVSXBDZ256rr                     $xmm0                                         
+  $ymm16 = VPMOVSXBDZ256rr                     $xmm0
   ; CHECK: $ymm16 = VPMOVSXBQZ256rm            $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMOVSXBQZ256rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMOVSXBQZ256rr            $xmm0
-  $ymm16 = VPMOVSXBQZ256rr                     $xmm0                                         
+  $ymm16 = VPMOVSXBQZ256rr                     $xmm0
   ; CHECK: $ymm16 = VPMOVSXBWZ256rm            $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMOVSXBWZ256rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMOVSXBWZ256rr            $xmm0
-  $ymm16 = VPMOVSXBWZ256rr                     $xmm0                                         
+  $ymm16 = VPMOVSXBWZ256rr                     $xmm0
   ; CHECK: $ymm16 = VPMOVSXDQZ256rm            $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMOVSXDQZ256rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMOVSXDQZ256rr            $xmm0
-  $ymm16 = VPMOVSXDQZ256rr                     $xmm0                                         
+  $ymm16 = VPMOVSXDQZ256rr                     $xmm0
   ; CHECK: $ymm16 = VPMOVSXWDZ256rm            $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMOVSXWDZ256rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMOVSXWDZ256rr            $xmm0
-  $ymm16 = VPMOVSXWDZ256rr                     $xmm0                                         
+  $ymm16 = VPMOVSXWDZ256rr                     $xmm0
   ; CHECK: $ymm16 = VPMOVSXWQZ256rm            $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMOVSXWQZ256rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMOVSXWQZ256rr            $xmm0
-  $ymm16 = VPMOVSXWQZ256rr                     $xmm0                                         
+  $ymm16 = VPMOVSXWQZ256rr                     $xmm0
   ; CHECK: $ymm16 = VPMOVZXBDZ256rm            $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMOVZXBDZ256rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMOVZXBDZ256rr            $xmm0
-  $ymm16 = VPMOVZXBDZ256rr                     $xmm0                                         
+  $ymm16 = VPMOVZXBDZ256rr                     $xmm0
   ; CHECK: $ymm16 = VPMOVZXBQZ256rm            $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMOVZXBQZ256rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMOVZXBQZ256rr            $xmm0
-  $ymm16 = VPMOVZXBQZ256rr                     $xmm0                                         
+  $ymm16 = VPMOVZXBQZ256rr                     $xmm0
   ; CHECK: $ymm16 = VPMOVZXBWZ256rm            $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMOVZXBWZ256rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMOVZXBWZ256rr            $xmm0
-  $ymm16 = VPMOVZXBWZ256rr                     $xmm0                                         
+  $ymm16 = VPMOVZXBWZ256rr                     $xmm0
   ; CHECK: $ymm16 = VPMOVZXDQZ256rm            $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMOVZXDQZ256rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMOVZXDQZ256rr            $xmm0
-  $ymm16 = VPMOVZXDQZ256rr                     $xmm0                                         
+  $ymm16 = VPMOVZXDQZ256rr                     $xmm0
   ; CHECK: $ymm16 = VPMOVZXWDZ256rm            $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMOVZXWDZ256rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPMOVZXWDZ256rr            $xmm0
-  $ymm16 = VPMOVZXWDZ256rr                     $xmm0                                         
+  $ymm16 = VPMOVZXWDZ256rr                     $xmm0
   ; CHECK: $ymm16 = VPMOVZXWQZ256rm            $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPMOVZXWQZ256rm                     $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $ymm16 = VPMOVZXWQZ256rr            $xmm0    
-  $ymm16 = VPMOVZXWQZ256rr                     $xmm0                                                 
+  ; CHECK: $ymm16 = VPMOVZXWQZ256rr            $xmm0
+  $ymm16 = VPMOVZXWQZ256rr                     $xmm0
   ; CHECK: $ymm16 = VBROADCASTF32X2Z256rm      $rip, 1, $noreg, 0, $noreg
   $ymm16 = VBROADCASTF32X2Z256rm               $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VBROADCASTF32X2Z256rr      $xmm16
@@ -3003,23 +3003,23 @@ body: |
   ; CHECK: $ymm16 = VBROADCASTSDZ256rm         $rip, 1, $noreg, 0, $noreg
   $ymm16 = VBROADCASTSDZ256rm                  $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VBROADCASTSDZ256rr         $xmm0
-  $ymm16 = VBROADCASTSDZ256rr                  $xmm0                                         
+  $ymm16 = VBROADCASTSDZ256rr                  $xmm0
   ; CHECK: $ymm16 = VBROADCASTSSZ256rm         $rip, 1, $noreg, 0, $noreg
   $ymm16 = VBROADCASTSSZ256rm                  $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VBROADCASTSSZ256rr         $xmm0
-  $ymm16 = VBROADCASTSSZ256rr                  $xmm0                                         
+  $ymm16 = VBROADCASTSSZ256rr                  $xmm0
   ; CHECK: $ymm16 = VPBROADCASTBZ256rm         $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPBROADCASTBZ256rm                  $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPBROADCASTBZ256rr         $xmm0
-  $ymm16 = VPBROADCASTBZ256rr                  $xmm0                                         
+  $ymm16 = VPBROADCASTBZ256rr                  $xmm0
   ; CHECK: $ymm16 = VPBROADCASTDZ256rm         $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPBROADCASTDZ256rm                  $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPBROADCASTDZ256rr         $xmm0
-  $ymm16 = VPBROADCASTDZ256rr                  $xmm0                                         
+  $ymm16 = VPBROADCASTDZ256rr                  $xmm0
   ; CHECK: $ymm16 = VPBROADCASTWZ256rm         $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPBROADCASTWZ256rm                  $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPBROADCASTWZ256rr         $xmm0
-  $ymm16 = VPBROADCASTWZ256rr                  $xmm0                                         
+  $ymm16 = VPBROADCASTWZ256rr                  $xmm0
   ; CHECK: $ymm16 = VBROADCASTI32X4Z256rm      $rip, 1, $noreg, 0, $noreg
   $ymm16 = VBROADCASTI32X4Z256rm               $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VBROADCASTI32X2Z256rm      $rip, 1, $noreg, 0, $noreg
@@ -3028,66 +3028,66 @@ body: |
   $ymm16 = VBROADCASTI32X2Z256rr               $xmm16
   ; CHECK: $ymm16 = VPBROADCASTQZ256rm         $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPBROADCASTQZ256rm                  $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $ymm16 = VPBROADCASTQZ256rr         $xmm0  
-  $ymm16 = VPBROADCASTQZ256rr                  $xmm0                                               
+  ; CHECK: $ymm16 = VPBROADCASTQZ256rr         $xmm0
+  $ymm16 = VPBROADCASTQZ256rr                  $xmm0
   ; CHECK: $ymm16 = VPABSBZ256rm               $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPABSBZ256rm                        $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPABSBZ256rr               $ymm16
-  $ymm16 = VPABSBZ256rr                        $ymm16                                        
+  $ymm16 = VPABSBZ256rr                        $ymm16
   ; CHECK: $ymm16 = VPABSDZ256rm               $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPABSDZ256rm                        $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPABSDZ256rr               $ymm16
-  $ymm16 = VPABSDZ256rr                        $ymm16                                        
+  $ymm16 = VPABSDZ256rr                        $ymm16
   ; CHECK: $ymm16 = VPABSWZ256rm               $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPABSWZ256rm                        $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $ymm16 = VPABSWZ256rr               $ymm16  
-  $ymm16 = VPABSWZ256rr                        $ymm16                                               
+  ; CHECK: $ymm16 = VPABSWZ256rr               $ymm16
+  $ymm16 = VPABSWZ256rr                        $ymm16
   ; CHECK: $ymm16 = VPSADBWZ256rm              $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPSADBWZ256rm                       $ymm16, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $ymm16 = VPSADBWZ256rr              $ymm16, $ymm1  
-  $ymm16 = VPSADBWZ256rr                       $ymm16, $ymm1                                               
+  ; CHECK: $ymm16 = VPSADBWZ256rr              $ymm16, $ymm1
+  $ymm16 = VPSADBWZ256rr                       $ymm16, $ymm1
   ; CHECK: $ymm16 = VPERMDZ256rm               $ymm16, $rdi, 1, $noreg, 0, $noreg
-  $ymm16 = VPERMDZ256rm                        $ymm16, $rdi, 1, $noreg, 0, $noreg                      
+  $ymm16 = VPERMDZ256rm                        $ymm16, $rdi, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPERMDZ256rr               $ymm1, $ymm16
-  $ymm16 = VPERMDZ256rr                        $ymm1, $ymm16                                 
+  $ymm16 = VPERMDZ256rr                        $ymm1, $ymm16
   ; CHECK: $ymm16 = VPERMILPDZ256mi            $rdi, 1, $noreg, 0, $noreg, 7
   $ymm16 = VPERMILPDZ256mi                     $rdi, 1, $noreg, 0, $noreg, 7
   ; CHECK: $ymm16 = VPERMILPDZ256ri            $ymm16, 7
-  $ymm16 = VPERMILPDZ256ri                     $ymm16, 7                                     
+  $ymm16 = VPERMILPDZ256ri                     $ymm16, 7
   ; CHECK: $ymm16 = VPERMILPDZ256rm            $ymm16, $rdi, 1, $noreg, 0, $noreg
-  $ymm16 = VPERMILPDZ256rm                     $ymm16, $rdi, 1, $noreg, 0, $noreg                      
+  $ymm16 = VPERMILPDZ256rm                     $ymm16, $rdi, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPERMILPDZ256rr            $ymm1, $ymm16
-  $ymm16 = VPERMILPDZ256rr                     $ymm1, $ymm16                                 
+  $ymm16 = VPERMILPDZ256rr                     $ymm1, $ymm16
   ; CHECK: $ymm16 = VPERMILPSZ256mi            $rdi, 1, $noreg, 0, $noreg, 7
   $ymm16 = VPERMILPSZ256mi                     $rdi, 1, $noreg, 0, $noreg, 7
   ; CHECK: $ymm16 = VPERMILPSZ256ri            $ymm16, 7
-  $ymm16 = VPERMILPSZ256ri                     $ymm16, 7                                     
+  $ymm16 = VPERMILPSZ256ri                     $ymm16, 7
   ; CHECK: $ymm16 = VPERMILPSZ256rm            $ymm16, $rdi, 1, $noreg, 0, $noreg
-  $ymm16 = VPERMILPSZ256rm                     $ymm16, $rdi, 1, $noreg, 0, $noreg                      
+  $ymm16 = VPERMILPSZ256rm                     $ymm16, $rdi, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPERMILPSZ256rr            $ymm1, $ymm16
-  $ymm16 = VPERMILPSZ256rr                     $ymm1, $ymm16                                 
+  $ymm16 = VPERMILPSZ256rr                     $ymm1, $ymm16
   ; CHECK: $ymm16 = VPERMPDZ256mi              $rdi, 1, $noreg, 0, $noreg, 7
   $ymm16 = VPERMPDZ256mi                       $rdi, 1, $noreg, 0, $noreg, 7
   ; CHECK: $ymm16 = VPERMPDZ256ri              $ymm16, 7
-  $ymm16 = VPERMPDZ256ri                       $ymm16, 7                                     
+  $ymm16 = VPERMPDZ256ri                       $ymm16, 7
   ; CHECK: $ymm16 = VPERMPSZ256rm              $ymm16, $rdi, 1, $noreg, 0, $noreg
-  $ymm16 = VPERMPSZ256rm                       $ymm16, $rdi, 1, $noreg, 0, $noreg                      
+  $ymm16 = VPERMPSZ256rm                       $ymm16, $rdi, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPERMPSZ256rr              $ymm1, $ymm16
-  $ymm16 = VPERMPSZ256rr                       $ymm1, $ymm16                                 
+  $ymm16 = VPERMPSZ256rr                       $ymm1, $ymm16
   ; CHECK: $ymm16 = VPERMQZ256mi               $rdi, 1, $noreg, 0, $noreg, 7
   $ymm16 = VPERMQZ256mi                        $rdi, 1, $noreg, 0, $noreg, 7
   ; CHECK: $ymm16 = VPERMQZ256ri               $ymm16, 7
-  $ymm16 = VPERMQZ256ri                        $ymm16, 7                                               
+  $ymm16 = VPERMQZ256ri                        $ymm16, 7
   ; CHECK: $ymm16 = VPSLLDQZ256ri              $ymm16, 14
   $ymm16 = VPSLLDQZ256ri                       $ymm16, 14
   ; CHECK: $ymm16 = VPSLLDZ256ri               $ymm16, 7
-  $ymm16 = VPSLLDZ256ri                        $ymm16, 7                                     
+  $ymm16 = VPSLLDZ256ri                        $ymm16, 7
   ; CHECK: $ymm16 = VPSLLDZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPSLLDZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPSLLDZ256rr               $ymm16, $xmm16
   $ymm16 = VPSLLDZ256rr                        $ymm16, $xmm16
   ; CHECK: $ymm16 = VPSLLQZ256ri               $ymm16, 7
-  $ymm16 = VPSLLQZ256ri                        $ymm16, 7                                     
+  $ymm16 = VPSLLQZ256ri                        $ymm16, 7
   ; CHECK: $ymm16 = VPSLLQZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPSLLQZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPSLLQZ256rr               $ymm16, $xmm16
@@ -3101,7 +3101,7 @@ body: |
   ; CHECK: $ymm16 = VPSLLVQZ256rr              $ymm16, $ymm16
   $ymm16 = VPSLLVQZ256rr                       $ymm16, $ymm16
   ; CHECK: $ymm16 = VPSLLWZ256ri               $ymm16, 7
-  $ymm16 = VPSLLWZ256ri                        $ymm16, 7                                     
+  $ymm16 = VPSLLWZ256ri                        $ymm16, 7
   ; CHECK: $ymm16 = VPSLLWZ256rm               $ymm16, $rip, 1, $noreg, 0, $noreg
   $ymm16 = VPSLLWZ256rm                        $ymm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPSLLWZ256rr               $ymm16, $xmm16
@@ -3158,26 +3158,26 @@ body: |
   $ymm16 = VPALIGNRZ256rmi                     $ymm16, $rdi, 1, $noreg, 0, $noreg, 1
   ; CHECK: $ymm16 = VPALIGNRZ256rri            $ymm16, $ymm1, 1
   $ymm16 = VPALIGNRZ256rri                     $ymm16, $ymm1, 1
-  ; CHECK: $ymm16 = VMOVUPSZ256rm              $rdi, 1, $noreg, 0, $noreg       
-  $ymm16 = VMOVUPSZ256rm                       $rdi, 1, $noreg, 0, $noreg                              
+  ; CHECK: $ymm16 = VMOVUPSZ256rm              $rdi, 1, $noreg, 0, $noreg
+  $ymm16 = VMOVUPSZ256rm                       $rdi, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VMOVUPSZ256rr              $ymm16
-  $ymm16 = VMOVUPSZ256rr                       $ymm16                                        
+  $ymm16 = VMOVUPSZ256rr                       $ymm16
   ; CHECK: $ymm16 = VPSHUFBZ256rm              $ymm16, $rdi, 1, $noreg, 0, $noreg
   $ymm16 = VPSHUFBZ256rm                       $ymm16, $rdi, 1, $noreg, 0, $noreg
   ; CHECK: $ymm16 = VPSHUFBZ256rr              $ymm16, $ymm1
-  $ymm16 = VPSHUFBZ256rr                       $ymm16, $ymm1                                 
+  $ymm16 = VPSHUFBZ256rr                       $ymm16, $ymm1
   ; CHECK: $ymm16 = VPSHUFDZ256mi              $rdi, 1, $noreg, 0, $noreg, -24
   $ymm16 = VPSHUFDZ256mi                       $rdi, 1, $noreg, 0, $noreg, -24
   ; CHECK: $ymm16 = VPSHUFDZ256ri              $ymm16, -24
-  $ymm16 = VPSHUFDZ256ri                       $ymm16, -24                                   
+  $ymm16 = VPSHUFDZ256ri                       $ymm16, -24
   ; CHECK: $ymm16 = VPSHUFHWZ256mi             $rdi, 1, $noreg, 0, $noreg, -24
   $ymm16 = VPSHUFHWZ256mi                      $rdi, 1, $noreg, 0, $noreg, -24
   ; CHECK: $ymm16 = VPSHUFHWZ256ri             $ymm16, -24
-  $ymm16 = VPSHUFHWZ256ri                      $ymm16, -24                                   
+  $ymm16 = VPSHUFHWZ256ri                      $ymm16, -24
   ; CHECK: $ymm16 = VPSHUFLWZ256mi             $rdi, 1, $noreg, 0, $noreg, -24
   $ymm16 = VPSHUFLWZ256mi                      $rdi, 1, $noreg, 0, $noreg, -24
   ; CHECK: $ymm16 = VPSHUFLWZ256ri             $ymm16, -24
-  $ymm16 = VPSHUFLWZ256ri                      $ymm16, -24                                   
+  $ymm16 = VPSHUFLWZ256ri                      $ymm16, -24
   ; CHECK: $ymm16 = VSHUFPDZ256rmi             $ymm16, $rip, 1, $noreg, 0, $noreg, -24
   $ymm16 = VSHUFPDZ256rmi                      $ymm16, $rip, 1, $noreg, 0, $noreg, -24
   ; CHECK: $ymm16 = VSHUFPDZ256rri             $ymm16, $ymm1, -24
@@ -3220,8 +3220,8 @@ body: |
   $ymm16 = VSHUFI64X2Z256rri                   $ymm16, $ymm1, 228
 
   RET64
-...                                            
----                                            
+...
+---
   # CHECK-LABEL: name: evex_z128_to_evex_test
   # CHECK: bb.0:
 
@@ -3229,137 +3229,137 @@ name: evex_z128_to_evex_test
 body: |
   bb.0:
   ; CHECK: VMOVAPDZ128mr                       $rdi, 1, $noreg, 0, $noreg, $xmm16
-  VMOVAPDZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm16                                  
+  VMOVAPDZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm16
   ; CHECK: $xmm16 = VMOVAPDZ128rm              $rip, 1, $noreg, 0, $noreg
   $xmm16 = VMOVAPDZ128rm                       $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VMOVAPDZ128rr              $xmm16
-  $xmm16 = VMOVAPDZ128rr                       $xmm16                                                    
+  $xmm16 = VMOVAPDZ128rr                       $xmm16
   ; CHECK: VMOVAPSZ128mr                       $rdi, 1, $noreg, 0, $noreg, $xmm16
-  VMOVAPSZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm16                                  
+  VMOVAPSZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm16
   ; CHECK: $xmm16 = VMOVAPSZ128rm              $rip, 1, $noreg, 0, $noreg
   $xmm16 = VMOVAPSZ128rm                       $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm16 = VMOVAPSZ128rr              $xmm16  
-  $xmm16 = VMOVAPSZ128rr                       $xmm16                                                    
+  ; CHECK: $xmm16 = VMOVAPSZ128rr              $xmm16
+  $xmm16 = VMOVAPSZ128rr                       $xmm16
   ; CHECK: VMOVDQA32Z128mr                     $rdi, 1, $noreg, 0, $noreg, $xmm16
-  VMOVDQA32Z128mr                              $rdi, 1, $noreg, 0, $noreg, $xmm16                                  
+  VMOVDQA32Z128mr                              $rdi, 1, $noreg, 0, $noreg, $xmm16
   ; CHECK: $xmm16 = VMOVDQA32Z128rm            $rip, 1, $noreg, 0, $noreg
   $xmm16 = VMOVDQA32Z128rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VMOVDQA32Z128rr            $xmm16
-  $xmm16 = VMOVDQA32Z128rr                     $xmm16                                                    
+  $xmm16 = VMOVDQA32Z128rr                     $xmm16
   ; CHECK: VMOVDQA64Z128mr                     $rdi, 1, $noreg, 0, $noreg, $xmm16
-  VMOVDQA64Z128mr                              $rdi, 1, $noreg, 0, $noreg, $xmm16                                  
+  VMOVDQA64Z128mr                              $rdi, 1, $noreg, 0, $noreg, $xmm16
   ; CHECK: $xmm16 = VMOVDQA64Z128rm            $rip, 1, $noreg, 0, $noreg
   $xmm16 = VMOVDQA64Z128rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VMOVDQA64Z128rr            $xmm16
-  $xmm16 = VMOVDQA64Z128rr                     $xmm16                                                    
+  $xmm16 = VMOVDQA64Z128rr                     $xmm16
   ; CHECK: VMOVDQU16Z128mr                     $rdi, 1, $noreg, 0, $noreg, $xmm16
-  VMOVDQU16Z128mr                              $rdi, 1, $noreg, 0, $noreg, $xmm16                                  
+  VMOVDQU16Z128mr                              $rdi, 1, $noreg, 0, $noreg, $xmm16
   ; CHECK: $xmm16 = VMOVDQU16Z128rm            $rip, 1, $noreg, 0, $noreg
   $xmm16 = VMOVDQU16Z128rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VMOVDQU16Z128rr            $xmm16
-  $xmm16 = VMOVDQU16Z128rr                     $xmm16                                                    
+  $xmm16 = VMOVDQU16Z128rr                     $xmm16
   ; CHECK: VMOVDQU32Z128mr                     $rdi, 1, $noreg, 0, $noreg, $xmm16
-  VMOVDQU32Z128mr                              $rdi, 1, $noreg, 0, $noreg, $xmm16                                  
+  VMOVDQU32Z128mr                              $rdi, 1, $noreg, 0, $noreg, $xmm16
   ; CHECK: $xmm16 = VMOVDQU32Z128rm            $rip, 1, $noreg, 0, $noreg
   $xmm16 = VMOVDQU32Z128rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VMOVDQU32Z128rr            $xmm16
-  $xmm16 = VMOVDQU32Z128rr                     $xmm16                                                    
+  $xmm16 = VMOVDQU32Z128rr                     $xmm16
   ; CHECK: VMOVDQU64Z128mr                     $rdi, 1, $noreg, 0, $noreg, $xmm16
-  VMOVDQU64Z128mr                              $rdi, 1, $noreg, 0, $noreg, $xmm16                                  
+  VMOVDQU64Z128mr                              $rdi, 1, $noreg, 0, $noreg, $xmm16
   ; CHECK: $xmm16 = VMOVDQU64Z128rm            $rip, 1, $noreg, 0, $noreg
   $xmm16 = VMOVDQU64Z128rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VMOVDQU64Z128rr            $xmm16
-  $xmm16 = VMOVDQU64Z128rr                     $xmm16                                                    
+  $xmm16 = VMOVDQU64Z128rr                     $xmm16
   ; CHECK: VMOVDQU8Z128mr                      $rdi, 1, $noreg, 0, $noreg, $xmm16
-  VMOVDQU8Z128mr                               $rdi, 1, $noreg, 0, $noreg, $xmm16                                  
+  VMOVDQU8Z128mr                               $rdi, 1, $noreg, 0, $noreg, $xmm16
   ; CHECK: $xmm16 = VMOVDQU8Z128rm             $rip, 1, $noreg, 0, $noreg
   $xmm16 = VMOVDQU8Z128rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VMOVDQU8Z128rr             $xmm16
-  $xmm16 = VMOVDQU8Z128rr                      $xmm16                                                    
+  $xmm16 = VMOVDQU8Z128rr                      $xmm16
   ; CHECK: $xmm16 = VMOVNTDQAZ128rm            $rip, 1, $noreg, 0, $noreg
   $xmm16 = VMOVNTDQAZ128rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: VMOVUPDZ128mr                       $rdi, 1, $noreg, 0, $noreg, $xmm16
-  VMOVUPDZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm16                                  
+  VMOVUPDZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm16
   ; CHECK: $xmm16 = VMOVUPDZ128rm              $rip, 1, $noreg, 0, $noreg
   $xmm16 = VMOVUPDZ128rm                       $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VMOVUPDZ128rr              $xmm16
-  $xmm16 = VMOVUPDZ128rr                       $xmm16                                                    
+  $xmm16 = VMOVUPDZ128rr                       $xmm16
   ; CHECK: VMOVUPSZ128mr                       $rdi, 1, $noreg, 0, $noreg, $xmm16
-  VMOVUPSZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm16                                  
+  VMOVUPSZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm16
   ; CHECK: $xmm16 = VMOVUPSZ128rm              $rip, 1, $noreg, 0, $noreg
   $xmm16 = VMOVUPSZ128rm                       $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VMOVUPSZ128rr              $xmm16
-  $xmm16 = VMOVUPSZ128rr                       $xmm16                                                    
+  $xmm16 = VMOVUPSZ128rr                       $xmm16
   ; CHECK: VMOVNTDQZ128mr                      $rdi, 1, $noreg, 0, $noreg, $xmm16
-  VMOVNTDQZ128mr                               $rdi, 1, $noreg, 0, $noreg, $xmm16                                  
+  VMOVNTDQZ128mr                               $rdi, 1, $noreg, 0, $noreg, $xmm16
   ; CHECK: VMOVNTPDZ128mr                      $rdi, 1, $noreg, 0, $noreg, $xmm16
-  VMOVNTPDZ128mr                               $rdi, 1, $noreg, 0, $noreg, $xmm16                                  
+  VMOVNTPDZ128mr                               $rdi, 1, $noreg, 0, $noreg, $xmm16
   ; CHECK: VMOVNTPSZ128mr                      $rdi, 1, $noreg, 0, $noreg, $xmm16
-  VMOVNTPSZ128mr                               $rdi, 1, $noreg, 0, $noreg, $xmm16                                  
+  VMOVNTPSZ128mr                               $rdi, 1, $noreg, 0, $noreg, $xmm16
   ; CHECK: $xmm16 = VPMOVSXBDZ128rm            $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMOVSXBDZ128rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMOVSXBDZ128rr            $xmm16
-  $xmm16 = VPMOVSXBDZ128rr                     $xmm16                                                    
+  $xmm16 = VPMOVSXBDZ128rr                     $xmm16
   ; CHECK: $xmm16 = VPMOVSXBQZ128rm            $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMOVSXBQZ128rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMOVSXBQZ128rr            $xmm16
-  $xmm16 = VPMOVSXBQZ128rr                     $xmm16                                                    
+  $xmm16 = VPMOVSXBQZ128rr                     $xmm16
   ; CHECK: $xmm16 = VPMOVSXBWZ128rm            $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMOVSXBWZ128rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMOVSXBWZ128rr            $xmm16
-  $xmm16 = VPMOVSXBWZ128rr                     $xmm16                                                    
+  $xmm16 = VPMOVSXBWZ128rr                     $xmm16
   ; CHECK: $xmm16 = VPMOVSXDQZ128rm            $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMOVSXDQZ128rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMOVSXDQZ128rr            $xmm16
-  $xmm16 = VPMOVSXDQZ128rr                     $xmm16                                                    
+  $xmm16 = VPMOVSXDQZ128rr                     $xmm16
   ; CHECK: $xmm16 = VPMOVSXWDZ128rm            $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMOVSXWDZ128rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMOVSXWDZ128rr            $xmm16
-  $xmm16 = VPMOVSXWDZ128rr                     $xmm16                                                    
+  $xmm16 = VPMOVSXWDZ128rr                     $xmm16
   ; CHECK: $xmm16 = VPMOVSXWQZ128rm            $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMOVSXWQZ128rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMOVSXWQZ128rr            $xmm16
-  $xmm16 = VPMOVSXWQZ128rr                     $xmm16                                                    
+  $xmm16 = VPMOVSXWQZ128rr                     $xmm16
   ; CHECK: $xmm16 = VPMOVZXBDZ128rm            $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMOVZXBDZ128rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMOVZXBDZ128rr            $xmm16
-  $xmm16 = VPMOVZXBDZ128rr                     $xmm16                                                    
+  $xmm16 = VPMOVZXBDZ128rr                     $xmm16
   ; CHECK: $xmm16 = VPMOVZXBQZ128rm            $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMOVZXBQZ128rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMOVZXBQZ128rr            $xmm16
-  $xmm16 = VPMOVZXBQZ128rr                     $xmm16                                                    
+  $xmm16 = VPMOVZXBQZ128rr                     $xmm16
   ; CHECK: $xmm16 = VPMOVZXBWZ128rm            $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMOVZXBWZ128rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMOVZXBWZ128rr            $xmm16
-  $xmm16 = VPMOVZXBWZ128rr                     $xmm16                                                    
+  $xmm16 = VPMOVZXBWZ128rr                     $xmm16
   ; CHECK: $xmm16 = VPMOVZXDQZ128rm            $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMOVZXDQZ128rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMOVZXDQZ128rr            $xmm16
-  $xmm16 = VPMOVZXDQZ128rr                     $xmm16                                                    
+  $xmm16 = VPMOVZXDQZ128rr                     $xmm16
   ; CHECK: $xmm16 = VPMOVZXWDZ128rm            $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMOVZXWDZ128rm                     $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMOVZXWDZ128rr            $xmm16
-  $xmm16 = VPMOVZXWDZ128rr                     $xmm16                                                    
+  $xmm16 = VPMOVZXWDZ128rr                     $xmm16
   ; CHECK: $xmm16 = VPMOVZXWQZ128rm            $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMOVZXWQZ128rm                     $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm16 = VPMOVZXWQZ128rr            $xmm16  
-  $xmm16 = VPMOVZXWQZ128rr                     $xmm16                                                    
+  ; CHECK: $xmm16 = VPMOVZXWQZ128rr            $xmm16
+  $xmm16 = VPMOVZXWQZ128rr                     $xmm16
   ; CHECK: VMOVHPDZ128mr                       $rdi, 1, $noreg, 0, $noreg, $xmm16
-  VMOVHPDZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm16                                  
+  VMOVHPDZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm16
   ; CHECK: $xmm16 = VMOVHPDZ128rm              $xmm16,  $rdi, 1, $noreg, 0, $noreg
-  $xmm16 = VMOVHPDZ128rm                       $xmm16,  $rdi, 1, $noreg, 0, $noreg                                 
+  $xmm16 = VMOVHPDZ128rm                       $xmm16,  $rdi, 1, $noreg, 0, $noreg
   ; CHECK: VMOVHPSZ128mr                       $rdi, 1, $noreg, 0, $noreg, $xmm16
-  VMOVHPSZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm16                                  
+  VMOVHPSZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm16
   ; CHECK: $xmm16 = VMOVHPSZ128rm              $xmm16,  $rdi, 1, $noreg, 0, $noreg
-  $xmm16 = VMOVHPSZ128rm                       $xmm16,  $rdi, 1, $noreg, 0, $noreg                                 
+  $xmm16 = VMOVHPSZ128rm                       $xmm16,  $rdi, 1, $noreg, 0, $noreg
   ; CHECK: VMOVLPDZ128mr                       $rdi, 1, $noreg, 0, $noreg, $xmm16
-  VMOVLPDZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm16                                  
+  VMOVLPDZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm16
   ; CHECK: $xmm16 = VMOVLPDZ128rm              $xmm16,  $rdi, 1, $noreg, 0, $noreg
-  $xmm16 = VMOVLPDZ128rm                       $xmm16,  $rdi, 1, $noreg, 0, $noreg                                 
+  $xmm16 = VMOVLPDZ128rm                       $xmm16,  $rdi, 1, $noreg, 0, $noreg
   ; CHECK: VMOVLPSZ128mr                       $rdi, 1, $noreg, 0, $noreg, $xmm16
-  VMOVLPSZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm16                                  
-  ; CHECK: $xmm16 = VMOVLPSZ128rm              $xmm16,  $rdi, 1, $noreg, 0, $noreg  
-  $xmm16 = VMOVLPSZ128rm                       $xmm16,  $rdi, 1, $noreg, 0, $noreg                                               
+  VMOVLPSZ128mr                                $rdi, 1, $noreg, 0, $noreg, $xmm16
+  ; CHECK: $xmm16 = VMOVLPSZ128rm              $xmm16,  $rdi, 1, $noreg, 0, $noreg
+  $xmm16 = VMOVLPSZ128rm                       $xmm16,  $rdi, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VMAXCPDZ128rm              $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   $xmm16 = VMAXCPDZ128rm                       $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $xmm16 = VMAXCPDZ128rr              $xmm16, $xmm1, implicit $mxcsr
@@ -3403,183 +3403,183 @@ body: |
   ; CHECK: $xmm16 = VORPDZ128rm                $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VORPDZ128rm                         $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VORPDZ128rr                $xmm16, $xmm1
-  $xmm16 = VORPDZ128rr                         $xmm16, $xmm1                                             
+  $xmm16 = VORPDZ128rr                         $xmm16, $xmm1
   ; CHECK: $xmm16 = VORPSZ128rm                $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VORPSZ128rm                         $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VORPSZ128rr                $xmm16, $xmm1
-  $xmm16 = VORPSZ128rr                         $xmm16, $xmm1                                             
+  $xmm16 = VORPSZ128rr                         $xmm16, $xmm1
   ; CHECK: $xmm16 = VPADDBZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPADDBZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPADDBZ128rr               $xmm16, $xmm1
-  $xmm16 = VPADDBZ128rr                        $xmm16, $xmm1                                             
+  $xmm16 = VPADDBZ128rr                        $xmm16, $xmm1
   ; CHECK: $xmm16 = VPADDDZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPADDDZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPADDDZ128rr               $xmm16, $xmm1
-  $xmm16 = VPADDDZ128rr                        $xmm16, $xmm1                                             
+  $xmm16 = VPADDDZ128rr                        $xmm16, $xmm1
   ; CHECK: $xmm16 = VPADDQZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPADDQZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPADDQZ128rr               $xmm16, $xmm1
-  $xmm16 = VPADDQZ128rr                        $xmm16, $xmm1                                             
+  $xmm16 = VPADDQZ128rr                        $xmm16, $xmm1
   ; CHECK: $xmm16 = VPADDSBZ128rm              $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPADDSBZ128rm                       $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPADDSBZ128rr              $xmm16, $xmm1
-  $xmm16 = VPADDSBZ128rr                       $xmm16, $xmm1                                             
+  $xmm16 = VPADDSBZ128rr                       $xmm16, $xmm1
   ; CHECK: $xmm16 = VPADDSWZ128rm              $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPADDSWZ128rm                       $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPADDSWZ128rr              $xmm16, $xmm1
-  $xmm16 = VPADDSWZ128rr                       $xmm16, $xmm1                                             
+  $xmm16 = VPADDSWZ128rr                       $xmm16, $xmm1
   ; CHECK: $xmm16 = VPADDUSBZ128rm             $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPADDUSBZ128rm                      $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPADDUSBZ128rr             $xmm16, $xmm1
-  $xmm16 = VPADDUSBZ128rr                      $xmm16, $xmm1                                             
+  $xmm16 = VPADDUSBZ128rr                      $xmm16, $xmm1
   ; CHECK: $xmm16 = VPADDUSWZ128rm             $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPADDUSWZ128rm                      $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPADDUSWZ128rr             $xmm16, $xmm1
-  $xmm16 = VPADDUSWZ128rr                      $xmm16, $xmm1                                             
+  $xmm16 = VPADDUSWZ128rr                      $xmm16, $xmm1
   ; CHECK: $xmm16 = VPADDWZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPADDWZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPADDWZ128rr               $xmm16, $xmm1
-  $xmm16 = VPADDWZ128rr                        $xmm16, $xmm1                                             
+  $xmm16 = VPADDWZ128rr                        $xmm16, $xmm1
   ; CHECK: $xmm16 = VPANDDZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPANDDZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPANDDZ128rr               $xmm16, $xmm1
-  $xmm16 = VPANDDZ128rr                        $xmm16, $xmm1                                             
+  $xmm16 = VPANDDZ128rr                        $xmm16, $xmm1
   ; CHECK: $xmm16 = VPANDQZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPANDQZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm16 = VPANDQZ128rr               $xmm16, $xmm1  
-  $xmm16 = VPANDQZ128rr                        $xmm16, $xmm1                                             
+  ; CHECK: $xmm16 = VPANDQZ128rr               $xmm16, $xmm1
+  $xmm16 = VPANDQZ128rr                        $xmm16, $xmm1
   ; CHECK: $xmm16 = VPANDNDZ128rm              $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPANDNDZ128rm                       $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPANDNDZ128rr              $xmm16, $xmm1
-  $xmm16 = VPANDNDZ128rr                       $xmm16, $xmm1                                             
+  $xmm16 = VPANDNDZ128rr                       $xmm16, $xmm1
   ; CHECK: $xmm16 = VPANDNQZ128rm              $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPANDNQZ128rm                       $xmm16, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm16 = VPANDNQZ128rr              $xmm16, $xmm1  
-  $xmm16 = VPANDNQZ128rr                       $xmm16, $xmm1                                             
+  ; CHECK: $xmm16 = VPANDNQZ128rr              $xmm16, $xmm1
+  $xmm16 = VPANDNQZ128rr                       $xmm16, $xmm1
   ; CHECK: $xmm16 = VPAVGBZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPAVGBZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm16 = VPAVGBZ128rr               $xmm16, $xmm1  
-  $xmm16 = VPAVGBZ128rr                        $xmm16, $xmm1                                             
+  ; CHECK: $xmm16 = VPAVGBZ128rr               $xmm16, $xmm1
+  $xmm16 = VPAVGBZ128rr                        $xmm16, $xmm1
   ; CHECK: $xmm16 = VPAVGWZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPAVGWZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPAVGWZ128rr               $xmm16, $xmm1
-  $xmm16 = VPAVGWZ128rr                        $xmm16, $xmm1                                             
+  $xmm16 = VPAVGWZ128rr                        $xmm16, $xmm1
   ; CHECK: $xmm16 = VPMAXSBZ128rm              $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMAXSBZ128rm                       $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMAXSBZ128rr              $xmm16, $xmm1
-  $xmm16 = VPMAXSBZ128rr                       $xmm16, $xmm1                                             
+  $xmm16 = VPMAXSBZ128rr                       $xmm16, $xmm1
   ; CHECK: $xmm16 = VPMAXSDZ128rm              $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMAXSDZ128rm                       $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMAXSDZ128rr              $xmm16, $xmm1
-  $xmm16 = VPMAXSDZ128rr                       $xmm16, $xmm1                                             
+  $xmm16 = VPMAXSDZ128rr                       $xmm16, $xmm1
   ; CHECK: $xmm16 = VPMAXSWZ128rm              $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMAXSWZ128rm                       $xmm16, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm16 = VPMAXSWZ128rr              $xmm16, $xmm1  
-  $xmm16 = VPMAXSWZ128rr                       $xmm16, $xmm1                                             
+  ; CHECK: $xmm16 = VPMAXSWZ128rr              $xmm16, $xmm1
+  $xmm16 = VPMAXSWZ128rr                       $xmm16, $xmm1
   ; CHECK: $xmm16 = VPMAXUBZ128rm              $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMAXUBZ128rm                       $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMAXUBZ128rr              $xmm16, $xmm1
-  $xmm16 = VPMAXUBZ128rr                       $xmm16, $xmm1                                             
+  $xmm16 = VPMAXUBZ128rr                       $xmm16, $xmm1
   ; CHECK: $xmm16 = VPMAXUDZ128rm              $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMAXUDZ128rm                       $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMAXUDZ128rr              $xmm16, $xmm1
-  $xmm16 = VPMAXUDZ128rr                       $xmm16, $xmm1                                             
+  $xmm16 = VPMAXUDZ128rr                       $xmm16, $xmm1
   ; CHECK: $xmm16 = VPMAXUWZ128rm              $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMAXUWZ128rm                       $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMAXUWZ128rr              $xmm16, $xmm1
-  $xmm16 = VPMAXUWZ128rr                       $xmm16, $xmm1                                             
+  $xmm16 = VPMAXUWZ128rr                       $xmm16, $xmm1
   ; CHECK: $xmm16 = VPMINSBZ128rm              $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMINSBZ128rm                       $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMINSBZ128rr              $xmm16, $xmm1
-  $xmm16 = VPMINSBZ128rr                       $xmm16, $xmm1                                             
+  $xmm16 = VPMINSBZ128rr                       $xmm16, $xmm1
   ; CHECK: $xmm16 = VPMINSDZ128rm              $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMINSDZ128rm                       $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMINSDZ128rr              $xmm16, $xmm1
-  $xmm16 = VPMINSDZ128rr                       $xmm16, $xmm1                                             
+  $xmm16 = VPMINSDZ128rr                       $xmm16, $xmm1
   ; CHECK: $xmm16 = VPMINSWZ128rm              $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMINSWZ128rm                       $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMINSWZ128rr              $xmm16, $xmm1
-  $xmm16 = VPMINSWZ128rr                       $xmm16, $xmm1                                             
+  $xmm16 = VPMINSWZ128rr                       $xmm16, $xmm1
   ; CHECK: $xmm16 = VPMINUBZ128rm              $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMINUBZ128rm                       $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMINUBZ128rr              $xmm16, $xmm1
-  $xmm16 = VPMINUBZ128rr                       $xmm16, $xmm1                                             
+  $xmm16 = VPMINUBZ128rr                       $xmm16, $xmm1
   ; CHECK: $xmm16 = VPMINUDZ128rm              $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMINUDZ128rm                       $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMINUDZ128rr              $xmm16, $xmm1
-  $xmm16 = VPMINUDZ128rr                       $xmm16, $xmm1                                             
+  $xmm16 = VPMINUDZ128rr                       $xmm16, $xmm1
   ; CHECK: $xmm16 = VPMINUWZ128rm              $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMINUWZ128rm                       $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMINUWZ128rr              $xmm16, $xmm1
-  $xmm16 = VPMINUWZ128rr                       $xmm16, $xmm1                                             
+  $xmm16 = VPMINUWZ128rr                       $xmm16, $xmm1
   ; CHECK: $xmm16 = VPMULDQZ128rm              $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMULDQZ128rm                       $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMULDQZ128rr              $xmm16, $xmm1
-  $xmm16 = VPMULDQZ128rr                       $xmm16, $xmm1                                             
+  $xmm16 = VPMULDQZ128rr                       $xmm16, $xmm1
   ; CHECK: $xmm16 = VPMULHRSWZ128rm            $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMULHRSWZ128rm                     $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMULHRSWZ128rr            $xmm16, $xmm1
-  $xmm16 = VPMULHRSWZ128rr                     $xmm16, $xmm1                                             
+  $xmm16 = VPMULHRSWZ128rr                     $xmm16, $xmm1
   ; CHECK: $xmm16 = VPMULHUWZ128rm             $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMULHUWZ128rm                      $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMULHUWZ128rr             $xmm16, $xmm1
-  $xmm16 = VPMULHUWZ128rr                      $xmm16, $xmm1                                             
+  $xmm16 = VPMULHUWZ128rr                      $xmm16, $xmm1
   ; CHECK: $xmm16 = VPMULHWZ128rm              $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMULHWZ128rm                       $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMULHWZ128rr              $xmm16, $xmm1
-  $xmm16 = VPMULHWZ128rr                       $xmm16, $xmm1                                             
+  $xmm16 = VPMULHWZ128rr                       $xmm16, $xmm1
   ; CHECK: $xmm16 = VPMULLDZ128rm              $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMULLDZ128rm                       $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMULLDZ128rr              $xmm16, $xmm1
-  $xmm16 = VPMULLDZ128rr                       $xmm16, $xmm1                                             
+  $xmm16 = VPMULLDZ128rr                       $xmm16, $xmm1
   ; CHECK: $xmm16 = VPMULLWZ128rm              $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMULLWZ128rm                       $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMULLWZ128rr              $xmm16, $xmm1
-  $xmm16 = VPMULLWZ128rr                       $xmm16, $xmm1                                             
+  $xmm16 = VPMULLWZ128rr                       $xmm16, $xmm1
   ; CHECK: $xmm16 = VPMULUDQZ128rm             $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMULUDQZ128rm                      $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMULUDQZ128rr             $xmm16, $xmm1
-  $xmm16 = VPMULUDQZ128rr                      $xmm16, $xmm1                                             
+  $xmm16 = VPMULUDQZ128rr                      $xmm16, $xmm1
   ; CHECK: $xmm16 = VPORDZ128rm                $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPORDZ128rm                         $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPORDZ128rr                $xmm16, $xmm1
-  $xmm16 = VPORDZ128rr                         $xmm16, $xmm1                                             
+  $xmm16 = VPORDZ128rr                         $xmm16, $xmm1
   ; CHECK: $xmm16 = VPORQZ128rm                $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPORQZ128rm                         $xmm16, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm16 = VPORQZ128rr                $xmm16, $xmm1  
-  $xmm16 = VPORQZ128rr                         $xmm16, $xmm1                                             
+  ; CHECK: $xmm16 = VPORQZ128rr                $xmm16, $xmm1
+  $xmm16 = VPORQZ128rr                         $xmm16, $xmm1
   ; CHECK: $xmm16 = VPSUBBZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPSUBBZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPSUBBZ128rr               $xmm16, $xmm1
-  $xmm16 = VPSUBBZ128rr                        $xmm16, $xmm1                                             
+  $xmm16 = VPSUBBZ128rr                        $xmm16, $xmm1
   ; CHECK: $xmm16 = VPSUBDZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPSUBDZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPSUBDZ128rr               $xmm16, $xmm1
-  $xmm16 = VPSUBDZ128rr                        $xmm16, $xmm1                                             
+  $xmm16 = VPSUBDZ128rr                        $xmm16, $xmm1
   ; CHECK: $xmm16 = VPSUBQZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPSUBQZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPSUBQZ128rr               $xmm16, $xmm1
-  $xmm16 = VPSUBQZ128rr                        $xmm16, $xmm1                                             
+  $xmm16 = VPSUBQZ128rr                        $xmm16, $xmm1
   ; CHECK: $xmm16 = VPSUBSBZ128rm              $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPSUBSBZ128rm                       $xmm16, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm16 = VPSUBSBZ128rr              $xmm16, $xmm1  
-  $xmm16 = VPSUBSBZ128rr                       $xmm16, $xmm1                                             
+  ; CHECK: $xmm16 = VPSUBSBZ128rr              $xmm16, $xmm1
+  $xmm16 = VPSUBSBZ128rr                       $xmm16, $xmm1
   ; CHECK: $xmm16 = VPSUBSWZ128rm              $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPSUBSWZ128rm                       $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPSUBSWZ128rr              $xmm16, $xmm1
-  $xmm16 = VPSUBSWZ128rr                       $xmm16, $xmm1                                             
+  $xmm16 = VPSUBSWZ128rr                       $xmm16, $xmm1
   ; CHECK: $xmm16 = VPSUBUSBZ128rm             $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPSUBUSBZ128rm                      $xmm16, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm16 = VPSUBUSBZ128rr             $xmm16, $xmm1  
-  $xmm16 = VPSUBUSBZ128rr                      $xmm16, $xmm1                                             
+  ; CHECK: $xmm16 = VPSUBUSBZ128rr             $xmm16, $xmm1
+  $xmm16 = VPSUBUSBZ128rr                      $xmm16, $xmm1
   ; CHECK: $xmm16 = VPSUBUSWZ128rm             $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPSUBUSWZ128rm                      $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPSUBUSWZ128rr             $xmm16, $xmm1
-  $xmm16 = VPSUBUSWZ128rr                      $xmm16, $xmm1                                             
+  $xmm16 = VPSUBUSWZ128rr                      $xmm16, $xmm1
   ; CHECK: $xmm16 = VPSUBWZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPSUBWZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm16 = VPSUBWZ128rr               $xmm16, $xmm1                            
-  $xmm16 = VPSUBWZ128rr                        $xmm16, $xmm1                                             
+  ; CHECK: $xmm16 = VPSUBWZ128rr               $xmm16, $xmm1
+  $xmm16 = VPSUBWZ128rr                        $xmm16, $xmm1
   ; CHECK: $xmm16 = VADDPDZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   $xmm16 = VADDPDZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $xmm16 = VADDPDZ128rr               $xmm16, $xmm1, implicit $mxcsr
@@ -3591,19 +3591,19 @@ body: |
   ; CHECK: $xmm16 = VANDNPDZ128rm              $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VANDNPDZ128rm                       $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VANDNPDZ128rr              $xmm16, $xmm1
-  $xmm16 = VANDNPDZ128rr                       $xmm16, $xmm1                                             
+  $xmm16 = VANDNPDZ128rr                       $xmm16, $xmm1
   ; CHECK: $xmm16 = VANDNPSZ128rm              $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VANDNPSZ128rm                       $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VANDNPSZ128rr              $xmm16, $xmm1
-  $xmm16 = VANDNPSZ128rr                       $xmm16, $xmm1                                             
+  $xmm16 = VANDNPSZ128rr                       $xmm16, $xmm1
   ; CHECK: $xmm16 = VANDPDZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VANDPDZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm16 = VANDPDZ128rr               $xmm16, $xmm1  
-  $xmm16 = VANDPDZ128rr                        $xmm16, $xmm1                                             
+  ; CHECK: $xmm16 = VANDPDZ128rr               $xmm16, $xmm1
+  $xmm16 = VANDPDZ128rr                        $xmm16, $xmm1
   ; CHECK: $xmm16 = VANDPSZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VANDPSZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VANDPSZ128rr               $xmm16, $xmm1
-  $xmm16 = VANDPSZ128rr                        $xmm16, $xmm1                                             
+  $xmm16 = VANDPSZ128rr                        $xmm16, $xmm1
   ; CHECK: $xmm16 = VDIVPDZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   $xmm16 = VDIVPDZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $xmm16 = VDIVPDZ128rr               $xmm16, $xmm1, implicit $mxcsr
@@ -3615,11 +3615,11 @@ body: |
   ; CHECK: $xmm16 = VPXORDZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPXORDZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPXORDZ128rr               $xmm16, $xmm1
-  $xmm16 = VPXORDZ128rr                        $xmm16, $xmm1                                             
+  $xmm16 = VPXORDZ128rr                        $xmm16, $xmm1
   ; CHECK: $xmm16 = VPXORQZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPXORQZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPXORQZ128rr               $xmm16, $xmm1
-  $xmm16 = VPXORQZ128rr                        $xmm16, $xmm1                                             
+  $xmm16 = VPXORQZ128rr                        $xmm16, $xmm1
   ; CHECK: $xmm16 = VSUBPDZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   $xmm16 = VSUBPDZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $xmm16 = VSUBPDZ128rr               $xmm16, $xmm1, implicit $mxcsr
@@ -3631,83 +3631,83 @@ body: |
   ; CHECK: $xmm16 = VXORPDZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VXORPDZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VXORPDZ128rr               $xmm16, $xmm1
-  $xmm16 = VXORPDZ128rr                        $xmm16, $xmm1                                             
+  $xmm16 = VXORPDZ128rr                        $xmm16, $xmm1
   ; CHECK: $xmm16 = VXORPSZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VXORPSZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VXORPSZ128rr               $xmm16, $xmm1
-  $xmm16 = VXORPSZ128rr                        $xmm16, $xmm1                                             
+  $xmm16 = VXORPSZ128rr                        $xmm16, $xmm1
   ; CHECK: $xmm16 = VPMADDUBSWZ128rm           $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMADDUBSWZ128rm                    $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPMADDUBSWZ128rr           $xmm16, $xmm1
-  $xmm16 = VPMADDUBSWZ128rr                    $xmm16, $xmm1                                             
+  $xmm16 = VPMADDUBSWZ128rr                    $xmm16, $xmm1
   ; CHECK: $xmm16 = VPMADDWDZ128rm             $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPMADDWDZ128rm                      $xmm16, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm16 = VPMADDWDZ128rr             $xmm16, $xmm1                                               
-  $xmm16 = VPMADDWDZ128rr                      $xmm16, $xmm1                                                 
+  ; CHECK: $xmm16 = VPMADDWDZ128rr             $xmm16, $xmm1
+  $xmm16 = VPMADDWDZ128rr                      $xmm16, $xmm1
   ; CHECK: $xmm16 = VPACKSSDWZ128rm            $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPACKSSDWZ128rm                     $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPACKSSDWZ128rr            $xmm16, $xmm1
-  $xmm16 = VPACKSSDWZ128rr                     $xmm16, $xmm1                                             
+  $xmm16 = VPACKSSDWZ128rr                     $xmm16, $xmm1
   ; CHECK: $xmm16 = VPACKSSWBZ128rm            $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPACKSSWBZ128rm                     $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPACKSSWBZ128rr            $xmm16, $xmm1
-  $xmm16 = VPACKSSWBZ128rr                     $xmm16, $xmm1                                             
+  $xmm16 = VPACKSSWBZ128rr                     $xmm16, $xmm1
   ; CHECK: $xmm16 = VPACKUSDWZ128rm            $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPACKUSDWZ128rm                     $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPACKUSDWZ128rr            $xmm16, $xmm1
-  $xmm16 = VPACKUSDWZ128rr                     $xmm16, $xmm1                                             
+  $xmm16 = VPACKUSDWZ128rr                     $xmm16, $xmm1
   ; CHECK: $xmm16 = VPACKUSWBZ128rm            $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPACKUSWBZ128rm                     $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPACKUSWBZ128rr            $xmm16, $xmm1
-  $xmm16 = VPACKUSWBZ128rr                     $xmm16, $xmm1                                             
+  $xmm16 = VPACKUSWBZ128rr                     $xmm16, $xmm1
   ; CHECK: $xmm16 = VPUNPCKHBWZ128rm           $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPUNPCKHBWZ128rm                    $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPUNPCKHBWZ128rr           $xmm16, $xmm1
-  $xmm16 = VPUNPCKHBWZ128rr                    $xmm16, $xmm1                                             
+  $xmm16 = VPUNPCKHBWZ128rr                    $xmm16, $xmm1
   ; CHECK: $xmm16 = VPUNPCKHDQZ128rm           $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPUNPCKHDQZ128rm                    $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPUNPCKHDQZ128rr           $xmm16, $xmm1
-  $xmm16 = VPUNPCKHDQZ128rr                    $xmm16, $xmm1                                             
+  $xmm16 = VPUNPCKHDQZ128rr                    $xmm16, $xmm1
   ; CHECK: $xmm16 = VPUNPCKHQDQZ128rm          $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPUNPCKHQDQZ128rm                   $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPUNPCKHQDQZ128rr          $xmm16, $xmm1
-  $xmm16 = VPUNPCKHQDQZ128rr                   $xmm16, $xmm1                                             
+  $xmm16 = VPUNPCKHQDQZ128rr                   $xmm16, $xmm1
   ; CHECK: $xmm16 = VPUNPCKHWDZ128rm           $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPUNPCKHWDZ128rm                    $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPUNPCKHWDZ128rr           $xmm16, $xmm1
-  $xmm16 = VPUNPCKHWDZ128rr                    $xmm16, $xmm1                                             
+  $xmm16 = VPUNPCKHWDZ128rr                    $xmm16, $xmm1
   ; CHECK: $xmm16 = VPUNPCKLBWZ128rm           $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPUNPCKLBWZ128rm                    $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPUNPCKLBWZ128rr           $xmm16, $xmm1
-  $xmm16 = VPUNPCKLBWZ128rr                    $xmm16, $xmm1                                             
+  $xmm16 = VPUNPCKLBWZ128rr                    $xmm16, $xmm1
   ; CHECK: $xmm16 = VPUNPCKLDQZ128rm           $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPUNPCKLDQZ128rm                    $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPUNPCKLDQZ128rr           $xmm16, $xmm1
-  $xmm16 = VPUNPCKLDQZ128rr                    $xmm16, $xmm1                                             
+  $xmm16 = VPUNPCKLDQZ128rr                    $xmm16, $xmm1
   ; CHECK: $xmm16 = VPUNPCKLQDQZ128rm          $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPUNPCKLQDQZ128rm                   $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPUNPCKLQDQZ128rr          $xmm16, $xmm1
-  $xmm16 = VPUNPCKLQDQZ128rr                   $xmm16, $xmm1                                             
+  $xmm16 = VPUNPCKLQDQZ128rr                   $xmm16, $xmm1
   ; CHECK: $xmm16 = VPUNPCKLWDZ128rm           $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPUNPCKLWDZ128rm                    $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPUNPCKLWDZ128rr           $xmm16, $xmm1
-  $xmm16 = VPUNPCKLWDZ128rr                    $xmm16, $xmm1                                             
+  $xmm16 = VPUNPCKLWDZ128rr                    $xmm16, $xmm1
   ; CHECK: $xmm16 = VUNPCKHPDZ128rm            $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VUNPCKHPDZ128rm                     $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VUNPCKHPDZ128rr            $xmm16, $xmm1
-  $xmm16 = VUNPCKHPDZ128rr                     $xmm16, $xmm1                                             
+  $xmm16 = VUNPCKHPDZ128rr                     $xmm16, $xmm1
   ; CHECK: $xmm16 = VUNPCKHPSZ128rm            $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VUNPCKHPSZ128rm                     $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VUNPCKHPSZ128rr            $xmm16, $xmm1
-  $xmm16 = VUNPCKHPSZ128rr                     $xmm16, $xmm1                                             
+  $xmm16 = VUNPCKHPSZ128rr                     $xmm16, $xmm1
   ; CHECK: $xmm16 = VUNPCKLPDZ128rm            $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VUNPCKLPDZ128rm                     $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VUNPCKLPDZ128rr            $xmm16, $xmm1
-  $xmm16 = VUNPCKLPDZ128rr                     $xmm16, $xmm1                                             
+  $xmm16 = VUNPCKLPDZ128rr                     $xmm16, $xmm1
   ; CHECK: $xmm16 = VUNPCKLPSZ128rm            $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VUNPCKLPSZ128rm                     $xmm16, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm16 = VUNPCKLPSZ128rr            $xmm16, $xmm1                                               
-  $xmm16 = VUNPCKLPSZ128rr                     $xmm16, $xmm1                                                             
+  ; CHECK: $xmm16 = VUNPCKLPSZ128rr            $xmm16, $xmm1
+  $xmm16 = VUNPCKLPSZ128rr                     $xmm16, $xmm1
   ; CHECK: $xmm16 = VFMADD132PDZ128m           $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
   $xmm16 = VFMADD132PDZ128m                    $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $xmm16 = VFMADD132PDZ128r           $xmm16, $xmm1, $xmm2, implicit $mxcsr
@@ -3852,14 +3852,14 @@ body: |
   $xmm16 = VFNMSUB231PSZ128m                   $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $xmm16 = VFNMSUB231PSZ128r          $xmm16, $xmm1, $xmm2, implicit $mxcsr
   $xmm16 = VFNMSUB231PSZ128r                   $xmm16, $xmm1, $xmm2, implicit $mxcsr
-  ; CHECK: $xmm16 = VPSLLDZ128ri               $xmm16, 7  
-  $xmm16 = VPSLLDZ128ri                        $xmm16, 7                                                 
+  ; CHECK: $xmm16 = VPSLLDZ128ri               $xmm16, 7
+  $xmm16 = VPSLLDZ128ri                        $xmm16, 7
   ; CHECK: $xmm16 = VPSLLDZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPSLLDZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPSLLDZ128rr               $xmm16, $xmm16
   $xmm16 = VPSLLDZ128rr                        $xmm16, $xmm16
   ; CHECK: $xmm16 = VPSLLQZ128ri               $xmm16, 7
-  $xmm16 = VPSLLQZ128ri                        $xmm16, 7                                                 
+  $xmm16 = VPSLLQZ128ri                        $xmm16, 7
   ; CHECK: $xmm16 = VPSLLQZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPSLLQZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPSLLQZ128rr               $xmm16, $xmm16
@@ -3873,13 +3873,13 @@ body: |
   ; CHECK: $xmm16 = VPSLLVQZ128rr              $xmm16, $xmm16
   $xmm16 = VPSLLVQZ128rr                       $xmm16, $xmm16
   ; CHECK: $xmm16 = VPSLLWZ128ri               $xmm16, 7
-  $xmm16 = VPSLLWZ128ri                        $xmm16, 7                                                 
+  $xmm16 = VPSLLWZ128ri                        $xmm16, 7
   ; CHECK: $xmm16 = VPSLLWZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPSLLWZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPSLLWZ128rr               $xmm16, $xmm16
   $xmm16 = VPSLLWZ128rr                        $xmm16, $xmm16
   ; CHECK: $xmm16 = VPSRADZ128ri               $xmm16, 7
-  $xmm16 = VPSRADZ128ri                        $xmm16, 7                                                 
+  $xmm16 = VPSRADZ128ri                        $xmm16, 7
   ; CHECK: $xmm16 = VPSRADZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPSRADZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPSRADZ128rr               $xmm16, $xmm16
@@ -3888,22 +3888,22 @@ body: |
   $xmm16 = VPSRAVDZ128rm                       $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPSRAVDZ128rr              $xmm16, $xmm16
   $xmm16 = VPSRAVDZ128rr                       $xmm16, $xmm16
-  ; CHECK: $xmm16 = VPSRAWZ128ri               $xmm16, 7 
-  $xmm16 = VPSRAWZ128ri                        $xmm16, 7                                                 
+  ; CHECK: $xmm16 = VPSRAWZ128ri               $xmm16, 7
+  $xmm16 = VPSRAWZ128ri                        $xmm16, 7
   ; CHECK: $xmm16 = VPSRAWZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPSRAWZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPSRAWZ128rr               $xmm16, $xmm16
   $xmm16 = VPSRAWZ128rr                        $xmm16, $xmm16
   ; CHECK: $xmm16 = VPSRLDQZ128ri              $xmm16, 14
-  $xmm16 = VPSRLDQZ128ri                       $xmm16, 14                                                
-  ; CHECK: $xmm16 = VPSRLDZ128ri               $xmm16, 7 
-  $xmm16 = VPSRLDZ128ri                        $xmm16, 7                                                 
+  $xmm16 = VPSRLDQZ128ri                       $xmm16, 14
+  ; CHECK: $xmm16 = VPSRLDZ128ri               $xmm16, 7
+  $xmm16 = VPSRLDZ128ri                        $xmm16, 7
   ; CHECK: $xmm16 = VPSRLDZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPSRLDZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPSRLDZ128rr               $xmm16, $xmm16
   $xmm16 = VPSRLDZ128rr                        $xmm16, $xmm16
-  ; CHECK: $xmm16 = VPSRLQZ128ri               $xmm16, 7 
-  $xmm16 = VPSRLQZ128ri                        $xmm16, 7                                                 
+  ; CHECK: $xmm16 = VPSRLQZ128ri               $xmm16, 7
+  $xmm16 = VPSRLQZ128ri                        $xmm16, 7
   ; CHECK: $xmm16 = VPSRLQZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPSRLQZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPSRLQZ128rr               $xmm16, $xmm16
@@ -3917,7 +3917,7 @@ body: |
   ; CHECK: $xmm16 = VPSRLVQZ128rr              $xmm16, $xmm16
   $xmm16 = VPSRLVQZ128rr                       $xmm16, $xmm16
   ; CHECK: $xmm16 = VPSRLWZ128ri               $xmm16, 7
-  $xmm16 = VPSRLWZ128ri                        $xmm16, 7                                                 
+  $xmm16 = VPSRLWZ128ri                        $xmm16, 7
   ; CHECK: $xmm16 = VPSRLWZ128rm               $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPSRLWZ128rm                        $xmm16, $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPSRLWZ128rr               $xmm16, $xmm16
@@ -3925,27 +3925,27 @@ body: |
   ; CHECK: $xmm16 = VPERMILPDZ128mi            $rdi, 1, $noreg, 0, $noreg, 9
   $xmm16 = VPERMILPDZ128mi                     $rdi, 1, $noreg, 0, $noreg, 9
   ; CHECK: $xmm16 = VPERMILPDZ128ri            $xmm16, 9
-  $xmm16 = VPERMILPDZ128ri                     $xmm16, 9                                                 
+  $xmm16 = VPERMILPDZ128ri                     $xmm16, 9
   ; CHECK: $xmm16 = VPERMILPDZ128rm            $xmm16, $rdi, 1, $noreg, 0, $noreg
-  $xmm16 = VPERMILPDZ128rm                     $xmm16, $rdi, 1, $noreg, 0, $noreg                                  
+  $xmm16 = VPERMILPDZ128rm                     $xmm16, $rdi, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPERMILPDZ128rr            $xmm16, $xmm1
-  $xmm16 = VPERMILPDZ128rr                     $xmm16, $xmm1                                             
+  $xmm16 = VPERMILPDZ128rr                     $xmm16, $xmm1
   ; CHECK: $xmm16 = VPERMILPSZ128mi            $rdi, 1, $noreg, 0, $noreg, 9
   $xmm16 = VPERMILPSZ128mi                     $rdi, 1, $noreg, 0, $noreg, 9
   ; CHECK: $xmm16 = VPERMILPSZ128ri            $xmm16, 9
-  $xmm16 = VPERMILPSZ128ri                     $xmm16, 9                                                 
+  $xmm16 = VPERMILPSZ128ri                     $xmm16, 9
   ; CHECK: $xmm16 = VPERMILPSZ128rm            $xmm16, $rdi, 1, $noreg, 0, $noreg
-  $xmm16 = VPERMILPSZ128rm                     $xmm16, $rdi, 1, $noreg, 0, $noreg                                  
+  $xmm16 = VPERMILPSZ128rm                     $xmm16, $rdi, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPERMILPSZ128rr            $xmm16, $xmm1
-  $xmm16 = VPERMILPSZ128rr                     $xmm16, $xmm1                                               
+  $xmm16 = VPERMILPSZ128rr                     $xmm16, $xmm1
   ; CHECK: $xmm16 = VCVTPH2PSZ128rm            $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
   $xmm16 = VCVTPH2PSZ128rm                     $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $xmm16 = VCVTPH2PSZ128rr            $xmm16, implicit $mxcsr
   $xmm16 = VCVTPH2PSZ128rr                     $xmm16, implicit $mxcsr
   ; CHECK: $xmm16 = VCVTDQ2PDZ128rm            $rdi, 1, $noreg, 0, $noreg
   $xmm16 = VCVTDQ2PDZ128rm                     $rdi, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm16 = VCVTDQ2PDZ128rr            $xmm16     
-  $xmm16 = VCVTDQ2PDZ128rr                     $xmm16                                                    
+  ; CHECK: $xmm16 = VCVTDQ2PDZ128rr            $xmm16
+  $xmm16 = VCVTDQ2PDZ128rr                     $xmm16
   ; CHECK: $xmm16 = VCVTDQ2PSZ128rm            $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
   $xmm16 = VCVTDQ2PSZ128rm                     $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $xmm16 = VCVTDQ2PSZ128rr            $xmm16, implicit $mxcsr
@@ -3982,34 +3982,34 @@ body: |
   $xmm16 = VSQRTPSZ128m                        $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $xmm16 = VSQRTPSZ128r               $xmm16, implicit $mxcsr
   $xmm16 = VSQRTPSZ128r                        $xmm16, implicit $mxcsr
-  ; CHECK: $xmm16 = VMOVDDUPZ128rm             $rdi, 1, $noreg, 0, $noreg     
-  $xmm16 = VMOVDDUPZ128rm                      $rdi, 1, $noreg, 0, $noreg                                          
-  ; CHECK: $xmm16 = VMOVDDUPZ128rr             $xmm16    
-  $xmm16 = VMOVDDUPZ128rr                      $xmm16                                                    
-  ; CHECK: $xmm16 = VMOVSHDUPZ128rm            $rdi, 1, $noreg, 0, $noreg    
-  $xmm16 = VMOVSHDUPZ128rm                     $rdi, 1, $noreg, 0, $noreg                                          
-  ; CHECK: $xmm16 = VMOVSHDUPZ128rr            $xmm16    
-  $xmm16 = VMOVSHDUPZ128rr                     $xmm16                                                    
-  ; CHECK: $xmm16 = VMOVSLDUPZ128rm            $rdi, 1, $noreg, 0, $noreg     
-  $xmm16 = VMOVSLDUPZ128rm                     $rdi, 1, $noreg, 0, $noreg                                          
-  ; CHECK: $xmm16 = VMOVSLDUPZ128rr            $xmm16  
-  $xmm16 = VMOVSLDUPZ128rr                     $xmm16                                                    
+  ; CHECK: $xmm16 = VMOVDDUPZ128rm             $rdi, 1, $noreg, 0, $noreg
+  $xmm16 = VMOVDDUPZ128rm                      $rdi, 1, $noreg, 0, $noreg
+  ; CHECK: $xmm16 = VMOVDDUPZ128rr             $xmm16
+  $xmm16 = VMOVDDUPZ128rr                      $xmm16
+  ; CHECK: $xmm16 = VMOVSHDUPZ128rm            $rdi, 1, $noreg, 0, $noreg
+  $xmm16 = VMOVSHDUPZ128rm                     $rdi, 1, $noreg, 0, $noreg
+  ; CHECK: $xmm16 = VMOVSHDUPZ128rr            $xmm16
+  $xmm16 = VMOVSHDUPZ128rr                     $xmm16
+  ; CHECK: $xmm16 = VMOVSLDUPZ128rm            $rdi, 1, $noreg, 0, $noreg
+  $xmm16 = VMOVSLDUPZ128rm                     $rdi, 1, $noreg, 0, $noreg
+  ; CHECK: $xmm16 = VMOVSLDUPZ128rr            $xmm16
+  $xmm16 = VMOVSLDUPZ128rr                     $xmm16
   ; CHECK: $xmm16 = VPSHUFBZ128rm              $xmm16, $rdi, 1, $noreg, 0, $noreg
   $xmm16 = VPSHUFBZ128rm                       $xmm16, $rdi, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPSHUFBZ128rr              $xmm16, $xmm1
-  $xmm16 = VPSHUFBZ128rr                       $xmm16, $xmm1                                             
+  $xmm16 = VPSHUFBZ128rr                       $xmm16, $xmm1
   ; CHECK: $xmm16 = VPSHUFDZ128mi              $rdi, 1, $noreg, 0, $noreg, -24
   $xmm16 = VPSHUFDZ128mi                       $rdi, 1, $noreg, 0, $noreg, -24
   ; CHECK: $xmm16 = VPSHUFDZ128ri              $xmm16, -24
-  $xmm16 = VPSHUFDZ128ri                       $xmm16, -24                                               
+  $xmm16 = VPSHUFDZ128ri                       $xmm16, -24
   ; CHECK: $xmm16 = VPSHUFHWZ128mi             $rdi, 1, $noreg, 0, $noreg, -24
   $xmm16 = VPSHUFHWZ128mi                      $rdi, 1, $noreg, 0, $noreg, -24
   ; CHECK: $xmm16 = VPSHUFHWZ128ri             $xmm16, -24
-  $xmm16 = VPSHUFHWZ128ri                      $xmm16, -24                                               
+  $xmm16 = VPSHUFHWZ128ri                      $xmm16, -24
   ; CHECK: $xmm16 = VPSHUFLWZ128mi             $rdi, 1, $noreg, 0, $noreg, -24
   $xmm16 = VPSHUFLWZ128mi                      $rdi, 1, $noreg, 0, $noreg, -24
   ; CHECK: $xmm16 = VPSHUFLWZ128ri             $xmm16, -24
-  $xmm16 = VPSHUFLWZ128ri                      $xmm16, -24                                               
+  $xmm16 = VPSHUFLWZ128ri                      $xmm16, -24
   ; CHECK: $xmm16 = VPSLLDQZ128ri              $xmm16, 1
   $xmm16 = VPSLLDQZ128ri                       $xmm16, 1
   ; CHECK: $xmm16 = VSHUFPDZ128rmi             $xmm16, $rip, 1, $noreg, 0, $noreg, -24
@@ -4022,28 +4022,28 @@ body: |
   $xmm16 = VSHUFPSZ128rri                      $xmm16, $xmm1, -24
   ; CHECK: $xmm16 = VPSADBWZ128rm              $xmm16, $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPSADBWZ128rm                       $xmm16, $rip, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm16 = VPSADBWZ128rr              $xmm16, $xmm1  
-  $xmm16 = VPSADBWZ128rr                       $xmm16, $xmm1                                               
+  ; CHECK: $xmm16 = VPSADBWZ128rr              $xmm16, $xmm1
+  $xmm16 = VPSADBWZ128rr                       $xmm16, $xmm1
   ; CHECK: $xmm16 = VBROADCASTSSZ128rm         $rip, 1, $noreg, 0, $noreg
   $xmm16 = VBROADCASTSSZ128rm                  $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VBROADCASTSSZ128rr         $xmm16
-  $xmm16 = VBROADCASTSSZ128rr                  $xmm16                                                    
+  $xmm16 = VBROADCASTSSZ128rr                  $xmm16
   ; CHECK: $xmm16 = VPBROADCASTBZ128rm         $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPBROADCASTBZ128rm                  $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPBROADCASTBZ128rr         $xmm16
-  $xmm16 = VPBROADCASTBZ128rr                  $xmm16                                                    
+  $xmm16 = VPBROADCASTBZ128rr                  $xmm16
   ; CHECK: $xmm16 = VPBROADCASTDZ128rm         $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPBROADCASTDZ128rm                  $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPBROADCASTDZ128rr         $xmm16
-  $xmm16 = VPBROADCASTDZ128rr                  $xmm16                                                    
+  $xmm16 = VPBROADCASTDZ128rr                  $xmm16
   ; CHECK: $xmm16 = VPBROADCASTQZ128rm         $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPBROADCASTQZ128rm                  $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPBROADCASTQZ128rr         $xmm16
-  $xmm16 = VPBROADCASTQZ128rr                  $xmm16                                                    
+  $xmm16 = VPBROADCASTQZ128rr                  $xmm16
   ; CHECK: $xmm16 = VPBROADCASTWZ128rm         $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPBROADCASTWZ128rm                  $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPBROADCASTWZ128rr         $xmm16
-  $xmm16 = VPBROADCASTWZ128rr                  $xmm16                                                                                            
+  $xmm16 = VPBROADCASTWZ128rr                  $xmm16
   ; CHECK: $xmm16 = VBROADCASTI32X2Z128rm      $rip, 1, $noreg, 0, $noreg
   $xmm16 = VBROADCASTI32X2Z128rm               $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VBROADCASTI32X2Z128rr      $xmm0
@@ -4055,15 +4055,15 @@ body: |
   ; CHECK: $xmm16 = VPABSBZ128rm               $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPABSBZ128rm                        $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPABSBZ128rr               $xmm16
-  $xmm16 = VPABSBZ128rr                        $xmm16                                                    
+  $xmm16 = VPABSBZ128rr                        $xmm16
   ; CHECK: $xmm16 = VPABSDZ128rm               $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPABSDZ128rm                        $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPABSDZ128rr               $xmm16
-  $xmm16 = VPABSDZ128rr                        $xmm16                                                    
+  $xmm16 = VPABSDZ128rr                        $xmm16
   ; CHECK: $xmm16 = VPABSWZ128rm               $rip, 1, $noreg, 0, $noreg
   $xmm16 = VPABSWZ128rm                        $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VPABSWZ128rr               $xmm16
-  $xmm16 = VPABSWZ128rr                        $xmm16                                                    
+  $xmm16 = VPABSWZ128rr                        $xmm16
   ; CHECK: $xmm16 = VPALIGNRZ128rmi            $xmm16, $rdi, 1, $noreg, 0, $noreg, 15
   $xmm16 = VPALIGNRZ128rmi                     $xmm16, $rdi, 1, $noreg, 0, $noreg, 15
   ; CHECK: $xmm16 = VPALIGNRZ128rri            $xmm16, $xmm1, 15
@@ -4092,12 +4092,12 @@ body: |
   $xmm0 = VRNDSCALEPSZ128rmi                   $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
   ; CHECK: $xmm0 = VRNDSCALEPSZ128rri          $xmm0, 31, implicit $mxcsr
   $xmm0 = VRNDSCALEPSZ128rri                   $xmm0, 31, implicit $mxcsr
-    
+
   RET64
 ...
 ---
   # CHECK-LABEL: name: evex_scalar_to_evex_test
-  # CHECK: bb.0:                               
+  # CHECK: bb.0:
 
 name: evex_scalar_to_evex_test
 body: |
@@ -4406,38 +4406,38 @@ body: |
   $xmm16 = VFNMSUB231SSZr                      $xmm16, $xmm1, $xmm2, implicit $mxcsr
   ; CHECK: $xmm16 = VFNMSUB231SSZr_Int         $xmm16, $xmm1, $xmm2, implicit $mxcsr
   $xmm16 = VFNMSUB231SSZr_Int                  $xmm16, $xmm1, $xmm2, implicit $mxcsr
-  ; CHECK: VPEXTRBZmr                          $rdi, 1, $noreg, 0, $noreg, $xmm16, 3       
-  VPEXTRBZmr                                   $rdi, 1, $noreg, 0, $noreg, $xmm16, 3                                
-  ; CHECK: $eax = VPEXTRBZrr                   $xmm16, 1    
-  $eax = VPEXTRBZrr                            $xmm16, 1                                                  
-  ; CHECK: VPEXTRDZmr                          $rdi, 1, $noreg, 0, $noreg, $xmm16, 3      
-  VPEXTRDZmr                                   $rdi, 1, $noreg, 0, $noreg, $xmm16, 3                                
-  ; CHECK: $eax = VPEXTRDZrr                   $xmm16, 1     
-  $eax = VPEXTRDZrr                            $xmm16, 1                                                  
-  ; CHECK: VPEXTRQZmr                          $rdi, 1, $noreg, 0, $noreg, $xmm16, 3       
-  VPEXTRQZmr                                   $rdi, 1, $noreg, 0, $noreg, $xmm16, 3                                
-  ; CHECK: $rax = VPEXTRQZrr                   $xmm16, 1      
-  $rax = VPEXTRQZrr                            $xmm16, 1                                                  
-  ; CHECK: VPEXTRWZmr                          $rdi, 1, $noreg, 0, $noreg,  $xmm16, 3       
-  VPEXTRWZmr                                   $rdi, 1, $noreg, 0, $noreg,  $xmm16, 3                               
-  ; CHECK: $eax = VPEXTRWZrr                   $xmm16, 1      
-  $eax = VPEXTRWZrr                            $xmm16, 1                                                     
-  ; CHECK: $xmm16 = VPINSRBZrm                 $xmm16, $rsi, 1, $noreg, 0, $noreg, 3      
-  $xmm16 = VPINSRBZrm                          $xmm16, $rsi, 1, $noreg, 0, $noreg, 3                                
-  ; CHECK: $xmm16 = VPINSRBZrr                 $xmm16, $edi, 5      
-  $xmm16 = VPINSRBZrr                          $xmm16, $edi, 5                                            
-  ; CHECK: $xmm16 = VPINSRDZrm                 $xmm16, $rsi, 1, $noreg, 0, $noreg, 3      
-  $xmm16 = VPINSRDZrm                          $xmm16, $rsi, 1, $noreg, 0, $noreg, 3                                
-  ; CHECK: $xmm16 = VPINSRDZrr                 $xmm16, $edi, 5            
-  $xmm16 = VPINSRDZrr                          $xmm16, $edi, 5                                            
-  ; CHECK: $xmm16 = VPINSRQZrm                 $xmm16, $rsi, 1, $noreg, 0, $noreg, 3      
-  $xmm16 = VPINSRQZrm                          $xmm16, $rsi, 1, $noreg, 0, $noreg, 3                                
-  ; CHECK: $xmm16 = VPINSRQZrr                 $xmm16, $rdi, 5            
-  $xmm16 = VPINSRQZrr                          $xmm16, $rdi, 5                                            
-  ; CHECK: $xmm16 = VPINSRWZrm                 $xmm16, $rsi, 1, $noreg, 0, $noreg, 3      
-  $xmm16 = VPINSRWZrm                          $xmm16, $rsi, 1, $noreg, 0, $noreg, 3                                
+  ; CHECK: VPEXTRBZmr                          $rdi, 1, $noreg, 0, $noreg, $xmm16, 3
+  VPEXTRBZmr                                   $rdi, 1, $noreg, 0, $noreg, $xmm16, 3
+  ; CHECK: $eax = VPEXTRBZrr                   $xmm16, 1
+  $eax = VPEXTRBZrr                            $xmm16, 1
+  ; CHECK: VPEXTRDZmr                          $rdi, 1, $noreg, 0, $noreg, $xmm16, 3
+  VPEXTRDZmr                                   $rdi, 1, $noreg, 0, $noreg, $xmm16, 3
+  ; CHECK: $eax = VPEXTRDZrr                   $xmm16, 1
+  $eax = VPEXTRDZrr                            $xmm16, 1
+  ; CHECK: VPEXTRQZmr                          $rdi, 1, $noreg, 0, $noreg, $xmm16, 3
+  VPEXTRQZmr                                   $rdi, 1, $noreg, 0, $noreg, $xmm16, 3
+  ; CHECK: $rax = VPEXTRQZrr                   $xmm16, 1
+  $rax = VPEXTRQZrr                            $xmm16, 1
+  ; CHECK: VPEXTRWZmr                          $rdi, 1, $noreg, 0, $noreg,  $xmm16, 3
+  VPEXTRWZmr                                   $rdi, 1, $noreg, 0, $noreg,  $xmm16, 3
+  ; CHECK: $eax = VPEXTRWZrr                   $xmm16, 1
+  $eax = VPEXTRWZrr                            $xmm16, 1
+  ; CHECK: $xmm16 = VPINSRBZrm                 $xmm16, $rsi, 1, $noreg, 0, $noreg, 3
+  $xmm16 = VPINSRBZrm                          $xmm16, $rsi, 1, $noreg, 0, $noreg, 3
+  ; CHECK: $xmm16 = VPINSRBZrr                 $xmm16, $edi, 5
+  $xmm16 = VPINSRBZrr                          $xmm16, $edi, 5
+  ; CHECK: $xmm16 = VPINSRDZrm                 $xmm16, $rsi, 1, $noreg, 0, $noreg, 3
+  $xmm16 = VPINSRDZrm                          $xmm16, $rsi, 1, $noreg, 0, $noreg, 3
+  ; CHECK: $xmm16 = VPINSRDZrr                 $xmm16, $edi, 5
+  $xmm16 = VPINSRDZrr                          $xmm16, $edi, 5
+  ; CHECK: $xmm16 = VPINSRQZrm                 $xmm16, $rsi, 1, $noreg, 0, $noreg, 3
+  $xmm16 = VPINSRQZrm                          $xmm16, $rsi, 1, $noreg, 0, $noreg, 3
+  ; CHECK: $xmm16 = VPINSRQZrr                 $xmm16, $rdi, 5
+  $xmm16 = VPINSRQZrr                          $xmm16, $rdi, 5
+  ; CHECK: $xmm16 = VPINSRWZrm                 $xmm16, $rsi, 1, $noreg, 0, $noreg, 3
+  $xmm16 = VPINSRWZrm                          $xmm16, $rsi, 1, $noreg, 0, $noreg, 3
   ; CHECK: $xmm16 = VPINSRWZrr                 $xmm16, $edi, 5
-  $xmm16 = VPINSRWZrr                          $xmm16, $edi, 5                                               
+  $xmm16 = VPINSRWZrr                          $xmm16, $edi, 5
   ; CHECK: $xmm16 = VSQRTSDZm                  $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
   $xmm16 = VSQRTSDZm                           $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
   ; CHECK: $xmm16 = VSQRTSDZm_Int              $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
@@ -4471,9 +4471,9 @@ body: |
   ; CHECK: $xmm16 = VCVTSD2SSZrr_Int           $xmm16, $xmm16, implicit $mxcsr
   $xmm16 = VCVTSD2SSZrr_Int                    $xmm16, $xmm16, implicit $mxcsr
   ; CHECK: $xmm16 = VCVTSI2SDZrm               $xmm16, $rdi, 1, $noreg, 0, $noreg
-  $xmm16 = VCVTSI2SDZrm                        $xmm16, $rdi, 1, $noreg, 0, $noreg                                   
+  $xmm16 = VCVTSI2SDZrm                        $xmm16, $rdi, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VCVTSI2SDZrm_Int           $xmm16, $rdi, 1, $noreg, 0, $noreg
-  $xmm16 = VCVTSI2SDZrm_Int                    $xmm16, $rdi, 1, $noreg, 0, $noreg                                   
+  $xmm16 = VCVTSI2SDZrm_Int                    $xmm16, $rdi, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VCVTSI2SDZrr               $xmm16, $edi
   $xmm16 = VCVTSI2SDZrr                        $xmm16, $edi
   ; CHECK: $xmm16 = VCVTSI2SDZrr_Int           $xmm16, $edi
@@ -4550,10 +4550,10 @@ body: |
   $edi = VCVTTSS2SIZrr                         $xmm16, implicit $mxcsr
   ; CHECK: $edi = VCVTTSS2SIZrr_Int            $xmm16, implicit $mxcsr
   $edi = VCVTTSS2SIZrr_Int                     $xmm16, implicit $mxcsr
-  ; CHECK: $xmm16 = VMOV64toSDZrr              $rdi    
-  $xmm16 = VMOV64toSDZrr                       $rdi                                                       
+  ; CHECK: $xmm16 = VMOV64toSDZrr              $rdi
+  $xmm16 = VMOV64toSDZrr                       $rdi
   ; CHECK: $xmm16 = VMOVDI2SSZrr               $eax
-  $xmm16 = VMOVDI2SSZrr                        $eax                                                       
+  $xmm16 = VMOVDI2SSZrr                        $eax
   ; CHECK: VMOVSDZmr                           $rdi, 1, $noreg, 0, $noreg, $xmm16
   VMOVSDZmr                                    $rdi, 1, $noreg, 0, $noreg, $xmm16
   ; CHECK: $xmm16 = VMOVSDZrm                  $rip, 1, $noreg, 0, $noreg
@@ -4561,7 +4561,7 @@ body: |
   ; CHECK: $xmm16 = VMOVSDZrm_alt              $rip, 1, $noreg, 0, $noreg
   $xmm16 = VMOVSDZrm_alt                       $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VMOVSDZrr                  $xmm16, $xmm1
-  $xmm16 = VMOVSDZrr                           $xmm16, $xmm1                                                  
+  $xmm16 = VMOVSDZrr                           $xmm16, $xmm1
   ; CHECK: $rax = VMOVSDto64Zrr                $xmm16
   $rax = VMOVSDto64Zrr                         $xmm16
   ; CHECK: VMOVSSZmr                           $rdi, 1, $noreg, 0, $noreg, $xmm16
@@ -4571,19 +4571,19 @@ body: |
   ; CHECK: $xmm16 = VMOVSSZrm_alt              $rip, 1, $noreg, 0, $noreg
   $xmm16 = VMOVSSZrm_alt                       $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VMOVSSZrr                  $xmm16, $xmm1
-  $xmm16 = VMOVSSZrr                           $xmm16, $xmm1                                                  
+  $xmm16 = VMOVSSZrr                           $xmm16, $xmm1
   ; CHECK: $eax = VMOVSS2DIZrr                 $xmm16
   $eax = VMOVSS2DIZrr                          $xmm16
   ; CHECK: $xmm16 = VMOV64toPQIZrr             $rdi
-  $xmm16 = VMOV64toPQIZrr                      $rdi                                                       
+  $xmm16 = VMOV64toPQIZrr                      $rdi
   ; CHECK: $xmm16 = VMOV64toPQIZrm             $rdi, 1, $noreg, 0, $noreg
   $xmm16 = VMOV64toPQIZrm                      $rdi, 1, $noreg, 0, $noreg
-  ; CHECK: $xmm16 = VMOV64toSDZrr              $rdi 
-  $xmm16 = VMOV64toSDZrr                       $rdi                                                       
+  ; CHECK: $xmm16 = VMOV64toSDZrr              $rdi
+  $xmm16 = VMOV64toSDZrr                       $rdi
   ; CHECK: $xmm16 = VMOVDI2PDIZrm              $rip, 1, $noreg, 0, $noreg
   $xmm16 = VMOVDI2PDIZrm                       $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VMOVDI2PDIZrr              $edi
-  $xmm16 = VMOVDI2PDIZrr                       $edi                                                       
+  $xmm16 = VMOVDI2PDIZrr                       $edi
   ; CHECK: $xmm16 = VMOVLHPSZrr                $xmm16, $xmm1
   $xmm16 = VMOVLHPSZrr                         $xmm16, $xmm1
   ; CHECK: $xmm16 = VMOVHLPSZrr                $xmm16, $xmm1
@@ -4591,19 +4591,19 @@ body: |
   ; CHECK: VMOVPDI2DIZmr                       $rdi, 1, $noreg, 0, $noreg, $xmm16
   VMOVPDI2DIZmr                                $rdi, 1, $noreg, 0, $noreg, $xmm16
   ; CHECK: $edi = VMOVPDI2DIZrr                $xmm16
-  $edi = VMOVPDI2DIZrr                         $xmm16                                                     
+  $edi = VMOVPDI2DIZrr                         $xmm16
   ; CHECK: $xmm16 = VMOVPQI2QIZrr              $xmm16
   $xmm16 = VMOVPQI2QIZrr                       $xmm16
   ; CHECK: VMOVPQI2QIZmr                       $rdi, 1, $noreg, 0, $noreg, $xmm16
   VMOVPQI2QIZmr                                $rdi, 1, $noreg, 0, $noreg, $xmm16
   ; CHECK: $rdi = VMOVPQIto64Zrr               $xmm16
-  $rdi = VMOVPQIto64Zrr                        $xmm16                                                     
+  $rdi = VMOVPQIto64Zrr                        $xmm16
   ; CHECK: VMOVPQIto64Zmr                      $rdi, 1, $noreg, 0, $noreg, $xmm16
   VMOVPQIto64Zmr                               $rdi, 1, $noreg, 0, $noreg, $xmm16
   ; CHECK: $xmm16 = VMOVQI2PQIZrm              $rip, 1, $noreg, 0, $noreg
   $xmm16 = VMOVQI2PQIZrm                       $rip, 1, $noreg, 0, $noreg
   ; CHECK: $xmm16 = VMOVZPQILo2PQIZrr          $xmm16
-  $xmm16 = VMOVZPQILo2PQIZrr                   $xmm16                                                     
+  $xmm16 = VMOVZPQILo2PQIZrr                   $xmm16
   ; CHECK: VCOMISDZrm_Int                      $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
   VCOMISDZrm_Int                               $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
   ; CHECK: VCOMISDZrr_Int                      $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
@@ -4668,6 +4668,6 @@ body: |
   $xmm0 = VRNDSCALESSZm_Int                    $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
   ; CHECK: $xmm0 = VRNDSCALESSZr_Int           $xmm0, $xmm1, 31, implicit $mxcsr
   $xmm0 = VRNDSCALESSZr_Int                    $xmm0, $xmm1, 31, implicit $mxcsr
-  
+
   RET64
 ...
-- 
GitLab


From dbee36c523dc3e04bb7d5d9cade392601b86fac4 Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Mon, 11 Dec 2023 12:12:09 +0100
Subject: [PATCH 098/349] [SCEV] Add test for unnecessary umax in BECount (NFC)

---
 .../Analysis/ScalarEvolution/trip-count.ll    | 25 +++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/llvm/test/Analysis/ScalarEvolution/trip-count.ll b/llvm/test/Analysis/ScalarEvolution/trip-count.ll
index 5973d52d05ea..22e49ebdbf4d 100644
--- a/llvm/test/Analysis/ScalarEvolution/trip-count.ll
+++ b/llvm/test/Analysis/ScalarEvolution/trip-count.ll
@@ -123,3 +123,28 @@ loop:
 leave:
   ret void
 }
+
+define void @non_zero_from_loop_guard(i16 %n) {
+; CHECK-LABEL: 'non_zero_from_loop_guard'
+; CHECK-NEXT:  Determining loop execution counts for: @non_zero_from_loop_guard
+; CHECK-NEXT:  Loop %loop: backedge-taken count is (-1 + (1 umax (%n /u 2)))<nsw>
+; CHECK-NEXT:  Loop %loop: constant max backedge-taken count is 32766
+; CHECK-NEXT:  Loop %loop: symbolic max backedge-taken count is (-1 + (1 umax (%n /u 2)))<nsw>
+; CHECK-NEXT:  Loop %loop: Predicated backedge-taken count is (-1 + (1 umax (%n /u 2)))<nsw>
+; CHECK-NEXT:   Predicates:
+; CHECK-NEXT:  Loop %loop: Trip multiple is 1
+;
+entry:
+  %shr = lshr i16 %n, 1
+  %precond = icmp ult i16 %n, 2
+  br i1 %precond, label %exit, label %loop
+
+loop:
+  %iv = phi i16 [ %inc, %loop ], [ 0, %entry ]
+  %inc = add nuw nsw i16 %iv, 1
+  %cmp = icmp ult i16 %inc, %shr
+  br i1 %cmp, label %loop, label %exit
+
+exit:
+  ret void
+}
-- 
GitLab


From 3c1e7fb95e44b6dbec4c0b3c262d91aeb7865d10 Mon Sep 17 00:00:00 2001
From: Paschalis Mpeis <paschalis.mpeis@arm.com>
Date: Mon, 11 Dec 2023 11:20:47 +0000
Subject: [PATCH 099/349] [VFABI] Improve VFABI unit tests (#73907)

The below changes were made:
- test the vector and scalar names, the ISA, and the presence or absence of a
  mask in all tests that is relevant
- test the number of the parameters, the order/types and for masks if present
- replaced methods like `sin` to `foo` to make it more clear that these are not
  existing functions but they are rather tests.
- using mostly `i32` for parameters where it is not relevant, except when the VF
  of elements in explicitly checked, and `ptr` for references.
  Also using `void` for return types.
- all `VFABIParserTest` tests are now listed contiguously in the source.
- Removed duplicate ISA tests
- Added an extra test to clearly show that the mangled name becomes the
  VectorName, when no VectorName is specified.
- Use `VFInfo` for `isMasked`
- Minor code refactoring, cleanup, and improved comments
---
 .../Analysis/VectorFunctionABITest.cpp        | 573 ++++++++++--------
 1 file changed, 319 insertions(+), 254 deletions(-)

diff --git a/llvm/unittests/Analysis/VectorFunctionABITest.cpp b/llvm/unittests/Analysis/VectorFunctionABITest.cpp
index 81c1807cdcaa..201dd1127ef2 100644
--- a/llvm/unittests/Analysis/VectorFunctionABITest.cpp
+++ b/llvm/unittests/Analysis/VectorFunctionABITest.cpp
@@ -1,4 +1,4 @@
-//===------- VectorFunctionABITest.cpp - VFABI Unittests  ---------===//
+//===------- VectorFunctionABITest.cpp - VFABI unit tests  ---------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -6,6 +6,7 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "llvm/ADT/StringRef.h"
 #include "llvm/Analysis/VectorUtils.h"
 #include "llvm/AsmParser/Parser.h"
 #include "llvm/IR/InstIterator.h"
@@ -14,24 +15,31 @@
 using namespace llvm;
 
 namespace {
-// Test fixture needed that holds the veariables needed by the parser.
+/// Perform tests against VFABI Rules. `invokeParser` creates a VFInfo object
+/// and a scalar FunctionType, which are used by tests to check that:
+/// 1. The scalar and vector names are correct.
+/// 2. The number of parameters from the parsed mangled name matches the number
+///    of arguments in the scalar function passed as FunctionType string.
+/// 3. The number of vector parameters and their types match the values
+///    specified in the test.
+///    On masked functions it also checks that the last parameter is a mask (ie,
+///    GlobalPredicate).
+/// 4. The vector function is correctly found to have a mask.
+///
 class VFABIParserTest : public ::testing::Test {
 private:
   // Parser output.
   VFInfo Info;
-  // Reset the data needed for the test.
-  void reset(const StringRef Name, const StringRef IRType) {
+  /// Reset the data needed for the test.
+  void reset(const StringRef ScalarFTyStr) {
     M = parseAssemblyString("declare void @dummy()", Err, Ctx);
     EXPECT_NE(M.get(), nullptr) << "Loading an invalid module.\n "
                                 << Err.getMessage() << "\n";
-    Type *Ty = parseType(IRType, Err, *(M.get()));
-    FTy = dyn_cast<FunctionType>(Ty);
-    EXPECT_NE(FTy, nullptr) << "Invalid function type string: " << IRType
-                            << "\n"
-                            << Err.getMessage() << "\n";
-    F = M->getOrInsertFunction(Name, FTy);
-    EXPECT_NE(F.getCallee(), nullptr)
-        << "The function must be present in the module\n";
+    Type *Ty = parseType(ScalarFTyStr, Err, *(M.get()));
+    ScalarFTy = dyn_cast<FunctionType>(Ty);
+    EXPECT_NE(ScalarFTy, nullptr)
+        << "Invalid function type string: " << ScalarFTyStr << "\n"
+        << Err.getMessage() << "\n";
     // Reset the VFInfo
     Info = VFInfo();
   }
@@ -40,69 +48,48 @@ private:
   LLVMContext Ctx;
   SMDiagnostic Err;
   std::unique_ptr<Module> M;
-  FunctionType *FTy;
-  FunctionCallee F;
+  FunctionType *ScalarFTy = nullptr;
 
 protected:
-  // Referencies to the parser output field.
+  // References to the parser output field.
   ElementCount &VF = Info.Shape.VF;
   VFISAKind &ISA = Info.ISA;
+  /// Parameters for the vectorized function
   SmallVector<VFParameter, 8> &Parameters = Info.Shape.Parameters;
   std::string &ScalarName = Info.ScalarName;
   std::string &VectorName = Info.VectorName;
-  // Invoke the parser. We need to make sure that a function exist in
-  // the module because the parser fails if such function don't
-  // exists. Every time this method is invoked the state of the test
-  // is reset.
-  //
-  // \p MangledName -> the string the parser has to demangle.
-  //
-  // \p VectorName -> optional vector name that the method needs to
-  // use to create the function in the module if it differs from the
-  // standard mangled name.
-  //
-  // \p IRType -> FunctionType string to be used for the signature of
-  // the vector function.  The correct signature is needed by the
-  // parser only for scalable functions. For the sake of testing, the
-  // generic fixed-length case can use as signature `void()`.
-  //
+
+  /// Invoke the parser. Every time this method is invoked the state of the test
+  /// is reset.
+  ///
+  /// \p MangledName string the parser has to demangle.
+  ///
+  /// \p ScalarFTyStr FunctionType string to get the signature of the scalar
+  /// function, which is used by `tryDemangleForVFABI` to check for the number
+  /// of arguments on scalable vectors, and by `matchParameters` to perform some
+  /// additional checking in the tests in this file.
   bool invokeParser(const StringRef MangledName,
-                    const StringRef ScalarName = "",
-                    const StringRef IRType = "void()") {
-    StringRef Name = MangledName;
-    if (!ScalarName.empty())
-      Name = ScalarName;
-    // Reset the VFInfo and the Module to be able to invoke
-    // `invokeParser` multiple times in the same test.
-    reset(Name, IRType);
-
-    // Fake the arguments to the CallInst.
-    SmallVector<Value *> Args;
-    for (Type *ParamTy : FTy->params()) {
-      Args.push_back(Constant::getNullValue(ParamTy->getScalarType()));
-    }
-    std::unique_ptr<CallInst> CI(CallInst::Create(F, Args));
-    const auto OptInfo =
-        VFABI::tryDemangleForVFABI(MangledName, CI->getFunctionType());
-    if (OptInfo) {
+                    const StringRef ScalarFTyStr = "void()") {
+    // Reset the VFInfo to be able to call `invokeParser` multiple times in
+    // the same test.
+    reset(ScalarFTyStr);
+
+    const auto OptInfo = VFABI::tryDemangleForVFABI(MangledName, ScalarFTy);
+    if (OptInfo)
       Info = *OptInfo;
-      return true;
-    }
 
-    return false;
+    return OptInfo.has_value();
   }
 
-  // Checks that 1. the last Parameter in the Shape is of type
-  // VFParamKind::GlobalPredicate and 2. it is the only one of such
-  // type.
-  bool IsMasked() const {
-    const auto NGlobalPreds =
-        std::count_if(Info.Shape.Parameters.begin(),
-                      Info.Shape.Parameters.end(), [](const VFParameter PK) {
-                        return PK.ParamKind == VFParamKind::GlobalPredicate;
-                      });
-    return NGlobalPreds == 1 && Info.Shape.Parameters.back().ParamKind ==
-                                    VFParamKind::GlobalPredicate;
+  /// Returns whether the parsed function contains a mask.
+  bool isMasked() const { return Info.isMasked(); }
+
+  /// Check if the number of vectorized parameters matches the scalar ones. This
+  /// requires a correct scalar FunctionType string to be fed to the
+  /// 'invokeParser'. Mask parameters that are only required by the vector
+  /// function call are ignored.
+  bool matchParametersNum() {
+    return (Parameters.size() - isMasked()) == ScalarFTy->getNumParams();
   }
 };
 } // unnamed namespace
@@ -132,47 +119,74 @@ TEST_F(VFABIParserTest, OnlyValidNames) {
   EXPECT_FALSE(invokeParser("_ZGVnN2v_"));
   // Missing _ separator.
   EXPECT_FALSE(invokeParser("_ZGVnN2vfoo"));
-  // Missing <vectorname>. Using `fakename` because the string being
-  // parsed is not a valid function name that `invokeParser` can add.
-  EXPECT_FALSE(invokeParser("_ZGVnN2v_foo()", "fakename"));
-  // Unterminated name. Using `fakename` because the string being
-  // parsed is not a valid function name that `invokeParser` can add.
-  EXPECT_FALSE(invokeParser("_ZGVnN2v_foo(bar", "fakename"));
+  // Missing <vectorname>.
+  EXPECT_FALSE(invokeParser("_ZGVnN2v_foo()"));
+  // Unterminated name.
+  EXPECT_FALSE(invokeParser("_ZGVnN2v_foo(bar"));
 }
 
 TEST_F(VFABIParserTest, ParamListParsing) {
-  EXPECT_TRUE(invokeParser("_ZGVnN2vl16Ls32R3l_foo"));
+  EXPECT_TRUE(
+      invokeParser("_ZGVnN2vl16Ls32R3l_foo", "void(i32, i32, i32, ptr, i32)"));
+  EXPECT_EQ(ISA, VFISAKind::AdvancedSIMD);
+  EXPECT_EQ(false, isMasked());
+  EXPECT_TRUE(matchParametersNum()) << "Different number of scalar parameters";
   EXPECT_EQ(Parameters.size(), (unsigned)5);
   EXPECT_EQ(Parameters[0], VFParameter({0, VFParamKind::Vector, 0}));
   EXPECT_EQ(Parameters[1], VFParameter({1, VFParamKind::OMP_Linear, 16}));
   EXPECT_EQ(Parameters[2], VFParameter({2, VFParamKind::OMP_LinearValPos, 32}));
   EXPECT_EQ(Parameters[3], VFParameter({3, VFParamKind::OMP_LinearRef, 3}));
   EXPECT_EQ(Parameters[4], VFParameter({4, VFParamKind::OMP_Linear, 1}));
+  EXPECT_EQ(ScalarName, "foo");
+  EXPECT_EQ(VectorName, "_ZGVnN2vl16Ls32R3l_foo");
 }
 
 TEST_F(VFABIParserTest, ScalarNameAndVectorName_01) {
-  EXPECT_TRUE(invokeParser("_ZGVnM2v_sin"));
-  EXPECT_EQ(ScalarName, "sin");
-  EXPECT_EQ(VectorName, "_ZGVnM2v_sin");
+  EXPECT_TRUE(invokeParser("_ZGVnM2v_foo(vector_foo)", "void(i32)"));
+  EXPECT_EQ(ISA, VFISAKind::AdvancedSIMD);
+  EXPECT_EQ(true, isMasked());
+  EXPECT_TRUE(matchParametersNum()) << "Different number of scalar parameters";
+  EXPECT_EQ(ScalarName, "foo");
+  EXPECT_EQ(VectorName, "vector_foo");
 }
 
 TEST_F(VFABIParserTest, ScalarNameAndVectorName_02) {
-  EXPECT_TRUE(invokeParser("_ZGVnM2v_sin(UserFunc)", "UserFunc"));
-  EXPECT_EQ(ScalarName, "sin");
-  EXPECT_EQ(VectorName, "UserFunc");
+  EXPECT_TRUE(invokeParser("_ZGVnM2v_foo(vector_foo)", "void(i32)"));
+  EXPECT_EQ(ISA, VFISAKind::AdvancedSIMD);
+  EXPECT_EQ(true, isMasked());
+  EXPECT_TRUE(matchParametersNum()) << "Different number of scalar parameters";
+  EXPECT_EQ(ScalarName, "foo");
+  EXPECT_EQ(VectorName, "vector_foo");
 }
 
 TEST_F(VFABIParserTest, ScalarNameAndVectorName_03) {
-  EXPECT_TRUE(invokeParser("_ZGVnM2v___sin_sin_sin"));
-  EXPECT_EQ(ScalarName, "__sin_sin_sin");
-  EXPECT_EQ(VectorName, "_ZGVnM2v___sin_sin_sin");
+  EXPECT_TRUE(
+      invokeParser("_ZGVnM2v___foo_bar_abc(fooBarAbcVec)", "void(i32)"));
+  EXPECT_EQ(ISA, VFISAKind::AdvancedSIMD);
+  EXPECT_EQ(true, isMasked());
+  EXPECT_TRUE(matchParametersNum()) << "Different number of scalar parameters";
+  EXPECT_EQ(ScalarName, "__foo_bar_abc");
+  EXPECT_EQ(VectorName, "fooBarAbcVec");
+}
+
+TEST_F(VFABIParserTest, ScalarNameOnly) {
+  EXPECT_TRUE(invokeParser("_ZGVnM2v___foo_bar_abc"));
+  EXPECT_EQ(ISA, VFISAKind::AdvancedSIMD);
+  EXPECT_EQ(true, isMasked());
+  EXPECT_EQ(ScalarName, "__foo_bar_abc");
+  // no vector name specified (as it's optional), so it should have the entire
+  // mangled name.
+  EXPECT_EQ(VectorName, "_ZGVnM2v___foo_bar_abc");
 }
 
 TEST_F(VFABIParserTest, Parse) {
-  EXPECT_TRUE(invokeParser("_ZGVnN2vls2Ls27Us4Rs5l1L10U100R1000_sin"));
-  EXPECT_EQ(VF, ElementCount::getFixed(2));
-  EXPECT_FALSE(IsMasked());
+  EXPECT_TRUE(
+      invokeParser("_ZGVnN2vls2Ls27Us4Rs5l1L10U100R1000_foo",
+                   "void(i32, i32, i32, i32, ptr, i32, i32, i32, ptr)"));
   EXPECT_EQ(ISA, VFISAKind::AdvancedSIMD);
+  EXPECT_FALSE(isMasked());
+  EXPECT_TRUE(matchParametersNum()) << "Different number of scalar parameters";
+  EXPECT_EQ(VF, ElementCount::getFixed(2));
   EXPECT_EQ(Parameters.size(), (unsigned)9);
   EXPECT_EQ(Parameters[0], VFParameter({0, VFParamKind::Vector, 0}));
   EXPECT_EQ(Parameters[1], VFParameter({1, VFParamKind::OMP_LinearPos, 2}));
@@ -183,75 +197,90 @@ TEST_F(VFABIParserTest, Parse) {
   EXPECT_EQ(Parameters[6], VFParameter({6, VFParamKind::OMP_LinearVal, 10}));
   EXPECT_EQ(Parameters[7], VFParameter({7, VFParamKind::OMP_LinearUVal, 100}));
   EXPECT_EQ(Parameters[8], VFParameter({8, VFParamKind::OMP_LinearRef, 1000}));
-  EXPECT_EQ(ScalarName, "sin");
-  EXPECT_EQ(VectorName, "_ZGVnN2vls2Ls27Us4Rs5l1L10U100R1000_sin");
+  EXPECT_EQ(ScalarName, "foo");
+  EXPECT_EQ(VectorName, "_ZGVnN2vls2Ls27Us4Rs5l1L10U100R1000_foo");
 }
 
 TEST_F(VFABIParserTest, ParseVectorName) {
-  EXPECT_TRUE(invokeParser("_ZGVnN2v_sin(my_v_sin)", "my_v_sin"));
-  EXPECT_EQ(VF, ElementCount::getFixed(2));
-  EXPECT_FALSE(IsMasked());
+  EXPECT_TRUE(invokeParser("_ZGVnN2v_foo(vector_foo)", "void(i32)"));
   EXPECT_EQ(ISA, VFISAKind::AdvancedSIMD);
+  EXPECT_FALSE(isMasked());
+  EXPECT_TRUE(matchParametersNum()) << "Different number of scalar parameters";
+  EXPECT_EQ(VF, ElementCount::getFixed(2));
   EXPECT_EQ(Parameters.size(), (unsigned)1);
   EXPECT_EQ(Parameters[0], VFParameter({0, VFParamKind::Vector, 0}));
-  EXPECT_EQ(ScalarName, "sin");
-  EXPECT_EQ(VectorName, "my_v_sin");
+  EXPECT_EQ(ScalarName, "foo");
+  EXPECT_EQ(VectorName, "vector_foo");
 }
 
 TEST_F(VFABIParserTest, LinearWithCompileTimeNegativeStep) {
-  EXPECT_TRUE(invokeParser("_ZGVnN2ln1Ln10Un100Rn1000_sin"));
-  EXPECT_EQ(VF, ElementCount::getFixed(2));
-  EXPECT_FALSE(IsMasked());
+  EXPECT_TRUE(invokeParser("_ZGVnN2ln1Ln10Un100Rn1000_foo(vector_foo)",
+                           "void(i32, i32, i32, ptr)"));
   EXPECT_EQ(ISA, VFISAKind::AdvancedSIMD);
+  EXPECT_FALSE(isMasked());
+  EXPECT_TRUE(matchParametersNum()) << "Different number of scalar parameters";
+  EXPECT_EQ(VF, ElementCount::getFixed(2));
   EXPECT_EQ(Parameters.size(), (unsigned)4);
   EXPECT_EQ(Parameters[0], VFParameter({0, VFParamKind::OMP_Linear, -1}));
   EXPECT_EQ(Parameters[1], VFParameter({1, VFParamKind::OMP_LinearVal, -10}));
   EXPECT_EQ(Parameters[2], VFParameter({2, VFParamKind::OMP_LinearUVal, -100}));
   EXPECT_EQ(Parameters[3], VFParameter({3, VFParamKind::OMP_LinearRef, -1000}));
-  EXPECT_EQ(ScalarName, "sin");
-  EXPECT_EQ(VectorName, "_ZGVnN2ln1Ln10Un100Rn1000_sin");
+  EXPECT_EQ(ScalarName, "foo");
+  EXPECT_EQ(VectorName, "vector_foo");
 }
 
 TEST_F(VFABIParserTest, ParseScalableSVE) {
-  EXPECT_TRUE(invokeParser("_ZGVsMxv_sin(custom_vg)", "sin", "i32(i32)"));
-  EXPECT_EQ(VF, ElementCount::getScalable(4));
-  EXPECT_TRUE(IsMasked());
+  EXPECT_TRUE(invokeParser("_ZGVsMxv_foo(vector_foo)", "void(i32)"));
   EXPECT_EQ(ISA, VFISAKind::SVE);
-  EXPECT_EQ(ScalarName, "sin");
-  EXPECT_EQ(VectorName, "custom_vg");
+  EXPECT_TRUE(isMasked());
+  EXPECT_TRUE(matchParametersNum()) << "Different number of scalar parameters";
+  EXPECT_EQ(VF, ElementCount::getScalable(4));
+  EXPECT_EQ(Parameters.size(), (unsigned)2);
+  EXPECT_EQ(Parameters[0], VFParameter({0, VFParamKind::Vector}));
+  EXPECT_EQ(Parameters[1], VFParameter({1, VFParamKind::GlobalPredicate}));
+  EXPECT_EQ(ScalarName, "foo");
+  EXPECT_EQ(VectorName, "vector_foo");
 }
 
 TEST_F(VFABIParserTest, ParseFixedWidthSVE) {
-  EXPECT_TRUE(invokeParser("_ZGVsM2v_sin"));
-  EXPECT_EQ(VF, ElementCount::getFixed(2));
-  EXPECT_TRUE(IsMasked());
+  EXPECT_TRUE(invokeParser("_ZGVsM2v_foo(vector_foo)", "void(i32)"));
   EXPECT_EQ(ISA, VFISAKind::SVE);
-  EXPECT_EQ(ScalarName, "sin");
-  EXPECT_EQ(VectorName, "_ZGVsM2v_sin");
+  EXPECT_TRUE(isMasked());
+  EXPECT_TRUE(matchParametersNum()) << "Different number of scalar parameters";
+  EXPECT_EQ(VF, ElementCount::getFixed(2));
+  EXPECT_EQ(Parameters.size(), (unsigned)2);
+  EXPECT_EQ(Parameters[0], VFParameter({0, VFParamKind::Vector}));
+  EXPECT_EQ(Parameters[1], VFParameter({1, VFParamKind::GlobalPredicate}));
+  EXPECT_EQ(ScalarName, "foo");
+  EXPECT_EQ(VectorName, "vector_foo");
 }
 
 TEST_F(VFABIParserTest, NotAVectorFunctionABIName) {
   // Vector names should start with `_ZGV`.
-  EXPECT_FALSE(invokeParser("ZGVnN2v_sin"));
+  EXPECT_FALSE(invokeParser("ZGVnN2v_foo"));
 }
 
 TEST_F(VFABIParserTest, LinearWithRuntimeStep) {
-  EXPECT_FALSE(invokeParser("_ZGVnN2ls_sin"))
+  EXPECT_FALSE(invokeParser("_ZGVnN2ls_foo"))
       << "A number should be present after \"ls\".";
-  EXPECT_TRUE(invokeParser("_ZGVnN2ls2_sin"));
-  EXPECT_FALSE(invokeParser("_ZGVnN2Rs_sin"))
+  EXPECT_TRUE(invokeParser("_ZGVnN2ls2_foo"));
+  EXPECT_FALSE(invokeParser("_ZGVnN2Rs_foo"))
       << "A number should be present after \"Rs\".";
-  EXPECT_TRUE(invokeParser("_ZGVnN2Rs4_sin"));
-  EXPECT_FALSE(invokeParser("_ZGVnN2Ls_sin"))
+  EXPECT_TRUE(invokeParser("_ZGVnN2Rs4_foo"));
+  EXPECT_FALSE(invokeParser("_ZGVnN2Ls_foo"))
       << "A number should be present after \"Ls\".";
-  EXPECT_TRUE(invokeParser("_ZGVnN2Ls6_sin"));
-  EXPECT_FALSE(invokeParser("_ZGVnN2Us_sin"))
+  EXPECT_TRUE(invokeParser("_ZGVnN2Ls6_foo"));
+  EXPECT_FALSE(invokeParser("_ZGVnN2Us_foo"))
       << "A number should be present after \"Us\".";
-  EXPECT_TRUE(invokeParser("_ZGVnN2Us8_sin"));
+  EXPECT_TRUE(invokeParser("_ZGVnN2Us8_foo"));
 }
 
 TEST_F(VFABIParserTest, LinearWithoutCompileTime) {
-  EXPECT_TRUE(invokeParser("_ZGVnN3lLRUlnLnRnUn_sin"));
+  EXPECT_TRUE(invokeParser("_ZGVnN3lLRUlnLnRnUn_foo(vector_foo)",
+                           "void(i32, i32, ptr, i32, i32, i32, ptr, i32)"));
+  EXPECT_EQ(ISA, VFISAKind::AdvancedSIMD);
+  EXPECT_FALSE(isMasked());
+  EXPECT_TRUE(matchParametersNum()) << "Different number of scalar parameters";
   EXPECT_EQ(Parameters.size(), (unsigned)8);
   EXPECT_EQ(Parameters[0], VFParameter({0, VFParamKind::OMP_Linear, 1}));
   EXPECT_EQ(Parameters[1], VFParameter({1, VFParamKind::OMP_LinearVal, 1}));
@@ -261,80 +290,73 @@ TEST_F(VFABIParserTest, LinearWithoutCompileTime) {
   EXPECT_EQ(Parameters[5], VFParameter({5, VFParamKind::OMP_LinearVal, -1}));
   EXPECT_EQ(Parameters[6], VFParameter({6, VFParamKind::OMP_LinearRef, -1}));
   EXPECT_EQ(Parameters[7], VFParameter({7, VFParamKind::OMP_LinearUVal, -1}));
-}
-
-TEST_F(VFABIParserTest, ISA) {
-  EXPECT_TRUE(invokeParser("_ZGVqN2v_sin"));
-  EXPECT_EQ(ISA, VFISAKind::Unknown);
-
-  EXPECT_TRUE(invokeParser("_ZGVnN2v_sin"));
-  EXPECT_EQ(ISA, VFISAKind::AdvancedSIMD);
-
-  EXPECT_TRUE(invokeParser("_ZGVsN2v_sin"));
-  EXPECT_EQ(ISA, VFISAKind::SVE);
-
-  EXPECT_TRUE(invokeParser("_ZGVbN2v_sin"));
-  EXPECT_EQ(ISA, VFISAKind::SSE);
-
-  EXPECT_TRUE(invokeParser("_ZGVcN2v_sin"));
-  EXPECT_EQ(ISA, VFISAKind::AVX);
-
-  EXPECT_TRUE(invokeParser("_ZGVdN2v_sin"));
-  EXPECT_EQ(ISA, VFISAKind::AVX2);
-
-  EXPECT_TRUE(invokeParser("_ZGVeN2v_sin"));
-  EXPECT_EQ(ISA, VFISAKind::AVX512);
+  EXPECT_EQ(ScalarName, "foo");
+  EXPECT_EQ(VectorName, "vector_foo");
 }
 
 TEST_F(VFABIParserTest, LLVM_ISA) {
-  EXPECT_FALSE(invokeParser("_ZGV_LLVM_N2v_sin"));
-  EXPECT_TRUE(invokeParser("_ZGV_LLVM_N2v_sin_(vector_name)", "vector_name"));
+  EXPECT_FALSE(invokeParser("_ZGV_LLVM_N2v_foo"));
+  EXPECT_TRUE(invokeParser("_ZGV_LLVM_N2v_foo(vector_foo)", "void(i32)"));
   EXPECT_EQ(ISA, VFISAKind::LLVM);
+  EXPECT_FALSE(isMasked());
+  EXPECT_TRUE(matchParametersNum()) << "Different number of scalar parameters";
+  EXPECT_EQ(Parameters.size(), (unsigned)1);
+  EXPECT_EQ(Parameters[0], VFParameter({0, VFParamKind::Vector}));
+  EXPECT_EQ(ScalarName, "foo");
+  EXPECT_EQ(VectorName, "vector_foo");
 }
 
 TEST_F(VFABIParserTest, InvalidMask) {
-  EXPECT_FALSE(invokeParser("_ZGVsK2v_sin"));
+  EXPECT_FALSE(invokeParser("_ZGVsK2v_foo"));
 }
 
 TEST_F(VFABIParserTest, InvalidParameter) {
-  EXPECT_FALSE(invokeParser("_ZGVsM2vX_sin"));
+  EXPECT_FALSE(invokeParser("_ZGVsM2vX_foo"));
 }
 
 TEST_F(VFABIParserTest, Align) {
-  EXPECT_TRUE(invokeParser("_ZGVsN2l2a2_sin"));
+  EXPECT_TRUE(invokeParser("_ZGVsN2l2a2_foo(vector_foo)", "void(i32)"));
+  EXPECT_EQ(ISA, VFISAKind::SVE);
+  EXPECT_FALSE(isMasked());
+  EXPECT_TRUE(matchParametersNum()) << "Different number of scalar parameters";
   EXPECT_EQ(Parameters.size(), (unsigned)1);
   EXPECT_EQ(Parameters[0].Alignment, Align(2));
+  EXPECT_EQ(ScalarName, "foo");
+  EXPECT_EQ(VectorName, "vector_foo");
 
   // Missing alignment value.
-  EXPECT_FALSE(invokeParser("_ZGVsM2l2a_sin"));
+  EXPECT_FALSE(invokeParser("_ZGVsM2l2a_foo"));
   // Invalid alignment token "x".
-  EXPECT_FALSE(invokeParser("_ZGVsM2l2ax_sin"));
+  EXPECT_FALSE(invokeParser("_ZGVsM2l2ax_foo"));
   // Alignment MUST be associated to a paramater.
-  EXPECT_FALSE(invokeParser("_ZGVsM2a2_sin"));
+  EXPECT_FALSE(invokeParser("_ZGVsM2a2_foo"));
   // Alignment must be a power of 2.
-  EXPECT_FALSE(invokeParser("_ZGVsN2l2a0_sin"));
-  EXPECT_TRUE(invokeParser("_ZGVsN2l2a1_sin"));
-  EXPECT_FALSE(invokeParser("_ZGVsN2l2a3_sin"));
-  EXPECT_FALSE(invokeParser("_ZGVsN2l2a6_sin"));
+  EXPECT_FALSE(invokeParser("_ZGVsN2l2a0_foo"));
+  EXPECT_TRUE(invokeParser("_ZGVsN2l2a1_foo"));
+  EXPECT_FALSE(invokeParser("_ZGVsN2l2a3_foo"));
+  EXPECT_FALSE(invokeParser("_ZGVsN2l2a6_foo"));
 }
 
 TEST_F(VFABIParserTest, ParseUniform) {
-  EXPECT_TRUE(invokeParser("_ZGVnN2u_sin"));
-  EXPECT_EQ(VF, ElementCount::getFixed(2));
-  EXPECT_FALSE(IsMasked());
+  EXPECT_TRUE(invokeParser("_ZGVnN2u_foo(vector_foo)", "void(i32)"));
   EXPECT_EQ(ISA, VFISAKind::AdvancedSIMD);
+  EXPECT_FALSE(isMasked());
+  EXPECT_TRUE(matchParametersNum()) << "Different number of scalar parameters";
+  EXPECT_EQ(VF, ElementCount::getFixed(2));
   EXPECT_EQ(Parameters.size(), (unsigned)1);
   EXPECT_EQ(Parameters[0], VFParameter({0, VFParamKind::OMP_Uniform, 0}));
-  EXPECT_EQ(ScalarName, "sin");
-  EXPECT_EQ(VectorName, "_ZGVnN2u_sin");
+  EXPECT_EQ(ScalarName, "foo");
+  EXPECT_EQ(VectorName, "vector_foo");
 
   // Uniform doesn't expect extra data.
-  EXPECT_FALSE(invokeParser("_ZGVnN2u0_sin"));
+  EXPECT_FALSE(invokeParser("_ZGVnN2u0_foo"));
 }
 
 TEST_F(VFABIParserTest, ISAIndependentMangling) {
   // This test makes sure that the mangling of the parameters in
   // independent on the <isa> token.
+  const StringRef IRTy =
+      "void(i32, i32, i32, i32, ptr, i32, i32, i32, i32, i32)";
   const SmallVector<VFParameter, 8> ExpectedParams = {
       VFParameter({0, VFParamKind::Vector, 0}),
       VFParameter({1, VFParamKind::OMP_LinearPos, 2}),
@@ -351,61 +373,63 @@ TEST_F(VFABIParserTest, ISAIndependentMangling) {
 #define __COMMON_CHECKS                                                        \
   do {                                                                         \
     EXPECT_EQ(VF, ElementCount::getFixed(2));                                  \
-    EXPECT_FALSE(IsMasked());                                                  \
+    EXPECT_FALSE(isMasked());                                                  \
+    EXPECT_TRUE(matchParametersNum())                                          \
+        << "Different number of scalar parameters";                            \
     EXPECT_EQ(Parameters.size(), (unsigned)10);                                \
     EXPECT_EQ(Parameters, ExpectedParams);                                     \
-    EXPECT_EQ(ScalarName, "sin");                                              \
+    EXPECT_EQ(ScalarName, "foo");                                              \
+    EXPECT_EQ(VectorName, "vector_foo");                                       \
   } while (0)
 
   // Advanced SIMD: <isa> = "n"
-  EXPECT_TRUE(invokeParser("_ZGVnN2vls2Ls27Us4Rs5l1L10U100R1000u_sin"));
+  EXPECT_TRUE(invokeParser(
+      "_ZGVnN2vls2Ls27Us4Rs5l1L10U100R1000u_foo(vector_foo)", IRTy));
   EXPECT_EQ(ISA, VFISAKind::AdvancedSIMD);
   __COMMON_CHECKS;
-  EXPECT_EQ(VectorName, "_ZGVnN2vls2Ls27Us4Rs5l1L10U100R1000u_sin");
 
   // SVE: <isa> = "s"
-  EXPECT_TRUE(invokeParser("_ZGVsN2vls2Ls27Us4Rs5l1L10U100R1000u_sin"));
+  EXPECT_TRUE(invokeParser(
+      "_ZGVsN2vls2Ls27Us4Rs5l1L10U100R1000u_foo(vector_foo)", IRTy));
   EXPECT_EQ(ISA, VFISAKind::SVE);
   __COMMON_CHECKS;
-  EXPECT_EQ(VectorName, "_ZGVsN2vls2Ls27Us4Rs5l1L10U100R1000u_sin");
 
   // SSE: <isa> = "b"
-  EXPECT_TRUE(invokeParser("_ZGVbN2vls2Ls27Us4Rs5l1L10U100R1000u_sin"));
+  EXPECT_TRUE(invokeParser(
+      "_ZGVbN2vls2Ls27Us4Rs5l1L10U100R1000u_foo(vector_foo)", IRTy));
   EXPECT_EQ(ISA, VFISAKind::SSE);
   __COMMON_CHECKS;
-  EXPECT_EQ(VectorName, "_ZGVbN2vls2Ls27Us4Rs5l1L10U100R1000u_sin");
 
   // AVX: <isa> = "c"
-  EXPECT_TRUE(invokeParser("_ZGVcN2vls2Ls27Us4Rs5l1L10U100R1000u_sin"));
+  EXPECT_TRUE(invokeParser(
+      "_ZGVcN2vls2Ls27Us4Rs5l1L10U100R1000u_foo(vector_foo)", IRTy));
   EXPECT_EQ(ISA, VFISAKind::AVX);
   __COMMON_CHECKS;
-  EXPECT_EQ(VectorName, "_ZGVcN2vls2Ls27Us4Rs5l1L10U100R1000u_sin");
 
   // AVX2: <isa> = "d"
-  EXPECT_TRUE(invokeParser("_ZGVdN2vls2Ls27Us4Rs5l1L10U100R1000u_sin"));
+  EXPECT_TRUE(invokeParser(
+      "_ZGVdN2vls2Ls27Us4Rs5l1L10U100R1000u_foo(vector_foo)", IRTy));
   EXPECT_EQ(ISA, VFISAKind::AVX2);
   __COMMON_CHECKS;
-  EXPECT_EQ(VectorName, "_ZGVdN2vls2Ls27Us4Rs5l1L10U100R1000u_sin");
 
   // AVX512: <isa> = "e"
-  EXPECT_TRUE(invokeParser("_ZGVeN2vls2Ls27Us4Rs5l1L10U100R1000u_sin"));
+  EXPECT_TRUE(invokeParser(
+      "_ZGVeN2vls2Ls27Us4Rs5l1L10U100R1000u_foo(vector_foo)", IRTy));
   EXPECT_EQ(ISA, VFISAKind::AVX512);
   __COMMON_CHECKS;
-  EXPECT_EQ(VectorName, "_ZGVeN2vls2Ls27Us4Rs5l1L10U100R1000u_sin");
 
   // LLVM: <isa> = "_LLVM_" internal vector function.
   EXPECT_TRUE(invokeParser(
-      "_ZGV_LLVM_N2vls2Ls27Us4Rs5l1L10U100R1000u_sin(vectorf)", "vectorf"));
+      "_ZGV_LLVM_N2vls2Ls27Us4Rs5l1L10U100R1000u_foo(vector_foo)", IRTy));
   EXPECT_EQ(ISA, VFISAKind::LLVM);
   __COMMON_CHECKS;
-  EXPECT_EQ(VectorName, "vectorf");
 
   // Unknown ISA (randomly using "q"). This test will need update if
   // some targets decide to use "q" as their ISA token.
-  EXPECT_TRUE(invokeParser("_ZGVqN2vls2Ls27Us4Rs5l1L10U100R1000u_sin"));
+  EXPECT_TRUE(invokeParser(
+      "_ZGVqN2vls2Ls27Us4Rs5l1L10U100R1000u_foo(vector_foo)", IRTy));
   EXPECT_EQ(ISA, VFISAKind::Unknown);
   __COMMON_CHECKS;
-  EXPECT_EQ(VectorName, "_ZGVqN2vls2Ls27Us4Rs5l1L10U100R1000u_sin");
 
 #undef __COMMON_CHECKS
 }
@@ -423,108 +447,167 @@ TEST_F(VFABIParserTest, MissingVectorNameTermination) {
 }
 
 TEST_F(VFABIParserTest, ParseMaskingNEON) {
-  EXPECT_TRUE(invokeParser("_ZGVnM2v_sin"));
-  EXPECT_EQ(VF, ElementCount::getFixed(2));
-  EXPECT_TRUE(IsMasked());
+  EXPECT_TRUE(invokeParser("_ZGVnM2v_foo(vector_foo)", "void(i32)"));
   EXPECT_EQ(ISA, VFISAKind::AdvancedSIMD);
+  EXPECT_TRUE(isMasked());
+  EXPECT_TRUE(matchParametersNum()) << "Different number of scalar parameters";
+  EXPECT_EQ(VF, ElementCount::getFixed(2));
   EXPECT_EQ(Parameters.size(), (unsigned)2);
   EXPECT_EQ(Parameters[0], VFParameter({0, VFParamKind::Vector}));
   EXPECT_EQ(Parameters[1], VFParameter({1, VFParamKind::GlobalPredicate}));
-  EXPECT_EQ(ScalarName, "sin");
+  EXPECT_EQ(ScalarName, "foo");
+  EXPECT_EQ(VectorName, "vector_foo");
 }
 
 TEST_F(VFABIParserTest, ParseMaskingSVE) {
-  EXPECT_TRUE(invokeParser("_ZGVsM2v_sin"));
-  EXPECT_EQ(VF, ElementCount::getFixed(2));
-  EXPECT_TRUE(IsMasked());
+  EXPECT_TRUE(invokeParser("_ZGVsM2v_foo(vector_foo)", "void(i32)"));
   EXPECT_EQ(ISA, VFISAKind::SVE);
+  EXPECT_TRUE(isMasked());
+  EXPECT_TRUE(matchParametersNum()) << "Different number of scalar parameters";
+  EXPECT_EQ(VF, ElementCount::getFixed(2));
   EXPECT_EQ(Parameters.size(), (unsigned)2);
   EXPECT_EQ(Parameters[0], VFParameter({0, VFParamKind::Vector}));
   EXPECT_EQ(Parameters[1], VFParameter({1, VFParamKind::GlobalPredicate}));
-  EXPECT_EQ(ScalarName, "sin");
+  EXPECT_EQ(ScalarName, "foo");
+  EXPECT_EQ(VectorName, "vector_foo");
 }
 
 TEST_F(VFABIParserTest, ParseMaskingSSE) {
-  EXPECT_TRUE(invokeParser("_ZGVbM2v_sin"));
-  EXPECT_EQ(VF, ElementCount::getFixed(2));
-  EXPECT_TRUE(IsMasked());
+  EXPECT_TRUE(invokeParser("_ZGVbM2v_foo(vector_foo)", "void(i32)"));
   EXPECT_EQ(ISA, VFISAKind::SSE);
+  EXPECT_TRUE(isMasked());
+  EXPECT_TRUE(matchParametersNum()) << "Different number of scalar parameters";
+  EXPECT_EQ(VF, ElementCount::getFixed(2));
   EXPECT_EQ(Parameters.size(), (unsigned)2);
   EXPECT_EQ(Parameters[0], VFParameter({0, VFParamKind::Vector}));
   EXPECT_EQ(Parameters[1], VFParameter({1, VFParamKind::GlobalPredicate}));
-  EXPECT_EQ(ScalarName, "sin");
+  EXPECT_EQ(ScalarName, "foo");
+  EXPECT_EQ(VectorName, "vector_foo");
 }
 
 TEST_F(VFABIParserTest, ParseMaskingAVX) {
-  EXPECT_TRUE(invokeParser("_ZGVcM2v_sin"));
-  EXPECT_EQ(VF, ElementCount::getFixed(2));
-  EXPECT_TRUE(IsMasked());
+  EXPECT_TRUE(invokeParser("_ZGVcM2v_foo(vector_foo)", "void(i32)"));
   EXPECT_EQ(ISA, VFISAKind::AVX);
+  EXPECT_TRUE(isMasked());
+  EXPECT_TRUE(matchParametersNum()) << "Different number of scalar parameters";
+  EXPECT_EQ(VF, ElementCount::getFixed(2));
   EXPECT_EQ(Parameters.size(), (unsigned)2);
   EXPECT_EQ(Parameters[0], VFParameter({0, VFParamKind::Vector}));
   EXPECT_EQ(Parameters[1], VFParameter({1, VFParamKind::GlobalPredicate}));
-  EXPECT_EQ(ScalarName, "sin");
+  EXPECT_EQ(ScalarName, "foo");
+  EXPECT_EQ(VectorName, "vector_foo");
 }
 
 TEST_F(VFABIParserTest, ParseMaskingAVX2) {
-  EXPECT_TRUE(invokeParser("_ZGVdM2v_sin"));
-  EXPECT_EQ(VF, ElementCount::getFixed(2));
-  EXPECT_TRUE(IsMasked());
+  EXPECT_TRUE(invokeParser("_ZGVdM2v_foo(vector_foo)", "void(i32)"));
   EXPECT_EQ(ISA, VFISAKind::AVX2);
+  EXPECT_TRUE(isMasked());
+  EXPECT_TRUE(matchParametersNum()) << "Different number of scalar parameters";
+  EXPECT_EQ(VF, ElementCount::getFixed(2));
   EXPECT_EQ(Parameters.size(), (unsigned)2);
   EXPECT_EQ(Parameters[0], VFParameter({0, VFParamKind::Vector}));
   EXPECT_EQ(Parameters[1], VFParameter({1, VFParamKind::GlobalPredicate}));
-  EXPECT_EQ(ScalarName, "sin");
+  EXPECT_EQ(ScalarName, "foo");
+  EXPECT_EQ(VectorName, "vector_foo");
 }
 
 TEST_F(VFABIParserTest, ParseMaskingAVX512) {
-  EXPECT_TRUE(invokeParser("_ZGVeM2v_sin"));
-  EXPECT_EQ(VF, ElementCount::getFixed(2));
-  EXPECT_TRUE(IsMasked());
+  EXPECT_TRUE(invokeParser("_ZGVeM2v_foo(vector_foo)", "void(i32)"));
   EXPECT_EQ(ISA, VFISAKind::AVX512);
+  EXPECT_TRUE(isMasked());
+  EXPECT_TRUE(matchParametersNum()) << "Different number of scalar parameters";
+  EXPECT_EQ(VF, ElementCount::getFixed(2));
   EXPECT_EQ(Parameters.size(), (unsigned)2);
   EXPECT_EQ(Parameters[0], VFParameter({0, VFParamKind::Vector}));
   EXPECT_EQ(Parameters[1], VFParameter({1, VFParamKind::GlobalPredicate}));
-  EXPECT_EQ(ScalarName, "sin");
+  EXPECT_EQ(ScalarName, "foo");
+  EXPECT_EQ(VectorName, "vector_foo");
 }
 
 TEST_F(VFABIParserTest, ParseMaskingLLVM) {
-  EXPECT_TRUE(invokeParser("_ZGV_LLVM_M2v_sin(custom_vector_sin)",
-                           "custom_vector_sin"));
+  EXPECT_TRUE(invokeParser("_ZGV_LLVM_M2v_foo(vector_foo)", "void(i32)"));
+  EXPECT_EQ(ISA, VFISAKind::LLVM);
+  EXPECT_TRUE(isMasked());
+  EXPECT_TRUE(matchParametersNum()) << "Different number of scalar parameters";
   EXPECT_EQ(VF, ElementCount::getFixed(2));
-  EXPECT_TRUE(IsMasked());
+  EXPECT_EQ(Parameters.size(), (unsigned)2);
+  EXPECT_EQ(Parameters[0], VFParameter({0, VFParamKind::Vector}));
+  EXPECT_EQ(Parameters[1], VFParameter({1, VFParamKind::GlobalPredicate}));
+  EXPECT_EQ(ScalarName, "foo");
+  EXPECT_EQ(VectorName, "vector_foo");
+}
+
+TEST_F(VFABIParserTest, ParseScalableMaskingLLVM) {
+  EXPECT_FALSE(invokeParser("_ZGV_LLVM_Mxv_foo(vector_foo)"));
+}
+
+TEST_F(VFABIParserTest, LLVM_InternalISA) {
+  EXPECT_FALSE(invokeParser("_ZGV_LLVM_N2v_foo"));
+  EXPECT_TRUE(invokeParser("_ZGV_LLVM_N2v_foo(vector_foo)", "void(i32)"));
   EXPECT_EQ(ISA, VFISAKind::LLVM);
+  EXPECT_FALSE(isMasked());
+  EXPECT_TRUE(matchParametersNum()) << "Different number of scalar parameters";
+  EXPECT_EQ(Parameters.size(), (unsigned)1);
+  EXPECT_EQ(Parameters[0], VFParameter({0, VFParamKind::Vector}));
+  EXPECT_EQ(ScalarName, "foo");
+  EXPECT_EQ(VectorName, "vector_foo");
+}
+
+TEST_F(VFABIParserTest, IntrinsicsInLLVMIsa) {
+  EXPECT_TRUE(invokeParser("_ZGV_LLVM_N4vv_llvm.pow.f32(__svml_powf4)",
+                           "void(float, float)"));
+  EXPECT_EQ(ISA, VFISAKind::LLVM);
+  EXPECT_FALSE(isMasked());
+  EXPECT_TRUE(matchParametersNum()) << "Different number of scalar parameters";
+  EXPECT_EQ(VF, ElementCount::getFixed(4));
+  EXPECT_EQ(Parameters.size(), (unsigned)2);
+  EXPECT_EQ(Parameters[0], VFParameter({0, VFParamKind::Vector}));
+  EXPECT_EQ(Parameters[1], VFParameter({1, VFParamKind::Vector}));
+  EXPECT_EQ(ScalarName, "llvm.pow.f32");
+  EXPECT_EQ(VectorName, "__svml_powf4");
+}
+
+TEST_F(VFABIParserTest, ParseScalableRequiresDeclaration) {
+  const char *MangledName = "_ZGVsMxv_sin(custom_vg)";
+  EXPECT_FALSE(invokeParser(MangledName));
+  EXPECT_TRUE(invokeParser(MangledName, "void(i32)"));
+  EXPECT_EQ(ISA, VFISAKind::SVE);
+  EXPECT_TRUE(isMasked());
+  EXPECT_TRUE(matchParametersNum()) << "Different number of scalar parameters";
   EXPECT_EQ(Parameters.size(), (unsigned)2);
   EXPECT_EQ(Parameters[0], VFParameter({0, VFParamKind::Vector}));
   EXPECT_EQ(Parameters[1], VFParameter({1, VFParamKind::GlobalPredicate}));
   EXPECT_EQ(ScalarName, "sin");
-  EXPECT_EQ(VectorName, "custom_vector_sin");
+  EXPECT_EQ(VectorName, "custom_vg");
 }
 
-TEST_F(VFABIParserTest, ParseScalableMaskingLLVM) {
-  EXPECT_FALSE(
-      invokeParser("_ZGV_LLVM_Mxv_sin(custom_vector_sin)", "sin", "i32(i32)"));
+TEST_F(VFABIParserTest, ZeroIsInvalidVLEN) {
+  EXPECT_FALSE(invokeParser("_ZGVeM0v_foo"));
+  EXPECT_FALSE(invokeParser("_ZGVeN0v_foo"));
+  EXPECT_FALSE(invokeParser("_ZGVsM0v_foo"));
+  EXPECT_FALSE(invokeParser("_ZGVsN0v_foo"));
 }
 
 TEST_F(VFABIParserTest, ParseScalableMaskingSVE) {
-  EXPECT_TRUE(
-      invokeParser("_ZGVsMxv_sin(custom_vector_sin)", "sin", "i32(i32)"));
-  EXPECT_TRUE(IsMasked());
-  EXPECT_EQ(VF, ElementCount::getScalable(4));
+  EXPECT_TRUE(invokeParser("_ZGVsMxv_foo(vector_foo)", "i32(i32)"));
   EXPECT_EQ(ISA, VFISAKind::SVE);
+  EXPECT_TRUE(isMasked());
+  EXPECT_TRUE(matchParametersNum()) << "Different number of scalar parameters";
+  EXPECT_EQ(VF, ElementCount::getScalable(4));
   EXPECT_EQ(Parameters.size(), (unsigned)2);
   EXPECT_EQ(Parameters[0], VFParameter({0, VFParamKind::Vector}));
   EXPECT_EQ(Parameters[1], VFParameter({1, VFParamKind::GlobalPredicate}));
-  EXPECT_EQ(ScalarName, "sin");
-  EXPECT_EQ(VectorName, "custom_vector_sin");
+  EXPECT_EQ(ScalarName, "foo");
+  EXPECT_EQ(VectorName, "vector_foo");
 }
 
 TEST_F(VFABIParserTest, ParseScalableMaskingSVESincos) {
   EXPECT_TRUE(invokeParser("_ZGVsMxvl8l8_sincos(custom_vector_sincos)",
-                           "sincos", "void(double, double *, double *)"));
-  EXPECT_EQ(VF, ElementCount::getScalable(2));
-  EXPECT_TRUE(IsMasked());
+                           "void(double, ptr, ptr)"));
   EXPECT_EQ(ISA, VFISAKind::SVE);
+  EXPECT_TRUE(isMasked());
+  EXPECT_TRUE(matchParametersNum()) << "Different number of scalar parameters";
+  EXPECT_EQ(VF, ElementCount::getScalable(2));
   EXPECT_EQ(Parameters.size(), (unsigned)4);
   EXPECT_EQ(Parameters[0], VFParameter({0, VFParamKind::Vector}));
   EXPECT_EQ(Parameters[1], VFParameter({1, VFParamKind::OMP_Linear, 8}));
@@ -537,27 +620,42 @@ TEST_F(VFABIParserTest, ParseScalableMaskingSVESincos) {
 // Make sure that we get the correct VF if the return type is wider than any
 // parameter type.
 TEST_F(VFABIParserTest, ParseWiderReturnTypeSVE) {
-  EXPECT_TRUE(
-      invokeParser("_ZGVsMxvv_foo(vector_foo)", "foo", "i64(i32, i32)"));
+  EXPECT_TRUE(invokeParser("_ZGVsMxvv_foo(vector_foo)", "i64(i32, i32)"));
+  EXPECT_EQ(ISA, VFISAKind::SVE);
+  EXPECT_TRUE(isMasked());
+  EXPECT_TRUE(matchParametersNum()) << "Different number of scalar parameters";
+  EXPECT_EQ(Parameters.size(), (unsigned)3);
+  EXPECT_EQ(Parameters[0], VFParameter({0, VFParamKind::Vector}));
+  EXPECT_EQ(Parameters[1], VFParameter({1, VFParamKind::Vector}));
+  EXPECT_EQ(Parameters[2], VFParameter({2, VFParamKind::GlobalPredicate}));
   EXPECT_EQ(VF, ElementCount::getScalable(2));
+  EXPECT_EQ(ScalarName, "foo");
+  EXPECT_EQ(VectorName, "vector_foo");
 }
 
 // Make sure we handle void return types.
 TEST_F(VFABIParserTest, ParseVoidReturnTypeSVE) {
-  EXPECT_TRUE(invokeParser("_ZGVsMxv_foo(vector_foo)", "foo", "void(i16)"));
+  EXPECT_TRUE(invokeParser("_ZGVsMxv_foo(vector_foo)", "void(i16)"));
+  EXPECT_EQ(ISA, VFISAKind::SVE);
+  EXPECT_TRUE(isMasked());
+  EXPECT_TRUE(matchParametersNum()) << "Different number of scalar parameters";
+  EXPECT_EQ(Parameters.size(), (unsigned)2);
+  EXPECT_EQ(Parameters[0], VFParameter({0, VFParamKind::Vector}));
+  EXPECT_EQ(Parameters[1], VFParameter({1, VFParamKind::GlobalPredicate}));
   EXPECT_EQ(VF, ElementCount::getScalable(8));
+  EXPECT_EQ(ScalarName, "foo");
+  EXPECT_EQ(VectorName, "vector_foo");
 }
 
 // Make sure we reject unsupported parameter types.
 TEST_F(VFABIParserTest, ParseUnsupportedElementTypeSVE) {
-  EXPECT_FALSE(invokeParser("_ZGVsMxv_foo(vector_foo)", "foo", "void(i128)"));
+  EXPECT_FALSE(invokeParser("_ZGVsMxv_foo(vector_foo)", "void(i128)"));
 }
 
 // Make sure we reject unsupported return types
 TEST_F(VFABIParserTest, ParseUnsupportedReturnTypeSVE) {
-  EXPECT_FALSE(invokeParser("_ZGVsMxv_foo(vector_foo)", "foo", "fp128(float)"));
+  EXPECT_FALSE(invokeParser("_ZGVsMxv_foo(vector_foo)", "fp128(float)"));
 }
-
 class VFABIAttrTest : public testing::Test {
 protected:
   void SetUp() override {
@@ -592,39 +690,6 @@ TEST_F(VFABIAttrTest, Read) {
   EXPECT_EQ(Mappings, Exp);
 }
 
-TEST_F(VFABIParserTest, LLVM_InternalISA) {
-  EXPECT_FALSE(invokeParser("_ZGV_LLVM_N2v_sin"));
-  EXPECT_TRUE(invokeParser("_ZGV_LLVM_N2v_sin_(vector_name)", "vector_name"));
-  EXPECT_EQ(ISA, VFISAKind::LLVM);
-}
-
-TEST_F(VFABIParserTest, IntrinsicsInLLVMIsa) {
-  EXPECT_TRUE(invokeParser("_ZGV_LLVM_N4vv_llvm.pow.f32(__svml_powf4)",
-                           "__svml_powf4"));
-  EXPECT_EQ(VF, ElementCount::getFixed(4));
-  EXPECT_FALSE(IsMasked());
-  EXPECT_EQ(ISA, VFISAKind::LLVM);
-  EXPECT_EQ(Parameters.size(), (unsigned)2);
-  EXPECT_EQ(Parameters[0], VFParameter({0, VFParamKind::Vector}));
-  EXPECT_EQ(Parameters[1], VFParameter({1, VFParamKind::Vector}));
-  EXPECT_EQ(ScalarName, "llvm.pow.f32");
-}
-
-TEST_F(VFABIParserTest, ParseScalableRequiresDeclaration) {
-  const char *MangledName = "_ZGVsMxv_sin(custom_vg)";
-  // The parser succeds only when the correct function definition of
-  // `custom_vg` is added to the module.
-  EXPECT_FALSE(invokeParser(MangledName));
-  EXPECT_TRUE(invokeParser(MangledName, "sin", "double(double)"));
-}
-
-TEST_F(VFABIParserTest, ZeroIsInvalidVLEN) {
-  EXPECT_FALSE(invokeParser("_ZGVeM0v_sin"));
-  EXPECT_FALSE(invokeParser("_ZGVeN0v_sin"));
-  EXPECT_FALSE(invokeParser("_ZGVsM0v_sin"));
-  EXPECT_FALSE(invokeParser("_ZGVsN0v_sin"));
-}
-
 static std::unique_ptr<Module> parseIR(LLVMContext &C, const char *IR) {
   SMDiagnostic Err;
   std::unique_ptr<Module> Mod = parseAssemblyString(IR, Err, C);
@@ -642,9 +707,9 @@ entry:
   ret void
 }
 )IR");
-  auto F = dyn_cast_or_null<Function>(M->getNamedValue("call"));
+  auto *F = dyn_cast_or_null<Function>(M->getNamedValue("call"));
   ASSERT_TRUE(F);
-  auto CI = dyn_cast<CallInst>(&F->front().front());
+  auto *CI = dyn_cast<CallInst>(&F->front().front());
   ASSERT_TRUE(CI);
   ASSERT_TRUE(CI->isIndirectCall());
   auto Mappings = VFDatabase::getMappings(*CI);
-- 
GitLab


From 01ac530a2ea3ee0c24b729a8f3c16ac85542cd15 Mon Sep 17 00:00:00 2001
From: Benjamin Maxwell <benjamin.maxwell@arm.com>
Date: Mon, 11 Dec 2023 11:25:43 +0000
Subject: [PATCH 100/349] [mlir][ArmSME] Remove `vector.print` legality from
 ArmSMEToSCF (NFC) (#74875)

This was moved to VectorToArmSME in #74063, so this is no longer needed.

VectorToArmSME uses a greedy rewriter, so a similar legality rule is not
needed there.

See:
https://github.com/llvm/llvm-project/blob/bbb8a0df7367068e1cf2fc54edd376beb976b430/mlir/lib/Conversion/VectorToArmSME/VectorToArmSMEPass.cpp#L35
---
 mlir/lib/Conversion/ArmSMEToSCF/ArmSMEToSCF.cpp | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/mlir/lib/Conversion/ArmSMEToSCF/ArmSMEToSCF.cpp b/mlir/lib/Conversion/ArmSMEToSCF/ArmSMEToSCF.cpp
index c3c9780318a9..c9d7c0c313b5 100644
--- a/mlir/lib/Conversion/ArmSMEToSCF/ArmSMEToSCF.cpp
+++ b/mlir/lib/Conversion/ArmSMEToSCF/ArmSMEToSCF.cpp
@@ -484,12 +484,6 @@ struct ConvertArmSMEToSCFPass
     target.addLegalDialect<arm_sme::ArmSMEDialect, vector::VectorDialect,
                            arith::ArithDialect, scf::SCFDialect>();
     target.addIllegalOp<arm_sme::TileLoadOp, arm_sme::TileStoreOp>();
-    target.addDynamicallyLegalOp<vector::PrintOp>([](vector::PrintOp op) {
-      if (!op.getSource())
-        return true;
-      VectorType vectorType = dyn_cast<VectorType>(op.getPrintType());
-      return !vectorType || !arm_sme::isValidSMETileVectorType(vectorType);
-    });
     if (failed(applyPartialConversion(getOperation(), target,
                                       std::move(patterns))))
       signalPassFailure();
-- 
GitLab


From 3764f5e816f3769bd1770062e65fcc0192464f8a Mon Sep 17 00:00:00 2001
From: Rik Huijzer <github@huijzer.xyz>
Date: Mon, 11 Dec 2023 12:29:53 +0100
Subject: [PATCH 101/349] [mlir][llvm] Fix negative GEP crash in type
 consistency (#74859)

Fixes https://github.com/llvm/llvm-project/issues/74453.

The `gepToByteOffset` was implicitly casting an signed integer to an
unsigned integer even though negative dimensions are valid for
`llvm.getelementptr`.

---------

Co-authored-by: Tobias Gysi <tobias.gysi@nextsilicon.com>
---
 .../Dialect/LLVMIR/Transforms/TypeConsistency.cpp  |  5 ++++-
 mlir/test/Dialect/LLVMIR/type-consistency.mlir     | 14 ++++++++++++++
 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/mlir/lib/Dialect/LLVMIR/Transforms/TypeConsistency.cpp b/mlir/lib/Dialect/LLVMIR/Transforms/TypeConsistency.cpp
index b094c650ff19..cf900ac0be8f 100644
--- a/mlir/lib/Dialect/LLVMIR/Transforms/TypeConsistency.cpp
+++ b/mlir/lib/Dialect/LLVMIR/Transforms/TypeConsistency.cpp
@@ -161,7 +161,10 @@ static std::optional<uint64_t> gepToByteOffset(DataLayout &layout, GEPOp gep) {
     IntegerAttr indexInt = llvm::dyn_cast_if_present<IntegerAttr>(index);
     if (!indexInt)
       return std::nullopt;
-    indices.push_back(indexInt.getInt());
+    int32_t gepIndex = indexInt.getInt();
+    if (gepIndex < 0)
+      return std::nullopt;
+    indices.push_back(static_cast<uint32_t>(gepIndex));
   }
 
   uint64_t offset = indices[0] * layout.getTypeSize(gep.getElemType());
diff --git a/mlir/test/Dialect/LLVMIR/type-consistency.mlir b/mlir/test/Dialect/LLVMIR/type-consistency.mlir
index 1504a98e6f8c..3a1ab924ebda 100644
--- a/mlir/test/Dialect/LLVMIR/type-consistency.mlir
+++ b/mlir/test/Dialect/LLVMIR/type-consistency.mlir
@@ -151,6 +151,20 @@ llvm.func @index_to_struct(%arg: i32) {
 
 // -----
 
+// CHECK-LABEL: llvm.func @no_crash_on_negative_gep_index
+llvm.func @no_crash_on_negative_gep_index() {
+  %0 = llvm.mlir.constant(1.000000e+00 : f16) : f16
+  %1 = llvm.mlir.constant(1 : i32) : i32
+  // CHECK: %[[ALLOCA:.*]] = llvm.alloca %{{.*}} x !llvm.struct<"foo", (i32, i32, i32)>
+  %2 = llvm.alloca %1 x !llvm.struct<"foo", (i32, i32, i32)> : (i32) -> !llvm.ptr
+  // CHECK: llvm.getelementptr %[[ALLOCA]][-1] : (!llvm.ptr) -> !llvm.ptr, f32
+  %3 = llvm.getelementptr %2[-1] : (!llvm.ptr) -> !llvm.ptr, f32
+  llvm.store %0, %3 : f16, !llvm.ptr
+  llvm.return
+}
+
+// -----
+
 // CHECK-LABEL: llvm.func @coalesced_store_ints
 // CHECK-SAME: %[[ARG:.*]]: i64
 llvm.func @coalesced_store_ints(%arg: i64) {
-- 
GitLab


From dc2ce60024bb4f38c2a3d19c4cbd39284e72969f Mon Sep 17 00:00:00 2001
From: Shenghang Tsai <jackalcooper@gmail.com>
Date: Mon, 11 Dec 2023 19:32:21 +0800
Subject: [PATCH 102/349] [mlir][CAPI] Add mlirOpOperandGetValue (#75032)

---
 mlir/include/mlir-c/IR.h | 3 +++
 mlir/lib/CAPI/IR/IR.cpp  | 4 ++++
 mlir/test/CAPI/ir.c      | 9 +++++++++
 3 files changed, 16 insertions(+)

diff --git a/mlir/include/mlir-c/IR.h b/mlir/include/mlir-c/IR.h
index 413eaa6aa3fe..82da511f807a 100644
--- a/mlir/include/mlir-c/IR.h
+++ b/mlir/include/mlir-c/IR.h
@@ -940,6 +940,9 @@ MLIR_CAPI_EXPORTED void mlirValueReplaceAllUsesOfWith(MlirValue of,
 /// Returns whether the op operand is null.
 MLIR_CAPI_EXPORTED bool mlirOpOperandIsNull(MlirOpOperand opOperand);
 
+/// Returns the value of an op operand.
+MLIR_CAPI_EXPORTED MlirValue mlirOpOperandGetValue(MlirOpOperand opOperand);
+
 /// Returns the owner operation of an op operand.
 MLIR_CAPI_EXPORTED MlirOperation mlirOpOperandGetOwner(MlirOpOperand opOperand);
 
diff --git a/mlir/lib/CAPI/IR/IR.cpp b/mlir/lib/CAPI/IR/IR.cpp
index d1ee1b774c34..ac9889df11f8 100644
--- a/mlir/lib/CAPI/IR/IR.cpp
+++ b/mlir/lib/CAPI/IR/IR.cpp
@@ -986,6 +986,10 @@ MlirOperation mlirOpOperandGetOwner(MlirOpOperand opOperand) {
   return wrap(unwrap(opOperand)->getOwner());
 }
 
+MlirValue mlirOpOperandGetValue(MlirOpOperand opOperand) {
+  return wrap(unwrap(opOperand)->get());
+}
+
 unsigned mlirOpOperandGetOperandNumber(MlirOpOperand opOperand) {
   return unwrap(opOperand)->getOperandNumber();
 }
diff --git a/mlir/test/CAPI/ir.c b/mlir/test/CAPI/ir.c
index 315458a08b61..a9850c0a132e 100644
--- a/mlir/test/CAPI/ir.c
+++ b/mlir/test/CAPI/ir.c
@@ -1970,6 +1970,15 @@ int testOperands(void) {
   fprintf(stderr, "\n");
   // CHECK: Second replacement use owner: "dummy.op2"
 
+  MlirOpOperand use5 = mlirValueGetFirstUse(constTwoValue);
+  MlirOpOperand use6 = mlirOpOperandGetNextUse(use5);
+  if (!mlirValueEqual(mlirOpOperandGetValue(use5),
+                      mlirOpOperandGetValue(use6))) {
+    fprintf(stderr,
+            "ERROR: First and second operand should share the same value\n");
+    return 5;
+  }
+
   mlirOperationDestroy(op);
   mlirOperationDestroy(op2);
   mlirOperationDestroy(constZero);
-- 
GitLab


From 4648acbb6047afc4834560825c5a2bc6d6384e0d Mon Sep 17 00:00:00 2001
From: Orlando Cazalet-Hyams <orlando.hyams@sony.com>
Date: Mon, 11 Dec 2023 11:34:53 +0000
Subject: [PATCH 103/349] [NFC][RemoveDIs] Add LocationType parameter to
 DPValue ctor (#74091)

We can tidy up the interfaces a bit once all intrinsics are supported, as we
will have a more informed view then.
---
 llvm/include/llvm/IR/DebugProgramInstruction.h | 2 +-
 llvm/lib/IR/DebugProgramInstruction.cpp        | 5 ++---
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/llvm/include/llvm/IR/DebugProgramInstruction.h b/llvm/include/llvm/IR/DebugProgramInstruction.h
index d6b4536a2a07..f73a6237a477 100644
--- a/llvm/include/llvm/IR/DebugProgramInstruction.h
+++ b/llvm/include/llvm/IR/DebugProgramInstruction.h
@@ -113,7 +113,7 @@ public:
   /// Directly construct a new DPValue representing a dbg.value intrinsic
   /// assigning \p Location to the DV / Expr / DI variable.
   DPValue(Metadata *Location, DILocalVariable *DV, DIExpression *Expr,
-          const DILocation *DI);
+          const DILocation *DI, LocationType Type = LocationType::Value);
 
   /// Iterator for ValueAsMetadata that internally uses direct pointer iteration
   /// over either a ValueAsMetadata* or a ValueAsMetadata**, dereferencing to the
diff --git a/llvm/lib/IR/DebugProgramInstruction.cpp b/llvm/lib/IR/DebugProgramInstruction.cpp
index 6a4ee9d61010..df45c6ea3a77 100644
--- a/llvm/lib/IR/DebugProgramInstruction.cpp
+++ b/llvm/lib/IR/DebugProgramInstruction.cpp
@@ -35,10 +35,9 @@ DPValue::DPValue(const DPValue &DPV)
       DbgLoc(DPV.getDebugLoc()), Type(DPV.getType()) {}
 
 DPValue::DPValue(Metadata *Location, DILocalVariable *DV, DIExpression *Expr,
-                 const DILocation *DI)
+                 const DILocation *DI, LocationType Type)
     : DebugValueUser(Location), Variable(DV), Expression(Expr), DbgLoc(DI),
-      Type(LocationType::Value) {
-}
+      Type(Type) {}
 
 void DPValue::deleteInstr() { delete this; }
 
-- 
GitLab


From ed07fc809c371825ade9cba99966c23b0f23e868 Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Mon, 11 Dec 2023 12:33:57 +0100
Subject: [PATCH 104/349] [Bitcode] Add missing getValue() return value checks

---
 llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
index 9d7e838733b5..98c5e948dc59 100644
--- a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
+++ b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
@@ -5363,6 +5363,8 @@ Error BitcodeReader::parseFunctionBody(Function *F) {
       Type *TokenTy = Type::getTokenTy(Context);
       Value *ParentPad = getValue(Record, Idx++, NextValueNo, TokenTy,
                                   getVirtualTypeID(TokenTy), CurBB);
+      if (!ParentPad)
+        return error("Invalid record");
 
       unsigned NumHandlers = Record[Idx++];
 
@@ -5404,6 +5406,8 @@ Error BitcodeReader::parseFunctionBody(Function *F) {
       Type *TokenTy = Type::getTokenTy(Context);
       Value *ParentPad = getValue(Record, Idx++, NextValueNo, TokenTy,
                                   getVirtualTypeID(TokenTy), CurBB);
+      if (!ParentPad)
+        return error("Invald record");
 
       unsigned NumArgOperands = Record[Idx++];
 
-- 
GitLab


From 6aa6ef73ece0042953f25c4b198fdec4d6f9769d Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp@bytedance.com>
Date: Mon, 11 Dec 2023 19:45:13 +0800
Subject: [PATCH 105/349] [MemCpyOpt] Don't perform call slot opt if alloc type
 is scalable (#75027)

This fixes #75010.
---
 .../lib/Transforms/Scalar/MemCpyOptimizer.cpp |  7 +++++--
 llvm/test/Transforms/MemCpyOpt/pr75010.ll     | 19 +++++++++++++++++++
 2 files changed, 24 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/Transforms/MemCpyOpt/pr75010.ll

diff --git a/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp b/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
index 0e55249d63a8..9d058e0d2483 100644
--- a/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
+++ b/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
@@ -880,8 +880,11 @@ bool MemCpyOptPass::performCallSlotOptzn(Instruction *cpyLoad,
     return false;
 
   const DataLayout &DL = cpyLoad->getModule()->getDataLayout();
-  uint64_t srcSize = DL.getTypeAllocSize(srcAlloca->getAllocatedType()) *
-                     srcArraySize->getZExtValue();
+  TypeSize SrcAllocaSize = DL.getTypeAllocSize(srcAlloca->getAllocatedType());
+  // We can't optimize scalable types.
+  if (SrcAllocaSize.isScalable())
+    return false;
+  uint64_t srcSize = SrcAllocaSize * srcArraySize->getZExtValue();
 
   if (cpySize < srcSize)
     return false;
diff --git a/llvm/test/Transforms/MemCpyOpt/pr75010.ll b/llvm/test/Transforms/MemCpyOpt/pr75010.ll
new file mode 100644
index 000000000000..c9af7543b42e
--- /dev/null
+++ b/llvm/test/Transforms/MemCpyOpt/pr75010.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -passes=memcpyopt < %s | FileCheck %s
+
+define void @f(ptr nocapture noundef writeonly %r, <vscale x 2 x i32> %x) {
+; CHECK-LABEL: @f(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[X_ADDR:%.*]] = alloca <vscale x 2 x i32>, align 8
+; CHECK-NEXT:    store <vscale x 2 x i32> [[X:%.*]], ptr [[X_ADDR]], align 8
+; CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr [[X_ADDR]], align 8
+; CHECK-NEXT:    store i64 [[TMP0]], ptr [[R:%.*]], align 1
+; CHECK-NEXT:    ret void
+;
+entry:
+  %x.addr = alloca <vscale x 2 x i32>, align 8
+  store <vscale x 2 x i32> %x, ptr %x.addr, align 8
+  %0 = load i64, ptr %x.addr, align 8
+  store i64 %0, ptr %r, align 1
+  ret void
+}
-- 
GitLab


From 7b7c85d156f327312e37a60c21a4a2093919c5e1 Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Mon, 11 Dec 2023 12:45:22 +0100
Subject: [PATCH 106/349] [Bitcode] Check type of alloca size argument

This must be an integer. This check is present in LLParser but not
the BitcodeReader.
---
 llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
index 98c5e948dc59..e3451675c213 100644
--- a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
+++ b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
@@ -5962,6 +5962,9 @@ Error BitcodeReader::parseFunctionBody(Function *F) {
       if (!Align)
         Align = DL.getPrefTypeAlign(Ty);
 
+      if (!Size->getType()->isIntegerTy())
+        return error("alloca element count must have integer type");
+
       AllocaInst *AI = new AllocaInst(Ty, AS, Size, *Align);
       AI->setUsedWithInAlloca(InAlloca);
       AI->setSwiftError(SwiftError);
-- 
GitLab


From d1deeae0946aad2de36153f3462575813ace88fd Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <RKSimon@users.noreply.github.com>
Date: Mon, 11 Dec 2023 11:52:53 +0000
Subject: [PATCH 107/349] [X86] Rename VBROADCASTF128/VBROADCASTI128 to
 VBROADCASTF128rm/VBROADCASTI128rm (#75040)

Add missing rm postfix to show these are load instructions
---
 .../X86/MCTargetDesc/X86InstComments.cpp      |  4 +--
 .../Target/X86/X86FixupVectorConstants.cpp    |  4 +--
 llvm/lib/Target/X86/X86InstrSSE.td            | 30 +++++++++----------
 llvm/lib/Target/X86/X86MCInstLower.cpp        |  8 ++---
 llvm/lib/Target/X86/X86ReplaceableInstrs.def  |  2 +-
 llvm/lib/Target/X86/X86SchedAlderlakeP.td     |  2 +-
 llvm/lib/Target/X86/X86SchedBroadwell.td      |  4 +--
 llvm/lib/Target/X86/X86SchedHaswell.td        |  4 +--
 llvm/lib/Target/X86/X86SchedIceLake.td        |  4 +--
 llvm/lib/Target/X86/X86SchedSapphireRapids.td |  2 +-
 llvm/lib/Target/X86/X86SchedSkylakeClient.td  |  4 +--
 llvm/lib/Target/X86/X86SchedSkylakeServer.td  |  4 +--
 llvm/lib/Target/X86/X86ScheduleBdVer2.td      |  2 +-
 llvm/lib/Target/X86/X86ScheduleBtVer2.td      |  2 +-
 llvm/lib/Target/X86/X86ScheduleZnver1.td      |  4 +--
 llvm/lib/Target/X86/X86ScheduleZnver2.td      |  4 +--
 .../test/CodeGen/X86/evex-to-vex-compress.mir |  4 +--
 17 files changed, 44 insertions(+), 44 deletions(-)

diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
index ee82faebb57e..20b37d5a9990 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
@@ -1285,8 +1285,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
     Src2Name = getRegName(MI->getOperand(2).getReg());
     break;
 
-  case X86::VBROADCASTF128:
-  case X86::VBROADCASTI128:
+  case X86::VBROADCASTF128rm:
+  case X86::VBROADCASTI128rm:
   CASE_AVX512_INS_COMMON(BROADCASTF64X2, Z128, rm)
   CASE_AVX512_INS_COMMON(BROADCASTI64X2, Z128, rm)
     DecodeSubVectorBroadcast(4, 2, ShuffleMask);
diff --git a/llvm/lib/Target/X86/X86FixupVectorConstants.cpp b/llvm/lib/Target/X86/X86FixupVectorConstants.cpp
index 99e92bbcf996..4b6038cb5938 100644
--- a/llvm/lib/Target/X86/X86FixupVectorConstants.cpp
+++ b/llvm/lib/Target/X86/X86FixupVectorConstants.cpp
@@ -285,7 +285,7 @@ bool X86FixupVectorConstantsPass::processInstruction(MachineFunction &MF,
   case X86::VMOVAPSYrm:
   case X86::VMOVUPDYrm:
   case X86::VMOVUPSYrm:
-    return ConvertToBroadcast(0, X86::VBROADCASTF128, X86::VBROADCASTSDYrm,
+    return ConvertToBroadcast(0, X86::VBROADCASTF128rm, X86::VBROADCASTSDYrm,
                               X86::VBROADCASTSSYrm, 0, 0, 1);
   case X86::VMOVAPDZ128rm:
   case X86::VMOVAPSZ128rm:
@@ -318,7 +318,7 @@ bool X86FixupVectorConstantsPass::processInstruction(MachineFunction &MF,
   case X86::VMOVDQAYrm:
   case X86::VMOVDQUYrm:
     return ConvertToBroadcast(
-        0, HasAVX2 ? X86::VBROADCASTI128 : X86::VBROADCASTF128,
+        0, HasAVX2 ? X86::VBROADCASTI128rm : X86::VBROADCASTF128rm,
         HasAVX2 ? X86::VPBROADCASTQYrm : X86::VBROADCASTSDYrm,
         HasAVX2 ? X86::VPBROADCASTDYrm : X86::VBROADCASTSSYrm,
         HasAVX2 ? X86::VPBROADCASTWYrm : 0, HasAVX2 ? X86::VPBROADCASTBYrm : 0,
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index 34eb17af1033..cf57fe562ed5 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -7093,35 +7093,35 @@ def VBROADCASTSDYrr  : avx2_broadcast_rr<0x19, "vbroadcastsd", VR256,
 //                  halves of a 256-bit vector.
 //
 let mayLoad = 1, hasSideEffects = 0, Predicates = [HasAVX2] in
-def VBROADCASTI128 : AVX8I<0x5A, MRMSrcMem, (outs VR256:$dst),
-                           (ins i128mem:$src),
-                           "vbroadcasti128\t{$src, $dst|$dst, $src}", []>,
-                           Sched<[WriteShuffleLd]>, VEX, VEX_L;
+def VBROADCASTI128rm : AVX8I<0x5A, MRMSrcMem, (outs VR256:$dst),
+                             (ins i128mem:$src),
+                             "vbroadcasti128\t{$src, $dst|$dst, $src}", []>,
+                             Sched<[WriteShuffleLd]>, VEX, VEX_L;
 
 let mayLoad = 1, hasSideEffects = 0, Predicates = [HasAVX],
     ExeDomain = SSEPackedSingle in
-def VBROADCASTF128 : AVX8I<0x1A, MRMSrcMem, (outs VR256:$dst),
-                           (ins f128mem:$src),
-                           "vbroadcastf128\t{$src, $dst|$dst, $src}", []>,
-                           Sched<[SchedWriteFShuffle.XMM.Folded]>, VEX, VEX_L;
+def VBROADCASTF128rm : AVX8I<0x1A, MRMSrcMem, (outs VR256:$dst),
+                             (ins f128mem:$src),
+                             "vbroadcastf128\t{$src, $dst|$dst, $src}", []>,
+                             Sched<[SchedWriteFShuffle.XMM.Folded]>, VEX, VEX_L;
 
 let Predicates = [HasAVX, NoVLX] in {
 def : Pat<(v4f64 (X86SubVBroadcastld128 addr:$src)),
-          (VBROADCASTF128 addr:$src)>;
+          (VBROADCASTF128rm addr:$src)>;
 def : Pat<(v8f32 (X86SubVBroadcastld128 addr:$src)),
-          (VBROADCASTF128 addr:$src)>;
+          (VBROADCASTF128rm addr:$src)>;
 // NOTE: We're using FP instructions here, but execution domain fixing can
 // convert to integer when profitable.
 def : Pat<(v4i64 (X86SubVBroadcastld128 addr:$src)),
-          (VBROADCASTF128 addr:$src)>;
+          (VBROADCASTF128rm addr:$src)>;
 def : Pat<(v8i32 (X86SubVBroadcastld128 addr:$src)),
-          (VBROADCASTF128 addr:$src)>;
+          (VBROADCASTF128rm addr:$src)>;
 def : Pat<(v16i16 (X86SubVBroadcastld128 addr:$src)),
-          (VBROADCASTF128 addr:$src)>;
+          (VBROADCASTF128rm addr:$src)>;
 def : Pat<(v16f16 (X86SubVBroadcastld128 addr:$src)),
-          (VBROADCASTF128 addr:$src)>;
+          (VBROADCASTF128rm addr:$src)>;
 def : Pat<(v32i8 (X86SubVBroadcastld128 addr:$src)),
-          (VBROADCASTF128 addr:$src)>;
+          (VBROADCASTF128rm addr:$src)>;
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp
index cbb012161524..e1a67f61e766 100644
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -1865,8 +1865,8 @@ static void addConstantComments(const MachineInstr *MI,
     // For loads from a constant pool to a vector register, print the constant
     // loaded.
     CASE_ALL_MOV_RM()
-  case X86::VBROADCASTF128:
-  case X86::VBROADCASTI128:
+  case X86::VBROADCASTF128rm:
+  case X86::VBROADCASTI128rm:
   case X86::VBROADCASTF32X4Z256rm:
   case X86::VBROADCASTF32X4rm:
   case X86::VBROADCASTF32X8rm:
@@ -1891,8 +1891,8 @@ static void addConstantComments(const MachineInstr *MI,
       CASE_128_MOV_RM()                NumLanes = 1; BitWidth = 128; break;
       CASE_256_MOV_RM()                NumLanes = 1; BitWidth = 256; break;
       CASE_512_MOV_RM()                NumLanes = 1; BitWidth = 512; break;
-      case X86::VBROADCASTF128:        NumLanes = 2; BitWidth = 128; break;
-      case X86::VBROADCASTI128:        NumLanes = 2; BitWidth = 128; break;
+      case X86::VBROADCASTF128rm:      NumLanes = 2; BitWidth = 128; break;
+      case X86::VBROADCASTI128rm:      NumLanes = 2; BitWidth = 128; break;
       case X86::VBROADCASTF32X4Z256rm: NumLanes = 2; BitWidth = 128; break;
       case X86::VBROADCASTF32X4rm:     NumLanes = 4; BitWidth = 128; break;
       case X86::VBROADCASTF32X8rm:     NumLanes = 2; BitWidth = 256; break;
diff --git a/llvm/lib/Target/X86/X86ReplaceableInstrs.def b/llvm/lib/Target/X86/X86ReplaceableInstrs.def
index 4798275c0519..e1383198d3fe 100644
--- a/llvm/lib/Target/X86/X86ReplaceableInstrs.def
+++ b/llvm/lib/Target/X86/X86ReplaceableInstrs.def
@@ -202,7 +202,7 @@ ENTRY(VBROADCASTSSYrr, VBROADCASTSSYrr, VPBROADCASTDYrr)
 ENTRY(VBROADCASTSSYrm, VBROADCASTSSYrm, VPBROADCASTDYrm)
 ENTRY(VBROADCASTSDYrr, VBROADCASTSDYrr, VPBROADCASTQYrr)
 ENTRY(VBROADCASTSDYrm, VBROADCASTSDYrm, VPBROADCASTQYrm)
-ENTRY(VBROADCASTF128, VBROADCASTF128, VBROADCASTI128)
+ENTRY(VBROADCASTF128rm, VBROADCASTF128rm, VBROADCASTI128rm)
 ENTRY(VBLENDPSYrri, VBLENDPSYrri, VPBLENDDYrri)
 ENTRY(VBLENDPSYrmi, VBLENDPSYrmi, VPBLENDDYrmi)
 ENTRY(VPERMILPSYmi, VPERMILPSYmi, VPSHUFDYmi)
diff --git a/llvm/lib/Target/X86/X86SchedAlderlakeP.td b/llvm/lib/Target/X86/X86SchedAlderlakeP.td
index 3406a28be2c2..8e3e55428264 100644
--- a/llvm/lib/Target/X86/X86SchedAlderlakeP.td
+++ b/llvm/lib/Target/X86/X86SchedAlderlakeP.td
@@ -1328,7 +1328,7 @@ def ADLPWriteResGroup117 : SchedWriteRes<[ADLPPort02_03_11]> {
   let Latency = 8;
 }
 def : InstRW<[ADLPWriteResGroup117], (instregex "^MMX_MOV(D|Q)64rm$",
-                                                "^VBROADCAST(F|I)128$",
+                                                "^VBROADCAST(F|I)128rm$",
                                                 "^VBROADCASTS(D|S)Yrm$",
                                                 "^VMOV(D|SH|SL)DUPYrm$",
                                                 "^VPBROADCAST(D|Q)Yrm$")>;
diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td
index 8575f747b4d3..61a8832000e2 100644
--- a/llvm/lib/Target/X86/X86SchedBroadwell.td
+++ b/llvm/lib/Target/X86/X86SchedBroadwell.td
@@ -946,8 +946,8 @@ def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> {
   let ReleaseAtCycles = [1];
 }
 def: InstRW<[BWWriteResGroup58], (instregex "LD_F(32|64|80)m")>;
-def: InstRW<[BWWriteResGroup58], (instrs VBROADCASTF128,
-                                         VBROADCASTI128,
+def: InstRW<[BWWriteResGroup58], (instrs VBROADCASTF128rm,
+                                         VBROADCASTI128rm,
                                          VBROADCASTSDYrm,
                                          VBROADCASTSSYrm,
                                          VMOVDDUPYrm,
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td
index d10d7684ac12..8795ca95c559 100644
--- a/llvm/lib/Target/X86/X86SchedHaswell.td
+++ b/llvm/lib/Target/X86/X86SchedHaswell.td
@@ -876,8 +876,8 @@ def HWWriteResGroup0_1 : SchedWriteRes<[HWPort23]> {
   let NumMicroOps = 1;
   let ReleaseAtCycles = [1];
 }
-def: InstRW<[HWWriteResGroup0_1], (instrs VBROADCASTF128,
-                                          VBROADCASTI128,
+def: InstRW<[HWWriteResGroup0_1], (instrs VBROADCASTF128rm,
+                                          VBROADCASTI128rm,
                                           VBROADCASTSDYrm,
                                           VBROADCASTSSYrm,
                                           VMOVDDUPYrm,
diff --git a/llvm/lib/Target/X86/X86SchedIceLake.td b/llvm/lib/Target/X86/X86SchedIceLake.td
index a2aa2655bca2..e27af1433d45 100644
--- a/llvm/lib/Target/X86/X86SchedIceLake.td
+++ b/llvm/lib/Target/X86/X86SchedIceLake.td
@@ -1274,8 +1274,8 @@ def ICXWriteResGroup89 : SchedWriteRes<[ICXPort23]> {
   let ReleaseAtCycles = [1];
 }
 def: InstRW<[ICXWriteResGroup89], (instregex "LD_F(32|64|80)m")>;
-def: InstRW<[ICXWriteResGroup89], (instrs VBROADCASTF128,
-                                          VBROADCASTI128,
+def: InstRW<[ICXWriteResGroup89], (instrs VBROADCASTF128rm,
+                                          VBROADCASTI128rm,
                                           VBROADCASTSDYrm,
                                           VBROADCASTSSYrm,
                                           VMOVDDUPYrm,
diff --git a/llvm/lib/Target/X86/X86SchedSapphireRapids.td b/llvm/lib/Target/X86/X86SchedSapphireRapids.td
index 6a426ef4cf54..4eac53385ae5 100644
--- a/llvm/lib/Target/X86/X86SchedSapphireRapids.td
+++ b/llvm/lib/Target/X86/X86SchedSapphireRapids.td
@@ -1599,7 +1599,7 @@ def SPRWriteResGroup126 : SchedWriteRes<[SPRPort02_03_11]> {
   let Latency = 8;
 }
 def : InstRW<[SPRWriteResGroup126], (instregex "^MMX_MOV(D|Q)64rm$",
-                                               "^VBROADCAST(F|I)128$",
+                                               "^VBROADCAST(F|I)128rm$",
                                                "^VBROADCAST(F|I)32X(2|4)Z256rm$",
                                                "^VBROADCAST(F|I)32X(8|2Z)rm$",
                                                "^VBROADCAST(F|I)(32|64)X4rm$",
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
index 92ed491bc296..4fa138f69fb9 100644
--- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
@@ -1064,8 +1064,8 @@ def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> {
   let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKLWriteResGroup85], (instregex "LD_F(32|64|80)m")>;
-def: InstRW<[SKLWriteResGroup85], (instrs VBROADCASTF128,
-                                          VBROADCASTI128,
+def: InstRW<[SKLWriteResGroup85], (instrs VBROADCASTF128rm,
+                                          VBROADCASTI128rm,
                                           VBROADCASTSDYrm,
                                           VBROADCASTSSYrm,
                                           VMOVDDUPYrm,
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
index ed22f95c83e5..8194af8a6e1d 100644
--- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
@@ -1254,8 +1254,8 @@ def SKXWriteResGroup89 : SchedWriteRes<[SKXPort23]> {
   let ReleaseAtCycles = [1];
 }
 def: InstRW<[SKXWriteResGroup89], (instregex "LD_F(32|64|80)m")>;
-def: InstRW<[SKXWriteResGroup89], (instrs VBROADCASTF128,
-                                          VBROADCASTI128,
+def: InstRW<[SKXWriteResGroup89], (instrs VBROADCASTF128rm,
+                                          VBROADCASTI128rm,
                                           VBROADCASTSDYrm,
                                           VBROADCASTSSYrm,
                                           VMOVDDUPYrm,
diff --git a/llvm/lib/Target/X86/X86ScheduleBdVer2.td b/llvm/lib/Target/X86/X86ScheduleBdVer2.td
index aeeabba45b65..c9749979576f 100644
--- a/llvm/lib/Target/X86/X86ScheduleBdVer2.td
+++ b/llvm/lib/Target/X86/X86ScheduleBdVer2.td
@@ -933,7 +933,7 @@ def PdWriteVBROADCASTF128 : SchedWriteRes<[PdFPU01, PdFPFMA]> {
   let ReleaseAtCycles = [1, 3];
   let NumMicroOps = 2;
 }
-def : InstRW<[PdWriteVBROADCASTF128], (instrs VBROADCASTF128)>;
+def : InstRW<[PdWriteVBROADCASTF128], (instrs VBROADCASTF128rm)>;
 
 defm : PdWriteResXMMPair<WriteFVarShuffle,  [PdFPU1, PdFPXBR],  3>;
 defm : PdWriteResYMMPair<WriteFVarShuffleY, [PdFPU1, PdFPXBR],  3, [2, 2], 2>;
diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td
index 8b7d501981b1..9cba933e82b0 100644
--- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td
+++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td
@@ -816,7 +816,7 @@ def JWriteVBROADCASTYLd: SchedWriteRes<[JLAGU, JFPU01, JFPX]> {
 }
 def : InstRW<[JWriteVBROADCASTYLd], (instrs VBROADCASTSDYrm,
                                             VBROADCASTSSYrm,
-                                            VBROADCASTF128)>;
+                                            VBROADCASTF128rm)>;
 
 def JWriteJVZEROALL: SchedWriteRes<[]> {
   let Latency = 90;
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td
index e39bcf807a0c..7ee9eadf8439 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver1.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td
@@ -996,8 +996,8 @@ def ZnWriteBROADCAST : SchedWriteRes<[ZnAGU, ZnFPU13]> {
   let Latency = 8;
 }
 // VBROADCASTF128 / VBROADCASTI128.
-def : InstRW<[ZnWriteBROADCAST], (instrs VBROADCASTF128,
-                                         VBROADCASTI128)>;
+def : InstRW<[ZnWriteBROADCAST], (instrs VBROADCASTF128rm,
+                                         VBROADCASTI128rm)>;
 
 // EXTRACTPS.
 // r32,x,i.
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver2.td b/llvm/lib/Target/X86/X86ScheduleZnver2.td
index ecaca70bb677..c0775847798d 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver2.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver2.td
@@ -1004,8 +1004,8 @@ def Zn2WriteBROADCAST : SchedWriteRes<[Zn2AGU, Zn2FPU13]> {
   let Latency = 8;
 }
 // VBROADCASTF128 / VBROADCASTI128.
-def : InstRW<[Zn2WriteBROADCAST], (instrs VBROADCASTF128,
-                                          VBROADCASTI128)>;
+def : InstRW<[Zn2WriteBROADCAST], (instrs VBROADCASTF128rm,
+                                          VBROADCASTI128rm)>;
 
 // EXTRACTPS.
 // r32,x,i.
diff --git a/llvm/test/CodeGen/X86/evex-to-vex-compress.mir b/llvm/test/CodeGen/X86/evex-to-vex-compress.mir
index dc19b2aa8afa..06d3c1532c3e 100644
--- a/llvm/test/CodeGen/X86/evex-to-vex-compress.mir
+++ b/llvm/test/CodeGen/X86/evex-to-vex-compress.mir
@@ -677,7 +677,7 @@ body: |
   $ymm0 = VPMOVZXWQZ256rm                      $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPMOVZXWQYrr                $xmm0
   $ymm0 = VPMOVZXWQZ256rr                      $xmm0
-  ; CHECK: $ymm0 = VBROADCASTF128              $rip, 1, $noreg, 0, $noreg
+  ; CHECK: $ymm0 = VBROADCASTF128rm            $rip, 1, $noreg, 0, $noreg
   $ymm0 = VBROADCASTF32X4Z256rm                $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VBROADCASTSDYrm             $rip, 1, $noreg, 0, $noreg
   $ymm0 = VBROADCASTF32X2Z256rm                $rip, 1, $noreg, 0, $noreg
@@ -703,7 +703,7 @@ body: |
   $ymm0 = VPBROADCASTWZ256rm                   $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPBROADCASTWYrr             $xmm0
   $ymm0 = VPBROADCASTWZ256rr                   $xmm0
-  ; CHECK: $ymm0 = VBROADCASTI128              $rip, 1, $noreg, 0, $noreg
+  ; CHECK: $ymm0 = VBROADCASTI128rm            $rip, 1, $noreg, 0, $noreg
   $ymm0 = VBROADCASTI32X4Z256rm                $rip, 1, $noreg, 0, $noreg
   ; CHECK: $ymm0 = VPBROADCASTQYrm             $rip, 1, $noreg, 0, $noreg
   $ymm0 = VBROADCASTI32X2Z256rm                $rip, 1, $noreg, 0, $noreg
-- 
GitLab


From b68afd7b51769796cf920d7926bad3067c7092a1 Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Mon, 11 Dec 2023 12:51:46 +0100
Subject: [PATCH 108/349] [Bitcode] Check validity of fcmp/icmp predicate

The predicate should match the operand types.
---
 llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
index e3451675c213..a11690a19a0e 100644
--- a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
+++ b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
@@ -5248,7 +5248,7 @@ Error BitcodeReader::parseFunctionBody(Function *F) {
         return error(
             "Invalid record: operand number exceeded available operands");
 
-      unsigned PredVal = Record[OpNum];
+      CmpInst::Predicate PredVal = CmpInst::Predicate(Record[OpNum]);
       bool IsFP = LHS->getType()->isFPOrFPVectorTy();
       FastMathFlags FMF;
       if (IsFP && Record.size() > OpNum+1)
@@ -5257,10 +5257,15 @@ Error BitcodeReader::parseFunctionBody(Function *F) {
       if (OpNum+1 != Record.size())
         return error("Invalid record");
 
-      if (LHS->getType()->isFPOrFPVectorTy())
-        I = new FCmpInst((FCmpInst::Predicate)PredVal, LHS, RHS);
-      else
-        I = new ICmpInst((ICmpInst::Predicate)PredVal, LHS, RHS);
+      if (IsFP) {
+        if (!CmpInst::isFPPredicate(PredVal))
+          return error("Invalid fcmp predicate");
+        I = new FCmpInst(PredVal, LHS, RHS);
+      } else {
+        if (!CmpInst::isIntPredicate(PredVal))
+          return error("Invalid icmp predicate");
+        I = new ICmpInst(PredVal, LHS, RHS);
+      }
 
       ResTypeID = getVirtualTypeID(I->getType()->getScalarType());
       if (LHS->getType()->isVectorTy())
-- 
GitLab


From 2460bf2facd1c0208ecda68c427a256710246dbb Mon Sep 17 00:00:00 2001
From: Yingchi Long <i@lyc.dev>
Date: Mon, 11 Dec 2023 19:58:34 +0800
Subject: [PATCH 109/349] [BPF][GlobalISel] add initial gisel support for BPF
 (#74999)

This adds initial codegen support for BPF backend.

Only implemented ir-translator for "RET" (but not support isel).

Depends on: #74998
---
 llvm/lib/Target/BPF/BPF.h                     |  7 ++
 llvm/lib/Target/BPF/BPF.td                    |  1 +
 llvm/lib/Target/BPF/BPFSubtarget.cpp          | 28 ++++++
 llvm/lib/Target/BPF/BPFSubtarget.h            | 17 +++-
 llvm/lib/Target/BPF/BPFTargetMachine.cpp      | 31 +++++++
 llvm/lib/Target/BPF/CMakeLists.txt            |  7 ++
 llvm/lib/Target/BPF/GISel/BPFCallLowering.cpp | 46 ++++++++++
 llvm/lib/Target/BPF/GISel/BPFCallLowering.h   | 39 ++++++++
 .../BPF/GISel/BPFInstructionSelector.cpp      | 91 +++++++++++++++++++
 .../lib/Target/BPF/GISel/BPFLegalizerInfo.cpp | 22 +++++
 llvm/lib/Target/BPF/GISel/BPFLegalizerInfo.h  | 28 ++++++
 .../Target/BPF/GISel/BPFRegisterBankInfo.cpp  | 25 +++++
 .../Target/BPF/GISel/BPFRegisterBankInfo.h    | 39 ++++++++
 llvm/lib/Target/BPF/GISel/BPFRegisterBanks.td | 15 +++
 .../Target/BPF/MCTargetDesc/BPFMCTargetDesc.h |  5 +-
 .../BPF/GlobalISel/ir-translator-ret.ll       |  7 ++
 16 files changed, 404 insertions(+), 4 deletions(-)
 create mode 100644 llvm/lib/Target/BPF/GISel/BPFCallLowering.cpp
 create mode 100644 llvm/lib/Target/BPF/GISel/BPFCallLowering.h
 create mode 100644 llvm/lib/Target/BPF/GISel/BPFInstructionSelector.cpp
 create mode 100644 llvm/lib/Target/BPF/GISel/BPFLegalizerInfo.cpp
 create mode 100644 llvm/lib/Target/BPF/GISel/BPFLegalizerInfo.h
 create mode 100644 llvm/lib/Target/BPF/GISel/BPFRegisterBankInfo.cpp
 create mode 100644 llvm/lib/Target/BPF/GISel/BPFRegisterBankInfo.h
 create mode 100644 llvm/lib/Target/BPF/GISel/BPFRegisterBanks.td
 create mode 100644 llvm/test/CodeGen/BPF/GlobalISel/ir-translator-ret.ll

diff --git a/llvm/lib/Target/BPF/BPF.h b/llvm/lib/Target/BPF/BPF.h
index 436cd62c2581..5c77d183e1ef 100644
--- a/llvm/lib/Target/BPF/BPF.h
+++ b/llvm/lib/Target/BPF/BPF.h
@@ -16,7 +16,10 @@
 #include "llvm/Target/TargetMachine.h"
 
 namespace llvm {
+class BPFRegisterBankInfo;
+class BPFSubtarget;
 class BPFTargetMachine;
+class InstructionSelector;
 class PassRegistry;
 
 ModulePass *createBPFCheckAndAdjustIR();
@@ -27,6 +30,10 @@ FunctionPass *createBPFMIPeepholePass();
 FunctionPass *createBPFMIPreEmitPeepholePass();
 FunctionPass *createBPFMIPreEmitCheckingPass();
 
+InstructionSelector *createBPFInstructionSelector(const BPFTargetMachine &,
+                                                  const BPFSubtarget &,
+                                                  const BPFRegisterBankInfo &);
+
 void initializeBPFCheckAndAdjustIRPass(PassRegistry&);
 void initializeBPFDAGToDAGISelPass(PassRegistry &);
 void initializeBPFMIPeepholePass(PassRegistry &);
diff --git a/llvm/lib/Target/BPF/BPF.td b/llvm/lib/Target/BPF/BPF.td
index 7f38fbdd8c5c..dff76ca07af5 100644
--- a/llvm/lib/Target/BPF/BPF.td
+++ b/llvm/lib/Target/BPF/BPF.td
@@ -11,6 +11,7 @@ include "llvm/Target/Target.td"
 include "BPFRegisterInfo.td"
 include "BPFCallingConv.td"
 include "BPFInstrInfo.td"
+include "GISel/BPFRegisterBanks.td"
 
 def BPFInstrInfo : InstrInfo;
 
diff --git a/llvm/lib/Target/BPF/BPFSubtarget.cpp b/llvm/lib/Target/BPF/BPFSubtarget.cpp
index 5e79142ea9e1..9a8e42f32371 100644
--- a/llvm/lib/Target/BPF/BPFSubtarget.cpp
+++ b/llvm/lib/Target/BPF/BPFSubtarget.cpp
@@ -12,6 +12,10 @@
 
 #include "BPFSubtarget.h"
 #include "BPF.h"
+#include "BPFTargetMachine.h"
+#include "GISel/BPFCallLowering.h"
+#include "GISel/BPFLegalizerInfo.h"
+#include "GISel/BPFRegisterBankInfo.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/TargetParser/Host.h"
 
@@ -95,4 +99,28 @@ BPFSubtarget::BPFSubtarget(const Triple &TT, const std::string &CPU,
       FrameLowering(initializeSubtargetDependencies(CPU, FS)),
       TLInfo(TM, *this) {
   IsLittleEndian = TT.isLittleEndian();
+
+  CallLoweringInfo.reset(new BPFCallLowering(*getTargetLowering()));
+  Legalizer.reset(new BPFLegalizerInfo(*this));
+  auto *RBI = new BPFRegisterBankInfo(*getRegisterInfo());
+  RegBankInfo.reset(RBI);
+
+  InstSelector.reset(createBPFInstructionSelector(
+      *static_cast<const BPFTargetMachine *>(&TM), *this, *RBI));
+}
+
+const CallLowering *BPFSubtarget::getCallLowering() const {
+  return CallLoweringInfo.get();
+}
+
+InstructionSelector *BPFSubtarget::getInstructionSelector() const {
+  return InstSelector.get();
+}
+
+const LegalizerInfo *BPFSubtarget::getLegalizerInfo() const {
+  return Legalizer.get();
+}
+
+const RegisterBankInfo *BPFSubtarget::getRegBankInfo() const {
+  return RegBankInfo.get();
 }
diff --git a/llvm/lib/Target/BPF/BPFSubtarget.h b/llvm/lib/Target/BPF/BPFSubtarget.h
index a55ae618f4d1..33747546eadc 100644
--- a/llvm/lib/Target/BPF/BPFSubtarget.h
+++ b/llvm/lib/Target/BPF/BPFSubtarget.h
@@ -16,7 +16,12 @@
 #include "BPFFrameLowering.h"
 #include "BPFISelLowering.h"
 #include "BPFInstrInfo.h"
+#include "BPFRegisterInfo.h"
 #include "BPFSelectionDAGInfo.h"
+#include "llvm/CodeGen/GlobalISel/CallLowering.h"
+#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
+#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
+#include "llvm/CodeGen/RegisterBankInfo.h"
 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/IR/DataLayout.h"
@@ -61,6 +66,11 @@ protected:
   // whether cpu v4 insns are enabled.
   bool HasLdsx, HasMovsx, HasBswap, HasSdivSmod, HasGotol, HasStoreImm;
 
+  std::unique_ptr<CallLowering> CallLoweringInfo;
+  std::unique_ptr<InstructionSelector> InstSelector;
+  std::unique_ptr<LegalizerInfo> Legalizer;
+  std::unique_ptr<RegisterBankInfo> RegBankInfo;
+
 public:
   // This constructor initializes the data members to match that
   // of the specified triple.
@@ -95,9 +105,14 @@ public:
   const BPFSelectionDAGInfo *getSelectionDAGInfo() const override {
     return &TSInfo;
   }
-  const TargetRegisterInfo *getRegisterInfo() const override {
+  const BPFRegisterInfo *getRegisterInfo() const override {
     return &InstrInfo.getRegisterInfo();
   }
+
+  const CallLowering *getCallLowering() const override;
+  InstructionSelector *getInstructionSelector() const override;
+  const LegalizerInfo *getLegalizerInfo() const override;
+  const RegisterBankInfo *getRegBankInfo() const override;
 };
 } // End llvm namespace
 
diff --git a/llvm/lib/Target/BPF/BPFTargetMachine.cpp b/llvm/lib/Target/BPF/BPFTargetMachine.cpp
index 65286c822c4b..ab0db576f7f7 100644
--- a/llvm/lib/Target/BPF/BPFTargetMachine.cpp
+++ b/llvm/lib/Target/BPF/BPFTargetMachine.cpp
@@ -15,10 +15,15 @@
 #include "BPFTargetTransformInfo.h"
 #include "MCTargetDesc/BPFMCAsmInfo.h"
 #include "TargetInfo/BPFTargetInfo.h"
+#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
+#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
+#include "llvm/CodeGen/GlobalISel/Legalizer.h"
+#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/IR/PassManager.h"
+#include "llvm/InitializePasses.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Passes/PassBuilder.h"
 #include "llvm/Support/FormattedStream.h"
@@ -40,6 +45,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeBPFTarget() {
   RegisterTargetMachine<BPFTargetMachine> Z(getTheBPFTarget());
 
   PassRegistry &PR = *PassRegistry::getPassRegistry();
+  initializeGlobalISel(PR);
   initializeBPFCheckAndAdjustIRPass(PR);
   initializeBPFMIPeepholePass(PR);
   initializeBPFDAGToDAGISelPass(PR);
@@ -90,6 +96,11 @@ public:
   bool addInstSelector() override;
   void addMachineSSAOptimization() override;
   void addPreEmitPass() override;
+
+  bool addIRTranslator() override;
+  bool addLegalizeMachineIR() override;
+  bool addRegBankSelect() override;
+  bool addGlobalInstructionSelect() override;
 };
 }
 
@@ -174,3 +185,23 @@ void BPFPassConfig::addPreEmitPass() {
     if (!DisableMIPeephole)
       addPass(createBPFMIPreEmitPeepholePass());
 }
+
+bool BPFPassConfig::addIRTranslator() {
+  addPass(new IRTranslator());
+  return false;
+}
+
+bool BPFPassConfig::addLegalizeMachineIR() {
+  addPass(new Legalizer());
+  return false;
+}
+
+bool BPFPassConfig::addRegBankSelect() {
+  addPass(new RegBankSelect());
+  return false;
+}
+
+bool BPFPassConfig::addGlobalInstructionSelect() {
+  addPass(new InstructionSelect(getOptLevel()));
+  return false;
+}
diff --git a/llvm/lib/Target/BPF/CMakeLists.txt b/llvm/lib/Target/BPF/CMakeLists.txt
index 6a96394a6aee..d88e7ade40b9 100644
--- a/llvm/lib/Target/BPF/CMakeLists.txt
+++ b/llvm/lib/Target/BPF/CMakeLists.txt
@@ -11,10 +11,16 @@ tablegen(LLVM BPFGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM BPFGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM BPFGenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM BPFGenSubtargetInfo.inc -gen-subtarget)
+tablegen(LLVM BPFGenGlobalISel.inc -gen-global-isel)
+tablegen(LLVM BPFGenRegisterBank.inc -gen-register-bank)
 
 add_public_tablegen_target(BPFCommonTableGen)
 
 add_llvm_target(BPFCodeGen
+  GISel/BPFCallLowering.cpp
+  GISel/BPFInstructionSelector.cpp
+  GISel/BPFRegisterBankInfo.cpp
+  GISel/BPFLegalizerInfo.cpp
   BPFAbstractMemberAccess.cpp
   BPFAdjustOpt.cpp
   BPFAsmPrinter.cpp
@@ -44,6 +50,7 @@ add_llvm_target(BPFCodeGen
   CodeGen
   CodeGenTypes
   Core
+  GlobalISel
   IPO
   MC
   Scalar
diff --git a/llvm/lib/Target/BPF/GISel/BPFCallLowering.cpp b/llvm/lib/Target/BPF/GISel/BPFCallLowering.cpp
new file mode 100644
index 000000000000..3829a1a3151f
--- /dev/null
+++ b/llvm/lib/Target/BPF/GISel/BPFCallLowering.cpp
@@ -0,0 +1,46 @@
+//===-- BPFCallLowering.cpp - Call lowering for GlobalISel ------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// This file implements the lowering of LLVM calls to machine code calls for
+/// GlobalISel.
+///
+//===----------------------------------------------------------------------===//
+
+#include "BPFCallLowering.h"
+#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
+#include "llvm/Support/Debug.h"
+
+#define DEBUG_TYPE "bpf-call-lowering"
+
+using namespace llvm;
+
+BPFCallLowering::BPFCallLowering(const BPFTargetLowering &TLI)
+    : CallLowering(&TLI) {}
+
+bool BPFCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
+                                  const Value *Val, ArrayRef<Register> VRegs,
+                                  FunctionLoweringInfo &FLI,
+                                  Register SwiftErrorVReg) const {
+  if (!VRegs.empty())
+    return false;
+  MIRBuilder.buildInstr(BPF::RET);
+  return true;
+}
+
+bool BPFCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
+                                           const Function &F,
+                                           ArrayRef<ArrayRef<Register>> VRegs,
+                                           FunctionLoweringInfo &FLI) const {
+  return VRegs.empty();
+}
+
+bool BPFCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
+                                CallLoweringInfo &Info) const {
+  return false;
+}
diff --git a/llvm/lib/Target/BPF/GISel/BPFCallLowering.h b/llvm/lib/Target/BPF/GISel/BPFCallLowering.h
new file mode 100644
index 000000000000..0099d2048fe5
--- /dev/null
+++ b/llvm/lib/Target/BPF/GISel/BPFCallLowering.h
@@ -0,0 +1,39 @@
+//===-- BPFCallLowering.h - Call lowering for GlobalISel --------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// This file describes how to lower LLVM calls to machine code calls.
+///
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_BPF_GISEL_BPFCALLLOWERING_H
+#define LLVM_LIB_TARGET_BPF_GISEL_BPFCALLLOWERING_H
+
+#include "BPFISelLowering.h"
+#include "llvm/CodeGen/GlobalISel/CallLowering.h"
+#include "llvm/IR/CallingConv.h"
+
+namespace llvm {
+
+class BPFTargetLowering;
+
+class BPFCallLowering : public CallLowering {
+public:
+  BPFCallLowering(const BPFTargetLowering &TLI);
+  bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
+                   ArrayRef<Register> VRegs, FunctionLoweringInfo &FLI,
+                   Register SwiftErrorVReg) const override;
+  bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
+                            ArrayRef<ArrayRef<Register>> VRegs,
+                            FunctionLoweringInfo &FLI) const override;
+  bool lowerCall(MachineIRBuilder &MIRBuilder,
+                 CallLoweringInfo &Info) const override;
+};
+} // namespace llvm
+
+#endif
diff --git a/llvm/lib/Target/BPF/GISel/BPFInstructionSelector.cpp b/llvm/lib/Target/BPF/GISel/BPFInstructionSelector.cpp
new file mode 100644
index 000000000000..1effeb7a57b1
--- /dev/null
+++ b/llvm/lib/Target/BPF/GISel/BPFInstructionSelector.cpp
@@ -0,0 +1,91 @@
+//===- BPFInstructionSelector.cpp --------------------------------*- C++ -*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+/// \file
+/// This file implements the targeting of the InstructionSelector class for BPF.
+//===----------------------------------------------------------------------===//
+
+#include "BPFInstrInfo.h"
+#include "BPFRegisterBankInfo.h"
+#include "BPFSubtarget.h"
+#include "BPFTargetMachine.h"
+#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
+#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
+#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/IR/IntrinsicsBPF.h"
+#include "llvm/Support/Debug.h"
+
+#define DEBUG_TYPE "bpf-gisel"
+
+using namespace llvm;
+
+namespace {
+
+#define GET_GLOBALISEL_PREDICATE_BITSET
+#include "BPFGenGlobalISel.inc"
+#undef GET_GLOBALISEL_PREDICATE_BITSET
+
+class BPFInstructionSelector : public InstructionSelector {
+public:
+  BPFInstructionSelector(const BPFTargetMachine &TM, const BPFSubtarget &STI,
+                         const BPFRegisterBankInfo &RBI);
+
+  bool select(MachineInstr &I) override;
+  static const char *getName() { return DEBUG_TYPE; }
+
+private:
+  /// tblgen generated 'select' implementation that is used as the initial
+  /// selector for the patterns that do not require complex C++.
+  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
+
+  const BPFInstrInfo &TII;
+  const BPFRegisterInfo &TRI;
+  const BPFRegisterBankInfo &RBI;
+
+#define GET_GLOBALISEL_PREDICATES_DECL
+#include "BPFGenGlobalISel.inc"
+#undef GET_GLOBALISEL_PREDICATES_DECL
+
+#define GET_GLOBALISEL_TEMPORARIES_DECL
+#include "BPFGenGlobalISel.inc"
+#undef GET_GLOBALISEL_TEMPORARIES_DECL
+};
+
+} // namespace
+
+#define GET_GLOBALISEL_IMPL
+#include "BPFGenGlobalISel.inc"
+#undef GET_GLOBALISEL_IMPL
+
+BPFInstructionSelector::BPFInstructionSelector(const BPFTargetMachine &TM,
+                                               const BPFSubtarget &STI,
+                                               const BPFRegisterBankInfo &RBI)
+    : TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI),
+#define GET_GLOBALISEL_PREDICATES_INIT
+#include "BPFGenGlobalISel.inc"
+#undef GET_GLOBALISEL_PREDICATES_INIT
+#define GET_GLOBALISEL_TEMPORARIES_INIT
+#include "BPFGenGlobalISel.inc"
+#undef GET_GLOBALISEL_TEMPORARIES_INIT
+{
+}
+
+bool BPFInstructionSelector::select(MachineInstr &I) {
+  if (selectImpl(I, *CoverageInfo))
+    return true;
+  return false;
+}
+
+namespace llvm {
+InstructionSelector *
+createBPFInstructionSelector(const BPFTargetMachine &TM,
+                             const BPFSubtarget &Subtarget,
+                             const BPFRegisterBankInfo &RBI) {
+  return new BPFInstructionSelector(TM, Subtarget, RBI);
+}
+} // namespace llvm
diff --git a/llvm/lib/Target/BPF/GISel/BPFLegalizerInfo.cpp b/llvm/lib/Target/BPF/GISel/BPFLegalizerInfo.cpp
new file mode 100644
index 000000000000..04220c176376
--- /dev/null
+++ b/llvm/lib/Target/BPF/GISel/BPFLegalizerInfo.cpp
@@ -0,0 +1,22 @@
+//===- BPFLegalizerInfo.h ----------------------------------------*- C++ -*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+/// \file
+/// This file implements the targeting of the Machinelegalizer class for BPF
+//===----------------------------------------------------------------------===//
+
+#include "BPFLegalizerInfo.h"
+#include "llvm/Support/Debug.h"
+
+#define DEBUG_TYPE "bpf-legalinfo"
+
+using namespace llvm;
+using namespace LegalizeActions;
+
+BPFLegalizerInfo::BPFLegalizerInfo(const BPFSubtarget &ST) {
+  getLegacyLegalizerInfo().computeTables();
+}
diff --git a/llvm/lib/Target/BPF/GISel/BPFLegalizerInfo.h b/llvm/lib/Target/BPF/GISel/BPFLegalizerInfo.h
new file mode 100644
index 000000000000..1704bc03144c
--- /dev/null
+++ b/llvm/lib/Target/BPF/GISel/BPFLegalizerInfo.h
@@ -0,0 +1,28 @@
+//===- BPFLegalizerInfo.h ----------------------------------------*- C++ -*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+/// \file
+/// This file declares the targeting of the Machinelegalizer class for BPF
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_BPF_GISEL_BPFMACHINELEGALIZER_H
+#define LLVM_LIB_TARGET_BPF_GISEL_BPFMACHINELEGALIZER_H
+
+#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
+
+namespace llvm {
+
+class BPFSubtarget;
+
+/// This class provides the information for the BPF target legalizer for
+/// GlobalISel.
+class BPFLegalizerInfo : public LegalizerInfo {
+public:
+  BPFLegalizerInfo(const BPFSubtarget &ST);
+};
+} // namespace llvm
+#endif
diff --git a/llvm/lib/Target/BPF/GISel/BPFRegisterBankInfo.cpp b/llvm/lib/Target/BPF/GISel/BPFRegisterBankInfo.cpp
new file mode 100644
index 000000000000..f50e8f524a87
--- /dev/null
+++ b/llvm/lib/Target/BPF/GISel/BPFRegisterBankInfo.cpp
@@ -0,0 +1,25 @@
+//===- BPFRegisterBankInfo.cpp --------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+/// \file
+/// This file implements the targeting of the RegisterBankInfo class for BPF
+//===----------------------------------------------------------------------===//
+
+#include "BPFRegisterBankInfo.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/Support/Debug.h"
+
+#define DEBUG_TYPE "bpf-reg-bank-info"
+
+#define GET_TARGET_REGBANK_IMPL
+#include "BPFGenRegisterBank.inc"
+
+using namespace llvm;
+
+BPFRegisterBankInfo::BPFRegisterBankInfo(const TargetRegisterInfo &TRI)
+    : BPFGenRegisterBankInfo() {}
diff --git a/llvm/lib/Target/BPF/GISel/BPFRegisterBankInfo.h b/llvm/lib/Target/BPF/GISel/BPFRegisterBankInfo.h
new file mode 100644
index 000000000000..82421916ca5e
--- /dev/null
+++ b/llvm/lib/Target/BPF/GISel/BPFRegisterBankInfo.h
@@ -0,0 +1,39 @@
+//===-- BPFRegisterBankInfo.h -----------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// This file declares the targeting of the RegisterBankInfo class for BPF.
+///
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_BPF_GISEL_BPFREGISTERBANKINFO_H
+#define LLVM_LIB_TARGET_BPF_GISEL_BPFREGISTERBANKINFO_H
+
+#include "MCTargetDesc/BPFMCTargetDesc.h"
+#include "llvm/CodeGen/RegisterBankInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+
+#define GET_REGBANK_DECLARATIONS
+#include "BPFGenRegisterBank.inc"
+
+namespace llvm {
+class TargetRegisterInfo;
+
+class BPFGenRegisterBankInfo : public RegisterBankInfo {
+protected:
+#define GET_TARGET_REGBANK_CLASS
+#include "BPFGenRegisterBank.inc"
+};
+
+class BPFRegisterBankInfo final : public BPFGenRegisterBankInfo {
+public:
+  BPFRegisterBankInfo(const TargetRegisterInfo &TRI);
+};
+} // namespace llvm
+
+#endif
diff --git a/llvm/lib/Target/BPF/GISel/BPFRegisterBanks.td b/llvm/lib/Target/BPF/GISel/BPFRegisterBanks.td
new file mode 100644
index 000000000000..af4af40a2537
--- /dev/null
+++ b/llvm/lib/Target/BPF/GISel/BPFRegisterBanks.td
@@ -0,0 +1,15 @@
+//===-- BPFRegisterBanks.td - Describe the BPF Banks -------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// Define the BPF register banks used for GlobalISel.
+///
+//===----------------------------------------------------------------------===//
+
+/// General Purpose Registers
+def GPRRegBank : RegisterBank<"GPRB", [GPR]>;
diff --git a/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h b/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h
index ea30e714a5b7..f12b79586baf 100644
--- a/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h
+++ b/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h
@@ -30,8 +30,7 @@ class MCSubtargetInfo;
 class MCTargetOptions;
 class Target;
 
-MCCodeEmitter *createBPFMCCodeEmitter(const MCInstrInfo &MCII,
-                                      MCContext &Ctx);
+MCCodeEmitter *createBPFMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx);
 MCCodeEmitter *createBPFbeMCCodeEmitter(const MCInstrInfo &MCII,
                                         MCContext &Ctx);
 
@@ -43,7 +42,7 @@ MCAsmBackend *createBPFbeAsmBackend(const Target &T, const MCSubtargetInfo &STI,
                                     const MCTargetOptions &Options);
 
 std::unique_ptr<MCObjectTargetWriter> createBPFELFObjectWriter(uint8_t OSABI);
-}
+} // namespace llvm
 
 // Defines symbolic names for BPF registers.  This defines a mapping from
 // register name to register number.
diff --git a/llvm/test/CodeGen/BPF/GlobalISel/ir-translator-ret.ll b/llvm/test/CodeGen/BPF/GlobalISel/ir-translator-ret.ll
new file mode 100644
index 000000000000..7a014f7841fc
--- /dev/null
+++ b/llvm/test/CodeGen/BPF/GlobalISel/ir-translator-ret.ll
@@ -0,0 +1,7 @@
+; RUN: llc -mtriple=bpfel -global-isel -verify-machineinstrs -stop-after=irtranslator < %s | FileCheck %s
+
+; CHECK: name: f
+; CHECK: RET
+define void @f() {
+  ret void
+}
-- 
GitLab


From ae7bffd71c44c8fa21b91e62da22e4d9272b0193 Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Mon, 11 Dec 2023 13:06:36 +0100
Subject: [PATCH 110/349] [InstCombine] Don't create unnecessary zero-index GEP
 (NFCI)

Note needed with opaque pointers.
---
 .../InstCombineLoadStoreAlloca.cpp            | 22 +------------------
 1 file changed, 1 insertion(+), 21 deletions(-)

diff --git a/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp b/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
index b72b68c68d98..f8fae773e476 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
@@ -215,27 +215,7 @@ static Instruction *simplifyAllocaArraySize(InstCombinerImpl &IC,
       New->setAlignment(AI.getAlign());
 
       replaceAllDbgUsesWith(AI, *New, *New, DT);
-
-      // Scan to the end of the allocation instructions, to skip over a block of
-      // allocas if possible...also skip interleaved debug info
-      //
-      BasicBlock::iterator It(New);
-      while (isa<AllocaInst>(*It) || isa<DbgInfoIntrinsic>(*It))
-        ++It;
-
-      // Now that I is pointing to the first non-allocation-inst in the block,
-      // insert our getelementptr instruction...
-      //
-      Type *IdxTy = IC.getDataLayout().getIndexType(AI.getType());
-      Value *NullIdx = Constant::getNullValue(IdxTy);
-      Value *Idx[2] = {NullIdx, NullIdx};
-      Instruction *GEP = GetElementPtrInst::CreateInBounds(
-          NewTy, New, Idx, New->getName() + ".sub");
-      IC.InsertNewInstBefore(GEP, It);
-
-      // Now make everything use the getelementptr instead of the original
-      // allocation.
-      return IC.replaceInstUsesWith(AI, GEP);
+      return IC.replaceInstUsesWith(AI, New);
     }
   }
 
-- 
GitLab


From 5d5583979179e3b0702888adf188b10831037758 Mon Sep 17 00:00:00 2001
From: Orlando Cazalet-Hyams <orlando.hyams@sony.com>
Date: Mon, 11 Dec 2023 12:23:26 +0000
Subject: [PATCH 111/349] [AssignmentTracking] Skip large types in redundant
 debug info pruning (#74329)

Fix https://github.com/llvm/llvm-project/issues/74189 (crash report).

The pruning code uses a BitVector to track which parts of a variable have been
defined in order to find redundant debug records. BitVector uses a u32 to track
size; variable of types with a bit-size greater than max(u32) ish* can't be
represented using a BitVector.

Fix the assertion by introducing a limit on type size. Improve performance by
bringing the limit down to a sensible number and tracking byte-sizes instead
of bit-sizes.

Skipping variables in this pruning code doesn't cause debug info correctness
issues; it just means there may be some extra redundant debug records.

(*) `max(u32) - 63` due to BitVector::NumBitWords implementation.
---
 .../CodeGen/AssignmentTrackingAnalysis.cpp    | 27 +++++----
 .../assignment-tracking/X86/large-type.ll     | 58 +++++++++++++++++++
 2 files changed, 75 insertions(+), 10 deletions(-)
 create mode 100644 llvm/test/DebugInfo/assignment-tracking/X86/large-type.ll

diff --git a/llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp b/llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp
index f00528023c91..ad3ad9928987 100644
--- a/llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp
+++ b/llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp
@@ -2269,14 +2269,14 @@ static bool
 removeRedundantDbgLocsUsingBackwardScan(const BasicBlock *BB,
                                         FunctionVarLocsBuilder &FnVarLocs) {
   bool Changed = false;
-  SmallDenseMap<DebugAggregate, BitVector> VariableDefinedBits;
+  SmallDenseMap<DebugAggregate, BitVector> VariableDefinedBytes;
   // Scan over the entire block, not just over the instructions mapped by
   // FnVarLocs, because wedges in FnVarLocs may only be seperated by debug
   // instructions.
   for (const Instruction &I : reverse(*BB)) {
     if (!isa<DbgVariableIntrinsic>(I)) {
       // Sequence of consecutive defs ended. Clear map for the next one.
-      VariableDefinedBits.clear();
+      VariableDefinedBytes.clear();
     }
 
     // Get the location defs that start just before this instruction.
@@ -2295,9 +2295,15 @@ removeRedundantDbgLocsUsingBackwardScan(const BasicBlock *BB,
       DebugAggregate Aggr =
           getAggregate(FnVarLocs.getVariable(RIt->VariableID));
       uint64_t SizeInBits = Aggr.first->getSizeInBits().value_or(0);
+      uint64_t SizeInBytes = divideCeil(SizeInBits, 8);
 
-      if (SizeInBits == 0) {
+      // Cutoff for large variables to prevent expensive bitvector operations.
+      const uint64_t MaxSizeBytes = 2048;
+
+      if (SizeInBytes == 0 || SizeInBytes > MaxSizeBytes) {
         // If the size is unknown (0) then keep this location def to be safe.
+        // Do the same for defs of large variables, which would be expensive
+        // to represent with a BitVector.
         NewDefsReversed.push_back(*RIt);
         continue;
       }
@@ -2305,23 +2311,24 @@ removeRedundantDbgLocsUsingBackwardScan(const BasicBlock *BB,
       // Only keep this location definition if it is not fully eclipsed by
       // other definitions in this wedge that come after it
 
-      // Inert the bits the location definition defines.
+      // Inert the bytes the location definition defines.
       auto InsertResult =
-          VariableDefinedBits.try_emplace(Aggr, BitVector(SizeInBits));
+          VariableDefinedBytes.try_emplace(Aggr, BitVector(SizeInBytes));
       bool FirstDefinition = InsertResult.second;
-      BitVector &DefinedBits = InsertResult.first->second;
+      BitVector &DefinedBytes = InsertResult.first->second;
 
       DIExpression::FragmentInfo Fragment =
           RIt->Expr->getFragmentInfo().value_or(
               DIExpression::FragmentInfo(SizeInBits, 0));
       bool InvalidFragment = Fragment.endInBits() > SizeInBits;
+      uint64_t StartInBytes = Fragment.startInBits() / 8;
+      uint64_t EndInBytes = divideCeil(Fragment.endInBits(), 8);
 
-      // If this defines any previously undefined bits, keep it.
+      // If this defines any previously undefined bytes, keep it.
       if (FirstDefinition || InvalidFragment ||
-          DefinedBits.find_first_unset_in(Fragment.startInBits(),
-                                          Fragment.endInBits()) != -1) {
+          DefinedBytes.find_first_unset_in(StartInBytes, EndInBytes) != -1) {
         if (!InvalidFragment)
-          DefinedBits.set(Fragment.startInBits(), Fragment.endInBits());
+          DefinedBytes.set(StartInBytes, EndInBytes);
         NewDefsReversed.push_back(*RIt);
         continue;
       }
diff --git a/llvm/test/DebugInfo/assignment-tracking/X86/large-type.ll b/llvm/test/DebugInfo/assignment-tracking/X86/large-type.ll
new file mode 100644
index 000000000000..cebbc162fcb3
--- /dev/null
+++ b/llvm/test/DebugInfo/assignment-tracking/X86/large-type.ll
@@ -0,0 +1,58 @@
+; RUN: llc %s -stop-after=finalize-isel -o - \
+; RUN: | FileCheck %s --implicit-check-not=DBG_
+
+;; Based on optimized IR from C source:
+;; int main () {
+;;   char a1[__INT_MAX__];
+;;   a1[__INT_MAX__ - 1] = 5;
+;;   return a1[__INT_MAX__ - 1];
+;; }
+;;
+;; Check extremely large types don't cause a crash.
+; CHECK: DBG_VALUE 5, $noreg, ![[#]], !DIExpression(DW_OP_LLVM_fragment, 4294967280, 8)
+; CHECK: DBG_VALUE 6, $noreg, ![[#]], !DIExpression(DW_OP_LLVM_fragment, 0, 8)
+; CHECK: DBG_VALUE 7, $noreg, ![[#]], !DIExpression(DW_OP_LLVM_fragment, 0, 8)
+
+define dso_local i32 @main() local_unnamed_addr !dbg !10 {
+entry:
+;; FIXME: SROA currently creates incorrect fragments if bit_offset > max(u32),
+;; with and without assignment-tracking.
+  tail call void @llvm.dbg.value(metadata i8 5, metadata !15, metadata !DIExpression(DW_OP_LLVM_fragment, 4294967280, 8)), !dbg !20
+;; These two were inserted by hand.
+  tail call void @llvm.dbg.value(metadata i8 6, metadata !22, metadata !DIExpression(DW_OP_LLVM_fragment, 0, 8)), !dbg !20
+  tail call void @llvm.dbg.value(metadata i8 7, metadata !23, metadata !DIExpression(DW_OP_LLVM_fragment, 0, 8)), !dbg !20
+  ret i32 5, !dbg !21
+}
+
+declare void @llvm.dbg.value(metadata, metadata, metadata)
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!2, !3, !4, !5, !6, !7, !8}
+!llvm.ident = !{!9}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang version 18.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None)
+!1 = !DIFile(filename: "test.c", directory: "/")
+!2 = !{i32 7, !"Dwarf Version", i32 5}
+!3 = !{i32 2, !"Debug Info Version", i32 3}
+!4 = !{i32 1, !"wchar_size", i32 4}
+!5 = !{i32 8, !"PIC Level", i32 2}
+!6 = !{i32 7, !"PIE Level", i32 2}
+!7 = !{i32 7, !"uwtable", i32 2}
+!8 = !{i32 7, !"debug-info-assignment-tracking", i1 true}
+!9 = !{!"clang version 18.0.0"}
+!10 = distinct !DISubprogram(name: "main", scope: !1, file: !1, line: 3, type: !11, scopeLine: 4, flags: DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !14)
+!11 = !DISubroutineType(types: !12)
+!12 = !{!13}
+!13 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
+!14 = !{!15}
+!15 = !DILocalVariable(name: "a1", scope: !10, file: !1, line: 5, type: !16)
+!16 = !DICompositeType(tag: DW_TAG_array_type, baseType: !17, size: 17179869176, elements: !18)
+!17 = !DIBasicType(name: "char", size: 8, encoding: DW_ATE_signed_char)
+!18 = !{!19}
+!19 = !DISubrange(count: 2147483647)
+!20 = !DILocation(line: 0, scope: !10)
+!21 = !DILocation(line: 7, column: 3, scope: !10)
+!22 = !DILocalVariable(name: "a2", scope: !10, file: !1, line: 5, type: !16)
+!23 = !DILocalVariable(name: "a3", scope: !10, file: !1, line: 5, type: !16)
+!24 = !DICompositeType(tag: DW_TAG_array_type, baseType: !17, size: 4294967232, elements: !18)
+!25 = !DICompositeType(tag: DW_TAG_array_type, baseType: !17, size: 4294967233, elements: !18)
-- 
GitLab


From 19918ac34dc5d304ec6ad413ceae1d4394abe28f Mon Sep 17 00:00:00 2001
From: Florian Hahn <flo@fhahn.com>
Date: Mon, 11 Dec 2023 12:26:28 +0000
Subject: [PATCH 112/349] [VPlan] Mark Select VPInstructions as not having
 sideeffects.

Select VPInstructions don't have sideeffects, mark them accordingly.
---
 llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp             | 1 +
 llvm/test/Transforms/LoopVectorize/reduction-small-size.ll | 5 +----
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
index c23428e2ba34..ffdeea80fa07 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
@@ -118,6 +118,7 @@ bool VPRecipeBase::mayHaveSideEffects() const {
   case VPInstructionSC:
     switch (cast<VPInstruction>(this)->getOpcode()) {
     case Instruction::ICmp:
+    case Instruction::Select:
     case VPInstruction::Not:
     case VPInstruction::CalculateTripCountMinusVF:
     case VPInstruction::CanonicalIVIncrementForPart:
diff --git a/llvm/test/Transforms/LoopVectorize/reduction-small-size.ll b/llvm/test/Transforms/LoopVectorize/reduction-small-size.ll
index 3973a288fe71..2a58748d8fb6 100644
--- a/llvm/test/Transforms/LoopVectorize/reduction-small-size.ll
+++ b/llvm/test/Transforms/LoopVectorize/reduction-small-size.ll
@@ -11,15 +11,12 @@ define i8 @PR34687(i1 %c, i32 %x, i32 %n) {
 ; CHECK:       vector.ph:
 ; CHECK-NEXT:    [[N_MOD_VF:%.*]] = urem i32 [[N]], 4
 ; CHECK-NEXT:    [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
-; CHECK-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i1> poison, i1 [[C:%.*]], i64 0
-; CHECK-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i1> [[BROADCAST_SPLATINSERT]], <4 x i1> poison, <4 x i32> zeroinitializer
 ; CHECK-NEXT:    [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i32> poison, i32 [[X:%.*]], i64 0
 ; CHECK-NEXT:    [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT1]], <4 x i32> poison, <4 x i32> zeroinitializer
 ; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
 ; CHECK:       vector.body:
 ; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
 ; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP4:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT:    [[TMP0:%.*]] = select <4 x i1> [[BROADCAST_SPLAT]], <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
 ; CHECK-NEXT:    [[TMP1:%.*]] = and <4 x i32> [[VEC_PHI]], <i32 255, i32 255, i32 255, i32 255>
 ; CHECK-NEXT:    [[TMP2:%.*]] = add <4 x i32> [[TMP1]], [[BROADCAST_SPLAT2]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = trunc <4 x i32> [[TMP2]] to <4 x i8>
@@ -40,7 +37,7 @@ define i8 @PR34687(i1 %c, i32 %x, i32 %n) {
 ; CHECK:       for.body:
 ; CHECK-NEXT:    [[I:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[I_NEXT:%.*]], [[IF_END:%.*]] ]
 ; CHECK-NEXT:    [[R:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[R_NEXT:%.*]], [[IF_END]] ]
-; CHECK-NEXT:    br i1 [[C]], label [[IF_THEN:%.*]], label [[IF_END]]
+; CHECK-NEXT:    br i1 [[C:%.*]], label [[IF_THEN:%.*]], label [[IF_END]]
 ; CHECK:       if.then:
 ; CHECK-NEXT:    [[T0:%.*]] = sdiv i32 undef, undef
 ; CHECK-NEXT:    br label [[IF_END]]
-- 
GitLab


From 50a5f5c1838f8583d050eb15a3b770bb4661910d Mon Sep 17 00:00:00 2001
From: Michael Klemm <michael.klemm@amd.com>
Date: Mon, 11 Dec 2023 13:35:27 +0100
Subject: [PATCH 113/349] [flang][driver] Add -fno-fortran-main (link time)
 option to remove Fortran_main from link line (#74139)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This PR adds the `-fno-fortran-main` command line option to remove
`Fortran_main.a` from the link and to allow for linking Fortran code w/o
program unit with C/C++ translation units that provide the `main()`
entrypoint.

When linking Fortran code with C/C++ code (Fortran calling into C/C++),
PR #73124 introduced a proper error message that would prevent
successful linkage, if there was a program unit from Fortran *and*
`main()` function coming from C/C++. Alas, this caused some breakage of
code that would call Fortran code from C/C++ and rightfully provided the
`main()` entrypoint. Classic Flang had the command-line option
`-fno-fortran-main` to then remove the entrypoints for the Fortran
program unit from the linker stage.

This PR is related to PR #74120 and (merged) PR #73124.

---------

Co-authored-by: Andrzej Warzyński <andrzej.warzynski@gmail.com>
---
 clang/include/clang/Driver/Options.td      |  6 ++
 clang/lib/Driver/ToolChains/CommonArgs.cpp | 92 ++++++++++++----------
 clang/lib/Driver/ToolChains/Flang.cpp      | 14 +++-
 flang/test/Driver/driver-help-hidden.f90   |  1 +
 flang/test/Driver/driver-help.f90          |  1 +
 flang/test/Driver/no-duplicate-main.f90    |  2 +
 6 files changed, 69 insertions(+), 47 deletions(-)

diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td
index b959fd20fe41..cf969cb0b318 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -6354,6 +6354,12 @@ def J : JoinedOrSeparate<["-"], "J">,
   Group<gfortran_Group>,
   Alias<module_dir>;
 
+let Visibility = [FlangOption] in {
+def no_fortran_main : Flag<["-"], "fno-fortran-main">,
+  Visibility<[FlangOption]>, Group<f_Group>,
+  HelpText<"Do not include Fortran_main.a (provided by Flang) when linking">;
+} // let Visibility = [ FlangOption ]
+
 //===----------------------------------------------------------------------===//
 // FC1 Options
 //===----------------------------------------------------------------------===//
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index 51b336216c56..31e7d68161ff 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -1120,55 +1120,61 @@ void tools::addFortranRuntimeLibs(const ToolChain &TC, const ArgList &Args,
                                   llvm::opt::ArgStringList &CmdArgs) {
   // These are handled earlier on Windows by telling the frontend driver to add
   // the correct libraries to link against as dependents in the object file.
-  if (!TC.getTriple().isKnownWindowsMSVCEnvironment()) {
-    // The --whole-archive option needs to be part of the link line to
-    // make sure that the main() function from Fortran_main.a is pulled
-    // in by the linker.  Determine if --whole-archive is active when
-    // flang will try to link Fortran_main.a.  If it is, don't add the
-    // --whole-archive flag to the link line.  If it's not, add a proper
-    // --whole-archive/--no-whole-archive bracket to the link line.
-    bool WholeArchiveActive = false;
-    for (auto *Arg : Args.filtered(options::OPT_Wl_COMMA))
-      if (Arg)
-        for (StringRef ArgValue : Arg->getValues()) {
-          if (ArgValue == "--whole-archive")
-            WholeArchiveActive = true;
-          if (ArgValue == "--no-whole-archive")
-            WholeArchiveActive = false;
-        }
 
-    if (!WholeArchiveActive)
-      CmdArgs.push_back("--whole-archive");
-    CmdArgs.push_back("-lFortran_main");
-    if (!WholeArchiveActive)
-      CmdArgs.push_back("--no-whole-archive");
+  // if -fno-fortran-main has been passed, skip linking Fortran_main.a
+  bool LinkFortranMain = !Args.hasArg(options::OPT_no_fortran_main);
+  if (!TC.getTriple().isKnownWindowsMSVCEnvironment()) {
+    if (LinkFortranMain) {
+      // The --whole-archive option needs to be part of the link line to
+      // make sure that the main() function from Fortran_main.a is pulled
+      // in by the linker.  Determine if --whole-archive is active when
+      // flang will try to link Fortran_main.a.  If it is, don't add the
+      // --whole-archive flag to the link line.  If it's not, add a proper
+      // --whole-archive/--no-whole-archive bracket to the link line.
+      bool WholeArchiveActive = false;
+      for (auto *Arg : Args.filtered(options::OPT_Wl_COMMA))
+        if (Arg)
+          for (StringRef ArgValue : Arg->getValues()) {
+            if (ArgValue == "--whole-archive")
+              WholeArchiveActive = true;
+            if (ArgValue == "--no-whole-archive")
+              WholeArchiveActive = false;
+          }
 
+      if (!WholeArchiveActive)
+        CmdArgs.push_back("--whole-archive");
+      CmdArgs.push_back("-lFortran_main");
+      if (!WholeArchiveActive)
+        CmdArgs.push_back("--no-whole-archive");
+    }
     // Perform regular linkage of the remaining runtime libraries.
     CmdArgs.push_back("-lFortranRuntime");
     CmdArgs.push_back("-lFortranDecimal");
   } else {
-    unsigned RTOptionID = options::OPT__SLASH_MT;
-    if (auto *rtl = Args.getLastArg(options::OPT_fms_runtime_lib_EQ)) {
-      RTOptionID = llvm::StringSwitch<unsigned>(rtl->getValue())
-                       .Case("static", options::OPT__SLASH_MT)
-                       .Case("static_dbg", options::OPT__SLASH_MTd)
-                       .Case("dll", options::OPT__SLASH_MD)
-                       .Case("dll_dbg", options::OPT__SLASH_MDd)
-                       .Default(options::OPT__SLASH_MT);
-    }
-    switch (RTOptionID) {
-    case options::OPT__SLASH_MT:
-      CmdArgs.push_back("/WHOLEARCHIVE:Fortran_main.static.lib");
-      break;
-    case options::OPT__SLASH_MTd:
-      CmdArgs.push_back("/WHOLEARCHIVE:Fortran_main.static_dbg.lib");
-      break;
-    case options::OPT__SLASH_MD:
-      CmdArgs.push_back("/WHOLEARCHIVE:Fortran_main.dynamic.lib");
-      break;
-    case options::OPT__SLASH_MDd:
-      CmdArgs.push_back("/WHOLEARCHIVE:Fortran_main.dynamic_dbg.lib");
-      break;
+    if (LinkFortranMain) {
+      unsigned RTOptionID = options::OPT__SLASH_MT;
+      if (auto *rtl = Args.getLastArg(options::OPT_fms_runtime_lib_EQ)) {
+        RTOptionID = llvm::StringSwitch<unsigned>(rtl->getValue())
+                         .Case("static", options::OPT__SLASH_MT)
+                         .Case("static_dbg", options::OPT__SLASH_MTd)
+                         .Case("dll", options::OPT__SLASH_MD)
+                         .Case("dll_dbg", options::OPT__SLASH_MDd)
+                         .Default(options::OPT__SLASH_MT);
+      }
+      switch (RTOptionID) {
+      case options::OPT__SLASH_MT:
+        CmdArgs.push_back("/WHOLEARCHIVE:Fortran_main.static.lib");
+        break;
+      case options::OPT__SLASH_MTd:
+        CmdArgs.push_back("/WHOLEARCHIVE:Fortran_main.static_dbg.lib");
+        break;
+      case options::OPT__SLASH_MD:
+        CmdArgs.push_back("/WHOLEARCHIVE:Fortran_main.dynamic.lib");
+        break;
+      case options::OPT__SLASH_MDd:
+        CmdArgs.push_back("/WHOLEARCHIVE:Fortran_main.dynamic_dbg.lib");
+        break;
+      }
     }
   }
 }
diff --git a/clang/lib/Driver/ToolChains/Flang.cpp b/clang/lib/Driver/ToolChains/Flang.cpp
index 9b21fe952af7..502b9f17a06c 100644
--- a/clang/lib/Driver/ToolChains/Flang.cpp
+++ b/clang/lib/Driver/ToolChains/Flang.cpp
@@ -231,6 +231,8 @@ static void processVSRuntimeLibrary(const ToolChain &TC, const ArgList &Args,
                                     ArgStringList &CmdArgs) {
   assert(TC.getTriple().isKnownWindowsMSVCEnvironment() &&
          "can only add VS runtime library on Windows!");
+  // if -fno-fortran-main has been passed, skip linking Fortran_main.a
+  bool LinkFortranMain = !Args.hasArg(options::OPT_no_fortran_main);
   if (TC.getTriple().isKnownWindowsMSVCEnvironment()) {
     CmdArgs.push_back(Args.MakeArgString(
         "--dependent-lib=" + TC.getCompilerRTBasename(Args, "builtins")));
@@ -248,7 +250,8 @@ static void processVSRuntimeLibrary(const ToolChain &TC, const ArgList &Args,
   case options::OPT__SLASH_MT:
     CmdArgs.push_back("-D_MT");
     CmdArgs.push_back("--dependent-lib=libcmt");
-    CmdArgs.push_back("--dependent-lib=Fortran_main.static.lib");
+    if (LinkFortranMain)
+      CmdArgs.push_back("--dependent-lib=Fortran_main.static.lib");
     CmdArgs.push_back("--dependent-lib=FortranRuntime.static.lib");
     CmdArgs.push_back("--dependent-lib=FortranDecimal.static.lib");
     break;
@@ -256,7 +259,8 @@ static void processVSRuntimeLibrary(const ToolChain &TC, const ArgList &Args,
     CmdArgs.push_back("-D_MT");
     CmdArgs.push_back("-D_DEBUG");
     CmdArgs.push_back("--dependent-lib=libcmtd");
-    CmdArgs.push_back("--dependent-lib=Fortran_main.static_dbg.lib");
+    if (LinkFortranMain)
+      CmdArgs.push_back("--dependent-lib=Fortran_main.static_dbg.lib");
     CmdArgs.push_back("--dependent-lib=FortranRuntime.static_dbg.lib");
     CmdArgs.push_back("--dependent-lib=FortranDecimal.static_dbg.lib");
     break;
@@ -264,7 +268,8 @@ static void processVSRuntimeLibrary(const ToolChain &TC, const ArgList &Args,
     CmdArgs.push_back("-D_MT");
     CmdArgs.push_back("-D_DLL");
     CmdArgs.push_back("--dependent-lib=msvcrt");
-    CmdArgs.push_back("--dependent-lib=Fortran_main.dynamic.lib");
+    if (LinkFortranMain)
+      CmdArgs.push_back("--dependent-lib=Fortran_main.dynamic.lib");
     CmdArgs.push_back("--dependent-lib=FortranRuntime.dynamic.lib");
     CmdArgs.push_back("--dependent-lib=FortranDecimal.dynamic.lib");
     break;
@@ -273,7 +278,8 @@ static void processVSRuntimeLibrary(const ToolChain &TC, const ArgList &Args,
     CmdArgs.push_back("-D_DEBUG");
     CmdArgs.push_back("-D_DLL");
     CmdArgs.push_back("--dependent-lib=msvcrtd");
-    CmdArgs.push_back("--dependent-lib=Fortran_main.dynamic_dbg.lib");
+    if (LinkFortranMain)
+      CmdArgs.push_back("--dependent-lib=Fortran_main.dynamic_dbg.lib");
     CmdArgs.push_back("--dependent-lib=FortranRuntime.dynamic_dbg.lib");
     CmdArgs.push_back("--dependent-lib=FortranDecimal.dynamic_dbg.lib");
     break;
diff --git a/flang/test/Driver/driver-help-hidden.f90 b/flang/test/Driver/driver-help-hidden.f90
index 8cb8b54d5941..9a11a7a571ff 100644
--- a/flang/test/Driver/driver-help-hidden.f90
+++ b/flang/test/Driver/driver-help-hidden.f90
@@ -64,6 +64,7 @@
 ! CHECK-NEXT:                         Select Windows run-time library
 ! CHECK-NEXT: -fno-automatic          Implies the SAVE attribute for non-automatic local objects in subprograms unless RECURSIVE
 ! CHECK-NEXT: -fno-color-diagnostics  Disable colors in diagnostics
+! CHECK-NEXT: -fno-fortran-main       Do not include Fortran_main.a (provided by Flang) when linking
 ! CHECK-NEXT: -fno-integrated-as      Disable the integrated assembler
 ! CHECK-NEXT: -fno-lto                Disable LTO mode (default)
 ! CHECK-NEXT: -fno-ppc-native-vector-element-order
diff --git a/flang/test/Driver/driver-help.f90 b/flang/test/Driver/driver-help.f90
index 0607ffde2378..e0e74dc56f33 100644
--- a/flang/test/Driver/driver-help.f90
+++ b/flang/test/Driver/driver-help.f90
@@ -54,6 +54,7 @@
 ! HELP-NEXT:                         Select Windows run-time library
 ! HELP-NEXT: -fno-automatic          Implies the SAVE attribute for non-automatic local objects in subprograms unless RECURSIVE
 ! HELP-NEXT: -fno-color-diagnostics  Disable colors in diagnostics
+! HELP-NEXT: -fno-fortran-main       Do not include Fortran_main.a (provided by Flang) when linking
 ! HELP-NEXT: -fno-integrated-as      Disable the integrated assembler
 ! HELP-NEXT: -fno-lto                Disable LTO mode (default)
 ! HELP-NEXT: -fno-ppc-native-vector-element-order
diff --git a/flang/test/Driver/no-duplicate-main.f90 b/flang/test/Driver/no-duplicate-main.f90
index 4e33f4f2aeba..12d5e46247ba 100644
--- a/flang/test/Driver/no-duplicate-main.f90
+++ b/flang/test/Driver/no-duplicate-main.f90
@@ -4,6 +4,8 @@
 ! RUN: %flang -o %t -c %s
 ! RUN: not %flang -o %t.exe %t %t.c-object 2>&1
 
+! RUN: %flang -fno-fortran-main -o %t.exe %t %t.c-object 2>&1
+
 ! TODO: potentially add further checks to ensure that proper
 !       linker error messages are detected and checked via
 !       FileCheck.
-- 
GitLab


From d1c9b37d36dd9739b08d5fd8ce53f47d869388a3 Mon Sep 17 00:00:00 2001
From: LLVM GN Syncbot <llvmgnsyncbot@gmail.com>
Date: Mon, 11 Dec 2023 12:43:54 +0000
Subject: [PATCH 114/349] [gn build] Port 2460bf2facd1

---
 llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn
index 2e5b7e03bd65..668512ecba88 100644
--- a/llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn
@@ -80,6 +80,10 @@ static_library("LLVMBPFCodeGen") {
     "BPFSubtarget.cpp",
     "BPFTargetMachine.cpp",
     "BTFDebug.cpp",
+    "GISel/BPFCallLowering.cpp",
+    "GISel/BPFInstructionSelector.cpp",
+    "GISel/BPFLegalizerInfo.cpp",
+    "GISel/BPFRegisterBankInfo.cpp",
   ]
 }
 
-- 
GitLab


From 2a988a38a0c9aee0855c1ef2a50cecba258a6bc7 Mon Sep 17 00:00:00 2001
From: Benjamin Kramer <benny.kra@googlemail.com>
Date: Mon, 11 Dec 2023 13:56:47 +0100
Subject: [PATCH 115/349] [bazel] Port 2460bf2facd1c0208ecda68c427a256710246dbb

---
 utils/bazel/llvm-project-overlay/llvm/BUILD.bazel | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
index d3c7443748d9..8ab97a605e06 100644
--- a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+++ b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
@@ -1934,10 +1934,12 @@ llvm_target_lib_list = [lib for lib in [
         "name": "BPF",
         "short_name": "BPF",
         "tbl_outs": [
+            ("-gen-register-bank", "lib/Target/BPF/BPFGenRegisterBank.inc"),
             ("-gen-asm-writer", "lib/Target/BPF/BPFGenAsmWriter.inc"),
             ("-gen-asm-matcher", "lib/Target/BPF/BPFGenAsmMatcher.inc"),
             ("-gen-callingconv", "lib/Target/BPF/BPFGenCallingConv.inc"),
             ("-gen-dag-isel", "lib/Target/BPF/BPFGenDAGISel.inc"),
+            ("-gen-global-isel", "lib/Target/BPF/BPFGenGlobalISel.inc"),
             ("-gen-disassembler", "lib/Target/BPF/BPFGenDisassemblerTables.inc"),
             ("-gen-emitter", "lib/Target/BPF/BPFGenMCCodeEmitter.inc"),
             ("-gen-instr-info", "lib/Target/BPF/BPFGenInstrInfo.inc"),
-- 
GitLab


From 0474a92c9e77d56ab4e64b96f1bbef1932a7086f Mon Sep 17 00:00:00 2001
From: martinboehme <mboehme@google.com>
Date: Mon, 11 Dec 2023 14:14:16 +0100
Subject: [PATCH 116/349] [clang][dataflow] Convert `SpecialBoolAnalysis` to
 synthetic fields. (#74706)

We're working towards eliminating `RecordValue`; this eliminates one
more
blocker on that path.
---
 .../TypeErasedDataflowAnalysisTest.cpp        | 78 +++++--------------
 1 file changed, 20 insertions(+), 58 deletions(-)

diff --git a/clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp b/clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp
index f92afd8c3d84..4c3cb322eacf 100644
--- a/clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp
+++ b/clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp
@@ -514,8 +514,17 @@ TEST_F(NoreturnDestructorTest, ConditionalOperatorNestedBranchReturns) {
 class SpecialBoolAnalysis final
     : public DataflowAnalysis<SpecialBoolAnalysis, NoopLattice> {
 public:
-  explicit SpecialBoolAnalysis(ASTContext &Context)
-      : DataflowAnalysis<SpecialBoolAnalysis, NoopLattice>(Context) {}
+  explicit SpecialBoolAnalysis(ASTContext &Context, Environment &Env)
+      : DataflowAnalysis<SpecialBoolAnalysis, NoopLattice>(Context) {
+    Env.getDataflowAnalysisContext().setSyntheticFieldCallback(
+        [](QualType Ty) -> llvm::StringMap<QualType> {
+          RecordDecl *RD = Ty->getAsRecordDecl();
+          if (RD == nullptr || RD->getIdentifier() == nullptr ||
+              RD->getName() != "SpecialBool")
+            return {};
+          return {{"is_set", RD->getASTContext().BoolTy}};
+        });
+  }
 
   static NoopLattice initialElement() { return {}; }
 
@@ -530,67 +539,18 @@ public:
     if (const auto *E = selectFirst<CXXConstructExpr>(
             "call", match(cxxConstructExpr(HasSpecialBoolType).bind("call"), *S,
                           getASTContext()))) {
-      cast<RecordValue>(Env.getValue(*E))
-          ->setProperty("is_set", Env.getBoolLiteralValue(false));
+      Env.setValue(Env.getResultObjectLocation(*E).getSyntheticField("is_set"),
+                   Env.getBoolLiteralValue(false));
     } else if (const auto *E = selectFirst<CXXMemberCallExpr>(
                    "call", match(cxxMemberCallExpr(callee(cxxMethodDecl(ofClass(
                                                        SpecialBoolRecordDecl))))
                                      .bind("call"),
                                  *S, getASTContext()))) {
-      auto &ObjectLoc =
-          *cast<RecordStorageLocation>(getImplicitObjectLocation(*E, Env));
-
-      refreshRecordValue(ObjectLoc, Env)
-          .setProperty("is_set", Env.getBoolLiteralValue(true));
+      if (RecordStorageLocation *ObjectLoc = getImplicitObjectLocation(*E, Env))
+        Env.setValue(ObjectLoc->getSyntheticField("is_set"),
+                     Env.getBoolLiteralValue(true));
     }
   }
-
-  ComparisonResult compare(QualType Type, const Value &Val1,
-                           const Environment &Env1, const Value &Val2,
-                           const Environment &Env2) override {
-    const auto *Decl = Type->getAsCXXRecordDecl();
-    if (Decl == nullptr || Decl->getIdentifier() == nullptr ||
-        Decl->getName() != "SpecialBool")
-      return ComparisonResult::Unknown;
-
-    auto *IsSet1 = cast_or_null<BoolValue>(Val1.getProperty("is_set"));
-    auto *IsSet2 = cast_or_null<BoolValue>(Val2.getProperty("is_set"));
-    if (IsSet1 == nullptr)
-      return IsSet2 == nullptr ? ComparisonResult::Same
-                               : ComparisonResult::Different;
-
-    if (IsSet2 == nullptr)
-      return ComparisonResult::Different;
-
-    return Env1.proves(IsSet1->formula()) == Env2.proves(IsSet2->formula())
-               ? ComparisonResult::Same
-               : ComparisonResult::Different;
-  }
-
-  // Always returns `true` to accept the `MergedVal`.
-  bool merge(QualType Type, const Value &Val1, const Environment &Env1,
-             const Value &Val2, const Environment &Env2, Value &MergedVal,
-             Environment &MergedEnv) override {
-    const auto *Decl = Type->getAsCXXRecordDecl();
-    if (Decl == nullptr || Decl->getIdentifier() == nullptr ||
-        Decl->getName() != "SpecialBool")
-      return true;
-
-    auto *IsSet1 = cast_or_null<BoolValue>(Val1.getProperty("is_set"));
-    if (IsSet1 == nullptr)
-      return true;
-
-    auto *IsSet2 = cast_or_null<BoolValue>(Val2.getProperty("is_set"));
-    if (IsSet2 == nullptr)
-      return true;
-
-    auto &IsSet = MergedEnv.makeAtomicBoolValue();
-    MergedVal.setProperty("is_set", IsSet);
-    if (Env1.proves(IsSet1->formula()) && Env2.proves(IsSet2->formula()))
-      MergedEnv.assume(IsSet.formula());
-
-    return true;
-  }
 };
 
 class JoinFlowConditionsTest : public Test {
@@ -602,7 +562,7 @@ protected:
             AnalysisInputs<SpecialBoolAnalysis>(
                 Code, ast_matchers::hasName("target"),
                 [](ASTContext &Context, Environment &Env) {
-                  return SpecialBoolAnalysis(Context);
+                  return SpecialBoolAnalysis(Context, Env);
                 })
                 .withASTBuildArgs({"-fsyntax-only", "-std=c++17"}),
             /*VerifyResults=*/[&Match](const llvm::StringMap<
@@ -650,7 +610,9 @@ TEST_F(JoinFlowConditionsTest, JoinDistinctButProvablyEquivalentValues) {
         ASSERT_THAT(FooDecl, NotNull());
 
         auto GetFoo = [FooDecl](const Environment &Env) -> const Formula & {
-          return cast<BoolValue>(Env.getValue(*FooDecl)->getProperty("is_set"))
+          auto *Loc =
+              cast<RecordStorageLocation>(Env.getStorageLocation(*FooDecl));
+          return cast<BoolValue>(Env.getValue(Loc->getSyntheticField("is_set")))
               ->formula();
         };
 
-- 
GitLab


From 97efd8aa435c07aac5676d30e0311e9c05fb12c7 Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Mon, 11 Dec 2023 14:25:45 +0100
Subject: [PATCH 117/349] [InstCombine] Preserve inalloca tag when transforming
 alloca

This is not meaningful in any practical sense, and just makes sure
we don't cause verifier failures.
---
 .../InstCombine/InstCombineLoadStoreAlloca.cpp        |  1 +
 llvm/test/Transforms/InstCombine/alloca.ll            | 11 +++++++++++
 2 files changed, 12 insertions(+)

diff --git a/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp b/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
index f8fae773e476..bb2a77daa60a 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
@@ -213,6 +213,7 @@ static Instruction *simplifyAllocaArraySize(InstCombinerImpl &IC,
       AllocaInst *New = IC.Builder.CreateAlloca(NewTy, AI.getAddressSpace(),
                                                 nullptr, AI.getName());
       New->setAlignment(AI.getAlign());
+      New->setUsedWithInAlloca(AI.isUsedWithInAlloca());
 
       replaceAllDbgUsesWith(AI, *New, *New, DT);
       return IC.replaceInstUsesWith(AI, New);
diff --git a/llvm/test/Transforms/InstCombine/alloca.ll b/llvm/test/Transforms/InstCombine/alloca.ll
index a64de28ee839..4247d6a30193 100644
--- a/llvm/test/Transforms/InstCombine/alloca.ll
+++ b/llvm/test/Transforms/InstCombine/alloca.ll
@@ -248,3 +248,14 @@ entry:
   call void (...) @use(ptr nonnull @int) [ "blah"(ptr %y) ]
   ret void
 }
+
+define void @test_inalloca_with_element_count(ptr %a) {
+; ALL-LABEL: @test_inalloca_with_element_count(
+; ALL-NEXT:    [[ALLOCA1:%.*]] = alloca inalloca [10 x %struct_type], align 4
+; ALL-NEXT:    call void @test9_aux(ptr nonnull inalloca([[STRUCT_TYPE:%.*]]) [[ALLOCA1]])
+; ALL-NEXT:    ret void
+;
+  %alloca = alloca inalloca %struct_type, i32 10, align 4
+  call void @test9_aux(ptr inalloca(%struct_type) %alloca)
+  ret void
+}
-- 
GitLab


From ef23bba6e5aecbc6008e8a9ff8740fc4b04fe814 Mon Sep 17 00:00:00 2001
From: Joseph Huber <huberjn@outlook.com>
Date: Mon, 11 Dec 2023 07:55:00 -0600
Subject: [PATCH 118/349] [Linkerwrapper] Make -Xoffload-linker pass directly
 to `clang`

Summary:
We provide `-Xoffload-linker` to pass arguments directly to the link
step. Currently this uses `-Wl,` implicitly which prevents us from using
clang options that we otherwise could make use of. This patch removes
that implicit behavior as users can just as easiliy pass
`-Xoffload-linker -Wl,-foo` if needed.
---
 clang/test/Driver/linker-wrapper.c                      | 4 ++--
 clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/clang/test/Driver/linker-wrapper.c b/clang/test/Driver/linker-wrapper.c
index e82febd61823..b763a003452b 100644
--- a/clang/test/Driver/linker-wrapper.c
+++ b/clang/test/Driver/linker-wrapper.c
@@ -123,8 +123,8 @@
 // RUN:   --linker-path=/usr/bin/ld --device-linker=a --device-linker=nvptx64-nvidia-cuda=b -- \
 // RUN:   %t.o -o a.out 2>&1 | FileCheck %s --check-prefix=LINKER-ARGS
 
-// LINKER-ARGS: clang{{.*}}--target=amdgcn-amd-amdhsa{{.*}}-Wl,a
-// LINKER-ARGS: clang{{.*}}--target=nvptx64-nvidia-cuda{{.*}}-Wl,a -Wl,b
+// LINKER-ARGS: clang{{.*}}--target=amdgcn-amd-amdhsa{{.*}}a
+// LINKER-ARGS: clang{{.*}}--target=nvptx64-nvidia-cuda{{.*}}a b
 
 // RUN: not clang-linker-wrapper --dry-run --host-triple=x86_64-unknown-linux-gnu -ldummy \
 // RUN:   --linker-path=/usr/bin/ld --device-linker=a --device-linker=nvptx64-nvidia-cuda=b -- \
diff --git a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
index db0ce3e2a190..5d2fe98fe560 100644
--- a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
+++ b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
@@ -428,7 +428,7 @@ Expected<StringRef> clang(ArrayRef<StringRef> InputFiles, const ArgList &Args) {
         std::back_inserter(CmdArgs));
 
   for (StringRef Arg : Args.getAllArgValues(OPT_linker_arg_EQ))
-    CmdArgs.push_back(Args.MakeArgString("-Wl," + Arg));
+    CmdArgs.push_back(Args.MakeArgString(Arg));
 
   for (StringRef Arg : Args.getAllArgValues(OPT_builtin_bitcode_EQ)) {
     if (llvm::Triple(Arg.split('=').first) == Triple)
-- 
GitLab


From 06d6af72fb6f87cebe90ab96fa56fb88f53d5f66 Mon Sep 17 00:00:00 2001
From: Felipe de Azevedo Piovezan <fpiovezan@apple.com>
Date: Mon, 11 Dec 2023 11:16:36 -0300
Subject: [PATCH 119/349] [lldb][NFC] Simplify
 DWARRFDeclContext::GetQualifiedName (#74788)

This commit factors out the logic building each component of a qualified
name into its own function so that it may be reused by a future commit,
while also simplifying the logic of assembling these pieces together by
using llvm::interleave.
---
 .../SymbolFile/DWARF/DWARFDeclContext.cpp     | 41 ++++++++++---------
 1 file changed, 21 insertions(+), 20 deletions(-)

diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFDeclContext.cpp b/lldb/source/Plugins/SymbolFile/DWARF/DWARFDeclContext.cpp
index 44e760227901..44421c0eda3e 100644
--- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFDeclContext.cpp
+++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFDeclContext.cpp
@@ -7,10 +7,27 @@
 //===----------------------------------------------------------------------===//
 
 #include "DWARFDeclContext.h"
+#include "llvm/Support/raw_ostream.h"
 
 using namespace lldb_private::dwarf;
 using namespace lldb_private::plugin::dwarf;
 
+/// Returns the name of `entry` if it has one, or the appropriate "anonymous
+/// {namespace, class, struct, union}".
+static const char *GetName(DWARFDeclContext::Entry entry) {
+  if (entry.name != nullptr)
+    return entry.name;
+  if (entry.tag == DW_TAG_namespace)
+    return "(anonymous namespace)";
+  if (entry.tag == DW_TAG_class_type)
+    return "(anonymous class)";
+  if (entry.tag == DW_TAG_structure_type)
+    return "(anonymous struct)";
+  if (entry.tag == DW_TAG_union_type)
+    return "(anonymous union)";
+  return "(anonymous)";
+}
+
 const char *DWARFDeclContext::GetQualifiedName() const {
   if (m_qualified_name.empty()) {
     // The declaration context array for a class named "foo" in namespace
@@ -26,26 +43,10 @@ const char *DWARFDeclContext::GetQualifiedName() const {
           m_qualified_name.append(m_entries[0].name);
         }
       } else {
-        collection::const_reverse_iterator pos;
-        collection::const_reverse_iterator begin = m_entries.rbegin();
-        collection::const_reverse_iterator end = m_entries.rend();
-        for (pos = begin; pos != end; ++pos) {
-          if (pos != begin)
-            m_qualified_name.append("::");
-          if (pos->name == nullptr) {
-            if (pos->tag == DW_TAG_namespace)
-              m_qualified_name.append("(anonymous namespace)");
-            else if (pos->tag == DW_TAG_class_type)
-              m_qualified_name.append("(anonymous class)");
-            else if (pos->tag == DW_TAG_structure_type)
-              m_qualified_name.append("(anonymous struct)");
-            else if (pos->tag == DW_TAG_union_type)
-              m_qualified_name.append("(anonymous union)");
-            else
-              m_qualified_name.append("(anonymous)");
-          } else
-            m_qualified_name.append(pos->name);
-        }
+        llvm::raw_string_ostream string_stream(m_qualified_name);
+        llvm::interleave(
+            llvm::reverse(m_entries), string_stream,
+            [&](auto entry) { string_stream << GetName(entry); }, "::");
       }
     }
   }
-- 
GitLab


From 9071a15d4b90be1c0f57b6d7540097662b31963a Mon Sep 17 00:00:00 2001
From: Youngsuk Kim <joseph942010@gmail.com>
Date: Mon, 11 Dec 2023 09:29:01 -0500
Subject: [PATCH 120/349] [llvm][Attributor] Strip AddressSpaceCast from
 'constructPointer' (#74742)

* Remove pointer AddressSpaceCast in function `constructPointer`
* Remove 1st parameter (`ResTy`) of function `constructPointer`

1st input argument to function `constructPointer` in all 4 call-sites is
`ptr addrspace(0)`. Function `constructPointer` performs a pointer
AddressSpaceCast to `ResTy`, making the returned pointer have type `ptr
addrspace(0)` in all 4 call-sites.

Unless there's a clear reason to discard the addrspace info of input
parameter `Ptr`, I think we should keep and forward that info to the
returned pointer of `constructPointer`.

Opaque ptr cleanup effort.
---
 .../Transforms/IPO/AttributorAttributes.cpp   | 41 ++++++-------------
 1 file changed, 13 insertions(+), 28 deletions(-)

diff --git a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
index 889ebd7438bd..cbe0a96976c3 100644
--- a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
+++ b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
@@ -290,20 +290,19 @@ static const Value *getPointerOperand(const Instruction *I,
   return nullptr;
 }
 
-/// Helper function to create a pointer of type \p ResTy, based on \p Ptr, and
-/// advanced by \p Offset bytes. To aid later analysis the method tries to build
+/// Helper function to create a pointer based on \p Ptr, and advanced by \p
+/// Offset bytes. To aid later analysis the method tries to build
 /// getelement pointer instructions that traverse the natural type of \p Ptr if
 /// possible. If that fails, the remaining offset is adjusted byte-wise, hence
 /// through a cast to i8*.
 ///
 /// TODO: This could probably live somewhere more prominantly if it doesn't
 ///       already exist.
-static Value *constructPointer(Type *ResTy, Type *PtrElemTy, Value *Ptr,
-                               int64_t Offset, IRBuilder<NoFolder> &IRB,
-                               const DataLayout &DL) {
+static Value *constructPointer(Type *PtrElemTy, Value *Ptr, int64_t Offset,
+                               IRBuilder<NoFolder> &IRB, const DataLayout &DL) {
   assert(Offset >= 0 && "Negative offset not supported yet!");
   LLVM_DEBUG(dbgs() << "Construct pointer: " << *Ptr << " + " << Offset
-                    << "-bytes as " << *ResTy << "\n");
+                    << "-bytes\n");
 
   if (Offset) {
     Type *Ty = PtrElemTy;
@@ -327,10 +326,6 @@ static Value *constructPointer(Type *ResTy, Type *PtrElemTy, Value *Ptr,
     }
   }
 
-  // Ensure the result has the requested type.
-  Ptr = IRB.CreatePointerBitCastOrAddrSpaceCast(Ptr, ResTy,
-                                                Ptr->getName() + ".cast");
-
   LLVM_DEBUG(dbgs() << "Constructed pointer: " << *Ptr << "\n");
   return Ptr;
 }
@@ -7492,19 +7487,16 @@ struct AAPrivatizablePtrArgument final : public AAPrivatizablePtrImpl {
     if (auto *PrivStructType = dyn_cast<StructType>(PrivType)) {
       const StructLayout *PrivStructLayout = DL.getStructLayout(PrivStructType);
       for (unsigned u = 0, e = PrivStructType->getNumElements(); u < e; u++) {
-        Type *PointeeTy = PrivStructType->getElementType(u)->getPointerTo();
-        Value *Ptr =
-            constructPointer(PointeeTy, PrivType, &Base,
-                             PrivStructLayout->getElementOffset(u), IRB, DL);
+        Value *Ptr = constructPointer(
+            PrivType, &Base, PrivStructLayout->getElementOffset(u), IRB, DL);
         new StoreInst(F.getArg(ArgNo + u), Ptr, &IP);
       }
     } else if (auto *PrivArrayType = dyn_cast<ArrayType>(PrivType)) {
       Type *PointeeTy = PrivArrayType->getElementType();
-      Type *PointeePtrTy = PointeeTy->getPointerTo();
       uint64_t PointeeTySize = DL.getTypeStoreSize(PointeeTy);
       for (unsigned u = 0, e = PrivArrayType->getNumElements(); u < e; u++) {
-        Value *Ptr = constructPointer(PointeePtrTy, PrivType, &Base,
-                                      u * PointeeTySize, IRB, DL);
+        Value *Ptr =
+            constructPointer(PrivType, &Base, u * PointeeTySize, IRB, DL);
         new StoreInst(F.getArg(ArgNo + u), Ptr, &IP);
       }
     } else {
@@ -7524,19 +7516,13 @@ struct AAPrivatizablePtrArgument final : public AAPrivatizablePtrImpl {
     IRBuilder<NoFolder> IRB(IP);
     const DataLayout &DL = IP->getModule()->getDataLayout();
 
-    Type *PrivPtrType = PrivType->getPointerTo();
-    if (Base->getType() != PrivPtrType)
-      Base = BitCastInst::CreatePointerBitCastOrAddrSpaceCast(
-          Base, PrivPtrType, "", ACS.getInstruction());
-
     // Traverse the type, build GEPs and loads.
     if (auto *PrivStructType = dyn_cast<StructType>(PrivType)) {
       const StructLayout *PrivStructLayout = DL.getStructLayout(PrivStructType);
       for (unsigned u = 0, e = PrivStructType->getNumElements(); u < e; u++) {
         Type *PointeeTy = PrivStructType->getElementType(u);
-        Value *Ptr =
-            constructPointer(PointeeTy->getPointerTo(), PrivType, Base,
-                             PrivStructLayout->getElementOffset(u), IRB, DL);
+        Value *Ptr = constructPointer(
+            PrivType, Base, PrivStructLayout->getElementOffset(u), IRB, DL);
         LoadInst *L = new LoadInst(PointeeTy, Ptr, "", IP);
         L->setAlignment(Alignment);
         ReplacementValues.push_back(L);
@@ -7544,10 +7530,9 @@ struct AAPrivatizablePtrArgument final : public AAPrivatizablePtrImpl {
     } else if (auto *PrivArrayType = dyn_cast<ArrayType>(PrivType)) {
       Type *PointeeTy = PrivArrayType->getElementType();
       uint64_t PointeeTySize = DL.getTypeStoreSize(PointeeTy);
-      Type *PointeePtrTy = PointeeTy->getPointerTo();
       for (unsigned u = 0, e = PrivArrayType->getNumElements(); u < e; u++) {
-        Value *Ptr = constructPointer(PointeePtrTy, PrivType, Base,
-                                      u * PointeeTySize, IRB, DL);
+        Value *Ptr =
+            constructPointer(PrivType, Base, u * PointeeTySize, IRB, DL);
         LoadInst *L = new LoadInst(PointeeTy, Ptr, "", IP);
         L->setAlignment(Alignment);
         ReplacementValues.push_back(L);
-- 
GitLab


From 29bd78b2f61e638f6c26bc417ae476754b91e985 Mon Sep 17 00:00:00 2001
From: Krystian Stasiowski <sdkrystian@gmail.com>
Date: Mon, 11 Dec 2023 09:35:57 -0500
Subject: [PATCH 121/349] [Clang][Sema] Diagnose friend function specialization
 definitions (#72863)

Per [[class.friend]p6](http://eel.is/c++draft/class.friend#6) a friend
function shall not be defined if its name isn't unqualified. A
_template-id_ is not a name, meaning that a friend function
specialization does not meet this criteria and cannot be defined.

GCC, MSVC, and EDG all consider friend function specialization
definitions to be invalid de facto explicit specializations and diagnose
them as such.

Instantiating a dependent friend function specialization definition
[currently sets off an assert](https://godbolt.org/z/Krqdq95hY) in
`FunctionDecl::setFunctionTemplateSpecialization`. This happens because
we do not set the `TemplateSpecializationKind` of the `FunctionDecl`
created by template argument deduction to `TSK_ExplicitSpecialization`
for friend functions
[here](https://github.com/llvm/llvm-project/blob/main/clang/lib/Sema/SemaTemplate.cpp#L9600).
I changed the assert condition because I believe this is the correct
behavior.
---
 clang/docs/ReleaseNotes.rst                   |  1 +
 .../clang/Basic/DiagnosticSemaKinds.td        |  2 +
 clang/lib/AST/Decl.cpp                        |  1 +
 clang/lib/Sema/SemaDeclCXX.cpp                | 71 +++++++++----------
 .../test/CXX/class.access/class.friend/p6.cpp | 13 ++++
 .../CXX/temp/temp.decls/temp.friend/p1.cpp    |  6 +-
 clang/test/SemaCXX/friend.cpp                 |  2 +-
 7 files changed, 55 insertions(+), 41 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index b4b5352a306c..bc3acf165f07 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -513,6 +513,7 @@ Improvements to Clang's diagnostics
        48 | static_assert(1 << 4 == 15);
           |               ~~~~~~~^~~~~
 
+- Clang now diagnoses definitions of friend function specializations, e.g. ``friend void f<>(int) {}``.
 
 Improvements to Clang's time-trace
 ----------------------------------
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index 28d95ca9b138..0b53c6dce810 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -1669,6 +1669,8 @@ def err_qualified_friend_def : Error<
   "friend function definition cannot be qualified with '%0'">;
 def err_friend_def_in_local_class : Error<
   "friend function cannot be defined in a local class">;
+def err_friend_specialization_def : Error<
+  "friend function specialization cannot be defined">;
 def err_friend_not_first_in_declaration : Error<
   "'friend' must appear first in a non-function declaration">;
 def err_using_decl_friend : Error<
diff --git a/clang/lib/AST/Decl.cpp b/clang/lib/AST/Decl.cpp
index c5c2edf1bfe3..527ea6042daa 100644
--- a/clang/lib/AST/Decl.cpp
+++ b/clang/lib/AST/Decl.cpp
@@ -4150,6 +4150,7 @@ FunctionDecl::setFunctionTemplateSpecialization(ASTContext &C,
   assert(TSK != TSK_Undeclared &&
          "Must specify the type of function template specialization");
   assert((TemplateOrSpecialization.isNull() ||
+          getFriendObjectKind() != FOK_None ||
           TSK == TSK_ExplicitSpecialization) &&
          "Member specialization must be an explicit specialization");
   FunctionTemplateSpecializationInfo *Info =
diff --git a/clang/lib/Sema/SemaDeclCXX.cpp b/clang/lib/Sema/SemaDeclCXX.cpp
index c6218a491aec..36e53c684ac4 100644
--- a/clang/lib/Sema/SemaDeclCXX.cpp
+++ b/clang/lib/Sema/SemaDeclCXX.cpp
@@ -17879,6 +17879,8 @@ NamedDecl *Sema::ActOnFriendFunctionDecl(Scope *S, Declarator &D,
   LookupResult Previous(*this, NameInfo, LookupOrdinaryName,
                         ForExternalRedeclaration);
 
+  bool isTemplateId = D.getName().getKind() == UnqualifiedIdKind::IK_TemplateId;
+
   // There are five cases here.
   //   - There's no scope specifier and we're in a local class. Only look
   //     for functions declared in the immediately-enclosing block scope.
@@ -17916,14 +17918,6 @@ NamedDecl *Sema::ActOnFriendFunctionDecl(Scope *S, Declarator &D,
     }
     adjustContextForLocalExternDecl(DC);
 
-    // C++ [class.friend]p6:
-    //   A function can be defined in a friend declaration of a class if and
-    //   only if the class is a non-local class (9.8), the function name is
-    //   unqualified, and the function has namespace scope.
-    if (D.isFunctionDefinition()) {
-      Diag(NameInfo.getBeginLoc(), diag::err_friend_def_in_local_class);
-    }
-
   //   - There's no scope specifier, in which case we just go to the
   //     appropriate scope and look for a function or function template
   //     there as appropriate.
@@ -17934,8 +17928,6 @@ NamedDecl *Sema::ActOnFriendFunctionDecl(Scope *S, Declarator &D,
     //   elaborated-type-specifier, the lookup to determine whether
     //   the entity has been previously declared shall not consider
     //   any scopes outside the innermost enclosing namespace.
-    bool isTemplateId =
-        D.getName().getKind() == UnqualifiedIdKind::IK_TemplateId;
 
     // Find the appropriate context according to the above.
     DC = CurContext;
@@ -17988,39 +17980,12 @@ NamedDecl *Sema::ActOnFriendFunctionDecl(Scope *S, Declarator &D,
              diag::warn_cxx98_compat_friend_is_member :
              diag::err_friend_is_member);
 
-    if (D.isFunctionDefinition()) {
-      // C++ [class.friend]p6:
-      //   A function can be defined in a friend declaration of a class if and
-      //   only if the class is a non-local class (9.8), the function name is
-      //   unqualified, and the function has namespace scope.
-      //
-      // FIXME: We should only do this if the scope specifier names the
-      // innermost enclosing namespace; otherwise the fixit changes the
-      // meaning of the code.
-      SemaDiagnosticBuilder DB
-        = Diag(SS.getRange().getBegin(), diag::err_qualified_friend_def);
-
-      DB << SS.getScopeRep();
-      if (DC->isFileContext())
-        DB << FixItHint::CreateRemoval(SS.getRange());
-      SS.clear();
-    }
-
   //   - There's a scope specifier that does not match any template
   //     parameter lists, in which case we use some arbitrary context,
   //     create a method or method template, and wait for instantiation.
   //   - There's a scope specifier that does match some template
   //     parameter lists, which we don't handle right now.
   } else {
-    if (D.isFunctionDefinition()) {
-      // C++ [class.friend]p6:
-      //   A function can be defined in a friend declaration of a class if and
-      //   only if the class is a non-local class (9.8), the function name is
-      //   unqualified, and the function has namespace scope.
-      Diag(SS.getRange().getBegin(), diag::err_qualified_friend_def)
-        << SS.getScopeRep();
-    }
-
     DC = CurContext;
     assert(isa<CXXRecordDecl>(DC) && "friend declaration not in class?");
   }
@@ -18105,6 +18070,38 @@ NamedDecl *Sema::ActOnFriendFunctionDecl(Scope *S, Declarator &D,
     else
       FD = cast<FunctionDecl>(ND);
 
+    // C++ [class.friend]p6:
+    //   A function may be defined in a friend declaration of a class if and
+    //   only if the class is a non-local class, and the function name is
+    //   unqualified.
+    if (D.isFunctionDefinition()) {
+      // Qualified friend function definition.
+      if (SS.isNotEmpty()) {
+        // FIXME: We should only do this if the scope specifier names the
+        // innermost enclosing namespace; otherwise the fixit changes the
+        // meaning of the code.
+        SemaDiagnosticBuilder DB =
+            Diag(SS.getRange().getBegin(), diag::err_qualified_friend_def);
+
+        DB << SS.getScopeRep();
+        if (DC->isFileContext())
+          DB << FixItHint::CreateRemoval(SS.getRange());
+
+        // Friend function defined in a local class.
+      } else if (FunctionContainingLocalClass) {
+        Diag(NameInfo.getBeginLoc(), diag::err_friend_def_in_local_class);
+
+        // Per [basic.pre]p4, a template-id is not a name. Therefore, if we have
+        // a template-id, the function name is not unqualified because these is
+        // no name. While the wording requires some reading in-between the
+        // lines, GCC, MSVC, and EDG all consider a friend function
+        // specialization definitions // to be de facto explicit specialization
+        // and diagnose them as such.
+      } else if (isTemplateId) {
+        Diag(NameInfo.getBeginLoc(), diag::err_friend_specialization_def);
+      }
+    }
+
     // C++11 [dcl.fct.default]p4: If a friend declaration specifies a
     // default argument expression, that declaration shall be a definition
     // and shall be the only declaration of the function or function
diff --git a/clang/test/CXX/class.access/class.friend/p6.cpp b/clang/test/CXX/class.access/class.friend/p6.cpp
index 2fe20fe77fc8..47104e29dc6b 100644
--- a/clang/test/CXX/class.access/class.friend/p6.cpp
+++ b/clang/test/CXX/class.access/class.friend/p6.cpp
@@ -22,3 +22,16 @@ void local() {
     friend void f() { } // expected-error{{friend function cannot be defined in a local class}}
   };
 }
+
+template<typename T> void f3(T);
+
+namespace N {
+  template<typename T> void f4(T);
+}
+
+template<typename T> struct A {
+  friend void f3(T) {}
+  friend void f3<T>(T) {} // expected-error{{friend function specialization cannot be defined}}
+  friend void N::f4(T) {} // expected-error{{friend function definition cannot be qualified with 'N::'}}
+  friend void N::f4<T>(T) {} // expected-error{{friend function definition cannot be qualified with 'N::'}}
+};
diff --git a/clang/test/CXX/temp/temp.decls/temp.friend/p1.cpp b/clang/test/CXX/temp/temp.decls/temp.friend/p1.cpp
index ab1b9f7a73ee..1cf9e1c9f9c0 100644
--- a/clang/test/CXX/temp/temp.decls/temp.friend/p1.cpp
+++ b/clang/test/CXX/temp/temp.decls/temp.friend/p1.cpp
@@ -17,7 +17,7 @@ public:
       for (U count = n.count_; count; --count)
         x += a;
       return x;
-    } 
+    }
   };
 
   friend Num operator+(const Num &a, const Num &b) {
@@ -145,7 +145,7 @@ namespace test5 {
 
 namespace Dependent {
   template<typename T, typename Traits> class X;
-  template<typename T, typename Traits> 
+  template<typename T, typename Traits>
   X<T, Traits> operator+(const X<T, Traits>&, const T*);
 
   template<typename T, typename Traits> class X {
@@ -249,7 +249,7 @@ namespace test11 {
   };
 
   template struct Foo::IteratorImpl<int>;
-  template struct Foo::IteratorImpl<long>;  
+  template struct Foo::IteratorImpl<long>;
 }
 
 // PR6827
diff --git a/clang/test/SemaCXX/friend.cpp b/clang/test/SemaCXX/friend.cpp
index 367d6a6c1807..53e6bbfcf42a 100644
--- a/clang/test/SemaCXX/friend.cpp
+++ b/clang/test/SemaCXX/friend.cpp
@@ -162,7 +162,7 @@ namespace test9 {
   class C {
   };
   struct A {
-    friend void C::f(int, int, int) {}  // expected-error {{friend function definition cannot be qualified with 'C::'}}
+    friend void C::f(int, int, int) {}  // expected-error {{friend declaration of 'f' does not match any declaration in 'test9::C'}}
   };
 }
 
-- 
GitLab


From 8b5af3139c18516433bc77d65dea59df50e052e9 Mon Sep 17 00:00:00 2001
From: Brad Smith <brad@comstyle.com>
Date: Mon, 11 Dec 2023 09:54:24 -0500
Subject: [PATCH 122/349] [OpenMP] Change check for OS to check for defined for
 a macro (#75012)

Check for the existence of the macro instead of checking for Solaris.
illumos has this macro in sys/time.h.

/export/home/brad/llvm-brad/openmp/runtime/src/z_Linux_util.cpp:77:9: warning: 'TIMEVAL_TO_TIMESPEC' macro redefined [-Wmacro-redefined]
   77 | #define TIMEVAL_TO_TIMESPEC(tv, ts)                                            \
      |         ^
/usr/include/sys/time.h:424:9: note: previous definition is here
  424 | #define TIMEVAL_TO_TIMESPEC(tv, ts) { \
      |         ^
---
 openmp/runtime/src/z_Linux_util.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openmp/runtime/src/z_Linux_util.cpp b/openmp/runtime/src/z_Linux_util.cpp
index 72da0f79865d..fdce932fd6d6 100644
--- a/openmp/runtime/src/z_Linux_util.cpp
+++ b/openmp/runtime/src/z_Linux_util.cpp
@@ -72,7 +72,7 @@ struct kmp_sys_timer {
   struct timespec start;
 };
 
-#if KMP_OS_SOLARIS
+#ifndef TIMEVAL_TO_TIMESPEC
 // Convert timeval to timespec.
 #define TIMEVAL_TO_TIMESPEC(tv, ts)                                            \
   do {                                                                         \
-- 
GitLab


From b40c53465650456bfd364c123b1001e025353a33 Mon Sep 17 00:00:00 2001
From: Zahira Ammarguellat <zahira.ammarguellat@intel.com>
Date: Mon, 11 Dec 2023 07:03:27 -0800
Subject: [PATCH 123/349] [clang] Add support for -fcx-limited-range, #pragma
 CX_LIMITED_RANGE and -fcx-fortran-rules.  (#70244)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This patch adds the #pragma CX_LIMITED_RANGE defined in the C
specification.
It also adds the options -f[no]cx-limited-range and
-f[no]cx-fortran-rules.
-fcx-limited-range enables algebraic formulas for complex multiplication
and division. This option is enabled with -ffast-math.
-fcx-fortran-rules enables algebraic formulas for complex multiplication
and enables Smith’s algorithm for complex division (SMITH, R. L.
Algorithm 116: Complex division. Commun. ACM 5, 8 (1962)).

---------

Signed-off-by: Med Ismail Bennani <ismail@bennani.ma>
Co-authored-by: Joseph Huber <jhuber6@vols.utk.edu>
Co-authored-by: Guray Ozen <guray.ozen@gmail.com>
Co-authored-by: Nishant Patel <nishant.b.patel@intel.com>
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
Co-authored-by: Petr Hosek <phosek@google.com>
Co-authored-by: Joseph Huber <35342157+jhuber6@users.noreply.github.com>
Co-authored-by: Craig Topper <craig.topper@sifive.com>
Co-authored-by: Alexander Yermolovich <43973793+ayermolo@users.noreply.github.com>
Co-authored-by: Usama Hameed <u_hameed@apple.com>
Co-authored-by: Philip Reames <preames@rivosinc.com>
Co-authored-by: Evgenii Kudriashov <evgenii.kudriashov@intel.com>
Co-authored-by: Fangrui Song <i@maskray.me>
Co-authored-by: Aart Bik <39774503+aartbik@users.noreply.github.com>
Co-authored-by: Valentin Clement <clementval@gmail.com>
Co-authored-by: Youngsuk Kim <youngsuk.kim@hpe.com>
Co-authored-by: Arthur Eubanks <aeubanks@google.com>
Co-authored-by: Jan Svoboda <jan_svoboda@apple.com>
Co-authored-by: Walter Erquinigo <a20012251@gmail.com>
Co-authored-by: Eric <eric@efcs.ca>
Co-authored-by: Fazlay Rabbi <106703039+mdfazlay@users.noreply.github.com>
Co-authored-by: Pete Lawrence <plawrence@apple.com>
Co-authored-by: Jonas Devlieghere <jonas@devlieghere.com>
Co-authored-by: Adrian Prantl <aprantl@apple.com>
Co-authored-by: Owen Pan <owenpiano@gmail.com>
Co-authored-by: LLVM GN Syncbot <llvmgnsyncbot@gmail.com>
Co-authored-by: Med Ismail Bennani <ismail@bennani.ma>
Co-authored-by: Congcong Cai <congcongcai0907@163.com>
Co-authored-by: Rik Huijzer <github@huijzer.xyz>
Co-authored-by: Wang Pengcheng <wangpengcheng.pp@bytedance.com>
Co-authored-by: Yuanfang Chen <tabloid.adroit@gmail.com>
Co-authored-by: Kazu Hirata <kazu@google.com>
Co-authored-by: Mehdi Amini <joker.eph@gmail.com>
Co-authored-by: Aiden Grossman <agrossman154@yahoo.com>
Co-authored-by: Rana Pratap Reddy <109514914+ranapratap55@users.noreply.github.com>
Co-authored-by: Yingwei Zheng <dtcxzyw2333@gmail.com>
Co-authored-by: Piotr Zegar <me@piotrzegar.pl>
Co-authored-by: KAWASHIMA Takahiro <t-kawashima@fujitsu.com>
Co-authored-by: Tobias Hieta <tobias@hieta.se>
Co-authored-by: Luke Lau <luke@igalia.com>
Co-authored-by: Shivam Gupta <shivam98.tkg@gmail.com>
Co-authored-by: cor3ntin <corentinjabot@gmail.com>
Co-authored-by: Yeting Kuo <46629943+yetingk@users.noreply.github.com>
Co-authored-by: Stanislav Mekhanoshin <rampitec@users.noreply.github.com>
Co-authored-by: David Spickett <david.spickett@linaro.org>
Co-authored-by: Matthew Devereau <matthew.devereau@arm.com>
Co-authored-by: Martin Storsjö <martin@martin.st>
Co-authored-by: Qiu Chaofan <qiucofan@cn.ibm.com>
Co-authored-by: Pierre van Houtryve <pierre.vanhoutryve@amd.com>
Co-authored-by: Mikael Holmen <mikael.holmen@ericsson.com>
Co-authored-by: Uday Bondhugula <uday@polymagelabs.com>
Co-authored-by: Nikita Popov <npopov@redhat.com>
Co-authored-by: Johannes Reifferscheid <jreiffers@google.com>
Co-authored-by: Benjamin Kramer <benny.kra@googlemail.com>
Co-authored-by: Oliver Stannard <oliver.stannard@arm.com>
Co-authored-by: Dmitry Vyukov <dvyukov@google.com>
Co-authored-by: Benjamin Maxwell <benjamin.maxwell@arm.com>
Co-authored-by: Piotr Sobczak <piotr.sobczak@amd.com>
Co-authored-by: Simon Pilgrim <llvm-dev@redking.me.uk>
Co-authored-by: Timm Bäder <tbaeder@redhat.com>
Co-authored-by: Sunil Kuravinakop <koops@hpe.com>
Co-authored-by: zhongyunde 00443407 <zhongyunde@huawei.com>
Co-authored-by: Christudasan Devadasan <Christudasan.Devadasan@amd.com>
Co-authored-by: bjacob <jacob.benoit.1@gmail.com>
Co-authored-by: Weining Lu <luweining@loongson.cn>
Co-authored-by: Andrzej Warzyński <andrzej.warzynski@arm.com>
Co-authored-by: Jay Foad <jay.foad@amd.com>
Co-authored-by: Markus Mützel <markus.muetzel@gmx.de>
Co-authored-by: Erik Jonsson <erik.j.jonsson@ericsson.com>
Co-authored-by: Pete Steinfeld <47540744+psteinfeld@users.noreply.github.com>
Co-authored-by: Alexey Bataev <a.bataev@outlook.com>
Co-authored-by: Louis Dionne <ldionne.2@gmail.com>
Co-authored-by: Qizhi Hu <836744285@qq.com>
---
 clang/docs/ReleaseNotes.rst                  |  13 +
 clang/docs/UsersManual.rst                   |  15 +
 clang/include/clang/Basic/FPOptions.def      |   1 +
 clang/include/clang/Basic/Features.def       |   1 +
 clang/include/clang/Basic/LangOptions.def    |   2 +
 clang/include/clang/Basic/LangOptions.h      |   3 +
 clang/include/clang/Basic/TokenKinds.def     |   5 +
 clang/include/clang/Driver/Options.td        |  24 +
 clang/include/clang/Parse/Parser.h           |   4 +
 clang/include/clang/Sema/Sema.h              |   5 +
 clang/lib/CodeGen/CGExprComplex.cpp          | 166 +++++--
 clang/lib/Driver/ToolChains/Clang.cpp        |  71 ++-
 clang/lib/Parse/ParsePragma.cpp              |  40 +-
 clang/lib/Parse/ParseStmt.cpp                |  11 +
 clang/lib/Parse/Parser.cpp                   |   3 +
 clang/lib/Sema/SemaAttr.cpp                  |   8 +
 clang/test/CodeGen/complex-math.c            | 468 +++++++++++++++----
 clang/test/CodeGen/cx-complex-range.c        | 108 +++++
 clang/test/CodeGen/pragma-cx-limited-range.c | 107 +++++
 clang/test/Driver/range.c                    |  39 ++
 clang/test/Preprocessor/pragma_unknown.c     |   2 +
 21 files changed, 960 insertions(+), 136 deletions(-)
 create mode 100644 clang/test/CodeGen/cx-complex-range.c
 create mode 100644 clang/test/CodeGen/pragma-cx-limited-range.c
 create mode 100644 clang/test/Driver/range.c

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index bc3acf165f07..6e4009deaf87 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -264,6 +264,16 @@ New Compiler Flags
 
 * ``-fopenacc`` was added as a part of the effort to support OpenACC in clang.
 
+* ``-fcx-limited-range`` enables the naive mathematical formulas for complex
+  division and multiplication with no NaN checking of results. The default is
+  ``-fno-cx-limited-range``, but this option is enabled by ``-ffast-math``.
+
+* ``-fcx-fortran-rules`` enables the naive mathematical formulas for complex
+  multiplication and enables application of Smith's algorithm for complex
+  division. See SMITH, R. L. Algorithm 116: Complex division. Commun. ACM 5, 8
+  (1962). The default is ``-fno-cx-fortran-rules``.
+
+
 Deprecated Compiler Flags
 -------------------------
 
@@ -1002,6 +1012,9 @@ Floating Point Support in Clang
   ``__builtin_exp10f128`` builtins.
 - Add ``__builtin_iszero``, ``__builtin_issignaling`` and
   ``__builtin_issubnormal``.
+- Add support for C99's ``#pragma STDC CX_LIMITED_RANGE`` feature.  This
+  enables the naive mathematical formulas for complex multiplication and
+  division, which are faster but do not correctly handle overflow and infinities.
 
 AST Matchers
 ------------
diff --git a/clang/docs/UsersManual.rst b/clang/docs/UsersManual.rst
index f1b344ef5109..7c30570437e8 100644
--- a/clang/docs/UsersManual.rst
+++ b/clang/docs/UsersManual.rst
@@ -1468,6 +1468,7 @@ floating point semantic models: precise (the default), strict, and fast.
    With the exception of ``-ffp-contract=fast``, using any of the options
    below to disable any of the individual optimizations in ``-ffast-math``
    will cause ``__FAST_MATH__`` to no longer be set.
+   ``-ffast-math`` enables ``-fcx-limited-range``.
 
    This option implies:
 
@@ -1834,6 +1835,20 @@ floating point semantic models: precise (the default), strict, and fast.
    * ``16`` - Forces ``_Float16`` operations to be emitted without using excess
      precision arithmetic.
 
+.. option:: -fcx-limited-range:
+
+   This option enables the naive mathematical formulas for complex division and
+   multiplication with no NaN checking of results. The default is
+   ``-fno-cx-limited-range``, but this option is enabled by the ``-ffast-math``
+   option.
+
+.. option:: -fcx-fortran-rules:
+
+   This option enables the naive mathematical formulas for complex
+   multiplication and enables application of Smith's algorithm for complex
+   division. See SMITH, R. L. Algorithm 116: Complex division. Commun.
+   ACM 5, 8 (1962). The default is ``-fno-cx-fortran-rules``.
+
 .. _floating-point-environment:
 
 Accessing the floating point environment
diff --git a/clang/include/clang/Basic/FPOptions.def b/clang/include/clang/Basic/FPOptions.def
index 5b923a1944e5..79f04c89c9fe 100644
--- a/clang/include/clang/Basic/FPOptions.def
+++ b/clang/include/clang/Basic/FPOptions.def
@@ -28,4 +28,5 @@ OPTION(FPEvalMethod, LangOptions::FPEvalMethodKind, 2, AllowApproxFunc)
 OPTION(Float16ExcessPrecision, LangOptions::ExcessPrecisionKind, 2, FPEvalMethod)
 OPTION(BFloat16ExcessPrecision, LangOptions::ExcessPrecisionKind, 2, Float16ExcessPrecision)
 OPTION(MathErrno, bool, 1, BFloat16ExcessPrecision)
+OPTION(ComplexRange, LangOptions::ComplexRangeKind, 2, MathErrno)
 #undef OPTION
diff --git a/clang/include/clang/Basic/Features.def b/clang/include/clang/Basic/Features.def
index df1eff8cbcc9..7473e00a7bd8 100644
--- a/clang/include/clang/Basic/Features.def
+++ b/clang/include/clang/Basic/Features.def
@@ -104,6 +104,7 @@ FEATURE(scudo, LangOpts.Sanitize.hasOneOf(SanitizerKind::Scudo))
 FEATURE(swiftasynccc,
   PP.getTargetInfo().checkCallingConvention(CC_SwiftAsync) ==
   clang::TargetInfo::CCCR_OK)
+FEATURE(pragma_stdc_cx_limited_range, true)
 // Objective-C features
 FEATURE(objc_arr, LangOpts.ObjCAutoRefCount) // FIXME: REMOVE?
 FEATURE(objc_arc, LangOpts.ObjCAutoRefCount)
diff --git a/clang/include/clang/Basic/LangOptions.def b/clang/include/clang/Basic/LangOptions.def
index c3d5399905a3..152d9f65f86d 100644
--- a/clang/include/clang/Basic/LangOptions.def
+++ b/clang/include/clang/Basic/LangOptions.def
@@ -220,6 +220,8 @@ BENIGN_LANGOPT(NoSignedZero      , 1, 0, "Permit Floating Point optimization wit
 BENIGN_LANGOPT(AllowRecip        , 1, 0, "Permit Floating Point reciprocal")
 BENIGN_LANGOPT(ApproxFunc        , 1, 0, "Permit Floating Point approximation")
 
+ENUM_LANGOPT(ComplexRange, ComplexRangeKind, 2, CX_Full, "Enable use of range reduction for complex arithmetics.")
+
 BENIGN_LANGOPT(ObjCGCBitmapPrint , 1, 0, "printing of GC's bitmap layout for __weak/__strong ivars")
 
 BENIGN_LANGOPT(AccessControl     , 1, 1, "C++ access control")
diff --git a/clang/include/clang/Basic/LangOptions.h b/clang/include/clang/Basic/LangOptions.h
index c4979b9a38c0..9f986fce2d44 100644
--- a/clang/include/clang/Basic/LangOptions.h
+++ b/clang/include/clang/Basic/LangOptions.h
@@ -392,6 +392,8 @@ public:
     IncompleteOnly = 3,
   };
 
+  enum ComplexRangeKind { CX_Full, CX_Limited, CX_Fortran };
+
 public:
   /// The used language standard.
   LangStandard::Kind LangStd;
@@ -741,6 +743,7 @@ public:
       setAllowFEnvAccess(true);
     else
       setAllowFEnvAccess(LangOptions::FPM_Off);
+    setComplexRange(LO.getComplexRange());
   }
 
   bool allowFPContractWithinStatement() const {
diff --git a/clang/include/clang/Basic/TokenKinds.def b/clang/include/clang/Basic/TokenKinds.def
index 5f9915d21022..3f0e1e1a7d45 100644
--- a/clang/include/clang/Basic/TokenKinds.def
+++ b/clang/include/clang/Basic/TokenKinds.def
@@ -911,6 +911,11 @@ PRAGMA_ANNOTATION(pragma_fenv_access_ms)
 // handles them.
 PRAGMA_ANNOTATION(pragma_fenv_round)
 
+// Annotation for #pragma STDC CX_LIMITED_RANGE
+// The lexer produces these so that they only take effect when the parser
+// handles them.
+PRAGMA_ANNOTATION(pragma_cx_limited_range)
+
 // Annotation for #pragma float_control
 // The lexer produces these so that they only take effect when the parser
 // handles them.
diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td
index cf969cb0b318..25c76cf2ad2c 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -1010,6 +1010,30 @@ defm offload_uniform_block : BoolFOption<"offload-uniform-block",
   NegFlag<SetFalse, [], [ClangOption, CC1Option], "Don't assume">,
   BothFlags<[], [ClangOption], " that kernels are launched with uniform block sizes (default true for CUDA/HIP and false otherwise)">>;
 
+def fcx_limited_range : Joined<["-"], "fcx-limited-range">,
+  Group<f_Group>, Visibility<[ClangOption, CC1Option]>,
+  HelpText<"Basic algebraic expansions of complex arithmetic operations "
+           "involving are enabled.">;
+
+def fno_cx_limited_range : Joined<["-"], "fno-cx-limited-range">,
+  Group<f_Group>, Visibility<[ClangOption, CC1Option]>,
+  HelpText<"Basic algebraic expansions of complex arithmetic operations "
+           "involving are disabled.">;
+
+def fcx_fortran_rules : Joined<["-"], "fcx-fortran-rules">,
+  Group<f_Group>, Visibility<[ClangOption, CC1Option]>,
+  HelpText<"Range reduction is enabled for complex arithmetic operations.">;
+
+def fno_cx_fortran_rules : Joined<["-"], "fno-cx-fortran-rules">,
+  Group<f_Group>, Visibility<[ClangOption, CC1Option]>,
+  HelpText<"Range reduction is disabled for complex arithmetic operations.">;
+
+def complex_range_EQ : Joined<["-"], "complex-range=">, Group<f_Group>,
+  Visibility<[CC1Option]>,
+  Values<"full,limited,fortran">, NormalizedValuesScope<"LangOptions">,
+  NormalizedValues<["CX_Full", "CX_Limited", "CX_Fortran"]>,
+  MarshallingInfoEnum<LangOpts<"ComplexRange">, "CX_Full">;
+
 // OpenCL-only Options
 def cl_opt_disable : Flag<["-"], "cl-opt-disable">, Group<opencl_Group>,
   Visibility<[ClangOption, CC1Option]>,
diff --git a/clang/include/clang/Parse/Parser.h b/clang/include/clang/Parse/Parser.h
index 066349823516..2dbe090bd093 100644
--- a/clang/include/clang/Parse/Parser.h
+++ b/clang/include/clang/Parse/Parser.h
@@ -769,6 +769,10 @@ private:
   /// #pragma STDC FENV_ROUND...
   void HandlePragmaFEnvRound();
 
+  /// Handle the annotation token produced for
+  /// #pragma STDC CX_LIMITED_RANGE...
+  void HandlePragmaCXLimitedRange();
+
   /// Handle the annotation token produced for
   /// #pragma float_control
   void HandlePragmaFloatControl();
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index f45e0a7d3d52..1902d098f3c2 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -11023,6 +11023,11 @@ public:
   /// \#pragma STDC FENV_ACCESS
   void ActOnPragmaFEnvAccess(SourceLocation Loc, bool IsEnabled);
 
+  /// ActOnPragmaCXLimitedRange - Called on well formed
+  /// \#pragma STDC CX_LIMITED_RANGE
+  void ActOnPragmaCXLimitedRange(SourceLocation Loc,
+                                 LangOptions::ComplexRangeKind Range);
+
   /// Called on well formed '\#pragma clang fp' that has option 'exceptions'.
   void ActOnPragmaFPExceptions(SourceLocation Loc,
                                LangOptions::FPExceptionModeKind);
diff --git a/clang/lib/CodeGen/CGExprComplex.cpp b/clang/lib/CodeGen/CGExprComplex.cpp
index f3cbd1d0451e..e532794b71bd 100644
--- a/clang/lib/CodeGen/CGExprComplex.cpp
+++ b/clang/lib/CodeGen/CGExprComplex.cpp
@@ -275,6 +275,10 @@ public:
   ComplexPairTy EmitBinSub(const BinOpInfo &Op);
   ComplexPairTy EmitBinMul(const BinOpInfo &Op);
   ComplexPairTy EmitBinDiv(const BinOpInfo &Op);
+  ComplexPairTy EmitAlgebraicDiv(llvm::Value *A, llvm::Value *B, llvm::Value *C,
+                                 llvm::Value *D);
+  ComplexPairTy EmitRangeReductionDiv(llvm::Value *A, llvm::Value *B,
+                                      llvm::Value *C, llvm::Value *D);
 
   ComplexPairTy EmitComplexBinOpLibCall(StringRef LibCallName,
                                         const BinOpInfo &Op);
@@ -781,6 +785,10 @@ ComplexPairTy ComplexExprEmitter::EmitBinMul(const BinOpInfo &Op) {
       ResR = Builder.CreateFSub(AC, BD, "mul_r");
       ResI = Builder.CreateFAdd(AD, BC, "mul_i");
 
+      if (Op.FPFeatures.getComplexRange() == LangOptions::CX_Limited ||
+          Op.FPFeatures.getComplexRange() == LangOptions::CX_Fortran)
+        return ComplexPairTy(ResR, ResI);
+
       // Emit the test for the real part becoming NaN and create a branch to
       // handle it. We test for NaN by comparing the number to itself.
       Value *IsRNaN = Builder.CreateFCmpUNO(ResR, ResR, "isnan_cmp");
@@ -846,23 +854,139 @@ ComplexPairTy ComplexExprEmitter::EmitBinMul(const BinOpInfo &Op) {
   return ComplexPairTy(ResR, ResI);
 }
 
+ComplexPairTy ComplexExprEmitter::EmitAlgebraicDiv(llvm::Value *LHSr,
+                                                   llvm::Value *LHSi,
+                                                   llvm::Value *RHSr,
+                                                   llvm::Value *RHSi) {
+  // (a+ib) / (c+id) = ((ac+bd)/(cc+dd)) + i((bc-ad)/(cc+dd))
+  llvm::Value *DSTr, *DSTi;
+
+  llvm::Value *AC = Builder.CreateFMul(LHSr, RHSr); // a*c
+  llvm::Value *BD = Builder.CreateFMul(LHSi, RHSi); // b*d
+  llvm::Value *ACpBD = Builder.CreateFAdd(AC, BD);  // ac+bd
+
+  llvm::Value *CC = Builder.CreateFMul(RHSr, RHSr); // c*c
+  llvm::Value *DD = Builder.CreateFMul(RHSi, RHSi); // d*d
+  llvm::Value *CCpDD = Builder.CreateFAdd(CC, DD);  // cc+dd
+
+  llvm::Value *BC = Builder.CreateFMul(LHSi, RHSr); // b*c
+  llvm::Value *AD = Builder.CreateFMul(LHSr, RHSi); // a*d
+  llvm::Value *BCmAD = Builder.CreateFSub(BC, AD);  // bc-ad
+
+  DSTr = Builder.CreateFDiv(ACpBD, CCpDD);
+  DSTi = Builder.CreateFDiv(BCmAD, CCpDD);
+  return ComplexPairTy(DSTr, DSTi);
+}
+
+// EmitFAbs - Emit a call to @llvm.fabs.
+static llvm::Value *EmitllvmFAbs(CodeGenFunction &CGF, llvm::Value *Value) {
+  llvm::Function *Func =
+      CGF.CGM.getIntrinsic(llvm::Intrinsic::fabs, Value->getType());
+  llvm::Value *Call = CGF.Builder.CreateCall(Func, Value);
+  return Call;
+}
+
+// EmitRangeReductionDiv - Implements Smith's algorithm for complex division.
+// SMITH, R. L. Algorithm 116: Complex division. Commun. ACM 5, 8 (1962).
+ComplexPairTy ComplexExprEmitter::EmitRangeReductionDiv(llvm::Value *LHSr,
+                                                        llvm::Value *LHSi,
+                                                        llvm::Value *RHSr,
+                                                        llvm::Value *RHSi) {
+  // (a + ib) / (c + id) = (e + if)
+  llvm::Value *FAbsRHSr = EmitllvmFAbs(CGF, RHSr); // |c|
+  llvm::Value *FAbsRHSi = EmitllvmFAbs(CGF, RHSi); // |d|
+  // |c| >= |d|
+  llvm::Value *IsR = Builder.CreateFCmpUGT(FAbsRHSr, FAbsRHSi, "abs_cmp");
+
+  llvm::BasicBlock *TrueBB =
+      CGF.createBasicBlock("abs_rhsr_greater_or_equal_abs_rhsi");
+  llvm::BasicBlock *FalseBB =
+      CGF.createBasicBlock("abs_rhsr_less_than_abs_rhsi");
+  llvm::BasicBlock *ContBB = CGF.createBasicBlock("complex_div");
+  Builder.CreateCondBr(IsR, TrueBB, FalseBB);
+
+  CGF.EmitBlock(TrueBB);
+  // abs(c) >= abs(d)
+  // r = d/c
+  // tmp = c + rd
+  // e = (a + br)/tmp
+  // f = (b - ar)/tmp
+  llvm::Value *DdC = Builder.CreateFDiv(RHSi, RHSr); // r=d/c
+
+  llvm::Value *RD = Builder.CreateFMul(DdC, RHSi);  // rd
+  llvm::Value *CpRD = Builder.CreateFAdd(RHSr, RD); // tmp=c+rd
+
+  llvm::Value *T3 = Builder.CreateFMul(LHSi, DdC);   // br
+  llvm::Value *T4 = Builder.CreateFAdd(LHSr, T3);    // a+br
+  llvm::Value *DSTTr = Builder.CreateFDiv(T4, CpRD); // (a+br)/tmp
+
+  llvm::Value *T5 = Builder.CreateFMul(LHSr, DdC);   // ar
+  llvm::Value *T6 = Builder.CreateFSub(LHSi, T5);    // b-ar
+  llvm::Value *DSTTi = Builder.CreateFDiv(T6, CpRD); // (b-ar)/tmp
+  Builder.CreateBr(ContBB);
+
+  CGF.EmitBlock(FalseBB);
+  // abs(c) < abs(d)
+  // r = c/d
+  // tmp = d + rc
+  // e = (ar + b)/tmp
+  // f = (br - a)/tmp
+  llvm::Value *CdD = Builder.CreateFDiv(RHSr, RHSi); // r=c/d
+
+  llvm::Value *RC = Builder.CreateFMul(CdD, RHSr);  // rc
+  llvm::Value *DpRC = Builder.CreateFAdd(RHSi, RC); // tmp=d+rc
+
+  llvm::Value *T7 = Builder.CreateFMul(LHSr, RC);    // ar
+  llvm::Value *T8 = Builder.CreateFAdd(T7, LHSi);    // ar+b
+  llvm::Value *DSTFr = Builder.CreateFDiv(T8, DpRC); // (ar+b)/tmp
+
+  llvm::Value *T9 = Builder.CreateFMul(LHSi, CdD);    // br
+  llvm::Value *T10 = Builder.CreateFSub(T9, LHSr);    // br-a
+  llvm::Value *DSTFi = Builder.CreateFDiv(T10, DpRC); // (br-a)/tmp
+  Builder.CreateBr(ContBB);
+
+  // Phi together the computation paths.
+  CGF.EmitBlock(ContBB);
+  llvm::PHINode *VALr = Builder.CreatePHI(DSTTr->getType(), 2);
+  VALr->addIncoming(DSTTr, TrueBB);
+  VALr->addIncoming(DSTFr, FalseBB);
+  llvm::PHINode *VALi = Builder.CreatePHI(DSTTi->getType(), 2);
+  VALi->addIncoming(DSTTi, TrueBB);
+  VALi->addIncoming(DSTFi, FalseBB);
+  return ComplexPairTy(VALr, VALi);
+}
+
 // See C11 Annex G.5.1 for the semantics of multiplicative operators on complex
 // typed values.
 ComplexPairTy ComplexExprEmitter::EmitBinDiv(const BinOpInfo &Op) {
   llvm::Value *LHSr = Op.LHS.first, *LHSi = Op.LHS.second;
   llvm::Value *RHSr = Op.RHS.first, *RHSi = Op.RHS.second;
-
   llvm::Value *DSTr, *DSTi;
   if (LHSr->getType()->isFloatingPointTy()) {
-    // If we have a complex operand on the RHS and FastMath is not allowed, we
-    // delegate to a libcall to handle all of the complexities and minimize
-    // underflow/overflow cases. When FastMath is allowed we construct the
-    // divide inline using the same algorithm as for integer operands.
-    //
-    // FIXME: We would be able to avoid the libcall in many places if we
-    // supported imaginary types in addition to complex types.
     CodeGenFunction::CGFPOptionsRAII FPOptsRAII(CGF, Op.FPFeatures);
-    if (RHSi && !CGF.getLangOpts().FastMath) {
+    if (!RHSi) {
+      assert(LHSi && "Can have at most one non-complex operand!");
+
+      DSTr = Builder.CreateFDiv(LHSr, RHSr);
+      DSTi = Builder.CreateFDiv(LHSi, RHSr);
+      return ComplexPairTy(DSTr, DSTi);
+    }
+    llvm::Value *OrigLHSi = LHSi;
+    if (!LHSi)
+      LHSi = llvm::Constant::getNullValue(RHSi->getType());
+    if (Op.FPFeatures.getComplexRange() == LangOptions::CX_Fortran)
+      return EmitRangeReductionDiv(LHSr, LHSi, RHSr, RHSi);
+    else if (Op.FPFeatures.getComplexRange() == LangOptions::CX_Limited)
+      return EmitAlgebraicDiv(LHSr, LHSi, RHSr, RHSi);
+    else if (!CGF.getLangOpts().FastMath) {
+      LHSi = OrigLHSi;
+      // If we have a complex operand on the RHS and FastMath is not allowed, we
+      // delegate to a libcall to handle all of the complexities and minimize
+      // underflow/overflow cases. When FastMath is allowed we construct the
+      // divide inline using the same algorithm as for integer operands.
+      //
+      // FIXME: We would be able to avoid the libcall in many places if we
+      // supported imaginary types in addition to complex types.
       BinOpInfo LibCallOp = Op;
       // If LHS was a real, supply a null imaginary part.
       if (!LHSi)
@@ -884,30 +1008,8 @@ ComplexPairTy ComplexExprEmitter::EmitBinDiv(const BinOpInfo &Op) {
       case llvm::Type::FP128TyID:
         return EmitComplexBinOpLibCall("__divtc3", LibCallOp);
       }
-    } else if (RHSi) {
-      if (!LHSi)
-        LHSi = llvm::Constant::getNullValue(RHSi->getType());
-
-      // (a+ib) / (c+id) = ((ac+bd)/(cc+dd)) + i((bc-ad)/(cc+dd))
-      llvm::Value *AC = Builder.CreateFMul(LHSr, RHSr); // a*c
-      llvm::Value *BD = Builder.CreateFMul(LHSi, RHSi); // b*d
-      llvm::Value *ACpBD = Builder.CreateFAdd(AC, BD); // ac+bd
-
-      llvm::Value *CC = Builder.CreateFMul(RHSr, RHSr); // c*c
-      llvm::Value *DD = Builder.CreateFMul(RHSi, RHSi); // d*d
-      llvm::Value *CCpDD = Builder.CreateFAdd(CC, DD); // cc+dd
-
-      llvm::Value *BC = Builder.CreateFMul(LHSi, RHSr); // b*c
-      llvm::Value *AD = Builder.CreateFMul(LHSr, RHSi); // a*d
-      llvm::Value *BCmAD = Builder.CreateFSub(BC, AD); // bc-ad
-
-      DSTr = Builder.CreateFDiv(ACpBD, CCpDD);
-      DSTi = Builder.CreateFDiv(BCmAD, CCpDD);
     } else {
-      assert(LHSi && "Can have at most one non-complex operand!");
-
-      DSTr = Builder.CreateFDiv(LHSr, RHSr);
-      DSTi = Builder.CreateFDiv(LHSi, RHSr);
+      return EmitAlgebraicDiv(LHSr, LHSi, RHSr, RHSi);
     }
   } else {
     assert(Op.LHS.second && Op.RHS.second &&
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp
index eb26bfade47b..f95f3227aba7 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -2660,6 +2660,35 @@ static void CollectArgsForIntegratedAssembler(Compilation &C,
   }
 }
 
+static StringRef EnumComplexRangeToStr(LangOptions::ComplexRangeKind Range) {
+  StringRef RangeStr = "";
+  switch (Range) {
+  case LangOptions::ComplexRangeKind::CX_Limited:
+    return "-fcx-limited-range";
+    break;
+  case LangOptions::ComplexRangeKind::CX_Fortran:
+    return "-fcx-fortran-rules";
+    break;
+  default:
+    return RangeStr;
+    break;
+  }
+}
+
+static void EmitComplexRangeDiag(const Driver &D,
+                                 LangOptions::ComplexRangeKind Range1,
+                                 LangOptions::ComplexRangeKind Range2) {
+  if (Range1 != LangOptions::ComplexRangeKind::CX_Full)
+    D.Diag(clang::diag::warn_drv_overriding_option)
+        << EnumComplexRangeToStr(Range1) << EnumComplexRangeToStr(Range2);
+}
+
+static std::string RenderComplexRangeOption(std::string Range) {
+  std::string ComplexRangeStr = "-complex-range=";
+  ComplexRangeStr += Range;
+  return ComplexRangeStr;
+}
+
 static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D,
                                        bool OFastEnabled, const ArgList &Args,
                                        ArgStringList &CmdArgs,
@@ -2706,6 +2735,7 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D,
   bool StrictFPModel = false;
   StringRef Float16ExcessPrecision = "";
   StringRef BFloat16ExcessPrecision = "";
+  LangOptions::ComplexRangeKind Range = LangOptions::ComplexRangeKind::CX_Full;
 
   if (const Arg *A = Args.getLastArg(options::OPT_flimited_precision_EQ)) {
     CmdArgs.push_back("-mlimit-float-precision");
@@ -2718,6 +2748,28 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D,
     switch (optID) {
     default:
       break;
+    case options::OPT_fcx_limited_range: {
+      EmitComplexRangeDiag(D, Range, LangOptions::ComplexRangeKind::CX_Limited);
+      Range = LangOptions::ComplexRangeKind::CX_Limited;
+      std::string ComplexRangeStr = RenderComplexRangeOption("limited");
+      if (!ComplexRangeStr.empty())
+        CmdArgs.push_back(Args.MakeArgString(ComplexRangeStr));
+      break;
+    }
+    case options::OPT_fno_cx_limited_range:
+      Range = LangOptions::ComplexRangeKind::CX_Full;
+      break;
+    case options::OPT_fcx_fortran_rules: {
+      EmitComplexRangeDiag(D, Range, LangOptions::ComplexRangeKind::CX_Fortran);
+      Range = LangOptions::ComplexRangeKind::CX_Fortran;
+      std::string ComplexRangeStr = RenderComplexRangeOption("fortran");
+      if (!ComplexRangeStr.empty())
+        CmdArgs.push_back(Args.MakeArgString(ComplexRangeStr));
+      break;
+    }
+    case options::OPT_fno_cx_fortran_rules:
+      Range = LangOptions::ComplexRangeKind::CX_Full;
+      break;
     case options::OPT_ffp_model_EQ: {
       // If -ffp-model= is seen, reset to fno-fast-math
       HonorINFs = true;
@@ -2772,7 +2824,7 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D,
         D.Diag(diag::err_drv_unsupported_option_argument)
             << A->getSpelling() << Val;
       break;
-      }
+    }
     }
 
     switch (optID) {
@@ -2971,7 +3023,7 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D,
       if (!OFastEnabled)
         continue;
       [[fallthrough]];
-    case options::OPT_ffast_math:
+    case options::OPT_ffast_math: {
       HonorINFs = false;
       HonorNaNs = false;
       MathErrno = false;
@@ -2985,7 +3037,13 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D,
       // If fast-math is set then set the fp-contract mode to fast.
       FPContract = "fast";
       SeenUnsafeMathModeOption = true;
+      // ffast-math enables fortran rules for complex multiplication and
+      // division.
+      std::string ComplexRangeStr = RenderComplexRangeOption("limited");
+      if (!ComplexRangeStr.empty())
+        CmdArgs.push_back(Args.MakeArgString(ComplexRangeStr));
       break;
+    }
     case options::OPT_fno_fast_math:
       HonorINFs = true;
       HonorNaNs = true;
@@ -3139,6 +3197,15 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D,
   if (Args.hasFlag(options::OPT_fno_strict_float_cast_overflow,
                    options::OPT_fstrict_float_cast_overflow, false))
     CmdArgs.push_back("-fno-strict-float-cast-overflow");
+
+  if (const Arg *A = Args.getLastArg(options::OPT_fcx_limited_range))
+    CmdArgs.push_back("-fcx-limited-range");
+  if (const Arg *A = Args.getLastArg(options::OPT_fcx_fortran_rules))
+    CmdArgs.push_back("-fcx-fortran-rules");
+  if (const Arg *A = Args.getLastArg(options::OPT_fno_cx_limited_range))
+    CmdArgs.push_back("-fno-cx-limited-range");
+  if (const Arg *A = Args.getLastArg(options::OPT_fno_cx_fortran_rules))
+    CmdArgs.push_back("-fno-cx-fortran-rules");
 }
 
 static void RenderAnalyzerOptions(const ArgList &Args, ArgStringList &CmdArgs,
diff --git a/clang/lib/Parse/ParsePragma.cpp b/clang/lib/Parse/ParsePragma.cpp
index efdf7c90f977..730ac1a0fee5 100644
--- a/clang/lib/Parse/ParsePragma.cpp
+++ b/clang/lib/Parse/ParsePragma.cpp
@@ -137,7 +137,20 @@ struct PragmaSTDC_CX_LIMITED_RANGEHandler : public PragmaHandler {
   void HandlePragma(Preprocessor &PP, PragmaIntroducer Introducer,
                     Token &Tok) override {
     tok::OnOffSwitch OOS;
-    PP.LexOnOffSwitch(OOS);
+    if (PP.LexOnOffSwitch(OOS))
+      return;
+
+    MutableArrayRef<Token> Toks(
+        PP.getPreprocessorAllocator().Allocate<Token>(1), 1);
+
+    Toks[0].startToken();
+    Toks[0].setKind(tok::annot_pragma_cx_limited_range);
+    Toks[0].setLocation(Tok.getLocation());
+    Toks[0].setAnnotationEndLoc(Tok.getLocation());
+    Toks[0].setAnnotationValue(
+        reinterpret_cast<void *>(static_cast<uintptr_t>(OOS)));
+    PP.EnterTokenStream(Toks, /*DisableMacroExpansion=*/true,
+                        /*IsReinject=*/false);
   }
 };
 
@@ -888,6 +901,31 @@ void Parser::HandlePragmaFEnvRound() {
   Actions.ActOnPragmaFEnvRound(PragmaLoc, RM);
 }
 
+void Parser::HandlePragmaCXLimitedRange() {
+  assert(Tok.is(tok::annot_pragma_cx_limited_range));
+  tok::OnOffSwitch OOS = static_cast<tok::OnOffSwitch>(
+      reinterpret_cast<uintptr_t>(Tok.getAnnotationValue()));
+
+  LangOptions::ComplexRangeKind Range;
+  switch (OOS) {
+  case tok::OOS_ON:
+    Range = LangOptions::CX_Limited;
+    break;
+  case tok::OOS_OFF:
+    Range = LangOptions::CX_Full;
+    break;
+  case tok::OOS_DEFAULT:
+    // According to ISO C99 standard chapter 7.3.4, the default value
+    // for the pragma is ``off'. -fcx-limited-range and -fcx-fortran-rules
+    // control the default value of these pragmas.
+    Range = getLangOpts().getComplexRange();
+    break;
+  }
+
+  SourceLocation PragmaLoc = ConsumeAnnotationToken();
+  Actions.ActOnPragmaCXLimitedRange(PragmaLoc, Range);
+}
+
 StmtResult Parser::HandlePragmaCaptured()
 {
   assert(Tok.is(tok::annot_pragma_captured));
diff --git a/clang/lib/Parse/ParseStmt.cpp b/clang/lib/Parse/ParseStmt.cpp
index 918afdc2baea..d0ff33bd1379 100644
--- a/clang/lib/Parse/ParseStmt.cpp
+++ b/clang/lib/Parse/ParseStmt.cpp
@@ -444,6 +444,14 @@ Retry:
     ConsumeAnnotationToken();
     return StmtError();
 
+  case tok::annot_pragma_cx_limited_range:
+    ProhibitAttributes(CXX11Attrs);
+    ProhibitAttributes(GNUAttrs);
+    Diag(Tok, diag::err_pragma_file_or_compound_scope)
+        << "STDC CX_LIMITED_RANGE";
+    ConsumeAnnotationToken();
+    return StmtError();
+
   case tok::annot_pragma_float_control:
     ProhibitAttributes(CXX11Attrs);
     ProhibitAttributes(GNUAttrs);
@@ -1066,6 +1074,9 @@ void Parser::ParseCompoundStatementLeadingPragmas() {
     case tok::annot_pragma_fenv_round:
       HandlePragmaFEnvRound();
       break;
+    case tok::annot_pragma_cx_limited_range:
+      HandlePragmaCXLimitedRange();
+      break;
     case tok::annot_pragma_float_control:
       HandlePragmaFloatControl();
       break;
diff --git a/clang/lib/Parse/Parser.cpp b/clang/lib/Parse/Parser.cpp
index 1baeb2aeb021..ec67faf7dcaf 100644
--- a/clang/lib/Parse/Parser.cpp
+++ b/clang/lib/Parse/Parser.cpp
@@ -844,6 +844,9 @@ Parser::ParseExternalDeclaration(ParsedAttributes &Attrs,
   case tok::annot_pragma_fenv_round:
     HandlePragmaFEnvRound();
     return nullptr;
+  case tok::annot_pragma_cx_limited_range:
+    HandlePragmaCXLimitedRange();
+    return nullptr;
   case tok::annot_pragma_float_control:
     HandlePragmaFloatControl();
     return nullptr;
diff --git a/clang/lib/Sema/SemaAttr.cpp b/clang/lib/Sema/SemaAttr.cpp
index 79271c872627..0dcf42e48997 100644
--- a/clang/lib/Sema/SemaAttr.cpp
+++ b/clang/lib/Sema/SemaAttr.cpp
@@ -1352,6 +1352,14 @@ void Sema::ActOnPragmaFEnvAccess(SourceLocation Loc, bool IsEnabled) {
   CurFPFeatures = NewFPFeatures.applyOverrides(getLangOpts());
 }
 
+void Sema::ActOnPragmaCXLimitedRange(SourceLocation Loc,
+                                     LangOptions::ComplexRangeKind Range) {
+  FPOptionsOverride NewFPFeatures = CurFPFeatureOverrides();
+  NewFPFeatures.setComplexRangeOverride(Range);
+  FpPragmaStack.Act(Loc, PSK_Set, StringRef(), NewFPFeatures);
+  CurFPFeatures = NewFPFeatures.applyOverrides(getLangOpts());
+}
+
 void Sema::ActOnPragmaFPExceptions(SourceLocation Loc,
                                    LangOptions::FPExceptionModeKind FPE) {
   setExceptionMode(Loc, FPE);
diff --git a/clang/test/CodeGen/complex-math.c b/clang/test/CodeGen/complex-math.c
index c59baaa45236..a44aa0014a65 100644
--- a/clang/test/CodeGen/complex-math.c
+++ b/clang/test/CodeGen/complex-math.c
@@ -5,7 +5,7 @@
 // RUN: %clang_cc1 %s -O0 -emit-llvm -triple armv7-none-linux-gnueabi -o - | FileCheck %s --check-prefix=ARM
 // RUN: %clang_cc1 %s -O0 -emit-llvm -triple armv7-none-linux-gnueabihf -o - | FileCheck %s --check-prefix=ARMHF
 // RUN: %clang_cc1 %s -O0 -emit-llvm -triple thumbv7k-apple-watchos2.0 -o - -target-abi aapcs16 | FileCheck %s --check-prefix=ARM7K
-// RUN: %clang_cc1 %s -O0 -emit-llvm -triple aarch64-unknown-unknown -ffast-math -ffp-contract=fast -o - | FileCheck %s --check-prefix=AARCH64-FASTMATH
+// RUN: %clang_cc1 %s -O0 -emit-llvm -triple aarch64-unknown-unknown -ffast-math -ffp-contract=fast -complex-range=fortran -o - | FileCheck %s --check-prefix=AARCH64-FASTMATH
 // RUN: %clang_cc1 %s -O0 -emit-llvm -triple spir -o - | FileCheck %s --check-prefix=SPIR
 
 float _Complex add_float_rr(float a, float b) {
@@ -135,24 +135,68 @@ float _Complex div_float_rc(float a, float _Complex b) {
 
   // SPIR: call spir_func {{.*}} @__divsc3(
 
-  // a / b = (A+iB) / (C+iD) = ((AC+BD)/(CC+DD)) + i((BC-AD)/(CC+DD))
+  // a / b = (A+iB) / (C+iD) = (E+iF)
+  // if (|C| >= |D|)
+  //   DdC = D/C
+  //   CpRD = C+DdC*D
+  //   E = (A+B*DdC)/CpRD
+  //   F = (B-A*DdC)/CpRD
+  // else
+  //   CdD = C/D
+  //   DpRC= D+CdD*C
+  //   E = (A*CdD+B)/DpRC
+  //   F = (B*CdD-A)/DpRC
   // AARCH64-FASTMATH-LABEL: @div_float_rc(float noundef nofpclass(nan inf) %a, [2 x float] noundef nofpclass(nan inf) alignstack(8) %b.coerce)
-  // A = a
-  // B = 0
-  //
-  // AARCH64-FASTMATH: [[AC:%.*]] = fmul fast float
-  // BD = 0
-  // ACpBD = AC
-  //
-  // AARCH64-FASTMATH: [[CC:%.*]] = fmul fast float
-  // AARCH64-FASTMATH: [[DD:%.*]] = fmul fast float
-  // AARCH64-FASTMATH: [[CCpDD:%.*]] = fadd fast float
-  //
-  // BC = 0
-  // AARCH64-FASTMATH: [[AD:%.*]] = fmul fast float
-  //
-  // AARCH64-FASTMATH: fdiv fast float
-  // AARCH64-FASTMATH: fdiv fast float
+  // |C|
+  // AARCH64-FASTMATH: call {{.*}}float @llvm.fabs.f32(float {{.*}})
+  // |D|
+  // AARCH64-FASTMATH-NEXT: call {{.*}}float @llvm.fabs.f32(float {{.*}})
+  // AARCH64-FASTMATH-NEXT: fcmp {{.*}}ugt float
+  // AARCH64-FASTMATH-NEXT: br i1 {{.*}}, label
+  // AARCH64-FASTMATH:      abs_rhsr_greater_or_equal_abs_rhsi:
+
+  // |C| >= |D|
+  // DdC=D/C
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}float
+
+  // CpRD=C+CdC*D
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}float
+  // AARCH64-FASTMATH-NEXT: fadd {{.*}}float
+
+  // A+BR/CpRD
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}float
+  // AARCH64-FASTMATH-NEXT: fadd {{.*}}float
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}float
+
+  // B-AR/CpRD
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}float
+  // AARCH64-FASTMATH-NEXT: fsub {{.*}}float
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}float
+  // AARCH64-FASTMATH-NEXT: br label
+  // AARCH64-FASTMATH:      abs_rhsr_less_than_abs_rhsi:
+
+  // |C| < |D|
+  // CdD=C/D
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}float
+
+  // DpRC=D+CdD*C
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}float
+  // AARCH64-FASTMATH-NEXT: fadd {{.*}}float
+
+  // (A*CdD+B)/DpRC
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}float
+  // AARCH64-FASTMATH-NEXT: fadd {{.*}}float
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}float
+
+  // (BCdD-A)/DpRC
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}float
+  // AARCH64-FASTMATH-NEXT: fsub {{.*}}float
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}float
+
+  // AARCH64-FASTMATH-NEXT: br label
+  // AARCH64-FASTMATH:      complex_div:
+  // AARCH64-FASTMATH-NEXT: phi {{.*}}float
+  // AARCH64-FASTMATH-NEXT: phi {{.*}}float
   // AARCH64-FASTMATH: ret
   return a / b;
 }
@@ -164,24 +208,68 @@ float _Complex div_float_cc(float _Complex a, float _Complex b) {
 
   // SPIR: call spir_func {{.*}} @__divsc3(
 
-  // a / b = (A+iB) / (C+iD) = ((AC+BD)/(CC+DD)) + i((BC-AD)/(CC+DD))
+  // a / b = (A+iB) / (C+iD) = (E+iF)
+  // if (|C| >= |D|)
+  //   DdC = D/C
+  //   CpRD = C+DdC*D
+  //   E = (A+B*DdC)/CpRD
+  //   F = (B-A*DdC)/CpRD
+  // else
+  //   CdD = C/D
+  //   DpRC= D+CdD*C
+  //   E = (A*CdD+B)/DpRC
+  //   F = (B*CdD-A)/DpRC
   // AARCH64-FASTMATH-LABEL: @div_float_cc([2 x float] noundef nofpclass(nan inf) alignstack(8) %a.coerce, [2 x float] noundef nofpclass(nan inf) alignstack(8) %b.coerce)
-  //
-  // AARCH64-FASTMATH: [[AC:%.*]] = fmul fast float
-  // AARCH64-FASTMATH: [[BD:%.*]] = fmul fast float
-  // AARCH64-FASTMATH: [[ACpBD:%.*]] = fadd fast float
-  //
-  // AARCH64-FASTMATH: [[CC:%.*]] = fmul fast float
-  // AARCH64-FASTMATH: [[DD:%.*]] = fmul fast float
-  // AARCH64-FASTMATH: [[CCpDD:%.*]] = fadd fast float
-  //
-  // AARCH64-FASTMATH: [[BC:%.*]] = fmul fast float
-  // AARCH64-FASTMATH: [[AD:%.*]] = fmul fast float
-  // AARCH64-FASTMATH: [[BCmAD:%.*]] = fsub fast float
-  //
-  // AARCH64-FASTMATH: fdiv fast float
-  // AARCH64-FASTMATH: fdiv fast float
-  // AARCH64-FASTMATH: ret
+  // |C|
+  // AARCH64-FASTMATH: call {{.*}}float @llvm.fabs.f32(float {{.*}})
+  // |D|
+  // AARCH64-FASTMATH-NEXT: call {{.*}}float @llvm.fabs.f32(float {{.*}})
+  // AARCH64-FASTMATH-NEXT: fcmp {{.*}}ugt float
+  // AARCH64-FASTMATH-NEXT: br i1 {{.*}}, label
+  // AARCH64-FASTMATH:      abs_rhsr_greater_or_equal_abs_rhsi:
+
+  // |C| >= |D|
+  // DdC=D/C
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}float
+
+  // CpRD=C+CdC*D
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}float
+  // AARCH64-FASTMATH-NEXT: fadd {{.*}}float
+
+  // A+BR/CpRD
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}float
+  // AARCH64-FASTMATH-NEXT: fadd {{.*}}float
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}float
+
+  // B-AR/CpRD
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}float
+  // AARCH64-FASTMATH-NEXT: fsub {{.*}}float
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}float
+  // AARCH64-FASTMATH-NEXT: br label
+  // AARCH64-FASTMATH:      abs_rhsr_less_than_abs_rhsi:
+
+  // |C| < |D|
+  // CdD=C/D
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}float
+
+  // DpRC=D+CdD*C
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}float
+  // AARCH64-FASTMATH-NEXT: fadd {{.*}}float
+
+  // (A*CdD+B)/DpRC
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}float
+  // AARCH64-FASTMATH-NEXT: fadd {{.*}}float
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}float
+
+  // (BCdD-A)/DpRC
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}float
+  // AARCH64-FASTMATH-NEXT: fsub {{.*}}float
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}float
+
+  // AARCH64-FASTMATH-NEXT: br label
+  // AARCH64-FASTMATH:      complex_div:
+  // AARCH64-FASTMATH-NEXT: phi {{.*}}float
+  // AARCH64-FASTMATH-NEXT: phi {{.*}}float
   return a / b;
 }
 
@@ -312,24 +400,68 @@ double _Complex div_double_rc(double a, double _Complex b) {
 
   // SPIR: call spir_func {{.*}} @__divdc3(
 
-  // a / b = (A+iB) / (C+iD) = ((AC+BD)/(CC+DD)) + i((BC-AD)/(CC+DD))
+  // a / b = (A+iB) / (C+iD) = (E+iF)
+  // if (|C| >= |D|)
+  //   DdC = D/C
+  //   CpRD = C+DdC*D
+  //   E = (A+B*DdC)/CpRD
+  //   F = (B-A*DdC)/CpRD
+  // else
+  //   CdD = C/D
+  //   DpRC= D+CdD*C
+  //   E = (A*CdD+B)/DpRC
+  //   F = (B*CdD-A)/DpRC
   // AARCH64-FASTMATH-LABEL: @div_double_rc(double noundef nofpclass(nan inf) %a, [2 x double] noundef nofpclass(nan inf) alignstack(8) %b.coerce)
-  // A = a
-  // B = 0
-  //
-  // AARCH64-FASTMATH: [[AC:%.*]] = fmul fast double
-  // BD = 0
-  // ACpBD = AC
-  //
-  // AARCH64-FASTMATH: [[CC:%.*]] = fmul fast double
-  // AARCH64-FASTMATH: [[DD:%.*]] = fmul fast double
-  // AARCH64-FASTMATH: [[CCpDD:%.*]] = fadd fast double
-  //
-  // BC = 0
-  // AARCH64-FASTMATH: [[AD:%.*]] = fmul fast double
-  //
-  // AARCH64-FASTMATH: fdiv fast double
-  // AARCH64-FASTMATH: fdiv fast double
+  // |C|
+  // AARCH64-FASTMATH: call {{.*}}double @llvm.fabs.f64(double {{.*}})
+  // |D|
+  // AARCH64-FASTMATH-NEXT: call {{.*}}double @llvm.fabs.f64(double {{.*}})
+  // AARCH64-FASTMATH-NEXT: fcmp {{.*}}ugt double
+  // AARCH64-FASTMATH-NEXT: br i1 {{.*}}, label
+  // AARCH64-FASTMATH:      abs_rhsr_greater_or_equal_abs_rhsi:
+
+  // |C| >= |D|
+  // DdC=D/C
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}double
+
+  // CpRD=C+CdC*D
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}double
+  // AARCH64-FASTMATH-NEXT: fadd {{.*}}double
+
+  // A+BR/CpRD
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}double
+  // AARCH64-FASTMATH-NEXT: fadd {{.*}}double
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}double
+
+  // B-AR/CpRD
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}double
+  // AARCH64-FASTMATH-NEXT: fsub {{.*}}double
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}double
+  // AARCH64-FASTMATH-NEXT: br label
+  // AARCH64-FASTMATH:      abs_rhsr_less_than_abs_rhsi:
+
+  // |C| < |D|
+  // CdD=C/D
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}double
+
+  // DpRC=D+CdD*C
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}double
+  // AARCH64-FASTMATH-NEXT: fadd {{.*}}double
+
+  // (A*CdD+B)/DpRC
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}double
+  // AARCH64-FASTMATH-NEXT: fadd {{.*}}double
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}double
+
+  // (BCdD-A)/DpRC
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}double
+  // AARCH64-FASTMATH-NEXT: fsub {{.*}}double
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}double
+
+  // AARCH64-FASTMATH-NEXT: br label
+  // AARCH64-FASTMATH:      complex_div:
+  // AARCH64-FASTMATH-NEXT: phi {{.*}}double
+  // AARCH64-FASTMATH-NEXT: phi {{.*}}double
   // AARCH64-FASTMATH: ret
   return a / b;
 }
@@ -341,23 +473,68 @@ double _Complex div_double_cc(double _Complex a, double _Complex b) {
 
   // SPIR: call spir_func {{.*}} @__divdc3(
 
-  // a / b = (A+iB) / (C+iD) = ((AC+BD)/(CC+DD)) + i((BC-AD)/(CC+DD))
+  // a / b = (A+iB) / (C+iD) = (E+iF)
+  // if (|C| >= |D|)
+  //   DdC = D/C
+  //   CpRD = C+DdC*D
+  //   E = (A+B*DdC)/CpRD
+  //   F = (B-A*DdC)/CpRD
+  // else
+  //   CdD = C/D
+  //   DpRC= D+CdD*C
+  //   E = (A*CdD+B)/DpRC
+  //   F = (B*CdD-A)/DpRC
   // AARCH64-FASTMATH-LABEL: @div_double_cc([2 x double] noundef nofpclass(nan inf) alignstack(8) %a.coerce, [2 x double] noundef nofpclass(nan inf) alignstack(8) %b.coerce)
-  //
-  // AARCH64-FASTMATH: [[AC:%.*]] = fmul fast double
-  // AARCH64-FASTMATH: [[BD:%.*]] = fmul fast double
-  // AARCH64-FASTMATH: [[ACpBD:%.*]] = fadd fast double
-  //
-  // AARCH64-FASTMATH: [[CC:%.*]] = fmul fast double
-  // AARCH64-FASTMATH: [[DD:%.*]] = fmul fast double
-  // AARCH64-FASTMATH: [[CCpDD:%.*]] = fadd fast double
-  //
-  // AARCH64-FASTMATH: [[BC:%.*]] = fmul fast double
-  // AARCH64-FASTMATH: [[AD:%.*]] = fmul fast double
-  // AARCH64-FASTMATH: [[BCmAD:%.*]] = fsub fast double
-  //
-  // AARCH64-FASTMATH: fdiv fast double
-  // AARCH64-FASTMATH: fdiv fast double
+  // |C|
+  // AARCH64-FASTMATH: call {{.*}}double @llvm.fabs.f64(double {{.*}})
+  // |D|
+  // AARCH64-FASTMATH-NEXT: call {{.*}}double @llvm.fabs.f64(double {{.*}})
+  // AARCH64-FASTMATH-NEXT: fcmp {{.*}}ugt double
+  // AARCH64-FASTMATH-NEXT: br i1 {{.*}}, label
+  // AARCH64-FASTMATH:      abs_rhsr_greater_or_equal_abs_rhsi:
+
+  // |C| >= |D|
+  // DdC=D/C
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}double
+
+  // CpRD=C+CdC*D
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}double
+  // AARCH64-FASTMATH-NEXT: fadd {{.*}}double
+
+  // A+BR/CpRD
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}double
+  // AARCH64-FASTMATH-NEXT: fadd {{.*}}double
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}double
+
+  // B-AR/CpRD
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}double
+  // AARCH64-FASTMATH-NEXT: fsub {{.*}}double
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}double
+  // AARCH64-FASTMATH-NEXT: br label
+  // AARCH64-FASTMATH:      abs_rhsr_less_than_abs_rhsi:
+
+  // |C| < |D|
+  // CdD=C/D
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}double
+
+  // DpRC=D+CdD*C
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}double
+  // AARCH64-FASTMATH-NEXT: fadd {{.*}}double
+
+  // (A*CdD+B)/DpRC
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}double
+  // AARCH64-FASTMATH-NEXT: fadd {{.*}}double
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}double
+
+  // (BCdD-A)/DpRC
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}double
+  // AARCH64-FASTMATH-NEXT: fsub {{.*}}double
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}double
+
+  // AARCH64-FASTMATH-NEXT: br label
+  // AARCH64-FASTMATH:      complex_div:
+  // AARCH64-FASTMATH-NEXT: phi {{.*}}double
+  // AARCH64-FASTMATH-NEXT: phi {{.*}}double
   // AARCH64-FASTMATH: ret
   return a / b;
 }
@@ -505,24 +682,68 @@ long double _Complex div_long_double_rc(long double a, long double _Complex b) {
   // PPC: ret
   // SPIR: call spir_func {{.*}} @__divdc3(
 
-  // a / b = (A+iB) / (C+iD) = ((AC+BD)/(CC+DD)) + i((BC-AD)/(CC+DD))
+  // a / b = (A+iB) / (C+iD) = (E+iF)
+  // if (|C| >= |D|)
+  //   DdC = D/C
+  //   CpRD = C+DdC*D
+  //   E = (A+B*DdC)/CpRD
+  //   F = (B-A*DdC)/CpRD
+  // else
+  //   CdD = C/D
+  //   DpRC= D+CdD*C
+  //   E = (A*CdD+B)/DpRC
+  //   F = (B*CdD-A)/DpRC
   // AARCH64-FASTMATH-LABEL: @div_long_double_rc(fp128 noundef nofpclass(nan inf) %a, [2 x fp128] noundef nofpclass(nan inf) alignstack(16) %b.coerce)
-  // A = a
-  // B = 0
-  //
-  // AARCH64-FASTMATH: [[AC:%.*]] = fmul fast fp128
-  // BD = 0
-  // ACpBD = AC
-  //
-  // AARCH64-FASTMATH: [[CC:%.*]] = fmul fast fp128
-  // AARCH64-FASTMATH: [[DD:%.*]] = fmul fast fp128
-  // AARCH64-FASTMATH: [[CCpDD:%.*]] = fadd fast fp128
-  //
-  // BC = 0
-  // AARCH64-FASTMATH: [[AD:%.*]] = fmul fast fp128
-  //
-  // AARCH64-FASTMATH: fdiv fast fp128
-  // AARCH64-FASTMATH: fdiv fast fp128
+  // |C|
+  // AARCH64-FASTMATH: call {{.*}}fp128 @llvm.fabs.f128(fp128 {{.*}})
+  // |D|
+  // AARCH64-FASTMATH-NEXT: call {{.*}}fp128 @llvm.fabs.f128(fp128 {{.*}})
+  // AARCH64-FASTMATH-NEXT: fcmp {{.*}}ugt fp128
+  // AARCH64-FASTMATH-NEXT: br i1 {{.*}}, label
+  // AARCH64-FASTMATH:      abs_rhsr_greater_or_equal_abs_rhsi:
+
+  // |C| >= |D|
+  // DdC=D/C
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}fp128
+
+  // CpRD=C+CdC*D
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}fp128
+  // AARCH64-FASTMATH-NEXT: fadd {{.*}}fp128
+
+  // A+BR/CpRD
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}fp128
+  // AARCH64-FASTMATH-NEXT: fadd {{.*}}fp128
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}fp128
+
+  // B-AR/CpRD
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}fp128
+  // AARCH64-FASTMATH-NEXT: fsub {{.*}}fp128
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}fp128
+  // AARCH64-FASTMATH-NEXT: br label
+  // AARCH64-FASTMATH:      abs_rhsr_less_than_abs_rhsi:
+
+  // |C| < |D|
+  // CdD=C/D
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}fp128
+
+  // DpRC=D+CdD*C
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}fp128
+  // AARCH64-FASTMATH-NEXT: fadd {{.*}}fp128
+
+  // (A*CdD+B)/DpRC
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}fp128
+  // AARCH64-FASTMATH-NEXT: fadd {{.*}}fp128
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}fp128
+
+  // (BCdD-A)/DpRC
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}fp128
+  // AARCH64-FASTMATH-NEXT: fsub {{.*}}fp128
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}fp128
+
+  // AARCH64-FASTMATH-NEXT: br label
+  // AARCH64-FASTMATH:      complex_div:
+  // AARCH64-FASTMATH-NEXT: phi {{.*}}fp128
+  // AARCH64-FASTMATH-NEXT: phi {{.*}}fp128
   // AARCH64-FASTMATH: ret
   return a / b;
 }
@@ -537,23 +758,68 @@ long double _Complex div_long_double_cc(long double _Complex a, long double _Com
   // PPC: ret
   // SPIR: call spir_func {{.*}} @__divdc3(
 
-  // a / b = (A+iB) / (C+iD) = ((AC+BD)/(CC+DD)) + i((BC-AD)/(CC+DD))
+  // a / b = (A+iB) / (C+iD) = (E+iF)
+  // if (|C| >= |D|)
+  //   DdC = D/C
+  //   CpRD = C+DdC*D
+  //   E = (A+B*DdC)/CpRD
+  //   F = (B-A*DdC)/CpRD
+  // else
+  //   CdD = C/D
+  //   DpRC= D+CdD*C
+  //   E = (A*CdD+B)/DpRC
+  //   F = (B*CdD-A)/DpRC
   // AARCH64-FASTMATH-LABEL: @div_long_double_cc([2 x fp128] noundef nofpclass(nan inf) alignstack(16) %a.coerce, [2 x fp128] noundef nofpclass(nan inf) alignstack(16) %b.coerce)
-  //
-  // AARCH64-FASTMATH: [[AC:%.*]] = fmul fast fp128
-  // AARCH64-FASTMATH: [[BD:%.*]] = fmul fast fp128
-  // AARCH64-FASTMATH: [[ACpBD:%.*]] = fadd fast fp128
-  //
-  // AARCH64-FASTMATH: [[CC:%.*]] = fmul fast fp128
-  // AARCH64-FASTMATH: [[DD:%.*]] = fmul fast fp128
-  // AARCH64-FASTMATH: [[CCpDD:%.*]] = fadd fast fp128
-  //
-  // AARCH64-FASTMATH: [[BC:%.*]] = fmul fast fp128
-  // AARCH64-FASTMATH: [[AD:%.*]] = fmul fast fp128
-  // AARCH64-FASTMATH: [[BCmAD:%.*]] = fsub fast fp128
-  //
-  // AARCH64-FASTMATH: fdiv fast fp128
-  // AARCH64-FASTMATH: fdiv fast fp128
+  // |C|
+  // AARCH64-FASTMATH: call {{.*}}fp128 @llvm.fabs.f128(fp128 {{.*}})
+  // |D|
+  // AARCH64-FASTMATH-NEXT: call {{.*}}fp128 @llvm.fabs.f128(fp128 {{.*}})
+  // AARCH64-FASTMATH-NEXT: fcmp {{.*}}ugt fp128
+  // AARCH64-FASTMATH-NEXT: br i1 {{.*}}, label
+  // AARCH64-FASTMATH:      abs_rhsr_greater_or_equal_abs_rhsi:
+
+  // |C| >= |D|
+  // DdC=D/C
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}fp128
+
+  // CpRD=C+CdC*D
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}fp128
+  // AARCH64-FASTMATH-NEXT: fadd {{.*}}fp128
+
+  // A+BR/CpRD
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}fp128
+  // AARCH64-FASTMATH-NEXT: fadd {{.*}}fp128
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}fp128
+
+  // B-AR/CpRD
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}fp128
+  // AARCH64-FASTMATH-NEXT: fsub {{.*}}fp128
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}fp128
+  // AARCH64-FASTMATH-NEXT: br label
+  // AARCH64-FASTMATH:      abs_rhsr_less_than_abs_rhsi:
+
+  // |C| < |D|
+  // CdD=C/D
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}fp128
+
+  // DpRC=D+CdD*C
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}fp128
+  // AARCH64-FASTMATH-NEXT: fadd {{.*}}fp128
+
+  // (A*CdD+B)/DpRC
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}fp128
+  // AARCH64-FASTMATH-NEXT: fadd {{.*}}fp128
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}fp128
+
+  // (BCdD-A)/DpRC
+  // AARCH64-FASTMATH-NEXT: fmul {{.*}}fp128
+  // AARCH64-FASTMATH-NEXT: fsub {{.*}}fp128
+  // AARCH64-FASTMATH-NEXT: fdiv {{.*}}fp128
+
+  // AARCH64-FASTMATH-NEXT: br label
+  // AARCH64-FASTMATH:      complex_div:
+  // AARCH64-FASTMATH-NEXT: phi {{.*}}fp128
+  // AARCH64-FASTMATH-NEXT: phi {{.*}}fp128
   // AARCH64-FASTMATH: ret
   return a / b;
 }
diff --git a/clang/test/CodeGen/cx-complex-range.c b/clang/test/CodeGen/cx-complex-range.c
new file mode 100644
index 000000000000..8368fa611335
--- /dev/null
+++ b/clang/test/CodeGen/cx-complex-range.c
@@ -0,0 +1,108 @@
+// RUN: %clang_cc1 %s -O0 -emit-llvm -triple x86_64-unknown-unknown \
+// RUN: -o - | FileCheck %s --check-prefix=FULL
+
+// RUN: %clang_cc1 %s -O0 -emit-llvm -triple x86_64-unknown-unknown \
+// RUN: -complex-range=limited -o - | FileCheck %s --check-prefix=LMTD
+
+// RUN: %clang_cc1 %s -O0 -emit-llvm -triple x86_64-unknown-unknown \
+// RUN: -fno-cx-limited-range -o - | FileCheck %s --check-prefix=FULL
+
+// RUN: %clang_cc1 %s -O0 -emit-llvm -triple x86_64-unknown-unknown \
+// RUN: -complex-range=fortran -o - | FileCheck %s --check-prefix=FRTRN
+
+// Fast math
+// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu \
+// RUN: -ffast-math -complex-range=limited -emit-llvm -o - %s \
+// RUN: | FileCheck %s --check-prefix=LMTD-FAST
+
+// RUN: %clang_cc1 %s -O0 -emit-llvm -triple x86_64-unknown-unknown \
+// RUN: -fno-cx-fortran-rules -o - | FileCheck %s --check-prefix=FULL
+
+_Complex float div(_Complex float a, _Complex float b) {
+  // LABEL: define {{.*}} @div(
+  // FULL:  call {{.*}} @__divsc3
+
+  // LMTD:      fmul float
+  // LMTD-NEXT: fmul float
+  // LMTD-NEXT: fadd float
+  // LMTD-NEXT: fmul float
+  // LMTD-NEXT: fmul float
+  // LMTD-NEXT: fadd float
+  // LMTD-NEXT: fmul float
+  // LMTD-NEXT: fmul float
+  // LMTD-NEXT: fsub float
+  // LMTD-NEXT: fdiv float
+  // LMTD-NEXT: fdiv float
+
+  // FRTRN: call {{.*}}float @llvm.fabs.f32(float {{.*}})
+  // FRTRN-NEXT: call {{.*}}float @llvm.fabs.f32(float {{.*}})
+  // FRTRN-NEXT: fcmp {{.*}}ugt float
+  // FRTRN-NEXT: br i1 {{.*}}, label
+  // FRTRN:      abs_rhsr_greater_or_equal_abs_rhsi:
+  // FRTRN-NEXT: fdiv {{.*}}float
+  // FRTRN-NEXT: fmul {{.*}}float
+  // FRTRN-NEXT: fadd {{.*}}float
+  // FRTRN-NEXT: fmul {{.*}}float
+  // FRTRN-NEXT: fadd {{.*}}float
+  // FRTRN-NEXT: fdiv {{.*}}float
+  // FRTRN-NEXT: fmul {{.*}}float
+  // FRTRN-NEXT: fsub {{.*}}float
+  // FRTRN-NEXT: fdiv {{.*}}float
+  // FRTRN-NEXT: br label
+  // FRTRN:      abs_rhsr_less_than_abs_rhsi:
+  // FRTRN-NEXT: fdiv {{.*}}float
+  // FRTRN-NEXT: fmul {{.*}}float
+  // FRTRN-NEXT: fadd {{.*}}float
+  // FRTRN-NEXT: fmul {{.*}}float
+  // FRTRN-NEXT: fadd {{.*}}float
+  // FRTRN-NEXT: fdiv {{.*}}float
+  // FRTRN-NEXT: fmul {{.*}}float
+  // FRTRN-NEXT: fsub {{.*}}float
+  // FRTRN-NEXT: fdiv {{.*}}float
+  // FRTRN-NEXT: br label
+  // FRTRN:      complex_div:
+  // FRTRN-NEXT: phi {{.*}}float
+  // FRTRN-NEXT: phi {{.*}}float
+
+  // LMTD-FAST: fmul {{.*}} float
+  // LMTD-FAST-NEXT: fmul {{.*}} float
+  // LMTD-FAST-NEXT: fadd {{.*}} float
+  // LMTD-FAST-NEXT: fmul {{.*}} float
+  // LMTD-FAST-NEXT: fmul {{.*}} float
+  // LMTD-FAST-NEXT: fadd {{.*}} float
+  // LMTD-FAST-NEXT: fmul {{.*}} float
+  // LMTD-FAST-NEXT: fmul {{.*}} float
+  // LMTD-FAST-NEXT: fsub {{.*}} float
+  // LMTD-FAST-NEXT: fdiv {{.*}} float
+  // LMTD-FAST-NEXT: fdiv {{.*}} float
+
+  return a / b;
+}
+
+_Complex float mul(_Complex float a, _Complex float b) {
+  // LABEL: define {{.*}} @mul(
+  // FULL:  call {{.*}} @__mulsc3
+
+  // LMTD: fmul float
+  // LMTD-NEXT: fmul float
+  // LMTD-NEXT: fmul float
+  // LMTD-NEXT: fmul float
+  // LMTD-NEXT: fsub float
+  // LMTD-NEXT: fadd float
+
+  // FRTRN: fmul {{.*}}float
+  // FRTRN-NEXT: fmul {{.*}}float
+  // FRTRN-NEXT: fmul {{.*}}float
+  // FRTRN-NEXT: fmul {{.*}}float
+  // FRTRN-NEXT: fsub {{.*}}float
+  // FRTRN-NEXT: fadd {{.*}}float
+
+  // LMTD-FAST: fmul {{.*}} float
+  // LMTD-FAST-NEXT: fmul {{.*}} float
+  // LMTD-FAST-NEXT: fmul {{.*}} float
+  // LMTD-FAST-NEXT: fmul {{.*}} float
+  // LMTD-FAST-NEXT: fsub {{.*}} float
+  // LMTD-FAST-NEXT: fadd {{.*}} float
+
+  return a * b;
+}
diff --git a/clang/test/CodeGen/pragma-cx-limited-range.c b/clang/test/CodeGen/pragma-cx-limited-range.c
new file mode 100644
index 000000000000..926da8afbee5
--- /dev/null
+++ b/clang/test/CodeGen/pragma-cx-limited-range.c
@@ -0,0 +1,107 @@
+// RUN: %clang_cc1 %s -O0 -emit-llvm -triple x86_64-unknown-unknown \
+// RUN: -o - | FileCheck %s --check-prefix=FULL
+
+// RUN: %clang_cc1 %s -O0 -emit-llvm -triple x86_64-unknown-unknown \
+// RUN: -complex-range=limited -o - | FileCheck --check-prefix=LMTD %s
+
+// RUN: %clang_cc1 %s -O0 -emit-llvm -triple x86_64-unknown-unknown \
+// RUN: -fno-cx-limited-range -o - | FileCheck %s --check-prefix=FULL
+
+// RUN: %clang_cc1 %s -O0 -emit-llvm -triple x86_64-unknown-unknown \
+// RUN: -complex-range=fortran -o - | FileCheck --check-prefix=FRTRN %s
+
+// RUN: %clang_cc1 %s -O0 -emit-llvm -triple x86_64-unknown-unknown \
+// RUN: -fno-cx-fortran-rules -o - | FileCheck --check-prefix=FULL %s
+
+_Complex float pragma_on_mul(_Complex float a, _Complex float b) {
+#pragma STDC CX_LIMITED_RANGE ON
+  // LABEL: define {{.*}} @pragma_on_mul(
+  // FULL: fmul float
+  // FULL-NEXT: fmul float
+  // FULL-NEXT: fmul float
+  // FULL-NEXT: fmul float
+  // FULL-NEXT: fsub float
+  // FULL-NEXT: fadd float
+
+  // LMTD: fmul float
+  // LMTD-NEXT: fmul float
+  // LMTD-NEXT: fmul float
+  // LMTD-NEXT: fmul float
+  // LMTD-NEXT: fsub float
+  // LMTD-NEXT: fadd float
+
+  // FRTRN: fmul float
+  // FRTRN-NEXT: fmul float
+  // FRTRN-NEXT: fmul float
+  // FRTRN-NEXT: fmul float
+  // FRTRN-NEXT: fsub float
+  // FRTRN-NEXT: fadd float
+
+  return a * b;
+}
+
+_Complex float pragma_off_mul(_Complex float a, _Complex float b) {
+#pragma STDC CX_LIMITED_RANGE OFF
+  // LABEL: define {{.*}} @pragma_off_mul(
+  // FULL: call {{.*}} @__mulsc3
+
+  // LMTD: call {{.*}} @__mulsc3
+
+  // FRTRN: call {{.*}} @__mulsc3
+
+  return a * b;
+}
+
+_Complex float pragma_on_div(_Complex float a, _Complex float b) {
+#pragma STDC CX_LIMITED_RANGE ON
+  // LABEL: define {{.*}} @pragma_on_div(
+  // FULL: fmul float
+  // FULL-NEXT: fmul float
+  // FULL-NEXT: fadd float
+  // FULL-NEXT: fmul float
+  // FULL-NEXT: fmul float
+  // FULL-NEXT: fadd float
+  // FULL-NEXT: fmul float
+  // FULL-NEXT: fmul float
+  // FULL-NEXT: fsub float
+  // FULL-NEXT: fdiv float
+  // FULL: fdiv float
+
+  // LMTD: fmul float
+  // LMTD-NEXT: fmul float
+  // LMTD-NEXT: fadd float
+  // LMTD-NEXT: fmul float
+  // LMTD-NEXT: fmul float
+  // LMTD-NEXT: fadd float
+  // LMTD-NEXT: fmul float
+  // LMTD-NEXT: fmul float
+  // LMTD-NEXT: fsub float
+  // LMTD-NEXT: fdiv float
+  // LMTD-NEXT: fdiv float
+
+  // FRTRN: fmul float
+  // FRTRN-NEXT: fmul float
+  // FRTRN-NEXT: fadd float
+  // FRTRN-NEXT: fmul float
+  // FRTRN-NEXT: fmul float
+  // FRTRN-NEXT: fadd float
+  // FRTRN-NEXT: fmul float
+  // FRTRN-NEXT: fmul float
+  // FRTRN-NEXT: fsub float
+  // FRTRN-NEXT: fdiv float
+  // FRTRN-NEXT: fdiv float
+
+  return a / b;
+}
+
+_Complex float pragma_off_div(_Complex float a, _Complex float b) {
+#pragma STDC CX_LIMITED_RANGE OFF
+  // LABEL: define {{.*}} @pragma_off_div(
+  // FULL: call {{.*}} @__divsc3
+
+  // LMTD: call {{.*}} @__divsc3
+
+  // FRTRN: call {{.*}} @__divsc3
+
+  return a / b;
+}
diff --git a/clang/test/Driver/range.c b/clang/test/Driver/range.c
new file mode 100644
index 000000000000..8d456a997d69
--- /dev/null
+++ b/clang/test/Driver/range.c
@@ -0,0 +1,39 @@
+// Test range options for complex multiplication and division.
+
+// RUN: %clang -### -target x86_64 -fcx-limited-range -c %s 2>&1 \
+// RUN:   | FileCheck --check-prefix=LMTD %s
+
+// RUN: %clang -### -target x86_64 -fno-cx-limited-range -c %s 2>&1 \
+// RUN:   | FileCheck %s
+
+// RUN: %clang -### -target x86_64 -fcx-fortran-rules -c %s 2>&1 \
+// RUN:   | FileCheck --check-prefix=FRTRN %s
+
+// RUN: %clang -### -target x86_64 -fno-cx-fortran-rules -c %s 2>&1 \
+// RUN:   | FileCheck  %s
+
+// RUN: %clang -### -target x86_64 -fcx-limited-range \
+// RUN: -fcx-fortran-rules -c %s 2>&1 \
+// RUN:   | FileCheck --check-prefix=WARN1 %s
+
+// RUN: %clang -### -target x86_64 -fcx-fortran-rules \
+// RUN: -fcx-limited-range  -c %s 2>&1 \
+// RUN:   | FileCheck --check-prefix=WARN2 %s
+
+// RUN: %clang -### -target x86_64 -ffast-math -c %s 2>&1 \
+// RUN:   | FileCheck --check-prefix=LMTD %s
+
+// RUN: %clang -### -target x86_64 -ffast-math -fcx-limited-range -c %s 2>&1 \
+// RUN:   | FileCheck --check-prefix=LMTD %s
+
+// RUN: %clang -### -target x86_64 -fcx-limited-range -ffast-math -c %s 2>&1 \
+// RUN:   | FileCheck --check-prefix=LMTD %s
+
+// LMTD: -complex-range=limited
+// LMTD-NOT: -complex-range=fortran
+// CHECK-NOT: -complex-range=limited
+// FRTRN: -complex-range=fortran
+// FRTRN-NOT: -complex-range=limited
+// CHECK-NOT: -complex-range=fortran
+// WARN1: warning: overriding '-fcx-limited-range' option with '-fcx-fortran-rules' [-Woverriding-option]
+// WARN2: warning: overriding '-fcx-fortran-rules' option with '-fcx-limited-range' [-Woverriding-option]
diff --git a/clang/test/Preprocessor/pragma_unknown.c b/clang/test/Preprocessor/pragma_unknown.c
index a7c4829c279d..1d39f8229eb5 100644
--- a/clang/test/Preprocessor/pragma_unknown.c
+++ b/clang/test/Preprocessor/pragma_unknown.c
@@ -27,6 +27,8 @@
 
 #pragma STDC CX_LIMITED_RANGE    // expected-warning {{expected 'ON' or 'OFF' or 'DEFAULT' in pragma}}
 #pragma STDC CX_LIMITED_RANGE ON FULL POWER  // expected-warning {{expected end of directive in pragma}}
+//expected-error@-1 {{unknown type name 'POWER'}}
+//expected-error@-2 {{expected identifier or '('}}
 // CHECK: {{^}}#pragma STDC CX_LIMITED_RANGE{{$}}
 // CHECK: {{^}}#pragma STDC CX_LIMITED_RANGE ON FULL POWER{{$}}
 
-- 
GitLab


From ace26b380f229e4148c12566473eea0a527e40dd Mon Sep 17 00:00:00 2001
From: Zequan Wu <zequanwu@google.com>
Date: Mon, 11 Dec 2023 10:13:08 -0500
Subject: [PATCH 124/349] [Profile] Disable continuous mode when reset to
 default.profraw due to malformed LLVM_PROFILE_FILE. (#74879)

When LLVM_PROFILE_FILE is set incorrectly (e.g. multiple %c) and it
falls back to use `default.profraw` name, but continuous mode is still
set. This might cause signal bus in the following scenario.

LLVM_PROFILE_FILE is set incorrectly (with "%c%c") for process A and B.
Suppose A starts first and falls back to use `default.profraw` and
mmaped its file content to memory. Later B starts and also falls back to
use `default.profraw`, but it will truncate the file because online
merging is disable when reseting to `default.profraw`. When A tries to
update counter via mmaped memory, signal bus will occur.

This fixes it by disabling continuous mode when reset to
default.profraw.
---
 compiler-rt/lib/profile/InstrProfiling.h      |  6 ++++++
 .../lib/profile/InstrProfilingBuffer.c        |  4 ++++
 compiler-rt/lib/profile/InstrProfilingFile.c  |  1 +
 .../reset-default-profile.c                   | 21 +++++++++++++++++++
 4 files changed, 32 insertions(+)
 create mode 100644 compiler-rt/test/profile/ContinuousSyncMode/reset-default-profile.c

diff --git a/compiler-rt/lib/profile/InstrProfiling.h b/compiler-rt/lib/profile/InstrProfiling.h
index c5b0b34f2d8a..137115996748 100644
--- a/compiler-rt/lib/profile/InstrProfiling.h
+++ b/compiler-rt/lib/profile/InstrProfiling.h
@@ -54,6 +54,12 @@ int __llvm_profile_is_continuous_mode_enabled(void);
  */
 void __llvm_profile_enable_continuous_mode(void);
 
+/*!
+ * \brief Disable continuous mode.
+ *
+ */
+void __llvm_profile_disable_continuous_mode(void);
+
 /*!
  * \brief Set the page size.
  *
diff --git a/compiler-rt/lib/profile/InstrProfilingBuffer.c b/compiler-rt/lib/profile/InstrProfilingBuffer.c
index cd1f067bd188..5657bf5bacf2 100644
--- a/compiler-rt/lib/profile/InstrProfilingBuffer.c
+++ b/compiler-rt/lib/profile/InstrProfilingBuffer.c
@@ -33,6 +33,10 @@ COMPILER_RT_VISIBILITY void __llvm_profile_enable_continuous_mode(void) {
   ContinuouslySyncProfile = 1;
 }
 
+void __llvm_profile_disable_continuous_mode(void) {
+  ContinuouslySyncProfile = 0;
+}
+
 COMPILER_RT_VISIBILITY void __llvm_profile_set_page_size(unsigned PS) {
   PageSize = PS;
 }
diff --git a/compiler-rt/lib/profile/InstrProfilingFile.c b/compiler-rt/lib/profile/InstrProfilingFile.c
index 1685b30b9492..745c567f2167 100644
--- a/compiler-rt/lib/profile/InstrProfilingFile.c
+++ b/compiler-rt/lib/profile/InstrProfilingFile.c
@@ -806,6 +806,7 @@ static int parseFilenamePattern(const char *FilenamePat,
         if (__llvm_profile_is_continuous_mode_enabled()) {
           PROF_WARN("%%c specifier can only be specified once in %s.\n",
                     FilenamePat);
+          __llvm_profile_disable_continuous_mode();
           return -1;
         }
 #if defined(__APPLE__) || defined(__ELF__) || defined(_WIN32)
diff --git a/compiler-rt/test/profile/ContinuousSyncMode/reset-default-profile.c b/compiler-rt/test/profile/ContinuousSyncMode/reset-default-profile.c
new file mode 100644
index 000000000000..75af7684161c
--- /dev/null
+++ b/compiler-rt/test/profile/ContinuousSyncMode/reset-default-profile.c
@@ -0,0 +1,21 @@
+// REQUIRES: darwin || linux
+
+// Test when LLVM_PROFILE_FILE is set incorrectly, it should fall backs to use default.profraw without runtime error.
+
+// Create & cd into a temporary directory.
+// RUN: rm -rf %t.dir && mkdir -p %t.dir && cd %t.dir
+// RUN: %clang -fprofile-instr-generate -fcoverage-mapping -mllvm -runtime-counter-relocation=true -o %t.exe %s
+// RUN: env LLVM_PROFILE_FILE="incorrect-profile-name%m%c%c.profraw" %run %t.exe
+// RUN: ls -l | FileCheck %s
+
+// CHECK:     default.profraw
+// CHECK-NOT: incorrect-profile-name.profraw
+
+#include <stdio.h>
+int f() { return 0; }
+
+int main(int argc, char **argv) {
+  FILE *File = fopen("default.profraw", "w");
+  f();
+  return 0;
+}
-- 
GitLab


From fcdb848596c33cf05c8b6e99296a171482719493 Mon Sep 17 00:00:00 2001
From: Lorenzo Chelini <l.chelini@icloud.com>
Date: Mon, 11 Dec 2023 16:11:29 +0100
Subject: [PATCH 125/349] [MLIR][Linalg] (NFC) Drop `verify-diagnostics` from
 `transpose-conv2d.mlir`

We are not checking diagnostics in this test.
---
 mlir/test/Dialect/Linalg/transpose-conv2d.mlir | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/mlir/test/Dialect/Linalg/transpose-conv2d.mlir b/mlir/test/Dialect/Linalg/transpose-conv2d.mlir
index 4655a261d986..409c36778ab7 100644
--- a/mlir/test/Dialect/Linalg/transpose-conv2d.mlir
+++ b/mlir/test/Dialect/Linalg/transpose-conv2d.mlir
@@ -1,4 +1,4 @@
-// RUN: mlir-opt %s -transform-interpreter -verify-diagnostics | FileCheck %s
+// RUN: mlir-opt %s -transform-interpreter | FileCheck %s
 
 // CHECK-LABEL: @conv_2d_nhwc_fhwc_f64
 // CHECK-SAME: (%[[INPUT:.+]]: tensor<1x4x4x6xf64>, %[[FILTER:.+]]: tensor<8x2x2x6xf64>, %[[INIT:.+]]: tensor<1x2x2x8xf64>) -> tensor<1x2x2x8xf64> {
-- 
GitLab


From e1c0e7e515a6fcc8e0cedeaca65015dc27f15ff0 Mon Sep 17 00:00:00 2001
From: Stephen Tozer <stephen.tozer@sony.com>
Date: Mon, 11 Dec 2023 15:19:40 +0000
Subject: [PATCH 126/349] [Dexter] Set ShouldBuild=false for Visual Studio
 solutions (#75045)

Since Dexter no longer intends to build any code, the ShouldBuild
property in any Visual Studio project being run by Dexter should be
false to ensure that a build step is never invoked by Dexter, whether
the project has already been built or not.

Reviewed by: OCHyams
---
 .../dexter/dex/debugger/visualstudio/VisualStudio.py       | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/cross-project-tests/debuginfo-tests/dexter/dex/debugger/visualstudio/VisualStudio.py b/cross-project-tests/debuginfo-tests/dexter/dex/debugger/visualstudio/VisualStudio.py
index 50a97e2b77d1..0e20cfbbd264 100644
--- a/cross-project-tests/debuginfo-tests/dexter/dex/debugger/visualstudio/VisualStudio.py
+++ b/cross-project-tests/debuginfo-tests/dexter/dex/debugger/visualstudio/VisualStudio.py
@@ -276,6 +276,13 @@ class VisualStudio(
             project.Properties, "ActiveConfiguration"
         ).Object
         ActiveConfiguration.DebugSettings.CommandArguments = cmdline_str
+        ConfigurationName = ActiveConfiguration.ConfigurationName
+        SolConfig = self._fetch_property(
+            self._interface.Solution.SolutionBuild.SolutionConfigurations,
+            ConfigurationName,
+        )
+        for Context in SolConfig.SolutionContexts:
+            Context.ShouldBuild = False
 
         self.context.logger.note("Launching VS debugger...")
         self._fn_go(False)
-- 
GitLab


From 7ff2ce9c7b61d9fe4ce055f4953d05032ad9d66e Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Mon, 11 Dec 2023 15:31:56 +0000
Subject: [PATCH 127/349] [X86] combineConcatVectorOps - pull out repeated
 DAG.getContext calls. NFC.

---
 llvm/lib/Target/X86/X86ISelLowering.cpp | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index d69976342fcb..22630f9a6b82 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -54483,6 +54483,7 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
   bool IsSplat = llvm::all_equal(Ops);
   unsigned NumOps = Ops.size();
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+  LLVMContext &Ctx = *DAG.getContext();
 
   // Repeated subvectors.
   if (IsSplat &&
@@ -54780,7 +54781,7 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
             Subtarget.useAVX512Regs() &&
             Subtarget.getPreferVectorWidth() >= 512 &&
             (SrcVT.getScalarSizeInBits() > 16 || Subtarget.useBWIRegs())) {
-          EVT NewSrcVT = SrcVT.getDoubleNumVectorElementsVT(*DAG.getContext());
+          EVT NewSrcVT = SrcVT.getDoubleNumVectorElementsVT(Ctx);
           return DAG.getNode(ISD::TRUNCATE, DL, VT,
                              ConcatSubOperand(NewSrcVT, Ops, 0));
         }
@@ -54937,7 +54938,7 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
           (EltSizeInBits >= 32 || Subtarget.hasBWI())) {
         EVT SelVT = Ops[0].getOperand(0).getValueType();
         if (SelVT.getVectorElementType() == MVT::i1) {
-          SelVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
+          SelVT = EVT::getVectorVT(Ctx, MVT::i1,
                                    NumOps * SelVT.getVectorNumElements());
           if (TLI.isTypeLegal(SelVT))
             return DAG.getNode(Op0.getOpcode(), DL, VT,
@@ -54952,7 +54953,7 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
           (EltSizeInBits >= 32 || Subtarget.hasInt256()) &&
           IsConcatFree(VT, Ops, 1) && IsConcatFree(VT, Ops, 2)) {
         EVT SelVT = Ops[0].getOperand(0).getValueType();
-        SelVT = SelVT.getDoubleNumVectorElementsVT(*DAG.getContext());
+        SelVT = SelVT.getDoubleNumVectorElementsVT(Ctx);
         if (TLI.isTypeLegal(SelVT))
           return DAG.getNode(Op0.getOpcode(), DL, VT,
                              ConcatSubOperand(SelVT.getSimpleVT(), Ops, 0),
@@ -54968,7 +54969,7 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
   if (auto *FirstLd = dyn_cast<LoadSDNode>(peekThroughBitcasts(Op0))) {
     unsigned Fast;
     const X86TargetLowering *TLI = Subtarget.getTargetLowering();
-    if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
+    if (TLI->allowsMemoryAccess(Ctx, DAG.getDataLayout(), VT,
                                 *FirstLd->getMemOperand(), &Fast) &&
         Fast) {
       if (SDValue Ld =
-- 
GitLab


From 45f3eea12aa6a051d12f1370fcb2e949c0d15c15 Mon Sep 17 00:00:00 2001
From: "Yaxun (Sam) Liu" <yaxun.liu@amd.com>
Date: Mon, 11 Dec 2023 10:39:48 -0500
Subject: [PATCH 128/349] Fix test rocm-detect.hip (#74872)

Replace %T with %t since %T is deprecated.
---
 clang/test/Driver/rocm-detect.hip | 34 +++++++++++++++----------------
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/clang/test/Driver/rocm-detect.hip b/clang/test/Driver/rocm-detect.hip
index 947c4f995be1..3644f215a345 100644
--- a/clang/test/Driver/rocm-detect.hip
+++ b/clang/test/Driver/rocm-detect.hip
@@ -78,39 +78,39 @@
 // RUN:   | FileCheck -check-prefixes=ROCM-ENV,HIP-PATH %s
 
 // Test detecting latest /opt/rocm-{release} directory.
-// RUN: rm -rf %T/opt
-// RUN: mkdir -p %T/opt
-// RUN: cp -r %S/Inputs/rocm %T/opt/rocm-3.9.0-1234
-// RUN: cp -r %S/Inputs/rocm %T/opt/rocm-3.10.0
-// RUN: %clang -### --target=x86_64-linux-gnu --offload-arch=gfx1010 --sysroot=%T \
+// RUN: rm -rf %t/opt
+// RUN: mkdir -p %t/opt
+// RUN: cp -r %S/Inputs/rocm %t/opt/rocm-3.9.0-1234
+// RUN: cp -r %S/Inputs/rocm %t/opt/rocm-3.10.0
+// RUN: %clang -### --target=x86_64-linux-gnu --offload-arch=gfx1010 --sysroot=%t \
 // RUN:   --print-rocm-search-dirs %s 2>&1 \
 // RUN:   | FileCheck -check-prefixes=ROCM-REL %s
 
-// Test ROCm installation built by SPACK by invoke clang at %T/rocm-spack/llvm-amdgpu-*
+// Test ROCm installation built by SPACK by invoke clang at %t/rocm-spack/llvm-amdgpu-*
 // directory through a soft link.
 
-// RUN: rm -rf %T/rocm-spack
-// RUN: cp -r %S/Inputs/rocm-spack %T
-// RUN: ln -fs %clang %T/rocm-spack/llvm-amdgpu-4.0.0-ieagcs7inf7runpyfvepqkurasoglq4z/bin/clang
-// RUN: %T/rocm-spack/llvm-amdgpu-4.0.0-ieagcs7inf7runpyfvepqkurasoglq4z/bin/clang -### -v \
-// RUN:   -resource-dir=%T/rocm-spack/llvm-amdgpu-4.0.0-ieagcs7inf7runpyfvepqkurasoglq4z/lib/clang \
+// RUN: rm -rf %t/rocm-spack
+// RUN: cp -r %S/Inputs/rocm-spack %t
+// RUN: ln -fs %clang %t/rocm-spack/llvm-amdgpu-4.0.0-ieagcs7inf7runpyfvepqkurasoglq4z/bin/clang
+// RUN: %t/rocm-spack/llvm-amdgpu-4.0.0-ieagcs7inf7runpyfvepqkurasoglq4z/bin/clang -### -v \
+// RUN:   -resource-dir=%t/rocm-spack/llvm-amdgpu-4.0.0-ieagcs7inf7runpyfvepqkurasoglq4z/lib/clang \
 // RUN:   -target x86_64-linux-gnu --cuda-gpu-arch=gfx900 --print-rocm-search-dirs %s 2>&1 \
 // RUN:   | FileCheck -check-prefixes=SPACK %s
 
 // Test SPACK installation with multiple hip and rocm-device-libs packages of the same
 // ROCm release. --hip-path and --rocm-device-lib-path can be used to specify them.
 
-// RUN: cp -r %T/rocm-spack/hip-* %T/rocm-spack/hip-4.0.0-abcd
-// RUN: %T/rocm-spack/llvm-amdgpu-4.0.0-ieagcs7inf7runpyfvepqkurasoglq4z/bin/clang -### -v \
+// RUN: cp -r %t/rocm-spack/hip-* %t/rocm-spack/hip-4.0.0-abcd
+// RUN: %t/rocm-spack/llvm-amdgpu-4.0.0-ieagcs7inf7runpyfvepqkurasoglq4z/bin/clang -### -v \
 // RUN:   -target x86_64-linux-gnu --cuda-gpu-arch=gfx900 \
-// RUN:   --hip-path=%T/rocm-spack/hip-4.0.0-abcd \
+// RUN:   --hip-path=%t/rocm-spack/hip-4.0.0-abcd \
 // RUN:    %s 2>&1 | FileCheck -check-prefixes=SPACK-SET %s
 
 // Test invalid SPACK ROCm installation missing hip and rocm-device-libs packages.
 
-// RUN: rm -rf %T/rocm-spack/hip-*
-// RUN: rm -rf %T/rocm-spack/llvm-amdgpu-4.0.0-ieagcs7inf7runpyfvepqkurasoglq4z/amdgcn
-// RUN: %T/rocm-spack/llvm-amdgpu-4.0.0-ieagcs7inf7runpyfvepqkurasoglq4z/bin/clang --version 2>&1 \
+// RUN: rm -rf %t/rocm-spack/hip-*
+// RUN: rm -rf %t/rocm-spack/llvm-amdgpu-4.0.0-ieagcs7inf7runpyfvepqkurasoglq4z/amdgcn
+// RUN: %t/rocm-spack/llvm-amdgpu-4.0.0-ieagcs7inf7runpyfvepqkurasoglq4z/bin/clang --version 2>&1 \
 // RUN:   | FileCheck -check-prefixes=SPACK-MISS-SILENT %s
 
 // GFX902-DEFAULTLIBS: error: cannot find ROCm device library for gfx902; provide its path via '--rocm-path' or '--rocm-device-lib-path', or pass '-nogpulib' to build without ROCm device library
-- 
GitLab


From 32ec462519accb92176fe87b1fc7566b02187e4b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Timm=20B=C3=A4der?= <tbaeder@redhat.com>
Date: Mon, 11 Dec 2023 09:44:04 +0100
Subject: [PATCH 129/349] [clang][Interp][NFC] Handle body-less functions like
 implicit ones

They don't have any source to look up locations in.
---
 clang/lib/AST/Interp/InterpFrame.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/clang/lib/AST/Interp/InterpFrame.cpp b/clang/lib/AST/Interp/InterpFrame.cpp
index b06923114c7a..d460d7ea3710 100644
--- a/clang/lib/AST/Interp/InterpFrame.cpp
+++ b/clang/lib/AST/Interp/InterpFrame.cpp
@@ -228,7 +228,7 @@ Pointer InterpFrame::getParamPointer(unsigned Off) {
 SourceInfo InterpFrame::getSource(CodePtr PC) const {
   // Implicitly created functions don't have any code we could point at,
   // so return the call site.
-  if (Func && Func->getDecl()->isImplicit() && Caller)
+  if (Func && (!Func->hasBody() || Func->getDecl()->isImplicit()) && Caller)
     return Caller->getSource(RetPC);
 
   return S.getSource(Func, PC);
@@ -243,7 +243,7 @@ SourceLocation InterpFrame::getLocation(CodePtr PC) const {
 }
 
 SourceRange InterpFrame::getRange(CodePtr PC) const {
-  if (Func && Func->getDecl()->isImplicit() && Caller)
+  if (Func && (!Func->hasBody() || Func->getDecl()->isImplicit()) && Caller)
     return Caller->getRange(RetPC);
 
   return S.getRange(Func, PC);
-- 
GitLab


From a9adcef45011f95ab54e7e40983da7cf9e14a08a Mon Sep 17 00:00:00 2001
From: Tom Eccles <tom.eccles@arm.com>
Date: Mon, 11 Dec 2023 15:56:40 +0000
Subject: [PATCH 130/349] [flang] fix ppc test broken after #74709 (#74826)

---
 flang/test/Lower/PowerPC/ppc-vec-store.f90 | 96 +++++++++++-----------
 1 file changed, 48 insertions(+), 48 deletions(-)

diff --git a/flang/test/Lower/PowerPC/ppc-vec-store.f90 b/flang/test/Lower/PowerPC/ppc-vec-store.f90
index 8e20228d6825..c25cc8b07cf7 100644
--- a/flang/test/Lower/PowerPC/ppc-vec-store.f90
+++ b/flang/test/Lower/PowerPC/ppc-vec-store.f90
@@ -89,10 +89,10 @@ subroutine vec_st_vi4i4via4(arg1, arg2, arg3, i)
 
 ! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
 ! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
-! LLVMIR: %[[iextsub:.*]] = sub i64 %[[iext]], 1
-! LLVMIR: %[[iextmul:.*]] = mul i64 %[[iextsub]], 1
-! LLVMIR: %[[iextmul2:.*]] = mul i64 %[[iextmul]], 1
-! LLVMIR: %[[iextadd:.*]] = add i64 %[[iextmul2]], 0
+! LLVMIR: %[[iextsub:.*]] = sub nsw i64 %[[iext]], 1
+! LLVMIR: %[[iextmul:.*]] = mul nsw i64 %[[iextsub]], 1
+! LLVMIR: %[[iextmul2:.*]] = mul nsw i64 %[[iextmul]], 1
+! LLVMIR: %[[iextadd:.*]] = add nsw i64 %[[iextmul2]], 0
 ! LLVMIR: %[[gep1:.*]] = getelementptr <4 x i32>, ptr %2, i64 %[[iextadd]]
 ! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
 ! LLVMIR: %[[arg2:.*]] = load i32, ptr %1, align 4
@@ -206,10 +206,10 @@ subroutine vec_ste_vi4i4ia4(arg1, arg2, arg3, i)
 
 ! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
 ! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
-! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1
-! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1
-! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1
-! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0
+! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1
+! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1
+! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1
+! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0
 ! LLVMIR: %[[gep1:.*]] = getelementptr i32, ptr %2, i64 %[[iadd]]
 ! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
 ! LLVMIR: %[[arg2:.*]] = load i32, ptr %1, align 4
@@ -244,10 +244,10 @@ subroutine vec_stxv_test_vi4i8ia4(arg1, arg2, arg3, i)
 
 ! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
 ! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
-! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1
-! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1
-! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1
-! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0
+! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1
+! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1
+! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1
+! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0
 ! LLVMIR: %[[gep1:.*]] = getelementptr i32, ptr %2, i64 %[[iadd]]
 ! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
 ! LLVMIR: %[[arg2:.*]] = load i64, ptr %1, align 8
@@ -278,10 +278,10 @@ subroutine vec_stxv_test_vi4i4vai4(arg1, arg2, arg3, i)
 
 ! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
 ! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
-! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1
-! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1
-! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1
-! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0
+! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1
+! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1
+! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1
+! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0
 ! LLVMIR: %[[gep1:.*]] = getelementptr <4 x i32>, ptr %2, i64 %[[iadd]]
 ! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
 ! LLVMIR: %[[arg2:.*]] = load i32, ptr %1, align 4
@@ -317,10 +317,10 @@ subroutine vec_xst_test_vi4i8ia4(arg1, arg2, arg3, i)
 
 ! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
 ! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
-! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1
-! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1
-! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1
-! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0
+! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1
+! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1
+! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1
+! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0
 ! LLVMIR: %[[gep1:.*]] = getelementptr i32, ptr %2, i64 %[[iadd]]
 ! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
 ! LLVMIR: %[[arg2:.*]] = load i64, ptr %1, align 8
@@ -351,10 +351,10 @@ subroutine vec_xst_test_vi4i4vai4(arg1, arg2, arg3, i)
 
 ! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
 ! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
-! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1
-! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1
-! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1
-! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0
+! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1
+! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1
+! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1
+! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0
 ! LLVMIR: %[[gep1:.*]] = getelementptr <4 x i32>, ptr %2, i64 %[[iadd]]
 ! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
 ! LLVMIR: %[[arg2:.*]] = load i32, ptr %1, align 4
@@ -390,10 +390,10 @@ subroutine vec_xst_be_test_vi4i8ia4(arg1, arg2, arg3, i)
 
 ! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
 ! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
-! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1
-! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1
-! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1
-! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0
+! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1
+! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1
+! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1
+! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0
 ! LLVMIR: %[[gep1:.*]] = getelementptr i32, ptr %2, i64 %[[iadd]]
 ! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
 ! LLVMIR: %[[arg2:.*]] = load i64, ptr %1, align 8
@@ -426,10 +426,10 @@ subroutine vec_xst_be_test_vi4i4vai4(arg1, arg2, arg3, i)
 
 ! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
 ! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
-! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1
-! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1
-! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1
-! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0
+! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1
+! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1
+! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1
+! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0
 ! LLVMIR: %[[gep1:.*]] = getelementptr <4 x i32>, ptr %2, i64 %[[iadd]]
 ! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
 ! LLVMIR: %[[arg2:.*]] = load i32, ptr %1, align 4 
@@ -467,10 +467,10 @@ subroutine vec_xstd2_test_vi4i8ia4(arg1, arg2, arg3, i)
 
 ! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
 ! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
-! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1
-! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1
-! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1
-! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0
+! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1
+! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1
+! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1
+! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0
 ! LLVMIR: %[[gep1:.*]] = getelementptr i32, ptr %2, i64 %[[iadd]]
 ! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
 ! LLVMIR: %[[arg2:.*]] = load i64, ptr %1, align 8
@@ -503,10 +503,10 @@ subroutine vec_xstd2_test_vi4i4vai4(arg1, arg2, arg3, i)
 
 ! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
 ! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
-! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1
-! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1
-! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1
-! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0
+! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1
+! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1
+! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1
+! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0
 ! LLVMIR: %[[gep1:.*]] = getelementptr <4 x i32>, ptr %2, i64 %[[iadd]]
 ! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
 ! LLVMIR: %[[arg2:.*]] = load i32, ptr %1, align 4 
@@ -543,10 +543,10 @@ subroutine vec_xstw4_test_vi4i8ia4(arg1, arg2, arg3, i)
 
 ! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
 ! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
-! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1
-! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1
-! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1
-! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0
+! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1
+! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1
+! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1
+! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0
 ! LLVMIR: %[[gep1:.*]] = getelementptr i32, ptr %2, i64 %[[iadd]]
 ! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
 ! LLVMIR: %[[arg2:.*]] = load i64, ptr %1, align 8
@@ -578,10 +578,10 @@ subroutine vec_xstw4_test_vi4i4vai4(arg1, arg2, arg3, i)
 
 ! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
 ! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
-! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1
-! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1
-! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1
-! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0
+! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1
+! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1
+! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1
+! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0
 ! LLVMIR: %[[gep1:.*]] = getelementptr <4 x i32>, ptr %2, i64 %[[iadd]]
 ! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
 ! LLVMIR: %[[arg2:.*]] = load i32, ptr %1, align 4 
-- 
GitLab


From 7b387d2758ed58b4a6c901dc3ea4ccf897c333a4 Mon Sep 17 00:00:00 2001
From: Guillaume Chatelet <gchatelet@google.com>
Date: Mon, 11 Dec 2023 17:06:48 +0100
Subject: [PATCH 131/349] [libc][NFC] Fix mixed up biased/unbiased exponent
 (#75037)

According to [wikipedia](https://en.wikipedia.org/wiki/Exponent_bias)
the "biased exponent" is the encoded form that is always positive
whereas the unbiased form is the actual "real" exponent that can be
positive or negative.
`FPBits` seems to be using `unbiased_exponent` to describe the encoded
form (unsigned). This patch simply use `biased` instead of `unbiased`.
---
 libc/src/__support/FPUtil/FPBits.h            | 20 +++----
 libc/src/__support/FPUtil/Hypot.h             |  4 +-
 libc/src/__support/FPUtil/NormalFloat.h       | 20 +++----
 libc/src/__support/FPUtil/fpbits_str.h        |  2 +-
 libc/src/__support/FPUtil/generic/FMA.h       | 14 ++---
 libc/src/__support/FPUtil/generic/FMod.h      |  4 +-
 libc/src/__support/FPUtil/generic/sqrt.h      |  2 +-
 .../FPUtil/generic/sqrt_80_bit_long_double.h  |  4 +-
 .../__support/FPUtil/x86_64/LongDoubleBits.h  | 32 +++++-----
 .../FPUtil/x86_64/NextAfterLongDouble.h       | 12 ++--
 libc/src/__support/str_to_float.h             |  6 +-
 libc/src/math/generic/expf.cpp                |  2 +-
 libc/src/math/generic/explogxf.h              |  4 +-
 libc/src/math/generic/hypotf.cpp              |  4 +-
 libc/src/math/generic/log10f.cpp              |  2 +-
 libc/src/math/generic/log1p.cpp               |  4 +-
 libc/src/math/generic/log1pf.cpp              |  2 +-
 libc/src/math/generic/log2f.cpp               |  4 +-
 libc/src/math/generic/logf.cpp                |  4 +-
 libc/src/math/generic/powf.cpp                |  4 +-
 .../test/src/__support/FPUtil/fpbits_test.cpp | 60 +++++++++----------
 libc/test/src/math/LdExpTest.h                |  2 +-
 libc/test/src/math/NextAfterTest.h            | 14 ++---
 libc/test/src/math/RoundToIntegerTest.h       |  4 +-
 libc/test/src/math/smoke/LdExpTest.h          |  2 +-
 libc/test/src/math/smoke/NextAfterTest.h      | 14 ++---
 libc/test/src/math/smoke/NextTowardTest.h     | 14 ++---
 .../utils/FPUtil/x86_long_double_test.cpp     | 10 ++--
 libc/utils/MPFRWrapper/MPFRUtils.cpp          |  8 +--
 29 files changed, 136 insertions(+), 142 deletions(-)

diff --git a/libc/src/__support/FPUtil/FPBits.h b/libc/src/__support/FPUtil/FPBits.h
index ca98aa712624..bd075fe3d728 100644
--- a/libc/src/__support/FPUtil/FPBits.h
+++ b/libc/src/__support/FPUtil/FPBits.h
@@ -59,13 +59,13 @@ template <typename T> struct FPBits {
     return bits & FloatProp::MANTISSA_MASK;
   }
 
-  LIBC_INLINE constexpr void set_unbiased_exponent(UIntType expVal) {
+  LIBC_INLINE constexpr void set_biased_exponent(UIntType expVal) {
     expVal = (expVal << (FloatProp::MANTISSA_WIDTH)) & FloatProp::EXPONENT_MASK;
     bits &= ~(FloatProp::EXPONENT_MASK);
     bits |= expVal;
   }
 
-  LIBC_INLINE constexpr uint16_t get_unbiased_exponent() const {
+  LIBC_INLINE constexpr uint16_t get_biased_exponent() const {
     return uint16_t((bits & FloatProp::EXPONENT_MASK) >>
                     (FloatProp::MANTISSA_WIDTH));
   }
@@ -73,7 +73,7 @@ template <typename T> struct FPBits {
   // The function return mantissa with the implicit bit set iff the current
   // value is a valid normal number.
   LIBC_INLINE constexpr UIntType get_explicit_mantissa() {
-    return ((get_unbiased_exponent() > 0 && !is_inf_or_nan())
+    return ((get_biased_exponent() > 0 && !is_inf_or_nan())
                 ? (FloatProp::MANTISSA_MASK + 1)
                 : 0) |
            (FloatProp::MANTISSA_MASK & bits);
@@ -126,7 +126,7 @@ template <typename T> struct FPBits {
   LIBC_INLINE constexpr UIntType uintval() const { return bits; }
 
   LIBC_INLINE constexpr int get_exponent() const {
-    return int(get_unbiased_exponent()) - EXPONENT_BIAS;
+    return int(get_biased_exponent()) - EXPONENT_BIAS;
   }
 
   // If the number is subnormal, the exponent is treated as if it were the
@@ -136,13 +136,13 @@ template <typename T> struct FPBits {
   // will give a slightly incorrect result. Additionally, zero has an exponent
   // of zero, and that should actually be treated as zero.
   LIBC_INLINE constexpr int get_explicit_exponent() const {
-    const int unbiased_exp = int(get_unbiased_exponent());
+    const int biased_exp = int(get_biased_exponent());
     if (is_zero()) {
       return 0;
-    } else if (unbiased_exp == 0) {
+    } else if (biased_exp == 0) {
       return 1 - EXPONENT_BIAS;
     } else {
-      return unbiased_exp - EXPONENT_BIAS;
+      return biased_exp - EXPONENT_BIAS;
     }
   }
 
@@ -228,7 +228,7 @@ template <typename T> struct FPBits {
     if (LIBC_LIKELY(ep >= 0)) {
       // Implicit number bit will be removed by mask
       result.set_mantissa(number);
-      result.set_unbiased_exponent(ep + 1);
+      result.set_biased_exponent(ep + 1);
     } else {
       result.set_mantissa(number >> -ep);
     }
@@ -236,10 +236,10 @@ template <typename T> struct FPBits {
   }
 
   LIBC_INLINE static constexpr FPBits<T>
-  create_value(bool sign, UIntType unbiased_exp, UIntType mantissa) {
+  create_value(bool sign, UIntType biased_exp, UIntType mantissa) {
     FPBits<T> result;
     result.set_sign(sign);
-    result.set_unbiased_exponent(unbiased_exp);
+    result.set_biased_exponent(biased_exp);
     result.set_mantissa(mantissa);
     return result;
   }
diff --git a/libc/src/__support/FPUtil/Hypot.h b/libc/src/__support/FPUtil/Hypot.h
index fb04d8a7775d..42d9e1b3f8ce 100644
--- a/libc/src/__support/FPUtil/Hypot.h
+++ b/libc/src/__support/FPUtil/Hypot.h
@@ -120,8 +120,8 @@ LIBC_INLINE T hypot(T x, T y) {
     return y;
   }
 
-  uint16_t x_exp = x_bits.get_unbiased_exponent();
-  uint16_t y_exp = y_bits.get_unbiased_exponent();
+  uint16_t x_exp = x_bits.get_biased_exponent();
+  uint16_t y_exp = y_bits.get_biased_exponent();
   uint16_t exp_diff = (x_exp > y_exp) ? (x_exp - y_exp) : (y_exp - x_exp);
 
   if ((exp_diff >= MantissaWidth<T>::VALUE + 2) || (x == 0) || (y == 0)) {
diff --git a/libc/src/__support/FPUtil/NormalFloat.h b/libc/src/__support/FPUtil/NormalFloat.h
index d59de14fb695..d3236316a879 100644
--- a/libc/src/__support/FPUtil/NormalFloat.h
+++ b/libc/src/__support/FPUtil/NormalFloat.h
@@ -111,7 +111,7 @@ template <typename T> struct NormalFloat {
         const UIntType shift_out_mask = (UIntType(1) << shift) - 1;
         const UIntType shift_out_value = mantissa & shift_out_mask;
         const UIntType halfway_value = UIntType(1) << (shift - 1);
-        result.set_unbiased_exponent(0);
+        result.set_biased_exponent(0);
         result.set_mantissa(mantissa >> shift);
         UIntType new_mantissa = result.get_mantissa();
         if (shift_out_value > halfway_value) {
@@ -126,14 +126,14 @@ template <typename T> struct NormalFloat {
         // mantissa was all ones (0b111..11). For such a case, we will carry
         // the overflow into the exponent.
         if (new_mantissa == ONE)
-          result.set_unbiased_exponent(1);
+          result.set_biased_exponent(1);
         return T(result);
       } else {
         return T(result);
       }
     }
 
-    result.set_unbiased_exponent(exponent + FPBits<T>::EXPONENT_BIAS);
+    result.set_biased_exponent(exponent + FPBits<T>::EXPONENT_BIAS);
     result.set_mantissa(mantissa);
     return T(result);
   }
@@ -151,12 +151,12 @@ private:
     }
 
     // Normalize subnormal numbers.
-    if (bits.get_unbiased_exponent() == 0) {
+    if (bits.get_biased_exponent() == 0) {
       unsigned shift = evaluate_normalization_shift(bits.get_mantissa());
       mantissa = UIntType(bits.get_mantissa()) << shift;
       exponent = 1 - FPBits<T>::EXPONENT_BIAS - shift;
     } else {
-      exponent = bits.get_unbiased_exponent() - FPBits<T>::EXPONENT_BIAS;
+      exponent = bits.get_biased_exponent() - FPBits<T>::EXPONENT_BIAS;
       mantissa = ONE | bits.get_mantissa();
     }
   }
@@ -184,7 +184,7 @@ NormalFloat<long double>::init_from_bits(FPBits<long double> bits) {
     return;
   }
 
-  if (bits.get_unbiased_exponent() == 0) {
+  if (bits.get_biased_exponent() == 0) {
     if (bits.get_implicit_bit() == 0) {
       // Since we ignore zero value, the mantissa in this case is non-zero.
       int normalization_shift =
@@ -201,7 +201,7 @@ NormalFloat<long double>::init_from_bits(FPBits<long double> bits) {
       exponent = 0;
       mantissa = 0;
     } else {
-      exponent = bits.get_unbiased_exponent() - 16383;
+      exponent = bits.get_biased_exponent() - 16383;
       mantissa = ONE | bits.get_mantissa();
     }
   }
@@ -228,7 +228,7 @@ template <> LIBC_INLINE NormalFloat<long double>::operator long double() const {
       const UIntType shift_out_mask = (UIntType(1) << shift) - 1;
       const UIntType shift_out_value = mantissa & shift_out_mask;
       const UIntType halfway_value = UIntType(1) << (shift - 1);
-      result.set_unbiased_exponent(0);
+      result.set_biased_exponent(0);
       result.set_mantissa(mantissa >> shift);
       UIntType new_mantissa = result.get_mantissa();
       if (shift_out_value > halfway_value) {
@@ -243,7 +243,7 @@ template <> LIBC_INLINE NormalFloat<long double>::operator long double() const {
       // mantissa was all ones (0b111..11). For such a case, we will carry
       // the overflow into the exponent and set the implicit bit to 1.
       if (new_mantissa == ONE) {
-        result.set_unbiased_exponent(1);
+        result.set_biased_exponent(1);
         result.set_implicit_bit(1);
       } else {
         result.set_implicit_bit(0);
@@ -254,7 +254,7 @@ template <> LIBC_INLINE NormalFloat<long double>::operator long double() const {
     }
   }
 
-  result.set_unbiased_exponent(biased_exponent);
+  result.set_biased_exponent(biased_exponent);
   result.set_mantissa(mantissa);
   result.set_implicit_bit(1);
   return static_cast<long double>(result);
diff --git a/libc/src/__support/FPUtil/fpbits_str.h b/libc/src/__support/FPUtil/fpbits_str.h
index 4dec85ac2cc8..5d0bb6cf1ac4 100644
--- a/libc/src/__support/FPUtil/fpbits_str.h
+++ b/libc/src/__support/FPUtil/fpbits_str.h
@@ -53,7 +53,7 @@ template <typename T> LIBC_INLINE cpp::string str(fputil::FPBits<T> x) {
   s += sign_char(x.get_sign());
 
   s += ", E: ";
-  const details::ZeroPaddedHexFmt<uint16_t> exponent(x.get_unbiased_exponent());
+  const details::ZeroPaddedHexFmt<uint16_t> exponent(x.get_biased_exponent());
   s += exponent.view();
 
   if constexpr (cpp::is_same_v<T, long double> &&
diff --git a/libc/src/__support/FPUtil/generic/FMA.h b/libc/src/__support/FPUtil/generic/FMA.h
index 4a825f2f4942..61a1401c30e8 100644
--- a/libc/src/__support/FPUtil/generic/FMA.h
+++ b/libc/src/__support/FPUtil/generic/FMA.h
@@ -58,7 +58,7 @@ template <> LIBC_INLINE float fma<float>(float x, float y, float z) {
     // bit of sum, so that the sticky bits used when rounding sum to float are
     // correct (when it matters).
     fputil::FPBits<double> t(
-        (bit_prod.get_unbiased_exponent() >= bitz.get_unbiased_exponent())
+        (bit_prod.get_biased_exponent() >= bitz.get_biased_exponent())
             ? ((double(bit_sum) - double(bit_prod)) - double(bitz))
             : ((double(bit_sum) - double(bitz)) - double(bit_prod)));
 
@@ -106,15 +106,15 @@ template <> LIBC_INLINE double fma<double>(double x, double y, double z) {
   int z_exp = 0;
 
   // Normalize denormal inputs.
-  if (LIBC_UNLIKELY(FPBits(x).get_unbiased_exponent() == 0)) {
+  if (LIBC_UNLIKELY(FPBits(x).get_biased_exponent() == 0)) {
     x_exp -= 52;
     x *= 0x1.0p+52;
   }
-  if (LIBC_UNLIKELY(FPBits(y).get_unbiased_exponent() == 0)) {
+  if (LIBC_UNLIKELY(FPBits(y).get_biased_exponent() == 0)) {
     y_exp -= 52;
     y *= 0x1.0p+52;
   }
-  if (LIBC_UNLIKELY(FPBits(z).get_unbiased_exponent() == 0)) {
+  if (LIBC_UNLIKELY(FPBits(z).get_biased_exponent() == 0)) {
     z_exp -= 52;
     z *= 0x1.0p+52;
   }
@@ -124,9 +124,9 @@ template <> LIBC_INLINE double fma<double>(double x, double y, double z) {
   bool y_sign = y_bits.get_sign();
   bool z_sign = z_bits.get_sign();
   bool prod_sign = x_sign != y_sign;
-  x_exp += x_bits.get_unbiased_exponent();
-  y_exp += y_bits.get_unbiased_exponent();
-  z_exp += z_bits.get_unbiased_exponent();
+  x_exp += x_bits.get_biased_exponent();
+  y_exp += y_bits.get_biased_exponent();
+  z_exp += z_bits.get_biased_exponent();
 
   if (LIBC_UNLIKELY(x_exp == FPBits::MAX_EXPONENT ||
                     y_exp == FPBits::MAX_EXPONENT ||
diff --git a/libc/src/__support/FPUtil/generic/FMod.h b/libc/src/__support/FPUtil/generic/FMod.h
index 0e71b039d5c0..7502660c88a1 100644
--- a/libc/src/__support/FPUtil/generic/FMod.h
+++ b/libc/src/__support/FPUtil/generic/FMod.h
@@ -233,8 +233,8 @@ private:
       return FPB(FPB::zero()); // |x|=|y| return 0.0
     }
 
-    int e_x = sx.get_unbiased_exponent();
-    int e_y = sy.get_unbiased_exponent();
+    int e_x = sx.get_biased_exponent();
+    int e_y = sy.get_biased_exponent();
 
     // Most common case where |y| is "very normal" and |x/y| < 2^EXPONENT_WIDTH
     if (LIBC_LIKELY(e_y > int(FPB::FloatProp::MANTISSA_WIDTH) &&
diff --git a/libc/src/__support/FPUtil/generic/sqrt.h b/libc/src/__support/FPUtil/generic/sqrt.h
index 6ae2171bacf7..5bde9589fdc0 100644
--- a/libc/src/__support/FPUtil/generic/sqrt.h
+++ b/libc/src/__support/FPUtil/generic/sqrt.h
@@ -97,7 +97,7 @@ LIBC_INLINE cpp::enable_if_t<cpp::is_floating_point_v<T>, T> sqrt(T x) {
       UIntType x_mant = bits.get_mantissa();
 
       // Step 1a: Normalize denormal input and append hidden bit to the mantissa
-      if (bits.get_unbiased_exponent() == 0) {
+      if (bits.get_biased_exponent() == 0) {
         ++x_exp; // let x_exp be the correct exponent of ONE bit.
         internal::normalize<T>(x_exp, x_mant);
       } else {
diff --git a/libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h b/libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h
index 0e7907e82943..2f25be54e0bc 100644
--- a/libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h
+++ b/libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h
@@ -65,7 +65,7 @@ LIBC_INLINE long double sqrt(long double x) {
     // Step 1a: Normalize denormal input
     if (bits.get_implicit_bit()) {
       x_mant |= ONE;
-    } else if (bits.get_unbiased_exponent() == 0) {
+    } else if (bits.get_biased_exponent() == 0) {
       normalize(x_exp, x_mant);
     }
 
@@ -128,7 +128,7 @@ LIBC_INLINE long double sqrt(long double x) {
 
     // Extract output
     FPBits<long double> out(0.0L);
-    out.set_unbiased_exponent(x_exp);
+    out.set_biased_exponent(x_exp);
     out.set_implicit_bit(1);
     out.set_mantissa((y & (ONE - 1)));
 
diff --git a/libc/src/__support/FPUtil/x86_64/LongDoubleBits.h b/libc/src/__support/FPUtil/x86_64/LongDoubleBits.h
index 2f07ff4a2c3e..bbc30ff7a376 100644
--- a/libc/src/__support/FPUtil/x86_64/LongDoubleBits.h
+++ b/libc/src/__support/FPUtil/x86_64/LongDoubleBits.h
@@ -71,7 +71,7 @@ template <> struct FPBits<long double> {
     return bits & (FloatProp::MANTISSA_MASK | FloatProp::EXPLICIT_BIT_MASK);
   }
 
-  LIBC_INLINE constexpr void set_unbiased_exponent(UIntType expVal) {
+  LIBC_INLINE constexpr void set_biased_exponent(UIntType expVal) {
     expVal =
         (expVal << (FloatProp::BIT_WIDTH - 1 - FloatProp::EXPONENT_WIDTH)) &
         FloatProp::EXPONENT_MASK;
@@ -79,7 +79,7 @@ template <> struct FPBits<long double> {
     bits |= expVal;
   }
 
-  LIBC_INLINE constexpr uint16_t get_unbiased_exponent() const {
+  LIBC_INLINE constexpr uint16_t get_biased_exponent() const {
     return uint16_t((bits & FloatProp::EXPONENT_MASK) >>
                     (FloatProp::BIT_WIDTH - 1 - FloatProp::EXPONENT_WIDTH));
   }
@@ -137,7 +137,7 @@ template <> struct FPBits<long double> {
   }
 
   LIBC_INLINE constexpr int get_exponent() const {
-    return int(get_unbiased_exponent()) - EXPONENT_BIAS;
+    return int(get_biased_exponent()) - EXPONENT_BIAS;
   }
 
   // If the number is subnormal, the exponent is treated as if it were the
@@ -147,38 +147,38 @@ template <> struct FPBits<long double> {
   // will give a slightly incorrect result. Additionally, zero has an exponent
   // of zero, and that should actually be treated as zero.
   LIBC_INLINE constexpr int get_explicit_exponent() const {
-    const int unbiased_exp = int(get_unbiased_exponent());
+    const int biased_exp = int(get_biased_exponent());
     if (is_zero()) {
       return 0;
-    } else if (unbiased_exp == 0) {
+    } else if (biased_exp == 0) {
       return 1 - EXPONENT_BIAS;
     } else {
-      return unbiased_exp - EXPONENT_BIAS;
+      return biased_exp - EXPONENT_BIAS;
     }
   }
 
   LIBC_INLINE constexpr bool is_zero() const {
-    return get_unbiased_exponent() == 0 && get_mantissa() == 0 &&
+    return get_biased_exponent() == 0 && get_mantissa() == 0 &&
            get_implicit_bit() == 0;
   }
 
   LIBC_INLINE constexpr bool is_inf() const {
-    return get_unbiased_exponent() == MAX_EXPONENT && get_mantissa() == 0 &&
+    return get_biased_exponent() == MAX_EXPONENT && get_mantissa() == 0 &&
            get_implicit_bit() == 1;
   }
 
   LIBC_INLINE constexpr bool is_nan() const {
-    if (get_unbiased_exponent() == MAX_EXPONENT) {
+    if (get_biased_exponent() == MAX_EXPONENT) {
       return (get_implicit_bit() == 0) || get_mantissa() != 0;
-    } else if (get_unbiased_exponent() != 0) {
+    } else if (get_biased_exponent() != 0) {
       return get_implicit_bit() == 0;
     }
     return false;
   }
 
   LIBC_INLINE constexpr bool is_inf_or_nan() const {
-    return (get_unbiased_exponent() == MAX_EXPONENT) ||
-           (get_unbiased_exponent() != 0 && get_implicit_bit() == 0);
+    return (get_biased_exponent() == MAX_EXPONENT) ||
+           (get_biased_exponent() != 0 && get_implicit_bit() == 0);
   }
 
   // Methods below this are used by tests.
@@ -189,7 +189,7 @@ template <> struct FPBits<long double> {
 
   LIBC_INLINE static constexpr long double inf(bool sign = false) {
     FPBits<long double> bits(0.0l);
-    bits.set_unbiased_exponent(MAX_EXPONENT);
+    bits.set_biased_exponent(MAX_EXPONENT);
     bits.set_implicit_bit(1);
     if (sign) {
       bits.set_sign(true);
@@ -201,7 +201,7 @@ template <> struct FPBits<long double> {
 
   LIBC_INLINE static constexpr long double build_nan(UIntType v) {
     FPBits<long double> bits(0.0l);
-    bits.set_unbiased_exponent(MAX_EXPONENT);
+    bits.set_biased_exponent(MAX_EXPONENT);
     bits.set_implicit_bit(1);
     bits.set_mantissa(v);
     return bits;
@@ -228,10 +228,10 @@ template <> struct FPBits<long double> {
   }
 
   LIBC_INLINE static constexpr FPBits<long double>
-  create_value(bool sign, UIntType unbiased_exp, UIntType mantissa) {
+  create_value(bool sign, UIntType biased_exp, UIntType mantissa) {
     FPBits<long double> result;
     result.set_sign(sign);
-    result.set_unbiased_exponent(unbiased_exp);
+    result.set_biased_exponent(biased_exp);
     result.set_mantissa(mantissa);
     return result;
   }
diff --git a/libc/src/__support/FPUtil/x86_64/NextAfterLongDouble.h b/libc/src/__support/FPUtil/x86_64/NextAfterLongDouble.h
index 4508671b47ee..5e32f766ad58 100644
--- a/libc/src/__support/FPUtil/x86_64/NextAfterLongDouble.h
+++ b/libc/src/__support/FPUtil/x86_64/NextAfterLongDouble.h
@@ -39,8 +39,8 @@ LIBC_INLINE long double nextafter(long double from, long double to) {
 
   // Convert pseudo subnormal number to normal number.
   if (from_bits.get_implicit_bit() == 1 &&
-      from_bits.get_unbiased_exponent() == 0) {
-    from_bits.set_unbiased_exponent(1);
+      from_bits.get_biased_exponent() == 0) {
+    from_bits.set_biased_exponent(1);
   }
 
   using UIntType = FPBits::UIntType;
@@ -59,7 +59,7 @@ LIBC_INLINE long double nextafter(long double from, long double to) {
         // Incrementing exponent might overflow the value to infinity,
         // which is what is expected. Since NaNs are handling separately,
         // it will never overflow "beyond" infinity.
-        from_bits.set_unbiased_exponent(from_bits.get_unbiased_exponent() + 1);
+        from_bits.set_biased_exponent(from_bits.get_biased_exponent() + 1);
         if (from_bits.is_inf())
           raise_except_if_required(FE_OVERFLOW | FE_INEXACT);
         return from_bits;
@@ -75,7 +75,7 @@ LIBC_INLINE long double nextafter(long double from, long double to) {
         from_bits.set_mantissa(MANTISSA_MASK);
         // from == 0 is handled separately so decrementing the exponent will not
         // lead to underflow.
-        from_bits.set_unbiased_exponent(from_bits.get_unbiased_exponent() - 1);
+        from_bits.set_biased_exponent(from_bits.get_biased_exponent() - 1);
         return from_bits;
       } else {
         --int_val;
@@ -94,7 +94,7 @@ LIBC_INLINE long double nextafter(long double from, long double to) {
         from_bits.set_mantissa(MANTISSA_MASK);
         // from == 0 is handled separately so decrementing the exponent will not
         // lead to underflow.
-        from_bits.set_unbiased_exponent(from_bits.get_unbiased_exponent() - 1);
+        from_bits.set_biased_exponent(from_bits.get_biased_exponent() - 1);
         return from_bits;
       } else {
         --int_val;
@@ -107,7 +107,7 @@ LIBC_INLINE long double nextafter(long double from, long double to) {
         // Incrementing exponent might overflow the value to infinity,
         // which is what is expected. Since NaNs are handling separately,
         // it will never overflow "beyond" infinity.
-        from_bits.set_unbiased_exponent(from_bits.get_unbiased_exponent() + 1);
+        from_bits.set_biased_exponent(from_bits.get_biased_exponent() + 1);
         if (from_bits.is_inf())
           raise_except_if_required(FE_OVERFLOW | FE_INEXACT);
         return from_bits;
diff --git a/libc/src/__support/str_to_float.h b/libc/src/__support/str_to_float.h
index ad73e93f6faa..d495c7a073cd 100644
--- a/libc/src/__support/str_to_float.h
+++ b/libc/src/__support/str_to_float.h
@@ -92,7 +92,7 @@ template <class T> LIBC_INLINE void set_implicit_bit(fputil::FPBits<T> &) {
 template <>
 LIBC_INLINE void
 set_implicit_bit<long double>(fputil::FPBits<long double> &result) {
-  result.set_implicit_bit(result.get_unbiased_exponent() != 0);
+  result.set_implicit_bit(result.get_biased_exponent() != 0);
 }
 #endif
 
@@ -643,7 +643,7 @@ clinger_fast_path(ExpandedFloat<T> init_num,
 
   ExpandedFloat<T> output;
   output.mantissa = result.get_mantissa();
-  output.exponent = result.get_unbiased_exponent();
+  output.exponent = result.get_biased_exponent();
   return output;
 }
 
@@ -1164,7 +1164,7 @@ LIBC_INLINE StrToNumResult<T> strtofloatingpoint(const char *__restrict src) {
     }
     seen_digit = parse_result.parsed_len != 0;
     result.set_mantissa(parse_result.value.mantissa);
-    result.set_unbiased_exponent(parse_result.value.exponent);
+    result.set_biased_exponent(parse_result.value.exponent);
     index += parse_result.parsed_len;
     error = parse_result.error;
   } else if (tolower(src[index]) == 'n') { // NaN
diff --git a/libc/src/math/generic/expf.cpp b/libc/src/math/generic/expf.cpp
index 5a938a7a1c22..12f62960fc10 100644
--- a/libc/src/math/generic/expf.cpp
+++ b/libc/src/math/generic/expf.cpp
@@ -37,7 +37,7 @@ LLVM_LIBC_FUNCTION(float, expf, (float x)) {
   // When |x| >= 89, |x| < 2^-25, or x is nan
   if (LIBC_UNLIKELY(x_abs >= 0x42b2'0000U || x_abs <= 0x3280'0000U)) {
     // |x| < 2^-25
-    if (xbits.get_unbiased_exponent() <= 101) {
+    if (xbits.get_biased_exponent() <= 101) {
       return 1.0f + x;
     }
 
diff --git a/libc/src/math/generic/explogxf.h b/libc/src/math/generic/explogxf.h
index 156c24c21e23..77ec9cb94e08 100644
--- a/libc/src/math/generic/explogxf.h
+++ b/libc/src/math/generic/explogxf.h
@@ -285,7 +285,7 @@ LIBC_INLINE static double log2_eval(double x) {
       (LOG_P1_SIZE - 1);
 
   bs.bits &= FPB::FloatProp::MANTISSA_MASK >> LOG_P1_BITS;
-  bs.set_unbiased_exponent(FPB::FloatProp::EXPONENT_BIAS);
+  bs.set_biased_exponent(FPB::FloatProp::EXPONENT_BIAS);
   double dx = (bs.get_val() - 1.0) * LOG_P1_1_OVER[p1];
 
   // Taylor series for log(2,1+x)
@@ -316,7 +316,7 @@ LIBC_INLINE static double log_eval(double x) {
 
   // Set bs to (1 + (mx - p1*2^(-7))
   bs.bits &= FPB::FloatProp::MANTISSA_MASK >> 7;
-  bs.set_unbiased_exponent(FPB::FloatProp::EXPONENT_BIAS);
+  bs.set_biased_exponent(FPB::FloatProp::EXPONENT_BIAS);
   // dx = (mx - p1*2^(-7)) / (1 + p1*2^(-7)).
   double dx = (bs.get_val() - 1.0) * ONE_OVER_F[p1];
 
diff --git a/libc/src/math/generic/hypotf.cpp b/libc/src/math/generic/hypotf.cpp
index 3fedeed4ed26..389de3c45029 100644
--- a/libc/src/math/generic/hypotf.cpp
+++ b/libc/src/math/generic/hypotf.cpp
@@ -19,8 +19,8 @@ LLVM_LIBC_FUNCTION(float, hypotf, (float x, float y)) {
 
   FPBits x_bits(x), y_bits(y);
 
-  uint16_t x_exp = x_bits.get_unbiased_exponent();
-  uint16_t y_exp = y_bits.get_unbiased_exponent();
+  uint16_t x_exp = x_bits.get_biased_exponent();
+  uint16_t y_exp = y_bits.get_biased_exponent();
   uint16_t exp_diff = (x_exp > y_exp) ? (x_exp - y_exp) : (y_exp - x_exp);
 
   if (exp_diff >= fputil::MantissaWidth<float>::VALUE + 2) {
diff --git a/libc/src/math/generic/log10f.cpp b/libc/src/math/generic/log10f.cpp
index bc9af75169b1..927af35c98f2 100644
--- a/libc/src/math/generic/log10f.cpp
+++ b/libc/src/math/generic/log10f.cpp
@@ -187,7 +187,7 @@ LLVM_LIBC_FUNCTION(float, log10f, (float x)) {
   // Extract 7 leading fractional bits of the mantissa
   int index = (x_u >> 16) & 0x7F;
   // Set bits to 1.m
-  xbits.set_unbiased_exponent(0x7F);
+  xbits.set_biased_exponent(0x7F);
 
   float u = static_cast<float>(xbits);
   double v;
diff --git a/libc/src/math/generic/log1p.cpp b/libc/src/math/generic/log1p.cpp
index 02299e271770..c8b45fd57b42 100644
--- a/libc/src/math/generic/log1p.cpp
+++ b/libc/src/math/generic/log1p.cpp
@@ -880,7 +880,7 @@ LLVM_LIBC_FUNCTION(double, log1p, (double x)) {
 
   fputil::DoubleDouble x_dd{0.0, 0.0};
 
-  uint16_t x_exp = xbits.get_unbiased_exponent();
+  uint16_t x_exp = xbits.get_biased_exponent();
 
   if (x_exp >= EXPONENT_BIAS) {
     // |x| >= 1
@@ -909,7 +909,7 @@ LLVM_LIBC_FUNCTION(double, log1p, (double x)) {
     }
   } else {
     // |x| < 1
-    if (LIBC_UNLIKELY(xbits.get_unbiased_exponent() <
+    if (LIBC_UNLIKELY(xbits.get_biased_exponent() <
                       EXPONENT_BIAS - MANTISSA_WIDTH - 1)) {
       // Quick return when |x| < 2^-53.
       // Since log(1 + x) = x - x^2/2 + x^3/3 - ...,
diff --git a/libc/src/math/generic/log1pf.cpp b/libc/src/math/generic/log1pf.cpp
index 023387d8add0..fd3cf4647fd0 100644
--- a/libc/src/math/generic/log1pf.cpp
+++ b/libc/src/math/generic/log1pf.cpp
@@ -60,7 +60,7 @@ LIBC_INLINE float log(double x) {
       xbits.get_mantissa() >> 45); // fputil::MantissaWidth<double>::VALUE - 7
 
   // Set bits to 1.m
-  xbits.set_unbiased_exponent(0x3FF);
+  xbits.set_biased_exponent(0x3FF);
   FPBits f = xbits;
 
   // Clear the lowest 45 bits.
diff --git a/libc/src/math/generic/log2f.cpp b/libc/src/math/generic/log2f.cpp
index 7665a90f0923..4bbc9f51c3d2 100644
--- a/libc/src/math/generic/log2f.cpp
+++ b/libc/src/math/generic/log2f.cpp
@@ -87,10 +87,10 @@ LLVM_LIBC_FUNCTION(float, log2f, (float x)) {
     m -= 23;
   }
 
-  m += xbits.get_unbiased_exponent();
+  m += xbits.get_biased_exponent();
   int index = xbits.get_mantissa() >> 16;
   // Set bits to 1.m
-  xbits.set_unbiased_exponent(0x7F);
+  xbits.set_biased_exponent(0x7F);
 
   float u = static_cast<float>(xbits);
   double v;
diff --git a/libc/src/math/generic/logf.cpp b/libc/src/math/generic/logf.cpp
index 1f689f25931d..2dfada38b972 100644
--- a/libc/src/math/generic/logf.cpp
+++ b/libc/src/math/generic/logf.cpp
@@ -135,7 +135,7 @@ LLVM_LIBC_FUNCTION(float, logf, (float x)) {
   // rounding mode.
   if (LIBC_UNLIKELY((x_u & 0x007f'ffffU) == 0))
     return static_cast<float>(
-        static_cast<double>(m + xbits.get_unbiased_exponent()) * LOG_2);
+        static_cast<double>(m + xbits.get_biased_exponent()) * LOG_2);
 #endif // LIBC_TARGET_CPU_HAS_FMA
 
   uint32_t mant = xbits.get_mantissa();
@@ -146,7 +146,7 @@ LLVM_LIBC_FUNCTION(float, logf, (float x)) {
   m += static_cast<int>((x_u + (1 << 16)) >> 23);
 
   // Set bits to 1.m
-  xbits.set_unbiased_exponent(0x7F);
+  xbits.set_biased_exponent(0x7F);
 
   float u = static_cast<float>(xbits);
   double v;
diff --git a/libc/src/math/generic/powf.cpp b/libc/src/math/generic/powf.cpp
index 5f2e95b44e52..17ccb41fc462 100644
--- a/libc/src/math/generic/powf.cpp
+++ b/libc/src/math/generic/powf.cpp
@@ -410,8 +410,8 @@ LIBC_INLINE bool is_integer(float x) {
 
 LIBC_INLINE bool larger_exponent(double a, double b) {
   using DoubleBits = typename fputil::FPBits<double>;
-  return DoubleBits(a).get_unbiased_exponent() >=
-         DoubleBits(b).get_unbiased_exponent();
+  return DoubleBits(a).get_biased_exponent() >=
+         DoubleBits(b).get_biased_exponent();
 }
 
 // Calculate 2^(y * log2(x)) in double-double precision.
diff --git a/libc/test/src/__support/FPUtil/fpbits_test.cpp b/libc/test/src/__support/FPUtil/fpbits_test.cpp
index 52635cc2af09..fa743855c486 100644
--- a/libc/test/src/__support/FPUtil/fpbits_test.cpp
+++ b/libc/test/src/__support/FPUtil/fpbits_test.cpp
@@ -24,7 +24,7 @@ TEST(LlvmLibcFPBitsTest, FloatType) {
 
   FloatBits zero(0.0f);
   EXPECT_EQ(zero.get_sign(), false);
-  EXPECT_EQ(zero.get_unbiased_exponent(), static_cast<uint16_t>(0));
+  EXPECT_EQ(zero.get_biased_exponent(), static_cast<uint16_t>(0));
   EXPECT_EQ(zero.get_mantissa(), static_cast<uint32_t>(0));
   EXPECT_EQ(zero.uintval(), static_cast<uint32_t>(0x00000000));
   EXPECT_STREQ(LIBC_NAMESPACE::str(zero).c_str(),
@@ -32,7 +32,7 @@ TEST(LlvmLibcFPBitsTest, FloatType) {
 
   FloatBits negzero(-0.0f);
   EXPECT_EQ(negzero.get_sign(), true);
-  EXPECT_EQ(negzero.get_unbiased_exponent(), static_cast<uint16_t>(0));
+  EXPECT_EQ(negzero.get_biased_exponent(), static_cast<uint16_t>(0));
   EXPECT_EQ(negzero.get_mantissa(), static_cast<uint32_t>(0));
   EXPECT_EQ(negzero.uintval(), static_cast<uint32_t>(0x80000000));
   EXPECT_STREQ(LIBC_NAMESPACE::str(negzero).c_str(),
@@ -40,7 +40,7 @@ TEST(LlvmLibcFPBitsTest, FloatType) {
 
   FloatBits one(1.0f);
   EXPECT_EQ(one.get_sign(), false);
-  EXPECT_EQ(one.get_unbiased_exponent(), static_cast<uint16_t>(0x7F));
+  EXPECT_EQ(one.get_biased_exponent(), static_cast<uint16_t>(0x7F));
   EXPECT_EQ(one.get_mantissa(), static_cast<uint32_t>(0));
   EXPECT_EQ(one.uintval(), static_cast<uint32_t>(0x3F800000));
   EXPECT_STREQ(LIBC_NAMESPACE::str(one).c_str(),
@@ -48,7 +48,7 @@ TEST(LlvmLibcFPBitsTest, FloatType) {
 
   FloatBits negone(-1.0f);
   EXPECT_EQ(negone.get_sign(), true);
-  EXPECT_EQ(negone.get_unbiased_exponent(), static_cast<uint16_t>(0x7F));
+  EXPECT_EQ(negone.get_biased_exponent(), static_cast<uint16_t>(0x7F));
   EXPECT_EQ(negone.get_mantissa(), static_cast<uint32_t>(0));
   EXPECT_EQ(negone.uintval(), static_cast<uint32_t>(0xBF800000));
   EXPECT_STREQ(LIBC_NAMESPACE::str(negone).c_str(),
@@ -56,7 +56,7 @@ TEST(LlvmLibcFPBitsTest, FloatType) {
 
   FloatBits num(1.125f);
   EXPECT_EQ(num.get_sign(), false);
-  EXPECT_EQ(num.get_unbiased_exponent(), static_cast<uint16_t>(0x7F));
+  EXPECT_EQ(num.get_biased_exponent(), static_cast<uint16_t>(0x7F));
   EXPECT_EQ(num.get_mantissa(), static_cast<uint32_t>(0x00100000));
   EXPECT_EQ(num.uintval(), static_cast<uint32_t>(0x3F900000));
   EXPECT_STREQ(LIBC_NAMESPACE::str(num).c_str(),
@@ -64,7 +64,7 @@ TEST(LlvmLibcFPBitsTest, FloatType) {
 
   FloatBits negnum(-1.125f);
   EXPECT_EQ(negnum.get_sign(), true);
-  EXPECT_EQ(negnum.get_unbiased_exponent(), static_cast<uint16_t>(0x7F));
+  EXPECT_EQ(negnum.get_biased_exponent(), static_cast<uint16_t>(0x7F));
   EXPECT_EQ(negnum.get_mantissa(), static_cast<uint32_t>(0x00100000));
   EXPECT_EQ(negnum.uintval(), static_cast<uint32_t>(0xBF900000));
   EXPECT_STREQ(LIBC_NAMESPACE::str(negnum).c_str(),
@@ -84,7 +84,7 @@ TEST(LlvmLibcFPBitsTest, DoubleType) {
 
   DoubleBits zero(0.0);
   EXPECT_EQ(zero.get_sign(), false);
-  EXPECT_EQ(zero.get_unbiased_exponent(), static_cast<uint16_t>(0x0000));
+  EXPECT_EQ(zero.get_biased_exponent(), static_cast<uint16_t>(0x0000));
   EXPECT_EQ(zero.get_mantissa(), static_cast<uint64_t>(0x0000000000000000));
   EXPECT_EQ(zero.uintval(), static_cast<uint64_t>(0x0000000000000000));
   EXPECT_STREQ(LIBC_NAMESPACE::str(zero).c_str(),
@@ -92,7 +92,7 @@ TEST(LlvmLibcFPBitsTest, DoubleType) {
 
   DoubleBits negzero(-0.0);
   EXPECT_EQ(negzero.get_sign(), true);
-  EXPECT_EQ(negzero.get_unbiased_exponent(), static_cast<uint16_t>(0x0000));
+  EXPECT_EQ(negzero.get_biased_exponent(), static_cast<uint16_t>(0x0000));
   EXPECT_EQ(negzero.get_mantissa(), static_cast<uint64_t>(0x0000000000000000));
   EXPECT_EQ(negzero.uintval(), static_cast<uint64_t>(0x8000000000000000));
   EXPECT_STREQ(LIBC_NAMESPACE::str(negzero).c_str(),
@@ -100,7 +100,7 @@ TEST(LlvmLibcFPBitsTest, DoubleType) {
 
   DoubleBits one(1.0);
   EXPECT_EQ(one.get_sign(), false);
-  EXPECT_EQ(one.get_unbiased_exponent(), static_cast<uint16_t>(0x03FF));
+  EXPECT_EQ(one.get_biased_exponent(), static_cast<uint16_t>(0x03FF));
   EXPECT_EQ(one.get_mantissa(), static_cast<uint64_t>(0x0000000000000000));
   EXPECT_EQ(one.uintval(), static_cast<uint64_t>(0x3FF0000000000000));
   EXPECT_STREQ(LIBC_NAMESPACE::str(one).c_str(),
@@ -108,7 +108,7 @@ TEST(LlvmLibcFPBitsTest, DoubleType) {
 
   DoubleBits negone(-1.0);
   EXPECT_EQ(negone.get_sign(), true);
-  EXPECT_EQ(negone.get_unbiased_exponent(), static_cast<uint16_t>(0x03FF));
+  EXPECT_EQ(negone.get_biased_exponent(), static_cast<uint16_t>(0x03FF));
   EXPECT_EQ(negone.get_mantissa(), static_cast<uint64_t>(0x0000000000000000));
   EXPECT_EQ(negone.uintval(), static_cast<uint64_t>(0xBFF0000000000000));
   EXPECT_STREQ(LIBC_NAMESPACE::str(negone).c_str(),
@@ -116,7 +116,7 @@ TEST(LlvmLibcFPBitsTest, DoubleType) {
 
   DoubleBits num(1.125);
   EXPECT_EQ(num.get_sign(), false);
-  EXPECT_EQ(num.get_unbiased_exponent(), static_cast<uint16_t>(0x03FF));
+  EXPECT_EQ(num.get_biased_exponent(), static_cast<uint16_t>(0x03FF));
   EXPECT_EQ(num.get_mantissa(), static_cast<uint64_t>(0x0002000000000000));
   EXPECT_EQ(num.uintval(), static_cast<uint64_t>(0x3FF2000000000000));
   EXPECT_STREQ(LIBC_NAMESPACE::str(num).c_str(),
@@ -124,7 +124,7 @@ TEST(LlvmLibcFPBitsTest, DoubleType) {
 
   DoubleBits negnum(-1.125);
   EXPECT_EQ(negnum.get_sign(), true);
-  EXPECT_EQ(negnum.get_unbiased_exponent(), static_cast<uint16_t>(0x03FF));
+  EXPECT_EQ(negnum.get_biased_exponent(), static_cast<uint16_t>(0x03FF));
   EXPECT_EQ(negnum.get_mantissa(), static_cast<uint64_t>(0x0002000000000000));
   EXPECT_EQ(negnum.uintval(), static_cast<uint64_t>(0xBFF2000000000000));
   EXPECT_STREQ(LIBC_NAMESPACE::str(negnum).c_str(),
@@ -150,7 +150,7 @@ TEST(LlvmLibcFPBitsTest, X86LongDoubleType) {
 
   LongDoubleBits zero(0.0l);
   EXPECT_EQ(zero.get_sign(), false);
-  EXPECT_EQ(zero.get_unbiased_exponent(), static_cast<uint16_t>(0x0000));
+  EXPECT_EQ(zero.get_biased_exponent(), static_cast<uint16_t>(0x0000));
   EXPECT_EQ(zero.get_mantissa(), static_cast<UInt128>(0x0000000000000000)
                                      << 64);
   EXPECT_EQ(zero.uintval(), static_cast<UInt128>(0x0000000000000000) << 64);
@@ -161,7 +161,7 @@ TEST(LlvmLibcFPBitsTest, X86LongDoubleType) {
 
   LongDoubleBits negzero(-0.0l);
   EXPECT_EQ(negzero.get_sign(), true);
-  EXPECT_EQ(negzero.get_unbiased_exponent(), static_cast<uint16_t>(0x0000));
+  EXPECT_EQ(negzero.get_biased_exponent(), static_cast<uint16_t>(0x0000));
   EXPECT_EQ(negzero.get_mantissa(), static_cast<UInt128>(0x0000000000000000)
                                         << 64);
   EXPECT_EQ(negzero.uintval(), static_cast<UInt128>(0x1) << 79);
@@ -172,7 +172,7 @@ TEST(LlvmLibcFPBitsTest, X86LongDoubleType) {
 
   LongDoubleBits one(1.0l);
   EXPECT_EQ(one.get_sign(), false);
-  EXPECT_EQ(one.get_unbiased_exponent(), static_cast<uint16_t>(0x3FFF));
+  EXPECT_EQ(one.get_biased_exponent(), static_cast<uint16_t>(0x3FFF));
   EXPECT_EQ(one.get_mantissa(), static_cast<UInt128>(0x0000000000000000) << 64);
   EXPECT_EQ(one.uintval(), static_cast<UInt128>(0x3FFF8) << 60);
   EXPECT_STREQ(
@@ -182,7 +182,7 @@ TEST(LlvmLibcFPBitsTest, X86LongDoubleType) {
 
   LongDoubleBits negone(-1.0l);
   EXPECT_EQ(negone.get_sign(), true);
-  EXPECT_EQ(negone.get_unbiased_exponent(), static_cast<uint16_t>(0x3FFF));
+  EXPECT_EQ(negone.get_biased_exponent(), static_cast<uint16_t>(0x3FFF));
   EXPECT_EQ(negone.get_mantissa(), static_cast<UInt128>(0x0000000000000000)
                                        << 64);
   EXPECT_EQ(negone.uintval(), static_cast<UInt128>(0xBFFF8) << 60);
@@ -193,7 +193,7 @@ TEST(LlvmLibcFPBitsTest, X86LongDoubleType) {
 
   LongDoubleBits num(1.125l);
   EXPECT_EQ(num.get_sign(), false);
-  EXPECT_EQ(num.get_unbiased_exponent(), static_cast<uint16_t>(0x3FFF));
+  EXPECT_EQ(num.get_biased_exponent(), static_cast<uint16_t>(0x3FFF));
   EXPECT_EQ(num.get_mantissa(), static_cast<UInt128>(0x1) << 60);
   EXPECT_EQ(num.uintval(), static_cast<UInt128>(0x3FFF9) << 60);
   EXPECT_STREQ(
@@ -203,7 +203,7 @@ TEST(LlvmLibcFPBitsTest, X86LongDoubleType) {
 
   LongDoubleBits negnum(-1.125l);
   EXPECT_EQ(negnum.get_sign(), true);
-  EXPECT_EQ(negnum.get_unbiased_exponent(), static_cast<uint16_t>(0x3FFF));
+  EXPECT_EQ(negnum.get_biased_exponent(), static_cast<uint16_t>(0x3FFF));
   EXPECT_EQ(negnum.get_mantissa(), static_cast<UInt128>(0x1) << 60);
   EXPECT_EQ(negnum.uintval(), static_cast<UInt128>(0xBFFF9) << 60);
   EXPECT_STREQ(
@@ -230,7 +230,7 @@ TEST(LlvmLibcFPBitsTest, LongDoubleType) {
 
   LongDoubleBits zero(0.0l);
   EXPECT_EQ(zero.get_sign(), false);
-  EXPECT_EQ(zero.get_unbiased_exponent(), static_cast<uint16_t>(0x0000));
+  EXPECT_EQ(zero.get_biased_exponent(), static_cast<uint16_t>(0x0000));
   EXPECT_EQ(zero.get_mantissa(), static_cast<UInt128>(0x0000000000000000)
                                      << 64);
   EXPECT_EQ(zero.uintval(), static_cast<UInt128>(0x0000000000000000) << 64);
@@ -240,7 +240,7 @@ TEST(LlvmLibcFPBitsTest, LongDoubleType) {
 
   LongDoubleBits negzero(-0.0l);
   EXPECT_EQ(negzero.get_sign(), true);
-  EXPECT_EQ(negzero.get_unbiased_exponent(), static_cast<uint16_t>(0x0000));
+  EXPECT_EQ(negzero.get_biased_exponent(), static_cast<uint16_t>(0x0000));
   EXPECT_EQ(negzero.get_mantissa(), static_cast<UInt128>(0x0000000000000000)
                                         << 64);
   EXPECT_EQ(negzero.uintval(), static_cast<UInt128>(0x1) << 127);
@@ -250,7 +250,7 @@ TEST(LlvmLibcFPBitsTest, LongDoubleType) {
 
   LongDoubleBits one(1.0l);
   EXPECT_EQ(one.get_sign(), false);
-  EXPECT_EQ(one.get_unbiased_exponent(), static_cast<uint16_t>(0x3FFF));
+  EXPECT_EQ(one.get_biased_exponent(), static_cast<uint16_t>(0x3FFF));
   EXPECT_EQ(one.get_mantissa(), static_cast<UInt128>(0x0000000000000000) << 64);
   EXPECT_EQ(one.uintval(), static_cast<UInt128>(0x3FFF) << 112);
   EXPECT_STREQ(LIBC_NAMESPACE::str(one).c_str(),
@@ -259,7 +259,7 @@ TEST(LlvmLibcFPBitsTest, LongDoubleType) {
 
   LongDoubleBits negone(-1.0l);
   EXPECT_EQ(negone.get_sign(), true);
-  EXPECT_EQ(negone.get_unbiased_exponent(), static_cast<uint16_t>(0x3FFF));
+  EXPECT_EQ(negone.get_biased_exponent(), static_cast<uint16_t>(0x3FFF));
   EXPECT_EQ(negone.get_mantissa(), static_cast<UInt128>(0x0000000000000000)
                                        << 64);
   EXPECT_EQ(negone.uintval(), static_cast<UInt128>(0xBFFF) << 112);
@@ -269,7 +269,7 @@ TEST(LlvmLibcFPBitsTest, LongDoubleType) {
 
   LongDoubleBits num(1.125l);
   EXPECT_EQ(num.get_sign(), false);
-  EXPECT_EQ(num.get_unbiased_exponent(), static_cast<uint16_t>(0x3FFF));
+  EXPECT_EQ(num.get_biased_exponent(), static_cast<uint16_t>(0x3FFF));
   EXPECT_EQ(num.get_mantissa(), static_cast<UInt128>(0x2) << 108);
   EXPECT_EQ(num.uintval(), static_cast<UInt128>(0x3FFF2) << 108);
   EXPECT_STREQ(LIBC_NAMESPACE::str(num).c_str(),
@@ -278,7 +278,7 @@ TEST(LlvmLibcFPBitsTest, LongDoubleType) {
 
   LongDoubleBits negnum(-1.125l);
   EXPECT_EQ(negnum.get_sign(), true);
-  EXPECT_EQ(negnum.get_unbiased_exponent(), static_cast<uint16_t>(0x3FFF));
+  EXPECT_EQ(negnum.get_biased_exponent(), static_cast<uint16_t>(0x3FFF));
   EXPECT_EQ(negnum.get_mantissa(), static_cast<UInt128>(0x2) << 108);
   EXPECT_EQ(negnum.uintval(), static_cast<UInt128>(0xBFFF2) << 108);
   EXPECT_STREQ(LIBC_NAMESPACE::str(negnum).c_str(),
@@ -303,7 +303,7 @@ TEST(LlvmLibcFPBitsTest, Float128Type) {
 
   Float128Bits zero(Float128Bits::zero());
   EXPECT_EQ(zero.get_sign(), false);
-  EXPECT_EQ(zero.get_unbiased_exponent(), static_cast<uint16_t>(0x0000));
+  EXPECT_EQ(zero.get_biased_exponent(), static_cast<uint16_t>(0x0000));
   EXPECT_EQ(zero.get_mantissa(), static_cast<UInt128>(0x0000000000000000)
                                      << 64);
   EXPECT_EQ(zero.uintval(), static_cast<UInt128>(0x0000000000000000) << 64);
@@ -313,7 +313,7 @@ TEST(LlvmLibcFPBitsTest, Float128Type) {
 
   Float128Bits negzero(Float128Bits::neg_zero());
   EXPECT_EQ(negzero.get_sign(), true);
-  EXPECT_EQ(negzero.get_unbiased_exponent(), static_cast<uint16_t>(0x0000));
+  EXPECT_EQ(negzero.get_biased_exponent(), static_cast<uint16_t>(0x0000));
   EXPECT_EQ(negzero.get_mantissa(), static_cast<UInt128>(0x0000000000000000)
                                         << 64);
   EXPECT_EQ(negzero.uintval(), static_cast<UInt128>(0x1) << 127);
@@ -323,7 +323,7 @@ TEST(LlvmLibcFPBitsTest, Float128Type) {
 
   Float128Bits one(float128(1.0));
   EXPECT_EQ(one.get_sign(), false);
-  EXPECT_EQ(one.get_unbiased_exponent(), static_cast<uint16_t>(0x3FFF));
+  EXPECT_EQ(one.get_biased_exponent(), static_cast<uint16_t>(0x3FFF));
   EXPECT_EQ(one.get_mantissa(), static_cast<UInt128>(0x0000000000000000) << 64);
   EXPECT_EQ(one.uintval(), static_cast<UInt128>(0x3FFF) << 112);
   EXPECT_STREQ(LIBC_NAMESPACE::str(one).c_str(),
@@ -332,7 +332,7 @@ TEST(LlvmLibcFPBitsTest, Float128Type) {
 
   Float128Bits negone(float128(-1.0));
   EXPECT_EQ(negone.get_sign(), true);
-  EXPECT_EQ(negone.get_unbiased_exponent(), static_cast<uint16_t>(0x3FFF));
+  EXPECT_EQ(negone.get_biased_exponent(), static_cast<uint16_t>(0x3FFF));
   EXPECT_EQ(negone.get_mantissa(), static_cast<UInt128>(0x0000000000000000)
                                        << 64);
   EXPECT_EQ(negone.uintval(), static_cast<UInt128>(0xBFFF) << 112);
@@ -342,7 +342,7 @@ TEST(LlvmLibcFPBitsTest, Float128Type) {
 
   Float128Bits num(float128(1.125));
   EXPECT_EQ(num.get_sign(), false);
-  EXPECT_EQ(num.get_unbiased_exponent(), static_cast<uint16_t>(0x3FFF));
+  EXPECT_EQ(num.get_biased_exponent(), static_cast<uint16_t>(0x3FFF));
   EXPECT_EQ(num.get_mantissa(), static_cast<UInt128>(0x2) << 108);
   EXPECT_EQ(num.uintval(), static_cast<UInt128>(0x3FFF2) << 108);
   EXPECT_STREQ(LIBC_NAMESPACE::str(num).c_str(),
@@ -351,7 +351,7 @@ TEST(LlvmLibcFPBitsTest, Float128Type) {
 
   Float128Bits negnum(float128(-1.125));
   EXPECT_EQ(negnum.get_sign(), true);
-  EXPECT_EQ(negnum.get_unbiased_exponent(), static_cast<uint16_t>(0x3FFF));
+  EXPECT_EQ(negnum.get_biased_exponent(), static_cast<uint16_t>(0x3FFF));
   EXPECT_EQ(negnum.get_mantissa(), static_cast<UInt128>(0x2) << 108);
   EXPECT_EQ(negnum.uintval(), static_cast<UInt128>(0xBFFF2) << 108);
   EXPECT_STREQ(LIBC_NAMESPACE::str(negnum).c_str(),
diff --git a/libc/test/src/math/LdExpTest.h b/libc/test/src/math/LdExpTest.h
index bffa7335fb25..a75c8ef31a2c 100644
--- a/libc/test/src/math/LdExpTest.h
+++ b/libc/test/src/math/LdExpTest.h
@@ -132,7 +132,7 @@ public:
     FPBits result_bits(result);
     ASSERT_FALSE(result_bits.is_zero());
     // Verify that the result is indeed subnormal.
-    ASSERT_EQ(result_bits.get_unbiased_exponent(), uint16_t(0));
+    ASSERT_EQ(result_bits.get_biased_exponent(), uint16_t(0));
     // But if the exp is so less that normalization leads to zero, then
     // the result should be zero.
     result = func(x, -FPBits::MAX_EXPONENT - int(MANTISSA_WIDTH) - 5);
diff --git a/libc/test/src/math/NextAfterTest.h b/libc/test/src/math/NextAfterTest.h
index 4e450cf5bc1e..57a801dfb28a 100644
--- a/libc/test/src/math/NextAfterTest.h
+++ b/libc/test/src/math/NextAfterTest.h
@@ -162,30 +162,28 @@ public:
     result = func(x, 0);
     FPBits x_bits = FPBits(x);
     FPBits result_bits = FPBits(result);
-    ASSERT_EQ(result_bits.get_unbiased_exponent(),
-              uint16_t(x_bits.get_unbiased_exponent() - 1));
+    ASSERT_EQ(result_bits.get_biased_exponent(),
+              uint16_t(x_bits.get_biased_exponent() - 1));
     ASSERT_EQ(result_bits.get_mantissa(),
               (UIntType(1) << MantissaWidth::VALUE) - 1);
 
     result = func(x, T(33.0));
     result_bits = FPBits(result);
-    ASSERT_EQ(result_bits.get_unbiased_exponent(),
-              x_bits.get_unbiased_exponent());
+    ASSERT_EQ(result_bits.get_biased_exponent(), x_bits.get_biased_exponent());
     ASSERT_EQ(result_bits.get_mantissa(), x_bits.get_mantissa() + UIntType(1));
 
     x = -x;
 
     result = func(x, 0);
     result_bits = FPBits(result);
-    ASSERT_EQ(result_bits.get_unbiased_exponent(),
-              uint16_t(x_bits.get_unbiased_exponent() - 1));
+    ASSERT_EQ(result_bits.get_biased_exponent(),
+              uint16_t(x_bits.get_biased_exponent() - 1));
     ASSERT_EQ(result_bits.get_mantissa(),
               (UIntType(1) << MantissaWidth::VALUE) - 1);
 
     result = func(x, T(-33.0));
     result_bits = FPBits(result);
-    ASSERT_EQ(result_bits.get_unbiased_exponent(),
-              x_bits.get_unbiased_exponent());
+    ASSERT_EQ(result_bits.get_biased_exponent(), x_bits.get_biased_exponent());
     ASSERT_EQ(result_bits.get_mantissa(), x_bits.get_mantissa() + UIntType(1));
   }
 };
diff --git a/libc/test/src/math/RoundToIntegerTest.h b/libc/test/src/math/RoundToIntegerTest.h
index 6b205869e7a7..1a976e97359e 100644
--- a/libc/test/src/math/RoundToIntegerTest.h
+++ b/libc/test/src/math/RoundToIntegerTest.h
@@ -126,7 +126,7 @@ public:
     // We start with 1.0 so that the implicit bit for x86 long doubles
     // is set.
     FPBits bits(F(1.0));
-    bits.set_unbiased_exponent(EXPONENT_LIMIT + FPBits::EXPONENT_BIAS);
+    bits.set_biased_exponent(EXPONENT_LIMIT + FPBits::EXPONENT_BIAS);
     bits.set_sign(1);
     bits.set_mantissa(0);
 
@@ -190,7 +190,7 @@ public:
     // We start with 1.0 so that the implicit bit for x86 long doubles
     // is set.
     FPBits bits(F(1.0));
-    bits.set_unbiased_exponent(EXPONENT_LIMIT + FPBits::EXPONENT_BIAS);
+    bits.set_biased_exponent(EXPONENT_LIMIT + FPBits::EXPONENT_BIAS);
     bits.set_sign(1);
     bits.set_mantissa(UIntType(0x1)
                       << (LIBC_NAMESPACE::fputil::MantissaWidth<F>::VALUE - 1));
diff --git a/libc/test/src/math/smoke/LdExpTest.h b/libc/test/src/math/smoke/LdExpTest.h
index bffa7335fb25..a75c8ef31a2c 100644
--- a/libc/test/src/math/smoke/LdExpTest.h
+++ b/libc/test/src/math/smoke/LdExpTest.h
@@ -132,7 +132,7 @@ public:
     FPBits result_bits(result);
     ASSERT_FALSE(result_bits.is_zero());
     // Verify that the result is indeed subnormal.
-    ASSERT_EQ(result_bits.get_unbiased_exponent(), uint16_t(0));
+    ASSERT_EQ(result_bits.get_biased_exponent(), uint16_t(0));
     // But if the exp is so less that normalization leads to zero, then
     // the result should be zero.
     result = func(x, -FPBits::MAX_EXPONENT - int(MANTISSA_WIDTH) - 5);
diff --git a/libc/test/src/math/smoke/NextAfterTest.h b/libc/test/src/math/smoke/NextAfterTest.h
index 1b082050a598..29098e0f49a4 100644
--- a/libc/test/src/math/smoke/NextAfterTest.h
+++ b/libc/test/src/math/smoke/NextAfterTest.h
@@ -173,30 +173,28 @@ public:
     result = func(x, 0);
     FPBits x_bits = FPBits(x);
     FPBits result_bits = FPBits(result);
-    ASSERT_EQ(result_bits.get_unbiased_exponent(),
-              uint16_t(x_bits.get_unbiased_exponent() - 1));
+    ASSERT_EQ(result_bits.get_biased_exponent(),
+              uint16_t(x_bits.get_biased_exponent() - 1));
     ASSERT_EQ(result_bits.get_mantissa(),
               (UIntType(1) << MantissaWidth::VALUE) - 1);
 
     result = func(x, T(33.0));
     result_bits = FPBits(result);
-    ASSERT_EQ(result_bits.get_unbiased_exponent(),
-              x_bits.get_unbiased_exponent());
+    ASSERT_EQ(result_bits.get_biased_exponent(), x_bits.get_biased_exponent());
     ASSERT_EQ(result_bits.get_mantissa(), x_bits.get_mantissa() + UIntType(1));
 
     x = -x;
 
     result = func(x, 0);
     result_bits = FPBits(result);
-    ASSERT_EQ(result_bits.get_unbiased_exponent(),
-              uint16_t(x_bits.get_unbiased_exponent() - 1));
+    ASSERT_EQ(result_bits.get_biased_exponent(),
+              uint16_t(x_bits.get_biased_exponent() - 1));
     ASSERT_EQ(result_bits.get_mantissa(),
               (UIntType(1) << MantissaWidth::VALUE) - 1);
 
     result = func(x, T(-33.0));
     result_bits = FPBits(result);
-    ASSERT_EQ(result_bits.get_unbiased_exponent(),
-              x_bits.get_unbiased_exponent());
+    ASSERT_EQ(result_bits.get_biased_exponent(), x_bits.get_biased_exponent());
     ASSERT_EQ(result_bits.get_mantissa(), x_bits.get_mantissa() + UIntType(1));
   }
 };
diff --git a/libc/test/src/math/smoke/NextTowardTest.h b/libc/test/src/math/smoke/NextTowardTest.h
index 4d27592a1142..111d8017e691 100644
--- a/libc/test/src/math/smoke/NextTowardTest.h
+++ b/libc/test/src/math/smoke/NextTowardTest.h
@@ -187,30 +187,28 @@ public:
     result = func(x, 0);
     FPBits x_bits = FPBits(x);
     FPBits result_bits = FPBits(result);
-    ASSERT_EQ(result_bits.get_unbiased_exponent(),
-              uint16_t(x_bits.get_unbiased_exponent() - 1));
+    ASSERT_EQ(result_bits.get_biased_exponent(),
+              uint16_t(x_bits.get_biased_exponent() - 1));
     ASSERT_EQ(result_bits.get_mantissa(),
               (UIntType(1) << MantissaWidth::VALUE) - 1);
 
     result = func(x, 33.0);
     result_bits = FPBits(result);
-    ASSERT_EQ(result_bits.get_unbiased_exponent(),
-              x_bits.get_unbiased_exponent());
+    ASSERT_EQ(result_bits.get_biased_exponent(), x_bits.get_biased_exponent());
     ASSERT_EQ(result_bits.get_mantissa(), x_bits.get_mantissa() + UIntType(1));
 
     x = -x;
 
     result = func(x, 0);
     result_bits = FPBits(result);
-    ASSERT_EQ(result_bits.get_unbiased_exponent(),
-              uint16_t(x_bits.get_unbiased_exponent() - 1));
+    ASSERT_EQ(result_bits.get_biased_exponent(),
+              uint16_t(x_bits.get_biased_exponent() - 1));
     ASSERT_EQ(result_bits.get_mantissa(),
               (UIntType(1) << MantissaWidth::VALUE) - 1);
 
     result = func(x, -33.0);
     result_bits = FPBits(result);
-    ASSERT_EQ(result_bits.get_unbiased_exponent(),
-              x_bits.get_unbiased_exponent());
+    ASSERT_EQ(result_bits.get_biased_exponent(), x_bits.get_biased_exponent());
     ASSERT_EQ(result_bits.get_mantissa(), x_bits.get_mantissa() + UIntType(1));
   }
 };
diff --git a/libc/test/utils/FPUtil/x86_long_double_test.cpp b/libc/test/utils/FPUtil/x86_long_double_test.cpp
index 6ca9b16377c0..cea43c1a6fa4 100644
--- a/libc/test/utils/FPUtil/x86_long_double_test.cpp
+++ b/libc/test/utils/FPUtil/x86_long_double_test.cpp
@@ -22,7 +22,7 @@ TEST(LlvmLibcX86LongDoubleTest, is_nan) {
   constexpr uint32_t COUNT = 100'000;
 
   FPBits bits(0.0l);
-  bits.set_unbiased_exponent(FPBits::MAX_EXPONENT);
+  bits.set_biased_exponent(FPBits::MAX_EXPONENT);
   for (unsigned int i = 0; i < COUNT; ++i) {
     // If exponent has the max value and the implicit bit is 0,
     // then the number is a NaN for all values of mantissa.
@@ -43,7 +43,7 @@ TEST(LlvmLibcX86LongDoubleTest, is_nan) {
     ASSERT_TRUE(bits.is_nan());
   }
 
-  bits.set_unbiased_exponent(1);
+  bits.set_biased_exponent(1);
   bits.set_implicit_bit(0);
   for (unsigned int i = 0; i < COUNT; ++i) {
     // If exponent is non-zero and also not max, and the implicit bit is 0,
@@ -54,7 +54,7 @@ TEST(LlvmLibcX86LongDoubleTest, is_nan) {
     ASSERT_TRUE(bits.is_nan());
   }
 
-  bits.set_unbiased_exponent(1);
+  bits.set_biased_exponent(1);
   bits.set_implicit_bit(1);
   for (unsigned int i = 0; i < COUNT; ++i) {
     // If exponent is non-zero and also not max, and the implicit bit is 1,
@@ -65,7 +65,7 @@ TEST(LlvmLibcX86LongDoubleTest, is_nan) {
     ASSERT_FALSE(bits.is_nan());
   }
 
-  bits.set_unbiased_exponent(0);
+  bits.set_biased_exponent(0);
   bits.set_implicit_bit(1);
   for (unsigned int i = 0; i < COUNT; ++i) {
     // If exponent is zero, then the number is a valid but denormal value.
@@ -75,7 +75,7 @@ TEST(LlvmLibcX86LongDoubleTest, is_nan) {
     ASSERT_FALSE(bits.is_nan());
   }
 
-  bits.set_unbiased_exponent(0);
+  bits.set_biased_exponent(0);
   bits.set_implicit_bit(0);
   for (unsigned int i = 0; i < COUNT; ++i) {
     // If exponent is zero, then the number is a valid but denormal value.
diff --git a/libc/utils/MPFRWrapper/MPFRUtils.cpp b/libc/utils/MPFRWrapper/MPFRUtils.cpp
index e1213e00ff36..e3dffadf4ed9 100644
--- a/libc/utils/MPFRWrapper/MPFRUtils.cpp
+++ b/libc/utils/MPFRWrapper/MPFRUtils.cpp
@@ -458,9 +458,9 @@ public:
     int thisExponent = fputil::FPBits<T>(thisAsT).get_exponent();
     int inputExponent = fputil::FPBits<T>(input).get_exponent();
     // Adjust the exponents for denormal numbers.
-    if (fputil::FPBits<T>(thisAsT).get_unbiased_exponent() == 0)
+    if (fputil::FPBits<T>(thisAsT).get_biased_exponent() == 0)
       ++thisExponent;
-    if (fputil::FPBits<T>(input).get_unbiased_exponent() == 0)
+    if (fputil::FPBits<T>(input).get_biased_exponent() == 0)
       ++inputExponent;
 
     if (thisAsT * input < 0 || thisExponent == inputExponent) {
@@ -483,9 +483,9 @@ public:
     int minExponent = fputil::FPBits<T>(min).get_exponent();
     int maxExponent = fputil::FPBits<T>(max).get_exponent();
     // Adjust the exponents for denormal numbers.
-    if (fputil::FPBits<T>(min).get_unbiased_exponent() == 0)
+    if (fputil::FPBits<T>(min).get_biased_exponent() == 0)
       ++minExponent;
-    if (fputil::FPBits<T>(max).get_unbiased_exponent() == 0)
+    if (fputil::FPBits<T>(max).get_biased_exponent() == 0)
       ++maxExponent;
 
     MPFRNumber minMPFR(min);
-- 
GitLab


From c703e6576575f182a04690a5ce323990e017bae9 Mon Sep 17 00:00:00 2001
From: Guillaume Chatelet <gchatelet@google.com>
Date: Mon, 11 Dec 2023 17:10:42 +0100
Subject: [PATCH 132/349] [libc][NFC] Remove custom leading_zeroes, factor in
 frequent typenames (#74825)

---
 libc/src/__support/str_to_float.h             | 263 ++++++++----------
 libc/test/src/__support/str_to_float_test.cpp |  39 ---
 2 files changed, 112 insertions(+), 190 deletions(-)

diff --git a/libc/src/__support/str_to_float.h b/libc/src/__support/str_to_float.h
index d495c7a073cd..7ec6b9947ad2 100644
--- a/libc/src/__support/str_to_float.h
+++ b/libc/src/__support/str_to_float.h
@@ -9,6 +9,7 @@
 #ifndef LLVM_LIBC_SRC___SUPPORT_STR_TO_FLOAT_H
 #define LLVM_LIBC_SRC___SUPPORT_STR_TO_FLOAT_H
 
+#include "src/__support/CPP/bit.h"
 #include "src/__support/CPP/limits.h"
 #include "src/__support/CPP/optional.h"
 #include "src/__support/FPUtil/FEnvImpl.h"
@@ -37,45 +38,6 @@ template <class T> struct FloatConvertReturn {
   int error = 0;
 };
 
-template <class T> LIBC_INLINE uint32_t leading_zeroes(T inputNumber) {
-  constexpr uint32_t BITS_IN_T = sizeof(T) * 8;
-  if (inputNumber == 0) {
-    return BITS_IN_T;
-  }
-  uint32_t cur_guess = BITS_IN_T / 2;
-  uint32_t range_size = BITS_IN_T / 2;
-  // while either shifting by curGuess does not get rid of all of the bits or
-  // shifting by one less also gets rid of all of the bits then we have not
-  // found the first bit.
-  while (((inputNumber >> cur_guess) > 0) ||
-         ((inputNumber >> (cur_guess - 1)) == 0)) {
-    // Binary search for the first set bit
-    range_size /= 2;
-    if (range_size == 0) {
-      break;
-    }
-    if ((inputNumber >> cur_guess) > 0) {
-      cur_guess += range_size;
-    } else {
-      cur_guess -= range_size;
-    }
-  }
-  if (inputNumber >> cur_guess > 0) {
-    cur_guess++;
-  }
-  return BITS_IN_T - cur_guess;
-}
-
-template <>
-LIBC_INLINE uint32_t leading_zeroes<uint32_t>(uint32_t inputNumber) {
-  return cpp::countl_zero(inputNumber);
-}
-
-template <>
-LIBC_INLINE uint32_t leading_zeroes<uint64_t>(uint64_t inputNumber) {
-  return cpp::countl_zero(inputNumber);
-}
-
 LIBC_INLINE uint64_t low64(const UInt128 &num) {
   return static_cast<uint64_t>(num & 0xffffffffffffffff);
 }
@@ -108,10 +70,11 @@ template <class T>
 LIBC_INLINE cpp::optional<ExpandedFloat<T>>
 eisel_lemire(ExpandedFloat<T> init_num,
              RoundDirection round = RoundDirection::Nearest) {
+  using FPBits = typename fputil::FPBits<T>;
+  using FloatProp = typename FPBits::FloatProp;
+  using UIntType = typename FPBits::UIntType;
 
-  using BitsType = typename fputil::FPBits<T>::UIntType;
-
-  BitsType mantissa = init_num.mantissa;
+  UIntType mantissa = init_num.mantissa;
   int32_t exp10 = init_num.exponent;
 
   constexpr uint32_t BITS_IN_MANTISSA = sizeof(mantissa) * 8;
@@ -128,12 +91,11 @@ eisel_lemire(ExpandedFloat<T> init_num,
   }
 
   // Normalization
-  uint32_t clz = leading_zeroes<BitsType>(mantissa);
+  uint32_t clz = cpp::countl_zero<UIntType>(mantissa);
   mantissa <<= clz;
 
   uint32_t exp2 = static_cast<uint32_t>(exp10_to_exp2(exp10)) +
-                  BITS_IN_MANTISSA + fputil::FloatProperties<T>::EXPONENT_BIAS -
-                  clz;
+                  BITS_IN_MANTISSA + FloatProp::EXPONENT_BIAS - clz;
 
   // Multiplication
   const uint64_t *power_of_ten =
@@ -150,9 +112,7 @@ eisel_lemire(ExpandedFloat<T> init_num,
   // accuracy, and the most significant bit is ignored.) = 9 bits. Similarly,
   // it's 6 bits for floats in this case.
   const uint64_t halfway_constant =
-      (uint64_t(1) << (BITS_IN_MANTISSA -
-                       fputil::FloatProperties<T>::MANTISSA_WIDTH - 3)) -
-      1;
+      (uint64_t(1) << (BITS_IN_MANTISSA - (FloatProp::MANTISSA_WIDTH + 3))) - 1;
   if ((high64(first_approx) & halfway_constant) == halfway_constant &&
       low64(first_approx) + mantissa < mantissa) {
     UInt128 low_bits =
@@ -171,12 +131,11 @@ eisel_lemire(ExpandedFloat<T> init_num,
   }
 
   // Shifting to 54 bits for doubles and 25 bits for floats
-  BitsType msb =
-      static_cast<BitsType>(high64(final_approx) >> (BITS_IN_MANTISSA - 1));
-  BitsType final_mantissa =
-      static_cast<BitsType>(high64(final_approx) >>
-                            (msb + BITS_IN_MANTISSA -
-                             (fputil::FloatProperties<T>::MANTISSA_WIDTH + 3)));
+  UIntType msb =
+      static_cast<UIntType>(high64(final_approx) >> (BITS_IN_MANTISSA - 1));
+  UIntType final_mantissa = static_cast<UIntType>(
+      high64(final_approx) >>
+      (msb + BITS_IN_MANTISSA - (FloatProp::MANTISSA_WIDTH + 3)));
   exp2 -= static_cast<uint32_t>(1 ^ msb); // same as !msb
 
   if (round == RoundDirection::Nearest) {
@@ -202,15 +161,14 @@ eisel_lemire(ExpandedFloat<T> init_num,
 
   // From 54 to 53 bits for doubles and 25 to 24 bits for floats
   final_mantissa >>= 1;
-  if ((final_mantissa >> (fputil::FloatProperties<T>::MANTISSA_WIDTH + 1)) >
-      0) {
+  if ((final_mantissa >> (FloatProp::MANTISSA_WIDTH + 1)) > 0) {
     final_mantissa >>= 1;
     ++exp2;
   }
 
   // The if block is equivalent to (but has fewer branches than):
   //   if exp2 <= 0 || exp2 >= 0x7FF { etc }
-  if (exp2 - 1 >= (1 << fputil::FloatProperties<T>::EXPONENT_WIDTH) - 2) {
+  if (exp2 - 1 >= (1 << FloatProp::EXPONENT_WIDTH) - 2) {
     return cpp::nullopt;
   }
 
@@ -225,9 +183,11 @@ template <>
 LIBC_INLINE cpp::optional<ExpandedFloat<long double>>
 eisel_lemire<long double>(ExpandedFloat<long double> init_num,
                           RoundDirection round) {
-  using BitsType = typename fputil::FPBits<long double>::UIntType;
+  using FPBits = typename fputil::FPBits<long double>;
+  using FloatProp = typename FPBits::FloatProp;
+  using UIntType = typename FPBits::UIntType;
 
-  BitsType mantissa = init_num.mantissa;
+  UIntType mantissa = init_num.mantissa;
   int32_t exp10 = init_num.exponent;
 
   constexpr uint32_t BITS_IN_MANTISSA = sizeof(mantissa) * 8;
@@ -248,12 +208,11 @@ eisel_lemire<long double>(ExpandedFloat<long double> init_num,
   }
 
   // Normalization
-  uint32_t clz = leading_zeroes<BitsType>(mantissa);
+  uint32_t clz = cpp::countl_zero<UIntType>(mantissa);
   mantissa <<= clz;
 
   uint32_t exp2 = static_cast<uint32_t>(exp10_to_exp2(exp10)) +
-                  BITS_IN_MANTISSA +
-                  fputil::FloatProperties<long double>::EXPONENT_BIAS - clz;
+                  BITS_IN_MANTISSA + FloatProp::EXPONENT_BIAS - clz;
 
   // Multiplication
   const uint64_t *power_of_ten =
@@ -290,10 +249,7 @@ eisel_lemire<long double>(ExpandedFloat<long double> init_num,
   // accuracy, and the most significant bit is ignored.) = 61 bits. Similarly,
   // it's 12 bits for 128 bit floats in this case.
   constexpr UInt128 HALFWAY_CONSTANT =
-      (UInt128(1) << (BITS_IN_MANTISSA -
-                      fputil::FloatProperties<long double>::MANTISSA_WIDTH -
-                      3)) -
-      1;
+      (UInt128(1) << (BITS_IN_MANTISSA - (FloatProp::MANTISSA_WIDTH + 3))) - 1;
 
   if ((final_approx_upper & HALFWAY_CONSTANT) == HALFWAY_CONSTANT &&
       final_approx_lower + mantissa < mantissa) {
@@ -303,10 +259,9 @@ eisel_lemire<long double>(ExpandedFloat<long double> init_num,
   // Shifting to 65 bits for 80 bit floats and 113 bits for 128 bit floats
   uint32_t msb =
       static_cast<uint32_t>(final_approx_upper >> (BITS_IN_MANTISSA - 1));
-  BitsType final_mantissa =
+  UIntType final_mantissa =
       final_approx_upper >>
-      (msb + BITS_IN_MANTISSA -
-       (fputil::FloatProperties<long double>::MANTISSA_WIDTH + 3));
+      (msb + BITS_IN_MANTISSA - (FloatProp::MANTISSA_WIDTH + 3));
   exp2 -= static_cast<uint32_t>(1 ^ msb); // same as !msb
 
   if (round == RoundDirection::Nearest) {
@@ -331,16 +286,14 @@ eisel_lemire<long double>(ExpandedFloat<long double> init_num,
   // From 65 to 64 bits for 80 bit floats and 113  to 112 bits for 128 bit
   // floats
   final_mantissa >>= 1;
-  if ((final_mantissa >>
-       (fputil::FloatProperties<long double>::MANTISSA_WIDTH + 1)) > 0) {
+  if ((final_mantissa >> (FloatProp::MANTISSA_WIDTH + 1)) > 0) {
     final_mantissa >>= 1;
     ++exp2;
   }
 
   // The if block is equivalent to (but has fewer branches than):
   //   if exp2 <= 0 || exp2 >= MANTISSA_MAX { etc }
-  if (exp2 - 1 >=
-      (1 << fputil::FloatProperties<long double>::EXPONENT_WIDTH) - 2) {
+  if (exp2 - 1 >= (1 << FloatProp::EXPONENT_WIDTH) - 2) {
     return cpp::nullopt;
   }
 
@@ -368,6 +321,9 @@ template <class T>
 LIBC_INLINE FloatConvertReturn<T>
 simple_decimal_conversion(const char *__restrict numStart,
                           RoundDirection round = RoundDirection::Nearest) {
+  using FPBits = typename fputil::FPBits<T>;
+  using FloatProp = typename FPBits::FloatProp;
+  using UIntType = typename FPBits::UIntType;
 
   int32_t exp2 = 0;
   HighPrecisionDecimal hpd = HighPrecisionDecimal(numStart);
@@ -383,16 +339,16 @@ simple_decimal_conversion(const char *__restrict numStart,
   // float, return inf.
   if (hpd.get_decimal_point() > 0 &&
       exp10_to_exp2(hpd.get_decimal_point() - 1) >
-          static_cast<int64_t>(fputil::FloatProperties<T>::EXPONENT_BIAS)) {
-    output.num = {0, fputil::FPBits<T>::MAX_EXPONENT};
+          static_cast<int64_t>(FloatProp::EXPONENT_BIAS)) {
+    output.num = {0, FPBits::MAX_EXPONENT};
     output.error = ERANGE;
     return output;
   }
   // If the exponent is too small even for a subnormal, return 0.
   if (hpd.get_decimal_point() < 0 &&
       exp10_to_exp2(-hpd.get_decimal_point()) >
-          static_cast<int64_t>(fputil::FloatProperties<T>::EXPONENT_BIAS +
-                               fputil::FloatProperties<T>::MANTISSA_WIDTH)) {
+          static_cast<int64_t>(FloatProp::EXPONENT_BIAS +
+                               FloatProp::MANTISSA_WIDTH)) {
     output.num = {0, 0};
     output.error = ERANGE;
     return output;
@@ -431,19 +387,18 @@ simple_decimal_conversion(const char *__restrict numStart,
   hpd.shift(1);
 
   // Get the biased exponent
-  exp2 += fputil::FloatProperties<T>::EXPONENT_BIAS;
+  exp2 += FloatProp::EXPONENT_BIAS;
 
   // Handle the exponent being too large (and return inf).
-  if (exp2 >= fputil::FPBits<T>::MAX_EXPONENT) {
-    output.num = {0, fputil::FPBits<T>::MAX_EXPONENT};
+  if (exp2 >= FPBits::MAX_EXPONENT) {
+    output.num = {0, FPBits::MAX_EXPONENT};
     output.error = ERANGE;
     return output;
   }
 
   // Shift left to fill the mantissa
-  hpd.shift(fputil::FloatProperties<T>::MANTISSA_WIDTH);
-  typename fputil::FPBits<T>::UIntType final_mantissa =
-      hpd.round_to_integer_type<typename fputil::FPBits<T>::UIntType>();
+  hpd.shift(FloatProp::MANTISSA_WIDTH);
+  UIntType final_mantissa = hpd.round_to_integer_type<UIntType>();
 
   // Handle subnormals
   if (exp2 <= 0) {
@@ -455,25 +410,23 @@ simple_decimal_conversion(const char *__restrict numStart,
     // Shift right one more time to compensate for the left shift to get it
     // between 1 and 2.
     hpd.shift(-1);
-    final_mantissa =
-        hpd.round_to_integer_type<typename fputil::FPBits<T>::UIntType>(round);
+    final_mantissa = hpd.round_to_integer_type<UIntType>(round);
 
     // Check if by shifting right we've caused this to round to a normal number.
-    if ((final_mantissa >> fputil::FloatProperties<T>::MANTISSA_WIDTH) != 0) {
+    if ((final_mantissa >> FloatProp::MANTISSA_WIDTH) != 0) {
       ++exp2;
     }
   }
 
   // Check if rounding added a bit, and shift down if that's the case.
-  if (final_mantissa == typename fputil::FPBits<T>::UIntType(2)
-                            << fputil::FloatProperties<T>::MANTISSA_WIDTH) {
+  if (final_mantissa == UIntType(2) << FloatProp::MANTISSA_WIDTH) {
     final_mantissa >>= 1;
     ++exp2;
 
     // Check if this rounding causes exp2 to go out of range and make the result
     // INF. If this is the case, then finalMantissa and exp2 are already the
     // correct values for an INF result.
-    if (exp2 >= fputil::FPBits<T>::MAX_EXPONENT) {
+    if (exp2 >= FPBits::MAX_EXPONENT) {
       output.error = ERANGE;
     }
   }
@@ -563,18 +516,20 @@ template <class T>
 LIBC_INLINE cpp::optional<ExpandedFloat<T>>
 clinger_fast_path(ExpandedFloat<T> init_num,
                   RoundDirection round = RoundDirection::Nearest) {
+  using FPBits = typename fputil::FPBits<T>;
+  using FloatProp = typename FPBits::FloatProp;
+  using UIntType = typename FPBits::UIntType;
 
-  typename fputil::FPBits<T>::UIntType mantissa = init_num.mantissa;
+  UIntType mantissa = init_num.mantissa;
   int32_t exp10 = init_num.exponent;
 
-  if (mantissa >> fputil::FloatProperties<T>::MANTISSA_WIDTH > 0) {
+  if ((mantissa >> FloatProp::MANTISSA_WIDTH) > 0) {
     return cpp::nullopt;
   }
 
-  fputil::FPBits<T> result;
+  FPBits result;
   T float_mantissa;
-  if constexpr (cpp::is_same_v<typename fputil::FPBits<T>::UIntType,
-                               cpp::UInt<128>>) {
+  if constexpr (cpp::is_same_v<UIntType, cpp::UInt<128>>) {
     float_mantissa = static_cast<T>(fputil::DyadicFloat<128>(
         false, 0,
         fputil::DyadicFloat<128>::MantissaType(
@@ -584,7 +539,7 @@ clinger_fast_path(ExpandedFloat<T> init_num,
   }
 
   if (exp10 == 0) {
-    result = fputil::FPBits<T>(float_mantissa);
+    result = FPBits(float_mantissa);
   }
   if (exp10 > 0) {
     if (exp10 > ClingerConsts<T>::EXACT_POWERS_OF_TEN +
@@ -600,14 +555,14 @@ clinger_fast_path(ExpandedFloat<T> init_num,
     if (float_mantissa > ClingerConsts<T>::MAX_EXACT_INT) {
       return cpp::nullopt;
     }
-    result = fputil::FPBits<T>(float_mantissa *
-                               ClingerConsts<T>::POWERS_OF_TEN_ARRAY[exp10]);
+    result =
+        FPBits(float_mantissa * ClingerConsts<T>::POWERS_OF_TEN_ARRAY[exp10]);
   } else if (exp10 < 0) {
     if (-exp10 > ClingerConsts<T>::EXACT_POWERS_OF_TEN) {
       return cpp::nullopt;
     }
-    result = fputil::FPBits<T>(float_mantissa /
-                               ClingerConsts<T>::POWERS_OF_TEN_ARRAY[-exp10]);
+    result =
+        FPBits(float_mantissa / ClingerConsts<T>::POWERS_OF_TEN_ARRAY[-exp10]);
   }
 
   // If the rounding mode is not nearest, then the sign of the number may affect
@@ -615,15 +570,15 @@ clinger_fast_path(ExpandedFloat<T> init_num,
   // calculation is redone with a negative result, and the rounding mode is used
   // to select the correct result.
   if (round != RoundDirection::Nearest) {
-    fputil::FPBits<T> negative_result;
+    FPBits negative_result;
     // I'm 99% sure this will break under fast math optimizations.
-    negative_result = fputil::FPBits<T>(
-        (-float_mantissa) * ClingerConsts<T>::POWERS_OF_TEN_ARRAY[exp10]);
+    negative_result = FPBits((-float_mantissa) *
+                             ClingerConsts<T>::POWERS_OF_TEN_ARRAY[exp10]);
 
     // If the results are equal, then we don't need to use the rounding mode.
     if (T(result) != -T(negative_result)) {
-      fputil::FPBits<T> lower_result;
-      fputil::FPBits<T> higher_result;
+      FPBits lower_result;
+      FPBits higher_result;
 
       if (T(result) < -T(negative_result)) {
         lower_result = result;
@@ -691,8 +646,10 @@ template <class T>
 LIBC_INLINE FloatConvertReturn<T>
 decimal_exp_to_float(ExpandedFloat<T> init_num, const char *__restrict numStart,
                      bool truncated, RoundDirection round) {
+  using FPBits = typename fputil::FPBits<T>;
+  using UIntType = typename FPBits::UIntType;
 
-  typename fputil::FPBits<T>::UIntType mantissa = init_num.mantissa;
+  UIntType mantissa = init_num.mantissa;
   int32_t exp10 = init_num.exponent;
 
   FloatConvertReturn<T> output;
@@ -702,7 +659,7 @@ decimal_exp_to_float(ExpandedFloat<T> init_num, const char *__restrict numStart,
   // float, return inf. These bounds are relatively loose, but are mostly
   // serving as a first pass. Some close numbers getting through is okay.
   if (exp10 > get_upper_bound<T>()) {
-    output.num = {0, fputil::FPBits<T>::MAX_EXPONENT};
+    output.num = {0, FPBits::MAX_EXPONENT};
     output.error = ERANGE;
     return output;
   }
@@ -766,40 +723,39 @@ template <class T>
 LIBC_INLINE FloatConvertReturn<T> binary_exp_to_float(ExpandedFloat<T> init_num,
                                                       bool truncated,
                                                       RoundDirection round) {
-  using BitsType = typename fputil::FPBits<T>::UIntType;
+  using FPBits = typename fputil::FPBits<T>;
+  using FloatProp = typename FPBits::FloatProp;
+  using UIntType = typename FPBits::UIntType;
 
-  BitsType mantissa = init_num.mantissa;
+  UIntType mantissa = init_num.mantissa;
   int32_t exp2 = init_num.exponent;
 
   FloatConvertReturn<T> output;
 
   // This is the number of leading zeroes a properly normalized float of type T
   // should have.
-  constexpr int32_t NUMBITS = sizeof(BitsType) * 8;
-  constexpr int32_t INF_EXP =
-      (1 << fputil::FloatProperties<T>::EXPONENT_WIDTH) - 1;
+  constexpr int32_t NUMBITS = sizeof(UIntType) * 8;
+  constexpr int32_t INF_EXP = (1 << FloatProp::EXPONENT_WIDTH) - 1;
 
-  // Normalization step 1: Bring the leading bit to the highest bit of BitsType.
-  uint32_t amount_to_shift_left = leading_zeroes<BitsType>(mantissa);
+  // Normalization step 1: Bring the leading bit to the highest bit of UIntType.
+  uint32_t amount_to_shift_left = cpp::countl_zero<UIntType>(mantissa);
   mantissa <<= amount_to_shift_left;
 
-  // Keep exp2 representing the exponent of the lowest bit of BitsType.
+  // Keep exp2 representing the exponent of the lowest bit of UIntType.
   exp2 -= amount_to_shift_left;
 
   // biasedExponent represents the biased exponent of the most significant bit.
-  int32_t biased_exponent =
-      exp2 + NUMBITS + fputil::FPBits<T>::EXPONENT_BIAS - 1;
+  int32_t biased_exponent = exp2 + NUMBITS + FPBits::EXPONENT_BIAS - 1;
 
   // Handle numbers that're too large and get squashed to inf
   if (biased_exponent >= INF_EXP) {
     // This indicates an overflow, so we make the result INF and set errno.
-    output.num = {0, (1 << fputil::FloatProperties<T>::EXPONENT_WIDTH) - 1};
+    output.num = {0, (1 << FloatProp::EXPONENT_WIDTH) - 1};
     output.error = ERANGE;
     return output;
   }
 
-  uint32_t amount_to_shift_right =
-      NUMBITS - fputil::FloatProperties<T>::MANTISSA_WIDTH - 1;
+  uint32_t amount_to_shift_right = NUMBITS - FloatProp::MANTISSA_WIDTH - 1;
 
   // Handle subnormals.
   if (biased_exponent <= 0) {
@@ -814,19 +770,19 @@ LIBC_INLINE FloatConvertReturn<T> binary_exp_to_float(ExpandedFloat<T> init_num,
     }
   }
 
-  BitsType round_bit_mask = BitsType(1) << (amount_to_shift_right - 1);
-  BitsType sticky_mask = round_bit_mask - 1;
+  UIntType round_bit_mask = UIntType(1) << (amount_to_shift_right - 1);
+  UIntType sticky_mask = round_bit_mask - 1;
   bool round_bit = static_cast<bool>(mantissa & round_bit_mask);
   bool sticky_bit = static_cast<bool>(mantissa & sticky_mask) || truncated;
 
   if (amount_to_shift_right < NUMBITS) {
     // Shift the mantissa and clear the implicit bit.
     mantissa >>= amount_to_shift_right;
-    mantissa &= fputil::FloatProperties<T>::MANTISSA_MASK;
+    mantissa &= FloatProp::MANTISSA_MASK;
   } else {
     mantissa = 0;
   }
-  bool least_significant_bit = static_cast<bool>(mantissa & BitsType(1));
+  bool least_significant_bit = static_cast<bool>(mantissa & UIntType(1));
 
   // TODO: check that this rounding behavior is correct.
 
@@ -845,7 +801,7 @@ LIBC_INLINE FloatConvertReturn<T> binary_exp_to_float(ExpandedFloat<T> init_num,
     }
   }
 
-  if (mantissa > fputil::FloatProperties<T>::MANTISSA_MASK) {
+  if (mantissa > FloatProp::MANTISSA_MASK) {
     // Rounding causes the exponent to increase.
     ++biased_exponent;
 
@@ -858,8 +814,7 @@ LIBC_INLINE FloatConvertReturn<T> binary_exp_to_float(ExpandedFloat<T> init_num,
     output.error = ERANGE;
   }
 
-  output.num = {mantissa & fputil::FloatProperties<T>::MANTISSA_MASK,
-                biased_exponent};
+  output.num = {mantissa & FloatProp::MANTISSA_MASK, biased_exponent};
   return output;
 }
 
@@ -887,14 +842,16 @@ template <class T>
 LIBC_INLINE StrToNumResult<ExpandedFloat<T>>
 decimal_string_to_float(const char *__restrict src, const char DECIMAL_POINT,
                         RoundDirection round) {
-  using BitsType = typename fputil::FPBits<T>::UIntType;
+  using FPBits = typename fputil::FPBits<T>;
+  using UIntType = typename FPBits::UIntType;
+
   constexpr uint32_t BASE = 10;
   constexpr char EXPONENT_MARKER = 'e';
 
   bool truncated = false;
   bool seen_digit = false;
   bool after_decimal = false;
-  BitsType mantissa = 0;
+  UIntType mantissa = 0;
   int32_t exponent = 0;
 
   size_t index = 0;
@@ -905,8 +862,8 @@ decimal_string_to_float(const char *__restrict src, const char DECIMAL_POINT,
   // the format mantissa * (base ^ exponent)
 
   // The loop fills the mantissa with as many digits as it can hold
-  const BitsType bitstype_max_div_by_base =
-      cpp::numeric_limits<BitsType>::max() / BASE;
+  const UIntType bitstype_max_div_by_base =
+      cpp::numeric_limits<UIntType>::max() / BASE;
   while (true) {
     if (isdigit(src[index])) {
       uint32_t digit = src[index] - '0';
@@ -962,10 +919,10 @@ decimal_string_to_float(const char *__restrict src, const char DECIMAL_POINT,
 
       // If the result is in the valid range, then we use it. The valid range is
       // also within the int32 range, so this prevents overflow issues.
-      if (temp_exponent > fputil::FPBits<T>::MAX_EXPONENT) {
-        exponent = fputil::FPBits<T>::MAX_EXPONENT;
-      } else if (temp_exponent < -fputil::FPBits<T>::MAX_EXPONENT) {
-        exponent = -fputil::FPBits<T>::MAX_EXPONENT;
+      if (temp_exponent > FPBits::MAX_EXPONENT) {
+        exponent = FPBits::MAX_EXPONENT;
+      } else if (temp_exponent < -FPBits::MAX_EXPONENT) {
+        exponent = -FPBits::MAX_EXPONENT;
       } else {
         exponent = static_cast<int32_t>(temp_exponent);
       }
@@ -994,14 +951,16 @@ template <class T>
 LIBC_INLINE StrToNumResult<ExpandedFloat<T>>
 hexadecimal_string_to_float(const char *__restrict src,
                             const char DECIMAL_POINT, RoundDirection round) {
-  using BitsType = typename fputil::FPBits<T>::UIntType;
+  using FPBits = typename fputil::FPBits<T>;
+  using UIntType = typename FPBits::UIntType;
+
   constexpr uint32_t BASE = 16;
   constexpr char EXPONENT_MARKER = 'p';
 
   bool truncated = false;
   bool seen_digit = false;
   bool after_decimal = false;
-  BitsType mantissa = 0;
+  UIntType mantissa = 0;
   int32_t exponent = 0;
 
   size_t index = 0;
@@ -1012,8 +971,8 @@ hexadecimal_string_to_float(const char *__restrict src,
   // the format mantissa * (base ^ exponent)
 
   // The loop fills the mantissa with as many digits as it can hold
-  const BitsType bitstype_max_div_by_base =
-      cpp::numeric_limits<BitsType>::max() / BASE;
+  const UIntType bitstype_max_div_by_base =
+      cpp::numeric_limits<UIntType>::max() / BASE;
   while (true) {
     if (isalnum(src[index])) {
       uint32_t digit = b36_char_to_int(src[index]);
@@ -1074,10 +1033,10 @@ hexadecimal_string_to_float(const char *__restrict src,
 
       // If the result is in the valid range, then we use it. The valid range is
       // also within the int32 range, so this prevents overflow issues.
-      if (temp_exponent > fputil::FPBits<T>::MAX_EXPONENT) {
-        exponent = fputil::FPBits<T>::MAX_EXPONENT;
-      } else if (temp_exponent < -fputil::FPBits<T>::MAX_EXPONENT) {
-        exponent = -fputil::FPBits<T>::MAX_EXPONENT;
+      if (temp_exponent > FPBits::MAX_EXPONENT) {
+        exponent = FPBits::MAX_EXPONENT;
+      } else if (temp_exponent < -FPBits::MAX_EXPONENT) {
+        exponent = -FPBits::MAX_EXPONENT;
       } else {
         exponent = static_cast<int32_t>(temp_exponent);
       }
@@ -1099,8 +1058,10 @@ hexadecimal_string_to_float(const char *__restrict src,
 // is used as the backend for all of the string to float functions.
 template <class T>
 LIBC_INLINE StrToNumResult<T> strtofloatingpoint(const char *__restrict src) {
-  using BitsType = typename fputil::FPBits<T>::UIntType;
-  fputil::FPBits<T> result = fputil::FPBits<T>();
+  using FPBits = typename fputil::FPBits<T>;
+  using UIntType = typename FPBits::UIntType;
+
+  FPBits result = FPBits();
   bool seen_digit = false;
   char sign = '+';
 
@@ -1172,7 +1133,7 @@ LIBC_INLINE StrToNumResult<T> strtofloatingpoint(const char *__restrict src) {
         tolower(src[index + 2]) == nan_string[2]) {
       seen_digit = true;
       index += 3;
-      BitsType nan_mantissa = 0;
+      UIntType nan_mantissa = 0;
       // this handles the case of `NaN(n-character-sequence)`, where the
       // n-character-sequence is made of 0 or more letters and numbers in any
       // order.
@@ -1186,7 +1147,7 @@ LIBC_INLINE StrToNumResult<T> strtofloatingpoint(const char *__restrict src) {
         if (src[index] == ')') {
           ++index;
           if (isdigit(src[left_paren + 1])) {
-            // This is to prevent errors when BitsType is larger than 64 bits,
+            // This is to prevent errors when UIntType is larger than 64 bits,
             // since strtointeger only supports up to 64 bits. This is actually
             // more than is required by the specification, which says for the
             // input type "NAN(n-char-sequence)" that "the meaning of
@@ -1197,7 +1158,7 @@ LIBC_INLINE StrToNumResult<T> strtofloatingpoint(const char *__restrict src) {
             if (strtoint_result.has_error()) {
               error = strtoint_result.error;
             }
-            nan_mantissa = static_cast<BitsType>(strtoint_result.value);
+            nan_mantissa = static_cast<UIntType>(strtoint_result.value);
             if (src[left_paren + 1 + strtoint_result.parsed_len] != ')')
               nan_mantissa = 0;
           }
@@ -1207,11 +1168,11 @@ LIBC_INLINE StrToNumResult<T> strtofloatingpoint(const char *__restrict src) {
       }
       nan_mantissa |= fputil::FloatProperties<T>::QUIET_NAN_MASK;
       if (result.get_sign()) {
-        result = fputil::FPBits<T>(result.build_quiet_nan(nan_mantissa));
+        result = FPBits(result.build_quiet_nan(nan_mantissa));
         result.set_sign(true);
       } else {
         result.set_sign(false);
-        result = fputil::FPBits<T>(result.build_quiet_nan(nan_mantissa));
+        result = FPBits(result.build_quiet_nan(nan_mantissa));
       }
     }
   } else if (tolower(src[index]) == 'i') { // INF
@@ -1219,9 +1180,9 @@ LIBC_INLINE StrToNumResult<T> strtofloatingpoint(const char *__restrict src) {
         tolower(src[index + 2]) == inf_string[2]) {
       seen_digit = true;
       if (result.get_sign())
-        result = fputil::FPBits<T>(result.neg_inf());
+        result = FPBits(result.neg_inf());
       else
-        result = fputil::FPBits<T>(result.inf());
+        result = FPBits(result.inf());
       if (tolower(src[index + 3]) == inf_string[3] &&
           tolower(src[index + 4]) == inf_string[4] &&
           tolower(src[index + 5]) == inf_string[5] &&
diff --git a/libc/test/src/__support/str_to_float_test.cpp b/libc/test/src/__support/str_to_float_test.cpp
index f9d12d95a50b..35f7318fb9c7 100644
--- a/libc/test/src/__support/str_to_float_test.cpp
+++ b/libc/test/src/__support/str_to_float_test.cpp
@@ -93,45 +93,6 @@ public:
   }
 };
 
-TEST(LlvmLibcStrToFloatTest, LeadingZeroes) {
-  uint64_t test_num64 = 1;
-  uint32_t num_of_zeroes = 63;
-  EXPECT_EQ(LIBC_NAMESPACE::internal::leading_zeroes<uint64_t>(0), 64u);
-  for (; num_of_zeroes < 64; test_num64 <<= 1, num_of_zeroes--) {
-    EXPECT_EQ(LIBC_NAMESPACE::internal::leading_zeroes<uint64_t>(test_num64),
-              num_of_zeroes);
-  }
-
-  test_num64 = 3;
-  num_of_zeroes = 62;
-  for (; num_of_zeroes > 63; test_num64 <<= 1, num_of_zeroes--) {
-    EXPECT_EQ(LIBC_NAMESPACE::internal::leading_zeroes<uint64_t>(test_num64),
-              num_of_zeroes);
-  }
-
-  EXPECT_EQ(
-      LIBC_NAMESPACE::internal::leading_zeroes<uint64_t>(0xffffffffffffffff),
-      0u);
-
-  test_num64 = 1;
-  num_of_zeroes = 63;
-  for (; num_of_zeroes > 63;
-       test_num64 = (test_num64 << 1) + 1, num_of_zeroes--) {
-    EXPECT_EQ(LIBC_NAMESPACE::internal::leading_zeroes<uint64_t>(test_num64),
-              num_of_zeroes);
-  }
-
-  uint64_t test_num32 = 1;
-  num_of_zeroes = 31;
-  EXPECT_EQ(LIBC_NAMESPACE::internal::leading_zeroes<uint32_t>(0), 32u);
-  for (; num_of_zeroes < 32; test_num32 <<= 1, num_of_zeroes--) {
-    EXPECT_EQ(LIBC_NAMESPACE::internal::leading_zeroes<uint32_t>(test_num32),
-              num_of_zeroes);
-  }
-
-  EXPECT_EQ(LIBC_NAMESPACE::internal::leading_zeroes<uint32_t>(0xffffffff), 0u);
-}
-
 TEST_F(LlvmLibcStrToFloatTest, ClingerFastPathFloat64Simple) {
   clinger_fast_path_test<double>(123, 0, 0xEC00000000000, 1029);
   clinger_fast_path_test<double>(1234567890123456, 1, 0x5ee2a2eb5a5c0, 1076);
-- 
GitLab


From 7e761ba8546e5553d7e74882c7df819419f3acc4 Mon Sep 17 00:00:00 2001
From: Guillaume Chatelet <gchatelet@google.com>
Date: Mon, 11 Dec 2023 17:14:20 +0100
Subject: [PATCH 133/349] [libc][NFC] Simplify FloatProperties implementation
 (#74481)

Factor in common properties of `FloatProperties`.

This is a first patch of a series to simplify `FloatProperties` and
`FPBits` implementations.
---
 libc/src/__support/FPUtil/FloatProperties.h | 131 ++++++++++++++------
 1 file changed, 94 insertions(+), 37 deletions(-)

diff --git a/libc/src/__support/FPUtil/FloatProperties.h b/libc/src/__support/FPUtil/FloatProperties.h
index 59e261e1047f..4288cd719a1d 100644
--- a/libc/src/__support/FPUtil/FloatProperties.h
+++ b/libc/src/__support/FPUtil/FloatProperties.h
@@ -10,7 +10,7 @@
 #define LLVM_LIBC_SRC___SUPPORT_FPUTIL_FLOATPROPERTIES_H
 
 #include "src/__support/UInt128.h"
-#include "src/__support/macros/attributes.h"       // LIBC_INLINE
+#include "src/__support/macros/attributes.h" // LIBC_INLINE, LIBC_INLINE_VAR
 #include "src/__support/macros/properties/float.h" // LIBC_COMPILER_HAS_FLOAT128
 
 #include <stdint.h>
@@ -27,22 +27,98 @@ enum class FPType {
   X86_Binary80,
 };
 
-template <FPType> struct FPProperties {};
-template <> struct FPProperties<FPType::IEEE754_Binary32> {
-  typedef uint32_t BitsType;
+// For now 'FPEncoding', 'FPBaseProperties' and 'FPCommonProperties' are
+// implementation details.
+namespace internal {
+
+// The type of encoding for supported floating point types.
+enum class FPEncoding {
+  IEEE754,
+  X86_ExtendedPrecision,
+};
+
+template <FPType> struct FPBaseProperties {};
+
+template <> struct FPBaseProperties<FPType::IEEE754_Binary16> {
+  using UIntType = uint16_t;
+  LIBC_INLINE_VAR static constexpr int TOTAL_BITS = 16;
+  LIBC_INLINE_VAR static constexpr int SIG_BITS = 10;
+  LIBC_INLINE_VAR static constexpr int EXP_BITS = 5;
+  LIBC_INLINE_VAR static constexpr auto ENCODING = FPEncoding::IEEE754;
+};
+
+template <> struct FPBaseProperties<FPType::IEEE754_Binary32> {
+  using UIntType = uint32_t;
+  LIBC_INLINE_VAR static constexpr int TOTAL_BITS = 32;
+  LIBC_INLINE_VAR static constexpr int SIG_BITS = 23;
+  LIBC_INLINE_VAR static constexpr int EXP_BITS = 8;
+  LIBC_INLINE_VAR static constexpr auto ENCODING = FPEncoding::IEEE754;
+};
+
+template <> struct FPBaseProperties<FPType::IEEE754_Binary64> {
+  using UIntType = uint64_t;
+  LIBC_INLINE_VAR static constexpr int TOTAL_BITS = 64;
+  LIBC_INLINE_VAR static constexpr int SIG_BITS = 52;
+  LIBC_INLINE_VAR static constexpr int EXP_BITS = 11;
+  LIBC_INLINE_VAR static constexpr auto ENCODING = FPEncoding::IEEE754;
+};
+
+template <> struct FPBaseProperties<FPType::IEEE754_Binary128> {
+  using UIntType = UInt128;
+  LIBC_INLINE_VAR static constexpr int TOTAL_BITS = 128;
+  LIBC_INLINE_VAR static constexpr int SIG_BITS = 112;
+  LIBC_INLINE_VAR static constexpr int EXP_BITS = 15;
+  LIBC_INLINE_VAR static constexpr auto ENCODING = FPEncoding::IEEE754;
+};
+
+template <> struct FPBaseProperties<FPType::X86_Binary80> {
+  using UIntType = UInt128;
+  LIBC_INLINE_VAR static constexpr int TOTAL_BITS = 80;
+  LIBC_INLINE_VAR static constexpr int SIG_BITS = 64;
+  LIBC_INLINE_VAR static constexpr int EXP_BITS = 15;
+  LIBC_INLINE_VAR static constexpr auto ENCODING =
+      FPEncoding::X86_ExtendedPrecision;
+};
+
+// Derives more properties from 'FPBaseProperties' above.
+// This class serves as a halfway point between 'FPBaseProperties' and
+// 'FPProperties' below.
+template <FPType fp_type>
+struct FPCommonProperties : private FPBaseProperties<fp_type> {
+  using UP = FPBaseProperties<fp_type>;
+  using BitsType = typename UP::UIntType;
+
+  LIBC_INLINE_VAR static constexpr uint32_t BIT_WIDTH = UP::TOTAL_BITS;
+  LIBC_INLINE_VAR static constexpr uint32_t MANTISSA_WIDTH = UP::SIG_BITS;
+  LIBC_INLINE_VAR static constexpr uint32_t EXPONENT_WIDTH = UP::EXP_BITS;
+
+  // The exponent bias. Always positive.
+  LIBC_INLINE_VAR static constexpr uint32_t EXPONENT_BIAS =
+      (1U << (UP::EXP_BITS - 1U)) - 1U;
+  static_assert(EXPONENT_BIAS > 0);
+};
+
+} // namespace internal
 
-  static constexpr uint32_t BIT_WIDTH = sizeof(BitsType) * 8;
+template <FPType> struct FPProperties {};
 
-  static constexpr uint32_t MANTISSA_WIDTH = 23;
+// ----------------
+// Work In Progress
+// ----------------
+// The 'FPProperties' template specializations below are being slowly replaced
+// with properties from 'FPCommonProperties' above. Once specializations are
+// empty, 'FPProperties' declaration can be fully replace with
+// 'FPCommonProperties' implementation.
+
+template <>
+struct FPProperties<FPType::IEEE754_Binary32>
+    : public internal::FPCommonProperties<FPType::IEEE754_Binary32> {
   // The mantissa precision includes the implicit bit.
   static constexpr uint32_t MANTISSA_PRECISION = MANTISSA_WIDTH + 1;
-  static constexpr uint32_t EXPONENT_WIDTH = 8;
   static constexpr BitsType MANTISSA_MASK = (BitsType(1) << MANTISSA_WIDTH) - 1;
   static constexpr BitsType SIGN_MASK = BitsType(1)
                                         << (EXPONENT_WIDTH + MANTISSA_WIDTH);
   static constexpr BitsType EXPONENT_MASK = ~(SIGN_MASK | MANTISSA_MASK);
-  static constexpr uint32_t EXPONENT_BIAS = 127;
-
   static constexpr BitsType EXP_MANT_MASK = MANTISSA_MASK + EXPONENT_MASK;
   static_assert(EXP_MANT_MASK == ~SIGN_MASK,
                 "Exponent and mantissa masks are not as expected.");
@@ -53,20 +129,14 @@ template <> struct FPProperties<FPType::IEEE754_Binary32> {
   static constexpr BitsType QUIET_NAN_MASK = 0x00400000U;
 };
 
-template <> struct FPProperties<FPType::IEEE754_Binary64> {
-  typedef uint64_t BitsType;
-
-  static constexpr uint32_t BIT_WIDTH = sizeof(BitsType) * 8;
-
-  static constexpr uint32_t MANTISSA_WIDTH = 52;
+template <>
+struct FPProperties<FPType::IEEE754_Binary64>
+    : public internal::FPCommonProperties<FPType::IEEE754_Binary64> {
   static constexpr uint32_t MANTISSA_PRECISION = MANTISSA_WIDTH + 1;
-  static constexpr uint32_t EXPONENT_WIDTH = 11;
   static constexpr BitsType MANTISSA_MASK = (BitsType(1) << MANTISSA_WIDTH) - 1;
   static constexpr BitsType SIGN_MASK = BitsType(1)
                                         << (EXPONENT_WIDTH + MANTISSA_WIDTH);
   static constexpr BitsType EXPONENT_MASK = ~(SIGN_MASK | MANTISSA_MASK);
-  static constexpr uint32_t EXPONENT_BIAS = 1023;
-
   static constexpr BitsType EXP_MANT_MASK = MANTISSA_MASK + EXPONENT_MASK;
   static_assert(EXP_MANT_MASK == ~SIGN_MASK,
                 "Exponent and mantissa masks are not as expected.");
@@ -79,27 +149,20 @@ template <> struct FPProperties<FPType::IEEE754_Binary64> {
 
 // Properties for numbers represented in 80 bits long double on non-Windows x86
 // platforms.
-template <> struct FPProperties<FPType::X86_Binary80> {
-  typedef UInt128 BitsType;
-
-  static constexpr uint32_t BIT_WIDTH = (sizeof(BitsType) * 8) - 48;
+template <>
+struct FPProperties<FPType::X86_Binary80>
+    : public internal::FPCommonProperties<FPType::X86_Binary80> {
   static constexpr BitsType FULL_WIDTH_MASK = ((BitsType(1) << BIT_WIDTH) - 1);
-
   static constexpr uint32_t MANTISSA_WIDTH = 63;
   static constexpr uint32_t MANTISSA_PRECISION = MANTISSA_WIDTH + 1;
-  static constexpr uint32_t EXPONENT_WIDTH = 15;
   static constexpr BitsType MANTISSA_MASK = (BitsType(1) << MANTISSA_WIDTH) - 1;
-
   // The x86 80 bit float represents the leading digit of the mantissa
   // explicitly. This is the mask for that bit.
   static constexpr BitsType EXPLICIT_BIT_MASK = (BitsType(1) << MANTISSA_WIDTH);
-
   static constexpr BitsType SIGN_MASK =
       BitsType(1) << (EXPONENT_WIDTH + MANTISSA_WIDTH + 1);
   static constexpr BitsType EXPONENT_MASK =
       ((BitsType(1) << EXPONENT_WIDTH) - 1) << (MANTISSA_WIDTH + 1);
-  static constexpr uint32_t EXPONENT_BIAS = 16383;
-
   static constexpr BitsType EXP_MANT_MASK =
       MANTISSA_MASK | EXPLICIT_BIT_MASK | EXPONENT_MASK;
   static_assert(EXP_MANT_MASK == (~SIGN_MASK & FULL_WIDTH_MASK),
@@ -114,20 +177,14 @@ template <> struct FPProperties<FPType::X86_Binary80> {
 
 // Properties for numbers represented in 128 bits long double on non x86
 // platform.
-template <> struct FPProperties<FPType::IEEE754_Binary128> {
-  typedef UInt128 BitsType;
-
-  static constexpr uint32_t BIT_WIDTH = sizeof(BitsType) << 3;
-
-  static constexpr uint32_t MANTISSA_WIDTH = 112;
+template <>
+struct FPProperties<FPType::IEEE754_Binary128>
+    : public internal::FPCommonProperties<FPType::IEEE754_Binary128> {
   static constexpr uint32_t MANTISSA_PRECISION = MANTISSA_WIDTH + 1;
-  static constexpr uint32_t EXPONENT_WIDTH = 15;
   static constexpr BitsType MANTISSA_MASK = (BitsType(1) << MANTISSA_WIDTH) - 1;
   static constexpr BitsType SIGN_MASK = BitsType(1)
                                         << (EXPONENT_WIDTH + MANTISSA_WIDTH);
   static constexpr BitsType EXPONENT_MASK = ~(SIGN_MASK | MANTISSA_MASK);
-  static constexpr uint32_t EXPONENT_BIAS = 16383;
-
   static constexpr BitsType EXP_MANT_MASK = MANTISSA_MASK | EXPONENT_MASK;
   static_assert(EXP_MANT_MASK == ~SIGN_MASK,
                 "Exponent and mantissa masks are not as expected.");
-- 
GitLab


From a7d8d11a144fb09afb3fcbef62fe302ae2fef897 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Mon, 11 Dec 2023 15:59:46 +0000
Subject: [PATCH 134/349] [X86] combineConcatVectorOps - constant fold vector
 load concatenation directly into a new load.

Create a new constant pool entry directly instead of going via a BUILD_VECTOR node, which makes constant pool reuse more difficult.

Helps with some regressions in #73509
---
 llvm/lib/Target/X86/X86ISelLowering.cpp       |  68 ++-
 .../test/CodeGen/X86/combine-concatvectors.ll |   3 +-
 .../vector-interleaved-store-i16-stride-3.ll  |   3 +-
 .../vector-interleaved-store-i16-stride-5.ll  | 276 +++++-----
 .../vector-interleaved-store-i16-stride-7.ll  |   3 +-
 .../vector-interleaved-store-i8-stride-3.ll   |   8 +-
 .../vector-interleaved-store-i8-stride-5.ll   | 492 +++++++++---------
 .../vector-interleaved-store-i8-stride-6.ll   | 100 ++--
 .../vector-interleaved-store-i8-stride-7.ll   | 428 +++++++--------
 llvm/test/CodeGen/X86/vector-shuffle-v192.ll  |  52 +-
 .../CodeGen/X86/x86-interleaved-access.ll     |   8 +-
 11 files changed, 730 insertions(+), 711 deletions(-)

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 22630f9a6b82..adafb425babf 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -7040,6 +7040,31 @@ static SDValue combineToConsecutiveLoads(EVT VT, SDValue Op, const SDLoc &DL,
                                   IsAfterLegalize);
 }
 
+static Constant *getConstantVector(MVT VT, ArrayRef<APInt> Bits,
+                                   const APInt &Undefs, LLVMContext &C) {
+  unsigned ScalarSize = VT.getScalarSizeInBits();
+  Type *Ty = EVT(VT.getScalarType()).getTypeForEVT(C);
+
+  auto getConstantScalar = [&](const APInt &Val) -> Constant * {
+    if (VT.isFloatingPoint()) {
+      if (ScalarSize == 16)
+        return ConstantFP::get(C, APFloat(APFloat::IEEEhalf(), Val));
+      if (ScalarSize == 32)
+        return ConstantFP::get(C, APFloat(APFloat::IEEEsingle(), Val));
+      assert(ScalarSize == 64 && "Unsupported floating point scalar size");
+      return ConstantFP::get(C, APFloat(APFloat::IEEEdouble(), Val));
+    }
+    return Constant::getIntegerValue(Ty, Val);
+  };
+
+  SmallVector<Constant *, 32> ConstantVec;
+  for (unsigned I = 0, E = Bits.size(); I != E; ++I)
+    ConstantVec.push_back(Undefs[I] ? UndefValue::get(Ty)
+                                    : getConstantScalar(Bits[I]));
+
+  return ConstantVector::get(ArrayRef<Constant *>(ConstantVec));
+}
+
 static Constant *getConstantVector(MVT VT, const APInt &SplatValue,
                                    unsigned SplatBitSize, LLVMContext &C) {
   unsigned ScalarSize = VT.getScalarSizeInBits();
@@ -54978,6 +55003,32 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
     }
   }
 
+  // Attempt to fold target constant loads.
+  if (all_of(Ops, [](SDValue Op) { return getTargetConstantFromNode(Op); })) {
+    SmallVector<APInt> EltBits;
+    APInt UndefElts = APInt::getZero(VT.getVectorNumElements());
+    for (unsigned I = 0; I != NumOps; ++I) {
+      APInt OpUndefElts;
+      SmallVector<APInt> OpEltBits;
+      if (!getTargetConstantBitsFromNode(Ops[I], EltSizeInBits, OpUndefElts,
+                                         OpEltBits, true, false))
+        break;
+      EltBits.append(OpEltBits);
+      UndefElts.insertBits(OpUndefElts, I * OpUndefElts.getBitWidth());
+    }
+    if (EltBits.size() == VT.getVectorNumElements()) {
+      Constant *C = getConstantVector(VT, EltBits, UndefElts, Ctx);
+      MVT PVT = TLI.getPointerTy(DAG.getDataLayout());
+      SDValue CV = DAG.getConstantPool(C, PVT);
+      MachineFunction &MF = DAG.getMachineFunction();
+      MachinePointerInfo MPI = MachinePointerInfo::getConstantPool(MF);
+      SDValue Ld = DAG.getLoad(VT, DL, DAG.getEntryNode(), CV, MPI);
+      SDValue Sub = extractSubVector(Ld, 0, DAG, DL, Op0.getValueSizeInBits());
+      DAG.ReplaceAllUsesOfValueWith(Op0, Sub);
+      return Ld;
+    }
+  }
+
   // If this simple subvector or scalar/subvector broadcast_load is inserted
   // into both halves, use a larger broadcast_load. Update other uses to use
   // an extracted subvector.
@@ -55000,23 +55051,6 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
     }
   }
 
-  // Attempt to fold target constant loads.
-  if (all_of(Ops, [](SDValue Op) { return getTargetConstantFromNode(Op); })) {
-    SmallVector<APInt> EltBits;
-    APInt UndefElts = APInt::getZero(VT.getVectorNumElements());
-    for (unsigned I = 0; I != NumOps; ++I) {
-      APInt OpUndefElts;
-      SmallVector<APInt> OpEltBits;
-      if (!getTargetConstantBitsFromNode(Ops[I], EltSizeInBits, OpUndefElts,
-                                        OpEltBits, true, false))
-          break;
-      EltBits.append(OpEltBits);
-      UndefElts.insertBits(OpUndefElts, I * OpUndefElts.getBitWidth());
-    }
-    if (EltBits.size() == VT.getVectorNumElements())
-      return getConstVector(EltBits, UndefElts, VT, DAG, DL);
-  }
-
   // If we're splatting a 128-bit subvector to 512-bits, use SHUF128 directly.
   if (IsSplat && NumOps == 4 && VT.is512BitVector() &&
       Subtarget.useAVX512Regs()) {
diff --git a/llvm/test/CodeGen/X86/combine-concatvectors.ll b/llvm/test/CodeGen/X86/combine-concatvectors.ll
index a8c3fb589bbf..8a0e39c57b78 100644
--- a/llvm/test/CodeGen/X86/combine-concatvectors.ll
+++ b/llvm/test/CodeGen/X86/combine-concatvectors.ll
@@ -48,8 +48,7 @@ define void @concat_of_broadcast_v2f64_v4f64() {
 ; AVX1-NEXT:    movl $1091567616, 30256(%rax) # imm = 0x41100000
 ; AVX1-NEXT:    movabsq $4294967297, %rcx # imm = 0x100000001
 ; AVX1-NEXT:    movq %rcx, 46348(%rax)
-; AVX1-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = [7.812501848093234E-3,7.812501848093234E-3,7.812501848093234E-3,7.812501848093234E-3]
-; AVX1-NEXT:    # ymm0 = mem[0,1,0,1]
+; AVX1-NEXT:    vbroadcastss {{.*#+}} ymm0 = [1065353216,1065353216,1065353216,1065353216,1065353216,1065353216,1065353216,1065353216]
 ; AVX1-NEXT:    vmovups %ymm0, 48296(%rax)
 ; AVX1-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX1-NEXT:    vmovsd %xmm0, 47372(%rax)
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
index 3dc5818d6c9b..16b5e8db76ef 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
@@ -652,8 +652,7 @@ define void @store_i16_stride3_vf16(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
 ; AVX512F-NEXT:    vinserti64x4 $1, %ymm1, %zmm3, %zmm1
 ; AVX512F-NEXT:    vmovdqa {{.*#+}} ymm2 = <u,0,0,u,1,1,u,2>
 ; AVX512F-NEXT:    vpermd %ymm0, %ymm2, %ymm2
-; AVX512F-NEXT:    vmovdqa {{.*#+}} ymm3 = [65535,65535,0,65535,65535,0,65535,65535,0,65535,65535,0,65535,65535,0,65535]
-; AVX512F-NEXT:    vpandn %ymm2, %ymm3, %ymm2
+; AVX512F-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
 ; AVX512F-NEXT:    vpshufb {{.*#+}} ymm3 = zero,zero,ymm0[10,11],zero,zero,zero,zero,ymm0[12,13],zero,zero,zero,zero,ymm0[14,15],zero,zero,zero,zero,ymm0[16,17],zero,zero,zero,zero,ymm0[18,19],zero,zero,zero,zero
 ; AVX512F-NEXT:    vinserti64x4 $1, %ymm3, %zmm2, %zmm2
 ; AVX512F-NEXT:    vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm2
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
index 59866f2b8577..413cd7d63d8c 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
@@ -2776,7 +2776,7 @@ define void @store_i16_stride5_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
 ; AVX512F-SLOW-NEXT:    vmovdqa {{.*#+}} xmm13 = [4,5,2,3,2,3,0,1,10,11,8,9,4,5,6,7]
 ; AVX512F-SLOW-NEXT:    vpshufb %xmm13, %xmm0, %xmm0
 ; AVX512F-SLOW-NEXT:    vmovdqa64 (%rdx), %ymm17
-; AVX512F-SLOW-NEXT:    vmovdqa 32(%rdx), %ymm5
+; AVX512F-SLOW-NEXT:    vmovdqa 32(%rdx), %ymm6
 ; AVX512F-SLOW-NEXT:    vpshufd {{.*#+}} ymm2 = ymm17[3,2,3,3,7,6,7,7]
 ; AVX512F-SLOW-NEXT:    vmovdqa (%rcx), %ymm1
 ; AVX512F-SLOW-NEXT:    vpshufhw {{.*#+}} ymm3 = ymm1[0,1,2,3,5,6,7,7,8,9,10,11,13,14,15,15]
@@ -2793,8 +2793,8 @@ define void @store_i16_stride5_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
 ; AVX512F-SLOW-NEXT:    vpshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,4,5,6]
 ; AVX512F-SLOW-NEXT:    vmovdqa64 (%rdi), %ymm20
 ; AVX512F-SLOW-NEXT:    vpshufd {{.*#+}} ymm3 = ymm20[2,3,2,3,6,7,6,7]
-; AVX512F-SLOW-NEXT:    vmovdqa (%rsi), %ymm6
-; AVX512F-SLOW-NEXT:    vpshufhw {{.*#+}} ymm7 = ymm6[0,1,2,3,7,6,5,7,8,9,10,11,15,14,13,15]
+; AVX512F-SLOW-NEXT:    vmovdqa (%rsi), %ymm5
+; AVX512F-SLOW-NEXT:    vpshufhw {{.*#+}} ymm7 = ymm5[0,1,2,3,7,6,5,7,8,9,10,11,15,14,13,15]
 ; AVX512F-SLOW-NEXT:    vpshufd {{.*#+}} ymm7 = ymm7[2,3,2,2,6,7,6,6]
 ; AVX512F-SLOW-NEXT:    vpblendw {{.*#+}} ymm3 = ymm7[0],ymm3[1],ymm7[2],ymm3[3],ymm7[4,5],ymm3[6],ymm7[7,8],ymm3[9],ymm7[10],ymm3[11],ymm7[12,13],ymm3[14],ymm7[15]
 ; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm3 = ymm3[2,3,2,2]
@@ -2822,7 +2822,7 @@ define void @store_i16_stride5_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
 ; AVX512F-SLOW-NEXT:    vmovdqa {{.*#+}} ymm4 = <u,u,12,13,u,u,0,1,u,u,u,u,14,15,u,u,u,u,28,29,u,u,16,17,u,u,u,u,30,31,u,u>
 ; AVX512F-SLOW-NEXT:    vpshufb %ymm4, %ymm0, %ymm2
 ; AVX512F-SLOW-NEXT:    vmovdqa64 %ymm4, %ymm23
-; AVX512F-SLOW-NEXT:    vpshufd {{.*#+}} ymm8 = ymm5[3,0,3,0,7,4,7,4]
+; AVX512F-SLOW-NEXT:    vpshufd {{.*#+}} ymm8 = ymm6[3,0,3,0,7,4,7,4]
 ; AVX512F-SLOW-NEXT:    vpblendw {{.*#+}} ymm2 = ymm8[0],ymm2[1],ymm8[2],ymm2[3],ymm8[4,5],ymm2[6],ymm8[7,8],ymm2[9],ymm8[10],ymm2[11],ymm8[12,13],ymm2[14],ymm8[15]
 ; AVX512F-SLOW-NEXT:    vmovdqa {{.*#+}} xmm8 = <10,11,u,u,6,7,u,u,8,9,8,9,u,u,8,9>
 ; AVX512F-SLOW-NEXT:    vpshufb %xmm8, %xmm10, %xmm10
@@ -2831,15 +2831,15 @@ define void @store_i16_stride5_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
 ; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm9 = ymm9[0,1,0,0]
 ; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm2, %zmm9, %zmm2
 ; AVX512F-SLOW-NEXT:    vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm11, %zmm2
-; AVX512F-SLOW-NEXT:    vmovdqa (%r8), %ymm10
-; AVX512F-SLOW-NEXT:    vmovdqa 32(%r8), %ymm9
+; AVX512F-SLOW-NEXT:    vmovdqa (%r8), %ymm9
+; AVX512F-SLOW-NEXT:    vmovdqa 32(%r8), %ymm10
 ; AVX512F-SLOW-NEXT:    vmovdqa {{.*#+}} ymm11 = [128,128,128,128,12,13,128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,16,17,128,128,128,128,128,128]
-; AVX512F-SLOW-NEXT:    vpshufb %ymm11, %ymm9, %ymm4
+; AVX512F-SLOW-NEXT:    vpshufb %ymm11, %ymm10, %ymm4
 ; AVX512F-SLOW-NEXT:    vmovdqa64 {{.*#+}} zmm21 = [65535,65535,65535,0,65535,65535,65535,65535,0,65535,65535,65535,65535,0,65535,65535,65535,65535,0,65535,65535,65535,65535,0,65535,65535,65535,65535,0,65535,65535,65535]
-; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm9 = ymm9[0,1,1,1]
-; AVX512F-SLOW-NEXT:    vpandnq %ymm9, %ymm21, %ymm9
-; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm4, %zmm9, %zmm9
-; AVX512F-SLOW-NEXT:    vpternlogq $248, %zmm21, %zmm2, %zmm9
+; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm10 = ymm10[0,1,1,1]
+; AVX512F-SLOW-NEXT:    vpandnq %ymm10, %ymm21, %ymm10
+; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm4, %zmm10, %zmm10
+; AVX512F-SLOW-NEXT:    vpternlogq $248, %zmm21, %zmm2, %zmm10
 ; AVX512F-SLOW-NEXT:    vmovdqa (%rdx), %xmm2
 ; AVX512F-SLOW-NEXT:    vpunpcklwd {{.*#+}} xmm4 = xmm12[0],xmm2[0],xmm12[1],xmm2[1],xmm12[2],xmm2[2],xmm12[3],xmm2[3]
 ; AVX512F-SLOW-NEXT:    vpshufb %xmm13, %xmm4, %xmm4
@@ -2860,43 +2860,44 @@ define void @store_i16_stride5_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
 ; AVX512F-SLOW-NEXT:    vmovdqa64 {{.*#+}} zmm7 = [65535,65535,0,0,65535,65535,65535,0,0,65535,65535,65535,0,0,65535,65535,65535,0,0,65535,65535,65535,0,0,65535,65535,65535,0,0,65535,65535,65535]
 ; AVX512F-SLOW-NEXT:    vpternlogq $226, %zmm2, %zmm7, %zmm4
 ; AVX512F-SLOW-NEXT:    vpbroadcastq (%r8), %ymm2
-; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm8 = ymm10[0,1,1,1]
-; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm8, %zmm2, %zmm2
-; AVX512F-SLOW-NEXT:    vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm4, %zmm2
-; AVX512F-SLOW-NEXT:    vpshufd {{.*#+}} ymm4 = ymm18[0,1,2,1,4,5,6,5]
-; AVX512F-SLOW-NEXT:    vprolq $16, %ymm3, %ymm8
-; AVX512F-SLOW-NEXT:    vpblendw {{.*#+}} ymm4 = ymm8[0,1],ymm4[2],ymm8[3],ymm4[4],ymm8[5,6],ymm4[7],ymm8[8,9],ymm4[10],ymm8[11],ymm4[12],ymm8[13,14],ymm4[15]
-; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm4 = ymm4[2,3,2,3]
-; AVX512F-SLOW-NEXT:    vpshufd {{.*#+}} ymm8 = ymm18[2,3,2,3,6,7,6,7]
+; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm8 = ymm9[0,1,1,1]
+; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm8, %zmm2, %zmm12
+; AVX512F-SLOW-NEXT:    vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm4, %zmm12
+; AVX512F-SLOW-NEXT:    vpshufd {{.*#+}} ymm2 = ymm18[0,1,2,1,4,5,6,5]
+; AVX512F-SLOW-NEXT:    vprolq $16, %ymm3, %ymm4
+; AVX512F-SLOW-NEXT:    vpblendw {{.*#+}} ymm2 = ymm4[0,1],ymm2[2],ymm4[3],ymm2[4],ymm4[5,6],ymm2[7],ymm4[8,9],ymm2[10],ymm4[11],ymm2[12],ymm4[13,14],ymm2[15]
+; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm2 = ymm2[2,3,2,3]
+; AVX512F-SLOW-NEXT:    vpshufd {{.*#+}} ymm4 = ymm18[2,3,2,3,6,7,6,7]
 ; AVX512F-SLOW-NEXT:    vpshufhw {{.*#+}} ymm3 = ymm3[0,1,2,3,7,6,5,7,8,9,10,11,15,14,13,15]
 ; AVX512F-SLOW-NEXT:    vpshufd {{.*#+}} ymm3 = ymm3[2,3,2,2,6,7,6,6]
-; AVX512F-SLOW-NEXT:    vpblendw {{.*#+}} ymm3 = ymm3[0],ymm8[1],ymm3[2],ymm8[3],ymm3[4,5],ymm8[6],ymm3[7,8],ymm8[9],ymm3[10],ymm8[11],ymm3[12,13],ymm8[14],ymm3[15]
+; AVX512F-SLOW-NEXT:    vpblendw {{.*#+}} ymm3 = ymm3[0],ymm4[1],ymm3[2],ymm4[3],ymm3[4,5],ymm4[6],ymm3[7,8],ymm4[9],ymm3[10],ymm4[11],ymm3[12,13],ymm4[14],ymm3[15]
 ; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm3 = ymm3[2,3,2,2]
-; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm3, %zmm4, %zmm4
+; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm3, %zmm2, %zmm2
 ; AVX512F-SLOW-NEXT:    vbroadcasti128 {{.*#+}} ymm3 = [18,19,0,0,22,23,22,23,0,0,20,21,0,0,24,25,18,19,0,0,22,23,22,23,0,0,20,21,0,0,24,25]
 ; AVX512F-SLOW-NEXT:    # ymm3 = mem[0,1,0,1]
-; AVX512F-SLOW-NEXT:    vpshufb %ymm3, %ymm0, %ymm8
-; AVX512F-SLOW-NEXT:    vpshufd {{.*#+}} ymm12 = ymm5[1,1,1,2,5,5,5,6]
-; AVX512F-SLOW-NEXT:    vpblendw {{.*#+}} ymm8 = ymm8[0],ymm12[1],ymm8[2,3],ymm12[4],ymm8[5],ymm12[6],ymm8[7,8],ymm12[9],ymm8[10,11],ymm12[12],ymm8[13],ymm12[14],ymm8[15]
-; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm8 = ymm8[2,3,2,3]
-; AVX512F-SLOW-NEXT:    vpshufd {{.*#+}} ymm5 = ymm5[3,2,3,3,7,6,7,7]
+; AVX512F-SLOW-NEXT:    vpshufb %ymm3, %ymm0, %ymm4
+; AVX512F-SLOW-NEXT:    vpshufd {{.*#+}} ymm8 = ymm6[1,1,1,2,5,5,5,6]
+; AVX512F-SLOW-NEXT:    vpblendw {{.*#+}} ymm4 = ymm4[0],ymm8[1],ymm4[2,3],ymm8[4],ymm4[5],ymm8[6],ymm4[7,8],ymm8[9],ymm4[10,11],ymm8[12],ymm4[13],ymm8[14],ymm4[15]
+; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm4 = ymm4[2,3,2,3]
+; AVX512F-SLOW-NEXT:    vpshufd {{.*#+}} ymm6 = ymm6[3,2,3,3,7,6,7,7]
 ; AVX512F-SLOW-NEXT:    vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,5,6,7,7,8,9,10,11,13,14,15,15]
 ; AVX512F-SLOW-NEXT:    vpshufd {{.*#+}} ymm0 = ymm0[2,3,2,3,6,7,6,7]
-; AVX512F-SLOW-NEXT:    vpblendw {{.*#+}} ymm0 = ymm0[0],ymm5[1],ymm0[2],ymm5[3,4],ymm0[5,6,7,8],ymm5[9],ymm0[10],ymm5[11,12],ymm0[13,14,15]
+; AVX512F-SLOW-NEXT:    vpblendw {{.*#+}} ymm0 = ymm0[0],ymm6[1],ymm0[2],ymm6[3,4],ymm0[5,6,7,8],ymm6[9],ymm0[10],ymm6[11,12],ymm0[13,14,15]
 ; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[2,2,3,2]
-; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm0, %zmm8, %zmm0
-; AVX512F-SLOW-NEXT:    vpternlogq $226, %zmm4, %zmm7, %zmm0
-; AVX512F-SLOW-NEXT:    vpbroadcastq 48(%r8), %ymm4
-; AVX512F-SLOW-NEXT:    vpbroadcastq 56(%r8), %ymm5
-; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm5, %zmm4, %zmm4
-; AVX512F-SLOW-NEXT:    vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm4
+; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm0, %zmm4, %zmm0
+; AVX512F-SLOW-NEXT:    vpternlogq $226, %zmm2, %zmm7, %zmm0
+; AVX512F-SLOW-NEXT:    vpbroadcastq 48(%r8), %ymm2
+; AVX512F-SLOW-NEXT:    vpbroadcastq 56(%r8), %ymm4
+; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm4, %zmm2, %zmm2
+; AVX512F-SLOW-NEXT:    vmovdqa64 {{.*#+}} zmm4 = [65535,0,65535,65535,65535,65535,0,65535,65535,65535,65535,0,65535,65535,65535,65535,0,65535,65535,65535,65535,0,65535,65535,65535,65535,0,65535,65535,65535,65535,0]
+; AVX512F-SLOW-NEXT:    vpternlogd $184, %zmm0, %zmm4, %zmm2
 ; AVX512F-SLOW-NEXT:    vmovdqa64 %ymm22, %ymm0
-; AVX512F-SLOW-NEXT:    vpshufb %ymm0, %ymm6, %ymm0
-; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm5 = ymm20[1,1,2,2]
-; AVX512F-SLOW-NEXT:    vpblendw {{.*#+}} ymm0 = ymm5[0],ymm0[1],ymm5[2,3],ymm0[4],ymm5[5],ymm0[6],ymm5[7,8],ymm0[9],ymm5[10,11],ymm0[12],ymm5[13],ymm0[14],ymm5[15]
-; AVX512F-SLOW-NEXT:    vpshufd {{.*#+}} ymm5 = ymm20[0,1,2,1,4,5,6,5]
-; AVX512F-SLOW-NEXT:    vprolq $16, %ymm6, %ymm6
-; AVX512F-SLOW-NEXT:    vpblendw {{.*#+}} ymm5 = ymm6[0,1],ymm5[2],ymm6[3],ymm5[4],ymm6[5,6],ymm5[7],ymm6[8,9],ymm5[10],ymm6[11],ymm5[12],ymm6[13,14],ymm5[15]
+; AVX512F-SLOW-NEXT:    vpshufb %ymm0, %ymm5, %ymm0
+; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm6 = ymm20[1,1,2,2]
+; AVX512F-SLOW-NEXT:    vpblendw {{.*#+}} ymm0 = ymm6[0],ymm0[1],ymm6[2,3],ymm0[4],ymm6[5],ymm0[6],ymm6[7,8],ymm0[9],ymm6[10,11],ymm0[12],ymm6[13],ymm0[14],ymm6[15]
+; AVX512F-SLOW-NEXT:    vpshufd {{.*#+}} ymm6 = ymm20[0,1,2,1,4,5,6,5]
+; AVX512F-SLOW-NEXT:    vprolq $16, %ymm5, %ymm5
+; AVX512F-SLOW-NEXT:    vpblendw {{.*#+}} ymm5 = ymm5[0,1],ymm6[2],ymm5[3],ymm6[4],ymm5[5,6],ymm6[7],ymm5[8,9],ymm6[10],ymm5[11],ymm6[12],ymm5[13,14],ymm6[15]
 ; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm5 = ymm5[2,3,2,3]
 ; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm5, %zmm0, %zmm0
 ; AVX512F-SLOW-NEXT:    vmovdqa64 %ymm23, %ymm5
@@ -2909,15 +2910,15 @@ define void @store_i16_stride5_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
 ; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm1 = ymm1[2,3,2,3]
 ; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm1, %zmm5, %zmm1
 ; AVX512F-SLOW-NEXT:    vpternlogq $226, %zmm0, %zmm16, %zmm1
-; AVX512F-SLOW-NEXT:    vpshufb %ymm11, %ymm10, %ymm0
-; AVX512F-SLOW-NEXT:    vpbroadcastq 16(%r8), %ymm3
-; AVX512F-SLOW-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
-; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm3, %zmm0, %zmm0
+; AVX512F-SLOW-NEXT:    vpbroadcastq 16(%r8), %ymm0
+; AVX512F-SLOW-NEXT:    vpandn %ymm0, %ymm4, %ymm0
+; AVX512F-SLOW-NEXT:    vpshufb %ymm11, %ymm9, %ymm3
+; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm0, %zmm3, %zmm0
 ; AVX512F-SLOW-NEXT:    vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
 ; AVX512F-SLOW-NEXT:    vmovdqa64 %zmm0, 64(%r9)
-; AVX512F-SLOW-NEXT:    vmovdqa64 %zmm4, 256(%r9)
-; AVX512F-SLOW-NEXT:    vmovdqa64 %zmm2, (%r9)
-; AVX512F-SLOW-NEXT:    vmovdqa64 %zmm9, 192(%r9)
+; AVX512F-SLOW-NEXT:    vmovdqa64 %zmm2, 256(%r9)
+; AVX512F-SLOW-NEXT:    vmovdqa64 %zmm12, (%r9)
+; AVX512F-SLOW-NEXT:    vmovdqa64 %zmm10, 192(%r9)
 ; AVX512F-SLOW-NEXT:    vmovdqa64 %zmm19, 128(%r9)
 ; AVX512F-SLOW-NEXT:    vzeroupper
 ; AVX512F-SLOW-NEXT:    retq
@@ -2927,7 +2928,7 @@ define void @store_i16_stride5_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
 ; AVX512F-FAST-NEXT:    vmovdqa 32(%rsi), %ymm5
 ; AVX512F-FAST-NEXT:    vmovdqa {{.*#+}} ymm1 = <u,u,0,1,u,u,u,u,14,15,u,u,2,3,u,u,u,u,16,17,u,u,u,u,30,31,u,u,18,19,u,u>
 ; AVX512F-FAST-NEXT:    vpshufb %ymm1, %ymm5, %ymm0
-; AVX512F-FAST-NEXT:    vmovdqa64 %ymm1, %ymm23
+; AVX512F-FAST-NEXT:    vmovdqa64 %ymm1, %ymm17
 ; AVX512F-FAST-NEXT:    vmovdqa 32(%rdi), %ymm7
 ; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm1 = ymm7[1,1,2,2]
 ; AVX512F-FAST-NEXT:    vpblendw {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2,3],ymm0[4],ymm1[5],ymm0[6],ymm1[7,8],ymm0[9],ymm1[10,11],ymm0[12],ymm1[13],ymm0[14],ymm1[15]
@@ -2935,29 +2936,29 @@ define void @store_i16_stride5_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
 ; AVX512F-FAST-NEXT:    vmovdqa 32(%rsi), %xmm2
 ; AVX512F-FAST-NEXT:    vmovdqa {{.*#+}} xmm12 = <6,7,u,u,10,11,6,7,u,u,8,9,u,u,12,13>
 ; AVX512F-FAST-NEXT:    vpshufb %xmm12, %xmm2, %xmm1
-; AVX512F-FAST-NEXT:    vmovdqa64 %xmm2, %xmm19
+; AVX512F-FAST-NEXT:    vmovdqa64 %xmm2, %xmm20
 ; AVX512F-FAST-NEXT:    vpbroadcastq 40(%rdi), %xmm2
 ; AVX512F-FAST-NEXT:    vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2,3],xmm2[4],xmm1[5],xmm2[6],xmm1[7]
 ; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm1 = ymm1[0,1,0,1]
 ; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
-; AVX512F-FAST-NEXT:    vmovdqa (%rcx), %ymm4
+; AVX512F-FAST-NEXT:    vmovdqa (%rcx), %ymm1
 ; AVX512F-FAST-NEXT:    vmovdqa 32(%rcx), %ymm8
-; AVX512F-FAST-NEXT:    vmovdqa {{.*#+}} ymm2 = <u,u,12,13,u,u,0,1,u,u,u,u,14,15,u,u,u,u,28,29,u,u,16,17,u,u,u,u,30,31,u,u>
-; AVX512F-FAST-NEXT:    vpshufb %ymm2, %ymm8, %ymm1
-; AVX512F-FAST-NEXT:    vmovdqa64 %ymm2, %ymm24
-; AVX512F-FAST-NEXT:    vmovdqa64 (%rdx), %ymm17
+; AVX512F-FAST-NEXT:    vmovdqa {{.*#+}} ymm3 = <u,u,12,13,u,u,0,1,u,u,u,u,14,15,u,u,u,u,28,29,u,u,16,17,u,u,u,u,30,31,u,u>
+; AVX512F-FAST-NEXT:    vpshufb %ymm3, %ymm8, %ymm2
+; AVX512F-FAST-NEXT:    vmovdqa64 %ymm3, %ymm24
+; AVX512F-FAST-NEXT:    vmovdqa64 (%rdx), %ymm18
 ; AVX512F-FAST-NEXT:    vmovdqa 32(%rdx), %ymm9
-; AVX512F-FAST-NEXT:    vpshufd {{.*#+}} ymm2 = ymm9[3,0,3,0,7,4,7,4]
-; AVX512F-FAST-NEXT:    vpblendw {{.*#+}} ymm1 = ymm2[0],ymm1[1],ymm2[2],ymm1[3],ymm2[4,5],ymm1[6],ymm2[7,8],ymm1[9],ymm2[10],ymm1[11],ymm2[12,13],ymm1[14],ymm2[15]
+; AVX512F-FAST-NEXT:    vpshufd {{.*#+}} ymm4 = ymm9[3,0,3,0,7,4,7,4]
+; AVX512F-FAST-NEXT:    vpblendw {{.*#+}} ymm2 = ymm4[0],ymm2[1],ymm4[2],ymm2[3],ymm4[4,5],ymm2[6],ymm4[7,8],ymm2[9],ymm4[10],ymm2[11],ymm4[12,13],ymm2[14],ymm4[15]
 ; AVX512F-FAST-NEXT:    vmovdqa 32(%rcx), %xmm11
-; AVX512F-FAST-NEXT:    vmovdqa {{.*#+}} xmm15 = <10,11,u,u,6,7,u,u,8,9,8,9,u,u,8,9>
-; AVX512F-FAST-NEXT:    vpshufb %xmm15, %xmm11, %xmm2
+; AVX512F-FAST-NEXT:    vmovdqa {{.*#+}} xmm4 = <10,11,u,u,6,7,u,u,8,9,8,9,u,u,8,9>
+; AVX512F-FAST-NEXT:    vpshufb %xmm4, %xmm11, %xmm13
 ; AVX512F-FAST-NEXT:    vmovdqa 32(%rdx), %xmm6
-; AVX512F-FAST-NEXT:    vpshufd {{.*#+}} xmm13 = xmm6[1,2,2,2]
-; AVX512F-FAST-NEXT:    vpblendw {{.*#+}} xmm2 = xmm2[0],xmm13[1],xmm2[2],xmm13[3],xmm2[4,5],xmm13[6],xmm2[7]
-; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm2 = ymm2[0,1,0,0]
-; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm1, %zmm2, %zmm1
-; AVX512F-FAST-NEXT:    vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1
+; AVX512F-FAST-NEXT:    vpshufd {{.*#+}} xmm15 = xmm6[1,2,2,2]
+; AVX512F-FAST-NEXT:    vpblendw {{.*#+}} xmm13 = xmm13[0],xmm15[1],xmm13[2],xmm15[3],xmm13[4,5],xmm15[6],xmm13[7]
+; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm13 = ymm13[0,1,0,0]
+; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm2, %zmm13, %zmm15
+; AVX512F-FAST-NEXT:    vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm15
 ; AVX512F-FAST-NEXT:    vmovdqa (%r8), %ymm0
 ; AVX512F-FAST-NEXT:    vmovdqa 32(%r8), %ymm2
 ; AVX512F-FAST-NEXT:    vmovdqa {{.*#+}} ymm13 = [128,128,128,128,12,13,128,128,128,128,128,128,128,128,14,15,128,128,128,128,128,128,128,128,16,17,128,128,128,128,128,128]
@@ -2966,64 +2967,65 @@ define void @store_i16_stride5_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
 ; AVX512F-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm16 = [65535,65535,65535,0,65535,65535,65535,65535,0,65535,65535,65535,65535,0,65535,65535,65535,65535,0,65535,65535,65535,65535,0,65535,65535,65535,65535,0,65535,65535,65535]
 ; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm2 = ymm2[0,1,1,1]
 ; AVX512F-FAST-NEXT:    vpandnq %ymm2, %ymm16, %ymm2
-; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm3, %zmm2, %zmm18
-; AVX512F-FAST-NEXT:    vpternlogq $248, %zmm16, %zmm1, %zmm18
-; AVX512F-FAST-NEXT:    vmovdqa (%rcx), %xmm1
-; AVX512F-FAST-NEXT:    vpshufb %xmm15, %xmm1, %xmm3
+; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm3, %zmm2, %zmm19
+; AVX512F-FAST-NEXT:    vpternlogq $248, %zmm16, %zmm15, %zmm19
+; AVX512F-FAST-NEXT:    vmovdqa (%rcx), %xmm3
+; AVX512F-FAST-NEXT:    vpshufb %xmm4, %xmm3, %xmm4
 ; AVX512F-FAST-NEXT:    vmovdqa (%rdx), %xmm15
 ; AVX512F-FAST-NEXT:    vpshufd {{.*#+}} xmm14 = xmm15[1,2,2,2]
-; AVX512F-FAST-NEXT:    vpblendw {{.*#+}} xmm3 = xmm3[0],xmm14[1],xmm3[2],xmm14[3],xmm3[4,5],xmm14[6],xmm3[7]
-; AVX512F-FAST-NEXT:    vpunpcklwd {{.*#+}} xmm1 = xmm1[0],xmm15[0],xmm1[1],xmm15[1],xmm1[2],xmm15[2],xmm1[3],xmm15[3]
+; AVX512F-FAST-NEXT:    vpblendw {{.*#+}} xmm4 = xmm4[0],xmm14[1],xmm4[2],xmm14[3],xmm4[4,5],xmm14[6],xmm4[7]
+; AVX512F-FAST-NEXT:    vpunpcklwd {{.*#+}} xmm3 = xmm3[0],xmm15[0],xmm3[1],xmm15[1],xmm3[2],xmm15[2],xmm3[3],xmm15[3]
 ; AVX512F-FAST-NEXT:    vmovdqa {{.*#+}} xmm2 = [4,5,2,3,2,3,0,1,10,11,8,9,4,5,6,7]
-; AVX512F-FAST-NEXT:    vpshufb %xmm2, %xmm1, %xmm1
-; AVX512F-FAST-NEXT:    vmovdqa64 %xmm2, %xmm20
+; AVX512F-FAST-NEXT:    vpshufb %xmm2, %xmm3, %xmm3
+; AVX512F-FAST-NEXT:    vmovdqa64 %xmm2, %xmm21
 ; AVX512F-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm14 = [0,1,0,1,8,9,8,8]
-; AVX512F-FAST-NEXT:    vpermi2q %zmm3, %zmm1, %zmm14
-; AVX512F-FAST-NEXT:    vpshufb %xmm12, %xmm10, %xmm1
-; AVX512F-FAST-NEXT:    vpbroadcastq 8(%rdi), %xmm3
-; AVX512F-FAST-NEXT:    vpblendw {{.*#+}} xmm1 = xmm1[0],xmm3[1],xmm1[2,3],xmm3[4],xmm1[5],xmm3[6],xmm1[7]
-; AVX512F-FAST-NEXT:    vmovdqa (%rdi), %xmm3
-; AVX512F-FAST-NEXT:    vmovdqa64 32(%rdi), %xmm21
-; AVX512F-FAST-NEXT:    vpunpcklwd {{.*#+}} xmm3 = xmm3[0],xmm10[0],xmm3[1],xmm10[1],xmm3[2],xmm10[2],xmm3[3],xmm10[3]
+; AVX512F-FAST-NEXT:    vpermi2q %zmm4, %zmm3, %zmm14
+; AVX512F-FAST-NEXT:    vpshufb %xmm12, %xmm10, %xmm3
+; AVX512F-FAST-NEXT:    vpbroadcastq 8(%rdi), %xmm4
+; AVX512F-FAST-NEXT:    vpblendw {{.*#+}} xmm3 = xmm3[0],xmm4[1],xmm3[2,3],xmm4[4],xmm3[5],xmm4[6],xmm3[7]
+; AVX512F-FAST-NEXT:    vmovdqa (%rdi), %xmm4
+; AVX512F-FAST-NEXT:    vmovdqa64 32(%rdi), %xmm22
+; AVX512F-FAST-NEXT:    vpunpcklwd {{.*#+}} xmm4 = xmm4[0],xmm10[0],xmm4[1],xmm10[1],xmm4[2],xmm10[2],xmm4[3],xmm10[3]
 ; AVX512F-FAST-NEXT:    vmovdqa {{.*#+}} xmm2 = [0,1,2,3,8,9,10,11,4,5,4,5,6,7,12,13]
-; AVX512F-FAST-NEXT:    vpshufb %xmm2, %xmm3, %xmm3
-; AVX512F-FAST-NEXT:    vmovdqa64 %xmm2, %xmm22
-; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm1, %zmm3, %zmm1
-; AVX512F-FAST-NEXT:    vpermq {{.*#+}} zmm1 = zmm1[0,1,0,1,4,5,4,5]
+; AVX512F-FAST-NEXT:    vpshufb %xmm2, %xmm4, %xmm4
+; AVX512F-FAST-NEXT:    vmovdqa64 %xmm2, %xmm23
+; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm3, %zmm4, %zmm3
+; AVX512F-FAST-NEXT:    vpermq {{.*#+}} zmm3 = zmm3[0,1,0,1,4,5,4,5]
 ; AVX512F-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm16 = [65535,65535,0,0,65535,65535,65535,0,0,65535,65535,65535,0,0,65535,65535,65535,0,0,65535,65535,65535,0,0,65535,65535,65535,0,0,65535,65535,65535]
-; AVX512F-FAST-NEXT:    vpternlogq $226, %zmm14, %zmm16, %zmm1
-; AVX512F-FAST-NEXT:    vpbroadcastq (%r8), %ymm3
+; AVX512F-FAST-NEXT:    vpternlogq $226, %zmm14, %zmm16, %zmm3
+; AVX512F-FAST-NEXT:    vpbroadcastq (%r8), %ymm4
 ; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm10 = ymm0[0,1,1,1]
-; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm10, %zmm3, %zmm10
-; AVX512F-FAST-NEXT:    vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm10
+; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm10, %zmm4, %zmm10
+; AVX512F-FAST-NEXT:    vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm10
 ; AVX512F-FAST-NEXT:    vmovdqa (%rsi), %ymm15
-; AVX512F-FAST-NEXT:    vmovdqa64 %ymm23, %ymm1
-; AVX512F-FAST-NEXT:    vpshufb %ymm1, %ymm15, %ymm1
+; AVX512F-FAST-NEXT:    vmovdqa64 %ymm17, %ymm2
+; AVX512F-FAST-NEXT:    vpshufb %ymm2, %ymm15, %ymm3
 ; AVX512F-FAST-NEXT:    vmovdqa (%rdi), %ymm14
-; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm3 = ymm14[1,1,2,2]
-; AVX512F-FAST-NEXT:    vpblendw {{.*#+}} ymm1 = ymm3[0],ymm1[1],ymm3[2,3],ymm1[4],ymm3[5],ymm1[6],ymm3[7,8],ymm1[9],ymm3[10,11],ymm1[12],ymm3[13],ymm1[14],ymm3[15]
-; AVX512F-FAST-NEXT:    vpshufd {{.*#+}} ymm3 = ymm14[0,1,2,1,4,5,6,5]
+; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm4 = ymm14[1,1,2,2]
+; AVX512F-FAST-NEXT:    vpblendw {{.*#+}} ymm3 = ymm4[0],ymm3[1],ymm4[2,3],ymm3[4],ymm4[5],ymm3[6],ymm4[7,8],ymm3[9],ymm4[10,11],ymm3[12],ymm4[13],ymm3[14],ymm4[15]
+; AVX512F-FAST-NEXT:    vpshufd {{.*#+}} ymm4 = ymm14[0,1,2,1,4,5,6,5]
 ; AVX512F-FAST-NEXT:    vprolq $16, %ymm15, %ymm13
-; AVX512F-FAST-NEXT:    vpblendw {{.*#+}} ymm3 = ymm13[0,1],ymm3[2],ymm13[3],ymm3[4],ymm13[5,6],ymm3[7],ymm13[8,9],ymm3[10],ymm13[11],ymm3[12],ymm13[13,14],ymm3[15]
-; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm3 = ymm3[2,3,2,3]
-; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm3, %zmm1, %zmm3
-; AVX512F-FAST-NEXT:    vmovdqa64 %ymm24, %ymm1
-; AVX512F-FAST-NEXT:    vpshufb %ymm1, %ymm4, %ymm1
-; AVX512F-FAST-NEXT:    vpshufd {{.*#+}} ymm13 = ymm17[3,0,3,0,7,4,7,4]
-; AVX512F-FAST-NEXT:    vpblendw {{.*#+}} ymm13 = ymm13[0],ymm1[1],ymm13[2],ymm1[3],ymm13[4,5],ymm1[6],ymm13[7,8],ymm1[9],ymm13[10],ymm1[11],ymm13[12,13],ymm1[14],ymm13[15]
-; AVX512F-FAST-NEXT:    vbroadcasti128 {{.*#+}} ymm1 = [18,19,0,0,22,23,22,23,0,0,20,21,0,0,24,25,18,19,0,0,22,23,22,23,0,0,20,21,0,0,24,25]
-; AVX512F-FAST-NEXT:    # ymm1 = mem[0,1,0,1]
-; AVX512F-FAST-NEXT:    vpshufb %ymm1, %ymm4, %ymm2
-; AVX512F-FAST-NEXT:    vpshufd {{.*#+}} ymm12 = ymm17[1,1,1,2,5,5,5,6]
+; AVX512F-FAST-NEXT:    vpblendw {{.*#+}} ymm4 = ymm13[0,1],ymm4[2],ymm13[3],ymm4[4],ymm13[5,6],ymm4[7],ymm13[8,9],ymm4[10],ymm13[11],ymm4[12],ymm13[13,14],ymm4[15]
+; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm4 = ymm4[2,3,2,3]
+; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm4, %zmm3, %zmm3
+; AVX512F-FAST-NEXT:    vmovdqa64 %ymm24, %ymm2
+; AVX512F-FAST-NEXT:    vpshufb %ymm2, %ymm1, %ymm4
+; AVX512F-FAST-NEXT:    vpshufd {{.*#+}} ymm13 = ymm18[3,0,3,0,7,4,7,4]
+; AVX512F-FAST-NEXT:    vpblendw {{.*#+}} ymm13 = ymm13[0],ymm4[1],ymm13[2],ymm4[3],ymm13[4,5],ymm4[6],ymm13[7,8],ymm4[9],ymm13[10],ymm4[11],ymm13[12,13],ymm4[14],ymm13[15]
+; AVX512F-FAST-NEXT:    vbroadcasti128 {{.*#+}} ymm4 = [18,19,0,0,22,23,22,23,0,0,20,21,0,0,24,25,18,19,0,0,22,23,22,23,0,0,20,21,0,0,24,25]
+; AVX512F-FAST-NEXT:    # ymm4 = mem[0,1,0,1]
+; AVX512F-FAST-NEXT:    vpshufb %ymm4, %ymm1, %ymm2
+; AVX512F-FAST-NEXT:    vpshufd {{.*#+}} ymm12 = ymm18[1,1,1,2,5,5,5,6]
 ; AVX512F-FAST-NEXT:    vpblendw {{.*#+}} ymm2 = ymm2[0],ymm12[1],ymm2[2,3],ymm12[4],ymm2[5],ymm12[6],ymm2[7,8],ymm12[9],ymm2[10,11],ymm12[12],ymm2[13],ymm12[14],ymm2[15]
 ; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm2 = ymm2[2,3,2,3]
 ; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm2, %zmm13, %zmm2
-; AVX512F-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm12 = [65535,65535,65535,0,0,65535,65535,65535,0,0,65535,65535,65535,0,0,65535,65535,65535,0,0,65535,65535,65535,0,0,65535,65535,65535,0,0,65535,65535]
-; AVX512F-FAST-NEXT:    vpternlogq $226, %zmm3, %zmm12, %zmm2
-; AVX512F-FAST-NEXT:    vmovdqa64 %ymm25, %ymm3
-; AVX512F-FAST-NEXT:    vpshufb %ymm3, %ymm0, %ymm0
+; AVX512F-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm17 = [65535,65535,65535,0,0,65535,65535,65535,0,0,65535,65535,65535,0,0,65535,65535,65535,0,0,65535,65535,65535,0,0,65535,65535,65535,0,0,65535,65535]
+; AVX512F-FAST-NEXT:    vpternlogq $226, %zmm3, %zmm17, %zmm2
 ; AVX512F-FAST-NEXT:    vpbroadcastq 16(%r8), %ymm3
-; AVX512F-FAST-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
+; AVX512F-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm12 = [65535,0,65535,65535,65535,65535,0,65535,65535,65535,65535,0,65535,65535,65535,65535,0,65535,65535,65535,65535,0,65535,65535,65535,65535,0,65535,65535,65535,65535,0]
+; AVX512F-FAST-NEXT:    vpandn %ymm3, %ymm12, %ymm3
+; AVX512F-FAST-NEXT:    vmovdqa64 %ymm25, %ymm13
+; AVX512F-FAST-NEXT:    vpshufb %ymm13, %ymm0, %ymm0
 ; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm3, %zmm0, %zmm0
 ; AVX512F-FAST-NEXT:    vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm0
 ; AVX512F-FAST-NEXT:    vbroadcasti128 {{.*#+}} ymm13 = [30,31,28,29,26,27,30,31,30,31,28,29,30,31,28,29,30,31,28,29,26,27,30,31,30,31,28,29,30,31,28,29]
@@ -3040,44 +3042,44 @@ define void @store_i16_stride5_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
 ; AVX512F-FAST-NEXT:    vpshufb %ymm2, %ymm8, %ymm3
 ; AVX512F-FAST-NEXT:    vpshufd {{.*#+}} ymm7 = ymm9[3,2,3,3,7,6,7,7]
 ; AVX512F-FAST-NEXT:    vpblendw {{.*#+}} ymm3 = ymm3[0],ymm7[1],ymm3[2],ymm7[3,4],ymm3[5,6,7,8],ymm7[9],ymm3[10],ymm7[11,12],ymm3[13,14,15]
-; AVX512F-FAST-NEXT:    vpshufb %ymm1, %ymm8, %ymm1
+; AVX512F-FAST-NEXT:    vpshufb %ymm4, %ymm8, %ymm4
 ; AVX512F-FAST-NEXT:    vpshufd {{.*#+}} ymm7 = ymm9[1,1,1,2,5,5,5,6]
-; AVX512F-FAST-NEXT:    vpblendw {{.*#+}} ymm1 = ymm1[0],ymm7[1],ymm1[2,3],ymm7[4],ymm1[5],ymm7[6],ymm1[7,8],ymm7[9],ymm1[10,11],ymm7[12],ymm1[13],ymm7[14],ymm1[15]
+; AVX512F-FAST-NEXT:    vpblendw {{.*#+}} ymm4 = ymm4[0],ymm7[1],ymm4[2,3],ymm7[4],ymm4[5],ymm7[6],ymm4[7,8],ymm7[9],ymm4[10,11],ymm7[12],ymm4[13],ymm7[14],ymm4[15]
 ; AVX512F-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm7 = [2,3,2,3,10,10,11,10]
-; AVX512F-FAST-NEXT:    vpermi2q %zmm3, %zmm1, %zmm7
+; AVX512F-FAST-NEXT:    vpermi2q %zmm3, %zmm4, %zmm7
 ; AVX512F-FAST-NEXT:    vpternlogq $226, %zmm5, %zmm16, %zmm7
-; AVX512F-FAST-NEXT:    vpbroadcastq 48(%r8), %ymm1
-; AVX512F-FAST-NEXT:    vpbroadcastq 56(%r8), %ymm3
-; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm3, %zmm1, %zmm1
-; AVX512F-FAST-NEXT:    vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm7, %zmm1
-; AVX512F-FAST-NEXT:    vpunpcklwd {{.*#+}} xmm3 = xmm11[0],xmm6[0],xmm11[1],xmm6[1],xmm11[2],xmm6[2],xmm11[3],xmm6[3]
-; AVX512F-FAST-NEXT:    vmovdqa64 %xmm20, %xmm5
-; AVX512F-FAST-NEXT:    vpshufb %xmm5, %xmm3, %xmm3
-; AVX512F-FAST-NEXT:    vpshufb %ymm2, %ymm4, %ymm2
-; AVX512F-FAST-NEXT:    vpshufd {{.*#+}} ymm4 = ymm17[3,2,3,3,7,6,7,7]
-; AVX512F-FAST-NEXT:    vpblendw {{.*#+}} ymm2 = ymm2[0],ymm4[1],ymm2[2],ymm4[3,4],ymm2[5,6,7,8],ymm4[9],ymm2[10],ymm4[11,12],ymm2[13,14,15]
-; AVX512F-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm4 = [2,2,3,2,8,9,8,9]
-; AVX512F-FAST-NEXT:    vpermi2q %zmm3, %zmm2, %zmm4
-; AVX512F-FAST-NEXT:    vmovdqa64 %xmm19, %xmm2
-; AVX512F-FAST-NEXT:    vmovdqa64 %xmm21, %xmm3
-; AVX512F-FAST-NEXT:    vpunpcklwd {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3]
-; AVX512F-FAST-NEXT:    vmovdqa64 %xmm22, %xmm3
-; AVX512F-FAST-NEXT:    vpshufb %xmm3, %xmm2, %xmm2
-; AVX512F-FAST-NEXT:    vpshufb %ymm13, %ymm15, %ymm3
+; AVX512F-FAST-NEXT:    vpbroadcastq 48(%r8), %ymm3
+; AVX512F-FAST-NEXT:    vpbroadcastq 56(%r8), %ymm4
+; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm4, %zmm3, %zmm3
+; AVX512F-FAST-NEXT:    vpternlogd $184, %zmm7, %zmm12, %zmm3
+; AVX512F-FAST-NEXT:    vpunpcklwd {{.*#+}} xmm4 = xmm11[0],xmm6[0],xmm11[1],xmm6[1],xmm11[2],xmm6[2],xmm11[3],xmm6[3]
+; AVX512F-FAST-NEXT:    vmovdqa64 %xmm21, %xmm5
+; AVX512F-FAST-NEXT:    vpshufb %xmm5, %xmm4, %xmm4
+; AVX512F-FAST-NEXT:    vpshufb %ymm2, %ymm1, %ymm1
+; AVX512F-FAST-NEXT:    vpshufd {{.*#+}} ymm2 = ymm18[3,2,3,3,7,6,7,7]
+; AVX512F-FAST-NEXT:    vpblendw {{.*#+}} ymm1 = ymm1[0],ymm2[1],ymm1[2],ymm2[3,4],ymm1[5,6,7,8],ymm2[9],ymm1[10],ymm2[11,12],ymm1[13,14,15]
+; AVX512F-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm2 = [2,2,3,2,8,9,8,9]
+; AVX512F-FAST-NEXT:    vpermi2q %zmm4, %zmm1, %zmm2
+; AVX512F-FAST-NEXT:    vmovdqa64 %xmm20, %xmm1
+; AVX512F-FAST-NEXT:    vmovdqa64 %xmm22, %xmm4
+; AVX512F-FAST-NEXT:    vpunpcklwd {{.*#+}} xmm1 = xmm4[0],xmm1[0],xmm4[1],xmm1[1],xmm4[2],xmm1[2],xmm4[3],xmm1[3]
+; AVX512F-FAST-NEXT:    vmovdqa64 %xmm23, %xmm4
+; AVX512F-FAST-NEXT:    vpshufb %xmm4, %xmm1, %xmm1
+; AVX512F-FAST-NEXT:    vpshufb %ymm13, %ymm15, %ymm4
 ; AVX512F-FAST-NEXT:    vpshufd {{.*#+}} ymm5 = ymm14[2,3,2,3,6,7,6,7]
-; AVX512F-FAST-NEXT:    vpblendw {{.*#+}} ymm3 = ymm3[0],ymm5[1],ymm3[2],ymm5[3],ymm3[4,5],ymm5[6],ymm3[7,8],ymm5[9],ymm3[10],ymm5[11],ymm3[12,13],ymm5[14],ymm3[15]
+; AVX512F-FAST-NEXT:    vpblendw {{.*#+}} ymm4 = ymm4[0],ymm5[1],ymm4[2],ymm5[3],ymm4[4,5],ymm5[6],ymm4[7,8],ymm5[9],ymm4[10],ymm5[11],ymm4[12,13],ymm5[14],ymm4[15]
 ; AVX512F-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm5 = [2,3,2,2,8,9,8,9]
-; AVX512F-FAST-NEXT:    vpermi2q %zmm2, %zmm3, %zmm5
-; AVX512F-FAST-NEXT:    vpternlogq $226, %zmm4, %zmm12, %zmm5
-; AVX512F-FAST-NEXT:    vpbroadcastq 24(%r8), %ymm2
-; AVX512F-FAST-NEXT:    vpbroadcastq 32(%r8), %ymm3
-; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm3, %zmm2, %zmm2
-; AVX512F-FAST-NEXT:    vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm5, %zmm2
-; AVX512F-FAST-NEXT:    vmovdqa64 %zmm2, 128(%r9)
-; AVX512F-FAST-NEXT:    vmovdqa64 %zmm1, 256(%r9)
+; AVX512F-FAST-NEXT:    vpermi2q %zmm1, %zmm4, %zmm5
+; AVX512F-FAST-NEXT:    vpternlogq $226, %zmm2, %zmm17, %zmm5
+; AVX512F-FAST-NEXT:    vpbroadcastq 24(%r8), %ymm1
+; AVX512F-FAST-NEXT:    vpbroadcastq 32(%r8), %ymm2
+; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm2, %zmm1, %zmm1
+; AVX512F-FAST-NEXT:    vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm5, %zmm1
+; AVX512F-FAST-NEXT:    vmovdqa64 %zmm1, 128(%r9)
+; AVX512F-FAST-NEXT:    vmovdqa64 %zmm3, 256(%r9)
 ; AVX512F-FAST-NEXT:    vmovdqa64 %zmm0, 64(%r9)
 ; AVX512F-FAST-NEXT:    vmovdqa64 %zmm10, (%r9)
-; AVX512F-FAST-NEXT:    vmovdqa64 %zmm18, 192(%r9)
+; AVX512F-FAST-NEXT:    vmovdqa64 %zmm19, 192(%r9)
 ; AVX512F-FAST-NEXT:    vzeroupper
 ; AVX512F-FAST-NEXT:    retq
 ;
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
index 3de19185ea05..0bb8e17e0ee4 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
@@ -2341,8 +2341,7 @@ define void @store_i16_stride7_vf16(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
 ; AVX512F-SLOW-NEXT:    vpshufb {{.*#+}} ymm10 = ymm2[u,u,u,u,u,u,u,u,u,u,14,15],zero,zero,ymm2[u,u,u,u,u,u,u,u,u,u,16,17],zero,zero,ymm2[u,u,u,u]
 ; AVX512F-SLOW-NEXT:    vporq %ymm5, %ymm10, %ymm19
 ; AVX512F-SLOW-NEXT:    vpbroadcastd 8(%rax), %ymm5
-; AVX512F-SLOW-NEXT:    vmovdqa {{.*#+}} ymm10 = [65535,65535,0,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535]
-; AVX512F-SLOW-NEXT:    vpandn %ymm5, %ymm10, %ymm5
+; AVX512F-SLOW-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm5, %ymm5
 ; AVX512F-SLOW-NEXT:    vpshufb {{.*#+}} ymm10 = ymm13[12,13,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm13[14,15,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm13[16,17,u,u]
 ; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm10, %zmm5, %zmm5
 ; AVX512F-SLOW-NEXT:    vpshufd {{.*#+}} ymm10 = ymm6[0,1,1,3,4,5,5,7]
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll
index 8ccb4ef56d9c..f727622682cf 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll
@@ -567,8 +567,8 @@ define void @store_i8_stride3_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
 ; AVX512BW-NEXT:    vinserti128 $1, %xmm0, %ymm1, %ymm3
 ; AVX512BW-NEXT:    vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm1[4,5,6,7]
 ; AVX512BW-NEXT:    vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],ymm2[2,3]
-; AVX512BW-NEXT:    vbroadcasti64x4 {{.*#+}} zmm2 = [0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5,0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5,0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5,0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5]
-; AVX512BW-NEXT:    # zmm2 = mem[0,1,2,3,0,1,2,3]
+; AVX512BW-NEXT:    vbroadcasti32x4 {{.*#+}} zmm2 = [0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5,0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5,0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5,0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5]
+; AVX512BW-NEXT:    # zmm2 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
 ; AVX512BW-NEXT:    vpshufb %ymm2, %ymm0, %ymm0
 ; AVX512BW-NEXT:    vinserti64x4 $1, %ymm1, %zmm3, %zmm1
 ; AVX512BW-NEXT:    vpshufb %zmm2, %zmm1, %zmm1
@@ -1086,8 +1086,8 @@ define void @store_i8_stride3_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
 ; AVX512BW-NEXT:    vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm1[4,5,6,7]
 ; AVX512BW-NEXT:    vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],ymm2[2,3]
 ; AVX512BW-NEXT:    vinserti64x4 $1, %ymm4, %zmm3, %zmm2
-; AVX512BW-NEXT:    vbroadcasti64x4 {{.*#+}} zmm3 = [0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5,0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5,0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5,0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5]
-; AVX512BW-NEXT:    # zmm3 = mem[0,1,2,3,0,1,2,3]
+; AVX512BW-NEXT:    vbroadcasti32x4 {{.*#+}} zmm3 = [0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5,0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5,0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5,0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5]
+; AVX512BW-NEXT:    # zmm3 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
 ; AVX512BW-NEXT:    vpshufb %zmm3, %zmm2, %zmm2
 ; AVX512BW-NEXT:    vinserti64x4 $1, %ymm6, %zmm5, %zmm4
 ; AVX512BW-NEXT:    vpshufb %zmm3, %zmm4, %zmm4
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
index 33f4e4b0f6d0..4174fde81747 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
@@ -3890,36 +3890,37 @@ define void @store_i8_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
 ; AVX512F-SLOW-NEXT:    vmovdqa {{.*#+}} ymm15 = [128,128,13,128,128,128,128,14,128,128,128,128,15,128,128,128,128,16,128,128,128,128,17,128,128,128,128,18,128,128,128,128]
 ; AVX512F-SLOW-NEXT:    vpshufb %ymm15, %ymm3, %ymm0
 ; AVX512F-SLOW-NEXT:    vmovdqa 32(%rdi), %ymm2
-; AVX512F-SLOW-NEXT:    vmovdqa {{.*#+}} ymm7 = <12,13,128,15,12,13,14,128,12,13,14,15,128,u,u,u,16,128,18,19,16,17,128,19,16,17,18,128,16,17,18,19>
-; AVX512F-SLOW-NEXT:    vpshufb %ymm7, %ymm2, %ymm1
+; AVX512F-SLOW-NEXT:    vmovdqa {{.*#+}} ymm9 = <12,13,128,15,12,13,14,128,12,13,14,15,128,u,u,u,16,128,18,19,16,17,128,19,16,17,18,128,16,17,18,19>
+; AVX512F-SLOW-NEXT:    vpshufb %ymm9, %ymm2, %ymm1
 ; AVX512F-SLOW-NEXT:    vpor %ymm0, %ymm1, %ymm0
 ; AVX512F-SLOW-NEXT:    vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
 ; AVX512F-SLOW-NEXT:    vmovdqa 32(%rdi), %xmm1
-; AVX512F-SLOW-NEXT:    vmovdqa {{.*#+}} xmm8 = <8,128,u,7,128,9,128,u,128,u,10,128,12,128,u,11>
-; AVX512F-SLOW-NEXT:    vpshufb %xmm8, %xmm1, %xmm0
-; AVX512F-SLOW-NEXT:    vmovdqa64 %xmm1, %xmm30
+; AVX512F-SLOW-NEXT:    vmovdqa {{.*#+}} xmm5 = <8,128,u,7,128,9,128,u,128,u,10,128,12,128,u,11>
+; AVX512F-SLOW-NEXT:    vpshufb %xmm5, %xmm1, %xmm0
+; AVX512F-SLOW-NEXT:    vmovdqa64 %xmm1, %xmm16
 ; AVX512F-SLOW-NEXT:    vmovdqa 32(%rsi), %xmm4
 ; AVX512F-SLOW-NEXT:    vmovdqa {{.*#+}} xmm14 = <128,8,u,128,7,128,9,u,11,u,128,10,128,12,u,128>
 ; AVX512F-SLOW-NEXT:    vpshufb %xmm14, %xmm4, %xmm1
 ; AVX512F-SLOW-NEXT:    vmovdqa64 %xmm4, %xmm31
 ; AVX512F-SLOW-NEXT:    vpor %xmm0, %xmm1, %xmm0
 ; AVX512F-SLOW-NEXT:    vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
-; AVX512F-SLOW-NEXT:    vmovdqa 32(%rcx), %ymm9
+; AVX512F-SLOW-NEXT:    vmovdqa 32(%rcx), %ymm8
 ; AVX512F-SLOW-NEXT:    vmovdqa {{.*#+}} ymm0 = [128,128,128,128,13,128,128,128,128,14,128,128,128,128,15,128,128,128,128,16,128,128,128,128,17,128,128,128,128,18,128,128]
-; AVX512F-SLOW-NEXT:    vpshufb %ymm0, %ymm9, %ymm4
+; AVX512F-SLOW-NEXT:    vpshufb %ymm0, %ymm8, %ymm4
 ; AVX512F-SLOW-NEXT:    vmovdqa 32(%rdx), %ymm11
 ; AVX512F-SLOW-NEXT:    vmovdqa {{.*#+}} ymm1 = <u,u,12,13,128,u,u,u,14,128,u,u,14,15,128,u,u,u,16,128,u,u,16,17,128,u,u,u,18,128,u,u>
 ; AVX512F-SLOW-NEXT:    vpshufb %ymm1, %ymm11, %ymm10
-; AVX512F-SLOW-NEXT:    vporq %ymm4, %ymm10, %ymm18
+; AVX512F-SLOW-NEXT:    vpor %ymm4, %ymm10, %ymm4
+; AVX512F-SLOW-NEXT:    vmovdqu %ymm4, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
 ; AVX512F-SLOW-NEXT:    vmovdqa 32(%rcx), %xmm13
-; AVX512F-SLOW-NEXT:    vmovdqa {{.*#+}} xmm5 = <128,6,128,8,u,128,7,128,9,128,11,u,128,10,128,12>
-; AVX512F-SLOW-NEXT:    vpshufb %xmm5, %xmm13, %xmm4
-; AVX512F-SLOW-NEXT:    vmovdqa64 %xmm5, %xmm25
+; AVX512F-SLOW-NEXT:    vmovdqa {{.*#+}} xmm6 = <128,6,128,8,u,128,7,128,9,128,11,u,128,10,128,12>
+; AVX512F-SLOW-NEXT:    vpshufb %xmm6, %xmm13, %xmm4
+; AVX512F-SLOW-NEXT:    vmovdqa64 %xmm6, %xmm25
 ; AVX512F-SLOW-NEXT:    vmovdqa 32(%rdx), %xmm10
-; AVX512F-SLOW-NEXT:    vmovdqa {{.*#+}} xmm5 = <6,128,8,128,u,7,128,9,128,11,128,u,10,128,12,128>
-; AVX512F-SLOW-NEXT:    vpshufb %xmm5, %xmm10, %xmm12
-; AVX512F-SLOW-NEXT:    vmovdqa64 %xmm5, %xmm26
-; AVX512F-SLOW-NEXT:    vporq %xmm4, %xmm12, %xmm19
+; AVX512F-SLOW-NEXT:    vmovdqa {{.*#+}} xmm6 = <6,128,8,128,u,7,128,9,128,11,128,u,10,128,12,128>
+; AVX512F-SLOW-NEXT:    vpshufb %xmm6, %xmm10, %xmm12
+; AVX512F-SLOW-NEXT:    vmovdqa64 %xmm6, %xmm26
+; AVX512F-SLOW-NEXT:    vporq %xmm4, %xmm12, %xmm20
 ; AVX512F-SLOW-NEXT:    vpshufb {{.*#+}} ymm4 = ymm3[11,u,u,10,u,12,u,u,u,u,13,u,15,u,u,14,27,u,u,26,u,28,u,u,u,u,29,u,31,u,u,30]
 ; AVX512F-SLOW-NEXT:    vpshufb {{.*#+}} ymm3 = ymm3[3,u,5,u,u,4,u,6,u,8,u,u,7,u,9,u,19,u,21,u,u,20,u,22,u,24,u,u,23,u,25,u]
 ; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm4, %zmm3, %zmm22
@@ -3927,31 +3928,31 @@ define void @store_i8_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
 ; AVX512F-SLOW-NEXT:    vpshufb {{.*#+}} ymm2 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm2[21],zero,zero,ymm2[20],zero,ymm2[22],zero,ymm2[24],zero,zero,ymm2[23],zero,ymm2[25],zero,zero
 ; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm3, %zmm2, %zmm23
 ; AVX512F-SLOW-NEXT:    vpshufb {{.*#+}} ymm2 = ymm11[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm11[27],zero,zero,ymm11[26],zero,ymm11[28],zero,ymm11[30],zero,zero,ymm11[29],zero,ymm11[31],zero,zero
-; AVX512F-SLOW-NEXT:    vpshufb {{.*#+}} ymm3 = ymm9[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm9[19],zero,ymm9[21],zero,zero,ymm9[20],zero,ymm9[22],zero,ymm9[24],zero,zero,ymm9[23],zero
+; AVX512F-SLOW-NEXT:    vpshufb {{.*#+}} ymm3 = ymm8[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm8[19],zero,ymm8[21],zero,zero,ymm8[20],zero,ymm8[22],zero,ymm8[24],zero,zero,ymm8[23],zero
 ; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm2, %zmm3, %zmm24
 ; AVX512F-SLOW-NEXT:    vmovdqa (%rcx), %ymm12
 ; AVX512F-SLOW-NEXT:    vpshufb %ymm0, %ymm12, %ymm0
 ; AVX512F-SLOW-NEXT:    vmovdqa (%rdx), %ymm6
 ; AVX512F-SLOW-NEXT:    vpshufb %ymm1, %ymm6, %ymm1
-; AVX512F-SLOW-NEXT:    vporq %ymm0, %ymm1, %ymm20
-; AVX512F-SLOW-NEXT:    vmovdqa (%rsi), %ymm5
-; AVX512F-SLOW-NEXT:    vpshufb %ymm15, %ymm5, %ymm2
+; AVX512F-SLOW-NEXT:    vporq %ymm0, %ymm1, %ymm19
+; AVX512F-SLOW-NEXT:    vmovdqa (%rsi), %ymm7
+; AVX512F-SLOW-NEXT:    vpshufb %ymm15, %ymm7, %ymm2
 ; AVX512F-SLOW-NEXT:    vmovdqa (%rdi), %ymm4
-; AVX512F-SLOW-NEXT:    vpshufb %ymm7, %ymm4, %ymm3
+; AVX512F-SLOW-NEXT:    vpshufb %ymm9, %ymm4, %ymm3
 ; AVX512F-SLOW-NEXT:    vporq %ymm2, %ymm3, %ymm21
 ; AVX512F-SLOW-NEXT:    vmovdqa (%rdi), %xmm0
-; AVX512F-SLOW-NEXT:    vpshufb %xmm8, %xmm0, %xmm2
-; AVX512F-SLOW-NEXT:    vmovdqa64 %xmm0, %xmm16
-; AVX512F-SLOW-NEXT:    vmovdqa (%rsi), %xmm7
-; AVX512F-SLOW-NEXT:    vpshufb %xmm14, %xmm7, %xmm3
-; AVX512F-SLOW-NEXT:    vporq %xmm2, %xmm3, %xmm27
+; AVX512F-SLOW-NEXT:    vpshufb %xmm5, %xmm0, %xmm3
+; AVX512F-SLOW-NEXT:    vmovdqa64 %xmm0, %xmm17
+; AVX512F-SLOW-NEXT:    vmovdqa (%rsi), %xmm5
+; AVX512F-SLOW-NEXT:    vpshufb %xmm14, %xmm5, %xmm9
+; AVX512F-SLOW-NEXT:    vporq %xmm3, %xmm9, %xmm27
 ; AVX512F-SLOW-NEXT:    vmovdqa (%rcx), %xmm1
 ; AVX512F-SLOW-NEXT:    vmovdqa64 %xmm25, %xmm0
 ; AVX512F-SLOW-NEXT:    vpshufb %xmm0, %xmm1, %xmm0
-; AVX512F-SLOW-NEXT:    vmovdqa64 %xmm1, %xmm17
-; AVX512F-SLOW-NEXT:    vmovdqa (%rdx), %xmm8
+; AVX512F-SLOW-NEXT:    vmovdqa64 %xmm1, %xmm18
+; AVX512F-SLOW-NEXT:    vmovdqa (%rdx), %xmm9
 ; AVX512F-SLOW-NEXT:    vmovdqa64 %xmm26, %xmm1
-; AVX512F-SLOW-NEXT:    vpshufb %xmm1, %xmm8, %xmm15
+; AVX512F-SLOW-NEXT:    vpshufb %xmm1, %xmm9, %xmm15
 ; AVX512F-SLOW-NEXT:    vporq %xmm0, %xmm15, %xmm29
 ; AVX512F-SLOW-NEXT:    vpshufd {{.*#+}} xmm0 = mem[1,1,2,2]
 ; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[0,1,1,1]
@@ -3965,10 +3966,11 @@ define void @store_i8_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
 ; AVX512F-SLOW-NEXT:    vpshufb %ymm1, %ymm0, %ymm1
 ; AVX512F-SLOW-NEXT:    vpshufd {{.*#+}} ymm0 = ymm0[0,2,1,1,4,6,5,5]
 ; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[2,3,3,2]
-; AVX512F-SLOW-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX512F-SLOW-NEXT:    vmovdqa64 {{.*#+}} zmm30 = [255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0]
+; AVX512F-SLOW-NEXT:    vpandnq %ymm0, %ymm30, %ymm0
 ; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm25
 ; AVX512F-SLOW-NEXT:    vpbroadcastq {{.*#+}} ymm0 = [9,14,11,0,13,10,15,12,9,14,11,0,13,10,15,12,9,14,11,0,13,10,15,12,9,14,11,0,13,10,15,12]
-; AVX512F-SLOW-NEXT:    vpshufb %ymm0, %ymm9, %ymm9
+; AVX512F-SLOW-NEXT:    vpshufb %ymm0, %ymm8, %ymm8
 ; AVX512F-SLOW-NEXT:    vpshufb {{.*#+}} ymm14 = ymm12[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm12[19],zero,ymm12[21],zero,zero,ymm12[20],zero,ymm12[22],zero,ymm12[24],zero,zero,ymm12[23],zero
 ; AVX512F-SLOW-NEXT:    vpshufb %ymm0, %ymm12, %ymm12
 ; AVX512F-SLOW-NEXT:    vbroadcasti128 {{.*#+}} ymm0 = [18,19,128,21,128,21,20,128,22,128,24,128,22,23,128,25,18,19,128,21,128,21,20,128,22,128,24,128,22,23,128,25]
@@ -3977,24 +3979,25 @@ define void @store_i8_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
 ; AVX512F-SLOW-NEXT:    vpshufb %ymm0, %ymm6, %ymm2
 ; AVX512F-SLOW-NEXT:    vpshufb {{.*#+}} ymm6 = ymm6[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm6[27],zero,zero,ymm6[26],zero,ymm6[28],zero,ymm6[30],zero,zero,ymm6[29],zero,ymm6[31],zero,zero
 ; AVX512F-SLOW-NEXT:    vpunpcklbw {{.*#+}} xmm10 = xmm13[0],xmm10[0],xmm13[1],xmm10[1],xmm13[2],xmm10[2],xmm13[3],xmm10[3],xmm13[4],xmm10[4],xmm13[5],xmm10[5],xmm13[6],xmm10[6],xmm13[7],xmm10[7]
-; AVX512F-SLOW-NEXT:    vpshufb {{.*#+}} ymm13 = ymm5[3,u,5,u,u,4,u,6,u,8,u,u,7,u,9,u,19,u,21,u,u,20,u,22,u,24,u,u,23,u,25,u]
-; AVX512F-SLOW-NEXT:    vpshufb {{.*#+}} ymm5 = ymm5[11,u,u,10,u,12,u,u,u,u,13,u,15,u,u,14,27,u,u,26,u,28,u,u,u,u,29,u,31,u,u,30]
+; AVX512F-SLOW-NEXT:    vpshufb {{.*#+}} ymm13 = ymm7[3,u,5,u,u,4,u,6,u,8,u,u,7,u,9,u,19,u,21,u,u,20,u,22,u,24,u,u,23,u,25,u]
+; AVX512F-SLOW-NEXT:    vpshufb {{.*#+}} ymm7 = ymm7[11,u,u,10,u,12,u,u,u,u,13,u,15,u,u,14,27,u,u,26,u,28,u,u,u,u,29,u,31,u,u,30]
 ; AVX512F-SLOW-NEXT:    vpshufb {{.*#+}} ymm0 = ymm4[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm4[21],zero,zero,ymm4[20],zero,ymm4[22],zero,ymm4[24],zero,zero,ymm4[23],zero,ymm4[25],zero,zero
 ; AVX512F-SLOW-NEXT:    vpshufb {{.*#+}} ymm3 = ymm4[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm4[26],zero,ymm4[28],zero,zero,ymm4[27],zero,ymm4[29],zero,ymm4[31],zero,zero,ymm4[30],zero
-; AVX512F-SLOW-NEXT:    vmovdqa64 %xmm30, %xmm1
+; AVX512F-SLOW-NEXT:    vmovdqa64 %xmm16, %xmm1
 ; AVX512F-SLOW-NEXT:    vmovdqa64 %xmm31, %xmm4
 ; AVX512F-SLOW-NEXT:    vpunpcklbw {{.*#+}} xmm4 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3],xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7]
 ; AVX512F-SLOW-NEXT:    vmovdqa64 {{.*#+}} zmm1 = <4,u,5,5,5,5,u,6,6,6,6,u,7,7,7,7>
-; AVX512F-SLOW-NEXT:    vpermd %zmm15, %zmm1, %zmm30
-; AVX512F-SLOW-NEXT:    vmovdqa64 (%r8), %zmm31
+; AVX512F-SLOW-NEXT:    vpermd %zmm15, %zmm1, %zmm31
+; AVX512F-SLOW-NEXT:    vmovdqa64 (%r8), %zmm16
 ; AVX512F-SLOW-NEXT:    vmovdqa64 {{.*#+}} zmm1 = <6,6,6,u,7,7,7,7,u,16,16,16,16,u,17,17>
-; AVX512F-SLOW-NEXT:    vpermi2d %zmm15, %zmm31, %zmm1
-; AVX512F-SLOW-NEXT:    vmovdqa64 %xmm16, %xmm15
-; AVX512F-SLOW-NEXT:    vpunpcklbw {{.*#+}} xmm7 = xmm15[0],xmm7[0],xmm15[1],xmm7[1],xmm15[2],xmm7[2],xmm15[3],xmm7[3],xmm15[4],xmm7[4],xmm15[5],xmm7[5],xmm15[6],xmm7[6],xmm15[7],xmm7[7]
+; AVX512F-SLOW-NEXT:    vpermi2d %zmm15, %zmm16, %zmm1
+; AVX512F-SLOW-NEXT:    vmovdqa64 %xmm17, %xmm15
+; AVX512F-SLOW-NEXT:    vpunpcklbw {{.*#+}} xmm5 = xmm15[0],xmm5[0],xmm15[1],xmm5[1],xmm15[2],xmm5[2],xmm15[3],xmm5[3],xmm15[4],xmm5[4],xmm15[5],xmm5[5],xmm15[6],xmm5[6],xmm15[7],xmm5[7]
 ; AVX512F-SLOW-NEXT:    vmovdqa {{.*#+}} xmm15 = <0,1,4,5,u,2,3,6,7,10,11,u,8,9,12,13>
 ; AVX512F-SLOW-NEXT:    vpshufb %xmm15, %xmm4, %xmm4
-; AVX512F-SLOW-NEXT:    vpshufb %xmm15, %xmm7, %xmm7
-; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm9 = ymm9[2,2,3,3]
+; AVX512F-SLOW-NEXT:    vpshufb %xmm15, %xmm5, %xmm5
+; AVX512F-SLOW-NEXT:    vinserti32x4 $2, %xmm27, %zmm5, %zmm5
+; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm8 = ymm8[2,2,3,3]
 ; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm11 = ymm11[2,2,3,3]
 ; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm14 = ymm14[2,2,3,3]
 ; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm2 = ymm2[2,2,3,3]
@@ -4002,65 +4005,64 @@ define void @store_i8_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
 ; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[2,2,3,3]
 ; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm12 = ymm12[2,2,3,3]
 ; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm6 = ymm6[2,2,3,3]
-; AVX512F-SLOW-NEXT:    vinserti32x4 $2, %xmm27, %zmm7, %zmm27
+; AVX512F-SLOW-NEXT:    vmovdqa64 %xmm18, %xmm15
+; AVX512F-SLOW-NEXT:    vpunpcklbw {{.*#+}} xmm9 = xmm15[0],xmm9[0],xmm15[1],xmm9[1],xmm15[2],xmm9[2],xmm15[3],xmm9[3],xmm15[4],xmm9[4],xmm15[5],xmm9[5],xmm15[6],xmm9[6],xmm15[7],xmm9[7]
 ; AVX512F-SLOW-NEXT:    vmovdqa {{.*#+}} xmm15 = <2,u,1,0,5,4,u,3,u,7,6,11,10,u,9,8>
 ; AVX512F-SLOW-NEXT:    vpshufb %xmm15, %xmm10, %xmm10
 ; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm10 = ymm10[0,0,1,1]
-; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm5 = ymm5[2,2,3,3]
+; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm7 = ymm7[2,2,3,3]
 ; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm3 = ymm3[2,2,3,3]
 ; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm4 = ymm4[0,0,1,1]
-; AVX512F-SLOW-NEXT:    vmovdqa64 %xmm17, %xmm7
-; AVX512F-SLOW-NEXT:    vpunpcklbw {{.*#+}} xmm8 = xmm7[0],xmm8[0],xmm7[1],xmm8[1],xmm7[2],xmm8[2],xmm7[3],xmm8[3],xmm7[4],xmm8[4],xmm7[5],xmm8[5],xmm7[6],xmm8[6],xmm7[7],xmm8[7]
-; AVX512F-SLOW-NEXT:    vpshufb %xmm15, %xmm8, %xmm8
-; AVX512F-SLOW-NEXT:    vinserti32x4 $2, %xmm29, %zmm8, %zmm8
+; AVX512F-SLOW-NEXT:    vpshufb %xmm15, %xmm9, %xmm9
+; AVX512F-SLOW-NEXT:    vinserti32x4 $2, %xmm29, %zmm9, %zmm9
 ; AVX512F-SLOW-NEXT:    vpermq $80, {{[-0-9]+}}(%r{{[sb]}}p), %ymm15 # 32-byte Folded Reload
 ; AVX512F-SLOW-NEXT:    # ymm15 = mem[0,0,1,1]
 ; AVX512F-SLOW-NEXT:    vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm15, %zmm15 # 32-byte Folded Reload
-; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm16 = ymm19[0,0,1,1]
-; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm18, %zmm16, %zmm16
-; AVX512F-SLOW-NEXT:    vmovdqa64 {{.*#+}} zmm17 = [255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0]
-; AVX512F-SLOW-NEXT:    vpternlogq $226, %zmm15, %zmm17, %zmm16
-; AVX512F-SLOW-NEXT:    vpternlogq $248, %zmm28, %zmm16, %zmm26
+; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm17 = ymm20[0,0,1,1]
+; AVX512F-SLOW-NEXT:    vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm17, %zmm17 # 32-byte Folded Reload
+; AVX512F-SLOW-NEXT:    vmovdqa64 {{.*#+}} zmm18 = [255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0]
+; AVX512F-SLOW-NEXT:    vpternlogq $226, %zmm15, %zmm18, %zmm17
+; AVX512F-SLOW-NEXT:    vpternlogq $248, %zmm28, %zmm17, %zmm26
+; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} zmm15 = zmm22[2,2,3,3,6,6,7,7]
+; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} zmm17 = zmm23[2,2,3,3,6,6,7,7]
+; AVX512F-SLOW-NEXT:    vmovdqa64 {{.*#+}} zmm20 = [18374966859431608575,18374966859431608575,18446463693966278400,18446463693966278400,72056498804555775,72056498804555775,18374967950370078975,18374967950370078975]
+; AVX512F-SLOW-NEXT:    vpternlogq $248, %zmm20, %zmm15, %zmm17
+; AVX512F-SLOW-NEXT:    vpandq %ymm20, %ymm8, %ymm8
+; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm8, %zmm11, %zmm8
+; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} zmm11 = zmm24[2,2,3,3,6,6,7,7]
+; AVX512F-SLOW-NEXT:    vporq %zmm11, %zmm8, %zmm8
+; AVX512F-SLOW-NEXT:    vmovdqa64 {{.*#+}} zmm11 = [0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255]
+; AVX512F-SLOW-NEXT:    vpternlogq $226, %zmm17, %zmm11, %zmm8
+; AVX512F-SLOW-NEXT:    vpternlogd $184, %zmm8, %zmm30, %zmm31
 ; AVX512F-SLOW-NEXT:    vpor %ymm2, %ymm14, %ymm2
-; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm2, %zmm20, %zmm2
-; AVX512F-SLOW-NEXT:    vmovdqa64 {{.*#+}} zmm14 = [18374966859431608575,18374966859431608575,18446463693966278400,18446463693966278400,72056498804555775,72056498804555775,18374967950370078975,18374967950370078975]
-; AVX512F-SLOW-NEXT:    vpternlogq $248, %ymm14, %ymm13, %ymm0
+; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm2, %zmm19, %zmm2
+; AVX512F-SLOW-NEXT:    vpternlogq $248, %ymm20, %ymm13, %ymm0
 ; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm0, %zmm21, %zmm0
-; AVX512F-SLOW-NEXT:    vpternlogq $226, %zmm2, %zmm17, %zmm0
-; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} zmm2 = zmm22[2,2,3,3,6,6,7,7]
-; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} zmm13 = zmm23[2,2,3,3,6,6,7,7]
-; AVX512F-SLOW-NEXT:    vpternlogq $248, %zmm14, %zmm2, %zmm13
-; AVX512F-SLOW-NEXT:    vpternlogq $248, %ymm14, %ymm12, %ymm6
-; AVX512F-SLOW-NEXT:    vpand %ymm14, %ymm9, %ymm2
-; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm2, %zmm11, %zmm2
-; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} zmm9 = zmm24[2,2,3,3,6,6,7,7]
-; AVX512F-SLOW-NEXT:    vporq %zmm9, %zmm2, %zmm2
-; AVX512F-SLOW-NEXT:    vmovdqa64 {{.*#+}} zmm9 = [0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255]
-; AVX512F-SLOW-NEXT:    vpternlogq $226, %zmm13, %zmm9, %zmm2
-; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm10, %zmm6, %zmm6
-; AVX512F-SLOW-NEXT:    vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm5, %ymm3
+; AVX512F-SLOW-NEXT:    vpternlogq $226, %zmm2, %zmm18, %zmm0
+; AVX512F-SLOW-NEXT:    vpternlogq $248, %ymm20, %ymm12, %ymm6
+; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm10, %zmm6, %zmm2
+; AVX512F-SLOW-NEXT:    vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm7, %ymm3
 ; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm4, %zmm3, %zmm3
-; AVX512F-SLOW-NEXT:    vpternlogq $226, %zmm6, %zmm9, %zmm3
-; AVX512F-SLOW-NEXT:    vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm30
+; AVX512F-SLOW-NEXT:    vpternlogq $226, %zmm2, %zmm11, %zmm3
 ; AVX512F-SLOW-NEXT:    vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm25
 ; AVX512F-SLOW-NEXT:    vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm1
-; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} zmm0 = zmm27[0,0,1,1,4,4,5,5]
-; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} zmm2 = zmm8[0,0,1,1,4,4,5,5]
+; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} zmm0 = zmm5[0,0,1,1,4,4,5,5]
+; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} zmm2 = zmm9[0,0,1,1,4,4,5,5]
 ; AVX512F-SLOW-NEXT:    vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm2
 ; AVX512F-SLOW-NEXT:    vmovdqa64 {{.*#+}} zmm0 = <u,0,0,0,0,u,1,1,1,1,u,2,2,2,2,u>
-; AVX512F-SLOW-NEXT:    vpermd %zmm31, %zmm0, %zmm0
+; AVX512F-SLOW-NEXT:    vpermd %zmm16, %zmm0, %zmm0
 ; AVX512F-SLOW-NEXT:    vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm0
 ; AVX512F-SLOW-NEXT:    vmovdqa64 %zmm25, 64(%r9)
 ; AVX512F-SLOW-NEXT:    vmovdqa64 %zmm0, (%r9)
 ; AVX512F-SLOW-NEXT:    vmovdqa64 %zmm1, 128(%r9)
-; AVX512F-SLOW-NEXT:    vmovdqa64 %zmm30, 256(%r9)
+; AVX512F-SLOW-NEXT:    vmovdqa64 %zmm31, 256(%r9)
 ; AVX512F-SLOW-NEXT:    vmovdqa64 %zmm26, 192(%r9)
 ; AVX512F-SLOW-NEXT:    vzeroupper
 ; AVX512F-SLOW-NEXT:    retq
 ;
 ; AVX512F-FAST-LABEL: store_i8_stride5_vf64:
 ; AVX512F-FAST:       # %bb.0:
-; AVX512F-FAST-NEXT:    pushq %rax
+; AVX512F-FAST-NEXT:    subq $24, %rsp
 ; AVX512F-FAST-NEXT:    vmovdqa 32(%rsi), %ymm3
 ; AVX512F-FAST-NEXT:    vmovdqa {{.*#+}} ymm8 = [128,128,13,128,128,128,128,14,128,128,128,128,15,128,128,128,128,16,128,128,128,128,17,128,128,128,128,18,128,128,128,128]
 ; AVX512F-FAST-NEXT:    vpshufb %ymm8, %ymm3, %ymm0
@@ -4069,14 +4071,14 @@ define void @store_i8_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
 ; AVX512F-FAST-NEXT:    vpshufb %ymm11, %ymm1, %ymm2
 ; AVX512F-FAST-NEXT:    vpor %ymm0, %ymm2, %ymm0
 ; AVX512F-FAST-NEXT:    vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
-; AVX512F-FAST-NEXT:    vmovdqa 32(%rdi), %xmm2
-; AVX512F-FAST-NEXT:    vmovdqa {{.*#+}} xmm6 = <8,128,u,7,128,9,128,u,128,u,10,128,12,128,u,11>
-; AVX512F-FAST-NEXT:    vpshufb %xmm6, %xmm2, %xmm0
-; AVX512F-FAST-NEXT:    vmovdqa64 %xmm2, %xmm19
+; AVX512F-FAST-NEXT:    vmovdqa 32(%rdi), %xmm0
+; AVX512F-FAST-NEXT:    vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; AVX512F-FAST-NEXT:    vmovdqa {{.*#+}} xmm5 = <8,128,u,7,128,9,128,u,128,u,10,128,12,128,u,11>
+; AVX512F-FAST-NEXT:    vpshufb %xmm5, %xmm0, %xmm0
 ; AVX512F-FAST-NEXT:    vmovdqa 32(%rsi), %xmm4
 ; AVX512F-FAST-NEXT:    vmovdqa {{.*#+}} xmm13 = <128,8,u,128,7,128,9,u,11,u,128,10,128,12,u,128>
 ; AVX512F-FAST-NEXT:    vpshufb %xmm13, %xmm4, %xmm2
-; AVX512F-FAST-NEXT:    vmovdqa64 %xmm4, %xmm18
+; AVX512F-FAST-NEXT:    vmovdqa64 %xmm4, %xmm19
 ; AVX512F-FAST-NEXT:    vpor %xmm0, %xmm2, %xmm0
 ; AVX512F-FAST-NEXT:    vmovdqu %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
 ; AVX512F-FAST-NEXT:    vmovdqa 32(%rcx), %ymm7
@@ -4092,9 +4094,9 @@ define void @store_i8_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
 ; AVX512F-FAST-NEXT:    vpshufb %xmm4, %xmm12, %xmm2
 ; AVX512F-FAST-NEXT:    vmovdqa64 %xmm4, %xmm25
 ; AVX512F-FAST-NEXT:    vmovdqa 32(%rdx), %xmm10
-; AVX512F-FAST-NEXT:    vmovdqa {{.*#+}} xmm5 = <6,128,8,128,u,7,128,9,128,11,128,u,10,128,12,128>
-; AVX512F-FAST-NEXT:    vpshufb %xmm5, %xmm10, %xmm4
-; AVX512F-FAST-NEXT:    vmovdqa64 %xmm5, %xmm26
+; AVX512F-FAST-NEXT:    vmovdqa {{.*#+}} xmm6 = <6,128,8,128,u,7,128,9,128,11,128,u,10,128,12,128>
+; AVX512F-FAST-NEXT:    vpshufb %xmm6, %xmm10, %xmm4
+; AVX512F-FAST-NEXT:    vmovdqa64 %xmm6, %xmm26
 ; AVX512F-FAST-NEXT:    vpor %xmm2, %xmm4, %xmm2
 ; AVX512F-FAST-NEXT:    vmovdqu %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
 ; AVX512F-FAST-NEXT:    vpshufb {{.*#+}} ymm2 = ymm3[11,u,u,10,u,12,u,u,u,u,13,u,15,u,u,14,27,u,u,26,u,28,u,u,u,u,29,u,31,u,u,30]
@@ -4104,140 +4106,139 @@ define void @store_i8_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
 ; AVX512F-FAST-NEXT:    vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm1[21],zero,zero,ymm1[20],zero,ymm1[22],zero,ymm1[24],zero,zero,ymm1[23],zero,ymm1[25],zero,zero
 ; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm2, %zmm1, %zmm22
 ; AVX512F-FAST-NEXT:    vpshufb {{.*#+}} ymm1 = ymm9[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm9[27],zero,zero,ymm9[26],zero,ymm9[28],zero,ymm9[30],zero,zero,ymm9[29],zero,ymm9[31],zero,zero
-; AVX512F-FAST-NEXT:    vbroadcasti128 {{.*#+}} ymm3 = [128,128,19,128,21,128,128,20,128,22,128,24,128,128,23,128,128,128,19,128,21,128,128,20,128,22,128,24,128,128,23,128]
-; AVX512F-FAST-NEXT:    # ymm3 = mem[0,1,0,1]
-; AVX512F-FAST-NEXT:    vpshufb %ymm3, %ymm7, %ymm2
-; AVX512F-FAST-NEXT:    vmovdqa64 %ymm3, %ymm31
+; AVX512F-FAST-NEXT:    vpshufb {{.*#+}} ymm2 = ymm7[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm7[19],zero,ymm7[21],zero,zero,ymm7[20],zero,ymm7[22],zero,ymm7[24],zero,zero,ymm7[23],zero
 ; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm1, %zmm2, %zmm23
-; AVX512F-FAST-NEXT:    vmovdqa (%rcx), %ymm5
-; AVX512F-FAST-NEXT:    vpshufb %ymm0, %ymm5, %ymm0
+; AVX512F-FAST-NEXT:    vmovdqa (%rcx), %ymm4
+; AVX512F-FAST-NEXT:    vpshufb %ymm0, %ymm4, %ymm0
 ; AVX512F-FAST-NEXT:    vmovdqa (%rdx), %ymm14
 ; AVX512F-FAST-NEXT:    vpshufb %ymm15, %ymm14, %ymm1
 ; AVX512F-FAST-NEXT:    vporq %ymm0, %ymm1, %ymm24
 ; AVX512F-FAST-NEXT:    vmovdqa (%rsi), %ymm15
 ; AVX512F-FAST-NEXT:    vpshufb %ymm8, %ymm15, %ymm0
-; AVX512F-FAST-NEXT:    vmovdqa (%rdi), %ymm4
-; AVX512F-FAST-NEXT:    vpshufb %ymm11, %ymm4, %ymm1
+; AVX512F-FAST-NEXT:    vmovdqa (%rdi), %ymm6
+; AVX512F-FAST-NEXT:    vpshufb %ymm11, %ymm6, %ymm1
 ; AVX512F-FAST-NEXT:    vporq %ymm0, %ymm1, %ymm20
-; AVX512F-FAST-NEXT:    vmovdqa (%rdi), %xmm1
-; AVX512F-FAST-NEXT:    vpshufb %xmm6, %xmm1, %xmm0
-; AVX512F-FAST-NEXT:    vmovdqa64 %xmm1, %xmm16
+; AVX512F-FAST-NEXT:    vmovdqa (%rdi), %xmm0
+; AVX512F-FAST-NEXT:    vpshufb %xmm5, %xmm0, %xmm1
+; AVX512F-FAST-NEXT:    vmovdqa64 %xmm0, %xmm16
 ; AVX512F-FAST-NEXT:    vmovdqa (%rsi), %xmm3
 ; AVX512F-FAST-NEXT:    vpshufb %xmm13, %xmm3, %xmm2
-; AVX512F-FAST-NEXT:    vporq %xmm0, %xmm2, %xmm28
+; AVX512F-FAST-NEXT:    vporq %xmm1, %xmm2, %xmm28
 ; AVX512F-FAST-NEXT:    vmovdqa (%rcx), %xmm1
 ; AVX512F-FAST-NEXT:    vmovdqa64 %xmm25, %xmm0
-; AVX512F-FAST-NEXT:    vpshufb %xmm0, %xmm1, %xmm0
+; AVX512F-FAST-NEXT:    vpshufb %xmm0, %xmm1, %xmm8
+; AVX512F-FAST-NEXT:    vmovdqa64 %xmm1, %xmm18
+; AVX512F-FAST-NEXT:    vmovdqa (%rdx), %xmm1
+; AVX512F-FAST-NEXT:    vmovdqa64 %xmm26, %xmm0
+; AVX512F-FAST-NEXT:    vpshufb %xmm0, %xmm1, %xmm11
 ; AVX512F-FAST-NEXT:    vmovdqa64 %xmm1, %xmm17
-; AVX512F-FAST-NEXT:    vmovdqa (%rdx), %xmm11
-; AVX512F-FAST-NEXT:    vmovdqa64 %xmm26, %xmm1
-; AVX512F-FAST-NEXT:    vpshufb %xmm1, %xmm11, %xmm8
-; AVX512F-FAST-NEXT:    vporq %xmm0, %xmm8, %xmm29
-; AVX512F-FAST-NEXT:    vmovdqa {{.*#+}} ymm0 = [1,1,2,2,2,2,2,2]
+; AVX512F-FAST-NEXT:    vporq %xmm8, %xmm11, %xmm29
+; AVX512F-FAST-NEXT:    vmovdqa {{.*#+}} ymm11 = [1,1,2,2,2,2,2,2]
 ; AVX512F-FAST-NEXT:    vmovdqa 32(%r8), %ymm8
-; AVX512F-FAST-NEXT:    vpermd %ymm8, %ymm0, %ymm0
+; AVX512F-FAST-NEXT:    vpermd %ymm8, %ymm11, %ymm11
 ; AVX512F-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm25 = [255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0,255]
-; AVX512F-FAST-NEXT:    vpandnq %ymm0, %ymm25, %ymm0
-; AVX512F-FAST-NEXT:    vmovdqa {{.*#+}} ymm1 = [12,128,128,128,128,13,128,128,128,128,14,128,128,128,128,15,128,128,128,128,16,128,128,128,128,17,128,128,128,128,18,128]
-; AVX512F-FAST-NEXT:    vpshufb %ymm1, %ymm8, %ymm13
-; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm13, %zmm0, %zmm26
-; AVX512F-FAST-NEXT:    vmovdqa (%r8), %ymm2
-; AVX512F-FAST-NEXT:    vpshufb %ymm1, %ymm2, %ymm1
-; AVX512F-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm30 = <4,u,5,5,5,5,u,6,30,30,30,u,31,31,31,31>
-; AVX512F-FAST-NEXT:    vpermd %ymm2, %ymm30, %ymm27
-; AVX512F-FAST-NEXT:    vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm27, %ymm27
-; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm27, %zmm1, %zmm27
-; AVX512F-FAST-NEXT:    vpbroadcastq {{.*#+}} ymm1 = [9,14,11,0,13,10,15,12,9,14,11,0,13,10,15,12,9,14,11,0,13,10,15,12,9,14,11,0,13,10,15,12]
-; AVX512F-FAST-NEXT:    vpshufb %ymm1, %ymm7, %ymm7
-; AVX512F-FAST-NEXT:    vmovdqa64 %ymm31, %ymm0
-; AVX512F-FAST-NEXT:    vpshufb %ymm0, %ymm5, %ymm13
-; AVX512F-FAST-NEXT:    vpshufb %ymm1, %ymm5, %ymm6
-; AVX512F-FAST-NEXT:    vbroadcasti128 {{.*#+}} ymm5 = [18,19,128,21,128,21,20,128,22,128,24,128,22,23,128,25,18,19,128,21,128,21,20,128,22,128,24,128,22,23,128,25]
-; AVX512F-FAST-NEXT:    # ymm5 = mem[0,1,0,1]
-; AVX512F-FAST-NEXT:    vpshufb %ymm5, %ymm9, %ymm9
-; AVX512F-FAST-NEXT:    vpshufb %ymm5, %ymm14, %ymm5
+; AVX512F-FAST-NEXT:    vpandnq %ymm11, %ymm25, %ymm11
+; AVX512F-FAST-NEXT:    vmovdqa {{.*#+}} ymm0 = [12,128,128,128,128,13,128,128,128,128,14,128,128,128,128,15,128,128,128,128,16,128,128,128,128,17,128,128,128,128,18,128]
+; AVX512F-FAST-NEXT:    vpshufb %ymm0, %ymm8, %ymm13
+; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm13, %zmm11, %zmm26
+; AVX512F-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm31 = <4,u,5,5,5,5,u,6,30,30,30,u,31,31,31,31>
+; AVX512F-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm30 = [255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0,255,255,255,255,0]
+; AVX512F-FAST-NEXT:    vmovdqa (%r8), %ymm11
+; AVX512F-FAST-NEXT:    vpermd %ymm11, %ymm31, %ymm27
+; AVX512F-FAST-NEXT:    vpandnq %ymm27, %ymm30, %ymm27
+; AVX512F-FAST-NEXT:    vpshufb %ymm0, %ymm11, %ymm0
+; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm27, %zmm0, %zmm27
+; AVX512F-FAST-NEXT:    vpbroadcastq {{.*#+}} ymm0 = [9,14,11,0,13,10,15,12,9,14,11,0,13,10,15,12,9,14,11,0,13,10,15,12,9,14,11,0,13,10,15,12]
+; AVX512F-FAST-NEXT:    vpshufb %ymm0, %ymm7, %ymm7
+; AVX512F-FAST-NEXT:    vpshufb {{.*#+}} ymm13 = ymm4[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm4[19],zero,ymm4[21],zero,zero,ymm4[20],zero,ymm4[22],zero,ymm4[24],zero,zero,ymm4[23],zero
+; AVX512F-FAST-NEXT:    vpshufb %ymm0, %ymm4, %ymm5
+; AVX512F-FAST-NEXT:    vbroadcasti128 {{.*#+}} ymm0 = [18,19,128,21,128,21,20,128,22,128,24,128,22,23,128,25,18,19,128,21,128,21,20,128,22,128,24,128,22,23,128,25]
+; AVX512F-FAST-NEXT:    # ymm0 = mem[0,1,0,1]
+; AVX512F-FAST-NEXT:    vpshufb %ymm0, %ymm9, %ymm9
+; AVX512F-FAST-NEXT:    vpshufb %ymm0, %ymm14, %ymm4
 ; AVX512F-FAST-NEXT:    vpshufb {{.*#+}} ymm14 = ymm14[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm14[27],zero,zero,ymm14[26],zero,ymm14[28],zero,ymm14[30],zero,zero,ymm14[29],zero,ymm14[31],zero,zero
 ; AVX512F-FAST-NEXT:    vpunpcklbw {{.*#+}} xmm10 = xmm12[0],xmm10[0],xmm12[1],xmm10[1],xmm12[2],xmm10[2],xmm12[3],xmm10[3],xmm12[4],xmm10[4],xmm12[5],xmm10[5],xmm12[6],xmm10[6],xmm12[7],xmm10[7]
 ; AVX512F-FAST-NEXT:    vpshufb {{.*#+}} ymm12 = ymm15[3,u,5,u,u,4,u,6,u,8,u,u,7,u,9,u,19,u,21,u,u,20,u,22,u,24,u,u,23,u,25,u]
 ; AVX512F-FAST-NEXT:    vpshufb {{.*#+}} ymm15 = ymm15[11,u,u,10,u,12,u,u,u,u,13,u,15,u,u,14,27,u,u,26,u,28,u,u,u,u,29,u,31,u,u,30]
-; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm31 = ymm7[2,2,3,3]
-; AVX512F-FAST-NEXT:    vpshufb {{.*#+}} ymm7 = ymm4[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm4[21],zero,zero,ymm4[20],zero,ymm4[22],zero,ymm4[24],zero,zero,ymm4[23],zero,ymm4[25],zero,zero
-; AVX512F-FAST-NEXT:    vpshufb {{.*#+}} ymm4 = ymm4[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm4[26],zero,ymm4[28],zero,zero,ymm4[27],zero,ymm4[29],zero,ymm4[31],zero,zero,ymm4[30],zero
-; AVX512F-FAST-NEXT:    vmovdqa64 %xmm19, %xmm0
-; AVX512F-FAST-NEXT:    vmovdqa64 %xmm18, %xmm1
+; AVX512F-FAST-NEXT:    vpshufb {{.*#+}} ymm2 = ymm6[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm6[21],zero,zero,ymm6[20],zero,ymm6[22],zero,ymm6[24],zero,zero,ymm6[23],zero,ymm6[25],zero,zero
+; AVX512F-FAST-NEXT:    vpshufb {{.*#+}} ymm6 = ymm6[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm6[26],zero,ymm6[28],zero,zero,ymm6[27],zero,ymm6[29],zero,ymm6[31],zero,zero,ymm6[30],zero
+; AVX512F-FAST-NEXT:    vmovdqa64 %xmm19, %xmm1
+; AVX512F-FAST-NEXT:    vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
 ; AVX512F-FAST-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
 ; AVX512F-FAST-NEXT:    vmovdqa64 %xmm16, %xmm1
 ; AVX512F-FAST-NEXT:    vpunpcklbw {{.*#+}} xmm3 = xmm1[0],xmm3[0],xmm1[1],xmm3[1],xmm1[2],xmm3[2],xmm1[3],xmm3[3],xmm1[4],xmm3[4],xmm1[5],xmm3[5],xmm1[6],xmm3[6],xmm1[7],xmm3[7]
 ; AVX512F-FAST-NEXT:    vmovdqa {{.*#+}} xmm1 = <0,1,4,5,u,2,3,6,7,10,11,u,8,9,12,13>
 ; AVX512F-FAST-NEXT:    vpshufb %xmm1, %xmm0, %xmm0
 ; AVX512F-FAST-NEXT:    vpshufb %xmm1, %xmm3, %xmm1
-; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm3 = ymm9[2,2,3,3]
+; AVX512F-FAST-NEXT:    vinserti32x4 $2, %xmm28, %zmm1, %zmm28
+; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm1 = ymm7[2,2,3,3]
+; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm7 = ymm9[2,2,3,3]
 ; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm9 = ymm13[2,2,3,3]
-; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm5 = ymm5[2,2,3,3]
+; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm4 = ymm4[2,2,3,3]
 ; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm12 = ymm12[2,2,3,3]
-; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm7 = ymm7[2,2,3,3]
-; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm6 = ymm6[2,2,3,3]
-; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm13 = ymm14[2,2,3,3]
-; AVX512F-FAST-NEXT:    vinserti32x4 $2, %xmm28, %zmm1, %zmm18
-; AVX512F-FAST-NEXT:    vmovdqa {{.*#+}} xmm14 = <2,u,1,0,5,4,u,3,u,7,6,11,10,u,9,8>
-; AVX512F-FAST-NEXT:    vpshufb %xmm14, %xmm10, %xmm10
+; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm2 = ymm2[2,2,3,3]
+; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm13 = ymm5[2,2,3,3]
+; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm14 = ymm14[2,2,3,3]
+; AVX512F-FAST-NEXT:    vmovdqa64 %xmm18, %xmm3
+; AVX512F-FAST-NEXT:    vmovdqa64 %xmm17, %xmm5
+; AVX512F-FAST-NEXT:    vpunpcklbw {{.*#+}} xmm5 = xmm3[0],xmm5[0],xmm3[1],xmm5[1],xmm3[2],xmm5[2],xmm3[3],xmm5[3],xmm3[4],xmm5[4],xmm3[5],xmm5[5],xmm3[6],xmm5[6],xmm3[7],xmm5[7]
+; AVX512F-FAST-NEXT:    vmovdqa {{.*#+}} xmm3 = <2,u,1,0,5,4,u,3,u,7,6,11,10,u,9,8>
+; AVX512F-FAST-NEXT:    vpshufb %xmm3, %xmm10, %xmm10
 ; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm10 = ymm10[0,0,1,1]
 ; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm15 = ymm15[2,2,3,3]
-; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm4 = ymm4[2,2,3,3]
+; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm6 = ymm6[2,2,3,3]
 ; AVX512F-FAST-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[0,0,1,1]
-; AVX512F-FAST-NEXT:    vmovdqa64 %xmm17, %xmm1
-; AVX512F-FAST-NEXT:    vpunpcklbw {{.*#+}} xmm11 = xmm1[0],xmm11[0],xmm1[1],xmm11[1],xmm1[2],xmm11[2],xmm1[3],xmm11[3],xmm1[4],xmm11[4],xmm1[5],xmm11[5],xmm1[6],xmm11[6],xmm1[7],xmm11[7]
-; AVX512F-FAST-NEXT:    vpshufb %xmm14, %xmm11, %xmm11
-; AVX512F-FAST-NEXT:    vinserti32x4 $2, %xmm29, %zmm11, %zmm11
-; AVX512F-FAST-NEXT:    vmovdqa64 (%r8), %zmm14
-; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm2, %zmm14, %zmm2
+; AVX512F-FAST-NEXT:    vpshufb %xmm3, %xmm5, %xmm3
+; AVX512F-FAST-NEXT:    vinserti32x4 $2, %xmm29, %zmm3, %zmm3
+; AVX512F-FAST-NEXT:    vmovdqa64 (%r8), %zmm5
+; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm11, %zmm5, %zmm11
 ; AVX512F-FAST-NEXT:    vpermq {{.*#+}} zmm21 = zmm21[2,2,3,3,6,6,7,7]
 ; AVX512F-FAST-NEXT:    vpermq {{.*#+}} zmm22 = zmm22[2,2,3,3,6,6,7,7]
-; AVX512F-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm28 = [18374966859431608575,18374966859431608575,18446463693966278400,18446463693966278400,72056498804555775,72056498804555775,18374967950370078975,18374967950370078975]
-; AVX512F-FAST-NEXT:    vpternlogq $248, %zmm28, %zmm21, %zmm22
-; AVX512F-FAST-NEXT:    vpandq %ymm28, %ymm31, %ymm21
-; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm21, %zmm3, %zmm3
-; AVX512F-FAST-NEXT:    vpermq {{.*#+}} zmm21 = zmm23[2,2,3,3,6,6,7,7]
-; AVX512F-FAST-NEXT:    vporq %zmm21, %zmm3, %zmm3
-; AVX512F-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm21 = [0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255]
-; AVX512F-FAST-NEXT:    vpternlogq $226, %zmm22, %zmm21, %zmm3
-; AVX512F-FAST-NEXT:    vpermt2d %zmm14, %zmm30, %zmm8
-; AVX512F-FAST-NEXT:    vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm8
+; AVX512F-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm29 = [18374966859431608575,18374966859431608575,18446463693966278400,18446463693966278400,72056498804555775,72056498804555775,18374967950370078975,18374967950370078975]
+; AVX512F-FAST-NEXT:    vpternlogq $248, %zmm29, %zmm21, %zmm22
+; AVX512F-FAST-NEXT:    vpandq %ymm29, %ymm1, %ymm1
+; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm1, %zmm7, %zmm1
+; AVX512F-FAST-NEXT:    vpermq {{.*#+}} zmm7 = zmm23[2,2,3,3,6,6,7,7]
+; AVX512F-FAST-NEXT:    vporq %zmm7, %zmm1, %zmm1
+; AVX512F-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm7 = [0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255]
+; AVX512F-FAST-NEXT:    vpternlogq $226, %zmm22, %zmm7, %zmm1
+; AVX512F-FAST-NEXT:    vpermt2d %zmm5, %zmm31, %zmm8
+; AVX512F-FAST-NEXT:    vpternlogd $184, %zmm1, %zmm30, %zmm8
 ; AVX512F-FAST-NEXT:    vmovdqa64 %zmm8, 256(%r9)
-; AVX512F-FAST-NEXT:    vpermq $80, {{[-0-9]+}}(%r{{[sb]}}p), %ymm3 # 32-byte Folded Reload
-; AVX512F-FAST-NEXT:    # ymm3 = mem[0,0,1,1]
-; AVX512F-FAST-NEXT:    vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm3, %zmm3 # 32-byte Folded Reload
+; AVX512F-FAST-NEXT:    vpermq $80, {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Folded Reload
+; AVX512F-FAST-NEXT:    # ymm1 = mem[0,0,1,1]
+; AVX512F-FAST-NEXT:    vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm1, %zmm1 # 32-byte Folded Reload
 ; AVX512F-FAST-NEXT:    vpermq $80, {{[-0-9]+}}(%r{{[sb]}}p), %ymm8 # 32-byte Folded Reload
 ; AVX512F-FAST-NEXT:    # ymm8 = mem[0,0,1,1]
 ; AVX512F-FAST-NEXT:    vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm8, %zmm8 # 32-byte Folded Reload
 ; AVX512F-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm16 = [255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0,0,255,255,255,0]
-; AVX512F-FAST-NEXT:    vpternlogq $226, %zmm3, %zmm16, %zmm8
+; AVX512F-FAST-NEXT:    vpternlogq $226, %zmm1, %zmm16, %zmm8
 ; AVX512F-FAST-NEXT:    vpternlogq $248, %zmm25, %zmm8, %zmm26
-; AVX512F-FAST-NEXT:    vpor %ymm5, %ymm9, %ymm3
-; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm3, %zmm24, %zmm3
-; AVX512F-FAST-NEXT:    vpternlogq $248, %ymm28, %ymm12, %ymm7
-; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm7, %zmm20, %zmm5
-; AVX512F-FAST-NEXT:    vpternlogq $226, %zmm3, %zmm16, %zmm5
-; AVX512F-FAST-NEXT:    vpternlogq $248, %ymm28, %ymm6, %ymm13
-; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm10, %zmm13, %zmm3
-; AVX512F-FAST-NEXT:    vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm15, %ymm4
-; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm0, %zmm4, %zmm0
-; AVX512F-FAST-NEXT:    vpternlogq $226, %zmm3, %zmm21, %zmm0
-; AVX512F-FAST-NEXT:    vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm5, %zmm27
-; AVX512F-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm3 = <6,6,6,u,7,7,7,7,u,8,8,8,8,u,9,9>
-; AVX512F-FAST-NEXT:    vpermd %zmm14, %zmm3, %zmm3
-; AVX512F-FAST-NEXT:    vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm3
-; AVX512F-FAST-NEXT:    vpermq {{.*#+}} zmm0 = zmm18[0,0,1,1,4,4,5,5]
-; AVX512F-FAST-NEXT:    vpermq {{.*#+}} zmm1 = zmm11[0,0,1,1,4,4,5,5]
-; AVX512F-FAST-NEXT:    vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1
+; AVX512F-FAST-NEXT:    vpor %ymm4, %ymm9, %ymm1
+; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm1, %zmm24, %zmm1
+; AVX512F-FAST-NEXT:    vpternlogq $248, %ymm29, %ymm12, %ymm2
+; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm2, %zmm20, %zmm2
+; AVX512F-FAST-NEXT:    vpternlogq $226, %zmm1, %zmm16, %zmm2
+; AVX512F-FAST-NEXT:    vpternlogq $248, %ymm29, %ymm13, %ymm14
+; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm10, %zmm14, %zmm1
+; AVX512F-FAST-NEXT:    vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm15, %ymm6
+; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm0, %zmm6, %zmm0
+; AVX512F-FAST-NEXT:    vpternlogq $226, %zmm1, %zmm7, %zmm0
+; AVX512F-FAST-NEXT:    vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm27
+; AVX512F-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm1 = <6,6,6,u,7,7,7,7,u,8,8,8,8,u,9,9>
+; AVX512F-FAST-NEXT:    vpermd %zmm5, %zmm1, %zmm1
+; AVX512F-FAST-NEXT:    vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1
+; AVX512F-FAST-NEXT:    vpermq {{.*#+}} zmm0 = zmm28[0,0,1,1,4,4,5,5]
+; AVX512F-FAST-NEXT:    vpermq {{.*#+}} zmm2 = zmm3[0,0,1,1,4,4,5,5]
+; AVX512F-FAST-NEXT:    vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm2
 ; AVX512F-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm0 = <u,0,0,0,0,u,1,1,9,9,u,10,10,10,10,u>
-; AVX512F-FAST-NEXT:    vpermd %zmm2, %zmm0, %zmm0
-; AVX512F-FAST-NEXT:    vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
+; AVX512F-FAST-NEXT:    vpermd %zmm11, %zmm0, %zmm0
+; AVX512F-FAST-NEXT:    vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm0
 ; AVX512F-FAST-NEXT:    vmovdqa64 %zmm27, 64(%r9)
 ; AVX512F-FAST-NEXT:    vmovdqa64 %zmm0, (%r9)
-; AVX512F-FAST-NEXT:    vmovdqa64 %zmm3, 128(%r9)
+; AVX512F-FAST-NEXT:    vmovdqa64 %zmm1, 128(%r9)
 ; AVX512F-FAST-NEXT:    vmovdqa64 %zmm26, 192(%r9)
-; AVX512F-FAST-NEXT:    popq %rax
+; AVX512F-FAST-NEXT:    addq $24, %rsp
 ; AVX512F-FAST-NEXT:    vzeroupper
 ; AVX512F-FAST-NEXT:    retq
 ;
@@ -4424,37 +4425,37 @@ define void @store_i8_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
 ; AVX512BW-FAST-LABEL: store_i8_stride5_vf64:
 ; AVX512BW-FAST:       # %bb.0:
 ; AVX512BW-FAST-NEXT:    vmovdqa64 (%r8), %zmm5
-; AVX512BW-FAST-NEXT:    vmovdqa64 32(%rdx), %ymm21
+; AVX512BW-FAST-NEXT:    vmovdqa64 32(%rdx), %ymm20
 ; AVX512BW-FAST-NEXT:    vmovdqa {{.*#+}} ymm1 = [128,128,12,13,128,128,128,128,14,128,128,128,14,15,128,128,128,128,16,128,128,128,16,17,128,128,128,128,18,128,128,128]
-; AVX512BW-FAST-NEXT:    vpshufb %ymm1, %ymm21, %ymm0
+; AVX512BW-FAST-NEXT:    vpshufb %ymm1, %ymm20, %ymm0
 ; AVX512BW-FAST-NEXT:    vmovdqa 32(%rcx), %ymm13
 ; AVX512BW-FAST-NEXT:    vmovdqa {{.*#+}} ymm2 = [128,128,128,128,13,128,128,128,128,14,128,128,128,128,15,128,128,128,128,16,128,128,128,128,17,128,128,128,128,18,128,128]
 ; AVX512BW-FAST-NEXT:    vpshufb %ymm2, %ymm13, %ymm3
 ; AVX512BW-FAST-NEXT:    vpor %ymm0, %ymm3, %ymm0
 ; AVX512BW-FAST-NEXT:    vmovdqa (%rcx), %xmm6
-; AVX512BW-FAST-NEXT:    vmovdqa64 32(%rcx), %xmm18
+; AVX512BW-FAST-NEXT:    vmovdqa64 32(%rcx), %xmm17
 ; AVX512BW-FAST-NEXT:    vmovdqa {{.*#+}} xmm8 = <128,6,128,8,u,128,7,128,9,128,11,u,128,10,128,12>
-; AVX512BW-FAST-NEXT:    vpshufb %xmm8, %xmm18, %xmm3
+; AVX512BW-FAST-NEXT:    vpshufb %xmm8, %xmm17, %xmm3
 ; AVX512BW-FAST-NEXT:    vmovdqa (%rdx), %xmm7
-; AVX512BW-FAST-NEXT:    vmovdqa64 32(%rdx), %xmm20
+; AVX512BW-FAST-NEXT:    vmovdqa64 32(%rdx), %xmm19
 ; AVX512BW-FAST-NEXT:    vmovdqa {{.*#+}} xmm10 = <6,128,8,128,u,7,128,9,128,11,128,u,10,128,12,128>
-; AVX512BW-FAST-NEXT:    vpshufb %xmm10, %xmm20, %xmm4
+; AVX512BW-FAST-NEXT:    vpshufb %xmm10, %xmm19, %xmm4
 ; AVX512BW-FAST-NEXT:    vpor %xmm3, %xmm4, %xmm3
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm3 = ymm3[0,0,1,1]
 ; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm0, %zmm3, %zmm0
 ; AVX512BW-FAST-NEXT:    vmovdqa (%rdi), %xmm9
-; AVX512BW-FAST-NEXT:    vmovdqa64 32(%rdi), %xmm17
+; AVX512BW-FAST-NEXT:    vmovdqa64 32(%rdi), %xmm16
 ; AVX512BW-FAST-NEXT:    vmovdqa {{.*#+}} xmm12 = <8,128,u,7,128,9,128,u,128,u,10,128,12,128,u,11>
-; AVX512BW-FAST-NEXT:    vpshufb %xmm12, %xmm17, %xmm3
+; AVX512BW-FAST-NEXT:    vpshufb %xmm12, %xmm16, %xmm3
 ; AVX512BW-FAST-NEXT:    vmovdqa (%rsi), %xmm11
-; AVX512BW-FAST-NEXT:    vmovdqa64 32(%rsi), %xmm19
+; AVX512BW-FAST-NEXT:    vmovdqa64 32(%rsi), %xmm18
 ; AVX512BW-FAST-NEXT:    vmovdqa {{.*#+}} xmm14 = <128,8,u,128,7,128,9,u,11,u,128,10,128,12,u,128>
-; AVX512BW-FAST-NEXT:    vpshufb %xmm14, %xmm19, %xmm4
+; AVX512BW-FAST-NEXT:    vpshufb %xmm14, %xmm18, %xmm4
 ; AVX512BW-FAST-NEXT:    vpor %xmm3, %xmm4, %xmm3
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm15 = ymm3[0,0,1,1]
-; AVX512BW-FAST-NEXT:    vmovdqa64 32(%rdi), %ymm16
+; AVX512BW-FAST-NEXT:    vmovdqa64 32(%rdi), %ymm21
 ; AVX512BW-FAST-NEXT:    vmovdqa {{.*#+}} ymm3 = <3,3,3,u,4,4,4,4>
-; AVX512BW-FAST-NEXT:    vpermd %ymm16, %ymm3, %ymm22
+; AVX512BW-FAST-NEXT:    vpermd %ymm21, %ymm3, %ymm22
 ; AVX512BW-FAST-NEXT:    vmovdqa64 32(%rsi), %ymm23
 ; AVX512BW-FAST-NEXT:    vpbroadcastq {{.*#+}} ymm4 = [0,0,13,2,15,0,1,14,0,0,13,2,15,0,1,14,0,0,13,2,15,0,1,14,0,0,13,2,15,0,1,14]
 ; AVX512BW-FAST-NEXT:    movl $138547332, %eax # imm = 0x8421084
@@ -4464,80 +4465,77 @@ define void @store_i8_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
 ; AVX512BW-FAST-NEXT:    movabsq $-8330787646191410408, %rax # imm = 0x8C6318C6318C6318
 ; AVX512BW-FAST-NEXT:    kmovq %rax, %k2
 ; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm15, %zmm0 {%k2}
-; AVX512BW-FAST-NEXT:    vmovdqa64 32(%r8), %ymm24
+; AVX512BW-FAST-NEXT:    vmovdqa64 32(%r8), %ymm22
 ; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm15 = <1,1,2,2,2,2,2,2,27,27,27,27,u,28,28,28>
-; AVX512BW-FAST-NEXT:    vpermi2d %zmm5, %zmm24, %zmm15
+; AVX512BW-FAST-NEXT:    vpermi2d %zmm5, %zmm22, %zmm15
 ; AVX512BW-FAST-NEXT:    movabsq $4760450083537948804, %rax # imm = 0x4210842108421084
 ; AVX512BW-FAST-NEXT:    kmovq %rax, %k3
 ; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm15, %zmm0 {%k3}
-; AVX512BW-FAST-NEXT:    vshufi64x2 {{.*#+}} zmm22 = zmm23[0,1,2,3],mem[4,5,6,7]
+; AVX512BW-FAST-NEXT:    vshufi64x2 {{.*#+}} zmm23 = zmm23[0,1,2,3],mem[4,5,6,7]
 ; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm15 = <u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,19,128,21,128,128,20,128,22,128,24,128,128,23,128,25,128,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,27,128,128,26,128,28,128,128,128,128,29,128,31,128,128,30>
-; AVX512BW-FAST-NEXT:    vpshufb %zmm15, %zmm22, %zmm22
-; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm22 = zmm22[2,2,3,3,6,6,7,7]
-; AVX512BW-FAST-NEXT:    vshufi64x2 {{.*#+}} zmm23 = zmm16[0,1,2,3],mem[4,5,6,7]
-; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm16 = <u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,128,21,128,128,20,128,22,128,24,128,128,23,128,25,128,128,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,128,128,26,128,28,128,128,27,128,29,128,31,128,128,30,128>
-; AVX512BW-FAST-NEXT:    vpshufb %zmm16, %zmm23, %zmm23
+; AVX512BW-FAST-NEXT:    vpshufb %zmm15, %zmm23, %zmm23
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm23 = zmm23[2,2,3,3,6,6,7,7]
-; AVX512BW-FAST-NEXT:    vporq %zmm22, %zmm23, %zmm23
-; AVX512BW-FAST-NEXT:    vshufi64x2 {{.*#+}} zmm22 = zmm21[0,1,2,3],mem[4,5,6,7]
-; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm21 = <u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,128,21,128,21,20,128,22,128,24,128,22,23,128,25,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,25,128,27,128,128,26,128,28,128,30,128,128,29,128,31,128>
-; AVX512BW-FAST-NEXT:    vpshufb %zmm21, %zmm22, %zmm22
-; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm25 = zmm22[2,2,3,3,6,6,7,7]
+; AVX512BW-FAST-NEXT:    vshufi64x2 {{.*#+}} zmm21 = zmm21[0,1,2,3],mem[4,5,6,7]
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} zmm21 = zmm21[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zmm21[21],zero,zero,zmm21[20],zero,zmm21[22],zero,zmm21[24],zero,zero,zmm21[23],zero,zmm21[25],zero,zero,zmm21[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zmm21[58],zero,zmm21[60],zero,zero,zmm21[59],zero,zmm21[61],zero,zmm21[63],zero,zero,zmm21[62],zero
+; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm21 = zmm21[2,2,3,3,6,6,7,7]
+; AVX512BW-FAST-NEXT:    vporq %zmm23, %zmm21, %zmm21
+; AVX512BW-FAST-NEXT:    vshufi64x2 {{.*#+}} zmm20 = zmm20[0,1,2,3],mem[4,5,6,7]
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} zmm20 = zmm20[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19],zero,zmm20[21],zero,zmm20[21,20],zero,zmm20[22],zero,zmm20[24],zero,zmm20[22,23],zero,zmm20[25,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,57],zero,zmm20[59],zero,zero,zmm20[58],zero,zmm20[60],zero,zmm20[62],zero,zero,zmm20[61],zero,zmm20[63],zero
+; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm20 = zmm20[2,2,3,3,6,6,7,7]
 ; AVX512BW-FAST-NEXT:    vshufi64x2 {{.*#+}} zmm13 = zmm13[0,1,2,3],mem[4,5,6,7]
-; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm22 = <u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,128,128,19,128,21,128,128,20,128,22,128,24,128,128,23,128,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,128,27,128,128,26,128,28,128,30,128,128,29,128,31,128,128>
-; AVX512BW-FAST-NEXT:    vpshufb %zmm22, %zmm13, %zmm13
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} zmm13 = zmm13[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zmm13[19],zero,zmm13[21],zero,zero,zmm13[20],zero,zmm13[22],zero,zmm13[24],zero,zero,zmm13[23],zero,zmm13[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zmm13[59],zero,zero,zmm13[58],zero,zmm13[60],zero,zmm13[62],zero,zero,zmm13[61],zero,zmm13[63],zero,zero
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm13 = zmm13[2,2,3,3,6,6,7,7]
-; AVX512BW-FAST-NEXT:    vporq %zmm25, %zmm13, %zmm13
+; AVX512BW-FAST-NEXT:    vporq %zmm20, %zmm13, %zmm13
 ; AVX512BW-FAST-NEXT:    movabsq $1785168781326730801, %rax # imm = 0x18C6318C6318C631
 ; AVX512BW-FAST-NEXT:    kmovq %rax, %k3
-; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm23, %zmm13 {%k3}
-; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm23 = [4,6,5,5,5,5,4,6,30,30,30,30,31,31,31,31]
-; AVX512BW-FAST-NEXT:    vpermi2d %zmm5, %zmm24, %zmm23
+; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm21, %zmm13 {%k3}
+; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm20 = [4,6,5,5,5,5,4,6,30,30,30,30,31,31,31,31]
+; AVX512BW-FAST-NEXT:    vpermi2d %zmm5, %zmm22, %zmm20
 ; AVX512BW-FAST-NEXT:    movabsq $-8925843906633654008, %rax # imm = 0x8421084210842108
 ; AVX512BW-FAST-NEXT:    kmovq %rax, %k4
-; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm23, %zmm13 {%k4}
-; AVX512BW-FAST-NEXT:    vmovdqa64 (%rcx), %ymm23
-; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm24 = ymm23[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,25],zero,ymm23[27],zero,zero,ymm23[26],zero,ymm23[28],zero,ymm23[30],zero,zero,ymm23[29],zero,ymm23[31],zero
-; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm25 = ymm24[2,2,3,3]
-; AVX512BW-FAST-NEXT:    vmovdqa64 (%rdx), %ymm24
-; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm26 = ymm24[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm24[27],zero,zero,ymm24[26],zero,ymm24[28],zero,ymm24[30],zero,zero,ymm24[29],zero,ymm24[31],zero,zero
-; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm26 = ymm26[2,2,3,3]
-; AVX512BW-FAST-NEXT:    vporq %ymm25, %ymm26, %ymm25
-; AVX512BW-FAST-NEXT:    vpunpcklbw {{.*#+}} xmm18 = xmm18[0],xmm20[0],xmm18[1],xmm20[1],xmm18[2],xmm20[2],xmm18[3],xmm20[3],xmm18[4],xmm20[4],xmm18[5],xmm20[5],xmm18[6],xmm20[6],xmm18[7],xmm20[7]
-; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} xmm26 = <2,u,1,0,5,4,u,3,u,7,6,11,10,u,9,8>
-; AVX512BW-FAST-NEXT:    vpshufb %xmm26, %xmm18, %xmm18
-; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm18 = ymm18[0,0,1,1]
-; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm18, %zmm25, %zmm25
-; AVX512BW-FAST-NEXT:    vmovdqa64 (%rsi), %ymm18
-; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm20 = ymm18[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,27],zero,zero,ymm18[26],zero,ymm18[28],zero,zero,zero,zero,ymm18[29],zero,ymm18[31],zero,zero,ymm18[30]
-; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm27 = ymm20[2,2,3,3]
-; AVX512BW-FAST-NEXT:    vmovdqa64 (%rdi), %ymm20
-; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm28 = ymm20[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm20[26],zero,ymm20[28],zero,zero,ymm20[27],zero,ymm20[29],zero,ymm20[31],zero,zero,ymm20[30],zero
-; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm28 = ymm28[2,2,3,3]
-; AVX512BW-FAST-NEXT:    vporq %ymm27, %ymm28, %ymm27
+; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm20, %zmm13 {%k4}
+; AVX512BW-FAST-NEXT:    vmovdqa64 (%rcx), %ymm20
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm21 = ymm20[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,25],zero,ymm20[27],zero,zero,ymm20[26],zero,ymm20[28],zero,ymm20[30],zero,zero,ymm20[29],zero,ymm20[31],zero
+; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm21 = ymm21[2,2,3,3]
+; AVX512BW-FAST-NEXT:    vmovdqa64 (%rdx), %ymm22
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm23 = ymm22[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm22[27],zero,zero,ymm22[26],zero,ymm22[28],zero,ymm22[30],zero,zero,ymm22[29],zero,ymm22[31],zero,zero
+; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm23 = ymm23[2,2,3,3]
+; AVX512BW-FAST-NEXT:    vporq %ymm21, %ymm23, %ymm21
 ; AVX512BW-FAST-NEXT:    vpunpcklbw {{.*#+}} xmm17 = xmm17[0],xmm19[0],xmm17[1],xmm19[1],xmm17[2],xmm19[2],xmm17[3],xmm19[3],xmm17[4],xmm19[4],xmm17[5],xmm19[5],xmm17[6],xmm19[6],xmm17[7],xmm19[7]
-; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} xmm19 = <0,1,4,5,u,2,3,6,7,10,11,u,8,9,12,13>
+; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} xmm19 = <2,u,1,0,5,4,u,3,u,7,6,11,10,u,9,8>
 ; AVX512BW-FAST-NEXT:    vpshufb %xmm19, %xmm17, %xmm17
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm17 = ymm17[0,0,1,1]
-; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm17, %zmm27, %zmm17
-; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm25, %zmm17 {%k3}
-; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm25 = [6,6,6,6,7,7,7,7,8,8,8,8,8,8,9,9]
-; AVX512BW-FAST-NEXT:    vpermd %zmm5, %zmm25, %zmm5
+; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm17, %zmm21, %zmm21
+; AVX512BW-FAST-NEXT:    vmovdqa64 (%rsi), %ymm17
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm23 = ymm17[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,27],zero,zero,ymm17[26],zero,ymm17[28],zero,zero,zero,zero,ymm17[29],zero,ymm17[31],zero,zero,ymm17[30]
+; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm23 = ymm23[2,2,3,3]
+; AVX512BW-FAST-NEXT:    vmovdqa64 (%rdi), %ymm24
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm25 = ymm24[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm24[26],zero,ymm24[28],zero,zero,ymm24[27],zero,ymm24[29],zero,ymm24[31],zero,zero,ymm24[30],zero
+; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm25 = ymm25[2,2,3,3]
+; AVX512BW-FAST-NEXT:    vporq %ymm23, %ymm25, %ymm23
+; AVX512BW-FAST-NEXT:    vpunpcklbw {{.*#+}} xmm16 = xmm16[0],xmm18[0],xmm16[1],xmm18[1],xmm16[2],xmm18[2],xmm16[3],xmm18[3],xmm16[4],xmm18[4],xmm16[5],xmm18[5],xmm16[6],xmm18[6],xmm16[7],xmm18[7]
+; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} xmm18 = <0,1,4,5,u,2,3,6,7,10,11,u,8,9,12,13>
+; AVX512BW-FAST-NEXT:    vpshufb %xmm18, %xmm16, %xmm16
+; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm16 = ymm16[0,0,1,1]
+; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm16, %zmm23, %zmm16
+; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm21, %zmm16 {%k3}
+; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm21 = [6,6,6,6,7,7,7,7,8,8,8,8,8,8,9,9]
+; AVX512BW-FAST-NEXT:    vpermd %zmm5, %zmm21, %zmm5
 ; AVX512BW-FAST-NEXT:    movabsq $2380225041768974402, %rax # imm = 0x2108421084210842
 ; AVX512BW-FAST-NEXT:    kmovq %rax, %k3
-; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm5, %zmm17 {%k3}
+; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm5, %zmm16 {%k3}
 ; AVX512BW-FAST-NEXT:    vpshufb %xmm8, %xmm6, %xmm5
 ; AVX512BW-FAST-NEXT:    vpshufb %xmm10, %xmm7, %xmm8
 ; AVX512BW-FAST-NEXT:    vpor %xmm5, %xmm8, %xmm5
 ; AVX512BW-FAST-NEXT:    vpunpcklbw {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[1],xmm6[2],xmm7[2],xmm6[3],xmm7[3],xmm6[4],xmm7[4],xmm6[5],xmm7[5],xmm6[6],xmm7[6],xmm6[7],xmm7[7]
-; AVX512BW-FAST-NEXT:    vpshufb %xmm26, %xmm6, %xmm6
+; AVX512BW-FAST-NEXT:    vpshufb %xmm19, %xmm6, %xmm6
 ; AVX512BW-FAST-NEXT:    vinserti32x4 $2, %xmm5, %zmm6, %zmm5
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm5 = zmm5[0,0,1,1,4,4,5,5]
 ; AVX512BW-FAST-NEXT:    vpshufb %xmm12, %xmm9, %xmm6
 ; AVX512BW-FAST-NEXT:    vpshufb %xmm14, %xmm11, %xmm7
 ; AVX512BW-FAST-NEXT:    vpor %xmm6, %xmm7, %xmm6
 ; AVX512BW-FAST-NEXT:    vpunpcklbw {{.*#+}} xmm7 = xmm9[0],xmm11[0],xmm9[1],xmm11[1],xmm9[2],xmm11[2],xmm9[3],xmm11[3],xmm9[4],xmm11[4],xmm9[5],xmm11[5],xmm9[6],xmm11[6],xmm9[7],xmm11[7]
-; AVX512BW-FAST-NEXT:    vpshufb %xmm19, %xmm7, %xmm7
+; AVX512BW-FAST-NEXT:    vpshufb %xmm18, %xmm7, %xmm7
 ; AVX512BW-FAST-NEXT:    vinserti32x4 $2, %xmm6, %zmm7, %zmm6
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm6 = zmm6[0,0,1,1,4,4,5,5]
 ; AVX512BW-FAST-NEXT:    movabsq $-4165393823095705204, %rax # imm = 0xC6318C6318C6318C
@@ -4549,22 +4547,22 @@ define void @store_i8_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
 ; AVX512BW-FAST-NEXT:    movabsq $595056260442243600, %rax # imm = 0x842108421084210
 ; AVX512BW-FAST-NEXT:    kmovq %rax, %k3
 ; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm7, %zmm6 {%k3}
-; AVX512BW-FAST-NEXT:    vpshufb %ymm21, %ymm24, %ymm7
-; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm7 = ymm7[2,2,3,3]
-; AVX512BW-FAST-NEXT:    vpshufb %ymm22, %ymm23, %ymm8
-; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm8 = ymm8[2,2,3,3]
-; AVX512BW-FAST-NEXT:    vpor %ymm7, %ymm8, %ymm7
-; AVX512BW-FAST-NEXT:    vpshufb %ymm1, %ymm24, %ymm1
-; AVX512BW-FAST-NEXT:    vpshufb %ymm2, %ymm23, %ymm2
+; AVX512BW-FAST-NEXT:    vpshufb %ymm1, %ymm22, %ymm1
+; AVX512BW-FAST-NEXT:    vpshufb %ymm2, %ymm20, %ymm2
 ; AVX512BW-FAST-NEXT:    vpor %ymm1, %ymm2, %ymm1
-; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm7, %zmm1, %zmm1
-; AVX512BW-FAST-NEXT:    vpshufb %ymm15, %ymm18, %ymm2
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm22[18,19],zero,ymm22[21],zero,ymm22[21,20],zero,ymm22[22],zero,ymm22[24],zero,ymm22[22,23],zero,ymm22[25]
+; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm2 = ymm2[2,2,3,3]
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm7 = ymm20[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,ymm20[19],zero,ymm20[21],zero,zero,ymm20[20],zero,ymm20[22],zero,ymm20[24],zero,zero,ymm20[23],zero
+; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm7 = ymm7[2,2,3,3]
+; AVX512BW-FAST-NEXT:    vpor %ymm2, %ymm7, %ymm2
+; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm2, %zmm1, %zmm1
+; AVX512BW-FAST-NEXT:    vpshufb %ymm15, %ymm17, %ymm2
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm2 = ymm2[2,2,3,3]
-; AVX512BW-FAST-NEXT:    vpshufb %ymm16, %ymm20, %ymm7
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm7 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm24[21],zero,zero,ymm24[20],zero,ymm24[22],zero,ymm24[24],zero,zero,ymm24[23],zero,ymm24[25],zero,zero
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm7 = ymm7[2,2,3,3]
 ; AVX512BW-FAST-NEXT:    vpor %ymm2, %ymm7, %ymm2
-; AVX512BW-FAST-NEXT:    vpermd %ymm20, %ymm3, %ymm3
-; AVX512BW-FAST-NEXT:    vpshufb %ymm4, %ymm18, %ymm3 {%k1}
+; AVX512BW-FAST-NEXT:    vpermd %ymm24, %ymm3, %ymm3
+; AVX512BW-FAST-NEXT:    vpshufb %ymm4, %ymm17, %ymm3 {%k1}
 ; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm2, %zmm3, %zmm2
 ; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm1, %zmm2 {%k2}
 ; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm1 = <3,3,3,3,u,4,4,4,12,14,13,13,13,13,12,14>
@@ -4574,7 +4572,7 @@ define void @store_i8_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
 ; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm1, %zmm2 {%k1}
 ; AVX512BW-FAST-NEXT:    vmovdqa64 %zmm2, 64(%r9)
 ; AVX512BW-FAST-NEXT:    vmovdqa64 %zmm6, (%r9)
-; AVX512BW-FAST-NEXT:    vmovdqa64 %zmm17, 128(%r9)
+; AVX512BW-FAST-NEXT:    vmovdqa64 %zmm16, 128(%r9)
 ; AVX512BW-FAST-NEXT:    vmovdqa64 %zmm13, 256(%r9)
 ; AVX512BW-FAST-NEXT:    vmovdqa64 %zmm0, 192(%r9)
 ; AVX512BW-FAST-NEXT:    vzeroupper
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
index d16daa04a482..b1493847cdb8 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
@@ -1724,10 +1724,10 @@ define void @store_i8_stride6_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
 ; AVX512F-SLOW-LABEL: store_i8_stride6_vf32:
 ; AVX512F-SLOW:       # %bb.0:
 ; AVX512F-SLOW-NEXT:    movq {{[0-9]+}}(%rsp), %rax
-; AVX512F-SLOW-NEXT:    vmovdqa (%rdi), %ymm2
-; AVX512F-SLOW-NEXT:    vmovdqa (%rsi), %ymm3
-; AVX512F-SLOW-NEXT:    vmovdqa (%rdx), %ymm4
-; AVX512F-SLOW-NEXT:    vmovdqa (%rcx), %ymm5
+; AVX512F-SLOW-NEXT:    vmovdqa (%rdi), %ymm3
+; AVX512F-SLOW-NEXT:    vmovdqa (%rsi), %ymm5
+; AVX512F-SLOW-NEXT:    vmovdqa (%rdx), %ymm2
+; AVX512F-SLOW-NEXT:    vmovdqa (%rcx), %ymm4
 ; AVX512F-SLOW-NEXT:    vmovdqa (%r8), %ymm0
 ; AVX512F-SLOW-NEXT:    vmovdqa (%r9), %ymm1
 ; AVX512F-SLOW-NEXT:    vmovdqa (%rcx), %xmm7
@@ -1735,7 +1735,7 @@ define void @store_i8_stride6_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
 ; AVX512F-SLOW-NEXT:    vpunpckhbw {{.*#+}} xmm6 = xmm8[8],xmm7[8],xmm8[9],xmm7[9],xmm8[10],xmm7[10],xmm8[11],xmm7[11],xmm8[12],xmm7[12],xmm8[13],xmm7[13],xmm8[14],xmm7[14],xmm8[15],xmm7[15]
 ; AVX512F-SLOW-NEXT:    vpshufb {{.*#+}} xmm6 = xmm6[10,11,8,9,6,7,12,13,14,15,14,15,14,15,14,15]
 ; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm6 = ymm6[0,0,0,1]
-; AVX512F-SLOW-NEXT:    vpunpcklbw {{.*#+}} ymm9 = ymm4[0],ymm5[0],ymm4[1],ymm5[1],ymm4[2],ymm5[2],ymm4[3],ymm5[3],ymm4[4],ymm5[4],ymm4[5],ymm5[5],ymm4[6],ymm5[6],ymm4[7],ymm5[7],ymm4[16],ymm5[16],ymm4[17],ymm5[17],ymm4[18],ymm5[18],ymm4[19],ymm5[19],ymm4[20],ymm5[20],ymm4[21],ymm5[21],ymm4[22],ymm5[22],ymm4[23],ymm5[23]
+; AVX512F-SLOW-NEXT:    vpunpcklbw {{.*#+}} ymm9 = ymm2[0],ymm4[0],ymm2[1],ymm4[1],ymm2[2],ymm4[2],ymm2[3],ymm4[3],ymm2[4],ymm4[4],ymm2[5],ymm4[5],ymm2[6],ymm4[6],ymm2[7],ymm4[7],ymm2[16],ymm4[16],ymm2[17],ymm4[17],ymm2[18],ymm4[18],ymm2[19],ymm4[19],ymm2[20],ymm4[20],ymm2[21],ymm4[21],ymm2[22],ymm4[22],ymm2[23],ymm4[23]
 ; AVX512F-SLOW-NEXT:    vprold $16, %ymm9, %ymm9
 ; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm9 = ymm9[2,2,2,3]
 ; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm9, %zmm6, %zmm6
@@ -1744,7 +1744,7 @@ define void @store_i8_stride6_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
 ; AVX512F-SLOW-NEXT:    vpunpckhbw {{.*#+}} xmm11 = xmm10[8],xmm9[8],xmm10[9],xmm9[9],xmm10[10],xmm9[10],xmm10[11],xmm9[11],xmm10[12],xmm9[12],xmm10[13],xmm9[13],xmm10[14],xmm9[14],xmm10[15],xmm9[15]
 ; AVX512F-SLOW-NEXT:    vpshufb {{.*#+}} xmm11 = xmm11[8,9,6,7,12,13,10,11,14,15,14,15,14,15,14,15]
 ; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm11 = ymm11[0,0,0,1]
-; AVX512F-SLOW-NEXT:    vpunpcklbw {{.*#+}} ymm12 = ymm2[0],ymm3[0],ymm2[1],ymm3[1],ymm2[2],ymm3[2],ymm2[3],ymm3[3],ymm2[4],ymm3[4],ymm2[5],ymm3[5],ymm2[6],ymm3[6],ymm2[7],ymm3[7],ymm2[16],ymm3[16],ymm2[17],ymm3[17],ymm2[18],ymm3[18],ymm2[19],ymm3[19],ymm2[20],ymm3[20],ymm2[21],ymm3[21],ymm2[22],ymm3[22],ymm2[23],ymm3[23]
+; AVX512F-SLOW-NEXT:    vpunpcklbw {{.*#+}} ymm12 = ymm3[0],ymm5[0],ymm3[1],ymm5[1],ymm3[2],ymm5[2],ymm3[3],ymm5[3],ymm3[4],ymm5[4],ymm3[5],ymm5[5],ymm3[6],ymm5[6],ymm3[7],ymm5[7],ymm3[16],ymm5[16],ymm3[17],ymm5[17],ymm3[18],ymm5[18],ymm3[19],ymm5[19],ymm3[20],ymm5[20],ymm3[21],ymm5[21],ymm3[22],ymm5[22],ymm3[23],ymm5[23]
 ; AVX512F-SLOW-NEXT:    vpshuflw {{.*#+}} ymm12 = ymm12[0,3,2,1,4,5,6,7,8,11,10,9,12,13,14,15]
 ; AVX512F-SLOW-NEXT:    vpshufhw {{.*#+}} ymm12 = ymm12[0,1,2,3,4,5,6,5,8,9,10,11,12,13,14,13]
 ; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm12 = ymm12[2,2,2,3]
@@ -1769,17 +1769,17 @@ define void @store_i8_stride6_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
 ; AVX512F-SLOW-NEXT:    vpunpcklbw {{.*#+}} xmm15 = xmm8[0],xmm7[0],xmm8[1],xmm7[1],xmm8[2],xmm7[2],xmm8[3],xmm7[3],xmm8[4],xmm7[4],xmm8[5],xmm7[5],xmm8[6],xmm7[6],xmm8[7],xmm7[7]
 ; AVX512F-SLOW-NEXT:    vprold $16, %xmm15, %xmm15
 ; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm13, %zmm15, %zmm13
-; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} zmm15 = zmm13[0,0,0,1,4,4,4,5]
-; AVX512F-SLOW-NEXT:    vpbroadcastq {{.*#+}} ymm13 = [5,8,7,6,9,0,0,10,5,8,7,6,9,0,0,10,5,8,7,6,9,0,0,10,5,8,7,6,9,0,0,10]
-; AVX512F-SLOW-NEXT:    vpshufb %xmm13, %xmm7, %xmm7
-; AVX512F-SLOW-NEXT:    vpshufb %xmm13, %xmm8, %xmm8
+; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} zmm13 = zmm13[0,0,0,1,4,4,4,5]
+; AVX512F-SLOW-NEXT:    vpbroadcastq {{.*#+}} ymm15 = [5,8,7,6,9,0,0,10,5,8,7,6,9,0,0,10,5,8,7,6,9,0,0,10,5,8,7,6,9,0,0,10]
+; AVX512F-SLOW-NEXT:    vpshufb %xmm15, %xmm7, %xmm7
+; AVX512F-SLOW-NEXT:    vpshufb %xmm15, %xmm8, %xmm8
 ; AVX512F-SLOW-NEXT:    vpunpcklbw {{.*#+}} xmm7 = xmm8[0],xmm7[0],xmm8[1],xmm7[1],xmm8[2],xmm7[2],xmm8[3],xmm7[3],xmm8[4],xmm7[4],xmm8[5],xmm7[5],xmm8[6],xmm7[6],xmm8[7],xmm7[7]
 ; AVX512F-SLOW-NEXT:    vpunpcklbw {{.*#+}} xmm8 = xmm10[0],xmm9[0],xmm10[1],xmm9[1],xmm10[2],xmm9[2],xmm10[3],xmm9[3],xmm10[4],xmm9[4],xmm10[5],xmm9[5],xmm10[6],xmm9[6],xmm10[7],xmm9[7]
 ; AVX512F-SLOW-NEXT:    vpshuflw {{.*#+}} xmm8 = xmm8[0,3,2,1,4,5,6,7]
 ; AVX512F-SLOW-NEXT:    vpshufhw {{.*#+}} xmm8 = xmm8[0,1,2,3,4,5,6,5]
 ; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm7, %zmm8, %zmm7
 ; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} zmm8 = zmm7[0,0,0,1,4,4,4,5]
-; AVX512F-SLOW-NEXT:    vpternlogd $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm15, %zmm8
+; AVX512F-SLOW-NEXT:    vpternlogd $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm13, %zmm8
 ; AVX512F-SLOW-NEXT:    vpbroadcastq {{.*#+}} ymm7 = [6,5,8,7,0,9,0,0,6,5,8,7,0,9,0,0,6,5,8,7,0,9,0,0,6,5,8,7,0,9,0,0]
 ; AVX512F-SLOW-NEXT:    vpshufb %xmm7, %xmm11, %xmm9
 ; AVX512F-SLOW-NEXT:    vpshufb %xmm7, %xmm12, %xmm10
@@ -1790,32 +1790,30 @@ define void @store_i8_stride6_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
 ; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm9, %zmm10, %zmm9
 ; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} zmm9 = zmm9[0,0,0,1,4,4,4,5]
 ; AVX512F-SLOW-NEXT:    vpternlogd $184, %zmm8, %zmm14, %zmm9
-; AVX512F-SLOW-NEXT:    vpbroadcastq {{.*#+}} ymm8 = [8,7,6,9,0,0,10,0,8,7,6,9,0,0,10,0,8,7,6,9,0,0,10,0,8,7,6,9,0,0,10,0]
-; AVX512F-SLOW-NEXT:    vpshufb %ymm8, %ymm3, %ymm10
-; AVX512F-SLOW-NEXT:    vpshufb %ymm8, %ymm2, %ymm8
-; AVX512F-SLOW-NEXT:    vpunpcklbw {{.*#+}} ymm8 = ymm8[0],ymm10[0],ymm8[1],ymm10[1],ymm8[2],ymm10[2],ymm8[3],ymm10[3],ymm8[4],ymm10[4],ymm8[5],ymm10[5],ymm8[6],ymm10[6],ymm8[7],ymm10[7],ymm8[16],ymm10[16],ymm8[17],ymm10[17],ymm8[18],ymm10[18],ymm8[19],ymm10[19],ymm8[20],ymm10[20],ymm8[21],ymm10[21],ymm8[22],ymm10[22],ymm8[23],ymm10[23]
-; AVX512F-SLOW-NEXT:    vpunpckhbw {{.*#+}} ymm10 = ymm4[8],ymm5[8],ymm4[9],ymm5[9],ymm4[10],ymm5[10],ymm4[11],ymm5[11],ymm4[12],ymm5[12],ymm4[13],ymm5[13],ymm4[14],ymm5[14],ymm4[15],ymm5[15],ymm4[24],ymm5[24],ymm4[25],ymm5[25],ymm4[26],ymm5[26],ymm4[27],ymm5[27],ymm4[28],ymm5[28],ymm4[29],ymm5[29],ymm4[30],ymm5[30],ymm4[31],ymm5[31]
-; AVX512F-SLOW-NEXT:    vpshufb {{.*#+}} ymm10 = ymm10[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,26,27,24,25,22,23,28,29,30,31,30,31,30,31,30,31]
+; AVX512F-SLOW-NEXT:    vpshufb %ymm15, %ymm4, %ymm8
+; AVX512F-SLOW-NEXT:    vpshufb %ymm15, %ymm2, %ymm10
+; AVX512F-SLOW-NEXT:    vpunpcklbw {{.*#+}} ymm8 = ymm10[0],ymm8[0],ymm10[1],ymm8[1],ymm10[2],ymm8[2],ymm10[3],ymm8[3],ymm10[4],ymm8[4],ymm10[5],ymm8[5],ymm10[6],ymm8[6],ymm10[7],ymm8[7],ymm10[16],ymm8[16],ymm10[17],ymm8[17],ymm10[18],ymm8[18],ymm10[19],ymm8[19],ymm10[20],ymm8[20],ymm10[21],ymm8[21],ymm10[22],ymm8[22],ymm10[23],ymm8[23]
+; AVX512F-SLOW-NEXT:    vpunpckhbw {{.*#+}} ymm10 = ymm3[8],ymm5[8],ymm3[9],ymm5[9],ymm3[10],ymm5[10],ymm3[11],ymm5[11],ymm3[12],ymm5[12],ymm3[13],ymm5[13],ymm3[14],ymm5[14],ymm3[15],ymm5[15],ymm3[24],ymm5[24],ymm3[25],ymm5[25],ymm3[26],ymm5[26],ymm3[27],ymm5[27],ymm3[28],ymm5[28],ymm3[29],ymm5[29],ymm3[30],ymm5[30],ymm3[31],ymm5[31]
+; AVX512F-SLOW-NEXT:    vpshufb {{.*#+}} ymm10 = ymm10[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25,22,23,28,29,26,27,30,31,30,31,30,31,30,31]
 ; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm10, %zmm8, %zmm8
 ; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} zmm8 = zmm8[2,2,2,3,6,6,6,7]
-; AVX512F-SLOW-NEXT:    vpshufb %ymm13, %ymm5, %ymm5
-; AVX512F-SLOW-NEXT:    vpshufb %ymm13, %ymm4, %ymm4
-; AVX512F-SLOW-NEXT:    vpunpcklbw {{.*#+}} ymm4 = ymm4[0],ymm5[0],ymm4[1],ymm5[1],ymm4[2],ymm5[2],ymm4[3],ymm5[3],ymm4[4],ymm5[4],ymm4[5],ymm5[5],ymm4[6],ymm5[6],ymm4[7],ymm5[7],ymm4[16],ymm5[16],ymm4[17],ymm5[17],ymm4[18],ymm5[18],ymm4[19],ymm5[19],ymm4[20],ymm5[20],ymm4[21],ymm5[21],ymm4[22],ymm5[22],ymm4[23],ymm5[23]
-; AVX512F-SLOW-NEXT:    vpunpckhbw {{.*#+}} ymm2 = ymm2[8],ymm3[8],ymm2[9],ymm3[9],ymm2[10],ymm3[10],ymm2[11],ymm3[11],ymm2[12],ymm3[12],ymm2[13],ymm3[13],ymm2[14],ymm3[14],ymm2[15],ymm3[15],ymm2[24],ymm3[24],ymm2[25],ymm3[25],ymm2[26],ymm3[26],ymm2[27],ymm3[27],ymm2[28],ymm3[28],ymm2[29],ymm3[29],ymm2[30],ymm3[30],ymm2[31],ymm3[31]
-; AVX512F-SLOW-NEXT:    vpshufb {{.*#+}} ymm2 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25,22,23,28,29,26,27,30,31,30,31,30,31,30,31]
-; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm2, %zmm4, %zmm2
+; AVX512F-SLOW-NEXT:    vpbroadcastq {{.*#+}} ymm10 = [8,7,6,9,0,0,10,0,8,7,6,9,0,0,10,0,8,7,6,9,0,0,10,0,8,7,6,9,0,0,10,0]
+; AVX512F-SLOW-NEXT:    vpshufb %ymm10, %ymm5, %ymm5
+; AVX512F-SLOW-NEXT:    vpshufb %ymm10, %ymm3, %ymm3
+; AVX512F-SLOW-NEXT:    vpunpcklbw {{.*#+}} ymm3 = ymm3[0],ymm5[0],ymm3[1],ymm5[1],ymm3[2],ymm5[2],ymm3[3],ymm5[3],ymm3[4],ymm5[4],ymm3[5],ymm5[5],ymm3[6],ymm5[6],ymm3[7],ymm5[7],ymm3[16],ymm5[16],ymm3[17],ymm5[17],ymm3[18],ymm5[18],ymm3[19],ymm5[19],ymm3[20],ymm5[20],ymm3[21],ymm5[21],ymm3[22],ymm5[22],ymm3[23],ymm5[23]
+; AVX512F-SLOW-NEXT:    vpunpckhbw {{.*#+}} ymm2 = ymm2[8],ymm4[8],ymm2[9],ymm4[9],ymm2[10],ymm4[10],ymm2[11],ymm4[11],ymm2[12],ymm4[12],ymm2[13],ymm4[13],ymm2[14],ymm4[14],ymm2[15],ymm4[15],ymm2[24],ymm4[24],ymm2[25],ymm4[25],ymm2[26],ymm4[26],ymm2[27],ymm4[27],ymm2[28],ymm4[28],ymm2[29],ymm4[29],ymm2[30],ymm4[30],ymm2[31],ymm4[31]
+; AVX512F-SLOW-NEXT:    vpshufb {{.*#+}} ymm2 = ymm2[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,26,27,24,25,22,23,28,29,30,31,30,31,30,31,30,31]
+; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm2, %zmm3, %zmm2
 ; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} zmm2 = zmm2[2,2,2,3,6,6,6,7]
-; AVX512F-SLOW-NEXT:    vbroadcasti64x4 {{.*#+}} zmm3 = [65535,65535,0,65535,65535,0,65535,65535,0,65535,65535,0,65535,65535,0,65535,65535,65535,0,65535,65535,0,65535,65535,0,65535,65535,0,65535,65535,0,65535]
-; AVX512F-SLOW-NEXT:    # zmm3 = mem[0,1,2,3,0,1,2,3]
-; AVX512F-SLOW-NEXT:    vpternlogq $202, %zmm8, %zmm2, %zmm3
-; AVX512F-SLOW-NEXT:    vpshufb %ymm7, %ymm1, %ymm2
+; AVX512F-SLOW-NEXT:    vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm8, %zmm2
+; AVX512F-SLOW-NEXT:    vpshufb %ymm7, %ymm1, %ymm3
 ; AVX512F-SLOW-NEXT:    vpshufb %ymm7, %ymm0, %ymm4
-; AVX512F-SLOW-NEXT:    vpunpcklbw {{.*#+}} ymm2 = ymm4[0],ymm2[0],ymm4[1],ymm2[1],ymm4[2],ymm2[2],ymm4[3],ymm2[3],ymm4[4],ymm2[4],ymm4[5],ymm2[5],ymm4[6],ymm2[6],ymm4[7],ymm2[7],ymm4[16],ymm2[16],ymm4[17],ymm2[17],ymm4[18],ymm2[18],ymm4[19],ymm2[19],ymm4[20],ymm2[20],ymm4[21],ymm2[21],ymm4[22],ymm2[22],ymm4[23],ymm2[23]
+; AVX512F-SLOW-NEXT:    vpunpcklbw {{.*#+}} ymm3 = ymm4[0],ymm3[0],ymm4[1],ymm3[1],ymm4[2],ymm3[2],ymm4[3],ymm3[3],ymm4[4],ymm3[4],ymm4[5],ymm3[5],ymm4[6],ymm3[6],ymm4[7],ymm3[7],ymm4[16],ymm3[16],ymm4[17],ymm3[17],ymm4[18],ymm3[18],ymm4[19],ymm3[19],ymm4[20],ymm3[20],ymm4[21],ymm3[21],ymm4[22],ymm3[22],ymm4[23],ymm3[23]
 ; AVX512F-SLOW-NEXT:    vpunpckhbw {{.*#+}} ymm0 = ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15],ymm0[24],ymm1[24],ymm0[25],ymm1[25],ymm0[26],ymm1[26],ymm0[27],ymm1[27],ymm0[28],ymm1[28],ymm0[29],ymm1[29],ymm0[30],ymm1[30],ymm0[31],ymm1[31]
 ; AVX512F-SLOW-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,20,21,26,27,24,25,22,23,28,29,26,27,28,29,30,31]
-; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm0, %zmm2, %zmm0
+; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm0, %zmm3, %zmm0
 ; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} zmm0 = zmm0[2,2,2,3,6,6,6,7]
-; AVX512F-SLOW-NEXT:    vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm0
+; AVX512F-SLOW-NEXT:    vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm0
 ; AVX512F-SLOW-NEXT:    vmovdqa64 %zmm0, 128(%rax)
 ; AVX512F-SLOW-NEXT:    vmovdqa64 %zmm9, (%rax)
 ; AVX512F-SLOW-NEXT:    vmovdqa64 %zmm6, 64(%rax)
@@ -1831,34 +1829,32 @@ define void @store_i8_stride6_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
 ; AVX512F-FAST-NEXT:    vmovdqa (%rcx), %ymm5
 ; AVX512F-FAST-NEXT:    vmovdqa (%r8), %ymm0
 ; AVX512F-FAST-NEXT:    vmovdqa (%r9), %ymm1
-; AVX512F-FAST-NEXT:    vpbroadcastq {{.*#+}} ymm6 = [8,7,6,9,0,0,10,0,8,7,6,9,0,0,10,0,8,7,6,9,0,0,10,0,8,7,6,9,0,0,10,0]
-; AVX512F-FAST-NEXT:    vpshufb %ymm6, %ymm3, %ymm7
-; AVX512F-FAST-NEXT:    vpshufb %ymm6, %ymm2, %ymm6
-; AVX512F-FAST-NEXT:    vpunpcklbw {{.*#+}} ymm6 = ymm6[0],ymm7[0],ymm6[1],ymm7[1],ymm6[2],ymm7[2],ymm6[3],ymm7[3],ymm6[4],ymm7[4],ymm6[5],ymm7[5],ymm6[6],ymm7[6],ymm6[7],ymm7[7],ymm6[16],ymm7[16],ymm6[17],ymm7[17],ymm6[18],ymm7[18],ymm6[19],ymm7[19],ymm6[20],ymm7[20],ymm6[21],ymm7[21],ymm6[22],ymm7[22],ymm6[23],ymm7[23]
-; AVX512F-FAST-NEXT:    vpunpckhbw {{.*#+}} ymm7 = ymm4[8],ymm5[8],ymm4[9],ymm5[9],ymm4[10],ymm5[10],ymm4[11],ymm5[11],ymm4[12],ymm5[12],ymm4[13],ymm5[13],ymm4[14],ymm5[14],ymm4[15],ymm5[15],ymm4[24],ymm5[24],ymm4[25],ymm5[25],ymm4[26],ymm5[26],ymm4[27],ymm5[27],ymm4[28],ymm5[28],ymm4[29],ymm5[29],ymm4[30],ymm5[30],ymm4[31],ymm5[31]
-; AVX512F-FAST-NEXT:    vpshufb {{.*#+}} ymm7 = ymm7[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,26,27,24,25,22,23,28,29,30,31,30,31,30,31,30,31]
-; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm7, %zmm6, %zmm6
-; AVX512F-FAST-NEXT:    vpermq {{.*#+}} zmm6 = zmm6[2,2,2,3,6,6,6,7]
 ; AVX512F-FAST-NEXT:    vpbroadcastq {{.*#+}} ymm7 = [5,8,7,6,9,0,0,10,5,8,7,6,9,0,0,10,5,8,7,6,9,0,0,10,5,8,7,6,9,0,0,10]
-; AVX512F-FAST-NEXT:    vpshufb %ymm7, %ymm5, %ymm8
-; AVX512F-FAST-NEXT:    vpshufb %ymm7, %ymm4, %ymm9
-; AVX512F-FAST-NEXT:    vpunpcklbw {{.*#+}} ymm8 = ymm9[0],ymm8[0],ymm9[1],ymm8[1],ymm9[2],ymm8[2],ymm9[3],ymm8[3],ymm9[4],ymm8[4],ymm9[5],ymm8[5],ymm9[6],ymm8[6],ymm9[7],ymm8[7],ymm9[16],ymm8[16],ymm9[17],ymm8[17],ymm9[18],ymm8[18],ymm9[19],ymm8[19],ymm9[20],ymm8[20],ymm9[21],ymm8[21],ymm9[22],ymm8[22],ymm9[23],ymm8[23]
-; AVX512F-FAST-NEXT:    vpunpckhbw {{.*#+}} ymm9 = ymm2[8],ymm3[8],ymm2[9],ymm3[9],ymm2[10],ymm3[10],ymm2[11],ymm3[11],ymm2[12],ymm3[12],ymm2[13],ymm3[13],ymm2[14],ymm3[14],ymm2[15],ymm3[15],ymm2[24],ymm3[24],ymm2[25],ymm3[25],ymm2[26],ymm3[26],ymm2[27],ymm3[27],ymm2[28],ymm3[28],ymm2[29],ymm3[29],ymm2[30],ymm3[30],ymm2[31],ymm3[31]
-; AVX512F-FAST-NEXT:    vpshufb {{.*#+}} ymm9 = ymm9[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25,22,23,28,29,26,27,30,31,30,31,30,31,30,31]
+; AVX512F-FAST-NEXT:    vpshufb %ymm7, %ymm5, %ymm6
+; AVX512F-FAST-NEXT:    vpshufb %ymm7, %ymm4, %ymm8
+; AVX512F-FAST-NEXT:    vpunpcklbw {{.*#+}} ymm6 = ymm8[0],ymm6[0],ymm8[1],ymm6[1],ymm8[2],ymm6[2],ymm8[3],ymm6[3],ymm8[4],ymm6[4],ymm8[5],ymm6[5],ymm8[6],ymm6[6],ymm8[7],ymm6[7],ymm8[16],ymm6[16],ymm8[17],ymm6[17],ymm8[18],ymm6[18],ymm8[19],ymm6[19],ymm8[20],ymm6[20],ymm8[21],ymm6[21],ymm8[22],ymm6[22],ymm8[23],ymm6[23]
+; AVX512F-FAST-NEXT:    vpunpckhbw {{.*#+}} ymm8 = ymm2[8],ymm3[8],ymm2[9],ymm3[9],ymm2[10],ymm3[10],ymm2[11],ymm3[11],ymm2[12],ymm3[12],ymm2[13],ymm3[13],ymm2[14],ymm3[14],ymm2[15],ymm3[15],ymm2[24],ymm3[24],ymm2[25],ymm3[25],ymm2[26],ymm3[26],ymm2[27],ymm3[27],ymm2[28],ymm3[28],ymm2[29],ymm3[29],ymm2[30],ymm3[30],ymm2[31],ymm3[31]
+; AVX512F-FAST-NEXT:    vpshufb {{.*#+}} ymm8 = ymm8[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25,22,23,28,29,26,27,30,31,30,31,30,31,30,31]
+; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm8, %zmm6, %zmm6
+; AVX512F-FAST-NEXT:    vpermq {{.*#+}} zmm6 = zmm6[2,2,2,3,6,6,6,7]
+; AVX512F-FAST-NEXT:    vpbroadcastq {{.*#+}} ymm8 = [8,7,6,9,0,0,10,0,8,7,6,9,0,0,10,0,8,7,6,9,0,0,10,0,8,7,6,9,0,0,10,0]
+; AVX512F-FAST-NEXT:    vpshufb %ymm8, %ymm3, %ymm9
+; AVX512F-FAST-NEXT:    vpshufb %ymm8, %ymm2, %ymm8
+; AVX512F-FAST-NEXT:    vpunpcklbw {{.*#+}} ymm8 = ymm8[0],ymm9[0],ymm8[1],ymm9[1],ymm8[2],ymm9[2],ymm8[3],ymm9[3],ymm8[4],ymm9[4],ymm8[5],ymm9[5],ymm8[6],ymm9[6],ymm8[7],ymm9[7],ymm8[16],ymm9[16],ymm8[17],ymm9[17],ymm8[18],ymm9[18],ymm8[19],ymm9[19],ymm8[20],ymm9[20],ymm8[21],ymm9[21],ymm8[22],ymm9[22],ymm8[23],ymm9[23]
+; AVX512F-FAST-NEXT:    vpunpckhbw {{.*#+}} ymm9 = ymm4[8],ymm5[8],ymm4[9],ymm5[9],ymm4[10],ymm5[10],ymm4[11],ymm5[11],ymm4[12],ymm5[12],ymm4[13],ymm5[13],ymm4[14],ymm5[14],ymm4[15],ymm5[15],ymm4[24],ymm5[24],ymm4[25],ymm5[25],ymm4[26],ymm5[26],ymm4[27],ymm5[27],ymm4[28],ymm5[28],ymm4[29],ymm5[29],ymm4[30],ymm5[30],ymm4[31],ymm5[31]
+; AVX512F-FAST-NEXT:    vpshufb {{.*#+}} ymm9 = ymm9[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,26,27,24,25,22,23,28,29,30,31,30,31,30,31,30,31]
 ; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm9, %zmm8, %zmm8
 ; AVX512F-FAST-NEXT:    vpermq {{.*#+}} zmm8 = zmm8[2,2,2,3,6,6,6,7]
-; AVX512F-FAST-NEXT:    vbroadcasti64x4 {{.*#+}} zmm9 = [65535,65535,0,65535,65535,0,65535,65535,0,65535,65535,0,65535,65535,0,65535,65535,65535,0,65535,65535,0,65535,65535,0,65535,65535,0,65535,65535,0,65535]
-; AVX512F-FAST-NEXT:    # zmm9 = mem[0,1,2,3,0,1,2,3]
-; AVX512F-FAST-NEXT:    vpternlogq $202, %zmm6, %zmm8, %zmm9
+; AVX512F-FAST-NEXT:    vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm6, %zmm8
 ; AVX512F-FAST-NEXT:    vpbroadcastq {{.*#+}} ymm10 = [6,5,8,7,0,9,0,0,6,5,8,7,0,9,0,0,6,5,8,7,0,9,0,0,6,5,8,7,0,9,0,0]
 ; AVX512F-FAST-NEXT:    vpshufb %ymm10, %ymm1, %ymm6
-; AVX512F-FAST-NEXT:    vpshufb %ymm10, %ymm0, %ymm8
-; AVX512F-FAST-NEXT:    vpunpcklbw {{.*#+}} ymm6 = ymm8[0],ymm6[0],ymm8[1],ymm6[1],ymm8[2],ymm6[2],ymm8[3],ymm6[3],ymm8[4],ymm6[4],ymm8[5],ymm6[5],ymm8[6],ymm6[6],ymm8[7],ymm6[7],ymm8[16],ymm6[16],ymm8[17],ymm6[17],ymm8[18],ymm6[18],ymm8[19],ymm6[19],ymm8[20],ymm6[20],ymm8[21],ymm6[21],ymm8[22],ymm6[22],ymm8[23],ymm6[23]
-; AVX512F-FAST-NEXT:    vpunpckhbw {{.*#+}} ymm8 = ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15],ymm0[24],ymm1[24],ymm0[25],ymm1[25],ymm0[26],ymm1[26],ymm0[27],ymm1[27],ymm0[28],ymm1[28],ymm0[29],ymm1[29],ymm0[30],ymm1[30],ymm0[31],ymm1[31]
-; AVX512F-FAST-NEXT:    vpshufb {{.*#+}} ymm8 = ymm8[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,20,21,26,27,24,25,22,23,28,29,26,27,28,29,30,31]
-; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm8, %zmm6, %zmm6
+; AVX512F-FAST-NEXT:    vpshufb %ymm10, %ymm0, %ymm9
+; AVX512F-FAST-NEXT:    vpunpcklbw {{.*#+}} ymm6 = ymm9[0],ymm6[0],ymm9[1],ymm6[1],ymm9[2],ymm6[2],ymm9[3],ymm6[3],ymm9[4],ymm6[4],ymm9[5],ymm6[5],ymm9[6],ymm6[6],ymm9[7],ymm6[7],ymm9[16],ymm6[16],ymm9[17],ymm6[17],ymm9[18],ymm6[18],ymm9[19],ymm6[19],ymm9[20],ymm6[20],ymm9[21],ymm6[21],ymm9[22],ymm6[22],ymm9[23],ymm6[23]
+; AVX512F-FAST-NEXT:    vpunpckhbw {{.*#+}} ymm9 = ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15],ymm0[24],ymm1[24],ymm0[25],ymm1[25],ymm0[26],ymm1[26],ymm0[27],ymm1[27],ymm0[28],ymm1[28],ymm0[29],ymm1[29],ymm0[30],ymm1[30],ymm0[31],ymm1[31]
+; AVX512F-FAST-NEXT:    vpshufb {{.*#+}} ymm9 = ymm9[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,20,21,26,27,24,25,22,23,28,29,26,27,28,29,30,31]
+; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm9, %zmm6, %zmm6
 ; AVX512F-FAST-NEXT:    vpermq {{.*#+}} zmm6 = zmm6[2,2,2,3,6,6,6,7]
-; AVX512F-FAST-NEXT:    vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm9, %zmm6
+; AVX512F-FAST-NEXT:    vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm8, %zmm6
 ; AVX512F-FAST-NEXT:    vmovdqa (%rcx), %xmm9
 ; AVX512F-FAST-NEXT:    vpshufb %xmm7, %xmm9, %xmm8
 ; AVX512F-FAST-NEXT:    vmovdqa (%rdx), %xmm11
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
index a4f21ea2a915..04c1bd532252 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
@@ -3437,8 +3437,7 @@ define void @store_i8_stride7_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
 ; AVX512F-SLOW-NEXT:    vpshufhw {{.*#+}} xmm7 = xmm15[0,1,2,3,4,5,5,6]
 ; AVX512F-SLOW-NEXT:    vpshufd {{.*#+}} xmm7 = xmm7[2,2,3,3]
 ; AVX512F-SLOW-NEXT:    vpermq {{.*#+}} ymm7 = ymm7[0,1,0,1]
-; AVX512F-SLOW-NEXT:    vmovdqa {{.*#+}} ymm9 = [255,255,255,255,255,0,255,255,255,255,255,255,0,255,255,255,255,255,255,0,255,255,255,255,255,255,0,255,255,255,255,255]
-; AVX512F-SLOW-NEXT:    vpandn %ymm7, %ymm9, %ymm7
+; AVX512F-SLOW-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm7, %ymm7
 ; AVX512F-SLOW-NEXT:    vpshufb {{.*#+}} ymm9 = zero,ymm4[13,u,u,u,u],zero,zero,ymm4[14,u,u,u,u],zero,zero,ymm4[15,u,u,u,u],zero,zero,ymm4[16,u,u,u,u],zero,zero,ymm4[17,u,u]
 ; AVX512F-SLOW-NEXT:    vinserti64x4 $1, %ymm9, %zmm7, %zmm7
 ; AVX512F-SLOW-NEXT:    vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm7
@@ -3547,8 +3546,7 @@ define void @store_i8_stride7_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
 ; AVX512F-FAST-NEXT:    vbroadcasti128 {{.*#+}} ymm10 = [2,2,3,3,2,2,3,3]
 ; AVX512F-FAST-NEXT:    # ymm10 = mem[0,1,0,1]
 ; AVX512F-FAST-NEXT:    vpermd %ymm8, %ymm10, %ymm8
-; AVX512F-FAST-NEXT:    vmovdqa {{.*#+}} ymm10 = [255,255,255,255,255,0,255,255,255,255,255,255,0,255,255,255,255,255,255,0,255,255,255,255,255,255,0,255,255,255,255,255]
-; AVX512F-FAST-NEXT:    vpandn %ymm8, %ymm10, %ymm8
+; AVX512F-FAST-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm8, %ymm8
 ; AVX512F-FAST-NEXT:    vmovdqa64 %ymm17, %ymm13
 ; AVX512F-FAST-NEXT:    vpshufb {{.*#+}} ymm10 = zero,ymm13[13,u,u,u,u],zero,zero,ymm13[14,u,u,u,u],zero,zero,ymm13[15,u,u,u,u],zero,zero,ymm13[16,u,u,u,u],zero,zero,ymm13[17,u,u]
 ; AVX512F-FAST-NEXT:    vinserti64x4 $1, %ymm10, %zmm8, %zmm8
@@ -8415,250 +8413,253 @@ define void @store_i8_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
 ;
 ; AVX512BW-FAST-LABEL: store_i8_stride7_vf64:
 ; AVX512BW-FAST:       # %bb.0:
-; AVX512BW-FAST-NEXT:    subq $200, %rsp
+; AVX512BW-FAST-NEXT:    subq $72, %rsp
 ; AVX512BW-FAST-NEXT:    movq {{[0-9]+}}(%rsp), %rax
-; AVX512BW-FAST-NEXT:    vmovdqa64 (%rdi), %zmm9
-; AVX512BW-FAST-NEXT:    vmovdqu64 %zmm9, (%rsp) # 64-byte Spill
-; AVX512BW-FAST-NEXT:    vmovdqa64 (%rsi), %zmm5
-; AVX512BW-FAST-NEXT:    vmovdqu64 %zmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
-; AVX512BW-FAST-NEXT:    vmovdqa64 (%rdx), %zmm2
-; AVX512BW-FAST-NEXT:    vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
-; AVX512BW-FAST-NEXT:    vmovdqa (%rax), %ymm4
-; AVX512BW-FAST-NEXT:    vmovdqu %ymm4, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
-; AVX512BW-FAST-NEXT:    vmovdqa 32(%rax), %ymm13
+; AVX512BW-FAST-NEXT:    vmovdqa64 (%rdi), %zmm7
+; AVX512BW-FAST-NEXT:    vmovdqu64 %zmm7, (%rsp) # 64-byte Spill
+; AVX512BW-FAST-NEXT:    vmovdqa (%rax), %ymm3
+; AVX512BW-FAST-NEXT:    vmovdqu %ymm3, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; AVX512BW-FAST-NEXT:    vmovdqa 32(%rax), %ymm11
 ; AVX512BW-FAST-NEXT:    vmovdqa {{.*#+}} ymm0 = [12,13,2,3,12,13,0,1,14,15,2,3,0,1,14,15,28,29,18,19,28,29,16,17,30,31,18,19,16,17,30,31]
-; AVX512BW-FAST-NEXT:    vpshufb %ymm0, %ymm4, %ymm1
-; AVX512BW-FAST-NEXT:    vbroadcasti128 {{.*#+}} ymm3 = [4,5,4,5,5,6,5,6,4,5,4,5,5,6,5,6]
-; AVX512BW-FAST-NEXT:    # ymm3 = mem[0,1,0,1]
-; AVX512BW-FAST-NEXT:    vpermw %ymm4, %ymm3, %ymm3
-; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm1, %zmm3, %zmm6
-; AVX512BW-FAST-NEXT:    vmovdqa (%r9), %ymm15
-; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} ymm17 = [13,128,128,128,128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128,128]
-; AVX512BW-FAST-NEXT:    vpshufb %ymm17, %ymm15, %ymm7
-; AVX512BW-FAST-NEXT:    vmovdqa (%r8), %ymm1
-; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} ymm20 = [128,128,128,128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128,128,128]
-; AVX512BW-FAST-NEXT:    vpshufb %ymm20, %ymm1, %ymm8
-; AVX512BW-FAST-NEXT:    vmovdqa64 %ymm1, %ymm24
-; AVX512BW-FAST-NEXT:    vpor %ymm7, %ymm8, %ymm7
-; AVX512BW-FAST-NEXT:    vmovdqa64 (%r9), %xmm25
-; AVX512BW-FAST-NEXT:    vmovdqa (%r8), %xmm10
-; AVX512BW-FAST-NEXT:    vpunpckhbw {{.*#+}} xmm8 = xmm10[8],xmm25[8],xmm10[9],xmm25[9],xmm10[10],xmm25[10],xmm10[11],xmm25[11],xmm10[12],xmm25[12],xmm10[13],xmm25[13],xmm10[14],xmm25[14],xmm10[15],xmm25[15]
-; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} xmm8 = xmm8[u,6,7,2,3,u,u,u,8,9,4,5,u,u,u,10]
-; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm8 = ymm8[0,1,0,1]
-; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm7, %zmm8, %zmm22
+; AVX512BW-FAST-NEXT:    vpshufb %ymm0, %ymm3, %ymm1
+; AVX512BW-FAST-NEXT:    vbroadcasti128 {{.*#+}} ymm2 = [4,5,4,5,5,6,5,6,4,5,4,5,5,6,5,6]
+; AVX512BW-FAST-NEXT:    # ymm2 = mem[0,1,0,1]
+; AVX512BW-FAST-NEXT:    vpermw %ymm3, %ymm2, %ymm2
+; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm1, %zmm2, %zmm4
+; AVX512BW-FAST-NEXT:    vmovdqa (%r9), %ymm2
+; AVX512BW-FAST-NEXT:    vmovdqa {{.*#+}} ymm1 = [13,128,128,128,128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128,128]
+; AVX512BW-FAST-NEXT:    vpshufb %ymm1, %ymm2, %ymm5
+; AVX512BW-FAST-NEXT:    vmovdqa %ymm2, %ymm3
+; AVX512BW-FAST-NEXT:    vmovdqa (%r8), %ymm2
+; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} ymm16 = [128,128,128,128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128,128,128]
+; AVX512BW-FAST-NEXT:    vpshufb %ymm16, %ymm2, %ymm6
+; AVX512BW-FAST-NEXT:    vmovdqa %ymm2, %ymm12
+; AVX512BW-FAST-NEXT:    vpor %ymm5, %ymm6, %ymm5
+; AVX512BW-FAST-NEXT:    vmovdqa (%r9), %xmm2
+; AVX512BW-FAST-NEXT:    vmovdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; AVX512BW-FAST-NEXT:    vmovdqa (%r8), %xmm6
+; AVX512BW-FAST-NEXT:    vmovdqa %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; AVX512BW-FAST-NEXT:    vpunpckhbw {{.*#+}} xmm6 = xmm6[8],xmm2[8],xmm6[9],xmm2[9],xmm6[10],xmm2[10],xmm6[11],xmm2[11],xmm6[12],xmm2[12],xmm6[13],xmm2[13],xmm6[14],xmm2[14],xmm6[15],xmm2[15]
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} xmm6 = xmm6[u,6,7,2,3,u,u,u,8,9,4,5,u,u,u,10]
+; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm6 = ymm6[0,1,0,1]
+; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm5, %zmm6, %zmm21
 ; AVX512BW-FAST-NEXT:    movabsq $2323999253380730912, %r10 # imm = 0x2040810204081020
 ; AVX512BW-FAST-NEXT:    kmovq %r10, %k1
-; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm6, %zmm22 {%k1}
-; AVX512BW-FAST-NEXT:    vmovdqa (%rdx), %ymm1
-; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} ymm21 = [0,1,0,1,14,128,14,15,0,1,14,15,128,13,14,15,16,17,16,128,30,31,30,31,16,17,128,31,28,29,30,31]
-; AVX512BW-FAST-NEXT:    vpshufb %ymm21, %ymm1, %ymm6
-; AVX512BW-FAST-NEXT:    vmovdqa %ymm1, %ymm7
-; AVX512BW-FAST-NEXT:    vmovdqa (%rcx), %ymm1
-; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} ymm23 = [128,128,128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128,128,128,128]
-; AVX512BW-FAST-NEXT:    vpshufb %ymm23, %ymm1, %ymm11
-; AVX512BW-FAST-NEXT:    vmovdqa %ymm1, %ymm8
-; AVX512BW-FAST-NEXT:    vmovdqu %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
-; AVX512BW-FAST-NEXT:    vpor %ymm6, %ymm11, %ymm6
-; AVX512BW-FAST-NEXT:    vmovdqa (%rdx), %xmm14
-; AVX512BW-FAST-NEXT:    vmovdqa64 (%rcx), %xmm16
-; AVX512BW-FAST-NEXT:    vpunpckhbw {{.*#+}} xmm11 = xmm16[8],xmm14[8],xmm16[9],xmm14[9],xmm16[10],xmm14[10],xmm16[11],xmm14[11],xmm16[12],xmm14[12],xmm16[13],xmm14[13],xmm16[14],xmm14[14],xmm16[15],xmm14[15]
-; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} xmm11 = xmm11[6,3,2,u,u,u,9,8,5,4,u,u,u,11,10,7]
-; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm11 = ymm11[0,1,0,1]
-; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm6, %zmm11, %zmm26
-; AVX512BW-FAST-NEXT:    vmovdqa (%rdi), %ymm11
-; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} ymm28 = [0,1,14,128,12,13,0,1,14,15,128,3,12,13,2,3,16,128,30,31,28,29,16,17,128,31,18,19,28,29,18,128]
-; AVX512BW-FAST-NEXT:    vpshufb %ymm28, %ymm11, %ymm6
-; AVX512BW-FAST-NEXT:    vmovdqa (%rsi), %ymm12
-; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} ymm29 = [128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128,128,128,128,128,18]
-; AVX512BW-FAST-NEXT:    vpshufb %ymm29, %ymm12, %ymm18
-; AVX512BW-FAST-NEXT:    vporq %ymm6, %ymm18, %ymm6
-; AVX512BW-FAST-NEXT:    vmovdqa64 (%rdi), %xmm18
-; AVX512BW-FAST-NEXT:    vmovdqa64 (%rsi), %xmm19
-; AVX512BW-FAST-NEXT:    vpunpckhbw {{.*#+}} xmm27 = xmm19[8],xmm18[8],xmm19[9],xmm18[9],xmm19[10],xmm18[10],xmm19[11],xmm18[11],xmm19[12],xmm18[12],xmm19[13],xmm18[13],xmm19[14],xmm18[14],xmm19[15],xmm18[15]
-; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} xmm27 = xmm27[2,u,u,u,9,8,5,4,u,u,u,11,10,7,6,u]
-; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm27 = ymm27[0,1,0,1]
-; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm6, %zmm27, %zmm6
+; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm4, %zmm21 {%k1}
+; AVX512BW-FAST-NEXT:    vmovdqa (%rdx), %ymm2
+; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} ymm19 = [0,1,0,1,14,128,14,15,0,1,14,15,128,13,14,15,16,17,16,128,30,31,30,31,16,17,128,31,28,29,30,31]
+; AVX512BW-FAST-NEXT:    vpshufb %ymm19, %ymm2, %ymm4
+; AVX512BW-FAST-NEXT:    vmovdqa %ymm2, %ymm5
+; AVX512BW-FAST-NEXT:    vmovdqu %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; AVX512BW-FAST-NEXT:    vmovdqa (%rcx), %ymm2
+; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} ymm20 = [128,128,128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128,128,128,128]
+; AVX512BW-FAST-NEXT:    vpshufb %ymm20, %ymm2, %ymm9
+; AVX512BW-FAST-NEXT:    vmovdqa64 %ymm2, %ymm25
+; AVX512BW-FAST-NEXT:    vmovdqu %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
+; AVX512BW-FAST-NEXT:    vpor %ymm4, %ymm9, %ymm4
+; AVX512BW-FAST-NEXT:    vmovdqa (%rdx), %xmm13
+; AVX512BW-FAST-NEXT:    vmovdqa (%rcx), %xmm15
+; AVX512BW-FAST-NEXT:    vpunpckhbw {{.*#+}} xmm9 = xmm15[8],xmm13[8],xmm15[9],xmm13[9],xmm15[10],xmm13[10],xmm15[11],xmm13[11],xmm15[12],xmm13[12],xmm15[13],xmm13[13],xmm15[14],xmm13[14],xmm15[15],xmm13[15]
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} xmm9 = xmm9[6,3,2,u,u,u,9,8,5,4,u,u,u,11,10,7]
+; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm9 = ymm9[0,1,0,1]
+; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm4, %zmm9, %zmm22
+; AVX512BW-FAST-NEXT:    vmovdqa (%rdi), %ymm14
+; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} ymm23 = [0,1,14,128,12,13,0,1,14,15,128,3,12,13,2,3,16,128,30,31,28,29,16,17,128,31,18,19,28,29,18,128]
+; AVX512BW-FAST-NEXT:    vpshufb %ymm23, %ymm14, %ymm4
+; AVX512BW-FAST-NEXT:    vmovdqa (%rsi), %ymm10
+; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} ymm24 = [128,128,128,14,128,128,128,128,128,128,15,128,128,128,128,128,128,16,128,128,128,128,128,128,17,128,128,128,128,128,128,18]
+; AVX512BW-FAST-NEXT:    vpshufb %ymm24, %ymm10, %ymm17
+; AVX512BW-FAST-NEXT:    vporq %ymm4, %ymm17, %ymm4
+; AVX512BW-FAST-NEXT:    vmovdqa64 (%rdi), %xmm17
+; AVX512BW-FAST-NEXT:    vmovdqa64 (%rsi), %xmm18
+; AVX512BW-FAST-NEXT:    vpunpckhbw {{.*#+}} xmm26 = xmm18[8],xmm17[8],xmm18[9],xmm17[9],xmm18[10],xmm17[10],xmm18[11],xmm17[11],xmm18[12],xmm17[12],xmm18[13],xmm17[13],xmm18[14],xmm17[14],xmm18[15],xmm17[15]
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} xmm26 = xmm26[2,u,u,u,9,8,5,4,u,u,u,11,10,7,6,u]
+; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm26 = ymm26[0,1,0,1]
+; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm4, %zmm26, %zmm8
 ; AVX512BW-FAST-NEXT:    movabsq $435749860008887046, %r10 # imm = 0x60C183060C18306
 ; AVX512BW-FAST-NEXT:    kmovq %r10, %k1
-; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm26, %zmm6 {%k1}
+; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm22, %zmm8 {%k1}
 ; AVX512BW-FAST-NEXT:    movabsq $4066998693416279096, %r10 # imm = 0x3870E1C3870E1C38
 ; AVX512BW-FAST-NEXT:    kmovq %r10, %k1
-; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm22, %zmm6 {%k1}
-; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} ymm22 = [10,9,9,10,10,9,9,10,9,10,14,15,10,9,9,10]
-; AVX512BW-FAST-NEXT:    vpermw %ymm13, %ymm22, %ymm22
-; AVX512BW-FAST-NEXT:    vpshufb %ymm0, %ymm13, %ymm0
-; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm22, %zmm0, %zmm22
-; AVX512BW-FAST-NEXT:    vmovdqa64 32(%r9), %ymm27
-; AVX512BW-FAST-NEXT:    vpshufb %ymm17, %ymm27, %ymm17
-; AVX512BW-FAST-NEXT:    vmovdqa 32(%r8), %ymm1
-; AVX512BW-FAST-NEXT:    vpshufb %ymm20, %ymm1, %ymm20
-; AVX512BW-FAST-NEXT:    vporq %ymm17, %ymm20, %ymm17
-; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm20 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm1[20],zero,ymm1[18],zero,ymm1[20,21,20,21],zero,ymm1[19],zero,ymm1[19,20,21,22],zero
-; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm20 = ymm20[2,3,2,3]
-; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm26 = ymm27[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm27[20],zero,ymm27[18],zero,zero,zero,zero,ymm27[21],zero,ymm27[19],zero,zero,zero,zero,ymm27[22]
-; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm26 = ymm26[2,3,2,3]
-; AVX512BW-FAST-NEXT:    vporq %ymm20, %ymm26, %ymm20
-; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm20, %zmm17, %zmm26
+; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm21, %zmm8 {%k1}
+; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} ymm21 = [10,9,9,10,10,9,9,10,9,10,14,15,10,9,9,10]
+; AVX512BW-FAST-NEXT:    vpermw %ymm11, %ymm21, %ymm21
+; AVX512BW-FAST-NEXT:    vpshufb %ymm0, %ymm11, %ymm0
+; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm21, %zmm0, %zmm21
+; AVX512BW-FAST-NEXT:    vmovdqa64 32(%r9), %ymm28
+; AVX512BW-FAST-NEXT:    vpshufb %ymm1, %ymm28, %ymm1
+; AVX512BW-FAST-NEXT:    vmovdqa 32(%r8), %ymm0
+; AVX512BW-FAST-NEXT:    vpshufb %ymm16, %ymm0, %ymm16
+; AVX512BW-FAST-NEXT:    vporq %ymm1, %ymm16, %ymm1
+; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm2 = <u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,128,20,128,18,128,128,128,128,21,128,19,128,128,128,128,22,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,128,128,128,128,25,128,23,128,128,128,128,26,128,24,128,128>
+; AVX512BW-FAST-NEXT:    vpshufb %ymm2, %ymm28, %ymm16
+; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm16 = ymm16[2,3,2,3]
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm22 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm0[20],zero,ymm0[18],zero,ymm0[20,21,20,21],zero,ymm0[19],zero,ymm0[19,20,21,22],zero
+; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm22 = ymm22[2,3,2,3]
+; AVX512BW-FAST-NEXT:    vporq %ymm22, %ymm16, %ymm16
+; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm16, %zmm1, %zmm1
 ; AVX512BW-FAST-NEXT:    movabsq $145249953336295682, %r10 # imm = 0x204081020408102
 ; AVX512BW-FAST-NEXT:    kmovq %r10, %k1
-; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm22, %zmm26 {%k1}
-; AVX512BW-FAST-NEXT:    vmovdqa64 32(%rdx), %ymm22
-; AVX512BW-FAST-NEXT:    vpshufb %ymm21, %ymm22, %ymm17
-; AVX512BW-FAST-NEXT:    vmovdqa64 32(%rcx), %ymm30
-; AVX512BW-FAST-NEXT:    vpshufb %ymm23, %ymm30, %ymm20
-; AVX512BW-FAST-NEXT:    vporq %ymm17, %ymm20, %ymm17
-; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm20 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm22[18],zero,ymm22[18,19,20,21],zero,ymm22[19],zero,ymm22[25,26,27,22],zero,ymm22[20],zero
+; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm21, %zmm1 {%k1}
+; AVX512BW-FAST-NEXT:    vmovdqa64 32(%rdx), %ymm26
+; AVX512BW-FAST-NEXT:    vpshufb %ymm19, %ymm26, %ymm16
+; AVX512BW-FAST-NEXT:    vmovdqa64 32(%rcx), %ymm29
+; AVX512BW-FAST-NEXT:    vpshufb %ymm20, %ymm29, %ymm19
+; AVX512BW-FAST-NEXT:    vporq %ymm16, %ymm19, %ymm16
+; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm2 = <u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,128,18,128,128,128,128,21,128,19,128,128,128,128,22,128,20,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,128,128,25,128,23,128,128,128,128,26,128,24,128,128,128,128>
+; AVX512BW-FAST-NEXT:    vpshufb %ymm2, %ymm29, %ymm20
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm20 = ymm20[2,3,2,3]
-; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm21 = ymm30[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm30[18],zero,zero,zero,zero,ymm30[21],zero,ymm30[19],zero,zero,zero,zero,ymm30[22],zero,ymm30[20]
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm21 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm26[18],zero,ymm26[18,19,20,21],zero,ymm26[19],zero,ymm26[25,26,27,22],zero,ymm26[20],zero
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm21 = ymm21[2,3,2,3]
-; AVX512BW-FAST-NEXT:    vporq %ymm20, %ymm21, %ymm20
-; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm20, %zmm17, %zmm21
-; AVX512BW-FAST-NEXT:    vmovdqa64 32(%rdi), %ymm31
-; AVX512BW-FAST-NEXT:    vpshufb %ymm28, %ymm31, %ymm17
-; AVX512BW-FAST-NEXT:    vmovdqa 32(%rsi), %ymm0
-; AVX512BW-FAST-NEXT:    vpshufb %ymm29, %ymm0, %ymm20
-; AVX512BW-FAST-NEXT:    vporq %ymm17, %ymm20, %ymm17
-; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm20 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm31[18,19,20,21],zero,ymm31[19],zero,ymm31[21,20,21,22],zero,ymm31[20],zero,ymm31[22,23]
-; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm20 = ymm20[2,3,2,3]
-; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm23 = ymm0[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm0[21],zero,ymm0[19],zero,zero,zero,zero,ymm0[22],zero,ymm0[20],zero,zero
-; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm23 = ymm23[2,3,2,3]
-; AVX512BW-FAST-NEXT:    vporq %ymm20, %ymm23, %ymm20
-; AVX512BW-FAST-NEXT:    vmovdqa64 (%rcx), %zmm23
-; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm20, %zmm17, %zmm17
-; AVX512BW-FAST-NEXT:    vmovdqa64 (%r8), %zmm3
-; AVX512BW-FAST-NEXT:    vmovdqu64 %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
+; AVX512BW-FAST-NEXT:    vporq %ymm21, %ymm20, %ymm20
+; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm20, %zmm16, %zmm20
+; AVX512BW-FAST-NEXT:    vmovdqa64 32(%rdi), %ymm30
+; AVX512BW-FAST-NEXT:    vpshufb %ymm23, %ymm30, %ymm16
+; AVX512BW-FAST-NEXT:    vmovdqa64 32(%rsi), %ymm31
+; AVX512BW-FAST-NEXT:    vpshufb %ymm24, %ymm31, %ymm21
+; AVX512BW-FAST-NEXT:    vporq %ymm16, %ymm21, %ymm16
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm21 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm30[18,19,20,21],zero,ymm30[19],zero,ymm30[21,20,21,22],zero,ymm30[20],zero,ymm30[22,23]
+; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm21 = ymm21[2,3,2,3]
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm22 = ymm31[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm31[21],zero,ymm31[19],zero,zero,zero,zero,ymm31[22],zero,ymm31[20],zero,zero
+; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm22 = ymm22[2,3,2,3]
+; AVX512BW-FAST-NEXT:    vporq %ymm21, %ymm22, %ymm21
+; AVX512BW-FAST-NEXT:    vmovdqa64 (%rsi), %zmm24
+; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm21, %zmm16, %zmm16
+; AVX512BW-FAST-NEXT:    vmovdqa64 (%rdx), %zmm22
 ; AVX512BW-FAST-NEXT:    movabsq $3485998880071096368, %r10 # imm = 0x3060C183060C1830
 ; AVX512BW-FAST-NEXT:    kmovq %r10, %k2
-; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm21, %zmm17 {%k2}
-; AVX512BW-FAST-NEXT:    vmovdqa64 (%r9), %zmm21
+; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm20, %zmm16 {%k2}
+; AVX512BW-FAST-NEXT:    vmovdqa64 (%rcx), %zmm23
 ; AVX512BW-FAST-NEXT:    movabsq $-4357498600088870461, %r10 # imm = 0xC3870E1C3870E1C3
 ; AVX512BW-FAST-NEXT:    kmovq %r10, %k1
-; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm26, %zmm17 {%k1}
-; AVX512BW-FAST-NEXT:    vmovdqa64 (%rax), %zmm26
-; AVX512BW-FAST-NEXT:    vshufi64x2 {{.*#+}} zmm22 = zmm22[0,1,2,3],zmm23[4,5,6,7]
-; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} zmm22 = zmm22[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25],zero,zmm22[23],zero,zmm22[21,22,23,26],zero,zmm22[24],zero,zmm22[28,29,26,27,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,59],zero,zero,zero,zero,zmm22[62],zero,zmm22[60],zero,zero,zero,zero,zmm22[63],zero,zmm22[61],zero
-; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm22 = zmm22[2,3,2,3,6,7,6,7]
-; AVX512BW-FAST-NEXT:    vshufi64x2 {{.*#+}} zmm28 = zmm30[0,1,2,3],zmm2[4,5,6,7]
-; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} zmm28 = zmm28[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zmm28[25],zero,zmm28[23],zero,zero,zero,zero,zmm28[26],zero,zmm28[24],zero,zero,zero,zero,zmm28[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,zmm28[62],zero,zmm28[60],zero,zero,zero,zero,zmm28[63],zero,zmm28[61],zero,zero
-; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm28 = zmm28[2,3,2,3,6,7,6,7]
-; AVX512BW-FAST-NEXT:    vporq %zmm22, %zmm28, %zmm29
-; AVX512BW-FAST-NEXT:    vmovdqa64 32(%rdi), %xmm28
-; AVX512BW-FAST-NEXT:    vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm9[4,5,6,7]
-; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} zmm0 = zmm0[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,25],zero,zmm0[23],zero,zero,zero,zero,zmm0[26],zero,zmm0[24],zero,zero,zero,zero,zmm0[27],zero,zmm0[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,60,61,62],zero,zmm0[60],zero,zmm0[62,63,62,63],zero,zmm0[61],zero,zmm0[63,60,61]
-; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm0 = zmm0[2,3,2,3,6,7,6,7]
-; AVX512BW-FAST-NEXT:    vshufi64x2 {{.*#+}} zmm22 = zmm31[0,1,2,3],zmm5[4,5,6,7]
-; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} zmm22 = zmm22[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zmm22[23],zero,zero,zero,zero,zmm22[26],zero,zmm22[24],zero,zero,zero,zero,zmm22[27],zero,zmm22[25,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zmm22[62],zero,zmm22[60],zero,zero,zero,zero,zmm22[63],zero,zmm22[61],zero,zero,zero
-; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm22 = zmm22[2,3,2,3,6,7,6,7]
-; AVX512BW-FAST-NEXT:    vporq %zmm0, %zmm22, %zmm22
-; AVX512BW-FAST-NEXT:    vmovdqa64 32(%rsi), %xmm30
+; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm1, %zmm16 {%k1}
+; AVX512BW-FAST-NEXT:    vmovdqa64 (%r8), %zmm27
+; AVX512BW-FAST-NEXT:    vshufi64x2 {{.*#+}} zmm1 = zmm26[0,1,2,3],zmm23[4,5,6,7]
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} zmm1 = zmm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25],zero,zmm1[23],zero,zmm1[21,22,23,26],zero,zmm1[24],zero,zmm1[28,29,26,27,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,59],zero,zero,zero,zero,zmm1[62],zero,zmm1[60],zero,zero,zero,zero,zmm1[63],zero,zmm1[61],zero
+; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm1 = zmm1[2,3,2,3,6,7,6,7]
+; AVX512BW-FAST-NEXT:    vshufi64x2 {{.*#+}} zmm20 = zmm29[0,1,2,3],zmm22[4,5,6,7]
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} zmm20 = zmm20[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zmm20[25],zero,zmm20[23],zero,zero,zero,zero,zmm20[26],zero,zmm20[24],zero,zero,zero,zero,zmm20[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,zmm20[62],zero,zmm20[60],zero,zero,zero,zero,zmm20[63],zero,zmm20[61],zero,zero
+; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm20 = zmm20[2,3,2,3,6,7,6,7]
+; AVX512BW-FAST-NEXT:    vporq %zmm1, %zmm20, %zmm1
+; AVX512BW-FAST-NEXT:    vmovdqa64 (%r9), %zmm26
+; AVX512BW-FAST-NEXT:    vshufi64x2 {{.*#+}} zmm20 = zmm31[0,1,2,3],zmm7[4,5,6,7]
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} zmm20 = zmm20[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,25],zero,zmm20[23],zero,zero,zero,zero,zmm20[26],zero,zmm20[24],zero,zero,zero,zero,zmm20[27],zero,zmm20[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,60,61,62],zero,zmm20[60],zero,zmm20[62,63,62,63],zero,zmm20[61],zero,zmm20[63,60,61]
+; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm20 = zmm20[2,3,2,3,6,7,6,7]
+; AVX512BW-FAST-NEXT:    vshufi64x2 {{.*#+}} zmm29 = zmm30[0,1,2,3],zmm24[4,5,6,7]
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} zmm29 = zmm29[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zmm29[23],zero,zero,zero,zero,zmm29[26],zero,zmm29[24],zero,zero,zero,zero,zmm29[27],zero,zmm29[25,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zmm29[62],zero,zmm29[60],zero,zero,zero,zero,zmm29[63],zero,zmm29[61],zero,zero,zero
+; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm29 = zmm29[2,3,2,3,6,7,6,7]
+; AVX512BW-FAST-NEXT:    vporq %zmm20, %zmm29, %zmm20
+; AVX512BW-FAST-NEXT:    vmovdqa64 (%rax), %zmm29
 ; AVX512BW-FAST-NEXT:    movabsq $1742999440035548184, %rax # imm = 0x183060C183060C18
 ; AVX512BW-FAST-NEXT:    kmovq %rax, %k1
-; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm29, %zmm22 {%k1}
-; AVX512BW-FAST-NEXT:    vshufi64x2 {{.*#+}} zmm0 = zmm1[0,1,2,3],zmm21[4,5,6,7]
+; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm1, %zmm20 {%k1}
+; AVX512BW-FAST-NEXT:    vmovdqa64 32(%rdi), %xmm31
+; AVX512BW-FAST-NEXT:    vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm26[4,5,6,7]
 ; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} zmm0 = zmm0[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25,24,25],zero,zmm0[23],zero,zmm0[23,24,25,26],zero,zmm0[24],zero,zmm0[30,31,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,61],zero,zmm0[59],zero,zero,zero,zero,zmm0[62],zero,zmm0[60],zero,zero,zero,zero,zmm0[63],zero
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm0 = zmm0[2,3,2,3,6,7,6,7]
-; AVX512BW-FAST-NEXT:    vshufi64x2 {{.*#+}} zmm1 = zmm27[0,1,2,3],zmm3[4,5,6,7]
+; AVX512BW-FAST-NEXT:    vshufi64x2 {{.*#+}} zmm1 = zmm28[0,1,2,3],zmm27[4,5,6,7]
 ; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} zmm1 = zmm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,zmm1[25],zero,zmm1[23],zero,zero,zero,zero,zmm1[26],zero,zmm1[24],zero,zero,zmm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zmm1[59],zero,zero,zero,zero,zmm1[62],zero,zmm1[60],zero,zero,zero,zero,zmm1[63],zero,zmm1[61]
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm1 = zmm1[2,3,2,3,6,7,6,7]
 ; AVX512BW-FAST-NEXT:    vporq %zmm0, %zmm1, %zmm0
 ; AVX512BW-FAST-NEXT:    movabsq $6971997760142192736, %rax # imm = 0x60C183060C183060
 ; AVX512BW-FAST-NEXT:    kmovq %rax, %k1
-; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm0, %zmm22 {%k1}
+; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm0, %zmm20 {%k1}
 ; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm0 = [11,13,12,11,12,13,13,12,11,13,12,11,12,13,13,12,62,61,62,63,63,62,62,63,62,61,62,63,63,62,62,63]
-; AVX512BW-FAST-NEXT:    vpermi2w %zmm26, %zmm13, %zmm0
+; AVX512BW-FAST-NEXT:    vpermi2w %zmm29, %zmm11, %zmm0
 ; AVX512BW-FAST-NEXT:    movabsq $-9150747060186627967, %rax # imm = 0x8102040810204081
 ; AVX512BW-FAST-NEXT:    kmovq %rax, %k3
-; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm0, %zmm22 {%k3}
-; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm0 = ymm11[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,28,29,30],zero,ymm11[28],zero,ymm11[30,31,30,31],zero,ymm11[29],zero,ymm11[31,28,29]
+; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm0, %zmm20 {%k3}
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm0 = ymm14[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,28,29,30],zero,ymm14[28],zero,ymm14[30,31,30,31],zero,ymm14[29],zero,ymm14[31,28,29]
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[2,3,2,3]
-; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm1 = ymm12[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,ymm12[30],zero,ymm12[28],zero,zero,zero,zero,ymm12[31],zero,ymm12[29],zero,zero,zero
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm1 = ymm10[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,ymm10[30],zero,ymm10[28],zero,zero,zero,zero,ymm10[31],zero,ymm10[29],zero,zero,zero
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm1 = ymm1[2,3,2,3]
 ; AVX512BW-FAST-NEXT:    vpor %ymm0, %ymm1, %ymm0
-; AVX512BW-FAST-NEXT:    vpunpcklbw {{.*#+}} xmm1 = xmm28[0],xmm30[0],xmm28[1],xmm30[1],xmm28[2],xmm30[2],xmm28[3],xmm30[3],xmm28[4],xmm30[4],xmm28[5],xmm30[5],xmm28[6],xmm30[6],xmm28[7],xmm30[7]
-; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,u,u,u,6,7,2,3,u,u,u,8,9,4,5]
-; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm1 = ymm1[0,1,0,1]
-; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm1, %zmm0, %zmm3
-; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm0 = ymm8[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,27],zero,zero,zero,zero,ymm8[30],zero,ymm8[28],zero,zero,zero,zero,ymm8[31],zero,ymm8[29],zero
+; AVX512BW-FAST-NEXT:    vmovdqa 32(%rsi), %xmm7
+; AVX512BW-FAST-NEXT:    vpunpcklbw {{.*#+}} xmm2 = xmm31[0],xmm7[0],xmm31[1],xmm7[1],xmm31[2],xmm7[2],xmm31[3],xmm7[3],xmm31[4],xmm7[4],xmm31[5],xmm7[5],xmm31[6],xmm7[6],xmm31[7],xmm7[7]
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} xmm2 = xmm2[0,1,u,u,u,6,7,2,3,u,u,u,8,9,4,5]
+; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm2 = ymm2[0,1,0,1]
+; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm2, %zmm0, %zmm6
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm0 = ymm25[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,27],zero,zero,zero,zero,ymm25[30],zero,ymm25[28],zero,zero,zero,zero,ymm25[31],zero,ymm25[29],zero
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[2,3,2,3]
-; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm27 = ymm7[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm7[30],zero,ymm7[28],zero,zero,zero,zero,ymm7[31],zero,ymm7[29],zero,zero
-; AVX512BW-FAST-NEXT:    vmovdqa64 %ymm7, %ymm20
-; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm27 = ymm27[2,3,2,3]
-; AVX512BW-FAST-NEXT:    vporq %ymm0, %ymm27, %ymm27
-; AVX512BW-FAST-NEXT:    vmovdqa64 32(%rdx), %xmm31
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm28 = ymm5[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,ymm5[30],zero,ymm5[28],zero,zero,zero,zero,ymm5[31],zero,ymm5[29],zero,zero
+; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm28 = ymm28[2,3,2,3]
+; AVX512BW-FAST-NEXT:    vporq %ymm0, %ymm28, %ymm28
+; AVX512BW-FAST-NEXT:    vmovdqa 32(%rdx), %xmm2
 ; AVX512BW-FAST-NEXT:    vmovdqa 32(%rcx), %xmm1
-; AVX512BW-FAST-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm31[0],xmm1[0],xmm31[1],xmm1[1],xmm31[2],xmm1[2],xmm31[3],xmm1[3],xmm31[4],xmm1[4],xmm31[5],xmm1[5],xmm31[6],xmm1[6],xmm31[7],xmm1[7]
-; AVX512BW-FAST-NEXT:    vmovdqa {{.*#+}} xmm7 = <4,5,0,1,u,u,u,6,7,2,3,u,u,u,8,9>
-; AVX512BW-FAST-NEXT:    vpshufb %xmm7, %xmm0, %xmm0
+; AVX512BW-FAST-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3],xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7]
+; AVX512BW-FAST-NEXT:    vmovdqa {{.*#+}} xmm9 = <4,5,0,1,u,u,u,6,7,2,3,u,u,u,8,9>
+; AVX512BW-FAST-NEXT:    vpshufb %xmm9, %xmm0, %xmm0
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[0,1,0,1]
-; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm0, %zmm27, %zmm27
-; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm3, %zmm27 {%k2}
-; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm0 = ymm15[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,29],zero,ymm15[27],zero,zero,zero,zero,ymm15[30],zero,ymm15[28],zero,zero,zero,zero,ymm15[31],zero
+; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm0, %zmm28, %zmm28
+; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm6, %zmm28 {%k2}
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm0 = ymm3[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,29],zero,ymm3[27],zero,zero,zero,zero,ymm3[30],zero,ymm3[28],zero,zero,zero,zero,ymm3[31],zero
+; AVX512BW-FAST-NEXT:    vmovdqa64 %ymm3, %ymm30
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[2,3,2,3]
-; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm3 = ymm24[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm24[27],zero,zero,zero,zero,ymm24[30],zero,ymm24[28],zero,zero,zero,zero,ymm24[31],zero,ymm24[29]
-; AVX512BW-FAST-NEXT:    vmovdqa64 %ymm24, %ymm9
-; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm3 = ymm3[2,3,2,3]
-; AVX512BW-FAST-NEXT:    vpor %ymm0, %ymm3, %ymm2
-; AVX512BW-FAST-NEXT:    vmovdqa 32(%r9), %xmm4
-; AVX512BW-FAST-NEXT:    vmovdqa 32(%r8), %xmm3
-; AVX512BW-FAST-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3],xmm3[4],xmm4[4],xmm3[5],xmm4[5],xmm3[6],xmm4[6],xmm3[7],xmm4[7]
-; AVX512BW-FAST-NEXT:    vmovdqa {{.*#+}} xmm8 = <u,u,4,5,0,1,u,u,u,6,7,2,3,u,u,u>
-; AVX512BW-FAST-NEXT:    vpshufb %xmm8, %xmm0, %xmm0
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} ymm6 = ymm12[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,ymm12[27],zero,zero,zero,zero,ymm12[30],zero,ymm12[28],zero,zero,zero,zero,ymm12[31],zero,ymm12[29]
+; AVX512BW-FAST-NEXT:    vmovdqa64 %ymm12, %ymm21
+; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm6 = ymm6[2,3,2,3]
+; AVX512BW-FAST-NEXT:    vpor %ymm0, %ymm6, %ymm3
+; AVX512BW-FAST-NEXT:    vmovdqa 32(%r9), %xmm5
+; AVX512BW-FAST-NEXT:    vmovdqa 32(%r8), %xmm4
+; AVX512BW-FAST-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm4[0],xmm5[0],xmm4[1],xmm5[1],xmm4[2],xmm5[2],xmm4[3],xmm5[3],xmm4[4],xmm5[4],xmm4[5],xmm5[5],xmm4[6],xmm5[6],xmm4[7],xmm5[7]
+; AVX512BW-FAST-NEXT:    vmovdqa {{.*#+}} xmm12 = <u,u,4,5,0,1,u,u,u,6,7,2,3,u,u,u>
+; AVX512BW-FAST-NEXT:    vpshufb %xmm12, %xmm0, %xmm0
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[0,1,0,1]
-; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm0, %zmm2, %zmm0
-; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm2 = [14,13,14,15,15,14,14,15,14,13,14,15,15,14,14,15,17,17,16,16,17,17,16,16,20,21,17,17,17,17,16,16]
-; AVX512BW-FAST-NEXT:    vpermw %zmm26, %zmm2, %zmm2
+; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm0, %zmm3, %zmm0
+; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm3 = [14,13,14,15,15,14,14,15,14,13,14,15,15,14,14,15,17,17,16,16,17,17,16,16,20,21,17,17,17,17,16,16]
+; AVX512BW-FAST-NEXT:    vpermw %zmm29, %zmm3, %zmm3
 ; AVX512BW-FAST-NEXT:    movabsq $580999813345182728, %rax # imm = 0x810204081020408
 ; AVX512BW-FAST-NEXT:    kmovq %rax, %k2
-; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm2, %zmm0 {%k2}
+; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm3, %zmm0 {%k2}
 ; AVX512BW-FAST-NEXT:    movabsq $1016749673354069774, %rax # imm = 0xE1C3870E1C3870E
 ; AVX512BW-FAST-NEXT:    kmovq %rax, %k2
-; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm0, %zmm27 {%k2}
-; AVX512BW-FAST-NEXT:    vmovdqa {{.*#+}} xmm5 = <u,u,u,128,7,128,5,u,u,u,128,8,128,6,u,u>
-; AVX512BW-FAST-NEXT:    vpshufb %xmm5, %xmm1, %xmm2
+; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm0, %zmm28 {%k2}
+; AVX512BW-FAST-NEXT:    vmovdqa {{.*#+}} xmm6 = <u,u,u,128,7,128,5,u,u,u,128,8,128,6,u,u>
+; AVX512BW-FAST-NEXT:    vpshufb %xmm6, %xmm1, %xmm3
 ; AVX512BW-FAST-NEXT:    vmovdqa {{.*#+}} xmm0 = <u,u,u,7,128,5,128,u,u,u,8,128,6,128,u,u>
-; AVX512BW-FAST-NEXT:    vpshufb %xmm0, %xmm31, %xmm24
-; AVX512BW-FAST-NEXT:    vporq %xmm2, %xmm24, %xmm2
-; AVX512BW-FAST-NEXT:    vpunpckhbw {{.*#+}} xmm1 = xmm1[8],xmm31[8],xmm1[9],xmm31[9],xmm1[10],xmm31[10],xmm1[11],xmm31[11],xmm1[12],xmm31[12],xmm1[13],xmm31[13],xmm1[14],xmm31[14],xmm1[15],xmm31[15]
+; AVX512BW-FAST-NEXT:    vpshufb %xmm0, %xmm2, %xmm19
+; AVX512BW-FAST-NEXT:    vporq %xmm3, %xmm19, %xmm3
+; AVX512BW-FAST-NEXT:    vpunpckhbw {{.*#+}} xmm1 = xmm1[8],xmm2[8],xmm1[9],xmm2[9],xmm1[10],xmm2[10],xmm1[11],xmm2[11],xmm1[12],xmm2[12],xmm1[13],xmm2[13],xmm1[14],xmm2[14],xmm1[15],xmm2[15]
 ; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[6,3,2,u,u,u,9,8,5,4,u,u,u,11,10,7]
-; AVX512BW-FAST-NEXT:    vinserti32x4 $2, %xmm1, %zmm2, %zmm1
+; AVX512BW-FAST-NEXT:    vinserti32x4 $2, %xmm1, %zmm3, %zmm1
 ; AVX512BW-FAST-NEXT:    vmovdqa {{.*#+}} xmm2 = <u,128,7,128,5,u,u,u,128,8,128,6,u,u,u,128>
-; AVX512BW-FAST-NEXT:    vpshufb %xmm2, %xmm30, %xmm24
-; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} xmm31 = <u,7,128,5,128,u,u,u,8,128,6,128,u,u,u,9>
-; AVX512BW-FAST-NEXT:    vpshufb %xmm31, %xmm28, %xmm29
-; AVX512BW-FAST-NEXT:    vporq %xmm24, %xmm29, %xmm24
-; AVX512BW-FAST-NEXT:    vpunpckhbw {{.*#+}} xmm28 = xmm30[8],xmm28[8],xmm30[9],xmm28[9],xmm30[10],xmm28[10],xmm30[11],xmm28[11],xmm30[12],xmm28[12],xmm30[13],xmm28[13],xmm30[14],xmm28[14],xmm30[15],xmm28[15]
-; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} xmm28 = xmm28[2,u,u,u,9,8,5,4,u,u,u,11,10,7,6,u]
-; AVX512BW-FAST-NEXT:    vinserti32x4 $2, %xmm28, %zmm24, %zmm24
+; AVX512BW-FAST-NEXT:    vpshufb %xmm2, %xmm7, %xmm3
+; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} xmm19 = <u,7,128,5,128,u,u,u,8,128,6,128,u,u,u,9>
+; AVX512BW-FAST-NEXT:    vpshufb %xmm19, %xmm31, %xmm25
+; AVX512BW-FAST-NEXT:    vporq %xmm3, %xmm25, %xmm3
+; AVX512BW-FAST-NEXT:    vpunpckhbw {{.*#+}} xmm7 = xmm7[8],xmm31[8],xmm7[9],xmm31[9],xmm7[10],xmm31[10],xmm7[11],xmm31[11],xmm7[12],xmm31[12],xmm7[13],xmm31[13],xmm7[14],xmm31[14],xmm7[15],xmm31[15]
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} xmm7 = xmm7[2,u,u,u,9,8,5,4,u,u,u,11,10,7,6,u]
+; AVX512BW-FAST-NEXT:    vinserti32x4 $2, %xmm7, %zmm3, %zmm3
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm1 = zmm1[0,1,0,1,4,5,4,5]
-; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm24 = zmm24[0,1,0,1,4,5,4,5]
-; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm1, %zmm24 {%k1}
+; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm25 = zmm3[0,1,0,1,4,5,4,5]
+; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm1, %zmm25 {%k1}
 ; AVX512BW-FAST-NEXT:    vmovdqa {{.*#+}} xmm1 = <128,4,u,u,u,128,7,128,5,u,u,u,128,8,128,6>
-; AVX512BW-FAST-NEXT:    vpshufb %xmm1, %xmm4, %xmm28
-; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} xmm29 = <4,128,u,u,u,7,128,5,128,u,u,u,8,128,6,128>
-; AVX512BW-FAST-NEXT:    vpshufb %xmm29, %xmm3, %xmm30
-; AVX512BW-FAST-NEXT:    vporq %xmm28, %xmm30, %xmm28
-; AVX512BW-FAST-NEXT:    vpunpckhbw {{.*#+}} xmm3 = xmm3[8],xmm4[8],xmm3[9],xmm4[9],xmm3[10],xmm4[10],xmm3[11],xmm4[11],xmm3[12],xmm4[12],xmm3[13],xmm4[13],xmm3[14],xmm4[14],xmm3[15],xmm4[15]
-; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} xmm3 = xmm3[u,6,7,2,3,u,u,u,8,9,4,5,u,u,u,10]
-; AVX512BW-FAST-NEXT:    vinserti32x4 $2, %xmm3, %zmm28, %zmm3
+; AVX512BW-FAST-NEXT:    vpshufb %xmm1, %xmm5, %xmm3
+; AVX512BW-FAST-NEXT:    vmovdqa {{.*#+}} xmm7 = <4,128,u,u,u,7,128,5,128,u,u,u,8,128,6,128>
+; AVX512BW-FAST-NEXT:    vpshufb %xmm7, %xmm4, %xmm31
+; AVX512BW-FAST-NEXT:    vporq %xmm3, %xmm31, %xmm3
+; AVX512BW-FAST-NEXT:    vpunpckhbw {{.*#+}} xmm4 = xmm4[8],xmm5[8],xmm4[9],xmm5[9],xmm4[10],xmm5[10],xmm4[11],xmm5[11],xmm4[12],xmm5[12],xmm4[13],xmm5[13],xmm4[14],xmm5[14],xmm4[15],xmm5[15]
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} xmm4 = xmm4[u,6,7,2,3,u,u,u,8,9,4,5,u,u,u,10]
+; AVX512BW-FAST-NEXT:    vinserti32x4 $2, %xmm4, %zmm3, %zmm3
 ; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm4 = [2,2,2,4,2,2,2,4,3,3,3,3,2,2,2,4,52,53,52,53,53,54,53,54,52,53,52,53,53,54,53,54]
-; AVX512BW-FAST-NEXT:    vpermi2w %zmm26, %zmm13, %zmm4
+; AVX512BW-FAST-NEXT:    vpermi2w %zmm29, %zmm11, %zmm4
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm3 = zmm3[0,1,0,1,4,5,4,5]
 ; AVX512BW-FAST-NEXT:    movabsq $290499906672591364, %rax # imm = 0x408102040810204
 ; AVX512BW-FAST-NEXT:    kmovq %rax, %k2
 ; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm4, %zmm3 {%k2}
 ; AVX512BW-FAST-NEXT:    movabsq $-8714997200177740921, %rax # imm = 0x870E1C3870E1C387
 ; AVX512BW-FAST-NEXT:    kmovq %rax, %k2
-; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm3, %zmm24 {%k2}
-; AVX512BW-FAST-NEXT:    vpshufb %xmm5, %xmm16, %xmm3
-; AVX512BW-FAST-NEXT:    vpshufb %xmm0, %xmm14, %xmm0
+; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm3, %zmm25 {%k2}
+; AVX512BW-FAST-NEXT:    vpshufb %xmm6, %xmm15, %xmm3
+; AVX512BW-FAST-NEXT:    vpshufb %xmm0, %xmm13, %xmm0
 ; AVX512BW-FAST-NEXT:    vpor %xmm3, %xmm0, %xmm0
-; AVX512BW-FAST-NEXT:    vpunpcklbw {{.*#+}} xmm3 = xmm14[0],xmm16[0],xmm14[1],xmm16[1],xmm14[2],xmm16[2],xmm14[3],xmm16[3],xmm14[4],xmm16[4],xmm14[5],xmm16[5],xmm14[6],xmm16[6],xmm14[7],xmm16[7]
-; AVX512BW-FAST-NEXT:    vpshufb %xmm7, %xmm3, %xmm3
+; AVX512BW-FAST-NEXT:    vpunpcklbw {{.*#+}} xmm3 = xmm13[0],xmm15[0],xmm13[1],xmm15[1],xmm13[2],xmm15[2],xmm13[3],xmm15[3],xmm13[4],xmm15[4],xmm13[5],xmm15[5],xmm13[6],xmm15[6],xmm13[7],xmm15[7]
+; AVX512BW-FAST-NEXT:    vpshufb %xmm9, %xmm3, %xmm3
 ; AVX512BW-FAST-NEXT:    vinserti32x4 $2, %xmm0, %zmm3, %zmm0
-; AVX512BW-FAST-NEXT:    vpshufb %xmm2, %xmm19, %xmm2
-; AVX512BW-FAST-NEXT:    vpshufb %xmm31, %xmm18, %xmm3
+; AVX512BW-FAST-NEXT:    vpshufb %xmm2, %xmm18, %xmm2
+; AVX512BW-FAST-NEXT:    vpshufb %xmm19, %xmm17, %xmm3
 ; AVX512BW-FAST-NEXT:    vpor %xmm2, %xmm3, %xmm2
-; AVX512BW-FAST-NEXT:    vpunpcklbw {{.*#+}} xmm3 = xmm18[0],xmm19[0],xmm18[1],xmm19[1],xmm18[2],xmm19[2],xmm18[3],xmm19[3],xmm18[4],xmm19[4],xmm18[5],xmm19[5],xmm18[6],xmm19[6],xmm18[7],xmm19[7]
+; AVX512BW-FAST-NEXT:    vpunpcklbw {{.*#+}} xmm3 = xmm17[0],xmm18[0],xmm17[1],xmm18[1],xmm17[2],xmm18[2],xmm17[3],xmm18[3],xmm17[4],xmm18[4],xmm17[5],xmm18[5],xmm17[6],xmm18[6],xmm17[7],xmm18[7]
 ; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} xmm3 = xmm3[0,1,u,u,u,6,7,2,3,u,u,u,8,9,4,5]
 ; AVX512BW-FAST-NEXT:    vinserti32x4 $2, %xmm2, %zmm3, %zmm2
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm3 = zmm0[0,1,0,1,4,5,4,5]
@@ -8666,14 +8667,16 @@ define void @store_i8_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
 ; AVX512BW-FAST-NEXT:    movabsq $871499720017774092, %rax # imm = 0xC183060C183060C
 ; AVX512BW-FAST-NEXT:    kmovq %rax, %k2
 ; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm3, %zmm0 {%k2}
-; AVX512BW-FAST-NEXT:    vpshufb %xmm1, %xmm25, %xmm1
-; AVX512BW-FAST-NEXT:    vpshufb %xmm29, %xmm10, %xmm2
+; AVX512BW-FAST-NEXT:    vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 # 16-byte Reload
+; AVX512BW-FAST-NEXT:    vpshufb %xmm1, %xmm3, %xmm1
+; AVX512BW-FAST-NEXT:    vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm4 # 16-byte Reload
+; AVX512BW-FAST-NEXT:    vpshufb %xmm7, %xmm4, %xmm2
 ; AVX512BW-FAST-NEXT:    vpor %xmm1, %xmm2, %xmm1
-; AVX512BW-FAST-NEXT:    vpunpcklbw {{.*#+}} xmm2 = xmm10[0],xmm25[0],xmm10[1],xmm25[1],xmm10[2],xmm25[2],xmm10[3],xmm25[3],xmm10[4],xmm25[4],xmm10[5],xmm25[5],xmm10[6],xmm25[6],xmm10[7],xmm25[7]
-; AVX512BW-FAST-NEXT:    vpshufb %xmm8, %xmm2, %xmm2
+; AVX512BW-FAST-NEXT:    vpunpcklbw {{.*#+}} xmm2 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3],xmm4[4],xmm3[4],xmm4[5],xmm3[5],xmm4[6],xmm3[6],xmm4[7],xmm3[7]
+; AVX512BW-FAST-NEXT:    vpshufb %xmm12, %xmm2, %xmm2
 ; AVX512BW-FAST-NEXT:    vinserti32x4 $2, %xmm1, %zmm2, %zmm1
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm1 = zmm1[0,1,0,1,4,5,4,5]
-; AVX512BW-FAST-NEXT:    vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm26, %zmm2 # 32-byte Folded Reload
+; AVX512BW-FAST-NEXT:    vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm29, %zmm2 # 32-byte Folded Reload
 ; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm3 = [1,1,0,0,1,1,0,0,4,5,1,1,1,1,0,0,18,18,18,20,18,18,18,20,19,19,19,19,18,18,18,20]
 ; AVX512BW-FAST-NEXT:    vpermw %zmm2, %zmm3, %zmm3
 ; AVX512BW-FAST-NEXT:    movabsq $4647998506761461824, %rax # imm = 0x4081020408102040
@@ -8683,29 +8686,26 @@ define void @store_i8_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
 ; AVX512BW-FAST-NEXT:    kmovq %rax, %k2
 ; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm1, %zmm0 {%k2}
 ; AVX512BW-FAST-NEXT:    vmovdqu64 (%rsp), %zmm1 # 64-byte Reload
-; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm12, %zmm1, %zmm1
-; AVX512BW-FAST-NEXT:    vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload
-; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm11, %zmm3, %zmm3
+; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm10, %zmm1, %zmm1
+; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm14, %zmm24, %zmm3
 ; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} zmm1 = zmm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18,19,20,21],zero,zmm1[19],zero,zmm1[21,20,21,22],zero,zmm1[20],zero,zmm1[22,23,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,57],zero,zmm1[55],zero,zero,zero,zero,zmm1[58],zero,zmm1[56],zero,zero,zero,zero,zmm1[59],zero
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm1 = zmm1[2,3,2,3,6,7,6,7]
 ; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} zmm3 = zmm3[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,zmm3[21],zero,zmm3[19],zero,zero,zero,zero,zmm3[22],zero,zmm3[20],zero,zero,zmm3[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zmm3[55],zero,zero,zero,zero,zmm3[58],zero,zmm3[56],zero,zero,zero,zero,zmm3[59],zero,zmm3[57]
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm3 = zmm3[2,3,2,3,6,7,6,7]
 ; AVX512BW-FAST-NEXT:    vporq %zmm1, %zmm3, %zmm1
-; AVX512BW-FAST-NEXT:    vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm3 # 64-byte Reload
-; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm20, %zmm3, %zmm3
+; AVX512BW-FAST-NEXT:    vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm22, %zmm3 # 32-byte Folded Reload
 ; AVX512BW-FAST-NEXT:    vinserti64x4 $1, {{[-0-9]+}}(%r{{[sb]}}p), %zmm23, %zmm4 # 32-byte Folded Reload
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} zmm4 = zmm4[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zmm4[18],zero,zero,zero,zero,zmm4[21],zero,zmm4[19],zero,zero,zero,zero,zmm4[22],zero,zmm4[20,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zmm4[57],zero,zmm4[55],zero,zero,zero,zero,zmm4[58],zero,zmm4[56],zero,zero,zero,zero
 ; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} zmm3 = zmm3[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,18],zero,zmm3[18,19,20,21],zero,zmm3[19],zero,zmm3[25,26,27,22],zero,zmm3[20],zero,zmm3[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,56,57],zero,zmm3[55],zero,zmm3[53,54,55,58],zero,zmm3[56],zero,zmm3[60,61,58,59]
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm3 = zmm3[2,3,2,3,6,7,6,7]
-; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} zmm4 = zmm4[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zmm4[18],zero,zero,zero,zero,zmm4[21],zero,zmm4[19],zero,zero,zero,zero,zmm4[22],zero,zmm4[20,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zmm4[57],zero,zmm4[55],zero,zero,zero,zero,zmm4[58],zero,zmm4[56],zero,zero,zero,zero
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm4 = zmm4[2,3,2,3,6,7,6,7]
 ; AVX512BW-FAST-NEXT:    vporq %zmm3, %zmm4, %zmm3
 ; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm1, %zmm3 {%k1}
-; AVX512BW-FAST-NEXT:    vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload
-; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm9, %zmm1, %zmm1
-; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm15, %zmm21, %zmm4
+; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm21, %zmm27, %zmm1
+; AVX512BW-FAST-NEXT:    vinserti64x4 $1, %ymm30, %zmm26, %zmm4
+; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} zmm4 = zmm4[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zmm4[20],zero,zmm4[18],zero,zero,zero,zero,zmm4[21],zero,zmm4[19],zero,zero,zero,zero,zmm4[22,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,zmm4[57],zero,zmm4[55],zero,zero,zero,zero,zmm4[58],zero,zmm4[56],zero,zero
 ; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} zmm1 = zmm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,20],zero,zmm1[18],zero,zmm1[20,21,20,21],zero,zmm1[19],zero,zmm1[19,20,21,22],zero,zmm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,56,57,56,57],zero,zmm1[55],zero,zmm1[55,56,57,58],zero,zmm1[56],zero,zmm1[62,63]
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm1 = zmm1[2,3,2,3,6,7,6,7]
-; AVX512BW-FAST-NEXT:    vpshufb {{.*#+}} zmm4 = zmm4[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zmm4[20],zero,zmm4[18],zero,zero,zero,zero,zmm4[21],zero,zmm4[19],zero,zero,zero,zero,zmm4[22,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,zmm4[57],zero,zmm4[55],zero,zero,zero,zero,zmm4[58],zero,zmm4[56],zero,zero
 ; AVX512BW-FAST-NEXT:    vpermq {{.*#+}} zmm4 = zmm4[2,3,2,3,6,7,6,7]
 ; AVX512BW-FAST-NEXT:    vporq %zmm1, %zmm4, %zmm1
 ; AVX512BW-FAST-NEXT:    vmovdqa64 {{.*#+}} zmm4 = [10,9,9,10,10,9,9,10,9,10,14,15,10,9,9,10,27,29,28,27,28,29,29,28,27,29,28,27,28,29,29,28]
@@ -8718,13 +8718,13 @@ define void @store_i8_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
 ; AVX512BW-FAST-NEXT:    vmovdqu8 %zmm1, %zmm3 {%k1}
 ; AVX512BW-FAST-NEXT:    movq {{[0-9]+}}(%rsp), %rax
 ; AVX512BW-FAST-NEXT:    vmovdqa64 %zmm3, 128(%rax)
-; AVX512BW-FAST-NEXT:    vmovdqa64 %zmm17, 320(%rax)
+; AVX512BW-FAST-NEXT:    vmovdqa64 %zmm16, 320(%rax)
 ; AVX512BW-FAST-NEXT:    vmovdqa64 %zmm0, (%rax)
-; AVX512BW-FAST-NEXT:    vmovdqa64 %zmm24, 256(%rax)
-; AVX512BW-FAST-NEXT:    vmovdqa64 %zmm27, 192(%rax)
-; AVX512BW-FAST-NEXT:    vmovdqa64 %zmm6, 64(%rax)
-; AVX512BW-FAST-NEXT:    vmovdqa64 %zmm22, 384(%rax)
-; AVX512BW-FAST-NEXT:    addq $200, %rsp
+; AVX512BW-FAST-NEXT:    vmovdqa64 %zmm25, 256(%rax)
+; AVX512BW-FAST-NEXT:    vmovdqa64 %zmm28, 192(%rax)
+; AVX512BW-FAST-NEXT:    vmovdqa64 %zmm8, 64(%rax)
+; AVX512BW-FAST-NEXT:    vmovdqa64 %zmm20, 384(%rax)
+; AVX512BW-FAST-NEXT:    addq $72, %rsp
 ; AVX512BW-FAST-NEXT:    vzeroupper
 ; AVX512BW-FAST-NEXT:    retq
   %in.vec0 = load <64 x i8>, ptr %in.vecptr0, align 64
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-v192.ll b/llvm/test/CodeGen/X86/vector-shuffle-v192.ll
index dd1022151214..75c26f38eb9e 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-v192.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-v192.ll
@@ -214,23 +214,21 @@ define <64 x i8> @f2(ptr %p0) {
 ; AVX512F-NEXT:    vmovdqa 128(%rdi), %ymm4
 ; AVX512F-NEXT:    vpshufb {{.*#+}} ymm4 = ymm4[u,u,u,u,u,u,u,u,u,u,u,3,5,9,11,15,17,21,23,27,29],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
 ; AVX512F-NEXT:    vinserti64x4 $1, %ymm4, %zmm2, %zmm2
-; AVX512F-NEXT:    vbroadcasti64x4 {{.*#+}} zmm4 = [255,255,255,255,255,255,255,255,255,255,255,0,0,0,0,0,0,0,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,0,0,0,0,0,0,0,0,0,255,255,255,255,255,255,255,255,255,255,255]
-; AVX512F-NEXT:    # zmm4 = mem[0,1,2,3,0,1,2,3]
-; AVX512F-NEXT:    vpternlogq $234, %zmm2, %zmm0, %zmm4
+; AVX512F-NEXT:    vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm2
 ; AVX512F-NEXT:    vmovdqa 96(%rdi), %xmm0
 ; AVX512F-NEXT:    vpshufb %xmm5, %xmm0, %xmm0
-; AVX512F-NEXT:    vmovdqa 112(%rdi), %xmm2
-; AVX512F-NEXT:    vpshufb %xmm6, %xmm2, %xmm2
-; AVX512F-NEXT:    vpor %xmm0, %xmm2, %xmm0
+; AVX512F-NEXT:    vmovdqa 112(%rdi), %xmm4
+; AVX512F-NEXT:    vpshufb %xmm6, %xmm4, %xmm4
+; AVX512F-NEXT:    vpor %xmm0, %xmm4, %xmm0
 ; AVX512F-NEXT:    vinserti32x4 $2, %xmm0, %zmm0, %zmm0
-; AVX512F-NEXT:    vmovdqa 80(%rdi), %xmm2
-; AVX512F-NEXT:    vpshufb %xmm1, %xmm2, %xmm1
-; AVX512F-NEXT:    vmovdqa 64(%rdi), %xmm2
-; AVX512F-NEXT:    vpshufb %xmm3, %xmm2, %xmm2
-; AVX512F-NEXT:    vpor %xmm1, %xmm2, %xmm1
+; AVX512F-NEXT:    vmovdqa 80(%rdi), %xmm4
+; AVX512F-NEXT:    vpshufb %xmm1, %xmm4, %xmm1
+; AVX512F-NEXT:    vmovdqa 64(%rdi), %xmm4
+; AVX512F-NEXT:    vpshufb %xmm3, %xmm4, %xmm3
+; AVX512F-NEXT:    vpor %xmm1, %xmm3, %xmm1
 ; AVX512F-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm1
 ; AVX512F-NEXT:    vshufi64x2 {{.*#+}} zmm0 = zmm1[0,1,2,3],zmm0[4,5,6,7]
-; AVX512F-NEXT:    vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm4, %zmm0
+; AVX512F-NEXT:    vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm0
 ; AVX512F-NEXT:    retq
 ;
 ; AVX512BW-LABEL: f2:
@@ -253,11 +251,9 @@ define <64 x i8> @f2(ptr %p0) {
 ; AVX512BW-NEXT:    vinserti64x4 $1, %ymm0, %zmm2, %zmm0
 ; AVX512BW-NEXT:    vmovdqa 32(%rdi), %ymm2
 ; AVX512BW-NEXT:    vinserti64x4 $1, 128(%rdi), %zmm2, %zmm2
-; AVX512BW-NEXT:    vbroadcasti64x4 {{.*#+}} zmm4 = <u,u,u,u,u,u,u,u,u,u,u,3,5,9,11,15,1,5,7,11,13,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,3,5,9,11,15,1,5,7,11,13,u,u,u,u,u,u,u,u,u,u,u>
-; AVX512BW-NEXT:    # zmm4 = mem[0,1,2,3,0,1,2,3]
 ; AVX512BW-NEXT:    movabsq $8998403163813888, %rax # imm = 0x1FF800001FF800
 ; AVX512BW-NEXT:    kmovq %rax, %k1
-; AVX512BW-NEXT:    vpshufb %zmm4, %zmm2, %zmm0 {%k1}
+; AVX512BW-NEXT:    vpshufb {{.*#+}} zmm0 {%k1} = zmm2[u,u,u,u,u,u,u,u,u,u,u,3,5,9,11,15,17,21,23,27,29,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,35,37,41,43,47,49,53,55,59,61,u,u,u,u,u,u,u,u,u,u,u]
 ; AVX512BW-NEXT:    vmovdqa 96(%rdi), %xmm2
 ; AVX512BW-NEXT:    vpshufb %xmm5, %xmm2, %xmm2
 ; AVX512BW-NEXT:    vmovdqa 112(%rdi), %xmm4
@@ -501,23 +497,21 @@ define <64 x i8> @f4(ptr %p0) {
 ; AVX512F-NEXT:    vmovdqa 128(%rdi), %ymm4
 ; AVX512F-NEXT:    vpshufb {{.*#+}} ymm4 = ymm4[u,u,u,u,u,u,u,u,u,u,u,2,4,8,10,14,16,20,22,26,28],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
 ; AVX512F-NEXT:    vinserti64x4 $1, %ymm4, %zmm2, %zmm2
-; AVX512F-NEXT:    vbroadcasti64x4 {{.*#+}} zmm4 = [255,255,255,255,255,255,255,255,255,255,255,0,0,0,0,0,0,0,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,0,0,0,0,0,0,0,0,0,255,255,255,255,255,255,255,255,255,255,255]
-; AVX512F-NEXT:    # zmm4 = mem[0,1,2,3,0,1,2,3]
-; AVX512F-NEXT:    vpternlogq $234, %zmm2, %zmm0, %zmm4
+; AVX512F-NEXT:    vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm2
 ; AVX512F-NEXT:    vmovdqa 96(%rdi), %xmm0
 ; AVX512F-NEXT:    vpshufb %xmm5, %xmm0, %xmm0
-; AVX512F-NEXT:    vmovdqa 112(%rdi), %xmm2
-; AVX512F-NEXT:    vpshufb %xmm6, %xmm2, %xmm2
-; AVX512F-NEXT:    vpor %xmm0, %xmm2, %xmm0
+; AVX512F-NEXT:    vmovdqa 112(%rdi), %xmm4
+; AVX512F-NEXT:    vpshufb %xmm6, %xmm4, %xmm4
+; AVX512F-NEXT:    vpor %xmm0, %xmm4, %xmm0
 ; AVX512F-NEXT:    vinserti32x4 $2, %xmm0, %zmm0, %zmm0
-; AVX512F-NEXT:    vmovdqa 80(%rdi), %xmm2
-; AVX512F-NEXT:    vpshufb %xmm1, %xmm2, %xmm1
-; AVX512F-NEXT:    vmovdqa 64(%rdi), %xmm2
-; AVX512F-NEXT:    vpshufb %xmm3, %xmm2, %xmm2
-; AVX512F-NEXT:    vpor %xmm1, %xmm2, %xmm1
+; AVX512F-NEXT:    vmovdqa 80(%rdi), %xmm4
+; AVX512F-NEXT:    vpshufb %xmm1, %xmm4, %xmm1
+; AVX512F-NEXT:    vmovdqa 64(%rdi), %xmm4
+; AVX512F-NEXT:    vpshufb %xmm3, %xmm4, %xmm3
+; AVX512F-NEXT:    vpor %xmm1, %xmm3, %xmm1
 ; AVX512F-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm1
 ; AVX512F-NEXT:    vshufi64x2 {{.*#+}} zmm0 = zmm1[0,1,2,3],zmm0[4,5,6,7]
-; AVX512F-NEXT:    vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm4, %zmm0
+; AVX512F-NEXT:    vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm0
 ; AVX512F-NEXT:    retq
 ;
 ; AVX512BW-LABEL: f4:
@@ -540,11 +534,9 @@ define <64 x i8> @f4(ptr %p0) {
 ; AVX512BW-NEXT:    vinserti64x4 $1, %ymm0, %zmm2, %zmm0
 ; AVX512BW-NEXT:    vmovdqa 32(%rdi), %ymm2
 ; AVX512BW-NEXT:    vinserti64x4 $1, 128(%rdi), %zmm2, %zmm2
-; AVX512BW-NEXT:    vbroadcasti64x4 {{.*#+}} zmm4 = <u,u,u,u,u,u,u,u,u,u,u,2,4,8,10,14,0,4,6,10,12,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,2,4,8,10,14,0,4,6,10,12,u,u,u,u,u,u,u,u,u,u,u>
-; AVX512BW-NEXT:    # zmm4 = mem[0,1,2,3,0,1,2,3]
 ; AVX512BW-NEXT:    movabsq $8998403163813888, %rax # imm = 0x1FF800001FF800
 ; AVX512BW-NEXT:    kmovq %rax, %k1
-; AVX512BW-NEXT:    vpshufb %zmm4, %zmm2, %zmm0 {%k1}
+; AVX512BW-NEXT:    vpshufb {{.*#+}} zmm0 {%k1} = zmm2[u,u,u,u,u,u,u,u,u,u,u,2,4,8,10,14,16,20,22,26,28,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,34,36,40,42,46,48,52,54,58,60,u,u,u,u,u,u,u,u,u,u,u]
 ; AVX512BW-NEXT:    vmovdqa 96(%rdi), %xmm2
 ; AVX512BW-NEXT:    vpshufb %xmm5, %xmm2, %xmm2
 ; AVX512BW-NEXT:    vmovdqa 112(%rdi), %xmm4
diff --git a/llvm/test/CodeGen/X86/x86-interleaved-access.ll b/llvm/test/CodeGen/X86/x86-interleaved-access.ll
index 216332943993..4f20a9d5db6a 100644
--- a/llvm/test/CodeGen/X86/x86-interleaved-access.ll
+++ b/llvm/test/CodeGen/X86/x86-interleaved-access.ll
@@ -1054,8 +1054,8 @@ define void @interleaved_store_vf32_i8_stride3(<32 x i8> %a, <32 x i8> %b, <32 x
 ; AVX512-NEXT:    vinserti128 $1, %xmm0, %ymm1, %ymm3
 ; AVX512-NEXT:    vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm1[4,5,6,7]
 ; AVX512-NEXT:    vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],ymm2[2,3]
-; AVX512-NEXT:    vbroadcasti64x4 {{.*#+}} zmm2 = [0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5,0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5,0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5,0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5]
-; AVX512-NEXT:    # zmm2 = mem[0,1,2,3,0,1,2,3]
+; AVX512-NEXT:    vbroadcasti32x4 {{.*#+}} zmm2 = [0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5,0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5,0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5,0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5]
+; AVX512-NEXT:    # zmm2 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
 ; AVX512-NEXT:    vpshufb %ymm2, %ymm0, %ymm0
 ; AVX512-NEXT:    vinserti64x4 $1, %ymm1, %zmm3, %zmm1
 ; AVX512-NEXT:    vpshufb %zmm2, %zmm1, %zmm1
@@ -1252,8 +1252,8 @@ define void @interleaved_store_vf64_i8_stride3(<64 x i8> %a, <64 x i8> %b, <64 x
 ; AVX512-NEXT:    vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm1[4,5,6,7]
 ; AVX512-NEXT:    vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],ymm2[2,3]
 ; AVX512-NEXT:    vinserti64x4 $1, %ymm4, %zmm3, %zmm2
-; AVX512-NEXT:    vbroadcasti64x4 {{.*#+}} zmm3 = [0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5,0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5,0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5,0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5]
-; AVX512-NEXT:    # zmm3 = mem[0,1,2,3,0,1,2,3]
+; AVX512-NEXT:    vbroadcasti32x4 {{.*#+}} zmm3 = [0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5,0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5,0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5,0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5]
+; AVX512-NEXT:    # zmm3 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
 ; AVX512-NEXT:    vpshufb %zmm3, %zmm2, %zmm2
 ; AVX512-NEXT:    vinserti64x4 $1, %ymm6, %zmm5, %zmm4
 ; AVX512-NEXT:    vpshufb %zmm3, %zmm4, %zmm4
-- 
GitLab


From 33819f3bfb9cd14f3d9603ac4698f55cd2f285b8 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Mon, 11 Dec 2023 16:22:52 +0000
Subject: [PATCH 135/349] [X86] X86FixupVectorConstants - create f32/f64
 broadcast constants if the source constant data was ANY floating point type

We don't need an exact match, this is mainly cleanup for cases where v2f32 style types have been cast to f64 etc.
---
 llvm/lib/Target/X86/X86FixupVectorConstants.cpp | 17 +++++++++--------
 llvm/test/CodeGen/X86/combine-concatvectors.ll  |  2 +-
 2 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/llvm/lib/Target/X86/X86FixupVectorConstants.cpp b/llvm/lib/Target/X86/X86FixupVectorConstants.cpp
index 4b6038cb5938..5cc3b26dddaf 100644
--- a/llvm/lib/Target/X86/X86FixupVectorConstants.cpp
+++ b/llvm/lib/Target/X86/X86FixupVectorConstants.cpp
@@ -190,12 +190,13 @@ static Constant *rebuildSplatableConstant(const Constant *C,
   Type *SclTy = OriginalType->getScalarType();
   unsigned NumSclBits = SclTy->getPrimitiveSizeInBits();
   NumSclBits = std::min<unsigned>(NumSclBits, SplatBitWidth);
+  LLVMContext &Ctx = OriginalType->getContext();
 
   if (NumSclBits == 8) {
     SmallVector<uint8_t> RawBits;
     for (unsigned I = 0; I != SplatBitWidth; I += 8)
       RawBits.push_back(Splat->extractBits(8, I).getZExtValue());
-    return ConstantDataVector::get(OriginalType->getContext(), RawBits);
+    return ConstantDataVector::get(Ctx, RawBits);
   }
 
   if (NumSclBits == 16) {
@@ -204,25 +205,25 @@ static Constant *rebuildSplatableConstant(const Constant *C,
       RawBits.push_back(Splat->extractBits(16, I).getZExtValue());
     if (SclTy->is16bitFPTy())
       return ConstantDataVector::getFP(SclTy, RawBits);
-    return ConstantDataVector::get(OriginalType->getContext(), RawBits);
+    return ConstantDataVector::get(Ctx, RawBits);
   }
 
   if (NumSclBits == 32) {
     SmallVector<uint32_t> RawBits;
     for (unsigned I = 0; I != SplatBitWidth; I += 32)
       RawBits.push_back(Splat->extractBits(32, I).getZExtValue());
-    if (SclTy->isFloatTy())
-      return ConstantDataVector::getFP(SclTy, RawBits);
-    return ConstantDataVector::get(OriginalType->getContext(), RawBits);
+    if (SclTy->isFloatingPointTy())
+      return ConstantDataVector::getFP(Type::getFloatTy(Ctx), RawBits);
+    return ConstantDataVector::get(Ctx, RawBits);
   }
 
   // Fallback to i64 / double.
   SmallVector<uint64_t> RawBits;
   for (unsigned I = 0; I != SplatBitWidth; I += 64)
     RawBits.push_back(Splat->extractBits(64, I).getZExtValue());
-  if (SclTy->isDoubleTy())
-    return ConstantDataVector::getFP(SclTy, RawBits);
-  return ConstantDataVector::get(OriginalType->getContext(), RawBits);
+  if (SclTy->isFloatingPointTy())
+    return ConstantDataVector::getFP(Type::getDoubleTy(Ctx), RawBits);
+  return ConstantDataVector::get(Ctx, RawBits);
 }
 
 bool X86FixupVectorConstantsPass::processInstruction(MachineFunction &MF,
diff --git a/llvm/test/CodeGen/X86/combine-concatvectors.ll b/llvm/test/CodeGen/X86/combine-concatvectors.ll
index 8a0e39c57b78..31eaa1b205aa 100644
--- a/llvm/test/CodeGen/X86/combine-concatvectors.ll
+++ b/llvm/test/CodeGen/X86/combine-concatvectors.ll
@@ -48,7 +48,7 @@ define void @concat_of_broadcast_v2f64_v4f64() {
 ; AVX1-NEXT:    movl $1091567616, 30256(%rax) # imm = 0x41100000
 ; AVX1-NEXT:    movabsq $4294967297, %rcx # imm = 0x100000001
 ; AVX1-NEXT:    movq %rcx, 46348(%rax)
-; AVX1-NEXT:    vbroadcastss {{.*#+}} ymm0 = [1065353216,1065353216,1065353216,1065353216,1065353216,1065353216,1065353216,1065353216]
+; AVX1-NEXT:    vbroadcastss {{.*#+}} ymm0 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
 ; AVX1-NEXT:    vmovups %ymm0, 48296(%rax)
 ; AVX1-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX1-NEXT:    vmovsd %xmm0, 47372(%rax)
-- 
GitLab


From 607f19cb947a25fe7ed131d983a90961f3c2541a Mon Sep 17 00:00:00 2001
From: Timm Baeder <tbaeder@redhat.com>
Date: Mon, 11 Dec 2023 17:25:03 +0100
Subject: [PATCH 136/349] [clang][Interp] Fix float->int casts overflowing
 (#72658)

If S.noteUndefinedBehavior() returns true, we will continue evaluation
and need a value on the stack.
---
 clang/lib/AST/Interp/Interp.h    | 6 +++++-
 clang/test/AST/Interp/floats.cpp | 4 ++++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/clang/lib/AST/Interp/Interp.h b/clang/lib/AST/Interp/Interp.h
index 4f7778bdd2ff..6cf122f2ba55 100644
--- a/clang/lib/AST/Interp/Interp.h
+++ b/clang/lib/AST/Interp/Interp.h
@@ -1619,7 +1619,11 @@ bool CastFloatingIntegral(InterpState &S, CodePtr OpPC) {
       QualType Type = E->getType();
 
       S.CCEDiag(E, diag::note_constexpr_overflow) << F.getAPFloat() << Type;
-      return S.noteUndefinedBehavior();
+      if (S.noteUndefinedBehavior()) {
+        S.Stk.push<T>(T(Result));
+        return true;
+      }
+      return false;
     }
 
     S.Stk.push<T>(T(Result));
diff --git a/clang/test/AST/Interp/floats.cpp b/clang/test/AST/Interp/floats.cpp
index e17167f5bf6d..45c31c759e47 100644
--- a/clang/test/AST/Interp/floats.cpp
+++ b/clang/test/AST/Interp/floats.cpp
@@ -39,6 +39,10 @@ constexpr float m = 5.0f / 0.0f; // ref-error {{must be initialized by a constan
 static_assert(~2.0f == 3, ""); // ref-error {{invalid argument type 'float' to unary expression}} \
                                // expected-error {{invalid argument type 'float' to unary expression}}
 
+
+typedef int tdb[(long long)4e20]; //expected-error {{variable length}} \
+                                  //ref-error {{variable length}}
+
 /// Initialized by a double.
 constexpr float df = 0.0;
 /// The other way around.
-- 
GitLab


From 07056c227456a63893cc809fadf62537863cb92d Mon Sep 17 00:00:00 2001
From: Jonas Paulsson <paulson1@linux.ibm.com>
Date: Mon, 11 Dec 2023 17:28:12 +0100
Subject: [PATCH 137/349] [SystemZ]  Use LCGR/AGHI for i64 XOR with -1 (#74882)

LCGR/AGHI is a more compact way of implementing a 64-bit NOT.
---
 .../Target/SystemZ/SystemZISelDAGToDAG.cpp    |  3 +
 llvm/lib/Target/SystemZ/SystemZInstrInfo.td   |  4 ++
 .../test/CodeGen/SystemZ/atomicrmw-nand-04.ll | 69 +++++++++----------
 llvm/test/CodeGen/SystemZ/xor-04.ll           |  4 +-
 4 files changed, 43 insertions(+), 37 deletions(-)

diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
index 4cc69530db01..0d8d5451b813 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -1558,6 +1558,9 @@ void SystemZDAGToDAGISel::Select(SDNode *Node) {
                 break;
           }
         }
+        // Don't split an XOR with -1 as LCGR/AGHI is more compact.
+        if (Opcode == ISD::XOR && Op1->isAllOnes())
+          break;
         if (!SystemZ::isImmLF(Val) && !SystemZ::isImmHF(Val)) {
           splitLargeImmediate(Opcode, Node, Node->getOperand(0),
                               Val - uint32_t(Val), uint32_t(Val));
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index 210e6a51b6dc..937e36057a6e 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -2263,6 +2263,10 @@ let isCodeGenOnly = 1, hasSideEffects = 1 in {
 def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y),
                           (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>;
 
+// Use LCGR/AGHI for i64 xor with -1.
+def : Pat<(xor GR64:$x, (i64 -1)),
+          (AGHI (LCGR GR64:$x), (i64 -1))>;
+
 // Shift/rotate instructions only use the last 6 bits of the second operand
 // register, so we can safely use NILL (16 fewer bits than NILF) to only AND the
 // last 16 bits.
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-nand-04.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-nand-04.ll
index 98056c9c9a01..3ff259d5576c 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-nand-04.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-nand-04.ll
@@ -9,8 +9,8 @@ define i64 @f1(i64 %dummy, ptr %src, i64 %b) {
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lgr %r0, %r2
 ; CHECK: ngr %r0, %r4
-; CHECK: xihf %r0, 4294967295
-; CHECK: xilf %r0, 4294967295
+; CHECK: lcgr %r0, %r0
+; CHECK: aghi %r0, -1
 ; CHECK: csg %r2, %r0, 0(%r3)
 ; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
@@ -21,8 +21,8 @@ define i64 @f1(i64 %dummy, ptr %src, i64 %b) {
 ; Check NANDs of 1, which are done using a register.
 define i64 @f2(i64 %dummy, ptr %src) {
 ; CHECK-LABEL: f2:
-; CHECK: xihf %r0, 4294967295
-; CHECK: xilf %r0, 4294967295
+; CHECK: lcgr %r0, %r2
+; CHECK: aghi %r0, -1
 ; CHECK: oihf %r0, 4294967295
 ; CHECK: oilf %r0, 4294967294
 ; CHECK: br %r14
@@ -34,8 +34,8 @@ define i64 @f3(i64 %dummy, ptr %src) {
 ; CHECK-LABEL: f3:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
-; CHECK: xihf %r0, 4294967295
-; CHECK: xilf %r0, 4294967295
+; CHECK: lcgr %r0, %r2
+; CHECK: aghi %r0, -1
 ; CHECK: oihf %r0, 4294967294
 ; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
@@ -47,9 +47,8 @@ define i64 @f4(i64 %dummy, ptr %src) {
 ; CHECK-LABEL: f4:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
-; CHECK: lgr %r0, %r2
-; CHECK: xihf %r0, 4294967295
-; CHECK: xilf %r0, 4294967295
+; CHECK: lcgr %r0, %r2
+; CHECK: aghi %r0, -1
 ; CHECK: oihf %r0, 4294967293
 ; CHECK: csg %r2, %r0, 0(%r3)
 ; CHECK: jl [[LABEL]]
@@ -60,8 +59,8 @@ define i64 @f4(i64 %dummy, ptr %src) {
 
 define i64 @f5(i64 %dummy, ptr %src) {
 ; CHECK-LABEL: f5:
-; CHECK: xihf %r0, 4294967295
-; CHECK: xilf %r0, 4294967295
+; CHECK: lcgr %r0, %r2
+; CHECK: aghi %r0, -1
 ; CHECK: oihf %r0, 4294967292
 ; CHECK: oilf %r0, 4294967295
 ; CHECK: br %r14
@@ -71,8 +70,8 @@ define i64 @f5(i64 %dummy, ptr %src) {
 
 define i64 @f6(i64 %dummy, ptr %src) {
 ; CHECK-LABEL: f6:
-; CHECK: xihf %r0, 4294967295
-; CHECK: xilf %r0, 4294967295
+; CHECK: lcgr %r0, %r2
+; CHECK: aghi %r0, -1
 ; CHECK: oihh %r0, 65533
 ; CHECK: br %r14
   %res = atomicrmw nand ptr %src, i64 844424930131967 seq_cst
@@ -81,8 +80,8 @@ define i64 @f6(i64 %dummy, ptr %src) {
 
 define i64 @f7(i64 %dummy, ptr %src) {
 ; CHECK-LABEL: f7:
-; CHECK: xihf %r0, 4294967295
-; CHECK: xilf %r0, 4294967295
+; CHECK: lcgr %r0, %r2
+; CHECK: aghi %r0, -1
 ; CHECK: oihf %r0, 4294901759
 ; CHECK: oilf %r0, 4294967295
 ; CHECK: br %r14
@@ -92,8 +91,8 @@ define i64 @f7(i64 %dummy, ptr %src) {
 
 define i64 @f8(i64 %dummy, ptr %src) {
 ; CHECK-LABEL: f8:
-; CHECK: xihf %r0, 4294967295
-; CHECK: xilf %r0, 4294967295
+; CHECK: lcgr %r0, %r2
+; CHECK: aghi %r0, -1
 ; CHECK: oill %r0, 5
 ; CHECK: br %r14
   %res = atomicrmw nand ptr %src, i64 -6 seq_cst
@@ -102,8 +101,8 @@ define i64 @f8(i64 %dummy, ptr %src) {
 
 define i64 @f9(i64 %dummy, ptr %src) {
 ; CHECK-LABEL: f9:
-; CHECK: xihf %r0, 4294967295
-; CHECK: xilf %r0, 4294967295
+; CHECK: lcgr %r0, %r2
+; CHECK: aghi %r0, -1
 ; CHECK: oill %r0, 65533
 ; CHECK: br %r14
   %res = atomicrmw nand ptr %src, i64 -65534 seq_cst
@@ -112,8 +111,8 @@ define i64 @f9(i64 %dummy, ptr %src) {
 
 define i64 @f10(i64 %dummy, ptr %src) {
 ; CHECK-LABEL: f10:
-; CHECK: xihf %r0, 4294967295
-; CHECK: xilf %r0, 4294967295
+; CHECK: lcgr %r0, %r2
+; CHECK: aghi %r0, -1
 ; CHECK: oilf %r0, 65537
 ; CHECK: br %r14
   %res = atomicrmw nand ptr %src, i64 -65538 seq_cst
@@ -122,8 +121,8 @@ define i64 @f10(i64 %dummy, ptr %src) {
 
 define i64 @f11(i64 %dummy, ptr %src) {
 ; CHECK-LABEL: f11:
-; CHECK: xihf %r0, 4294967295
-; CHECK: xilf %r0, 4294967295
+; CHECK: lcgr %r0, %r2
+; CHECK: aghi %r0, -1
 ; CHECK: oilh %r0, 5
 ; CHECK: br %r14
   %res = atomicrmw nand ptr %src, i64 -327681 seq_cst
@@ -132,8 +131,8 @@ define i64 @f11(i64 %dummy, ptr %src) {
 
 define i64 @f12(i64 %dummy, ptr %src) {
 ; CHECK-LABEL: f12:
-; CHECK: xihf %r0, 4294967295
-; CHECK: xilf %r0, 4294967295
+; CHECK: lcgr %r0, %r2
+; CHECK: aghi %r0, -1
 ; CHECK: oilh %r0, 65533
 ; CHECK: br %r14
   %res = atomicrmw nand ptr %src, i64 -4294770689 seq_cst
@@ -142,8 +141,8 @@ define i64 @f12(i64 %dummy, ptr %src) {
 
 define i64 @f13(i64 %dummy, ptr %src) {
 ; CHECK-LABEL: f13:
-; CHECK: xihf %r0, 4294967295
-; CHECK: xilf %r0, 4294967295
+; CHECK: lcgr %r0, %r2
+; CHECK: aghi %r0, -1
 ; CHECK: oilf %r0, 4294967293
 ; CHECK: br %r14
   %res = atomicrmw nand ptr %src, i64 -4294967294 seq_cst
@@ -152,8 +151,8 @@ define i64 @f13(i64 %dummy, ptr %src) {
 
 define i64 @f14(i64 %dummy, ptr %src) {
 ; CHECK-LABEL: f14:
-; CHECK: xihf %r0, 4294967295
-; CHECK: xilf %r0, 4294967295
+; CHECK: lcgr %r0, %r2
+; CHECK: aghi %r0, -1
 ; CHECK: oihl %r0, 5
 ; CHECK: br %r14
   %res = atomicrmw nand ptr %src, i64 -21474836481 seq_cst
@@ -162,8 +161,8 @@ define i64 @f14(i64 %dummy, ptr %src) {
 
 define i64 @f15(i64 %dummy, ptr %src) {
 ; CHECK-LABEL: f15:
-; CHECK: xihf %r0, 4294967295
-; CHECK: xilf %r0, 4294967295
+; CHECK: lcgr %r0, %r2
+; CHECK: aghi %r0, -1
 ; CHECK: oihl %r0, 65533
 ; CHECK: br %r14
   %res = atomicrmw nand ptr %src, i64 -281462091808769 seq_cst
@@ -172,8 +171,8 @@ define i64 @f15(i64 %dummy, ptr %src) {
 
 define i64 @f16(i64 %dummy, ptr %src) {
 ; CHECK-LABEL: f16:
-; CHECK: xihf %r0, 4294967295
-; CHECK: xilf %r0, 4294967295
+; CHECK: lcgr %r0, %r2
+; CHECK: aghi %r0, -1
 ; CHECK: oihh %r0, 5
 ; CHECK: br %r14
   %res = atomicrmw nand ptr %src, i64 -1407374883553281 seq_cst
@@ -182,8 +181,8 @@ define i64 @f16(i64 %dummy, ptr %src) {
 
 define i64 @f17(i64 %dummy, ptr %src) {
 ; CHECK-LABEL: f17:
-; CHECK: xihf %r0, 4294967295
-; CHECK: xilf %r0, 4294967295
+; CHECK: lcgr %r0, %r2
+; CHECK: aghi %r0, -1
 ; CHECK: oihf %r0, 65537
 ; CHECK: br %r14
   %res = atomicrmw nand ptr %src, i64 -281479271677953 seq_cst
diff --git a/llvm/test/CodeGen/SystemZ/xor-04.ll b/llvm/test/CodeGen/SystemZ/xor-04.ll
index 44f0a4cc39d0..ce5b76507b0d 100644
--- a/llvm/test/CodeGen/SystemZ/xor-04.ll
+++ b/llvm/test/CodeGen/SystemZ/xor-04.ll
@@ -61,8 +61,8 @@ define i64 @f6(i64 %a) {
 ; Check full bitwise negation
 define i64 @f7(i64 %a) {
 ; CHECK-LABEL: f7:
-; CHECK: xihf %r2, 4294967295
-; CHECK: xilf %r2, 4294967295
+; CHECK: lcgr %r2, %r2
+; CHECK: aghi %r2, -1
 ; CHECK: br %r14
   %xor = xor i64 %a, -1
   ret i64 %xor
-- 
GitLab


From 898db1136e67939e075c502eebc0fbb5ab168e50 Mon Sep 17 00:00:00 2001
From: Philip Reames <preames@rivosinc.com>
Date: Mon, 11 Dec 2023 08:34:02 -0800
Subject: [PATCH 138/349] [flang] Support -mvscale-min and mvscale-max on all
 targets (#74633)

We have other targets with scalable vectors (e.g.RISC-V), and there
doesn't seem to be any particular reason these options can't be used on
those targets.
---
 flang/lib/Frontend/FrontendActions.cpp        | 14 +++++--------
 .../RISCV/riscv-vector-bits-vscale-range.f90  | 21 +++++++++++++++++++
 2 files changed, 26 insertions(+), 9 deletions(-)
 create mode 100644 flang/test/Lower/RISCV/riscv-vector-bits-vscale-range.f90

diff --git a/flang/lib/Frontend/FrontendActions.cpp b/flang/lib/Frontend/FrontendActions.cpp
index 0b6708f47951..d4a3e164d207 100644
--- a/flang/lib/Frontend/FrontendActions.cpp
+++ b/flang/lib/Frontend/FrontendActions.cpp
@@ -710,8 +710,8 @@ void CodeGenAction::lowerHLFIRToFIR() {
 // TODO: We should get this from TargetInfo. However, that depends on
 // too much of clang, so for now, replicate the functionality.
 static std::optional<std::pair<unsigned, unsigned>>
-getVScaleRange(CompilerInstance &ci,
-               const Fortran::frontend::LangOptions &langOpts) {
+getVScaleRange(CompilerInstance &ci) {
+  const auto &langOpts = ci.getInvocation().getLangOpts();
   if (langOpts.VScaleMin || langOpts.VScaleMax)
     return std::pair<unsigned, unsigned>(
         langOpts.VScaleMin ? langOpts.VScaleMin : 1, langOpts.VScaleMax);
@@ -746,13 +746,9 @@ void CodeGenAction::generateLLVMIR() {
   const auto targetOpts = ci.getInvocation().getTargetOpts();
   const llvm::Triple triple(targetOpts.triple);
 
-  // Only get the vscale range if AArch64.
-  if (triple.isAArch64()) {
-    auto langOpts = ci.getInvocation().getLangOpts();
-    if (auto vsr = getVScaleRange(ci, langOpts)) {
-      config.VScaleMin = vsr->first;
-      config.VScaleMax = vsr->second;
-    }
+  if (auto vsr = getVScaleRange(ci)) {
+    config.VScaleMin = vsr->first;
+    config.VScaleMax = vsr->second;
   }
 
   // Create the pass pipeline
diff --git a/flang/test/Lower/RISCV/riscv-vector-bits-vscale-range.f90 b/flang/test/Lower/RISCV/riscv-vector-bits-vscale-range.f90
new file mode 100644
index 000000000000..b08ad91feb38
--- /dev/null
+++ b/flang/test/Lower/RISCV/riscv-vector-bits-vscale-range.f90
@@ -0,0 +1,21 @@
+! REQUIRES: riscv-registered-target
+! RUN: %flang_fc1 -triple riscv64-none-linux-gnu -target-feature +v -mvscale-min=1 -mvscale-max=1  -emit-llvm -o - %s | FileCheck %s -D#VBITS=1
+! RUN: %flang_fc1 -triple riscv64-none-linux-gnu -target-feature +v -mvscale-min=2 -mvscale-max=2  -emit-llvm -o - %s | FileCheck %s -D#VBITS=2
+! RUN: %flang_fc1 -triple riscv64-none-linux-gnu -target-feature +v -mvscale-min=4 -mvscale-max=4  -emit-llvm -o - %s | FileCheck %s -D#VBITS=4
+! RUN: %flang_fc1 -triple riscv64-none-linux-gnu -target-feature +v -mvscale-min=8 -mvscale-max=8  -emit-llvm -o - %s | FileCheck %s -D#VBITS=8
+! RUN: %flang_fc1 -triple riscv64-none-linux-gnu -target-feature +v -mvscale-min=16 -mvscale-max=16  -emit-llvm -o - %s | FileCheck %s -D#VBITS=16
+! RUN: %flang_fc1 -triple riscv64-none-linux-gnu -target-feature +v -mvscale-min=1  -emit-llvm -o - %s | FileCheck %s -D#VBITS=1 --check-prefix=CHECK-NOMAX
+! RUN: %flang_fc1 -triple riscv64-none-linux-gnu -target-feature +v -mvscale-min=2  -emit-llvm -o - %s | FileCheck %s -D#VBITS=2 --check-prefix=CHECK-NOMAX
+! RUN: %flang_fc1 -triple riscv64-none-linux-gnu -target-feature +v -mvscale-min=4  -emit-llvm -o - %s | FileCheck %s -D#VBITS=4 --check-prefix=CHECK-NOMAX
+! RUN: %flang_fc1 -triple riscv64-none-linux-gnu -target-feature +v -mvscale-min=8  -emit-llvm -o - %s | FileCheck %s -D#VBITS=8 --check-prefix=CHECK-NOMAX
+! RUN: %flang_fc1 -triple riscv64-none-linux-gnu -target-feature +v -mvscale-min=16  -emit-llvm -o - %s | FileCheck %s -D#VBITS=16 --check-prefix=CHECK-NOMAX
+! RUN: %flang_fc1 -triple riscv64-none-linux-gnu -target-feature +v -mvscale-min=1 -mvscale-max=0  -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-UNBOUNDED
+! RUN: %flang_fc1 -triple riscv64-none-linux-gnu -target-feature +v -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-NONE
+
+! CHECK-LABEL: @func_() #0
+! CHECK: attributes #0 = {{{.*}} vscale_range([[#VBITS]],[[#VBITS]]) {{.*}}}
+! CHECK-NOMAX: attributes #0 = {{{.*}} vscale_range([[#VBITS]],0) {{.*}}}
+! CHECK-UNBOUNDED: attributes #0 = {{{.*}} vscale_range(1,0) {{.*}}}
+! CHECK-NONE-NOT: vscale_range
+subroutine func
+end subroutine func
-- 
GitLab


From e4f3ec2579a0f42e9258009c1e94985f99d9a02f Mon Sep 17 00:00:00 2001
From: Guillaume Chatelet <gchatelet@google.com>
Date: Mon, 11 Dec 2023 17:40:47 +0100
Subject: [PATCH 139/349] [libc][NFC] Simplify FloatProperties implementation
 (#74821)

This is a follow up on #74481 that migrates code from all
specializations into `FPCommonProperties` (except for
`EXPLICIT_BIT_MASK` in the `X86_Binary80` specialization)
---
 libc/src/__support/FPUtil/FloatProperties.h | 168 ++++++++++----------
 1 file changed, 85 insertions(+), 83 deletions(-)

diff --git a/libc/src/__support/FPUtil/FloatProperties.h b/libc/src/__support/FPUtil/FloatProperties.h
index 4288cd719a1d..ba54e9d1781c 100644
--- a/libc/src/__support/FPUtil/FloatProperties.h
+++ b/libc/src/__support/FPUtil/FloatProperties.h
@@ -80,27 +80,105 @@ template <> struct FPBaseProperties<FPType::X86_Binary80> {
       FPEncoding::X86_ExtendedPrecision;
 };
 
+// TODO: Move this utility elsewhere.
+template <typename T, size_t count> static constexpr T mask_trailing_ones() {
+  static_assert(cpp::is_unsigned_v<T>);
+  constexpr unsigned t_bits = CHAR_BIT * sizeof(T);
+  static_assert(count <= t_bits && "Invalid bit index");
+  return count == 0 ? 0 : (T(-1) >> (t_bits - count));
+}
+
 // Derives more properties from 'FPBaseProperties' above.
 // This class serves as a halfway point between 'FPBaseProperties' and
 // 'FPProperties' below.
 template <FPType fp_type>
 struct FPCommonProperties : private FPBaseProperties<fp_type> {
+private:
   using UP = FPBaseProperties<fp_type>;
-  using BitsType = typename UP::UIntType;
+  using UP::EXP_BITS;
+  using UP::SIG_BITS;
+  using UP::TOTAL_BITS;
+  using UIntType = typename UP::UIntType;
+
+  LIBC_INLINE_VAR static constexpr int STORAGE_BITS =
+      sizeof(UIntType) * CHAR_BIT;
+  static_assert(STORAGE_BITS >= TOTAL_BITS);
 
-  LIBC_INLINE_VAR static constexpr uint32_t BIT_WIDTH = UP::TOTAL_BITS;
-  LIBC_INLINE_VAR static constexpr uint32_t MANTISSA_WIDTH = UP::SIG_BITS;
-  LIBC_INLINE_VAR static constexpr uint32_t EXPONENT_WIDTH = UP::EXP_BITS;
+  // The number of bits to represent sign.
+  // For documentation purpose, always 1.
+  LIBC_INLINE_VAR static constexpr int SIGN_BITS = 1;
+  static_assert(SIGN_BITS + EXP_BITS + SIG_BITS == TOTAL_BITS);
 
   // The exponent bias. Always positive.
+  LIBC_INLINE_VAR static constexpr int32_t EXP_BIAS =
+      (1U << (EXP_BITS - 1U)) - 1U;
+  static_assert(EXP_BIAS > 0);
+
+  // Shifts
+  LIBC_INLINE_VAR static constexpr int SIG_MASK_SHIFT = 0;
+  LIBC_INLINE_VAR static constexpr int EXP_MASK_SHIFT = SIG_BITS;
+  LIBC_INLINE_VAR static constexpr int SIGN_MASK_SHIFT = SIG_BITS + EXP_BITS;
+
+  // Masks
+  LIBC_INLINE_VAR static constexpr UIntType SIG_MASK =
+      mask_trailing_ones<UIntType, SIG_BITS>() << SIG_MASK_SHIFT;
+  LIBC_INLINE_VAR static constexpr UIntType EXP_MASK =
+      mask_trailing_ones<UIntType, EXP_BITS>() << EXP_MASK_SHIFT;
+  // Trailing underscore on SIGN_MASK_ is temporary - it will be removed
+  // once we can replace the public part below with the private one.
+  LIBC_INLINE_VAR static constexpr UIntType SIGN_MASK_ =
+      mask_trailing_ones<UIntType, SIGN_BITS>() << SIGN_MASK_SHIFT;
+  LIBC_INLINE_VAR static constexpr UIntType FP_MASK =
+      mask_trailing_ones<UIntType, TOTAL_BITS>();
+  static_assert((SIG_MASK & EXP_MASK & SIGN_MASK_) == 0, "masks disjoint");
+  static_assert((SIG_MASK | EXP_MASK | SIGN_MASK_) == FP_MASK, "masks covers");
+
+  LIBC_INLINE static constexpr UIntType bit_at(int position) {
+    return UIntType(1) << position;
+  }
+
+  LIBC_INLINE_VAR static constexpr UIntType QNAN_MASK =
+      UP::ENCODING == FPEncoding::X86_ExtendedPrecision
+          ? bit_at(SIG_BITS - 1) | bit_at(SIG_BITS - 2) // 0b1100...
+          : bit_at(SIG_BITS - 1);                       // 0b1000...
+
+  LIBC_INLINE_VAR static constexpr UIntType SNAN_MASK =
+      UP::ENCODING == FPEncoding::X86_ExtendedPrecision
+          ? bit_at(SIG_BITS - 1) | bit_at(SIG_BITS - 3) // 0b1010...
+          : bit_at(SIG_BITS - 2);                       // 0b0100...
+
+  // The number of bits after the decimal dot when the number if in normal form.
+  LIBC_INLINE_VAR static constexpr int FRACTION_BITS =
+      UP::ENCODING == FPEncoding::X86_ExtendedPrecision ? SIG_BITS - 1
+                                                        : SIG_BITS;
+
+public:
+  // Public facing API to keep the change local to this file.
+  using BitsType = UIntType;
+
+  LIBC_INLINE_VAR static constexpr uint32_t BIT_WIDTH = TOTAL_BITS;
+  LIBC_INLINE_VAR static constexpr uint32_t MANTISSA_WIDTH = FRACTION_BITS;
+  LIBC_INLINE_VAR static constexpr uint32_t MANTISSA_PRECISION =
+      MANTISSA_WIDTH + 1;
+  LIBC_INLINE_VAR static constexpr BitsType MANTISSA_MASK =
+      mask_trailing_ones<UIntType, MANTISSA_WIDTH>();
+  LIBC_INLINE_VAR static constexpr uint32_t EXPONENT_WIDTH = EXP_BITS;
   LIBC_INLINE_VAR static constexpr uint32_t EXPONENT_BIAS =
-      (1U << (UP::EXP_BITS - 1U)) - 1U;
-  static_assert(EXPONENT_BIAS > 0);
+      static_cast<uint32_t>(EXP_BIAS);
+  LIBC_INLINE_VAR static constexpr BitsType SIGN_MASK = SIGN_MASK_;
+  LIBC_INLINE_VAR static constexpr BitsType EXPONENT_MASK = EXP_MASK;
+  LIBC_INLINE_VAR static constexpr BitsType EXP_MANT_MASK = EXP_MASK | SIG_MASK;
+
+  // If a number x is a NAN, then it is a quiet NAN if:
+  //   QuietNaNMask & bits(x) != 0
+  // Else, it is a signalling NAN.
+  static constexpr BitsType QUIET_NAN_MASK = QNAN_MASK;
 };
 
 } // namespace internal
 
-template <FPType> struct FPProperties {};
+template <FPType fp_type>
+struct FPProperties : public internal::FPCommonProperties<fp_type> {};
 
 // ----------------
 // Work In Progress
@@ -110,90 +188,14 @@ template <FPType> struct FPProperties {};
 // empty, 'FPProperties' declaration can be fully replace with
 // 'FPCommonProperties' implementation.
 
-template <>
-struct FPProperties<FPType::IEEE754_Binary32>
-    : public internal::FPCommonProperties<FPType::IEEE754_Binary32> {
-  // The mantissa precision includes the implicit bit.
-  static constexpr uint32_t MANTISSA_PRECISION = MANTISSA_WIDTH + 1;
-  static constexpr BitsType MANTISSA_MASK = (BitsType(1) << MANTISSA_WIDTH) - 1;
-  static constexpr BitsType SIGN_MASK = BitsType(1)
-                                        << (EXPONENT_WIDTH + MANTISSA_WIDTH);
-  static constexpr BitsType EXPONENT_MASK = ~(SIGN_MASK | MANTISSA_MASK);
-  static constexpr BitsType EXP_MANT_MASK = MANTISSA_MASK + EXPONENT_MASK;
-  static_assert(EXP_MANT_MASK == ~SIGN_MASK,
-                "Exponent and mantissa masks are not as expected.");
-
-  // If a number x is a NAN, then it is a quiet NAN if:
-  //   QuietNaNMask & bits(x) != 0
-  // Else, it is a signalling NAN.
-  static constexpr BitsType QUIET_NAN_MASK = 0x00400000U;
-};
-
-template <>
-struct FPProperties<FPType::IEEE754_Binary64>
-    : public internal::FPCommonProperties<FPType::IEEE754_Binary64> {
-  static constexpr uint32_t MANTISSA_PRECISION = MANTISSA_WIDTH + 1;
-  static constexpr BitsType MANTISSA_MASK = (BitsType(1) << MANTISSA_WIDTH) - 1;
-  static constexpr BitsType SIGN_MASK = BitsType(1)
-                                        << (EXPONENT_WIDTH + MANTISSA_WIDTH);
-  static constexpr BitsType EXPONENT_MASK = ~(SIGN_MASK | MANTISSA_MASK);
-  static constexpr BitsType EXP_MANT_MASK = MANTISSA_MASK + EXPONENT_MASK;
-  static_assert(EXP_MANT_MASK == ~SIGN_MASK,
-                "Exponent and mantissa masks are not as expected.");
-
-  // If a number x is a NAN, then it is a quiet NAN if:
-  //   QuietNaNMask & bits(x) != 0
-  // Else, it is a signalling NAN.
-  static constexpr BitsType QUIET_NAN_MASK = 0x0008000000000000ULL;
-};
-
 // Properties for numbers represented in 80 bits long double on non-Windows x86
 // platforms.
 template <>
 struct FPProperties<FPType::X86_Binary80>
     : public internal::FPCommonProperties<FPType::X86_Binary80> {
-  static constexpr BitsType FULL_WIDTH_MASK = ((BitsType(1) << BIT_WIDTH) - 1);
-  static constexpr uint32_t MANTISSA_WIDTH = 63;
-  static constexpr uint32_t MANTISSA_PRECISION = MANTISSA_WIDTH + 1;
-  static constexpr BitsType MANTISSA_MASK = (BitsType(1) << MANTISSA_WIDTH) - 1;
   // The x86 80 bit float represents the leading digit of the mantissa
   // explicitly. This is the mask for that bit.
   static constexpr BitsType EXPLICIT_BIT_MASK = (BitsType(1) << MANTISSA_WIDTH);
-  static constexpr BitsType SIGN_MASK =
-      BitsType(1) << (EXPONENT_WIDTH + MANTISSA_WIDTH + 1);
-  static constexpr BitsType EXPONENT_MASK =
-      ((BitsType(1) << EXPONENT_WIDTH) - 1) << (MANTISSA_WIDTH + 1);
-  static constexpr BitsType EXP_MANT_MASK =
-      MANTISSA_MASK | EXPLICIT_BIT_MASK | EXPONENT_MASK;
-  static_assert(EXP_MANT_MASK == (~SIGN_MASK & FULL_WIDTH_MASK),
-                "Exponent and mantissa masks are not as expected.");
-
-  // If a number x is a NAN, then it is a quiet NAN if:
-  //   QuietNaNMask & bits(x) != 0
-  // Else, it is a signalling NAN.
-  static constexpr BitsType QUIET_NAN_MASK = BitsType(1)
-                                             << (MANTISSA_WIDTH - 1);
-};
-
-// Properties for numbers represented in 128 bits long double on non x86
-// platform.
-template <>
-struct FPProperties<FPType::IEEE754_Binary128>
-    : public internal::FPCommonProperties<FPType::IEEE754_Binary128> {
-  static constexpr uint32_t MANTISSA_PRECISION = MANTISSA_WIDTH + 1;
-  static constexpr BitsType MANTISSA_MASK = (BitsType(1) << MANTISSA_WIDTH) - 1;
-  static constexpr BitsType SIGN_MASK = BitsType(1)
-                                        << (EXPONENT_WIDTH + MANTISSA_WIDTH);
-  static constexpr BitsType EXPONENT_MASK = ~(SIGN_MASK | MANTISSA_MASK);
-  static constexpr BitsType EXP_MANT_MASK = MANTISSA_MASK | EXPONENT_MASK;
-  static_assert(EXP_MANT_MASK == ~SIGN_MASK,
-                "Exponent and mantissa masks are not as expected.");
-
-  // If a number x is a NAN, then it is a quiet NAN if:
-  //   QuietNaNMask & bits(x) != 0
-  // Else, it is a signalling NAN.
-  static constexpr BitsType QUIET_NAN_MASK = BitsType(1)
-                                             << (MANTISSA_WIDTH - 1);
 };
 
 //-----------------------------------------------------------------------------
-- 
GitLab


From 99c0a3ea98724798361c8ef72d07d9646dcb64ee Mon Sep 17 00:00:00 2001
From: Philip Reames <preames@rivosinc.com>
Date: Mon, 11 Dec 2023 08:55:21 -0800
Subject: [PATCH 140/349] [RISCV] Enable target attribute when invoked through
 clang driver (#74889)

d80e46d added support for the target function attribute. However, it
turns out that commit has a nasty bug/oversight. As the tests in that
revision show, everything works if clang -cc1 is directly invoked. I was
suprised to learn this morning that compiling with clang (i.e. the
typical user workflow) did not work.

The bug is that if a set of explicit negative extensions is passed to
cc1 at the command line (as the clang driver always does), we were
copying these negative extensions to the end of the rewritten extension
list. When this was later parsed, this had the effect of turning back
off any extension that the target attribute had enabled.

This patch updates the logic to only propagate the features from the
input which don't appear in the rewritten form in either positive or
negative form.

Note that this code structure is still highly suspect. In particular I'm
fairly sure that mixing extension versions with this code will result in
odd results. However, I figure its better to have something which mostly
works than something which doesn't work at all.
---
 clang/lib/Basic/Targets/RISCV.cpp             | 15 +++++++++----
 .../CodeGen/RISCV/riscv-func-attr-target.c    | 21 ++++++++++---------
 2 files changed, 22 insertions(+), 14 deletions(-)

diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
index b1733b878e88..45d23022b530 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -304,11 +304,18 @@ bool RISCVTargetInfo::initFeatureMap(
 
   // RISCVISAInfo makes implications for ISA features
   std::vector<std::string> ImpliedFeatures = (*ParseResult)->toFeatureVector();
-  // Add non-ISA features like `relax` and `save-restore` back
-  for (const std::string &Feature : NewFeaturesVec)
-    if (!llvm::is_contained(ImpliedFeatures, Feature))
-      ImpliedFeatures.push_back(Feature);
 
+  // parseFeatures normalizes the feature set by dropping any explicit
+  // negatives, and non-extension features.  We need to preserve the later
+  // for correctness and want to preserve the former for consistency.
+  for (auto &Feature : NewFeaturesVec) {
+     StringRef ExtName = Feature;
+     assert(ExtName.size() > 1 && (ExtName[0] == '+' || ExtName[0] == '-'));
+     ExtName = ExtName.drop_front(1); // Drop '+' or '-'
+     if (!llvm::is_contained(ImpliedFeatures, ("+" + ExtName).str()) &&
+         !llvm::is_contained(ImpliedFeatures, ("-" + ExtName).str()))
+       ImpliedFeatures.push_back(Feature);
+  }
   return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures);
 }
 
diff --git a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
index 74bc5f2ac704..506acaba6874 100644
--- a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
+++ b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -1,6 +1,7 @@
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +zifencei -target-feature +m \
-// RUN:  -target-feature +a -target-feature +save-restore \
+// RUN:  -target-feature +a -target-feature +save-restore -target-feature -zbb \
+// RUN:  -target-feature -relax -target-feature -zfa \
 // RUN:  -emit-llvm %s -o - | FileCheck %s
 
 // CHECK-LABEL: define dso_local void @testDefault
@@ -35,12 +36,12 @@ testAttrFullArchAndAttrCpu() {}
 __attribute__((target("cpu=sifive-u54"))) void testAttrCpuOnly() {}
 
 //.
-// CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zifencei" }
-// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" "tune-cpu"="generic-rv64" }
-// CHECK: attributes #2 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei" }
-// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+experimental-zicond,+f,+m,+save-restore,+v,+zbb,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
-// CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei" }
-// CHECK: attributes #5 = { {{.*}}"target-features"="+64bit,+m,+save-restore" }
-// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei" }
-// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+m,+save-restore" }
-// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei" }
+// CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zifencei,-relax,-zbb,-zfa" }
+// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa" "tune-cpu"="generic-rv64" }
+// CHECK: attributes #2 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,-relax,-zfa" }
+// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+experimental-zicond,+f,+m,+save-restore,+v,+zbb,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa" }
+// CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,-relax,-zfa" }
+// CHECK: attributes #5 = { {{.*}}"target-features"="+64bit,+m,+save-restore,-relax,-zbb,-zfa" }
+// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,-relax,-zfa" }
+// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+m,+save-restore,-relax,-zbb,-zfa" }
+// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei,-relax,-zbb,-zfa" }
-- 
GitLab


From 05b68d596047cf50f721eea1c69275f8906ba561 Mon Sep 17 00:00:00 2001
From: Dinar Temirbulatov <Dinar.Temirbulatov@arm.com>
Date: Mon, 11 Dec 2023 16:58:22 +0000
Subject: [PATCH 141/349] [AArch64][SME2] Add PEXT, PSEL builtins for SME2
 (#72827)

This change enables PEXT, PSEL builtins for SME2 target.
---
 clang/include/clang/Basic/arm_sve.td          |  30 +--
 .../acle_sve2p1_pext.c                        | 205 +++++++++++++++++-
 .../acle_sve2p1_psel.c                        |  21 +-
 3 files changed, 225 insertions(+), 31 deletions(-)

diff --git a/clang/include/clang/Basic/arm_sve.td b/clang/include/clang/Basic/arm_sve.td
index 85656c00c5b3..42ad7da737b4 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1935,16 +1935,25 @@ def SVBGRP   : SInst<"svbgrp[_{d}]",   "ddd", "UcUsUiUl", MergeNone, "aarch64_sv
 def SVBGRP_N : SInst<"svbgrp[_n_{d}]", "dda", "UcUsUiUl", MergeNone, "aarch64_sve_bgrp_x">;
 }
 
-let TargetGuard = "sve2p1" in {
-def SVFCLAMP   : SInst<"svclamp[_{d}]", "dddd", "hfd", MergeNone, "aarch64_sve_fclamp", [], []>;
+let TargetGuard = "sve2p1|sme" in {
+def SVPSEL_B : SInst<"svpsel_lane_b8",  "PPPm", "Pc", MergeNone, "", [IsStreamingCompatible], []>;
+def SVPSEL_H : SInst<"svpsel_lane_b16", "PPPm", "Ps", MergeNone, "", [IsStreamingCompatible], []>;
+def SVPSEL_S : SInst<"svpsel_lane_b32", "PPPm", "Pi", MergeNone, "", [IsStreamingCompatible], []>;
+def SVPSEL_D : SInst<"svpsel_lane_b64", "PPPm", "Pl", MergeNone, "", [IsStreamingCompatible], []>;
+def SVPSEL_COUNT_ALIAS_B : SInst<"svpsel_lane_c8",  "}}Pm", "Pc", MergeNone, "", [IsStreamingCompatible], []>;
+def SVPSEL_COUNT_ALIAS_H : SInst<"svpsel_lane_c16", "}}Pm", "Ps", MergeNone, "", [IsStreamingCompatible], []>;
+def SVPSEL_COUNT_ALIAS_S : SInst<"svpsel_lane_c32", "}}Pm", "Pi", MergeNone, "", [IsStreamingCompatible], []>;
+def SVPSEL_COUNT_ALIAS_D : SInst<"svpsel_lane_c64", "}}Pm", "Pl", MergeNone, "", [IsStreamingCompatible], []>;
+}
 
-def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone, "aarch64_sve_pext", [], [ImmCheck<1, ImmCheck0_3>]>;
-def SVPEXT_X2     : SInst<"svpext_lane_{d}_x2", "2.P}i", "QcQsQiQl", MergeNone, "aarch64_sve_pext_x2", [], [ImmCheck<1, ImmCheck0_1>]>;
+let TargetGuard = "sve2p1|sme2" in {
+//FIXME: Replace IsStreamingCompatible with IsStreamingOrHasSVE2p1 when available
+def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone, "aarch64_sve_pext", [IsStreamingCompatible], [ImmCheck<1, ImmCheck0_3>]>;
+def SVPEXT_X2     : SInst<"svpext_lane_{d}_x2", "2.P}i", "QcQsQiQl", MergeNone, "aarch64_sve_pext_x2", [IsStreamingCompatible], [ImmCheck<1, ImmCheck0_1>]>;
+}
 
-def SVPSEL_COUNT_ALIAS_B : SInst<"svpsel_lane_c8",  "}}Pm", "Pc", MergeNone, "", [], []>;
-def SVPSEL_COUNT_ALIAS_H : SInst<"svpsel_lane_c16", "}}Pm", "Ps", MergeNone, "", [], []>;
-def SVPSEL_COUNT_ALIAS_S : SInst<"svpsel_lane_c32", "}}Pm", "Pi", MergeNone, "", [], []>;
-def SVPSEL_COUNT_ALIAS_D : SInst<"svpsel_lane_c64", "}}Pm", "Pl", MergeNone, "", [], []>;
+let TargetGuard = "sve2p1" in {
+def SVFCLAMP   : SInst<"svclamp[_{d}]", "dddd", "hfd", MergeNone, "aarch64_sve_fclamp", [], []>;
 
 def SVWHILEGE_COUNT  : SInst<"svwhilege_{d}",  "}lli", "QcQsQiQl", MergeNone, "aarch64_sve_whilege_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
 def SVWHILEGT_COUNT  : SInst<"svwhilegt_{d}",  "}lli", "QcQsQiQl", MergeNone, "aarch64_sve_whilegt_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
@@ -2045,11 +2054,6 @@ let TargetGuard = "sve2p1" in {
 def SVSCLAMP : SInst<"svclamp[_{d}]", "dddd", "csil",     MergeNone, "aarch64_sve_sclamp", [], []>;
 def SVUCLAMP : SInst<"svclamp[_{d}]", "dddd", "UcUsUiUl", MergeNone, "aarch64_sve_uclamp", [], []>;
 
-def SVPSEL_B : SInst<"svpsel_lane_b8",  "PPPm", "Pc", MergeNone, "", [], []>;
-def SVPSEL_H : SInst<"svpsel_lane_b16", "PPPm", "Ps", MergeNone, "", [], []>;
-def SVPSEL_S : SInst<"svpsel_lane_b32", "PPPm", "Pi", MergeNone, "", [], []>;
-def SVPSEL_D : SInst<"svpsel_lane_b64", "PPPm", "Pl", MergeNone, "", [], []>;
-
 def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i", "QcQsQiQl", MergeNone, "aarch64_sve_cntp_{d}", [IsOverloadNone], [ImmCheck<1, ImmCheck2_4_Mul2>]>;
 
 defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUl", "aarch64_sve_revd">;
diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pext.c b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pext.c
index fe15d5a9db81..a3206029019c 100644
--- a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pext.c
+++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pext.c
@@ -1,10 +1,17 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -DTEST_SME2 -target-feature +sve -target-feature +sme2 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
 
 #include <arm_sve.h>
 
+#ifndef TEST_SME2
+#define ATTR
+#else
+#define ATTR __arm_streaming
+#endif
+
 // CHECK-LABEL: @test_svpext_lane_c8_0(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.pext.nxv16i1(target("aarch64.svcount") [[C:%.*]], i32 0)
@@ -15,7 +22,7 @@
 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.pext.nxv16i1(target("aarch64.svcount") [[C:%.*]], i32 0)
 // CPP-CHECK-NEXT:    ret <vscale x 16 x i1> [[TMP0]]
 //
-svbool_t test_svpext_lane_c8_0(svcount_t c) {
+svbool_t test_svpext_lane_c8_0(svcount_t c) ATTR {
   return svpext_lane_c8(c, 0);
 }
 
@@ -29,7 +36,7 @@ svbool_t test_svpext_lane_c8_0(svcount_t c) {
 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.pext.nxv16i1(target("aarch64.svcount") [[C:%.*]], i32 3)
 // CPP-CHECK-NEXT:    ret <vscale x 16 x i1> [[TMP0]]
 //
-svbool_t test_svpext_lane_c8_3(svcount_t c) {
+svbool_t test_svpext_lane_c8_3(svcount_t c) ATTR {
   return svpext_lane_c8(c, 3);
 }
 
@@ -45,7 +52,7 @@ svbool_t test_svpext_lane_c8_3(svcount_t c) {
 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP0]])
 // CPP-CHECK-NEXT:    ret <vscale x 16 x i1> [[TMP1]]
 //
-svbool_t test_svpext_lane_c16_0(svcount_t c) {
+svbool_t test_svpext_lane_c16_0(svcount_t c) ATTR {
   return svpext_lane_c16(c, 0);
 }
 
@@ -61,7 +68,7 @@ svbool_t test_svpext_lane_c16_0(svcount_t c) {
 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP0]])
 // CPP-CHECK-NEXT:    ret <vscale x 16 x i1> [[TMP1]]
 //
-svbool_t test_svpext_lane_c16_3(svcount_t c) {
+svbool_t test_svpext_lane_c16_3(svcount_t c) ATTR {
   return svpext_lane_c16(c, 3);
 }
 
@@ -77,7 +84,7 @@ svbool_t test_svpext_lane_c16_3(svcount_t c) {
 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP0]])
 // CPP-CHECK-NEXT:    ret <vscale x 16 x i1> [[TMP1]]
 //
-svbool_t test_svpext_lane_c32_0(svcount_t c) {
+svbool_t test_svpext_lane_c32_0(svcount_t c) ATTR {
   return svpext_lane_c32(c, 0);
 }
 
@@ -93,7 +100,7 @@ svbool_t test_svpext_lane_c32_0(svcount_t c) {
 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP0]])
 // CPP-CHECK-NEXT:    ret <vscale x 16 x i1> [[TMP1]]
 //
-svbool_t test_svpext_lane_c32_3(svcount_t c) {
+svbool_t test_svpext_lane_c32_3(svcount_t c) ATTR {
   return svpext_lane_c32(c, 3);
 }
 
@@ -109,7 +116,7 @@ svbool_t test_svpext_lane_c32_3(svcount_t c) {
 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP0]])
 // CPP-CHECK-NEXT:    ret <vscale x 16 x i1> [[TMP1]]
 //
-svbool_t test_svpext_lane_c64_0(svcount_t c) {
+svbool_t test_svpext_lane_c64_0(svcount_t c) ATTR {
   return svpext_lane_c64(c, 0);
 }
 
@@ -125,7 +132,7 @@ svbool_t test_svpext_lane_c64_0(svcount_t c) {
 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP0]])
 // CPP-CHECK-NEXT:    ret <vscale x 16 x i1> [[TMP1]]
 //
-svbool_t test_svpext_lane_c64_3(svcount_t c) {
+svbool_t test_svpext_lane_c64_3(svcount_t c) ATTR {
   return svpext_lane_c64(c, 3);
 }
 
@@ -147,6 +154,184 @@ svbool_t test_svpext_lane_c64_3(svcount_t c) {
 // CPP-CHECK-NEXT:    [[TMP4:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP2]], <vscale x 16 x i1> [[TMP3]], i64 16)
 // CPP-CHECK-NEXT:    ret <vscale x 32 x i1> [[TMP4]]
 //
-svboolx2_t test_svpext_lane_c8_x2_0(svcount_t c) {
+svboolx2_t test_svpext_lane_c8_x2_0(svcount_t c) ATTR {
   return svpext_lane_c8_x2(c, 0);
 }
+
+// CHECK-LABEL: @test_svpext_lane_c8_x2_1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 16 x i1>, <vscale x 16 x i1> } @llvm.aarch64.sve.pext.x2.nxv16i1(target("aarch64.svcount") [[C:%.*]], i32 1)
+// CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } [[TMP0]], 0
+// CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x i1> [[TMP1]], i64 0)
+// CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } [[TMP0]], 1
+// CHECK-NEXT:    [[TMP4:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP2]], <vscale x 16 x i1> [[TMP3]], i64 16)
+// CHECK-NEXT:    ret <vscale x 32 x i1> [[TMP4]]
+//
+// CPP-CHECK-LABEL: @_Z24test_svpext_lane_c8_x2_1u11__SVCount_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 16 x i1>, <vscale x 16 x i1> } @llvm.aarch64.sve.pext.x2.nxv16i1(target("aarch64.svcount") [[C:%.*]], i32 1)
+// CPP-CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } [[TMP0]], 0
+// CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x i1> [[TMP1]], i64 0)
+// CPP-CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } [[TMP0]], 1
+// CPP-CHECK-NEXT:    [[TMP4:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP2]], <vscale x 16 x i1> [[TMP3]], i64 16)
+// CPP-CHECK-NEXT:    ret <vscale x 32 x i1> [[TMP4]]
+//
+svboolx2_t test_svpext_lane_c8_x2_1(svcount_t c) ATTR {
+  return svpext_lane_c8_x2(c, 1);
+}
+
+// CHECK-LABEL: @test_svpext_lane_c16_x2_0(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 8 x i1>, <vscale x 8 x i1> } @llvm.aarch64.sve.pext.x2.nxv8i1(target("aarch64.svcount") [[C:%.*]], i32 0)
+// CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } [[TMP0]], 0
+// CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x i1> [[TMP2]], i64 0)
+// CHECK-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } [[TMP0]], 1
+// CHECK-NEXT:    [[TMP5:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP4]])
+// CHECK-NEXT:    [[TMP6:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x i1> [[TMP5]], i64 16)
+// CHECK-NEXT:    ret <vscale x 32 x i1> [[TMP6]]
+//
+// CPP-CHECK-LABEL: @_Z25test_svpext_lane_c16_x2_0u11__SVCount_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 8 x i1>, <vscale x 8 x i1> } @llvm.aarch64.sve.pext.x2.nxv8i1(target("aarch64.svcount") [[C:%.*]], i32 0)
+// CPP-CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } [[TMP0]], 0
+// CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
+// CPP-CHECK-NEXT:    [[TMP3:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x i1> [[TMP2]], i64 0)
+// CPP-CHECK-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } [[TMP0]], 1
+// CPP-CHECK-NEXT:    [[TMP5:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP4]])
+// CPP-CHECK-NEXT:    [[TMP6:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x i1> [[TMP5]], i64 16)
+// CPP-CHECK-NEXT:    ret <vscale x 32 x i1> [[TMP6]]
+//
+svboolx2_t test_svpext_lane_c16_x2_0(svcount_t c) ATTR {
+  return svpext_lane_c16_x2(c, 0);
+}
+
+// CHECK-LABEL: @test_svpext_lane_c16_x2_1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 8 x i1>, <vscale x 8 x i1> } @llvm.aarch64.sve.pext.x2.nxv8i1(target("aarch64.svcount") [[C:%.*]], i32 1)
+// CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } [[TMP0]], 0
+// CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x i1> [[TMP2]], i64 0)
+// CHECK-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } [[TMP0]], 1
+// CHECK-NEXT:    [[TMP5:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP4]])
+// CHECK-NEXT:    [[TMP6:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x i1> [[TMP5]], i64 16)
+// CHECK-NEXT:    ret <vscale x 32 x i1> [[TMP6]]
+//
+// CPP-CHECK-LABEL: @_Z25test_svpext_lane_c16_x2_1u11__SVCount_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 8 x i1>, <vscale x 8 x i1> } @llvm.aarch64.sve.pext.x2.nxv8i1(target("aarch64.svcount") [[C:%.*]], i32 1)
+// CPP-CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } [[TMP0]], 0
+// CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
+// CPP-CHECK-NEXT:    [[TMP3:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x i1> [[TMP2]], i64 0)
+// CPP-CHECK-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } [[TMP0]], 1
+// CPP-CHECK-NEXT:    [[TMP5:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP4]])
+// CPP-CHECK-NEXT:    [[TMP6:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x i1> [[TMP5]], i64 16)
+// CPP-CHECK-NEXT:    ret <vscale x 32 x i1> [[TMP6]]
+//
+svboolx2_t test_svpext_lane_c16_x2_1(svcount_t c) ATTR {
+  return svpext_lane_c16_x2(c, 1);
+}
+
+// CHECK-LABEL: @test_svpext_lane_c32_x2_0(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.pext.x2.nxv4i1(target("aarch64.svcount") [[C:%.*]], i32 0)
+// CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } [[TMP0]], 0
+// CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x i1> [[TMP2]], i64 0)
+// CHECK-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } [[TMP0]], 1
+// CHECK-NEXT:    [[TMP5:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP4]])
+// CHECK-NEXT:    [[TMP6:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x i1> [[TMP5]], i64 16)
+// CHECK-NEXT:    ret <vscale x 32 x i1> [[TMP6]]
+//
+// CPP-CHECK-LABEL: @_Z25test_svpext_lane_c32_x2_0u11__SVCount_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.pext.x2.nxv4i1(target("aarch64.svcount") [[C:%.*]], i32 0)
+// CPP-CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } [[TMP0]], 0
+// CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
+// CPP-CHECK-NEXT:    [[TMP3:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x i1> [[TMP2]], i64 0)
+// CPP-CHECK-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } [[TMP0]], 1
+// CPP-CHECK-NEXT:    [[TMP5:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP4]])
+// CPP-CHECK-NEXT:    [[TMP6:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x i1> [[TMP5]], i64 16)
+// CPP-CHECK-NEXT:    ret <vscale x 32 x i1> [[TMP6]]
+//
+svboolx2_t test_svpext_lane_c32_x2_0(svcount_t c) ATTR {
+  return svpext_lane_c32_x2(c, 0);
+}
+
+// CHECK-LABEL: @test_svpext_lane_c32_x2_1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.pext.x2.nxv4i1(target("aarch64.svcount") [[C:%.*]], i32 1)
+// CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } [[TMP0]], 0
+// CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x i1> [[TMP2]], i64 0)
+// CHECK-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } [[TMP0]], 1
+// CHECK-NEXT:    [[TMP5:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP4]])
+// CHECK-NEXT:    [[TMP6:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x i1> [[TMP5]], i64 16)
+// CHECK-NEXT:    ret <vscale x 32 x i1> [[TMP6]]
+//
+// CPP-CHECK-LABEL: @_Z25test_svpext_lane_c32_x2_1u11__SVCount_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.pext.x2.nxv4i1(target("aarch64.svcount") [[C:%.*]], i32 1)
+// CPP-CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } [[TMP0]], 0
+// CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
+// CPP-CHECK-NEXT:    [[TMP3:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x i1> [[TMP2]], i64 0)
+// CPP-CHECK-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } [[TMP0]], 1
+// CPP-CHECK-NEXT:    [[TMP5:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP4]])
+// CPP-CHECK-NEXT:    [[TMP6:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x i1> [[TMP5]], i64 16)
+// CPP-CHECK-NEXT:    ret <vscale x 32 x i1> [[TMP6]]
+//
+svboolx2_t test_svpext_lane_c32_x2_1(svcount_t c) ATTR {
+  return svpext_lane_c32_x2(c, 1);
+}
+
+// CHECK-LABEL: @test_svpext_lane_c64_x2_0(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 2 x i1>, <vscale x 2 x i1> } @llvm.aarch64.sve.pext.x2.nxv2i1(target("aarch64.svcount") [[C:%.*]], i32 0)
+// CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i1>, <vscale x 2 x i1> } [[TMP0]], 0
+// CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x i1> [[TMP2]], i64 0)
+// CHECK-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 2 x i1>, <vscale x 2 x i1> } [[TMP0]], 1
+// CHECK-NEXT:    [[TMP5:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP4]])
+// CHECK-NEXT:    [[TMP6:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x i1> [[TMP5]], i64 16)
+// CHECK-NEXT:    ret <vscale x 32 x i1> [[TMP6]]
+//
+// CPP-CHECK-LABEL: @_Z25test_svpext_lane_c64_x2_0u11__SVCount_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 2 x i1>, <vscale x 2 x i1> } @llvm.aarch64.sve.pext.x2.nxv2i1(target("aarch64.svcount") [[C:%.*]], i32 0)
+// CPP-CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i1>, <vscale x 2 x i1> } [[TMP0]], 0
+// CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP1]])
+// CPP-CHECK-NEXT:    [[TMP3:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x i1> [[TMP2]], i64 0)
+// CPP-CHECK-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 2 x i1>, <vscale x 2 x i1> } [[TMP0]], 1
+// CPP-CHECK-NEXT:    [[TMP5:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP4]])
+// CPP-CHECK-NEXT:    [[TMP6:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x i1> [[TMP5]], i64 16)
+// CPP-CHECK-NEXT:    ret <vscale x 32 x i1> [[TMP6]]
+//
+svboolx2_t test_svpext_lane_c64_x2_0(svcount_t c) ATTR {
+  return svpext_lane_c64_x2(c, 0);
+}
+
+// CHECK-LABEL: @test_svpext_lane_c64_x2_1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 2 x i1>, <vscale x 2 x i1> } @llvm.aarch64.sve.pext.x2.nxv2i1(target("aarch64.svcount") [[C:%.*]], i32 1)
+// CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i1>, <vscale x 2 x i1> } [[TMP0]], 0
+// CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x i1> [[TMP2]], i64 0)
+// CHECK-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 2 x i1>, <vscale x 2 x i1> } [[TMP0]], 1
+// CHECK-NEXT:    [[TMP5:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP4]])
+// CHECK-NEXT:    [[TMP6:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x i1> [[TMP5]], i64 16)
+// CHECK-NEXT:    ret <vscale x 32 x i1> [[TMP6]]
+//
+// CPP-CHECK-LABEL: @_Z25test_svpext_lane_c64_x2_1u11__SVCount_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 2 x i1>, <vscale x 2 x i1> } @llvm.aarch64.sve.pext.x2.nxv2i1(target("aarch64.svcount") [[C:%.*]], i32 1)
+// CPP-CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i1>, <vscale x 2 x i1> } [[TMP0]], 0
+// CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP1]])
+// CPP-CHECK-NEXT:    [[TMP3:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x i1> [[TMP2]], i64 0)
+// CPP-CHECK-NEXT:    [[TMP4:%.*]] = extractvalue { <vscale x 2 x i1>, <vscale x 2 x i1> } [[TMP0]], 1
+// CPP-CHECK-NEXT:    [[TMP5:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP4]])
+// CPP-CHECK-NEXT:    [[TMP6:%.*]] = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> [[TMP3]], <vscale x 16 x i1> [[TMP5]], i64 16)
+// CPP-CHECK-NEXT:    ret <vscale x 32 x i1> [[TMP6]]
+//
+svboolx2_t test_svpext_lane_c64_x2_1(svcount_t c) ATTR {
+  return svpext_lane_c64_x2(c, 1);
+}
diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_psel.c b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_psel.c
index aa2a35c2fd25..73b7b0347dd9 100644
--- a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_psel.c
+++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_psel.c
@@ -5,6 +5,11 @@
 // RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu \
 // RUN:   -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
 // RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
+// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu \
+// RUN:   -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu \
+// RUN:   -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
 
 #include <arm_sve.h>
 
@@ -20,7 +25,7 @@
 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv16i1(<vscale x 16 x i1> [[P1:%.*]], <vscale x 16 x i1> [[P2:%.*]], i32 [[ADD]])
 // CPP-CHECK-NEXT:    ret <vscale x 16 x i1> [[TMP0]]
 //
-svbool_t test_svpsel_lane_b8(svbool_t p1, svbool_t p2, uint32_t idx) {
+svbool_t test_svpsel_lane_b8(svbool_t p1, svbool_t p2, uint32_t idx) __arm_streaming_compatible {
   return svpsel_lane_b8(p1, p2, idx + 15);
 }
 
@@ -38,7 +43,7 @@ svbool_t test_svpsel_lane_b8(svbool_t p1, svbool_t p2, uint32_t idx) {
 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv8i1(<vscale x 16 x i1> [[P1:%.*]], <vscale x 8 x i1> [[TMP0]], i32 [[ADD]])
 // CPP-CHECK-NEXT:    ret <vscale x 16 x i1> [[TMP1]]
 //
-svbool_t test_svpsel_lane_b16(svbool_t p1, svbool_t p2, uint32_t idx) {
+svbool_t test_svpsel_lane_b16(svbool_t p1, svbool_t p2, uint32_t idx) __arm_streaming_compatible {
   return svpsel_lane_b16(p1, p2, idx + 7);
 }
 
@@ -56,7 +61,7 @@ svbool_t test_svpsel_lane_b16(svbool_t p1, svbool_t p2, uint32_t idx) {
 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv4i1(<vscale x 16 x i1> [[P1:%.*]], <vscale x 4 x i1> [[TMP0]], i32 [[ADD]])
 // CPP-CHECK-NEXT:    ret <vscale x 16 x i1> [[TMP1]]
 //
-svbool_t test_svpsel_lane_b32(svbool_t p1, svbool_t p2, uint32_t idx) {
+svbool_t test_svpsel_lane_b32(svbool_t p1, svbool_t p2, uint32_t idx) __arm_streaming_compatible {
   return svpsel_lane_b32(p1, p2, idx + 3);
 }
 
@@ -74,7 +79,7 @@ svbool_t test_svpsel_lane_b32(svbool_t p1, svbool_t p2, uint32_t idx) {
 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv2i1(<vscale x 16 x i1> [[P1:%.*]], <vscale x 2 x i1> [[TMP0]], i32 [[ADD]])
 // CPP-CHECK-NEXT:    ret <vscale x 16 x i1> [[TMP1]]
 //
-svbool_t test_svpsel_lane_b64(svbool_t p1, svbool_t p2, uint32_t idx) {
+svbool_t test_svpsel_lane_b64(svbool_t p1, svbool_t p2, uint32_t idx) __arm_streaming_compatible {
   return svpsel_lane_b64(p1, p2, idx + 1);
 }
 
@@ -94,7 +99,7 @@ svbool_t test_svpsel_lane_b64(svbool_t p1, svbool_t p2, uint32_t idx) {
 // CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.convert.from.svbool.taarch64.svcountt(<vscale x 16 x i1> [[TMP1]])
 // CPP-CHECK-NEXT:    ret target("aarch64.svcount") [[TMP2]]
 //
-svcount_t test_svpsel_lane_c8(svcount_t p1, svbool_t p2, uint32_t idx) {
+svcount_t test_svpsel_lane_c8(svcount_t p1, svbool_t p2, uint32_t idx) __arm_streaming_compatible {
   return svpsel_lane_c8(p1, p2, idx + 15);
 }
 
@@ -116,7 +121,7 @@ svcount_t test_svpsel_lane_c8(svcount_t p1, svbool_t p2, uint32_t idx) {
 // CPP-CHECK-NEXT:    [[TMP3:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.convert.from.svbool.taarch64.svcountt(<vscale x 16 x i1> [[TMP2]])
 // CPP-CHECK-NEXT:    ret target("aarch64.svcount") [[TMP3]]
 //
-svcount_t test_svpsel_lane_c16(svcount_t p1, svbool_t p2, uint32_t idx) {
+svcount_t test_svpsel_lane_c16(svcount_t p1, svbool_t p2, uint32_t idx) __arm_streaming_compatible {
   return svpsel_lane_c16(p1, p2, idx + 7);
 }
 
@@ -138,7 +143,7 @@ svcount_t test_svpsel_lane_c16(svcount_t p1, svbool_t p2, uint32_t idx) {
 // CPP-CHECK-NEXT:    [[TMP3:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.convert.from.svbool.taarch64.svcountt(<vscale x 16 x i1> [[TMP2]])
 // CPP-CHECK-NEXT:    ret target("aarch64.svcount") [[TMP3]]
 //
-svcount_t test_svpsel_lane_c32(svcount_t p1, svbool_t p2, uint32_t idx) {
+svcount_t test_svpsel_lane_c32(svcount_t p1, svbool_t p2, uint32_t idx) __arm_streaming_compatible {
   return svpsel_lane_c32(p1, p2, idx + 3);
 }
 
@@ -160,6 +165,6 @@ svcount_t test_svpsel_lane_c32(svcount_t p1, svbool_t p2, uint32_t idx) {
 // CPP-CHECK-NEXT:    [[TMP3:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.convert.from.svbool.taarch64.svcountt(<vscale x 16 x i1> [[TMP2]])
 // CPP-CHECK-NEXT:    ret target("aarch64.svcount") [[TMP3]]
 //
-svcount_t test_svpsel_lane_c64(svcount_t p1, svbool_t p2, uint32_t idx) {
+svcount_t test_svpsel_lane_c64(svcount_t p1, svbool_t p2, uint32_t idx) __arm_streaming_compatible {
   return svpsel_lane_c64(p1, p2, idx + 1);
 }
-- 
GitLab


From 54b4a0d688dd6463b81678273b125ff24dc25cff Mon Sep 17 00:00:00 2001
From: Fangrui Song <i@maskray.me>
Date: Mon, 11 Dec 2023 08:59:19 -0800
Subject: [PATCH 142/349] [llvm-readobj] --needed-libs: support
 --elf-output-style=JSON (#75028)

Close #74529
---
 llvm/test/tools/llvm-readobj/ELF/needed-libs.test | 13 +++++++++++++
 llvm/tools/llvm-readobj/ELFDumper.cpp             |  2 +-
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/llvm/test/tools/llvm-readobj/ELF/needed-libs.test b/llvm/test/tools/llvm-readobj/ELF/needed-libs.test
index d37ab6238e13..d2d0bdad26ed 100644
--- a/llvm/test/tools/llvm-readobj/ELF/needed-libs.test
+++ b/llvm/test/tools/llvm-readobj/ELF/needed-libs.test
@@ -5,6 +5,8 @@
 # RUN:   | FileCheck %s -DFILE=%t1 --implicit-check-not=warning: --strict-whitespace --check-prefix=NEEDED-LIBS
 # RUN: llvm-readelf --needed-libs %t1 2>&1 \
 # RUN:   | FileCheck %s -DFILE=%t1 --implicit-check-not=warning: --strict-whitespace --check-prefix=NEEDED-LIBS
+# RUN: llvm-readobj --elf-output-style=JSON --needed-libs --pretty-print %t1 2>&1 \
+# RUN:   | FileCheck %s -DFILE=%t1 --implicit-check-not=warning: --match-full-lines --strict-whitespace --check-prefix=JSON
 
 ## Check that library names are sorted when printed.
 ## Document that we also sort error entries.
@@ -19,6 +21,17 @@
 # NEEDED-LIBS-NEXT:{{^}}  ccc{{$}}
 # NEEDED-LIBS-NEXT:{{^}}]{{$}}
 
+#      JSON:    "FileSummary": {
+#      JSON:    "NeededLibraries": [{{.*}}warning: '[[FILE]]': string table at offset 0x78: unable to read the string at 0x9999a11: it goes past the end of the table (0x85)
+# JSON-NEXT:{{.*}}warning: '[[FILE]]': string table at offset 0x78: unable to read the string at 0x1111189: it goes past the end of the table (0x85)
+# JSON-EMPTY:
+# JSON-NEXT:      "<?>",
+# JSON-NEXT:      "<?>",
+# JSON-NEXT:      "aaa",
+# JSON-NEXT:      "bbb",
+# JSON-NEXT:      "ccc"
+# JSON-NEXT:    ]
+
 --- !ELF
 FileHeader:
   Class: ELFCLASS64
diff --git a/llvm/tools/llvm-readobj/ELFDumper.cpp b/llvm/tools/llvm-readobj/ELFDumper.cpp
index 85d5ab68b495..a9a31ae6c474 100644
--- a/llvm/tools/llvm-readobj/ELFDumper.cpp
+++ b/llvm/tools/llvm-readobj/ELFDumper.cpp
@@ -2581,7 +2581,7 @@ template <class ELFT> void ELFDumper<ELFT>::printNeededLibraries() {
   llvm::sort(Libs);
 
   for (StringRef L : Libs)
-    W.startLine() << L << "\n";
+    W.printString(L);
 }
 
 template <class ELFT>
-- 
GitLab


From a4e67de96f0a9833756b6c79fff3cd6ee459fee0 Mon Sep 17 00:00:00 2001
From: kkwli <kkwli@users.noreply.github.com>
Date: Mon, 11 Dec 2023 12:32:13 -0500
Subject: [PATCH 143/349] [flang] update ppc-vec-store-elem-order.f90 after
 #74709 (NFC) (#75064)

---
 .../Lower/PowerPC/ppc-vec-store-elem-order.f90   | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/flang/test/Lower/PowerPC/ppc-vec-store-elem-order.f90 b/flang/test/Lower/PowerPC/ppc-vec-store-elem-order.f90
index 494ed21f4fe9..caf6d5463a83 100644
--- a/flang/test/Lower/PowerPC/ppc-vec-store-elem-order.f90
+++ b/flang/test/Lower/PowerPC/ppc-vec-store-elem-order.f90
@@ -67,10 +67,10 @@ subroutine vec_xstd2_test(arg1, arg2, arg3, i)
 
 ! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
 ! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
-! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1
-! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1
-! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1
-! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0
+! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1
+! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1
+! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1
+! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0
 ! LLVMIR: %[[gep1:.*]] = getelementptr <4 x float>, ptr %2, i64 %[[iadd]]
 ! LLVMIR: %[[arg1:.*]] = load <4 x float>, ptr %0, align 16
 ! LLVMIR: %[[arg2:.*]] = load i16, ptr %1, align 2
@@ -93,10 +93,10 @@ subroutine vec_xstw4_test(arg1, arg2, arg3, i)
 
 ! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
 ! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
-! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1
-! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1
-! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1
-! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0
+! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1
+! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1
+! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1
+! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0
 ! LLVMIR: %[[gep1:.*]] = getelementptr <4 x float>, ptr %2, i64 %[[iadd]]
 ! LLVMIR: %[[arg1:.*]] = load <4 x float>, ptr %0, align 16
 ! LLVMIR: %[[arg2:.*]] = load i16, ptr %1, align 2
-- 
GitLab


From f92d970c8cc27747478abb7df66bb8b6701cea49 Mon Sep 17 00:00:00 2001
From: Youngsuk Kim <youngsuk.kim@hpe.com>
Date: Mon, 11 Dec 2023 11:50:53 -0600
Subject: [PATCH 144/349] [llvm][SanitizerCoverage] Remove no-op 'ptr
 addrspace(0)' to 'ptr addrspace(0)' pointercast (NFC)

Opaque ptr cleanup effort.
---
 llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp b/llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
index 906687663519..fe672a4377a1 100644
--- a/llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
+++ b/llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
@@ -329,8 +329,7 @@ ModuleSanitizerCoverage::CreateSecStartEnd(Module &M, const char *Section,
 
   // Account for the fact that on windows-msvc __start_* symbols actually
   // point to a uint64_t before the start of the array.
-  auto SecStartI8Ptr = IRB.CreatePointerCast(SecStart, PtrTy);
-  auto GEP = IRB.CreateGEP(Int8Ty, SecStartI8Ptr,
+  auto GEP = IRB.CreateGEP(Int8Ty, SecStart,
                            ConstantInt::get(IntptrTy, sizeof(uint64_t)));
   return std::make_pair(GEP, SecEnd);
 }
@@ -838,8 +837,7 @@ void ModuleSanitizerCoverage::InjectTraceForSwitch(
           *CurModule, ArrayOfInt64Ty, false, GlobalVariable::InternalLinkage,
           ConstantArray::get(ArrayOfInt64Ty, Initializers),
           "__sancov_gen_cov_switch_values");
-      IRB.CreateCall(SanCovTraceSwitchFunction,
-                     {Cond, IRB.CreatePointerCast(GV, PtrTy)});
+      IRB.CreateCall(SanCovTraceSwitchFunction, {Cond, GV});
     }
   }
 }
-- 
GitLab


From ef314d39b920a0989f17181ce280086146a71b75 Mon Sep 17 00:00:00 2001
From: Lang Hames <lhames@gmail.com>
Date: Sun, 10 Dec 2023 21:51:01 -0800
Subject: [PATCH 145/349] [ORC][MachO] Enable customization of MachO-headers
 produced by MachOPlatform.

MachOPlatform users can now override the default MachO header graph produced
for JITDylibs when setupJITDylib is called.
---
 .../llvm/ExecutionEngine/Orc/MachOPlatform.h  | 17 ++++++++++-
 .../lib/ExecutionEngine/Orc/MachOPlatform.cpp | 30 +++++++++++++------
 2 files changed, 37 insertions(+), 10 deletions(-)

diff --git a/llvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h b/llvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h
index ad205de16213..3a622281f227 100644
--- a/llvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h
+++ b/llvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h
@@ -47,6 +47,14 @@ public:
     LLVM_MARK_AS_BITMASK_ENUM(/* LargestValue = */ Callable)
   };
 
+  /// Used by setupJITDylib to create MachO header MaterializationUnits for
+  /// JITDylibs.
+  using MachOHeaderMUBuilder =
+      unique_function<std::unique_ptr<MaterializationUnit>(MachOPlatform &MOP)>;
+
+  static std::unique_ptr<MaterializationUnit>
+  defaultMachOHeaderBuilder(MachOPlatform &MOP);
+
   /// Try to create a MachOPlatform instance, adding the ORC runtime to the
   /// given JITDylib.
   ///
@@ -88,17 +96,23 @@ public:
   static Expected<std::unique_ptr<MachOPlatform>>
   Create(ExecutionSession &ES, ObjectLinkingLayer &ObjLinkingLayer,
          JITDylib &PlatformJD, std::unique_ptr<DefinitionGenerator> OrcRuntime,
+         MachOHeaderMUBuilder BuildMachOHeaderMU = defaultMachOHeaderBuilder,
          std::optional<SymbolAliasMap> RuntimeAliases = std::nullopt);
 
   /// Construct using a path to the ORC runtime.
   static Expected<std::unique_ptr<MachOPlatform>>
   Create(ExecutionSession &ES, ObjectLinkingLayer &ObjLinkingLayer,
          JITDylib &PlatformJD, const char *OrcRuntimePath,
+         MachOHeaderMUBuilder BuildMachOHeaderMU = defaultMachOHeaderBuilder,
          std::optional<SymbolAliasMap> RuntimeAliases = std::nullopt);
 
   ExecutionSession &getExecutionSession() const { return ES; }
   ObjectLinkingLayer &getObjectLinkingLayer() const { return ObjLinkingLayer; }
 
+  NonOwningSymbolStringPtr getMachOHeaderStartSymbol() const {
+    return NonOwningSymbolStringPtr(MachOHeaderStartSymbol);
+  }
+
   Error setupJITDylib(JITDylib &JD) override;
   Error teardownJITDylib(JITDylib &JD) override;
   Error notifyAdding(ResourceTracker &RT,
@@ -243,7 +257,7 @@ private:
   MachOPlatform(ExecutionSession &ES, ObjectLinkingLayer &ObjLinkingLayer,
                 JITDylib &PlatformJD,
                 std::unique_ptr<DefinitionGenerator> OrcRuntimeGenerator,
-                Error &Err);
+                MachOHeaderMUBuilder BuildMachOHeaderMU, Error &Err);
 
   // Associate MachOPlatform JIT-side runtime support functions with handlers.
   Error associateRuntimeSupportFunctions();
@@ -271,6 +285,7 @@ private:
   ExecutionSession &ES;
   JITDylib &PlatformJD;
   ObjectLinkingLayer &ObjLinkingLayer;
+  MachOHeaderMUBuilder BuildMachOHeaderMU;
 
   SymbolStringPtr MachOHeaderStartSymbol = ES.intern("___dso_handle");
 
diff --git a/llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp b/llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
index a155b39ae263..1a65bfc3234f 100644
--- a/llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
+++ b/llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
@@ -15,6 +15,7 @@
 #include "llvm/ExecutionEngine/Orc/DebugUtils.h"
 #include "llvm/ExecutionEngine/Orc/ExecutionUtils.h"
 #include "llvm/ExecutionEngine/Orc/LookupAndRecordAddrs.h"
+#include "llvm/ExecutionEngine/Orc/MachOBuilder.h"
 #include "llvm/ExecutionEngine/Orc/Shared/ObjectFormats.h"
 #include "llvm/Support/BinaryByteStream.h"
 #include "llvm/Support/Debug.h"
@@ -119,8 +120,9 @@ std::unique_ptr<jitlink::LinkGraph> createPlatformGraph(MachOPlatform &MOP,
 class MachOHeaderMaterializationUnit : public MaterializationUnit {
 public:
   MachOHeaderMaterializationUnit(MachOPlatform &MOP,
-                                 const SymbolStringPtr &HeaderStartSymbol)
-      : MaterializationUnit(createHeaderInterface(MOP, HeaderStartSymbol)),
+                                 SymbolStringPtr HeaderStartSymbol)
+      : MaterializationUnit(
+            createHeaderInterface(MOP, std::move(HeaderStartSymbol))),
         MOP(MOP) {}
 
   StringRef getName() const override { return "MachOHeaderMU"; }
@@ -348,10 +350,17 @@ struct ObjCImageInfoFlags {
 namespace llvm {
 namespace orc {
 
+std::unique_ptr<MaterializationUnit>
+MachOPlatform::defaultMachOHeaderBuilder(MachOPlatform &MOP) {
+  return std::make_unique<MachOHeaderMaterializationUnit>(
+      MOP, SymbolStringPtr(MOP.getMachOHeaderStartSymbol()));
+}
+
 Expected<std::unique_ptr<MachOPlatform>>
 MachOPlatform::Create(ExecutionSession &ES, ObjectLinkingLayer &ObjLinkingLayer,
                       JITDylib &PlatformJD,
                       std::unique_ptr<DefinitionGenerator> OrcRuntime,
+                      MachOHeaderMUBuilder BuildMachOHeaderMU,
                       std::optional<SymbolAliasMap> RuntimeAliases) {
 
   // If the target is not supported then bail out immediately.
@@ -382,8 +391,9 @@ MachOPlatform::Create(ExecutionSession &ES, ObjectLinkingLayer &ObjLinkingLayer,
 
   // Create the instance.
   Error Err = Error::success();
-  auto P = std::unique_ptr<MachOPlatform>(new MachOPlatform(
-      ES, ObjLinkingLayer, PlatformJD, std::move(OrcRuntime), Err));
+  auto P = std::unique_ptr<MachOPlatform>(
+      new MachOPlatform(ES, ObjLinkingLayer, PlatformJD, std::move(OrcRuntime),
+                        std::move(BuildMachOHeaderMU), Err));
   if (Err)
     return std::move(Err);
   return std::move(P);
@@ -392,6 +402,7 @@ MachOPlatform::Create(ExecutionSession &ES, ObjectLinkingLayer &ObjLinkingLayer,
 Expected<std::unique_ptr<MachOPlatform>>
 MachOPlatform::Create(ExecutionSession &ES, ObjectLinkingLayer &ObjLinkingLayer,
                       JITDylib &PlatformJD, const char *OrcRuntimePath,
+                      MachOHeaderMUBuilder BuildMachOHeaderMU,
                       std::optional<SymbolAliasMap> RuntimeAliases) {
 
   // Create a generator for the ORC runtime archive.
@@ -402,12 +413,11 @@ MachOPlatform::Create(ExecutionSession &ES, ObjectLinkingLayer &ObjLinkingLayer,
 
   return Create(ES, ObjLinkingLayer, PlatformJD,
                 std::move(*OrcRuntimeArchiveGenerator),
-                std::move(RuntimeAliases));
+                std::move(BuildMachOHeaderMU), std::move(RuntimeAliases));
 }
 
 Error MachOPlatform::setupJITDylib(JITDylib &JD) {
-  if (auto Err = JD.define(std::make_unique<MachOHeaderMaterializationUnit>(
-          *this, MachOHeaderStartSymbol)))
+  if (auto Err = JD.define(BuildMachOHeaderMU(*this)))
     return Err;
 
   return ES.lookup({&JD}, MachOHeaderStartSymbol).takeError();
@@ -522,8 +532,10 @@ MachOPlatform::flagsForSymbol(jitlink::Symbol &Sym) {
 MachOPlatform::MachOPlatform(
     ExecutionSession &ES, ObjectLinkingLayer &ObjLinkingLayer,
     JITDylib &PlatformJD,
-    std::unique_ptr<DefinitionGenerator> OrcRuntimeGenerator, Error &Err)
-    : ES(ES), PlatformJD(PlatformJD), ObjLinkingLayer(ObjLinkingLayer) {
+    std::unique_ptr<DefinitionGenerator> OrcRuntimeGenerator,
+    MachOHeaderMUBuilder BuildMachOHeaderMU, Error &Err)
+    : ES(ES), PlatformJD(PlatformJD), ObjLinkingLayer(ObjLinkingLayer),
+      BuildMachOHeaderMU(std::move(BuildMachOHeaderMU)) {
   ErrorAsOutParameter _(&Err);
   ObjLinkingLayer.addPlugin(std::make_unique<MachOPlatformPlugin>(*this));
   PlatformJD.addGenerator(std::move(OrcRuntimeGenerator));
-- 
GitLab


From 40e2bb5330840b56d452244f96e491b6530ce4bf Mon Sep 17 00:00:00 2001
From: Finn Plummer <50529406+inbelic@users.noreply.github.com>
Date: Mon, 11 Dec 2023 10:09:40 -0800
Subject: [PATCH 146/349] [mlir][spirv] Add folding for Bitwise[Or|And|Xor]
 (#74193)

Add missing constant propogation folder for Bitwise[Or|And|Xor].

Move previous Bitwise[Or|And] fold implementations to
SPIRVCanonicalization for consistency.

Implement additional folding when lhs == rhs and rhs = 0 for Xor. As
well as, update an Xor testcase to account for this introduced folding.

This helps for readability of lowered code into SPIR-V.

Part of work for #70704
---
 .../mlir/Dialect/SPIRV/IR/SPIRVBitOps.td      |   2 +
 .../SPIRV/IR/SPIRVCanonicalization.cpp        | 105 +++++++++-
 mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp        |  49 -----
 mlir/test/Dialect/SPIRV/IR/bit-ops.mlir       |   6 +-
 .../SPIRV/Transforms/canonicalize.mlir        | 188 ++++++++++++++++++
 5 files changed, 290 insertions(+), 60 deletions(-)

diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBitOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBitOps.td
index 7423bb3c68d7..b460c8e68aa0 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBitOps.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBitOps.td
@@ -334,6 +334,8 @@ def SPIRV_BitwiseXorOp : SPIRV_BitBinaryOp<"BitwiseXor",
     %2 = spirv.BitwiseXor %0, %1 : vector<4xi32>
     ```
   }];
+
+  let hasFolder = 1;
 }
 
 // -----
diff --git a/mlir/lib/Dialect/SPIRV/IR/SPIRVCanonicalization.cpp b/mlir/lib/Dialect/SPIRV/IR/SPIRVCanonicalization.cpp
index 4643fc08c08d..9de1707dfca4 100644
--- a/mlir/lib/Dialect/SPIRV/IR/SPIRVCanonicalization.cpp
+++ b/mlir/lib/Dialect/SPIRV/IR/SPIRVCanonicalization.cpp
@@ -722,9 +722,6 @@ OpFoldResult spirv::ShiftLeftLogicalOp::fold(
 
   // Unfortunately due to below undefined behaviour can't fold 0 for Base.
 
-  // According to the SPIR-V spec:
-  //
-  // Type is a scalar or vector of integer type.
   // Results are computed per component, and within each component, per bit...
   //
   // The result is undefined if Shift is greater than or equal to the bit width
@@ -756,9 +753,6 @@ OpFoldResult spirv::ShiftRightArithmeticOp::fold(
 
   // Unfortunately due to below undefined behaviour can't fold 0, -1 for Base.
 
-  // According to the SPIR-V spec:
-  //
-  // Type is a scalar or vector of integer type.
   // Results are computed per component, and within each component, per bit...
   //
   // The result is undefined if Shift is greater than or equal to the bit width
@@ -790,9 +784,6 @@ OpFoldResult spirv::ShiftRightLogicalOp::fold(
 
   // Unfortunately due to below undefined behaviour can't fold 0 for Base.
 
-  // According to the SPIR-V spec:
-  //
-  // Type is a scalar or vector of integer type.
   // Results are computed per component, and within each component, per bit...
   //
   // The result is undefined if Shift is greater than or equal to the bit width
@@ -811,6 +802,102 @@ OpFoldResult spirv::ShiftRightLogicalOp::fold(
   return shiftToLarge ? Attribute() : res;
 }
 
+//===----------------------------------------------------------------------===//
+// spirv.BitwiseAndOp
+//===----------------------------------------------------------------------===//
+
+OpFoldResult
+spirv::BitwiseAndOp::fold(spirv::BitwiseAndOp::FoldAdaptor adaptor) {
+  // x & x -> x
+  if (getOperand1() == getOperand2()) {
+    return getOperand1();
+  }
+
+  APInt rhsMask;
+  if (matchPattern(adaptor.getOperand2(), m_ConstantInt(&rhsMask))) {
+    // x & 0 -> 0
+    if (rhsMask.isZero())
+      return getOperand2();
+
+    // x & <all ones> -> x
+    if (rhsMask.isAllOnes())
+      return getOperand1();
+
+    // (UConvert x : iN to iK) & <mask with N low bits set> -> UConvert x
+    if (auto zext = getOperand1().getDefiningOp<spirv::UConvertOp>()) {
+      int valueBits =
+          getElementTypeOrSelf(zext.getOperand()).getIntOrFloatBitWidth();
+      if (rhsMask.zextOrTrunc(valueBits).isAllOnes())
+        return getOperand1();
+    }
+  }
+
+  // According to the SPIR-V spec:
+  //
+  // Type is a scalar or vector of integer type.
+  // Results are computed per component, and within each component, per bit.
+  // So we can use the APInt & method.
+  return constFoldBinaryOp<IntegerAttr>(
+      adaptor.getOperands(),
+      [](const APInt &a, const APInt &b) { return a & b; });
+}
+
+//===----------------------------------------------------------------------===//
+// spirv.BitwiseOrOp
+//===----------------------------------------------------------------------===//
+
+OpFoldResult spirv::BitwiseOrOp::fold(spirv::BitwiseOrOp::FoldAdaptor adaptor) {
+  // x | x -> x
+  if (getOperand1() == getOperand2()) {
+    return getOperand1();
+  }
+
+  APInt rhsMask;
+  if (matchPattern(adaptor.getOperand2(), m_ConstantInt(&rhsMask))) {
+    // x | 0 -> x
+    if (rhsMask.isZero())
+      return getOperand1();
+
+    // x | <all ones> -> <all ones>
+    if (rhsMask.isAllOnes())
+      return getOperand2();
+  }
+
+  // According to the SPIR-V spec:
+  //
+  // Type is a scalar or vector of integer type.
+  // Results are computed per component, and within each component, per bit.
+  // So we can use the APInt | method.
+  return constFoldBinaryOp<IntegerAttr>(
+      adaptor.getOperands(),
+      [](const APInt &a, const APInt &b) { return a | b; });
+}
+
+//===----------------------------------------------------------------------===//
+// spirv.BitwiseXorOp
+//===----------------------------------------------------------------------===//
+
+OpFoldResult
+spirv::BitwiseXorOp::fold(spirv::BitwiseXorOp::FoldAdaptor adaptor) {
+  // x ^ 0 -> x
+  if (matchPattern(adaptor.getOperand2(), m_Zero())) {
+    return getOperand1();
+  }
+
+  // x ^ x -> 0
+  if (getOperand1() == getOperand2())
+    return Builder(getContext()).getZeroAttr(getType());
+
+  // According to the SPIR-V spec:
+  //
+  // Type is a scalar or vector of integer type.
+  // Results are computed per component, and within each component, per bit.
+  // So we can use the APInt ^ method.
+  return constFoldBinaryOp<IntegerAttr>(
+      adaptor.getOperands(),
+      [](const APInt &a, const APInt &b) { return a ^ b; });
+}
+
 //===----------------------------------------------------------------------===//
 // spirv.mlir.selection
 //===----------------------------------------------------------------------===//
diff --git a/mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp b/mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
index 3906bf74ea72..2a1d08330828 100644
--- a/mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
+++ b/mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
@@ -1968,55 +1968,6 @@ LogicalResult spirv::ShiftRightLogicalOp::verify() {
   return verifyShiftOp(*this);
 }
 
-//===----------------------------------------------------------------------===//
-// spirv.BtiwiseAndOp
-//===----------------------------------------------------------------------===//
-
-OpFoldResult
-spirv::BitwiseAndOp::fold(spirv::BitwiseAndOp::FoldAdaptor adaptor) {
-  APInt rhsMask;
-  if (!matchPattern(adaptor.getOperand2(), m_ConstantInt(&rhsMask)))
-    return {};
-
-  // x & 0 -> 0
-  if (rhsMask.isZero())
-    return getOperand2();
-
-  // x & <all ones> -> x
-  if (rhsMask.isAllOnes())
-    return getOperand1();
-
-  // (UConvert x : iN to iK) & <mask with N low bits set> -> UConvert x
-  if (auto zext = getOperand1().getDefiningOp<spirv::UConvertOp>()) {
-    int valueBits =
-        getElementTypeOrSelf(zext.getOperand()).getIntOrFloatBitWidth();
-    if (rhsMask.zextOrTrunc(valueBits).isAllOnes())
-      return getOperand1();
-  }
-
-  return {};
-}
-
-//===----------------------------------------------------------------------===//
-// spirv.BtiwiseOrOp
-//===----------------------------------------------------------------------===//
-
-OpFoldResult spirv::BitwiseOrOp::fold(spirv::BitwiseOrOp::FoldAdaptor adaptor) {
-  APInt rhsMask;
-  if (!matchPattern(adaptor.getOperand2(), m_ConstantInt(&rhsMask)))
-    return {};
-
-  // x | 0 -> x
-  if (rhsMask.isZero())
-    return getOperand1();
-
-  // x | <all ones> -> <all ones>
-  if (rhsMask.isAllOnes())
-    return getOperand2();
-
-  return {};
-}
-
 //===----------------------------------------------------------------------===//
 // spirv.ImageQuerySize
 //===----------------------------------------------------------------------===//
diff --git a/mlir/test/Dialect/SPIRV/IR/bit-ops.mlir b/mlir/test/Dialect/SPIRV/IR/bit-ops.mlir
index 82a2316f6c78..f3f0ebf60f46 100644
--- a/mlir/test/Dialect/SPIRV/IR/bit-ops.mlir
+++ b/mlir/test/Dialect/SPIRV/IR/bit-ops.mlir
@@ -149,14 +149,16 @@ func.func @bitwise_or_float(%arg0: f16, %arg1: f16) -> f16 {
 //===----------------------------------------------------------------------===//
 
 func.func @bitwise_xor_scalar(%arg: i32) -> i32 {
+  %c1 = spirv.Constant 1 : i32 // using constant to avoid folding
   // CHECK: spirv.BitwiseXor
-  %0 = spirv.BitwiseXor %arg, %arg : i32
+  %0 = spirv.BitwiseXor %c1, %arg : i32
   return %0 : i32
 }
 
 func.func @bitwise_xor_vector(%arg: vector<4xi32>) -> vector<4xi32> {
+  %c1 = spirv.Constant dense<1> : vector<4xi32> // using constant to avoid folding
   // CHECK: spirv.BitwiseXor
-  %0 = spirv.BitwiseXor %arg, %arg : vector<4xi32>
+  %0 = spirv.BitwiseXor %c1, %arg : vector<4xi32>
   return %0 : vector<4xi32>
 }
 
diff --git a/mlir/test/Dialect/SPIRV/Transforms/canonicalize.mlir b/mlir/test/Dialect/SPIRV/Transforms/canonicalize.mlir
index 6be4b8d20ff3..29bea91ce461 100644
--- a/mlir/test/Dialect/SPIRV/Transforms/canonicalize.mlir
+++ b/mlir/test/Dialect/SPIRV/Transforms/canonicalize.mlir
@@ -1317,6 +1317,194 @@ func.func @const_fold_vector_lsr() -> vector<3xi32> {
 
 // -----
 
+//===----------------------------------------------------------------------===//
+// spirv.BitwiseAnd
+//===----------------------------------------------------------------------===//
+
+// CHECK-LABEL: @bitwise_and_x_x
+// CHECK-SAME: (%[[ARG0:.*]]: i32, %[[ARG1:.*]]: vector<3xi32>)
+func.func @bitwise_and_x_x(%arg0: i32, %arg1: vector<3xi32>) -> (i32, vector<3xi32>) {
+  %0 = spirv.BitwiseAnd %arg0, %arg0 : i32
+  %1 = spirv.BitwiseAnd %arg1, %arg1 : vector<3xi32>
+
+  // CHECK: return %[[ARG0]], %[[ARG1]]
+  return %0, %1 : i32, vector<3xi32>
+}
+
+// CHECK-LABEL: @bitwise_and_x_0
+func.func @bitwise_and_x_0(%arg0 : i32, %arg1 : vector<3xi32>) -> (i32, vector<3xi32>) {
+  // CHECK-DAG: %[[C0:.*]] = spirv.Constant 0 : i32
+  // CHECK-DAG: %[[CV0:.*]] = spirv.Constant dense<0> : vector<3xi32>
+  %c0 = spirv.Constant 0 : i32
+  %cv0 = spirv.Constant dense<0> : vector<3xi32>
+
+  %0 = spirv.BitwiseAnd %arg0, %c0 : i32
+  %1 = spirv.BitwiseAnd %arg1, %cv0 : vector<3xi32>
+
+  // CHECK: return %[[C0]], %[[CV0]]
+  return %0, %1 : i32, vector<3xi32>
+}
+
+// CHECK-LABEL: @bitwise_and_x_n1
+// CHECK-SAME: (%[[ARG0:.*]]: i32, %[[ARG1:.*]]: vector<3xi32>)
+func.func @bitwise_and_x_n1(%arg0: i32, %arg1: vector<3xi32>) -> (i32, vector<3xi32>) {
+  %cn1 = spirv.Constant -1 : i32
+  %cvn1 = spirv.Constant dense<-1> : vector<3xi32>
+  %0 = spirv.BitwiseAnd %arg0, %cn1 : i32
+  %1 = spirv.BitwiseAnd %arg1, %cvn1 : vector<3xi32>
+
+  // CHECK: return %[[ARG0]], %[[ARG1]]
+  return %0, %1 : i32, vector<3xi32>
+}
+
+// CHECK-LABEL: @const_fold_scalar_band
+func.func @const_fold_scalar_band() -> i32 {
+  %c1 = spirv.Constant -268464129 : i32   // 0xefff 8fff
+  %c2 = spirv.Constant 268464128: i32     // 0x1000 7000
+
+  // 0xefff 8fff | 0x1000 7000 = 0xffff ffff = -1
+  // CHECK: %[[C0:.*]] = spirv.Constant 0
+  %0 = spirv.BitwiseAnd %c1, %c2 : i32
+
+  // CHECK: return %[[C0]]
+  return %0 : i32
+}
+
+// CHECK-LABEL: @const_fold_vector_band
+func.func @const_fold_vector_band() -> vector<3xi32> {
+  %c1 = spirv.Constant dense<[42, -55, 127]> : vector<3xi32>
+  %c2 = spirv.Constant dense<[-3, -15, 28]> : vector<3xi32>
+
+  // CHECK: %[[CV:.*]] = spirv.Constant dense<[40, -63, 28]>
+  %0 = spirv.BitwiseAnd %c1, %c2 : vector<3xi32>
+
+  // CHECK: return %[[CV]]
+  return %0 : vector<3xi32>
+}
+
+// -----
+
+//===----------------------------------------------------------------------===//
+// spirv.BitwiseOr
+//===----------------------------------------------------------------------===//
+
+// CHECK-LABEL: @bitwise_or_x_x
+// CHECK-SAME: (%[[ARG0:.*]]: i32, %[[ARG1:.*]]: vector<3xi32>)
+func.func @bitwise_or_x_x(%arg0: i32, %arg1: vector<3xi32>) -> (i32, vector<3xi32>) {
+  %0 = spirv.BitwiseOr %arg0, %arg0 : i32
+  %1 = spirv.BitwiseOr %arg1, %arg1 : vector<3xi32>
+
+  // CHECK: return %[[ARG0]], %[[ARG1]]
+  return %0, %1 : i32, vector<3xi32>
+}
+
+// CHECK-LABEL: @bitwise_or_x_0
+// CHECK-SAME: (%[[ARG0:.*]]: i32, %[[ARG1:.*]]: vector<3xi32>)
+func.func @bitwise_or_x_0(%arg0: i32, %arg1: vector<3xi32>) -> (i32, vector<3xi32>) {
+  %c1 = spirv.Constant 0 : i32
+  %cv1 = spirv.Constant dense<0> : vector<3xi32>
+  %0 = spirv.BitwiseOr %arg0, %c1 : i32
+  %1 = spirv.BitwiseOr %arg1, %cv1 : vector<3xi32>
+
+  // CHECK: return %[[ARG0]], %[[ARG1]]
+  return %0, %1 : i32, vector<3xi32>
+}
+
+// CHECK-LABEL: @bitwise_or_x_n1
+func.func @bitwise_or_x_n1(%arg0 : i32, %arg1 : vector<3xi32>) -> (i32, vector<3xi32>) {
+  // CHECK-DAG: %[[CN1:.*]] = spirv.Constant -1 : i32
+  // CHECK-DAG: %[[CVN1:.*]] = spirv.Constant dense<-1> : vector<3xi32>
+  %cn1 = spirv.Constant -1 : i32
+  %cvn1 = spirv.Constant dense<-1> : vector<3xi32>
+  %0 = spirv.BitwiseOr %arg0, %cn1 : i32
+  %1 = spirv.BitwiseOr %arg1, %cvn1 : vector<3xi32>
+
+  // CHECK: return %[[CN1]], %[[CVN1]]
+  return %0, %1 : i32, vector<3xi32>
+}
+
+// CHECK-LABEL: @const_fold_scalar_bor
+func.func @const_fold_scalar_bor() -> i32 {
+  %c1 = spirv.Constant -268464129 : i32   // 0xefff 8fff
+  %c2 = spirv.Constant 268464128: i32     // 0x1000 7000
+
+  // 0xefff 8fff | 0x1000 7000 = 0xffff ffff = -1
+  // CHECK: %[[CN1:.*]] = spirv.Constant -1
+  %0 = spirv.BitwiseOr %c1, %c2 : i32
+
+  // CHECK: return %[[CN1]]
+  return %0 : i32
+}
+
+// CHECK-LABEL: @const_fold_vector_bor
+func.func @const_fold_vector_bor() -> vector<3xi32> {
+  %c1 = spirv.Constant dense<[42, -55, 127]> : vector<3xi32>
+  %c2 = spirv.Constant dense<[-3, -15, 28]> : vector<3xi32>
+
+  // CHECK: %[[CV:.*]] = spirv.Constant dense<[-1, -7, 127]>
+  %0 = spirv.BitwiseOr %c1, %c2 : vector<3xi32>
+
+  // CHECK: return %[[CV]]
+  return %0 : vector<3xi32>
+}
+
+// -----
+
+//===----------------------------------------------------------------------===//
+// spirv.BitwiseXor
+//===----------------------------------------------------------------------===//
+
+// CHECK-LABEL: @bitwise_xor_x_0
+// CHECK-SAME: (%[[ARG0:.*]]: i32, %[[ARG1:.*]]: vector<3xi32>)
+func.func @bitwise_xor_x_0(%arg0: i32, %arg1: vector<3xi32>) -> (i32, vector<3xi32>) {
+  %c0 = spirv.Constant 0 : i32
+  %cv0 = spirv.Constant dense<0> : vector<3xi32>
+
+  %0 = spirv.BitwiseXor %arg0, %c0 : i32
+  %1 = spirv.BitwiseXor %arg1, %cv0 : vector<3xi32>
+
+  // CHECK: return %[[ARG0]], %[[ARG1]]
+  return %0, %1 : i32, vector<3xi32>
+}
+
+// CHECK-LABEL: @bitwise_xor_x_x
+func.func @bitwise_xor_x_x(%arg0 : i32, %arg1 : vector<3xi32>) -> (i32, vector<3xi32>) {
+  // CHECK-DAG: %[[C0:.*]] = spirv.Constant 0
+  // CHECK-DAG: %[[CV0:.*]] = spirv.Constant dense<0>
+  %0 = spirv.BitwiseXor %arg0, %arg0 : i32
+  %1 = spirv.BitwiseXor %arg1, %arg1 : vector<3xi32>
+
+  // CHECK: return %[[C0]], %[[CV0]]
+  return %0, %1 : i32, vector<3xi32>
+}
+
+// CHECK-LABEL: @const_fold_scalar_bxor
+func.func @const_fold_scalar_bxor() -> i32 {
+  %c1 = spirv.Constant 4294967295 : i32  // 2^32 - 1: 0xffff ffff
+  %c2 = spirv.Constant -2147483648 : i32 // -2^31   : 0x8000 0000
+
+  // 0x8000 0000 ^ 0xffff fffe = 0xefff ffff
+  // CHECK: %[[CBIG:.*]] = spirv.Constant 2147483647
+  %0 = spirv.BitwiseXor %c1, %c2 : i32
+
+  // CHECK: return %[[CBIG]]
+  return %0 : i32
+}
+
+// CHECK-LABEL: @const_fold_vector_bxor
+func.func @const_fold_vector_bxor() -> vector<3xi32> {
+  %c1 = spirv.Constant dense<[42, -55, 127]> : vector<3xi32>
+  %c2 = spirv.Constant dense<[-3, -15, 28]> : vector<3xi32>
+
+  // CHECK: %[[CV:.*]] = spirv.Constant dense<[-41, 56, 99]>
+  %0 = spirv.BitwiseXor %c1, %c2 : vector<3xi32>
+
+  // CHECK: return %[[CV]]
+  return %0 : vector<3xi32>
+}
+
+// -----
+
 //===----------------------------------------------------------------------===//
 // spirv.mlir.selection
 //===----------------------------------------------------------------------===//
-- 
GitLab


From d96f46dd20157be9c11e16d8bdd3ebf900df41fc Mon Sep 17 00:00:00 2001
From: Aart Bik <39774503+aartbik@users.noreply.github.com>
Date: Mon, 11 Dec 2023 10:22:17 -0800
Subject: [PATCH 147/349] [mlir][sparse] fix bug in custom reduction
 scalarization code (#74898)

Bug found with BSR of "spy" SDDMM method
---
 .../Transforms/Sparsification.cpp             |  24 ++--
 .../Dialect/SparseTensor/spy_sddmm_bsr.mlir   | 103 ++++++++++++++++++
 2 files changed, 120 insertions(+), 7 deletions(-)
 create mode 100755 mlir/test/Dialect/SparseTensor/spy_sddmm_bsr.mlir

diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp b/mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp
index 6c9adf9fa21a..992be434fc62 100644
--- a/mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp
+++ b/mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp
@@ -673,25 +673,35 @@ static void genInvariants(CodegenEnv &env, OpBuilder &builder, ExprId exp,
     // All exhausted at current level.
     if (!isCurrentLoop)
       return;
+    // Generate code for a scalarized reduction or invariant. Note that
+    // because custom reduction lhs may occur several times in the IR,
+    // we have a built-in safety for only initializing and wrapping-up
+    // the scalarized reduction once.
     OpOperand *lhs = op.getDpsInitOperand(0);
     if (lhs == &t) {
       // Start or end a scalarized reduction.
       if (isStart) {
-        Value load = env.isCustomReduc() ? env.getCustomRedId()
-                                         : genTensorLoad(env, builder, exp);
-        env.startReduc(exp, load);
+        if (env.isCustomReduc()) {
+          if (!env.isReduc())
+            env.startReduc(exp, env.getCustomRedId());
+        } else {
+          env.startReduc(exp, genTensorLoad(env, builder, exp));
+        }
         if (env.hasSparseOutput())
           env.setValidLexInsert(constantI1(builder, env.op().getLoc(), false));
       } else {
-        genTensorStore(env, builder, exp, env.endReduc());
-        env.clearValidLexInsert();
+        if (!env.isCustomReduc() || env.isReduc())
+          genTensorStore(env, builder, exp, env.endReduc());
+        if (env.hasSparseOutput())
+          env.clearValidLexInsert();
       }
     } else {
       // Start or end loop invariant hoisting of a tensor load.
-      if (isStart)
+      if (isStart) {
         env.merger().setExprValue(exp, genTensorLoad(env, builder, exp));
-      else
+      } else {
         env.merger().clearExprValue(exp);
+      }
     }
   } else if (env.exp(exp).kind != TensorExp::Kind::kInvariant &&
              env.exp(exp).kind != TensorExp::Kind::kLoopVar &&
diff --git a/mlir/test/Dialect/SparseTensor/spy_sddmm_bsr.mlir b/mlir/test/Dialect/SparseTensor/spy_sddmm_bsr.mlir
new file mode 100755
index 000000000000..ed8d63987896
--- /dev/null
+++ b/mlir/test/Dialect/SparseTensor/spy_sddmm_bsr.mlir
@@ -0,0 +1,103 @@
+// RUN: mlir-opt %s --sparse-reinterpret-map -sparsification | FileCheck %s
+
+//
+// A SDDMM implementation with "spy" function and
+// in-place update of the sampling sparse matrix.
+//
+
+#BSR = #sparse_tensor.encoding<{
+  map = (i, j) -> (
+    i floordiv 2 : dense,
+    j floordiv 2 : compressed,
+    i mod 2 : dense,
+    j mod 2 : dense)
+}>
+
+#trait_SDDMM = {
+  indexing_maps = [
+    affine_map<(i,j,k) -> (i,k)>,  // A
+    affine_map<(i,j,k) -> (k,j)>,  // B
+    affine_map<(i,j,k) -> (i,j)>   // S (in/out)
+  ],
+  iterator_types = ["parallel", "parallel", "reduction"],
+  doc = "S(i,j) += spy[S(i,j)] x SUM_k A(i,k) B(k,j)"
+}
+
+//
+// CHECK: #[[$BSR:.+]] = #sparse_tensor.encoding<{ map = (d0, d1) -> (d0 floordiv 2 : dense, d1 floordiv 2 : compressed, d0 mod 2 : dense, d1 mod 2 : dense) }>
+// CHECK: #[[$MAP:.+]] = #sparse_tensor.encoding<{ map = (d0, d1, d2, d3) -> (d0 : dense, d1 : compressed, d2 : dense, d3 : dense) }>
+//
+// CHECK-LABEL:   func.func @SDDMM_block(
+// CHECK-SAME:      %[[VAL_0:.*]]: tensor<?x?xf32, #[[$BSR]]>,
+// CHECK-SAME:      %[[VAL_1:.*]]: tensor<?x?xf32>,
+// CHECK-SAME:      %[[VAL_2:.*]]: tensor<?x?xf32>) -> tensor<?x?xf32, #[[$BSR]]> {
+// CHECK-DAG:       %[[VAL_3:.*]] = arith.constant 1 : index
+// CHECK-DAG:       %[[VAL_4:.*]] = arith.constant 0 : index
+// CHECK-DAG:       %[[VAL_5:.*]] = arith.constant 2 : index
+// CHECK-DAG:       %[[VAL_6:.*]] = arith.constant 0.000000e+00 : f32
+// CHECK:           %[[VAL_7:.*]] = sparse_tensor.reinterpret_map %[[VAL_0]] : tensor<?x?xf32, #[[$BSR]]> to tensor<?x?x2x2xf32, #[[$MAP]]>
+// CHECK:           %[[VAL_8:.*]] = tensor.dim %[[VAL_1]], %[[VAL_3]] : tensor<?x?xf32>
+// CHECK:           %[[VAL_9:.*]] = bufferization.to_memref %[[VAL_1]] : memref<?x?xf32>
+// CHECK:           %[[VAL_10:.*]] = bufferization.to_memref %[[VAL_2]] : memref<?x?xf32>
+// CHECK:           %[[VAL_11:.*]] = sparse_tensor.lvl %[[VAL_7]], %[[VAL_4]] : tensor<?x?x2x2xf32, #[[$MAP]]>
+// CHECK:           %[[VAL_12:.*]] = sparse_tensor.positions %[[VAL_7]] {level = 1 : index} : tensor<?x?x2x2xf32, #[[$MAP]]> to memref<?xindex>
+// CHECK:           %[[VAL_13:.*]] = sparse_tensor.coordinates %[[VAL_7]] {level = 1 : index} : tensor<?x?x2x2xf32, #[[$MAP]]> to memref<?xindex>
+// CHECK:           %[[VAL_14:.*]] = sparse_tensor.values %[[VAL_7]] : tensor<?x?x2x2xf32, #[[$MAP]]> to memref<?xf32>
+// CHECK:           scf.for %[[VAL_15:.*]] = %[[VAL_4]] to %[[VAL_11]] step %[[VAL_3]] {
+// CHECK:             %[[VAL_16:.*]] = memref.load %[[VAL_12]]{{\[}}%[[VAL_15]]] : memref<?xindex>
+// CHECK:             %[[VAL_17:.*]] = arith.addi %[[VAL_15]], %[[VAL_3]] : index
+// CHECK:             %[[VAL_18:.*]] = memref.load %[[VAL_12]]{{\[}}%[[VAL_17]]] : memref<?xindex>
+// CHECK:             scf.for %[[VAL_19:.*]] = %[[VAL_16]] to %[[VAL_18]] step %[[VAL_3]] {
+// CHECK:               %[[VAL_20:.*]] = memref.load %[[VAL_13]]{{\[}}%[[VAL_19]]] : memref<?xindex>
+// CHECK:               scf.for %[[VAL_21:.*]] = %[[VAL_4]] to %[[VAL_5]] step %[[VAL_3]] {
+// CHECK:                 %[[VAL_22:.*]] = arith.muli %[[VAL_19]], %[[VAL_5]] : index
+// CHECK:                 %[[VAL_23:.*]] = arith.addi %[[VAL_22]], %[[VAL_21]] : index
+// CHECK:                 scf.for %[[VAL_24:.*]] = %[[VAL_4]] to %[[VAL_5]] step %[[VAL_3]] {
+// CHECK:                   %[[VAL_25:.*]] = arith.muli %[[VAL_23]], %[[VAL_5]] : index
+// CHECK:                   %[[VAL_26:.*]] = arith.addi %[[VAL_25]], %[[VAL_24]] : index
+// CHECK:                   %[[VAL_27:.*]] = scf.for %[[VAL_28:.*]] = %[[VAL_4]] to %[[VAL_8]] step %[[VAL_3]] iter_args(%[[VAL_29:.*]] = %[[VAL_6]]) -> (f32) {
+// CHECK:                     %[[VAL_30:.*]] = arith.muli %[[VAL_15]], %[[VAL_5]] : index
+// CHECK:                     %[[VAL_31:.*]] = arith.addi %[[VAL_30]], %[[VAL_21]] : index
+// CHECK:                     %[[VAL_32:.*]] = memref.load %[[VAL_9]]{{\[}}%[[VAL_31]], %[[VAL_28]]] : memref<?x?xf32>
+// CHECK:                     %[[VAL_33:.*]] = arith.muli %[[VAL_20]], %[[VAL_5]] : index
+// CHECK:                     %[[VAL_34:.*]] = arith.addi %[[VAL_33]], %[[VAL_24]] : index
+// CHECK:                     %[[VAL_35:.*]] = memref.load %[[VAL_10]]{{\[}}%[[VAL_28]], %[[VAL_34]]] : memref<?x?xf32>
+// CHECK:                     %[[VAL_36:.*]] = arith.mulf %[[VAL_32]], %[[VAL_35]] : f32
+// CHECK:                     %[[VAL_37:.*]] = arith.addf %[[VAL_29]], %[[VAL_36]] : f32
+// CHECK:                     scf.yield %[[VAL_37]] : f32
+// CHECK:                   } {"Emitted from" = "linalg.generic"}
+// CHECK:                   memref.store %[[VAL_27]], %[[VAL_14]]{{\[}}%[[VAL_26]]] : memref<?xf32>
+// CHECK:                 } {"Emitted from" = "linalg.generic"}
+// CHECK:               } {"Emitted from" = "linalg.generic"}
+// CHECK:             } {"Emitted from" = "linalg.generic"}
+// CHECK:           } {"Emitted from" = "linalg.generic"}
+// CHECK:           %[[VAL_38:.*]] = sparse_tensor.load %[[VAL_7]] : tensor<?x?x2x2xf32, #[[$MAP]]>
+// CHECK:           %[[VAL_39:.*]] = sparse_tensor.reinterpret_map %[[VAL_38]] : tensor<?x?x2x2xf32, #[[$MAP]]> to tensor<?x?xf32, #[[$BSR]]>
+// CHECK:           return %[[VAL_39]] : tensor<?x?xf32, #[[$BSR]]>
+// CHECK:         }
+module {
+  func.func @SDDMM_block(%args: tensor<?x?xf32, #BSR>,
+                         %arga: tensor<?x?xf32>,
+                         %argb: tensor<?x?xf32>) -> tensor<?x?xf32, #BSR> {
+    %result = linalg.generic #trait_SDDMM
+      ins(%arga, %argb: tensor<?x?xf32>, tensor<?x?xf32>)
+      outs(%args: tensor<?x?xf32, #BSR>) {
+        ^bb(%a: f32, %b: f32, %s: f32):
+           %f0 = arith.constant 0.0 : f32
+           %u = sparse_tensor.unary %s : f32 to f32
+             present={
+                ^bb0(%p: f32):
+                  %mul = arith.mulf %a, %b : f32
+                  sparse_tensor.yield %mul : f32
+             }
+             absent={}
+           %r = sparse_tensor.reduce %s, %u, %f0 : f32 {
+              ^bb0(%p: f32, %q: f32):
+                %add = arith.addf %p, %q : f32
+                sparse_tensor.yield %add : f32
+            }
+           linalg.yield %r : f32
+      } -> tensor<?x?xf32, #BSR>
+    return %result : tensor<?x?xf32, #BSR>
+  }
+}
-- 
GitLab


From 3745f475875d763b65541e0bab195b0d774ff9c8 Mon Sep 17 00:00:00 2001
From: Amy Huang <akhuang@google.com>
Date: Mon, 11 Dec 2023 10:38:46 -0800
Subject: [PATCH 148/349] Fix to msvc::no_unique_address causing assert when
 used with __declspec(empty_bases) (#74776)

no_unique_address makes it possible for a class to be empty and have
non-zero virtual size, so just remove this assert.

Bug: https://github.com/llvm/llvm-project/issues/74442
---
 clang/lib/AST/RecordLayoutBuilder.cpp         |  4 +-
 .../Layout/ms-x86-declspec-empty_bases.cpp    | 60 +++++++++++++++++++
 2 files changed, 62 insertions(+), 2 deletions(-)

diff --git a/clang/lib/AST/RecordLayoutBuilder.cpp b/clang/lib/AST/RecordLayoutBuilder.cpp
index a51c8b938f41..706991f4fb50 100644
--- a/clang/lib/AST/RecordLayoutBuilder.cpp
+++ b/clang/lib/AST/RecordLayoutBuilder.cpp
@@ -2942,8 +2942,8 @@ void MicrosoftRecordLayoutBuilder::layoutNonVirtualBase(
   }
 
   if (!FoundBase) {
-    if (MDCUsesEBO && BaseDecl->isEmpty()) {
-      assert(BaseLayout.getNonVirtualSize() == CharUnits::Zero());
+    if (MDCUsesEBO && BaseDecl->isEmpty() &&
+        (BaseLayout.getNonVirtualSize() == CharUnits::Zero())) {
       BaseOffset = CharUnits::Zero();
     } else {
       // Otherwise, lay the base out at the end of the MDC.
diff --git a/clang/test/Layout/ms-x86-declspec-empty_bases.cpp b/clang/test/Layout/ms-x86-declspec-empty_bases.cpp
index cc13a980cb5d..4738ce5720f7 100644
--- a/clang/test/Layout/ms-x86-declspec-empty_bases.cpp
+++ b/clang/test/Layout/ms-x86-declspec-empty_bases.cpp
@@ -264,3 +264,63 @@ int _ = sizeof(G);
 // CHECK-NEXT:            | [sizeof=12, align=4,
 // CHECK-NEXT:            |  nvsize=12, nvalign=4]
 }
+
+namespace test5 {
+
+struct A {
+  int a;
+};
+struct B {
+  int b;
+};
+struct C {};
+struct __declspec(align(16)) D {};
+struct E {
+  [[msvc::no_unique_address]] C c;
+};
+struct __declspec(empty_bases) X : A, D, B, C, E {
+};
+
+// CHECK: *** Dumping AST Record Layout
+// CHECK-NEXT:          0 | struct test5::A
+// CHECK-NEXT:          0 |   int a
+// CHECK-NEXT:            | [sizeof=4, align=4,
+// CHECK-NEXT:            |  nvsize=4, nvalign=4]
+
+// CHECK: *** Dumping AST Record Layout
+// CHECK-NEXT:          0 | struct test5::D (empty)
+// CHECK-NEXT:            | [sizeof=16, align=16,
+// CHECK-NEXT:            |  nvsize=0, nvalign=16]
+
+// CHECK: *** Dumping AST Record Layout
+// CHECK-NEXT:          0 | struct test5::B
+// CHECK-NEXT:          0 |   int b
+// CHECK-NEXT:            | [sizeof=4, align=4,
+// CHECK-NEXT:            |  nvsize=4, nvalign=4]
+
+// CHECK: *** Dumping AST Record Layout
+// CHECK-NEXT:          0 | struct test5::C (empty)
+// CHECK-NEXT:            | [sizeof=1, align=1,
+// CHECK-NEXT:            |  nvsize=0, nvalign=1]
+
+// CHECK: *** Dumping AST Record Layout
+// CHECK-NEXT:          0 | struct test5::E (empty)
+// CHECK-NEXT:          0 |   struct test5::C c (empty)
+// CHECK-NEXT:            | [sizeof=1, align=1,
+// CHECK-NEXT:            |  nvsize=1, nvalign=1]
+
+// CHECK: *** Dumping AST Record Layout
+// CHECK-NEXT:          0 | struct test5::X
+// CHECK-NEXT:          0 |   struct test5::A (base)
+// CHECK-NEXT:          0 |     int a
+// CHECK-NEXT:          0 |   struct test5::D (base) (empty)
+// CHECK-NEXT:          0 |   struct test5::C (base) (empty)
+// CHECK-NEXT:          4 |   struct test5::B (base)
+// CHECK-NEXT:          4 |     int b
+// CHECK-NEXT:          8 |   struct test5::E (base) (empty)
+// CHECK-NEXT:          8 |     struct test5::C c (empty)
+// CHECK-NEXT:            | [sizeof=16, align=16,
+// CHECK-NEXT:            |  nvsize=16, nvalign=16]
+
+int _ = sizeof(X);
+}
-- 
GitLab


From 12cbccc3125725fad00022a9b3a52ed9be69c3a3 Mon Sep 17 00:00:00 2001
From: Johannes Doerfert <johannes@jdoerfert.de>
Date: Mon, 11 Dec 2023 10:41:50 -0800
Subject: [PATCH 149/349] [OpenMP] Add extra flags to libomptarget and plugin
 builds (#74520)

---
 openmp/libomptarget/CMakeLists.txt            | 19 +++++++++++++++++++
 .../plugins-nextgen/common/CMakeLists.txt     |  3 +++
 openmp/libomptarget/src/CMakeLists.txt        |  3 +++
 3 files changed, 25 insertions(+)

diff --git a/openmp/libomptarget/CMakeLists.txt b/openmp/libomptarget/CMakeLists.txt
index e64a175be860..66925ccbe030 100644
--- a/openmp/libomptarget/CMakeLists.txt
+++ b/openmp/libomptarget/CMakeLists.txt
@@ -75,6 +75,25 @@ if(LIBOMPTARGET_ENABLE_DEBUG)
   add_definitions(-DOMPTARGET_DEBUG)
 endif()
 
+# No exceptions and no RTTI, except if requested.
+set(offload_compile_flags -fno-exceptions)
+if(NOT LLVM_ENABLE_RTTI)
+  set(offload_compile_flags ${offload_compile_flags} -fno-rtti)
+endif()
+
+# If LTO is not explicitly disabled we check if we can enable it and do so.
+set(LIBOMPTARGET_USE_LTO TRUE CACHE BOOL "Use LTO for the offload runtimes if available")
+if (LIBOMPTARGET_USE_LTO)
+  include(CheckIPOSupported)
+  check_ipo_supported(RESULT use_lto OUTPUT output)
+  if(use_lto)
+    set(offload_compile_flags ${offload_compile_flags} -flto)
+    set(offload_link_flags ${offload_link_flags} -flto)
+  else()
+    message(WARNING "LTO is not supported: ${output}")
+  endif()
+endif()
+
 # OMPT support for libomptarget
 # Follow host OMPT support and check if host support has been requested.
 # LIBOMP_HAVE_OMPT_SUPPORT indicates whether host OMPT support has been implemented.
diff --git a/openmp/libomptarget/plugins-nextgen/common/CMakeLists.txt b/openmp/libomptarget/plugins-nextgen/common/CMakeLists.txt
index 5b332ed3d2f4..8ae3ff2a6d29 100644
--- a/openmp/libomptarget/plugins-nextgen/common/CMakeLists.txt
+++ b/openmp/libomptarget/plugins-nextgen/common/CMakeLists.txt
@@ -88,6 +88,9 @@ target_compile_definitions(PluginCommon PRIVATE
   DEBUG_PREFIX="PluginInterface"
 )
 
+target_compile_options(PluginCommon PUBLIC ${offload_compile_flags})
+target_link_options(PluginCommon PUBLIC ${offload_link_flags})
+
 target_include_directories(PluginCommon
   PRIVATE
   ${LIBOMPTARGET_INCLUDE_DIR}
diff --git a/openmp/libomptarget/src/CMakeLists.txt b/openmp/libomptarget/src/CMakeLists.txt
index 7c07c61142ba..429a670be849 100644
--- a/openmp/libomptarget/src/CMakeLists.txt
+++ b/openmp/libomptarget/src/CMakeLists.txt
@@ -55,6 +55,9 @@ target_compile_definitions(omptarget PRIVATE
   DEBUG_PREFIX="omptarget"
 )
 
+target_compile_options(omptarget PUBLIC ${offload_compile_flags})
+target_link_options(omptarget PUBLIC ${offload_link_flags})
+
 macro(check_plugin_target target)
 if (TARGET omptarget.rtl.${target})
 	list(APPEND LIBOMPTARGET_PLUGINS_TO_LOAD ${target})
-- 
GitLab


From b1a91b7ee0e26139beeac4deed86a7323a50ca60 Mon Sep 17 00:00:00 2001
From: michaelrj-google <71531609+michaelrj-google@users.noreply.github.com>
Date: Mon, 11 Dec 2023 10:46:10 -0800
Subject: [PATCH 150/349] [libc][NFC] fix uint128 init in float properties
 (#75084)

An unsigned integer was being initialized with -1 to set all its bits to
1, but this doesn't work for the BigInt class which may be used as an
integer type on systems that don't support uint128 natively. This patch
moves the initialization to use ~T(0) instead.
---
 libc/src/__support/FPUtil/FloatProperties.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/libc/src/__support/FPUtil/FloatProperties.h b/libc/src/__support/FPUtil/FloatProperties.h
index ba54e9d1781c..ef6a3cd403db 100644
--- a/libc/src/__support/FPUtil/FloatProperties.h
+++ b/libc/src/__support/FPUtil/FloatProperties.h
@@ -85,7 +85,9 @@ template <typename T, size_t count> static constexpr T mask_trailing_ones() {
   static_assert(cpp::is_unsigned_v<T>);
   constexpr unsigned t_bits = CHAR_BIT * sizeof(T);
   static_assert(count <= t_bits && "Invalid bit index");
-  return count == 0 ? 0 : (T(-1) >> (t_bits - count));
+  // It's important not to initialize T with -1, since T may be BigInt which
+  // will take -1 as a uint64_t and only initialize the low 64 bits.
+  return count == 0 ? 0 : ((~T(0)) >> (t_bits - count));
 }
 
 // Derives more properties from 'FPBaseProperties' above.
@@ -131,7 +133,7 @@ private:
   LIBC_INLINE_VAR static constexpr UIntType FP_MASK =
       mask_trailing_ones<UIntType, TOTAL_BITS>();
   static_assert((SIG_MASK & EXP_MASK & SIGN_MASK_) == 0, "masks disjoint");
-  static_assert((SIG_MASK | EXP_MASK | SIGN_MASK_) == FP_MASK, "masks covers");
+  static_assert((SIG_MASK | EXP_MASK | SIGN_MASK_) == FP_MASK, "masks cover");
 
   LIBC_INLINE static constexpr UIntType bit_at(int position) {
     return UIntType(1) << position;
-- 
GitLab


From f576cbe44eabb8a5ac0af817424a0d1e7c8fbf85 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray <jonathan.thackray@arm.com>
Date: Mon, 11 Dec 2023 18:52:25 +0000
Subject: [PATCH 151/349] [AArch64] Correctly mark Neoverse N2 as an Armv9.0a
 core (#75055)

Neoverse N2 was incorrectly marked as an Armv8.5a core. This has been
changed to an Armv9.0a core. However, crypto options are not enabled
by default for Armv9 cores, so -mcpu=neoverse-n2+crypto is required
to enable crypto for this core.

Neoverse N2 Technical Reference Manual:
   https://developer.arm.com/documentation/102099/0003/
---
 clang/test/Driver/arm-cortex-cpus-2.c                |  2 +-
 llvm/docs/ReleaseNotes.rst                           |  7 +++++++
 llvm/include/llvm/TargetParser/AArch64TargetParser.h |  5 ++---
 llvm/include/llvm/TargetParser/ARMTargetParser.def   |  2 +-
 llvm/lib/Target/AArch64/AArch64.td                   |  4 ++--
 llvm/lib/Target/ARM/ARM.td                           |  2 +-
 llvm/test/CodeGen/AArch64/misched-fusion-aes.ll      |  1 -
 llvm/unittests/TargetParser/TargetParserTest.cpp     | 10 ++++------
 8 files changed, 18 insertions(+), 15 deletions(-)

diff --git a/clang/test/Driver/arm-cortex-cpus-2.c b/clang/test/Driver/arm-cortex-cpus-2.c
index 4bf2b3a50412..c322303d2278 100644
--- a/clang/test/Driver/arm-cortex-cpus-2.c
+++ b/clang/test/Driver/arm-cortex-cpus-2.c
@@ -566,7 +566,7 @@
 // CHECK-CORTEX-M52:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} "-target-cpu" "cortex-m52"
 
 // RUN: %clang -target arm -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NEOVERSE-N2 %s
-// CHECK-NEOVERSE-N2: "-cc1"{{.*}} "-triple" "armv8.5a-{{.*}}" "-target-cpu" "neoverse-n2"
+// CHECK-NEOVERSE-N2: "-cc1"{{.*}} "-triple" "armv9a-{{.*}}" "-target-cpu" "neoverse-n2"
 
 // ================== Check whether -mcpu accepts mixed-case values.
 // RUN: %clang -target arm-linux-gnueabi -mcpu=Cortex-a5 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CASE-INSENSITIVE-CPUV7A %s
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 6b70146efe82..d5c634d2f29a 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -94,6 +94,13 @@ Changes to the AArch64 Backend
 
 * Added support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs.
 
+* Neoverse-N2 was incorrectly marked as an Armv8.5a core. This has been
+  changed to an Armv9.0a core. However, crypto options are not enabled
+  by default for Armv9 cores, so `-mcpu=neoverse-n2+crypto` is now required
+  to enable crypto for this core. As far as the compiler is concerned,
+  Armv9.0a has the same features enabled as Armv8.5a, with the exception
+  of crypto.
+
 Changes to the AMDGPU Backend
 -----------------------------
 
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 17cafd146b0e..56c32fae712c 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -536,10 +536,9 @@ inline constexpr CpuInfo CpuInfos[] = {
          {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_DOTPROD,
           AArch64::AEK_FP16, AArch64::AEK_PROFILE, AArch64::AEK_RCPC,
           AArch64::AEK_SSBS}))},
-    {"neoverse-n2", ARMV8_5A,
+    {"neoverse-n2", ARMV9A,
      (AArch64::ExtensionBitset(
-         {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SHA3,
-          AArch64::AEK_SM4, AArch64::AEK_BF16, AArch64::AEK_DOTPROD,
+         {AArch64::AEK_BF16, AArch64::AEK_DOTPROD,
           AArch64::AEK_FP16, AArch64::AEK_I8MM, AArch64::AEK_MTE,
           AArch64::AEK_SB, AArch64::AEK_SSBS, AArch64::AEK_SVE,
           AArch64::AEK_SVE2, AArch64::AEK_SVE2BITPERM}))},
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.def b/llvm/include/llvm/TargetParser/ARMTargetParser.def
index 558b6f127de3..c520ab898cb9 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.def
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.def
@@ -340,7 +340,7 @@ ARM_CPU_NAME("cortex-x1c", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
              (ARM::AEK_FP16 | ARM::AEK_DOTPROD))
 ARM_CPU_NAME("neoverse-n1", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
              (ARM::AEK_FP16 | ARM::AEK_DOTPROD))
-ARM_CPU_NAME("neoverse-n2", ARMV8_5A, FK_CRYPTO_NEON_FP_ARMV8, false,
+ARM_CPU_NAME("neoverse-n2", ARMV9A, FK_NEON_FP_ARMV8, false,
              (ARM::AEK_BF16 | ARM::AEK_DOTPROD | ARM::AEK_I8MM | ARM::AEK_RAS |
               ARM::AEK_SB))
 ARM_CPU_NAME("neoverse-v1", ARMV8_4A, FK_CRYPTO_NEON_FP_ARMV8, false,
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index ff256c9a8ccd..c600bcaab2b3 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -1480,9 +1480,9 @@ def ProcessorFeatures {
                                        FeatureFPARMv8, FeatureFullFP16, FeatureNEON,
                                        FeatureRCPC, FeatureSPE, FeatureSSBS,
                                        FeaturePerfMon];
-  list<SubtargetFeature> NeoverseN2 = [HasV8_5aOps, FeatureBF16, FeatureETE,
+  list<SubtargetFeature> NeoverseN2 = [HasV9_0aOps, FeatureBF16, FeatureETE,
                                        FeatureMatMulInt8, FeatureMTE, FeatureSVE2,
-                                       FeatureSVE2BitPerm, FeatureTRBE, FeatureCrypto,
+                                       FeatureSVE2BitPerm, FeatureTRBE,
                                        FeaturePerfMon];
   list<SubtargetFeature> Neoverse512TVB = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist,
                                            FeatureCrypto, FeatureFPARMv8, FeatureFP16FML,
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index 3df428b9ce96..97d1444a553e 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -1662,7 +1662,7 @@ def : ProcNoItin<"neoverse-n1",                         [ARMv82a,
                                                          FeatureCRC,
                                                          FeatureDotProd]>;
 
-def : ProcNoItin<"neoverse-n2",                         [ARMv85a,
+def : ProcNoItin<"neoverse-n2",                         [ARMv9a,
                                                          FeatureBF16,
                                                          FeatureMatMulInt8]>;
 
diff --git a/llvm/test/CodeGen/AArch64/misched-fusion-aes.ll b/llvm/test/CodeGen/AArch64/misched-fusion-aes.ll
index 6ee3cb489285..ee3e808f9f92 100644
--- a/llvm/test/CodeGen/AArch64/misched-fusion-aes.ll
+++ b/llvm/test/CodeGen/AArch64/misched-fusion-aes.ll
@@ -12,7 +12,6 @@
 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-x1  | FileCheck %s
 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-e1 | FileCheck %s
 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-n1 | FileCheck %s
-; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-n2 | FileCheck %s
 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-v1 | FileCheck %s
 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-512tvb | FileCheck %s
 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m3  | FileCheck %s
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index acd0b9b9d65c..687b56cc5aa2 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -416,13 +416,13 @@ INSTANTIATE_TEST_SUITE_P(
                              ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP |
                 ARM::AEK_FP16 | ARM::AEK_RAS | ARM::AEK_DOTPROD,
             "8.2-A"),
-        ARMCPUTestParams<uint64_t>("neoverse-n2", "armv8.5-a", "crypto-neon-fp-armv8",
+        ARMCPUTestParams<uint64_t>("neoverse-n2", "armv9-a", "neon-fp-armv8",
             ARM::AEK_CRC | ARM::AEK_HWDIVTHUMB |
                              ARM::AEK_HWDIVARM | ARM::AEK_MP | ARM::AEK_SEC |
                              ARM::AEK_VIRT | ARM::AEK_DSP | ARM::AEK_BF16 |
                              ARM::AEK_DOTPROD | ARM::AEK_RAS | ARM::AEK_I8MM |
                              ARM::AEK_SB,
-            "8.5-A"),
+            "9-A"),
         ARMCPUTestParams<uint64_t>("neoverse-v1", "armv8.4-a", "crypto-neon-fp-armv8",
             ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
                              ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
@@ -1521,11 +1521,9 @@ INSTANTIATE_TEST_SUITE_P(
                  AArch64::AEK_SSBS})),
             "8.2-A"),
         ARMCPUTestParams<AArch64::ExtensionBitset>(
-            "neoverse-n2", "armv8.5-a", "crypto-neon-fp-armv8",
+            "neoverse-n2", "armv9-a", "crypto-neon-fp-armv8",
             (AArch64::ExtensionBitset(
-                {AArch64::AEK_CRC,         AArch64::AEK_AES,
-                 AArch64::AEK_SHA2,        AArch64::AEK_SHA3,
-                 AArch64::AEK_SM4,         AArch64::AEK_FP,
+                {AArch64::AEK_CRC,         AArch64::AEK_FP,
                  AArch64::AEK_SIMD,        AArch64::AEK_FP16,
                  AArch64::AEK_RAS,         AArch64::AEK_LSE,
                  AArch64::AEK_SVE,         AArch64::AEK_DOTPROD,
-- 
GitLab


From f2afd10776bda7e0dc23176afd1a99d4ccbf967c Mon Sep 17 00:00:00 2001
From: Natalie Chouinard <sudonatalie@google.com>
Date: Mon, 11 Dec 2023 13:58:18 -0500
Subject: [PATCH 152/349] [github] Enable assertions on test workflow (#74849)

---
 .github/workflows/llvm-project-tests.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/llvm-project-tests.yml b/.github/workflows/llvm-project-tests.yml
index 6751bde4a11a..02b1ab75e960 100644
--- a/.github/workflows/llvm-project-tests.yml
+++ b/.github/workflows/llvm-project-tests.yml
@@ -96,7 +96,7 @@ jobs:
           # This should be a no-op for non-mac OSes
           PKG_CONFIG_PATH: /usr/local/Homebrew/Library/Homebrew/os/mac/pkgconfig//12
         with:
-          cmake_args: '-GNinja -DLLVM_ENABLE_PROJECTS="${{ inputs.projects }}" -DCMAKE_BUILD_TYPE=Release -DLLDB_INCLUDE_TESTS=OFF -DCMAKE_C_COMPILER_LAUNCHER=sccache -DCMAKE_CXX_COMPILER_LAUNCHER=sccache ${{ inputs.extra_cmake_args }}'
+          cmake_args: '-GNinja -DLLVM_ENABLE_PROJECTS="${{ inputs.projects }}" -DCMAKE_BUILD_TYPE=Release -DLLVM_ENABLE_ASSERTIONS=ON -DLLDB_INCLUDE_TESTS=OFF -DCMAKE_C_COMPILER_LAUNCHER=sccache -DCMAKE_CXX_COMPILER_LAUNCHER=sccache ${{ inputs.extra_cmake_args }}'
           build_target: '${{ inputs.build_target }}'
 
       - name: Build and Test libclc
-- 
GitLab


From 10f15e2ec419328aa35292b64721e1e1e9e37d70 Mon Sep 17 00:00:00 2001
From: Peter Klausler <35819229+klausler@users.noreply.github.com>
Date: Mon, 11 Dec 2023 11:28:38 -0800
Subject: [PATCH 153/349] [flang][runtime] Crash more informatively in defined
 I/O error case (#74134)

Defined unformatted I/O is not allowed except from/to an external unit.
This restriction prohibits an INQUIRE(IOLENGTH=n) statement from using
derived types with defined unformatted output in its I/O list. The
runtime currently detects this case and crashes with an internal error;
this patch defines a new I/O error enum and causes the program to crash
with a more useful message.
---
 flang/include/flang/Runtime/iostat.h | 1 +
 flang/runtime/descriptor-io.cpp      | 5 ++++-
 flang/runtime/iostat.cpp             | 2 ++
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/flang/include/flang/Runtime/iostat.h b/flang/include/flang/Runtime/iostat.h
index 0456e24f4e38..afce509cf1f5 100644
--- a/flang/include/flang/Runtime/iostat.h
+++ b/flang/include/flang/Runtime/iostat.h
@@ -85,6 +85,7 @@ enum Iostat {
   IostatBadOpOnChildUnit,
   IostatBadNewUnit,
   IostatBadListDirectedInputSeparator,
+  IostatNonExternalDefinedUnformattedIo,
 };
 
 const char *IostatErrorString(int);
diff --git a/flang/runtime/descriptor-io.cpp b/flang/runtime/descriptor-io.cpp
index 563a69e999d5..3093a23a0351 100644
--- a/flang/runtime/descriptor-io.cpp
+++ b/flang/runtime/descriptor-io.cpp
@@ -119,7 +119,10 @@ bool DefinedUnformattedIo(IoStatementState &io, const Descriptor &descriptor,
   // Unformatted I/O must have an external unit (or child thereof).
   IoErrorHandler &handler{io.GetIoErrorHandler()};
   ExternalFileUnit *external{io.GetExternalFileUnit()};
-  RUNTIME_CHECK(handler, external != nullptr);
+  if (!external) { // INQUIRE(IOLENGTH=)
+    handler.SignalError(IostatNonExternalDefinedUnformattedIo);
+    return false;
+  }
   ChildIo &child{external->PushChildIo(io)};
   int unit{external->unitNumber()};
   int ioStat{IostatOk};
diff --git a/flang/runtime/iostat.cpp b/flang/runtime/iostat.cpp
index cc5641693a07..c993b778e9e1 100644
--- a/flang/runtime/iostat.cpp
+++ b/flang/runtime/iostat.cpp
@@ -115,6 +115,8 @@ const char *IostatErrorString(int iostat) {
     return "NEWUNIT= without FILE= or STATUS='SCRATCH'";
   case IostatBadListDirectedInputSeparator:
     return "List-directed input value has trailing unused characters";
+  case IostatNonExternalDefinedUnformattedIo:
+    return "Defined unformatted I/O without an external unit";
   default:
     return nullptr;
   }
-- 
GitLab


From 07ed3258d0b38bdfd60c203c23a59c8ce8def914 Mon Sep 17 00:00:00 2001
From: Walter Erquinigo <a20012251@gmail.com>
Date: Mon, 11 Dec 2023 14:46:25 -0500
Subject: [PATCH 154/349] [lldb-dap] Include [opt] in the frame name only if a
 custom frame format is not specified. (#74861)

Currently there's an include in which `[opt]` might be emitted twice if
the frame format also asks for it. As a trivial fix, we should manually
emit `[opt]` only if a custom frame format is not specified.
---
 lldb/tools/lldb-dap/JSONUtils.cpp | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/lldb/tools/lldb-dap/JSONUtils.cpp b/lldb/tools/lldb-dap/JSONUtils.cpp
index 3a63046d9a88..62d7fa54e75f 100644
--- a/lldb/tools/lldb-dap/JSONUtils.cpp
+++ b/lldb/tools/lldb-dap/JSONUtils.cpp
@@ -804,9 +804,11 @@ llvm::json::Value CreateStackFrame(lldb::SBFrame &frame) {
     llvm::raw_string_ostream os(frame_name);
     os << llvm::format_hex(frame.GetPC(), 18);
   }
-  bool is_optimized = frame.GetFunction().GetIsOptimized();
-  if (is_optimized)
+
+  // We only include `[opt]` if a custom frame format is not specified.
+  if (!g_dap.frame_format && frame.GetFunction().GetIsOptimized())
     frame_name += " [opt]";
+
   EmplaceSafeString(object, "name", frame_name);
 
   auto source = CreateSource(frame);
-- 
GitLab


From 54397f9ac128568838f2ac7bfc8e1f94b3eb264d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Stefan=20Gr=C3=A4nitz?= <stefan.graenitz@gmail.com>
Date: Mon, 11 Dec 2023 20:47:20 +0100
Subject: [PATCH 155/349] [llvm-c] Expose debug support for LLJIT in Orc C-API
 bindings (#73257)

Allow C-API users to debug their JITed code via the GDB JIT Interface.

This is currently supported on ELF and MachO based platforms. On
other systems `LLVMOrcLLJITEnableDebugSupport()` returns an error.

This patch adds a new C-API header `LLJITUtils.h`, which can host
further advanced JIT features in the future. Using the header requires
linking against LLVMOrcDebugging.
---
 llvm/include/llvm-c/LLJIT.h                   |  2 +-
 llvm/include/llvm-c/LLJITUtils.h              | 52 ++++++++++++
 .../Orc/Debugging/CMakeLists.txt              |  1 +
 .../Orc/Debugging/DebuggerSupport.cpp         |  2 +-
 .../Orc/Debugging/LLJITUtilsCBindings.cpp     | 22 +++++
 .../ExecutionEngine/Orc/CMakeLists.txt        |  1 +
 .../ExecutionEngine/Orc/OrcCAPITest.cpp       | 85 +++++++++++++++++++
 7 files changed, 163 insertions(+), 2 deletions(-)
 create mode 100644 llvm/include/llvm-c/LLJITUtils.h
 create mode 100644 llvm/lib/ExecutionEngine/Orc/Debugging/LLJITUtilsCBindings.cpp

diff --git a/llvm/include/llvm-c/LLJIT.h b/llvm/include/llvm-c/LLJIT.h
index a06133aac4fb..a58c3b8bbef7 100644
--- a/llvm/include/llvm-c/LLJIT.h
+++ b/llvm/include/llvm-c/LLJIT.h
@@ -1,4 +1,4 @@
-/*===----------- llvm-c/LLJIT.h - OrcV2 LLJIT C bindings --------*- C++ -*-===*\
+/*===----------- llvm-c/LLJIT.h - OrcV2 LLJIT C bindings ----------*- C -*-===*\
 |*                                                                            *|
 |* Part of the LLVM Project, under the Apache License v2.0 with LLVM          *|
 |* Exceptions.                                                                *|
diff --git a/llvm/include/llvm-c/LLJITUtils.h b/llvm/include/llvm-c/LLJITUtils.h
new file mode 100644
index 000000000000..940097432b78
--- /dev/null
+++ b/llvm/include/llvm-c/LLJITUtils.h
@@ -0,0 +1,52 @@
+/*===------- llvm-c/LLJITUtils.h - Advanced LLJIT features --------*- C -*-===*\
+|*                                                                            *|
+|* Part of the LLVM Project, under the Apache License v2.0 with LLVM          *|
+|* Exceptions.                                                                *|
+|* See https://llvm.org/LICENSE.txt for license information.                  *|
+|* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception                    *|
+|*                                                                            *|
+|*===----------------------------------------------------------------------===*|
+|*                                                                            *|
+|* This header declares the C interface for extra utilities to be used with   *|
+|* the LLJIT class from the llvm-c/LLJIT.h header. It requires to following   *|
+|* link libraries in addition to libLLVMOrcJIT.a:                             *|
+|*  - libLLVMOrcDebugging.a                                                   *|
+|*                                                                            *|
+|* Many exotic languages can interoperate with C code but have a harder time  *|
+|* with C++ due to name mangling. So in addition to C, this interface enables *|
+|* tools written in such languages.                                           *|
+|*                                                                            *|
+|* Note: This interface is experimental. It is *NOT* stable, and may be       *|
+|*       changed without warning. Only C API usage documentation is           *|
+|*       provided. See the C++ documentation for all higher level ORC API     *|
+|*       details.                                                             *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+#ifndef LLVM_C_LLJITUTILS_H
+#define LLVM_C_LLJITUTILS_H
+
+#include "llvm-c/LLJIT.h"
+
+LLVM_C_EXTERN_C_BEGIN
+
+/**
+ * @defgroup LLVMCExecutionEngineLLJITUtils LLJIT Utilities
+ * @ingroup LLVMCExecutionEngineLLJIT
+ *
+ * @{
+ */
+
+/**
+ * Install the plugin that submits debug objects to the executor. Executors must
+ * expose the llvm_orc_registerJITLoaderGDBWrapper symbol.
+ */
+LLVMErrorRef LLVMOrcLLJITEnableDebugSupport(LLVMOrcLLJITRef J);
+
+/**
+ * @}
+ */
+
+LLVM_C_EXTERN_C_END
+
+#endif /* LLVM_C_LLJITUTILS_H */
diff --git a/llvm/lib/ExecutionEngine/Orc/Debugging/CMakeLists.txt b/llvm/lib/ExecutionEngine/Orc/Debugging/CMakeLists.txt
index 23b471481618..5bf23a7ec0bc 100644
--- a/llvm/lib/ExecutionEngine/Orc/Debugging/CMakeLists.txt
+++ b/llvm/lib/ExecutionEngine/Orc/Debugging/CMakeLists.txt
@@ -6,6 +6,7 @@ add_llvm_component_library(LLVMOrcDebugging
   DebugInfoSupport.cpp
   DebuggerSupport.cpp
   DebuggerSupportPlugin.cpp
+  LLJITUtilsCBindings.cpp
   PerfSupportPlugin.cpp
 
   ADDITIONAL_HEADER_DIRS
diff --git a/llvm/lib/ExecutionEngine/Orc/Debugging/DebuggerSupport.cpp b/llvm/lib/ExecutionEngine/Orc/Debugging/DebuggerSupport.cpp
index 9ba6dd90f50d..1668473c0eb4 100644
--- a/llvm/lib/ExecutionEngine/Orc/Debugging/DebuggerSupport.cpp
+++ b/llvm/lib/ExecutionEngine/Orc/Debugging/DebuggerSupport.cpp
@@ -39,7 +39,7 @@ Error enableDebuggerSupport(LLJIT &J) {
     if (!Registrar)
       return Registrar.takeError();
     ObjLinkingLayer->addPlugin(std::make_unique<DebugObjectManagerPlugin>(
-        ES, std::move(*Registrar), true, true));
+        ES, std::move(*Registrar), false, true));
     return Error::success();
   }
   case Triple::MachO: {
diff --git a/llvm/lib/ExecutionEngine/Orc/Debugging/LLJITUtilsCBindings.cpp b/llvm/lib/ExecutionEngine/Orc/Debugging/LLJITUtilsCBindings.cpp
new file mode 100644
index 000000000000..2df5aef733fb
--- /dev/null
+++ b/llvm/lib/ExecutionEngine/Orc/Debugging/LLJITUtilsCBindings.cpp
@@ -0,0 +1,22 @@
+//===--------- LLJITUtilsCBindings.cpp - Advanced LLJIT features ----------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm-c/LLJIT.h"
+#include "llvm-c/LLJITUtils.h"
+
+#include "llvm/ExecutionEngine/Orc/Debugging/DebuggerSupport.h"
+#include "llvm/ExecutionEngine/Orc/LLJIT.h"
+
+using namespace llvm;
+using namespace llvm::orc;
+
+DEFINE_SIMPLE_CONVERSION_FUNCTIONS(LLJIT, LLVMOrcLLJITRef)
+
+LLVMErrorRef LLVMOrcLLJITEnableDebugSupport(LLVMOrcLLJITRef J) {
+  return wrap(llvm::orc::enableDebuggerSupport(*unwrap(J)));
+}
diff --git a/llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt b/llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt
index 37768e91fd44..f102ba59e375 100644
--- a/llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt
+++ b/llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt
@@ -5,6 +5,7 @@ set(LLVM_LINK_COMPONENTS
   IRReader
   JITLink
   Object
+  OrcDebugging
   OrcJIT
   OrcShared
   OrcTargetProcess
diff --git a/llvm/unittests/ExecutionEngine/Orc/OrcCAPITest.cpp b/llvm/unittests/ExecutionEngine/Orc/OrcCAPITest.cpp
index cbdd4af47e1d..65d2f57234d0 100644
--- a/llvm/unittests/ExecutionEngine/Orc/OrcCAPITest.cpp
+++ b/llvm/unittests/ExecutionEngine/Orc/OrcCAPITest.cpp
@@ -9,10 +9,12 @@
 #include "llvm-c/Core.h"
 #include "llvm-c/Error.h"
 #include "llvm-c/LLJIT.h"
+#include "llvm-c/LLJITUtils.h"
 #include "llvm-c/Orc.h"
 #include "gtest/gtest.h"
 
 #include "llvm/ExecutionEngine/Orc/CompileUtils.h"
+#include "llvm/ExecutionEngine/Orc/TargetProcess/JITLoaderGDB.h"
 #include "llvm/IR/LLVMContext.h"
 #include "llvm/IR/Module.h"
 #include "llvm/IRReader/IRReader.h"
@@ -211,6 +213,20 @@ constexpr StringRef SumExample =
     }
   )";
 
+constexpr StringRef SumDebugExample =
+    R"(
+    define i32 @sum(i32 %x, i32 %y) {
+    entry:
+      %r = add nsw i32 %x, %y
+      ret i32 %r
+    }
+    !llvm.module.flags = !{!0}
+    !llvm.dbg.cu = !{!1}
+    !0 = !{i32 2, !"Debug Info Version", i32 3}
+    !1 = distinct !DICompileUnit(language: DW_LANG_C99, file: !2, emissionKind: FullDebug)
+    !2 = !DIFile(filename: "sum.c", directory: "/tmp")
+  )";
+
 } // end anonymous namespace.
 
 // Consumes the given error ref and returns the string error message.
@@ -494,6 +510,75 @@ TEST_F(OrcCAPITestBase, AddObjectBuffer) {
   ASSERT_TRUE(!!SumAddr);
 }
 
+// This must be kept in sync with gdb/gdb/jit.h .
+extern "C" {
+
+typedef enum {
+  JIT_NOACTION = 0,
+  JIT_REGISTER_FN,
+  JIT_UNREGISTER_FN
+} jit_actions_t;
+
+struct jit_code_entry {
+  struct jit_code_entry *next_entry;
+  struct jit_code_entry *prev_entry;
+  const char *symfile_addr;
+  uint64_t symfile_size;
+};
+
+struct jit_descriptor {
+  uint32_t version;
+  // This should be jit_actions_t, but we want to be specific about the
+  // bit-width.
+  uint32_t action_flag;
+  struct jit_code_entry *relevant_entry;
+  struct jit_code_entry *first_entry;
+};
+
+// We put information about the JITed function in this global, which the
+// debugger reads.  Make sure to specify the version statically, because the
+// debugger checks the version before we can set it during runtime.
+extern struct jit_descriptor __jit_debug_descriptor;
+
+static void *findLastDebugDescriptorEntryPtr() {
+  struct jit_code_entry *Last = __jit_debug_descriptor.first_entry;
+  while (Last && Last->next_entry)
+    Last = Last->next_entry;
+  return Last;
+}
+}
+
+#if defined(_AIX) or not(defined(__ELF__) or defined(__MACH__))
+TEST_F(OrcCAPITestBase, DISABLED_EnableDebugSupport) {
+#else
+static LLVM_ATTRIBUTE_USED void linkComponents() {
+  errs() << "Linking in runtime functions\n"
+         << (void *)&llvm_orc_registerJITLoaderGDBWrapper << '\n'
+         << (void *)&llvm_orc_registerJITLoaderGDBAllocAction << '\n';
+}
+TEST_F(OrcCAPITestBase, EnableDebugSupport) {
+#endif
+  if (LLVMErrorRef E = LLVMOrcLLJITEnableDebugSupport(Jit))
+    FAIL() << "Error testing LLJIT debug support (triple = " << TargetTriple
+           << "): " << toString(E);
+
+  void *Before = findLastDebugDescriptorEntryPtr();
+  LLVMMemoryBufferRef ObjBuffer = createTestObject(SumDebugExample, "sum.ll");
+  LLVMOrcObjectLayerRef ObjLayer = LLVMOrcLLJITGetObjLinkingLayer(Jit);
+  if (LLVMErrorRef E =
+          LLVMOrcObjectLayerAddObjectFile(ObjLayer, MainDylib, ObjBuffer))
+    FAIL() << "Failed to add object file to ObjLinkingLayer (triple = "
+           << TargetTriple << "): " << toString(E);
+
+  LLVMOrcJITTargetAddress SumAddr;
+  if (LLVMErrorRef E = LLVMOrcLLJITLookup(Jit, &SumAddr, "sum"))
+    FAIL() << "Symbol \"sum\" was not added into JIT (triple = " << TargetTriple
+           << "): " << toString(E);
+
+  void *After = findLastDebugDescriptorEntryPtr();
+  ASSERT_NE(Before, After);
+}
+
 #if defined(_AIX)
 TEST_F(OrcCAPITestBase, DISABLED_ExecutionTest) {
 #else
-- 
GitLab


From a6e77fdd741ff8d2fb2e61b395c11c20ec03f172 Mon Sep 17 00:00:00 2001
From: Peter Klausler <35819229+klausler@users.noreply.github.com>
Date: Mon, 11 Dec 2023 11:55:44 -0800
Subject: [PATCH 156/349] [flang][runtime] Make defined formatted I/O process
 format elementally (#74150)

The present implementation of defined formatted I/O is incorrect for
arrays in the data item list; it assumes that a DT defined format
descriptor (or list-directed/namelist instance) applies to all of the
elements in the array. The loop over the elements in the array is within
the DefinedFormattedIo() template function that handles defined
formatted I/O, not around its calls. This causes only one format list
edit descriptor to be used for the whole array, which is of course
wrong.

Invert this arrangment by performing the per-element looping in at the
top level in FormattedDerivedTypeIo() instead.

Defined unformatted I/O remains as it was.
---
 flang/runtime/descriptor-io.cpp | 26 +++------
 flang/runtime/descriptor-io.h   | 93 ++++++++++++++++++++++++---------
 2 files changed, 74 insertions(+), 45 deletions(-)

diff --git a/flang/runtime/descriptor-io.cpp b/flang/runtime/descriptor-io.cpp
index 3093a23a0351..6041104773cc 100644
--- a/flang/runtime/descriptor-io.cpp
+++ b/flang/runtime/descriptor-io.cpp
@@ -14,7 +14,8 @@ namespace Fortran::runtime::io::descr {
 // Defined formatted I/O (maybe)
 std::optional<bool> DefinedFormattedIo(IoStatementState &io,
     const Descriptor &descriptor, const typeInfo::DerivedType &derived,
-    const typeInfo::SpecialBinding &special) {
+    const typeInfo::SpecialBinding &special,
+    const SubscriptValue subscripts[]) {
   std::optional<DataEdit> peek{io.GetNextDataEdit(0 /*to peek at it*/)};
   if (peek &&
       (peek->descriptor == DataEdit::DefinedDerivedType ||
@@ -61,9 +62,6 @@ std::optional<bool> DefinedFormattedIo(IoStatementState &io,
       // I/O subroutine reads counts towards READ(SIZE=).
       startPos = io.InquirePos();
     }
-    std::size_t numElements{descriptor.Elements()};
-    SubscriptValue subscripts[maxRank];
-    descriptor.GetLowerBounds(subscripts);
     if (special.IsArgDescriptor(0)) {
       // "dtv" argument is "class(t)", pass a descriptor
       auto *p{special.GetProc<void (*)(const Descriptor &, int &, char *,
@@ -72,25 +70,15 @@ std::optional<bool> DefinedFormattedIo(IoStatementState &io,
       Descriptor &elementDesc{elementStatDesc.descriptor()};
       elementDesc.Establish(
           derived, nullptr, 0, nullptr, CFI_attribute_pointer);
-      for (; numElements-- > 0; descriptor.IncrementSubscripts(subscripts)) {
-        elementDesc.set_base_addr(descriptor.Element<char>(subscripts));
-        p(elementDesc, unit, ioType, vListDesc, ioStat, ioMsg, ioTypeLen,
-            sizeof ioMsg);
-        if (ioStat != IostatOk) {
-          break;
-        }
-      }
+      elementDesc.set_base_addr(descriptor.Element<char>(subscripts));
+      p(elementDesc, unit, ioType, vListDesc, ioStat, ioMsg, ioTypeLen,
+          sizeof ioMsg);
     } else {
       // "dtv" argument is "type(t)", pass a raw pointer
       auto *p{special.GetProc<void (*)(const void *, int &, char *,
           const Descriptor &, int &, char *, std::size_t, std::size_t)>()};
-      for (; numElements-- > 0; descriptor.IncrementSubscripts(subscripts)) {
-        p(descriptor.Element<char>(subscripts), unit, ioType, vListDesc, ioStat,
-            ioMsg, ioTypeLen, sizeof ioMsg);
-        if (ioStat != IostatOk) {
-          break;
-        }
-      }
+      p(descriptor.Element<char>(subscripts), unit, ioType, vListDesc, ioStat,
+          ioMsg, ioTypeLen, sizeof ioMsg);
     }
     handler.Forward(ioStat, ioMsg, sizeof ioMsg);
     external->PopChildIo(child);
diff --git a/flang/runtime/descriptor-io.h b/flang/runtime/descriptor-io.h
index 2b5bf8248aca..394578796faa 100644
--- a/flang/runtime/descriptor-io.h
+++ b/flang/runtime/descriptor-io.h
@@ -268,7 +268,33 @@ static bool DefaultComponentIO(IoStatementState &io,
 }
 
 template <Direction DIR>
-static bool DefaultComponentwiseIO(IoStatementState &io,
+static bool DefaultComponentwiseFormattedIO(IoStatementState &io,
+    const Descriptor &descriptor, const typeInfo::DerivedType &type,
+    const NonTbpDefinedIoTable *table, const SubscriptValue subscripts[]) {
+  IoErrorHandler &handler{io.GetIoErrorHandler()};
+  const Descriptor &compArray{type.component()};
+  RUNTIME_CHECK(handler, compArray.rank() == 1);
+  std::size_t numComponents{compArray.Elements()};
+  SubscriptValue at[maxRank];
+  compArray.GetLowerBounds(at);
+  for (std::size_t k{0}; k < numComponents;
+       ++k, compArray.IncrementSubscripts(at)) {
+    const typeInfo::Component &component{
+        *compArray.Element<typeInfo::Component>(at)};
+    if (!DefaultComponentIO<DIR>(
+            io, component, descriptor, subscripts, handler, table)) {
+      // Return true for NAMELIST input if any component appeared.
+      auto *listInput{
+          io.get_if<ListDirectedStatementState<Direction::Input>>()};
+      return DIR == Direction::Input && k > 0 && listInput &&
+          listInput->inNamelistSequence();
+    }
+  }
+  return true;
+}
+
+template <Direction DIR>
+static bool DefaultComponentwiseUnformattedIO(IoStatementState &io,
     const Descriptor &descriptor, const typeInfo::DerivedType &type,
     const NonTbpDefinedIoTable *table) {
   IoErrorHandler &handler{io.GetIoErrorHandler()};
@@ -288,11 +314,7 @@ static bool DefaultComponentwiseIO(IoStatementState &io,
           *compArray.Element<typeInfo::Component>(at)};
       if (!DefaultComponentIO<DIR>(
               io, component, descriptor, subscripts, handler, table)) {
-        // Truncated nonempty namelist input sequence?
-        auto *listInput{
-            io.get_if<ListDirectedStatementState<Direction::Input>>()};
-        return DIR == Direction::Input && (j > 0 || k > 0) && listInput &&
-            listInput->inNamelistSequence();
+        return false;
       }
     }
   }
@@ -300,7 +322,8 @@ static bool DefaultComponentwiseIO(IoStatementState &io,
 }
 
 std::optional<bool> DefinedFormattedIo(IoStatementState &, const Descriptor &,
-    const typeInfo::DerivedType &, const typeInfo::SpecialBinding &);
+    const typeInfo::DerivedType &, const typeInfo::SpecialBinding &,
+    const SubscriptValue[]);
 
 template <Direction DIR>
 static bool FormattedDerivedTypeIO(IoStatementState &io,
@@ -311,37 +334,54 @@ static bool FormattedDerivedTypeIO(IoStatementState &io,
   RUNTIME_CHECK(handler, addendum != nullptr);
   const typeInfo::DerivedType *type{addendum->derivedType()};
   RUNTIME_CHECK(handler, type != nullptr);
+  std::optional<typeInfo::SpecialBinding> nonTbpSpecial;
+  const typeInfo::SpecialBinding *special{nullptr};
   if (table) {
     if (const auto *definedIo{table->Find(*type,
             DIR == Direction::Input ? common::DefinedIo::ReadFormatted
                                     : common::DefinedIo::WriteFormatted)}) {
       if (definedIo->subroutine) {
-        typeInfo::SpecialBinding special{DIR == Direction::Input
+        nonTbpSpecial.emplace(DIR == Direction::Input
                 ? typeInfo::SpecialBinding::Which::ReadFormatted
                 : typeInfo::SpecialBinding::Which::WriteFormatted,
             definedIo->subroutine, definedIo->isDtvArgPolymorphic, false,
-            false};
-        if (std::optional<bool> wasDefined{
-                DefinedFormattedIo(io, descriptor, *type, special)}) {
-          return *wasDefined;
-        }
-      } else {
-        return DefaultComponentwiseIO<DIR>(io, descriptor, *type, table);
+            false);
+        special = &*nonTbpSpecial;
       }
     }
   }
-  if (const typeInfo::SpecialBinding *
-      special{type->FindSpecialBinding(DIR == Direction::Input
-              ? typeInfo::SpecialBinding::Which::ReadFormatted
-              : typeInfo::SpecialBinding::Which::WriteFormatted)}) {
-    if (!table || !table->ignoreNonTbpEntries || special->isTypeBound()) {
-      if (std::optional<bool> wasDefined{
-              DefinedFormattedIo(io, descriptor, *type, *special)}) {
-        return *wasDefined; // defined I/O was applied
+  if (!special) {
+    if (const typeInfo::SpecialBinding *
+        binding{type->FindSpecialBinding(DIR == Direction::Input
+                ? typeInfo::SpecialBinding::Which::ReadFormatted
+                : typeInfo::SpecialBinding::Which::WriteFormatted)}) {
+      if (!table || !table->ignoreNonTbpEntries || binding->isTypeBound()) {
+        special = binding;
       }
     }
   }
-  return DefaultComponentwiseIO<DIR>(io, descriptor, *type, table);
+  SubscriptValue subscripts[maxRank];
+  descriptor.GetLowerBounds(subscripts);
+  std::size_t numElements{descriptor.Elements()};
+  for (std::size_t j{0}; j < numElements;
+       ++j, descriptor.IncrementSubscripts(subscripts)) {
+    std::optional<bool> result;
+    if (special) {
+      result = DefinedFormattedIo(io, descriptor, *type, *special, subscripts);
+    }
+    if (!result) {
+      result = DefaultComponentwiseFormattedIO<DIR>(
+          io, descriptor, *type, table, subscripts);
+    }
+    if (!result.value()) {
+      // Return true for NAMELIST input if we got anything.
+      auto *listInput{
+          io.get_if<ListDirectedStatementState<Direction::Input>>()};
+      return DIR == Direction::Input && j > 0 && listInput &&
+          listInput->inNamelistSequence();
+    }
+  }
+  return true;
 }
 
 bool DefinedUnformattedIo(IoStatementState &, const Descriptor &,
@@ -371,7 +411,8 @@ static bool UnformattedDescriptorIO(IoStatementState &io,
             return *wasDefined;
           }
         } else {
-          return DefaultComponentwiseIO<DIR>(io, descriptor, *type, table);
+          return DefaultComponentwiseUnformattedIO<DIR>(
+              io, descriptor, *type, table);
         }
       }
     }
@@ -388,7 +429,7 @@ static bool UnformattedDescriptorIO(IoStatementState &io,
     // TODO: If no component at any level has defined READ or WRITE
     // (as appropriate), the elements are contiguous, and no byte swapping
     // is active, do a block transfer via the code below.
-    return DefaultComponentwiseIO<DIR>(io, descriptor, *type, table);
+    return DefaultComponentwiseUnformattedIO<DIR>(io, descriptor, *type, table);
   } else {
     // intrinsic type unformatted I/O
     auto *externalUnf{io.get_if<ExternalUnformattedIoStatementState<DIR>>()};
-- 
GitLab


From 1bbf7225c1f0dde8c59c8acfc0b54999391df184 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@sifive.com>
Date: Mon, 11 Dec 2023 11:54:42 -0800
Subject: [PATCH 157/349] [RISCV] Use getBuiltinVectorTypeInfo to simplify
 code. NFC

---
 clang/lib/Sema/SemaChecking.cpp | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 5c9734618447..08c03d75ec3c 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5082,12 +5082,10 @@ static bool CheckInvalidVLENandLMUL(const TargetInfo &TI, CallExpr *TheCall,
   assert((EGW == 128 || EGW == 256) && "EGW can only be 128 or 256 bits");
 
   // LMUL * VLEN >= EGW
-  unsigned ElemSize = Type->isRVVType(32, false) ? 32 : 64;
-  unsigned MinElemCount = Type->isRVVType(1)   ? 1
-                          : Type->isRVVType(2) ? 2
-                          : Type->isRVVType(4) ? 4
-                          : Type->isRVVType(8) ? 8
-                                               : 16;
+  ASTContext::BuiltinVectorTypeInfo Info =
+      S.Context.getBuiltinVectorTypeInfo(Type->castAs<BuiltinType>());
+  unsigned ElemSize = S.Context.getTypeSize(Info.ElementType);
+  unsigned MinElemCount = Info.EC.getKnownMinValue();
 
   unsigned EGS = EGW / ElemSize;
   // If EGS is less than or equal to the minimum number of elements, then the
-- 
GitLab


From f58f089164ade240e1bcb60b7c3cead840a33e1c Mon Sep 17 00:00:00 2001
From: Peter Klausler <35819229+klausler@users.noreply.github.com>
Date: Mon, 11 Dec 2023 12:03:59 -0800
Subject: [PATCH 158/349] [flang] Correct definability checking for INTENT(IN)
 pointers (#74158)

An INTENT(IN) attribute on a pointer dummy argument prevents
modification of the pointer itself only, not modification of any
component of its target. Fix this case without breaking definability
checking for pointer components of non-pointer INTENT(IN) dummy
arguments.
---
 flang/lib/Semantics/definable.cpp    | 23 +++++++++++++++++------
 flang/test/Semantics/definable01.f90 | 15 +++++++++++++++
 2 files changed, 32 insertions(+), 6 deletions(-)

diff --git a/flang/lib/Semantics/definable.cpp b/flang/lib/Semantics/definable.cpp
index d5ffcabc7233..b73290109248 100644
--- a/flang/lib/Semantics/definable.cpp
+++ b/flang/lib/Semantics/definable.cpp
@@ -89,7 +89,8 @@ static const Symbol &GetRelevantSymbol(const evaluate::DataRef &dataRef,
 
 // Check the leftmost (or only) symbol from a data-ref or expression.
 static std::optional<parser::Message> WhyNotDefinableBase(parser::CharBlock at,
-    const Scope &scope, DefinabilityFlags flags, const Symbol &original) {
+    const Scope &scope, DefinabilityFlags flags, const Symbol &original,
+    bool isWholeSymbol) {
   const Symbol &ultimate{original.GetUltimate()};
   bool isPointerDefinition{flags.test(DefinabilityFlag::PointerDefinition)};
   bool acceptAllocatable{flags.test(DefinabilityFlag::AcceptAllocatable)};
@@ -104,7 +105,8 @@ static std::optional<parser::Message> WhyNotDefinableBase(parser::CharBlock at,
     } else if (auto dataRef{evaluate::ExtractDataRef(
                    *association->expr(), true, true)}) {
       return WhyNotDefinableBase(at, scope, flags,
-          GetRelevantSymbol(*dataRef, isPointerDefinition, acceptAllocatable));
+          GetRelevantSymbol(*dataRef, isPointerDefinition, acceptAllocatable),
+          isWholeSymbol);
     }
   }
   if (isTargetDefinition) {
@@ -112,7 +114,8 @@ static std::optional<parser::Message> WhyNotDefinableBase(parser::CharBlock at,
     return BlameSymbol(at, "'%s' is not a variable"_en_US, original);
   } else if (IsProtected(ultimate) && IsUseAssociated(original, scope)) {
     return BlameSymbol(at, "'%s' is protected in this scope"_en_US, original);
-  } else if (IsIntentIn(ultimate)) {
+  } else if (IsIntentIn(ultimate) &&
+      (!IsPointer(ultimate) || (isWholeSymbol && isPointerDefinition))) {
     return BlameSymbol(
         at, "'%s' is an INTENT(IN) dummy argument"_en_US, original);
   }
@@ -165,6 +168,12 @@ static std::optional<parser::Message> WhyNotDefinableBase(parser::CharBlock at,
 static std::optional<parser::Message> WhyNotDefinableLast(parser::CharBlock at,
     const Scope &scope, DefinabilityFlags flags, const Symbol &original) {
   const Symbol &ultimate{original.GetUltimate()};
+  if (const auto *association{ultimate.detailsIf<AssocEntityDetails>()}) {
+    if (auto dataRef{
+            evaluate::ExtractDataRef(*association->expr(), true, true)}) {
+      return WhyNotDefinableLast(at, scope, flags, dataRef->GetLastSymbol());
+    }
+  }
   if (flags.test(DefinabilityFlag::PointerDefinition)) {
     if (flags.test(DefinabilityFlag::AcceptAllocatable)) {
       if (!IsAllocatableOrObjectPointer(&ultimate)) {
@@ -216,7 +225,8 @@ static std::optional<parser::Message> WhyNotDefinable(parser::CharBlock at,
   const Symbol &base{GetRelevantSymbol(dataRef,
       flags.test(DefinabilityFlag::PointerDefinition),
       flags.test(DefinabilityFlag::AcceptAllocatable))};
-  if (auto whyNot{WhyNotDefinableBase(at, scope, flags, base)}) {
+  if (auto whyNot{WhyNotDefinableBase(at, scope, flags, base,
+          std::holds_alternative<evaluate::SymbolRef>(dataRef.u))}) {
     return whyNot;
   } else {
     return WhyNotDefinableLast(at, scope, flags, dataRef.GetLastSymbol());
@@ -231,12 +241,13 @@ static std::optional<parser::Message> WhyNotDefinable(parser::CharBlock at,
   const Symbol &base{GetRelevantSymbol(dataRef, false, false)};
   DefinabilityFlags baseFlags{flags};
   baseFlags.reset(DefinabilityFlag::PointerDefinition);
-  return WhyNotDefinableBase(at, scope, baseFlags, base);
+  return WhyNotDefinableBase(at, scope, baseFlags, base,
+      std::holds_alternative<evaluate::SymbolRef>(dataRef.u));
 }
 
 std::optional<parser::Message> WhyNotDefinable(parser::CharBlock at,
     const Scope &scope, DefinabilityFlags flags, const Symbol &original) {
-  if (auto base{WhyNotDefinableBase(at, scope, flags, original)}) {
+  if (auto base{WhyNotDefinableBase(at, scope, flags, original, true)}) {
     return base;
   }
   return WhyNotDefinableLast(at, scope, flags, original);
diff --git a/flang/test/Semantics/definable01.f90 b/flang/test/Semantics/definable01.f90
index fff493fe7a41..c0f10668fb48 100644
--- a/flang/test/Semantics/definable01.f90
+++ b/flang/test/Semantics/definable01.f90
@@ -82,4 +82,19 @@ module m
   subroutine test3b(pp)
     procedure(sin), pointer, intent(in out) :: pp
   end subroutine
+  subroutine test4(p)
+    type(ptype), pointer, intent(in) :: p
+    p%x = 1.
+    p%ptr = 1. ! ok
+    nullify(p%ptr) ! ok
+    !CHECK: error: 'p' may not appear in NULLIFY
+    !CHECK: because: 'p' is an INTENT(IN) dummy argument
+    nullify(p)
+  end
+  subroutine test5(np)
+    type(ptype), intent(in) :: np
+    !CHECK: error: 'ptr' may not appear in NULLIFY
+    !CHECK: because: 'np' is an INTENT(IN) dummy argument
+    nullify(np%ptr)
+  end
 end module
-- 
GitLab


From 9458bae553c82438e1817b4a5b1d003a8de064c3 Mon Sep 17 00:00:00 2001
From: Benjamin Kramer <benny.kra@googlemail.com>
Date: Fri, 8 Dec 2023 12:16:53 +0100
Subject: [PATCH 159/349] [NVPTX] Custom lower integer<->bf16 conversions for
 sm_80 (#74827)

sm_80 only has f32->bf16 conversions, the remaining integer conversions
arrived with sm_90. Use a two-step conversion for sm_80.

There doesn't seem to be a way to express this promotion directly within
the legalization framework, so fallback on Custom lowering.
---
 llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp  |  48 +++++++++
 llvm/lib/Target/NVPTX/NVPTXISelLowering.h    |   3 +
 llvm/test/CodeGen/NVPTX/bf16-instructions.ll | 103 +++++++++++++++++++
 3 files changed, 154 insertions(+)

diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index 61285c6ba98d..f5d8abaf847a 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -766,6 +766,17 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
       AddPromotedToType(Op, MVT::bf16, MVT::f32);
   }
 
+  // sm_80 only has conversions between f32 and bf16. Custom lower all other
+  // bf16 conversions.
+  if (STI.hasBF16Math() &&
+      (STI.getSmVersion() < 90 || STI.getPTXVersion() < 78)) {
+    for (MVT VT : {MVT::i1, MVT::i16, MVT::i32, MVT::i64}) {
+      setOperationAction(
+          {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT},
+          VT, Custom);
+    }
+  }
+
   setOperationAction(ISD::FROUND, MVT::f16, Promote);
   setOperationAction(ISD::FROUND, MVT::v2f16, Expand);
   setOperationAction(ISD::FROUND, MVT::v2bf16, Expand);
@@ -2580,6 +2591,37 @@ SDValue NVPTXTargetLowering::LowerFROUND64(SDValue Op,
   return DAG.getNode(ISD::SELECT, SL, VT, IsLarge, A, RoundedA);
 }
 
+SDValue NVPTXTargetLowering::LowerINT_TO_FP(SDValue Op,
+                                            SelectionDAG &DAG) const {
+  assert(STI.getSmVersion() < 90 || STI.getPTXVersion() < 78);
+
+  if (Op.getValueType() == MVT::bf16) {
+    SDLoc Loc(Op);
+    return DAG.getNode(
+        ISD::FP_ROUND, Loc, MVT::bf16,
+        DAG.getNode(Op.getOpcode(), Loc, MVT::f32, Op.getOperand(0)),
+        DAG.getIntPtrConstant(0, Loc));
+  }
+
+  // Everything else is considered legal.
+  return Op;
+}
+
+SDValue NVPTXTargetLowering::LowerFP_TO_INT(SDValue Op,
+                                            SelectionDAG &DAG) const {
+  assert(STI.getSmVersion() < 90 || STI.getPTXVersion() < 78);
+
+  if (Op.getOperand(0).getValueType() == MVT::bf16) {
+    SDLoc Loc(Op);
+    return DAG.getNode(
+        Op.getOpcode(), Loc, Op.getValueType(),
+        DAG.getNode(ISD::FP_EXTEND, Loc, MVT::f32, Op.getOperand(0)));
+  }
+
+  // Everything else is considered legal.
+  return Op;
+}
+
 static SDValue LowerVectorArith(SDValue Op, SelectionDAG &DAG) {
   SDLoc DL(Op);
   if (Op.getValueType() != MVT::v2i16)
@@ -2636,6 +2678,12 @@ NVPTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
     return LowerSelect(Op, DAG);
   case ISD::FROUND:
     return LowerFROUND(Op, DAG);
+  case ISD::SINT_TO_FP:
+  case ISD::UINT_TO_FP:
+    return LowerINT_TO_FP(Op, DAG);
+  case ISD::FP_TO_SINT:
+  case ISD::FP_TO_UINT:
+    return LowerFP_TO_INT(Op, DAG);
   case ISD::VAARG:
     return LowerVAARG(Op, DAG);
   case ISD::VASTART:
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.h b/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
index 54e34dedc667..cd6bcb048c5f 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
@@ -607,6 +607,9 @@ private:
   SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
 
+  SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
+  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
+
   SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerLOADi1(SDValue Op, SelectionDAG &DAG) const;
 
diff --git a/llvm/test/CodeGen/NVPTX/bf16-instructions.ll b/llvm/test/CodeGen/NVPTX/bf16-instructions.ll
index 5a6ab2926b40..a9faa130d637 100644
--- a/llvm/test/CodeGen/NVPTX/bf16-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/bf16-instructions.ll
@@ -227,3 +227,106 @@ define <8 x float> @test_extload_bf16x8(ptr addrspace(3) noundef %arg) #0 {
   %res = fpext <8 x bfloat> %load to <8 x float>
   ret <8 x float> %res
 }
+
+; CHECK-LABEL: test_fptosi_i16(
+; CHECK:      ld.param.b16     [[A:%rs[0-9]+]], [test_fptosi_i16_param_0];
+; SM80:       cvt.f32.bf16     [[B:%f[0-9]+]], [[A]];
+; SM80:       cvt.rzi.s16.f32  [[C:%rs[0-9]+]], [[B]];
+; SM80:       cvt.u32.u16      [[R:%r[0-9]+]], [[C]];
+; SM90:       cvt.rzi.s16.bf16 [[B:%rs[0-9]+]], [[A]];
+; SM90:       cvt.u32.u16      [[R:%r[0-9]+]], [[B]];
+; CHECK:      st.param.b32     [func_retval0+0], [[R]];
+; CHECK:      ret;
+define i16 @test_fptosi_i16(bfloat %a) {
+  %r = fptosi bfloat %a to i16
+  ret i16 %r
+}
+
+; CHECK-LABEL: test_fptoui_i16(
+; CHECK:      ld.param.b16     [[A:%rs[0-9]+]], [test_fptoui_i16_param_0];
+; SM80:       cvt.f32.bf16     [[B:%f[0-9]+]], [[A]];
+; SM80:       cvt.rzi.u16.f32  [[C:%rs[0-9]+]], [[B]];
+; SM80:       cvt.u32.u16      [[R:%r[0-9]+]], [[C]];
+; SM90:       cvt.rzi.u16.bf16 [[B:%rs[0-9]+]], [[A]];
+; SM90:       cvt.u32.u16      [[R:%r[0-9]+]], [[B]];
+; CHECK:      st.param.b32     [func_retval0+0], [[R]];
+; CHECK:      ret;
+define i16 @test_fptoui_i16(bfloat %a) {
+  %r = fptoui bfloat %a to i16
+  ret i16 %r
+}
+
+; CHECK-LABEL: test_sitofp_i16(
+; CHECK:      ld.param.u16    [[A:%rs[0-9]+]], [test_sitofp_i16_param_0];
+; SM80:       cvt.rn.f32.s16  [[B:%f[0-9]+]], [[A]];
+; SM80:       cvt.rn.bf16.f32 [[R:%rs[0-9]+]], [[B]];
+; SM90:       cvt.rn.bf16.s16 [[R:%rs[0-9]+]], [[A]];
+; CHECK:      st.param.b16    [func_retval0+0], [[R]];
+; CHECK:      ret;
+define bfloat @test_sitofp_i16(i16 %a) {
+  %r = sitofp i16 %a to bfloat
+  ret bfloat %r
+}
+
+; CHECK-LABEL: test_uitofp_i8(
+; CHECK:      ld.param.u8 %rs1, [test_uitofp_i8_param_0];
+; SM80:       cvt.rn.f32.u16  [[B:%f[0-9]+]], [[A]];
+; SM80:       cvt.rn.bf16.f32 [[R:%rs[0-9]+]], [[B]];
+; SM90:       cvt.rn.bf16.u16 [[R:%rs[0-9]+]], [[A]];
+; CHECK:      st.param.b16    [func_retval0+0], [[R]];
+; CHECK:      ret;
+define bfloat @test_uitofp_i8(i8 %a) {
+  %r = uitofp i8 %a to bfloat
+  ret bfloat %r
+}
+
+; CHECK-LABEL: test_uitofp_i1(
+; CHECK:      ld.param.u8     [[A:%rs[0-9]+]], [test_uitofp_i1_param_0];
+; CHECK:      and.b16         [[B:%rs[0-9]+]], [[A]], 1;
+; CHECK:      setp.eq.b16     [[C:%p[0-9]+]], [[B]], 1;
+; CHECK:      selp.u32        [[D:%r[0-9]+]], 1, 0, [[C]];
+; SM80:       cvt.rn.f32.u32  [[E:%f[0-9]+]], [[D]];
+; SM80:       cvt.rn.bf16.f32 [[R:%rs[0-9]+]], [[E]];
+; SM90:       cvt.rn.bf16.u32 [[R:%rs[0-9]+]], [[D]];
+; CHECK:      st.param.b16    [func_retval0+0], [[R]];
+; CHECK:      ret;
+define bfloat @test_uitofp_i1(i1 %a) {
+  %r = uitofp i1 %a to bfloat
+  ret bfloat %r
+}
+
+; CHECK-LABEL: test_uitofp_i16(
+; CHECK:      ld.param.u16    [[A:%rs[0-9]+]], [test_uitofp_i16_param_0];
+; SM80:       cvt.rn.f32.u16  [[B:%f[0-9]+]], [[A]];
+; SM80:       cvt.rn.bf16.f32 [[R:%rs[0-9]+]], [[B]];
+; SM90:       cvt.rn.bf16.u16 [[R:%rs[0-9]+]], [[A]];
+; CHECK:      st.param.b16    [func_retval0+0], [[R]];
+; CHECK:      ret;
+define bfloat @test_uitofp_i16(i16 %a) {
+  %r = uitofp i16 %a to bfloat
+  ret bfloat %r
+}
+
+; CHECK-LABEL: test_uitofp_i32(
+; CHECK:      ld.param.u32    [[A:%r[0-9]+]], [test_uitofp_i32_param_0];
+; SM80:       cvt.rn.f32.u32  [[B:%f[0-9]+]], [[A]];
+; SM80:       cvt.rn.bf16.f32 [[R:%rs[0-9]+]], [[B]];
+; SM90:       cvt.rn.bf16.u32 [[R:%rs[0-9]+]], [[A]];
+; CHECK:      st.param.b16    [func_retval0+0], [[R]];
+; CHECK:      ret;
+define bfloat @test_uitofp_i32(i32 %a) {
+  %r = uitofp i32 %a to bfloat
+  ret bfloat %r
+}
+
+; CHECK-LABEL: test_uitofp_i64(
+; CHECK:      ld.param.u64    [[A:%rd[0-9]+]], [test_uitofp_i64_param_0];
+; SM80:       cvt.rn.f32.u64  [[B:%f[0-9]+]], [[A]];
+; SM80:       cvt.rn.bf16.f32 [[R:%rs[0-9]+]], [[B]];
+; SM90:       cvt.rn.bf16.u64 [[R:%rs[0-9]+]], [[A]];
+; CHECK:      st.param.b16    [func_retval0+0], [[R]];
+; CHECK:      ret;
+define bfloat @test_uitofp_i64(i64 %a) {
+  %r = uitofp i64 %a to bfloat
+  ret bfloat %r
+}
-- 
GitLab


From ced631e0da3443d4afe4b5c1992bc2c438caa8a8 Mon Sep 17 00:00:00 2001
From: Peter Klausler <35819229+klausler@users.noreply.github.com>
Date: Mon, 11 Dec 2023 12:11:20 -0800
Subject: [PATCH 160/349] [flang][runtime] Handle Fw.0 case that needs to round
 up to 1.0 (#74384)

A tricky case in Fw.d output editing is when the value needs to be
rounded either to a signed zero or away from zero to a power of ten
(1.0, 0.1, &c.). A bug report for LLVM on GitHub (#74274) exposed a bug
in this code in the case of Fw.0 editing where a value just over 0.5 was
rounded incorrectly to 0 rather than 1 when no fractional digits were
requested.

Rework that algorithm a little, ensuring that the initial
binary->decimal conversion produces at least one digit, and coping
correctly with the rounding of an exact 0.5 value for Fw.0 editing
(rounding it to the nearest even decimal, namely 0, following
near-universal compiler-dependent behavior in other Fortrans).

Fixes https://github.com/llvm/llvm-project/issues/74274.
---
 flang/runtime/edit-output.cpp                 | 80 ++++++++++++-------
 .../unittests/Runtime/NumericalFormatTest.cpp | 29 +++++--
 2 files changed, 72 insertions(+), 37 deletions(-)

diff --git a/flang/runtime/edit-output.cpp b/flang/runtime/edit-output.cpp
index 18e2a3f1e537..a4ce0b12f911 100644
--- a/flang/runtime/edit-output.cpp
+++ b/flang/runtime/edit-output.cpp
@@ -433,27 +433,28 @@ bool RealOutputEditing<KIND>::EditFOutput(const DataEdit &edit) {
   }
   // Multiple conversions may be needed to get the right number of
   // effective rounded fractional digits.
-  int extraDigits{0};
   bool canIncrease{true};
-  while (true) {
+  for (int extraDigits{fracDigits == 0 ? 1 : 0};;) {
     decimal::ConversionToDecimalResult converted{
         ConvertToDecimal(extraDigits + fracDigits, rounding, flags)};
-    if (IsInfOrNaN(converted.str, static_cast<int>(converted.length))) {
+    const char *convertedStr{converted.str};
+    if (IsInfOrNaN(convertedStr, static_cast<int>(converted.length))) {
       return editWidth > 0 &&
               converted.length > static_cast<std::size_t>(editWidth)
           ? EmitRepeated(io_, '*', editWidth)
           : EmitPrefix(edit, converted.length, editWidth) &&
-              EmitAscii(io_, converted.str, converted.length) &&
+              EmitAscii(io_, convertedStr, converted.length) &&
               EmitSuffix(edit);
     }
     int expo{converted.decimalExponent + edit.modes.scale /*kP*/};
-    int signLength{*converted.str == '-' || *converted.str == '+' ? 1 : 0};
+    int signLength{*convertedStr == '-' || *convertedStr == '+' ? 1 : 0};
     int convertedDigits{static_cast<int>(converted.length) - signLength};
     if (IsZero()) { // don't treat converted "0" as significant digit
       expo = 0;
       convertedDigits = 0;
     }
-    int trailingOnes{0};
+    bool isNegative{*convertedStr == '-'};
+    char one[2];
     if (expo > extraDigits && extraDigits >= 0 && canIncrease) {
       extraDigits = expo;
       if (!edit.digits.has_value()) { // F0
@@ -462,24 +463,45 @@ bool RealOutputEditing<KIND>::EditFOutput(const DataEdit &edit) {
       canIncrease = false; // only once
       continue;
     } else if (expo == -fracDigits && convertedDigits > 0) {
-      if ((rounding == decimal::FortranRounding::RoundUp &&
-              *converted.str != '-') ||
-          (rounding == decimal::FortranRounding::RoundDown &&
-              *converted.str == '-') ||
-          (rounding == decimal::FortranRounding::RoundToZero &&
-              rounding != edit.modes.round && // it changed below
-              converted.str[signLength] >= '5')) {
-        // Round up/down to a scaled 1
+      // Result will be either a signed zero or power of ten, depending
+      // on rounding.
+      char leading{convertedStr[signLength]};
+      bool roundToPowerOfTen{false};
+      switch (edit.modes.round) {
+      case decimal::FortranRounding::RoundUp:
+        roundToPowerOfTen = !isNegative;
+        break;
+      case decimal::FortranRounding::RoundDown:
+        roundToPowerOfTen = isNegative;
+        break;
+      case decimal::FortranRounding::RoundToZero:
+        break;
+      case decimal::FortranRounding::RoundNearest:
+        if (leading == '5' &&
+            rounding == decimal::FortranRounding::RoundNearest) {
+          // Try again, rounding away from zero.
+          rounding = isNegative ? decimal::FortranRounding::RoundDown
+                                : decimal::FortranRounding::RoundUp;
+          extraDigits = 1 - fracDigits; // just one digit needed
+          continue;
+        }
+        roundToPowerOfTen = leading > '5';
+        break;
+      case decimal::FortranRounding::RoundCompatible:
+        roundToPowerOfTen = leading >= '5';
+        break;
+      }
+      if (roundToPowerOfTen) {
         ++expo;
-        convertedDigits = 0;
-        trailingOnes = 1;
-      } else if (rounding != decimal::FortranRounding::RoundToZero) {
-        // Convert again with truncation so first digit can be checked
-        // on the next iteration by the code above
-        rounding = decimal::FortranRounding::RoundToZero;
-        continue;
+        convertedDigits = 1;
+        if (signLength > 0) {
+          one[0] = *convertedStr;
+          one[1] = '1';
+        } else {
+          one[0] = '1';
+        }
+        convertedStr = one;
       } else {
-        // Value rounds down to zero
         expo = 0;
         convertedDigits = 0;
       }
@@ -493,17 +515,14 @@ bool RealOutputEditing<KIND>::EditFOutput(const DataEdit &edit) {
     int digitsAfterPoint{convertedDigits - digitsBeforePoint};
     int trailingZeroes{flags & decimal::Minimize
             ? 0
-            : std::max(0,
-                  fracDigits -
-                      (zeroesAfterPoint + digitsAfterPoint + trailingOnes))};
+            : std::max(0, fracDigits - (zeroesAfterPoint + digitsAfterPoint))};
     if (digitsBeforePoint + zeroesBeforePoint + zeroesAfterPoint +
-            digitsAfterPoint + trailingOnes + trailingZeroes ==
+            digitsAfterPoint + trailingZeroes ==
         0) {
       zeroesBeforePoint = 1; // "." -> "0."
     }
     int totalLength{signLength + digitsBeforePoint + zeroesBeforePoint +
-        1 /*'.'*/ + zeroesAfterPoint + digitsAfterPoint + trailingOnes +
-        trailingZeroes};
+        1 /*'.'*/ + zeroesAfterPoint + digitsAfterPoint + trailingZeroes};
     int width{editWidth > 0 ? editWidth : totalLength};
     if (totalLength > width) {
       return EmitRepeated(io_, '*', width);
@@ -513,13 +532,12 @@ bool RealOutputEditing<KIND>::EditFOutput(const DataEdit &edit) {
       ++totalLength;
     }
     return EmitPrefix(edit, totalLength, width) &&
-        EmitAscii(io_, converted.str, signLength + digitsBeforePoint) &&
+        EmitAscii(io_, convertedStr, signLength + digitsBeforePoint) &&
         EmitRepeated(io_, '0', zeroesBeforePoint) &&
         EmitAscii(io_, edit.modes.editingFlags & decimalComma ? "," : ".", 1) &&
         EmitRepeated(io_, '0', zeroesAfterPoint) &&
-        EmitAscii(io_, converted.str + signLength + digitsBeforePoint,
+        EmitAscii(io_, convertedStr + signLength + digitsBeforePoint,
             digitsAfterPoint) &&
-        EmitRepeated(io_, '1', trailingOnes) &&
         EmitRepeated(io_, '0', trailingZeroes) &&
         EmitRepeated(io_, ' ', trailingBlanks_) && EmitSuffix(edit);
   }
diff --git a/flang/unittests/Runtime/NumericalFormatTest.cpp b/flang/unittests/Runtime/NumericalFormatTest.cpp
index 219947fe4fbb..b5b8eb059437 100644
--- a/flang/unittests/Runtime/NumericalFormatTest.cpp
+++ b/flang/unittests/Runtime/NumericalFormatTest.cpp
@@ -710,8 +710,12 @@ TEST(IOApiTests, FormatDoubleValues) {
       {"(F5.3,';')", 0.099999, "0.100;"},
       {"(F5.3,';')", 0.0099999, "0.010;"},
       {"(F5.3,';')", 0.00099999, "0.001;"},
-      {"(F5.3,';')", 0.0005, "0.001;"},
-      {"(F5.3,';')", 0.00049999, "0.000;"},
+      {"(F5.3,';')",
+          0.0005000000000000000104083408558608425664715468883514404296875,
+          "0.001;"},
+      {"(F5.3,';')",
+          0.000499999999999999901988123607310399165726266801357269287109375,
+          "0.000;"},
       {"(F5.3,';')", 0.000099999, "0.000;"},
       {"(F5.3,';')", -99.999, "*****;"},
       {"(F5.3,';')", -9.9999, "*****;"},
@@ -719,17 +723,30 @@ TEST(IOApiTests, FormatDoubleValues) {
       {"(F5.3,';')", -0.099999, "-.100;"},
       {"(F5.3,';')", -0.0099999, "-.010;"},
       {"(F5.3,';')", -0.00099999, "-.001;"},
-      {"(F5.3,';')", -0.0005, "-.001;"},
-      {"(F5.3,';')", -0.00049999, "-.000;"},
+      {"(F5.3,';')",
+          -0.0005000000000000000104083408558608425664715468883514404296875,
+          "-.001;"},
+      {"(F5.3,';')",
+          -0.000499999999999999901988123607310399165726266801357269287109375,
+          "-.000;"},
       {"(F5.3,';')", -0.000099999, "-.000;"},
       {"(F0.1,';')", 0.0, ".0;"},
+      {"(F5.0,';')", -0.5000000000000001, "  -1.;"},
+      {"(F5.0,';')", -0.5, "  -0.;"},
+      {"(F5.0,';')", -0.49999999999999994, "  -0.;"},
+      {"(F5.0,';')", 0.49999999999999994, "   0.;"},
+      {"(F5.0,';')", 0.5, "   0.;"},
+      {"(F5.0,';')", 0.5000000000000001, "   1.;"},
   };
 
   for (auto const &[format, value, expect] : individualTestCases) {
     std::string got;
+    char hex[17];
+    std::snprintf(hex, sizeof hex, "%016llx",
+        *reinterpret_cast<const unsigned long long *>(&value));
     ASSERT_TRUE(CompareFormatReal(format, value, expect, got))
-        << "Failed to format " << format << ", expected '" << expect
-        << "', got '" << got << "'";
+        << "Failed to format " << value << " 0x" << hex << " with format "
+        << format << ", expected '" << expect << "', got '" << got << "'";
   }
 
   // Problematic EN formatting edge cases with rounding
-- 
GitLab


From 631c6e834cb07b2769e2c8f1e186dd3a3e0777a1 Mon Sep 17 00:00:00 2001
From: Artem Belevich <tra@google.com>
Date: Mon, 11 Dec 2023 12:18:28 -0800
Subject: [PATCH 161/349] [CUDA] Add support for CUDA-12.3 and sm_90a (#74895)

---
 clang/docs/ReleaseNotes.rst                 |  3 +++
 clang/include/clang/Basic/BuiltinsNVPTX.def | 13 +++++++++++--
 clang/include/clang/Basic/Cuda.h            |  7 +++++--
 clang/lib/Basic/Cuda.cpp                    |  5 +++++
 clang/lib/Basic/Targets/NVPTX.cpp           |  3 +++
 clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp    |  1 +
 clang/lib/Driver/ToolChains/Cuda.cpp        |  6 ++++++
 clang/test/Misc/target-invalid-cpu-note.c   |  2 +-
 llvm/lib/Target/NVPTX/NVPTX.td              | 19 ++++++++++---------
 llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp    |  7 ++++++-
 llvm/lib/Target/NVPTX/NVPTXSubtarget.h      | 17 +++++++++++++++--
 11 files changed, 66 insertions(+), 17 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 6e4009deaf87..783dc7333af7 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -973,6 +973,9 @@ CUDA/HIP Language Changes
 CUDA Support
 ^^^^^^^^^^^^
 
+- Clang now supports CUDA SDK up to 12.3
+- Added support for sm_90a
+
 AIX Support
 ^^^^^^^^^^^
 
diff --git a/clang/include/clang/Basic/BuiltinsNVPTX.def b/clang/include/clang/Basic/BuiltinsNVPTX.def
index d74a7d1e55dd..0f2e8260143b 100644
--- a/clang/include/clang/Basic/BuiltinsNVPTX.def
+++ b/clang/include/clang/Basic/BuiltinsNVPTX.def
@@ -26,7 +26,9 @@
 #pragma push_macro("SM_87")
 #pragma push_macro("SM_89")
 #pragma push_macro("SM_90")
-#define SM_90 "sm_90"
+#pragma push_macro("SM_90a")
+#define SM_90a "sm_90a"
+#define SM_90 "sm_90|" SM_90a
 #define SM_89 "sm_89|" SM_90
 #define SM_87 "sm_87|" SM_89
 #define SM_86 "sm_86|" SM_87
@@ -56,7 +58,11 @@
 #pragma push_macro("PTX78")
 #pragma push_macro("PTX80")
 #pragma push_macro("PTX81")
-#define PTX81 "ptx81"
+#pragma push_macro("PTX82")
+#pragma push_macro("PTX83")
+#define PTX83 "ptx83"
+#define PTX82 "ptx82|" PTX83
+#define PTX81 "ptx81|" PTX82
 #define PTX80 "ptx80|" PTX81
 #define PTX78 "ptx78|" PTX80
 #define PTX77 "ptx77|" PTX78
@@ -1055,6 +1061,7 @@ TARGET_BUILTIN(__nvvm_getctarank_shared_cluster, "iv*3", "", AND(SM_90,PTX78))
 #pragma pop_macro("SM_87")
 #pragma pop_macro("SM_89")
 #pragma pop_macro("SM_90")
+#pragma pop_macro("SM_90a")
 #pragma pop_macro("PTX42")
 #pragma pop_macro("PTX60")
 #pragma pop_macro("PTX61")
@@ -1072,3 +1079,5 @@ TARGET_BUILTIN(__nvvm_getctarank_shared_cluster, "iv*3", "", AND(SM_90,PTX78))
 #pragma pop_macro("PTX78")
 #pragma pop_macro("PTX80")
 #pragma pop_macro("PTX81")
+#pragma pop_macro("PTX82")
+#pragma pop_macro("PTX83")
diff --git a/clang/include/clang/Basic/Cuda.h b/clang/include/clang/Basic/Cuda.h
index 2d912bdbbd1b..916cb4b7ef34 100644
--- a/clang/include/clang/Basic/Cuda.h
+++ b/clang/include/clang/Basic/Cuda.h
@@ -39,9 +39,11 @@ enum class CudaVersion {
   CUDA_118,
   CUDA_120,
   CUDA_121,
-  FULLY_SUPPORTED = CUDA_118,
+  CUDA_122,
+  CUDA_123,
+  FULLY_SUPPORTED = CUDA_123,
   PARTIALLY_SUPPORTED =
-      CUDA_121, // Partially supported. Proceed with a warning.
+      CUDA_123, // Partially supported. Proceed with a warning.
   NEW = 10000,  // Too new. Issue a warning, but allow using it.
 };
 const char *CudaVersionToString(CudaVersion V);
@@ -71,6 +73,7 @@ enum class CudaArch {
   SM_87,
   SM_89,
   SM_90,
+  SM_90a,
   GFX600,
   GFX601,
   GFX602,
diff --git a/clang/lib/Basic/Cuda.cpp b/clang/lib/Basic/Cuda.cpp
index 65840b9f2025..1b1da6a1356f 100644
--- a/clang/lib/Basic/Cuda.cpp
+++ b/clang/lib/Basic/Cuda.cpp
@@ -39,6 +39,8 @@ static const CudaVersionMapEntry CudaNameVersionMap[] = {
     CUDA_ENTRY(11, 8),
     CUDA_ENTRY(12, 0),
     CUDA_ENTRY(12, 1),
+    CUDA_ENTRY(12, 2),
+    CUDA_ENTRY(12, 3),
     {"", CudaVersion::NEW, llvm::VersionTuple(std::numeric_limits<int>::max())},
     {"unknown", CudaVersion::UNKNOWN, {}} // End of list tombstone.
 };
@@ -93,6 +95,7 @@ static const CudaArchToStringMap arch_names[] = {
     SM(87),                          // Jetson/Drive AGX Orin
     SM(89),                          // Ada Lovelace
     SM(90),                          // Hopper
+    SM(90a),                         // Hopper
     GFX(600),  // gfx600
     GFX(601),  // gfx601
     GFX(602),  // gfx602
@@ -209,6 +212,8 @@ CudaVersion MinVersionForCudaArch(CudaArch A) {
   case CudaArch::SM_89:
   case CudaArch::SM_90:
     return CudaVersion::CUDA_118;
+  case CudaArch::SM_90a:
+    return CudaVersion::CUDA_120;
   default:
     llvm_unreachable("invalid enum");
   }
diff --git a/clang/lib/Basic/Targets/NVPTX.cpp b/clang/lib/Basic/Targets/NVPTX.cpp
index 3a4a75b0348f..5c601812f617 100644
--- a/clang/lib/Basic/Targets/NVPTX.cpp
+++ b/clang/lib/Basic/Targets/NVPTX.cpp
@@ -262,11 +262,14 @@ void NVPTXTargetInfo::getTargetDefines(const LangOptions &Opts,
       case CudaArch::SM_89:
         return "890";
       case CudaArch::SM_90:
+      case CudaArch::SM_90a:
         return "900";
       }
       llvm_unreachable("unhandled CudaArch");
     }();
     Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
+    if (GPU == CudaArch::SM_90a)
+      Builder.defineMacro("__CUDA_ARCH_FEAT_SM90_ALL", "1");
   }
 }
 
diff --git a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
index 293ccaa3413c..299ee1460b3d 100644
--- a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
+++ b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
@@ -3483,6 +3483,7 @@ void CGOpenMPRuntimeGPU::processRequiresDirective(
       case CudaArch::SM_87:
       case CudaArch::SM_89:
       case CudaArch::SM_90:
+      case CudaArch::SM_90a:
       case CudaArch::GFX600:
       case CudaArch::GFX601:
       case CudaArch::GFX602:
diff --git a/clang/lib/Driver/ToolChains/Cuda.cpp b/clang/lib/Driver/ToolChains/Cuda.cpp
index e95ff98e6c94..ef1e77974c1e 100644
--- a/clang/lib/Driver/ToolChains/Cuda.cpp
+++ b/clang/lib/Driver/ToolChains/Cuda.cpp
@@ -78,6 +78,10 @@ CudaVersion getCudaVersion(uint32_t raw_version) {
     return CudaVersion::CUDA_120;
   if (raw_version < 12020)
     return CudaVersion::CUDA_121;
+  if (raw_version < 12030)
+    return CudaVersion::CUDA_122;
+  if (raw_version < 12040)
+    return CudaVersion::CUDA_123;
   return CudaVersion::NEW;
 }
 
@@ -671,6 +675,8 @@ void NVPTX::getNVPTXTargetFeatures(const Driver &D, const llvm::Triple &Triple,
   case CudaVersion::CUDA_##CUDA_VER:                                           \
     PtxFeature = "+ptx" #PTX_VER;                                              \
     break;
+    CASE_CUDA_VERSION(123, 83);
+    CASE_CUDA_VERSION(122, 82);
     CASE_CUDA_VERSION(121, 81);
     CASE_CUDA_VERSION(120, 80);
     CASE_CUDA_VERSION(118, 78);
diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c
index e8c5ecbcb536..e840a9208f5a 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -29,7 +29,7 @@
 
 // RUN: not %clang_cc1 -triple nvptx--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix NVPTX
 // NVPTX: error: unknown target CPU 'not-a-cpu'
-// NVPTX-NEXT: note: valid target CPU values are: sm_20, sm_21, sm_30, sm_32, sm_35, sm_37, sm_50, sm_52, sm_53, sm_60, sm_61, sm_62, sm_70, sm_72, sm_75, sm_80, sm_86, sm_87, sm_89, sm_90, gfx600, gfx601, gfx602, gfx700, gfx701, gfx702, gfx703, gfx704, gfx705, gfx801, gfx802, gfx803, gfx805, gfx810, gfx900, gfx902, gfx904, gfx906, gfx908, gfx909, gfx90a, gfx90c, gfx940, gfx941, gfx942, gfx1010, gfx1011, gfx1012, gfx1013, gfx1030, gfx1031, gfx1032, gfx1033, gfx1034, gfx1035, gfx1036, gfx1100, gfx1101, gfx1102, gfx1103, gfx1150, gfx1151, gfx1200, gfx1201{{$}}
+// NVPTX-NEXT: note: valid target CPU values are: sm_20, sm_21, sm_30, sm_32, sm_35, sm_37, sm_50, sm_52, sm_53, sm_60, sm_61, sm_62, sm_70, sm_72, sm_75, sm_80, sm_86, sm_87, sm_89, sm_90, sm_90a, gfx600, gfx601, gfx602, gfx700, gfx701, gfx702, gfx703, gfx704, gfx705, gfx801, gfx802, gfx803, gfx805, gfx810, gfx900, gfx902, gfx904, gfx906, gfx908, gfx909, gfx90a, gfx90c, gfx940, gfx941, gfx942, gfx1010, gfx1011, gfx1012, gfx1013, gfx1030, gfx1031, gfx1032, gfx1033, gfx1034, gfx1035, gfx1036, gfx1100, gfx1101, gfx1102, gfx1103, gfx1150, gfx1151, gfx1200, gfx1201{{$}}
 
 // RUN: not %clang_cc1 -triple r600--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix R600
 // R600: error: unknown target CPU 'not-a-cpu'
diff --git a/llvm/lib/Target/NVPTX/NVPTX.td b/llvm/lib/Target/NVPTX/NVPTX.td
index 02fa2a4ee81e..f2a4ce381b40 100644
--- a/llvm/lib/Target/NVPTX/NVPTX.td
+++ b/llvm/lib/Target/NVPTX/NVPTX.td
@@ -24,23 +24,24 @@ include "NVPTXInstrInfo.td"
 //   TableGen in NVPTXGenSubtarget.inc.
 //===----------------------------------------------------------------------===//
 
-class FeatureSM<int version>:
-   SubtargetFeature<"sm_"# version, "SmVersion",
-                    "" # version,
-                    "Target SM " # version>;
-def SM90a: FeatureSM<90>;
+class FeatureSM<string sm, int value>:
+   SubtargetFeature<"sm_"# sm, "FullSmVersion",
+                    "" # value,
+                    "Target SM " # sm>;
 
 class FeaturePTX<int version>:
    SubtargetFeature<"ptx"# version, "PTXVersion",
                     "" # version,
                     "Use PTX version " # version>;
 
-foreach version = [20, 21, 30, 32, 35, 37, 50, 52, 53,
-                   60, 61, 62, 70, 72, 75, 80, 86, 87, 89, 90] in
-  def SM#version: FeatureSM<version>;
+foreach sm = [20, 21, 30, 32, 35, 37, 50, 52, 53,
+              60, 61, 62, 70, 72, 75, 80, 86, 87, 89, 90] in
+  def SM#sm: FeatureSM<""#sm, !mul(sm, 10)>;
+
+def SM90a: FeatureSM<"90a", 901>;
 
 foreach version = [32, 40, 41, 42, 43, 50, 60, 61, 63, 64, 65,
-                   70, 71, 72, 73, 74, 75, 76, 77, 78, 80, 81] in
+                   70, 71, 72, 73, 74, 75, 76, 77, 78, 80, 81, 82, 83] in
   def PTX#version: FeaturePTX<version>;
 
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp b/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
index 7fa64af196b9..420065585b38 100644
--- a/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
@@ -36,6 +36,11 @@ NVPTXSubtarget &NVPTXSubtarget::initializeSubtargetDependencies(StringRef CPU,
 
     ParseSubtargetFeatures(TargetName, /*TuneCPU*/ TargetName, FS);
 
+    // Re-map SM version numbers, SmVersion carries the regular SMs which do
+    // have relative order, while FullSmVersion allows distinguishing sm_90 from
+    // sm_90a, which would *not* be a subset of sm_91.
+    SmVersion = getSmVersion();
+
     // Set default to PTX 6.0 (CUDA 9.0)
     if (PTXVersion == 0) {
       PTXVersion = 60;
@@ -48,7 +53,7 @@ NVPTXSubtarget::NVPTXSubtarget(const Triple &TT, const std::string &CPU,
                                const std::string &FS,
                                const NVPTXTargetMachine &TM)
     : NVPTXGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), PTXVersion(0),
-      SmVersion(20), TM(TM),
+      FullSmVersion(200), SmVersion(getSmVersion()), TM(TM),
       TLInfo(TM, initializeSubtargetDependencies(CPU, FS)) {}
 
 bool NVPTXSubtarget::hasImageHandles() const {
diff --git a/llvm/lib/Target/NVPTX/NVPTXSubtarget.h b/llvm/lib/Target/NVPTX/NVPTXSubtarget.h
index 93af11c258b4..3ca4c1a24c79 100644
--- a/llvm/lib/Target/NVPTX/NVPTXSubtarget.h
+++ b/llvm/lib/Target/NVPTX/NVPTXSubtarget.h
@@ -35,7 +35,12 @@ class NVPTXSubtarget : public NVPTXGenSubtargetInfo {
   // PTX version x.y is represented as 10*x+y, e.g. 3.1 == 31
   unsigned PTXVersion;
 
-  // SM version x.y is represented as 10*x+y, e.g. 3.1 == 31
+  // Full SM version x.y is represented as 100*x+10*y+feature, e.g. 3.1 == 310
+  // sm_90a == 901
+  unsigned int FullSmVersion;
+
+  // SM version x.y is represented as 10*x+y, e.g. 3.1 == 31. Derived from
+  // FullSmVersion.
   unsigned int SmVersion;
 
   const NVPTXTargetMachine &TM;
@@ -80,7 +85,15 @@ public:
   bool allowFP16Math() const;
   bool hasMaskOperator() const { return PTXVersion >= 71; }
   bool hasNoReturn() const { return SmVersion >= 30 && PTXVersion >= 64; }
-  unsigned int getSmVersion() const { return SmVersion; }
+  unsigned int getFullSmVersion() const { return FullSmVersion; }
+  unsigned int getSmVersion() const { return getFullSmVersion() / 10; }
+  // GPUs with "a" suffix have include architecture-accelerated features that
+  // are supported on the specified architecture only, hence such targets do not
+  // follow the onion layer model. hasAAFeatures() allows distinguishing such
+  // GPU variants from the base GPU architecture.
+  // - 0 represents base GPU model,
+  // - non-zero value identifies particular architecture-accelerated variant.
+  bool hasAAFeatures() const { return getFullSmVersion() % 10; }
   std::string getTargetName() const { return TargetName; }
 
   // Get maximum value of required alignments among the supported data types.
-- 
GitLab


From 0ea19bd3333af71dd3aaf7c0a6ef9a0930958c12 Mon Sep 17 00:00:00 2001
From: Walter Erquinigo <a20012251@gmail.com>
Date: Mon, 11 Dec 2023 15:20:06 -0500
Subject: [PATCH 162/349] [lldb-dap] Emit declarations along with variables
 (#74865)

This is an extension to the protocol that emits the declaration
information along with the metadata of each variable. This can be used
by vscode extensions to implement, for example, a "goToDefinition"
action in the debug tab, or for showing the value of a variable right
next to where it's declared during a debug session.
As this is cheap, I'm not gating this information under any setting.
---
 .../lldb-dap/variables/TestDAP_variables.py   | 10 ++++-
 lldb/tools/lldb-dap/JSONUtils.cpp             | 41 +++++++++++++++++++
 2 files changed, 49 insertions(+), 2 deletions(-)

diff --git a/lldb/test/API/tools/lldb-dap/variables/TestDAP_variables.py b/lldb/test/API/tools/lldb-dap/variables/TestDAP_variables.py
index d2a21ad3cd1d..9b0755eea7d3 100644
--- a/lldb/test/API/tools/lldb-dap/variables/TestDAP_variables.py
+++ b/lldb/test/API/tools/lldb-dap/variables/TestDAP_variables.py
@@ -4,8 +4,8 @@ Test lldb-dap setBreakpoints request
 
 import os
 
-import lldbdap_testcase
 import dap_server
+import lldbdap_testcase
 from lldbsuite.test import lldbutil
 from lldbsuite.test.decorators import *
 from lldbsuite.test.lldbtest import *
@@ -152,7 +152,13 @@ class TestDAP_variables(lldbdap_testcase.DAPTestCaseBase):
         globals = self.dap_server.get_global_variables()
         buffer_children = make_buffer_verify_dict(0, 32)
         verify_locals = {
-            "argc": {"equals": {"type": "int", "value": "1"}},
+            "argc": {
+                "equals": {"type": "int", "value": "1"},
+                "declaration": {
+                    "equals": {"line": 12, "column": 14},
+                    "contains": {"path": ["lldb-dap", "variables", "main.cpp"]},
+                },
+            },
             "argv": {
                 "equals": {"type": "const char **"},
                 "startswith": {"value": "0x"},
diff --git a/lldb/tools/lldb-dap/JSONUtils.cpp b/lldb/tools/lldb-dap/JSONUtils.cpp
index 62d7fa54e75f..c8e5304ecec8 100644
--- a/lldb/tools/lldb-dap/JSONUtils.cpp
+++ b/lldb/tools/lldb-dap/JSONUtils.cpp
@@ -1103,6 +1103,29 @@ std::string CreateUniqueVariableNameForDisplay(lldb::SBValue v,
 //                       can use this optional information to present the
 //                       children in a paged UI and fetch them in chunks."
 //     }
+//     "declaration": {
+//       "type": "object | undefined",
+//       "description": "Extension to the protocol that indicates the source
+//                       location where the variable was declared. This value
+//                       might not be present if no declaration is available.",
+//       "properties": {
+//         "path": {
+//           "type": "string | undefined",
+//           "description": "The source file path where the variable was
+//                           declared."
+//         },
+//         "line": {
+//           "type": "number | undefined",
+//           "description": "The 1-indexed source line where the variable was
+//                          declared."
+//         },
+//         "column": {
+//           "type": "number | undefined",
+//           "description": "The 1-indexed source column where the variable was
+//                          declared."
+//         }
+//       }
+//     }
 //   },
 //   "required": [ "name", "value", "variablesReference" ]
 // }
@@ -1167,6 +1190,24 @@ llvm::json::Value CreateVariable(lldb::SBValue v, int64_t variablesReference,
   const char *evaluateName = evaluateStream.GetData();
   if (evaluateName && evaluateName[0])
     EmplaceSafeString(object, "evaluateName", std::string(evaluateName));
+
+  if (lldb::SBDeclaration decl = v.GetDeclaration(); decl.IsValid()) {
+    llvm::json::Object decl_obj;
+    if (lldb::SBFileSpec file = decl.GetFileSpec(); file.IsValid()) {
+      char path[PATH_MAX] = "";
+      if (file.GetPath(path, sizeof(path)) &&
+          lldb::SBFileSpec::ResolvePath(path, path, PATH_MAX)) {
+        decl_obj.try_emplace("path", std::string(path));
+      }
+    }
+
+    if (int line = decl.GetLine())
+      decl_obj.try_emplace("line", line);
+    if (int column = decl.GetColumn())
+      decl_obj.try_emplace("column", column);
+
+    object.try_emplace("declaration", std::move(decl_obj));
+  }
   return llvm::json::Value(std::move(object));
 }
 
-- 
GitLab


From 7ec399485218e24e80ad403b0abcf84c93fcd51e Mon Sep 17 00:00:00 2001
From: Nico Weber <thakis@chromium.org>
Date: Mon, 11 Dec 2023 15:18:51 -0500
Subject: [PATCH 163/349] [gn build] Port 54397f9ac128

---
 .../secondary/llvm/lib/ExecutionEngine/Orc/Debugging/BUILD.gn  | 3 ++-
 .../gn/secondary/llvm/unittests/ExecutionEngine/Orc/BUILD.gn   | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/Debugging/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/Debugging/BUILD.gn
index 64d38360e250..1d3fc6cfdfaa 100644
--- a/llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/Debugging/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/Debugging/BUILD.gn
@@ -1,9 +1,9 @@
 static_library("Debugging") {
   output_name = "LLVMOrcDebugging"
   deps = [
+    "//llvm/lib/DebugInfo/DWARF",
     "//llvm/lib/ExecutionEngine/Orc",
     "//llvm/lib/ExecutionEngine/Orc/Shared",
-    "//llvm/lib/DebugInfo/DWARF",
     "//llvm/lib/Support",
     "//llvm/lib/TargetParser",
   ]
@@ -11,6 +11,7 @@ static_library("Debugging") {
     "DebugInfoSupport.cpp",
     "DebuggerSupport.cpp",
     "DebuggerSupportPlugin.cpp",
+    "LLJITUtilsCBindings.cpp",
     "PerfSupportPlugin.cpp",
   ]
   if (current_os == "linux") {
diff --git a/llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/Orc/BUILD.gn b/llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/Orc/BUILD.gn
index c258b5232280..47c7bb3d97d1 100644
--- a/llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/Orc/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/Orc/BUILD.gn
@@ -4,6 +4,7 @@ unittest("OrcJITTests") {
   deps = [
     "//llvm/lib/ExecutionEngine",
     "//llvm/lib/ExecutionEngine/Orc",
+    "//llvm/lib/ExecutionEngine/Orc/Debugging",
     "//llvm/lib/ExecutionEngine/Orc/Shared",
     "//llvm/lib/ExecutionEngine/RuntimeDyld",
     "//llvm/lib/IR",
-- 
GitLab


From 13662211c32cb9034b67d7fe0fb73fdebd15471e Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@sifive.com>
Date: Mon, 11 Dec 2023 12:16:59 -0800
Subject: [PATCH 164/349] [RISCV] Simplify checking whether SEW=64 multiply
 builtins require V. NFC

We only need to check the result type. Use getBuiltinVectorTypeInfo
to lookup the element size.
---
 clang/lib/Sema/SemaChecking.cpp | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 08c03d75ec3c..4c5187774233 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5213,12 +5213,10 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
   case RISCVVector::BI__builtin_rvv_vsmul_vx_tum:
   case RISCVVector::BI__builtin_rvv_vsmul_vv_tumu:
   case RISCVVector::BI__builtin_rvv_vsmul_vx_tumu: {
-    bool RequireV = false;
-    for (unsigned ArgNum = 0; ArgNum < TheCall->getNumArgs(); ++ArgNum)
-      RequireV |= TheCall->getArg(ArgNum)->getType()->isRVVType(
-          /* Bitwidth */ 64, /* IsFloat */ false);
+    ASTContext::BuiltinVectorTypeInfo Info = Context.getBuiltinVectorTypeInfo(
+        TheCall->getType()->castAs<BuiltinType>());
 
-    if (RequireV && !TI.hasFeature("v"))
+    if (Context.getTypeSize(Info.ElementType) == 64 && !TI.hasFeature("v"))
       return Diag(TheCall->getBeginLoc(),
                   diag::err_riscv_builtin_requires_extension)
              << /* IsExtension */ false << TheCall->getSourceRange() << "v";
-- 
GitLab


From b62605388c975c3c0649a2d5a51136ffeea86e7b Mon Sep 17 00:00:00 2001
From: Peter Klausler <35819229+klausler@users.noreply.github.com>
Date: Mon, 11 Dec 2023 12:25:05 -0800
Subject: [PATCH 165/349] [flang][runtime] Terminate last partial record after
 non-advancing write (#74524)

After a non-advancing WRITE to a unit, ensure that any ENDFILE operation
(explicit or implicit) terminates the record. (All other Fortran
implementations do so except XLF.)

Fixes llvm-test-suite/Fortran/gfortran/regression/advance_6.f90.
---
 flang/runtime/unit.cpp | 31 ++++++++++++++++---------------
 1 file changed, 16 insertions(+), 15 deletions(-)

diff --git a/flang/runtime/unit.cpp b/flang/runtime/unit.cpp
index 5fa8565c2f61..dfe61263feb8 100644
--- a/flang/runtime/unit.cpp
+++ b/flang/runtime/unit.cpp
@@ -595,8 +595,8 @@ void ExternalFileUnit::BackspaceRecord(IoErrorHandler &handler) {
     if (IsAfterEndfile()) {
       // BACKSPACE after explicit ENDFILE
       currentRecordNumber = *endfileRecordNumber;
-    } else if (leftTabLimit) {
-      // BACKSPACE after non-advancing I/O
+    } else if (leftTabLimit && direction_ == Direction::Input) {
+      // BACKSPACE after non-advancing input
       leftTabLimit.reset();
     } else {
       DoImpliedEndfile(handler);
@@ -896,28 +896,29 @@ void ExternalFileUnit::BackspaceVariableFormattedRecord(
 }
 
 void ExternalFileUnit::DoImpliedEndfile(IoErrorHandler &handler) {
-  if (!impliedEndfile_ && direction_ == Direction::Output && IsRecordFile() &&
-      access != Access::Direct && leftTabLimit) {
-    // Complete partial record after non-advancing write before
-    // positioning or closing the unit.  Usually sets impliedEndfile_.
-    AdvanceRecord(handler);
-  }
-  if (impliedEndfile_) {
-    impliedEndfile_ = false;
-    if (access != Access::Direct && IsRecordFile() && mayPosition()) {
+  if (access != Access::Direct) {
+    if (!impliedEndfile_ && leftTabLimit && direction_ == Direction::Output) {
+      // Flush a partial record after non-advancing output
+      impliedEndfile_ = true;
+    }
+    if (impliedEndfile_ && mayPosition()) {
       DoEndfile(handler);
     }
   }
+  impliedEndfile_ = false;
 }
 
 void ExternalFileUnit::DoEndfile(IoErrorHandler &handler) {
   if (IsRecordFile() && access != Access::Direct) {
     furthestPositionInRecord =
         std::max(positionInRecord, furthestPositionInRecord);
-    if (leftTabLimit) {
-      // Last read/write was non-advancing, so AdvanceRecord() was not called.
-      leftTabLimit.reset();
-      ++currentRecordNumber;
+    if (leftTabLimit) { // last I/O was non-advancing
+      if (access == Access::Sequential && direction_ == Direction::Output) {
+        AdvanceRecord(handler);
+      } else { // Access::Stream or input
+        leftTabLimit.reset();
+        ++currentRecordNumber;
+      }
     }
     endfileRecordNumber = currentRecordNumber;
   }
-- 
GitLab


From b039ccc684e6f71baf6dc961d100673cd1f333ae Mon Sep 17 00:00:00 2001
From: Amir Ayupov <aaupov@fb.com>
Date: Mon, 11 Dec 2023 12:27:32 -0800
Subject: [PATCH 166/349] [BOLT] Provide backwards compatibility for YAML
 profile with std::hash (#74253)

Provide backwards compatibility for YAML profile that uses `std::hash`:
xxh3 hash is the default for newly produced profile (sets `std-hash:
false`),
whereas the profile that doesn't specify `std-hash` will be treated as
`std-hash: true`, preserving old behavior.
---
 bolt/include/bolt/Core/BinaryFunction.h       | 15 +++-
 .../include/bolt/Profile/ProfileYAMLMapping.h | 11 +++
 bolt/lib/Core/BinaryFunction.cpp              | 10 ++-
 bolt/lib/Passes/IdenticalCodeFolding.cpp      |  6 +-
 bolt/lib/Profile/StaleProfileMatching.cpp     | 40 ++++++++---
 bolt/lib/Profile/YAMLProfileReader.cpp        | 18 ++++-
 bolt/lib/Profile/YAMLProfileWriter.cpp        |  1 +
 .../Inputs/blarge_profile_stale.std-hash.yaml | 56 +++++++++++++++
 .../test/X86/Inputs/blarge_profile_stale.yaml |  1 +
 bolt/test/X86/reader-stale-yaml-std.test      | 68 +++++++++++++++++++
 10 files changed, 209 insertions(+), 17 deletions(-)
 create mode 100644 bolt/test/X86/Inputs/blarge_profile_stale.std-hash.yaml
 create mode 100644 bolt/test/X86/reader-stale-yaml-std.test

diff --git a/bolt/include/bolt/Core/BinaryFunction.h b/bolt/include/bolt/Core/BinaryFunction.h
index 182d5ff049c3..3a1eae3311bd 100644
--- a/bolt/include/bolt/Core/BinaryFunction.h
+++ b/bolt/include/bolt/Core/BinaryFunction.h
@@ -75,6 +75,14 @@ enum IndirectCallPromotionType : char {
   ICP_ALL          /// Perform ICP on calls and jump tables.
 };
 
+/// Hash functions supported for BF/BB hashing.
+enum class HashFunction : char {
+  StdHash, /// std::hash, implementation is platform-dependent. Provided for
+           /// backwards compatibility.
+  XXH3,    /// llvm::xxh3_64bits, the default.
+  Default = XXH3,
+};
+
 /// Information on a single indirect call to a particular callee.
 struct IndirectCallProfile {
   MCSymbol *Symbol;
@@ -2234,18 +2242,21 @@ public:
   ///
   /// If \p UseDFS is set, process basic blocks in DFS order. Otherwise, use
   /// the existing layout order.
+  /// \p HashFunction specifies which function is used for BF hashing.
   ///
   /// By default, instruction operands are ignored while calculating the hash.
   /// The caller can change this via passing \p OperandHashFunc function.
   /// The return result of this function will be mixed with internal hash.
   size_t computeHash(
-      bool UseDFS = false,
+      bool UseDFS = false, HashFunction HashFunction = HashFunction::Default,
       OperandHashFuncTy OperandHashFunc = [](const MCOperand &) {
         return std::string();
       }) const;
 
   /// Compute hash values for each block of the function.
-  void computeBlockHashes() const;
+  /// \p HashFunction specifies which function is used for BB hashing.
+  void
+  computeBlockHashes(HashFunction HashFunction = HashFunction::Default) const;
 
   void setDWARFUnit(DWARFUnit *Unit) { DwarfUnit = Unit; }
 
diff --git a/bolt/include/bolt/Profile/ProfileYAMLMapping.h b/bolt/include/bolt/Profile/ProfileYAMLMapping.h
index 2218a167a74e..548b528ae2d6 100644
--- a/bolt/include/bolt/Profile/ProfileYAMLMapping.h
+++ b/bolt/include/bolt/Profile/ProfileYAMLMapping.h
@@ -178,6 +178,14 @@ template <> struct ScalarBitSetTraits<PROFILE_PF> {
   }
 };
 
+template <> struct ScalarEnumerationTraits<llvm::bolt::HashFunction> {
+  using HashFunction = llvm::bolt::HashFunction;
+  static void enumeration(IO &io, HashFunction &value) {
+    io.enumCase(value, "std-hash", HashFunction::StdHash);
+    io.enumCase(value, "xxh3", HashFunction::XXH3);
+  }
+};
+
 namespace bolt {
 struct BinaryProfileHeader {
   uint32_t Version{1};
@@ -188,6 +196,7 @@ struct BinaryProfileHeader {
   std::string Origin;     // How the profile was obtained.
   std::string EventNames; // Events used for sample profile.
   bool IsDFSOrder{true};  // Whether using DFS block order in function profile
+  llvm::bolt::HashFunction HashFunction; // Hash used for BB/BF hashing
 };
 } // end namespace bolt
 
@@ -200,6 +209,8 @@ template <> struct MappingTraits<bolt::BinaryProfileHeader> {
     YamlIO.mapOptional("profile-origin", Header.Origin);
     YamlIO.mapOptional("profile-events", Header.EventNames);
     YamlIO.mapOptional("dfs-order", Header.IsDFSOrder);
+    YamlIO.mapOptional("hash-func", Header.HashFunction,
+                       llvm::bolt::HashFunction::StdHash);
   }
 };
 
diff --git a/bolt/lib/Core/BinaryFunction.cpp b/bolt/lib/Core/BinaryFunction.cpp
index be033cf07668..0ac47a53a446 100644
--- a/bolt/lib/Core/BinaryFunction.cpp
+++ b/bolt/lib/Core/BinaryFunction.cpp
@@ -3633,7 +3633,7 @@ BinaryFunction::BasicBlockListType BinaryFunction::dfs() const {
   return DFS;
 }
 
-size_t BinaryFunction::computeHash(bool UseDFS,
+size_t BinaryFunction::computeHash(bool UseDFS, HashFunction HashFunction,
                                    OperandHashFuncTy OperandHashFunc) const {
   if (size() == 0)
     return 0;
@@ -3652,7 +3652,13 @@ size_t BinaryFunction::computeHash(bool UseDFS,
   for (const BinaryBasicBlock *BB : Order)
     HashString.append(hashBlock(BC, *BB, OperandHashFunc));
 
-  return Hash = llvm::xxh3_64bits(HashString);
+  switch (HashFunction) {
+  case HashFunction::StdHash:
+    return Hash = std::hash<std::string>{}(HashString);
+  case HashFunction::XXH3:
+    return Hash = llvm::xxh3_64bits(HashString);
+  }
+  llvm_unreachable("Unhandled HashFunction");
 }
 
 void BinaryFunction::insertBasicBlocks(
diff --git a/bolt/lib/Passes/IdenticalCodeFolding.cpp b/bolt/lib/Passes/IdenticalCodeFolding.cpp
index b4ec89ca8fd7..dfbc72e48e5d 100644
--- a/bolt/lib/Passes/IdenticalCodeFolding.cpp
+++ b/bolt/lib/Passes/IdenticalCodeFolding.cpp
@@ -360,9 +360,9 @@ void IdenticalCodeFolding::runOnFunctions(BinaryContext &BC) {
 
       // Pre-compute hash before pushing into hashtable.
       // Hash instruction operands to minimize hash collisions.
-      BF.computeHash(opts::ICFUseDFS, [&BC](const MCOperand &Op) {
-        return hashInstOperand(BC, Op);
-      });
+      BF.computeHash(
+          opts::ICFUseDFS, HashFunction::Default,
+          [&BC](const MCOperand &Op) { return hashInstOperand(BC, Op); });
     };
 
     ParallelUtilities::PredicateTy SkipFunc = [&](const BinaryFunction &BF) {
diff --git a/bolt/lib/Profile/StaleProfileMatching.cpp b/bolt/lib/Profile/StaleProfileMatching.cpp
index 6fb6f380f71e..26180f132147 100644
--- a/bolt/lib/Profile/StaleProfileMatching.cpp
+++ b/bolt/lib/Profile/StaleProfileMatching.cpp
@@ -225,7 +225,7 @@ private:
   std::unordered_map<uint16_t, std::vector<HashBlockPairType>> OpHashToBlocks;
 };
 
-void BinaryFunction::computeBlockHashes() const {
+void BinaryFunction::computeBlockHashes(HashFunction HashFunction) const {
   if (size() == 0)
     return;
 
@@ -241,12 +241,26 @@ void BinaryFunction::computeBlockHashes() const {
     // Hashing complete instructions.
     std::string InstrHashStr = hashBlock(
         BC, *BB, [&](const MCOperand &Op) { return hashInstOperand(BC, Op); });
-    uint64_t InstrHash = llvm::xxh3_64bits(InstrHashStr);
-    BlendedHashes[I].InstrHash = (uint16_t)InstrHash;
+    if (HashFunction == HashFunction::StdHash) {
+      uint64_t InstrHash = std::hash<std::string>{}(InstrHashStr);
+      BlendedHashes[I].InstrHash = (uint16_t)hash_value(InstrHash);
+    } else if (HashFunction == HashFunction::XXH3) {
+      uint64_t InstrHash = llvm::xxh3_64bits(InstrHashStr);
+      BlendedHashes[I].InstrHash = (uint16_t)InstrHash;
+    } else {
+      llvm_unreachable("Unhandled HashFunction");
+    }
     // Hashing opcodes.
     std::string OpcodeHashStr = hashBlockLoose(BC, *BB);
-    OpcodeHashes[I] = llvm::xxh3_64bits(OpcodeHashStr);
-    BlendedHashes[I].OpcodeHash = (uint16_t)OpcodeHashes[I];
+    if (HashFunction == HashFunction::StdHash) {
+      OpcodeHashes[I] = std::hash<std::string>{}(OpcodeHashStr);
+      BlendedHashes[I].OpcodeHash = (uint16_t)hash_value(OpcodeHashes[I]);
+    } else if (HashFunction == HashFunction::XXH3) {
+      OpcodeHashes[I] = llvm::xxh3_64bits(OpcodeHashStr);
+      BlendedHashes[I].OpcodeHash = (uint16_t)OpcodeHashes[I];
+    } else {
+      llvm_unreachable("Unhandled HashFunction");
+    }
   }
 
   // Initialize neighbor hash.
@@ -258,7 +272,12 @@ void BinaryFunction::computeBlockHashes() const {
       uint64_t SuccHash = OpcodeHashes[SuccBB->getIndex()];
       Hash = hashing::detail::hash_16_bytes(Hash, SuccHash);
     }
-    BlendedHashes[I].SuccHash = (uint8_t)Hash;
+    if (HashFunction == HashFunction::StdHash) {
+      // Compatibility with old behavior.
+      BlendedHashes[I].SuccHash = (uint8_t)hash_value(Hash);
+    } else {
+      BlendedHashes[I].SuccHash = (uint8_t)Hash;
+    }
 
     // Append hashes of predecessors.
     Hash = 0;
@@ -266,7 +285,12 @@ void BinaryFunction::computeBlockHashes() const {
       uint64_t PredHash = OpcodeHashes[PredBB->getIndex()];
       Hash = hashing::detail::hash_16_bytes(Hash, PredHash);
     }
-    BlendedHashes[I].PredHash = (uint8_t)Hash;
+    if (HashFunction == HashFunction::StdHash) {
+      // Compatibility with old behavior.
+      BlendedHashes[I].PredHash = (uint8_t)hash_value(Hash);
+    } else {
+      BlendedHashes[I].PredHash = (uint8_t)Hash;
+    }
   }
 
   //  Assign hashes.
@@ -682,7 +706,7 @@ bool YAMLProfileReader::inferStaleProfile(
                     << "\"" << BF.getPrintName() << "\"\n");
 
   // Make sure that block hashes are up to date.
-  BF.computeBlockHashes();
+  BF.computeBlockHashes(YamlBP.Header.HashFunction);
 
   const BinaryFunction::BasicBlockOrderType BlockOrder(
       BF.getLayout().block_begin(), BF.getLayout().block_end());
diff --git a/bolt/lib/Profile/YAMLProfileReader.cpp b/bolt/lib/Profile/YAMLProfileReader.cpp
index 079cb352d36e..ade562ef6fb1 100644
--- a/bolt/lib/Profile/YAMLProfileReader.cpp
+++ b/bolt/lib/Profile/YAMLProfileReader.cpp
@@ -83,6 +83,7 @@ bool YAMLProfileReader::parseFunctionProfile(
   BinaryContext &BC = BF.getBinaryContext();
 
   const bool IsDFSOrder = YamlBP.Header.IsDFSOrder;
+  const HashFunction HashFunction = YamlBP.Header.HashFunction;
   bool ProfileMatched = true;
   uint64_t MismatchedBlocks = 0;
   uint64_t MismatchedCalls = 0;
@@ -98,7 +99,8 @@ bool YAMLProfileReader::parseFunctionProfile(
       FuncRawBranchCount += YamlSI.Count;
   BF.setRawBranchCount(FuncRawBranchCount);
 
-  if (!opts::IgnoreHash && YamlBF.Hash != BF.computeHash(IsDFSOrder)) {
+  if (!opts::IgnoreHash &&
+      YamlBF.Hash != BF.computeHash(IsDFSOrder, HashFunction)) {
     if (opts::Verbosity >= 1)
       errs() << "BOLT-WARNING: function hash mismatch\n";
     ProfileMatched = false;
@@ -326,6 +328,17 @@ bool YAMLProfileReader::mayHaveProfileData(const BinaryFunction &BF) {
 }
 
 Error YAMLProfileReader::readProfile(BinaryContext &BC) {
+  if (opts::Verbosity >= 1) {
+    outs() << "BOLT-INFO: YAML profile with hash: ";
+    switch (YamlBP.Header.HashFunction) {
+    case HashFunction::StdHash:
+      outs() << "std::hash\n";
+      break;
+    case HashFunction::XXH3:
+      outs() << "xxh3\n";
+      break;
+    }
+  }
   YamlProfileToFunction.resize(YamlBP.Functions.size() + 1);
 
   auto profileMatches = [](const yaml::bolt::BinaryFunctionProfile &Profile,
@@ -348,7 +361,8 @@ Error YAMLProfileReader::readProfile(BinaryContext &BC) {
 
     // Recompute hash once per function.
     if (!opts::IgnoreHash)
-      Function.computeHash(YamlBP.Header.IsDFSOrder);
+      Function.computeHash(YamlBP.Header.IsDFSOrder,
+                           YamlBP.Header.HashFunction);
 
     if (profileMatches(YamlBF, Function))
       matchProfileToFunction(YamlBF, Function);
diff --git a/bolt/lib/Profile/YAMLProfileWriter.cpp b/bolt/lib/Profile/YAMLProfileWriter.cpp
index 3326d1d8f559..dffd851a1d6f 100644
--- a/bolt/lib/Profile/YAMLProfileWriter.cpp
+++ b/bolt/lib/Profile/YAMLProfileWriter.cpp
@@ -189,6 +189,7 @@ std::error_code YAMLProfileWriter::writeProfile(const RewriteInstance &RI) {
   BP.Header.Id = BuildID ? std::string(*BuildID) : "<unknown>";
   BP.Header.Origin = std::string(RI.getProfileReader()->getReaderName());
   BP.Header.IsDFSOrder = opts::ProfileUseDFS;
+  BP.Header.HashFunction = HashFunction::Default;
 
   StringSet<> EventNames = RI.getProfileReader()->getEventNames();
   if (!EventNames.empty()) {
diff --git a/bolt/test/X86/Inputs/blarge_profile_stale.std-hash.yaml b/bolt/test/X86/Inputs/blarge_profile_stale.std-hash.yaml
new file mode 100644
index 000000000000..d520a0d242bf
--- /dev/null
+++ b/bolt/test/X86/Inputs/blarge_profile_stale.std-hash.yaml
@@ -0,0 +1,56 @@
+---
+header:
+  profile-version: 1
+  binary-name:     'reader-yaml.test.tmp.exe'
+  binary-build-id: '<unknown>'
+  profile-flags:   [ lbr ]
+  profile-origin:  branch profile reader
+  profile-events:  ''
+  dfs-order:       false
+functions:
+  - name: SolveCubic
+    fid: 6
+    hash: 0xC6E9098E973BBE19
+    exec: 151
+    nblocks: 18
+    blocks:
+      - bid: 0
+        insns: 43
+        hash: 0xed4db287e71c0000
+        exec: 151
+        succ: [ { bid: 1, cnt: 151, mis: 2 }, { bid: 7, cnt: 0 } ]
+      - bid: 1
+        insns: 7
+        hash: 0x39330000e4560088
+        succ: [ { bid: 13, cnt: 151 }, { bid: 2, cnt: 0 } ]
+      - bid: 13
+        insns: 26
+        hash: 0xa9700000fe202a7
+        succ: [ { bid: 3, cnt: 89 }, { bid: 2, cnt: 10 } ]
+      - bid: 3
+        insns: 9
+        hash: 0x62391dad18a700a0
+        succ: [ { bid: 5, cnt: 151 } ]
+      - bid: 5
+        insns: 9
+        hash: 0x4d906d19ecec0111
+  - name: usqrt
+    fid: 7
+    hash: 0x8B62B1F9AD81EA35
+    exec: 20
+    nblocks: 6
+    blocks:
+      - bid: 0
+        insns: 4
+        hash: 0x1111111111111111
+        exec: 20
+        succ: [ { bid: 1, cnt: 0 } ]
+      - bid: 1
+        insns: 9
+        hash: 0x27e43a5e10cd0010
+        succ: [ { bid: 3, cnt: 320, mis: 171 }, { bid: 2, cnt: 0 } ]
+      - bid: 3
+        insns: 2
+        hash: 0x4db935b6471e0039
+        succ: [ { bid: 1, cnt: 300, mis: 33 }, { bid: 4, cnt: 20 } ]
+...
diff --git a/bolt/test/X86/Inputs/blarge_profile_stale.yaml b/bolt/test/X86/Inputs/blarge_profile_stale.yaml
index 43b75c99656f..ac46b37b56a1 100644
--- a/bolt/test/X86/Inputs/blarge_profile_stale.yaml
+++ b/bolt/test/X86/Inputs/blarge_profile_stale.yaml
@@ -7,6 +7,7 @@ header:
   profile-origin:  branch profile reader
   profile-events:  ''
   dfs-order:       false
+  hash-func:       xxh3
 functions:
   - name:            SolveCubic
     fid:             6
diff --git a/bolt/test/X86/reader-stale-yaml-std.test b/bolt/test/X86/reader-stale-yaml-std.test
new file mode 100644
index 000000000000..e0b6ca0645e1
--- /dev/null
+++ b/bolt/test/X86/reader-stale-yaml-std.test
@@ -0,0 +1,68 @@
+# This script checks that YamlProfileReader in llvm-bolt is reading data
+# correctly and stale data is corrected by profile inference.
+
+RUN: yaml2obj %p/Inputs/blarge.yaml &> %t.exe
+RUN: llvm-bolt %t.exe -o %t.null -b %p/Inputs/blarge_profile_stale.std-hash.yaml \
+RUN:   --print-cfg --print-only=usqrt,SolveCubic --infer-stale-profile=1 -v=1 \
+RUN:   2>&1 | FileCheck %s
+
+# Verify that yaml reader works as expected.
+CHECK: pre-processing profile using YAML profile reader
+CHECK: BOLT-INFO: YAML profile with hash: std::hash
+
+# Function "SolveCubic" has stale profile, since there is one jump in the
+# profile (from bid=13 to bid=2) which is not in the CFG in the binary. The test
+# verifies that the inference is able to match two blocks (bid=1 and bid=13)
+# using "loose" hashes and then correctly propagate the counts.
+
+CHECK: Binary Function "SolveCubic" after building cfg {
+CHECK:   State       : CFG constructed
+CHECK:   Address     : 0x400e00
+CHECK:   Size        : 0x368
+CHECK:   Section     : .text
+CHECK:   IsSimple    : 1
+CHECK:   BB Count    : 18
+CHECK:   Exec Count  : 151
+CHECK:   Branch Count: 552
+CHECK: }
+# Verify block counts.
+CHECK: .LBB00 (43 instructions, align : 1)
+CHECK:   Successors: .Ltmp[[#BB07:]] (mispreds: 0, count: 0), .LFT[[#BB01:]] (mispreds: 0, count: 151)
+CHECK: .LFT[[#BB01:]] (5 instructions, align : 1)
+CHECK:   Successors: .Ltmp[[#BB013:]] (mispreds: 0, count: 151), .LFT[[#BB02:]] (mispreds: 0, count: 0)
+CHECK: .Ltmp[[#BB03:]] (26 instructions, align : 1)
+CHECK:   Successors: .Ltmp[[#BB05:]] (mispreds: 0, count: 151), .LFT[[#BB04:]] (mispreds: 0, count: 0)
+CHECK: .Ltmp[[#BB05:]] (9 instructions, align : 1)
+CHECK: .Ltmp[[#BB013:]] (12 instructions, align : 1)
+CHECK:   Successors: .Ltmp[[#BB03:]] (mispreds: 0, count: 151)
+CHECK: End of Function "SolveCubic"
+
+# Function "usqrt" has stale profile, since the number of blocks in the profile
+# (nblocks=6) does not match the size of the CFG in the binary. The entry
+# block (bid=0) has an incorrect (missing) count, which should be inferred by
+# the algorithm.
+
+CHECK: Binary Function "usqrt" after building cfg {
+CHECK:   State       : CFG constructed
+CHECK:   Address     : 0x401170
+CHECK:   Size        : 0x43
+CHECK:   Section     : .text
+CHECK:   IsSimple    : 1
+CHECK:   BB Count    : 5
+CHECK:   Exec Count  : 20
+CHECK:   Branch Count: 640
+CHECK: }
+# Verify block counts.
+CHECK: .LBB01 (4 instructions, align : 1)
+CHECK:   Successors: .Ltmp[[#BB113:]] (mispreds: 0, count: 20)
+CHECK: .Ltmp[[#BB113:]] (9 instructions, align : 1)
+CHECK:   Successors: .Ltmp[[#BB112:]] (mispreds: 0, count: 320), .LFT[[#BB10:]] (mispreds: 0, count: 0)
+CHECK: .LFT[[#BB10:]] (2 instructions, align : 1)
+CHECK:   Successors: .Ltmp[[#BB112:]] (mispreds: 0, count: 0)
+CHECK: .Ltmp[[#BB112:]] (2 instructions, align : 1)
+CHECK:   Successors: .Ltmp[[#BB113:]] (mispreds: 0, count: 300), .LFT[[#BB11:]] (mispreds: 0, count: 20)
+CHECK: .LFT[[#BB11:]] (2 instructions, align : 1)
+CHECK: End of Function "usqrt"
+# Check the overall inference stats.
+CHECK: 2 out of 7 functions in the binary (28.6%) have non-empty execution profile
+CHECK: inferred profile for 2 (100.00% of profiled, 100.00% of stale) functions responsible for {{.*}} samples ({{.*}} out of {{.*}})
-- 
GitLab


From a439ef518dc0a30b85cf041cd3b83641ea78308f Mon Sep 17 00:00:00 2001
From: Fangrui Song <i@maskray.me>
Date: Mon, 11 Dec 2023 12:32:12 -0800
Subject: [PATCH 167/349] [ELF][test] Improve copy relocation/canonical PLT
 entry tests

---
 lld/test/ELF/x86-64-dyn-rel-error.s  | 52 +++++++++++++++++++++-------
 lld/test/ELF/x86-64-dyn-rel-error2.s | 14 --------
 lld/test/ELF/x86-64-reloc-32.s       |  3 --
 3 files changed, 39 insertions(+), 30 deletions(-)
 delete mode 100644 lld/test/ELF/x86-64-dyn-rel-error2.s

diff --git a/lld/test/ELF/x86-64-dyn-rel-error.s b/lld/test/ELF/x86-64-dyn-rel-error.s
index 8f41f1493dde..edc2875c6fa6 100644
--- a/lld/test/ELF/x86-64-dyn-rel-error.s
+++ b/lld/test/ELF/x86-64-dyn-rel-error.s
@@ -1,17 +1,43 @@
-// REQUIRES: x86
-// RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o
-// RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %p/Inputs/shared.s -o %t2.o
-// RUN: ld.lld %t2.o -shared -o %t2.so
-// RUN: not ld.lld -shared %t.o %t2.so -o /dev/null 2>&1 | FileCheck %s
+# REQUIRES: x86
+# RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o %t.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64 %p/Inputs/shared.s -o %t2.o
+# RUN: ld.lld %t2.o -shared -o %t2.so --threads=1
+# RUN: not ld.lld -pie %t.o %t2.so -o /dev/null --threads=1 2>&1 | FileCheck %s
+# RUN: not ld.lld -shared %t.o %t2.so -o /dev/null --threads=1 2>&1 | FileCheck %s --check-prefixes=CHECK,SHARED
 
-        .global _start
-_start:
-        .data
-        .long zed
+# CHECK:      error: relocation R_X86_64_32 cannot be used against symbol 'zed'; recompile with -fPIC
+# CHECK-NEXT: >>> defined in {{.*}}.so
+# CHECK-NEXT: >>> referenced by {{.*}}.o:(.data+0x0)
+# CHECK-EMPTY:
+# CHECK-NEXT: error: relocation R_X86_64_PC32 cannot be used against symbol 'zed'; recompile with -fPIC
+# CHECK-NEXT: >>> defined in {{.*}}.so
+# CHECK-NEXT: >>> referenced by {{.*}}.o:(.data+0x4)
+# CHECK-EMPTY:
+# CHECK-NEXT: error: relocation R_X86_64_64 cannot be used against symbol '_start'; recompile with -fPIC
+# SHARED:     error: relocation R_X86_64_64 cannot be used against symbol 'main'; recompile with -fPIC
+# SHARED:     error: relocation R_X86_64_64 cannot be used against symbol 'data'; recompile with -fPIC
+# CHECK-NOT:  error:
+
+# RUN: ld.lld --noinhibit-exec %t.o %t2.so -o /dev/null 2>&1 | FileCheck --check-prefix=WARN %s
+# RUN: not ld.lld --export-dynamic --unresolved-symbols=ignore-all %t.o -o /dev/null 2>&1 | FileCheck --check-prefix=WARN %s
 
-// CHECK: error: relocation R_X86_64_32 cannot be used against symbol 'zed'; recompile with -fPIC
+# WARN: relocation R_X86_64_32 cannot be used against symbol 'zed'; recompile with -fPIC
+# WARN: relocation R_X86_64_PC32 cannot be used against symbol 'zed'; recompile with -fPIC
+
+        .global _start, main, data
+        .type main, @function
+        .type data, @object
+_start:
+  ret
+main:
+  ret
 
-// RUN: ld.lld --noinhibit-exec %t.o %t2.so -o /dev/null 2>&1 | FileCheck --check-prefix=WARN %s
-// RUN: not ld.lld --export-dynamic --unresolved-symbols=ignore-all %t.o -o /dev/null 2>&1 | FileCheck --check-prefix=WARN %s
+.data
+data:
+.long zed
+.long zed - .
 
-// WARN: relocation R_X86_64_32 cannot be used against symbol 'zed'; recompile with -fPIC
+.rodata
+.quad _start
+.quad main
+.quad data
diff --git a/lld/test/ELF/x86-64-dyn-rel-error2.s b/lld/test/ELF/x86-64-dyn-rel-error2.s
deleted file mode 100644
index 853e61faef68..000000000000
--- a/lld/test/ELF/x86-64-dyn-rel-error2.s
+++ /dev/null
@@ -1,14 +0,0 @@
-// REQUIRES: x86
-// RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o
-// RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %p/Inputs/shared.s -o %t2.o
-// RUN: ld.lld %t2.o -shared -o %t2.so
-// RUN: not ld.lld -shared %t.o %t2.so -o /dev/null 2>&1 | FileCheck %s
-
-// CHECK: error: relocation R_X86_64_PC32 cannot be used against symbol 'zed'; recompile with -fPIC
-// CHECK: >>> defined in {{.*}}.so
-// CHECK: >>> referenced by {{.*}}.o:(.data+0x0)
-
-        .global _start
-_start:
-        .data
-        .long zed - .
diff --git a/lld/test/ELF/x86-64-reloc-32.s b/lld/test/ELF/x86-64-reloc-32.s
index 70a46301ad24..bf2fc26a5820 100644
--- a/lld/test/ELF/x86-64-reloc-32.s
+++ b/lld/test/ELF/x86-64-reloc-32.s
@@ -1,9 +1,6 @@
 # REQUIRES: x86
 # RUN: rm -rf %t && split-file %s %t
-
-## Check recompile with -fPIC error message
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %t/shared.s -o %t/shared.o
-# RUN: not ld.lld -shared %t/shared.o -o /dev/null 2>&1 | FileCheck %s
 
 # CHECK: error: relocation R_X86_64_32 cannot be used against symbol '_shared'; recompile with -fPIC
 # CHECK: >>> defined in {{.*}}
-- 
GitLab


From 06b3144c3f533c82ee9ae6afa68ff41566eb2df5 Mon Sep 17 00:00:00 2001
From: Peter Klausler <35819229+klausler@users.noreply.github.com>
Date: Mon, 11 Dec 2023 12:32:29 -0800
Subject: [PATCH 168/349] =?UTF-8?q?[flang][runtime]=20Clear=20last=20recor?=
 =?UTF-8?q?d=20in=20internal=20WRITE=20even=20if=20nothing=20=E2=80=A6=20(?=
 =?UTF-8?q?#74528)?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

…was written

At the end of an internal output statement, The I/O runtime fills (the
remainder of) the current record with blanks if it's the only record or
if anything had been written to it. This turns out to be wrong in the
case of a format that ends with an explicit advance to the next record,
which needs to be cleared even if nothing has been written.

Fixes llvm-test-suite/Fortran/gfortran/regression/arrayio_1.f90.
---
 flang/runtime/internal-unit.cpp | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/flang/runtime/internal-unit.cpp b/flang/runtime/internal-unit.cpp
index aa7130f3a6a5..e3fffaa6f378 100644
--- a/flang/runtime/internal-unit.cpp
+++ b/flang/runtime/internal-unit.cpp
@@ -43,11 +43,9 @@ InternalDescriptorUnit<DIR>::InternalDescriptorUnit(
 
 template <Direction DIR> void InternalDescriptorUnit<DIR>::EndIoStatement() {
   if constexpr (DIR == Direction::Output) {
-    // Clear the remainder of the current record if anything was written
-    // to it, or if it is the only record.
+    // Clear the remainder of the current record.
     auto end{endfileRecordNumber.value_or(0)};
-    if (currentRecordNumber < end &&
-        (end == 2 || furthestPositionInRecord > 0)) {
+    if (currentRecordNumber < end) {
       BlankFillOutputRecord();
     }
   }
-- 
GitLab


From 0d71df4e6e88a707d5aa8c7c480248d0fbde112e Mon Sep 17 00:00:00 2001
From: Peter Klausler <35819229+klausler@users.noreply.github.com>
Date: Mon, 11 Dec 2023 12:38:39 -0800
Subject: [PATCH 169/349] [flang][runtime] Delete CharacterAssign() (#74621)

Lowering doesn't use it, and won't need it in the future; it emits
in-line code for conversions and for assignments to scalars, and uses
the general Assign() routine for arrays.
---
 flang/include/flang/Runtime/character.h |  11 --
 flang/runtime/character.cpp             | 142 ------------------------
 2 files changed, 153 deletions(-)

diff --git a/flang/include/flang/Runtime/character.h b/flang/include/flang/Runtime/character.h
index 24f26920bdd2..768de75b639c 100644
--- a/flang/include/flang/Runtime/character.h
+++ b/flang/include/flang/Runtime/character.h
@@ -44,17 +44,6 @@ void RTNAME(CharacterConcatenate)(Descriptor &accumulator,
 void RTNAME(CharacterConcatenateScalar1)(
     Descriptor &accumulator, const char *from, std::size_t chars);
 
-// Copies the value(s) of 'rhs' to 'lhs'.  Handles reallocation,
-// truncation, or padding ss necessary.  Crashes when not conforming and
-// the LHS is not allocatable.  Assumes independence of data.
-// The LHS and RHS need not have the same kind of character;
-// so when the LHS is a deallocated allocatable temporary result, this
-// function can be used as a simple conversion routine.
-// Call MoveAlloc() instead as an optimization when a temporary value is
-// being assigned to a deferred-length allocatable.
-void RTNAME(CharacterAssign)(Descriptor &lhs, const Descriptor &rhs,
-    const char *sourceFile = nullptr, int sourceLine = 0);
-
 // CHARACTER comparisons.  The kinds must match.  Like std::memcmp(),
 // the result is less than zero, zero, or greater than zero if the first
 // argument is less than the second, equal to the second, or greater than
diff --git a/flang/runtime/character.cpp b/flang/runtime/character.cpp
index 571f64ec42f4..2afde7cd5e83 100644
--- a/flang/runtime/character.cpp
+++ b/flang/runtime/character.cpp
@@ -629,148 +629,6 @@ void RTNAME(CharacterConcatenateScalar1)(
   FreeMemory(old);
 }
 
-void RTNAME(CharacterAssign)(Descriptor &lhs, const Descriptor &rhs,
-    const char *sourceFile, int sourceLine) {
-  Terminator terminator{sourceFile, sourceLine};
-  int rank{lhs.rank()};
-  RUNTIME_CHECK(terminator, rhs.rank() == 0 || rhs.rank() == rank);
-  SubscriptValue ub[maxRank], lhsAt[maxRank], rhsAt[maxRank];
-  SubscriptValue elements{1};
-  std::size_t lhsBytes{lhs.ElementBytes()};
-  std::size_t rhsBytes{rhs.ElementBytes()};
-  bool reallocate{lhs.IsAllocatable() &&
-      (lhs.raw().base_addr == nullptr || lhsBytes != rhsBytes)};
-  for (int j{0}; j < rank; ++j) {
-    lhsAt[j] = lhs.GetDimension(j).LowerBound();
-    if (rhs.rank() > 0) {
-      SubscriptValue lhsExt{lhs.GetDimension(j).Extent()};
-      SubscriptValue rhsExt{rhs.GetDimension(j).Extent()};
-      ub[j] = lhsAt[j] + rhsExt - 1;
-      if (lhsExt != rhsExt) {
-        if (lhs.IsAllocatable()) {
-          reallocate = true;
-        } else {
-          terminator.Crash("Character array assignment: operands are not "
-                           "conforming on dimension %d (%jd != %jd)",
-              j + 1, static_cast<std::intmax_t>(lhsExt),
-              static_cast<std::intmax_t>(rhsExt));
-        }
-      }
-      rhsAt[j] = rhs.GetDimension(j).LowerBound();
-    } else {
-      ub[j] = lhs.GetDimension(j).UpperBound();
-    }
-    elements *= ub[j] - lhsAt[j] + 1;
-  }
-  void *old{nullptr};
-  if (reallocate) {
-    old = lhs.raw().base_addr;
-    lhs.set_base_addr(nullptr);
-    lhs.raw().elem_len = lhsBytes = rhsBytes;
-    if (rhs.rank() > 0) {
-      // When the RHS is not scalar, the LHS acquires its bounds.
-      for (int j{0}; j < rank; ++j) {
-        lhsAt[j] = rhsAt[j];
-        ub[j] = rhs.GetDimension(j).UpperBound();
-        lhs.GetDimension(j).SetBounds(lhsAt[j], ub[j]);
-      }
-    }
-    RUNTIME_CHECK(terminator, lhs.Allocate() == CFI_SUCCESS);
-  }
-  switch (lhs.raw().type) {
-  case CFI_type_char:
-    switch (rhs.raw().type) {
-    case CFI_type_char:
-      for (; elements-- > 0;
-           lhs.IncrementSubscripts(lhsAt), rhs.IncrementSubscripts(rhsAt)) {
-        CopyAndPad(lhs.Element<char>(lhsAt), rhs.Element<char>(rhsAt), lhsBytes,
-            rhsBytes);
-      }
-      break;
-    case CFI_type_char16_t:
-      for (; elements-- > 0;
-           lhs.IncrementSubscripts(lhsAt), rhs.IncrementSubscripts(rhsAt)) {
-        CopyAndPad(lhs.Element<char>(lhsAt), rhs.Element<char16_t>(rhsAt),
-            lhsBytes, rhsBytes >> 1);
-      }
-      break;
-    case CFI_type_char32_t:
-      for (; elements-- > 0;
-           lhs.IncrementSubscripts(lhsAt), rhs.IncrementSubscripts(rhsAt)) {
-        CopyAndPad(lhs.Element<char>(lhsAt), rhs.Element<char32_t>(rhsAt),
-            lhsBytes, rhsBytes >> 2);
-      }
-      break;
-    default:
-      terminator.Crash(
-          "RHS of character assignment does not have a character type");
-    }
-    break;
-  case CFI_type_char16_t:
-    switch (rhs.raw().type) {
-    case CFI_type_char:
-      for (; elements-- > 0;
-           lhs.IncrementSubscripts(lhsAt), rhs.IncrementSubscripts(rhsAt)) {
-        CopyAndPad(lhs.Element<char16_t>(lhsAt), rhs.Element<char>(rhsAt),
-            lhsBytes >> 1, rhsBytes);
-      }
-      break;
-    case CFI_type_char16_t:
-      for (; elements-- > 0;
-           lhs.IncrementSubscripts(lhsAt), rhs.IncrementSubscripts(rhsAt)) {
-        CopyAndPad(lhs.Element<char16_t>(lhsAt), rhs.Element<char16_t>(rhsAt),
-            lhsBytes >> 1, rhsBytes >> 1);
-      }
-      break;
-    case CFI_type_char32_t:
-      for (; elements-- > 0;
-           lhs.IncrementSubscripts(lhsAt), rhs.IncrementSubscripts(rhsAt)) {
-        CopyAndPad(lhs.Element<char16_t>(lhsAt), rhs.Element<char32_t>(rhsAt),
-            lhsBytes >> 1, rhsBytes >> 2);
-      }
-      break;
-    default:
-      terminator.Crash(
-          "RHS of character assignment does not have a character type");
-    }
-    break;
-  case CFI_type_char32_t:
-    switch (rhs.raw().type) {
-    case CFI_type_char:
-      for (; elements-- > 0;
-           lhs.IncrementSubscripts(lhsAt), rhs.IncrementSubscripts(rhsAt)) {
-        CopyAndPad(lhs.Element<char32_t>(lhsAt), rhs.Element<char>(rhsAt),
-            lhsBytes >> 2, rhsBytes);
-      }
-      break;
-    case CFI_type_char16_t:
-      for (; elements-- > 0;
-           lhs.IncrementSubscripts(lhsAt), rhs.IncrementSubscripts(rhsAt)) {
-        CopyAndPad(lhs.Element<char32_t>(lhsAt), rhs.Element<char16_t>(rhsAt),
-            lhsBytes >> 2, rhsBytes >> 1);
-      }
-      break;
-    case CFI_type_char32_t:
-      for (; elements-- > 0;
-           lhs.IncrementSubscripts(lhsAt), rhs.IncrementSubscripts(rhsAt)) {
-        CopyAndPad(lhs.Element<char32_t>(lhsAt), rhs.Element<char32_t>(rhsAt),
-            lhsBytes >> 2, rhsBytes >> 2);
-      }
-      break;
-    default:
-      terminator.Crash(
-          "RHS of character assignment does not have a character type");
-    }
-    break;
-  default:
-    terminator.Crash(
-        "LHS of character assignment does not have a character type");
-  }
-  if (reallocate) {
-    FreeMemory(old);
-  }
-}
-
 int RTNAME(CharacterCompareScalar)(const Descriptor &x, const Descriptor &y) {
   Terminator terminator{__FILE__, __LINE__};
   RUNTIME_CHECK(terminator, x.rank() == 0);
-- 
GitLab


From bf1c89c3432e74726d49175a34daa2085dc57430 Mon Sep 17 00:00:00 2001
From: Peter Klausler <35819229+klausler@users.noreply.github.com>
Date: Mon, 11 Dec 2023 12:45:04 -0800
Subject: [PATCH 170/349] =?UTF-8?q?[flang][runtime]=20Don't=20use=20endfil?=
 =?UTF-8?q?e=20record=20number=20for=20EOF=20detection=20on=E2=80=A6=20(#7?=
 =?UTF-8?q?4640)?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

… input

The current EOF detection method (IsAtEOF()) depends on comparing the
current record number with the record number of the endfile record, if
it is known, which it is for units that have been written and then
rewound for input. For formatted input, this is wrong in the case of a
unit written with in-band newline characters. Rather than scan output
data to count newlines, it's best to just organically determine EOF by
detecting a failed or short read(), as we would have done anyway had the
endfile record number not been known. (I considered resetting the
endfile record number at the point of a REWIND, but not all rewinds are
followed by input; it seems wiser to defer the resetting until an actual
READ takes place.)

Fixes llvm-test-suite/Fortran/gfortran/regression/backslash_2.f90
---
 flang/runtime/unit.cpp | 25 +++++++++++++++----------
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/flang/runtime/unit.cpp b/flang/runtime/unit.cpp
index dfe61263feb8..962f97bf260c 100644
--- a/flang/runtime/unit.cpp
+++ b/flang/runtime/unit.cpp
@@ -440,6 +440,14 @@ bool ExternalFileUnit::BeginReadingRecord(IoErrorHandler &handler) {
   RUNTIME_CHECK(handler, direction_ == Direction::Input);
   if (!beganReadingRecord_) {
     beganReadingRecord_ = true;
+    // Don't use IsAtEOF() to check for an EOF condition here, just detect
+    // it from a failed or short read from the file.  IsAtEOF() could be
+    // wrong for formatted input if actual newline characters had been
+    // written in-band by previous WRITEs before a REWIND.  In fact,
+    // now that we know that the unit is being used for input (again),
+    // it's best to reset endfileRecordNumber and ensure IsAtEOF() will
+    // now be true on return only if it gets set by HitEndOnRead().
+    endfileRecordNumber.reset();
     if (access == Access::Direct) {
       CheckDirectAccess(handler);
       auto need{static_cast<std::size_t>(recordOffsetInFrame_ + *openRecl)};
@@ -452,17 +460,13 @@ bool ExternalFileUnit::BeginReadingRecord(IoErrorHandler &handler) {
       }
     } else {
       recordLength.reset();
-      if (IsAtEOF()) {
-        handler.SignalEnd();
-      } else {
-        RUNTIME_CHECK(handler, isUnformatted.has_value());
-        if (*isUnformatted) {
-          if (access == Access::Sequential) {
-            BeginSequentialVariableUnformattedInputRecord(handler);
-          }
-        } else { // formatted sequential or stream
-          BeginVariableFormattedInputRecord(handler);
+      RUNTIME_CHECK(handler, isUnformatted.has_value());
+      if (*isUnformatted) {
+        if (access == Access::Sequential) {
+          BeginSequentialVariableUnformattedInputRecord(handler);
         }
+      } else { // formatted sequential or stream
+        BeginVariableFormattedInputRecord(handler);
       }
     }
   }
@@ -727,6 +731,7 @@ void ExternalFileUnit::EndIoStatement() {
 
 void ExternalFileUnit::BeginSequentialVariableUnformattedInputRecord(
     IoErrorHandler &handler) {
+  RUNTIME_CHECK(handler, access == Access::Sequential);
   std::int32_t header{0}, footer{0};
   std::size_t need{recordOffsetInFrame_ + sizeof header};
   std::size_t got{ReadFrame(frameOffsetInFile_, need, handler)};
-- 
GitLab


From 0d44c9f99a7d9d9444d1656ca52fa0784c711680 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@sifive.com>
Date: Mon, 11 Dec 2023 12:35:40 -0800
Subject: [PATCH 171/349] [RISCV] Shorten diagnostic a bit.

The "to be enabled" seemed unnecessary.
---
 clang/include/clang/Basic/DiagnosticSemaKinds.td                | 2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index 0b53c6dce810..94e97a891bae 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -12002,7 +12002,7 @@ def warn_tcb_enforcement_violation : Warning<
 
 // RISC-V builtin required extension warning
 def err_riscv_builtin_requires_extension : Error<
-  "builtin requires%select{| at least one of the following extensions to be enabled}0: %1">;
+  "builtin requires%select{| at least one of the following extensions}0: %1">;
 def err_riscv_builtin_invalid_lmul : Error<
   "LMUL argument must be in the range [0,3] or [5,7]">;
 def err_riscv_type_requires_extension : Error<
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
index 1a29acbf3ba9..6ec9b0579976 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
@@ -11,7 +11,7 @@
 // CHECK-RV64V-NEXT:    ret i32 [[CONV]]
 //
 
-// CHECK-RV64-ERR: error: builtin requires at least one of the following extensions to be enabled: 'Zve32x'
+// CHECK-RV64-ERR: error: builtin requires at least one of the following extensions: 'Zve32x'
 
 int test() {
   return __builtin_rvv_vsetvli(1, 0, 0);
-- 
GitLab


From 4a11222f50dbe95e61c7cd7ddc2de8b3e87cddd7 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@sifive.com>
Date: Mon, 11 Dec 2023 12:41:22 -0800
Subject: [PATCH 172/349] [RISCV] Correct the SEW=64 MUL diagnostic to refer to
 V as an extension.

This makes it consistent with other builtins that require a specific
extension.
---
 clang/lib/Sema/SemaChecking.cpp        |   2 +-
 clang/test/Sema/riscv-vector-v-check.c | 128 ++++++++++++-------------
 2 files changed, 65 insertions(+), 65 deletions(-)

diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 4c5187774233..cdb6e9584e95 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5219,7 +5219,7 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
     if (Context.getTypeSize(Info.ElementType) == 64 && !TI.hasFeature("v"))
       return Diag(TheCall->getBeginLoc(),
                   diag::err_riscv_builtin_requires_extension)
-             << /* IsExtension */ false << TheCall->getSourceRange() << "v";
+             << /* IsExtension */ true << TheCall->getSourceRange() << "v";
 
     break;
   }
diff --git a/clang/test/Sema/riscv-vector-v-check.c b/clang/test/Sema/riscv-vector-v-check.c
index 8faa92c7b3cf..a1091c1e5d66 100644
--- a/clang/test/Sema/riscv-vector-v-check.c
+++ b/clang/test/Sema/riscv-vector-v-check.c
@@ -4,194 +4,194 @@
 #include <riscv_vector.h>
 
 vint64m1_t test_vsmul_vv_i64m1(vint64m1_t op1, vint64m1_t op2, size_t vl) {
-  return __riscv_vsmul_vv_i64m1(op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vsmul_vv_i64m1(op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m1_t test_vsmul_vx_i64m1(vint64m1_t op1, int64_t op2, size_t vl) {
-  return __riscv_vsmul_vx_i64m1(op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vsmul_vx_i64m1(op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m2_t test_vsmul_vv_i64m2(vint64m2_t op1, vint64m2_t op2, size_t vl) {
-  return __riscv_vsmul_vv_i64m2(op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vsmul_vv_i64m2(op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m2_t test_vsmul_vx_i64m2(vint64m2_t op1, int64_t op2, size_t vl) {
-  return __riscv_vsmul_vx_i64m2(op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vsmul_vx_i64m2(op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m4_t test_vsmul_vv_i64m4(vint64m4_t op1, vint64m4_t op2, size_t vl) {
-  return __riscv_vsmul_vv_i64m4(op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vsmul_vv_i64m4(op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m4_t test_vsmul_vx_i64m4(vint64m4_t op1, int64_t op2, size_t vl) {
-  return __riscv_vsmul_vx_i64m4(op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vsmul_vx_i64m4(op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m8_t test_vsmul_vv_i64m8(vint64m8_t op1, vint64m8_t op2, size_t vl) {
-  return __riscv_vsmul_vv_i64m8(op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vsmul_vv_i64m8(op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m8_t test_vsmul_vx_i64m8(vint64m8_t op1, int64_t op2, size_t vl) {
-  return __riscv_vsmul_vx_i64m8(op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vsmul_vx_i64m8(op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m1_t test_vsmul_vv_i64m1_m(vbool64_t mask, vint64m1_t op1, vint64m1_t op2, size_t vl) {
-  return __riscv_vsmul_vv_i64m1_m(mask, op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vsmul_vv_i64m1_m(mask, op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m1_t test_vsmul_vx_i64m1_m(vbool64_t mask, vint64m1_t op1, int64_t op2, size_t vl) {
-  return __riscv_vsmul_vx_i64m1_m(mask, op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vsmul_vx_i64m1_m(mask, op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m2_t test_vsmul_vv_i64m2_m(vbool32_t mask, vint64m2_t op1, vint64m2_t op2, size_t vl) {
-  return __riscv_vsmul_vv_i64m2_m(mask, op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vsmul_vv_i64m2_m(mask, op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m2_t test_vsmul_vx_i64m2_m(vbool32_t mask, vint64m2_t op1, int64_t op2, size_t vl) {
-  return __riscv_vsmul_vx_i64m2_m(mask, op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vsmul_vx_i64m2_m(mask, op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m4_t test_vsmul_vv_i64m4_m(vbool16_t mask, vint64m4_t op1, vint64m4_t op2, size_t vl) {
-  return __riscv_vsmul_vv_i64m4_m(mask, op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vsmul_vv_i64m4_m(mask, op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m4_t test_vsmul_vx_i64m4_m(vbool16_t mask, vint64m4_t op1, int64_t op2, size_t vl) {
-  return __riscv_vsmul_vx_i64m4_m(mask, op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vsmul_vx_i64m4_m(mask, op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m8_t test_vsmul_vv_i64m8_m(vbool8_t mask, vint64m8_t op1, vint64m8_t op2, size_t vl) {
-  return __riscv_vsmul_vv_i64m8_m(mask, op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vsmul_vv_i64m8_m(mask, op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m8_t test_vsmul_vx_i64m8_m(vbool8_t mask, vint64m8_t op1, int64_t op2, size_t vl) {
-  return __riscv_vsmul_vx_i64m8_m(mask, op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vsmul_vx_i64m8_m(mask, op1, op2, __RISCV_VXRM_RNU, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m1_t test_vmulh_vv_i64m1(vint64m1_t op1, vint64m1_t op2, size_t vl) {
-  return __riscv_vmulh_vv_i64m1(op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulh_vv_i64m1(op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m1_t test_vmulh_vx_i64m1(vint64m1_t op1, int64_t op2, size_t vl) {
-  return __riscv_vmulh_vx_i64m1(op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulh_vx_i64m1(op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m2_t test_vmulh_vv_i64m2(vint64m2_t op1, vint64m2_t op2, size_t vl) {
-  return __riscv_vmulh_vv_i64m2(op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulh_vv_i64m2(op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m2_t test_vmulh_vx_i64m2(vint64m2_t op1, int64_t op2, size_t vl) {
-  return __riscv_vmulh_vx_i64m2(op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulh_vx_i64m2(op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m4_t test_vmulh_vv_i64m4(vint64m4_t op1, vint64m4_t op2, size_t vl) {
-  return __riscv_vmulh_vv_i64m4(op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulh_vv_i64m4(op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m4_t test_vmulh_vx_i64m4(vint64m4_t op1, int64_t op2, size_t vl) {
-  return __riscv_vmulh_vx_i64m4(op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulh_vx_i64m4(op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m8_t test_vmulh_vv_i64m8(vint64m8_t op1, vint64m8_t op2, size_t vl) {
-  return __riscv_vmulh_vv_i64m8(op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulh_vv_i64m8(op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m8_t test_vmulh_vx_i64m8(vint64m8_t op1, int64_t op2, size_t vl) {
-  return __riscv_vmulh_vx_i64m8(op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulh_vx_i64m8(op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m1_t test_vmulh_vv_i64m1_m(vbool64_t mask, vint64m1_t op1, vint64m1_t op2, size_t vl) {
-  return __riscv_vmulh_vv_i64m1_m(mask, op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulh_vv_i64m1_m(mask, op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m1_t test_vmulh_vx_i64m1_m(vbool64_t mask, vint64m1_t op1, int64_t op2, size_t vl) {
-  return __riscv_vmulh_vx_i64m1_m(mask, op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulh_vx_i64m1_m(mask, op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m2_t test_vmulh_vv_i64m2_m(vbool32_t mask, vint64m2_t op1, vint64m2_t op2, size_t vl) {
-  return __riscv_vmulh_vv_i64m2_m(mask, op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulh_vv_i64m2_m(mask, op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m2_t test_vmulh_vx_i64m2_m(vbool32_t mask, vint64m2_t op1, int64_t op2, size_t vl) {
-  return __riscv_vmulh_vx_i64m2_m(mask, op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulh_vx_i64m2_m(mask, op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m4_t test_vmulh_vv_i64m4_m(vbool16_t mask, vint64m4_t op1, vint64m4_t op2, size_t vl) {
-  return __riscv_vmulh_vv_i64m4_m(mask, op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulh_vv_i64m4_m(mask, op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m4_t test_vmulh_vx_i64m4_m(vbool16_t mask, vint64m4_t op1, int64_t op2, size_t vl) {
-  return __riscv_vmulh_vx_i64m4_m(mask, op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulh_vx_i64m4_m(mask, op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m8_t test_vmulh_vv_i64m8_m(vbool8_t mask, vint64m8_t op1, vint64m8_t op2, size_t vl) {
-  return __riscv_vmulh_vv_i64m8_m(mask, op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulh_vv_i64m8_m(mask, op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m8_t test_vmulh_vx_i64m8_m(vbool8_t mask, vint64m8_t op1, int64_t op2, size_t vl) {
-  return __riscv_vmulh_vx_i64m8_m(mask, op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulh_vx_i64m8_m(mask, op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vuint64m1_t test_vmulhu_vv_u64m1(vuint64m1_t op1, vuint64m1_t op2, size_t vl) {
-  return __riscv_vmulhu_vv_u64m1(op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhu_vv_u64m1(op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vuint64m1_t test_vmulhu_vx_u64m1(vuint64m1_t op1, uint64_t op2, size_t vl) {
-  return __riscv_vmulhu_vx_u64m1(op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhu_vx_u64m1(op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vuint64m2_t test_vmulhu_vv_u64m2(vuint64m2_t op1, vuint64m2_t op2, size_t vl) {
-  return __riscv_vmulhu_vv_u64m2(op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhu_vv_u64m2(op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vuint64m2_t test_vmulhu_vx_u64m2(vuint64m2_t op1, uint64_t op2, size_t vl) {
-  return __riscv_vmulhu_vx_u64m2(op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhu_vx_u64m2(op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vuint64m4_t test_vmulhu_vv_u64m4(vuint64m4_t op1, vuint64m4_t op2, size_t vl) {
-  return __riscv_vmulhu_vv_u64m4(op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhu_vv_u64m4(op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vuint64m4_t test_vmulhu_vx_u64m4(vuint64m4_t op1, uint64_t op2, size_t vl) {
-  return __riscv_vmulhu_vx_u64m4(op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhu_vx_u64m4(op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vuint64m8_t test_vmulhu_vv_u64m8(vuint64m8_t op1, vuint64m8_t op2, size_t vl) {
-  return __riscv_vmulhu_vv_u64m8(op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhu_vv_u64m8(op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vuint64m8_t test_vmulhu_vx_u64m8(vuint64m8_t op1, uint64_t op2, size_t vl) {
-  return __riscv_vmulhu_vx_u64m8(op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhu_vx_u64m8(op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vuint64m1_t test_vmulhu_vv_u64m1_m(vbool64_t mask, vuint64m1_t op1, vuint64m1_t op2, size_t vl) {
-  return __riscv_vmulhu_vv_u64m1_m(mask, op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhu_vv_u64m1_m(mask, op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vuint64m1_t test_vmulhu_vx_u64m1_m(vbool64_t mask, vuint64m1_t op1, uint64_t op2, size_t vl) {
-  return __riscv_vmulhu_vx_u64m1_m(mask, op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhu_vx_u64m1_m(mask, op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vuint64m2_t test_vmulhu_vv_u64m2_m(vbool32_t mask, vuint64m2_t op1, vuint64m2_t op2, size_t vl) {
-  return __riscv_vmulhu_vv_u64m2_m(mask, op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhu_vv_u64m2_m(mask, op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vuint64m2_t test_vmulhu_vx_u64m2_m(vbool32_t mask, vuint64m2_t op1, uint64_t op2, size_t vl) {
-  return __riscv_vmulhu_vx_u64m2_m(mask, op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhu_vx_u64m2_m(mask, op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vuint64m4_t test_vmulhu_vv_u64m4_m(vbool16_t mask, vuint64m4_t op1, vuint64m4_t op2, size_t vl) {
-  return __riscv_vmulhu_vv_u64m4_m(mask, op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhu_vv_u64m4_m(mask, op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vuint64m4_t test_vmulhu_vx_u64m4_m(vbool16_t mask, vuint64m4_t op1, uint64_t op2, size_t vl) {
-  return __riscv_vmulhu_vx_u64m4_m(mask, op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhu_vx_u64m4_m(mask, op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vuint64m8_t test_vmulhu_vv_u64m8_m(vbool8_t mask, vuint64m8_t op1, vuint64m8_t op2, size_t vl) {
-  return __riscv_vmulhu_vv_u64m8_m(mask, op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhu_vv_u64m8_m(mask, op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vuint64m8_t test_vmulhu_vx_u64m8_m(vbool8_t mask, vuint64m8_t op1, uint64_t op2, size_t vl) {
-  return __riscv_vmulhu_vx_u64m8_m(mask, op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhu_vx_u64m8_m(mask, op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m1_t test_vmulhsu_vv_i64m1(vint64m1_t op1, vuint64m1_t op2, size_t vl) {
-  return __riscv_vmulhsu_vv_i64m1(op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhsu_vv_i64m1(op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m1_t test_vmulhsu_vx_i64m1(vint64m1_t op1, uint64_t op2, size_t vl) {
-  return __riscv_vmulhsu_vx_i64m1(op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhsu_vx_i64m1(op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m2_t test_vmulhsu_vv_i64m2(vint64m2_t op1, vuint64m2_t op2, size_t vl) {
-  return __riscv_vmulhsu_vv_i64m2(op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhsu_vv_i64m2(op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m2_t test_vmulhsu_vx_i64m2(vint64m2_t op1, uint64_t op2, size_t vl) {
-  return __riscv_vmulhsu_vx_i64m2(op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhsu_vx_i64m2(op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m4_t test_vmulhsu_vv_i64m4(vint64m4_t op1, vuint64m4_t op2, size_t vl) {
-  return __riscv_vmulhsu_vv_i64m4(op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhsu_vv_i64m4(op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m4_t test_vmulhsu_vx_i64m4(vint64m4_t op1, uint64_t op2, size_t vl) {
-  return __riscv_vmulhsu_vx_i64m4(op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhsu_vx_i64m4(op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m8_t test_vmulhsu_vv_i64m8(vint64m8_t op1, vuint64m8_t op2, size_t vl) {
-  return __riscv_vmulhsu_vv_i64m8(op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhsu_vv_i64m8(op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m8_t test_vmulhsu_vx_i64m8(vint64m8_t op1, uint64_t op2, size_t vl) {
-  return __riscv_vmulhsu_vx_i64m8(op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhsu_vx_i64m8(op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m1_t test_vmulhsu_vv_i64m1_m(vbool64_t mask, vint64m1_t op1, vuint64m1_t op2, size_t vl) {
-  return __riscv_vmulhsu_vv_i64m1_m(mask, op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhsu_vv_i64m1_m(mask, op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m1_t test_vmulhsu_vx_i64m1_m(vbool64_t mask, vint64m1_t op1, uint64_t op2, size_t vl) {
-  return __riscv_vmulhsu_vx_i64m1_m(mask, op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhsu_vx_i64m1_m(mask, op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m2_t test_vmulhsu_vv_i64m2_m(vbool32_t mask, vint64m2_t op1, vuint64m2_t op2, size_t vl) {
-  return __riscv_vmulhsu_vv_i64m2_m(mask, op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhsu_vv_i64m2_m(mask, op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m2_t test_vmulhsu_vx_i64m2_m(vbool32_t mask, vint64m2_t op1, uint64_t op2, size_t vl) {
-  return __riscv_vmulhsu_vx_i64m2_m(mask, op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhsu_vx_i64m2_m(mask, op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m4_t test_vmulhsu_vv_i64m4_m(vbool16_t mask, vint64m4_t op1, vuint64m4_t op2, size_t vl) {
-  return __riscv_vmulhsu_vv_i64m4_m(mask, op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhsu_vv_i64m4_m(mask, op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m4_t test_vmulhsu_vx_i64m4_m(vbool16_t mask, vint64m4_t op1, uint64_t op2, size_t vl) {
-  return __riscv_vmulhsu_vx_i64m4_m(mask, op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhsu_vx_i64m4_m(mask, op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m8_t test_vmulhsu_vv_i64m8_m(vbool8_t mask, vint64m8_t op1, vuint64m8_t op2, size_t vl) {
-  return __riscv_vmulhsu_vv_i64m8_m(mask, op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhsu_vv_i64m8_m(mask, op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
 vint64m8_t test_vmulhsu_vx_i64m8_m(vbool8_t mask, vint64m8_t op1, uint64_t op2, size_t vl) {
-  return __riscv_vmulhsu_vx_i64m8_m(mask, op1, op2, vl); /* expected-error {{builtin requires: v}} */
+  return __riscv_vmulhsu_vx_i64m8_m(mask, op1, op2, vl); /* expected-error {{builtin requires at least one of the following extensions: v}} */
 }
-- 
GitLab


From da0decf002a6e8c5f14dcf61135c6c758facec2b Mon Sep 17 00:00:00 2001
From: Zequan Wu <zequanwu@google.com>
Date: Mon, 11 Dec 2023 15:44:01 -0500
Subject: [PATCH 173/349] [Profile] Add missing COMPILER_RT_VISIBILITY to
 __llvm_profile_disable_continuous_mode.

---
 compiler-rt/lib/profile/InstrProfilingBuffer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/compiler-rt/lib/profile/InstrProfilingBuffer.c b/compiler-rt/lib/profile/InstrProfilingBuffer.c
index 5657bf5bacf2..af52804b2b53 100644
--- a/compiler-rt/lib/profile/InstrProfilingBuffer.c
+++ b/compiler-rt/lib/profile/InstrProfilingBuffer.c
@@ -33,7 +33,7 @@ COMPILER_RT_VISIBILITY void __llvm_profile_enable_continuous_mode(void) {
   ContinuouslySyncProfile = 1;
 }
 
-void __llvm_profile_disable_continuous_mode(void) {
+COMPILER_RT_VISIBILITY void __llvm_profile_disable_continuous_mode(void) {
   ContinuouslySyncProfile = 0;
 }
 
-- 
GitLab


From 1cc5431285f407f72e8e9312b1c2a2d22b1cadd7 Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu@google.com>
Date: Mon, 11 Dec 2023 12:55:29 -0800
Subject: [PATCH 174/349] [BOLT] Fix warnings

This patch fixes:

  bolt/lib/Core/BinaryFunctionProfile.cpp:222:10: error: variable
  'BBMergeSI' set but not used [-Werror,-Wunused-but-set-variable]

  bolt/lib/Passes/VeneerElimination.cpp:67:12: error: variable
  'VeneerCallers' set but not used [-Werror,-Wunused-but-set-variable]
---
 bolt/lib/Core/BinaryFunctionProfile.cpp | 1 +
 bolt/lib/Passes/VeneerElimination.cpp   | 1 +
 2 files changed, 2 insertions(+)

diff --git a/bolt/lib/Core/BinaryFunctionProfile.cpp b/bolt/lib/Core/BinaryFunctionProfile.cpp
index 0d705cd82f5d..55ebe5fc900e 100644
--- a/bolt/lib/Core/BinaryFunctionProfile.cpp
+++ b/bolt/lib/Core/BinaryFunctionProfile.cpp
@@ -225,6 +225,7 @@ void BinaryFunction::mergeProfileDataInto(BinaryFunction &BF) const {
     for (const BinaryBasicBlock *BBSucc : BB->successors()) {
       (void)BBSucc;
       assert(getIndex(BBSucc) == BF.getIndex(*BBMergeSI));
+      (void)BBMergeSI;
 
       // At this point no branch count should be set to COUNT_NO_PROFILE.
       assert(BII->Count != BinaryBasicBlock::COUNT_NO_PROFILE &&
diff --git a/bolt/lib/Passes/VeneerElimination.cpp b/bolt/lib/Passes/VeneerElimination.cpp
index eadbfc17fb97..929c7360b7ff 100644
--- a/bolt/lib/Passes/VeneerElimination.cpp
+++ b/bolt/lib/Passes/VeneerElimination.cpp
@@ -89,6 +89,7 @@ void VeneerElimination::runOnFunctions(BinaryContext &BC) {
   LLVM_DEBUG(
       dbgs() << "BOLT-INFO: number of linker-inserted veneers call sites: "
              << VeneerCallers << "\n");
+  (void)VeneerCallers;
 }
 
 } // namespace bolt
-- 
GitLab


From c94f7804877ed39a67d58efa27ea190170d30bc3 Mon Sep 17 00:00:00 2001
From: Peter Klausler <35819229+klausler@users.noreply.github.com>
Date: Mon, 11 Dec 2023 12:56:34 -0800
Subject: [PATCH 175/349] [flang][runtime] Support READ after WRITE w/o
 positioning (#74650)

Most Fortran implementations support a READ statement after a WRITE
without repositioning on a sequential unit; it implies on ENDFILE and
then hits an EOF condition.

Fixes llvm-test-suite/Fortran/gfortran/regression/backspace_2.f.
---
 flang/runtime/unit.cpp | 9 +++++++++
 flang/runtime/unit.h   | 1 +
 2 files changed, 10 insertions(+)

diff --git a/flang/runtime/unit.cpp b/flang/runtime/unit.cpp
index 962f97bf260c..e4f346ae941f 100644
--- a/flang/runtime/unit.cpp
+++ b/flang/runtime/unit.cpp
@@ -355,6 +355,7 @@ bool ExternalFileUnit::Emit(const char *data, std::size_t bytes,
   }
   positionInRecord += bytes;
   furthestPositionInRecord = furthestAfter;
+  anyWriteSinceLastPositioning_ = true;
   return true;
 }
 
@@ -459,6 +460,11 @@ bool ExternalFileUnit::BeginReadingRecord(IoErrorHandler &handler) {
         HitEndOnRead(handler);
       }
     } else {
+      if (anyWriteSinceLastPositioning_ && access == Access::Sequential) {
+        // Most Fortran implementations allow a READ after a WRITE;
+        // the read then just hits an EOF.
+        DoEndfile(handler);
+      }
       recordLength.reset();
       RUNTIME_CHECK(handler, isUnformatted.has_value());
       if (*isUnformatted) {
@@ -619,6 +625,7 @@ void ExternalFileUnit::BackspaceRecord(IoErrorHandler &handler) {
       }
     }
     BeginRecord();
+    anyWriteSinceLastPositioning_ = false;
   }
 }
 
@@ -671,6 +678,7 @@ void ExternalFileUnit::Rewind(IoErrorHandler &handler) {
     SetPosition(0, handler);
     currentRecordNumber = 1;
     leftTabLimit.reset();
+    anyWriteSinceLastPositioning_ = false;
   }
 }
 
@@ -934,6 +942,7 @@ void ExternalFileUnit::DoEndfile(IoErrorHandler &handler) {
   TruncateFrame(frameOffsetInFile_, handler);
   BeginRecord();
   impliedEndfile_ = false;
+  anyWriteSinceLastPositioning_ = false;
 }
 
 void ExternalFileUnit::CommitWrites() {
diff --git a/flang/runtime/unit.h b/flang/runtime/unit.h
index 1ec3013ba82b..140fda3c4d2a 100644
--- a/flang/runtime/unit.h
+++ b/flang/runtime/unit.h
@@ -140,6 +140,7 @@ private:
   Direction direction_{Direction::Output};
   bool impliedEndfile_{false}; // sequential/stream output has taken place
   bool beganReadingRecord_{false};
+  bool anyWriteSinceLastPositioning_{false};
   bool directAccessRecWasSet_{false}; // REC= appeared
   // Subtle: The beginning of the frame can't be allowed to advance
   // during a single list-directed READ due to the possibility of a
-- 
GitLab


From 4f9cb79a442fe39d02c05dff07625014976c6769 Mon Sep 17 00:00:00 2001
From: Peter Klausler <35819229+klausler@users.noreply.github.com>
Date: Mon, 11 Dec 2023 13:01:33 -0800
Subject: [PATCH 176/349] [flang][runtime] Fix octal input of REAL(10) (#74658)

The overflow check didn't work for a 27-digit octal field containing an
80-bit x87 extended precision real value. The count of bytes required
was too large because the leading digit (1) was assumed to require a
full three bits. And the actual transmission of the octal input digits
to the output buffer was incorrect, too.

Fixes llvm-test-suite/Fortran/gfortran/regression/boz_15.f90.
---
 flang/runtime/edit-input.cpp | 42 +++++++++++++++++++++++++++---------
 1 file changed, 32 insertions(+), 10 deletions(-)

diff --git a/flang/runtime/edit-input.cpp b/flang/runtime/edit-input.cpp
index 4e8c9aa868a6..7a868d56f075 100644
--- a/flang/runtime/edit-input.cpp
+++ b/flang/runtime/edit-input.cpp
@@ -64,10 +64,15 @@ static bool EditBOZInput(
   }
   // Count significant digits after any leading white space & zeroes
   int digits{0};
+  int significantBits{0};
   for (; next; next = io.NextInField(remaining, edit)) {
     char32_t ch{*next};
     if (ch == ' ' || ch == '\t') {
-      continue;
+      if (edit.modes.editingFlags & blankZero) {
+        ch = '0'; // BZ mode - treat blank as if it were zero
+      } else {
+        continue;
+      }
     }
     if (ch >= '0' && ch <= '1') {
     } else if (LOG2_BASE >= 3 && ch >= '2' && ch <= '7') {
@@ -79,9 +84,22 @@ static bool EditBOZInput(
           "Bad character '%lc' in B/O/Z input field", ch);
       return false;
     }
-    ++digits;
+    if (digits++ == 0) {
+      significantBits = 4;
+      if (ch >= '0' && ch <= '1') {
+        significantBits = 1;
+      } else if (ch >= '2' && ch <= '3') {
+        significantBits = 2;
+      } else if (ch >= '4' && ch <= '7') {
+        significantBits = 3;
+      } else {
+        significantBits = 4;
+      }
+    } else {
+      significantBits += LOG2_BASE;
+    }
   }
-  auto significantBytes{static_cast<std::size_t>(digits * LOG2_BASE + 7) / 8};
+  auto significantBytes{static_cast<std::size_t>(significantBits + 7) / 8};
   if (significantBytes > bytes) {
     io.GetIoErrorHandler().SignalError(IostatBOZInputOverflow,
         "B/O/Z input of %d digits overflows %zd-byte variable", digits, bytes);
@@ -96,12 +114,17 @@ static bool EditBOZInput(
   auto *data{reinterpret_cast<unsigned char *>(n) +
       (isHostLittleEndian ? significantBytes - 1 : 0)};
   int shift{((digits - 1) * LOG2_BASE) & 7};
-  if (shift + LOG2_BASE > 8) {
-    shift -= 8; // misaligned octal
-  }
   while (digits > 0) {
     char32_t ch{*io.NextInField(remaining, edit)};
     int digit{0};
+    if (ch == ' ' || ch == '\t') {
+      if (edit.modes.editingFlags & blankZero) {
+        ch = '0'; // BZ mode - treat blank as if it were zero
+      } else {
+        continue;
+      }
+    }
+    --digits;
     if (ch >= '0' && ch <= '9') {
       digit = ch - '0';
     } else if (ch >= 'A' && ch <= 'F') {
@@ -111,12 +134,11 @@ static bool EditBOZInput(
     } else {
       continue;
     }
-    --digits;
     if (shift < 0) {
-      shift += 8;
-      if (shift + LOG2_BASE > 8) { // misaligned octal
-        *data |= digit >> (8 - shift);
+      if (shift + LOG2_BASE > 0) { // misaligned octal
+        *data |= digit >> -shift;
       }
+      shift += 8;
       data += increment;
     }
     *data |= digit << shift;
-- 
GitLab


From 353d56d22bfb77ee48554705c50ee71b115854fd Mon Sep 17 00:00:00 2001
From: Peter Klausler <35819229+klausler@users.noreply.github.com>
Date: Mon, 11 Dec 2023 13:05:29 -0800
Subject: [PATCH 177/349] [flang][runtime] Fix fixed-width field internal wide
 character input (#74683)

There was some confusion about units (bytes vs characters) in the
handling of the amount of input remaining in fixed-width formatted input
fields. Clarify that any variable or parameter counting "remaining"
space in a field in the I/O runtime is always in units of bytes, and
make it so where it wasn't.

Fixes the bug(s) in
llvm-test-suite/Fortran/gfortran/regression/char4_iunit_2.f03, although
the test still won't pass due to its dependence on gfortran's
list-directed output spacing.
---
 flang/runtime/edit-input.cpp | 101 ++++++++++++++++++-----------------
 flang/runtime/io-stmt.h      |  14 +++--
 2 files changed, 64 insertions(+), 51 deletions(-)

diff --git a/flang/runtime/edit-input.cpp b/flang/runtime/edit-input.cpp
index 7a868d56f075..822099b5141b 100644
--- a/flang/runtime/edit-input.cpp
+++ b/flang/runtime/edit-input.cpp
@@ -916,20 +916,20 @@ static bool EditListDirectedCharacterInput(
 }
 
 template <typename CHAR>
-bool EditCharacterInput(
-    IoStatementState &io, const DataEdit &edit, CHAR *x, std::size_t length) {
+bool EditCharacterInput(IoStatementState &io, const DataEdit &edit, CHAR *x,
+    std::size_t lengthChars) {
   switch (edit.descriptor) {
   case DataEdit::ListDirected:
-    return EditListDirectedCharacterInput(io, x, length, edit);
+    return EditListDirectedCharacterInput(io, x, lengthChars, edit);
   case 'A':
   case 'G':
     break;
   case 'B':
-    return EditBOZInput<1>(io, edit, x, length * sizeof *x);
+    return EditBOZInput<1>(io, edit, x, lengthChars * sizeof *x);
   case 'O':
-    return EditBOZInput<3>(io, edit, x, length * sizeof *x);
+    return EditBOZInput<3>(io, edit, x, lengthChars * sizeof *x);
   case 'Z':
-    return EditBOZInput<4>(io, edit, x, length * sizeof *x);
+    return EditBOZInput<4>(io, edit, x, lengthChars * sizeof *x);
   default:
     io.GetIoErrorHandler().SignalError(IostatErrorInFormat,
         "Data edit descriptor '%c' may not be used with a CHARACTER data item",
@@ -937,27 +937,31 @@ bool EditCharacterInput(
     return false;
   }
   const ConnectionState &connection{io.GetConnectionState()};
-  std::size_t remaining{length};
+  std::size_t remainingChars{lengthChars};
+  // Skip leading characters.
+  // Their bytes don't count towards INQUIRE(IOLENGTH=).
+  std::size_t skipChars{0};
   if (edit.width && *edit.width > 0) {
-    remaining = *edit.width;
+    remainingChars = *edit.width;
+    if (remainingChars > lengthChars) {
+      skipChars = remainingChars - lengthChars;
+    }
   }
   // When the field is wider than the variable, we drop the leading
   // characters.  When the variable is wider than the field, there can be
   // trailing padding or an EOR condition.
   const char *input{nullptr};
-  std::size_t ready{0};
-  // Skip leading bytes.
-  // These bytes don't count towards INQUIRE(IOLENGTH=).
-  std::size_t skip{remaining > length ? remaining - length : 0};
+  std::size_t readyBytes{0};
   // Transfer payload bytes; these do count.
-  while (remaining > 0) {
-    if (ready == 0) {
-      ready = io.GetNextInputBytes(input);
-      if (ready == 0 || (ready < remaining && edit.modes.nonAdvancing)) {
-        if (io.CheckForEndOfRecord(ready)) {
-          if (ready == 0) {
+  while (remainingChars > 0) {
+    if (readyBytes == 0) {
+      readyBytes = io.GetNextInputBytes(input);
+      if (readyBytes == 0 ||
+          (readyBytes < remainingChars && edit.modes.nonAdvancing)) {
+        if (io.CheckForEndOfRecord(readyBytes)) {
+          if (readyBytes == 0) {
             // PAD='YES' and no more data
-            std::fill_n(x, length, ' ');
+            std::fill_n(x, lengthChars, ' ');
             return !io.GetIoErrorHandler().InError();
           } else {
             // Do partial read(s) then pad on last iteration
@@ -967,63 +971,64 @@ bool EditCharacterInput(
         }
       }
     }
-    std::size_t chunk;
-    bool skipping{skip > 0};
+    std::size_t chunkBytes;
+    std::size_t chunkChars{1};
+    bool skipping{skipChars > 0};
     if (connection.isUTF8) {
-      chunk = MeasureUTF8Bytes(*input);
+      chunkBytes = MeasureUTF8Bytes(*input);
       if (skipping) {
-        --skip;
+        --skipChars;
       } else if (auto ucs{DecodeUTF8(input)}) {
         *x++ = *ucs;
-        --length;
-      } else if (chunk == 0) {
+        --lengthChars;
+      } else if (chunkBytes == 0) {
         // error recovery: skip bad encoding
-        chunk = 1;
+        chunkBytes = 1;
       }
-      --remaining;
     } else if (connection.internalIoCharKind > 1) {
       // Reading from non-default character internal unit
-      chunk = connection.internalIoCharKind;
+      chunkBytes = connection.internalIoCharKind;
       if (skipping) {
-        --skip;
+        --skipChars;
       } else {
         char32_t buffer{0};
-        std::memcpy(&buffer, input, chunk);
+        std::memcpy(&buffer, input, chunkBytes);
         *x++ = buffer;
-        --length;
+        --lengthChars;
       }
-      --remaining;
     } else if constexpr (sizeof *x > 1) {
       // Read single byte with expansion into multi-byte CHARACTER
-      chunk = 1;
+      chunkBytes = 1;
       if (skipping) {
-        --skip;
+        --skipChars;
       } else {
         *x++ = static_cast<unsigned char>(*input);
-        --length;
+        --lengthChars;
       }
-      --remaining;
     } else { // single bytes -> default CHARACTER
       if (skipping) {
-        chunk = std::min<std::size_t>(skip, ready);
-        skip -= chunk;
+        chunkBytes = std::min<std::size_t>(skipChars, readyBytes);
+        chunkChars = chunkBytes;
+        skipChars -= chunkChars;
       } else {
-        chunk = std::min<std::size_t>(remaining, ready);
-        std::memcpy(x, input, chunk);
-        x += chunk;
-        length -= chunk;
+        chunkBytes = std::min<std::size_t>(remainingChars, readyBytes);
+        chunkBytes = std::min<std::size_t>(lengthChars, chunkBytes);
+        chunkChars = chunkBytes;
+        std::memcpy(x, input, chunkBytes);
+        x += chunkBytes;
+        lengthChars -= chunkChars;
       }
-      remaining -= chunk;
     }
-    input += chunk;
+    input += chunkBytes;
+    remainingChars -= chunkChars;
     if (!skipping) {
-      io.GotChar(chunk);
+      io.GotChar(chunkBytes);
     }
-    io.HandleRelativePosition(chunk);
-    ready -= chunk;
+    io.HandleRelativePosition(chunkBytes);
+    readyBytes -= chunkBytes;
   }
   // Pad the remainder of the input variable, if any.
-  std::fill_n(x, length, ' ');
+  std::fill_n(x, lengthChars, ' ');
   return CheckCompleteListDirectedField(io, edit);
 }
 
diff --git a/flang/runtime/io-stmt.h b/flang/runtime/io-stmt.h
index d4ceb8326524..91169f6c6e32 100644
--- a/flang/runtime/io-stmt.h
+++ b/flang/runtime/io-stmt.h
@@ -92,8 +92,8 @@ public:
   std::size_t GetNextInputBytes(const char *&);
   bool AdvanceRecord(int = 1);
   void BackspaceRecord();
-  void HandleRelativePosition(std::int64_t);
-  void HandleAbsolutePosition(std::int64_t); // for r* in list I/O
+  void HandleRelativePosition(std::int64_t byteOffset);
+  void HandleAbsolutePosition(std::int64_t byteOffset); // for r* in list I/O
   std::optional<DataEdit> GetNextDataEdit(int maxRepeat = 1);
   ExternalFileUnit *GetExternalFileUnit() const; // null if internal unit
   bool BeginReadingRecord();
@@ -124,7 +124,11 @@ public:
   // Vacant after the end of the current record
   std::optional<char32_t> GetCurrentChar(std::size_t &byteCount);
 
-  // For fixed-width fields, return the number of remaining characters.
+  // The "remaining" arguments to CueUpInput(), SkipSpaces(), & NextInField()
+  // are always in units of bytes, not characters; the distinction matters
+  // for internal input from CHARACTER(KIND=2 and 4).
+
+  // For fixed-width fields, return the number of remaining bytes.
   // Skip over leading blanks.
   std::optional<int> CueUpInput(const DataEdit &edit) {
     std::optional<int> remaining;
@@ -134,6 +138,10 @@ public:
     } else {
       if (edit.width.value_or(0) > 0) {
         remaining = *edit.width;
+        if (int bytesPerChar{GetConnectionState().internalIoCharKind};
+            bytesPerChar > 1) {
+          *remaining *= bytesPerChar;
+        }
       }
       SkipSpaces(remaining);
     }
-- 
GitLab


From ea3a3b25b93664c8be750ac3cd550855dcd1848b Mon Sep 17 00:00:00 2001
From: Peter Klausler <35819229+klausler@users.noreply.github.com>
Date: Mon, 11 Dec 2023 13:09:12 -0800
Subject: [PATCH 178/349] [flang] Handle continuation line edge case (#74751)

For a character literal that is split over more than one source line
with free form line continuation using '&'
at the end of one line but missing the standard-required '&' on the
continuation line, also handle the case of spaces at the beginning of
the continuation line.

For example,

PRINT *, 'don'&
   't poke the bear'

now prints "don't poke the bear", like nearly all other Fortran
compilers do.

This is not strictly standard conforming behavior, and the compiler
emits a portability warning with -pedantic.

Fixes llvm-test-suite/Fortran/gfortran/regression/continuation_1.f90,
.../continuation_12.f90, and .../continuation_13.f90.
---
 flang/lib/Parser/prescan.cpp                  | 20 ++++++++++---------
 flang/lib/Parser/prescan.h                    |  1 +
 .../test/Parser/continuation-before-quote.f90 | 10 ----------
 .../Parser/continuation-without-ampersand.f90 | 13 ++++++++++++
 4 files changed, 25 insertions(+), 19 deletions(-)
 delete mode 100644 flang/test/Parser/continuation-before-quote.f90
 create mode 100644 flang/test/Parser/continuation-without-ampersand.f90

diff --git a/flang/lib/Parser/prescan.cpp b/flang/lib/Parser/prescan.cpp
index 449ea6014442..79cdaccf1fbf 100644
--- a/flang/lib/Parser/prescan.cpp
+++ b/flang/lib/Parser/prescan.cpp
@@ -706,6 +706,7 @@ void Prescanner::QuotedCharacterLiteral(
   char quote{*at_};
   const char *end{at_ + 1};
   inCharLiteral_ = true;
+  continuationInCharLiteral_ = true;
   const auto emit{[&](char ch) { EmitChar(tokens, ch); }};
   const auto insert{[&](char ch) { EmitInsertedChar(tokens, ch); }};
   bool isEscaped{false};
@@ -749,16 +750,9 @@ void Prescanner::QuotedCharacterLiteral(
         break;
       }
       inCharLiteral_ = true;
-      if (insertASpace_) {
-        if (features_.ShouldWarn(
-                common::LanguageFeature::MiscSourceExtensions)) {
-          Say(GetProvenanceRange(at_, end),
-              "Repeated quote mark in character literal continuation line should have been preceded by '&'"_port_en_US);
-        }
-        insertASpace_ = false;
-      }
     }
   }
+  continuationInCharLiteral_ = false;
   inCharLiteral_ = false;
 }
 
@@ -1122,7 +1116,15 @@ const char *Prescanner::FreeFormContinuationLine(bool ampersand) {
     } else if (*p == '!' || *p == '\n' || *p == '#') {
       return nullptr;
     } else if (ampersand || IsImplicitContinuation()) {
-      if (p > nextLine_) {
+      if (continuationInCharLiteral_) {
+        // 'a'&            -> 'a''b' == "a'b"
+        //   'b'
+        if (features_.ShouldWarn(
+                common::LanguageFeature::MiscSourceExtensions)) {
+          Say(GetProvenanceRange(p, p + 1),
+              "Character literal continuation line should have been preceded by '&'"_port_en_US);
+        }
+      } else if (p > nextLine_) {
         --p;
       } else {
         insertASpace_ = true;
diff --git a/flang/lib/Parser/prescan.h b/flang/lib/Parser/prescan.h
index 16b2c6165f61..84e046c1b102 100644
--- a/flang/lib/Parser/prescan.h
+++ b/flang/lib/Parser/prescan.h
@@ -218,6 +218,7 @@ private:
   bool slashInCurrentStatement_{false};
   bool preventHollerith_{false}; // CHARACTER*4HIMOM not Hollerith
   bool inCharLiteral_{false};
+  bool continuationInCharLiteral_{false};
   bool inPreprocessorDirective_{false};
 
   // In some edge cases of compiler directive continuation lines, it
diff --git a/flang/test/Parser/continuation-before-quote.f90 b/flang/test/Parser/continuation-before-quote.f90
deleted file mode 100644
index 66252010d89c..000000000000
--- a/flang/test/Parser/continuation-before-quote.f90
+++ /dev/null
@@ -1,10 +0,0 @@
-! RUN: %flang_fc1 -fsyntax-only -pedantic %s 2>&1 | FileCheck %s
-! Continuation between repeated quotation marks
-subroutine test
-!CHECK: portability: Repeated quote mark in character literal continuation line should have been preceded by '&'
-  print *, 'needs an '&
-'ampersand'''
-!CHECK-NOT: portability: Repeated quote mark in character literal continuation line should have been preceded by '&'
-  print *, 'has an '&
-&'ampersand'''
-end
diff --git a/flang/test/Parser/continuation-without-ampersand.f90 b/flang/test/Parser/continuation-without-ampersand.f90
new file mode 100644
index 000000000000..5c3f23235edc
--- /dev/null
+++ b/flang/test/Parser/continuation-without-ampersand.f90
@@ -0,0 +1,13 @@
+! RUN: %flang_fc1 -fsyntax-only -pedantic %s 2>&1 | FileCheck %s
+! Continuation between repeated quotation marks
+subroutine test
+!CHECK: portability: Character literal continuation line should have been preceded by '&'
+  print *, 'needs an '&
+'ampersand'''
+!CHECK: portability: Character literal continuation line should have been preceded by '&'
+  print *, 'also needs an '&
+ 'ampersand'''
+!CHECK-NOT: portability: Character literal continuation line should have been preceded by '&'
+  print *, 'has an '&
+&'ampersand'''
+end
-- 
GitLab


From 66be0571932c016d5904fa9e14423b4e0a3fd586 Mon Sep 17 00:00:00 2001
From: Hui <hui.xie0621@gmail.com>
Date: Mon, 11 Dec 2023 21:20:20 +0000
Subject: [PATCH 179/349] [libc++][test] disable all atomic<long double> tests
 (#74201)

Clang's support for atomic operations on long doubles is currently broken,
so these tests don't work everywhere. This is a long standing condition and
the goal of this patch is to get the CI green again on all platforms.

The actual Clang fixes will be pursued separately.

Fixes #73791
---
 .../atomics.types.float/lockfree.pass.cpp              |  3 ++-
 .../atomics.types.float/assign.pass.cpp                |  3 ++-
 .../compare_exchange_strong.pass.cpp                   |  2 +-
 .../atomics.types.float/compare_exchange_weak.pass.cpp |  8 +++-----
 .../atomics.types.float/ctor.pass.cpp                  |  3 ++-
 .../atomics.types.float/exchange.pass.cpp              |  6 ++----
 .../atomics.types.float/fetch_add.pass.cpp             | 10 +++++-----
 .../atomics.types.float/fetch_sub.pass.cpp             | 10 +++++-----
 .../atomics.types.float/load.pass.cpp                  |  5 ++---
 .../atomics.types.float/lockfree.pass.cpp              |  3 ++-
 .../atomics.types.float/notify_all.pass.cpp            |  3 ++-
 .../atomics.types.float/notify_one.pass.cpp            |  3 ++-
 .../atomics.types.float/operator.float.pass.cpp        |  3 ++-
 .../atomics.types.float/operator.minus_equals.pass.cpp |  7 +++----
 .../atomics.types.float/operator.plus_equals.pass.cpp  |  7 +++----
 .../atomics.types.float/store.pass.cpp                 |  5 ++---
 .../atomics.types.float/wait.pass.cpp                  |  6 ++----
 17 files changed, 42 insertions(+), 45 deletions(-)

diff --git a/libcxx/test/libcxx/atomics/atomics.types.generic/atomics.types.float/lockfree.pass.cpp b/libcxx/test/libcxx/atomics/atomics.types.generic/atomics.types.float/lockfree.pass.cpp
index 42a7c08fa75b..a59839ff806e 100644
--- a/libcxx/test/libcxx/atomics/atomics.types.generic/atomics.types.float/lockfree.pass.cpp
+++ b/libcxx/test/libcxx/atomics/atomics.types.generic/atomics.types.float/lockfree.pass.cpp
@@ -45,7 +45,8 @@ void test() {
 int main(int, char**) {
   test<float>();
   test<double>();
-  test<long double>();
+  // TODO https://github.com/llvm/llvm-project/issues/47978
+  // test<long double>();
 
   return 0;
 }
diff --git a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/assign.pass.cpp b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/assign.pass.cpp
index 66f6c91b802c..1561bd27d8d7 100644
--- a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/assign.pass.cpp
+++ b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/assign.pass.cpp
@@ -56,7 +56,8 @@ void test() {
 int main(int, char**) {
   test<float>();
   test<double>();
-  test<long double>();
+  // TODO https://github.com/llvm/llvm-project/issues/47978
+  // test<long double>();
 
   return 0;
 }
diff --git a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/compare_exchange_strong.pass.cpp b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/compare_exchange_strong.pass.cpp
index 711b49ddc233..84ef7b70bc0a 100644
--- a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/compare_exchange_strong.pass.cpp
+++ b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/compare_exchange_strong.pass.cpp
@@ -220,7 +220,7 @@ void test() {
 int main(int, char**) {
   test<float>();
   test<double>();
-  // https://github.com/llvm/llvm-project/issues/47978
+  // TODO https://github.com/llvm/llvm-project/issues/47978
   // test<long double>();
 
   return 0;
diff --git a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/compare_exchange_weak.pass.cpp b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/compare_exchange_weak.pass.cpp
index ee1a00c28427..54ca29a0d427 100644
--- a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/compare_exchange_weak.pass.cpp
+++ b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/compare_exchange_weak.pass.cpp
@@ -68,7 +68,7 @@ void testBasic(MemoryOrder... memory_order) {
     assert(a.load() == T(1.2));
 
     // bug
-    // https://github.com/llvm/llvm-project/issues/47978
+    // TODO https://github.com/llvm/llvm-project/issues/47978
     if constexpr (!std::same_as<T, long double>) {
       assert(expected == T(1.2));
     }
@@ -236,10 +236,8 @@ int main(int, char**) {
   test<float>();
   test<double>();
 
-// https://github.com/llvm/llvm-project/issues/47978
-#ifndef TEST_COMPILER_CLANG
-  test<long double>();
-#endif
+  // TODO https://github.com/llvm/llvm-project/issues/47978
+  // test<long double>();
 
   return 0;
 }
diff --git a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/ctor.pass.cpp b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/ctor.pass.cpp
index aad635408476..92351d74f35c 100644
--- a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/ctor.pass.cpp
+++ b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/ctor.pass.cpp
@@ -56,7 +56,8 @@ constexpr void testOne() {
 constexpr bool test() {
   testOne<float>();
   testOne<double>();
-  testOne<long double>();
+  // TODO https://github.com/llvm/llvm-project/issues/47978
+  // testOne<long double>();
   return true;
 }
 
diff --git a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/exchange.pass.cpp b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/exchange.pass.cpp
index c0d1eb686db7..c365923c42d0 100644
--- a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/exchange.pass.cpp
+++ b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/exchange.pass.cpp
@@ -6,9 +6,6 @@
 //
 //===----------------------------------------------------------------------===//
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// Clang's support for atomic operations on long double is broken. See https://github.com/llvm/llvm-project/issues/72893
-// XFAIL: target={{x86_64-.*}} && tsan
-// XFAIL: target={{x86_64-.*}} && msan
 // XFAIL: !has-64-bit-atomics
 // UNSUPPORTED: !non-lockfree-atomics
 
@@ -72,7 +69,8 @@ void test() {
 int main(int, char**) {
   test<float>();
   test<double>();
-  test<long double>();
+  // TODO https://github.com/llvm/llvm-project/issues/47978
+  // test<long double>();
 
   return 0;
 }
diff --git a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/fetch_add.pass.cpp b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/fetch_add.pass.cpp
index c31243053e69..d74502f52e1b 100644
--- a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/fetch_add.pass.cpp
+++ b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/fetch_add.pass.cpp
@@ -7,13 +7,12 @@
 //===----------------------------------------------------------------------===//
 // UNSUPPORTED: c++03, c++11, c++14, c++17
 // UNSUPPORTED: LIBCXX-AIX-FIXME
-// Clang's support for atomic operations on long double is broken. See https://github.com/llvm/llvm-project/issues/72893
-// XFAIL: target={{x86_64-.*}} && tsan
-// Hangs with msan.
-// UNSUPPORTED: msan
 // XFAIL: !has-64-bit-atomics
 // UNSUPPORTED: !non-lockfree-atomics
 
+// https://github.com/llvm/llvm-project/issues/72893
+// XFAIL: target={{x86_64-.*}} && tsan
+
 // floating-point-type fetch_add(floating-point-type,
 //                               memory_order = memory_order::seq_cst) volatile noexcept;
 // floating-point-type fetch_add(floating-point-type,
@@ -114,7 +113,8 @@ void test() {
 int main(int, char**) {
   test<float>();
   test<double>();
-  test<long double>();
+  // TODO https://github.com/llvm/llvm-project/issues/47978
+  // test<long double>();
 
   return 0;
 }
diff --git a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/fetch_sub.pass.cpp b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/fetch_sub.pass.cpp
index d26d21dec1b3..2b07f1fdbb5b 100644
--- a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/fetch_sub.pass.cpp
+++ b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/fetch_sub.pass.cpp
@@ -7,13 +7,12 @@
 //===----------------------------------------------------------------------===//
 // UNSUPPORTED: c++03, c++11, c++14, c++17
 // UNSUPPORTED: LIBCXX-AIX-FIXME
-// Clang's support for atomic operations on long double is broken. See https://github.com/llvm/llvm-project/issues/72893
-// XFAIL: target={{x86_64-.*}} && tsan
-// Hangs with msan.
-// UNSUPPORTED: msan
 // XFAIL: !has-64-bit-atomics
 // UNSUPPORTED: !non-lockfree-atomics
 
+// https://github.com/llvm/llvm-project/issues/72893
+// XFAIL: target={{x86_64-.*}} && tsan
+
 // floating-point-type fetch_sub(floating-point-type,
 //                               memory_order = memory_order::seq_cst) volatile noexcept;
 // floating-point-type fetch_sub(floating-point-type,
@@ -115,7 +114,8 @@ void test() {
 int main(int, char**) {
   test<float>();
   test<double>();
-  test<long double>();
+  // TODO https://github.com/llvm/llvm-project/issues/47978
+  // test<long double>();
 
   return 0;
 }
diff --git a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/load.pass.cpp b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/load.pass.cpp
index b567af457dca..784fdb96c464 100644
--- a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/load.pass.cpp
+++ b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/load.pass.cpp
@@ -6,9 +6,7 @@
 //
 //===----------------------------------------------------------------------===//
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// Clang's support for atomic operations on long double is broken. See https://github.com/llvm/llvm-project/issues/72893
 // XFAIL: !has-64-bit-atomics
-// XFAIL: target={{x86_64-.*}} && tsan
 // UNSUPPORTED: !non-lockfree-atomics
 
 //  floating-point-type load(memory_order = memory_order::seq_cst) volatile noexcept;
@@ -134,7 +132,8 @@ void test() {
 int main(int, char**) {
   test<float>();
   test<double>();
-  test<long double>();
+  // TODO https://github.com/llvm/llvm-project/issues/47978
+  // test<long double>();
 
   return 0;
 }
diff --git a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/lockfree.pass.cpp b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/lockfree.pass.cpp
index b5422c0362dc..cf5af00cd4e8 100644
--- a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/lockfree.pass.cpp
+++ b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/lockfree.pass.cpp
@@ -55,7 +55,8 @@ void test() {
 int main(int, char**) {
   test<float>();
   test<double>();
-  test<long double>();
+  // TODO https://github.com/llvm/llvm-project/issues/47978
+  // test<long double>();
 
   return 0;
 }
diff --git a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/notify_all.pass.cpp b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/notify_all.pass.cpp
index b50c0ad9ee92..d8bec9160c68 100644
--- a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/notify_all.pass.cpp
+++ b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/notify_all.pass.cpp
@@ -93,7 +93,8 @@ void test() {
 int main(int, char**) {
   test<float>();
   test<double>();
-  test<long double>();
+  // TODO https://github.com/llvm/llvm-project/issues/47978
+  // test<long double>();
 
   return 0;
 }
diff --git a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/notify_one.pass.cpp b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/notify_one.pass.cpp
index aee4af186b9f..fd4ea44ff851 100644
--- a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/notify_one.pass.cpp
+++ b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/notify_one.pass.cpp
@@ -77,7 +77,8 @@ void test() {
 int main(int, char**) {
   test<float>();
   test<double>();
-  test<long double>();
+  // TODO https://github.com/llvm/llvm-project/issues/47978
+  // test<long double>();
 
   return 0;
 }
diff --git a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/operator.float.pass.cpp b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/operator.float.pass.cpp
index 5d957ca68404..a1733276c0ec 100644
--- a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/operator.float.pass.cpp
+++ b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/operator.float.pass.cpp
@@ -52,7 +52,8 @@ void test() {
 int main(int, char**) {
   test<float>();
   test<double>();
-  test<long double>();
+  // TODO https://github.com/llvm/llvm-project/issues/47978
+  // test<long double>();
 
   return 0;
 }
diff --git a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/operator.minus_equals.pass.cpp b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/operator.minus_equals.pass.cpp
index 269eb819524f..22233b5a62ba 100644
--- a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/operator.minus_equals.pass.cpp
+++ b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/operator.minus_equals.pass.cpp
@@ -6,11 +6,9 @@
 //
 //===----------------------------------------------------------------------===//
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// XFAIL: !has-64-bit-atomics
 // UNSUPPORTED: LIBCXX-AIX-FIXME
+// XFAIL: !has-64-bit-atomics
 // UNSUPPORTED: !non-lockfree-atomics
-// Hangs with msan.
-// UNSUPPORTED: msan
 
 // floating-point-type operator-=(floating-point-type) volatile noexcept;
 // floating-point-type operator-=(floating-point-type) noexcept;
@@ -98,7 +96,8 @@ void test() {
 int main(int, char**) {
   test<float>();
   test<double>();
-  test<long double>();
+  // TODO https://github.com/llvm/llvm-project/issues/47978
+  // test<long double>();
 
   return 0;
 }
diff --git a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/operator.plus_equals.pass.cpp b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/operator.plus_equals.pass.cpp
index 9a2298ea46d6..548c5ac11a26 100644
--- a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/operator.plus_equals.pass.cpp
+++ b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/operator.plus_equals.pass.cpp
@@ -6,11 +6,9 @@
 //
 //===----------------------------------------------------------------------===//
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// XFAIL: !has-64-bit-atomics
 // UNSUPPORTED: LIBCXX-AIX-FIXME
+// XFAIL: !has-64-bit-atomics
 // UNSUPPORTED: !non-lockfree-atomics
-// Hangs with msan.
-// UNSUPPORTED: msan
 
 // floating-point-type operator+=(floating-point-type) volatile noexcept;
 // floating-point-type operator+=(floating-point-type) noexcept;
@@ -98,7 +96,8 @@ void test() {
 int main(int, char**) {
   test<float>();
   test<double>();
-  test<long double>();
+  // TODO https://github.com/llvm/llvm-project/issues/47978
+  // test<long double>();
 
   return 0;
 }
diff --git a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/store.pass.cpp b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/store.pass.cpp
index b0888aac67db..d232eea6ef01 100644
--- a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/store.pass.cpp
+++ b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/store.pass.cpp
@@ -6,9 +6,7 @@
 //
 //===----------------------------------------------------------------------===//
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// Clang's support for atomic operations on long double is broken. See https://github.com/llvm/llvm-project/issues/72893
 // XFAIL: !has-64-bit-atomics
-// XFAIL: target={{x86_64-.*}} && tsan
 // UNSUPPORTED: !non-lockfree-atomics
 
 // void store(floating-point-type, memory_order = memory_order::seq_cst) volatile noexcept;
@@ -109,7 +107,8 @@ void test() {
 int main(int, char**) {
   test<float>();
   test<double>();
-  test<long double>();
+  // TODO https://github.com/llvm/llvm-project/issues/47978
+  // test<long double>();
 
   return 0;
 }
diff --git a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/wait.pass.cpp b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/wait.pass.cpp
index 8e003a7e365d..ad70c133b99e 100644
--- a/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/wait.pass.cpp
+++ b/libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/wait.pass.cpp
@@ -7,9 +7,6 @@
 //===----------------------------------------------------------------------===//
 // UNSUPPORTED: c++03, c++11, c++14, c++17
 // XFAIL: availability-synchronization_library-missing
-// Clang's support for atomic operations on long double is broken. See https://github.com/llvm/llvm-project/issues/72893
-// XFAIL: target={{x86_64-.*}} && tsan
-// XFAIL: target={{x86_64-.*}} && msan
 // XFAIL: !has-64-bit-atomics
 // UNSUPPORTED: !non-lockfree-atomics
 
@@ -120,7 +117,8 @@ void test() {
 int main(int, char**) {
   test<float>();
   test<double>();
-  test<long double>();
+  // TODO https://github.com/llvm/llvm-project/issues/47978
+  // test<long double>();
 
   return 0;
 }
-- 
GitLab


From 13ef4fec26650a93b57709a23a3392582825afe7 Mon Sep 17 00:00:00 2001
From: Fangrui Song <i@maskray.me>
Date: Mon, 11 Dec 2023 13:26:25 -0800
Subject: [PATCH 180/349] [bazel] Port #73257
 54397f9ac128568838f2ac7bfc8e1f94b3eb264d

---
 .../llvm-project-overlay/llvm/BUILD.bazel     | 34 +++++++++----------
 1 file changed, 16 insertions(+), 18 deletions(-)

diff --git a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
index 8ab97a605e06..477e59e366d1 100644
--- a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+++ b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
@@ -2239,10 +2239,10 @@ gentbl(
     name = "riscv_isel_target_gen",
     strip_include_prefix = "lib/Target/RISCV",
     tbl_outs = [
-      ("-gen-global-isel", "lib/Target/RISCV/RISCVGenGlobalISel.inc"),
-      ("-gen-global-isel-combiner -combiners=RISCVO0PreLegalizerCombiner", "lib/Target/RISCV/RISCVGenO0PreLegalizeGICombiner.inc"),
-      ("-gen-global-isel-combiner -combiners=RISCVPostLegalizerCombiner", "lib/Target/RISCV/RISCVGenPostLegalizeGICombiner.inc"),
-      ("-gen-global-isel-combiner -combiners=RISCVPreLegalizerCombiner", "lib/Target/RISCV/RISCVGenPreLegalizeGICombiner.inc"),
+        ("-gen-global-isel", "lib/Target/RISCV/RISCVGenGlobalISel.inc"),
+        ("-gen-global-isel-combiner -combiners=RISCVO0PreLegalizerCombiner", "lib/Target/RISCV/RISCVGenO0PreLegalizeGICombiner.inc"),
+        ("-gen-global-isel-combiner -combiners=RISCVPostLegalizerCombiner", "lib/Target/RISCV/RISCVGenPostLegalizeGICombiner.inc"),
+        ("-gen-global-isel-combiner -combiners=RISCVPreLegalizerCombiner", "lib/Target/RISCV/RISCVGenPreLegalizeGICombiner.inc"),
     ],
     tblgen = ":llvm-tblgen",
     td_file = "lib/Target/RISCV/RISCVGISel.td",
@@ -2343,10 +2343,10 @@ gentbl(
         deps = [
             ":BinaryFormat",
             ":CodeGenTypes",
+            ":Core",
             ":DebugInfoCodeView",
             ":MC",
             ":MCDisassembler",
-            ":Core",
             ":Support",
             ":Target",
             ":config",
@@ -2552,23 +2552,23 @@ cc_library(
         ":AggressiveInstCombine",
         ":Analysis",
         ":CodeGen",
-        ":common_transforms",
-        ":config",
         ":Core",
         ":Coroutines",
         ":HipStdPar",
-        ":InstCombine",
-        ":Instrumentation",
         ":IPO",
         ":IRPrinter",
+        ":InstCombine",
+        ":Instrumentation",
         ":MLPolicies",
         ":ObjCARC",
-        ":pass_registry_def",
         ":Scalar",
         ":Support",
         ":Target",
         ":TransformUtils",
         ":Vectorize",
+        ":common_transforms",
+        ":config",
+        ":pass_registry_def",
     ],
 )
 
@@ -2804,20 +2804,19 @@ cc_library(
     ]),
     hdrs = glob([
         "include/llvm/ExecutionEngine/Orc/Debugging/*.h",
-    ]),
+    ]) + ["include/llvm-c/LLJITUtils.h"],
     copts = llvm_copts,
     deps = [
         ":BinaryFormat",
         ":DebugInfo",
-        ":OrcShared",
-        ":OrcJIT",
         ":JITLink",
+        ":OrcJIT",
+        ":OrcShared",
         ":Support",
         ":TargetParser",
     ],
 )
 
-
 cc_library(
     name = "OrcTargetProcess",
     srcs = glob([
@@ -3119,9 +3118,9 @@ cc_library(
         ":MC",
         ":MCA",
         ":MCDisassembler",
-        ":OrcJIT",
         ":Object",
         ":ObjectYAML",
+        ":OrcJIT",
         ":Support",
         ":Target",
         ":config",
@@ -3251,9 +3250,9 @@ cc_binary(
         ":Interpreter",
         ":MCJIT",
         ":Object",
+        ":OrcDebugging",
         ":OrcJIT",
         ":OrcTargetProcess",
-        ":OrcDebugging",
         ":Support",
         ":TargetParser",
         ":config",
@@ -4705,7 +4704,7 @@ cc_binary(
     srcs = glob([
         "tools/llvm-symbolizer/*.cpp",
         "tools/llvm-symbolizer/*.h",
-    ]) + [ "llvm-symbolizer-driver.cpp"],
+    ]) + ["llvm-symbolizer-driver.cpp"],
     copts = llvm_copts,
     stamp = 0,
     deps = [
@@ -4818,7 +4817,6 @@ expand_template(
     template = "cmake/modules/llvm-driver-template.cpp.in",
 )
 
-
 cc_binary(
     name = "sancov",
     srcs = glob([
-- 
GitLab


From 07919cf8957f715657145907a74ab410b33007a3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Andrzej=20Warzy=C5=84ski?= <andrzej.warzynski@arm.com>
Date: Mon, 11 Dec 2023 21:32:23 +0000
Subject: [PATCH 181/349] Revert "[mlir][vector] Make `TransposeOpLowering`
 configurable (#73915)" (#75062)

Reverting a workaround intended specifically for SPRI-V. That workaround
emerged from this discussion:

  * https://github.com/llvm/llvm-project/pull/72105

AFAIK, it hasn't been required in practice. This is based on IREE
(https://github.com/openxla/iree), which has just bumped it's fork of
LLVM without using it (*).

(*) https://github.com/openxla/iree/commit/cef31e775e03ec83420e4a7b47a992242d8df37c

This reverts commit bbd2b08b95fe76bea138c1b03c1cd42ed3ee04df.
---
 .../Vector/Transforms/VectorTransforms.h      | 10 ------
 .../Transforms/LowerVectorTranspose.cpp       | 34 +++++++++----------
 2 files changed, 16 insertions(+), 28 deletions(-)

diff --git a/mlir/include/mlir/Dialect/Vector/Transforms/VectorTransforms.h b/mlir/include/mlir/Dialect/Vector/Transforms/VectorTransforms.h
index 41ffc9299460..08d3bb157a0e 100644
--- a/mlir/include/mlir/Dialect/Vector/Transforms/VectorTransforms.h
+++ b/mlir/include/mlir/Dialect/Vector/Transforms/VectorTransforms.h
@@ -59,16 +59,6 @@ struct VectorTransformsOptions {
     vectorTransferSplit = opt;
     return *this;
   }
-
-  /// Option to control if vector.transpose can lower to a vector.shape_cast.
-  /// TODO: ATM it's not possible to lower `vector.shape_cast` to SPIR-V
-  /// and hence the need for this opt-out. Once the missing support has been
-  /// added, this option can be removed.
-  bool useShapeCast = true;
-  VectorTransformsOptions &setUseShapeCast(bool opt = true) {
-    useShapeCast = opt;
-    return *this;
-  }
 };
 
 //===----------------------------------------------------------------------===//
diff --git a/mlir/lib/Dialect/Vector/Transforms/LowerVectorTranspose.cpp b/mlir/lib/Dialect/Vector/Transforms/LowerVectorTranspose.cpp
index 4d43a76c4a4e..97f6caca1b25 100644
--- a/mlir/lib/Dialect/Vector/Transforms/LowerVectorTranspose.cpp
+++ b/mlir/lib/Dialect/Vector/Transforms/LowerVectorTranspose.cpp
@@ -334,24 +334,22 @@ public:
       return rewriter.notifyMatchFailure(
           op, "Options specifies lowering to shuffle");
 
-    if (vectorTransformOptions.useShapeCast) {
-      // Replace:
-      //   vector.transpose %0, [1, 0] : vector<nx1x<eltty>> to
-      //                                 vector<1xnxelty>
-      // with:
-      //   vector.shape_cast %0 : vector<nx1x<eltty>> to vector<1xnxelty>
-      //
-      // Source with leading unit dim (inverse) is also replaced. Unit dim must
-      // be fixed. Non-unit can be scalable.
-      if (resType.getRank() == 2 &&
-          ((resType.getShape().front() == 1 &&
-            !resType.getScalableDims().front()) ||
-           (resType.getShape().back() == 1 &&
-            !resType.getScalableDims().back())) &&
-          transp == ArrayRef<int64_t>({1, 0})) {
-        rewriter.replaceOpWithNewOp<vector::ShapeCastOp>(op, resType, input);
-        return success();
-      }
+    // Replace:
+    //   vector.transpose %0, [1, 0] : vector<nx1x<eltty>> to
+    //                                 vector<1xnxelty>
+    // with:
+    //   vector.shape_cast %0 : vector<nx1x<eltty>> to vector<1xnxelty>
+    //
+    // Source with leading unit dim (inverse) is also replaced. Unit dim must
+    // be fixed. Non-unit can be scalable.
+    if (resType.getRank() == 2 &&
+        ((resType.getShape().front() == 1 &&
+          !resType.getScalableDims().front()) ||
+         (resType.getShape().back() == 1 &&
+          !resType.getScalableDims().back())) &&
+        transp == ArrayRef<int64_t>({1, 0})) {
+      rewriter.replaceOpWithNewOp<vector::ShapeCastOp>(op, resType, input);
+      return success();
     }
 
     if (inputType.isScalable())
-- 
GitLab


From 86fa4b2c46191fe6be88e38bb46487472f6892c9 Mon Sep 17 00:00:00 2001
From: Cyndy Ishida <cyndy_ishida@apple.com>
Date: Mon, 11 Dec 2023 13:33:36 -0800
Subject: [PATCH 182/349] [readtapi] Swap anon namespaces in favor of
 annotating `static`, NFC (#75078)

---
 llvm/tools/llvm-readtapi/llvm-readtapi.cpp | 37 +++++++++++-----------
 1 file changed, 18 insertions(+), 19 deletions(-)

diff --git a/llvm/tools/llvm-readtapi/llvm-readtapi.cpp b/llvm/tools/llvm-readtapi/llvm-readtapi.cpp
index cb2b36072a55..64eff70dbfc7 100644
--- a/llvm/tools/llvm-readtapi/llvm-readtapi.cpp
+++ b/llvm/tools/llvm-readtapi/llvm-readtapi.cpp
@@ -56,30 +56,31 @@ public:
   }
 };
 
+struct Context {
+  std::vector<std::string> Inputs;
+  std::unique_ptr<llvm::raw_fd_stream> OutStream;
+  FileType WriteFT = FileType::TBD_V5;
+  bool Compact = false;
+  Architecture Arch = AK_unknown;
+};
+
 // Use unique exit code to differentiate failures not directly caused from
 // TextAPI operations. This is used for wrapping `compare` operations in
 // automation and scripting.
 const int NON_TAPI_EXIT_CODE = 2;
 const std::string TOOLNAME = "llvm-readtapi";
 ExitOnError ExitOnErr;
+} // anonymous namespace
 
 // Handle error reporting in cases where `ExitOnError` is not used.
-void reportError(Twine Message, int ExitCode = EXIT_FAILURE) {
+static void reportError(Twine Message, int ExitCode = EXIT_FAILURE) {
   errs() << TOOLNAME << ": error: " << Message << "\n";
   errs().flush();
   exit(ExitCode);
 }
 
-struct Context {
-  std::vector<std::string> Inputs;
-  std::unique_ptr<llvm::raw_fd_stream> OutStream;
-  FileType WriteFT = FileType::TBD_V5;
-  bool Compact = false;
-  Architecture Arch = AK_unknown;
-};
-
-std::unique_ptr<InterfaceFile> getInterfaceFile(const StringRef Filename,
-                                                bool ResetBanner = true) {
+static std::unique_ptr<InterfaceFile>
+getInterfaceFile(const StringRef Filename, bool ResetBanner = true) {
   ExitOnErr.setBanner(TOOLNAME + ": error: '" + Filename.str() + "' ");
   ErrorOr<std::unique_ptr<MemoryBuffer>> BufferOrErr =
       MemoryBuffer::getFile(Filename);
@@ -94,7 +95,7 @@ std::unique_ptr<InterfaceFile> getInterfaceFile(const StringRef Filename,
   return std::move(*IF);
 }
 
-bool handleCompareAction(const Context &Ctx) {
+static bool handleCompareAction(const Context &Ctx) {
   if (Ctx.Inputs.size() != 2)
     reportError("compare only supports two input files",
                 /*ExitCode=*/NON_TAPI_EXIT_CODE);
@@ -109,8 +110,8 @@ bool handleCompareAction(const Context &Ctx) {
   return DiffEngine(LeftIF.get(), RightIF.get()).compareFiles(OS);
 }
 
-bool handleWriteAction(const Context &Ctx,
-                       std::unique_ptr<InterfaceFile> Out = nullptr) {
+static bool handleWriteAction(const Context &Ctx,
+                              std::unique_ptr<InterfaceFile> Out = nullptr) {
   if (!Out) {
     if (Ctx.Inputs.size() != 1)
       reportError("write only supports one input file");
@@ -121,7 +122,7 @@ bool handleWriteAction(const Context &Ctx,
   return EXIT_SUCCESS;
 }
 
-bool handleMergeAction(const Context &Ctx) {
+static bool handleMergeAction(const Context &Ctx) {
   if (Ctx.Inputs.size() < 2)
     reportError("merge requires at least two input files");
 
@@ -144,8 +145,8 @@ bool handleMergeAction(const Context &Ctx) {
 using IFOperation =
     std::function<llvm::Expected<std::unique_ptr<InterfaceFile>>(
         const llvm::MachO::InterfaceFile &, Architecture)>;
-bool handleSingleFileAction(const Context &Ctx, const StringRef Action,
-                            IFOperation act) {
+static bool handleSingleFileAction(const Context &Ctx, const StringRef Action,
+                                   IFOperation act) {
   if (Ctx.Inputs.size() != 1)
     reportError(Action + " only supports one input file");
   if (Ctx.Arch == AK_unknown)
@@ -159,8 +160,6 @@ bool handleSingleFileAction(const Context &Ctx, const StringRef Action,
   return handleWriteAction(Ctx, std::move(*OutIF));
 }
 
-} // anonymous namespace
-
 int main(int Argc, char **Argv) {
   InitLLVM X(Argc, Argv);
   BumpPtrAllocator A;
-- 
GitLab


From 29ee66f4a0967e43a035f147c960743c7b640f2f Mon Sep 17 00:00:00 2001
From: Mikhail Gudim <mgudim@gmail.com>
Date: Mon, 11 Dec 2023 16:34:13 -0500
Subject: [PATCH 183/349] [RISCV] Macro-fusion support for veyron-v1 CPU.
 (#70012)

Support was added for the following fusions:
  auipc-addi, slli-srli, ld-add
Some parts of the code became repetative, so small refactoring of
existing lui-addi fusion was done.
---
 llvm/lib/Target/RISCV/RISCVFeatures.td        |  19 ++-
 llvm/lib/Target/RISCV/RISCVMacroFusion.cpp    | 121 +++++++++++--
 llvm/lib/Target/RISCV/RISCVProcessors.td      |   2 +-
 llvm/lib/Target/RISCV/RISCVSubtarget.h        |   5 +-
 .../CodeGen/RISCV/macro-fusions-veyron-v1.mir | 159 ++++++++++++++++++
 5 files changed, 285 insertions(+), 21 deletions(-)
 create mode 100644 llvm/test/CodeGen/RISCV/macro-fusions-veyron-v1.mir

diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 7d142d38d0f9..294927aecb94 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -970,6 +970,16 @@ def TuneLUIADDIFusion
     : SubtargetFeature<"lui-addi-fusion", "HasLUIADDIFusion",
                        "true", "Enable LUI+ADDI macrofusion">;
 
+def TuneAUIPCADDIFusion
+    : SubtargetFeature<"auipc-addi-fusion", "HasAUIPCADDIFusion",
+                       "true", "Enable AUIPC+ADDI macrofusion">;
+def TuneShiftedZExtFusion
+    : SubtargetFeature<"shifted-zext-fusion", "HasShiftedZExtFusion",
+                       "true", "Enable SLLI+SRLI to be fused when computing (shifted) zero extension">;
+def TuneLDADDFusion
+    : SubtargetFeature<"ld-add-fusion", "HasLDADDFusion",
+                       "true", "Enable LD+ADD macrofusion.">;
+
 def TuneNoDefaultUnroll
     : SubtargetFeature<"no-default-unroll", "EnableDefaultUnroll", "false",
                        "Disable default unroll preference.">;
@@ -987,9 +997,12 @@ def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
                                    [TuneNoDefaultUnroll,
                                     TuneShortForwardBranchOpt]>;
 
-def TuneVentanaVeyron : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron",
-                                         "Ventana-Veyron Series processors",
-                                         [TuneLUIADDIFusion]>;
+def TuneVeyronFusions : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron",
+                                         "Ventana Veyron-Series processors",
+                                         [TuneLUIADDIFusion,
+                                          TuneAUIPCADDIFusion,
+                                          TuneShiftedZExtFusion,
+                                          TuneLDADDFusion]>;
 
 // Assume that lock-free native-width atomics are available, even if the target
 // and operating system combination would not usually provide them. The user
diff --git a/llvm/lib/Target/RISCV/RISCVMacroFusion.cpp b/llvm/lib/Target/RISCV/RISCVMacroFusion.cpp
index 02a8d5c18fe1..02ea5270823d 100644
--- a/llvm/lib/Target/RISCV/RISCVMacroFusion.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMacroFusion.cpp
@@ -18,6 +18,101 @@
 
 using namespace llvm;
 
+static bool checkRegisters(Register FirstDest, const MachineInstr &SecondMI) {
+  if (!SecondMI.getOperand(1).isReg())
+    return false;
+
+  if (SecondMI.getOperand(1).getReg() != FirstDest)
+    return false;
+
+  // If the input is virtual make sure this is the only user.
+  if (FirstDest.isVirtual()) {
+    auto &MRI = SecondMI.getMF()->getRegInfo();
+    return MRI.hasOneNonDBGUse(FirstDest);
+  }
+
+  return SecondMI.getOperand(0).getReg() == FirstDest;
+}
+
+// Fuse load with add:
+// add rd, rs1, rs2
+// ld rd, 0(rd)
+static bool isLDADD(const MachineInstr *FirstMI, const MachineInstr &SecondMI) {
+  if (SecondMI.getOpcode() != RISCV::LD)
+    return false;
+
+  if (!SecondMI.getOperand(2).isImm())
+    return false;
+
+  if (SecondMI.getOperand(2).getImm() != 0)
+    return false;
+
+  // Given SecondMI, when FirstMI is unspecified, we must return
+  // if SecondMI may be part of a fused pair at all.
+  if (!FirstMI)
+    return true;
+
+  if (FirstMI->getOpcode() != RISCV::ADD)
+    return true;
+
+  return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI);
+}
+
+// Fuse these patterns:
+//
+// slli rd, rs1, 32
+// srli rd, rd, x
+// where 0 <= x <= 32
+//
+// and
+//
+// slli rd, rs1, 48
+// srli rd, rd, x
+static bool isShiftedZExt(const MachineInstr *FirstMI,
+                          const MachineInstr &SecondMI) {
+  if (SecondMI.getOpcode() != RISCV::SRLI)
+    return false;
+
+  if (!SecondMI.getOperand(2).isImm())
+    return false;
+
+  unsigned SRLIImm = SecondMI.getOperand(2).getImm();
+  bool IsShiftBy48 = SRLIImm == 48;
+  if (SRLIImm > 32 && !IsShiftBy48)
+    return false;
+
+  // Given SecondMI, when FirstMI is unspecified, we must return
+  // if SecondMI may be part of a fused pair at all.
+  if (!FirstMI)
+    return true;
+
+  if (FirstMI->getOpcode() != RISCV::SLLI)
+    return false;
+
+  unsigned SLLIImm = FirstMI->getOperand(2).getImm();
+  if (IsShiftBy48 ? (SLLIImm != 48) : (SLLIImm != 32))
+    return false;
+
+  return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI);
+}
+
+// Fuse AUIPC followed by ADDI
+// auipc rd, imm20
+// addi rd, rd, imm12
+static bool isAUIPCADDI(const MachineInstr *FirstMI,
+                        const MachineInstr &SecondMI) {
+  if (SecondMI.getOpcode() != RISCV::ADDI)
+    return false;
+  // Assume the 1st instr to be a wildcard if it is unspecified.
+  if (!FirstMI)
+    return true;
+
+  if (FirstMI->getOpcode() != RISCV::AUIPC)
+    return false;
+
+  return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI);
+}
+
 // Fuse LUI followed by ADDI or ADDIW.
 // rd = imm[31:0] which decomposes to
 // lui rd, imm[31:12]
@@ -27,7 +122,6 @@ static bool isLUIADDI(const MachineInstr *FirstMI,
   if (SecondMI.getOpcode() != RISCV::ADDI &&
       SecondMI.getOpcode() != RISCV::ADDIW)
     return false;
-
   // Assume the 1st instr to be a wildcard if it is unspecified.
   if (!FirstMI)
     return true;
@@ -35,21 +129,7 @@ static bool isLUIADDI(const MachineInstr *FirstMI,
   if (FirstMI->getOpcode() != RISCV::LUI)
     return false;
 
-  Register FirstDest = FirstMI->getOperand(0).getReg();
-
-  // Destination of LUI should be the ADDI(W) source register.
-  if (SecondMI.getOperand(1).getReg() != FirstDest)
-    return false;
-
-  // If the input is virtual make sure this is the only user.
-  if (FirstDest.isVirtual()) {
-    auto &MRI = SecondMI.getMF()->getRegInfo();
-    return MRI.hasOneNonDBGUse(FirstDest);
-  }
-
-  // If the FirstMI destination is non-virtual, it should match the SecondMI
-  // destination.
-  return SecondMI.getOperand(0).getReg() == FirstDest;
+  return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI);
 }
 
 static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
@@ -61,6 +141,15 @@ static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
   if (ST.hasLUIADDIFusion() && isLUIADDI(FirstMI, SecondMI))
     return true;
 
+  if (ST.hasAUIPCADDIFusion() && isAUIPCADDI(FirstMI, SecondMI))
+    return true;
+
+  if (ST.hasShiftedZExtFusion() && isShiftedZExt(FirstMI, SecondMI))
+    return true;
+
+  if (ST.hasLDADDFusion() && isLDADD(FirstMI, SecondMI))
+    return true;
+
   return false;
 }
 
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 90ba99d3f845..58989fd716fa 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -254,7 +254,7 @@ def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
                                              FeatureStdExtZicbop,
                                              FeatureStdExtZicboz,
                                              FeatureVendorXVentanaCondOps],
-                                             [TuneVentanaVeyron]>;
+                                             [TuneVeyronFusions]>;
 
 def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                           NoSchedModel,
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 40720826b90b..23d56cfa6e4e 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -193,7 +193,10 @@ public:
     return UserReservedRegister[i];
   }
 
-  bool hasMacroFusion() const { return hasLUIADDIFusion(); }
+  bool hasMacroFusion() const {
+    return hasLUIADDIFusion() || hasAUIPCADDIFusion() ||
+           hasShiftedZExtFusion() || hasLDADDFusion();
+  }
 
   // Vector codegen related methods.
   bool hasVInstructions() const { return HasStdExtZve32x; }
diff --git a/llvm/test/CodeGen/RISCV/macro-fusions-veyron-v1.mir b/llvm/test/CodeGen/RISCV/macro-fusions-veyron-v1.mir
new file mode 100644
index 000000000000..6d1e92e997b3
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/macro-fusions-veyron-v1.mir
@@ -0,0 +1,159 @@
+# REQUIRES: asserts
+# RUN: llc -mtriple=riscv64-linux-gnu  -mcpu=veyron-v1 -x=mir < %s \
+# RUN:   -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \
+# RUN:   -mattr=+lui-addi-fusion,+auipc-addi-fusion,+shifted-zext-fusion,+ld-add-fusion \
+# RUN:   | FileCheck %s
+
+# CHECK: lui_addi:%bb.0
+# CHECK: Macro fuse: {{.*}}LUI - ADDI
+---
+name: lui_addi
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10
+    %1:gpr = COPY $x10
+    %2:gpr = LUI 1
+    %3:gpr = XORI %1, 2
+    %4:gpr = ADDI %2, 3
+    $x10 = COPY %3
+    $x11 = COPY %4
+    PseudoRET
+...
+
+# CHECK: auipc_addi
+# CHECK: Macro fuse: {{.*}}AUIPC - ADDI
+---
+name: auipc_addi
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10
+    %1:gpr = COPY $x10
+    %2:gpr = AUIPC 1
+    %3:gpr = XORI %1, 2
+    %4:gpr = ADDI %2, 3
+    $x10 = COPY %3
+    $x11 = COPY %4
+    PseudoRET
+...
+
+# CHECK: slli_srli
+# CHECK: Macro fuse: {{.*}}SLLI - SRLI
+---
+name: slli_srli
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10
+    %1:gpr = COPY $x10
+    %2:gpr = SLLI %1, 32
+    %3:gpr = XORI %1, 3
+    %4:gpr = SRLI %2, 4
+    $x10 = COPY %3
+    $x11 = COPY %4
+    PseudoRET
+...
+
+# CHECK: slli_srli_48
+# CHECK: Macro fuse: {{.*}}SLLI - SRLI
+---
+name: slli_srli_48
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10
+    %1:gpr = COPY $x10
+    %2:gpr = SLLI %1, 48
+    %3:gpr = XORI %1, 3
+    %4:gpr = SRLI %2, 48
+    $x10 = COPY %3
+    $x11 = COPY %4
+    PseudoRET
+...
+
+# CHECK: slli_srli_no_fusion_0
+# CHECK-NOT: Macro fuse: {{.*}}SLLI - SRLI
+---
+name: slli_srli_no_fusion_0
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10
+    %1:gpr = COPY $x10
+    %2:gpr = SLLI %1, 32
+    %3:gpr = XORI %1, 3
+    %4:gpr = SRLI %2, 33
+    $x10 = COPY %3
+    $x11 = COPY %4
+    PseudoRET
+...
+
+# CHECK: slli_srli_no_fusion_1
+# CHECK-NOT: Macro fuse: {{.*}}SLLI - SRLI
+---
+name: slli_srli_no_fusion_1
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10
+    %1:gpr = COPY $x10
+    %2:gpr = SLLI %1, 48
+    %3:gpr = XORI %1, 3
+    %4:gpr = SRLI %2, 4
+    $x10 = COPY %3
+    $x11 = COPY %4
+    PseudoRET
+...
+
+# CHECK: slli_srli_no_fusion_2
+# CHECK-NOT: Macro fuse: {{.*}}SLLI - SRLI
+---
+name: slli_srli_no_fusion_2
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10
+    %1:gpr = COPY $x10
+    %2:gpr = SLLI %1, 31
+    %3:gpr = XORI %1, 3
+    %4:gpr = SRLI %2, 4
+    $x10 = COPY %3
+    $x11 = COPY %4
+    PseudoRET
+...
+
+# CHECK: slli_srli_no_fusion_3
+# CHECK-NOT: Macro fuse: {{.*}}SLLI - SRLI
+---
+name: slli_srli_no_fusion_3
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10
+    %1:gpr = COPY $x10
+    %2:gpr = SLLI %1, 31
+    %3:gpr = XORI %1, 3
+    %4:gpr = SRLI %2, 48
+    $x10 = COPY %3
+    $x11 = COPY %4
+    PseudoRET
+...
+
+# CHECK: ld_add
+# CHECK: Macro fuse: {{.*}}ADD - LD
+---
+name: ld_add
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+    %1:gpr = COPY $x10
+    %2:gpr = COPY $x11
+    %3:gpr = ADD %1, %2
+    %4:gpr = XORI %2, 3
+    %5:gpr = LD %3, 0
+    $x10 = COPY %4
+    $x11 = COPY %5
+    PseudoRET
+...
-- 
GitLab


From 6e761f3a04e59dd8aa1a0d3c29d81a85f5351472 Mon Sep 17 00:00:00 2001
From: Fangrui Song <i@maskray.me>
Date: Mon, 11 Dec 2023 13:45:57 -0800
Subject: [PATCH 184/349] [bazel] Port #73257
 54397f9ac128568838f2ac7bfc8e1f94b3eb264d

---
 utils/bazel/llvm-project-overlay/llvm/unittests/BUILD.bazel | 1 +
 1 file changed, 1 insertion(+)

diff --git a/utils/bazel/llvm-project-overlay/llvm/unittests/BUILD.bazel b/utils/bazel/llvm-project-overlay/llvm/unittests/BUILD.bazel
index 42b417548d94..d2bcfc14ff75 100644
--- a/utils/bazel/llvm-project-overlay/llvm/unittests/BUILD.bazel
+++ b/utils/bazel/llvm-project-overlay/llvm/unittests/BUILD.bazel
@@ -309,6 +309,7 @@ cc_test(
         "//llvm:JITLink",
         "//llvm:MC",
         "//llvm:Object",
+        "//llvm:OrcDebugging",
         "//llvm:OrcJIT",
         "//llvm:OrcShared",
         "//llvm:OrcTargetProcess",
-- 
GitLab


From 85c395393480a77736fc7ad10f35e67f6cae6fed Mon Sep 17 00:00:00 2001
From: Lang Hames <lhames@gmail.com>
Date: Mon, 11 Dec 2023 14:06:15 -0800
Subject: [PATCH 185/349] [ORC][MachO] Expose SimpleMachOHeaderMU and related
 utilities.

SimpleMachOHeaderMU can be used as a convenient base for classes that create
custom MachO headers. Instances of these custom classes can be used by passing
a MachOHeaderMUBuilder using the MachOPlatform extensions added in ef314d39b92.
---
 .../llvm/ExecutionEngine/Orc/MachOPlatform.h  |  52 ++++-
 .../lib/ExecutionEngine/Orc/MachOPlatform.cpp | 196 +++++++++---------
 2 files changed, 141 insertions(+), 107 deletions(-)

diff --git a/llvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h b/llvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h
index 3a622281f227..db7855e69a66 100644
--- a/llvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h
+++ b/llvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h
@@ -52,8 +52,9 @@ public:
   using MachOHeaderMUBuilder =
       unique_function<std::unique_ptr<MaterializationUnit>(MachOPlatform &MOP)>;
 
-  static std::unique_ptr<MaterializationUnit>
-  defaultMachOHeaderBuilder(MachOPlatform &MOP);
+  /// Simple MachO header graph builder.
+  static inline std::unique_ptr<MaterializationUnit>
+  buildSimpleMachOHeaderMU(MachOPlatform &MOP);
 
   /// Try to create a MachOPlatform instance, adding the ORC runtime to the
   /// given JITDylib.
@@ -96,14 +97,14 @@ public:
   static Expected<std::unique_ptr<MachOPlatform>>
   Create(ExecutionSession &ES, ObjectLinkingLayer &ObjLinkingLayer,
          JITDylib &PlatformJD, std::unique_ptr<DefinitionGenerator> OrcRuntime,
-         MachOHeaderMUBuilder BuildMachOHeaderMU = defaultMachOHeaderBuilder,
+         MachOHeaderMUBuilder BuildMachOHeaderMU = buildSimpleMachOHeaderMU,
          std::optional<SymbolAliasMap> RuntimeAliases = std::nullopt);
 
   /// Construct using a path to the ORC runtime.
   static Expected<std::unique_ptr<MachOPlatform>>
   Create(ExecutionSession &ES, ObjectLinkingLayer &ObjLinkingLayer,
          JITDylib &PlatformJD, const char *OrcRuntimePath,
-         MachOHeaderMUBuilder BuildMachOHeaderMU = defaultMachOHeaderBuilder,
+         MachOHeaderMUBuilder BuildMachOHeaderMU = buildSimpleMachOHeaderMU,
          std::optional<SymbolAliasMap> RuntimeAliases = std::nullopt);
 
   ExecutionSession &getExecutionSession() const { return ES; }
@@ -332,6 +333,49 @@ private:
   std::atomic<BootstrapInfo *> Bootstrap;
 };
 
+// Generates a MachO header.
+class SimpleMachOHeaderMU : public MaterializationUnit {
+public:
+  SimpleMachOHeaderMU(MachOPlatform &MOP, SymbolStringPtr HeaderStartSymbol);
+  StringRef getName() const override { return "MachOHeaderMU"; }
+  void materialize(std::unique_ptr<MaterializationResponsibility> R) override;
+  void discard(const JITDylib &JD, const SymbolStringPtr &Sym) override;
+
+protected:
+  virtual jitlink::Block &createHeaderBlock(JITDylib &JD, jitlink::LinkGraph &G,
+                                            jitlink::Section &HeaderSection);
+
+private:
+  struct HeaderSymbol {
+    const char *Name;
+    uint64_t Offset;
+  };
+
+  static constexpr HeaderSymbol AdditionalHeaderSymbols[] = {
+      {"___mh_executable_header", 0}};
+
+  void addMachOHeader(JITDylib &JD, jitlink::LinkGraph &G,
+                      const SymbolStringPtr &InitializerSymbol);
+  static MaterializationUnit::Interface
+  createHeaderInterface(MachOPlatform &MOP,
+                        const SymbolStringPtr &HeaderStartSymbol);
+
+  MachOPlatform &MOP;
+};
+
+/// Simple MachO header graph builder.
+inline std::unique_ptr<MaterializationUnit>
+MachOPlatform::buildSimpleMachOHeaderMU(MachOPlatform &MOP) {
+  return std::make_unique<SimpleMachOHeaderMU>(MOP, MOP.MachOHeaderStartSymbol);
+}
+
+struct MachOHeaderInfo {
+  size_t PageSize = 0;
+  uint32_t CPUType = 0;
+  uint32_t CPUSubType = 0;
+};
+MachOHeaderInfo getMachOHeaderInfoFromTriple(const Triple &TT);
+
 } // end namespace orc
 } // end namespace llvm
 
diff --git a/llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp b/llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
index 1a65bfc3234f..9057300bf043 100644
--- a/llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
+++ b/llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
@@ -116,101 +116,6 @@ std::unique_ptr<jitlink::LinkGraph> createPlatformGraph(MachOPlatform &MOP,
                                               jitlink::getGenericEdgeKindName);
 }
 
-// Generates a MachO header.
-class MachOHeaderMaterializationUnit : public MaterializationUnit {
-public:
-  MachOHeaderMaterializationUnit(MachOPlatform &MOP,
-                                 SymbolStringPtr HeaderStartSymbol)
-      : MaterializationUnit(
-            createHeaderInterface(MOP, std::move(HeaderStartSymbol))),
-        MOP(MOP) {}
-
-  StringRef getName() const override { return "MachOHeaderMU"; }
-
-  void materialize(std::unique_ptr<MaterializationResponsibility> R) override {
-    auto G = createPlatformGraph(MOP, "<MachOHeaderMU>");
-    addMachOHeader(*G, MOP, R->getInitializerSymbol());
-    MOP.getObjectLinkingLayer().emit(std::move(R), std::move(G));
-  }
-
-  void discard(const JITDylib &JD, const SymbolStringPtr &Sym) override {}
-
-  static void addMachOHeader(jitlink::LinkGraph &G, MachOPlatform &MOP,
-                             const SymbolStringPtr &InitializerSymbol) {
-    auto &HeaderSection = G.createSection("__header", MemProt::Read);
-    auto &HeaderBlock = createHeaderBlock(G, HeaderSection);
-
-    // Init symbol is header-start symbol.
-    G.addDefinedSymbol(HeaderBlock, 0, *InitializerSymbol,
-                       HeaderBlock.getSize(), jitlink::Linkage::Strong,
-                       jitlink::Scope::Default, false, true);
-    for (auto &HS : AdditionalHeaderSymbols)
-      G.addDefinedSymbol(HeaderBlock, HS.Offset, HS.Name, HeaderBlock.getSize(),
-                         jitlink::Linkage::Strong, jitlink::Scope::Default,
-                         false, true);
-  }
-
-private:
-  struct HeaderSymbol {
-    const char *Name;
-    uint64_t Offset;
-  };
-
-  static constexpr HeaderSymbol AdditionalHeaderSymbols[] = {
-      {"___mh_executable_header", 0}};
-
-  static jitlink::Block &createHeaderBlock(jitlink::LinkGraph &G,
-                                           jitlink::Section &HeaderSection) {
-    MachO::mach_header_64 Hdr;
-    Hdr.magic = MachO::MH_MAGIC_64;
-    switch (G.getTargetTriple().getArch()) {
-    case Triple::aarch64:
-      Hdr.cputype = MachO::CPU_TYPE_ARM64;
-      Hdr.cpusubtype = MachO::CPU_SUBTYPE_ARM64_ALL;
-      break;
-    case Triple::x86_64:
-      Hdr.cputype = MachO::CPU_TYPE_X86_64;
-      Hdr.cpusubtype = MachO::CPU_SUBTYPE_X86_64_ALL;
-      break;
-    default:
-      llvm_unreachable("Unrecognized architecture");
-    }
-    Hdr.filetype = MachO::MH_DYLIB; // Custom file type?
-    Hdr.ncmds = 0;
-    Hdr.sizeofcmds = 0;
-    Hdr.flags = 0;
-    Hdr.reserved = 0;
-
-    if (G.getEndianness() != llvm::endianness::native)
-      MachO::swapStruct(Hdr);
-
-    auto HeaderContent = G.allocateContent(
-        ArrayRef<char>(reinterpret_cast<const char *>(&Hdr), sizeof(Hdr)));
-
-    return G.createContentBlock(HeaderSection, HeaderContent, ExecutorAddr(), 8,
-                                0);
-  }
-
-  static MaterializationUnit::Interface
-  createHeaderInterface(MachOPlatform &MOP,
-                        const SymbolStringPtr &HeaderStartSymbol) {
-    SymbolFlagsMap HeaderSymbolFlags;
-
-    HeaderSymbolFlags[HeaderStartSymbol] = JITSymbolFlags::Exported;
-    for (auto &HS : AdditionalHeaderSymbols)
-      HeaderSymbolFlags[MOP.getExecutionSession().intern(HS.Name)] =
-          JITSymbolFlags::Exported;
-
-    return MaterializationUnit::Interface(std::move(HeaderSymbolFlags),
-                                          HeaderStartSymbol);
-  }
-
-  MachOPlatform &MOP;
-};
-
-constexpr MachOHeaderMaterializationUnit::HeaderSymbol
-    MachOHeaderMaterializationUnit::AdditionalHeaderSymbols[];
-
 // Creates a Bootstrap-Complete LinkGraph to run deferred actions.
 class MachOPlatformCompleteBootstrapMaterializationUnit
     : public MaterializationUnit {
@@ -350,12 +255,6 @@ struct ObjCImageInfoFlags {
 namespace llvm {
 namespace orc {
 
-std::unique_ptr<MaterializationUnit>
-MachOPlatform::defaultMachOHeaderBuilder(MachOPlatform &MOP) {
-  return std::make_unique<MachOHeaderMaterializationUnit>(
-      MOP, SymbolStringPtr(MOP.getMachOHeaderStartSymbol()));
-}
-
 Expected<std::unique_ptr<MachOPlatform>>
 MachOPlatform::Create(ExecutionSession &ES, ObjectLinkingLayer &ObjLinkingLayer,
                       JITDylib &PlatformJD,
@@ -598,8 +497,7 @@ MachOPlatform::MachOPlatform(
   //    the support methods callable. The bootstrap is now complete.
 
   // Step (1) Add header materialization unit and request.
-  if ((Err = PlatformJD.define(std::make_unique<MachOHeaderMaterializationUnit>(
-           *this, MachOHeaderStartSymbol))))
+  if ((Err = PlatformJD.define(this->BuildMachOHeaderMU(*this))))
     return;
   if ((Err = ES.lookup(&PlatformJD, MachOHeaderStartSymbol).takeError()))
     return;
@@ -1767,5 +1665,97 @@ Error MachOPlatform::MachOPlatformPlugin::addSymbolTableRegistration(
 
   return Error::success();
 }
+
+template <typename MachOTraits>
+jitlink::Block &createTrivialHeaderBlock(MachOPlatform &MOP,
+                                         jitlink::LinkGraph &G,
+                                         jitlink::Section &HeaderSection) {
+  auto HdrInfo =
+      getMachOHeaderInfoFromTriple(MOP.getExecutionSession().getTargetTriple());
+  MachOBuilder<MachOTraits> B(HdrInfo.PageSize);
+
+  B.Header.filetype = MachO::MH_DYLIB;
+  B.Header.cputype = HdrInfo.CPUType;
+  B.Header.cpusubtype = HdrInfo.CPUSubType;
+
+  auto HeaderContent = G.allocateBuffer(B.layout());
+  B.write(HeaderContent);
+
+  return G.createContentBlock(HeaderSection, HeaderContent, ExecutorAddr(), 8,
+                              0);
+}
+
+SimpleMachOHeaderMU::SimpleMachOHeaderMU(MachOPlatform &MOP,
+                                         SymbolStringPtr HeaderStartSymbol)
+    : MaterializationUnit(
+          createHeaderInterface(MOP, std::move(HeaderStartSymbol))),
+      MOP(MOP) {}
+
+void SimpleMachOHeaderMU::materialize(
+    std::unique_ptr<MaterializationResponsibility> R) {
+  auto G = createPlatformGraph(MOP, "<MachOHeaderMU>");
+  addMachOHeader(R->getTargetJITDylib(), *G, R->getInitializerSymbol());
+  MOP.getObjectLinkingLayer().emit(std::move(R), std::move(G));
+}
+
+void SimpleMachOHeaderMU::discard(const JITDylib &JD,
+                                  const SymbolStringPtr &Sym) {}
+
+void SimpleMachOHeaderMU::addMachOHeader(
+    JITDylib &JD, jitlink::LinkGraph &G,
+    const SymbolStringPtr &InitializerSymbol) {
+  auto &HeaderSection = G.createSection("__header", MemProt::Read);
+  auto &HeaderBlock = createHeaderBlock(JD, G, HeaderSection);
+
+  // Init symbol is header-start symbol.
+  G.addDefinedSymbol(HeaderBlock, 0, *InitializerSymbol, HeaderBlock.getSize(),
+                     jitlink::Linkage::Strong, jitlink::Scope::Default, false,
+                     true);
+  for (auto &HS : AdditionalHeaderSymbols)
+    G.addDefinedSymbol(HeaderBlock, HS.Offset, HS.Name, HeaderBlock.getSize(),
+                       jitlink::Linkage::Strong, jitlink::Scope::Default, false,
+                       true);
+}
+
+jitlink::Block &
+SimpleMachOHeaderMU::createHeaderBlock(JITDylib &JD, jitlink::LinkGraph &G,
+                                       jitlink::Section &HeaderSection) {
+  switch (MOP.getExecutionSession().getTargetTriple().getArch()) {
+  case Triple::aarch64:
+  case Triple::x86_64:
+    return createTrivialHeaderBlock<MachO64LE>(MOP, G, HeaderSection);
+  default:
+    llvm_unreachable("Unsupported architecture");
+  }
+}
+
+MaterializationUnit::Interface SimpleMachOHeaderMU::createHeaderInterface(
+    MachOPlatform &MOP, const SymbolStringPtr &HeaderStartSymbol) {
+  SymbolFlagsMap HeaderSymbolFlags;
+
+  HeaderSymbolFlags[HeaderStartSymbol] = JITSymbolFlags::Exported;
+  for (auto &HS : AdditionalHeaderSymbols)
+    HeaderSymbolFlags[MOP.getExecutionSession().intern(HS.Name)] =
+        JITSymbolFlags::Exported;
+
+  return MaterializationUnit::Interface(std::move(HeaderSymbolFlags),
+                                        HeaderStartSymbol);
+}
+
+MachOHeaderInfo getMachOHeaderInfoFromTriple(const Triple &TT) {
+  switch (TT.getArch()) {
+  case Triple::aarch64:
+    return {/* PageSize   = */ 16 * 1024,
+            /* CPUType    = */ MachO::CPU_TYPE_ARM64,
+            /* CPUSubType = */ MachO::CPU_SUBTYPE_ARM64_ALL};
+  case Triple::x86_64:
+    return {/* PageSize   = */ 4 * 1024,
+            /* CPUType    = */ MachO::CPU_TYPE_X86_64,
+            /* CPUSubType = */ MachO::CPU_SUBTYPE_X86_64_ALL};
+  default:
+    llvm_unreachable("Unrecognized architecture");
+  }
+}
+
 } // End namespace orc.
 } // End namespace llvm.
-- 
GitLab


From a37fa2a8e1c827f1ff04b0b13b83cf97eefe74c0 Mon Sep 17 00:00:00 2001
From: Augusto Noronha <augusto2112@me.com>
Date: Mon, 11 Dec 2023 14:40:43 -0800
Subject: [PATCH 186/349] [lldb] Disable new TestLocationListLookup when clang
 version is <= 11 (#75102)

The newly introduced LocationListLookupTestCase.test_loclist_expr test
fails with older clangs.
---
 .../location-list-lookup/TestLocationListLookup.py               | 1 +
 1 file changed, 1 insertion(+)

diff --git a/lldb/test/API/functionalities/location-list-lookup/TestLocationListLookup.py b/lldb/test/API/functionalities/location-list-lookup/TestLocationListLookup.py
index ccee3bfde3f5..feea14ff355e 100644
--- a/lldb/test/API/functionalities/location-list-lookup/TestLocationListLookup.py
+++ b/lldb/test/API/functionalities/location-list-lookup/TestLocationListLookup.py
@@ -43,6 +43,7 @@ class LocationListLookupTestCase(TestBase):
         self.build()
         self.check_local_vars(self.launch(), check_expr=False)
 
+    @skipIf(compiler="clang", compiler_version=["<=", "11.0"])
     @skipUnlessDarwin
     def test_loclist_expr(self):
         self.build()
-- 
GitLab


From 876816ff183b6fe4e23ba2a01dfd9cd0c52bf056 Mon Sep 17 00:00:00 2001
From: James Y Knight <jyknight@google.com>
Date: Mon, 11 Dec 2023 17:55:07 -0500
Subject: [PATCH 187/349] [AArch64] Set MaxAtomicSizeInBitsSupported. (#74385)

This will result in larger atomic operations getting expanded to
`__atomic_*` libcalls via AtomicExpandPass, which matches what Clang
already does in the frontend.

Additionally, adjust some comments, and remove partial code dealing with
larger-than-128bit atomics, as it's now unreachable.

AArch64 always supports 128-bit atomics, so there's no conditionals
needed here. (Though: we really ought to require that a 128-bit load is
available, not just a cmpxchg, which would mean conditioning on LSE2.
But that's future work.)

The arm64-irtranslator.ll test was adjusted as it was using an i258 type
as a hack to avoid IR atomic lowering to test GlobalISel behavior. Pass
-mattr=+lse and use i32, instead, to accomplish that goal in a way that
continues to work.
---
 .../Target/AArch64/AArch64ISelLowering.cpp    |  15 +-
 .../AArch64/GlobalISel/arm64-irtranslator.ll  | 165 +++++++-----------
 llvm/test/CodeGen/AArch64/atomic-oversize.ll  |  11 ++
 3 files changed, 83 insertions(+), 108 deletions(-)
 create mode 100644 llvm/test/CodeGen/AArch64/atomic-oversize.ll

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index bc74d44a8fbc..3882e843fb69 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1651,6 +1651,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
   PredictableSelectIsExpensive = Subtarget->predictableSelectIsExpensive();
 
   IsStrictFPEnabled = true;
+  setMaxAtomicSizeInBitsSupported(128);
 }
 
 void AArch64TargetLowering::addTypeForNEON(MVT VT) {
@@ -24909,15 +24910,21 @@ AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
                              : AtomicExpansionKind::LLSC;
 }
 
-// For the real atomic operations, we have ldxr/stxr up to 128 bits,
+// The "default" for integer RMW operations is to expand to an LL/SC loop.
+// However, with the LSE instructions (or outline-atomics mode, which provides
+// library routines in place of the LSE-instructions), we can directly emit many
+// operations instead.
+//
+// Floating-point operations are always emitted to a cmpxchg loop, because they
+// may trigger a trap which aborts an LLSC sequence.
 TargetLowering::AtomicExpansionKind
 AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
+  unsigned Size = AI->getType()->getPrimitiveSizeInBits();
+  assert(Size <= 128 && "AtomicExpandPass should've handled larger sizes.");
+
   if (AI->isFloatingPointOperation())
     return AtomicExpansionKind::CmpXChg;
 
-  unsigned Size = AI->getType()->getPrimitiveSizeInBits();
-  if (Size > 128) return AtomicExpansionKind::None;
-
   bool CanUseLSE128 = Subtarget->hasLSE128() && Size == 128 &&
                       (AI->getOperation() == AtomicRMWInst::Xchg ||
                        AI->getOperation() == AtomicRMWInst::Or ||
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
index 575cd6b874e3..92ddc6309546 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -1,5 +1,5 @@
-; RUN: llc -O0 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
-; RUN: llc -O3 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O3
+; RUN: llc -O0 -aarch64-enable-atomic-cfg-tidy=0 -mattr=+lse -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+; RUN: llc -O3 -aarch64-enable-atomic-cfg-tidy=0 -mattr=+lse -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O3
 
 ; This file checks that the translation from llvm IR to generic MachineInstr
 ; is correct.
@@ -2077,190 +2077,147 @@ done:
 }
 
 ; Try a monotonic atomicrmw xchg
-; AArch64 will expand some atomicrmw's at the LLVM-IR level so we use a wide type to avoid this.
 define i32 @test_atomicrmw_xchg(ptr %addr) {
 ; CHECK-LABEL: name: test_atomicrmw_xchg
 ; CHECK:       bb.1 (%ir-block.{{[0-9]+}}):
 ; CHECK-NEXT:  liveins: $x0
 ; CHECK:         [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT:    [[VAL:%[0-9]+]]:_(s256) = G_CONSTANT i256 1
-; CHECK-NEXT:    [[OLDVALRES:%[0-9]+]]:_(s256) = G_ATOMICRMW_XCHG [[ADDR]](p0), [[VAL]] :: (load store monotonic (s256) on %ir.addr)
-; CHECK-NEXT:    [[RES:%[0-9]+]]:_(s32) = G_TRUNC [[OLDVALRES]]
-  %oldval = atomicrmw xchg ptr %addr, i256 1 monotonic
-  ; FIXME: We currently can't lower 'ret i256' and it's not the purpose of this
-  ;        test so work around it by truncating to i32 for now.
-  %oldval.trunc = trunc i256 %oldval to i32
-  ret i32 %oldval.trunc
+; CHECK-NEXT:    [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK-NEXT:    [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_XCHG [[ADDR]](p0), [[VAL]] :: (load store monotonic (s32) on %ir.addr)
+  %oldval = atomicrmw xchg ptr %addr, i32 1 monotonic
+  ret i32 %oldval
 }
 
 ; Try an acquire atomicrmw add
-; AArch64 will expand some atomicrmw's at the LLVM-IR level so we use a wide type to avoid this.
 define i32 @test_atomicrmw_add(ptr %addr) {
 ; CHECK-LABEL: name: test_atomicrmw_add
 ; CHECK:       bb.1 (%ir-block.{{[0-9]+}}):
 ; CHECK-NEXT:  liveins: $x0
 ; CHECK:         [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT:    [[VAL:%[0-9]+]]:_(s256) = G_CONSTANT i256 1
-; CHECK-NEXT:    [[OLDVALRES:%[0-9]+]]:_(s256) = G_ATOMICRMW_ADD [[ADDR]](p0), [[VAL]] :: (load store acquire (s256) on %ir.addr)
-; CHECK-NEXT:    [[RES:%[0-9]+]]:_(s32) = G_TRUNC [[OLDVALRES]]
-  %oldval = atomicrmw add ptr %addr, i256 1 acquire
-  ; FIXME: We currently can't lower 'ret i256' and it's not the purpose of this
-  ;        test so work around it by truncating to i32 for now.
-  %oldval.trunc = trunc i256 %oldval to i32
-  ret i32 %oldval.trunc
+; CHECK-NEXT:    [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK-NEXT:    [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[ADDR]](p0), [[VAL]] :: (load store acquire (s32) on %ir.addr)
+  %oldval = atomicrmw add ptr %addr, i32 1 acquire
+  ret i32 %oldval
 }
 
 ; Try a release atomicrmw sub
-; AArch64 will expand some atomicrmw's at the LLVM-IR level so we use a wide type to avoid this.
 define i32 @test_atomicrmw_sub(ptr %addr) {
 ; CHECK-LABEL: name: test_atomicrmw_sub
 ; CHECK:       bb.1 (%ir-block.{{[0-9]+}}):
 ; CHECK-NEXT:  liveins: $x0
 ; CHECK:         [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT:    [[VAL:%[0-9]+]]:_(s256) = G_CONSTANT i256 1
-; CHECK-NEXT:    [[OLDVALRES:%[0-9]+]]:_(s256) = G_ATOMICRMW_SUB [[ADDR]](p0), [[VAL]] :: (load store release (s256) on %ir.addr)
-; CHECK-NEXT:    [[RES:%[0-9]+]]:_(s32) = G_TRUNC [[OLDVALRES]]
-  %oldval = atomicrmw sub ptr %addr, i256 1 release
-  ; FIXME: We currently can't lower 'ret i256' and it's not the purpose of this
-  ;        test so work around it by truncating to i32 for now.
-  %oldval.trunc = trunc i256 %oldval to i32
-  ret i32 %oldval.trunc
+; CHECK-NEXT:    [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK-NEXT:    [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_SUB [[ADDR]](p0), [[VAL]] :: (load store release (s32) on %ir.addr)
+  %oldval = atomicrmw sub ptr %addr, i32 1 release
+  ret i32 %oldval
 }
 
 ; Try an acq_rel atomicrmw and
-; AArch64 will expand some atomicrmw's at the LLVM-IR level so we use a wide type to avoid this.
 define i32 @test_atomicrmw_and(ptr %addr) {
 ; CHECK-LABEL: name: test_atomicrmw_and
 ; CHECK:       bb.1 (%ir-block.{{[0-9]+}}):
 ; CHECK-NEXT:  liveins: $x0
 ; CHECK:         [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT:    [[VAL:%[0-9]+]]:_(s256) = G_CONSTANT i256 1
-; CHECK-NEXT:    [[OLDVALRES:%[0-9]+]]:_(s256) = G_ATOMICRMW_AND [[ADDR]](p0), [[VAL]] :: (load store acq_rel (s256) on %ir.addr)
-; CHECK-NEXT:    [[RES:%[0-9]+]]:_(s32) = G_TRUNC [[OLDVALRES]]
-  %oldval = atomicrmw and ptr %addr, i256 1 acq_rel
-  ; FIXME: We currently can't lower 'ret i256' and it's not the purpose of this
-  ;        test so work around it by truncating to i32 for now.
-  %oldval.trunc = trunc i256 %oldval to i32
-  ret i32 %oldval.trunc
-}
-
-; Try an seq_cst atomicrmw nand
-; AArch64 will expand some atomicrmw's at the LLVM-IR level so we use a wide type to avoid this.
+; CHECK-NEXT:    [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK-NEXT:    [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_AND [[ADDR]](p0), [[VAL]] :: (load store acq_rel (s32) on %ir.addr)
+  %oldval = atomicrmw and ptr %addr, i32 1 acq_rel
+  ret i32 %oldval
+}
+
+; Try an seq_cst atomicrmw nand. NAND isn't supported by LSE, so it
+; expands to G_ATOMIC_CMPXCHG_WITH_SUCCESS.
 define i32 @test_atomicrmw_nand(ptr %addr) {
 ; CHECK-LABEL: name: test_atomicrmw_nand
 ; CHECK:       bb.1 (%ir-block.{{[0-9]+}}):
+; CHECK-NEXT:  successors: %bb.2(0x80000000)
 ; CHECK-NEXT:  liveins: $x0
 ; CHECK:         [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT:    [[VAL:%[0-9]+]]:_(s256) = G_CONSTANT i256 1
-; CHECK-NEXT:    [[OLDVALRES:%[0-9]+]]:_(s256) = G_ATOMICRMW_NAND [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s256) on %ir.addr)
-; CHECK-NEXT:    [[RES:%[0-9]+]]:_(s32) = G_TRUNC [[OLDVALRES]]
-  %oldval = atomicrmw nand ptr %addr, i256 1 seq_cst
-  ; FIXME: We currently can't lower 'ret i256' and it's not the purpose of this
-  ;        test so work around it by truncating to i32 for now.
-  %oldval.trunc = trunc i256 %oldval to i32
-  ret i32 %oldval.trunc
+; CHECK-NEXT:    [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK-NEXT:    [[NEG1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+; CHECK-NEXT:    [[OLDVALSTART:%[0-9]+]]:_(s32) = G_LOAD [[ADDR]](p0) :: (load (s32) from %ir.addr)
+; CHECK:       bb.2.atomicrmw.start:
+; CHECK-NEXT:    successors: %bb.3({{[^)]+}}), %bb.2({{[^)]+}})
+; CHECK:         [[OLDVAL:%[0-9]+]]:_(s32) = G_PHI [[OLDVALSTART]](s32), %bb.1, [[OLDVALRES:%[0-9]+]](s32), %bb.2
+; CHECK-NEXT:    [[AND:%[0-9]+]]:_(s32) = G_AND [[OLDVAL]], [[VAL]]
+; CHECK-NEXT:    [[NEWVAL:%[0-9]+]]:_(s32) = G_XOR [[AND]], [[NEG1]]
+; CHECK:         [[OLDVALRES]]:_(s32), [[SUCCESS:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[ADDR]](p0), [[OLDVAL]], [[NEWVAL]] :: (load store seq_cst seq_cst (s32) on %ir.addr)
+; CHECK-NEXT:    G_BRCOND [[SUCCESS]](s1), %bb.3
+; CHECK-NEXT:    G_BR %bb.2
+; CHECK:       bb.3.atomicrmw.end:
+  %oldval = atomicrmw nand ptr %addr, i32 1 seq_cst
+  ret i32 %oldval
 }
 
 ; Try an seq_cst atomicrmw or
-; AArch64 will expand some atomicrmw's at the LLVM-IR level so we use a wide type to avoid this.
 define i32 @test_atomicrmw_or(ptr %addr) {
 ; CHECK-LABEL: name: test_atomicrmw_or
 ; CHECK:       bb.1 (%ir-block.{{[0-9]+}}):
 ; CHECK-NEXT:  liveins: $x0
 ; CHECK:         [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT:    [[VAL:%[0-9]+]]:_(s256) = G_CONSTANT i256 1
-; CHECK-NEXT:    [[OLDVALRES:%[0-9]+]]:_(s256) = G_ATOMICRMW_OR [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s256) on %ir.addr)
-; CHECK-NEXT:    [[RES:%[0-9]+]]:_(s32) = G_TRUNC [[OLDVALRES]]
-  %oldval = atomicrmw or ptr %addr, i256 1 seq_cst
-  ; FIXME: We currently can't lower 'ret i256' and it's not the purpose of this
-  ;        test so work around it by truncating to i32 for now.
-  %oldval.trunc = trunc i256 %oldval to i32
-  ret i32 %oldval.trunc
+; CHECK-NEXT:    [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK-NEXT:    [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_OR [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s32) on %ir.addr)
+  %oldval = atomicrmw or ptr %addr, i32 1 seq_cst
+  ret i32 %oldval
 }
 
 ; Try an seq_cst atomicrmw xor
-; AArch64 will expand some atomicrmw's at the LLVM-IR level so we use a wide type to avoid this.
 define i32 @test_atomicrmw_xor(ptr %addr) {
 ; CHECK-LABEL: name: test_atomicrmw_xor
 ; CHECK:       bb.1 (%ir-block.{{[0-9]+}}):
 ; CHECK-NEXT:  liveins: $x0
 ; CHECK:         [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT:    [[VAL:%[0-9]+]]:_(s256) = G_CONSTANT i256 1
-; CHECK-NEXT:    [[OLDVALRES:%[0-9]+]]:_(s256) = G_ATOMICRMW_XOR [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s256) on %ir.addr)
-; CHECK-NEXT:    [[RES:%[0-9]+]]:_(s32) = G_TRUNC [[OLDVALRES]]
-  %oldval = atomicrmw xor ptr %addr, i256 1 seq_cst
-  ; FIXME: We currently can't lower 'ret i256' and it's not the purpose of this
-  ;        test so work around it by truncating to i32 for now.
-  %oldval.trunc = trunc i256 %oldval to i32
-  ret i32 %oldval.trunc
+; CHECK-NEXT:    [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK-NEXT:    [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_XOR [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s32) on %ir.addr)
+  %oldval = atomicrmw xor ptr %addr, i32 1 seq_cst
+  ret i32 %oldval
 }
 
 ; Try an seq_cst atomicrmw min
-; AArch64 will expand some atomicrmw's at the LLVM-IR level so we use a wide type to avoid this.
 define i32 @test_atomicrmw_min(ptr %addr) {
 ; CHECK-LABEL: name: test_atomicrmw_min
 ; CHECK:       bb.1 (%ir-block.{{[0-9]+}}):
 ; CHECK-NEXT:  liveins: $x0
 ; CHECK:         [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT:    [[VAL:%[0-9]+]]:_(s256) = G_CONSTANT i256 1
-; CHECK-NEXT:    [[OLDVALRES:%[0-9]+]]:_(s256) = G_ATOMICRMW_MIN [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s256) on %ir.addr)
-; CHECK-NEXT:    [[RES:%[0-9]+]]:_(s32) = G_TRUNC [[OLDVALRES]]
-  %oldval = atomicrmw min ptr %addr, i256 1 seq_cst
-  ; FIXME: We currently can't lower 'ret i256' and it's not the purpose of this
-  ;        test so work around it by truncating to i32 for now.
-  %oldval.trunc = trunc i256 %oldval to i32
-  ret i32 %oldval.trunc
+; CHECK-NEXT:    [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK-NEXT:    [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_MIN [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s32) on %ir.addr)
+  %oldval = atomicrmw min ptr %addr, i32 1 seq_cst
+  ret i32 %oldval
 }
 
 ; Try an seq_cst atomicrmw max
-; AArch64 will expand some atomicrmw's at the LLVM-IR level so we use a wide type to avoid this.
 define i32 @test_atomicrmw_max(ptr %addr) {
 ; CHECK-LABEL: name: test_atomicrmw_max
 ; CHECK:       bb.1 (%ir-block.{{[0-9]+}}):
 ; CHECK-NEXT:  liveins: $x0
 ; CHECK:         [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT:    [[VAL:%[0-9]+]]:_(s256) = G_CONSTANT i256 1
-; CHECK-NEXT:    [[OLDVALRES:%[0-9]+]]:_(s256) = G_ATOMICRMW_MAX [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s256) on %ir.addr)
-; CHECK-NEXT:    [[RES:%[0-9]+]]:_(s32) = G_TRUNC [[OLDVALRES]]
-  %oldval = atomicrmw max ptr %addr, i256 1 seq_cst
-  ; FIXME: We currently can't lower 'ret i256' and it's not the purpose of this
-  ;        test so work around it by truncating to i32 for now.
-  %oldval.trunc = trunc i256 %oldval to i32
-  ret i32 %oldval.trunc
+; CHECK-NEXT:    [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK-NEXT:    [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_MAX [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s32) on %ir.addr)
+  %oldval = atomicrmw max ptr %addr, i32 1 seq_cst
+  ret i32 %oldval
 }
 
 ; Try an seq_cst atomicrmw unsigned min
-; AArch64 will expand some atomicrmw's at the LLVM-IR level so we use a wide type to avoid this.
 define i32 @test_atomicrmw_umin(ptr %addr) {
 ; CHECK-LABEL: name: test_atomicrmw_umin
 ; CHECK:       bb.1 (%ir-block.{{[0-9]+}}):
 ; CHECK-NEXT:  liveins: $x0
 ; CHECK:         [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT:    [[VAL:%[0-9]+]]:_(s256) = G_CONSTANT i256 1
-; CHECK-NEXT:    [[OLDVALRES:%[0-9]+]]:_(s256) = G_ATOMICRMW_UMIN [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s256) on %ir.addr)
-; CHECK-NEXT:    [[RES:%[0-9]+]]:_(s32) = G_TRUNC [[OLDVALRES]]
-  %oldval = atomicrmw umin ptr %addr, i256 1 seq_cst
-  ; FIXME: We currently can't lower 'ret i256' and it's not the purpose of this
-  ;        test so work around it by truncating to i32 for now.
-  %oldval.trunc = trunc i256 %oldval to i32
-  ret i32 %oldval.trunc
+; CHECK-NEXT:    [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK-NEXT:    [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_UMIN [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s32) on %ir.addr)
+  %oldval = atomicrmw umin ptr %addr, i32 1 seq_cst
+  ret i32 %oldval
 }
 
 ; Try an seq_cst atomicrmw unsigned max
-; AArch64 will expand some atomicrmw's at the LLVM-IR level so we use a wide type to avoid this.
 define i32 @test_atomicrmw_umax(ptr %addr) {
 ; CHECK-LABEL: name: test_atomicrmw_umax
 ; CHECK:       bb.1 (%ir-block.{{[0-9]+}}):
 ; CHECK-NEXT:  liveins: $x0
 ; CHECK:         [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT:    [[VAL:%[0-9]+]]:_(s256) = G_CONSTANT i256 1
-; CHECK-NEXT:    [[OLDVALRES:%[0-9]+]]:_(s256) = G_ATOMICRMW_UMAX [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s256) on %ir.addr)
-; CHECK-NEXT:    [[RES:%[0-9]+]]:_(s32) = G_TRUNC [[OLDVALRES]]
-  %oldval = atomicrmw umax ptr %addr, i256 1 seq_cst
-  ; FIXME: We currently can't lower 'ret i256' and it's not the purpose of this
-  ;        test so work around it by truncating to i32 for now.
-  %oldval.trunc = trunc i256 %oldval to i32
-  ret i32 %oldval.trunc
+; CHECK-NEXT:    [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK-NEXT:    [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_UMAX [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s32) on %ir.addr)
+  %oldval = atomicrmw umax ptr %addr, i32 1 seq_cst
+  ret i32 %oldval
 }
 
 @addr = global ptr null
diff --git a/llvm/test/CodeGen/AArch64/atomic-oversize.ll b/llvm/test/CodeGen/AArch64/atomic-oversize.ll
new file mode 100644
index 000000000000..9065311a9aaa
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/atomic-oversize.ll
@@ -0,0 +1,11 @@
+; RUN: llc -march=aarch64 < %s | FileCheck %s
+
+; Atomics larger than 128-bit are unsupported, and emit libcalls.
+define void @test(ptr %a) nounwind {
+; CHECK-LABEL: test:
+; CHECK: bl __atomic_load
+; CHECK: bl __atomic_store
+  %1 = load atomic i256, ptr %a seq_cst, align 32
+  store atomic i256 %1, ptr %a seq_cst, align 32
+  ret void
+}
-- 
GitLab


From e1655a98cb9c098fa941ed199664927ba8a4b031 Mon Sep 17 00:00:00 2001
From: Rashmi Mudduluru <r_mudduluru@apple.com>
Date: Mon, 11 Dec 2023 15:00:08 -0800
Subject: [PATCH 188/349] [-Wunsafe-buffer-usage] Add FixableGadget for
 AddAssign in UnspecifiedUntypedContext (#71862)

---
 .../Analyses/UnsafeBufferUsageGadgets.def     |  1 +
 clang/lib/Analysis/UnsafeBufferUsage.cpp      | 99 +++++++++++++++++--
 ...-unsafe-buffer-usage-fixits-add-assign.cpp | 59 +++++++++++
 3 files changed, 153 insertions(+), 6 deletions(-)
 create mode 100644 clang/test/SemaCXX/warn-unsafe-buffer-usage-fixits-add-assign.cpp

diff --git a/clang/include/clang/Analysis/Analyses/UnsafeBufferUsageGadgets.def b/clang/include/clang/Analysis/Analyses/UnsafeBufferUsageGadgets.def
index ff687a0d178b..757ee452ced7 100644
--- a/clang/include/clang/Analysis/Analyses/UnsafeBufferUsageGadgets.def
+++ b/clang/include/clang/Analysis/Analyses/UnsafeBufferUsageGadgets.def
@@ -36,6 +36,7 @@ FIXABLE_GADGET(PointerDereference)
 FIXABLE_GADGET(UPCAddressofArraySubscript) // '&DRE[any]' in an Unspecified Pointer Context
 FIXABLE_GADGET(UPCStandalonePointer)
 FIXABLE_GADGET(UPCPreIncrement)            // '++Ptr' in an Unspecified Pointer Context
+FIXABLE_GADGET(UUCAddAssign)            // 'Ptr += n' in an Unspecified Untyped Context
 FIXABLE_GADGET(PointerAssignment)
 FIXABLE_GADGET(PointerInit)
 
diff --git a/clang/lib/Analysis/UnsafeBufferUsage.cpp b/clang/lib/Analysis/UnsafeBufferUsage.cpp
index e332a3609290..a1efb76be68b 100644
--- a/clang/lib/Analysis/UnsafeBufferUsage.cpp
+++ b/clang/lib/Analysis/UnsafeBufferUsage.cpp
@@ -1028,6 +1028,46 @@ public:
   }
 };
 
+// Representing a pointer type expression of the form `Ptr += n` in an
+// Unspecified Untyped Context (UUC):
+class UUCAddAssignGadget : public FixableGadget {
+private:
+  static constexpr const char *const UUCAddAssignTag =
+      "PointerAddAssignUnderUUC";
+  static constexpr const char *const OffsetTag = "Offset";
+
+  const BinaryOperator *Node; // the `Ptr += n` node
+  const Expr *Offset = nullptr;
+
+public:
+  UUCAddAssignGadget(const MatchFinder::MatchResult &Result)
+      : FixableGadget(Kind::UUCAddAssign),
+        Node(Result.Nodes.getNodeAs<BinaryOperator>(UUCAddAssignTag)),
+        Offset(Result.Nodes.getNodeAs<Expr>(OffsetTag)) {
+    assert(Node != nullptr && "Expecting a non-null matching result");
+  }
+
+  static bool classof(const Gadget *G) {
+    return G->getKind() == Kind::UUCAddAssign;
+  }
+
+  static Matcher matcher() {
+    return stmt(isInUnspecifiedUntypedContext(expr(ignoringImpCasts(
+        binaryOperator(hasOperatorName("+="),
+                       hasLHS(declRefExpr(toSupportedVariable())),
+                       hasRHS(expr().bind(OffsetTag)))
+            .bind(UUCAddAssignTag)))));
+  }
+
+  virtual std::optional<FixItList> getFixits(const Strategy &S) const override;
+
+  virtual const Stmt *getBaseStmt() const override { return Node; }
+
+  virtual DeclUseList getClaimedVarUseSites() const override {
+    return {dyn_cast<DeclRefExpr>(Node->getLHS())};
+  }
+};
+
 // Representing a fixable expression of the form `*(ptr + 123)` or `*(123 +
 // ptr)`:
 class DerefSimplePtrArithFixableGadget : public FixableGadget {
@@ -1312,6 +1352,16 @@ PointerInitGadget::getFixits(const Strategy &S) const {
   return std::nullopt;
 }
 
+static bool isNonNegativeIntegerExpr(const Expr *Expr, const VarDecl *VD,
+                                     const ASTContext &Ctx) {
+  if (auto ConstVal = Expr->getIntegerConstantExpr(Ctx)) {
+    if (ConstVal->isNegative())
+      return false;
+  } else if (!Expr->getType()->isUnsignedIntegerType())
+    return false;
+  return true;
+}
+
 std::optional<FixItList>
 ULCArraySubscriptGadget::getFixits(const Strategy &S) const {
   if (const auto *DRE =
@@ -1319,14 +1369,12 @@ ULCArraySubscriptGadget::getFixits(const Strategy &S) const {
     if (const auto *VD = dyn_cast<VarDecl>(DRE->getDecl())) {
       switch (S.lookup(VD)) {
       case Strategy::Kind::Span: {
+
         // If the index has a negative constant value, we give up as no valid
         // fix-it can be generated:
         const ASTContext &Ctx = // FIXME: we need ASTContext to be passed in!
             VD->getASTContext();
-        if (auto ConstVal = Node->getIdx()->getIntegerConstantExpr(Ctx)) {
-          if (ConstVal->isNegative())
-            return std::nullopt;
-        } else if (!Node->getIdx()->getType()->isUnsignedIntegerType())
+        if (!isNonNegativeIntegerExpr(Node->getIdx(), VD, Ctx))
           return std::nullopt;
         // no-op is a good fix-it, otherwise
         return FixItList{};
@@ -1405,10 +1453,8 @@ static std::optional<SourceLocation> getPastLoc(const NodeTy *Node,
                                                 const LangOptions &LangOpts) {
   SourceLocation Loc =
       Lexer::getLocForEndOfToken(Node->getEndLoc(), 0, SM, LangOpts);
-
   if (Loc.isValid())
     return Loc;
-
   return std::nullopt;
 }
 
@@ -1766,6 +1812,47 @@ fixUPCAddressofArraySubscriptWithSpan(const UnaryOperator *Node) {
       FixItHint::CreateReplacement(Node->getSourceRange(), SS.str())};
 }
 
+std::optional<FixItList>
+UUCAddAssignGadget::getFixits(const Strategy &S) const {
+  DeclUseList DREs = getClaimedVarUseSites();
+
+  if (DREs.size() != 1)
+    return std::nullopt; // In cases of `Ptr += n` where `Ptr` is not a DRE, we
+                         // give up
+  if (const VarDecl *VD = dyn_cast<VarDecl>(DREs.front()->getDecl())) {
+    if (S.lookup(VD) == Strategy::Kind::Span) {
+      FixItList Fixes;
+
+      const Stmt *AddAssignNode = getBaseStmt();
+      StringRef varName = VD->getName();
+      const ASTContext &Ctx = VD->getASTContext();
+
+      if (!isNonNegativeIntegerExpr(Offset, VD, Ctx))
+        return std::nullopt;
+
+      // To transform UUC(p += n) to UUC(p = p.subspan(..)):
+      bool NotParenExpr =
+          (Offset->IgnoreParens()->getBeginLoc() == Offset->getBeginLoc());
+      std::string SS = varName.str() + " = " + varName.str() + ".subspan";
+      if (NotParenExpr)
+        SS += "(";
+
+      std::optional<SourceLocation> AddAssignLocation = getEndCharLoc(
+          AddAssignNode, Ctx.getSourceManager(), Ctx.getLangOpts());
+      if (!AddAssignLocation)
+        return std::nullopt;
+
+      Fixes.push_back(FixItHint::CreateReplacement(
+          SourceRange(AddAssignNode->getBeginLoc(), Node->getOperatorLoc()),
+          SS));
+      if (NotParenExpr)
+        Fixes.push_back(FixItHint::CreateInsertion(
+            Offset->getEndLoc().getLocWithOffset(1), ")"));
+      return Fixes;
+    }
+  }
+  return std::nullopt; // Not in the cases that we can handle for now, give up.
+}
 
 std::optional<FixItList> UPCPreIncrementGadget::getFixits(const Strategy &S) const {
   DeclUseList DREs = getClaimedVarUseSites();
diff --git a/clang/test/SemaCXX/warn-unsafe-buffer-usage-fixits-add-assign.cpp b/clang/test/SemaCXX/warn-unsafe-buffer-usage-fixits-add-assign.cpp
new file mode 100644
index 000000000000..5c03cc10025c
--- /dev/null
+++ b/clang/test/SemaCXX/warn-unsafe-buffer-usage-fixits-add-assign.cpp
@@ -0,0 +1,59 @@
+// RUN: %clang_cc1 -std=c++20 -Wunsafe-buffer-usage \
+// RUN:            -fsafe-buffer-usage-suggestions \
+// RUN:            -fdiagnostics-parseable-fixits %s 2>&1 | FileCheck %s
+void foo(int * , int *);
+
+void add_assign_test(unsigned int n, int *a, int y) {
+  int *p = new int[10];
+  // CHECK: fix-it:"{{.*}}":{[[@LINE-1]]:3-[[@LINE-1]]:11}:"std::span<int> p"
+  // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:12-[[@LINE-2]]:12}:"{"
+  // CHECK: fix-it:"{{.*}}":{[[@LINE-3]]:23-[[@LINE-3]]:23}:", 10}"
+  p += 2;
+  // CHECK: fix-it:"{{.*}}":{[[@LINE-1]]:3-[[@LINE-1]]:7}:"p = p.subspan("
+  // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:9-[[@LINE-2]]:9}:")"
+  
+  int *r = p;
+  // CHECK: fix-it:"{{.*}}":{[[@LINE-1]]:3-[[@LINE-1]]:11}:"std::span<int> r"
+  // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:12-[[@LINE-2]]:12}:"{"
+  // CHECK: fix-it:"{{.*}}":{[[@LINE-3]]:13-[[@LINE-3]]:13}:", <# placeholder #>}"
+  while (*r != 0) {
+  // CHECK: fix-it:"{{.*}}":{[[@LINE-1]]:10-[[@LINE-1]]:11}:""
+  // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:12-[[@LINE-2]]:12}:"[0]"
+    r += 2;
+    // CHECK: fix-it:"{{.*}}":{[[@LINE-1]]:5-[[@LINE-1]]:9}:"r = r.subspan("
+    // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:11-[[@LINE-2]]:11}:")"
+  }
+  
+  if (*p == 0) {
+  // CHECK: fix-it:"{{.*}}":{[[@LINE-1]]:7-[[@LINE-1]]:8}:""
+  // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:9-[[@LINE-2]]:9}:"[0]"
+    p += n;
+    // CHECK: fix-it:"{{.*}}":{[[@LINE-1]]:5-[[@LINE-1]]:9}:"p = p.subspan("
+    // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:11-[[@LINE-2]]:11}:")"
+  }
+  
+  if (*p == 1)
+  // CHECK: fix-it:"{{.*}}":{[[@LINE-1]]:7-[[@LINE-1]]:8}:""
+  // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:9-[[@LINE-2]]:9}:"[0]"
+    p += 3;
+  // CHECK: fix-it:"{{.*}}":{[[@LINE-1]]:5-[[@LINE-1]]:9}:"p = p.subspan("
+  // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:11-[[@LINE-2]]:11}:")"
+  
+  a += -9;
+  // CHECK-NOT: fix-it:"{{.*}}":{[[@LINE-1]]:5-[[@LINE-1]]:9}:"p = p.subspan("
+  
+  a += y;
+  // CHECK-NOT: fix-it:"{{.*}}":{[[@LINE-1]]:5-[[@LINE-1]]:9}:"p = p.subspan("
+}
+
+int expr_test(unsigned x, int *q, int y) {
+  char *p = new char[8];
+  // CHECK: fix-it:"{{.*}}":{[[@LINE-1]]:3-[[@LINE-1]]:12}:"std::span<char> p"
+  // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:13-[[@LINE-2]]:13}:"{"
+  // CHECK: fix-it:"{{.*}}":{[[@LINE-3]]:24-[[@LINE-3]]:24}:", 8}"
+  p += (x + 1);
+  // CHECK: fix-it:"{{.*}}":{[[@LINE-1]]:3-[[@LINE-1]]:7}:"p = p.subspan"
+  
+  q += (y + 7);
+  // CHECK-NOT: fix-it:"{{.*}}":{[[@LINE-1]]:3-[[@LINE-1]]:7}:"q = q.subspan"
+}
-- 
GitLab


From 81d1df2a39f0616be4b530cbf86b3f575442a347 Mon Sep 17 00:00:00 2001
From: Fangrui Song <i@maskray.me>
Date: Mon, 11 Dec 2023 15:30:28 -0800
Subject: [PATCH 189/349] [SpecialCaseList] Use glob by default (#74809)

https://reviews.llvm.org/D154014 addes glob support and enables it when
`#!special-case-list-v2` is the first line. This patch makes the glob
support the default (faster than regex after
https://reviews.llvm.org/D156046) and switches to the deprecated regex
support if `#!special-case-list-v1` is the first line.

I have surveyed many ignore lists. All ignore lists I find only use
basic `*` `.` and don't use regex metacharacters such as `(` and `)`.
(As neither `src:` nor `fun:` benefits from using regex.)
They are unaffected by the transition (with a caution that regex
`src:x/a.pb.*` matches `x/axpbx` but glob `src:x/a.pb.*` doesn't).

There is no deprecating warning. If a user finds
`#!special-case-list-v1`, they shall read that the old syntax is
deprecated.

Link:
https://discourse.llvm.org/t/use-glob-instead-of-regex-for-specialcaselists/71666
---
 clang/docs/SanitizerSpecialCaseList.rst       | 18 ++++++++-----
 llvm/lib/Support/SpecialCaseList.cpp          | 11 ++++----
 .../unittests/Support/SpecialCaseListTest.cpp | 26 +++++++++----------
 3 files changed, 29 insertions(+), 26 deletions(-)

diff --git a/clang/docs/SanitizerSpecialCaseList.rst b/clang/docs/SanitizerSpecialCaseList.rst
index ab39276b0439..c7fb0fa3f8a8 100644
--- a/clang/docs/SanitizerSpecialCaseList.rst
+++ b/clang/docs/SanitizerSpecialCaseList.rst
@@ -56,13 +56,18 @@ and lines starting with "#" are ignored.
 
 .. note::
 
-  In `D154014 <https://reviews.llvm.org/D154014>`_ we transitioned to using globs instead
-  of regexes to match patterns in special case lists. Since this was a
-  breaking change, we will temporarily support the original behavior using
-  regexes. If ``#!special-case-list-v2`` is the first line of the file, then
-  we will use the new behavior using globs. For more details, see
-  `this discourse post <https://discourse.llvm.org/t/use-glob-instead-of-regex-for-specialcaselists/71666>`_.
+  Prior to Clang 18, section names and entries described below use a variant of
+  regex where ``*`` is translated to ``.*``. Clang 18 (`D154014
+  <https://reviews.llvm.org/D154014>`) switches to glob and plans to remove
+  regex support in Clang 19.
 
+  For Clang 18, regex is supported if ``#!special-case-list-v1`` is the first
+  line of the file.
+
+  Many special case lists use ``.`` to indicate the literal character and do
+  not use regex metacharacters such as ``(``, ``)``. They are unaffected by the
+  regex to glob transition. For more details, see `this discourse post
+  <https://discourse.llvm.org/t/use-glob-instead-of-regex-for-specialcaselists/71666>`_.
 
 Section names are globs written in square brackets that denote
 which sanitizer the following entries apply to. For example, ``[address]``
@@ -80,7 +85,6 @@ tool-specific docs.
 
 .. code-block:: bash
 
-    #!special-case-list-v2
     # The line above is explained in the note above
     # Lines starting with # are ignored.
     # Turn off checks for the source file
diff --git a/llvm/lib/Support/SpecialCaseList.cpp b/llvm/lib/Support/SpecialCaseList.cpp
index ac8877cca8bc..7a23421eaeb8 100644
--- a/llvm/lib/Support/SpecialCaseList.cpp
+++ b/llvm/lib/Support/SpecialCaseList.cpp
@@ -150,13 +150,12 @@ bool SpecialCaseList::parse(const MemoryBuffer *MB, std::string &Error) {
     return false;
   }
 
-  // In https://reviews.llvm.org/D154014 we transitioned to using globs instead
-  // of regexes to match patterns in special case lists. Since this was a
-  // breaking change, we will temporarily support the original behavior using
-  // regexes. If "#!special-case-list-v2" is the first line of the file, then
-  // we will use the new behavior using globs. For more details, see
+  // In https://reviews.llvm.org/D154014 we added glob support and planned to
+  // remove regex support in patterns. We temporarily support the original
+  // behavior using regexes if "#!special-case-list-v1" is the first line of the
+  // file. For more details, see
   // https://discourse.llvm.org/t/use-glob-instead-of-regex-for-specialcaselists/71666
-  bool UseGlobs = MB->getBuffer().starts_with("#!special-case-list-v2\n");
+  bool UseGlobs = !MB->getBuffer().starts_with("#!special-case-list-v1\n");
 
   for (line_iterator LineIt(*MB, /*SkipBlanks=*/true, /*CommentMarker=*/'#');
        !LineIt.is_at_eof(); LineIt++) {
diff --git a/llvm/unittests/Support/SpecialCaseListTest.cpp b/llvm/unittests/Support/SpecialCaseListTest.cpp
index 81faeca5d635..4289a5e70215 100644
--- a/llvm/unittests/Support/SpecialCaseListTest.cpp
+++ b/llvm/unittests/Support/SpecialCaseListTest.cpp
@@ -25,8 +25,8 @@ protected:
                                                        std::string &Error,
                                                        bool UseGlobs = true) {
     auto S = List.str();
-    if (UseGlobs)
-      S = (Twine("#!special-case-list-v2\n") + S).str();
+    if (!UseGlobs)
+      S = (Twine("#!special-case-list-v1\n") + S).str();
     std::unique_ptr<MemoryBuffer> MB = MemoryBuffer::getMemBuffer(S);
     return SpecialCaseList::create(MB.get(), Error);
   }
@@ -46,8 +46,8 @@ protected:
     SmallString<64> Path;
     sys::fs::createTemporaryFile("SpecialCaseListTest", "temp", FD, Path);
     raw_fd_ostream OF(FD, true, true);
-    if (UseGlobs)
-      OF << "#!special-case-list-v2\n";
+    if (!UseGlobs)
+      OF << "#!special-case-list-v1\n";
     OF << Contents;
     OF.close();
     return std::string(Path.str());
@@ -70,10 +70,10 @@ TEST_F(SpecialCaseListTest, Basic) {
   EXPECT_FALSE(SCL->inSection("", "fun", "hello"));
   EXPECT_FALSE(SCL->inSection("", "src", "hello", "category"));
 
-  EXPECT_EQ(4u, SCL->inSectionBlame("", "src", "hello"));
-  EXPECT_EQ(5u, SCL->inSectionBlame("", "src", "bye"));
-  EXPECT_EQ(6u, SCL->inSectionBlame("", "src", "hi", "category"));
-  EXPECT_EQ(7u, SCL->inSectionBlame("", "src", "zzzz", "category"));
+  EXPECT_EQ(3u, SCL->inSectionBlame("", "src", "hello"));
+  EXPECT_EQ(4u, SCL->inSectionBlame("", "src", "bye"));
+  EXPECT_EQ(5u, SCL->inSectionBlame("", "src", "hi", "category"));
+  EXPECT_EQ(6u, SCL->inSectionBlame("", "src", "zzzz", "category"));
   EXPECT_EQ(0u, SCL->inSectionBlame("", "src", "hi"));
   EXPECT_EQ(0u, SCL->inSectionBlame("", "fun", "hello"));
   EXPECT_EQ(0u, SCL->inSectionBlame("", "src", "hello", "category"));
@@ -85,12 +85,12 @@ TEST_F(SpecialCaseListTest, CorrectErrorLineNumberWithBlankLine) {
                                          "\n"
                                          "[not valid\n",
                                          Error));
-  EXPECT_THAT(Error, StartsWith("malformed section header on line 4:"));
+  EXPECT_THAT(Error, StartsWith("malformed section header on line 3:"));
 
   EXPECT_EQ(nullptr, makeSpecialCaseList("\n\n\n"
                                          "[not valid\n",
                                          Error));
-  EXPECT_THAT(Error, StartsWith("malformed section header on line 5:"));
+  EXPECT_THAT(Error, StartsWith("malformed section header on line 4:"));
 }
 
 TEST_F(SpecialCaseListTest, SectionGlobErrorHandling) {
@@ -101,7 +101,7 @@ TEST_F(SpecialCaseListTest, SectionGlobErrorHandling) {
   EXPECT_EQ(makeSpecialCaseList("[[]", Error), nullptr);
   EXPECT_EQ(
       Error,
-      "malformed section at line 2: '[': invalid glob pattern, unmatched '['");
+      "malformed section at line 1: '[': invalid glob pattern, unmatched '['");
 
   EXPECT_EQ(makeSpecialCaseList("src:=", Error), nullptr);
   EXPECT_THAT(Error, HasSubstr("Supplied glob was blank"));
@@ -163,10 +163,10 @@ TEST_F(SpecialCaseListTest, Substring) {
 TEST_F(SpecialCaseListTest, InvalidSpecialCaseList) {
   std::string Error;
   EXPECT_EQ(nullptr, makeSpecialCaseList("badline", Error));
-  EXPECT_EQ("malformed line 2: 'badline'", Error);
+  EXPECT_EQ("malformed line 1: 'badline'", Error);
   EXPECT_EQ(nullptr, makeSpecialCaseList("src:bad[a-", Error));
   EXPECT_EQ(
-      "malformed glob in line 2: 'bad[a-': invalid glob pattern, unmatched '['",
+      "malformed glob in line 1: 'bad[a-': invalid glob pattern, unmatched '['",
       Error);
   std::vector<std::string> Files(1, "unexisting");
   EXPECT_EQ(nullptr,
-- 
GitLab


From e9b2a0722b9e9035e08c3f82925622ee6f932cd2 Mon Sep 17 00:00:00 2001
From: madanial0 <118996571+madanial0@users.noreply.github.com>
Date: Mon, 11 Dec 2023 18:34:53 -0500
Subject: [PATCH 190/349] [flang] Modify lto testcase for AIX (#74496)

Change the lto-flags test case to check for `-bdbg:thinlto` on AIX

---------

Co-authored-by: Mark Danial <mark.danial@ibm.com>
---
 flang/test/Driver/lto-flags.f90 | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/flang/test/Driver/lto-flags.f90 b/flang/test/Driver/lto-flags.f90
index 2b3b08fbcc71..a51febc70096 100644
--- a/flang/test/Driver/lto-flags.f90
+++ b/flang/test/Driver/lto-flags.f90
@@ -11,9 +11,12 @@
 
 ! Also check linker plugin opt for Thin LTO
 ! RUN: %flang -### -flto=thin %s 2>&1 | FileCheck %s \
-! RUN:        --check-prefixes=%if system-darwin %{THIN-LTO-ALL%} \
+! RUN:        --check-prefixes=%if system-darwin || system-aix %{THIN-LTO-ALL%} \
 ! RUN:        %else %{THIN-LTO-ALL,THIN-LTO-LINKER-PLUGIN%}
 
+! RUN: %flang -### -flto=thin --target=powerpc64-aix %s 2>&1 | FileCheck %s \
+! RUN:        --check-prefix THIN-LTO-LINKER-AIX
+
 ! RUN: not %flang -### -S -flto=somelto %s 2>&1 | FileCheck %s --check-prefix=ERROR
 
 ! FC1 tests. Check that it does not crash.
@@ -31,5 +34,6 @@
 ! THIN-LTO-ALL: "-fc1"
 ! THIN-LTO-ALL-SAME: "-flto=thin"
 ! THIN-LTO-LINKER-PLUGIN: "-plugin-opt=thinlto"
+! THIN-LTO-LINKER-AIX: "-bdbg:thinlto"
 
 ! ERROR: error: unsupported argument 'somelto' to option '-flto=
-- 
GitLab


From 863b9388687d01c67de1248e48cee0df698515c0 Mon Sep 17 00:00:00 2001
From: Shoaib Meenai <smeenai@fb.com>
Date: Mon, 11 Dec 2023 15:35:09 -0800
Subject: [PATCH 191/349] [clang] Remove stale release note

This fix was merged into 17.0.3 (commit 69c8c96691c7), so the release
note for Clang 18 should be removed.
---
 clang/docs/ReleaseNotes.rst | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 783dc7333af7..d6719680d2ac 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -401,9 +401,6 @@ Improvements to Clang's diagnostics
   (`#54678: <https://github.com/llvm/llvm-project/issues/54678>`_).
 - Clang now prints its 'note' diagnostic in cyan instead of black, to be more compatible
   with terminals with dark background colors. This is also more consistent with GCC.
-- The fix-it emitted by ``-Wformat`` for scoped enumerations now take the
-  enumeration's underlying type into account instead of suggesting a type just
-  based on the format string specifier being used.
 - Clang now displays an improved diagnostic and a note when a defaulted special
   member is marked ``constexpr`` in a class with a virtual base class
   (`#64843: <https://github.com/llvm/llvm-project/issues/64843>`_).
-- 
GitLab


From 072cea668e95125b1eee20d88efa12ad58723791 Mon Sep 17 00:00:00 2001
From: Fangrui Song <i@maskray.me>
Date: Mon, 11 Dec 2023 15:42:12 -0800
Subject: [PATCH 192/349] [test] Change llc -march to -mtriple

Similar to d20190e68413634b87f0f9426312a0e9d8456d18
---
 llvm/test/CodeGen/AArch64/atomic-oversize.ll | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/test/CodeGen/AArch64/atomic-oversize.ll b/llvm/test/CodeGen/AArch64/atomic-oversize.ll
index 9065311a9aaa..312c7e2a9bc3 100644
--- a/llvm/test/CodeGen/AArch64/atomic-oversize.ll
+++ b/llvm/test/CodeGen/AArch64/atomic-oversize.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=aarch64 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
 
 ; Atomics larger than 128-bit are unsupported, and emit libcalls.
 define void @test(ptr %a) nounwind {
-- 
GitLab


From 6ed1daa0c9413bf63c2bd1f113bba4fb119f2b2b Mon Sep 17 00:00:00 2001
From: Mircea Trofin <mtrofin@google.com>
Date: Mon, 11 Dec 2023 15:42:57 -0800
Subject: [PATCH 193/349] [NFC][InstrProf] Move `InstrProfiling` to the .cpp
 file (#75018)

---
 .../Instrumentation/InstrProfiling.h          | 157 ------------------
 .../Instrumentation/InstrProfiling.cpp        | 149 +++++++++++++++++
 2 files changed, 149 insertions(+), 157 deletions(-)

diff --git a/llvm/include/llvm/Transforms/Instrumentation/InstrProfiling.h b/llvm/include/llvm/Transforms/Instrumentation/InstrProfiling.h
index 95eb3019eab0..0dd37c9ca58b 100644
--- a/llvm/include/llvm/Transforms/Instrumentation/InstrProfiling.h
+++ b/llvm/include/llvm/Transforms/Instrumentation/InstrProfiling.h
@@ -13,21 +13,12 @@
 #ifndef LLVM_TRANSFORMS_INSTRUMENTATION_INSTRPROFILING_H
 #define LLVM_TRANSFORMS_INSTRUMENTATION_INSTRPROFILING_H
 
-#include "llvm/ADT/DenseMap.h"
-#include "llvm/ADT/StringRef.h"
-#include "llvm/IR/IntrinsicInst.h"
 #include "llvm/IR/PassManager.h"
-#include "llvm/ProfileData/InstrProf.h"
 #include "llvm/Transforms/Instrumentation.h"
-#include <cstdint>
-#include <cstring>
-#include <vector>
 
 namespace llvm {
 
 class TargetLibraryInfo;
-using LoadStorePair = std::pair<Instruction *, Instruction *>;
-
 /// Instrumentation based profiling lowering pass. This pass lowers
 /// the profile instrumented code generated by FE or the IR based
 /// instrumentation pass.
@@ -44,154 +35,6 @@ public:
 
   PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
 };
-
-class InstrProfiling final {
-public:
-  InstrProfiling(Module &M, const InstrProfOptions &Options,
-                 std::function<const TargetLibraryInfo &(Function &F)> GetTLI,
-                 bool IsCS)
-      : M(M), Options(Options), TT(Triple(M.getTargetTriple())), IsCS(IsCS),
-        GetTLI(GetTLI) {}
-
-  bool lower();
-
-private:
-  Module &M;
-  const InstrProfOptions Options;
-  const Triple TT;
-  // Is this lowering for the context-sensitive instrumentation.
-  const bool IsCS;
-
-  std::function<const TargetLibraryInfo &(Function &F)> GetTLI;
-  struct PerFunctionProfileData {
-    uint32_t NumValueSites[IPVK_Last + 1] = {};
-    GlobalVariable *RegionCounters = nullptr;
-    GlobalVariable *DataVar = nullptr;
-    GlobalVariable *RegionBitmaps = nullptr;
-    uint32_t NumBitmapBytes = 0;
-
-    PerFunctionProfileData() = default;
-  };
-  DenseMap<GlobalVariable *, PerFunctionProfileData> ProfileDataMap;
-  /// If runtime relocation is enabled, this maps functions to the load
-  /// instruction that produces the profile relocation bias.
-  DenseMap<const Function *, LoadInst *> FunctionToProfileBiasMap;
-  std::vector<GlobalValue *> CompilerUsedVars;
-  std::vector<GlobalValue *> UsedVars;
-  std::vector<GlobalVariable *> ReferencedNames;
-  GlobalVariable *NamesVar = nullptr;
-  size_t NamesSize = 0;
-
-  // vector of counter load/store pairs to be register promoted.
-  std::vector<LoadStorePair> PromotionCandidates;
-
-  int64_t TotalCountersPromoted = 0;
-
-  /// Lower instrumentation intrinsics in the function. Returns true if there
-  /// any lowering.
-  bool lowerIntrinsics(Function *F);
-
-  /// Register-promote counter loads and stores in loops.
-  void promoteCounterLoadStores(Function *F);
-
-  /// Returns true if relocating counters at runtime is enabled.
-  bool isRuntimeCounterRelocationEnabled() const;
-
-  /// Returns true if profile counter update register promotion is enabled.
-  bool isCounterPromotionEnabled() const;
-
-  /// Count the number of instrumented value sites for the function.
-  void computeNumValueSiteCounts(InstrProfValueProfileInst *Ins);
-
-  /// Replace instrprof.value.profile with a call to runtime library.
-  void lowerValueProfileInst(InstrProfValueProfileInst *Ins);
-
-  /// Replace instrprof.cover with a store instruction to the coverage byte.
-  void lowerCover(InstrProfCoverInst *Inc);
-
-  /// Replace instrprof.timestamp with a call to
-  /// INSTR_PROF_PROFILE_SET_TIMESTAMP.
-  void lowerTimestamp(InstrProfTimestampInst *TimestampInstruction);
-
-  /// Replace instrprof.increment with an increment of the appropriate value.
-  void lowerIncrement(InstrProfIncrementInst *Inc);
-
-  /// Force emitting of name vars for unused functions.
-  void lowerCoverageData(GlobalVariable *CoverageNamesVar);
-
-  /// Replace instrprof.mcdc.tvbitmask.update with a shift and or instruction
-  /// using the index represented by the a temp value into a bitmap.
-  void lowerMCDCTestVectorBitmapUpdate(InstrProfMCDCTVBitmapUpdate *Ins);
-
-  /// Replace instrprof.mcdc.temp.update with a shift and or instruction using
-  /// the corresponding condition ID.
-  void lowerMCDCCondBitmapUpdate(InstrProfMCDCCondBitmapUpdate *Ins);
-
-  /// Compute the address of the counter value that this profiling instruction
-  /// acts on.
-  Value *getCounterAddress(InstrProfCntrInstBase *I);
-
-  /// Get the region counters for an increment, creating them if necessary.
-  ///
-  /// If the counter array doesn't yet exist, the profile data variables
-  /// referring to them will also be created.
-  GlobalVariable *getOrCreateRegionCounters(InstrProfCntrInstBase *Inc);
-
-  /// Create the region counters.
-  GlobalVariable *createRegionCounters(InstrProfCntrInstBase *Inc,
-                                       StringRef Name,
-                                       GlobalValue::LinkageTypes Linkage);
-
-  /// Compute the address of the test vector bitmap that this profiling
-  /// instruction acts on.
-  Value *getBitmapAddress(InstrProfMCDCTVBitmapUpdate *I);
-
-  /// Get the region bitmaps for an increment, creating them if necessary.
-  ///
-  /// If the bitmap array doesn't yet exist, the profile data variables
-  /// referring to them will also be created.
-  GlobalVariable *getOrCreateRegionBitmaps(InstrProfMCDCBitmapInstBase *Inc);
-
-  /// Create the MC/DC bitmap as a byte-aligned array of bytes associated with
-  /// an MC/DC Decision region. The number of bytes required is indicated by
-  /// the intrinsic used (type InstrProfMCDCBitmapInstBase).  This is called
-  /// as part of setupProfileSection() and is conceptually very similar to
-  /// what is done for profile data counters in createRegionCounters().
-  GlobalVariable *createRegionBitmaps(InstrProfMCDCBitmapInstBase *Inc,
-                                      StringRef Name,
-                                      GlobalValue::LinkageTypes Linkage);
-
-  /// Set Comdat property of GV, if required.
-  void maybeSetComdat(GlobalVariable *GV, Function *Fn, StringRef VarName);
-
-  /// Setup the sections into which counters and bitmaps are allocated.
-  GlobalVariable *setupProfileSection(InstrProfInstBase *Inc,
-                                      InstrProfSectKind IPSK);
-
-  /// Create INSTR_PROF_DATA variable for counters and bitmaps.
-  void createDataVariable(InstrProfCntrInstBase *Inc);
-
-  /// Emit the section with compressed function names.
-  void emitNameData();
-
-  /// Emit value nodes section for value profiling.
-  void emitVNodes();
-
-  /// Emit runtime registration functions for each profile data variable.
-  void emitRegistration();
-
-  /// Emit the necessary plumbing to pull in the runtime initialization.
-  /// Returns true if a change was made.
-  bool emitRuntimeHook();
-
-  /// Add uses of our data variables and runtime hook.
-  void emitUses();
-
-  /// Create a static initializer for our data, on platforms that need it,
-  /// and for any profile output file that was specified.
-  void emitInitialization();
-};
-
 } // end namespace llvm
 
 #endif // LLVM_TRANSFORMS_INSTRUMENTATION_INSTRPROFILING_H
diff --git a/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp b/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
index adb4ffd4c812..c1127259d304 100644
--- a/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
+++ b/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
@@ -152,6 +152,155 @@ cl::opt<bool> SkipRetExitBlock(
     "skip-ret-exit-block", cl::init(true),
     cl::desc("Suppress counter promotion if exit blocks contain ret."));
 
+using LoadStorePair = std::pair<Instruction *, Instruction *>;
+
+class InstrProfiling final {
+public:
+  InstrProfiling(Module &M, const InstrProfOptions &Options,
+                 std::function<const TargetLibraryInfo &(Function &F)> GetTLI,
+                 bool IsCS)
+      : M(M), Options(Options), TT(Triple(M.getTargetTriple())), IsCS(IsCS),
+        GetTLI(GetTLI) {}
+
+  bool lower();
+
+private:
+  Module &M;
+  const InstrProfOptions Options;
+  const Triple TT;
+  // Is this lowering for the context-sensitive instrumentation.
+  const bool IsCS;
+
+  std::function<const TargetLibraryInfo &(Function &F)> GetTLI;
+  struct PerFunctionProfileData {
+    uint32_t NumValueSites[IPVK_Last + 1] = {};
+    GlobalVariable *RegionCounters = nullptr;
+    GlobalVariable *DataVar = nullptr;
+    GlobalVariable *RegionBitmaps = nullptr;
+    uint32_t NumBitmapBytes = 0;
+
+    PerFunctionProfileData() = default;
+  };
+  DenseMap<GlobalVariable *, PerFunctionProfileData> ProfileDataMap;
+  /// If runtime relocation is enabled, this maps functions to the load
+  /// instruction that produces the profile relocation bias.
+  DenseMap<const Function *, LoadInst *> FunctionToProfileBiasMap;
+  std::vector<GlobalValue *> CompilerUsedVars;
+  std::vector<GlobalValue *> UsedVars;
+  std::vector<GlobalVariable *> ReferencedNames;
+  GlobalVariable *NamesVar = nullptr;
+  size_t NamesSize = 0;
+
+  // vector of counter load/store pairs to be register promoted.
+  std::vector<LoadStorePair> PromotionCandidates;
+
+  int64_t TotalCountersPromoted = 0;
+
+  /// Lower instrumentation intrinsics in the function. Returns true if there
+  /// any lowering.
+  bool lowerIntrinsics(Function *F);
+
+  /// Register-promote counter loads and stores in loops.
+  void promoteCounterLoadStores(Function *F);
+
+  /// Returns true if relocating counters at runtime is enabled.
+  bool isRuntimeCounterRelocationEnabled() const;
+
+  /// Returns true if profile counter update register promotion is enabled.
+  bool isCounterPromotionEnabled() const;
+
+  /// Count the number of instrumented value sites for the function.
+  void computeNumValueSiteCounts(InstrProfValueProfileInst *Ins);
+
+  /// Replace instrprof.value.profile with a call to runtime library.
+  void lowerValueProfileInst(InstrProfValueProfileInst *Ins);
+
+  /// Replace instrprof.cover with a store instruction to the coverage byte.
+  void lowerCover(InstrProfCoverInst *Inc);
+
+  /// Replace instrprof.timestamp with a call to
+  /// INSTR_PROF_PROFILE_SET_TIMESTAMP.
+  void lowerTimestamp(InstrProfTimestampInst *TimestampInstruction);
+
+  /// Replace instrprof.increment with an increment of the appropriate value.
+  void lowerIncrement(InstrProfIncrementInst *Inc);
+
+  /// Force emitting of name vars for unused functions.
+  void lowerCoverageData(GlobalVariable *CoverageNamesVar);
+
+  /// Replace instrprof.mcdc.tvbitmask.update with a shift and or instruction
+  /// using the index represented by the a temp value into a bitmap.
+  void lowerMCDCTestVectorBitmapUpdate(InstrProfMCDCTVBitmapUpdate *Ins);
+
+  /// Replace instrprof.mcdc.temp.update with a shift and or instruction using
+  /// the corresponding condition ID.
+  void lowerMCDCCondBitmapUpdate(InstrProfMCDCCondBitmapUpdate *Ins);
+
+  /// Compute the address of the counter value that this profiling instruction
+  /// acts on.
+  Value *getCounterAddress(InstrProfCntrInstBase *I);
+
+  /// Get the region counters for an increment, creating them if necessary.
+  ///
+  /// If the counter array doesn't yet exist, the profile data variables
+  /// referring to them will also be created.
+  GlobalVariable *getOrCreateRegionCounters(InstrProfCntrInstBase *Inc);
+
+  /// Create the region counters.
+  GlobalVariable *createRegionCounters(InstrProfCntrInstBase *Inc,
+                                       StringRef Name,
+                                       GlobalValue::LinkageTypes Linkage);
+
+  /// Compute the address of the test vector bitmap that this profiling
+  /// instruction acts on.
+  Value *getBitmapAddress(InstrProfMCDCTVBitmapUpdate *I);
+
+  /// Get the region bitmaps for an increment, creating them if necessary.
+  ///
+  /// If the bitmap array doesn't yet exist, the profile data variables
+  /// referring to them will also be created.
+  GlobalVariable *getOrCreateRegionBitmaps(InstrProfMCDCBitmapInstBase *Inc);
+
+  /// Create the MC/DC bitmap as a byte-aligned array of bytes associated with
+  /// an MC/DC Decision region. The number of bytes required is indicated by
+  /// the intrinsic used (type InstrProfMCDCBitmapInstBase).  This is called
+  /// as part of setupProfileSection() and is conceptually very similar to
+  /// what is done for profile data counters in createRegionCounters().
+  GlobalVariable *createRegionBitmaps(InstrProfMCDCBitmapInstBase *Inc,
+                                      StringRef Name,
+                                      GlobalValue::LinkageTypes Linkage);
+
+  /// Set Comdat property of GV, if required.
+  void maybeSetComdat(GlobalVariable *GV, Function *Fn, StringRef VarName);
+
+  /// Setup the sections into which counters and bitmaps are allocated.
+  GlobalVariable *setupProfileSection(InstrProfInstBase *Inc,
+                                      InstrProfSectKind IPSK);
+
+  /// Create INSTR_PROF_DATA variable for counters and bitmaps.
+  void createDataVariable(InstrProfCntrInstBase *Inc);
+
+  /// Emit the section with compressed function names.
+  void emitNameData();
+
+  /// Emit value nodes section for value profiling.
+  void emitVNodes();
+
+  /// Emit runtime registration functions for each profile data variable.
+  void emitRegistration();
+
+  /// Emit the necessary plumbing to pull in the runtime initialization.
+  /// Returns true if a change was made.
+  bool emitRuntimeHook();
+
+  /// Add uses of our data variables and runtime hook.
+  void emitUses();
+
+  /// Create a static initializer for our data, on platforms that need it,
+  /// and for any profile output file that was specified.
+  void emitInitialization();
+};
+
 ///
 /// A helper class to promote one counter RMW operation in the loop
 /// into register update.
-- 
GitLab


From a43641c9dbd7e61d10f130858b55cf011260cebf Mon Sep 17 00:00:00 2001
From: Matthias Springer <me@m-sp.org>
Date: Tue, 12 Dec 2023 08:56:23 +0900
Subject: [PATCH 194/349] [mlir][bufferization] Fix
 `regionOperatesOnMemrefValues` (#75016)

`Region::walk([](Block *b) {...})` does not enumerate blocks that are
direct children of the region. These blocks must be checked manually.
---
 .../OwnershipBasedBufferDeallocation.cpp        | 16 +++++++++++++---
 .../dealloc-region-branchop-interface.mlir      | 17 ++++++++++++++++-
 2 files changed, 29 insertions(+), 4 deletions(-)

diff --git a/mlir/lib/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation.cpp b/mlir/lib/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation.cpp
index 9459cc43547f..38ffae68a43d 100644
--- a/mlir/lib/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation.cpp
+++ b/mlir/lib/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation.cpp
@@ -463,7 +463,7 @@ BufferDeallocation::materializeUniqueOwnership(OpBuilder &builder, Value memref,
 }
 
 static bool regionOperatesOnMemrefValues(Region &region) {
-  WalkResult result = region.walk([](Block *block) {
+  auto checkBlock = [](Block *block) {
     if (llvm::any_of(block->getArguments(), isMemref))
       return WalkResult::interrupt();
     for (Operation &op : *block) {
@@ -473,8 +473,18 @@ static bool regionOperatesOnMemrefValues(Region &region) {
         return WalkResult::interrupt();
     }
     return WalkResult::advance();
-  });
-  return result.wasInterrupted();
+  };
+  WalkResult result = region.walk(checkBlock);
+  if (result.wasInterrupted())
+    return true;
+
+  // Note: Block::walk/Region::walk visits only blocks that are nested under
+  // nested operations, but not direct children.
+  for (Block &block : region)
+    if (checkBlock(&block).wasInterrupted())
+      return true;
+
+  return false;
 }
 
 LogicalResult
diff --git a/mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/dealloc-region-branchop-interface.mlir b/mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/dealloc-region-branchop-interface.mlir
index ad7c4c783e90..1a8a930bc900 100644
--- a/mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/dealloc-region-branchop-interface.mlir
+++ b/mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/dealloc-region-branchop-interface.mlir
@@ -531,8 +531,8 @@ func.func @noRegionBranchOpInterface() {
 // This is not allowed in buffer deallocation.
 
 func.func @noRegionBranchOpInterface() {
-  // expected-error@+1 {{All operations with attached regions need to implement the RegionBranchOpInterface.}}
   %0 = "test.bar"() ({
+    // expected-error@+1 {{All operations with attached regions need to implement the RegionBranchOpInterface.}}
     %1 = "test.bar"() ({
       %2 = "test.get_memref"() : () -> memref<2xi32>
       "test.yield"(%2) : (memref<2xi32>) -> ()
@@ -544,6 +544,21 @@ func.func @noRegionBranchOpInterface() {
 
 // -----
 
+// Test Case: The op "test.bar" does not implement the RegionBranchOpInterface.
+// This is not allowed in buffer deallocation.
+
+func.func @noRegionBranchOpInterface() {
+  // expected-error@+1 {{All operations with attached regions need to implement the RegionBranchOpInterface.}}
+  %0 = "test.bar"() ({
+    %2 = "test.get_memref"() : () -> memref<2xi32>
+    %3 = "test.foo"(%2) : (memref<2xi32>) -> (i32)
+    "test.yield"(%3) : (i32) -> ()
+  }) : () -> (i32)
+  "test.terminator"() : () -> ()
+}
+
+// -----
+
 func.func @while_two_arg(%arg0: index) {
   %a = memref.alloc(%arg0) : memref<?xf32>
   scf.while (%arg1 = %a, %arg2 = %a) : (memref<?xf32>, memref<?xf32>) -> (memref<?xf32>, memref<?xf32>) {
-- 
GitLab


From fb9a8512240a44f5d1f03bb5e524b42e0946c689 Mon Sep 17 00:00:00 2001
From: Alexander Yermolovich <43973793+ayermolo@users.noreply.github.com>
Date: Mon, 11 Dec 2023 15:56:32 -0800
Subject: [PATCH 195/349] [BOLT][DWARF] Fix handling of debug_str_offsets
 (#75100)

We were not setting size field of .debug_str_offsets correctly. Fixed
it, and added a test.
---
 bolt/include/bolt/Core/DebugData.h            |  2 -
 bolt/lib/Core/DebugData.cpp                   |  6 +-
 bolt/lib/Rewrite/DWARFRewriter.cpp            |  5 +-
 .../X86/dwarf5-two-cu-str-offset-table.test   | 66 +++++++++++++++++++
 4 files changed, 73 insertions(+), 6 deletions(-)
 create mode 100644 bolt/test/X86/dwarf5-two-cu-str-offset-table.test

diff --git a/bolt/include/bolt/Core/DebugData.h b/bolt/include/bolt/Core/DebugData.h
index 23430cc36167..9f0dd88b115f 100644
--- a/bolt/include/bolt/Core/DebugData.h
+++ b/bolt/include/bolt/Core/DebugData.h
@@ -459,8 +459,6 @@ private:
   std::unique_ptr<raw_svector_ostream> StrOffsetsStream;
   std::map<uint32_t, uint32_t> IndexToAddressMap;
   std::unordered_map<uint64_t, uint64_t> ProcessedBaseOffsets;
-  // Section size not including header.
-  uint32_t CurrentSectionSize{0};
   bool StrOffsetSectionWasModified = false;
 };
 
diff --git a/bolt/lib/Core/DebugData.cpp b/bolt/lib/Core/DebugData.cpp
index 9061d4f0e197..dcf3a36e35e3 100644
--- a/bolt/lib/Core/DebugData.cpp
+++ b/bolt/lib/Core/DebugData.cpp
@@ -889,8 +889,10 @@ void DebugStrOffsetsWriter::finalizeSection(DWARFUnit &Unit,
   // Handling re-use of str-offsets section.
   if (RetVal == ProcessedBaseOffsets.end() || StrOffsetSectionWasModified) {
     // Writing out the header for each section.
-    support::endian::write(*StrOffsetsStream, CurrentSectionSize + 4,
-                           llvm::endianness::little);
+    support::endian::write(
+        *StrOffsetsStream,
+        static_cast<uint32_t>(IndexToAddressMap.size() * 4 + 4),
+        llvm::endianness::little);
     support::endian::write(*StrOffsetsStream, static_cast<uint16_t>(5),
                            llvm::endianness::little);
     support::endian::write(*StrOffsetsStream, static_cast<uint16_t>(0),
diff --git a/bolt/lib/Rewrite/DWARFRewriter.cpp b/bolt/lib/Rewrite/DWARFRewriter.cpp
index 5580d85e3fa7..1cc07c1cc9f7 100644
--- a/bolt/lib/Rewrite/DWARFRewriter.cpp
+++ b/bolt/lib/Rewrite/DWARFRewriter.cpp
@@ -696,8 +696,9 @@ void DWARFRewriter::updateDebugInfo() {
     std::optional<DWARFUnit *> SplitCU;
     std::optional<uint64_t> RangesBase;
     std::optional<uint64_t> DWOId = Unit->getDWOId();
-    StrOffstsWriter->initialize(Unit->getStringOffsetSection(),
-                                Unit->getStringOffsetsTableContribution());
+    if (Unit->getVersion() >= 5)
+      StrOffstsWriter->initialize(Unit->getStringOffsetSection(),
+                                  Unit->getStringOffsetsTableContribution());
     if (DWOId)
       SplitCU = BC.getDWOCU(*DWOId);
     DebugLocWriter *DebugLocWriter = createRangeLocList(*Unit);
diff --git a/bolt/test/X86/dwarf5-two-cu-str-offset-table.test b/bolt/test/X86/dwarf5-two-cu-str-offset-table.test
new file mode 100644
index 000000000000..20503951df4e
--- /dev/null
+++ b/bolt/test/X86/dwarf5-two-cu-str-offset-table.test
@@ -0,0 +1,66 @@
+# REQUIRES: system-linux
+
+# RUN: llvm-mc -dwarf-version=5 -filetype=obj -triple x86_64-unknown-linux %p/Inputs/dwarf5_main.s -o %tmain.o
+# RUN: llvm-mc -dwarf-version=5 -filetype=obj -triple x86_64-unknown-linux %p/Inputs/dwarf5_helper.s -o %thelper.o
+# RUN: %clang %cflags -dwarf-5 %tmain.o %thelper.o -o %t.exe -Wl,-q
+# RUN: llvm-bolt %t.exe -o %t.bolt --update-debug-sections
+# RUN: llvm-dwarfdump --show-form --verbose --debug-str-offsets %t.exe > %t.txt
+# RUN: llvm-dwarfdump --show-form --verbose --debug-str-offsets %t.bolt >> %t.txt
+# RUN: cat %t.txt | FileCheck --check-prefix=CHECK %s
+
+## This test checks we correclty re-renerate .debug_str_offsets.
+
+# CHECK: .debug_str_offsets contents
+# CHECK-NEXT: 0x00000000: Contribution size = 52, Format = DWARF32, Version = 5
+# CHECK-NEXT: "clang version 15.0.0"
+# CHECK-NEXT: "main.cpp"
+# CHECK-NEXT: "/testLocListMultiple"
+# CHECK-NEXT: "_Z3usePiS_"
+# CHECK-NEXT: "use"
+# CHECK-NEXT: "main"
+# CHECK-NEXT: "int"
+# CHECK-NEXT: "x"
+# CHECK-NEXT: "y"
+# CHECK-NEXT: "argc"
+# CHECK-NEXT: "argv"
+# CHECK-NEXT: "char"
+# CHECK-NEXT: 0x00000038: Contribution size = 48, Format = DWARF32, Version = 5
+# CHECK-NEXT: "clang version 15.0.0)"
+# CHECK-NEXT: "foo.cpp"
+# CHECK-NEXT: "/testLocListMultiple"
+# CHECK-NEXT: "fooVar"
+# CHECK-NEXT: "int"
+# CHECK-NEXT: "_Z6useFooPi"
+# CHECK-NEXT: "useFoo"
+# CHECK-NEXT: "x"
+# CHECK-NEXT: "_Z3fooi"
+# CHECK-NEXT: "foo"
+# CHECK-NEXT: "argc"
+
+## Checking post bolt
+# CHECK: .debug_str_offsets contents
+# CHECK-NEXT: 0x00000000: Contribution size = 52, Format = DWARF32, Version = 5
+# CHECK-NEXT: "clang version 15.0.0"
+# CHECK-NEXT: "main.cpp"
+# CHECK-NEXT: "/testLocListMultiple"
+# CHECK-NEXT: "_Z3usePiS_"
+# CHECK-NEXT: "use"
+# CHECK-NEXT: "main"
+# CHECK-NEXT: "int"
+# CHECK-NEXT: "x"
+# CHECK-NEXT: "y"
+# CHECK-NEXT: "argc"
+# CHECK-NEXT: "argv"
+# CHECK-NEXT: "char"
+# CHECK-NEXT: 0x00000038: Contribution size = 48, Format = DWARF32, Version = 5
+# CHECK-NEXT: "clang version 15.0.0)"
+# CHECK-NEXT: "foo.cpp"
+# CHECK-NEXT: "/testLocListMultiple"
+# CHECK-NEXT: "fooVar"
+# CHECK-NEXT: "int"
+# CHECK-NEXT: "_Z6useFooPi"
+# CHECK-NEXT: "useFoo"
+# CHECK-NEXT: "x"
+# CHECK-NEXT: "_Z3fooi"
+# CHECK-NEXT: "foo"
+# CHECK-NEXT: "argc"
-- 
GitLab


From 95d6aa21fbd41b786a6fb50821bb84b59b3b20e7 Mon Sep 17 00:00:00 2001
From: Matthias Springer <me@m-sp.org>
Date: Tue, 12 Dec 2023 08:56:47 +0900
Subject: [PATCH 196/349] [mlir][SparseTensor][NFC] Use `tensor.empty` for
 dense tensors (#74804)

Use `tensor.empty` + initialization for dense tensors instead of
`bufferization.alloc_tensor`.
---
 .../Dialect/SparseTensor/CPU/sparse_matmul_slice.mlir      | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matmul_slice.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matmul_slice.mlir
index 8c42f667bb60..85d51931db6c 100644
--- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matmul_slice.mlir
+++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matmul_slice.mlir
@@ -158,7 +158,6 @@ module {
         [ 0.0, 0.0, 6.0, 0.0 ],
         [ 0.0, 0.0, 7.0, 8.0 ]
     ]> : tensor<8x4xf64>
-    %zero = arith.constant dense<0.0> : tensor<4x4xf64>
 
     // Convert all these matrices to sparse format.
     %tmp = sparse_tensor.convert %sa : tensor<8x8xf64> to tensor<8x8xf64, #DCSR>
@@ -257,9 +256,11 @@ module {
     %ds1 = tensor.extract_slice %sa[0, 1][4, 4][2, 1] : tensor<8x8xf64> to tensor<4x4xf64>
     %ds2 = tensor.extract_slice %sb[0, 0][4, 4][2, 1] : tensor<8x4xf64> to tensor<4x4xf64>
 
-    %d = bufferization.alloc_tensor() copy(%zero) : tensor<4x4xf64>
+    %d = tensor.empty() : tensor<4x4xf64>
+    %zeroed = linalg.fill ins(%f0 : f64) outs(%d : tensor<4x4xf64>)
+        -> tensor<4x4xf64>
     %r = linalg.matmul ins(%ds2, %ds1: tensor<4x4xf64>, tensor<4x4xf64>)
-                       outs(%d: tensor<4x4xf64>) -> tensor<4x4xf64>
+                       outs(%zeroed: tensor<4x4xf64>) -> tensor<4x4xf64>
     %du = tensor.cast %r : tensor<4x4xf64> to tensor<*xf64>
     call @printMemrefF64(%du) : (tensor<*xf64>) -> ()
 
-- 
GitLab


From 67c631d283fc96d652304199cd625be426b98f8e Mon Sep 17 00:00:00 2001
From: David Blaikie <dblaikie@gmail.com>
Date: Mon, 11 Dec 2023 23:50:11 +0000
Subject: [PATCH 197/349] [ADT][StringMap] Add ability to precompute and reuse
 the string hash
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Useful for lldb's const string pool, using the hash to determine which
string map to lock and query/insert.

Derived from https://reviews.llvm.org/D122974 by Luboš Luňák
---
 llvm/include/llvm/ADT/StringMap.h    | 49 +++++++++++++++++++++++-----
 llvm/lib/Support/StringMap.cpp       | 15 ++++++---
 llvm/unittests/ADT/StringMapTest.cpp | 11 +++++++
 3 files changed, 63 insertions(+), 12 deletions(-)

diff --git a/llvm/include/llvm/ADT/StringMap.h b/llvm/include/llvm/ADT/StringMap.h
index 466f95254d10..32e611467ac5 100644
--- a/llvm/include/llvm/ADT/StringMap.h
+++ b/llvm/include/llvm/ADT/StringMap.h
@@ -17,6 +17,7 @@
 #include "llvm/ADT/StringMapEntry.h"
 #include "llvm/ADT/iterator.h"
 #include "llvm/Support/AllocatorBase.h"
+#include "llvm/Support/DJB.h"
 #include "llvm/Support/PointerLikeTypeTraits.h"
 #include <initializer_list>
 #include <iterator>
@@ -60,12 +61,20 @@ protected:
   /// specified bucket will be non-null.  Otherwise, it will be null.  In either
   /// case, the FullHashValue field of the bucket will be set to the hash value
   /// of the string.
-  unsigned LookupBucketFor(StringRef Key);
+  unsigned LookupBucketFor(StringRef Key) {
+    return LookupBucketFor(Key, hash(Key));
+  }
+
+  /// Overload that explicitly takes precomputed hash(Key).
+  unsigned LookupBucketFor(StringRef Key, uint32_t FullHashValue);
 
   /// FindKey - Look up the bucket that contains the specified key. If it exists
   /// in the map, return the bucket number of the key.  Otherwise return -1.
   /// This does not modify the map.
-  int FindKey(StringRef Key) const;
+  int FindKey(StringRef Key) const { return FindKey(Key, hash(Key)); }
+
+  /// Overload that explicitly takes precomputed hash(Key).
+  int FindKey(StringRef Key, uint32_t FullHashValue) const;
 
   /// RemoveKey - Remove the specified StringMapEntry from the table, but do not
   /// delete it.  This aborts if the value isn't in the table.
@@ -94,6 +103,13 @@ public:
   bool empty() const { return NumItems == 0; }
   unsigned size() const { return NumItems; }
 
+  /// Returns the hash value that will be used for the given string.
+  /// This allows precomputing the value and passing it explicitly
+  /// to some of the functions.
+  /// The implementation of this function is not guaranteed to be stable
+  /// and may change.
+  static uint32_t hash(StringRef Key);
+
   void swap(StringMapImpl &Other) {
     std::swap(TheTable, Other.TheTable);
     std::swap(NumBuckets, Other.NumBuckets);
@@ -215,15 +231,19 @@ public:
                       StringMapKeyIterator<ValueTy>(end()));
   }
 
-  iterator find(StringRef Key) {
-    int Bucket = FindKey(Key);
+  iterator find(StringRef Key) { return find(Key, hash(Key)); }
+
+  iterator find(StringRef Key, uint32_t FullHashValue) {
+    int Bucket = FindKey(Key, FullHashValue);
     if (Bucket == -1)
       return end();
     return iterator(TheTable + Bucket, true);
   }
 
-  const_iterator find(StringRef Key) const {
-    int Bucket = FindKey(Key);
+  const_iterator find(StringRef Key) const { return find(Key, hash(Key)); }
+
+  const_iterator find(StringRef Key, uint32_t FullHashValue) const {
+    int Bucket = FindKey(Key, FullHashValue);
     if (Bucket == -1)
       return end();
     return const_iterator(TheTable + Bucket, true);
@@ -305,7 +325,13 @@ public:
   /// if and only if the insertion takes place, and the iterator component of
   /// the pair points to the element with key equivalent to the key of the pair.
   std::pair<iterator, bool> insert(std::pair<StringRef, ValueTy> KV) {
-    return try_emplace(KV.first, std::move(KV.second));
+    return try_emplace_with_hash(KV.first, hash(KV.first),
+                                 std::move(KV.second));
+  }
+
+  std::pair<iterator, bool> insert(std::pair<StringRef, ValueTy> KV,
+                                   uint32_t FullHashValue) {
+    return try_emplace_with_hash(KV.first, FullHashValue, std::move(KV.second));
   }
 
   /// Inserts elements from range [first, last). If multiple elements in the
@@ -339,7 +365,14 @@ public:
   /// the pair points to the element with key equivalent to the key of the pair.
   template <typename... ArgsTy>
   std::pair<iterator, bool> try_emplace(StringRef Key, ArgsTy &&...Args) {
-    unsigned BucketNo = LookupBucketFor(Key);
+    return try_emplace_with_hash(Key, hash(Key), std::forward<ArgsTy>(Args)...);
+  }
+
+  template <typename... ArgsTy>
+  std::pair<iterator, bool> try_emplace_with_hash(StringRef Key,
+                                                  uint32_t FullHashValue,
+                                                  ArgsTy &&...Args) {
+    unsigned BucketNo = LookupBucketFor(Key, FullHashValue);
     StringMapEntryBase *&Bucket = TheTable[BucketNo];
     if (Bucket && Bucket != getTombstoneVal())
       return std::make_pair(iterator(TheTable + BucketNo, false),
diff --git a/llvm/lib/Support/StringMap.cpp b/llvm/lib/Support/StringMap.cpp
index 67c05a87959c..451108d01d38 100644
--- a/llvm/lib/Support/StringMap.cpp
+++ b/llvm/lib/Support/StringMap.cpp
@@ -43,6 +43,8 @@ static inline unsigned *getHashTable(StringMapEntryBase **TheTable,
   return reinterpret_cast<unsigned *>(TheTable + NumBuckets + 1);
 }
 
+uint32_t StringMapImpl::hash(StringRef Key) { return xxh3_64bits(Key); }
+
 StringMapImpl::StringMapImpl(unsigned InitSize, unsigned itemSize) {
   ItemSize = itemSize;
 
@@ -81,11 +83,14 @@ void StringMapImpl::init(unsigned InitSize) {
 /// specified bucket will be non-null.  Otherwise, it will be null.  In either
 /// case, the FullHashValue field of the bucket will be set to the hash value
 /// of the string.
-unsigned StringMapImpl::LookupBucketFor(StringRef Name) {
+unsigned StringMapImpl::LookupBucketFor(StringRef Name,
+                                        uint32_t FullHashValue) {
+#ifdef EXPENSIVE_CHECKS
+  assert(FullHashValue == hash(Name));
+#endif
   // Hash table unallocated so far?
   if (NumBuckets == 0)
     init(16);
-  unsigned FullHashValue = xxh3_64bits(Name);
   if (shouldReverseIterate())
     FullHashValue = ~FullHashValue;
   unsigned BucketNo = FullHashValue & (NumBuckets - 1);
@@ -139,10 +144,12 @@ unsigned StringMapImpl::LookupBucketFor(StringRef Name) {
 /// FindKey - Look up the bucket that contains the specified key. If it exists
 /// in the map, return the bucket number of the key.  Otherwise return -1.
 /// This does not modify the map.
-int StringMapImpl::FindKey(StringRef Key) const {
+int StringMapImpl::FindKey(StringRef Key, uint32_t FullHashValue) const {
   if (NumBuckets == 0)
     return -1; // Really empty table?
-  unsigned FullHashValue = xxh3_64bits(Key);
+#ifdef EXPENSIVE_CHECKS
+  assert(FullHashValue == hash(Key);
+#endif
   if (shouldReverseIterate())
     FullHashValue = ~FullHashValue;
   unsigned BucketNo = FullHashValue & (NumBuckets - 1);
diff --git a/llvm/unittests/ADT/StringMapTest.cpp b/llvm/unittests/ADT/StringMapTest.cpp
index f9b138e9a472..c9ef3f8a096e 100644
--- a/llvm/unittests/ADT/StringMapTest.cpp
+++ b/llvm/unittests/ADT/StringMapTest.cpp
@@ -487,6 +487,17 @@ TEST_F(StringMapTest, NotEqualWithDifferentValues) {
   ASSERT_TRUE(B != A);
 }
 
+TEST_F(StringMapTest, PrecomputedHash) {
+  StringMap<int> A;
+  StringRef Key = "foo";
+  int Value = 42;
+  uint64_t Hash = StringMap<int>::hash(Key);
+  A.insert({"foo", Value}, Hash);
+  auto I = A.find(Key, Hash);
+  ASSERT_NE(I, A.end());
+  ASSERT_EQ(I->second, Value);
+}
+
 struct Countable {
   int &InstanceCount;
   int Number;
-- 
GitLab


From 2e197602305be18b963928e6ae024a004a95af6d Mon Sep 17 00:00:00 2001
From: David Blaikie <dblaikie@gmail.com>
Date: Mon, 11 Dec 2023 23:51:51 +0000
Subject: [PATCH 198/349] lldb: Cache string hash during ConstString pool
 queries/insertions

lldb was rehashing the string 3 times (once to determine which StringMap
to use, once to query the StringMap, once to insert) on insertion (twice
on successful lookup).

This patch allows the lldb to benefit from hash improvements in LLVM
(from djbHash to xxh3).

Though further changes would be needed to cache this value to disk - we
shouldn't rely on the StringMap::hash remaining the same in the
future/this value should not be serialized to disk. If we want cache
this value StringMap should take a hashing template parameter to allow
for a fixed hash to be requested.
---
 lldb/source/Utility/ConstString.cpp | 50 ++++++++++++++++-------------
 1 file changed, 28 insertions(+), 22 deletions(-)

diff --git a/lldb/source/Utility/ConstString.cpp b/lldb/source/Utility/ConstString.cpp
index 4535771adfb7..ea897dc611cc 100644
--- a/lldb/source/Utility/ConstString.cpp
+++ b/lldb/source/Utility/ConstString.cpp
@@ -77,10 +77,10 @@ public:
     return 0;
   }
 
-  StringPoolValueType GetMangledCounterpart(const char *ccstr) const {
+  StringPoolValueType GetMangledCounterpart(const char *ccstr) {
     if (ccstr != nullptr) {
-      const uint8_t h = hash(llvm::StringRef(ccstr));
-      llvm::sys::SmartScopedReader<false> rlock(m_string_pools[h].m_mutex);
+      const PoolEntry &pool = selectPool(llvm::StringRef(ccstr));
+      llvm::sys::SmartScopedReader<false> rlock(pool.m_mutex);
       return GetStringMapEntryFromKeyData(ccstr).getValue();
     }
     return nullptr;
@@ -100,19 +100,20 @@ public:
 
   const char *GetConstCStringWithStringRef(llvm::StringRef string_ref) {
     if (string_ref.data()) {
-      const uint8_t h = hash(string_ref);
+      const uint32_t string_hash = StringPool::hash(string_ref);
+      PoolEntry &pool = selectPool(string_hash);
 
       {
-        llvm::sys::SmartScopedReader<false> rlock(m_string_pools[h].m_mutex);
-        auto it = m_string_pools[h].m_string_map.find(string_ref);
-        if (it != m_string_pools[h].m_string_map.end())
+        llvm::sys::SmartScopedReader<false> rlock(pool.m_mutex);
+        auto it = pool.m_string_map.find(string_ref, string_hash);
+        if (it != pool.m_string_map.end())
           return it->getKeyData();
       }
 
-      llvm::sys::SmartScopedWriter<false> wlock(m_string_pools[h].m_mutex);
+      llvm::sys::SmartScopedWriter<false> wlock(pool.m_mutex);
       StringPoolEntryType &entry =
-          *m_string_pools[h]
-               .m_string_map.insert(std::make_pair(string_ref, nullptr))
+          *pool.m_string_map
+               .insert(std::make_pair(string_ref, nullptr), string_hash)
                .first;
       return entry.getKeyData();
     }
@@ -125,12 +126,14 @@ public:
     const char *demangled_ccstr = nullptr;
 
     {
-      const uint8_t h = hash(demangled);
-      llvm::sys::SmartScopedWriter<false> wlock(m_string_pools[h].m_mutex);
+      const uint32_t demangled_hash = StringPool::hash(demangled);
+      PoolEntry &pool = selectPool(demangled_hash);
+      llvm::sys::SmartScopedWriter<false> wlock(pool.m_mutex);
 
       // Make or update string pool entry with the mangled counterpart
-      StringPool &map = m_string_pools[h].m_string_map;
-      StringPoolEntryType &entry = *map.try_emplace(demangled).first;
+      StringPool &map = pool.m_string_map;
+      StringPoolEntryType &entry =
+          *map.try_emplace_with_hash(demangled, demangled_hash).first;
 
       entry.second = mangled_ccstr;
 
@@ -141,8 +144,8 @@ public:
     {
       // Now assign the demangled const string as the counterpart of the
       // mangled const string...
-      const uint8_t h = hash(llvm::StringRef(mangled_ccstr));
-      llvm::sys::SmartScopedWriter<false> wlock(m_string_pools[h].m_mutex);
+      PoolEntry &pool = selectPool(llvm::StringRef(mangled_ccstr));
+      llvm::sys::SmartScopedWriter<false> wlock(pool.m_mutex);
       GetStringMapEntryFromKeyData(mangled_ccstr).setValue(demangled_ccstr);
     }
 
@@ -171,17 +174,20 @@ public:
   }
 
 protected:
-  uint8_t hash(llvm::StringRef s) const {
-    uint32_t h = llvm::djbHash(s);
-    return ((h >> 24) ^ (h >> 16) ^ (h >> 8) ^ h) & 0xff;
-  }
-
   struct PoolEntry {
     mutable llvm::sys::SmartRWMutex<false> m_mutex;
     StringPool m_string_map;
   };
 
   std::array<PoolEntry, 256> m_string_pools;
+
+  PoolEntry &selectPool(const llvm::StringRef &s) {
+    return selectPool(StringPool::hash(s));
+  }
+
+  PoolEntry &selectPool(uint32_t h) {
+    return m_string_pools[((h >> 24) ^ (h >> 16) ^ (h >> 8) ^ h) & 0xff];
+  }
 };
 
 // Frameworks and dylibs aren't supposed to have global C++ initializers so we
@@ -197,7 +203,7 @@ static Pool &StringPool() {
   static Pool *g_string_pool = nullptr;
 
   llvm::call_once(g_pool_initialization_flag,
-                 []() { g_string_pool = new Pool(); });
+                  []() { g_string_pool = new Pool(); });
 
   return *g_string_pool;
 }
-- 
GitLab


From d36b483f4f1109f53399ef82fda32f2c04d4ef44 Mon Sep 17 00:00:00 2001
From: Maksim Levental <maksim.levental@gmail.com>
Date: Mon, 11 Dec 2023 18:35:02 -0600
Subject: [PATCH 199/349] [mlir][python] update type stubs (#75099)

---
 mlir/python/mlir/_mlir_libs/_mlir/ir.pyi | 2530 +++++++++++++++++-----
 1 file changed, 2046 insertions(+), 484 deletions(-)

diff --git a/mlir/python/mlir/_mlir_libs/_mlir/ir.pyi b/mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
index 2609117dd220..fa591e5f142d 100644
--- a/mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
+++ b/mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
@@ -1,15 +1,62 @@
 # Originally imported via:
-#   stubgen {...} -m mlir._mlir_libs._mlir.ir
+#   pybind11-stubgen --print-invalid-expressions-as-is mlir._mlir_libs._mlir.ir
+# but with the following diff (in order to remove pipes from types,
+# which we won't support until bumping minimum python to 3.10)
+#
+# --------------------- diff begins ------------------------------------
+#
+# diff --git a/pybind11_stubgen/printer.py b/pybind11_stubgen/printer.py
+# index 1f755aa..4924927 100644
+# --- a/pybind11_stubgen/printer.py
+# +++ b/pybind11_stubgen/printer.py
+# @@ -283,14 +283,6 @@ class Printer:
+#              return split[0] + "..."
+#
+#      def print_type(self, type_: ResolvedType) -> str:
+# -        if (
+# -            str(type_.name) == "typing.Optional"
+# -            and type_.parameters is not None
+# -            and len(type_.parameters) == 1
+# -        ):
+# -            return f"{self.print_annotation(type_.parameters[0])} | None"
+# -        if str(type_.name) == "typing.Union" and type_.parameters is not None:
+# -            return " | ".join(self.print_annotation(p) for p in type_.parameters)
+#          if type_.parameters:
+#              param_str = (
+#                  "["
+#
+# --------------------- diff ends ------------------------------------
+#
 # Local modifications:
-#   * Rewrite references to 'mlir.ir.' to local types
-#   * Add __all__ with the following incantation:
-#       egrep '^class ' ir.pyi | awk -F ' |:|\\(' '{print "    \"" $2 "\","}'
-#   * Local edits to signatures and types that MyPy did not auto detect (or
-#     detected incorrectly).
-
+#   * Rewrite references to 'mlir.ir' to local types.
+#   * Drop `typing.` everywhere (top-level import instead).
+#   * List -> List, dict -> Dict, Tuple -> Tuple.
+#   * copy-paste Buffer type from typing_extensions.
+#   * Shuffle _OperationBase, AffineExpr, Attribute, Type, Value to the top.
+#   * Patch raw C++ types (like "PyAsmState") with a regex like `Py(.*)`.
+#   * _BaseContext -> Context, MlirType -> Type, MlirTypeID -> TypeID, MlirAttribute -> Attribute.
+#   * Local edits to signatures and types that pybind11-stubgen did not auto detect (or detected incorrectly).
+#   * Add MLIRError, _GlobalDebug, _OperationBase to __all__ by hand.
+#   * Fill in `Any`s where possible.
+#   * black formatting.
+
+from __future__ import annotations
+
+import abc
+import collections
+import io
 from typing import (
-    Any, Callable, ClassVar, Dict, List, Optional, Sequence, Tuple,
-    Type as _Type, TypeVar
+    Any,
+    Callable,
+    ClassVar,
+    Dict,
+    List,
+    Optional,
+    Sequence,
+    Tuple,
+    Type as _Type,
+    TypeVar,
+    Union,
 )
 
 from typing import overload
@@ -30,6 +77,8 @@ __all__ = [
     "AffineSymbolExpr",
     "ArrayAttr",
     "ArrayAttributeIterator",
+    "AsmState",
+    "AttrBuilder",
     "Attribute",
     "BF16Type",
     "Block",
@@ -40,29 +89,44 @@ __all__ = [
     "BoolAttr",
     "ComplexType",
     "Context",
+    "DenseBoolArrayAttr",
+    "DenseBoolArrayIterator",
     "DenseElementsAttr",
+    "DenseF32ArrayAttr",
+    "DenseF32ArrayIterator",
+    "DenseF64ArrayAttr",
+    "DenseF64ArrayIterator",
     "DenseFPElementsAttr",
+    "DenseI16ArrayAttr",
+    "DenseI16ArrayIterator",
+    "DenseI32ArrayAttr",
+    "DenseI32ArrayIterator",
+    "DenseI64ArrayAttr",
+    "DenseI64ArrayIterator",
+    "DenseI8ArrayAttr",
+    "DenseI8ArrayIterator",
     "DenseIntElementsAttr",
     "DenseResourceElementsAttr",
-    "Dialect",
-    "DialectDescriptor",
-    "Dialects",
     "Diagnostic",
     "DiagnosticHandler",
     "DiagnosticInfo",
     "DiagnosticSeverity",
+    "Dialect",
+    "DialectDescriptor",
+    "DialectRegistry",
+    "Dialects",
     "DictAttr",
-    "Float8E4M3FNType",
-    "Float8E5M2Type",
-    "Float8E4M3FNUZType",
-    "Float8E4M3B11FNUZType",
-    "Float8E5M2FNUZType",
     "F16Type",
-    "FloatTF32Type",
     "F32Type",
     "F64Type",
     "FlatSymbolRefAttr",
+    "Float8E4M3B11FNUZType",
+    "Float8E4M3FNType",
+    "Float8E4M3FNUZType",
+    "Float8E5M2FNUZType",
+    "Float8E5M2Type",
     "FloatAttr",
+    "FloatTF32Type",
     "FunctionType",
     "IndexType",
     "InferShapedTypeOpInterface",
@@ -76,15 +140,18 @@ __all__ = [
     "Location",
     "MemRefType",
     "Module",
-    "MLIRError",
     "NamedAttribute",
     "NoneType",
-    "OpaqueType",
     "OpAttributeMap",
+    "OpOperand",
+    "OpOperandIterator",
     "OpOperandList",
     "OpResult",
     "OpResultList",
+    "OpSuccessors",
     "OpView",
+    "OpaqueAttr",
+    "OpaqueType",
     "Operation",
     "OperationIterator",
     "OperationList",
@@ -94,11 +161,14 @@ __all__ = [
     "RegionSequence",
     "ShapedType",
     "ShapedTypeComponents",
+    "StridedLayoutAttr",
     "StringAttr",
+    "SymbolRefAttr",
     "SymbolTable",
     "TupleType",
     "Type",
     "TypeAttr",
+    "TypeID",
     "UnitAttr",
     "UnrankedMemRefType",
     "UnrankedTensorType",
@@ -108,222 +178,561 @@ __all__ = [
     "_OperationBase",
 ]
 
-# Base classes: declared first to simplify declarations below.
+if hasattr(collections.abc, "Buffer"):
+    Buffer = collections.abc.Buffer
+else:
+    class Buffer(abc.ABC):
+        pass
+
 class _OperationBase:
-    def detach_from_parent(self) -> OpView: ...
-    def get_asm(self, binary: bool = False, large_elements_limit: Optional[int] = None, enable_debug_info: bool = False, pretty_debug_info: bool = False, print_generic_op_form: bool = False, use_local_scope: bool = False, assume_verified: bool = False) -> object: ...
-    def move_after(self, other: _OperationBase) -> None: ...
-    def move_before(self, other: _OperationBase) -> None: ...
-    def print(self, file: Optional[Any] = None, binary: bool = False, large_elements_limit: Optional[int] = None, enable_debug_info: bool = False, pretty_debug_info: bool = False, print_generic_op_form: bool = False, use_local_scope: bool = False, assume_verified: bool = False) -> None: ...
-    def verify(self) -> bool: ...
     @overload
     def __eq__(self, arg0: _OperationBase) -> bool: ...
     @overload
-    def __eq__(self, arg0: object) -> bool: ...
+    def __eq__(self, arg0: _OperationBase) -> bool: ...
     def __hash__(self) -> int: ...
+    def __str__(self) -> str:
+        """
+        Returns the assembly form of the operation.
+        """
+    def clone(self, ip: InsertionPoint = None) -> OpView: ...
+    def detach_from_parent(self) -> OpView:
+        """
+        Detaches the operation from its parent block.
+        """
+    def erase(self) -> None: ...
+    def get_asm(
+        self,
+        binary: bool = False,
+        large_elements_limit: Optional[int] = None,
+        enable_debug_info: bool = False,
+        pretty_debug_info: bool = False,
+        print_generic_op_form: bool = False,
+        use_local_scope: bool = False,
+        assume_verified: bool = False,
+    ) -> Union[io.BytesIO, io.StringIO]:
+        """
+        Gets the assembly form of the operation with all options available.
+
+        Args:
+          binary: Whether to return a bytes (True) or str (False) object. Defaults to
+            False.
+          ... others ...: See the print() method for common keyword arguments for
+            configuring the printout.
+        Returns:
+          Either a bytes or str object, depending on the setting of the 'binary'
+          argument.
+        """
+    def move_after(self, other: _OperationBase) -> None:
+        """
+        Puts self immediately after the other operation in its parent block.
+        """
+    def move_before(self, other: _OperationBase) -> None:
+        """
+        Puts self immediately before the other operation in its parent block.
+        """
+    @overload
+    def print(
+        self,
+        state: AsmState,
+        file: Optional[Any] = None,
+        binary: bool = False,
+    ) -> None:
+        """
+        Prints the assembly form of the operation to a file like object.
+
+        Args:
+          file: The file like object to write to. Defaults to sys.stdout.
+          binary: Whether to write bytes (True) or str (False). Defaults to False.
+          state: AsmState capturing the operation numbering and flags.
+        """
+    @overload
+    def print(
+        self,
+        large_elements_limit: Optional[int] = None,
+        enable_debug_info: bool = False,
+        pretty_debug_info: bool = False,
+        print_generic_op_form: bool = False,
+        use_local_scope: bool = False,
+        assume_verified: bool = False,
+        file: Optional[Any] = None,
+        binary: bool = False,
+    ) -> None:
+        """
+        Prints the assembly form of the operation to a file like object.
+
+        Args:
+          file: The file like object to write to. Defaults to sys.stdout.
+          binary: Whether to write bytes (True) or str (False). Defaults to False.
+          large_elements_limit: Whether to elide elements attributes above this
+            number of elements. Defaults to None (no limit).
+          enable_debug_info: Whether to print debug/location information. Defaults
+            to False.
+          pretty_debug_info: Whether to format debug information for easier reading
+            by a human (warning: the result is unparseable).
+          print_generic_op_form: Whether to print the generic assembly forms of all
+            ops. Defaults to False.
+          use_local_Scope: Whether to print in a way that is more optimized for
+            multi-threaded access but may not be consistent with how the overall
+            module prints.
+          assume_verified: By default, if not printing generic form, the verifier
+            will be run and if it fails, generic form will be printed with a comment
+            about failed verification. While a reasonable default for interactive use,
+            for systematic use, it is often better for the caller to verify explicitly
+            and report failures in a more robust fashion. Set this to True if doing this
+            in order to avoid running a redundant verification. If the IR is actually
+            invalid, behavior is undefined.
+        """
+    def verify(self) -> bool:
+        """
+        Verify the operation. Raises MLIRError if verification fails, and returns true otherwise.
+        """
+    def write_bytecode(self, file: Any, desired_version: Optional[int] = None) -> None:
+        """
+        Write the bytecode form of the operation to a file like object.
+
+        Args:
+          file: The file like object to write to.
+          desired_version: The version of bytecode to emit.
+        Returns:
+          The bytecode writer status.
+        """
     @property
     def _CAPIPtr(self) -> object: ...
     @property
     def attributes(self) -> OpAttributeMap: ...
     @property
-    def context(self) -> Context: ...
+    def context(self) -> Context:
+        """
+        Context that owns the Operation
+        """
     @property
-    def location(self) -> Location: ...
+    def location(self) -> Location:
+        """
+        Returns the source location the operation was defined or derived from.
+        """
     @property
     def name(self) -> str: ...
     @property
     def operands(self) -> OpOperandList: ...
     @property
-    @property
     def parent(self) -> Optional[_OperationBase]: ...
+    @property
     def regions(self) -> RegionSequence: ...
     @property
-    def result(self) -> OpResult: ...
+    def result(self) -> OpResult:
+        """
+        Shortcut to get an op result if it has only one (throws an error otherwise).
+        """
     @property
-    def results(self) -> OpResultList: ...
+    def results(self) -> OpResultList:
+        """
+        Returns the List of Operation results.
+        """
 
 _TOperation = TypeVar("_TOperation", bound=_OperationBase)
 
-# TODO: Auto-generated. Audit and fix.
 class AffineExpr:
-    def __init__(self, *args, **kwargs) -> None: ...
+    @staticmethod
+    @overload
+    def get_add(arg0: AffineExpr, arg1: AffineExpr) -> AffineAddExpr:
+        """
+        Gets an affine expression containing a sum of two expressions.
+        """
+    @staticmethod
+    @overload
+    def get_add(arg0: int, arg1: AffineExpr) -> AffineAddExpr:
+        """
+        Gets an affine expression containing a sum of a constant and another expression.
+        """
+    @staticmethod
+    @overload
+    def get_add(arg0: AffineExpr, arg1: int) -> AffineAddExpr:
+        """
+        Gets an affine expression containing a sum of an expression and a constant.
+        """
+    @staticmethod
+    @overload
+    def get_ceil_div(arg0: AffineExpr, arg1: AffineExpr) -> AffineCeilDivExpr:
+        """
+        Gets an affine expression containing the rounded-up result of dividing one expression by another.
+        """
+    @staticmethod
+    @overload
+    def get_ceil_div(arg0: int, arg1: AffineExpr) -> AffineCeilDivExpr:
+        """
+        Gets a semi-affine expression containing the rounded-up result of dividing a constant by an expression.
+        """
+    @staticmethod
+    @overload
+    def get_ceil_div(arg0: AffineExpr, arg1: int) -> AffineCeilDivExpr:
+        """
+        Gets an affine expression containing the rounded-up result of dividing an expression by a constant.
+        """
+    @staticmethod
+    def get_constant(
+        value: int, context: Optional[Context] = None
+    ) -> AffineConstantExpr:
+        """
+        Gets a constant affine expression with the given value.
+        """
+    @staticmethod
+    def get_dim(position: int, context: Optional[Context] = None) -> AffineDimExpr:
+        """
+        Gets an affine expression of a dimension at the given position.
+        """
+    @staticmethod
+    @overload
+    def get_floor_div(arg0: AffineExpr, arg1: AffineExpr) -> AffineFloorDivExpr:
+        """
+        Gets an affine expression containing the rounded-down result of dividing one expression by another.
+        """
+    @staticmethod
+    @overload
+    def get_floor_div(arg0: int, arg1: AffineExpr) -> AffineFloorDivExpr:
+        """
+        Gets a semi-affine expression containing the rounded-down result of dividing a constant by an expression.
+        """
+    @staticmethod
+    @overload
+    def get_floor_div(arg0: AffineExpr, arg1: int) -> AffineFloorDivExpr:
+        """
+        Gets an affine expression containing the rounded-down result of dividing an expression by a constant.
+        """
+    @staticmethod
+    @overload
+    def get_mod(arg0: AffineExpr, arg1: AffineExpr) -> AffineModExpr:
+        """
+        Gets an affine expression containing the modulo of dividing one expression by another.
+        """
+    @staticmethod
+    @overload
+    def get_mod(arg0: int, arg1: AffineExpr) -> AffineModExpr:
+        """
+        Gets a semi-affine expression containing the modulo of dividing a constant by an expression.
+        """
+    @staticmethod
+    @overload
+    def get_mod(arg0: AffineExpr, arg1: int) -> AffineModExpr:
+        """
+        Gets an affine expression containing the module of dividingan expression by a constant.
+        """
+    @staticmethod
+    @overload
+    def get_mul(arg0: AffineExpr, arg1: AffineExpr) -> AffineMulExpr:
+        """
+        Gets an affine expression containing a product of two expressions.
+        """
+    @staticmethod
+    @overload
+    def get_mul(arg0: int, arg1: AffineExpr) -> AffineMulExpr:
+        """
+        Gets an affine expression containing a product of a constant and another expression.
+        """
+    @staticmethod
+    @overload
+    def get_mul(arg0: AffineExpr, arg1: int) -> AffineMulExpr:
+        """
+        Gets an affine expression containing a product of an expression and a constant.
+        """
+    @staticmethod
+    def get_symbol(
+        position: int, context: Optional[Context] = None
+    ) -> AffineSymbolExpr:
+        """
+        Gets an affine expression of a symbol at the given position.
+        """
     def _CAPICreate(self) -> AffineExpr: ...
-    def compose(self, arg0) -> AffineExpr: ...
-    def dump(self) -> None: ...
-    def get_add(self, *args, **kwargs) -> Any: ...
-    def get_ceil_div(self, *args, **kwargs) -> Any: ...
-    def get_constant(self, *args, **kwargs) -> Any: ...
-    def get_dim(self, *args, **kwargs) -> Any: ...
-    def get_floor_div(self, *args, **kwargs) -> Any: ...
-    def get_mod(self, *args, **kwargs) -> Any: ...
-    def get_mul(self, *args, **kwargs) -> Any: ...
-    def get_symbol(self, *args, **kwargs) -> Any: ...
-    def __add__(self, other) -> Any: ...
+    @overload
+    def __add__(self, arg0: AffineExpr) -> AffineAddExpr: ...
+    @overload
+    def __add__(self, arg0: int) -> AffineAddExpr: ...
     @overload
     def __eq__(self, arg0: AffineExpr) -> bool: ...
     @overload
-    def __eq__(self, arg0: object) -> bool: ...
+    def __eq__(self, arg0: Any) -> bool: ...
     def __hash__(self) -> int: ...
-    def __mod__(self, other) -> Any: ...
-    def __mul__(self, other) -> Any: ...
-    def __radd__(self, other) -> Any: ...
-    def __rmod__(self, other) -> Any: ...
-    def __rmul__(self, other) -> Any: ...
-    def __rsub__(self, other) -> Any: ...
-    def __sub__(self, other) -> Any: ...
+    @overload
+    def __mod__(self, arg0: AffineExpr) -> AffineModExpr: ...
+    @overload
+    def __mod__(self, arg0: int) -> AffineModExpr: ...
+    @overload
+    def __mul__(self, arg0: AffineExpr) -> AffineMulExpr: ...
+    @overload
+    def __mul__(self, arg0: int) -> AffineMulExpr: ...
+    def __radd__(self, arg0: int) -> AffineAddExpr: ...
+    def __repr__(self) -> str: ...
+    def __rmod__(self, arg0: int) -> AffineModExpr: ...
+    def __rmul__(self, arg0: int) -> AffineMulExpr: ...
+    def __rsub__(self, arg0: int) -> AffineAddExpr: ...
+    def __str__(self) -> str: ...
+    @overload
+    def __sub__(self, arg0: AffineExpr) -> AffineAddExpr: ...
+    @overload
+    def __sub__(self, arg0: int) -> AffineAddExpr: ...
+    def compose(self, arg0: AffineMap) -> AffineExpr: ...
+    def dump(self) -> None:
+        """
+        Dumps a debug representation of the object to stderr.
+        """
     @property
     def _CAPIPtr(self) -> object: ...
     @property
     def context(self) -> Context: ...
 
 class Attribute:
-    def __init__(self, cast_from_type: Attribute) -> None: ...
-    def _CAPICreate(self) -> Attribute: ...
-    def dump(self) -> None: ...
-    def get_named(self, *args, **kwargs) -> Any: ...
     @staticmethod
-    def parse(asm: str, context: Optional[Context] = None) -> Any: ...
+    def parse(asm: str, context: Optional[Context] = None) -> Attribute:
+        """
+        Parses an attribute from an assembly form. Raises an MLIRError on failure.
+        """
+    def _CAPICreate(self) -> Attribute: ...
     @overload
     def __eq__(self, arg0: Attribute) -> bool: ...
     @overload
     def __eq__(self, arg0: object) -> bool: ...
     def __hash__(self) -> int: ...
+    def __init__(self, cast_from_type: Attribute) -> None:
+        """
+        Casts the passed attribute to the generic Attribute
+        """
+    def __repr__(self) -> str: ...
+    def __str__(self) -> str:
+        """
+        Returns the assembly form of the Attribute.
+        """
+    def dump(self) -> None:
+        """
+        Dumps a debug representation of the object to stderr.
+        """
+    def get_named(self, arg0: str) -> NamedAttribute:
+        """
+        Binds a name to the attribute
+        """
+    def maybe_downcast(self) -> Any: ...
     @property
     def _CAPIPtr(self) -> object: ...
     @property
-    def context(self) -> Context: ...
+    def context(self) -> Context:
+        """
+        Context that owns the Attribute
+        """
     @property
     def type(self) -> Type: ...
+    @property
+    def typeid(self) -> TypeID: ...
 
 class Type:
-    def __init__(self, cast_from_type: Type) -> None: ...
-    def _CAPICreate(self) -> Type: ...
-    def dump(self) -> None: ...
     @staticmethod
-    def parse(asm: str, context: Optional[Context] = None) -> Type: ...
+    def parse(asm: str, context: Optional[Context] = None) -> Type:
+        """
+        Parses the assembly form of a type.
+
+        Returns a Type object or raises an MLIRError if the type cannot be parsed.
+
+        See also: https://mlir.llvm.org/docs/LangRef/#type-system
+        """
+    def _CAPICreate(self) -> Type: ...
     @overload
     def __eq__(self, arg0: Type) -> bool: ...
     @overload
     def __eq__(self, arg0: object) -> bool: ...
     def __hash__(self) -> int: ...
+    def __init__(self, cast_from_type: Type) -> None:
+        """
+        Casts the passed type to the generic Type
+        """
+    def __repr__(self) -> str: ...
+    def __str__(self) -> str:
+        """
+        Returns the assembly form of the type.
+        """
+    def dump(self) -> None:
+        """
+        Dumps a debug representation of the object to stderr.
+        """
+    def maybe_downcast(self) -> Any: ...
     @property
     def _CAPIPtr(self) -> object: ...
     @property
-    def context(self) -> Context: ...
+    def context(self) -> Context:
+        """
+        Context that owns the Type
+        """
+    @property
+    def typeid(self) -> TypeID: ...
 
 class Value:
     def _CAPICreate(self) -> Value: ...
-    def dump(self) -> None: ...
     @overload
     def __eq__(self, arg0: Value) -> bool: ...
     @overload
     def __eq__(self, arg0: object) -> bool: ...
     def __hash__(self) -> int: ...
+    def __init__(self, value: Value) -> None: ...
+    def __str__(self) -> str:
+        """
+        Returns the string form of the value.
+
+        If the value is a block argument, this is the assembly form of its type and the
+        position in the argument List. If the value is an operation result, this is
+        equivalent to printing the operation that produced it.
+        """
+    def dump(self) -> None:
+        """
+        Dumps a debug representation of the object to stderr.
+        """
+    @overload
+    def get_name(self, use_local_scope: bool = False) -> str: ...
+    @overload
+    def get_name(self, state: AsmState) -> str:
+        """
+        Returns the string form of value as an operand (i.e., the ValueID).
+        """
+    def maybe_downcast(self) -> Any: ...
+    def replace_all_uses_with(self, arg0: Value) -> None:
+        """
+        Replace all uses of value with the new value, updating anything in
+        the IR that uses 'self' to use the other value instead.
+        """
+    def set_type(self, type: Type) -> None: ...
     @property
     def _CAPIPtr(self) -> object: ...
     @property
-    def context(self) -> Context: ...
+    def context(self) -> Context:
+        """
+        Context in which the value lives.
+        """
     @property
     def owner(self) -> _OperationBase: ...
     @property
     def type(self) -> Type: ...
+    @property
+    def uses(self) -> OpOperandIterator: ...
 
-
-# Classes with no particular order sensitivity in alpha order.
-# TODO: Auto-generated. Audit and fix.
 class AffineAddExpr(AffineBinaryExpr):
-    def __init__(self, expr: AffineExpr) -> None: ...
     @staticmethod
-    def get(*args, **kwargs) -> AffineAddExpr: ...
+    def get(arg0: AffineExpr, arg1: AffineExpr) -> AffineAddExpr: ...
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: AffineExpr) -> bool: ...
+    def __init__(self, expr: AffineExpr) -> None: ...
 
-# TODO: Auto-generated. Audit and fix.
 class AffineBinaryExpr(AffineExpr):
-    def __init__(self, expr: AffineExpr) -> None: ...
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: AffineExpr) -> bool: ...
+    def __init__(self, expr: AffineExpr) -> None: ...
     @property
     def lhs(self) -> AffineExpr: ...
     @property
     def rhs(self) -> AffineExpr: ...
 
-# TODO: Auto-generated. Audit and fix.
 class AffineCeilDivExpr(AffineBinaryExpr):
-    def __init__(self, expr: AffineExpr) -> None: ...
     @staticmethod
-    def get(*args, **kwargs) -> AffineCeilDivExpr: ...
+    def get(arg0: AffineExpr, arg1: AffineExpr) -> AffineCeilDivExpr: ...
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: AffineExpr) -> bool: ...
+    def __init__(self, expr: AffineExpr) -> None: ...
 
-# TODO: Auto-generated. Audit and fix.
 class AffineConstantExpr(AffineExpr):
-    def __init__(self, expr: AffineExpr) -> None: ...
     @staticmethod
-    def get(*args, **kwargs) -> AffineConstantExpr: ...
+    def get(value: int, context: Optional[Context] = None) -> AffineConstantExpr: ...
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: AffineExpr) -> bool: ...
+    def __init__(self, expr: AffineExpr) -> None: ...
     @property
     def value(self) -> int: ...
 
-# TODO: Auto-generated. Audit and fix.
 class AffineDimExpr(AffineExpr):
-    def __init__(self, expr: AffineExpr) -> None: ...
     @staticmethod
-    def get(*args, **kwargs) -> AffineDimExpr: ...
+    def get(position: int, context: Optional[Context] = None) -> AffineDimExpr: ...
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: AffineExpr) -> bool: ...
+    def __init__(self, expr: AffineExpr) -> None: ...
     @property
     def position(self) -> int: ...
 
-# TODO: Auto-generated. Audit and fix.
 class AffineExprList:
-    def __init__(self, *args, **kwargs) -> None: ...
     def __add__(self, arg0: AffineExprList) -> List[AffineExpr]: ...
-    @overload
-    def __getitem__(self, arg0: int) -> AffineExpr: ...
-    @overload
-    def __getitem__(self, arg0: slice) -> AffineExprList: ...
-    def __len__(self) -> int: ...
 
-# TODO: Auto-generated. Audit and fix.
 class AffineFloorDivExpr(AffineBinaryExpr):
-    def __init__(self, expr: AffineExpr) -> None: ...
-    def get(*args, **kwargs) -> AffineFloorDivExpr: ...
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def get(arg0: AffineExpr, arg1: AffineExpr) -> AffineFloorDivExpr: ...
+    @staticmethod
+    def isinstance(other: AffineExpr) -> bool: ...
+    def __init__(self, expr: AffineExpr) -> None: ...
 
-# TODO: Auto-generated. Audit and fix.
 class AffineMap:
-    def __init__(self, *args, **kwargs) -> None: ...
-    def _CAPICreate(self) -> AffineMap: ...
-    @staticmethod
-    def compress_unused_symbols(*args, **kwargs) -> Any: ...
-    def dump(self) -> None: ...
-    @staticmethod
-    def get(*args, **kwargs) -> AffineMap: ...
     @staticmethod
-    def get_constant(*args, **kwargs) -> AffineMap: ...
-    @staticmethod
-    def get_empty(*args, **kwargs) -> AffineMap: ...
-    @staticmethod
-    def get_identity(*args, **kwargs) -> AffineMap: ...
-    @staticmethod
-    def get_minor_identity(*args, **kwargs) -> AffineMap: ...
-    def get_minor_submap(self, n_results: int) -> AffineMap: ...
-    def get_major_submap(self, n_results: int) -> AffineMap: ...
-    def get_permutation(self, *args, **kwargs) -> Any: ...
-    def get_submap(self, result_positions: List[int]) -> AffineMap: ...
-    def replace(self, expr: AffineExpr, replacement: AffineExpr, n_result_dims: int, n_result_syms: int) -> AffineMap: ...
+    def compress_unused_symbols(
+        arg0: List, arg1: Optional[Context]
+    ) -> List[AffineMap]: ...
+    @staticmethod
+    def get(
+        dim_count: int,
+        symbol_count: int,
+        exprs: List,
+        context: Optional[Context] = None,
+    ) -> AffineMap:
+        """
+        Gets a map with the given expressions as results.
+        """
+    @staticmethod
+    def get_constant(value: int, context: Optional[Context] = None) -> AffineMap:
+        """
+        Gets an affine map with a single constant result
+        """
+    @staticmethod
+    def get_empty(context: Optional[Context] = None) -> AffineMap:
+        """
+        Gets an empty affine map.
+        """
+    @staticmethod
+    def get_identity(n_dims: int, context: Optional[Context] = None) -> AffineMap:
+        """
+        Gets an identity map with the given number of dimensions.
+        """
+    @staticmethod
+    def get_minor_identity(
+        n_dims: int, n_results: int, context: Optional[Context] = None
+    ) -> AffineMap:
+        """
+        Gets a minor identity map with the given number of dimensions and results.
+        """
+    @staticmethod
+    def get_permutation(
+        permutation: List[int], context: Optional[Context] = None
+    ) -> AffineMap:
+        """
+        Gets an affine map that permutes its inputs.
+        """
+    def _CAPICreate(self) -> AffineMap: ...
     @overload
     def __eq__(self, arg0: AffineMap) -> bool: ...
     @overload
     def __eq__(self, arg0: object) -> bool: ...
     def __hash__(self) -> int: ...
+    def __repr__(self) -> str: ...
+    def __str__(self) -> str: ...
+    def dump(self) -> None:
+        """
+        Dumps a debug representation of the object to stderr.
+        """
+    def get_major_submap(self, n_results: int) -> AffineMap: ...
+    def get_minor_submap(self, n_results: int) -> AffineMap: ...
+    def get_submap(self, result_positions: List[int]) -> AffineMap: ...
+    def replace(
+        self,
+        expr: AffineExpr,
+        replacement: AffineExpr,
+        n_result_dims: int,
+        n_result_syms: int,
+    ) -> AffineMap: ...
     @property
     def _CAPIPtr(self) -> object: ...
     @property
-    def context(self) -> Context: ...
+    def context(self) -> Context:
+        """
+        Context that owns the Affine Map
+        """
     @property
     def is_permutation(self) -> bool: ...
     @property
@@ -335,460 +744,1119 @@ class AffineMap:
     @property
     def n_symbols(self) -> int: ...
     @property
-    def results(self) -> Any: ...
+    def results(self) -> "AffineMapExprList": ...
 
-# TODO: Auto-generated. Audit and fix.
 class AffineMapAttr(Attribute):
-    def __init__(self, cast_from_attr: Attribute) -> None: ...
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
     @staticmethod
-    def get(*args, **kwargs) -> AffineMapAttr: ...
+    def get(affine_map: AffineMap) -> AffineMapAttr:
+        """
+        Gets an attribute wrapping an AffineMap.
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: Attribute) -> bool: ...
+    def __init__(self, cast_from_attr: Attribute) -> None: ...
+    def __repr__(self) -> str: ...
     @property
     def type(self) -> Type: ...
+    @property
+    def typeid(self) -> TypeID: ...
 
-# TODO: Auto-generated. Audit and fix.
 class AffineModExpr(AffineBinaryExpr):
-    def __init__(self, expr: AffineExpr) -> None: ...
     @staticmethod
-    def get(*args, **kwargs) -> AffineModExpr: ...
+    def get(arg0: AffineExpr, arg1: AffineExpr) -> AffineModExpr: ...
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: AffineExpr) -> bool: ...
+    def __init__(self, expr: AffineExpr) -> None: ...
 
-# TODO: Auto-generated. Audit and fix.
 class AffineMulExpr(AffineBinaryExpr):
-    def __init__(self, expr: AffineExpr) -> None: ...
     @staticmethod
-    def get(*args, **kwargs) -> AffineMulExpr: ...
+    def get(arg0: AffineExpr, arg1: AffineExpr) -> AffineMulExpr: ...
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: AffineExpr) -> bool: ...
+    def __init__(self, expr: AffineExpr) -> None: ...
 
-# TODO: Auto-generated. Audit and fix.
 class AffineSymbolExpr(AffineExpr):
-    def __init__(self, expr: AffineExpr) -> None: ...
     @staticmethod
-    def get(*args, **kwargs) -> AffineSymbolExpr: ...
+    def get(position: int, context: Optional[Context] = None) -> AffineSymbolExpr: ...
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: AffineExpr) -> bool: ...
+    def __init__(self, expr: AffineExpr) -> None: ...
     @property
     def position(self) -> int: ...
 
-# TODO: Auto-generated. Audit and fix.
 class ArrayAttr(Attribute):
-    def __init__(self, cast_from_attr: Attribute) -> None: ...
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
     @staticmethod
-    def get(*args, **kwargs) -> ArrayAttr: ...
+    def get(attributes: List, context: Optional[Context] = None) -> ArrayAttr:
+        """
+        Gets a uniqued Array attribute
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
-    def __add__(self, arg0: list) -> ArrayAttr: ...
+    def isinstance(other: Attribute) -> bool: ...
+    def __add__(self, arg0: List) -> ArrayAttr: ...
     def __getitem__(self, arg0: int) -> Attribute: ...
-    def __iter__(self) -> Any: ...
+    def __init__(self, cast_from_attr: Attribute) -> None: ...
+    def __iter__(
+        self,
+    ) -> ArrayAttributeIterator: ...
     def __len__(self) -> int: ...
+    def __repr__(self) -> str: ...
     @property
     def type(self) -> Type: ...
+    @property
+    def typeid(self) -> TypeID: ...
 
-# TODO: Auto-generated. Audit and fix.
 class ArrayAttributeIterator:
-    def __init__(self, *args, **kwargs) -> None: ...
     def __iter__(self) -> ArrayAttributeIterator: ...
     def __next__(self) -> Attribute: ...
 
-# TODO: Auto-generated. Audit and fix.
+class AsmState:
+    @overload
+    def __init__(self, value: Value, use_local_scope: bool = False) -> None: ...
+    @overload
+    def __init__(self, op: _OperationBase, use_local_scope: bool = False) -> None: ...
+
+class AttrBuilder:
+    @staticmethod
+    def contains(arg0: str) -> bool: ...
+    @staticmethod
+    def get(arg0: str) -> Callable: ...
+    @staticmethod
+    def insert(
+        attribute_kind: str, attr_builder: Callable, replace: bool = False
+    ) -> None:
+        """
+        Register an attribute builder for building MLIR attributes from python values.
+        """
+
 class BF16Type(Type):
-    def __init__(self, cast_from_type: Type) -> None: ...
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
     @staticmethod
-    def get(*args, **kwargs) -> BF16Type: ...
+    def get(context: Optional[Context] = None) -> BF16Type:
+        """
+        Create a bf16 type.
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: Type) -> bool: ...
+    def __init__(self, cast_from_type: Type) -> None: ...
+    def __repr__(self) -> str: ...
+    @property
+    def typeid(self) -> TypeID: ...
 
 class Block:
-    __hash__: ClassVar[None] = ...  # type: ignore
-    def append(self, operation: _OperationBase) -> None: ...
-    def create_after(self, *args: Type) -> Block: ...
     @staticmethod
-    def create_at_start(parent: Region, arg_types: List[Type]) -> Block: ...
-    def create_before(self, *args: Type) -> Block: ...
+    def create_at_start(
+        parent: Region,
+        arg_types: List[Type],
+        arg_locs: Optional[Sequence] = None,
+    ) -> Block:
+        """
+        Creates and returns a new Block at the beginning of the given region (with given argument types and locations).
+        """
     @overload
     def __eq__(self, arg0: Block) -> bool: ...
     @overload
-    def __eq__(self, arg0: object) -> bool: ...
-    def __iter__(self) -> Any: ...
+    def __eq__(self, arg0: Any) -> bool: ...
+    def __hash__(self) -> int: ...
+    def __iter__(self) -> OperationIterator:
+        """
+        Iterates over operations in the block.
+        """
+    def __str__(self) -> str:
+        """
+        Returns the assembly form of the block.
+        """
+    def append(self, operation: _OperationBase) -> None:
+        """
+        Appends an operation to this block. If the operation is currently in another block, it will be moved.
+        """
+    def append_to(self, arg0: Region) -> None:
+        """
+        Append this block to a region, transferring ownership if necessary
+        """
+    def create_after(self, *args, arg_locs: Optional[Sequence] = None) -> Block:
+        """
+        Creates and returns a new Block after this block (with given argument types and locations).
+        """
+    def create_before(self, *args, arg_locs: Optional[Sequence] = None) -> Block:
+        """
+        Creates and returns a new Block before this block (with given argument types and locations).
+        """
+    @property
+    def _CAPIPtr(self) -> object: ...
     @property
-    def arguments(self) -> BlockArgumentList: ...
+    def arguments(self) -> BlockArgumentList:
+        """
+        Returns a List of block arguments.
+        """
     @property
-    def operations(self) -> OperationList: ...
+    def operations(self) -> OperationList:
+        """
+        Returns a forward-optimized sequence of operations.
+        """
     @property
-    def owner(self) -> OpView: ...
+    def owner(self) -> OpView:
+        """
+        Returns the owning operation of this block.
+        """
     @property
-    def region(self) -> Region: ...
+    def region(self) -> Region:
+        """
+        Returns the owning region of this block.
+        """
 
 class BlockArgument(Value):
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other_value: Value) -> bool: ...
+    def __init__(self, value: Value) -> None: ...
+    def maybe_downcast(self) -> Any: ...
     def set_type(self, type: Type) -> None: ...
     @property
     def arg_number(self) -> int: ...
     @property
-    def owner(self) -> Block: ...  # type: ignore[override]
+    def owner(self) -> Block: ...
 
 class BlockArgumentList:
     def __add__(self, arg0: BlockArgumentList) -> List[BlockArgument]: ...
-    @overload
-    def __getitem__(self, arg0: int) -> BlockArgument: ...
-    @overload
-    def __getitem__(self, arg0: slice) -> BlockArgumentList: ...
-    def __len__(self) -> int: ...
     @property
     def types(self) -> List[Type]: ...
 
 class BlockIterator:
-    def __init__(self, *args, **kwargs) -> None: ...
     def __iter__(self) -> BlockIterator: ...
     def __next__(self) -> Block: ...
 
 class BlockList:
-    def append(self, *args) -> Block: ...
     def __getitem__(self, arg0: int) -> Block: ...
     def __iter__(self) -> BlockIterator: ...
     def __len__(self) -> int: ...
+    def append(self, *args, arg_locs: Optional[Sequence] = None) -> Block:
+        """
+        Appends a new block, with argument types as positional args.
+
+        Returns:
+          The created block.
+        """
 
-# TODO: Auto-generated. Audit and fix.
 class BoolAttr(Attribute):
-    def __init__(self, cast_from_attr: Attribute) -> None: ...
     @staticmethod
-    def get(*args, **kwargs) -> BoolAttr: ...
+    def get(value: bool, context: Optional[Context] = None) -> BoolAttr:
+        """
+        Gets an uniqued bool attribute
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: Attribute) -> bool: ...
+    def __bool__(self: Attribute) -> bool:
+        """
+        Converts the value of the bool attribute to a Python bool
+        """
+    def __init__(self, cast_from_attr: Attribute) -> None: ...
+    def __repr__(self) -> str: ...
+    @property
+    def static_typeid(self) -> TypeID: ...
     @property
     def type(self) -> Type: ...
     @property
-    def value(self) -> bool: ...
+    def typeid(self) -> TypeID: ...
+    @property
+    def value(self) -> bool:
+        """
+        Returns the value of the bool attribute
+        """
 
-# TODO: Auto-generated. Audit and fix.
 class ComplexType(Type):
-    def __init__(self, cast_from_type: Type) -> None: ...
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
     @staticmethod
-    def get(*args, **kwargs) -> ComplexType: ...
+    def get(arg0: Type) -> ComplexType:
+        """
+        Create a complex type
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: Type) -> bool: ...
+    def __init__(self, cast_from_type: Type) -> None: ...
+    def __repr__(self) -> str: ...
+    @property
+    def element_type(self) -> Type:
+        """
+        Returns element type.
+        """
     @property
-    def element_type(self) -> Type: ...
+    def typeid(self) -> TypeID: ...
 
 class Context:
     current: ClassVar[Context] = ...  # read-only
     allow_unregistered_dialects: bool
-    def __init__(self) -> None: ...
-    def _CAPICreate(self) -> object: ...
-    def _get_context_again(self) -> Context: ...
     @staticmethod
     def _get_live_count() -> int: ...
+    def _CAPICreate(self) -> object: ...
+    def __enter__(self) -> Any: ...
+    def __exit__(self, arg0: Any, arg1: Any, arg2: Any) -> None: ...
+    def __init__(self) -> None: ...
+    def _clear_live_operations(self) -> int: ...
+    def _get_context_again(self) -> Context: ...
     def _get_live_module_count(self) -> int: ...
     def _get_live_operation_count(self) -> int: ...
-    def attach_diagnostic_handler(self, callback: Callable[[Diagnostic], bool]) -> DiagnosticHandler: ...
+    def append_dialect_registry(self, registry: DialectRegistry) -> None: ...
+    def attach_diagnostic_handler(
+        self, callback: Callable[[Diagnostic], bool]
+    ) -> DiagnosticHandler:
+        """
+        Attaches a diagnostic handler that will receive callbacks
+        """
     def enable_multithreading(self, enable: bool) -> None: ...
-    def get_dialect_descriptor(self, dialect_name: str) -> DialectDescriptor: ...
+    def get_dialect_descriptor(self, dialect_name: str) -> DialectDescriptor:
+        """
+        Gets or loads a dialect by name, returning its descriptor object
+        """
     def is_registered_operation(self, operation_name: str) -> bool: ...
-    def __enter__(self) -> Context: ...
-    def __exit__(self, arg0: object, arg1: object, arg2: object) -> None: ...
+    def load_all_available_dialects(self) -> None: ...
     @property
     def _CAPIPtr(self) -> object: ...
     @property
-    def d(self) -> Dialects: ...
+    def d(self) -> Dialects:
+        """
+        Alias for 'dialect'
+        """
     @property
-    def dialects(self) -> Dialects: ...
-    def append_dialect_registry(self, registry: "DialectRegistry") -> None: ...
-    def load_all_available_dialects(self) -> None: ...
-
-class DialectRegistry:
-    def __init__(self) -> None: ...
+    def dialects(self) -> Dialects:
+        """
+        Gets a container for accessing dialects by name
+        """
 
-# TODO: Auto-generated. Audit and fix.
-class DenseElementsAttr(Attribute):
-    def __init__(self, cast_from_attr: Attribute) -> None: ...
+class DenseBoolArrayAttr(Attribute):
     @staticmethod
-    def get(*args, **kwargs) -> DenseElementsAttr: ...
+    def get(
+        values: List[bool], context: Optional[Context] = None
+    ) -> DenseBoolArrayAttr:
+        """
+        Gets a uniqued dense array attribute
+        """
     @staticmethod
-    def get_splat(*args, **kwargs) -> Any: ...
+    def isinstance(other: Attribute) -> bool: ...
+    def __add__(self, arg0: List) -> DenseBoolArrayAttr: ...
+    def __getitem__(self, arg0: int) -> bool: ...
+    def __init__(self, cast_from_attr: Attribute) -> None: ...
+    def __iter__(
+        self,
+    ) -> DenseBoolArrayIterator: ...
+    def __len__(self) -> int: ...
+    def __repr__(self) -> str: ...
+    @property
+    def static_typeid(self) -> TypeID: ...
+    @property
+    def type(self) -> Type: ...
+    @property
+    def typeid(self) -> TypeID: ...
+
+class DenseBoolArrayIterator:
+    def __iter__(self) -> DenseBoolArrayIterator: ...
+    def __next__(self) -> bool: ...
+
+class DenseElementsAttr(Attribute):
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def get(
+        array: Buffer,
+        signless: bool = True,
+        type: Optional[Type] = None,
+        shape: Optional[List[int]] = None,
+        context: Optional[Context] = None,
+    ) -> DenseElementsAttr:
+        """
+        Gets a DenseElementsAttr from a Python buffer or array.
+
+        When `type` is not provided, then some limited type inferencing is done based
+        on the buffer format. Support presently exists for 8/16/32/64 signed and
+        unsigned integers and float16/float32/float64. DenseElementsAttrs of these
+        types can also be converted back to a corresponding buffer.
+
+        For conversions outside of these types, a `type=` must be explicitly provided
+        and the buffer contents must be bit-castable to the MLIR internal
+        representation:
+
+          * Integer types (except for i1): the buffer must be byte aligned to the
+            next byte boundary.
+          * Floating point types: Must be bit-castable to the given floating point
+            size.
+          * i1 (bool): Bit packed into 8bit words where the bit pattern matches a
+            row major ordering. An arbitrary Numpy `bool_` array can be bit packed to
+            this specification with: `np.packbits(ary, axis=None, bitorder='little')`.
+
+        If a single element buffer is passed (or for i1, a single byte with value 0
+        or 255), then a splat will be created.
+
+        Args:
+          array: The array or buffer to convert.
+          signless: If inferring an appropriate MLIR type, use signless types for
+            integers (defaults True).
+          type: Skips inference of the MLIR element type and uses this instead. The
+            storage size must be consistent with the actual contents of the buffer.
+          shape: Overrides the shape of the buffer when constructing the MLIR
+            shaped type. This is needed when the physical and logical shape differ (as
+            for i1).
+          context: Explicit context, if not from context manager.
+
+        Returns:
+          DenseElementsAttr on success.
+
+        Raises:
+          ValueError: If the type of the buffer or array cannot be matched to an MLIR
+            type or if the buffer does not meet expectations.
+        """
+    @staticmethod
+    def get_splat(shaped_type: Type, element_attr: Attribute) -> DenseElementsAttr:
+        """
+        Gets a DenseElementsAttr where all values are the same
+        """
+    @staticmethod
+    def isinstance(other: Attribute) -> bool: ...
+    def __init__(self, cast_from_attr: Attribute) -> None: ...
     def __len__(self) -> int: ...
+    def __repr__(self) -> str: ...
+    def get_splat_value(self) -> Attribute: ...
     @property
     def is_splat(self) -> bool: ...
     @property
+    def static_typeid(self) -> TypeID: ...
+    @property
     def type(self) -> Type: ...
+    @property
+    def typeid(self) -> TypeID: ...
 
-# TODO: Auto-generated. Audit and fix.
-class DenseFPElementsAttr(DenseElementsAttr):
-    def __init__(self, cast_from_attr: Attribute) -> None: ...
+class DenseF32ArrayAttr(Attribute):
     @staticmethod
-    def get(*args, **kwargs) -> DenseFPElementsAttr: ...
+    def get(
+        values: List[float], context: Optional[Context] = None
+    ) -> DenseF32ArrayAttr:
+        """
+        Gets a uniqued dense array attribute
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: Attribute) -> bool: ...
+    def __add__(self, arg0: List) -> DenseF32ArrayAttr: ...
     def __getitem__(self, arg0: int) -> float: ...
+    def __init__(self, cast_from_attr: Attribute) -> None: ...
+    def __iter__(
+        self,
+    ) -> DenseF32ArrayIterator: ...
+    def __len__(self) -> int: ...
+    def __repr__(self) -> str: ...
+    @property
+    def static_typeid(self) -> TypeID: ...
     @property
     def type(self) -> Type: ...
+    @property
+    def typeid(self) -> TypeID: ...
 
-# TODO: Auto-generated. Audit and fix.
-class DenseIntElementsAttr(DenseElementsAttr):
-    def __init__(self, cast_from_attr: Attribute) -> None: ...
+class DenseF32ArrayIterator:
+    def __iter__(self) -> DenseF32ArrayIterator: ...
+    def __next__(self) -> float: ...
+
+class DenseF64ArrayAttr(Attribute):
     @staticmethod
-    def get(*args, **kwargs) -> DenseIntElementsAttr: ...
+    def get(
+        values: List[float], context: Optional[Context] = None
+    ) -> DenseF64ArrayAttr:
+        """
+        Gets a uniqued dense array attribute
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
-    def __getitem__(self, arg0: int) -> int: ...
+    def isinstance(other: Attribute) -> bool: ...
+    def __add__(self, arg0: List) -> DenseF64ArrayAttr: ...
+    def __getitem__(self, arg0: int) -> float: ...
+    def __init__(self, cast_from_attr: Attribute) -> None: ...
+    def __iter__(
+        self,
+    ) -> DenseF64ArrayIterator: ...
+    def __len__(self) -> int: ...
+    def __repr__(self) -> str: ...
+    @property
+    def static_typeid(self) -> TypeID: ...
     @property
     def type(self) -> Type: ...
+    @property
+    def typeid(self) -> TypeID: ...
 
-class DenseResourceElementsAttr(Attribute):
-    @staticmethod
-    def get_from_buffer(array: Any, name: str, type: Type, alignment: Optional[int] = None, is_mutable: bool = False, context: Optional[Context] = None) -> None: ...
+class DenseF64ArrayIterator:
+    def __iter__(self) -> DenseF64ArrayIterator: ...
+    def __next__(self) -> float: ...
 
-class Dialect:
-    def __init__(self, descriptor: DialectDescriptor) -> None: ...
+class DenseFPElementsAttr(DenseElementsAttr):
+    @staticmethod
+    def isinstance(other: Attribute) -> bool: ...
+    def __getitem__(self, arg0: int) -> float: ...
+    def __init__(self, cast_from_attr: Attribute) -> None: ...
+    def __repr__(self) -> str: ...
     @property
-    def descriptor(self) -> DialectDescriptor: ...
+    def static_typeid(self) -> TypeID: ...
+    @property
+    def type(self) -> Type: ...
+    @property
+    def typeid(self) -> TypeID: ...
 
-class DialectDescriptor:
+class DenseI16ArrayAttr(Attribute):
+    @staticmethod
+    def get(values: List[int], context: Optional[Context] = None) -> DenseI16ArrayAttr:
+        """
+        Gets a uniqued dense array attribute
+        """
+    @staticmethod
+    def isinstance(other: Attribute) -> bool: ...
+    def __add__(self, arg0: List) -> DenseI16ArrayAttr: ...
+    def __getitem__(self, arg0: int) -> int: ...
+    def __init__(self, cast_from_attr: Attribute) -> None: ...
+    def __iter__(
+        self,
+    ) -> DenseI16ArrayIterator: ...
+    def __len__(self) -> int: ...
+    def __repr__(self) -> str: ...
     @property
-    def namespace(self) -> str: ...
+    def static_typeid(self) -> TypeID: ...
+    @property
+    def type(self) -> Type: ...
+    @property
+    def typeid(self) -> TypeID: ...
 
-class Dialects:
-    def __init__(self, *args, **kwargs) -> None: ...
-    def __getattr__(self, arg0: str) -> Dialect: ...
-    def __getitem__(self, arg0: str) -> Dialect: ...
+class DenseI16ArrayIterator:
+    def __iter__(self) -> DenseI16ArrayIterator: ...
+    def __next__(self) -> int: ...
 
-class Diagnostic:
-    @property
-    def severity(self) -> DiagnosticSeverity: ...
+class DenseI32ArrayAttr(Attribute):
+    @staticmethod
+    def get(values: List[int], context: Optional[Context] = None) -> DenseI32ArrayAttr:
+        """
+        Gets a uniqued dense array attribute
+        """
+    @staticmethod
+    def isinstance(other: Attribute) -> bool: ...
+    def __add__(self, arg0: List) -> DenseI32ArrayAttr: ...
+    def __getitem__(self, arg0: int) -> int: ...
+    def __init__(self, cast_from_attr: Attribute) -> None: ...
+    def __iter__(
+        self,
+    ) -> DenseI32ArrayIterator: ...
+    def __len__(self) -> int: ...
+    def __repr__(self) -> str: ...
     @property
-    def location(self) -> Location: ...
+    def static_typeid(self) -> TypeID: ...
     @property
-    def message(self) -> str: ...
+    def type(self) -> Type: ...
     @property
-    def notes(self) -> Tuple[Diagnostic]: ...
+    def typeid(self) -> TypeID: ...
+
+class DenseI32ArrayIterator:
+    def __iter__(self) -> DenseI32ArrayIterator: ...
+    def __next__(self) -> int: ...
+
+class DenseI64ArrayAttr(Attribute):
+    @staticmethod
+    def get(values: List[int], context: Optional[Context] = None) -> DenseI64ArrayAttr:
+        """
+        Gets a uniqued dense array attribute
+        """
+    @staticmethod
+    def isinstance(other: Attribute) -> bool: ...
+    def __add__(self, arg0: List) -> DenseI64ArrayAttr: ...
+    def __getitem__(self, arg0: int) -> int: ...
+    def __init__(self, cast_from_attr: Attribute) -> None: ...
+    def __iter__(
+        self,
+    ) -> DenseI16ArrayIterator: ...
+    def __len__(self) -> int: ...
+    def __repr__(self) -> str: ...
+    @property
+    def static_typeid(self) -> TypeID: ...
+    @property
+    def type(self) -> Type: ...
+    @property
+    def typeid(self) -> TypeID: ...
+
+class DenseI64ArrayIterator:
+    def __iter__(self) -> DenseI64ArrayIterator: ...
+    def __next__(self) -> int: ...
+
+class DenseI8ArrayAttr(Attribute):
+    @staticmethod
+    def get(values: List[int], context: Optional[Context] = None) -> DenseI8ArrayAttr:
+        """
+        Gets a uniqued dense array attribute
+        """
+    @staticmethod
+    def isinstance(other: Attribute) -> bool: ...
+    def __add__(self, arg0: List) -> DenseI8ArrayAttr: ...
+    def __getitem__(self, arg0: int) -> int: ...
+    def __init__(self, cast_from_attr: Attribute) -> None: ...
+    def __iter__(
+        self,
+    ) -> DenseI8ArrayIterator: ...
+    def __len__(self) -> int: ...
+    def __repr__(self) -> str: ...
+    @property
+    def static_typeid(self) -> TypeID: ...
+    @property
+    def type(self) -> Type: ...
+    @property
+    def typeid(self) -> TypeID: ...
+
+class DenseI8ArrayIterator:
+    def __iter__(self) -> DenseI8ArrayIterator: ...
+    def __next__(self) -> int: ...
+
+class DenseIntElementsAttr(DenseElementsAttr):
+    @staticmethod
+    def isinstance(other: Attribute) -> bool: ...
+    def __getitem__(self, arg0: int) -> int: ...
+    def __init__(self, cast_from_attr: Attribute) -> None: ...
+    def __repr__(self) -> str: ...
+    @property
+    def static_typeid(self) -> TypeID: ...
+    @property
+    def type(self) -> Type: ...
+    @property
+    def typeid(self) -> TypeID: ...
+
+class DenseResourceElementsAttr(Attribute):
+    @staticmethod
+    def get_from_buffer(
+        array: Buffer,
+        name: str,
+        type: Type,
+        alignment: Optional[int] = None,
+        is_mutable: bool = False,
+        context: Optional[Context] = None,
+    ) -> DenseResourceElementsAttr:
+        """
+        Gets a DenseResourceElementsAttr from a Python buffer or array.
+
+        This function does minimal validation or massaging of the data, and it is
+        up to the caller to ensure that the buffer meets the characteristics
+        implied by the shape.
+
+        The backing buffer and any user objects will be retained for the lifetime
+        of the resource blob. This is typically bounded to the context but the
+        resource can have a shorter lifespan depending on how it is used in
+        subsequent processing.
+
+        Args:
+          buffer: The array or buffer to convert.
+          name: Name to provide to the resource (may be changed upon collision).
+          type: The explicit ShapedType to construct the attribute with.
+          context: Explicit context, if not from context manager.
+
+        Returns:
+          DenseResourceElementsAttr on success.
+
+        Raises:
+          ValueError: If the type of the buffer or array cannot be matched to an MLIR
+            type or if the buffer does not meet expectations.
+        """
+    @staticmethod
+    def isinstance(other: Attribute) -> bool: ...
+    def __init__(self, cast_from_attr: Attribute) -> None: ...
+    def __repr__(self) -> str: ...
+    @property
+    def static_typeid(self) -> TypeID: ...
+    @property
+    def type(self) -> Type: ...
+    @property
+    def typeid(self) -> TypeID: ...
+
+class Diagnostic:
+    def __str__(self) -> str: ...
+    @property
+    def location(self) -> Location: ...
+    @property
+    def message(self) -> str: ...
+    @property
+    def notes(self) -> Tuple[Diagnostic]: ...
+    @property
+    def severity(self) -> DiagnosticSeverity: ...
 
 class DiagnosticHandler:
+    def __enter__(self) -> DiagnosticHandler: ...
+    def __exit__(self, arg0: object, arg1: object, arg2: object) -> None: ...
     def detach(self) -> None: ...
     @property
     def attached(self) -> bool: ...
     @property
     def had_error(self) -> bool: ...
-    def __enter__(self) -> DiagnosticHandler: ...
-    def __exit__(self, arg0: object, arg1: object, arg2: object) -> None: ...
 
 class DiagnosticInfo:
-    def __init__(self, diag: Diagnostic) -> None: ...
-    @property
-    def severity(self) -> "DiagnosticSeverity": ...
+    def __init__(self, arg0: Diagnostic) -> None: ...
+    def __str__(self) -> str: ...
     @property
-    def location(self) -> "Location": ...
+    def location(self) -> Location: ...
     @property
     def message(self) -> str: ...
     @property
-    def notes(self) -> Sequence["DiagnosticInfo"]: ...
+    def notes(self) -> List[DiagnosticInfo]: ...
+    @property
+    def severity(self) -> DiagnosticSeverity: ...
 
 class DiagnosticSeverity:
-    ERROR: DiagnosticSeverity
-    WARNING: DiagnosticSeverity
-    NOTE: DiagnosticSeverity
-    REMARK: DiagnosticSeverity
+    """
+    Members:
+
+      ERROR
+
+      WARNING
+
+      NOTE
+
+      REMARK
+    """
+
+    ERROR: ClassVar[DiagnosticSeverity]  # value = <DiagnosticSeverity.ERROR: 0>
+    NOTE: ClassVar[DiagnosticSeverity]  # value = <DiagnosticSeverity.NOTE: 2>
+    REMARK: ClassVar[DiagnosticSeverity]  # value = <DiagnosticSeverity.REMARK: 3>
+    WARNING: ClassVar[DiagnosticSeverity]  # value = <DiagnosticSeverity.WARNING: 1>
+    __members__: ClassVar[
+        Dict[str, DiagnosticSeverity]
+    ]  # value = {'ERROR': <DiagnosticSeverity.ERROR: 0>, 'WARNING': <DiagnosticSeverity.WARNING: 1>, 'NOTE': <DiagnosticSeverity.NOTE: 2>, 'REMARK': <DiagnosticSeverity.REMARK: 3>}
+    def __eq__(self, other: Any) -> bool: ...
+    def __getstate__(self) -> int: ...
+    def __hash__(self) -> int: ...
+    def __index__(self) -> int: ...
+    def __init__(self, value: int) -> None: ...
+    def __int__(self) -> int: ...
+    def __ne__(self, other: Any) -> bool: ...
+    def __repr__(self) -> str: ...
+    def __setstate__(self, state: int) -> None: ...
+    def __str__(self) -> str: ...
+    @property
+    def name(self) -> str: ...
+    @property
+    def value(self) -> int: ...
+
+class Dialect:
+    def __init__(self, descriptor: DialectDescriptor) -> None: ...
+    def __repr__(self) -> Any: ...
+    @property
+    def descriptor(self) -> DialectDescriptor: ...
+
+class DialectDescriptor:
+    def __repr__(self) -> str: ...
+    @property
+    def namespace(self) -> str: ...
+
+class DialectRegistry:
+    def _CAPICreate(self) -> DialectRegistry: ...
+    def __init__(self) -> None: ...
+    @property
+    def _CAPIPtr(self) -> object: ...
+
+class Dialects:
+    def __getattr__(self, arg0: str) -> Any: ...
+    def __getitem__(self, arg0: str) -> Any: ...
 
-# TODO: Auto-generated. Audit and fix.
 class DictAttr(Attribute):
-    def __init__(self, cast_from_attr: Attribute) -> None: ...
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
     @staticmethod
-    def get(*args, **kwargs) -> DictAttr: ...
+    def get(value: Dict = {}, context: Optional[Context] = None) -> DictAttr:
+        """
+        Gets an uniqued Dict attribute
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: Attribute) -> bool: ...
     def __contains__(self, arg0: str) -> bool: ...
     @overload
     def __getitem__(self, arg0: str) -> Attribute: ...
     @overload
     def __getitem__(self, arg0: int) -> NamedAttribute: ...
+    def __init__(self, cast_from_attr: Attribute) -> None: ...
     def __len__(self) -> int: ...
+    def __repr__(self) -> str: ...
     @property
     def type(self) -> Type: ...
+    @property
+    def typeid(self) -> TypeID: ...
 
-class Float8E4M3FNType(Type):
-    def __init__(self, cast_from_type: Type) -> None: ...
+class F16Type(Type):
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
     @staticmethod
-    def get(*args, **kwargs) -> Float8E4M3FNType: ...
+    def get(context: Optional[Context] = None) -> F16Type:
+        """
+        Create a f16 type.
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
-
-class Float8E5M2Type(Type):
+    def isinstance(other: Type) -> bool: ...
     def __init__(self, cast_from_type: Type) -> None: ...
+    def __repr__(self) -> str: ...
+    @property
+    def typeid(self) -> TypeID: ...
+
+class F32Type(Type):
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
     @staticmethod
-    def get(*args, **kwargs) -> Float8E5M2Type: ...
+    def get(context: Optional[Context] = None) -> F32Type:
+        """
+        Create a f32 type.
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
-
-class Float8E4M3FNUZType(Type):
+    def isinstance(other: Type) -> bool: ...
     def __init__(self, cast_from_type: Type) -> None: ...
+    def __repr__(self) -> str: ...
+    @property
+    def typeid(self) -> TypeID: ...
+
+class F64Type(Type):
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
     @staticmethod
-    def get(*args, **kwargs) -> Float8E4M3FNUZType: ...
+    def get(context: Optional[Context] = None) -> F64Type:
+        """
+        Create a f64 type.
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
-
-class Float8E4M3B11FNUZType(Type):
+    def isinstance(other: Type) -> bool: ...
     def __init__(self, cast_from_type: Type) -> None: ...
+    def __repr__(self) -> str: ...
+    @property
+    def typeid(self) -> TypeID: ...
+
+class FlatSymbolRefAttr(Attribute):
     @staticmethod
-    def get(*args, **kwargs) -> Float8E4M3B11FNUZType: ...
+    def get(value: str, context: Optional[Context] = None) -> FlatSymbolRefAttr:
+        """
+        Gets a uniqued FlatSymbolRef attribute
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: Attribute) -> bool: ...
+    def __init__(self, cast_from_attr: Attribute) -> None: ...
+    def __repr__(self) -> str: ...
+    @property
+    def static_typeid(self) -> TypeID: ...
+    @property
+    def type(self) -> Type: ...
+    @property
+    def typeid(self) -> TypeID: ...
+    @property
+    def value(self) -> str:
+        """
+        Returns the value of the FlatSymbolRef attribute as a string
+        """
 
-class Float8E5M2FNUZType(Type):
-    def __init__(self, cast_from_type: Type) -> None: ...
+class Float8E4M3B11FNUZType(Type):
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
     @staticmethod
-    def get(*args, **kwargs) -> Float8E5M2FNUZType: ...
+    def get(context: Optional[Context] = None) -> Float8E4M3B11FNUZType:
+        """
+        Create a float8_e4m3b11fnuz type.
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
-
-# TODO: Auto-generated. Audit and fix.
-class F16Type(Type):
+    def isinstance(other: Type) -> bool: ...
     def __init__(self, cast_from_type: Type) -> None: ...
+    def __repr__(self) -> str: ...
+    @property
+    def typeid(self) -> TypeID: ...
+
+class Float8E4M3FNType(Type):
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
     @staticmethod
-    def get(*args, **kwargs) -> F16Type: ...
+    def get(context: Optional[Context] = None) -> Float8E4M3FNType:
+        """
+        Create a float8_e4m3fn type.
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
-
-# TODO: Auto-generated. Audit and fix.
-class FloatTF32Type(Type):
+    def isinstance(other: Type) -> bool: ...
     def __init__(self, cast_from_type: Type) -> None: ...
+    def __repr__(self) -> str: ...
+    @property
+    def typeid(self) -> TypeID: ...
+
+class Float8E4M3FNUZType(Type):
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
     @staticmethod
-    def get(*args, **kwargs) -> FloatTF32Type: ...
+    def get(context: Optional[Context] = None) -> Float8E4M3FNUZType:
+        """
+        Create a float8_e4m3fnuz type.
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
-
-# TODO: Auto-generated. Audit and fix.
-class F32Type(Type):
+    def isinstance(other: Type) -> bool: ...
     def __init__(self, cast_from_type: Type) -> None: ...
+    def __repr__(self) -> str: ...
+    @property
+    def typeid(self) -> TypeID: ...
+
+class Float8E5M2FNUZType(Type):
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
     @staticmethod
-    def get(*args, **kwargs) -> F32Type: ...
+    def get(context: Optional[Context] = None) -> Float8E5M2FNUZType:
+        """
+        Create a float8_e5m2fnuz type.
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
-
-# TODO: Auto-generated. Audit and fix.
-class F64Type(Type):
+    def isinstance(other: Type) -> bool: ...
     def __init__(self, cast_from_type: Type) -> None: ...
+    def __repr__(self) -> str: ...
+    @property
+    def typeid(self) -> TypeID: ...
+
+class Float8E5M2Type(Type):
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
     @staticmethod
-    def get(*args, **kwargs) -> F64Type: ...
+    def get(context: Optional[Context] = None) -> Float8E5M2Type:
+        """
+        Create a float8_e5m2 type.
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: Type) -> bool: ...
+    def __init__(self, cast_from_type: Type) -> None: ...
+    def __repr__(self) -> str: ...
+    @property
+    def typeid(self) -> TypeID: ...
 
-# TODO: Auto-generated. Audit and fix.
-class FlatSymbolRefAttr(Attribute):
+class FloatAttr(Attribute):
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
+    @staticmethod
+    def get(type: Type, value: float, loc: Optional[Location] = None) -> FloatAttr:
+        """
+        Gets an uniqued float point attribute associated to a type
+        """
+    @staticmethod
+    def get_f32(value: float, context: Optional[Context] = None) -> FloatAttr:
+        """
+        Gets an uniqued float point attribute associated to a f32 type
+        """
+    @staticmethod
+    def get_f64(value: float, context: Optional[Context] = None) -> FloatAttr:
+        """
+        Gets an uniqued float point attribute associated to a f64 type
+        """
+    @staticmethod
+    def isinstance(other: Attribute) -> bool: ...
+    def __float__(self: Attribute) -> float:
+        """
+        Converts the value of the float attribute to a Python float
+        """
     def __init__(self, cast_from_attr: Attribute) -> None: ...
-    @staticmethod
-    def get(*args, **kwargs) -> FlatSymbolRefAttr: ...
-    @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def __repr__(self) -> str: ...
     @property
     def type(self) -> Type: ...
     @property
-    def value(self) -> str: ...
+    def typeid(self) -> TypeID: ...
+    @property
+    def value(self) -> float:
+        """
+        Returns the value of the float attribute
+        """
 
-# TODO: Auto-generated. Audit and fix.
-class FloatAttr(Attribute):
-    def __init__(self, cast_from_attr: Attribute) -> None: ...
-    @staticmethod
-    def get(*args, **kwargs) -> FloatAttr: ...
-    @staticmethod
-    def get_f32(*args, **kwargs) -> FloatAttr: ...
+class FloatTF32Type(Type):
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
     @staticmethod
-    def get_f64(*args, **kwargs) -> FloatAttr: ...
+    def get(context: Optional[Context] = None) -> FloatTF32Type:
+        """
+        Create a tf32 type.
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
-    @property
-    def type(self) -> Type: ...
+    def isinstance(other: Type) -> bool: ...
+    def __init__(self, cast_from_type: Type) -> None: ...
+    def __repr__(self) -> str: ...
     @property
-    def value(self) -> float: ...
+    def typeid(self) -> TypeID: ...
 
-# TODO: Auto-generated. Audit and fix.
 class FunctionType(Type):
-    def __init__(self, cast_from_type: Type) -> None: ...
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
     @staticmethod
-    def get(*args, **kwargs) -> FunctionType: ...
+    def get(
+        inputs: List[Type], results: List[Type], context: Optional[Context] = None
+    ) -> FunctionType:
+        """
+        Gets a FunctionType from a List of input and result types
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: Type) -> bool: ...
+    def __init__(self, cast_from_type: Type) -> None: ...
+    def __repr__(self) -> str: ...
+    @property
+    def inputs(self) -> List:
+        """
+        Returns the List of input types in the FunctionType.
+        """
     @property
-    def inputs(self) -> list: ...
+    def results(self) -> List:
+        """
+        Returns the List of result types in the FunctionType.
+        """
     @property
-    def results(self) -> list: ...
+    def typeid(self) -> TypeID: ...
 
-# TODO: Auto-generated. Audit and fix.
 class IndexType(Type):
-    def __init__(self, cast_from_type: Type) -> None: ...
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
     @staticmethod
-    def get(*args, **kwargs) -> IndexType: ...
+    def get(context: Optional[Context] = None) -> IndexType:
+        """
+        Create a index type.
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: Type) -> bool: ...
+    def __init__(self, cast_from_type: Type) -> None: ...
+    def __repr__(self) -> str: ...
+    @property
+    def typeid(self) -> TypeID: ...
 
 class InferShapedTypeOpInterface:
-    def __init__(self, object: object, context: Optional[Context] = None) -> None: ...
-    def inferReturnTypeComponents(self, operands: Optional[List] = None, attributes: Optional[Attribute] = None, properties = None, regions: Optional[List[Region]] = None, context: Optional[Context] = None, loc: Optional[Location] = None) -> List[ShapedTypeComponents]: ...
-    @property
-    def operation(self) -> Operation: ...
-    @property
-    def opview(self) -> OpView: ...
+    def __init__(self, object: object, context: Optional[Context] = None) -> None:
+        """
+        Creates an interface from a given operation/opview object or from a
+        subclass of OpView. Raises ValueError if the operation does not implement the
+        interface.
+        """
+    def inferReturnTypeComponents(
+        self,
+        operands: Optional[List] = None,
+        attributes: Optional[Attribute] = None,
+        properties=None,
+        regions: Optional[List[Region]] = None,
+        context: Optional[Context] = None,
+        loc: Optional[Location] = None,
+    ) -> List[ShapedTypeComponents]:
+        """
+        Given the arguments required to build an operation, attempts to infer
+        its return shaped type components. Raises ValueError on failure.
+        """
+    @property
+    def operation(self) -> Operation:
+        """
+        Returns an Operation for which the interface was constructed.
+        """
+    @property
+    def opview(self) -> OpView:
+        """
+        Returns an OpView subclass _instance_ for which the interface was
+        constructed
+        """
 
 class InferTypeOpInterface:
-    def __init__(self, object: object, context: Optional[Context] = None) -> None: ...
-    def inferReturnTypes(self, operands: Optional[List] = None, attributes: Optional[Attribute] = None, properties = None, regions: Optional[List[Region]] = None, context: Optional[Context] = None, loc: Optional[Location] = None) -> List[Type]: ...
-    @property
-    def operation(self) -> Operation: ...
-    @property
-    def opview(self) -> OpView: ...
+    def __init__(self, object: object, context: Optional[Context] = None) -> None:
+        """
+        Creates an interface from a given operation/opview object or from a
+        subclass of OpView. Raises ValueError if the operation does not implement the
+        interface.
+        """
+    def inferReturnTypes(
+        self,
+        operands: Optional[List] = None,
+        attributes: Optional[Attribute] = None,
+        properties=None,
+        regions: Optional[List[Region]] = None,
+        context: Optional[Context] = None,
+        loc: Optional[Location] = None,
+    ) -> List[Type]:
+        """
+        Given the arguments required to build an operation, attempts to infer
+        its return types. Raises ValueError on failure.
+        """
+    @property
+    def operation(self) -> Operation:
+        """
+        Returns an Operation for which the interface was constructed.
+        """
+    @property
+    def opview(self) -> OpView:
+        """
+        Returns an OpView subclass _instance_ for which the interface was
+        constructed
+        """
 
 class InsertionPoint:
     current: ClassVar[InsertionPoint] = ...  # read-only
+    @staticmethod
+    def at_block_begin(block: Block) -> InsertionPoint:
+        """
+        Inserts at the beginning of the block.
+        """
+    @staticmethod
+    def at_block_terminator(block: Block) -> InsertionPoint:
+        """
+        Inserts before the block terminator.
+        """
+    def __enter__(self) -> Any: ...
+    def __exit__(self, arg0: Any, arg1: Any, arg2: Any) -> None: ...
     @overload
-    def __init__(self, block: Block) -> None: ...
+    def __init__(self, block: Block) -> None:
+        """
+        Inserts after the last operation but still inside the block.
+        """
     @overload
-    def __init__(self, beforeOperation: _OperationBase) -> None: ...
-    @staticmethod
-    def at_block_begin(block: Block) -> InsertionPoint: ...
-    @staticmethod
-    def at_block_terminator(block: Block) -> InsertionPoint: ...
-    def insert(self, operation: _OperationBase) -> None: ...
-    def __enter__(self) -> InsertionPoint: ...
-    def __exit__(self, arg0: object, arg1: object, arg2: object) -> None: ...
-    @property
-    def block(self) -> Block: ...
-    @property
-    def ref_operation(self) -> Optional[_OperationBase]: ...
+    def __init__(self, beforeOperation: _OperationBase) -> None:
+        """
+        Inserts before a referenced operation.
+        """
+    def insert(self, operation: _OperationBase) -> None:
+        """
+        Inserts an operation.
+        """
+    @property
+    def block(self) -> Block:
+        """
+        Returns the block that this InsertionPoint points to.
+        """
+    @property
+    def ref_operation(self) -> Optional[_OperationBase]:
+        """
+        The reference operation before which new operations are inserted, or None if the insertion point is at the end of the block
+        """
 
-# TODO: Auto-generated. Audit and fix.
 class IntegerAttr(Attribute):
-    def __init__(self, cast_from_attr: Attribute) -> None: ...
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
     @staticmethod
-    def get(*args, **kwargs) -> IntegerAttr: ...
+    def get(type: Type, value: int) -> IntegerAttr:
+        """
+        Gets an uniqued integer attribute associated to a type
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: Attribute) -> bool: ...
+    def __init__(self, cast_from_attr: Attribute) -> None: ...
+    def __int__(self) -> int:
+        """
+        Converts the value of the integer attribute to a Python int
+        """
+    def __repr__(self) -> str: ...
     @property
     def type(self) -> Type: ...
     @property
-    def value(self) -> int: ...
+    def typeid(self) -> TypeID: ...
+    @property
+    def value(self) -> int:
+        """
+        Returns the value of the integer attribute
+        """
 
-# TODO: Auto-generated. Audit and fix.
 class IntegerSet:
-    def __init__(self, *args, **kwargs) -> None: ...
-    def _CAPICreate(self) -> IntegerSet: ...
-    def dump(self) -> None: ...
     @staticmethod
-    def get(*args, **kwargs) -> IntegerSet: ...
-    @staticmethod
-    def get_empty(*args, **kwargs) -> IntegerSet: ...
-    def get_replaced(self, dim_exprs: list, symbol_exprs: list, num_result_dims: int, num_result_symbols: int) -> IntegerSet: ...
+    def get(
+        num_dims: int,
+        num_symbols: int,
+        exprs: List,
+        eq_flags: List[bool],
+        context: Optional[Context] = None,
+    ) -> IntegerSet: ...
+    @staticmethod
+    def get_empty(
+        num_dims: int, num_symbols: int, context: Optional[Context] = None
+    ) -> IntegerSet: ...
+    def _CAPICreate(self) -> IntegerSet: ...
     @overload
     def __eq__(self, arg0: IntegerSet) -> bool: ...
     @overload
     def __eq__(self, arg0: object) -> bool: ...
     def __hash__(self) -> int: ...
+    def __repr__(self) -> str: ...
+    def __str__(self) -> str: ...
+    def dump(self) -> None:
+        """
+        Dumps a debug representation of the object to stderr.
+        """
+    def get_replaced(
+        self,
+        dim_exprs: List,
+        symbol_exprs: List,
+        num_result_dims: int,
+        num_result_symbols: int,
+    ) -> IntegerSet: ...
     @property
     def _CAPIPtr(self) -> object: ...
     @property
-    def constraints(self) -> Any: ...
+    def constraints(self) -> IntegerSetConstraintList: ...
     @property
     def context(self) -> Context: ...
     @property
@@ -804,7 +1872,6 @@ class IntegerSet:
     @property
     def n_symbols(self) -> int: ...
 
-# TODO: Auto-generated. Audit and fix.
 class IntegerSetConstraint:
     def __init__(self, *args, **kwargs) -> None: ...
     @property
@@ -812,7 +1879,6 @@ class IntegerSetConstraint:
     @property
     def is_eq(self) -> bool: ...
 
-# TODO: Auto-generated. Audit and fix.
 class IntegerSetConstraintList:
     def __init__(self, *args, **kwargs) -> None: ...
     def __add__(self, arg0: IntegerSetConstraintList) -> List[IntegerSetConstraint]: ...
@@ -822,108 +1888,232 @@ class IntegerSetConstraintList:
     def __getitem__(self, arg0: slice) -> IntegerSetConstraintList: ...
     def __len__(self) -> int: ...
 
-# TODO: Auto-generated. Audit and fix.
 class IntegerType(Type):
-    def __init__(self, cast_from_type: Type) -> None: ...
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
     @staticmethod
-    def get_signed(*args, **kwargs) -> IntegerType: ...
+    def get_signed(width: int, context: Optional[Context] = None) -> IntegerType:
+        """
+        Create a signed integer type
+        """
     @staticmethod
-    def get_signless(*args, **kwargs) -> IntegerType: ...
+    def get_signless(width: int, context: Optional[Context] = None) -> IntegerType:
+        """
+        Create a signless integer type
+        """
     @staticmethod
-    def get_unsigned(*args, **kwargs) -> IntegerType: ...
+    def get_unsigned(width: int, context: Optional[Context] = None) -> IntegerType:
+        """
+        Create an unsigned integer type
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: Type) -> bool: ...
+    def __init__(self, cast_from_type: Type) -> None: ...
+    def __repr__(self) -> str: ...
+    @property
+    def is_signed(self) -> bool:
+        """
+        Returns whether this is a signed integer
+        """
     @property
-    def is_signed(self) -> bool: ...
+    def is_signless(self) -> bool:
+        """
+        Returns whether this is a signless integer
+        """
     @property
-    def is_signless(self) -> bool: ...
+    def is_unsigned(self) -> bool:
+        """
+        Returns whether this is an unsigned integer
+        """
     @property
-    def is_unsigned(self) -> bool: ...
+    def typeid(self) -> TypeID: ...
     @property
-    def width(self) -> int: ...
+    def width(self) -> int:
+        """
+        Returns the width of the integer type
+        """
 
 class Location:
     current: ClassVar[Location] = ...  # read-only
-    __hash__: ClassVar[None] = ...  # type: ignore
+    __hash__: ClassVar[None] = None
+    @staticmethod
+    def callsite(
+        callee: Location, frames: Sequence[Location], context: Optional[Context] = None
+    ) -> Location:
+        """
+        Gets a Location representing a caller and callsite
+        """
+    @staticmethod
+    def file(
+        filename: str, line: int, col: int, context: Optional[Context] = None
+    ) -> Location:
+        """
+        Gets a Location representing a file, line and column
+        """
+    @staticmethod
+    def from_attr(attribute: Attribute, context: Optional[Context] = None) -> Location:
+        """
+        Gets a Location from a LocationAttr
+        """
+    @staticmethod
+    def fused(
+        locations: Sequence[Location],
+        metadata: Optional[Attribute] = None,
+        context: Optional[Context] = None,
+    ) -> Location:
+        """
+        Gets a Location representing a fused location with optional metadata
+        """
+    @staticmethod
+    def name(
+        name: str,
+        childLoc: Optional[Location] = None,
+        context: Optional[Context] = None,
+    ) -> Location:
+        """
+        Gets a Location representing a named location with optional child location
+        """
+    @staticmethod
+    def unknown(context: Optional[Context] = None) -> Location:
+        """
+        Gets a Location representing an unknown location
+        """
     def _CAPICreate(self) -> Location: ...
-    @staticmethod
-    def callsite(callee: Location, frames: Sequence[Location], context: Optional[Context] = None) -> Location: ...
-    @staticmethod
-    def file(filename: str, line: int, col: int, context: Optional[Context] = None) -> Location: ...
-    @staticmethod
-    def fused(locations: Sequence[Location], metadata: Optional[Attribute] = None, context: Optional[Context] = None) -> Location: ...
-    @staticmethod
-    def name(name: str, childLoc: Optional[Location] = None, context: Optional[Context] = None) -> Location: ...
-    @staticmethod
-    def unknown(context: Optional[Context] = None) -> Any: ...
     def __enter__(self) -> Location: ...
     @overload
     def __eq__(self, arg0: Location) -> bool: ...
     @overload
-    def __eq__(self, arg0: object) -> bool: ...
+    def __eq__(self, arg0: Location) -> bool: ...
     def __exit__(self, arg0: object, arg1: object, arg2: object) -> None: ...
+    def __repr__(self) -> str: ...
+    def emit_error(self, message: str) -> None:
+        """
+        Emits an error at this location
+        """
     @property
     def _CAPIPtr(self) -> object: ...
     @property
-    def context(self) -> Context: ...
+    def attr(self) -> Attribute:
+        """
+        Get the underlying LocationAttr
+        """
+    @property
+    def context(self) -> Context:
+        """
+        Context that owns the Location
+        """
 
-# TODO: Auto-generated. Audit and fix.
 class MemRefType(ShapedType):
-    def __init__(self, cast_from_type: Type) -> None: ...
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
     @staticmethod
-    def get(*args, **kwargs) -> MemRefType: ...
+    def get(
+        shape: List[int],
+        element_type: Type,
+        layout: Attribute = None,
+        memory_space: Attribute = None,
+        loc: Optional[Location] = None,
+    ) -> MemRefType:
+        """
+        Create a memref type
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: Type) -> bool: ...
+    def __init__(self, cast_from_type: Type) -> None: ...
+    def __repr__(self) -> str: ...
+    @property
+    def affine_map(self) -> AffineMap:
+        """
+        The layout of the MemRef type as an affine map.
+        """
     @property
-    def affine_map(self) -> AffineMap: ...
+    def layout(self) -> Attribute:
+        """
+        The layout of the MemRef type.
+        """
     @property
-    def layout(self) -> Attribute: ...
+    def memory_space(self) -> Optional[Attribute]:
+        """
+        Returns the memory space of the given MemRef type.
+        """
     @property
-    def memory_space(self) -> Attribute: ...
+    def typeid(self) -> TypeID: ...
 
 class Module:
-    def _CAPICreate(self) -> object: ...
     @staticmethod
-    def create(loc: Optional[Location] = None) -> Module: ...
-    def dump(self) -> None: ...
-    @staticmethod
-    def parse(asm: str, context: Optional[Context] = None) -> Module: ...
+    def create(loc: Optional[Location] = None) -> Any:
+        """
+        Creates an empty module
+        """
+    @staticmethod
+    def parse(asm: str, context: Optional[Context] = None) -> Any:
+        """
+        Parses a module's assembly format from a string.
+
+        Returns a new MlirModule or raises an MLIRError if the parsing fails.
+
+        See also: https://mlir.llvm.org/docs/LangRef/
+        """
+    def _CAPICreate(self) -> Any: ...
+    def __str__(self) -> Any:
+        """
+        Gets the assembly form of the operation with default options.
+
+        If more advanced control over the assembly formatting or I/O options is needed,
+        use the dedicated print or get_asm method, which supports keyword arguments to
+        customize behavior.
+        """
+    def dump(self) -> None:
+        """
+        Dumps a debug representation of the object to stderr.
+        """
     @property
     def _CAPIPtr(self) -> object: ...
     @property
-    def body(self) -> Block: ...
+    def body(self) -> Block:
+        """
+        Return the block for this module
+        """
     @property
-    def context(self) -> Context: ...
+    def context(self) -> Context:
+        """
+        Context that created the Module
+        """
     @property
-    def operation(self) -> Operation: ...
+    def operation(self) -> Any:
+        """
+        Accesses the module as an operation
+        """
 
 class MLIRError(Exception):
-    def __init__(self, message: str, error_diagnostics: List[DiagnosticInfo]) -> None: ...
+    def __init__(
+        self, message: str, error_diagnostics: List[DiagnosticInfo]
+    ) -> None: ...
 
 class NamedAttribute:
+    def __repr__(self) -> str: ...
     @property
-    def attr(self) -> Attribute: ...
+    def attr(self) -> Attribute:
+        """
+        The underlying generic attribute of the NamedAttribute binding
+        """
     @property
-    def name(self) -> str: ...
+    def name(self) -> str:
+        """
+        The name of the NamedAttribute binding
+        """
 
-# TODO: Auto-generated. Audit and fix.
 class NoneType(Type):
-    def __init__(self, cast_from_type: Type) -> None: ...
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
     @staticmethod
-    def get(*args, **kwargs) -> NoneType: ...
+    def get(context: Optional[Context] = None) -> NoneType:
+        """
+        Create a none type.
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
-
-class OpaqueType(Type):
+    def isinstance(other: Type) -> bool: ...
     def __init__(self, cast_from_type: Type) -> None: ...
-    @staticmethod
-    def get(*args, **kwargs) -> OpaqueType: ...
-    @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def __repr__(self) -> str: ...
     @property
-    def dialect_namespace(self) -> str: ...
-    @property
-    def data(self) -> str: ...
+    def typeid(self) -> TypeID: ...
 
 class OpAttributeMap:
     def __contains__(self, arg0: str) -> bool: ...
@@ -935,6 +2125,16 @@ class OpAttributeMap:
     def __len__(self) -> int: ...
     def __setitem__(self, arg0: str, arg1: Attribute) -> None: ...
 
+class OpOperand:
+    @property
+    def operand_number(self) -> int: ...
+    @property
+    def owner(self) -> _OperationBase: ...
+
+class OpOperandIterator:
+    def __iter__(self) -> OpOperandIterator: ...
+    def __next__(self) -> OpOperand: ...
+
 class OpOperandList:
     def __add__(self, arg0: OpOperandList) -> List[Value]: ...
     @overload
@@ -945,6 +2145,8 @@ class OpOperandList:
     def __setitem__(self, arg0: int, arg1: Value) -> None: ...
 
 class OpResult(Value):
+    @staticmethod
+    def isinstance(other_value: Value) -> bool: ...
     def __init__(self, value: Value) -> None: ...
     @staticmethod
     def isinstance(arg: Any) -> bool: ...
@@ -961,8 +2163,14 @@ class OpResultList:
     def __getitem__(self, arg0: slice) -> OpResultList: ...
     def __len__(self) -> int: ...
     @property
+    def owner(self) -> _OperationBase: ...
+    @property
     def types(self) -> List[Type]: ...
 
+class OpSuccessors:
+    def __add__(self, arg0: OpSuccessors) -> List[Block]: ...
+    def __setitem__(self, arg0: int, arg1: Block) -> None: ...
+
 class OpView(_OperationBase):
     _ODS_OPERAND_SEGMENTS: ClassVar[None] = ...
     _ODS_REGIONS: ClassVar[tuple] = ...
@@ -977,60 +2185,193 @@ class OpView(_OperationBase):
         successors: Optional[Sequence[Block]] = None,
         regions: Optional[int] = None,
         loc: Optional[Location] = None,
-        ip: Optional[InsertionPoint] = None) -> _TOperation: ...
+        ip: Optional[InsertionPoint] = None,
+    ) -> _TOperation:
+        """
+        Builds a specific, generated OpView based on class level attributes.
+        """
+    @classmethod
+    def parse(
+        cls: _Type[_TOperation],
+        source: str,
+        *,
+        source_name: str = "",
+        context: Optional[Context] = None,
+    ) -> _TOperation:
+        """
+        Parses a specific, generated OpView based on class level attributes
+        """
+    def __init__(self, operation: _OperationBase) -> None: ...
+    def __str__(self) -> str: ...
     @property
-    def operation(self) -> Operation: ...
+    def operation(self) -> _OperationBase: ...
+    @property
+    def opview(self) -> OpView: ...
+    @property
+    def successors(self) -> OpSuccessors:
+        """
+        Returns the List of Operation successors.
+        """
+
+class OpaqueAttr(Attribute):
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
+    @staticmethod
+    def get(
+        dialect_namespace: str,
+        buffer: Buffer,
+        type: Type,
+        context: Optional[Context] = None,
+    ) -> OpaqueAttr:
+        """
+        Gets an Opaque attribute.
+        """
+    @staticmethod
+    def isinstance(other: Attribute) -> bool: ...
+    def __init__(self, cast_from_attr: Attribute) -> None: ...
+    def __repr__(self) -> str: ...
+    @property
+    def data(self) -> bytes:
+        """
+        Returns the data for the Opaqued attributes as `bytes`
+        """
+    @property
+    def dialect_namespace(self) -> str:
+        """
+        Returns the dialect namespace for the Opaque attribute as a string
+        """
+    @property
+    def type(self) -> Type: ...
+    @property
+    def typeid(self) -> TypeID: ...
+
+class OpaqueType(Type):
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
+    @staticmethod
+    def get(
+        dialect_namespace: str, buffer: str, context: Optional[Context] = None
+    ) -> OpaqueType:
+        """
+        Create an unregistered (opaque) dialect type.
+        """
+    @staticmethod
+    def isinstance(other: Type) -> bool: ...
+    def __init__(self, cast_from_type: Type) -> None: ...
+    def __repr__(self) -> str: ...
     @property
-    def opview(self) -> "OpView": ...
+    def data(self) -> str:
+        """
+        Returns the data for the Opaque type as a string.
+        """
+    @property
+    def dialect_namespace(self) -> str:
+        """
+        Returns the dialect namespace for the Opaque type as a string.
+        """
+    @property
+    def typeid(self) -> TypeID: ...
 
 class Operation(_OperationBase):
     def _CAPICreate(self) -> object: ...
     @staticmethod
-    def create(name: str, results: Optional[Sequence[Type]] = None,
+    def create(
+        name: str,
+        results: Optional[Sequence[Type]] = None,
         operands: Optional[Sequence[Value]] = None,
         attributes: Optional[Dict[str, Attribute]] = None,
         successors: Optional[Sequence[Block]] = None,
         regions: int = 0,
         loc: Optional[Location] = None,
-        ip: Optional[InsertionPoint] = None) -> _OperationBase: ...
-    def erase(self) -> None: ...
+        ip: Optional[InsertionPoint] = None,
+        infer_type: bool = False,
+    ) -> Operation:
+        """
+        Creates a new operation.
+
+        Args:
+          name: Operation name (e.g. "dialect.operation").
+          results: Sequence of Type representing op result types.
+          attributes: Dict of str:Attribute.
+          successors: List of Block for the operation's successors.
+          regions: Number of regions to create.
+          location: A Location object (defaults to resolve from context manager).
+          ip: An InsertionPoint (defaults to resolve from context manager or set to
+            False to disable insertion, even with an insertion point set in the
+            context manager).
+          infer_type: Whether to infer result types.
+        Returns:
+          A new "detached" Operation object. Detached operations can be added
+          to blocks, which causes them to become "attached."
+        """
+    @staticmethod
+    def parse(
+        source: str, *, source_name: str = "", context: Optional[Context] = None
+    ) -> Any:
+        """
+        Parses an operation. Supports both text assembly format and binary bytecode format.
+        """
+    def _CAPICreate(self) -> object: ...
     @property
     def _CAPIPtr(self) -> object: ...
     @property
-    def operation(self) -> "Operation": ...
+    def operation(self) -> Operation: ...
     @property
     def opview(self) -> OpView: ...
+    @property
+    def successors(self) -> OpSuccessors:
+        """
+        Returns the List of Operation successors.
+        """
 
 class OperationIterator:
     def __iter__(self) -> OperationIterator: ...
     def __next__(self) -> OpView: ...
 
 class OperationList:
-    def __getitem__(self, arg0: int) -> OpView: ...
+    def __getitem__(self, arg0: int) -> Any: ...
     def __iter__(self) -> OperationIterator: ...
     def __len__(self) -> int: ...
 
-# TODO: Auto-generated. Audit and fix.
 class RankedTensorType(ShapedType):
-    def __init__(self, cast_from_type: Type) -> None: ...
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
     @staticmethod
-    def get(*args, **kwargs) -> RankedTensorType: ...
+    def get(
+        shape: List[int],
+        element_type: Type,
+        encoding: Optional[Attribute] = None,
+        loc: Optional[Location] = None,
+    ) -> RankedTensorType:
+        """
+        Create a ranked tensor type
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: Type) -> bool: ...
+    def __init__(self, cast_from_type: Type) -> None: ...
+    def __repr__(self) -> str: ...
     @property
     def encoding(self) -> Optional[Attribute]: ...
+    @property
+    def typeid(self) -> TypeID: ...
 
 class Region:
-    __hash__: ClassVar[None] = ...  # type: ignore
+    __hash__: ClassVar[None] = None
     @overload
     def __eq__(self, arg0: Region) -> bool: ...
     @overload
     def __eq__(self, arg0: object) -> bool: ...
-    def __iter__(self) -> BlockIterator: ...
+    def __iter__(self) -> BlockIterator:
+        """
+        Iterates over blocks in the region.
+        """
     @property
-    def blocks(self) -> BlockList: ...
+    def blocks(self) -> BlockList:
+        """
+        Returns a forward-optimized sequence of blocks.
+        """
     @property
-    def owner(self) -> OpView: ...
+    def owner(self) -> OpView:
+        """
+        Returns the operation owning this region.
+        """
 
 class RegionIterator:
     def __iter__(self) -> RegionIterator: ...
@@ -1038,132 +2379,353 @@ class RegionIterator:
 
 class RegionSequence:
     def __getitem__(self, arg0: int) -> Region: ...
+    def __iter__(self) -> RegionIterator: ...
     def __len__(self) -> int: ...
 
-# TODO: Auto-generated. Audit and fix.
 class ShapedType(Type):
+    @staticmethod
+    def get_dynamic_size() -> int:
+        """
+        Returns the value used to indicate dynamic dimensions in shaped types.
+        """
+    @staticmethod
+    def get_dynamic_stride_or_offset() -> int:
+        """
+        Returns the value used to indicate dynamic strides or offsets in shaped types.
+        """
+    @staticmethod
+    def is_dynamic_size(dim_size: int) -> bool:
+        """
+        Returns whether the given dimension size indicates a dynamic dimension.
+        """
+    @staticmethod
+    def isinstance(other: Type) -> bool: ...
     def __init__(self, cast_from_type: Type) -> None: ...
-    def get_dim_size(self, dim: int) -> int: ...
-    def is_dynamic_dim(self, dim: int) -> bool: ...
-    def is_dynamic_size(self, *args, **kwargs) -> Any: ...
-    def is_dynamic_stride_or_offset(self, dim_size: int) -> bool: ...
+    def __repr__(self) -> str: ...
+    def get_dim_size(self, dim: int) -> int:
+        """
+        Returns the dim-th dimension of the given ranked shaped type.
+        """
+    def is_dynamic_dim(self, dim: int) -> bool:
+        """
+        Returns whether the dim-th dimension of the given shaped type is dynamic.
+        """
+    def is_dynamic_stride_or_offset(self, dim_size: int) -> bool:
+        """
+        Returns whether the given value is used as a placeholder for dynamic strides and offsets in shaped types.
+        """
+    @property
+    def element_type(self) -> Type:
+        """
+        Returns the element type of the shaped type.
+        """
+    @property
+    def has_rank(self) -> bool:
+        """
+        Returns whether the given shaped type is ranked.
+        """
+    @property
+    def has_static_shape(self) -> bool:
+        """
+        Returns whether the given shaped type has a static shape.
+        """
+    @property
+    def rank(self) -> int:
+        """
+        Returns the rank of the given ranked shaped type.
+        """
+    @property
+    def shape(self) -> List[int]:
+        """
+        Returns the shape of the ranked shaped type as a List of integers.
+        """
+    @property
+    def static_typeid(self) -> TypeID: ...
+    @property
+    def typeid(self) -> TypeID: ...
+
+class ShapedTypeComponents:
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
-    @property
-    def element_type(self) -> Type: ...
+    @overload
+    def get(element_type: Type) -> ShapedTypeComponents:
+        """
+        Create an shaped type components object with only the element type.
+        """
+    @staticmethod
+    @overload
+    def get(shape: List, element_type: Type) -> ShapedTypeComponents:
+        """
+        Create a ranked shaped type components object.
+        """
+    @staticmethod
+    @overload
+    def get(
+        shape: List, element_type: Type, attribute: Attribute
+    ) -> ShapedTypeComponents:
+        """
+        Create a ranked shaped type components object with attribute.
+        """
+    @property
+    def element_type(self) -> Type:
+        """
+        Returns the element type of the shaped type components.
+        """
+    @property
+    def has_rank(self) -> bool:
+        """
+        Returns whether the given shaped type component is ranked.
+        """
+    @property
+    def rank(self) -> int:
+        """
+        Returns the rank of the given ranked shaped type components. If the shaped type components does not have a rank, None is returned.
+        """
+    @property
+    def shape(self) -> List[int]:
+        """
+        Returns the shape of the ranked shaped type components as a List of integers. Returns none if the shaped type component does not have a rank.
+        """
+
+class StridedLayoutAttr(Attribute):
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
+    @staticmethod
+    def get(
+        offset: int, strides: List[int], context: Optional[Context] = None
+    ) -> StridedLayoutAttr:
+        """
+        Gets a strided layout attribute.
+        """
+    @staticmethod
+    def get_fully_dynamic(
+        rank: int, context: Optional[Context] = None
+    ) -> StridedLayoutAttr:
+        """
+        Gets a strided layout attribute with dynamic offset and strides of a given rank.
+        """
+    @staticmethod
+    def isinstance(other: Attribute) -> bool: ...
+    def __init__(self, cast_from_attr: Attribute) -> None: ...
+    def __repr__(self) -> str: ...
     @property
-    def has_rank(self) -> bool: ...
+    def offset(self) -> int:
+        """
+        Returns the value of the float point attribute
+        """
     @property
-    def has_static_shape(self) -> bool: ...
+    def strides(self) -> List[int]:
+        """
+        Returns the value of the float point attribute
+        """
     @property
-    def rank(self) -> int: ...
+    def type(self) -> Type: ...
     @property
-    def shape(self) -> List[int]: ...
+    def typeid(self) -> TypeID: ...
 
-class ShapedTypeComponents:
-    @property
-    def element_type(self) -> Type: ...
+class StringAttr(Attribute):
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
     @staticmethod
-    def get(*args, **kwargs) -> ShapedTypeComponents: ...
+    def get(value: str, context: Optional[Context] = None) -> StringAttr:
+        """
+        Gets a uniqued string attribute
+        """
+    @staticmethod
+    def get_typed(type: Type, value: str) -> StringAttr:
+        """
+        Gets a uniqued string attribute associated to a type
+        """
+    @staticmethod
+    def isinstance(other: Attribute) -> bool: ...
+    def __init__(self, cast_from_attr: Attribute) -> None: ...
+    def __repr__(self) -> str: ...
+    @property
+    def type(self) -> Type: ...
     @property
-    def has_rank(self) -> bool: ...
+    def typeid(self) -> TypeID: ...
     @property
-    def rank(self) -> int: ...
+    def value(self) -> str:
+        """
+        Returns the value of the string attribute
+        """
     @property
-    def shape(self) -> List[int]: ...
+    def value_bytes(self) -> bytes:
+        """
+        Returns the value of the string attribute as `bytes`
+        """
 
-# TODO: Auto-generated. Audit and fix.
-class StringAttr(Attribute):
-    def __init__(self, cast_from_attr: Attribute) -> None: ...
-    @staticmethod
-    def get(*args, **kwargs) -> Any: ...
+class SymbolRefAttr(Attribute):
     @staticmethod
-    def get_typed(*args, **kwargs) -> Any: ...
+    def get(symbols: List[str], context: Optional[Context] = None) -> Attribute:
+        """
+        Gets a uniqued SymbolRef attribute from a List of symbol names
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: Attribute) -> bool: ...
+    def __init__(self, cast_from_attr: Attribute) -> None: ...
+    def __repr__(self) -> str: ...
+    @property
+    def static_typeid(self) -> TypeID: ...
     @property
     def type(self) -> Type: ...
     @property
-    def value(self) -> str: ...
+    def typeid(self) -> TypeID: ...
+    @property
+    def value(self) -> List[str]:
+        """
+        Returns the value of the SymbolRef attribute as a List[str]
+        """
 
 class SymbolTable:
-    def __init__(self, arg0: _OperationBase) -> None: ...
-    def erase(self, operation: _OperationBase) -> None: ...
     @staticmethod
     def get_symbol_name(symbol: _OperationBase) -> Attribute: ...
     @staticmethod
     def get_visibility(symbol: _OperationBase) -> Attribute: ...
-    def insert(self, operation: _OperationBase) -> Attribute: ...
     @staticmethod
-    def replace_all_symbol_uses(old_symbol: str, new_symbol: str, from_op: _OperationBase) -> None: ...
+    def replace_all_symbol_uses(
+        old_symbol: str, new_symbol: str, from_op: _OperationBase
+    ) -> None: ...
     @staticmethod
     def set_symbol_name(symbol: _OperationBase, name: str) -> None: ...
     @staticmethod
     def set_visibility(symbol: _OperationBase, visibility: str) -> None: ...
     @staticmethod
-    def walk_symbol_tables(from_op: _OperationBase, all_sym_uses_visible: bool, callback: Callable[[_OperationBase, bool], None]) -> None: ...
+    def walk_symbol_tables(
+        from_op: _OperationBase,
+        all_sym_uses_visible: bool,
+        callback: Callable[[_OperationBase, bool], None],
+    ) -> None: ...
     def __contains__(self, arg0: str) -> bool: ...
     def __delitem__(self, arg0: str) -> None: ...
     def __getitem__(self, arg0: str) -> OpView: ...
+    def __init__(self, arg0: _OperationBase) -> None: ...
+    def erase(self, operation: _OperationBase) -> None: ...
+    def insert(self, operation: _OperationBase) -> Attribute: ...
 
-# TODO: Auto-generated. Audit and fix.
 class TupleType(Type):
-    def __init__(self, cast_from_type: Type) -> None: ...
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
     @staticmethod
-    def get_tuple(*args, **kwargs) -> TupleType: ...
-    def get_type(self, pos: int) -> Type: ...
+    def get_Tuple(elements: List[Type], context: Optional[Context] = None) -> TupleType:
+        """
+        Create a Tuple type
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: Type) -> bool: ...
+    def __init__(self, cast_from_type: Type) -> None: ...
+    def __repr__(self) -> str: ...
+    def get_type(self, pos: int) -> Type:
+        """
+        Returns the pos-th type in the Tuple type.
+        """
     @property
-    def num_types(self) -> int: ...
+    def num_types(self) -> int:
+        """
+        Returns the number of types contained in a Tuple.
+        """
+    @property
+    def typeid(self) -> TypeID: ...
 
-# TODO: Auto-generated. Audit and fix.
 class TypeAttr(Attribute):
-    def __init__(self, cast_from_attr: Attribute) -> None: ...
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
     @staticmethod
-    def get(*args, **kwargs) -> Any: ...
+    def get(value: Type, context: Optional[Context] = None) -> TypeAttr:
+        """
+        Gets a uniqued Type attribute
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: Attribute) -> bool: ...
+    def __init__(self, cast_from_attr: Attribute) -> None: ...
+    def __repr__(self) -> str: ...
     @property
     def type(self) -> Type: ...
     @property
+    def typeid(self) -> TypeID: ...
+    @property
     def value(self) -> Type: ...
 
-# TODO: Auto-generated. Audit and fix.
+class TypeID:
+    def _CAPICreate(self) -> TypeID: ...
+    @overload
+    def __eq__(self, arg0: TypeID) -> bool: ...
+    @overload
+    def __eq__(self, arg0: Any) -> bool: ...
+    def __hash__(self) -> int: ...
+    @property
+    def _CAPIPtr(self) -> object: ...
+
 class UnitAttr(Attribute):
-    def __init__(self, cast_from_attr: Attribute) -> None: ...
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
     @staticmethod
-    def get(*args, **kwargs) -> Any: ...
+    def get(context: Optional[Context] = None) -> UnitAttr:
+        """
+        Create a Unit attribute.
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: Attribute) -> bool: ...
+    def __init__(self, cast_from_attr: Attribute) -> None: ...
+    def __repr__(self) -> str: ...
     @property
     def type(self) -> Type: ...
+    @property
+    def typeid(self) -> TypeID: ...
 
-# TODO: Auto-generated. Audit and fix.
 class UnrankedMemRefType(ShapedType):
-    def __init__(self, cast_from_type: Type) -> None: ...
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
     @staticmethod
-    def get(*args, **kwargs) -> UnrankedMemRefType: ...
+    def get(
+        element_type: Type, memory_space: Attribute, loc: Optional[Location] = None
+    ) -> UnrankedMemRefType:
+        """
+        Create a unranked memref type
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: Type) -> bool: ...
+    def __init__(self, cast_from_type: Type) -> None: ...
+    def __repr__(self) -> str: ...
+    @property
+    def memory_space(self) -> Optional[Attribute]:
+        """
+        Returns the memory space of the given Unranked MemRef type.
+        """
     @property
-    def memory_space(self) -> Attribute: ...
+    def typeid(self) -> TypeID: ...
 
-# TODO: Auto-generated. Audit and fix.
 class UnrankedTensorType(ShapedType):
-    def __init__(self, cast_from_type: Type) -> None: ...
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
     @staticmethod
-    def get(*args, **kwargs) -> UnrankedTensorType: ...
+    def get(element_type: Type, loc: Optional[Location] = None) -> UnrankedTensorType:
+        """
+        Create a unranked tensor type
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: Type) -> bool: ...
+    def __init__(self, cast_from_type: Type) -> None: ...
+    def __repr__(self) -> str: ...
+    @property
+    def typeid(self) -> TypeID: ...
 
-# TODO: Auto-generated. Audit and fix.
 class VectorType(ShapedType):
-    def __init__(self, cast_from_type: Type) -> None: ...
-    @staticmethod
-    def get(*args, **kwargs) -> VectorType: ...
+    static_typeid: ClassVar[TypeID]  # value = <mlir._mlir_libs._TypeID object>
+    @staticmethod
+    def get(
+        shape: List[int],
+        element_type: Type,
+        *,
+        scalable: Optional[List] = None,
+        scalable_dims: Optional[List[int]] = None,
+        loc: Optional[Location] = None,
+    ) -> VectorType:
+        """
+        Create a vector type
+        """
     @staticmethod
-    def isinstance(arg: Any) -> bool: ...
+    def isinstance(other: Type) -> bool: ...
+    def __init__(self, cast_from_type: Type) -> None: ...
+    def __repr__(self) -> str: ...
+    @property
+    def scalable(self) -> bool: ...
+    @property
+    def scalable_dims(self) -> List[bool]: ...
+    @property
+    def typeid(self) -> TypeID: ...
 
 class _GlobalDebug:
-    flag: ClassVar[bool] = ...
+    flag: ClassVar[bool] = False
-- 
GitLab


From 52ba075571958e2fec8d871ddfa1ef56486b86d3 Mon Sep 17 00:00:00 2001
From: David Blaikie <dblaikie@gmail.com>
Date: Tue, 12 Dec 2023 00:41:30 +0000
Subject: [PATCH 200/349] Add missing paren

---
 llvm/lib/Support/StringMap.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Support/StringMap.cpp b/llvm/lib/Support/StringMap.cpp
index 451108d01d38..432e1fc343f1 100644
--- a/llvm/lib/Support/StringMap.cpp
+++ b/llvm/lib/Support/StringMap.cpp
@@ -148,7 +148,7 @@ int StringMapImpl::FindKey(StringRef Key, uint32_t FullHashValue) const {
   if (NumBuckets == 0)
     return -1; // Really empty table?
 #ifdef EXPENSIVE_CHECKS
-  assert(FullHashValue == hash(Key);
+  assert(FullHashValue == hash(Key));
 #endif
   if (shouldReverseIterate())
     FullHashValue = ~FullHashValue;
-- 
GitLab


From a8ef9c0969ab0807672bcad60970bf22395ffaf1 Mon Sep 17 00:00:00 2001
From: Christopher Ferris <cferris1000@users.noreply.github.com>
Date: Mon, 11 Dec 2023 16:42:44 -0800
Subject: [PATCH 201/349] [scudo] Add utilization percentages for stats.
 (#75101)

Refactor the percentage display in the secondary code. Re-use that to
display a utilization percentage when displaying fragmentation data.
---
 compiler-rt/lib/scudo/standalone/common.h    | 15 +++++++++++++++
 compiler-rt/lib/scudo/standalone/primary32.h |  8 ++++++--
 compiler-rt/lib/scudo/standalone/primary64.h |  8 ++++++--
 compiler-rt/lib/scudo/standalone/secondary.h | 14 +++++---------
 4 files changed, 32 insertions(+), 13 deletions(-)

diff --git a/compiler-rt/lib/scudo/standalone/common.h b/compiler-rt/lib/scudo/standalone/common.h
index 3581c946d160..ae45683f1ee3 100644
--- a/compiler-rt/lib/scudo/standalone/common.h
+++ b/compiler-rt/lib/scudo/standalone/common.h
@@ -112,6 +112,21 @@ template <typename T> inline void shuffle(T *A, u32 N, u32 *RandState) {
   *RandState = State;
 }
 
+inline void computePercentage(uptr Numerator, uptr Denominator, uptr *Integral,
+                              uptr *Fractional) {
+  constexpr uptr Digits = 100;
+  if (Denominator == 0) {
+    *Integral = 100;
+    *Fractional = 0;
+    return;
+  }
+
+  *Integral = Numerator * Digits / Denominator;
+  *Fractional =
+      (((Numerator * Digits) % Denominator) * Digits + Denominator / 2) /
+      Denominator;
+}
+
 // Platform specific functions.
 
 extern uptr PageSizeCached;
diff --git a/compiler-rt/lib/scudo/standalone/primary32.h b/compiler-rt/lib/scudo/standalone/primary32.h
index 8281e02ba164..4d03b282d000 100644
--- a/compiler-rt/lib/scudo/standalone/primary32.h
+++ b/compiler-rt/lib/scudo/standalone/primary32.h
@@ -931,10 +931,14 @@ private:
         AllocatedPagesCount - Recorder.getReleasedPagesCount();
     const uptr InUseBytes = InUsePages * PageSize;
 
+    uptr Integral;
+    uptr Fractional;
+    computePercentage(BlockSize * InUseBlocks, InUsePages * PageSize, &Integral,
+                      &Fractional);
     Str->append("  %02zu (%6zu): inuse/total blocks: %6zu/%6zu inuse/total "
-                "pages: %6zu/%6zu inuse bytes: %6zuK\n",
+                "pages: %6zu/%6zu inuse bytes: %6zuK util: %3zu.%02zu%%\n",
                 ClassId, BlockSize, InUseBlocks, TotalBlocks, InUsePages,
-                AllocatedPagesCount, InUseBytes >> 10);
+                AllocatedPagesCount, InUseBytes >> 10, Integral, Fractional);
   }
 
   NOINLINE uptr releaseToOSMaybe(SizeClassInfo *Sci, uptr ClassId,
diff --git a/compiler-rt/lib/scudo/standalone/primary64.h b/compiler-rt/lib/scudo/standalone/primary64.h
index d1929ff7212f..9a642d23620e 100644
--- a/compiler-rt/lib/scudo/standalone/primary64.h
+++ b/compiler-rt/lib/scudo/standalone/primary64.h
@@ -1130,10 +1130,14 @@ private:
         AllocatedPagesCount - Recorder.getReleasedPagesCount();
     const uptr InUseBytes = InUsePages * PageSize;
 
+    uptr Integral;
+    uptr Fractional;
+    computePercentage(BlockSize * InUseBlocks, InUsePages * PageSize, &Integral,
+                      &Fractional);
     Str->append("  %02zu (%6zu): inuse/total blocks: %6zu/%6zu inuse/total "
-                "pages: %6zu/%6zu inuse bytes: %6zuK\n",
+                "pages: %6zu/%6zu inuse bytes: %6zuK util: %3zu.%02zu%%\n",
                 ClassId, BlockSize, InUseBlocks, TotalBlocks, InUsePages,
-                AllocatedPagesCount, InUseBytes >> 10);
+                AllocatedPagesCount, InUseBytes >> 10, Integral, Fractional);
   }
 
   NOINLINE uptr releaseToOSMaybe(RegionInfo *Region, uptr ClassId,
diff --git a/compiler-rt/lib/scudo/standalone/secondary.h b/compiler-rt/lib/scudo/standalone/secondary.h
index 8dc4c87fa7c6..f52a4188bcf3 100644
--- a/compiler-rt/lib/scudo/standalone/secondary.h
+++ b/compiler-rt/lib/scudo/standalone/secondary.h
@@ -155,20 +155,16 @@ public:
 
   void getStats(ScopedString *Str) {
     ScopedLock L(Mutex);
-    u32 Integral = 0;
-    u32 Fractional = 0;
-    if (CallsToRetrieve != 0) {
-      Integral = SuccessfulRetrieves * 100 / CallsToRetrieve;
-      Fractional = (((SuccessfulRetrieves * 100) % CallsToRetrieve) * 100 +
-                    CallsToRetrieve / 2) /
-                   CallsToRetrieve;
-    }
+    uptr Integral;
+    uptr Fractional;
+    computePercentage(SuccessfulRetrieves, CallsToRetrieve, &Integral,
+                      &Fractional);
     Str->append("Stats: MapAllocatorCache: EntriesCount: %d, "
                 "MaxEntriesCount: %u, MaxEntrySize: %zu\n",
                 EntriesCount, atomic_load_relaxed(&MaxEntriesCount),
                 atomic_load_relaxed(&MaxEntrySize));
     Str->append("Stats: CacheRetrievalStats: SuccessRate: %u/%u "
-                "(%u.%02u%%)\n",
+                "(%zu.%02zu%%)\n",
                 SuccessfulRetrieves, CallsToRetrieve, Integral, Fractional);
     for (CachedBlock Entry : Entries) {
       if (!Entry.isValid())
-- 
GitLab


From 62b21c6ced918c7fec97b557e3087e3ffdf71494 Mon Sep 17 00:00:00 2001
From: paperchalice <liujunchang97@outlook.com>
Date: Tue, 12 Dec 2023 09:00:44 +0800
Subject: [PATCH 202/349] [CodeGen] Port `JMCInstrumenter` to new pass manager
 (#75049)

---
 .../include/llvm/CodeGen/CodeGenPassBuilder.h |  1 +
 llvm/include/llvm/CodeGen/JMCInstrumenter.h   | 23 +++++++++++++++++++
 .../llvm/CodeGen/MachinePassRegistry.def      |  1 +
 llvm/lib/CodeGen/JMCInstrumenter.cpp          | 13 ++++++++---
 llvm/lib/Passes/PassBuilder.cpp               |  1 +
 llvm/lib/Passes/PassRegistry.def              |  1 +
 .../JustMyCode/jmc-instrument-elf.ll          |  3 ++-
 .../JustMyCode/jmc-instrument-x86.ll          |  3 ++-
 .../JustMyCode/jmc-instrument.ll              |  9 +++++---
 llvm/tools/opt/opt.cpp                        |  2 +-
 10 files changed, 48 insertions(+), 9 deletions(-)
 create mode 100644 llvm/include/llvm/CodeGen/JMCInstrumenter.h

diff --git a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
index bb139ef2eb35..4e704411270c 100644
--- a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
@@ -26,6 +26,7 @@
 #include "llvm/CodeGen/DwarfEHPrepare.h"
 #include "llvm/CodeGen/ExpandReductions.h"
 #include "llvm/CodeGen/InterleavedAccess.h"
+#include "llvm/CodeGen/JMCInstrumenter.h"
 #include "llvm/CodeGen/MachinePassManager.h"
 #include "llvm/CodeGen/PreISelIntrinsicLowering.h"
 #include "llvm/CodeGen/ReplaceWithVeclib.h"
diff --git a/llvm/include/llvm/CodeGen/JMCInstrumenter.h b/llvm/include/llvm/CodeGen/JMCInstrumenter.h
new file mode 100644
index 000000000000..addac1654826
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/JMCInstrumenter.h
@@ -0,0 +1,23 @@
+//===-- llvm/CodeGen/JMCInstrumenter------------------------ ----*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_JMCINSTRUMENTER_H
+#define LLVM_CODEGEN_JMCINSTRUMENTER_H
+
+#include "llvm/IR/PassManager.h"
+
+namespace llvm {
+
+class JMCInstrumenterPass : public PassInfoMixin<JMCInstrumenterPass> {
+public:
+  PreservedAnalyses run(Module &M, ModuleAnalysisManager &MAM);
+};
+
+} // namespace llvm
+
+#endif // LLVM_CODEGEN_JMCINSTRUMENTER_H
diff --git a/llvm/include/llvm/CodeGen/MachinePassRegistry.def b/llvm/include/llvm/CodeGen/MachinePassRegistry.def
index e6e979a4582c..6b720736c3e5 100644
--- a/llvm/include/llvm/CodeGen/MachinePassRegistry.def
+++ b/llvm/include/llvm/CodeGen/MachinePassRegistry.def
@@ -23,6 +23,7 @@ MODULE_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis, (PIC))
 #define MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR)
 #endif
 MODULE_PASS("pre-isel-intrinsic-lowering", PreISelIntrinsicLoweringPass, ())
+MODULE_PASS("jmc-instrumenter", JMCInstrumenterPass, ())
 #undef MODULE_PASS
 
 #ifndef FUNCTION_ANALYSIS
diff --git a/llvm/lib/CodeGen/JMCInstrumenter.cpp b/llvm/lib/CodeGen/JMCInstrumenter.cpp
index a1f0a5040664..62a381918875 100644
--- a/llvm/lib/CodeGen/JMCInstrumenter.cpp
+++ b/llvm/lib/CodeGen/JMCInstrumenter.cpp
@@ -20,6 +20,7 @@
 //   weak symbol.
 //===----------------------------------------------------------------------===//
 
+#include "llvm/CodeGen/JMCInstrumenter.h"
 #include "llvm/ADT/SmallString.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/CodeGen/Passes.h"
@@ -39,19 +40,25 @@
 
 using namespace llvm;
 
-#define DEBUG_TYPE "jmc-instrument"
+#define DEBUG_TYPE "jmc-instrumenter"
 
+static bool runImpl(Module &M);
 namespace {
 struct JMCInstrumenter : public ModulePass {
   static char ID;
   JMCInstrumenter() : ModulePass(ID) {
     initializeJMCInstrumenterPass(*PassRegistry::getPassRegistry());
   }
-  bool runOnModule(Module &M) override;
+  bool runOnModule(Module &M) override { return runImpl(M); }
 };
 char JMCInstrumenter::ID = 0;
 } // namespace
 
+PreservedAnalyses JMCInstrumenterPass::run(Module &M, ModuleAnalysisManager &) {
+  bool Changed = runImpl(M);
+  return Changed ? PreservedAnalyses::none() : PreservedAnalyses::all();
+}
+
 INITIALIZE_PASS(
     JMCInstrumenter, DEBUG_TYPE,
     "Instrument function entry with call to __CheckForDebuggerJustMyCode",
@@ -143,7 +150,7 @@ Function *createDefaultCheckFunction(Module &M, bool UseX86FastCall) {
 }
 } // namespace
 
-bool JMCInstrumenter::runOnModule(Module &M) {
+bool runImpl(Module &M) {
   bool Changed = false;
   LLVMContext &Ctx = M.getContext();
   Triple ModuleTriple(M.getTargetTriple());
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index f26450e94187..0608e1b2201b 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -78,6 +78,7 @@
 #include "llvm/CodeGen/ExpandLargeFpConvert.h"
 #include "llvm/CodeGen/HardwareLoops.h"
 #include "llvm/CodeGen/InterleavedAccess.h"
+#include "llvm/CodeGen/JMCInstrumenter.h"
 #include "llvm/CodeGen/SafeStack.h"
 #include "llvm/CodeGen/TypePromotion.h"
 #include "llvm/CodeGen/WasmEHPrepare.h"
diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def
index 56449906eb65..d49e35db8722 100644
--- a/llvm/lib/Passes/PassRegistry.def
+++ b/llvm/lib/Passes/PassRegistry.def
@@ -81,6 +81,7 @@ MODULE_PASS("instrprof", InstrProfilingLoweringPass())
 MODULE_PASS("internalize", InternalizePass())
 MODULE_PASS("invalidate<all>", InvalidateAllAnalysesPass())
 MODULE_PASS("iroutliner", IROutlinerPass())
+MODULE_PASS("jmc-instrumenter", JMCInstrumenterPass())
 MODULE_PASS("lower-global-dtors", LowerGlobalDtorsPass())
 MODULE_PASS("lower-ifunc", LowerIFuncPass())
 MODULE_PASS("lowertypetests", LowerTypeTestsPass())
diff --git a/llvm/test/Instrumentation/JustMyCode/jmc-instrument-elf.ll b/llvm/test/Instrumentation/JustMyCode/jmc-instrument-elf.ll
index 12ca42703732..f2889db2b56d 100644
--- a/llvm/test/Instrumentation/JustMyCode/jmc-instrument-elf.ll
+++ b/llvm/test/Instrumentation/JustMyCode/jmc-instrument-elf.ll
@@ -1,4 +1,5 @@
-; RUN: opt -jmc-instrument -mtriple=x86_64-unknown-linux-gnu  -S < %s | FileCheck %s
+; RUN: opt -jmc-instrumenter -mtriple=x86_64-unknown-linux-gnu  -S < %s | FileCheck %s
+; RUN: opt -passes=jmc-instrumenter -mtriple=x86_64-unknown-linux-gnu  -S < %s | FileCheck %s
 
 ; CHECK: @"__7DF23CF5_x@c" = internal unnamed_addr global i8 1, section ".data.just.my.code", align 1, !dbg !0
 ; CHECK: @"__A8764FDD_x@c" = internal unnamed_addr global i8 1, section ".data.just.my.code", align 1, !dbg !5
diff --git a/llvm/test/Instrumentation/JustMyCode/jmc-instrument-x86.ll b/llvm/test/Instrumentation/JustMyCode/jmc-instrument-x86.ll
index c884395bea49..8a2318eee5e5 100644
--- a/llvm/test/Instrumentation/JustMyCode/jmc-instrument-x86.ll
+++ b/llvm/test/Instrumentation/JustMyCode/jmc-instrument-x86.ll
@@ -1,4 +1,5 @@
-; RUN: opt -jmc-instrument -S < %s | FileCheck %s
+; RUN: opt -jmc-instrumenter -S < %s | FileCheck %s
+; RUN: opt -passes=jmc-instrumenter -S < %s | FileCheck %s
 
 ; CHECK: $_JustMyCode_Default = comdat any
 
diff --git a/llvm/test/Instrumentation/JustMyCode/jmc-instrument.ll b/llvm/test/Instrumentation/JustMyCode/jmc-instrument.ll
index 098ff1b2a958..acbcc2917ae9 100644
--- a/llvm/test/Instrumentation/JustMyCode/jmc-instrument.ll
+++ b/llvm/test/Instrumentation/JustMyCode/jmc-instrument.ll
@@ -1,6 +1,9 @@
-; RUN: opt -jmc-instrument -mtriple=x86_64-pc-windows-msvc  -S < %s | FileCheck %s
-; RUN: opt -jmc-instrument -mtriple=aarch64-pc-windows-msvc -S < %s | FileCheck %s
-; RUN: opt -jmc-instrument -mtriple=arm-pc-windows-msvc     -S < %s | FileCheck %s
+; RUN: opt -jmc-instrumenter -mtriple=x86_64-pc-windows-msvc  -S < %s | FileCheck %s
+; RUN: opt -jmc-instrumenter -mtriple=aarch64-pc-windows-msvc -S < %s | FileCheck %s
+; RUN: opt -jmc-instrumenter -mtriple=arm-pc-windows-msvc     -S < %s | FileCheck %s
+; RUN: opt -passes=jmc-instrumenter -mtriple=x86_64-pc-windows-msvc  -S < %s | FileCheck %s
+; RUN: opt -passes=jmc-instrumenter -mtriple=aarch64-pc-windows-msvc -S < %s | FileCheck %s
+; RUN: opt -passes=jmc-instrumenter -mtriple=arm-pc-windows-msvc     -S < %s | FileCheck %s
 
 ; CHECK: $__JustMyCode_Default = comdat any
 
diff --git a/llvm/tools/opt/opt.cpp b/llvm/tools/opt/opt.cpp
index 50b36dc74267..8d26580d8f38 100644
--- a/llvm/tools/opt/opt.cpp
+++ b/llvm/tools/opt/opt.cpp
@@ -364,7 +364,7 @@ static bool shouldPinPassToLegacyPM(StringRef Pass) {
       "polyhedral-info",
       "print-polyhedral-info",
       "replace-with-veclib",
-      "jmc-instrument",
+      "jmc-instrumenter",
       "dot-regions",
       "dot-regions-only",
       "view-regions",
-- 
GitLab


From 4d8bf6ea7fa8f68f46b6f0b6d0ae7d114904914a Mon Sep 17 00:00:00 2001
From: paperchalice <liujunchang97@outlook.com>
Date: Tue, 12 Dec 2023 09:22:01 +0800
Subject: [PATCH 203/349] [CodeGen][GC] Remove `GCInfoPrinter` (#75033)

This pass is broken and looks like no one uses it for the last 15+ years.

```c++
bool Printer::runOnFunction(Function &F) {
  if (F.hasGC())
    return false;

  GCFunctionInfo *FD = &getAnalysis<GCModuleInfo>().getFunctionInfo(F);
```
```c++
GCFunctionInfo &GCModuleInfo::getFunctionInfo(const Function &F) {
  assert(!F.isDeclaration() && "Can only get GCFunctionInfo for a definition!");
  assert(F.hasGC()); // Equivalent to `assert(false);` when called by `Printer::runOnFunction`
```

See also #74972.
---
 .../llvm/CodeGen/MachinePassRegistry.def      |  1 -
 llvm/include/llvm/CodeGen/Passes.h            |  4 --
 .../include/llvm/Target/CGPassBuilderOption.h |  1 -
 llvm/lib/CodeGen/GCMetadata.cpp               | 71 -------------------
 llvm/lib/CodeGen/TargetPassConfig.cpp         | 13 ++--
 5 files changed, 4 insertions(+), 86 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/MachinePassRegistry.def b/llvm/include/llvm/CodeGen/MachinePassRegistry.def
index 6b720736c3e5..d92ff9b858ee 100644
--- a/llvm/include/llvm/CodeGen/MachinePassRegistry.def
+++ b/llvm/include/llvm/CodeGen/MachinePassRegistry.def
@@ -126,7 +126,6 @@ DUMMY_FUNCTION_PASS("cfguard-check", CFGuardCheckPass, ())
 DUMMY_FUNCTION_PASS("cfguard-dispatch", CFGuardDispatchPass, ())
 DUMMY_FUNCTION_PASS("codegenprepare", CodeGenPreparePass, ())
 DUMMY_FUNCTION_PASS("expandmemcmp", ExpandMemCmpPass, ())
-DUMMY_FUNCTION_PASS("gc-info-printer", GCInfoPrinterPass, ())
 DUMMY_FUNCTION_PASS("gc-lowering", GCLoweringPass, ())
 DUMMY_FUNCTION_PASS("indirectbr-expand", IndirectBrExpandPass, ())
 DUMMY_FUNCTION_PASS("select-optimize", SelectOptimizePass, ())
diff --git a/llvm/include/llvm/CodeGen/Passes.h b/llvm/include/llvm/CodeGen/Passes.h
index 712048017bca..80def6dfef49 100644
--- a/llvm/include/llvm/CodeGen/Passes.h
+++ b/llvm/include/llvm/CodeGen/Passes.h
@@ -324,10 +324,6 @@ namespace llvm {
   /// branch folding).
   extern char &GCMachineCodeAnalysisID;
 
-  /// Creates a pass to print GC metadata.
-  ///
-  FunctionPass *createGCInfoPrinter(raw_ostream &OS);
-
   /// MachineCSE - This pass performs global CSE on machine instructions.
   extern char &MachineCSEID;
 
diff --git a/llvm/include/llvm/Target/CGPassBuilderOption.h b/llvm/include/llvm/Target/CGPassBuilderOption.h
index 85abddbb2292..72cb1b383da4 100644
--- a/llvm/include/llvm/Target/CGPassBuilderOption.h
+++ b/llvm/include/llvm/Target/CGPassBuilderOption.h
@@ -42,7 +42,6 @@ struct CGPassBuilderOption {
   bool DisableConstantHoisting = false;
   bool DisableSelectOptimize = true;
   bool PrintISelInput = false;
-  bool PrintGCInfo = false;
   bool RequiresCodeGenSCCOrder = false;
 
   RunOutliner EnableMachineOutliner = RunOutliner::TargetDefault;
diff --git a/llvm/lib/CodeGen/GCMetadata.cpp b/llvm/lib/CodeGen/GCMetadata.cpp
index 4d27143c5298..49e03b4b132c 100644
--- a/llvm/lib/CodeGen/GCMetadata.cpp
+++ b/llvm/lib/CodeGen/GCMetadata.cpp
@@ -24,25 +24,6 @@
 
 using namespace llvm;
 
-namespace {
-
-class Printer : public FunctionPass {
-  static char ID;
-
-  raw_ostream &OS;
-
-public:
-  explicit Printer(raw_ostream &OS) : FunctionPass(ID), OS(OS) {}
-
-  StringRef getPassName() const override;
-  void getAnalysisUsage(AnalysisUsage &AU) const override;
-
-  bool runOnFunction(Function &F) override;
-  bool doFinalization(Module &M) override;
-};
-
-} // end anonymous namespace
-
 INITIALIZE_PASS(GCModuleInfo, "collector-metadata",
                 "Create Garbage Collector Module Metadata", false, false)
 
@@ -84,58 +65,6 @@ void GCModuleInfo::clear() {
 
 // -----------------------------------------------------------------------------
 
-char Printer::ID = 0;
-
-FunctionPass *llvm::createGCInfoPrinter(raw_ostream &OS) {
-  return new Printer(OS);
-}
-
-StringRef Printer::getPassName() const {
-  return "Print Garbage Collector Information";
-}
-
-void Printer::getAnalysisUsage(AnalysisUsage &AU) const {
-  FunctionPass::getAnalysisUsage(AU);
-  AU.setPreservesAll();
-  AU.addRequired<GCModuleInfo>();
-}
-
-bool Printer::runOnFunction(Function &F) {
-  if (F.hasGC())
-    return false;
-
-  GCFunctionInfo *FD = &getAnalysis<GCModuleInfo>().getFunctionInfo(F);
-
-  OS << "GC roots for " << FD->getFunction().getName() << ":\n";
-  for (GCFunctionInfo::roots_iterator RI = FD->roots_begin(),
-                                      RE = FD->roots_end();
-       RI != RE; ++RI)
-    OS << "\t" << RI->Num << "\t" << RI->StackOffset << "[sp]\n";
-
-  OS << "GC safe points for " << FD->getFunction().getName() << ":\n";
-  for (GCFunctionInfo::iterator PI = FD->begin(), PE = FD->end(); PI != PE;
-       ++PI) {
-
-    OS << "\t" << PI->Label->getName() << ": " << "post-call"
-       << ", live = {";
-
-    ListSeparator LS(",");
-    for (const GCRoot &R : make_range(FD->live_begin(PI), FD->live_end(PI)))
-      OS << LS << " " << R.Num;
-
-    OS << " }\n";
-  }
-
-  return false;
-}
-
-bool Printer::doFinalization(Module &M) {
-  GCModuleInfo *GMI = getAnalysisIfAvailable<GCModuleInfo>();
-  assert(GMI && "Printer didn't require GCModuleInfo?!");
-  GMI->clear();
-  return false;
-}
-
 GCStrategy *GCModuleInfo::getGCStrategy(const StringRef Name) {
   // TODO: Arguably, just doing a linear search would be faster for small N
   auto NMI = GCStrategyMap.find(Name);
diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp
index 1f7c949cd603..b82fe5fb99f9 100644
--- a/llvm/lib/CodeGen/TargetPassConfig.cpp
+++ b/llvm/lib/CodeGen/TargetPassConfig.cpp
@@ -113,10 +113,9 @@ static cl::opt<bool> DisableMergeICmps("disable-mergeicmps",
     cl::init(false), cl::Hidden);
 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
     cl::desc("Print LLVM IR produced by the loop-reduce pass"));
-static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
-    cl::desc("Print LLVM IR input to isel pass"));
-static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
-    cl::desc("Dump garbage collector data"));
+static cl::opt<bool>
+    PrintISelInput("print-isel-input", cl::Hidden,
+                   cl::desc("Print LLVM IR input to isel pass"));
 static cl::opt<cl::boolOrDefault>
     VerifyMachineCode("verify-machineinstrs", cl::Hidden,
                       cl::desc("Verify generated machine code"));
@@ -491,7 +490,6 @@ CGPassBuilderOption llvm::getCGPassBuilderOption() {
   SET_BOOLEAN_OPTION(DisableSelectOptimize)
   SET_BOOLEAN_OPTION(PrintLSR)
   SET_BOOLEAN_OPTION(PrintISelInput)
-  SET_BOOLEAN_OPTION(PrintGCInfo)
 
   return Opt;
 }
@@ -1211,10 +1209,7 @@ void TargetPassConfig::addMachinePasses() {
   }
 
   // GC
-  if (addGCPasses()) {
-    if (PrintGCInfo)
-      addPass(createGCInfoPrinter(dbgs()));
-  }
+  addGCPasses();
 
   // Basic block placement.
   if (getOptLevel() != CodeGenOptLevel::None)
-- 
GitLab


From cee6918d876cb1650c4fd232e8da0e726061653c Mon Sep 17 00:00:00 2001
From: Johannes Doerfert <johannes@jdoerfert.de>
Date: Tue, 5 Dec 2023 08:41:32 -0800
Subject: [PATCH 204/349] [OpenMP][NFC] Move api.cpp to OpenMP/API.cpp

---
 .../include/OpenMP/InternalTypes.h            |  72 ++++++++++++
 openmp/libomptarget/src/CMakeLists.txt        |   2 +-
 .../src/{api.cpp => OpenMP/API.cpp}           |  33 +++++-
 openmp/libomptarget/src/private.h             | 109 ------------------
 4 files changed, 105 insertions(+), 111 deletions(-)
 rename openmp/libomptarget/src/{api.cpp => OpenMP/API.cpp} (93%)

diff --git a/openmp/libomptarget/include/OpenMP/InternalTypes.h b/openmp/libomptarget/include/OpenMP/InternalTypes.h
index fd5836e973ae..bd84c38fb201 100644
--- a/openmp/libomptarget/include/OpenMP/InternalTypes.h
+++ b/openmp/libomptarget/include/OpenMP/InternalTypes.h
@@ -75,6 +75,78 @@ bool __kmpc_omp_has_task_team(int32_t gtid) __attribute__((weak));
 void **__kmpc_omp_get_target_async_handle_ptr(int32_t gtid)
     __attribute__((weak));
 
+/**
+ * The argument set that is passed from asynchronous memory copy to block
+ * version of memory copy invoked in helper task
+ */
+struct TargetMemcpyArgsTy {
+  /**
+   * Common attribuutes
+   */
+  void *Dst;
+  const void *Src;
+  int DstDevice;
+  int SrcDevice;
+
+  /**
+   * The flag that denotes single dimensional or rectangle dimensional copy
+   */
+  bool IsRectMemcpy;
+
+  /**
+   * Arguments for single dimensional copy
+   */
+  size_t Length;
+  size_t DstOffset;
+  size_t SrcOffset;
+
+  /**
+   * Arguments for rectangle dimensional copy
+   */
+  size_t ElementSize;
+  int NumDims;
+  const size_t *Volume;
+  const size_t *DstOffsets;
+  const size_t *SrcOffsets;
+  const size_t *DstDimensions;
+  const size_t *SrcDimensions;
+
+  /**
+   * Constructor for single dimensional copy
+   */
+  TargetMemcpyArgsTy(void *Dst, const void *Src, size_t Length,
+                     size_t DstOffset, size_t SrcOffset, int DstDevice,
+                     int SrcDevice)
+      : Dst(Dst), Src(Src), DstDevice(DstDevice), SrcDevice(SrcDevice),
+        IsRectMemcpy(false), Length(Length), DstOffset(DstOffset),
+        SrcOffset(SrcOffset), ElementSize(0), NumDims(0), Volume(0),
+        DstOffsets(0), SrcOffsets(0), DstDimensions(0), SrcDimensions(0){};
+
+  /**
+   * Constructor for rectangle dimensional copy
+   */
+  TargetMemcpyArgsTy(void *Dst, const void *Src, size_t ElementSize,
+                     int NumDims, const size_t *Volume,
+                     const size_t *DstOffsets, const size_t *SrcOffsets,
+                     const size_t *DstDimensions, const size_t *SrcDimensions,
+                     int DstDevice, int SrcDevice)
+      : Dst(Dst), Src(Src), DstDevice(DstDevice), SrcDevice(SrcDevice),
+        IsRectMemcpy(true), Length(0), DstOffset(0), SrcOffset(0),
+        ElementSize(ElementSize), NumDims(NumDims), Volume(Volume),
+        DstOffsets(DstOffsets), SrcOffsets(SrcOffsets),
+        DstDimensions(DstDimensions), SrcDimensions(SrcDimensions){};
+};
+
+struct TargetMemsetArgsTy {
+  // Common attributes of a memset operation
+  void *Ptr;
+  int C;
+  size_t N;
+  int DeviceNum;
+
+  // no constructors defined, because this is a PoD
+};
+
 } // extern "C"
 
 #endif // OMPTARGET_OPENMP_INTERNAL_TYPES_H
diff --git a/openmp/libomptarget/src/CMakeLists.txt b/openmp/libomptarget/src/CMakeLists.txt
index 429a670be849..42674e2d9daa 100644
--- a/openmp/libomptarget/src/CMakeLists.txt
+++ b/openmp/libomptarget/src/CMakeLists.txt
@@ -15,7 +15,6 @@ libomptarget_say("Building offloading runtime library libomptarget.")
 add_llvm_library(omptarget
   SHARED
 
-  api.cpp
   device.cpp
   interface.cpp
   omptarget.cpp
@@ -24,6 +23,7 @@ add_llvm_library(omptarget
   PluginManager.cpp
   DeviceImage.cpp
 
+  OpenMP/API.cpp
   OpenMP/Mapping.cpp
   OpenMP/InteropAPI.cpp
   OpenMP/OMPT/Callback.cpp
diff --git a/openmp/libomptarget/src/api.cpp b/openmp/libomptarget/src/OpenMP/API.cpp
similarity index 93%
rename from openmp/libomptarget/src/api.cpp
rename to openmp/libomptarget/src/OpenMP/API.cpp
index 0341e0c75464..b73315f2b77a 100644
--- a/openmp/libomptarget/src/api.cpp
+++ b/openmp/libomptarget/src/OpenMP/API.cpp
@@ -13,9 +13,9 @@
 #include "PluginManager.h"
 #include "device.h"
 #include "omptarget.h"
-#include "private.h"
 #include "rtl.h"
 
+#include "OpenMP/InternalTypes.h"
 #include "OpenMP/omp.h"
 #include "Shared/Profile.h"
 
@@ -26,6 +26,37 @@
 #include <cstring>
 #include <mutex>
 
+void *targetAllocExplicit(size_t Size, int DeviceNum, int Kind,
+                          const char *Name);
+void targetFreeExplicit(void *DevicePtr, int DeviceNum, int Kind,
+                        const char *Name);
+void *targetLockExplicit(void *HostPtr, size_t Size, int DeviceNum,
+                         const char *Name);
+void targetUnlockExplicit(void *HostPtr, int DeviceNum, const char *Name);
+
+// Implemented in libomp, they are called from within __tgt_* functions.
+extern "C" {
+int __kmpc_get_target_offload(void) __attribute__((weak));
+kmp_task_t *__kmpc_omp_task_alloc(ident_t *loc_ref, int32_t gtid, int32_t flags,
+                                  size_t sizeof_kmp_task_t,
+                                  size_t sizeof_shareds,
+                                  kmp_routine_entry_t task_entry)
+    __attribute__((weak));
+
+kmp_task_t *
+__kmpc_omp_target_task_alloc(ident_t *loc_ref, int32_t gtid, int32_t flags,
+                             size_t sizeof_kmp_task_t, size_t sizeof_shareds,
+                             kmp_routine_entry_t task_entry, int64_t device_id)
+    __attribute__((weak));
+
+int32_t __kmpc_omp_task_with_deps(ident_t *loc_ref, int32_t gtid,
+                                  kmp_task_t *new_task, int32_t ndeps,
+                                  kmp_depend_info_t *dep_list,
+                                  int32_t ndeps_noalias,
+                                  kmp_depend_info_t *noalias_dep_list)
+    __attribute__((weak));
+}
+
 EXTERN int omp_get_num_devices(void) {
   TIMESCOPE();
   size_t NumDevices = PM->getNumDevices();
diff --git a/openmp/libomptarget/src/private.h b/openmp/libomptarget/src/private.h
index 607c2a0dd86a..d569f2af5433 100644
--- a/openmp/libomptarget/src/private.h
+++ b/openmp/libomptarget/src/private.h
@@ -38,115 +38,6 @@ extern int target_replay(ident_t *Loc, DeviceTy &Device, void *HostPtr,
 
 extern void handleTargetOutcome(bool Success, ident_t *Loc);
 extern bool checkDeviceAndCtors(int64_t &DeviceID, ident_t *Loc);
-extern void *targetAllocExplicit(size_t Size, int DeviceNum, int Kind,
-                                 const char *Name);
-extern void targetFreeExplicit(void *DevicePtr, int DeviceNum, int Kind,
-                               const char *Name);
-extern void *targetLockExplicit(void *HostPtr, size_t Size, int DeviceNum,
-                                const char *Name);
-extern void targetUnlockExplicit(void *HostPtr, int DeviceNum,
-                                 const char *Name);
-
-// Implemented in libomp, they are called from within __tgt_* functions.
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-int __kmpc_get_target_offload(void) __attribute__((weak));
-kmp_task_t *__kmpc_omp_task_alloc(ident_t *loc_ref, int32_t gtid, int32_t flags,
-                                  size_t sizeof_kmp_task_t,
-                                  size_t sizeof_shareds,
-                                  kmp_routine_entry_t task_entry)
-    __attribute__((weak));
-
-kmp_task_t *
-__kmpc_omp_target_task_alloc(ident_t *loc_ref, int32_t gtid, int32_t flags,
-                             size_t sizeof_kmp_task_t, size_t sizeof_shareds,
-                             kmp_routine_entry_t task_entry, int64_t device_id)
-    __attribute__((weak));
-
-int32_t __kmpc_omp_task_with_deps(ident_t *loc_ref, int32_t gtid,
-                                  kmp_task_t *new_task, int32_t ndeps,
-                                  kmp_depend_info_t *dep_list,
-                                  int32_t ndeps_noalias,
-                                  kmp_depend_info_t *noalias_dep_list)
-    __attribute__((weak));
-
-/**
- * The argument set that is passed from asynchronous memory copy to block
- * version of memory copy invoked in helper task
- */
-struct TargetMemcpyArgsTy {
-  /**
-   * Common attribuutes
-   */
-  void *Dst;
-  const void *Src;
-  int DstDevice;
-  int SrcDevice;
-
-  /**
-   * The flag that denotes single dimensional or rectangle dimensional copy
-   */
-  bool IsRectMemcpy;
-
-  /**
-   * Arguments for single dimensional copy
-   */
-  size_t Length;
-  size_t DstOffset;
-  size_t SrcOffset;
-
-  /**
-   * Arguments for rectangle dimensional copy
-   */
-  size_t ElementSize;
-  int NumDims;
-  const size_t *Volume;
-  const size_t *DstOffsets;
-  const size_t *SrcOffsets;
-  const size_t *DstDimensions;
-  const size_t *SrcDimensions;
-
-  /**
-   * Constructor for single dimensional copy
-   */
-  TargetMemcpyArgsTy(void *Dst, const void *Src, size_t Length,
-                     size_t DstOffset, size_t SrcOffset, int DstDevice,
-                     int SrcDevice)
-      : Dst(Dst), Src(Src), DstDevice(DstDevice), SrcDevice(SrcDevice),
-        IsRectMemcpy(false), Length(Length), DstOffset(DstOffset),
-        SrcOffset(SrcOffset), ElementSize(0), NumDims(0), Volume(0),
-        DstOffsets(0), SrcOffsets(0), DstDimensions(0), SrcDimensions(0){};
-
-  /**
-   * Constructor for rectangle dimensional copy
-   */
-  TargetMemcpyArgsTy(void *Dst, const void *Src, size_t ElementSize,
-                     int NumDims, const size_t *Volume,
-                     const size_t *DstOffsets, const size_t *SrcOffsets,
-                     const size_t *DstDimensions, const size_t *SrcDimensions,
-                     int DstDevice, int SrcDevice)
-      : Dst(Dst), Src(Src), DstDevice(DstDevice), SrcDevice(SrcDevice),
-        IsRectMemcpy(true), Length(0), DstOffset(0), SrcOffset(0),
-        ElementSize(ElementSize), NumDims(NumDims), Volume(Volume),
-        DstOffsets(DstOffsets), SrcOffsets(SrcOffsets),
-        DstDimensions(DstDimensions), SrcDimensions(SrcDimensions){};
-};
-
-struct TargetMemsetArgsTy {
-  // Common attributes of a memset operation
-  void *Ptr;
-  int C;
-  size_t N;
-  int DeviceNum;
-
-  // no constructors defined, because this is a PoD
-};
-
-#ifdef __cplusplus
-}
-#endif
 
 ////////////////////////////////////////////////////////////////////////////////
 /// Print out the names and properties of the arguments to each kernel
-- 
GitLab


From f0ccaeecd27406937d6f840a9e72ccd14eae4bb5 Mon Sep 17 00:00:00 2001
From: Johannes Doerfert <johannes@jdoerfert.de>
Date: Tue, 5 Dec 2023 09:01:32 -0800
Subject: [PATCH 205/349] [OpenMP][NFC] Move rtl.cpp to OffloadRTL.cpp

---
 openmp/libomptarget/src/CMakeLists.txt        |  2 +-
 .../src/{rtl.cpp => OffloadRTL.cpp}           | 28 ++++---------------
 2 files changed, 6 insertions(+), 24 deletions(-)
 rename openmp/libomptarget/src/{rtl.cpp => OffloadRTL.cpp} (62%)

diff --git a/openmp/libomptarget/src/CMakeLists.txt b/openmp/libomptarget/src/CMakeLists.txt
index 42674e2d9daa..1a0e26f104be 100644
--- a/openmp/libomptarget/src/CMakeLists.txt
+++ b/openmp/libomptarget/src/CMakeLists.txt
@@ -18,7 +18,7 @@ add_llvm_library(omptarget
   device.cpp
   interface.cpp
   omptarget.cpp
-  rtl.cpp
+  OffloadRTL.cpp
   LegacyAPI.cpp
   PluginManager.cpp
   DeviceImage.cpp
diff --git a/openmp/libomptarget/src/rtl.cpp b/openmp/libomptarget/src/OffloadRTL.cpp
similarity index 62%
rename from openmp/libomptarget/src/rtl.cpp
rename to openmp/libomptarget/src/OffloadRTL.cpp
index 5eb1c553df49..061b053c68cc 100644
--- a/openmp/libomptarget/src/rtl.cpp
+++ b/openmp/libomptarget/src/OffloadRTL.cpp
@@ -6,46 +6,28 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// Functionality for handling RTL plugins.
+// Initialization and tear down of the offload runtime.
 //
 //===----------------------------------------------------------------------===//
 
-#include "llvm/Object/OffloadBinary.h"
-
-#include "DeviceImage.h"
 #include "OpenMP/OMPT/Callback.h"
 #include "PluginManager.h"
-#include "device.h"
-#include "private.h"
-#include "rtl.h"
 
 #include "Shared/Debug.h"
 #include "Shared/Profile.h"
-#include "Shared/Utils.h"
-
-#include <cassert>
-#include <cstdlib>
-#include <cstring>
-#include <memory>
-#include <mutex>
-#include <string>
-
-using namespace llvm;
-using namespace llvm::sys;
-using namespace llvm::omp::target;
 
 #ifdef OMPT_SUPPORT
-extern void ompt::connectLibrary();
+extern void llvm::omp::target::ompt::connectLibrary();
 #endif
 
 __attribute__((constructor(101))) void init() {
-  DP("Init target library!\n");
+  DP("Init offload library!\n");
 
   PM = new PluginManager();
 
 #ifdef OMPT_SUPPORT
   // Initialize OMPT first
-  ompt::connectLibrary();
+  llvm::omp::target::ompt::connectLibrary();
 #endif
 
   PM->init();
@@ -55,6 +37,6 @@ __attribute__((constructor(101))) void init() {
 }
 
 __attribute__((destructor(101))) void deinit() {
-  DP("Deinit target library!\n");
+  DP("Deinit offload library!\n");
   delete PM;
 }
-- 
GitLab


From 2ada7bb68bef36cd228d1c236e96932efb18daaa Mon Sep 17 00:00:00 2001
From: Johannes Doerfert <johannes@jdoerfert.de>
Date: Tue, 5 Dec 2023 10:08:47 -0800
Subject: [PATCH 206/349] [OpenMP][NFCI] Remove effectively unused mutex

The only use was already guarded by a different lock in the caller of
loadBinary.
---
 openmp/libomptarget/include/PluginManager.h | 5 -----
 openmp/libomptarget/src/device.cpp          | 1 -
 openmp/libomptarget/src/interface.cpp       | 5 -----
 3 files changed, 11 deletions(-)

diff --git a/openmp/libomptarget/include/PluginManager.h b/openmp/libomptarget/include/PluginManager.h
index 0b0974709b52..a0499c37504c 100644
--- a/openmp/libomptarget/include/PluginManager.h
+++ b/openmp/libomptarget/include/PluginManager.h
@@ -82,11 +82,6 @@ struct PluginAdaptorTy {
 
   llvm::DenseSet<const __tgt_device_image *> UsedImages;
 
-  // Mutex for thread-safety when calling RTL interface functions.
-  // It is easier to enforce thread-safety at the libomptarget level,
-  // so that developers of new RTLs do not have to worry about it.
-  std::mutex Mtx;
-
 private:
   /// Number of devices the underling plugins sees.
   int32_t NumberOfPluginDevices = -1;
diff --git a/openmp/libomptarget/src/device.cpp b/openmp/libomptarget/src/device.cpp
index 1302c4e3d917..01fc32328876 100644
--- a/openmp/libomptarget/src/device.cpp
+++ b/openmp/libomptarget/src/device.cpp
@@ -561,7 +561,6 @@ llvm::Error DeviceTy::init() {
 
 // Load binary to device.
 __tgt_target_table *DeviceTy::loadBinary(__tgt_device_image *Img) {
-  std::lock_guard<decltype(RTL->Mtx)> LG(RTL->Mtx);
   return RTL->load_binary(RTLDeviceID, Img);
 }
 
diff --git a/openmp/libomptarget/src/interface.cpp b/openmp/libomptarget/src/interface.cpp
index d92f40ce1d14..d9e87640161f 100644
--- a/openmp/libomptarget/src/interface.cpp
+++ b/openmp/libomptarget/src/interface.cpp
@@ -14,10 +14,7 @@
 #include "OpenMP/OMPT/Interface.h"
 #include "OpenMP/OMPT/Callback.h"
 #include "PluginManager.h"
-#include "device.h"
-#include "omptarget.h"
 #include "private.h"
-#include "rtl.h"
 
 #include "Shared/EnvironmentVar.h"
 #include "Shared/Profile.h"
@@ -28,8 +25,6 @@
 #include <cstdint>
 #include <cstdio>
 #include <cstdlib>
-#include <mutex>
-#include <type_traits>
 
 #ifdef OMPT_SUPPORT
 using namespace llvm::omp::target::ompt;
-- 
GitLab


From 5dd1fc700857eb46882c7e27cd8835ef4fee1f22 Mon Sep 17 00:00:00 2001
From: Johannes Doerfert <johannes@jdoerfert.de>
Date: Tue, 5 Dec 2023 14:33:16 -0800
Subject: [PATCH 207/349] [OpenMP][NFC] Improve profiling for the offload
 runtime

---
 openmp/libomptarget/include/Shared/Profile.h | 2 +-
 openmp/libomptarget/src/OffloadRTL.cpp       | 4 +++-
 openmp/libomptarget/src/PluginManager.cpp    | 4 ++++
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/openmp/libomptarget/include/Shared/Profile.h b/openmp/libomptarget/include/Shared/Profile.h
index 316b0c3086d0..19ca0cf22751 100644
--- a/openmp/libomptarget/include/Shared/Profile.h
+++ b/openmp/libomptarget/include/Shared/Profile.h
@@ -75,7 +75,7 @@ public:
 };
 
 /// Time spend in the current scope, assigned to the function name.
-#define TIMESCOPE() llvm::TimeTraceScope TimeScope(__FUNCTION__)
+#define TIMESCOPE() llvm::TimeTraceScope TimeScope(__PRETTY_FUNCTION__)
 
 /// Time spend in the current scope, assigned to the function name and source
 /// info.
diff --git a/openmp/libomptarget/src/OffloadRTL.cpp b/openmp/libomptarget/src/OffloadRTL.cpp
index 061b053c68cc..86ef0d5bc91c 100644
--- a/openmp/libomptarget/src/OffloadRTL.cpp
+++ b/openmp/libomptarget/src/OffloadRTL.cpp
@@ -21,6 +21,9 @@ extern void llvm::omp::target::ompt::connectLibrary();
 #endif
 
 __attribute__((constructor(101))) void init() {
+  Profiler::get();
+  TIMESCOPE();
+
   DP("Init offload library!\n");
 
   PM = new PluginManager();
@@ -32,7 +35,6 @@ __attribute__((constructor(101))) void init() {
 
   PM->init();
 
-  Profiler::get();
   PM->registerDelayedLibraries();
 }
 
diff --git a/openmp/libomptarget/src/PluginManager.cpp b/openmp/libomptarget/src/PluginManager.cpp
index 16e04dde923d..17787284441c 100644
--- a/openmp/libomptarget/src/PluginManager.cpp
+++ b/openmp/libomptarget/src/PluginManager.cpp
@@ -12,6 +12,7 @@
 
 #include "PluginManager.h"
 #include "Shared/Debug.h"
+#include "Shared/Profile.h"
 
 #include "llvm/Support/Error.h"
 #include "llvm/Support/ErrorHandling.h"
@@ -28,6 +29,7 @@ static const char *RTLNames[] = {ENABLED_OFFLOAD_PLUGINS};
 Expected<std::unique_ptr<PluginAdaptorTy>>
 PluginAdaptorTy::create(const std::string &Name) {
   DP("Attempting to load library '%s'...\n", Name.c_str());
+  TIMESCOPE_WITH_NAME_AND_IDENT(Name, (const ident_t *)nullptr);
 
   std::string ErrMsg;
   auto LibraryHandler = std::make_unique<DynamicLibrary>(
@@ -101,6 +103,7 @@ void PluginAdaptorTy::addOffloadEntries(DeviceImageTy &DI) {
 }
 
 void PluginManager::init() {
+  TIMESCOPE();
   DP("Loading RTLs...\n");
 
   // Attempt to open all the plugins and, if they exist, check if the interface
@@ -123,6 +126,7 @@ void PluginManager::init() {
 void PluginAdaptorTy::initDevices(PluginManager &PM) {
   if (isUsed())
     return;
+  TIMESCOPE();
 
   // If this RTL is not already in use, initialize it.
   assert(getNumberOfPluginDevices() > 0 &&
-- 
GitLab


From 2f4d601b6466323c3bb19b3d9e953c7b182223ba Mon Sep 17 00:00:00 2001
From: Lang Hames <lhames@gmail.com>
Date: Mon, 11 Dec 2023 17:18:36 -0800
Subject: [PATCH 208/349] [ORC][LLJIT] Expose ORCPlatformSupport to aid custom
 native Platform setup.

LLJIT users may want to customize their native platform setup beyond what the
ExecutorNativePlatform helper permits. In this case LLJIT users can construct
the platform instance manually, and then add an ORCPlatformSupport instance
to forward initialize/deinitialize operations to the ORC runtime.
---
 llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h |  13 +++
 llvm/lib/ExecutionEngine/Orc/LLJIT.cpp        | 107 ++++++++----------
 2 files changed, 61 insertions(+), 59 deletions(-)

diff --git a/llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h b/llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
index 8ab8ff8a0034..923976b182d1 100644
--- a/llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
+++ b/llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
@@ -584,6 +584,19 @@ Expected<JITDylibSP> setUpGenericLLVMIRPlatform(LLJIT &J);
 /// with the generic IR platform.
 Expected<JITDylibSP> setUpInactivePlatform(LLJIT &J);
 
+/// A Platform-support class that implements initialize / deinitialize by
+/// forwarding to ORC runtime dlopen / dlclose operations.
+class ORCPlatformSupport : public LLJIT::PlatformSupport {
+public:
+  ORCPlatformSupport(orc::LLJIT &J) : J(J) {}
+  Error initialize(orc::JITDylib &JD) override;
+  Error deinitialize(orc::JITDylib &JD) override;
+
+private:
+  orc::LLJIT &J;
+  DenseMap<orc::JITDylib *, orc::ExecutorAddr> DSOHandles;
+};
+
 } // End namespace orc
 } // End namespace llvm
 
diff --git a/llvm/lib/ExecutionEngine/Orc/LLJIT.cpp b/llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
index 90123b3f0a96..2ce8058c918d 100644
--- a/llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
+++ b/llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
@@ -84,65 +84,6 @@ Function *addHelperAndWrapper(Module &M, StringRef WrapperName,
   return WrapperFn;
 }
 
-class ORCPlatformSupport : public LLJIT::PlatformSupport {
-public:
-  ORCPlatformSupport(orc::LLJIT &J) : J(J) {}
-
-  Error initialize(orc::JITDylib &JD) override {
-    using llvm::orc::shared::SPSExecutorAddr;
-    using llvm::orc::shared::SPSString;
-    using SPSDLOpenSig = SPSExecutorAddr(SPSString, int32_t);
-    enum dlopen_mode : int32_t {
-      ORC_RT_RTLD_LAZY = 0x1,
-      ORC_RT_RTLD_NOW = 0x2,
-      ORC_RT_RTLD_LOCAL = 0x4,
-      ORC_RT_RTLD_GLOBAL = 0x8
-    };
-
-    auto &ES = J.getExecutionSession();
-    auto MainSearchOrder = J.getMainJITDylib().withLinkOrderDo(
-        [](const JITDylibSearchOrder &SO) { return SO; });
-
-    if (auto WrapperAddr =
-            ES.lookup(MainSearchOrder,
-                      J.mangleAndIntern("__orc_rt_jit_dlopen_wrapper"))) {
-      return ES.callSPSWrapper<SPSDLOpenSig>(WrapperAddr->getAddress(),
-                                             DSOHandles[&JD], JD.getName(),
-                                             int32_t(ORC_RT_RTLD_LAZY));
-    } else
-      return WrapperAddr.takeError();
-  }
-
-  Error deinitialize(orc::JITDylib &JD) override {
-    using llvm::orc::shared::SPSExecutorAddr;
-    using SPSDLCloseSig = int32_t(SPSExecutorAddr);
-
-    auto &ES = J.getExecutionSession();
-    auto MainSearchOrder = J.getMainJITDylib().withLinkOrderDo(
-        [](const JITDylibSearchOrder &SO) { return SO; });
-
-    if (auto WrapperAddr =
-            ES.lookup(MainSearchOrder,
-                      J.mangleAndIntern("__orc_rt_jit_dlclose_wrapper"))) {
-      int32_t result;
-      auto E = J.getExecutionSession().callSPSWrapper<SPSDLCloseSig>(
-          WrapperAddr->getAddress(), result, DSOHandles[&JD]);
-      if (E)
-        return E;
-      else if (result)
-        return make_error<StringError>("dlclose failed",
-                                       inconvertibleErrorCode());
-      DSOHandles.erase(&JD);
-    } else
-      return WrapperAddr.takeError();
-    return Error::success();
-  }
-
-private:
-  orc::LLJIT &J;
-  DenseMap<orc::JITDylib *, orc::ExecutorAddr> DSOHandles;
-};
-
 class GenericLLVMIRPlatformSupport;
 
 /// orc::Platform component of Generic LLVM IR Platform support.
@@ -656,6 +597,54 @@ public:
 namespace llvm {
 namespace orc {
 
+Error ORCPlatformSupport::initialize(orc::JITDylib &JD) {
+  using llvm::orc::shared::SPSExecutorAddr;
+  using llvm::orc::shared::SPSString;
+  using SPSDLOpenSig = SPSExecutorAddr(SPSString, int32_t);
+  enum dlopen_mode : int32_t {
+    ORC_RT_RTLD_LAZY = 0x1,
+    ORC_RT_RTLD_NOW = 0x2,
+    ORC_RT_RTLD_LOCAL = 0x4,
+    ORC_RT_RTLD_GLOBAL = 0x8
+  };
+
+  auto &ES = J.getExecutionSession();
+  auto MainSearchOrder = J.getMainJITDylib().withLinkOrderDo(
+      [](const JITDylibSearchOrder &SO) { return SO; });
+
+  if (auto WrapperAddr = ES.lookup(
+          MainSearchOrder, J.mangleAndIntern("__orc_rt_jit_dlopen_wrapper"))) {
+    return ES.callSPSWrapper<SPSDLOpenSig>(WrapperAddr->getAddress(),
+                                           DSOHandles[&JD], JD.getName(),
+                                           int32_t(ORC_RT_RTLD_LAZY));
+  } else
+    return WrapperAddr.takeError();
+}
+
+Error ORCPlatformSupport::deinitialize(orc::JITDylib &JD) {
+  using llvm::orc::shared::SPSExecutorAddr;
+  using SPSDLCloseSig = int32_t(SPSExecutorAddr);
+
+  auto &ES = J.getExecutionSession();
+  auto MainSearchOrder = J.getMainJITDylib().withLinkOrderDo(
+      [](const JITDylibSearchOrder &SO) { return SO; });
+
+  if (auto WrapperAddr = ES.lookup(
+          MainSearchOrder, J.mangleAndIntern("__orc_rt_jit_dlclose_wrapper"))) {
+    int32_t result;
+    auto E = J.getExecutionSession().callSPSWrapper<SPSDLCloseSig>(
+        WrapperAddr->getAddress(), result, DSOHandles[&JD]);
+    if (E)
+      return E;
+    else if (result)
+      return make_error<StringError>("dlclose failed",
+                                     inconvertibleErrorCode());
+    DSOHandles.erase(&JD);
+  } else
+    return WrapperAddr.takeError();
+  return Error::success();
+}
+
 void LLJIT::PlatformSupport::setInitTransform(
     LLJIT &J, IRTransformLayer::TransformFunction T) {
   J.InitHelperTransformLayer->setTransform(std::move(T));
-- 
GitLab


From 30b94302f7c9ac59cda0a0a5b768b4b53b8bdde7 Mon Sep 17 00:00:00 2001
From: Nico Weber <thakis@chromium.org>
Date: Mon, 11 Dec 2023 21:30:04 -0500
Subject: [PATCH 209/349] [gn] port 6747fc07d1aa9 (made necessary by
 54397f9ac128)

---
 .../gn/secondary/llvm/unittests/ExecutionEngine/Orc/BUILD.gn | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/Orc/BUILD.gn b/llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/Orc/BUILD.gn
index 47c7bb3d97d1..be1efff15f5a 100644
--- a/llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/Orc/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/Orc/BUILD.gn
@@ -40,4 +40,9 @@ unittest("OrcJITTests") {
     "ThreadSafeModuleTest.cpp",
     "WrapperFunctionUtilsTest.cpp",
   ]
+
+  if (host_os != "mac" && host_os != "win") {
+    # Corresponds to export_executable_symbols() in cmake.
+    ldflags = [ "-rdynamic" ]
+  }
 }
-- 
GitLab


From 843ea9843718c57da19b3916565f387adf4e440c Mon Sep 17 00:00:00 2001
From: Arthur Eubanks <aeubanks@google.com>
Date: Mon, 11 Dec 2023 19:00:56 -0800
Subject: [PATCH 210/349] [X86] Allow constant pool references under medium
 code model in X86InstrInfo::foldMemoryOperandImpl() (#75011)

The medium code model assumes that the constant pool is referenceable
with 32-bit relocations.
---
 llvm/lib/Target/X86/X86InstrInfo.cpp   |  5 ++--
 llvm/test/CodeGen/X86/mmx-fold-zero.ll | 39 +++++++++++++++++++++++++-
 2 files changed, 40 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index d6ae4971d238..7b607c6f198c 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -8026,9 +8026,8 @@ MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
     // Create a constant-pool entry and operands to load from it.
 
-    // Medium and large mode can't fold loads this way.
-    if (MF.getTarget().getCodeModel() != CodeModel::Small &&
-        MF.getTarget().getCodeModel() != CodeModel::Kernel)
+    // Large code model can't fold loads this way.
+    if (MF.getTarget().getCodeModel() == CodeModel::Large)
       return nullptr;
 
     // x86-32 PIC requires a PIC base register for constant pools.
diff --git a/llvm/test/CodeGen/X86/mmx-fold-zero.ll b/llvm/test/CodeGen/X86/mmx-fold-zero.ll
index d40146453cff..b2c94e3aaa3a 100644
--- a/llvm/test/CodeGen/X86/mmx-fold-zero.ll
+++ b/llvm/test/CodeGen/X86/mmx-fold-zero.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X86
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+mmx,+sse2 -code-model=small | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+mmx,+sse2 -code-model=medium | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+mmx,+sse2 -code-model=large | FileCheck %s --check-prefix=X64-LARGE
 
 define double @mmx_zero(double, double, double, double) nounwind {
 ; X86-LABEL: mmx_zero:
@@ -78,6 +80,41 @@ define double @mmx_zero(double, double, double, double) nounwind {
 ; X64-NEXT:    paddw %mm2, %mm0
 ; X64-NEXT:    movq2dq %mm0, %xmm0
 ; X64-NEXT:    retq
+;
+; X64-LARGE-LABEL: mmx_zero:
+; X64-LARGE:       # %bb.0:
+; X64-LARGE-NEXT:    movdq2q %xmm0, %mm0
+; X64-LARGE-NEXT:    movdq2q %xmm1, %mm5
+; X64-LARGE-NEXT:    movq %mm5, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; X64-LARGE-NEXT:    movq %mm0, %mm3
+; X64-LARGE-NEXT:    paddd %mm5, %mm3
+; X64-LARGE-NEXT:    pxor %mm1, %mm1
+; X64-LARGE-NEXT:    movq %mm3, %mm6
+; X64-LARGE-NEXT:    pmuludq %mm1, %mm6
+; X64-LARGE-NEXT:    movdq2q %xmm2, %mm4
+; X64-LARGE-NEXT:    movq %mm6, %mm2
+; X64-LARGE-NEXT:    paddd %mm4, %mm2
+; X64-LARGE-NEXT:    paddw %mm2, %mm0
+; X64-LARGE-NEXT:    movq %mm5, %mm1
+; X64-LARGE-NEXT:    paddw %mm0, %mm1
+; X64-LARGE-NEXT:    movdq2q %xmm3, %mm5
+; X64-LARGE-NEXT:    movq %mm1, %mm7
+; X64-LARGE-NEXT:    pmuludq %mm5, %mm7
+; X64-LARGE-NEXT:    paddw %mm4, %mm7
+; X64-LARGE-NEXT:    paddw %mm7, %mm5
+; X64-LARGE-NEXT:    paddw %mm5, %mm2
+; X64-LARGE-NEXT:    paddw %mm2, %mm0
+; X64-LARGE-NEXT:    paddw %mm6, %mm0
+; X64-LARGE-NEXT:    pmuludq %mm3, %mm0
+; X64-LARGE-NEXT:    pxor %mm3, %mm3
+; X64-LARGE-NEXT:    paddw %mm3, %mm0
+; X64-LARGE-NEXT:    paddw %mm1, %mm0
+; X64-LARGE-NEXT:    pmuludq %mm7, %mm0
+; X64-LARGE-NEXT:    pmuludq {{[-0-9]+}}(%r{{[sb]}}p), %mm0 # 8-byte Folded Reload
+; X64-LARGE-NEXT:    paddw %mm5, %mm0
+; X64-LARGE-NEXT:    paddw %mm2, %mm0
+; X64-LARGE-NEXT:    movq2dq %mm0, %xmm0
+; X64-LARGE-NEXT:    retq
   %5 = bitcast double %0 to x86_mmx
   %6 = bitcast double %1 to x86_mmx
   %7 = tail call x86_mmx @llvm.x86.mmx.padd.d(x86_mmx %5, x86_mmx %6)
-- 
GitLab


From 3850131197b7508e2e2f25f966f75105a0be3929 Mon Sep 17 00:00:00 2001
From: Arthur Eubanks <aeubanks@google.com>
Date: Mon, 11 Dec 2023 19:01:44 -0800
Subject: [PATCH 211/349] [X86] Handle ifuncs in
 TargetMachine::isLargeGlobalObject() (#74911)

isLargeGlobalObject() didn't handle GlobalIFuncs, resulting in crashes.

Treat ifuncs the same as normal Functions.
---
 llvm/lib/Target/TargetMachine.cpp       |   7 +-
 llvm/test/CodeGen/X86/code-model-elf.ll | 122 +++++++++++++++++++++---
 2 files changed, 114 insertions(+), 15 deletions(-)

diff --git a/llvm/lib/Target/TargetMachine.cpp b/llvm/lib/Target/TargetMachine.cpp
index ff496d29b391..86c819a82810 100644
--- a/llvm/lib/Target/TargetMachine.cpp
+++ b/llvm/lib/Target/TargetMachine.cpp
@@ -43,10 +43,11 @@ bool TargetMachine::isLargeGlobalObject(const GlobalObject *GO) const {
   if (getTargetTriple().getArch() != Triple::x86_64)
     return false;
 
-  if (isa<Function>(GO))
-    return getCodeModel() == CodeModel::Large;
+  auto *GV = dyn_cast<GlobalVariable>(GO);
 
-  auto *GV = cast<GlobalVariable>(GO);
+  // Functions/GlobalIFuncs are only large under the large code model.
+  if (!GV)
+    return getCodeModel() == CodeModel::Large;
 
   if (GV->isThreadLocal())
     return false;
diff --git a/llvm/test/CodeGen/X86/code-model-elf.ll b/llvm/test/CodeGen/X86/code-model-elf.ll
index 457c6bde354f..3154a3d9baaa 100644
--- a/llvm/test/CodeGen/X86/code-model-elf.ll
+++ b/llvm/test/CodeGen/X86/code-model-elf.ll
@@ -583,6 +583,18 @@ define internal void @static_fn() #0 {
 
 declare void @extern_fn()
 
+@ifunc_func = ifunc void (), ptr @resolver
+@dso_local_ifunc_func = dso_local ifunc void (), ptr @resolver
+
+define internal ptr @resolver() {
+; CHECK-LABEL: resolver:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    retq
+entry:
+  ret ptr null
+}
+
 define dso_local ptr @lea_static_fn() #0 {
 ; SMALL-STATIC-LABEL: lea_static_fn:
 ; SMALL-STATIC:       # %bb.0:
@@ -616,9 +628,9 @@ define dso_local ptr @lea_static_fn() #0 {
 ;
 ; LARGE-PIC-LABEL: lea_static_fn:
 ; LARGE-PIC:       # %bb.0:
-; LARGE-PIC-NEXT:  .L13$pb:
-; LARGE-PIC-NEXT:    leaq .L13$pb(%rip), %rax
-; LARGE-PIC-NEXT:    movabsq $_GLOBAL_OFFSET_TABLE_-.L13$pb, %rcx
+; LARGE-PIC-NEXT:  .L14$pb:
+; LARGE-PIC-NEXT:    leaq .L14$pb(%rip), %rax
+; LARGE-PIC-NEXT:    movabsq $_GLOBAL_OFFSET_TABLE_-.L14$pb, %rcx
 ; LARGE-PIC-NEXT:    addq %rax, %rcx
 ; LARGE-PIC-NEXT:    movabsq $static_fn@GOTOFF, %rax
 ; LARGE-PIC-NEXT:    addq %rcx, %rax
@@ -659,9 +671,9 @@ define dso_local ptr @lea_global_fn() #0 {
 ;
 ; LARGE-PIC-LABEL: lea_global_fn:
 ; LARGE-PIC:       # %bb.0:
-; LARGE-PIC-NEXT:  .L14$pb:
-; LARGE-PIC-NEXT:    leaq .L14$pb(%rip), %rax
-; LARGE-PIC-NEXT:    movabsq $_GLOBAL_OFFSET_TABLE_-.L14$pb, %rcx
+; LARGE-PIC-NEXT:  .L15$pb:
+; LARGE-PIC-NEXT:    leaq .L15$pb(%rip), %rax
+; LARGE-PIC-NEXT:    movabsq $_GLOBAL_OFFSET_TABLE_-.L15$pb, %rcx
 ; LARGE-PIC-NEXT:    addq %rax, %rcx
 ; LARGE-PIC-NEXT:    movabsq $global_fn@GOTOFF, %rax
 ; LARGE-PIC-NEXT:    addq %rcx, %rax
@@ -702,9 +714,9 @@ define dso_local ptr @lea_extern_fn() #0 {
 ;
 ; LARGE-PIC-LABEL: lea_extern_fn:
 ; LARGE-PIC:       # %bb.0:
-; LARGE-PIC-NEXT:  .L15$pb:
-; LARGE-PIC-NEXT:    leaq .L15$pb(%rip), %rax
-; LARGE-PIC-NEXT:    movabsq $_GLOBAL_OFFSET_TABLE_-.L15$pb, %rcx
+; LARGE-PIC-NEXT:  .L16$pb:
+; LARGE-PIC-NEXT:    leaq .L16$pb(%rip), %rax
+; LARGE-PIC-NEXT:    movabsq $_GLOBAL_OFFSET_TABLE_-.L16$pb, %rcx
 ; LARGE-PIC-NEXT:    addq %rax, %rcx
 ; LARGE-PIC-NEXT:    movabsq $extern_fn@GOT, %rax
 ; LARGE-PIC-NEXT:    movq (%rcx,%rax), %rax
@@ -712,6 +724,92 @@ define dso_local ptr @lea_extern_fn() #0 {
   ret ptr @extern_fn
 }
 
+define dso_local ptr @lea_ifunc() #0 {
+; SMALL-STATIC-LABEL: lea_ifunc:
+; SMALL-STATIC:       # %bb.0:
+; SMALL-STATIC-NEXT:    movq ifunc_func@GOTPCREL(%rip), %rax
+; SMALL-STATIC-NEXT:    retq
+;
+; MEDIUM-STATIC-LABEL: lea_ifunc:
+; MEDIUM-STATIC:       # %bb.0:
+; MEDIUM-STATIC-NEXT:    movq ifunc_func@GOTPCREL(%rip), %rax
+; MEDIUM-STATIC-NEXT:    retq
+;
+; LARGE-STATIC-LABEL: lea_ifunc:
+; LARGE-STATIC:       # %bb.0:
+; LARGE-STATIC-NEXT:    movabsq $ifunc_func, %rax
+; LARGE-STATIC-NEXT:    retq
+;
+; SMALL-PIC-LABEL: lea_ifunc:
+; SMALL-PIC:       # %bb.0:
+; SMALL-PIC-NEXT:    movq ifunc_func@GOTPCREL(%rip), %rax
+; SMALL-PIC-NEXT:    retq
+;
+; MEDIUM-SMALL-DATA-PIC-LABEL: lea_ifunc:
+; MEDIUM-SMALL-DATA-PIC:       # %bb.0:
+; MEDIUM-SMALL-DATA-PIC-NEXT:    movq ifunc_func@GOTPCREL(%rip), %rax
+; MEDIUM-SMALL-DATA-PIC-NEXT:    retq
+;
+; MEDIUM-PIC-LABEL: lea_ifunc:
+; MEDIUM-PIC:       # %bb.0:
+; MEDIUM-PIC-NEXT:    movq ifunc_func@GOTPCREL(%rip), %rax
+; MEDIUM-PIC-NEXT:    retq
+;
+; LARGE-PIC-LABEL: lea_ifunc:
+; LARGE-PIC:       # %bb.0:
+; LARGE-PIC-NEXT:  .L17$pb:
+; LARGE-PIC-NEXT:    leaq .L17$pb(%rip), %rax
+; LARGE-PIC-NEXT:    movabsq $_GLOBAL_OFFSET_TABLE_-.L17$pb, %rcx
+; LARGE-PIC-NEXT:    addq %rax, %rcx
+; LARGE-PIC-NEXT:    movabsq $ifunc_func@GOT, %rax
+; LARGE-PIC-NEXT:    movq (%rcx,%rax), %rax
+; LARGE-PIC-NEXT:    retq
+  ret ptr @ifunc_func
+}
+
+define dso_local ptr @lea_dso_local_ifunc() #0 {
+; SMALL-STATIC-LABEL: lea_dso_local_ifunc:
+; SMALL-STATIC:       # %bb.0:
+; SMALL-STATIC-NEXT:    movl $dso_local_ifunc_func, %eax
+; SMALL-STATIC-NEXT:    retq
+;
+; MEDIUM-STATIC-LABEL: lea_dso_local_ifunc:
+; MEDIUM-STATIC:       # %bb.0:
+; MEDIUM-STATIC-NEXT:    movabsq $dso_local_ifunc_func, %rax
+; MEDIUM-STATIC-NEXT:    retq
+;
+; LARGE-STATIC-LABEL: lea_dso_local_ifunc:
+; LARGE-STATIC:       # %bb.0:
+; LARGE-STATIC-NEXT:    movabsq $dso_local_ifunc_func, %rax
+; LARGE-STATIC-NEXT:    retq
+;
+; SMALL-PIC-LABEL: lea_dso_local_ifunc:
+; SMALL-PIC:       # %bb.0:
+; SMALL-PIC-NEXT:    leaq dso_local_ifunc_func(%rip), %rax
+; SMALL-PIC-NEXT:    retq
+;
+; MEDIUM-SMALL-DATA-PIC-LABEL: lea_dso_local_ifunc:
+; MEDIUM-SMALL-DATA-PIC:       # %bb.0:
+; MEDIUM-SMALL-DATA-PIC-NEXT:    leaq dso_local_ifunc_func(%rip), %rax
+; MEDIUM-SMALL-DATA-PIC-NEXT:    retq
+;
+; MEDIUM-PIC-LABEL: lea_dso_local_ifunc:
+; MEDIUM-PIC:       # %bb.0:
+; MEDIUM-PIC-NEXT:    leaq dso_local_ifunc_func(%rip), %rax
+; MEDIUM-PIC-NEXT:    retq
+;
+; LARGE-PIC-LABEL: lea_dso_local_ifunc:
+; LARGE-PIC:       # %bb.0:
+; LARGE-PIC-NEXT:  .L18$pb:
+; LARGE-PIC-NEXT:    leaq .L18$pb(%rip), %rax
+; LARGE-PIC-NEXT:    movabsq $_GLOBAL_OFFSET_TABLE_-.L18$pb, %rcx
+; LARGE-PIC-NEXT:    addq %rax, %rcx
+; LARGE-PIC-NEXT:    movabsq $dso_local_ifunc_func@GOTOFF, %rax
+; LARGE-PIC-NEXT:    addq %rcx, %rax
+; LARGE-PIC-NEXT:    retq
+  ret ptr @dso_local_ifunc_func
+}
+
 ; FIXME: The result is same for small, medium and large model, because we
 ; specify pie option in the test case. And the type of tls is initial exec tls.
 ; For pic code. The large model code for pic tls should be emitted as below.
@@ -780,9 +878,9 @@ define dso_local float @load_constant_pool(float %x) #0 {
 ;
 ; LARGE-PIC-LABEL: load_constant_pool:
 ; LARGE-PIC:       # %bb.0:
-; LARGE-PIC-NEXT:  .L17$pb:
-; LARGE-PIC-NEXT:    leaq .L17$pb(%rip), %rax
-; LARGE-PIC-NEXT:    movabsq $_GLOBAL_OFFSET_TABLE_-.L17$pb, %rcx
+; LARGE-PIC-NEXT:  .L20$pb:
+; LARGE-PIC-NEXT:    leaq .L20$pb(%rip), %rax
+; LARGE-PIC-NEXT:    movabsq $_GLOBAL_OFFSET_TABLE_-.L20$pb, %rcx
 ; LARGE-PIC-NEXT:    addq %rax, %rcx
 ; LARGE-PIC-NEXT:    movabsq ${{\.?LCPI[0-9]+_[0-9]+}}@GOTOFF, %rax
 ; LARGE-PIC-NEXT:    addss (%rcx,%rax), %xmm0
-- 
GitLab


From a19c7c403fa056a37585407586a2d84d03f41d8a Mon Sep 17 00:00:00 2001
From: bcahoon <59846893+bcahoon@users.noreply.github.com>
Date: Mon, 11 Dec 2023 21:10:34 -0600
Subject: [PATCH 212/349] [MachinePipeliner] Fix store-store dependences
 (#72575)

The pipeliner needs to mark store-store order dependences as
loop carried dependences. Otherwise, the stores may be scheduled
further apart than the MII. The order dependences implies that
the first instance of the dependent store is scheduled before the
second instance of the source store instruction.
---
 llvm/lib/CodeGen/MachinePipeliner.cpp         |  8 +-
 .../CodeGen/PowerPC/sms-store-dependence.ll   | 84 +++++++++++++++++++
 2 files changed, 89 insertions(+), 3 deletions(-)
 create mode 100644 llvm/test/CodeGen/PowerPC/sms-store-dependence.ll

diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index 81b7fdcc5961..8cd7f4ebe88d 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -2225,7 +2225,7 @@ MachineInstr *SwingSchedulerDAG::findDefInLoop(Register Reg) {
 }
 
 /// Return true for an order or output dependence that is loop carried
-/// potentially. A dependence is loop carried if the destination defines a valu
+/// potentially. A dependence is loop carried if the destination defines a value
 /// that may be used or defined by the source in a subsequent iteration.
 bool SwingSchedulerDAG::isLoopCarriedDep(SUnit *Source, const SDep &Dep,
                                          bool isSucc) {
@@ -2251,10 +2251,12 @@ bool SwingSchedulerDAG::isLoopCarriedDep(SUnit *Source, const SDep &Dep,
       SI->hasOrderedMemoryRef() || DI->hasOrderedMemoryRef())
     return true;
 
-  // Only chain dependences between a load and store can be loop carried.
-  if (!DI->mayStore() || !SI->mayLoad())
+  if (!DI->mayLoadOrStore() || !SI->mayLoadOrStore())
     return false;
 
+  // The conservative assumption is that a dependence between memory operations
+  // may be loop carried. The following code checks when it can be proved that
+  // there is no loop carried dependence.
   unsigned DeltaS, DeltaD;
   if (!computeDelta(*SI, DeltaS) || !computeDelta(*DI, DeltaD))
     return true;
diff --git a/llvm/test/CodeGen/PowerPC/sms-store-dependence.ll b/llvm/test/CodeGen/PowerPC/sms-store-dependence.ll
new file mode 100644
index 000000000000..d1ec320d5568
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/sms-store-dependence.ll
@@ -0,0 +1,84 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\
+; RUN:       -mcpu=pwr9 --ppc-enable-pipeliner 2>&1 | FileCheck %s
+
+; Test that the pipeliner schedules the store instructions correctly. Since
+; there is a dependence between the store, they cannot be scheduled further than
+; MII cycles/instructions apart. That is, the first store cannot occur multiple
+; times before the second ctore in the schedule.
+define dso_local void @comp_method(ptr noalias nocapture noundef readonly %0, ptr nocapture noundef writeonly %1, ptr nocapture noundef writeonly %2, i32 noundef %3, i32 noundef %4, i32 noundef %5, i32 noundef %6, i64 %v1) local_unnamed_addr {
+; CHECK-LABEL: comp_method:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    extsw 7, 8
+; CHECK-NEXT:    extsw 8, 9
+; CHECK-NEXT:    clrldi 9, 6, 32
+; CHECK-NEXT:    addi 6, 3, -1
+; CHECK-NEXT:    mtctr 9
+; CHECK-NEXT:    li 11, 0
+; CHECK-NEXT:    sradi 12, 11, 2
+; CHECK-NEXT:    add 5, 5, 8
+; CHECK-NEXT:    li 8, 2
+; CHECK-NEXT:    li 3, 8
+; CHECK-NEXT:    addi 11, 7, 0
+; CHECK-NEXT:    std 30, -16(1) # 8-byte Folded Spill
+; CHECK-NEXT:    lbzu 9, 1(6)
+; CHECK-NEXT:    add 12, 12, 10
+; CHECK-NEXT:    extsb 9, 9
+; CHECK-NEXT:    stbx 8, 4, 9
+; CHECK-NEXT:    add 9, 9, 12
+; CHECK-NEXT:    bdz .LBB0_2
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_1:
+; CHECK-NEXT:    lbzu 0, 1(6)
+; CHECK-NEXT:    sradi 12, 11, 2
+; CHECK-NEXT:    add 11, 11, 7
+; CHECK-NEXT:    add 12, 12, 10
+; CHECK-NEXT:    sldi 30, 9, 2
+; CHECK-NEXT:    add 9, 9, 30
+; CHECK-NEXT:    extsb 0, 0
+; CHECK-NEXT:    stbx 3, 5, 9
+; CHECK-NEXT:    add 9, 0, 12
+; CHECK-NEXT:    stbx 8, 4, 0
+; CHECK-NEXT:    bdnz .LBB0_1
+; CHECK-NEXT:  .LBB0_2:
+; CHECK-NEXT:    sldi 4, 9, 2
+; CHECK-NEXT:    ld 30, -16(1) # 8-byte Folded Reload
+; CHECK-NEXT:    add 4, 9, 4
+; CHECK-NEXT:    stbx 3, 5, 4
+; CHECK-NEXT:    blr
+  %8 = icmp sgt i32 %3, 64
+  tail call void @llvm.assume(i1 %8)
+  %9 = and i32 %3, 1
+  %10 = icmp eq i32 %9, 0
+  tail call void @llvm.assume(i1 %10)
+  %11 = sext i32 %5 to i64
+  %12 = sext i32 %6 to i64
+  %13 = zext nneg i32 %3 to i64
+  %14 = getelementptr i8, ptr %2, i64 %12
+  br label %16
+
+15:
+  ret void
+
+16:
+  %17 = phi i64 [ 0, %7 ], [ %24, %16 ]
+  %18 = getelementptr inbounds i8, ptr %0, i64 %17
+  %19 = load i8, ptr %18, align 1
+  %20 = sext i8 %19 to i64
+  %21 = getelementptr inbounds i8, ptr %1, i64 %20
+  store i8 2, ptr %21, align 1
+  %22 = mul nsw i64 %17, %11
+  %a1 = ashr i64 %22, 2
+  %a2 = add i64 %a1, %v1
+  %a3 = add i64 %20, %a2
+  %a4 = mul nsw i64 %a3, 5
+  %23 = getelementptr i8, ptr %14, i64 %a4
+  store i8 8, ptr %23, align 1
+  %24 = add nuw nsw i64 %17, 1
+  %25 = icmp eq i64 %24, %13
+  br i1 %25, label %15, label %16
+}
+
+declare void @llvm.assume(i1 noundef) #1
+
+attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
-- 
GitLab


From f82c85d21f85321a2626a2e8c17d9828a34f55d8 Mon Sep 17 00:00:00 2001
From: Arthur Eubanks <aeubanks@google.com>
Date: Mon, 11 Dec 2023 19:13:09 -0800
Subject: [PATCH 213/349] [X86] Handle unsized types in
 TargetMachine::isLargeGlobalObject() (#74952)

isLargeGlobalObject() didn't handle opaque types, resulting in crashes.
---
 llvm/lib/Target/TargetMachine.cpp       |  2 +
 llvm/test/CodeGen/X86/code-model-elf.ll | 86 +++++++++++++++++++------
 2 files changed, 70 insertions(+), 18 deletions(-)

diff --git a/llvm/lib/Target/TargetMachine.cpp b/llvm/lib/Target/TargetMachine.cpp
index 86c819a82810..246f6b4b492c 100644
--- a/llvm/lib/Target/TargetMachine.cpp
+++ b/llvm/lib/Target/TargetMachine.cpp
@@ -79,6 +79,8 @@ bool TargetMachine::isLargeGlobalObject(const GlobalObject *GO) const {
 
   if (getCodeModel() == CodeModel::Medium ||
       getCodeModel() == CodeModel::Large) {
+    if (!GV->getValueType()->isSized())
+      return true;
     const DataLayout &DL = GV->getParent()->getDataLayout();
     uint64_t Size = DL.getTypeSizeInBits(GV->getValueType()) / 8;
     return Size == 0 || Size > LargeDataThreshold;
diff --git a/llvm/test/CodeGen/X86/code-model-elf.ll b/llvm/test/CodeGen/X86/code-model-elf.ll
index 3154a3d9baaa..06989b0ffd22 100644
--- a/llvm/test/CodeGen/X86/code-model-elf.ll
+++ b/llvm/test/CodeGen/X86/code-model-elf.ll
@@ -36,11 +36,14 @@ source_filename = "model.c"
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64--linux"
 
+%t = type opaque
+
 @global_data = dso_local global [10 x i32] [i32 1, i32 2, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0], align 16
 @static_data = internal global [10 x i32] zeroinitializer, align 16
 @extern_data = external global [10 x i32], align 16
 @thread_data = external thread_local global i32, align 4
 @unknown_size_data = dso_local global [0 x i32] zeroinitializer, align 16
+@opaque = external dso_local global %t
 @forced_small_data = dso_local global [10 x i32] zeroinitializer, code_model "small", align 16
 @forced_large_data = dso_local global [10 x i32] zeroinitializer, code_model "large", align 16
 
@@ -567,6 +570,53 @@ define dso_local i32 @load_unknown_size_data() #0 {
   ret i32 %rv
 }
 
+define dso_local ptr @lea_opaque() #0 {
+; SMALL-STATIC-LABEL: lea_opaque:
+; SMALL-STATIC:       # %bb.0:
+; SMALL-STATIC-NEXT:    movl $opaque, %eax
+; SMALL-STATIC-NEXT:    retq
+;
+; MEDIUM-STATIC-LABEL: lea_opaque:
+; MEDIUM-STATIC:       # %bb.0:
+; MEDIUM-STATIC-NEXT:    movabsq $opaque, %rax
+; MEDIUM-STATIC-NEXT:    retq
+;
+; LARGE-STATIC-LABEL: lea_opaque:
+; LARGE-STATIC:       # %bb.0:
+; LARGE-STATIC-NEXT:    movabsq $opaque, %rax
+; LARGE-STATIC-NEXT:    retq
+;
+; SMALL-PIC-LABEL: lea_opaque:
+; SMALL-PIC:       # %bb.0:
+; SMALL-PIC-NEXT:    leaq opaque(%rip), %rax
+; SMALL-PIC-NEXT:    retq
+;
+; MEDIUM-SMALL-DATA-PIC-LABEL: lea_opaque:
+; MEDIUM-SMALL-DATA-PIC:       # %bb.0:
+; MEDIUM-SMALL-DATA-PIC-NEXT:    leaq _GLOBAL_OFFSET_TABLE_(%rip), %rcx
+; MEDIUM-SMALL-DATA-PIC-NEXT:    movabsq $opaque@GOTOFF, %rax
+; MEDIUM-SMALL-DATA-PIC-NEXT:    addq %rcx, %rax
+; MEDIUM-SMALL-DATA-PIC-NEXT:    retq
+;
+; MEDIUM-PIC-LABEL: lea_opaque:
+; MEDIUM-PIC:       # %bb.0:
+; MEDIUM-PIC-NEXT:    leaq _GLOBAL_OFFSET_TABLE_(%rip), %rcx
+; MEDIUM-PIC-NEXT:    movabsq $opaque@GOTOFF, %rax
+; MEDIUM-PIC-NEXT:    addq %rcx, %rax
+; MEDIUM-PIC-NEXT:    retq
+;
+; LARGE-PIC-LABEL: lea_opaque:
+; LARGE-PIC:       # %bb.0:
+; LARGE-PIC-NEXT:  .L11$pb:
+; LARGE-PIC-NEXT:    leaq .L11$pb(%rip), %rax
+; LARGE-PIC-NEXT:    movabsq $_GLOBAL_OFFSET_TABLE_-.L11$pb, %rcx
+; LARGE-PIC-NEXT:    addq %rax, %rcx
+; LARGE-PIC-NEXT:    movabsq $opaque@GOTOFF, %rax
+; LARGE-PIC-NEXT:    addq %rcx, %rax
+; LARGE-PIC-NEXT:    retq
+  ret ptr @opaque
+}
+
 define dso_local void @global_fn() #0 {
 ; CHECK-LABEL: global_fn:
 ; CHECK:       # %bb.0:
@@ -628,9 +678,9 @@ define dso_local ptr @lea_static_fn() #0 {
 ;
 ; LARGE-PIC-LABEL: lea_static_fn:
 ; LARGE-PIC:       # %bb.0:
-; LARGE-PIC-NEXT:  .L14$pb:
-; LARGE-PIC-NEXT:    leaq .L14$pb(%rip), %rax
-; LARGE-PIC-NEXT:    movabsq $_GLOBAL_OFFSET_TABLE_-.L14$pb, %rcx
+; LARGE-PIC-NEXT:  .L15$pb:
+; LARGE-PIC-NEXT:    leaq .L15$pb(%rip), %rax
+; LARGE-PIC-NEXT:    movabsq $_GLOBAL_OFFSET_TABLE_-.L15$pb, %rcx
 ; LARGE-PIC-NEXT:    addq %rax, %rcx
 ; LARGE-PIC-NEXT:    movabsq $static_fn@GOTOFF, %rax
 ; LARGE-PIC-NEXT:    addq %rcx, %rax
@@ -671,9 +721,9 @@ define dso_local ptr @lea_global_fn() #0 {
 ;
 ; LARGE-PIC-LABEL: lea_global_fn:
 ; LARGE-PIC:       # %bb.0:
-; LARGE-PIC-NEXT:  .L15$pb:
-; LARGE-PIC-NEXT:    leaq .L15$pb(%rip), %rax
-; LARGE-PIC-NEXT:    movabsq $_GLOBAL_OFFSET_TABLE_-.L15$pb, %rcx
+; LARGE-PIC-NEXT:  .L16$pb:
+; LARGE-PIC-NEXT:    leaq .L16$pb(%rip), %rax
+; LARGE-PIC-NEXT:    movabsq $_GLOBAL_OFFSET_TABLE_-.L16$pb, %rcx
 ; LARGE-PIC-NEXT:    addq %rax, %rcx
 ; LARGE-PIC-NEXT:    movabsq $global_fn@GOTOFF, %rax
 ; LARGE-PIC-NEXT:    addq %rcx, %rax
@@ -714,9 +764,9 @@ define dso_local ptr @lea_extern_fn() #0 {
 ;
 ; LARGE-PIC-LABEL: lea_extern_fn:
 ; LARGE-PIC:       # %bb.0:
-; LARGE-PIC-NEXT:  .L16$pb:
-; LARGE-PIC-NEXT:    leaq .L16$pb(%rip), %rax
-; LARGE-PIC-NEXT:    movabsq $_GLOBAL_OFFSET_TABLE_-.L16$pb, %rcx
+; LARGE-PIC-NEXT:  .L17$pb:
+; LARGE-PIC-NEXT:    leaq .L17$pb(%rip), %rax
+; LARGE-PIC-NEXT:    movabsq $_GLOBAL_OFFSET_TABLE_-.L17$pb, %rcx
 ; LARGE-PIC-NEXT:    addq %rax, %rcx
 ; LARGE-PIC-NEXT:    movabsq $extern_fn@GOT, %rax
 ; LARGE-PIC-NEXT:    movq (%rcx,%rax), %rax
@@ -757,9 +807,9 @@ define dso_local ptr @lea_ifunc() #0 {
 ;
 ; LARGE-PIC-LABEL: lea_ifunc:
 ; LARGE-PIC:       # %bb.0:
-; LARGE-PIC-NEXT:  .L17$pb:
-; LARGE-PIC-NEXT:    leaq .L17$pb(%rip), %rax
-; LARGE-PIC-NEXT:    movabsq $_GLOBAL_OFFSET_TABLE_-.L17$pb, %rcx
+; LARGE-PIC-NEXT:  .L18$pb:
+; LARGE-PIC-NEXT:    leaq .L18$pb(%rip), %rax
+; LARGE-PIC-NEXT:    movabsq $_GLOBAL_OFFSET_TABLE_-.L18$pb, %rcx
 ; LARGE-PIC-NEXT:    addq %rax, %rcx
 ; LARGE-PIC-NEXT:    movabsq $ifunc_func@GOT, %rax
 ; LARGE-PIC-NEXT:    movq (%rcx,%rax), %rax
@@ -800,9 +850,9 @@ define dso_local ptr @lea_dso_local_ifunc() #0 {
 ;
 ; LARGE-PIC-LABEL: lea_dso_local_ifunc:
 ; LARGE-PIC:       # %bb.0:
-; LARGE-PIC-NEXT:  .L18$pb:
-; LARGE-PIC-NEXT:    leaq .L18$pb(%rip), %rax
-; LARGE-PIC-NEXT:    movabsq $_GLOBAL_OFFSET_TABLE_-.L18$pb, %rcx
+; LARGE-PIC-NEXT:  .L19$pb:
+; LARGE-PIC-NEXT:    leaq .L19$pb(%rip), %rax
+; LARGE-PIC-NEXT:    movabsq $_GLOBAL_OFFSET_TABLE_-.L19$pb, %rcx
 ; LARGE-PIC-NEXT:    addq %rax, %rcx
 ; LARGE-PIC-NEXT:    movabsq $dso_local_ifunc_func@GOTOFF, %rax
 ; LARGE-PIC-NEXT:    addq %rcx, %rax
@@ -878,9 +928,9 @@ define dso_local float @load_constant_pool(float %x) #0 {
 ;
 ; LARGE-PIC-LABEL: load_constant_pool:
 ; LARGE-PIC:       # %bb.0:
-; LARGE-PIC-NEXT:  .L20$pb:
-; LARGE-PIC-NEXT:    leaq .L20$pb(%rip), %rax
-; LARGE-PIC-NEXT:    movabsq $_GLOBAL_OFFSET_TABLE_-.L20$pb, %rcx
+; LARGE-PIC-NEXT:  .L21$pb:
+; LARGE-PIC-NEXT:    leaq .L21$pb(%rip), %rax
+; LARGE-PIC-NEXT:    movabsq $_GLOBAL_OFFSET_TABLE_-.L21$pb, %rcx
 ; LARGE-PIC-NEXT:    addq %rax, %rcx
 ; LARGE-PIC-NEXT:    movabsq ${{\.?LCPI[0-9]+_[0-9]+}}@GOTOFF, %rax
 ; LARGE-PIC-NEXT:    addss (%rcx,%rax), %xmm0
-- 
GitLab


From d3f6e82a6a562e3288a6fc0970d324073996c16d Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp@bytedance.com>
Date: Tue, 12 Dec 2023 11:18:31 +0800
Subject: [PATCH 214/349] [MacroFusion] Support multiple predicators (#72219)

The user can provide multiple predicators to MacroFusion and the
DAG mutation will be applied if one of them is evalated to true.

`ShouldSchedulePredTy` is renamed to `MacroFusionPredTy`.
---
 llvm/include/llvm/CodeGen/MacroFusion.h | 19 +++++++------
 llvm/lib/CodeGen/MacroFusion.cpp        | 37 +++++++++++++++++--------
 llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp |  4 +--
 3 files changed, 37 insertions(+), 23 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/MacroFusion.h b/llvm/include/llvm/CodeGen/MacroFusion.h
index ea2c7a5faae3..41a027ea0669 100644
--- a/llvm/include/llvm/CodeGen/MacroFusion.h
+++ b/llvm/include/llvm/CodeGen/MacroFusion.h
@@ -14,7 +14,7 @@
 #ifndef LLVM_CODEGEN_MACROFUSION_H
 #define LLVM_CODEGEN_MACROFUSION_H
 
-#include <functional>
+#include "llvm/ADT/ArrayRef.h"
 #include <memory>
 
 namespace llvm {
@@ -29,10 +29,9 @@ class SUnit;
 /// Check if the instr pair, FirstMI and SecondMI, should be fused
 /// together. Given SecondMI, when FirstMI is unspecified, then check if
 /// SecondMI may be part of a fused pair at all.
-using ShouldSchedulePredTy = std::function<bool(const TargetInstrInfo &TII,
-                                                const TargetSubtargetInfo &TSI,
-                                                const MachineInstr *FirstMI,
-                                                const MachineInstr &SecondMI)>;
+using MacroFusionPredTy = function_ref<bool(
+    const TargetInstrInfo &TII, const TargetSubtargetInfo &STI,
+    const MachineInstr *FirstMI, const MachineInstr &SecondMI)>;
 
 /// Checks if the number of cluster edges between SU and its predecessors is
 /// less than FuseLimit
@@ -48,15 +47,17 @@ bool fuseInstructionPair(ScheduleDAGInstrs &DAG, SUnit &FirstSU,
 
 /// Create a DAG scheduling mutation to pair instructions back to back
 /// for instructions that benefit according to the target-specific
-/// shouldScheduleAdjacent predicate function.
+/// predicate functions. shouldScheduleAdjacent will be true if any of the
+/// provided predicates are true.
 std::unique_ptr<ScheduleDAGMutation>
-createMacroFusionDAGMutation(ShouldSchedulePredTy shouldScheduleAdjacent);
+createMacroFusionDAGMutation(ArrayRef<MacroFusionPredTy> Predicates);
 
 /// Create a DAG scheduling mutation to pair branch instructions with one
 /// of their predecessors back to back for instructions that benefit according
-/// to the target-specific shouldScheduleAdjacent predicate function.
+/// to the target-specific predicate functions. shouldScheduleAdjacent will be
+/// true if any of the provided predicates are true.
 std::unique_ptr<ScheduleDAGMutation>
-createBranchMacroFusionDAGMutation(ShouldSchedulePredTy shouldScheduleAdjacent);
+createBranchMacroFusionDAGMutation(ArrayRef<MacroFusionPredTy> Predicates);
 
 } // end namespace llvm
 
diff --git a/llvm/lib/CodeGen/MacroFusion.cpp b/llvm/lib/CodeGen/MacroFusion.cpp
index fa5df68b8abc..aff4d95781f4 100644
--- a/llvm/lib/CodeGen/MacroFusion.cpp
+++ b/llvm/lib/CodeGen/MacroFusion.cpp
@@ -137,19 +137,34 @@ namespace {
 /// Post-process the DAG to create cluster edges between instrs that may
 /// be fused by the processor into a single operation.
 class MacroFusion : public ScheduleDAGMutation {
-  ShouldSchedulePredTy shouldScheduleAdjacent;
+  std::vector<MacroFusionPredTy> Predicates;
   bool FuseBlock;
   bool scheduleAdjacentImpl(ScheduleDAGInstrs &DAG, SUnit &AnchorSU);
 
 public:
-  MacroFusion(ShouldSchedulePredTy shouldScheduleAdjacent, bool FuseBlock)
-    : shouldScheduleAdjacent(shouldScheduleAdjacent), FuseBlock(FuseBlock) {}
+  MacroFusion(ArrayRef<MacroFusionPredTy> Predicates, bool FuseBlock)
+      : Predicates(Predicates.begin(), Predicates.end()), FuseBlock(FuseBlock) {
+  }
 
   void apply(ScheduleDAGInstrs *DAGInstrs) override;
+
+  bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
+                              const TargetSubtargetInfo &STI,
+                              const MachineInstr *FirstMI,
+                              const MachineInstr &SecondMI);
 };
 
 } // end anonymous namespace
 
+bool MacroFusion::shouldScheduleAdjacent(const TargetInstrInfo &TII,
+                                         const TargetSubtargetInfo &STI,
+                                         const MachineInstr *FirstMI,
+                                         const MachineInstr &SecondMI) {
+  return llvm::any_of(Predicates, [&](MacroFusionPredTy Predicate) {
+    return Predicate(TII, STI, FirstMI, SecondMI);
+  });
+}
+
 void MacroFusion::apply(ScheduleDAGInstrs *DAG) {
   if (FuseBlock)
     // For each of the SUnits in the scheduling block, try to fuse the instr in
@@ -197,17 +212,15 @@ bool MacroFusion::scheduleAdjacentImpl(ScheduleDAGInstrs &DAG, SUnit &AnchorSU)
 }
 
 std::unique_ptr<ScheduleDAGMutation>
-llvm::createMacroFusionDAGMutation(
-     ShouldSchedulePredTy shouldScheduleAdjacent) {
-  if(EnableMacroFusion)
-    return std::make_unique<MacroFusion>(shouldScheduleAdjacent, true);
+llvm::createMacroFusionDAGMutation(ArrayRef<MacroFusionPredTy> Predicates) {
+  if (EnableMacroFusion)
+    return std::make_unique<MacroFusion>(Predicates, true);
   return nullptr;
 }
 
-std::unique_ptr<ScheduleDAGMutation>
-llvm::createBranchMacroFusionDAGMutation(
-     ShouldSchedulePredTy shouldScheduleAdjacent) {
-  if(EnableMacroFusion)
-    return std::make_unique<MacroFusion>(shouldScheduleAdjacent, false);
+std::unique_ptr<ScheduleDAGMutation> llvm::createBranchMacroFusionDAGMutation(
+    ArrayRef<MacroFusionPredTy> Predicates) {
+  if (EnableMacroFusion)
+    return std::make_unique<MacroFusion>(Predicates, false);
   return nullptr;
 }
diff --git a/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp b/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
index 29c9b9ccf276..0bddeeef9e9b 100644
--- a/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
@@ -142,10 +142,10 @@ namespace {
 /// be turned into VOPD instructions
 /// Greedily pairs instruction candidates. O(n^2) algorithm.
 struct VOPDPairingMutation : ScheduleDAGMutation {
-  ShouldSchedulePredTy shouldScheduleAdjacent; // NOLINT: function pointer
+  MacroFusionPredTy shouldScheduleAdjacent; // NOLINT: function pointer
 
   VOPDPairingMutation(
-      ShouldSchedulePredTy shouldScheduleAdjacent) // NOLINT: function pointer
+      MacroFusionPredTy shouldScheduleAdjacent) // NOLINT: function pointer
       : shouldScheduleAdjacent(shouldScheduleAdjacent) {}
 
   void apply(ScheduleDAGInstrs *DAG) override {
-- 
GitLab


From 59f3661bd22766e5d0dea391d4950605b249594a Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp@bytedance.com>
Date: Tue, 12 Dec 2023 11:21:39 +0800
Subject: [PATCH 215/349] Revert "[MacroFusion] Support multiple predicators
 (#72219)"

This reverts commit d3f6e82a6a562e3288a6fc0970d324073996c16d.

Some code can't be compiled.
---
 llvm/include/llvm/CodeGen/MacroFusion.h | 19 ++++++-------
 llvm/lib/CodeGen/MacroFusion.cpp        | 37 ++++++++-----------------
 llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp |  4 +--
 3 files changed, 23 insertions(+), 37 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/MacroFusion.h b/llvm/include/llvm/CodeGen/MacroFusion.h
index 41a027ea0669..ea2c7a5faae3 100644
--- a/llvm/include/llvm/CodeGen/MacroFusion.h
+++ b/llvm/include/llvm/CodeGen/MacroFusion.h
@@ -14,7 +14,7 @@
 #ifndef LLVM_CODEGEN_MACROFUSION_H
 #define LLVM_CODEGEN_MACROFUSION_H
 
-#include "llvm/ADT/ArrayRef.h"
+#include <functional>
 #include <memory>
 
 namespace llvm {
@@ -29,9 +29,10 @@ class SUnit;
 /// Check if the instr pair, FirstMI and SecondMI, should be fused
 /// together. Given SecondMI, when FirstMI is unspecified, then check if
 /// SecondMI may be part of a fused pair at all.
-using MacroFusionPredTy = function_ref<bool(
-    const TargetInstrInfo &TII, const TargetSubtargetInfo &STI,
-    const MachineInstr *FirstMI, const MachineInstr &SecondMI)>;
+using ShouldSchedulePredTy = std::function<bool(const TargetInstrInfo &TII,
+                                                const TargetSubtargetInfo &TSI,
+                                                const MachineInstr *FirstMI,
+                                                const MachineInstr &SecondMI)>;
 
 /// Checks if the number of cluster edges between SU and its predecessors is
 /// less than FuseLimit
@@ -47,17 +48,15 @@ bool fuseInstructionPair(ScheduleDAGInstrs &DAG, SUnit &FirstSU,
 
 /// Create a DAG scheduling mutation to pair instructions back to back
 /// for instructions that benefit according to the target-specific
-/// predicate functions. shouldScheduleAdjacent will be true if any of the
-/// provided predicates are true.
+/// shouldScheduleAdjacent predicate function.
 std::unique_ptr<ScheduleDAGMutation>
-createMacroFusionDAGMutation(ArrayRef<MacroFusionPredTy> Predicates);
+createMacroFusionDAGMutation(ShouldSchedulePredTy shouldScheduleAdjacent);
 
 /// Create a DAG scheduling mutation to pair branch instructions with one
 /// of their predecessors back to back for instructions that benefit according
-/// to the target-specific predicate functions. shouldScheduleAdjacent will be
-/// true if any of the provided predicates are true.
+/// to the target-specific shouldScheduleAdjacent predicate function.
 std::unique_ptr<ScheduleDAGMutation>
-createBranchMacroFusionDAGMutation(ArrayRef<MacroFusionPredTy> Predicates);
+createBranchMacroFusionDAGMutation(ShouldSchedulePredTy shouldScheduleAdjacent);
 
 } // end namespace llvm
 
diff --git a/llvm/lib/CodeGen/MacroFusion.cpp b/llvm/lib/CodeGen/MacroFusion.cpp
index aff4d95781f4..fa5df68b8abc 100644
--- a/llvm/lib/CodeGen/MacroFusion.cpp
+++ b/llvm/lib/CodeGen/MacroFusion.cpp
@@ -137,34 +137,19 @@ namespace {
 /// Post-process the DAG to create cluster edges between instrs that may
 /// be fused by the processor into a single operation.
 class MacroFusion : public ScheduleDAGMutation {
-  std::vector<MacroFusionPredTy> Predicates;
+  ShouldSchedulePredTy shouldScheduleAdjacent;
   bool FuseBlock;
   bool scheduleAdjacentImpl(ScheduleDAGInstrs &DAG, SUnit &AnchorSU);
 
 public:
-  MacroFusion(ArrayRef<MacroFusionPredTy> Predicates, bool FuseBlock)
-      : Predicates(Predicates.begin(), Predicates.end()), FuseBlock(FuseBlock) {
-  }
+  MacroFusion(ShouldSchedulePredTy shouldScheduleAdjacent, bool FuseBlock)
+    : shouldScheduleAdjacent(shouldScheduleAdjacent), FuseBlock(FuseBlock) {}
 
   void apply(ScheduleDAGInstrs *DAGInstrs) override;
-
-  bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
-                              const TargetSubtargetInfo &STI,
-                              const MachineInstr *FirstMI,
-                              const MachineInstr &SecondMI);
 };
 
 } // end anonymous namespace
 
-bool MacroFusion::shouldScheduleAdjacent(const TargetInstrInfo &TII,
-                                         const TargetSubtargetInfo &STI,
-                                         const MachineInstr *FirstMI,
-                                         const MachineInstr &SecondMI) {
-  return llvm::any_of(Predicates, [&](MacroFusionPredTy Predicate) {
-    return Predicate(TII, STI, FirstMI, SecondMI);
-  });
-}
-
 void MacroFusion::apply(ScheduleDAGInstrs *DAG) {
   if (FuseBlock)
     // For each of the SUnits in the scheduling block, try to fuse the instr in
@@ -212,15 +197,17 @@ bool MacroFusion::scheduleAdjacentImpl(ScheduleDAGInstrs &DAG, SUnit &AnchorSU)
 }
 
 std::unique_ptr<ScheduleDAGMutation>
-llvm::createMacroFusionDAGMutation(ArrayRef<MacroFusionPredTy> Predicates) {
-  if (EnableMacroFusion)
-    return std::make_unique<MacroFusion>(Predicates, true);
+llvm::createMacroFusionDAGMutation(
+     ShouldSchedulePredTy shouldScheduleAdjacent) {
+  if(EnableMacroFusion)
+    return std::make_unique<MacroFusion>(shouldScheduleAdjacent, true);
   return nullptr;
 }
 
-std::unique_ptr<ScheduleDAGMutation> llvm::createBranchMacroFusionDAGMutation(
-    ArrayRef<MacroFusionPredTy> Predicates) {
-  if (EnableMacroFusion)
-    return std::make_unique<MacroFusion>(Predicates, false);
+std::unique_ptr<ScheduleDAGMutation>
+llvm::createBranchMacroFusionDAGMutation(
+     ShouldSchedulePredTy shouldScheduleAdjacent) {
+  if(EnableMacroFusion)
+    return std::make_unique<MacroFusion>(shouldScheduleAdjacent, false);
   return nullptr;
 }
diff --git a/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp b/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
index 0bddeeef9e9b..29c9b9ccf276 100644
--- a/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
@@ -142,10 +142,10 @@ namespace {
 /// be turned into VOPD instructions
 /// Greedily pairs instruction candidates. O(n^2) algorithm.
 struct VOPDPairingMutation : ScheduleDAGMutation {
-  MacroFusionPredTy shouldScheduleAdjacent; // NOLINT: function pointer
+  ShouldSchedulePredTy shouldScheduleAdjacent; // NOLINT: function pointer
 
   VOPDPairingMutation(
-      MacroFusionPredTy shouldScheduleAdjacent) // NOLINT: function pointer
+      ShouldSchedulePredTy shouldScheduleAdjacent) // NOLINT: function pointer
       : shouldScheduleAdjacent(shouldScheduleAdjacent) {}
 
   void apply(ScheduleDAGInstrs *DAG) override {
-- 
GitLab


From 87e2e89019ec4405fa47c3b4585be4e67473b590 Mon Sep 17 00:00:00 2001
From: Billy Zhu <billyzhu@modular.com>
Date: Mon, 11 Dec 2023 19:31:54 -0800
Subject: [PATCH 216/349] [MLIR] Fuse locations of merged constants (#74670)

When merging constants by the operation folder, the location of the op
that remains should be updated to track the new meaning of this op. This
way we do not lose track of all possible source locations that the
constant op came from, and the final location of the op is less reliant
on the order of folding. This will also help debuggers understand how to
step these instructions.

This PR introduces a helper for operation folder to fuse another
location into the location of an op. When an op is deduplicated, fuse
the location of the op to be removed into the op that is retained. The
retained op now represents both original ops.

The FusedLoc will have a string metadata to help understand the reason
for the location fusion (motivated by the
[example](https://github.com/llvm/llvm-project/blob/71be8f3c23497e28c86f1135f564b16106d8d6fb/mlir/include/mlir/IR/BuiltinLocationAttributes.td#L130)
in the docstring of FusedLoc).
---
 mlir/include/mlir/Transforms/FoldUtils.h      | 12 ++++++-
 mlir/lib/Transforms/Utils/FoldUtils.cpp       | 35 ++++++++++++++++++-
 .../Transforms/canonicalize-debuginfo.mlir    | 34 ++++++++++++++++++
 .../Transforms/constant-fold-debuginfo.mlir   | 34 ++++++++++++++++++
 4 files changed, 113 insertions(+), 2 deletions(-)
 create mode 100644 mlir/test/Transforms/canonicalize-debuginfo.mlir
 create mode 100644 mlir/test/Transforms/constant-fold-debuginfo.mlir

diff --git a/mlir/include/mlir/Transforms/FoldUtils.h b/mlir/include/mlir/Transforms/FoldUtils.h
index 2600da361496..28fa18cf942d 100644
--- a/mlir/include/mlir/Transforms/FoldUtils.h
+++ b/mlir/include/mlir/Transforms/FoldUtils.h
@@ -33,7 +33,8 @@ class Value;
 class OperationFolder {
 public:
   OperationFolder(MLIRContext *ctx, OpBuilder::Listener *listener = nullptr)
-      : interfaces(ctx), rewriter(ctx, listener) {}
+      : fusedLocationTag(StringAttr::get(ctx, "CSE")), interfaces(ctx),
+        rewriter(ctx, listener) {}
 
   /// Tries to perform folding on the given `op`, including unifying
   /// deduplicated constants. If successful, replaces `op`'s uses with
@@ -95,6 +96,15 @@ private:
                                     Dialect *dialect, Attribute value,
                                     Type type, Location loc);
 
+  // Fuse `foldedLocation` into the Location of `retainedOp`. This will result
+  // in `retainedOp` having a FusedLoc with `fusedLocationTag` to help trace the
+  // source of the fusion. If `retainedOp` already had a FusedLoc with the same
+  // tag, `foldedLocation` will simply be appended to it.
+  void appendFoldedLocation(Operation *retainedOp, Location foldedLocation);
+
+  /// Tag for annotating fused locations as a result of merging constants.
+  StringAttr fusedLocationTag;
+
   /// A mapping between an insertion region and the constants that have been
   /// created within it.
   DenseMap<Region *, ConstantMap> foldScopes;
diff --git a/mlir/lib/Transforms/Utils/FoldUtils.cpp b/mlir/lib/Transforms/Utils/FoldUtils.cpp
index 90ee5ba51de3..dfc63ed6c4a5 100644
--- a/mlir/lib/Transforms/Utils/FoldUtils.cpp
+++ b/mlir/lib/Transforms/Utils/FoldUtils.cpp
@@ -141,6 +141,7 @@ bool OperationFolder::insertKnownConstant(Operation *op, Attribute constValue) {
   // If there is an existing constant, replace `op`.
   if (folderConstOp) {
     notifyRemoval(op);
+    appendFoldedLocation(folderConstOp, op->getLoc());
     rewriter.replaceOp(op, folderConstOp->getResults());
     return false;
   }
@@ -294,8 +295,10 @@ OperationFolder::tryGetOrCreateConstant(ConstantMap &uniquedConstants,
   // Check if an existing mapping already exists.
   auto constKey = std::make_tuple(dialect, value, type);
   Operation *&constOp = uniquedConstants[constKey];
-  if (constOp)
+  if (constOp) {
+    appendFoldedLocation(constOp, loc);
     return constOp;
+  }
 
   // If one doesn't exist, try to materialize one.
   if (!(constOp = materializeConstant(dialect, rewriter, value, type, loc)))
@@ -316,6 +319,7 @@ OperationFolder::tryGetOrCreateConstant(ConstantMap &uniquedConstants,
   // materialized operation in favor of the existing one.
   if (auto *existingOp = uniquedConstants.lookup(newKey)) {
     notifyRemoval(constOp);
+    appendFoldedLocation(existingOp, constOp->getLoc());
     rewriter.eraseOp(constOp);
     referencedDialects[existingOp].push_back(dialect);
     return constOp = existingOp;
@@ -326,3 +330,32 @@ OperationFolder::tryGetOrCreateConstant(ConstantMap &uniquedConstants,
   auto newIt = uniquedConstants.insert({newKey, constOp});
   return newIt.first->second;
 }
+
+void OperationFolder::appendFoldedLocation(Operation *retainedOp,
+                                           Location foldedLocation) {
+  // Append into existing fused location if it has the same tag.
+  if (auto existingFusedLoc =
+          dyn_cast<FusedLocWith<StringAttr>>(retainedOp->getLoc())) {
+    StringAttr existingMetadata = existingFusedLoc.getMetadata();
+    if (existingMetadata == fusedLocationTag) {
+      ArrayRef<Location> existingLocations = existingFusedLoc.getLocations();
+      SetVector<Location> locations(existingLocations.begin(),
+                                    existingLocations.end());
+      locations.insert(foldedLocation);
+      Location newFusedLoc = FusedLoc::get(
+          retainedOp->getContext(), locations.takeVector(), existingMetadata);
+      retainedOp->setLoc(newFusedLoc);
+      return;
+    }
+  }
+
+  // Create a new fusedloc with retainedOp's loc and foldedLocation.
+  // If they're already equal, no need to fuse.
+  if (retainedOp->getLoc() == foldedLocation)
+    return;
+
+  Location newFusedLoc =
+      FusedLoc::get(retainedOp->getContext(),
+                    {retainedOp->getLoc(), foldedLocation}, fusedLocationTag);
+  retainedOp->setLoc(newFusedLoc);
+}
diff --git a/mlir/test/Transforms/canonicalize-debuginfo.mlir b/mlir/test/Transforms/canonicalize-debuginfo.mlir
new file mode 100644
index 000000000000..034c9163a805
--- /dev/null
+++ b/mlir/test/Transforms/canonicalize-debuginfo.mlir
@@ -0,0 +1,34 @@
+// RUN: mlir-opt %s -pass-pipeline='builtin.module(func.func(canonicalize{test-convergence}))' -split-input-file -mlir-print-debuginfo | FileCheck %s
+
+// CHECK-LABEL: func @merge_constants
+func.func @merge_constants() -> (index, index, index, index) {
+  // CHECK-NEXT: arith.constant 42 : index loc(#[[FusedLoc:.*]])
+  %0 = arith.constant 42 : index loc("merge_constants":0:0)
+  %1 = arith.constant 42 : index loc("merge_constants":1:0)
+  %2 = arith.constant 42 : index loc("merge_constants":2:0)
+  %3 = arith.constant 42 : index loc("merge_constants":2:0) // repeated loc
+  return %0, %1, %2, %3: index, index, index, index
+}
+
+// CHECK-DAG: #[[LocConst0:.*]] = loc("merge_constants":0:0)
+// CHECK-DAG: #[[LocConst1:.*]] = loc("merge_constants":1:0)
+// CHECK-DAG: #[[LocConst2:.*]] = loc("merge_constants":2:0)
+// CHECK: #[[FusedLoc]] = loc(fused<"CSE">[#[[LocConst0]], #[[LocConst1]], #[[LocConst2]]])
+
+// -----
+
+// CHECK-LABEL: func @hoist_constant
+func.func @hoist_constant(%arg0: memref<8xi32>) {
+  // CHECK-NEXT: arith.constant 42 : i32 loc(#[[FusedLoc:.*]])
+  affine.for %arg1 = 0 to 8 {
+    %0 = arith.constant 42 : i32 loc("hoist_constant":0:0)
+    %1 = arith.constant 42 : i32 loc("hoist_constant":1:0)
+    memref.store %0, %arg0[%arg1] : memref<8xi32>
+    memref.store %1, %arg0[%arg1] : memref<8xi32>
+  }
+  return
+}
+
+// CHECK-DAG: #[[LocConst0:.*]] = loc("hoist_constant":0:0)
+// CHECK-DAG: #[[LocConst1:.*]] = loc("hoist_constant":1:0)
+// CHECK: #[[FusedLoc]] = loc(fused<"CSE">[#[[LocConst0]], #[[LocConst1]]])
diff --git a/mlir/test/Transforms/constant-fold-debuginfo.mlir b/mlir/test/Transforms/constant-fold-debuginfo.mlir
new file mode 100644
index 000000000000..79a25f860a48
--- /dev/null
+++ b/mlir/test/Transforms/constant-fold-debuginfo.mlir
@@ -0,0 +1,34 @@
+// RUN: mlir-opt %s -split-input-file -test-constant-fold -mlir-print-debuginfo | FileCheck %s
+
+// CHECK-LABEL: func @fold_and_merge
+func.func @fold_and_merge() -> (i32, i32) {
+  %0 = arith.constant 1 : i32
+  %1 = arith.constant 5 : i32
+
+  // CHECK-NEXT: [[C:%.+]] = arith.constant 6 : i32 loc(#[[FusedLoc:.*]])
+  %2 = arith.addi %0, %1 : i32 loc("fold_and_merge":0:0)
+
+  %3 = arith.constant 6 : i32 loc("fold_and_merge":1:0)
+
+  return %2, %3: i32, i32
+}
+
+// CHECK-DAG: #[[LocConst0:.*]] = loc("fold_and_merge":0:0)
+// CHECK-DAG: #[[LocConst1:.*]] = loc("fold_and_merge":1:0)
+// CHECK: #[[FusedLoc]] = loc(fused<"CSE">[#[[LocConst1]], #[[LocConst0]]])
+
+// -----
+
+// CHECK-LABEL: func @materialize_different_dialect
+func.func @materialize_different_dialect() -> (f32, f32) {
+  // CHECK: arith.constant 1.{{0*}}e+00 : f32 loc(#[[FusedLoc:.*]])
+  %0 = arith.constant -1.0 : f32
+  %1 = math.absf %0 : f32 loc("materialize_different_dialect":0:0)
+  %2 = arith.constant 1.0 : f32 loc("materialize_different_dialect":1:0)
+
+  return %1, %2: f32, f32
+}
+
+// CHECK-DAG: #[[LocConst0:.*]] = loc("materialize_different_dialect":0:0)
+// CHECK-DAG: #[[LocConst1:.*]] = loc("materialize_different_dialect":1:0)
+// CHECK: #[[FusedLoc]] = loc(fused<"CSE">[#[[LocConst1]], #[[LocConst0]]])
-- 
GitLab


From ce08c7ee1e86ec6d4c02e19db6724d16a578a48b Mon Sep 17 00:00:00 2001
From: paperchalice <liujunchang97@outlook.com>
Date: Tue, 12 Dec 2023 12:09:30 +0800
Subject: [PATCH 217/349] [CodeGen] Port `SelectOptimize` to new pass manager
 (#74920)

- Use `BlockFrequencyInfoWrapperPass` in legacy pass so member
`std::unique_ptr<BranchProbabilityInfo> BPI` could be removed.
- Member `DominatorTree *DT = nullptr` is unused, remove it.
---
 .../include/llvm/CodeGen/CodeGenPassBuilder.h |   6 +-
 .../llvm/CodeGen/MachinePassRegistry.def      |   2 +-
 llvm/include/llvm/CodeGen/SelectOptimize.h    |  34 ++++
 llvm/lib/CodeGen/SelectOptimize.cpp           | 174 ++++++++++++------
 llvm/lib/Passes/PassBuilder.cpp               |   1 +
 llvm/lib/Passes/PassRegistry.def              |   1 +
 llvm/test/CodeGen/AArch64/O3-pipeline.ll      |   3 +
 ...ert-highly-predictable-select-to-branch.ll |   4 +
 .../test/CodeGen/AArch64/selectopt-logical.ll |   1 +
 llvm/test/CodeGen/AArch64/selectopt.ll        |   7 +
 llvm/test/CodeGen/X86/select-optimize.ll      |   1 +
 11 files changed, 171 insertions(+), 63 deletions(-)
 create mode 100644 llvm/include/llvm/CodeGen/SelectOptimize.h

diff --git a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
index 4e704411270c..4f4f00b4e0e0 100644
--- a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
@@ -19,6 +19,7 @@
 #include "llvm/ADT/StringRef.h"
 #include "llvm/Analysis/AliasAnalysis.h"
 #include "llvm/Analysis/BasicAliasAnalysis.h"
+#include "llvm/Analysis/ProfileSummaryInfo.h"
 #include "llvm/Analysis/ScopedNoAliasAA.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Analysis/TypeBasedAliasAnalysis.h"
@@ -31,6 +32,7 @@
 #include "llvm/CodeGen/PreISelIntrinsicLowering.h"
 #include "llvm/CodeGen/ReplaceWithVeclib.h"
 #include "llvm/CodeGen/SafeStack.h"
+#include "llvm/CodeGen/SelectOptimize.h"
 #include "llvm/CodeGen/UnreachableBlockElim.h"
 #include "llvm/CodeGen/WasmEHPrepare.h"
 #include "llvm/CodeGen/WinEHPrepare.h"
@@ -470,6 +472,8 @@ Error CodeGenPassBuilder<Derived>::buildPipeline(
     raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut,
     CodeGenFileType FileType) const {
   AddIRPass addIRPass(MPM, Opt.DebugPM);
+  // `ProfileSummaryInfo` is always valid.
+  addIRPass(RequireAnalysisPass<ProfileSummaryAnalysis, Module>());
   addISelPasses(addIRPass);
 
   AddMachinePass addPass(MFPM);
@@ -657,7 +661,7 @@ void CodeGenPassBuilder<Derived>::addIRPasses(AddIRPass &addPass) const {
 
   // Convert conditional moves to conditional jumps when profitable.
   if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableSelectOptimize)
-    addPass(SelectOptimizePass());
+    addPass(SelectOptimizePass(&TM));
 }
 
 /// Turn exception handling constructs into something the code generators can
diff --git a/llvm/include/llvm/CodeGen/MachinePassRegistry.def b/llvm/include/llvm/CodeGen/MachinePassRegistry.def
index d92ff9b858ee..b98daa485cf8 100644
--- a/llvm/include/llvm/CodeGen/MachinePassRegistry.def
+++ b/llvm/include/llvm/CodeGen/MachinePassRegistry.def
@@ -54,6 +54,7 @@ FUNCTION_PASS("post-inline-ee-instrument", EntryExitInstrumenterPass, (true))
 FUNCTION_PASS("replace-with-veclib", ReplaceWithVeclib, ())
 FUNCTION_PASS("safe-stack", SafeStackPass, (TM))
 FUNCTION_PASS("scalarize-masked-mem-intrin", ScalarizeMaskedMemIntrinPass, ())
+FUNCTION_PASS("select-optimize", SelectOptimizePass, (TM))
 FUNCTION_PASS("tlshoist", TLSVariableHoistPass, ())
 FUNCTION_PASS("unreachableblockelim", UnreachableBlockElimPass, ())
 FUNCTION_PASS("verify", VerifierPass, ())
@@ -128,7 +129,6 @@ DUMMY_FUNCTION_PASS("codegenprepare", CodeGenPreparePass, ())
 DUMMY_FUNCTION_PASS("expandmemcmp", ExpandMemCmpPass, ())
 DUMMY_FUNCTION_PASS("gc-lowering", GCLoweringPass, ())
 DUMMY_FUNCTION_PASS("indirectbr-expand", IndirectBrExpandPass, ())
-DUMMY_FUNCTION_PASS("select-optimize", SelectOptimizePass, ())
 DUMMY_FUNCTION_PASS("shadow-stack-gc-lowering", ShadowStackGCLoweringPass, ())
 DUMMY_FUNCTION_PASS("sjljehprepare", SjLjEHPreparePass, ())
 DUMMY_FUNCTION_PASS("stack-protector", StackProtectorPass, ())
diff --git a/llvm/include/llvm/CodeGen/SelectOptimize.h b/llvm/include/llvm/CodeGen/SelectOptimize.h
new file mode 100644
index 000000000000..37024a154145
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/SelectOptimize.h
@@ -0,0 +1,34 @@
+//===--- llvm/CodeGen/SelectOptimize.h ---------------------------*- C++ -*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// This file contains the declaration of the SelectOptimizePass class,
+/// its corresponding pass name is `select-optimize`.
+///
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_SELECTOPTIMIZE_H
+#define LLVM_CODEGEN_SELECTOPTIMIZE_H
+
+#include "llvm/IR/PassManager.h"
+
+namespace llvm {
+
+class TargetMachine;
+
+class SelectOptimizePass : public PassInfoMixin<SelectOptimizePass> {
+  const TargetMachine *TM;
+
+public:
+  explicit SelectOptimizePass(const TargetMachine *TM) : TM(TM) {}
+  PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM);
+};
+
+} // namespace llvm
+
+#endif // LLVM_CODEGEN_SELECTOPTIMIZE_H
diff --git a/llvm/lib/CodeGen/SelectOptimize.cpp b/llvm/lib/CodeGen/SelectOptimize.cpp
index 05413fb5d758..1316919e65da 100644
--- a/llvm/lib/CodeGen/SelectOptimize.cpp
+++ b/llvm/lib/CodeGen/SelectOptimize.cpp
@@ -10,6 +10,7 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "llvm/CodeGen/SelectOptimize.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/Analysis/BlockFrequencyInfo.h"
@@ -96,36 +97,22 @@ static cl::opt<bool>
 
 namespace {
 
-class SelectOptimize : public FunctionPass {
+class SelectOptimizeImpl {
   const TargetMachine *TM = nullptr;
   const TargetSubtargetInfo *TSI = nullptr;
   const TargetLowering *TLI = nullptr;
   const TargetTransformInfo *TTI = nullptr;
   const LoopInfo *LI = nullptr;
-  DominatorTree *DT = nullptr;
-  std::unique_ptr<BlockFrequencyInfo> BFI;
-  std::unique_ptr<BranchProbabilityInfo> BPI;
+  BlockFrequencyInfo *BFI;
   ProfileSummaryInfo *PSI = nullptr;
   OptimizationRemarkEmitter *ORE = nullptr;
   TargetSchedModel TSchedModel;
 
 public:
-  static char ID;
-
-  SelectOptimize() : FunctionPass(ID) {
-    initializeSelectOptimizePass(*PassRegistry::getPassRegistry());
-  }
-
-  bool runOnFunction(Function &F) override;
-
-  void getAnalysisUsage(AnalysisUsage &AU) const override {
-    AU.addRequired<ProfileSummaryInfoWrapperPass>();
-    AU.addRequired<TargetPassConfig>();
-    AU.addRequired<TargetTransformInfoWrapperPass>();
-    AU.addRequired<DominatorTreeWrapperPass>();
-    AU.addRequired<LoopInfoWrapperPass>();
-    AU.addRequired<OptimizationRemarkEmitterWrapperPass>();
-  }
+  SelectOptimizeImpl() = default;
+  SelectOptimizeImpl(const TargetMachine *TM) : TM(TM){};
+  PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM);
+  bool runOnFunction(Function &F, Pass &P);
 
 private:
   // Select groups consist of consecutive select instructions with the same
@@ -211,29 +198,94 @@ private:
   // Returns true if the target architecture supports lowering a given select.
   bool isSelectKindSupported(SelectInst *SI);
 };
+
+class SelectOptimize : public FunctionPass {
+  SelectOptimizeImpl Impl;
+
+public:
+  static char ID;
+
+  SelectOptimize() : FunctionPass(ID) {
+    initializeSelectOptimizePass(*PassRegistry::getPassRegistry());
+  }
+
+  bool runOnFunction(Function &F) override {
+    return Impl.runOnFunction(F, *this);
+  }
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.addRequired<ProfileSummaryInfoWrapperPass>();
+    AU.addRequired<TargetPassConfig>();
+    AU.addRequired<TargetTransformInfoWrapperPass>();
+    AU.addRequired<LoopInfoWrapperPass>();
+    AU.addRequired<BlockFrequencyInfoWrapperPass>();
+    AU.addRequired<OptimizationRemarkEmitterWrapperPass>();
+  }
+};
+
 } // namespace
 
+PreservedAnalyses SelectOptimizePass::run(Function &F,
+                                          FunctionAnalysisManager &FAM) {
+  SelectOptimizeImpl Impl(TM);
+  return Impl.run(F, FAM);
+}
+
 char SelectOptimize::ID = 0;
 
 INITIALIZE_PASS_BEGIN(SelectOptimize, DEBUG_TYPE, "Optimize selects", false,
                       false)
 INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
 INITIALIZE_PASS_DEPENDENCY(ProfileSummaryInfoWrapperPass)
 INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
 INITIALIZE_PASS_DEPENDENCY(TargetTransformInfoWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(BlockFrequencyInfoWrapperPass)
 INITIALIZE_PASS_DEPENDENCY(OptimizationRemarkEmitterWrapperPass)
 INITIALIZE_PASS_END(SelectOptimize, DEBUG_TYPE, "Optimize selects", false,
                     false)
 
 FunctionPass *llvm::createSelectOptimizePass() { return new SelectOptimize(); }
 
-bool SelectOptimize::runOnFunction(Function &F) {
-  TM = &getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
+PreservedAnalyses SelectOptimizeImpl::run(Function &F,
+                                          FunctionAnalysisManager &FAM) {
+  TSI = TM->getSubtargetImpl(F);
+  TLI = TSI->getTargetLowering();
+
+  // If none of the select types are supported then skip this pass.
+  // This is an optimization pass. Legality issues will be handled by
+  // instruction selection.
+  if (!TLI->isSelectSupported(TargetLowering::ScalarValSelect) &&
+      !TLI->isSelectSupported(TargetLowering::ScalarCondVectorVal) &&
+      !TLI->isSelectSupported(TargetLowering::VectorMaskSelect))
+    return PreservedAnalyses::all();
+
+  TTI = &FAM.getResult<TargetIRAnalysis>(F);
+  if (!TTI->enableSelectOptimize())
+    return PreservedAnalyses::all();
+
+  PSI = FAM.getResult<ModuleAnalysisManagerFunctionProxy>(F)
+            .getCachedResult<ProfileSummaryAnalysis>(*F.getParent());
+  assert(PSI && "This pass requires module analysis pass `profile-summary`!");
+  BFI = &FAM.getResult<BlockFrequencyAnalysis>(F);
+
+  // When optimizing for size, selects are preferable over branches.
+  if (F.hasOptSize() || llvm::shouldOptimizeForSize(&F, PSI, BFI))
+    return PreservedAnalyses::all();
+
+  LI = &FAM.getResult<LoopAnalysis>(F);
+  ORE = &FAM.getResult<OptimizationRemarkEmitterAnalysis>(F);
+  TSchedModel.init(TSI);
+
+  bool Changed = optimizeSelects(F);
+  return Changed ? PreservedAnalyses::none() : PreservedAnalyses::all();
+}
+
+bool SelectOptimizeImpl::runOnFunction(Function &F, Pass &P) {
+  TM = &P.getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
   TSI = TM->getSubtargetImpl(F);
   TLI = TSI->getTargetLowering();
 
-  // If none of the select types is supported then skip this pass.
+  // If none of the select types are supported then skip this pass.
   // This is an optimization pass. Legality issues will be handled by
   // instruction selection.
   if (!TLI->isSelectSupported(TargetLowering::ScalarValSelect) &&
@@ -241,27 +293,25 @@ bool SelectOptimize::runOnFunction(Function &F) {
       !TLI->isSelectSupported(TargetLowering::VectorMaskSelect))
     return false;
 
-  TTI = &getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
+  TTI = &P.getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
 
   if (!TTI->enableSelectOptimize())
     return false;
 
-  DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
-  LI = &getAnalysis<LoopInfoWrapperPass>().getLoopInfo();
-  BPI.reset(new BranchProbabilityInfo(F, *LI));
-  BFI.reset(new BlockFrequencyInfo(F, *BPI, *LI));
-  PSI = &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
-  ORE = &getAnalysis<OptimizationRemarkEmitterWrapperPass>().getORE();
+  LI = &P.getAnalysis<LoopInfoWrapperPass>().getLoopInfo();
+  BFI = &P.getAnalysis<BlockFrequencyInfoWrapperPass>().getBFI();
+  PSI = &P.getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
+  ORE = &P.getAnalysis<OptimizationRemarkEmitterWrapperPass>().getORE();
   TSchedModel.init(TSI);
 
   // When optimizing for size, selects are preferable over branches.
-  if (F.hasOptSize() || llvm::shouldOptimizeForSize(&F, PSI, BFI.get()))
+  if (F.hasOptSize() || llvm::shouldOptimizeForSize(&F, PSI, BFI))
     return false;
 
   return optimizeSelects(F);
 }
 
-bool SelectOptimize::optimizeSelects(Function &F) {
+bool SelectOptimizeImpl::optimizeSelects(Function &F) {
   // Determine for which select groups it is profitable converting to branches.
   SelectGroups ProfSIGroups;
   // Base heuristics apply only to non-loops and outer loops.
@@ -277,8 +327,8 @@ bool SelectOptimize::optimizeSelects(Function &F) {
   return !ProfSIGroups.empty();
 }
 
-void SelectOptimize::optimizeSelectsBase(Function &F,
-                                         SelectGroups &ProfSIGroups) {
+void SelectOptimizeImpl::optimizeSelectsBase(Function &F,
+                                             SelectGroups &ProfSIGroups) {
   // Collect all the select groups.
   SelectGroups SIGroups;
   for (BasicBlock &BB : F) {
@@ -293,8 +343,8 @@ void SelectOptimize::optimizeSelectsBase(Function &F,
   findProfitableSIGroupsBase(SIGroups, ProfSIGroups);
 }
 
-void SelectOptimize::optimizeSelectsInnerLoops(Function &F,
-                                               SelectGroups &ProfSIGroups) {
+void SelectOptimizeImpl::optimizeSelectsInnerLoops(Function &F,
+                                                   SelectGroups &ProfSIGroups) {
   SmallVector<Loop *, 4> Loops(LI->begin(), LI->end());
   // Need to check size on each iteration as we accumulate child loops.
   for (unsigned long i = 0; i < Loops.size(); ++i)
@@ -331,7 +381,7 @@ getTrueOrFalseValue(SelectInst *SI, bool isTrue,
   return V;
 }
 
-void SelectOptimize::convertProfitableSIGroups(SelectGroups &ProfSIGroups) {
+void SelectOptimizeImpl::convertProfitableSIGroups(SelectGroups &ProfSIGroups) {
   for (SelectGroup &ASI : ProfSIGroups) {
     // The code transformation here is a modified version of the sinking
     // transformation in CodeGenPrepare::optimizeSelectInst with a more
@@ -531,8 +581,8 @@ static bool isSpecialSelect(SelectInst *SI) {
   return false;
 }
 
-void SelectOptimize::collectSelectGroups(BasicBlock &BB,
-                                         SelectGroups &SIGroups) {
+void SelectOptimizeImpl::collectSelectGroups(BasicBlock &BB,
+                                             SelectGroups &SIGroups) {
   BasicBlock::iterator BBIt = BB.begin();
   while (BBIt != BB.end()) {
     Instruction *I = &*BBIt++;
@@ -565,8 +615,8 @@ void SelectOptimize::collectSelectGroups(BasicBlock &BB,
   }
 }
 
-void SelectOptimize::findProfitableSIGroupsBase(SelectGroups &SIGroups,
-                                                SelectGroups &ProfSIGroups) {
+void SelectOptimizeImpl::findProfitableSIGroupsBase(
+    SelectGroups &SIGroups, SelectGroups &ProfSIGroups) {
   for (SelectGroup &ASI : SIGroups) {
     ++NumSelectOptAnalyzed;
     if (isConvertToBranchProfitableBase(ASI))
@@ -580,14 +630,14 @@ static void EmitAndPrintRemark(OptimizationRemarkEmitter *ORE,
   ORE->emit(Rem);
 }
 
-void SelectOptimize::findProfitableSIGroupsInnerLoops(
+void SelectOptimizeImpl::findProfitableSIGroupsInnerLoops(
     const Loop *L, SelectGroups &SIGroups, SelectGroups &ProfSIGroups) {
   NumSelectOptAnalyzed += SIGroups.size();
   // For each select group in an inner-most loop,
   // a branch is more preferable than a select/conditional-move if:
   // i) conversion to branches for all the select groups of the loop satisfies
   //    loop-level heuristics including reducing the loop's critical path by
-  //    some threshold (see SelectOptimize::checkLoopHeuristics); and
+  //    some threshold (see SelectOptimizeImpl::checkLoopHeuristics); and
   // ii) the total cost of the select group is cheaper with a branch compared
   //     to its predicated version. The cost is in terms of latency and the cost
   //     of a select group is the cost of its most expensive select instruction
@@ -627,7 +677,7 @@ void SelectOptimize::findProfitableSIGroupsInnerLoops(
   }
 }
 
-bool SelectOptimize::isConvertToBranchProfitableBase(
+bool SelectOptimizeImpl::isConvertToBranchProfitableBase(
     const SmallVector<SelectInst *, 2> &ASI) {
   SelectInst *SI = ASI.front();
   LLVM_DEBUG(dbgs() << "Analyzing select group containing " << *SI << "\n");
@@ -635,7 +685,7 @@ bool SelectOptimize::isConvertToBranchProfitableBase(
   OptimizationRemarkMissed ORmiss(DEBUG_TYPE, "SelectOpti", SI);
 
   // Skip cold basic blocks. Better to optimize for size for cold blocks.
-  if (PSI->isColdBlock(SI->getParent(), BFI.get())) {
+  if (PSI->isColdBlock(SI->getParent(), BFI)) {
     ++NumSelectColdBB;
     ORmiss << "Not converted to branch because of cold basic block. ";
     EmitAndPrintRemark(ORE, ORmiss);
@@ -678,7 +728,7 @@ static InstructionCost divideNearest(InstructionCost Numerator,
   return (Numerator + (Denominator / 2)) / Denominator;
 }
 
-bool SelectOptimize::hasExpensiveColdOperand(
+bool SelectOptimizeImpl::hasExpensiveColdOperand(
     const SmallVector<SelectInst *, 2> &ASI) {
   bool ColdOperand = false;
   uint64_t TrueWeight, FalseWeight, TotalWeight;
@@ -752,9 +802,10 @@ static bool isSafeToSinkLoad(Instruction *LoadI, Instruction *SI) {
 // (sufficiently-accurate in practice), we populate this set with the
 // instructions of the backwards dependence slice that only have one-use and
 // form an one-use chain that leads to the source instruction.
-void SelectOptimize::getExclBackwardsSlice(Instruction *I,
-                                           std::stack<Instruction *> &Slice,
-                                           Instruction *SI, bool ForSinking) {
+void SelectOptimizeImpl::getExclBackwardsSlice(Instruction *I,
+                                               std::stack<Instruction *> &Slice,
+                                               Instruction *SI,
+                                               bool ForSinking) {
   SmallPtrSet<Instruction *, 2> Visited;
   std::queue<Instruction *> Worklist;
   Worklist.push(I);
@@ -798,7 +849,7 @@ void SelectOptimize::getExclBackwardsSlice(Instruction *I,
   }
 }
 
-bool SelectOptimize::isSelectHighlyPredictable(const SelectInst *SI) {
+bool SelectOptimizeImpl::isSelectHighlyPredictable(const SelectInst *SI) {
   uint64_t TrueWeight, FalseWeight;
   if (extractBranchWeights(*SI, TrueWeight, FalseWeight)) {
     uint64_t Max = std::max(TrueWeight, FalseWeight);
@@ -812,8 +863,8 @@ bool SelectOptimize::isSelectHighlyPredictable(const SelectInst *SI) {
   return false;
 }
 
-bool SelectOptimize::checkLoopHeuristics(const Loop *L,
-                                         const CostInfo LoopCost[2]) {
+bool SelectOptimizeImpl::checkLoopHeuristics(const Loop *L,
+                                             const CostInfo LoopCost[2]) {
   // Loop-level checks to determine if a non-predicated version (with branches)
   // of the loop is more profitable than its predicated version.
 
@@ -881,7 +932,7 @@ bool SelectOptimize::checkLoopHeuristics(const Loop *L,
 // and non-predicated version of the given loop.
 // Returns false if unable to compute these costs due to invalid cost of loop
 // instruction(s).
-bool SelectOptimize::computeLoopCosts(
+bool SelectOptimizeImpl::computeLoopCosts(
     const Loop *L, const SelectGroups &SIGroups,
     DenseMap<const Instruction *, CostInfo> &InstCostMap, CostInfo *LoopCost) {
   LLVM_DEBUG(dbgs() << "Calculating Latency / IPredCost / INonPredCost of loop "
@@ -969,7 +1020,7 @@ bool SelectOptimize::computeLoopCosts(
 }
 
 SmallPtrSet<const Instruction *, 2>
-SelectOptimize::getSIset(const SelectGroups &SIGroups) {
+SelectOptimizeImpl::getSIset(const SelectGroups &SIGroups) {
   SmallPtrSet<const Instruction *, 2> SIset;
   for (const SelectGroup &ASI : SIGroups)
     for (const SelectInst *SI : ASI)
@@ -977,7 +1028,8 @@ SelectOptimize::getSIset(const SelectGroups &SIGroups) {
   return SIset;
 }
 
-std::optional<uint64_t> SelectOptimize::computeInstCost(const Instruction *I) {
+std::optional<uint64_t>
+SelectOptimizeImpl::computeInstCost(const Instruction *I) {
   InstructionCost ICost =
       TTI->getInstructionCost(I, TargetTransformInfo::TCK_Latency);
   if (auto OC = ICost.getValue())
@@ -986,8 +1038,8 @@ std::optional<uint64_t> SelectOptimize::computeInstCost(const Instruction *I) {
 }
 
 ScaledNumber<uint64_t>
-SelectOptimize::getMispredictionCost(const SelectInst *SI,
-                                     const Scaled64 CondCost) {
+SelectOptimizeImpl::getMispredictionCost(const SelectInst *SI,
+                                         const Scaled64 CondCost) {
   uint64_t MispredictPenalty = TSchedModel.getMCSchedModel()->MispredictPenalty;
 
   // Account for the default misprediction rate when using a branch
@@ -1012,8 +1064,8 @@ SelectOptimize::getMispredictionCost(const SelectInst *SI,
 // Returns the cost of a branch when the prediction is correct.
 // TrueCost * TrueProbability + FalseCost * FalseProbability.
 ScaledNumber<uint64_t>
-SelectOptimize::getPredictedPathCost(Scaled64 TrueCost, Scaled64 FalseCost,
-                                     const SelectInst *SI) {
+SelectOptimizeImpl::getPredictedPathCost(Scaled64 TrueCost, Scaled64 FalseCost,
+                                         const SelectInst *SI) {
   Scaled64 PredPathCost;
   uint64_t TrueWeight, FalseWeight;
   if (extractBranchWeights(*SI, TrueWeight, FalseWeight)) {
@@ -1033,7 +1085,7 @@ SelectOptimize::getPredictedPathCost(Scaled64 TrueCost, Scaled64 FalseCost,
   return PredPathCost;
 }
 
-bool SelectOptimize::isSelectKindSupported(SelectInst *SI) {
+bool SelectOptimizeImpl::isSelectKindSupported(SelectInst *SI) {
   bool VectorCond = !SI->getCondition()->getType()->isIntegerTy(1);
   if (VectorCond)
     return false;
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index 0608e1b2201b..41f1ce966ad2 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -80,6 +80,7 @@
 #include "llvm/CodeGen/InterleavedAccess.h"
 #include "llvm/CodeGen/JMCInstrumenter.h"
 #include "llvm/CodeGen/SafeStack.h"
+#include "llvm/CodeGen/SelectOptimize.h"
 #include "llvm/CodeGen/TypePromotion.h"
 #include "llvm/CodeGen/WasmEHPrepare.h"
 #include "llvm/CodeGen/WinEHPrepare.h"
diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def
index d49e35db8722..9afb73b2e8c1 100644
--- a/llvm/lib/Passes/PassRegistry.def
+++ b/llvm/lib/Passes/PassRegistry.def
@@ -397,6 +397,7 @@ FUNCTION_PASS("safe-stack", SafeStackPass(TM))
 FUNCTION_PASS("scalarize-masked-mem-intrin", ScalarizeMaskedMemIntrinPass())
 FUNCTION_PASS("scalarizer", ScalarizerPass())
 FUNCTION_PASS("sccp", SCCPPass())
+FUNCTION_PASS("select-optimize", SelectOptimizePass(TM))
 FUNCTION_PASS("separate-const-offset-from-gep",
               SeparateConstOffsetFromGEPPass())
 FUNCTION_PASS("sink", SinkingPass())
diff --git a/llvm/test/CodeGen/AArch64/O3-pipeline.ll b/llvm/test/CodeGen/AArch64/O3-pipeline.ll
index f5c1c3c291cb..638f26298ee2 100644
--- a/llvm/test/CodeGen/AArch64/O3-pipeline.ll
+++ b/llvm/test/CodeGen/AArch64/O3-pipeline.ll
@@ -66,6 +66,9 @@
 ; CHECK-NEXT:       Expand reduction intrinsics
 ; CHECK-NEXT:       Natural Loop Information
 ; CHECK-NEXT:       TLS Variable Hoist
+; CHECK-NEXT:       Post-Dominator Tree Construction
+; CHECK-NEXT:       Branch Probability Analysis
+; CHECK-NEXT:       Block Frequency Analysis
 ; CHECK-NEXT:       Lazy Branch Probability Analysis
 ; CHECK-NEXT:       Lazy Block Frequency Analysis
 ; CHECK-NEXT:       Optimization Remark Emitter
diff --git a/llvm/test/CodeGen/AArch64/convert-highly-predictable-select-to-branch.ll b/llvm/test/CodeGen/AArch64/convert-highly-predictable-select-to-branch.ll
index 156ec400d5e7..22fa8b100533 100644
--- a/llvm/test/CodeGen/AArch64/convert-highly-predictable-select-to-branch.ll
+++ b/llvm/test/CodeGen/AArch64/convert-highly-predictable-select-to-branch.ll
@@ -3,6 +3,10 @@
 ; RUN: opt -select-optimize -mtriple=aarch64-linux-gnu -mcpu=neoverse-n1 -S < %s | FileCheck %s
 ; RUN: opt -select-optimize -mtriple=aarch64-linux-gnu -mcpu=neoverse-v2 -S < %s | FileCheck %s
 ; RUN: opt -select-optimize -mtriple=aarch64-linux-gnu -mcpu=cortex-a72 -S < %s | FileCheck %s
+; RUN: opt -passes='require<profile-summary>,function(select-optimize)' -mtriple=aarch64-linux-gnu -mcpu=generic -S < %s | FileCheck %s --check-prefix=CHECK-GENERIC
+; RUN: opt -passes='require<profile-summary>,function(select-optimize)' -mtriple=aarch64-linux-gnu -mcpu=neoverse-n1 -S < %s | FileCheck %s
+; RUN: opt -passes='require<profile-summary>,function(select-optimize)' -mtriple=aarch64-linux-gnu -mcpu=neoverse-v2 -S < %s | FileCheck %s
+; RUN: opt -passes='require<profile-summary>,function(select-optimize)' -mtriple=aarch64-linux-gnu -mcpu=cortex-a72 -S < %s | FileCheck %s
 
 ; Test has not predictable select, which should not be transformed to a branch
 define i32 @test1(i32 %a) {
diff --git a/llvm/test/CodeGen/AArch64/selectopt-logical.ll b/llvm/test/CodeGen/AArch64/selectopt-logical.ll
index 635922e272c4..b8cc896b61d4 100644
--- a/llvm/test/CodeGen/AArch64/selectopt-logical.ll
+++ b/llvm/test/CodeGen/AArch64/selectopt-logical.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -select-optimize -mtriple=aarch64-linux-gnu -mcpu=neoverse-v2 -S < %s | FileCheck %s
+; RUN: opt -passes='require<profile-summary>,function(select-optimize)' -mtriple=aarch64-linux-gnu -mcpu=neoverse-v2 -S < %s | FileCheck %s
 
 define i32 @test(ptr nocapture noundef readnone %x, i32 noundef %iters) {
 ; CHECK-LABEL: @test(
diff --git a/llvm/test/CodeGen/AArch64/selectopt.ll b/llvm/test/CodeGen/AArch64/selectopt.ll
index 46ac585b6d55..8922eba0406c 100644
--- a/llvm/test/CodeGen/AArch64/selectopt.ll
+++ b/llvm/test/CodeGen/AArch64/selectopt.ll
@@ -6,6 +6,13 @@
 ; RUN: opt -select-optimize -mtriple=aarch64-linux-gnu -mcpu=neoverse-n1 -S < %s | FileCheck %s --check-prefix=CHECKOO
 ; RUN: opt -select-optimize -mtriple=aarch64-linux-gnu -mcpu=cortex-a710 -S < %s | FileCheck %s --check-prefix=CHECKOO
 ; RUN: opt -select-optimize -mtriple=aarch64-linux-gnu -mcpu=neoverse-v2 -S < %s | FileCheck %s --check-prefix=CHECKOO
+; RUN: opt -passes='require<profile-summary>,function(select-optimize)' -mtriple=aarch64-linux-gnu -mcpu=generic -S < %s | FileCheck %s --check-prefix=CHECKOO
+; RUN: opt -passes='require<profile-summary>,function(select-optimize)' -mtriple=aarch64-linux-gnu -mcpu=cortex-a55 -S < %s | FileCheck %s --check-prefix=CHECKII
+; RUN: opt -passes='require<profile-summary>,function(select-optimize)' -mtriple=aarch64-linux-gnu -mcpu=cortex-a510 -S < %s | FileCheck %s --check-prefix=CHECKII
+; RUN: opt -passes='require<profile-summary>,function(select-optimize)' -mtriple=aarch64-linux-gnu -mcpu=cortex-a72 -S < %s | FileCheck %s --check-prefix=CHECKOO
+; RUN: opt -passes='require<profile-summary>,function(select-optimize)' -mtriple=aarch64-linux-gnu -mcpu=neoverse-n1 -S < %s | FileCheck %s --check-prefix=CHECKOO
+; RUN: opt -passes='require<profile-summary>,function(select-optimize)' -mtriple=aarch64-linux-gnu -mcpu=cortex-a710 -S < %s | FileCheck %s --check-prefix=CHECKOO
+; RUN: opt -passes='require<profile-summary>,function(select-optimize)' -mtriple=aarch64-linux-gnu -mcpu=neoverse-v2 -S < %s | FileCheck %s --check-prefix=CHECKOO
 
 %struct.st = type { i32, i64, ptr, ptr, i16, ptr, ptr, i64, i64 }
 
diff --git a/llvm/test/CodeGen/X86/select-optimize.ll b/llvm/test/CodeGen/X86/select-optimize.ll
index a53dd36d813e..6e4406544087 100644
--- a/llvm/test/CodeGen/X86/select-optimize.ll
+++ b/llvm/test/CodeGen/X86/select-optimize.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -mtriple=x86_64-unknown-unknown -select-optimize -S < %s | FileCheck %s
+; RUN: opt -mtriple=x86_64-unknown-unknown -passes='require<profile-summary>,function(select-optimize)' -S < %s | FileCheck %s
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;; Test base heuristic 1:
-- 
GitLab


From d11e54f3fe697e2f6a88ed45c12622ccdb55c2e7 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp@bytedance.com>
Date: Tue, 12 Dec 2023 11:18:31 +0800
Subject: [PATCH 218/349] [MacroFusion] Support multiple predicators (#72219)

The user can provide multiple predicators to MacroFusion and the
DAG mutation will be applied if one of them is evalated to true.

`ShouldSchedulePredTy` is renamed to `MacroFusionPredTy`.
---
 llvm/include/llvm/CodeGen/MacroFusion.h | 20 +++++++------
 llvm/lib/CodeGen/MacroFusion.cpp        | 37 +++++++++++++++++--------
 llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp |  4 +--
 3 files changed, 38 insertions(+), 23 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/MacroFusion.h b/llvm/include/llvm/CodeGen/MacroFusion.h
index ea2c7a5faae3..a359fca60426 100644
--- a/llvm/include/llvm/CodeGen/MacroFusion.h
+++ b/llvm/include/llvm/CodeGen/MacroFusion.h
@@ -14,7 +14,7 @@
 #ifndef LLVM_CODEGEN_MACROFUSION_H
 #define LLVM_CODEGEN_MACROFUSION_H
 
-#include <functional>
+#include "llvm/ADT/ArrayRef.h"
 #include <memory>
 
 namespace llvm {
@@ -29,10 +29,10 @@ class SUnit;
 /// Check if the instr pair, FirstMI and SecondMI, should be fused
 /// together. Given SecondMI, when FirstMI is unspecified, then check if
 /// SecondMI may be part of a fused pair at all.
-using ShouldSchedulePredTy = std::function<bool(const TargetInstrInfo &TII,
-                                                const TargetSubtargetInfo &TSI,
-                                                const MachineInstr *FirstMI,
-                                                const MachineInstr &SecondMI)>;
+using MacroFusionPredTy = bool (*)(const TargetInstrInfo &TII,
+                                   const TargetSubtargetInfo &STI,
+                                   const MachineInstr *FirstMI,
+                                   const MachineInstr &SecondMI);
 
 /// Checks if the number of cluster edges between SU and its predecessors is
 /// less than FuseLimit
@@ -48,15 +48,17 @@ bool fuseInstructionPair(ScheduleDAGInstrs &DAG, SUnit &FirstSU,
 
 /// Create a DAG scheduling mutation to pair instructions back to back
 /// for instructions that benefit according to the target-specific
-/// shouldScheduleAdjacent predicate function.
+/// predicate functions. shouldScheduleAdjacent will be true if any of the
+/// provided predicates are true.
 std::unique_ptr<ScheduleDAGMutation>
-createMacroFusionDAGMutation(ShouldSchedulePredTy shouldScheduleAdjacent);
+createMacroFusionDAGMutation(ArrayRef<MacroFusionPredTy> Predicates);
 
 /// Create a DAG scheduling mutation to pair branch instructions with one
 /// of their predecessors back to back for instructions that benefit according
-/// to the target-specific shouldScheduleAdjacent predicate function.
+/// to the target-specific predicate functions. shouldScheduleAdjacent will be
+/// true if any of the provided predicates are true.
 std::unique_ptr<ScheduleDAGMutation>
-createBranchMacroFusionDAGMutation(ShouldSchedulePredTy shouldScheduleAdjacent);
+createBranchMacroFusionDAGMutation(ArrayRef<MacroFusionPredTy> Predicates);
 
 } // end namespace llvm
 
diff --git a/llvm/lib/CodeGen/MacroFusion.cpp b/llvm/lib/CodeGen/MacroFusion.cpp
index fa5df68b8abc..aff4d95781f4 100644
--- a/llvm/lib/CodeGen/MacroFusion.cpp
+++ b/llvm/lib/CodeGen/MacroFusion.cpp
@@ -137,19 +137,34 @@ namespace {
 /// Post-process the DAG to create cluster edges between instrs that may
 /// be fused by the processor into a single operation.
 class MacroFusion : public ScheduleDAGMutation {
-  ShouldSchedulePredTy shouldScheduleAdjacent;
+  std::vector<MacroFusionPredTy> Predicates;
   bool FuseBlock;
   bool scheduleAdjacentImpl(ScheduleDAGInstrs &DAG, SUnit &AnchorSU);
 
 public:
-  MacroFusion(ShouldSchedulePredTy shouldScheduleAdjacent, bool FuseBlock)
-    : shouldScheduleAdjacent(shouldScheduleAdjacent), FuseBlock(FuseBlock) {}
+  MacroFusion(ArrayRef<MacroFusionPredTy> Predicates, bool FuseBlock)
+      : Predicates(Predicates.begin(), Predicates.end()), FuseBlock(FuseBlock) {
+  }
 
   void apply(ScheduleDAGInstrs *DAGInstrs) override;
+
+  bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
+                              const TargetSubtargetInfo &STI,
+                              const MachineInstr *FirstMI,
+                              const MachineInstr &SecondMI);
 };
 
 } // end anonymous namespace
 
+bool MacroFusion::shouldScheduleAdjacent(const TargetInstrInfo &TII,
+                                         const TargetSubtargetInfo &STI,
+                                         const MachineInstr *FirstMI,
+                                         const MachineInstr &SecondMI) {
+  return llvm::any_of(Predicates, [&](MacroFusionPredTy Predicate) {
+    return Predicate(TII, STI, FirstMI, SecondMI);
+  });
+}
+
 void MacroFusion::apply(ScheduleDAGInstrs *DAG) {
   if (FuseBlock)
     // For each of the SUnits in the scheduling block, try to fuse the instr in
@@ -197,17 +212,15 @@ bool MacroFusion::scheduleAdjacentImpl(ScheduleDAGInstrs &DAG, SUnit &AnchorSU)
 }
 
 std::unique_ptr<ScheduleDAGMutation>
-llvm::createMacroFusionDAGMutation(
-     ShouldSchedulePredTy shouldScheduleAdjacent) {
-  if(EnableMacroFusion)
-    return std::make_unique<MacroFusion>(shouldScheduleAdjacent, true);
+llvm::createMacroFusionDAGMutation(ArrayRef<MacroFusionPredTy> Predicates) {
+  if (EnableMacroFusion)
+    return std::make_unique<MacroFusion>(Predicates, true);
   return nullptr;
 }
 
-std::unique_ptr<ScheduleDAGMutation>
-llvm::createBranchMacroFusionDAGMutation(
-     ShouldSchedulePredTy shouldScheduleAdjacent) {
-  if(EnableMacroFusion)
-    return std::make_unique<MacroFusion>(shouldScheduleAdjacent, false);
+std::unique_ptr<ScheduleDAGMutation> llvm::createBranchMacroFusionDAGMutation(
+    ArrayRef<MacroFusionPredTy> Predicates) {
+  if (EnableMacroFusion)
+    return std::make_unique<MacroFusion>(Predicates, false);
   return nullptr;
 }
diff --git a/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp b/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
index 29c9b9ccf276..0bddeeef9e9b 100644
--- a/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
@@ -142,10 +142,10 @@ namespace {
 /// be turned into VOPD instructions
 /// Greedily pairs instruction candidates. O(n^2) algorithm.
 struct VOPDPairingMutation : ScheduleDAGMutation {
-  ShouldSchedulePredTy shouldScheduleAdjacent; // NOLINT: function pointer
+  MacroFusionPredTy shouldScheduleAdjacent; // NOLINT: function pointer
 
   VOPDPairingMutation(
-      ShouldSchedulePredTy shouldScheduleAdjacent) // NOLINT: function pointer
+      MacroFusionPredTy shouldScheduleAdjacent) // NOLINT: function pointer
       : shouldScheduleAdjacent(shouldScheduleAdjacent) {}
 
   void apply(ScheduleDAGInstrs *DAG) override {
-- 
GitLab


From d5fb4c0f118b47db74233af2d99ae075e1dbe148 Mon Sep 17 00:00:00 2001
From: "Ivan R. Ivanov" <ivanov.i.aa@m.titech.ac.jp>
Date: Tue, 12 Dec 2023 13:31:55 +0900
Subject: [PATCH 219/349] [MLIR][NVVM] Enable nvvm intrinsics import to LLVMIR 
  (#68843)

Co-authored-by: Tobias Gysi <tobias.gysi@nextsilicon.com>
Co-authored-by: Christian Ulmann <christianulmann@gmail.com>
---
 .../mlir/Dialect/LLVMIR/CMakeLists.txt        |   2 +
 mlir/include/mlir/Target/LLVMIR/Dialect/All.h |   2 +
 .../Dialect/NVVM/LLVMIRToNVVMTranslation.h    |  31 ++
 .../Target/LLVMIR/Dialect/NVVM/CMakeLists.txt |  18 +
 .../Dialect/NVVM/LLVMIRToNVVMTranslation.cpp  |  93 +++++
 mlir/test/Target/LLVMIR/Import/nvvmir.ll      | 355 ++++++++++++++++++
 6 files changed, 501 insertions(+)
 create mode 100644 mlir/include/mlir/Target/LLVMIR/Dialect/NVVM/LLVMIRToNVVMTranslation.h
 create mode 100644 mlir/lib/Target/LLVMIR/Dialect/NVVM/LLVMIRToNVVMTranslation.cpp
 create mode 100644 mlir/test/Target/LLVMIR/Import/nvvmir.ll

diff --git a/mlir/include/mlir/Dialect/LLVMIR/CMakeLists.txt b/mlir/include/mlir/Dialect/LLVMIR/CMakeLists.txt
index 64de028c7fe4..8e41fcc05a16 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/CMakeLists.txt
+++ b/mlir/include/mlir/Dialect/LLVMIR/CMakeLists.txt
@@ -56,6 +56,8 @@ add_mlir_dialect(NVVMOps nvvm)
 add_mlir_doc(NVVMOps NVVMDialect Dialects/ -gen-dialect-doc -dialect=nvvm)
 set(LLVM_TARGET_DEFINITIONS NVVMOps.td)
 mlir_tablegen(NVVMConversions.inc -gen-llvmir-conversions)
+mlir_tablegen(NVVMFromLLVMIRConversions.inc -gen-intr-from-llvmir-conversions)
+mlir_tablegen(NVVMConvertibleLLVMIRIntrinsics.inc -gen-convertible-llvmir-intrinsics)
 mlir_tablegen(NVVMOpsEnums.h.inc -gen-enum-decls)
 mlir_tablegen(NVVMOpsEnums.cpp.inc -gen-enum-defs)
 mlir_tablegen(NVVMOpsAttributes.h.inc -gen-attrdef-decls -attrdefs-dialect=nvvm)
diff --git a/mlir/include/mlir/Target/LLVMIR/Dialect/All.h b/mlir/include/mlir/Target/LLVMIR/Dialect/All.h
index 5dfc15afb759..0b37e23e4511 100644
--- a/mlir/include/mlir/Target/LLVMIR/Dialect/All.h
+++ b/mlir/include/mlir/Target/LLVMIR/Dialect/All.h
@@ -22,6 +22,7 @@
 #include "mlir/Target/LLVMIR/Dialect/GPU/GPUToLLVMIRTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/LLVMIR/LLVMIRToLLVMTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.h"
+#include "mlir/Target/LLVMIR/Dialect/NVVM/LLVMIRToNVVMTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.h"
@@ -74,6 +75,7 @@ registerAllGPUToLLVMIRTranslations(DialectRegistry &registry) {
 static inline void
 registerAllFromLLVMIRTranslations(DialectRegistry &registry) {
   registerLLVMDialectImport(registry);
+  registerNVVMDialectImport(registry);
 }
 } // namespace mlir
 
diff --git a/mlir/include/mlir/Target/LLVMIR/Dialect/NVVM/LLVMIRToNVVMTranslation.h b/mlir/include/mlir/Target/LLVMIR/Dialect/NVVM/LLVMIRToNVVMTranslation.h
new file mode 100644
index 000000000000..02ee83284dd3
--- /dev/null
+++ b/mlir/include/mlir/Target/LLVMIR/Dialect/NVVM/LLVMIRToNVVMTranslation.h
@@ -0,0 +1,31 @@
+//===- LLVMIRToNVVMTranslation.h - LLVM IR to NVVM Dialect ------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This provides registration calls for LLVM IR to NVVM dialect translation.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_TARGET_LLVMIR_DIALECT_NVVM_LLVMIRTONVVMTRANSLATION_H
+#define MLIR_TARGET_LLVMIR_DIALECT_NVVM_LLVMIRTONVVMTRANSLATION_H
+
+namespace mlir {
+
+class DialectRegistry;
+class MLIRContext;
+
+/// Registers the NVVM dialect and its import from LLVM IR in the given
+/// registry.
+void registerNVVMDialectImport(DialectRegistry &registry);
+
+/// Registers the NVVM dialect and its import from LLVM IR with the given
+/// context.
+void registerNVVMDialectImport(MLIRContext &context);
+
+} // namespace mlir
+
+#endif // MLIR_TARGET_LLVMIR_DIALECT_NVVM_LLVMIRTONVVMTRANSLATION_H
diff --git a/mlir/lib/Target/LLVMIR/Dialect/NVVM/CMakeLists.txt b/mlir/lib/Target/LLVMIR/Dialect/NVVM/CMakeLists.txt
index 9f3935b0c3f4..a90de1579816 100644
--- a/mlir/lib/Target/LLVMIR/Dialect/NVVM/CMakeLists.txt
+++ b/mlir/lib/Target/LLVMIR/Dialect/NVVM/CMakeLists.txt
@@ -1,3 +1,21 @@
+set(LLVM_OPTIONAL_SOURCES
+  LLVMIRToNVVMTranslation.cpp
+  NVVMToLLVMIRTranslation.cpp
+  )
+
+add_mlir_translation_library(MLIRLLVMIRToNVVMTranslation
+  LLVMIRToNVVMTranslation.cpp
+
+  LINK_COMPONENTS
+  Core
+
+  LINK_LIBS PUBLIC
+  MLIRIR
+  MLIRNVVMDialect
+  MLIRSupport
+  MLIRTargetLLVMIRImport
+  )
+
 add_mlir_translation_library(MLIRNVVMToLLVMIRTranslation
   NVVMToLLVMIRTranslation.cpp
 
diff --git a/mlir/lib/Target/LLVMIR/Dialect/NVVM/LLVMIRToNVVMTranslation.cpp b/mlir/lib/Target/LLVMIR/Dialect/NVVM/LLVMIRToNVVMTranslation.cpp
new file mode 100644
index 000000000000..855abc12a909
--- /dev/null
+++ b/mlir/lib/Target/LLVMIR/Dialect/NVVM/LLVMIRToNVVMTranslation.cpp
@@ -0,0 +1,93 @@
+//===- LLVMIRToNVVMTranslation.cpp - Translate LLVM IR to NVVM dialect ----===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements a translation between LLVM IR and the MLIR NVVM dialect.
+//
+//===----------------------------------------------------------------------===//
+
+#include "mlir/Target/LLVMIR/Dialect/NVVM/LLVMIRToNVVMTranslation.h"
+#include "mlir/Dialect/LLVMIR/NVVMDialect.h"
+#include "mlir/Target/LLVMIR/ModuleImport.h"
+
+#include "llvm/IR/IntrinsicsNVPTX.h"
+
+using namespace mlir;
+using namespace mlir::NVVM;
+
+/// Returns true if the LLVM IR intrinsic is convertible to an MLIR NVVM dialect
+/// intrinsic. Returns false otherwise.
+static bool isConvertibleIntrinsic(llvm::Intrinsic::ID id) {
+  static const DenseSet<unsigned> convertibleIntrinsics = {
+#include "mlir/Dialect/LLVMIR/NVVMConvertibleLLVMIRIntrinsics.inc"
+  };
+  return convertibleIntrinsics.contains(id);
+}
+
+/// Returns the list of LLVM IR intrinsic identifiers that are convertible to
+/// MLIR NVVM dialect intrinsics.
+static ArrayRef<unsigned> getSupportedIntrinsicsImpl() {
+  static const SmallVector<unsigned> convertibleIntrinsics = {
+#include "mlir/Dialect/LLVMIR/NVVMConvertibleLLVMIRIntrinsics.inc"
+  };
+  return convertibleIntrinsics;
+}
+
+/// Converts the LLVM intrinsic to an MLIR NVVM dialect operation if a
+/// conversion exits. Returns failure otherwise.
+static LogicalResult convertIntrinsicImpl(OpBuilder &odsBuilder,
+                                          llvm::CallInst *inst,
+                                          LLVM::ModuleImport &moduleImport) {
+  llvm::Intrinsic::ID intrinsicID = inst->getIntrinsicID();
+
+  // Check if the intrinsic is convertible to an MLIR dialect counterpart and
+  // copy the arguments to an an LLVM operands array reference for conversion.
+  if (isConvertibleIntrinsic(intrinsicID)) {
+    SmallVector<llvm::Value *> args(inst->args());
+    ArrayRef<llvm::Value *> llvmOperands(args);
+#include "mlir/Dialect/LLVMIR/NVVMFromLLVMIRConversions.inc"
+  }
+
+  return failure();
+}
+
+namespace {
+
+/// Implementation of the dialect interface that converts operations belonging
+/// to the NVVM dialect.
+class NVVMDialectLLVMIRImportInterface : public LLVMImportDialectInterface {
+public:
+  using LLVMImportDialectInterface::LLVMImportDialectInterface;
+
+  /// Converts the LLVM intrinsic to an MLIR NVVM dialect operation if a
+  /// conversion exits. Returns failure otherwise.
+  LogicalResult convertIntrinsic(OpBuilder &builder, llvm::CallInst *inst,
+                                 LLVM::ModuleImport &moduleImport) const final {
+    return convertIntrinsicImpl(builder, inst, moduleImport);
+  }
+
+  /// Returns the list of LLVM IR intrinsic identifiers that are convertible to
+  /// MLIR NVVM dialect intrinsics.
+  ArrayRef<unsigned> getSupportedIntrinsics() const final {
+    return getSupportedIntrinsicsImpl();
+  }
+};
+
+} // namespace
+
+void mlir::registerNVVMDialectImport(DialectRegistry &registry) {
+  registry.insert<NVVM::NVVMDialect>();
+  registry.addExtension(+[](MLIRContext *ctx, NVVM::NVVMDialect *dialect) {
+    dialect->addInterfaces<NVVMDialectLLVMIRImportInterface>();
+  });
+}
+
+void mlir::registerNVVMDialectImport(MLIRContext &context) {
+  DialectRegistry registry;
+  registerNVVMDialectImport(registry);
+  context.appendDialectRegistry(registry);
+}
diff --git a/mlir/test/Target/LLVMIR/Import/nvvmir.ll b/mlir/test/Target/LLVMIR/Import/nvvmir.ll
new file mode 100644
index 000000000000..e4a8773e2dd8
--- /dev/null
+++ b/mlir/test/Target/LLVMIR/Import/nvvmir.ll
@@ -0,0 +1,355 @@
+; RUN: mlir-translate -import-llvm %s | FileCheck %s
+
+; CHECK-LABEL: @nvvm_special_regs
+define i32 @nvvm_special_regs() {
+  ; CHECK: = nvvm.read.ptx.sreg.tid.x : i32
+  %1 = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
+  ; CHECK: = nvvm.read.ptx.sreg.tid.y : i32
+  %2 = call i32 @llvm.nvvm.read.ptx.sreg.tid.y()
+  ; CHECK: = nvvm.read.ptx.sreg.tid.z : i32
+  %3 = call i32 @llvm.nvvm.read.ptx.sreg.tid.z()
+  ; CHECK: = nvvm.read.ptx.sreg.ntid.x : i32
+  %4 = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
+  ; CHECK: = nvvm.read.ptx.sreg.ntid.y : i32
+  %5 = call i32 @llvm.nvvm.read.ptx.sreg.ntid.y()
+  ; CHECK: = nvvm.read.ptx.sreg.ntid.z : i32
+  %6 = call i32 @llvm.nvvm.read.ptx.sreg.ntid.z()
+  ; CHECK: = nvvm.read.ptx.sreg.ctaid.x : i32
+  %7 = call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x()
+  ; CHECK: = nvvm.read.ptx.sreg.ctaid.y : i32
+  %8 = call i32 @llvm.nvvm.read.ptx.sreg.ctaid.y()
+  ; CHECK: = nvvm.read.ptx.sreg.ctaid.z : i32
+  %9 = call i32 @llvm.nvvm.read.ptx.sreg.ctaid.z()
+  ; CHECK: = nvvm.read.ptx.sreg.nctaid.x : i32
+  %10 = call i32 @llvm.nvvm.read.ptx.sreg.nctaid.x()
+  ; CHECK: = nvvm.read.ptx.sreg.nctaid.y : i32
+  %11 = call i32 @llvm.nvvm.read.ptx.sreg.nctaid.y()
+  ; CHECK: = nvvm.read.ptx.sreg.nctaid.z : i32
+  %12 = call i32 @llvm.nvvm.read.ptx.sreg.nctaid.z()
+  ; CHECK: = nvvm.read.ptx.sreg.warpsize : i32
+  %13 = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
+  ; CHECK: = nvvm.read.ptx.sreg.laneid : i32
+  %14 = call i32 @llvm.nvvm.read.ptx.sreg.laneid()
+  ; CHECK: = nvvm.read.ptx.sreg.clusterid.x : i32
+  %15 = call i32 @llvm.nvvm.read.ptx.sreg.clusterid.x()
+  ; CHECK: = nvvm.read.ptx.sreg.clusterid.y : i32
+  %16 = call i32 @llvm.nvvm.read.ptx.sreg.clusterid.y()
+  ; CHECK: = nvvm.read.ptx.sreg.clusterid.z : i32
+  %17 = call i32 @llvm.nvvm.read.ptx.sreg.clusterid.z()
+  ; CHECK: = nvvm.read.ptx.sreg.nclusterid.x : i32
+  %18 = call i32 @llvm.nvvm.read.ptx.sreg.nclusterid.x()
+  ; CHECK: = nvvm.read.ptx.sreg.nclusterid.y : i32
+  %19 = call i32 @llvm.nvvm.read.ptx.sreg.nclusterid.y()
+  ; CHECK: = nvvm.read.ptx.sreg.nclusterid.z : i32
+  %20 = call i32 @llvm.nvvm.read.ptx.sreg.nclusterid.z()
+  ; CHECK: = nvvm.read.ptx.sreg.cluster.ctaid.x : i32
+  %21 = call i32 @llvm.nvvm.read.ptx.sreg.cluster.ctaid.x()
+  ; CHECK: = nvvm.read.ptx.sreg.cluster.ctaid.y : i32
+  %22 = call i32 @llvm.nvvm.read.ptx.sreg.cluster.ctaid.y()
+  ; CHECK: = nvvm.read.ptx.sreg.cluster.ctaid.z : i32
+  %23 = call i32 @llvm.nvvm.read.ptx.sreg.cluster.ctaid.z()
+  ; CHECK: = nvvm.read.ptx.sreg.cluster.nctaid.x : i32
+  %24 = call i32 @llvm.nvvm.read.ptx.sreg.cluster.nctaid.x()
+  ; CHECK: = nvvm.read.ptx.sreg.cluster.nctaid.y : i32
+  %25 = call i32 @llvm.nvvm.read.ptx.sreg.cluster.nctaid.y()
+  ; CHECK: = nvvm.read.ptx.sreg.cluster.nctaid.z : i32
+  %26 = call i32 @llvm.nvvm.read.ptx.sreg.cluster.nctaid.z()
+  ; CHECK: = nvvm.read.ptx.sreg.cluster.ctarank : i32
+  %27 = call i32 @llvm.nvvm.read.ptx.sreg.cluster.ctarank()
+  ; CHECK: = nvvm.read.ptx.sreg.cluster.nctarank : i32
+  %28 = call i32 @llvm.nvvm.read.ptx.sreg.cluster.nctarank()
+  ret i32 %1
+}
+
+; CHECK-LABEL: @nvvm_rcp
+define float @nvvm_rcp(float %0) {
+  ; CHECK: = nvvm.rcp.approx.ftz.f %{{.*}} : f32
+  %2 = call float @llvm.nvvm.rcp.approx.ftz.f(float %0)
+  ret float %2
+}
+
+; TODO: Support the intrinsics below once they derive from NVVM_IntrOp rather than from NVVM_Op.
+
+; define void @llvm_nvvm_barrier0() {
+;   call void @llvm.nvvm.barrier0()
+;   ret void
+; }
+;
+; define i32 @nvvm_shfl(i32 %0, i32 %1, i32 %2, i32 %3, float %4) {
+;   %6 = call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 %0, i32 %3, i32 %1, i32 %2)
+;   %7 = call float @llvm.nvvm.shfl.sync.bfly.f32(i32 %0, float %4, i32 %1, i32 %2)
+;   %8 = call i32 @llvm.nvvm.shfl.sync.up.i32(i32 %0, i32 %3, i32 %1, i32 %2)
+;   %9 = call float @llvm.nvvm.shfl.sync.up.f32(i32 %0, float %4, i32 %1, i32 %2)
+;   %10 = call i32 @llvm.nvvm.shfl.sync.down.i32(i32 %0, i32 %3, i32 %1, i32 %2)
+;   %11 = call float @llvm.nvvm.shfl.sync.down.f32(i32 %0, float %4, i32 %1, i32 %2)
+;   %12 = call i32 @llvm.nvvm.shfl.sync.idx.i32(i32 %0, i32 %3, i32 %1, i32 %2)
+;   %13 = call float @llvm.nvvm.shfl.sync.idx.f32(i32 %0, float %4, i32 %1, i32 %2)
+;   ret i32 %6
+; }
+;
+; define { i32, i1 } @nvvm_shfl_pred(i32 %0, i32 %1, i32 %2, i32 %3, float %4) {
+;   %6 = call { i32, i1 } @llvm.nvvm.shfl.sync.bfly.i32p(i32 %0, i32 %3, i32 %1, i32 %2)
+;   %7 = call { float, i1 } @llvm.nvvm.shfl.sync.bfly.f32p(i32 %0, float %4, i32 %1, i32 %2)
+;   %8 = call { i32, i1 } @llvm.nvvm.shfl.sync.up.i32p(i32 %0, i32 %3, i32 %1, i32 %2)
+;   %9 = call { float, i1 } @llvm.nvvm.shfl.sync.up.f32p(i32 %0, float %4, i32 %1, i32 %2)
+;   %10 = call { i32, i1 } @llvm.nvvm.shfl.sync.down.i32p(i32 %0, i32 %3, i32 %1, i32 %2)
+;   %11 = call { float, i1 } @llvm.nvvm.shfl.sync.down.f32p(i32 %0, float %4, i32 %1, i32 %2)
+;   %12 = call { i32, i1 } @llvm.nvvm.shfl.sync.idx.i32p(i32 %0, i32 %3, i32 %1, i32 %2)
+;   %13 = call { float, i1 } @llvm.nvvm.shfl.sync.idx.f32p(i32 %0, float %4, i32 %1, i32 %2)
+;   ret { i32, i1 } %6
+; }
+;
+; define i32 @nvvm_vote(i32 %0, i1 %1) {
+;   %3 = call i32 @llvm.nvvm.vote.ballot.sync(i32 %0, i1 %1)
+;   ret i32 %3
+; }
+;
+; define { float, float, float, float, float, float, float, float } @nvvm_mma_mn8n8k4_row_col_f32_f32(<2 x half> %0, <2 x half> %1, <2 x half> %2, <2 x half> %3, float %4, float %5, float %6, float %7, float %8, float %9, float %10, float %11) {
+;   %13 = call { float, float, float, float, float, float, float, float } @llvm.nvvm.mma.m8n8k4.row.col.f32.f32(<2 x half> %0, <2 x half> %1, <2 x half> %2, <2 x half> %3, float %4, float %5, float %6, float %7, float %8, float %9, float %10, float %11)
+;   ret { float, float, float, float, float, float, float, float } %13
+; }
+;
+; define { <2 x half>, <2 x half> } @nvvm_mma_m16n8k16_f16_f16(<2 x half> %0, <2 x half> %1, <2 x half> %2, <2 x half> %3, <2 x half> %4, <2 x half> %5, <2 x half> %6, <2 x half> %7) {
+;   %9 = call { <2 x half>, <2 x half> } @llvm.nvvm.mma.m16n8k16.row.col.f16.f16(<2 x half> %0, <2 x half> %1, <2 x half> %2, <2 x half> %3, <2 x half> %4, <2 x half> %5, <2 x half> %6, <2 x half> %7)
+;   ret { <2 x half>, <2 x half> } %9
+; }
+;
+; define { float, float, float, float } @nvvm_mma_m16n8k16_f32_f16(<2 x half> %0, <2 x half> %1, <2 x half> %2, <2 x half> %3, <2 x half> %4, <2 x half> %5, <2 x half> %6, <2 x half> %7) {
+;   %9 = call { float, float, float, float } @llvm.nvvm.mma.m16n8k16.row.col.f32.f16(<2 x half> %0, <2 x half> %1, <2 x half> %2, <2 x half> %3, <2 x half> %4, <2 x half> %5, <2 x half> %6, <2 x half> %7)
+;   ret { float, float, float, float } %9
+; }
+;
+; define { <2 x half>, <2 x half> } @nvvm_mma_m16n8k16_f16_f32(<2 x half> %0, <2 x half> %1, <2 x half> %2, <2 x half> %3, <2 x half> %4, <2 x half> %5, float %6, float %7, float %8, float %9) {
+;   %11 = call { <2 x half>, <2 x half> } @llvm.nvvm.mma.m16n8k16.row.col.f16.f32(<2 x half> %0, <2 x half> %1, <2 x half> %2, <2 x half> %3, <2 x half> %4, <2 x half> %5, float %6, float %7, float %8, float %9)
+;   ret { <2 x half>, <2 x half> } %11
+; }
+;
+; define { float, float, float, float } @nvvm_mma_m16n8k16_f32_f32(<2 x half> %0, <2 x half> %1, <2 x half> %2, <2 x half> %3, <2 x half> %4, <2 x half> %5, float %6, float %7, float %8, float %9) {
+;   %11 = call { float, float, float, float } @llvm.nvvm.mma.m16n8k16.row.col.f32.f32(<2 x half> %0, <2 x half> %1, <2 x half> %2, <2 x half> %3, <2 x half> %4, <2 x half> %5, float %6, float %7, float %8, float %9)
+;   ret { float, float, float, float } %11
+; }
+;
+; define { i32, i32, i32, i32 } @nvvm_mma_m16n8k16_s8_s8(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6) {
+;   %8 = call { i32, i32, i32, i32 } @llvm.nvvm.mma.m16n8k16.row.col.s8(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6)
+;   ret { i32, i32, i32, i32 } %8
+; }
+;
+; define { i32, i32, i32, i32 } @nvvm_mma_m16n8k16_s8_u8(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6) {
+;   %8 = call { i32, i32, i32, i32 } @llvm.nvvm.mma.m16n8k16.row.col.satfinite.s8.u8(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6)
+;   ret { i32, i32, i32, i32 } %8
+; }
+;
+; define { i32, i32, i32, i32 } @nvvm_mma_m16n8k128_b1_b1(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6) {
+;   %8 = call { i32, i32, i32, i32 } @llvm.nvvm.mma.xor.popc.m16n8k128.row.col.b1(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6)
+;   ret { i32, i32, i32, i32 } %8
+; }
+;
+; define { i32, i32, i32, i32 } @nvvm_mma_m16n8k32_s4_s4(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6) {
+;   %8 = call { i32, i32, i32, i32 } @llvm.nvvm.mma.m16n8k32.row.col.satfinite.s4(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6)
+;   ret { i32, i32, i32, i32 } %8
+; }
+;
+; define { double, double } @nvvm_mma_m8n8k4_f64_f64(double %0, double %1, double %2, double %3) {
+;   %5 = call { double, double } @llvm.nvvm.mma.m8n8k4.row.col.f64(double %0, double %1, double %2, double %3)
+;   ret { double, double } %5
+; }
+;
+; define { float, float, float, float } @nvvm_mma_m16n8k4_tf32_f32(i32 %0, i32 %1, i32 %2, float %3, float %4, float %5, float %6) {
+;   %8 = call { float, float, float, float } @llvm.nvvm.mma.m16n8k4.row.col.tf32(i32 %0, i32 %1, i32 %2, float %3, float %4, float %5, float %6)
+;   ret { float, float, float, float } %8
+; }
+;
+; define void @gpu_wmma_load_op(ptr addrspace(3) %0, i32 %1) {
+;   %3 = call { <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half> } @llvm.nvvm.wmma.m16n16k16.load.a.row.stride.f16.p3(ptr addrspace(3) %0, i32 %1)
+;   ret void
+; }
+;
+; define void @gpu_wmma_store_op(ptr addrspace(3) %0, i32 %1, <2 x half> %2, <2 x half> %3, <2 x half> %4, <2 x half> %5) {
+;   call void @llvm.nvvm.wmma.m16n16k16.store.d.row.stride.f16.p3(ptr addrspace(3) %0, <2 x half> %2, <2 x half> %3, <2 x half> %4, <2 x half> %5, i32 %1)
+;   ret void
+; }
+;
+; define void @gpu_wmma_mma_op(<2 x half> %0, <2 x half> %1, <2 x half> %2, <2 x half> %3, <2 x half> %4, <2 x half> %5, <2 x half> %6, <2 x half> %7, <2 x half> %8, <2 x half> %9, <2 x half> %10, <2 x half> %11, <2 x half> %12, <2 x half> %13, <2 x half> %14, <2 x half> %15, <2 x half> %16, <2 x half> %17, <2 x half> %18, <2 x half> %19) {
+;   %21 = call { <2 x half>, <2 x half>, <2 x half>, <2 x half> } @llvm.nvvm.wmma.m16n16k16.mma.row.row.f16.f16(<2 x half> %0, <2 x half> %1, <2 x half> %2, <2 x half> %3, <2 x half> %4, <2 x half> %5, <2 x half> %6, <2 x half> %7, <2 x half> %8, <2 x half> %9, <2 x half> %10, <2 x half> %11, <2 x half> %12, <2 x half> %13, <2 x half> %14, <2 x half> %15, <2 x half> %16, <2 x half> %17, <2 x half> %18, <2 x half> %19)
+;   ret void
+; }
+;
+; define void @nvvm_wmma_load_tf32(ptr %0, i32 %1) {
+;   %3 = call { i32, i32, i32, i32 } @llvm.nvvm.wmma.m16n16k8.load.a.row.stride.tf32.p0(ptr %0, i32 %1)
+;   ret void
+; }
+;
+; define void @nvvm_wmma_mma(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, float %8, float %9, float %10, float %11, float %12, float %13, float %14, float %15) {
+;   %17 = call { float, float, float, float, float, float, float, float } @llvm.nvvm.wmma.m16n16k8.mma.row.row.tf32(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, float %8, float %9, float %10, float %11, float %12, float %13, float %14, float %15)
+;   ret void
+; }
+;
+; define void @cp_async(ptr addrspace(3) %0, ptr addrspace(1) %1) {
+;   call void @llvm.nvvm.cp.async.ca.shared.global.4(ptr addrspace(3) %0, ptr addrspace(1) %1)
+;   call void @llvm.nvvm.cp.async.ca.shared.global.8(ptr addrspace(3) %0, ptr addrspace(1) %1)
+;   call void @llvm.nvvm.cp.async.ca.shared.global.16(ptr addrspace(3) %0, ptr addrspace(1) %1)
+;   call void @llvm.nvvm.cp.async.cg.shared.global.16(ptr addrspace(3) %0, ptr addrspace(1) %1)
+;   call void @llvm.nvvm.cp.async.commit.group()
+;   call void @llvm.nvvm.cp.async.wait.group(i32 0)
+;   ret void
+; }
+;
+; define void @ld_matrix(ptr addrspace(3) %0) {
+;   %2 = call i32 @llvm.nvvm.ldmatrix.sync.aligned.m8n8.x1.b16.p3(ptr addrspace(3) %0)
+;   %3 = call { i32, i32 } @llvm.nvvm.ldmatrix.sync.aligned.m8n8.x2.b16.p3(ptr addrspace(3) %0)
+;   %4 = call { i32, i32, i32, i32 } @llvm.nvvm.ldmatrix.sync.aligned.m8n8.x4.b16.p3(ptr addrspace(3) %0)
+;   %5 = call i32 @llvm.nvvm.ldmatrix.sync.aligned.m8n8.x1.trans.b16.p3(ptr addrspace(3) %0)
+;   %6 = call { i32, i32 } @llvm.nvvm.ldmatrix.sync.aligned.m8n8.x2.trans.b16.p3(ptr addrspace(3) %0)
+;   %7 = call { i32, i32, i32, i32 } @llvm.nvvm.ldmatrix.sync.aligned.m8n8.x4.trans.b16.p3(ptr addrspace(3) %0)
+;   ret void
+; }
+
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x()
+
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.y()
+
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.z()
+
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
+
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.ntid.y()
+
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.ntid.z()
+
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.ctaid.x()
+
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.ctaid.y()
+
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.ctaid.z()
+
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.nctaid.x()
+
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.nctaid.y()
+
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.nctaid.z()
+
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.warpsize()
+
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.laneid()
+
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.clusterid.x()
+
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.clusterid.y()
+
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.clusterid.z()
+
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.nclusterid.x()
+
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.nclusterid.y()
+
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.nclusterid.z()
+
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.cluster.ctaid.x()
+
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.cluster.ctaid.y()
+
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.cluster.ctaid.z()
+
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.cluster.nctaid.x()
+
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.cluster.nctaid.y()
+
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.cluster.nctaid.z()
+
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.cluster.ctarank()
+
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.cluster.nctarank()
+
+declare float @llvm.nvvm.rcp.approx.ftz.f(float)
+
+declare void @llvm.nvvm.barrier0()
+
+declare i32 @llvm.nvvm.shfl.sync.bfly.i32(i32, i32, i32, i32)
+
+declare float @llvm.nvvm.shfl.sync.bfly.f32(i32, float, i32, i32)
+
+declare i32 @llvm.nvvm.shfl.sync.up.i32(i32, i32, i32, i32)
+
+declare float @llvm.nvvm.shfl.sync.up.f32(i32, float, i32, i32)
+
+declare i32 @llvm.nvvm.shfl.sync.down.i32(i32, i32, i32, i32)
+
+declare float @llvm.nvvm.shfl.sync.down.f32(i32, float, i32, i32)
+
+declare i32 @llvm.nvvm.shfl.sync.idx.i32(i32, i32, i32, i32)
+
+declare float @llvm.nvvm.shfl.sync.idx.f32(i32, float, i32, i32)
+
+declare { i32, i1 } @llvm.nvvm.shfl.sync.bfly.i32p(i32, i32, i32, i32)
+
+declare { float, i1 } @llvm.nvvm.shfl.sync.bfly.f32p(i32, float, i32, i32)
+
+declare { i32, i1 } @llvm.nvvm.shfl.sync.up.i32p(i32, i32, i32, i32)
+
+declare { float, i1 } @llvm.nvvm.shfl.sync.up.f32p(i32, float, i32, i32)
+
+declare { i32, i1 } @llvm.nvvm.shfl.sync.down.i32p(i32, i32, i32, i32)
+
+declare { float, i1 } @llvm.nvvm.shfl.sync.down.f32p(i32, float, i32, i32)
+
+declare { i32, i1 } @llvm.nvvm.shfl.sync.idx.i32p(i32, i32, i32, i32)
+
+declare { float, i1 } @llvm.nvvm.shfl.sync.idx.f32p(i32, float, i32, i32)
+
+declare i32 @llvm.nvvm.vote.ballot.sync(i32, i1)
+
+declare { float, float, float, float, float, float, float, float } @llvm.nvvm.mma.m8n8k4.row.col.f32.f32(<2 x half>, <2 x half>, <2 x half>, <2 x half>, float, float, float, float, float, float, float, float)
+
+declare { <2 x half>, <2 x half> } @llvm.nvvm.mma.m16n8k16.row.col.f16.f16(<2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>)
+
+declare { float, float, float, float } @llvm.nvvm.mma.m16n8k16.row.col.f32.f16(<2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>)
+
+declare { <2 x half>, <2 x half> } @llvm.nvvm.mma.m16n8k16.row.col.f16.f32(<2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, float, float, float, float)
+
+declare { float, float, float, float } @llvm.nvvm.mma.m16n8k16.row.col.f32.f32(<2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, float, float, float, float)
+
+declare { i32, i32, i32, i32 } @llvm.nvvm.mma.m16n8k16.row.col.s8(i32, i32, i32, i32, i32, i32, i32)
+
+declare { i32, i32, i32, i32 } @llvm.nvvm.mma.m16n8k16.row.col.satfinite.s8.u8(i32, i32, i32, i32, i32, i32, i32)
+
+declare { i32, i32, i32, i32 } @llvm.nvvm.mma.xor.popc.m16n8k128.row.col.b1(i32, i32, i32, i32, i32, i32, i32)
+
+declare { i32, i32, i32, i32 } @llvm.nvvm.mma.m16n8k32.row.col.satfinite.s4(i32, i32, i32, i32, i32, i32, i32)
+
+declare { double, double } @llvm.nvvm.mma.m8n8k4.row.col.f64(double, double, double, double)
+
+declare { float, float, float, float } @llvm.nvvm.mma.m16n8k4.row.col.tf32(i32, i32, i32, float, float, float, float)
+
+declare { <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half> } @llvm.nvvm.wmma.m16n16k16.load.a.row.stride.f16.p3(ptr addrspace(3) nocapture readonly, i32)
+
+declare void @llvm.nvvm.wmma.m16n16k16.store.d.row.stride.f16.p3(ptr addrspace(3) nocapture writeonly, <2 x half>, <2 x half>, <2 x half>, <2 x half>, i32)
+
+declare { <2 x half>, <2 x half>, <2 x half>, <2 x half> } @llvm.nvvm.wmma.m16n16k16.mma.row.row.f16.f16(<2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>)
+
+declare { i32, i32, i32, i32 } @llvm.nvvm.wmma.m16n16k8.load.a.row.stride.tf32.p0(ptr nocapture readonly, i32)
+
+declare { float, float, float, float, float, float, float, float } @llvm.nvvm.wmma.m16n16k8.mma.row.row.tf32(i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float)
+
+declare void @llvm.nvvm.cp.async.ca.shared.global.4(ptr addrspace(3) noalias writeonly, ptr addrspace(1) noalias readonly)
+
+declare void @llvm.nvvm.cp.async.ca.shared.global.8(ptr addrspace(3) noalias writeonly, ptr addrspace(1) noalias readonly)
+
+declare void @llvm.nvvm.cp.async.ca.shared.global.16(ptr addrspace(3) noalias writeonly, ptr addrspace(1) noalias readonly)
+
+declare void @llvm.nvvm.cp.async.cg.shared.global.16(ptr addrspace(3) noalias writeonly, ptr addrspace(1) noalias readonly)
+
+declare void @llvm.nvvm.cp.async.commit.group()
+
+declare void @llvm.nvvm.cp.async.wait.group(i32 immarg)
+
+declare i32 @llvm.nvvm.ldmatrix.sync.aligned.m8n8.x1.b16.p3(ptr addrspace(3) nocapture readonly)
+
+declare { i32, i32 } @llvm.nvvm.ldmatrix.sync.aligned.m8n8.x2.b16.p3(ptr addrspace(3) nocapture readonly)
+
+declare { i32, i32, i32, i32 } @llvm.nvvm.ldmatrix.sync.aligned.m8n8.x4.b16.p3(ptr addrspace(3) nocapture readonly)
+
+declare i32 @llvm.nvvm.ldmatrix.sync.aligned.m8n8.x1.trans.b16.p3(ptr addrspace(3) nocapture readonly)
+
+declare { i32, i32 } @llvm.nvvm.ldmatrix.sync.aligned.m8n8.x2.trans.b16.p3(ptr addrspace(3) nocapture readonly)
+
+declare { i32, i32, i32, i32 } @llvm.nvvm.ldmatrix.sync.aligned.m8n8.x4.trans.b16.p3(ptr addrspace(3) nocapture readonly)
-- 
GitLab


From 586ecdf205aa8b3d162da6f955170a6736656615 Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu@google.com>
Date: Mon, 11 Dec 2023 21:01:36 -0800
Subject: [PATCH 220/349] [llvm] Use StringRef::{starts,ends}_with (NFC)
 (#74956)

This patch replaces uses of StringRef::{starts,ends}with with
StringRef::{starts,ends}_with for consistency with
std::{string,string_view}::{starts,ends}_with in C++20.

I'm planning to deprecate and eventually remove
StringRef::{starts,ends}with.
---
 .../llvm/Analysis/ObjCARCAnalysisUtils.h      |   2 +-
 llvm/include/llvm/CodeGen/IndirectThunks.h    |   4 +-
 llvm/include/llvm/CodeGen/MIRYamlMapping.h    |   4 +-
 llvm/include/llvm/MC/MCSectionCOFF.h          |   2 +-
 llvm/include/llvm/Object/ELFObjectFile.h      |  14 +-
 llvm/include/llvm/Passes/PassBuilder.h        |   6 +-
 llvm/include/llvm/ProfileData/SampleProf.h    |   2 +-
 llvm/include/llvm/Transforms/IPO/Attributor.h |   4 +-
 llvm/lib/Analysis/LoopInfo.cpp                |   2 +-
 llvm/lib/Analysis/VFABIDemangling.cpp         |   2 +-
 llvm/lib/AsmParser/LLLexer.cpp                |   6 +-
 llvm/lib/BinaryFormat/Magic.cpp               |   6 +-
 llvm/lib/Bitcode/Reader/MetadataLoader.cpp    |   2 +-
 .../BasicBlockSectionsProfileReader.cpp       |   2 +-
 llvm/lib/CodeGen/GlobalMerge.cpp              |   3 +-
 llvm/lib/CodeGen/MIRParser/MILexer.cpp        |  16 +-
 llvm/lib/CodeGen/SanitizerBinaryMetadata.cpp  |   2 +-
 .../CodeGen/TargetLoweringObjectFileImpl.cpp  |  33 ++-
 llvm/lib/CodeGen/WinEHPrepare.cpp             |   2 +-
 llvm/lib/DWARFLinker/DWARFLinker.cpp          |   6 +-
 .../DWARFLinkerCompileUnit.cpp                |   6 +-
 .../SyntheticTypeNameBuilder.cpp              |   2 +-
 .../ExecutionEngine/JITLink/ELF_x86_64.cpp    |   4 +-
 .../JITLink/MachOLinkGraphBuilder.cpp         |   2 +-
 .../Orc/Debugging/DebugInfoSupport.cpp        |   2 +-
 .../Orc/Debugging/DebuggerSupportPlugin.cpp   |   2 +-
 .../ExecutionEngine/Orc/ExecutionUtils.cpp    |   6 +-
 .../ExecutionEngine/Orc/IndirectionUtils.cpp  |   2 +-
 llvm/lib/ExecutionEngine/Orc/LLJIT.cpp        |   4 +-
 .../Orc/ObjectFileInterface.cpp               |   2 +-
 .../Orc/Shared/ObjectFormats.cpp              |   2 +-
 .../ExecutionEngine/RuntimeDyld/JITSymbol.cpp |   2 +-
 .../RuntimeDyld/RuntimeDyldCOFF.cpp           |   3 +-
 .../RuntimeDyld/RuntimeDyldChecker.cpp        |  52 ++---
 .../Targets/RuntimeDyldCOFFAArch64.h          |   2 +-
 .../RuntimeDyld/Targets/RuntimeDyldCOFFI386.h |   2 +-
 .../Targets/RuntimeDyldCOFFThumb.h            |   2 +-
 .../Targets/RuntimeDyldCOFFX86_64.h           |   2 +-
 llvm/lib/FileCheck/FileCheck.cpp              |  32 +--
 llvm/lib/FuzzMutate/FuzzerCLI.cpp             |   4 +-
 llvm/lib/IR/AutoUpgrade.cpp                   |   2 +-
 llvm/lib/IR/DebugInfo.cpp                     |   2 +-
 llvm/lib/IR/Function.cpp                      |   6 +-
 llvm/lib/IR/Mangler.cpp                       |   4 +-
 llvm/lib/IR/PassInstrumentation.cpp           |   3 +-
 llvm/lib/IR/Type.cpp                          |   2 +-
 llvm/lib/IR/Verifier.cpp                      |   2 +-
 llvm/lib/InterfaceStub/IFSHandler.cpp         |   2 +-
 llvm/lib/LTO/LTOModule.cpp                    |   8 +-
 llvm/lib/Linker/IRMover.cpp                   |   2 +-
 llvm/lib/MC/ELFObjectWriter.cpp               |  12 +-
 llvm/lib/MC/MCAsmStreamer.cpp                 |   6 +-
 llvm/lib/MC/MCContext.cpp                     |  10 +-
 llvm/lib/MC/MCDwarf.cpp                       |   2 +-
 llvm/lib/MC/MCParser/AsmLexer.cpp             |   4 +-
 llvm/lib/MC/MCParser/AsmParser.cpp            |   2 +-
 llvm/lib/MC/MCParser/COFFMasmParser.cpp       |   2 +-
 llvm/lib/MC/MCParser/ELFAsmParser.cpp         |   4 +-
 llvm/lib/MC/MCParser/MasmParser.cpp           |   4 +-
 llvm/lib/MC/StringTableBuilder.cpp            |   2 +-
 llvm/lib/MC/WasmObjectWriter.cpp              |  12 +-
 llvm/lib/MC/WinCOFFObjectWriter.cpp           |   2 +-
 llvm/lib/ObjCopy/COFF/COFFObjcopy.cpp         |   2 +-
 llvm/lib/ObjCopy/ELF/ELFObjcopy.cpp           |  16 +-
 llvm/lib/ObjCopy/MachO/MachOObject.h          |   4 +-
 llvm/lib/ObjCopy/wasm/WasmObjcopy.cpp         |   4 +-
 llvm/lib/Object/Archive.cpp                   |  16 +-
 llvm/lib/Object/COFFImportFile.cpp            |   6 +-
 llvm/lib/Object/COFFModuleDefinition.cpp      |   4 +-
 llvm/lib/Object/COFFObjectFile.cpp            |   6 +-
 llvm/lib/Object/MachOObjectFile.cpp           |  10 +-
 llvm/lib/Object/ModuleSymbolTable.cpp         |   2 +-
 llvm/lib/Object/RecordStreamer.cpp            |   2 +-
 llvm/lib/Object/WasmObjectFile.cpp            |   2 +-
 llvm/lib/ObjectYAML/ELFEmitter.cpp            |   2 +-
 llvm/lib/ObjectYAML/ELFYAML.cpp               |   6 +-
 llvm/lib/Option/ArgList.cpp                   |   4 +-
 llvm/lib/Option/OptTable.cpp                  |  12 +-
 llvm/lib/Passes/PassBuilder.cpp               |   6 +-
 llvm/lib/ProfileData/GCOV.cpp                 |   2 +-
 llvm/lib/ProfileData/InstrProf.cpp            |   2 +-
 llvm/lib/ProfileData/InstrProfCorrelator.cpp  |   2 +-
 llvm/lib/ProfileData/InstrProfReader.cpp      |   8 +-
 .../ItaniumManglingCanonicalizer.cpp          |   6 +-
 llvm/lib/ProfileData/SampleProfReader.cpp     |   4 +-
 .../lib/ProfileData/SymbolRemappingReader.cpp |   2 +-
 llvm/lib/Remarks/YAMLRemarkParser.cpp         |   2 +-
 llvm/lib/Support/Unix/Path.inc                |   2 +-
 .../Target/AArch64/AArch64GlobalsTagging.cpp  |   2 +-
 .../Target/AArch64/AArch64SLSHardening.cpp    |   2 +-
 .../AArch64/AsmParser/AArch64AsmParser.cpp    |   4 +-
 llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp      |   2 +-
 .../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp |   4 +-
 .../Target/AMDGPU/AMDGPUTargetObjectFile.cpp  |   2 +-
 .../AMDGPU/AMDGPUTargetTransformInfo.cpp      |   2 +-
 .../AMDGPU/AsmParser/AMDGPUAsmParser.cpp      |  32 +--
 .../Disassembler/AMDGPUDisassembler.cpp       |   2 +-
 .../R600OpenCLImageTypeLoweringPass.cpp       |   6 +-
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp     |   2 +-
 .../Target/AMDGPU/SIMachineFunctionInfo.cpp   |   2 +-
 .../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp    |  10 +-
 llvm/lib/Target/ARM/ARMSLSHardening.cpp       |   2 +-
 llvm/lib/Target/ARM/ARMTargetMachine.cpp      |   4 +-
 .../lib/Target/ARM/ARMTargetTransformInfo.cpp |   2 +-
 .../lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 213 +++++++++---------
 .../ARM/MCTargetDesc/ARMTargetStreamer.cpp    |   2 +-
 llvm/lib/Target/AVR/AVRAsmPrinter.cpp         |   6 +-
 .../Target/BPF/BPFAbstractMemberAccess.cpp    |  12 +-
 llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp   |   4 +-
 llvm/lib/Target/BPF/BPFPreserveDIType.cpp     |   2 +-
 llvm/lib/Target/BPF/BTFDebug.cpp              |   6 +-
 llvm/lib/Target/Hexagon/HexagonSubtarget.cpp  |   6 +-
 .../Hexagon/HexagonTargetObjectFile.cpp       |   2 +-
 .../MCTargetDesc/HexagonMCTargetDesc.cpp      |   2 +-
 .../Target/Lanai/AsmParser/LanaiAsmParser.cpp |  14 +-
 .../Target/Lanai/LanaiTargetObjectFile.cpp    |   2 +-
 .../LoongArch/LoongArchISelLowering.cpp       |   4 +-
 .../Target/Mips/AsmParser/MipsAsmParser.cpp   |   6 +-
 .../Target/Mips/MCTargetDesc/MipsABIInfo.cpp  |   6 +-
 llvm/lib/Target/Mips/MipsISelLowering.cpp     |   2 +-
 llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp     |   4 +-
 llvm/lib/Target/NVPTX/NVPTXGenericToNVVM.cpp  |   2 +-
 .../Target/NVPTX/NVPTXReplaceImageHandles.cpp |   2 +-
 .../Target/PowerPC/AsmParser/PPCAsmParser.cpp |   2 +-
 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp     |   2 +-
 llvm/lib/Target/PowerPC/PPCTargetMachine.cpp  |   4 +-
 .../Target/RISCV/AsmParser/RISCVAsmParser.cpp |   4 +-
 .../RISCV/MCTargetDesc/RISCVBaseInfo.cpp      |   4 +-
 .../SystemZ/AsmParser/SystemZAsmParser.cpp    |   2 +-
 llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp  |  34 +--
 .../AsmParser/WebAssemblyAsmParser.cpp        |   2 +-
 .../WebAssembly/WebAssemblyAsmPrinter.cpp     |   4 +-
 .../WebAssemblyLowerEmscriptenEHSjLj.cpp      |   4 +-
 .../lib/Target/X86/AsmParser/X86AsmParser.cpp |  71 +++---
 .../X86/MCTargetDesc/X86MCTargetDesc.cpp      |   4 +-
 llvm/lib/Target/X86/X86InsertPrefetch.cpp     |   2 +-
 llvm/lib/Target/X86/X86Subtarget.cpp          |   4 +-
 llvm/lib/Target/XCore/XCoreISelLowering.cpp   |   2 +-
 .../Target/XCore/XCoreTargetObjectFile.cpp    |   2 +-
 llvm/lib/TargetParser/AArch64TargetParser.cpp |   4 +-
 llvm/lib/TargetParser/ARMTargetParser.cpp     |   4 +-
 .../TargetParser/ARMTargetParserCommon.cpp    |  26 +--
 llvm/lib/TargetParser/CSKYTargetParser.cpp    |   2 +-
 llvm/lib/TargetParser/Host.cpp                |  14 +-
 llvm/lib/TargetParser/Triple.cpp              |  29 +--
 llvm/lib/TextAPI/Symbol.cpp                   |  10 +-
 llvm/lib/TextAPI/Target.cpp                   |   2 +-
 llvm/lib/TextAPI/TextStub.cpp                 |  18 +-
 llvm/tools/dsymutil/BinaryHolder.cpp          |   2 +-
 llvm/tools/dsymutil/DwarfLinkerForBinary.cpp  |   4 +-
 llvm/tools/dsymutil/MachODebugMapParser.cpp   |   4 +-
 llvm/tools/dsymutil/MachOUtils.cpp            |   2 +-
 llvm/tools/dsymutil/SymbolMap.cpp             |   4 +-
 llvm/tools/llc/llc.cpp                        |   6 +-
 llvm/tools/lli/lli.cpp                        |   2 +-
 llvm/tools/llvm-ar/llvm-ar.cpp                |   4 +-
 llvm/tools/llvm-as/llvm-as.cpp                |   2 +-
 llvm/tools/llvm-config/llvm-config.cpp        |  10 +-
 llvm/tools/llvm-cxxdump/llvm-cxxdump.cpp      |  28 +--
 llvm/tools/llvm-diff/llvm-diff.cpp            |   3 +-
 llvm/tools/llvm-dis/llvm-dis.cpp              |   2 +-
 llvm/tools/llvm-dwarfutil/DebugInfoLinker.h   |   2 +-
 llvm/tools/llvm-exegesis/lib/X86/Target.cpp   |   6 +-
 llvm/tools/llvm-jitlink/llvm-jitlink.cpp      |   6 +-
 .../llvm-libtool-darwin.cpp                   |   2 +-
 llvm/tools/llvm-nm/llvm-nm.cpp                |  14 +-
 llvm/tools/llvm-objcopy/ObjcopyOptions.cpp    |   2 +-
 llvm/tools/llvm-objdump/COFFDump.cpp          |   2 +-
 llvm/tools/llvm-objdump/MachODump.cpp         |   4 +-
 llvm/tools/llvm-objdump/SourcePrinter.cpp     |   2 +-
 llvm/tools/llvm-objdump/llvm-objdump.cpp      |   2 +-
 llvm/tools/llvm-profdata/llvm-profdata.cpp    |   2 +-
 llvm/tools/llvm-profgen/PerfReader.cpp        |  12 +-
 .../tools/llvm-rc/ResourceScriptCppFilter.cpp |   2 +-
 llvm/tools/llvm-rc/ResourceScriptToken.cpp    |   6 +-
 llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp   |   2 +-
 llvm/tools/llvm-readobj/COFFDumper.cpp        |   2 +-
 llvm/tools/llvm-readobj/ELFDumper.cpp         |   6 +-
 llvm/tools/llvm-readobj/Win64EHDumper.cpp     |   2 +-
 .../llvm-reduce/deltas/StripDebugInfo.cpp     |   2 +-
 llvm/tools/llvm-reduce/llvm-reduce.cpp        |   2 +-
 llvm/tools/llvm-stress/llvm-stress.cpp        |   2 +-
 llvm/tools/llvm-undname/llvm-undname.cpp      |   2 +-
 llvm/tools/obj2yaml/archive2yaml.cpp          |   2 +-
 llvm/tools/obj2yaml/elf2yaml.cpp              |   2 +-
 llvm/tools/obj2yaml/macho2yaml.cpp            |   6 +-
 llvm/tools/obj2yaml/wasm2yaml.cpp             |   2 +-
 llvm/tools/opt/opt.cpp                        |   2 +-
 llvm/tools/yaml2obj/yaml2obj.cpp              |   6 +-
 llvm/utils/split-file/split-file.cpp          |   4 +-
 llvm/utils/yaml-bench/YAMLBench.cpp           |   2 +-
 191 files changed, 645 insertions(+), 655 deletions(-)

diff --git a/llvm/include/llvm/Analysis/ObjCARCAnalysisUtils.h b/llvm/include/llvm/Analysis/ObjCARCAnalysisUtils.h
index 20ff5a5bc6e0..ccf859922e16 100644
--- a/llvm/include/llvm/Analysis/ObjCARCAnalysisUtils.h
+++ b/llvm/include/llvm/Analysis/ObjCARCAnalysisUtils.h
@@ -203,7 +203,7 @@ inline bool IsObjCIdentifiedObject(const Value *V) {
       StringRef Name = GV->getName();
       // These special variables are known to hold values which are not
       // reference-counted pointers.
-      if (Name.startswith("\01l_objc_msgSend_fixup_"))
+      if (Name.starts_with("\01l_objc_msgSend_fixup_"))
         return true;
 
       StringRef Section = GV->getSection();
diff --git a/llvm/include/llvm/CodeGen/IndirectThunks.h b/llvm/include/llvm/CodeGen/IndirectThunks.h
index b0a8e3043be5..9b064ab788bf 100644
--- a/llvm/include/llvm/CodeGen/IndirectThunks.h
+++ b/llvm/include/llvm/CodeGen/IndirectThunks.h
@@ -48,7 +48,7 @@ template <typename Derived, typename InsertedThunksTy>
 void ThunkInserter<Derived, InsertedThunksTy>::createThunkFunction(
     MachineModuleInfo &MMI, StringRef Name, bool Comdat,
     StringRef TargetAttrs) {
-  assert(Name.startswith(getDerived().getThunkPrefix()) &&
+  assert(Name.starts_with(getDerived().getThunkPrefix()) &&
          "Created a thunk with an unexpected prefix!");
 
   Module &M = const_cast<Module &>(*MMI.getModule());
@@ -94,7 +94,7 @@ template <typename Derived, typename InsertedThunksTy>
 bool ThunkInserter<Derived, InsertedThunksTy>::run(MachineModuleInfo &MMI,
                                                    MachineFunction &MF) {
   // If MF is not a thunk, check to see if we need to insert a thunk.
-  if (!MF.getName().startswith(getDerived().getThunkPrefix())) {
+  if (!MF.getName().starts_with(getDerived().getThunkPrefix())) {
     // Only add a thunk if one of the functions has the corresponding feature
     // enabled in its subtarget, and doesn't enable external thunks. The target
     // can use InsertedThunks to detect whether relevant thunks have already
diff --git a/llvm/include/llvm/CodeGen/MIRYamlMapping.h b/llvm/include/llvm/CodeGen/MIRYamlMapping.h
index bf35febb8057..bb8dbb0478ff 100644
--- a/llvm/include/llvm/CodeGen/MIRYamlMapping.h
+++ b/llvm/include/llvm/CodeGen/MIRYamlMapping.h
@@ -433,9 +433,9 @@ template <> struct ScalarTraits<FrameIndex> {
   static StringRef input(StringRef Scalar, void *Ctx, FrameIndex &FI) {
     FI.IsFixed = false;
     StringRef Num;
-    if (Scalar.startswith("%stack.")) {
+    if (Scalar.starts_with("%stack.")) {
       Num = Scalar.substr(7);
-    } else if (Scalar.startswith("%fixed-stack.")) {
+    } else if (Scalar.starts_with("%fixed-stack.")) {
       Num = Scalar.substr(13);
       FI.IsFixed = true;
     } else {
diff --git a/llvm/include/llvm/MC/MCSectionCOFF.h b/llvm/include/llvm/MC/MCSectionCOFF.h
index 373863e21ff0..2faf84f0372c 100644
--- a/llvm/include/llvm/MC/MCSectionCOFF.h
+++ b/llvm/include/llvm/MC/MCSectionCOFF.h
@@ -83,7 +83,7 @@ public:
   }
 
   static bool isImplicitlyDiscardable(StringRef Name) {
-    return Name.startswith(".debug");
+    return Name.starts_with(".debug");
   }
 
   static bool classof(const MCSection *S) { return S->getVariant() == SV_COFF; }
diff --git a/llvm/include/llvm/Object/ELFObjectFile.h b/llvm/include/llvm/Object/ELFObjectFile.h
index 8e16fc148a3c..761c532b9bf1 100644
--- a/llvm/include/llvm/Object/ELFObjectFile.h
+++ b/llvm/include/llvm/Object/ELFObjectFile.h
@@ -742,7 +742,7 @@ Expected<uint32_t> ELFObjectFile<ELFT>::getSymbolFlags(DataRefImpl Sym) const {
   if (EF.getHeader().e_machine == ELF::EM_AARCH64) {
     if (Expected<StringRef> NameOrErr = getSymbolName(Sym)) {
       StringRef Name = *NameOrErr;
-      if (Name.startswith("$d") || Name.startswith("$x"))
+      if (Name.starts_with("$d") || Name.starts_with("$x"))
         Result |= SymbolRef::SF_FormatSpecific;
     } else {
       // TODO: Actually report errors helpfully.
@@ -752,8 +752,8 @@ Expected<uint32_t> ELFObjectFile<ELFT>::getSymbolFlags(DataRefImpl Sym) const {
     if (Expected<StringRef> NameOrErr = getSymbolName(Sym)) {
       StringRef Name = *NameOrErr;
       // TODO Investigate why empty name symbols need to be marked.
-      if (Name.empty() || Name.startswith("$d") || Name.startswith("$t") ||
-          Name.startswith("$a"))
+      if (Name.empty() || Name.starts_with("$d") || Name.starts_with("$t") ||
+          Name.starts_with("$a"))
         Result |= SymbolRef::SF_FormatSpecific;
     } else {
       // TODO: Actually report errors helpfully.
@@ -764,7 +764,7 @@ Expected<uint32_t> ELFObjectFile<ELFT>::getSymbolFlags(DataRefImpl Sym) const {
   } else if (EF.getHeader().e_machine == ELF::EM_CSKY) {
     if (Expected<StringRef> NameOrErr = getSymbolName(Sym)) {
       StringRef Name = *NameOrErr;
-      if (Name.startswith("$d") || Name.startswith("$t"))
+      if (Name.starts_with("$d") || Name.starts_with("$t"))
         Result |= SymbolRef::SF_FormatSpecific;
     } else {
       // TODO: Actually report errors helpfully.
@@ -775,7 +775,7 @@ Expected<uint32_t> ELFObjectFile<ELFT>::getSymbolFlags(DataRefImpl Sym) const {
       StringRef Name = *NameOrErr;
       // Mark empty name symbols (used for label differences) and mapping
       // symbols.
-      if (Name.empty() || Name.startswith("$d") || Name.startswith("$x"))
+      if (Name.empty() || Name.starts_with("$d") || Name.starts_with("$x"))
         Result |= SymbolRef::SF_FormatSpecific;
     } else {
       // TODO: Actually report errors helpfully.
@@ -973,8 +973,8 @@ bool ELFObjectFile<ELFT>::isDebugSection(DataRefImpl Sec) const {
     return false;
   }
   StringRef SectionName = SectionNameOrErr.get();
-  return SectionName.startswith(".debug") ||
-         SectionName.startswith(".zdebug") || SectionName == ".gdb_index";
+  return SectionName.starts_with(".debug") ||
+         SectionName.starts_with(".zdebug") || SectionName == ".gdb_index";
 }
 
 template <class ELFT>
diff --git a/llvm/include/llvm/Passes/PassBuilder.h b/llvm/include/llvm/Passes/PassBuilder.h
index 19ac90842bcb..61417431f8a8 100644
--- a/llvm/include/llvm/Passes/PassBuilder.h
+++ b/llvm/include/llvm/Passes/PassBuilder.h
@@ -720,10 +720,10 @@ template <typename AnalysisT, typename IRUnitT, typename AnalysisManagerT,
 bool parseAnalysisUtilityPasses(
     StringRef AnalysisName, StringRef PipelineName,
     PassManager<IRUnitT, AnalysisManagerT, ExtraArgTs...> &PM) {
-  if (!PipelineName.endswith(">"))
+  if (!PipelineName.ends_with(">"))
     return false;
   // See if this is an invalidate<> pass name
-  if (PipelineName.startswith("invalidate<")) {
+  if (PipelineName.starts_with("invalidate<")) {
     PipelineName = PipelineName.substr(11, PipelineName.size() - 12);
     if (PipelineName != AnalysisName)
       return false;
@@ -732,7 +732,7 @@ bool parseAnalysisUtilityPasses(
   }
 
   // See if this is a require<> pass name
-  if (PipelineName.startswith("require<")) {
+  if (PipelineName.starts_with("require<")) {
     PipelineName = PipelineName.substr(8, PipelineName.size() - 9);
     if (PipelineName != AnalysisName)
       return false;
diff --git a/llvm/include/llvm/ProfileData/SampleProf.h b/llvm/include/llvm/ProfileData/SampleProf.h
index f001f5ee9d39..d995cc69af89 100644
--- a/llvm/include/llvm/ProfileData/SampleProf.h
+++ b/llvm/include/llvm/ProfileData/SampleProf.h
@@ -548,7 +548,7 @@ public:
     assert(!ContextStr.empty());
     // Note that `[]` wrapped input indicates a full context string, otherwise
     // it's treated as context-less function name only.
-    bool HasContext = ContextStr.startswith("[");
+    bool HasContext = ContextStr.starts_with("[");
     if (!HasContext) {
       State = UnknownContext;
       Func = FunctionId(ContextStr);
diff --git a/llvm/include/llvm/Transforms/IPO/Attributor.h b/llvm/include/llvm/Transforms/IPO/Attributor.h
index 97b18e51beee..50167708163e 100644
--- a/llvm/include/llvm/Transforms/IPO/Attributor.h
+++ b/llvm/include/llvm/Transforms/IPO/Attributor.h
@@ -2161,7 +2161,7 @@ public:
     Function *F = I->getFunction();
     auto &ORE = Configuration.OREGetter(F);
 
-    if (RemarkName.startswith("OMP"))
+    if (RemarkName.starts_with("OMP"))
       ORE.emit([&]() {
         return RemarkCB(RemarkKind(Configuration.PassName, RemarkName, I))
                << " [" << RemarkName << "]";
@@ -2181,7 +2181,7 @@ public:
 
     auto &ORE = Configuration.OREGetter(F);
 
-    if (RemarkName.startswith("OMP"))
+    if (RemarkName.starts_with("OMP"))
       ORE.emit([&]() {
         return RemarkCB(RemarkKind(Configuration.PassName, RemarkName, F))
                << " [" << RemarkName << "]";
diff --git a/llvm/lib/Analysis/LoopInfo.cpp b/llvm/lib/Analysis/LoopInfo.cpp
index 7567efbedfb0..87ddfe3e92ae 100644
--- a/llvm/lib/Analysis/LoopInfo.cpp
+++ b/llvm/lib/Analysis/LoopInfo.cpp
@@ -1143,7 +1143,7 @@ MDNode *llvm::makePostTransformationMetadata(LLVMContext &Context,
         if (S)
           IsVectorMetadata =
               llvm::any_of(RemovePrefixes, [S](StringRef Prefix) -> bool {
-                return S->getString().startswith(Prefix);
+                return S->getString().starts_with(Prefix);
               });
       }
       if (!IsVectorMetadata)
diff --git a/llvm/lib/Analysis/VFABIDemangling.cpp b/llvm/lib/Analysis/VFABIDemangling.cpp
index 92af314a41ca..ad918ef7245b 100644
--- a/llvm/lib/Analysis/VFABIDemangling.cpp
+++ b/llvm/lib/Analysis/VFABIDemangling.cpp
@@ -32,7 +32,7 @@ static ParseRet tryParseISA(StringRef &MangledName, VFISAKind &ISA) {
   if (MangledName.empty())
     return ParseRet::Error;
 
-  if (MangledName.startswith(VFABI::_LLVM_)) {
+  if (MangledName.starts_with(VFABI::_LLVM_)) {
     MangledName = MangledName.drop_front(strlen(VFABI::_LLVM_));
     ISA = VFISAKind::LLVM;
   } else {
diff --git a/llvm/lib/AsmParser/LLLexer.cpp b/llvm/lib/AsmParser/LLLexer.cpp
index 919c69fe2783..fcb25f5f1d49 100644
--- a/llvm/lib/AsmParser/LLLexer.cpp
+++ b/llvm/lib/AsmParser/LLLexer.cpp
@@ -922,17 +922,17 @@ lltok::Kind LLLexer::LexIdentifier() {
 
 #undef DWKEYWORD
 
-  if (Keyword.startswith("DIFlag")) {
+  if (Keyword.starts_with("DIFlag")) {
     StrVal.assign(Keyword.begin(), Keyword.end());
     return lltok::DIFlag;
   }
 
-  if (Keyword.startswith("DISPFlag")) {
+  if (Keyword.starts_with("DISPFlag")) {
     StrVal.assign(Keyword.begin(), Keyword.end());
     return lltok::DISPFlag;
   }
 
-  if (Keyword.startswith("CSK_")) {
+  if (Keyword.starts_with("CSK_")) {
     StrVal.assign(Keyword.begin(), Keyword.end());
     return lltok::ChecksumKind;
   }
diff --git a/llvm/lib/BinaryFormat/Magic.cpp b/llvm/lib/BinaryFormat/Magic.cpp
index 420224df57df..255937a5bdd0 100644
--- a/llvm/lib/BinaryFormat/Magic.cpp
+++ b/llvm/lib/BinaryFormat/Magic.cpp
@@ -26,7 +26,7 @@ using namespace llvm::sys::fs;
 
 template <size_t N>
 static bool startswith(StringRef Magic, const char (&S)[N]) {
-  return Magic.startswith(StringRef(S, N - 1));
+  return Magic.starts_with(StringRef(S, N - 1));
 }
 
 /// Identify the magic in magic.
@@ -217,11 +217,11 @@ file_magic llvm::identify_magic(StringRef Magic) {
     if (startswith(Magic, "MZ") && Magic.size() >= 0x3c + 4) {
       uint32_t off = read32le(Magic.data() + 0x3c);
       // PE/COFF file, either EXE or DLL.
-      if (Magic.substr(off).startswith(
+      if (Magic.substr(off).starts_with(
               StringRef(COFF::PEMagic, sizeof(COFF::PEMagic))))
         return file_magic::pecoff_executable;
     }
-    if (Magic.startswith("Microsoft C/C++ MSF 7.00\r\n"))
+    if (Magic.starts_with("Microsoft C/C++ MSF 7.00\r\n"))
       return file_magic::pdb;
     if (startswith(Magic, "MDMP"))
       return file_magic::minidump;
diff --git a/llvm/lib/Bitcode/Reader/MetadataLoader.cpp b/llvm/lib/Bitcode/Reader/MetadataLoader.cpp
index 1a4b55ea3818..910e97489dbb 100644
--- a/llvm/lib/Bitcode/Reader/MetadataLoader.cpp
+++ b/llvm/lib/Bitcode/Reader/MetadataLoader.cpp
@@ -1633,7 +1633,7 @@ Error MetadataLoader::MetadataLoaderImpl::parseOneMetadata(
         // DICompositeType flag specifying whether template parameters are
         // required on declarations of this type.
         StringRef NameStr = Name->getString();
-        if (!NameStr.contains('<') || NameStr.startswith("_STN|"))
+        if (!NameStr.contains('<') || NameStr.starts_with("_STN|"))
           TemplateParams = getMDOrNull(Record[14]);
       }
     } else {
diff --git a/llvm/lib/CodeGen/BasicBlockSectionsProfileReader.cpp b/llvm/lib/CodeGen/BasicBlockSectionsProfileReader.cpp
index 96662378a869..15b6f63e8632 100644
--- a/llvm/lib/CodeGen/BasicBlockSectionsProfileReader.cpp
+++ b/llvm/lib/CodeGen/BasicBlockSectionsProfileReader.cpp
@@ -302,7 +302,7 @@ Error BasicBlockSectionsProfileReader::ReadV0Profile() {
       // specifier starting with `M=`.
       auto [AliasesStr, DIFilenameStr] = S.split(' ');
       SmallString<128> DIFilename;
-      if (DIFilenameStr.startswith("M=")) {
+      if (DIFilenameStr.starts_with("M=")) {
         DIFilename =
             sys::path::remove_leading_dotslash(DIFilenameStr.substr(2));
         if (DIFilename.empty())
diff --git a/llvm/lib/CodeGen/GlobalMerge.cpp b/llvm/lib/CodeGen/GlobalMerge.cpp
index 339019923c00..22b6d31d0634 100644
--- a/llvm/lib/CodeGen/GlobalMerge.cpp
+++ b/llvm/lib/CodeGen/GlobalMerge.cpp
@@ -643,8 +643,7 @@ bool GlobalMerge::doInitialization(Module &M) {
     StringRef Section = GV.getSection();
 
     // Ignore all 'special' globals.
-    if (GV.getName().startswith("llvm.") ||
-        GV.getName().startswith(".llvm."))
+    if (GV.getName().starts_with("llvm.") || GV.getName().starts_with(".llvm."))
       continue;
 
     // Ignore all "required" globals:
diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.cpp b/llvm/lib/CodeGen/MIRParser/MILexer.cpp
index 0a0e386cde61..870611248466 100644
--- a/llvm/lib/CodeGen/MIRParser/MILexer.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MILexer.cpp
@@ -300,8 +300,8 @@ static Cursor maybeLexIdentifier(Cursor C, MIToken &Token) {
 
 static Cursor maybeLexMachineBasicBlock(Cursor C, MIToken &Token,
                                         ErrorCallbackType ErrorCallback) {
-  bool IsReference = C.remaining().startswith("%bb.");
-  if (!IsReference && !C.remaining().startswith("bb."))
+  bool IsReference = C.remaining().starts_with("%bb.");
+  if (!IsReference && !C.remaining().starts_with("bb."))
     return std::nullopt;
   auto Range = C;
   unsigned PrefixLength = IsReference ? 4 : 3;
@@ -335,7 +335,7 @@ static Cursor maybeLexMachineBasicBlock(Cursor C, MIToken &Token,
 
 static Cursor maybeLexIndex(Cursor C, MIToken &Token, StringRef Rule,
                             MIToken::TokenKind Kind) {
-  if (!C.remaining().startswith(Rule) || !isdigit(C.peek(Rule.size())))
+  if (!C.remaining().starts_with(Rule) || !isdigit(C.peek(Rule.size())))
     return std::nullopt;
   auto Range = C;
   C.advance(Rule.size());
@@ -348,7 +348,7 @@ static Cursor maybeLexIndex(Cursor C, MIToken &Token, StringRef Rule,
 
 static Cursor maybeLexIndexAndName(Cursor C, MIToken &Token, StringRef Rule,
                                    MIToken::TokenKind Kind) {
-  if (!C.remaining().startswith(Rule) || !isdigit(C.peek(Rule.size())))
+  if (!C.remaining().starts_with(Rule) || !isdigit(C.peek(Rule.size())))
     return std::nullopt;
   auto Range = C;
   C.advance(Rule.size());
@@ -388,7 +388,7 @@ static Cursor maybeLexConstantPoolItem(Cursor C, MIToken &Token) {
 static Cursor maybeLexSubRegisterIndex(Cursor C, MIToken &Token,
                                        ErrorCallbackType ErrorCallback) {
   const StringRef Rule = "%subreg.";
-  if (!C.remaining().startswith(Rule))
+  if (!C.remaining().starts_with(Rule))
     return std::nullopt;
   return lexName(C, Token, MIToken::SubRegisterIndex, Rule.size(),
                  ErrorCallback);
@@ -397,7 +397,7 @@ static Cursor maybeLexSubRegisterIndex(Cursor C, MIToken &Token,
 static Cursor maybeLexIRBlock(Cursor C, MIToken &Token,
                               ErrorCallbackType ErrorCallback) {
   const StringRef Rule = "%ir-block.";
-  if (!C.remaining().startswith(Rule))
+  if (!C.remaining().starts_with(Rule))
     return std::nullopt;
   if (isdigit(C.peek(Rule.size())))
     return maybeLexIndex(C, Token, Rule, MIToken::IRBlock);
@@ -407,7 +407,7 @@ static Cursor maybeLexIRBlock(Cursor C, MIToken &Token,
 static Cursor maybeLexIRValue(Cursor C, MIToken &Token,
                               ErrorCallbackType ErrorCallback) {
   const StringRef Rule = "%ir.";
-  if (!C.remaining().startswith(Rule))
+  if (!C.remaining().starts_with(Rule))
     return std::nullopt;
   if (isdigit(C.peek(Rule.size())))
     return maybeLexIndex(C, Token, Rule, MIToken::IRValue);
@@ -501,7 +501,7 @@ static Cursor maybeLexExternalSymbol(Cursor C, MIToken &Token,
 static Cursor maybeLexMCSymbol(Cursor C, MIToken &Token,
                                ErrorCallbackType ErrorCallback) {
   const StringRef Rule = "<mcsymbol ";
-  if (!C.remaining().startswith(Rule))
+  if (!C.remaining().starts_with(Rule))
     return std::nullopt;
   auto Start = C;
   C.advance(Rule.size());
diff --git a/llvm/lib/CodeGen/SanitizerBinaryMetadata.cpp b/llvm/lib/CodeGen/SanitizerBinaryMetadata.cpp
index cc29bdce1210..9002a7076840 100644
--- a/llvm/lib/CodeGen/SanitizerBinaryMetadata.cpp
+++ b/llvm/lib/CodeGen/SanitizerBinaryMetadata.cpp
@@ -52,7 +52,7 @@ bool MachineSanitizerBinaryMetadata::runOnMachineFunction(MachineFunction &MF) {
   if (!MD)
     return false;
   const auto &Section = *cast<MDString>(MD->getOperand(0));
-  if (!Section.getString().startswith(kSanitizerBinaryMetadataCoveredSection))
+  if (!Section.getString().starts_with(kSanitizerBinaryMetadataCoveredSection))
     return false;
   auto &AuxMDs = *cast<MDTuple>(MD->getOperand(1));
   // Assume it currently only has features.
diff --git a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
index 9827bd3ff4f1..27d47aab4b68 100644
--- a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
@@ -478,26 +478,21 @@ static SectionKind getELFKindForNamedSection(StringRef Name, SectionKind K) {
   if (Name.empty() || Name[0] != '.') return K;
 
   // Default implementation based on some magic section names.
-  if (Name == ".bss" ||
-      Name.startswith(".bss.") ||
-      Name.startswith(".gnu.linkonce.b.") ||
-      Name.startswith(".llvm.linkonce.b.") ||
-      Name == ".sbss" ||
-      Name.startswith(".sbss.") ||
-      Name.startswith(".gnu.linkonce.sb.") ||
-      Name.startswith(".llvm.linkonce.sb."))
+  if (Name == ".bss" || Name.starts_with(".bss.") ||
+      Name.starts_with(".gnu.linkonce.b.") ||
+      Name.starts_with(".llvm.linkonce.b.") || Name == ".sbss" ||
+      Name.starts_with(".sbss.") || Name.starts_with(".gnu.linkonce.sb.") ||
+      Name.starts_with(".llvm.linkonce.sb."))
     return SectionKind::getBSS();
 
-  if (Name == ".tdata" ||
-      Name.startswith(".tdata.") ||
-      Name.startswith(".gnu.linkonce.td.") ||
-      Name.startswith(".llvm.linkonce.td."))
+  if (Name == ".tdata" || Name.starts_with(".tdata.") ||
+      Name.starts_with(".gnu.linkonce.td.") ||
+      Name.starts_with(".llvm.linkonce.td."))
     return SectionKind::getThreadData();
 
-  if (Name == ".tbss" ||
-      Name.startswith(".tbss.") ||
-      Name.startswith(".gnu.linkonce.tb.") ||
-      Name.startswith(".llvm.linkonce.tb."))
+  if (Name == ".tbss" || Name.starts_with(".tbss.") ||
+      Name.starts_with(".gnu.linkonce.tb.") ||
+      Name.starts_with(".llvm.linkonce.tb."))
     return SectionKind::getThreadBSS();
 
   return K;
@@ -512,7 +507,7 @@ static unsigned getELFSectionType(StringRef Name, SectionKind K) {
   // Use SHT_NOTE for section whose name starts with ".note" to allow
   // emitting ELF notes from C variable declaration.
   // See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77609
-  if (Name.startswith(".note"))
+  if (Name.starts_with(".note"))
     return ELF::SHT_NOTE;
 
   if (hasPrefix(Name, ".init_array"))
@@ -752,7 +747,7 @@ calcUniqueIDUpdateFlagsAndSize(const GlobalObject *GO, StringRef SectionName,
       getELFSectionNameForGlobal(GO, Kind, Mang, TM, EntrySize, false);
   if (SymbolMergeable &&
       Ctx.isELFImplicitMergeableSectionNamePrefix(SectionName) &&
-      SectionName.startswith(ImplicitSectionNameStem))
+      SectionName.starts_with(ImplicitSectionNameStem))
     return MCContext::GenericSectionID;
 
   // We have seen this section name before, but with different flags or entity
@@ -1036,7 +1031,7 @@ MCSection *TargetLoweringObjectFileELF::getSectionForMachineBasicBlock(
   SmallString<128> Name;
   StringRef FunctionSectionName = MBB.getParent()->getSection()->getName();
   if (FunctionSectionName.equals(".text") ||
-      FunctionSectionName.startswith(".text.")) {
+      FunctionSectionName.starts_with(".text.")) {
     // Function is in a regular .text section.
     StringRef FunctionName = MBB.getParent()->getName();
     if (MBB.getSectionID() == MBBSectionID::ColdSectionID) {
diff --git a/llvm/lib/CodeGen/WinEHPrepare.cpp b/llvm/lib/CodeGen/WinEHPrepare.cpp
index bd14e8104a6a..95976c218c2f 100644
--- a/llvm/lib/CodeGen/WinEHPrepare.cpp
+++ b/llvm/lib/CodeGen/WinEHPrepare.cpp
@@ -324,7 +324,7 @@ void llvm::calculateSEHStateForAsynchEH(const BasicBlock *BB, int State,
       const Constant *FilterOrNull = cast<Constant>(
           cast<CatchPadInst>(I)->getArgOperand(0)->stripPointerCasts());
       const Function *Filter = dyn_cast<Function>(FilterOrNull);
-      if (!Filter || !Filter->getName().startswith("__IsLocalUnwind"))
+      if (!Filter || !Filter->getName().starts_with("__IsLocalUnwind"))
         State = EHInfo.SEHUnwindMap[State].ToState; // Retrive next State
     } else if ((isa<CleanupReturnInst>(TI) || isa<CatchReturnInst>(TI)) &&
                State > 0) {
diff --git a/llvm/lib/DWARFLinker/DWARFLinker.cpp b/llvm/lib/DWARFLinker/DWARFLinker.cpp
index 1a7ea47adc5c..10967123a562 100644
--- a/llvm/lib/DWARFLinker/DWARFLinker.cpp
+++ b/llvm/lib/DWARFLinker/DWARFLinker.cpp
@@ -204,18 +204,18 @@ static void analyzeImportedModule(
     return;
 
   StringRef Path = dwarf::toStringRef(DIE.find(dwarf::DW_AT_LLVM_include_path));
-  if (!Path.endswith(".swiftinterface"))
+  if (!Path.ends_with(".swiftinterface"))
     return;
   // Don't track interfaces that are part of the SDK.
   StringRef SysRoot = dwarf::toStringRef(DIE.find(dwarf::DW_AT_LLVM_sysroot));
   if (SysRoot.empty())
     SysRoot = CU.getSysRoot();
-  if (!SysRoot.empty() && Path.startswith(SysRoot))
+  if (!SysRoot.empty() && Path.starts_with(SysRoot))
     return;
   // Don't track interfaces that are part of the toolchain.
   // For example: Swift, _Concurrency, ...
   SmallString<128> Toolchain = guessToolchainBaseDir(SysRoot);
-  if (!Toolchain.empty() && Path.startswith(Toolchain))
+  if (!Toolchain.empty() && Path.starts_with(Toolchain))
     return;
   std::optional<const char *> Name =
       dwarf::toString(DIE.find(dwarf::DW_AT_name));
diff --git a/llvm/lib/DWARFLinkerParallel/DWARFLinkerCompileUnit.cpp b/llvm/lib/DWARFLinkerParallel/DWARFLinkerCompileUnit.cpp
index 48e7cb1fd7e2..3f0e75690272 100644
--- a/llvm/lib/DWARFLinkerParallel/DWARFLinkerCompileUnit.cpp
+++ b/llvm/lib/DWARFLinkerParallel/DWARFLinkerCompileUnit.cpp
@@ -271,19 +271,19 @@ void CompileUnit::analyzeImportedModule(const DWARFDebugInfoEntry *DieEntry) {
 
   StringRef Path =
       dwarf::toStringRef(find(DieEntry, dwarf::DW_AT_LLVM_include_path));
-  if (!Path.endswith(".swiftinterface"))
+  if (!Path.ends_with(".swiftinterface"))
     return;
   // Don't track interfaces that are part of the SDK.
   StringRef SysRoot =
       dwarf::toStringRef(find(DieEntry, dwarf::DW_AT_LLVM_sysroot));
   if (SysRoot.empty())
     SysRoot = getSysRoot();
-  if (!SysRoot.empty() && Path.startswith(SysRoot))
+  if (!SysRoot.empty() && Path.starts_with(SysRoot))
     return;
   // Don't track interfaces that are part of the toolchain.
   // For example: Swift, _Concurrency, ...
   SmallString<128> Toolchain = guessToolchainBaseDir(SysRoot);
-  if (!Toolchain.empty() && Path.startswith(Toolchain))
+  if (!Toolchain.empty() && Path.starts_with(Toolchain))
     return;
   if (std::optional<DWARFFormValue> Val = find(DieEntry, dwarf::DW_AT_name)) {
     Expected<const char *> Name = Val->getAsCString();
diff --git a/llvm/lib/DWARFLinkerParallel/SyntheticTypeNameBuilder.cpp b/llvm/lib/DWARFLinkerParallel/SyntheticTypeNameBuilder.cpp
index e0900f7a8e3d..a9b4478e33c4 100644
--- a/llvm/lib/DWARFLinkerParallel/SyntheticTypeNameBuilder.cpp
+++ b/llvm/lib/DWARFLinkerParallel/SyntheticTypeNameBuilder.cpp
@@ -333,7 +333,7 @@ Error SyntheticTypeNameBuilder::addTypeName(UnitEntryPairTy InputUnitEntryPair,
 
     HasShortName = true;
     HasTemplatesInShortName =
-        Name.endswith(">") && Name.count("<") != 0 && !Name.endswith("<=>");
+        Name.ends_with(">") && Name.count("<") != 0 && !Name.ends_with("<=>");
   } else {
     // Finally check for declaration attributes.
     addDieNameFromDeclFileAndDeclLine(InputUnitEntryPair, HasDeclFileName);
diff --git a/llvm/lib/ExecutionEngine/JITLink/ELF_x86_64.cpp b/llvm/lib/ExecutionEngine/JITLink/ELF_x86_64.cpp
index 46f8064bb168..a1fe9c5fcd73 100644
--- a/llvm/lib/ExecutionEngine/JITLink/ELF_x86_64.cpp
+++ b/llvm/lib/ExecutionEngine/JITLink/ELF_x86_64.cpp
@@ -349,11 +349,11 @@ identifyELFSectionStartAndEndSymbols(LinkGraph &G, Symbol &Sym) {
   constexpr StringRef EndSymbolPrefix = "__end";
 
   auto SymName = Sym.getName();
-  if (SymName.startswith(StartSymbolPrefix)) {
+  if (SymName.starts_with(StartSymbolPrefix)) {
     if (auto *Sec =
             G.findSectionByName(SymName.drop_front(StartSymbolPrefix.size())))
       return {*Sec, true};
-  } else if (SymName.startswith(EndSymbolPrefix)) {
+  } else if (SymName.starts_with(EndSymbolPrefix)) {
     if (auto *Sec =
             G.findSectionByName(SymName.drop_front(EndSymbolPrefix.size())))
       return {*Sec, false};
diff --git a/llvm/lib/ExecutionEngine/JITLink/MachOLinkGraphBuilder.cpp b/llvm/lib/ExecutionEngine/JITLink/MachOLinkGraphBuilder.cpp
index bcbc429cae12..bb21f633d982 100644
--- a/llvm/lib/ExecutionEngine/JITLink/MachOLinkGraphBuilder.cpp
+++ b/llvm/lib/ExecutionEngine/JITLink/MachOLinkGraphBuilder.cpp
@@ -73,7 +73,7 @@ Linkage MachOLinkGraphBuilder::getLinkage(uint16_t Desc) {
 
 Scope MachOLinkGraphBuilder::getScope(StringRef Name, uint8_t Type) {
   if (Type & MachO::N_EXT) {
-    if ((Type & MachO::N_PEXT) || Name.startswith("l"))
+    if ((Type & MachO::N_PEXT) || Name.starts_with("l"))
       return Scope::Hidden;
     else
       return Scope::Default;
diff --git a/llvm/lib/ExecutionEngine/Orc/Debugging/DebugInfoSupport.cpp b/llvm/lib/ExecutionEngine/Orc/Debugging/DebugInfoSupport.cpp
index b541db3672f4..f65ec27ff875 100644
--- a/llvm/lib/ExecutionEngine/Orc/Debugging/DebugInfoSupport.cpp
+++ b/llvm/lib/ExecutionEngine/Orc/Debugging/DebugInfoSupport.cpp
@@ -105,7 +105,7 @@ llvm::orc::createDWARFContext(LinkGraph &G) {
       auto SecData = getSectionData(Sec);
       auto Name = Sec.getName();
       // DWARFContext expects the section name to not start with a dot
-      if (Name.startswith("."))
+      if (Name.starts_with("."))
         Name = Name.drop_front();
       LLVM_DEBUG(dbgs() << "Creating DWARFContext section " << Name
                         << " with size " << SecData.size() << "\n");
diff --git a/llvm/lib/ExecutionEngine/Orc/Debugging/DebuggerSupportPlugin.cpp b/llvm/lib/ExecutionEngine/Orc/Debugging/DebuggerSupportPlugin.cpp
index c6ffd9f7c2e3..e387b06ee934 100644
--- a/llvm/lib/ExecutionEngine/Orc/Debugging/DebuggerSupportPlugin.cpp
+++ b/llvm/lib/ExecutionEngine/Orc/Debugging/DebuggerSupportPlugin.cpp
@@ -34,7 +34,7 @@ class MachODebugObjectSynthesizerBase
     : public GDBJITDebugInfoRegistrationPlugin::DebugSectionSynthesizer {
 public:
   static bool isDebugSection(Section &Sec) {
-    return Sec.getName().startswith("__DWARF,");
+    return Sec.getName().starts_with("__DWARF,");
   }
 
   MachODebugObjectSynthesizerBase(LinkGraph &G, ExecutorAddr RegisterActionAddr)
diff --git a/llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp b/llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
index 7316b2dce8ab..8d5608cc4d4c 100644
--- a/llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
+++ b/llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
@@ -103,8 +103,8 @@ bool StaticInitGVIterator::isStaticInitGlobal(GlobalValue &GV) {
     // FIXME: These section checks are too strict: We should match first and
     // second word split by comma.
     if (GV.hasSection() &&
-        (GV.getSection().startswith("__DATA,__objc_classlist") ||
-         GV.getSection().startswith("__DATA,__objc_selrefs")))
+        (GV.getSection().starts_with("__DATA,__objc_classlist") ||
+         GV.getSection().starts_with("__DATA,__objc_selrefs")))
       return true;
   }
 
@@ -503,7 +503,7 @@ Error DLLImportDefinitionGenerator::tryToGenerate(
   DenseMap<StringRef, SymbolLookupFlags> ToLookUpSymbols;
   for (auto &KV : Symbols) {
     StringRef Deinterned = *KV.first;
-    if (Deinterned.startswith(getImpPrefix()))
+    if (Deinterned.starts_with(getImpPrefix()))
       Deinterned = Deinterned.drop_front(StringRef(getImpPrefix()).size());
     // Don't degrade the required state
     if (ToLookUpSymbols.count(Deinterned) &&
diff --git a/llvm/lib/ExecutionEngine/Orc/IndirectionUtils.cpp b/llvm/lib/ExecutionEngine/Orc/IndirectionUtils.cpp
index adf38659de3d..f9efff148df9 100644
--- a/llvm/lib/ExecutionEngine/Orc/IndirectionUtils.cpp
+++ b/llvm/lib/ExecutionEngine/Orc/IndirectionUtils.cpp
@@ -285,7 +285,7 @@ std::vector<GlobalValue *> SymbolLinkagePromoter::operator()(Module &M) {
     // Rename if necessary.
     if (!GV.hasName())
       GV.setName("__orc_anon." + Twine(NextId++));
-    else if (GV.getName().startswith("\01L"))
+    else if (GV.getName().starts_with("\01L"))
       GV.setName("__" + GV.getName().substr(1) + "." + Twine(NextId++));
     else if (GV.hasLocalLinkage())
       GV.setName("__orc_lcl." + GV.getName() + "." + Twine(NextId++));
diff --git a/llvm/lib/ExecutionEngine/Orc/LLJIT.cpp b/llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
index 2ce8058c918d..a19e17029810 100644
--- a/llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
+++ b/llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
@@ -213,11 +213,11 @@ public:
       // will trigger a lookup to materialize the module) and the InitFunctions
       // map (which holds the names of the symbols to execute).
       for (auto &KV : MU.getSymbols())
-        if ((*KV.first).startswith(InitFunctionPrefix)) {
+        if ((*KV.first).starts_with(InitFunctionPrefix)) {
           InitSymbols[&JD].add(KV.first,
                                SymbolLookupFlags::WeaklyReferencedSymbol);
           InitFunctions[&JD].add(KV.first);
-        } else if ((*KV.first).startswith(DeInitFunctionPrefix)) {
+        } else if ((*KV.first).starts_with(DeInitFunctionPrefix)) {
           DeInitFunctions[&JD].add(KV.first);
         }
     }
diff --git a/llvm/lib/ExecutionEngine/Orc/ObjectFileInterface.cpp b/llvm/lib/ExecutionEngine/Orc/ObjectFileInterface.cpp
index 7c8fa63477d0..0286b0c93197 100644
--- a/llvm/lib/ExecutionEngine/Orc/ObjectFileInterface.cpp
+++ b/llvm/lib/ExecutionEngine/Orc/ObjectFileInterface.cpp
@@ -72,7 +72,7 @@ getMachOObjectFileSymbolInfo(ExecutionSession &ES,
       return SymFlags.takeError();
 
     // Strip the 'exported' flag from MachO linker-private symbols.
-    if (Name->startswith("l"))
+    if (Name->starts_with("l"))
       *SymFlags &= ~JITSymbolFlags::Exported;
 
     I.SymbolFlags[ES.intern(*Name)] = std::move(*SymFlags);
diff --git a/llvm/lib/ExecutionEngine/Orc/Shared/ObjectFormats.cpp b/llvm/lib/ExecutionEngine/Orc/Shared/ObjectFormats.cpp
index 1d9d23e64158..a407fcab6ae3 100644
--- a/llvm/lib/ExecutionEngine/Orc/Shared/ObjectFormats.cpp
+++ b/llvm/lib/ExecutionEngine/Orc/Shared/ObjectFormats.cpp
@@ -102,7 +102,7 @@ bool isELFInitializerSection(StringRef SecName) {
 }
 
 bool isCOFFInitializerSection(StringRef SecName) {
-  return SecName.startswith(".CRT");
+  return SecName.starts_with(".CRT");
 }
 
 } // namespace orc
diff --git a/llvm/lib/ExecutionEngine/RuntimeDyld/JITSymbol.cpp b/llvm/lib/ExecutionEngine/RuntimeDyld/JITSymbol.cpp
index 210fbf6e43e3..c153b4464568 100644
--- a/llvm/lib/ExecutionEngine/RuntimeDyld/JITSymbol.cpp
+++ b/llvm/lib/ExecutionEngine/RuntimeDyld/JITSymbol.cpp
@@ -42,7 +42,7 @@ JITSymbolFlags llvm::JITSymbolFlags::fromGlobalValue(const GlobalValue &GV) {
     const auto &DL = M->getDataLayout();
     StringRef LPGP = DL.getLinkerPrivateGlobalPrefix();
     if (!LPGP.empty() && GV.getName().front() == '\01' &&
-        GV.getName().substr(1).startswith(LPGP))
+        GV.getName().substr(1).starts_with(LPGP))
       Flags &= ~JITSymbolFlags::Exported;
   }
 
diff --git a/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldCOFF.cpp b/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldCOFF.cpp
index 9255311f992d..25a2d8780fb5 100644
--- a/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldCOFF.cpp
+++ b/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldCOFF.cpp
@@ -83,7 +83,8 @@ uint64_t RuntimeDyldCOFF::getDLLImportOffset(unsigned SectionID, StubMap &Stubs,
                                              StringRef Name,
                                              bool SetSectionIDMinus1) {
   LLVM_DEBUG(dbgs() << "Getting DLLImport entry for " << Name << "... ");
-  assert(Name.startswith(getImportSymbolPrefix()) && "Not a DLLImport symbol?");
+  assert(Name.starts_with(getImportSymbolPrefix()) &&
+         "Not a DLLImport symbol?");
   RelocationValueRef Reloc;
   Reloc.SymbolName = Name.data();
   auto I = Stubs.find(Reloc);
diff --git a/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpp b/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpp
index 68497305f06b..7fadbdd6a1ff 100644
--- a/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpp
+++ b/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpp
@@ -142,7 +142,7 @@ private:
       std::tie(Token, Remaining) = parseNumberString(Expr);
     else {
       unsigned TokLen = 1;
-      if (Expr.startswith("<<") || Expr.startswith(">>"))
+      if (Expr.starts_with("<<") || Expr.starts_with(">>"))
         TokLen = 2;
       Token = Expr.substr(0, TokLen);
     }
@@ -177,9 +177,9 @@ private:
       return std::make_pair(BinOpToken::Invalid, "");
 
     // Handle the two 2-character tokens.
-    if (Expr.startswith("<<"))
+    if (Expr.starts_with("<<"))
       return std::make_pair(BinOpToken::ShiftLeft, Expr.substr(2).ltrim());
-    if (Expr.startswith(">>"))
+    if (Expr.starts_with(">>"))
       return std::make_pair(BinOpToken::ShiftRight, Expr.substr(2).ltrim());
 
     // Handle one-character tokens.
@@ -242,7 +242,7 @@ private:
   // On success, returns a pair containing the value of the operand, plus
   // the expression remaining to be evaluated.
   std::pair<EvalResult, StringRef> evalDecodeOperand(StringRef Expr) const {
-    if (!Expr.startswith("("))
+    if (!Expr.starts_with("("))
       return std::make_pair(unexpectedToken(Expr, Expr, "expected '('"), "");
     StringRef RemainingExpr = Expr.substr(1).ltrim();
     StringRef Symbol;
@@ -273,7 +273,7 @@ private:
           "");
     }
 
-    if (!RemainingExpr.startswith(","))
+    if (!RemainingExpr.starts_with(","))
       return std::make_pair(
           unexpectedToken(RemainingExpr, RemainingExpr, "expected ','"), "");
     RemainingExpr = RemainingExpr.substr(1).ltrim();
@@ -283,7 +283,7 @@ private:
     if (OpIdxExpr.hasError())
       return std::make_pair(OpIdxExpr, "");
 
-    if (!RemainingExpr.startswith(")"))
+    if (!RemainingExpr.starts_with(")"))
       return std::make_pair(
           unexpectedToken(RemainingExpr, RemainingExpr, "expected ')'"), "");
     RemainingExpr = RemainingExpr.substr(1).ltrim();
@@ -343,7 +343,7 @@ private:
   // expression remaining to be evaluated.
   std::pair<EvalResult, StringRef> evalNextPC(StringRef Expr,
                                               ParseContext PCtx) const {
-    if (!Expr.startswith("("))
+    if (!Expr.starts_with("("))
       return std::make_pair(unexpectedToken(Expr, Expr, "expected '('"), "");
     StringRef RemainingExpr = Expr.substr(1).ltrim();
     StringRef Symbol;
@@ -354,7 +354,7 @@ private:
           EvalResult(("Cannot decode unknown symbol '" + Symbol + "'").str()),
           "");
 
-    if (!RemainingExpr.startswith(")"))
+    if (!RemainingExpr.starts_with(")"))
       return std::make_pair(
           unexpectedToken(RemainingExpr, RemainingExpr, "expected ')'"), "");
     RemainingExpr = RemainingExpr.substr(1).ltrim();
@@ -381,7 +381,7 @@ private:
   // remaining to be evaluated.
   std::pair<EvalResult, StringRef>
   evalStubOrGOTAddr(StringRef Expr, ParseContext PCtx, bool IsStubAddr) const {
-    if (!Expr.startswith("("))
+    if (!Expr.starts_with("("))
       return std::make_pair(unexpectedToken(Expr, Expr, "expected '('"), "");
     StringRef RemainingExpr = Expr.substr(1).ltrim();
 
@@ -392,7 +392,7 @@ private:
     StubContainerName = RemainingExpr.substr(0, ComaIdx).rtrim();
     RemainingExpr = RemainingExpr.substr(ComaIdx).ltrim();
 
-    if (!RemainingExpr.startswith(","))
+    if (!RemainingExpr.starts_with(","))
       return std::make_pair(
           unexpectedToken(RemainingExpr, Expr, "expected ','"), "");
     RemainingExpr = RemainingExpr.substr(1).ltrim();
@@ -400,7 +400,7 @@ private:
     StringRef Symbol;
     std::tie(Symbol, RemainingExpr) = parseSymbol(RemainingExpr);
 
-    if (!RemainingExpr.startswith(")"))
+    if (!RemainingExpr.starts_with(")"))
       return std::make_pair(
           unexpectedToken(RemainingExpr, Expr, "expected ')'"), "");
     RemainingExpr = RemainingExpr.substr(1).ltrim();
@@ -418,7 +418,7 @@ private:
 
   std::pair<EvalResult, StringRef> evalSectionAddr(StringRef Expr,
                                                    ParseContext PCtx) const {
-    if (!Expr.startswith("("))
+    if (!Expr.starts_with("("))
       return std::make_pair(unexpectedToken(Expr, Expr, "expected '('"), "");
     StringRef RemainingExpr = Expr.substr(1).ltrim();
 
@@ -429,7 +429,7 @@ private:
     FileName = RemainingExpr.substr(0, ComaIdx).rtrim();
     RemainingExpr = RemainingExpr.substr(ComaIdx).ltrim();
 
-    if (!RemainingExpr.startswith(","))
+    if (!RemainingExpr.starts_with(","))
       return std::make_pair(
           unexpectedToken(RemainingExpr, Expr, "expected ','"), "");
     RemainingExpr = RemainingExpr.substr(1).ltrim();
@@ -439,7 +439,7 @@ private:
     SectionName = RemainingExpr.substr(0, CloseParensIdx).rtrim();
     RemainingExpr = RemainingExpr.substr(CloseParensIdx).ltrim();
 
-    if (!RemainingExpr.startswith(")"))
+    if (!RemainingExpr.starts_with(")"))
       return std::make_pair(
           unexpectedToken(RemainingExpr, Expr, "expected ')'"), "");
     RemainingExpr = RemainingExpr.substr(1).ltrim();
@@ -480,7 +480,7 @@ private:
       std::string ErrMsg("No known address for symbol '");
       ErrMsg += Symbol;
       ErrMsg += "'";
-      if (Symbol.startswith("L"))
+      if (Symbol.starts_with("L"))
         ErrMsg += " (this appears to be an assembler local label - "
                   " perhaps drop the 'L'?)";
 
@@ -501,7 +501,7 @@ private:
   // pair representing the number and the expression remaining to be parsed.
   std::pair<StringRef, StringRef> parseNumberString(StringRef Expr) const {
     size_t FirstNonDigit = StringRef::npos;
-    if (Expr.startswith("0x")) {
+    if (Expr.starts_with("0x")) {
       FirstNonDigit = Expr.find_first_not_of("0123456789abcdefABCDEF", 2);
       if (FirstNonDigit == StringRef::npos)
         FirstNonDigit = Expr.size();
@@ -535,14 +535,14 @@ private:
   // remaining to be parsed.
   std::pair<EvalResult, StringRef> evalParensExpr(StringRef Expr,
                                                   ParseContext PCtx) const {
-    assert(Expr.startswith("(") && "Not a parenthesized expression");
+    assert(Expr.starts_with("(") && "Not a parenthesized expression");
     EvalResult SubExprResult;
     StringRef RemainingExpr;
     std::tie(SubExprResult, RemainingExpr) =
         evalComplexExpr(evalSimpleExpr(Expr.substr(1).ltrim(), PCtx), PCtx);
     if (SubExprResult.hasError())
       return std::make_pair(SubExprResult, "");
-    if (!RemainingExpr.startswith(")"))
+    if (!RemainingExpr.starts_with(")"))
       return std::make_pair(
           unexpectedToken(RemainingExpr, Expr, "expected ')'"), "");
     RemainingExpr = RemainingExpr.substr(1).ltrim();
@@ -554,11 +554,11 @@ private:
   // Return a pair containing the result, plus the expression remaining to be
   // parsed.
   std::pair<EvalResult, StringRef> evalLoadExpr(StringRef Expr) const {
-    assert(Expr.startswith("*") && "Not a load expression");
+    assert(Expr.starts_with("*") && "Not a load expression");
     StringRef RemainingExpr = Expr.substr(1).ltrim();
 
     // Parse read size.
-    if (!RemainingExpr.startswith("{"))
+    if (!RemainingExpr.starts_with("{"))
       return std::make_pair(EvalResult("Expected '{' following '*'."), "");
     RemainingExpr = RemainingExpr.substr(1).ltrim();
     EvalResult ReadSizeExpr;
@@ -568,7 +568,7 @@ private:
     uint64_t ReadSize = ReadSizeExpr.getValue();
     if (ReadSize < 1 || ReadSize > 8)
       return std::make_pair(EvalResult("Invalid size for dereference."), "");
-    if (!RemainingExpr.startswith("}"))
+    if (!RemainingExpr.starts_with("}"))
       return std::make_pair(EvalResult("Missing '}' for dereference."), "");
     RemainingExpr = RemainingExpr.substr(1).ltrim();
 
@@ -625,7 +625,7 @@ private:
       return std::make_pair(SubExprResult, RemainingExpr);
 
     // Evaluate bit-slice if present.
-    if (RemainingExpr.startswith("["))
+    if (RemainingExpr.starts_with("["))
       std::tie(SubExprResult, RemainingExpr) =
           evalSliceExpr(std::make_pair(SubExprResult, RemainingExpr));
 
@@ -645,7 +645,7 @@ private:
     StringRef RemainingExpr;
     std::tie(SubExprResult, RemainingExpr) = Ctx;
 
-    assert(RemainingExpr.startswith("[") && "Not a slice expr.");
+    assert(RemainingExpr.starts_with("[") && "Not a slice expr.");
     RemainingExpr = RemainingExpr.substr(1).ltrim();
 
     EvalResult HighBitExpr;
@@ -654,7 +654,7 @@ private:
     if (HighBitExpr.hasError())
       return std::make_pair(HighBitExpr, RemainingExpr);
 
-    if (!RemainingExpr.startswith(":"))
+    if (!RemainingExpr.starts_with(":"))
       return std::make_pair(
           unexpectedToken(RemainingExpr, RemainingExpr, "expected ':'"), "");
     RemainingExpr = RemainingExpr.substr(1).ltrim();
@@ -665,7 +665,7 @@ private:
     if (LowBitExpr.hasError())
       return std::make_pair(LowBitExpr, RemainingExpr);
 
-    if (!RemainingExpr.startswith("]"))
+    if (!RemainingExpr.starts_with("]"))
       return std::make_pair(
           unexpectedToken(RemainingExpr, RemainingExpr, "expected ']'"), "");
     RemainingExpr = RemainingExpr.substr(1).ltrim();
@@ -846,7 +846,7 @@ bool RuntimeDyldCheckerImpl::checkAllRulesInBuffer(StringRef RulePrefix,
       ++LineEnd;
 
     StringRef Line(LineStart, LineEnd - LineStart);
-    if (Line.startswith(RulePrefix))
+    if (Line.starts_with(RulePrefix))
       CheckExpr += Line.substr(RulePrefix.size()).str();
 
     // If there's a check expr string...
diff --git a/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldCOFFAArch64.h b/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldCOFFAArch64.h
index a1151b81d141..66c9753a72fd 100644
--- a/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldCOFFAArch64.h
+++ b/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldCOFFAArch64.h
@@ -174,7 +174,7 @@ public:
     unsigned TargetSectionID = -1;
     uint64_t TargetOffset = -1;
 
-    if (TargetName.startswith(getImportSymbolPrefix())) {
+    if (TargetName.starts_with(getImportSymbolPrefix())) {
       TargetSectionID = SectionID;
       TargetOffset = getDLLImportOffset(SectionID, Stubs, TargetName);
       TargetName = StringRef();
diff --git a/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldCOFFI386.h b/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldCOFFI386.h
index 2a54728fd0bf..0d5afc289b8c 100644
--- a/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldCOFFI386.h
+++ b/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldCOFFI386.h
@@ -60,7 +60,7 @@ public:
 
     unsigned TargetSectionID = -1;
     uint64_t TargetOffset = -1;
-    if (TargetName.startswith(getImportSymbolPrefix())) {
+    if (TargetName.starts_with(getImportSymbolPrefix())) {
       TargetSectionID = SectionID;
       TargetOffset = getDLLImportOffset(SectionID, Stubs, TargetName, true);
       TargetName = StringRef();
diff --git a/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldCOFFThumb.h b/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldCOFFThumb.h
index a3e66c6bc0ec..c079d8896c1d 100644
--- a/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldCOFFThumb.h
+++ b/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldCOFFThumb.h
@@ -129,7 +129,7 @@ public:
     unsigned TargetSectionID = -1;
     uint64_t TargetOffset = -1;
 
-    if (TargetName.startswith(getImportSymbolPrefix())) {
+    if (TargetName.starts_with(getImportSymbolPrefix())) {
       TargetSectionID = SectionID;
       TargetOffset = getDLLImportOffset(SectionID, Stubs, TargetName, true);
       TargetName = StringRef();
diff --git a/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldCOFFX86_64.h b/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldCOFFX86_64.h
index 43ce64af8685..984a8d765c84 100644
--- a/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldCOFFX86_64.h
+++ b/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldCOFFX86_64.h
@@ -226,7 +226,7 @@ public:
     unsigned TargetSectionID = 0;
     uint64_t TargetOffset = 0;
 
-    if (TargetName.startswith(getImportSymbolPrefix())) {
+    if (TargetName.starts_with(getImportSymbolPrefix())) {
       assert(IsExtern && "DLLImport not marked extern?");
       TargetSectionID = SectionID;
       TargetOffset = getDLLImportOffset(SectionID, Stubs, TargetName);
diff --git a/llvm/lib/FileCheck/FileCheck.cpp b/llvm/lib/FileCheck/FileCheck.cpp
index ac8f52d586bc..b728c14d288a 100644
--- a/llvm/lib/FileCheck/FileCheck.cpp
+++ b/llvm/lib/FileCheck/FileCheck.cpp
@@ -404,7 +404,7 @@ Expected<std::unique_ptr<ExpressionAST>> Pattern::parseNumericOperand(
     StringRef &Expr, AllowedOperand AO, bool MaybeInvalidConstraint,
     std::optional<size_t> LineNumber, FileCheckPatternContext *Context,
     const SourceMgr &SM) {
-  if (Expr.startswith("(")) {
+  if (Expr.starts_with("(")) {
     if (AO != AllowedOperand::Any)
       return ErrorDiagnostic::get(
           SM, Expr, "parenthesized expression not permitted here");
@@ -417,7 +417,7 @@ Expected<std::unique_ptr<ExpressionAST>> Pattern::parseNumericOperand(
         parseVariable(Expr, SM);
     if (ParseVarResult) {
       // Try to parse a function call.
-      if (Expr.ltrim(SpaceChars).startswith("(")) {
+      if (Expr.ltrim(SpaceChars).starts_with("(")) {
         if (AO != AllowedOperand::Any)
           return ErrorDiagnostic::get(SM, ParseVarResult->Name,
                                       "unexpected function call");
@@ -458,7 +458,7 @@ Expected<std::unique_ptr<ExpressionAST>>
 Pattern::parseParenExpr(StringRef &Expr, std::optional<size_t> LineNumber,
                         FileCheckPatternContext *Context, const SourceMgr &SM) {
   Expr = Expr.ltrim(SpaceChars);
-  assert(Expr.startswith("("));
+  assert(Expr.starts_with("("));
 
   // Parse right operand.
   Expr.consume_front("(");
@@ -471,7 +471,7 @@ Pattern::parseParenExpr(StringRef &Expr, std::optional<size_t> LineNumber,
       Expr, AllowedOperand::Any, /*MaybeInvalidConstraint=*/false, LineNumber,
       Context, SM);
   Expr = Expr.ltrim(SpaceChars);
-  while (SubExprResult && !Expr.empty() && !Expr.startswith(")")) {
+  while (SubExprResult && !Expr.empty() && !Expr.starts_with(")")) {
     StringRef OrigExpr = Expr;
     SubExprResult = parseBinop(OrigExpr, Expr, std::move(*SubExprResult), false,
                                LineNumber, Context, SM);
@@ -537,7 +537,7 @@ Pattern::parseCallExpr(StringRef &Expr, StringRef FuncName,
                        std::optional<size_t> LineNumber,
                        FileCheckPatternContext *Context, const SourceMgr &SM) {
   Expr = Expr.ltrim(SpaceChars);
-  assert(Expr.startswith("("));
+  assert(Expr.starts_with("("));
 
   auto OptFunc = StringSwitch<binop_eval_t>(FuncName)
                      .Case("add", exprAdd)
@@ -557,8 +557,8 @@ Pattern::parseCallExpr(StringRef &Expr, StringRef FuncName,
 
   // Parse call arguments, which are comma separated.
   SmallVector<std::unique_ptr<ExpressionAST>, 4> Args;
-  while (!Expr.empty() && !Expr.startswith(")")) {
-    if (Expr.startswith(","))
+  while (!Expr.empty() && !Expr.starts_with(")")) {
+    if (Expr.starts_with(","))
       return ErrorDiagnostic::get(SM, Expr, "missing argument");
 
     // Parse the argument, which is an arbitary expression.
@@ -569,7 +569,7 @@ Pattern::parseCallExpr(StringRef &Expr, StringRef FuncName,
     while (Arg && !Expr.empty()) {
       Expr = Expr.ltrim(SpaceChars);
       // Have we reached an argument terminator?
-      if (Expr.startswith(",") || Expr.startswith(")"))
+      if (Expr.starts_with(",") || Expr.starts_with(")"))
         break;
 
       // Arg = Arg <op> <expr>
@@ -588,7 +588,7 @@ Pattern::parseCallExpr(StringRef &Expr, StringRef FuncName,
       break;
 
     Expr = Expr.ltrim(SpaceChars);
-    if (Expr.startswith(")"))
+    if (Expr.starts_with(")"))
       return ErrorDiagnostic::get(SM, Expr, "missing argument");
   }
 
@@ -818,7 +818,7 @@ bool Pattern::parsePattern(StringRef PatternStr, StringRef Prefix,
   // by escaping scary characters in fixed strings, building up one big regex.
   while (!PatternStr.empty()) {
     // RegEx matches.
-    if (PatternStr.startswith("{{")) {
+    if (PatternStr.starts_with("{{")) {
       // This is the start of a regex match.  Scan for the }}.
       size_t End = PatternStr.find("}}");
       if (End == StringRef::npos) {
@@ -857,7 +857,7 @@ bool Pattern::parsePattern(StringRef PatternStr, StringRef Prefix,
     // names must satisfy the regular expression "[a-zA-Z_][0-9a-zA-Z_]*" to be
     // valid, as this helps catch some common errors. If there are extra '['s
     // before the "[[", treat them literally.
-    if (PatternStr.startswith("[[") && !PatternStr.startswith("[[[")) {
+    if (PatternStr.starts_with("[[") && !PatternStr.starts_with("[[[")) {
       StringRef UnparsedPatternStr = PatternStr.substr(2);
       // Find the closing bracket pair ending the match.  End is going to be an
       // offset relative to the beginning of the match string.
@@ -1392,7 +1392,7 @@ size_t Pattern::FindRegexVarEnd(StringRef Str, SourceMgr &SM) {
   size_t BracketDepth = 0;
 
   while (!Str.empty()) {
-    if (Str.startswith("]]") && BracketDepth == 0)
+    if (Str.starts_with("]]") && BracketDepth == 0)
       return Offset;
     if (Str[0] == '\\') {
       // Backslash escapes the next char within regexes, so skip them both.
@@ -1591,10 +1591,10 @@ FindCheckType(const FileCheckRequest &Req, StringRef Buffer, StringRef Prefix,
   }
 
   // You can't combine -NOT with another suffix.
-  if (Rest.startswith("DAG-NOT:") || Rest.startswith("NOT-DAG:") ||
-      Rest.startswith("NEXT-NOT:") || Rest.startswith("NOT-NEXT:") ||
-      Rest.startswith("SAME-NOT:") || Rest.startswith("NOT-SAME:") ||
-      Rest.startswith("EMPTY-NOT:") || Rest.startswith("NOT-EMPTY:"))
+  if (Rest.starts_with("DAG-NOT:") || Rest.starts_with("NOT-DAG:") ||
+      Rest.starts_with("NEXT-NOT:") || Rest.starts_with("NOT-NEXT:") ||
+      Rest.starts_with("SAME-NOT:") || Rest.starts_with("NOT-SAME:") ||
+      Rest.starts_with("EMPTY-NOT:") || Rest.starts_with("NOT-EMPTY:"))
     return {Check::CheckBadNot, Rest};
 
   if (Rest.consume_front("NEXT"))
diff --git a/llvm/lib/FuzzMutate/FuzzerCLI.cpp b/llvm/lib/FuzzMutate/FuzzerCLI.cpp
index 0e47e3cc3af2..c64e9c04e199 100644
--- a/llvm/lib/FuzzMutate/FuzzerCLI.cpp
+++ b/llvm/lib/FuzzMutate/FuzzerCLI.cpp
@@ -43,7 +43,7 @@ void llvm::handleExecNameEncodedBEOpts(StringRef ExecName) {
       Args.push_back("-global-isel");
       // For now we default GlobalISel to -O0
       Args.push_back("-O0");
-    } else if (Opt.startswith("O")) {
+    } else if (Opt.starts_with("O")) {
       Args.push_back("-" + Opt.str());
     } else if (Triple(Opt).getArch()) {
       Args.push_back("-mtriple=" + Opt.str());
@@ -140,7 +140,7 @@ int llvm::runFuzzerOnInputs(int ArgC, char *ArgV[], FuzzerTestFun TestOne,
 
   for (int I = 1; I < ArgC; ++I) {
     StringRef Arg(ArgV[I]);
-    if (Arg.startswith("-")) {
+    if (Arg.starts_with("-")) {
       if (Arg.equals("-ignore_remaining_args=1"))
         break;
       continue;
diff --git a/llvm/lib/IR/AutoUpgrade.cpp b/llvm/lib/IR/AutoUpgrade.cpp
index 645691f44179..eeac80c013a1 100644
--- a/llvm/lib/IR/AutoUpgrade.cpp
+++ b/llvm/lib/IR/AutoUpgrade.cpp
@@ -582,7 +582,7 @@ static bool UpgradeX86IntrinsicFunction(Function *F, StringRef Name,
 
   if (Name.consume_front("xop.")) {
     Intrinsic::ID ID = Intrinsic::not_intrinsic;
-    if (Name.startswith("vpermil2")) { // Added in 3.9
+    if (Name.starts_with("vpermil2")) { // Added in 3.9
       // Upgrade any XOP PERMIL2 index operand still using a float/double
       // vector.
       auto Idx = F->getFunctionType()->getParamType(2);
diff --git a/llvm/lib/IR/DebugInfo.cpp b/llvm/lib/IR/DebugInfo.cpp
index 3fe940e19295..d532aead90be 100644
--- a/llvm/lib/IR/DebugInfo.cpp
+++ b/llvm/lib/IR/DebugInfo.cpp
@@ -559,7 +559,7 @@ bool llvm::StripDebugInfo(Module &M) {
   for (NamedMDNode &NMD : llvm::make_early_inc_range(M.named_metadata())) {
     // We're stripping debug info, and without them, coverage information
     // doesn't quite make sense.
-    if (NMD.getName().startswith("llvm.dbg.") ||
+    if (NMD.getName().starts_with("llvm.dbg.") ||
         NMD.getName() == "llvm.gcov") {
       NMD.eraseFromParent();
       Changed = true;
diff --git a/llvm/lib/IR/Function.cpp b/llvm/lib/IR/Function.cpp
index c3706dc1b02f..22e2455462bf 100644
--- a/llvm/lib/IR/Function.cpp
+++ b/llvm/lib/IR/Function.cpp
@@ -439,7 +439,7 @@ Function::Function(FunctionType *Ty, LinkageTypes Linkage, unsigned AddrSpace,
   if (ParentModule)
     ParentModule->getFunctionList().push_back(this);
 
-  HasLLVMReservedName = getName().startswith("llvm.");
+  HasLLVMReservedName = getName().starts_with("llvm.");
   // Ensure intrinsics have the right parameter attributes.
   // Note, the IntID field will have been set in Value::setName if this function
   // name is a valid intrinsic ID.
@@ -876,7 +876,7 @@ bool Function::isTargetIntrinsic() const {
 ///
 /// Returns the relevant slice of \c IntrinsicNameTable
 static ArrayRef<const char *> findTargetSubtable(StringRef Name) {
-  assert(Name.startswith("llvm."));
+  assert(Name.starts_with("llvm."));
 
   ArrayRef<IntrinsicTargetInfo> Targets(TargetInfos);
   // Drop "llvm." and take the first dotted component. That will be the target
@@ -915,7 +915,7 @@ Intrinsic::ID Function::lookupIntrinsicID(StringRef Name) {
 void Function::updateAfterNameChange() {
   LibFuncCache = UnknownLibFunc;
   StringRef Name = getName();
-  if (!Name.startswith("llvm.")) {
+  if (!Name.starts_with("llvm.")) {
     HasLLVMReservedName = false;
     IntID = Intrinsic::not_intrinsic;
     return;
diff --git a/llvm/lib/IR/Mangler.cpp b/llvm/lib/IR/Mangler.cpp
index 8d9880ecba58..3acac2c3e3db 100644
--- a/llvm/lib/IR/Mangler.cpp
+++ b/llvm/lib/IR/Mangler.cpp
@@ -149,8 +149,8 @@ void Mangler::getNameWithPrefix(raw_ostream &OS, const GlobalValue *GV,
 
   // Don't add byte count suffixes when '\01' or '?' are in the first
   // character.
-  if (Name.startswith("\01") ||
-      (DL.doNotMangleLeadingQuestionMark() && Name.startswith("?")))
+  if (Name.starts_with("\01") ||
+      (DL.doNotMangleLeadingQuestionMark() && Name.starts_with("?")))
     MSFunc = nullptr;
 
   CallingConv::ID CC =
diff --git a/llvm/lib/IR/PassInstrumentation.cpp b/llvm/lib/IR/PassInstrumentation.cpp
index d85cefbbe6f7..6d5f3acb7a4d 100644
--- a/llvm/lib/IR/PassInstrumentation.cpp
+++ b/llvm/lib/IR/PassInstrumentation.cpp
@@ -35,7 +35,8 @@ bool isSpecialPass(StringRef PassID, const std::vector<StringRef> &Specials) {
   StringRef Prefix = PassID;
   if (Pos != StringRef::npos)
     Prefix = PassID.substr(0, Pos);
-  return any_of(Specials, [Prefix](StringRef S) { return Prefix.endswith(S); });
+  return any_of(Specials,
+                [Prefix](StringRef S) { return Prefix.ends_with(S); });
 }
 
 } // namespace llvm
diff --git a/llvm/lib/IR/Type.cpp b/llvm/lib/IR/Type.cpp
index a185ca3fb8dc..85d779c98a9b 100644
--- a/llvm/lib/IR/Type.cpp
+++ b/llvm/lib/IR/Type.cpp
@@ -834,7 +834,7 @@ struct TargetTypeInfo {
 static TargetTypeInfo getTargetTypeInfo(const TargetExtType *Ty) {
   LLVMContext &C = Ty->getContext();
   StringRef Name = Ty->getName();
-  if (Name.startswith("spirv."))
+  if (Name.starts_with("spirv."))
     return TargetTypeInfo(PointerType::get(C, 0), TargetExtType::HasZeroInit,
                           TargetExtType::CanBeGlobal);
 
diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index c87f164bdd0f..cdc556ba7df8 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -958,7 +958,7 @@ void Verifier::visitGlobalIFunc(const GlobalIFunc &GI) {
 void Verifier::visitNamedMDNode(const NamedMDNode &NMD) {
   // There used to be various other llvm.dbg.* nodes, but we don't support
   // upgrading them and we want to reserve the namespace for future uses.
-  if (NMD.getName().startswith("llvm.dbg."))
+  if (NMD.getName().starts_with("llvm.dbg."))
     CheckDI(NMD.getName() == "llvm.dbg.cu",
             "unrecognized named metadata node in the llvm.dbg namespace", &NMD);
   for (const MDNode *MD : NMD.operands()) {
diff --git a/llvm/lib/InterfaceStub/IFSHandler.cpp b/llvm/lib/InterfaceStub/IFSHandler.cpp
index aa5817dceed5..da46592bd381 100644
--- a/llvm/lib/InterfaceStub/IFSHandler.cpp
+++ b/llvm/lib/InterfaceStub/IFSHandler.cpp
@@ -167,7 +167,7 @@ template <> struct MappingTraits<IFSStubTriple> {
 bool usesTriple(StringRef Buf) {
   for (line_iterator I(MemoryBufferRef(Buf, "ELFStub")); !I.is_at_eof(); ++I) {
     StringRef Line = (*I).trim();
-    if (Line.startswith("Target:")) {
+    if (Line.starts_with("Target:")) {
       if (Line == "Target:" || Line.contains("{")) {
         return false;
       }
diff --git a/llvm/lib/LTO/LTOModule.cpp b/llvm/lib/LTO/LTOModule.cpp
index 868169e78225..f839fe944e18 100644
--- a/llvm/lib/LTO/LTOModule.cpp
+++ b/llvm/lib/LTO/LTOModule.cpp
@@ -91,7 +91,7 @@ bool LTOModule::isBitcodeForTarget(MemoryBuffer *Buffer,
       expectedToErrorOrAndEmitErrors(Context, getBitcodeTargetTriple(*BCOrErr));
   if (!TripleOrErr)
     return false;
-  return StringRef(*TripleOrErr).startswith(TriplePrefix);
+  return StringRef(*TripleOrErr).starts_with(TriplePrefix);
 }
 
 std::string LTOModule::getProducerString(MemoryBuffer *Buffer) {
@@ -382,17 +382,17 @@ void LTOModule::addDefinedDataSymbol(StringRef Name, const GlobalValue *v) {
   // special case if this data blob is an ObjC class definition
   if (const GlobalVariable *GV = dyn_cast<GlobalVariable>(v)) {
     StringRef Section = GV->getSection();
-    if (Section.startswith("__OBJC,__class,")) {
+    if (Section.starts_with("__OBJC,__class,")) {
       addObjCClass(GV);
     }
 
     // special case if this data blob is an ObjC category definition
-    else if (Section.startswith("__OBJC,__category,")) {
+    else if (Section.starts_with("__OBJC,__category,")) {
       addObjCCategory(GV);
     }
 
     // special case if this data blob is the list of referenced classes
-    else if (Section.startswith("__OBJC,__cls_refs,")) {
+    else if (Section.starts_with("__OBJC,__cls_refs,")) {
       addObjCClassRef(GV);
     }
   }
diff --git a/llvm/lib/Linker/IRMover.cpp b/llvm/lib/Linker/IRMover.cpp
index 5d8fae28bf40..1bd562d1e8ae 100644
--- a/llvm/lib/Linker/IRMover.cpp
+++ b/llvm/lib/Linker/IRMover.cpp
@@ -1569,7 +1569,7 @@ Error IRLinker::run() {
     std::string ModuleId = SrcM->getModuleIdentifier();
     StringRef FileName = llvm::sys::path::filename(ModuleId);
     bool SrcIsLibDevice =
-        FileName.startswith("libdevice") && FileName.endswith(".10.bc");
+        FileName.starts_with("libdevice") && FileName.ends_with(".10.bc");
     bool SrcHasLibDeviceDL =
         (SrcM->getDataLayoutStr().empty() ||
          SrcM->getDataLayoutStr() == "e-i64:64-v16:16-v32:32-n16:32:64");
diff --git a/llvm/lib/MC/ELFObjectWriter.cpp b/llvm/lib/MC/ELFObjectWriter.cpp
index e4d18d8a7dd5..cb8af1aa9955 100644
--- a/llvm/lib/MC/ELFObjectWriter.cpp
+++ b/llvm/lib/MC/ELFObjectWriter.cpp
@@ -72,7 +72,7 @@ class ELFObjectWriter;
 struct ELFWriter;
 
 bool isDwoSection(const MCSectionELF &Sec) {
-  return Sec.getName().endswith(".dwo");
+  return Sec.getName().ends_with(".dwo");
 }
 
 class SymbolTableWriter {
@@ -872,7 +872,7 @@ void ELFWriter::writeSectionData(const MCAssembler &Asm, MCSection &Sec,
 
   const DebugCompressionType CompressionType = MAI->compressDebugSections();
   if (CompressionType == DebugCompressionType::None ||
-      !SectionName.startswith(".debug_")) {
+      !SectionName.starts_with(".debug_")) {
     Asm.writeSectionData(W.OS, &Section, Layout);
     return;
   }
@@ -1250,7 +1250,7 @@ void ELFObjectWriter::executePostLayoutBinding(MCAssembler &Asm,
     StringRef Prefix = AliasName.substr(0, Pos);
     StringRef Rest = AliasName.substr(Pos);
     StringRef Tail = Rest;
-    if (Rest.startswith("@@@"))
+    if (Rest.starts_with("@@@"))
       Tail = Rest.substr(Symbol.isUndefined() ? 2 : 1);
 
     auto *Alias =
@@ -1268,8 +1268,8 @@ void ELFObjectWriter::executePostLayoutBinding(MCAssembler &Asm,
     if (!Symbol.isUndefined() && S.KeepOriginalSym)
       continue;
 
-    if (Symbol.isUndefined() && Rest.startswith("@@") &&
-        !Rest.startswith("@@@")) {
+    if (Symbol.isUndefined() && Rest.starts_with("@@") &&
+        !Rest.starts_with("@@@")) {
       Asm.getContext().reportError(S.Loc, "default version symbol " +
                                               AliasName + " must be defined");
       continue;
@@ -1287,7 +1287,7 @@ void ELFObjectWriter::executePostLayoutBinding(MCAssembler &Asm,
   for (const MCSymbol *&Sym : AddrsigSyms) {
     if (const MCSymbol *R = Renames.lookup(cast<MCSymbolELF>(Sym)))
       Sym = R;
-    if (Sym->isInSection() && Sym->getName().startswith(".L"))
+    if (Sym->isInSection() && Sym->getName().starts_with(".L"))
       Sym = Sym->getSection().getBeginSymbol();
     Sym->setUsedInReloc();
   }
diff --git a/llvm/lib/MC/MCAsmStreamer.cpp b/llvm/lib/MC/MCAsmStreamer.cpp
index 5a157fc36d8e..9e1d108ac14d 100644
--- a/llvm/lib/MC/MCAsmStreamer.cpp
+++ b/llvm/lib/MC/MCAsmStreamer.cpp
@@ -467,12 +467,12 @@ void MCAsmStreamer::addExplicitComment(const Twine &T) {
   StringRef c = T.getSingleStringRef();
   if (c.equals(StringRef(MAI->getSeparatorString())))
     return;
-  if (c.startswith(StringRef("//"))) {
+  if (c.starts_with(StringRef("//"))) {
     ExplicitCommentToEmit.append("\t");
     ExplicitCommentToEmit.append(MAI->getCommentString());
     // drop //
     ExplicitCommentToEmit.append(c.slice(2, c.size()).str());
-  } else if (c.startswith(StringRef("/*"))) {
+  } else if (c.starts_with(StringRef("/*"))) {
     size_t p = 2, len = c.size() - 2;
     // emit each line in comment as separate newline.
     do {
@@ -485,7 +485,7 @@ void MCAsmStreamer::addExplicitComment(const Twine &T) {
         ExplicitCommentToEmit.append("\n");
       p = newp + 1;
     } while (p < len);
-  } else if (c.startswith(StringRef(MAI->getCommentString()))) {
+  } else if (c.starts_with(StringRef(MAI->getCommentString()))) {
     ExplicitCommentToEmit.append("\t");
     ExplicitCommentToEmit.append(c.str());
   } else if (c.front() == '#') {
diff --git a/llvm/lib/MC/MCContext.cpp b/llvm/lib/MC/MCContext.cpp
index ba4e1c3c4107..6e72b5062a1d 100644
--- a/llvm/lib/MC/MCContext.cpp
+++ b/llvm/lib/MC/MCContext.cpp
@@ -271,7 +271,7 @@ MCSymbol *MCContext::createSymbol(StringRef Name, bool AlwaysAddSuffix,
   // label, if used.
   bool IsTemporary = CanBeUnnamed;
   if (AllowTemporaryLabels && !IsTemporary)
-    IsTemporary = Name.startswith(MAI->getPrivateGlobalPrefix());
+    IsTemporary = Name.starts_with(MAI->getPrivateGlobalPrefix());
 
   SmallString<128> NewName = Name;
   bool AddSuffix = AlwaysAddSuffix;
@@ -382,8 +382,8 @@ MCContext::createXCOFFSymbolImpl(const StringMapEntry<bool> *Name,
     return new (nullptr, *this) MCSymbolXCOFF(nullptr, IsTemporary);
 
   StringRef OriginalName = Name->first();
-  if (OriginalName.startswith("._Renamed..") ||
-      OriginalName.startswith("_Renamed.."))
+  if (OriginalName.starts_with("._Renamed..") ||
+      OriginalName.starts_with("_Renamed.."))
     reportError(SMLoc(), "invalid symbol name from source");
 
   if (MAI->isValidUnquotedName(OriginalName))
@@ -628,8 +628,8 @@ void MCContext::recordELFMergeableSectionInfo(StringRef SectionName,
 }
 
 bool MCContext::isELFImplicitMergeableSectionNamePrefix(StringRef SectionName) {
-  return SectionName.startswith(".rodata.str") ||
-         SectionName.startswith(".rodata.cst");
+  return SectionName.starts_with(".rodata.str") ||
+         SectionName.starts_with(".rodata.cst");
 }
 
 bool MCContext::isELFGenericMergeableSection(StringRef SectionName) {
diff --git a/llvm/lib/MC/MCDwarf.cpp b/llvm/lib/MC/MCDwarf.cpp
index f94fc48a033d..d0face9140de 100644
--- a/llvm/lib/MC/MCDwarf.cpp
+++ b/llvm/lib/MC/MCDwarf.cpp
@@ -1211,7 +1211,7 @@ void MCGenDwarfLabelEntry::Make(MCSymbol *Symbol, MCStreamer *MCOS,
   // The dwarf label's name does not have the symbol name's leading
   // underbar if any.
   StringRef Name = Symbol->getName();
-  if (Name.startswith("_"))
+  if (Name.starts_with("_"))
     Name = Name.substr(1, Name.size()-1);
 
   // Get the dwarf file number to be used for the dwarf label.
diff --git a/llvm/lib/MC/MCParser/AsmLexer.cpp b/llvm/lib/MC/MCParser/AsmLexer.cpp
index f13549b24e2d..e08404ae0ad9 100644
--- a/llvm/lib/MC/MCParser/AsmLexer.cpp
+++ b/llvm/lib/MC/MCParser/AsmLexer.cpp
@@ -32,7 +32,7 @@
 using namespace llvm;
 
 AsmLexer::AsmLexer(const MCAsmInfo &MAI) : MAI(MAI) {
-  AllowAtInIdentifier = !StringRef(MAI.getCommentString()).startswith("@");
+  AllowAtInIdentifier = !StringRef(MAI.getCommentString()).starts_with("@");
   LexMotorolaIntegers = MAI.shouldUseMotorolaIntegers();
 }
 
@@ -605,7 +605,7 @@ AsmToken AsmLexer::LexSingleQuote() {
   StringRef Res = StringRef(TokStart,CurPtr - TokStart);
   long long Value;
 
-  if (Res.startswith("\'\\")) {
+  if (Res.starts_with("\'\\")) {
     char theChar = Res[2];
     switch (theChar) {
       default: Value = theChar; break;
diff --git a/llvm/lib/MC/MCParser/AsmParser.cpp b/llvm/lib/MC/MCParser/AsmParser.cpp
index 825b12e037d3..8e508dbdb1c6 100644
--- a/llvm/lib/MC/MCParser/AsmParser.cpp
+++ b/llvm/lib/MC/MCParser/AsmParser.cpp
@@ -1991,7 +1991,7 @@ bool AsmParser::parseStatement(ParseStatementInfo &Info,
   // Otherwise, we have a normal instruction or directive.
 
   // Directives start with "."
-  if (IDVal.startswith(".") && IDVal != ".") {
+  if (IDVal.starts_with(".") && IDVal != ".") {
     // There are several entities interested in parsing directives:
     //
     // 1. The target-specific assembly parser. Some directives are target
diff --git a/llvm/lib/MC/MCParser/COFFMasmParser.cpp b/llvm/lib/MC/MCParser/COFFMasmParser.cpp
index 34aa5bf2ae39..8adb0dcddb16 100644
--- a/llvm/lib/MC/MCParser/COFFMasmParser.cpp
+++ b/llvm/lib/MC/MCParser/COFFMasmParser.cpp
@@ -250,7 +250,7 @@ bool COFFMasmParser::ParseDirectiveSegment(StringRef Directive, SMLoc Loc) {
   SmallVector<char, 247> SectionNameVector;
 
   StringRef Class;
-  if (SegmentName == "_TEXT" || SegmentName.startswith("_TEXT$")) {
+  if (SegmentName == "_TEXT" || SegmentName.starts_with("_TEXT$")) {
     if (SegmentName.size() == 5) {
       SectionName = ".text";
     } else {
diff --git a/llvm/lib/MC/MCParser/ELFAsmParser.cpp b/llvm/lib/MC/MCParser/ELFAsmParser.cpp
index dbfe0d83e1b2..93e1d2f44b8c 100644
--- a/llvm/lib/MC/MCParser/ELFAsmParser.cpp
+++ b/llvm/lib/MC/MCParser/ELFAsmParser.cpp
@@ -531,7 +531,7 @@ static bool allowSectionTypeMismatch(const Triple &TT, StringRef SectionName,
     // MIPS .debug_* sections should have SHT_MIPS_DWARF section type to
     // distinguish among sections contain DWARF and ECOFF debug formats,
     // but in assembly files these sections have SHT_PROGBITS type.
-    return SectionName.startswith(".debug_") && Type == ELF::SHT_PROGBITS;
+    return SectionName.starts_with(".debug_") && Type == ELF::SHT_PROGBITS;
   }
   return false;
 }
@@ -634,7 +634,7 @@ EndStmt:
   unsigned Type = ELF::SHT_PROGBITS;
 
   if (TypeName.empty()) {
-    if (SectionName.startswith(".note"))
+    if (SectionName.starts_with(".note"))
       Type = ELF::SHT_NOTE;
     else if (hasPrefix(SectionName, ".init_array"))
       Type = ELF::SHT_INIT_ARRAY;
diff --git a/llvm/lib/MC/MCParser/MasmParser.cpp b/llvm/lib/MC/MCParser/MasmParser.cpp
index 8960e739365c..51563ea86a6c 100644
--- a/llvm/lib/MC/MCParser/MasmParser.cpp
+++ b/llvm/lib/MC/MCParser/MasmParser.cpp
@@ -2117,7 +2117,7 @@ bool MasmParser::parseStatement(ParseStatementInfo &Info,
     // Treat ".<number>" as a valid identifier in this context.
     IDVal = getTok().getString();
     Lex(); // always eat a token
-    if (!IDVal.startswith("."))
+    if (!IDVal.starts_with("."))
       return Error(IDLoc, "unexpected token at start of statement");
   } else if (parseIdentifier(IDVal, StartOfStatement)) {
     if (!TheCondState.Ignore) {
@@ -7190,7 +7190,7 @@ bool MasmParser::parseDirectiveRadix(SMLoc DirectiveLoc) {
 bool MasmParser::parseDirectiveEcho(SMLoc DirectiveLoc) {
   std::string Message = parseStringTo(AsmToken::EndOfStatement);
   llvm::outs() << Message;
-  if (!StringRef(Message).endswith("\n"))
+  if (!StringRef(Message).ends_with("\n"))
     llvm::outs() << '\n';
   return false;
 }
diff --git a/llvm/lib/MC/StringTableBuilder.cpp b/llvm/lib/MC/StringTableBuilder.cpp
index 0e4f72e13615..df316bae98ce 100644
--- a/llvm/lib/MC/StringTableBuilder.cpp
+++ b/llvm/lib/MC/StringTableBuilder.cpp
@@ -150,7 +150,7 @@ void StringTableBuilder::finalizeStringTable(bool Optimize) {
     StringRef Previous;
     for (StringPair *P : Strings) {
       StringRef S = P->first.val();
-      if (Previous.endswith(S)) {
+      if (Previous.ends_with(S)) {
         size_t Pos = Size - S.size() - (K != RAW);
         if (isAligned(Alignment, Pos)) {
           P->second = Pos;
diff --git a/llvm/lib/MC/WasmObjectWriter.cpp b/llvm/lib/MC/WasmObjectWriter.cpp
index b99df3837cc2..fd48d5080ff6 100644
--- a/llvm/lib/MC/WasmObjectWriter.cpp
+++ b/llvm/lib/MC/WasmObjectWriter.cpp
@@ -193,7 +193,7 @@ static void patchI64(raw_pwrite_stream &Stream, uint64_t Value,
 }
 
 bool isDwoSection(const MCSection &Sec) {
-  return Sec.getName().endswith(".dwo");
+  return Sec.getName().ends_with(".dwo");
 }
 
 class WasmObjectWriter : public MCObjectWriter {
@@ -529,7 +529,7 @@ void WasmObjectWriter::recordRelocation(MCAssembler &Asm,
   const auto *SymA = cast<MCSymbolWasm>(&RefA->getSymbol());
 
   // The .init_array isn't translated as data, so don't do relocations in it.
-  if (FixupSection.getName().startswith(".init_array")) {
+  if (FixupSection.getName().starts_with(".init_array")) {
     SymA->setUsedInInitArray();
     return;
   }
@@ -1491,7 +1491,7 @@ uint64_t WasmObjectWriter::writeOneObject(MCAssembler &Asm,
                       << Section.getGroup() << "\n";);
 
     // .init_array sections are handled specially elsewhere.
-    if (SectionName.startswith(".init_array"))
+    if (SectionName.starts_with(".init_array"))
       continue;
 
     // Code is handled separately
@@ -1526,7 +1526,7 @@ uint64_t WasmObjectWriter::writeOneObject(MCAssembler &Asm,
       StringRef Name = SectionName;
 
       // For user-defined custom sections, strip the prefix
-      if (Name.startswith(".custom_section."))
+      if (Name.starts_with(".custom_section."))
         Name = Name.substr(strlen(".custom_section."));
 
       MCSymbol *Begin = Sec.getBeginSymbol();
@@ -1851,9 +1851,9 @@ uint64_t WasmObjectWriter::writeOneObject(MCAssembler &Asm,
   // Translate .init_array section contents into start functions.
   for (const MCSection &S : Asm) {
     const auto &WS = static_cast<const MCSectionWasm &>(S);
-    if (WS.getName().startswith(".fini_array"))
+    if (WS.getName().starts_with(".fini_array"))
       report_fatal_error(".fini_array sections are unsupported");
-    if (!WS.getName().startswith(".init_array"))
+    if (!WS.getName().starts_with(".init_array"))
       continue;
     if (WS.getFragmentList().empty())
       continue;
diff --git a/llvm/lib/MC/WinCOFFObjectWriter.cpp b/llvm/lib/MC/WinCOFFObjectWriter.cpp
index 1f73cb9884e0..f265fafa59e7 100644
--- a/llvm/lib/MC/WinCOFFObjectWriter.cpp
+++ b/llvm/lib/MC/WinCOFFObjectWriter.cpp
@@ -241,7 +241,7 @@ public:
 } // end anonymous namespace
 
 static bool isDwoSection(const MCSection &Sec) {
-  return Sec.getName().endswith(".dwo");
+  return Sec.getName().ends_with(".dwo");
 }
 
 //------------------------------------------------------------------------------
diff --git a/llvm/lib/ObjCopy/COFF/COFFObjcopy.cpp b/llvm/lib/ObjCopy/COFF/COFFObjcopy.cpp
index 622726be8ce5..782d5b2f70c3 100644
--- a/llvm/lib/ObjCopy/COFF/COFFObjcopy.cpp
+++ b/llvm/lib/ObjCopy/COFF/COFFObjcopy.cpp
@@ -29,7 +29,7 @@ using namespace object;
 using namespace COFF;
 
 static bool isDebugSection(const Section &Sec) {
-  return Sec.Name.startswith(".debug");
+  return Sec.Name.starts_with(".debug");
 }
 
 static uint64_t getNextRVA(const Object &Obj) {
diff --git a/llvm/lib/ObjCopy/ELF/ELFObjcopy.cpp b/llvm/lib/ObjCopy/ELF/ELFObjcopy.cpp
index 9d02ba051a0a..ceb676dec22f 100644
--- a/llvm/lib/ObjCopy/ELF/ELFObjcopy.cpp
+++ b/llvm/lib/ObjCopy/ELF/ELFObjcopy.cpp
@@ -52,11 +52,11 @@ using namespace llvm::object;
 using SectionPred = std::function<bool(const SectionBase &Sec)>;
 
 static bool isDebugSection(const SectionBase &Sec) {
-  return StringRef(Sec.Name).startswith(".debug") || Sec.Name == ".gdb_index";
+  return StringRef(Sec.Name).starts_with(".debug") || Sec.Name == ".gdb_index";
 }
 
 static bool isDWOSection(const SectionBase &Sec) {
-  return StringRef(Sec.Name).endswith(".dwo");
+  return StringRef(Sec.Name).ends_with(".dwo");
 }
 
 static bool onlyKeepDWOPred(const Object &Obj, const SectionBase &Sec) {
@@ -214,7 +214,7 @@ static Error dumpSectionToFile(StringRef SecName, StringRef Filename,
 
 static bool isCompressable(const SectionBase &Sec) {
   return !(Sec.Flags & ELF::SHF_COMPRESSED) &&
-         StringRef(Sec.Name).startswith(".debug");
+         StringRef(Sec.Name).starts_with(".debug");
 }
 
 static Error replaceDebugSections(
@@ -248,7 +248,7 @@ static bool isAArch64MappingSymbol(const Symbol &Sym) {
   StringRef Name = Sym.Name;
   if (!Name.consume_front("$x") && !Name.consume_front("$d"))
     return false;
-  return Name.empty() || Name.startswith(".");
+  return Name.empty() || Name.starts_with(".");
 }
 
 static bool isArmMappingSymbol(const Symbol &Sym) {
@@ -259,7 +259,7 @@ static bool isArmMappingSymbol(const Symbol &Sym) {
   if (!Name.consume_front("$a") && !Name.consume_front("$d") &&
       !Name.consume_front("$t"))
     return false;
-  return Name.empty() || Name.startswith(".");
+  return Name.empty() || Name.starts_with(".");
 }
 
 // Check if the symbol should be preserved because it is required by ABI.
@@ -361,7 +361,7 @@ static Error updateAndRemoveSymbols(const CommonConfig &Config,
 
     if ((Config.DiscardMode == DiscardType::All ||
          (Config.DiscardMode == DiscardType::Locals &&
-          StringRef(Sym.Name).startswith(".L"))) &&
+          StringRef(Sym.Name).starts_with(".L"))) &&
         Sym.Binding == STB_LOCAL && Sym.getShndx() != SHN_UNDEF &&
         Sym.Type != STT_FILE && Sym.Type != STT_SECTION)
       return true;
@@ -448,7 +448,7 @@ static Error replaceAndRemoveSections(const CommonConfig &Config,
         return true;
       if (&Sec == Obj.SectionNames)
         return false;
-      if (StringRef(Sec.Name).startswith(".gnu.warning"))
+      if (StringRef(Sec.Name).starts_with(".gnu.warning"))
         return false;
       // We keep the .ARM.attribute section to maintain compatibility
       // with Debian derived distributions. This is a bug in their
@@ -662,7 +662,7 @@ static Error handleArgs(const CommonConfig &Config, const ELFConfig &ELFConfig,
     auto AddSection = [&](StringRef Name, ArrayRef<uint8_t> Data) {
       OwnedDataSection &NewSection =
           Obj.addSection<OwnedDataSection>(Name, Data);
-      if (Name.startswith(".note") && Name != ".note.GNU-stack")
+      if (Name.starts_with(".note") && Name != ".note.GNU-stack")
         NewSection.Type = SHT_NOTE;
       return Error::success();
     };
diff --git a/llvm/lib/ObjCopy/MachO/MachOObject.h b/llvm/lib/ObjCopy/MachO/MachOObject.h
index 1cbd2eb5f320..b3303fd291c8 100644
--- a/llvm/lib/ObjCopy/MachO/MachOObject.h
+++ b/llvm/lib/ObjCopy/MachO/MachOObject.h
@@ -119,8 +119,8 @@ struct SymbolEntry {
   }
 
   bool isSwiftSymbol() const {
-    return StringRef(Name).startswith("_$s") ||
-           StringRef(Name).startswith("_$S");
+    return StringRef(Name).starts_with("_$s") ||
+           StringRef(Name).starts_with("_$S");
   }
 
   std::optional<uint32_t> section() const {
diff --git a/llvm/lib/ObjCopy/wasm/WasmObjcopy.cpp b/llvm/lib/ObjCopy/wasm/WasmObjcopy.cpp
index e5af59f93280..5bba1dea9adf 100644
--- a/llvm/lib/ObjCopy/wasm/WasmObjcopy.cpp
+++ b/llvm/lib/ObjCopy/wasm/WasmObjcopy.cpp
@@ -22,11 +22,11 @@ using namespace object;
 using SectionPred = std::function<bool(const Section &Sec)>;
 
 static bool isDebugSection(const Section &Sec) {
-  return Sec.Name.startswith(".debug");
+  return Sec.Name.starts_with(".debug");
 }
 
 static bool isLinkerSection(const Section &Sec) {
-  return Sec.Name.startswith("reloc.") || Sec.Name == "linking";
+  return Sec.Name.starts_with("reloc.") || Sec.Name == "linking";
 }
 
 static bool isNameSection(const Section &Sec) { return Sec.Name == "name"; }
diff --git a/llvm/lib/Object/Archive.cpp b/llvm/lib/Object/Archive.cpp
index fdd87824e229..4ac4d727afb6 100644
--- a/llvm/lib/Object/Archive.cpp
+++ b/llvm/lib/Object/Archive.cpp
@@ -227,7 +227,7 @@ Expected<StringRef> BigArchiveMemberHeader::getRawName() const {
   StringRef NameTerminator = "`\n";
   StringRef NameStringWithNameTerminator =
       StringRef(ArMemHdr->Name, NameLenWithPadding + NameTerminator.size());
-  if (!NameStringWithNameTerminator.endswith(NameTerminator)) {
+  if (!NameStringWithNameTerminator.ends_with(NameTerminator)) {
     uint64_t Offset =
         reinterpret_cast<const char *>(ArMemHdr->Name + NameLenWithPadding) -
         Parent->getData().data();
@@ -315,7 +315,7 @@ Expected<StringRef> ArchiveMemberHeader::getName(uint64_t Size) const {
     return Parent->getStringTable().begin() + StringOffset;
   }
 
-  if (Name.startswith("#1/")) {
+  if (Name.starts_with("#1/")) {
     uint64_t NameLength;
     if (Name.substr(3).rtrim(' ').getAsInteger(10, NameLength)) {
       std::string Buf;
@@ -524,7 +524,7 @@ Archive::Child::Child(const Archive *Parent, const char *Start, Error *Err)
     // The actual start of the file is after the name and any necessary
     // even-alignment padding.
     StartOfFile += ((Name.size() + 1) >> 1) << 1;
-  } else if (Name.startswith("#1/")) {
+  } else if (Name.starts_with("#1/")) {
     uint64_t NameSize;
     StringRef RawNameSize = Name.substr(3).rtrim(' ');
     if (RawNameSize.getAsInteger(10, NameSize)) {
@@ -671,7 +671,7 @@ Expected<std::unique_ptr<Archive>> Archive::create(MemoryBufferRef Source) {
   std::unique_ptr<Archive> Ret;
   StringRef Buffer = Source.getBuffer();
 
-  if (Buffer.startswith(BigArchiveMagic))
+  if (Buffer.starts_with(BigArchiveMagic))
     Ret = std::make_unique<BigArchive>(Source, Err);
   else
     Ret = std::make_unique<Archive>(Source, Err);
@@ -711,11 +711,11 @@ Archive::Archive(MemoryBufferRef Source, Error &Err)
   ErrorAsOutParameter ErrAsOutParam(&Err);
   StringRef Buffer = Data.getBuffer();
   // Check for sufficient magic.
-  if (Buffer.startswith(ThinArchiveMagic)) {
+  if (Buffer.starts_with(ThinArchiveMagic)) {
     IsThin = true;
-  } else if (Buffer.startswith(ArchiveMagic)) {
+  } else if (Buffer.starts_with(ArchiveMagic)) {
     IsThin = false;
-  } else if (Buffer.startswith(BigArchiveMagic)) {
+  } else if (Buffer.starts_with(BigArchiveMagic)) {
     Format = K_AIXBIG;
     IsThin = false;
     return;
@@ -800,7 +800,7 @@ Archive::Archive(MemoryBufferRef Source, Error &Err)
     return;
   }
 
-  if (Name.startswith("#1/")) {
+  if (Name.starts_with("#1/")) {
     Format = K_BSD;
     // We know this is BSD, so getName will work since there is no string table.
     Expected<StringRef> NameOrErr = C->getName();
diff --git a/llvm/lib/Object/COFFImportFile.cpp b/llvm/lib/Object/COFFImportFile.cpp
index 2cca1f728cc7..eeb13ffe9c11 100644
--- a/llvm/lib/Object/COFFImportFile.cpp
+++ b/llvm/lib/Object/COFFImportFile.cpp
@@ -91,11 +91,11 @@ static ImportNameType getNameType(StringRef Sym, StringRef ExtName,
   // stdcall function still omits the underscore (IMPORT_NAME_NOPREFIX).
   // See the comment in isDecorated in COFFModuleDefinition.cpp for more
   // details.
-  if (ExtName.startswith("_") && ExtName.contains('@') && !MinGW)
+  if (ExtName.starts_with("_") && ExtName.contains('@') && !MinGW)
     return IMPORT_NAME;
   if (Sym != ExtName)
     return IMPORT_NAME_UNDECORATE;
-  if (Machine == IMAGE_FILE_MACHINE_I386 && Sym.startswith("_"))
+  if (Machine == IMAGE_FILE_MACHINE_I386 && Sym.starts_with("_"))
     return IMPORT_NAME_NOPREFIX;
   return IMPORT_NAME;
 }
@@ -105,7 +105,7 @@ static Expected<std::string> replace(StringRef S, StringRef From,
   size_t Pos = S.find(From);
 
   // From and To may be mangled, but substrings in S may not.
-  if (Pos == StringRef::npos && From.startswith("_") && To.startswith("_")) {
+  if (Pos == StringRef::npos && From.starts_with("_") && To.starts_with("_")) {
     From = From.substr(1);
     To = To.substr(1);
     Pos = S.find(From);
diff --git a/llvm/lib/Object/COFFModuleDefinition.cpp b/llvm/lib/Object/COFFModuleDefinition.cpp
index a33949733c8e..648f01f823d0 100644
--- a/llvm/lib/Object/COFFModuleDefinition.cpp
+++ b/llvm/lib/Object/COFFModuleDefinition.cpp
@@ -74,7 +74,7 @@ static bool isDecorated(StringRef Sym, bool MingwDef) {
   // We can't check for a leading underscore here, since function names
   // themselves can start with an underscore, while a second one still needs
   // to be added.
-  return Sym.startswith("@") || Sym.contains("@@") || Sym.startswith("?") ||
+  return Sym.starts_with("@") || Sym.contains("@@") || Sym.starts_with("?") ||
          (!MingwDef && Sym.contains('@'));
 }
 
@@ -97,7 +97,7 @@ public:
     }
     case '=':
       Buf = Buf.drop_front();
-      if (Buf.startswith("=")) {
+      if (Buf.starts_with("=")) {
         Buf = Buf.drop_front();
         return Token(EqualEqual, "==");
       }
diff --git a/llvm/lib/Object/COFFObjectFile.cpp b/llvm/lib/Object/COFFObjectFile.cpp
index 574f7a7cf1f4..8700912614db 100644
--- a/llvm/lib/Object/COFFObjectFile.cpp
+++ b/llvm/lib/Object/COFFObjectFile.cpp
@@ -336,7 +336,7 @@ bool COFFObjectFile::isDebugSection(DataRefImpl Ref) const {
     return false;
   }
   StringRef SectionName = SectionNameOrErr.get();
-  return SectionName.startswith(".debug");
+  return SectionName.starts_with(".debug");
 }
 
 unsigned COFFObjectFile::getSectionID(SectionRef Sec) const {
@@ -1203,9 +1203,9 @@ COFFObjectFile::getSectionName(const coff_section *Sec) const {
   StringRef Name = StringRef(Sec->Name, COFF::NameSize).split('\0').first;
 
   // Check for string table entry. First byte is '/'.
-  if (Name.startswith("/")) {
+  if (Name.starts_with("/")) {
     uint32_t Offset;
-    if (Name.startswith("//")) {
+    if (Name.starts_with("//")) {
       if (decodeBase64StringEntry(Name.substr(2), Offset))
         return createStringError(object_error::parse_failed,
                                  "invalid section name");
diff --git a/llvm/lib/Object/MachOObjectFile.cpp b/llvm/lib/Object/MachOObjectFile.cpp
index 5e6c6ea79427..1cfd0a069463 100644
--- a/llvm/lib/Object/MachOObjectFile.cpp
+++ b/llvm/lib/Object/MachOObjectFile.cpp
@@ -2066,9 +2066,9 @@ bool MachOObjectFile::isDebugSection(DataRefImpl Sec) const {
     return false;
   }
   StringRef SectionName = SectionNameOrErr.get();
-  return SectionName.startswith("__debug") ||
-         SectionName.startswith("__zdebug") ||
-         SectionName.startswith("__apple") || SectionName == "__gdb_index" ||
+  return SectionName.starts_with("__debug") ||
+         SectionName.starts_with("__zdebug") ||
+         SectionName.starts_with("__apple") || SectionName == "__gdb_index" ||
          SectionName == "__swift_ast";
 }
 
@@ -2083,7 +2083,7 @@ ArrayRef<uint8_t> getSegmentContents(const MachOObjectFile &Obj,
     return {};
   }
   auto &Segment = SegmentOrErr.get();
-  if (StringRef(Segment.segname, 16).startswith(SegmentName))
+  if (StringRef(Segment.segname, 16).starts_with(SegmentName))
     return arrayRefFromStringRef(Obj.getData().slice(
         Segment.fileoff, Segment.fileoff + Segment.filesize));
   return {};
@@ -2469,7 +2469,7 @@ StringRef MachOObjectFile::guessLibraryShortName(StringRef Name,
   if (c == Name.npos || c == 0)
     goto guess_library;
   V = Name.slice(c+1, Name.npos);
-  if (!V.startswith("Versions/"))
+  if (!V.starts_with("Versions/"))
     goto guess_library;
   d =  Name.rfind('/', c);
   if (d == Name.npos)
diff --git a/llvm/lib/Object/ModuleSymbolTable.cpp b/llvm/lib/Object/ModuleSymbolTable.cpp
index dc73937863e6..ab073e18cb46 100644
--- a/llvm/lib/Object/ModuleSymbolTable.cpp
+++ b/llvm/lib/Object/ModuleSymbolTable.cpp
@@ -215,7 +215,7 @@ uint32_t ModuleSymbolTable::getSymbolFlags(Symbol S) const {
       GV->hasExternalWeakLinkage())
     Res |= BasicSymbolRef::SF_Weak;
 
-  if (GV->getName().startswith("llvm."))
+  if (GV->getName().starts_with("llvm."))
     Res |= BasicSymbolRef::SF_FormatSpecific;
   else if (auto *Var = dyn_cast<GlobalVariable>(GV)) {
     if (Var->getSection() == "llvm.metadata")
diff --git a/llvm/lib/Object/RecordStreamer.cpp b/llvm/lib/Object/RecordStreamer.cpp
index d01076c0bceb..891016cf7475 100644
--- a/llvm/lib/Object/RecordStreamer.cpp
+++ b/llvm/lib/Object/RecordStreamer.cpp
@@ -206,7 +206,7 @@ void RecordStreamer::flushSymverDirectives() {
     for (auto AliasName : Symver.second) {
       std::pair<StringRef, StringRef> Split = AliasName.split("@@@");
       SmallString<128> NewName;
-      if (!Split.second.empty() && !Split.second.startswith("@")) {
+      if (!Split.second.empty() && !Split.second.starts_with("@")) {
         // Special processing for "@@@" according
         // https://sourceware.org/binutils/docs/as/Symver.html
         const char *Separator = IsDefined ? "@@" : "@";
diff --git a/llvm/lib/Object/WasmObjectFile.cpp b/llvm/lib/Object/WasmObjectFile.cpp
index 0982c7e2efbb..168fb57935d6 100644
--- a/llvm/lib/Object/WasmObjectFile.cpp
+++ b/llvm/lib/Object/WasmObjectFile.cpp
@@ -1092,7 +1092,7 @@ Error WasmObjectFile::parseCustomSection(WasmSection &Sec, ReadContext &Ctx) {
   } else if (Sec.Name == "target_features") {
     if (Error Err = parseTargetFeaturesSection(Ctx))
       return Err;
-  } else if (Sec.Name.startswith("reloc.")) {
+  } else if (Sec.Name.starts_with("reloc.")) {
     if (Error Err = parseRelocSection(Sec.Name, Ctx))
       return Err;
   }
diff --git a/llvm/lib/ObjectYAML/ELFEmitter.cpp b/llvm/lib/ObjectYAML/ELFEmitter.cpp
index 40f81f867efa..d54faec20866 100644
--- a/llvm/lib/ObjectYAML/ELFEmitter.cpp
+++ b/llvm/lib/ObjectYAML/ELFEmitter.cpp
@@ -666,7 +666,7 @@ bool ELFState<ELFT>::initImplicitHeader(ContiguousBlobAccumulator &CBA,
     initSymtabSectionHeader(Header, SymtabType::Static, CBA, YAMLSec);
   else if (SecName == ".dynsym")
     initSymtabSectionHeader(Header, SymtabType::Dynamic, CBA, YAMLSec);
-  else if (SecName.startswith(".debug_")) {
+  else if (SecName.starts_with(".debug_")) {
     // If a ".debug_*" section's type is a preserved one, e.g., SHT_DYNAMIC, we
     // will not treat it as a debug section.
     if (YAMLSec && !isa<ELFYAML::RawContentSection>(YAMLSec))
diff --git a/llvm/lib/ObjectYAML/ELFYAML.cpp b/llvm/lib/ObjectYAML/ELFYAML.cpp
index c47d4eaa309d..9d845a0c7c48 100644
--- a/llvm/lib/ObjectYAML/ELFYAML.cpp
+++ b/llvm/lib/ObjectYAML/ELFYAML.cpp
@@ -1291,10 +1291,10 @@ StringRef ScalarTraits<ELFYAML::YAMLIntUInt>::input(StringRef Scalar, void *Ctx,
   StringRef ErrMsg = "invalid number";
   // We do not accept negative hex numbers because their meaning is ambiguous.
   // For example, would -0xfffffffff mean 1 or INT32_MIN?
-  if (Scalar.empty() || Scalar.startswith("-0x"))
+  if (Scalar.empty() || Scalar.starts_with("-0x"))
     return ErrMsg;
 
-  if (Scalar.startswith("-")) {
+  if (Scalar.starts_with("-")) {
     const int64_t MinVal = Is64 ? INT64_MIN : INT32_MIN;
     long long Int;
     if (getAsSignedInteger(Scalar, /*Radix=*/0, Int) || (Int < MinVal))
@@ -1559,7 +1559,7 @@ void MappingTraits<std::unique_ptr<ELFYAML::Chunk>>::mapping(
     // When the Type string does not have a "SHT_" prefix, we know it is not a
     // description of a regular ELF output section.
     TypeStr = getStringValue(IO, "Type");
-    if (TypeStr.startswith("SHT_") || isInteger(TypeStr))
+    if (TypeStr.starts_with("SHT_") || isInteger(TypeStr))
       IO.mapRequired("Type", Type);
   }
 
diff --git a/llvm/lib/Option/ArgList.cpp b/llvm/lib/Option/ArgList.cpp
index 8f764ec779f3..72003e3a5259 100644
--- a/llvm/lib/Option/ArgList.cpp
+++ b/llvm/lib/Option/ArgList.cpp
@@ -185,8 +185,8 @@ const char *ArgList::GetOrMakeJoinedArgString(unsigned Index,
                                               StringRef LHS,
                                               StringRef RHS) const {
   StringRef Cur = getArgString(Index);
-  if (Cur.size() == LHS.size() + RHS.size() &&
-      Cur.startswith(LHS) && Cur.endswith(RHS))
+  if (Cur.size() == LHS.size() + RHS.size() && Cur.starts_with(LHS) &&
+      Cur.ends_with(RHS))
     return Cur.data();
 
   return MakeArgString(LHS + RHS);
diff --git a/llvm/lib/Option/OptTable.cpp b/llvm/lib/Option/OptTable.cpp
index 50eebf1f954b..a4d0f4a54937 100644
--- a/llvm/lib/Option/OptTable.cpp
+++ b/llvm/lib/Option/OptTable.cpp
@@ -152,7 +152,7 @@ static bool isInput(const ArrayRef<StringLiteral> &Prefixes, StringRef Arg) {
   if (Arg == "-")
     return true;
   for (const StringRef &Prefix : Prefixes)
-    if (Arg.startswith(Prefix))
+    if (Arg.starts_with(Prefix))
       return false;
   return true;
 }
@@ -161,10 +161,10 @@ static bool isInput(const ArrayRef<StringLiteral> &Prefixes, StringRef Arg) {
 static unsigned matchOption(const OptTable::Info *I, StringRef Str,
                             bool IgnoreCase) {
   for (auto Prefix : I->Prefixes) {
-    if (Str.startswith(Prefix)) {
+    if (Str.starts_with(Prefix)) {
       StringRef Rest = Str.substr(Prefix.size());
       bool Matched = IgnoreCase ? Rest.starts_with_insensitive(I->getName())
-                                : Rest.startswith(I->getName());
+                                : Rest.starts_with(I->getName());
       if (Matched)
         return Prefix.size() + StringRef(I->getName()).size();
     }
@@ -175,7 +175,7 @@ static unsigned matchOption(const OptTable::Info *I, StringRef Str,
 // Returns true if one of the Prefixes + In.Names matches Option
 static bool optionMatches(const OptTable::Info &In, StringRef Option) {
   for (auto Prefix : In.Prefixes)
-    if (Option.endswith(In.getName()))
+    if (Option.ends_with(In.getName()))
       if (Option.slice(0, Option.size() - In.getName().size()) == Prefix)
         return true;
   return false;
@@ -197,7 +197,7 @@ OptTable::suggestValueCompletions(StringRef Option, StringRef Arg) const {
 
     std::vector<std::string> Result;
     for (StringRef Val : Candidates)
-      if (Val.startswith(Arg) && Arg.compare(Val))
+      if (Val.starts_with(Arg) && Arg.compare(Val))
         Result.push_back(std::string(Val));
     return Result;
   }
@@ -221,7 +221,7 @@ OptTable::findByPrefix(StringRef Cur, Visibility VisibilityMask,
       std::string S = (Prefix + In.getName() + "\t").str();
       if (In.HelpText)
         S += In.HelpText;
-      if (StringRef(S).startswith(Cur) && S != std::string(Cur) + "\t")
+      if (StringRef(S).starts_with(Cur) && S != std::string(Cur) + "\t")
         Ret.push_back(S);
     }
   }
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index 41f1ce966ad2..36f6e5396375 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -565,7 +565,7 @@ static bool checkParametrizedPassName(StringRef Name, StringRef PassName) {
   // normal pass name w/o parameters == default parameters
   if (Name.empty())
     return true;
-  return Name.startswith("<") && Name.endswith(">");
+  return Name.starts_with("<") && Name.ends_with(">");
 }
 
 static std::optional<OptimizationLevel> parseOptLevel(StringRef S) {
@@ -1133,8 +1133,8 @@ Expected<bool> parseWinEHPrepareOptions(StringRef Params) {
 /// Tests whether a pass name starts with a valid prefix for a default pipeline
 /// alias.
 static bool startsWithDefaultPipelineAliasPrefix(StringRef Name) {
-  return Name.startswith("default") || Name.startswith("thinlto") ||
-         Name.startswith("lto");
+  return Name.starts_with("default") || Name.starts_with("thinlto") ||
+         Name.starts_with("lto");
 }
 
 /// Tests whether registered callbacks will accept a given pass name.
diff --git a/llvm/lib/ProfileData/GCOV.cpp b/llvm/lib/ProfileData/GCOV.cpp
index 5fce3dd5f7b7..f7bf42e5c4d2 100644
--- a/llvm/lib/ProfileData/GCOV.cpp
+++ b/llvm/lib/ProfileData/GCOV.cpp
@@ -337,7 +337,7 @@ StringRef GCOVFunction::getName(bool demangle) const {
     return Name;
   if (demangled.empty()) {
     do {
-      if (Name.startswith("_Z")) {
+      if (Name.starts_with("_Z")) {
         // Name is guaranteed to be NUL-terminated.
         if (char *res = itaniumDemangle(Name.data())) {
           demangled = res;
diff --git a/llvm/lib/ProfileData/InstrProf.cpp b/llvm/lib/ProfileData/InstrProf.cpp
index 236b083a1e21..a53e44d85d09 100644
--- a/llvm/lib/ProfileData/InstrProf.cpp
+++ b/llvm/lib/ProfileData/InstrProf.cpp
@@ -385,7 +385,7 @@ StringRef getFuncNameWithoutPrefix(StringRef PGOFuncName, StringRef FileName) {
   if (FileName.empty())
     return PGOFuncName;
   // Drop the file name including ':'. See also getPGOFuncName.
-  if (PGOFuncName.startswith(FileName))
+  if (PGOFuncName.starts_with(FileName))
     PGOFuncName = PGOFuncName.drop_front(FileName.size() + 1);
   return PGOFuncName;
 }
diff --git a/llvm/lib/ProfileData/InstrProfCorrelator.cpp b/llvm/lib/ProfileData/InstrProfCorrelator.cpp
index 24d828f69c71..8529a1798735 100644
--- a/llvm/lib/ProfileData/InstrProfCorrelator.cpp
+++ b/llvm/lib/ProfileData/InstrProfCorrelator.cpp
@@ -277,7 +277,7 @@ bool DwarfInstrProfCorrelator<IntPtrT>::isDIEOfProbe(const DWARFDie &Die) {
   if (!Die.hasChildren())
     return false;
   if (const char *Name = Die.getName(DINameKind::ShortName))
-    return StringRef(Name).startswith(getInstrProfCountersVarPrefix());
+    return StringRef(Name).starts_with(getInstrProfCountersVarPrefix());
   return false;
 }
 
diff --git a/llvm/lib/ProfileData/InstrProfReader.cpp b/llvm/lib/ProfileData/InstrProfReader.cpp
index 74f3f3270c4c..f3fd456ae797 100644
--- a/llvm/lib/ProfileData/InstrProfReader.cpp
+++ b/llvm/lib/ProfileData/InstrProfReader.cpp
@@ -246,7 +246,7 @@ bool TextInstrProfReader::hasFormat(const MemoryBuffer &Buffer) {
 Error TextInstrProfReader::readHeader() {
   Symtab.reset(new InstrProfSymtab());
 
-  while (Line->startswith(":")) {
+  while (Line->starts_with(":")) {
     StringRef Str = Line->substr(1);
     if (Str.equals_insensitive("ir"))
       ProfileKind |= InstrProfKind::IRInstrumentation;
@@ -386,7 +386,7 @@ TextInstrProfReader::readValueProfileData(InstrProfRecord &Record) {
 
 Error TextInstrProfReader::readNextRecord(NamedInstrProfRecord &Record) {
   // Skip empty lines and comments.
-  while (!Line.is_at_end() && (Line->empty() || Line->startswith("#")))
+  while (!Line.is_at_end() && (Line->empty() || Line->starts_with("#")))
     ++Line;
   // If we hit EOF while looking for a name, we're done.
   if (Line.is_at_end()) {
@@ -428,7 +428,7 @@ Error TextInstrProfReader::readNextRecord(NamedInstrProfRecord &Record) {
   }
 
   // Bitmap byte information is indicated with special character.
-  if (Line->startswith("$")) {
+  if (Line->starts_with("$")) {
     Record.BitmapBytes.clear();
     // Read the number of bitmap bytes.
     uint64_t NumBitmapBytes;
@@ -1017,7 +1017,7 @@ public:
     std::pair<StringRef, StringRef> Parts = {StringRef(), Name};
     while (true) {
       Parts = Parts.second.split(':');
-      if (Parts.first.startswith("_Z"))
+      if (Parts.first.starts_with("_Z"))
         return Parts.first;
       if (Parts.second.empty())
         return Name;
diff --git a/llvm/lib/ProfileData/ItaniumManglingCanonicalizer.cpp b/llvm/lib/ProfileData/ItaniumManglingCanonicalizer.cpp
index 593677214e58..6271b1622693 100644
--- a/llvm/lib/ProfileData/ItaniumManglingCanonicalizer.cpp
+++ b/llvm/lib/ProfileData/ItaniumManglingCanonicalizer.cpp
@@ -225,7 +225,7 @@ ItaniumManglingCanonicalizer::addEquivalence(FragmentKind Kind, StringRef First,
       // arguments. This mostly just falls out, as almost all template names
       // are valid as <name>s, but we also want to parse <substitution>s as
       // <name>s, even though they're not.
-      else if (Str.startswith("S"))
+      else if (Str.starts_with("S"))
         // Parse the substitution and optional following template arguments.
         N = P->Demangler.parseType();
       else
@@ -289,8 +289,8 @@ parseMaybeMangledName(CanonicalizingDemangler &Demangler, StringRef Mangling,
   //   encoding 6memcpy 7memmove
   // consistent with how they are encoded as local-names inside a C++ mangling.
   Node *N;
-  if (Mangling.startswith("_Z") || Mangling.startswith("__Z") ||
-      Mangling.startswith("___Z") || Mangling.startswith("____Z"))
+  if (Mangling.starts_with("_Z") || Mangling.starts_with("__Z") ||
+      Mangling.starts_with("___Z") || Mangling.starts_with("____Z"))
     N = Demangler.parse();
   else
     N = Demangler.make<itanium_demangle::NameType>(
diff --git a/llvm/lib/ProfileData/SampleProfReader.cpp b/llvm/lib/ProfileData/SampleProfReader.cpp
index ed92713c2c62..98d0aa794529 100644
--- a/llvm/lib/ProfileData/SampleProfReader.cpp
+++ b/llvm/lib/ProfileData/SampleProfReader.cpp
@@ -180,12 +180,12 @@ static bool isOffsetLegal(unsigned L) { return (L & 0xffff) == L; }
 /// Stores the FunctionHash (a.k.a. CFG Checksum) into \p FunctionHash.
 static bool parseMetadata(const StringRef &Input, uint64_t &FunctionHash,
                           uint32_t &Attributes) {
-  if (Input.startswith("!CFGChecksum:")) {
+  if (Input.starts_with("!CFGChecksum:")) {
     StringRef CFGInfo = Input.substr(strlen("!CFGChecksum:")).trim();
     return !CFGInfo.getAsInteger(10, FunctionHash);
   }
 
-  if (Input.startswith("!Attributes:")) {
+  if (Input.starts_with("!Attributes:")) {
     StringRef Attrib = Input.substr(strlen("!Attributes:")).trim();
     return !Attrib.getAsInteger(10, Attributes);
   }
diff --git a/llvm/lib/ProfileData/SymbolRemappingReader.cpp b/llvm/lib/ProfileData/SymbolRemappingReader.cpp
index 78457beb3e49..805f66b68ce7 100644
--- a/llvm/lib/ProfileData/SymbolRemappingReader.cpp
+++ b/llvm/lib/ProfileData/SymbolRemappingReader.cpp
@@ -37,7 +37,7 @@ Error SymbolRemappingReader::read(MemoryBuffer &B) {
     StringRef Line = *LineIt;
     Line = Line.ltrim(' ');
     // line_iterator only detects comments starting in column 1.
-    if (Line.startswith("#") || Line.empty())
+    if (Line.starts_with("#") || Line.empty())
       continue;
 
     SmallVector<StringRef, 4> Parts;
diff --git a/llvm/lib/Remarks/YAMLRemarkParser.cpp b/llvm/lib/Remarks/YAMLRemarkParser.cpp
index 947adbba10a2..218b6691398b 100644
--- a/llvm/lib/Remarks/YAMLRemarkParser.cpp
+++ b/llvm/lib/Remarks/YAMLRemarkParser.cpp
@@ -136,7 +136,7 @@ Expected<std::unique_ptr<YAMLRemarkParser>> remarks::createYAMLParserFromMeta(
       StrTab = std::move(*MaybeStrTab);
     }
     // If it starts with "---", there is no external file.
-    if (!Buf.startswith("---")) {
+    if (!Buf.starts_with("---")) {
       // At this point, we expect Buf to contain the external file path.
       StringRef ExternalFilePath = Buf;
       SmallString<80> FullPath;
diff --git a/llvm/lib/Support/Unix/Path.inc b/llvm/lib/Support/Unix/Path.inc
index 3b668ba82ebb..9f89d63bb0fd 100644
--- a/llvm/lib/Support/Unix/Path.inc
+++ b/llvm/lib/Support/Unix/Path.inc
@@ -652,7 +652,7 @@ std::error_code equivalent(const Twine &A, const Twine &B, bool &result) {
 
 static void expandTildeExpr(SmallVectorImpl<char> &Path) {
   StringRef PathStr(Path.begin(), Path.size());
-  if (PathStr.empty() || !PathStr.startswith("~"))
+  if (PathStr.empty() || !PathStr.starts_with("~"))
     return;
 
   PathStr = PathStr.drop_front();
diff --git a/llvm/lib/Target/AArch64/AArch64GlobalsTagging.cpp b/llvm/lib/Target/AArch64/AArch64GlobalsTagging.cpp
index 88e44eb0bfbb..8ce6f94e7341 100644
--- a/llvm/lib/Target/AArch64/AArch64GlobalsTagging.cpp
+++ b/llvm/lib/Target/AArch64/AArch64GlobalsTagging.cpp
@@ -37,7 +37,7 @@ static bool shouldTagGlobal(GlobalVariable &G) {
   // For now, don't instrument constant data, as it'll be in .rodata anyway. It
   // may be worth instrumenting these in future to stop them from being used as
   // gadgets.
-  if (G.getName().startswith("llvm.") || G.isThreadLocal() || G.isConstant()) {
+  if (G.getName().starts_with("llvm.") || G.isThreadLocal() || G.isConstant()) {
     Meta.Memtag = false;
     G.setSanitizerMetadata(Meta);
     return false;
diff --git a/llvm/lib/Target/AArch64/AArch64SLSHardening.cpp b/llvm/lib/Target/AArch64/AArch64SLSHardening.cpp
index 3687492c3e3e..76dd5a2d713e 100644
--- a/llvm/lib/Target/AArch64/AArch64SLSHardening.cpp
+++ b/llvm/lib/Target/AArch64/AArch64SLSHardening.cpp
@@ -212,7 +212,7 @@ bool SLSBLRThunkInserter::insertThunks(MachineModuleInfo &MMI,
 void SLSBLRThunkInserter::populateThunk(MachineFunction &MF) {
   // FIXME: How to better communicate Register number, rather than through
   // name and lookup table?
-  assert(MF.getName().startswith(getThunkPrefix()));
+  assert(MF.getName().starts_with(getThunkPrefix()));
   auto ThunkIt = llvm::find_if(
       SLSBLRThunks, [&MF](auto T) { return T.Name == MF.getName(); });
   assert(ThunkIt != std::end(SLSBLRThunks));
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index fbe1bf3c5238..238269cf27bd 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -3250,7 +3250,7 @@ ParseStatus AArch64AsmParser::tryParseFPImm(OperandVector &Operands) {
   }
 
   // Parse hexadecimal representation.
-  if (Tok.is(AsmToken::Integer) && Tok.getString().startswith("0x")) {
+  if (Tok.is(AsmToken::Integer) && Tok.getString().starts_with("0x")) {
     if (Tok.getIntVal() > 255 || isNegative)
       return TokError("encoded floating point value out of range");
 
@@ -7524,7 +7524,7 @@ bool AArch64AsmParser::parseAuthExpr(const MCExpr *&Res, SMLoc &EndLoc) {
   AsmToken Tok = Parser.getTok();
 
   // Look for '_sym@AUTH' ...
-  if (Tok.is(AsmToken::Identifier) && Tok.getIdentifier().endswith("@AUTH")) {
+  if (Tok.is(AsmToken::Identifier) && Tok.getIdentifier().ends_with("@AUTH")) {
     StringRef SymName = Tok.getIdentifier().drop_back(strlen("@AUTH"));
     if (SymName.contains('@'))
       return TokError(
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp b/llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp
index c798ab5f03b3..3437b6dc8ae0 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp
@@ -478,7 +478,7 @@ static bool eatTerm(StringRef& mangledName, const char c) {
 
 template <size_t N>
 static bool eatTerm(StringRef& mangledName, const char (&str)[N]) {
-  if (mangledName.startswith(StringRef(str, N-1))) {
+  if (mangledName.starts_with(StringRef(str, N - 1))) {
     drop_front(mangledName, N-1);
     return true;
   }
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 0c38fa32c6f3..97db19064f6f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -601,8 +601,8 @@ StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
 /// Predicate for Internalize pass.
 static bool mustPreserveGV(const GlobalValue &GV) {
   if (const Function *F = dyn_cast<Function>(&GV))
-    return F->isDeclaration() || F->getName().startswith("__asan_") ||
-           F->getName().startswith("__sanitizer_") ||
+    return F->isDeclaration() || F->getName().starts_with("__asan_") ||
+           F->getName().starts_with("__sanitizer_") ||
            AMDGPU::isEntryFunctionCC(F->getCallingConv());
 
   GV.removeDeadConstantUsers();
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetObjectFile.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetObjectFile.cpp
index f854c8c16e5a..584e41bfd546 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetObjectFile.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetObjectFile.cpp
@@ -30,7 +30,7 @@ MCSection *AMDGPUTargetObjectFile::getExplicitSectionGlobal(
     const GlobalObject *GO, SectionKind SK, const TargetMachine &TM) const {
   // Set metadata access for the explicit section
   StringRef SectionName = GO->getSection();
-  if (SectionName.startswith(".AMDGPU.comment."))
+  if (SectionName.starts_with(".AMDGPU.comment."))
     SK = SectionKind::getMetadata();
 
   return TargetLoweringObjectFileELF::getExplicitSectionGlobal(GO, SK, TM);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
index cb877a4695f1..3316659671bd 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
@@ -892,7 +892,7 @@ bool GCNTTIImpl::isReadRegisterSourceOfDivergence(
     return true;
 
   // Special case scalar registers that start with 'v'.
-  if (RegName.startswith("vcc") || RegName.empty())
+  if (RegName.starts_with("vcc") || RegName.empty())
     return false;
 
   // VGPR or AGPR is divergent. There aren't any specially named vector
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 092845d391a3..ed93948868da 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -2570,7 +2570,7 @@ static bool isRegularReg(RegisterKind Kind) {
 
 static const RegInfo* getRegularRegInfo(StringRef Str) {
   for (const RegInfo &Reg : RegularRegisters)
-    if (Str.startswith(Reg.Name))
+    if (Str.starts_with(Reg.Name))
       return &Reg;
   return nullptr;
 }
@@ -4479,7 +4479,7 @@ bool AMDGPUAsmParser::validateBLGP(const MCInst &Inst,
   SMLoc BLGPLoc = getBLGPLoc(Operands);
   if (!BLGPLoc.isValid())
     return true;
-  bool IsNeg = StringRef(BLGPLoc.getPointer()).startswith("neg:");
+  bool IsNeg = StringRef(BLGPLoc.getPointer()).starts_with("neg:");
   auto FB = getFeatureBits();
   bool UsesNeg = false;
   if (FB[AMDGPU::FeatureGFX940Insts]) {
@@ -5974,20 +5974,20 @@ StringRef AMDGPUAsmParser::parseMnemonicSuffix(StringRef Name) {
   setForcedDPP(false);
   setForcedSDWA(false);
 
-  if (Name.endswith("_e64_dpp")) {
+  if (Name.ends_with("_e64_dpp")) {
     setForcedDPP(true);
     setForcedEncodingSize(64);
     return Name.substr(0, Name.size() - 8);
-  } else if (Name.endswith("_e64")) {
+  } else if (Name.ends_with("_e64")) {
     setForcedEncodingSize(64);
     return Name.substr(0, Name.size() - 4);
-  } else if (Name.endswith("_e32")) {
+  } else if (Name.ends_with("_e32")) {
     setForcedEncodingSize(32);
     return Name.substr(0, Name.size() - 4);
-  } else if (Name.endswith("_dpp")) {
+  } else if (Name.ends_with("_dpp")) {
     setForcedDPP(true);
     return Name.substr(0, Name.size() - 4);
-  } else if (Name.endswith("_sdwa")) {
+  } else if (Name.ends_with("_sdwa")) {
     setForcedSDWA(true);
     return Name.substr(0, Name.size() - 5);
   }
@@ -6010,7 +6010,7 @@ bool AMDGPUAsmParser::ParseInstruction(ParseInstructionInfo &Info,
 
   Operands.push_back(AMDGPUOperand::CreateToken(this, Name, NameLoc));
 
-  bool IsMIMG = Name.startswith("image_");
+  bool IsMIMG = Name.starts_with("image_");
 
   while (!trySkipToken(AsmToken::EndOfStatement)) {
     OperandMode Mode = OperandMode_Default;
@@ -6150,7 +6150,7 @@ unsigned AMDGPUAsmParser::getCPolKind(StringRef Id, StringRef Mnemo,
                                       bool &Disabling) const {
   Disabling = Id.consume_front("no");
 
-  if (isGFX940() && !Mnemo.startswith("s_")) {
+  if (isGFX940() && !Mnemo.starts_with("s_")) {
     return StringSwitch<unsigned>(Id)
         .Case("nt", AMDGPU::CPol::NT)
         .Case("sc0", AMDGPU::CPol::SC0)
@@ -6282,13 +6282,13 @@ ParseStatus AMDGPUAsmParser::parseTH(OperandVector &Operands, int64_t &TH) {
   else if (Value == "TH_STORE_LU" || Value == "TH_LOAD_RT_WB" ||
            Value == "TH_LOAD_NT_WB") {
     return Error(StringLoc, "invalid th value");
-  } else if (Value.startswith("TH_ATOMIC_")) {
+  } else if (Value.starts_with("TH_ATOMIC_")) {
     Value = Value.drop_front(10);
     TH = AMDGPU::CPol::TH_TYPE_ATOMIC;
-  } else if (Value.startswith("TH_LOAD_")) {
+  } else if (Value.starts_with("TH_LOAD_")) {
     Value = Value.drop_front(8);
     TH = AMDGPU::CPol::TH_TYPE_LOAD;
-  } else if (Value.startswith("TH_STORE_")) {
+  } else if (Value.starts_with("TH_STORE_")) {
     Value = Value.drop_front(9);
     TH = AMDGPU::CPol::TH_TYPE_STORE;
   } else {
@@ -6733,7 +6733,7 @@ bool AMDGPUAsmParser::parseCnt(int64_t &IntVal) {
   AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());
 
   bool Failed = true;
-  bool Sat = CntName.endswith("_sat");
+  bool Sat = CntName.ends_with("_sat");
 
   if (CntName == "vmcnt" || CntName == "vmcnt_sat") {
     Failed = encodeCnt(ISA, IntVal, CntVal, Sat, encodeVmcnt, decodeVmcnt);
@@ -7206,7 +7206,7 @@ ParseStatus AMDGPUAsmParser::parseInterpAttr(OperandVector &Operands) {
   if (!parseId(Str))
     return ParseStatus::NoMatch;
 
-  if (!Str.startswith("attr"))
+  if (!Str.starts_with("attr"))
     return Error(S, "invalid interpolation attribute");
 
   StringRef Chan = Str.take_back(2);
@@ -7297,7 +7297,7 @@ bool
 AMDGPUAsmParser::trySkipId(const StringRef Pref, const StringRef Id) {
   if (isToken(AsmToken::Identifier)) {
     StringRef Tok = getTokenStr();
-    if (Tok.startswith(Pref) && Tok.drop_front(Pref.size()) == Id) {
+    if (Tok.starts_with(Pref) && Tok.drop_front(Pref.size()) == Id) {
       lex();
       return true;
     }
@@ -8446,7 +8446,7 @@ bool AMDGPUAsmParser::parseDimId(unsigned &Encoding) {
   Token += Suffix;
 
   StringRef DimId = Token;
-  if (DimId.startswith("SQ_RSRC_IMG_"))
+  if (DimId.starts_with("SQ_RSRC_IMG_"))
     DimId = DimId.drop_front(12);
 
   const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByAsmSuffix(DimId);
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 1f11beb71101..f0ba870b6619 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -2184,7 +2184,7 @@ AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size,
 
   // Code Object V3 kernel descriptors.
   StringRef Name = Symbol.Name;
-  if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) {
+  if (Symbol.Type == ELF::STT_OBJECT && Name.ends_with(StringRef(".kd"))) {
     Size = 64; // Size = 64 regardless of success or failure.
     return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address);
   }
diff --git a/llvm/lib/Target/AMDGPU/R600OpenCLImageTypeLoweringPass.cpp b/llvm/lib/Target/AMDGPU/R600OpenCLImageTypeLoweringPass.cpp
index 2a15c0123b74..195dc4f9a0f4 100644
--- a/llvm/lib/Target/AMDGPU/R600OpenCLImageTypeLoweringPass.cpp
+++ b/llvm/lib/Target/AMDGPU/R600OpenCLImageTypeLoweringPass.cpp
@@ -163,11 +163,11 @@ class R600OpenCLImageTypeLoweringPass : public ModulePass {
 
       Value *Replacement = nullptr;
       StringRef Name = F->getName();
-      if (Name.startswith(GetImageResourceIDFunc)) {
+      if (Name.starts_with(GetImageResourceIDFunc)) {
         Replacement = ConstantInt::get(Int32Type, ResourceID);
-      } else if (Name.startswith(GetImageSizeFunc)) {
+      } else if (Name.starts_with(GetImageSizeFunc)) {
         Replacement = &ImageSizeArg;
-      } else if (Name.startswith(GetImageFormatFunc)) {
+      } else if (Name.starts_with(GetImageFormatFunc)) {
         Replacement = &ImageFormatArg;
       } else {
         continue;
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index a7f4d63229b7..aedb832b9459 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -14461,7 +14461,7 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI_,
       return std::pair(0U, RC);
   }
 
-  if (Constraint.startswith("{") && Constraint.endswith("}")) {
+  if (Constraint.starts_with("{") && Constraint.ends_with("}")) {
     StringRef RegName(Constraint.data() + 1, Constraint.size() - 2);
     if (RegName.consume_front("v")) {
       RC = &AMDGPU::VGPR_32RegClass;
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
index f8eb67199f62..e0c23e40e19d 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
@@ -728,7 +728,7 @@ bool SIMachineFunctionInfo::mayUseAGPRs(const Function &F) const {
         for (const auto &CI : IA->ParseConstraints()) {
           for (StringRef Code : CI.Codes) {
             Code.consume_front("{");
-            if (Code.startswith("a"))
+            if (Code.starts_with("a"))
               return true;
           }
         }
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 68d561a0d9f7..8faa9e5f6d30 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -716,9 +716,9 @@ void AMDGPUTargetID::setTargetIDFromFeaturesString(StringRef FS) {
 
 static TargetIDSetting
 getTargetIDSettingFromFeatureString(StringRef FeatureString) {
-  if (FeatureString.endswith("-"))
+  if (FeatureString.ends_with("-"))
     return TargetIDSetting::Off;
-  if (FeatureString.endswith("+"))
+  if (FeatureString.ends_with("+"))
     return TargetIDSetting::On;
 
   llvm_unreachable("Malformed feature string");
@@ -729,9 +729,9 @@ void AMDGPUTargetID::setTargetIDFromTargetIDStream(StringRef TargetID) {
   TargetID.split(TargetIDSplit, ':');
 
   for (const auto &FeatureString : TargetIDSplit) {
-    if (FeatureString.startswith("xnack"))
+    if (FeatureString.starts_with("xnack"))
       XnackSetting = getTargetIDSettingFromFeatureString(FeatureString);
-    if (FeatureString.startswith("sramecc"))
+    if (FeatureString.starts_with("sramecc"))
       SramEccSetting = getTargetIDSettingFromFeatureString(FeatureString);
   }
 }
@@ -1578,7 +1578,7 @@ unsigned getTgtId(const StringRef Name) {
     if (Val.MaxIndex == 0 && Name == Val.Name)
       return Val.Tgt;
 
-    if (Val.MaxIndex > 0 && Name.startswith(Val.Name)) {
+    if (Val.MaxIndex > 0 && Name.starts_with(Val.Name)) {
       StringRef Suffix = Name.drop_front(Val.Name.size());
 
       unsigned Id;
diff --git a/llvm/lib/Target/ARM/ARMSLSHardening.cpp b/llvm/lib/Target/ARM/ARMSLSHardening.cpp
index 09357ae2e3a3..23d72b34902d 100644
--- a/llvm/lib/Target/ARM/ARMSLSHardening.cpp
+++ b/llvm/lib/Target/ARM/ARMSLSHardening.cpp
@@ -210,7 +210,7 @@ ArmInsertedThunks SLSBLRThunkInserter::insertThunks(MachineModuleInfo &MMI,
 void SLSBLRThunkInserter::populateThunk(MachineFunction &MF) {
   // FIXME: How to better communicate Register number, rather than through
   // name and lookup table?
-  assert(MF.getName().startswith(getThunkPrefix()));
+  assert(MF.getName().starts_with(getThunkPrefix()));
   auto ThunkIt = llvm::find_if(
       SLSBLRThunks, [&MF](auto T) { return T.Name == MF.getName(); });
   assert(ThunkIt != std::end(SLSBLRThunks));
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index a80d485e750b..deae3c9df35d 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -130,9 +130,9 @@ computeTargetABI(const Triple &TT, StringRef CPU,
 
   if (ABIName == "aapcs16")
     return ARMBaseTargetMachine::ARM_ABI_AAPCS16;
-  else if (ABIName.startswith("aapcs"))
+  else if (ABIName.starts_with("aapcs"))
     return ARMBaseTargetMachine::ARM_ABI_AAPCS;
-  else if (ABIName.startswith("apcs"))
+  else if (ABIName.starts_with("apcs"))
     return ARMBaseTargetMachine::ARM_ABI_APCS;
 
   llvm_unreachable("Unhandled/unknown ABI Name!");
diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
index ab0a8f78b156..cbc5e5210865 100644
--- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
@@ -1984,7 +1984,7 @@ bool ARMTTIImpl::isLoweredToCall(const Function *F) {
     return BaseT::isLoweredToCall(F);
 
   // Assume all Arm-specific intrinsics map to an instruction.
-  if (F->getName().startswith("llvm.arm"))
+  if (F->getName().starts_with("llvm.arm"))
     return false;
 
   switch (F->getIntrinsicID()) {
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 20b52ebc544a..18dccb26b877 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -191,7 +191,7 @@ public:
   /// Returns true iff a given mnemonic is a CDE instruction
   bool isCDEInstr(StringRef Mnemonic) {
     // Quick check before searching the set
-    if (!Mnemonic.startswith("cx") && !Mnemonic.startswith("vcx"))
+    if (!Mnemonic.starts_with("cx") && !Mnemonic.starts_with("vcx"))
       return false;
     return CDE.count(Mnemonic);
   }
@@ -199,7 +199,7 @@ public:
   /// Returns true iff a given mnemonic is a VPT-predicable CDE instruction
   /// (possibly with a predication suffix "e" or "t")
   bool isVPTPredicableCDEInstr(StringRef Mnemonic) {
-    if (!Mnemonic.startswith("vcx"))
+    if (!Mnemonic.starts_with("vcx"))
       return false;
     return CDEWithVPTSuffix.count(Mnemonic);
   }
@@ -207,17 +207,17 @@ public:
   /// Returns true iff a given mnemonic is an IT-predicable CDE instruction
   /// (possibly with a condition suffix)
   bool isITPredicableCDEInstr(StringRef Mnemonic) {
-    if (!Mnemonic.startswith("cx"))
+    if (!Mnemonic.starts_with("cx"))
       return false;
-    return Mnemonic.startswith("cx1a") || Mnemonic.startswith("cx1da") ||
-           Mnemonic.startswith("cx2a") || Mnemonic.startswith("cx2da") ||
-           Mnemonic.startswith("cx3a") || Mnemonic.startswith("cx3da");
+    return Mnemonic.starts_with("cx1a") || Mnemonic.starts_with("cx1da") ||
+           Mnemonic.starts_with("cx2a") || Mnemonic.starts_with("cx2da") ||
+           Mnemonic.starts_with("cx3a") || Mnemonic.starts_with("cx3da");
   }
 
   /// Return true iff a given mnemonic is an integer CDE instruction with
   /// dual-register destination
   bool isCDEDualRegInstr(StringRef Mnemonic) {
-    if (!Mnemonic.startswith("cx"))
+    if (!Mnemonic.starts_with("cx"))
       return false;
     return Mnemonic == "cx1d" || Mnemonic == "cx1da" ||
            Mnemonic == "cx2d" || Mnemonic == "cx2da" ||
@@ -6083,7 +6083,7 @@ bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
   case AsmToken::LBrac:
     return parseMemory(Operands);
   case AsmToken::LCurly:
-    return parseRegisterList(Operands, !Mnemonic.startswith("clr"));
+    return parseRegisterList(Operands, !Mnemonic.starts_with("clr"));
   case AsmToken::Dollar:
   case AsmToken::Hash: {
     // #42 -> immediate
@@ -6295,32 +6295,29 @@ StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
   // Ignore some mnemonics we know aren't predicated forms.
   //
   // FIXME: Would be nice to autogen this.
-  if ((Mnemonic == "movs" && isThumb()) ||
-      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
-      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
-      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
-      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
-      Mnemonic == "vaclt" || Mnemonic == "vacle"  || Mnemonic == "hlt" ||
-      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
-      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
-      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
-      Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
-      Mnemonic == "vcvta" || Mnemonic == "vcvtn"  || Mnemonic == "vcvtp" ||
-      Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
-      Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" ||
-      Mnemonic.startswith("vsel") || Mnemonic == "vins" || Mnemonic == "vmovx" ||
-      Mnemonic == "bxns"  || Mnemonic == "blxns" ||
-      Mnemonic == "vdot"  || Mnemonic == "vmmla" ||
-      Mnemonic == "vudot" || Mnemonic == "vsdot" ||
-      Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
-      Mnemonic == "vfmal" || Mnemonic == "vfmsl" ||
-      Mnemonic == "wls"   || Mnemonic == "le"    || Mnemonic == "dls" ||
-      Mnemonic == "csel"  || Mnemonic == "csinc" ||
-      Mnemonic == "csinv" || Mnemonic == "csneg" || Mnemonic == "cinc" ||
-      Mnemonic == "cinv"  || Mnemonic == "cneg"  || Mnemonic == "cset" ||
-      Mnemonic == "csetm" ||
-      Mnemonic == "aut"   || Mnemonic == "pac" || Mnemonic == "pacbti" ||
-      Mnemonic == "bti")
+  if ((Mnemonic == "movs" && isThumb()) || Mnemonic == "teq" ||
+      Mnemonic == "vceq" || Mnemonic == "svc" || Mnemonic == "mls" ||
+      Mnemonic == "smmls" || Mnemonic == "vcls" || Mnemonic == "vmls" ||
+      Mnemonic == "vnmls" || Mnemonic == "vacge" || Mnemonic == "vcge" ||
+      Mnemonic == "vclt" || Mnemonic == "vacgt" || Mnemonic == "vaclt" ||
+      Mnemonic == "vacle" || Mnemonic == "hlt" || Mnemonic == "vcgt" ||
+      Mnemonic == "vcle" || Mnemonic == "smlal" || Mnemonic == "umaal" ||
+      Mnemonic == "umlal" || Mnemonic == "vabal" || Mnemonic == "vmlal" ||
+      Mnemonic == "vpadal" || Mnemonic == "vqdmlal" || Mnemonic == "fmuls" ||
+      Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
+      Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
+      Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
+      Mnemonic == "vrintm" || Mnemonic == "hvc" ||
+      Mnemonic.starts_with("vsel") || Mnemonic == "vins" ||
+      Mnemonic == "vmovx" || Mnemonic == "bxns" || Mnemonic == "blxns" ||
+      Mnemonic == "vdot" || Mnemonic == "vmmla" || Mnemonic == "vudot" ||
+      Mnemonic == "vsdot" || Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
+      Mnemonic == "vfmal" || Mnemonic == "vfmsl" || Mnemonic == "wls" ||
+      Mnemonic == "le" || Mnemonic == "dls" || Mnemonic == "csel" ||
+      Mnemonic == "csinc" || Mnemonic == "csinv" || Mnemonic == "csneg" ||
+      Mnemonic == "cinc" || Mnemonic == "cinv" || Mnemonic == "cneg" ||
+      Mnemonic == "cset" || Mnemonic == "csetm" || Mnemonic == "aut" ||
+      Mnemonic == "pac" || Mnemonic == "pacbti" || Mnemonic == "bti")
     return Mnemonic;
 
   // First, split out any predication code. Ignore mnemonics we know aren't
@@ -6330,16 +6327,13 @@ StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
       Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
       Mnemonic != "sbcs" && Mnemonic != "rscs" &&
       !(hasMVE() &&
-        (Mnemonic == "vmine" ||
-         Mnemonic == "vshle" || Mnemonic == "vshlt" || Mnemonic == "vshllt" ||
-         Mnemonic == "vrshle" || Mnemonic == "vrshlt" ||
-         Mnemonic == "vmvne" || Mnemonic == "vorne" ||
-         Mnemonic == "vnege" || Mnemonic == "vnegt" ||
-         Mnemonic == "vmule" || Mnemonic == "vmult" ||
-         Mnemonic == "vrintne" ||
-         Mnemonic == "vcmult" || Mnemonic == "vcmule" ||
-         Mnemonic == "vpsele" || Mnemonic == "vpselt" ||
-         Mnemonic.startswith("vq")))) {
+        (Mnemonic == "vmine" || Mnemonic == "vshle" || Mnemonic == "vshlt" ||
+         Mnemonic == "vshllt" || Mnemonic == "vrshle" || Mnemonic == "vrshlt" ||
+         Mnemonic == "vmvne" || Mnemonic == "vorne" || Mnemonic == "vnege" ||
+         Mnemonic == "vnegt" || Mnemonic == "vmule" || Mnemonic == "vmult" ||
+         Mnemonic == "vrintne" || Mnemonic == "vcmult" ||
+         Mnemonic == "vcmule" || Mnemonic == "vpsele" || Mnemonic == "vpselt" ||
+         Mnemonic.starts_with("vq")))) {
     unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2));
     if (CC != ~0U) {
       Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
@@ -6349,18 +6343,17 @@ StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
 
   // Next, determine if we have a carry setting bit. We explicitly ignore all
   // the instructions we know end in 's'.
-  if (Mnemonic.endswith("s") &&
-      !(Mnemonic == "cps" || Mnemonic == "mls" ||
-        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
-        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
-        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
-        Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
-        Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
-        Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
-        Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
-        Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
-        Mnemonic == "bxns" || Mnemonic == "blxns" || Mnemonic == "vfmas" ||
-        Mnemonic == "vmlas" ||
+  if (Mnemonic.ends_with("s") &&
+      !(Mnemonic == "cps" || Mnemonic == "mls" || Mnemonic == "mrs" ||
+        Mnemonic == "smmls" || Mnemonic == "vabs" || Mnemonic == "vcls" ||
+        Mnemonic == "vmls" || Mnemonic == "vmrs" || Mnemonic == "vnmls" ||
+        Mnemonic == "vqabs" || Mnemonic == "vrecps" || Mnemonic == "vrsqrts" ||
+        Mnemonic == "srs" || Mnemonic == "flds" || Mnemonic == "fmrs" ||
+        Mnemonic == "fsqrts" || Mnemonic == "fsubs" || Mnemonic == "fsts" ||
+        Mnemonic == "fcpys" || Mnemonic == "fdivs" || Mnemonic == "fmuls" ||
+        Mnemonic == "fcmps" || Mnemonic == "fcmpzs" || Mnemonic == "vfms" ||
+        Mnemonic == "vfnms" || Mnemonic == "fconsts" || Mnemonic == "bxns" ||
+        Mnemonic == "blxns" || Mnemonic == "vfmas" || Mnemonic == "vmlas" ||
         (Mnemonic == "movs" && isThumb()))) {
     Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
     CarrySetting = true;
@@ -6368,7 +6361,7 @@ StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
 
   // The "cps" instruction can have a interrupt mode operand which is glued into
   // the mnemonic. Check if this is the case, split it and parse the imod op
-  if (Mnemonic.startswith("cps")) {
+  if (Mnemonic.starts_with("cps")) {
     // Split out any imod code.
     unsigned IMod =
       StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
@@ -6397,16 +6390,15 @@ StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
   }
 
   // The "it" instruction has the condition mask on the end of the mnemonic.
-  if (Mnemonic.startswith("it")) {
+  if (Mnemonic.starts_with("it")) {
     ITMask = Mnemonic.slice(2, Mnemonic.size());
     Mnemonic = Mnemonic.slice(0, 2);
   }
 
-  if (Mnemonic.startswith("vpst")) {
+  if (Mnemonic.starts_with("vpst")) {
     ITMask = Mnemonic.slice(4, Mnemonic.size());
     Mnemonic = Mnemonic.slice(0, 4);
-  }
-  else if (Mnemonic.startswith("vpt")) {
+  } else if (Mnemonic.starts_with("vpt")) {
     ITMask = Mnemonic.slice(3, Mnemonic.size());
     Mnemonic = Mnemonic.slice(0, 3);
   }
@@ -6441,39 +6433,36 @@ void ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic,
   if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
       Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
       Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" ||
-      Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
-      Mnemonic.startswith("vsel") || Mnemonic == "vmaxnm" ||
+      Mnemonic.starts_with("crc32") || Mnemonic.starts_with("cps") ||
+      Mnemonic.starts_with("vsel") || Mnemonic == "vmaxnm" ||
       Mnemonic == "vminnm" || Mnemonic == "vcvta" || Mnemonic == "vcvtn" ||
       Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || Mnemonic == "vrinta" ||
       Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" ||
-      Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" ||
-      Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
-      (FullInst.startswith("vmull") && FullInst.endswith(".p64")) ||
-      Mnemonic == "vmovx" || Mnemonic == "vins" ||
-      Mnemonic == "vudot" || Mnemonic == "vsdot" ||
-      Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
-      Mnemonic == "vfmal" || Mnemonic == "vfmsl" ||
-      Mnemonic == "vfmat" || Mnemonic == "vfmab" ||
-      Mnemonic == "vdot"  || Mnemonic == "vmmla" ||
-      Mnemonic == "sb"    || Mnemonic == "ssbb"  ||
-      Mnemonic == "pssbb" || Mnemonic == "vsmmla" ||
-      Mnemonic == "vummla" || Mnemonic == "vusmmla" ||
-      Mnemonic == "vusdot" || Mnemonic == "vsudot" ||
-      Mnemonic == "bfcsel" || Mnemonic == "wls" ||
-      Mnemonic == "dls" || Mnemonic == "le" || Mnemonic == "csel" ||
-      Mnemonic == "csinc" || Mnemonic == "csinv" || Mnemonic == "csneg" ||
-      Mnemonic == "cinc" || Mnemonic == "cinv" || Mnemonic == "cneg" ||
-      Mnemonic == "cset" || Mnemonic == "csetm" ||
+      Mnemonic.starts_with("aes") || Mnemonic == "hvc" ||
+      Mnemonic == "setpan" || Mnemonic.starts_with("sha1") ||
+      Mnemonic.starts_with("sha256") ||
+      (FullInst.starts_with("vmull") && FullInst.ends_with(".p64")) ||
+      Mnemonic == "vmovx" || Mnemonic == "vins" || Mnemonic == "vudot" ||
+      Mnemonic == "vsdot" || Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
+      Mnemonic == "vfmal" || Mnemonic == "vfmsl" || Mnemonic == "vfmat" ||
+      Mnemonic == "vfmab" || Mnemonic == "vdot" || Mnemonic == "vmmla" ||
+      Mnemonic == "sb" || Mnemonic == "ssbb" || Mnemonic == "pssbb" ||
+      Mnemonic == "vsmmla" || Mnemonic == "vummla" || Mnemonic == "vusmmla" ||
+      Mnemonic == "vusdot" || Mnemonic == "vsudot" || Mnemonic == "bfcsel" ||
+      Mnemonic == "wls" || Mnemonic == "dls" || Mnemonic == "le" ||
+      Mnemonic == "csel" || Mnemonic == "csinc" || Mnemonic == "csinv" ||
+      Mnemonic == "csneg" || Mnemonic == "cinc" || Mnemonic == "cinv" ||
+      Mnemonic == "cneg" || Mnemonic == "cset" || Mnemonic == "csetm" ||
       (hasCDE() && MS.isCDEInstr(Mnemonic) &&
        !MS.isITPredicableCDEInstr(Mnemonic)) ||
-      Mnemonic.startswith("vpt") || Mnemonic.startswith("vpst") ||
+      Mnemonic.starts_with("vpt") || Mnemonic.starts_with("vpst") ||
       Mnemonic == "pac" || Mnemonic == "pacbti" || Mnemonic == "aut" ||
       Mnemonic == "bti" ||
       (hasMVE() &&
-       (Mnemonic.startswith("vst2") || Mnemonic.startswith("vld2") ||
-        Mnemonic.startswith("vst4") || Mnemonic.startswith("vld4") ||
-        Mnemonic.startswith("wlstp") || Mnemonic.startswith("dlstp") ||
-        Mnemonic.startswith("letp")))) {
+       (Mnemonic.starts_with("vst2") || Mnemonic.starts_with("vld2") ||
+        Mnemonic.starts_with("vst4") || Mnemonic.starts_with("vld4") ||
+        Mnemonic.starts_with("wlstp") || Mnemonic.starts_with("dlstp") ||
+        Mnemonic.starts_with("letp")))) {
     // These mnemonics are never predicable
     CanAcceptPredicationCode = false;
   } else if (!isThumb()) {
@@ -6484,9 +6473,8 @@ void ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic,
         Mnemonic != "dmb" && Mnemonic != "dfb" && Mnemonic != "dsb" &&
         Mnemonic != "isb" && Mnemonic != "pld" && Mnemonic != "pli" &&
         Mnemonic != "pldw" && Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
-        Mnemonic != "stc2" && Mnemonic != "stc2l" &&
-        Mnemonic != "tsb" &&
-        !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
+        Mnemonic != "stc2" && Mnemonic != "stc2l" && Mnemonic != "tsb" &&
+        !Mnemonic.starts_with("rfe") && !Mnemonic.starts_with("srs");
   } else if (isThumbOne()) {
     if (hasV6MOps())
       CanAcceptPredicationCode = Mnemonic != "movs";
@@ -6782,16 +6770,16 @@ bool ARMAsmParser::shouldOmitVectorPredicateOperand(StringRef Mnemonic,
   if (!hasMVE() || Operands.size() < 3)
     return true;
 
-  if (Mnemonic.startswith("vld2") || Mnemonic.startswith("vld4") ||
-      Mnemonic.startswith("vst2") || Mnemonic.startswith("vst4"))
+  if (Mnemonic.starts_with("vld2") || Mnemonic.starts_with("vld4") ||
+      Mnemonic.starts_with("vst2") || Mnemonic.starts_with("vst4"))
     return true;
 
-  if (Mnemonic.startswith("vctp") || Mnemonic.startswith("vpnot"))
+  if (Mnemonic.starts_with("vctp") || Mnemonic.starts_with("vpnot"))
     return false;
 
-  if (Mnemonic.startswith("vmov") &&
-      !(Mnemonic.startswith("vmovl") || Mnemonic.startswith("vmovn") ||
-        Mnemonic.startswith("vmovx"))) {
+  if (Mnemonic.starts_with("vmov") &&
+      !(Mnemonic.starts_with("vmovl") || Mnemonic.starts_with("vmovn") ||
+        Mnemonic.starts_with("vmovx"))) {
     for (auto &Operand : Operands) {
       if (static_cast<ARMOperand &>(*Operand).isVectorIndex() ||
           ((*Operand).isReg() &&
@@ -6831,7 +6819,7 @@ static bool isDataTypeToken(StringRef Tok) {
 // in the .td files that matches the suffix instead of having it be
 // a literal string token the way it is now.
 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
-  return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
+  return Mnemonic.starts_with("vldm") || Mnemonic.starts_with("vstm");
 }
 
 static void applyMnemonicAliases(StringRef &Mnemonic,
@@ -7001,8 +6989,8 @@ bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
   //    ITxyz -> xyz1    (e.g. ITEET -> 1101)
   // Note: See the ARM::PredBlockMask enum in
   //   /lib/Target/ARM/Utils/ARMBaseInfo.h
-  if (Mnemonic == "it" || Mnemonic.startswith("vpt") ||
-      Mnemonic.startswith("vpst")) {
+  if (Mnemonic == "it" || Mnemonic.starts_with("vpt") ||
+      Mnemonic.starts_with("vpst")) {
     SMLoc Loc = Mnemonic == "it"  ? SMLoc::getFromPointer(NameLoc.getPointer() + 2) :
                 Mnemonic == "vpt" ? SMLoc::getFromPointer(NameLoc.getPointer() + 3) :
                                     SMLoc::getFromPointer(NameLoc.getPointer() + 4);
@@ -7080,8 +7068,8 @@ bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
   // scalar predication operand we do not add the vector one and leave until
   // now to fix it up.
   if (CanAcceptVPTPredicationCode && Mnemonic != "vmov" &&
-      !Mnemonic.startswith("vcmp") &&
-      !(Mnemonic.startswith("vcvt") && Mnemonic != "vcvta" &&
+      !Mnemonic.starts_with("vcmp") &&
+      !(Mnemonic.starts_with("vcvt") && Mnemonic != "vcvta" &&
         Mnemonic != "vcvtn" && Mnemonic != "vcvtp" && Mnemonic != "vcvtm")) {
     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
                                       CarrySetting);
@@ -7226,10 +7214,11 @@ bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
     // special parsing.  So now we have to see if they require vector
     // predication and replace the scalar one with the vector predication
     // operand if that is the case.
-    else if (Mnemonic == "vmov" || Mnemonic.startswith("vcmp") ||
-             (Mnemonic.startswith("vcvt") && !Mnemonic.startswith("vcvta") &&
-              !Mnemonic.startswith("vcvtn") && !Mnemonic.startswith("vcvtp") &&
-              !Mnemonic.startswith("vcvtm"))) {
+    else if (Mnemonic == "vmov" || Mnemonic.starts_with("vcmp") ||
+             (Mnemonic.starts_with("vcvt") && !Mnemonic.starts_with("vcvta") &&
+              !Mnemonic.starts_with("vcvtn") &&
+              !Mnemonic.starts_with("vcvtp") &&
+              !Mnemonic.starts_with("vcvtm"))) {
       if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
         // We could not split the vector predicate off vcvt because it might
         // have been the scalar vcvtt instruction.  Now we know its a vector
@@ -7237,11 +7226,11 @@ bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
         // predicated vcvt with 'Then' predication or the vector vcvtt.  We can
         // distinguish the two based on the suffixes, if it is any of
         // ".f16.f32", ".f32.f16", ".f16.f64" or ".f64.f16" then it is the vcvtt.
-        if (Mnemonic.startswith("vcvtt") && Operands.size() >= 4) {
+        if (Mnemonic.starts_with("vcvtt") && Operands.size() >= 4) {
           auto Sz1 = static_cast<ARMOperand &>(*Operands[2]);
           auto Sz2 = static_cast<ARMOperand &>(*Operands[3]);
-          if (!(Sz1.isToken() && Sz1.getToken().startswith(".f") &&
-              Sz2.isToken() && Sz2.getToken().startswith(".f"))) {
+          if (!(Sz1.isToken() && Sz1.getToken().starts_with(".f") &&
+                Sz2.isToken() && Sz2.getToken().starts_with(".f"))) {
             Operands.erase(Operands.begin());
             SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
             VPTPredicationCode = ARMVCC::Then;
@@ -12798,12 +12787,12 @@ bool ARMAsmParser::isMnemonicVPTPredicable(StringRef Mnemonic,
     return false;
 
   if (MS.isVPTPredicableCDEInstr(Mnemonic) ||
-      (Mnemonic.startswith("vldrh") && Mnemonic != "vldrhi") ||
-      (Mnemonic.startswith("vmov") &&
+      (Mnemonic.starts_with("vldrh") && Mnemonic != "vldrhi") ||
+      (Mnemonic.starts_with("vmov") &&
        !(ExtraToken == ".f16" || ExtraToken == ".32" || ExtraToken == ".16" ||
          ExtraToken == ".8")) ||
-      (Mnemonic.startswith("vrint") && Mnemonic != "vrintr") ||
-      (Mnemonic.startswith("vstrh") && Mnemonic != "vstrhi"))
+      (Mnemonic.starts_with("vrint") && Mnemonic != "vrintr") ||
+      (Mnemonic.starts_with("vstrh") && Mnemonic != "vstrhi"))
     return true;
 
   const char *predicable_prefixes[] = {
@@ -12833,5 +12822,5 @@ bool ARMAsmParser::isMnemonicVPTPredicable(StringRef Mnemonic,
 
   return std::any_of(
       std::begin(predicable_prefixes), std::end(predicable_prefixes),
-      [&Mnemonic](const char *prefix) { return Mnemonic.startswith(prefix); });
+      [&Mnemonic](const char *prefix) { return Mnemonic.starts_with(prefix); });
 }
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
index e84b597e4382..1237e50c22fd 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
@@ -177,7 +177,7 @@ void ARMTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
   switchVendor("aeabi");
 
   const StringRef CPUString = STI.getCPU();
-  if (!CPUString.empty() && !CPUString.startswith("generic")) {
+  if (!CPUString.empty() && !CPUString.starts_with("generic")) {
     // FIXME: remove krait check when GNU tools support krait cpu
     if (STI.hasFeature(ARM::ProcKrait)) {
       emitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a9");
diff --git a/llvm/lib/Target/AVR/AVRAsmPrinter.cpp b/llvm/lib/Target/AVR/AVRAsmPrinter.cpp
index abe5dcc48340..1c8213b668f7 100644
--- a/llvm/lib/Target/AVR/AVRAsmPrinter.cpp
+++ b/llvm/lib/Target/AVR/AVRAsmPrinter.cpp
@@ -251,13 +251,13 @@ bool AVRAsmPrinter::doFinalization(Module &M) {
     }
 
     auto *Section = cast<MCSectionELF>(TLOF.SectionForGlobal(&GO, TM));
-    if (Section->getName().startswith(".data"))
+    if (Section->getName().starts_with(".data"))
       NeedsCopyData = true;
-    else if (Section->getName().startswith(".rodata") && SubTM->hasLPM())
+    else if (Section->getName().starts_with(".rodata") && SubTM->hasLPM())
       // AVRs that have a separate program memory (that's most AVRs) store
       // .rodata sections in RAM.
       NeedsCopyData = true;
-    else if (Section->getName().startswith(".bss"))
+    else if (Section->getName().starts_with(".bss"))
       NeedsClearBSS = true;
   }
 
diff --git a/llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp b/llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp
index 9634c16a30dc..f2d1206d0231 100644
--- a/llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp
+++ b/llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp
@@ -338,7 +338,7 @@ bool BPFAbstractMemberAccess::IsPreserveDIAccessIndexCall(const CallInst *Call,
   const auto *GV = dyn_cast<GlobalValue>(Call->getCalledOperand());
   if (!GV)
     return false;
-  if (GV->getName().startswith("llvm.preserve.array.access.index")) {
+  if (GV->getName().starts_with("llvm.preserve.array.access.index")) {
     CInfo.Kind = BPFPreserveArrayAI;
     CInfo.Metadata = Call->getMetadata(LLVMContext::MD_preserve_access_index);
     if (!CInfo.Metadata)
@@ -348,7 +348,7 @@ bool BPFAbstractMemberAccess::IsPreserveDIAccessIndexCall(const CallInst *Call,
     CInfo.RecordAlignment = DL->getABITypeAlign(getBaseElementType(Call));
     return true;
   }
-  if (GV->getName().startswith("llvm.preserve.union.access.index")) {
+  if (GV->getName().starts_with("llvm.preserve.union.access.index")) {
     CInfo.Kind = BPFPreserveUnionAI;
     CInfo.Metadata = Call->getMetadata(LLVMContext::MD_preserve_access_index);
     if (!CInfo.Metadata)
@@ -358,7 +358,7 @@ bool BPFAbstractMemberAccess::IsPreserveDIAccessIndexCall(const CallInst *Call,
     CInfo.Base = Call->getArgOperand(0);
     return true;
   }
-  if (GV->getName().startswith("llvm.preserve.struct.access.index")) {
+  if (GV->getName().starts_with("llvm.preserve.struct.access.index")) {
     CInfo.Kind = BPFPreserveStructAI;
     CInfo.Metadata = Call->getMetadata(LLVMContext::MD_preserve_access_index);
     if (!CInfo.Metadata)
@@ -369,7 +369,7 @@ bool BPFAbstractMemberAccess::IsPreserveDIAccessIndexCall(const CallInst *Call,
     CInfo.RecordAlignment = DL->getABITypeAlign(getBaseElementType(Call));
     return true;
   }
-  if (GV->getName().startswith("llvm.bpf.preserve.field.info")) {
+  if (GV->getName().starts_with("llvm.bpf.preserve.field.info")) {
     CInfo.Kind = BPFPreserveFieldInfoAI;
     CInfo.Metadata = nullptr;
     // Check validity of info_kind as clang did not check this.
@@ -379,7 +379,7 @@ bool BPFAbstractMemberAccess::IsPreserveDIAccessIndexCall(const CallInst *Call,
     CInfo.AccessIndex = InfoKind;
     return true;
   }
-  if (GV->getName().startswith("llvm.bpf.preserve.type.info")) {
+  if (GV->getName().starts_with("llvm.bpf.preserve.type.info")) {
     CInfo.Kind = BPFPreserveFieldInfoAI;
     CInfo.Metadata = Call->getMetadata(LLVMContext::MD_preserve_access_index);
     if (!CInfo.Metadata)
@@ -395,7 +395,7 @@ bool BPFAbstractMemberAccess::IsPreserveDIAccessIndexCall(const CallInst *Call,
       CInfo.AccessIndex = BTF::TYPE_SIZE;
     return true;
   }
-  if (GV->getName().startswith("llvm.bpf.preserve.enum.value")) {
+  if (GV->getName().starts_with("llvm.bpf.preserve.enum.value")) {
     CInfo.Kind = BPFPreserveFieldInfoAI;
     CInfo.Metadata = Call->getMetadata(LLVMContext::MD_preserve_access_index);
     if (!CInfo.Metadata)
diff --git a/llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp b/llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp
index 56c89f61b319..81effc9b1db4 100644
--- a/llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp
+++ b/llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp
@@ -119,7 +119,7 @@ bool BPFCheckAndAdjustIR::removePassThroughBuiltin(Module &M) {
         auto *GV = dyn_cast<GlobalValue>(Call->getCalledOperand());
         if (!GV)
           continue;
-        if (!GV->getName().startswith("llvm.bpf.passthrough"))
+        if (!GV->getName().starts_with("llvm.bpf.passthrough"))
           continue;
         Changed = true;
         Value *Arg = Call->getArgOperand(1);
@@ -149,7 +149,7 @@ bool BPFCheckAndAdjustIR::removeCompareBuiltin(Module &M) {
         auto *GV = dyn_cast<GlobalValue>(Call->getCalledOperand());
         if (!GV)
           continue;
-        if (!GV->getName().startswith("llvm.bpf.compare"))
+        if (!GV->getName().starts_with("llvm.bpf.compare"))
           continue;
 
         Changed = true;
diff --git a/llvm/lib/Target/BPF/BPFPreserveDIType.cpp b/llvm/lib/Target/BPF/BPFPreserveDIType.cpp
index fc4fb4d8f800..dae1aeea3521 100644
--- a/llvm/lib/Target/BPF/BPFPreserveDIType.cpp
+++ b/llvm/lib/Target/BPF/BPFPreserveDIType.cpp
@@ -57,7 +57,7 @@ static bool BPFPreserveDITypeImpl(Function &F) {
       if (!GV)
         continue;
 
-      if (GV->getName().startswith("llvm.bpf.btf.type.id")) {
+      if (GV->getName().starts_with("llvm.bpf.btf.type.id")) {
         if (!Call->getMetadata(LLVMContext::MD_preserve_access_index))
           report_fatal_error(
               "Missing metadata for llvm.bpf.btf.type.id intrinsic");
diff --git a/llvm/lib/Target/BPF/BTFDebug.cpp b/llvm/lib/Target/BPF/BTFDebug.cpp
index f91ce7f25035..ebd8447eba85 100644
--- a/llvm/lib/Target/BPF/BTFDebug.cpp
+++ b/llvm/lib/Target/BPF/BTFDebug.cpp
@@ -977,7 +977,7 @@ std::string BTFDebug::populateFileContent(const DISubprogram *SP) {
   auto File = SP->getFile();
   std::string FileName;
 
-  if (!File->getFilename().startswith("/") && File->getDirectory().size())
+  if (!File->getFilename().starts_with("/") && File->getDirectory().size())
     FileName = File->getDirectory().str() + "/" + File->getFilename().str();
   else
     FileName = std::string(File->getFilename());
@@ -1417,7 +1417,7 @@ void BTFDebug::processGlobals(bool ProcessingMapDef) {
       SecName = Sec->getName();
     }
 
-    if (ProcessingMapDef != SecName.startswith(".maps"))
+    if (ProcessingMapDef != SecName.starts_with(".maps"))
       continue;
 
     // Create a .rodata datasec if the global variable is an initialized
@@ -1443,7 +1443,7 @@ void BTFDebug::processGlobals(bool ProcessingMapDef) {
     DIGlobalVariable *DIGlobal = nullptr;
     for (auto *GVE : GVs) {
       DIGlobal = GVE->getVariable();
-      if (SecName.startswith(".maps"))
+      if (SecName.starts_with(".maps"))
         visitMapDefType(DIGlobal->getType(), GVTypeId);
       else
         visitTypeEntry(DIGlobal->getType(), GVTypeId, false, false);
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
index e1ad15bbc7c1..4df811f188df 100644
--- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
@@ -116,13 +116,13 @@ HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
   if (!llvm::count_if(Features.getFeatures(), IsQFloatFS)) {
     auto getHvxVersion = [&Features](StringRef FS) -> StringRef {
       for (StringRef F : llvm::reverse(Features.getFeatures())) {
-        if (F.startswith("+hvxv"))
+        if (F.starts_with("+hvxv"))
           return F;
       }
       for (StringRef F : llvm::reverse(Features.getFeatures())) {
         if (F == "-hvx")
           return StringRef();
-        if (F.startswith("+hvx") || F == "-hvx")
+        if (F.starts_with("+hvx") || F == "-hvx")
           return F.take_front(4);  // Return "+hvx" or "-hvx".
       }
       return StringRef();
@@ -130,7 +130,7 @@ HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
 
     bool AddQFloat = false;
     StringRef HvxVer = getHvxVersion(FS);
-    if (HvxVer.startswith("+hvxv")) {
+    if (HvxVer.starts_with("+hvxv")) {
       int Ver = 0;
       if (!HvxVer.drop_front(5).consumeInteger(10, Ver) && Ver >= 68)
         AddQFloat = true;
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp b/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
index 8355de4cfe96..a7ac24e25a5f 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
@@ -140,7 +140,7 @@ MCSection *HexagonTargetObjectFile::SelectSectionForGlobal(
 
   // If the lookup table is used by more than one function, do not place
   // it in text section.
-  if (EmitLutInText && GO->getName().startswith("switch.table")) {
+  if (EmitLutInText && GO->getName().starts_with("switch.table")) {
     if (const Function *Fn = getLutUsedFunction(GO))
       return selectSectionForLookupTable(GO, TM, Fn);
   }
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
index cf6fa78a2005..fffd5abd9f8b 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
@@ -253,7 +253,7 @@ public:
       if (!Duplex.second.empty()) {
         OS << Indent << Duplex.first << Separator;
         InstTxt = Duplex.second;
-      } else if (!HeadTail.first.trim().startswith("immext")) {
+      } else if (!HeadTail.first.trim().starts_with("immext")) {
         InstTxt = Duplex.first;
       }
       if (!InstTxt.empty())
diff --git a/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp b/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
index cf6f7800a441..d0a89ad72b4c 100644
--- a/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
+++ b/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
@@ -1048,15 +1048,15 @@ StringRef LanaiAsmParser::splitMnemonic(StringRef Name, SMLoc NameLoc,
   StringRef Mnemonic = Name;
 
   bool IsBRR = false;
-  if (Name.endswith(".r")) {
+  if (Name.ends_with(".r")) {
     Mnemonic = Name.substr(0, Name.size() - 2);
     IsBRR = true;
   }
 
   // Match b?? and s?? (BR, BRR, and SCC instruction classes).
   if (Mnemonic[0] == 'b' ||
-      (Mnemonic[0] == 's' && !Mnemonic.startswith("sel") &&
-       !Mnemonic.startswith("st"))) {
+      (Mnemonic[0] == 's' && !Mnemonic.starts_with("sel") &&
+       !Mnemonic.starts_with("st"))) {
     // Parse instructions with a conditional code. For example, 'bne' is
     // converted into two operands 'b' and 'ne'.
     LPCC::CondCode CondCode =
@@ -1077,8 +1077,8 @@ StringRef LanaiAsmParser::splitMnemonic(StringRef Name, SMLoc NameLoc,
   // We ignore .f here and assume they are flag-setting operations, not
   // conditional codes (except for select instructions where flag-setting
   // variants are not yet implemented).
-  if (Mnemonic.startswith("sel") ||
-      (!Mnemonic.endswith(".f") && !Mnemonic.startswith("st"))) {
+  if (Mnemonic.starts_with("sel") ||
+      (!Mnemonic.ends_with(".f") && !Mnemonic.starts_with("st"))) {
     LPCC::CondCode CondCode = LPCC::suffixToLanaiCondCode(Mnemonic);
     if (CondCode != LPCC::UNKNOWN) {
       size_t Next = Mnemonic.rfind('.', Name.size());
@@ -1087,7 +1087,7 @@ StringRef LanaiAsmParser::splitMnemonic(StringRef Name, SMLoc NameLoc,
       // expected by the generated matcher). If the mnemonic starts with 'sel'
       // then include the period as part of the mnemonic, else don't include it
       // as part of the mnemonic.
-      if (Mnemonic.startswith("sel")) {
+      if (Mnemonic.starts_with("sel")) {
         Mnemonic = Mnemonic.substr(0, Next + 1);
       } else {
         Mnemonic = Mnemonic.substr(0, Next);
@@ -1194,7 +1194,7 @@ bool LanaiAsmParser::ParseInstruction(ParseInstructionInfo & /*Info*/,
   // If the instruction is a bt instruction with 1 operand (in assembly) then it
   // is an unconditional branch instruction and the first two elements of
   // operands need to be merged.
-  if (Lexer.is(AsmToken::EndOfStatement) && Name.startswith("bt") &&
+  if (Lexer.is(AsmToken::EndOfStatement) && Name.starts_with("bt") &&
       Operands.size() == 3) {
     Operands.erase(Operands.begin(), Operands.begin() + 2);
     Operands.insert(Operands.begin(), LanaiOperand::CreateToken("bt", NameLoc));
diff --git a/llvm/lib/Target/Lanai/LanaiTargetObjectFile.cpp b/llvm/lib/Target/Lanai/LanaiTargetObjectFile.cpp
index a421f3156153..a366a89af863 100644
--- a/llvm/lib/Target/Lanai/LanaiTargetObjectFile.cpp
+++ b/llvm/lib/Target/Lanai/LanaiTargetObjectFile.cpp
@@ -80,7 +80,7 @@ bool LanaiTargetObjectFile::isGlobalInSmallSectionImpl(
   // Global values placed in sections starting with .ldata do not fit in
   // 21-bits, so always use large memory access for them. FIXME: This is a
   // workaround for a tool limitation.
-  if (GVA->getSection().startswith(".ldata"))
+  if (GVA->getSection().starts_with(".ldata"))
     return false;
 
   if (TM.getCodeModel() == CodeModel::Small)
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 61ec63ff6c1c..4794a131edae 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -4665,8 +4665,8 @@ LoongArchTargetLowering::getRegForInlineAsmConstraint(
   // decode the usage of register name aliases into their official names. And
   // AFAIK, the not yet upstreamed `rustc` for LoongArch will always use
   // official register names.
-  if (Constraint.startswith("{$r") || Constraint.startswith("{$f") ||
-      Constraint.startswith("{$vr") || Constraint.startswith("{$xr")) {
+  if (Constraint.starts_with("{$r") || Constraint.starts_with("{$f") ||
+      Constraint.starts_with("{$vr") || Constraint.starts_with("{$xr")) {
     bool IsFP = Constraint[2] == 'f';
     std::pair<StringRef, StringRef> Temp = Constraint.split('$');
     std::pair<unsigned, const TargetRegisterClass *> R;
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 60075c819b29..3c673ae938fd 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -6249,7 +6249,7 @@ int MipsAsmParser::matchFPURegisterName(StringRef Name) {
 }
 
 int MipsAsmParser::matchFCCRegisterName(StringRef Name) {
-  if (Name.startswith("fcc")) {
+  if (Name.starts_with("fcc")) {
     StringRef NumString = Name.substr(3);
     unsigned IntVal;
     if (NumString.getAsInteger(10, IntVal))
@@ -6262,7 +6262,7 @@ int MipsAsmParser::matchFCCRegisterName(StringRef Name) {
 }
 
 int MipsAsmParser::matchACRegisterName(StringRef Name) {
-  if (Name.startswith("ac")) {
+  if (Name.starts_with("ac")) {
     StringRef NumString = Name.substr(2);
     unsigned IntVal;
     if (NumString.getAsInteger(10, IntVal))
@@ -6567,7 +6567,7 @@ bool MipsAsmParser::searchSymbolAlias(OperandVector &Operands) {
     if (Expr->getKind() == MCExpr::SymbolRef) {
       const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr *>(Expr);
       StringRef DefSymbol = Ref->getSymbol().getName();
-      if (DefSymbol.startswith("$")) {
+      if (DefSymbol.starts_with("$")) {
         ParseStatus Res =
             matchAnyRegisterNameWithoutDollar(Operands, DefSymbol.substr(1), S);
         if (Res.isSuccess()) {
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
index 81c1ccec7bed..94e3d28a4186 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
@@ -56,11 +56,11 @@ unsigned MipsABIInfo::GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const {
 
 MipsABIInfo MipsABIInfo::computeTargetABI(const Triple &TT, StringRef CPU,
                                           const MCTargetOptions &Options) {
-  if (Options.getABIName().startswith("o32"))
+  if (Options.getABIName().starts_with("o32"))
     return MipsABIInfo::O32();
-  if (Options.getABIName().startswith("n32"))
+  if (Options.getABIName().starts_with("n32"))
     return MipsABIInfo::N32();
-  if (Options.getABIName().startswith("n64"))
+  if (Options.getABIName().starts_with("n64"))
     return MipsABIInfo::N64();
   if (TT.getEnvironment() == llvm::Triple::GNUABIN32)
     return MipsABIInfo::N32();
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index f09d52aa5fd6..a0cab8024386 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -4064,7 +4064,7 @@ parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
     RC = TRI->getRegClass(Prefix == "hi" ?
                           Mips::HI32RegClassID : Mips::LO32RegClassID);
     return std::make_pair(*(RC->begin()), RC);
-  } else if (Prefix.startswith("$msa")) {
+  } else if (Prefix.starts_with("$msa")) {
     // Parse $msa(ir|csr|access|save|modify|request|map|unmap)
 
     // No numeric characters follow the name.
diff --git a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
index 5ced4129ee80..6a03c7b0abc3 100644
--- a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
@@ -1016,8 +1016,8 @@ void NVPTXAsmPrinter::printModuleLevelGV(const GlobalVariable *GVar,
   }
 
   // Skip LLVM intrinsic global variables
-  if (GVar->getName().startswith("llvm.") ||
-      GVar->getName().startswith("nvvm."))
+  if (GVar->getName().starts_with("llvm.") ||
+      GVar->getName().starts_with("nvvm."))
     return;
 
   const DataLayout &DL = getDataLayout();
diff --git a/llvm/lib/Target/NVPTX/NVPTXGenericToNVVM.cpp b/llvm/lib/Target/NVPTX/NVPTXGenericToNVVM.cpp
index 4f03e474edb4..3d6bd1d8ad06 100644
--- a/llvm/lib/Target/NVPTX/NVPTXGenericToNVVM.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXGenericToNVVM.cpp
@@ -62,7 +62,7 @@ bool GenericToNVVM::runOnModule(Module &M) {
   for (GlobalVariable &GV : llvm::make_early_inc_range(M.globals())) {
     if (GV.getType()->getAddressSpace() == llvm::ADDRESS_SPACE_GENERIC &&
         !llvm::isTexture(GV) && !llvm::isSurface(GV) && !llvm::isSampler(GV) &&
-        !GV.getName().startswith("llvm.")) {
+        !GV.getName().starts_with("llvm.")) {
       GlobalVariable *NewGV = new GlobalVariable(
           M, GV.getValueType(), GV.isConstant(), GV.getLinkage(),
           GV.hasInitializer() ? GV.getInitializer() : nullptr, "", &GV,
diff --git a/llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp b/llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
index 4bd820e98f05..85f75df39c0d 100644
--- a/llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
@@ -1812,7 +1812,7 @@ findIndexForHandle(MachineOperand &Op, MachineFunction &MF, unsigned &Idx) {
     StringRef Sym = TexHandleDef.getOperand(6).getSymbolName();
     std::string ParamBaseName = std::string(MF.getName());
     ParamBaseName += "_param_";
-    assert(Sym.startswith(ParamBaseName) && "Invalid symbol reference");
+    assert(Sym.starts_with(ParamBaseName) && "Invalid symbol reference");
     unsigned Param = atoi(Sym.data()+ParamBaseName.size());
     std::string NewSym;
     raw_string_ostream NewSymStr(NewSym);
diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
index a33f44542eb5..8108cfa521c8 100644
--- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
@@ -1744,7 +1744,7 @@ bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
     ParseDirectiveAbiVersion(DirectiveID.getLoc());
   else if (IDVal == ".localentry")
     ParseDirectiveLocalEntry(DirectiveID.getLoc());
-  else if (IDVal.startswith(".gnu_attribute"))
+  else if (IDVal.starts_with(".gnu_attribute"))
     ParseGNUAttribute(DirectiveID.getLoc());
   else
     return true;
diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
index 4b551bc51c4f..780b22b4fbe6 100644
--- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -2519,7 +2519,7 @@ void PPCAIXAsmPrinter::emitGlobalVariable(const GlobalVariable *GV) {
 }
 
 void PPCAIXAsmPrinter::emitGlobalVariableHelper(const GlobalVariable *GV) {
-  assert(!GV->getName().startswith("llvm.") &&
+  assert(!GV->getName().starts_with("llvm.") &&
          "Unhandled intrinsic global variable.");
 
   if (GV->hasComdat())
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
index b09975172bf5..d676fa86a10e 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -242,9 +242,9 @@ static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
 
 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
                                                  const TargetOptions &Options) {
-  if (Options.MCOptions.getABIName().startswith("elfv1"))
+  if (Options.MCOptions.getABIName().starts_with("elfv1"))
     return PPCTargetMachine::PPC_ABI_ELFv1;
-  else if (Options.MCOptions.getABIName().startswith("elfv2"))
+  else if (Options.MCOptions.getABIName().starts_with("elfv2"))
     return PPCTargetMachine::PPC_ABI_ELFv2;
 
   assert(Options.MCOptions.getABIName().empty() &&
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 138134d00f64..f3ea0f597eec 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -286,11 +286,11 @@ public:
     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
 
     auto ABIName = StringRef(Options.ABIName);
-    if (ABIName.endswith("f") && !getSTI().hasFeature(RISCV::FeatureStdExtF)) {
+    if (ABIName.ends_with("f") && !getSTI().hasFeature(RISCV::FeatureStdExtF)) {
       errs() << "Hard-float 'f' ABI can't be used for a target that "
                 "doesn't support the F instruction set extension (ignoring "
                 "target-abi)\n";
-    } else if (ABIName.endswith("d") &&
+    } else if (ABIName.ends_with("d") &&
                !getSTI().hasFeature(RISCV::FeatureStdExtD)) {
       errs() << "Hard-float 'd' ABI can't be used for a target that "
                 "doesn't support the D instruction set extension (ignoring "
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
index edcca8805dfc..66a46a485f53 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
@@ -47,11 +47,11 @@ ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
     errs()
         << "'" << ABIName
         << "' is not a recognized ABI for this target (ignoring target-abi)\n";
-  } else if (ABIName.startswith("ilp32") && IsRV64) {
+  } else if (ABIName.starts_with("ilp32") && IsRV64) {
     errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring "
               "target-abi)\n";
     TargetABI = ABI_Unknown;
-  } else if (ABIName.startswith("lp64") && !IsRV64) {
+  } else if (ABIName.starts_with("lp64") && !IsRV64) {
     errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring "
               "target-abi)\n";
     TargetABI = ABI_Unknown;
diff --git a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
index c16004e2fea2..a58e8e0dfedf 100644
--- a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
+++ b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
@@ -1203,7 +1203,7 @@ ParseStatus SystemZAsmParser::parseDirective(AsmToken DirectiveID) {
     return ParseDirectiveInsn(DirectiveID.getLoc());
   if (IDVal == ".machine")
     return ParseDirectiveMachine(DirectiveID.getLoc());
-  if (IDVal.startswith(".gnu_attribute"))
+  if (IDVal.starts_with(".gnu_attribute"))
     return ParseGNUAttribute(DirectiveID.getLoc());
 
   return ParseStatus::NoMatch;
diff --git a/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp b/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
index 19dd6c83b750..21d5f7653a68 100644
--- a/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
+++ b/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
@@ -923,31 +923,35 @@ StringRef VEAsmParser::splitMnemonic(StringRef Name, SMLoc NameLoc,
         (Name[Next + 1] == 'd' || Name[Next + 1] == 's'))
       ICC = false;
     Mnemonic = parseCC(Name, Start, Next, ICC, true, NameLoc, Operands);
-  } else if (Name.startswith("cmov.l.") || Name.startswith("cmov.w.") ||
-             Name.startswith("cmov.d.") || Name.startswith("cmov.s.")) {
+  } else if (Name.starts_with("cmov.l.") || Name.starts_with("cmov.w.") ||
+             Name.starts_with("cmov.d.") || Name.starts_with("cmov.s.")) {
     bool ICC = Name[5] == 'l' || Name[5] == 'w';
     Mnemonic = parseCC(Name, 7, Name.size(), ICC, false, NameLoc, Operands);
-  } else if (Name.startswith("cvt.w.d.sx") || Name.startswith("cvt.w.d.zx") ||
-             Name.startswith("cvt.w.s.sx") || Name.startswith("cvt.w.s.zx")) {
+  } else if (Name.starts_with("cvt.w.d.sx") || Name.starts_with("cvt.w.d.zx") ||
+             Name.starts_with("cvt.w.s.sx") || Name.starts_with("cvt.w.s.zx")) {
     Mnemonic = parseRD(Name, 10, NameLoc, Operands);
-  } else if (Name.startswith("cvt.l.d")) {
+  } else if (Name.starts_with("cvt.l.d")) {
     Mnemonic = parseRD(Name, 7, NameLoc, Operands);
-  } else if (Name.startswith("vcvt.w.d.sx") || Name.startswith("vcvt.w.d.zx") ||
-             Name.startswith("vcvt.w.s.sx") || Name.startswith("vcvt.w.s.zx")) {
+  } else if (Name.starts_with("vcvt.w.d.sx") ||
+             Name.starts_with("vcvt.w.d.zx") ||
+             Name.starts_with("vcvt.w.s.sx") ||
+             Name.starts_with("vcvt.w.s.zx")) {
     Mnemonic = parseRD(Name, 11, NameLoc, Operands);
-  } else if (Name.startswith("vcvt.l.d")) {
+  } else if (Name.starts_with("vcvt.l.d")) {
     Mnemonic = parseRD(Name, 8, NameLoc, Operands);
-  } else if (Name.startswith("pvcvt.w.s.lo") ||
-             Name.startswith("pvcvt.w.s.up")) {
+  } else if (Name.starts_with("pvcvt.w.s.lo") ||
+             Name.starts_with("pvcvt.w.s.up")) {
     Mnemonic = parseRD(Name, 12, NameLoc, Operands);
-  } else if (Name.startswith("pvcvt.w.s")) {
+  } else if (Name.starts_with("pvcvt.w.s")) {
     Mnemonic = parseRD(Name, 9, NameLoc, Operands);
-  } else if (Name.startswith("vfmk.l.") || Name.startswith("vfmk.w.") ||
-             Name.startswith("vfmk.d.") || Name.startswith("vfmk.s.")) {
+  } else if (Name.starts_with("vfmk.l.") || Name.starts_with("vfmk.w.") ||
+             Name.starts_with("vfmk.d.") || Name.starts_with("vfmk.s.")) {
     bool ICC = Name[5] == 'l' || Name[5] == 'w' ? true : false;
     Mnemonic = parseCC(Name, 7, Name.size(), ICC, true, NameLoc, Operands);
-  } else if (Name.startswith("pvfmk.w.lo.") || Name.startswith("pvfmk.w.up.") ||
-             Name.startswith("pvfmk.s.lo.") || Name.startswith("pvfmk.s.up.")) {
+  } else if (Name.starts_with("pvfmk.w.lo.") ||
+             Name.starts_with("pvfmk.w.up.") ||
+             Name.starts_with("pvfmk.s.lo.") ||
+             Name.starts_with("pvfmk.s.up.")) {
     bool ICC = Name[6] == 'l' || Name[6] == 'w' ? true : false;
     Mnemonic = parseCC(Name, 11, Name.size(), ICC, true, NameLoc, Operands);
   } else {
diff --git a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
index b70fa957a859..1b92997f03f1 100644
--- a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
+++ b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
@@ -1103,7 +1103,7 @@ public:
     // object writer expects each function to have its own section. This way
     // The user can't forget this "convention".
     auto SymName = Symbol->getName();
-    if (SymName.startswith(".L"))
+    if (SymName.starts_with(".L"))
       return; // Local Symbol.
 
     // TODO: If the user explicitly creates a new function section, we ignore
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
index 2c1ec21ba17d..908efbb8d321 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
@@ -104,7 +104,7 @@ WebAssemblyTargetStreamer *WebAssemblyAsmPrinter::getTargetStreamer() {
 static bool isEmscriptenInvokeName(StringRef Name) {
   if (Name.front() == '"' && Name.back() == '"')
     Name = Name.substr(1, Name.size() - 2);
-  return Name.startswith("__invoke_");
+  return Name.starts_with("__invoke_");
 }
 
 // Returns a character that represents the given wasm value type in invoke
@@ -235,7 +235,7 @@ MCSymbol *WebAssemblyAsmPrinter::getOrCreateWasmSymbol(StringRef Name) {
     return WasmSym;
   }
 
-  if (Name.startswith("GCC_except_table")) {
+  if (Name.starts_with("GCC_except_table")) {
     WasmSym->setType(wasm::WASM_SYMBOL_TYPE_DATA);
     return WasmSym;
   }
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
index 5e84fff351b2..77e6640d5a82 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
@@ -623,7 +623,7 @@ static bool canLongjmp(const Value *Callee) {
     return false;
 
   // __cxa_find_matching_catch_N functions cannot longjmp
-  if (Callee->getName().startswith("__cxa_find_matching_catch_"))
+  if (Callee->getName().starts_with("__cxa_find_matching_catch_"))
     return false;
 
   // Exception-catching related functions
@@ -1517,7 +1517,7 @@ void WebAssemblyLowerEmscriptenEHSjLj::handleLongjmpableCallsForEmscriptenSjLj(
 
       Value *Threw = nullptr;
       BasicBlock *Tail;
-      if (Callee->getName().startswith("__invoke_")) {
+      if (Callee->getName().starts_with("__invoke_")) {
         // If invoke wrapper has already been generated for this call in
         // previous EH phase, search for the load instruction
         // %__THREW__.val = __THREW__;
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 32ede8558efe..e78d16056460 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1417,7 +1417,7 @@ bool X86AsmParser::MatchRegisterByName(MCRegister &RegNo, StringRef RegName,
 
   // If this is "db[0-15]", match it as an alias
   // for dr[0-15].
-  if (RegNo == 0 && RegName.startswith("db")) {
+  if (RegNo == 0 && RegName.starts_with("db")) {
     if (RegName.size() == 3) {
       switch (RegName[2]) {
       case '0':
@@ -2072,7 +2072,7 @@ bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
           Lex(); // eat type
           bool EndDot = parseOptionalToken(AsmToken::Dot);
           while (EndDot || (getTok().is(AsmToken::Identifier) &&
-                            getTok().getString().startswith("."))) {
+                            getTok().getString().starts_with("."))) {
             getParser().parseIdentifier(Identifier);
             if (!EndDot)
               Identifier.consume_front(".");
@@ -2271,7 +2271,7 @@ bool X86AsmParser::ParseRoundingModeOp(SMLoc Start, OperandVector &Operands) {
   const SMLoc consumedToken = consumeToken();
   if (Tok.isNot(AsmToken::Identifier))
     return Error(Tok.getLoc(), "Expected an identifier after {");
-  if (Tok.getIdentifier().startswith("r")){
+  if (Tok.getIdentifier().starts_with("r")) {
     int rndMode = StringSwitch<int>(Tok.getIdentifier())
       .Case("rn", X86::STATIC_ROUNDING::TO_NEAREST_INT)
       .Case("rd", X86::STATIC_ROUNDING::TO_NEG_INF)
@@ -2313,7 +2313,7 @@ bool X86AsmParser::ParseIntelDotOperator(IntelExprStateMachine &SM,
 
   // Drop the optional '.'.
   StringRef DotDispStr = Tok.getString();
-  if (DotDispStr.startswith("."))
+  if (DotDispStr.starts_with("."))
     DotDispStr = DotDispStr.drop_front(1);
   StringRef TrailingDot;
 
@@ -2325,7 +2325,7 @@ bool X86AsmParser::ParseIntelDotOperator(IntelExprStateMachine &SM,
     Info.Offset = DotDisp.getZExtValue();
   } else if ((isParsingMSInlineAsm() || getParser().isParsingMasm()) &&
              Tok.is(AsmToken::Identifier)) {
-    if (DotDispStr.endswith(".")) {
+    if (DotDispStr.ends_with(".")) {
       TrailingDot = DotDispStr.substr(DotDispStr.size() - 1);
       DotDispStr = DotDispStr.drop_back(1);
     }
@@ -2815,7 +2815,7 @@ bool X86AsmParser::HandleAVX512Operand(OperandVector &Operands) {
       SmallVector<char, 5> BroadcastVector;
       StringRef BroadcastString = (Prefix + getLexer().getTok().getIdentifier())
                                       .toStringRef(BroadcastVector);
-      if (!BroadcastString.startswith("1to"))
+      if (!BroadcastString.starts_with("1to"))
         return TokError("Expected 1to<NUM> at this point");
       const char *BroadcastPrimitive =
           StringSwitch<const char *>(BroadcastString)
@@ -3174,7 +3174,7 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
   if (isParsingIntelSyntax() &&
       (PatchedName == "jmp" || PatchedName == "jc" || PatchedName == "jnc" ||
        PatchedName == "jcxz" || PatchedName == "jecxz" ||
-       (PatchedName.startswith("j") &&
+       (PatchedName.starts_with("j") &&
         ParseConditionCode(PatchedName.substr(1)) != X86::COND_INVALID))) {
     StringRef NextTok = Parser.getTok().getString();
     if (Parser.isParsingMasm() ? NextTok.equals_insensitive("short")
@@ -3192,17 +3192,17 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
   }
 
   // FIXME: Hack to recognize setneb as setne.
-  if (PatchedName.startswith("set") && PatchedName.endswith("b") &&
+  if (PatchedName.starts_with("set") && PatchedName.ends_with("b") &&
       PatchedName != "setb" && PatchedName != "setnb")
     PatchedName = PatchedName.substr(0, Name.size()-1);
 
   unsigned ComparisonPredicate = ~0U;
 
   // FIXME: Hack to recognize cmp<comparison code>{sh,ss,sd,ph,ps,pd}.
-  if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
-      (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
-       PatchedName.endswith("sh") || PatchedName.endswith("ph") ||
-       PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
+  if ((PatchedName.starts_with("cmp") || PatchedName.starts_with("vcmp")) &&
+      (PatchedName.ends_with("ss") || PatchedName.ends_with("sd") ||
+       PatchedName.ends_with("sh") || PatchedName.ends_with("ph") ||
+       PatchedName.ends_with("ps") || PatchedName.ends_with("pd"))) {
     bool IsVCMP = PatchedName[0] == 'v';
     unsigned CCIdx = IsVCMP ? 4 : 3;
     unsigned CC = StringSwitch<unsigned>(
@@ -3257,17 +3257,17 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
       .Default(~0U);
     if (CC != ~0U && (IsVCMP || CC < 8) &&
         (IsVCMP || PatchedName.back() != 'h')) {
-      if (PatchedName.endswith("ss"))
+      if (PatchedName.ends_with("ss"))
         PatchedName = IsVCMP ? "vcmpss" : "cmpss";
-      else if (PatchedName.endswith("sd"))
+      else if (PatchedName.ends_with("sd"))
         PatchedName = IsVCMP ? "vcmpsd" : "cmpsd";
-      else if (PatchedName.endswith("ps"))
+      else if (PatchedName.ends_with("ps"))
         PatchedName = IsVCMP ? "vcmpps" : "cmpps";
-      else if (PatchedName.endswith("pd"))
+      else if (PatchedName.ends_with("pd"))
         PatchedName = IsVCMP ? "vcmppd" : "cmppd";
-      else if (PatchedName.endswith("sh"))
+      else if (PatchedName.ends_with("sh"))
         PatchedName = "vcmpsh";
-      else if (PatchedName.endswith("ph"))
+      else if (PatchedName.ends_with("ph"))
         PatchedName = "vcmpph";
       else
         llvm_unreachable("Unexpected suffix!");
@@ -3277,7 +3277,7 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
   }
 
   // FIXME: Hack to recognize vpcmp<comparison code>{ub,uw,ud,uq,b,w,d,q}.
-  if (PatchedName.startswith("vpcmp") &&
+  if (PatchedName.starts_with("vpcmp") &&
       (PatchedName.back() == 'b' || PatchedName.back() == 'w' ||
        PatchedName.back() == 'd' || PatchedName.back() == 'q')) {
     unsigned SuffixSize = PatchedName.drop_back().back() == 'u' ? 2 : 1;
@@ -3306,7 +3306,7 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
   }
 
   // FIXME: Hack to recognize vpcom<comparison code>{ub,uw,ud,uq,b,w,d,q}.
-  if (PatchedName.startswith("vpcom") &&
+  if (PatchedName.starts_with("vpcom") &&
       (PatchedName.back() == 'b' || PatchedName.back() == 'w' ||
        PatchedName.back() == 'd' || PatchedName.back() == 'q')) {
     unsigned SuffixSize = PatchedName.drop_back().back() == 'u' ? 2 : 1;
@@ -3334,7 +3334,6 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
     }
   }
 
-
   // Determine whether this is an instruction prefix.
   // FIXME:
   // Enhance prefixes integrity robustness. for example, following forms
@@ -3380,9 +3379,9 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
     Parser.Lex(); // eat the prefix
     // Hack: we could have something like "rep # some comment" or
     //    "lock; cmpxchg16b $1" or "lock\0A\09incl" or "lock/incl"
-    while (Name.startswith(";") || Name.startswith("\n") ||
-           Name.startswith("#") || Name.startswith("\t") ||
-           Name.startswith("/")) {
+    while (Name.starts_with(";") || Name.starts_with("\n") ||
+           Name.starts_with("#") || Name.starts_with("\t") ||
+           Name.starts_with("/")) {
       // FIXME: The mnemonic won't match correctly if its not in lower case.
       Name = Parser.getTok().getString();
       Parser.Lex(); // go to next prefix or instr
@@ -3541,7 +3540,7 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
   bool HadVerifyError = false;
 
   // Append default arguments to "ins[bwld]"
-  if (Name.startswith("ins") &&
+  if (Name.starts_with("ins") &&
       (Operands.size() == 1 || Operands.size() == 3) &&
       (Name == "insb" || Name == "insw" || Name == "insl" || Name == "insd" ||
        Name == "ins")) {
@@ -3553,7 +3552,7 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
   }
 
   // Append default arguments to "outs[bwld]"
-  if (Name.startswith("outs") &&
+  if (Name.starts_with("outs") &&
       (Operands.size() == 1 || Operands.size() == 3) &&
       (Name == "outsb" || Name == "outsw" || Name == "outsl" ||
        Name == "outsd" || Name == "outs")) {
@@ -3565,7 +3564,7 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
   // Transform "lods[bwlq]" into "lods[bwlq] ($SIREG)" for appropriate
   // values of $SIREG according to the mode. It would be nice if this
   // could be achieved with InstAlias in the tables.
-  if (Name.startswith("lods") &&
+  if (Name.starts_with("lods") &&
       (Operands.size() == 1 || Operands.size() == 2) &&
       (Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
        Name == "lodsl" || Name == "lodsd" || Name == "lodsq")) {
@@ -3576,7 +3575,7 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
   // Transform "stos[bwlq]" into "stos[bwlq] ($DIREG)" for appropriate
   // values of $DIREG according to the mode. It would be nice if this
   // could be achieved with InstAlias in the tables.
-  if (Name.startswith("stos") &&
+  if (Name.starts_with("stos") &&
       (Operands.size() == 1 || Operands.size() == 2) &&
       (Name == "stos" || Name == "stosb" || Name == "stosw" ||
        Name == "stosl" || Name == "stosd" || Name == "stosq")) {
@@ -3587,7 +3586,7 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
   // Transform "scas[bwlq]" into "scas[bwlq] ($DIREG)" for appropriate
   // values of $DIREG according to the mode. It would be nice if this
   // could be achieved with InstAlias in the tables.
-  if (Name.startswith("scas") &&
+  if (Name.starts_with("scas") &&
       (Operands.size() == 1 || Operands.size() == 2) &&
       (Name == "scas" || Name == "scasb" || Name == "scasw" ||
        Name == "scasl" || Name == "scasd" || Name == "scasq")) {
@@ -3596,7 +3595,7 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
   }
 
   // Add default SI and DI operands to "cmps[bwlq]".
-  if (Name.startswith("cmps") &&
+  if (Name.starts_with("cmps") &&
       (Operands.size() == 1 || Operands.size() == 3) &&
       (Name == "cmps" || Name == "cmpsb" || Name == "cmpsw" ||
        Name == "cmpsl" || Name == "cmpsd" || Name == "cmpsq")) {
@@ -3606,10 +3605,10 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
   }
 
   // Add default SI and DI operands to "movs[bwlq]".
-  if (((Name.startswith("movs") &&
+  if (((Name.starts_with("movs") &&
         (Name == "movs" || Name == "movsb" || Name == "movsw" ||
          Name == "movsl" || Name == "movsd" || Name == "movsq")) ||
-       (Name.startswith("smov") &&
+       (Name.starts_with("smov") &&
         (Name == "smov" || Name == "smovb" || Name == "smovw" ||
          Name == "smovl" || Name == "smovd" || Name == "smovq"))) &&
       (Operands.size() == 1 || Operands.size() == 3)) {
@@ -4472,11 +4471,11 @@ bool X86AsmParser::OmitRegisterFromClobberLists(unsigned RegNo) {
 bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
   MCAsmParser &Parser = getParser();
   StringRef IDVal = DirectiveID.getIdentifier();
-  if (IDVal.startswith(".arch"))
+  if (IDVal.starts_with(".arch"))
     return parseDirectiveArch();
-  if (IDVal.startswith(".code"))
+  if (IDVal.starts_with(".code"))
     return ParseDirectiveCode(IDVal, DirectiveID.getLoc());
-  else if (IDVal.startswith(".att_syntax")) {
+  else if (IDVal.starts_with(".att_syntax")) {
     if (getLexer().isNot(AsmToken::EndOfStatement)) {
       if (Parser.getTok().getString() == "prefix")
         Parser.Lex();
@@ -4487,7 +4486,7 @@ bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
     }
     getParser().setAssemblerDialect(0);
     return false;
-  } else if (IDVal.startswith(".intel_syntax")) {
+  } else if (IDVal.starts_with(".intel_syntax")) {
     getParser().setAssemblerDialect(1);
     if (getLexer().isNot(AsmToken::EndOfStatement)) {
       if (Parser.getTok().getString() == "noprefix")
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
index 165e9207ef1c..ed4d0a45bd8f 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
@@ -399,8 +399,8 @@ MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT,
 
   size_t posNoEVEX512 = FS.rfind("-evex512");
   // Make sure we won't be cheated by "-avx512fp16".
-  size_t posNoAVX512F = FS.endswith("-avx512f") ? FS.size() - 8
-                                                : FS.rfind("-avx512f,");
+  size_t posNoAVX512F =
+      FS.ends_with("-avx512f") ? FS.size() - 8 : FS.rfind("-avx512f,");
   size_t posEVEX512 = FS.rfind("+evex512");
   size_t posAVX512F = FS.rfind("+avx512"); // Any AVX512XXX will enable AVX512F.
 
diff --git a/llvm/lib/Target/X86/X86InsertPrefetch.cpp b/llvm/lib/Target/X86/X86InsertPrefetch.cpp
index 3c9738be547f..3e11ab2d98a4 100644
--- a/llvm/lib/Target/X86/X86InsertPrefetch.cpp
+++ b/llvm/lib/Target/X86/X86InsertPrefetch.cpp
@@ -135,7 +135,7 @@ bool X86InsertPrefetch::findPrefetchInfo(const FunctionSamples *TopSamples,
       int64_t D = static_cast<int64_t>(S_V.second);
       unsigned IID = 0;
       for (const auto &HintType : HintTypes) {
-        if (Name.startswith(HintType.first)) {
+        if (Name.starts_with(HintType.first)) {
           Name = Name.drop_front(HintType.first.size());
           IID = HintType.second;
           break;
diff --git a/llvm/lib/Target/X86/X86Subtarget.cpp b/llvm/lib/Target/X86/X86Subtarget.cpp
index 328608363a8f..0f76daffd463 100644
--- a/llvm/lib/Target/X86/X86Subtarget.cpp
+++ b/llvm/lib/Target/X86/X86Subtarget.cpp
@@ -267,8 +267,8 @@ void X86Subtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU,
   if (CPU == "generic" || CPU == "pentium4" || CPU == "x86-64") {
     size_t posNoEVEX512 = FS.rfind("-evex512");
     // Make sure we won't be cheated by "-avx512fp16".
-    size_t posNoAVX512F = FS.endswith("-avx512f") ? FS.size() - 8
-                                                  : FS.rfind("-avx512f,");
+    size_t posNoAVX512F =
+        FS.ends_with("-avx512f") ? FS.size() - 8 : FS.rfind("-avx512f,");
     size_t posEVEX512 = FS.rfind("+evex512");
     // Any AVX512XXX will enable AVX512F.
     size_t posAVX512F = FS.rfind("+avx512");
diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.cpp b/llvm/lib/Target/XCore/XCoreISelLowering.cpp
index 80edad58985b..7736adab19e8 100644
--- a/llvm/lib/Target/XCore/XCoreISelLowering.cpp
+++ b/llvm/lib/Target/XCore/XCoreISelLowering.cpp
@@ -249,7 +249,7 @@ SDValue XCoreTargetLowering::getGlobalAddressWrapper(SDValue GA,
     return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA);
 
   const auto *GVar = dyn_cast<GlobalVariable>(GV);
-  if ((GV->hasSection() && GV->getSection().startswith(".cp.")) ||
+  if ((GV->hasSection() && GV->getSection().starts_with(".cp.")) ||
       (GVar && GVar->isConstant() && GV->hasLocalLinkage()))
     return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA);
 
diff --git a/llvm/lib/Target/XCore/XCoreTargetObjectFile.cpp b/llvm/lib/Target/XCore/XCoreTargetObjectFile.cpp
index 52a0a09d3ea5..ae697f43b0ee 100644
--- a/llvm/lib/Target/XCore/XCoreTargetObjectFile.cpp
+++ b/llvm/lib/Target/XCore/XCoreTargetObjectFile.cpp
@@ -98,7 +98,7 @@ MCSection *XCoreTargetObjectFile::getExplicitSectionGlobal(
     const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const {
   StringRef SectionName = GO->getSection();
   // Infer section flags from the section name if we can.
-  bool IsCPRel = SectionName.startswith(".cp.");
+  bool IsCPRel = SectionName.starts_with(".cp.");
   if (IsCPRel && !Kind.isReadOnly())
     report_fatal_error("Using .cp. section for writeable object.");
   return getContext().getELFSection(SectionName, getXCoreSectionType(Kind),
diff --git a/llvm/lib/TargetParser/AArch64TargetParser.cpp b/llvm/lib/TargetParser/AArch64TargetParser.cpp
index a3f9dfa4a283..d3c72497c41c 100644
--- a/llvm/lib/TargetParser/AArch64TargetParser.cpp
+++ b/llvm/lib/TargetParser/AArch64TargetParser.cpp
@@ -75,7 +75,7 @@ StringRef AArch64::resolveCPUAlias(StringRef Name) {
 }
 
 StringRef AArch64::getArchExtFeature(StringRef ArchExt) {
-  if (ArchExt.startswith("no")) {
+  if (ArchExt.starts_with("no")) {
     StringRef ArchExtBase(ArchExt.substr(2));
     for (const auto &AE : Extensions) {
       if (!AE.NegFeature.empty() && ArchExtBase == AE.Name)
@@ -110,7 +110,7 @@ std::optional<AArch64::ArchInfo> AArch64::parseArch(StringRef Arch) {
 
   StringRef Syn = llvm::ARM::getArchSynonym(Arch);
   for (const auto *A : ArchInfos) {
-    if (A->Name.endswith(Syn))
+    if (A->Name.ends_with(Syn))
       return *A;
   }
   return {};
diff --git a/llvm/lib/TargetParser/ARMTargetParser.cpp b/llvm/lib/TargetParser/ARMTargetParser.cpp
index d09992441909..27d168020ce6 100644
--- a/llvm/lib/TargetParser/ARMTargetParser.cpp
+++ b/llvm/lib/TargetParser/ARMTargetParser.cpp
@@ -32,7 +32,7 @@ ARM::ArchKind ARM::parseArch(StringRef Arch) {
   Arch = getCanonicalArchName(Arch);
   StringRef Syn = getArchSynonym(Arch);
   for (const auto &A : ARMArchNames) {
-    if (A.Name.endswith(Syn))
+    if (A.Name.ends_with(Syn))
       return A.ID;
   }
   return ArchKind::INVALID;
@@ -348,7 +348,7 @@ StringRef ARM::getArchExtName(uint64_t ArchExtKind) {
 }
 
 static bool stripNegationPrefix(StringRef &Name) {
-  if (Name.startswith("no")) {
+  if (Name.starts_with("no")) {
     Name = Name.substr(2);
     return true;
   }
diff --git a/llvm/lib/TargetParser/ARMTargetParserCommon.cpp b/llvm/lib/TargetParser/ARMTargetParserCommon.cpp
index 907ee5957c7c..10b80cad4347 100644
--- a/llvm/lib/TargetParser/ARMTargetParserCommon.cpp
+++ b/llvm/lib/TargetParser/ARMTargetParserCommon.cpp
@@ -57,19 +57,19 @@ StringRef ARM::getCanonicalArchName(StringRef Arch) {
   StringRef Error = "";
 
   // Begins with "arm" / "thumb", move past it.
-  if (A.startswith("arm64_32"))
+  if (A.starts_with("arm64_32"))
     offset = 8;
-  else if (A.startswith("arm64e"))
+  else if (A.starts_with("arm64e"))
     offset = 6;
-  else if (A.startswith("arm64"))
+  else if (A.starts_with("arm64"))
     offset = 5;
-  else if (A.startswith("aarch64_32"))
+  else if (A.starts_with("aarch64_32"))
     offset = 10;
-  else if (A.startswith("arm"))
+  else if (A.starts_with("arm"))
     offset = 3;
-  else if (A.startswith("thumb"))
+  else if (A.starts_with("thumb"))
     offset = 5;
-  else if (A.startswith("aarch64")) {
+  else if (A.starts_with("aarch64")) {
     offset = 7;
     // AArch64 uses "_be", not "eb" suffix.
     if (A.contains("eb"))
@@ -82,7 +82,7 @@ StringRef ARM::getCanonicalArchName(StringRef Arch) {
   if (offset != StringRef::npos && A.substr(offset, 2) == "eb")
     offset += 2;
   // Or, if it ends with eb ("armv7eb"), chop it off.
-  else if (A.endswith("eb"))
+  else if (A.ends_with("eb"))
     A = A.substr(0, A.size() - 2);
   // Trim the head
   if (offset != StringRef::npos)
@@ -116,18 +116,18 @@ ARM::ISAKind ARM::parseArchISA(StringRef Arch) {
 }
 
 ARM::EndianKind ARM::parseArchEndian(StringRef Arch) {
-  if (Arch.startswith("armeb") || Arch.startswith("thumbeb") ||
-      Arch.startswith("aarch64_be"))
+  if (Arch.starts_with("armeb") || Arch.starts_with("thumbeb") ||
+      Arch.starts_with("aarch64_be"))
     return EndianKind::BIG;
 
-  if (Arch.startswith("arm") || Arch.startswith("thumb")) {
-    if (Arch.endswith("eb"))
+  if (Arch.starts_with("arm") || Arch.starts_with("thumb")) {
+    if (Arch.ends_with("eb"))
       return EndianKind::BIG;
     else
       return EndianKind::LITTLE;
   }
 
-  if (Arch.startswith("aarch64") || Arch.startswith("aarch64_32"))
+  if (Arch.starts_with("aarch64") || Arch.starts_with("aarch64_32"))
     return EndianKind::LITTLE;
 
   return EndianKind::INVALID;
diff --git a/llvm/lib/TargetParser/CSKYTargetParser.cpp b/llvm/lib/TargetParser/CSKYTargetParser.cpp
index 493f253cd716..006d2bb342ac 100644
--- a/llvm/lib/TargetParser/CSKYTargetParser.cpp
+++ b/llvm/lib/TargetParser/CSKYTargetParser.cpp
@@ -150,7 +150,7 @@ StringRef CSKY::getArchExtName(uint64_t ArchExtKind) {
 }
 
 static bool stripNegationPrefix(StringRef &Name) {
-  if (Name.startswith("no")) {
+  if (Name.starts_with("no")) {
     Name = Name.substr(2);
     return true;
   }
diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
index 40f4ba0be550..e822da11ee85 100644
--- a/llvm/lib/TargetParser/Host.cpp
+++ b/llvm/lib/TargetParser/Host.cpp
@@ -170,18 +170,18 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) {
   StringRef Hardware;
   StringRef Part;
   for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
-    if (Lines[I].startswith("CPU implementer"))
+    if (Lines[I].starts_with("CPU implementer"))
       Implementer = Lines[I].substr(15).ltrim("\t :");
-    if (Lines[I].startswith("Hardware"))
+    if (Lines[I].starts_with("Hardware"))
       Hardware = Lines[I].substr(8).ltrim("\t :");
-    if (Lines[I].startswith("CPU part"))
+    if (Lines[I].starts_with("CPU part"))
       Part = Lines[I].substr(8).ltrim("\t :");
   }
 
   if (Implementer == "0x41") { // ARM Ltd.
     // MSM8992/8994 may give cpu part for the core that the kernel is running on,
     // which is undeterministic and wrong. Always return cortex-a53 for these SoC.
-    if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996"))
+    if (Hardware.ends_with("MSM8994") || Hardware.ends_with("MSM8996"))
       return "cortex-a53";
 
 
@@ -367,7 +367,7 @@ StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) {
   // Look for the CPU features.
   SmallVector<StringRef, 32> CPUFeatures;
   for (unsigned I = 0, E = Lines.size(); I != E; ++I)
-    if (Lines[I].startswith("features")) {
+    if (Lines[I].starts_with("features")) {
       size_t Pos = Lines[I].find(':');
       if (Pos != StringRef::npos) {
         Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' ');
@@ -386,7 +386,7 @@ StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) {
 
   // Now check the processor machine type.
   for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
-    if (Lines[I].startswith("processor ")) {
+    if (Lines[I].starts_with("processor ")) {
       size_t Pos = Lines[I].find("machine = ");
       if (Pos != StringRef::npos) {
         Pos += sizeof("machine = ") - 1;
@@ -409,7 +409,7 @@ StringRef sys::detail::getHostCPUNameForRISCV(StringRef ProcCpuinfoContent) {
   // Look for uarch line to determine cpu name
   StringRef UArch;
   for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
-    if (Lines[I].startswith("uarch")) {
+    if (Lines[I].starts_with("uarch")) {
       UArch = Lines[I].substr(5).ltrim("\t :");
       break;
     }
diff --git a/llvm/lib/TargetParser/Triple.cpp b/llvm/lib/TargetParser/Triple.cpp
index c5e9ad43d225..ac04dab04897 100644
--- a/llvm/lib/TargetParser/Triple.cpp
+++ b/llvm/lib/TargetParser/Triple.cpp
@@ -477,7 +477,7 @@ static Triple::ArchType parseARMArch(StringRef ArchName) {
 
   // Thumb only exists in v4+
   if (ISA == ARM::ISAKind::THUMB &&
-      (ArchName.startswith("v2") || ArchName.startswith("v3")))
+      (ArchName.starts_with("v2") || ArchName.starts_with("v3")))
     return Triple::UnknownArch;
 
   // Thumb only for v6m
@@ -574,10 +574,10 @@ static Triple::ArchType parseArch(StringRef ArchName) {
   // Some architectures require special parsing logic just to compute the
   // ArchType result.
   if (AT == Triple::UnknownArch) {
-    if (ArchName.startswith("arm") || ArchName.startswith("thumb") ||
-        ArchName.startswith("aarch64"))
+    if (ArchName.starts_with("arm") || ArchName.starts_with("thumb") ||
+        ArchName.starts_with("aarch64"))
       return parseARMArch(ArchName);
-    if (ArchName.startswith("bpf"))
+    if (ArchName.starts_with("bpf"))
       return parseBPFArch(ArchName);
   }
 
@@ -706,8 +706,8 @@ static Triple::ObjectFormatType parseFormat(StringRef EnvironmentName) {
 }
 
 static Triple::SubArchType parseSubArch(StringRef SubArchName) {
-  if (SubArchName.startswith("mips") &&
-      (SubArchName.endswith("r6el") || SubArchName.endswith("r6")))
+  if (SubArchName.starts_with("mips") &&
+      (SubArchName.ends_with("r6el") || SubArchName.ends_with("r6")))
     return Triple::MipsSubArch_r6;
 
   if (SubArchName == "powerpcspe")
@@ -719,7 +719,7 @@ static Triple::SubArchType parseSubArch(StringRef SubArchName) {
   if (SubArchName == "arm64ec")
     return Triple::AArch64SubArch_arm64ec;
 
-  if (SubArchName.startswith("spirv"))
+  if (SubArchName.starts_with("spirv"))
     return StringSwitch<Triple::SubArchType>(SubArchName)
         .EndsWith("v1.0", Triple::SPIRVSubArch_v10)
         .EndsWith("v1.1", Triple::SPIRVSubArch_v11)
@@ -1004,8 +1004,8 @@ std::string Triple::normalize(StringRef Str) {
   OSType OS = UnknownOS;
   if (Components.size() > 2) {
     OS = parseOS(Components[2]);
-    IsCygwin = Components[2].startswith("cygwin");
-    IsMinGW32 = Components[2].startswith("mingw");
+    IsCygwin = Components[2].starts_with("cygwin");
+    IsMinGW32 = Components[2].starts_with("mingw");
   }
   EnvironmentType Environment = UnknownEnvironment;
   if (Components.size() > 3)
@@ -1049,8 +1049,8 @@ std::string Triple::normalize(StringRef Str) {
         break;
       case 2:
         OS = parseOS(Comp);
-        IsCygwin = Comp.startswith("cygwin");
-        IsMinGW32 = Comp.startswith("mingw");
+        IsCygwin = Comp.starts_with("cygwin");
+        IsMinGW32 = Comp.starts_with("mingw");
         Valid = OS != UnknownOS || IsCygwin || IsMinGW32;
         break;
       case 3:
@@ -1127,7 +1127,8 @@ std::string Triple::normalize(StringRef Str) {
   // Special case logic goes here.  At this point Arch, Vendor and OS have the
   // correct values for the computed components.
   std::string NormalizedEnvironment;
-  if (Environment == Triple::Android && Components[3].startswith("androideabi")) {
+  if (Environment == Triple::Android &&
+      Components[3].starts_with("androideabi")) {
     StringRef AndroidVersion = Components[3].drop_front(strlen("androideabi"));
     if (AndroidVersion.empty()) {
       Components[3] = "android";
@@ -1206,7 +1207,7 @@ static VersionTuple parseVersionFromName(StringRef Name) {
 VersionTuple Triple::getEnvironmentVersion() const {
   StringRef EnvironmentName = getEnvironmentName();
   StringRef EnvironmentTypeName = getEnvironmentTypeName(getEnvironment());
-  if (EnvironmentName.startswith(EnvironmentTypeName))
+  if (EnvironmentName.starts_with(EnvironmentTypeName))
     EnvironmentName = EnvironmentName.substr(EnvironmentTypeName.size());
 
   return parseVersionFromName(EnvironmentName);
@@ -1216,7 +1217,7 @@ VersionTuple Triple::getOSVersion() const {
   StringRef OSName = getOSName();
   // Assume that the OS portion of the triple starts with the canonical name.
   StringRef OSTypeName = getOSTypeName(getOS());
-  if (OSName.startswith(OSTypeName))
+  if (OSName.starts_with(OSTypeName))
     OSName = OSName.substr(OSTypeName.size());
   else if (getOS() == MacOSX)
     OSName.consume_front("macos");
diff --git a/llvm/lib/TextAPI/Symbol.cpp b/llvm/lib/TextAPI/Symbol.cpp
index c3756fcb8435..fd395436051d 100644
--- a/llvm/lib/TextAPI/Symbol.cpp
+++ b/llvm/lib/TextAPI/Symbol.cpp
@@ -73,16 +73,16 @@ bool Symbol::operator==(const Symbol &O) const {
 }
 
 SimpleSymbol parseSymbol(StringRef SymName, const SymbolFlags Flags) {
-  if (SymName.startswith(ObjC1ClassNamePrefix))
+  if (SymName.starts_with(ObjC1ClassNamePrefix))
     return {SymName.drop_front(ObjC1ClassNamePrefix.size()),
             SymbolKind::ObjectiveCClass};
-  if (SymName.startswith(ObjC2ClassNamePrefix))
+  if (SymName.starts_with(ObjC2ClassNamePrefix))
     return {SymName.drop_front(ObjC2ClassNamePrefix.size()),
             SymbolKind::ObjectiveCClass};
-  if (SymName.startswith(ObjC2MetaClassNamePrefix))
+  if (SymName.starts_with(ObjC2MetaClassNamePrefix))
     return {SymName.drop_front(ObjC2MetaClassNamePrefix.size()),
             SymbolKind::ObjectiveCClass};
-  if (SymName.startswith(ObjC2EHTypePrefix)) {
+  if (SymName.starts_with(ObjC2EHTypePrefix)) {
     // When classes without ehtype are used in try/catch blocks
     // a weak-defined symbol is exported. In those cases, treat these as a
     // global instead.
@@ -92,7 +92,7 @@ SimpleSymbol parseSymbol(StringRef SymName, const SymbolFlags Flags) {
             SymbolKind::ObjectiveCClassEHType};
   }
 
-  if (SymName.startswith(ObjC2IVarPrefix))
+  if (SymName.starts_with(ObjC2IVarPrefix))
     return {SymName.drop_front(ObjC2IVarPrefix.size()),
             SymbolKind::ObjectiveCInstanceVariable};
   return {SymName, SymbolKind::GlobalSymbol};
diff --git a/llvm/lib/TextAPI/Target.cpp b/llvm/lib/TextAPI/Target.cpp
index 7f4551973507..a50abeeca194 100644
--- a/llvm/lib/TextAPI/Target.cpp
+++ b/llvm/lib/TextAPI/Target.cpp
@@ -28,7 +28,7 @@ Expected<Target> Target::create(StringRef TargetValue) {
                  .Default(PLATFORM_UNKNOWN);
 
   if (Platform == PLATFORM_UNKNOWN) {
-    if (PlatformStr.startswith("<") && PlatformStr.endswith(">")) {
+    if (PlatformStr.starts_with("<") && PlatformStr.ends_with(">")) {
       PlatformStr = PlatformStr.drop_front().drop_back();
       unsigned long long RawValue;
       if (!PlatformStr.getAsInteger(10, RawValue))
diff --git a/llvm/lib/TextAPI/TextStub.cpp b/llvm/lib/TextAPI/TextStub.cpp
index 635f6b3a3df6..9fa1459e9557 100644
--- a/llvm/lib/TextAPI/TextStub.cpp
+++ b/llvm/lib/TextAPI/TextStub.cpp
@@ -614,7 +614,7 @@ template <> struct MappingTraits<const InterfaceFile *> {
 
         for (const auto &Symbol : Section.Symbols) {
           if (Ctx->FileKind != FileType::TBD_V3 &&
-              Symbol.value.startswith(ObjC2EHTypePrefix))
+              Symbol.value.starts_with(ObjC2EHTypePrefix))
             File->addSymbol(SymbolKind::ObjectiveCClassEHType,
                             Symbol.value.drop_front(15), Targets, Flags);
           else
@@ -649,7 +649,7 @@ template <> struct MappingTraits<const InterfaceFile *> {
             synthesizeTargets(Section.Architectures, Platforms);
         for (auto &Symbol : Section.Symbols) {
           if (Ctx->FileKind != FileType::TBD_V3 &&
-              Symbol.value.startswith(ObjC2EHTypePrefix))
+              Symbol.value.starts_with(ObjC2EHTypePrefix))
             File->addSymbol(SymbolKind::ObjectiveCClassEHType,
                             Symbol.value.drop_front(15), Targets,
                             SymbolFlags::Undefined | Flags);
@@ -1073,23 +1073,23 @@ static void DiagHandler(const SMDiagnostic &Diag, void *Context) {
 
 Expected<FileType> TextAPIReader::canRead(MemoryBufferRef InputBuffer) {
   auto TAPIFile = InputBuffer.getBuffer().trim();
-  if (TAPIFile.startswith("{") && TAPIFile.endswith("}"))
+  if (TAPIFile.starts_with("{") && TAPIFile.ends_with("}"))
     return FileType::TBD_V5;
 
-  if (!TAPIFile.endswith("..."))
+  if (!TAPIFile.ends_with("..."))
     return createStringError(std::errc::not_supported, "unsupported file type");
 
-  if (TAPIFile.startswith("--- !tapi-tbd\n"))
+  if (TAPIFile.starts_with("--- !tapi-tbd\n"))
     return FileType::TBD_V4;
 
-  if (TAPIFile.startswith("--- !tapi-tbd-v3\n"))
+  if (TAPIFile.starts_with("--- !tapi-tbd-v3\n"))
     return FileType::TBD_V3;
 
-  if (TAPIFile.startswith("--- !tapi-tbd-v2\n"))
+  if (TAPIFile.starts_with("--- !tapi-tbd-v2\n"))
     return FileType::TBD_V2;
 
-  if (TAPIFile.startswith("--- !tapi-tbd-v1\n") ||
-      TAPIFile.startswith("---\narchs:"))
+  if (TAPIFile.starts_with("--- !tapi-tbd-v1\n") ||
+      TAPIFile.starts_with("---\narchs:"))
     return FileType::TBD_V1;
 
   return createStringError(std::errc::not_supported, "unsupported file type");
diff --git a/llvm/tools/dsymutil/BinaryHolder.cpp b/llvm/tools/dsymutil/BinaryHolder.cpp
index c19285eebdd7..646fe4fc8f80 100644
--- a/llvm/tools/dsymutil/BinaryHolder.cpp
+++ b/llvm/tools/dsymutil/BinaryHolder.cpp
@@ -26,7 +26,7 @@ getArchiveAndObjectName(StringRef Filename) {
   return {Archive, Object};
 }
 
-static bool isArchive(StringRef Filename) { return Filename.endswith(")"); }
+static bool isArchive(StringRef Filename) { return Filename.ends_with(")"); }
 
 static std::vector<MemoryBufferRef>
 getMachOFatMemoryBuffers(StringRef Filename, MemoryBuffer &Mem,
diff --git a/llvm/tools/dsymutil/DwarfLinkerForBinary.cpp b/llvm/tools/dsymutil/DwarfLinkerForBinary.cpp
index d00ef1a8c228..33d053c745b0 100644
--- a/llvm/tools/dsymutil/DwarfLinkerForBinary.cpp
+++ b/llvm/tools/dsymutil/DwarfLinkerForBinary.cpp
@@ -164,7 +164,7 @@ DwarfLinkerForBinary::loadObject(const DebugMapObject &Obj,
 static Error remarksErrorHandler(const DebugMapObject &DMO,
                                  DwarfLinkerForBinary &Linker,
                                  std::unique_ptr<FileError> FE) {
-  bool IsArchive = DMO.getObjectFilename().endswith(")");
+  bool IsArchive = DMO.getObjectFilename().ends_with(")");
   // Don't report errors for missing remark files from static
   // archives.
   if (!IsArchive)
@@ -713,7 +713,7 @@ bool DwarfLinkerForBinary::linkImpl(
       // Try and emit more helpful warnings by applying some heuristics.
       StringRef ObjFile = ContainerName;
       bool IsClangModule = sys::path::extension(Path).equals(".pcm");
-      bool IsArchive = ObjFile.endswith(")");
+      bool IsArchive = ObjFile.ends_with(")");
 
       if (IsClangModule) {
         StringRef ModuleCacheDir = sys::path::parent_path(Path);
diff --git a/llvm/tools/dsymutil/MachODebugMapParser.cpp b/llvm/tools/dsymutil/MachODebugMapParser.cpp
index 9623b7171458..7a32eacee14c 100644
--- a/llvm/tools/dsymutil/MachODebugMapParser.cpp
+++ b/llvm/tools/dsymutil/MachODebugMapParser.cpp
@@ -550,11 +550,11 @@ static bool shouldLinkArch(SmallVectorImpl<StringRef> &Archs, StringRef Arch) {
   if (Archs.empty() || is_contained(Archs, "all") || is_contained(Archs, "*"))
     return true;
 
-  if (Arch.startswith("arm") && Arch != "arm64" && is_contained(Archs, "arm"))
+  if (Arch.starts_with("arm") && Arch != "arm64" && is_contained(Archs, "arm"))
     return true;
 
   SmallString<16> ArchName = Arch;
-  if (Arch.startswith("thumb"))
+  if (Arch.starts_with("thumb"))
     ArchName = ("arm" + Arch.substr(5)).str();
 
   return is_contained(Archs, ArchName);
diff --git a/llvm/tools/dsymutil/MachOUtils.cpp b/llvm/tools/dsymutil/MachOUtils.cpp
index 44c925fce5c2..3efc1aff8237 100644
--- a/llvm/tools/dsymutil/MachOUtils.cpp
+++ b/llvm/tools/dsymutil/MachOUtils.cpp
@@ -57,7 +57,7 @@ ArchAndFile::~ArchAndFile() {
 }
 
 std::string getArchName(StringRef Arch) {
-  if (Arch.startswith("thumb"))
+  if (Arch.starts_with("thumb"))
     return (llvm::Twine("arm") + Arch.drop_front(5)).str();
   return std::string(Arch);
 }
diff --git a/llvm/tools/dsymutil/SymbolMap.cpp b/llvm/tools/dsymutil/SymbolMap.cpp
index 07a54795a841..0cf8b983db1f 100644
--- a/llvm/tools/dsymutil/SymbolMap.cpp
+++ b/llvm/tools/dsymutil/SymbolMap.cpp
@@ -23,7 +23,7 @@ namespace llvm {
 namespace dsymutil {
 
 StringRef SymbolMapTranslator::operator()(StringRef Input) {
-  if (!Input.startswith("__hidden#") && !Input.startswith("___hidden#"))
+  if (!Input.starts_with("__hidden#") && !Input.starts_with("___hidden#"))
     return Input;
 
   bool MightNeedUnderscore = false;
@@ -131,7 +131,7 @@ SymbolMapTranslator SymbolMapLoader::Load(StringRef InputFile,
   bool MangleNames = false;
 
   // Check version string first.
-  if (!LHS.startswith("BCSymbolMap Version:")) {
+  if (!LHS.starts_with("BCSymbolMap Version:")) {
     // Version string not present, warns but try to parse it.
     WithColor::warning() << SymbolMapPath
                          << " is missing version string: assuming 1.0.\n";
diff --git a/llvm/tools/llc/llc.cpp b/llvm/tools/llc/llc.cpp
index 34e563399813..8d906cf37287 100644
--- a/llvm/tools/llc/llc.cpp
+++ b/llvm/tools/llc/llc.cpp
@@ -249,9 +249,9 @@ static std::unique_ptr<ToolOutputFile> GetOutputStream(const char *TargetName,
     else {
       // If InputFilename ends in .bc or .ll, remove it.
       StringRef IFN = InputFilename;
-      if (IFN.endswith(".bc") || IFN.endswith(".ll"))
+      if (IFN.ends_with(".bc") || IFN.ends_with(".ll"))
         OutputFilename = std::string(IFN.drop_back(3));
-      else if (IFN.endswith(".mir"))
+      else if (IFN.ends_with(".mir"))
         OutputFilename = std::string(IFN.drop_back(4));
       else
         OutputFilename = std::string(IFN);
@@ -584,7 +584,7 @@ static int compileModule(char **argv, LLVMContext &Context) {
       return Target->createDataLayout().getStringRepresentation();
     };
     if (InputLanguage == "mir" ||
-        (InputLanguage == "" && StringRef(InputFilename).endswith(".mir"))) {
+        (InputLanguage == "" && StringRef(InputFilename).ends_with(".mir"))) {
       MIR = createMIRParserFromFile(InputFilename, Err, Context,
                                     setMIRFunctionAttributes);
       if (MIR)
diff --git a/llvm/tools/lli/lli.cpp b/llvm/tools/lli/lli.cpp
index 36fca4c40ed0..5f1fd1578764 100644
--- a/llvm/tools/lli/lli.cpp
+++ b/llvm/tools/lli/lli.cpp
@@ -622,7 +622,7 @@ int main(int argc, char **argv, char * const *envp) {
   } else {
     // Otherwise, if there is a .bc suffix on the executable strip it off, it
     // might confuse the program.
-    if (StringRef(InputFile).endswith(".bc"))
+    if (StringRef(InputFile).ends_with(".bc"))
       InputFile.erase(InputFile.length() - 3);
   }
 
diff --git a/llvm/tools/llvm-ar/llvm-ar.cpp b/llvm/tools/llvm-ar/llvm-ar.cpp
index 9889ad9de627..fcb6392a1d95 100644
--- a/llvm/tools/llvm-ar/llvm-ar.cpp
+++ b/llvm/tools/llvm-ar/llvm-ar.cpp
@@ -1287,7 +1287,7 @@ static const char *matchFlagWithArg(StringRef Expected,
                                     ArrayRef<const char *> Args) {
   StringRef Arg = *ArgIt;
 
-  if (Arg.startswith("--"))
+  if (Arg.starts_with("--"))
     Arg = Arg.substr(2);
 
   size_t len = Expected.size();
@@ -1297,7 +1297,7 @@ static const char *matchFlagWithArg(StringRef Expected,
 
     return *ArgIt;
   }
-  if (Arg.startswith(Expected) && Arg.size() > len && Arg[len] == '=')
+  if (Arg.starts_with(Expected) && Arg.size() > len && Arg[len] == '=')
     return Arg.data() + len + 1;
 
   return nullptr;
diff --git a/llvm/tools/llvm-as/llvm-as.cpp b/llvm/tools/llvm-as/llvm-as.cpp
index ef1c50fc2284..1c869e173931 100644
--- a/llvm/tools/llvm-as/llvm-as.cpp
+++ b/llvm/tools/llvm-as/llvm-as.cpp
@@ -75,7 +75,7 @@ static void WriteOutputFile(const Module *M, const ModuleSummaryIndex *Index) {
       OutputFilename = "-";
     } else {
       StringRef IFN = InputFilename;
-      OutputFilename = (IFN.endswith(".ll") ? IFN.drop_back(3) : IFN).str();
+      OutputFilename = (IFN.ends_with(".ll") ? IFN.drop_back(3) : IFN).str();
       OutputFilename += ".bc";
     }
   }
diff --git a/llvm/tools/llvm-config/llvm-config.cpp b/llvm/tools/llvm-config/llvm-config.cpp
index e86eb2b44b10..f31098eb67cc 100644
--- a/llvm/tools/llvm-config/llvm-config.cpp
+++ b/llvm/tools/llvm-config/llvm-config.cpp
@@ -454,11 +454,11 @@ int main(int argc, char **argv) {
   /// extension. Returns true if Lib is in a recognized format.
   auto GetComponentLibraryNameSlice = [&](const StringRef &Lib,
                                           StringRef &Out) {
-    if (Lib.startswith("lib")) {
+    if (Lib.starts_with("lib")) {
       unsigned FromEnd;
-      if (Lib.endswith(StaticExt)) {
+      if (Lib.ends_with(StaticExt)) {
         FromEnd = StaticExt.size() + 1;
-      } else if (Lib.endswith(SharedExt)) {
+      } else if (Lib.ends_with(SharedExt)) {
         FromEnd = SharedExt.size() + 1;
       } else {
         FromEnd = 0;
@@ -481,7 +481,7 @@ int main(int argc, char **argv) {
         // Treat the DyLibName specially. It is not a component library and
         // already has the necessary prefix and suffix (e.g. `.so`) added so
         // just return it unmodified.
-        assert(Lib.endswith(SharedExt) && "DyLib is missing suffix");
+        assert(Lib.ends_with(SharedExt) && "DyLib is missing suffix");
         LibFileName = std::string(Lib);
       } else {
         LibFileName = (SharedPrefix + Lib + "." + SharedExt).str();
@@ -507,7 +507,7 @@ int main(int argc, char **argv) {
   for (int i = 1; i != argc; ++i) {
     StringRef Arg = argv[i];
 
-    if (Arg.startswith("-")) {
+    if (Arg.starts_with("-")) {
       HasAnyOption = true;
       if (Arg == "--version") {
         OS << PACKAGE_VERSION << '\n';
diff --git a/llvm/tools/llvm-cxxdump/llvm-cxxdump.cpp b/llvm/tools/llvm-cxxdump/llvm-cxxdump.cpp
index f35f62632763..c04aec19174b 100644
--- a/llvm/tools/llvm-cxxdump/llvm-cxxdump.cpp
+++ b/llvm/tools/llvm-cxxdump/llvm-cxxdump.cpp
@@ -217,7 +217,7 @@ static void dumpCXXData(const ObjectFile *Obj) {
     // VFTables in the MS-ABI start with '??_7' and are contained within their
     // own COMDAT section.  We then determine the contents of the VFTable by
     // looking at each relocation in the section.
-    if (SymName.startswith("??_7")) {
+    if (SymName.starts_with("??_7")) {
       // Each relocation either names a virtual method or a thunk.  We note the
       // offset into the section and the symbol used for the relocation.
       collectRelocationOffsets(Obj, Sec, SecAddress, SecAddress, SecSize,
@@ -225,14 +225,14 @@ static void dumpCXXData(const ObjectFile *Obj) {
     }
     // VBTables in the MS-ABI start with '??_8' and are filled with 32-bit
     // offsets of virtual bases.
-    else if (SymName.startswith("??_8")) {
+    else if (SymName.starts_with("??_8")) {
       ArrayRef<little32_t> VBTableData(
           reinterpret_cast<const little32_t *>(SymContents.data()),
           SymContents.size() / sizeof(little32_t));
       VBTables[SymName] = VBTableData;
     }
     // Complete object locators in the MS-ABI start with '??_R4'
-    else if (SymName.startswith("??_R4")) {
+    else if (SymName.starts_with("??_R4")) {
       CompleteObjectLocator COL;
       COL.Data =
           ArrayRef(reinterpret_cast<const little32_t *>(SymContents.data()), 3);
@@ -241,7 +241,7 @@ static void dumpCXXData(const ObjectFile *Obj) {
       COLs[SymName] = COL;
     }
     // Class hierarchy descriptors in the MS-ABI start with '??_R3'
-    else if (SymName.startswith("??_R3")) {
+    else if (SymName.starts_with("??_R3")) {
       ClassHierarchyDescriptor CHD;
       CHD.Data =
           ArrayRef(reinterpret_cast<const little32_t *>(SymContents.data()), 3);
@@ -250,14 +250,14 @@ static void dumpCXXData(const ObjectFile *Obj) {
       CHDs[SymName] = CHD;
     }
     // Class hierarchy descriptors in the MS-ABI start with '??_R2'
-    else if (SymName.startswith("??_R2")) {
+    else if (SymName.starts_with("??_R2")) {
       // Each relocation names a base class descriptor.  We note the offset into
       // the section and the symbol used for the relocation.
       collectRelocationOffsets(Obj, Sec, SecAddress, SymAddress, SymSize,
                                SymName, BCAEntries);
     }
     // Base class descriptors in the MS-ABI start with '??_R1'
-    else if (SymName.startswith("??_R1")) {
+    else if (SymName.starts_with("??_R1")) {
       BaseClassDescriptor BCD;
       BCD.Data = ArrayRef(
           reinterpret_cast<const little32_t *>(SymContents.data()) + 1, 5);
@@ -266,7 +266,7 @@ static void dumpCXXData(const ObjectFile *Obj) {
       BCDs[SymName] = BCD;
     }
     // Type descriptors in the MS-ABI start with '??_R0'
-    else if (SymName.startswith("??_R0")) {
+    else if (SymName.starts_with("??_R0")) {
       const char *DataPtr = SymContents.drop_front(BytesInAddress).data();
       TypeDescriptor TD;
       if (BytesInAddress == 8)
@@ -279,7 +279,7 @@ static void dumpCXXData(const ObjectFile *Obj) {
       TDs[SymName] = TD;
     }
     // Throw descriptors in the MS-ABI start with '_TI'
-    else if (SymName.startswith("_TI") || SymName.startswith("__TI")) {
+    else if (SymName.starts_with("_TI") || SymName.starts_with("__TI")) {
       ThrowInfo TI;
       TI.Flags = *reinterpret_cast<const little32_t *>(SymContents.data());
       collectRelocationOffsets(Obj, Sec, SecAddress, SymAddress, SymSize,
@@ -287,7 +287,7 @@ static void dumpCXXData(const ObjectFile *Obj) {
       TIs[SymName] = TI;
     }
     // Catchable type arrays in the MS-ABI start with _CTA or __CTA.
-    else if (SymName.startswith("_CTA") || SymName.startswith("__CTA")) {
+    else if (SymName.starts_with("_CTA") || SymName.starts_with("__CTA")) {
       CatchableTypeArray CTA;
       CTA.NumEntries =
           *reinterpret_cast<const little32_t *>(SymContents.data());
@@ -296,7 +296,7 @@ static void dumpCXXData(const ObjectFile *Obj) {
       CTAs[SymName] = CTA;
     }
     // Catchable types in the MS-ABI start with _CT or __CT.
-    else if (SymName.startswith("_CT") || SymName.startswith("__CT")) {
+    else if (SymName.starts_with("_CT") || SymName.starts_with("__CT")) {
       const little32_t *DataPtr =
           reinterpret_cast<const little32_t *>(SymContents.data());
       CatchableType CT;
@@ -310,16 +310,16 @@ static void dumpCXXData(const ObjectFile *Obj) {
       CTs[SymName] = CT;
     }
     // Construction vtables in the Itanium ABI start with '_ZTT' or '__ZTT'.
-    else if (SymName.startswith("_ZTT") || SymName.startswith("__ZTT")) {
+    else if (SymName.starts_with("_ZTT") || SymName.starts_with("__ZTT")) {
       collectRelocationOffsets(Obj, Sec, SecAddress, SymAddress, SymSize,
                                SymName, VTTEntries);
     }
     // Typeinfo names in the Itanium ABI start with '_ZTS' or '__ZTS'.
-    else if (SymName.startswith("_ZTS") || SymName.startswith("__ZTS")) {
+    else if (SymName.starts_with("_ZTS") || SymName.starts_with("__ZTS")) {
       TINames[SymName] = SymContents.slice(0, SymContents.find('\0'));
     }
     // Vtables in the Itanium ABI start with '_ZTV' or '__ZTV'.
-    else if (SymName.startswith("_ZTV") || SymName.startswith("__ZTV")) {
+    else if (SymName.starts_with("_ZTV") || SymName.starts_with("__ZTV")) {
       collectRelocationOffsets(Obj, Sec, SecAddress, SymAddress, SymSize,
                                SymName, VTableSymEntries);
       for (uint64_t SymOffI = 0; SymOffI < SymSize; SymOffI += BytesInAddress) {
@@ -337,7 +337,7 @@ static void dumpCXXData(const ObjectFile *Obj) {
       }
     }
     // Typeinfo structures in the Itanium ABI start with '_ZTI' or '__ZTI'.
-    else if (SymName.startswith("_ZTI") || SymName.startswith("__ZTI")) {
+    else if (SymName.starts_with("_ZTI") || SymName.starts_with("__ZTI")) {
       // FIXME: Do something with these!
     }
   }
diff --git a/llvm/tools/llvm-diff/llvm-diff.cpp b/llvm/tools/llvm-diff/llvm-diff.cpp
index 7349469c80d6..6fe18a51c9f5 100644
--- a/llvm/tools/llvm-diff/llvm-diff.cpp
+++ b/llvm/tools/llvm-diff/llvm-diff.cpp
@@ -42,7 +42,8 @@ static std::unique_ptr<Module> readModule(LLVMContext &Context,
 static void diffGlobal(DifferenceEngine &Engine, Module &L, Module &R,
                        StringRef Name) {
   // Drop leading sigils from the global name.
-  if (Name.startswith("@")) Name = Name.substr(1);
+  if (Name.starts_with("@"))
+    Name = Name.substr(1);
 
   Function *LFn = L.getFunction(Name);
   Function *RFn = R.getFunction(Name);
diff --git a/llvm/tools/llvm-dis/llvm-dis.cpp b/llvm/tools/llvm-dis/llvm-dis.cpp
index 4996fc12ae32..06fc669390bf 100644
--- a/llvm/tools/llvm-dis/llvm-dis.cpp
+++ b/llvm/tools/llvm-dis/llvm-dis.cpp
@@ -225,7 +225,7 @@ int main(int argc, char **argv) {
           FinalFilename = "-";
         } else {
           StringRef IFN = InputFilename;
-          FinalFilename = (IFN.endswith(".bc") ? IFN.drop_back(3) : IFN).str();
+          FinalFilename = (IFN.ends_with(".bc") ? IFN.drop_back(3) : IFN).str();
           if (N > 1)
             FinalFilename += std::string(".") + std::to_string(I);
           FinalFilename += ".ll";
diff --git a/llvm/tools/llvm-dwarfutil/DebugInfoLinker.h b/llvm/tools/llvm-dwarfutil/DebugInfoLinker.h
index d9d99ffc8747..77cb8bb1aa7d 100644
--- a/llvm/tools/llvm-dwarfutil/DebugInfoLinker.h
+++ b/llvm/tools/llvm-dwarfutil/DebugInfoLinker.h
@@ -18,7 +18,7 @@ namespace llvm {
 namespace dwarfutil {
 
 inline bool isDebugSection(StringRef SecName) {
-  return SecName.startswith(".debug") || SecName.startswith(".zdebug") ||
+  return SecName.starts_with(".debug") || SecName.starts_with(".zdebug") ||
          SecName == ".gdb_index";
 }
 
diff --git a/llvm/tools/llvm-exegesis/lib/X86/Target.cpp b/llvm/tools/llvm-exegesis/lib/X86/Target.cpp
index d025fe955be5..73c0f5430d80 100644
--- a/llvm/tools/llvm-exegesis/lib/X86/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/X86/Target.cpp
@@ -210,9 +210,9 @@ static const char *isInvalidOpcode(const Instruction &Instr) {
   const auto OpcodeName = Instr.Name;
   if ((Instr.Description.TSFlags & X86II::FormMask) == X86II::Pseudo)
     return "unsupported opcode: pseudo instruction";
-  if ((OpcodeName.startswith("POP") && !OpcodeName.startswith("POPCNT")) ||
-      OpcodeName.startswith("PUSH") || OpcodeName.startswith("ADJCALLSTACK") ||
-      OpcodeName.startswith("LEAVE"))
+  if ((OpcodeName.starts_with("POP") && !OpcodeName.starts_with("POPCNT")) ||
+      OpcodeName.starts_with("PUSH") ||
+      OpcodeName.starts_with("ADJCALLSTACK") || OpcodeName.starts_with("LEAVE"))
     return "unsupported opcode: Push/Pop/AdjCallStack/Leave";
   switch (Instr.Description.Opcode) {
   case X86::LFS16rm:
diff --git a/llvm/tools/llvm-jitlink/llvm-jitlink.cpp b/llvm/tools/llvm-jitlink/llvm-jitlink.cpp
index 3d6247ca6a25..aa032c97485f 100644
--- a/llvm/tools/llvm-jitlink/llvm-jitlink.cpp
+++ b/llvm/tools/llvm-jitlink/llvm-jitlink.cpp
@@ -1547,8 +1547,8 @@ static Error addObjects(Session &S,
     unsigned InputFileArgIdx =
         InputFiles.getPosition(InputFileItr - InputFiles.begin());
     const std::string &InputFile = *InputFileItr;
-    if (StringRef(InputFile).endswith(".a") ||
-        StringRef(InputFile).endswith(".lib"))
+    if (StringRef(InputFile).ends_with(".a") ||
+        StringRef(InputFile).ends_with(".lib"))
       continue;
     auto &JD = *std::prev(IdxToJD.lower_bound(InputFileArgIdx))->second;
     LLVM_DEBUG(dbgs() << "  " << InputFileArgIdx << ": \"" << InputFile
@@ -1648,7 +1648,7 @@ static Error addLibraries(Session &S,
   for (auto InputFileItr = InputFiles.begin(), InputFileEnd = InputFiles.end();
        InputFileItr != InputFileEnd; ++InputFileItr) {
     StringRef InputFile = *InputFileItr;
-    if (!InputFile.endswith(".a") && !InputFile.endswith(".lib"))
+    if (!InputFile.ends_with(".a") && !InputFile.ends_with(".lib"))
       continue;
     LibraryLoad LL;
     LL.LibName = InputFile.str();
diff --git a/llvm/tools/llvm-libtool-darwin/llvm-libtool-darwin.cpp b/llvm/tools/llvm-libtool-darwin/llvm-libtool-darwin.cpp
index 9680cfa13cc5..45e04d8f9dd0 100644
--- a/llvm/tools/llvm-libtool-darwin/llvm-libtool-darwin.cpp
+++ b/llvm/tools/llvm-libtool-darwin/llvm-libtool-darwin.cpp
@@ -132,7 +132,7 @@ static Expected<std::string> searchForFile(const Twine &FileName) {
 static Error processCommandLineLibraries() {
   for (StringRef BaseName : Libraries) {
     Expected<std::string> FullPath = searchForFile(
-        BaseName.endswith(".o") ? BaseName.str() : "lib" + BaseName + ".a");
+        BaseName.ends_with(".o") ? BaseName.str() : "lib" + BaseName + ".a");
     if (!FullPath)
       return FullPath.takeError();
     InputFiles.push_back(FullPath.get());
diff --git a/llvm/tools/llvm-nm/llvm-nm.cpp b/llvm/tools/llvm-nm/llvm-nm.cpp
index fede89e9c116..19ee5374979c 100644
--- a/llvm/tools/llvm-nm/llvm-nm.cpp
+++ b/llvm/tools/llvm-nm/llvm-nm.cpp
@@ -900,7 +900,7 @@ static char getSymbolNMTypeChar(ELFObjectFileBase &Obj,
       consumeError(NameOrErr.takeError());
       return '?';
     }
-    if ((*NameOrErr).startswith(".debug"))
+    if ((*NameOrErr).starts_with(".debug"))
       return 'N';
     if (!(Flags & ELF::SHF_WRITE))
       return 'n';
@@ -939,7 +939,7 @@ static char getSymbolNMTypeChar(COFFObjectFile &Obj, symbol_iterator I) {
     const coff_section *Section = Obj.getCOFFSection(*SecI);
     Characteristics = Section->Characteristics;
     if (Expected<StringRef> NameOrErr = Obj.getSectionName(Section))
-      if (NameOrErr->startswith(".idata"))
+      if (NameOrErr->starts_with(".idata"))
         return 'i';
   }
 
@@ -1738,13 +1738,13 @@ static void getXCOFFExports(XCOFFObjectFile *XCOFFObj,
     StringRef SymName = cantFail(Sym.getName());
     if (SymName.empty())
       continue;
-    if (SymName.startswith("__sinit") || SymName.startswith("__sterm") ||
+    if (SymName.starts_with("__sinit") || SymName.starts_with("__sterm") ||
         SymName.front() == '.' || SymName.front() == '(')
       continue;
 
     // Check the SymName regex matching with "^__[0-9]+__".
-    if (SymName.size() > 4 && SymName.startswith("__") &&
-        SymName.endswith("__")) {
+    if (SymName.size() > 4 && SymName.starts_with("__") &&
+        SymName.ends_with("__")) {
       if (std::all_of(SymName.begin() + 2, SymName.end() - 2, isDigit))
         continue;
     }
@@ -1752,9 +1752,9 @@ static void getXCOFFExports(XCOFFObjectFile *XCOFFObj,
     if (SymName == "__rsrc" && NoRsrc)
       continue;
 
-    if (SymName.startswith("__tf1"))
+    if (SymName.starts_with("__tf1"))
       SymName = SymName.substr(6);
-    else if (SymName.startswith("__tf9"))
+    else if (SymName.starts_with("__tf9"))
       SymName = SymName.substr(14);
 
     NMSymbol S = {};
diff --git a/llvm/tools/llvm-objcopy/ObjcopyOptions.cpp b/llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
index 571290253944..efc09f308f46 100644
--- a/llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
+++ b/llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
@@ -315,7 +315,7 @@ getOutputTargetInfoByTargetName(StringRef TargetName) {
     MI.OSABI = ELF::ELFOSABI_FREEBSD;
 
   FileFormat Format;
-  if (TargetName.startswith("elf"))
+  if (TargetName.starts_with("elf"))
     Format = FileFormat::ELF;
   else
     // This should never happen because `TargetName` is valid (it certainly
diff --git a/llvm/tools/llvm-objdump/COFFDump.cpp b/llvm/tools/llvm-objdump/COFFDump.cpp
index 8f685a21505c..71697fa01e62 100644
--- a/llvm/tools/llvm-objdump/COFFDump.cpp
+++ b/llvm/tools/llvm-objdump/COFFDump.cpp
@@ -857,7 +857,7 @@ void objdump::printCOFFSymbolTable(const COFFObjectFile &coff) {
            << "(nx " << unsigned(Symbol->getNumberOfAuxSymbols()) << ") "
            << "0x" << format("%08x", unsigned(Symbol->getValue())) << " "
            << Name;
-    if (Demangle && Name.startswith("?")) {
+    if (Demangle && Name.starts_with("?")) {
       int Status = -1;
       char *DemangledSymbol = microsoftDemangle(Name, nullptr, &Status);
 
diff --git a/llvm/tools/llvm-objdump/MachODump.cpp b/llvm/tools/llvm-objdump/MachODump.cpp
index f80a12d2f84b..0e6935c0ac58 100644
--- a/llvm/tools/llvm-objdump/MachODump.cpp
+++ b/llvm/tools/llvm-objdump/MachODump.cpp
@@ -290,7 +290,7 @@ static void getSectionsAndSymbols(MachOObjectFile *MachOObj,
   const StringRef FileName = MachOObj->getFileName();
   for (const SymbolRef &Symbol : MachOObj->symbols()) {
     StringRef SymName = unwrapOrError(Symbol.getName(), FileName);
-    if (!SymName.startswith("ltmp"))
+    if (!SymName.starts_with("ltmp"))
       Symbols.push_back(Symbol);
   }
 
@@ -1482,7 +1482,7 @@ static void CreateSymbolAddressMap(MachOObjectFile *O,
         ST == SymbolRef::ST_Other) {
       uint64_t Address = cantFail(Symbol.getValue());
       StringRef SymName = unwrapOrError(Symbol.getName(), FileName);
-      if (!SymName.startswith(".objc"))
+      if (!SymName.starts_with(".objc"))
         (*AddrMap)[Address] = SymName;
     }
   }
diff --git a/llvm/tools/llvm-objdump/SourcePrinter.cpp b/llvm/tools/llvm-objdump/SourcePrinter.cpp
index b2fe56cf2e1c..76da86587586 100644
--- a/llvm/tools/llvm-objdump/SourcePrinter.cpp
+++ b/llvm/tools/llvm-objdump/SourcePrinter.cpp
@@ -436,7 +436,7 @@ void SourcePrinter::printLines(formatted_raw_ostream &OS,
     OS << Delimiter << LineInfo.FunctionName;
     // If demangling is successful, FunctionName will end with "()". Print it
     // only if demangling did not run or was unsuccessful.
-    if (!StringRef(LineInfo.FunctionName).endswith("()"))
+    if (!StringRef(LineInfo.FunctionName).ends_with("()"))
       OS << "()";
     OS << ":\n";
   }
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index 631ca955776d..12bb70d5537d 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -1538,7 +1538,7 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
       // __mh_(execute|dylib|dylinker|bundle|preload|object)_header are special
       // symbols that support MachO header introspection. They do not bind to
       // code locations and are irrelevant for disassembly.
-      if (NameOrErr->startswith("__mh_") && NameOrErr->endswith("_header"))
+      if (NameOrErr->starts_with("__mh_") && NameOrErr->ends_with("_header"))
         continue;
       // Don't ask a Mach-O STAB symbol for its section unless you know that
       // STAB symbol's section field refers to a valid section index. Otherwise
diff --git a/llvm/tools/llvm-profdata/llvm-profdata.cpp b/llvm/tools/llvm-profdata/llvm-profdata.cpp
index 63e34d81f189..088138f27de5 100644
--- a/llvm/tools/llvm-profdata/llvm-profdata.cpp
+++ b/llvm/tools/llvm-profdata/llvm-profdata.cpp
@@ -1514,7 +1514,7 @@ static void parseInputFilenamesFile(MemoryBuffer *Buffer,
   for (const StringRef &FileWeightEntry : Entries) {
     StringRef SanitizedEntry = FileWeightEntry.trim(" \t\v\f\r");
     // Skip comments.
-    if (SanitizedEntry.startswith("#"))
+    if (SanitizedEntry.starts_with("#"))
       continue;
     // If there's no comma, it's an unweighted profile.
     else if (!SanitizedEntry.contains(','))
diff --git a/llvm/tools/llvm-profgen/PerfReader.cpp b/llvm/tools/llvm-profgen/PerfReader.cpp
index 9f4516730690..313d40483a25 100644
--- a/llvm/tools/llvm-profgen/PerfReader.cpp
+++ b/llvm/tools/llvm-profgen/PerfReader.cpp
@@ -597,7 +597,7 @@ bool PerfScriptReader::extractCallstack(TraceStream &TraceIt,
   // It's in bottom-up order with each frame in one line.
 
   // Extract stack frames from sample
-  while (!TraceIt.isAtEoF() && !TraceIt.getCurrentLine().startswith(" 0x")) {
+  while (!TraceIt.isAtEoF() && !TraceIt.getCurrentLine().starts_with(" 0x")) {
     StringRef FrameStr = TraceIt.getCurrentLine().ltrim();
     uint64_t FrameAddr = 0;
     if (FrameStr.getAsInteger(16, FrameAddr)) {
@@ -645,7 +645,7 @@ bool PerfScriptReader::extractCallstack(TraceStream &TraceIt,
   // Skip other unrelated line, find the next valid LBR line
   // Note that even for empty call stack, we should skip the address at the
   // bottom, otherwise the following pass may generate a truncated callstack
-  while (!TraceIt.isAtEoF() && !TraceIt.getCurrentLine().startswith(" 0x")) {
+  while (!TraceIt.isAtEoF() && !TraceIt.getCurrentLine().starts_with(" 0x")) {
     TraceIt.advance();
   }
   // Filter out broken stack sample. We may not have complete frame info
@@ -690,14 +690,14 @@ void HybridPerfReader::parseSample(TraceStream &TraceIt, uint64_t Count) {
   // Parsing call stack and populate into PerfSample.CallStack
   if (!extractCallstack(TraceIt, Sample->CallStack)) {
     // Skip the next LBR line matched current call stack
-    if (!TraceIt.isAtEoF() && TraceIt.getCurrentLine().startswith(" 0x"))
+    if (!TraceIt.isAtEoF() && TraceIt.getCurrentLine().starts_with(" 0x"))
       TraceIt.advance();
     return;
   }
 
   warnIfMissingMMap();
 
-  if (!TraceIt.isAtEoF() && TraceIt.getCurrentLine().startswith(" 0x")) {
+  if (!TraceIt.isAtEoF() && TraceIt.getCurrentLine().starts_with(" 0x")) {
     // Parsing LBR stack and populate into PerfSample.LBRStack
     if (extractLBRStack(TraceIt, Sample->LBRStack)) {
       if (IgnoreStackSamples) {
@@ -846,7 +846,7 @@ void UnsymbolizedProfileReader::readUnsymbolizedProfile(StringRef FileName) {
         std::make_shared<StringBasedCtxKey>();
     StringRef Line = TraceIt.getCurrentLine();
     // Read context stack for CS profile.
-    if (Line.startswith("[")) {
+    if (Line.starts_with("[")) {
       ProfileIsCS = true;
       auto I = ContextStrSet.insert(Line.str());
       SampleContext::createCtxVectorFromStr(*I.first, Key->Context);
@@ -1005,7 +1005,7 @@ bool PerfScriptReader::isLBRSample(StringRef Line) {
   Line.trim().split(Records, " ", 2, false);
   if (Records.size() < 2)
     return false;
-  if (Records[1].startswith("0x") && Records[1].contains('/'))
+  if (Records[1].starts_with("0x") && Records[1].contains('/'))
     return true;
   return false;
 }
diff --git a/llvm/tools/llvm-rc/ResourceScriptCppFilter.cpp b/llvm/tools/llvm-rc/ResourceScriptCppFilter.cpp
index 6657aa54cf6e..3081dbbb6d76 100644
--- a/llvm/tools/llvm-rc/ResourceScriptCppFilter.cpp
+++ b/llvm/tools/llvm-rc/ResourceScriptCppFilter.cpp
@@ -67,7 +67,7 @@ bool Filter::parseLine(StringRef Line) {
   // false since the preprocessing directives should be filtered out.
 
   Line.consume_front("line");
-  if (!Line.startswith(" "))
+  if (!Line.starts_with(" "))
     return false; // Not a line directive (pragma etc).
 
   // #line 123 "path/file.h"
diff --git a/llvm/tools/llvm-rc/ResourceScriptToken.cpp b/llvm/tools/llvm-rc/ResourceScriptToken.cpp
index a8f40abdf8a6..aad1060c4a38 100644
--- a/llvm/tools/llvm-rc/ResourceScriptToken.cpp
+++ b/llvm/tools/llvm-rc/ResourceScriptToken.cpp
@@ -274,7 +274,7 @@ Error Tokenizer::consumeToken(const Kind TokenKind) {
 }
 
 bool Tokenizer::willNowRead(StringRef FollowingChars) const {
-  return Data.drop_front(Pos).startswith(FollowingChars);
+  return Data.drop_front(Pos).starts_with(FollowingChars);
 }
 
 bool Tokenizer::canStartIdentifier() const {
@@ -298,12 +298,12 @@ bool Tokenizer::canStartInt() const {
 
 bool Tokenizer::canStartBlockComment() const {
   assert(!streamEof());
-  return Data.drop_front(Pos).startswith("/*");
+  return Data.drop_front(Pos).starts_with("/*");
 }
 
 bool Tokenizer::canStartLineComment() const {
   assert(!streamEof());
-  return Data.drop_front(Pos).startswith("//");
+  return Data.drop_front(Pos).starts_with("//");
 }
 
 bool Tokenizer::canContinueInt() const {
diff --git a/llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp b/llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp
index cf5c77cf107c..b77839c2c57c 100644
--- a/llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp
+++ b/llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp
@@ -1476,7 +1476,7 @@ Error Decoder::dumpProcedureData(const COFFObjectFile &COFF) {
     if (!NameOrErr)
       return NameOrErr.takeError();
 
-    if (NameOrErr->startswith(".pdata"))
+    if (NameOrErr->starts_with(".pdata"))
       dumpProcedureData(COFF, Section);
   }
   return Error::success();
diff --git a/llvm/tools/llvm-readobj/COFFDumper.cpp b/llvm/tools/llvm-readobj/COFFDumper.cpp
index 3ad40dc35510..32b1d6a2089c 100644
--- a/llvm/tools/llvm-readobj/COFFDumper.cpp
+++ b/llvm/tools/llvm-readobj/COFFDumper.cpp
@@ -1946,7 +1946,7 @@ void COFFDumper::printCOFFResources() {
   ListScope ResourcesD(W, "Resources");
   for (const SectionRef &S : Obj->sections()) {
     StringRef Name = unwrapOrError(Obj->getFileName(), S.getName());
-    if (!Name.startswith(".rsrc"))
+    if (!Name.starts_with(".rsrc"))
       continue;
 
     StringRef Ref = unwrapOrError(Obj->getFileName(), S.getContents());
diff --git a/llvm/tools/llvm-readobj/ELFDumper.cpp b/llvm/tools/llvm-readobj/ELFDumper.cpp
index a9a31ae6c474..23f35fa6dfdb 100644
--- a/llvm/tools/llvm-readobj/ELFDumper.cpp
+++ b/llvm/tools/llvm-readobj/ELFDumper.cpp
@@ -1500,7 +1500,7 @@ static std::string getGNUPtType(unsigned Arch, unsigned Type) {
     return Seg.str();
 
   // E.g. "PT_LOAD" -> "LOAD".
-  assert(Seg.startswith("PT_"));
+  assert(Seg.starts_with("PT_"));
   return Seg.drop_front(3).str();
 }
 
@@ -5862,13 +5862,13 @@ StringRef getNoteTypeName(const typename ELFT::Note &Note, unsigned ELFType) {
       return FindNote(FreeBSDNoteTypes);
     }
   }
-  if (ELFType == ELF::ET_CORE && Name.startswith("NetBSD-CORE")) {
+  if (ELFType == ELF::ET_CORE && Name.starts_with("NetBSD-CORE")) {
     StringRef Result = FindNote(NetBSDCoreNoteTypes);
     if (!Result.empty())
       return Result;
     return FindNote(CoreNoteTypes);
   }
-  if (ELFType == ELF::ET_CORE && Name.startswith("OpenBSD")) {
+  if (ELFType == ELF::ET_CORE && Name.starts_with("OpenBSD")) {
     // OpenBSD also places the generic core notes in the OpenBSD namespace.
     StringRef Result = FindNote(OpenBSDCoreNoteTypes);
     if (!Result.empty())
diff --git a/llvm/tools/llvm-readobj/Win64EHDumper.cpp b/llvm/tools/llvm-readobj/Win64EHDumper.cpp
index 2896f20336c5..e4bd77219151 100644
--- a/llvm/tools/llvm-readobj/Win64EHDumper.cpp
+++ b/llvm/tools/llvm-readobj/Win64EHDumper.cpp
@@ -397,7 +397,7 @@ void Dumper::printData(const Context &Ctx) {
     else
       consumeError(NameOrErr.takeError());
 
-    if (Name != ".pdata" && !Name.startswith(".pdata$"))
+    if (Name != ".pdata" && !Name.starts_with(".pdata$"))
       continue;
 
     const coff_section *PData = Ctx.COFF.getCOFFSection(Section);
diff --git a/llvm/tools/llvm-reduce/deltas/StripDebugInfo.cpp b/llvm/tools/llvm-reduce/deltas/StripDebugInfo.cpp
index a65e55d5f6f4..c9e1261c366a 100644
--- a/llvm/tools/llvm-reduce/deltas/StripDebugInfo.cpp
+++ b/llvm/tools/llvm-reduce/deltas/StripDebugInfo.cpp
@@ -18,7 +18,7 @@ using namespace llvm;
 static void stripDebugInfoImpl(Oracle &O, ReducerWorkItem &WorkItem) {
   Module &Program = WorkItem.getModule();
   bool HasDebugInfo = any_of(Program.named_metadata(), [](NamedMDNode &NMD) {
-    return NMD.getName().startswith("llvm.dbg.");
+    return NMD.getName().starts_with("llvm.dbg.");
   });
   if (HasDebugInfo && !O.shouldKeep())
     StripDebugInfo(Program);
diff --git a/llvm/tools/llvm-reduce/llvm-reduce.cpp b/llvm/tools/llvm-reduce/llvm-reduce.cpp
index 466efe4bd439..bd2db635b4d8 100644
--- a/llvm/tools/llvm-reduce/llvm-reduce.cpp
+++ b/llvm/tools/llvm-reduce/llvm-reduce.cpp
@@ -157,7 +157,7 @@ int main(int Argc, char **Argv) {
   if (InputLanguage != InputLanguages::None) {
     if (InputLanguage == InputLanguages::MIR)
       ReduceModeMIR = true;
-  } else if (StringRef(InputFilename).endswith(".mir")) {
+  } else if (StringRef(InputFilename).ends_with(".mir")) {
     ReduceModeMIR = true;
   }
 
diff --git a/llvm/tools/llvm-stress/llvm-stress.cpp b/llvm/tools/llvm-stress/llvm-stress.cpp
index 783316d67655..8cb7fce5c366 100644
--- a/llvm/tools/llvm-stress/llvm-stress.cpp
+++ b/llvm/tools/llvm-stress/llvm-stress.cpp
@@ -175,7 +175,7 @@ public:
         Ty = Type::getPPC_FP128Ty(Context);
       else if (Arg == "x86_mmx")
         Ty = Type::getX86_MMXTy(Context);
-      else if (Arg.startswith("i")) {
+      else if (Arg.starts_with("i")) {
         unsigned N = 0;
         Arg.drop_front().getAsInteger(10, N);
         if (N > 0)
diff --git a/llvm/tools/llvm-undname/llvm-undname.cpp b/llvm/tools/llvm-undname/llvm-undname.cpp
index 96f031abe9c1..d2d76def7ae0 100644
--- a/llvm/tools/llvm-undname/llvm-undname.cpp
+++ b/llvm/tools/llvm-undname/llvm-undname.cpp
@@ -116,7 +116,7 @@ int main(int argc, char **argv) {
 
       StringRef Line(LineStr);
       Line = Line.trim();
-      if (Line.empty() || Line.startswith("#") || Line.startswith(";"))
+      if (Line.empty() || Line.starts_with("#") || Line.starts_with(";"))
         continue;
 
       // If the user is manually typing in these decorated names, don't echo
diff --git a/llvm/tools/obj2yaml/archive2yaml.cpp b/llvm/tools/obj2yaml/archive2yaml.cpp
index c7b0ee480293..35bcd434c8fa 100644
--- a/llvm/tools/obj2yaml/archive2yaml.cpp
+++ b/llvm/tools/obj2yaml/archive2yaml.cpp
@@ -24,7 +24,7 @@ public:
         std::make_unique<ArchYAML::Archive>();
 
     StringRef Magic = "!<arch>\n";
-    if (!Buffer.startswith(Magic))
+    if (!Buffer.starts_with(Magic))
       return createStringError(std::errc::not_supported,
                                "only regular archives are supported");
     Obj->Magic = Magic;
diff --git a/llvm/tools/obj2yaml/elf2yaml.cpp b/llvm/tools/obj2yaml/elf2yaml.cpp
index bec4a10a5d35..86bd138c2206 100644
--- a/llvm/tools/obj2yaml/elf2yaml.cpp
+++ b/llvm/tools/obj2yaml/elf2yaml.cpp
@@ -514,7 +514,7 @@ std::optional<DWARFYAML::Data> ELFDumper<ELFT>::dumpDWARFSections(
     std::vector<std::unique_ptr<ELFYAML::Chunk>> &Sections) {
   DWARFYAML::Data DWARF;
   for (std::unique_ptr<ELFYAML::Chunk> &C : Sections) {
-    if (!C->Name.startswith(".debug_"))
+    if (!C->Name.starts_with(".debug_"))
       continue;
 
     if (ELFYAML::RawContentSection *RawSec =
diff --git a/llvm/tools/obj2yaml/macho2yaml.cpp b/llvm/tools/obj2yaml/macho2yaml.cpp
index efd43a5f1285..c006c0d2cbea 100644
--- a/llvm/tools/obj2yaml/macho2yaml.cpp
+++ b/llvm/tools/obj2yaml/macho2yaml.cpp
@@ -151,7 +151,7 @@ static Error dumpDebugSection(StringRef SecName, DWARFContext &DCtx,
     dumpDebugLines(DCtx, DWARF);
     return Error::success();
   }
-  if (SecName.startswith("__debug_pub")) {
+  if (SecName.starts_with("__debug_pub")) {
     // FIXME: We should extract pub-section dumpers from this function.
     dumpDebugPubSections(DCtx, DWARF);
     return Error::success();
@@ -183,11 +183,11 @@ Expected<const char *> MachODumper::extractSections(
 
       // Copy data sections if requested.
       if ((RawSegment & ::RawSegments::data) &&
-          StringRef(S->segname).startswith("__DATA"))
+          StringRef(S->segname).starts_with("__DATA"))
         S->content =
             yaml::BinaryRef(Obj.getSectionContents(Sec.offset, Sec.size));
 
-      if (SecName.startswith("__debug_")) {
+      if (SecName.starts_with("__debug_")) {
         // If the DWARF section cannot be successfully parsed, emit raw content
         // instead of an entry in the DWARF section of the YAML.
         if (Error Err = dumpDebugSection(SecName, *DWARFCtx, Y.DWARF))
diff --git a/llvm/tools/obj2yaml/wasm2yaml.cpp b/llvm/tools/obj2yaml/wasm2yaml.cpp
index c450c02a05ec..8557a3840519 100644
--- a/llvm/tools/obj2yaml/wasm2yaml.cpp
+++ b/llvm/tools/obj2yaml/wasm2yaml.cpp
@@ -205,7 +205,7 @@ ErrorOr<WasmYAML::Object *> WasmDumper::dump() {
     std::unique_ptr<WasmYAML::Section> S;
     switch (WasmSec.Type) {
     case wasm::WASM_SEC_CUSTOM: {
-      if (WasmSec.Name.startswith("reloc.")) {
+      if (WasmSec.Name.starts_with("reloc.")) {
         // Relocations are attached the sections they apply to rather than
         // being represented as a custom section in the YAML output.
         continue;
diff --git a/llvm/tools/opt/opt.cpp b/llvm/tools/opt/opt.cpp
index 8d26580d8f38..e2ff73c9d073 100644
--- a/llvm/tools/opt/opt.cpp
+++ b/llvm/tools/opt/opt.cpp
@@ -377,7 +377,7 @@ static bool shouldPinPassToLegacyPM(StringRef Pass) {
       "callbrprepare",
   };
   for (const auto &P : PassNamePrefix)
-    if (Pass.startswith(P))
+    if (Pass.starts_with(P))
       return true;
   for (const auto &P : PassNameContain)
     if (Pass.contains(P))
diff --git a/llvm/tools/yaml2obj/yaml2obj.cpp b/llvm/tools/yaml2obj/yaml2obj.cpp
index ba1f54d2ecf7..b7f5356e22a9 100644
--- a/llvm/tools/yaml2obj/yaml2obj.cpp
+++ b/llvm/tools/yaml2obj/yaml2obj.cpp
@@ -78,9 +78,9 @@ static std::optional<std::string> preprocess(StringRef Buf,
 
   std::string Preprocessed;
   while (!Buf.empty()) {
-    if (Buf.startswith("[[")) {
+    if (Buf.starts_with("[[")) {
       size_t I = Buf.find_first_of("[]", 2);
-      if (Buf.substr(I).startswith("]]")) {
+      if (Buf.substr(I).starts_with("]]")) {
         StringRef MacroExpr = Buf.substr(2, I - 2);
         StringRef Macro;
         StringRef Default;
@@ -92,7 +92,7 @@ static std::optional<std::string> preprocess(StringRef Buf,
         std::optional<StringRef> Value;
         if (It != Defines.end())
           Value = It->second;
-        else if (!Default.empty() || MacroExpr.endswith("="))
+        else if (!Default.empty() || MacroExpr.ends_with("="))
           Value = Default;
 
         if (Value) {
diff --git a/llvm/utils/split-file/split-file.cpp b/llvm/utils/split-file/split-file.cpp
index 4a92c1be78a2..2ad04d6e42f2 100644
--- a/llvm/utils/split-file/split-file.cpp
+++ b/llvm/utils/split-file/split-file.cpp
@@ -75,9 +75,9 @@ static int handle(MemoryBuffer &inputBuf, StringRef input) {
   for (line_iterator i(inputBuf, /*SkipBlanks=*/false, '\0'); !i.is_at_eof();) {
     const int64_t lineNo = i.line_number();
     const StringRef line = *i++;
-    const size_t markerLen = line.startswith("//") ? 6 : 5;
+    const size_t markerLen = line.starts_with("//") ? 6 : 5;
     if (!(line.size() >= markerLen &&
-          line.substr(markerLen - 4).startswith("--- ")))
+          line.substr(markerLen - 4).starts_with("--- ")))
       continue;
     separator = line.substr(0, markerLen);
     const StringRef partName = line.substr(markerLen);
diff --git a/llvm/utils/yaml-bench/YAMLBench.cpp b/llvm/utils/yaml-bench/YAMLBench.cpp
index 8b4043ef66cb..50e55538a011 100644
--- a/llvm/utils/yaml-bench/YAMLBench.cpp
+++ b/llvm/utils/yaml-bench/YAMLBench.cpp
@@ -70,7 +70,7 @@ static raw_ostream &operator <<(raw_ostream &os, const indent &in) {
 /// Pretty print a tag by replacing tag:yaml.org,2002: with !!.
 static std::string prettyTag(yaml::Node *N) {
   std::string Tag = N->getVerbatimTag();
-  if (StringRef(Tag).startswith("tag:yaml.org,2002:")) {
+  if (StringRef(Tag).starts_with("tag:yaml.org,2002:")) {
     std::string Ret = "!!";
     Ret += StringRef(Tag).substr(18);
     return Ret;
-- 
GitLab


From 95dce3e86d698af74f4c2cdd4648cf0f8cfb71f7 Mon Sep 17 00:00:00 2001
From: Ivan Radanov Ivanov <ivanov.i.aa@m.titech.ac.jp>
Date: Tue, 12 Dec 2023 14:00:06 +0900
Subject: [PATCH 221/349] Link NVVM translation in the to LLVMIR registration
 library

---
 mlir/lib/Target/LLVMIR/CMakeLists.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/mlir/lib/Target/LLVMIR/CMakeLists.txt b/mlir/lib/Target/LLVMIR/CMakeLists.txt
index 531c15a8703e..94280a2ec901 100644
--- a/mlir/lib/Target/LLVMIR/CMakeLists.txt
+++ b/mlir/lib/Target/LLVMIR/CMakeLists.txt
@@ -86,4 +86,5 @@ add_mlir_translation_library(MLIRFromLLVMIRTranslationRegistration
 
   LINK_LIBS PUBLIC
   MLIRLLVMIRToLLVMTranslation
+  MLIRLLVMIRToNVVMTranslation
   )
-- 
GitLab


From dc5570319676c14c48440b4ee87c8cfb35102ff6 Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu@sifive.com>
Date: Tue, 12 Dec 2023 13:17:47 +0800
Subject: [PATCH 222/349] [RISCV] Update the interface of sifive vqmaccqoq
 (#74284)

The
spec(https://sifive.cdn.prismic.io/sifive/60d5a660-3af0-49a3-a904-d2bbb1a21517_int8-matmul-spec.pdf)
is updated.
---
 .../clang/Basic/riscv_sifive_vector.td        | 26 +++++---
 .../non-overloaded/sf_vqmacc_4x8x4.c          | 24 ++++----
 .../non-overloaded/sf_vqmaccsu_4x8x4.c        | 24 ++++----
 .../non-overloaded/sf_vqmaccu_4x8x4.c         | 24 ++++----
 .../non-overloaded/sf_vqmaccus_4x8x4.c        | 24 ++++----
 .../non-policy/overloaded/sf_vqmacc_4x8x4.c   | 24 ++++----
 .../non-policy/overloaded/sf_vqmaccsu_4x8x4.c | 24 ++++----
 .../non-policy/overloaded/sf_vqmaccu_4x8x4.c  | 24 ++++----
 .../non-policy/overloaded/sf_vqmaccus_4x8x4.c | 24 ++++----
 .../policy/non-overloaded/sf_vqmacc_4x8x4.c   | 24 ++++----
 .../policy/non-overloaded/sf_vqmaccsu_4x8x4.c | 24 ++++----
 .../policy/non-overloaded/sf_vqmaccu_4x8x4.c  | 24 ++++----
 .../policy/non-overloaded/sf_vqmaccus_4x8x4.c | 24 ++++----
 .../policy/overloaded/sf_vqmacc_4x8x4.c       | 24 ++++----
 .../policy/overloaded/sf_vqmaccsu_4x8x4.c     | 24 ++++----
 .../policy/overloaded/sf_vqmaccu_4x8x4.c      | 24 ++++----
 .../policy/overloaded/sf_vqmaccus_4x8x4.c     | 24 ++++----
 clang/test/Sema/rvv-required-features.c       | 18 +-----
 llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td    | 61 ++++++++++++-------
 .../test/CodeGen/RISCV/rvv/sf_vqmacc_4x8x4.ll | 58 +++++++++---------
 .../CodeGen/RISCV/rvv/sf_vqmaccsu_4x8x4.ll    | 58 +++++++++---------
 .../CodeGen/RISCV/rvv/sf_vqmaccu_4x8x4.ll     | 58 +++++++++---------
 .../CodeGen/RISCV/rvv/sf_vqmaccus_4x8x4.ll    | 58 +++++++++---------
 23 files changed, 361 insertions(+), 360 deletions(-)

diff --git a/clang/include/clang/Basic/riscv_sifive_vector.td b/clang/include/clang/Basic/riscv_sifive_vector.td
index bb54e2664186..61c2ff52d9f7 100644
--- a/clang/include/clang/Basic/riscv_sifive_vector.td
+++ b/clang/include/clang/Basic/riscv_sifive_vector.td
@@ -112,7 +112,7 @@ multiclass RVVVFWMACCBuiltinSet<list<list<string>> suffixes_prototypes> {
     defm NAME : RVVOutOp1Op2BuiltinSet<NAME, "b", suffixes_prototypes>;
 }
 
-multiclass RVVVQMACCBuiltinSet<list<list<string>> suffixes_prototypes> {
+multiclass RVVVQMACCDODBuiltinSet<list<list<string>> suffixes_prototypes> {
   let OverloadedName = NAME,
       Name = NAME,
       HasMasked = false,
@@ -120,6 +120,14 @@ multiclass RVVVQMACCBuiltinSet<list<list<string>> suffixes_prototypes> {
     defm NAME : RVVOutOp1Op2BuiltinSet<NAME, "i", suffixes_prototypes>;
 }
 
+multiclass RVVVQMACCQOQBuiltinSet<list<list<string>> suffixes_prototypes> {
+   let OverloadedName = NAME,
+       Name = NAME,
+       HasMasked = false,
+       Log2LMUL = [-1, 0, 1, 2] in
+     defm NAME : RVVOutOp1Op2BuiltinSet<NAME, "s", suffixes_prototypes>;
+}
+
 multiclass RVVVFNRCLIPBuiltinSet<string suffix, string prototype, string type_range> {
   let Log2LMUL = [-3, -2, -1, 0, 1, 2],
       Name = NAME,
@@ -130,18 +138,18 @@ multiclass RVVVFNRCLIPBuiltinSet<string suffix, string prototype, string type_ra
 
 let UnMaskedPolicyScheme = HasPolicyOperand in
   let RequiredFeatures = ["Xsfvqmaccdod"] in {
-    defm sf_vqmaccu_2x8x2 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)Uv"]]>;
-    defm sf_vqmacc_2x8x2 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)v"]]>;
-    defm sf_vqmaccus_2x8x2 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)v"]]>;
-    defm sf_vqmaccsu_2x8x2 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)Uv"]]>;
+    defm sf_vqmaccu_2x8x2 : RVVVQMACCDODBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)Uv"]]>;
+    defm sf_vqmacc_2x8x2 : RVVVQMACCDODBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)v"]]>;
+    defm sf_vqmaccus_2x8x2 : RVVVQMACCDODBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)v"]]>;
+    defm sf_vqmaccsu_2x8x2 : RVVVQMACCDODBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)Uv"]]>;
   }
 
 let UnMaskedPolicyScheme = HasPolicyOperand in
   let RequiredFeatures = ["Xsfvqmaccqoq"] in {
-    defm sf_vqmaccu_4x8x4 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)Uv"]]>;
-    defm sf_vqmacc_4x8x4 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)v"]]>;
-    defm sf_vqmaccus_4x8x4 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)v"]]>;
-    defm sf_vqmaccsu_4x8x4 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)Uv"]]>;
+    defm sf_vqmaccu_4x8x4 : RVVVQMACCQOQBuiltinSet<[["", "w", "ww(FixedSEW:8)SUv(FixedSEW:8)Uw"]]>;
+    defm sf_vqmacc_4x8x4 : RVVVQMACCQOQBuiltinSet<[["", "w", "ww(FixedSEW:8)Sv(FixedSEW:8)w"]]>;
+    defm sf_vqmaccus_4x8x4 : RVVVQMACCQOQBuiltinSet<[["", "w", "ww(FixedSEW:8)SUv(FixedSEW:8)w"]]>;
+    defm sf_vqmaccsu_4x8x4 : RVVVQMACCQOQBuiltinSet<[["", "w", "ww(FixedSEW:8)Sv(FixedSEW:8)Uw"]]>;
   }
 
 let UnMaskedPolicyScheme = HasPolicyOperand in
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmacc_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmacc_4x8x4.c
index 935cb2e007d3..80e1c443eb54 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmacc_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmacc_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmacc_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmacc_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vint8mf2_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4_i32m1(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmacc_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmacc_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4_i32m2(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmacc_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmacc_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4_i32m4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmacc_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vint8m8_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmacc_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4_i32m8(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c
index f34517b24bcf..8c0a6218c1d2 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vuint8mf2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4_i32m1(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4_i32m2(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4_i32m4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vuint8m8_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4_i32m8(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c
index ab7f6627ad1f..b40891f417f2 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_4x8x4_i32m1
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmaccu_4x8x4_i32m1(vint32m1_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmaccu_4x8x4_i32m1(vint32m1_t vd, vuint8m1_t vs1, vuint8mf2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4_i32m1(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_4x8x4_i32m2
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmaccu_4x8x4_i32m2(vint32m2_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmaccu_4x8x4_i32m2(vint32m2_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4_i32m2(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_4x8x4_i32m4
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmaccu_4x8x4_i32m4(vint32m4_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmaccu_4x8x4_i32m4(vint32m4_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4_i32m4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_4x8x4_i32m8
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmaccu_4x8x4_i32m8(vint32m8_t vd, vuint8m1_t vs1, vuint8m8_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmaccu_4x8x4_i32m8(vint32m8_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4_i32m8(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c
index d0bcdcbf40cc..d106aab64c51 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_4x8x4_i32m1
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmaccus_4x8x4_i32m1(vint32m1_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmaccus_4x8x4_i32m1(vint32m1_t vd, vuint8m1_t vs1, vint8mf2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4_i32m1(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_4x8x4_i32m2
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmaccus_4x8x4_i32m2(vint32m2_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmaccus_4x8x4_i32m2(vint32m2_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4_i32m2(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_4x8x4_i32m4
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmaccus_4x8x4_i32m4(vint32m4_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmaccus_4x8x4_i32m4(vint32m4_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4_i32m4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_4x8x4_i32m8
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmaccus_4x8x4_i32m8(vint32m8_t vd, vuint8m1_t vs1, vint8m8_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmaccus_4x8x4_i32m8(vint32m8_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4_i32m8(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmacc_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmacc_4x8x4.c
index 839d09c4f9a9..88fae7306944 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmacc_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmacc_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmacc_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmacc_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vint8mf2_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmacc_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmacc_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmacc_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmacc_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmacc_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vint8m8_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmacc_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccsu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccsu_4x8x4.c
index b18853043e92..0aec4bfd9fe2 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccsu_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccsu_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vuint8mf2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vuint8m8_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccu_4x8x4.c
index 4cb966b08f23..81965e86f77c 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccu_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccu_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_4x8x4_i32m1
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmaccu_4x8x4_i32m1(vint32m1_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmaccu_4x8x4_i32m1(vint32m1_t vd, vuint8m1_t vs1, vuint8mf2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_4x8x4_i32m2
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmaccu_4x8x4_i32m2(vint32m2_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmaccu_4x8x4_i32m2(vint32m2_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_4x8x4_i32m4
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmaccu_4x8x4_i32m4(vint32m4_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmaccu_4x8x4_i32m4(vint32m4_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_4x8x4_i32m8
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmaccu_4x8x4_i32m8(vint32m8_t vd, vuint8m1_t vs1, vuint8m8_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmaccu_4x8x4_i32m8(vint32m8_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccus_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccus_4x8x4.c
index f558151f88a3..f2544cf3ef2a 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccus_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccus_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_4x8x4_i32m1
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmaccus_4x8x4_i32m1(vint32m1_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmaccus_4x8x4_i32m1(vint32m1_t vd, vuint8m1_t vs1, vint8mf2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_4x8x4_i32m2
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmaccus_4x8x4_i32m2(vint32m2_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmaccus_4x8x4_i32m2(vint32m2_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_4x8x4_i32m4
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmaccus_4x8x4_i32m4(vint32m4_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmaccus_4x8x4_i32m4(vint32m4_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_4x8x4_i32m8
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmaccus_4x8x4_i32m8(vint32m8_t vd, vuint8m1_t vs1, vint8m8_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmaccus_4x8x4_i32m8(vint32m8_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmacc_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmacc_4x8x4.c
index 05c10840cabf..8fdeac62a31f 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmacc_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmacc_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1_tu
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmacc_4x8x4_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmacc_4x8x4_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vint8mf2_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4_i32m1_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2_tu
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmacc_4x8x4_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmacc_4x8x4_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4_i32m2_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4_tu
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmacc_4x8x4_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmacc_4x8x4_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4_i32m4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8_tu
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmacc_4x8x4_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vint8m8_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmacc_4x8x4_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4_i32m8_tu(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccsu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccsu_4x8x4.c
index bce1a4e9443f..e02c790dfbeb 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccsu_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccsu_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1_tu
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vuint8mf2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4_i32m1_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2_tu
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4_i32m2_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4_tu
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4_i32m4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8_tu
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vuint8m8_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4_i32m8_tu(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccu_4x8x4.c
index 36aaae9caebf..ddeb6de00716 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccu_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccu_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_4x8x4_i32m1_tu
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmaccu_4x8x4_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmaccu_4x8x4_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vuint8mf2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4_i32m1_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_4x8x4_i32m2_tu
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmaccu_4x8x4_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmaccu_4x8x4_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4_i32m2_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_4x8x4_i32m4_tu
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmaccu_4x8x4_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmaccu_4x8x4_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4_i32m4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_4x8x4_i32m8_tu
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmaccu_4x8x4_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vuint8m8_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmaccu_4x8x4_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4_i32m8_tu(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccus_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccus_4x8x4.c
index f5ac2bf0f1f3..397e406c2ee5 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccus_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccus_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_4x8x4_i32m1_tu
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmaccus_4x8x4_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmaccus_4x8x4_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vint8mf2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4_i32m1_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_4x8x4_i32m2_tu
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmaccus_4x8x4_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmaccus_4x8x4_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4_i32m2_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_4x8x4_i32m4_tu
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmaccus_4x8x4_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmaccus_4x8x4_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4_i32m4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_4x8x4_i32m8_tu
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmaccus_4x8x4_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vint8m8_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmaccus_4x8x4_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4_i32m8_tu(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmacc_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmacc_4x8x4.c
index 531bc2b2b942..7b3b25a20331 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmacc_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmacc_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1_tu
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmacc_4x8x4_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmacc_4x8x4_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vint8mf2_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2_tu
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmacc_4x8x4_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmacc_4x8x4_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4_tu
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmacc_4x8x4_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmacc_4x8x4_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8_tu
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmacc_4x8x4_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vint8m8_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmacc_4x8x4_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4_tu(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccsu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccsu_4x8x4.c
index 23bba523aaa4..2f3cbeec26fc 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccsu_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccsu_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1_tu
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vuint8mf2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2_tu
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4_tu
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8_tu
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vuint8m8_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4_tu(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccu_4x8x4.c
index 950688c6c785..1f2b2a1c8645 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccu_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccu_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_4x8x4_i32m1_tu
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmaccu_4x8x4_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmaccu_4x8x4_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vuint8mf2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_4x8x4_i32m2_tu
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmaccu_4x8x4_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmaccu_4x8x4_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_4x8x4_i32m4_tu
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmaccu_4x8x4_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmaccu_4x8x4_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_4x8x4_i32m8_tu
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmaccu_4x8x4_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vuint8m8_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmaccu_4x8x4_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4_tu(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccus_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccus_4x8x4.c
index 7bdce95043ee..923234fe8e2b 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccus_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccus_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_4x8x4_i32m1_tu
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmaccus_4x8x4_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmaccus_4x8x4_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vint8mf2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_4x8x4_i32m2_tu
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmaccus_4x8x4_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmaccus_4x8x4_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_4x8x4_i32m4_tu
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmaccus_4x8x4_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmaccus_4x8x4_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_4x8x4_i32m8_tu
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmaccus_4x8x4_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vint8m8_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmaccus_4x8x4_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4_tu(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/Sema/rvv-required-features.c b/clang/test/Sema/rvv-required-features.c
index 2714ef04b9bf..5846f338aa80 100644
--- a/clang/test/Sema/rvv-required-features.c
+++ b/clang/test/Sema/rvv-required-features.c
@@ -1,8 +1,6 @@
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp \
-// RUN:     -target-feature +xsfvqmaccdod -target-feature +xsfvqmaccqoq \
-// RUN:     -target-feature +experimental-zvfbfmin -target-feature +xsfvfwmaccqqq \
-// RUN:     -target-feature +xsfvfnrclipxfqf %s -fsyntax-only -verify
+// RUN:     -target-feature +xsfvqmaccdod -target-feature +xsfvqmaccqoq %s -fsyntax-only -verify
 
 // expected-no-diagnostics
 
@@ -25,18 +23,6 @@ void test_xsfvqmaccdod(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
   __riscv_sf_vqmacc_2x8x2(vd, vs1, vs2, vl);
 }
 
-void test_xsfvqmaccqoq(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
+void test_xsfvqmaccqoq(vint32m1_t vd, vint8m1_t vs1, vint8mf2_t vs2, size_t vl) {
   __riscv_sf_vqmacc_4x8x4(vd, vs1, vs2, vl);
 }
-
-void test_xsfvfwmaccqqq(vfloat32m1_t vd, vbfloat16m1_t vs1, vbfloat16mf2_t vs2, size_t vl) {
-  __riscv_sf_vfwmacc_4x4x4(vd, vs1, vs2, vl);
-}
-
-void test_xsfvfnrclipxufqf(vfloat32m1_t vs1, float rs2, size_t vl) {
-  __riscv_sf_vfnrclip_xu_f_qf(vs1, rs2, vl);
-}
-
-void test_xsfvfnrclipxfqf(vfloat32m1_t vs1, float rs2, size_t vl) {
-  __riscv_sf_vfnrclip_x_f_qf(vs1, rs2, vl);
-}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
index fa618b437ce7..9812aa501e04 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
@@ -349,14 +349,20 @@ multiclass VPseudoSiFiveVMACC<string mx, VReg vd_type, VReg vs2_type,
       : VPseudoTernaryNoMaskWithPolicy<vd_type, V_M1.vrclass, vs2_type, Constraint>;
 }
 
-multiclass VPseudoSiFiveVQMACC<string Constraint = ""> {
+multiclass VPseudoSiFiveVQMACCDOD<string Constraint = ""> {
   foreach m = MxListVF8 in
     defm NAME : VPseudoSiFiveVMACC<m.MX, m.vrclass, m.vrclass, Constraint>;
 }
 
+multiclass VPseudoSiFiveVQMACCQOQ<string Constraint = ""> {
+   foreach m = MxListVF8 in
+     defm NAME : VPseudoSiFiveVMACC<m.MX, m.vrclass, m.f2vrclass, Constraint>;
+}
+
 multiclass VPseudoSiFiveVFWMACC<string Constraint = ""> {
-  foreach m = MxListFW in
-    defm NAME : VPseudoSiFiveVMACC<m.MX, m.wvrclass, m.vrclass, Constraint>;
+  foreach i = [0, 1, 2, 3, 4] in
+    defm NAME : VPseudoSiFiveVMACC<MxListVF4[i].MX, MxListFW[i].wvrclass,
+                                   MxListFW[i].vrclass, Constraint>;
 }
 
 multiclass VPseudoSiFiveVFNRCLIP<string Constraint = "@earlyclobber $rd"> {
@@ -398,17 +404,17 @@ let Predicates = [HasVendorXSfvcp] in {
 }
 
 let Predicates = [HasVendorXSfvqmaccdod] in {
-  defm VQMACCU_2x8x2  : VPseudoSiFiveVQMACC;
-  defm VQMACC_2x8x2   : VPseudoSiFiveVQMACC;
-  defm VQMACCUS_2x8x2 : VPseudoSiFiveVQMACC;
-  defm VQMACCSU_2x8x2 : VPseudoSiFiveVQMACC;
+  defm VQMACCU_2x8x2  : VPseudoSiFiveVQMACCDOD;
+  defm VQMACC_2x8x2   : VPseudoSiFiveVQMACCDOD;
+  defm VQMACCUS_2x8x2 : VPseudoSiFiveVQMACCDOD;
+  defm VQMACCSU_2x8x2 : VPseudoSiFiveVQMACCDOD;
 }
 
 let Predicates = [HasVendorXSfvqmaccqoq] in {
-  defm VQMACCU_4x8x4  : VPseudoSiFiveVQMACC;
-  defm VQMACC_4x8x4   : VPseudoSiFiveVQMACC;
-  defm VQMACCUS_4x8x4 : VPseudoSiFiveVQMACC;
-  defm VQMACCSU_4x8x4 : VPseudoSiFiveVQMACC;
+  defm VQMACCU_4x8x4  : VPseudoSiFiveVQMACCQOQ;
+  defm VQMACC_4x8x4   : VPseudoSiFiveVQMACCQOQ;
+  defm VQMACCUS_4x8x4 : VPseudoSiFiveVQMACCQOQ;
+  defm VQMACCSU_4x8x4 : VPseudoSiFiveVQMACCQOQ;
 }
 
 let Predicates = [HasVendorXSfvfwmaccqqq] in {
@@ -559,21 +565,30 @@ multiclass VPatVMACC<string intrinsic, string instruction, string kind,
     def : VPatTernaryNoMaskWithPolicy<"int_riscv_sf_" # intrinsic,
                                       "Pseudo" # instruction, kind, VdInfo.Vector,
                                       vec_m1, Vs2Info.Vector,
-                                      Vs2Info.Log2SEW, Vs2Info.LMul,
+                                      Vs2Info.Log2SEW, VdInfo.LMul,
                                       VdInfo.RegClass, VR, Vs2Info.RegClass>;
   }
 }
 
-defset list<VTypeInfoToWide> VQMACCInfoPairs = {
+defset list<VTypeInfoToWide> VQMACCDODInfoPairs = {
   def : VTypeInfoToWide<VI8M1, VI32M1>;
   def : VTypeInfoToWide<VI8M2, VI32M2>;
   def : VTypeInfoToWide<VI8M4, VI32M4>;
   def : VTypeInfoToWide<VI8M8, VI32M8>;
 }
 
-multiclass VPatVQMACC<string intrinsic, string instruction, string kind>
-    : VPatVMACC<intrinsic, instruction, kind, VQMACCInfoPairs, vint8m1_t>;
+defset list<VTypeInfoToWide> VQMACCQOQInfoPairs = {
+   def : VTypeInfoToWide<VI8MF2, VI32M1>;
+   def : VTypeInfoToWide<VI8M1, VI32M2>;
+   def : VTypeInfoToWide<VI8M2, VI32M4>;
+   def : VTypeInfoToWide<VI8M4, VI32M8>;
+}
+
+multiclass VPatVQMACCDOD<string intrinsic, string instruction, string kind>
+    : VPatVMACC<intrinsic, instruction, kind, VQMACCDODInfoPairs, vint8m1_t>;
 
+multiclass VPatVQMACCQOQ<string intrinsic, string instruction, string kind>
+    : VPatVMACC<intrinsic, instruction, kind, VQMACCQOQInfoPairs, vint8m1_t>;
 
 multiclass VPatVFWMACC<string intrinsic, string instruction, string kind>
     : VPatVMACC<intrinsic, instruction, kind, AllWidenableBFloatToFloatVectors,
@@ -635,17 +650,17 @@ let Predicates = [HasVendorXSfvcp] in {
 }
 
 let Predicates = [HasVendorXSfvqmaccdod] in {
-  defm : VPatVQMACC<"vqmaccu_2x8x2", "VQMACCU", "2x8x2">;
-  defm : VPatVQMACC<"vqmacc_2x8x2", "VQMACC", "2x8x2">;
-  defm : VPatVQMACC<"vqmaccus_2x8x2", "VQMACCUS", "2x8x2">;
-  defm : VPatVQMACC<"vqmaccsu_2x8x2", "VQMACCSU", "2x8x2">;
+  defm : VPatVQMACCDOD<"vqmaccu_2x8x2", "VQMACCU", "2x8x2">;
+  defm : VPatVQMACCDOD<"vqmacc_2x8x2", "VQMACC", "2x8x2">;
+  defm : VPatVQMACCDOD<"vqmaccus_2x8x2", "VQMACCUS", "2x8x2">;
+  defm : VPatVQMACCDOD<"vqmaccsu_2x8x2", "VQMACCSU", "2x8x2">;
 }
 
 let Predicates = [HasVendorXSfvqmaccqoq] in {
-  defm : VPatVQMACC<"vqmaccu_4x8x4", "VQMACCU", "4x8x4">;
-  defm : VPatVQMACC<"vqmacc_4x8x4", "VQMACC", "4x8x4">;
-  defm : VPatVQMACC<"vqmaccus_4x8x4", "VQMACCUS", "4x8x4">;
-  defm : VPatVQMACC<"vqmaccsu_4x8x4", "VQMACCSU", "4x8x4">;
+  defm : VPatVQMACCQOQ<"vqmaccu_4x8x4", "VQMACCU", "4x8x4">;
+  defm : VPatVQMACCQOQ<"vqmacc_4x8x4", "VQMACC", "4x8x4">;
+  defm : VPatVQMACCQOQ<"vqmaccus_4x8x4", "VQMACCUS", "4x8x4">;
+  defm : VPatVQMACCQOQ<"vqmaccsu_4x8x4", "VQMACCSU", "4x8x4">;
 }
 
 let Predicates = [HasVendorXSfvfwmaccqqq] in {
diff --git a/llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_4x8x4.ll b/llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_4x8x4.ll
index 843e4bda4d12..300fda43ada4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_4x8x4.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_4x8x4.ll
@@ -7,10 +7,10 @@
 declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8(
   <vscale x 2 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
   iXLen, iXLen);
 
-define <vscale x 2 x i32> @intrinsic_vqmacc_4x8x4_tu_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vqmacc_4x8x4_tu_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmacc_4x8x4_tu_i32m1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
@@ -20,13 +20,13 @@ entry:
   %a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8(
     <vscale x 2 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 8 x i8> %2,
+    <vscale x 4 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 2 x i32> %a
 }
 
-define <vscale x 2 x i32> @intrinsic_vqmacc_4x8x4_ta_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vqmacc_4x8x4_ta_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmacc_4x8x4_ta_i32m1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
@@ -36,7 +36,7 @@ entry:
   %a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8(
     <vscale x 2 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 8 x i8> %2,
+    <vscale x 4 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 2 x i32> %a
@@ -45,36 +45,36 @@ entry:
 declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8(
   <vscale x 4 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
   iXLen, iXLen);
 
-define <vscale x 4 x i32> @intrinsic_vqmacc_4x8x4_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
+define <vscale x 4 x i32> @intrinsic_vqmacc_4x8x4_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmacc_4x8x4_tu_i32m2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
-; CHECK-NEXT:    sf.vqmacc.4x8x4 v8, v10, v12
+; CHECK-NEXT:    sf.vqmacc.4x8x4 v8, v10, v11
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8(
     <vscale x 4 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 16 x i8> %2,
+    <vscale x 8 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 4 x i32> %a
 }
 
-define <vscale x 4 x i32> @intrinsic_vqmacc_4x8x4_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
+define <vscale x 4 x i32> @intrinsic_vqmacc_4x8x4_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmacc_4x8x4_ta_i32m2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT:    sf.vqmacc.4x8x4 v8, v10, v12
+; CHECK-NEXT:    sf.vqmacc.4x8x4 v8, v10, v11
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8(
     <vscale x 4 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 16 x i8> %2,
+    <vscale x 8 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 4 x i32> %a
@@ -83,36 +83,36 @@ entry:
 declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8(
   <vscale x 8 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 32 x i8>,
+  <vscale x 16 x i8>,
   iXLen, iXLen);
 
-define <vscale x 8 x i32> @intrinsic_vqmacc_4x8x4_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
+define <vscale x 8 x i32> @intrinsic_vqmacc_4x8x4_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmacc_4x8x4_tu_i32m4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
-; CHECK-NEXT:    sf.vqmacc.4x8x4 v8, v12, v16
+; CHECK-NEXT:    sf.vqmacc.4x8x4 v8, v12, v14
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 32 x i8> %2,
+    <vscale x 16 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 8 x i32> %a
 }
 
-define <vscale x 8 x i32> @intrinsic_vqmacc_4x8x4_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
+define <vscale x 8 x i32> @intrinsic_vqmacc_4x8x4_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmacc_4x8x4_ta_i32m4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT:    sf.vqmacc.4x8x4 v8, v12, v16
+; CHECK-NEXT:    sf.vqmacc.4x8x4 v8, v12, v14
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 32 x i8> %2,
+    <vscale x 16 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 8 x i32> %a
@@ -121,38 +121,36 @@ entry:
 declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8(
   <vscale x 16 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 64 x i8>,
+  <vscale x 32 x i8>,
   iXLen, iXLen);
 
-define <vscale x 16 x i32> @intrinsic_vqmacc_4x8x4_tu_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
+define <vscale x 16 x i32> @intrinsic_vqmacc_4x8x4_tu_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmacc_4x8x4_tu_i32m8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vl8r.v v24, (a0)
-; CHECK-NEXT:    vsetvli zero, a1, e8, m1, tu, ma
-; CHECK-NEXT:    sf.vqmacc.4x8x4 v8, v16, v24
+; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
+; CHECK-NEXT:    sf.vqmacc.4x8x4 v8, v16, v20
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8(
     <vscale x 16 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 64 x i8> %2,
+    <vscale x 32 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 16 x i32> %a
 }
 
-define <vscale x 16 x i32> @intrinsic_vqmacc_4x8x4_ta_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
+define <vscale x 16 x i32> @intrinsic_vqmacc_4x8x4_ta_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmacc_4x8x4_ta_i32m8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vl8r.v v24, (a0)
-; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
-; CHECK-NEXT:    sf.vqmacc.4x8x4 v8, v16, v24
+; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-NEXT:    sf.vqmacc.4x8x4 v8, v16, v20
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8(
     <vscale x 16 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 64 x i8> %2,
+    <vscale x 32 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 16 x i32> %a
diff --git a/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_4x8x4.ll b/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_4x8x4.ll
index 45a3b22d9618..1df81527850e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_4x8x4.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_4x8x4.ll
@@ -7,10 +7,10 @@
 declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8(
   <vscale x 2 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
   iXLen, iXLen);
 
-define <vscale x 2 x i32> @intrinsic_vqmaccsu_4x8x4_tu_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vqmaccsu_4x8x4_tu_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_tu_i32m1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
@@ -20,13 +20,13 @@ entry:
   %a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8(
     <vscale x 2 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 8 x i8> %2,
+    <vscale x 4 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 2 x i32> %a
 }
 
-define <vscale x 2 x i32> @intrinsic_vqmaccsu_4x8x4_ta_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vqmaccsu_4x8x4_ta_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_ta_i32m1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
@@ -36,7 +36,7 @@ entry:
   %a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8(
     <vscale x 2 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 8 x i8> %2,
+    <vscale x 4 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 2 x i32> %a
@@ -45,36 +45,36 @@ entry:
 declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8(
   <vscale x 4 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
   iXLen, iXLen);
 
-define <vscale x 4 x i32> @intrinsic_vqmaccsu_4x8x4_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
+define <vscale x 4 x i32> @intrinsic_vqmaccsu_4x8x4_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_tu_i32m2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
-; CHECK-NEXT:    sf.vqmaccsu.4x8x4 v8, v10, v12
+; CHECK-NEXT:    sf.vqmaccsu.4x8x4 v8, v10, v11
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8(
     <vscale x 4 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 16 x i8> %2,
+    <vscale x 8 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 4 x i32> %a
 }
 
-define <vscale x 4 x i32> @intrinsic_vqmaccsu_4x8x4_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
+define <vscale x 4 x i32> @intrinsic_vqmaccsu_4x8x4_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_ta_i32m2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT:    sf.vqmaccsu.4x8x4 v8, v10, v12
+; CHECK-NEXT:    sf.vqmaccsu.4x8x4 v8, v10, v11
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8(
     <vscale x 4 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 16 x i8> %2,
+    <vscale x 8 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 4 x i32> %a
@@ -83,36 +83,36 @@ entry:
 declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8(
   <vscale x 8 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 32 x i8>,
+  <vscale x 16 x i8>,
   iXLen, iXLen);
 
-define <vscale x 8 x i32> @intrinsic_vqmaccsu_4x8x4_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
+define <vscale x 8 x i32> @intrinsic_vqmaccsu_4x8x4_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_tu_i32m4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
-; CHECK-NEXT:    sf.vqmaccsu.4x8x4 v8, v12, v16
+; CHECK-NEXT:    sf.vqmaccsu.4x8x4 v8, v12, v14
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 32 x i8> %2,
+    <vscale x 16 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 8 x i32> %a
 }
 
-define <vscale x 8 x i32> @intrinsic_vqmaccsu_4x8x4_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
+define <vscale x 8 x i32> @intrinsic_vqmaccsu_4x8x4_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_ta_i32m4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT:    sf.vqmaccsu.4x8x4 v8, v12, v16
+; CHECK-NEXT:    sf.vqmaccsu.4x8x4 v8, v12, v14
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 32 x i8> %2,
+    <vscale x 16 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 8 x i32> %a
@@ -121,38 +121,36 @@ entry:
 declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8(
   <vscale x 16 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 64 x i8>,
+  <vscale x 32 x i8>,
   iXLen, iXLen);
 
-define <vscale x 16 x i32> @intrinsic_vqmaccsu_4x8x4_tu_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
+define <vscale x 16 x i32> @intrinsic_vqmaccsu_4x8x4_tu_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_tu_i32m8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vl8r.v v24, (a0)
-; CHECK-NEXT:    vsetvli zero, a1, e8, m1, tu, ma
-; CHECK-NEXT:    sf.vqmaccsu.4x8x4 v8, v16, v24
+; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
+; CHECK-NEXT:    sf.vqmaccsu.4x8x4 v8, v16, v20
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8(
     <vscale x 16 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 64 x i8> %2,
+    <vscale x 32 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 16 x i32> %a
 }
 
-define <vscale x 16 x i32> @intrinsic_vqmaccsu_4x8x4_ta_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
+define <vscale x 16 x i32> @intrinsic_vqmaccsu_4x8x4_ta_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_ta_i32m8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vl8r.v v24, (a0)
-; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
-; CHECK-NEXT:    sf.vqmaccsu.4x8x4 v8, v16, v24
+; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-NEXT:    sf.vqmaccsu.4x8x4 v8, v16, v20
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8(
     <vscale x 16 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 64 x i8> %2,
+    <vscale x 32 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 16 x i32> %a
diff --git a/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_4x8x4.ll b/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_4x8x4.ll
index 9d15ab68a091..be2ce2fffe31 100644
--- a/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_4x8x4.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_4x8x4.ll
@@ -7,10 +7,10 @@
 declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv8i8(
   <vscale x 2 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
   iXLen, iXLen);
 
-define <vscale x 2 x i32> @intrinsic_vqmaccu_4x8x4_tu_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vqmaccu_4x8x4_tu_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_tu_i32m1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
@@ -20,13 +20,13 @@ entry:
   %a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv8i8(
     <vscale x 2 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 8 x i8> %2,
+    <vscale x 4 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 2 x i32> %a
 }
 
-define <vscale x 2 x i32> @intrinsic_vqmaccu_4x8x4_ta_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vqmaccu_4x8x4_ta_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_ta_i32m1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
@@ -36,7 +36,7 @@ entry:
   %a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv8i8(
     <vscale x 2 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 8 x i8> %2,
+    <vscale x 4 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 2 x i32> %a
@@ -45,36 +45,36 @@ entry:
 declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv16i8(
   <vscale x 4 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
   iXLen, iXLen);
 
-define <vscale x 4 x i32> @intrinsic_vqmaccu_4x8x4_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
+define <vscale x 4 x i32> @intrinsic_vqmaccu_4x8x4_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_tu_i32m2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
-; CHECK-NEXT:    sf.vqmaccu.4x8x4 v8, v10, v12
+; CHECK-NEXT:    sf.vqmaccu.4x8x4 v8, v10, v11
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv16i8(
     <vscale x 4 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 16 x i8> %2,
+    <vscale x 8 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 4 x i32> %a
 }
 
-define <vscale x 4 x i32> @intrinsic_vqmaccu_4x8x4_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
+define <vscale x 4 x i32> @intrinsic_vqmaccu_4x8x4_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_ta_i32m2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT:    sf.vqmaccu.4x8x4 v8, v10, v12
+; CHECK-NEXT:    sf.vqmaccu.4x8x4 v8, v10, v11
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv16i8(
     <vscale x 4 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 16 x i8> %2,
+    <vscale x 8 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 4 x i32> %a
@@ -83,36 +83,36 @@ entry:
 declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv32i8(
   <vscale x 8 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 32 x i8>,
+  <vscale x 16 x i8>,
   iXLen, iXLen);
 
-define <vscale x 8 x i32> @intrinsic_vqmaccu_4x8x4_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
+define <vscale x 8 x i32> @intrinsic_vqmaccu_4x8x4_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_tu_i32m4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
-; CHECK-NEXT:    sf.vqmaccu.4x8x4 v8, v12, v16
+; CHECK-NEXT:    sf.vqmaccu.4x8x4 v8, v12, v14
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv32i8(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 32 x i8> %2,
+    <vscale x 16 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 8 x i32> %a
 }
 
-define <vscale x 8 x i32> @intrinsic_vqmaccu_4x8x4_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
+define <vscale x 8 x i32> @intrinsic_vqmaccu_4x8x4_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_ta_i32m4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT:    sf.vqmaccu.4x8x4 v8, v12, v16
+; CHECK-NEXT:    sf.vqmaccu.4x8x4 v8, v12, v14
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv32i8(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 32 x i8> %2,
+    <vscale x 16 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 8 x i32> %a
@@ -121,38 +121,36 @@ entry:
 declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv64i8(
   <vscale x 16 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 64 x i8>,
+  <vscale x 32 x i8>,
   iXLen, iXLen);
 
-define <vscale x 16 x i32> @intrinsic_vqmaccu_4x8x4_tu_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
+define <vscale x 16 x i32> @intrinsic_vqmaccu_4x8x4_tu_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_tu_i32m8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vl8r.v v24, (a0)
-; CHECK-NEXT:    vsetvli zero, a1, e8, m1, tu, ma
-; CHECK-NEXT:    sf.vqmaccu.4x8x4 v8, v16, v24
+; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
+; CHECK-NEXT:    sf.vqmaccu.4x8x4 v8, v16, v20
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv64i8(
     <vscale x 16 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 64 x i8> %2,
+    <vscale x 32 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 16 x i32> %a
 }
 
-define <vscale x 16 x i32> @intrinsic_vqmaccu_4x8x4_ta_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
+define <vscale x 16 x i32> @intrinsic_vqmaccu_4x8x4_ta_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_ta_i32m8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vl8r.v v24, (a0)
-; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
-; CHECK-NEXT:    sf.vqmaccu.4x8x4 v8, v16, v24
+; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-NEXT:    sf.vqmaccu.4x8x4 v8, v16, v20
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv64i8(
     <vscale x 16 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 64 x i8> %2,
+    <vscale x 32 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 16 x i32> %a
diff --git a/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccus_4x8x4.ll b/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccus_4x8x4.ll
index d9b62d8a5769..caa1b226bd39 100644
--- a/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccus_4x8x4.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccus_4x8x4.ll
@@ -7,10 +7,10 @@
 declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv8i8(
   <vscale x 2 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
   iXLen, iXLen);
 
-define <vscale x 2 x i32> @intrinsic_vqmaccus_4x8x4_tu_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vqmaccus_4x8x4_tu_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_tu_i32m1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
@@ -20,13 +20,13 @@ entry:
   %a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv8i8(
     <vscale x 2 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 8 x i8> %2,
+    <vscale x 4 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 2 x i32> %a
 }
 
-define <vscale x 2 x i32> @intrinsic_vqmaccus_4x8x4_ta_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vqmaccus_4x8x4_ta_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_ta_i32m1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
@@ -36,7 +36,7 @@ entry:
   %a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv8i8(
     <vscale x 2 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 8 x i8> %2,
+    <vscale x 4 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 2 x i32> %a
@@ -45,36 +45,36 @@ entry:
 declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv16i8(
   <vscale x 4 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
   iXLen, iXLen);
 
-define <vscale x 4 x i32> @intrinsic_vqmaccus_4x8x4_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
+define <vscale x 4 x i32> @intrinsic_vqmaccus_4x8x4_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_tu_i32m2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
-; CHECK-NEXT:    sf.vqmaccus.4x8x4 v8, v10, v12
+; CHECK-NEXT:    sf.vqmaccus.4x8x4 v8, v10, v11
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv16i8(
     <vscale x 4 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 16 x i8> %2,
+    <vscale x 8 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 4 x i32> %a
 }
 
-define <vscale x 4 x i32> @intrinsic_vqmaccus_4x8x4_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
+define <vscale x 4 x i32> @intrinsic_vqmaccus_4x8x4_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_ta_i32m2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT:    sf.vqmaccus.4x8x4 v8, v10, v12
+; CHECK-NEXT:    sf.vqmaccus.4x8x4 v8, v10, v11
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv16i8(
     <vscale x 4 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 16 x i8> %2,
+    <vscale x 8 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 4 x i32> %a
@@ -83,36 +83,36 @@ entry:
 declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv32i8(
   <vscale x 8 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 32 x i8>,
+  <vscale x 16 x i8>,
   iXLen, iXLen);
 
-define <vscale x 8 x i32> @intrinsic_vqmaccus_4x8x4_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
+define <vscale x 8 x i32> @intrinsic_vqmaccus_4x8x4_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_tu_i32m4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
-; CHECK-NEXT:    sf.vqmaccus.4x8x4 v8, v12, v16
+; CHECK-NEXT:    sf.vqmaccus.4x8x4 v8, v12, v14
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv32i8(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 32 x i8> %2,
+    <vscale x 16 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 8 x i32> %a
 }
 
-define <vscale x 8 x i32> @intrinsic_vqmaccus_4x8x4_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
+define <vscale x 8 x i32> @intrinsic_vqmaccus_4x8x4_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_ta_i32m4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT:    sf.vqmaccus.4x8x4 v8, v12, v16
+; CHECK-NEXT:    sf.vqmaccus.4x8x4 v8, v12, v14
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv32i8(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 32 x i8> %2,
+    <vscale x 16 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 8 x i32> %a
@@ -121,38 +121,36 @@ entry:
 declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8(
   <vscale x 16 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 64 x i8>,
+  <vscale x 32 x i8>,
   iXLen, iXLen);
 
-define <vscale x 16 x i32> @intrinsic_vqmaccus_4x8x4_tu_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
+define <vscale x 16 x i32> @intrinsic_vqmaccus_4x8x4_tu_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_tu_i32m8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vl8r.v v24, (a0)
-; CHECK-NEXT:    vsetvli zero, a1, e8, m1, tu, ma
-; CHECK-NEXT:    sf.vqmaccus.4x8x4 v8, v16, v24
+; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
+; CHECK-NEXT:    sf.vqmaccus.4x8x4 v8, v16, v20
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8(
     <vscale x 16 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 64 x i8> %2,
+    <vscale x 32 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 16 x i32> %a
 }
 
-define <vscale x 16 x i32> @intrinsic_vqmaccus_4x8x4_ta_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
+define <vscale x 16 x i32> @intrinsic_vqmaccus_4x8x4_ta_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_ta_i32m8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vl8r.v v24, (a0)
-; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
-; CHECK-NEXT:    sf.vqmaccus.4x8x4 v8, v16, v24
+; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-NEXT:    sf.vqmaccus.4x8x4 v8, v16, v20
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8(
     <vscale x 16 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 64 x i8> %2,
+    <vscale x 32 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 16 x i32> %a
-- 
GitLab


From 41a38288388a91d259fd9b1068c85ff9a19eafa5 Mon Sep 17 00:00:00 2001
From: Nilanjana Basu <n_basu@apple.com>
Date: Mon, 11 Dec 2023 21:39:25 -0800
Subject: [PATCH 223/349] [LV] Added pre-commit tests for changing loop
 interleaving count computation (#74689)

Added more pre-commit tests for evaluating changes to loop interleaving count computation in (https://github.com/llvm/llvm-project/pull/73766). The new set of tests address the change in IC computation to minimize the remainder TC of the vectorized loop while maximizing the IC when the
remainder TC is the same.
---
 .../LoopVectorize/AArch64/interleave_count.ll | 107 -------
 .../interleave_count_for_estimated_tc.ll      | 282 +++++++++++++++++
 .../AArch64/interleave_count_for_known_tc.ll  | 294 ++++++++++++++++++
 3 files changed, 576 insertions(+), 107 deletions(-)
 delete mode 100644 llvm/test/Transforms/LoopVectorize/AArch64/interleave_count.ll
 create mode 100644 llvm/test/Transforms/LoopVectorize/AArch64/interleave_count_for_estimated_tc.ll
 create mode 100644 llvm/test/Transforms/LoopVectorize/AArch64/interleave_count_for_known_tc.ll

diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/interleave_count.ll b/llvm/test/Transforms/LoopVectorize/AArch64/interleave_count.ll
deleted file mode 100644
index 061cdb564367..000000000000
--- a/llvm/test/Transforms/LoopVectorize/AArch64/interleave_count.ll
+++ /dev/null
@@ -1,107 +0,0 @@
-; RUN: opt < %s -tiny-trip-count-interleave-threshold=32 -p loop-vectorize -S -pass-remarks=loop-vectorize -disable-output 2>&1 | FileCheck %s
-; TODO: remove -tiny-trip-count-interleave-threshold once the interleave threshold is removed
-
-target triple = "aarch64-linux-gnu"
-
-%pair = type { i8, i8 }
-
-; For this loop with known TC of 32, when the auto-vectorizer chooses VF 16, it should choose
-; IC 2 since there is no remainder loop run needed when the vector loop runs.
-; CHECK: remark: <unknown>:0:0: vectorized loop (vectorization width: 16, interleaved count: 2)
-define void @loop_with_tc_32(ptr noalias %p, ptr noalias %q) {
-entry:
-  br label %for.body
-
-for.body:
-  %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ]
-  %tmp0 = getelementptr %pair, ptr %p, i64 %i, i32 0
-  %tmp1 = load i8, ptr %tmp0, align 1
-  %tmp2 = getelementptr %pair, ptr %p, i64 %i, i32 1
-  %tmp3 = load i8, ptr %tmp2, align 1
-  %add = add i8 %tmp1, %tmp3
-  %qi = getelementptr i8, ptr %q, i64 %i
-  store i8 %add, ptr %qi, align 1
-  %i.next = add nuw nsw i64 %i, 1
-  %cond = icmp eq i64 %i.next, 32
-  br i1 %cond, label %for.end, label %for.body
-
-for.end:
-  ret void
-}
-
-; TODO: For this loop with known TC of 33, when the auto-vectorizer chooses VF 16, it should choose
-; IC 1 since there may be a remainder loop that needs to run after the vector loop.
-; CHECK: remark: <unknown>:0:0: vectorized loop (vectorization width: 16, interleaved count: 2)
-define void @loop_with_tc_33(ptr noalias %p, ptr noalias %q) {
-entry:
-  br label %for.body
-
-for.body:
-  %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ]
-  %tmp0 = getelementptr %pair, ptr %p, i64 %i, i32 0
-  %tmp1 = load i8, ptr %tmp0, align 1
-  %tmp2 = getelementptr %pair, ptr %p, i64 %i, i32 1
-  %tmp3 = load i8, ptr %tmp2, align 1
-  %add = add i8 %tmp1, %tmp3
-  %qi = getelementptr i8, ptr %q, i64 %i
-  store i8 %add, ptr %qi, align 1
-  %i.next = add nuw nsw i64 %i, 1
-  %cond = icmp eq i64 %i.next, 33
-  br i1 %cond, label %for.end, label %for.body
-
-for.end:
-  ret void
-}
-
-; For a loop with unknown trip count but a profile showing an approx TC estimate of 32, when the
-; auto-vectorizer chooses VF 16, it should choose IC 2 since chances are high that the remainder loop
-; won't need to run
-; CHECK: remark: <unknown>:0:0: vectorized loop (vectorization width: 16, interleaved count: 2)
-define void @loop_with_profile_tc_32(ptr noalias %p, ptr noalias %q, i64 %n) {
-entry:
-  br label %for.body
-
-for.body:
-  %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ]
-  %tmp0 = getelementptr %pair, ptr %p, i64 %i, i32 0
-  %tmp1 = load i8, ptr %tmp0, align 1
-  %tmp2 = getelementptr %pair, ptr %p, i64 %i, i32 1
-  %tmp3 = load i8, ptr %tmp2, align 1
-  %add = add i8 %tmp1, %tmp3
-  %qi = getelementptr i8, ptr %q, i64 %i
-  store i8 %add, ptr %qi, align 1
-  %i.next = add nuw nsw i64 %i, 1
-  %cond = icmp eq i64 %i.next, %n
-  br i1 %cond, label %for.end, label %for.body, !prof !0
-
-for.end:
-  ret void
-}
-
-; TODO: For a loop with unknown trip count but a profile showing an approx TC estimate of 33, 
-; when the auto-vectorizer chooses VF 16, it should choose IC 1 since chances are high that the 
-; remainder loop will need to run
-; CHECK: remark: <unknown>:0:0: vectorized loop (vectorization width: 16, interleaved count: 2)
-define void @loop_with_profile_tc_33(ptr noalias %p, ptr noalias %q, i64 %n) {
-entry:
-  br label %for.body
-
-for.body:
-  %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ]
-  %tmp0 = getelementptr %pair, ptr %p, i64 %i, i32 0
-  %tmp1 = load i8, ptr %tmp0, align 1
-  %tmp2 = getelementptr %pair, ptr %p, i64 %i, i32 1
-  %tmp3 = load i8, ptr %tmp2, align 1
-  %add = add i8 %tmp1, %tmp3
-  %qi = getelementptr i8, ptr %q, i64 %i
-  store i8 %add, ptr %qi, align 1
-  %i.next = add nuw nsw i64 %i, 1
-  %cond = icmp eq i64 %i.next, %n
-  br i1 %cond, label %for.end, label %for.body, !prof !1
-
-for.end:
-  ret void
-}
-
-!0 = !{!"branch_weights", i32 1, i32 31}
-!1 = !{!"branch_weights", i32 1, i32 32}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/interleave_count_for_estimated_tc.ll b/llvm/test/Transforms/LoopVectorize/AArch64/interleave_count_for_estimated_tc.ll
new file mode 100644
index 000000000000..6d49d7159998
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/interleave_count_for_estimated_tc.ll
@@ -0,0 +1,282 @@
+; RUN: opt < %s -tiny-trip-count-interleave-threshold=16 -force-target-max-vector-interleave=8 -p loop-vectorize -S -pass-remarks=loop-vectorize -disable-output 2>&1 | FileCheck %s
+; TODO: remove -tiny-trip-count-interleave-threshold once the interleave threshold is removed
+
+target triple = "aarch64-linux-gnu"
+
+%pair = type { i8, i8 }
+
+; TODO: For a loop with a profile-guided estimated TC of 32, when the auto-vectorizer chooses VF 16, 
+; it should conservatively choose IC 1 so that the vector loop runs twice at least
+; CHECK: remark: <unknown>:0:0: vectorized loop (vectorization width: 16, interleaved count: 2)
+define void @loop_with_profile_tc_32(ptr noalias %p, ptr noalias %q, i64 %n) {
+entry:
+  br label %for.body
+
+for.body:
+  %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ]
+  %tmp0 = getelementptr %pair, ptr %p, i64 %i, i32 0
+  %tmp1 = load i8, ptr %tmp0, align 1
+  %tmp2 = getelementptr %pair, ptr %p, i64 %i, i32 1
+  %tmp3 = load i8, ptr %tmp2, align 1
+  %add = add i8 %tmp1, %tmp3
+  %qi = getelementptr i8, ptr %q, i64 %i
+  store i8 %add, ptr %qi, align 1
+  %i.next = add nuw nsw i64 %i, 1
+  %cond = icmp eq i64 %i.next, %n
+  br i1 %cond, label %for.end, label %for.body, !prof !0
+
+for.end:
+  ret void
+}
+
+; TODO: For a loop with a profile-guided estimated TC of 33, when the auto-vectorizer chooses VF 16, 
+; it should conservatively choose IC 1 so that the vector loop runs twice at least
+; CHECK: remark: <unknown>:0:0: vectorized loop (vectorization width: 16, interleaved count: 2)
+define void @loop_with_profile_tc_33(ptr noalias %p, ptr noalias %q, i64 %n) {
+entry:
+  br label %for.body
+
+for.body:
+  %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ]
+  %tmp0 = getelementptr %pair, ptr %p, i64 %i, i32 0
+  %tmp1 = load i8, ptr %tmp0, align 1
+  %tmp2 = getelementptr %pair, ptr %p, i64 %i, i32 1
+  %tmp3 = load i8, ptr %tmp2, align 1
+  %add = add i8 %tmp1, %tmp3
+  %qi = getelementptr i8, ptr %q, i64 %i
+  store i8 %add, ptr %qi, align 1
+  %i.next = add nuw nsw i64 %i, 1
+  %cond = icmp eq i64 %i.next, %n
+  br i1 %cond, label %for.end, label %for.body, !prof !1
+
+for.end:
+  ret void
+}
+
+; TODO: For a loop with a profile-guided estimated TC of 48, when the auto-vectorizer chooses VF 16, 
+; it should conservatively choose IC 1 so that the vector loop runs twice at least
+; CHECK: remark: <unknown>:0:0: vectorized loop (vectorization width: 16, interleaved count: 3)
+define void @loop_with_profile_tc_48(ptr noalias %p, ptr noalias %q, i64 %n) {
+entry:
+  br label %for.body
+
+for.body:
+  %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ]
+  %tmp0 = getelementptr %pair, ptr %p, i64 %i, i32 0
+  %tmp1 = load i8, ptr %tmp0, align 1
+  %tmp2 = getelementptr %pair, ptr %p, i64 %i, i32 1
+  %tmp3 = load i8, ptr %tmp2, align 1
+  %add = add i8 %tmp1, %tmp3
+  %qi = getelementptr i8, ptr %q, i64 %i
+  store i8 %add, ptr %qi, align 1
+  %i.next = add nuw nsw i64 %i, 1
+  %cond = icmp eq i64 %i.next, %n
+  br i1 %cond, label %for.end, label %for.body, !prof !2
+
+for.end:
+  ret void
+}
+
+; TODO: For a loop with a profile-guided estimated TC of 63, when the auto-vectorizer chooses VF 16, 
+; it should conservatively choose IC 1 so that the vector loop runs twice at least
+; CHECK: remark: <unknown>:0:0: vectorized loop (vectorization width: 16, interleaved count: 3)
+define void @loop_with_profile_tc_63(ptr noalias %p, ptr noalias %q, i64 %n) {
+entry:
+  br label %for.body
+
+for.body:
+  %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ]
+  %tmp0 = getelementptr %pair, ptr %p, i64 %i, i32 0
+  %tmp1 = load i8, ptr %tmp0, align 1
+  %tmp2 = getelementptr %pair, ptr %p, i64 %i, i32 1
+  %tmp3 = load i8, ptr %tmp2, align 1
+  %add = add i8 %tmp1, %tmp3
+  %qi = getelementptr i8, ptr %q, i64 %i
+  store i8 %add, ptr %qi, align 1
+  %i.next = add nuw nsw i64 %i, 1
+  %cond = icmp eq i64 %i.next, %n
+  br i1 %cond, label %for.end, label %for.body, !prof !3
+
+for.end:
+  ret void
+}
+
+; TODO: For a loop with a profile-guided estimated TC of 64, when the auto-vectorizer chooses VF 16, 
+; it should choose conservatively IC 2 so that the vector loop runs twice at least
+; CHECK: remark: <unknown>:0:0: vectorized loop (vectorization width: 16, interleaved count: 4)
+define void @loop_with_profile_tc_64(ptr noalias %p, ptr noalias %q, i64 %n) {
+entry:
+  br label %for.body
+
+for.body:
+  %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ]
+  %tmp0 = getelementptr %pair, ptr %p, i64 %i, i32 0
+  %tmp1 = load i8, ptr %tmp0, align 1
+  %tmp2 = getelementptr %pair, ptr %p, i64 %i, i32 1
+  %tmp3 = load i8, ptr %tmp2, align 1
+  %add = add i8 %tmp1, %tmp3
+  %qi = getelementptr i8, ptr %q, i64 %i
+  store i8 %add, ptr %qi, align 1
+  %i.next = add nuw nsw i64 %i, 1
+  %cond = icmp eq i64 %i.next, %n
+  br i1 %cond, label %for.end, label %for.body, !prof !4
+
+for.end:
+  ret void
+}
+
+; TODO: For a loop with a profile-guided estimated TC of 100, when the auto-vectorizer chooses VF 16, 
+; it should choose conservatively IC 2 so that the vector loop runs twice at least
+; CHECK: remark: <unknown>:0:0: vectorized loop (vectorization width: 16, interleaved count: 6)
+define void @loop_with_profile_tc_100(ptr noalias %p, ptr noalias %q, i64 %n) {
+entry:
+  br label %for.body
+
+for.body:
+  %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ]
+  %tmp0 = getelementptr %pair, ptr %p, i64 %i, i32 0
+  %tmp1 = load i8, ptr %tmp0, align 1
+  %tmp2 = getelementptr %pair, ptr %p, i64 %i, i32 1
+  %tmp3 = load i8, ptr %tmp2, align 1
+  %add = add i8 %tmp1, %tmp3
+  %qi = getelementptr i8, ptr %q, i64 %i
+  store i8 %add, ptr %qi, align 1
+  %i.next = add nuw nsw i64 %i, 1
+  %cond = icmp eq i64 %i.next, %n
+  br i1 %cond, label %for.end, label %for.body, !prof !5
+
+for.end:
+  ret void
+}
+
+; TODO: For a loop with a profile-guided estimated TC of 128, when the auto-vectorizer chooses VF 16, 
+; it should choose conservatively IC 4 so that the vector loop runs twice at least
+; CHECK: remark: <unknown>:0:0: vectorized loop (vectorization width: 16, interleaved count: 8)
+define void @loop_with_profile_tc_128(ptr noalias %p, ptr noalias %q, i64 %n) {
+entry:
+  br label %for.body
+
+for.body:
+  %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ]
+  %tmp0 = getelementptr %pair, ptr %p, i64 %i, i32 0
+  %tmp1 = load i8, ptr %tmp0, align 1
+  %tmp2 = getelementptr %pair, ptr %p, i64 %i, i32 1
+  %tmp3 = load i8, ptr %tmp2, align 1
+  %add = add i8 %tmp1, %tmp3
+  %qi = getelementptr i8, ptr %q, i64 %i
+  store i8 %add, ptr %qi, align 1
+  %i.next = add nuw nsw i64 %i, 1
+  %cond = icmp eq i64 %i.next, %n
+  br i1 %cond, label %for.end, label %for.body, !prof !6
+
+for.end:
+  ret void
+}
+
+; TODO: For a loop with a profile-guided estimated TC of 129, when the auto-vectorizer chooses VF 16, 
+; it should choose conservatively IC 4 so that the vector loop runs twice at least
+; CHECK: remark: <unknown>:0:0: vectorized loop (vectorization width: 16, interleaved count: 8)
+define void @loop_with_profile_tc_129(ptr noalias %p, ptr noalias %q, i64 %n) {
+entry:
+  br label %for.body
+
+for.body:
+  %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ]
+  %tmp0 = getelementptr %pair, ptr %p, i64 %i, i32 0
+  %tmp1 = load i8, ptr %tmp0, align 1
+  %tmp2 = getelementptr %pair, ptr %p, i64 %i, i32 1
+  %tmp3 = load i8, ptr %tmp2, align 1
+  %add = add i8 %tmp1, %tmp3
+  %qi = getelementptr i8, ptr %q, i64 %i
+  store i8 %add, ptr %qi, align 1
+  %i.next = add nuw nsw i64 %i, 1
+  %cond = icmp eq i64 %i.next, %n
+  br i1 %cond, label %for.end, label %for.body, !prof !7
+
+for.end:
+  ret void
+}
+
+; TODO: For a loop with a profile-guided estimated TC of 180, when the auto-vectorizer chooses VF 16, 
+; it should choose conservatively IC 4 so that the vector loop runs twice at least
+; CHECK: remark: <unknown>:0:0: vectorized loop (vectorization width: 16, interleaved count: 8)
+define void @loop_with_profile_tc_180(ptr noalias %p, ptr noalias %q, i64 %n) {
+entry:
+  br label %for.body
+
+for.body:
+  %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ]
+  %tmp0 = getelementptr %pair, ptr %p, i64 %i, i32 0
+  %tmp1 = load i8, ptr %tmp0, align 1
+  %tmp2 = getelementptr %pair, ptr %p, i64 %i, i32 1
+  %tmp3 = load i8, ptr %tmp2, align 1
+  %add = add i8 %tmp1, %tmp3
+  %qi = getelementptr i8, ptr %q, i64 %i
+  store i8 %add, ptr %qi, align 1
+  %i.next = add nuw nsw i64 %i, 1
+  %cond = icmp eq i64 %i.next, %n
+  br i1 %cond, label %for.end, label %for.body, !prof !8
+
+for.end:
+  ret void
+}
+
+; TODO: For a loop with a profile-guided estimated TC of 193, when the auto-vectorizer chooses VF 16, 
+; it should choose conservatively IC 4 so that the vector loop runs twice at least
+; CHECK: remark: <unknown>:0:0: vectorized loop (vectorization width: 16, interleaved count: 8)
+define void @loop_with_profile_tc_193(ptr noalias %p, ptr noalias %q, i64 %n) {
+entry:
+  br label %for.body
+
+for.body:
+  %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ]
+  %tmp0 = getelementptr %pair, ptr %p, i64 %i, i32 0
+  %tmp1 = load i8, ptr %tmp0, align 1
+  %tmp2 = getelementptr %pair, ptr %p, i64 %i, i32 1
+  %tmp3 = load i8, ptr %tmp2, align 1
+  %add = add i8 %tmp1, %tmp3
+  %qi = getelementptr i8, ptr %q, i64 %i
+  store i8 %add, ptr %qi, align 1
+  %i.next = add nuw nsw i64 %i, 1
+  %cond = icmp eq i64 %i.next, %n
+  br i1 %cond, label %for.end, label %for.body, !prof !9
+
+for.end:
+  ret void
+}
+
+; TODO: For a loop with a profile-guided estimated TC of 1000, when the auto-vectorizer chooses VF 16, 
+; the IC will be capped by the target-specific maximum interleave count
+; CHECK: remark: <unknown>:0:0: vectorized loop (vectorization width: 16, interleaved count: 8)
+define void @loop_with_profile_tc_1000(ptr noalias %p, ptr noalias %q, i64 %n) {
+entry:
+  br label %for.body
+
+for.body:
+  %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ]
+  %tmp0 = getelementptr %pair, ptr %p, i64 %i, i32 0
+  %tmp1 = load i8, ptr %tmp0, align 1
+  %tmp2 = getelementptr %pair, ptr %p, i64 %i, i32 1
+  %tmp3 = load i8, ptr %tmp2, align 1
+  %add = add i8 %tmp1, %tmp3
+  %qi = getelementptr i8, ptr %q, i64 %i
+  store i8 %add, ptr %qi, align 1
+  %i.next = add nuw nsw i64 %i, 1
+  %cond = icmp eq i64 %i.next, %n
+  br i1 %cond, label %for.end, label %for.body, !prof !10
+
+for.end:
+  ret void
+}
+
+!0 = !{!"branch_weights", i32 1, i32 31}
+!1 = !{!"branch_weights", i32 1, i32 32}
+!2 = !{!"branch_weights", i32 1, i32 47}
+!3 = !{!"branch_weights", i32 1, i32 62}
+!4 = !{!"branch_weights", i32 1, i32 63}
+!5 = !{!"branch_weights", i32 1, i32 99}
+!6 = !{!"branch_weights", i32 1, i32 127}
+!7 = !{!"branch_weights", i32 1, i32 128}
+!8 = !{!"branch_weights", i32 1, i32 179}
+!9 = !{!"branch_weights", i32 1, i32 192}
+!10 = !{!"branch_weights", i32 1, i32 999}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/interleave_count_for_known_tc.ll b/llvm/test/Transforms/LoopVectorize/AArch64/interleave_count_for_known_tc.ll
new file mode 100644
index 000000000000..828cbe76489a
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/interleave_count_for_known_tc.ll
@@ -0,0 +1,294 @@
+; RUN: opt < %s -tiny-trip-count-interleave-threshold=16 -force-target-max-vector-interleave=8 -p loop-vectorize -S -pass-remarks=loop-vectorize -disable-output 2>&1 | FileCheck %s
+; TODO: remove -tiny-trip-count-interleave-threshold once the interleave threshold is removed
+
+target triple = "aarch64-linux-gnu"
+
+%pair = type { i8, i8 }
+
+; For this loop with known TC of 32, when the auto-vectorizer chooses VF 16, it should choose
+; IC 2 since there is no remainder loop run needed after the vector loop runs.
+; CHECK: remark: <unknown>:0:0: vectorized loop (vectorization width: 16, interleaved count: 2)
+define void @loop_with_tc_32(ptr noalias %p, ptr noalias %q) {
+entry:
+  br label %for.body
+
+for.body:
+  %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ]
+  %tmp0 = getelementptr %pair, ptr %p, i64 %i, i32 0
+  %tmp1 = load i8, ptr %tmp0, align 1
+  %tmp2 = getelementptr %pair, ptr %p, i64 %i, i32 1
+  %tmp3 = load i8, ptr %tmp2, align 1
+  %add = add i8 %tmp1, %tmp3
+  %qi = getelementptr i8, ptr %q, i64 %i
+  store i8 %add, ptr %qi, align 1
+  %i.next = add nuw nsw i64 %i, 1
+  %cond = icmp eq i64 %i.next, 32
+  br i1 %cond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
+; For this loop with known TC of 33, when the auto-vectorizer chooses VF 16, it should choose
+; IC 2 since there is a small remainder loop TC that needs to run after the vector loop.
+; CHECK: remark: <unknown>:0:0: vectorized loop (vectorization width: 16, interleaved count: 2)
+define void @loop_with_tc_33(ptr noalias %p, ptr noalias %q) {
+entry:
+  br label %for.body
+
+for.body:
+  %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ]
+  %tmp0 = getelementptr %pair, ptr %p, i64 %i, i32 0
+  %tmp1 = load i8, ptr %tmp0, align 1
+  %tmp2 = getelementptr %pair, ptr %p, i64 %i, i32 1
+  %tmp3 = load i8, ptr %tmp2, align 1
+  %add = add i8 %tmp1, %tmp3
+  %qi = getelementptr i8, ptr %q, i64 %i
+  store i8 %add, ptr %qi, align 1
+  %i.next = add nuw nsw i64 %i, 1
+  %cond = icmp eq i64 %i.next, 33
+  br i1 %cond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
+; For this loop with known TC of 39, when the auto-vectorizer chooses VF 16, it should choose
+; IC 2 since there is a small remainder loop that needs to run after the vector loop.
+; CHECK: remark: <unknown>:0:0: vectorized loop (vectorization width: 16, interleaved count: 2)
+define void @loop_with_tc_39(ptr noalias %p, ptr noalias %q) {
+entry:
+  br label %for.body
+
+for.body:
+  %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ]
+  %tmp0 = getelementptr %pair, ptr %p, i64 %i, i32 0
+  %tmp1 = load i8, ptr %tmp0, align 1
+  %tmp2 = getelementptr %pair, ptr %p, i64 %i, i32 1
+  %tmp3 = load i8, ptr %tmp2, align 1
+  %add = add i8 %tmp1, %tmp3
+  %qi = getelementptr i8, ptr %q, i64 %i
+  store i8 %add, ptr %qi, align 1
+  %i.next = add nuw nsw i64 %i, 1
+  %cond = icmp eq i64 %i.next, 39
+  br i1 %cond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
+; TODO: For this loop with known TC of 48, when the auto-vectorizer chooses VF 16, it should choose
+; IC 1 since there will be no remainder loop that needs to run after the vector loop.
+; CHECK: remark: <unknown>:0:0: vectorized loop (vectorization width: 16, interleaved count: 3)
+define void @loop_with_tc_48(ptr noalias %p, ptr noalias %q) {
+entry:
+  br label %for.body
+
+for.body:
+  %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ]
+  %tmp0 = getelementptr %pair, ptr %p, i64 %i, i32 0
+  %tmp1 = load i8, ptr %tmp0, align 1
+  %tmp2 = getelementptr %pair, ptr %p, i64 %i, i32 1
+  %tmp3 = load i8, ptr %tmp2, align 1
+  %add = add i8 %tmp1, %tmp3
+  %qi = getelementptr i8, ptr %q, i64 %i
+  store i8 %add, ptr %qi, align 1
+  %i.next = add nuw nsw i64 %i, 1
+  %cond = icmp eq i64 %i.next, 48
+  br i1 %cond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
+; TODO: For this loop with known TC of 49, when the auto-vectorizer chooses VF 16, it should choose
+; IC 1 since a remainder loop TC of 1 is more efficient than remainder loop TC of 17 with IC 2
+; CHECK: remark: <unknown>:0:0: vectorized loop (vectorization width: 16, interleaved count: 3)
+define void @loop_with_tc_49(ptr noalias %p, ptr noalias %q) {
+entry:
+  br label %for.body
+
+for.body:
+  %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ]
+  %tmp0 = getelementptr %pair, ptr %p, i64 %i, i32 0
+  %tmp1 = load i8, ptr %tmp0, align 1
+  %tmp2 = getelementptr %pair, ptr %p, i64 %i, i32 1
+  %tmp3 = load i8, ptr %tmp2, align 1
+  %add = add i8 %tmp1, %tmp3
+  %qi = getelementptr i8, ptr %q, i64 %i
+  store i8 %add, ptr %qi, align 1
+  %i.next = add nuw nsw i64 %i, 1
+  %cond = icmp eq i64 %i.next, 49
+  br i1 %cond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
+; TODO: For this loop with known TC of 55, when the auto-vectorizer chooses VF 16, it should choose
+; IC 1 since a remainder loop TC of 7 is more efficient than remainder loop TC of 23 with IC 2
+; CHECK: remark: <unknown>:0:0: vectorized loop (vectorization width: 16, interleaved count: 3)
+define void @loop_with_tc_55(ptr noalias %p, ptr noalias %q) {
+entry:
+  br label %for.body
+
+for.body:
+  %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ]
+  %tmp0 = getelementptr %pair, ptr %p, i64 %i, i32 0
+  %tmp1 = load i8, ptr %tmp0, align 1
+  %tmp2 = getelementptr %pair, ptr %p, i64 %i, i32 1
+  %tmp3 = load i8, ptr %tmp2, align 1
+  %add = add i8 %tmp1, %tmp3
+  %qi = getelementptr i8, ptr %q, i64 %i
+  store i8 %add, ptr %qi, align 1
+  %i.next = add nuw nsw i64 %i, 1
+  %cond = icmp eq i64 %i.next, 55
+  br i1 %cond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
+; TODO: For this loop with known TC of 100, when the auto-vectorizer chooses VF 16, it should choose
+; IC 2 since a remainder loop TC of 4 is more efficient than remainder loop TC of 36 with IC 4
+; CHECK: remark: <unknown>:0:0: vectorized loop (vectorization width: 16, interleaved count: 6)
+define void @loop_with_tc_100(ptr noalias %p, ptr noalias %q) {
+entry:
+  br label %for.body
+
+for.body:
+  %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ]
+  %tmp0 = getelementptr %pair, ptr %p, i64 %i, i32 0
+  %tmp1 = load i8, ptr %tmp0, align 1
+  %tmp2 = getelementptr %pair, ptr %p, i64 %i, i32 1
+  %tmp3 = load i8, ptr %tmp2, align 1
+  %add = add i8 %tmp1, %tmp3
+  %qi = getelementptr i8, ptr %q, i64 %i
+  store i8 %add, ptr %qi, align 1
+  %i.next = add nuw nsw i64 %i, 1
+  %cond = icmp eq i64 %i.next, 100
+  br i1 %cond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
+; For this loop with known TC of 128, when the auto-vectorizer chooses VF 16, it should choose
+; IC 8 since there is no remainder loop run needed after the vector loop runs
+; CHECK: remark: <unknown>:0:0: vectorized loop (vectorization width: 16, interleaved count: 8)
+define void @loop_with_tc_128(ptr noalias %p, ptr noalias %q) {
+entry:
+  br label %for.body
+
+for.body:
+  %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ]
+  %tmp0 = getelementptr %pair, ptr %p, i64 %i, i32 0
+  %tmp1 = load i8, ptr %tmp0, align 1
+  %tmp2 = getelementptr %pair, ptr %p, i64 %i, i32 1
+  %tmp3 = load i8, ptr %tmp2, align 1
+  %add = add i8 %tmp1, %tmp3
+  %qi = getelementptr i8, ptr %q, i64 %i
+  store i8 %add, ptr %qi, align 1
+  %i.next = add nuw nsw i64 %i, 1
+  %cond = icmp eq i64 %i.next, 128
+  br i1 %cond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
+; For this loop with known TC of 129, when the auto-vectorizer chooses VF 16, it should choose
+; IC 8 since there is a small remainder loop that needs to run after the vector loop
+; CHECK: remark: <unknown>:0:0: vectorized loop (vectorization width: 16, interleaved count: 8)
+define void @loop_with_tc_129(ptr noalias %p, ptr noalias %q) {
+entry:
+  br label %for.body
+
+for.body:
+  %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ]
+  %tmp0 = getelementptr %pair, ptr %p, i64 %i, i32 0
+  %tmp1 = load i8, ptr %tmp0, align 1
+  %tmp2 = getelementptr %pair, ptr %p, i64 %i, i32 1
+  %tmp3 = load i8, ptr %tmp2, align 1
+  %add = add i8 %tmp1, %tmp3
+  %qi = getelementptr i8, ptr %q, i64 %i
+  store i8 %add, ptr %qi, align 1
+  %i.next = add nuw nsw i64 %i, 1
+  %cond = icmp eq i64 %i.next, 129
+  br i1 %cond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
+; For this loop with known TC of 180, when the auto-vectorizer chooses VF 16, it should choose
+; IC 8 since the remainder loop of TC 52 cannot be reduced by choosing IC 4
+; CHECK: remark: <unknown>:0:0: vectorized loop (vectorization width: 16, interleaved count: 8)
+define void @loop_with_tc_180(ptr noalias %p, ptr noalias %q) {
+entry:
+  br label %for.body
+
+for.body:
+  %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ]
+  %tmp0 = getelementptr %pair, ptr %p, i64 %i, i32 0
+  %tmp1 = load i8, ptr %tmp0, align 1
+  %tmp2 = getelementptr %pair, ptr %p, i64 %i, i32 1
+  %tmp3 = load i8, ptr %tmp2, align 1
+  %add = add i8 %tmp1, %tmp3
+  %qi = getelementptr i8, ptr %q, i64 %i
+  store i8 %add, ptr %qi, align 1
+  %i.next = add nuw nsw i64 %i, 1
+  %cond = icmp eq i64 %i.next, 180
+  br i1 %cond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
+; TODO: For this loop with known TC of 193, when the auto-vectorizer chooses VF 16, it should choose
+; IC 4 since a remainder loop TC of 1 is more efficient than remainder loop TC of 65 with IC 8
+; CHECK: remark: <unknown>:0:0: vectorized loop (vectorization width: 16, interleaved count: 8)
+define void @loop_with_tc_193(ptr noalias %p, ptr noalias %q) {
+entry:
+  br label %for.body
+
+for.body:
+  %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ]
+  %tmp0 = getelementptr %pair, ptr %p, i64 %i, i32 0
+  %tmp1 = load i8, ptr %tmp0, align 1
+  %tmp2 = getelementptr %pair, ptr %p, i64 %i, i32 1
+  %tmp3 = load i8, ptr %tmp2, align 1
+  %add = add i8 %tmp1, %tmp3
+  %qi = getelementptr i8, ptr %q, i64 %i
+  store i8 %add, ptr %qi, align 1
+  %i.next = add nuw nsw i64 %i, 1
+  %cond = icmp eq i64 %i.next, 193
+  br i1 %cond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
+; For a loop with high known TC of 1000, when the auto-vectorizer chooses VF 16, the IC will
+; be capped by the target-specific maximum interleave count
+; CHECK: remark: <unknown>:0:0: vectorized loop (vectorization width: 16, interleaved count: 8)
+define void @loop_with_tc_1000(ptr noalias %p, ptr noalias %q) {
+entry:
+  br label %for.body
+
+for.body:
+  %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ]
+  %tmp0 = getelementptr %pair, ptr %p, i64 %i, i32 0
+  %tmp1 = load i8, ptr %tmp0, align 1
+  %tmp2 = getelementptr %pair, ptr %p, i64 %i, i32 1
+  %tmp3 = load i8, ptr %tmp2, align 1
+  %add = add i8 %tmp1, %tmp3
+  %qi = getelementptr i8, ptr %q, i64 %i
+  store i8 %add, ptr %qi, align 1
+  %i.next = add nuw nsw i64 %i, 1
+  %cond = icmp eq i64 %i.next, 1000
+  br i1 %cond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
-- 
GitLab


From b3af755254599f474601d0d7b7374dcc36af279a Mon Sep 17 00:00:00 2001
From: Aiden Grossman <agrossman154@yahoo.com>
Date: Mon, 11 Dec 2023 21:46:51 -0800
Subject: [PATCH 224/349] [Github] Set start rev to merge base in code format
 action (#75132)

This patch sets the start revision to the merge base so that the c++
formatting action won't produce any diffs related to changes in main but
not in the PR branch. This also leaves a TODO to migrate over to the
--diff_from_common_commit option in git-clang-format once LLVM v18 is
released.
---
 .github/workflows/pr-code-format.yml | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/.github/workflows/pr-code-format.yml b/.github/workflows/pr-code-format.yml
index c27c282eb2a1..5223089ee8a9 100644
--- a/.github/workflows/pr-code-format.yml
+++ b/.github/workflows/pr-code-format.yml
@@ -67,10 +67,14 @@ jobs:
           START_REV: ${{ github.event.pull_request.base.sha }}
           END_REV: ${{ github.event.pull_request.head.sha }}
           CHANGED_FILES: ${{ steps.changed-files.outputs.all_changed_files }}
+        # TODO(boomanaiden154): Once clang v18 is released, we should be able
+        # to take advantage of the new --diff_from_common_commit option
+        # explicitly in code-format-helper.py and not have to diff starting at
+        # the merge base.
         run: |
           python ./code-format-tools/llvm/utils/git/code-format-helper.py \
             --token ${{ secrets.GITHUB_TOKEN }} \
             --issue-number $GITHUB_PR_NUMBER \
-            --start-rev $START_REV \
+            --start-rev $(git merge-base $START_REV $END_REV) \
             --end-rev $END_REV \
             --changed-files "$CHANGED_FILES"
-- 
GitLab


From 5d12274646ee9bad8e9f59d7d2de44706aa58145 Mon Sep 17 00:00:00 2001
From: Shreyansh Chouhan <chouhan.shreyansh2702@gmail.com>
Date: Tue, 12 Dec 2023 11:18:45 +0530
Subject: [PATCH 225/349] [AArch64]: Added code for generating XAR instruction
 (#75085)

Fixes #61584
---
 .../Target/AArch64/AArch64ISelDAGToDAG.cpp    | 38 +++++++++++++++++++
 llvm/test/CodeGen/AArch64/xar.ll              | 22 +++++++++++
 2 files changed, 60 insertions(+)
 create mode 100644 llvm/test/CodeGen/AArch64/xar.ll

diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index d05d22a7164e..463ec41b94e9 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -435,6 +435,8 @@ public:
   bool trySelectCastFixedLengthToScalableVector(SDNode *N);
   bool trySelectCastScalableToFixedLengthVector(SDNode *N);
 
+  bool trySelectXAR(SDNode *N);
+
 // Include the pieces autogenerated from the target description.
 #include "AArch64GenDAGISel.inc"
 
@@ -4273,6 +4275,40 @@ bool AArch64DAGToDAGISel::trySelectCastScalableToFixedLengthVector(SDNode *N) {
   return true;
 }
 
+bool AArch64DAGToDAGISel::trySelectXAR(SDNode *N) {
+  assert(N->getOpcode() == ISD::OR && "Expected OR instruction");
+
+  SDValue N0 = N->getOperand(0);
+  SDValue N1 = N->getOperand(1);
+
+  if (N0->getOpcode() != AArch64ISD::VSHL ||
+      N1->getOpcode() != AArch64ISD::VLSHR)
+    return false;
+
+  if (N0->getOperand(0) != N1->getOperand(0) ||
+      N1->getOperand(0)->getOpcode() != ISD::XOR)
+    return false;
+
+  SDValue XOR = N0.getOperand(0);
+  SDValue R1 = XOR.getOperand(0);
+  SDValue R2 = XOR.getOperand(1);
+
+  unsigned HsAmt = N0.getConstantOperandVal(1);
+  unsigned ShAmt = N1.getConstantOperandVal(1);
+
+  SDLoc DL = SDLoc(N0.getOperand(1));
+  SDValue Imm = CurDAG->getTargetConstant(
+      ShAmt, DL, N0.getOperand(1).getValueType(), false);
+
+  if (ShAmt + HsAmt != 64)
+    return false;
+
+  SDValue Ops[] = {R1, R2, Imm};
+  CurDAG->SelectNodeTo(N, AArch64::XAR, N0.getValueType(), Ops);
+
+  return true;
+}
+
 void AArch64DAGToDAGISel::Select(SDNode *Node) {
   // If we have a custom node, we already have selected!
   if (Node->isMachineOpcode()) {
@@ -4336,6 +4372,8 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
   case ISD::OR:
     if (tryBitfieldInsertOp(Node))
       return;
+    if (Subtarget->hasSHA3() && trySelectXAR(Node))
+      return;
     break;
 
   case ISD::EXTRACT_SUBVECTOR: {
diff --git a/llvm/test/CodeGen/AArch64/xar.ll b/llvm/test/CodeGen/AArch64/xar.ll
new file mode 100644
index 000000000000..c602837a6e6c
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/xar.ll
@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -mtriple=aarch64-none-eabi -mattr=+sha3 < %s | FileCheck --check-prefix=SHA3 %s
+; RUN: llc -mtriple=aarch64-none-eabi -mattr=-sha3 < %s | FileCheck --check-prefix=NOSHA3 %s
+
+define <2 x i64> @xar(<2 x i64> %x, <2 x i64> %y) {
+; SHA3-LABEL: xar:
+; SHA3:       // %bb.0:
+; SHA3-NEXT:    xar v0.2d, v0.2d, v1.2d, #54
+; SHA3-NEXT:    ret
+;
+; NOSHA3-LABEL: xar:
+; NOSHA3:       // %bb.0:
+; NOSHA3-NEXT:    eor v1.16b, v0.16b, v1.16b
+; NOSHA3-NEXT:    shl v0.2d, v1.2d, #10
+; NOSHA3-NEXT:    usra v0.2d, v1.2d, #54
+; NOSHA3-NEXT:    ret
+    %a = xor <2 x i64> %x, %y
+    %b = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> <i64 10, i64 10>)
+    ret <2 x i64> %b
+}
+
+declare <2 x i64> @llvm.fshl.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
-- 
GitLab


From c88d73164a3960c5ef3ff578631f0e765b893809 Mon Sep 17 00:00:00 2001
From: Ben Jackson <puremourning@users.noreply.github.com>
Date: Tue, 12 Dec 2023 06:30:23 +0000
Subject: [PATCH 226/349] [clang] Crash when referencing capture in static
 lambda (#74661)

The constant evaluator could try to reference a lambda capture in a
static lambda call operator. Static lambdas can't have captures, so we
simply abort. Either the lambda needs to be made non-static, or the
capture (and reference to it) need to be removed.

Fixes: https://github.com/llvm/llvm-project/issues/74608
---
 clang/docs/ReleaseNotes.rst         |  4 ++++
 clang/lib/AST/ExprConstant.cpp      | 14 ++++++++++++--
 clang/test/Parser/cxx2b-lambdas.cpp | 12 ++++++++++++
 3 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index d6719680d2ac..b62293a33bb9 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -870,6 +870,10 @@ Miscellaneous Clang Crashes Fixed
   `Issue 41302 <https://github.com/llvm/llvm-project/issues/41302>`_
 - Fixed a crash when ``-ast-dump=json`` was used for code using class
   template deduction guides.
+- Fixed a crash when a lambda marked as ``static`` referenced a captured
+  variable in an expression.
+  `Issue 74608 <https://github.com/llvm/llvm-project/issues/74608>`_
+
 
 OpenACC Specific Changes
 ------------------------
diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp
index f035c1419f4c..f6aeee1a4e93 100644
--- a/clang/lib/AST/ExprConstant.cpp
+++ b/clang/lib/AST/ExprConstant.cpp
@@ -8514,14 +8514,24 @@ bool LValueExprEvaluator::VisitVarDecl(const Expr *E, const VarDecl *VD) {
       return false;
 
     if (auto *FD = Info.CurrentCall->LambdaCaptureFields.lookup(VD)) {
+      const auto *MD = cast<CXXMethodDecl>(Info.CurrentCall->Callee);
+
+      // Static lambda function call operators can't have captures. We already
+      // diagnosed this, so bail out here.
+      if (MD->isStatic()) {
+        assert(Info.CurrentCall->This == nullptr &&
+               "This should not be set for a static call operator");
+        return false;
+      }
+
       // Start with 'Result' referring to the complete closure object...
-      if (auto *MD = cast<CXXMethodDecl>(Info.CurrentCall->Callee);
-          MD->isExplicitObjectMemberFunction()) {
+      if (MD->isExplicitObjectMemberFunction()) {
         APValue *RefValue =
             Info.getParamSlot(Info.CurrentCall->Arguments, MD->getParamDecl(0));
         Result.setFrom(Info.Ctx, *RefValue);
       } else
         Result = *Info.CurrentCall->This;
+
       // ... then update it to refer to the field of the closure object
       // that represents the capture.
       if (!HandleLValueMember(Info, E, Result, FD))
diff --git a/clang/test/Parser/cxx2b-lambdas.cpp b/clang/test/Parser/cxx2b-lambdas.cpp
index bb9ed226afff..ad975a17b6e4 100644
--- a/clang/test/Parser/cxx2b-lambdas.cpp
+++ b/clang/test/Parser/cxx2b-lambdas.cpp
@@ -66,3 +66,15 @@ void static_captures() {
     }
   };
 }
+
+constexpr auto static_capture_constexpr() {
+  char n = 'n';
+  return [n] static { return n; }(); // expected-error {{a static lambda cannot have any captures}}
+}
+static_assert(static_capture_constexpr()); // expected-error {{static assertion expression is not an integral constant expression}}
+
+constexpr auto capture_constexpr() {
+  char n = 'n';
+  return [n] { return n; }();
+}
+static_assert(capture_constexpr());
-- 
GitLab


From 8f1accfb35f2da96e8521efcabdabec74a28bc4e Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu@google.com>
Date: Mon, 11 Dec 2023 22:46:42 -0800
Subject: [PATCH 227/349] Revert "[RISCV] Update the interface of sifive
 vqmaccqoq (#74284)"

This reverts commit dc5570319676c14c48440b4ee87c8cfb35102ff6.

Several bots seem to be failing:

https://lab.llvm.org/buildbot/#/builders/10/builds/34651
https://lab.llvm.org/buildbot/#/builders/178/builds/6320
https://lab.llvm.org/buildbot/#/builders/77/builds/32918
---
 .../clang/Basic/riscv_sifive_vector.td        | 26 +++-----
 .../non-overloaded/sf_vqmacc_4x8x4.c          | 24 ++++----
 .../non-overloaded/sf_vqmaccsu_4x8x4.c        | 24 ++++----
 .../non-overloaded/sf_vqmaccu_4x8x4.c         | 24 ++++----
 .../non-overloaded/sf_vqmaccus_4x8x4.c        | 24 ++++----
 .../non-policy/overloaded/sf_vqmacc_4x8x4.c   | 24 ++++----
 .../non-policy/overloaded/sf_vqmaccsu_4x8x4.c | 24 ++++----
 .../non-policy/overloaded/sf_vqmaccu_4x8x4.c  | 24 ++++----
 .../non-policy/overloaded/sf_vqmaccus_4x8x4.c | 24 ++++----
 .../policy/non-overloaded/sf_vqmacc_4x8x4.c   | 24 ++++----
 .../policy/non-overloaded/sf_vqmaccsu_4x8x4.c | 24 ++++----
 .../policy/non-overloaded/sf_vqmaccu_4x8x4.c  | 24 ++++----
 .../policy/non-overloaded/sf_vqmaccus_4x8x4.c | 24 ++++----
 .../policy/overloaded/sf_vqmacc_4x8x4.c       | 24 ++++----
 .../policy/overloaded/sf_vqmaccsu_4x8x4.c     | 24 ++++----
 .../policy/overloaded/sf_vqmaccu_4x8x4.c      | 24 ++++----
 .../policy/overloaded/sf_vqmaccus_4x8x4.c     | 24 ++++----
 clang/test/Sema/rvv-required-features.c       | 18 +++++-
 llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td    | 61 +++++++------------
 .../test/CodeGen/RISCV/rvv/sf_vqmacc_4x8x4.ll | 58 +++++++++---------
 .../CodeGen/RISCV/rvv/sf_vqmaccsu_4x8x4.ll    | 58 +++++++++---------
 .../CodeGen/RISCV/rvv/sf_vqmaccu_4x8x4.ll     | 58 +++++++++---------
 .../CodeGen/RISCV/rvv/sf_vqmaccus_4x8x4.ll    | 58 +++++++++---------
 23 files changed, 360 insertions(+), 361 deletions(-)

diff --git a/clang/include/clang/Basic/riscv_sifive_vector.td b/clang/include/clang/Basic/riscv_sifive_vector.td
index 61c2ff52d9f7..bb54e2664186 100644
--- a/clang/include/clang/Basic/riscv_sifive_vector.td
+++ b/clang/include/clang/Basic/riscv_sifive_vector.td
@@ -112,7 +112,7 @@ multiclass RVVVFWMACCBuiltinSet<list<list<string>> suffixes_prototypes> {
     defm NAME : RVVOutOp1Op2BuiltinSet<NAME, "b", suffixes_prototypes>;
 }
 
-multiclass RVVVQMACCDODBuiltinSet<list<list<string>> suffixes_prototypes> {
+multiclass RVVVQMACCBuiltinSet<list<list<string>> suffixes_prototypes> {
   let OverloadedName = NAME,
       Name = NAME,
       HasMasked = false,
@@ -120,14 +120,6 @@ multiclass RVVVQMACCDODBuiltinSet<list<list<string>> suffixes_prototypes> {
     defm NAME : RVVOutOp1Op2BuiltinSet<NAME, "i", suffixes_prototypes>;
 }
 
-multiclass RVVVQMACCQOQBuiltinSet<list<list<string>> suffixes_prototypes> {
-   let OverloadedName = NAME,
-       Name = NAME,
-       HasMasked = false,
-       Log2LMUL = [-1, 0, 1, 2] in
-     defm NAME : RVVOutOp1Op2BuiltinSet<NAME, "s", suffixes_prototypes>;
-}
-
 multiclass RVVVFNRCLIPBuiltinSet<string suffix, string prototype, string type_range> {
   let Log2LMUL = [-3, -2, -1, 0, 1, 2],
       Name = NAME,
@@ -138,18 +130,18 @@ multiclass RVVVFNRCLIPBuiltinSet<string suffix, string prototype, string type_ra
 
 let UnMaskedPolicyScheme = HasPolicyOperand in
   let RequiredFeatures = ["Xsfvqmaccdod"] in {
-    defm sf_vqmaccu_2x8x2 : RVVVQMACCDODBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)Uv"]]>;
-    defm sf_vqmacc_2x8x2 : RVVVQMACCDODBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)v"]]>;
-    defm sf_vqmaccus_2x8x2 : RVVVQMACCDODBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)v"]]>;
-    defm sf_vqmaccsu_2x8x2 : RVVVQMACCDODBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)Uv"]]>;
+    defm sf_vqmaccu_2x8x2 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)Uv"]]>;
+    defm sf_vqmacc_2x8x2 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)v"]]>;
+    defm sf_vqmaccus_2x8x2 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)v"]]>;
+    defm sf_vqmaccsu_2x8x2 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)Uv"]]>;
   }
 
 let UnMaskedPolicyScheme = HasPolicyOperand in
   let RequiredFeatures = ["Xsfvqmaccqoq"] in {
-    defm sf_vqmaccu_4x8x4 : RVVVQMACCQOQBuiltinSet<[["", "w", "ww(FixedSEW:8)SUv(FixedSEW:8)Uw"]]>;
-    defm sf_vqmacc_4x8x4 : RVVVQMACCQOQBuiltinSet<[["", "w", "ww(FixedSEW:8)Sv(FixedSEW:8)w"]]>;
-    defm sf_vqmaccus_4x8x4 : RVVVQMACCQOQBuiltinSet<[["", "w", "ww(FixedSEW:8)SUv(FixedSEW:8)w"]]>;
-    defm sf_vqmaccsu_4x8x4 : RVVVQMACCQOQBuiltinSet<[["", "w", "ww(FixedSEW:8)Sv(FixedSEW:8)Uw"]]>;
+    defm sf_vqmaccu_4x8x4 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)Uv"]]>;
+    defm sf_vqmacc_4x8x4 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)v"]]>;
+    defm sf_vqmaccus_4x8x4 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)v"]]>;
+    defm sf_vqmaccsu_4x8x4 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)Uv"]]>;
   }
 
 let UnMaskedPolicyScheme = HasPolicyOperand in
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmacc_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmacc_4x8x4.c
index 80e1c443eb54..935cb2e007d3 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmacc_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmacc_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmacc_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vint8mf2_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmacc_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4_i32m1(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmacc_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmacc_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4_i32m2(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmacc_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmacc_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4_i32m4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmacc_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmacc_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vint8m8_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4_i32m8(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c
index 8c0a6218c1d2..f34517b24bcf 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vuint8mf2_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4_i32m1(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4_i32m2(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4_i32m4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vuint8m8_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4_i32m8(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c
index b40891f417f2..ab7f6627ad1f 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_4x8x4_i32m1
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmaccu_4x8x4_i32m1(vint32m1_t vd, vuint8m1_t vs1, vuint8mf2_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmaccu_4x8x4_i32m1(vint32m1_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4_i32m1(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_4x8x4_i32m2
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmaccu_4x8x4_i32m2(vint32m2_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmaccu_4x8x4_i32m2(vint32m2_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4_i32m2(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_4x8x4_i32m4
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmaccu_4x8x4_i32m4(vint32m4_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmaccu_4x8x4_i32m4(vint32m4_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4_i32m4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_4x8x4_i32m8
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmaccu_4x8x4_i32m8(vint32m8_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmaccu_4x8x4_i32m8(vint32m8_t vd, vuint8m1_t vs1, vuint8m8_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4_i32m8(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c
index d106aab64c51..d0bcdcbf40cc 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_4x8x4_i32m1
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmaccus_4x8x4_i32m1(vint32m1_t vd, vuint8m1_t vs1, vint8mf2_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmaccus_4x8x4_i32m1(vint32m1_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4_i32m1(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_4x8x4_i32m2
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmaccus_4x8x4_i32m2(vint32m2_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmaccus_4x8x4_i32m2(vint32m2_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4_i32m2(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_4x8x4_i32m4
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmaccus_4x8x4_i32m4(vint32m4_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmaccus_4x8x4_i32m4(vint32m4_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4_i32m4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_4x8x4_i32m8
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmaccus_4x8x4_i32m8(vint32m8_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmaccus_4x8x4_i32m8(vint32m8_t vd, vuint8m1_t vs1, vint8m8_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4_i32m8(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmacc_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmacc_4x8x4.c
index 88fae7306944..839d09c4f9a9 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmacc_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmacc_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmacc_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vint8mf2_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmacc_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmacc_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmacc_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmacc_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmacc_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmacc_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmacc_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vint8m8_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccsu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccsu_4x8x4.c
index 0aec4bfd9fe2..b18853043e92 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccsu_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccsu_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vuint8mf2_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vuint8m8_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccu_4x8x4.c
index 81965e86f77c..4cb966b08f23 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccu_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccu_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_4x8x4_i32m1
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmaccu_4x8x4_i32m1(vint32m1_t vd, vuint8m1_t vs1, vuint8mf2_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmaccu_4x8x4_i32m1(vint32m1_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_4x8x4_i32m2
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmaccu_4x8x4_i32m2(vint32m2_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmaccu_4x8x4_i32m2(vint32m2_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_4x8x4_i32m4
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmaccu_4x8x4_i32m4(vint32m4_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmaccu_4x8x4_i32m4(vint32m4_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_4x8x4_i32m8
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmaccu_4x8x4_i32m8(vint32m8_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmaccu_4x8x4_i32m8(vint32m8_t vd, vuint8m1_t vs1, vuint8m8_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccus_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccus_4x8x4.c
index f2544cf3ef2a..f558151f88a3 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccus_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccus_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_4x8x4_i32m1
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmaccus_4x8x4_i32m1(vint32m1_t vd, vuint8m1_t vs1, vint8mf2_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmaccus_4x8x4_i32m1(vint32m1_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_4x8x4_i32m2
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmaccus_4x8x4_i32m2(vint32m2_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmaccus_4x8x4_i32m2(vint32m2_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_4x8x4_i32m4
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmaccus_4x8x4_i32m4(vint32m4_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmaccus_4x8x4_i32m4(vint32m4_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_4x8x4_i32m8
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 3)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmaccus_4x8x4_i32m8(vint32m8_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmaccus_4x8x4_i32m8(vint32m8_t vd, vuint8m1_t vs1, vint8m8_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmacc_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmacc_4x8x4.c
index 8fdeac62a31f..05c10840cabf 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmacc_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmacc_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1_tu
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmacc_4x8x4_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vint8mf2_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmacc_4x8x4_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4_i32m1_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2_tu
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmacc_4x8x4_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmacc_4x8x4_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4_i32m2_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4_tu
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmacc_4x8x4_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmacc_4x8x4_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4_i32m4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8_tu
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmacc_4x8x4_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmacc_4x8x4_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vint8m8_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4_i32m8_tu(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccsu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccsu_4x8x4.c
index e02c790dfbeb..bce1a4e9443f 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccsu_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccsu_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1_tu
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vuint8mf2_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4_i32m1_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2_tu
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4_i32m2_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4_tu
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4_i32m4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8_tu
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vuint8m8_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4_i32m8_tu(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccu_4x8x4.c
index ddeb6de00716..36aaae9caebf 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccu_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccu_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_4x8x4_i32m1_tu
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmaccu_4x8x4_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vuint8mf2_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmaccu_4x8x4_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4_i32m1_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_4x8x4_i32m2_tu
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmaccu_4x8x4_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmaccu_4x8x4_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4_i32m2_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_4x8x4_i32m4_tu
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmaccu_4x8x4_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmaccu_4x8x4_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4_i32m4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_4x8x4_i32m8_tu
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmaccu_4x8x4_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmaccu_4x8x4_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vuint8m8_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4_i32m8_tu(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccus_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccus_4x8x4.c
index 397e406c2ee5..f5ac2bf0f1f3 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccus_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccus_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_4x8x4_i32m1_tu
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmaccus_4x8x4_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vint8mf2_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmaccus_4x8x4_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4_i32m1_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_4x8x4_i32m2_tu
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmaccus_4x8x4_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmaccus_4x8x4_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4_i32m2_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_4x8x4_i32m4_tu
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmaccus_4x8x4_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmaccus_4x8x4_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4_i32m4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_4x8x4_i32m8_tu
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmaccus_4x8x4_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmaccus_4x8x4_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vint8m8_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4_i32m8_tu(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmacc_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmacc_4x8x4.c
index 7b3b25a20331..531bc2b2b942 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmacc_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmacc_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1_tu
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmacc_4x8x4_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vint8mf2_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmacc_4x8x4_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2_tu
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmacc_4x8x4_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmacc_4x8x4_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4_tu
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmacc_4x8x4_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmacc_4x8x4_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8_tu
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmacc_4x8x4_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmacc_4x8x4_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vint8m8_t vs2, size_t vl) {
   return __riscv_sf_vqmacc_4x8x4_tu(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccsu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccsu_4x8x4.c
index 2f3cbeec26fc..23bba523aaa4 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccsu_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccsu_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1_tu
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vuint8mf2_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2_tu
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4_tu
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8_tu
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vuint8m8_t vs2, size_t vl) {
   return __riscv_sf_vqmaccsu_4x8x4_tu(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccu_4x8x4.c
index 1f2b2a1c8645..950688c6c785 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccu_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccu_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_4x8x4_i32m1_tu
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmaccu_4x8x4_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vuint8mf2_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmaccu_4x8x4_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_4x8x4_i32m2_tu
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmaccu_4x8x4_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmaccu_4x8x4_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_4x8x4_i32m4_tu
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmaccu_4x8x4_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmaccu_4x8x4_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_4x8x4_i32m8_tu
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmaccu_4x8x4_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmaccu_4x8x4_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vuint8m8_t vs2, size_t vl) {
   return __riscv_sf_vqmaccu_4x8x4_tu(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccus_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccus_4x8x4.c
index 923234fe8e2b..7bdce95043ee 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccus_4x8x4.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccus_4x8x4.c
@@ -7,41 +7,41 @@
 #include <sifive_vector.h>
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_4x8x4_i32m1_tu
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
-vint32m1_t test_sf_vqmaccus_4x8x4_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vint8mf2_t vs2, size_t vl) {
+vint32m1_t test_sf_vqmaccus_4x8x4_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_4x8x4_i32m2_tu
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
-vint32m2_t test_sf_vqmaccus_4x8x4_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) {
+vint32m2_t test_sf_vqmaccus_4x8x4_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_4x8x4_i32m4_tu
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
-vint32m4_t test_sf_vqmaccus_4x8x4_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) {
+vint32m4_t test_sf_vqmaccus_4x8x4_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4_tu(vd, vs1, vs2, vl);
 }
 
 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_4x8x4_i32m8_tu
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 2)
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
-vint32m8_t test_sf_vqmaccus_4x8x4_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) {
+vint32m8_t test_sf_vqmaccus_4x8x4_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vint8m8_t vs2, size_t vl) {
   return __riscv_sf_vqmaccus_4x8x4_tu(vd, vs1, vs2, vl);
 }
diff --git a/clang/test/Sema/rvv-required-features.c b/clang/test/Sema/rvv-required-features.c
index 5846f338aa80..2714ef04b9bf 100644
--- a/clang/test/Sema/rvv-required-features.c
+++ b/clang/test/Sema/rvv-required-features.c
@@ -1,6 +1,8 @@
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp \
-// RUN:     -target-feature +xsfvqmaccdod -target-feature +xsfvqmaccqoq %s -fsyntax-only -verify
+// RUN:     -target-feature +xsfvqmaccdod -target-feature +xsfvqmaccqoq \
+// RUN:     -target-feature +experimental-zvfbfmin -target-feature +xsfvfwmaccqqq \
+// RUN:     -target-feature +xsfvfnrclipxfqf %s -fsyntax-only -verify
 
 // expected-no-diagnostics
 
@@ -23,6 +25,18 @@ void test_xsfvqmaccdod(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
   __riscv_sf_vqmacc_2x8x2(vd, vs1, vs2, vl);
 }
 
-void test_xsfvqmaccqoq(vint32m1_t vd, vint8m1_t vs1, vint8mf2_t vs2, size_t vl) {
+void test_xsfvqmaccqoq(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
   __riscv_sf_vqmacc_4x8x4(vd, vs1, vs2, vl);
 }
+
+void test_xsfvfwmaccqqq(vfloat32m1_t vd, vbfloat16m1_t vs1, vbfloat16mf2_t vs2, size_t vl) {
+  __riscv_sf_vfwmacc_4x4x4(vd, vs1, vs2, vl);
+}
+
+void test_xsfvfnrclipxufqf(vfloat32m1_t vs1, float rs2, size_t vl) {
+  __riscv_sf_vfnrclip_xu_f_qf(vs1, rs2, vl);
+}
+
+void test_xsfvfnrclipxfqf(vfloat32m1_t vs1, float rs2, size_t vl) {
+  __riscv_sf_vfnrclip_x_f_qf(vs1, rs2, vl);
+}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
index 9812aa501e04..fa618b437ce7 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
@@ -349,20 +349,14 @@ multiclass VPseudoSiFiveVMACC<string mx, VReg vd_type, VReg vs2_type,
       : VPseudoTernaryNoMaskWithPolicy<vd_type, V_M1.vrclass, vs2_type, Constraint>;
 }
 
-multiclass VPseudoSiFiveVQMACCDOD<string Constraint = ""> {
+multiclass VPseudoSiFiveVQMACC<string Constraint = ""> {
   foreach m = MxListVF8 in
     defm NAME : VPseudoSiFiveVMACC<m.MX, m.vrclass, m.vrclass, Constraint>;
 }
 
-multiclass VPseudoSiFiveVQMACCQOQ<string Constraint = ""> {
-   foreach m = MxListVF8 in
-     defm NAME : VPseudoSiFiveVMACC<m.MX, m.vrclass, m.f2vrclass, Constraint>;
-}
-
 multiclass VPseudoSiFiveVFWMACC<string Constraint = ""> {
-  foreach i = [0, 1, 2, 3, 4] in
-    defm NAME : VPseudoSiFiveVMACC<MxListVF4[i].MX, MxListFW[i].wvrclass,
-                                   MxListFW[i].vrclass, Constraint>;
+  foreach m = MxListFW in
+    defm NAME : VPseudoSiFiveVMACC<m.MX, m.wvrclass, m.vrclass, Constraint>;
 }
 
 multiclass VPseudoSiFiveVFNRCLIP<string Constraint = "@earlyclobber $rd"> {
@@ -404,17 +398,17 @@ let Predicates = [HasVendorXSfvcp] in {
 }
 
 let Predicates = [HasVendorXSfvqmaccdod] in {
-  defm VQMACCU_2x8x2  : VPseudoSiFiveVQMACCDOD;
-  defm VQMACC_2x8x2   : VPseudoSiFiveVQMACCDOD;
-  defm VQMACCUS_2x8x2 : VPseudoSiFiveVQMACCDOD;
-  defm VQMACCSU_2x8x2 : VPseudoSiFiveVQMACCDOD;
+  defm VQMACCU_2x8x2  : VPseudoSiFiveVQMACC;
+  defm VQMACC_2x8x2   : VPseudoSiFiveVQMACC;
+  defm VQMACCUS_2x8x2 : VPseudoSiFiveVQMACC;
+  defm VQMACCSU_2x8x2 : VPseudoSiFiveVQMACC;
 }
 
 let Predicates = [HasVendorXSfvqmaccqoq] in {
-  defm VQMACCU_4x8x4  : VPseudoSiFiveVQMACCQOQ;
-  defm VQMACC_4x8x4   : VPseudoSiFiveVQMACCQOQ;
-  defm VQMACCUS_4x8x4 : VPseudoSiFiveVQMACCQOQ;
-  defm VQMACCSU_4x8x4 : VPseudoSiFiveVQMACCQOQ;
+  defm VQMACCU_4x8x4  : VPseudoSiFiveVQMACC;
+  defm VQMACC_4x8x4   : VPseudoSiFiveVQMACC;
+  defm VQMACCUS_4x8x4 : VPseudoSiFiveVQMACC;
+  defm VQMACCSU_4x8x4 : VPseudoSiFiveVQMACC;
 }
 
 let Predicates = [HasVendorXSfvfwmaccqqq] in {
@@ -565,30 +559,21 @@ multiclass VPatVMACC<string intrinsic, string instruction, string kind,
     def : VPatTernaryNoMaskWithPolicy<"int_riscv_sf_" # intrinsic,
                                       "Pseudo" # instruction, kind, VdInfo.Vector,
                                       vec_m1, Vs2Info.Vector,
-                                      Vs2Info.Log2SEW, VdInfo.LMul,
+                                      Vs2Info.Log2SEW, Vs2Info.LMul,
                                       VdInfo.RegClass, VR, Vs2Info.RegClass>;
   }
 }
 
-defset list<VTypeInfoToWide> VQMACCDODInfoPairs = {
+defset list<VTypeInfoToWide> VQMACCInfoPairs = {
   def : VTypeInfoToWide<VI8M1, VI32M1>;
   def : VTypeInfoToWide<VI8M2, VI32M2>;
   def : VTypeInfoToWide<VI8M4, VI32M4>;
   def : VTypeInfoToWide<VI8M8, VI32M8>;
 }
 
-defset list<VTypeInfoToWide> VQMACCQOQInfoPairs = {
-   def : VTypeInfoToWide<VI8MF2, VI32M1>;
-   def : VTypeInfoToWide<VI8M1, VI32M2>;
-   def : VTypeInfoToWide<VI8M2, VI32M4>;
-   def : VTypeInfoToWide<VI8M4, VI32M8>;
-}
-
-multiclass VPatVQMACCDOD<string intrinsic, string instruction, string kind>
-    : VPatVMACC<intrinsic, instruction, kind, VQMACCDODInfoPairs, vint8m1_t>;
+multiclass VPatVQMACC<string intrinsic, string instruction, string kind>
+    : VPatVMACC<intrinsic, instruction, kind, VQMACCInfoPairs, vint8m1_t>;
 
-multiclass VPatVQMACCQOQ<string intrinsic, string instruction, string kind>
-    : VPatVMACC<intrinsic, instruction, kind, VQMACCQOQInfoPairs, vint8m1_t>;
 
 multiclass VPatVFWMACC<string intrinsic, string instruction, string kind>
     : VPatVMACC<intrinsic, instruction, kind, AllWidenableBFloatToFloatVectors,
@@ -650,17 +635,17 @@ let Predicates = [HasVendorXSfvcp] in {
 }
 
 let Predicates = [HasVendorXSfvqmaccdod] in {
-  defm : VPatVQMACCDOD<"vqmaccu_2x8x2", "VQMACCU", "2x8x2">;
-  defm : VPatVQMACCDOD<"vqmacc_2x8x2", "VQMACC", "2x8x2">;
-  defm : VPatVQMACCDOD<"vqmaccus_2x8x2", "VQMACCUS", "2x8x2">;
-  defm : VPatVQMACCDOD<"vqmaccsu_2x8x2", "VQMACCSU", "2x8x2">;
+  defm : VPatVQMACC<"vqmaccu_2x8x2", "VQMACCU", "2x8x2">;
+  defm : VPatVQMACC<"vqmacc_2x8x2", "VQMACC", "2x8x2">;
+  defm : VPatVQMACC<"vqmaccus_2x8x2", "VQMACCUS", "2x8x2">;
+  defm : VPatVQMACC<"vqmaccsu_2x8x2", "VQMACCSU", "2x8x2">;
 }
 
 let Predicates = [HasVendorXSfvqmaccqoq] in {
-  defm : VPatVQMACCQOQ<"vqmaccu_4x8x4", "VQMACCU", "4x8x4">;
-  defm : VPatVQMACCQOQ<"vqmacc_4x8x4", "VQMACC", "4x8x4">;
-  defm : VPatVQMACCQOQ<"vqmaccus_4x8x4", "VQMACCUS", "4x8x4">;
-  defm : VPatVQMACCQOQ<"vqmaccsu_4x8x4", "VQMACCSU", "4x8x4">;
+  defm : VPatVQMACC<"vqmaccu_4x8x4", "VQMACCU", "4x8x4">;
+  defm : VPatVQMACC<"vqmacc_4x8x4", "VQMACC", "4x8x4">;
+  defm : VPatVQMACC<"vqmaccus_4x8x4", "VQMACCUS", "4x8x4">;
+  defm : VPatVQMACC<"vqmaccsu_4x8x4", "VQMACCSU", "4x8x4">;
 }
 
 let Predicates = [HasVendorXSfvfwmaccqqq] in {
diff --git a/llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_4x8x4.ll b/llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_4x8x4.ll
index 300fda43ada4..843e4bda4d12 100644
--- a/llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_4x8x4.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_4x8x4.ll
@@ -7,10 +7,10 @@
 declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8(
   <vscale x 2 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
   iXLen, iXLen);
 
-define <vscale x 2 x i32> @intrinsic_vqmacc_4x8x4_tu_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vqmacc_4x8x4_tu_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmacc_4x8x4_tu_i32m1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
@@ -20,13 +20,13 @@ entry:
   %a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8(
     <vscale x 2 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 4 x i8> %2,
+    <vscale x 8 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 2 x i32> %a
 }
 
-define <vscale x 2 x i32> @intrinsic_vqmacc_4x8x4_ta_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vqmacc_4x8x4_ta_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmacc_4x8x4_ta_i32m1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
@@ -36,7 +36,7 @@ entry:
   %a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8(
     <vscale x 2 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 4 x i8> %2,
+    <vscale x 8 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 2 x i32> %a
@@ -45,36 +45,36 @@ entry:
 declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8(
   <vscale x 4 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
   iXLen, iXLen);
 
-define <vscale x 4 x i32> @intrinsic_vqmacc_4x8x4_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
+define <vscale x 4 x i32> @intrinsic_vqmacc_4x8x4_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmacc_4x8x4_tu_i32m2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
-; CHECK-NEXT:    sf.vqmacc.4x8x4 v8, v10, v11
+; CHECK-NEXT:    sf.vqmacc.4x8x4 v8, v10, v12
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8(
     <vscale x 4 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 8 x i8> %2,
+    <vscale x 16 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 4 x i32> %a
 }
 
-define <vscale x 4 x i32> @intrinsic_vqmacc_4x8x4_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
+define <vscale x 4 x i32> @intrinsic_vqmacc_4x8x4_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmacc_4x8x4_ta_i32m2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT:    sf.vqmacc.4x8x4 v8, v10, v11
+; CHECK-NEXT:    sf.vqmacc.4x8x4 v8, v10, v12
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8(
     <vscale x 4 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 8 x i8> %2,
+    <vscale x 16 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 4 x i32> %a
@@ -83,36 +83,36 @@ entry:
 declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8(
   <vscale x 8 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 16 x i8>,
+  <vscale x 32 x i8>,
   iXLen, iXLen);
 
-define <vscale x 8 x i32> @intrinsic_vqmacc_4x8x4_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
+define <vscale x 8 x i32> @intrinsic_vqmacc_4x8x4_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmacc_4x8x4_tu_i32m4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
-; CHECK-NEXT:    sf.vqmacc.4x8x4 v8, v12, v14
+; CHECK-NEXT:    sf.vqmacc.4x8x4 v8, v12, v16
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 16 x i8> %2,
+    <vscale x 32 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 8 x i32> %a
 }
 
-define <vscale x 8 x i32> @intrinsic_vqmacc_4x8x4_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
+define <vscale x 8 x i32> @intrinsic_vqmacc_4x8x4_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmacc_4x8x4_ta_i32m4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT:    sf.vqmacc.4x8x4 v8, v12, v14
+; CHECK-NEXT:    sf.vqmacc.4x8x4 v8, v12, v16
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 16 x i8> %2,
+    <vscale x 32 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 8 x i32> %a
@@ -121,36 +121,38 @@ entry:
 declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8(
   <vscale x 16 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 32 x i8>,
+  <vscale x 64 x i8>,
   iXLen, iXLen);
 
-define <vscale x 16 x i32> @intrinsic_vqmacc_4x8x4_tu_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
+define <vscale x 16 x i32> @intrinsic_vqmacc_4x8x4_tu_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmacc_4x8x4_tu_i32m8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
-; CHECK-NEXT:    sf.vqmacc.4x8x4 v8, v16, v20
+; CHECK-NEXT:    vl8r.v v24, (a0)
+; CHECK-NEXT:    vsetvli zero, a1, e8, m1, tu, ma
+; CHECK-NEXT:    sf.vqmacc.4x8x4 v8, v16, v24
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8(
     <vscale x 16 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 32 x i8> %2,
+    <vscale x 64 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 16 x i32> %a
 }
 
-define <vscale x 16 x i32> @intrinsic_vqmacc_4x8x4_ta_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
+define <vscale x 16 x i32> @intrinsic_vqmacc_4x8x4_ta_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmacc_4x8x4_ta_i32m8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT:    sf.vqmacc.4x8x4 v8, v16, v20
+; CHECK-NEXT:    vl8r.v v24, (a0)
+; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT:    sf.vqmacc.4x8x4 v8, v16, v24
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8(
     <vscale x 16 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 32 x i8> %2,
+    <vscale x 64 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 16 x i32> %a
diff --git a/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_4x8x4.ll b/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_4x8x4.ll
index 1df81527850e..45a3b22d9618 100644
--- a/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_4x8x4.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_4x8x4.ll
@@ -7,10 +7,10 @@
 declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8(
   <vscale x 2 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
   iXLen, iXLen);
 
-define <vscale x 2 x i32> @intrinsic_vqmaccsu_4x8x4_tu_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vqmaccsu_4x8x4_tu_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_tu_i32m1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
@@ -20,13 +20,13 @@ entry:
   %a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8(
     <vscale x 2 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 4 x i8> %2,
+    <vscale x 8 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 2 x i32> %a
 }
 
-define <vscale x 2 x i32> @intrinsic_vqmaccsu_4x8x4_ta_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vqmaccsu_4x8x4_ta_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_ta_i32m1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
@@ -36,7 +36,7 @@ entry:
   %a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8(
     <vscale x 2 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 4 x i8> %2,
+    <vscale x 8 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 2 x i32> %a
@@ -45,36 +45,36 @@ entry:
 declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8(
   <vscale x 4 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
   iXLen, iXLen);
 
-define <vscale x 4 x i32> @intrinsic_vqmaccsu_4x8x4_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
+define <vscale x 4 x i32> @intrinsic_vqmaccsu_4x8x4_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_tu_i32m2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
-; CHECK-NEXT:    sf.vqmaccsu.4x8x4 v8, v10, v11
+; CHECK-NEXT:    sf.vqmaccsu.4x8x4 v8, v10, v12
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8(
     <vscale x 4 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 8 x i8> %2,
+    <vscale x 16 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 4 x i32> %a
 }
 
-define <vscale x 4 x i32> @intrinsic_vqmaccsu_4x8x4_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
+define <vscale x 4 x i32> @intrinsic_vqmaccsu_4x8x4_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_ta_i32m2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT:    sf.vqmaccsu.4x8x4 v8, v10, v11
+; CHECK-NEXT:    sf.vqmaccsu.4x8x4 v8, v10, v12
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8(
     <vscale x 4 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 8 x i8> %2,
+    <vscale x 16 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 4 x i32> %a
@@ -83,36 +83,36 @@ entry:
 declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8(
   <vscale x 8 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 16 x i8>,
+  <vscale x 32 x i8>,
   iXLen, iXLen);
 
-define <vscale x 8 x i32> @intrinsic_vqmaccsu_4x8x4_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
+define <vscale x 8 x i32> @intrinsic_vqmaccsu_4x8x4_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_tu_i32m4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
-; CHECK-NEXT:    sf.vqmaccsu.4x8x4 v8, v12, v14
+; CHECK-NEXT:    sf.vqmaccsu.4x8x4 v8, v12, v16
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 16 x i8> %2,
+    <vscale x 32 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 8 x i32> %a
 }
 
-define <vscale x 8 x i32> @intrinsic_vqmaccsu_4x8x4_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
+define <vscale x 8 x i32> @intrinsic_vqmaccsu_4x8x4_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_ta_i32m4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT:    sf.vqmaccsu.4x8x4 v8, v12, v14
+; CHECK-NEXT:    sf.vqmaccsu.4x8x4 v8, v12, v16
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 16 x i8> %2,
+    <vscale x 32 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 8 x i32> %a
@@ -121,36 +121,38 @@ entry:
 declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8(
   <vscale x 16 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 32 x i8>,
+  <vscale x 64 x i8>,
   iXLen, iXLen);
 
-define <vscale x 16 x i32> @intrinsic_vqmaccsu_4x8x4_tu_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
+define <vscale x 16 x i32> @intrinsic_vqmaccsu_4x8x4_tu_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_tu_i32m8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
-; CHECK-NEXT:    sf.vqmaccsu.4x8x4 v8, v16, v20
+; CHECK-NEXT:    vl8r.v v24, (a0)
+; CHECK-NEXT:    vsetvli zero, a1, e8, m1, tu, ma
+; CHECK-NEXT:    sf.vqmaccsu.4x8x4 v8, v16, v24
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8(
     <vscale x 16 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 32 x i8> %2,
+    <vscale x 64 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 16 x i32> %a
 }
 
-define <vscale x 16 x i32> @intrinsic_vqmaccsu_4x8x4_ta_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
+define <vscale x 16 x i32> @intrinsic_vqmaccsu_4x8x4_ta_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_ta_i32m8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT:    sf.vqmaccsu.4x8x4 v8, v16, v20
+; CHECK-NEXT:    vl8r.v v24, (a0)
+; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT:    sf.vqmaccsu.4x8x4 v8, v16, v24
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8(
     <vscale x 16 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 32 x i8> %2,
+    <vscale x 64 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 16 x i32> %a
diff --git a/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_4x8x4.ll b/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_4x8x4.ll
index be2ce2fffe31..9d15ab68a091 100644
--- a/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_4x8x4.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_4x8x4.ll
@@ -7,10 +7,10 @@
 declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv8i8(
   <vscale x 2 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
   iXLen, iXLen);
 
-define <vscale x 2 x i32> @intrinsic_vqmaccu_4x8x4_tu_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vqmaccu_4x8x4_tu_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_tu_i32m1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
@@ -20,13 +20,13 @@ entry:
   %a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv8i8(
     <vscale x 2 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 4 x i8> %2,
+    <vscale x 8 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 2 x i32> %a
 }
 
-define <vscale x 2 x i32> @intrinsic_vqmaccu_4x8x4_ta_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vqmaccu_4x8x4_ta_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_ta_i32m1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
@@ -36,7 +36,7 @@ entry:
   %a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv8i8(
     <vscale x 2 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 4 x i8> %2,
+    <vscale x 8 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 2 x i32> %a
@@ -45,36 +45,36 @@ entry:
 declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv16i8(
   <vscale x 4 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
   iXLen, iXLen);
 
-define <vscale x 4 x i32> @intrinsic_vqmaccu_4x8x4_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
+define <vscale x 4 x i32> @intrinsic_vqmaccu_4x8x4_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_tu_i32m2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
-; CHECK-NEXT:    sf.vqmaccu.4x8x4 v8, v10, v11
+; CHECK-NEXT:    sf.vqmaccu.4x8x4 v8, v10, v12
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv16i8(
     <vscale x 4 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 8 x i8> %2,
+    <vscale x 16 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 4 x i32> %a
 }
 
-define <vscale x 4 x i32> @intrinsic_vqmaccu_4x8x4_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
+define <vscale x 4 x i32> @intrinsic_vqmaccu_4x8x4_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_ta_i32m2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT:    sf.vqmaccu.4x8x4 v8, v10, v11
+; CHECK-NEXT:    sf.vqmaccu.4x8x4 v8, v10, v12
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv16i8(
     <vscale x 4 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 8 x i8> %2,
+    <vscale x 16 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 4 x i32> %a
@@ -83,36 +83,36 @@ entry:
 declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv32i8(
   <vscale x 8 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 16 x i8>,
+  <vscale x 32 x i8>,
   iXLen, iXLen);
 
-define <vscale x 8 x i32> @intrinsic_vqmaccu_4x8x4_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
+define <vscale x 8 x i32> @intrinsic_vqmaccu_4x8x4_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_tu_i32m4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
-; CHECK-NEXT:    sf.vqmaccu.4x8x4 v8, v12, v14
+; CHECK-NEXT:    sf.vqmaccu.4x8x4 v8, v12, v16
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv32i8(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 16 x i8> %2,
+    <vscale x 32 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 8 x i32> %a
 }
 
-define <vscale x 8 x i32> @intrinsic_vqmaccu_4x8x4_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
+define <vscale x 8 x i32> @intrinsic_vqmaccu_4x8x4_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_ta_i32m4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT:    sf.vqmaccu.4x8x4 v8, v12, v14
+; CHECK-NEXT:    sf.vqmaccu.4x8x4 v8, v12, v16
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv32i8(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 16 x i8> %2,
+    <vscale x 32 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 8 x i32> %a
@@ -121,36 +121,38 @@ entry:
 declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv64i8(
   <vscale x 16 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 32 x i8>,
+  <vscale x 64 x i8>,
   iXLen, iXLen);
 
-define <vscale x 16 x i32> @intrinsic_vqmaccu_4x8x4_tu_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
+define <vscale x 16 x i32> @intrinsic_vqmaccu_4x8x4_tu_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_tu_i32m8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
-; CHECK-NEXT:    sf.vqmaccu.4x8x4 v8, v16, v20
+; CHECK-NEXT:    vl8r.v v24, (a0)
+; CHECK-NEXT:    vsetvli zero, a1, e8, m1, tu, ma
+; CHECK-NEXT:    sf.vqmaccu.4x8x4 v8, v16, v24
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv64i8(
     <vscale x 16 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 32 x i8> %2,
+    <vscale x 64 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 16 x i32> %a
 }
 
-define <vscale x 16 x i32> @intrinsic_vqmaccu_4x8x4_ta_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
+define <vscale x 16 x i32> @intrinsic_vqmaccu_4x8x4_ta_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_ta_i32m8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT:    sf.vqmaccu.4x8x4 v8, v16, v20
+; CHECK-NEXT:    vl8r.v v24, (a0)
+; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT:    sf.vqmaccu.4x8x4 v8, v16, v24
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv64i8(
     <vscale x 16 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 32 x i8> %2,
+    <vscale x 64 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 16 x i32> %a
diff --git a/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccus_4x8x4.ll b/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccus_4x8x4.ll
index caa1b226bd39..d9b62d8a5769 100644
--- a/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccus_4x8x4.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccus_4x8x4.ll
@@ -7,10 +7,10 @@
 declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv8i8(
   <vscale x 2 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
   iXLen, iXLen);
 
-define <vscale x 2 x i32> @intrinsic_vqmaccus_4x8x4_tu_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vqmaccus_4x8x4_tu_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_tu_i32m1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
@@ -20,13 +20,13 @@ entry:
   %a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv8i8(
     <vscale x 2 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 4 x i8> %2,
+    <vscale x 8 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 2 x i32> %a
 }
 
-define <vscale x 2 x i32> @intrinsic_vqmaccus_4x8x4_ta_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vqmaccus_4x8x4_ta_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_ta_i32m1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
@@ -36,7 +36,7 @@ entry:
   %a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv8i8(
     <vscale x 2 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 4 x i8> %2,
+    <vscale x 8 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 2 x i32> %a
@@ -45,36 +45,36 @@ entry:
 declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv16i8(
   <vscale x 4 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
   iXLen, iXLen);
 
-define <vscale x 4 x i32> @intrinsic_vqmaccus_4x8x4_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
+define <vscale x 4 x i32> @intrinsic_vqmaccus_4x8x4_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_tu_i32m2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
-; CHECK-NEXT:    sf.vqmaccus.4x8x4 v8, v10, v11
+; CHECK-NEXT:    sf.vqmaccus.4x8x4 v8, v10, v12
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv16i8(
     <vscale x 4 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 8 x i8> %2,
+    <vscale x 16 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 4 x i32> %a
 }
 
-define <vscale x 4 x i32> @intrinsic_vqmaccus_4x8x4_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
+define <vscale x 4 x i32> @intrinsic_vqmaccus_4x8x4_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_ta_i32m2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT:    sf.vqmaccus.4x8x4 v8, v10, v11
+; CHECK-NEXT:    sf.vqmaccus.4x8x4 v8, v10, v12
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv16i8(
     <vscale x 4 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 8 x i8> %2,
+    <vscale x 16 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 4 x i32> %a
@@ -83,36 +83,36 @@ entry:
 declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv32i8(
   <vscale x 8 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 16 x i8>,
+  <vscale x 32 x i8>,
   iXLen, iXLen);
 
-define <vscale x 8 x i32> @intrinsic_vqmaccus_4x8x4_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
+define <vscale x 8 x i32> @intrinsic_vqmaccus_4x8x4_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_tu_i32m4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
-; CHECK-NEXT:    sf.vqmaccus.4x8x4 v8, v12, v14
+; CHECK-NEXT:    sf.vqmaccus.4x8x4 v8, v12, v16
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv32i8(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 16 x i8> %2,
+    <vscale x 32 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 8 x i32> %a
 }
 
-define <vscale x 8 x i32> @intrinsic_vqmaccus_4x8x4_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
+define <vscale x 8 x i32> @intrinsic_vqmaccus_4x8x4_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_ta_i32m4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT:    sf.vqmaccus.4x8x4 v8, v12, v14
+; CHECK-NEXT:    sf.vqmaccus.4x8x4 v8, v12, v16
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv32i8(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 16 x i8> %2,
+    <vscale x 32 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 8 x i32> %a
@@ -121,36 +121,38 @@ entry:
 declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8(
   <vscale x 16 x i32>,
   <vscale x 8 x i8>,
-  <vscale x 32 x i8>,
+  <vscale x 64 x i8>,
   iXLen, iXLen);
 
-define <vscale x 16 x i32> @intrinsic_vqmaccus_4x8x4_tu_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
+define <vscale x 16 x i32> @intrinsic_vqmaccus_4x8x4_tu_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_tu_i32m8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma
-; CHECK-NEXT:    sf.vqmaccus.4x8x4 v8, v16, v20
+; CHECK-NEXT:    vl8r.v v24, (a0)
+; CHECK-NEXT:    vsetvli zero, a1, e8, m1, tu, ma
+; CHECK-NEXT:    sf.vqmaccus.4x8x4 v8, v16, v24
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8(
     <vscale x 16 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 32 x i8> %2,
+    <vscale x 64 x i8> %2,
     iXLen %3, iXLen 2)
 
   ret <vscale x 16 x i32> %a
 }
 
-define <vscale x 16 x i32> @intrinsic_vqmaccus_4x8x4_ta_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
+define <vscale x 16 x i32> @intrinsic_vqmaccus_4x8x4_ta_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_ta_i32m8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT:    sf.vqmaccus.4x8x4 v8, v16, v20
+; CHECK-NEXT:    vl8r.v v24, (a0)
+; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT:    sf.vqmaccus.4x8x4 v8, v16, v24
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8(
     <vscale x 16 x i32> %0,
     <vscale x 8 x i8> %1,
-    <vscale x 32 x i8> %2,
+    <vscale x 64 x i8> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 16 x i32> %a
-- 
GitLab


From d2672a550137c0d9c3f4d05c8eb41dc5ab51867b Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min@myhsu.dev>
Date: Mon, 11 Dec 2023 23:00:21 -0800
Subject: [PATCH 228/349] [M68k][MC] Add fmove.l from / to fp control registers

Including splitting up the FPCR register class into classes with finer
granularities.
Right now we only support address / data registers as source /
destinations.
---
 .../Target/M68k/AsmParser/M68kAsmParser.cpp   | 42 ++++++++++++++---
 .../M68k/Disassembler/M68kDisassembler.cpp    | 17 +++++--
 llvm/lib/Target/M68k/M68kInstrData.td         | 46 +++++++++++++++++++
 llvm/lib/Target/M68k/M68kInstrInfo.td         | 10 ++++
 llvm/lib/Target/M68k/M68kRegisterInfo.td      |  5 +-
 .../M68k/MCTargetDesc/M68kMCCodeEmitter.cpp   | 24 ++++++++++
 llvm/test/MC/M68k/Data/Classes/MxFMove_FSYS.s | 17 +++++++
 7 files changed, 149 insertions(+), 12 deletions(-)
 create mode 100644 llvm/test/MC/M68k/Data/Classes/MxFMove_FSYS.s

diff --git a/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp b/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
index 31e525ad4d79..b2c0fda1ccc2 100644
--- a/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
+++ b/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
@@ -156,6 +156,7 @@ public:
   bool isAReg() const;
   bool isDReg() const;
   bool isFPDReg() const;
+  bool isFPCReg() const;
   unsigned getReg() const override;
   void addRegOperands(MCInst &Inst, unsigned N) const;
 
@@ -254,9 +255,13 @@ static inline unsigned getRegisterIndex(unsigned Register) {
     // SP is sadly not contiguous with the rest of the An registers
     return 15;
 
+  // We don't care about the indices of these registers.
   case M68k::PC:
   case M68k::CCR:
-    return 16;
+  case M68k::FPC:
+  case M68k::FPS:
+  case M68k::FPIAR:
+    return UINT_MAX;
 
   default:
     llvm_unreachable("unexpected register number");
@@ -488,7 +493,8 @@ void M68kOperand::addPCIOperands(MCInst &Inst, unsigned N) const {
 }
 
 static inline bool checkRegisterClass(unsigned RegNo, bool Data, bool Address,
-                                      bool SP, bool FPDR = false) {
+                                      bool SP, bool FPDR = false,
+                                      bool FPCR = false) {
   switch (RegNo) {
   case M68k::A0:
   case M68k::A1:
@@ -526,6 +532,11 @@ static inline bool checkRegisterClass(unsigned RegNo, bool Data, bool Address,
   case M68k::FP7:
     return FPDR;
 
+  case M68k::FPC:
+  case M68k::FPS:
+  case M68k::FPIAR:
+    return FPCR;
+
   default:
     llvm_unreachable("unexpected register type");
     return false;
@@ -551,6 +562,13 @@ bool M68kOperand::isFPDReg() const {
                                        /*FPDR=*/true);
 }
 
+bool M68kOperand::isFPCReg() const {
+  return isReg() && checkRegisterClass(getReg(),
+                                       /*Data=*/false,
+                                       /*Address=*/false, /*SP=*/false,
+                                       /*FPDR=*/false, /*FPCR=*/true);
+}
+
 unsigned M68kAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
                                                    unsigned Kind) {
   M68kOperand &Operand = (M68kOperand &)Op;
@@ -660,12 +678,22 @@ bool M68kAsmParser::parseRegisterName(MCRegister &RegNo, SMLoc Loc,
     }
   } else if (StringRef(RegisterNameLower).starts_with("fp") &&
              RegisterNameLower.size() > 2) {
-    // Floating point data register.
     auto RegIndex = unsigned(RegisterNameLower[2] - '0');
-    if (RegIndex >= 8 || RegisterNameLower.size() > 3)
-      return false;
-    RegNo = getRegisterByIndex(16 + RegIndex);
-    return true;
+    if (RegIndex < 8 && RegisterNameLower.size() == 3) {
+      // Floating point data register.
+      RegNo = getRegisterByIndex(16 + RegIndex);
+      return true;
+    } else {
+      // Floating point control register.
+      RegNo = StringSwitch<unsigned>(RegisterNameLower)
+                  .Cases("fpc", "fpcr", M68k::FPC)
+                  .Cases("fps", "fpsr", M68k::FPS)
+                  .Cases("fpi", "fpiar", M68k::FPIAR)
+                  .Default(M68k::NoRegister);
+      assert(RegNo != M68k::NoRegister &&
+             "Unrecognized FP control register name");
+      return true;
+    }
   }
 
   return false;
diff --git a/llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp b/llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp
index 2124a35cc65a..7f0f737faccd 100644
--- a/llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp
+++ b/llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp
@@ -33,10 +33,11 @@ using namespace llvm;
 typedef MCDisassembler::DecodeStatus DecodeStatus;
 
 static const unsigned RegisterDecode[] = {
-    M68k::D0,  M68k::D1,  M68k::D2,  M68k::D3,  M68k::D4,  M68k::D5,
-    M68k::D6,  M68k::D7,  M68k::A0,  M68k::A1,  M68k::A2,  M68k::A3,
-    M68k::A4,  M68k::A5,  M68k::A6,  M68k::SP,  M68k::FP0, M68k::FP1,
-    M68k::FP2, M68k::FP3, M68k::FP4, M68k::FP5, M68k::FP6, M68k::FP7};
+    M68k::D0,    M68k::D1,  M68k::D2,  M68k::D3,  M68k::D4,  M68k::D5,
+    M68k::D6,    M68k::D7,  M68k::A0,  M68k::A1,  M68k::A2,  M68k::A3,
+    M68k::A4,    M68k::A5,  M68k::A6,  M68k::SP,  M68k::FP0, M68k::FP1,
+    M68k::FP2,   M68k::FP3, M68k::FP4, M68k::FP5, M68k::FP6, M68k::FP7,
+    M68k::FPIAR, M68k::FPS, M68k::FPC};
 
 static DecodeStatus DecodeRegisterClass(MCInst &Inst, uint64_t RegNo,
                                         uint64_t Address, const void *Decoder) {
@@ -97,6 +98,13 @@ static DecodeStatus DecodeFPDRRegisterClass(MCInst &Inst, uint64_t RegNo,
 #define DecodeFPDR64RegisterClass DecodeFPDRRegisterClass
 #define DecodeFPDR80RegisterClass DecodeFPDRRegisterClass
 
+static DecodeStatus DecodeFPCSCRegisterClass(MCInst &Inst, uint64_t RegNo,
+                                             uint64_t Address,
+                                             const void *Decoder) {
+  return DecodeRegisterClass(Inst, (RegNo >> 1) + 24, Address, Decoder);
+}
+#define DecodeFPICRegisterClass DecodeFPCSCRegisterClass
+
 static DecodeStatus DecodeCCRCRegisterClass(MCInst &Inst, APInt &Insn,
                                             uint64_t Address,
                                             const void *Decoder) {
@@ -114,6 +122,7 @@ static DecodeStatus DecodeImm32(MCInst &Inst, uint64_t Imm, uint64_t Address,
 #undef DecodeFPDR32RegisterClass
 #undef DecodeFPDR64RegisterClass
 #undef DecodeFPDR80RegisterClass
+#undef DecodeFPICRegisterClass
 
 /// A disassembler class for M68k.
 struct M68kDisassembler : public MCDisassembler {
diff --git a/llvm/lib/Target/M68k/M68kInstrData.td b/llvm/lib/Target/M68k/M68kInstrData.td
index e6d4471f7aab..624093661d19 100644
--- a/llvm/lib/Target/M68k/M68kInstrData.td
+++ b/llvm/lib/Target/M68k/M68kInstrData.td
@@ -672,3 +672,49 @@ foreach rounding = ["", "s", "d"] in {
   foreach size = [32, 64] in
     def F # !toupper(rounding) # MOV # size # fp_fp : MxFMove_FF<rounding, size>;
 }
+// Direction
+defvar MxFMove_FP_EA = false;
+defvar MxFMove_EA_FP = true;
+
+// Encoding scheme for FPSYS <-> R/M
+class MxEncFSysMove<bit dir, MxEncMemOp EAEnc, string fsys_reg> {
+  dag Value = (ascend
+    (descend 0b1111,
+      /*COPROCESSOR ID*/0b001,
+      0b000,
+      /*MODE + REGISTER*/
+      EAEnc.EA
+    ),
+    (descend 0b10, /*dir*/ dir,
+      /*REGISTER SELECT*/
+      (operand "$"#fsys_reg, 3, (encoder "encodeFPSYSSelect")),
+      0b0000000000
+    )
+  );
+}
+
+// FPSYS <-> R
+class MxFMove_FSYS_R<string src_reg,
+                     MxOpBundle SrcOpnd = !cast<MxOpBundle>("MxOp32AddrMode_"#src_reg),
+                     MxOpBundle DstOpnd = !cond(!eq(src_reg, "d"): MxOp32AddrMode_fpcs,
+                                                !eq(src_reg, "a"): MxOp32AddrMode_fpi),
+                     MxEncMemOp SrcEnc = !cast<MxEncMemOp>("MxMoveSrcOpEnc_"#src_reg)>
+    : MxFMove<"l", (outs DstOpnd.Op:$dst), (ins SrcOpnd.Op:$src),
+              [(null_frag)]> {
+  let Inst = MxEncFSysMove<MxFMove_FP_EA, SrcEnc, "dst">.Value;
+}
+
+class MxFMove_R_FSYS<string dst_reg,
+                     MxOpBundle SrcOpnd = !cond(!eq(dst_reg, "d"): MxOp32AddrMode_fpcs,
+                                                !eq(dst_reg, "a"): MxOp32AddrMode_fpi),
+                     MxOpBundle DstOpnd = !cast<MxOpBundle>("MxOp32AddrMode_"#dst_reg),
+                     MxEncMemOp DstEnc = !cast<MxEncMemOp>("MxMoveDstOpEnc_"#dst_reg)>
+    : MxFMove<"l", (outs DstOpnd.Op:$dst), (ins SrcOpnd.Op:$src),
+              [(null_frag)]> {
+  let Inst = MxEncFSysMove<MxFMove_EA_FP, DstEnc, "src">.Value;
+}
+
+def FMOVE32fpcs_d : MxFMove_FSYS_R<"d">;
+def FMOVE32d_fpcs : MxFMove_R_FSYS<"d">;
+def FMOVE32fpi_a  : MxFMove_FSYS_R<"a">;
+def FMOVE32a_fpi  : MxFMove_R_FSYS<"a">;
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.td b/llvm/lib/Target/M68k/M68kInstrInfo.td
index 6d3370d5ee90..dc66e103361a 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.td
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.td
@@ -186,6 +186,7 @@ let RenderMethod = "addRegOperands", SuperClasses = [MxRegClass]in {
   def MxDRegClass : MxOpClass<"DReg">;
 
   def MxFPDRegClass : MxOpClass<"FPDReg">;
+  def MxFPCRegClass : MxOpClass<"FPCReg">;
 }
 
 class MxOperand<ValueType vt, MxSize size, string letter, RegisterClass rc, dag pat = (null_frag)> {
@@ -242,6 +243,12 @@ let ParserMatchClass = MxFPDRegClass in {
   def MxFPR80 : MxRegOp<f80, FPDR80, MxSizeF80, "fp">;
 }
 
+// FLOATING POINT SYSTEM CONTROL REGISTER
+let ParserMatchClass = MxFPCRegClass in {
+  def MxFPCSR : MxRegOp<i32, FPCSC, MxSize32, "fpcs">;
+  def MxFPIR  : MxRegOp<i32, FPIC,  MxSize32, "fpi">;
+}
+
 class MxMemOp<dag ops, MxSize size, string letter,
               string printMethod = "printOperand",
               AsmOperandClass parserMatchClass = ImmAsmOperand>
@@ -727,6 +734,9 @@ foreach size = [32, 64, 80] in
 def MxOp#size#AddrMode_fpr
   : MxOpBundle<size, !cast<MxOperand>("MxFPR"#size), ?>;
 
+def MxOp32AddrMode_fpcs : MxOpBundle<32, MxFPCSR, ?>;
+def MxOp32AddrMode_fpi  : MxOpBundle<32, MxFPIR, ?>;
+
 class MxType8Class<string rLet, MxOperand reg>
     : MxType<i8, "b", "", rLet, reg,
              MxARI8,   MxCP_ARI,
diff --git a/llvm/lib/Target/M68k/M68kRegisterInfo.td b/llvm/lib/Target/M68k/M68kRegisterInfo.td
index 1567bcbb7319..45b492eba4ec 100644
--- a/llvm/lib/Target/M68k/M68kRegisterInfo.td
+++ b/llvm/lib/Target/M68k/M68kRegisterInfo.td
@@ -125,7 +125,10 @@ let CopyCost = -1 in {
   def CCRC : MxRegClass<[i8],  16, (add CCR)>;
   def SRC  : MxRegClass<[i16], 16, (add SR)>;
 
-  def FPCR : MxRegClass<[i32], 32, (add FPC, FPS, FPIAR)>;
+  // Float Point System Control Registers
+  def FPIC   : MxRegClass<[i32], 32, (add FPIAR)>;
+  def FPCSC  : MxRegClass<[i32], 32, (add FPC, FPS)>;
+  def FPSYSC : MxRegClass<[i32], 32, (add FPCSC, FPIC)>;
 }
 
 let isAllocatable = 0 in {
diff --git a/llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp b/llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp
index a9ff059bc990..e6bc3af6e191 100644
--- a/llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp
+++ b/llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp
@@ -59,6 +59,10 @@ class M68kMCCodeEmitter : public MCCodeEmitter {
                       APInt &Value, SmallVectorImpl<MCFixup> &Fixups,
                       const MCSubtargetInfo &STI) const;
 
+  void encodeFPSYSSelect(const MCInst &MI, unsigned OpIdx, unsigned InsertPos,
+                         APInt &Value, SmallVectorImpl<MCFixup> &Fixups,
+                         const MCSubtargetInfo &STI) const;
+
 public:
   M68kMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
       : MCII(mcii), Ctx(ctx) {}
@@ -172,6 +176,26 @@ void M68kMCCodeEmitter::encodePCRelImm(const MCInst &MI, unsigned OpIdx,
   }
 }
 
+void M68kMCCodeEmitter::encodeFPSYSSelect(const MCInst &MI, unsigned OpIdx,
+                                          unsigned InsertPos, APInt &Value,
+                                          SmallVectorImpl<MCFixup> &Fixups,
+                                          const MCSubtargetInfo &STI) const {
+  MCRegister FPSysReg = MI.getOperand(OpIdx).getReg();
+  switch (FPSysReg) {
+  case M68k::FPC:
+    Value = 0b100;
+    break;
+  case M68k::FPS:
+    Value = 0b010;
+    break;
+  case M68k::FPIAR:
+    Value = 0b001;
+    break;
+  default:
+    llvm_unreachable("Unrecognized FPSYS register");
+  }
+}
+
 void M68kMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &Op,
                                           unsigned InsertPos, APInt &Value,
                                           SmallVectorImpl<MCFixup> &Fixups,
diff --git a/llvm/test/MC/M68k/Data/Classes/MxFMove_FSYS.s b/llvm/test/MC/M68k/Data/Classes/MxFMove_FSYS.s
new file mode 100644
index 000000000000..a02ce97e28c2
--- /dev/null
+++ b/llvm/test/MC/M68k/Data/Classes/MxFMove_FSYS.s
@@ -0,0 +1,17 @@
+; RUN: llvm-mc -triple=m68k -mcpu=M68040 -show-encoding < %s | FileCheck %s
+
+; CHECK: fmove.l %d0, %fpcr
+; CHECK-SAME: [0xf2,0x00,0x90,0x00]
+fmove.l %d0, %fpc
+
+; CHECK: fmove.l %fpsr, %d2
+; CHECK-SAME: [0xf2,0x02,0xa8,0x00]
+fmove.l %fps, %d2
+
+; CHECK: fmove.l %fpiar, %a3
+; CHECK-SAME: [0xf2,0x0b,0xa4,0x00]
+fmove.l %fpiar, %a3
+
+; CHECK: fmove.l %a1, %fpiar
+; CHECK-SAME: [0xf2,0x09,0x84,0x00]
+fmove.l %a1, %fpi
-- 
GitLab


From 1c830b787c0d8ccc863d23fa507182dc7685fcc2 Mon Sep 17 00:00:00 2001
From: Fangrui Song <i@maskray.me>
Date: Mon, 11 Dec 2023 23:09:14 -0800
Subject: [PATCH 229/349] [Preprocessor] Define
 __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 for AArch64 (#74954)

GCC sets `#define HAVE_atomic_compare_and_swapti 1` and therefore
defines `__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16`.

Clang compiles the 16-byte legacy `__sync_bool_compare_and_swap` and new
`__atomic_compare_exchange` compile to LDXP/STXP or (with LSE)
CASP{,A,L,AL}.

Link: https://github.com/llvm/llvm-project/issues/71883
---
 clang/lib/Basic/Targets/AArch64.cpp    | 3 ++-
 clang/test/Preprocessor/init-aarch64.c | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp
index c31f2e0bee54..e3e08b571667 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -574,11 +574,12 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
   else if (*ArchInfo == llvm::AArch64::ARMV9_5A)
     getTargetDefinesARMV95A(Opts, Builder);
 
-  // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
+  // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8|16) builtins work.
   Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
   Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
   Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
   Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
+  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
 
   // Allow detection of fast FMA support.
   Builder.defineMacro("__FP_FAST_FMA", "1");
diff --git a/clang/test/Preprocessor/init-aarch64.c b/clang/test/Preprocessor/init-aarch64.c
index b0333b3f0238..94c091a69e84 100644
--- a/clang/test/Preprocessor/init-aarch64.c
+++ b/clang/test/Preprocessor/init-aarch64.c
@@ -118,6 +118,7 @@
 // AARCH64-NEXT: #define __FP_FAST_FMAF 1
 // AARCH64-NEXT: #define __GCC_ASM_FLAG_OUTPUTS__ 1
 // AARCH64-NEXT: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
+// AARCH64-NEXT: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 1
 // AARCH64-NEXT: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
 // AARCH64-NEXT: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
 // AARCH64-NEXT: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
-- 
GitLab


From 5830e8e7458f3605f67a33439592432cc599ea40 Mon Sep 17 00:00:00 2001
From: Aiden Grossman <agrossman154@yahoo.com>
Date: Mon, 11 Dec 2023 23:15:56 -0800
Subject: [PATCH 230/349] [llvm-exegesis] Use explicit error classes for
 different snippet crashes (#74210)

This patch switches to using explicit snippet crashes that contain more
information about the specific type of error (like the address for a
segmentation fault) that occurred. All these new error classes inherit
from SnippetExecutionFailure to allow for easily grabbing all of them in
addition to filtering for specific types using the standard LLVM error
primitives.
---
 .../latency/subprocess-abnormal-exit-code.s   |  4 +-
 .../X86/latency/subprocess-segfault.s         |  4 +-
 .../llvm-exegesis/lib/BenchmarkRunner.cpp     | 23 ++++++------
 llvm/tools/llvm-exegesis/lib/Error.cpp        | 26 +++++++++++--
 llvm/tools/llvm-exegesis/lib/Error.h          | 37 ++++++++++++++++---
 llvm/tools/llvm-exegesis/llvm-exegesis.cpp    |  2 +-
 6 files changed, 70 insertions(+), 26 deletions(-)

diff --git a/llvm/test/tools/llvm-exegesis/X86/latency/subprocess-abnormal-exit-code.s b/llvm/test/tools/llvm-exegesis/X86/latency/subprocess-abnormal-exit-code.s
index 849f1a2e552f..1edb263455f9 100644
--- a/llvm/test/tools/llvm-exegesis/X86/latency/subprocess-abnormal-exit-code.s
+++ b/llvm/test/tools/llvm-exegesis/X86/latency/subprocess-abnormal-exit-code.s
@@ -1,8 +1,8 @@
 # REQUIRES: exegesis-can-measure-latency, x86_64-linux
 
-# RUN: llvm-exegesis -mtriple=x86_64-unknown-unknown -mode=latency -snippets-file=%s -execution-mode=subprocess | FileCheck %s
+# RUN: not llvm-exegesis -mtriple=x86_64-unknown-unknown -mode=latency -snippets-file=%s -execution-mode=subprocess 2>&1 | FileCheck %s
 
-# CHECK: error: 'Child benchmarking process exited with non-zero exit code: Child process returned with unknown exit code'
+# CHECK: llvm-exegesis error: Child benchmarking process exited with non-zero exit code: Child process returned with unknown exit code
 
 movl $60, %eax
 movl $127, %edi
diff --git a/llvm/test/tools/llvm-exegesis/X86/latency/subprocess-segfault.s b/llvm/test/tools/llvm-exegesis/X86/latency/subprocess-segfault.s
index 92b08e1c18c6..c72ac287d717 100644
--- a/llvm/test/tools/llvm-exegesis/X86/latency/subprocess-segfault.s
+++ b/llvm/test/tools/llvm-exegesis/X86/latency/subprocess-segfault.s
@@ -2,7 +2,7 @@
 
 # RUN: llvm-exegesis -mtriple=x86_64-unknown-unknown -mode=latency -snippets-file=%s -execution-mode=subprocess | FileCheck %s
 
-# CHECK: error:           'The benchmarking subprocess sent unexpected signal: Segmentation fault'
+# CHECK: error: The snippet encountered a segmentation fault at address 10
 
-# LLVM-EXEGESIS-DEFREG RBX 0
+# LLVM-EXEGESIS-DEFREG RBX 10
 movq (%rbx), %rax
diff --git a/llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp b/llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp
index 6c34446e8d66..2d396df7337f 100644
--- a/llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp
+++ b/llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp
@@ -147,17 +147,16 @@ private:
       CrashRecoveryContext::Disable();
       PS.reset();
       if (Crashed) {
-        std::string Msg = "snippet crashed while running";
 #ifdef LLVM_ON_UNIX
         // See "Exit Status for Commands":
         // https://pubs.opengroup.org/onlinepubs/9699919799/xrat/V4_xcu_chap02.html
         constexpr const int kSigOffset = 128;
-        if (const char *const SigName = strsignal(CRC.RetCode - kSigOffset)) {
-          Msg += ": ";
-          Msg += SigName;
-        }
-#endif
-        return make_error<SnippetCrash>(std::move(Msg));
+        return make_error<SnippetSignal>(CRC.RetCode - kSigOffset);
+#else
+        // The exit code of the process on windows is not meaningful as a
+        // signal, so simply pass in -1 as the signal into the error.
+        return make_error<SnippetSignal>(-1);
+#endif // LLVM_ON_UNIX
       }
     }
 
@@ -366,7 +365,7 @@ private:
         return Error::success();
       }
       // The child exited, but not successfully
-      return make_error<SnippetCrash>(
+      return make_error<Failure>(
           "Child benchmarking process exited with non-zero exit code: " +
           childProcessExitCodeToString(ChildExitCode));
     }
@@ -379,9 +378,11 @@ private:
                                  Twine(strerror(errno)));
     }
 
-    return make_error<SnippetCrash>(
-        "The benchmarking subprocess sent unexpected signal: " +
-        Twine(strsignal(ChildSignalInfo.si_signo)));
+    if (ChildSignalInfo.si_signo == SIGSEGV)
+      return make_error<SnippetSegmentationFault>(
+          reinterpret_cast<intptr_t>(ChildSignalInfo.si_addr));
+
+    return make_error<SnippetSignal>(ChildSignalInfo.si_signo);
   }
 
   void disableCoreDumps() const {
diff --git a/llvm/tools/llvm-exegesis/lib/Error.cpp b/llvm/tools/llvm-exegesis/lib/Error.cpp
index 51ce41bf00bf..d29c41385670 100644
--- a/llvm/tools/llvm-exegesis/lib/Error.cpp
+++ b/llvm/tools/llvm-exegesis/lib/Error.cpp
@@ -8,6 +8,10 @@
 
 #include "Error.h"
 
+#ifdef LLVM_ON_UNIX
+#include <string.h>
+#endif // LLVM_ON_UNIX
+
 namespace llvm {
 namespace exegesis {
 
@@ -19,13 +23,27 @@ std::error_code ClusteringError::convertToErrorCode() const {
   return inconvertibleErrorCode();
 }
 
-char SnippetCrash::ID;
-
-void SnippetCrash::log(raw_ostream &OS) const { OS << Msg; }
+char SnippetExecutionFailure::ID;
 
-std::error_code SnippetCrash::convertToErrorCode() const {
+std::error_code SnippetExecutionFailure::convertToErrorCode() const {
   return inconvertibleErrorCode();
 }
 
+char SnippetSegmentationFault::ID;
+
+void SnippetSegmentationFault::log(raw_ostream &OS) const {
+  OS << "The snippet encountered a segmentation fault at address "
+     << Twine::utohexstr(Address);
+}
+
+char SnippetSignal::ID;
+
+void SnippetSignal::log(raw_ostream &OS) const {
+  OS << "snippet crashed while running";
+#ifdef LLVM_ON_UNIX
+  OS << ": " << strsignal(SignalNumber);
+#endif // LLVM_ON_UNIX
+}
+
 } // namespace exegesis
 } // namespace llvm
diff --git a/llvm/tools/llvm-exegesis/lib/Error.h b/llvm/tools/llvm-exegesis/lib/Error.h
index e5fa093e6e12..2587c45f5574 100644
--- a/llvm/tools/llvm-exegesis/lib/Error.h
+++ b/llvm/tools/llvm-exegesis/lib/Error.h
@@ -36,19 +36,44 @@ private:
   std::string Msg;
 };
 
-// A class representing failures that happened during snippet execution.
-// Instead of terminating the program crashes are logged into the output.
-class SnippetCrash : public ErrorInfo<SnippetCrash> {
+// A class representing a non-descript snippet execution failure. This class
+// is designed to sub-classed into more specific failures that contain
+// additional data about the specific error that they represent. Instead of
+// halting the program, the errors are reported in the output.
+class SnippetExecutionFailure : public ErrorInfo<SnippetExecutionFailure> {
 public:
   static char ID;
-  SnippetCrash(const Twine &S) : Msg(S.str()) {}
+
+  std::error_code convertToErrorCode() const override;
+};
+
+// A class representing specifically segmentation faults that happen during
+// snippet execution.
+class SnippetSegmentationFault : public SnippetExecutionFailure {
+public:
+  static char ID;
+  SnippetSegmentationFault(intptr_t SegFaultAddress)
+      : Address(SegFaultAddress){};
+
+  intptr_t getAddress() { return Address; }
 
   void log(raw_ostream &OS) const override;
 
-  std::error_code convertToErrorCode() const override;
+private:
+  intptr_t Address;
+};
+
+// A class representing all other non-specific failures that happen during
+// snippet execution.
+class SnippetSignal : public SnippetExecutionFailure {
+public:
+  static char ID;
+  SnippetSignal(int Signal) : SignalNumber(Signal){};
+
+  void log(raw_ostream &OS) const override;
 
 private:
-  std::string Msg;
+  int SignalNumber;
 };
 
 } // namespace exegesis
diff --git a/llvm/tools/llvm-exegesis/llvm-exegesis.cpp b/llvm/tools/llvm-exegesis/llvm-exegesis.cpp
index 148891a18246..a5f8a09dcb24 100644
--- a/llvm/tools/llvm-exegesis/llvm-exegesis.cpp
+++ b/llvm/tools/llvm-exegesis/llvm-exegesis.cpp
@@ -415,7 +415,7 @@ static void runBenchmarkConfigurations(
       if (Err) {
         // Errors from executing the snippets are fine.
         // All other errors are a framework issue and should fail.
-        if (!Err.isA<SnippetCrash>()) {
+        if (!Err.isA<SnippetExecutionFailure>()) {
           llvm::errs() << "llvm-exegesis error: " << toString(std::move(Err));
           exit(1);
         }
-- 
GitLab


From 8a5b448fa04dc0a9b82321351e3d9a44cf00dab0 Mon Sep 17 00:00:00 2001
From: Adrian Kuegel <akuegel@google.com>
Date: Tue, 12 Dec 2023 07:34:03 +0000
Subject: [PATCH 231/349] [mlir][GPU] Apply ClangTidy fixes

Use const reference in loops if possible.
---
 mlir/lib/Dialect/GPU/Transforms/SPIRVAttachTarget.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/mlir/lib/Dialect/GPU/Transforms/SPIRVAttachTarget.cpp b/mlir/lib/Dialect/GPU/Transforms/SPIRVAttachTarget.cpp
index a099a44f3dc6..88c365d9ce3e 100644
--- a/mlir/lib/Dialect/GPU/Transforms/SPIRVAttachTarget.cpp
+++ b/mlir/lib/Dialect/GPU/Transforms/SPIRVAttachTarget.cpp
@@ -64,13 +64,13 @@ void SPIRVAttachTarget::runOnOperation() {
   Version version = versionSymbol.value();
   SmallVector<Capability, 4> capabilities;
   SmallVector<Extension, 8> extensions;
-  for (auto cap : spirvCapabilities) {
+  for (const auto &cap : spirvCapabilities) {
     auto capSymbol = symbolizeCapability(cap);
     if (capSymbol)
       capabilities.push_back(capSymbol.value());
   }
   ArrayRef<Capability> caps(capabilities);
-  for (auto ext : spirvExtensions) {
+  for (const auto &ext : spirvExtensions) {
     auto extSymbol = symbolizeExtension(ext);
     if (extSymbol)
       extensions.push_back(extSymbol.value());
-- 
GitLab


From b0cc42ae0f85a899a970f66ec182985e4bd316cf Mon Sep 17 00:00:00 2001
From: paperchalice <liujunchang97@outlook.com>
Date: Tue, 12 Dec 2023 16:07:26 +0800
Subject: [PATCH 232/349] [CodeGen] Port `SjLjEHPrepare` to new pass manager
 (#75023)

`doInitialization` in `SjLjEHPrepare` is trivial.

This is the last pass suffix with `ehprepare`.
---
 .../include/llvm/CodeGen/CodeGenPassBuilder.h |  3 +-
 .../llvm/CodeGen/MachinePassRegistry.def      |  2 +-
 llvm/include/llvm/CodeGen/SjLjEHPrepare.h     | 28 ++++++++
 llvm/lib/CodeGen/SjLjEHPrepare.cpp            | 67 ++++++++++++-------
 llvm/lib/Passes/PassBuilder.cpp               |  1 +
 llvm/lib/Passes/PassRegistry.def              |  1 +
 llvm/test/CodeGen/ARM/sjljeh-swifterror.ll    |  3 +-
 llvm/tools/opt/opt.cpp                        |  3 +-
 8 files changed, 79 insertions(+), 29 deletions(-)
 create mode 100644 llvm/include/llvm/CodeGen/SjLjEHPrepare.h

diff --git a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
index 4f4f00b4e0e0..92bfef2b0148 100644
--- a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
@@ -33,6 +33,7 @@
 #include "llvm/CodeGen/ReplaceWithVeclib.h"
 #include "llvm/CodeGen/SafeStack.h"
 #include "llvm/CodeGen/SelectOptimize.h"
+#include "llvm/CodeGen/SjLjEHPrepare.h"
 #include "llvm/CodeGen/UnreachableBlockElim.h"
 #include "llvm/CodeGen/WasmEHPrepare.h"
 #include "llvm/CodeGen/WinEHPrepare.h"
@@ -679,7 +680,7 @@ void CodeGenPassBuilder<Derived>::addPassesToHandleExceptions(
     // removed from the parent invoke(s). This could happen when a landing
     // pad is shared by multiple invokes and is also a target of a normal
     // edge from elsewhere.
-    addPass(SjLjEHPreparePass());
+    addPass(SjLjEHPreparePass(&TM));
     [[fallthrough]];
   case ExceptionHandling::DwarfCFI:
   case ExceptionHandling::ARM:
diff --git a/llvm/include/llvm/CodeGen/MachinePassRegistry.def b/llvm/include/llvm/CodeGen/MachinePassRegistry.def
index b98daa485cf8..9ebf33b2b9a5 100644
--- a/llvm/include/llvm/CodeGen/MachinePassRegistry.def
+++ b/llvm/include/llvm/CodeGen/MachinePassRegistry.def
@@ -55,6 +55,7 @@ FUNCTION_PASS("replace-with-veclib", ReplaceWithVeclib, ())
 FUNCTION_PASS("safe-stack", SafeStackPass, (TM))
 FUNCTION_PASS("scalarize-masked-mem-intrin", ScalarizeMaskedMemIntrinPass, ())
 FUNCTION_PASS("select-optimize", SelectOptimizePass, (TM))
+FUNCTION_PASS("sjlj-eh-prepare", SjLjEHPreparePass, (TM))
 FUNCTION_PASS("tlshoist", TLSVariableHoistPass, ())
 FUNCTION_PASS("unreachableblockelim", UnreachableBlockElimPass, ())
 FUNCTION_PASS("verify", VerifierPass, ())
@@ -130,7 +131,6 @@ DUMMY_FUNCTION_PASS("expandmemcmp", ExpandMemCmpPass, ())
 DUMMY_FUNCTION_PASS("gc-lowering", GCLoweringPass, ())
 DUMMY_FUNCTION_PASS("indirectbr-expand", IndirectBrExpandPass, ())
 DUMMY_FUNCTION_PASS("shadow-stack-gc-lowering", ShadowStackGCLoweringPass, ())
-DUMMY_FUNCTION_PASS("sjljehprepare", SjLjEHPreparePass, ())
 DUMMY_FUNCTION_PASS("stack-protector", StackProtectorPass, ())
 #undef DUMMY_FUNCTION_PASS
 
diff --git a/llvm/include/llvm/CodeGen/SjLjEHPrepare.h b/llvm/include/llvm/CodeGen/SjLjEHPrepare.h
new file mode 100644
index 000000000000..c1fd680ff8af
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/SjLjEHPrepare.h
@@ -0,0 +1,28 @@
+//===-- llvm/CodeGen/SjLjEHPrepare.h -------------------------- -*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_SJLJEHPREPARE_H
+#define LLVM_CODEGEN_SJLJEHPREPARE_H
+
+#include "llvm/IR/PassManager.h"
+
+namespace llvm {
+
+class TargetMachine;
+
+class SjLjEHPreparePass : public PassInfoMixin<SjLjEHPreparePass> {
+  const TargetMachine *TM;
+
+public:
+  explicit SjLjEHPreparePass(const TargetMachine *TM) : TM(TM) {}
+  PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM);
+};
+
+} // namespace llvm
+
+#endif // LLVM_CODEGEN_SJLJEHPREPARE_H
diff --git a/llvm/lib/CodeGen/SjLjEHPrepare.cpp b/llvm/lib/CodeGen/SjLjEHPrepare.cpp
index f98c096ccf08..515b5764a094 100644
--- a/llvm/lib/CodeGen/SjLjEHPrepare.cpp
+++ b/llvm/lib/CodeGen/SjLjEHPrepare.cpp
@@ -11,6 +11,7 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "llvm/CodeGen/SjLjEHPrepare.h"
 #include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/SmallVector.h"
@@ -31,13 +32,13 @@
 #include "llvm/Transforms/Utils/Local.h"
 using namespace llvm;
 
-#define DEBUG_TYPE "sjljehprepare"
+#define DEBUG_TYPE "sjlj-eh-prepare"
 
 STATISTIC(NumInvokes, "Number of invokes replaced");
 STATISTIC(NumSpilled, "Number of registers live across unwind edges");
 
 namespace {
-class SjLjEHPrepare : public FunctionPass {
+class SjLjEHPrepareImpl {
   IntegerType *DataTy = nullptr;
   Type *doubleUnderDataTy = nullptr;
   Type *doubleUnderJBufTy = nullptr;
@@ -55,16 +56,9 @@ class SjLjEHPrepare : public FunctionPass {
   const TargetMachine *TM = nullptr;
 
 public:
-  static char ID; // Pass identification, replacement for typeid
-  explicit SjLjEHPrepare(const TargetMachine *TM = nullptr)
-      : FunctionPass(ID), TM(TM) {}
-  bool doInitialization(Module &M) override;
-  bool runOnFunction(Function &F) override;
-
-  void getAnalysisUsage(AnalysisUsage &AU) const override {}
-  StringRef getPassName() const override {
-    return "SJLJ Exception Handling preparation";
-  }
+  explicit SjLjEHPrepareImpl(const TargetMachine *TM = nullptr) : TM(TM) {}
+  bool doInitialization(Module &M);
+  bool runOnFunction(Function &F);
 
 private:
   bool setupEntryBlockAndCallSites(Function &F);
@@ -74,8 +68,32 @@ private:
   void lowerAcrossUnwindEdges(Function &F, ArrayRef<InvokeInst *> Invokes);
   void insertCallSiteStore(Instruction *I, int Number);
 };
+
+class SjLjEHPrepare : public FunctionPass {
+  SjLjEHPrepareImpl Impl;
+
+public:
+  static char ID; // Pass identification, replacement for typeid
+  explicit SjLjEHPrepare(const TargetMachine *TM = nullptr)
+      : FunctionPass(ID), Impl(TM) {}
+  bool doInitialization(Module &M) override { return Impl.doInitialization(M); }
+  bool runOnFunction(Function &F) override { return Impl.runOnFunction(F); };
+
+  StringRef getPassName() const override {
+    return "SJLJ Exception Handling preparation";
+  }
+};
+
 } // end anonymous namespace
 
+PreservedAnalyses SjLjEHPreparePass::run(Function &F,
+                                         FunctionAnalysisManager &FAM) {
+  SjLjEHPrepareImpl Impl(TM);
+  Impl.doInitialization(*F.getParent());
+  bool Changed = Impl.runOnFunction(F);
+  return Changed ? PreservedAnalyses::none() : PreservedAnalyses::all();
+}
+
 char SjLjEHPrepare::ID = 0;
 INITIALIZE_PASS(SjLjEHPrepare, DEBUG_TYPE, "Prepare SjLj exceptions",
                 false, false)
@@ -87,7 +105,7 @@ FunctionPass *llvm::createSjLjEHPreparePass(const TargetMachine *TM) {
 
 // doInitialization - Set up decalarations and types needed to process
 // exceptions.
-bool SjLjEHPrepare::doInitialization(Module &M) {
+bool SjLjEHPrepareImpl::doInitialization(Module &M) {
   // Build the function context structure.
   // builtin_setjmp uses a five word jbuf
   Type *VoidPtrTy = PointerType::getUnqual(M.getContext());
@@ -104,12 +122,12 @@ bool SjLjEHPrepare::doInitialization(Module &M) {
                                       doubleUnderJBufTy  // __jbuf
   );
 
-  return true;
+  return false;
 }
 
 /// insertCallSiteStore - Insert a store of the call-site value to the
 /// function context
-void SjLjEHPrepare::insertCallSiteStore(Instruction *I, int Number) {
+void SjLjEHPrepareImpl::insertCallSiteStore(Instruction *I, int Number) {
   IRBuilder<> Builder(I);
 
   // Get a reference to the call_site field.
@@ -140,8 +158,8 @@ static void MarkBlocksLiveIn(BasicBlock *BB,
 
 /// substituteLPadValues - Substitute the values returned by the landingpad
 /// instruction with those returned by the personality function.
-void SjLjEHPrepare::substituteLPadValues(LandingPadInst *LPI, Value *ExnVal,
-                                         Value *SelVal) {
+void SjLjEHPrepareImpl::substituteLPadValues(LandingPadInst *LPI, Value *ExnVal,
+                                             Value *SelVal) {
   SmallVector<Value *, 8> UseWorkList(LPI->users());
   while (!UseWorkList.empty()) {
     Value *Val = UseWorkList.pop_back_val();
@@ -175,8 +193,9 @@ void SjLjEHPrepare::substituteLPadValues(LandingPadInst *LPI, Value *ExnVal,
 
 /// setupFunctionContext - Allocate the function context on the stack and fill
 /// it with all of the data that we know at this point.
-Value *SjLjEHPrepare::setupFunctionContext(Function &F,
-                                           ArrayRef<LandingPadInst *> LPads) {
+Value *
+SjLjEHPrepareImpl::setupFunctionContext(Function &F,
+                                        ArrayRef<LandingPadInst *> LPads) {
   BasicBlock *EntryBB = &F.front();
 
   // Create an alloca for the incoming jump buffer ptr and the new jump buffer
@@ -233,7 +252,7 @@ Value *SjLjEHPrepare::setupFunctionContext(Function &F,
 /// specially, we lower each arg to a copy instruction in the entry block. This
 /// ensures that the argument value itself cannot be live out of the entry
 /// block.
-void SjLjEHPrepare::lowerIncomingArguments(Function &F) {
+void SjLjEHPrepareImpl::lowerIncomingArguments(Function &F) {
   BasicBlock::iterator AfterAllocaInsPt = F.begin()->begin();
   while (isa<AllocaInst>(AfterAllocaInsPt) &&
          cast<AllocaInst>(AfterAllocaInsPt)->isStaticAlloca())
@@ -264,8 +283,8 @@ void SjLjEHPrepare::lowerIncomingArguments(Function &F) {
 
 /// lowerAcrossUnwindEdges - Find all variables which are alive across an unwind
 /// edge and spill them.
-void SjLjEHPrepare::lowerAcrossUnwindEdges(Function &F,
-                                           ArrayRef<InvokeInst *> Invokes) {
+void SjLjEHPrepareImpl::lowerAcrossUnwindEdges(Function &F,
+                                               ArrayRef<InvokeInst *> Invokes) {
   // Finally, scan the code looking for instructions with bad live ranges.
   for (BasicBlock &BB : F) {
     for (Instruction &Inst : BB) {
@@ -358,7 +377,7 @@ void SjLjEHPrepare::lowerAcrossUnwindEdges(Function &F,
 /// setupEntryBlockAndCallSites - Setup the entry block by creating and filling
 /// the function context and marking the call sites with the appropriate
 /// values. These values are used by the DWARF EH emitter.
-bool SjLjEHPrepare::setupEntryBlockAndCallSites(Function &F) {
+bool SjLjEHPrepareImpl::setupEntryBlockAndCallSites(Function &F) {
   SmallVector<ReturnInst *, 16> Returns;
   SmallVector<InvokeInst *, 16> Invokes;
   SmallSetVector<LandingPadInst *, 16> LPads;
@@ -479,7 +498,7 @@ bool SjLjEHPrepare::setupEntryBlockAndCallSites(Function &F) {
   return true;
 }
 
-bool SjLjEHPrepare::runOnFunction(Function &F) {
+bool SjLjEHPrepareImpl::runOnFunction(Function &F) {
   Module &M = *F.getParent();
   RegisterFn = M.getOrInsertFunction(
       "_Unwind_SjLj_Register", Type::getVoidTy(M.getContext()),
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index 36f6e5396375..c48e591fc600 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -81,6 +81,7 @@
 #include "llvm/CodeGen/JMCInstrumenter.h"
 #include "llvm/CodeGen/SafeStack.h"
 #include "llvm/CodeGen/SelectOptimize.h"
+#include "llvm/CodeGen/SjLjEHPrepare.h"
 #include "llvm/CodeGen/TypePromotion.h"
 #include "llvm/CodeGen/WasmEHPrepare.h"
 #include "llvm/CodeGen/WinEHPrepare.h"
diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def
index 9afb73b2e8c1..6afc8b4898fe 100644
--- a/llvm/lib/Passes/PassRegistry.def
+++ b/llvm/lib/Passes/PassRegistry.def
@@ -401,6 +401,7 @@ FUNCTION_PASS("select-optimize", SelectOptimizePass(TM))
 FUNCTION_PASS("separate-const-offset-from-gep",
               SeparateConstOffsetFromGEPPass())
 FUNCTION_PASS("sink", SinkingPass())
+FUNCTION_PASS("sjlj-eh-prepare", SjLjEHPreparePass(TM))
 FUNCTION_PASS("slp-vectorizer", SLPVectorizerPass())
 FUNCTION_PASS("slsr", StraightLineStrengthReducePass())
 FUNCTION_PASS("strip-gc-relocates", StripGCRelocates())
diff --git a/llvm/test/CodeGen/ARM/sjljeh-swifterror.ll b/llvm/test/CodeGen/ARM/sjljeh-swifterror.ll
index 1436a73c7c26..46f559f2a81d 100644
--- a/llvm/test/CodeGen/ARM/sjljeh-swifterror.ll
+++ b/llvm/test/CodeGen/ARM/sjljeh-swifterror.ll
@@ -1,4 +1,5 @@
-; RUN: opt -sjljehprepare -verify < %s -S | FileCheck %s
+; RUN: opt -sjlj-eh-prepare < %s -S | FileCheck %s
+; RUN: opt -passes=sjlj-eh-prepare < %s -S | FileCheck %s
 target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
 target triple = "armv7s-apple-ios7.0"
 
diff --git a/llvm/tools/opt/opt.cpp b/llvm/tools/opt/opt.cpp
index e2ff73c9d073..62081fc01b13 100644
--- a/llvm/tools/opt/opt.cpp
+++ b/llvm/tools/opt/opt.cpp
@@ -339,8 +339,7 @@ static bool shouldPinPassToLegacyPM(StringRef Pass) {
       "nvptx-",  "mips-",  "lanai-", "hexagon-", "bpf-",    "avr-",
       "thumb2-", "arm-",   "si-",    "gcn-",     "amdgpu-", "aarch64-",
       "amdgcn-", "polly-", "riscv-", "dxil-"};
-  // TODO: remove "ehprepare"
-  std::vector<StringRef> PassNameContain = {"-eh-prepare", "ehprepare"};
+  std::vector<StringRef> PassNameContain = {"-eh-prepare"};
   std::vector<StringRef> PassNameExact = {
       "safe-stack",
       "cost-model",
-- 
GitLab


From c4ac1d239fbc13c66d3eabdc24783ebb407c35e4 Mon Sep 17 00:00:00 2001
From: Yingchi Long <i@lyc.dev>
Date: Tue, 12 Dec 2023 16:19:34 +0800
Subject: [PATCH 233/349] [BPF][GlobalISel] select non-PreISelGenericOpcode
 (#75034)

This selects non-PreISelGenericOpcode as-is.

Depends on: #74999

Co-authored-by: Origami404 <Origami404@foxmail.com>
---
 llvm/lib/Target/BPF/GISel/BPFInstructionSelector.cpp  | 2 ++
 llvm/test/CodeGen/BPF/GlobalISel/ir-translator-ret.ll | 5 +++++
 2 files changed, 7 insertions(+)

diff --git a/llvm/lib/Target/BPF/GISel/BPFInstructionSelector.cpp b/llvm/lib/Target/BPF/GISel/BPFInstructionSelector.cpp
index 1effeb7a57b1..c7db93a260c4 100644
--- a/llvm/lib/Target/BPF/GISel/BPFInstructionSelector.cpp
+++ b/llvm/lib/Target/BPF/GISel/BPFInstructionSelector.cpp
@@ -76,6 +76,8 @@ BPFInstructionSelector::BPFInstructionSelector(const BPFTargetMachine &TM,
 }
 
 bool BPFInstructionSelector::select(MachineInstr &I) {
+  if (!isPreISelGenericOpcode(I.getOpcode()))
+    return true;
   if (selectImpl(I, *CoverageInfo))
     return true;
   return false;
diff --git a/llvm/test/CodeGen/BPF/GlobalISel/ir-translator-ret.ll b/llvm/test/CodeGen/BPF/GlobalISel/ir-translator-ret.ll
index 7a014f7841fc..031e82dcb67b 100644
--- a/llvm/test/CodeGen/BPF/GlobalISel/ir-translator-ret.ll
+++ b/llvm/test/CodeGen/BPF/GlobalISel/ir-translator-ret.ll
@@ -1,7 +1,12 @@
 ; RUN: llc -mtriple=bpfel -global-isel -verify-machineinstrs -stop-after=irtranslator < %s | FileCheck %s
+; RUN: llc -mtriple=bpfel -global-isel -verify-machineinstrs < %s | FileCheck --check-prefix=ISEL %s
 
 ; CHECK: name: f
 ; CHECK: RET
 define void @f() {
+; ISEL-LABEL: f:
+; ISEL:       # %bb.0:
+; ISEL-NEXT:  exit
+; ISEL-NEXT: .Lfunc_end0:
   ret void
 }
-- 
GitLab


From 39445046dc945070f80579c582fb28dc937ec15f Mon Sep 17 00:00:00 2001
From: Luke Lau <luke@igalia.com>
Date: Tue, 12 Dec 2023 17:25:19 +0900
Subject: [PATCH 234/349] [RISCV] Remove unecessary early exit in
 transferBefore (#74040)

Previously we bailed if we encountered a pseudo without a VL op, i.e.
vmv.x.s,
which prevented us from preserving VL and VTYPE. It looks like this was
copied
over from a time whenever this code was operating on the MachineInstrs
in
place, see https://reviews.llvm.org/D127870

However because we no longer mutate the MIs, we can just get rid of this
early
exit which allows us to preserve VL and VTYPE when dealing with vmv.x.s.
---
 llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp  |   5 -
 .../RISCV/65704-illegal-instruction.ll        |   6 +-
 llvm/test/CodeGen/RISCV/double_reduct.ll      |   2 +-
 .../RISCV/rvv/fixed-vectors-extract-i1.ll     |  20 +-
 .../RISCV/rvv/fixed-vectors-masked-gather.ll  | 496 +++++++-----------
 .../RISCV/rvv/fixed-vectors-masked-scatter.ll |  84 +--
 .../RISCV/rvv/fixed-vectors-reduction-fp.ll   |  34 +-
 .../RISCV/rvv/fixed-vectors-reduction-int.ll  |  48 +-
 .../RISCV/rvv/fixed-vectors-unaligned.ll      |  20 +-
 .../RISCV/rvv/vreductions-fp-sdnode.ll        |  16 +-
 .../CodeGen/RISCV/rvv/vreductions-int-vp.ll   |   8 +-
 .../test/CodeGen/RISCV/rvv/vreductions-int.ll |  24 +-
 llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll |   3 +-
 .../CodeGen/RISCV/rvv/vsetvli-regression.ll   |   2 +-
 14 files changed, 313 insertions(+), 455 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index ed3489f6db1c..c9c6b2185403 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -1062,11 +1062,6 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
   if (Info.hasSEWLMULRatioOnly() || !Info.isValid() || Info.isUnknown())
     Info = NewInfo;
 
-  if (!RISCVII::hasVLOp(TSFlags)) {
-    Info = NewInfo;
-    return;
-  }
-
   DemandedFields Demanded = getDemanded(MI, MRI, ST);
   const VSETVLIInfo IncomingInfo =
       adjustIncoming(PrevInfo, NewInfo, Demanded, MRI);
diff --git a/llvm/test/CodeGen/RISCV/65704-illegal-instruction.ll b/llvm/test/CodeGen/RISCV/65704-illegal-instruction.ll
index 3181fa60cfa2..42d6dac5b07f 100644
--- a/llvm/test/CodeGen/RISCV/65704-illegal-instruction.ll
+++ b/llvm/test/CodeGen/RISCV/65704-illegal-instruction.ll
@@ -22,11 +22,11 @@ define void @foo(<vscale x 8 x i8> %0) {
 ; CHECK-NEXT:    vmv.v.i v9, 0
 ; CHECK-NEXT:    vsetivli zero, 0, e8, m1, tu, ma
 ; CHECK-NEXT:    vslideup.vi v9, v10, 0
-; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
 ; CHECK-NEXT:    vmv.x.s s0, v9
-; CHECK-NEXT:    vsetivli zero, 0, e8, m1, tu, ma
+; CHECK-NEXT:    vsetvli zero, zero, e8, m1, tu, ma
 ; CHECK-NEXT:    vslideup.vi v8, v9, 0
-; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
 ; CHECK-NEXT:    vmv.x.s s1, v8
 ; CHECK-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    li a1, 0
diff --git a/llvm/test/CodeGen/RISCV/double_reduct.ll b/llvm/test/CodeGen/RISCV/double_reduct.ll
index 92f78032e81b..25228b21ef05 100644
--- a/llvm/test/CodeGen/RISCV/double_reduct.ll
+++ b/llvm/test/CodeGen/RISCV/double_reduct.ll
@@ -113,7 +113,7 @@ define i16 @add_ext_v32i16(<32 x i8> %a, <16 x i8> %b) {
 ; CHECK-NEXT:    li a0, 32
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
 ; CHECK-NEXT:    vwredsumu.vs v8, v8, v10
-; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %ae = zext <32 x i8> %a to <32 x i16>
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
index 9d689c732d79..dccb62877af3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
@@ -106,7 +106,7 @@ define i1 @extractelt_v16i1(ptr %x, i64 %idx) nounwind {
 ; RV32-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
 ; RV32-NEXT:    vle8.v v8, (a0)
 ; RV32-NEXT:    vmseq.vi v8, v8, 0
-; RV32-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
+; RV32-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
 ; RV32-NEXT:    vmv.x.s a0, v8
 ; RV32-NEXT:    srl a0, a0, a1
 ; RV32-NEXT:    andi a0, a0, 1
@@ -117,7 +117,7 @@ define i1 @extractelt_v16i1(ptr %x, i64 %idx) nounwind {
 ; RV64-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
 ; RV64-NEXT:    vle8.v v8, (a0)
 ; RV64-NEXT:    vmseq.vi v8, v8, 0
-; RV64-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
+; RV64-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
 ; RV64-NEXT:    vmv.x.s a0, v8
 ; RV64-NEXT:    srl a0, a0, a1
 ; RV64-NEXT:    andi a0, a0, 1
@@ -128,7 +128,7 @@ define i1 @extractelt_v16i1(ptr %x, i64 %idx) nounwind {
 ; RV32ZBS-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
 ; RV32ZBS-NEXT:    vle8.v v8, (a0)
 ; RV32ZBS-NEXT:    vmseq.vi v8, v8, 0
-; RV32ZBS-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
+; RV32ZBS-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
 ; RV32ZBS-NEXT:    vmv.x.s a0, v8
 ; RV32ZBS-NEXT:    bext a0, a0, a1
 ; RV32ZBS-NEXT:    ret
@@ -138,7 +138,7 @@ define i1 @extractelt_v16i1(ptr %x, i64 %idx) nounwind {
 ; RV64ZBS-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
 ; RV64ZBS-NEXT:    vle8.v v8, (a0)
 ; RV64ZBS-NEXT:    vmseq.vi v8, v8, 0
-; RV64ZBS-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
+; RV64ZBS-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
 ; RV64ZBS-NEXT:    vmv.x.s a0, v8
 ; RV64ZBS-NEXT:    bext a0, a0, a1
 ; RV64ZBS-NEXT:    ret
@@ -155,7 +155,7 @@ define i1 @extractelt_v32i1(ptr %x, i64 %idx) nounwind {
 ; RV32-NEXT:    vsetvli zero, a2, e8, m2, ta, ma
 ; RV32-NEXT:    vle8.v v8, (a0)
 ; RV32-NEXT:    vmseq.vi v10, v8, 0
-; RV32-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
+; RV32-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
 ; RV32-NEXT:    vmv.x.s a0, v10
 ; RV32-NEXT:    srl a0, a0, a1
 ; RV32-NEXT:    andi a0, a0, 1
@@ -167,7 +167,7 @@ define i1 @extractelt_v32i1(ptr %x, i64 %idx) nounwind {
 ; RV64-NEXT:    vsetvli zero, a2, e8, m2, ta, ma
 ; RV64-NEXT:    vle8.v v8, (a0)
 ; RV64-NEXT:    vmseq.vi v10, v8, 0
-; RV64-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
+; RV64-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
 ; RV64-NEXT:    vmv.x.s a0, v10
 ; RV64-NEXT:    srl a0, a0, a1
 ; RV64-NEXT:    andi a0, a0, 1
@@ -179,7 +179,7 @@ define i1 @extractelt_v32i1(ptr %x, i64 %idx) nounwind {
 ; RV32ZBS-NEXT:    vsetvli zero, a2, e8, m2, ta, ma
 ; RV32ZBS-NEXT:    vle8.v v8, (a0)
 ; RV32ZBS-NEXT:    vmseq.vi v10, v8, 0
-; RV32ZBS-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
+; RV32ZBS-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
 ; RV32ZBS-NEXT:    vmv.x.s a0, v10
 ; RV32ZBS-NEXT:    bext a0, a0, a1
 ; RV32ZBS-NEXT:    ret
@@ -190,7 +190,7 @@ define i1 @extractelt_v32i1(ptr %x, i64 %idx) nounwind {
 ; RV64ZBS-NEXT:    vsetvli zero, a2, e8, m2, ta, ma
 ; RV64ZBS-NEXT:    vle8.v v8, (a0)
 ; RV64ZBS-NEXT:    vmseq.vi v10, v8, 0
-; RV64ZBS-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
+; RV64ZBS-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
 ; RV64ZBS-NEXT:    vmv.x.s a0, v10
 ; RV64ZBS-NEXT:    bext a0, a0, a1
 ; RV64ZBS-NEXT:    ret
@@ -221,7 +221,7 @@ define i1 @extractelt_v64i1(ptr %x, i64 %idx) nounwind {
 ; RV64-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
 ; RV64-NEXT:    vle8.v v8, (a0)
 ; RV64-NEXT:    vmseq.vi v12, v8, 0
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
 ; RV64-NEXT:    vmv.x.s a0, v12
 ; RV64-NEXT:    srl a0, a0, a1
 ; RV64-NEXT:    andi a0, a0, 1
@@ -246,7 +246,7 @@ define i1 @extractelt_v64i1(ptr %x, i64 %idx) nounwind {
 ; RV64ZBS-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
 ; RV64ZBS-NEXT:    vle8.v v8, (a0)
 ; RV64ZBS-NEXT:    vmseq.vi v12, v8, 0
-; RV64ZBS-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; RV64ZBS-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
 ; RV64ZBS-NEXT:    vmv.x.s a0, v12
 ; RV64ZBS-NEXT:    bext a0, a0, a1
 ; RV64ZBS-NEXT:    ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
index d74fd6cd3f03..ac3bf0d89b5e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
@@ -3844,7 +3844,7 @@ define <4 x i64> @mgather_truemask_v4i64(<4 x ptr> %ptrs, <4 x i64> %passthru) {
 ; RV32ZVE32F-NEXT:    vmv.x.s a6, v9
 ; RV32ZVE32F-NEXT:    bnez zero, .LBB45_5
 ; RV32ZVE32F-NEXT:  # %bb.1: # %cond.load
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a3, v8
 ; RV32ZVE32F-NEXT:    lw a2, 4(a3)
 ; RV32ZVE32F-NEXT:    lw a3, 0(a3)
@@ -4265,12 +4265,12 @@ define <8 x i64> @mgather_baseidx_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8 x i1>
 ; RV32ZVE32F-NEXT:    vsext.vf4 v10, v8
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s t0, v0
 ; RV32ZVE32F-NEXT:    andi a1, t0, 1
 ; RV32ZVE32F-NEXT:    beqz a1, .LBB48_7
 ; RV32ZVE32F-NEXT:  # %bb.1: # %cond.load
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a3, v8
 ; RV32ZVE32F-NEXT:    lw a1, 4(a3)
 ; RV32ZVE32F-NEXT:    lw a3, 0(a3)
@@ -4539,12 +4539,12 @@ define <8 x i64> @mgather_baseidx_sext_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8
 ; RV32ZVE32F-NEXT:    vsext.vf4 v10, v8
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s t0, v0
 ; RV32ZVE32F-NEXT:    andi a1, t0, 1
 ; RV32ZVE32F-NEXT:    beqz a1, .LBB49_7
 ; RV32ZVE32F-NEXT:  # %bb.1: # %cond.load
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a3, v8
 ; RV32ZVE32F-NEXT:    lw a1, 4(a3)
 ; RV32ZVE32F-NEXT:    lw a3, 0(a3)
@@ -4815,12 +4815,12 @@ define <8 x i64> @mgather_baseidx_zext_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8
 ; RV32ZVE32F-NEXT:    vzext.vf4 v10, v8
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s t0, v0
 ; RV32ZVE32F-NEXT:    andi a1, t0, 1
 ; RV32ZVE32F-NEXT:    beqz a1, .LBB50_7
 ; RV32ZVE32F-NEXT:  # %bb.1: # %cond.load
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a3, v8
 ; RV32ZVE32F-NEXT:    lw a1, 4(a3)
 ; RV32ZVE32F-NEXT:    lw a3, 0(a3)
@@ -5098,12 +5098,12 @@ define <8 x i64> @mgather_baseidx_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <8 x i
 ; RV32ZVE32F-NEXT:    vsext.vf2 v10, v8
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s t0, v0
 ; RV32ZVE32F-NEXT:    andi a1, t0, 1
 ; RV32ZVE32F-NEXT:    beqz a1, .LBB51_7
 ; RV32ZVE32F-NEXT:  # %bb.1: # %cond.load
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a3, v8
 ; RV32ZVE32F-NEXT:    lw a1, 4(a3)
 ; RV32ZVE32F-NEXT:    lw a3, 0(a3)
@@ -5373,12 +5373,12 @@ define <8 x i64> @mgather_baseidx_sext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
 ; RV32ZVE32F-NEXT:    vsext.vf2 v10, v8
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s t0, v0
 ; RV32ZVE32F-NEXT:    andi a1, t0, 1
 ; RV32ZVE32F-NEXT:    beqz a1, .LBB52_7
 ; RV32ZVE32F-NEXT:  # %bb.1: # %cond.load
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a3, v8
 ; RV32ZVE32F-NEXT:    lw a1, 4(a3)
 ; RV32ZVE32F-NEXT:    lw a3, 0(a3)
@@ -5650,12 +5650,12 @@ define <8 x i64> @mgather_baseidx_zext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
 ; RV32ZVE32F-NEXT:    vzext.vf2 v10, v8
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s t0, v0
 ; RV32ZVE32F-NEXT:    andi a1, t0, 1
 ; RV32ZVE32F-NEXT:    beqz a1, .LBB53_7
 ; RV32ZVE32F-NEXT:  # %bb.1: # %cond.load
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a3, v8
 ; RV32ZVE32F-NEXT:    lw a1, 4(a3)
 ; RV32ZVE32F-NEXT:    lw a3, 0(a3)
@@ -5934,12 +5934,12 @@ define <8 x i64> @mgather_baseidx_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <8 x i
 ; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v8, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s t0, v0
 ; RV32ZVE32F-NEXT:    andi a1, t0, 1
 ; RV32ZVE32F-NEXT:    beqz a1, .LBB54_7
 ; RV32ZVE32F-NEXT:  # %bb.1: # %cond.load
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a3, v8
 ; RV32ZVE32F-NEXT:    lw a1, 4(a3)
 ; RV32ZVE32F-NEXT:    lw a3, 0(a3)
@@ -6207,12 +6207,12 @@ define <8 x i64> @mgather_baseidx_sext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
 ; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v8, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s t0, v0
 ; RV32ZVE32F-NEXT:    andi a1, t0, 1
 ; RV32ZVE32F-NEXT:    beqz a1, .LBB55_7
 ; RV32ZVE32F-NEXT:  # %bb.1: # %cond.load
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a3, v8
 ; RV32ZVE32F-NEXT:    lw a1, 4(a3)
 ; RV32ZVE32F-NEXT:    lw a3, 0(a3)
@@ -6481,12 +6481,12 @@ define <8 x i64> @mgather_baseidx_zext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
 ; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v8, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s t0, v0
 ; RV32ZVE32F-NEXT:    andi a1, t0, 1
 ; RV32ZVE32F-NEXT:    beqz a1, .LBB56_7
 ; RV32ZVE32F-NEXT:  # %bb.1: # %cond.load
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a3, v8
 ; RV32ZVE32F-NEXT:    lw a1, 4(a3)
 ; RV32ZVE32F-NEXT:    lw a3, 0(a3)
@@ -6778,12 +6778,12 @@ define <8 x i64> @mgather_baseidx_v8i64(ptr %base, <8 x i64> %idxs, <8 x i1> %m,
 ; RV32ZVE32F-NEXT:    vslide1down.vx v8, v8, a4
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v8, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s t0, v0
 ; RV32ZVE32F-NEXT:    andi a1, t0, 1
 ; RV32ZVE32F-NEXT:    beqz a1, .LBB57_7
 ; RV32ZVE32F-NEXT:  # %bb.1: # %cond.load
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a2, v8
 ; RV32ZVE32F-NEXT:    lw a1, 4(a2)
 ; RV32ZVE32F-NEXT:    lw a2, 0(a2)
@@ -9652,7 +9652,7 @@ define <4 x double> @mgather_truemask_v4f64(<4 x ptr> %ptrs, <4 x double> %passt
 ; RV32ZVE32F-NEXT:    fsd fa3, 24(a0)
 ; RV32ZVE32F-NEXT:    ret
 ; RV32ZVE32F-NEXT:  .LBB84_6: # %cond.load
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a2, v8
 ; RV32ZVE32F-NEXT:    fld fa0, 0(a2)
 ; RV32ZVE32F-NEXT:    andi a2, a1, 2
@@ -9964,7 +9964,7 @@ define <8 x double> @mgather_baseidx_v8i8_v8f64(ptr %base, <8 x i8> %idxs, <8 x
 ; RV32ZVE32F-NEXT:    vsext.vf4 v10, v8
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v0
 ; RV32ZVE32F-NEXT:    andi a2, a1, 1
 ; RV32ZVE32F-NEXT:    bnez a2, .LBB87_10
@@ -10005,7 +10005,7 @@ define <8 x double> @mgather_baseidx_v8i8_v8f64(ptr %base, <8 x i8> %idxs, <8 x
 ; RV32ZVE32F-NEXT:    fsd fa7, 56(a0)
 ; RV32ZVE32F-NEXT:    ret
 ; RV32ZVE32F-NEXT:  .LBB87_10: # %cond.load
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a2, v8
 ; RV32ZVE32F-NEXT:    fld fa0, 0(a2)
 ; RV32ZVE32F-NEXT:    andi a2, a1, 2
@@ -10179,7 +10179,7 @@ define <8 x double> @mgather_baseidx_sext_v8i8_v8f64(ptr %base, <8 x i8> %idxs,
 ; RV32ZVE32F-NEXT:    vsext.vf4 v10, v8
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v0
 ; RV32ZVE32F-NEXT:    andi a2, a1, 1
 ; RV32ZVE32F-NEXT:    bnez a2, .LBB88_10
@@ -10220,7 +10220,7 @@ define <8 x double> @mgather_baseidx_sext_v8i8_v8f64(ptr %base, <8 x i8> %idxs,
 ; RV32ZVE32F-NEXT:    fsd fa7, 56(a0)
 ; RV32ZVE32F-NEXT:    ret
 ; RV32ZVE32F-NEXT:  .LBB88_10: # %cond.load
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a2, v8
 ; RV32ZVE32F-NEXT:    fld fa0, 0(a2)
 ; RV32ZVE32F-NEXT:    andi a2, a1, 2
@@ -10396,7 +10396,7 @@ define <8 x double> @mgather_baseidx_zext_v8i8_v8f64(ptr %base, <8 x i8> %idxs,
 ; RV32ZVE32F-NEXT:    vzext.vf4 v10, v8
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v0
 ; RV32ZVE32F-NEXT:    andi a2, a1, 1
 ; RV32ZVE32F-NEXT:    bnez a2, .LBB89_10
@@ -10437,7 +10437,7 @@ define <8 x double> @mgather_baseidx_zext_v8i8_v8f64(ptr %base, <8 x i8> %idxs,
 ; RV32ZVE32F-NEXT:    fsd fa7, 56(a0)
 ; RV32ZVE32F-NEXT:    ret
 ; RV32ZVE32F-NEXT:  .LBB89_10: # %cond.load
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a2, v8
 ; RV32ZVE32F-NEXT:    fld fa0, 0(a2)
 ; RV32ZVE32F-NEXT:    andi a2, a1, 2
@@ -10620,7 +10620,7 @@ define <8 x double> @mgather_baseidx_v8i16_v8f64(ptr %base, <8 x i16> %idxs, <8
 ; RV32ZVE32F-NEXT:    vsext.vf2 v10, v8
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v0
 ; RV32ZVE32F-NEXT:    andi a2, a1, 1
 ; RV32ZVE32F-NEXT:    bnez a2, .LBB90_10
@@ -10661,7 +10661,7 @@ define <8 x double> @mgather_baseidx_v8i16_v8f64(ptr %base, <8 x i16> %idxs, <8
 ; RV32ZVE32F-NEXT:    fsd fa7, 56(a0)
 ; RV32ZVE32F-NEXT:    ret
 ; RV32ZVE32F-NEXT:  .LBB90_10: # %cond.load
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a2, v8
 ; RV32ZVE32F-NEXT:    fld fa0, 0(a2)
 ; RV32ZVE32F-NEXT:    andi a2, a1, 2
@@ -10836,7 +10836,7 @@ define <8 x double> @mgather_baseidx_sext_v8i16_v8f64(ptr %base, <8 x i16> %idxs
 ; RV32ZVE32F-NEXT:    vsext.vf2 v10, v8
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v0
 ; RV32ZVE32F-NEXT:    andi a2, a1, 1
 ; RV32ZVE32F-NEXT:    bnez a2, .LBB91_10
@@ -10877,7 +10877,7 @@ define <8 x double> @mgather_baseidx_sext_v8i16_v8f64(ptr %base, <8 x i16> %idxs
 ; RV32ZVE32F-NEXT:    fsd fa7, 56(a0)
 ; RV32ZVE32F-NEXT:    ret
 ; RV32ZVE32F-NEXT:  .LBB91_10: # %cond.load
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a2, v8
 ; RV32ZVE32F-NEXT:    fld fa0, 0(a2)
 ; RV32ZVE32F-NEXT:    andi a2, a1, 2
@@ -11054,7 +11054,7 @@ define <8 x double> @mgather_baseidx_zext_v8i16_v8f64(ptr %base, <8 x i16> %idxs
 ; RV32ZVE32F-NEXT:    vzext.vf2 v10, v8
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v0
 ; RV32ZVE32F-NEXT:    andi a2, a1, 1
 ; RV32ZVE32F-NEXT:    bnez a2, .LBB92_10
@@ -11095,7 +11095,7 @@ define <8 x double> @mgather_baseidx_zext_v8i16_v8f64(ptr %base, <8 x i16> %idxs
 ; RV32ZVE32F-NEXT:    fsd fa7, 56(a0)
 ; RV32ZVE32F-NEXT:    ret
 ; RV32ZVE32F-NEXT:  .LBB92_10: # %cond.load
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a2, v8
 ; RV32ZVE32F-NEXT:    fld fa0, 0(a2)
 ; RV32ZVE32F-NEXT:    andi a2, a1, 2
@@ -11279,7 +11279,7 @@ define <8 x double> @mgather_baseidx_v8i32_v8f64(ptr %base, <8 x i32> %idxs, <8
 ; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v8, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v0
 ; RV32ZVE32F-NEXT:    andi a2, a1, 1
 ; RV32ZVE32F-NEXT:    bnez a2, .LBB93_10
@@ -11320,7 +11320,7 @@ define <8 x double> @mgather_baseidx_v8i32_v8f64(ptr %base, <8 x i32> %idxs, <8
 ; RV32ZVE32F-NEXT:    fsd fa7, 56(a0)
 ; RV32ZVE32F-NEXT:    ret
 ; RV32ZVE32F-NEXT:  .LBB93_10: # %cond.load
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a2, v8
 ; RV32ZVE32F-NEXT:    fld fa0, 0(a2)
 ; RV32ZVE32F-NEXT:    andi a2, a1, 2
@@ -11493,7 +11493,7 @@ define <8 x double> @mgather_baseidx_sext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
 ; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v8, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v0
 ; RV32ZVE32F-NEXT:    andi a2, a1, 1
 ; RV32ZVE32F-NEXT:    bnez a2, .LBB94_10
@@ -11534,7 +11534,7 @@ define <8 x double> @mgather_baseidx_sext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
 ; RV32ZVE32F-NEXT:    fsd fa7, 56(a0)
 ; RV32ZVE32F-NEXT:    ret
 ; RV32ZVE32F-NEXT:  .LBB94_10: # %cond.load
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a2, v8
 ; RV32ZVE32F-NEXT:    fld fa0, 0(a2)
 ; RV32ZVE32F-NEXT:    andi a2, a1, 2
@@ -11708,7 +11708,7 @@ define <8 x double> @mgather_baseidx_zext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
 ; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v8, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v0
 ; RV32ZVE32F-NEXT:    andi a2, a1, 1
 ; RV32ZVE32F-NEXT:    bnez a2, .LBB95_10
@@ -11749,7 +11749,7 @@ define <8 x double> @mgather_baseidx_zext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
 ; RV32ZVE32F-NEXT:    fsd fa7, 56(a0)
 ; RV32ZVE32F-NEXT:    ret
 ; RV32ZVE32F-NEXT:  .LBB95_10: # %cond.load
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a2, v8
 ; RV32ZVE32F-NEXT:    fld fa0, 0(a2)
 ; RV32ZVE32F-NEXT:    andi a2, a1, 2
@@ -11946,7 +11946,7 @@ define <8 x double> @mgather_baseidx_v8f64(ptr %base, <8 x i64> %idxs, <8 x i1>
 ; RV32ZVE32F-NEXT:    vslide1down.vx v8, v8, a3
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v8, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v0
 ; RV32ZVE32F-NEXT:    andi a2, a1, 1
 ; RV32ZVE32F-NEXT:    bnez a2, .LBB96_10
@@ -11987,7 +11987,7 @@ define <8 x double> @mgather_baseidx_v8f64(ptr %base, <8 x i64> %idxs, <8 x i1>
 ; RV32ZVE32F-NEXT:    fsd fa7, 56(a0)
 ; RV32ZVE32F-NEXT:    ret
 ; RV32ZVE32F-NEXT:  .LBB96_10: # %cond.load
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a2, v8
 ; RV32ZVE32F-NEXT:    fld fa0, 0(a2)
 ; RV32ZVE32F-NEXT:    andi a2, a1, 2
@@ -13056,141 +13056,141 @@ define <4 x i32> @mgather_narrow_edge_case(ptr %base) {
 }
 
 define <8 x i16> @mgather_strided_unaligned(ptr %base) {
-; RV32V-LABEL: mgather_strided_unaligned:
-; RV32V:       # %bb.0:
-; RV32V-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
-; RV32V-NEXT:    vmset.m v8
-; RV32V-NEXT:    vid.v v10
-; RV32V-NEXT:    vsll.vi v10, v10, 2
-; RV32V-NEXT:    vadd.vx v10, v10, a0
-; RV32V-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
-; RV32V-NEXT:    vmv.x.s a0, v8
-; RV32V-NEXT:    # implicit-def: $v8
-; RV32V-NEXT:    beqz zero, .LBB107_9
-; RV32V-NEXT:  # %bb.1: # %else
-; RV32V-NEXT:    andi a1, a0, 2
-; RV32V-NEXT:    bnez a1, .LBB107_10
-; RV32V-NEXT:  .LBB107_2: # %else2
-; RV32V-NEXT:    andi a1, a0, 4
-; RV32V-NEXT:    bnez a1, .LBB107_11
-; RV32V-NEXT:  .LBB107_3: # %else5
-; RV32V-NEXT:    andi a1, a0, 8
-; RV32V-NEXT:    bnez a1, .LBB107_12
-; RV32V-NEXT:  .LBB107_4: # %else8
-; RV32V-NEXT:    andi a1, a0, 16
-; RV32V-NEXT:    bnez a1, .LBB107_13
-; RV32V-NEXT:  .LBB107_5: # %else11
-; RV32V-NEXT:    andi a1, a0, 32
-; RV32V-NEXT:    bnez a1, .LBB107_14
-; RV32V-NEXT:  .LBB107_6: # %else14
-; RV32V-NEXT:    andi a1, a0, 64
-; RV32V-NEXT:    bnez a1, .LBB107_15
-; RV32V-NEXT:  .LBB107_7: # %else17
-; RV32V-NEXT:    andi a0, a0, -128
-; RV32V-NEXT:    bnez a0, .LBB107_16
-; RV32V-NEXT:  .LBB107_8: # %else20
-; RV32V-NEXT:    ret
-; RV32V-NEXT:  .LBB107_9: # %cond.load
-; RV32V-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32V-NEXT:    vmv.x.s a1, v10
-; RV32V-NEXT:    lbu a2, 1(a1)
-; RV32V-NEXT:    lbu a1, 0(a1)
-; RV32V-NEXT:    slli a2, a2, 8
-; RV32V-NEXT:    or a1, a2, a1
-; RV32V-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32V-NEXT:    vmv.v.x v8, a1
-; RV32V-NEXT:    andi a1, a0, 2
-; RV32V-NEXT:    beqz a1, .LBB107_2
-; RV32V-NEXT:  .LBB107_10: # %cond.load1
-; RV32V-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32V-NEXT:    vslidedown.vi v9, v10, 1
-; RV32V-NEXT:    vmv.x.s a1, v9
-; RV32V-NEXT:    lbu a2, 1(a1)
-; RV32V-NEXT:    lbu a1, 0(a1)
-; RV32V-NEXT:    slli a2, a2, 8
-; RV32V-NEXT:    or a1, a2, a1
-; RV32V-NEXT:    vmv.s.x v9, a1
-; RV32V-NEXT:    vsetivli zero, 2, e16, m1, tu, ma
-; RV32V-NEXT:    vslideup.vi v8, v9, 1
-; RV32V-NEXT:    andi a1, a0, 4
-; RV32V-NEXT:    beqz a1, .LBB107_3
-; RV32V-NEXT:  .LBB107_11: # %cond.load4
-; RV32V-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32V-NEXT:    vslidedown.vi v9, v10, 2
-; RV32V-NEXT:    vmv.x.s a1, v9
-; RV32V-NEXT:    lbu a2, 1(a1)
-; RV32V-NEXT:    lbu a1, 0(a1)
-; RV32V-NEXT:    slli a2, a2, 8
-; RV32V-NEXT:    or a1, a2, a1
-; RV32V-NEXT:    vmv.s.x v9, a1
-; RV32V-NEXT:    vsetivli zero, 3, e16, m1, tu, ma
-; RV32V-NEXT:    vslideup.vi v8, v9, 2
-; RV32V-NEXT:    andi a1, a0, 8
-; RV32V-NEXT:    beqz a1, .LBB107_4
-; RV32V-NEXT:  .LBB107_12: # %cond.load7
-; RV32V-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32V-NEXT:    vslidedown.vi v9, v10, 3
-; RV32V-NEXT:    vmv.x.s a1, v9
-; RV32V-NEXT:    lbu a2, 1(a1)
-; RV32V-NEXT:    lbu a1, 0(a1)
-; RV32V-NEXT:    slli a2, a2, 8
-; RV32V-NEXT:    or a1, a2, a1
-; RV32V-NEXT:    vmv.s.x v9, a1
-; RV32V-NEXT:    vsetivli zero, 4, e16, m1, tu, ma
-; RV32V-NEXT:    vslideup.vi v8, v9, 3
-; RV32V-NEXT:    andi a1, a0, 16
-; RV32V-NEXT:    beqz a1, .LBB107_5
-; RV32V-NEXT:  .LBB107_13: # %cond.load10
-; RV32V-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
-; RV32V-NEXT:    vslidedown.vi v12, v10, 4
-; RV32V-NEXT:    vmv.x.s a1, v12
-; RV32V-NEXT:    lbu a2, 1(a1)
-; RV32V-NEXT:    lbu a1, 0(a1)
-; RV32V-NEXT:    slli a2, a2, 8
-; RV32V-NEXT:    or a1, a2, a1
-; RV32V-NEXT:    vmv.s.x v9, a1
-; RV32V-NEXT:    vsetivli zero, 5, e16, m1, tu, ma
-; RV32V-NEXT:    vslideup.vi v8, v9, 4
-; RV32V-NEXT:    andi a1, a0, 32
-; RV32V-NEXT:    beqz a1, .LBB107_6
-; RV32V-NEXT:  .LBB107_14: # %cond.load13
-; RV32V-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
-; RV32V-NEXT:    vslidedown.vi v12, v10, 5
-; RV32V-NEXT:    vmv.x.s a1, v12
-; RV32V-NEXT:    lbu a2, 1(a1)
-; RV32V-NEXT:    lbu a1, 0(a1)
-; RV32V-NEXT:    slli a2, a2, 8
-; RV32V-NEXT:    or a1, a2, a1
-; RV32V-NEXT:    vmv.s.x v9, a1
-; RV32V-NEXT:    vsetivli zero, 6, e16, m1, tu, ma
-; RV32V-NEXT:    vslideup.vi v8, v9, 5
-; RV32V-NEXT:    andi a1, a0, 64
-; RV32V-NEXT:    beqz a1, .LBB107_7
-; RV32V-NEXT:  .LBB107_15: # %cond.load16
-; RV32V-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
-; RV32V-NEXT:    vslidedown.vi v12, v10, 6
-; RV32V-NEXT:    vmv.x.s a1, v12
-; RV32V-NEXT:    lbu a2, 1(a1)
-; RV32V-NEXT:    lbu a1, 0(a1)
-; RV32V-NEXT:    slli a2, a2, 8
-; RV32V-NEXT:    or a1, a2, a1
-; RV32V-NEXT:    vmv.s.x v9, a1
-; RV32V-NEXT:    vsetivli zero, 7, e16, m1, tu, ma
-; RV32V-NEXT:    vslideup.vi v8, v9, 6
-; RV32V-NEXT:    andi a0, a0, -128
-; RV32V-NEXT:    beqz a0, .LBB107_8
-; RV32V-NEXT:  .LBB107_16: # %cond.load19
-; RV32V-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
-; RV32V-NEXT:    vslidedown.vi v10, v10, 7
-; RV32V-NEXT:    vmv.x.s a0, v10
-; RV32V-NEXT:    lbu a1, 1(a0)
-; RV32V-NEXT:    lbu a0, 0(a0)
-; RV32V-NEXT:    slli a1, a1, 8
-; RV32V-NEXT:    or a0, a1, a0
-; RV32V-NEXT:    vmv.s.x v9, a0
-; RV32V-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32V-NEXT:    vslideup.vi v8, v9, 7
-; RV32V-NEXT:    ret
+; RV32-LABEL: mgather_strided_unaligned:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
+; RV32-NEXT:    vmset.m v8
+; RV32-NEXT:    vid.v v10
+; RV32-NEXT:    vsll.vi v10, v10, 2
+; RV32-NEXT:    vadd.vx v10, v10, a0
+; RV32-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
+; RV32-NEXT:    vmv.x.s a0, v8
+; RV32-NEXT:    # implicit-def: $v8
+; RV32-NEXT:    beqz zero, .LBB107_9
+; RV32-NEXT:  # %bb.1: # %else
+; RV32-NEXT:    andi a1, a0, 2
+; RV32-NEXT:    bnez a1, .LBB107_10
+; RV32-NEXT:  .LBB107_2: # %else2
+; RV32-NEXT:    andi a1, a0, 4
+; RV32-NEXT:    bnez a1, .LBB107_11
+; RV32-NEXT:  .LBB107_3: # %else5
+; RV32-NEXT:    andi a1, a0, 8
+; RV32-NEXT:    bnez a1, .LBB107_12
+; RV32-NEXT:  .LBB107_4: # %else8
+; RV32-NEXT:    andi a1, a0, 16
+; RV32-NEXT:    bnez a1, .LBB107_13
+; RV32-NEXT:  .LBB107_5: # %else11
+; RV32-NEXT:    andi a1, a0, 32
+; RV32-NEXT:    bnez a1, .LBB107_14
+; RV32-NEXT:  .LBB107_6: # %else14
+; RV32-NEXT:    andi a1, a0, 64
+; RV32-NEXT:    bnez a1, .LBB107_15
+; RV32-NEXT:  .LBB107_7: # %else17
+; RV32-NEXT:    andi a0, a0, -128
+; RV32-NEXT:    bnez a0, .LBB107_16
+; RV32-NEXT:  .LBB107_8: # %else20
+; RV32-NEXT:    ret
+; RV32-NEXT:  .LBB107_9: # %cond.load
+; RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
+; RV32-NEXT:    vmv.x.s a1, v10
+; RV32-NEXT:    lbu a2, 1(a1)
+; RV32-NEXT:    lbu a1, 0(a1)
+; RV32-NEXT:    slli a2, a2, 8
+; RV32-NEXT:    or a1, a2, a1
+; RV32-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
+; RV32-NEXT:    vmv.v.x v8, a1
+; RV32-NEXT:    andi a1, a0, 2
+; RV32-NEXT:    beqz a1, .LBB107_2
+; RV32-NEXT:  .LBB107_10: # %cond.load1
+; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; RV32-NEXT:    vslidedown.vi v9, v10, 1
+; RV32-NEXT:    vmv.x.s a1, v9
+; RV32-NEXT:    lbu a2, 1(a1)
+; RV32-NEXT:    lbu a1, 0(a1)
+; RV32-NEXT:    slli a2, a2, 8
+; RV32-NEXT:    or a1, a2, a1
+; RV32-NEXT:    vmv.s.x v9, a1
+; RV32-NEXT:    vsetivli zero, 2, e16, m1, tu, ma
+; RV32-NEXT:    vslideup.vi v8, v9, 1
+; RV32-NEXT:    andi a1, a0, 4
+; RV32-NEXT:    beqz a1, .LBB107_3
+; RV32-NEXT:  .LBB107_11: # %cond.load4
+; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; RV32-NEXT:    vslidedown.vi v9, v10, 2
+; RV32-NEXT:    vmv.x.s a1, v9
+; RV32-NEXT:    lbu a2, 1(a1)
+; RV32-NEXT:    lbu a1, 0(a1)
+; RV32-NEXT:    slli a2, a2, 8
+; RV32-NEXT:    or a1, a2, a1
+; RV32-NEXT:    vmv.s.x v9, a1
+; RV32-NEXT:    vsetivli zero, 3, e16, m1, tu, ma
+; RV32-NEXT:    vslideup.vi v8, v9, 2
+; RV32-NEXT:    andi a1, a0, 8
+; RV32-NEXT:    beqz a1, .LBB107_4
+; RV32-NEXT:  .LBB107_12: # %cond.load7
+; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; RV32-NEXT:    vslidedown.vi v9, v10, 3
+; RV32-NEXT:    vmv.x.s a1, v9
+; RV32-NEXT:    lbu a2, 1(a1)
+; RV32-NEXT:    lbu a1, 0(a1)
+; RV32-NEXT:    slli a2, a2, 8
+; RV32-NEXT:    or a1, a2, a1
+; RV32-NEXT:    vmv.s.x v9, a1
+; RV32-NEXT:    vsetivli zero, 4, e16, m1, tu, ma
+; RV32-NEXT:    vslideup.vi v8, v9, 3
+; RV32-NEXT:    andi a1, a0, 16
+; RV32-NEXT:    beqz a1, .LBB107_5
+; RV32-NEXT:  .LBB107_13: # %cond.load10
+; RV32-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
+; RV32-NEXT:    vslidedown.vi v12, v10, 4
+; RV32-NEXT:    vmv.x.s a1, v12
+; RV32-NEXT:    lbu a2, 1(a1)
+; RV32-NEXT:    lbu a1, 0(a1)
+; RV32-NEXT:    slli a2, a2, 8
+; RV32-NEXT:    or a1, a2, a1
+; RV32-NEXT:    vmv.s.x v9, a1
+; RV32-NEXT:    vsetivli zero, 5, e16, m1, tu, ma
+; RV32-NEXT:    vslideup.vi v8, v9, 4
+; RV32-NEXT:    andi a1, a0, 32
+; RV32-NEXT:    beqz a1, .LBB107_6
+; RV32-NEXT:  .LBB107_14: # %cond.load13
+; RV32-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
+; RV32-NEXT:    vslidedown.vi v12, v10, 5
+; RV32-NEXT:    vmv.x.s a1, v12
+; RV32-NEXT:    lbu a2, 1(a1)
+; RV32-NEXT:    lbu a1, 0(a1)
+; RV32-NEXT:    slli a2, a2, 8
+; RV32-NEXT:    or a1, a2, a1
+; RV32-NEXT:    vmv.s.x v9, a1
+; RV32-NEXT:    vsetivli zero, 6, e16, m1, tu, ma
+; RV32-NEXT:    vslideup.vi v8, v9, 5
+; RV32-NEXT:    andi a1, a0, 64
+; RV32-NEXT:    beqz a1, .LBB107_7
+; RV32-NEXT:  .LBB107_15: # %cond.load16
+; RV32-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
+; RV32-NEXT:    vslidedown.vi v12, v10, 6
+; RV32-NEXT:    vmv.x.s a1, v12
+; RV32-NEXT:    lbu a2, 1(a1)
+; RV32-NEXT:    lbu a1, 0(a1)
+; RV32-NEXT:    slli a2, a2, 8
+; RV32-NEXT:    or a1, a2, a1
+; RV32-NEXT:    vmv.s.x v9, a1
+; RV32-NEXT:    vsetivli zero, 7, e16, m1, tu, ma
+; RV32-NEXT:    vslideup.vi v8, v9, 6
+; RV32-NEXT:    andi a0, a0, -128
+; RV32-NEXT:    beqz a0, .LBB107_8
+; RV32-NEXT:  .LBB107_16: # %cond.load19
+; RV32-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
+; RV32-NEXT:    vslidedown.vi v10, v10, 7
+; RV32-NEXT:    vmv.x.s a0, v10
+; RV32-NEXT:    lbu a1, 1(a0)
+; RV32-NEXT:    lbu a0, 0(a0)
+; RV32-NEXT:    slli a1, a1, 8
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    vmv.s.x v9, a0
+; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; RV32-NEXT:    vslideup.vi v8, v9, 7
+; RV32-NEXT:    ret
 ;
 ; RV64V-LABEL: mgather_strided_unaligned:
 ; RV64V:       # %bb.0:
@@ -13199,7 +13199,7 @@ define <8 x i16> @mgather_strided_unaligned(ptr %base) {
 ; RV64V-NEXT:    vid.v v12
 ; RV64V-NEXT:    vsll.vi v12, v12, 2
 ; RV64V-NEXT:    vadd.vx v12, v12, a0
-; RV64V-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
+; RV64V-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV64V-NEXT:    vmv.x.s a0, v8
 ; RV64V-NEXT:    # implicit-def: $v8
 ; RV64V-NEXT:    beqz zero, .LBB107_11
@@ -13263,13 +13263,13 @@ define <8 x i16> @mgather_strided_unaligned(ptr %base) {
 ; RV64V-NEXT:    addi sp, sp, 320
 ; RV64V-NEXT:    ret
 ; RV64V-NEXT:  .LBB107_11: # %cond.load
-; RV64V-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
+; RV64V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
 ; RV64V-NEXT:    vmv.x.s a1, v12
 ; RV64V-NEXT:    lbu a2, 1(a1)
 ; RV64V-NEXT:    lbu a1, 0(a1)
 ; RV64V-NEXT:    slli a2, a2, 8
 ; RV64V-NEXT:    or a1, a2, a1
-; RV64V-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; RV64V-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
 ; RV64V-NEXT:    vmv.v.x v8, a1
 ; RV64V-NEXT:    andi a1, a0, 2
 ; RV64V-NEXT:    beqz a1, .LBB107_2
@@ -13344,142 +13344,6 @@ define <8 x i16> @mgather_strided_unaligned(ptr %base) {
 ; RV64V-NEXT:    bnez a0, .LBB107_9
 ; RV64V-NEXT:    j .LBB107_10
 ;
-; RV32ZVE32F-LABEL: mgather_strided_unaligned:
-; RV32ZVE32F:       # %bb.0:
-; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
-; RV32ZVE32F-NEXT:    vmset.m v8
-; RV32ZVE32F-NEXT:    vid.v v10
-; RV32ZVE32F-NEXT:    vsll.vi v10, v10, 2
-; RV32ZVE32F-NEXT:    vadd.vx v10, v10, a0
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
-; RV32ZVE32F-NEXT:    vmv.x.s a0, v8
-; RV32ZVE32F-NEXT:    # implicit-def: $v8
-; RV32ZVE32F-NEXT:    beqz zero, .LBB107_9
-; RV32ZVE32F-NEXT:  # %bb.1: # %else
-; RV32ZVE32F-NEXT:    andi a1, a0, 2
-; RV32ZVE32F-NEXT:    bnez a1, .LBB107_10
-; RV32ZVE32F-NEXT:  .LBB107_2: # %else2
-; RV32ZVE32F-NEXT:    andi a1, a0, 4
-; RV32ZVE32F-NEXT:    bnez a1, .LBB107_11
-; RV32ZVE32F-NEXT:  .LBB107_3: # %else5
-; RV32ZVE32F-NEXT:    andi a1, a0, 8
-; RV32ZVE32F-NEXT:    bnez a1, .LBB107_12
-; RV32ZVE32F-NEXT:  .LBB107_4: # %else8
-; RV32ZVE32F-NEXT:    andi a1, a0, 16
-; RV32ZVE32F-NEXT:    bnez a1, .LBB107_13
-; RV32ZVE32F-NEXT:  .LBB107_5: # %else11
-; RV32ZVE32F-NEXT:    andi a1, a0, 32
-; RV32ZVE32F-NEXT:    bnez a1, .LBB107_14
-; RV32ZVE32F-NEXT:  .LBB107_6: # %else14
-; RV32ZVE32F-NEXT:    andi a1, a0, 64
-; RV32ZVE32F-NEXT:    bnez a1, .LBB107_15
-; RV32ZVE32F-NEXT:  .LBB107_7: # %else17
-; RV32ZVE32F-NEXT:    andi a0, a0, -128
-; RV32ZVE32F-NEXT:    bnez a0, .LBB107_16
-; RV32ZVE32F-NEXT:  .LBB107_8: # %else20
-; RV32ZVE32F-NEXT:    ret
-; RV32ZVE32F-NEXT:  .LBB107_9: # %cond.load
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
-; RV32ZVE32F-NEXT:    vmv.x.s a1, v10
-; RV32ZVE32F-NEXT:    lbu a2, 1(a1)
-; RV32ZVE32F-NEXT:    lbu a1, 0(a1)
-; RV32ZVE32F-NEXT:    slli a2, a2, 8
-; RV32ZVE32F-NEXT:    or a1, a2, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32ZVE32F-NEXT:    vmv.v.x v8, a1
-; RV32ZVE32F-NEXT:    andi a1, a0, 2
-; RV32ZVE32F-NEXT:    beqz a1, .LBB107_2
-; RV32ZVE32F-NEXT:  .LBB107_10: # %cond.load1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32ZVE32F-NEXT:    vslidedown.vi v9, v10, 1
-; RV32ZVE32F-NEXT:    vmv.x.s a1, v9
-; RV32ZVE32F-NEXT:    lbu a2, 1(a1)
-; RV32ZVE32F-NEXT:    lbu a1, 0(a1)
-; RV32ZVE32F-NEXT:    slli a2, a2, 8
-; RV32ZVE32F-NEXT:    or a1, a2, a1
-; RV32ZVE32F-NEXT:    vmv.s.x v9, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 2, e16, m1, tu, ma
-; RV32ZVE32F-NEXT:    vslideup.vi v8, v9, 1
-; RV32ZVE32F-NEXT:    andi a1, a0, 4
-; RV32ZVE32F-NEXT:    beqz a1, .LBB107_3
-; RV32ZVE32F-NEXT:  .LBB107_11: # %cond.load4
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32ZVE32F-NEXT:    vslidedown.vi v9, v10, 2
-; RV32ZVE32F-NEXT:    vmv.x.s a1, v9
-; RV32ZVE32F-NEXT:    lbu a2, 1(a1)
-; RV32ZVE32F-NEXT:    lbu a1, 0(a1)
-; RV32ZVE32F-NEXT:    slli a2, a2, 8
-; RV32ZVE32F-NEXT:    or a1, a2, a1
-; RV32ZVE32F-NEXT:    vmv.s.x v9, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 3, e16, m1, tu, ma
-; RV32ZVE32F-NEXT:    vslideup.vi v8, v9, 2
-; RV32ZVE32F-NEXT:    andi a1, a0, 8
-; RV32ZVE32F-NEXT:    beqz a1, .LBB107_4
-; RV32ZVE32F-NEXT:  .LBB107_12: # %cond.load7
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32ZVE32F-NEXT:    vslidedown.vi v9, v10, 3
-; RV32ZVE32F-NEXT:    vmv.x.s a1, v9
-; RV32ZVE32F-NEXT:    lbu a2, 1(a1)
-; RV32ZVE32F-NEXT:    lbu a1, 0(a1)
-; RV32ZVE32F-NEXT:    slli a2, a2, 8
-; RV32ZVE32F-NEXT:    or a1, a2, a1
-; RV32ZVE32F-NEXT:    vmv.s.x v9, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 4, e16, m1, tu, ma
-; RV32ZVE32F-NEXT:    vslideup.vi v8, v9, 3
-; RV32ZVE32F-NEXT:    andi a1, a0, 16
-; RV32ZVE32F-NEXT:    beqz a1, .LBB107_5
-; RV32ZVE32F-NEXT:  .LBB107_13: # %cond.load10
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
-; RV32ZVE32F-NEXT:    vslidedown.vi v12, v10, 4
-; RV32ZVE32F-NEXT:    vmv.x.s a1, v12
-; RV32ZVE32F-NEXT:    lbu a2, 1(a1)
-; RV32ZVE32F-NEXT:    lbu a1, 0(a1)
-; RV32ZVE32F-NEXT:    slli a2, a2, 8
-; RV32ZVE32F-NEXT:    or a1, a2, a1
-; RV32ZVE32F-NEXT:    vmv.s.x v9, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 5, e16, m1, tu, ma
-; RV32ZVE32F-NEXT:    vslideup.vi v8, v9, 4
-; RV32ZVE32F-NEXT:    andi a1, a0, 32
-; RV32ZVE32F-NEXT:    beqz a1, .LBB107_6
-; RV32ZVE32F-NEXT:  .LBB107_14: # %cond.load13
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
-; RV32ZVE32F-NEXT:    vslidedown.vi v12, v10, 5
-; RV32ZVE32F-NEXT:    vmv.x.s a1, v12
-; RV32ZVE32F-NEXT:    lbu a2, 1(a1)
-; RV32ZVE32F-NEXT:    lbu a1, 0(a1)
-; RV32ZVE32F-NEXT:    slli a2, a2, 8
-; RV32ZVE32F-NEXT:    or a1, a2, a1
-; RV32ZVE32F-NEXT:    vmv.s.x v9, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 6, e16, m1, tu, ma
-; RV32ZVE32F-NEXT:    vslideup.vi v8, v9, 5
-; RV32ZVE32F-NEXT:    andi a1, a0, 64
-; RV32ZVE32F-NEXT:    beqz a1, .LBB107_7
-; RV32ZVE32F-NEXT:  .LBB107_15: # %cond.load16
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
-; RV32ZVE32F-NEXT:    vslidedown.vi v12, v10, 6
-; RV32ZVE32F-NEXT:    vmv.x.s a1, v12
-; RV32ZVE32F-NEXT:    lbu a2, 1(a1)
-; RV32ZVE32F-NEXT:    lbu a1, 0(a1)
-; RV32ZVE32F-NEXT:    slli a2, a2, 8
-; RV32ZVE32F-NEXT:    or a1, a2, a1
-; RV32ZVE32F-NEXT:    vmv.s.x v9, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 7, e16, m1, tu, ma
-; RV32ZVE32F-NEXT:    vslideup.vi v8, v9, 6
-; RV32ZVE32F-NEXT:    andi a0, a0, -128
-; RV32ZVE32F-NEXT:    beqz a0, .LBB107_8
-; RV32ZVE32F-NEXT:  .LBB107_16: # %cond.load19
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
-; RV32ZVE32F-NEXT:    vslidedown.vi v10, v10, 7
-; RV32ZVE32F-NEXT:    vmv.x.s a0, v10
-; RV32ZVE32F-NEXT:    lbu a1, 1(a0)
-; RV32ZVE32F-NEXT:    lbu a0, 0(a0)
-; RV32ZVE32F-NEXT:    slli a1, a1, 8
-; RV32ZVE32F-NEXT:    or a0, a1, a0
-; RV32ZVE32F-NEXT:    vmv.s.x v9, a0
-; RV32ZVE32F-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32ZVE32F-NEXT:    vslideup.vi v8, v9, 7
-; RV32ZVE32F-NEXT:    ret
-;
 ; RV64ZVE32F-LABEL: mgather_strided_unaligned:
 ; RV64ZVE32F:       # %bb.0:
 ; RV64ZVE32F-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
index ecc81cbaa503..0125c0256162 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
@@ -3151,7 +3151,7 @@ define void @mscatter_truemask_v4i64(<4 x i64> %val, <4 x ptr> %ptrs) {
 ; RV32ZVE32F-NEXT:  .LBB39_5: # %cond.store
 ; RV32ZVE32F-NEXT:    lw t0, 4(a0)
 ; RV32ZVE32F-NEXT:    lw a0, 0(a0)
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s t1, v8
 ; RV32ZVE32F-NEXT:    sw t0, 4(t1)
 ; RV32ZVE32F-NEXT:    sw a0, 0(t1)
@@ -3508,7 +3508,7 @@ define void @mscatter_baseidx_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8> %id
 ; RV32ZVE32F-NEXT:    vsext.vf4 v10, v8
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v0
 ; RV32ZVE32F-NEXT:    andi s1, a1, 1
 ; RV32ZVE32F-NEXT:    bnez s1, .LBB42_10
@@ -3548,7 +3548,7 @@ define void @mscatter_baseidx_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8> %id
 ; RV32ZVE32F-NEXT:  .LBB42_10: # %cond.store
 ; RV32ZVE32F-NEXT:    lw s1, 4(a0)
 ; RV32ZVE32F-NEXT:    lw a0, 0(a0)
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s s2, v8
 ; RV32ZVE32F-NEXT:    sw s1, 4(s2)
 ; RV32ZVE32F-NEXT:    sw a0, 0(s2)
@@ -3752,7 +3752,7 @@ define void @mscatter_baseidx_sext_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8
 ; RV32ZVE32F-NEXT:    vsext.vf4 v10, v8
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v0
 ; RV32ZVE32F-NEXT:    andi s1, a1, 1
 ; RV32ZVE32F-NEXT:    bnez s1, .LBB43_10
@@ -3792,7 +3792,7 @@ define void @mscatter_baseidx_sext_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8
 ; RV32ZVE32F-NEXT:  .LBB43_10: # %cond.store
 ; RV32ZVE32F-NEXT:    lw s1, 4(a0)
 ; RV32ZVE32F-NEXT:    lw a0, 0(a0)
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s s2, v8
 ; RV32ZVE32F-NEXT:    sw s1, 4(s2)
 ; RV32ZVE32F-NEXT:    sw a0, 0(s2)
@@ -3998,7 +3998,7 @@ define void @mscatter_baseidx_zext_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8
 ; RV32ZVE32F-NEXT:    vzext.vf4 v10, v8
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v0
 ; RV32ZVE32F-NEXT:    andi s1, a1, 1
 ; RV32ZVE32F-NEXT:    bnez s1, .LBB44_10
@@ -4038,7 +4038,7 @@ define void @mscatter_baseidx_zext_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8
 ; RV32ZVE32F-NEXT:  .LBB44_10: # %cond.store
 ; RV32ZVE32F-NEXT:    lw s1, 4(a0)
 ; RV32ZVE32F-NEXT:    lw a0, 0(a0)
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s s2, v8
 ; RV32ZVE32F-NEXT:    sw s1, 4(s2)
 ; RV32ZVE32F-NEXT:    sw a0, 0(s2)
@@ -4251,7 +4251,7 @@ define void @mscatter_baseidx_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i16> %
 ; RV32ZVE32F-NEXT:    vsext.vf2 v10, v8
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v0
 ; RV32ZVE32F-NEXT:    andi s1, a1, 1
 ; RV32ZVE32F-NEXT:    bnez s1, .LBB45_10
@@ -4291,7 +4291,7 @@ define void @mscatter_baseidx_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i16> %
 ; RV32ZVE32F-NEXT:  .LBB45_10: # %cond.store
 ; RV32ZVE32F-NEXT:    lw s1, 4(a0)
 ; RV32ZVE32F-NEXT:    lw a0, 0(a0)
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s s2, v8
 ; RV32ZVE32F-NEXT:    sw s1, 4(s2)
 ; RV32ZVE32F-NEXT:    sw a0, 0(s2)
@@ -4496,7 +4496,7 @@ define void @mscatter_baseidx_sext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i
 ; RV32ZVE32F-NEXT:    vsext.vf2 v10, v8
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v0
 ; RV32ZVE32F-NEXT:    andi s1, a1, 1
 ; RV32ZVE32F-NEXT:    bnez s1, .LBB46_10
@@ -4536,7 +4536,7 @@ define void @mscatter_baseidx_sext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i
 ; RV32ZVE32F-NEXT:  .LBB46_10: # %cond.store
 ; RV32ZVE32F-NEXT:    lw s1, 4(a0)
 ; RV32ZVE32F-NEXT:    lw a0, 0(a0)
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s s2, v8
 ; RV32ZVE32F-NEXT:    sw s1, 4(s2)
 ; RV32ZVE32F-NEXT:    sw a0, 0(s2)
@@ -4743,7 +4743,7 @@ define void @mscatter_baseidx_zext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i
 ; RV32ZVE32F-NEXT:    vzext.vf2 v10, v8
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v0
 ; RV32ZVE32F-NEXT:    andi s1, a1, 1
 ; RV32ZVE32F-NEXT:    bnez s1, .LBB47_10
@@ -4783,7 +4783,7 @@ define void @mscatter_baseidx_zext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i
 ; RV32ZVE32F-NEXT:  .LBB47_10: # %cond.store
 ; RV32ZVE32F-NEXT:    lw s1, 4(a0)
 ; RV32ZVE32F-NEXT:    lw a0, 0(a0)
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s s2, v8
 ; RV32ZVE32F-NEXT:    sw s1, 4(s2)
 ; RV32ZVE32F-NEXT:    sw a0, 0(s2)
@@ -4997,7 +4997,7 @@ define void @mscatter_baseidx_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i32> %
 ; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v8, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v0
 ; RV32ZVE32F-NEXT:    andi s1, a1, 1
 ; RV32ZVE32F-NEXT:    bnez s1, .LBB48_10
@@ -5037,7 +5037,7 @@ define void @mscatter_baseidx_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i32> %
 ; RV32ZVE32F-NEXT:  .LBB48_10: # %cond.store
 ; RV32ZVE32F-NEXT:    lw s1, 4(a0)
 ; RV32ZVE32F-NEXT:    lw a0, 0(a0)
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s s2, v8
 ; RV32ZVE32F-NEXT:    sw s1, 4(s2)
 ; RV32ZVE32F-NEXT:    sw a0, 0(s2)
@@ -5240,7 +5240,7 @@ define void @mscatter_baseidx_sext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
 ; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v8, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v0
 ; RV32ZVE32F-NEXT:    andi s1, a1, 1
 ; RV32ZVE32F-NEXT:    bnez s1, .LBB49_10
@@ -5280,7 +5280,7 @@ define void @mscatter_baseidx_sext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
 ; RV32ZVE32F-NEXT:  .LBB49_10: # %cond.store
 ; RV32ZVE32F-NEXT:    lw s1, 4(a0)
 ; RV32ZVE32F-NEXT:    lw a0, 0(a0)
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s s2, v8
 ; RV32ZVE32F-NEXT:    sw s1, 4(s2)
 ; RV32ZVE32F-NEXT:    sw a0, 0(s2)
@@ -5484,7 +5484,7 @@ define void @mscatter_baseidx_zext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
 ; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v8, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v0
 ; RV32ZVE32F-NEXT:    andi s1, a1, 1
 ; RV32ZVE32F-NEXT:    bnez s1, .LBB50_10
@@ -5524,7 +5524,7 @@ define void @mscatter_baseidx_zext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
 ; RV32ZVE32F-NEXT:  .LBB50_10: # %cond.store
 ; RV32ZVE32F-NEXT:    lw s1, 4(a0)
 ; RV32ZVE32F-NEXT:    lw a0, 0(a0)
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s s2, v8
 ; RV32ZVE32F-NEXT:    sw s1, 4(s2)
 ; RV32ZVE32F-NEXT:    sw a0, 0(s2)
@@ -5763,7 +5763,7 @@ define void @mscatter_baseidx_v8i64(<8 x i64> %val, ptr %base, <8 x i64> %idxs,
 ; RV32ZVE32F-NEXT:    vslide1down.vx v8, v8, s2
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v8, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a1
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v0
 ; RV32ZVE32F-NEXT:    andi a2, a1, 1
 ; RV32ZVE32F-NEXT:    bnez a2, .LBB51_10
@@ -5809,7 +5809,7 @@ define void @mscatter_baseidx_v8i64(<8 x i64> %val, ptr %base, <8 x i64> %idxs,
 ; RV32ZVE32F-NEXT:  .LBB51_10: # %cond.store
 ; RV32ZVE32F-NEXT:    lw a2, 4(a0)
 ; RV32ZVE32F-NEXT:    lw a0, 0(a0)
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s s2, v8
 ; RV32ZVE32F-NEXT:    sw a2, 4(s2)
 ; RV32ZVE32F-NEXT:    sw a0, 0(s2)
@@ -8352,7 +8352,7 @@ define void @mscatter_truemask_v4f64(<4 x double> %val, <4 x ptr> %ptrs) {
 ; RV32ZVE32F-NEXT:  .LBB78_4: # %else6
 ; RV32ZVE32F-NEXT:    ret
 ; RV32ZVE32F-NEXT:  .LBB78_5: # %cond.store
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v8
 ; RV32ZVE32F-NEXT:    fsd fa0, 0(a1)
 ; RV32ZVE32F-NEXT:    andi a1, a0, 2
@@ -8623,7 +8623,7 @@ define void @mscatter_baseidx_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x i8>
 ; RV32ZVE32F-NEXT:    vsext.vf4 v10, v8
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a0
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a0, v0
 ; RV32ZVE32F-NEXT:    andi a1, a0, 1
 ; RV32ZVE32F-NEXT:    bnez a1, .LBB81_9
@@ -8651,7 +8651,7 @@ define void @mscatter_baseidx_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x i8>
 ; RV32ZVE32F-NEXT:  .LBB81_8: # %else14
 ; RV32ZVE32F-NEXT:    ret
 ; RV32ZVE32F-NEXT:  .LBB81_9: # %cond.store
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v8
 ; RV32ZVE32F-NEXT:    fsd fa0, 0(a1)
 ; RV32ZVE32F-NEXT:    andi a1, a0, 2
@@ -8823,7 +8823,7 @@ define void @mscatter_baseidx_sext_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x
 ; RV32ZVE32F-NEXT:    vsext.vf4 v10, v8
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a0
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a0, v0
 ; RV32ZVE32F-NEXT:    andi a1, a0, 1
 ; RV32ZVE32F-NEXT:    bnez a1, .LBB82_9
@@ -8851,7 +8851,7 @@ define void @mscatter_baseidx_sext_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x
 ; RV32ZVE32F-NEXT:  .LBB82_8: # %else14
 ; RV32ZVE32F-NEXT:    ret
 ; RV32ZVE32F-NEXT:  .LBB82_9: # %cond.store
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v8
 ; RV32ZVE32F-NEXT:    fsd fa0, 0(a1)
 ; RV32ZVE32F-NEXT:    andi a1, a0, 2
@@ -9025,7 +9025,7 @@ define void @mscatter_baseidx_zext_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x
 ; RV32ZVE32F-NEXT:    vzext.vf4 v10, v8
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a0
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a0, v0
 ; RV32ZVE32F-NEXT:    andi a1, a0, 1
 ; RV32ZVE32F-NEXT:    bnez a1, .LBB83_9
@@ -9053,7 +9053,7 @@ define void @mscatter_baseidx_zext_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x
 ; RV32ZVE32F-NEXT:  .LBB83_8: # %else14
 ; RV32ZVE32F-NEXT:    ret
 ; RV32ZVE32F-NEXT:  .LBB83_9: # %cond.store
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v8
 ; RV32ZVE32F-NEXT:    fsd fa0, 0(a1)
 ; RV32ZVE32F-NEXT:    andi a1, a0, 2
@@ -9234,7 +9234,7 @@ define void @mscatter_baseidx_v8i16_v8f64(<8 x double> %val, ptr %base, <8 x i16
 ; RV32ZVE32F-NEXT:    vsext.vf2 v10, v8
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a0
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a0, v0
 ; RV32ZVE32F-NEXT:    andi a1, a0, 1
 ; RV32ZVE32F-NEXT:    bnez a1, .LBB84_9
@@ -9262,7 +9262,7 @@ define void @mscatter_baseidx_v8i16_v8f64(<8 x double> %val, ptr %base, <8 x i16
 ; RV32ZVE32F-NEXT:  .LBB84_8: # %else14
 ; RV32ZVE32F-NEXT:    ret
 ; RV32ZVE32F-NEXT:  .LBB84_9: # %cond.store
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v8
 ; RV32ZVE32F-NEXT:    fsd fa0, 0(a1)
 ; RV32ZVE32F-NEXT:    andi a1, a0, 2
@@ -9435,7 +9435,7 @@ define void @mscatter_baseidx_sext_v8i16_v8f64(<8 x double> %val, ptr %base, <8
 ; RV32ZVE32F-NEXT:    vsext.vf2 v10, v8
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a0
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a0, v0
 ; RV32ZVE32F-NEXT:    andi a1, a0, 1
 ; RV32ZVE32F-NEXT:    bnez a1, .LBB85_9
@@ -9463,7 +9463,7 @@ define void @mscatter_baseidx_sext_v8i16_v8f64(<8 x double> %val, ptr %base, <8
 ; RV32ZVE32F-NEXT:  .LBB85_8: # %else14
 ; RV32ZVE32F-NEXT:    ret
 ; RV32ZVE32F-NEXT:  .LBB85_9: # %cond.store
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v8
 ; RV32ZVE32F-NEXT:    fsd fa0, 0(a1)
 ; RV32ZVE32F-NEXT:    andi a1, a0, 2
@@ -9638,7 +9638,7 @@ define void @mscatter_baseidx_zext_v8i16_v8f64(<8 x double> %val, ptr %base, <8
 ; RV32ZVE32F-NEXT:    vzext.vf2 v10, v8
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v10, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a0
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a0, v0
 ; RV32ZVE32F-NEXT:    andi a1, a0, 1
 ; RV32ZVE32F-NEXT:    bnez a1, .LBB86_9
@@ -9666,7 +9666,7 @@ define void @mscatter_baseidx_zext_v8i16_v8f64(<8 x double> %val, ptr %base, <8
 ; RV32ZVE32F-NEXT:  .LBB86_8: # %else14
 ; RV32ZVE32F-NEXT:    ret
 ; RV32ZVE32F-NEXT:  .LBB86_9: # %cond.store
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v8
 ; RV32ZVE32F-NEXT:    fsd fa0, 0(a1)
 ; RV32ZVE32F-NEXT:    andi a1, a0, 2
@@ -9848,7 +9848,7 @@ define void @mscatter_baseidx_v8i32_v8f64(<8 x double> %val, ptr %base, <8 x i32
 ; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v8, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a0
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a0, v0
 ; RV32ZVE32F-NEXT:    andi a1, a0, 1
 ; RV32ZVE32F-NEXT:    bnez a1, .LBB87_9
@@ -9876,7 +9876,7 @@ define void @mscatter_baseidx_v8i32_v8f64(<8 x double> %val, ptr %base, <8 x i32
 ; RV32ZVE32F-NEXT:  .LBB87_8: # %else14
 ; RV32ZVE32F-NEXT:    ret
 ; RV32ZVE32F-NEXT:  .LBB87_9: # %cond.store
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v8
 ; RV32ZVE32F-NEXT:    fsd fa0, 0(a1)
 ; RV32ZVE32F-NEXT:    andi a1, a0, 2
@@ -10047,7 +10047,7 @@ define void @mscatter_baseidx_sext_v8i32_v8f64(<8 x double> %val, ptr %base, <8
 ; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v8, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a0
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a0, v0
 ; RV32ZVE32F-NEXT:    andi a1, a0, 1
 ; RV32ZVE32F-NEXT:    bnez a1, .LBB88_9
@@ -10075,7 +10075,7 @@ define void @mscatter_baseidx_sext_v8i32_v8f64(<8 x double> %val, ptr %base, <8
 ; RV32ZVE32F-NEXT:  .LBB88_8: # %else14
 ; RV32ZVE32F-NEXT:    ret
 ; RV32ZVE32F-NEXT:  .LBB88_9: # %cond.store
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v8
 ; RV32ZVE32F-NEXT:    fsd fa0, 0(a1)
 ; RV32ZVE32F-NEXT:    andi a1, a0, 2
@@ -10247,7 +10247,7 @@ define void @mscatter_baseidx_zext_v8i32_v8f64(<8 x double> %val, ptr %base, <8
 ; RV32ZVE32F-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v8, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a0
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a0, v0
 ; RV32ZVE32F-NEXT:    andi a1, a0, 1
 ; RV32ZVE32F-NEXT:    bnez a1, .LBB89_9
@@ -10275,7 +10275,7 @@ define void @mscatter_baseidx_zext_v8i32_v8f64(<8 x double> %val, ptr %base, <8
 ; RV32ZVE32F-NEXT:  .LBB89_8: # %else14
 ; RV32ZVE32F-NEXT:    ret
 ; RV32ZVE32F-NEXT:  .LBB89_9: # %cond.store
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v8
 ; RV32ZVE32F-NEXT:    fsd fa0, 0(a1)
 ; RV32ZVE32F-NEXT:    andi a1, a0, 2
@@ -10470,7 +10470,7 @@ define void @mscatter_baseidx_v8f64(<8 x double> %val, ptr %base, <8 x i64> %idx
 ; RV32ZVE32F-NEXT:    vslide1down.vx v8, v8, a2
 ; RV32ZVE32F-NEXT:    vsll.vi v8, v8, 3
 ; RV32ZVE32F-NEXT:    vadd.vx v8, v8, a0
-; RV32ZVE32F-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a0, v0
 ; RV32ZVE32F-NEXT:    andi a1, a0, 1
 ; RV32ZVE32F-NEXT:    bnez a1, .LBB90_9
@@ -10498,7 +10498,7 @@ define void @mscatter_baseidx_v8f64(<8 x double> %val, ptr %base, <8 x i64> %idx
 ; RV32ZVE32F-NEXT:  .LBB90_8: # %else14
 ; RV32ZVE32F-NEXT:    ret
 ; RV32ZVE32F-NEXT:  .LBB90_9: # %cond.store
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32ZVE32F-NEXT:    vmv.x.s a1, v8
 ; RV32ZVE32F-NEXT:    fsd fa0, 0(a1)
 ; RV32ZVE32F-NEXT:    andi a1, a0, 2
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
index 3f6aa72bc2e3..95a4c9a249e7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
@@ -306,7 +306,7 @@ define float @vreduce_ord_fwadd_v1f32(ptr %x, float %s) {
 ; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
 ; CHECK-NEXT:    vfwredosum.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <1 x half>, ptr %x
@@ -353,7 +353,7 @@ define float @vreduce_fwadd_v2f32(ptr %x, float %s) {
 ; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
 ; CHECK-NEXT:    vfwredusum.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <2 x half>, ptr %x
@@ -370,7 +370,7 @@ define float @vreduce_ord_fwadd_v2f32(ptr %x, float %s) {
 ; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
 ; CHECK-NEXT:    vfwredosum.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <2 x half>, ptr %x
@@ -481,7 +481,7 @@ define float @vreduce_fwadd_v8f32(ptr %x, float %s) {
 ; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
 ; CHECK-NEXT:    vfwredusum.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <8 x half>, ptr %x
@@ -498,7 +498,7 @@ define float @vreduce_ord_fwadd_v8f32(ptr %x, float %s) {
 ; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
 ; CHECK-NEXT:    vfwredosum.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <8 x half>, ptr %x
@@ -545,7 +545,7 @@ define float @vreduce_fwadd_v16f32(ptr %x, float %s) {
 ; CHECK-NEXT:    vfmv.s.f v10, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
 ; CHECK-NEXT:    vfwredusum.vs v8, v8, v10
-; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <16 x half>, ptr %x
@@ -562,7 +562,7 @@ define float @vreduce_ord_fwadd_v16f32(ptr %x, float %s) {
 ; CHECK-NEXT:    vfmv.s.f v10, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
 ; CHECK-NEXT:    vfwredosum.vs v8, v8, v10
-; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <16 x half>, ptr %x
@@ -612,7 +612,7 @@ define float @vreduce_fwadd_v32f32(ptr %x, float %s) {
 ; CHECK-NEXT:    vfmv.s.f v12, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
 ; CHECK-NEXT:    vfwredusum.vs v8, v8, v12
-; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <32 x half>, ptr %x
@@ -630,7 +630,7 @@ define float @vreduce_ord_fwadd_v32f32(ptr %x, float %s) {
 ; CHECK-NEXT:    vfmv.s.f v12, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
 ; CHECK-NEXT:    vfwredosum.vs v8, v8, v12
-; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <32 x half>, ptr %x
@@ -713,7 +713,7 @@ define float @vreduce_ord_fwadd_v64f32(ptr %x, float %s) {
 ; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
 ; CHECK-NEXT:    vfwredosum.vs v8, v8, v12
 ; CHECK-NEXT:    vfwredosum.vs v8, v16, v8
-; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <64 x half>, ptr %x
@@ -886,7 +886,7 @@ define double @vreduce_fwadd_v4f64(ptr %x, double %s) {
 ; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
 ; CHECK-NEXT:    vfwredusum.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <4 x float>, ptr %x
@@ -903,7 +903,7 @@ define double @vreduce_ord_fwadd_v4f64(ptr %x, double %s) {
 ; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
 ; CHECK-NEXT:    vfwredosum.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <4 x float>, ptr %x
@@ -950,7 +950,7 @@ define double @vreduce_fwadd_v8f64(ptr %x, double %s) {
 ; CHECK-NEXT:    vfmv.s.f v10, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; CHECK-NEXT:    vfwredusum.vs v8, v8, v10
-; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <8 x float>, ptr %x
@@ -967,7 +967,7 @@ define double @vreduce_ord_fwadd_v8f64(ptr %x, double %s) {
 ; CHECK-NEXT:    vfmv.s.f v10, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; CHECK-NEXT:    vfwredosum.vs v8, v8, v10
-; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <8 x float>, ptr %x
@@ -1014,7 +1014,7 @@ define double @vreduce_fwadd_v16f64(ptr %x, double %s) {
 ; CHECK-NEXT:    vfmv.s.f v12, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
 ; CHECK-NEXT:    vfwredusum.vs v8, v8, v12
-; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <16 x float>, ptr %x
@@ -1031,7 +1031,7 @@ define double @vreduce_ord_fwadd_v16f64(ptr %x, double %s) {
 ; CHECK-NEXT:    vfmv.s.f v12, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
 ; CHECK-NEXT:    vfwredosum.vs v8, v8, v12
-; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <16 x float>, ptr %x
@@ -1110,7 +1110,7 @@ define double @vreduce_ord_fwadd_v32f64(ptr %x, double %s) {
 ; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
 ; CHECK-NEXT:    vfwredosum.vs v8, v8, v12
 ; CHECK-NEXT:    vfwredosum.vs v8, v16, v8
-; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %v = load <32 x float>, ptr %x
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
index 90ded1d70d5f..6c75c9b9c294 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
@@ -217,7 +217,7 @@ define i16 @vwreduce_add_v2i16(ptr %x) {
 ; CHECK-NEXT:    vmv.s.x v9, zero
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
 ; CHECK-NEXT:    vwredsum.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %v = load <2 x i8>, ptr %x
@@ -234,7 +234,7 @@ define i16 @vwreduce_uadd_v2i16(ptr %x) {
 ; CHECK-NEXT:    vmv.s.x v9, zero
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
 ; CHECK-NEXT:    vwredsumu.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %v = load <2 x i8>, ptr %x
@@ -267,7 +267,7 @@ define i16 @vwreduce_add_v4i16(ptr %x) {
 ; CHECK-NEXT:    vmv.s.x v9, zero
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
 ; CHECK-NEXT:    vwredsum.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %v = load <4 x i8>, ptr %x
@@ -284,7 +284,7 @@ define i16 @vwreduce_uadd_v4i16(ptr %x) {
 ; CHECK-NEXT:    vmv.s.x v9, zero
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
 ; CHECK-NEXT:    vwredsumu.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %v = load <4 x i8>, ptr %x
@@ -367,7 +367,7 @@ define i16 @vwreduce_add_v16i16(ptr %x) {
 ; CHECK-NEXT:    vmv.s.x v9, zero
 ; CHECK-NEXT:    vsetvli zero, zero, e8, m1, ta, ma
 ; CHECK-NEXT:    vwredsum.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %v = load <16 x i8>, ptr %x
@@ -384,7 +384,7 @@ define i16 @vwreduce_uadd_v16i16(ptr %x) {
 ; CHECK-NEXT:    vmv.s.x v9, zero
 ; CHECK-NEXT:    vsetvli zero, zero, e8, m1, ta, ma
 ; CHECK-NEXT:    vwredsumu.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %v = load <16 x i8>, ptr %x
@@ -419,7 +419,7 @@ define i16 @vwreduce_add_v32i16(ptr %x) {
 ; CHECK-NEXT:    vmv.s.x v10, zero
 ; CHECK-NEXT:    vsetvli zero, zero, e8, m2, ta, ma
 ; CHECK-NEXT:    vwredsum.vs v8, v8, v10
-; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %v = load <32 x i8>, ptr %x
@@ -437,7 +437,7 @@ define i16 @vwreduce_uadd_v32i16(ptr %x) {
 ; CHECK-NEXT:    vmv.s.x v10, zero
 ; CHECK-NEXT:    vsetvli zero, zero, e8, m2, ta, ma
 ; CHECK-NEXT:    vwredsumu.vs v8, v8, v10
-; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %v = load <32 x i8>, ptr %x
@@ -472,7 +472,7 @@ define i16 @vwreduce_add_v64i16(ptr %x) {
 ; CHECK-NEXT:    vmv.s.x v12, zero
 ; CHECK-NEXT:    vsetvli zero, zero, e8, m4, ta, ma
 ; CHECK-NEXT:    vwredsum.vs v8, v8, v12
-; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e16, m8, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %v = load <64 x i8>, ptr %x
@@ -490,7 +490,7 @@ define i16 @vwreduce_uadd_v64i16(ptr %x) {
 ; CHECK-NEXT:    vmv.s.x v12, zero
 ; CHECK-NEXT:    vsetvli zero, zero, e8, m4, ta, ma
 ; CHECK-NEXT:    vwredsumu.vs v8, v8, v12
-; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e16, m8, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %v = load <64 x i8>, ptr %x
@@ -629,7 +629,7 @@ define i32 @vwreduce_add_v2i32(ptr %x) {
 ; CHECK-NEXT:    vmv.s.x v9, zero
 ; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
 ; CHECK-NEXT:    vwredsum.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %v = load <2 x i16>, ptr %x
@@ -646,7 +646,7 @@ define i32 @vwreduce_uadd_v2i32(ptr %x) {
 ; CHECK-NEXT:    vmv.s.x v9, zero
 ; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
 ; CHECK-NEXT:    vwredsumu.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %v = load <2 x i16>, ptr %x
@@ -729,7 +729,7 @@ define i32 @vwreduce_add_v8i32(ptr %x) {
 ; CHECK-NEXT:    vmv.s.x v9, zero
 ; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
 ; CHECK-NEXT:    vwredsum.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %v = load <8 x i16>, ptr %x
@@ -746,7 +746,7 @@ define i32 @vwreduce_uadd_v8i32(ptr %x) {
 ; CHECK-NEXT:    vmv.s.x v9, zero
 ; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
 ; CHECK-NEXT:    vwredsumu.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %v = load <8 x i16>, ptr %x
@@ -779,7 +779,7 @@ define i32 @vwreduce_add_v16i32(ptr %x) {
 ; CHECK-NEXT:    vmv.s.x v10, zero
 ; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
 ; CHECK-NEXT:    vwredsum.vs v8, v8, v10
-; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %v = load <16 x i16>, ptr %x
@@ -796,7 +796,7 @@ define i32 @vwreduce_uadd_v16i32(ptr %x) {
 ; CHECK-NEXT:    vmv.s.x v10, zero
 ; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
 ; CHECK-NEXT:    vwredsumu.vs v8, v8, v10
-; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %v = load <16 x i16>, ptr %x
@@ -831,7 +831,7 @@ define i32 @vwreduce_add_v32i32(ptr %x) {
 ; CHECK-NEXT:    vmv.s.x v12, zero
 ; CHECK-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
 ; CHECK-NEXT:    vwredsum.vs v8, v8, v12
-; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %v = load <32 x i16>, ptr %x
@@ -849,7 +849,7 @@ define i32 @vwreduce_uadd_v32i32(ptr %x) {
 ; CHECK-NEXT:    vmv.s.x v12, zero
 ; CHECK-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
 ; CHECK-NEXT:    vwredsumu.vs v8, v8, v12
-; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %v = load <32 x i16>, ptr %x
@@ -1138,7 +1138,7 @@ define i64 @vwreduce_add_v4i64(ptr %x) {
 ; RV64-NEXT:    vmv.s.x v9, zero
 ; RV64-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
 ; RV64-NEXT:    vwredsum.vs v8, v8, v9
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
 ; RV64-NEXT:    vmv.x.s a0, v8
 ; RV64-NEXT:    ret
   %v = load <4 x i32>, ptr %x
@@ -1169,7 +1169,7 @@ define i64 @vwreduce_uadd_v4i64(ptr %x) {
 ; RV64-NEXT:    vmv.s.x v9, zero
 ; RV64-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
 ; RV64-NEXT:    vwredsumu.vs v8, v8, v9
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
 ; RV64-NEXT:    vmv.x.s a0, v8
 ; RV64-NEXT:    ret
   %v = load <4 x i32>, ptr %x
@@ -1229,7 +1229,7 @@ define i64 @vwreduce_add_v8i64(ptr %x) {
 ; RV64-NEXT:    vmv.s.x v10, zero
 ; RV64-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV64-NEXT:    vwredsum.vs v8, v8, v10
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
 ; RV64-NEXT:    vmv.x.s a0, v8
 ; RV64-NEXT:    ret
   %v = load <8 x i32>, ptr %x
@@ -1260,7 +1260,7 @@ define i64 @vwreduce_uadd_v8i64(ptr %x) {
 ; RV64-NEXT:    vmv.s.x v10, zero
 ; RV64-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV64-NEXT:    vwredsumu.vs v8, v8, v10
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
 ; RV64-NEXT:    vmv.x.s a0, v8
 ; RV64-NEXT:    ret
   %v = load <8 x i32>, ptr %x
@@ -1320,7 +1320,7 @@ define i64 @vwreduce_add_v16i64(ptr %x) {
 ; RV64-NEXT:    vmv.s.x v12, zero
 ; RV64-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
 ; RV64-NEXT:    vwredsum.vs v8, v8, v12
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
 ; RV64-NEXT:    vmv.x.s a0, v8
 ; RV64-NEXT:    ret
   %v = load <16 x i32>, ptr %x
@@ -1351,7 +1351,7 @@ define i64 @vwreduce_uadd_v16i64(ptr %x) {
 ; RV64-NEXT:    vmv.s.x v12, zero
 ; RV64-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
 ; RV64-NEXT:    vwredsumu.vs v8, v8, v12
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
 ; RV64-NEXT:    vmv.x.s a0, v8
 ; RV64-NEXT:    ret
   %v = load <16 x i32>, ptr %x
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
index 398ac7077237..5b6b2299859c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
@@ -278,9 +278,9 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x ptr> %ptrs, <4 x i1> %m)
 ; RV32-SLOW-NEXT:  .LBB6_4: # %else6
 ; RV32-SLOW-NEXT:    ret
 ; RV32-SLOW-NEXT:  .LBB6_5: # %cond.store
-; RV32-SLOW-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma
+; RV32-SLOW-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
 ; RV32-SLOW-NEXT:    vmv.x.s a1, v8
-; RV32-SLOW-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32-SLOW-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
 ; RV32-SLOW-NEXT:    vmv.x.s a2, v9
 ; RV32-SLOW-NEXT:    sb a1, 0(a2)
 ; RV32-SLOW-NEXT:    srli a1, a1, 8
@@ -341,9 +341,9 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x ptr> %ptrs, <4 x i1> %m)
 ; RV64-SLOW-NEXT:  .LBB6_4: # %else6
 ; RV64-SLOW-NEXT:    ret
 ; RV64-SLOW-NEXT:  .LBB6_5: # %cond.store
-; RV64-SLOW-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma
+; RV64-SLOW-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
 ; RV64-SLOW-NEXT:    vmv.x.s a1, v8
-; RV64-SLOW-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; RV64-SLOW-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
 ; RV64-SLOW-NEXT:    vmv.x.s a2, v10
 ; RV64-SLOW-NEXT:    srli a3, a1, 8
 ; RV64-SLOW-NEXT:    sb a3, 1(a2)
@@ -506,7 +506,7 @@ define void @masked_load_v2i32_align1(ptr %a, <2 x i32> %m, ptr %res_ptr) nounwi
 ; RV32-SLOW-NEXT:    slli a6, a6, 24
 ; RV32-SLOW-NEXT:    or a4, a6, a5
 ; RV32-SLOW-NEXT:    or a3, a4, a3
-; RV32-SLOW-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
+; RV32-SLOW-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
 ; RV32-SLOW-NEXT:    vmv.v.x v8, a3
 ; RV32-SLOW-NEXT:  .LBB8_2: # %else
 ; RV32-SLOW-NEXT:    andi a2, a2, 2
@@ -522,11 +522,11 @@ define void @masked_load_v2i32_align1(ptr %a, <2 x i32> %m, ptr %res_ptr) nounwi
 ; RV32-SLOW-NEXT:    slli a0, a0, 24
 ; RV32-SLOW-NEXT:    or a0, a0, a4
 ; RV32-SLOW-NEXT:    or a0, a0, a2
-; RV32-SLOW-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
+; RV32-SLOW-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
 ; RV32-SLOW-NEXT:    vmv.s.x v9, a0
 ; RV32-SLOW-NEXT:    vslideup.vi v8, v9, 1
 ; RV32-SLOW-NEXT:  .LBB8_4: # %else2
-; RV32-SLOW-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
+; RV32-SLOW-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
 ; RV32-SLOW-NEXT:    vse32.v v8, (a1)
 ; RV32-SLOW-NEXT:    ret
 ;
@@ -550,7 +550,7 @@ define void @masked_load_v2i32_align1(ptr %a, <2 x i32> %m, ptr %res_ptr) nounwi
 ; RV64-SLOW-NEXT:    slli a6, a6, 24
 ; RV64-SLOW-NEXT:    or a4, a6, a5
 ; RV64-SLOW-NEXT:    or a3, a4, a3
-; RV64-SLOW-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
+; RV64-SLOW-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
 ; RV64-SLOW-NEXT:    vmv.v.x v8, a3
 ; RV64-SLOW-NEXT:  .LBB8_2: # %else
 ; RV64-SLOW-NEXT:    andi a2, a2, 2
@@ -566,11 +566,11 @@ define void @masked_load_v2i32_align1(ptr %a, <2 x i32> %m, ptr %res_ptr) nounwi
 ; RV64-SLOW-NEXT:    slli a0, a0, 24
 ; RV64-SLOW-NEXT:    or a0, a0, a4
 ; RV64-SLOW-NEXT:    or a0, a0, a2
-; RV64-SLOW-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
+; RV64-SLOW-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
 ; RV64-SLOW-NEXT:    vmv.s.x v9, a0
 ; RV64-SLOW-NEXT:    vslideup.vi v8, v9, 1
 ; RV64-SLOW-NEXT:  .LBB8_4: # %else2
-; RV64-SLOW-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
+; RV64-SLOW-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
 ; RV64-SLOW-NEXT:    vse32.v v8, (a1)
 ; RV64-SLOW-NEXT:    ret
 ;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
index c5245451dc44..2546ec95a007 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
@@ -115,7 +115,7 @@ define float @vreduce_fwadd_nxv1f32(<vscale x 1 x half> %v, float %s) {
 ; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
 ; CHECK-NEXT:    vfwredusum.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %e = fpext <vscale x 1 x half> %v to <vscale x 1 x float>
@@ -130,7 +130,7 @@ define float @vreduce_ord_fwadd_nxv1f32(<vscale x 1 x half> %v, float %s) {
 ; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
 ; CHECK-NEXT:    vfwredosum.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %e = fpext <vscale x 1 x half> %v to <vscale x 1 x float>
@@ -227,7 +227,7 @@ define float @vreduce_fwadd_nxv4f32(<vscale x 4 x half> %v, float %s) {
 ; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
 ; CHECK-NEXT:    vfwredusum.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %e = fpext <vscale x 4 x half> %v to <vscale x 4 x float>
@@ -242,7 +242,7 @@ define float @vreduce_ord_fwadd_nxv4f32(<vscale x 4 x half> %v, float %s) {
 ; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
 ; CHECK-NEXT:    vfwredosum.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %e = fpext <vscale x 4 x half> %v to <vscale x 4 x float>
@@ -339,7 +339,7 @@ define double @vreduce_fwadd_nxv2f64(<vscale x 2 x float> %v, double %s) {
 ; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
 ; CHECK-NEXT:    vfwredusum.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %e = fpext <vscale x 2 x float> %v to <vscale x 2 x double>
@@ -354,7 +354,7 @@ define double @vreduce_ord_fwadd_nxv2f64(<vscale x 2 x float> %v, double %s) {
 ; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
 ; CHECK-NEXT:    vfwredosum.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %e = fpext <vscale x 2 x float> %v to <vscale x 2 x double>
@@ -395,7 +395,7 @@ define double @vreduce_fwadd_nxv4f64(<vscale x 4 x float> %v, double %s) {
 ; CHECK-NEXT:    vfmv.s.f v10, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
 ; CHECK-NEXT:    vfwredusum.vs v8, v8, v10
-; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %e = fpext <vscale x 4 x float> %v to <vscale x 4 x double>
@@ -410,7 +410,7 @@ define double @vreduce_ord_fwadd_nxv4f64(<vscale x 4 x float> %v, double %s) {
 ; CHECK-NEXT:    vfmv.s.f v10, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
 ; CHECK-NEXT:    vfwredosum.vs v8, v8, v10
-; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %e = fpext <vscale x 4 x float> %v to <vscale x 4 x double>
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
index 9f7b64c79616..290fb6daedd0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
@@ -1700,7 +1700,7 @@ define signext i64 @vwpreduce_add_nxv2i32(i64 signext %s, <vscale x 2 x i32> %v,
 ; RV64-NEXT:    vmv.s.x v9, a0
 ; RV64-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
 ; RV64-NEXT:    vwredsum.vs v9, v8, v9, v0.t
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
 ; RV64-NEXT:    vmv.x.s a0, v9
 ; RV64-NEXT:    ret
   %e = sext <vscale x 2 x i32> %v to <vscale x 2 x i64>
@@ -1734,7 +1734,7 @@ define signext i64 @vwpreduce_uadd_nxv2i32(i64 signext %s, <vscale x 2 x i32> %v
 ; RV64-NEXT:    vmv.s.x v9, a0
 ; RV64-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
 ; RV64-NEXT:    vwredsum.vs v9, v8, v9, v0.t
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
 ; RV64-NEXT:    vmv.x.s a0, v9
 ; RV64-NEXT:    ret
   %e = sext <vscale x 2 x i32> %v to <vscale x 2 x i64>
@@ -2040,7 +2040,7 @@ define signext i64 @vpwreduce_add_nxv4i32(i64 signext %s, <vscale x 4 x i32> %v,
 ; RV64-NEXT:    vmv.s.x v10, a0
 ; RV64-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
 ; RV64-NEXT:    vwredsum.vs v10, v8, v10, v0.t
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
 ; RV64-NEXT:    vmv.x.s a0, v10
 ; RV64-NEXT:    ret
   %e = sext <vscale x 4 x i32> %v to <vscale x 4 x i64>
@@ -2074,7 +2074,7 @@ define signext i64 @vpwreduce_uadd_nxv4i32(i64 signext %s, <vscale x 4 x i32> %v
 ; RV64-NEXT:    vmv.s.x v10, a0
 ; RV64-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
 ; RV64-NEXT:    vwredsumu.vs v10, v8, v10, v0.t
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
 ; RV64-NEXT:    vmv.x.s a0, v10
 ; RV64-NEXT:    ret
   %e = zext <vscale x 4 x i32> %v to <vscale x 4 x i64>
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
index 3f1892ede567..6e24d58f9695 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
@@ -343,7 +343,7 @@ define signext i16 @vwreduce_add_nxv1i8(<vscale x 1 x i8> %v) {
 ; CHECK-NEXT:    vmv.s.x v9, zero
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
 ; CHECK-NEXT:    vwredsum.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %e = sext <vscale x 1 x i8> %v to <vscale x 1 x i16>
@@ -358,7 +358,7 @@ define signext i16 @vwreduce_uadd_nxv1i8(<vscale x 1 x i8> %v) {
 ; CHECK-NEXT:    vmv.s.x v9, zero
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
 ; CHECK-NEXT:    vwredsum.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %e = sext <vscale x 1 x i8> %v to <vscale x 1 x i16>
@@ -479,7 +479,7 @@ define signext i16 @vwreduce_add_nxv2i8(<vscale x 2 x i8> %v) {
 ; CHECK-NEXT:    vmv.s.x v9, zero
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
 ; CHECK-NEXT:    vwredsum.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %e = sext <vscale x 2 x i8> %v to <vscale x 2 x i16>
@@ -494,7 +494,7 @@ define signext i16 @vwreduce_uadd_nxv2i8(<vscale x 2 x i8> %v) {
 ; CHECK-NEXT:    vmv.s.x v9, zero
 ; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
 ; CHECK-NEXT:    vwredsum.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %e = sext <vscale x 2 x i8> %v to <vscale x 2 x i16>
@@ -751,7 +751,7 @@ define signext i32 @vwreduce_add_nxv1i16(<vscale x 1 x i16> %v) {
 ; CHECK-NEXT:    vmv.s.x v9, zero
 ; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
 ; CHECK-NEXT:    vwredsum.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %e = sext <vscale x 1 x i16> %v to <vscale x 1 x i32>
@@ -766,7 +766,7 @@ define signext i32 @vwreduce_uadd_nxv1i16(<vscale x 1 x i16> %v) {
 ; CHECK-NEXT:    vmv.s.x v9, zero
 ; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
 ; CHECK-NEXT:    vwredsumu.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %e = zext <vscale x 1 x i16> %v to <vscale x 1 x i32>
@@ -1023,7 +1023,7 @@ define signext i32 @vwreduce_add_nxv4i16(<vscale x 4 x i16> %v) {
 ; CHECK-NEXT:    vmv.s.x v9, zero
 ; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
 ; CHECK-NEXT:    vwredsum.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %e = sext <vscale x 4 x i16> %v to <vscale x 4 x i32>
@@ -1038,7 +1038,7 @@ define signext i32 @vwreduce_uadd_nxv4i16(<vscale x 4 x i16> %v) {
 ; CHECK-NEXT:    vmv.s.x v9, zero
 ; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
 ; CHECK-NEXT:    vwredsumu.vs v8, v8, v9
-; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %e = zext <vscale x 4 x i16> %v to <vscale x 4 x i32>
@@ -1436,7 +1436,7 @@ define i64 @vwreduce_add_nxv2i32(<vscale x 2 x i32> %v) {
 ; RV64-NEXT:    vmv.s.x v9, zero
 ; RV64-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
 ; RV64-NEXT:    vwredsum.vs v8, v8, v9
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
 ; RV64-NEXT:    vmv.x.s a0, v8
 ; RV64-NEXT:    ret
   %e = sext <vscale x 2 x i32> %v to <vscale x 2 x i64>
@@ -1464,7 +1464,7 @@ define i64 @vwreduce_uadd_nxv2i32(<vscale x 2 x i32> %v) {
 ; RV64-NEXT:    vmv.s.x v9, zero
 ; RV64-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
 ; RV64-NEXT:    vwredsumu.vs v8, v8, v9
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
 ; RV64-NEXT:    vmv.x.s a0, v8
 ; RV64-NEXT:    ret
   %e = zext <vscale x 2 x i32> %v to <vscale x 2 x i64>
@@ -1688,7 +1688,7 @@ define i64 @vwreduce_add_nxv4i32(<vscale x 4 x i32> %v) {
 ; RV64-NEXT:    vmv.s.x v10, zero
 ; RV64-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
 ; RV64-NEXT:    vwredsum.vs v8, v8, v10
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
 ; RV64-NEXT:    vmv.x.s a0, v8
 ; RV64-NEXT:    ret
   %e = sext <vscale x 4 x i32> %v to <vscale x 4 x i64>
@@ -1716,7 +1716,7 @@ define i64 @vwreduce_uadd_nxv4i32(<vscale x 4 x i32> %v) {
 ; RV64-NEXT:    vmv.s.x v10, zero
 ; RV64-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
 ; RV64-NEXT:    vwredsumu.vs v8, v8, v10
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
 ; RV64-NEXT:    vmv.x.s a0, v8
 ; RV64-NEXT:    ret
   %e = zext <vscale x 4 x i32> %v to <vscale x 4 x i64>
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
index 4d0f640408dd..1114c7657c63 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
@@ -329,9 +329,8 @@ entry:
 define double @test17(i64 %avl, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
 ; CHECK-LABEL: test17:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a0, a0, e64, m1, ta, ma
-; CHECK-NEXT:    vfmv.f.s fa5, v8
 ; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT:    vfmv.f.s fa5, v8
 ; CHECK-NEXT:    vfadd.vv v8, v8, v9
 ; CHECK-NEXT:    vfmv.f.s fa4, v8
 ; CHECK-NEXT:    fadd.d fa0, fa5, fa4
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll
index 22eb2d8fb99a..bb49b9fd65d0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll
@@ -12,7 +12,7 @@ define i32 @illegal_preserve_vl(<vscale x 2 x i32> %a, <vscale x 4 x i64> %x, <v
 ; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
 ; CHECK-NEXT:    vadd.vv v12, v12, v12
 ; CHECK-NEXT:    vs4r.v v12, (a0)
-; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %index = add <vscale x 4 x i64> %x, %x
-- 
GitLab


From 6707b33b807a6c85b04197a718706251906a5b77 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke@igalia.com>
Date: Tue, 12 Dec 2023 17:30:18 +0900
Subject: [PATCH 235/349] [RISCV] Don't set AVL if only zeroness is demanded
 (#74049)

This refactors the logic in transferBefore so that we're moving in the
direction of "keep the existing Info, only change what is needed".

For the sake of review there are two commits in this PR: The former is
needed to make the latter an NFC commit. Neither introduce any test
diffs but the former is not technically NFC, hence why I did not
precommit it.

- [RISCV] Preserve AVL when previous info is ratio only in
transferBefore
- [RISCV] Don't change AVL if only zeroness is demanded. NFC
---
 llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 35 +++++++++++---------
 1 file changed, 19 insertions(+), 16 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index c9c6b2185403..723af1182cb7 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -1059,14 +1059,23 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
     return;
 
   const VSETVLIInfo PrevInfo = Info;
-  if (Info.hasSEWLMULRatioOnly() || !Info.isValid() || Info.isUnknown())
+  if (!Info.isValid() || Info.isUnknown())
     Info = NewInfo;
 
   DemandedFields Demanded = getDemanded(MI, MRI, ST);
   const VSETVLIInfo IncomingInfo =
       adjustIncoming(PrevInfo, NewInfo, Demanded, MRI);
 
-  if (Demanded.usedVL())
+  // If MI only demands that VL has the same zeroness, we only need to set the
+  // AVL if the zeroness differs.  This removes a vsetvli entirely if the types
+  // match or allows use of cheaper avl preserving variant if VLMAX doesn't
+  // change. If VLMAX might change, we couldn't use the 'vsetvli x0, x0, vtype"
+  // variant, so we avoid the transform to prevent extending live range of an
+  // avl register operand.
+  // TODO: We can probably relax this for immediates.
+  bool EquallyZero = IncomingInfo.hasEquallyZeroAVL(PrevInfo, *MRI) &&
+                     IncomingInfo.hasSameVLMAX(PrevInfo);
+  if (Demanded.VLAny || (Demanded.VLZeroness && !EquallyZero))
     Info.setAVL(IncomingInfo);
 
   Info.setVTYPE(
@@ -1079,6 +1088,14 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
           IncomingInfo.getTailAgnostic(),
       (Demanded.MaskPolicy ? IncomingInfo : Info).getMaskAgnostic() ||
           IncomingInfo.getMaskAgnostic());
+
+  // If we only knew the sew/lmul ratio previously, replace the VTYPE but keep
+  // the AVL.
+  if (Info.hasSEWLMULRatioOnly()) {
+    VSETVLIInfo RatiolessInfo = IncomingInfo;
+    RatiolessInfo.setAVL(Info);
+    Info = RatiolessInfo;
+  }
 }
 
 static VSETVLIInfo adjustIncoming(VSETVLIInfo PrevInfo, VSETVLIInfo NewInfo,
@@ -1097,20 +1114,6 @@ static VSETVLIInfo adjustIncoming(VSETVLIInfo PrevInfo, VSETVLIInfo NewInfo,
     Demanded.LMUL = true;
   }
 
-  // If we only demand VL zeroness (i.e. vmv.s.x and vmv.x.s), then there are
-  // only two behaviors, VL = 0 and VL > 0. We can discard the user requested
-  // AVL and just use the last one if we can prove it equally zero. This
-  // removes a vsetvli entirely if the types match or allows use of cheaper avl
-  // preserving variant if VLMAX doesn't change. If VLMAX might change, we
-  // couldn't use the 'vsetvli x0, x0, vtype" variant, so we avoid the transform
-  // to prevent extending live range of an avl register operand.
-  // TODO: We can probably relax this for immediates.
-  if (Demanded.VLZeroness && !Demanded.VLAny && PrevInfo.isValid() &&
-      PrevInfo.hasEquallyZeroAVL(Info, *MRI) && Info.hasSameVLMAX(PrevInfo)) {
-    Info.setAVL(PrevInfo);
-    Demanded.demandVL();
-  }
-
   return Info;
 }
 
-- 
GitLab


From c87eb63abfdb9142f90f4498b545a947d2824aef Mon Sep 17 00:00:00 2001
From: Luke Lau <luke@igalia.com>
Date: Tue, 12 Dec 2023 17:31:59 +0900
Subject: [PATCH 236/349] [RISCV] Move test to RVV directory. NFC

Just a nit, moving the test so that it gets picked up by
check-codegen-riscv-rvv since it contains vector code
---
 llvm/test/CodeGen/RISCV/{ => rvv}/65704-illegal-instruction.ll | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename llvm/test/CodeGen/RISCV/{ => rvv}/65704-illegal-instruction.ll (100%)

diff --git a/llvm/test/CodeGen/RISCV/65704-illegal-instruction.ll b/llvm/test/CodeGen/RISCV/rvv/65704-illegal-instruction.ll
similarity index 100%
rename from llvm/test/CodeGen/RISCV/65704-illegal-instruction.ll
rename to llvm/test/CodeGen/RISCV/rvv/65704-illegal-instruction.ll
-- 
GitLab


From 90d82412ea2103fe086a968c29e8ba4ea899381e Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Tue, 12 Dec 2023 09:41:54 +0100
Subject: [PATCH 237/349] [SCEV] Use loop guards when checking that RHS >=
 Start (#75039)

Loop guards tend to provide better results when it comes to reasoning
about ranges than isLoopEntryGuardedByCond(). See the test change for
the motivating case.

I have retained both the loop guard check and the implied cond based
check for now, though the latter only seems to impact a single test and
only via side effects (nowrap flag calculation) at that.
---
 llvm/lib/Analysis/ScalarEvolution.cpp            | 6 +++++-
 llvm/test/Analysis/ScalarEvolution/trip-count.ll | 6 +++---
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Analysis/ScalarEvolution.cpp b/llvm/lib/Analysis/ScalarEvolution.cpp
index 451ae73dbd60..580fe112fcd7 100644
--- a/llvm/lib/Analysis/ScalarEvolution.cpp
+++ b/llvm/lib/Analysis/ScalarEvolution.cpp
@@ -12910,7 +12910,11 @@ ScalarEvolution::howManyLessThans(const SCEV *LHS, const SCEV *RHS,
   if (!BECount) {
     auto canProveRHSGreaterThanEqualStart = [&]() {
       auto CondGE = IsSigned ? ICmpInst::ICMP_SGE : ICmpInst::ICMP_UGE;
-      if (isLoopEntryGuardedByCond(L, CondGE, OrigRHS, OrigStart))
+      const SCEV *GuardedRHS = applyLoopGuards(OrigRHS, L);
+      const SCEV *GuardedStart = applyLoopGuards(OrigStart, L);
+
+      if (isLoopEntryGuardedByCond(L, CondGE, OrigRHS, OrigStart) ||
+          isKnownPredicate(CondGE, GuardedRHS, GuardedStart))
         return true;
 
       // (RHS > Start - 1) implies RHS >= Start.
diff --git a/llvm/test/Analysis/ScalarEvolution/trip-count.ll b/llvm/test/Analysis/ScalarEvolution/trip-count.ll
index 22e49ebdbf4d..36b42c62dd39 100644
--- a/llvm/test/Analysis/ScalarEvolution/trip-count.ll
+++ b/llvm/test/Analysis/ScalarEvolution/trip-count.ll
@@ -127,10 +127,10 @@ leave:
 define void @non_zero_from_loop_guard(i16 %n) {
 ; CHECK-LABEL: 'non_zero_from_loop_guard'
 ; CHECK-NEXT:  Determining loop execution counts for: @non_zero_from_loop_guard
-; CHECK-NEXT:  Loop %loop: backedge-taken count is (-1 + (1 umax (%n /u 2)))<nsw>
+; CHECK-NEXT:  Loop %loop: backedge-taken count is (-1 + (%n /u 2))<nsw>
 ; CHECK-NEXT:  Loop %loop: constant max backedge-taken count is 32766
-; CHECK-NEXT:  Loop %loop: symbolic max backedge-taken count is (-1 + (1 umax (%n /u 2)))<nsw>
-; CHECK-NEXT:  Loop %loop: Predicated backedge-taken count is (-1 + (1 umax (%n /u 2)))<nsw>
+; CHECK-NEXT:  Loop %loop: symbolic max backedge-taken count is (-1 + (%n /u 2))<nsw>
+; CHECK-NEXT:  Loop %loop: Predicated backedge-taken count is (-1 + (%n /u 2))<nsw>
 ; CHECK-NEXT:   Predicates:
 ; CHECK-NEXT:  Loop %loop: Trip multiple is 1
 ;
-- 
GitLab


From 30e200b81e2feb1541d8578913d959a2c6e31762 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke@igalia.com>
Date: Tue, 12 Dec 2023 17:50:31 +0900
Subject: [PATCH 238/349] [RISCV] Remove forward declaration and unused
 argument. NFC

---
 llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 40 +++++++++-----------
 1 file changed, 17 insertions(+), 23 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 723af1182cb7..096d7ce0cb64 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -1040,9 +1040,23 @@ bool RISCVInsertVSETVLI::needVSETVLI(const MachineInstr &MI,
   return true;
 }
 
+// If we don't use LMUL or the SEW/LMUL ratio, then adjust LMUL so that we
+// maintain the SEW/LMUL ratio. This allows us to eliminate VL toggles in more
+// places.
 static VSETVLIInfo adjustIncoming(VSETVLIInfo PrevInfo, VSETVLIInfo NewInfo,
-                                  DemandedFields &Demanded,
-                                  const MachineRegisterInfo *MRI);
+                                  DemandedFields &Demanded) {
+  VSETVLIInfo Info = NewInfo;
+
+  if (!Demanded.LMUL && !Demanded.SEWLMULRatio && PrevInfo.isValid() &&
+      !PrevInfo.isUnknown()) {
+    if (auto NewVLMul = RISCVVType::getSameRatioLMUL(
+            PrevInfo.getSEW(), PrevInfo.getVLMUL(), Info.getSEW()))
+      Info.setVLMul(*NewVLMul);
+    Demanded.LMUL = true;
+  }
+
+  return Info;
+}
 
 // Given an incoming state reaching MI, minimally modifies that state so that it
 // is compatible with MI. The resulting state is guaranteed to be semantically
@@ -1063,8 +1077,7 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
     Info = NewInfo;
 
   DemandedFields Demanded = getDemanded(MI, MRI, ST);
-  const VSETVLIInfo IncomingInfo =
-      adjustIncoming(PrevInfo, NewInfo, Demanded, MRI);
+  const VSETVLIInfo IncomingInfo = adjustIncoming(PrevInfo, NewInfo, Demanded);
 
   // If MI only demands that VL has the same zeroness, we only need to set the
   // AVL if the zeroness differs.  This removes a vsetvli entirely if the types
@@ -1098,25 +1111,6 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
   }
 }
 
-static VSETVLIInfo adjustIncoming(VSETVLIInfo PrevInfo, VSETVLIInfo NewInfo,
-                                  DemandedFields &Demanded,
-                                  const MachineRegisterInfo *MRI) {
-  VSETVLIInfo Info = NewInfo;
-
-  // If we don't use LMUL or the SEW/LMUL ratio, then adjust LMUL so that we
-  // maintain the SEW/LMUL ratio. This allows us to eliminate VL toggles in more
-  // places.
-  if (!Demanded.LMUL && !Demanded.SEWLMULRatio && PrevInfo.isValid() &&
-      !PrevInfo.isUnknown()) {
-    if (auto NewVLMul = RISCVVType::getSameRatioLMUL(
-            PrevInfo.getSEW(), PrevInfo.getVLMUL(), Info.getSEW()))
-      Info.setVLMul(*NewVLMul);
-    Demanded.LMUL = true;
-  }
-
-  return Info;
-}
-
 // Given a state with which we evaluated MI (see transferBefore above for why
 // this might be different that the state MI requested), modify the state to
 // reflect the changes MI might make.
-- 
GitLab


From 4204b94264c6acf15bc790548644715485afa0f1 Mon Sep 17 00:00:00 2001
From: Adrian Kuegel <akuegel@google.com>
Date: Tue, 12 Dec 2023 08:55:36 +0000
Subject: [PATCH 239/349] [mlir][Bazel] Adjust for
 d5fb4c0f118b47db74233af2d99ae075e1dbe148

---
 .../llvm-project-overlay/mlir/BUILD.bazel     | 48 ++++++++++++++++++-
 1 file changed, 46 insertions(+), 2 deletions(-)

diff --git a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
index c831df20349e..d26299094bc8 100644
--- a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+++ b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
@@ -6149,6 +6149,32 @@ gentbl_cc_library(
     deps = [":NVVMOpsTdFiles"],
 )
 
+gentbl_cc_library(
+    name = "NVVMFromLLVMIRConversionsIncGen",
+    tbl_outs = [
+        (
+            ["-gen-intr-from-llvmir-conversions"],
+            "include/mlir/Dialect/LLVMIR/NVVMFromLLVMIRConversions.inc",
+        ),
+    ],
+    tblgen = ":mlir-tblgen",
+    td_file = "include/mlir/Dialect/LLVMIR/NVVMOps.td",
+    deps = [":NVVMOpsTdFiles"],
+)
+
+gentbl_cc_library(
+    name = "NVVMConvertibleLLVMIRIntrinsicsIncGen",
+    tbl_outs = [
+        (
+            ["-gen-convertible-llvmir-intrinsics"],
+            "include/mlir/Dialect/LLVMIR/NVVMConvertibleLLVMIRIntrinsics.inc",
+        ),
+    ],
+    tblgen = ":mlir-tblgen",
+    td_file = "include/mlir/Dialect/LLVMIR/NVVMOps.td",
+    deps = [":NVVMOpsTdFiles"],
+)
+
 cc_library(
     name = "BasicPtxBuilderInterface",
     srcs = ["lib/Dialect/LLVMIR/IR/BasicPtxBuilderInterface.cpp"],
@@ -8350,8 +8376,8 @@ cc_library(
 
 cc_library(
     name = "NVVMToLLVMIRTranslation",
-    srcs = glob(["lib/Target/LLVMIR/Dialect/NVVM/*.cpp"]),
-    hdrs = glob(["include/mlir/Target/LLVMIR/Dialect/NVVM/*.h"]),
+    srcs = ["lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp"],
+    hdrs = ["include/mlir/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.h"],
     includes = ["include"],
     deps = [
         ":DialectUtils",
@@ -8468,6 +8494,23 @@ cc_library(
     ],
 )
 
+cc_library(
+    name = "LLVMIRToNVVMTranslation",
+    srcs = ["lib/Target/LLVMIR/Dialect/NVVM/LLVMIRToNVVMTranslation.cpp"],
+    hdrs = ["include/mlir/Target/LLVMIR/Dialect/NVVM/LLVMIRToNVVMTranslation.h"],
+    includes = ["include"],
+    deps = [
+        ":FromLLVMIRTranslation",
+        ":IR",
+        ":NVVMConvertibleLLVMIRIntrinsicsIncGen",
+        ":NVVMDialect",
+        ":NVVMFromLLVMIRConversionsIncGen",
+        ":Support",
+        "//llvm:Core",
+        "//llvm:Support",
+    ],
+)
+
 cc_library(
     name = "OpenACCToLLVMIRTranslation",
     srcs = glob(["lib/Target/LLVMIR/Dialect/OpenACC/*.cpp"]),
@@ -8521,6 +8564,7 @@ cc_library(
         ":BuiltinToLLVMIRTranslation",
         ":GPUToLLVMIRTranslation",
         ":LLVMIRToLLVMTranslation",
+        ":LLVMIRToNVVMTranslation",
         ":LLVMToLLVMIRTranslation",
         ":NVVMTarget",
         ":NVVMToLLVMIRTranslation",
-- 
GitLab


From 777b6de7a416e8fdb1aae5d28412e8d6dcc4ab8e Mon Sep 17 00:00:00 2001
From: Saiyedul Islam <Saiyedul.Islam@amd.com>
Date: Tue, 12 Dec 2023 14:35:13 +0530
Subject: [PATCH 240/349] [AMDGPU][NFC] Test autogenerated llc tests for COV5
 (#74339)

Regenerate a few llc tests to test for COV5 instead of the default ABI
version.
---
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp     |    2 +-
 .../abi-attribute-hints-undefined-behavior.ll |   29 +-
 .../test/CodeGen/AMDGPU/addrspacecast.gfx6.ll |    9 +-
 .../amdgpu-simplify-libcall-pow-codegen.ll    |   63 +-
 .../annotate-kernel-features-hsa-call.ll      |   31 +-
 .../AMDGPU/annotate-kernel-features-hsa.ll    |   22 +-
 ...der-no-live-segment-at-def-implicit-def.ll |   70 +-
 .../branch-folding-implicit-def-subreg.ll     |  779 ++---
 .../CodeGen/AMDGPU/call-argument-types.ll     | 2683 ++++++++---------
 llvm/test/CodeGen/AMDGPU/call-waitcnt.ll      |   92 +-
 .../callee-special-input-sgprs-fixed-abi.ll   |   23 +-
 llvm/test/CodeGen/AMDGPU/cc-update.ll         |  307 +-
 .../CodeGen/AMDGPU/cf-loop-on-constant.ll     |   93 +-
 llvm/test/CodeGen/AMDGPU/collapse-endcf.ll    |   23 +-
 .../AMDGPU/cross-block-use-is-not-abi-copy.ll |   63 +-
 llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll     |   43 +-
 llvm/test/CodeGen/AMDGPU/ds_read2.ll          |   49 +-
 .../AMDGPU/dwarf-multi-register-use-crash.ll  |   15 +-
 llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll |   39 +-
 .../AMDGPU/global_atomics_scan_fadd.ll        | 1158 ++++---
 .../AMDGPU/global_atomics_scan_fmax.ll        |  696 ++---
 .../AMDGPU/global_atomics_scan_fmin.ll        |  696 ++---
 .../AMDGPU/global_atomics_scan_fsub.ll        | 1157 ++++---
 23 files changed, 3894 insertions(+), 4248 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index aedb832b9459..3626715acb3c 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -1791,7 +1791,7 @@ SDValue SITargetLowering::lowerKernArgParameterPtr(SelectionDAG &DAG,
   // We may not have the kernarg segment argument if we have no kernel
   // arguments.
   if (!InputPtrReg)
-    return DAG.getConstant(0, SL, PtrVT);
+    return DAG.getConstant(Offset, SL, PtrVT);
 
   MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
   SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
diff --git a/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll b/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
index c7bc584d42d5..a439c0f51ffe 100644
--- a/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
+++ b/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
@@ -276,10 +276,13 @@ define void @addrspacecast_requires_queue_ptr(ptr addrspace(5) %ptr.private, ptr
 ; FIXEDABI-SDAG-LABEL: addrspacecast_requires_queue_ptr:
 ; FIXEDABI-SDAG:       ; %bb.0:
 ; FIXEDABI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; FIXEDABI-SDAG-NEXT:    s_load_dwordx2 s[4:5], s[6:7], 0x40
+; FIXEDABI-SDAG-NEXT:    s_mov_b64 s[4:5], 0xc0
+; FIXEDABI-SDAG-NEXT:    s_load_dword s6, s[4:5], 0x0
+; FIXEDABI-SDAG-NEXT:    s_mov_b64 s[4:5], 0xc4
+; FIXEDABI-SDAG-NEXT:    s_load_dword s4, s[4:5], 0x0
 ; FIXEDABI-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, -1, v0
 ; FIXEDABI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; FIXEDABI-SDAG-NEXT:    v_mov_b32_e32 v2, s5
+; FIXEDABI-SDAG-NEXT:    v_mov_b32_e32 v2, s6
 ; FIXEDABI-SDAG-NEXT:    v_cndmask_b32_e32 v3, 0, v2, vcc
 ; FIXEDABI-SDAG-NEXT:    v_cndmask_b32_e32 v2, 0, v0, vcc
 ; FIXEDABI-SDAG-NEXT:    v_mov_b32_e32 v0, s4
@@ -297,12 +300,15 @@ define void @addrspacecast_requires_queue_ptr(ptr addrspace(5) %ptr.private, ptr
 ; FIXEDABI-GISEL-LABEL: addrspacecast_requires_queue_ptr:
 ; FIXEDABI-GISEL:       ; %bb.0:
 ; FIXEDABI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; FIXEDABI-GISEL-NEXT:    s_load_dwordx2 s[4:5], s[6:7], 0x40
+; FIXEDABI-GISEL-NEXT:    s_mov_b64 s[4:5], 0xc0
+; FIXEDABI-GISEL-NEXT:    s_load_dword s6, s[4:5], 0x0
+; FIXEDABI-GISEL-NEXT:    s_mov_b64 s[4:5], 0xc4
+; FIXEDABI-GISEL-NEXT:    s_load_dword s4, s[4:5], 0x0
 ; FIXEDABI-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, -1, v0
 ; FIXEDABI-GISEL-NEXT:    v_cndmask_b32_e32 v2, 0, v0, vcc
 ; FIXEDABI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; FIXEDABI-GISEL-NEXT:    v_mov_b32_e32 v0, s5
-; FIXEDABI-GISEL-NEXT:    v_cndmask_b32_e32 v3, 0, v0, vcc
+; FIXEDABI-GISEL-NEXT:    v_mov_b32_e32 v3, s6
+; FIXEDABI-GISEL-NEXT:    v_cndmask_b32_e32 v3, 0, v3, vcc
 ; FIXEDABI-GISEL-NEXT:    v_mov_b32_e32 v4, s4
 ; FIXEDABI-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, -1, v1
 ; FIXEDABI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
@@ -325,7 +331,8 @@ define void @is_shared_requires_queue_ptr(ptr %ptr) #0 {
 ; FIXEDABI-LABEL: is_shared_requires_queue_ptr:
 ; FIXEDABI:       ; %bb.0:
 ; FIXEDABI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; FIXEDABI-NEXT:    s_load_dword s4, s[6:7], 0x40
+; FIXEDABI-NEXT:    s_mov_b64 s[4:5], 0xc4
+; FIXEDABI-NEXT:    s_load_dword s4, s[4:5], 0x0
 ; FIXEDABI-NEXT:    s_waitcnt lgkmcnt(0)
 ; FIXEDABI-NEXT:    v_cmp_eq_u32_e32 vcc, s4, v1
 ; FIXEDABI-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
@@ -342,7 +349,8 @@ define void @is_private_requires_queue_ptr(ptr %ptr) #0 {
 ; FIXEDABI-LABEL: is_private_requires_queue_ptr:
 ; FIXEDABI:       ; %bb.0:
 ; FIXEDABI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; FIXEDABI-NEXT:    s_load_dword s4, s[6:7], 0x44
+; FIXEDABI-NEXT:    s_mov_b64 s[4:5], 0xc0
+; FIXEDABI-NEXT:    s_load_dword s4, s[4:5], 0x0
 ; FIXEDABI-NEXT:    s_waitcnt lgkmcnt(0)
 ; FIXEDABI-NEXT:    v_cmp_eq_u32_e32 vcc, s4, v1
 ; FIXEDABI-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
@@ -359,7 +367,9 @@ define void @trap_requires_queue() #0 {
 ; FIXEDABI-LABEL: trap_requires_queue:
 ; FIXEDABI:       ; %bb.0:
 ; FIXEDABI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; FIXEDABI-NEXT:    s_mov_b64 s[0:1], s[6:7]
+; FIXEDABI-NEXT:    s_mov_b64 s[4:5], 0xc8
+; FIXEDABI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; FIXEDABI-NEXT:    s_waitcnt lgkmcnt(0)
 ; FIXEDABI-NEXT:    s_trap 2
   call void @llvm.trap()
   unreachable
@@ -390,3 +400,6 @@ declare void @llvm.trap()
 declare void @llvm.debugtrap()
 
 attributes #0 = { "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-queue-ptr" "amdgpu-no-work-group-id-x" "amdgpu-no-work-group-id-y" "amdgpu-no-work-group-id-z" "amdgpu-no-work-item-id-x" "amdgpu-no-work-item-id-y" "amdgpu-no-work-item-id-z" }
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"amdgpu_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast.gfx6.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast.gfx6.ll
index 2d60faaf8c8c..ed574d012bc6 100644
--- a/llvm/test/CodeGen/AMDGPU/addrspacecast.gfx6.ll
+++ b/llvm/test/CodeGen/AMDGPU/addrspacecast.gfx6.ll
@@ -24,7 +24,8 @@ define ptr @group_to_flat_addrspacecast(ptr addrspace(3) %ptr) {
 ; CHECK-LABEL: group_to_flat_addrspacecast:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    s_load_dword s4, s[6:7], 0x10
+; CHECK-NEXT:    s_mov_b64 s[4:5], 0xc4
+; CHECK-NEXT:    s_load_dword s4, s[4:5], 0x0
 ; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, -1, v0
 ; CHECK-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
@@ -50,7 +51,8 @@ define ptr @private_to_flat_addrspacecast(ptr addrspace(5) %ptr) {
 ; CHECK-LABEL: private_to_flat_addrspacecast:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    s_load_dword s4, s[6:7], 0x11
+; CHECK-NEXT:    s_mov_b64 s[4:5], 0xc0
+; CHECK-NEXT:    s_load_dword s4, s[4:5], 0x0
 ; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, -1, v0
 ; CHECK-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
@@ -204,3 +206,6 @@ define ptr addrspace(6) @addrspacecast_flat_null_to_constant32bit() {
 }
 
 attributes #0 = { "amdgpu-32bit-address-high-bits"="0xffff8000" }
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"amdgpu_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
index 8c64ab5952de..e53fa9650f9e 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
@@ -146,13 +146,13 @@ define double @test_pow_fast_f64__integral_y(double %x, i32 %y.i) {
 ; CHECK-NEXT:    s_mov_b64 s[4:5], s[40:41]
 ; CHECK-NEXT:    v_writelane_b32 v40, s45, 13
 ; CHECK-NEXT:    v_mov_b32_e32 v41, v31
+; CHECK-NEXT:    s_mov_b64 s[34:35], s[6:7]
 ; CHECK-NEXT:    s_mov_b32 s42, s15
 ; CHECK-NEXT:    s_mov_b32 s43, s14
 ; CHECK-NEXT:    s_mov_b32 s44, s13
 ; CHECK-NEXT:    s_mov_b32 s45, s12
-; CHECK-NEXT:    s_mov_b64 s[34:35], s[10:11]
-; CHECK-NEXT:    s_mov_b64 s[36:37], s[8:9]
-; CHECK-NEXT:    s_mov_b64 s[38:39], s[6:7]
+; CHECK-NEXT:    s_mov_b64 s[36:37], s[10:11]
+; CHECK-NEXT:    s_mov_b64 s[38:39], s[8:9]
 ; CHECK-NEXT:    v_mov_b32_e32 v42, v2
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
 ; CHECK-NEXT:    s_swappc_b64 s[30:31], s[16:17]
@@ -163,9 +163,9 @@ define double @test_pow_fast_f64__integral_y(double %x, i32 %y.i) {
 ; CHECK-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
 ; CHECK-NEXT:    s_mov_b64 s[4:5], s[40:41]
 ; CHECK-NEXT:    v_mul_f64 v[0:1], v[0:1], v[2:3]
-; CHECK-NEXT:    s_mov_b64 s[6:7], s[38:39]
-; CHECK-NEXT:    s_mov_b64 s[8:9], s[36:37]
-; CHECK-NEXT:    s_mov_b64 s[10:11], s[34:35]
+; CHECK-NEXT:    s_mov_b64 s[6:7], s[34:35]
+; CHECK-NEXT:    s_mov_b64 s[8:9], s[38:39]
+; CHECK-NEXT:    s_mov_b64 s[10:11], s[36:37]
 ; CHECK-NEXT:    s_mov_b32 s12, s45
 ; CHECK-NEXT:    s_mov_b32 s13, s44
 ; CHECK-NEXT:    s_mov_b32 s14, s43
@@ -285,13 +285,13 @@ define double @test_powr_fast_f64(double %x, double %y) {
 ; CHECK-NEXT:    buffer_store_dword v43, off, s[0:3], s33 ; 4-byte Folded Spill
 ; CHECK-NEXT:    v_writelane_b32 v40, s45, 13
 ; CHECK-NEXT:    v_mov_b32_e32 v43, v31
+; CHECK-NEXT:    s_mov_b64 s[34:35], s[6:7]
 ; CHECK-NEXT:    s_mov_b32 s42, s15
 ; CHECK-NEXT:    s_mov_b32 s43, s14
 ; CHECK-NEXT:    s_mov_b32 s44, s13
 ; CHECK-NEXT:    s_mov_b32 s45, s12
-; CHECK-NEXT:    s_mov_b64 s[34:35], s[10:11]
-; CHECK-NEXT:    s_mov_b64 s[36:37], s[8:9]
-; CHECK-NEXT:    s_mov_b64 s[38:39], s[6:7]
+; CHECK-NEXT:    s_mov_b64 s[36:37], s[10:11]
+; CHECK-NEXT:    s_mov_b64 s[38:39], s[8:9]
 ; CHECK-NEXT:    v_mov_b32_e32 v42, v3
 ; CHECK-NEXT:    v_mov_b32_e32 v41, v2
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
@@ -302,9 +302,9 @@ define double @test_powr_fast_f64(double %x, double %y) {
 ; CHECK-NEXT:    s_addc_u32 s5, s5, _Z4exp2d@gotpcrel32@hi+12
 ; CHECK-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
 ; CHECK-NEXT:    s_mov_b64 s[4:5], s[40:41]
-; CHECK-NEXT:    s_mov_b64 s[6:7], s[38:39]
-; CHECK-NEXT:    s_mov_b64 s[8:9], s[36:37]
-; CHECK-NEXT:    s_mov_b64 s[10:11], s[34:35]
+; CHECK-NEXT:    s_mov_b64 s[6:7], s[34:35]
+; CHECK-NEXT:    s_mov_b64 s[8:9], s[38:39]
+; CHECK-NEXT:    s_mov_b64 s[10:11], s[36:37]
 ; CHECK-NEXT:    s_mov_b32 s12, s45
 ; CHECK-NEXT:    s_mov_b32 s13, s44
 ; CHECK-NEXT:    s_mov_b32 s14, s43
@@ -430,13 +430,13 @@ define double @test_pown_fast_f64(double %x, i32 %y) {
 ; CHECK-NEXT:    s_mov_b64 s[4:5], s[40:41]
 ; CHECK-NEXT:    v_writelane_b32 v40, s45, 13
 ; CHECK-NEXT:    v_mov_b32_e32 v41, v31
+; CHECK-NEXT:    s_mov_b64 s[34:35], s[6:7]
 ; CHECK-NEXT:    s_mov_b32 s42, s15
 ; CHECK-NEXT:    s_mov_b32 s43, s14
 ; CHECK-NEXT:    s_mov_b32 s44, s13
 ; CHECK-NEXT:    s_mov_b32 s45, s12
-; CHECK-NEXT:    s_mov_b64 s[34:35], s[10:11]
-; CHECK-NEXT:    s_mov_b64 s[36:37], s[8:9]
-; CHECK-NEXT:    s_mov_b64 s[38:39], s[6:7]
+; CHECK-NEXT:    s_mov_b64 s[36:37], s[10:11]
+; CHECK-NEXT:    s_mov_b64 s[38:39], s[8:9]
 ; CHECK-NEXT:    v_mov_b32_e32 v42, v2
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
 ; CHECK-NEXT:    s_swappc_b64 s[30:31], s[16:17]
@@ -447,9 +447,9 @@ define double @test_pown_fast_f64(double %x, i32 %y) {
 ; CHECK-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
 ; CHECK-NEXT:    s_mov_b64 s[4:5], s[40:41]
 ; CHECK-NEXT:    v_mul_f64 v[0:1], v[0:1], v[2:3]
-; CHECK-NEXT:    s_mov_b64 s[6:7], s[38:39]
-; CHECK-NEXT:    s_mov_b64 s[8:9], s[36:37]
-; CHECK-NEXT:    s_mov_b64 s[10:11], s[34:35]
+; CHECK-NEXT:    s_mov_b64 s[6:7], s[34:35]
+; CHECK-NEXT:    s_mov_b64 s[8:9], s[38:39]
+; CHECK-NEXT:    s_mov_b64 s[10:11], s[36:37]
 ; CHECK-NEXT:    s_mov_b32 s12, s45
 ; CHECK-NEXT:    s_mov_b32 s13, s44
 ; CHECK-NEXT:    s_mov_b32 s14, s43
@@ -571,13 +571,13 @@ define double @test_pown_fast_f64_known_even(double %x, i32 %y.arg) {
 ; CHECK-NEXT:    buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill
 ; CHECK-NEXT:    v_writelane_b32 v40, s45, 13
 ; CHECK-NEXT:    v_mov_b32_e32 v41, v31
+; CHECK-NEXT:    s_mov_b64 s[34:35], s[6:7]
 ; CHECK-NEXT:    s_mov_b32 s42, s15
 ; CHECK-NEXT:    s_mov_b32 s43, s14
 ; CHECK-NEXT:    s_mov_b32 s44, s13
 ; CHECK-NEXT:    s_mov_b32 s45, s12
-; CHECK-NEXT:    s_mov_b64 s[34:35], s[10:11]
-; CHECK-NEXT:    s_mov_b64 s[36:37], s[8:9]
-; CHECK-NEXT:    s_mov_b64 s[38:39], s[6:7]
+; CHECK-NEXT:    s_mov_b64 s[36:37], s[10:11]
+; CHECK-NEXT:    s_mov_b64 s[38:39], s[8:9]
 ; CHECK-NEXT:    v_lshlrev_b32_e32 v42, 1, v2
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
 ; CHECK-NEXT:    s_swappc_b64 s[30:31], s[16:17]
@@ -588,9 +588,9 @@ define double @test_pown_fast_f64_known_even(double %x, i32 %y.arg) {
 ; CHECK-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
 ; CHECK-NEXT:    s_mov_b64 s[4:5], s[40:41]
 ; CHECK-NEXT:    v_mul_f64 v[0:1], v[0:1], v[2:3]
-; CHECK-NEXT:    s_mov_b64 s[6:7], s[38:39]
-; CHECK-NEXT:    s_mov_b64 s[8:9], s[36:37]
-; CHECK-NEXT:    s_mov_b64 s[10:11], s[34:35]
+; CHECK-NEXT:    s_mov_b64 s[6:7], s[34:35]
+; CHECK-NEXT:    s_mov_b64 s[8:9], s[38:39]
+; CHECK-NEXT:    s_mov_b64 s[10:11], s[36:37]
 ; CHECK-NEXT:    s_mov_b32 s12, s45
 ; CHECK-NEXT:    s_mov_b32 s13, s44
 ; CHECK-NEXT:    s_mov_b32 s14, s43
@@ -715,13 +715,13 @@ define double @test_pown_fast_f64_known_odd(double %x, i32 %y.arg) {
 ; CHECK-NEXT:    s_mov_b64 s[4:5], s[40:41]
 ; CHECK-NEXT:    v_writelane_b32 v40, s45, 13
 ; CHECK-NEXT:    v_mov_b32_e32 v41, v31
+; CHECK-NEXT:    s_mov_b64 s[34:35], s[6:7]
 ; CHECK-NEXT:    s_mov_b32 s42, s15
 ; CHECK-NEXT:    s_mov_b32 s43, s14
 ; CHECK-NEXT:    s_mov_b32 s44, s13
 ; CHECK-NEXT:    s_mov_b32 s45, s12
-; CHECK-NEXT:    s_mov_b64 s[34:35], s[10:11]
-; CHECK-NEXT:    s_mov_b64 s[36:37], s[8:9]
-; CHECK-NEXT:    s_mov_b64 s[38:39], s[6:7]
+; CHECK-NEXT:    s_mov_b64 s[36:37], s[10:11]
+; CHECK-NEXT:    s_mov_b64 s[38:39], s[8:9]
 ; CHECK-NEXT:    v_or_b32_e32 v43, 1, v2
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
 ; CHECK-NEXT:    s_swappc_b64 s[30:31], s[16:17]
@@ -732,9 +732,9 @@ define double @test_pown_fast_f64_known_odd(double %x, i32 %y.arg) {
 ; CHECK-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
 ; CHECK-NEXT:    s_mov_b64 s[4:5], s[40:41]
 ; CHECK-NEXT:    v_mul_f64 v[0:1], v[0:1], v[2:3]
-; CHECK-NEXT:    s_mov_b64 s[6:7], s[38:39]
-; CHECK-NEXT:    s_mov_b64 s[8:9], s[36:37]
-; CHECK-NEXT:    s_mov_b64 s[10:11], s[34:35]
+; CHECK-NEXT:    s_mov_b64 s[6:7], s[34:35]
+; CHECK-NEXT:    s_mov_b64 s[8:9], s[38:39]
+; CHECK-NEXT:    s_mov_b64 s[10:11], s[36:37]
 ; CHECK-NEXT:    s_mov_b32 s12, s45
 ; CHECK-NEXT:    s_mov_b32 s13, s44
 ; CHECK-NEXT:    s_mov_b32 s14, s43
@@ -773,3 +773,6 @@ define double @test_pown_fast_f64_known_odd(double %x, i32 %y.arg) {
   %call = tail call fast double @_Z4powndi(double %x, i32 %y)
   ret double %call
 }
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"amdgpu_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
index 1f90c0d03a85..1396dab69c13 100644
--- a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
@@ -458,7 +458,7 @@ define void @use_group_to_flat_addrspacecast(ptr addrspace(3) %ptr) #1 {
 ; AKF_HSA-NEXT:    ret void
 ;
 ; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_group_to_flat_addrspacecast
-; ATTRIBUTOR_HSA-SAME: (ptr addrspace(3) [[PTR:%.*]]) #[[ATTR8]] {
+; ATTRIBUTOR_HSA-SAME: (ptr addrspace(3) [[PTR:%.*]]) #[[ATTR12:[0-9]+]] {
 ; ATTRIBUTOR_HSA-NEXT:    [[STOF:%.*]] = addrspacecast ptr addrspace(3) [[PTR]] to ptr addrspace(4)
 ; ATTRIBUTOR_HSA-NEXT:    store volatile i32 0, ptr addrspace(4) [[STOF]], align 4
 ; ATTRIBUTOR_HSA-NEXT:    ret void
@@ -477,7 +477,7 @@ define void @use_group_to_flat_addrspacecast_gfx9(ptr addrspace(3) %ptr) #2 {
 ; AKF_HSA-NEXT:    ret void
 ;
 ; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_group_to_flat_addrspacecast_gfx9
-; ATTRIBUTOR_HSA-SAME: (ptr addrspace(3) [[PTR:%.*]]) #[[ATTR12:[0-9]+]] {
+; ATTRIBUTOR_HSA-SAME: (ptr addrspace(3) [[PTR:%.*]]) #[[ATTR13:[0-9]+]] {
 ; ATTRIBUTOR_HSA-NEXT:    [[STOF:%.*]] = addrspacecast ptr addrspace(3) [[PTR]] to ptr addrspace(4)
 ; ATTRIBUTOR_HSA-NEXT:    store volatile i32 0, ptr addrspace(4) [[STOF]], align 4
 ; ATTRIBUTOR_HSA-NEXT:    ret void
@@ -496,7 +496,7 @@ define void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(ptr addrspace(3) %pt
 ; AKF_HSA-NEXT:    ret void
 ;
 ; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_group_to_flat_addrspacecast_queue_ptr_gfx9
-; ATTRIBUTOR_HSA-SAME: (ptr addrspace(3) [[PTR:%.*]]) #[[ATTR13:[0-9]+]] {
+; ATTRIBUTOR_HSA-SAME: (ptr addrspace(3) [[PTR:%.*]]) #[[ATTR14:[0-9]+]] {
 ; ATTRIBUTOR_HSA-NEXT:    [[STOF:%.*]] = addrspacecast ptr addrspace(3) [[PTR]] to ptr addrspace(4)
 ; ATTRIBUTOR_HSA-NEXT:    store volatile i32 0, ptr addrspace(4) [[STOF]], align 4
 ; ATTRIBUTOR_HSA-NEXT:    call void @func_indirect_use_queue_ptr()
@@ -515,7 +515,7 @@ define void @indirect_use_group_to_flat_addrspacecast() #1 {
 ; AKF_HSA-NEXT:    ret void
 ;
 ; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@indirect_use_group_to_flat_addrspacecast
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR8]] {
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR12]] {
 ; ATTRIBUTOR_HSA-NEXT:    call void @use_group_to_flat_addrspacecast(ptr addrspace(3) null)
 ; ATTRIBUTOR_HSA-NEXT:    ret void
 ;
@@ -593,7 +593,7 @@ define amdgpu_kernel void @kern_use_implicitarg_ptr() #1 {
 ; AKF_HSA-NEXT:    ret void
 ;
 ; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@kern_use_implicitarg_ptr
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR14:[0-9]+]] {
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR15:[0-9]+]] {
 ; ATTRIBUTOR_HSA-NEXT:    [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
 ; ATTRIBUTOR_HSA-NEXT:    store volatile ptr addrspace(4) [[IMPLICITARG_PTR]], ptr addrspace(1) undef, align 8
 ; ATTRIBUTOR_HSA-NEXT:    ret void
@@ -611,7 +611,7 @@ define void @use_implicitarg_ptr() #1 {
 ; AKF_HSA-NEXT:    ret void
 ;
 ; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_implicitarg_ptr
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR15:[0-9]+]] {
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR12]] {
 ; ATTRIBUTOR_HSA-NEXT:    [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
 ; ATTRIBUTOR_HSA-NEXT:    store volatile ptr addrspace(4) [[IMPLICITARG_PTR]], ptr addrspace(1) undef, align 8
 ; ATTRIBUTOR_HSA-NEXT:    ret void
@@ -628,7 +628,7 @@ define void @func_indirect_use_implicitarg_ptr() #1 {
 ; AKF_HSA-NEXT:    ret void
 ;
 ; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@func_indirect_use_implicitarg_ptr
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR15]] {
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR12]] {
 ; ATTRIBUTOR_HSA-NEXT:    call void @use_implicitarg_ptr()
 ; ATTRIBUTOR_HSA-NEXT:    ret void
 ;
@@ -1010,6 +1010,9 @@ attributes #4 = { nounwind sanitize_address }
 attributes #5 = { nounwind sanitize_address "amdgpu-no-implicitarg-ptr" }
 attributes #6 = { "enqueued-block" }
 
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"amdgpu_code_object_version", i32 500}
 ;.
 ; AKF_HSA: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
 ; AKF_HSA: attributes #[[ATTR1]] = { nounwind "target-cpu"="fiji" }
@@ -1029,14 +1032,14 @@ attributes #6 = { "enqueued-block" }
 ; ATTRIBUTOR_HSA: attributes #[[ATTR5]] = { nounwind "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "target-cpu"="fiji" "uniform-work-group-size"="false" }
 ; ATTRIBUTOR_HSA: attributes #[[ATTR6]] = { nounwind "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "target-cpu"="fiji" "uniform-work-group-size"="false" }
 ; ATTRIBUTOR_HSA: attributes #[[ATTR7]] = { nounwind "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "target-cpu"="fiji" "uniform-work-group-size"="false" }
-; ATTRIBUTOR_HSA: attributes #[[ATTR8]] = { nounwind "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "target-cpu"="fiji" "uniform-work-group-size"="false" }
+; ATTRIBUTOR_HSA: attributes #[[ATTR8]] = { nounwind "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "target-cpu"="fiji" "uniform-work-group-size"="false" }
 ; ATTRIBUTOR_HSA: attributes #[[ATTR9]] = { nounwind "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "target-cpu"="fiji" "uniform-work-group-size"="false" }
 ; ATTRIBUTOR_HSA: attributes #[[ATTR10]] = { nounwind "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "target-cpu"="fiji" "uniform-work-group-size"="false" }
 ; ATTRIBUTOR_HSA: attributes #[[ATTR11]] = { nounwind "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "target-cpu"="fiji" "uniform-work-group-size"="false" }
-; ATTRIBUTOR_HSA: attributes #[[ATTR12]] = { nounwind "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "target-cpu"="gfx900" "uniform-work-group-size"="false" }
-; ATTRIBUTOR_HSA: attributes #[[ATTR13]] = { nounwind "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "target-cpu"="gfx900" "uniform-work-group-size"="false" }
-; ATTRIBUTOR_HSA: attributes #[[ATTR14]] = { nounwind "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" }
-; ATTRIBUTOR_HSA: attributes #[[ATTR15]] = { nounwind "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "target-cpu"="fiji" "uniform-work-group-size"="false" }
+; ATTRIBUTOR_HSA: attributes #[[ATTR12]] = { nounwind "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "target-cpu"="fiji" "uniform-work-group-size"="false" }
+; ATTRIBUTOR_HSA: attributes #[[ATTR13]] = { nounwind "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "target-cpu"="gfx900" "uniform-work-group-size"="false" }
+; ATTRIBUTOR_HSA: attributes #[[ATTR14]] = { nounwind "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "target-cpu"="gfx900" "uniform-work-group-size"="false" }
+; ATTRIBUTOR_HSA: attributes #[[ATTR15]] = { nounwind "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" }
 ; ATTRIBUTOR_HSA: attributes #[[ATTR16]] = { nounwind "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
 ; ATTRIBUTOR_HSA: attributes #[[ATTR17]] = { nounwind "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
 ; ATTRIBUTOR_HSA: attributes #[[ATTR18]] = { nounwind "uniform-work-group-size"="false" }
@@ -1052,3 +1055,7 @@ attributes #6 = { "enqueued-block" }
 ; ATTRIBUTOR_HSA: attributes #[[ATTR28]] = { nounwind }
 ; ATTRIBUTOR_HSA: attributes #[[ATTR29]] = { "enqueued-block" }
 ;.
+; AKF_HSA: [[META0:![0-9]+]] = !{i32 1, !"amdgpu_code_object_version", i32 500}
+;.
+; ATTRIBUTOR_HSA: [[META0:![0-9]+]] = !{i32 1, !"amdgpu_code_object_version", i32 500}
+;.
diff --git a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
index 9e5df73d69a0..e0139fda653f 100644
--- a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
+++ b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
@@ -424,7 +424,7 @@ define amdgpu_kernel void @use_group_to_flat_addrspacecast(ptr addrspace(3) %ptr
 ; AKF_HSA-NEXT:    ret void
 ;
 ; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_group_to_flat_addrspacecast
-; ATTRIBUTOR_HSA-SAME: (ptr addrspace(3) [[PTR:%.*]]) #[[ATTR11]] {
+; ATTRIBUTOR_HSA-SAME: (ptr addrspace(3) [[PTR:%.*]]) #[[ATTR12:[0-9]+]] {
 ; ATTRIBUTOR_HSA-NEXT:    [[STOF:%.*]] = addrspacecast ptr addrspace(3) [[PTR]] to ptr
 ; ATTRIBUTOR_HSA-NEXT:    store volatile i32 0, ptr [[STOF]], align 4
 ; ATTRIBUTOR_HSA-NEXT:    ret void
@@ -442,7 +442,7 @@ define amdgpu_kernel void @use_private_to_flat_addrspacecast(ptr addrspace(5) %p
 ; AKF_HSA-NEXT:    ret void
 ;
 ; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_private_to_flat_addrspacecast
-; ATTRIBUTOR_HSA-SAME: (ptr addrspace(5) [[PTR:%.*]]) #[[ATTR11]] {
+; ATTRIBUTOR_HSA-SAME: (ptr addrspace(5) [[PTR:%.*]]) #[[ATTR12]] {
 ; ATTRIBUTOR_HSA-NEXT:    [[STOF:%.*]] = addrspacecast ptr addrspace(5) [[PTR]] to ptr
 ; ATTRIBUTOR_HSA-NEXT:    store volatile i32 0, ptr [[STOF]], align 4
 ; ATTRIBUTOR_HSA-NEXT:    ret void
@@ -534,7 +534,7 @@ define amdgpu_kernel void @use_is_shared(ptr %ptr) #1 {
 ; AKF_HSA-NEXT:    ret void
 ;
 ; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_is_shared
-; ATTRIBUTOR_HSA-SAME: (ptr [[PTR:%.*]]) #[[ATTR11]] {
+; ATTRIBUTOR_HSA-SAME: (ptr [[PTR:%.*]]) #[[ATTR12]] {
 ; ATTRIBUTOR_HSA-NEXT:    [[IS_SHARED:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[PTR]])
 ; ATTRIBUTOR_HSA-NEXT:    [[EXT:%.*]] = zext i1 [[IS_SHARED]] to i32
 ; ATTRIBUTOR_HSA-NEXT:    store i32 [[EXT]], ptr addrspace(1) undef, align 4
@@ -555,7 +555,7 @@ define amdgpu_kernel void @use_is_private(ptr %ptr) #1 {
 ; AKF_HSA-NEXT:    ret void
 ;
 ; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_is_private
-; ATTRIBUTOR_HSA-SAME: (ptr [[PTR:%.*]]) #[[ATTR11]] {
+; ATTRIBUTOR_HSA-SAME: (ptr [[PTR:%.*]]) #[[ATTR12]] {
 ; ATTRIBUTOR_HSA-NEXT:    [[IS_PRIVATE:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[PTR]])
 ; ATTRIBUTOR_HSA-NEXT:    [[EXT:%.*]] = zext i1 [[IS_PRIVATE]] to i32
 ; ATTRIBUTOR_HSA-NEXT:    store i32 [[EXT]], ptr addrspace(1) undef, align 4
@@ -621,7 +621,7 @@ define void @use_alloca_func() #1 {
 ; AKF_HSA-NEXT:    ret void
 ;
 ; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_alloca_func
-; ATTRIBUTOR_HSA-SAME: () #[[ATTR12:[0-9]+]] {
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR13:[0-9]+]] {
 ; ATTRIBUTOR_HSA-NEXT:    [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5)
 ; ATTRIBUTOR_HSA-NEXT:    store i32 0, ptr addrspace(5) [[ALLOCA]], align 4
 ; ATTRIBUTOR_HSA-NEXT:    ret void
@@ -634,6 +634,9 @@ define void @use_alloca_func() #1 {
 attributes #0 = { nounwind readnone speculatable }
 attributes #1 = { nounwind }
 
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"amdgpu_code_object_version", i32 500}
+
 ;.
 ; AKF_HSA: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
 ; AKF_HSA: attributes #[[ATTR1]] = { nounwind }
@@ -650,6 +653,11 @@ attributes #1 = { nounwind }
 ; ATTRIBUTOR_HSA: attributes #[[ATTR8]] = { nounwind "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "uniform-work-group-size"="false" }
 ; ATTRIBUTOR_HSA: attributes #[[ATTR9]] = { nounwind "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workitem-id-x" "uniform-work-group-size"="false" }
 ; ATTRIBUTOR_HSA: attributes #[[ATTR10]] = { nounwind "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
-; ATTRIBUTOR_HSA: attributes #[[ATTR11]] = { nounwind "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
-; ATTRIBUTOR_HSA: attributes #[[ATTR12]] = { nounwind "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
+; ATTRIBUTOR_HSA: attributes #[[ATTR11]] = { nounwind "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
+; ATTRIBUTOR_HSA: attributes #[[ATTR12]] = { nounwind "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
+; ATTRIBUTOR_HSA: attributes #[[ATTR13]] = { nounwind "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
+;.
+; AKF_HSA: [[META0:![0-9]+]] = !{i32 1, !"amdgpu_code_object_version", i32 500}
+;.
+; ATTRIBUTOR_HSA: [[META0:![0-9]+]] = !{i32 1, !"amdgpu_code_object_version", i32 500}
 ;.
diff --git a/llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll b/llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
index a965a20244b4..7c8d40c49bb8 100644
--- a/llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
+++ b/llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
@@ -4,15 +4,16 @@
 define amdgpu_kernel void @blender_no_live_segment_at_def_error(<4 x float> %extractVec358.i.i, i32 %cmp5.i.i.arg, float %i1.i, i32 %cmp221.i.i.arg, i32 %cmp262.i.i.arg, ptr addrspace(1) %arg) {
 ; CHECK-LABEL: blender_no_live_segment_at_def_error:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    s_add_u32 s12, s12, s17
+; CHECK-NEXT:    s_add_u32 s10, s10, s15
+; CHECK-NEXT:    s_addc_u32 s11, s11, 0
 ; CHECK-NEXT:    s_mov_b32 s32, 0
-; CHECK-NEXT:    s_addc_u32 s13, s13, 0
-; CHECK-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12
-; CHECK-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13
-; CHECK-NEXT:    s_load_dwordx8 s[36:43], s[8:9], 0x0
-; CHECK-NEXT:    s_add_u32 s0, s0, s17
+; CHECK-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s10
+; CHECK-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s11
+; CHECK-NEXT:    s_load_dwordx8 s[36:43], s[6:7], 0x0
+; CHECK-NEXT:    s_add_u32 s0, s0, s15
 ; CHECK-NEXT:    s_addc_u32 s1, s1, 0
-; CHECK-NEXT:    s_mov_b32 s12, 0
+; CHECK-NEXT:    s_mov_b64 s[10:11], s[8:9]
+; CHECK-NEXT:    s_mov_b32 s8, 0
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
 ; CHECK-NEXT:    s_cmp_lg_u32 s40, 0
 ; CHECK-NEXT:    s_cbranch_scc1 .LBB0_8
@@ -21,54 +22,50 @@ define amdgpu_kernel void @blender_no_live_segment_at_def_error(<4 x float> %ext
 ; CHECK-NEXT:    s_cbranch_scc1 .LBB0_4
 ; CHECK-NEXT:  ; %bb.2: ; %if.else251.i.i
 ; CHECK-NEXT:    s_cmp_lg_u32 s43, 0
-; CHECK-NEXT:    s_mov_b32 s17, 0
-; CHECK-NEXT:    s_cselect_b32 s12, -1, 0
-; CHECK-NEXT:    s_and_b32 vcc_lo, exec_lo, s12
+; CHECK-NEXT:    s_mov_b32 s15, 0
+; CHECK-NEXT:    s_cselect_b32 s8, -1, 0
+; CHECK-NEXT:    s_and_b32 vcc_lo, exec_lo, s8
 ; CHECK-NEXT:    s_cbranch_vccz .LBB0_5
 ; CHECK-NEXT:  ; %bb.3:
 ; CHECK-NEXT:    s_mov_b32 s36, 0
-; CHECK-NEXT:    s_andn2_b32 vcc_lo, exec_lo, s12
+; CHECK-NEXT:    s_andn2_b32 vcc_lo, exec_lo, s8
 ; CHECK-NEXT:    s_cbranch_vccz .LBB0_6
 ; CHECK-NEXT:    s_branch .LBB0_7
 ; CHECK-NEXT:  .LBB0_4:
-; CHECK-NEXT:    s_mov_b32 s14, s12
-; CHECK-NEXT:    s_mov_b32 s15, s12
-; CHECK-NEXT:    s_mov_b32 s13, s12
-; CHECK-NEXT:    s_mov_b64 s[38:39], s[14:15]
-; CHECK-NEXT:    s_mov_b64 s[36:37], s[12:13]
+; CHECK-NEXT:    s_mov_b32 s10, s8
+; CHECK-NEXT:    s_mov_b32 s11, s8
+; CHECK-NEXT:    s_mov_b32 s9, s8
+; CHECK-NEXT:    s_mov_b64 s[38:39], s[10:11]
+; CHECK-NEXT:    s_mov_b64 s[36:37], s[8:9]
 ; CHECK-NEXT:    s_branch .LBB0_7
 ; CHECK-NEXT:  .LBB0_5: ; %if.then263.i.i
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s12, s41, 0
+; CHECK-NEXT:    v_cmp_lt_f32_e64 s8, s41, 0
 ; CHECK-NEXT:    s_mov_b32 s36, 1.0
-; CHECK-NEXT:    s_mov_b32 s17, 0x7fc00000
+; CHECK-NEXT:    s_mov_b32 s15, 0x7fc00000
 ; CHECK-NEXT:    s_mov_b32 s37, s36
 ; CHECK-NEXT:    s_mov_b32 s38, s36
 ; CHECK-NEXT:    s_mov_b32 s39, s36
-; CHECK-NEXT:    s_andn2_b32 vcc_lo, exec_lo, s12
+; CHECK-NEXT:    s_andn2_b32 vcc_lo, exec_lo, s8
 ; CHECK-NEXT:    s_cbranch_vccnz .LBB0_7
 ; CHECK-NEXT:  .LBB0_6: ; %if.end273.i.i
-; CHECK-NEXT:    s_add_u32 s12, s8, 40
-; CHECK-NEXT:    s_addc_u32 s13, s9, 0
-; CHECK-NEXT:    s_getpc_b64 s[18:19]
-; CHECK-NEXT:    s_add_u32 s18, s18, _Z3dotDv3_fS_@gotpcrel32@lo+4
-; CHECK-NEXT:    s_addc_u32 s19, s19, _Z3dotDv3_fS_@gotpcrel32@hi+12
+; CHECK-NEXT:    s_add_u32 s8, s6, 40
+; CHECK-NEXT:    s_addc_u32 s9, s7, 0
+; CHECK-NEXT:    s_getpc_b64 s[16:17]
+; CHECK-NEXT:    s_add_u32 s16, s16, _Z3dotDv3_fS_@gotpcrel32@lo+4
+; CHECK-NEXT:    s_addc_u32 s17, s17, _Z3dotDv3_fS_@gotpcrel32@hi+12
 ; CHECK-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; CHECK-NEXT:    s_load_dwordx2 s[18:19], s[18:19], 0x0
+; CHECK-NEXT:    s_load_dwordx2 s[16:17], s[16:17], 0x0
 ; CHECK-NEXT:    v_lshlrev_b32_e32 v3, 10, v1
-; CHECK-NEXT:    v_add_f32_e64 v1, s17, s36
-; CHECK-NEXT:    s_mov_b64 s[34:35], s[8:9]
-; CHECK-NEXT:    s_mov_b64 s[8:9], s[12:13]
-; CHECK-NEXT:    s_mov_b32 s12, s14
+; CHECK-NEXT:    v_add_f32_e64 v1, s15, s36
+; CHECK-NEXT:    s_mov_b32 s36, 0
+; CHECK-NEXT:    s_mov_b64 s[34:35], s[6:7]
 ; CHECK-NEXT:    v_or3_b32 v31, v0, v3, v2
 ; CHECK-NEXT:    v_mov_b32_e32 v0, v1
 ; CHECK-NEXT:    v_mov_b32_e32 v1, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 0
-; CHECK-NEXT:    s_mov_b32 s13, s15
-; CHECK-NEXT:    s_mov_b32 s14, s16
-; CHECK-NEXT:    s_mov_b32 s36, 0
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
-; CHECK-NEXT:    s_swappc_b64 s[30:31], s[18:19]
-; CHECK-NEXT:    s_mov_b64 s[8:9], s[34:35]
+; CHECK-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; CHECK-NEXT:    s_mov_b64 s[6:7], s[34:35]
 ; CHECK-NEXT:    s_mov_b32 s37, s36
 ; CHECK-NEXT:    s_mov_b32 s38, s36
 ; CHECK-NEXT:    s_mov_b32 s39, s36
@@ -79,7 +76,7 @@ define amdgpu_kernel void @blender_no_live_segment_at_def_error(<4 x float> %ext
 ; CHECK-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:4
 ; CHECK-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; CHECK-NEXT:  .LBB0_8: ; %kernel_direct_lighting.exit
-; CHECK-NEXT:    s_load_dwordx2 s[4:5], s[8:9], 0x20
+; CHECK-NEXT:    s_load_dwordx2 s[4:5], s[6:7], 0x20
 ; CHECK-NEXT:    v_mov_b32_e32 v0, s36
 ; CHECK-NEXT:    v_mov_b32_e32 v4, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v1, s37
@@ -125,3 +122,6 @@ kernel_direct_lighting.exit:                      ; preds = %if.end294.i.i, %ent
 }
 
 declare float @_Z3dotDv3_fS_(<3 x float>)
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"amdgpu_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll b/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
index afd43de2eaaf..5a128c7541d1 100644
--- a/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
@@ -5,95 +5,96 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
   ; GFX90A-LABEL: name: f1
   ; GFX90A: bb.0.bb:
   ; GFX90A-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr17, $sgpr12_sgpr13
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr15, $sgpr10_sgpr11
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   $sgpr32 = S_MOV_B32 0
-  ; GFX90A-NEXT:   $flat_scr_lo = S_ADD_U32 $sgpr12, $sgpr17, implicit-def $scc
-  ; GFX90A-NEXT:   $flat_scr_hi = S_ADDC_U32 $sgpr13, 0, implicit-def dead $scc, implicit $scc
-  ; GFX90A-NEXT:   $sgpr0 = S_ADD_U32 $sgpr0, $sgpr17, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   $flat_scr_lo = S_ADD_U32 $sgpr10, $sgpr15, implicit-def $scc
+  ; GFX90A-NEXT:   $flat_scr_hi = S_ADDC_U32 $sgpr11, 0, implicit-def dead $scc, implicit $scc
+  ; GFX90A-NEXT:   $sgpr0 = S_ADD_U32 $sgpr0, $sgpr15, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT:   $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   renamable $sgpr10_sgpr11 = COPY $sgpr8_sgpr9
   ; GFX90A-NEXT:   renamable $vgpr31 = COPY $vgpr0, implicit $exec
-  ; GFX90A-NEXT:   renamable $sgpr33 = S_LOAD_DWORD_IMM renamable $sgpr8_sgpr9, 24, 0 :: (dereferenceable invariant load (s32) from %ir.arg4.kernarg.offset.align.down, align 8, addrspace 4)
-  ; GFX90A-NEXT:   renamable $sgpr20_sgpr21_sgpr22_sgpr23 = S_LOAD_DWORDX4_IMM renamable $sgpr8_sgpr9, 24, 0 :: (dereferenceable invariant load (s128) from %ir.arg6.kernarg.offset.align.down, align 8, addrspace 4)
-  ; GFX90A-NEXT:   renamable $sgpr17 = S_LOAD_DWORD_IMM renamable $sgpr8_sgpr9, 40, 0 :: (dereferenceable invariant load (s32) from %ir.arg6.kernarg.offset.align.down + 16, align 8, addrspace 4)
-  ; GFX90A-NEXT:   renamable $sgpr24_sgpr25_sgpr26_sgpr27 = S_LOAD_DWORDX4_IMM renamable $sgpr8_sgpr9, 0, 0 :: (dereferenceable invariant load (s128) from %ir.arg.kernarg.offset1, addrspace 4)
-  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_LOAD_DWORDX2_IMM renamable $sgpr8_sgpr9, 16, 0 :: (dereferenceable invariant load (s64) from %ir.arg.kernarg.offset1 + 16, align 16, addrspace 4)
+  ; GFX90A-NEXT:   renamable $sgpr33 = S_LOAD_DWORD_IMM renamable $sgpr6_sgpr7, 24, 0 :: (dereferenceable invariant load (s32) from %ir.arg4.kernarg.offset.align.down, align 8, addrspace 4)
+  ; GFX90A-NEXT:   renamable $sgpr20_sgpr21_sgpr22_sgpr23 = S_LOAD_DWORDX4_IMM renamable $sgpr6_sgpr7, 24, 0 :: (dereferenceable invariant load (s128) from %ir.arg6.kernarg.offset.align.down, align 8, addrspace 4)
+  ; GFX90A-NEXT:   renamable $sgpr15 = S_LOAD_DWORD_IMM renamable $sgpr6_sgpr7, 40, 0 :: (dereferenceable invariant load (s32) from %ir.arg6.kernarg.offset.align.down + 16, align 8, addrspace 4)
+  ; GFX90A-NEXT:   renamable $sgpr16_sgpr17_sgpr18_sgpr19 = S_LOAD_DWORDX4_IMM renamable $sgpr6_sgpr7, 0, 0 :: (dereferenceable invariant load (s128) from %ir.arg.kernarg.offset1, addrspace 4)
+  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = S_LOAD_DWORDX2_IMM renamable $sgpr6_sgpr7, 16, 0 :: (dereferenceable invariant load (s64) from %ir.arg.kernarg.offset1 + 16, align 16, addrspace 4)
   ; GFX90A-NEXT:   S_BITCMP1_B32 renamable $sgpr33, 0, implicit-def $scc
-  ; GFX90A-NEXT:   renamable $sgpr12_sgpr13 = S_CSELECT_B64 -1, 0, implicit killed $scc
-  ; GFX90A-NEXT:   renamable $sgpr34_sgpr35 = S_MOV_B64 -1
-  ; GFX90A-NEXT:   renamable $sgpr28_sgpr29 = S_XOR_B64 renamable $sgpr12_sgpr13, -1, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr8_sgpr9 = S_CSELECT_B64 -1, 0, implicit killed $scc
+  ; GFX90A-NEXT:   renamable $sgpr30_sgpr31 = S_MOV_B64 -1
+  ; GFX90A-NEXT:   renamable $sgpr24_sgpr25 = S_XOR_B64 renamable $sgpr8_sgpr9, -1, implicit-def dead $scc
   ; GFX90A-NEXT:   S_BITCMP1_B32 renamable $sgpr33, 8, implicit-def $scc
-  ; GFX90A-NEXT:   renamable $sgpr18_sgpr19 = S_CSELECT_B64 -1, 0, implicit killed $scc
-  ; GFX90A-NEXT:   renamable $sgpr30_sgpr31 = S_XOR_B64 killed renamable $sgpr18_sgpr19, -1, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr26_sgpr27 = S_CSELECT_B64 -1, 0, implicit killed $scc
+  ; GFX90A-NEXT:   renamable $sgpr26_sgpr27 = S_XOR_B64 killed renamable $sgpr26_sgpr27, -1, implicit-def dead $scc
   ; GFX90A-NEXT:   renamable $vgpr3 = V_MOV_B32_e32 0, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr2 = DS_READ_B32_gfx9 renamable $vgpr3, 0, 0, implicit $exec :: (load (s32) from `ptr addrspace(3) null`, align 8, addrspace 3)
-  ; GFX90A-NEXT:   renamable $sgpr18_sgpr19 = S_MOV_B64 0
-  ; GFX90A-NEXT:   renamable $vcc = S_AND_B64 $exec, renamable $sgpr28_sgpr29, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr42_sgpr43 = S_MOV_B64 0
+  ; GFX90A-NEXT:   renamable $vcc = S_AND_B64 $exec, renamable $sgpr24_sgpr25, implicit-def dead $scc
   ; GFX90A-NEXT:   S_CBRANCH_VCCZ %bb.2, implicit $vcc
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.1.bb103:
-  ; GFX90A-NEXT:   successors: %bb.58(0x40000000), %bb.2(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr33, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x00000000000000FF, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000FF, $vgpr2_vgpr3:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   successors: %bb.59(0x40000000), %bb.2(0x40000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr33, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr42_sgpr43, $sgpr54_sgpr55:0x000000000000000F, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000FF, $sgpr20_sgpr21_sgpr22_sgpr23:0x00000000000000FF, $vgpr2_vgpr3:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   renamable $sgpr34_sgpr35 = S_MOV_B64 0
-  ; GFX90A-NEXT:   renamable $vcc = S_AND_B64 $exec, renamable $sgpr30_sgpr31, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr30_sgpr31 = S_MOV_B64 0
+  ; GFX90A-NEXT:   renamable $vcc = S_AND_B64 $exec, renamable $sgpr26_sgpr27, implicit-def dead $scc
   ; GFX90A-NEXT:   $vgpr22 = IMPLICIT_DEF
   ; GFX90A-NEXT:   $vgpr10 = IMPLICIT_DEF
   ; GFX90A-NEXT:   $vgpr24 = IMPLICIT_DEF
   ; GFX90A-NEXT:   $vgpr18 = IMPLICIT_DEF
   ; GFX90A-NEXT:   $vgpr20 = IMPLICIT_DEF
-  ; GFX90A-NEXT:   S_CBRANCH_VCCNZ %bb.58, implicit $vcc
+  ; GFX90A-NEXT:   S_CBRANCH_VCCNZ %bb.59, implicit $vcc
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.2:
   ; GFX90A-NEXT:   successors: %bb.3(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr22, $sgpr33, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8, $sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr56, $sgpr57, $sgpr20_sgpr21_sgpr22, $sgpr24_sgpr25_sgpr26, $sgpr26_sgpr27, $vgpr2, $vgpr3, $vgpr10, $vgpr24, $vgpr18, $vgpr20
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr22, $sgpr33, $vgpr31, $sgpr4_sgpr5, $sgpr6, $sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr30_sgpr31, $sgpr42_sgpr43, $sgpr54, $sgpr55, $sgpr16_sgpr17_sgpr18, $sgpr18_sgpr19, $sgpr20_sgpr21_sgpr22, $vgpr2, $vgpr3, $vgpr10, $vgpr24, $vgpr18, $vgpr20
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   renamable $sgpr17 = IMPLICIT_DEF
+  ; GFX90A-NEXT:   renamable $sgpr15 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $sgpr23 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr11 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr19 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr21 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr23 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr25 = IMPLICIT_DEF
-  ; GFX90A-NEXT:   renamable $sgpr36_sgpr37 = S_MOV_B64 0
+  ; GFX90A-NEXT:   renamable $sgpr28_sgpr29 = S_MOV_B64 0
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.3.Flow17:
-  ; GFX90A-NEXT:   successors: %bb.4(0x40000000), %bb.57(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr23, $sgpr33, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000FF, $vgpr2_vgpr3:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x000000000000000F, $vgpr24_vgpr25:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   successors: %bb.4(0x40000000), %bb.58(0x40000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr23, $sgpr33, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr42_sgpr43, $sgpr54_sgpr55:0x000000000000000F, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000FF, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $vgpr2_vgpr3:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x000000000000000F, $vgpr24_vgpr25:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   renamable $vgpr30 = V_AND_B32_e32 1023, $vgpr31, implicit $exec
-  ; GFX90A-NEXT:   renamable $vcc = S_AND_B64 $exec, killed renamable $sgpr34_sgpr35, implicit-def dead $scc
-  ; GFX90A-NEXT:   S_CBRANCH_VCCZ %bb.57, implicit $vcc
+  ; GFX90A-NEXT:   renamable $vcc = S_AND_B64 $exec, killed renamable $sgpr30_sgpr31, implicit-def dead $scc
+  ; GFX90A-NEXT:   S_CBRANCH_VCCZ %bb.58, implicit $vcc
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.4.bb15:
   ; GFX90A-NEXT:   successors: %bb.35(0x40000000), %bb.5(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $sgpr33, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000FF, $vgpr2_vgpr3:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr18_sgpr19
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr33, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr54_sgpr55:0x000000000000000F, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000FF, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $vgpr2_vgpr3:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr42_sgpr43
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   renamable $vgpr0_vgpr1 = V_LSHLREV_B64_e64 2, $vgpr2_vgpr3, implicit $exec
-  ; GFX90A-NEXT:   renamable $vgpr4 = COPY renamable $sgpr25, implicit $exec
-  ; GFX90A-NEXT:   renamable $vgpr46, renamable $vcc = V_ADD_CO_U32_e64 $sgpr24, $vgpr0, 0, implicit $exec
+  ; GFX90A-NEXT:   renamable $vgpr4 = COPY renamable $sgpr17, implicit $exec
+  ; GFX90A-NEXT:   renamable $vgpr46, renamable $vcc = V_ADD_CO_U32_e64 $sgpr16, $vgpr0, 0, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr47, dead renamable $vcc = V_ADDC_U32_e64 killed $vgpr4, killed $vgpr1, killed $vcc, 0, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr0 = nuw nsw V_LSHLREV_B32_e32 2, $vgpr30, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr40, renamable $vcc = V_ADD_CO_U32_e64 $vgpr46, killed $vgpr0, 0, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr41, dead renamable $vcc = V_ADDC_U32_e64 0, $vgpr47, killed $vcc, 0, implicit $exec
-  ; GFX90A-NEXT:   renamable $vcc = S_AND_B64 $exec, renamable $sgpr30_sgpr31, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $vcc = S_AND_B64 $exec, renamable $sgpr26_sgpr27, implicit-def dead $scc
   ; GFX90A-NEXT:   S_CBRANCH_VCCNZ %bb.35, implicit $vcc
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.5:
   ; GFX90A-NEXT:   successors: %bb.6(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr18_sgpr19
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $vgpr2_vgpr3:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr42_sgpr43
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   renamable $sgpr34_sgpr35 = S_MOV_B64 -1
-  ; GFX90A-NEXT:   renamable $sgpr58_sgpr59 = S_MOV_B64 0
-  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = S_MOV_B64 0
+  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $sgpr52_sgpr53 = S_MOV_B64 0
+  ; GFX90A-NEXT:   renamable $sgpr16_sgpr17 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $sgpr50_sgpr51 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $sgpr48_sgpr49 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $sgpr46_sgpr47 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $sgpr44_sgpr45 = S_MOV_B64 0
-  ; GFX90A-NEXT:   renamable $sgpr42_sgpr43 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $sgpr40_sgpr41 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $sgpr38_sgpr39 = S_MOV_B64 0
+  ; GFX90A-NEXT:   renamable $sgpr36_sgpr37 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $vgpr8_vgpr9 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr6_vgpr7 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr4_vgpr5 = IMPLICIT_DEF
@@ -112,123 +113,120 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
   ; GFX90A-NEXT:   renamable $vgpr53 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr13 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr11 = IMPLICIT_DEF
-  ; GFX90A-NEXT:   renamable $sgpr17 = IMPLICIT_DEF
+  ; GFX90A-NEXT:   renamable $sgpr15 = IMPLICIT_DEF
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.6.Flow20:
   ; GFX90A-NEXT:   successors: %bb.7(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr15, $vgpr17, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr15, $vgpr17, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   renamable $vgpr19 = COPY renamable $sgpr17, implicit $exec
-  ; GFX90A-NEXT:   renamable $vgpr18 = COPY $sgpr17, implicit $exec
-  ; GFX90A-NEXT:   renamable $vgpr21 = COPY $sgpr17, implicit $exec
-  ; GFX90A-NEXT:   renamable $vgpr20 = COPY $sgpr17, implicit $exec
-  ; GFX90A-NEXT:   renamable $vgpr23 = COPY $sgpr17, implicit $exec
-  ; GFX90A-NEXT:   renamable $vgpr22 = COPY $sgpr17, implicit $exec
-  ; GFX90A-NEXT:   renamable $vgpr25 = COPY $sgpr17, implicit $exec
-  ; GFX90A-NEXT:   renamable $vgpr24 = COPY $sgpr17, implicit $exec
+  ; GFX90A-NEXT:   renamable $vgpr19 = COPY renamable $sgpr15, implicit $exec
+  ; GFX90A-NEXT:   renamable $vgpr18 = COPY $sgpr15, implicit $exec
+  ; GFX90A-NEXT:   renamable $vgpr21 = COPY $sgpr15, implicit $exec
+  ; GFX90A-NEXT:   renamable $vgpr20 = COPY $sgpr15, implicit $exec
+  ; GFX90A-NEXT:   renamable $vgpr23 = COPY $sgpr15, implicit $exec
+  ; GFX90A-NEXT:   renamable $vgpr22 = COPY $sgpr15, implicit $exec
+  ; GFX90A-NEXT:   renamable $vgpr25 = COPY $sgpr15, implicit $exec
+  ; GFX90A-NEXT:   renamable $vgpr24 = COPY $sgpr15, implicit $exec
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.7.Flow19:
-  ; GFX90A-NEXT:   successors: %bb.62(0x40000000), %bb.8(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr15, $vgpr17, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x000000000000000F, $vgpr24_vgpr25:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   successors: %bb.63(0x40000000), %bb.8(0x40000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr15, $vgpr17, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x000000000000000F, $vgpr24_vgpr25:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_MOV_B64 0
-  ; GFX90A-NEXT:   $sgpr24_sgpr25 = S_AND_SAVEEXEC_B64 $sgpr36_sgpr37, implicit-def $exec, implicit-def $scc, implicit $exec
-  ; GFX90A-NEXT:   S_CBRANCH_EXECNZ %bb.62, implicit $exec
+  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = S_MOV_B64 0
+  ; GFX90A-NEXT:   $sgpr30_sgpr31 = S_AND_SAVEEXEC_B64 $sgpr28_sgpr29, implicit-def $exec, implicit-def $scc, implicit $exec
+  ; GFX90A-NEXT:   S_CBRANCH_EXECNZ %bb.63, implicit $exec
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.8.Flow32:
   ; GFX90A-NEXT:   successors: %bb.9(0x40000000), %bb.10(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr56_sgpr57, $sgpr58_sgpr59, $vgpr0_vgpr1:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr56_sgpr57, $vgpr0_vgpr1:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr24_sgpr25, implicit-def $scc
-  ; GFX90A-NEXT:   $sgpr12_sgpr13 = S_AND_SAVEEXEC_B64 $sgpr18_sgpr19, implicit-def $exec, implicit-def $scc, implicit $exec
-  ; GFX90A-NEXT:   renamable $sgpr12_sgpr13 = S_XOR_B64 $exec, killed renamable $sgpr12_sgpr13, implicit-def dead $scc
+  ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr30_sgpr31, implicit-def $scc
+  ; GFX90A-NEXT:   $sgpr8_sgpr9 = S_AND_SAVEEXEC_B64 $sgpr42_sgpr43, implicit-def $exec, implicit-def $scc, implicit $exec
+  ; GFX90A-NEXT:   renamable $sgpr8_sgpr9 = S_XOR_B64 $exec, killed renamable $sgpr8_sgpr9, implicit-def dead $scc
   ; GFX90A-NEXT:   S_CBRANCH_EXECZ %bb.10, implicit $exec
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.9.bb89:
   ; GFX90A-NEXT:   successors: %bb.10(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr56_sgpr57, $sgpr58_sgpr59, $vgpr0_vgpr1:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr56_sgpr57, $vgpr0_vgpr1:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   BUFFER_STORE_DWORD_OFFSET renamable $vgpr9, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null` + 4, basealign 8, addrspace 5)
   ; GFX90A-NEXT:   BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null`, align 8, addrspace 5)
-  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_OR_B64 killed renamable $sgpr56_sgpr57, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = S_OR_B64 killed renamable $sgpr54_sgpr55, $exec, implicit-def dead $scc
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.10.Flow33:
   ; GFX90A-NEXT:   successors: %bb.11(0x40000000), %bb.12(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr56_sgpr57, $sgpr58_sgpr59, $vgpr0_vgpr1:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr56_sgpr57, $vgpr0_vgpr1:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr12_sgpr13, implicit-def $scc
-  ; GFX90A-NEXT:   $sgpr12_sgpr13 = S_AND_SAVEEXEC_B64 $sgpr58_sgpr59, implicit-def $exec, implicit-def $scc, implicit $exec
-  ; GFX90A-NEXT:   renamable $sgpr12_sgpr13 = S_XOR_B64 $exec, killed renamable $sgpr12_sgpr13, implicit-def dead $scc
+  ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr8_sgpr9, implicit-def $scc
+  ; GFX90A-NEXT:   $sgpr8_sgpr9 = S_AND_SAVEEXEC_B64 $sgpr56_sgpr57, implicit-def $exec, implicit-def $scc, implicit $exec
+  ; GFX90A-NEXT:   renamable $sgpr8_sgpr9 = S_XOR_B64 $exec, killed renamable $sgpr8_sgpr9, implicit-def dead $scc
   ; GFX90A-NEXT:   S_CBRANCH_EXECZ %bb.12, implicit $exec
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.11.bb84:
   ; GFX90A-NEXT:   successors: %bb.12(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr56_sgpr57, $vgpr0_vgpr1:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $vgpr0_vgpr1:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   BUFFER_STORE_DWORD_OFFSET renamable $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null` + 4, basealign 8, addrspace 5)
   ; GFX90A-NEXT:   BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null`, align 8, addrspace 5)
-  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_OR_B64 killed renamable $sgpr56_sgpr57, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = S_OR_B64 killed renamable $sgpr54_sgpr55, $exec, implicit-def dead $scc
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.12.Flow34:
   ; GFX90A-NEXT:   successors: %bb.13(0x40000000), %bb.14(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr56_sgpr57, $vgpr0_vgpr1:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $vgpr0_vgpr1:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr12_sgpr13, implicit-def $scc
-  ; GFX90A-NEXT:   $sgpr12_sgpr13 = S_AND_SAVEEXEC_B64 $sgpr54_sgpr55, implicit-def $exec, implicit-def $scc, implicit $exec
-  ; GFX90A-NEXT:   renamable $sgpr12_sgpr13 = S_XOR_B64 $exec, killed renamable $sgpr12_sgpr13, implicit-def dead $scc
+  ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr8_sgpr9, implicit-def $scc
+  ; GFX90A-NEXT:   $sgpr8_sgpr9 = S_AND_SAVEEXEC_B64 $sgpr52_sgpr53, implicit-def $exec, implicit-def $scc, implicit $exec
+  ; GFX90A-NEXT:   renamable $sgpr8_sgpr9 = S_XOR_B64 $exec, killed renamable $sgpr8_sgpr9, implicit-def dead $scc
   ; GFX90A-NEXT:   S_CBRANCH_EXECZ %bb.14, implicit $exec
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.13.bb79:
   ; GFX90A-NEXT:   successors: %bb.14(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $vgpr0_vgpr1:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr54_sgpr55, $vgpr0_vgpr1:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   BUFFER_STORE_DWORD_OFFSET renamable $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null` + 4, basealign 8, addrspace 5)
   ; GFX90A-NEXT:   BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null`, align 8, addrspace 5)
-  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_OR_B64 killed renamable $sgpr56_sgpr57, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = S_OR_B64 killed renamable $sgpr54_sgpr55, $exec, implicit-def dead $scc
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.14.Flow35:
   ; GFX90A-NEXT:   successors: %bb.15(0x40000000), %bb.16(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $vgpr0_vgpr1:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr54_sgpr55, $vgpr0_vgpr1:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr12_sgpr13, implicit-def $scc
-  ; GFX90A-NEXT:   $sgpr12_sgpr13 = S_AND_SAVEEXEC_B64 $sgpr52_sgpr53, implicit-def $exec, implicit-def $scc, implicit $exec
-  ; GFX90A-NEXT:   renamable $sgpr36_sgpr37 = S_XOR_B64 $exec, killed renamable $sgpr12_sgpr13, implicit-def dead $scc
+  ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr8_sgpr9, implicit-def $scc
+  ; GFX90A-NEXT:   $sgpr8_sgpr9 = S_AND_SAVEEXEC_B64 $sgpr16_sgpr17, implicit-def $exec, implicit-def $scc, implicit $exec
+  ; GFX90A-NEXT:   renamable $sgpr42_sgpr43 = S_XOR_B64 $exec, killed renamable $sgpr8_sgpr9, implicit-def dead $scc
   ; GFX90A-NEXT:   S_CBRANCH_EXECZ %bb.16, implicit $exec
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.15.bb72:
   ; GFX90A-NEXT:   successors: %bb.16(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $vgpr0_vgpr1:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
-  ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   renamable $sgpr8 = S_ADD_U32 renamable $sgpr8, 48, implicit-def $scc
-  ; GFX90A-NEXT:   renamable $sgpr9 = S_ADDC_U32 killed renamable $sgpr9, 0, implicit-def dead $scc, implicit killed $scc
-  ; GFX90A-NEXT:   renamable $sgpr12_sgpr13 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @f2, target-flags(amdgpu-gotprel32-hi) @f2, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr18_sgpr19 = S_LOAD_DWORDX2_IMM killed renamable $sgpr12_sgpr13, 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
-  ; GFX90A-NEXT:   $sgpr12 = COPY killed renamable $sgpr14
-  ; GFX90A-NEXT:   $sgpr13 = COPY killed renamable $sgpr15
-  ; GFX90A-NEXT:   $sgpr14 = COPY killed renamable $sgpr16
-  ; GFX90A-NEXT:   dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr18_sgpr19, @f2, csr_amdgpu_gfx90ainsts, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit undef $sgpr15, implicit $vgpr31, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $vgpr0, implicit $vgpr1
-  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_OR_B64 killed renamable $sgpr56_sgpr57, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr10_sgpr11, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr54_sgpr55, $vgpr0_vgpr1:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT: {{  $}}
+  ; GFX90A-NEXT:   renamable $sgpr8 = S_ADD_U32 renamable $sgpr6, 48, implicit-def $scc
+  ; GFX90A-NEXT:   renamable $sgpr9 = S_ADDC_U32 killed renamable $sgpr7, 0, implicit-def dead $scc, implicit killed $scc
+  ; GFX90A-NEXT:   renamable $sgpr6_sgpr7 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @f2, target-flags(amdgpu-gotprel32-hi) @f2, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr6_sgpr7 = S_LOAD_DWORDX2_IMM killed renamable $sgpr6_sgpr7, 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
+  ; GFX90A-NEXT:   dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr6_sgpr7, @f2, csr_amdgpu_gfx90ainsts, implicit $sgpr4_sgpr5, implicit undef $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit undef $sgpr15, implicit $vgpr31, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $vgpr0, implicit $vgpr1
+  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = S_OR_B64 killed renamable $sgpr54_sgpr55, $exec, implicit-def dead $scc
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.16.Flow36:
   ; GFX90A-NEXT:   successors: %bb.17(0x40000000), %bb.18(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr54_sgpr55, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr36_sgpr37, implicit-def $scc
+  ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr42_sgpr43, implicit-def $scc
   ; GFX90A-NEXT:   $sgpr4_sgpr5 = S_AND_SAVEEXEC_B64 $sgpr50_sgpr51, implicit-def $exec, implicit-def $scc, implicit $exec
   ; GFX90A-NEXT:   renamable $sgpr4_sgpr5 = S_XOR_B64 $exec, killed renamable $sgpr4_sgpr5, implicit-def dead $scc
   ; GFX90A-NEXT:   S_CBRANCH_EXECZ %bb.18, implicit $exec
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.17.bb67:
   ; GFX90A-NEXT:   successors: %bb.18(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr56_sgpr57, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr54_sgpr55, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   BUFFER_STORE_DWORD_OFFSET renamable $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null` + 4, basealign 8, addrspace 5)
   ; GFX90A-NEXT:   BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null`, align 8, addrspace 5)
-  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_OR_B64 killed renamable $sgpr56_sgpr57, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = S_OR_B64 killed renamable $sgpr54_sgpr55, $exec, implicit-def dead $scc
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.18.Flow37:
   ; GFX90A-NEXT:   successors: %bb.19(0x40000000), %bb.20(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr56_sgpr57, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr54_sgpr55, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr4_sgpr5, implicit-def $scc
   ; GFX90A-NEXT:   $sgpr4_sgpr5 = S_AND_SAVEEXEC_B64 $sgpr48_sgpr49, implicit-def $exec, implicit-def $scc, implicit $exec
@@ -237,15 +235,15 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.19.bb62:
   ; GFX90A-NEXT:   successors: %bb.20(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr56_sgpr57, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr54_sgpr55, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   BUFFER_STORE_DWORD_OFFSET renamable $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null` + 4, basealign 8, addrspace 5)
   ; GFX90A-NEXT:   BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null`, align 8, addrspace 5)
-  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_OR_B64 killed renamable $sgpr56_sgpr57, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = S_OR_B64 killed renamable $sgpr54_sgpr55, $exec, implicit-def dead $scc
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.20.Flow38:
   ; GFX90A-NEXT:   successors: %bb.21(0x40000000), %bb.22(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr56_sgpr57, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr54_sgpr55, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr4_sgpr5, implicit-def $scc
   ; GFX90A-NEXT:   $sgpr4_sgpr5 = S_AND_SAVEEXEC_B64 $sgpr46_sgpr47, implicit-def $exec, implicit-def $scc, implicit $exec
@@ -254,15 +252,15 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.21.bb54:
   ; GFX90A-NEXT:   successors: %bb.22(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr56_sgpr57, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr44_sgpr45, $sgpr54_sgpr55, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   BUFFER_STORE_DWORD_OFFSET renamable $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null` + 4, basealign 8, addrspace 5)
   ; GFX90A-NEXT:   BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null`, align 8, addrspace 5)
-  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_OR_B64 killed renamable $sgpr56_sgpr57, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = S_OR_B64 killed renamable $sgpr54_sgpr55, $exec, implicit-def dead $scc
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.22.Flow39:
   ; GFX90A-NEXT:   successors: %bb.23(0x40000000), %bb.24(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr56_sgpr57, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr44_sgpr45, $sgpr54_sgpr55, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr4_sgpr5, implicit-def $scc
   ; GFX90A-NEXT:   $sgpr4_sgpr5 = S_AND_SAVEEXEC_B64 $sgpr44_sgpr45, implicit-def $exec, implicit-def $scc, implicit $exec
@@ -271,58 +269,58 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.23.bb47:
   ; GFX90A-NEXT:   successors: %bb.24(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr56_sgpr57, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr54_sgpr55, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   BUFFER_STORE_DWORD_OFFSET renamable $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null` + 4, basealign 8, addrspace 5)
   ; GFX90A-NEXT:   BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null`, align 8, addrspace 5)
-  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_OR_B64 killed renamable $sgpr56_sgpr57, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = S_OR_B64 killed renamable $sgpr54_sgpr55, $exec, implicit-def dead $scc
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.24.Flow40:
   ; GFX90A-NEXT:   successors: %bb.25(0x40000000), %bb.26(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr56_sgpr57, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr54_sgpr55, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr4_sgpr5, implicit-def $scc
-  ; GFX90A-NEXT:   $sgpr4_sgpr5 = S_AND_SAVEEXEC_B64 $sgpr42_sgpr43, implicit-def $exec, implicit-def $scc, implicit $exec
+  ; GFX90A-NEXT:   $sgpr4_sgpr5 = S_AND_SAVEEXEC_B64 $sgpr40_sgpr41, implicit-def $exec, implicit-def $scc, implicit $exec
   ; GFX90A-NEXT:   renamable $sgpr4_sgpr5 = S_XOR_B64 $exec, killed renamable $sgpr4_sgpr5, implicit-def dead $scc
   ; GFX90A-NEXT:   S_CBRANCH_EXECZ %bb.26, implicit $exec
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.25.bb40:
   ; GFX90A-NEXT:   successors: %bb.26(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr56_sgpr57, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr54_sgpr55, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   BUFFER_STORE_DWORD_OFFSET renamable $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null` + 4, basealign 8, addrspace 5)
   ; GFX90A-NEXT:   BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null`, align 8, addrspace 5)
-  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_OR_B64 killed renamable $sgpr56_sgpr57, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = S_OR_B64 killed renamable $sgpr54_sgpr55, $exec, implicit-def dead $scc
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.26.Flow41:
   ; GFX90A-NEXT:   successors: %bb.27(0x40000000), %bb.28(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr56_sgpr57, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr54_sgpr55, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr4_sgpr5, implicit-def $scc
-  ; GFX90A-NEXT:   $sgpr4_sgpr5 = S_AND_SAVEEXEC_B64 $sgpr40_sgpr41, implicit-def $exec, implicit-def $scc, implicit $exec
+  ; GFX90A-NEXT:   $sgpr4_sgpr5 = S_AND_SAVEEXEC_B64 $sgpr38_sgpr39, implicit-def $exec, implicit-def $scc, implicit $exec
   ; GFX90A-NEXT:   renamable $sgpr4_sgpr5 = S_XOR_B64 $exec, killed renamable $sgpr4_sgpr5, implicit-def dead $scc
   ; GFX90A-NEXT:   S_CBRANCH_EXECZ %bb.28, implicit $exec
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.27.bb33:
   ; GFX90A-NEXT:   successors: %bb.28(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr56_sgpr57, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr54_sgpr55, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   BUFFER_STORE_DWORD_OFFSET renamable $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null` + 4, basealign 8, addrspace 5)
   ; GFX90A-NEXT:   BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null`, align 8, addrspace 5)
-  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_OR_B64 killed renamable $sgpr56_sgpr57, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = S_OR_B64 killed renamable $sgpr54_sgpr55, $exec, implicit-def dead $scc
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.28.Flow42:
   ; GFX90A-NEXT:   successors: %bb.34(0x40000000), %bb.29(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr56_sgpr57, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr54_sgpr55, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr4_sgpr5, implicit-def $scc
-  ; GFX90A-NEXT:   $sgpr4_sgpr5 = S_AND_SAVEEXEC_B64 $sgpr38_sgpr39, implicit-def $exec, implicit-def $scc, implicit $exec
+  ; GFX90A-NEXT:   $sgpr4_sgpr5 = S_AND_SAVEEXEC_B64 $sgpr36_sgpr37, implicit-def $exec, implicit-def $scc, implicit $exec
   ; GFX90A-NEXT:   renamable $sgpr4_sgpr5 = S_XOR_B64 $exec, killed renamable $sgpr4_sgpr5, implicit-def dead $scc
   ; GFX90A-NEXT:   S_CBRANCH_EXECNZ %bb.34, implicit $exec
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.29.Flow43:
   ; GFX90A-NEXT:   successors: %bb.30(0x40000000), %bb.31(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr34_sgpr35, $sgpr56_sgpr57, $vgpr40_vgpr41:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr34_sgpr35, $sgpr54_sgpr55, $vgpr40_vgpr41:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr4_sgpr5, implicit-def $scc
   ; GFX90A-NEXT:   $vcc = S_ANDN2_B64 $exec, killed renamable $sgpr34_sgpr35, implicit-def dead $scc
@@ -330,17 +328,17 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.30.bb19:
   ; GFX90A-NEXT:   successors: %bb.31(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr56_sgpr57, $vgpr40_vgpr41:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr54_sgpr55, $vgpr40_vgpr41:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   BUFFER_STORE_DWORD_OFFSET renamable $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null` + 4, basealign 8, addrspace 5)
   ; GFX90A-NEXT:   BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null`, align 8, addrspace 5)
-  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_OR_B64 killed renamable $sgpr56_sgpr57, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = S_OR_B64 killed renamable $sgpr54_sgpr55, $exec, implicit-def dead $scc
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.31.Flow44:
   ; GFX90A-NEXT:   successors: %bb.32(0x40000000), %bb.33(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr56_sgpr57, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr54_sgpr55, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   $sgpr4_sgpr5 = S_AND_SAVEEXEC_B64 $sgpr56_sgpr57, implicit-def $exec, implicit-def $scc, implicit $exec
+  ; GFX90A-NEXT:   $sgpr4_sgpr5 = S_AND_SAVEEXEC_B64 $sgpr54_sgpr55, implicit-def $exec, implicit-def $scc, implicit $exec
   ; GFX90A-NEXT:   S_CBRANCH_EXECZ %bb.33, implicit $exec
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.32.UnifiedUnreachableBlock:
@@ -356,32 +354,32 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.34.bb26:
   ; GFX90A-NEXT:   successors: %bb.29(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr34_sgpr35, $sgpr56_sgpr57, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr34_sgpr35, $sgpr54_sgpr55, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   BUFFER_STORE_DWORD_OFFSET renamable $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null` + 4, basealign 8, addrspace 5)
   ; GFX90A-NEXT:   BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null`, align 8, addrspace 5)
-  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_OR_B64 killed renamable $sgpr56_sgpr57, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = S_OR_B64 killed renamable $sgpr54_sgpr55, $exec, implicit-def dead $scc
   ; GFX90A-NEXT:   S_BRANCH %bb.29
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.35.bb20:
   ; GFX90A-NEXT:   successors: %bb.37(0x40000000), %bb.36(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $sgpr33, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr18_sgpr19
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr33, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr54_sgpr55:0x000000000000000F, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $vgpr2_vgpr3:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr42_sgpr43
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   renamable $vgpr0 = GLOBAL_LOAD_SBYTE renamable $vgpr40_vgpr41, 1024, 0, implicit $exec :: (load (s8) from %ir.i21, addrspace 1)
   ; GFX90A-NEXT:   renamable $vgpr42 = V_ADD_CO_U32_e32 1024, $vgpr40, implicit-def $vcc, implicit $exec
   ; GFX90A-NEXT:   renamable $sgpr34_sgpr35 = S_MOV_B64 0
-  ; GFX90A-NEXT:   renamable $sgpr38_sgpr39 = S_MOV_B64 -1
-  ; GFX90A-NEXT:   renamable $sgpr58_sgpr59 = S_MOV_B64 0
-  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = S_MOV_B64 0
+  ; GFX90A-NEXT:   renamable $sgpr36_sgpr37 = S_MOV_B64 -1
+  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $sgpr52_sgpr53 = S_MOV_B64 0
+  ; GFX90A-NEXT:   renamable $sgpr16_sgpr17 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $sgpr50_sgpr51 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $sgpr48_sgpr49 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $sgpr46_sgpr47 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $sgpr44_sgpr45 = S_MOV_B64 0
-  ; GFX90A-NEXT:   renamable $sgpr42_sgpr43 = S_MOV_B64 0
+  ; GFX90A-NEXT:   renamable $sgpr40_sgpr41 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $vgpr43, dead renamable $vcc = V_ADDC_U32_e64 0, $vgpr41, killed $vcc, 0, implicit $exec
   ; GFX90A-NEXT:   renamable $vcc = V_CMP_LT_I16_e64 0, killed $vgpr0, implicit $exec
-  ; GFX90A-NEXT:   renamable $sgpr40_sgpr41 = S_MOV_B64 0
+  ; GFX90A-NEXT:   renamable $sgpr38_sgpr39 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $vgpr8_vgpr9 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr6_vgpr7 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr4_vgpr5 = IMPLICIT_DEF
@@ -399,27 +397,29 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
   ; GFX90A-NEXT:   renamable $vgpr53 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr13 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr11 = IMPLICIT_DEF
-  ; GFX90A-NEXT:   renamable $sgpr17 = IMPLICIT_DEF
-  ; GFX90A-NEXT:   $sgpr24_sgpr25 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
+  ; GFX90A-NEXT:   renamable $sgpr15 = IMPLICIT_DEF
+  ; GFX90A-NEXT:   $sgpr30_sgpr31 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
   ; GFX90A-NEXT:   S_CBRANCH_EXECNZ %bb.37, implicit $exec
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.36.Flow21:
   ; GFX90A-NEXT:   successors: %bb.6(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr15, $vgpr17, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr15, $vgpr17, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr24_sgpr25, implicit-def $scc
+  ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr30_sgpr31, implicit-def $scc
   ; GFX90A-NEXT:   S_BRANCH %bb.6
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.37.bb27:
   ; GFX90A-NEXT:   successors: %bb.39(0x40000000), %bb.38(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $sgpr33, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr18_sgpr19, $sgpr58_sgpr59, $sgpr54_sgpr55, $sgpr52_sgpr53, $sgpr50_sgpr51, $sgpr48_sgpr49, $sgpr46_sgpr47, $sgpr44_sgpr45, $sgpr42_sgpr43
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr33, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr54_sgpr55:0x000000000000000F, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $vgpr2_vgpr3:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr42_sgpr43, $sgpr56_sgpr57, $sgpr52_sgpr53, $sgpr50_sgpr51, $sgpr48_sgpr49, $sgpr46_sgpr47, $sgpr44_sgpr45, $sgpr40_sgpr41
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   renamable $vgpr0 = GLOBAL_LOAD_UBYTE renamable $vgpr40_vgpr41, 2048, 0, implicit $exec :: (load (s8) from %ir.i28, addrspace 1)
   ; GFX90A-NEXT:   renamable $vgpr44 = V_ADD_CO_U32_e32 2048, $vgpr40, implicit-def $vcc, implicit $exec
-  ; GFX90A-NEXT:   renamable $sgpr40_sgpr41 = S_MOV_B64 -1
-  ; GFX90A-NEXT:   renamable $sgpr60_sgpr61 = COPY renamable $sgpr36_sgpr37
+  ; GFX90A-NEXT:   renamable $sgpr16_sgpr17 = S_MOV_B64 -1
+  ; GFX90A-NEXT:   renamable $sgpr58_sgpr59 = COPY renamable $sgpr28_sgpr29
+  ; GFX90A-NEXT:   renamable $sgpr60_sgpr61 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $vgpr45, dead renamable $vcc = V_ADDC_U32_e64 0, $vgpr41, killed $vcc, 0, implicit $exec
   ; GFX90A-NEXT:   renamable $vcc = V_CMP_EQ_U16_e64 0, killed $vgpr0, implicit $exec
+  ; GFX90A-NEXT:   renamable $sgpr62_sgpr63 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $vgpr8_vgpr9 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr6_vgpr7 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr4_vgpr5 = IMPLICIT_DEF
@@ -436,39 +436,39 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
   ; GFX90A-NEXT:   renamable $vgpr53 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr13 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr11 = IMPLICIT_DEF
-  ; GFX90A-NEXT:   renamable $sgpr17 = IMPLICIT_DEF
-  ; GFX90A-NEXT:   $sgpr38_sgpr39 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
+  ; GFX90A-NEXT:   renamable $sgpr15 = IMPLICIT_DEF
+  ; GFX90A-NEXT:   $sgpr36_sgpr37 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
   ; GFX90A-NEXT:   S_CBRANCH_EXECNZ %bb.39, implicit $exec
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.38.Flow22:
   ; GFX90A-NEXT:   successors: %bb.36(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr15, $vgpr17, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr15, $vgpr17, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr38_sgpr39, implicit-def $scc
-  ; GFX90A-NEXT:   renamable $sgpr38_sgpr39 = S_XOR_B64 $exec, -1, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr40_sgpr41 = S_AND_B64 killed renamable $sgpr40_sgpr41, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr42_sgpr43 = S_AND_B64 killed renamable $sgpr42_sgpr43, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr36_sgpr37, implicit-def $scc
+  ; GFX90A-NEXT:   renamable $sgpr36_sgpr37 = S_XOR_B64 $exec, -1, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr38_sgpr39 = S_AND_B64 killed renamable $sgpr16_sgpr17, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr40_sgpr41 = S_AND_B64 killed renamable $sgpr62_sgpr63, $exec, implicit-def dead $scc
   ; GFX90A-NEXT:   renamable $sgpr44_sgpr45 = S_AND_B64 killed renamable $sgpr44_sgpr45, $exec, implicit-def dead $scc
   ; GFX90A-NEXT:   renamable $sgpr46_sgpr47 = S_AND_B64 killed renamable $sgpr46_sgpr47, $exec, implicit-def dead $scc
   ; GFX90A-NEXT:   renamable $sgpr48_sgpr49 = S_AND_B64 killed renamable $sgpr48_sgpr49, $exec, implicit-def dead $scc
   ; GFX90A-NEXT:   renamable $sgpr50_sgpr51 = S_AND_B64 killed renamable $sgpr50_sgpr51, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr16_sgpr17 = S_AND_B64 killed renamable $sgpr60_sgpr61, $exec, implicit-def dead $scc
   ; GFX90A-NEXT:   renamable $sgpr52_sgpr53 = S_AND_B64 killed renamable $sgpr52_sgpr53, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = S_AND_B64 killed renamable $sgpr54_sgpr55, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr58_sgpr59 = S_AND_B64 killed renamable $sgpr58_sgpr59, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr18_sgpr19 = S_AND_B64 killed renamable $sgpr18_sgpr19, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr36_sgpr37 = S_ANDN2_B64 killed renamable $sgpr36_sgpr37, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_AND_B64 killed renamable $sgpr60_sgpr61, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr36_sgpr37 = S_OR_B64 killed renamable $sgpr36_sgpr37, killed renamable $sgpr56_sgpr57, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_AND_B64 killed renamable $sgpr56_sgpr57, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr42_sgpr43 = S_AND_B64 killed renamable $sgpr42_sgpr43, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr28_sgpr29 = S_ANDN2_B64 killed renamable $sgpr28_sgpr29, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = S_AND_B64 killed renamable $sgpr58_sgpr59, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr28_sgpr29 = S_OR_B64 killed renamable $sgpr28_sgpr29, killed renamable $sgpr54_sgpr55, implicit-def dead $scc
   ; GFX90A-NEXT:   S_BRANCH %bb.36
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.39.bb34:
   ; GFX90A-NEXT:   successors: %bb.41(0x40000000), %bb.40(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $sgpr33, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr18_sgpr19, $sgpr58_sgpr59, $sgpr54_sgpr55, $sgpr52_sgpr53, $sgpr50_sgpr51, $sgpr48_sgpr49, $sgpr46_sgpr47, $sgpr44_sgpr45
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr33, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr54_sgpr55:0x000000000000000F, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $vgpr2_vgpr3:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr40_sgpr41, $sgpr56_sgpr57, $sgpr52_sgpr53, $sgpr60_sgpr61, $sgpr50_sgpr51, $sgpr48_sgpr49, $sgpr46_sgpr47, $sgpr44_sgpr45
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   renamable $vgpr0 = GLOBAL_LOAD_UBYTE renamable $vgpr40_vgpr41, 3072, 0, implicit $exec :: (load (s8) from %ir.i35, addrspace 1)
   ; GFX90A-NEXT:   renamable $vgpr56 = V_ADD_CO_U32_e32 3072, $vgpr40, implicit-def $vcc, implicit $exec
   ; GFX90A-NEXT:   renamable $sgpr42_sgpr43 = S_MOV_B64 -1
-  ; GFX90A-NEXT:   renamable $sgpr60_sgpr61 = COPY renamable $sgpr36_sgpr37
+  ; GFX90A-NEXT:   renamable $sgpr58_sgpr59 = COPY renamable $sgpr28_sgpr29
   ; GFX90A-NEXT:   renamable $vgpr57, dead renamable $vcc = V_ADDC_U32_e64 0, $vgpr41, killed $vcc, 0, implicit $exec
   ; GFX90A-NEXT:   renamable $vcc = V_CMP_EQ_U16_e64 0, killed $vgpr0, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr8_vgpr9 = IMPLICIT_DEF
@@ -486,44 +486,43 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
   ; GFX90A-NEXT:   renamable $vgpr53 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr13 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr11 = IMPLICIT_DEF
-  ; GFX90A-NEXT:   renamable $sgpr17 = IMPLICIT_DEF
-  ; GFX90A-NEXT:   $sgpr40_sgpr41 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
+  ; GFX90A-NEXT:   renamable $sgpr15 = IMPLICIT_DEF
+  ; GFX90A-NEXT:   $sgpr38_sgpr39 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
   ; GFX90A-NEXT:   S_CBRANCH_EXECNZ %bb.41, implicit $exec
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.40.Flow23:
   ; GFX90A-NEXT:   successors: %bb.38(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr15, $vgpr17, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr15, $vgpr17, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr40_sgpr41, implicit-def $scc
-  ; GFX90A-NEXT:   renamable $sgpr40_sgpr41 = S_XOR_B64 $exec, -1, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr42_sgpr43 = S_AND_B64 killed renamable $sgpr42_sgpr43, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr38_sgpr39, implicit-def $scc
+  ; GFX90A-NEXT:   renamable $sgpr16_sgpr17 = S_XOR_B64 $exec, -1, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr62_sgpr63 = S_AND_B64 killed renamable $sgpr42_sgpr43, $exec, implicit-def dead $scc
   ; GFX90A-NEXT:   renamable $sgpr44_sgpr45 = S_AND_B64 killed renamable $sgpr44_sgpr45, $exec, implicit-def dead $scc
   ; GFX90A-NEXT:   renamable $sgpr46_sgpr47 = S_AND_B64 killed renamable $sgpr46_sgpr47, $exec, implicit-def dead $scc
   ; GFX90A-NEXT:   renamable $sgpr48_sgpr49 = S_AND_B64 killed renamable $sgpr48_sgpr49, $exec, implicit-def dead $scc
   ; GFX90A-NEXT:   renamable $sgpr50_sgpr51 = S_AND_B64 killed renamable $sgpr50_sgpr51, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr52_sgpr53 = S_AND_B64 killed renamable $sgpr52_sgpr53, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = S_AND_B64 killed renamable $sgpr54_sgpr55, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr58_sgpr59 = S_AND_B64 killed renamable $sgpr58_sgpr59, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr18_sgpr19 = S_AND_B64 killed renamable $sgpr18_sgpr19, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_ANDN2_B64 renamable $sgpr36_sgpr37, $exec, implicit-def dead $scc
   ; GFX90A-NEXT:   renamable $sgpr60_sgpr61 = S_AND_B64 killed renamable $sgpr60_sgpr61, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr60_sgpr61 = S_OR_B64 killed renamable $sgpr56_sgpr57, killed renamable $sgpr60_sgpr61, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr52_sgpr53 = S_AND_B64 killed renamable $sgpr52_sgpr53, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_AND_B64 killed renamable $sgpr56_sgpr57, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr42_sgpr43 = S_AND_B64 killed renamable $sgpr40_sgpr41, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr38_sgpr39 = S_ANDN2_B64 renamable $sgpr28_sgpr29, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr40_sgpr41 = S_AND_B64 killed renamable $sgpr58_sgpr59, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr58_sgpr59 = S_OR_B64 killed renamable $sgpr38_sgpr39, killed renamable $sgpr40_sgpr41, implicit-def dead $scc
   ; GFX90A-NEXT:   S_BRANCH %bb.38
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.41.bb41:
-  ; GFX90A-NEXT:   successors: %bb.46(0x40000000), %bb.42(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $sgpr33, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr58_sgpr59, $sgpr54_sgpr55, $sgpr52_sgpr53, $sgpr50_sgpr51, $sgpr48_sgpr49, $sgpr46_sgpr47
+  ; GFX90A-NEXT:   successors: %bb.47(0x40000000), %bb.42(0x40000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr33, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr54_sgpr55:0x000000000000000F, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $vgpr2_vgpr3:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr56_sgpr57, $sgpr52_sgpr53, $sgpr60_sgpr61, $sgpr50_sgpr51, $sgpr48_sgpr49, $sgpr46_sgpr47
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   renamable $vgpr58 = V_ADD_CO_U32_e32 4096, $vgpr40, implicit-def $vcc, implicit $exec
-  ; GFX90A-NEXT:   renamable $sgpr18_sgpr19 = COPY $vcc
-  ; GFX90A-NEXT:   renamable $vgpr59, dead renamable $sgpr18_sgpr19 = V_ADDC_U32_e64 0, $vgpr41, killed $sgpr18_sgpr19, 0, implicit $exec
+  ; GFX90A-NEXT:   renamable $sgpr16_sgpr17 = COPY $vcc
+  ; GFX90A-NEXT:   renamable $vgpr59, dead renamable $sgpr16_sgpr17 = V_ADDC_U32_e64 0, $vgpr41, killed $sgpr16_sgpr17, 0, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr0 = GLOBAL_LOAD_UBYTE renamable $vgpr58_vgpr59, 0, 0, implicit $exec :: (load (s8) from %ir.i42, addrspace 1)
-  ; GFX90A-NEXT:   renamable $sgpr18_sgpr19 = S_MOV_B64 0
+  ; GFX90A-NEXT:   renamable $sgpr16_sgpr17 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $sgpr44_sgpr45 = S_MOV_B64 -1
-  ; GFX90A-NEXT:   renamable $sgpr60_sgpr61 = COPY renamable $sgpr36_sgpr37
+  ; GFX90A-NEXT:   renamable $sgpr58_sgpr59 = COPY renamable $sgpr28_sgpr29
   ; GFX90A-NEXT:   renamable $vgpr18, dead renamable $vcc = V_ADDC_U32_e64 0, $vgpr41, killed $vcc, 0, implicit $exec
   ; GFX90A-NEXT:   renamable $vcc = V_CMP_EQ_U16_e64 0, killed $vgpr0, implicit $exec
-  ; GFX90A-NEXT:   renamable $sgpr62_sgpr63 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $vgpr8_vgpr9 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr6_vgpr7 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr4_vgpr5 = IMPLICIT_DEF
@@ -538,49 +537,48 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
   ; GFX90A-NEXT:   renamable $vgpr53 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr13 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr11 = IMPLICIT_DEF
-  ; GFX90A-NEXT:   renamable $sgpr17 = IMPLICIT_DEF
-  ; GFX90A-NEXT:   $sgpr42_sgpr43 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
-  ; GFX90A-NEXT:   S_CBRANCH_EXECNZ %bb.46, implicit $exec
+  ; GFX90A-NEXT:   renamable $sgpr15 = IMPLICIT_DEF
+  ; GFX90A-NEXT:   $sgpr40_sgpr41 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
+  ; GFX90A-NEXT:   S_CBRANCH_EXECNZ %bb.47, implicit $exec
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.42.Flow24:
   ; GFX90A-NEXT:   successors: %bb.40(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr15, $vgpr17, $vgpr18, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr15, $vgpr17, $vgpr18, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr42_sgpr43, implicit-def $scc
+  ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr40_sgpr41, implicit-def $scc
   ; GFX90A-NEXT:   renamable $vgpr59 = COPY killed renamable $vgpr18, implicit $exec
   ; GFX90A-NEXT:   renamable $sgpr42_sgpr43 = S_XOR_B64 $exec, -1, implicit-def dead $scc
   ; GFX90A-NEXT:   renamable $sgpr44_sgpr45 = S_AND_B64 killed renamable $sgpr44_sgpr45, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr46_sgpr47 = S_AND_B64 killed renamable $sgpr62_sgpr63, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr46_sgpr47 = S_AND_B64 killed renamable $sgpr46_sgpr47, $exec, implicit-def dead $scc
   ; GFX90A-NEXT:   renamable $sgpr48_sgpr49 = S_AND_B64 killed renamable $sgpr48_sgpr49, $exec, implicit-def dead $scc
   ; GFX90A-NEXT:   renamable $sgpr50_sgpr51 = S_AND_B64 killed renamable $sgpr50_sgpr51, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr52_sgpr53 = S_AND_B64 killed renamable $sgpr52_sgpr53, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = S_AND_B64 killed renamable $sgpr54_sgpr55, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr58_sgpr59 = S_AND_B64 killed renamable $sgpr58_sgpr59, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr18_sgpr19 = S_AND_B64 killed renamable $sgpr18_sgpr19, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_ANDN2_B64 renamable $sgpr36_sgpr37, $exec, implicit-def dead $scc
   ; GFX90A-NEXT:   renamable $sgpr60_sgpr61 = S_AND_B64 killed renamable $sgpr60_sgpr61, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr60_sgpr61 = S_OR_B64 killed renamable $sgpr56_sgpr57, killed renamable $sgpr60_sgpr61, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr52_sgpr53 = S_AND_B64 killed renamable $sgpr52_sgpr53, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_AND_B64 killed renamable $sgpr56_sgpr57, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr40_sgpr41 = S_AND_B64 killed renamable $sgpr16_sgpr17, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr16_sgpr17 = S_ANDN2_B64 renamable $sgpr28_sgpr29, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = S_AND_B64 killed renamable $sgpr58_sgpr59, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr58_sgpr59 = S_OR_B64 killed renamable $sgpr16_sgpr17, killed renamable $sgpr54_sgpr55, implicit-def dead $scc
   ; GFX90A-NEXT:   S_BRANCH %bb.40
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.43.bb55:
-  ; GFX90A-NEXT:   successors: %bb.48(0x40000000), %bb.44(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $sgpr33, $vgpr18, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr44_sgpr45, $sgpr52_sgpr53, $sgpr58_sgpr59, $sgpr54_sgpr55, $sgpr46_sgpr47
+  ; GFX90A-NEXT:   successors: %bb.49(0x40000000), %bb.44(0x40000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr33, $vgpr18, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr54_sgpr55:0x000000000000000F, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $vgpr2_vgpr3:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr52_sgpr53, $sgpr44_sgpr45
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   S_BITCMP1_B32 killed renamable $sgpr33, 16, implicit-def $scc
-  ; GFX90A-NEXT:   renamable $sgpr64_sgpr65 = S_CSELECT_B64 -1, 0, implicit killed $scc
-  ; GFX90A-NEXT:   renamable $sgpr48_sgpr49 = S_XOR_B64 renamable $sgpr64_sgpr65, -1, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr62_sgpr63 = S_CSELECT_B64 -1, 0, implicit killed $scc
+  ; GFX90A-NEXT:   renamable $sgpr42_sgpr43 = S_MOV_B64 -1
+  ; GFX90A-NEXT:   renamable $sgpr46_sgpr47 = S_XOR_B64 renamable $sgpr62_sgpr63, -1, implicit-def dead $scc
   ; GFX90A-NEXT:   renamable $vgpr62 = V_ADD_CO_U32_e32 6144, $vgpr40, implicit-def $vcc, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr63, dead renamable $vcc = V_ADDC_U32_e64 0, $vgpr41, killed $vcc, 0, implicit $exec
-  ; GFX90A-NEXT:   renamable $vcc = S_AND_B64 $exec, renamable $sgpr48_sgpr49, implicit-def dead $scc
-  ; GFX90A-NEXT:   $vgpr10 = IMPLICIT_DEF
-  ; GFX90A-NEXT:   $vgpr12 = IMPLICIT_DEF
-  ; GFX90A-NEXT:   S_CBRANCH_VCCNZ %bb.48, implicit $vcc
+  ; GFX90A-NEXT:   renamable $vcc = S_AND_B64 $exec, renamable $sgpr46_sgpr47, implicit-def dead $scc
+  ; GFX90A-NEXT:   S_CBRANCH_VCCNZ %bb.49, implicit $vcc
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.44:
   ; GFX90A-NEXT:   successors: %bb.45(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr58, $vgpr57, $vgpr18, $vgpr30, $vgpr31, $vgpr61, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8, $sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $vgpr40, $vgpr62, $vgpr60, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr20_sgpr21_sgpr22, $sgpr22_sgpr23, $sgpr24_sgpr25_sgpr26, $sgpr26_sgpr27, $vgpr56, $vgpr47, $vgpr2, $vgpr3, $vgpr46, $vgpr45, $vgpr44, $vgpr43, $vgpr42, $vgpr41, $vgpr10, $vgpr12
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr18, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $vgpr2_vgpr3:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr52_sgpr53
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   renamable $sgpr50_sgpr51 = COPY renamable $sgpr36_sgpr37
+  ; GFX90A-NEXT:   renamable $sgpr48_sgpr49 = COPY renamable $sgpr28_sgpr29
   ; GFX90A-NEXT:   renamable $vgpr8_vgpr9 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr6_vgpr7 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr4_vgpr5 = IMPLICIT_DEF
@@ -593,41 +591,47 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
   ; GFX90A-NEXT:   renamable $vgpr53 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr13 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr11 = IMPLICIT_DEF
-  ; GFX90A-NEXT:   renamable $sgpr17 = IMPLICIT_DEF
-  ; GFX90A-NEXT:   renamable $sgpr48_sgpr49 = S_MOV_B64 0
+  ; GFX90A-NEXT:   renamable $sgpr15 = IMPLICIT_DEF
+  ; GFX90A-NEXT:   renamable $sgpr44_sgpr45 = S_MOV_B64 0
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT: bb.45.Flow26:
-  ; GFX90A-NEXT:   successors: %bb.47(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr15, $vgpr17, $vgpr18, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
-  ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   renamable $sgpr60_sgpr61 = S_XOR_B64 $exec, -1, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr70_sgpr71 = S_AND_B64 killed renamable $sgpr44_sgpr45, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr68_sgpr69 = S_AND_B64 killed renamable $sgpr46_sgpr47, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr66_sgpr67 = S_AND_B64 killed renamable $sgpr48_sgpr49, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = S_AND_B64 killed renamable $sgpr54_sgpr55, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr58_sgpr59 = S_AND_B64 killed renamable $sgpr58_sgpr59, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr46_sgpr47 = S_AND_B64 killed renamable $sgpr52_sgpr53, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr44_sgpr45 = S_ANDN2_B64 renamable $sgpr36_sgpr37, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr48_sgpr49 = S_AND_B64 killed renamable $sgpr50_sgpr51, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr64_sgpr65 = S_OR_B64 killed renamable $sgpr44_sgpr45, killed renamable $sgpr48_sgpr49, implicit-def dead $scc
-  ; GFX90A-NEXT:   S_BRANCH %bb.47
-  ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT: bb.46.bb48:
-  ; GFX90A-NEXT:   successors: %bb.43(0x40000000), %bb.47(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $sgpr33, $vgpr18, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr46_sgpr47, $sgpr58_sgpr59, $sgpr54_sgpr55, $sgpr44_sgpr45, $sgpr52_sgpr53
+  ; GFX90A-NEXT:   successors: %bb.46(0x80000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr15, $vgpr17, $vgpr18, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6, $sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $sgpr16_sgpr17_sgpr18, $sgpr18_sgpr19, $sgpr20_sgpr21_sgpr22, $sgpr22_sgpr23, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr16, $vgpr40, $vgpr41, $vgpr42, $vgpr43, $vgpr44, $vgpr45, $vgpr46, $vgpr47, $vgpr56, $vgpr57, $vgpr58, $vgpr60, $vgpr61, $vgpr62, $vgpr63
+  ; GFX90A-NEXT: {{  $}}
+  ; GFX90A-NEXT:   renamable $sgpr46_sgpr47 = S_MOV_B64 0
+  ; GFX90A-NEXT: {{  $}}
+  ; GFX90A-NEXT: bb.46.Flow26:
+  ; GFX90A-NEXT:   successors: %bb.48(0x80000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr15, $vgpr17, $vgpr18, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT: {{  $}}
+  ; GFX90A-NEXT:   renamable $sgpr58_sgpr59 = S_XOR_B64 $exec, -1, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr66_sgpr67 = S_AND_B64 killed renamable $sgpr42_sgpr43, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr64_sgpr65 = S_AND_B64 killed renamable $sgpr44_sgpr45, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr60_sgpr61 = S_AND_B64 killed renamable $sgpr46_sgpr47, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr52_sgpr53 = S_AND_B64 killed renamable $sgpr52_sgpr53, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_AND_B64 killed renamable $sgpr56_sgpr57, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr42_sgpr43 = S_AND_B64 killed renamable $sgpr50_sgpr51, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr44_sgpr45 = S_ANDN2_B64 renamable $sgpr28_sgpr29, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr46_sgpr47 = S_AND_B64 killed renamable $sgpr48_sgpr49, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr62_sgpr63 = S_OR_B64 killed renamable $sgpr44_sgpr45, killed renamable $sgpr46_sgpr47, implicit-def dead $scc
+  ; GFX90A-NEXT:   S_BRANCH %bb.48
+  ; GFX90A-NEXT: {{  $}}
+  ; GFX90A-NEXT: bb.47.bb48:
+  ; GFX90A-NEXT:   successors: %bb.43(0x40000000), %bb.48(0x40000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr33, $vgpr18, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr54_sgpr55:0x000000000000000F, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $vgpr2_vgpr3:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr56_sgpr57, $sgpr52_sgpr53, $sgpr60_sgpr61, $sgpr50_sgpr51, $sgpr44_sgpr45
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   renamable $vgpr60 = V_ADD_CO_U32_e32 5120, $vgpr40, implicit-def $vcc, implicit $exec
-  ; GFX90A-NEXT:   renamable $sgpr18_sgpr19 = COPY $vcc
+  ; GFX90A-NEXT:   renamable $sgpr16_sgpr17 = COPY $vcc
   ; GFX90A-NEXT:   renamable $vgpr0 = V_ADD_CO_U32_e32 4096, $vgpr40, implicit-def $vcc, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr1, dead renamable $vcc = V_ADDC_U32_e64 0, $vgpr41, killed $vcc, 0, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr0 = GLOBAL_LOAD_UBYTE killed renamable $vgpr0_vgpr1, 1024, 0, implicit $exec :: (load (s8) from %ir.i49, addrspace 1)
-  ; GFX90A-NEXT:   renamable $sgpr60_sgpr61 = S_MOV_B64 -1
-  ; GFX90A-NEXT:   renamable $sgpr64_sgpr65 = COPY renamable $sgpr36_sgpr37
-  ; GFX90A-NEXT:   renamable $sgpr66_sgpr67 = S_MOV_B64 0
-  ; GFX90A-NEXT:   renamable $sgpr68_sgpr69 = S_MOV_B64 0
-  ; GFX90A-NEXT:   renamable $vgpr61, dead renamable $vcc = V_ADDC_U32_e64 0, $vgpr41, killed $sgpr18_sgpr19, 0, implicit $exec
+  ; GFX90A-NEXT:   renamable $sgpr42_sgpr43 = S_MOV_B64 0
+  ; GFX90A-NEXT:   renamable $sgpr58_sgpr59 = S_MOV_B64 -1
+  ; GFX90A-NEXT:   renamable $sgpr62_sgpr63 = COPY renamable $sgpr28_sgpr29
+  ; GFX90A-NEXT:   renamable $sgpr64_sgpr65 = S_MOV_B64 0
+  ; GFX90A-NEXT:   renamable $vgpr61, dead renamable $vcc = V_ADDC_U32_e64 0, $vgpr41, killed $sgpr16_sgpr17, 0, implicit $exec
   ; GFX90A-NEXT:   renamable $vcc = V_CMP_EQ_U16_e64 0, killed $vgpr0, implicit $exec
-  ; GFX90A-NEXT:   renamable $sgpr70_sgpr71 = S_MOV_B64 0
+  ; GFX90A-NEXT:   renamable $sgpr66_sgpr67 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $vgpr8_vgpr9 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr6_vgpr7 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr4_vgpr5 = IMPLICIT_DEF
@@ -641,57 +645,71 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
   ; GFX90A-NEXT:   renamable $vgpr53 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr13 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr11 = IMPLICIT_DEF
-  ; GFX90A-NEXT:   renamable $sgpr17 = IMPLICIT_DEF
-  ; GFX90A-NEXT:   $sgpr18_sgpr19 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
+  ; GFX90A-NEXT:   renamable $sgpr15 = IMPLICIT_DEF
+  ; GFX90A-NEXT:   $sgpr16_sgpr17 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
   ; GFX90A-NEXT:   S_CBRANCH_EXECNZ %bb.43, implicit $exec
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT: bb.47.Flow25:
+  ; GFX90A-NEXT: bb.48.Flow25:
   ; GFX90A-NEXT:   successors: %bb.42(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr15, $vgpr17, $vgpr18, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr46_sgpr47, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $sgpr70_sgpr71, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr15, $vgpr17, $vgpr18, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr52_sgpr53, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr18_sgpr19, implicit-def $scc
+  ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr16_sgpr17, implicit-def $scc
   ; GFX90A-NEXT:   renamable $sgpr44_sgpr45 = S_XOR_B64 $exec, -1, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr62_sgpr63 = S_AND_B64 killed renamable $sgpr60_sgpr61, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr48_sgpr49 = S_AND_B64 killed renamable $sgpr70_sgpr71, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr50_sgpr51 = S_AND_B64 killed renamable $sgpr68_sgpr69, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr52_sgpr53 = S_AND_B64 killed renamable $sgpr66_sgpr67, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = S_AND_B64 killed renamable $sgpr54_sgpr55, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr58_sgpr59 = S_AND_B64 killed renamable $sgpr58_sgpr59, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr18_sgpr19 = S_AND_B64 killed renamable $sgpr46_sgpr47, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr46_sgpr47 = S_ANDN2_B64 renamable $sgpr36_sgpr37, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_AND_B64 killed renamable $sgpr64_sgpr65, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr60_sgpr61 = S_OR_B64 killed renamable $sgpr46_sgpr47, killed renamable $sgpr56_sgpr57, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr46_sgpr47 = S_AND_B64 killed renamable $sgpr58_sgpr59, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr48_sgpr49 = S_AND_B64 killed renamable $sgpr66_sgpr67, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr50_sgpr51 = S_AND_B64 killed renamable $sgpr64_sgpr65, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr60_sgpr61 = S_AND_B64 killed renamable $sgpr60_sgpr61, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr52_sgpr53 = S_AND_B64 killed renamable $sgpr52_sgpr53, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_AND_B64 killed renamable $sgpr56_sgpr57, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr16_sgpr17 = S_AND_B64 killed renamable $sgpr42_sgpr43, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr42_sgpr43 = S_ANDN2_B64 renamable $sgpr28_sgpr29, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = S_AND_B64 killed renamable $sgpr62_sgpr63, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr58_sgpr59 = S_OR_B64 killed renamable $sgpr42_sgpr43, killed renamable $sgpr54_sgpr55, implicit-def dead $scc
   ; GFX90A-NEXT:   S_BRANCH %bb.42
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT: bb.48.bb63:
-  ; GFX90A-NEXT:   successors: %bb.50(0x40000000), %bb.49(0x40000000)
-  ; GFX90A-NEXT:   liveins: $vcc, $sgpr14, $sgpr15, $sgpr16, $vgpr18, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr48_sgpr49, $sgpr56_sgpr57:0x000000000000000F, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr52_sgpr53, $sgpr58_sgpr59, $sgpr54_sgpr55, $sgpr46_sgpr47
+  ; GFX90A-NEXT: bb.49.bb63:
+  ; GFX90A-NEXT:   successors: %bb.51(0x40000000), %bb.50(0x40000000)
+  ; GFX90A-NEXT:   liveins: $vcc, $sgpr12, $sgpr13, $sgpr14, $vgpr18, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr46_sgpr47, $sgpr54_sgpr55:0x000000000000000F, $sgpr62_sgpr63, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $vgpr2_vgpr3:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr44_sgpr45, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr52_sgpr53
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   renamable $sgpr44_sgpr45 = S_MOV_B64 0
-  ; GFX90A-NEXT:   S_CBRANCH_VCCNZ %bb.50, implicit $vcc
+  ; GFX90A-NEXT:   renamable $sgpr42_sgpr43 = S_MOV_B64 0
+  ; GFX90A-NEXT:   S_CBRANCH_VCCNZ %bb.51, implicit $vcc
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT: bb.49:
-  ; GFX90A-NEXT:   successors: %bb.44(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr18, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr52_sgpr53, $sgpr58_sgpr59, $sgpr54_sgpr55
+  ; GFX90A-NEXT: bb.50:
+  ; GFX90A-NEXT:   successors: %bb.45(0x80000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr18, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $vgpr2_vgpr3:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr44_sgpr45, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr52_sgpr53
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   renamable $sgpr46_sgpr47 = S_MOV_B64 -1
-  ; GFX90A-NEXT:   S_BRANCH %bb.44
+  ; GFX90A-NEXT:   renamable $sgpr48_sgpr49 = COPY renamable $sgpr28_sgpr29
+  ; GFX90A-NEXT:   renamable $vgpr8_vgpr9 = IMPLICIT_DEF
+  ; GFX90A-NEXT:   renamable $vgpr6_vgpr7 = IMPLICIT_DEF
+  ; GFX90A-NEXT:   renamable $vgpr4_vgpr5 = IMPLICIT_DEF
+  ; GFX90A-NEXT:   renamable $vgpr0_vgpr1 = IMPLICIT_DEF
+  ; GFX90A-NEXT:   renamable $vgpr17 = IMPLICIT_DEF
+  ; GFX90A-NEXT:   renamable $vgpr15 = IMPLICIT_DEF
+  ; GFX90A-NEXT:   renamable $vgpr14 = IMPLICIT_DEF
+  ; GFX90A-NEXT:   renamable $vgpr52 = IMPLICIT_DEF
+  ; GFX90A-NEXT:   renamable $vgpr16 = IMPLICIT_DEF
+  ; GFX90A-NEXT:   renamable $vgpr53 = IMPLICIT_DEF
+  ; GFX90A-NEXT:   renamable $vgpr13 = IMPLICIT_DEF
+  ; GFX90A-NEXT:   renamable $vgpr11 = IMPLICIT_DEF
+  ; GFX90A-NEXT:   renamable $sgpr15 = IMPLICIT_DEF
+  ; GFX90A-NEXT:   S_BRANCH %bb.45
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT: bb.50.bb68:
-  ; GFX90A-NEXT:   successors: %bb.54(0x40000000), %bb.51(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr18, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr48_sgpr49, $sgpr56_sgpr57:0x000000000000000F, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr46_sgpr47, $sgpr52_sgpr53, $sgpr58_sgpr59, $sgpr54_sgpr55
+  ; GFX90A-NEXT: bb.51.bb68:
+  ; GFX90A-NEXT:   successors: %bb.55(0x40000000), %bb.52(0x40000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr18, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr46_sgpr47, $sgpr54_sgpr55:0x000000000000000F, $sgpr62_sgpr63, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $vgpr2_vgpr3:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr52_sgpr53
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   renamable $vgpr0 = nuw nsw V_LSHLREV_B32_e32 3, $vgpr30, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr1 = V_MOV_B32_e32 0, implicit $exec
-  ; GFX90A-NEXT:   renamable $vcc = S_AND_B64 $exec, killed renamable $sgpr48_sgpr49, implicit-def dead $scc
-  ; GFX90A-NEXT:   S_CBRANCH_VCCNZ %bb.54, implicit $vcc
+  ; GFX90A-NEXT:   renamable $sgpr44_sgpr45 = S_MOV_B64 0
+  ; GFX90A-NEXT:   renamable $vcc = S_AND_B64 $exec, killed renamable $sgpr46_sgpr47, implicit-def dead $scc
+  ; GFX90A-NEXT:   S_CBRANCH_VCCNZ %bb.55, implicit $vcc
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT: bb.51:
-  ; GFX90A-NEXT:   successors: %bb.45(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr18, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr52_sgpr53, $sgpr58_sgpr59, $sgpr54_sgpr55
+  ; GFX90A-NEXT: bb.52:
+  ; GFX90A-NEXT:   successors: %bb.46(0x80000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr18, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr50_sgpr51, $sgpr56_sgpr57, $sgpr52_sgpr53
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   renamable $sgpr48_sgpr49 = S_MOV_B64 -1
-  ; GFX90A-NEXT:   renamable $sgpr50_sgpr51 = COPY renamable $sgpr36_sgpr37
+  ; GFX90A-NEXT:   renamable $sgpr46_sgpr47 = S_MOV_B64 -1
+  ; GFX90A-NEXT:   renamable $sgpr48_sgpr49 = COPY renamable $sgpr28_sgpr29
   ; GFX90A-NEXT:   renamable $vgpr8_vgpr9 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr6_vgpr7 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr4_vgpr5 = IMPLICIT_DEF
@@ -703,26 +721,26 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
   ; GFX90A-NEXT:   renamable $vgpr53 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr13 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr11 = IMPLICIT_DEF
-  ; GFX90A-NEXT:   renamable $sgpr17 = IMPLICIT_DEF
-  ; GFX90A-NEXT:   S_BRANCH %bb.45
+  ; GFX90A-NEXT:   renamable $sgpr15 = IMPLICIT_DEF
+  ; GFX90A-NEXT:   S_BRANCH %bb.46
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT: bb.52.bb80:
-  ; GFX90A-NEXT:   successors: %bb.59(0x40000000), %bb.53(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr18, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr56_sgpr57:0x000000000000000F, $sgpr60_sgpr61, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT: bb.53.bb80:
+  ; GFX90A-NEXT:   successors: %bb.60(0x40000000), %bb.54(0x40000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr18, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr54_sgpr55:0x000000000000000F, $sgpr58_sgpr59, $sgpr62_sgpr63, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   renamable $sgpr17 = S_BFE_U32 renamable $sgpr20, 65560, implicit-def dead $scc
-  ; GFX90A-NEXT:   S_CMP_EQ_U32 killed renamable $sgpr17, 0, implicit-def $scc
+  ; GFX90A-NEXT:   renamable $sgpr15 = S_BFE_U32 renamable $sgpr20, 65560, implicit-def dead $scc
+  ; GFX90A-NEXT:   S_CMP_EQ_U32 killed renamable $sgpr15, 0, implicit-def $scc
   ; GFX90A-NEXT:   renamable $vgpr6 = V_ADD_CO_U32_e32 4096, $vgpr0, implicit-def $vcc, implicit $exec
-  ; GFX90A-NEXT:   renamable $vgpr7, dead renamable $sgpr50_sgpr51 = V_ADDC_U32_e64 0, 0, killed $vcc, 0, implicit $exec
-  ; GFX90A-NEXT:   S_CBRANCH_SCC1 %bb.59, implicit killed $scc
+  ; GFX90A-NEXT:   renamable $vgpr7, dead renamable $sgpr48_sgpr49 = V_ADDC_U32_e64 0, 0, killed $vcc, 0, implicit $exec
+  ; GFX90A-NEXT:   S_CBRANCH_SCC1 %bb.60, implicit killed $scc
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT: bb.53:
-  ; GFX90A-NEXT:   successors: %bb.61(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr18, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr60_sgpr61, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT: bb.54:
+  ; GFX90A-NEXT:   successors: %bb.62(0x80000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr18, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr58_sgpr59, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   renamable $sgpr50_sgpr51 = S_MOV_B64 0
-  ; GFX90A-NEXT:   renamable $sgpr52_sgpr53 = S_MOV_B64 -1
-  ; GFX90A-NEXT:   renamable $sgpr62_sgpr63 = COPY renamable $sgpr36_sgpr37
+  ; GFX90A-NEXT:   renamable $sgpr48_sgpr49 = S_MOV_B64 0
+  ; GFX90A-NEXT:   renamable $sgpr50_sgpr51 = S_MOV_B64 -1
+  ; GFX90A-NEXT:   renamable $sgpr60_sgpr61 = COPY renamable $sgpr28_sgpr29
   ; GFX90A-NEXT:   renamable $vgpr8_vgpr9 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr17 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr15 = IMPLICIT_DEF
@@ -732,21 +750,21 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
   ; GFX90A-NEXT:   renamable $vgpr53 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr13 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr11 = IMPLICIT_DEF
-  ; GFX90A-NEXT:   renamable $sgpr17 = IMPLICIT_DEF
-  ; GFX90A-NEXT:   S_BRANCH %bb.61
+  ; GFX90A-NEXT:   renamable $sgpr15 = IMPLICIT_DEF
+  ; GFX90A-NEXT:   S_BRANCH %bb.62
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT: bb.54.bb73:
-  ; GFX90A-NEXT:   successors: %bb.52(0x40000000), %bb.55(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr18, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr56_sgpr57:0x000000000000000F, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr52_sgpr53
+  ; GFX90A-NEXT: bb.55.bb73:
+  ; GFX90A-NEXT:   successors: %bb.53(0x40000000), %bb.56(0x40000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr18, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr54_sgpr55:0x000000000000000F, $sgpr62_sgpr63, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr50_sgpr51
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   renamable $vgpr6 = GLOBAL_LOAD_UBYTE renamable $vgpr0_vgpr1, 2048, 0, implicit $exec :: (load (s8) from %ir.i74, addrspace 1)
   ; GFX90A-NEXT:   renamable $vgpr4 = V_ADD_CO_U32_e32 2048, $vgpr0, implicit-def $vcc, implicit $exec
-  ; GFX90A-NEXT:   renamable $sgpr48_sgpr49 = S_MOV_B64 0
-  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = S_MOV_B64 -1
-  ; GFX90A-NEXT:   renamable $sgpr50_sgpr51 = COPY renamable $sgpr36_sgpr37
-  ; GFX90A-NEXT:   renamable $vgpr5, dead renamable $sgpr58_sgpr59 = V_ADDC_U32_e64 0, 0, killed $vcc, 0, implicit $exec
+  ; GFX90A-NEXT:   renamable $sgpr46_sgpr47 = S_MOV_B64 0
+  ; GFX90A-NEXT:   renamable $sgpr52_sgpr53 = S_MOV_B64 -1
+  ; GFX90A-NEXT:   renamable $sgpr48_sgpr49 = COPY renamable $sgpr28_sgpr29
+  ; GFX90A-NEXT:   renamable $vgpr5, dead renamable $sgpr56_sgpr57 = V_ADDC_U32_e64 0, 0, killed $vcc, 0, implicit $exec
   ; GFX90A-NEXT:   renamable $vcc = V_CMP_EQ_U16_e64 0, killed $vgpr6, implicit $exec
-  ; GFX90A-NEXT:   renamable $sgpr58_sgpr59 = S_MOV_B64 0
+  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $vgpr8_vgpr9 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr6_vgpr7 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr17 = IMPLICIT_DEF
@@ -757,53 +775,53 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
   ; GFX90A-NEXT:   renamable $vgpr53 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr13 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr11 = IMPLICIT_DEF
-  ; GFX90A-NEXT:   renamable $sgpr17 = IMPLICIT_DEF
-  ; GFX90A-NEXT:   $sgpr60_sgpr61 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
-  ; GFX90A-NEXT:   S_CBRANCH_EXECNZ %bb.52, implicit $exec
+  ; GFX90A-NEXT:   renamable $sgpr15 = IMPLICIT_DEF
+  ; GFX90A-NEXT:   $sgpr58_sgpr59 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
+  ; GFX90A-NEXT:   S_CBRANCH_EXECNZ %bb.53, implicit $exec
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT: bb.55.Flow29:
-  ; GFX90A-NEXT:   successors: %bb.45(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr15, $vgpr17, $vgpr18, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT: bb.56.Flow29:
+  ; GFX90A-NEXT:   successors: %bb.46(0x80000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr15, $vgpr17, $vgpr18, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $sgpr58_sgpr59, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr60_sgpr61, implicit-def $scc
-  ; GFX90A-NEXT:   S_BRANCH %bb.45
+  ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr58_sgpr59, implicit-def $scc
+  ; GFX90A-NEXT:   S_BRANCH %bb.46
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT: bb.56.bb90:
-  ; GFX90A-NEXT:   successors: %bb.60(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr18, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr52_sgpr53, $sgpr56_sgpr57:0x000000000000000F, $sgpr60_sgpr61, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT: bb.57.bb90:
+  ; GFX90A-NEXT:   successors: %bb.61(0x80000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr18, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr50_sgpr51, $sgpr54_sgpr55:0x000000000000000F, $sgpr58_sgpr59, $sgpr62_sgpr63, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   renamable $vgpr53 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $sgpr64_sgpr65, implicit $exec
+  ; GFX90A-NEXT:   renamable $vgpr53 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $sgpr62_sgpr63, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr10 = V_MOV_B32_e32 0, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr14_vgpr15 = DS_READ_B64_gfx9 killed renamable $vgpr10, 0, 0, implicit $exec :: (load (s64) from `ptr addrspace(3) null`, addrspace 3)
   ; GFX90A-NEXT:   renamable $vgpr10 = COPY renamable $sgpr21, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr16_vgpr17 = DS_READ_B64_gfx9 killed renamable $vgpr10, 0, 0, implicit $exec :: (load (s64) from %ir.7, addrspace 3)
   ; GFX90A-NEXT:   renamable $vgpr10 = COPY renamable $sgpr22, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr12_vgpr13 = DS_READ_B64_gfx9 killed renamable $vgpr10, 0, 0, implicit $exec :: (load (s64) from %ir.8, addrspace 3)
-  ; GFX90A-NEXT:   renamable $vgpr10 = COPY renamable $sgpr56, implicit $exec
-  ; GFX90A-NEXT:   renamable $vgpr11 = V_ALIGNBIT_B32_e64 killed $sgpr57, killed $vgpr10, 1, implicit $exec
+  ; GFX90A-NEXT:   renamable $vgpr10 = COPY renamable $sgpr54, implicit $exec
+  ; GFX90A-NEXT:   renamable $vgpr11 = V_ALIGNBIT_B32_e64 killed $sgpr55, killed $vgpr10, 1, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr52 = V_ALIGNBIT_B32_e64 $vgpr17, $vgpr16, 1, implicit $exec
-  ; GFX90A-NEXT:   renamable $vgpr17 = V_CNDMASK_B32_e64 0, 0, 0, 1, $sgpr12_sgpr13, implicit $exec
+  ; GFX90A-NEXT:   renamable $vgpr17 = V_CNDMASK_B32_e64 0, 0, 0, 1, $sgpr8_sgpr9, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr15 = V_ALIGNBIT_B32_e64 $vgpr15, $vgpr14, 1, implicit $exec
-  ; GFX90A-NEXT:   renamable $sgpr50_sgpr51 = S_XOR_B64 $exec, -1, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr62_sgpr63 = S_OR_B64 renamable $sgpr36_sgpr37, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   S_BRANCH %bb.60
+  ; GFX90A-NEXT:   renamable $sgpr48_sgpr49 = S_XOR_B64 $exec, -1, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr60_sgpr61 = S_OR_B64 renamable $sgpr28_sgpr29, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   S_BRANCH %bb.61
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT: bb.57:
+  ; GFX90A-NEXT: bb.58:
   ; GFX90A-NEXT:   successors: %bb.7(0x80000000)
-  ; GFX90A-NEXT:   liveins: $exec:0x000000000000000F, $sgpr14, $sgpr15, $sgpr16, $sgpr17:0x0000000000000003, $sgpr23:0x0000000000000003, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x000000000000000F, $vgpr24_vgpr25:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $exec:0x000000000000000F, $sgpr12, $sgpr13, $sgpr14, $sgpr15:0x0000000000000003, $sgpr23:0x0000000000000003, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr42_sgpr43, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $vgpr2_vgpr3:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x000000000000000F, $vgpr24_vgpr25:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   renamable $vgpr15 = COPY killed renamable $sgpr23, implicit $exec
-  ; GFX90A-NEXT:   renamable $vgpr17 = COPY killed renamable $sgpr17, implicit $exec
-  ; GFX90A-NEXT:   renamable $sgpr58_sgpr59 = S_MOV_B64 0
-  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = S_MOV_B64 0
+  ; GFX90A-NEXT:   renamable $vgpr17 = COPY killed renamable $sgpr15, implicit $exec
+  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $sgpr52_sgpr53 = S_MOV_B64 0
+  ; GFX90A-NEXT:   renamable $sgpr16_sgpr17 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $sgpr50_sgpr51 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $sgpr48_sgpr49 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $sgpr46_sgpr47 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $sgpr44_sgpr45 = S_MOV_B64 0
-  ; GFX90A-NEXT:   renamable $sgpr42_sgpr43 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $sgpr40_sgpr41 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $sgpr38_sgpr39 = S_MOV_B64 0
+  ; GFX90A-NEXT:   renamable $sgpr36_sgpr37 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $vgpr8_vgpr9 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr6_vgpr7 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr4_vgpr5 = IMPLICIT_DEF
@@ -825,9 +843,9 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
   ; GFX90A-NEXT:   renamable $sgpr34_sgpr35 = S_MOV_B64 0
   ; GFX90A-NEXT:   S_BRANCH %bb.7
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT: bb.58.bb105:
+  ; GFX90A-NEXT: bb.59.bb105:
   ; GFX90A-NEXT:   successors: %bb.3(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr33, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x00000000000000FF, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000FF, $vgpr2_vgpr3:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr33, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr30_sgpr31, $sgpr42_sgpr43, $sgpr54_sgpr55:0x000000000000000F, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000FF, $sgpr20_sgpr21_sgpr22_sgpr23:0x00000000000000FF, $vgpr2_vgpr3:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   renamable $vgpr0 = V_MOV_B32_e32 0, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr22_vgpr23 = DS_READ_B64_gfx9 killed renamable $vgpr0, 0, 0, implicit $exec :: (load (s64) from `ptr addrspace(3) null`, addrspace 3)
@@ -835,26 +853,26 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
   ; GFX90A-NEXT:   renamable $vgpr20_vgpr21 = DS_READ_B64_gfx9 killed renamable $vgpr0, 0, 0, implicit $exec :: (load (s64) from %ir.434, addrspace 3)
   ; GFX90A-NEXT:   renamable $vgpr0 = COPY renamable $sgpr21, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr18_vgpr19 = DS_READ_B64_gfx9 killed renamable $vgpr0, 0, 0, implicit $exec :: (load (s64) from %ir.7, addrspace 3)
-  ; GFX90A-NEXT:   renamable $vgpr0 = COPY killed renamable $sgpr17, implicit $exec
+  ; GFX90A-NEXT:   renamable $vgpr0 = COPY killed renamable $sgpr15, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr10_vgpr11 = DS_READ_B64_gfx9 killed renamable $vgpr0, 0, 0, implicit $exec :: (load (s64) from %ir.435, addrspace 3)
   ; GFX90A-NEXT:   renamable $vgpr0 = COPY renamable $sgpr22, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr24_vgpr25 = DS_READ_B64_gfx9 killed renamable $vgpr0, 0, 0, implicit $exec :: (load (s64) from %ir.8, addrspace 3)
-  ; GFX90A-NEXT:   renamable $sgpr36_sgpr37 = S_MOV_B64 -1
+  ; GFX90A-NEXT:   renamable $sgpr28_sgpr29 = S_MOV_B64 -1
   ; GFX90A-NEXT:   renamable $sgpr23 = S_MOV_B32 0
-  ; GFX90A-NEXT:   renamable $sgpr17 = S_MOV_B32 0
+  ; GFX90A-NEXT:   renamable $sgpr15 = S_MOV_B32 0
   ; GFX90A-NEXT:   S_BRANCH %bb.3
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT: bb.59.bb85:
-  ; GFX90A-NEXT:   successors: %bb.56(0x40000000), %bb.60(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr18, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr56_sgpr57:0x000000000000000F, $sgpr60_sgpr61, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT: bb.60.bb85:
+  ; GFX90A-NEXT:   successors: %bb.57(0x40000000), %bb.61(0x40000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr18, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr54_sgpr55:0x000000000000000F, $sgpr58_sgpr59, $sgpr62_sgpr63, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   renamable $vgpr8 = V_OR_B32_e32 1, $vgpr6, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr9 = COPY renamable $vgpr7, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr10 = FLAT_LOAD_UBYTE renamable $vgpr8_vgpr9, 0, 0, implicit $exec, implicit $flat_scr :: (load (s8) from %ir.i86)
-  ; GFX90A-NEXT:   renamable $sgpr17 = S_MOV_B32 0
-  ; GFX90A-NEXT:   renamable $sgpr50_sgpr51 = S_MOV_B64 -1
+  ; GFX90A-NEXT:   renamable $sgpr15 = S_MOV_B32 0
+  ; GFX90A-NEXT:   renamable $sgpr48_sgpr49 = S_MOV_B64 -1
   ; GFX90A-NEXT:   renamable $vcc = V_CMP_EQ_U16_e64 0, killed $vgpr10, implicit $exec
-  ; GFX90A-NEXT:   renamable $sgpr62_sgpr63 = COPY renamable $sgpr36_sgpr37
+  ; GFX90A-NEXT:   renamable $sgpr60_sgpr61 = COPY renamable $sgpr28_sgpr29
   ; GFX90A-NEXT:   renamable $vgpr17 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr15 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr14 = IMPLICIT_DEF
@@ -863,70 +881,70 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
   ; GFX90A-NEXT:   renamable $vgpr53 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr13 = IMPLICIT_DEF
   ; GFX90A-NEXT:   renamable $vgpr11 = IMPLICIT_DEF
-  ; GFX90A-NEXT:   $sgpr52_sgpr53 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
-  ; GFX90A-NEXT:   S_CBRANCH_EXECNZ %bb.56, implicit $exec
+  ; GFX90A-NEXT:   $sgpr50_sgpr51 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
+  ; GFX90A-NEXT:   S_CBRANCH_EXECNZ %bb.57, implicit $exec
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT: bb.60.Flow31:
-  ; GFX90A-NEXT:   successors: %bb.61(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr15, $vgpr17, $vgpr18, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000C, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT: bb.61.Flow31:
+  ; GFX90A-NEXT:   successors: %bb.62(0x80000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr15, $vgpr17, $vgpr18, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000C, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr52_sgpr53, implicit-def $scc
-  ; GFX90A-NEXT:   renamable $sgpr52_sgpr53 = S_MOV_B64 0
+  ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr50_sgpr51, implicit-def $scc
+  ; GFX90A-NEXT:   renamable $sgpr50_sgpr51 = S_MOV_B64 0
   ; GFX90A-NEXT:   renamable $vgpr10 = COPY renamable $vgpr14, implicit $exec
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT: bb.61.Flow30:
-  ; GFX90A-NEXT:   successors: %bb.55(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr15, $vgpr17, $vgpr18, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT: bb.62.Flow30:
+  ; GFX90A-NEXT:   successors: %bb.56(0x80000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr15, $vgpr17, $vgpr18, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = S_XOR_B64 $exec, -1, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr58_sgpr59 = S_AND_B64 killed renamable $sgpr52_sgpr53, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr52_sgpr53 = S_AND_B64 killed renamable $sgpr50_sgpr51, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr50_sgpr51 = S_ANDN2_B64 renamable $sgpr36_sgpr37, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_AND_B64 killed renamable $sgpr62_sgpr63, $exec, implicit-def dead $scc
-  ; GFX90A-NEXT:   renamable $sgpr50_sgpr51 = S_OR_B64 killed renamable $sgpr50_sgpr51, killed renamable $sgpr56_sgpr57, implicit-def dead $scc
-  ; GFX90A-NEXT:   S_BRANCH %bb.55
+  ; GFX90A-NEXT:   renamable $sgpr52_sgpr53 = S_XOR_B64 $exec, -1, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = S_AND_B64 killed renamable $sgpr50_sgpr51, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr50_sgpr51 = S_AND_B64 killed renamable $sgpr48_sgpr49, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr48_sgpr49 = S_ANDN2_B64 renamable $sgpr28_sgpr29, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = S_AND_B64 killed renamable $sgpr60_sgpr61, $exec, implicit-def dead $scc
+  ; GFX90A-NEXT:   renamable $sgpr48_sgpr49 = S_OR_B64 killed renamable $sgpr48_sgpr49, killed renamable $sgpr54_sgpr55, implicit-def dead $scc
+  ; GFX90A-NEXT:   S_BRANCH %bb.56
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT: bb.62.bb140:
-  ; GFX90A-NEXT:   successors: %bb.68(0x40000000), %bb.63(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr15, $vgpr17, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x000000000000000F, $vgpr24_vgpr25:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT: bb.63.bb140:
+  ; GFX90A-NEXT:   successors: %bb.69(0x40000000), %bb.64(0x40000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr15, $vgpr17, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr24_sgpr25, $sgpr26_sgpr27, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x000000000000000F, $vgpr24_vgpr25:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   renamable $sgpr36_sgpr37 = S_MOV_B64 -1
-  ; GFX90A-NEXT:   renamable $vcc = S_AND_B64 $exec, killed renamable $sgpr30_sgpr31, implicit-def dead $scc
-  ; GFX90A-NEXT:   S_CBRANCH_VCCNZ %bb.68, implicit $vcc
+  ; GFX90A-NEXT:   renamable $sgpr28_sgpr29 = S_MOV_B64 -1
+  ; GFX90A-NEXT:   renamable $vcc = S_AND_B64 $exec, killed renamable $sgpr26_sgpr27, implicit-def dead $scc
+  ; GFX90A-NEXT:   S_CBRANCH_VCCNZ %bb.69, implicit $vcc
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT: bb.63.Flow13:
-  ; GFX90A-NEXT:   successors: %bb.64(0x40000000), %bb.66(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr15, $vgpr17, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $vgpr0_vgpr1:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000C, $vgpr12_vgpr13:0x000000000000000C, $vgpr18_vgpr19:0x000000000000000C, $vgpr20_vgpr21:0x000000000000000C, $vgpr22_vgpr23:0x000000000000000C, $vgpr24_vgpr25:0x000000000000000C, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT: bb.64.Flow13:
+  ; GFX90A-NEXT:   successors: %bb.65(0x40000000), %bb.67(0x40000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr15, $vgpr17, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $vgpr0_vgpr1:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000C, $vgpr12_vgpr13:0x000000000000000C, $vgpr18_vgpr19:0x000000000000000C, $vgpr20_vgpr21:0x000000000000000C, $vgpr22_vgpr23:0x000000000000000C, $vgpr24_vgpr25:0x000000000000000C, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   $vcc = S_ANDN2_B64 $exec, killed renamable $sgpr36_sgpr37, implicit-def dead $scc
-  ; GFX90A-NEXT:   S_CBRANCH_VCCNZ %bb.66, implicit $vcc
+  ; GFX90A-NEXT:   $vcc = S_ANDN2_B64 $exec, killed renamable $sgpr28_sgpr29, implicit-def dead $scc
+  ; GFX90A-NEXT:   S_CBRANCH_VCCNZ %bb.67, implicit $vcc
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT: bb.64.bb159:
-  ; GFX90A-NEXT:   successors: %bb.67(0x40000000), %bb.65(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr15, $vgpr17, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $vgpr0_vgpr1:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000C, $vgpr12_vgpr13:0x000000000000000C, $vgpr18_vgpr19:0x000000000000000C, $vgpr20_vgpr21:0x000000000000000C, $vgpr22_vgpr23:0x000000000000000C, $vgpr24_vgpr25:0x000000000000000C, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT: bb.65.bb159:
+  ; GFX90A-NEXT:   successors: %bb.68(0x40000000), %bb.66(0x40000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr15, $vgpr17, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $vgpr0_vgpr1:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000C, $vgpr12_vgpr13:0x000000000000000C, $vgpr18_vgpr19:0x000000000000000C, $vgpr20_vgpr21:0x000000000000000C, $vgpr22_vgpr23:0x000000000000000C, $vgpr24_vgpr25:0x000000000000000C, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   renamable $vcc = V_CMP_NE_U32_e64 0, killed $vgpr30, implicit $exec
-  ; GFX90A-NEXT:   $sgpr12_sgpr13 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
-  ; GFX90A-NEXT:   renamable $sgpr12_sgpr13 = S_XOR_B64 $exec, killed renamable $sgpr12_sgpr13, implicit-def dead $scc
-  ; GFX90A-NEXT:   S_CBRANCH_EXECNZ %bb.67, implicit $exec
+  ; GFX90A-NEXT:   $sgpr8_sgpr9 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
+  ; GFX90A-NEXT:   renamable $sgpr8_sgpr9 = S_XOR_B64 $exec, killed renamable $sgpr8_sgpr9, implicit-def dead $scc
+  ; GFX90A-NEXT:   S_CBRANCH_EXECNZ %bb.68, implicit $exec
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT: bb.65.Flow10:
-  ; GFX90A-NEXT:   successors: %bb.66(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $vgpr0_vgpr1:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT: bb.66.Flow10:
+  ; GFX90A-NEXT:   successors: %bb.67(0x80000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $vgpr0_vgpr1:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   $sgpr12_sgpr13 = S_ANDN2_SAVEEXEC_B64 $sgpr12_sgpr13, implicit-def $exec, implicit-def $scc, implicit $exec
-  ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr12_sgpr13, implicit-def $scc
+  ; GFX90A-NEXT:   $sgpr8_sgpr9 = S_ANDN2_SAVEEXEC_B64 $sgpr8_sgpr9, implicit-def $exec, implicit-def $scc, implicit $exec
+  ; GFX90A-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr8_sgpr9, implicit-def $scc
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT: bb.66.Flow14:
+  ; GFX90A-NEXT: bb.67.Flow14:
   ; GFX90A-NEXT:   successors: %bb.8(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $vgpr0_vgpr1:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $vgpr0_vgpr1:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   renamable $sgpr56_sgpr57 = COPY $exec
+  ; GFX90A-NEXT:   renamable $sgpr54_sgpr55 = COPY $exec
   ; GFX90A-NEXT:   S_BRANCH %bb.8
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT: bb.67.bb161:
-  ; GFX90A-NEXT:   successors: %bb.65(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr15, $vgpr17, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $vgpr0_vgpr1:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000C, $vgpr12_vgpr13:0x000000000000000C, $vgpr18_vgpr19:0x000000000000000C, $vgpr20_vgpr21:0x000000000000000C, $vgpr22_vgpr23:0x000000000000000C, $vgpr24_vgpr25:0x000000000000000C, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT: bb.68.bb161:
+  ; GFX90A-NEXT:   successors: %bb.66(0x80000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr15, $vgpr17, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $vgpr0_vgpr1:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000C, $vgpr12_vgpr13:0x000000000000000C, $vgpr18_vgpr19:0x000000000000000C, $vgpr20_vgpr21:0x000000000000000C, $vgpr22_vgpr23:0x000000000000000C, $vgpr24_vgpr25:0x000000000000000C, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   renamable $vgpr2 = V_OR_B32_e32 killed $vgpr21, killed $vgpr23, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr2 = V_OR_B32_e32 killed $vgpr2, killed $vgpr25, implicit $exec
@@ -941,38 +959,38 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
   ; GFX90A-NEXT:   renamable $vgpr2 = V_CNDMASK_B32_e64 0, 0, 0, killed $vgpr2, killed $vcc, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr2 = V_OR_B32_e32 killed $vgpr2, killed $vgpr15, implicit $exec
   ; GFX90A-NEXT:   DS_WRITE2_B32_gfx9 killed renamable $vgpr3, killed renamable $vgpr2, renamable $vgpr3, 0, 1, 0, implicit $exec :: (store (s64) into `ptr addrspace(3) null`, align 4, addrspace 3)
-  ; GFX90A-NEXT:   S_BRANCH %bb.65
+  ; GFX90A-NEXT:   S_BRANCH %bb.66
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT: bb.68.bb174:
-  ; GFX90A-NEXT:   successors: %bb.72(0x40000000), %bb.69(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr15, $vgpr17, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x000000000000000F, $vgpr24_vgpr25:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT: bb.69.bb174:
+  ; GFX90A-NEXT:   successors: %bb.73(0x40000000), %bb.70(0x40000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr15, $vgpr17, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr24_sgpr25, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x000000000000000F, $vgpr24_vgpr25:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   renamable $vgpr26 = V_OR_B32_e32 1, $vgpr24, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr48 = V_OR_B32_e32 $vgpr26, $vgpr22, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr34 = V_OR_B32_e32 $vgpr48, $vgpr20, implicit $exec
-  ; GFX90A-NEXT:   renamable $vgpr28 = V_CNDMASK_B32_e64 0, $vgpr34, 0, 0, $sgpr12_sgpr13, implicit $exec
+  ; GFX90A-NEXT:   renamable $vgpr28 = V_CNDMASK_B32_e64 0, $vgpr34, 0, 0, $sgpr8_sgpr9, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr38 = V_OR_B32_e32 $vgpr28, $vgpr18, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr36 = V_OR_B32_e32 $vgpr38, $vgpr10, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr32 = V_OR_B32_e32 $vgpr36, $vgpr12, implicit $exec
-  ; GFX90A-NEXT:   renamable $vgpr50 = V_CNDMASK_B32_e64 0, 0, 0, $vgpr32, killed $sgpr12_sgpr13, implicit $exec
-  ; GFX90A-NEXT:   renamable $sgpr12_sgpr13 = S_MOV_B64 -1
-  ; GFX90A-NEXT:   renamable $vcc = S_AND_B64 $exec, killed renamable $sgpr28_sgpr29, implicit-def dead $scc
-  ; GFX90A-NEXT:   S_CBRANCH_VCCNZ %bb.72, implicit $vcc
+  ; GFX90A-NEXT:   renamable $vgpr50 = V_CNDMASK_B32_e64 0, 0, 0, $vgpr32, killed $sgpr8_sgpr9, implicit $exec
+  ; GFX90A-NEXT:   renamable $sgpr8_sgpr9 = S_MOV_B64 -1
+  ; GFX90A-NEXT:   renamable $vcc = S_AND_B64 $exec, killed renamable $sgpr24_sgpr25, implicit-def dead $scc
+  ; GFX90A-NEXT:   S_CBRANCH_VCCNZ %bb.73, implicit $vcc
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT: bb.69.Flow:
-  ; GFX90A-NEXT:   successors: %bb.70(0x40000000), %bb.71(0x40000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr15, $vgpr17, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000C, $vgpr12_vgpr13:0x000000000000000C, $vgpr18_vgpr19:0x000000000000000C, $vgpr20_vgpr21:0x000000000000000C, $vgpr22_vgpr23:0x000000000000000C, $vgpr24_vgpr25:0x000000000000000C, $vgpr26_vgpr27:0x0000000000000003, $vgpr28_vgpr29:0x0000000000000003, $vgpr32_vgpr33:0x0000000000000003, $vgpr34_vgpr35:0x0000000000000003, $vgpr36_vgpr37:0x0000000000000003, $vgpr38_vgpr39:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr48_vgpr49:0x0000000000000003, $vgpr50_vgpr51:0x0000000000000003, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT: bb.70.Flow:
+  ; GFX90A-NEXT:   successors: %bb.71(0x40000000), %bb.72(0x40000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr15, $vgpr17, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000C, $vgpr12_vgpr13:0x000000000000000C, $vgpr18_vgpr19:0x000000000000000C, $vgpr20_vgpr21:0x000000000000000C, $vgpr22_vgpr23:0x000000000000000C, $vgpr24_vgpr25:0x000000000000000C, $vgpr26_vgpr27:0x0000000000000003, $vgpr28_vgpr29:0x0000000000000003, $vgpr32_vgpr33:0x0000000000000003, $vgpr34_vgpr35:0x0000000000000003, $vgpr36_vgpr37:0x0000000000000003, $vgpr38_vgpr39:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr48_vgpr49:0x0000000000000003, $vgpr50_vgpr51:0x0000000000000003, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   $vcc = S_ANDN2_B64 $exec, killed renamable $sgpr12_sgpr13, implicit-def dead $scc
-  ; GFX90A-NEXT:   S_CBRANCH_VCCNZ %bb.71, implicit $vcc
+  ; GFX90A-NEXT:   $vcc = S_ANDN2_B64 $exec, killed renamable $sgpr8_sgpr9, implicit-def dead $scc
+  ; GFX90A-NEXT:   S_CBRANCH_VCCNZ %bb.72, implicit $vcc
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT: bb.70.bb186:
-  ; GFX90A-NEXT:   successors: %bb.71(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr15, $vgpr17, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000C, $vgpr12_vgpr13:0x000000000000000C, $vgpr18_vgpr19:0x000000000000000C, $vgpr20_vgpr21:0x000000000000000C, $vgpr22_vgpr23:0x000000000000000C, $vgpr24_vgpr25:0x000000000000000C, $vgpr26_vgpr27:0x0000000000000003, $vgpr28_vgpr29:0x0000000000000003, $vgpr32_vgpr33:0x0000000000000003, $vgpr34_vgpr35:0x0000000000000003, $vgpr36_vgpr37:0x0000000000000003, $vgpr38_vgpr39:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr48_vgpr49:0x0000000000000003, $vgpr50_vgpr51:0x0000000000000003, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT: bb.71.bb186:
+  ; GFX90A-NEXT:   successors: %bb.72(0x80000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr15, $vgpr17, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000C, $vgpr12_vgpr13:0x000000000000000C, $vgpr18_vgpr19:0x000000000000000C, $vgpr20_vgpr21:0x000000000000000C, $vgpr22_vgpr23:0x000000000000000C, $vgpr24_vgpr25:0x000000000000000C, $vgpr26_vgpr27:0x0000000000000003, $vgpr28_vgpr29:0x0000000000000003, $vgpr32_vgpr33:0x0000000000000003, $vgpr34_vgpr35:0x0000000000000003, $vgpr36_vgpr37:0x0000000000000003, $vgpr38_vgpr39:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr48_vgpr49:0x0000000000000003, $vgpr50_vgpr51:0x0000000000000003, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   renamable $vgpr2_vgpr3 = V_LSHLREV_B64_e64 3, killed $vgpr2_vgpr3, implicit $exec
-  ; GFX90A-NEXT:   renamable $vgpr10 = COPY renamable $sgpr27, implicit $exec
-  ; GFX90A-NEXT:   renamable $vgpr2, renamable $vcc = V_ADD_CO_U32_e64 killed $sgpr26, $vgpr2, 0, implicit $exec
+  ; GFX90A-NEXT:   renamable $vgpr10 = COPY renamable $sgpr19, implicit $exec
+  ; GFX90A-NEXT:   renamable $vgpr2, renamable $vcc = V_ADD_CO_U32_e64 killed $sgpr18, $vgpr2, 0, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr3, dead renamable $vcc = V_ADDC_U32_e64 killed $vgpr10, killed $vgpr3, killed $vcc, 0, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr27 = V_MOV_B32_e32 0, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr49 = COPY renamable $vgpr27, implicit $exec
@@ -995,23 +1013,23 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
   ; GFX90A-NEXT:   BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null` + 4, basealign 8, addrspace 5)
   ; GFX90A-NEXT:   BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null`, align 8, addrspace 5)
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT: bb.71.Flow9:
-  ; GFX90A-NEXT:   successors: %bb.63(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr15, $vgpr17, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $vgpr0_vgpr1:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000C, $vgpr12_vgpr13:0x000000000000000C, $vgpr18_vgpr19:0x000000000000000C, $vgpr20_vgpr21:0x000000000000000C, $vgpr22_vgpr23:0x000000000000000C, $vgpr24_vgpr25:0x000000000000000C, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT: bb.72.Flow9:
+  ; GFX90A-NEXT:   successors: %bb.64(0x80000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr15, $vgpr17, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $vgpr0_vgpr1:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000C, $vgpr12_vgpr13:0x000000000000000C, $vgpr18_vgpr19:0x000000000000000C, $vgpr20_vgpr21:0x000000000000000C, $vgpr22_vgpr23:0x000000000000000C, $vgpr24_vgpr25:0x000000000000000C, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT:   renamable $sgpr36_sgpr37 = S_MOV_B64 0
-  ; GFX90A-NEXT:   S_BRANCH %bb.63
+  ; GFX90A-NEXT:   renamable $sgpr28_sgpr29 = S_MOV_B64 0
+  ; GFX90A-NEXT:   S_BRANCH %bb.64
   ; GFX90A-NEXT: {{  $}}
-  ; GFX90A-NEXT: bb.72.bb196:
-  ; GFX90A-NEXT:   successors: %bb.69(0x80000000)
-  ; GFX90A-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr15, $vgpr17, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000C, $vgpr12_vgpr13:0x000000000000000C, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000C, $vgpr20_vgpr21:0x000000000000000C, $vgpr22_vgpr23:0x000000000000000C, $vgpr24_vgpr25:0x000000000000000C, $vgpr26_vgpr27:0x0000000000000003, $vgpr28_vgpr29:0x0000000000000003, $vgpr32_vgpr33:0x0000000000000003, $vgpr34_vgpr35:0x0000000000000003, $vgpr36_vgpr37:0x0000000000000003, $vgpr38_vgpr39:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr48_vgpr49:0x0000000000000003, $vgpr50_vgpr51:0x0000000000000003, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+  ; GFX90A-NEXT: bb.73.bb196:
+  ; GFX90A-NEXT:   successors: %bb.70(0x80000000)
+  ; GFX90A-NEXT:   liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr15, $vgpr17, $vgpr30, $vgpr31, $vgpr52, $vgpr53, $sgpr4_sgpr5, $sgpr6_sgpr7:0x000000000000000F, $sgpr10_sgpr11, $sgpr16_sgpr17, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr56_sgpr57, $sgpr16_sgpr17_sgpr18_sgpr19:0x00000000000000F0, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000C, $vgpr12_vgpr13:0x000000000000000C, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000C, $vgpr20_vgpr21:0x000000000000000C, $vgpr22_vgpr23:0x000000000000000C, $vgpr24_vgpr25:0x000000000000000C, $vgpr26_vgpr27:0x0000000000000003, $vgpr28_vgpr29:0x0000000000000003, $vgpr32_vgpr33:0x0000000000000003, $vgpr34_vgpr35:0x0000000000000003, $vgpr36_vgpr37:0x0000000000000003, $vgpr38_vgpr39:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr48_vgpr49:0x0000000000000003, $vgpr50_vgpr51:0x0000000000000003, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
   ; GFX90A-NEXT: {{  $}}
   ; GFX90A-NEXT:   renamable $vgpr10 = V_OR_B32_e32 $vgpr50, killed $vgpr16, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr54 = V_OR_B32_e32 killed $vgpr10, killed $vgpr14, implicit $exec
   ; GFX90A-NEXT:   renamable $vgpr55 = V_MOV_B32_e32 0, implicit $exec
   ; GFX90A-NEXT:   DS_WRITE_B64_gfx9 killed renamable $vgpr55, renamable $vgpr54_vgpr55, 0, 0, implicit $exec :: (store (s64) into `ptr addrspace(3) null`, addrspace 3)
-  ; GFX90A-NEXT:   renamable $sgpr12_sgpr13 = S_MOV_B64 0
-  ; GFX90A-NEXT:   S_BRANCH %bb.69
+  ; GFX90A-NEXT:   renamable $sgpr8_sgpr9 = S_MOV_B64 0
+  ; GFX90A-NEXT:   S_BRANCH %bb.70
 bb:
   %i = tail call i32 @llvm.amdgcn.workitem.id.x()
   %i11 = icmp eq i32 %i, 0
@@ -1312,3 +1330,6 @@ bb196:
 declare void @f2(i64)
 
 declare i32 @llvm.amdgcn.workitem.id.x()
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"amdgpu_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/call-argument-types.ll b/llvm/test/CodeGen/AMDGPU/call-argument-types.ll
index 4e2b83af7f5e..a192a1b8dff9 100644
--- a/llvm/test/CodeGen/AMDGPU/call-argument-types.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-argument-types.ll
@@ -67,9 +67,8 @@ define amdgpu_kernel void @test_call_external_void_func_i1_imm() #0 {
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    v_mov_b32_e32 v0, 1
@@ -86,9 +85,8 @@ define amdgpu_kernel void @test_call_external_void_func_i1_imm() #0 {
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    v_mov_b32_e32 v0, 1
@@ -105,9 +103,8 @@ define amdgpu_kernel void @test_call_external_void_func_i1_imm() #0 {
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 1
@@ -121,29 +118,27 @@ define amdgpu_kernel void @test_call_external_void_func_i1_imm() #0 {
 ; GFX11-LABEL: test_call_external_void_func_i1_imm:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    v_mov_b32_e32 v0, 1
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_i1@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_i1@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_i1@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_i1@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_i1_imm:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s9
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s7
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    v_mov_b32_e32 v0, 1
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_i1@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_i1@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_i1@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_i1@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   call void @external_void_func_i1(i1 true)
   ret void
@@ -152,17 +147,16 @@ define amdgpu_kernel void @test_call_external_void_func_i1_imm() #0 {
 define amdgpu_kernel void @test_call_external_void_func_i1_signext(i32) #0 {
 ; VI-LABEL: test_call_external_void_func_i1_signext:
 ; VI:       ; %bb.0:
-; VI-NEXT:    s_mov_b32 s3, 0xf000
-; VI-NEXT:    s_mov_b32 s2, -1
-; VI-NEXT:    buffer_load_ubyte v0, off, s[0:3], 0 glc
-; VI-NEXT:    s_waitcnt vmcnt(0)
 ; VI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s5
+; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_mov_b32 s3, 0xf000
+; VI-NEXT:    s_mov_b32 s2, -1
+; VI-NEXT:    buffer_load_ubyte v0, off, s[0:3], 0 glc
+; VI-NEXT:    s_waitcnt vmcnt(0)
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    s_mov_b32 s32, 0
@@ -175,17 +169,16 @@ define amdgpu_kernel void @test_call_external_void_func_i1_signext(i32) #0 {
 ;
 ; CI-LABEL: test_call_external_void_func_i1_signext:
 ; CI:       ; %bb.0:
-; CI-NEXT:    s_mov_b32 s3, 0xf000
-; CI-NEXT:    s_mov_b32 s2, -1
-; CI-NEXT:    buffer_load_ubyte v0, off, s[0:3], 0 glc
-; CI-NEXT:    s_waitcnt vmcnt(0)
 ; CI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s5
+; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_mov_b32 s3, 0xf000
+; CI-NEXT:    s_mov_b32 s2, -1
+; CI-NEXT:    buffer_load_ubyte v0, off, s[0:3], 0 glc
+; CI-NEXT:    s_waitcnt vmcnt(0)
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    s_mov_b32 s32, 0
@@ -198,17 +191,16 @@ define amdgpu_kernel void @test_call_external_void_func_i1_signext(i32) #0 {
 ;
 ; GFX9-LABEL: test_call_external_void_func_i1_signext:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_mov_b32 s3, 0xf000
-; GFX9-NEXT:    s_mov_b32 s2, -1
-; GFX9-NEXT:    buffer_load_ubyte v0, off, s[0:3], 0 glc
-; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s5
+; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_mov_b32 s3, 0xf000
+; GFX9-NEXT:    s_mov_b32 s2, -1
+; GFX9-NEXT:    buffer_load_ubyte v0, off, s[0:3], 0 glc
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
@@ -223,35 +215,33 @@ define amdgpu_kernel void @test_call_external_void_func_i1_signext(i32) #0 {
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
+; GFX11-NEXT:    s_mov_b32 s32, 0
 ; GFX11-NEXT:    buffer_load_u8 v0, off, s[0:3], 0 glc dlc
 ; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_i1_signext@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_i1_signext@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_i1_signext@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_i1_signext@rel32@hi+12
 ; GFX11-NEXT:    v_bfe_i32 v0, v0, 0, 1
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_i1_signext:
 ; HSA:       ; %bb.0:
+; HSA-NEXT:    s_add_i32 s6, s6, s9
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
 ; HSA-NEXT:    s_mov_b32 s7, 0x1100f000
 ; HSA-NEXT:    s_mov_b32 s6, -1
 ; HSA-NEXT:    buffer_load_ubyte v0, off, s[4:7], 0 glc
 ; HSA-NEXT:    s_waitcnt vmcnt(0)
-; HSA-NEXT:    s_add_i32 s8, s8, s11
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s8, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s11
+; HSA-NEXT:    s_add_u32 s0, s0, s9
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s9
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_i1_signext@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_i1_signext@rel32@hi+12
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_i1_signext@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_i1_signext@rel32@hi+12
 ; HSA-NEXT:    v_bfe_i32 v0, v0, 0, 1
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   %var = load volatile i1, ptr addrspace(1) undef
   call void @external_void_func_i1_signext(i1 signext %var)
@@ -262,17 +252,16 @@ define amdgpu_kernel void @test_call_external_void_func_i1_signext(i32) #0 {
 define amdgpu_kernel void @test_call_external_void_func_i1_zeroext(i32) #0 {
 ; VI-LABEL: test_call_external_void_func_i1_zeroext:
 ; VI:       ; %bb.0:
-; VI-NEXT:    s_mov_b32 s3, 0xf000
-; VI-NEXT:    s_mov_b32 s2, -1
-; VI-NEXT:    buffer_load_ubyte v0, off, s[0:3], 0 glc
-; VI-NEXT:    s_waitcnt vmcnt(0)
 ; VI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s5
+; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_mov_b32 s3, 0xf000
+; VI-NEXT:    s_mov_b32 s2, -1
+; VI-NEXT:    buffer_load_ubyte v0, off, s[0:3], 0 glc
+; VI-NEXT:    s_waitcnt vmcnt(0)
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    s_mov_b32 s32, 0
@@ -285,17 +274,16 @@ define amdgpu_kernel void @test_call_external_void_func_i1_zeroext(i32) #0 {
 ;
 ; CI-LABEL: test_call_external_void_func_i1_zeroext:
 ; CI:       ; %bb.0:
-; CI-NEXT:    s_mov_b32 s3, 0xf000
-; CI-NEXT:    s_mov_b32 s2, -1
-; CI-NEXT:    buffer_load_ubyte v0, off, s[0:3], 0 glc
-; CI-NEXT:    s_waitcnt vmcnt(0)
 ; CI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s5
+; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_mov_b32 s3, 0xf000
+; CI-NEXT:    s_mov_b32 s2, -1
+; CI-NEXT:    buffer_load_ubyte v0, off, s[0:3], 0 glc
+; CI-NEXT:    s_waitcnt vmcnt(0)
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    s_mov_b32 s32, 0
@@ -308,17 +296,16 @@ define amdgpu_kernel void @test_call_external_void_func_i1_zeroext(i32) #0 {
 ;
 ; GFX9-LABEL: test_call_external_void_func_i1_zeroext:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_mov_b32 s3, 0xf000
-; GFX9-NEXT:    s_mov_b32 s2, -1
-; GFX9-NEXT:    buffer_load_ubyte v0, off, s[0:3], 0 glc
-; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s5
+; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_mov_b32 s3, 0xf000
+; GFX9-NEXT:    s_mov_b32 s2, -1
+; GFX9-NEXT:    buffer_load_ubyte v0, off, s[0:3], 0 glc
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
@@ -333,35 +320,33 @@ define amdgpu_kernel void @test_call_external_void_func_i1_zeroext(i32) #0 {
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
+; GFX11-NEXT:    s_mov_b32 s32, 0
 ; GFX11-NEXT:    buffer_load_u8 v0, off, s[0:3], 0 glc dlc
 ; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_i1_zeroext@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_i1_zeroext@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_i1_zeroext@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_i1_zeroext@rel32@hi+12
 ; GFX11-NEXT:    v_and_b32_e32 v0, 1, v0
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_i1_zeroext:
 ; HSA:       ; %bb.0:
+; HSA-NEXT:    s_add_i32 s6, s6, s9
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
 ; HSA-NEXT:    s_mov_b32 s7, 0x1100f000
 ; HSA-NEXT:    s_mov_b32 s6, -1
 ; HSA-NEXT:    buffer_load_ubyte v0, off, s[4:7], 0 glc
 ; HSA-NEXT:    s_waitcnt vmcnt(0)
-; HSA-NEXT:    s_add_i32 s8, s8, s11
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s8, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s11
+; HSA-NEXT:    s_add_u32 s0, s0, s9
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s9
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_i1_zeroext@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_i1_zeroext@rel32@hi+12
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_i1_zeroext@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_i1_zeroext@rel32@hi+12
 ; HSA-NEXT:    v_and_b32_e32 v0, 1, v0
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   %var = load volatile i1, ptr addrspace(1) undef
   call void @external_void_func_i1_zeroext(i1 zeroext %var)
@@ -375,9 +360,8 @@ define amdgpu_kernel void @test_call_external_void_func_i8_imm(i32) #0 {
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s5
+; VI-NEXT:    s_add_u32 s36, s36, s3
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    v_mov_b32_e32 v0, 0x7b
@@ -394,9 +378,8 @@ define amdgpu_kernel void @test_call_external_void_func_i8_imm(i32) #0 {
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s5
+; CI-NEXT:    s_add_u32 s36, s36, s3
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    v_mov_b32_e32 v0, 0x7b
@@ -413,9 +396,8 @@ define amdgpu_kernel void @test_call_external_void_func_i8_imm(i32) #0 {
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s5
+; GFX9-NEXT:    s_add_u32 s36, s36, s3
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0x7b
@@ -429,29 +411,27 @@ define amdgpu_kernel void @test_call_external_void_func_i8_imm(i32) #0 {
 ; GFX11-LABEL: test_call_external_void_func_i8_imm:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    v_mov_b32_e32 v0, 0x7b
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_i8@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_i8@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_i8@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_i8@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_i8_imm:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s8, s8, s11
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s8, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s11
+; HSA-NEXT:    s_add_i32 s6, s6, s9
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s9
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    v_mov_b32_e32 v0, 0x7b
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s9
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_i8@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_i8@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_i8@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_i8@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   call void @external_void_func_i8(i8 123)
   ret void
@@ -461,17 +441,16 @@ define amdgpu_kernel void @test_call_external_void_func_i8_imm(i32) #0 {
 define amdgpu_kernel void @test_call_external_void_func_i8_signext(i32) #0 {
 ; VI-LABEL: test_call_external_void_func_i8_signext:
 ; VI:       ; %bb.0:
-; VI-NEXT:    s_mov_b32 s3, 0xf000
-; VI-NEXT:    s_mov_b32 s2, -1
-; VI-NEXT:    buffer_load_sbyte v0, off, s[0:3], 0 glc
-; VI-NEXT:    s_waitcnt vmcnt(0)
 ; VI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s5
+; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_mov_b32 s3, 0xf000
+; VI-NEXT:    s_mov_b32 s2, -1
+; VI-NEXT:    buffer_load_sbyte v0, off, s[0:3], 0 glc
+; VI-NEXT:    s_waitcnt vmcnt(0)
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    s_mov_b32 s32, 0
@@ -483,17 +462,16 @@ define amdgpu_kernel void @test_call_external_void_func_i8_signext(i32) #0 {
 ;
 ; CI-LABEL: test_call_external_void_func_i8_signext:
 ; CI:       ; %bb.0:
-; CI-NEXT:    s_mov_b32 s3, 0xf000
-; CI-NEXT:    s_mov_b32 s2, -1
-; CI-NEXT:    buffer_load_sbyte v0, off, s[0:3], 0 glc
-; CI-NEXT:    s_waitcnt vmcnt(0)
 ; CI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s5
+; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_mov_b32 s3, 0xf000
+; CI-NEXT:    s_mov_b32 s2, -1
+; CI-NEXT:    buffer_load_sbyte v0, off, s[0:3], 0 glc
+; CI-NEXT:    s_waitcnt vmcnt(0)
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    s_mov_b32 s32, 0
@@ -505,17 +483,16 @@ define amdgpu_kernel void @test_call_external_void_func_i8_signext(i32) #0 {
 ;
 ; GFX9-LABEL: test_call_external_void_func_i8_signext:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_mov_b32 s3, 0xf000
-; GFX9-NEXT:    s_mov_b32 s2, -1
-; GFX9-NEXT:    buffer_load_sbyte v0, off, s[0:3], 0 glc
-; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s5
+; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_mov_b32 s3, 0xf000
+; GFX9-NEXT:    s_mov_b32 s2, -1
+; GFX9-NEXT:    buffer_load_sbyte v0, off, s[0:3], 0 glc
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
@@ -529,34 +506,32 @@ define amdgpu_kernel void @test_call_external_void_func_i8_signext(i32) #0 {
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
+; GFX11-NEXT:    s_mov_b32 s32, 0
 ; GFX11-NEXT:    buffer_load_i8 v0, off, s[0:3], 0 glc dlc
 ; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_i8_signext@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_i8_signext@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_i8_signext@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_i8_signext@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_i8_signext:
 ; HSA:       ; %bb.0:
+; HSA-NEXT:    s_add_i32 s6, s6, s9
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
 ; HSA-NEXT:    s_mov_b32 s7, 0x1100f000
 ; HSA-NEXT:    s_mov_b32 s6, -1
 ; HSA-NEXT:    buffer_load_sbyte v0, off, s[4:7], 0 glc
 ; HSA-NEXT:    s_waitcnt vmcnt(0)
-; HSA-NEXT:    s_add_i32 s8, s8, s11
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s8, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s11
+; HSA-NEXT:    s_add_u32 s0, s0, s9
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s9
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_i8_signext@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_i8_signext@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_i8_signext@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_i8_signext@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   %var = load volatile i8, ptr addrspace(1) undef
   call void @external_void_func_i8_signext(i8 signext %var)
@@ -566,17 +541,16 @@ define amdgpu_kernel void @test_call_external_void_func_i8_signext(i32) #0 {
 define amdgpu_kernel void @test_call_external_void_func_i8_zeroext(i32) #0 {
 ; VI-LABEL: test_call_external_void_func_i8_zeroext:
 ; VI:       ; %bb.0:
-; VI-NEXT:    s_mov_b32 s3, 0xf000
-; VI-NEXT:    s_mov_b32 s2, -1
-; VI-NEXT:    buffer_load_ubyte v0, off, s[0:3], 0 glc
-; VI-NEXT:    s_waitcnt vmcnt(0)
 ; VI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s5
+; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_mov_b32 s3, 0xf000
+; VI-NEXT:    s_mov_b32 s2, -1
+; VI-NEXT:    buffer_load_ubyte v0, off, s[0:3], 0 glc
+; VI-NEXT:    s_waitcnt vmcnt(0)
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    s_mov_b32 s32, 0
@@ -588,17 +562,16 @@ define amdgpu_kernel void @test_call_external_void_func_i8_zeroext(i32) #0 {
 ;
 ; CI-LABEL: test_call_external_void_func_i8_zeroext:
 ; CI:       ; %bb.0:
-; CI-NEXT:    s_mov_b32 s3, 0xf000
-; CI-NEXT:    s_mov_b32 s2, -1
-; CI-NEXT:    buffer_load_ubyte v0, off, s[0:3], 0 glc
-; CI-NEXT:    s_waitcnt vmcnt(0)
 ; CI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s5
+; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_mov_b32 s3, 0xf000
+; CI-NEXT:    s_mov_b32 s2, -1
+; CI-NEXT:    buffer_load_ubyte v0, off, s[0:3], 0 glc
+; CI-NEXT:    s_waitcnt vmcnt(0)
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    s_mov_b32 s32, 0
@@ -610,17 +583,16 @@ define amdgpu_kernel void @test_call_external_void_func_i8_zeroext(i32) #0 {
 ;
 ; GFX9-LABEL: test_call_external_void_func_i8_zeroext:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_mov_b32 s3, 0xf000
-; GFX9-NEXT:    s_mov_b32 s2, -1
-; GFX9-NEXT:    buffer_load_ubyte v0, off, s[0:3], 0 glc
-; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s5
+; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_mov_b32 s3, 0xf000
+; GFX9-NEXT:    s_mov_b32 s2, -1
+; GFX9-NEXT:    buffer_load_ubyte v0, off, s[0:3], 0 glc
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
@@ -634,34 +606,32 @@ define amdgpu_kernel void @test_call_external_void_func_i8_zeroext(i32) #0 {
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
+; GFX11-NEXT:    s_mov_b32 s32, 0
 ; GFX11-NEXT:    buffer_load_u8 v0, off, s[0:3], 0 glc dlc
 ; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_i8_zeroext@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_i8_zeroext@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_i8_zeroext@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_i8_zeroext@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_i8_zeroext:
 ; HSA:       ; %bb.0:
+; HSA-NEXT:    s_add_i32 s6, s6, s9
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
 ; HSA-NEXT:    s_mov_b32 s7, 0x1100f000
 ; HSA-NEXT:    s_mov_b32 s6, -1
 ; HSA-NEXT:    buffer_load_ubyte v0, off, s[4:7], 0 glc
 ; HSA-NEXT:    s_waitcnt vmcnt(0)
-; HSA-NEXT:    s_add_i32 s8, s8, s11
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s8, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s11
+; HSA-NEXT:    s_add_u32 s0, s0, s9
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s9
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_i8_zeroext@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_i8_zeroext@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_i8_zeroext@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_i8_zeroext@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   %var = load volatile i8, ptr addrspace(1) undef
   call void @external_void_func_i8_zeroext(i8 zeroext %var)
@@ -675,9 +645,8 @@ define amdgpu_kernel void @test_call_external_void_func_i16_imm() #0 {
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    v_mov_b32_e32 v0, 0x7b
@@ -694,9 +663,8 @@ define amdgpu_kernel void @test_call_external_void_func_i16_imm() #0 {
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    v_mov_b32_e32 v0, 0x7b
@@ -713,9 +681,8 @@ define amdgpu_kernel void @test_call_external_void_func_i16_imm() #0 {
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0x7b
@@ -729,29 +696,27 @@ define amdgpu_kernel void @test_call_external_void_func_i16_imm() #0 {
 ; GFX11-LABEL: test_call_external_void_func_i16_imm:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    v_mov_b32_e32 v0, 0x7b
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_i16@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_i16@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_i16@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_i16@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_i16_imm:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s9
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s7
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    v_mov_b32_e32 v0, 0x7b
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_i16@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_i16@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_i16@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_i16@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   call void @external_void_func_i16(i16 123)
   ret void
@@ -760,17 +725,16 @@ define amdgpu_kernel void @test_call_external_void_func_i16_imm() #0 {
 define amdgpu_kernel void @test_call_external_void_func_i16_signext(i32) #0 {
 ; VI-LABEL: test_call_external_void_func_i16_signext:
 ; VI:       ; %bb.0:
-; VI-NEXT:    s_mov_b32 s3, 0xf000
-; VI-NEXT:    s_mov_b32 s2, -1
-; VI-NEXT:    buffer_load_sshort v0, off, s[0:3], 0 glc
-; VI-NEXT:    s_waitcnt vmcnt(0)
 ; VI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s5
+; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_mov_b32 s3, 0xf000
+; VI-NEXT:    s_mov_b32 s2, -1
+; VI-NEXT:    buffer_load_sshort v0, off, s[0:3], 0 glc
+; VI-NEXT:    s_waitcnt vmcnt(0)
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    s_mov_b32 s32, 0
@@ -782,17 +746,16 @@ define amdgpu_kernel void @test_call_external_void_func_i16_signext(i32) #0 {
 ;
 ; CI-LABEL: test_call_external_void_func_i16_signext:
 ; CI:       ; %bb.0:
-; CI-NEXT:    s_mov_b32 s3, 0xf000
-; CI-NEXT:    s_mov_b32 s2, -1
-; CI-NEXT:    buffer_load_sshort v0, off, s[0:3], 0 glc
-; CI-NEXT:    s_waitcnt vmcnt(0)
 ; CI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s5
+; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_mov_b32 s3, 0xf000
+; CI-NEXT:    s_mov_b32 s2, -1
+; CI-NEXT:    buffer_load_sshort v0, off, s[0:3], 0 glc
+; CI-NEXT:    s_waitcnt vmcnt(0)
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    s_mov_b32 s32, 0
@@ -804,17 +767,16 @@ define amdgpu_kernel void @test_call_external_void_func_i16_signext(i32) #0 {
 ;
 ; GFX9-LABEL: test_call_external_void_func_i16_signext:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_mov_b32 s3, 0xf000
-; GFX9-NEXT:    s_mov_b32 s2, -1
-; GFX9-NEXT:    buffer_load_sshort v0, off, s[0:3], 0 glc
-; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s5
+; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_mov_b32 s3, 0xf000
+; GFX9-NEXT:    s_mov_b32 s2, -1
+; GFX9-NEXT:    buffer_load_sshort v0, off, s[0:3], 0 glc
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
@@ -828,34 +790,32 @@ define amdgpu_kernel void @test_call_external_void_func_i16_signext(i32) #0 {
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
+; GFX11-NEXT:    s_mov_b32 s32, 0
 ; GFX11-NEXT:    buffer_load_i16 v0, off, s[0:3], 0 glc dlc
 ; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_i16_signext@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_i16_signext@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_i16_signext@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_i16_signext@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_i16_signext:
 ; HSA:       ; %bb.0:
+; HSA-NEXT:    s_add_i32 s6, s6, s9
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
 ; HSA-NEXT:    s_mov_b32 s7, 0x1100f000
 ; HSA-NEXT:    s_mov_b32 s6, -1
 ; HSA-NEXT:    buffer_load_sshort v0, off, s[4:7], 0 glc
 ; HSA-NEXT:    s_waitcnt vmcnt(0)
-; HSA-NEXT:    s_add_i32 s8, s8, s11
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s8, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s11
+; HSA-NEXT:    s_add_u32 s0, s0, s9
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s9
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_i16_signext@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_i16_signext@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_i16_signext@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_i16_signext@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   %var = load volatile i16, ptr addrspace(1) undef
   call void @external_void_func_i16_signext(i16 signext %var)
@@ -865,17 +825,16 @@ define amdgpu_kernel void @test_call_external_void_func_i16_signext(i32) #0 {
 define amdgpu_kernel void @test_call_external_void_func_i16_zeroext(i32) #0 {
 ; VI-LABEL: test_call_external_void_func_i16_zeroext:
 ; VI:       ; %bb.0:
-; VI-NEXT:    s_mov_b32 s3, 0xf000
-; VI-NEXT:    s_mov_b32 s2, -1
-; VI-NEXT:    buffer_load_ushort v0, off, s[0:3], 0 glc
-; VI-NEXT:    s_waitcnt vmcnt(0)
 ; VI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s5
+; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_mov_b32 s3, 0xf000
+; VI-NEXT:    s_mov_b32 s2, -1
+; VI-NEXT:    buffer_load_ushort v0, off, s[0:3], 0 glc
+; VI-NEXT:    s_waitcnt vmcnt(0)
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    s_mov_b32 s32, 0
@@ -887,17 +846,16 @@ define amdgpu_kernel void @test_call_external_void_func_i16_zeroext(i32) #0 {
 ;
 ; CI-LABEL: test_call_external_void_func_i16_zeroext:
 ; CI:       ; %bb.0:
-; CI-NEXT:    s_mov_b32 s3, 0xf000
-; CI-NEXT:    s_mov_b32 s2, -1
-; CI-NEXT:    buffer_load_ushort v0, off, s[0:3], 0 glc
-; CI-NEXT:    s_waitcnt vmcnt(0)
 ; CI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s5
+; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_mov_b32 s3, 0xf000
+; CI-NEXT:    s_mov_b32 s2, -1
+; CI-NEXT:    buffer_load_ushort v0, off, s[0:3], 0 glc
+; CI-NEXT:    s_waitcnt vmcnt(0)
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    s_mov_b32 s32, 0
@@ -909,17 +867,16 @@ define amdgpu_kernel void @test_call_external_void_func_i16_zeroext(i32) #0 {
 ;
 ; GFX9-LABEL: test_call_external_void_func_i16_zeroext:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_mov_b32 s3, 0xf000
-; GFX9-NEXT:    s_mov_b32 s2, -1
-; GFX9-NEXT:    buffer_load_ushort v0, off, s[0:3], 0 glc
-; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s5
+; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_mov_b32 s3, 0xf000
+; GFX9-NEXT:    s_mov_b32 s2, -1
+; GFX9-NEXT:    buffer_load_ushort v0, off, s[0:3], 0 glc
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
@@ -933,34 +890,32 @@ define amdgpu_kernel void @test_call_external_void_func_i16_zeroext(i32) #0 {
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
+; GFX11-NEXT:    s_mov_b32 s32, 0
 ; GFX11-NEXT:    buffer_load_u16 v0, off, s[0:3], 0 glc dlc
 ; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_i16_zeroext@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_i16_zeroext@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_i16_zeroext@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_i16_zeroext@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_i16_zeroext:
 ; HSA:       ; %bb.0:
+; HSA-NEXT:    s_add_i32 s6, s6, s9
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
 ; HSA-NEXT:    s_mov_b32 s7, 0x1100f000
 ; HSA-NEXT:    s_mov_b32 s6, -1
 ; HSA-NEXT:    buffer_load_ushort v0, off, s[4:7], 0 glc
 ; HSA-NEXT:    s_waitcnt vmcnt(0)
-; HSA-NEXT:    s_add_i32 s8, s8, s11
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s8, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s11
+; HSA-NEXT:    s_add_u32 s0, s0, s9
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s9
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_i16_zeroext@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_i16_zeroext@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_i16_zeroext@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_i16_zeroext@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   %var = load volatile i16, ptr addrspace(1) undef
   call void @external_void_func_i16_zeroext(i16 zeroext %var)
@@ -974,9 +929,8 @@ define amdgpu_kernel void @test_call_external_void_func_i32_imm(i32) #0 {
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s5
+; VI-NEXT:    s_add_u32 s36, s36, s3
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    v_mov_b32_e32 v0, 42
@@ -993,9 +947,8 @@ define amdgpu_kernel void @test_call_external_void_func_i32_imm(i32) #0 {
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s5
+; CI-NEXT:    s_add_u32 s36, s36, s3
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    v_mov_b32_e32 v0, 42
@@ -1012,9 +965,8 @@ define amdgpu_kernel void @test_call_external_void_func_i32_imm(i32) #0 {
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s5
+; GFX9-NEXT:    s_add_u32 s36, s36, s3
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 42
@@ -1028,29 +980,27 @@ define amdgpu_kernel void @test_call_external_void_func_i32_imm(i32) #0 {
 ; GFX11-LABEL: test_call_external_void_func_i32_imm:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    v_mov_b32_e32 v0, 42
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_i32@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_i32@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_i32@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_i32@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_i32_imm:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s8, s8, s11
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s8, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s11
+; HSA-NEXT:    s_add_i32 s6, s6, s9
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s9
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    v_mov_b32_e32 v0, 42
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s9
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_i32@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_i32@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_i32@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_i32@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   call void @external_void_func_i32(i32 42)
   ret void
@@ -1063,9 +1013,8 @@ define amdgpu_kernel void @test_call_external_void_func_i64_imm() #0 {
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    v_mov_b32_e32 v0, 0x7b
@@ -1083,9 +1032,8 @@ define amdgpu_kernel void @test_call_external_void_func_i64_imm() #0 {
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    v_mov_b32_e32 v0, 0x7b
@@ -1103,9 +1051,8 @@ define amdgpu_kernel void @test_call_external_void_func_i64_imm() #0 {
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0x7b
@@ -1120,30 +1067,28 @@ define amdgpu_kernel void @test_call_external_void_func_i64_imm() #0 {
 ; GFX11-LABEL: test_call_external_void_func_i64_imm:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    v_dual_mov_b32 v0, 0x7b :: v_dual_mov_b32 v1, 0
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_i64@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_i64@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_i64@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_i64@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_i64_imm:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s9
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s7
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    v_mov_b32_e32 v0, 0x7b
 ; HSA-NEXT:    v_mov_b32_e32 v1, 0
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_i64@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_i64@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_i64@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_i64@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   call void @external_void_func_i64(i64 123)
   ret void
@@ -1156,9 +1101,8 @@ define amdgpu_kernel void @test_call_external_void_func_v2i64() #0 {
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b32 s0, 0
-; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_mov_b32 s3, 0xf000
 ; VI-NEXT:    s_mov_b32 s2, -1
 ; VI-NEXT:    s_mov_b32 s1, s0
@@ -1179,9 +1123,8 @@ define amdgpu_kernel void @test_call_external_void_func_v2i64() #0 {
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b32 s0, 0
-; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_mov_b32 s3, 0xf000
 ; CI-NEXT:    s_mov_b32 s2, -1
 ; CI-NEXT:    s_mov_b32 s1, s0
@@ -1202,9 +1145,8 @@ define amdgpu_kernel void @test_call_external_void_func_v2i64() #0 {
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b32 s0, 0
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX9-NEXT:    s_mov_b32 s2, -1
 ; GFX9-NEXT:    s_mov_b32 s1, s0
@@ -1221,38 +1163,36 @@ define amdgpu_kernel void @test_call_external_void_func_v2i64() #0 {
 ;
 ; GFX11-LABEL: test_call_external_void_func_v2i64:
 ; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_mov_b32 s4, 0
-; GFX11-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX11-NEXT:    s_mov_b32 s6, -1
-; GFX11-NEXT:    s_mov_b32 s5, s4
+; GFX11-NEXT:    s_mov_b32 s0, 0
+; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-NEXT:    s_mov_b32 s2, -1
+; GFX11-NEXT:    s_mov_b32 s1, s0
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    buffer_load_b128 v[0:3], off, s[4:7], 0
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v2i64@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v2i64@rel32@hi+12
+; GFX11-NEXT:    buffer_load_b128 v[0:3], off, s[0:3], 0
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v2i64@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v2i64@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v2i64:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
-; HSA-NEXT:    s_mov_b32 s8, 0
-; HSA-NEXT:    s_add_u32 s0, s0, s9
-; HSA-NEXT:    s_mov_b32 s11, 0x1100f000
-; HSA-NEXT:    s_mov_b32 s10, -1
-; HSA-NEXT:    s_mov_b32 s9, s8
-; HSA-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_mov_b32 s4, 0
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_add_u32 s0, s0, s7
+; HSA-NEXT:    s_mov_b32 s7, 0x1100f000
+; HSA-NEXT:    s_mov_b32 s6, -1
+; HSA-NEXT:    s_mov_b32 s5, s4
+; HSA-NEXT:    buffer_load_dwordx4 v[0:3], off, s[4:7], 0
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v2i64@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v2i64@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v2i64@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v2i64@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   %val = load <2 x i64>, ptr addrspace(1) null
   call void @external_void_func_v2i64(<2 x i64> %val)
@@ -1266,9 +1206,8 @@ define amdgpu_kernel void @test_call_external_void_func_v2i64_imm() #0 {
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    v_mov_b32_e32 v0, 1
@@ -1288,9 +1227,8 @@ define amdgpu_kernel void @test_call_external_void_func_v2i64_imm() #0 {
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    v_mov_b32_e32 v0, 1
@@ -1310,9 +1248,8 @@ define amdgpu_kernel void @test_call_external_void_func_v2i64_imm() #0 {
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 1
@@ -1330,32 +1267,30 @@ define amdgpu_kernel void @test_call_external_void_func_v2i64_imm() #0 {
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 2
 ; GFX11-NEXT:    v_dual_mov_b32 v2, 3 :: v_dual_mov_b32 v3, 4
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v2i64@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v2i64@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v2i64@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v2i64@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v2i64_imm:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s9
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s7
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    v_mov_b32_e32 v0, 1
 ; HSA-NEXT:    v_mov_b32_e32 v1, 2
 ; HSA-NEXT:    v_mov_b32_e32 v2, 3
 ; HSA-NEXT:    v_mov_b32_e32 v3, 4
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v2i64@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v2i64@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v2i64@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v2i64@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   call void @external_void_func_v2i64(<2 x i64> <i64 8589934593, i64 17179869187>)
   ret void
@@ -1368,9 +1303,8 @@ define amdgpu_kernel void @test_call_external_void_func_v3i64() #0 {
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b32 s0, 0
-; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_mov_b32 s3, 0xf000
 ; VI-NEXT:    s_mov_b32 s2, -1
 ; VI-NEXT:    s_mov_b32 s1, s0
@@ -1393,9 +1327,8 @@ define amdgpu_kernel void @test_call_external_void_func_v3i64() #0 {
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b32 s0, 0
-; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_mov_b32 s3, 0xf000
 ; CI-NEXT:    s_mov_b32 s2, -1
 ; CI-NEXT:    s_mov_b32 s1, s0
@@ -1418,9 +1351,8 @@ define amdgpu_kernel void @test_call_external_void_func_v3i64() #0 {
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b32 s0, 0
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX9-NEXT:    s_mov_b32 s2, -1
 ; GFX9-NEXT:    s_mov_b32 s1, s0
@@ -1439,41 +1371,39 @@ define amdgpu_kernel void @test_call_external_void_func_v3i64() #0 {
 ;
 ; GFX11-LABEL: test_call_external_void_func_v3i64:
 ; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_mov_b32 s4, 0
-; GFX11-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX11-NEXT:    s_mov_b32 s6, -1
-; GFX11-NEXT:    s_mov_b32 s5, s4
+; GFX11-NEXT:    s_mov_b32 s0, 0
+; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-NEXT:    s_mov_b32 s2, -1
+; GFX11-NEXT:    s_mov_b32 s1, s0
 ; GFX11-NEXT:    v_dual_mov_b32 v4, 1 :: v_dual_mov_b32 v5, 2
-; GFX11-NEXT:    buffer_load_b128 v[0:3], off, s[4:7], 0
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
+; GFX11-NEXT:    buffer_load_b128 v[0:3], off, s[0:3], 0
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v3i64@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v3i64@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v3i64@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v3i64@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v3i64:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
-; HSA-NEXT:    s_mov_b32 s8, 0
-; HSA-NEXT:    s_add_u32 s0, s0, s9
-; HSA-NEXT:    s_mov_b32 s11, 0x1100f000
-; HSA-NEXT:    s_mov_b32 s10, -1
-; HSA-NEXT:    s_mov_b32 s9, s8
-; HSA-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_mov_b32 s4, 0
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_add_u32 s0, s0, s7
+; HSA-NEXT:    s_mov_b32 s7, 0x1100f000
+; HSA-NEXT:    s_mov_b32 s6, -1
+; HSA-NEXT:    s_mov_b32 s5, s4
+; HSA-NEXT:    buffer_load_dwordx4 v[0:3], off, s[4:7], 0
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
 ; HSA-NEXT:    v_mov_b32_e32 v4, 1
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    v_mov_b32_e32 v5, 2
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v3i64@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v3i64@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v3i64@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v3i64@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   %load = load <2 x i64>, ptr addrspace(1) null
   %val = shufflevector <2 x i64> %load, <2 x i64> <i64 8589934593, i64 undef>, <3 x i32> <i32 0, i32 1, i32 2>
@@ -1489,9 +1419,8 @@ define amdgpu_kernel void @test_call_external_void_func_v4i64() #0 {
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b32 s0, 0
-; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_mov_b32 s3, 0xf000
 ; VI-NEXT:    s_mov_b32 s2, -1
 ; VI-NEXT:    s_mov_b32 s1, s0
@@ -1516,9 +1445,8 @@ define amdgpu_kernel void @test_call_external_void_func_v4i64() #0 {
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b32 s0, 0
-; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_mov_b32 s3, 0xf000
 ; CI-NEXT:    s_mov_b32 s2, -1
 ; CI-NEXT:    s_mov_b32 s1, s0
@@ -1543,9 +1471,8 @@ define amdgpu_kernel void @test_call_external_void_func_v4i64() #0 {
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b32 s0, 0
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX9-NEXT:    s_mov_b32 s2, -1
 ; GFX9-NEXT:    s_mov_b32 s1, s0
@@ -1566,44 +1493,42 @@ define amdgpu_kernel void @test_call_external_void_func_v4i64() #0 {
 ;
 ; GFX11-LABEL: test_call_external_void_func_v4i64:
 ; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_mov_b32 s4, 0
-; GFX11-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX11-NEXT:    s_mov_b32 s6, -1
-; GFX11-NEXT:    s_mov_b32 s5, s4
+; GFX11-NEXT:    s_mov_b32 s0, 0
+; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-NEXT:    s_mov_b32 s2, -1
+; GFX11-NEXT:    s_mov_b32 s1, s0
 ; GFX11-NEXT:    v_dual_mov_b32 v4, 1 :: v_dual_mov_b32 v5, 2
-; GFX11-NEXT:    buffer_load_b128 v[0:3], off, s[4:7], 0
+; GFX11-NEXT:    buffer_load_b128 v[0:3], off, s[0:3], 0
 ; GFX11-NEXT:    v_dual_mov_b32 v6, 3 :: v_dual_mov_b32 v7, 4
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v4i64@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v4i64@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v4i64@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v4i64@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v4i64:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
-; HSA-NEXT:    s_mov_b32 s8, 0
-; HSA-NEXT:    s_add_u32 s0, s0, s9
-; HSA-NEXT:    s_mov_b32 s11, 0x1100f000
-; HSA-NEXT:    s_mov_b32 s10, -1
-; HSA-NEXT:    s_mov_b32 s9, s8
-; HSA-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_mov_b32 s4, 0
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_add_u32 s0, s0, s7
+; HSA-NEXT:    s_mov_b32 s7, 0x1100f000
+; HSA-NEXT:    s_mov_b32 s6, -1
+; HSA-NEXT:    s_mov_b32 s5, s4
+; HSA-NEXT:    buffer_load_dwordx4 v[0:3], off, s[4:7], 0
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
 ; HSA-NEXT:    v_mov_b32_e32 v4, 1
 ; HSA-NEXT:    v_mov_b32_e32 v5, 2
 ; HSA-NEXT:    v_mov_b32_e32 v6, 3
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    v_mov_b32_e32 v7, 4
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v4i64@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v4i64@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v4i64@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v4i64@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   %load = load <2 x i64>, ptr addrspace(1) null
   %val = shufflevector <2 x i64> %load, <2 x i64> <i64 8589934593, i64 17179869187>, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
@@ -1618,9 +1543,8 @@ define amdgpu_kernel void @test_call_external_void_func_f16_imm() #0 {
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    v_mov_b32_e32 v0, 0x4400
@@ -1637,9 +1561,8 @@ define amdgpu_kernel void @test_call_external_void_func_f16_imm() #0 {
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    v_mov_b32_e32 v0, 4.0
@@ -1656,9 +1579,8 @@ define amdgpu_kernel void @test_call_external_void_func_f16_imm() #0 {
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0x4400
@@ -1672,29 +1594,27 @@ define amdgpu_kernel void @test_call_external_void_func_f16_imm() #0 {
 ; GFX11-LABEL: test_call_external_void_func_f16_imm:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    v_mov_b32_e32 v0, 0x4400
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_f16@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_f16@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_f16@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_f16@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_f16_imm:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s9
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s7
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    v_mov_b32_e32 v0, 0x4400
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_f16@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_f16@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_f16@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_f16@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   call void @external_void_func_f16(half 4.0)
   ret void
@@ -1707,9 +1627,8 @@ define amdgpu_kernel void @test_call_external_void_func_f32_imm() #0 {
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    v_mov_b32_e32 v0, 4.0
@@ -1726,9 +1645,8 @@ define amdgpu_kernel void @test_call_external_void_func_f32_imm() #0 {
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    v_mov_b32_e32 v0, 4.0
@@ -1745,9 +1663,8 @@ define amdgpu_kernel void @test_call_external_void_func_f32_imm() #0 {
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 4.0
@@ -1761,29 +1678,27 @@ define amdgpu_kernel void @test_call_external_void_func_f32_imm() #0 {
 ; GFX11-LABEL: test_call_external_void_func_f32_imm:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    v_mov_b32_e32 v0, 4.0
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_f32@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_f32@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_f32@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_f32@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_f32_imm:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s9
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s7
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    v_mov_b32_e32 v0, 4.0
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_f32@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_f32@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_f32@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_f32@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   call void @external_void_func_f32(float 4.0)
   ret void
@@ -1796,9 +1711,8 @@ define amdgpu_kernel void @test_call_external_void_func_v2f32_imm() #0 {
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    v_mov_b32_e32 v0, 1.0
@@ -1816,9 +1730,8 @@ define amdgpu_kernel void @test_call_external_void_func_v2f32_imm() #0 {
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    v_mov_b32_e32 v0, 1.0
@@ -1836,9 +1749,8 @@ define amdgpu_kernel void @test_call_external_void_func_v2f32_imm() #0 {
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 1.0
@@ -1853,30 +1765,28 @@ define amdgpu_kernel void @test_call_external_void_func_v2f32_imm() #0 {
 ; GFX11-LABEL: test_call_external_void_func_v2f32_imm:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    v_dual_mov_b32 v0, 1.0 :: v_dual_mov_b32 v1, 2.0
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v2f32@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v2f32@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v2f32@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v2f32@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v2f32_imm:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s9
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s7
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    v_mov_b32_e32 v0, 1.0
 ; HSA-NEXT:    v_mov_b32_e32 v1, 2.0
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v2f32@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v2f32@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v2f32@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v2f32@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   call void @external_void_func_v2f32(<2 x float> <float 1.0, float 2.0>)
   ret void
@@ -1889,9 +1799,8 @@ define amdgpu_kernel void @test_call_external_void_func_v3f32_imm() #0 {
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    v_mov_b32_e32 v0, 1.0
@@ -1910,9 +1819,8 @@ define amdgpu_kernel void @test_call_external_void_func_v3f32_imm() #0 {
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    v_mov_b32_e32 v0, 1.0
@@ -1931,9 +1839,8 @@ define amdgpu_kernel void @test_call_external_void_func_v3f32_imm() #0 {
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 1.0
@@ -1950,31 +1857,29 @@ define amdgpu_kernel void @test_call_external_void_func_v3f32_imm() #0 {
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    v_dual_mov_b32 v0, 1.0 :: v_dual_mov_b32 v1, 2.0
 ; GFX11-NEXT:    v_mov_b32_e32 v2, 4.0
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v3f32@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v3f32@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v3f32@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v3f32@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v3f32_imm:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s9
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s7
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    v_mov_b32_e32 v0, 1.0
 ; HSA-NEXT:    v_mov_b32_e32 v1, 2.0
 ; HSA-NEXT:    v_mov_b32_e32 v2, 4.0
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v3f32@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v3f32@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v3f32@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v3f32@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   call void @external_void_func_v3f32(<3 x float> <float 1.0, float 2.0, float 4.0>)
   ret void
@@ -1987,9 +1892,8 @@ define amdgpu_kernel void @test_call_external_void_func_v5f32_imm() #0 {
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    v_mov_b32_e32 v0, 1.0
@@ -2010,9 +1914,8 @@ define amdgpu_kernel void @test_call_external_void_func_v5f32_imm() #0 {
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    v_mov_b32_e32 v0, 1.0
@@ -2033,9 +1936,8 @@ define amdgpu_kernel void @test_call_external_void_func_v5f32_imm() #0 {
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 1.0
@@ -2055,33 +1957,31 @@ define amdgpu_kernel void @test_call_external_void_func_v5f32_imm() #0 {
 ; GFX11-NEXT:    v_dual_mov_b32 v0, 1.0 :: v_dual_mov_b32 v1, 2.0
 ; GFX11-NEXT:    v_dual_mov_b32 v2, 4.0 :: v_dual_mov_b32 v3, -1.0
 ; GFX11-NEXT:    v_mov_b32_e32 v4, 0.5
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v5f32@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v5f32@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v5f32@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v5f32@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v5f32_imm:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s9
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s7
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    v_mov_b32_e32 v0, 1.0
 ; HSA-NEXT:    v_mov_b32_e32 v1, 2.0
 ; HSA-NEXT:    v_mov_b32_e32 v2, 4.0
 ; HSA-NEXT:    v_mov_b32_e32 v3, -1.0
 ; HSA-NEXT:    v_mov_b32_e32 v4, 0.5
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v5f32@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v5f32@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v5f32@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v5f32@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   call void @external_void_func_v5f32(<5 x float> <float 1.0, float 2.0, float 4.0, float -1.0, float 0.5>)
   ret void
@@ -2094,9 +1994,8 @@ define amdgpu_kernel void @test_call_external_void_func_f64_imm() #0 {
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    v_mov_b32_e32 v0, 0
@@ -2114,9 +2013,8 @@ define amdgpu_kernel void @test_call_external_void_func_f64_imm() #0 {
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    v_mov_b32_e32 v0, 0
@@ -2134,9 +2032,8 @@ define amdgpu_kernel void @test_call_external_void_func_f64_imm() #0 {
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0
@@ -2151,30 +2048,28 @@ define amdgpu_kernel void @test_call_external_void_func_f64_imm() #0 {
 ; GFX11-LABEL: test_call_external_void_func_f64_imm:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x40100000
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_f64@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_f64@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_f64@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_f64@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_f64_imm:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s9
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s7
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    v_mov_b32_e32 v0, 0
 ; HSA-NEXT:    v_mov_b32_e32 v1, 0x40100000
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_f64@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_f64@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_f64@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_f64@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   call void @external_void_func_f64(double 4.0)
   ret void
@@ -2187,9 +2082,8 @@ define amdgpu_kernel void @test_call_external_void_func_v2f64_imm() #0 {
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    v_mov_b32_e32 v0, 0
@@ -2209,9 +2103,8 @@ define amdgpu_kernel void @test_call_external_void_func_v2f64_imm() #0 {
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    v_mov_b32_e32 v0, 0
@@ -2231,9 +2124,8 @@ define amdgpu_kernel void @test_call_external_void_func_v2f64_imm() #0 {
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0
@@ -2251,32 +2143,30 @@ define amdgpu_kernel void @test_call_external_void_func_v2f64_imm() #0 {
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 2.0
 ; GFX11-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0x40100000
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v2f64@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v2f64@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v2f64@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v2f64@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v2f64_imm:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s9
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s7
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    v_mov_b32_e32 v0, 0
 ; HSA-NEXT:    v_mov_b32_e32 v1, 2.0
 ; HSA-NEXT:    v_mov_b32_e32 v2, 0
 ; HSA-NEXT:    v_mov_b32_e32 v3, 0x40100000
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v2f64@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v2f64@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v2f64@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v2f64@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   call void @external_void_func_v2f64(<2 x double> <double 2.0, double 4.0>)
   ret void
@@ -2289,9 +2179,8 @@ define amdgpu_kernel void @test_call_external_void_func_v3f64_imm() #0 {
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    v_mov_b32_e32 v0, 0
@@ -2313,9 +2202,8 @@ define amdgpu_kernel void @test_call_external_void_func_v3f64_imm() #0 {
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    v_mov_b32_e32 v0, 0
@@ -2337,9 +2225,8 @@ define amdgpu_kernel void @test_call_external_void_func_v3f64_imm() #0 {
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0
@@ -2360,23 +2247,20 @@ define amdgpu_kernel void @test_call_external_void_func_v3f64_imm() #0 {
 ; GFX11-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 2.0
 ; GFX11-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0x40100000
 ; GFX11-NEXT:    v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0x40200000
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v3f64@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v3f64@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v3f64@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v3f64@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v3f64_imm:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s9
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s7
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    v_mov_b32_e32 v0, 0
 ; HSA-NEXT:    v_mov_b32_e32 v1, 2.0
 ; HSA-NEXT:    v_mov_b32_e32 v2, 0
@@ -2384,10 +2268,11 @@ define amdgpu_kernel void @test_call_external_void_func_v3f64_imm() #0 {
 ; HSA-NEXT:    v_mov_b32_e32 v4, 0
 ; HSA-NEXT:    v_mov_b32_e32 v5, 0x40200000
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v3f64@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v3f64@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v3f64@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v3f64@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   call void @external_void_func_v3f64(<3 x double> <double 2.0, double 4.0, double 8.0>)
   ret void
@@ -2396,16 +2281,15 @@ define amdgpu_kernel void @test_call_external_void_func_v3f64_imm() #0 {
 define amdgpu_kernel void @test_call_external_void_func_v2i16() #0 {
 ; VI-LABEL: test_call_external_void_func_v2i16:
 ; VI:       ; %bb.0:
+; VI-NEXT:    s_mov_b32 s3, 0xf000
+; VI-NEXT:    s_mov_b32 s2, -1
+; VI-NEXT:    buffer_load_dword v0, off, s[0:3], 0
 ; VI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
-; VI-NEXT:    s_mov_b32 s3, 0xf000
-; VI-NEXT:    s_mov_b32 s2, -1
-; VI-NEXT:    buffer_load_dword v0, off, s[0:3], 0
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    s_mov_b32 s32, 0
@@ -2417,16 +2301,15 @@ define amdgpu_kernel void @test_call_external_void_func_v2i16() #0 {
 ;
 ; CI-LABEL: test_call_external_void_func_v2i16:
 ; CI:       ; %bb.0:
+; CI-NEXT:    s_mov_b32 s3, 0xf000
+; CI-NEXT:    s_mov_b32 s2, -1
+; CI-NEXT:    buffer_load_dword v0, off, s[0:3], 0
 ; CI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
-; CI-NEXT:    s_mov_b32 s3, 0xf000
-; CI-NEXT:    s_mov_b32 s2, -1
-; CI-NEXT:    buffer_load_dword v0, off, s[0:3], 0
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    s_mov_b32 s32, 0
@@ -2440,16 +2323,15 @@ define amdgpu_kernel void @test_call_external_void_func_v2i16() #0 {
 ;
 ; GFX9-LABEL: test_call_external_void_func_v2i16:
 ; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_mov_b32 s3, 0xf000
+; GFX9-NEXT:    s_mov_b32 s2, -1
+; GFX9-NEXT:    buffer_load_dword v0, off, s[0:3], 0
 ; GFX9-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
-; GFX9-NEXT:    s_mov_b32 s3, 0xf000
-; GFX9-NEXT:    s_mov_b32 s2, -1
-; GFX9-NEXT:    buffer_load_dword v0, off, s[0:3], 0
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
@@ -2463,32 +2345,30 @@ define amdgpu_kernel void @test_call_external_void_func_v2i16() #0 {
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; GFX11-NEXT:    buffer_load_b32 v0, off, s[0:3], 0
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v2i16@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v2i16@rel32@hi+12
+; GFX11-NEXT:    buffer_load_b32 v0, off, s[0:3], 0
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v2i16@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v2i16@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v2i16:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s7
 ; HSA-NEXT:    s_mov_b32 s7, 0x1100f000
 ; HSA-NEXT:    s_mov_b32 s6, -1
 ; HSA-NEXT:    buffer_load_dword v0, off, s[4:7], 0
-; HSA-NEXT:    s_add_u32 s0, s0, s9
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v2i16@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v2i16@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v2i16@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v2i16@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   %val = load <2 x i16>, ptr addrspace(1) undef
   call void @external_void_func_v2i16(<2 x i16> %val)
@@ -2498,16 +2378,15 @@ define amdgpu_kernel void @test_call_external_void_func_v2i16() #0 {
 define amdgpu_kernel void @test_call_external_void_func_v3i16() #0 {
 ; VI-LABEL: test_call_external_void_func_v3i16:
 ; VI:       ; %bb.0:
+; VI-NEXT:    s_mov_b32 s3, 0xf000
+; VI-NEXT:    s_mov_b32 s2, -1
+; VI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
 ; VI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
-; VI-NEXT:    s_mov_b32 s3, 0xf000
-; VI-NEXT:    s_mov_b32 s2, -1
-; VI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    s_mov_b32 s32, 0
@@ -2519,16 +2398,15 @@ define amdgpu_kernel void @test_call_external_void_func_v3i16() #0 {
 ;
 ; CI-LABEL: test_call_external_void_func_v3i16:
 ; CI:       ; %bb.0:
+; CI-NEXT:    s_mov_b32 s3, 0xf000
+; CI-NEXT:    s_mov_b32 s2, -1
+; CI-NEXT:    buffer_load_dwordx2 v[2:3], off, s[0:3], 0
 ; CI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
-; CI-NEXT:    s_mov_b32 s3, 0xf000
-; CI-NEXT:    s_mov_b32 s2, -1
-; CI-NEXT:    buffer_load_dwordx2 v[2:3], off, s[0:3], 0
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    s_mov_b32 s32, 0
@@ -2544,16 +2422,15 @@ define amdgpu_kernel void @test_call_external_void_func_v3i16() #0 {
 ;
 ; GFX9-LABEL: test_call_external_void_func_v3i16:
 ; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_mov_b32 s3, 0xf000
+; GFX9-NEXT:    s_mov_b32 s2, -1
+; GFX9-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX9-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
-; GFX9-NEXT:    s_mov_b32 s3, 0xf000
-; GFX9-NEXT:    s_mov_b32 s2, -1
-; GFX9-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
@@ -2567,32 +2444,30 @@ define amdgpu_kernel void @test_call_external_void_func_v3i16() #0 {
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; GFX11-NEXT:    buffer_load_b64 v[0:1], off, s[0:3], 0
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v3i16@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v3i16@rel32@hi+12
+; GFX11-NEXT:    buffer_load_b64 v[0:1], off, s[0:3], 0
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v3i16@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v3i16@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v3i16:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s7
 ; HSA-NEXT:    s_mov_b32 s7, 0x1100f000
 ; HSA-NEXT:    s_mov_b32 s6, -1
 ; HSA-NEXT:    buffer_load_dwordx2 v[0:1], off, s[4:7], 0
-; HSA-NEXT:    s_add_u32 s0, s0, s9
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v3i16@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v3i16@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v3i16@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v3i16@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   %val = load <3 x i16>, ptr addrspace(1) undef
   call void @external_void_func_v3i16(<3 x i16> %val)
@@ -2602,16 +2477,15 @@ define amdgpu_kernel void @test_call_external_void_func_v3i16() #0 {
 define amdgpu_kernel void @test_call_external_void_func_v3f16() #0 {
 ; VI-LABEL: test_call_external_void_func_v3f16:
 ; VI:       ; %bb.0:
+; VI-NEXT:    s_mov_b32 s3, 0xf000
+; VI-NEXT:    s_mov_b32 s2, -1
+; VI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
 ; VI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
-; VI-NEXT:    s_mov_b32 s3, 0xf000
-; VI-NEXT:    s_mov_b32 s2, -1
-; VI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    s_mov_b32 s32, 0
@@ -2623,16 +2497,15 @@ define amdgpu_kernel void @test_call_external_void_func_v3f16() #0 {
 ;
 ; CI-LABEL: test_call_external_void_func_v3f16:
 ; CI:       ; %bb.0:
+; CI-NEXT:    s_mov_b32 s3, 0xf000
+; CI-NEXT:    s_mov_b32 s2, -1
+; CI-NEXT:    buffer_load_dwordx2 v[1:2], off, s[0:3], 0
 ; CI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
-; CI-NEXT:    s_mov_b32 s3, 0xf000
-; CI-NEXT:    s_mov_b32 s2, -1
-; CI-NEXT:    buffer_load_dwordx2 v[1:2], off, s[0:3], 0
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    s_mov_b32 s32, 0
@@ -2642,23 +2515,22 @@ define amdgpu_kernel void @test_call_external_void_func_v3f16() #0 {
 ; CI-NEXT:    s_waitcnt vmcnt(0)
 ; CI-NEXT:    v_cvt_f32_f16_e32 v0, v1
 ; CI-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; CI-NEXT:    v_cvt_f32_f16_e32 v2, v2
 ; CI-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; CI-NEXT:    v_cvt_f32_f16_e32 v2, v2
 ; CI-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; CI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: test_call_external_void_func_v3f16:
 ; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_mov_b32 s3, 0xf000
+; GFX9-NEXT:    s_mov_b32 s2, -1
+; GFX9-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX9-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
-; GFX9-NEXT:    s_mov_b32 s3, 0xf000
-; GFX9-NEXT:    s_mov_b32 s2, -1
-; GFX9-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
@@ -2672,32 +2544,30 @@ define amdgpu_kernel void @test_call_external_void_func_v3f16() #0 {
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; GFX11-NEXT:    buffer_load_b64 v[0:1], off, s[0:3], 0
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v3f16@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v3f16@rel32@hi+12
+; GFX11-NEXT:    buffer_load_b64 v[0:1], off, s[0:3], 0
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v3f16@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v3f16@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v3f16:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s7
 ; HSA-NEXT:    s_mov_b32 s7, 0x1100f000
 ; HSA-NEXT:    s_mov_b32 s6, -1
 ; HSA-NEXT:    buffer_load_dwordx2 v[0:1], off, s[4:7], 0
-; HSA-NEXT:    s_add_u32 s0, s0, s9
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v3f16@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v3f16@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v3f16@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v3f16@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   %val = load <3 x half>, ptr addrspace(1) undef
   call void @external_void_func_v3f16(<3 x half> %val)
@@ -2711,9 +2581,8 @@ define amdgpu_kernel void @test_call_external_void_func_v3i16_imm() #0 {
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    v_mov_b32_e32 v0, 0x20001
@@ -2731,9 +2600,8 @@ define amdgpu_kernel void @test_call_external_void_func_v3i16_imm() #0 {
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    v_mov_b32_e32 v0, 1
@@ -2752,9 +2620,8 @@ define amdgpu_kernel void @test_call_external_void_func_v3i16_imm() #0 {
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0x20001
@@ -2769,30 +2636,28 @@ define amdgpu_kernel void @test_call_external_void_func_v3i16_imm() #0 {
 ; GFX11-LABEL: test_call_external_void_func_v3i16_imm:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    v_dual_mov_b32 v0, 0x20001 :: v_dual_mov_b32 v1, 3
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v3i16@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v3i16@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v3i16@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v3i16@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v3i16_imm:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s9
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s7
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    v_mov_b32_e32 v0, 0x20001
 ; HSA-NEXT:    v_mov_b32_e32 v1, 3
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v3i16@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v3i16@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v3i16@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v3i16@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   call void @external_void_func_v3i16(<3 x i16> <i16 1, i16 2, i16 3>)
   ret void
@@ -2805,9 +2670,8 @@ define amdgpu_kernel void @test_call_external_void_func_v3f16_imm() #0 {
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    v_mov_b32_e32 v0, 0x40003c00
@@ -2825,9 +2689,8 @@ define amdgpu_kernel void @test_call_external_void_func_v3f16_imm() #0 {
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    v_mov_b32_e32 v0, 1.0
@@ -2846,9 +2709,8 @@ define amdgpu_kernel void @test_call_external_void_func_v3f16_imm() #0 {
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0x40003c00
@@ -2864,30 +2726,28 @@ define amdgpu_kernel void @test_call_external_void_func_v3f16_imm() #0 {
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    v_mov_b32_e32 v0, 0x40003c00
 ; GFX11-NEXT:    v_mov_b32_e32 v1, 0x4400
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v3f16@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v3f16@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v3f16@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v3f16@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v3f16_imm:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s9
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s7
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    v_mov_b32_e32 v0, 0x40003c00
 ; HSA-NEXT:    v_mov_b32_e32 v1, 0x4400
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v3f16@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v3f16@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v3f16@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v3f16@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   call void @external_void_func_v3f16(<3 x half> <half 1.0, half 2.0, half 4.0>)
   ret void
@@ -2896,16 +2756,15 @@ define amdgpu_kernel void @test_call_external_void_func_v3f16_imm() #0 {
 define amdgpu_kernel void @test_call_external_void_func_v4i16() #0 {
 ; VI-LABEL: test_call_external_void_func_v4i16:
 ; VI:       ; %bb.0:
+; VI-NEXT:    s_mov_b32 s3, 0xf000
+; VI-NEXT:    s_mov_b32 s2, -1
+; VI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
 ; VI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
-; VI-NEXT:    s_mov_b32 s3, 0xf000
-; VI-NEXT:    s_mov_b32 s2, -1
-; VI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    s_mov_b32 s32, 0
@@ -2917,16 +2776,15 @@ define amdgpu_kernel void @test_call_external_void_func_v4i16() #0 {
 ;
 ; CI-LABEL: test_call_external_void_func_v4i16:
 ; CI:       ; %bb.0:
+; CI-NEXT:    s_mov_b32 s3, 0xf000
+; CI-NEXT:    s_mov_b32 s2, -1
+; CI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
 ; CI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
-; CI-NEXT:    s_mov_b32 s3, 0xf000
-; CI-NEXT:    s_mov_b32 s2, -1
-; CI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    s_mov_b32 s32, 0
@@ -2943,16 +2801,15 @@ define amdgpu_kernel void @test_call_external_void_func_v4i16() #0 {
 ;
 ; GFX9-LABEL: test_call_external_void_func_v4i16:
 ; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_mov_b32 s3, 0xf000
+; GFX9-NEXT:    s_mov_b32 s2, -1
+; GFX9-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX9-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
-; GFX9-NEXT:    s_mov_b32 s3, 0xf000
-; GFX9-NEXT:    s_mov_b32 s2, -1
-; GFX9-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
@@ -2966,32 +2823,30 @@ define amdgpu_kernel void @test_call_external_void_func_v4i16() #0 {
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; GFX11-NEXT:    buffer_load_b64 v[0:1], off, s[0:3], 0
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v4i16@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v4i16@rel32@hi+12
+; GFX11-NEXT:    buffer_load_b64 v[0:1], off, s[0:3], 0
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v4i16@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v4i16@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v4i16:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s7
 ; HSA-NEXT:    s_mov_b32 s7, 0x1100f000
 ; HSA-NEXT:    s_mov_b32 s6, -1
 ; HSA-NEXT:    buffer_load_dwordx2 v[0:1], off, s[4:7], 0
-; HSA-NEXT:    s_add_u32 s0, s0, s9
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v4i16@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v4i16@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v4i16@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v4i16@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   %val = load <4 x i16>, ptr addrspace(1) undef
   call void @external_void_func_v4i16(<4 x i16> %val)
@@ -3005,9 +2860,8 @@ define amdgpu_kernel void @test_call_external_void_func_v4i16_imm() #0 {
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    v_mov_b32_e32 v0, 0x20001
@@ -3025,9 +2879,8 @@ define amdgpu_kernel void @test_call_external_void_func_v4i16_imm() #0 {
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    v_mov_b32_e32 v0, 1
@@ -3047,9 +2900,8 @@ define amdgpu_kernel void @test_call_external_void_func_v4i16_imm() #0 {
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0x20001
@@ -3065,30 +2917,28 @@ define amdgpu_kernel void @test_call_external_void_func_v4i16_imm() #0 {
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    v_mov_b32_e32 v0, 0x20001
 ; GFX11-NEXT:    v_mov_b32_e32 v1, 0x40003
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v4i16@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v4i16@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v4i16@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v4i16@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v4i16_imm:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s9
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s7
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    v_mov_b32_e32 v0, 0x20001
 ; HSA-NEXT:    v_mov_b32_e32 v1, 0x40003
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v4i16@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v4i16@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v4i16@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v4i16@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   call void @external_void_func_v4i16(<4 x i16> <i16 1, i16 2, i16 3, i16 4>)
   ret void
@@ -3097,16 +2947,15 @@ define amdgpu_kernel void @test_call_external_void_func_v4i16_imm() #0 {
 define amdgpu_kernel void @test_call_external_void_func_v2f16() #0 {
 ; VI-LABEL: test_call_external_void_func_v2f16:
 ; VI:       ; %bb.0:
+; VI-NEXT:    s_mov_b32 s3, 0xf000
+; VI-NEXT:    s_mov_b32 s2, -1
+; VI-NEXT:    buffer_load_dword v0, off, s[0:3], 0
 ; VI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
-; VI-NEXT:    s_mov_b32 s3, 0xf000
-; VI-NEXT:    s_mov_b32 s2, -1
-; VI-NEXT:    buffer_load_dword v0, off, s[0:3], 0
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    s_mov_b32 s32, 0
@@ -3118,16 +2967,15 @@ define amdgpu_kernel void @test_call_external_void_func_v2f16() #0 {
 ;
 ; CI-LABEL: test_call_external_void_func_v2f16:
 ; CI:       ; %bb.0:
+; CI-NEXT:    s_mov_b32 s3, 0xf000
+; CI-NEXT:    s_mov_b32 s2, -1
+; CI-NEXT:    buffer_load_dword v1, off, s[0:3], 0
 ; CI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
-; CI-NEXT:    s_mov_b32 s3, 0xf000
-; CI-NEXT:    s_mov_b32 s2, -1
-; CI-NEXT:    buffer_load_dword v1, off, s[0:3], 0
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    s_mov_b32 s32, 0
@@ -3143,16 +2991,15 @@ define amdgpu_kernel void @test_call_external_void_func_v2f16() #0 {
 ;
 ; GFX9-LABEL: test_call_external_void_func_v2f16:
 ; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_mov_b32 s3, 0xf000
+; GFX9-NEXT:    s_mov_b32 s2, -1
+; GFX9-NEXT:    buffer_load_dword v0, off, s[0:3], 0
 ; GFX9-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
-; GFX9-NEXT:    s_mov_b32 s3, 0xf000
-; GFX9-NEXT:    s_mov_b32 s2, -1
-; GFX9-NEXT:    buffer_load_dword v0, off, s[0:3], 0
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
@@ -3166,32 +3013,30 @@ define amdgpu_kernel void @test_call_external_void_func_v2f16() #0 {
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; GFX11-NEXT:    buffer_load_b32 v0, off, s[0:3], 0
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v2f16@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v2f16@rel32@hi+12
+; GFX11-NEXT:    buffer_load_b32 v0, off, s[0:3], 0
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v2f16@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v2f16@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v2f16:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s7
 ; HSA-NEXT:    s_mov_b32 s7, 0x1100f000
 ; HSA-NEXT:    s_mov_b32 s6, -1
 ; HSA-NEXT:    buffer_load_dword v0, off, s[4:7], 0
-; HSA-NEXT:    s_add_u32 s0, s0, s9
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v2f16@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v2f16@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v2f16@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v2f16@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   %val = load <2 x half>, ptr addrspace(1) undef
   call void @external_void_func_v2f16(<2 x half> %val)
@@ -3201,16 +3046,15 @@ define amdgpu_kernel void @test_call_external_void_func_v2f16() #0 {
 define amdgpu_kernel void @test_call_external_void_func_v2i32() #0 {
 ; VI-LABEL: test_call_external_void_func_v2i32:
 ; VI:       ; %bb.0:
+; VI-NEXT:    s_mov_b32 s3, 0xf000
+; VI-NEXT:    s_mov_b32 s2, -1
+; VI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
 ; VI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
-; VI-NEXT:    s_mov_b32 s3, 0xf000
-; VI-NEXT:    s_mov_b32 s2, -1
-; VI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    s_mov_b32 s32, 0
@@ -3222,16 +3066,15 @@ define amdgpu_kernel void @test_call_external_void_func_v2i32() #0 {
 ;
 ; CI-LABEL: test_call_external_void_func_v2i32:
 ; CI:       ; %bb.0:
+; CI-NEXT:    s_mov_b32 s3, 0xf000
+; CI-NEXT:    s_mov_b32 s2, -1
+; CI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
 ; CI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
-; CI-NEXT:    s_mov_b32 s3, 0xf000
-; CI-NEXT:    s_mov_b32 s2, -1
-; CI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    s_mov_b32 s32, 0
@@ -3243,16 +3086,15 @@ define amdgpu_kernel void @test_call_external_void_func_v2i32() #0 {
 ;
 ; GFX9-LABEL: test_call_external_void_func_v2i32:
 ; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_mov_b32 s3, 0xf000
+; GFX9-NEXT:    s_mov_b32 s2, -1
+; GFX9-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX9-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
-; GFX9-NEXT:    s_mov_b32 s3, 0xf000
-; GFX9-NEXT:    s_mov_b32 s2, -1
-; GFX9-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
@@ -3266,32 +3108,30 @@ define amdgpu_kernel void @test_call_external_void_func_v2i32() #0 {
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; GFX11-NEXT:    buffer_load_b64 v[0:1], off, s[0:3], 0
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v2i32@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v2i32@rel32@hi+12
+; GFX11-NEXT:    buffer_load_b64 v[0:1], off, s[0:3], 0
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v2i32@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v2i32@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v2i32:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s7
 ; HSA-NEXT:    s_mov_b32 s7, 0x1100f000
 ; HSA-NEXT:    s_mov_b32 s6, -1
 ; HSA-NEXT:    buffer_load_dwordx2 v[0:1], off, s[4:7], 0
-; HSA-NEXT:    s_add_u32 s0, s0, s9
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v2i32@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v2i32@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v2i32@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v2i32@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   %val = load <2 x i32>, ptr addrspace(1) undef
   call void @external_void_func_v2i32(<2 x i32> %val)
@@ -3305,9 +3145,8 @@ define amdgpu_kernel void @test_call_external_void_func_v2i32_imm() #0 {
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    v_mov_b32_e32 v0, 1
@@ -3325,9 +3164,8 @@ define amdgpu_kernel void @test_call_external_void_func_v2i32_imm() #0 {
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    v_mov_b32_e32 v0, 1
@@ -3345,9 +3183,8 @@ define amdgpu_kernel void @test_call_external_void_func_v2i32_imm() #0 {
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 1
@@ -3362,30 +3199,28 @@ define amdgpu_kernel void @test_call_external_void_func_v2i32_imm() #0 {
 ; GFX11-LABEL: test_call_external_void_func_v2i32_imm:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 2
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v2i32@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v2i32@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v2i32@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v2i32@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v2i32_imm:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s9
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s7
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    v_mov_b32_e32 v0, 1
 ; HSA-NEXT:    v_mov_b32_e32 v1, 2
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v2i32@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v2i32@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v2i32@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v2i32@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   call void @external_void_func_v2i32(<2 x i32> <i32 1, i32 2>)
   ret void
@@ -3398,9 +3233,8 @@ define amdgpu_kernel void @test_call_external_void_func_v3i32_imm(i32) #0 {
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s5
+; VI-NEXT:    s_add_u32 s36, s36, s3
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    v_mov_b32_e32 v0, 3
@@ -3419,9 +3253,8 @@ define amdgpu_kernel void @test_call_external_void_func_v3i32_imm(i32) #0 {
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s5
+; CI-NEXT:    s_add_u32 s36, s36, s3
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    v_mov_b32_e32 v0, 3
@@ -3440,9 +3273,8 @@ define amdgpu_kernel void @test_call_external_void_func_v3i32_imm(i32) #0 {
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s5
+; GFX9-NEXT:    s_add_u32 s36, s36, s3
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 3
@@ -3459,31 +3291,29 @@ define amdgpu_kernel void @test_call_external_void_func_v3i32_imm(i32) #0 {
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v1, 4
 ; GFX11-NEXT:    v_mov_b32_e32 v2, 5
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v3i32@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v3i32@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v3i32@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v3i32@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v3i32_imm:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s8, s8, s11
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s8, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s11
+; HSA-NEXT:    s_add_i32 s6, s6, s9
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s9
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    v_mov_b32_e32 v0, 3
 ; HSA-NEXT:    v_mov_b32_e32 v1, 4
 ; HSA-NEXT:    v_mov_b32_e32 v2, 5
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s9
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v3i32@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v3i32@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v3i32@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v3i32@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   call void @external_void_func_v3i32(<3 x i32> <i32 3, i32 4, i32 5>)
   ret void
@@ -3496,9 +3326,8 @@ define amdgpu_kernel void @test_call_external_void_func_v3i32_i32(i32) #0 {
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s5
+; VI-NEXT:    s_add_u32 s36, s36, s3
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    v_mov_b32_e32 v0, 3
@@ -3518,9 +3347,8 @@ define amdgpu_kernel void @test_call_external_void_func_v3i32_i32(i32) #0 {
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s5
+; CI-NEXT:    s_add_u32 s36, s36, s3
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    v_mov_b32_e32 v0, 3
@@ -3540,9 +3368,8 @@ define amdgpu_kernel void @test_call_external_void_func_v3i32_i32(i32) #0 {
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s5
+; GFX9-NEXT:    s_add_u32 s36, s36, s3
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 3
@@ -3560,32 +3387,30 @@ define amdgpu_kernel void @test_call_external_void_func_v3i32_i32(i32) #0 {
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v1, 4
 ; GFX11-NEXT:    v_dual_mov_b32 v2, 5 :: v_dual_mov_b32 v3, 6
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v3i32_i32@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v3i32_i32@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v3i32_i32@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v3i32_i32@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v3i32_i32:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s8, s8, s11
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s8, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s11
+; HSA-NEXT:    s_add_i32 s6, s6, s9
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s9
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    v_mov_b32_e32 v0, 3
 ; HSA-NEXT:    v_mov_b32_e32 v1, 4
 ; HSA-NEXT:    v_mov_b32_e32 v2, 5
 ; HSA-NEXT:    v_mov_b32_e32 v3, 6
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s9
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v3i32_i32@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v3i32_i32@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v3i32_i32@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v3i32_i32@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   call void @external_void_func_v3i32_i32(<3 x i32> <i32 3, i32 4, i32 5>, i32 6)
   ret void
@@ -3594,16 +3419,15 @@ define amdgpu_kernel void @test_call_external_void_func_v3i32_i32(i32) #0 {
 define amdgpu_kernel void @test_call_external_void_func_v4i32() #0 {
 ; VI-LABEL: test_call_external_void_func_v4i32:
 ; VI:       ; %bb.0:
+; VI-NEXT:    s_mov_b32 s3, 0xf000
+; VI-NEXT:    s_mov_b32 s2, -1
+; VI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0
 ; VI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
-; VI-NEXT:    s_mov_b32 s3, 0xf000
-; VI-NEXT:    s_mov_b32 s2, -1
-; VI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    s_mov_b32 s32, 0
@@ -3615,16 +3439,15 @@ define amdgpu_kernel void @test_call_external_void_func_v4i32() #0 {
 ;
 ; CI-LABEL: test_call_external_void_func_v4i32:
 ; CI:       ; %bb.0:
+; CI-NEXT:    s_mov_b32 s3, 0xf000
+; CI-NEXT:    s_mov_b32 s2, -1
+; CI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0
 ; CI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
-; CI-NEXT:    s_mov_b32 s3, 0xf000
-; CI-NEXT:    s_mov_b32 s2, -1
-; CI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    s_mov_b32 s32, 0
@@ -3636,16 +3459,15 @@ define amdgpu_kernel void @test_call_external_void_func_v4i32() #0 {
 ;
 ; GFX9-LABEL: test_call_external_void_func_v4i32:
 ; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_mov_b32 s3, 0xf000
+; GFX9-NEXT:    s_mov_b32 s2, -1
+; GFX9-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0
 ; GFX9-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
-; GFX9-NEXT:    s_mov_b32 s3, 0xf000
-; GFX9-NEXT:    s_mov_b32 s2, -1
-; GFX9-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
@@ -3659,32 +3481,30 @@ define amdgpu_kernel void @test_call_external_void_func_v4i32() #0 {
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; GFX11-NEXT:    buffer_load_b128 v[0:3], off, s[0:3], 0
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v4i32@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v4i32@rel32@hi+12
+; GFX11-NEXT:    buffer_load_b128 v[0:3], off, s[0:3], 0
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v4i32@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v4i32@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v4i32:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s7
 ; HSA-NEXT:    s_mov_b32 s7, 0x1100f000
 ; HSA-NEXT:    s_mov_b32 s6, -1
 ; HSA-NEXT:    buffer_load_dwordx4 v[0:3], off, s[4:7], 0
-; HSA-NEXT:    s_add_u32 s0, s0, s9
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v4i32@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v4i32@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v4i32@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v4i32@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   %val = load <4 x i32>, ptr addrspace(1) undef
   call void @external_void_func_v4i32(<4 x i32> %val)
@@ -3698,9 +3518,8 @@ define amdgpu_kernel void @test_call_external_void_func_v4i32_imm() #0 {
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    v_mov_b32_e32 v0, 1
@@ -3720,9 +3539,8 @@ define amdgpu_kernel void @test_call_external_void_func_v4i32_imm() #0 {
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    v_mov_b32_e32 v0, 1
@@ -3742,9 +3560,8 @@ define amdgpu_kernel void @test_call_external_void_func_v4i32_imm() #0 {
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 1
@@ -3762,32 +3579,30 @@ define amdgpu_kernel void @test_call_external_void_func_v4i32_imm() #0 {
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 2
 ; GFX11-NEXT:    v_dual_mov_b32 v2, 3 :: v_dual_mov_b32 v3, 4
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v4i32@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v4i32@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v4i32@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v4i32@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v4i32_imm:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s9
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s7
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    v_mov_b32_e32 v0, 1
 ; HSA-NEXT:    v_mov_b32_e32 v1, 2
 ; HSA-NEXT:    v_mov_b32_e32 v2, 3
 ; HSA-NEXT:    v_mov_b32_e32 v3, 4
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v4i32@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v4i32@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v4i32@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v4i32@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   call void @external_void_func_v4i32(<4 x i32> <i32 1, i32 2, i32 3, i32 4>)
   ret void
@@ -3800,9 +3615,8 @@ define amdgpu_kernel void @test_call_external_void_func_v5i32_imm() #0 {
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    v_mov_b32_e32 v0, 1
@@ -3823,9 +3637,8 @@ define amdgpu_kernel void @test_call_external_void_func_v5i32_imm() #0 {
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    v_mov_b32_e32 v0, 1
@@ -3846,9 +3659,8 @@ define amdgpu_kernel void @test_call_external_void_func_v5i32_imm() #0 {
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 1
@@ -3868,33 +3680,31 @@ define amdgpu_kernel void @test_call_external_void_func_v5i32_imm() #0 {
 ; GFX11-NEXT:    v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 2
 ; GFX11-NEXT:    v_dual_mov_b32 v2, 3 :: v_dual_mov_b32 v3, 4
 ; GFX11-NEXT:    v_mov_b32_e32 v4, 5
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v5i32@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v5i32@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v5i32@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v5i32@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v5i32_imm:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s9
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s7
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    v_mov_b32_e32 v0, 1
 ; HSA-NEXT:    v_mov_b32_e32 v1, 2
 ; HSA-NEXT:    v_mov_b32_e32 v2, 3
 ; HSA-NEXT:    v_mov_b32_e32 v3, 4
 ; HSA-NEXT:    v_mov_b32_e32 v4, 5
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v5i32@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v5i32@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v5i32@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v5i32@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   call void @external_void_func_v5i32(<5 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5>)
   ret void
@@ -3904,18 +3714,17 @@ define amdgpu_kernel void @test_call_external_void_func_v8i32() #0 {
 ; VI-LABEL: test_call_external_void_func_v8i32:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_add_u32 s36, s36, s1
+; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; VI-NEXT:    s_mov_b32 s3, 0xf000
 ; VI-NEXT:    s_mov_b32 s2, -1
+; VI-NEXT:    s_addc_u32 s37, s37, 0
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0
 ; VI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[0:3], 0 offset:16
-; VI-NEXT:    s_addc_u32 s37, s37, 0
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    s_mov_b32 s32, 0
@@ -3928,18 +3737,17 @@ define amdgpu_kernel void @test_call_external_void_func_v8i32() #0 {
 ; CI-LABEL: test_call_external_void_func_v8i32:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_add_u32 s36, s36, s1
+; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; CI-NEXT:    s_mov_b32 s3, 0xf000
 ; CI-NEXT:    s_mov_b32 s2, -1
+; CI-NEXT:    s_addc_u32 s37, s37, 0
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0
 ; CI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[0:3], 0 offset:16
-; CI-NEXT:    s_addc_u32 s37, s37, 0
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    s_mov_b32 s32, 0
@@ -3952,18 +3760,17 @@ define amdgpu_kernel void @test_call_external_void_func_v8i32() #0 {
 ; GFX9-LABEL: test_call_external_void_func_v8i32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; GFX9-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX9-NEXT:    s_mov_b32 s2, -1
+; GFX9-NEXT:    s_addc_u32 s37, s37, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0
 ; GFX9-NEXT:    buffer_load_dwordx4 v[4:7], off, s[0:3], 0 offset:16
-; GFX9-NEXT:    s_addc_u32 s37, s37, 0
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
@@ -3975,40 +3782,39 @@ define amdgpu_kernel void @test_call_external_void_func_v8i32() #0 {
 ;
 ; GFX11-LABEL: test_call_external_void_func_v8i32:
 ; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[4:5], s[0:1], 0x0
-; GFX11-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX11-NEXT:    s_mov_b32 s6, -1
+; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x0
+; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-NEXT:    s_mov_b32 s2, -1
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v8i32@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v8i32@rel32@hi+12
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    buffer_load_b128 v[0:3], off, s[4:7], 0
-; GFX11-NEXT:    buffer_load_b128 v[4:7], off, s[4:7], 0 offset:16
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    buffer_load_b128 v[0:3], off, s[0:3], 0
+; GFX11-NEXT:    buffer_load_b128 v[4:7], off, s[0:3], 0 offset:16
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v8i32@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v8i32@rel32@hi+12
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v8i32:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s9
-; HSA-NEXT:    s_load_dwordx2 s[8:9], s[4:5], 0x0
-; HSA-NEXT:    s_mov_b32 s11, 0x1100f000
-; HSA-NEXT:    s_mov_b32 s10, -1
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x0
+; HSA-NEXT:    s_add_u32 s0, s0, s7
+; HSA-NEXT:    s_mov_b32 s7, 0x1100f000
+; HSA-NEXT:    s_mov_b32 s6, -1
 ; HSA-NEXT:    s_waitcnt lgkmcnt(0)
-; HSA-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; HSA-NEXT:    buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
+; HSA-NEXT:    buffer_load_dwordx4 v[0:3], off, s[4:7], 0
+; HSA-NEXT:    buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:16
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v8i32@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v8i32@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v8i32@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v8i32@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   %ptr = load ptr addrspace(1), ptr addrspace(4) undef
   %val = load <8 x i32>, ptr addrspace(1) %ptr
@@ -4023,9 +3829,8 @@ define amdgpu_kernel void @test_call_external_void_func_v8i32_imm() #0 {
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    v_mov_b32_e32 v0, 1
@@ -4049,9 +3854,8 @@ define amdgpu_kernel void @test_call_external_void_func_v8i32_imm() #0 {
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    v_mov_b32_e32 v0, 1
@@ -4075,9 +3879,8 @@ define amdgpu_kernel void @test_call_external_void_func_v8i32_imm() #0 {
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 1
@@ -4101,23 +3904,20 @@ define amdgpu_kernel void @test_call_external_void_func_v8i32_imm() #0 {
 ; GFX11-NEXT:    v_dual_mov_b32 v2, 3 :: v_dual_mov_b32 v3, 4
 ; GFX11-NEXT:    v_dual_mov_b32 v4, 5 :: v_dual_mov_b32 v5, 6
 ; GFX11-NEXT:    v_dual_mov_b32 v6, 7 :: v_dual_mov_b32 v7, 8
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v8i32@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v8i32@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v8i32@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v8i32@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v8i32_imm:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s9
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s7
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    v_mov_b32_e32 v0, 1
 ; HSA-NEXT:    v_mov_b32_e32 v1, 2
 ; HSA-NEXT:    v_mov_b32_e32 v2, 3
@@ -4127,10 +3927,11 @@ define amdgpu_kernel void @test_call_external_void_func_v8i32_imm() #0 {
 ; HSA-NEXT:    v_mov_b32_e32 v6, 7
 ; HSA-NEXT:    v_mov_b32_e32 v7, 8
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v8i32@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v8i32@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v8i32@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v8i32@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   call void @external_void_func_v8i32(<8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>)
   ret void
@@ -4140,20 +3941,19 @@ define amdgpu_kernel void @test_call_external_void_func_v16i32() #0 {
 ; VI-LABEL: test_call_external_void_func_v16i32:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_add_u32 s36, s36, s1
+; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; VI-NEXT:    s_mov_b32 s3, 0xf000
 ; VI-NEXT:    s_mov_b32 s2, -1
+; VI-NEXT:    s_addc_u32 s37, s37, 0
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0
 ; VI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[0:3], 0 offset:16
 ; VI-NEXT:    buffer_load_dwordx4 v[8:11], off, s[0:3], 0 offset:32
 ; VI-NEXT:    buffer_load_dwordx4 v[12:15], off, s[0:3], 0 offset:48
-; VI-NEXT:    s_addc_u32 s37, s37, 0
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    s_mov_b32 s32, 0
@@ -4166,20 +3966,19 @@ define amdgpu_kernel void @test_call_external_void_func_v16i32() #0 {
 ; CI-LABEL: test_call_external_void_func_v16i32:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_add_u32 s36, s36, s1
+; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; CI-NEXT:    s_mov_b32 s3, 0xf000
 ; CI-NEXT:    s_mov_b32 s2, -1
+; CI-NEXT:    s_addc_u32 s37, s37, 0
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0
 ; CI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[0:3], 0 offset:16
 ; CI-NEXT:    buffer_load_dwordx4 v[8:11], off, s[0:3], 0 offset:32
 ; CI-NEXT:    buffer_load_dwordx4 v[12:15], off, s[0:3], 0 offset:48
-; CI-NEXT:    s_addc_u32 s37, s37, 0
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    s_mov_b32 s32, 0
@@ -4192,20 +3991,19 @@ define amdgpu_kernel void @test_call_external_void_func_v16i32() #0 {
 ; GFX9-LABEL: test_call_external_void_func_v16i32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; GFX9-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX9-NEXT:    s_mov_b32 s2, -1
+; GFX9-NEXT:    s_addc_u32 s37, s37, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0
 ; GFX9-NEXT:    buffer_load_dwordx4 v[4:7], off, s[0:3], 0 offset:16
 ; GFX9-NEXT:    buffer_load_dwordx4 v[8:11], off, s[0:3], 0 offset:32
 ; GFX9-NEXT:    buffer_load_dwordx4 v[12:15], off, s[0:3], 0 offset:48
-; GFX9-NEXT:    s_addc_u32 s37, s37, 0
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
@@ -4217,44 +4015,43 @@ define amdgpu_kernel void @test_call_external_void_func_v16i32() #0 {
 ;
 ; GFX11-LABEL: test_call_external_void_func_v16i32:
 ; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[4:5], s[0:1], 0x0
-; GFX11-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX11-NEXT:    s_mov_b32 s6, -1
+; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x0
+; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-NEXT:    s_mov_b32 s2, -1
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v16i32@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v16i32@rel32@hi+12
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11-NEXT:    s_clause 0x3
-; GFX11-NEXT:    buffer_load_b128 v[0:3], off, s[4:7], 0
-; GFX11-NEXT:    buffer_load_b128 v[4:7], off, s[4:7], 0 offset:16
-; GFX11-NEXT:    buffer_load_b128 v[8:11], off, s[4:7], 0 offset:32
-; GFX11-NEXT:    buffer_load_b128 v[12:15], off, s[4:7], 0 offset:48
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    buffer_load_b128 v[0:3], off, s[0:3], 0
+; GFX11-NEXT:    buffer_load_b128 v[4:7], off, s[0:3], 0 offset:16
+; GFX11-NEXT:    buffer_load_b128 v[8:11], off, s[0:3], 0 offset:32
+; GFX11-NEXT:    buffer_load_b128 v[12:15], off, s[0:3], 0 offset:48
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v16i32@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v16i32@rel32@hi+12
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v16i32:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s9
-; HSA-NEXT:    s_load_dwordx2 s[8:9], s[4:5], 0x0
-; HSA-NEXT:    s_mov_b32 s11, 0x1100f000
-; HSA-NEXT:    s_mov_b32 s10, -1
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x0
+; HSA-NEXT:    s_add_u32 s0, s0, s7
+; HSA-NEXT:    s_mov_b32 s7, 0x1100f000
+; HSA-NEXT:    s_mov_b32 s6, -1
 ; HSA-NEXT:    s_waitcnt lgkmcnt(0)
-; HSA-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; HSA-NEXT:    buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
-; HSA-NEXT:    buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:32
-; HSA-NEXT:    buffer_load_dwordx4 v[12:15], off, s[8:11], 0 offset:48
+; HSA-NEXT:    buffer_load_dwordx4 v[0:3], off, s[4:7], 0
+; HSA-NEXT:    buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:16
+; HSA-NEXT:    buffer_load_dwordx4 v[8:11], off, s[4:7], 0 offset:32
+; HSA-NEXT:    buffer_load_dwordx4 v[12:15], off, s[4:7], 0 offset:48
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v16i32@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v16i32@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v16i32@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v16i32@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   %ptr = load ptr addrspace(1), ptr addrspace(4) undef
   %val = load <16 x i32>, ptr addrspace(1) %ptr
@@ -4265,152 +4062,147 @@ define amdgpu_kernel void @test_call_external_void_func_v16i32() #0 {
 define amdgpu_kernel void @test_call_external_void_func_v32i32() #0 {
 ; VI-LABEL: test_call_external_void_func_v32i32:
 ; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x0
-; VI-NEXT:    s_mov_b32 s7, 0xf000
-; VI-NEXT:    s_mov_b32 s6, -1
 ; VI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    buffer_load_dwordx4 v[28:31], off, s[4:7], 0 offset:112
-; VI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[4:7], 0
-; VI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:16
-; VI-NEXT:    buffer_load_dwordx4 v[8:11], off, s[4:7], 0 offset:32
-; VI-NEXT:    buffer_load_dwordx4 v[12:15], off, s[4:7], 0 offset:48
-; VI-NEXT:    buffer_load_dwordx4 v[16:19], off, s[4:7], 0 offset:64
-; VI-NEXT:    buffer_load_dwordx4 v[20:23], off, s[4:7], 0 offset:80
-; VI-NEXT:    buffer_load_dwordx4 v[24:27], off, s[4:7], 0 offset:96
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_add_u32 s36, s36, s1
+; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
+; VI-NEXT:    s_mov_b32 s3, 0xf000
+; VI-NEXT:    s_mov_b32 s2, -1
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT:    s_waitcnt lgkmcnt(0)
+; VI-NEXT:    buffer_load_dwordx4 v[28:31], off, s[0:3], 0 offset:112
+; VI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0
+; VI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; VI-NEXT:    buffer_load_dwordx4 v[8:11], off, s[0:3], 0 offset:32
+; VI-NEXT:    buffer_load_dwordx4 v[12:15], off, s[0:3], 0 offset:48
+; VI-NEXT:    buffer_load_dwordx4 v[16:19], off, s[0:3], 0 offset:64
+; VI-NEXT:    buffer_load_dwordx4 v[20:23], off, s[0:3], 0 offset:80
+; VI-NEXT:    buffer_load_dwordx4 v[24:27], off, s[0:3], 0 offset:96
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b32 s32, 0
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
-; VI-NEXT:    s_getpc_b64 s[8:9]
-; VI-NEXT:    s_add_u32 s8, s8, external_void_func_v32i32@rel32@lo+4
-; VI-NEXT:    s_addc_u32 s9, s9, external_void_func_v32i32@rel32@hi+12
+; VI-NEXT:    s_getpc_b64 s[4:5]
+; VI-NEXT:    s_add_u32 s4, s4, external_void_func_v32i32@rel32@lo+4
+; VI-NEXT:    s_addc_u32 s5, s5, external_void_func_v32i32@rel32@hi+12
 ; VI-NEXT:    s_waitcnt vmcnt(7)
 ; VI-NEXT:    buffer_store_dword v31, off, s[36:39], s32
-; VI-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; VI-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; VI-NEXT:    s_endpgm
 ;
 ; CI-LABEL: test_call_external_void_func_v32i32:
 ; CI:       ; %bb.0:
-; CI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x0
-; CI-NEXT:    s_mov_b32 s7, 0xf000
-; CI-NEXT:    s_mov_b32 s6, -1
 ; CI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
-; CI-NEXT:    s_waitcnt lgkmcnt(0)
-; CI-NEXT:    buffer_load_dwordx4 v[28:31], off, s[4:7], 0 offset:112
-; CI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[4:7], 0
-; CI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:16
-; CI-NEXT:    buffer_load_dwordx4 v[8:11], off, s[4:7], 0 offset:32
-; CI-NEXT:    buffer_load_dwordx4 v[12:15], off, s[4:7], 0 offset:48
-; CI-NEXT:    buffer_load_dwordx4 v[16:19], off, s[4:7], 0 offset:64
-; CI-NEXT:    buffer_load_dwordx4 v[20:23], off, s[4:7], 0 offset:80
-; CI-NEXT:    buffer_load_dwordx4 v[24:27], off, s[4:7], 0 offset:96
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_add_u32 s36, s36, s1
+; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
+; CI-NEXT:    s_mov_b32 s3, 0xf000
+; CI-NEXT:    s_mov_b32 s2, -1
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT:    s_waitcnt lgkmcnt(0)
+; CI-NEXT:    buffer_load_dwordx4 v[28:31], off, s[0:3], 0 offset:112
+; CI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0
+; CI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; CI-NEXT:    buffer_load_dwordx4 v[8:11], off, s[0:3], 0 offset:32
+; CI-NEXT:    buffer_load_dwordx4 v[12:15], off, s[0:3], 0 offset:48
+; CI-NEXT:    buffer_load_dwordx4 v[16:19], off, s[0:3], 0 offset:64
+; CI-NEXT:    buffer_load_dwordx4 v[20:23], off, s[0:3], 0 offset:80
+; CI-NEXT:    buffer_load_dwordx4 v[24:27], off, s[0:3], 0 offset:96
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b32 s32, 0
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
-; CI-NEXT:    s_getpc_b64 s[8:9]
-; CI-NEXT:    s_add_u32 s8, s8, external_void_func_v32i32@rel32@lo+4
-; CI-NEXT:    s_addc_u32 s9, s9, external_void_func_v32i32@rel32@hi+12
+; CI-NEXT:    s_getpc_b64 s[4:5]
+; CI-NEXT:    s_add_u32 s4, s4, external_void_func_v32i32@rel32@lo+4
+; CI-NEXT:    s_addc_u32 s5, s5, external_void_func_v32i32@rel32@hi+12
 ; CI-NEXT:    s_waitcnt vmcnt(7)
 ; CI-NEXT:    buffer_store_dword v31, off, s[36:39], s32
-; CI-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; CI-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; CI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: test_call_external_void_func_v32i32:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x0
-; GFX9-NEXT:    s_mov_b32 s7, 0xf000
-; GFX9-NEXT:    s_mov_b32 s6, -1
 ; GFX9-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
-; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    buffer_load_dwordx4 v[28:31], off, s[4:7], 0 offset:112
-; GFX9-NEXT:    buffer_load_dwordx4 v[0:3], off, s[4:7], 0
-; GFX9-NEXT:    buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:16
-; GFX9-NEXT:    buffer_load_dwordx4 v[8:11], off, s[4:7], 0 offset:32
-; GFX9-NEXT:    buffer_load_dwordx4 v[12:15], off, s[4:7], 0 offset:48
-; GFX9-NEXT:    buffer_load_dwordx4 v[16:19], off, s[4:7], 0 offset:64
-; GFX9-NEXT:    buffer_load_dwordx4 v[20:23], off, s[4:7], 0 offset:80
-; GFX9-NEXT:    buffer_load_dwordx4 v[24:27], off, s[4:7], 0 offset:96
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
+; GFX9-NEXT:    s_mov_b32 s3, 0xf000
+; GFX9-NEXT:    s_mov_b32 s2, -1
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    buffer_load_dwordx4 v[28:31], off, s[0:3], 0 offset:112
+; GFX9-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0
+; GFX9-NEXT:    buffer_load_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; GFX9-NEXT:    buffer_load_dwordx4 v[8:11], off, s[0:3], 0 offset:32
+; GFX9-NEXT:    buffer_load_dwordx4 v[12:15], off, s[0:3], 0 offset:48
+; GFX9-NEXT:    buffer_load_dwordx4 v[16:19], off, s[0:3], 0 offset:64
+; GFX9-NEXT:    buffer_load_dwordx4 v[20:23], off, s[0:3], 0 offset:80
+; GFX9-NEXT:    buffer_load_dwordx4 v[24:27], off, s[0:3], 0 offset:96
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
-; GFX9-NEXT:    s_getpc_b64 s[8:9]
-; GFX9-NEXT:    s_add_u32 s8, s8, external_void_func_v32i32@rel32@lo+4
-; GFX9-NEXT:    s_addc_u32 s9, s9, external_void_func_v32i32@rel32@hi+12
+; GFX9-NEXT:    s_getpc_b64 s[4:5]
+; GFX9-NEXT:    s_add_u32 s4, s4, external_void_func_v32i32@rel32@lo+4
+; GFX9-NEXT:    s_addc_u32 s5, s5, external_void_func_v32i32@rel32@hi+12
 ; GFX9-NEXT:    s_waitcnt vmcnt(7)
 ; GFX9-NEXT:    buffer_store_dword v31, off, s[36:39], s32
-; GFX9-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; GFX9-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: test_call_external_void_func_v32i32:
 ; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[4:5], s[0:1], 0x0
-; GFX11-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX11-NEXT:    s_mov_b32 s6, -1
+; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x0
+; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-NEXT:    s_mov_b32 s2, -1
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v32i32@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v32i32@rel32@hi+12
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11-NEXT:    s_clause 0x7
-; GFX11-NEXT:    buffer_load_b128 v[28:31], off, s[4:7], 0 offset:112
-; GFX11-NEXT:    buffer_load_b128 v[0:3], off, s[4:7], 0
-; GFX11-NEXT:    buffer_load_b128 v[4:7], off, s[4:7], 0 offset:16
-; GFX11-NEXT:    buffer_load_b128 v[8:11], off, s[4:7], 0 offset:32
-; GFX11-NEXT:    buffer_load_b128 v[12:15], off, s[4:7], 0 offset:48
-; GFX11-NEXT:    buffer_load_b128 v[16:19], off, s[4:7], 0 offset:64
-; GFX11-NEXT:    buffer_load_b128 v[20:23], off, s[4:7], 0 offset:80
-; GFX11-NEXT:    buffer_load_b128 v[24:27], off, s[4:7], 0 offset:96
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
+; GFX11-NEXT:    buffer_load_b128 v[28:31], off, s[0:3], 0 offset:112
+; GFX11-NEXT:    buffer_load_b128 v[0:3], off, s[0:3], 0
+; GFX11-NEXT:    buffer_load_b128 v[4:7], off, s[0:3], 0 offset:16
+; GFX11-NEXT:    buffer_load_b128 v[8:11], off, s[0:3], 0 offset:32
+; GFX11-NEXT:    buffer_load_b128 v[12:15], off, s[0:3], 0 offset:48
+; GFX11-NEXT:    buffer_load_b128 v[16:19], off, s[0:3], 0 offset:64
+; GFX11-NEXT:    buffer_load_b128 v[20:23], off, s[0:3], 0 offset:80
+; GFX11-NEXT:    buffer_load_b128 v[24:27], off, s[0:3], 0 offset:96
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v32i32@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v32i32@rel32@hi+12
 ; GFX11-NEXT:    s_waitcnt vmcnt(7)
 ; GFX11-NEXT:    scratch_store_b32 off, v31, s32
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v32i32:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s9
-; HSA-NEXT:    s_load_dwordx2 s[8:9], s[4:5], 0x0
-; HSA-NEXT:    s_mov_b32 s11, 0x1100f000
-; HSA-NEXT:    s_mov_b32 s10, -1
-; HSA-NEXT:    s_mov_b32 s32, 0
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x0
+; HSA-NEXT:    s_add_u32 s0, s0, s7
+; HSA-NEXT:    s_mov_b32 s7, 0x1100f000
+; HSA-NEXT:    s_mov_b32 s6, -1
 ; HSA-NEXT:    s_waitcnt lgkmcnt(0)
-; HSA-NEXT:    buffer_load_dwordx4 v[28:31], off, s[8:11], 0 offset:112
-; HSA-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; HSA-NEXT:    buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
-; HSA-NEXT:    buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:32
-; HSA-NEXT:    buffer_load_dwordx4 v[12:15], off, s[8:11], 0 offset:48
-; HSA-NEXT:    buffer_load_dwordx4 v[16:19], off, s[8:11], 0 offset:64
-; HSA-NEXT:    buffer_load_dwordx4 v[20:23], off, s[8:11], 0 offset:80
-; HSA-NEXT:    buffer_load_dwordx4 v[24:27], off, s[8:11], 0 offset:96
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    buffer_load_dwordx4 v[28:31], off, s[4:7], 0 offset:112
+; HSA-NEXT:    buffer_load_dwordx4 v[0:3], off, s[4:7], 0
+; HSA-NEXT:    buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:16
+; HSA-NEXT:    buffer_load_dwordx4 v[8:11], off, s[4:7], 0 offset:32
+; HSA-NEXT:    buffer_load_dwordx4 v[12:15], off, s[4:7], 0 offset:48
+; HSA-NEXT:    buffer_load_dwordx4 v[16:19], off, s[4:7], 0 offset:64
+; HSA-NEXT:    buffer_load_dwordx4 v[20:23], off, s[4:7], 0 offset:80
+; HSA-NEXT:    buffer_load_dwordx4 v[24:27], off, s[4:7], 0 offset:96
+; HSA-NEXT:    s_mov_b32 s32, 0
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
-; HSA-NEXT:    s_getpc_b64 s[12:13]
-; HSA-NEXT:    s_add_u32 s12, s12, external_void_func_v32i32@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s13, s13, external_void_func_v32i32@rel32@hi+12
+; HSA-NEXT:    s_getpc_b64 s[8:9]
+; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v32i32@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v32i32@rel32@hi+12
 ; HSA-NEXT:    s_waitcnt vmcnt(7)
 ; HSA-NEXT:    buffer_store_dword v31, off, s[0:3], s32
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[12:13]
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
 ; HSA-NEXT:    s_endpgm
   %ptr = load ptr addrspace(1), ptr addrspace(4) undef
   %val = load <32 x i32>, ptr addrspace(1) %ptr
@@ -4422,25 +4214,24 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32_i32(i32) #0 {
 ; VI-LABEL: test_call_external_void_func_v32i32_i32:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
+; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s5
-; VI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x0
-; VI-NEXT:    s_mov_b32 s7, 0xf000
-; VI-NEXT:    s_mov_b32 s6, -1
-; VI-NEXT:    s_addc_u32 s37, s37, 0
+; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_mov_b32 s3, 0xf000
+; VI-NEXT:    s_mov_b32 s2, -1
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    buffer_load_dword v32, off, s[4:7], 0
-; VI-NEXT:    buffer_load_dwordx4 v[28:31], off, s[4:7], 0 offset:112
-; VI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[4:7], 0
-; VI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:16
-; VI-NEXT:    buffer_load_dwordx4 v[8:11], off, s[4:7], 0 offset:32
-; VI-NEXT:    buffer_load_dwordx4 v[12:15], off, s[4:7], 0 offset:48
-; VI-NEXT:    buffer_load_dwordx4 v[16:19], off, s[4:7], 0 offset:64
-; VI-NEXT:    buffer_load_dwordx4 v[20:23], off, s[4:7], 0 offset:80
-; VI-NEXT:    buffer_load_dwordx4 v[24:27], off, s[4:7], 0 offset:96
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT:    buffer_load_dword v32, off, s[0:3], 0
+; VI-NEXT:    buffer_load_dwordx4 v[28:31], off, s[0:3], 0 offset:112
+; VI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0
+; VI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; VI-NEXT:    buffer_load_dwordx4 v[8:11], off, s[0:3], 0 offset:32
+; VI-NEXT:    buffer_load_dwordx4 v[12:15], off, s[0:3], 0 offset:48
+; VI-NEXT:    buffer_load_dwordx4 v[16:19], off, s[0:3], 0 offset:64
+; VI-NEXT:    buffer_load_dwordx4 v[20:23], off, s[0:3], 0 offset:80
+; VI-NEXT:    buffer_load_dwordx4 v[24:27], off, s[0:3], 0 offset:96
+; VI-NEXT:    s_addc_u32 s37, s37, 0
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b32 s32, 0
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
@@ -4457,25 +4248,24 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32_i32(i32) #0 {
 ; CI-LABEL: test_call_external_void_func_v32i32_i32:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
+; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s5
-; CI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x0
-; CI-NEXT:    s_mov_b32 s7, 0xf000
-; CI-NEXT:    s_mov_b32 s6, -1
-; CI-NEXT:    s_addc_u32 s37, s37, 0
+; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_mov_b32 s3, 0xf000
+; CI-NEXT:    s_mov_b32 s2, -1
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
-; CI-NEXT:    buffer_load_dword v32, off, s[4:7], 0
-; CI-NEXT:    buffer_load_dwordx4 v[28:31], off, s[4:7], 0 offset:112
-; CI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[4:7], 0
-; CI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:16
-; CI-NEXT:    buffer_load_dwordx4 v[8:11], off, s[4:7], 0 offset:32
-; CI-NEXT:    buffer_load_dwordx4 v[12:15], off, s[4:7], 0 offset:48
-; CI-NEXT:    buffer_load_dwordx4 v[16:19], off, s[4:7], 0 offset:64
-; CI-NEXT:    buffer_load_dwordx4 v[20:23], off, s[4:7], 0 offset:80
-; CI-NEXT:    buffer_load_dwordx4 v[24:27], off, s[4:7], 0 offset:96
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT:    buffer_load_dword v32, off, s[0:3], 0
+; CI-NEXT:    buffer_load_dwordx4 v[28:31], off, s[0:3], 0 offset:112
+; CI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0
+; CI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; CI-NEXT:    buffer_load_dwordx4 v[8:11], off, s[0:3], 0 offset:32
+; CI-NEXT:    buffer_load_dwordx4 v[12:15], off, s[0:3], 0 offset:48
+; CI-NEXT:    buffer_load_dwordx4 v[16:19], off, s[0:3], 0 offset:64
+; CI-NEXT:    buffer_load_dwordx4 v[20:23], off, s[0:3], 0 offset:80
+; CI-NEXT:    buffer_load_dwordx4 v[24:27], off, s[0:3], 0 offset:96
+; CI-NEXT:    s_addc_u32 s37, s37, 0
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b32 s32, 0
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
@@ -4492,25 +4282,24 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32_i32(i32) #0 {
 ; GFX9-LABEL: test_call_external_void_func_v32i32_i32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s5
-; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x0
-; GFX9-NEXT:    s_mov_b32 s7, 0xf000
-; GFX9-NEXT:    s_mov_b32 s6, -1
-; GFX9-NEXT:    s_addc_u32 s37, s37, 0
+; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_mov_b32 s3, 0xf000
+; GFX9-NEXT:    s_mov_b32 s2, -1
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    buffer_load_dword v32, off, s[4:7], 0
-; GFX9-NEXT:    buffer_load_dwordx4 v[28:31], off, s[4:7], 0 offset:112
-; GFX9-NEXT:    buffer_load_dwordx4 v[0:3], off, s[4:7], 0
-; GFX9-NEXT:    buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:16
-; GFX9-NEXT:    buffer_load_dwordx4 v[8:11], off, s[4:7], 0 offset:32
-; GFX9-NEXT:    buffer_load_dwordx4 v[12:15], off, s[4:7], 0 offset:48
-; GFX9-NEXT:    buffer_load_dwordx4 v[16:19], off, s[4:7], 0 offset:64
-; GFX9-NEXT:    buffer_load_dwordx4 v[20:23], off, s[4:7], 0 offset:80
-; GFX9-NEXT:    buffer_load_dwordx4 v[24:27], off, s[4:7], 0 offset:96
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
+; GFX9-NEXT:    buffer_load_dword v32, off, s[0:3], 0
+; GFX9-NEXT:    buffer_load_dwordx4 v[28:31], off, s[0:3], 0 offset:112
+; GFX9-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0
+; GFX9-NEXT:    buffer_load_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; GFX9-NEXT:    buffer_load_dwordx4 v[8:11], off, s[0:3], 0 offset:32
+; GFX9-NEXT:    buffer_load_dwordx4 v[12:15], off, s[0:3], 0 offset:48
+; GFX9-NEXT:    buffer_load_dwordx4 v[16:19], off, s[0:3], 0 offset:64
+; GFX9-NEXT:    buffer_load_dwordx4 v[20:23], off, s[0:3], 0 offset:80
+; GFX9-NEXT:    buffer_load_dwordx4 v[24:27], off, s[0:3], 0 offset:96
+; GFX9-NEXT:    s_addc_u32 s37, s37, 0
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
@@ -4526,63 +4315,61 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32_i32(i32) #0 {
 ;
 ; GFX11-LABEL: test_call_external_void_func_v32i32_i32:
 ; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[4:5], s[0:1], 0x0
-; GFX11-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX11-NEXT:    s_mov_b32 s6, -1
+; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x0
+; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-NEXT:    s_mov_b32 s2, -1
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v32i32_i32@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v32i32_i32@rel32@hi+12
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11-NEXT:    s_clause 0x8
-; GFX11-NEXT:    buffer_load_b128 v[28:31], off, s[4:7], 0 offset:112
-; GFX11-NEXT:    buffer_load_b32 v32, off, s[4:7], 0
-; GFX11-NEXT:    buffer_load_b128 v[0:3], off, s[4:7], 0
-; GFX11-NEXT:    buffer_load_b128 v[4:7], off, s[4:7], 0 offset:16
-; GFX11-NEXT:    buffer_load_b128 v[8:11], off, s[4:7], 0 offset:32
-; GFX11-NEXT:    buffer_load_b128 v[12:15], off, s[4:7], 0 offset:48
-; GFX11-NEXT:    buffer_load_b128 v[16:19], off, s[4:7], 0 offset:64
-; GFX11-NEXT:    buffer_load_b128 v[20:23], off, s[4:7], 0 offset:80
-; GFX11-NEXT:    buffer_load_b128 v[24:27], off, s[4:7], 0 offset:96
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; GFX11-NEXT:    s_add_i32 s4, s32, 4
+; GFX11-NEXT:    buffer_load_b128 v[28:31], off, s[0:3], 0 offset:112
+; GFX11-NEXT:    buffer_load_b32 v32, off, s[0:3], 0
+; GFX11-NEXT:    buffer_load_b128 v[0:3], off, s[0:3], 0
+; GFX11-NEXT:    buffer_load_b128 v[4:7], off, s[0:3], 0 offset:16
+; GFX11-NEXT:    buffer_load_b128 v[8:11], off, s[0:3], 0 offset:32
+; GFX11-NEXT:    buffer_load_b128 v[12:15], off, s[0:3], 0 offset:48
+; GFX11-NEXT:    buffer_load_b128 v[16:19], off, s[0:3], 0 offset:64
+; GFX11-NEXT:    buffer_load_b128 v[20:23], off, s[0:3], 0 offset:80
+; GFX11-NEXT:    buffer_load_b128 v[24:27], off, s[0:3], 0 offset:96
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v32i32_i32@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v32i32_i32@rel32@hi+12
+; GFX11-NEXT:    s_add_i32 s2, s32, 4
 ; GFX11-NEXT:    s_waitcnt vmcnt(8)
 ; GFX11-NEXT:    scratch_store_b32 off, v31, s32
 ; GFX11-NEXT:    s_waitcnt vmcnt(7)
-; GFX11-NEXT:    scratch_store_b32 off, v32, s4
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    scratch_store_b32 off, v32, s2
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v32i32_i32:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s8, s8, s11
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s8, 8
-; HSA-NEXT:    s_load_dwordx2 s[8:9], s[4:5], 0x0
-; HSA-NEXT:    s_add_u32 s0, s0, s11
-; HSA-NEXT:    s_mov_b32 s11, 0x1100f000
-; HSA-NEXT:    s_mov_b32 s10, -1
+; HSA-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x0
+; HSA-NEXT:    s_add_i32 s6, s6, s9
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
+; HSA-NEXT:    s_mov_b32 s7, 0x1100f000
+; HSA-NEXT:    s_mov_b32 s6, -1
 ; HSA-NEXT:    s_waitcnt lgkmcnt(0)
-; HSA-NEXT:    buffer_load_dword v32, off, s[8:11], 0
-; HSA-NEXT:    buffer_load_dwordx4 v[28:31], off, s[8:11], 0 offset:112
-; HSA-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; HSA-NEXT:    buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
-; HSA-NEXT:    buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:32
-; HSA-NEXT:    buffer_load_dwordx4 v[12:15], off, s[8:11], 0 offset:48
-; HSA-NEXT:    buffer_load_dwordx4 v[16:19], off, s[8:11], 0 offset:64
-; HSA-NEXT:    buffer_load_dwordx4 v[20:23], off, s[8:11], 0 offset:80
-; HSA-NEXT:    buffer_load_dwordx4 v[24:27], off, s[8:11], 0 offset:96
+; HSA-NEXT:    buffer_load_dword v32, off, s[4:7], 0
+; HSA-NEXT:    buffer_load_dwordx4 v[28:31], off, s[4:7], 0 offset:112
+; HSA-NEXT:    buffer_load_dwordx4 v[0:3], off, s[4:7], 0
+; HSA-NEXT:    buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:16
+; HSA-NEXT:    buffer_load_dwordx4 v[8:11], off, s[4:7], 0 offset:32
+; HSA-NEXT:    buffer_load_dwordx4 v[12:15], off, s[4:7], 0 offset:48
+; HSA-NEXT:    buffer_load_dwordx4 v[16:19], off, s[4:7], 0 offset:64
+; HSA-NEXT:    buffer_load_dwordx4 v[20:23], off, s[4:7], 0 offset:80
+; HSA-NEXT:    buffer_load_dwordx4 v[24:27], off, s[4:7], 0 offset:96
+; HSA-NEXT:    s_add_u32 s0, s0, s9
 ; HSA-NEXT:    s_mov_b32 s32, 0
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v32i32_i32@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v32i32_i32@rel32@hi+12
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v32i32_i32@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v32i32_i32@rel32@hi+12
 ; HSA-NEXT:    s_waitcnt vmcnt(8)
 ; HSA-NEXT:    buffer_store_dword v32, off, s[0:3], s32 offset:4
 ; HSA-NEXT:    s_waitcnt vmcnt(8)
 ; HSA-NEXT:    buffer_store_dword v31, off, s[0:3], s32
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   %ptr0 = load ptr addrspace(1), ptr addrspace(4) undef
   %val0 = load <32 x i32>, ptr addrspace(1) %ptr0
@@ -4598,10 +4385,9 @@ define amdgpu_kernel void @test_call_external_i32_func_i32_imm(ptr addrspace(1)
 ; VI-NEXT:    s_mov_b32 s41, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s42, -1
 ; VI-NEXT:    s_mov_b32 s43, 0xe80000
-; VI-NEXT:    s_add_u32 s40, s40, s5
-; VI-NEXT:    s_load_dwordx2 s[36:37], s[2:3], 0x24
+; VI-NEXT:    s_add_u32 s40, s40, s3
+; VI-NEXT:    s_load_dwordx2 s[36:37], s[0:1], 0x24
 ; VI-NEXT:    s_addc_u32 s41, s41, 0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[40:41]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[42:43]
 ; VI-NEXT:    v_mov_b32_e32 v0, 42
@@ -4622,10 +4408,9 @@ define amdgpu_kernel void @test_call_external_i32_func_i32_imm(ptr addrspace(1)
 ; CI-NEXT:    s_mov_b32 s41, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s42, -1
 ; CI-NEXT:    s_mov_b32 s43, 0xe8f000
-; CI-NEXT:    s_add_u32 s40, s40, s5
-; CI-NEXT:    s_load_dwordx2 s[36:37], s[2:3], 0x9
+; CI-NEXT:    s_add_u32 s40, s40, s3
+; CI-NEXT:    s_load_dwordx2 s[36:37], s[0:1], 0x9
 ; CI-NEXT:    s_addc_u32 s41, s41, 0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[40:41]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[42:43]
 ; CI-NEXT:    v_mov_b32_e32 v0, 42
@@ -4646,10 +4431,9 @@ define amdgpu_kernel void @test_call_external_i32_func_i32_imm(ptr addrspace(1)
 ; GFX9-NEXT:    s_mov_b32 s41, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s42, -1
 ; GFX9-NEXT:    s_mov_b32 s43, 0xe00000
-; GFX9-NEXT:    s_add_u32 s40, s40, s5
-; GFX9-NEXT:    s_load_dwordx2 s[36:37], s[2:3], 0x24
+; GFX9-NEXT:    s_add_u32 s40, s40, s3
+; GFX9-NEXT:    s_load_dwordx2 s[36:37], s[0:1], 0x24
 ; GFX9-NEXT:    s_addc_u32 s41, s41, 0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[40:41]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[42:43]
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 42
@@ -4666,17 +4450,16 @@ define amdgpu_kernel void @test_call_external_i32_func_i32_imm(ptr addrspace(1)
 ;
 ; GFX11-LABEL: test_call_external_i32_func_i32_imm:
 ; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[36:37], s[2:3], 0x24
+; GFX11-NEXT:    s_load_b64 s[36:37], s[0:1], 0x24
 ; GFX11-NEXT:    v_mov_b32_e32 v0, 42
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX11-NEXT:    s_mov_b32 s32, 0
 ; GFX11-NEXT:    s_mov_b32 s39, 0x31016000
 ; GFX11-NEXT:    s_mov_b32 s38, -1
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_i32_func_i32@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_i32_func_i32@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_i32_func_i32@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_i32_func_i32@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    buffer_store_b32 v0, off, s[36:39], 0 dlc
 ; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX11-NEXT:    s_nop 0
@@ -4685,21 +4468,20 @@ define amdgpu_kernel void @test_call_external_i32_func_i32_imm(ptr addrspace(1)
 ;
 ; HSA-LABEL: test_call_external_i32_func_i32_imm:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s8, s8, s11
-; HSA-NEXT:    s_load_dwordx2 s[36:37], s[6:7], 0x0
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s8, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s11
+; HSA-NEXT:    s_add_i32 s6, s6, s9
+; HSA-NEXT:    s_load_dwordx2 s[36:37], s[4:5], 0x0
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s9
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    v_mov_b32_e32 v0, 42
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s9
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
 ; HSA-NEXT:    s_mov_b32 s39, 0x1100f000
 ; HSA-NEXT:    s_mov_b32 s38, -1
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_i32_func_i32@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_i32_func_i32@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_i32_func_i32@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_i32_func_i32@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    buffer_store_dword v0, off, s[36:39], 0
 ; HSA-NEXT:    s_waitcnt vmcnt(0)
 ; HSA-NEXT:    s_endpgm
@@ -4712,18 +4494,17 @@ define amdgpu_kernel void @test_call_external_void_func_struct_i8_i32() #0 {
 ; VI-LABEL: test_call_external_void_func_struct_i8_i32:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_add_u32 s36, s36, s1
+; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; VI-NEXT:    s_mov_b32 s3, 0xf000
 ; VI-NEXT:    s_mov_b32 s2, -1
+; VI-NEXT:    s_addc_u32 s37, s37, 0
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    buffer_load_ubyte v0, off, s[0:3], 0
 ; VI-NEXT:    buffer_load_dword v1, off, s[0:3], 0 offset:4
-; VI-NEXT:    s_addc_u32 s37, s37, 0
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    s_mov_b32 s32, 0
@@ -4736,18 +4517,17 @@ define amdgpu_kernel void @test_call_external_void_func_struct_i8_i32() #0 {
 ; CI-LABEL: test_call_external_void_func_struct_i8_i32:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_add_u32 s36, s36, s1
+; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; CI-NEXT:    s_mov_b32 s3, 0xf000
 ; CI-NEXT:    s_mov_b32 s2, -1
+; CI-NEXT:    s_addc_u32 s37, s37, 0
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    buffer_load_ubyte v0, off, s[0:3], 0
 ; CI-NEXT:    buffer_load_dword v1, off, s[0:3], 0 offset:4
-; CI-NEXT:    s_addc_u32 s37, s37, 0
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    s_mov_b32 s32, 0
@@ -4760,18 +4540,17 @@ define amdgpu_kernel void @test_call_external_void_func_struct_i8_i32() #0 {
 ; GFX9-LABEL: test_call_external_void_func_struct_i8_i32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; GFX9-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX9-NEXT:    s_mov_b32 s2, -1
+; GFX9-NEXT:    s_addc_u32 s37, s37, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    buffer_load_ubyte v0, off, s[0:3], 0
 ; GFX9-NEXT:    buffer_load_dword v1, off, s[0:3], 0 offset:4
-; GFX9-NEXT:    s_addc_u32 s37, s37, 0
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
@@ -4783,40 +4562,39 @@ define amdgpu_kernel void @test_call_external_void_func_struct_i8_i32() #0 {
 ;
 ; GFX11-LABEL: test_call_external_void_func_struct_i8_i32:
 ; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[4:5], s[0:1], 0x0
-; GFX11-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX11-NEXT:    s_mov_b32 s6, -1
+; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x0
+; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-NEXT:    s_mov_b32 s2, -1
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_struct_i8_i32@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_struct_i8_i32@rel32@hi+12
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    buffer_load_u8 v0, off, s[4:7], 0
-; GFX11-NEXT:    buffer_load_b32 v1, off, s[4:7], 0 offset:4
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    buffer_load_u8 v0, off, s[0:3], 0
+; GFX11-NEXT:    buffer_load_b32 v1, off, s[0:3], 0 offset:4
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_struct_i8_i32@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_struct_i8_i32@rel32@hi+12
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_struct_i8_i32:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s9
-; HSA-NEXT:    s_load_dwordx2 s[8:9], s[4:5], 0x0
-; HSA-NEXT:    s_mov_b32 s11, 0x1100f000
-; HSA-NEXT:    s_mov_b32 s10, -1
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x0
+; HSA-NEXT:    s_add_u32 s0, s0, s7
+; HSA-NEXT:    s_mov_b32 s7, 0x1100f000
+; HSA-NEXT:    s_mov_b32 s6, -1
 ; HSA-NEXT:    s_waitcnt lgkmcnt(0)
-; HSA-NEXT:    buffer_load_ubyte v0, off, s[8:11], 0
-; HSA-NEXT:    buffer_load_dword v1, off, s[8:11], 0 offset:4
+; HSA-NEXT:    buffer_load_ubyte v0, off, s[4:7], 0
+; HSA-NEXT:    buffer_load_dword v1, off, s[4:7], 0 offset:4
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_struct_i8_i32@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_struct_i8_i32@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_struct_i8_i32@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_struct_i8_i32@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   %ptr0 = load ptr addrspace(1), ptr addrspace(4) undef
   %val = load { i8, i32 }, ptr addrspace(1) %ptr0
@@ -4831,7 +4609,7 @@ define amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_add_u32 s36, s36, s1
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
 ; VI-NEXT:    v_mov_b32_e32 v0, 3
 ; VI-NEXT:    buffer_store_byte v0, off, s[36:39], 0 offset:8
@@ -4839,7 +4617,6 @@ define amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0
 ; VI-NEXT:    buffer_store_dword v0, off, s[36:39], 0 offset:12
 ; VI-NEXT:    buffer_load_dword v0, off, s[36:39], 0 offset:12
 ; VI-NEXT:    buffer_load_dword v1, off, s[36:39], 0 offset:8
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_movk_i32 s32, 0x400
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
@@ -4859,7 +4636,7 @@ define amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_add_u32 s36, s36, s1
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
 ; CI-NEXT:    v_mov_b32_e32 v0, 3
 ; CI-NEXT:    buffer_store_byte v0, off, s[36:39], 0 offset:8
@@ -4867,7 +4644,6 @@ define amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0
 ; CI-NEXT:    buffer_store_dword v0, off, s[36:39], 0 offset:12
 ; CI-NEXT:    buffer_load_dword v0, off, s[36:39], 0 offset:12
 ; CI-NEXT:    buffer_load_dword v1, off, s[36:39], 0 offset:8
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_movk_i32 s32, 0x400
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
@@ -4887,7 +4663,7 @@ define amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 3
 ; GFX9-NEXT:    buffer_store_byte v0, off, s[36:39], 0 offset:8
@@ -4896,7 +4672,6 @@ define amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0
 ; GFX9-NEXT:    buffer_load_dword v0, off, s[36:39], 0 offset:12
 ; GFX9-NEXT:    s_nop 0
 ; GFX9-NEXT:    buffer_load_dword v1, off, s[36:39], 0 offset:8
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_movk_i32 s32, 0x400
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
@@ -4914,24 +4689,23 @@ define amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v1, 8
 ; GFX11-NEXT:    s_mov_b32 s32, 16
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_byval_struct_i8_i32@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_byval_struct_i8_i32@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_byval_struct_i8_i32@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_byval_struct_i8_i32@rel32@hi+12
 ; GFX11-NEXT:    s_clause 0x1
 ; GFX11-NEXT:    scratch_store_b8 off, v0, off offset:8
 ; GFX11-NEXT:    scratch_store_b32 off, v1, off offset:12
 ; GFX11-NEXT:    scratch_load_b64 v[0:1], off, off offset:8
 ; GFX11-NEXT:    s_waitcnt vmcnt(0)
 ; GFX11-NEXT:    scratch_store_b64 off, v[0:1], s32
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_byval_struct_i8_i32:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s9
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s7
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
 ; HSA-NEXT:    v_mov_b32_e32 v0, 3
 ; HSA-NEXT:    buffer_store_byte v0, off, s[0:3], 0 offset:8
@@ -4940,16 +4714,15 @@ define amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0
 ; HSA-NEXT:    buffer_load_dword v0, off, s[0:3], 0 offset:12
 ; HSA-NEXT:    buffer_load_dword v1, off, s[0:3], 0 offset:8
 ; HSA-NEXT:    s_movk_i32 s32, 0x400
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_byval_struct_i8_i32@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_byval_struct_i8_i32@rel32@hi+12
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_byval_struct_i8_i32@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_byval_struct_i8_i32@rel32@hi+12
 ; HSA-NEXT:    s_waitcnt vmcnt(1)
 ; HSA-NEXT:    buffer_store_dword v0, off, s[0:3], s32 offset:4
 ; HSA-NEXT:    s_waitcnt vmcnt(1)
 ; HSA-NEXT:    buffer_store_dword v1, off, s[0:3], s32
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   %val = alloca { i8, i32 }, align 8, addrspace(5)
   %gep0 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %val, i32 0, i32 0
@@ -4967,7 +4740,7 @@ define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s5
+; VI-NEXT:    s_add_u32 s36, s36, s3
 ; VI-NEXT:    s_addc_u32 s37, s37, 0
 ; VI-NEXT:    v_mov_b32_e32 v0, 3
 ; VI-NEXT:    buffer_store_byte v0, off, s[36:39], 0 offset:8
@@ -4976,7 +4749,6 @@ define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval
 ; VI-NEXT:    buffer_load_dword v0, off, s[36:39], 0 offset:12
 ; VI-NEXT:    buffer_load_dword v1, off, s[36:39], 0 offset:8
 ; VI-NEXT:    s_movk_i32 s32, 0x800
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; VI-NEXT:    s_getpc_b64 s[4:5]
@@ -5005,7 +4777,7 @@ define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s5
+; CI-NEXT:    s_add_u32 s36, s36, s3
 ; CI-NEXT:    s_addc_u32 s37, s37, 0
 ; CI-NEXT:    v_mov_b32_e32 v0, 3
 ; CI-NEXT:    buffer_store_byte v0, off, s[36:39], 0 offset:8
@@ -5014,7 +4786,6 @@ define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval
 ; CI-NEXT:    buffer_load_dword v0, off, s[36:39], 0 offset:12
 ; CI-NEXT:    buffer_load_dword v1, off, s[36:39], 0 offset:8
 ; CI-NEXT:    s_movk_i32 s32, 0x800
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; CI-NEXT:    s_getpc_b64 s[4:5]
@@ -5043,7 +4814,7 @@ define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s5
+; GFX9-NEXT:    s_add_u32 s36, s36, s3
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 3
 ; GFX9-NEXT:    buffer_store_byte v0, off, s[36:39], 0 offset:8
@@ -5053,7 +4824,6 @@ define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval
 ; GFX9-NEXT:    s_nop 0
 ; GFX9-NEXT:    buffer_load_dword v1, off, s[36:39], 0 offset:8
 ; GFX9-NEXT:    s_movk_i32 s32, 0x800
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_getpc_b64 s[4:5]
@@ -5080,10 +4850,9 @@ define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v1, 8
 ; GFX11-NEXT:    s_mov_b32 s32, 32
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@rel32@hi+12
 ; GFX11-NEXT:    s_clause 0x1
 ; GFX11-NEXT:    scratch_store_b8 off, v0, off offset:8
 ; GFX11-NEXT:    scratch_store_b32 off, v1, off offset:12
@@ -5091,7 +4860,7 @@ define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval
 ; GFX11-NEXT:    s_waitcnt vmcnt(0)
 ; GFX11-NEXT:    scratch_store_b64 off, v[0:1], s32
 ; GFX11-NEXT:    v_mov_b32_e32 v0, 16
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_clause 0x1
 ; GFX11-NEXT:    scratch_load_u8 v0, off, off offset:16
 ; GFX11-NEXT:    scratch_load_b32 v1, off, off offset:20
@@ -5109,9 +4878,9 @@ define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval
 ;
 ; HSA-LABEL: test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s8, s8, s11
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s8, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s11
+; HSA-NEXT:    s_add_i32 s6, s6, s9
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
+; HSA-NEXT:    s_add_u32 s0, s0, s9
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
 ; HSA-NEXT:    v_mov_b32_e32 v0, 3
 ; HSA-NEXT:    buffer_store_byte v0, off, s[0:3], 0 offset:8
@@ -5120,17 +4889,16 @@ define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval
 ; HSA-NEXT:    buffer_load_dword v0, off, s[0:3], 0 offset:12
 ; HSA-NEXT:    buffer_load_dword v1, off, s[0:3], 0 offset:8
 ; HSA-NEXT:    s_movk_i32 s32, 0x800
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s9
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@rel32@hi+12
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@rel32@hi+12
 ; HSA-NEXT:    s_waitcnt vmcnt(1)
 ; HSA-NEXT:    buffer_store_dword v0, off, s[0:3], s32 offset:4
 ; HSA-NEXT:    s_waitcnt vmcnt(1)
 ; HSA-NEXT:    buffer_store_dword v1, off, s[0:3], s32
 ; HSA-NEXT:    v_mov_b32_e32 v0, 16
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    buffer_load_ubyte v0, off, s[0:3], 0 offset:16
 ; HSA-NEXT:    buffer_load_dword v1, off, s[0:3], 0 offset:20
 ; HSA-NEXT:    s_mov_b32 s7, 0x1100f000
@@ -5162,20 +4930,19 @@ define amdgpu_kernel void @test_call_external_void_func_v16i8() #0 {
 ; VI-LABEL: test_call_external_void_func_v16i8:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; VI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s38, -1
 ; VI-NEXT:    s_mov_b32 s39, 0xe80000
-; VI-NEXT:    s_add_u32 s36, s36, s3
+; VI-NEXT:    s_add_u32 s36, s36, s1
+; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; VI-NEXT:    s_mov_b32 s3, 0xf000
 ; VI-NEXT:    s_mov_b32 s2, -1
+; VI-NEXT:    s_addc_u32 s37, s37, 0
+; VI-NEXT:    s_mov_b32 s32, 0
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0
-; VI-NEXT:    s_addc_u32 s37, s37, 0
 ; VI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; VI-NEXT:    s_mov_b64 s[2:3], s[38:39]
-; VI-NEXT:    s_mov_b32 s32, 0
 ; VI-NEXT:    s_getpc_b64 s[4:5]
 ; VI-NEXT:    s_add_u32 s4, s4, external_void_func_v16i8@rel32@lo+4
 ; VI-NEXT:    s_addc_u32 s5, s5, external_void_func_v16i8@rel32@hi+12
@@ -5204,20 +4971,19 @@ define amdgpu_kernel void @test_call_external_void_func_v16i8() #0 {
 ; CI-LABEL: test_call_external_void_func_v16i8:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; CI-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s38, -1
 ; CI-NEXT:    s_mov_b32 s39, 0xe8f000
-; CI-NEXT:    s_add_u32 s36, s36, s3
+; CI-NEXT:    s_add_u32 s36, s36, s1
+; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; CI-NEXT:    s_mov_b32 s3, 0xf000
 ; CI-NEXT:    s_mov_b32 s2, -1
+; CI-NEXT:    s_addc_u32 s37, s37, 0
+; CI-NEXT:    s_mov_b32 s32, 0
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0
-; CI-NEXT:    s_addc_u32 s37, s37, 0
 ; CI-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; CI-NEXT:    s_mov_b64 s[2:3], s[38:39]
-; CI-NEXT:    s_mov_b32 s32, 0
 ; CI-NEXT:    s_getpc_b64 s[4:5]
 ; CI-NEXT:    s_add_u32 s4, s4, external_void_func_v16i8@rel32@lo+4
 ; CI-NEXT:    s_addc_u32 s5, s5, external_void_func_v16i8@rel32@hi+12
@@ -5246,20 +5012,19 @@ define amdgpu_kernel void @test_call_external_void_func_v16i8() #0 {
 ; GFX9-LABEL: test_call_external_void_func_v16i8:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_mov_b32 s36, SCRATCH_RSRC_DWORD0
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s3
+; GFX9-NEXT:    s_add_u32 s36, s36, s1
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; GFX9-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX9-NEXT:    s_mov_b32 s2, -1
+; GFX9-NEXT:    s_addc_u32 s37, s37, 0
+; GFX9-NEXT:    s_mov_b32 s32, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0
-; GFX9-NEXT:    s_addc_u32 s37, s37, 0
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
-; GFX9-NEXT:    s_mov_b32 s32, 0
 ; GFX9-NEXT:    s_getpc_b64 s[4:5]
 ; GFX9-NEXT:    s_add_u32 s4, s4, external_void_func_v16i8@rel32@lo+4
 ; GFX9-NEXT:    s_addc_u32 s5, s5, external_void_func_v16i8@rel32@hi+12
@@ -5287,16 +5052,15 @@ define amdgpu_kernel void @test_call_external_void_func_v16i8() #0 {
 ;
 ; GFX11-LABEL: test_call_external_void_func_v16i8:
 ; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[4:5], s[0:1], 0x0
-; GFX11-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX11-NEXT:    s_mov_b32 s6, -1
+; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x0
+; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-NEXT:    s_mov_b32 s2, -1
 ; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v16i8@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v16i8@rel32@hi+12
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    buffer_load_b128 v[0:3], off, s[4:7], 0
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
+; GFX11-NEXT:    buffer_load_b128 v[0:3], off, s[0:3], 0
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, external_void_func_v16i8@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, external_void_func_v16i8@rel32@hi+12
 ; GFX11-NEXT:    s_waitcnt vmcnt(0)
 ; GFX11-NEXT:    v_lshrrev_b32_e32 v16, 8, v0
 ; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 16, v0
@@ -5314,26 +5078,25 @@ define amdgpu_kernel void @test_call_external_void_func_v16i8() #0 {
 ; GFX11-NEXT:    v_mov_b32_e32 v8, v2
 ; GFX11-NEXT:    v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v3, v18
 ; GFX11-NEXT:    v_mov_b32_e32 v2, v17
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v16i8:
 ; HSA:       ; %bb.0:
-; HSA-NEXT:    s_add_i32 s6, s6, s9
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
-; HSA-NEXT:    s_add_u32 s0, s0, s9
-; HSA-NEXT:    s_load_dwordx2 s[8:9], s[4:5], 0x0
-; HSA-NEXT:    s_mov_b32 s11, 0x1100f000
-; HSA-NEXT:    s_mov_b32 s10, -1
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_add_i32 s4, s4, s7
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s5
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
+; HSA-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x0
+; HSA-NEXT:    s_add_u32 s0, s0, s7
+; HSA-NEXT:    s_mov_b32 s7, 0x1100f000
+; HSA-NEXT:    s_mov_b32 s6, -1
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
 ; HSA-NEXT:    s_waitcnt lgkmcnt(0)
-; HSA-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
+; HSA-NEXT:    buffer_load_dwordx4 v[0:3], off, s[4:7], 0
 ; HSA-NEXT:    s_mov_b32 s32, 0
-; HSA-NEXT:    s_getpc_b64 s[8:9]
-; HSA-NEXT:    s_add_u32 s8, s8, external_void_func_v16i8@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s9, s9, external_void_func_v16i8@rel32@hi+12
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, external_void_func_v16i8@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, external_void_func_v16i8@rel32@hi+12
 ; HSA-NEXT:    s_waitcnt vmcnt(0)
 ; HSA-NEXT:    v_lshrrev_b32_e32 v16, 8, v0
 ; HSA-NEXT:    v_lshrrev_b32_e32 v17, 16, v0
@@ -5353,7 +5116,7 @@ define amdgpu_kernel void @test_call_external_void_func_v16i8() #0 {
 ; HSA-NEXT:    v_mov_b32_e32 v1, v16
 ; HSA-NEXT:    v_mov_b32_e32 v2, v17
 ; HSA-NEXT:    v_mov_b32_e32 v3, v18
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
   %ptr = load ptr addrspace(1), ptr addrspace(4) undef
   %val = load <16 x i8>, ptr addrspace(1) %ptr
@@ -5368,19 +5131,18 @@ define amdgpu_kernel void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val
 ; VI-NEXT:    s_mov_b32 s53, SCRATCH_RSRC_DWORD1
 ; VI-NEXT:    s_mov_b32 s54, -1
 ; VI-NEXT:    s_mov_b32 s55, 0xe80000
-; VI-NEXT:    s_add_u32 s52, s52, s5
-; VI-NEXT:    s_load_dwordx16 s[8:23], s[2:3], 0x64
-; VI-NEXT:    s_load_dwordx2 s[4:5], s[2:3], 0xa4
-; VI-NEXT:    s_load_dwordx16 s[36:51], s[2:3], 0x24
+; VI-NEXT:    s_add_u32 s52, s52, s3
+; VI-NEXT:    s_load_dwordx16 s[4:19], s[0:1], 0x64
+; VI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xa4
+; VI-NEXT:    s_load_dwordx16 s[36:51], s[0:1], 0x24
 ; VI-NEXT:    s_mov_b32 s32, 0
 ; VI-NEXT:    s_addc_u32 s53, s53, 0
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s23
+; VI-NEXT:    v_mov_b32_e32 v0, s19
+; VI-NEXT:    v_mov_b32_e32 v1, s2
 ; VI-NEXT:    buffer_store_dword v0, off, s[52:55], s32
-; VI-NEXT:    v_mov_b32_e32 v0, s4
-; VI-NEXT:    buffer_store_dword v0, off, s[52:55], s32 offset:4
-; VI-NEXT:    v_mov_b32_e32 v0, s5
-; VI-NEXT:    s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT:    buffer_store_dword v1, off, s[52:55], s32 offset:4
+; VI-NEXT:    v_mov_b32_e32 v0, s3
 ; VI-NEXT:    s_mov_b64 s[0:1], s[52:53]
 ; VI-NEXT:    buffer_store_dword v0, off, s[52:55], s32 offset:8
 ; VI-NEXT:    s_mov_b64 s[2:3], s[54:55]
@@ -5400,25 +5162,25 @@ define amdgpu_kernel void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val
 ; VI-NEXT:    v_mov_b32_e32 v13, s49
 ; VI-NEXT:    v_mov_b32_e32 v14, s50
 ; VI-NEXT:    v_mov_b32_e32 v15, s51
-; VI-NEXT:    v_mov_b32_e32 v16, s8
-; VI-NEXT:    v_mov_b32_e32 v17, s9
-; VI-NEXT:    v_mov_b32_e32 v18, s10
-; VI-NEXT:    v_mov_b32_e32 v19, s11
-; VI-NEXT:    v_mov_b32_e32 v20, s12
-; VI-NEXT:    v_mov_b32_e32 v21, s13
-; VI-NEXT:    v_mov_b32_e32 v22, s14
-; VI-NEXT:    v_mov_b32_e32 v23, s15
-; VI-NEXT:    v_mov_b32_e32 v24, s16
-; VI-NEXT:    v_mov_b32_e32 v25, s17
-; VI-NEXT:    v_mov_b32_e32 v26, s18
-; VI-NEXT:    v_mov_b32_e32 v27, s19
-; VI-NEXT:    v_mov_b32_e32 v28, s20
-; VI-NEXT:    v_mov_b32_e32 v29, s21
-; VI-NEXT:    v_mov_b32_e32 v30, s22
-; VI-NEXT:    s_getpc_b64 s[4:5]
-; VI-NEXT:    s_add_u32 s4, s4, stack_passed_f64_arg@rel32@lo+4
-; VI-NEXT:    s_addc_u32 s5, s5, stack_passed_f64_arg@rel32@hi+12
-; VI-NEXT:    s_swappc_b64 s[30:31], s[4:5]
+; VI-NEXT:    v_mov_b32_e32 v16, s4
+; VI-NEXT:    v_mov_b32_e32 v17, s5
+; VI-NEXT:    v_mov_b32_e32 v18, s6
+; VI-NEXT:    v_mov_b32_e32 v19, s7
+; VI-NEXT:    v_mov_b32_e32 v20, s8
+; VI-NEXT:    v_mov_b32_e32 v21, s9
+; VI-NEXT:    v_mov_b32_e32 v22, s10
+; VI-NEXT:    v_mov_b32_e32 v23, s11
+; VI-NEXT:    v_mov_b32_e32 v24, s12
+; VI-NEXT:    v_mov_b32_e32 v25, s13
+; VI-NEXT:    v_mov_b32_e32 v26, s14
+; VI-NEXT:    v_mov_b32_e32 v27, s15
+; VI-NEXT:    v_mov_b32_e32 v28, s16
+; VI-NEXT:    v_mov_b32_e32 v29, s17
+; VI-NEXT:    v_mov_b32_e32 v30, s18
+; VI-NEXT:    s_getpc_b64 s[20:21]
+; VI-NEXT:    s_add_u32 s20, s20, stack_passed_f64_arg@rel32@lo+4
+; VI-NEXT:    s_addc_u32 s21, s21, stack_passed_f64_arg@rel32@hi+12
+; VI-NEXT:    s_swappc_b64 s[30:31], s[20:21]
 ; VI-NEXT:    s_endpgm
 ;
 ; CI-LABEL: stack_passed_arg_alignment_v32i32_f64:
@@ -5427,19 +5189,18 @@ define amdgpu_kernel void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val
 ; CI-NEXT:    s_mov_b32 s53, SCRATCH_RSRC_DWORD1
 ; CI-NEXT:    s_mov_b32 s54, -1
 ; CI-NEXT:    s_mov_b32 s55, 0xe8f000
-; CI-NEXT:    s_add_u32 s52, s52, s5
-; CI-NEXT:    s_load_dwordx16 s[8:23], s[2:3], 0x19
-; CI-NEXT:    s_load_dwordx2 s[4:5], s[2:3], 0x29
-; CI-NEXT:    s_load_dwordx16 s[36:51], s[2:3], 0x9
+; CI-NEXT:    s_add_u32 s52, s52, s3
+; CI-NEXT:    s_load_dwordx16 s[4:19], s[0:1], 0x19
+; CI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x29
+; CI-NEXT:    s_load_dwordx16 s[36:51], s[0:1], 0x9
 ; CI-NEXT:    s_mov_b32 s32, 0
 ; CI-NEXT:    s_addc_u32 s53, s53, 0
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
-; CI-NEXT:    v_mov_b32_e32 v0, s23
+; CI-NEXT:    v_mov_b32_e32 v0, s19
+; CI-NEXT:    v_mov_b32_e32 v1, s2
 ; CI-NEXT:    buffer_store_dword v0, off, s[52:55], s32
-; CI-NEXT:    v_mov_b32_e32 v0, s4
-; CI-NEXT:    buffer_store_dword v0, off, s[52:55], s32 offset:4
-; CI-NEXT:    v_mov_b32_e32 v0, s5
-; CI-NEXT:    s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT:    buffer_store_dword v1, off, s[52:55], s32 offset:4
+; CI-NEXT:    v_mov_b32_e32 v0, s3
 ; CI-NEXT:    s_mov_b64 s[0:1], s[52:53]
 ; CI-NEXT:    buffer_store_dword v0, off, s[52:55], s32 offset:8
 ; CI-NEXT:    s_mov_b64 s[2:3], s[54:55]
@@ -5459,25 +5220,25 @@ define amdgpu_kernel void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val
 ; CI-NEXT:    v_mov_b32_e32 v13, s49
 ; CI-NEXT:    v_mov_b32_e32 v14, s50
 ; CI-NEXT:    v_mov_b32_e32 v15, s51
-; CI-NEXT:    v_mov_b32_e32 v16, s8
-; CI-NEXT:    v_mov_b32_e32 v17, s9
-; CI-NEXT:    v_mov_b32_e32 v18, s10
-; CI-NEXT:    v_mov_b32_e32 v19, s11
-; CI-NEXT:    v_mov_b32_e32 v20, s12
-; CI-NEXT:    v_mov_b32_e32 v21, s13
-; CI-NEXT:    v_mov_b32_e32 v22, s14
-; CI-NEXT:    v_mov_b32_e32 v23, s15
-; CI-NEXT:    v_mov_b32_e32 v24, s16
-; CI-NEXT:    v_mov_b32_e32 v25, s17
-; CI-NEXT:    v_mov_b32_e32 v26, s18
-; CI-NEXT:    v_mov_b32_e32 v27, s19
-; CI-NEXT:    v_mov_b32_e32 v28, s20
-; CI-NEXT:    v_mov_b32_e32 v29, s21
-; CI-NEXT:    v_mov_b32_e32 v30, s22
-; CI-NEXT:    s_getpc_b64 s[4:5]
-; CI-NEXT:    s_add_u32 s4, s4, stack_passed_f64_arg@rel32@lo+4
-; CI-NEXT:    s_addc_u32 s5, s5, stack_passed_f64_arg@rel32@hi+12
-; CI-NEXT:    s_swappc_b64 s[30:31], s[4:5]
+; CI-NEXT:    v_mov_b32_e32 v16, s4
+; CI-NEXT:    v_mov_b32_e32 v17, s5
+; CI-NEXT:    v_mov_b32_e32 v18, s6
+; CI-NEXT:    v_mov_b32_e32 v19, s7
+; CI-NEXT:    v_mov_b32_e32 v20, s8
+; CI-NEXT:    v_mov_b32_e32 v21, s9
+; CI-NEXT:    v_mov_b32_e32 v22, s10
+; CI-NEXT:    v_mov_b32_e32 v23, s11
+; CI-NEXT:    v_mov_b32_e32 v24, s12
+; CI-NEXT:    v_mov_b32_e32 v25, s13
+; CI-NEXT:    v_mov_b32_e32 v26, s14
+; CI-NEXT:    v_mov_b32_e32 v27, s15
+; CI-NEXT:    v_mov_b32_e32 v28, s16
+; CI-NEXT:    v_mov_b32_e32 v29, s17
+; CI-NEXT:    v_mov_b32_e32 v30, s18
+; CI-NEXT:    s_getpc_b64 s[20:21]
+; CI-NEXT:    s_add_u32 s20, s20, stack_passed_f64_arg@rel32@lo+4
+; CI-NEXT:    s_addc_u32 s21, s21, stack_passed_f64_arg@rel32@hi+12
+; CI-NEXT:    s_swappc_b64 s[30:31], s[20:21]
 ; CI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: stack_passed_arg_alignment_v32i32_f64:
@@ -5486,19 +5247,18 @@ define amdgpu_kernel void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val
 ; GFX9-NEXT:    s_mov_b32 s53, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s54, -1
 ; GFX9-NEXT:    s_mov_b32 s55, 0xe00000
-; GFX9-NEXT:    s_add_u32 s52, s52, s5
-; GFX9-NEXT:    s_load_dwordx16 s[8:23], s[2:3], 0x64
-; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[2:3], 0xa4
-; GFX9-NEXT:    s_load_dwordx16 s[36:51], s[2:3], 0x24
+; GFX9-NEXT:    s_add_u32 s52, s52, s3
+; GFX9-NEXT:    s_load_dwordx16 s[4:19], s[0:1], 0x64
+; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xa4
+; GFX9-NEXT:    s_load_dwordx16 s[36:51], s[0:1], 0x24
 ; GFX9-NEXT:    s_mov_b32 s32, 0
 ; GFX9-NEXT:    s_addc_u32 s53, s53, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v0, s23
+; GFX9-NEXT:    v_mov_b32_e32 v0, s19
+; GFX9-NEXT:    v_mov_b32_e32 v1, s2
 ; GFX9-NEXT:    buffer_store_dword v0, off, s[52:55], s32
-; GFX9-NEXT:    v_mov_b32_e32 v0, s4
-; GFX9-NEXT:    buffer_store_dword v0, off, s[52:55], s32 offset:4
-; GFX9-NEXT:    v_mov_b32_e32 v0, s5
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
+; GFX9-NEXT:    buffer_store_dword v1, off, s[52:55], s32 offset:4
+; GFX9-NEXT:    v_mov_b32_e32 v0, s3
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[52:53]
 ; GFX9-NEXT:    buffer_store_dword v0, off, s[52:55], s32 offset:8
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[54:55]
@@ -5518,43 +5278,43 @@ define amdgpu_kernel void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val
 ; GFX9-NEXT:    v_mov_b32_e32 v13, s49
 ; GFX9-NEXT:    v_mov_b32_e32 v14, s50
 ; GFX9-NEXT:    v_mov_b32_e32 v15, s51
-; GFX9-NEXT:    v_mov_b32_e32 v16, s8
-; GFX9-NEXT:    v_mov_b32_e32 v17, s9
-; GFX9-NEXT:    v_mov_b32_e32 v18, s10
-; GFX9-NEXT:    v_mov_b32_e32 v19, s11
-; GFX9-NEXT:    v_mov_b32_e32 v20, s12
-; GFX9-NEXT:    v_mov_b32_e32 v21, s13
-; GFX9-NEXT:    v_mov_b32_e32 v22, s14
-; GFX9-NEXT:    v_mov_b32_e32 v23, s15
-; GFX9-NEXT:    v_mov_b32_e32 v24, s16
-; GFX9-NEXT:    v_mov_b32_e32 v25, s17
-; GFX9-NEXT:    v_mov_b32_e32 v26, s18
-; GFX9-NEXT:    v_mov_b32_e32 v27, s19
-; GFX9-NEXT:    v_mov_b32_e32 v28, s20
-; GFX9-NEXT:    v_mov_b32_e32 v29, s21
-; GFX9-NEXT:    v_mov_b32_e32 v30, s22
-; GFX9-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-NEXT:    s_add_u32 s4, s4, stack_passed_f64_arg@rel32@lo+4
-; GFX9-NEXT:    s_addc_u32 s5, s5, stack_passed_f64_arg@rel32@hi+12
-; GFX9-NEXT:    s_swappc_b64 s[30:31], s[4:5]
+; GFX9-NEXT:    v_mov_b32_e32 v16, s4
+; GFX9-NEXT:    v_mov_b32_e32 v17, s5
+; GFX9-NEXT:    v_mov_b32_e32 v18, s6
+; GFX9-NEXT:    v_mov_b32_e32 v19, s7
+; GFX9-NEXT:    v_mov_b32_e32 v20, s8
+; GFX9-NEXT:    v_mov_b32_e32 v21, s9
+; GFX9-NEXT:    v_mov_b32_e32 v22, s10
+; GFX9-NEXT:    v_mov_b32_e32 v23, s11
+; GFX9-NEXT:    v_mov_b32_e32 v24, s12
+; GFX9-NEXT:    v_mov_b32_e32 v25, s13
+; GFX9-NEXT:    v_mov_b32_e32 v26, s14
+; GFX9-NEXT:    v_mov_b32_e32 v27, s15
+; GFX9-NEXT:    v_mov_b32_e32 v28, s16
+; GFX9-NEXT:    v_mov_b32_e32 v29, s17
+; GFX9-NEXT:    v_mov_b32_e32 v30, s18
+; GFX9-NEXT:    s_getpc_b64 s[20:21]
+; GFX9-NEXT:    s_add_u32 s20, s20, stack_passed_f64_arg@rel32@lo+4
+; GFX9-NEXT:    s_addc_u32 s21, s21, stack_passed_f64_arg@rel32@hi+12
+; GFX9-NEXT:    s_swappc_b64 s[30:31], s[20:21]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: stack_passed_arg_alignment_v32i32_f64:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_clause 0x2
-; GFX11-NEXT:    s_load_b64 s[20:21], s[2:3], 0xa4
-; GFX11-NEXT:    s_load_b512 s[4:19], s[2:3], 0x64
-; GFX11-NEXT:    s_load_b512 s[36:51], s[2:3], 0x24
+; GFX11-NEXT:    s_load_b64 s[2:3], s[0:1], 0xa4
+; GFX11-NEXT:    s_load_b512 s[4:19], s[0:1], 0x64
+; GFX11-NEXT:    s_load_b512 s[36:51], s[0:1], 0x24
 ; GFX11-NEXT:    s_mov_b32 s32, 0
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_add_i32 s22, s32, 8
+; GFX11-NEXT:    s_add_i32 s20, s32, 8
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v0, s21 :: v_dual_mov_b32 v1, s20
+; GFX11-NEXT:    v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s2
 ; GFX11-NEXT:    v_mov_b32_e32 v2, s19
-; GFX11-NEXT:    s_add_i32 s19, s32, 4
+; GFX11-NEXT:    s_add_i32 s2, s32, 4
 ; GFX11-NEXT:    v_dual_mov_b32 v4, s40 :: v_dual_mov_b32 v7, s43
-; GFX11-NEXT:    scratch_store_b32 off, v0, s22
-; GFX11-NEXT:    scratch_store_b32 off, v1, s19
+; GFX11-NEXT:    scratch_store_b32 off, v0, s20
+; GFX11-NEXT:    scratch_store_b32 off, v1, s2
 ; GFX11-NEXT:    scratch_store_b32 off, v2, s32
 ; GFX11-NEXT:    v_dual_mov_b32 v0, s36 :: v_dual_mov_b32 v3, s39
 ; GFX11-NEXT:    v_dual_mov_b32 v1, s37 :: v_dual_mov_b32 v2, s38
@@ -5571,33 +5331,31 @@ define amdgpu_kernel void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val
 ; GFX11-NEXT:    v_dual_mov_b32 v27, s15 :: v_dual_mov_b32 v26, s14
 ; GFX11-NEXT:    v_dual_mov_b32 v29, s17 :: v_dual_mov_b32 v28, s16
 ; GFX11-NEXT:    v_mov_b32_e32 v30, s18
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, stack_passed_f64_arg@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, stack_passed_f64_arg@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-NEXT:    s_add_u32 s0, s0, stack_passed_f64_arg@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s1, s1, stack_passed_f64_arg@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: stack_passed_arg_alignment_v32i32_f64:
 ; HSA:       ; %bb.0: ; %entry
-; HSA-NEXT:    s_add_i32 s8, s8, s11
-; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s8, 8
-; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s9
-; HSA-NEXT:    s_add_u32 s0, s0, s11
-; HSA-NEXT:    s_load_dwordx16 s[8:23], s[6:7], 0x40
-; HSA-NEXT:    s_load_dwordx2 s[24:25], s[6:7], 0x80
-; HSA-NEXT:    s_load_dwordx16 s[36:51], s[6:7], 0x0
+; HSA-NEXT:    s_add_i32 s6, s6, s9
+; HSA-NEXT:    s_lshr_b32 flat_scratch_hi, s6, 8
+; HSA-NEXT:    s_mov_b32 flat_scratch_lo, s7
+; HSA-NEXT:    s_add_u32 s0, s0, s9
+; HSA-NEXT:    s_load_dwordx16 s[8:23], s[4:5], 0x40
+; HSA-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x80
+; HSA-NEXT:    s_load_dwordx16 s[36:51], s[4:5], 0x0
 ; HSA-NEXT:    s_mov_b32 s32, 0
 ; HSA-NEXT:    s_addc_u32 s1, s1, 0
 ; HSA-NEXT:    s_waitcnt lgkmcnt(0)
 ; HSA-NEXT:    v_mov_b32_e32 v0, s23
+; HSA-NEXT:    v_mov_b32_e32 v1, s6
 ; HSA-NEXT:    buffer_store_dword v0, off, s[0:3], s32
-; HSA-NEXT:    v_mov_b32_e32 v0, s24
-; HSA-NEXT:    buffer_store_dword v0, off, s[0:3], s32 offset:4
-; HSA-NEXT:    v_mov_b32_e32 v0, s25
+; HSA-NEXT:    buffer_store_dword v1, off, s[0:3], s32 offset:4
+; HSA-NEXT:    v_mov_b32_e32 v0, s7
 ; HSA-NEXT:    buffer_store_dword v0, off, s[0:3], s32 offset:8
-; HSA-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; HSA-NEXT:    v_mov_b32_e32 v0, s36
 ; HSA-NEXT:    v_mov_b32_e32 v1, s37
 ; HSA-NEXT:    v_mov_b32_e32 v2, s38
@@ -5629,10 +5387,10 @@ define amdgpu_kernel void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val
 ; HSA-NEXT:    v_mov_b32_e32 v28, s20
 ; HSA-NEXT:    v_mov_b32_e32 v29, s21
 ; HSA-NEXT:    v_mov_b32_e32 v30, s22
-; HSA-NEXT:    s_getpc_b64 s[24:25]
-; HSA-NEXT:    s_add_u32 s24, s24, stack_passed_f64_arg@rel32@lo+4
-; HSA-NEXT:    s_addc_u32 s25, s25, stack_passed_f64_arg@rel32@hi+12
-; HSA-NEXT:    s_swappc_b64 s[30:31], s[24:25]
+; HSA-NEXT:    s_getpc_b64 s[4:5]
+; HSA-NEXT:    s_add_u32 s4, s4, stack_passed_f64_arg@rel32@lo+4
+; HSA-NEXT:    s_addc_u32 s5, s5, stack_passed_f64_arg@rel32@hi+12
+; HSA-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; HSA-NEXT:    s_endpgm
 entry:
   call void @stack_passed_f64_arg(<32 x i32> %val, double %tmp)
@@ -7258,3 +7016,6 @@ declare hidden void @external_void_func_8xv5f32(<5 x float>, <5 x float>, <5 x f
 attributes #0 = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }
 attributes #1 = { nounwind readnone }
 attributes #2 = { nounwind noinline }
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"amdgpu_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/call-waitcnt.ll b/llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
index c0ba343d1dd3..616e5f00fc1e 100644
--- a/llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
@@ -5,20 +5,19 @@
 define amdgpu_kernel void @call_memory_arg_load(ptr addrspace(3) %ptr, i32) #0 {
 ; GCN-LABEL: call_memory_arg_load:
 ; GCN:       ; %bb.0:
-; GCN-NEXT:    s_load_dword s6, s[6:7], 0x0
-; GCN-NEXT:    s_add_u32 flat_scratch_lo, s8, s11
-; GCN-NEXT:    s_addc_u32 flat_scratch_hi, s9, 0
-; GCN-NEXT:    s_add_u32 s0, s0, s11
+; GCN-NEXT:    s_load_dword s4, s[4:5], 0x0
+; GCN-NEXT:    s_add_u32 flat_scratch_lo, s6, s9
+; GCN-NEXT:    s_addc_u32 flat_scratch_hi, s7, 0
+; GCN-NEXT:    s_add_u32 s0, s0, s9
 ; GCN-NEXT:    s_addc_u32 s1, s1, 0
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v0, s6
+; GCN-NEXT:    v_mov_b32_e32 v0, s4
 ; GCN-NEXT:    ds_read_b32 v0, v0
-; GCN-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; GCN-NEXT:    s_mov_b32 s32, 0
-; GCN-NEXT:    s_getpc_b64 s[8:9]
-; GCN-NEXT:    s_add_u32 s8, s8, func@rel32@lo+4
-; GCN-NEXT:    s_addc_u32 s9, s9, func@rel32@hi+12
-; GCN-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; GCN-NEXT:    s_getpc_b64 s[4:5]
+; GCN-NEXT:    s_add_u32 s4, s4, func@rel32@lo+4
+; GCN-NEXT:    s_addc_u32 s5, s5, func@rel32@hi+12
+; GCN-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; GCN-NEXT:    s_endpgm
   %vgpr = load volatile i32, ptr addrspace(3) %ptr
   call void @func(i32 %vgpr)
@@ -29,21 +28,20 @@ define amdgpu_kernel void @call_memory_arg_load(ptr addrspace(3) %ptr, i32) #0 {
 define amdgpu_kernel void @call_memory_no_dep(ptr addrspace(1) %ptr, i32) #0 {
 ; GCN-LABEL: call_memory_no_dep:
 ; GCN:       ; %bb.0:
-; GCN-NEXT:    s_load_dwordx2 s[6:7], s[6:7], 0x0
-; GCN-NEXT:    s_add_u32 flat_scratch_lo, s8, s11
-; GCN-NEXT:    s_addc_u32 flat_scratch_hi, s9, 0
-; GCN-NEXT:    s_add_u32 s0, s0, s11
+; GCN-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x0
+; GCN-NEXT:    s_add_u32 flat_scratch_lo, s6, s9
+; GCN-NEXT:    s_addc_u32 flat_scratch_hi, s7, 0
+; GCN-NEXT:    s_add_u32 s0, s0, s9
 ; GCN-NEXT:    v_mov_b32_e32 v0, 0
 ; GCN-NEXT:    s_addc_u32 s1, s1, 0
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    global_store_dword v0, v0, s[6:7]
-; GCN-NEXT:    s_mov_b64 s[6:7], s[4:5]
+; GCN-NEXT:    global_store_dword v0, v0, s[4:5]
 ; GCN-NEXT:    v_mov_b32_e32 v0, 0
 ; GCN-NEXT:    s_mov_b32 s32, 0
-; GCN-NEXT:    s_getpc_b64 s[8:9]
-; GCN-NEXT:    s_add_u32 s8, s8, func@rel32@lo+4
-; GCN-NEXT:    s_addc_u32 s9, s9, func@rel32@hi+12
-; GCN-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; GCN-NEXT:    s_getpc_b64 s[6:7]
+; GCN-NEXT:    s_add_u32 s6, s6, func@rel32@lo+4
+; GCN-NEXT:    s_addc_u32 s7, s7, func@rel32@hi+12
+; GCN-NEXT:    s_swappc_b64 s[30:31], s[6:7]
 ; GCN-NEXT:    s_endpgm
   store i32 0, ptr addrspace(1) %ptr
   call void @func(i32 0)
@@ -54,19 +52,18 @@ define amdgpu_kernel void @call_memory_no_dep(ptr addrspace(1) %ptr, i32) #0 {
 define amdgpu_kernel void @call_no_wait_after_call(ptr addrspace(1) %ptr, i32) #0 {
 ; GCN-LABEL: call_no_wait_after_call:
 ; GCN:       ; %bb.0:
-; GCN-NEXT:    s_add_u32 flat_scratch_lo, s8, s11
-; GCN-NEXT:    s_load_dwordx2 s[34:35], s[6:7], 0x0
-; GCN-NEXT:    s_addc_u32 flat_scratch_hi, s9, 0
-; GCN-NEXT:    s_add_u32 s0, s0, s11
+; GCN-NEXT:    s_add_u32 flat_scratch_lo, s6, s9
+; GCN-NEXT:    s_load_dwordx2 s[34:35], s[4:5], 0x0
+; GCN-NEXT:    s_addc_u32 flat_scratch_hi, s7, 0
+; GCN-NEXT:    s_add_u32 s0, s0, s9
 ; GCN-NEXT:    s_addc_u32 s1, s1, 0
-; GCN-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; GCN-NEXT:    v_mov_b32_e32 v0, 0
 ; GCN-NEXT:    s_mov_b32 s32, 0
-; GCN-NEXT:    s_getpc_b64 s[8:9]
-; GCN-NEXT:    s_add_u32 s8, s8, func@rel32@lo+4
-; GCN-NEXT:    s_addc_u32 s9, s9, func@rel32@hi+12
+; GCN-NEXT:    s_getpc_b64 s[4:5]
+; GCN-NEXT:    s_add_u32 s4, s4, func@rel32@lo+4
+; GCN-NEXT:    s_addc_u32 s5, s5, func@rel32@hi+12
 ; GCN-NEXT:    v_mov_b32_e32 v40, 0
-; GCN-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; GCN-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; GCN-NEXT:    global_store_dword v40, v40, s[34:35]
 ; GCN-NEXT:    s_endpgm
   call void @func(i32 0)
@@ -77,19 +74,18 @@ define amdgpu_kernel void @call_no_wait_after_call(ptr addrspace(1) %ptr, i32) #
 define amdgpu_kernel void @call_no_wait_after_call_return_val(ptr addrspace(1) %ptr, i32) #0 {
 ; GCN-LABEL: call_no_wait_after_call_return_val:
 ; GCN:       ; %bb.0:
-; GCN-NEXT:    s_add_u32 flat_scratch_lo, s8, s11
-; GCN-NEXT:    s_load_dwordx2 s[34:35], s[6:7], 0x0
-; GCN-NEXT:    s_addc_u32 flat_scratch_hi, s9, 0
-; GCN-NEXT:    s_add_u32 s0, s0, s11
+; GCN-NEXT:    s_add_u32 flat_scratch_lo, s6, s9
+; GCN-NEXT:    s_load_dwordx2 s[34:35], s[4:5], 0x0
+; GCN-NEXT:    s_addc_u32 flat_scratch_hi, s7, 0
+; GCN-NEXT:    s_add_u32 s0, s0, s9
 ; GCN-NEXT:    s_addc_u32 s1, s1, 0
-; GCN-NEXT:    s_mov_b64 s[6:7], s[4:5]
 ; GCN-NEXT:    v_mov_b32_e32 v0, 0
 ; GCN-NEXT:    s_mov_b32 s32, 0
-; GCN-NEXT:    s_getpc_b64 s[8:9]
-; GCN-NEXT:    s_add_u32 s8, s8, func.return@rel32@lo+4
-; GCN-NEXT:    s_addc_u32 s9, s9, func.return@rel32@hi+12
+; GCN-NEXT:    s_getpc_b64 s[4:5]
+; GCN-NEXT:    s_add_u32 s4, s4, func.return@rel32@lo+4
+; GCN-NEXT:    s_addc_u32 s5, s5, func.return@rel32@hi+12
 ; GCN-NEXT:    v_mov_b32_e32 v40, 0
-; GCN-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; GCN-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; GCN-NEXT:    global_store_dword v40, v0, s[34:35]
 ; GCN-NEXT:    s_endpgm
   %rv = call i32 @func.return(i32 0)
@@ -101,19 +97,18 @@ define amdgpu_kernel void @call_no_wait_after_call_return_val(ptr addrspace(1) %
 define amdgpu_kernel void @call_got_load(ptr addrspace(1) %ptr, i32) #0 {
 ; GCN-LABEL: call_got_load:
 ; GCN:       ; %bb.0:
-; GCN-NEXT:    s_add_u32 flat_scratch_lo, s8, s11
-; GCN-NEXT:    s_addc_u32 flat_scratch_hi, s9, 0
-; GCN-NEXT:    s_add_u32 s0, s0, s11
+; GCN-NEXT:    s_add_u32 flat_scratch_lo, s6, s9
+; GCN-NEXT:    s_addc_u32 flat_scratch_hi, s7, 0
+; GCN-NEXT:    s_add_u32 s0, s0, s9
 ; GCN-NEXT:    s_addc_u32 s1, s1, 0
-; GCN-NEXT:    s_getpc_b64 s[6:7]
-; GCN-NEXT:    s_add_u32 s6, s6, got.func@gotpcrel32@lo+4
-; GCN-NEXT:    s_addc_u32 s7, s7, got.func@gotpcrel32@hi+12
-; GCN-NEXT:    s_load_dwordx2 s[8:9], s[6:7], 0x0
-; GCN-NEXT:    s_mov_b64 s[6:7], s[4:5]
+; GCN-NEXT:    s_getpc_b64 s[4:5]
+; GCN-NEXT:    s_add_u32 s4, s4, got.func@gotpcrel32@lo+4
+; GCN-NEXT:    s_addc_u32 s5, s5, got.func@gotpcrel32@hi+12
+; GCN-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x0
 ; GCN-NEXT:    v_mov_b32_e32 v0, 0
 ; GCN-NEXT:    s_mov_b32 s32, 0
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_swappc_b64 s[30:31], s[8:9]
+; GCN-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; GCN-NEXT:    s_endpgm
   call void @got.func(i32 0)
   ret void
@@ -155,3 +150,6 @@ declare hidden i32 @func.return(i32) #0
 declare void @got.func(i32) #0
 
 attributes #0 = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"amdgpu_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll b/llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
index 9eed9b5bb26c..e1828042752e 100644
--- a/llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
+++ b/llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
@@ -28,15 +28,15 @@ define hidden void @use_queue_ptr() #1 {
 }
 
 ; GCN-LABEL: {{^}}kern_indirect_use_queue_ptr:
-; GCN: s_mov_b64 s[6:7], s[4:5]
-; GCN: .amdhsa_user_sgpr_queue_ptr 1
+; GCN: s_swappc_b64 s[30:31], s[4:5]
+; GCN: .amdhsa_user_sgpr_queue_ptr 0
 define amdgpu_kernel void @kern_indirect_use_queue_ptr(i32) #1 {
   call void @use_queue_ptr()
   ret void
 }
 
 ; GCN-LABEL: {{^}}use_queue_ptr_addrspacecast:
-; CIVI: s_load_dword [[APERTURE_LOAD:s[0-9]+]], s[6:7], 0x10
+; CIVI: s_load_dword [[APERTURE_LOAD:s[0-9]+]], s[4:5], 0x0
 ; CIVI: v_mov_b32_e32 v[[LO:[0-9]+]], 16
 ; CIVI-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[APERTURE_LOAD]]
 
@@ -52,8 +52,8 @@ define hidden void @use_queue_ptr_addrspacecast() #1 {
 }
 
 ; GCN-LABEL: {{^}}kern_indirect_use_queue_ptr_addrspacecast:
-; CIVI: s_mov_b64 s[6:7], s[4:5]
-; CIVI: .amdhsa_user_sgpr_queue_ptr 1
+; CIVI: s_swappc_b64 s[30:31], s[4:5]
+; CIVI: .amdhsa_user_sgpr_queue_ptr 0
 
 ; GFX9-NOT: s_mov_b64 s[6:7]
 ; GFX9: .amdhsa_user_sgpr_queue_ptr 0
@@ -463,15 +463,12 @@ define hidden void @use_every_sgpr_input() #1 {
 }
 
 ; GCN-LABEL: {{^}}kern_indirect_use_every_sgpr_input:
-; GCN: s_mov_b32 s13, s15
-; GCN: s_mov_b32 s12, s14
-; GCN: s_mov_b32 s14, s16
 ; GCN: s_mov_b32 s32, 0
 ; GCN: s_swappc_b64
 
 ; GCN: .amdhsa_user_sgpr_private_segment_buffer 1
 ; GCN: .amdhsa_user_sgpr_dispatch_ptr 1
-; GCN: .amdhsa_user_sgpr_queue_ptr 1
+; GCN: .amdhsa_user_sgpr_queue_ptr 0
 ; GCN: .amdhsa_user_sgpr_kernarg_segment_ptr 1
 ; GCN: .amdhsa_user_sgpr_dispatch_id 1
 ; GCN: .amdhsa_user_sgpr_flat_scratch_init 1
@@ -490,14 +487,13 @@ define amdgpu_kernel void @kern_indirect_use_every_sgpr_input(i8) #1 {
 ; We have to pass the kernarg segment, but there are no kernel
 ; arguments so null is passed.
 ; GCN-LABEL: {{^}}kern_indirect_use_every_sgpr_input_no_kernargs:
-; GCN: s_mov_b64 s[10:11], s[8:9]
-; GCN: s_mov_b64 s[8:9], 0{{$}}
+; GCN: s_mov_b64 s[10:11], s[6:7]
 ; GCN: s_mov_b32 s32, 0
 ; GCN: s_swappc_b64
 
 ; GCN: .amdhsa_user_sgpr_private_segment_buffer 1
 ; GCN: .amdhsa_user_sgpr_dispatch_ptr 1
-; GCN: .amdhsa_user_sgpr_queue_ptr 1
+; GCN: .amdhsa_user_sgpr_queue_ptr 0
 ; GCN: .amdhsa_user_sgpr_kernarg_segment_ptr 0
 ; GCN: .amdhsa_user_sgpr_dispatch_id 1
 ; GCN: .amdhsa_user_sgpr_flat_scratch_init 1
@@ -584,3 +580,6 @@ declare noalias ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() #0
 attributes #0 = { nounwind readnone speculatable }
 attributes #1 = { nounwind noinline }
 attributes #2 = { nounwind noinline "amdgpu-implicitarg-num-bytes"="0" }
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"amdgpu_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/cc-update.ll b/llvm/test/CodeGen/AMDGPU/cc-update.ll
index 8a69069d75e2..ca09163b20af 100644
--- a/llvm/test/CodeGen/AMDGPU/cc-update.ll
+++ b/llvm/test/CodeGen/AMDGPU/cc-update.ll
@@ -67,80 +67,76 @@ entry:
 define amdgpu_kernel void @test_kern_call() local_unnamed_addr #0 {
 ; GFX803-LABEL: test_kern_call:
 ; GFX803:       ; %bb.0: ; %entry
-; GFX803-NEXT:    s_add_i32 s12, s12, s17
-; GFX803-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX803-NEXT:    s_add_i32 s10, s10, s15
+; GFX803-NEXT:    s_lshr_b32 flat_scratch_hi, s10, 8
 ; GFX803-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX803-NEXT:    s_add_u32 s0, s0, s17
+; GFX803-NEXT:    s_add_u32 s0, s0, s15
 ; GFX803-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX803-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX803-NEXT:    s_mov_b32 flat_scratch_lo, s13
+; GFX803-NEXT:    s_mov_b32 flat_scratch_lo, s11
 ; GFX803-NEXT:    s_addc_u32 s1, s1, 0
-; GFX803-NEXT:    s_mov_b32 s13, s15
-; GFX803-NEXT:    s_mov_b32 s12, s14
+; GFX803-NEXT:    s_mov_b64 s[10:11], s[8:9]
 ; GFX803-NEXT:    v_or_b32_e32 v31, v0, v2
-; GFX803-NEXT:    s_mov_b32 s14, s16
+; GFX803-NEXT:    s_mov_b64 s[8:9], s[6:7]
 ; GFX803-NEXT:    s_mov_b32 s32, 0
-; GFX803-NEXT:    s_getpc_b64 s[18:19]
-; GFX803-NEXT:    s_add_u32 s18, s18, ex@rel32@lo+4
-; GFX803-NEXT:    s_addc_u32 s19, s19, ex@rel32@hi+12
-; GFX803-NEXT:    s_swappc_b64 s[30:31], s[18:19]
+; GFX803-NEXT:    s_getpc_b64 s[16:17]
+; GFX803-NEXT:    s_add_u32 s16, s16, ex@rel32@lo+4
+; GFX803-NEXT:    s_addc_u32 s17, s17, ex@rel32@hi+12
+; GFX803-NEXT:    s_swappc_b64 s[30:31], s[16:17]
 ; GFX803-NEXT:    s_endpgm
 ;
 ; GFX900-LABEL: test_kern_call:
 ; GFX900:       ; %bb.0: ; %entry
-; GFX900-NEXT:    s_add_u32 flat_scratch_lo, s12, s17
-; GFX900-NEXT:    s_addc_u32 flat_scratch_hi, s13, 0
-; GFX900-NEXT:    s_add_u32 s0, s0, s17
+; GFX900-NEXT:    s_add_u32 flat_scratch_lo, s10, s15
+; GFX900-NEXT:    s_addc_u32 flat_scratch_hi, s11, 0
+; GFX900-NEXT:    s_add_u32 s0, s0, s15
 ; GFX900-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX900-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX900-NEXT:    s_addc_u32 s1, s1, 0
-; GFX900-NEXT:    s_mov_b32 s13, s15
-; GFX900-NEXT:    s_mov_b32 s12, s14
+; GFX900-NEXT:    s_mov_b64 s[10:11], s[8:9]
 ; GFX900-NEXT:    v_or3_b32 v31, v0, v1, v2
-; GFX900-NEXT:    s_mov_b32 s14, s16
+; GFX900-NEXT:    s_mov_b64 s[8:9], s[6:7]
 ; GFX900-NEXT:    s_mov_b32 s32, 0
-; GFX900-NEXT:    s_getpc_b64 s[18:19]
-; GFX900-NEXT:    s_add_u32 s18, s18, ex@rel32@lo+4
-; GFX900-NEXT:    s_addc_u32 s19, s19, ex@rel32@hi+12
-; GFX900-NEXT:    s_swappc_b64 s[30:31], s[18:19]
+; GFX900-NEXT:    s_getpc_b64 s[16:17]
+; GFX900-NEXT:    s_add_u32 s16, s16, ex@rel32@lo+4
+; GFX900-NEXT:    s_addc_u32 s17, s17, ex@rel32@hi+12
+; GFX900-NEXT:    s_swappc_b64 s[30:31], s[16:17]
 ; GFX900-NEXT:    s_endpgm
 ;
 ; GFX1010-LABEL: test_kern_call:
 ; GFX1010:       ; %bb.0: ; %entry
-; GFX1010-NEXT:    s_add_u32 s12, s12, s17
+; GFX1010-NEXT:    s_add_u32 s10, s10, s15
 ; GFX1010-NEXT:    s_mov_b32 s32, 0
-; GFX1010-NEXT:    s_addc_u32 s13, s13, 0
-; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12
-; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13
+; GFX1010-NEXT:    s_addc_u32 s11, s11, 0
+; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s10
+; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s11
 ; GFX1010-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX1010-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1010-NEXT:    s_add_u32 s0, s0, s17
+; GFX1010-NEXT:    s_add_u32 s0, s0, s15
 ; GFX1010-NEXT:    s_addc_u32 s1, s1, 0
-; GFX1010-NEXT:    s_mov_b32 s13, s15
-; GFX1010-NEXT:    s_mov_b32 s12, s14
+; GFX1010-NEXT:    s_mov_b64 s[10:11], s[8:9]
+; GFX1010-NEXT:    s_mov_b64 s[8:9], s[6:7]
 ; GFX1010-NEXT:    v_or3_b32 v31, v0, v1, v2
-; GFX1010-NEXT:    s_mov_b32 s14, s16
-; GFX1010-NEXT:    s_getpc_b64 s[18:19]
-; GFX1010-NEXT:    s_add_u32 s18, s18, ex@rel32@lo+4
-; GFX1010-NEXT:    s_addc_u32 s19, s19, ex@rel32@hi+12
-; GFX1010-NEXT:    s_swappc_b64 s[30:31], s[18:19]
+; GFX1010-NEXT:    s_getpc_b64 s[16:17]
+; GFX1010-NEXT:    s_add_u32 s16, s16, ex@rel32@lo+4
+; GFX1010-NEXT:    s_addc_u32 s17, s17, ex@rel32@hi+12
+; GFX1010-NEXT:    s_swappc_b64 s[30:31], s[16:17]
 ; GFX1010-NEXT:    s_endpgm
 ;
 ; GFX1100-LABEL: test_kern_call:
 ; GFX1100:       ; %bb.0: ; %entry
 ; GFX1100-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1100-NEXT:    s_mov_b32 s12, s13
-; GFX1100-NEXT:    s_mov_b64 s[10:11], s[6:7]
-; GFX1100-NEXT:    s_mov_b64 s[8:9], s[4:5]
+; GFX1100-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1100-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1100-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1100-NEXT:    s_mov_b64 s[8:9], s[2:3]
 ; GFX1100-NEXT:    s_mov_b32 s13, s14
 ; GFX1100-NEXT:    s_mov_b32 s14, s15
 ; GFX1100-NEXT:    s_mov_b32 s32, 0
-; GFX1100-NEXT:    s_getpc_b64 s[16:17]
-; GFX1100-NEXT:    s_add_u32 s16, s16, ex@rel32@lo+4
-; GFX1100-NEXT:    s_addc_u32 s17, s17, ex@rel32@hi+12
-; GFX1100-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1100-NEXT:    s_getpc_b64 s[6:7]
+; GFX1100-NEXT:    s_add_u32 s6, s6, ex@rel32@lo+4
+; GFX1100-NEXT:    s_addc_u32 s7, s7, ex@rel32@hi+12
+; GFX1100-NEXT:    s_swappc_b64 s[30:31], s[6:7]
 ; GFX1100-NEXT:    s_endpgm
 
 entry:
@@ -151,72 +147,69 @@ entry:
 define amdgpu_kernel void @test_kern_stack_and_call() local_unnamed_addr #0 {
 ; GFX803-LABEL: test_kern_stack_and_call:
 ; GFX803:       ; %bb.0: ; %entry
-; GFX803-NEXT:    s_add_i32 s12, s12, s17
-; GFX803-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX803-NEXT:    s_add_i32 s10, s10, s15
+; GFX803-NEXT:    s_lshr_b32 flat_scratch_hi, s10, 8
 ; GFX803-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX803-NEXT:    s_add_u32 s0, s0, s17
+; GFX803-NEXT:    s_add_u32 s0, s0, s15
 ; GFX803-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX803-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX803-NEXT:    s_mov_b32 flat_scratch_lo, s13
+; GFX803-NEXT:    s_mov_b32 flat_scratch_lo, s11
 ; GFX803-NEXT:    s_addc_u32 s1, s1, 0
-; GFX803-NEXT:    s_mov_b32 s13, s15
-; GFX803-NEXT:    s_mov_b32 s12, s14
+; GFX803-NEXT:    s_mov_b64 s[10:11], s[8:9]
 ; GFX803-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX803-NEXT:    v_or_b32_e32 v31, v0, v2
-; GFX803-NEXT:    s_mov_b32 s14, s16
+; GFX803-NEXT:    s_mov_b64 s[8:9], s[6:7]
 ; GFX803-NEXT:    s_movk_i32 s32, 0x400
 ; GFX803-NEXT:    buffer_store_dword v3, off, s[0:3], 0 offset:4
 ; GFX803-NEXT:    s_waitcnt vmcnt(0)
-; GFX803-NEXT:    s_getpc_b64 s[18:19]
-; GFX803-NEXT:    s_add_u32 s18, s18, ex@rel32@lo+4
-; GFX803-NEXT:    s_addc_u32 s19, s19, ex@rel32@hi+12
-; GFX803-NEXT:    s_swappc_b64 s[30:31], s[18:19]
+; GFX803-NEXT:    s_getpc_b64 s[16:17]
+; GFX803-NEXT:    s_add_u32 s16, s16, ex@rel32@lo+4
+; GFX803-NEXT:    s_addc_u32 s17, s17, ex@rel32@hi+12
+; GFX803-NEXT:    s_swappc_b64 s[30:31], s[16:17]
 ; GFX803-NEXT:    s_endpgm
 ;
 ; GFX900-LABEL: test_kern_stack_and_call:
 ; GFX900:       ; %bb.0: ; %entry
-; GFX900-NEXT:    s_add_u32 flat_scratch_lo, s12, s17
-; GFX900-NEXT:    s_addc_u32 flat_scratch_hi, s13, 0
-; GFX900-NEXT:    s_add_u32 s0, s0, s17
+; GFX900-NEXT:    s_add_u32 flat_scratch_lo, s10, s15
+; GFX900-NEXT:    s_addc_u32 flat_scratch_hi, s11, 0
+; GFX900-NEXT:    s_add_u32 s0, s0, s15
 ; GFX900-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX900-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX900-NEXT:    s_addc_u32 s1, s1, 0
-; GFX900-NEXT:    s_mov_b32 s13, s15
-; GFX900-NEXT:    s_mov_b32 s12, s14
+; GFX900-NEXT:    s_mov_b64 s[10:11], s[8:9]
 ; GFX900-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX900-NEXT:    v_or3_b32 v31, v0, v1, v2
-; GFX900-NEXT:    s_mov_b32 s14, s16
+; GFX900-NEXT:    s_mov_b64 s[8:9], s[6:7]
 ; GFX900-NEXT:    s_movk_i32 s32, 0x400
 ; GFX900-NEXT:    buffer_store_dword v3, off, s[0:3], 0 offset:4
 ; GFX900-NEXT:    s_waitcnt vmcnt(0)
-; GFX900-NEXT:    s_getpc_b64 s[18:19]
-; GFX900-NEXT:    s_add_u32 s18, s18, ex@rel32@lo+4
-; GFX900-NEXT:    s_addc_u32 s19, s19, ex@rel32@hi+12
-; GFX900-NEXT:    s_swappc_b64 s[30:31], s[18:19]
+; GFX900-NEXT:    s_getpc_b64 s[16:17]
+; GFX900-NEXT:    s_add_u32 s16, s16, ex@rel32@lo+4
+; GFX900-NEXT:    s_addc_u32 s17, s17, ex@rel32@hi+12
+; GFX900-NEXT:    s_swappc_b64 s[30:31], s[16:17]
 ; GFX900-NEXT:    s_endpgm
 ;
 ; GFX1010-LABEL: test_kern_stack_and_call:
 ; GFX1010:       ; %bb.0: ; %entry
-; GFX1010-NEXT:    s_add_u32 s12, s12, s17
+; GFX1010-NEXT:    s_add_u32 s10, s10, s15
 ; GFX1010-NEXT:    s_movk_i32 s32, 0x200
-; GFX1010-NEXT:    s_addc_u32 s13, s13, 0
-; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12
-; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13
+; GFX1010-NEXT:    s_addc_u32 s11, s11, 0
+; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s10
+; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s11
 ; GFX1010-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX1010-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX1010-NEXT:    v_mov_b32_e32 v3, 0
-; GFX1010-NEXT:    s_add_u32 s0, s0, s17
+; GFX1010-NEXT:    s_add_u32 s0, s0, s15
 ; GFX1010-NEXT:    s_addc_u32 s1, s1, 0
-; GFX1010-NEXT:    s_mov_b32 s13, s15
+; GFX1010-NEXT:    s_mov_b64 s[10:11], s[8:9]
 ; GFX1010-NEXT:    v_or3_b32 v31, v0, v1, v2
-; GFX1010-NEXT:    s_mov_b32 s12, s14
-; GFX1010-NEXT:    s_mov_b32 s14, s16
+; GFX1010-NEXT:    s_mov_b64 s[8:9], s[6:7]
 ; GFX1010-NEXT:    buffer_store_dword v3, off, s[0:3], 0 offset:4
 ; GFX1010-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX1010-NEXT:    s_getpc_b64 s[18:19]
-; GFX1010-NEXT:    s_add_u32 s18, s18, ex@rel32@lo+4
-; GFX1010-NEXT:    s_addc_u32 s19, s19, ex@rel32@hi+12
-; GFX1010-NEXT:    s_swappc_b64 s[30:31], s[18:19]
+; GFX1010-NEXT:    s_getpc_b64 s[16:17]
+; GFX1010-NEXT:    s_add_u32 s16, s16, ex@rel32@lo+4
+; GFX1010-NEXT:    s_addc_u32 s17, s17, ex@rel32@hi+12
+; GFX1010-NEXT:    s_swappc_b64 s[30:31], s[16:17]
 ; GFX1010-NEXT:    s_endpgm
 ;
 ; GFX1100-LABEL: test_kern_stack_and_call:
@@ -224,19 +217,18 @@ define amdgpu_kernel void @test_kern_stack_and_call() local_unnamed_addr #0 {
 ; GFX1100-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1100-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1100-NEXT:    s_mov_b32 s12, s13
-; GFX1100-NEXT:    s_mov_b64 s[10:11], s[6:7]
-; GFX1100-NEXT:    s_mov_b64 s[8:9], s[4:5]
+; GFX1100-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1100-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1100-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1100-NEXT:    s_mov_b64 s[8:9], s[2:3]
 ; GFX1100-NEXT:    s_mov_b32 s13, s14
 ; GFX1100-NEXT:    s_mov_b32 s14, s15
 ; GFX1100-NEXT:    s_mov_b32 s32, 16
 ; GFX1100-NEXT:    scratch_store_b32 off, v1, off offset:4 dlc
 ; GFX1100-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX1100-NEXT:    s_getpc_b64 s[16:17]
-; GFX1100-NEXT:    s_add_u32 s16, s16, ex@rel32@lo+4
-; GFX1100-NEXT:    s_addc_u32 s17, s17, ex@rel32@hi+12
-; GFX1100-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1100-NEXT:    s_getpc_b64 s[6:7]
+; GFX1100-NEXT:    s_add_u32 s6, s6, ex@rel32@lo+4
+; GFX1100-NEXT:    s_addc_u32 s7, s7, ex@rel32@hi+12
+; GFX1100-NEXT:    s_swappc_b64 s[30:31], s[6:7]
 ; GFX1100-NEXT:    s_endpgm
 
 entry:
@@ -318,84 +310,80 @@ entry:
 define amdgpu_kernel void @test_force_fp_kern_call() local_unnamed_addr #2 {
 ; GFX803-LABEL: test_force_fp_kern_call:
 ; GFX803:       ; %bb.0: ; %entry
-; GFX803-NEXT:    s_add_i32 s12, s12, s17
-; GFX803-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX803-NEXT:    s_add_i32 s10, s10, s15
+; GFX803-NEXT:    s_lshr_b32 flat_scratch_hi, s10, 8
 ; GFX803-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX803-NEXT:    s_add_u32 s0, s0, s17
+; GFX803-NEXT:    s_add_u32 s0, s0, s15
 ; GFX803-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX803-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX803-NEXT:    s_mov_b32 flat_scratch_lo, s13
+; GFX803-NEXT:    s_mov_b32 flat_scratch_lo, s11
 ; GFX803-NEXT:    s_addc_u32 s1, s1, 0
-; GFX803-NEXT:    s_mov_b32 s13, s15
-; GFX803-NEXT:    s_mov_b32 s12, s14
+; GFX803-NEXT:    s_mov_b64 s[10:11], s[8:9]
 ; GFX803-NEXT:    v_or_b32_e32 v31, v0, v2
-; GFX803-NEXT:    s_mov_b32 s14, s16
+; GFX803-NEXT:    s_mov_b64 s[8:9], s[6:7]
 ; GFX803-NEXT:    s_mov_b32 s32, 0
 ; GFX803-NEXT:    s_mov_b32 s33, 0
-; GFX803-NEXT:    s_getpc_b64 s[18:19]
-; GFX803-NEXT:    s_add_u32 s18, s18, ex@rel32@lo+4
-; GFX803-NEXT:    s_addc_u32 s19, s19, ex@rel32@hi+12
-; GFX803-NEXT:    s_swappc_b64 s[30:31], s[18:19]
+; GFX803-NEXT:    s_getpc_b64 s[16:17]
+; GFX803-NEXT:    s_add_u32 s16, s16, ex@rel32@lo+4
+; GFX803-NEXT:    s_addc_u32 s17, s17, ex@rel32@hi+12
+; GFX803-NEXT:    s_swappc_b64 s[30:31], s[16:17]
 ; GFX803-NEXT:    s_endpgm
 ;
 ; GFX900-LABEL: test_force_fp_kern_call:
 ; GFX900:       ; %bb.0: ; %entry
-; GFX900-NEXT:    s_add_u32 flat_scratch_lo, s12, s17
-; GFX900-NEXT:    s_addc_u32 flat_scratch_hi, s13, 0
-; GFX900-NEXT:    s_add_u32 s0, s0, s17
+; GFX900-NEXT:    s_add_u32 flat_scratch_lo, s10, s15
+; GFX900-NEXT:    s_addc_u32 flat_scratch_hi, s11, 0
+; GFX900-NEXT:    s_add_u32 s0, s0, s15
 ; GFX900-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX900-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX900-NEXT:    s_addc_u32 s1, s1, 0
-; GFX900-NEXT:    s_mov_b32 s13, s15
-; GFX900-NEXT:    s_mov_b32 s12, s14
+; GFX900-NEXT:    s_mov_b64 s[10:11], s[8:9]
 ; GFX900-NEXT:    v_or3_b32 v31, v0, v1, v2
-; GFX900-NEXT:    s_mov_b32 s14, s16
+; GFX900-NEXT:    s_mov_b64 s[8:9], s[6:7]
 ; GFX900-NEXT:    s_mov_b32 s32, 0
 ; GFX900-NEXT:    s_mov_b32 s33, 0
-; GFX900-NEXT:    s_getpc_b64 s[18:19]
-; GFX900-NEXT:    s_add_u32 s18, s18, ex@rel32@lo+4
-; GFX900-NEXT:    s_addc_u32 s19, s19, ex@rel32@hi+12
-; GFX900-NEXT:    s_swappc_b64 s[30:31], s[18:19]
+; GFX900-NEXT:    s_getpc_b64 s[16:17]
+; GFX900-NEXT:    s_add_u32 s16, s16, ex@rel32@lo+4
+; GFX900-NEXT:    s_addc_u32 s17, s17, ex@rel32@hi+12
+; GFX900-NEXT:    s_swappc_b64 s[30:31], s[16:17]
 ; GFX900-NEXT:    s_endpgm
 ;
 ; GFX1010-LABEL: test_force_fp_kern_call:
 ; GFX1010:       ; %bb.0: ; %entry
-; GFX1010-NEXT:    s_add_u32 s12, s12, s17
+; GFX1010-NEXT:    s_add_u32 s10, s10, s15
 ; GFX1010-NEXT:    s_mov_b32 s32, 0
 ; GFX1010-NEXT:    s_mov_b32 s33, 0
-; GFX1010-NEXT:    s_addc_u32 s13, s13, 0
-; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12
-; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13
+; GFX1010-NEXT:    s_addc_u32 s11, s11, 0
+; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s10
+; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s11
 ; GFX1010-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX1010-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1010-NEXT:    s_add_u32 s0, s0, s17
+; GFX1010-NEXT:    s_add_u32 s0, s0, s15
 ; GFX1010-NEXT:    s_addc_u32 s1, s1, 0
-; GFX1010-NEXT:    s_mov_b32 s13, s15
-; GFX1010-NEXT:    s_mov_b32 s12, s14
+; GFX1010-NEXT:    s_mov_b64 s[10:11], s[8:9]
+; GFX1010-NEXT:    s_mov_b64 s[8:9], s[6:7]
 ; GFX1010-NEXT:    v_or3_b32 v31, v0, v1, v2
-; GFX1010-NEXT:    s_mov_b32 s14, s16
-; GFX1010-NEXT:    s_getpc_b64 s[18:19]
-; GFX1010-NEXT:    s_add_u32 s18, s18, ex@rel32@lo+4
-; GFX1010-NEXT:    s_addc_u32 s19, s19, ex@rel32@hi+12
-; GFX1010-NEXT:    s_swappc_b64 s[30:31], s[18:19]
+; GFX1010-NEXT:    s_getpc_b64 s[16:17]
+; GFX1010-NEXT:    s_add_u32 s16, s16, ex@rel32@lo+4
+; GFX1010-NEXT:    s_addc_u32 s17, s17, ex@rel32@hi+12
+; GFX1010-NEXT:    s_swappc_b64 s[30:31], s[16:17]
 ; GFX1010-NEXT:    s_endpgm
 ;
 ; GFX1100-LABEL: test_force_fp_kern_call:
 ; GFX1100:       ; %bb.0: ; %entry
 ; GFX1100-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1100-NEXT:    s_mov_b32 s12, s13
-; GFX1100-NEXT:    s_mov_b64 s[10:11], s[6:7]
-; GFX1100-NEXT:    s_mov_b64 s[8:9], s[4:5]
+; GFX1100-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1100-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1100-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1100-NEXT:    s_mov_b64 s[8:9], s[2:3]
 ; GFX1100-NEXT:    s_mov_b32 s13, s14
 ; GFX1100-NEXT:    s_mov_b32 s14, s15
 ; GFX1100-NEXT:    s_mov_b32 s32, 0
 ; GFX1100-NEXT:    s_mov_b32 s33, 0
-; GFX1100-NEXT:    s_getpc_b64 s[16:17]
-; GFX1100-NEXT:    s_add_u32 s16, s16, ex@rel32@lo+4
-; GFX1100-NEXT:    s_addc_u32 s17, s17, ex@rel32@hi+12
-; GFX1100-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1100-NEXT:    s_getpc_b64 s[6:7]
+; GFX1100-NEXT:    s_add_u32 s6, s6, ex@rel32@lo+4
+; GFX1100-NEXT:    s_addc_u32 s7, s7, ex@rel32@hi+12
+; GFX1100-NEXT:    s_swappc_b64 s[30:31], s[6:7]
 ; GFX1100-NEXT:    s_endpgm
 ; GFX1010-NEXT    s_add_u32 s12, s12, s17
 ; GFX1010-NEXT    s_mov_b32 s32, 0
@@ -424,75 +412,72 @@ entry:
 define amdgpu_kernel void @test_force_fp_kern_stack_and_call() local_unnamed_addr #2 {
 ; GFX803-LABEL: test_force_fp_kern_stack_and_call:
 ; GFX803:       ; %bb.0: ; %entry
-; GFX803-NEXT:    s_add_i32 s12, s12, s17
-; GFX803-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX803-NEXT:    s_add_i32 s10, s10, s15
+; GFX803-NEXT:    s_lshr_b32 flat_scratch_hi, s10, 8
 ; GFX803-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX803-NEXT:    s_add_u32 s0, s0, s17
+; GFX803-NEXT:    s_add_u32 s0, s0, s15
 ; GFX803-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX803-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX803-NEXT:    s_mov_b32 s33, 0
-; GFX803-NEXT:    s_mov_b32 flat_scratch_lo, s13
+; GFX803-NEXT:    s_mov_b32 flat_scratch_lo, s11
 ; GFX803-NEXT:    s_addc_u32 s1, s1, 0
-; GFX803-NEXT:    s_mov_b32 s13, s15
-; GFX803-NEXT:    s_mov_b32 s12, s14
+; GFX803-NEXT:    s_mov_b64 s[10:11], s[8:9]
 ; GFX803-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX803-NEXT:    v_or_b32_e32 v31, v0, v2
-; GFX803-NEXT:    s_mov_b32 s14, s16
+; GFX803-NEXT:    s_mov_b64 s[8:9], s[6:7]
 ; GFX803-NEXT:    s_movk_i32 s32, 0x400
 ; GFX803-NEXT:    buffer_store_dword v3, off, s[0:3], s33 offset:4
 ; GFX803-NEXT:    s_waitcnt vmcnt(0)
-; GFX803-NEXT:    s_getpc_b64 s[18:19]
-; GFX803-NEXT:    s_add_u32 s18, s18, ex@rel32@lo+4
-; GFX803-NEXT:    s_addc_u32 s19, s19, ex@rel32@hi+12
-; GFX803-NEXT:    s_swappc_b64 s[30:31], s[18:19]
+; GFX803-NEXT:    s_getpc_b64 s[16:17]
+; GFX803-NEXT:    s_add_u32 s16, s16, ex@rel32@lo+4
+; GFX803-NEXT:    s_addc_u32 s17, s17, ex@rel32@hi+12
+; GFX803-NEXT:    s_swappc_b64 s[30:31], s[16:17]
 ; GFX803-NEXT:    s_endpgm
 ;
 ; GFX900-LABEL: test_force_fp_kern_stack_and_call:
 ; GFX900:       ; %bb.0: ; %entry
-; GFX900-NEXT:    s_add_u32 flat_scratch_lo, s12, s17
-; GFX900-NEXT:    s_addc_u32 flat_scratch_hi, s13, 0
-; GFX900-NEXT:    s_add_u32 s0, s0, s17
+; GFX900-NEXT:    s_add_u32 flat_scratch_lo, s10, s15
+; GFX900-NEXT:    s_addc_u32 flat_scratch_hi, s11, 0
+; GFX900-NEXT:    s_add_u32 s0, s0, s15
 ; GFX900-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX900-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX900-NEXT:    s_mov_b32 s33, 0
 ; GFX900-NEXT:    s_addc_u32 s1, s1, 0
-; GFX900-NEXT:    s_mov_b32 s13, s15
-; GFX900-NEXT:    s_mov_b32 s12, s14
+; GFX900-NEXT:    s_mov_b64 s[10:11], s[8:9]
 ; GFX900-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX900-NEXT:    v_or3_b32 v31, v0, v1, v2
-; GFX900-NEXT:    s_mov_b32 s14, s16
+; GFX900-NEXT:    s_mov_b64 s[8:9], s[6:7]
 ; GFX900-NEXT:    s_movk_i32 s32, 0x400
 ; GFX900-NEXT:    buffer_store_dword v3, off, s[0:3], s33 offset:4
 ; GFX900-NEXT:    s_waitcnt vmcnt(0)
-; GFX900-NEXT:    s_getpc_b64 s[18:19]
-; GFX900-NEXT:    s_add_u32 s18, s18, ex@rel32@lo+4
-; GFX900-NEXT:    s_addc_u32 s19, s19, ex@rel32@hi+12
-; GFX900-NEXT:    s_swappc_b64 s[30:31], s[18:19]
+; GFX900-NEXT:    s_getpc_b64 s[16:17]
+; GFX900-NEXT:    s_add_u32 s16, s16, ex@rel32@lo+4
+; GFX900-NEXT:    s_addc_u32 s17, s17, ex@rel32@hi+12
+; GFX900-NEXT:    s_swappc_b64 s[30:31], s[16:17]
 ; GFX900-NEXT:    s_endpgm
 ;
 ; GFX1010-LABEL: test_force_fp_kern_stack_and_call:
 ; GFX1010:       ; %bb.0: ; %entry
-; GFX1010-NEXT:    s_add_u32 s12, s12, s17
+; GFX1010-NEXT:    s_add_u32 s10, s10, s15
 ; GFX1010-NEXT:    s_movk_i32 s32, 0x200
 ; GFX1010-NEXT:    s_mov_b32 s33, 0
-; GFX1010-NEXT:    s_addc_u32 s13, s13, 0
-; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12
-; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13
+; GFX1010-NEXT:    s_addc_u32 s11, s11, 0
+; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s10
+; GFX1010-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s11
 ; GFX1010-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX1010-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX1010-NEXT:    v_mov_b32_e32 v3, 0
-; GFX1010-NEXT:    s_add_u32 s0, s0, s17
+; GFX1010-NEXT:    s_add_u32 s0, s0, s15
 ; GFX1010-NEXT:    s_addc_u32 s1, s1, 0
-; GFX1010-NEXT:    s_mov_b32 s13, s15
+; GFX1010-NEXT:    s_mov_b64 s[10:11], s[8:9]
 ; GFX1010-NEXT:    v_or3_b32 v31, v0, v1, v2
-; GFX1010-NEXT:    s_mov_b32 s12, s14
-; GFX1010-NEXT:    s_mov_b32 s14, s16
+; GFX1010-NEXT:    s_mov_b64 s[8:9], s[6:7]
 ; GFX1010-NEXT:    buffer_store_dword v3, off, s[0:3], s33 offset:4
 ; GFX1010-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX1010-NEXT:    s_getpc_b64 s[18:19]
-; GFX1010-NEXT:    s_add_u32 s18, s18, ex@rel32@lo+4
-; GFX1010-NEXT:    s_addc_u32 s19, s19, ex@rel32@hi+12
-; GFX1010-NEXT:    s_swappc_b64 s[30:31], s[18:19]
+; GFX1010-NEXT:    s_getpc_b64 s[16:17]
+; GFX1010-NEXT:    s_add_u32 s16, s16, ex@rel32@lo+4
+; GFX1010-NEXT:    s_addc_u32 s17, s17, ex@rel32@hi+12
+; GFX1010-NEXT:    s_swappc_b64 s[30:31], s[16:17]
 ; GFX1010-NEXT:    s_endpgm
 ;
 ; GFX1100-LABEL: test_force_fp_kern_stack_and_call:
@@ -501,19 +486,18 @@ define amdgpu_kernel void @test_force_fp_kern_stack_and_call() local_unnamed_add
 ; GFX1100-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1100-NEXT:    s_mov_b32 s33, 0
 ; GFX1100-NEXT:    s_mov_b32 s12, s13
-; GFX1100-NEXT:    s_mov_b64 s[10:11], s[6:7]
-; GFX1100-NEXT:    s_mov_b64 s[8:9], s[4:5]
+; GFX1100-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1100-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1100-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1100-NEXT:    s_mov_b64 s[8:9], s[2:3]
 ; GFX1100-NEXT:    s_mov_b32 s13, s14
 ; GFX1100-NEXT:    s_mov_b32 s14, s15
 ; GFX1100-NEXT:    s_mov_b32 s32, 16
 ; GFX1100-NEXT:    scratch_store_b32 off, v1, s33 offset:4 dlc
 ; GFX1100-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX1100-NEXT:    s_getpc_b64 s[16:17]
-; GFX1100-NEXT:    s_add_u32 s16, s16, ex@rel32@lo+4
-; GFX1100-NEXT:    s_addc_u32 s17, s17, ex@rel32@hi+12
-; GFX1100-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1100-NEXT:    s_getpc_b64 s[6:7]
+; GFX1100-NEXT:    s_add_u32 s6, s6, ex@rel32@lo+4
+; GFX1100-NEXT:    s_addc_u32 s7, s7, ex@rel32@hi+12
+; GFX1100-NEXT:    s_swappc_b64 s[30:31], s[6:7]
 ; GFX1100-NEXT:    s_endpgm
 entry:
   %x = alloca i32, align 4, addrspace(5)
@@ -609,3 +593,6 @@ declare hidden void @ex() local_unnamed_addr #0
 attributes #0 = { nounwind }
 attributes #1 = { nounwind "amdgpu-num-vgpr"="8" }
 attributes #2 = { nounwind "frame-pointer"="all" }
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"amdgpu_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll b/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
index c6b17b40ffb6..362427f5835a 100644
--- a/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
+++ b/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
@@ -34,36 +34,36 @@ define amdgpu_kernel void @test_loop(ptr addrspace(3) %ptr, i32 %n) nounwind {
 ; GCN_DBG-NEXT:    s_mov_b32 s13, SCRATCH_RSRC_DWORD1
 ; GCN_DBG-NEXT:    s_mov_b32 s14, -1
 ; GCN_DBG-NEXT:    s_mov_b32 s15, 0xe8f000
-; GCN_DBG-NEXT:    s_add_u32 s12, s12, s11
+; GCN_DBG-NEXT:    s_add_u32 s12, s12, s9
 ; GCN_DBG-NEXT:    s_addc_u32 s13, s13, 0
 ; GCN_DBG-NEXT:    ; implicit-def: $vgpr0 : SGPR spill to VGPR lane
-; GCN_DBG-NEXT:    s_load_dword s0, s[4:5], 0x9
+; GCN_DBG-NEXT:    s_load_dword s0, s[2:3], 0x9
 ; GCN_DBG-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN_DBG-NEXT:    v_writelane_b32 v0, s0, 0
-; GCN_DBG-NEXT:    s_load_dword s1, s[4:5], 0xa
+; GCN_DBG-NEXT:    s_load_dword s1, s[2:3], 0xa
 ; GCN_DBG-NEXT:    s_mov_b32 s0, 0
 ; GCN_DBG-NEXT:    s_mov_b32 s2, -1
 ; GCN_DBG-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN_DBG-NEXT:    s_cmp_lg_u32 s1, s2
 ; GCN_DBG-NEXT:    v_writelane_b32 v0, s0, 1
-; GCN_DBG-NEXT:    s_mov_b64 s[6:7], exec
+; GCN_DBG-NEXT:    s_mov_b64 s[4:5], exec
 ; GCN_DBG-NEXT:    s_mov_b64 exec, -1
 ; GCN_DBG-NEXT:    buffer_store_dword v0, off, s[12:15], 0 offset:4 ; 4-byte Folded Spill
-; GCN_DBG-NEXT:    s_mov_b64 exec, s[6:7]
+; GCN_DBG-NEXT:    s_mov_b64 exec, s[4:5]
 ; GCN_DBG-NEXT:    s_cbranch_scc1 .LBB0_2
 ; GCN_DBG-NEXT:  ; %bb.1: ; %for.exit
-; GCN_DBG-NEXT:    s_or_saveexec_b64 s[6:7], -1
+; GCN_DBG-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GCN_DBG-NEXT:    s_waitcnt expcnt(0)
 ; GCN_DBG-NEXT:    buffer_load_dword v0, off, s[12:15], 0 offset:4 ; 4-byte Folded Reload
-; GCN_DBG-NEXT:    s_mov_b64 exec, s[6:7]
+; GCN_DBG-NEXT:    s_mov_b64 exec, s[4:5]
 ; GCN_DBG-NEXT:    ; kill: killed $vgpr0
 ; GCN_DBG-NEXT:    s_endpgm
 ; GCN_DBG-NEXT:  .LBB0_2: ; %for.body
 ; GCN_DBG-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GCN_DBG-NEXT:    s_or_saveexec_b64 s[6:7], -1
+; GCN_DBG-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GCN_DBG-NEXT:    s_waitcnt expcnt(0)
 ; GCN_DBG-NEXT:    buffer_load_dword v0, off, s[12:15], 0 offset:4 ; 4-byte Folded Reload
-; GCN_DBG-NEXT:    s_mov_b64 exec, s[6:7]
+; GCN_DBG-NEXT:    s_mov_b64 exec, s[4:5]
 ; GCN_DBG-NEXT:    s_waitcnt vmcnt(0)
 ; GCN_DBG-NEXT:    v_readlane_b32 s0, v0, 1
 ; GCN_DBG-NEXT:    v_readlane_b32 s2, v0, 0
@@ -86,15 +86,15 @@ define amdgpu_kernel void @test_loop(ptr addrspace(3) %ptr, i32 %n) nounwind {
 ; GCN_DBG-NEXT:    s_mov_b64 s[2:3], -1
 ; GCN_DBG-NEXT:    s_and_b64 vcc, exec, s[2:3]
 ; GCN_DBG-NEXT:    v_writelane_b32 v0, s0, 1
-; GCN_DBG-NEXT:    s_or_saveexec_b64 s[6:7], -1
+; GCN_DBG-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GCN_DBG-NEXT:    buffer_store_dword v0, off, s[12:15], 0 offset:4 ; 4-byte Folded Spill
-; GCN_DBG-NEXT:    s_mov_b64 exec, s[6:7]
+; GCN_DBG-NEXT:    s_mov_b64 exec, s[4:5]
 ; GCN_DBG-NEXT:    s_cbranch_vccnz .LBB0_2
 ; GCN_DBG-NEXT:  ; %bb.3: ; %DummyReturnBlock
-; GCN_DBG-NEXT:    s_or_saveexec_b64 s[6:7], -1
+; GCN_DBG-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GCN_DBG-NEXT:    s_waitcnt expcnt(0)
 ; GCN_DBG-NEXT:    buffer_load_dword v0, off, s[12:15], 0 offset:4 ; 4-byte Folded Reload
-; GCN_DBG-NEXT:    s_mov_b64 exec, s[6:7]
+; GCN_DBG-NEXT:    s_mov_b64 exec, s[4:5]
 ; GCN_DBG-NEXT:    ; kill: killed $vgpr0
 ; GCN_DBG-NEXT:    s_endpgm
 entry:
@@ -142,31 +142,31 @@ define amdgpu_kernel void @loop_const_true(ptr addrspace(3) %ptr, i32 %n) nounwi
 ; GCN_DBG-NEXT:    s_mov_b32 s13, SCRATCH_RSRC_DWORD1
 ; GCN_DBG-NEXT:    s_mov_b32 s14, -1
 ; GCN_DBG-NEXT:    s_mov_b32 s15, 0xe8f000
-; GCN_DBG-NEXT:    s_add_u32 s12, s12, s11
+; GCN_DBG-NEXT:    s_add_u32 s12, s12, s9
 ; GCN_DBG-NEXT:    s_addc_u32 s13, s13, 0
 ; GCN_DBG-NEXT:    ; implicit-def: $vgpr0 : SGPR spill to VGPR lane
-; GCN_DBG-NEXT:    s_load_dword s0, s[4:5], 0x9
+; GCN_DBG-NEXT:    s_load_dword s0, s[2:3], 0x9
 ; GCN_DBG-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN_DBG-NEXT:    v_writelane_b32 v0, s0, 0
 ; GCN_DBG-NEXT:    s_mov_b32 s0, 0
 ; GCN_DBG-NEXT:    v_writelane_b32 v0, s0, 1
-; GCN_DBG-NEXT:    s_or_saveexec_b64 s[6:7], -1
+; GCN_DBG-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GCN_DBG-NEXT:    buffer_store_dword v0, off, s[12:15], 0 offset:4 ; 4-byte Folded Spill
-; GCN_DBG-NEXT:    s_mov_b64 exec, s[6:7]
+; GCN_DBG-NEXT:    s_mov_b64 exec, s[4:5]
 ; GCN_DBG-NEXT:    s_branch .LBB1_2
 ; GCN_DBG-NEXT:  .LBB1_1: ; %for.exit
-; GCN_DBG-NEXT:    s_or_saveexec_b64 s[6:7], -1
+; GCN_DBG-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GCN_DBG-NEXT:    s_waitcnt expcnt(0)
 ; GCN_DBG-NEXT:    buffer_load_dword v0, off, s[12:15], 0 offset:4 ; 4-byte Folded Reload
-; GCN_DBG-NEXT:    s_mov_b64 exec, s[6:7]
+; GCN_DBG-NEXT:    s_mov_b64 exec, s[4:5]
 ; GCN_DBG-NEXT:    ; kill: killed $vgpr0
 ; GCN_DBG-NEXT:    s_endpgm
 ; GCN_DBG-NEXT:  .LBB1_2: ; %for.body
 ; GCN_DBG-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GCN_DBG-NEXT:    s_or_saveexec_b64 s[6:7], -1
+; GCN_DBG-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GCN_DBG-NEXT:    s_waitcnt expcnt(0)
 ; GCN_DBG-NEXT:    buffer_load_dword v0, off, s[12:15], 0 offset:4 ; 4-byte Folded Reload
-; GCN_DBG-NEXT:    s_mov_b64 exec, s[6:7]
+; GCN_DBG-NEXT:    s_mov_b64 exec, s[4:5]
 ; GCN_DBG-NEXT:    s_waitcnt vmcnt(0)
 ; GCN_DBG-NEXT:    v_readlane_b32 s0, v0, 1
 ; GCN_DBG-NEXT:    v_readlane_b32 s2, v0, 0
@@ -189,9 +189,9 @@ define amdgpu_kernel void @loop_const_true(ptr addrspace(3) %ptr, i32 %n) nounwi
 ; GCN_DBG-NEXT:    s_mov_b64 s[2:3], 0
 ; GCN_DBG-NEXT:    s_and_b64 vcc, exec, s[2:3]
 ; GCN_DBG-NEXT:    v_writelane_b32 v0, s0, 1
-; GCN_DBG-NEXT:    s_or_saveexec_b64 s[6:7], -1
+; GCN_DBG-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GCN_DBG-NEXT:    buffer_store_dword v0, off, s[12:15], 0 offset:4 ; 4-byte Folded Spill
-; GCN_DBG-NEXT:    s_mov_b64 exec, s[6:7]
+; GCN_DBG-NEXT:    s_mov_b64 exec, s[4:5]
 ; GCN_DBG-NEXT:    s_cbranch_vccnz .LBB1_1
 ; GCN_DBG-NEXT:    s_branch .LBB1_2
 entry:
@@ -230,31 +230,31 @@ define amdgpu_kernel void @loop_const_false(ptr addrspace(3) %ptr, i32 %n) nounw
 ; GCN_DBG-NEXT:    s_mov_b32 s13, SCRATCH_RSRC_DWORD1
 ; GCN_DBG-NEXT:    s_mov_b32 s14, -1
 ; GCN_DBG-NEXT:    s_mov_b32 s15, 0xe8f000
-; GCN_DBG-NEXT:    s_add_u32 s12, s12, s11
+; GCN_DBG-NEXT:    s_add_u32 s12, s12, s9
 ; GCN_DBG-NEXT:    s_addc_u32 s13, s13, 0
 ; GCN_DBG-NEXT:    ; implicit-def: $vgpr0 : SGPR spill to VGPR lane
-; GCN_DBG-NEXT:    s_load_dword s0, s[4:5], 0x9
+; GCN_DBG-NEXT:    s_load_dword s0, s[2:3], 0x9
 ; GCN_DBG-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN_DBG-NEXT:    v_writelane_b32 v0, s0, 0
 ; GCN_DBG-NEXT:    s_mov_b32 s0, 0
 ; GCN_DBG-NEXT:    v_writelane_b32 v0, s0, 1
-; GCN_DBG-NEXT:    s_or_saveexec_b64 s[6:7], -1
+; GCN_DBG-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GCN_DBG-NEXT:    buffer_store_dword v0, off, s[12:15], 0 offset:4 ; 4-byte Folded Spill
-; GCN_DBG-NEXT:    s_mov_b64 exec, s[6:7]
+; GCN_DBG-NEXT:    s_mov_b64 exec, s[4:5]
 ; GCN_DBG-NEXT:    s_branch .LBB2_2
 ; GCN_DBG-NEXT:  .LBB2_1: ; %for.exit
-; GCN_DBG-NEXT:    s_or_saveexec_b64 s[6:7], -1
+; GCN_DBG-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GCN_DBG-NEXT:    s_waitcnt expcnt(0)
 ; GCN_DBG-NEXT:    buffer_load_dword v0, off, s[12:15], 0 offset:4 ; 4-byte Folded Reload
-; GCN_DBG-NEXT:    s_mov_b64 exec, s[6:7]
+; GCN_DBG-NEXT:    s_mov_b64 exec, s[4:5]
 ; GCN_DBG-NEXT:    ; kill: killed $vgpr0
 ; GCN_DBG-NEXT:    s_endpgm
 ; GCN_DBG-NEXT:  .LBB2_2: ; %for.body
 ; GCN_DBG-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GCN_DBG-NEXT:    s_or_saveexec_b64 s[6:7], -1
+; GCN_DBG-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GCN_DBG-NEXT:    s_waitcnt expcnt(0)
 ; GCN_DBG-NEXT:    buffer_load_dword v0, off, s[12:15], 0 offset:4 ; 4-byte Folded Reload
-; GCN_DBG-NEXT:    s_mov_b64 exec, s[6:7]
+; GCN_DBG-NEXT:    s_mov_b64 exec, s[4:5]
 ; GCN_DBG-NEXT:    s_waitcnt vmcnt(0)
 ; GCN_DBG-NEXT:    v_readlane_b32 s0, v0, 1
 ; GCN_DBG-NEXT:    v_readlane_b32 s2, v0, 0
@@ -277,9 +277,9 @@ define amdgpu_kernel void @loop_const_false(ptr addrspace(3) %ptr, i32 %n) nounw
 ; GCN_DBG-NEXT:    s_mov_b64 s[2:3], -1
 ; GCN_DBG-NEXT:    s_and_b64 vcc, exec, s[2:3]
 ; GCN_DBG-NEXT:    v_writelane_b32 v0, s0, 1
-; GCN_DBG-NEXT:    s_or_saveexec_b64 s[6:7], -1
+; GCN_DBG-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GCN_DBG-NEXT:    buffer_store_dword v0, off, s[12:15], 0 offset:4 ; 4-byte Folded Spill
-; GCN_DBG-NEXT:    s_mov_b64 exec, s[6:7]
+; GCN_DBG-NEXT:    s_mov_b64 exec, s[4:5]
 ; GCN_DBG-NEXT:    s_cbranch_vccnz .LBB2_1
 ; GCN_DBG-NEXT:    s_branch .LBB2_2
 entry:
@@ -319,31 +319,31 @@ define amdgpu_kernel void @loop_const_undef(ptr addrspace(3) %ptr, i32 %n) nounw
 ; GCN_DBG-NEXT:    s_mov_b32 s13, SCRATCH_RSRC_DWORD1
 ; GCN_DBG-NEXT:    s_mov_b32 s14, -1
 ; GCN_DBG-NEXT:    s_mov_b32 s15, 0xe8f000
-; GCN_DBG-NEXT:    s_add_u32 s12, s12, s11
+; GCN_DBG-NEXT:    s_add_u32 s12, s12, s9
 ; GCN_DBG-NEXT:    s_addc_u32 s13, s13, 0
 ; GCN_DBG-NEXT:    ; implicit-def: $vgpr0 : SGPR spill to VGPR lane
-; GCN_DBG-NEXT:    s_load_dword s0, s[4:5], 0x9
+; GCN_DBG-NEXT:    s_load_dword s0, s[2:3], 0x9
 ; GCN_DBG-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN_DBG-NEXT:    v_writelane_b32 v0, s0, 0
 ; GCN_DBG-NEXT:    s_mov_b32 s0, 0
 ; GCN_DBG-NEXT:    v_writelane_b32 v0, s0, 1
-; GCN_DBG-NEXT:    s_or_saveexec_b64 s[6:7], -1
+; GCN_DBG-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GCN_DBG-NEXT:    buffer_store_dword v0, off, s[12:15], 0 offset:4 ; 4-byte Folded Spill
-; GCN_DBG-NEXT:    s_mov_b64 exec, s[6:7]
+; GCN_DBG-NEXT:    s_mov_b64 exec, s[4:5]
 ; GCN_DBG-NEXT:    s_branch .LBB3_2
 ; GCN_DBG-NEXT:  .LBB3_1: ; %for.exit
-; GCN_DBG-NEXT:    s_or_saveexec_b64 s[6:7], -1
+; GCN_DBG-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GCN_DBG-NEXT:    s_waitcnt expcnt(0)
 ; GCN_DBG-NEXT:    buffer_load_dword v0, off, s[12:15], 0 offset:4 ; 4-byte Folded Reload
-; GCN_DBG-NEXT:    s_mov_b64 exec, s[6:7]
+; GCN_DBG-NEXT:    s_mov_b64 exec, s[4:5]
 ; GCN_DBG-NEXT:    ; kill: killed $vgpr0
 ; GCN_DBG-NEXT:    s_endpgm
 ; GCN_DBG-NEXT:  .LBB3_2: ; %for.body
 ; GCN_DBG-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GCN_DBG-NEXT:    s_or_saveexec_b64 s[6:7], -1
+; GCN_DBG-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GCN_DBG-NEXT:    s_waitcnt expcnt(0)
 ; GCN_DBG-NEXT:    buffer_load_dword v0, off, s[12:15], 0 offset:4 ; 4-byte Folded Reload
-; GCN_DBG-NEXT:    s_mov_b64 exec, s[6:7]
+; GCN_DBG-NEXT:    s_mov_b64 exec, s[4:5]
 ; GCN_DBG-NEXT:    s_waitcnt vmcnt(0)
 ; GCN_DBG-NEXT:    v_readlane_b32 s0, v0, 1
 ; GCN_DBG-NEXT:    v_readlane_b32 s2, v0, 0
@@ -364,9 +364,9 @@ define amdgpu_kernel void @loop_const_undef(ptr addrspace(3) %ptr, i32 %n) nounw
 ; GCN_DBG-NEXT:    s_mov_b32 s1, 1
 ; GCN_DBG-NEXT:    s_add_i32 s0, s0, s1
 ; GCN_DBG-NEXT:    v_writelane_b32 v0, s0, 1
-; GCN_DBG-NEXT:    s_or_saveexec_b64 s[6:7], -1
+; GCN_DBG-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GCN_DBG-NEXT:    buffer_store_dword v0, off, s[12:15], 0 offset:4 ; 4-byte Folded Spill
-; GCN_DBG-NEXT:    s_mov_b64 exec, s[6:7]
+; GCN_DBG-NEXT:    s_mov_b64 exec, s[4:5]
 ; GCN_DBG-NEXT:    s_cbranch_scc1 .LBB3_1
 ; GCN_DBG-NEXT:    s_branch .LBB3_2
 entry:
@@ -420,10 +420,10 @@ define amdgpu_kernel void @loop_arg_0(ptr addrspace(3) %ptr, i32 %n) nounwind {
 ; GCN_DBG-NEXT:    s_mov_b32 s13, SCRATCH_RSRC_DWORD1
 ; GCN_DBG-NEXT:    s_mov_b32 s14, -1
 ; GCN_DBG-NEXT:    s_mov_b32 s15, 0xe8f000
-; GCN_DBG-NEXT:    s_add_u32 s12, s12, s11
+; GCN_DBG-NEXT:    s_add_u32 s12, s12, s9
 ; GCN_DBG-NEXT:    s_addc_u32 s13, s13, 0
 ; GCN_DBG-NEXT:    ; implicit-def: $vgpr0 : SGPR spill to VGPR lane
-; GCN_DBG-NEXT:    s_load_dword s0, s[4:5], 0x9
+; GCN_DBG-NEXT:    s_load_dword s0, s[2:3], 0x9
 ; GCN_DBG-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN_DBG-NEXT:    v_writelane_b32 v0, s0, 0
 ; GCN_DBG-NEXT:    v_mov_b32_e32 v1, 0
@@ -502,3 +502,6 @@ for.body:
   %inc = add i32 %indvar, 1
   br i1 %cond, label %for.body, label %for.exit
 }
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"amdgpu_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll b/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
index 8b1c5c3ae071..b2098344f93f 100644
--- a/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
+++ b/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
@@ -46,14 +46,14 @@ define amdgpu_kernel void @simple_nested_if(ptr addrspace(1) nocapture %arg) {
 ; GCN-O0-NEXT:    s_mov_b32 s13, SCRATCH_RSRC_DWORD1
 ; GCN-O0-NEXT:    s_mov_b32 s14, -1
 ; GCN-O0-NEXT:    s_mov_b32 s15, 0xe8f000
-; GCN-O0-NEXT:    s_add_u32 s12, s12, s11
+; GCN-O0-NEXT:    s_add_u32 s12, s12, s9
 ; GCN-O0-NEXT:    s_addc_u32 s13, s13, 0
 ; GCN-O0-NEXT:    ; implicit-def: $vgpr1 : SGPR spill to VGPR lane
 ; GCN-O0-NEXT:    v_mov_b32_e32 v1, v0
 ; GCN-O0-NEXT:    s_or_saveexec_b64 s[8:9], -1
 ; GCN-O0-NEXT:    buffer_load_dword v0, off, s[12:15], 0 offset:4 ; 4-byte Folded Reload
 ; GCN-O0-NEXT:    s_mov_b64 exec, s[8:9]
-; GCN-O0-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
+; GCN-O0-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x9
 ; GCN-O0-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GCN-O0-NEXT:    v_writelane_b32 v0, s0, 0
 ; GCN-O0-NEXT:    v_writelane_b32 v0, s1, 1
@@ -220,14 +220,14 @@ define amdgpu_kernel void @uncollapsable_nested_if(ptr addrspace(1) nocapture %a
 ; GCN-O0-NEXT:    s_mov_b32 s13, SCRATCH_RSRC_DWORD1
 ; GCN-O0-NEXT:    s_mov_b32 s14, -1
 ; GCN-O0-NEXT:    s_mov_b32 s15, 0xe8f000
-; GCN-O0-NEXT:    s_add_u32 s12, s12, s11
+; GCN-O0-NEXT:    s_add_u32 s12, s12, s9
 ; GCN-O0-NEXT:    s_addc_u32 s13, s13, 0
 ; GCN-O0-NEXT:    ; implicit-def: $vgpr1 : SGPR spill to VGPR lane
 ; GCN-O0-NEXT:    v_mov_b32_e32 v1, v0
 ; GCN-O0-NEXT:    s_or_saveexec_b64 s[8:9], -1
 ; GCN-O0-NEXT:    buffer_load_dword v0, off, s[12:15], 0 offset:4 ; 4-byte Folded Reload
 ; GCN-O0-NEXT:    s_mov_b64 exec, s[8:9]
-; GCN-O0-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
+; GCN-O0-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x9
 ; GCN-O0-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GCN-O0-NEXT:    v_writelane_b32 v0, s0, 0
 ; GCN-O0-NEXT:    v_writelane_b32 v0, s1, 1
@@ -431,14 +431,14 @@ define amdgpu_kernel void @nested_if_if_else(ptr addrspace(1) nocapture %arg) {
 ; GCN-O0-NEXT:    s_mov_b32 s13, SCRATCH_RSRC_DWORD1
 ; GCN-O0-NEXT:    s_mov_b32 s14, -1
 ; GCN-O0-NEXT:    s_mov_b32 s15, 0xe8f000
-; GCN-O0-NEXT:    s_add_u32 s12, s12, s11
+; GCN-O0-NEXT:    s_add_u32 s12, s12, s9
 ; GCN-O0-NEXT:    s_addc_u32 s13, s13, 0
 ; GCN-O0-NEXT:    ; implicit-def: $vgpr1 : SGPR spill to VGPR lane
 ; GCN-O0-NEXT:    v_mov_b32_e32 v1, v0
 ; GCN-O0-NEXT:    s_or_saveexec_b64 s[6:7], -1
 ; GCN-O0-NEXT:    buffer_load_dword v0, off, s[12:15], 0 offset:4 ; 4-byte Folded Reload
 ; GCN-O0-NEXT:    s_mov_b64 exec, s[6:7]
-; GCN-O0-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
+; GCN-O0-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x9
 ; GCN-O0-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-O0-NEXT:    s_mov_b64 s[2:3], s[0:1]
 ; GCN-O0-NEXT:    s_waitcnt vmcnt(0)
@@ -679,14 +679,14 @@ define amdgpu_kernel void @nested_if_else_if(ptr addrspace(1) nocapture %arg) {
 ; GCN-O0-NEXT:    s_mov_b32 s13, SCRATCH_RSRC_DWORD1
 ; GCN-O0-NEXT:    s_mov_b32 s14, -1
 ; GCN-O0-NEXT:    s_mov_b32 s15, 0xe8f000
-; GCN-O0-NEXT:    s_add_u32 s12, s12, s11
+; GCN-O0-NEXT:    s_add_u32 s12, s12, s9
 ; GCN-O0-NEXT:    s_addc_u32 s13, s13, 0
 ; GCN-O0-NEXT:    ; implicit-def: $vgpr1 : SGPR spill to VGPR lane
 ; GCN-O0-NEXT:    v_mov_b32_e32 v1, v0
 ; GCN-O0-NEXT:    s_or_saveexec_b64 s[8:9], -1
 ; GCN-O0-NEXT:    buffer_load_dword v0, off, s[12:15], 0 offset:4 ; 4-byte Folded Reload
 ; GCN-O0-NEXT:    s_mov_b64 exec, s[8:9]
-; GCN-O0-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x9
+; GCN-O0-NEXT:    s_load_dwordx2 s[4:5], s[2:3], 0x9
 ; GCN-O0-NEXT:    v_mov_b32_e32 v2, v1
 ; GCN-O0-NEXT:    buffer_store_dword v2, off, s[12:15], 0 offset:16 ; 4-byte Folded Spill
 ; GCN-O0-NEXT:    s_mov_b32 s0, 2
@@ -933,14 +933,14 @@ define amdgpu_kernel void @s_endpgm_unsafe_barrier(ptr addrspace(1) nocapture %a
 ; GCN-O0-NEXT:    s_mov_b32 s13, SCRATCH_RSRC_DWORD1
 ; GCN-O0-NEXT:    s_mov_b32 s14, -1
 ; GCN-O0-NEXT:    s_mov_b32 s15, 0xe8f000
-; GCN-O0-NEXT:    s_add_u32 s12, s12, s11
+; GCN-O0-NEXT:    s_add_u32 s12, s12, s9
 ; GCN-O0-NEXT:    s_addc_u32 s13, s13, 0
 ; GCN-O0-NEXT:    ; implicit-def: $vgpr1 : SGPR spill to VGPR lane
 ; GCN-O0-NEXT:    v_mov_b32_e32 v1, v0
 ; GCN-O0-NEXT:    s_or_saveexec_b64 s[6:7], -1
 ; GCN-O0-NEXT:    buffer_load_dword v0, off, s[12:15], 0 offset:4 ; 4-byte Folded Reload
 ; GCN-O0-NEXT:    s_mov_b64 exec, s[6:7]
-; GCN-O0-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
+; GCN-O0-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x9
 ; GCN-O0-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GCN-O0-NEXT:    v_writelane_b32 v0, s0, 0
 ; GCN-O0-NEXT:    v_writelane_b32 v0, s1, 1
@@ -1437,3 +1437,6 @@ declare void @llvm.amdgcn.s.barrier() #1
 attributes #0 = { nounwind readnone speculatable }
 attributes #1 = { nounwind convergent }
 attributes #2 = { nounwind }
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"amdgpu_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll b/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
index f97d15739be2..11871db1ef65 100644
--- a/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
+++ b/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
@@ -176,30 +176,28 @@ bb1:
 define amdgpu_kernel void @v3i16_registers(i1 %cond) #0 {
 ; GCN-LABEL: v3i16_registers:
 ; GCN:       ; %bb.0: ; %entry
-; GCN-NEXT:    s_add_u32 flat_scratch_lo, s12, s17
-; GCN-NEXT:    s_load_dword s12, s[8:9], 0x0
-; GCN-NEXT:    s_addc_u32 flat_scratch_hi, s13, 0
-; GCN-NEXT:    s_add_u32 s0, s0, s17
+; GCN-NEXT:    s_add_u32 flat_scratch_lo, s10, s15
+; GCN-NEXT:    s_addc_u32 flat_scratch_hi, s11, 0
+; GCN-NEXT:    s_mov_b64 s[10:11], s[8:9]
+; GCN-NEXT:    s_load_dword s8, s[6:7], 0x0
+; GCN-NEXT:    s_add_u32 s0, s0, s15
 ; GCN-NEXT:    s_addc_u32 s1, s1, 0
 ; GCN-NEXT:    s_mov_b32 s32, 0
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_bitcmp1_b32 s12, 0
-; GCN-NEXT:    s_cselect_b64 s[12:13], -1, 0
-; GCN-NEXT:    s_and_b64 vcc, exec, s[12:13]
+; GCN-NEXT:    s_bitcmp1_b32 s8, 0
+; GCN-NEXT:    s_cselect_b64 s[8:9], -1, 0
+; GCN-NEXT:    s_and_b64 vcc, exec, s[8:9]
 ; GCN-NEXT:    s_cbranch_vccnz .LBB4_2
 ; GCN-NEXT:  ; %bb.1: ; %if.else
-; GCN-NEXT:    s_add_u32 s8, s8, 8
+; GCN-NEXT:    s_add_u32 s8, s6, 8
 ; GCN-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GCN-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GCN-NEXT:    s_addc_u32 s9, s9, 0
+; GCN-NEXT:    s_addc_u32 s9, s7, 0
 ; GCN-NEXT:    v_or3_b32 v31, v0, v1, v2
-; GCN-NEXT:    s_mov_b32 s12, s14
-; GCN-NEXT:    s_mov_b32 s13, s15
-; GCN-NEXT:    s_mov_b32 s14, s16
-; GCN-NEXT:    s_getpc_b64 s[18:19]
-; GCN-NEXT:    s_add_u32 s18, s18, func_v3i16@rel32@lo+4
-; GCN-NEXT:    s_addc_u32 s19, s19, func_v3i16@rel32@hi+12
-; GCN-NEXT:    s_swappc_b64 s[30:31], s[18:19]
+; GCN-NEXT:    s_getpc_b64 s[6:7]
+; GCN-NEXT:    s_add_u32 s6, s6, func_v3i16@rel32@lo+4
+; GCN-NEXT:    s_addc_u32 s7, s7, func_v3i16@rel32@hi+12
+; GCN-NEXT:    s_swappc_b64 s[30:31], s[6:7]
 ; GCN-NEXT:    s_branch .LBB4_3
 ; GCN-NEXT:  .LBB4_2:
 ; GCN-NEXT:    v_mov_b32_e32 v0, 0
@@ -227,30 +225,28 @@ if.end:                                           ; preds = %if.else, %if.then
 define amdgpu_kernel void @v3f16_registers(i1 %cond) #0 {
 ; GCN-LABEL: v3f16_registers:
 ; GCN:       ; %bb.0: ; %entry
-; GCN-NEXT:    s_add_u32 flat_scratch_lo, s12, s17
-; GCN-NEXT:    s_load_dword s12, s[8:9], 0x0
-; GCN-NEXT:    s_addc_u32 flat_scratch_hi, s13, 0
-; GCN-NEXT:    s_add_u32 s0, s0, s17
+; GCN-NEXT:    s_add_u32 flat_scratch_lo, s10, s15
+; GCN-NEXT:    s_addc_u32 flat_scratch_hi, s11, 0
+; GCN-NEXT:    s_mov_b64 s[10:11], s[8:9]
+; GCN-NEXT:    s_load_dword s8, s[6:7], 0x0
+; GCN-NEXT:    s_add_u32 s0, s0, s15
 ; GCN-NEXT:    s_addc_u32 s1, s1, 0
 ; GCN-NEXT:    s_mov_b32 s32, 0
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_bitcmp1_b32 s12, 0
-; GCN-NEXT:    s_cselect_b64 s[12:13], -1, 0
-; GCN-NEXT:    s_and_b64 vcc, exec, s[12:13]
+; GCN-NEXT:    s_bitcmp1_b32 s8, 0
+; GCN-NEXT:    s_cselect_b64 s[8:9], -1, 0
+; GCN-NEXT:    s_and_b64 vcc, exec, s[8:9]
 ; GCN-NEXT:    s_cbranch_vccnz .LBB5_2
 ; GCN-NEXT:  ; %bb.1: ; %if.else
-; GCN-NEXT:    s_add_u32 s8, s8, 8
+; GCN-NEXT:    s_add_u32 s8, s6, 8
 ; GCN-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GCN-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GCN-NEXT:    s_addc_u32 s9, s9, 0
+; GCN-NEXT:    s_addc_u32 s9, s7, 0
 ; GCN-NEXT:    v_or3_b32 v31, v0, v1, v2
-; GCN-NEXT:    s_mov_b32 s12, s14
-; GCN-NEXT:    s_mov_b32 s13, s15
-; GCN-NEXT:    s_mov_b32 s14, s16
-; GCN-NEXT:    s_getpc_b64 s[18:19]
-; GCN-NEXT:    s_add_u32 s18, s18, func_v3f16@rel32@lo+4
-; GCN-NEXT:    s_addc_u32 s19, s19, func_v3f16@rel32@hi+12
-; GCN-NEXT:    s_swappc_b64 s[30:31], s[18:19]
+; GCN-NEXT:    s_getpc_b64 s[6:7]
+; GCN-NEXT:    s_add_u32 s6, s6, func_v3f16@rel32@lo+4
+; GCN-NEXT:    s_addc_u32 s7, s7, func_v3f16@rel32@hi+12
+; GCN-NEXT:    s_swappc_b64 s[30:31], s[6:7]
 ; GCN-NEXT:    s_branch .LBB5_3
 ; GCN-NEXT:  .LBB5_2:
 ; GCN-NEXT:    v_mov_b32_e32 v0, 0
@@ -285,3 +281,6 @@ declare hidden <3 x half> @func_v3f16()
 declare hidden { <4 x i32>, <4 x half> } @func_struct() #0
 
 attributes #0 = { nounwind}
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"amdgpu_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
index 901cbd4a5272..7b0ad8625b45 100644
--- a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
+++ b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
@@ -944,7 +944,7 @@ define amdgpu_kernel void @load_i8_to_f32(ptr addrspace(1) noalias %out, ptr add
 ;
 ; GFX9-LABEL: load_i8_to_f32:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[2:3], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    global_load_ubyte v0, v0, s[2:3]
@@ -1026,7 +1026,7 @@ define amdgpu_kernel void @load_v2i8_to_v2f32(ptr addrspace(1) noalias %out, ptr
 ;
 ; GFX9-LABEL: load_v2i8_to_v2f32:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[2:3], 0x24
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -1116,7 +1116,7 @@ define amdgpu_kernel void @load_v3i8_to_v3f32(ptr addrspace(1) noalias %out, ptr
 ;
 ; GFX9-LABEL: load_v3i8_to_v3f32:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[2:3], 0x24
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX9-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -1209,7 +1209,7 @@ define amdgpu_kernel void @load_v4i8_to_v4f32(ptr addrspace(1) noalias %out, ptr
 ;
 ; GFX9-LABEL: load_v4i8_to_v4f32:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[2:3], 0x24
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX9-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -1334,7 +1334,7 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_unaligned(ptr addrspace(1) noalias
 ;
 ; GFX9-LABEL: load_v4i8_to_v4f32_unaligned:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[2:3], 0x24
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX9-NEXT:    v_mov_b32_e32 v6, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -1497,7 +1497,7 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_unaligned_multiuse(<4 x float> add
 ;
 ; GFX9-LABEL: load_v4i8_to_v4f32_unaligned_multiuse:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_load_dwordx8 s[0:7], s[4:5], 0x24
+; GFX9-NEXT:    s_load_dwordx8 s[0:7], s[2:3], 0x24
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX9-NEXT:    v_mov_b32_e32 v5, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -1672,13 +1672,13 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_2_uses(ptr addrspace(1) noalias %o
 ;
 ; GFX9-LABEL: load_v4i8_to_v4f32_2_uses:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x34
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x34
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX9-NEXT:    v_mov_b32_e32 v5, 0
+; GFX9-NEXT:    s_movk_i32 s4, 0x900
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    global_load_dword v4, v0, s[0:1]
-; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT:    s_movk_i32 s4, 0x900
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[2:3], 0x24
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v4
 ; GFX9-NEXT:    v_cvt_f32_ubyte3_e32 v3, v4
@@ -1867,7 +1867,7 @@ define amdgpu_kernel void @load_v7i8_to_v7f32(ptr addrspace(1) noalias %out, ptr
 ;
 ; GFX9-LABEL: load_v7i8_to_v7f32:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[2:3], 0x24
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
 ; GFX9-NEXT:    v_mov_b32_e32 v10, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2008,7 +2008,7 @@ define amdgpu_kernel void @load_v8i8_to_v8f32(ptr addrspace(1) noalias %out, ptr
 ;
 ; GFX9-LABEL: load_v8i8_to_v8f32:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[2:3], 0x24
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
 ; GFX9-NEXT:    v_mov_b32_e32 v9, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2109,7 +2109,7 @@ define amdgpu_kernel void @i8_zext_inreg_i32_to_f32(ptr addrspace(1) noalias %ou
 ;
 ; GFX9-LABEL: i8_zext_inreg_i32_to_f32:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[2:3], 0x24
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2194,7 +2194,7 @@ define amdgpu_kernel void @i8_zext_inreg_hi1_to_f32(ptr addrspace(1) noalias %ou
 ;
 ; GFX9-LABEL: i8_zext_inreg_hi1_to_f32:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[2:3], 0x24
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2275,7 +2275,7 @@ define amdgpu_kernel void @i8_zext_i32_to_f32(ptr addrspace(1) noalias %out, ptr
 ;
 ; GFX9-LABEL: i8_zext_i32_to_f32:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[2:3], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    global_load_ubyte v0, v0, s[2:3]
@@ -2389,7 +2389,7 @@ define amdgpu_kernel void @v4i8_zext_v4i32_to_v4f32(ptr addrspace(1) noalias %ou
 ;
 ; GFX9-LABEL: v4i8_zext_v4i32_to_v4f32:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[2:3], 0x24
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX9-NEXT:    v_mov_b32_e32 v6, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2489,7 +2489,7 @@ define amdgpu_kernel void @extract_byte0_to_f32(ptr addrspace(1) noalias %out, p
 ;
 ; GFX9-LABEL: extract_byte0_to_f32:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[2:3], 0x24
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2570,7 +2570,7 @@ define amdgpu_kernel void @extract_byte1_to_f32(ptr addrspace(1) noalias %out, p
 ;
 ; GFX9-LABEL: extract_byte1_to_f32:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[2:3], 0x24
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2652,7 +2652,7 @@ define amdgpu_kernel void @extract_byte2_to_f32(ptr addrspace(1) noalias %out, p
 ;
 ; GFX9-LABEL: extract_byte2_to_f32:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[2:3], 0x24
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2734,7 +2734,7 @@ define amdgpu_kernel void @extract_byte3_to_f32(ptr addrspace(1) noalias %out, p
 ;
 ; GFX9-LABEL: extract_byte3_to_f32:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[2:3], 0x24
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2823,7 +2823,7 @@ define amdgpu_kernel void @cvt_ubyte0_or_multiuse(ptr addrspace(1) %in, ptr addr
 ;
 ; GFX9-LABEL: cvt_ubyte0_or_multiuse:
 ; GFX9:       ; %bb.0: ; %bb
-; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[2:3], 0x24
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -3019,3 +3019,6 @@ for.body.i:                                       ; preds = %for.body.i, %entry
   store i32 %retval.sroa.0.0.insert.insert, ptr addrspace(1) undef, align 1
   ret void
 }
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"amdgpu_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/ds_read2.ll b/llvm/test/CodeGen/AMDGPU/ds_read2.ll
index 9d94f8e6ca22..1b0ffb97ecb1 100644
--- a/llvm/test/CodeGen/AMDGPU/ds_read2.ll
+++ b/llvm/test/CodeGen/AMDGPU/ds_read2.ll
@@ -1334,31 +1334,29 @@ define amdgpu_kernel void @ds_read_call_read(ptr addrspace(1) %out, ptr addrspac
 ; CI-NEXT:    s_getpc_b64 s[40:41]
 ; CI-NEXT:    s_mov_b32 s40, s0
 ; CI-NEXT:    s_load_dwordx4 s[40:43], s[40:41], 0x0
-; CI-NEXT:    s_mov_b32 s14, s10
+; CI-NEXT:    s_mov_b64 s[10:11], s[4:5]
+; CI-NEXT:    s_load_dwordx2 s[36:37], s[2:3], 0x0
+; CI-NEXT:    s_load_dword s4, s[2:3], 0x2
 ; CI-NEXT:    v_lshlrev_b32_e32 v3, 2, v0
 ; CI-NEXT:    s_mov_b32 m0, -1
-; CI-NEXT:    s_mov_b32 s12, s8
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
-; CI-NEXT:    s_add_u32 s40, s40, s11
-; CI-NEXT:    s_mov_b64 s[10:11], s[6:7]
-; CI-NEXT:    s_load_dwordx2 s[36:37], s[4:5], 0x0
-; CI-NEXT:    s_load_dword s6, s[4:5], 0x2
+; CI-NEXT:    s_add_u32 s40, s40, s9
 ; CI-NEXT:    s_addc_u32 s41, s41, 0
-; CI-NEXT:    s_add_u32 s8, s4, 12
-; CI-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; CI-NEXT:    s_mov_b32 s13, s9
-; CI-NEXT:    s_waitcnt lgkmcnt(0)
-; CI-NEXT:    v_add_i32_e32 v40, vcc, s6, v3
+; CI-NEXT:    v_add_i32_e32 v40, vcc, s4, v3
 ; CI-NEXT:    ds_read_b32 v41, v40
-; CI-NEXT:    s_addc_u32 s9, s5, 0
+; CI-NEXT:    s_mov_b32 s14, s8
+; CI-NEXT:    s_add_u32 s8, s2, 12
+; CI-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
+; CI-NEXT:    s_addc_u32 s9, s3, 0
 ; CI-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; CI-NEXT:    v_or_b32_e32 v0, v0, v1
 ; CI-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; CI-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; CI-NEXT:    s_mov_b64 s[0:1], s[40:41]
 ; CI-NEXT:    s_mov_b32 s17, void_func_void@abs32@hi
 ; CI-NEXT:    s_mov_b32 s16, void_func_void@abs32@lo
 ; CI-NEXT:    v_or_b32_e32 v31, v0, v2
+; CI-NEXT:    s_mov_b32 s12, s6
+; CI-NEXT:    s_mov_b32 s13, s7
 ; CI-NEXT:    s_mov_b64 s[2:3], s[42:43]
 ; CI-NEXT:    s_mov_b32 s32, 0
 ; CI-NEXT:    s_mov_b32 s39, 0xf000
@@ -1375,28 +1373,26 @@ define amdgpu_kernel void @ds_read_call_read(ptr addrspace(1) %out, ptr addrspac
 ; GFX9-NEXT:    s_getpc_b64 s[36:37]
 ; GFX9-NEXT:    s_mov_b32 s36, s0
 ; GFX9-NEXT:    s_load_dwordx4 s[36:39], s[36:37], 0x0
-; GFX9-NEXT:    s_mov_b32 s14, s10
-; GFX9-NEXT:    s_mov_b32 s12, s8
-; GFX9-NEXT:    s_mov_b32 s13, s9
+; GFX9-NEXT:    s_mov_b64 s[10:11], s[4:5]
+; GFX9-NEXT:    s_load_dword s4, s[2:3], 0x8
+; GFX9-NEXT:    s_load_dwordx2 s[34:35], s[2:3], 0x0
+; GFX9-NEXT:    s_mov_b32 s14, s8
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    s_add_u32 s36, s36, s11
-; GFX9-NEXT:    s_mov_b64 s[10:11], s[6:7]
-; GFX9-NEXT:    s_load_dword s6, s[4:5], 0x8
-; GFX9-NEXT:    s_load_dwordx2 s[34:35], s[4:5], 0x0
+; GFX9-NEXT:    s_add_u32 s36, s36, s9
+; GFX9-NEXT:    v_lshl_add_u32 v41, v0, 2, s4
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_add_u32 s8, s4, 12
-; GFX9-NEXT:    s_addc_u32 s9, s5, 0
-; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    v_lshl_add_u32 v41, v0, 2, s6
 ; GFX9-NEXT:    ds_read_b32 v42, v41
+; GFX9-NEXT:    s_add_u32 s8, s2, 12
+; GFX9-NEXT:    s_addc_u32 s9, s3, 0
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    s_mov_b32 s17, void_func_void@abs32@hi
 ; GFX9-NEXT:    s_mov_b32 s16, void_func_void@abs32@lo
 ; GFX9-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-NEXT:    s_mov_b32 s12, s6
+; GFX9-NEXT:    s_mov_b32 s13, s7
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
 ; GFX9-NEXT:    v_mov_b32_e32 v40, 0
@@ -1544,3 +1540,6 @@ attributes #0 = { nounwind }
 attributes #1 = { nounwind readnone speculatable }
 attributes #2 = { convergent nounwind }
 attributes #3 = { nounwind noinline }
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"amdgpu_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll b/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
index f4d985833eb9..36a7ed51227a 100644
--- a/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
@@ -50,19 +50,19 @@ define weak_odr void @test(i32 %0) !dbg !34 {
 ; CHECK-NEXT:    s_mov_b64 s[4:5], s[40:41]
 ; CHECK-NEXT:    buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
 ; CHECK-NEXT:    v_mov_b32_e32 v41, v31
+; CHECK-NEXT:    s_mov_b64 s[34:35], s[6:7]
 ; CHECK-NEXT:    s_mov_b32 s42, s15
 ; CHECK-NEXT:    s_mov_b32 s43, s14
 ; CHECK-NEXT:    s_mov_b32 s44, s13
 ; CHECK-NEXT:    s_mov_b32 s45, s12
-; CHECK-NEXT:    s_mov_b64 s[34:35], s[10:11]
-; CHECK-NEXT:    s_mov_b64 s[36:37], s[8:9]
-; CHECK-NEXT:    s_mov_b64 s[38:39], s[6:7]
+; CHECK-NEXT:    s_mov_b64 s[36:37], s[10:11]
+; CHECK-NEXT:    s_mov_b64 s[38:39], s[8:9]
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
 ; CHECK-NEXT:    s_swappc_b64 s[30:31], s[46:47]
 ; CHECK-NEXT:    s_mov_b64 s[4:5], s[40:41]
-; CHECK-NEXT:    s_mov_b64 s[6:7], s[38:39]
-; CHECK-NEXT:    s_mov_b64 s[8:9], s[36:37]
-; CHECK-NEXT:    s_mov_b64 s[10:11], s[34:35]
+; CHECK-NEXT:    s_mov_b64 s[6:7], s[34:35]
+; CHECK-NEXT:    s_mov_b64 s[8:9], s[38:39]
+; CHECK-NEXT:    s_mov_b64 s[10:11], s[36:37]
 ; CHECK-NEXT:    s_mov_b32 s12, s45
 ; CHECK-NEXT:    s_mov_b32 s13, s44
 ; CHECK-NEXT:    s_mov_b32 s14, s43
@@ -110,7 +110,7 @@ define weak_odr void @test(i32 %0) !dbg !34 {
 attributes #0 = { nocallback nofree nosync nounwind readnone speculatable willreturn }
 
 !llvm.dbg.cu = !{!0, !25, !26}
-!llvm.module.flags = !{!27, !28, !29, !30, !31, !32}
+!llvm.module.flags = !{!27, !28, !29, !30, !31, !32, !44}
 
 !0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang version 15.0.0 (https://github.com/llvm/llvm-project.git 05256c8d95e0b15bcc502d595c15d902ff520f97)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !8, imports: !20, splitDebugInlining: false, nameTableKind: None)
 !1 = !DIFile(filename: "dummy", directory: "dummy", checksumkind: CSK_MD5, checksum: "b67bec84bdce3730b4a6f2ed8d50b85c")
@@ -155,3 +155,4 @@ attributes #0 = { nocallback nofree nosync nounwind readnone speculatable willre
 !41 = !DILocalVariable(name: "dummy", arg: 3, scope: !34, file: !1, line: 49, type: !5)
 !42 = !DILocalVariable(name: "dummy", arg: 4, scope: !34, file: !1, line: 49, type: !5)
 !43 = !DILocation(line: 49, column: 9, scope: !34)
+!44 = !{i32 1, !"amdgpu_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll b/llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
index b3cca5ff2429..bcf6bda807c8 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
@@ -62,45 +62,43 @@ define amdgpu_kernel void @stack_object_in_kernel_no_calls() {
 define amdgpu_kernel void @kernel_calls_no_stack() {
 ; FLAT_SCR_OPT-LABEL: kernel_calls_no_stack:
 ; FLAT_SCR_OPT:       ; %bb.0:
-; FLAT_SCR_OPT-NEXT:    s_add_u32 s8, s8, s13
+; FLAT_SCR_OPT-NEXT:    s_add_u32 s6, s6, s11
 ; FLAT_SCR_OPT-NEXT:    s_mov_b32 s32, 0
-; FLAT_SCR_OPT-NEXT:    s_addc_u32 s9, s9, 0
-; FLAT_SCR_OPT-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s8
-; FLAT_SCR_OPT-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s9
-; FLAT_SCR_OPT-NEXT:    s_mov_b64 s[8:9], s[4:5]
+; FLAT_SCR_OPT-NEXT:    s_addc_u32 s7, s7, 0
+; FLAT_SCR_OPT-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s6
+; FLAT_SCR_OPT-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s7
+; FLAT_SCR_OPT-NEXT:    s_mov_b32 s14, s10
+; FLAT_SCR_OPT-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; FLAT_SCR_OPT-NEXT:    s_getpc_b64 s[4:5]
 ; FLAT_SCR_OPT-NEXT:    s_add_u32 s4, s4, extern_func@gotpcrel32@lo+4
 ; FLAT_SCR_OPT-NEXT:    s_addc_u32 s5, s5, extern_func@gotpcrel32@hi+12
 ; FLAT_SCR_OPT-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; FLAT_SCR_OPT-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; FLAT_SCR_OPT-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x0
 ; FLAT_SCR_OPT-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; FLAT_SCR_OPT-NEXT:    s_mov_b32 s14, s12
-; FLAT_SCR_OPT-NEXT:    s_mov_b32 s13, s11
-; FLAT_SCR_OPT-NEXT:    s_mov_b32 s12, s10
-; FLAT_SCR_OPT-NEXT:    s_mov_b64 s[10:11], s[6:7]
-; FLAT_SCR_OPT-NEXT:    v_or3_b32 v31, v0, v1, v2
+; FLAT_SCR_OPT-NEXT:    s_mov_b32 s13, s9
+; FLAT_SCR_OPT-NEXT:    s_mov_b32 s12, s8
 ; FLAT_SCR_OPT-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; FLAT_SCR_OPT-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; FLAT_SCR_OPT-NEXT:    s_mov_b64 s[8:9], s[2:3]
+; FLAT_SCR_OPT-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; FLAT_SCR_OPT-NEXT:    s_waitcnt lgkmcnt(0)
-; FLAT_SCR_OPT-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; FLAT_SCR_OPT-NEXT:    s_swappc_b64 s[30:31], s[6:7]
 ; FLAT_SCR_OPT-NEXT:    s_endpgm
 ;
 ; FLAT_SCR_ARCH-LABEL: kernel_calls_no_stack:
 ; FLAT_SCR_ARCH:       ; %bb.0:
-; FLAT_SCR_ARCH-NEXT:    s_mov_b32 s13, s9
-; FLAT_SCR_ARCH-NEXT:    s_mov_b32 s12, s8
-; FLAT_SCR_ARCH-NEXT:    s_mov_b64 s[8:9], s[4:5]
+; FLAT_SCR_ARCH-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; FLAT_SCR_ARCH-NEXT:    s_getpc_b64 s[4:5]
 ; FLAT_SCR_ARCH-NEXT:    s_add_u32 s4, s4, extern_func@gotpcrel32@lo+4
 ; FLAT_SCR_ARCH-NEXT:    s_addc_u32 s5, s5, extern_func@gotpcrel32@hi+12
 ; FLAT_SCR_ARCH-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; FLAT_SCR_ARCH-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
 ; FLAT_SCR_ARCH-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; FLAT_SCR_ARCH-NEXT:    s_mov_b32 s14, s10
-; FLAT_SCR_ARCH-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; FLAT_SCR_ARCH-NEXT:    s_mov_b32 s14, s8
 ; FLAT_SCR_ARCH-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; FLAT_SCR_ARCH-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; FLAT_SCR_ARCH-NEXT:    s_mov_b64 s[8:9], s[2:3]
+; FLAT_SCR_ARCH-NEXT:    s_mov_b32 s12, s6
 ; FLAT_SCR_ARCH-NEXT:    v_or3_b32 v31, v0, v1, v2
+; FLAT_SCR_ARCH-NEXT:    s_mov_b32 s13, s7
 ; FLAT_SCR_ARCH-NEXT:    s_mov_b32 s32, 0
 ; FLAT_SCR_ARCH-NEXT:    s_waitcnt lgkmcnt(0)
 ; FLAT_SCR_ARCH-NEXT:    s_swappc_b64 s[30:31], s[16:17]
@@ -418,3 +416,6 @@ define amdgpu_kernel void @kernel_no_calls_no_stack() {
 }
 
 attributes #0 = { nounwind }
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"amdgpu_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
index 4cbd5e84871c..064831f09866 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
@@ -340,27 +340,26 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ; GFX7LESS-NEXT:    s_mov_b32 s41, SCRATCH_RSRC_DWORD1
 ; GFX7LESS-NEXT:    s_mov_b32 s42, -1
 ; GFX7LESS-NEXT:    s_mov_b32 s43, 0xe8f000
-; GFX7LESS-NEXT:    s_add_u32 s40, s40, s11
+; GFX7LESS-NEXT:    s_add_u32 s40, s40, s9
 ; GFX7LESS-NEXT:    s_addc_u32 s41, s41, 0
-; GFX7LESS-NEXT:    s_mov_b32 s14, s10
-; GFX7LESS-NEXT:    s_mov_b32 s13, s9
-; GFX7LESS-NEXT:    s_mov_b32 s12, s8
-; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[6:7]
-; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[4:5], 0x9
+; GFX7LESS-NEXT:    s_mov_b32 s14, s8
+; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[4:5]
+; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[2:3], 0x9
 ; GFX7LESS-NEXT:    s_mov_b32 s39, 0xf000
 ; GFX7LESS-NEXT:    s_mov_b32 s38, -1
-; GFX7LESS-NEXT:    s_add_u32 s8, s4, 44
-; GFX7LESS-NEXT:    s_addc_u32 s9, s5, 0
-; GFX7LESS-NEXT:    s_getpc_b64 s[4:5]
-; GFX7LESS-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX7LESS-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX7LESS-NEXT:    s_add_u32 s8, s2, 44
+; GFX7LESS-NEXT:    s_addc_u32 s9, s3, 0
+; GFX7LESS-NEXT:    s_getpc_b64 s[2:3]
+; GFX7LESS-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX7LESS-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v31, v0, v2
 ; GFX7LESS-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX7LESS-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX7LESS-NEXT:    s_mov_b32 s12, s6
+; GFX7LESS-NEXT:    s_mov_b32 s13, s7
 ; GFX7LESS-NEXT:    s_mov_b64 s[0:1], s[40:41]
 ; GFX7LESS-NEXT:    s_mov_b64 s[2:3], s[42:43]
 ; GFX7LESS-NEXT:    s_waitcnt lgkmcnt(0)
@@ -390,25 +389,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-NEXT:    s_mov_b32 s12, s8
+; GFX9-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-NEXT:    s_mov_b32 s14, s8
 ; GFX9-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-NEXT:    s_mov_b32 s13, s9
 ; GFX9-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT:    s_mov_b32 s14, s10
-; GFX9-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-NEXT:    s_mov_b32 s12, s6
+; GFX9-NEXT:    s_mov_b32 s13, s7
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -460,25 +458,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ; GFX1064-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-NEXT:    s_mov_b32 s12, s8
+; GFX1064-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-NEXT:    s_mov_b32 s14, s10
-; GFX1064-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-NEXT:    s_mov_b32 s12, s6
+; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
@@ -530,25 +527,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ; GFX1032-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-NEXT:    s_mov_b32 s12, s8
+; GFX1032-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-NEXT:    s_mov_b32 s14, s10
-; GFX1032-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-NEXT:    s_mov_b32 s12, s6
+; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
@@ -592,23 +588,22 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ;
 ; GFX1164-LABEL: global_atomic_fadd_uni_address_div_value_agent_scope_align4_unsafe:
 ; GFX1164:       ; %bb.0:
-; GFX1164-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-NEXT:    s_mov_b32 s12, s8
+; GFX1164-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-NEXT:    s_mov_b32 s14, s10
-; GFX1164-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s12, s6
+; GFX1164-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX1164-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX1164-NEXT:  .LBB1_1: ; %ComputeLoop
@@ -646,23 +641,22 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ;
 ; GFX1132-LABEL: global_atomic_fadd_uni_address_div_value_agent_scope_align4_unsafe:
 ; GFX1132:       ; %bb.0:
-; GFX1132-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-NEXT:    s_mov_b32 s12, s13
-; GFX1132-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX1132-NEXT:    s_mov_b32 s0, exec_lo
 ; GFX1132-NEXT:  .LBB1_1: ; %ComputeLoop
@@ -700,25 +694,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ; GFX9-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX9-DPP-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX9-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX9-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX9-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX9-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -785,25 +778,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ; GFX1064-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1064-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -868,25 +860,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ; GFX1032-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1032-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -941,23 +932,22 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ;
 ; GFX1164-DPP-LABEL: global_atomic_fadd_uni_address_div_value_agent_scope_align4_unsafe:
 ; GFX1164-DPP:       ; %bb.0:
-; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-DPP-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1164-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-DPP-NEXT:    s_or_saveexec_b64 s[0:1], -1
 ; GFX1164-DPP-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX1164-DPP-NEXT:    s_mov_b64 exec, s[0:1]
@@ -1013,23 +1003,22 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ;
 ; GFX1132-DPP-LABEL: global_atomic_fadd_uni_address_div_value_agent_scope_align4_unsafe:
 ; GFX1132-DPP:       ; %bb.0:
-; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-DPP-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-DPP-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-DPP-NEXT:    s_mov_b32 s12, s13
-; GFX1132-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-DPP-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-DPP-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-DPP-NEXT:    s_or_saveexec_b32 s0, -1
 ; GFX1132-DPP-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX1132-DPP-NEXT:    s_mov_b32 exec_lo, s0
@@ -1546,27 +1535,26 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_one_as_scope
 ; GFX7LESS-NEXT:    s_mov_b32 s41, SCRATCH_RSRC_DWORD1
 ; GFX7LESS-NEXT:    s_mov_b32 s42, -1
 ; GFX7LESS-NEXT:    s_mov_b32 s43, 0xe8f000
-; GFX7LESS-NEXT:    s_add_u32 s40, s40, s11
+; GFX7LESS-NEXT:    s_add_u32 s40, s40, s9
 ; GFX7LESS-NEXT:    s_addc_u32 s41, s41, 0
-; GFX7LESS-NEXT:    s_mov_b32 s14, s10
-; GFX7LESS-NEXT:    s_mov_b32 s13, s9
-; GFX7LESS-NEXT:    s_mov_b32 s12, s8
-; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[6:7]
-; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[4:5], 0x9
+; GFX7LESS-NEXT:    s_mov_b32 s14, s8
+; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[4:5]
+; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[2:3], 0x9
 ; GFX7LESS-NEXT:    s_mov_b32 s39, 0xf000
 ; GFX7LESS-NEXT:    s_mov_b32 s38, -1
-; GFX7LESS-NEXT:    s_add_u32 s8, s4, 44
-; GFX7LESS-NEXT:    s_addc_u32 s9, s5, 0
-; GFX7LESS-NEXT:    s_getpc_b64 s[4:5]
-; GFX7LESS-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX7LESS-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX7LESS-NEXT:    s_add_u32 s8, s2, 44
+; GFX7LESS-NEXT:    s_addc_u32 s9, s3, 0
+; GFX7LESS-NEXT:    s_getpc_b64 s[2:3]
+; GFX7LESS-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX7LESS-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v31, v0, v2
 ; GFX7LESS-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX7LESS-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX7LESS-NEXT:    s_mov_b32 s12, s6
+; GFX7LESS-NEXT:    s_mov_b32 s13, s7
 ; GFX7LESS-NEXT:    s_mov_b64 s[0:1], s[40:41]
 ; GFX7LESS-NEXT:    s_mov_b64 s[2:3], s[42:43]
 ; GFX7LESS-NEXT:    s_waitcnt lgkmcnt(0)
@@ -1596,25 +1584,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_one_as_scope
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-NEXT:    s_mov_b32 s12, s8
+; GFX9-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-NEXT:    s_mov_b32 s14, s8
 ; GFX9-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-NEXT:    s_mov_b32 s13, s9
 ; GFX9-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT:    s_mov_b32 s14, s10
-; GFX9-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-NEXT:    s_mov_b32 s12, s6
+; GFX9-NEXT:    s_mov_b32 s13, s7
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -1666,25 +1653,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_one_as_scope
 ; GFX1064-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-NEXT:    s_mov_b32 s12, s8
+; GFX1064-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-NEXT:    s_mov_b32 s14, s10
-; GFX1064-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-NEXT:    s_mov_b32 s12, s6
+; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
@@ -1736,25 +1722,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_one_as_scope
 ; GFX1032-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-NEXT:    s_mov_b32 s12, s8
+; GFX1032-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-NEXT:    s_mov_b32 s14, s10
-; GFX1032-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-NEXT:    s_mov_b32 s12, s6
+; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
@@ -1798,23 +1783,22 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_one_as_scope
 ;
 ; GFX1164-LABEL: global_atomic_fadd_uni_address_div_value_one_as_scope_unsafe_structfp:
 ; GFX1164:       ; %bb.0:
-; GFX1164-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-NEXT:    s_mov_b32 s12, s8
+; GFX1164-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-NEXT:    s_mov_b32 s14, s10
-; GFX1164-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s12, s6
+; GFX1164-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-NEXT:    v_bfrev_b32_e32 v2, 1
 ; GFX1164-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX1164-NEXT:  .LBB3_1: ; %ComputeLoop
@@ -1863,23 +1847,22 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_one_as_scope
 ;
 ; GFX1132-LABEL: global_atomic_fadd_uni_address_div_value_one_as_scope_unsafe_structfp:
 ; GFX1132:       ; %bb.0:
-; GFX1132-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-NEXT:    s_mov_b32 s12, s13
-; GFX1132-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-NEXT:    v_bfrev_b32_e32 v2, 1
 ; GFX1132-NEXT:    s_mov_b32 s0, exec_lo
 ; GFX1132-NEXT:  .LBB3_1: ; %ComputeLoop
@@ -1928,25 +1911,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_one_as_scope
 ; GFX9-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX9-DPP-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX9-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX9-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX9-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX9-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2013,25 +1995,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_one_as_scope
 ; GFX1064-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1064-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2096,25 +2077,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_one_as_scope
 ; GFX1032-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1032-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2169,23 +2149,22 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_one_as_scope
 ;
 ; GFX1164-DPP-LABEL: global_atomic_fadd_uni_address_div_value_one_as_scope_unsafe_structfp:
 ; GFX1164-DPP:       ; %bb.0:
-; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-DPP-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1164-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-DPP-NEXT:    s_or_saveexec_b64 s[0:1], -1
 ; GFX1164-DPP-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX1164-DPP-NEXT:    s_mov_b64 exec, s[0:1]
@@ -2252,23 +2231,22 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_one_as_scope
 ;
 ; GFX1132-DPP-LABEL: global_atomic_fadd_uni_address_div_value_one_as_scope_unsafe_structfp:
 ; GFX1132-DPP:       ; %bb.0:
-; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-DPP-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-DPP-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-DPP-NEXT:    s_mov_b32 s12, s13
-; GFX1132-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-DPP-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-DPP-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-DPP-NEXT:    s_or_saveexec_b32 s0, -1
 ; GFX1132-DPP-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX1132-DPP-NEXT:    s_mov_b32 exec_lo, s0
@@ -2796,27 +2774,26 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ; GFX7LESS-NEXT:    s_mov_b32 s41, SCRATCH_RSRC_DWORD1
 ; GFX7LESS-NEXT:    s_mov_b32 s42, -1
 ; GFX7LESS-NEXT:    s_mov_b32 s43, 0xe8f000
-; GFX7LESS-NEXT:    s_add_u32 s40, s40, s11
+; GFX7LESS-NEXT:    s_add_u32 s40, s40, s9
 ; GFX7LESS-NEXT:    s_addc_u32 s41, s41, 0
-; GFX7LESS-NEXT:    s_mov_b32 s14, s10
-; GFX7LESS-NEXT:    s_mov_b32 s13, s9
-; GFX7LESS-NEXT:    s_mov_b32 s12, s8
-; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[6:7]
-; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[4:5], 0x9
+; GFX7LESS-NEXT:    s_mov_b32 s14, s8
+; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[4:5]
+; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[2:3], 0x9
 ; GFX7LESS-NEXT:    s_mov_b32 s39, 0xf000
 ; GFX7LESS-NEXT:    s_mov_b32 s38, -1
-; GFX7LESS-NEXT:    s_add_u32 s8, s4, 44
-; GFX7LESS-NEXT:    s_addc_u32 s9, s5, 0
-; GFX7LESS-NEXT:    s_getpc_b64 s[4:5]
-; GFX7LESS-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX7LESS-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX7LESS-NEXT:    s_add_u32 s8, s2, 44
+; GFX7LESS-NEXT:    s_addc_u32 s9, s3, 0
+; GFX7LESS-NEXT:    s_getpc_b64 s[2:3]
+; GFX7LESS-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX7LESS-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v31, v0, v2
 ; GFX7LESS-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX7LESS-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX7LESS-NEXT:    s_mov_b32 s12, s6
+; GFX7LESS-NEXT:    s_mov_b32 s13, s7
 ; GFX7LESS-NEXT:    s_mov_b64 s[0:1], s[40:41]
 ; GFX7LESS-NEXT:    s_mov_b64 s[2:3], s[42:43]
 ; GFX7LESS-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2846,25 +2823,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-NEXT:    s_mov_b32 s12, s8
+; GFX9-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-NEXT:    s_mov_b32 s14, s8
 ; GFX9-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-NEXT:    s_mov_b32 s13, s9
 ; GFX9-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT:    s_mov_b32 s14, s10
-; GFX9-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-NEXT:    s_mov_b32 s12, s6
+; GFX9-NEXT:    s_mov_b32 s13, s7
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2916,25 +2892,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ; GFX1064-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-NEXT:    s_mov_b32 s12, s8
+; GFX1064-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-NEXT:    s_mov_b32 s14, s10
-; GFX1064-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-NEXT:    s_mov_b32 s12, s6
+; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2986,25 +2961,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ; GFX1032-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-NEXT:    s_mov_b32 s12, s8
+; GFX1032-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-NEXT:    s_mov_b32 s14, s10
-; GFX1032-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-NEXT:    s_mov_b32 s12, s6
+; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
@@ -3048,23 +3022,22 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ;
 ; GFX1164-LABEL: global_atomic_fadd_uni_address_div_value_agent_scope_unsafe:
 ; GFX1164:       ; %bb.0:
-; GFX1164-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-NEXT:    s_mov_b32 s12, s8
+; GFX1164-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-NEXT:    s_mov_b32 s14, s10
-; GFX1164-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s12, s6
+; GFX1164-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX1164-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX1164-NEXT:  .LBB5_1: ; %ComputeLoop
@@ -3102,23 +3075,22 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ;
 ; GFX1132-LABEL: global_atomic_fadd_uni_address_div_value_agent_scope_unsafe:
 ; GFX1132:       ; %bb.0:
-; GFX1132-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-NEXT:    s_mov_b32 s12, s13
-; GFX1132-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX1132-NEXT:    s_mov_b32 s0, exec_lo
 ; GFX1132-NEXT:  .LBB5_1: ; %ComputeLoop
@@ -3156,25 +3128,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ; GFX9-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX9-DPP-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX9-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX9-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX9-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX9-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -3241,25 +3212,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ; GFX1064-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1064-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -3324,25 +3294,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ; GFX1032-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1032-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -3397,23 +3366,22 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ;
 ; GFX1164-DPP-LABEL: global_atomic_fadd_uni_address_div_value_agent_scope_unsafe:
 ; GFX1164-DPP:       ; %bb.0:
-; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-DPP-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1164-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-DPP-NEXT:    s_or_saveexec_b64 s[0:1], -1
 ; GFX1164-DPP-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX1164-DPP-NEXT:    s_mov_b64 exec, s[0:1]
@@ -3469,23 +3437,22 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ;
 ; GFX1132-DPP-LABEL: global_atomic_fadd_uni_address_div_value_agent_scope_unsafe:
 ; GFX1132-DPP:       ; %bb.0:
-; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-DPP-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-DPP-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-DPP-NEXT:    s_mov_b32 s12, s13
-; GFX1132-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-DPP-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-DPP-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-DPP-NEXT:    s_or_saveexec_b32 s0, -1
 ; GFX1132-DPP-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX1132-DPP-NEXT:    s_mov_b32 exec_lo, s0
@@ -3544,27 +3511,26 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ; GFX7LESS-NEXT:    s_mov_b32 s41, SCRATCH_RSRC_DWORD1
 ; GFX7LESS-NEXT:    s_mov_b32 s42, -1
 ; GFX7LESS-NEXT:    s_mov_b32 s43, 0xe8f000
-; GFX7LESS-NEXT:    s_add_u32 s40, s40, s11
+; GFX7LESS-NEXT:    s_add_u32 s40, s40, s9
 ; GFX7LESS-NEXT:    s_addc_u32 s41, s41, 0
-; GFX7LESS-NEXT:    s_mov_b32 s14, s10
-; GFX7LESS-NEXT:    s_mov_b32 s13, s9
-; GFX7LESS-NEXT:    s_mov_b32 s12, s8
-; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[6:7]
-; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[4:5], 0x9
+; GFX7LESS-NEXT:    s_mov_b32 s14, s8
+; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[4:5]
+; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[2:3], 0x9
 ; GFX7LESS-NEXT:    s_mov_b32 s39, 0xf000
 ; GFX7LESS-NEXT:    s_mov_b32 s38, -1
-; GFX7LESS-NEXT:    s_add_u32 s8, s4, 44
-; GFX7LESS-NEXT:    s_addc_u32 s9, s5, 0
-; GFX7LESS-NEXT:    s_getpc_b64 s[4:5]
-; GFX7LESS-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX7LESS-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX7LESS-NEXT:    s_add_u32 s8, s2, 44
+; GFX7LESS-NEXT:    s_addc_u32 s9, s3, 0
+; GFX7LESS-NEXT:    s_getpc_b64 s[2:3]
+; GFX7LESS-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX7LESS-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v31, v0, v2
 ; GFX7LESS-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX7LESS-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX7LESS-NEXT:    s_mov_b32 s12, s6
+; GFX7LESS-NEXT:    s_mov_b32 s13, s7
 ; GFX7LESS-NEXT:    s_mov_b64 s[0:1], s[40:41]
 ; GFX7LESS-NEXT:    s_mov_b64 s[2:3], s[42:43]
 ; GFX7LESS-NEXT:    s_waitcnt lgkmcnt(0)
@@ -3594,25 +3560,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-NEXT:    s_mov_b32 s12, s8
+; GFX9-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-NEXT:    s_mov_b32 s14, s8
 ; GFX9-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-NEXT:    s_mov_b32 s13, s9
 ; GFX9-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT:    s_mov_b32 s14, s10
-; GFX9-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-NEXT:    s_mov_b32 s12, s6
+; GFX9-NEXT:    s_mov_b32 s13, s7
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -3664,25 +3629,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ; GFX1064-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-NEXT:    s_mov_b32 s12, s8
+; GFX1064-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-NEXT:    s_mov_b32 s14, s10
-; GFX1064-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-NEXT:    s_mov_b32 s12, s6
+; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
@@ -3734,25 +3698,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ; GFX1032-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-NEXT:    s_mov_b32 s12, s8
+; GFX1032-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-NEXT:    s_mov_b32 s14, s10
-; GFX1032-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-NEXT:    s_mov_b32 s12, s6
+; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
@@ -3796,23 +3759,22 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ;
 ; GFX1164-LABEL: global_atomic_fadd_uni_address_div_value_agent_scope_unsafe_structfp:
 ; GFX1164:       ; %bb.0:
-; GFX1164-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-NEXT:    s_mov_b32 s12, s8
+; GFX1164-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-NEXT:    s_mov_b32 s14, s10
-; GFX1164-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s12, s6
+; GFX1164-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX1164-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX1164-NEXT:  .LBB6_1: ; %ComputeLoop
@@ -3850,23 +3812,22 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ;
 ; GFX1132-LABEL: global_atomic_fadd_uni_address_div_value_agent_scope_unsafe_structfp:
 ; GFX1132:       ; %bb.0:
-; GFX1132-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-NEXT:    s_mov_b32 s12, s13
-; GFX1132-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX1132-NEXT:    s_mov_b32 s0, exec_lo
 ; GFX1132-NEXT:  .LBB6_1: ; %ComputeLoop
@@ -3904,25 +3865,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ; GFX9-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX9-DPP-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX9-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX9-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX9-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX9-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -3989,25 +3949,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ; GFX1064-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1064-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -4072,25 +4031,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ; GFX1032-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1032-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -4145,23 +4103,22 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ;
 ; GFX1164-DPP-LABEL: global_atomic_fadd_uni_address_div_value_agent_scope_unsafe_structfp:
 ; GFX1164-DPP:       ; %bb.0:
-; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-DPP-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1164-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-DPP-NEXT:    s_or_saveexec_b64 s[0:1], -1
 ; GFX1164-DPP-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX1164-DPP-NEXT:    s_mov_b64 exec, s[0:1]
@@ -4217,23 +4174,22 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
 ;
 ; GFX1132-DPP-LABEL: global_atomic_fadd_uni_address_div_value_agent_scope_unsafe_structfp:
 ; GFX1132-DPP:       ; %bb.0:
-; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-DPP-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-DPP-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-DPP-NEXT:    s_mov_b32 s12, s13
-; GFX1132-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-DPP-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-DPP-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-DPP-NEXT:    s_or_saveexec_b32 s0, -1
 ; GFX1132-DPP-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX1132-DPP-NEXT:    s_mov_b32 exec_lo, s0
@@ -4749,27 +4705,26 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_defalut_scop
 ; GFX7LESS-NEXT:    s_mov_b32 s41, SCRATCH_RSRC_DWORD1
 ; GFX7LESS-NEXT:    s_mov_b32 s42, -1
 ; GFX7LESS-NEXT:    s_mov_b32 s43, 0xe8f000
-; GFX7LESS-NEXT:    s_add_u32 s40, s40, s11
+; GFX7LESS-NEXT:    s_add_u32 s40, s40, s9
 ; GFX7LESS-NEXT:    s_addc_u32 s41, s41, 0
-; GFX7LESS-NEXT:    s_mov_b32 s14, s10
-; GFX7LESS-NEXT:    s_mov_b32 s13, s9
-; GFX7LESS-NEXT:    s_mov_b32 s12, s8
-; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[6:7]
-; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[4:5], 0x9
+; GFX7LESS-NEXT:    s_mov_b32 s14, s8
+; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[4:5]
+; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[2:3], 0x9
 ; GFX7LESS-NEXT:    s_mov_b32 s39, 0xf000
 ; GFX7LESS-NEXT:    s_mov_b32 s38, -1
-; GFX7LESS-NEXT:    s_add_u32 s8, s4, 44
-; GFX7LESS-NEXT:    s_addc_u32 s9, s5, 0
-; GFX7LESS-NEXT:    s_getpc_b64 s[4:5]
-; GFX7LESS-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX7LESS-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX7LESS-NEXT:    s_add_u32 s8, s2, 44
+; GFX7LESS-NEXT:    s_addc_u32 s9, s3, 0
+; GFX7LESS-NEXT:    s_getpc_b64 s[2:3]
+; GFX7LESS-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX7LESS-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v31, v0, v2
 ; GFX7LESS-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX7LESS-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX7LESS-NEXT:    s_mov_b32 s12, s6
+; GFX7LESS-NEXT:    s_mov_b32 s13, s7
 ; GFX7LESS-NEXT:    s_mov_b64 s[0:1], s[40:41]
 ; GFX7LESS-NEXT:    s_mov_b64 s[2:3], s[42:43]
 ; GFX7LESS-NEXT:    s_waitcnt lgkmcnt(0)
@@ -4799,25 +4754,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_defalut_scop
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-NEXT:    s_mov_b32 s12, s8
+; GFX9-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-NEXT:    s_mov_b32 s14, s8
 ; GFX9-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-NEXT:    s_mov_b32 s13, s9
 ; GFX9-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT:    s_mov_b32 s14, s10
-; GFX9-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-NEXT:    s_mov_b32 s12, s6
+; GFX9-NEXT:    s_mov_b32 s13, s7
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -4869,25 +4823,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_defalut_scop
 ; GFX1064-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-NEXT:    s_mov_b32 s12, s8
+; GFX1064-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-NEXT:    s_mov_b32 s14, s10
-; GFX1064-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-NEXT:    s_mov_b32 s12, s6
+; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
@@ -4939,25 +4892,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_defalut_scop
 ; GFX1032-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-NEXT:    s_mov_b32 s12, s8
+; GFX1032-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-NEXT:    s_mov_b32 s14, s10
-; GFX1032-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-NEXT:    s_mov_b32 s12, s6
+; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
@@ -5001,23 +4953,22 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_defalut_scop
 ;
 ; GFX1164-LABEL: global_atomic_fadd_uni_address_div_value_defalut_scope_strictfp:
 ; GFX1164:       ; %bb.0:
-; GFX1164-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-NEXT:    s_mov_b32 s12, s8
+; GFX1164-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-NEXT:    s_mov_b32 s14, s10
-; GFX1164-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s12, s6
+; GFX1164-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-NEXT:    v_bfrev_b32_e32 v2, 1
 ; GFX1164-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX1164-NEXT:  .LBB8_1: ; %ComputeLoop
@@ -5066,23 +5017,22 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_defalut_scop
 ;
 ; GFX1132-LABEL: global_atomic_fadd_uni_address_div_value_defalut_scope_strictfp:
 ; GFX1132:       ; %bb.0:
-; GFX1132-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-NEXT:    s_mov_b32 s12, s13
-; GFX1132-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-NEXT:    v_bfrev_b32_e32 v2, 1
 ; GFX1132-NEXT:    s_mov_b32 s0, exec_lo
 ; GFX1132-NEXT:  .LBB8_1: ; %ComputeLoop
@@ -5131,25 +5081,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_defalut_scop
 ; GFX9-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX9-DPP-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX9-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX9-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX9-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX9-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -5216,25 +5165,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_defalut_scop
 ; GFX1064-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1064-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -5299,25 +5247,24 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_defalut_scop
 ; GFX1032-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1032-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -5372,23 +5319,22 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_defalut_scop
 ;
 ; GFX1164-DPP-LABEL: global_atomic_fadd_uni_address_div_value_defalut_scope_strictfp:
 ; GFX1164-DPP:       ; %bb.0:
-; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-DPP-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1164-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-DPP-NEXT:    s_or_saveexec_b64 s[0:1], -1
 ; GFX1164-DPP-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX1164-DPP-NEXT:    s_mov_b64 exec, s[0:1]
@@ -5455,23 +5401,22 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_defalut_scop
 ;
 ; GFX1132-DPP-LABEL: global_atomic_fadd_uni_address_div_value_defalut_scope_strictfp:
 ; GFX1132-DPP:       ; %bb.0:
-; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-DPP-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-DPP-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-DPP-NEXT:    s_mov_b32 s12, s13
-; GFX1132-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-DPP-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-DPP-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-DPP-NEXT:    s_or_saveexec_b32 s0, -1
 ; GFX1132-DPP-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX1132-DPP-NEXT:    s_mov_b32 exec_lo, s0
@@ -5535,3 +5480,6 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_defalut_scop
 attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" "amdgpu-unsafe-fp-atomics"="true" }
 attributes #1 = { strictfp "denormal-fp-math-f32"="preserve-sign,preserve-sign" "amdgpu-unsafe-fp-atomics"="true" }
 attributes #2 = { strictfp}
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"amdgpu_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
index e07514b063ee..66c89de1789e 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
@@ -357,27 +357,26 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_agent_scope_
 ; GFX7LESS-NEXT:    s_mov_b32 s41, SCRATCH_RSRC_DWORD1
 ; GFX7LESS-NEXT:    s_mov_b32 s42, -1
 ; GFX7LESS-NEXT:    s_mov_b32 s43, 0xe8f000
-; GFX7LESS-NEXT:    s_add_u32 s40, s40, s11
+; GFX7LESS-NEXT:    s_add_u32 s40, s40, s9
 ; GFX7LESS-NEXT:    s_addc_u32 s41, s41, 0
-; GFX7LESS-NEXT:    s_mov_b32 s14, s10
-; GFX7LESS-NEXT:    s_mov_b32 s13, s9
-; GFX7LESS-NEXT:    s_mov_b32 s12, s8
-; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[6:7]
-; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[4:5], 0x9
+; GFX7LESS-NEXT:    s_mov_b32 s14, s8
+; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[4:5]
+; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[2:3], 0x9
 ; GFX7LESS-NEXT:    s_mov_b32 s39, 0xf000
 ; GFX7LESS-NEXT:    s_mov_b32 s38, -1
-; GFX7LESS-NEXT:    s_add_u32 s8, s4, 44
-; GFX7LESS-NEXT:    s_addc_u32 s9, s5, 0
-; GFX7LESS-NEXT:    s_getpc_b64 s[4:5]
-; GFX7LESS-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX7LESS-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX7LESS-NEXT:    s_add_u32 s8, s2, 44
+; GFX7LESS-NEXT:    s_addc_u32 s9, s3, 0
+; GFX7LESS-NEXT:    s_getpc_b64 s[2:3]
+; GFX7LESS-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX7LESS-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v31, v0, v2
 ; GFX7LESS-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX7LESS-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX7LESS-NEXT:    s_mov_b32 s12, s6
+; GFX7LESS-NEXT:    s_mov_b32 s13, s7
 ; GFX7LESS-NEXT:    s_mov_b64 s[0:1], s[40:41]
 ; GFX7LESS-NEXT:    s_mov_b64 s[2:3], s[42:43]
 ; GFX7LESS-NEXT:    s_waitcnt lgkmcnt(0)
@@ -409,25 +408,24 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_agent_scope_
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-NEXT:    s_mov_b32 s12, s8
+; GFX9-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-NEXT:    s_mov_b32 s14, s8
 ; GFX9-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-NEXT:    s_mov_b32 s13, s9
 ; GFX9-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT:    s_mov_b32 s14, s10
-; GFX9-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-NEXT:    s_mov_b32 s12, s6
+; GFX9-NEXT:    s_mov_b32 s13, s7
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -483,25 +481,24 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_agent_scope_
 ; GFX1064-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-NEXT:    s_mov_b32 s12, s8
+; GFX1064-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-NEXT:    s_mov_b32 s14, s10
-; GFX1064-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-NEXT:    s_mov_b32 s12, s6
+; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
@@ -557,25 +554,24 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_agent_scope_
 ; GFX1032-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-NEXT:    s_mov_b32 s12, s8
+; GFX1032-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-NEXT:    s_mov_b32 s14, s10
-; GFX1032-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-NEXT:    s_mov_b32 s12, s6
+; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
@@ -623,23 +619,22 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_agent_scope_
 ;
 ; GFX1164-LABEL: global_atomic_fmax_uni_address_div_value_agent_scope_unsafe:
 ; GFX1164:       ; %bb.0:
-; GFX1164-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-NEXT:    s_mov_b32 s12, s8
+; GFX1164-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-NEXT:    s_mov_b32 s14, s10
-; GFX1164-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s12, s6
+; GFX1164-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-NEXT:    v_mov_b32_e32 v2, 0xff800000
 ; GFX1164-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX1164-NEXT:  .LBB1_1: ; %ComputeLoop
@@ -693,23 +688,22 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_agent_scope_
 ;
 ; GFX1132-LABEL: global_atomic_fmax_uni_address_div_value_agent_scope_unsafe:
 ; GFX1132:       ; %bb.0:
-; GFX1132-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-NEXT:    s_mov_b32 s12, s13
-; GFX1132-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-NEXT:    v_mov_b32_e32 v2, 0xff800000
 ; GFX1132-NEXT:    s_mov_b32 s0, exec_lo
 ; GFX1132-NEXT:  .LBB1_1: ; %ComputeLoop
@@ -762,25 +756,24 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_agent_scope_
 ; GFX9-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX9-DPP-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX9-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX9-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX9-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX9-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -856,25 +849,24 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_agent_scope_
 ; GFX1064-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1064-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -949,25 +941,24 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_agent_scope_
 ; GFX1032-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1032-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -1030,23 +1021,22 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_agent_scope_
 ;
 ; GFX1164-DPP-LABEL: global_atomic_fmax_uni_address_div_value_agent_scope_unsafe:
 ; GFX1164-DPP:       ; %bb.0:
-; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-DPP-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1164-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-DPP-NEXT:    s_or_saveexec_b64 s[0:1], -1
 ; GFX1164-DPP-NEXT:    v_mov_b32_e32 v1, 0xff800000
 ; GFX1164-DPP-NEXT:    s_mov_b64 exec, s[0:1]
@@ -1126,23 +1116,22 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_agent_scope_
 ;
 ; GFX1132-DPP-LABEL: global_atomic_fmax_uni_address_div_value_agent_scope_unsafe:
 ; GFX1132-DPP:       ; %bb.0:
-; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-DPP-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-DPP-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-DPP-NEXT:    s_mov_b32 s12, s13
-; GFX1132-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-DPP-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-DPP-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-DPP-NEXT:    s_or_saveexec_b32 s0, -1
 ; GFX1132-DPP-NEXT:    v_mov_b32_e32 v1, 0xff800000
 ; GFX1132-DPP-NEXT:    s_mov_b32 exec_lo, s0
@@ -1556,27 +1545,26 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_one_as_scope
 ; GFX7LESS-NEXT:    s_mov_b32 s41, SCRATCH_RSRC_DWORD1
 ; GFX7LESS-NEXT:    s_mov_b32 s42, -1
 ; GFX7LESS-NEXT:    s_mov_b32 s43, 0xe8f000
-; GFX7LESS-NEXT:    s_add_u32 s40, s40, s11
+; GFX7LESS-NEXT:    s_add_u32 s40, s40, s9
 ; GFX7LESS-NEXT:    s_addc_u32 s41, s41, 0
-; GFX7LESS-NEXT:    s_mov_b32 s14, s10
-; GFX7LESS-NEXT:    s_mov_b32 s13, s9
-; GFX7LESS-NEXT:    s_mov_b32 s12, s8
-; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[6:7]
-; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[4:5], 0x9
+; GFX7LESS-NEXT:    s_mov_b32 s14, s8
+; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[4:5]
+; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[2:3], 0x9
 ; GFX7LESS-NEXT:    s_mov_b32 s39, 0xf000
 ; GFX7LESS-NEXT:    s_mov_b32 s38, -1
-; GFX7LESS-NEXT:    s_add_u32 s8, s4, 44
-; GFX7LESS-NEXT:    s_addc_u32 s9, s5, 0
-; GFX7LESS-NEXT:    s_getpc_b64 s[4:5]
-; GFX7LESS-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX7LESS-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX7LESS-NEXT:    s_add_u32 s8, s2, 44
+; GFX7LESS-NEXT:    s_addc_u32 s9, s3, 0
+; GFX7LESS-NEXT:    s_getpc_b64 s[2:3]
+; GFX7LESS-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX7LESS-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v31, v0, v2
 ; GFX7LESS-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX7LESS-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX7LESS-NEXT:    s_mov_b32 s12, s6
+; GFX7LESS-NEXT:    s_mov_b32 s13, s7
 ; GFX7LESS-NEXT:    s_mov_b64 s[0:1], s[40:41]
 ; GFX7LESS-NEXT:    s_mov_b64 s[2:3], s[42:43]
 ; GFX7LESS-NEXT:    s_waitcnt lgkmcnt(0)
@@ -1608,25 +1596,24 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_one_as_scope
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-NEXT:    s_mov_b32 s12, s8
+; GFX9-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-NEXT:    s_mov_b32 s14, s8
 ; GFX9-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-NEXT:    s_mov_b32 s13, s9
 ; GFX9-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT:    s_mov_b32 s14, s10
-; GFX9-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-NEXT:    s_mov_b32 s12, s6
+; GFX9-NEXT:    s_mov_b32 s13, s7
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -1682,25 +1669,24 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_one_as_scope
 ; GFX1064-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-NEXT:    s_mov_b32 s12, s8
+; GFX1064-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-NEXT:    s_mov_b32 s14, s10
-; GFX1064-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-NEXT:    s_mov_b32 s12, s6
+; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
@@ -1756,25 +1742,24 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_one_as_scope
 ; GFX1032-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-NEXT:    s_mov_b32 s12, s8
+; GFX1032-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-NEXT:    s_mov_b32 s14, s10
-; GFX1032-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-NEXT:    s_mov_b32 s12, s6
+; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
@@ -1822,23 +1807,22 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_one_as_scope
 ;
 ; GFX1164-LABEL: global_atomic_fmax_uni_address_div_value_one_as_scope_unsafe:
 ; GFX1164:       ; %bb.0:
-; GFX1164-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-NEXT:    s_mov_b32 s12, s8
+; GFX1164-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-NEXT:    s_mov_b32 s14, s10
-; GFX1164-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s12, s6
+; GFX1164-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-NEXT:    v_mov_b32_e32 v2, 0xff800000
 ; GFX1164-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX1164-NEXT:  .LBB3_1: ; %ComputeLoop
@@ -1892,23 +1876,22 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_one_as_scope
 ;
 ; GFX1132-LABEL: global_atomic_fmax_uni_address_div_value_one_as_scope_unsafe:
 ; GFX1132:       ; %bb.0:
-; GFX1132-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-NEXT:    s_mov_b32 s12, s13
-; GFX1132-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-NEXT:    v_mov_b32_e32 v2, 0xff800000
 ; GFX1132-NEXT:    s_mov_b32 s0, exec_lo
 ; GFX1132-NEXT:  .LBB3_1: ; %ComputeLoop
@@ -1961,25 +1944,24 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_one_as_scope
 ; GFX9-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX9-DPP-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX9-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX9-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX9-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX9-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2055,25 +2037,24 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_one_as_scope
 ; GFX1064-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1064-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2148,25 +2129,24 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_one_as_scope
 ; GFX1032-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1032-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2229,23 +2209,22 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_one_as_scope
 ;
 ; GFX1164-DPP-LABEL: global_atomic_fmax_uni_address_div_value_one_as_scope_unsafe:
 ; GFX1164-DPP:       ; %bb.0:
-; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-DPP-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1164-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-DPP-NEXT:    s_or_saveexec_b64 s[0:1], -1
 ; GFX1164-DPP-NEXT:    v_mov_b32_e32 v1, 0xff800000
 ; GFX1164-DPP-NEXT:    s_mov_b64 exec, s[0:1]
@@ -2325,23 +2304,22 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_one_as_scope
 ;
 ; GFX1132-DPP-LABEL: global_atomic_fmax_uni_address_div_value_one_as_scope_unsafe:
 ; GFX1132-DPP:       ; %bb.0:
-; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-DPP-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-DPP-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-DPP-NEXT:    s_mov_b32 s12, s13
-; GFX1132-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-DPP-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-DPP-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-DPP-NEXT:    s_or_saveexec_b32 s0, -1
 ; GFX1132-DPP-NEXT:    v_mov_b32_e32 v1, 0xff800000
 ; GFX1132-DPP-NEXT:    s_mov_b32 exec_lo, s0
@@ -2755,27 +2733,26 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_defalut_scop
 ; GFX7LESS-NEXT:    s_mov_b32 s41, SCRATCH_RSRC_DWORD1
 ; GFX7LESS-NEXT:    s_mov_b32 s42, -1
 ; GFX7LESS-NEXT:    s_mov_b32 s43, 0xe8f000
-; GFX7LESS-NEXT:    s_add_u32 s40, s40, s11
+; GFX7LESS-NEXT:    s_add_u32 s40, s40, s9
 ; GFX7LESS-NEXT:    s_addc_u32 s41, s41, 0
-; GFX7LESS-NEXT:    s_mov_b32 s14, s10
-; GFX7LESS-NEXT:    s_mov_b32 s13, s9
-; GFX7LESS-NEXT:    s_mov_b32 s12, s8
-; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[6:7]
-; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[4:5], 0x9
+; GFX7LESS-NEXT:    s_mov_b32 s14, s8
+; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[4:5]
+; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[2:3], 0x9
 ; GFX7LESS-NEXT:    s_mov_b32 s39, 0xf000
 ; GFX7LESS-NEXT:    s_mov_b32 s38, -1
-; GFX7LESS-NEXT:    s_add_u32 s8, s4, 44
-; GFX7LESS-NEXT:    s_addc_u32 s9, s5, 0
-; GFX7LESS-NEXT:    s_getpc_b64 s[4:5]
-; GFX7LESS-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX7LESS-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX7LESS-NEXT:    s_add_u32 s8, s2, 44
+; GFX7LESS-NEXT:    s_addc_u32 s9, s3, 0
+; GFX7LESS-NEXT:    s_getpc_b64 s[2:3]
+; GFX7LESS-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX7LESS-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v31, v0, v2
 ; GFX7LESS-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX7LESS-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX7LESS-NEXT:    s_mov_b32 s12, s6
+; GFX7LESS-NEXT:    s_mov_b32 s13, s7
 ; GFX7LESS-NEXT:    s_mov_b64 s[0:1], s[40:41]
 ; GFX7LESS-NEXT:    s_mov_b64 s[2:3], s[42:43]
 ; GFX7LESS-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2807,25 +2784,24 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_defalut_scop
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-NEXT:    s_mov_b32 s12, s8
+; GFX9-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-NEXT:    s_mov_b32 s14, s8
 ; GFX9-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-NEXT:    s_mov_b32 s13, s9
 ; GFX9-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT:    s_mov_b32 s14, s10
-; GFX9-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-NEXT:    s_mov_b32 s12, s6
+; GFX9-NEXT:    s_mov_b32 s13, s7
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2881,25 +2857,24 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_defalut_scop
 ; GFX1064-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-NEXT:    s_mov_b32 s12, s8
+; GFX1064-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-NEXT:    s_mov_b32 s14, s10
-; GFX1064-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-NEXT:    s_mov_b32 s12, s6
+; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2955,25 +2930,24 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_defalut_scop
 ; GFX1032-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-NEXT:    s_mov_b32 s12, s8
+; GFX1032-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-NEXT:    s_mov_b32 s14, s10
-; GFX1032-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-NEXT:    s_mov_b32 s12, s6
+; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
@@ -3021,23 +2995,22 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_defalut_scop
 ;
 ; GFX1164-LABEL: global_atomic_fmax_uni_address_div_value_defalut_scope_unsafe:
 ; GFX1164:       ; %bb.0:
-; GFX1164-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-NEXT:    s_mov_b32 s12, s8
+; GFX1164-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-NEXT:    s_mov_b32 s14, s10
-; GFX1164-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s12, s6
+; GFX1164-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-NEXT:    v_mov_b32_e32 v2, 0xff800000
 ; GFX1164-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX1164-NEXT:  .LBB5_1: ; %ComputeLoop
@@ -3091,23 +3064,22 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_defalut_scop
 ;
 ; GFX1132-LABEL: global_atomic_fmax_uni_address_div_value_defalut_scope_unsafe:
 ; GFX1132:       ; %bb.0:
-; GFX1132-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-NEXT:    s_mov_b32 s12, s13
-; GFX1132-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-NEXT:    v_mov_b32_e32 v2, 0xff800000
 ; GFX1132-NEXT:    s_mov_b32 s0, exec_lo
 ; GFX1132-NEXT:  .LBB5_1: ; %ComputeLoop
@@ -3160,25 +3132,24 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_defalut_scop
 ; GFX9-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX9-DPP-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX9-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX9-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX9-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX9-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -3254,25 +3225,24 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_defalut_scop
 ; GFX1064-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1064-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -3347,25 +3317,24 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_defalut_scop
 ; GFX1032-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1032-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -3428,23 +3397,22 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_defalut_scop
 ;
 ; GFX1164-DPP-LABEL: global_atomic_fmax_uni_address_div_value_defalut_scope_unsafe:
 ; GFX1164-DPP:       ; %bb.0:
-; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-DPP-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1164-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-DPP-NEXT:    s_or_saveexec_b64 s[0:1], -1
 ; GFX1164-DPP-NEXT:    v_mov_b32_e32 v1, 0xff800000
 ; GFX1164-DPP-NEXT:    s_mov_b64 exec, s[0:1]
@@ -3524,23 +3492,22 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_defalut_scop
 ;
 ; GFX1132-DPP-LABEL: global_atomic_fmax_uni_address_div_value_defalut_scope_unsafe:
 ; GFX1132-DPP:       ; %bb.0:
-; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-DPP-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-DPP-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-DPP-NEXT:    s_mov_b32 s12, s13
-; GFX1132-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-DPP-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-DPP-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-DPP-NEXT:    s_or_saveexec_b32 s0, -1
 ; GFX1132-DPP-NEXT:    v_mov_b32_e32 v1, 0xff800000
 ; GFX1132-DPP-NEXT:    s_mov_b32 exec_lo, s0
@@ -3611,3 +3578,6 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_defalut_scop
 }
 
 attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" "amdgpu-unsafe-fp-atomics"="true" }
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"amdgpu_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
index ad6edbd2c37a..17533e22ce2a 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
@@ -357,27 +357,26 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_agent_scope_
 ; GFX7LESS-NEXT:    s_mov_b32 s41, SCRATCH_RSRC_DWORD1
 ; GFX7LESS-NEXT:    s_mov_b32 s42, -1
 ; GFX7LESS-NEXT:    s_mov_b32 s43, 0xe8f000
-; GFX7LESS-NEXT:    s_add_u32 s40, s40, s11
+; GFX7LESS-NEXT:    s_add_u32 s40, s40, s9
 ; GFX7LESS-NEXT:    s_addc_u32 s41, s41, 0
-; GFX7LESS-NEXT:    s_mov_b32 s14, s10
-; GFX7LESS-NEXT:    s_mov_b32 s13, s9
-; GFX7LESS-NEXT:    s_mov_b32 s12, s8
-; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[6:7]
-; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[4:5], 0x9
+; GFX7LESS-NEXT:    s_mov_b32 s14, s8
+; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[4:5]
+; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[2:3], 0x9
 ; GFX7LESS-NEXT:    s_mov_b32 s39, 0xf000
 ; GFX7LESS-NEXT:    s_mov_b32 s38, -1
-; GFX7LESS-NEXT:    s_add_u32 s8, s4, 44
-; GFX7LESS-NEXT:    s_addc_u32 s9, s5, 0
-; GFX7LESS-NEXT:    s_getpc_b64 s[4:5]
-; GFX7LESS-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX7LESS-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX7LESS-NEXT:    s_add_u32 s8, s2, 44
+; GFX7LESS-NEXT:    s_addc_u32 s9, s3, 0
+; GFX7LESS-NEXT:    s_getpc_b64 s[2:3]
+; GFX7LESS-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX7LESS-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v31, v0, v2
 ; GFX7LESS-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX7LESS-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX7LESS-NEXT:    s_mov_b32 s12, s6
+; GFX7LESS-NEXT:    s_mov_b32 s13, s7
 ; GFX7LESS-NEXT:    s_mov_b64 s[0:1], s[40:41]
 ; GFX7LESS-NEXT:    s_mov_b64 s[2:3], s[42:43]
 ; GFX7LESS-NEXT:    s_waitcnt lgkmcnt(0)
@@ -409,25 +408,24 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_agent_scope_
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-NEXT:    s_mov_b32 s12, s8
+; GFX9-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-NEXT:    s_mov_b32 s14, s8
 ; GFX9-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-NEXT:    s_mov_b32 s13, s9
 ; GFX9-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT:    s_mov_b32 s14, s10
-; GFX9-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-NEXT:    s_mov_b32 s12, s6
+; GFX9-NEXT:    s_mov_b32 s13, s7
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -483,25 +481,24 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_agent_scope_
 ; GFX1064-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-NEXT:    s_mov_b32 s12, s8
+; GFX1064-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-NEXT:    s_mov_b32 s14, s10
-; GFX1064-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-NEXT:    s_mov_b32 s12, s6
+; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
@@ -557,25 +554,24 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_agent_scope_
 ; GFX1032-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-NEXT:    s_mov_b32 s12, s8
+; GFX1032-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-NEXT:    s_mov_b32 s14, s10
-; GFX1032-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-NEXT:    s_mov_b32 s12, s6
+; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
@@ -623,23 +619,22 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_agent_scope_
 ;
 ; GFX1164-LABEL: global_atomic_fmin_uni_address_div_value_agent_scope_unsafe:
 ; GFX1164:       ; %bb.0:
-; GFX1164-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-NEXT:    s_mov_b32 s12, s8
+; GFX1164-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-NEXT:    s_mov_b32 s14, s10
-; GFX1164-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s12, s6
+; GFX1164-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; GFX1164-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX1164-NEXT:  .LBB1_1: ; %ComputeLoop
@@ -693,23 +688,22 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_agent_scope_
 ;
 ; GFX1132-LABEL: global_atomic_fmin_uni_address_div_value_agent_scope_unsafe:
 ; GFX1132:       ; %bb.0:
-; GFX1132-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-NEXT:    s_mov_b32 s12, s13
-; GFX1132-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; GFX1132-NEXT:    s_mov_b32 s0, exec_lo
 ; GFX1132-NEXT:  .LBB1_1: ; %ComputeLoop
@@ -762,25 +756,24 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_agent_scope_
 ; GFX9-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX9-DPP-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX9-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX9-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX9-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX9-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -856,25 +849,24 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_agent_scope_
 ; GFX1064-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1064-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -949,25 +941,24 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_agent_scope_
 ; GFX1032-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1032-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -1030,23 +1021,22 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_agent_scope_
 ;
 ; GFX1164-DPP-LABEL: global_atomic_fmin_uni_address_div_value_agent_scope_unsafe:
 ; GFX1164-DPP:       ; %bb.0:
-; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-DPP-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1164-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-DPP-NEXT:    s_or_saveexec_b64 s[0:1], -1
 ; GFX1164-DPP-NEXT:    v_mov_b32_e32 v1, 0x7f800000
 ; GFX1164-DPP-NEXT:    s_mov_b64 exec, s[0:1]
@@ -1126,23 +1116,22 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_agent_scope_
 ;
 ; GFX1132-DPP-LABEL: global_atomic_fmin_uni_address_div_value_agent_scope_unsafe:
 ; GFX1132-DPP:       ; %bb.0:
-; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-DPP-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-DPP-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-DPP-NEXT:    s_mov_b32 s12, s13
-; GFX1132-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-DPP-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-DPP-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-DPP-NEXT:    s_or_saveexec_b32 s0, -1
 ; GFX1132-DPP-NEXT:    v_mov_b32_e32 v1, 0x7f800000
 ; GFX1132-DPP-NEXT:    s_mov_b32 exec_lo, s0
@@ -1556,27 +1545,26 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_one_as_scope
 ; GFX7LESS-NEXT:    s_mov_b32 s41, SCRATCH_RSRC_DWORD1
 ; GFX7LESS-NEXT:    s_mov_b32 s42, -1
 ; GFX7LESS-NEXT:    s_mov_b32 s43, 0xe8f000
-; GFX7LESS-NEXT:    s_add_u32 s40, s40, s11
+; GFX7LESS-NEXT:    s_add_u32 s40, s40, s9
 ; GFX7LESS-NEXT:    s_addc_u32 s41, s41, 0
-; GFX7LESS-NEXT:    s_mov_b32 s14, s10
-; GFX7LESS-NEXT:    s_mov_b32 s13, s9
-; GFX7LESS-NEXT:    s_mov_b32 s12, s8
-; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[6:7]
-; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[4:5], 0x9
+; GFX7LESS-NEXT:    s_mov_b32 s14, s8
+; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[4:5]
+; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[2:3], 0x9
 ; GFX7LESS-NEXT:    s_mov_b32 s39, 0xf000
 ; GFX7LESS-NEXT:    s_mov_b32 s38, -1
-; GFX7LESS-NEXT:    s_add_u32 s8, s4, 44
-; GFX7LESS-NEXT:    s_addc_u32 s9, s5, 0
-; GFX7LESS-NEXT:    s_getpc_b64 s[4:5]
-; GFX7LESS-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX7LESS-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX7LESS-NEXT:    s_add_u32 s8, s2, 44
+; GFX7LESS-NEXT:    s_addc_u32 s9, s3, 0
+; GFX7LESS-NEXT:    s_getpc_b64 s[2:3]
+; GFX7LESS-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX7LESS-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v31, v0, v2
 ; GFX7LESS-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX7LESS-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX7LESS-NEXT:    s_mov_b32 s12, s6
+; GFX7LESS-NEXT:    s_mov_b32 s13, s7
 ; GFX7LESS-NEXT:    s_mov_b64 s[0:1], s[40:41]
 ; GFX7LESS-NEXT:    s_mov_b64 s[2:3], s[42:43]
 ; GFX7LESS-NEXT:    s_waitcnt lgkmcnt(0)
@@ -1608,25 +1596,24 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_one_as_scope
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-NEXT:    s_mov_b32 s12, s8
+; GFX9-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-NEXT:    s_mov_b32 s14, s8
 ; GFX9-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-NEXT:    s_mov_b32 s13, s9
 ; GFX9-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT:    s_mov_b32 s14, s10
-; GFX9-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-NEXT:    s_mov_b32 s12, s6
+; GFX9-NEXT:    s_mov_b32 s13, s7
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -1682,25 +1669,24 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_one_as_scope
 ; GFX1064-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-NEXT:    s_mov_b32 s12, s8
+; GFX1064-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-NEXT:    s_mov_b32 s14, s10
-; GFX1064-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-NEXT:    s_mov_b32 s12, s6
+; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
@@ -1756,25 +1742,24 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_one_as_scope
 ; GFX1032-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-NEXT:    s_mov_b32 s12, s8
+; GFX1032-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-NEXT:    s_mov_b32 s14, s10
-; GFX1032-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-NEXT:    s_mov_b32 s12, s6
+; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
@@ -1822,23 +1807,22 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_one_as_scope
 ;
 ; GFX1164-LABEL: global_atomic_fmin_uni_address_div_value_one_as_scope_unsafe:
 ; GFX1164:       ; %bb.0:
-; GFX1164-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-NEXT:    s_mov_b32 s12, s8
+; GFX1164-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-NEXT:    s_mov_b32 s14, s10
-; GFX1164-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s12, s6
+; GFX1164-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; GFX1164-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX1164-NEXT:  .LBB3_1: ; %ComputeLoop
@@ -1892,23 +1876,22 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_one_as_scope
 ;
 ; GFX1132-LABEL: global_atomic_fmin_uni_address_div_value_one_as_scope_unsafe:
 ; GFX1132:       ; %bb.0:
-; GFX1132-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-NEXT:    s_mov_b32 s12, s13
-; GFX1132-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; GFX1132-NEXT:    s_mov_b32 s0, exec_lo
 ; GFX1132-NEXT:  .LBB3_1: ; %ComputeLoop
@@ -1961,25 +1944,24 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_one_as_scope
 ; GFX9-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX9-DPP-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX9-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX9-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX9-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX9-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2055,25 +2037,24 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_one_as_scope
 ; GFX1064-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1064-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2148,25 +2129,24 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_one_as_scope
 ; GFX1032-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1032-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2229,23 +2209,22 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_one_as_scope
 ;
 ; GFX1164-DPP-LABEL: global_atomic_fmin_uni_address_div_value_one_as_scope_unsafe:
 ; GFX1164-DPP:       ; %bb.0:
-; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-DPP-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1164-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-DPP-NEXT:    s_or_saveexec_b64 s[0:1], -1
 ; GFX1164-DPP-NEXT:    v_mov_b32_e32 v1, 0x7f800000
 ; GFX1164-DPP-NEXT:    s_mov_b64 exec, s[0:1]
@@ -2325,23 +2304,22 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_one_as_scope
 ;
 ; GFX1132-DPP-LABEL: global_atomic_fmin_uni_address_div_value_one_as_scope_unsafe:
 ; GFX1132-DPP:       ; %bb.0:
-; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-DPP-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-DPP-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-DPP-NEXT:    s_mov_b32 s12, s13
-; GFX1132-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-DPP-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-DPP-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-DPP-NEXT:    s_or_saveexec_b32 s0, -1
 ; GFX1132-DPP-NEXT:    v_mov_b32_e32 v1, 0x7f800000
 ; GFX1132-DPP-NEXT:    s_mov_b32 exec_lo, s0
@@ -2755,27 +2733,26 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_defalut_scop
 ; GFX7LESS-NEXT:    s_mov_b32 s41, SCRATCH_RSRC_DWORD1
 ; GFX7LESS-NEXT:    s_mov_b32 s42, -1
 ; GFX7LESS-NEXT:    s_mov_b32 s43, 0xe8f000
-; GFX7LESS-NEXT:    s_add_u32 s40, s40, s11
+; GFX7LESS-NEXT:    s_add_u32 s40, s40, s9
 ; GFX7LESS-NEXT:    s_addc_u32 s41, s41, 0
-; GFX7LESS-NEXT:    s_mov_b32 s14, s10
-; GFX7LESS-NEXT:    s_mov_b32 s13, s9
-; GFX7LESS-NEXT:    s_mov_b32 s12, s8
-; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[6:7]
-; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[4:5], 0x9
+; GFX7LESS-NEXT:    s_mov_b32 s14, s8
+; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[4:5]
+; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[2:3], 0x9
 ; GFX7LESS-NEXT:    s_mov_b32 s39, 0xf000
 ; GFX7LESS-NEXT:    s_mov_b32 s38, -1
-; GFX7LESS-NEXT:    s_add_u32 s8, s4, 44
-; GFX7LESS-NEXT:    s_addc_u32 s9, s5, 0
-; GFX7LESS-NEXT:    s_getpc_b64 s[4:5]
-; GFX7LESS-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX7LESS-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX7LESS-NEXT:    s_add_u32 s8, s2, 44
+; GFX7LESS-NEXT:    s_addc_u32 s9, s3, 0
+; GFX7LESS-NEXT:    s_getpc_b64 s[2:3]
+; GFX7LESS-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX7LESS-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v31, v0, v2
 ; GFX7LESS-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX7LESS-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX7LESS-NEXT:    s_mov_b32 s12, s6
+; GFX7LESS-NEXT:    s_mov_b32 s13, s7
 ; GFX7LESS-NEXT:    s_mov_b64 s[0:1], s[40:41]
 ; GFX7LESS-NEXT:    s_mov_b64 s[2:3], s[42:43]
 ; GFX7LESS-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2807,25 +2784,24 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_defalut_scop
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-NEXT:    s_mov_b32 s12, s8
+; GFX9-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-NEXT:    s_mov_b32 s14, s8
 ; GFX9-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-NEXT:    s_mov_b32 s13, s9
 ; GFX9-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT:    s_mov_b32 s14, s10
-; GFX9-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-NEXT:    s_mov_b32 s12, s6
+; GFX9-NEXT:    s_mov_b32 s13, s7
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2881,25 +2857,24 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_defalut_scop
 ; GFX1064-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-NEXT:    s_mov_b32 s12, s8
+; GFX1064-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-NEXT:    s_mov_b32 s14, s10
-; GFX1064-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-NEXT:    s_mov_b32 s12, s6
+; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2955,25 +2930,24 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_defalut_scop
 ; GFX1032-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-NEXT:    s_mov_b32 s12, s8
+; GFX1032-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-NEXT:    s_mov_b32 s14, s10
-; GFX1032-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-NEXT:    s_mov_b32 s12, s6
+; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
@@ -3021,23 +2995,22 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_defalut_scop
 ;
 ; GFX1164-LABEL: global_atomic_fmin_uni_address_div_value_defalut_scope_unsafe:
 ; GFX1164:       ; %bb.0:
-; GFX1164-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-NEXT:    s_mov_b32 s12, s8
+; GFX1164-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-NEXT:    s_mov_b32 s14, s10
-; GFX1164-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s12, s6
+; GFX1164-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; GFX1164-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX1164-NEXT:  .LBB5_1: ; %ComputeLoop
@@ -3091,23 +3064,22 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_defalut_scop
 ;
 ; GFX1132-LABEL: global_atomic_fmin_uni_address_div_value_defalut_scope_unsafe:
 ; GFX1132:       ; %bb.0:
-; GFX1132-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-NEXT:    s_mov_b32 s12, s13
-; GFX1132-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; GFX1132-NEXT:    s_mov_b32 s0, exec_lo
 ; GFX1132-NEXT:  .LBB5_1: ; %ComputeLoop
@@ -3160,25 +3132,24 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_defalut_scop
 ; GFX9-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX9-DPP-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX9-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX9-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX9-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX9-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -3254,25 +3225,24 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_defalut_scop
 ; GFX1064-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1064-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -3347,25 +3317,24 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_defalut_scop
 ; GFX1032-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1032-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -3428,23 +3397,22 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_defalut_scop
 ;
 ; GFX1164-DPP-LABEL: global_atomic_fmin_uni_address_div_value_defalut_scope_unsafe:
 ; GFX1164-DPP:       ; %bb.0:
-; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-DPP-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1164-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-DPP-NEXT:    s_or_saveexec_b64 s[0:1], -1
 ; GFX1164-DPP-NEXT:    v_mov_b32_e32 v1, 0x7f800000
 ; GFX1164-DPP-NEXT:    s_mov_b64 exec, s[0:1]
@@ -3524,23 +3492,22 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_defalut_scop
 ;
 ; GFX1132-DPP-LABEL: global_atomic_fmin_uni_address_div_value_defalut_scope_unsafe:
 ; GFX1132-DPP:       ; %bb.0:
-; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-DPP-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-DPP-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-DPP-NEXT:    s_mov_b32 s12, s13
-; GFX1132-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-DPP-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-DPP-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-DPP-NEXT:    s_or_saveexec_b32 s0, -1
 ; GFX1132-DPP-NEXT:    v_mov_b32_e32 v1, 0x7f800000
 ; GFX1132-DPP-NEXT:    s_mov_b32 exec_lo, s0
@@ -3611,3 +3578,6 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_defalut_scop
 }
 
 attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" "amdgpu-unsafe-fp-atomics"="true" }
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"amdgpu_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
index 4a00d7bc71bc..a8b83edfa743 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
@@ -392,27 +392,26 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ; GFX7LESS-NEXT:    s_mov_b32 s41, SCRATCH_RSRC_DWORD1
 ; GFX7LESS-NEXT:    s_mov_b32 s42, -1
 ; GFX7LESS-NEXT:    s_mov_b32 s43, 0xe8f000
-; GFX7LESS-NEXT:    s_add_u32 s40, s40, s11
+; GFX7LESS-NEXT:    s_add_u32 s40, s40, s9
 ; GFX7LESS-NEXT:    s_addc_u32 s41, s41, 0
-; GFX7LESS-NEXT:    s_mov_b32 s14, s10
-; GFX7LESS-NEXT:    s_mov_b32 s13, s9
-; GFX7LESS-NEXT:    s_mov_b32 s12, s8
-; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[6:7]
-; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[4:5], 0x9
+; GFX7LESS-NEXT:    s_mov_b32 s14, s8
+; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[4:5]
+; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[2:3], 0x9
 ; GFX7LESS-NEXT:    s_mov_b32 s39, 0xf000
 ; GFX7LESS-NEXT:    s_mov_b32 s38, -1
-; GFX7LESS-NEXT:    s_add_u32 s8, s4, 44
-; GFX7LESS-NEXT:    s_addc_u32 s9, s5, 0
-; GFX7LESS-NEXT:    s_getpc_b64 s[4:5]
-; GFX7LESS-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX7LESS-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX7LESS-NEXT:    s_add_u32 s8, s2, 44
+; GFX7LESS-NEXT:    s_addc_u32 s9, s3, 0
+; GFX7LESS-NEXT:    s_getpc_b64 s[2:3]
+; GFX7LESS-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX7LESS-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v31, v0, v2
 ; GFX7LESS-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX7LESS-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX7LESS-NEXT:    s_mov_b32 s12, s6
+; GFX7LESS-NEXT:    s_mov_b32 s13, s7
 ; GFX7LESS-NEXT:    s_mov_b64 s[0:1], s[40:41]
 ; GFX7LESS-NEXT:    s_mov_b64 s[2:3], s[42:43]
 ; GFX7LESS-NEXT:    s_waitcnt lgkmcnt(0)
@@ -442,25 +441,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-NEXT:    s_mov_b32 s12, s8
+; GFX9-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-NEXT:    s_mov_b32 s14, s8
 ; GFX9-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-NEXT:    s_mov_b32 s13, s9
 ; GFX9-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT:    s_mov_b32 s14, s10
-; GFX9-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-NEXT:    s_mov_b32 s12, s6
+; GFX9-NEXT:    s_mov_b32 s13, s7
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -512,25 +510,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ; GFX1064-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-NEXT:    s_mov_b32 s12, s8
+; GFX1064-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-NEXT:    s_mov_b32 s14, s10
-; GFX1064-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-NEXT:    s_mov_b32 s12, s6
+; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
@@ -582,25 +579,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ; GFX1032-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-NEXT:    s_mov_b32 s12, s8
+; GFX1032-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-NEXT:    s_mov_b32 s14, s10
-; GFX1032-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-NEXT:    s_mov_b32 s12, s6
+; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
@@ -644,23 +640,22 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ;
 ; GFX1164-LABEL: global_atomic_fsub_uni_address_div_value_agent_scope_align4_unsafe:
 ; GFX1164:       ; %bb.0:
-; GFX1164-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-NEXT:    s_mov_b32 s12, s8
+; GFX1164-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-NEXT:    s_mov_b32 s14, s10
-; GFX1164-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s12, s6
+; GFX1164-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-NEXT:    v_bfrev_b32_e32 v2, 1
 ; GFX1164-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX1164-NEXT:  .LBB1_1: ; %ComputeLoop
@@ -709,23 +704,22 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ;
 ; GFX1132-LABEL: global_atomic_fsub_uni_address_div_value_agent_scope_align4_unsafe:
 ; GFX1132:       ; %bb.0:
-; GFX1132-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-NEXT:    s_mov_b32 s12, s13
-; GFX1132-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-NEXT:    v_bfrev_b32_e32 v2, 1
 ; GFX1132-NEXT:    s_mov_b32 s0, exec_lo
 ; GFX1132-NEXT:  .LBB1_1: ; %ComputeLoop
@@ -774,25 +768,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ; GFX9-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX9-DPP-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX9-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX9-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX9-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX9-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -859,25 +852,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ; GFX1064-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1064-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -942,25 +934,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ; GFX1032-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1032-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -1015,23 +1006,22 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ;
 ; GFX1164-DPP-LABEL: global_atomic_fsub_uni_address_div_value_agent_scope_align4_unsafe:
 ; GFX1164-DPP:       ; %bb.0:
-; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-DPP-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1164-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-DPP-NEXT:    s_or_saveexec_b64 s[0:1], -1
 ; GFX1164-DPP-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX1164-DPP-NEXT:    s_mov_b64 exec, s[0:1]
@@ -1098,23 +1088,22 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ;
 ; GFX1132-DPP-LABEL: global_atomic_fsub_uni_address_div_value_agent_scope_align4_unsafe:
 ; GFX1132-DPP:       ; %bb.0:
-; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-DPP-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-DPP-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-DPP-NEXT:    s_mov_b32 s12, s13
-; GFX1132-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-DPP-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-DPP-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-DPP-NEXT:    s_or_saveexec_b32 s0, -1
 ; GFX1132-DPP-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX1132-DPP-NEXT:    s_mov_b32 exec_lo, s0
@@ -1642,27 +1631,26 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_one_as_scope
 ; GFX7LESS-NEXT:    s_mov_b32 s41, SCRATCH_RSRC_DWORD1
 ; GFX7LESS-NEXT:    s_mov_b32 s42, -1
 ; GFX7LESS-NEXT:    s_mov_b32 s43, 0xe8f000
-; GFX7LESS-NEXT:    s_add_u32 s40, s40, s11
+; GFX7LESS-NEXT:    s_add_u32 s40, s40, s9
 ; GFX7LESS-NEXT:    s_addc_u32 s41, s41, 0
-; GFX7LESS-NEXT:    s_mov_b32 s14, s10
-; GFX7LESS-NEXT:    s_mov_b32 s13, s9
-; GFX7LESS-NEXT:    s_mov_b32 s12, s8
-; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[6:7]
-; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[4:5], 0x9
+; GFX7LESS-NEXT:    s_mov_b32 s14, s8
+; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[4:5]
+; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[2:3], 0x9
 ; GFX7LESS-NEXT:    s_mov_b32 s39, 0xf000
 ; GFX7LESS-NEXT:    s_mov_b32 s38, -1
-; GFX7LESS-NEXT:    s_add_u32 s8, s4, 44
-; GFX7LESS-NEXT:    s_addc_u32 s9, s5, 0
-; GFX7LESS-NEXT:    s_getpc_b64 s[4:5]
-; GFX7LESS-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX7LESS-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX7LESS-NEXT:    s_add_u32 s8, s2, 44
+; GFX7LESS-NEXT:    s_addc_u32 s9, s3, 0
+; GFX7LESS-NEXT:    s_getpc_b64 s[2:3]
+; GFX7LESS-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX7LESS-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v31, v0, v2
 ; GFX7LESS-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX7LESS-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX7LESS-NEXT:    s_mov_b32 s12, s6
+; GFX7LESS-NEXT:    s_mov_b32 s13, s7
 ; GFX7LESS-NEXT:    s_mov_b64 s[0:1], s[40:41]
 ; GFX7LESS-NEXT:    s_mov_b64 s[2:3], s[42:43]
 ; GFX7LESS-NEXT:    s_waitcnt lgkmcnt(0)
@@ -1692,25 +1680,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_one_as_scope
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-NEXT:    s_mov_b32 s12, s8
+; GFX9-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-NEXT:    s_mov_b32 s14, s8
 ; GFX9-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-NEXT:    s_mov_b32 s13, s9
 ; GFX9-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT:    s_mov_b32 s14, s10
-; GFX9-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-NEXT:    s_mov_b32 s12, s6
+; GFX9-NEXT:    s_mov_b32 s13, s7
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -1762,25 +1749,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_one_as_scope
 ; GFX1064-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-NEXT:    s_mov_b32 s12, s8
+; GFX1064-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-NEXT:    s_mov_b32 s14, s10
-; GFX1064-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-NEXT:    s_mov_b32 s12, s6
+; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
@@ -1832,25 +1818,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_one_as_scope
 ; GFX1032-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-NEXT:    s_mov_b32 s12, s8
+; GFX1032-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-NEXT:    s_mov_b32 s14, s10
-; GFX1032-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-NEXT:    s_mov_b32 s12, s6
+; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
@@ -1894,23 +1879,22 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_one_as_scope
 ;
 ; GFX1164-LABEL: global_atomic_fsub_uni_address_div_value_one_as_scope_unsafe_structfp:
 ; GFX1164:       ; %bb.0:
-; GFX1164-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-NEXT:    s_mov_b32 s12, s8
+; GFX1164-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-NEXT:    s_mov_b32 s14, s10
-; GFX1164-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s12, s6
+; GFX1164-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-NEXT:    v_bfrev_b32_e32 v2, 1
 ; GFX1164-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX1164-NEXT:  .LBB3_1: ; %ComputeLoop
@@ -1959,23 +1943,22 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_one_as_scope
 ;
 ; GFX1132-LABEL: global_atomic_fsub_uni_address_div_value_one_as_scope_unsafe_structfp:
 ; GFX1132:       ; %bb.0:
-; GFX1132-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-NEXT:    s_mov_b32 s12, s13
-; GFX1132-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-NEXT:    v_bfrev_b32_e32 v2, 1
 ; GFX1132-NEXT:    s_mov_b32 s0, exec_lo
 ; GFX1132-NEXT:  .LBB3_1: ; %ComputeLoop
@@ -2024,25 +2007,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_one_as_scope
 ; GFX9-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX9-DPP-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX9-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX9-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX9-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX9-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2109,25 +2091,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_one_as_scope
 ; GFX1064-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1064-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2192,25 +2173,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_one_as_scope
 ; GFX1032-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1032-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2265,23 +2245,22 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_one_as_scope
 ;
 ; GFX1164-DPP-LABEL: global_atomic_fsub_uni_address_div_value_one_as_scope_unsafe_structfp:
 ; GFX1164-DPP:       ; %bb.0:
-; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-DPP-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1164-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-DPP-NEXT:    s_or_saveexec_b64 s[0:1], -1
 ; GFX1164-DPP-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX1164-DPP-NEXT:    s_mov_b64 exec, s[0:1]
@@ -2348,23 +2327,22 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_one_as_scope
 ;
 ; GFX1132-DPP-LABEL: global_atomic_fsub_uni_address_div_value_one_as_scope_unsafe_structfp:
 ; GFX1132-DPP:       ; %bb.0:
-; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-DPP-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-DPP-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-DPP-NEXT:    s_mov_b32 s12, s13
-; GFX1132-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-DPP-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-DPP-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-DPP-NEXT:    s_or_saveexec_b32 s0, -1
 ; GFX1132-DPP-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX1132-DPP-NEXT:    s_mov_b32 exec_lo, s0
@@ -2892,27 +2870,26 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ; GFX7LESS-NEXT:    s_mov_b32 s41, SCRATCH_RSRC_DWORD1
 ; GFX7LESS-NEXT:    s_mov_b32 s42, -1
 ; GFX7LESS-NEXT:    s_mov_b32 s43, 0xe8f000
-; GFX7LESS-NEXT:    s_add_u32 s40, s40, s11
+; GFX7LESS-NEXT:    s_add_u32 s40, s40, s9
 ; GFX7LESS-NEXT:    s_addc_u32 s41, s41, 0
-; GFX7LESS-NEXT:    s_mov_b32 s14, s10
-; GFX7LESS-NEXT:    s_mov_b32 s13, s9
-; GFX7LESS-NEXT:    s_mov_b32 s12, s8
-; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[6:7]
-; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[4:5], 0x9
+; GFX7LESS-NEXT:    s_mov_b32 s14, s8
+; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[4:5]
+; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[2:3], 0x9
 ; GFX7LESS-NEXT:    s_mov_b32 s39, 0xf000
 ; GFX7LESS-NEXT:    s_mov_b32 s38, -1
-; GFX7LESS-NEXT:    s_add_u32 s8, s4, 44
-; GFX7LESS-NEXT:    s_addc_u32 s9, s5, 0
-; GFX7LESS-NEXT:    s_getpc_b64 s[4:5]
-; GFX7LESS-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX7LESS-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX7LESS-NEXT:    s_add_u32 s8, s2, 44
+; GFX7LESS-NEXT:    s_addc_u32 s9, s3, 0
+; GFX7LESS-NEXT:    s_getpc_b64 s[2:3]
+; GFX7LESS-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX7LESS-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v31, v0, v2
 ; GFX7LESS-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX7LESS-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX7LESS-NEXT:    s_mov_b32 s12, s6
+; GFX7LESS-NEXT:    s_mov_b32 s13, s7
 ; GFX7LESS-NEXT:    s_mov_b64 s[0:1], s[40:41]
 ; GFX7LESS-NEXT:    s_mov_b64 s[2:3], s[42:43]
 ; GFX7LESS-NEXT:    s_waitcnt lgkmcnt(0)
@@ -2942,25 +2919,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-NEXT:    s_mov_b32 s12, s8
+; GFX9-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-NEXT:    s_mov_b32 s14, s8
 ; GFX9-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-NEXT:    s_mov_b32 s13, s9
 ; GFX9-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT:    s_mov_b32 s14, s10
-; GFX9-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-NEXT:    s_mov_b32 s12, s6
+; GFX9-NEXT:    s_mov_b32 s13, s7
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -3012,25 +2988,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ; GFX1064-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-NEXT:    s_mov_b32 s12, s8
+; GFX1064-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-NEXT:    s_mov_b32 s14, s10
-; GFX1064-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-NEXT:    s_mov_b32 s12, s6
+; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
@@ -3082,25 +3057,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ; GFX1032-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-NEXT:    s_mov_b32 s12, s8
+; GFX1032-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-NEXT:    s_mov_b32 s14, s10
-; GFX1032-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-NEXT:    s_mov_b32 s12, s6
+; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
@@ -3144,23 +3118,22 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ;
 ; GFX1164-LABEL: global_atomic_fsub_uni_address_div_value_agent_scope_unsafe:
 ; GFX1164:       ; %bb.0:
-; GFX1164-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-NEXT:    s_mov_b32 s12, s8
+; GFX1164-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-NEXT:    s_mov_b32 s14, s10
-; GFX1164-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s12, s6
+; GFX1164-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-NEXT:    v_bfrev_b32_e32 v2, 1
 ; GFX1164-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX1164-NEXT:  .LBB5_1: ; %ComputeLoop
@@ -3209,23 +3182,22 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ;
 ; GFX1132-LABEL: global_atomic_fsub_uni_address_div_value_agent_scope_unsafe:
 ; GFX1132:       ; %bb.0:
-; GFX1132-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-NEXT:    s_mov_b32 s12, s13
-; GFX1132-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-NEXT:    v_bfrev_b32_e32 v2, 1
 ; GFX1132-NEXT:    s_mov_b32 s0, exec_lo
 ; GFX1132-NEXT:  .LBB5_1: ; %ComputeLoop
@@ -3274,25 +3246,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ; GFX9-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX9-DPP-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX9-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX9-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX9-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX9-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -3359,25 +3330,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ; GFX1064-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1064-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -3442,25 +3412,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ; GFX1032-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1032-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -3515,23 +3484,22 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ;
 ; GFX1164-DPP-LABEL: global_atomic_fsub_uni_address_div_value_agent_scope_unsafe:
 ; GFX1164-DPP:       ; %bb.0:
-; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-DPP-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1164-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-DPP-NEXT:    s_or_saveexec_b64 s[0:1], -1
 ; GFX1164-DPP-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX1164-DPP-NEXT:    s_mov_b64 exec, s[0:1]
@@ -3598,23 +3566,22 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ;
 ; GFX1132-DPP-LABEL: global_atomic_fsub_uni_address_div_value_agent_scope_unsafe:
 ; GFX1132-DPP:       ; %bb.0:
-; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-DPP-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-DPP-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-DPP-NEXT:    s_mov_b32 s12, s13
-; GFX1132-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-DPP-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-DPP-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-DPP-NEXT:    s_or_saveexec_b32 s0, -1
 ; GFX1132-DPP-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX1132-DPP-NEXT:    s_mov_b32 exec_lo, s0
@@ -3684,27 +3651,26 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ; GFX7LESS-NEXT:    s_mov_b32 s41, SCRATCH_RSRC_DWORD1
 ; GFX7LESS-NEXT:    s_mov_b32 s42, -1
 ; GFX7LESS-NEXT:    s_mov_b32 s43, 0xe8f000
-; GFX7LESS-NEXT:    s_add_u32 s40, s40, s11
+; GFX7LESS-NEXT:    s_add_u32 s40, s40, s9
 ; GFX7LESS-NEXT:    s_addc_u32 s41, s41, 0
-; GFX7LESS-NEXT:    s_mov_b32 s14, s10
-; GFX7LESS-NEXT:    s_mov_b32 s13, s9
-; GFX7LESS-NEXT:    s_mov_b32 s12, s8
-; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[6:7]
-; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[4:5], 0x9
+; GFX7LESS-NEXT:    s_mov_b32 s14, s8
+; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[4:5]
+; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[2:3], 0x9
 ; GFX7LESS-NEXT:    s_mov_b32 s39, 0xf000
 ; GFX7LESS-NEXT:    s_mov_b32 s38, -1
-; GFX7LESS-NEXT:    s_add_u32 s8, s4, 44
-; GFX7LESS-NEXT:    s_addc_u32 s9, s5, 0
-; GFX7LESS-NEXT:    s_getpc_b64 s[4:5]
-; GFX7LESS-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX7LESS-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX7LESS-NEXT:    s_add_u32 s8, s2, 44
+; GFX7LESS-NEXT:    s_addc_u32 s9, s3, 0
+; GFX7LESS-NEXT:    s_getpc_b64 s[2:3]
+; GFX7LESS-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX7LESS-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v31, v0, v2
 ; GFX7LESS-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX7LESS-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX7LESS-NEXT:    s_mov_b32 s12, s6
+; GFX7LESS-NEXT:    s_mov_b32 s13, s7
 ; GFX7LESS-NEXT:    s_mov_b64 s[0:1], s[40:41]
 ; GFX7LESS-NEXT:    s_mov_b64 s[2:3], s[42:43]
 ; GFX7LESS-NEXT:    s_waitcnt lgkmcnt(0)
@@ -3734,25 +3700,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-NEXT:    s_mov_b32 s12, s8
+; GFX9-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-NEXT:    s_mov_b32 s14, s8
 ; GFX9-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-NEXT:    s_mov_b32 s13, s9
 ; GFX9-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT:    s_mov_b32 s14, s10
-; GFX9-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-NEXT:    s_mov_b32 s12, s6
+; GFX9-NEXT:    s_mov_b32 s13, s7
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -3804,25 +3769,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ; GFX1064-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-NEXT:    s_mov_b32 s12, s8
+; GFX1064-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-NEXT:    s_mov_b32 s14, s10
-; GFX1064-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-NEXT:    s_mov_b32 s12, s6
+; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
@@ -3874,25 +3838,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ; GFX1032-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-NEXT:    s_mov_b32 s12, s8
+; GFX1032-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-NEXT:    s_mov_b32 s14, s10
-; GFX1032-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-NEXT:    s_mov_b32 s12, s6
+; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
@@ -3936,23 +3899,22 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ;
 ; GFX1164-LABEL: global_atomic_fsub_uni_address_div_value_agent_scope_unsafe_structfp:
 ; GFX1164:       ; %bb.0:
-; GFX1164-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-NEXT:    s_mov_b32 s12, s8
+; GFX1164-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-NEXT:    s_mov_b32 s14, s10
-; GFX1164-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s12, s6
+; GFX1164-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-NEXT:    v_bfrev_b32_e32 v2, 1
 ; GFX1164-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX1164-NEXT:  .LBB6_1: ; %ComputeLoop
@@ -4001,23 +3963,22 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ;
 ; GFX1132-LABEL: global_atomic_fsub_uni_address_div_value_agent_scope_unsafe_structfp:
 ; GFX1132:       ; %bb.0:
-; GFX1132-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-NEXT:    s_mov_b32 s12, s13
-; GFX1132-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-NEXT:    v_bfrev_b32_e32 v2, 1
 ; GFX1132-NEXT:    s_mov_b32 s0, exec_lo
 ; GFX1132-NEXT:  .LBB6_1: ; %ComputeLoop
@@ -4066,25 +4027,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ; GFX9-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX9-DPP-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX9-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX9-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX9-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX9-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -4151,25 +4111,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ; GFX1064-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1064-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -4234,25 +4193,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ; GFX1032-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1032-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -4307,23 +4265,22 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ;
 ; GFX1164-DPP-LABEL: global_atomic_fsub_uni_address_div_value_agent_scope_unsafe_structfp:
 ; GFX1164-DPP:       ; %bb.0:
-; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-DPP-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1164-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-DPP-NEXT:    s_or_saveexec_b64 s[0:1], -1
 ; GFX1164-DPP-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX1164-DPP-NEXT:    s_mov_b64 exec, s[0:1]
@@ -4390,23 +4347,22 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
 ;
 ; GFX1132-DPP-LABEL: global_atomic_fsub_uni_address_div_value_agent_scope_unsafe_structfp:
 ; GFX1132-DPP:       ; %bb.0:
-; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-DPP-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-DPP-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-DPP-NEXT:    s_mov_b32 s12, s13
-; GFX1132-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-DPP-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-DPP-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-DPP-NEXT:    s_or_saveexec_b32 s0, -1
 ; GFX1132-DPP-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX1132-DPP-NEXT:    s_mov_b32 exec_lo, s0
@@ -4933,27 +4889,26 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_defalut_scop
 ; GFX7LESS-NEXT:    s_mov_b32 s41, SCRATCH_RSRC_DWORD1
 ; GFX7LESS-NEXT:    s_mov_b32 s42, -1
 ; GFX7LESS-NEXT:    s_mov_b32 s43, 0xe8f000
-; GFX7LESS-NEXT:    s_add_u32 s40, s40, s11
+; GFX7LESS-NEXT:    s_add_u32 s40, s40, s9
 ; GFX7LESS-NEXT:    s_addc_u32 s41, s41, 0
-; GFX7LESS-NEXT:    s_mov_b32 s14, s10
-; GFX7LESS-NEXT:    s_mov_b32 s13, s9
-; GFX7LESS-NEXT:    s_mov_b32 s12, s8
-; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[6:7]
-; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[4:5], 0x9
+; GFX7LESS-NEXT:    s_mov_b32 s14, s8
+; GFX7LESS-NEXT:    s_mov_b64 s[10:11], s[4:5]
+; GFX7LESS-NEXT:    s_load_dwordx2 s[36:37], s[2:3], 0x9
 ; GFX7LESS-NEXT:    s_mov_b32 s39, 0xf000
 ; GFX7LESS-NEXT:    s_mov_b32 s38, -1
-; GFX7LESS-NEXT:    s_add_u32 s8, s4, 44
-; GFX7LESS-NEXT:    s_addc_u32 s9, s5, 0
-; GFX7LESS-NEXT:    s_getpc_b64 s[4:5]
-; GFX7LESS-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX7LESS-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX7LESS-NEXT:    s_add_u32 s8, s2, 44
+; GFX7LESS-NEXT:    s_addc_u32 s9, s3, 0
+; GFX7LESS-NEXT:    s_getpc_b64 s[2:3]
+; GFX7LESS-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX7LESS-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX7LESS-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX7LESS-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX7LESS-NEXT:    v_or_b32_e32 v31, v0, v2
 ; GFX7LESS-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX7LESS-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX7LESS-NEXT:    s_mov_b32 s12, s6
+; GFX7LESS-NEXT:    s_mov_b32 s13, s7
 ; GFX7LESS-NEXT:    s_mov_b64 s[0:1], s[40:41]
 ; GFX7LESS-NEXT:    s_mov_b64 s[2:3], s[42:43]
 ; GFX7LESS-NEXT:    s_waitcnt lgkmcnt(0)
@@ -4983,25 +4938,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_defalut_scop
 ; GFX9-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s38, -1
 ; GFX9-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-NEXT:    s_mov_b32 s12, s8
+; GFX9-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-NEXT:    s_mov_b32 s14, s8
 ; GFX9-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-NEXT:    s_mov_b32 s13, s9
 ; GFX9-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT:    s_mov_b32 s14, s10
-; GFX9-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-NEXT:    s_mov_b32 s12, s6
+; GFX9-NEXT:    s_mov_b32 s13, s7
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-NEXT:    s_mov_b32 s32, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
@@ -5053,25 +5007,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_defalut_scop
 ; GFX1064-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-NEXT:    s_mov_b32 s12, s8
+; GFX1064-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-NEXT:    s_mov_b32 s14, s10
-; GFX1064-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-NEXT:    s_mov_b32 s12, s6
+; GFX1064-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
@@ -5123,25 +5076,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_defalut_scop
 ; GFX1032-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-NEXT:    s_mov_b32 s12, s8
+; GFX1032-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-NEXT:    s_mov_b32 s14, s10
-; GFX1032-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-NEXT:    s_mov_b32 s12, s6
+; GFX1032-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
@@ -5185,23 +5137,22 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_defalut_scop
 ;
 ; GFX1164-LABEL: global_atomic_fsub_uni_address_div_value_defalut_scope_strictfp:
 ; GFX1164:       ; %bb.0:
-; GFX1164-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-NEXT:    s_mov_b32 s12, s8
+; GFX1164-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-NEXT:    s_mov_b32 s14, s10
-; GFX1164-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-NEXT:    s_mov_b32 s12, s6
+; GFX1164-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-NEXT:    v_bfrev_b32_e32 v2, 1
 ; GFX1164-NEXT:    s_mov_b64 s[0:1], exec
 ; GFX1164-NEXT:  .LBB8_1: ; %ComputeLoop
@@ -5250,23 +5201,22 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_defalut_scop
 ;
 ; GFX1132-LABEL: global_atomic_fsub_uni_address_div_value_defalut_scope_strictfp:
 ; GFX1132:       ; %bb.0:
-; GFX1132-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-NEXT:    s_mov_b32 s12, s13
-; GFX1132-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-NEXT:    v_bfrev_b32_e32 v2, 1
 ; GFX1132-NEXT:    s_mov_b32 s0, exec_lo
 ; GFX1132-NEXT:  .LBB8_1: ; %ComputeLoop
@@ -5315,25 +5265,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_defalut_scop
 ; GFX9-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX9-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX9-DPP-NEXT:    s_mov_b32 s39, 0xe00000
-; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s11
+; GFX9-DPP-NEXT:    s_add_u32 s36, s36, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX9-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX9-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX9-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX9-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX9-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX9-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX9-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX9-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX9-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
-; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX9-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX9-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
+; GFX9-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
+; GFX9-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
 ; GFX9-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
 ; GFX9-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX9-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX9-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
 ; GFX9-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX9-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX9-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX9-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX9-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX9-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -5400,25 +5349,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_defalut_scop
 ; GFX1064-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1064-DPP-NEXT:    s_mov_b32 s39, 0x31e16000
-; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1064-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1064-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1064-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1064-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1064-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1064-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1064-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1064-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1064-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1064-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1064-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1064-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1064-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1064-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1064-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1064-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1064-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1064-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1064-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1064-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1064-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1064-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1064-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1064-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1064-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -5483,25 +5431,24 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_defalut_scop
 ; GFX1032-DPP-NEXT:    s_mov_b32 s37, SCRATCH_RSRC_DWORD1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s38, -1
 ; GFX1032-DPP-NEXT:    s_mov_b32 s39, 0x31c16000
-; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s11
-; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1032-DPP-NEXT:    s_add_u32 s36, s36, s9
+; GFX1032-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1032-DPP-NEXT:    s_addc_u32 s37, s37, 0
-; GFX1032-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1032-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1032-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1032-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1032-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1032-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1032-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1032-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1032-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1032-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1032-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
-; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX1032-DPP-NEXT:    s_load_dwordx2 s[16:17], s[2:3], 0x0
 ; GFX1032-DPP-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
-; GFX1032-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1032-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1032-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[0:1], s[36:37]
+; GFX1032-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1032-DPP-NEXT:    v_or3_b32 v31, v0, v1, v2
+; GFX1032-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1032-DPP-NEXT:    s_mov_b64 s[2:3], s[38:39]
 ; GFX1032-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1032-DPP-NEXT:    s_waitcnt lgkmcnt(0)
@@ -5556,23 +5503,22 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_defalut_scop
 ;
 ; GFX1164-DPP-LABEL: global_atomic_fsub_uni_address_div_value_defalut_scope_strictfp:
 ; GFX1164-DPP:       ; %bb.0:
-; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
-; GFX1164-DPP-NEXT:    s_mov_b32 s12, s8
+; GFX1164-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s14, s8
 ; GFX1164-DPP-NEXT:    s_add_u32 s8, s34, 44
-; GFX1164-DPP-NEXT:    s_mov_b32 s13, s9
 ; GFX1164-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1164-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1164-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1164-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1164-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1164-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1164-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1164-DPP-NEXT:    v_mov_b32_e32 v31, v0
-; GFX1164-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1164-DPP-NEXT:    s_mov_b32 s14, s10
-; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1164-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1164-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1164-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1164-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX1164-DPP-NEXT:    s_mov_b32 s12, s6
+; GFX1164-DPP-NEXT:    s_mov_b32 s13, s7
 ; GFX1164-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1164-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1164-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1164-DPP-NEXT:    s_or_saveexec_b64 s[0:1], -1
 ; GFX1164-DPP-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX1164-DPP-NEXT:    s_mov_b64 exec, s[0:1]
@@ -5639,23 +5585,22 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_defalut_scop
 ;
 ; GFX1132-DPP-LABEL: global_atomic_fsub_uni_address_div_value_defalut_scope_strictfp:
 ; GFX1132-DPP:       ; %bb.0:
-; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[4:5]
+; GFX1132-DPP-NEXT:    s_mov_b64 s[34:35], s[2:3]
 ; GFX1132-DPP-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX1132-DPP-NEXT:    s_add_u32 s8, s34, 44
 ; GFX1132-DPP-NEXT:    s_addc_u32 s9, s35, 0
-; GFX1132-DPP-NEXT:    s_getpc_b64 s[4:5]
-; GFX1132-DPP-NEXT:    s_add_u32 s4, s4, div.float.value@gotpcrel32@lo+4
-; GFX1132-DPP-NEXT:    s_addc_u32 s5, s5, div.float.value@gotpcrel32@hi+12
+; GFX1132-DPP-NEXT:    s_getpc_b64 s[2:3]
+; GFX1132-DPP-NEXT:    s_add_u32 s2, s2, div.float.value@gotpcrel32@lo+4
+; GFX1132-DPP-NEXT:    s_addc_u32 s3, s3, div.float.value@gotpcrel32@hi+12
 ; GFX1132-DPP-NEXT:    s_mov_b32 s12, s13
-; GFX1132-DPP-NEXT:    s_load_b64 s[16:17], s[4:5], 0x0
-; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX1132-DPP-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1132-DPP-NEXT:    s_mov_b64 s[10:11], s[4:5]
 ; GFX1132-DPP-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX1132-DPP-NEXT:    s_mov_b64 s[6:7], s[2:3]
 ; GFX1132-DPP-NEXT:    s_mov_b32 s13, s14
 ; GFX1132-DPP-NEXT:    s_mov_b32 s14, s15
 ; GFX1132-DPP-NEXT:    s_mov_b32 s32, 0
 ; GFX1132-DPP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; GFX1132-DPP-NEXT:    s_swappc_b64 s[30:31], s[2:3]
 ; GFX1132-DPP-NEXT:    s_or_saveexec_b32 s0, -1
 ; GFX1132-DPP-NEXT:    v_bfrev_b32_e32 v1, 1
 ; GFX1132-DPP-NEXT:    s_mov_b32 exec_lo, s0
@@ -5720,3 +5665,5 @@ attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" "amdgpu-u
 attributes #1 = { strictfp "denormal-fp-math-f32"="preserve-sign,preserve-sign" "amdgpu-unsafe-fp-atomics"="true" }
 attributes #2 = { strictfp}
 
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"amdgpu_code_object_version", i32 500}
-- 
GitLab


From ceb02379a9636371c4f0c837c2c24164fdf03062 Mon Sep 17 00:00:00 2001
From: David Sherwood <57997763+david-arm@users.noreply.github.com>
Date: Tue, 12 Dec 2023 09:10:39 +0000
Subject: [PATCH 241/349] [LoopVectorize] Improve algorithm for hoisting
 runtime checks (#73515)

When attempting to hoist runtime checks out of a loop we currently avoid
creating pointer diff checks and prefer to do expanded range checks
instead. This gives us the opportunity to hoist runtime checks out of a
loop, since these checks are loop invariant. However, in some cases the
pointer diff checks would also be loop invariant and so will naturally
get hoisted. Therefore, since diff checks are cheaper so we should
prefer to use those instead.
---
 llvm/lib/Analysis/LoopAccessAnalysis.cpp      |   7 +-
 .../LoopVectorize/runtime-checks-hoist.ll     | 144 ++++++++++++++----
 2 files changed, 124 insertions(+), 27 deletions(-)

diff --git a/llvm/lib/Analysis/LoopAccessAnalysis.cpp b/llvm/lib/Analysis/LoopAccessAnalysis.cpp
index a8dbb66c4a9f..9a9d06a81f49 100644
--- a/llvm/lib/Analysis/LoopAccessAnalysis.cpp
+++ b/llvm/lib/Analysis/LoopAccessAnalysis.cpp
@@ -347,7 +347,12 @@ void RuntimePointerChecking::tryToCreateDiffCheck(
     auto *SinkStartAR = cast<SCEVAddRecExpr>(SinkStartInt);
     const Loop *StartARLoop = SrcStartAR->getLoop();
     if (StartARLoop == SinkStartAR->getLoop() &&
-        StartARLoop == InnerLoop->getParentLoop()) {
+        StartARLoop == InnerLoop->getParentLoop() &&
+        // If the diff check would already be loop invariant (due to the
+        // recurrences being the same), then we prefer to keep the diff checks
+        // because they are cheaper.
+        SrcStartAR->getStepRecurrence(*SE) !=
+            SinkStartAR->getStepRecurrence(*SE)) {
       LLVM_DEBUG(dbgs() << "LAA: Not creating diff runtime check, since these "
                            "cannot be hoisted out of the outer loop\n");
       CanUseDiffCheck = false;
diff --git a/llvm/test/Transforms/LoopVectorize/runtime-checks-hoist.ll b/llvm/test/Transforms/LoopVectorize/runtime-checks-hoist.ll
index 0ae0c7265547..7892db23d528 100644
--- a/llvm/test/Transforms/LoopVectorize/runtime-checks-hoist.ll
+++ b/llvm/test/Transforms/LoopVectorize/runtime-checks-hoist.ll
@@ -4,6 +4,7 @@
 ; RUN:   -force-vector-width=4 -debug-only=loop-accesses,loop-vectorize,loop-utils 2> %t | FileCheck %s
 ; RUN: cat %t | FileCheck %s --check-prefix=DEBUG
 
+target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
 
 ; Equivalent example in C:
 ; void diff_checks(int32_t *dst, int32_t *src, int m, int n) {
@@ -69,11 +70,11 @@ define void @diff_checks(ptr nocapture noundef writeonly %dst, ptr nocapture nou
 ; CHECK-NEXT:    [[TMP14:%.*]] = add nuw nsw i64 [[TMP13]], [[TMP10]]
 ; CHECK-NEXT:    [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[TMP14]]
 ; CHECK-NEXT:    [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[TMP15]], i32 0
-; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4, !alias.scope !0
+; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4, !alias.scope [[META0:![0-9]+]]
 ; CHECK-NEXT:    [[TMP17:%.*]] = add nsw i64 [[TMP13]], [[TMP11]]
 ; CHECK-NEXT:    [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP17]]
 ; CHECK-NEXT:    [[TMP19:%.*]] = getelementptr inbounds i32, ptr [[TMP18]], i32 0
-; CHECK-NEXT:    store <4 x i32> [[WIDE_LOAD]], ptr [[TMP19]], align 4, !alias.scope !3, !noalias !0
+; CHECK-NEXT:    store <4 x i32> [[WIDE_LOAD]], ptr [[TMP19]], align 4, !alias.scope [[META3:![0-9]+]], !noalias [[META0]]
 ; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
 ; CHECK-NEXT:    [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
 ; CHECK-NEXT:    br i1 [[TMP20]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
@@ -189,12 +190,12 @@ define void @full_checks(ptr nocapture noundef %dst, ptr nocapture noundef reado
 ; CHECK-NEXT:    [[TMP5:%.*]] = add nuw nsw i64 [[TMP4]], [[TMP3]]
 ; CHECK-NEXT:    [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[TMP5]]
 ; CHECK-NEXT:    [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP6]], i32 0
-; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 4, !alias.scope !9
+; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 4, !alias.scope [[META9:![0-9]+]]
 ; CHECK-NEXT:    [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP5]]
 ; CHECK-NEXT:    [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[TMP8]], i32 0
-; CHECK-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP9]], align 4, !alias.scope !12, !noalias !9
+; CHECK-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP9]], align 4, !alias.scope [[META12:![0-9]+]], !noalias [[META9]]
 ; CHECK-NEXT:    [[TMP10:%.*]] = add nsw <4 x i32> [[WIDE_LOAD2]], [[WIDE_LOAD]]
-; CHECK-NEXT:    store <4 x i32> [[TMP10]], ptr [[TMP9]], align 4, !alias.scope !12, !noalias !9
+; CHECK-NEXT:    store <4 x i32> [[TMP10]], ptr [[TMP9]], align 4, !alias.scope [[META12]], !noalias [[META9]]
 ; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
 ; CHECK-NEXT:    [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
 ; CHECK-NEXT:    br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]
@@ -319,13 +320,13 @@ define void @full_checks_diff_strides(ptr nocapture noundef %dst, ptr nocapture
 ; CHECK-NEXT:    [[TMP10:%.*]] = add nuw nsw i64 [[TMP9]], [[TMP7]]
 ; CHECK-NEXT:    [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[TMP10]]
 ; CHECK-NEXT:    [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[TMP11]], i32 0
-; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP12]], align 4, !alias.scope !16
+; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP12]], align 4, !alias.scope [[META16:![0-9]+]]
 ; CHECK-NEXT:    [[TMP13:%.*]] = add nuw nsw i64 [[TMP9]], [[TMP8]]
 ; CHECK-NEXT:    [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP13]]
 ; CHECK-NEXT:    [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[TMP14]], i32 0
-; CHECK-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP15]], align 4, !alias.scope !19, !noalias !16
+; CHECK-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP15]], align 4, !alias.scope [[META19:![0-9]+]], !noalias [[META16]]
 ; CHECK-NEXT:    [[TMP16:%.*]] = add nsw <4 x i32> [[WIDE_LOAD2]], [[WIDE_LOAD]]
-; CHECK-NEXT:    store <4 x i32> [[TMP16]], ptr [[TMP15]], align 4, !alias.scope !19, !noalias !16
+; CHECK-NEXT:    store <4 x i32> [[TMP16]], ptr [[TMP15]], align 4, !alias.scope [[META19]], !noalias [[META16]]
 ; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
 ; CHECK-NEXT:    [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
 ; CHECK-NEXT:    br i1 [[TMP17]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP21:![0-9]+]]
@@ -546,13 +547,13 @@ define void @full_checks_src_start_invariant(ptr nocapture noundef %dst, ptr noc
 ; CHECK-NEXT:    [[TMP5:%.*]] = add i64 [[INDEX]], 0
 ; CHECK-NEXT:    [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[TMP5]]
 ; CHECK-NEXT:    [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP6]], i32 0
-; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 4, !alias.scope !25
+; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 4, !alias.scope [[META25:![0-9]+]]
 ; CHECK-NEXT:    [[TMP8:%.*]] = add nuw nsw i64 [[TMP5]], [[TMP4]]
 ; CHECK-NEXT:    [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP8]]
 ; CHECK-NEXT:    [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[TMP9]], i32 0
-; CHECK-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4, !alias.scope !28, !noalias !25
+; CHECK-NEXT:    [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4, !alias.scope [[META28:![0-9]+]], !noalias [[META25]]
 ; CHECK-NEXT:    [[TMP11:%.*]] = add nsw <4 x i32> [[WIDE_LOAD2]], [[WIDE_LOAD]]
-; CHECK-NEXT:    store <4 x i32> [[TMP11]], ptr [[TMP10]], align 4, !alias.scope !28, !noalias !25
+; CHECK-NEXT:    store <4 x i32> [[TMP11]], ptr [[TMP10]], align 4, !alias.scope [[META28]], !noalias [[META25]]
 ; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
 ; CHECK-NEXT:    [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
 ; CHECK-NEXT:    br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP30:![0-9]+]]
@@ -690,13 +691,13 @@ define void @triple_nested_loop_mixed_access(ptr nocapture noundef %dst, ptr noc
 ; CHECK-NEXT:    [[TMP20:%.*]] = add nuw nsw i64 [[TMP19]], [[TMP15]]
 ; CHECK-NEXT:    [[TMP21:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[TMP20]]
 ; CHECK-NEXT:    [[TMP22:%.*]] = getelementptr inbounds i32, ptr [[TMP21]], i32 0
-; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4, !alias.scope !32
+; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4, !alias.scope [[META32:![0-9]+]]
 ; CHECK-NEXT:    [[TMP23:%.*]] = add nuw nsw i64 [[TMP18]], [[TMP19]]
 ; CHECK-NEXT:    [[TMP24:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP23]]
 ; CHECK-NEXT:    [[TMP25:%.*]] = getelementptr inbounds i32, ptr [[TMP24]], i32 0
-; CHECK-NEXT:    [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP25]], align 4, !alias.scope !35, !noalias !32
+; CHECK-NEXT:    [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP25]], align 4, !alias.scope [[META35:![0-9]+]], !noalias [[META32]]
 ; CHECK-NEXT:    [[TMP26:%.*]] = add nsw <4 x i32> [[WIDE_LOAD4]], [[WIDE_LOAD]]
-; CHECK-NEXT:    store <4 x i32> [[TMP26]], ptr [[TMP25]], align 4, !alias.scope !35, !noalias !32
+; CHECK-NEXT:    store <4 x i32> [[TMP26]], ptr [[TMP25]], align 4, !alias.scope [[META35]], !noalias [[META32]]
 ; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
 ; CHECK-NEXT:    [[TMP27:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
 ; CHECK-NEXT:    br i1 [[TMP27]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP37:![0-9]+]]
@@ -847,13 +848,13 @@ define void @uncomputable_outer_tc(ptr nocapture noundef %dst, ptr nocapture nou
 ; CHECK-NEXT:    [[TMP13:%.*]] = add nsw i64 [[TMP12]], [[TMP10]]
 ; CHECK-NEXT:    [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[TMP13]]
 ; CHECK-NEXT:    [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[TMP14]], i32 0
-; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP15]], align 4, !alias.scope !39
+; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP15]], align 4, !alias.scope [[META39:![0-9]+]]
 ; CHECK-NEXT:    [[TMP16:%.*]] = add nsw i64 [[TMP12]], [[TMP11]]
 ; CHECK-NEXT:    [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP16]]
 ; CHECK-NEXT:    [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[TMP17]], i32 0
-; CHECK-NEXT:    [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP18]], align 4, !alias.scope !42, !noalias !39
+; CHECK-NEXT:    [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP18]], align 4, !alias.scope [[META42:![0-9]+]], !noalias [[META39]]
 ; CHECK-NEXT:    [[TMP19:%.*]] = add nsw <4 x i32> [[WIDE_LOAD4]], [[WIDE_LOAD]]
-; CHECK-NEXT:    store <4 x i32> [[TMP19]], ptr [[TMP18]], align 4, !alias.scope !42, !noalias !39
+; CHECK-NEXT:    store <4 x i32> [[TMP19]], ptr [[TMP18]], align 4, !alias.scope [[META42]], !noalias [[META39]]
 ; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
 ; CHECK-NEXT:    [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
 ; CHECK-NEXT:    br i1 [[TMP20]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP44:![0-9]+]]
@@ -1011,17 +1012,17 @@ define void @decreasing_inner_iv(ptr nocapture noundef %dst, ptr nocapture nound
 ; CHECK-NEXT:    [[TMP22:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[TMP21]]
 ; CHECK-NEXT:    [[TMP23:%.*]] = getelementptr inbounds i32, ptr [[TMP22]], i32 0
 ; CHECK-NEXT:    [[TMP24:%.*]] = getelementptr inbounds i32, ptr [[TMP23]], i32 -3
-; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP24]], align 4, !alias.scope !46
+; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP24]], align 4, !alias.scope [[META46:![0-9]+]]
 ; CHECK-NEXT:    [[REVERSE:%.*]] = shufflevector <4 x i32> [[WIDE_LOAD]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
 ; CHECK-NEXT:    [[TMP25:%.*]] = add nsw i64 [[TMP20]], [[TMP17]]
 ; CHECK-NEXT:    [[TMP26:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP25]]
 ; CHECK-NEXT:    [[TMP27:%.*]] = getelementptr inbounds i32, ptr [[TMP26]], i32 0
 ; CHECK-NEXT:    [[TMP28:%.*]] = getelementptr inbounds i32, ptr [[TMP27]], i32 -3
-; CHECK-NEXT:    [[WIDE_LOAD3:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4, !alias.scope !49, !noalias !46
+; CHECK-NEXT:    [[WIDE_LOAD3:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4, !alias.scope [[META49:![0-9]+]], !noalias [[META46]]
 ; CHECK-NEXT:    [[REVERSE4:%.*]] = shufflevector <4 x i32> [[WIDE_LOAD3]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
 ; CHECK-NEXT:    [[TMP29:%.*]] = add nsw <4 x i32> [[REVERSE4]], [[REVERSE]]
 ; CHECK-NEXT:    [[REVERSE5:%.*]] = shufflevector <4 x i32> [[TMP29]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
-; CHECK-NEXT:    store <4 x i32> [[REVERSE5]], ptr [[TMP28]], align 4, !alias.scope !49, !noalias !46
+; CHECK-NEXT:    store <4 x i32> [[REVERSE5]], ptr [[TMP28]], align 4, !alias.scope [[META49]], !noalias [[META46]]
 ; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
 ; CHECK-NEXT:    [[TMP30:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
 ; CHECK-NEXT:    br i1 [[TMP30]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP51:![0-9]+]]
@@ -1176,13 +1177,13 @@ define void @decreasing_outer_iv(ptr nocapture noundef %dst, ptr nocapture nound
 ; CHECK-NEXT:    [[TMP20:%.*]] = add nsw i64 [[TMP19]], [[TMP15]]
 ; CHECK-NEXT:    [[TMP21:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[TMP20]]
 ; CHECK-NEXT:    [[TMP22:%.*]] = getelementptr inbounds i32, ptr [[TMP21]], i32 0
-; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4, !alias.scope !53
+; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4, !alias.scope [[META53:![0-9]+]]
 ; CHECK-NEXT:    [[TMP23:%.*]] = add nsw i64 [[TMP19]], [[TMP16]]
 ; CHECK-NEXT:    [[TMP24:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP23]]
 ; CHECK-NEXT:    [[TMP25:%.*]] = getelementptr inbounds i32, ptr [[TMP24]], i32 0
-; CHECK-NEXT:    [[WIDE_LOAD5:%.*]] = load <4 x i32>, ptr [[TMP25]], align 4, !alias.scope !56, !noalias !53
+; CHECK-NEXT:    [[WIDE_LOAD5:%.*]] = load <4 x i32>, ptr [[TMP25]], align 4, !alias.scope [[META56:![0-9]+]], !noalias [[META53]]
 ; CHECK-NEXT:    [[TMP26:%.*]] = add nsw <4 x i32> [[WIDE_LOAD5]], [[WIDE_LOAD]]
-; CHECK-NEXT:    store <4 x i32> [[TMP26]], ptr [[TMP25]], align 4, !alias.scope !56, !noalias !53
+; CHECK-NEXT:    store <4 x i32> [[TMP26]], ptr [[TMP25]], align 4, !alias.scope [[META56]], !noalias [[META53]]
 ; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
 ; CHECK-NEXT:    [[TMP27:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
 ; CHECK-NEXT:    br i1 [[TMP27]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP58:![0-9]+]]
@@ -1331,14 +1332,14 @@ define void @unknown_inner_stride(ptr nocapture noundef %dst, ptr nocapture noun
 ; CHECK-NEXT:    [[TMP16:%.*]] = add nsw i64 [[TMP15]], [[TMP11]]
 ; CHECK-NEXT:    [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[TMP16]]
 ; CHECK-NEXT:    [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[TMP17]], i32 0
-; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP18]], align 4, !alias.scope !60
+; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP18]], align 4, !alias.scope [[META60:![0-9]+]]
 ; CHECK-NEXT:    [[TMP19:%.*]] = mul nsw i64 [[TMP14]], [[TMP1]]
 ; CHECK-NEXT:    [[TMP20:%.*]] = add nsw i64 [[TMP19]], [[TMP12]]
 ; CHECK-NEXT:    [[TMP21:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP20]]
 ; CHECK-NEXT:    [[TMP22:%.*]] = getelementptr inbounds i32, ptr [[TMP21]], i32 0
-; CHECK-NEXT:    [[WIDE_LOAD3:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4, !alias.scope !63, !noalias !60
+; CHECK-NEXT:    [[WIDE_LOAD3:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4, !alias.scope [[META63:![0-9]+]], !noalias [[META60]]
 ; CHECK-NEXT:    [[TMP23:%.*]] = add nsw <4 x i32> [[WIDE_LOAD3]], [[WIDE_LOAD]]
-; CHECK-NEXT:    store <4 x i32> [[TMP23]], ptr [[TMP22]], align 4, !alias.scope !63, !noalias !60
+; CHECK-NEXT:    store <4 x i32> [[TMP23]], ptr [[TMP22]], align 4, !alias.scope [[META63]], !noalias [[META60]]
 ; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
 ; CHECK-NEXT:    [[TMP24:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
 ; CHECK-NEXT:    br i1 [[TMP24]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP65:![0-9]+]]
@@ -1418,3 +1419,94 @@ inner.loop.exit:
 exit:
   ret void
 }
+
+
+; Test case where the AddRec for the pointers in the inner loop have the AddRec
+; of the outer loop as start value. It is sufficient to subtract the start
+; values (%dst, %src) of the outer AddRecs.
+define void @nested_loop_start_of_inner_ptr_addrec_is_same_outer_addrec(ptr nocapture noundef %dst, ptr nocapture noundef readonly %src, i64 noundef %m, i64 noundef %n) {
+; CHECK-LABEL: define void @nested_loop_start_of_inner_ptr_addrec_is_same_outer_addrec
+; CHECK-SAME: (ptr nocapture noundef [[DST:%.*]], ptr nocapture noundef readonly [[SRC:%.*]], i64 noundef [[M:%.*]], i64 noundef [[N:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[SRC2:%.*]] = ptrtoint ptr [[SRC]] to i64
+; CHECK-NEXT:    [[DST1:%.*]] = ptrtoint ptr [[DST]] to i64
+; CHECK-NEXT:    [[TMP0:%.*]] = sub i64 [[DST1]], [[SRC2]]
+; CHECK-NEXT:    br label [[OUTER_LOOP:%.*]]
+; CHECK:       outer.loop:
+; CHECK-NEXT:    [[OUTER_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[OUTER_IV_NEXT:%.*]], [[INNER_EXIT:%.*]] ]
+; CHECK-NEXT:    [[MUL:%.*]] = mul nsw i64 [[OUTER_IV]], [[N]]
+; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4
+; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]]
+; CHECK:       vector.memcheck:
+; CHECK-NEXT:    [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP0]], 16
+; CHECK-NEXT:    br i1 [[DIFF_CHECK]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
+; CHECK:       vector.ph:
+; CHECK-NEXT:    [[N_MOD_VF:%.*]] = urem i64 [[N]], 4
+; CHECK-NEXT:    [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
+; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
+; CHECK:       vector.body:
+; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[TMP1:%.*]] = add i64 [[INDEX]], 0
+; CHECK-NEXT:    [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], [[MUL]]
+; CHECK-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[TMP2]]
+; CHECK-NEXT:    [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i32 0
+; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4
+; CHECK-NEXT:    [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP2]]
+; CHECK-NEXT:    [[TMP6:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], <i32 10, i32 10, i32 10, i32 10>
+; CHECK-NEXT:    [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i32 0
+; CHECK-NEXT:    store <4 x i32> [[TMP6]], ptr [[TMP7]], align 4
+; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
+; CHECK-NEXT:    [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT:    br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP67:![0-9]+]]
+; CHECK:       middle.block:
+; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
+; CHECK-NEXT:    br i1 [[CMP_N]], label [[INNER_EXIT]], label [[SCALAR_PH]]
+; CHECK:       scalar.ph:
+; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[OUTER_LOOP]] ], [ 0, [[VECTOR_MEMCHECK]] ]
+; CHECK-NEXT:    br label [[INNER_LOOP:%.*]]
+; CHECK:       inner.loop:
+; CHECK-NEXT:    [[IV_INNER:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_INNER_NEXT:%.*]], [[INNER_LOOP]] ]
+; CHECK-NEXT:    [[IDX:%.*]] = add nuw nsw i64 [[IV_INNER]], [[MUL]]
+; CHECK-NEXT:    [[GEP_SRC:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[IDX]]
+; CHECK-NEXT:    [[L:%.*]] = load i32, ptr [[GEP_SRC]], align 4
+; CHECK-NEXT:    [[GEP_DST:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[IDX]]
+; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[L]], 10
+; CHECK-NEXT:    store i32 [[ADD]], ptr [[GEP_DST]], align 4
+; CHECK-NEXT:    [[IV_INNER_NEXT]] = add nuw nsw i64 [[IV_INNER]], 1
+; CHECK-NEXT:    [[INNER_EXIT_COND:%.*]] = icmp eq i64 [[IV_INNER_NEXT]], [[N]]
+; CHECK-NEXT:    br i1 [[INNER_EXIT_COND]], label [[INNER_EXIT]], label [[INNER_LOOP]], !llvm.loop [[LOOP68:![0-9]+]]
+; CHECK:       inner.exit:
+; CHECK-NEXT:    [[OUTER_IV_NEXT]] = add nuw nsw i64 [[OUTER_IV]], 1
+; CHECK-NEXT:    [[OUTER_EXIT_COND:%.*]] = icmp eq i64 [[OUTER_IV_NEXT]], [[M]]
+; CHECK-NEXT:    br i1 [[OUTER_EXIT_COND]], label [[OUTER_EXIT:%.*]], label [[OUTER_LOOP]]
+; CHECK:       outer.exit:
+; CHECK-NEXT:    ret void
+;
+entry:
+  br label %outer.loop
+
+outer.loop:
+  %outer.iv = phi i64 [ 0, %entry ], [ %outer.iv.next, %inner.exit ]
+  %mul = mul nsw i64 %outer.iv, %n
+  br label %inner.loop
+
+inner.loop:
+  %iv.inner = phi i64 [ 0, %outer.loop ], [ %iv.inner.next, %inner.loop ]
+  %idx = add nuw nsw i64 %iv.inner, %mul
+  %gep.src = getelementptr inbounds i32, ptr %src, i64 %idx
+  %l = load i32, ptr %gep.src, align 4
+  %gep.dst = getelementptr inbounds i32, ptr %dst, i64 %idx
+  %add = add nsw i32 %l, 10
+  store i32 %add, ptr %gep.dst, align 4
+  %iv.inner.next = add nuw nsw i64 %iv.inner, 1
+  %inner.exit.cond = icmp eq i64 %iv.inner.next, %n
+  br i1 %inner.exit.cond, label %inner.exit, label %inner.loop
+
+inner.exit:
+  %outer.iv.next = add nuw nsw i64 %outer.iv, 1
+  %outer.exit.cond = icmp eq i64 %outer.iv.next, %m
+  br i1 %outer.exit.cond, label %outer.exit, label %outer.loop
+
+outer.exit:
+  ret void
+}
-- 
GitLab


From e052c688690f1eac5a6ca294a687f52a7e1305cc Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp@bytedance.com>
Date: Tue, 12 Dec 2023 17:12:08 +0800
Subject: [PATCH 242/349] [SelectionDAG] Add instantiated OPC_CheckType
 (#73283)

The most common type is i32 or i64 so we add `OPC_CheckTypeI32` and
`OPC_CheckTypeI64` to save one byte.

Overall this reduces the llc binary size with all in-tree targets by
about 29K.
---
 llvm/include/llvm/CodeGen/SelectionDAGISel.h  |  3 +
 .../CodeGen/SelectionDAG/SelectionDAGISel.cpp | 81 +++++++++++++------
 llvm/test/TableGen/dag-isel-complexpattern.td |  2 +-
 llvm/utils/TableGen/DAGISelMatcherEmitter.cpp | 13 ++-
 4 files changed, 69 insertions(+), 30 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index aa71be5d1960..16f070650aa6 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -156,6 +156,9 @@ public:
     OPC_CheckOpcode,
     OPC_SwitchOpcode,
     OPC_CheckType,
+    // Space-optimized forms that implicitly encode VT.
+    OPC_CheckTypeI32,
+    OPC_CheckTypeI64,
     OPC_CheckTypeRes,
     OPC_SwitchType,
     OPC_CheckChild0Type,
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 2018b5f0ee29..9fe8ecff184c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -2711,11 +2711,10 @@ CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
   return N->getOpcode() == Opc;
 }
 
-LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
-CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N,
-          const TargetLowering *TLI, const DataLayout &DL) {
-  MVT::SimpleValueType VT =
-      static_cast<MVT::SimpleValueType>(MatcherTable[MatcherIndex++]);
+LLVM_ATTRIBUTE_ALWAYS_INLINE static bool CheckType(MVT::SimpleValueType VT,
+                                                   SDValue N,
+                                                   const TargetLowering *TLI,
+                                                   const DataLayout &DL) {
   if (N.getValueType() == VT)
     return true;
 
@@ -2724,13 +2723,11 @@ CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N,
 }
 
 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
-CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
-               SDValue N, const TargetLowering *TLI, const DataLayout &DL,
-               unsigned ChildNo) {
+CheckChildType(MVT::SimpleValueType VT, SDValue N, const TargetLowering *TLI,
+               const DataLayout &DL, unsigned ChildNo) {
   if (ChildNo >= N.getNumOperands())
-    return false;  // Match fails if out of range child #.
-  return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI,
-                     DL);
+    return false; // Match fails if out of range child #.
+  return ::CheckType(VT, N.getOperand(ChildNo), TLI, DL);
 }
 
 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
@@ -2829,7 +2826,8 @@ static unsigned IsPredicateKnownToFail(const unsigned char *Table,
                                        bool &Result,
                                        const SelectionDAGISel &SDISel,
                   SmallVectorImpl<std::pair<SDValue, SDNode*>> &RecordedNodes) {
-  switch (Table[Index++]) {
+  unsigned Opcode = Table[Index++];
+  switch (Opcode) {
   default:
     Result = false;
     return Index-1;  // Could not evaluate this predicate.
@@ -2856,12 +2854,27 @@ static unsigned IsPredicateKnownToFail(const unsigned char *Table,
     Result = !::CheckOpcode(Table, Index, N.getNode());
     return Index;
   case SelectionDAGISel::OPC_CheckType:
-    Result = !::CheckType(Table, Index, N, SDISel.TLI,
-                          SDISel.CurDAG->getDataLayout());
+  case SelectionDAGISel::OPC_CheckTypeI32:
+  case SelectionDAGISel::OPC_CheckTypeI64: {
+    MVT::SimpleValueType VT;
+    switch (Opcode) {
+    case SelectionDAGISel::OPC_CheckTypeI32:
+      VT = MVT::i32;
+      break;
+    case SelectionDAGISel::OPC_CheckTypeI64:
+      VT = MVT::i64;
+      break;
+    default:
+      VT = static_cast<MVT::SimpleValueType>(Table[Index++]);
+      break;
+    }
+    Result = !::CheckType(VT, N, SDISel.TLI, SDISel.CurDAG->getDataLayout());
     return Index;
+  }
   case SelectionDAGISel::OPC_CheckTypeRes: {
     unsigned Res = Table[Index++];
-    Result = !::CheckType(Table, Index, N.getValue(Res), SDISel.TLI,
+    Result = !::CheckType(static_cast<MVT::SimpleValueType>(Table[Index++]),
+                          N.getValue(Res), SDISel.TLI,
                           SDISel.CurDAG->getDataLayout());
     return Index;
   }
@@ -2872,11 +2885,13 @@ static unsigned IsPredicateKnownToFail(const unsigned char *Table,
   case SelectionDAGISel::OPC_CheckChild4Type:
   case SelectionDAGISel::OPC_CheckChild5Type:
   case SelectionDAGISel::OPC_CheckChild6Type:
-  case SelectionDAGISel::OPC_CheckChild7Type:
-    Result = !::CheckChildType(
-                 Table, Index, N, SDISel.TLI, SDISel.CurDAG->getDataLayout(),
-                 Table[Index - 1] - SelectionDAGISel::OPC_CheckChild0Type);
+  case SelectionDAGISel::OPC_CheckChild7Type: {
+    Result =
+        !::CheckChildType(static_cast<MVT::SimpleValueType>(Table[Index++]), N,
+                          SDISel.TLI, SDISel.CurDAG->getDataLayout(),
+                          Opcode - SelectionDAGISel::OPC_CheckChild0Type);
     return Index;
+  }
   case SelectionDAGISel::OPC_CheckCondCode:
     Result = !::CheckCondCode(Table, Index, N);
     return Index;
@@ -3306,15 +3321,29 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
       continue;
 
     case OPC_CheckType:
-      if (!::CheckType(MatcherTable, MatcherIndex, N, TLI,
-                       CurDAG->getDataLayout()))
+    case OPC_CheckTypeI32:
+    case OPC_CheckTypeI64:
+      MVT::SimpleValueType VT;
+      switch (Opcode) {
+      case OPC_CheckTypeI32:
+        VT = MVT::i32;
+        break;
+      case OPC_CheckTypeI64:
+        VT = MVT::i64;
+        break;
+      default:
+        VT = static_cast<MVT::SimpleValueType>(MatcherTable[MatcherIndex++]);
+        break;
+      }
+      if (!::CheckType(VT, N, TLI, CurDAG->getDataLayout()))
         break;
       continue;
 
     case OPC_CheckTypeRes: {
       unsigned Res = MatcherTable[MatcherIndex++];
-      if (!::CheckType(MatcherTable, MatcherIndex, N.getValue(Res), TLI,
-                       CurDAG->getDataLayout()))
+      if (!::CheckType(
+              static_cast<MVT::SimpleValueType>(MatcherTable[MatcherIndex++]),
+              N.getValue(Res), TLI, CurDAG->getDataLayout()))
         break;
       continue;
     }
@@ -3387,9 +3416,9 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
     case OPC_CheckChild2Type: case OPC_CheckChild3Type:
     case OPC_CheckChild4Type: case OPC_CheckChild5Type:
     case OPC_CheckChild6Type: case OPC_CheckChild7Type:
-      if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
-                            CurDAG->getDataLayout(),
-                            Opcode - OPC_CheckChild0Type))
+      if (!::CheckChildType(
+              static_cast<MVT::SimpleValueType>(MatcherTable[MatcherIndex++]),
+              N, TLI, CurDAG->getDataLayout(), Opcode - OPC_CheckChild0Type))
         break;
       continue;
     case OPC_CheckCondCode:
diff --git a/llvm/test/TableGen/dag-isel-complexpattern.td b/llvm/test/TableGen/dag-isel-complexpattern.td
index 40fd03cc8839..3d74e4e46dc4 100644
--- a/llvm/test/TableGen/dag-isel-complexpattern.td
+++ b/llvm/test/TableGen/dag-isel-complexpattern.td
@@ -21,7 +21,7 @@ def CP32 : ComplexPattern<i32, 0, "SelectCP32">;
 // (CP32) still worked.
 def INSTR : Instruction {
 // CHECK-LABEL: OPC_CheckOpcode, TARGET_VAL(ISD::STORE)
-// CHECK: OPC_CheckType, MVT::i32
+// CHECK: OPC_CheckTypeI32
 // CHECK: OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectCP32:$
 // CHECK: Src: (st (add:{ *:[i32] } (CP32:{ *:[i32] }), (CP32:{ *:[i32] })), i64:{ *:[i64] }:$addr)
   let OutOperandList = (outs);
diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
index ed4be74ad0d4..6077efe30b5e 100644
--- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
@@ -578,9 +578,16 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx,
 
  case Matcher::CheckType:
     if (cast<CheckTypeMatcher>(N)->getResNo() == 0) {
-      OS << "OPC_CheckType, "
-         << getEnumName(cast<CheckTypeMatcher>(N)->getType()) << ",\n";
-      return 2;
+      MVT::SimpleValueType VT = cast<CheckTypeMatcher>(N)->getType();
+      switch (VT) {
+      case MVT::i32:
+      case MVT::i64:
+        OS << "OPC_CheckTypeI" << MVT(VT).getSizeInBits() << ",\n";
+        return 1;
+      default:
+        OS << "OPC_CheckType, " << getEnumName(VT) << ",\n";
+        return 2;
+      }
     }
     OS << "OPC_CheckTypeRes, " << cast<CheckTypeMatcher>(N)->getResNo()
        << ", " << getEnumName(cast<CheckTypeMatcher>(N)->getType()) << ",\n";
-- 
GitLab


From 50c174f99f4207fab1188762a68104e7843f834c Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp@bytedance.com>
Date: Tue, 12 Dec 2023 17:13:43 +0800
Subject: [PATCH 243/349] [SelectionDAG] Add space-optimized forms of
 OPC_EmitConvertToTarget (#73286)

These new opcodes implicitly indicate the RecNo.

Overall this reduces the llc binary size with all in-tree targets by
about 13K.
---
 llvm/include/llvm/CodeGen/SelectionDAGISel.h       |  8 ++++++++
 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 14 ++++++++++++--
 llvm/utils/TableGen/DAGISelMatcherEmitter.cpp      | 11 ++++++++---
 3 files changed, 28 insertions(+), 5 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index 16f070650aa6..8a0e790bd170 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -197,6 +197,14 @@ public:
     OPC_EmitRegister,
     OPC_EmitRegister2,
     OPC_EmitConvertToTarget,
+    OPC_EmitConvertToTarget0,
+    OPC_EmitConvertToTarget1,
+    OPC_EmitConvertToTarget2,
+    OPC_EmitConvertToTarget3,
+    OPC_EmitConvertToTarget4,
+    OPC_EmitConvertToTarget5,
+    OPC_EmitConvertToTarget6,
+    OPC_EmitConvertToTarget7,
     OPC_EmitMergeInputChains,
     OPC_EmitMergeInputChains1_0,
     OPC_EmitMergeInputChains1_1,
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 9fe8ecff184c..09d5a74688e4 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -3541,9 +3541,19 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
       continue;
     }
 
-    case OPC_EmitConvertToTarget:  {
+    case OPC_EmitConvertToTarget:
+    case OPC_EmitConvertToTarget0:
+    case OPC_EmitConvertToTarget1:
+    case OPC_EmitConvertToTarget2:
+    case OPC_EmitConvertToTarget3:
+    case OPC_EmitConvertToTarget4:
+    case OPC_EmitConvertToTarget5:
+    case OPC_EmitConvertToTarget6:
+    case OPC_EmitConvertToTarget7: {
       // Convert from IMM/FPIMM to target version.
-      unsigned RecNo = MatcherTable[MatcherIndex++];
+      unsigned RecNo = Opcode == OPC_EmitConvertToTarget
+                           ? MatcherTable[MatcherIndex++]
+                           : Opcode - OPC_EmitConvertToTarget0;
       assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
       SDValue Imm = RecordedNodes[RecNo].first;
 
diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
index 6077efe30b5e..c9ee071fd8d3 100644
--- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
@@ -737,10 +737,15 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx,
     }
   }
 
-  case Matcher::EmitConvertToTarget:
-    OS << "OPC_EmitConvertToTarget, "
-       << cast<EmitConvertToTargetMatcher>(N)->getSlot() << ",\n";
+  case Matcher::EmitConvertToTarget: {
+    unsigned Slot = cast<EmitConvertToTargetMatcher>(N)->getSlot();
+    if (Slot < 8) {
+      OS << "OPC_EmitConvertToTarget" << Slot << ",\n";
+      return 1;
+    }
+    OS << "OPC_EmitConvertToTarget, " << Slot << ",\n";
     return 2;
+  }
 
   case Matcher::EmitMergeInputChains: {
     const EmitMergeInputChainsMatcher *MN =
-- 
GitLab


From b010747a4f481d4f2119ffa52f5da75e8cc8c6da Mon Sep 17 00:00:00 2001
From: Thomas Symalla <5754458+tsymalla@users.noreply.github.com>
Date: Tue, 12 Dec 2023 10:24:11 +0100
Subject: [PATCH 244/349] [NFC] Fix typo in ConstraintElimination assertion.
 (#75151)

unsinged => unsigned

Co-authored-by: Thomas Symalla <tsymalla@amd.com>
---
 llvm/lib/Transforms/Scalar/ConstraintElimination.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp b/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
index 43d9883fcfd4..fafbe17583f5 100644
--- a/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+++ b/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
@@ -431,7 +431,7 @@ static Decomposition decomposeGEP(GEPOperator &GEP,
     return &GEP;
 
   assert(!IsSigned && "The logic below only supports decomposition for "
-                      "unsinged predicates at the moment.");
+                      "unsigned predicates at the moment.");
   const auto &[BasePtr, ConstantOffset, VariableOffsets, AllInbounds] =
       collectOffsets(GEP, DL);
   if (!BasePtr || !AllInbounds)
-- 
GitLab


From cbf1d58820877b06a379005c155bf354cece57ff Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp@bytedance.com>
Date: Tue, 12 Dec 2023 17:25:33 +0800
Subject: [PATCH 245/349] [SelectionDAG] Add space-optimized forms of
 OPC_EmitCopyToReg (#73293)

These new opcodes implicitly indicate the RecNo.

The old `OPC_EmitCopyToReg2` is renamed to `OPC_EmitCopyToRegTwoByte`.

Overall this reduces the llc binary size with all in-tree targets by
about 33K (most are from RISCV target).
---
 llvm/include/llvm/CodeGen/SelectionDAGISel.h    |  8 ++++++++
 .../CodeGen/SelectionDAG/SelectionDAGISel.cpp   | 17 ++++++++++++++---
 llvm/utils/TableGen/DAGISelMatcherEmitter.cpp   | 12 +++++++++---
 3 files changed, 31 insertions(+), 6 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index 8a0e790bd170..ca3d03408629 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -210,7 +210,15 @@ public:
     OPC_EmitMergeInputChains1_1,
     OPC_EmitMergeInputChains1_2,
     OPC_EmitCopyToReg,
+    OPC_EmitCopyToReg0,
+    OPC_EmitCopyToReg1,
     OPC_EmitCopyToReg2,
+    OPC_EmitCopyToReg3,
+    OPC_EmitCopyToReg4,
+    OPC_EmitCopyToReg5,
+    OPC_EmitCopyToReg6,
+    OPC_EmitCopyToReg7,
+    OPC_EmitCopyToRegTwoByte,
     OPC_EmitNodeXForm,
     OPC_EmitNode,
     // Space-optimized forms that implicitly encode number of result VTs.
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 09d5a74688e4..9c423dba7d2c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -3649,11 +3649,22 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
     }
 
     case OPC_EmitCopyToReg:
-    case OPC_EmitCopyToReg2: {
-      unsigned RecNo = MatcherTable[MatcherIndex++];
+    case OPC_EmitCopyToReg0:
+    case OPC_EmitCopyToReg1:
+    case OPC_EmitCopyToReg2:
+    case OPC_EmitCopyToReg3:
+    case OPC_EmitCopyToReg4:
+    case OPC_EmitCopyToReg5:
+    case OPC_EmitCopyToReg6:
+    case OPC_EmitCopyToReg7:
+    case OPC_EmitCopyToRegTwoByte: {
+      unsigned RecNo =
+          Opcode >= OPC_EmitCopyToReg0 && Opcode <= OPC_EmitCopyToReg7
+              ? Opcode - OPC_EmitCopyToReg0
+              : MatcherTable[MatcherIndex++];
       assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
       unsigned DestPhysReg = MatcherTable[MatcherIndex++];
-      if (Opcode == OPC_EmitCopyToReg2)
+      if (Opcode == OPC_EmitCopyToRegTwoByte)
         DestPhysReg |= MatcherTable[MatcherIndex++] << 8;
 
       if (!InputChain.getNode())
diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
index c9ee071fd8d3..22bf5926966d 100644
--- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
@@ -767,14 +767,20 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx,
     const auto *C2RMatcher = cast<EmitCopyToRegMatcher>(N);
     int Bytes = 3;
     const CodeGenRegister *Reg = C2RMatcher->getDestPhysReg();
+    unsigned Slot = C2RMatcher->getSrcSlot();
     if (Reg->EnumValue > 255) {
       assert(isUInt<16>(Reg->EnumValue) && "not handled");
-      OS << "OPC_EmitCopyToReg2, " << C2RMatcher->getSrcSlot() << ", "
+      OS << "OPC_EmitCopyToRegTwoByte, " << Slot << ", "
          << "TARGET_VAL(" << getQualifiedName(Reg->TheDef) << "),\n";
       ++Bytes;
     } else {
-      OS << "OPC_EmitCopyToReg, " << C2RMatcher->getSrcSlot() << ", "
-         << getQualifiedName(Reg->TheDef) << ",\n";
+      if (Slot < 8) {
+        OS << "OPC_EmitCopyToReg" << Slot << ", "
+           << getQualifiedName(Reg->TheDef) << ",\n";
+        --Bytes;
+      } else
+        OS << "OPC_EmitCopyToReg, " << Slot << ", "
+           << getQualifiedName(Reg->TheDef) << ",\n";
     }
 
     return Bytes;
-- 
GitLab


From e00ade1144ef661b01e195e4bf4a3e4b18c4328f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Stefan=20Gr=C3=A4nitz?= <stefan.graenitz@gmail.com>
Date: Tue, 12 Dec 2023 10:03:16 +0100
Subject: [PATCH 246/349] [llvm-c] Mitigate debug support test for systems that
 still default to RuntimeDyld

Fix test failure reported from buildbot clang-s390x-linux-lnt after #73257
OrcCAPITest.cpp:562: Debugger support requires JITLink
---
 llvm/unittests/ExecutionEngine/Orc/OrcCAPITest.cpp | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/llvm/unittests/ExecutionEngine/Orc/OrcCAPITest.cpp b/llvm/unittests/ExecutionEngine/Orc/OrcCAPITest.cpp
index 65d2f57234d0..d62973f30add 100644
--- a/llvm/unittests/ExecutionEngine/Orc/OrcCAPITest.cpp
+++ b/llvm/unittests/ExecutionEngine/Orc/OrcCAPITest.cpp
@@ -14,6 +14,7 @@
 #include "gtest/gtest.h"
 
 #include "llvm/ExecutionEngine/Orc/CompileUtils.h"
+#include "llvm/ExecutionEngine/Orc/ObjectLinkingLayer.h"
 #include "llvm/ExecutionEngine/Orc/TargetProcess/JITLoaderGDB.h"
 #include "llvm/IR/LLVMContext.h"
 #include "llvm/IR/Module.h"
@@ -28,6 +29,7 @@
 using namespace llvm;
 using namespace llvm::orc;
 
+DEFINE_SIMPLE_CONVERSION_FUNCTIONS(ObjectLayer, LLVMOrcObjectLayerRef)
 DEFINE_SIMPLE_CONVERSION_FUNCTIONS(ThreadSafeModule, LLVMOrcThreadSafeModuleRef)
 
 // OrcCAPITestBase contains several helper methods and pointers for unit tests
@@ -558,13 +560,17 @@ static LLVM_ATTRIBUTE_USED void linkComponents() {
 }
 TEST_F(OrcCAPITestBase, EnableDebugSupport) {
 #endif
-  if (LLVMErrorRef E = LLVMOrcLLJITEnableDebugSupport(Jit))
-    FAIL() << "Error testing LLJIT debug support (triple = " << TargetTriple
-           << "): " << toString(E);
-
   void *Before = findLastDebugDescriptorEntryPtr();
   LLVMMemoryBufferRef ObjBuffer = createTestObject(SumDebugExample, "sum.ll");
   LLVMOrcObjectLayerRef ObjLayer = LLVMOrcLLJITGetObjLinkingLayer(Jit);
+
+  if (LLVMErrorRef E = LLVMOrcLLJITEnableDebugSupport(Jit)) {
+    EXPECT_FALSE(isa<ObjectLinkingLayer>(unwrap(ObjLayer)))
+        << "Error testing LLJIT debug support "
+        << "(triple = " << TargetTriple << "): " << toString(E);
+    GTEST_SKIP() << "LLJIT C bindings provide debug support only for JITLink";
+  }
+
   if (LLVMErrorRef E =
           LLVMOrcObjectLayerAddObjectFile(ObjLayer, MainDylib, ObjBuffer))
     FAIL() << "Failed to add object file to ObjLinkingLayer (triple = "
-- 
GitLab


From 117d083845cc3910ffc0a8016f641ae835ffaa73 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Stefan=20Gr=C3=A4nitz?= <stefan.graenitz@gmail.com>
Date: Tue, 12 Dec 2023 10:20:07 +0100
Subject: [PATCH 247/349] [JITLink][AArch32] Drop anonymous namespaces around
 FixupInfo helper classes (NFC)

This fixes various buildbots reporting subobject-linkage warnings after #71649:
<class> has a base <name> whose type uses the anonymous namespace
---
 llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h b/llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h
index 51413a46dc41..f346cfb2a931 100644
--- a/llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h
+++ b/llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h
@@ -195,12 +195,10 @@ struct FixupInfoThumb : public FixupInfoBase {
 ///
 template <EdgeKind_aarch32 Kind> struct FixupInfo {};
 
-namespace {
 struct FixupInfoArmBranch : public FixupInfoArm {
   static constexpr uint32_t Opcode = 0x0a000000;
   static constexpr uint32_t ImmMask = 0x00ffffff;
 };
-} // namespace
 
 template <> struct FixupInfo<Arm_Jump24> : public FixupInfoArmBranch {
   static constexpr uint32_t OpcodeMask = 0x0f000000;
@@ -214,13 +212,11 @@ template <> struct FixupInfo<Arm_Call> : public FixupInfoArmBranch {
   static constexpr uint32_t BitBlx = 0x10000000;
 };
 
-namespace {
 struct FixupInfoArmMov : public FixupInfoArm {
   static constexpr uint32_t OpcodeMask = 0x0ff00000;
   static constexpr uint32_t ImmMask = 0x000f0fff;
   static constexpr uint32_t RegMask = 0x0000f000;
 };
-} // namespace
 
 template <> struct FixupInfo<Arm_MovtAbs> : public FixupInfoArmMov {
   static constexpr uint32_t Opcode = 0x03400000;
@@ -244,13 +240,11 @@ template <> struct FixupInfo<Thumb_Call> : public FixupInfoThumb {
   static constexpr uint16_t LoBitNoBlx = 0x1000;
 };
 
-namespace {
 struct FixupInfoThumbMov : public FixupInfoThumb {
   static constexpr HalfWords OpcodeMask{0xfbf0, 0x8000};
   static constexpr HalfWords ImmMask{0x040f, 0x70ff};
   static constexpr HalfWords RegMask{0x0000, 0x0f00};
 };
-} // namespace
 
 template <> struct FixupInfo<Thumb_MovtAbs> : public FixupInfoThumbMov {
   static constexpr HalfWords Opcode{0xf2c0, 0x0000};
-- 
GitLab


From 6111f5c5925cb40357e2a972ebae4294731c307f Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp@bytedance.com>
Date: Tue, 12 Dec 2023 17:31:12 +0800
Subject: [PATCH 248/349] [SelectionDAG] Add instantiated OPC_CheckChildType
 (#73297)

The most common type is i32 or i64 so we add `OPC_CheckChildTypeI32`
and `OPC_CheckChildTypeI64` to save one byte.

Overall this reduces the llc binary size with all in-tree targets by
about 70K.
---
 llvm/include/llvm/CodeGen/SelectionDAGISel.h  | 19 +++++
 .../CodeGen/SelectionDAG/SelectionDAGISel.cpp | 85 ++++++++++++++++---
 llvm/utils/TableGen/DAGISelMatcherEmitter.cpp | 19 +++--
 3 files changed, 106 insertions(+), 17 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index ca3d03408629..9b3a2352fb1a 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -169,6 +169,25 @@ public:
     OPC_CheckChild5Type,
     OPC_CheckChild6Type,
     OPC_CheckChild7Type,
+
+    OPC_CheckChild0TypeI32,
+    OPC_CheckChild1TypeI32,
+    OPC_CheckChild2TypeI32,
+    OPC_CheckChild3TypeI32,
+    OPC_CheckChild4TypeI32,
+    OPC_CheckChild5TypeI32,
+    OPC_CheckChild6TypeI32,
+    OPC_CheckChild7TypeI32,
+
+    OPC_CheckChild0TypeI64,
+    OPC_CheckChild1TypeI64,
+    OPC_CheckChild2TypeI64,
+    OPC_CheckChild3TypeI64,
+    OPC_CheckChild4TypeI64,
+    OPC_CheckChild5TypeI64,
+    OPC_CheckChild6TypeI64,
+    OPC_CheckChild7TypeI64,
+
     OPC_CheckInteger,
     OPC_CheckChild0Integer,
     OPC_CheckChild1Integer,
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 9c423dba7d2c..cba25b8d7c02 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -2885,11 +2885,39 @@ static unsigned IsPredicateKnownToFail(const unsigned char *Table,
   case SelectionDAGISel::OPC_CheckChild4Type:
   case SelectionDAGISel::OPC_CheckChild5Type:
   case SelectionDAGISel::OPC_CheckChild6Type:
-  case SelectionDAGISel::OPC_CheckChild7Type: {
-    Result =
-        !::CheckChildType(static_cast<MVT::SimpleValueType>(Table[Index++]), N,
-                          SDISel.TLI, SDISel.CurDAG->getDataLayout(),
-                          Opcode - SelectionDAGISel::OPC_CheckChild0Type);
+  case SelectionDAGISel::OPC_CheckChild7Type:
+  case SelectionDAGISel::OPC_CheckChild0TypeI32:
+  case SelectionDAGISel::OPC_CheckChild1TypeI32:
+  case SelectionDAGISel::OPC_CheckChild2TypeI32:
+  case SelectionDAGISel::OPC_CheckChild3TypeI32:
+  case SelectionDAGISel::OPC_CheckChild4TypeI32:
+  case SelectionDAGISel::OPC_CheckChild5TypeI32:
+  case SelectionDAGISel::OPC_CheckChild6TypeI32:
+  case SelectionDAGISel::OPC_CheckChild7TypeI32:
+  case SelectionDAGISel::OPC_CheckChild0TypeI64:
+  case SelectionDAGISel::OPC_CheckChild1TypeI64:
+  case SelectionDAGISel::OPC_CheckChild2TypeI64:
+  case SelectionDAGISel::OPC_CheckChild3TypeI64:
+  case SelectionDAGISel::OPC_CheckChild4TypeI64:
+  case SelectionDAGISel::OPC_CheckChild5TypeI64:
+  case SelectionDAGISel::OPC_CheckChild6TypeI64:
+  case SelectionDAGISel::OPC_CheckChild7TypeI64: {
+    MVT::SimpleValueType VT;
+    unsigned ChildNo;
+    if (Opcode >= SelectionDAGISel::OPC_CheckChild0TypeI32 &&
+        Opcode <= SelectionDAGISel::OPC_CheckChild7TypeI32) {
+      VT = MVT::i32;
+      ChildNo = Opcode - SelectionDAGISel::OPC_CheckChild0TypeI32;
+    } else if (Opcode >= SelectionDAGISel::OPC_CheckChild0TypeI64 &&
+               Opcode <= SelectionDAGISel::OPC_CheckChild7TypeI64) {
+      VT = MVT::i64;
+      ChildNo = Opcode - SelectionDAGISel::OPC_CheckChild0TypeI64;
+    } else {
+      VT = static_cast<MVT::SimpleValueType>(Table[Index++]);
+      ChildNo = Opcode - SelectionDAGISel::OPC_CheckChild0Type;
+    }
+    Result = !::CheckChildType(VT, N, SDISel.TLI,
+                               SDISel.CurDAG->getDataLayout(), ChildNo);
     return Index;
   }
   case SelectionDAGISel::OPC_CheckCondCode:
@@ -3412,15 +3440,48 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
                         << '\n');
       continue;
     }
-    case OPC_CheckChild0Type: case OPC_CheckChild1Type:
-    case OPC_CheckChild2Type: case OPC_CheckChild3Type:
-    case OPC_CheckChild4Type: case OPC_CheckChild5Type:
-    case OPC_CheckChild6Type: case OPC_CheckChild7Type:
-      if (!::CheckChildType(
-              static_cast<MVT::SimpleValueType>(MatcherTable[MatcherIndex++]),
-              N, TLI, CurDAG->getDataLayout(), Opcode - OPC_CheckChild0Type))
+    case OPC_CheckChild0Type:
+    case OPC_CheckChild1Type:
+    case OPC_CheckChild2Type:
+    case OPC_CheckChild3Type:
+    case OPC_CheckChild4Type:
+    case OPC_CheckChild5Type:
+    case OPC_CheckChild6Type:
+    case OPC_CheckChild7Type:
+    case OPC_CheckChild0TypeI32:
+    case OPC_CheckChild1TypeI32:
+    case OPC_CheckChild2TypeI32:
+    case OPC_CheckChild3TypeI32:
+    case OPC_CheckChild4TypeI32:
+    case OPC_CheckChild5TypeI32:
+    case OPC_CheckChild6TypeI32:
+    case OPC_CheckChild7TypeI32:
+    case OPC_CheckChild0TypeI64:
+    case OPC_CheckChild1TypeI64:
+    case OPC_CheckChild2TypeI64:
+    case OPC_CheckChild3TypeI64:
+    case OPC_CheckChild4TypeI64:
+    case OPC_CheckChild5TypeI64:
+    case OPC_CheckChild6TypeI64:
+    case OPC_CheckChild7TypeI64: {
+      MVT::SimpleValueType VT;
+      unsigned ChildNo;
+      if (Opcode >= SelectionDAGISel::OPC_CheckChild0TypeI32 &&
+          Opcode <= SelectionDAGISel::OPC_CheckChild7TypeI32) {
+        VT = MVT::i32;
+        ChildNo = Opcode - SelectionDAGISel::OPC_CheckChild0TypeI32;
+      } else if (Opcode >= SelectionDAGISel::OPC_CheckChild0TypeI64 &&
+                 Opcode <= SelectionDAGISel::OPC_CheckChild7TypeI64) {
+        VT = MVT::i64;
+        ChildNo = Opcode - SelectionDAGISel::OPC_CheckChild0TypeI64;
+      } else {
+        VT = static_cast<MVT::SimpleValueType>(MatcherTable[MatcherIndex++]);
+        ChildNo = Opcode - SelectionDAGISel::OPC_CheckChild0Type;
+      }
+      if (!::CheckChildType(VT, N, TLI, CurDAG->getDataLayout(), ChildNo))
         break;
       continue;
+    }
     case OPC_CheckCondCode:
       if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
       continue;
diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
index 22bf5926966d..5f79e2ad0df2 100644
--- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
@@ -593,11 +593,20 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx,
        << ", " << getEnumName(cast<CheckTypeMatcher>(N)->getType()) << ",\n";
     return 3;
 
-  case Matcher::CheckChildType:
-    OS << "OPC_CheckChild"
-       << cast<CheckChildTypeMatcher>(N)->getChildNo() << "Type, "
-       << getEnumName(cast<CheckChildTypeMatcher>(N)->getType()) << ",\n";
-    return 2;
+ case Matcher::CheckChildType: {
+   MVT::SimpleValueType VT = cast<CheckChildTypeMatcher>(N)->getType();
+   switch (VT) {
+   case MVT::i32:
+   case MVT::i64:
+     OS << "OPC_CheckChild" << cast<CheckChildTypeMatcher>(N)->getChildNo()
+        << "TypeI" << MVT(VT).getScalarSizeInBits() << ",\n";
+     return 1;
+   default:
+     OS << "OPC_CheckChild" << cast<CheckChildTypeMatcher>(N)->getChildNo()
+        << "Type, " << getEnumName(VT) << ",\n";
+     return 2;
+   }
+ }
 
   case Matcher::CheckInteger: {
     OS << "OPC_CheckInteger, ";
-- 
GitLab


From 2d9d9a1a556a5f8845a7a9e19dc52346b825989e Mon Sep 17 00:00:00 2001
From: Orlando Cazalet-Hyams <orlando.hyams@sony.com>
Date: Tue, 12 Dec 2023 09:43:58 +0000
Subject: [PATCH 249/349] [NFC] Change FindDbgDeclareUsers interface to match
 findDbgUsers/values (#73498)

This simplifies an upcoming patch to support the RemoveDIs project (tracking
variable locations without using intrinsics).

Next in this series is #73500.
---
 llvm/include/llvm/IR/DebugInfo.h             |  2 +-
 llvm/lib/IR/DebugInfo.cpp                    | 14 ++++++--------
 llvm/lib/Transforms/Coroutines/CoroFrame.cpp | 12 ++++++++----
 llvm/lib/Transforms/Scalar/SROA.cpp          | 13 ++++++++++---
 llvm/lib/Transforms/Utils/Local.cpp          |  3 ++-
 llvm/lib/Transforms/Utils/MemoryOpRemark.cpp |  5 +++--
 6 files changed, 30 insertions(+), 19 deletions(-)

diff --git a/llvm/include/llvm/IR/DebugInfo.h b/llvm/include/llvm/IR/DebugInfo.h
index 2a581eb5f09d..5ed423bfd1c1 100644
--- a/llvm/include/llvm/IR/DebugInfo.h
+++ b/llvm/include/llvm/IR/DebugInfo.h
@@ -40,7 +40,7 @@ class Module;
 
 /// Finds dbg.declare intrinsics declaring local variables as living in the
 /// memory that 'V' points to.
-TinyPtrVector<DbgDeclareInst *> FindDbgDeclareUses(Value *V);
+void findDbgDeclares(SmallVectorImpl<DbgDeclareInst *> &DbgUsers, Value *V);
 
 /// Finds the llvm.dbg.value intrinsics describing a value.
 void findDbgValues(SmallVectorImpl<DbgValueInst *> &DbgValues,
diff --git a/llvm/lib/IR/DebugInfo.cpp b/llvm/lib/IR/DebugInfo.cpp
index d532aead90be..b3cc9996ace4 100644
--- a/llvm/lib/IR/DebugInfo.cpp
+++ b/llvm/lib/IR/DebugInfo.cpp
@@ -44,25 +44,23 @@ using namespace llvm;
 using namespace llvm::at;
 using namespace llvm::dwarf;
 
-TinyPtrVector<DbgDeclareInst *> llvm::FindDbgDeclareUses(Value *V) {
+void llvm::findDbgDeclares(SmallVectorImpl<DbgDeclareInst *> &DbgUsers,
+                           Value *V) {
   // This function is hot. Check whether the value has any metadata to avoid a
   // DenseMap lookup.
   if (!V->isUsedByMetadata())
-    return {};
+    return;
   auto *L = LocalAsMetadata::getIfExists(V);
   if (!L)
-    return {};
+    return;
   auto *MDV = MetadataAsValue::getIfExists(V->getContext(), L);
   if (!MDV)
-    return {};
+    return;
 
-  TinyPtrVector<DbgDeclareInst *> Declares;
   for (User *U : MDV->users()) {
     if (auto *DDI = dyn_cast<DbgDeclareInst>(U))
-      Declares.push_back(DDI);
+      DbgUsers.push_back(DDI);
   }
-
-  return Declares;
 }
 
 template <typename IntrinsicT>
diff --git a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp
index 1134b20880f1..6b85de15947c 100644
--- a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp
+++ b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp
@@ -963,7 +963,8 @@ static void cacheDIVar(FrameDataInfo &FrameData,
     if (DIVarCache.contains(V))
       continue;
 
-    auto DDIs = FindDbgDeclareUses(V);
+    SmallVector<DbgDeclareInst *, 1> DDIs;
+    findDbgDeclares(DDIs, V);
     auto *I = llvm::find_if(DDIs, [](DbgDeclareInst *DDI) {
       return DDI->getExpression()->getNumElements() == 0;
     });
@@ -1119,7 +1120,8 @@ static void buildFrameDebugInfo(Function &F, coro::Shape &Shape,
   assert(PromiseAlloca &&
          "Coroutine with switch ABI should own Promise alloca");
 
-  TinyPtrVector<DbgDeclareInst *> DIs = FindDbgDeclareUses(PromiseAlloca);
+  SmallVector<DbgDeclareInst *, 1> DIs;
+  findDbgDeclares(DIs, PromiseAlloca);
   if (DIs.empty())
     return;
 
@@ -1840,7 +1842,8 @@ static void insertSpills(const FrameDataInfo &FrameData, coro::Shape &Shape) {
               FrameTy->getElementType(FrameData.getFieldIndex(E.first)), GEP,
               SpillAlignment, E.first->getName() + Twine(".reload"));
 
-        TinyPtrVector<DbgDeclareInst *> DIs = FindDbgDeclareUses(Def);
+        SmallVector<DbgDeclareInst *, 1> DIs;
+        findDbgDeclares(DIs, Def);
         // Try best to find dbg.declare. If the spill is a temp, there may not
         // be a direct dbg.declare. Walk up the load chain to find one from an
         // alias.
@@ -1854,7 +1857,8 @@ static void insertSpills(const FrameDataInfo &FrameData, coro::Shape &Shape) {
             CurDef = LdInst->getPointerOperand();
             if (!isa<AllocaInst, LoadInst>(CurDef))
               break;
-            DIs = FindDbgDeclareUses(CurDef);
+            DIs.clear();
+            findDbgDeclares(DIs, CurDef);
           }
         }
 
diff --git a/llvm/lib/Transforms/Scalar/SROA.cpp b/llvm/lib/Transforms/Scalar/SROA.cpp
index f578762d2b49..9c72cb67e4d6 100644
--- a/llvm/lib/Transforms/Scalar/SROA.cpp
+++ b/llvm/lib/Transforms/Scalar/SROA.cpp
@@ -4940,10 +4940,13 @@ bool SROA::splitAlloca(AllocaInst &AI, AllocaSlices &AS) {
   // Migrate debug information from the old alloca to the new alloca(s)
   // and the individual partitions.
   TinyPtrVector<DbgVariableIntrinsic *> DbgVariables;
-  for (auto *DbgDeclare : FindDbgDeclareUses(&AI))
+  SmallVector<DbgDeclareInst *, 1> DbgDeclares;
+  findDbgDeclares(DbgDeclares, &AI);
+  for (auto *DbgDeclare : DbgDeclares)
     DbgVariables.push_back(DbgDeclare);
   for (auto *DbgAssign : at::getAssignmentMarkers(&AI))
     DbgVariables.push_back(DbgAssign);
+
   for (DbgVariableIntrinsic *DbgVariable : DbgVariables) {
     auto *Expr = DbgVariable->getExpression();
     DIBuilder DIB(*AI.getModule(), /*AllowUnresolved*/ false);
@@ -4997,7 +5000,9 @@ bool SROA::splitAlloca(AllocaInst &AI, AllocaSlices &AS) {
 
       // Remove any existing intrinsics on the new alloca describing
       // the variable fragment.
-      for (DbgDeclareInst *OldDII : FindDbgDeclareUses(Fragment.Alloca)) {
+      SmallVector<DbgDeclareInst *, 1> FragDbgDeclares;
+      findDbgDeclares(FragDbgDeclares, Fragment.Alloca);
+      for (DbgDeclareInst *OldDII : FragDbgDeclares) {
         auto SameVariableFragment = [](const DbgVariableIntrinsic *LHS,
                                        const DbgVariableIntrinsic *RHS) {
           return LHS->getVariable() == RHS->getVariable() &&
@@ -5147,7 +5152,9 @@ bool SROA::deleteDeadInstructions(
     // not be able to find it.
     if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) {
       DeletedAllocas.insert(AI);
-      for (DbgDeclareInst *OldDII : FindDbgDeclareUses(AI))
+      SmallVector<DbgDeclareInst *, 1> DbgDeclares;
+      findDbgDeclares(DbgDeclares, AI);
+      for (DbgDeclareInst *OldDII : DbgDeclares)
         OldDII->eraseFromParent();
     }
 
diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp
index 51f39e0ba0cc..c19a8d103cfc 100644
--- a/llvm/lib/Transforms/Utils/Local.cpp
+++ b/llvm/lib/Transforms/Utils/Local.cpp
@@ -2103,7 +2103,8 @@ void llvm::insertDebugValuesForPHIs(BasicBlock *BB,
 bool llvm::replaceDbgDeclare(Value *Address, Value *NewAddress,
                              DIBuilder &Builder, uint8_t DIExprFlags,
                              int Offset) {
-  auto DbgDeclares = FindDbgDeclareUses(Address);
+  SmallVector<DbgDeclareInst *, 1> DbgDeclares;
+  findDbgDeclares(DbgDeclares, Address);
   for (DbgVariableIntrinsic *DII : DbgDeclares) {
     const DebugLoc &Loc = DII->getDebugLoc();
     auto *DIVar = DII->getVariable();
diff --git a/llvm/lib/Transforms/Utils/MemoryOpRemark.cpp b/llvm/lib/Transforms/Utils/MemoryOpRemark.cpp
index 531b0a624daf..5c3776683d5d 100644
--- a/llvm/lib/Transforms/Utils/MemoryOpRemark.cpp
+++ b/llvm/lib/Transforms/Utils/MemoryOpRemark.cpp
@@ -321,8 +321,9 @@ void MemoryOpRemark::visitVariable(const Value *V,
   bool FoundDI = false;
   // Try to get an llvm.dbg.declare, which has a DILocalVariable giving us the
   // real debug info name and size of the variable.
-  for (const DbgVariableIntrinsic *DVI :
-       FindDbgDeclareUses(const_cast<Value *>(V))) {
+  SmallVector<DbgDeclareInst *, 1> DbgDeclares;
+  findDbgDeclares(DbgDeclares, const_cast<Value *>(V));
+  for (const DbgVariableIntrinsic *DVI : DbgDeclares) {
     if (DILocalVariable *DILV = DVI->getVariable()) {
       std::optional<uint64_t> DISize = getSizeInBytes(DILV->getSizeInBits());
       VariableInfo Var{DILV->getName(), DISize};
-- 
GitLab


From e3f4fa98349b85dbd7845a505a98bd331e5d2897 Mon Sep 17 00:00:00 2001
From: Timm Baeder <tbaeder@redhat.com>
Date: Tue, 12 Dec 2023 10:44:43 +0100
Subject: [PATCH 250/349] [clang][Interp] Implement inc/dec for IntegralAP
 (#69597)

Implement `++` and `--` for arbitrary-bitwidth values.
---
 clang/lib/AST/Interp/IntegralAP.h | 12 ++----
 clang/test/AST/Interp/intap.cpp   | 66 ++++++++++++++++++++++++++++++-
 2 files changed, 68 insertions(+), 10 deletions(-)

diff --git a/clang/lib/AST/Interp/IntegralAP.h b/clang/lib/AST/Interp/IntegralAP.h
index 9019f32e6cef..d5f46409d231 100644
--- a/clang/lib/AST/Interp/IntegralAP.h
+++ b/clang/lib/AST/Interp/IntegralAP.h
@@ -182,17 +182,13 @@ public:
   }
 
   static bool increment(IntegralAP A, IntegralAP *R) {
-    // FIXME: Implement.
-    assert(false);
-    *R = IntegralAP(A.V - 1);
-    return false;
+    IntegralAP<Signed> One(1, A.bitWidth());
+    return add(A, One, A.bitWidth() + 1, R);
   }
 
   static bool decrement(IntegralAP A, IntegralAP *R) {
-    // FIXME: Implement.
-    assert(false);
-    *R = IntegralAP(A.V - 1);
-    return false;
+    IntegralAP<Signed> One(1, A.bitWidth());
+    return sub(A, One, A.bitWidth() + 1, R);
   }
 
   static bool add(IntegralAP A, IntegralAP B, unsigned OpBits, IntegralAP *R) {
diff --git a/clang/test/AST/Interp/intap.cpp b/clang/test/AST/Interp/intap.cpp
index c93ec3312966..b99422dc8f93 100644
--- a/clang/test/AST/Interp/intap.cpp
+++ b/clang/test/AST/Interp/intap.cpp
@@ -57,9 +57,25 @@ namespace APCast {
 }
 
 #ifdef __SIZEOF_INT128__
+typedef __int128 int128_t;
+typedef unsigned __int128 uint128_t;
+static const __uint128_t UINT128_MAX =__uint128_t(__int128_t(-1L));
+static_assert(UINT128_MAX == -1, "");
+static_assert(UINT128_MAX == 1, ""); // expected-error {{static assertion failed}} \
+                                     // expected-note {{'340282366920938463463374607431768211455 == 1'}} \
+                                     // ref-error {{static assertion failed}} \
+                                     // ref-note {{'340282366920938463463374607431768211455 == 1'}}
+
+static const __int128_t INT128_MAX = UINT128_MAX >> (__int128_t)1;
+static_assert(INT128_MAX != 0, "");
+static_assert(INT128_MAX == 0, ""); // expected-error {{failed}} \
+                                    // expected-note {{evaluates to '170141183460469231731687303715884105727 == 0'}} \
+                                    // ref-error {{failed}} \
+                                    // ref-note {{evaluates to '170141183460469231731687303715884105727 == 0'}}
+static const __int128_t INT128_MIN = -INT128_MAX - 1;
+
 namespace i128 {
-  typedef __int128 int128_t;
-  typedef unsigned __int128 uint128_t;
+
   constexpr int128_t I128_1 = 12;
   static_assert(I128_1 == 12, "");
   static_assert(I128_1 != 10, "");
@@ -200,4 +216,50 @@ namespace BitOps {
   static_assert((Max ^ UZero) == Max, "");
 }
 
+namespace IncDec {
+#if __cplusplus >= 201402L
+  constexpr int128_t maxPlus1(bool Pre) {
+    int128_t a = INT128_MAX;
+
+    if (Pre)
+      ++a; // ref-note {{value 170141183460469231731687303715884105728 is outside the range}} \
+           // expected-note {{value 170141183460469231731687303715884105728 is outside the range}}
+    else
+      a++; // ref-note {{value 170141183460469231731687303715884105728 is outside the range}} \
+           // expected-note {{value 170141183460469231731687303715884105728 is outside the range}}
+    return a;
+  }
+  static_assert(maxPlus1(true) == 0, ""); // ref-error {{not an integral constant expression}} \
+                                          // ref-note {{in call to}} \
+                                          // expected-error {{not an integral constant expression}} \
+                                          // expected-note {{in call to}}
+  static_assert(maxPlus1(false) == 0, ""); // ref-error {{not an integral constant expression}} \
+                                           // ref-note {{in call to}} \
+                                           // expected-error {{not an integral constant expression}} \
+                                           // expected-note {{in call to}}
+
+  constexpr int128_t inc1(bool Pre) {
+    int128_t A = 0;
+    if (Pre)
+      ++A;
+    else
+      A++;
+    return A;
+  }
+  static_assert(inc1(true) == 1, "");
+  static_assert(inc1(false) == 1, "");
+
+  constexpr int128_t dec1(bool Pre) {
+    int128_t A = 2;
+    if (Pre)
+      --A;
+    else
+      A--;
+    return A;
+  }
+  static_assert(dec1(true) == 1, "");
+  static_assert(dec1(false) == 1, "");
+#endif
+}
+
 #endif
-- 
GitLab


From 0d5f1cc4d0e339d433370b7658a065edb84daa01 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp@bytedance.com>
Date: Tue, 12 Dec 2023 17:45:32 +0800
Subject: [PATCH 251/349] [SelectionDAG] Add space-optimized forms of
 OPC_EmitNode/OPC_MorphNodeTo (#73502)

If there is only one bit set in EmitNodeInfo, then we can encode it
implicitly to save one byte.

Overall this reduces the llc binary size with all in-tree targets by
about 168K.
---
 llvm/include/llvm/CodeGen/SelectionDAGISel.h  | 20 ++++++
 .../CodeGen/SelectionDAG/SelectionDAGISel.cpp | 70 +++++++++++++++++--
 llvm/test/TableGen/DAGDefaultOps.td           | 10 +--
 .../TableGen/dag-isel-regclass-emit-enum.td   |  6 +-
 llvm/test/TableGen/dag-isel-res-order.td      |  2 +-
 llvm/utils/TableGen/DAGISelMatcherEmitter.cpp | 53 ++++++++++----
 6 files changed, 134 insertions(+), 27 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index 9b3a2352fb1a..233e94c4e743 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -244,11 +244,31 @@ public:
     OPC_EmitNode0,
     OPC_EmitNode1,
     OPC_EmitNode2,
+    // Space-optimized forms that implicitly encode EmitNodeInfo.
+    OPC_EmitNode0None,
+    OPC_EmitNode1None,
+    OPC_EmitNode2None,
+    OPC_EmitNode0Chain,
+    OPC_EmitNode1Chain,
+    OPC_EmitNode2Chain,
     OPC_MorphNodeTo,
     // Space-optimized forms that implicitly encode number of result VTs.
     OPC_MorphNodeTo0,
     OPC_MorphNodeTo1,
     OPC_MorphNodeTo2,
+    // Space-optimized forms that implicitly encode EmitNodeInfo.
+    OPC_MorphNodeTo0None,
+    OPC_MorphNodeTo1None,
+    OPC_MorphNodeTo2None,
+    OPC_MorphNodeTo0Chain,
+    OPC_MorphNodeTo1Chain,
+    OPC_MorphNodeTo2Chain,
+    OPC_MorphNodeTo0GlueInput,
+    OPC_MorphNodeTo1GlueInput,
+    OPC_MorphNodeTo2GlueInput,
+    OPC_MorphNodeTo0GlueOutput,
+    OPC_MorphNodeTo1GlueOutput,
+    OPC_MorphNodeTo2GlueOutput,
     OPC_CompleteMatch,
     // Contains offset in table for pattern being selected
     OPC_Coverage
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index cba25b8d7c02..b43847db32aa 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -3757,20 +3757,77 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
       continue;
     }
 
-    case OPC_EmitNode:     case OPC_MorphNodeTo:
-    case OPC_EmitNode0:    case OPC_EmitNode1:    case OPC_EmitNode2:
-    case OPC_MorphNodeTo0: case OPC_MorphNodeTo1: case OPC_MorphNodeTo2: {
+    case OPC_EmitNode:
+    case OPC_EmitNode0:
+    case OPC_EmitNode1:
+    case OPC_EmitNode2:
+    case OPC_EmitNode0None:
+    case OPC_EmitNode1None:
+    case OPC_EmitNode2None:
+    case OPC_EmitNode0Chain:
+    case OPC_EmitNode1Chain:
+    case OPC_EmitNode2Chain:
+    case OPC_MorphNodeTo:
+    case OPC_MorphNodeTo0:
+    case OPC_MorphNodeTo1:
+    case OPC_MorphNodeTo2:
+    case OPC_MorphNodeTo0None:
+    case OPC_MorphNodeTo1None:
+    case OPC_MorphNodeTo2None:
+    case OPC_MorphNodeTo0Chain:
+    case OPC_MorphNodeTo1Chain:
+    case OPC_MorphNodeTo2Chain:
+    case OPC_MorphNodeTo0GlueInput:
+    case OPC_MorphNodeTo1GlueInput:
+    case OPC_MorphNodeTo2GlueInput:
+    case OPC_MorphNodeTo0GlueOutput:
+    case OPC_MorphNodeTo1GlueOutput:
+    case OPC_MorphNodeTo2GlueOutput: {
       uint16_t TargetOpc = MatcherTable[MatcherIndex++];
       TargetOpc |= static_cast<uint16_t>(MatcherTable[MatcherIndex++]) << 8;
-      unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
+      unsigned EmitNodeInfo;
+      if (Opcode >= OPC_EmitNode0None && Opcode <= OPC_EmitNode2Chain) {
+        if (Opcode >= OPC_EmitNode0Chain && Opcode <= OPC_EmitNode2Chain)
+          EmitNodeInfo = OPFL_Chain;
+        else
+          EmitNodeInfo = OPFL_None;
+      } else if (Opcode >= OPC_MorphNodeTo0None &&
+                 Opcode <= OPC_MorphNodeTo2GlueOutput) {
+        if (Opcode >= OPC_MorphNodeTo0Chain && Opcode <= OPC_MorphNodeTo2Chain)
+          EmitNodeInfo = OPFL_Chain;
+        else if (Opcode >= OPC_MorphNodeTo0GlueInput &&
+                 Opcode <= OPC_MorphNodeTo2GlueInput)
+          EmitNodeInfo = OPFL_GlueInput;
+        else if (Opcode >= OPC_MorphNodeTo0GlueOutput &&
+                 Opcode <= OPC_MorphNodeTo2GlueOutput)
+          EmitNodeInfo = OPFL_GlueOutput;
+        else
+          EmitNodeInfo = OPFL_None;
+      } else
+        EmitNodeInfo = MatcherTable[MatcherIndex++];
       // Get the result VT list.
       unsigned NumVTs;
       // If this is one of the compressed forms, get the number of VTs based
       // on the Opcode. Otherwise read the next byte from the table.
       if (Opcode >= OPC_MorphNodeTo0 && Opcode <= OPC_MorphNodeTo2)
         NumVTs = Opcode - OPC_MorphNodeTo0;
+      else if (Opcode >= OPC_MorphNodeTo0None && Opcode <= OPC_MorphNodeTo2None)
+        NumVTs = Opcode - OPC_MorphNodeTo0None;
+      else if (Opcode >= OPC_MorphNodeTo0Chain &&
+               Opcode <= OPC_MorphNodeTo2Chain)
+        NumVTs = Opcode - OPC_MorphNodeTo0Chain;
+      else if (Opcode >= OPC_MorphNodeTo0GlueInput &&
+               Opcode <= OPC_MorphNodeTo2GlueInput)
+        NumVTs = Opcode - OPC_MorphNodeTo0GlueInput;
+      else if (Opcode >= OPC_MorphNodeTo0GlueOutput &&
+               Opcode <= OPC_MorphNodeTo2GlueOutput)
+        NumVTs = Opcode - OPC_MorphNodeTo0GlueOutput;
       else if (Opcode >= OPC_EmitNode0 && Opcode <= OPC_EmitNode2)
         NumVTs = Opcode - OPC_EmitNode0;
+      else if (Opcode >= OPC_EmitNode0None && Opcode <= OPC_EmitNode2None)
+        NumVTs = Opcode - OPC_EmitNode0None;
+      else if (Opcode >= OPC_EmitNode0Chain && Opcode <= OPC_EmitNode2Chain)
+        NumVTs = Opcode - OPC_EmitNode0Chain;
       else
         NumVTs = MatcherTable[MatcherIndex++];
       SmallVector<EVT, 4> VTs;
@@ -3843,8 +3900,9 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
 
       // Create the node.
       MachineSDNode *Res = nullptr;
-      bool IsMorphNodeTo = Opcode == OPC_MorphNodeTo ||
-                     (Opcode >= OPC_MorphNodeTo0 && Opcode <= OPC_MorphNodeTo2);
+      bool IsMorphNodeTo =
+          Opcode == OPC_MorphNodeTo ||
+          (Opcode >= OPC_MorphNodeTo0 && Opcode <= OPC_MorphNodeTo2GlueOutput);
       if (!IsMorphNodeTo) {
         // If this is a normal EmitNode command, just create the new node and
         // add the results to the RecordedNodes list.
diff --git a/llvm/test/TableGen/DAGDefaultOps.td b/llvm/test/TableGen/DAGDefaultOps.td
index 010ee205e6ff..70c8413f2c05 100644
--- a/llvm/test/TableGen/DAGDefaultOps.td
+++ b/llvm/test/TableGen/DAGDefaultOps.td
@@ -77,20 +77,20 @@ def MulIRRPat : Pat<(mul i32:$x, i32:$y), (MulIRR Reg:$x, Reg:$y)>;
 // ADD-NEXT: OPC_RecordChild0
 // ADD-NEXT: OPC_RecordChild1
 // ADD-NEXT: OPC_EmitInteger32, 0
-// ADD-NEXT: OPC_MorphNodeTo1, TARGET_VAL(::AddRRI)
+// ADD-NEXT: OPC_MorphNodeTo1None, TARGET_VAL(::AddRRI)
 
 // ADDINT: SwitchOpcode{{.*}}TARGET_VAL(ISD::INTRINSIC_WO_CHAIN)
 // ADDINT-NEXT: OPC_CheckChild0Integer
 // ADDINT-NEXT: OPC_RecordChild1
 // ADDINT-NEXT: OPC_RecordChild2
 // ADDINT-NEXT: OPC_EmitInteger32, 2
-// ADDINT-NEXT: OPC_MorphNodeTo1, TARGET_VAL(::AddRRI)
+// ADDINT-NEXT: OPC_MorphNodeTo1None, TARGET_VAL(::AddRRI)
 
 // SUB: SwitchOpcode{{.*}}TARGET_VAL(ISD::SUB)
 // SUB-NEXT: OPC_RecordChild0
 // SUB-NEXT: OPC_RecordChild1
 // SUB-NEXT: OPC_EmitInteger32, 0
-// SUB-NEXT: OPC_MorphNodeTo1, TARGET_VAL(::SubRRI)
+// SUB-NEXT: OPC_MorphNodeTo1None, TARGET_VAL(::SubRRI)
 
 // MULINT: SwitchOpcode{{.*}}TARGET_VAL(ISD::INTRINSIC_W_CHAIN)
 // MULINT-NEXT: OPC_RecordNode
@@ -99,10 +99,10 @@ def MulIRRPat : Pat<(mul i32:$x, i32:$y), (MulIRR Reg:$x, Reg:$y)>;
 // MULINT-NEXT: OPC_RecordChild3
 // MULINT-NEXT: OPC_RecordChild4
 // MULINT-NEXT: OPC_EmitMergeInputChains
-// MULINT-NEXT: OPC_MorphNodeTo1, TARGET_VAL(::MulRRI)
+// MULINT-NEXT: OPC_MorphNodeTo1Chain, TARGET_VAL(::MulRRI)
 
 // MUL: SwitchOpcode{{.*}}TARGET_VAL(ISD::MUL)
 // MUL-NEXT: OPC_EmitInteger32, 0
 // MUL-NEXT: OPC_RecordChild0
 // MUL-NEXT: OPC_RecordChild1
-// MUL-NEXT: OPC_MorphNodeTo1, TARGET_VAL(::MulRRI)
+// MUL-NEXT: OPC_MorphNodeTo1Chain, TARGET_VAL(::MulRRI)
diff --git a/llvm/test/TableGen/dag-isel-regclass-emit-enum.td b/llvm/test/TableGen/dag-isel-regclass-emit-enum.td
index 27e214f1641d..ba60df2bbcf6 100644
--- a/llvm/test/TableGen/dag-isel-regclass-emit-enum.td
+++ b/llvm/test/TableGen/dag-isel-regclass-emit-enum.td
@@ -23,17 +23,17 @@ def GPRAbove127 : RegisterClass<"TestTarget", [i32], 32,
 
 // CHECK:      OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
 // CHECK-NEXT: OPC_RecordChild0, // #0 = $src
-// CHECK-NEXT: OPC_Scope, 13, /*->19*/ // 2 children in Scope
+// CHECK-NEXT: OPC_Scope, 12, /*->18*/ // 2 children in Scope
 // CHECK-NEXT: OPC_CheckChild1Integer, 0,
 // CHECK-NEXT: OPC_EmitInteger32, 0|128,2/*256*/,
-// CHECK-NEXT: OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+// CHECK-NEXT: OPC_MorphNodeTo1None, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS),
 // CHECK-NEXT:     MVT::i32, 2/*#Ops*/, 1, 0,
 def : Pat<(i32 (add i32:$src, (i32 0))),
           (COPY_TO_REGCLASS GPRAbove127, GPR0:$src)>;
 
 // CHECK:      OPC_CheckChild1Integer, 2,
 // CHECK-NEXT: OPC_EmitStringInteger32, TestNamespace::GPR127RegClassID,
-// CHECK-NEXT: OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+// CHECK-NEXT: OPC_MorphNodeTo1None, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS),
 // CHECK-NEXT:     MVT::i32, 2/*#Ops*/, 1, 0,
 def : Pat<(i32 (add i32:$src, (i32 1))),
           (COPY_TO_REGCLASS GPR127, GPR0:$src)>;
diff --git a/llvm/test/TableGen/dag-isel-res-order.td b/llvm/test/TableGen/dag-isel-res-order.td
index 4da6b6d6867c..6937dd8c6b80 100644
--- a/llvm/test/TableGen/dag-isel-res-order.td
+++ b/llvm/test/TableGen/dag-isel-res-order.td
@@ -12,7 +12,7 @@ def REG : Register<"REG">;
 def GPR : RegisterClass<"TestTarget", [i32], 32, (add REG)>;
 
 // CHECK-LABEL: OPC_CheckOpcode, TARGET_VAL(ISD::UDIVREM)
-// CHECK: OPC_EmitNode2, TARGET_VAL(::INSTR)
+// CHECK: OPC_EmitNode2None, TARGET_VAL(::INSTR)
 // CHECK: Results = #2 #3
 // CHECK: OPC_CompleteMatch, 2, 3, 2
 def INSTR : Instruction {
diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
index 5f79e2ad0df2..2ba57c30046e 100644
--- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
@@ -824,21 +824,50 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx,
       }
     }
     const EmitNodeMatcherCommon *EN = cast<EmitNodeMatcherCommon>(N);
-    OS << (isa<EmitNodeMatcher>(EN) ? "OPC_EmitNode" : "OPC_MorphNodeTo");
+    bool IsEmitNode = isa<EmitNodeMatcher>(EN);
+    OS << (IsEmitNode ? "OPC_EmitNode" : "OPC_MorphNodeTo");
     bool CompressVTs = EN->getNumVTs() < 3;
-    if (CompressVTs)
+    bool CompressNodeInfo = false;
+    if (CompressVTs) {
       OS << EN->getNumVTs();
+      if (!EN->hasChain() && !EN->hasInGlue() && !EN->hasOutGlue() &&
+          !EN->hasMemRefs() && EN->getNumFixedArityOperands() == -1) {
+        CompressNodeInfo = true;
+        OS << "None";
+      } else if (EN->hasChain() && !EN->hasInGlue() && !EN->hasOutGlue() &&
+                 !EN->hasMemRefs() && EN->getNumFixedArityOperands() == -1) {
+        CompressNodeInfo = true;
+        OS << "Chain";
+      } else if (!IsEmitNode && !EN->hasChain() && EN->hasInGlue() &&
+                 !EN->hasOutGlue() && !EN->hasMemRefs() &&
+                 EN->getNumFixedArityOperands() == -1) {
+        CompressNodeInfo = true;
+        OS << "GlueInput";
+      } else if (!IsEmitNode && !EN->hasChain() && !EN->hasInGlue() &&
+                 EN->hasOutGlue() && !EN->hasMemRefs() &&
+                 EN->getNumFixedArityOperands() == -1) {
+        CompressNodeInfo = true;
+        OS << "GlueOutput";
+      }
+    }
 
     const CodeGenInstruction &CGI = EN->getInstruction();
     OS << ", TARGET_VAL(" << CGI.Namespace << "::" << CGI.TheDef->getName()
-       << "), 0";
-
-    if (EN->hasChain())   OS << "|OPFL_Chain";
-    if (EN->hasInGlue())  OS << "|OPFL_GlueInput";
-    if (EN->hasOutGlue()) OS << "|OPFL_GlueOutput";
-    if (EN->hasMemRefs()) OS << "|OPFL_MemRefs";
-    if (EN->getNumFixedArityOperands() != -1)
-      OS << "|OPFL_Variadic" << EN->getNumFixedArityOperands();
+       << ")";
+
+    if (!CompressNodeInfo) {
+      OS << ", 0";
+      if (EN->hasChain())
+        OS << "|OPFL_Chain";
+      if (EN->hasInGlue())
+        OS << "|OPFL_GlueInput";
+      if (EN->hasOutGlue())
+        OS << "|OPFL_GlueOutput";
+      if (EN->hasMemRefs())
+        OS << "|OPFL_MemRefs";
+      if (EN->getNumFixedArityOperands() != -1)
+        OS << "|OPFL_Variadic" << EN->getNumFixedArityOperands();
+    }
     OS << ",\n";
 
     OS.indent(FullIndexWidth + Indent+4);
@@ -881,8 +910,8 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx,
     } else
       OS << '\n';
 
-    return 5 + !CompressVTs + EN->getNumVTs() + NumOperandBytes +
-           NumCoveredBytes;
+    return 4 + !CompressVTs + !CompressNodeInfo + EN->getNumVTs() +
+           NumOperandBytes + NumCoveredBytes;
   }
   case Matcher::CompleteMatch: {
     const CompleteMatchMatcher *CM = cast<CompleteMatchMatcher>(N);
-- 
GitLab


From 43e6aec145262afe53bf56372d363d1fbc4f6125 Mon Sep 17 00:00:00 2001
From: Timm Baeder <tbaeder@redhat.com>
Date: Tue, 12 Dec 2023 10:48:00 +0100
Subject: [PATCH 252/349] [clang][Interp] Implement
 __builtin_rotate{right,left} (#72984)

---
 clang/lib/AST/Interp/InterpBuiltin.cpp      | 49 +++++++++++++++++++++
 clang/test/AST/Interp/builtin-functions.cpp | 14 ++++++
 2 files changed, 63 insertions(+)

diff --git a/clang/lib/AST/Interp/InterpBuiltin.cpp b/clang/lib/AST/Interp/InterpBuiltin.cpp
index 4384ace6b6be..deba38e4e9dd 100644
--- a/clang/lib/AST/Interp/InterpBuiltin.cpp
+++ b/clang/lib/AST/Interp/InterpBuiltin.cpp
@@ -579,6 +579,29 @@ static bool interp__builtin_expect(InterpState &S, CodePtr OpPC,
   return true;
 }
 
+/// rotateleft(value, amount)
+static bool interp__builtin_rotate(InterpState &S, CodePtr OpPC,
+                                   const InterpFrame *Frame,
+                                   const Function *Func, const CallExpr *Call,
+                                   bool Right) {
+  PrimType ArgT = *S.getContext().classify(Call->getArg(0)->getType());
+  assert(ArgT == *S.getContext().classify(Call->getArg(1)->getType()));
+
+  APSInt Amount = peekToAPSInt(S.Stk, ArgT);
+  APSInt Value = peekToAPSInt(S.Stk, ArgT, align(primSize(ArgT)) * 2);
+
+  APSInt Result;
+  if (Right)
+    Result = APSInt(Value.rotr(Amount.urem(Value.getBitWidth())),
+                    /*IsUnsigned=*/true);
+  else // Left.
+    Result = APSInt(Value.rotl(Amount.urem(Value.getBitWidth())),
+                    /*IsUnsigned=*/true);
+
+  pushAPSInt(S, Result);
+  return true;
+}
+
 bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const Function *F,
                       const CallExpr *Call) {
   InterpFrame *Frame = S.Current;
@@ -754,6 +777,32 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const Function *F,
       return false;
     break;
 
+  case Builtin::BI__builtin_rotateleft8:
+  case Builtin::BI__builtin_rotateleft16:
+  case Builtin::BI__builtin_rotateleft32:
+  case Builtin::BI__builtin_rotateleft64:
+  case Builtin::BI_rotl8: // Microsoft variants of rotate left
+  case Builtin::BI_rotl16:
+  case Builtin::BI_rotl:
+  case Builtin::BI_lrotl:
+  case Builtin::BI_rotl64:
+    if (!interp__builtin_rotate(S, OpPC, Frame, F, Call, /*Right=*/false))
+      return false;
+    break;
+
+  case Builtin::BI__builtin_rotateright8:
+  case Builtin::BI__builtin_rotateright16:
+  case Builtin::BI__builtin_rotateright32:
+  case Builtin::BI__builtin_rotateright64:
+  case Builtin::BI_rotr8: // Microsoft variants of rotate right
+  case Builtin::BI_rotr16:
+  case Builtin::BI_rotr:
+  case Builtin::BI_lrotr:
+  case Builtin::BI_rotr64:
+    if (!interp__builtin_rotate(S, OpPC, Frame, F, Call, /*Right=*/true))
+      return false;
+    break;
+
   default:
     return false;
   }
diff --git a/clang/test/AST/Interp/builtin-functions.cpp b/clang/test/AST/Interp/builtin-functions.cpp
index 35a1f9a75092..62fe9b081c78 100644
--- a/clang/test/AST/Interp/builtin-functions.cpp
+++ b/clang/test/AST/Interp/builtin-functions.cpp
@@ -339,3 +339,17 @@ namespace expect {
   static_assert(__builtin_expect(a(),1) == 12, "");
   static_assert(__builtin_expect_with_probability(a(), 1, 1.0) == 12, "");
 }
+
+namespace rotateleft {
+  char rotateleft1[__builtin_rotateleft8(0x01, 5) == 0x20 ? 1 : -1];
+  char rotateleft2[__builtin_rotateleft16(0x3210, 11) == 0x8190 ? 1 : -1];
+  char rotateleft3[__builtin_rotateleft32(0x76543210, 22) == 0x841D950C ? 1 : -1];
+  char rotateleft4[__builtin_rotateleft64(0xFEDCBA9876543210ULL, 55) == 0x87F6E5D4C3B2A19ULL ? 1 : -1];
+}
+
+namespace rotateright {
+  char rotateright1[__builtin_rotateright8(0x01, 5) == 0x08 ? 1 : -1];
+  char rotateright2[__builtin_rotateright16(0x3210, 11) == 0x4206 ? 1 : -1];
+  char rotateright3[__builtin_rotateright32(0x76543210, 22) == 0x50C841D9 ? 1 : -1];
+  char rotateright4[__builtin_rotateright64(0xFEDCBA9876543210ULL, 55) == 0xB97530ECA86421FDULL ? 1 : -1];
+}
-- 
GitLab


From 714417455da34855290c3b575b8daabb78340e45 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp@bytedance.com>
Date: Tue, 12 Dec 2023 17:48:45 +0800
Subject: [PATCH 253/349] [SelectionDAG] Add OPC_MoveSibling (#73643)

There are a lot of operations to move current node to parent and
then move to another child.

So `OPC_MoveSibling` and its space-optimized forms are added to do
this "move to sibling" operations.

These new operations will be generated when optimizing matcher in
`ContractNodes`. Currently `MoveParent+MoveChild` will be optimized
to `MoveSibling` and sequences `MoveParent+RecordChild+MoveChild`
will be transformed into `MoveSibling+RecordNode`.

Overall this reduces the llc binary size with all in-tree targets by
about 30K.
---
 llvm/include/llvm/CodeGen/SelectionDAGISel.h  |  9 +++
 .../CodeGen/SelectionDAG/SelectionDAGISel.cpp | 23 ++++++++
 llvm/utils/TableGen/DAGISelMatcher.cpp        |  4 ++
 llvm/utils/TableGen/DAGISelMatcher.h          | 59 +++++++++++++------
 llvm/utils/TableGen/DAGISelMatcherEmitter.cpp | 13 ++++
 llvm/utils/TableGen/DAGISelMatcherOpt.cpp     | 24 ++++++++
 6 files changed, 113 insertions(+), 19 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index 233e94c4e743..c604e7eaa088 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -143,6 +143,15 @@ public:
     OPC_MoveChild5,
     OPC_MoveChild6,
     OPC_MoveChild7,
+    OPC_MoveSibling,
+    OPC_MoveSibling0,
+    OPC_MoveSibling1,
+    OPC_MoveSibling2,
+    OPC_MoveSibling3,
+    OPC_MoveSibling4,
+    OPC_MoveSibling5,
+    OPC_MoveSibling6,
+    OPC_MoveSibling7,
     OPC_MoveParent,
     OPC_CheckSame,
     OPC_CheckChild0Same,
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index b43847db32aa..dd28ec09d0e2 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -3285,6 +3285,29 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
       continue;
     }
 
+    case OPC_MoveSibling:
+    case OPC_MoveSibling0:
+    case OPC_MoveSibling1:
+    case OPC_MoveSibling2:
+    case OPC_MoveSibling3:
+    case OPC_MoveSibling4:
+    case OPC_MoveSibling5:
+    case OPC_MoveSibling6:
+    case OPC_MoveSibling7: {
+      // Pop the current node off the NodeStack.
+      NodeStack.pop_back();
+      assert(!NodeStack.empty() && "Node stack imbalance!");
+      N = NodeStack.back();
+
+      unsigned SiblingNo = Opcode == OPC_MoveSibling
+                               ? MatcherTable[MatcherIndex++]
+                               : Opcode - OPC_MoveSibling0;
+      if (SiblingNo >= N.getNumOperands())
+        break; // Match fails if out of range sibling #.
+      N = N.getOperand(SiblingNo);
+      NodeStack.push_back(N);
+      continue;
+    }
     case OPC_MoveParent:
       // Pop the current node off the NodeStack.
       NodeStack.pop_back();
diff --git a/llvm/utils/TableGen/DAGISelMatcher.cpp b/llvm/utils/TableGen/DAGISelMatcher.cpp
index 0609f006763b..1a5c728fafd9 100644
--- a/llvm/utils/TableGen/DAGISelMatcher.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcher.cpp
@@ -145,6 +145,10 @@ void MoveChildMatcher::printImpl(raw_ostream &OS, unsigned indent) const {
   OS.indent(indent) << "MoveChild " << ChildNo << '\n';
 }
 
+void MoveSiblingMatcher::printImpl(raw_ostream &OS, unsigned Indent) const {
+  OS.indent(Indent) << "MoveSibling " << SiblingNo << '\n';
+}
+
 void MoveParentMatcher::printImpl(raw_ostream &OS, unsigned indent) const {
   OS.indent(indent) << "MoveParent\n";
 }
diff --git a/llvm/utils/TableGen/DAGISelMatcher.h b/llvm/utils/TableGen/DAGISelMatcher.h
index e3cf847edd12..e69f8fa9c5d3 100644
--- a/llvm/utils/TableGen/DAGISelMatcher.h
+++ b/llvm/utils/TableGen/DAGISelMatcher.h
@@ -52,28 +52,29 @@ class Matcher {
 public:
   enum KindTy {
     // Matcher state manipulation.
-    Scope,                // Push a checking scope.
-    RecordNode,           // Record the current node.
-    RecordChild,          // Record a child of the current node.
-    RecordMemRef,         // Record the memref in the current node.
-    CaptureGlueInput,     // If the current node has an input glue, save it.
-    MoveChild,            // Move current node to specified child.
-    MoveParent,           // Move current node to parent.
+    Scope,            // Push a checking scope.
+    RecordNode,       // Record the current node.
+    RecordChild,      // Record a child of the current node.
+    RecordMemRef,     // Record the memref in the current node.
+    CaptureGlueInput, // If the current node has an input glue, save it.
+    MoveChild,        // Move current node to specified child.
+    MoveSibling,      // Move current node to specified sibling.
+    MoveParent,       // Move current node to parent.
 
     // Predicate checking.
-    CheckSame,            // Fail if not same as prev match.
-    CheckChildSame,       // Fail if child not same as prev match.
+    CheckSame,      // Fail if not same as prev match.
+    CheckChildSame, // Fail if child not same as prev match.
     CheckPatternPredicate,
-    CheckPredicate,       // Fail if node predicate fails.
-    CheckOpcode,          // Fail if not opcode.
-    SwitchOpcode,         // Dispatch based on opcode.
-    CheckType,            // Fail if not correct type.
-    SwitchType,           // Dispatch based on type.
-    CheckChildType,       // Fail if child has wrong type.
-    CheckInteger,         // Fail if wrong val.
-    CheckChildInteger,    // Fail if child is wrong val.
-    CheckCondCode,        // Fail if not condcode.
-    CheckChild2CondCode,  // Fail if child is wrong condcode.
+    CheckPredicate,      // Fail if node predicate fails.
+    CheckOpcode,         // Fail if not opcode.
+    SwitchOpcode,        // Dispatch based on opcode.
+    CheckType,           // Fail if not correct type.
+    SwitchType,          // Dispatch based on type.
+    CheckChildType,      // Fail if child has wrong type.
+    CheckInteger,        // Fail if wrong val.
+    CheckChildInteger,   // Fail if child is wrong val.
+    CheckCondCode,       // Fail if not condcode.
+    CheckChild2CondCode, // Fail if child is wrong condcode.
     CheckValueType,
     CheckComplexPat,
     CheckAndImm,
@@ -342,6 +343,26 @@ private:
   }
 };
 
+/// MoveSiblingMatcher - This tells the interpreter to move into the
+/// specified sibling node.
+class MoveSiblingMatcher : public Matcher {
+  unsigned SiblingNo;
+
+public:
+  MoveSiblingMatcher(unsigned SiblingNo)
+      : Matcher(MoveSibling), SiblingNo(SiblingNo) {}
+
+  unsigned getSiblingNo() const { return SiblingNo; }
+
+  static bool classof(const Matcher *N) { return N->getKind() == MoveSibling; }
+
+private:
+  void printImpl(raw_ostream &OS, unsigned Indent) const override;
+  bool isEqualImpl(const Matcher *M) const override {
+    return cast<MoveSiblingMatcher>(M)->getSiblingNo() == getSiblingNo();
+  }
+};
+
 /// MoveParentMatcher - This tells the interpreter to move to the parent
 /// of the current node.
 class MoveParentMatcher : public Matcher {
diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
index 2ba57c30046e..5f96f11279f2 100644
--- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
@@ -456,6 +456,17 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx,
     return (MCM->getChildNo() >= 8) ? 2 : 1;
   }
 
+  case Matcher::MoveSibling: {
+    const auto *MSM = cast<MoveSiblingMatcher>(N);
+
+    OS << "OPC_MoveSibling";
+    // Handle the specialized forms.
+    if (MSM->getSiblingNo() >= 8)
+      OS << ", ";
+    OS << MSM->getSiblingNo() << ",\n";
+    return (MSM->getSiblingNo() >= 8) ? 2 : 1;
+  }
+
   case Matcher::MoveParent:
     OS << "OPC_MoveParent,\n";
     return 1;
@@ -1128,6 +1139,8 @@ static StringRef getOpcodeString(Matcher::KindTy Kind) {
     return "OPC_CaptureGlueInput";
   case Matcher::MoveChild:
     return "OPC_MoveChild";
+  case Matcher::MoveSibling:
+    return "OPC_MoveSibling";
   case Matcher::MoveParent:
     return "OPC_MoveParent";
   case Matcher::CheckSame:
diff --git a/llvm/utils/TableGen/DAGISelMatcherOpt.cpp b/llvm/utils/TableGen/DAGISelMatcherOpt.cpp
index bf2a24241e84..c4c25dc1a5fd 100644
--- a/llvm/utils/TableGen/DAGISelMatcherOpt.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherOpt.cpp
@@ -155,6 +155,30 @@ static void ContractNodes(std::unique_ptr<Matcher> &MatcherPtr,
     CheckType->setNext(Tail);
     return ContractNodes(MatcherPtr, CGP);
   }
+
+  // If we have a MoveParent followed by a MoveChild, we convert it to
+  // MoveSibling.
+  if (auto *MP = dyn_cast<MoveParentMatcher>(N)) {
+    if (auto *MC = dyn_cast<MoveChildMatcher>(MP->getNext())) {
+      auto *MS = new MoveSiblingMatcher(MC->getChildNo());
+      MS->setNext(MC->takeNext());
+      MatcherPtr.reset(MS);
+      return ContractNodes(MatcherPtr, CGP);
+    }
+    if (auto *RC = dyn_cast<RecordChildMatcher>(MP->getNext())) {
+      if (auto *MC = dyn_cast<MoveChildMatcher>(RC->getNext())) {
+        if (RC->getChildNo() == MC->getChildNo()) {
+          auto *MS = new MoveSiblingMatcher(MC->getChildNo());
+          auto *RM = new RecordMatcher(RC->getWhatFor(), RC->getResultNo());
+          // Insert the new node.
+          RM->setNext(MC->takeNext());
+          MS->setNext(RM);
+          MatcherPtr.reset(MS);
+          return ContractNodes(MatcherPtr, CGP);
+        }
+      }
+    }
+  }
 }
 
 /// FindNodeWithKind - Scan a series of matchers looking for a matcher with a
-- 
GitLab


From 7cee4704aeca5bb9b171f307b7749d247dc0b446 Mon Sep 17 00:00:00 2001
From: David Spickett <david.spickett@linaro.org>
Date: Tue, 12 Dec 2023 09:53:03 +0000
Subject: [PATCH 254/349] [GitHub] Try a workaround to get the new contributor
 greeting to work (#75036)

For reasons unknown, the FIRST_TIMER and FIRST_TIME_CONTRIBUTOR states
don't come through on new user PRs, I have opened
https://github.com/orgs/community/discussions/78038 to see if that's my
mistake or GitHub's.

In the meantime, a possible workaround is to check that we have none of
the other states. If there's some bug that means the first time
associations aren't available in workflows, maybe the association will
be "NONE".

Also added a debug step to print that association so I can add it to the
linked report. I will remove this as soon as I have 1 example PR.
---
 .github/workflows/new-prs.yml | 21 ++++++++++++++++++---
 1 file changed, 18 insertions(+), 3 deletions(-)

diff --git a/.github/workflows/new-prs.yml b/.github/workflows/new-prs.yml
index 18caa408df57..23455c57ea77 100644
--- a/.github/workflows/new-prs.yml
+++ b/.github/workflows/new-prs.yml
@@ -20,12 +20,19 @@ jobs:
     permissions:
       pull-requests: write
     # Only comment on PRs that have been opened for the first time, by someone
-    # new to LLVM or to GitHub as a whole.
+    # new to LLVM or to GitHub as a whole. Ideally we'd look for FIRST_TIMER
+    # or FIRST_TIME_CONTRIBUTOR, but this does not appear to work. Instead check
+    # that we do not have any of the other author associations.
+    # See https://docs.github.com/en/webhooks/webhook-events-and-payloads?actionType=opened#pull_request
+    # for all the possible values.
     if: >-
       (github.repository == 'llvm/llvm-project') &&
       (github.event.action == 'opened') &&
-      (github.event.pull_request.author_association == 'FIRST_TIME_CONTRIBUTOR' ||
-       github.event.pull_request.author_association == 'FIRST_TIMER')
+      (github.event.pull_request.author_association != 'COLLABORATOR') &&
+      (github.event.pull_request.author_association != 'CONTRIBUTOR') &&
+      (github.event.pull_request.author_association != 'MANNEQUIN') &&
+      (github.event.pull_request.author_association != 'MEMBER') &&
+      (github.event.pull_request.author_association != 'OWNER')
     steps:
       - name: Setup Automation Script
         run: |
@@ -34,6 +41,14 @@ jobs:
           chmod a+x github-automation.py
           pip install -r requirements.txt
 
+      # Will be removed shortly, just gathering info to report to Github that
+      # this is not working as expected.
+      - name: Dump Author Association
+        env:
+          AUTHOR_ASSOCIATION: ${{ github.event.pull_request.author_association }}
+        run: |
+          echo "$AUTHOR_ASSOCIATION"
+
       - name: Greet Author
         run: |
           ./github-automation.py \
-- 
GitLab


From 516e34d98a97b5f684451d2c73855ab42c8b3865 Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Tue, 12 Dec 2023 10:21:55 +0100
Subject: [PATCH 255/349] [LVI] Switch getValueFromCondition() to use recursion

The current implementation using a worklist and visited map adds
a significant amount of additional complexity and compile-time
overhead. All we really care about here is that we don't overflow
the stack or cause exponential complexity in degenerate cases. We
can achieve this with a simple depth limit.
---
 llvm/lib/Analysis/LazyValueInfo.cpp | 98 ++++++-----------------------
 1 file changed, 20 insertions(+), 78 deletions(-)

diff --git a/llvm/lib/Analysis/LazyValueInfo.cpp b/llvm/lib/Analysis/LazyValueInfo.cpp
index b708ee04c0dd..45f7f049ceb9 100644
--- a/llvm/lib/Analysis/LazyValueInfo.cpp
+++ b/llvm/lib/Analysis/LazyValueInfo.cpp
@@ -754,7 +754,8 @@ LazyValueInfoImpl::solveBlockValuePHINode(PHINode *PN, BasicBlock *BB) {
 }
 
 static ValueLatticeElement getValueFromCondition(Value *Val, Value *Cond,
-                                                 bool isTrueDest = true);
+                                                 bool isTrueDest = true,
+                                                 unsigned Depth = 0);
 
 // If we can determine a constraint on the value given conditions assumed by
 // the program, intersect those constraints with BBLV
@@ -1213,36 +1214,22 @@ static ValueLatticeElement getValueFromOverflowCondition(
   return ValueLatticeElement::getRange(NWR);
 }
 
-// Tracks a Value * condition and whether we're interested in it or its inverse
-typedef PointerIntPair<Value *, 1, bool> CondValue;
+static ValueLatticeElement getValueFromCondition(
+    Value *Val, Value *Cond, bool IsTrueDest, unsigned Depth) {
+  if (ICmpInst *ICI = dyn_cast<ICmpInst>(Cond))
+    return getValueFromICmpCondition(Val, ICI, IsTrueDest);
 
-static std::optional<ValueLatticeElement> getValueFromConditionImpl(
-    Value *Val, CondValue CondVal, bool isRevisit,
-    SmallDenseMap<CondValue, ValueLatticeElement> &Visited,
-    SmallVectorImpl<CondValue> &Worklist) {
+  if (auto *EVI = dyn_cast<ExtractValueInst>(Cond))
+    if (auto *WO = dyn_cast<WithOverflowInst>(EVI->getAggregateOperand()))
+      if (EVI->getNumIndices() == 1 && *EVI->idx_begin() == 1)
+        return getValueFromOverflowCondition(Val, WO, IsTrueDest);
 
-  Value *Cond = CondVal.getPointer();
-  bool isTrueDest = CondVal.getInt();
-  if (!isRevisit) {
-    if (ICmpInst *ICI = dyn_cast<ICmpInst>(Cond))
-      return getValueFromICmpCondition(Val, ICI, isTrueDest);
-
-    if (auto *EVI = dyn_cast<ExtractValueInst>(Cond))
-      if (auto *WO = dyn_cast<WithOverflowInst>(EVI->getAggregateOperand()))
-        if (EVI->getNumIndices() == 1 && *EVI->idx_begin() == 1)
-          return getValueFromOverflowCondition(Val, WO, isTrueDest);
-  }
+  if (++Depth == MaxAnalysisRecursionDepth)
+    return ValueLatticeElement::getOverdefined();
 
   Value *N;
-  if (match(Cond, m_Not(m_Value(N)))) {
-    CondValue NKey(N, !isTrueDest);
-    auto NV = Visited.find(NKey);
-    if (NV == Visited.end()) {
-      Worklist.push_back(NKey);
-      return std::nullopt;
-    }
-    return NV->second;
-  }
+  if (match(Cond, m_Not(m_Value(N))))
+    return getValueFromCondition(Val, N, !IsTrueDest, Depth);
 
   Value *L, *R;
   bool IsAnd;
@@ -1253,64 +1240,19 @@ static std::optional<ValueLatticeElement> getValueFromConditionImpl(
   else
     return ValueLatticeElement::getOverdefined();
 
-  auto LV = Visited.find(CondValue(L, isTrueDest));
-  auto RV = Visited.find(CondValue(R, isTrueDest));
+  ValueLatticeElement LV = getValueFromCondition(Val, L, IsTrueDest, Depth);
+  ValueLatticeElement RV = getValueFromCondition(Val, R, IsTrueDest, Depth);
 
   // if (L && R) -> intersect L and R
   // if (!(L || R)) -> intersect !L and !R
   // if (L || R) -> union L and R
   // if (!(L && R)) -> union !L and !R
-  if ((isTrueDest ^ IsAnd) && (LV != Visited.end())) {
-    ValueLatticeElement V = LV->second;
-    if (V.isOverdefined())
-      return V;
-    if (RV != Visited.end()) {
-      V.mergeIn(RV->second);
-      return V;
-    }
-  }
-
-  if (LV == Visited.end() || RV == Visited.end()) {
-    assert(!isRevisit);
-    if (LV == Visited.end())
-      Worklist.push_back(CondValue(L, isTrueDest));
-    if (RV == Visited.end())
-      Worklist.push_back(CondValue(R, isTrueDest));
-    return std::nullopt;
+  if (IsTrueDest ^ IsAnd) {
+    LV.mergeIn(RV);
+    return LV;
   }
 
-  return intersect(LV->second, RV->second);
-}
-
-ValueLatticeElement getValueFromCondition(Value *Val, Value *Cond,
-                                          bool isTrueDest) {
-  assert(Cond && "precondition");
-  SmallDenseMap<CondValue, ValueLatticeElement> Visited;
-  SmallVector<CondValue> Worklist;
-
-  CondValue CondKey(Cond, isTrueDest);
-  Worklist.push_back(CondKey);
-  do {
-    CondValue CurrentCond = Worklist.back();
-    // Insert an Overdefined placeholder into the set to prevent
-    // infinite recursion if there exists IRs that use not
-    // dominated by its def as in this example:
-    //   "%tmp3 = or i1 undef, %tmp4"
-    //   "%tmp4 = or i1 undef, %tmp3"
-    auto Iter =
-        Visited.try_emplace(CurrentCond, ValueLatticeElement::getOverdefined());
-    bool isRevisit = !Iter.second;
-    std::optional<ValueLatticeElement> Result = getValueFromConditionImpl(
-        Val, CurrentCond, isRevisit, Visited, Worklist);
-    if (Result) {
-      Visited[CurrentCond] = *Result;
-      Worklist.pop_back();
-    }
-  } while (!Worklist.empty());
-
-  auto Result = Visited.find(CondKey);
-  assert(Result != Visited.end());
-  return Result->second;
+  return intersect(LV, RV);
 }
 
 // Return true if Usr has Op as an operand, otherwise false.
-- 
GitLab


From c8c9af150d34306ee0af94baf8357891ace233ba Mon Sep 17 00:00:00 2001
From: Timm Baeder <tbaeder@redhat.com>
Date: Tue, 12 Dec 2023 11:01:47 +0100
Subject: [PATCH 256/349] [clang][Interp] Decay arrays to the first element
 (#72660)

This way we have a pointer to the
first element on the stack.
---
 clang/lib/AST/Interp/Interp.h    | 6 ++++--
 clang/test/AST/Interp/arrays.cpp | 4 ++++
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/clang/lib/AST/Interp/Interp.h b/clang/lib/AST/Interp/Interp.h
index 6cf122f2ba55..a240d74d6342 100644
--- a/clang/lib/AST/Interp/Interp.h
+++ b/clang/lib/AST/Interp/Interp.h
@@ -1826,10 +1826,12 @@ inline bool ArrayElemPtr(InterpState &S, CodePtr OpPC) {
 /// Just takes a pointer and checks if its' an incomplete
 /// array type.
 inline bool ArrayDecay(InterpState &S, CodePtr OpPC) {
-  const Pointer &Ptr = S.Stk.peek<Pointer>();
+  const Pointer &Ptr = S.Stk.pop<Pointer>();
 
-  if (!Ptr.isUnknownSizeArray())
+  if (!Ptr.isUnknownSizeArray()) {
+    S.Stk.push<Pointer>(Ptr.atIndex(0));
     return true;
+  }
 
   const SourceInfo &E = S.Current->getSource(OpPC);
   S.FFDiag(E, diag::note_constexpr_unsupported_unsized_array);
diff --git a/clang/test/AST/Interp/arrays.cpp b/clang/test/AST/Interp/arrays.cpp
index 34e0086fb9ee..c455731e7669 100644
--- a/clang/test/AST/Interp/arrays.cpp
+++ b/clang/test/AST/Interp/arrays.cpp
@@ -27,6 +27,10 @@ static_assert(foo[2][3] == &m, "");
 static_assert(foo[2][4] == nullptr, "");
 
 
+constexpr int SomeInt[] = {1};
+constexpr int getSomeInt() { return *SomeInt; }
+static_assert(getSomeInt() == 1, "");
+
 /// A init list for a primitive value.
 constexpr int f{5};
 static_assert(f == 5, "");
-- 
GitLab


From 1908d4cda6760d2c9b28d8bbb4a5b7eeb9697c96 Mon Sep 17 00:00:00 2001
From: Timm Baeder <tbaeder@redhat.com>
Date: Tue, 12 Dec 2023 11:08:38 +0100
Subject: [PATCH 257/349] [clang][Interp] Reject static lambdas with captures
 (#74718)

Static lambdas cannot have captures. They may still end up in the
constant evaluator though. They've been diagnosted appropriately before,
so just reject them here.

This is similar to #74661, but for the new constant expression
interpreter.
---
 clang/lib/AST/Interp/ByteCodeEmitter.cpp |  5 +++++
 clang/test/AST/Interp/cxx23.cpp          | 27 +++++++++++++++++++++---
 2 files changed, 29 insertions(+), 3 deletions(-)

diff --git a/clang/lib/AST/Interp/ByteCodeEmitter.cpp b/clang/lib/AST/Interp/ByteCodeEmitter.cpp
index 89b7708c0c2a..045263447cbc 100644
--- a/clang/lib/AST/Interp/ByteCodeEmitter.cpp
+++ b/clang/lib/AST/Interp/ByteCodeEmitter.cpp
@@ -61,6 +61,11 @@ ByteCodeEmitter::compileFunc(const FunctionDecl *FuncDecl) {
       MD->getParent()->getCaptureFields(LC, LTC);
 
       for (auto Cap : LC) {
+        // Static lambdas cannot have any captures. If this one does,
+        // it has already been diagnosed and we can only ignore it.
+        if (MD->isStatic())
+          return nullptr;
+
         unsigned Offset = R->getField(Cap.second)->Offset;
         this->LambdaCaptures[Cap.first] = {
             Offset, Cap.second->getType()->isReferenceType()};
diff --git a/clang/test/AST/Interp/cxx23.cpp b/clang/test/AST/Interp/cxx23.cpp
index e284a66626fb..bd1cf186d519 100644
--- a/clang/test/AST/Interp/cxx23.cpp
+++ b/clang/test/AST/Interp/cxx23.cpp
@@ -4,9 +4,6 @@
 // RUN: %clang_cc1 -std=c++23 -fsyntax-only -fcxx-exceptions -verify=expected23 %s -fexperimental-new-constant-interpreter
 
 
-// expected23-no-diagnostics
-
-
 /// FIXME: The new interpreter is missing all the 'control flows through...' diagnostics.
 
 constexpr int f(int n) {  // ref20-error {{constexpr function never produces a constant expression}} \
@@ -82,3 +79,27 @@ constexpr int k(int n) {
   return m;
 }
 constexpr int k0 = k(0);
+
+namespace StaticLambdas {
+  constexpr auto static_capture_constexpr() {
+    char n = 'n';
+    return [n] static { return n; }(); // expected23-error {{a static lambda cannot have any captures}} \
+                                       // expected20-error {{a static lambda cannot have any captures}} \
+                                       // expected20-warning {{are a C++23 extension}} \
+                                       // expected20-warning {{is a C++23 extension}} \
+                                       // ref23-error {{a static lambda cannot have any captures}} \
+                                       // ref20-error {{a static lambda cannot have any captures}} \
+                                       // ref20-warning {{are a C++23 extension}} \
+                                       // ref20-warning {{is a C++23 extension}}
+  }
+  static_assert(static_capture_constexpr()); // expected23-error {{static assertion expression is not an integral constant expression}} \
+                                             // expected20-error {{static assertion expression is not an integral constant expression}} \
+                                             // ref23-error {{static assertion expression is not an integral constant expression}} \
+                                             // ref20-error {{static assertion expression is not an integral constant expression}}
+
+  constexpr auto capture_constexpr() {
+    char n = 'n';
+    return [n] { return n; }();
+  }
+  static_assert(capture_constexpr());
+}
-- 
GitLab


From 0c2a3d6033829f0fa22ace8669e4561e7dce2722 Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp@bytedance.com>
Date: Tue, 12 Dec 2023 18:11:26 +0800
Subject: [PATCH 258/349] [TableGen][NFC] Format parts of
 DAGISelMatcher.h/DAGISelMatcherGen.cpp

To reduce the diff in #73310
---
 llvm/utils/TableGen/DAGISelMatcher.h      | 311 +++++++++++-----------
 llvm/utils/TableGen/DAGISelMatcherGen.cpp |  37 +--
 2 files changed, 177 insertions(+), 171 deletions(-)

diff --git a/llvm/utils/TableGen/DAGISelMatcher.h b/llvm/utils/TableGen/DAGISelMatcher.h
index e69f8fa9c5d3..0e8a948ec8a9 100644
--- a/llvm/utils/TableGen/DAGISelMatcher.h
+++ b/llvm/utils/TableGen/DAGISelMatcher.h
@@ -33,162 +33,167 @@ namespace llvm {
   class TreePredicateFn;
   class TreePattern;
 
-Matcher *ConvertPatternToMatcher(const PatternToMatch &Pattern,unsigned Variant,
-                                 const CodeGenDAGPatterns &CGP);
-void OptimizeMatcher(std::unique_ptr<Matcher> &Matcher,
-                     const CodeGenDAGPatterns &CGP);
-void EmitMatcherTable(Matcher *Matcher, const CodeGenDAGPatterns &CGP,
-                      raw_ostream &OS);
-
-
-/// Matcher - Base class for all the DAG ISel Matcher representation
-/// nodes.
-class Matcher {
-  // The next matcher node that is executed after this one.  Null if this is the
-  // last stage of a match.
-  std::unique_ptr<Matcher> Next;
-  size_t Size = 0; // Size in bytes of matcher and all its children (if any).
-  virtual void anchor();
-public:
-  enum KindTy {
-    // Matcher state manipulation.
-    Scope,            // Push a checking scope.
-    RecordNode,       // Record the current node.
-    RecordChild,      // Record a child of the current node.
-    RecordMemRef,     // Record the memref in the current node.
-    CaptureGlueInput, // If the current node has an input glue, save it.
-    MoveChild,        // Move current node to specified child.
-    MoveSibling,      // Move current node to specified sibling.
-    MoveParent,       // Move current node to parent.
-
-    // Predicate checking.
-    CheckSame,      // Fail if not same as prev match.
-    CheckChildSame, // Fail if child not same as prev match.
-    CheckPatternPredicate,
-    CheckPredicate,      // Fail if node predicate fails.
-    CheckOpcode,         // Fail if not opcode.
-    SwitchOpcode,        // Dispatch based on opcode.
-    CheckType,           // Fail if not correct type.
-    SwitchType,          // Dispatch based on type.
-    CheckChildType,      // Fail if child has wrong type.
-    CheckInteger,        // Fail if wrong val.
-    CheckChildInteger,   // Fail if child is wrong val.
-    CheckCondCode,       // Fail if not condcode.
-    CheckChild2CondCode, // Fail if child is wrong condcode.
-    CheckValueType,
-    CheckComplexPat,
-    CheckAndImm,
-    CheckOrImm,
-    CheckImmAllOnesV,
-    CheckImmAllZerosV,
-    CheckFoldableChainNode,
-
-    // Node creation/emisssion.
-    EmitInteger,          // Create a TargetConstant
-    EmitStringInteger,    // Create a TargetConstant from a string.
-    EmitRegister,         // Create a register.
-    EmitConvertToTarget,  // Convert a imm/fpimm to target imm/fpimm
-    EmitMergeInputChains, // Merge together a chains for an input.
-    EmitCopyToReg,        // Emit a copytoreg into a physreg.
-    EmitNode,             // Create a DAG node
-    EmitNodeXForm,        // Run a SDNodeXForm
-    CompleteMatch,        // Finish a match and update the results.
-    MorphNodeTo,          // Build a node, finish a match and update results.
-
-    // Highest enum value; watch out when adding more.
-    HighestKind = MorphNodeTo
-  };
-  const KindTy Kind;
+  Matcher *ConvertPatternToMatcher(const PatternToMatch &Pattern,
+                                   unsigned Variant,
+                                   const CodeGenDAGPatterns &CGP);
+  void OptimizeMatcher(std::unique_ptr<Matcher> &Matcher,
+                       const CodeGenDAGPatterns &CGP);
+  void EmitMatcherTable(Matcher *Matcher, const CodeGenDAGPatterns &CGP,
+                        raw_ostream &OS);
+
+  /// Matcher - Base class for all the DAG ISel Matcher representation
+  /// nodes.
+  class Matcher {
+    // The next matcher node that is executed after this one.  Null if this is
+    // the last stage of a match.
+    std::unique_ptr<Matcher> Next;
+    size_t Size = 0; // Size in bytes of matcher and all its children (if any).
+    virtual void anchor();
+
+  public:
+    enum KindTy {
+      // Matcher state manipulation.
+      Scope,            // Push a checking scope.
+      RecordNode,       // Record the current node.
+      RecordChild,      // Record a child of the current node.
+      RecordMemRef,     // Record the memref in the current node.
+      CaptureGlueInput, // If the current node has an input glue, save it.
+      MoveChild,        // Move current node to specified child.
+      MoveSibling,      // Move current node to specified sibling.
+      MoveParent,       // Move current node to parent.
+
+      // Predicate checking.
+      CheckSame,      // Fail if not same as prev match.
+      CheckChildSame, // Fail if child not same as prev match.
+      CheckPatternPredicate,
+      CheckPredicate,      // Fail if node predicate fails.
+      CheckOpcode,         // Fail if not opcode.
+      SwitchOpcode,        // Dispatch based on opcode.
+      CheckType,           // Fail if not correct type.
+      SwitchType,          // Dispatch based on type.
+      CheckChildType,      // Fail if child has wrong type.
+      CheckInteger,        // Fail if wrong val.
+      CheckChildInteger,   // Fail if child is wrong val.
+      CheckCondCode,       // Fail if not condcode.
+      CheckChild2CondCode, // Fail if child is wrong condcode.
+      CheckValueType,
+      CheckComplexPat,
+      CheckAndImm,
+      CheckOrImm,
+      CheckImmAllOnesV,
+      CheckImmAllZerosV,
+      CheckFoldableChainNode,
+
+      // Node creation/emisssion.
+      EmitInteger,          // Create a TargetConstant
+      EmitStringInteger,    // Create a TargetConstant from a string.
+      EmitRegister,         // Create a register.
+      EmitConvertToTarget,  // Convert a imm/fpimm to target imm/fpimm
+      EmitMergeInputChains, // Merge together a chains for an input.
+      EmitCopyToReg,        // Emit a copytoreg into a physreg.
+      EmitNode,             // Create a DAG node
+      EmitNodeXForm,        // Run a SDNodeXForm
+      CompleteMatch,        // Finish a match and update the results.
+      MorphNodeTo,          // Build a node, finish a match and update results.
+
+      // Highest enum value; watch out when adding more.
+      HighestKind = MorphNodeTo
+    };
+    const KindTy Kind;
+
+  protected:
+    Matcher(KindTy K) : Kind(K) {}
+
+  public:
+    virtual ~Matcher() {}
+
+    unsigned getSize() const { return Size; }
+    void setSize(unsigned sz) { Size = sz; }
+    KindTy getKind() const { return Kind; }
+
+    Matcher *getNext() { return Next.get(); }
+    const Matcher *getNext() const { return Next.get(); }
+    void setNext(Matcher *C) { Next.reset(C); }
+    Matcher *takeNext() { return Next.release(); }
+
+    std::unique_ptr<Matcher> &getNextPtr() { return Next; }
+
+    bool isEqual(const Matcher *M) const {
+      if (getKind() != M->getKind())
+        return false;
+      return isEqualImpl(M);
+    }
 
-protected:
-  Matcher(KindTy K) : Kind(K) {}
-public:
-  virtual ~Matcher() {}
-
-  unsigned getSize() const { return Size; }
-  void setSize(unsigned sz) { Size = sz; }
-  KindTy getKind() const { return Kind; }
-
-  Matcher *getNext() { return Next.get(); }
-  const Matcher *getNext() const { return Next.get(); }
-  void setNext(Matcher *C) { Next.reset(C); }
-  Matcher *takeNext() { return Next.release(); }
-
-  std::unique_ptr<Matcher> &getNextPtr() { return Next; }
-
-  bool isEqual(const Matcher *M) const {
-    if (getKind() != M->getKind()) return false;
-    return isEqualImpl(M);
-  }
-
-  /// isSimplePredicateNode - Return true if this is a simple predicate that
-  /// operates on the node or its children without potential side effects or a
-  /// change of the current node.
-  bool isSimplePredicateNode() const {
-    switch (getKind()) {
-    default: return false;
-    case CheckSame:
-    case CheckChildSame:
-    case CheckPatternPredicate:
-    case CheckPredicate:
-    case CheckOpcode:
-    case CheckType:
-    case CheckChildType:
-    case CheckInteger:
-    case CheckChildInteger:
-    case CheckCondCode:
-    case CheckChild2CondCode:
-    case CheckValueType:
-    case CheckAndImm:
-    case CheckOrImm:
-    case CheckImmAllOnesV:
-    case CheckImmAllZerosV:
-    case CheckFoldableChainNode:
-      return true;
+    /// isSimplePredicateNode - Return true if this is a simple predicate that
+    /// operates on the node or its children without potential side effects or a
+    /// change of the current node.
+    bool isSimplePredicateNode() const {
+      switch (getKind()) {
+      default:
+        return false;
+      case CheckSame:
+      case CheckChildSame:
+      case CheckPatternPredicate:
+      case CheckPredicate:
+      case CheckOpcode:
+      case CheckType:
+      case CheckChildType:
+      case CheckInteger:
+      case CheckChildInteger:
+      case CheckCondCode:
+      case CheckChild2CondCode:
+      case CheckValueType:
+      case CheckAndImm:
+      case CheckOrImm:
+      case CheckImmAllOnesV:
+      case CheckImmAllZerosV:
+      case CheckFoldableChainNode:
+        return true;
+      }
     }
-  }
 
-  /// isSimplePredicateOrRecordNode - Return true if this is a record node or
-  /// a simple predicate.
-  bool isSimplePredicateOrRecordNode() const {
-    return isSimplePredicateNode() ||
-           getKind() == RecordNode || getKind() == RecordChild;
-  }
-
-  /// unlinkNode - Unlink the specified node from this chain.  If Other == this,
-  /// we unlink the next pointer and return it.  Otherwise we unlink Other from
-  /// the list and return this.
-  Matcher *unlinkNode(Matcher *Other);
-
-  /// canMoveBefore - Return true if this matcher is the same as Other, or if
-  /// we can move this matcher past all of the nodes in-between Other and this
-  /// node.  Other must be equal to or before this.
-  bool canMoveBefore(const Matcher *Other) const;
-
-  /// canMoveBeforeNode - Return true if it is safe to move the current matcher
-  /// across the specified one.
-  bool canMoveBeforeNode(const Matcher *Other) const;
-
-  /// isContradictory - Return true of these two matchers could never match on
-  /// the same node.
-  bool isContradictory(const Matcher *Other) const {
-    // Since this predicate is reflexive, we canonicalize the ordering so that
-    // we always match a node against nodes with kinds that are greater or equal
-    // to them.  For example, we'll pass in a CheckType node as an argument to
-    // the CheckOpcode method, not the other way around.
-    if (getKind() < Other->getKind())
-      return isContradictoryImpl(Other);
-    return Other->isContradictoryImpl(this);
-  }
-
-  void print(raw_ostream &OS, unsigned indent = 0) const;
-  void printOne(raw_ostream &OS) const;
-  void dump() const;
-protected:
-  virtual void printImpl(raw_ostream &OS, unsigned indent) const = 0;
-  virtual bool isEqualImpl(const Matcher *M) const = 0;
-  virtual bool isContradictoryImpl(const Matcher *M) const { return false; }
-};
+    /// isSimplePredicateOrRecordNode - Return true if this is a record node or
+    /// a simple predicate.
+    bool isSimplePredicateOrRecordNode() const {
+      return isSimplePredicateNode() || getKind() == RecordNode ||
+             getKind() == RecordChild;
+    }
+
+    /// unlinkNode - Unlink the specified node from this chain.  If Other ==
+    /// this, we unlink the next pointer and return it.  Otherwise we unlink
+    /// Other from the list and return this.
+    Matcher *unlinkNode(Matcher *Other);
+
+    /// canMoveBefore - Return true if this matcher is the same as Other, or if
+    /// we can move this matcher past all of the nodes in-between Other and this
+    /// node.  Other must be equal to or before this.
+    bool canMoveBefore(const Matcher *Other) const;
+
+    /// canMoveBeforeNode - Return true if it is safe to move the current
+    /// matcher across the specified one.
+    bool canMoveBeforeNode(const Matcher *Other) const;
+
+    /// isContradictory - Return true of these two matchers could never match on
+    /// the same node.
+    bool isContradictory(const Matcher *Other) const {
+      // Since this predicate is reflexive, we canonicalize the ordering so that
+      // we always match a node against nodes with kinds that are greater or
+      // equal to them.  For example, we'll pass in a CheckType node as an
+      // argument to the CheckOpcode method, not the other way around.
+      if (getKind() < Other->getKind())
+        return isContradictoryImpl(Other);
+      return Other->isContradictoryImpl(this);
+    }
+
+    void print(raw_ostream &OS, unsigned indent = 0) const;
+    void printOne(raw_ostream &OS) const;
+    void dump() const;
+
+  protected:
+    virtual void printImpl(raw_ostream &OS, unsigned indent) const = 0;
+    virtual bool isEqualImpl(const Matcher *M) const = 0;
+    virtual bool isContradictoryImpl(const Matcher *M) const { return false; }
+  };
 
 /// ScopeMatcher - This attempts to match each of its children to find the first
 /// one that successfully matches.  If one child fails, it tries the next child.
diff --git a/llvm/utils/TableGen/DAGISelMatcherGen.cpp b/llvm/utils/TableGen/DAGISelMatcherGen.cpp
index d08f57b84b95..fcc5e4d061c8 100644
--- a/llvm/utils/TableGen/DAGISelMatcherGen.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherGen.cpp
@@ -147,25 +147,26 @@ namespace {
 
 MatcherGen::MatcherGen(const PatternToMatch &pattern,
                        const CodeGenDAGPatterns &cgp)
-: Pattern(pattern), CGP(cgp), NextRecordedOperandNo(0),
-  TheMatcher(nullptr), CurPredicate(nullptr) {
-  // We need to produce the matcher tree for the patterns source pattern.  To do
-  // this we need to match the structure as well as the types.  To do the type
-  // matching, we want to figure out the fewest number of type checks we need to
-  // emit.  For example, if there is only one integer type supported by a
-  // target, there should be no type comparisons at all for integer patterns!
-  //
-  // To figure out the fewest number of type checks needed, clone the pattern,
-  // remove the types, then perform type inference on the pattern as a whole.
-  // If there are unresolved types, emit an explicit check for those types,
-  // apply the type to the tree, then rerun type inference.  Iterate until all
-  // types are resolved.
-  //
-  PatWithNoTypes = Pattern.getSrcPattern()->clone();
-  PatWithNoTypes->RemoveAllTypes();
+    : Pattern(pattern), CGP(cgp), NextRecordedOperandNo(0), TheMatcher(nullptr),
+      CurPredicate(nullptr) {
+    // We need to produce the matcher tree for the patterns source pattern.  To
+    // do this we need to match the structure as well as the types.  To do the
+    // type matching, we want to figure out the fewest number of type checks we
+    // need to emit.  For example, if there is only one integer type supported
+    // by a target, there should be no type comparisons at all for integer
+    // patterns!
+    //
+    // To figure out the fewest number of type checks needed, clone the pattern,
+    // remove the types, then perform type inference on the pattern as a whole.
+    // If there are unresolved types, emit an explicit check for those types,
+    // apply the type to the tree, then rerun type inference.  Iterate until all
+    // types are resolved.
+    //
+    PatWithNoTypes = Pattern.getSrcPattern()->clone();
+    PatWithNoTypes->RemoveAllTypes();
 
-  // If there are types that are manifestly known, infer them.
-  InferPossibleTypes();
+    // If there are types that are manifestly known, infer them.
+    InferPossibleTypes();
 }
 
 /// InferPossibleTypes - As we emit the pattern, we end up generating type
-- 
GitLab


From bbc7f099590cb33b220c12bfe8f5c8ff7b7a5011 Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp@bytedance.com>
Date: Tue, 12 Dec 2023 18:17:13 +0800
Subject: [PATCH 259/349] [TableGen][NFC] Remove leading spaces

---
 llvm/utils/TableGen/DAGISelMatcherGen.cpp | 34 +++++++++++------------
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/llvm/utils/TableGen/DAGISelMatcherGen.cpp b/llvm/utils/TableGen/DAGISelMatcherGen.cpp
index fcc5e4d061c8..3526e97c8e08 100644
--- a/llvm/utils/TableGen/DAGISelMatcherGen.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherGen.cpp
@@ -149,24 +149,24 @@ MatcherGen::MatcherGen(const PatternToMatch &pattern,
                        const CodeGenDAGPatterns &cgp)
     : Pattern(pattern), CGP(cgp), NextRecordedOperandNo(0), TheMatcher(nullptr),
       CurPredicate(nullptr) {
-    // We need to produce the matcher tree for the patterns source pattern.  To
-    // do this we need to match the structure as well as the types.  To do the
-    // type matching, we want to figure out the fewest number of type checks we
-    // need to emit.  For example, if there is only one integer type supported
-    // by a target, there should be no type comparisons at all for integer
-    // patterns!
-    //
-    // To figure out the fewest number of type checks needed, clone the pattern,
-    // remove the types, then perform type inference on the pattern as a whole.
-    // If there are unresolved types, emit an explicit check for those types,
-    // apply the type to the tree, then rerun type inference.  Iterate until all
-    // types are resolved.
-    //
-    PatWithNoTypes = Pattern.getSrcPattern()->clone();
-    PatWithNoTypes->RemoveAllTypes();
+  // We need to produce the matcher tree for the patterns source pattern.  To
+  // do this we need to match the structure as well as the types.  To do the
+  // type matching, we want to figure out the fewest number of type checks we
+  // need to emit.  For example, if there is only one integer type supported
+  // by a target, there should be no type comparisons at all for integer
+  // patterns!
+  //
+  // To figure out the fewest number of type checks needed, clone the pattern,
+  // remove the types, then perform type inference on the pattern as a whole.
+  // If there are unresolved types, emit an explicit check for those types,
+  // apply the type to the tree, then rerun type inference.  Iterate until all
+  // types are resolved.
+  //
+  PatWithNoTypes = Pattern.getSrcPattern()->clone();
+  PatWithNoTypes->RemoveAllTypes();
 
-    // If there are types that are manifestly known, infer them.
-    InferPossibleTypes();
+  // If there are types that are manifestly known, infer them.
+  InferPossibleTypes();
 }
 
 /// InferPossibleTypes - As we emit the pattern, we end up generating type
-- 
GitLab


From 23d0a3044cdb6a6b543a58bb9278f62a1c9810db Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Tue, 12 Dec 2023 11:11:25 +0100
Subject: [PATCH 260/349] [CVP] Regenerate test checks (NFC)

---
 .../CorrelatedValuePropagation/add.ll         | 272 +++++++++++++++---
 1 file changed, 236 insertions(+), 36 deletions(-)

diff --git a/llvm/test/Transforms/CorrelatedValuePropagation/add.ll b/llvm/test/Transforms/CorrelatedValuePropagation/add.ll
index 9ddb7dace104..d2b543168253 100644
--- a/llvm/test/Transforms/CorrelatedValuePropagation/add.ll
+++ b/llvm/test/Transforms/CorrelatedValuePropagation/add.ll
@@ -1,13 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
 ; RUN: opt < %s -passes=correlated-propagation -S | FileCheck %s
 
-; CHECK-LABEL: @test0(
 define void @test0(i32 %a) {
+; CHECK-LABEL: define void @test0(
+; CHECK-SAME: i32 [[A:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[A]], 100
+; CHECK-NEXT:    br i1 [[CMP]], label [[BB:%.*]], label [[EXIT:%.*]]
+; CHECK:       bb:
+; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[A]], 1
+; CHECK-NEXT:    br label [[EXIT]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
 entry:
   %cmp = icmp slt i32 %a, 100
   br i1 %cmp, label %bb, label %exit
 
 bb:
-; CHECK: %add = add nsw i32 %a, 1
   %add = add i32 %a, 1
   br label %exit
 
@@ -15,14 +25,23 @@ exit:
   ret void
 }
 
-; CHECK-LABEL: @test1(
 define void @test1(i32 %a) {
+; CHECK-LABEL: define void @test1(
+; CHECK-SAME: i32 [[A:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[A]], 100
+; CHECK-NEXT:    br i1 [[CMP]], label [[BB:%.*]], label [[EXIT:%.*]]
+; CHECK:       bb:
+; CHECK-NEXT:    [[ADD:%.*]] = add nuw nsw i32 [[A]], 1
+; CHECK-NEXT:    br label [[EXIT]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
 entry:
   %cmp = icmp ult i32 %a, 100
   br i1 %cmp, label %bb, label %exit
 
 bb:
-; CHECK: %add = add nuw nsw i32 %a, 1
   %add = add i32 %a, 1
   br label %exit
 
@@ -30,14 +49,23 @@ exit:
   ret void
 }
 
-; CHECK-LABEL: @test2(
 define void @test2(i32 %a) {
+; CHECK-LABEL: define void @test2(
+; CHECK-SAME: i32 [[A:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[A]], -1
+; CHECK-NEXT:    br i1 [[CMP]], label [[BB:%.*]], label [[EXIT:%.*]]
+; CHECK:       bb:
+; CHECK-NEXT:    [[ADD:%.*]] = add nuw i32 [[A]], 1
+; CHECK-NEXT:    br label [[EXIT]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
 entry:
   %cmp = icmp ult i32 %a, -1
   br i1 %cmp, label %bb, label %exit
 
 bb:
-; CHECK: %add = add nuw i32 %a, 1
   %add = add i32 %a, 1
   br label %exit
 
@@ -45,14 +73,23 @@ exit:
   ret void
 }
 
-; CHECK-LABEL: @test3(
 define void @test3(i32 %a) {
+; CHECK-LABEL: define void @test3(
+; CHECK-SAME: i32 [[A:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ule i32 [[A]], -1
+; CHECK-NEXT:    br i1 [[CMP]], label [[BB:%.*]], label [[EXIT:%.*]]
+; CHECK:       bb:
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[A]], 1
+; CHECK-NEXT:    br label [[EXIT]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
 entry:
   %cmp = icmp ule i32 %a, -1
   br i1 %cmp, label %bb, label %exit
 
 bb:
-; CHECK: %add = add i32 %a, 1
   %add = add i32 %a, 1
   br label %exit
 
@@ -60,14 +97,23 @@ exit:
   ret void
 }
 
-; CHECK-LABEL: @test4(
 define void @test4(i32 %a) {
+; CHECK-LABEL: define void @test4(
+; CHECK-SAME: i32 [[A:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[A]], 2147483647
+; CHECK-NEXT:    br i1 [[CMP]], label [[BB:%.*]], label [[EXIT:%.*]]
+; CHECK:       bb:
+; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[A]], 1
+; CHECK-NEXT:    br label [[EXIT]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
 entry:
   %cmp = icmp slt i32 %a, 2147483647
   br i1 %cmp, label %bb, label %exit
 
 bb:
-; CHECK: %add = add nsw i32 %a, 1
   %add = add i32 %a, 1
   br label %exit
 
@@ -75,14 +121,23 @@ exit:
   ret void
 }
 
-; CHECK-LABEL: @test5(
 define void @test5(i32 %a) {
+; CHECK-LABEL: define void @test5(
+; CHECK-SAME: i32 [[A:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sle i32 [[A]], 2147483647
+; CHECK-NEXT:    br i1 [[CMP]], label [[BB:%.*]], label [[EXIT:%.*]]
+; CHECK:       bb:
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[A]], 1
+; CHECK-NEXT:    br label [[EXIT]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
 entry:
   %cmp = icmp sle i32 %a, 2147483647
   br i1 %cmp, label %bb, label %exit
 
 bb:
-; CHECK: %add = add i32 %a, 1
   %add = add i32 %a, 1
   br label %exit
 
@@ -95,6 +150,12 @@ exit:
 ; assertion in this case.
 @b = global i32 0, align 4
 define void @test6(i32 %a) {
+; CHECK-LABEL: define void @test6(
+; CHECK-SAME: i32 [[A:%.*]]) {
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[A]], ptrtoint (ptr @b to i32)
+; CHECK-NEXT:    ret void
+;
 bb:
   %add = add i32 %a, ptrtoint (ptr @b to i32)
   ret void
@@ -102,15 +163,25 @@ bb:
 
 ; Check that we can gather information for conditions is the form of
 ;   and ( i s< 100, Unknown )
-; CHECK-LABEL: @test7(
 define void @test7(i32 %a, i1 %flag) {
+; CHECK-LABEL: define void @test7(
+; CHECK-SAME: i32 [[A:%.*]], i1 [[FLAG:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP_1:%.*]] = icmp slt i32 [[A]], 100
+; CHECK-NEXT:    [[CMP:%.*]] = and i1 [[CMP_1]], [[FLAG]]
+; CHECK-NEXT:    br i1 [[CMP]], label [[BB:%.*]], label [[EXIT:%.*]]
+; CHECK:       bb:
+; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[A]], 1
+; CHECK-NEXT:    br label [[EXIT]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
 entry:
   %cmp.1 = icmp slt i32 %a, 100
   %cmp = and i1 %cmp.1, %flag
   br i1 %cmp, label %bb, label %exit
 
 bb:
-; CHECK: %add = add nsw i32 %a, 1
   %add = add i32 %a, 1
   br label %exit
 
@@ -120,8 +191,20 @@ exit:
 
 ; Check that we can gather information for conditions is the form of
 ;   and ( i s< 100, i s> 0 )
-; CHECK-LABEL: @test8(
 define void @test8(i32 %a) {
+; CHECK-LABEL: define void @test8(
+; CHECK-SAME: i32 [[A:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP_1:%.*]] = icmp slt i32 [[A]], 100
+; CHECK-NEXT:    [[CMP_2:%.*]] = icmp sgt i32 [[A]], 0
+; CHECK-NEXT:    [[CMP:%.*]] = and i1 [[CMP_1]], [[CMP_2]]
+; CHECK-NEXT:    br i1 [[CMP]], label [[BB:%.*]], label [[EXIT:%.*]]
+; CHECK:       bb:
+; CHECK-NEXT:    [[ADD:%.*]] = add nuw nsw i32 [[A]], 1
+; CHECK-NEXT:    br label [[EXIT]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
 entry:
   %cmp.1 = icmp slt i32 %a, 100
   %cmp.2 = icmp sgt i32 %a, 0
@@ -129,7 +212,6 @@ entry:
   br i1 %cmp, label %bb, label %exit
 
 bb:
-; CHECK: %add = add nuw nsw i32 %a, 1
   %add = add i32 %a, 1
   br label %exit
 
@@ -139,8 +221,20 @@ exit:
 
 ; Check that for conditions is the form of cond1 && cond2 we don't mistakenly
 ; assume that !cond1 && !cond2 holds down to false path.
-; CHECK-LABEL: @test8_neg(
 define void @test8_neg(i32 %a) {
+; CHECK-LABEL: define void @test8_neg(
+; CHECK-SAME: i32 [[A:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP_1:%.*]] = icmp sge i32 [[A]], 100
+; CHECK-NEXT:    [[CMP_2:%.*]] = icmp sle i32 [[A]], 0
+; CHECK-NEXT:    [[CMP:%.*]] = and i1 [[CMP_1]], [[CMP_2]]
+; CHECK-NEXT:    br i1 [[CMP]], label [[EXIT:%.*]], label [[BB:%.*]]
+; CHECK:       bb:
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[A]], 1
+; CHECK-NEXT:    br label [[EXIT]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
 entry:
   %cmp.1 = icmp sge i32 %a, 100
   %cmp.2 = icmp sle i32 %a, 0
@@ -148,7 +242,6 @@ entry:
   br i1 %cmp, label %exit, label %bb
 
 bb:
-; CHECK: %add = add i32 %a, 1
   %add = add i32 %a, 1
   br label %exit
 
@@ -158,8 +251,21 @@ exit:
 
 ; Check that we can gather information for conditions is the form of
 ;   and ( i s< 100, and (i s> 0, Unknown )
-; CHECK-LABEL: @test9(
 define void @test9(i32 %a, i1 %flag) {
+; CHECK-LABEL: define void @test9(
+; CHECK-SAME: i32 [[A:%.*]], i1 [[FLAG:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP_1:%.*]] = icmp slt i32 [[A]], 100
+; CHECK-NEXT:    [[CMP_2:%.*]] = icmp sgt i32 [[A]], 0
+; CHECK-NEXT:    [[CMP_3:%.*]] = and i1 [[CMP_2]], [[FLAG]]
+; CHECK-NEXT:    [[CMP:%.*]] = and i1 [[CMP_1]], [[CMP_3]]
+; CHECK-NEXT:    br i1 [[CMP]], label [[BB:%.*]], label [[EXIT:%.*]]
+; CHECK:       bb:
+; CHECK-NEXT:    [[ADD:%.*]] = add nuw nsw i32 [[A]], 1
+; CHECK-NEXT:    br label [[EXIT]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
 entry:
   %cmp.1 = icmp slt i32 %a, 100
   %cmp.2 = icmp sgt i32 %a, 0
@@ -168,7 +274,6 @@ entry:
   br i1 %cmp, label %bb, label %exit
 
 bb:
-; CHECK: %add = add nuw nsw i32 %a, 1
   %add = add i32 %a, 1
   br label %exit
 
@@ -178,15 +283,25 @@ exit:
 
 ; Check that we can gather information for conditions is the form of
 ;   and ( i s< Unknown, ... )
-; CHECK-LABEL: @test10(
 define void @test10(i32 %a, i32 %b, i1 %flag) {
+; CHECK-LABEL: define void @test10(
+; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i1 [[FLAG:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP_1:%.*]] = icmp slt i32 [[A]], [[B]]
+; CHECK-NEXT:    [[CMP:%.*]] = and i1 [[CMP_1]], [[FLAG]]
+; CHECK-NEXT:    br i1 [[CMP]], label [[BB:%.*]], label [[EXIT:%.*]]
+; CHECK:       bb:
+; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[A]], 1
+; CHECK-NEXT:    br label [[EXIT]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
 entry:
   %cmp.1 = icmp slt i32 %a, %b
   %cmp = and i1 %cmp.1, %flag
   br i1 %cmp, label %bb, label %exit
 
 bb:
-; CHECK: %add = add nsw i32 %a, 1
   %add = add i32 %a, 1
   br label %exit
 
@@ -195,8 +310,21 @@ exit:
 }
 
 @limit = external global i32
-; CHECK-LABEL: @test11(
 define i32 @test11(ptr %p, i32 %i) {
+; CHECK-LABEL: define i32 @test11(
+; CHECK-SAME: ptr [[P:%.*]], i32 [[I:%.*]]) {
+; CHECK-NEXT:    [[LIMIT:%.*]] = load i32, ptr [[P]], align 4, !range [[RNG0:![0-9]+]]
+; CHECK-NEXT:    [[WITHIN_1:%.*]] = icmp ugt i32 [[LIMIT]], [[I]]
+; CHECK-NEXT:    [[I_PLUS_7:%.*]] = add i32 [[I]], 7
+; CHECK-NEXT:    [[WITHIN_2:%.*]] = icmp ugt i32 [[LIMIT]], [[I_PLUS_7]]
+; CHECK-NEXT:    [[WITHIN:%.*]] = and i1 [[WITHIN_1]], [[WITHIN_2]]
+; CHECK-NEXT:    br i1 [[WITHIN]], label [[THEN:%.*]], label [[ELSE:%.*]]
+; CHECK:       then:
+; CHECK-NEXT:    [[I_PLUS_6:%.*]] = add nuw nsw i32 [[I]], 6
+; CHECK-NEXT:    ret i32 [[I_PLUS_6]]
+; CHECK:       else:
+; CHECK-NEXT:    ret i32 0
+;
   %limit = load i32, ptr %p, !range !{i32 0, i32 2147483647}
   %within.1 = icmp ugt i32 %limit, %i
   %i.plus.7 = add i32 %i, 7
@@ -205,7 +333,6 @@ define i32 @test11(ptr %p, i32 %i) {
   br i1 %within, label %then, label %else
 
 then:
-; CHECK: %i.plus.6 = add nuw nsw i32 %i, 6
   %i.plus.6 = add i32 %i, 6
   ret i32 %i.plus.6
 
@@ -215,15 +342,25 @@ else:
 
 ; Check that we can gather information for conditions is the form of
 ;   or ( i s>= 100, Unknown )
-; CHECK-LABEL: @test12(
 define void @test12(i32 %a, i1 %flag) {
+; CHECK-LABEL: define void @test12(
+; CHECK-SAME: i32 [[A:%.*]], i1 [[FLAG:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP_1:%.*]] = icmp sge i32 [[A]], 100
+; CHECK-NEXT:    [[CMP:%.*]] = or i1 [[CMP_1]], [[FLAG]]
+; CHECK-NEXT:    br i1 [[CMP]], label [[EXIT:%.*]], label [[BB:%.*]]
+; CHECK:       bb:
+; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[A]], 1
+; CHECK-NEXT:    br label [[EXIT]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
 entry:
   %cmp.1 = icmp sge i32 %a, 100
   %cmp = or i1 %cmp.1, %flag
   br i1 %cmp, label %exit, label %bb
 
 bb:
-; CHECK: %add = add nsw i32 %a, 1
   %add = add i32 %a, 1
   br label %exit
 
@@ -233,8 +370,20 @@ exit:
 
 ; Check that we can gather information for conditions is the form of
 ;   or ( i s>= 100, i s<= 0 )
-; CHECK-LABEL: @test13(
 define void @test13(i32 %a) {
+; CHECK-LABEL: define void @test13(
+; CHECK-SAME: i32 [[A:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP_1:%.*]] = icmp sge i32 [[A]], 100
+; CHECK-NEXT:    [[CMP_2:%.*]] = icmp sle i32 [[A]], 0
+; CHECK-NEXT:    [[CMP:%.*]] = or i1 [[CMP_1]], [[CMP_2]]
+; CHECK-NEXT:    br i1 [[CMP]], label [[EXIT:%.*]], label [[BB:%.*]]
+; CHECK:       bb:
+; CHECK-NEXT:    [[ADD:%.*]] = add nuw nsw i32 [[A]], 1
+; CHECK-NEXT:    br label [[EXIT]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
 entry:
   %cmp.1 = icmp sge i32 %a, 100
   %cmp.2 = icmp sle i32 %a, 0
@@ -242,7 +391,6 @@ entry:
   br i1 %cmp, label %exit, label %bb
 
 bb:
-; CHECK: %add = add nuw nsw i32 %a, 1
   %add = add i32 %a, 1
   br label %exit
 
@@ -252,8 +400,20 @@ exit:
 
 ; Check that for conditions is the form of cond1 || cond2 we don't mistakenly
 ; assume that cond1 || cond2 holds down to true path.
-; CHECK-LABEL: @test13_neg(
 define void @test13_neg(i32 %a) {
+; CHECK-LABEL: define void @test13_neg(
+; CHECK-SAME: i32 [[A:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP_1:%.*]] = icmp slt i32 [[A]], 100
+; CHECK-NEXT:    [[CMP_2:%.*]] = icmp sgt i32 [[A]], 0
+; CHECK-NEXT:    [[CMP:%.*]] = or i1 [[CMP_1]], [[CMP_2]]
+; CHECK-NEXT:    br i1 [[CMP]], label [[BB:%.*]], label [[EXIT:%.*]]
+; CHECK:       bb:
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[A]], 1
+; CHECK-NEXT:    br label [[EXIT]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
 entry:
   %cmp.1 = icmp slt i32 %a, 100
   %cmp.2 = icmp sgt i32 %a, 0
@@ -261,7 +421,6 @@ entry:
   br i1 %cmp, label %bb, label %exit
 
 bb:
-; CHECK: %add = add i32 %a, 1
   %add = add i32 %a, 1
   br label %exit
 
@@ -271,8 +430,21 @@ exit:
 
 ; Check that we can gather information for conditions is the form of
 ;   or ( i s>=100, or (i s<= 0, Unknown )
-; CHECK-LABEL: @test14(
 define void @test14(i32 %a, i1 %flag) {
+; CHECK-LABEL: define void @test14(
+; CHECK-SAME: i32 [[A:%.*]], i1 [[FLAG:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP_1:%.*]] = icmp sge i32 [[A]], 100
+; CHECK-NEXT:    [[CMP_2:%.*]] = icmp sle i32 [[A]], 0
+; CHECK-NEXT:    [[CMP_3:%.*]] = or i1 [[CMP_2]], [[FLAG]]
+; CHECK-NEXT:    [[CMP:%.*]] = or i1 [[CMP_1]], [[CMP_3]]
+; CHECK-NEXT:    br i1 [[CMP]], label [[EXIT:%.*]], label [[BB:%.*]]
+; CHECK:       bb:
+; CHECK-NEXT:    [[ADD:%.*]] = add nuw nsw i32 [[A]], 1
+; CHECK-NEXT:    br label [[EXIT]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
 entry:
   %cmp.1 = icmp sge i32 %a, 100
   %cmp.2 = icmp sle i32 %a, 0
@@ -281,7 +453,6 @@ entry:
   br i1 %cmp, label %exit, label %bb
 
 bb:
-; CHECK: %add = add nuw nsw i32 %a, 1
   %add = add i32 %a, 1
   br label %exit
 
@@ -291,15 +462,25 @@ exit:
 
 ; Check that we can gather information for conditions is the form of
 ;   or ( i s>= Unknown, ... )
-; CHECK-LABEL: @test15(
 define void @test15(i32 %a, i32 %b, i1 %flag) {
+; CHECK-LABEL: define void @test15(
+; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i1 [[FLAG:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP_1:%.*]] = icmp sge i32 [[A]], [[B]]
+; CHECK-NEXT:    [[CMP:%.*]] = or i1 [[CMP_1]], [[FLAG]]
+; CHECK-NEXT:    br i1 [[CMP]], label [[EXIT:%.*]], label [[BB:%.*]]
+; CHECK:       bb:
+; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[A]], 1
+; CHECK-NEXT:    br label [[EXIT]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
 entry:
   %cmp.1 = icmp sge i32 %a, %b
   %cmp = or i1 %cmp.1, %flag
   br i1 %cmp, label %exit, label %bb
 
 bb:
-; CHECK: %add = add nsw i32 %a, 1
   %add = add i32 %a, 1
   br label %exit
 
@@ -310,13 +491,28 @@ exit:
 ; single basic block loop
 ; because the loop exit condition is SLT, we can supplement the iv add
 ; (iv.next def) with an nsw.
-; CHECK-LABEL: @test16(
 define i32 @test16(ptr %n, ptr %a) {
+; CHECK-LABEL: define i32 @test16(
+; CHECK-SAME: ptr [[N:%.*]], ptr [[A:%.*]]) {
+; CHECK-NEXT:  preheader:
+; CHECK-NEXT:    br label [[LOOP:%.*]]
+; CHECK:       loop:
+; CHECK-NEXT:    [[IV:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT:    [[ACC:%.*]] = phi i32 [ 0, [[PREHEADER]] ], [ [[ACC_CURR:%.*]], [[LOOP]] ]
+; CHECK-NEXT:    [[X:%.*]] = load atomic i32, ptr [[A]] unordered, align 8
+; CHECK-NEXT:    fence acquire
+; CHECK-NEXT:    [[ACC_CURR]] = add i32 [[ACC]], [[X]]
+; CHECK-NEXT:    [[IV_NEXT]] = add nsw i32 [[IV]], 1
+; CHECK-NEXT:    [[NVAL:%.*]] = load atomic i32, ptr [[N]] unordered, align 8
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[IV_NEXT]], [[NVAL]]
+; CHECK-NEXT:    br i1 [[CMP]], label [[LOOP]], label [[EXIT:%.*]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret i32 [[ACC_CURR]]
+;
 preheader:
   br label %loop
 
 loop:
-; CHECK: %iv.next = add nsw i32 %iv, 1
   %iv = phi i32 [ 0, %preheader ], [ %iv.next, %loop ]
   %acc = phi i32 [ 0, %preheader ], [ %acc.curr, %loop ]
   %x = load atomic i32, ptr %a unordered, align 8
@@ -330,3 +526,7 @@ loop:
 exit:
   ret i32 %acc.curr
 }
+
+;.
+; CHECK: [[RNG0]] = !{i32 0, i32 2147483647}
+;.
-- 
GitLab


From 5799d1310759bf71edb62e050e2ed884c8f575f0 Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Tue, 12 Dec 2023 11:13:51 +0100
Subject: [PATCH 261/349] [CVP] Add test for incorrect use of range with undef
 (NFC)

---
 .../CorrelatedValuePropagation/add.ll         | 36 +++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/llvm/test/Transforms/CorrelatedValuePropagation/add.ll b/llvm/test/Transforms/CorrelatedValuePropagation/add.ll
index d2b543168253..0768408563f5 100644
--- a/llvm/test/Transforms/CorrelatedValuePropagation/add.ll
+++ b/llvm/test/Transforms/CorrelatedValuePropagation/add.ll
@@ -527,6 +527,42 @@ exit:
   ret i32 %acc.curr
 }
 
+; FIXME: This is a miscompile.
+define i32 @test_undef_range(i32 %x) {
+; CHECK-LABEL: define i32 @test_undef_range(
+; CHECK-SAME: i32 [[X:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i32 [[X]], label [[JOIN:%.*]] [
+; CHECK-NEXT:      i32 1, label [[CASE1:%.*]]
+; CHECK-NEXT:      i32 2, label [[CASE2:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       case1:
+; CHECK-NEXT:    br label [[JOIN]]
+; CHECK:       case2:
+; CHECK-NEXT:    br label [[JOIN]]
+; CHECK:       join:
+; CHECK-NEXT:    [[PHI:%.*]] = phi i32 [ 1, [[CASE1]] ], [ 2, [[CASE2]] ], [ undef, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    [[ADD:%.*]] = add nuw nsw i32 [[PHI]], 1
+; CHECK-NEXT:    ret i32 [[ADD]]
+;
+entry:
+  switch i32 %x, label %join [
+  i32 1, label %case1
+  i32 2, label %case2
+  ]
+
+case1:
+  br label %join
+
+case2:
+  br label %join
+
+join:
+  %phi = phi i32 [ 1, %case1 ], [ 2, %case2 ], [ undef, %entry ]
+  %add = add i32 %phi, 1
+  ret i32 %add
+}
+
 ;.
 ; CHECK: [[RNG0]] = !{i32 0, i32 2147483647}
 ;.
-- 
GitLab


From 4949fb7954ba3b98026ce358af328396b858134a Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Tue, 12 Dec 2023 11:19:19 +0100
Subject: [PATCH 262/349] [CVP] Don't allow undef range when inferring nowrap
 flags

---
 llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp | 6 ++++--
 llvm/test/Transforms/CorrelatedValuePropagation/add.ll    | 3 +--
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp b/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
index a5cf875ef354..669bdf50ba6e 100644
--- a/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
+++ b/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
@@ -1048,8 +1048,10 @@ static bool processBinOp(BinaryOperator *BinOp, LazyValueInfo *LVI) {
   Value *LHS = BinOp->getOperand(0);
   Value *RHS = BinOp->getOperand(1);
 
-  ConstantRange LRange = LVI->getConstantRange(LHS, BinOp);
-  ConstantRange RRange = LVI->getConstantRange(RHS, BinOp);
+  ConstantRange LRange =
+      LVI->getConstantRange(LHS, BinOp, /*UndefAllowed*/ false);
+  ConstantRange RRange =
+      LVI->getConstantRange(RHS, BinOp, /*UndefAllowed*/ false);
 
   bool Changed = false;
   bool NewNUW = false, NewNSW = false;
diff --git a/llvm/test/Transforms/CorrelatedValuePropagation/add.ll b/llvm/test/Transforms/CorrelatedValuePropagation/add.ll
index 0768408563f5..b29a496ab1de 100644
--- a/llvm/test/Transforms/CorrelatedValuePropagation/add.ll
+++ b/llvm/test/Transforms/CorrelatedValuePropagation/add.ll
@@ -527,7 +527,6 @@ exit:
   ret i32 %acc.curr
 }
 
-; FIXME: This is a miscompile.
 define i32 @test_undef_range(i32 %x) {
 ; CHECK-LABEL: define i32 @test_undef_range(
 ; CHECK-SAME: i32 [[X:%.*]]) {
@@ -542,7 +541,7 @@ define i32 @test_undef_range(i32 %x) {
 ; CHECK-NEXT:    br label [[JOIN]]
 ; CHECK:       join:
 ; CHECK-NEXT:    [[PHI:%.*]] = phi i32 [ 1, [[CASE1]] ], [ 2, [[CASE2]] ], [ undef, [[ENTRY:%.*]] ]
-; CHECK-NEXT:    [[ADD:%.*]] = add nuw nsw i32 [[PHI]], 1
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[PHI]], 1
 ; CHECK-NEXT:    ret i32 [[ADD]]
 ;
 entry:
-- 
GitLab


From 1d56138d741ebec81ac7a6dada10f5d6b891a768 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Tue, 12 Dec 2023 10:31:54 +0000
Subject: [PATCH 263/349] [X86] X86FixupVectorConstants - create f32/f64
 broadcast constants if the source constant data was f32/f64

This partially reverts 33819f3bfb9c - the asm comments become a lot messier in #73509 - we're better off ensuring the constant data is the correct type in DAG
---
 llvm/lib/Target/X86/X86FixupVectorConstants.cpp | 8 ++++----
 llvm/test/CodeGen/X86/combine-concatvectors.ll  | 2 +-
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/llvm/lib/Target/X86/X86FixupVectorConstants.cpp b/llvm/lib/Target/X86/X86FixupVectorConstants.cpp
index 5cc3b26dddaf..483becebbe10 100644
--- a/llvm/lib/Target/X86/X86FixupVectorConstants.cpp
+++ b/llvm/lib/Target/X86/X86FixupVectorConstants.cpp
@@ -212,8 +212,8 @@ static Constant *rebuildSplatableConstant(const Constant *C,
     SmallVector<uint32_t> RawBits;
     for (unsigned I = 0; I != SplatBitWidth; I += 32)
       RawBits.push_back(Splat->extractBits(32, I).getZExtValue());
-    if (SclTy->isFloatingPointTy())
-      return ConstantDataVector::getFP(Type::getFloatTy(Ctx), RawBits);
+    if (SclTy->isFloatTy())
+      return ConstantDataVector::getFP(SclTy, RawBits);
     return ConstantDataVector::get(Ctx, RawBits);
   }
 
@@ -221,8 +221,8 @@ static Constant *rebuildSplatableConstant(const Constant *C,
   SmallVector<uint64_t> RawBits;
   for (unsigned I = 0; I != SplatBitWidth; I += 64)
     RawBits.push_back(Splat->extractBits(64, I).getZExtValue());
-  if (SclTy->isFloatingPointTy())
-    return ConstantDataVector::getFP(Type::getDoubleTy(Ctx), RawBits);
+  if (SclTy->isDoubleTy())
+    return ConstantDataVector::getFP(SclTy, RawBits);
   return ConstantDataVector::get(Ctx, RawBits);
 }
 
diff --git a/llvm/test/CodeGen/X86/combine-concatvectors.ll b/llvm/test/CodeGen/X86/combine-concatvectors.ll
index 31eaa1b205aa..8a0e39c57b78 100644
--- a/llvm/test/CodeGen/X86/combine-concatvectors.ll
+++ b/llvm/test/CodeGen/X86/combine-concatvectors.ll
@@ -48,7 +48,7 @@ define void @concat_of_broadcast_v2f64_v4f64() {
 ; AVX1-NEXT:    movl $1091567616, 30256(%rax) # imm = 0x41100000
 ; AVX1-NEXT:    movabsq $4294967297, %rcx # imm = 0x100000001
 ; AVX1-NEXT:    movq %rcx, 46348(%rax)
-; AVX1-NEXT:    vbroadcastss {{.*#+}} ymm0 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
+; AVX1-NEXT:    vbroadcastss {{.*#+}} ymm0 = [1065353216,1065353216,1065353216,1065353216,1065353216,1065353216,1065353216,1065353216]
 ; AVX1-NEXT:    vmovups %ymm0, 48296(%rax)
 ; AVX1-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX1-NEXT:    vmovsd %xmm0, 47372(%rax)
-- 
GitLab


From a97028ac511c2cda607a1e93c3b11d654cbdbf72 Mon Sep 17 00:00:00 2001
From: Mariusz Sikora <mariusz.sikora@amd.com>
Date: Tue, 12 Dec 2023 11:38:24 +0100
Subject: [PATCH 264/349] [AMDGPU] Update VOP instructions for GFX12 (#74853)

Co-authored-by: Mirko Brkusanin <Mirko.Brkusanin@amd.com>
---
 llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp    |     4 +
 .../AMDGPU/AsmParser/AMDGPUAsmParser.cpp      |    10 +-
 .../Disassembler/AMDGPUDisassembler.cpp       |    48 +-
 llvm/lib/Target/AMDGPU/GCNCreateVOPD.cpp      |     7 +-
 llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp       |     8 +-
 .../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp |    21 +
 llvm/lib/Target/AMDGPU/SIInstrInfo.cpp        |     4 +-
 llvm/lib/Target/AMDGPU/SIInstrInfo.td         |     4 +-
 .../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp    |    26 +-
 llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h |    19 +-
 llvm/lib/Target/AMDGPU/VOP1Instructions.td    |   410 +-
 llvm/lib/Target/AMDGPU/VOP2Instructions.td    |   659 +-
 llvm/lib/Target/AMDGPU/VOP3Instructions.td    |   248 +-
 llvm/lib/Target/AMDGPU/VOP3PInstructions.td   |   164 +-
 llvm/lib/Target/AMDGPU/VOPCInstructions.td    |   589 +-
 llvm/lib/Target/AMDGPU/VOPDInstructions.td    |   140 +-
 llvm/lib/Target/AMDGPU/VOPInstructions.td     |   399 +-
 .../CodeGen/AMDGPU/move-to-valu-lshlrev.mir   |    32 +
 .../test/CodeGen/AMDGPU/verify-vopd-gfx12.mir |    11 +
 llvm/test/CodeGen/AMDGPU/verify-vopd.mir      |     4 +-
 llvm/test/CodeGen/AMDGPU/vopd-combine.mir     |   319 +-
 .../CodeGen/AMDGPU/vopd-src2acc-delay.mir     |     8 +-
 llvm/test/MC/AMDGPU/gfx12_asm_vop1.s          |  3545 +++++
 llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp16.s    |  2816 ++++
 llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp8.s     |   605 +
 llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_err.s  |   505 +
 .../MC/AMDGPU/gfx12_asm_vop1_t16_promote.s    |  1480 ++
 llvm/test/MC/AMDGPU/gfx12_asm_vop2.s          |  2560 +++
 llvm/test/MC/AMDGPU/gfx12_asm_vop2_aliases.s  |    19 +
 llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s    |  2006 +++
 llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s     |   433 +
 llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_err.s  |   226 +
 .../MC/AMDGPU/gfx12_asm_vop2_t16_promote.s    |   190 +
 llvm/test/MC/AMDGPU/gfx12_asm_vop3.s          |  5983 ++++++++
 llvm/test/MC/AMDGPU/gfx12_asm_vop3_aliases.s  |    49 +
 llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s    |  4695 ++++++
 llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s     |  2968 ++++
 llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s      |     8 +
 .../test/MC/AMDGPU/gfx12_asm_vop3_from_vop1.s |  3508 +++++
 .../AMDGPU/gfx12_asm_vop3_from_vop1_dpp16.s   |  2689 ++++
 .../MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp8.s |   691 +
 .../test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s |  2268 +++
 .../AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s   |  1902 +++
 .../MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s |   526 +
 llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s         |  8695 +++++++++++
 llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16.s   |  5782 +++++++
 llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp8.s    |  2110 +++
 llvm/test/MC/AMDGPU/gfx12_asm_vop3cx.s        |  3413 ++++
 llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp16.s  |  2270 +++
 llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp8.s   |   572 +
 llvm/test/MC/AMDGPU/gfx12_asm_vop3p.s         |  1252 ++
 llvm/test/MC/AMDGPU/gfx12_asm_vop3p_aliases.s |     7 +
 llvm/test/MC/AMDGPU/gfx12_asm_vop3p_dpp16.s   |    14 +
 llvm/test/MC/AMDGPU/gfx12_asm_vop3p_dpp8.s    |    18 +
 .../test/MC/AMDGPU/gfx12_asm_vop3p_features.s |   143 +
 llvm/test/MC/AMDGPU/gfx12_asm_vopc.s          |  9076 +++++++++++
 llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp16.s    |  6052 ++++++++
 llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp8.s     |  1300 ++
 llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_err.s  |  1774 +++
 .../MC/AMDGPU/gfx12_asm_vopc_t16_promote.s    |  2368 +++
 llvm/test/MC/AMDGPU/gfx12_asm_vopcx.s         |  3404 ++++
 llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp16.s   |  2270 +++
 llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp8.s    |   488 +
 llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_err.s |   487 +
 .../MC/AMDGPU/gfx12_asm_vopcx_t16_promote.s   |   487 +
 llvm/test/MC/AMDGPU/gfx12_asm_vopd.s          | 12819 ++++++++++++++++
 llvm/test/MC/AMDGPU/gfx12_asm_vopd_errs.s     |   143 +
 llvm/test/MC/AMDGPU/gfx12_asm_vopd_features.s |   101 +
 .../Disassembler/AMDGPU/gfx12_dasm_vop1.txt   |  3302 ++++
 .../AMDGPU/gfx12_dasm_vop1_dpp16.txt          |  2606 ++++
 .../AMDGPU/gfx12_dasm_vop1_dpp8.txt           |   374 +
 .../Disassembler/AMDGPU/gfx12_dasm_vop2.txt   |  2228 +++
 .../AMDGPU/gfx12_dasm_vop2_dpp16.txt          |  1696 ++
 .../AMDGPU/gfx12_dasm_vop2_dpp8.txt           |   244 +
 .../Disassembler/AMDGPU/gfx12_dasm_vop3.txt   |  5497 +++++++
 .../AMDGPU/gfx12_dasm_vop3_dpp16.txt          |  4112 +++++
 .../AMDGPU/gfx12_dasm_vop3_dpp8.txt           |  2631 ++++
 .../AMDGPU/gfx12_dasm_vop3_from_vop1.txt      |  3277 ++++
 .../gfx12_dasm_vop3_from_vop1_dpp16.txt       |  2479 +++
 .../AMDGPU/gfx12_dasm_vop3_from_vop1_dpp8.txt |   583 +
 .../AMDGPU/gfx12_dasm_vop3_from_vop2.txt      |  1968 +++
 .../gfx12_dasm_vop3_from_vop2_dpp16.txt       |  1608 ++
 .../AMDGPU/gfx12_dasm_vop3_from_vop2_dpp8.txt |   366 +
 .../Disassembler/AMDGPU/gfx12_dasm_vop3c.txt  |  4469 ++++++
 .../AMDGPU/gfx12_dasm_vop3c_dpp16.txt         |  2972 ++++
 .../AMDGPU/gfx12_dasm_vop3c_dpp8.txt          |  1028 ++
 .../Disassembler/AMDGPU/gfx12_dasm_vop3cx.txt |  3413 ++++
 .../AMDGPU/gfx12_dasm_vop3cx_dpp16.txt        |  2278 +++
 .../AMDGPU/gfx12_dasm_vop3cx_dpp8.txt         |   502 +
 .../Disassembler/AMDGPU/gfx12_dasm_vop3p.txt  |  1253 ++
 .../AMDGPU/gfx12_dasm_vop3p_dpp16.txt         |    14 +
 .../AMDGPU/gfx12_dasm_vop3p_dpp8.txt          |    17 +
 .../AMDGPU/gfx12_dasm_vop3p_err.txt           |   144 +
 .../Disassembler/AMDGPU/gfx12_dasm_vopc.txt   |  4538 ++++++
 .../AMDGPU/gfx12_dasm_vopc_dpp16.txt          |  3026 ++++
 .../AMDGPU/gfx12_dasm_vopc_dpp8.txt           |   434 +
 .../Disassembler/AMDGPU/gfx12_dasm_vopcx.txt  |  3404 ++++
 .../AMDGPU/gfx12_dasm_vopcx_dpp16.txt         |  2270 +++
 .../AMDGPU/gfx12_dasm_vopcx_dpp8.txt          |   326 +
 .../Disassembler/AMDGPU/gfx12_dasm_vopd.txt   |  9613 ++++++++++++
 .../AMDGPU/gfx12_dasm_vopd_features.txt       |    23 +
 101 files changed, 179367 insertions(+), 1179 deletions(-)
 create mode 100644 llvm/test/CodeGen/AMDGPU/move-to-valu-lshlrev.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/verify-vopd-gfx12.mir
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop1.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp16.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp8.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_err.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_promote.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop2.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop2_aliases.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_err.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop3_aliases.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp16.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp8.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp8.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop3cx.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp16.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp8.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop3p.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop3p_aliases.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop3p_dpp16.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop3p_dpp8.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vop3p_features.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vopc.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp16.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp8.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_err.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vopcx.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp16.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp8.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_err.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_promote.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vopd.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vopd_errs.s
 create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_vopd_features.s
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp16.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp8.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp16.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp8.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp16.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp8.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2_dpp16.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2_dpp8.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp16.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp8.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp16.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp8.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p_dpp16.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p_dpp8.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p_err.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp16.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp8.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp16.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp8.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopd.txt
 create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopd_features.txt

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
index 3c9f9cfd834f..f19c57668564 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
@@ -201,14 +201,18 @@ unsigned GCNSubtarget::getConstantBusLimit(unsigned Opcode) const {
   case AMDGPU::V_LSHLREV_B64_e64:
   case AMDGPU::V_LSHLREV_B64_gfx10:
   case AMDGPU::V_LSHLREV_B64_e64_gfx11:
+  case AMDGPU::V_LSHLREV_B64_e32_gfx12:
+  case AMDGPU::V_LSHLREV_B64_e64_gfx12:
   case AMDGPU::V_LSHL_B64_e64:
   case AMDGPU::V_LSHRREV_B64_e64:
   case AMDGPU::V_LSHRREV_B64_gfx10:
   case AMDGPU::V_LSHRREV_B64_e64_gfx11:
+  case AMDGPU::V_LSHRREV_B64_e64_gfx12:
   case AMDGPU::V_LSHR_B64_e64:
   case AMDGPU::V_ASHRREV_I64_e64:
   case AMDGPU::V_ASHRREV_I64_gfx10:
   case AMDGPU::V_ASHRREV_I64_e64_gfx11:
+  case AMDGPU::V_ASHRREV_I64_e64_gfx12:
   case AMDGPU::V_ASHR_I64_e64:
     return 1;
   }
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index ed93948868da..92427335c0ad 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -3411,12 +3411,16 @@ unsigned AMDGPUAsmParser::getConstantBusLimit(unsigned Opcode) const {
   case AMDGPU::V_LSHLREV_B64_e64:
   case AMDGPU::V_LSHLREV_B64_gfx10:
   case AMDGPU::V_LSHLREV_B64_e64_gfx11:
+  case AMDGPU::V_LSHLREV_B64_e32_gfx12:
+  case AMDGPU::V_LSHLREV_B64_e64_gfx12:
   case AMDGPU::V_LSHRREV_B64_e64:
   case AMDGPU::V_LSHRREV_B64_gfx10:
   case AMDGPU::V_LSHRREV_B64_e64_gfx11:
+  case AMDGPU::V_LSHRREV_B64_e64_gfx12:
   case AMDGPU::V_ASHRREV_I64_e64:
   case AMDGPU::V_ASHRREV_I64_gfx10:
   case AMDGPU::V_ASHRREV_I64_e64_gfx11:
+  case AMDGPU::V_ASHRREV_I64_e64_gfx12:
   case AMDGPU::V_LSHL_B64_e64:
   case AMDGPU::V_LSHR_B64_e64:
   case AMDGPU::V_ASHR_I64_e64:
@@ -3571,8 +3575,12 @@ bool AMDGPUAsmParser::validateVOPDRegBankConstraints(
                : MCRegister::NoRegister;
   };
 
+  // On GFX12 if both OpX and OpY are V_MOV_B32 then OPY uses SRC2 source-cache.
+  bool SkipSrc = Opcode == AMDGPU::V_DUAL_MOV_B32_e32_X_MOV_B32_e32_gfx12;
+
   const auto &InstInfo = getVOPDInstInfo(Opcode, &MII);
-  auto InvalidCompOprIdx = InstInfo.getInvalidCompOperandIndex(getVRegIdx);
+  auto InvalidCompOprIdx =
+      InstInfo.getInvalidCompOperandIndex(getVRegIdx, SkipSrc);
   if (!InvalidCompOprIdx)
     return true;
 
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index f0ba870b6619..ed019d26c1df 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -493,17 +493,33 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
       if (Res && convertDPP8Inst(MI) == MCDisassembler::Success)
         break;
       MI = MCInst(); // clear
-      Res = tryDecodeInst(DecoderTableDPPGFX1196, DecoderTableDPPGFX11_FAKE1696,
-                          MI, DecW, Address, CS);
-      if (Res) {
-        if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P)
+      Res =
+          tryDecodeInst(DecoderTableDPP8GFX1296, DecoderTableDPP8GFX12_FAKE1696,
+                        MI, DecW, Address, CS);
+      if (Res && convertDPP8Inst(MI) == MCDisassembler::Success)
+        break;
+      MI = MCInst(); // clear
+
+      const auto convertVOPDPP = [&]() {
+        if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) {
           convertVOP3PDPPInst(MI);
-        else if (AMDGPU::isVOPC64DPP(MI.getOpcode()))
+        } else if (AMDGPU::isVOPC64DPP(MI.getOpcode())) {
           convertVOPCDPPInst(MI); // Special VOP3 case
-        else {
+        } else {
           assert(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3);
           convertVOP3DPPInst(MI); // Regular VOP3 case
         }
+      };
+      Res = tryDecodeInst(DecoderTableDPPGFX1196, DecoderTableDPPGFX11_FAKE1696,
+                          MI, DecW, Address, CS);
+      if (Res) {
+        convertVOPDPP();
+        break;
+      }
+      Res = tryDecodeInst(DecoderTableDPPGFX1296, DecoderTableDPPGFX12_FAKE1696,
+                          MI, DecW, Address, CS);
+      if (Res) {
+        convertVOPDPP();
         break;
       }
       Res = tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address, CS);
@@ -543,6 +559,12 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
         break;
       MI = MCInst(); // clear
 
+      Res = tryDecodeInst(DecoderTableDPP8GFX1264,
+                          DecoderTableDPP8GFX12_FAKE1664, MI, QW, Address, CS);
+      if (Res && convertDPP8Inst(MI) == MCDisassembler::Success)
+        break;
+      MI = MCInst(); // clear
+
       Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address, CS);
       if (Res) break;
 
@@ -554,6 +576,14 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
         break;
       }
 
+      Res = tryDecodeInst(DecoderTableDPPGFX1264, DecoderTableDPPGFX12_FAKE1664,
+                          MI, QW, Address, CS);
+      if (Res) {
+        if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC)
+          convertVOPCDPPInst(MI);
+        break;
+      }
+
       Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address, CS);
       if (Res) { IsSDWA = true;  break; }
 
@@ -612,7 +642,8 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
                         Address, CS);
     if (Res) break;
 
-    Res = tryDecodeInst(DecoderTableGFX1232, MI, DW, Address, CS);
+    Res = tryDecodeInst(DecoderTableGFX1232, DecoderTableGFX12_FAKE1632, MI, DW,
+                        Address, CS);
     if (Res)
       break;
 
@@ -643,7 +674,8 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
     Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address, CS);
     if (Res) break;
 
-    Res = tryDecodeInst(DecoderTableGFX1264, MI, QW, Address, CS);
+    Res = tryDecodeInst(DecoderTableGFX1264, DecoderTableGFX12_FAKE1664, MI, QW,
+                        Address, CS);
     if (Res)
       break;
 
diff --git a/llvm/lib/Target/AMDGPU/GCNCreateVOPD.cpp b/llvm/lib/Target/AMDGPU/GCNCreateVOPD.cpp
index 982367f8f934..05e10a95b157 100644
--- a/llvm/lib/Target/AMDGPU/GCNCreateVOPD.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNCreateVOPD.cpp
@@ -71,8 +71,11 @@ public:
     auto *SecondMI = CI.SecondMI;
     unsigned Opc1 = FirstMI->getOpcode();
     unsigned Opc2 = SecondMI->getOpcode();
-    int NewOpcode = AMDGPU::getVOPDFull(AMDGPU::getVOPDOpcode(Opc1),
-                                        AMDGPU::getVOPDOpcode(Opc2));
+    unsigned EncodingFamily =
+        AMDGPU::getVOPDEncodingFamily(SII->getSubtarget());
+    int NewOpcode =
+        AMDGPU::getVOPDFull(AMDGPU::getVOPDOpcode(Opc1),
+                            AMDGPU::getVOPDOpcode(Opc2), EncodingFamily);
     assert(NewOpcode != -1 &&
            "Should have previously determined this as a possible VOPD\n");
 
diff --git a/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp b/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
index 0bddeeef9e9b..33c208495c50 100644
--- a/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
@@ -103,7 +103,13 @@ bool llvm::checkVOPDRegConstraints(const SIInstrInfo &TII,
     return false;
   if ((UniqueLiterals.size() + UniqueScalarRegs.size()) > 2)
     return false;
-  if (InstInfo.hasInvalidOperand(getVRegIdx))
+
+  // On GFX12 if both OpX and OpY are V_MOV_B32 then OPY uses SRC2 source-cache.
+  bool SkipSrc = ST.getGeneration() >= AMDGPUSubtarget::GFX12 &&
+                 FirstMI.getOpcode() == AMDGPU::V_MOV_B32_e32 &&
+                 SecondMI.getOpcode() == AMDGPU::V_MOV_B32_e32;
+
+  if (InstInfo.hasInvalidOperand(getVRegIdx, SkipSrc))
     return false;
 
   LLVM_DEBUG(dbgs() << "VOPD Reg Constraints Passed\n\tX: " << FirstMI
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index 7ba015cdea24..57f74ae08b35 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -416,6 +416,15 @@ void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
+  case AMDGPU::V_ADD_CO_CI_U32_e32_gfx12:
+  case AMDGPU::V_SUB_CO_CI_U32_e32_gfx12:
+  case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx12:
+  case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx12:
+  case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx12:
+  case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx12:
+  case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx12:
+  case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx12:
+  case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx12:
     printDefaultVccOperand(false, STI, O);
     break;
   }
@@ -807,6 +816,18 @@ void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
+  case AMDGPU::V_CNDMASK_B32_e32_gfx12:
+  case AMDGPU::V_ADD_CO_CI_U32_e32_gfx12:
+  case AMDGPU::V_SUB_CO_CI_U32_e32_gfx12:
+  case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx12:
+  case AMDGPU::V_CNDMASK_B32_dpp_gfx12:
+  case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx12:
+  case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx12:
+  case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx12:
+  case AMDGPU::V_CNDMASK_B32_dpp8_gfx12:
+  case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx12:
+  case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx12:
+  case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx12:
 
   case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
   case AMDGPU::V_CNDMASK_B32_e32_vi:
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 0a06fa88b6b1..dda54a0929c1 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -6869,7 +6869,9 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist,
     break;
   case AMDGPU::S_LSHL_B64:
     if (ST.hasOnlyRevVALUShifts()) {
-      NewOpcode = AMDGPU::V_LSHLREV_B64_e64;
+      NewOpcode = ST.getGeneration() >= AMDGPUSubtarget::GFX12
+                      ? AMDGPU::V_LSHLREV_B64_pseudo_e64
+                      : AMDGPU::V_LSHLREV_B64_e64;
       swapOperands(Inst);
     }
     break;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 091b40eefa55..9e60bdda5ef3 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -2898,14 +2898,14 @@ def getVOPDBaseFromComponent : SearchIndex {
 def VOPDPairs : GenericTable {
   let FilterClass = "VOPD_Base";
   let CppTypeName = "VOPDInfo";
-  let Fields = ["Opcode", "OpX", "OpY"];
+  let Fields = ["Opcode", "OpX", "OpY", "SubTgt"];
   let PrimaryKey = ["Opcode"];
   let PrimaryKeyName = "getVOPDOpcodeHelper";
 }
 
 def getVOPDInfoFromComponentOpcodes : SearchIndex {
   let Table = VOPDPairs;
-  let Key = ["OpX", "OpY"];
+  let Key = ["OpX", "OpY", "SubTgt"];
 }
 
 include "SIInstructions.td"
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 8faa9e5f6d30..ede70c3f3404 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -309,6 +309,7 @@ struct VOPDInfo {
   uint16_t Opcode;
   uint16_t OpX;
   uint16_t OpY;
+  uint16_t Subtarget;
 };
 
 struct VOPTrue16Info {
@@ -443,6 +444,14 @@ bool getMAIIsGFX940XDL(unsigned Opc) {
   return Info ? Info->is_gfx940_xdl : false;
 }
 
+unsigned getVOPDEncodingFamily(const MCSubtargetInfo &ST) {
+  if (ST.hasFeature(AMDGPU::FeatureGFX12Insts))
+    return SIEncodingFamily::GFX12;
+  if (ST.hasFeature(AMDGPU::FeatureGFX11Insts))
+    return SIEncodingFamily::GFX11;
+  llvm_unreachable("Subtarget generation does not support VOPD!");
+}
+
 CanBeVOPD getCanBeVOPD(unsigned Opc) {
   const VOPDComponentInfo *Info = getVOPDComponentHelper(Opc);
   if (Info)
@@ -470,11 +479,13 @@ bool isMAC(unsigned Opc) {
          Opc == AMDGPU::V_FMAC_F64_e64_gfx90a ||
          Opc == AMDGPU::V_FMAC_F32_e64_gfx10 ||
          Opc == AMDGPU::V_FMAC_F32_e64_gfx11 ||
+         Opc == AMDGPU::V_FMAC_F32_e64_gfx12 ||
          Opc == AMDGPU::V_FMAC_F32_e64_vi ||
          Opc == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 ||
          Opc == AMDGPU::V_FMAC_DX9_ZERO_F32_e64_gfx11 ||
          Opc == AMDGPU::V_FMAC_F16_e64_gfx10 ||
          Opc == AMDGPU::V_FMAC_F16_t16_e64_gfx11 ||
+         Opc == AMDGPU::V_FMAC_F16_t16_e64_gfx12 ||
          Opc == AMDGPU::V_DOT2C_F32_F16_e64_vi ||
          Opc == AMDGPU::V_DOT2C_I32_I16_e64_vi ||
          Opc == AMDGPU::V_DOT4C_I32_I8_e64_vi ||
@@ -485,7 +496,9 @@ bool isPermlane16(unsigned Opc) {
   return Opc == AMDGPU::V_PERMLANE16_B32_gfx10 ||
          Opc == AMDGPU::V_PERMLANEX16_B32_gfx10 ||
          Opc == AMDGPU::V_PERMLANE16_B32_e64_gfx11 ||
-         Opc == AMDGPU::V_PERMLANEX16_B32_e64_gfx11;
+         Opc == AMDGPU::V_PERMLANEX16_B32_e64_gfx11 ||
+         Opc == AMDGPU::V_PERMLANE16_B32_e64_gfx12 ||
+         Opc == AMDGPU::V_PERMLANEX16_B32_e64_gfx12;
 }
 
 bool isGenericAtomic(unsigned Opc) {
@@ -532,8 +545,9 @@ int getMCOpcode(uint16_t Opcode, unsigned Gen) {
   return getMCOpcodeGen(Opcode, static_cast<Subtarget>(Gen));
 }
 
-int getVOPDFull(unsigned OpX, unsigned OpY) {
-  const VOPDInfo *Info = getVOPDInfoFromComponentOpcodes(OpX, OpY);
+int getVOPDFull(unsigned OpX, unsigned OpY, unsigned EncodingFamily) {
+  const VOPDInfo *Info =
+      getVOPDInfoFromComponentOpcodes(OpX, OpY, EncodingFamily);
   return Info ? Info->Opcode : -1;
 }
 
@@ -585,13 +599,15 @@ unsigned ComponentInfo::getIndexInParsedOperands(unsigned CompOprIdx) const {
 }
 
 std::optional<unsigned> InstInfo::getInvalidCompOperandIndex(
-    std::function<unsigned(unsigned, unsigned)> GetRegIdx) const {
+    std::function<unsigned(unsigned, unsigned)> GetRegIdx, bool SkipSrc) const {
 
   auto OpXRegs = getRegIndices(ComponentIndex::X, GetRegIdx);
   auto OpYRegs = getRegIndices(ComponentIndex::Y, GetRegIdx);
 
+  const unsigned CompOprNum =
+      SkipSrc ? Component::DST_NUM : Component::MAX_OPR_NUM;
   unsigned CompOprIdx;
-  for (CompOprIdx = 0; CompOprIdx < Component::MAX_OPR_NUM; ++CompOprIdx) {
+  for (CompOprIdx = 0; CompOprIdx < CompOprNum; ++CompOprIdx) {
     unsigned BanksMasks = VOPD_VGPR_BANK_MASKS[CompOprIdx];
     if (OpXRegs[CompOprIdx] && OpYRegs[CompOprIdx] &&
         ((OpXRegs[CompOprIdx] & BanksMasks) ==
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index 436a0ff5ce26..bd333ed2cca7 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -505,6 +505,10 @@ struct CanBeVOPD {
   bool Y;
 };
 
+/// \returns SIEncodingFamily used for VOPD encoding on a \p ST.
+LLVM_READONLY
+unsigned getVOPDEncodingFamily(const MCSubtargetInfo &ST);
+
 LLVM_READONLY
 CanBeVOPD getCanBeVOPD(unsigned Opc);
 
@@ -524,7 +528,7 @@ LLVM_READONLY
 unsigned getVOPDOpcode(unsigned Opc);
 
 LLVM_READONLY
-int getVOPDFull(unsigned OpX, unsigned OpY);
+int getVOPDFull(unsigned OpX, unsigned OpY, unsigned EncodingFamily);
 
 LLVM_READONLY
 bool isVOPD(unsigned Opc);
@@ -747,15 +751,20 @@ public:
   // GetRegIdx(Component, MCOperandIdx) must return a VGPR register index
   // for the specified component and MC operand. The callback must return 0
   // if the operand is not a register or not a VGPR.
-  bool hasInvalidOperand(
-      std::function<unsigned(unsigned, unsigned)> GetRegIdx) const {
-    return getInvalidCompOperandIndex(GetRegIdx).has_value();
+  // If \p SkipSrc is set to true then constraints for source operands are not
+  // checked.
+  bool hasInvalidOperand(std::function<unsigned(unsigned, unsigned)> GetRegIdx,
+                         bool SkipSrc = false) const {
+    return getInvalidCompOperandIndex(GetRegIdx, SkipSrc).has_value();
   }
 
   // Check VOPD operands constraints.
   // Return the index of an invalid component operand, if any.
+  // If \p SkipSrc is set to true then constraints for source operands are not
+  // checked.
   std::optional<unsigned> getInvalidCompOperandIndex(
-      std::function<unsigned(unsigned, unsigned)> GetRegIdx) const;
+      std::function<unsigned(unsigned, unsigned)> GetRegIdx,
+      bool SkipSrc = false) const;
 
 private:
   RegIndices
diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
index 53b0513c85d8..27a7c29cb1ac 100644
--- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -88,6 +88,12 @@ class VOP1_Real <VOP1_Pseudo ps, int EncodingFamily, string real_name = ps.Mnemo
   let TRANS                = ps.TRANS;
 }
 
+class VOP1_Real_Gen <VOP1_Pseudo ps, GFXGen Gen, string real_name = ps.Mnemonic> :
+  VOP1_Real <ps, Gen.Subtarget, real_name> {
+  let AssemblerPredicate = Gen.AssemblerPredicate;
+  let DecoderNamespace = Gen.DecoderNamespace;
+}
+
 class VOP1_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
   VOP_SDWA_Pseudo <OpName, P, pattern> {
   let AsmMatchConverter = "cvtSdwaVOP1";
@@ -688,6 +694,13 @@ class VOP1_DPP16<bits<8> op, VOP1_DPP_Pseudo ps, int subtarget, VOPProfile p = p
   let SubtargetPredicate = HasDPP16;
 }
 
+class VOP1_DPP16_Gen<bits<8> op, VOP1_DPP_Pseudo ps, GFXGen Gen, VOPProfile p = ps.Pfl> :
+    VOP1_DPP16 <op, ps, Gen.Subtarget, p> {
+  let AssemblerPredicate = Gen.AssemblerPredicate;
+  let DecoderNamespace = "DPP"#Gen.DecoderNamespace;
+}
+
+
 class VOP1_DPP8<bits<8> op, VOP1_Pseudo ps, VOPProfile p = ps.Pfl> :
     VOP_DPP8<ps.OpName, p> {
   let hasSideEffects = ps.hasSideEffects;
@@ -702,138 +715,173 @@ class VOP1_DPP8<bits<8> op, VOP1_Pseudo ps, VOPProfile p = ps.Pfl> :
   let Inst{31-25} = 0x3f;
 }
 
+class VOP1_DPP8_Gen<bits<8> op, VOP1_Pseudo ps, GFXGen Gen, VOPProfile p = ps.Pfl> :
+    VOP1_DPP8<op, ps, p> {
+  let AssemblerPredicate = Gen.AssemblerPredicate;
+  let DecoderNamespace = "DPP8"#Gen.DecoderNamespace;
+}
+
 //===----------------------------------------------------------------------===//
-// GFX11.
+// GFX11, GFX12
 //===----------------------------------------------------------------------===//
 
-let AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11" in {
-  multiclass VOP1Only_Real_gfx11<bits<9> op> {
-    let IsSingle = 1 in
-      def _gfx11 :
-        VOP1_Real<!cast<VOP1_Pseudo>(NAME), SIEncodingFamily.GFX11>,
-        VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME).Pfl>;
-  }
-  multiclass VOP1_Real_e32_gfx11<bits<9> op, string opName = NAME> {
-    defvar ps = !cast<VOP1_Pseudo>(opName#"_e32");
-    def _e32_gfx11 :
-      VOP1_Real<ps, SIEncodingFamily.GFX11>,
-      VOP1e<op{7-0}, ps.Pfl>;
-  }
-  multiclass VOP1_Real_e32_with_name_gfx11<bits<9> op, string opName,
-                                       string asmName> {
-    defvar ps = !cast<VOP1_Pseudo>(opName#"_e32");
-    let AsmString = asmName # ps.AsmOperands in {
-      defm NAME : VOP1_Real_e32_gfx11<op, opName>;
-    }
-  }
-  multiclass VOP1_Real_e64_gfx11<bits<9> op> {
-    def _e64_gfx11 :
-      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX11>,
-      VOP3e_gfx11<{0, 1, 1, op{6-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
-  }
-  multiclass VOP1_Real_dpp_gfx11<bits<9> op, string opName = NAME> {
-    defvar ps = !cast<VOP1_Pseudo>(opName#"_e32");
-    def _dpp_gfx11 : VOP1_DPP16<op{7-0}, !cast<VOP1_DPP_Pseudo>(opName#"_dpp"), SIEncodingFamily.GFX11> {
-      let DecoderNamespace = "DPPGFX11";
-    }
-  }
-  multiclass VOP1_Real_dpp_with_name_gfx11<bits<9> op, string opName,
-                                           string asmName> {
-    defvar ps = !cast<VOP1_Pseudo>(opName#"_e32");
-    let AsmString = asmName # ps.Pfl.AsmDPP16, DecoderNamespace = "DPPGFX11" in {
-      defm NAME : VOP1_Real_dpp_gfx11<op, opName>;
-    }
+multiclass VOP1Only_Real<GFXGen Gen, bits<9> op> {
+  let IsSingle = 1 in
+    def Gen.Suffix :
+      VOP1_Real_Gen<!cast<VOP1_Pseudo>(NAME), Gen>,
+      VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME).Pfl>;
+}
+
+multiclass VOP1_Real_e32<GFXGen Gen, bits<9> op, string opName = NAME> {
+  defvar ps = !cast<VOP1_Pseudo>(opName#"_e32");
+  def _e32#Gen.Suffix :
+    VOP1_Real_Gen<ps, Gen>,
+    VOP1e<op{7-0}, ps.Pfl>;
+}
+
+multiclass VOP1_Real_e32_with_name<GFXGen Gen, bits<9> op, string opName,
+                                   string asmName> {
+  defvar ps = !cast<VOP1_Pseudo>(opName#"_e32");
+  let AsmString = asmName # ps.AsmOperands in {
+    defm NAME : VOP1_Real_e32<Gen, op, opName>;
   }
-  multiclass VOP1_Real_dpp8_gfx11<bits<9> op, string opName = NAME> {
-    defvar ps = !cast<VOP1_Pseudo>(opName#"_e32");
-    def _dpp8_gfx11 : VOP1_DPP8<op{7-0}, ps> {
-      let DecoderNamespace = "DPP8GFX11";
-    }
+}
+
+multiclass VOP1_Real_e64<GFXGen Gen, bits<9> op> {
+  def _e64#Gen.Suffix :
+    VOP3_Real_Gen<!cast<VOP3_Pseudo>(NAME#"_e64"), Gen>,
+    VOP3e_gfx11_gfx12<{0, 1, 1, op{6-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
+}
+
+multiclass VOP1_Real_dpp<GFXGen Gen, bits<9> op, string opName = NAME> {
+  defvar ps = !cast<VOP1_Pseudo>(opName#"_e32");
+  def _dpp#Gen.Suffix : VOP1_DPP16_Gen<op{7-0}, !cast<VOP1_DPP_Pseudo>(opName#"_dpp"), Gen>;
+}
+
+multiclass VOP1_Real_dpp_with_name<GFXGen Gen, bits<9> op, string opName,
+                                   string asmName> {
+  defvar ps = !cast<VOP1_Pseudo>(opName#"_e32");
+  let AsmString = asmName # ps.Pfl.AsmDPP16 in {
+    defm NAME : VOP1_Real_dpp<Gen, op, opName>;
   }
-  multiclass VOP1_Real_dpp8_with_name_gfx11<bits<9> op, string opName,
-                                           string asmName> {
-    defvar ps = !cast<VOP1_Pseudo>(opName#"_e32");
-    let AsmString = asmName # ps.Pfl.AsmDPP8, DecoderNamespace = "DPP8GFX11" in {
-      defm NAME : VOP1_Real_dpp8_gfx11<op, opName>;
-    }
+}
+
+multiclass VOP1_Real_dpp8<GFXGen Gen, bits<9> op, string opName = NAME> {
+  defvar ps = !cast<VOP1_Pseudo>(opName#"_e32");
+  def _dpp8#Gen.Suffix : VOP1_DPP8_Gen<op{7-0}, ps, Gen>;
+}
+
+multiclass VOP1_Real_dpp8_with_name<GFXGen Gen, bits<9> op, string opName,
+                                    string asmName> {
+  defvar ps = !cast<VOP1_Pseudo>(opName#"_e32");
+  let AsmString = asmName # ps.Pfl.AsmDPP8 in {
+    defm NAME : VOP1_Real_dpp8<Gen, op, opName>;
   }
-} // End AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11"
+}
 
-multiclass VOP1_Realtriple_e64_gfx11<bits<9> op> {
-  defm NAME : VOP3_Realtriple_gfx11<{0, 1, 1, op{6-0}}, /*isSingle=*/ 0, NAME>;
+multiclass VOP1_Realtriple_e64<GFXGen Gen, bits<9> op> {
+  defm NAME : VOP3_Realtriple<Gen, {0, 1, 1, op{6-0}}, /*isSingle=*/ 0, NAME>;
 }
-multiclass VOP1_Realtriple_e64_with_name_gfx11<bits<9> op, string opName,
+
+multiclass VOP1_Realtriple_e64_with_name<GFXGen Gen, bits<9> op, string opName,
   string asmName> {
-  defm NAME : VOP3_Realtriple_with_name_gfx11<{0, 1, 1, op{6-0}}, opName,
+  defm NAME : VOP3_Realtriple_with_name<Gen, {0, 1, 1, op{6-0}}, opName,
     asmName>;
 }
 
-multiclass VOP1_Real_FULL_gfx11<bits<9> op> :
-  VOP1_Real_e32_gfx11<op>, VOP1_Realtriple_e64_gfx11<op>,
-  VOP1_Real_dpp_gfx11<op>, VOP1_Real_dpp8_gfx11<op>;
+multiclass VOP1_Real_FULL<GFXGen Gen, bits<9> op> :
+  VOP1_Real_e32<Gen, op>, VOP1_Realtriple_e64<Gen, op>,
+  VOP1_Real_dpp<Gen, op>, VOP1_Real_dpp8<Gen, op>;
 
 multiclass VOP1_Real_NO_VOP3_with_name_gfx11<bits<9> op, string opName,
-                                           string asmName> {
-  defm NAME : VOP1_Real_e32_with_name_gfx11<op, opName, asmName>,
-              VOP1_Real_dpp_with_name_gfx11<op, opName, asmName>,
-              VOP1_Real_dpp8_with_name_gfx11<op, opName, asmName>;
+                                             string asmName> {
+  defm NAME : VOP1_Real_e32_with_name<GFX11Gen, op, opName, asmName>,
+              VOP1_Real_dpp_with_name<GFX11Gen, op, opName, asmName>,
+              VOP1_Real_dpp8_with_name<GFX11Gen, op, opName, asmName>;
   defvar ps = !cast<VOP1_Pseudo>(opName#"_e32");
   def gfx11_alias : MnemonicAlias<ps.Mnemonic, asmName>,
                     Requires<[isGFX11Plus]>;
 }
 
-multiclass VOP1_Real_FULL_with_name_gfx11<bits<9> op, string opName,
+multiclass VOP1_Real_NO_VOP3_with_name_gfx12<bits<9> op, string opName,
+                                             string asmName> {
+  defm NAME : VOP1_Real_e32_with_name<GFX12Gen, op, opName, asmName>,
+              VOP1_Real_dpp_with_name<GFX12Gen, op, opName, asmName>,
+              VOP1_Real_dpp8_with_name<GFX12Gen, op, opName, asmName>;
+}
+
+multiclass VOP1_Real_FULL_with_name<GFXGen Gen, bits<9> op, string opName,
                                          string asmName> :
-  VOP1_Real_NO_VOP3_with_name_gfx11<op, opName, asmName>,
-  VOP1_Realtriple_e64_with_name_gfx11<op, opName, asmName>;
+  VOP1_Real_e32_with_name<Gen, op, opName, asmName>,
+  VOP1_Real_dpp_with_name<Gen, op, opName, asmName>,
+  VOP1_Real_dpp8_with_name<Gen, op, opName, asmName>,
+  VOP1_Realtriple_e64_with_name<Gen, op, opName, asmName>;
 
-multiclass VOP1_Real_FULL_t16_gfx11<bits<9> op, string asmName,
-                                    string opName = NAME> :
-  VOP1_Real_FULL_with_name_gfx11<op, opName, asmName>;
+multiclass VOP1_Real_NO_DPP<GFXGen Gen, bits<9> op> :
+  VOP1_Real_e32<Gen, op>, VOP1_Real_e64<Gen, op>;
 
-multiclass VOP1_Real_NO_DPP_gfx11<bits<9> op> :
-  VOP1_Real_e32_gfx11<op>, VOP1_Real_e64_gfx11<op>;
+multiclass VOP1_Real_FULL_t16_gfx11_gfx12<bits<9> op, string asmName,
+                                          string opName = NAME> :
+  VOP1_Real_FULL_with_name<GFX11Gen, op, opName, asmName>,
+  VOP1_Real_FULL_with_name<GFX12Gen, op, opName, asmName>;
 
-defm V_CVT_NEAREST_I32_F32 : VOP1_Real_FULL_with_name_gfx11<0x00c,
+multiclass VOP1_Real_FULL_with_name_gfx11_gfx12<bits<9> op, string opName,
+                                                string asmName> :
+  VOP1_Real_FULL_with_name<GFX11Gen, op, opName, asmName>,
+  VOP1_Real_FULL_with_name<GFX12Gen, op, opName, asmName>;
+
+multiclass VOP1Only_Real_gfx11_gfx12<bits<9> op> :
+  VOP1Only_Real<GFX11Gen, op>, VOP1Only_Real<GFX12Gen, op>;
+
+multiclass VOP1_Real_FULL_gfx11_gfx12<bits<9> op> :
+  VOP1_Real_FULL<GFX11Gen, op>, VOP1_Real_FULL<GFX12Gen, op>;
+
+multiclass VOP1_Real_NO_DPP_OP_SEL_with_name<GFXGen Gen, bits<9> op,
+                                             string opName, string asmName> :
+  VOP1_Real_e32_with_name<Gen, op, opName, asmName>,
+  VOP3_Real_with_name<Gen, {0, 1, 1, op{6-0}}, opName, asmName>;
+
+
+defm V_CVT_NEAREST_I32_F32 : VOP1_Real_FULL_with_name_gfx11_gfx12<0x00c,
   "V_CVT_RPI_I32_F32", "v_cvt_nearest_i32_f32">;
-defm V_CVT_FLOOR_I32_F32   : VOP1_Real_FULL_with_name_gfx11<0x00d,
+defm V_CVT_FLOOR_I32_F32   : VOP1_Real_FULL_with_name_gfx11_gfx12<0x00d,
   "V_CVT_FLR_I32_F32", "v_cvt_floor_i32_f32">;
-defm V_CLZ_I32_U32         : VOP1_Real_FULL_with_name_gfx11<0x039,
+defm V_CLZ_I32_U32         : VOP1_Real_FULL_with_name_gfx11_gfx12<0x039,
   "V_FFBH_U32", "v_clz_i32_u32">;
-defm V_CTZ_I32_B32         : VOP1_Real_FULL_with_name_gfx11<0x03a,
+defm V_CTZ_I32_B32         : VOP1_Real_FULL_with_name_gfx11_gfx12<0x03a,
   "V_FFBL_B32", "v_ctz_i32_b32">;
-defm V_CLS_I32             : VOP1_Real_FULL_with_name_gfx11<0x03b,
+defm V_CLS_I32             : VOP1_Real_FULL_with_name_gfx11_gfx12<0x03b,
   "V_FFBH_I32", "v_cls_i32">;
-defm V_PERMLANE64_B32      : VOP1Only_Real_gfx11<0x067>;
-defm V_MOV_B16_t16           : VOP1_Real_FULL_t16_gfx11<0x01c, "v_mov_b16">;
-defm V_NOT_B16_t16           : VOP1_Real_FULL_t16_gfx11<0x069, "v_not_b16">;
-defm V_CVT_I32_I16_t16       : VOP1_Real_FULL_t16_gfx11<0x06a, "v_cvt_i32_i16">;
-defm V_CVT_U32_U16_t16       : VOP1_Real_FULL_t16_gfx11<0x06b, "v_cvt_u32_u16">;
-
-defm V_CVT_F16_U16_t16       : VOP1_Real_FULL_t16_gfx11<0x050, "v_cvt_f16_u16">;
-defm V_CVT_F16_I16_t16       : VOP1_Real_FULL_t16_gfx11<0x051, "v_cvt_f16_i16">;
-defm V_CVT_U16_F16_t16       : VOP1_Real_FULL_t16_gfx11<0x052, "v_cvt_u16_f16">;
-defm V_CVT_I16_F16_t16       : VOP1_Real_FULL_t16_gfx11<0x053, "v_cvt_i16_f16">;
-defm V_RCP_F16_t16           : VOP1_Real_FULL_t16_gfx11<0x054, "v_rcp_f16">;
-defm V_SQRT_F16_t16          : VOP1_Real_FULL_t16_gfx11<0x055, "v_sqrt_f16">;
-defm V_RSQ_F16_t16           : VOP1_Real_FULL_t16_gfx11<0x056, "v_rsq_f16">;
-defm V_LOG_F16_t16           : VOP1_Real_FULL_t16_gfx11<0x057, "v_log_f16">;
-defm V_EXP_F16_t16           : VOP1_Real_FULL_t16_gfx11<0x058, "v_exp_f16">;
-defm V_FREXP_MANT_F16_t16    : VOP1_Real_FULL_t16_gfx11<0x059, "v_frexp_mant_f16">;
-defm V_FREXP_EXP_I16_F16_t16 : VOP1_Real_FULL_t16_gfx11<0x05a, "v_frexp_exp_i16_f16">;
-defm V_FLOOR_F16_t16         : VOP1_Real_FULL_t16_gfx11<0x05b, "v_floor_f16">;
-defm V_CEIL_F16_t16          : VOP1_Real_FULL_t16_gfx11<0x05c, "v_ceil_f16">;
-defm V_TRUNC_F16_t16         : VOP1_Real_FULL_t16_gfx11<0x05d, "v_trunc_f16">;
-defm V_RNDNE_F16_t16         : VOP1_Real_FULL_t16_gfx11<0x05e, "v_rndne_f16">;
-defm V_FRACT_F16_t16         : VOP1_Real_FULL_t16_gfx11<0x05f, "v_fract_f16">;
-defm V_SIN_F16_t16           : VOP1_Real_FULL_t16_gfx11<0x060, "v_sin_f16">;
-defm V_COS_F16_t16           : VOP1_Real_FULL_t16_gfx11<0x061, "v_cos_f16">;
-defm V_SAT_PK_U8_I16_t16     : VOP1_Real_FULL_t16_gfx11<0x062, "v_sat_pk_u8_i16">;
-defm V_CVT_NORM_I16_F16_t16  : VOP1_Real_FULL_t16_gfx11<0x063, "v_cvt_norm_i16_f16">;
-defm V_CVT_NORM_U16_F16_t16  : VOP1_Real_FULL_t16_gfx11<0x064, "v_cvt_norm_u16_f16">;
-
-defm V_CVT_F16_F32_t16       : VOP1_Real_FULL_t16_gfx11<0x00a, "v_cvt_f16_f32">;
-defm V_CVT_F32_F16_t16       : VOP1_Real_FULL_t16_gfx11<0x00b, "v_cvt_f32_f16">;
+defm V_PERMLANE64_B32      : VOP1Only_Real_gfx11_gfx12<0x067>;
+defm V_MOV_B16_t16           : VOP1_Real_FULL_t16_gfx11_gfx12<0x01c, "v_mov_b16">;
+defm V_NOT_B16_t16           : VOP1_Real_FULL_t16_gfx11_gfx12<0x069, "v_not_b16">;
+defm V_CVT_I32_I16_t16       : VOP1_Real_FULL_t16_gfx11_gfx12<0x06a, "v_cvt_i32_i16">;
+defm V_CVT_U32_U16_t16       : VOP1_Real_FULL_t16_gfx11_gfx12<0x06b, "v_cvt_u32_u16">;
+
+defm V_CVT_F16_U16_t16       : VOP1_Real_FULL_t16_gfx11_gfx12<0x050, "v_cvt_f16_u16">;
+defm V_CVT_F16_I16_t16       : VOP1_Real_FULL_t16_gfx11_gfx12<0x051, "v_cvt_f16_i16">;
+defm V_CVT_U16_F16_t16       : VOP1_Real_FULL_t16_gfx11_gfx12<0x052, "v_cvt_u16_f16">;
+defm V_CVT_I16_F16_t16       : VOP1_Real_FULL_t16_gfx11_gfx12<0x053, "v_cvt_i16_f16">;
+defm V_RCP_F16_t16           : VOP1_Real_FULL_t16_gfx11_gfx12<0x054, "v_rcp_f16">;
+defm V_SQRT_F16_t16          : VOP1_Real_FULL_t16_gfx11_gfx12<0x055, "v_sqrt_f16">;
+defm V_RSQ_F16_t16           : VOP1_Real_FULL_t16_gfx11_gfx12<0x056, "v_rsq_f16">;
+defm V_LOG_F16_t16           : VOP1_Real_FULL_t16_gfx11_gfx12<0x057, "v_log_f16">;
+defm V_EXP_F16_t16           : VOP1_Real_FULL_t16_gfx11_gfx12<0x058, "v_exp_f16">;
+defm V_FREXP_MANT_F16_t16    : VOP1_Real_FULL_t16_gfx11_gfx12<0x059, "v_frexp_mant_f16">;
+defm V_FREXP_EXP_I16_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05a, "v_frexp_exp_i16_f16">;
+defm V_FLOOR_F16_t16         : VOP1_Real_FULL_t16_gfx11_gfx12<0x05b, "v_floor_f16">;
+defm V_CEIL_F16_t16          : VOP1_Real_FULL_t16_gfx11_gfx12<0x05c, "v_ceil_f16">;
+defm V_TRUNC_F16_t16         : VOP1_Real_FULL_t16_gfx11_gfx12<0x05d, "v_trunc_f16">;
+defm V_RNDNE_F16_t16         : VOP1_Real_FULL_t16_gfx11_gfx12<0x05e, "v_rndne_f16">;
+defm V_FRACT_F16_t16         : VOP1_Real_FULL_t16_gfx11_gfx12<0x05f, "v_fract_f16">;
+defm V_SIN_F16_t16           : VOP1_Real_FULL_t16_gfx11_gfx12<0x060, "v_sin_f16">;
+defm V_COS_F16_t16           : VOP1_Real_FULL_t16_gfx11_gfx12<0x061, "v_cos_f16">;
+defm V_SAT_PK_U8_I16_t16     : VOP1_Real_FULL_t16_gfx11_gfx12<0x062, "v_sat_pk_u8_i16">;
+defm V_CVT_NORM_I16_F16_t16  : VOP1_Real_FULL_t16_gfx11_gfx12<0x063, "v_cvt_norm_i16_f16">;
+defm V_CVT_NORM_U16_F16_t16  : VOP1_Real_FULL_t16_gfx11_gfx12<0x064, "v_cvt_norm_u16_f16">;
+
+defm V_CVT_F16_F32_t16       : VOP1_Real_FULL_t16_gfx11_gfx12<0x00a, "v_cvt_f16_f32">;
+defm V_CVT_F32_F16_t16       : VOP1_Real_FULL_t16_gfx11_gfx12<0x00b, "v_cvt_f32_f16">;
 
 //===----------------------------------------------------------------------===//
 // GFX10.
@@ -882,17 +930,23 @@ multiclass VOP1_Real_gfx10<bits<9> op> :
   VOP1_Real_sdwa_gfx10<op>, VOP1_Real_dpp_gfx10<op>,
   VOP1_Real_dpp8_gfx10<op>;
 
-multiclass VOP1_Real_gfx10_FULL_gfx11<bits<9> op> :
-  VOP1_Real_gfx10<op>, VOP1_Real_FULL_gfx11<op>;
+multiclass VOP1_Real_gfx10_FULL_gfx11_gfx12<bits<9> op> :
+  VOP1_Real_gfx10<op>,
+  VOP1_Real_FULL<GFX11Gen, op>,
+  VOP1_Real_FULL<GFX12Gen, op>;
 
-multiclass VOP1_Real_gfx10_NO_DPP_gfx11<bits<9> op> :
-  VOP1_Real_gfx10<op>, VOP1_Real_NO_DPP_gfx11<op>;
+multiclass VOP1_Real_gfx10_NO_DPP_gfx11_gfx12<bits<9> op> :
+  VOP1_Real_gfx10<op>,
+  VOP1_Real_NO_DPP<GFX11Gen, op>,
+  VOP1_Real_NO_DPP<GFX12Gen, op>;
 
-multiclass VOP1Only_Real_gfx10_gfx11<bits<9> op> :
-  VOP1Only_Real_gfx10<op>, VOP1Only_Real_gfx11<op>;
+multiclass VOP1Only_Real_gfx10_gfx11_gfx12<bits<9> op> :
+  VOP1Only_Real_gfx10<op>,
+  VOP1Only_Real<GFX11Gen, op>,
+  VOP1Only_Real<GFX12Gen, op>;
 
-defm V_PIPEFLUSH         : VOP1_Real_gfx10_NO_DPP_gfx11<0x01b>;
-defm V_MOVRELSD_2_B32    : VOP1_Real_gfx10_FULL_gfx11<0x048>;
+defm V_PIPEFLUSH         : VOP1_Real_gfx10_NO_DPP_gfx11_gfx12<0x01b>;
+defm V_MOVRELSD_2_B32    : VOP1_Real_gfx10_FULL_gfx11_gfx12<0x048>;
 defm V_CVT_F16_U16       : VOP1_Real_gfx10<0x050>;
 defm V_CVT_F16_I16       : VOP1_Real_gfx10<0x051>;
 defm V_CVT_U16_F16       : VOP1_Real_gfx10<0x052>;
@@ -915,11 +969,11 @@ defm V_SAT_PK_U8_I16     : VOP1_Real_gfx10<0x062>;
 defm V_CVT_NORM_I16_F16  : VOP1_Real_gfx10<0x063>;
 defm V_CVT_NORM_U16_F16  : VOP1_Real_gfx10<0x064>;
 
-defm V_SWAP_B32          : VOP1Only_Real_gfx10_gfx11<0x065>;
-defm V_SWAPREL_B32       : VOP1Only_Real_gfx10_gfx11<0x068>;
+defm V_SWAP_B32          : VOP1Only_Real_gfx10_gfx11_gfx12<0x065>;
+defm V_SWAPREL_B32       : VOP1Only_Real_gfx10_gfx11_gfx12<0x068>;
 
 //===----------------------------------------------------------------------===//
-// GFX7, GFX10.
+// GFX7, GFX10, GFX11, GFX12
 //===----------------------------------------------------------------------===//
 
 let AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" in {
@@ -938,22 +992,20 @@ let AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" in {
 multiclass VOP1_Real_gfx7<bits<9> op> :
   VOP1_Real_e32_gfx7<op>, VOP1_Real_e64_gfx7<op>;
 
-multiclass VOP1_Real_gfx7_gfx10<bits<9> op> :
-  VOP1_Real_gfx7<op>, VOP1_Real_gfx10<op>;
-
-multiclass VOP1_Real_gfx7_gfx10_NO_DPP_gfx11<bits<9> op> :
-  VOP1_Real_gfx7_gfx10<op>, VOP1_Real_NO_DPP_gfx11<op>;
+multiclass VOP1_Real_gfx7_gfx10_NO_DPP_gfx11_gfx12<bits<9> op> :
+  VOP1_Real_gfx7<op>, VOP1_Real_gfx10<op>, VOP1_Real_NO_DPP<GFX11Gen, op>,
+  VOP1_Real_NO_DPP<GFX12Gen, op>;
 
 defm V_LOG_LEGACY_F32 : VOP1_Real_gfx7<0x045>;
 defm V_EXP_LEGACY_F32 : VOP1_Real_gfx7<0x046>;
 
-defm V_TRUNC_F64      : VOP1_Real_gfx7_gfx10_NO_DPP_gfx11<0x017>;
-defm V_CEIL_F64       : VOP1_Real_gfx7_gfx10_NO_DPP_gfx11<0x018>;
-defm V_RNDNE_F64      : VOP1_Real_gfx7_gfx10_NO_DPP_gfx11<0x019>;
-defm V_FLOOR_F64      : VOP1_Real_gfx7_gfx10_NO_DPP_gfx11<0x01a>;
+defm V_TRUNC_F64      : VOP1_Real_gfx7_gfx10_NO_DPP_gfx11_gfx12<0x017>;
+defm V_CEIL_F64       : VOP1_Real_gfx7_gfx10_NO_DPP_gfx11_gfx12<0x018>;
+defm V_RNDNE_F64      : VOP1_Real_gfx7_gfx10_NO_DPP_gfx11_gfx12<0x019>;
+defm V_FLOOR_F64      : VOP1_Real_gfx7_gfx10_NO_DPP_gfx11_gfx12<0x01a>;
 
 //===----------------------------------------------------------------------===//
-// GFX6, GFX7, GFX10, GFX11.
+// GFX6, GFX7, GFX10, GFX11, GFX12
 //===----------------------------------------------------------------------===//
 
 let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {
@@ -975,11 +1027,13 @@ multiclass VOP1_Real_gfx6_gfx7<bits<9> op> :
 multiclass VOP1_Real_gfx6_gfx7_gfx10<bits<9> op> :
   VOP1_Real_gfx6_gfx7<op>, VOP1_Real_gfx10<op>;
 
-multiclass VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<bits<9> op> :
-  VOP1_Real_gfx6_gfx7_gfx10<op>, VOP1_Real_FULL_gfx11<op>;
+multiclass VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<bits<9> op> :
+  VOP1_Real_gfx6_gfx7_gfx10<op>, VOP1_Real_FULL<GFX11Gen, op>,
+  VOP1_Real_FULL<GFX12Gen, op>;
 
-multiclass VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11<bits<9> op> :
-  VOP1_Real_gfx6_gfx7_gfx10<op>, VOP1_Real_NO_DPP_gfx11<op>;
+multiclass VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_gfx12<bits<9> op> :
+  VOP1_Real_gfx6_gfx7_gfx10<op>, VOP1_Real_NO_DPP<GFX11Gen, op>,
+  VOP1_Real_NO_DPP<GFX12Gen, op>;
 
 defm V_LOG_CLAMP_F32     : VOP1_Real_gfx6_gfx7<0x026>;
 defm V_RCP_CLAMP_F32     : VOP1_Real_gfx6_gfx7<0x028>;
@@ -989,57 +1043,57 @@ defm V_RSQ_LEGACY_F32    : VOP1_Real_gfx6_gfx7<0x02d>;
 defm V_RCP_CLAMP_F64     : VOP1_Real_gfx6_gfx7<0x030>;
 defm V_RSQ_CLAMP_F64     : VOP1_Real_gfx6_gfx7<0x032>;
 
-defm V_NOP               : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11<0x000>;
-defm V_MOV_B32           : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x001>;
-defm V_CVT_I32_F64       : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11<0x003>;
-defm V_CVT_F64_I32       : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11<0x004>;
-defm V_CVT_F32_I32       : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x005>;
-defm V_CVT_F32_U32       : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x006>;
-defm V_CVT_U32_F32       : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x007>;
-defm V_CVT_I32_F32       : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x008>;
+defm V_NOP               : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_gfx12<0x000>;
+defm V_MOV_B32           : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x001>;
+defm V_CVT_I32_F64       : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_gfx12<0x003>;
+defm V_CVT_F64_I32       : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_gfx12<0x004>;
+defm V_CVT_F32_I32       : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x005>;
+defm V_CVT_F32_U32       : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x006>;
+defm V_CVT_U32_F32       : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x007>;
+defm V_CVT_I32_F32       : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x008>;
 defm V_CVT_F16_F32       : VOP1_Real_gfx6_gfx7_gfx10<0x00a>;
 defm V_CVT_F32_F16       : VOP1_Real_gfx6_gfx7_gfx10<0x00b>;
 defm V_CVT_RPI_I32_F32   : VOP1_Real_gfx6_gfx7_gfx10<0x00c>;
 defm V_CVT_FLR_I32_F32   : VOP1_Real_gfx6_gfx7_gfx10<0x00d>;
-defm V_CVT_OFF_F32_I4    : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x00e>;
-defm V_CVT_F32_F64       : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11<0x00f>;
-defm V_CVT_F64_F32       : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11<0x010>;
-defm V_CVT_F32_UBYTE0    : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x011>;
-defm V_CVT_F32_UBYTE1    : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x012>;
-defm V_CVT_F32_UBYTE2    : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x013>;
-defm V_CVT_F32_UBYTE3    : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x014>;
-defm V_CVT_U32_F64       : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11<0x015>;
-defm V_CVT_F64_U32       : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11<0x016>;
-defm V_FRACT_F32         : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x020>;
-defm V_TRUNC_F32         : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x021>;
-defm V_CEIL_F32          : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x022>;
-defm V_RNDNE_F32         : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x023>;
-defm V_FLOOR_F32         : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x024>;
-defm V_EXP_F32           : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x025>;
-defm V_LOG_F32           : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x027>;
-defm V_RCP_F32           : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x02a>;
-defm V_RCP_IFLAG_F32     : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x02b>;
-defm V_RSQ_F32           : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x02e>;
-defm V_RCP_F64           : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11<0x02f>;
-defm V_RSQ_F64           : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11<0x031>;
-defm V_SQRT_F32          : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x033>;
-defm V_SQRT_F64          : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11<0x034>;
-defm V_SIN_F32           : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x035>;
-defm V_COS_F32           : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x036>;
-defm V_NOT_B32           : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x037>;
-defm V_BFREV_B32         : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x038>;
+defm V_CVT_OFF_F32_I4    : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x00e>;
+defm V_CVT_F32_F64       : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_gfx12<0x00f>;
+defm V_CVT_F64_F32       : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_gfx12<0x010>;
+defm V_CVT_F32_UBYTE0    : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x011>;
+defm V_CVT_F32_UBYTE1    : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x012>;
+defm V_CVT_F32_UBYTE2    : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x013>;
+defm V_CVT_F32_UBYTE3    : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x014>;
+defm V_CVT_U32_F64       : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_gfx12<0x015>;
+defm V_CVT_F64_U32       : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_gfx12<0x016>;
+defm V_FRACT_F32         : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x020>;
+defm V_TRUNC_F32         : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x021>;
+defm V_CEIL_F32          : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x022>;
+defm V_RNDNE_F32         : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x023>;
+defm V_FLOOR_F32         : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x024>;
+defm V_EXP_F32           : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x025>;
+defm V_LOG_F32           : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x027>;
+defm V_RCP_F32           : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x02a>;
+defm V_RCP_IFLAG_F32     : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x02b>;
+defm V_RSQ_F32           : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x02e>;
+defm V_RCP_F64           : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_gfx12<0x02f>;
+defm V_RSQ_F64           : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_gfx12<0x031>;
+defm V_SQRT_F32          : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x033>;
+defm V_SQRT_F64          : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_gfx12<0x034>;
+defm V_SIN_F32           : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x035>;
+defm V_COS_F32           : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x036>;
+defm V_NOT_B32           : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x037>;
+defm V_BFREV_B32         : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x038>;
 defm V_FFBH_U32          : VOP1_Real_gfx6_gfx7_gfx10<0x039>;
 defm V_FFBL_B32          : VOP1_Real_gfx6_gfx7_gfx10<0x03a>;
 defm V_FFBH_I32          : VOP1_Real_gfx6_gfx7_gfx10<0x03b>;
-defm V_FREXP_EXP_I32_F64 : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11<0x03c>;
-defm V_FREXP_MANT_F64    : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11<0x03d>;
-defm V_FRACT_F64         : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11<0x03e>;
-defm V_FREXP_EXP_I32_F32 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x03f>;
-defm V_FREXP_MANT_F32    : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x040>;
+defm V_FREXP_EXP_I32_F64 : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_gfx12<0x03c>;
+defm V_FREXP_MANT_F64    : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_gfx12<0x03d>;
+defm V_FRACT_F64         : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_gfx12<0x03e>;
+defm V_FREXP_EXP_I32_F32 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x03f>;
+defm V_FREXP_MANT_F32    : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x040>;
 defm V_CLREXCP           : VOP1_Real_gfx6_gfx7_gfx10<0x041>;
-defm V_MOVRELD_B32       : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x042>;
-defm V_MOVRELS_B32       : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x043>;
-defm V_MOVRELSD_B32      : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11<0x044>;
+defm V_MOVRELD_B32       : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x042>;
+defm V_MOVRELS_B32       : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x043>;
+defm V_MOVRELSD_B32      : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x044>;
 
 //===----------------------------------------------------------------------===//
 // GFX8, GFX9 (VI).
@@ -1320,3 +1374,15 @@ def : GCNPat <
                         (as_i32timm $dpp8), (i32 DPP8Mode.FI_0))
 >;
 } // End OtherPredicates = [isGFX11Only]
+
+//===----------------------------------------------------------------------===//
+// GFX12
+//===----------------------------------------------------------------------===//
+
+let OtherPredicates = [isGFX12Only] in {
+def : GCNPat <
+  (i32 (int_amdgcn_mov_dpp8 i32:$src, timm:$dpp8)),
+  (V_MOV_B32_dpp8_gfx12 VGPR_32:$src, VGPR_32:$src,
+                        (as_i32timm $dpp8), (i32 DPP8Mode.FI_0))
+>;
+} // End OtherPredicates = [isGFX12Only]
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index 1917b24539d0..0aa62ea77b11 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -109,6 +109,14 @@ class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily, string real_name = ps.Mnemo
   let mayStore             = ps.mayStore;
 }
 
+class VOP2_Real_Gen <VOP2_Pseudo ps, GFXGen Gen, string real_name = ps.Mnemonic> :
+  VOP2_Real <ps, Gen.Subtarget, real_name> {
+  let AssemblerPredicate = !if(ps.Pfl.IsRealTrue16, UseRealTrue16Insts,
+                               Gen.AssemblerPredicate);
+  let DecoderNamespace = Gen.DecoderNamespace#
+                         !if(ps.Pfl.IsRealTrue16, "", "_FAKE16");
+}
+
 class VOP2_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
   VOP_SDWA_Pseudo <OpName, P, pattern> {
   let AsmMatchConverter = "cvtSdwaVOP2";
@@ -1215,6 +1223,20 @@ def : VOPBinOpClampPat<uaddsat, V_ADD_U16_e64, i16>;
 def : VOPBinOpClampPat<usubsat, V_SUB_U16_e64, i16>;
 }
 
+let SubtargetPredicate = isGFX12Plus, isReMaterializable = 1 in {
+  let SchedRW = [WriteDoubleAdd], isCommutable = 1 in {
+    let FPDPRounding = 1 in {
+      defm V_ADD_F64_pseudo : VOP2Inst <"v_add_f64_pseudo", VOP_F64_F64_F64, any_fadd>;
+      defm V_MUL_F64_pseudo : VOP2Inst <"v_mul_f64_pseudo", VOP_F64_F64_F64, fmul>;
+    } // End FPDPRounding = 1
+    defm V_MIN_NUM_F64 : VOP2Inst <"v_min_num_f64", VOP_F64_F64_F64, fminnum_like>;
+    defm V_MAX_NUM_F64 : VOP2Inst <"v_max_num_f64", VOP_F64_F64_F64, fmaxnum_like>;
+  } // End SchedRW = [WriteDoubleAdd], isCommutable = 1
+  let SchedRW = [Write64Bit] in {
+    defm V_LSHLREV_B64_pseudo : VOP2Inst <"v_lshlrev_b64_pseudo", VOP_I64_I32_I64, clshl_rev_64>;
+  } // End SchedRW = [Write64Bit]
+} // End SubtargetPredicate = isGFX12Plus, isReMaterializable = 1
+
 //===----------------------------------------------------------------------===//
 // DPP Encodings
 //===----------------------------------------------------------------------===//
@@ -1250,6 +1272,15 @@ class VOP2_DPP16<bits<6> op, VOP2_DPP_Pseudo ps, int subtarget,
     Base_VOP2_DPP16<op, ps, opName, p>,
     SIMCInstr <ps.PseudoInstr, subtarget>;
 
+class VOP2_DPP16_Gen<bits<6> op, VOP2_DPP_Pseudo ps, GFXGen Gen,
+                 string opName = ps.OpName, VOPProfile p = ps.Pfl> :
+    VOP2_DPP16<op, ps, Gen.Subtarget, opName, p> {
+  let AssemblerPredicate = !if(ps.Pfl.IsRealTrue16, UseRealTrue16Insts,
+                               Gen.AssemblerPredicate);
+  let DecoderNamespace = "DPP"#Gen.DecoderNamespace#
+                         !if(ps.Pfl.IsRealTrue16, "", "_FAKE16");
+}
+
 class VOP2_DPP8<bits<6> op, VOP2_Pseudo ps,
                 VOPProfile p = ps.Pfl> :
     VOP_DPP8<ps.OpName, p> {
@@ -1269,234 +1300,362 @@ class VOP2_DPP8<bits<6> op, VOP2_Pseudo ps,
 
   let OtherPredicates = ps.OtherPredicates;
 }
+ 
+class VOP2_DPP8_Gen<bits<6> op, VOP2_Pseudo ps, GFXGen Gen,
+                    VOPProfile p = ps.Pfl> :
+    VOP2_DPP8<op, ps, p> {
+  let AssemblerPredicate = !if(ps.Pfl.IsRealTrue16, UseRealTrue16Insts,
+                               Gen.AssemblerPredicate);
+  let DecoderNamespace = "DPP8"#Gen.DecoderNamespace#
+                         !if(ps.Pfl.IsRealTrue16, "", "_FAKE16");
+}
 
 //===----------------------------------------------------------------------===//
-// GFX11.
+// GFX11, GFX12
 //===----------------------------------------------------------------------===//
 
-let AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11" in {
-  //===------------------------------- VOP2 -------------------------------===//
-  multiclass VOP2Only_Real_MADK_gfx11<bits<6> op> {
-    def _gfx11 :
-      VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.GFX11>,
-      VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
+//===------------------------------- VOP2 -------------------------------===//
+multiclass VOP2Only_Real_MADK<GFXGen Gen, bits<6> op> {
+  def Gen.Suffix :
+    VOP2_Real_Gen<!cast<VOP2_Pseudo>(NAME), Gen>,
+    VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
+}
+
+multiclass VOP2Only_Real_MADK_with_name<GFXGen Gen, bits<6> op, string asmName,
+                                        string opName = NAME> {
+  def Gen.Suffix :
+      VOP2_Real_Gen<!cast<VOP2_Pseudo>(opName), Gen>,
+      VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(opName).Pfl> {
+    VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName);
+    let AsmString = asmName # ps.AsmOperands;
   }
-  multiclass VOP2Only_Real_MADK_gfx11_with_name<bits<6> op, string asmName,
-                                                string opName = NAME> {
-    def _gfx11 :
-        VOP2_Real<!cast<VOP2_Pseudo>(opName), SIEncodingFamily.GFX11>,
-        VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(opName).Pfl> {
-      VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName);
+}
+
+multiclass VOP2_Real_e32<GFXGen Gen, bits<6> op> {
+  def _e32#Gen.Suffix :
+    VOP2_Real_Gen<!cast<VOP2_Pseudo>(NAME#"_e32"), Gen>,
+    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
+}
+
+multiclass VOP2Only_Real_e32<GFXGen Gen, bits<6> op> {
+  let IsSingle = 1 in
+    defm NAME: VOP2_Real_e32<Gen, op>;
+}
+
+multiclass VOP2_Real_e64<GFXGen Gen, bits<6> op> {
+  def _e64#Gen.Suffix :
+    VOP3_Real_Gen<!cast<VOP3_Pseudo>(NAME#"_e64"), Gen>,
+    VOP3e_gfx11_gfx12<{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
+}
+
+multiclass VOP2_Real_dpp<GFXGen Gen, bits<6> op> {
+  if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP then
+  def _dpp#Gen.Suffix : VOP2_DPP16_Gen<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), Gen>;
+}
+
+multiclass VOP2_Real_dpp8<GFXGen Gen, bits<6> op> {
+  if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP then
+  def _dpp8#Gen.Suffix : VOP2_DPP8_Gen<op, !cast<VOP2_Pseudo>(NAME#"_e32"), Gen>;
+}
+
+//===------------------------- VOP2 (with name) -------------------------===//
+multiclass VOP2_Real_e32_with_name<GFXGen Gen, bits<6> op, string opName,
+                                   string asmName, bit single = 0> {
+  defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");
+  def _e32#Gen.Suffix :
+    VOP2_Real_Gen<ps, Gen, asmName>,
+    VOP2e<op{5-0}, ps.Pfl> {
       let AsmString = asmName # ps.AsmOperands;
+      let IsSingle = single;
     }
-  }
-  multiclass VOP2_Real_e32_gfx11<bits<6> op> {
-    def _e32_gfx11 :
-      VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX11>,
-      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
-  }
-  multiclass VOP2Only_Real_e32_gfx11<bits<6> op> {
-    let IsSingle = 1 in
-      defm NAME: VOP2_Real_e32_gfx11<op>;
-  }
-  multiclass VOP2_Real_e64_gfx11<bits<6> op> {
-    def _e64_gfx11 :
-      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX11>,
-      VOP3e_gfx11<{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
-  }
-  multiclass VOP2_Real_dpp_gfx11<bits<6> op> {
-    if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP then
-    def _dpp_gfx11 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX11> {
-      let DecoderNamespace = "DPPGFX11";
-    }
-  }
-  multiclass VOP2_Real_dpp8_gfx11<bits<6> op> {
-    if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP then
-    def _dpp8_gfx11 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(NAME#"_e32")> {
-      let DecoderNamespace = "DPP8GFX11";
+}
+multiclass VOP2_Real_e64_with_name<GFXGen Gen, bits<6> op, string opName,
+                                   string asmName> {
+  defvar ps = !cast<VOP3_Pseudo>(opName#"_e64");
+  def _e64#Gen.Suffix :
+    VOP3_Real_Gen<ps, Gen>,
+    VOP3e_gfx11_gfx12<{0, 1, 0, 0, op{5-0}}, ps.Pfl> {
+      let AsmString = asmName # ps.AsmOperands;
     }
-  }
+}
 
-  //===------------------------- VOP2 (with name) -------------------------===//
-  multiclass VOP2_Real_e32_with_name_gfx11<bits<6> op, string opName,
-                                           string asmName, bit single = 0> {
-    defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");
-    let DecoderNamespace = !if(ps.Pfl.IsRealTrue16, "GFX11", "GFX11_FAKE16"),
-        AssemblerPredicate = !if(ps.Pfl.IsRealTrue16, UseRealTrue16Insts, isGFX11Only) in
-    def _e32_gfx11 :
-      VOP2_Real<ps, SIEncodingFamily.GFX11, asmName>,
-      VOP2e<op{5-0}, ps.Pfl> {
-        let AsmString = asmName # ps.AsmOperands;
-        let IsSingle = single;
-      }
+multiclass VOP2_Real_dpp_with_name<GFXGen Gen, bits<6> op, string opName,
+                                   string asmName> {
+  defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");
+  if ps.Pfl.HasExtDPP then
+  def _dpp#Gen.Suffix : VOP2_DPP16_Gen<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), Gen> {
+    let AsmString = asmName # ps.Pfl.AsmDPP16;
   }
-  multiclass VOP2_Real_e64_with_name_gfx11<bits<6> op, string opName,
-                                           string asmName> {
-    defvar ps = !cast<VOP3_Pseudo>(opName#"_e64");
-    def _e64_gfx11 :
-      VOP3_Real<ps, SIEncodingFamily.GFX11>,
-      VOP3e_gfx11<{0, 1, 0, 0, op{5-0}}, ps.Pfl> {
-        let AsmString = asmName # ps.AsmOperands;
-      }
+}
+multiclass VOP2_Real_dpp8_with_name<GFXGen Gen, bits<6> op, string opName,
+                                    string asmName> {
+  defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");
+  if ps.Pfl.HasExtDPP then
+  def _dpp8#Gen.Suffix : VOP2_DPP8_Gen<op, ps, Gen> {
+    let AsmString = asmName # ps.Pfl.AsmDPP8;
   }
+}
 
-  multiclass VOP2_Real_dpp_with_name_gfx11<bits<6> op, string opName,
-                                           string asmName> {
-    defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");
-    if ps.Pfl.HasExtDPP then
-    def _dpp_gfx11 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"),
-        SIEncodingFamily.GFX11> {
-      let AsmString = asmName # ps.Pfl.AsmDPP16;
-      let DecoderNamespace = !if(ps.Pfl.IsRealTrue16, "DPPGFX11", "DPPGFX11_FAKE16");
-      let AssemblerPredicate = !if(ps.Pfl.IsRealTrue16, UseRealTrue16Insts, isGFX11Only);
+//===------------------------------ VOP2be ------------------------------===//
+multiclass VOP2be_Real_e32<GFXGen Gen, bits<6> op, string opName, string asmName> {
+  defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");
+  def _e32#Gen.Suffix :
+    VOP2_Real_Gen<ps, Gen>,
+    VOP2e<op{5-0}, ps.Pfl> {
+      let AsmString = asmName # !subst(", vcc", "", ps.AsmOperands);
     }
-  }
-  multiclass VOP2_Real_dpp8_with_name_gfx11<bits<6> op, string opName,
-                                            string asmName> {
-    defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");
-    if ps.Pfl.HasExtDPP then
-    def _dpp8_gfx11 : VOP2_DPP8<op, ps> {
-      let AsmString = asmName # ps.Pfl.AsmDPP8;
-      let DecoderNamespace = !if(ps.Pfl.IsRealTrue16, "DPP8GFX11", "DPP8GFX11_FAKE16");
-      let AssemblerPredicate = !if(ps.Pfl.IsRealTrue16, UseRealTrue16Insts, isGFX11Only);
+}
+multiclass VOP2be_Real_dpp<GFXGen Gen, bits<6> op, string opName, string asmName> {
+  if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP then
+  def _dpp#Gen.Suffix :
+    VOP2_DPP16_Gen<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), Gen, asmName> {
+      string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
+      let AsmString = asmName # !subst(", vcc", "", AsmDPP);
     }
-  }
-
-  //===------------------------------ VOP2be ------------------------------===//
-  multiclass VOP2be_Real_e32_gfx11<bits<6> op, string opName, string asmName> {
-    defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");
-    def _e32_gfx11 :
-      VOP2_Real<ps, SIEncodingFamily.GFX11>,
-      VOP2e<op{5-0}, ps.Pfl> {
-        let AsmString = asmName # !subst(", vcc", "", ps.AsmOperands);
-      }
-  }
-  multiclass VOP2be_Real_dpp_gfx11<bits<6> op, string opName, string asmName> {
-    if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP then
-    def _dpp_gfx11 :
-      VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), SIEncodingFamily.GFX11, asmName> {
-        string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
-        let AsmString = asmName # !subst(", vcc", "", AsmDPP);
-        let DecoderNamespace = "DPPGFX11";
-      }
-    if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP then
-    def _dpp_w32_gfx11 :
-      Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
-        string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
-        let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP);
-        let isAsmParserOnly = 1;
-        let WaveSizePredicate = isWave32;
-      }
-    if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP then
-    def _dpp_w64_gfx11 :
-      Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
-        string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
-        let AsmString = asmName # AsmDPP;
-        let isAsmParserOnly = 1;
-        let WaveSizePredicate = isWave64;
-      }
-  }
-  multiclass VOP2be_Real_dpp8_gfx11<bits<6> op, string opName, string asmName> {
-    if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP then
-    def _dpp8_gfx11 :
-      VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> {
-        string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
-        let AsmString = asmName # !subst(", vcc", "", AsmDPP8);
-        let DecoderNamespace = "DPP8GFX11";
-      }
-    if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP then
-    def _dpp8_w32_gfx11 :
-      VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> {
-        string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
-        let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP8);
-        let isAsmParserOnly = 1;
-        let WaveSizePredicate = isWave32;
-      }
-    if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP then
-    def _dpp8_w64_gfx11 :
-      VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> {
-        string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
-        let AsmString = asmName # AsmDPP8;
-        let isAsmParserOnly = 1;
-        let WaveSizePredicate = isWave64;
-      }
-  }
-
-} // End AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11"
+  if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP then
+  def _dpp_w32#Gen.Suffix :
+    Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
+      string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
+      let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP);
+      let isAsmParserOnly = 1;
+      let WaveSizePredicate = isWave32;
+      let AssemblerPredicate = Gen.AssemblerPredicate;
+      let DecoderNamespace = Gen.DecoderNamespace;
+    }
+  if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP then
+  def _dpp_w64#Gen.Suffix :
+    Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
+      string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
+      let AsmString = asmName # AsmDPP;
+      let isAsmParserOnly = 1;
+      let WaveSizePredicate = isWave64;
+      let AssemblerPredicate = Gen.AssemblerPredicate;
+      let DecoderNamespace = Gen.DecoderNamespace;
+    }
+}
+multiclass VOP2be_Real_dpp8<GFXGen Gen, bits<6> op, string opName, string asmName> {
+  if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP then
+  def _dpp8#Gen.Suffix :
+    VOP2_DPP8_Gen<op, !cast<VOP2_Pseudo>(opName#"_e32"), Gen> {
+      string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
+      let AsmString = asmName # !subst(", vcc", "", AsmDPP8);
+    }
+  if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP then
+  def _dpp8_w32#Gen.Suffix :
+    VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> {
+      string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
+      let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP8);
+      let isAsmParserOnly = 1;
+      let WaveSizePredicate = isWave32;
+      let AssemblerPredicate = Gen.AssemblerPredicate;
+      let DecoderNamespace = Gen.DecoderNamespace;
+    }
+  if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP then
+  def _dpp8_w64#Gen.Suffix :
+    VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> {
+      string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
+      let AsmString = asmName # AsmDPP8;
+      let isAsmParserOnly = 1;
+      let WaveSizePredicate = isWave64;
+      let AssemblerPredicate = Gen.AssemblerPredicate;
+      let DecoderNamespace = Gen.DecoderNamespace;
+    }
+}
 
 // We don't want to override separate decoderNamespaces within these
-multiclass VOP2_Realtriple_e64_gfx11<bits<6> op> {
-  defm NAME : VOP3_Realtriple_gfx11<{0, 1, 0, 0, op{5-0}}, /*isSingle=*/ 0, NAME> ;
+multiclass VOP2_Realtriple_e64<GFXGen Gen, bits<6> op> {
+  defm NAME : VOP3_Realtriple<Gen, {0, 1, 0, 0, op{5-0}}, /*isSingle=*/ 0, NAME> ;
 }
-multiclass VOP2_Realtriple_e64_with_name_gfx11<bits<6> op, string opName,
+
+multiclass VOP2_Realtriple_e64_with_name<GFXGen Gen, bits<6> op, string opName,
                                                string asmName> {
-  defm NAME : VOP3_Realtriple_with_name_gfx11<{0, 1, 0, 0, op{5-0}}, opName, asmName> ;
+  defm NAME : VOP3_Realtriple_with_name<Gen, {0, 1, 0, 0, op{5-0}}, opName, asmName> ;
 }
 
-multiclass VOP2be_Real_gfx11<bits<6> op, string opName, string asmName> :
-  VOP2be_Real_e32_gfx11<op, opName, asmName>,
-  VOP3be_Realtriple_gfx11<{0, 1, 0, 0, op{5-0}}, /*isSingle=*/ 0, opName, asmName>,
-  VOP2be_Real_dpp_gfx11<op, opName, asmName>,
-  VOP2be_Real_dpp8_gfx11<op, opName, asmName>;
+multiclass VOP2be_Real<GFXGen Gen, bits<6> op, string opName, string asmName> :
+  VOP2be_Real_e32<Gen, op, opName, asmName>,
+  VOP3be_Realtriple<Gen, {0, 1, 0, 0, op{5-0}}, /*isSingle=*/ 0, opName, asmName>,
+  VOP2be_Real_dpp<Gen, op, opName, asmName>,
+  VOP2be_Real_dpp8<Gen, op, opName, asmName>;
 
 // Only for CNDMASK
-multiclass VOP2e_Real_gfx11<bits<6> op, string opName, string asmName> :
-  VOP2_Real_e32_gfx11<op>,
-  VOP2_Realtriple_e64_gfx11<op>,
-  VOP2be_Real_dpp_gfx11<op, opName, asmName>,
-  VOP2be_Real_dpp8_gfx11<op, opName, asmName>;
+multiclass VOP2e_Real<GFXGen Gen, bits<6> op, string opName, string asmName> :
+  VOP2_Real_e32<Gen, op>,
+  VOP2_Realtriple_e64<Gen, op>,
+  VOP2be_Real_dpp<Gen, op, opName, asmName>,
+  VOP2be_Real_dpp8<Gen, op, opName, asmName>;
+
+multiclass VOP2Only_Real<GFXGen Gen, bits<6> op> :
+  VOP2Only_Real_e32<Gen, op>,
+  VOP2_Real_dpp<Gen, op>,
+  VOP2_Real_dpp8<Gen, op>;
+
+multiclass VOP2_Real_FULL<GFXGen Gen, bits<6> op> :
+  VOP2_Realtriple_e64<Gen, op>,
+  VOP2_Real_e32<Gen, op>,
+  VOP2_Real_dpp<Gen, op>,
+  VOP2_Real_dpp8<Gen, op>;
+
+multiclass VOP2_Real_NO_VOP3_with_name<GFXGen Gen, bits<6> op, string opName,
+                                       string asmName, bit isSingle = 0> {
+  defm NAME : VOP2_Real_e32_with_name<Gen, op, opName, asmName, isSingle>,
+              VOP2_Real_dpp_with_name<Gen, op, opName, asmName>,
+              VOP2_Real_dpp8_with_name<Gen, op, opName, asmName>;
+  defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");
+  def Gen.Suffix#"_alias" : MnemonicAlias<ps.Mnemonic, asmName>, Requires<[Gen.AssemblerPredicate]>;
+}
 
-multiclass VOP2Only_Real_gfx11<bits<6> op> :
-  VOP2Only_Real_e32_gfx11<op>,
-  VOP2_Real_dpp_gfx11<op>,
-  VOP2_Real_dpp8_gfx11<op>;
+multiclass VOP2_Real_FULL_with_name<GFXGen Gen, bits<6> op, string opName,
+                                    string asmName> :
+  VOP2_Realtriple_e64_with_name<Gen, op, opName, asmName>,
+  VOP2_Real_NO_VOP3_with_name<Gen, op, opName, asmName>;
 
-multiclass VOP2_Real_NO_VOP3_gfx11<bits<6> op> :
-  VOP2_Real_e32_gfx11<op>, VOP2_Real_dpp_gfx11<op>, VOP2_Real_dpp8_gfx11<op>;
+multiclass VOP2_Real_NO_DPP_with_name<GFXGen Gen, bits<6> op, string opName,
+                                      string asmName> {
+  defm NAME : VOP2_Real_e32_with_name<Gen, op, opName, asmName>,
+              VOP2_Real_e64_with_name<Gen, op, opName, asmName>;
+  defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");
+  def Gen.Suffix#"_alias" : MnemonicAlias<ps.Mnemonic, asmName>, Requires<[Gen.AssemblerPredicate]>;
+}
 
-multiclass VOP2_Real_FULL_gfx11<bits<6> op> :
-  VOP2_Realtriple_e64_gfx11<op>, VOP2_Real_NO_VOP3_gfx11<op>;
+multiclass VOP2_Real_NO_DPP_with_alias<GFXGen Gen, bits<6> op, string alias> {
+  defm NAME : VOP2_Real_e32<Gen, op>,
+              VOP2_Real_e64<Gen, op>;
+  def Gen.Suffix#"_alias" : MnemonicAlias<alias, NAME>, Requires<[Gen.AssemblerPredicate]>;
+}
 
-multiclass VOP2_Real_NO_VOP3_with_name_gfx11<bits<6> op, string opName,
-                                           string asmName, bit isSingle = 0> {
+//===----------------------------------------------------------------------===//
+// GFX12.
+//===----------------------------------------------------------------------===//
 
-  defm NAME : VOP2_Real_e32_with_name_gfx11<op, opName, asmName, isSingle>,
-  VOP2_Real_dpp_with_name_gfx11<op, opName, asmName>,
-  VOP2_Real_dpp8_with_name_gfx11<op, opName, asmName>;
-  defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");
-  def _gfx11_alias : MnemonicAlias<ps.Mnemonic, asmName>, Requires<[isGFX11Plus]>;
+multiclass VOP2be_Real_gfx12<bits<6> op, string opName, string asmName> :
+  VOP2be_Real<GFX12Gen, op, opName, asmName>;
+
+// Only for CNDMASK
+multiclass VOP2e_Real_gfx12<bits<6> op, string opName, string asmName> :
+  VOP2e_Real<GFX12Gen, op, opName, asmName>;
+
+multiclass VOP2_Real_FULL_with_name_gfx12<bits<6> op, string opName,
+                                          string asmName> :
+  VOP2_Real_FULL_with_name<GFX12Gen, op, opName, asmName>;
+
+multiclass VOP2_Real_FULL_t16_with_name_gfx12<bits<6> op, string opName,
+                                              string asmName, string alias> {
+  defm NAME : VOP2_Real_FULL_with_name<GFX12Gen, op, opName, asmName>;
+  def _gfx12_2nd_alias : MnemonicAlias<alias, asmName>, Requires<[isGFX12Only]>;
 }
 
-multiclass VOP2_Real_FULL_with_name_gfx11<bits<6> op, string opName,
-                                         string asmName> :
-  VOP2_Realtriple_e64_with_name_gfx11<op, opName, asmName>,
-  VOP2_Real_NO_VOP3_with_name_gfx11<op, opName, asmName>;
+multiclass VOP2_Real_NO_DPP_with_name_gfx12<bits<6> op, string opName,
+                                            string asmName> :
+  VOP2_Real_NO_DPP_with_name<GFX12Gen, op, opName, asmName>;
 
-multiclass VOP2_Real_FULL_t16_gfx11<bits<6> op, string asmName, string opName = NAME>
-    : VOP2_Real_FULL_with_name_gfx11<op, opName, asmName>;
+multiclass VOP2_Real_NO_DPP_with_alias_gfx12<bits<6> op, string alias> :
+  VOP2_Real_NO_DPP_with_alias<GFX12Gen, op, alias>;
 
-multiclass VOP2_Real_NO_DPP_gfx11<bits<6> op> :
-  VOP2_Real_e32_gfx11<op>, VOP2_Real_e64_gfx11<op>;
+defm V_ADD_F64     : VOP2_Real_NO_DPP_with_name_gfx12<0x002, "V_ADD_F64_pseudo", "v_add_f64">;
+defm V_MUL_F64     : VOP2_Real_NO_DPP_with_name_gfx12<0x006, "V_MUL_F64_pseudo", "v_mul_f64">;
+defm V_LSHLREV_B64 : VOP2_Real_NO_DPP_with_name_gfx12<0x01f, "V_LSHLREV_B64_pseudo", "v_lshlrev_b64">;
+defm V_MIN_NUM_F64 : VOP2_Real_NO_DPP_with_alias_gfx12<0x00d, "v_min_f64">;
+defm V_MAX_NUM_F64 : VOP2_Real_NO_DPP_with_alias_gfx12<0x00e, "v_max_f64">;
 
-multiclass VOP2_Real_NO_DPP_with_name_gfx11<bits<6> op, string opName,
-                                           string asmName> {
-  defm NAME : VOP2_Real_e32_with_name_gfx11<op, opName, asmName>,
-              VOP2_Real_e64_with_name_gfx11<op, opName, asmName>;
+defm V_CNDMASK_B32 : VOP2e_Real_gfx12<0x001, "V_CNDMASK_B32", "v_cndmask_b32">;
+defm V_ADD_CO_CI_U32 :
+  VOP2be_Real_gfx12<0x020, "V_ADDC_U32", "v_add_co_ci_u32">;
+defm V_SUB_CO_CI_U32 :
+  VOP2be_Real_gfx12<0x021, "V_SUBB_U32", "v_sub_co_ci_u32">;
+defm V_SUBREV_CO_CI_U32 :
+  VOP2be_Real_gfx12<0x022, "V_SUBBREV_U32", "v_subrev_co_ci_u32">;
+
+defm V_MIN_NUM_F32 : VOP2_Real_FULL_with_name_gfx12<0x015, "V_MIN_F32", "v_min_num_f32">;
+defm V_MAX_NUM_F32 : VOP2_Real_FULL_with_name_gfx12<0x016, "V_MAX_F32", "v_max_num_f32">;
+defm V_MIN_NUM_F16 : VOP2_Real_FULL_t16_with_name_gfx12<0x030, "V_MIN_F16_t16", "v_min_num_f16", "v_min_f16">;
+defm V_MIN_NUM_F16_fake16 : VOP2_Real_FULL_t16_with_name_gfx12<0x030, "V_MIN_F16_fake16", "v_min_num_f16", "v_min_f16">;
+defm V_MAX_NUM_F16 : VOP2_Real_FULL_t16_with_name_gfx12<0x031, "V_MAX_F16_t16", "v_max_num_f16", "v_max_f16">;
+defm V_MAX_NUM_F16_fake16 : VOP2_Real_FULL_t16_with_name_gfx12<0x031, "V_MAX_F16_fake16", "v_max_num_f16", "v_max_f16">;
+
+let SubtargetPredicate = isGFX12Plus in {
+  defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx12>;
+
+  defm : VOP2bInstAliases<
+    V_ADDC_U32_e32, V_ADD_CO_CI_U32_e32_gfx12, "v_add_co_ci_u32">;
+  defm : VOP2bInstAliases<
+    V_SUBB_U32_e32, V_SUB_CO_CI_U32_e32_gfx12, "v_sub_co_ci_u32">;
+  defm : VOP2bInstAliases<
+    V_SUBBREV_U32_e32, V_SUBREV_CO_CI_U32_e32_gfx12, "v_subrev_co_ci_u32">;
+} // End SubtargetPredicate = isGFX12Plus
+
+//===----------------------------------------------------------------------===//
+// GFX11.
+//===----------------------------------------------------------------------===//
+
+multiclass VOP2be_Real_gfx11<bits<6> op, string opName, string asmName> :
+  VOP2be_Real<GFX11Gen, op, opName, asmName>;
+
+// Only for CNDMASK
+multiclass VOP2e_Real_gfx11<bits<6> op, string opName, string asmName> :
+  VOP2e_Real<GFX11Gen, op, opName, asmName>;
+
+multiclass VOP2_Real_NO_VOP3_with_name_gfx11<bits<6> op, string opName,
+                                           string asmName, bit isSingle = 0> {
+  defm NAME : VOP2_Real_e32_with_name<GFX11Gen, op, opName, asmName, isSingle>,
+              VOP2_Real_dpp_with_name<GFX11Gen, op, opName, asmName>,
+              VOP2_Real_dpp8_with_name<GFX11Gen, op, opName, asmName>;
   defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");
-  def _gfx11_alias : MnemonicAlias<ps.Mnemonic, asmName>, Requires<[isGFX11Plus]>;
+  def _gfx11_alias : MnemonicAlias<ps.Mnemonic, asmName>, Requires<[isGFX11Only]>;
 }
 
+multiclass VOP2_Real_NO_DPP_with_name_gfx11<bits<6> op, string opName,
+                                           string asmName> :
+  VOP2_Real_NO_DPP_with_name<GFX11Gen, op, opName, asmName>;
+
+multiclass VOP2_Real_FULL_gfx11_gfx12<bits<6> op> :
+  VOP2_Real_FULL<GFX11Gen, op>, VOP2_Real_FULL<GFX12Gen, op>;
+
+multiclass VOP2_Real_FULL_with_name_gfx11_gfx12<bits<6> op, string opName,
+                                                string asmName> :
+  VOP2_Real_FULL_with_name<GFX11Gen, op, opName, asmName>,
+  VOP2_Real_FULL_with_name<GFX12Gen, op, opName, asmName>;
+
+multiclass VOP2_Real_e32_gfx11_gfx12<bits<6> op> :
+  VOP2Only_Real<GFX11Gen, op>, VOP2Only_Real<GFX12Gen, op>;
+
+multiclass VOP3Only_Realtriple_gfx11_gfx12<bits<10> op> :
+  VOP3Only_Realtriple<GFX11Gen, op>, VOP3Only_Realtriple<GFX12Gen, op>;
+
+multiclass VOP3Only_Realtriple_t16_gfx11_gfx12<bits<10> op, string asmName> :
+  VOP3Only_Realtriple_t16<GFX11Gen, op, asmName>,
+  VOP3Only_Realtriple_t16<GFX12Gen, op, asmName>;
+
+multiclass VOP3beOnly_Realtriple_gfx11_gfx12<bits<10> op> :
+  VOP3beOnly_Realtriple<GFX11Gen, op>, VOP3beOnly_Realtriple<GFX12Gen, op>;
+
+multiclass VOP2Only_Real_MADK_with_name_gfx11_gfx12<bits<6> op, string asmName,
+                                                    string opName = NAME> :
+  VOP2Only_Real_MADK_with_name<GFX11Gen, op, asmName, opName>,
+  VOP2Only_Real_MADK_with_name<GFX12Gen, op, asmName, opName>;
+
+multiclass VOP2_Real_FULL_t16_gfx11<bits<6> op, string asmName,
+                                    string opName = NAME> :
+  VOP2_Real_FULL_with_name<GFX11Gen, op, opName, asmName>;
+
+multiclass VOP2_Real_FULL_t16_gfx11_gfx12<bits<6> op, string asmName,
+                                          string opName = NAME> :
+  VOP2_Real_FULL_with_name_gfx11_gfx12<op, opName, asmName>;
+
+multiclass VOP2_Real_FULL_gfx11<bits<6> op> :
+  VOP2_Real_FULL<GFX11Gen, op>;
+
 defm V_CNDMASK_B32 : VOP2e_Real_gfx11<0x001, "V_CNDMASK_B32",
   "v_cndmask_b32">;
 defm V_DOT2ACC_F32_F16 : VOP2_Real_NO_VOP3_with_name_gfx11<0x002,
   "V_DOT2C_F32_F16", "v_dot2acc_f32_f16", 1>;
 defm V_FMAC_DX9_ZERO_F32 : VOP2_Real_NO_DPP_with_name_gfx11<0x006,
   "V_FMAC_LEGACY_F32", "v_fmac_dx9_zero_f32">;
-defm V_MUL_DX9_ZERO_F32 : VOP2_Real_FULL_with_name_gfx11<0x007,
+defm V_MUL_DX9_ZERO_F32 : VOP2_Real_FULL_with_name_gfx11_gfx12<0x007,
   "V_MUL_LEGACY_F32", "v_mul_dx9_zero_f32">;
-defm V_LSHLREV_B32        : VOP2_Real_FULL_gfx11<0x018>;
-defm V_LSHRREV_B32        : VOP2_Real_FULL_gfx11<0x019>;
-defm V_ASHRREV_I32        : VOP2_Real_FULL_gfx11<0x01a>;
+defm V_LSHLREV_B32        : VOP2_Real_FULL_gfx11_gfx12<0x018>;
+defm V_LSHRREV_B32        : VOP2_Real_FULL_gfx11_gfx12<0x019>;
+defm V_ASHRREV_I32        : VOP2_Real_FULL_gfx11_gfx12<0x01a>;
 defm V_ADD_CO_CI_U32 :
   VOP2be_Real_gfx11<0x020, "V_ADDC_U32", "v_add_co_ci_u32">;
 defm V_SUB_CO_CI_U32 :
@@ -1504,43 +1663,43 @@ defm V_SUB_CO_CI_U32 :
 defm V_SUBREV_CO_CI_U32 :
   VOP2be_Real_gfx11<0x022, "V_SUBBREV_U32", "v_subrev_co_ci_u32">;
 
-defm V_CVT_PK_RTZ_F16_F32  : VOP2_Real_FULL_with_name_gfx11<0x02f,
+defm V_CVT_PK_RTZ_F16_F32  : VOP2_Real_FULL_with_name_gfx11_gfx12<0x02f,
   "V_CVT_PKRTZ_F16_F32", "v_cvt_pk_rtz_f16_f32">;
-defm V_PK_FMAC_F16     : VOP2Only_Real_gfx11<0x03c>;
-
-defm V_ADD_F16_t16         : VOP2_Real_FULL_t16_gfx11<0x032, "v_add_f16">;
-defm V_ADD_F16_fake16      : VOP2_Real_FULL_t16_gfx11<0x032, "v_add_f16">;
-defm V_SUB_F16_t16         : VOP2_Real_FULL_t16_gfx11<0x033, "v_sub_f16">;
-defm V_SUB_F16_fake16      : VOP2_Real_FULL_t16_gfx11<0x033, "v_sub_f16">;
-defm V_SUBREV_F16_t16      : VOP2_Real_FULL_t16_gfx11<0x034, "v_subrev_f16">;
-defm V_SUBREV_F16_fake16   : VOP2_Real_FULL_t16_gfx11<0x034, "v_subrev_f16">;
-defm V_MUL_F16_t16         : VOP2_Real_FULL_t16_gfx11<0x035, "v_mul_f16">;
-defm V_MUL_F16_fake16      : VOP2_Real_FULL_t16_gfx11<0x035, "v_mul_f16">;
-defm V_FMAC_F16_t16        : VOP2_Real_FULL_t16_gfx11<0x036, "v_fmac_f16">;
-defm V_LDEXP_F16_t16       : VOP2_Real_FULL_t16_gfx11<0x03b, "v_ldexp_f16">;
+defm V_PK_FMAC_F16     : VOP2_Real_e32_gfx11_gfx12<0x03c>;
+
+defm V_ADD_F16_t16         : VOP2_Real_FULL_t16_gfx11_gfx12<0x032, "v_add_f16">;
+defm V_ADD_F16_fake16      : VOP2_Real_FULL_t16_gfx11_gfx12<0x032, "v_add_f16">;
+defm V_SUB_F16_t16         : VOP2_Real_FULL_t16_gfx11_gfx12<0x033, "v_sub_f16">;
+defm V_SUB_F16_fake16      : VOP2_Real_FULL_t16_gfx11_gfx12<0x033, "v_sub_f16">;
+defm V_SUBREV_F16_t16      : VOP2_Real_FULL_t16_gfx11_gfx12<0x034, "v_subrev_f16">;
+defm V_SUBREV_F16_fake16   : VOP2_Real_FULL_t16_gfx11_gfx12<0x034, "v_subrev_f16">;
+defm V_MUL_F16_t16         : VOP2_Real_FULL_t16_gfx11_gfx12<0x035, "v_mul_f16">;
+defm V_MUL_F16_fake16      : VOP2_Real_FULL_t16_gfx11_gfx12<0x035, "v_mul_f16">;
+defm V_FMAC_F16_t16        : VOP2_Real_FULL_t16_gfx11_gfx12<0x036, "v_fmac_f16">;
+defm V_LDEXP_F16_t16       : VOP2_Real_FULL_t16_gfx11_gfx12<0x03b, "v_ldexp_f16">;
 defm V_MAX_F16_t16         : VOP2_Real_FULL_t16_gfx11<0x039, "v_max_f16">;
 defm V_MAX_F16_fake16      : VOP2_Real_FULL_t16_gfx11<0x039, "v_max_f16">;
 defm V_MIN_F16_t16         : VOP2_Real_FULL_t16_gfx11<0x03a, "v_min_f16">;
 defm V_MIN_F16_fake16      : VOP2_Real_FULL_t16_gfx11<0x03a, "v_min_f16">;
-defm V_FMAMK_F16_t16       : VOP2Only_Real_MADK_gfx11_with_name<0x037, "v_fmamk_f16">;
-defm V_FMAAK_F16_t16       : VOP2Only_Real_MADK_gfx11_with_name<0x038, "v_fmaak_f16">;
+defm V_FMAMK_F16_t16       : VOP2Only_Real_MADK_with_name_gfx11_gfx12<0x037, "v_fmamk_f16">;
+defm V_FMAAK_F16_t16       : VOP2Only_Real_MADK_with_name_gfx11_gfx12<0x038, "v_fmaak_f16">;
 
 // VOP3 only.
-defm V_CNDMASK_B16         : VOP3Only_Realtriple_gfx11<0x25d>;
-defm V_LDEXP_F32           : VOP3Only_Realtriple_gfx11<0x31c>;
-defm V_BFM_B32             : VOP3Only_Realtriple_gfx11<0x31d>;
-defm V_BCNT_U32_B32        : VOP3Only_Realtriple_gfx11<0x31e>;
-defm V_MBCNT_LO_U32_B32    : VOP3Only_Realtriple_gfx11<0x31f>;
-defm V_MBCNT_HI_U32_B32    : VOP3Only_Realtriple_gfx11<0x320>;
-defm V_CVT_PK_NORM_I16_F32 : VOP3Only_Realtriple_with_name_gfx11<0x321, "V_CVT_PKNORM_I16_F32", "v_cvt_pk_norm_i16_f32">;
-defm V_CVT_PK_NORM_U16_F32 : VOP3Only_Realtriple_with_name_gfx11<0x322, "V_CVT_PKNORM_U16_F32", "v_cvt_pk_norm_u16_f32">;
-defm V_CVT_PK_U16_U32      : VOP3Only_Realtriple_gfx11<0x323>;
-defm V_CVT_PK_I16_I32      : VOP3Only_Realtriple_gfx11<0x324>;
-defm V_ADD_CO_U32          : VOP3beOnly_Realtriple_gfx11<0x300>;
-defm V_SUB_CO_U32          : VOP3beOnly_Realtriple_gfx11<0x301>;
-defm V_SUBREV_CO_U32       : VOP3beOnly_Realtriple_gfx11<0x302>;
-
-let SubtargetPredicate = isGFX11Plus in {
+defm V_CNDMASK_B16         : VOP3Only_Realtriple_gfx11_gfx12<0x25d>;
+defm V_LDEXP_F32           : VOP3Only_Realtriple_gfx11_gfx12<0x31c>;
+defm V_BFM_B32             : VOP3Only_Realtriple_gfx11_gfx12<0x31d>;
+defm V_BCNT_U32_B32        : VOP3Only_Realtriple_gfx11_gfx12<0x31e>;
+defm V_MBCNT_LO_U32_B32    : VOP3Only_Realtriple_gfx11_gfx12<0x31f>;
+defm V_MBCNT_HI_U32_B32    : VOP3Only_Realtriple_gfx11_gfx12<0x320>;
+defm V_CVT_PK_NORM_I16_F32 : VOP3Only_Realtriple_with_name_gfx11_gfx12<0x321, "V_CVT_PKNORM_I16_F32", "v_cvt_pk_norm_i16_f32">;
+defm V_CVT_PK_NORM_U16_F32 : VOP3Only_Realtriple_with_name_gfx11_gfx12<0x322, "V_CVT_PKNORM_U16_F32", "v_cvt_pk_norm_u16_f32">;
+defm V_CVT_PK_U16_U32      : VOP3Only_Realtriple_gfx11_gfx12<0x323>;
+defm V_CVT_PK_I16_I32      : VOP3Only_Realtriple_gfx11_gfx12<0x324>;
+defm V_ADD_CO_U32          : VOP3beOnly_Realtriple_gfx11_gfx12<0x300>;
+defm V_SUB_CO_U32          : VOP3beOnly_Realtriple_gfx11_gfx12<0x301>;
+defm V_SUBREV_CO_U32       : VOP3beOnly_Realtriple_gfx11_gfx12<0x302>;
+
+let SubtargetPredicate = isGFX11Only in {
   defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx11>;
 
   defm : VOP2bInstAliases<
@@ -1549,7 +1708,7 @@ let SubtargetPredicate = isGFX11Plus in {
     V_SUBB_U32_e32, V_SUB_CO_CI_U32_e32_gfx11, "v_sub_co_ci_u32">;
   defm : VOP2bInstAliases<
     V_SUBBREV_U32_e32, V_SUBREV_CO_CI_U32_e32_gfx11, "v_subrev_co_ci_u32">;
-} // End SubtargetPredicate = isGFX11Plus
+} // End SubtargetPredicate = isGFX11Only
 
 //===----------------------------------------------------------------------===//
 // GFX10.
@@ -1771,7 +1930,10 @@ let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
 } // End AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10"
 
 multiclass VOP2Only_Real_MADK_gfx10_gfx11<bits<6> op> :
-  VOP2Only_Real_MADK_gfx10<op>, VOP2Only_Real_MADK_gfx11<op>;
+  VOP2Only_Real_MADK_gfx10<op>, VOP2Only_Real_MADK<GFX11Gen, op>;
+
+multiclass VOP2Only_Real_MADK_gfx10_gfx11_gfx12<bits<6> op> :
+  VOP2Only_Real_MADK_gfx10_gfx11<op>, VOP2Only_Real_MADK<GFX12Gen, op>;
 
 multiclass VOP2be_Real_gfx10<bits<6> op, string opName, string asmName> :
   VOP2be_Real_e32_gfx10<op, opName, asmName>,
@@ -1792,7 +1954,10 @@ multiclass VOP2_Real_gfx10<bits<6> op> :
   VOP2_Real_sdwa_gfx10<op>, VOP2_Real_dpp_gfx10<op>, VOP2_Real_dpp8_gfx10<op>;
 
 multiclass VOP2_Real_gfx10_gfx11<bits<6> op> :
-  VOP2_Real_gfx10<op>, VOP2_Real_FULL_gfx11<op>;
+  VOP2_Real_gfx10<op>, VOP2_Real_FULL<GFX11Gen, op>;
+
+multiclass VOP2_Real_gfx10_gfx11_gfx12<bits<6> op> :
+  VOP2_Real_gfx10_gfx11<op>, VOP2_Real_FULL<GFX12Gen, op>;
 
 multiclass VOP2_Real_with_name_gfx10<bits<6> op, string opName,
                                      string asmName> :
@@ -1802,19 +1967,20 @@ multiclass VOP2_Real_with_name_gfx10<bits<6> op, string opName,
   VOP2_Real_dpp_gfx10_with_name<op, opName, asmName>,
   VOP2_Real_dpp8_gfx10_with_name<op, opName, asmName>;
 
-multiclass VOP2_Real_with_name_gfx10_gfx11<bits<6> op, string opName,
-                                     string asmName> :
+multiclass VOP2_Real_with_name_gfx10_gfx11_gfx12<bits<6> op, string opName,
+                                                 string asmName> :
   VOP2_Real_with_name_gfx10<op, opName, asmName>,
-  VOP2_Real_FULL_with_name_gfx11<op, opName, asmName>;
+  VOP2_Real_FULL_with_name<GFX11Gen, op, opName, asmName>,
+  VOP2_Real_FULL_with_name<GFX12Gen, op, opName, asmName>;
 
 // NB: Same opcode as v_mac_legacy_f32
 let DecoderNamespace = "GFX10_B" in
 defm V_FMAC_LEGACY_F32 : VOP2_Real_gfx10<0x006>;
 
-defm V_XNOR_B32        : VOP2_Real_gfx10_gfx11<0x01e>;
-defm V_FMAC_F32        : VOP2_Real_gfx10_gfx11<0x02b>;
-defm V_FMAMK_F32       : VOP2Only_Real_MADK_gfx10_gfx11<0x02c>;
-defm V_FMAAK_F32       : VOP2Only_Real_MADK_gfx10_gfx11<0x02d>;
+defm V_XNOR_B32        : VOP2_Real_gfx10_gfx11_gfx12<0x01e>;
+defm V_FMAC_F32        : VOP2_Real_gfx10_gfx11_gfx12<0x02b>;
+defm V_FMAMK_F32       : VOP2Only_Real_MADK_gfx10_gfx11_gfx12<0x02c>;
+defm V_FMAAK_F32       : VOP2Only_Real_MADK_gfx10_gfx11_gfx12<0x02d>;
 defm V_ADD_F16         : VOP2_Real_gfx10<0x032>;
 defm V_SUB_F16         : VOP2_Real_gfx10<0x033>;
 defm V_SUBREV_F16      : VOP2_Real_gfx10<0x034>;
@@ -1832,11 +1998,11 @@ let IsSingle = 1 in {
 
 // VOP2 no carry-in, carry-out.
 defm V_ADD_NC_U32 :
-  VOP2_Real_with_name_gfx10_gfx11<0x025, "V_ADD_U32", "v_add_nc_u32">;
+  VOP2_Real_with_name_gfx10_gfx11_gfx12<0x025, "V_ADD_U32", "v_add_nc_u32">;
 defm V_SUB_NC_U32 :
-  VOP2_Real_with_name_gfx10_gfx11<0x026, "V_SUB_U32", "v_sub_nc_u32">;
+  VOP2_Real_with_name_gfx10_gfx11_gfx12<0x026, "V_SUB_U32", "v_sub_nc_u32">;
 defm V_SUBREV_NC_U32 :
-  VOP2_Real_with_name_gfx10_gfx11<0x027, "V_SUBREV_U32", "v_subrev_nc_u32">;
+  VOP2_Real_with_name_gfx10_gfx11_gfx12<0x027, "V_SUBREV_U32", "v_subrev_nc_u32">;
 
 // VOP2 carry-in, carry-out.
 defm V_ADD_CO_CI_U32 :
@@ -1929,7 +2095,10 @@ multiclass VOP2_Real_gfx6_gfx7_gfx10<bits<6> op> :
   VOP2_Real_gfx6_gfx7<op>, VOP2_Real_gfx10<op>;
 
 multiclass VOP2_Real_gfx6_gfx7_gfx10_gfx11<bits<6> op> :
-  VOP2_Real_gfx6_gfx7_gfx10<op>, VOP2_Real_FULL_gfx11<op>;
+  VOP2_Real_gfx6_gfx7_gfx10<op>, VOP2_Real_FULL<GFX11Gen, op>;
+
+multiclass VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<bits<6> op> :
+  VOP2_Real_gfx6_gfx7_gfx10_gfx11<op>, VOP2_Real_FULL<GFX12Gen, op>;
 
 multiclass VOP2be_Real_gfx6_gfx7<bits<6> op> :
   VOP2_Real_e32_gfx6_gfx7<op>, VOP2be_Real_e64_gfx6_gfx7<op>;
@@ -1991,28 +2160,28 @@ let SubtargetPredicate = isGFX6GFX7 in {
   def : VOP2e64InstAlias<V_SUBREV_CO_U32_e64, V_SUBREV_I32_e64_gfx6_gfx7>;
 } // End SubtargetPredicate = isGFX6GFX7
 
-defm V_ADD_F32            : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x003>;
-defm V_SUB_F32            : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x004>;
-defm V_SUBREV_F32         : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x005>;
+defm V_ADD_F32            : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x003>;
+defm V_SUB_F32            : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x004>;
+defm V_SUBREV_F32         : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x005>;
 defm V_MAC_LEGACY_F32     : VOP2_Real_gfx6_gfx7_gfx10<0x006>;
 defm V_MUL_LEGACY_F32     : VOP2_Real_gfx6_gfx7_gfx10<0x007>;
-defm V_MUL_F32            : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x008>;
-defm V_MUL_I32_I24        : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x009>;
-defm V_MUL_HI_I32_I24     : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x00a>;
-defm V_MUL_U32_U24        : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x00b>;
-defm V_MUL_HI_U32_U24     : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x00c>;
+defm V_MUL_F32            : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x008>;
+defm V_MUL_I32_I24        : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x009>;
+defm V_MUL_HI_I32_I24     : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x00a>;
+defm V_MUL_U32_U24        : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x00b>;
+defm V_MUL_HI_U32_U24     : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x00c>;
 defm V_MIN_F32            : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x00f>;
 defm V_MAX_F32            : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x010>;
-defm V_MIN_I32            : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x011>;
-defm V_MAX_I32            : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x012>;
-defm V_MIN_U32            : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x013>;
-defm V_MAX_U32            : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x014>;
+defm V_MIN_I32            : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x011>;
+defm V_MAX_I32            : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x012>;
+defm V_MIN_U32            : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x013>;
+defm V_MAX_U32            : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x014>;
 defm V_LSHRREV_B32        : VOP2_Real_gfx6_gfx7_gfx10<0x016>;
 defm V_ASHRREV_I32        : VOP2_Real_gfx6_gfx7_gfx10<0x018>;
 defm V_LSHLREV_B32        : VOP2_Real_gfx6_gfx7_gfx10<0x01a>;
-defm V_AND_B32            : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x01b>;
-defm V_OR_B32             : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x01c>;
-defm V_XOR_B32            : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x01d>;
+defm V_AND_B32            : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x01b>;
+defm V_OR_B32             : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x01c>;
+defm V_XOR_B32            : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x01d>;
 defm V_MAC_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x01f>;
 defm V_CVT_PKRTZ_F16_F32  : VOP2_Real_gfx6_gfx7_gfx10<0x02f>;
 defm V_MADMK_F32          : VOP2Only_Real_MADK_gfx6_gfx7_gfx10<0x020>;
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index a73042f2e411..617773b34ae9 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -144,11 +144,15 @@ defm V_LERP_U8 : VOP3Inst <"v_lerp_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_a
 let SchedRW = [WriteDoubleAdd] in {
 let FPDPRounding = 1 in {
 defm V_FMA_F64 : VOP3Inst <"v_fma_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, any_fma>;
+let SubtargetPredicate = isNotGFX12Plus in {
 defm V_ADD_F64 : VOP3Inst <"v_add_f64", VOP3_Profile<VOP_F64_F64_F64>, any_fadd>;
 defm V_MUL_F64 : VOP3Inst <"v_mul_f64", VOP3_Profile<VOP_F64_F64_F64>, any_fmul>;
+} // End SubtargetPredicate = isNotGFX12Plus
 } // End FPDPRounding = 1
+let SubtargetPredicate = isNotGFX12Plus in {
 defm V_MIN_F64 : VOP3Inst <"v_min_f64", VOP3_Profile<VOP_F64_F64_F64>, fminnum_like>;
 defm V_MAX_F64 : VOP3Inst <"v_max_f64", VOP3_Profile<VOP_F64_F64_F64>, fmaxnum_like>;
+} // End SubtargetPredicate = isNotGFX12Plus
 } // End SchedRW = [WriteDoubleAdd]
 
 let SchedRW = [WriteIntMul] in {
@@ -254,10 +258,13 @@ let SchedRW = [Write64Bit] in {
   } // End SubtargetPredicate = isGFX6GFX7
 
   let SubtargetPredicate = isGFX8Plus in {
-  defm V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>, clshl_rev_64>;
   defm V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP3_Profile<VOP_I64_I32_I64>, clshr_rev_64>;
   defm V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>, cashr_rev_64>;
   } // End SubtargetPredicate = isGFX8Plus
+
+  let SubtargetPredicate = isGFX8GFX9GFX10GFX11 in {
+  defm V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>, clshl_rev_64>;
+  } // End SubtargetPredicate = isGFX8GFX9GFX10GFX11
 } // End SchedRW = [Write64Bit]
 } // End isReMaterializable = 1
 
@@ -848,125 +855,168 @@ def : IntClampPat<V_MQSAD_U32_U8_e64, int_amdgcn_mqsad_u32_u8>;
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
-// GFX11.
+// GFX12.
+//===----------------------------------------------------------------------===//
+
+defm V_MIN3_NUM_F32       : VOP3_Realtriple_with_name_gfx12<0x229, "V_MIN3_F32", "v_min3_num_f32">;
+defm V_MAX3_NUM_F32       : VOP3_Realtriple_with_name_gfx12<0x22a, "V_MAX3_F32", "v_max3_num_f32">;
+defm V_MIN3_NUM_F16       : VOP3_Realtriple_with_name_gfx12<0x22b, "V_MIN3_F16", "v_min3_num_f16">;
+defm V_MAX3_NUM_F16       : VOP3_Realtriple_with_name_gfx12<0x22c, "V_MAX3_F16", "v_max3_num_f16">;
+defm V_MED3_NUM_F32       : VOP3_Realtriple_with_name_gfx12<0x231, "V_MED3_F32", "v_med3_num_f32">;
+defm V_MED3_NUM_F16       : VOP3_Realtriple_with_name_gfx12<0x232, "V_MED3_F16", "v_med3_num_f16">;
+defm V_MINMAX_NUM_F32     : VOP3_Realtriple_with_name_gfx12<0x268, "V_MINMAX_F32", "v_minmax_num_f32">;
+defm V_MAXMIN_NUM_F32     : VOP3_Realtriple_with_name_gfx12<0x269, "V_MAXMIN_F32", "v_maxmin_num_f32">;
+defm V_MINMAX_NUM_F16     : VOP3_Realtriple_with_name_gfx12<0x26a, "V_MINMAX_F16", "v_minmax_num_f16">;
+defm V_MAXMIN_NUM_F16     : VOP3_Realtriple_with_name_gfx12<0x26b, "V_MAXMIN_F16", "v_maxmin_num_f16">;
+defm V_MAD_CO_U64_U32     : VOP3be_Real_with_name_gfx12<0x2fe, "V_MAD_U64_U32", "v_mad_co_u64_u32">;
+defm V_MAD_CO_I64_I32     : VOP3be_Real_with_name_gfx12<0x2ff, "V_MAD_I64_I32", "v_mad_co_i64_i32">;
+
+//===----------------------------------------------------------------------===//
+// GFX11, GFX12
 //===----------------------------------------------------------------------===//
 
-defm V_FMA_DX9_ZERO_F32    : VOP3_Real_with_name_gfx11<0x209, "V_FMA_LEGACY_F32", "v_fma_dx9_zero_f32">;
-defm V_MAD_I32_I24         : VOP3_Realtriple_gfx11<0x20a>;
-defm V_MAD_U32_U24         : VOP3_Realtriple_gfx11<0x20b>;
-defm V_CUBEID_F32          : VOP3_Realtriple_gfx11<0x20c>;
-defm V_CUBESC_F32          : VOP3_Realtriple_gfx11<0x20d>;
-defm V_CUBETC_F32          : VOP3_Realtriple_gfx11<0x20e>;
-defm V_CUBEMA_F32          : VOP3_Realtriple_gfx11<0x20f>;
-defm V_BFE_U32             : VOP3_Realtriple_gfx11<0x210>;
-defm V_BFE_I32             : VOP3_Realtriple_gfx11<0x211>;
-defm V_BFI_B32             : VOP3_Realtriple_gfx11<0x212>;
-defm V_FMA_F32             : VOP3_Realtriple_gfx11<0x213>;
-defm V_FMA_F64             : VOP3_Real_Base_gfx11<0x214>;
-defm V_LERP_U8             : VOP3_Realtriple_gfx11<0x215>;
-defm V_ALIGNBIT_B32        : VOP3_Realtriple_gfx11<0x216>;
-defm V_ALIGNBYTE_B32       : VOP3_Realtriple_gfx11<0x217>;
-defm V_MULLIT_F32          : VOP3_Realtriple_gfx11<0x218>;
+multiclass VOP3_Real_with_name_gfx11_gfx12<bits<10> op, string opName,
+                                           string asmName> :
+  VOP3_Real_with_name<GFX11Gen, op, opName, asmName>,
+  VOP3_Real_with_name<GFX12Gen, op, opName, asmName>;
+
+multiclass VOP3_Realtriple_gfx11_gfx12<bits<10> op> :
+  VOP3_Realtriple<GFX11Gen, op>, VOP3_Realtriple<GFX12Gen, op>;
+
+multiclass VOP3_Real_Base_gfx11_gfx12<bits<10> op> :
+  VOP3_Real_Base<GFX11Gen, op>, VOP3_Real_Base<GFX12Gen, op>;
+
+multiclass VOP3_Realtriple_with_name_gfx11_gfx12<bits<10> op, string opName,
+                                                 string asmName> :
+  VOP3_Realtriple_with_name<GFX11Gen, op, opName, asmName>,
+  VOP3_Realtriple_with_name<GFX12Gen, op, opName, asmName>;
+
+multiclass VOP3Dot_Realtriple_gfx11_gfx12<bits<10> op> :
+  VOP3Dot_Realtriple<GFX11Gen, op>, VOP3Dot_Realtriple<GFX12Gen, op>;
+
+multiclass VOP3be_Real_gfx11_gfx12<bits<10> op, string opName, string asmName> :
+  VOP3be_Real<GFX11Gen, op, opName, asmName>,
+  VOP3be_Real<GFX12Gen, op, opName, asmName>;
+
+multiclass VOP3_Real_No_Suffix_gfx11_gfx12<bits<10> op> :
+  VOP3_Real_No_Suffix<GFX11Gen, op>, VOP3_Real_No_Suffix<GFX12Gen, op>;
+
+defm V_FMA_DX9_ZERO_F32    : VOP3_Real_with_name_gfx11_gfx12<0x209, "V_FMA_LEGACY_F32", "v_fma_dx9_zero_f32">;
+defm V_MAD_I32_I24         : VOP3_Realtriple_gfx11_gfx12<0x20a>;
+defm V_MAD_U32_U24         : VOP3_Realtriple_gfx11_gfx12<0x20b>;
+defm V_CUBEID_F32          : VOP3_Realtriple_gfx11_gfx12<0x20c>;
+defm V_CUBESC_F32          : VOP3_Realtriple_gfx11_gfx12<0x20d>;
+defm V_CUBETC_F32          : VOP3_Realtriple_gfx11_gfx12<0x20e>;
+defm V_CUBEMA_F32          : VOP3_Realtriple_gfx11_gfx12<0x20f>;
+defm V_BFE_U32             : VOP3_Realtriple_gfx11_gfx12<0x210>;
+defm V_BFE_I32             : VOP3_Realtriple_gfx11_gfx12<0x211>;
+defm V_BFI_B32             : VOP3_Realtriple_gfx11_gfx12<0x212>;
+defm V_FMA_F32             : VOP3_Realtriple_gfx11_gfx12<0x213>;
+defm V_FMA_F64             : VOP3_Real_Base_gfx11_gfx12<0x214>;
+defm V_LERP_U8             : VOP3_Realtriple_gfx11_gfx12<0x215>;
+defm V_ALIGNBIT_B32        : VOP3_Realtriple_gfx11_gfx12<0x216>;
+defm V_ALIGNBYTE_B32       : VOP3_Realtriple_gfx11_gfx12<0x217>;
+defm V_MULLIT_F32          : VOP3_Realtriple_gfx11_gfx12<0x218>;
 defm V_MIN3_F32            : VOP3_Realtriple_gfx11<0x219>;
-defm V_MIN3_I32            : VOP3_Realtriple_gfx11<0x21a>;
-defm V_MIN3_U32            : VOP3_Realtriple_gfx11<0x21b>;
+defm V_MIN3_I32            : VOP3_Realtriple_gfx11_gfx12<0x21a>;
+defm V_MIN3_U32            : VOP3_Realtriple_gfx11_gfx12<0x21b>;
 defm V_MAX3_F32            : VOP3_Realtriple_gfx11<0x21c>;
-defm V_MAX3_I32            : VOP3_Realtriple_gfx11<0x21d>;
-defm V_MAX3_U32            : VOP3_Realtriple_gfx11<0x21e>;
+defm V_MAX3_I32            : VOP3_Realtriple_gfx11_gfx12<0x21d>;
+defm V_MAX3_U32            : VOP3_Realtriple_gfx11_gfx12<0x21e>;
 defm V_MED3_F32            : VOP3_Realtriple_gfx11<0x21f>;
-defm V_MED3_I32            : VOP3_Realtriple_gfx11<0x220>;
-defm V_MED3_U32            : VOP3_Realtriple_gfx11<0x221>;
-defm V_SAD_U8              : VOP3_Realtriple_gfx11<0x222>;
-defm V_SAD_HI_U8           : VOP3_Realtriple_gfx11<0x223>;
-defm V_SAD_U16             : VOP3_Realtriple_gfx11<0x224>;
-defm V_SAD_U32             : VOP3_Realtriple_gfx11<0x225>;
-defm V_CVT_PK_U8_F32       : VOP3_Realtriple_gfx11<0x226>;
-defm V_DIV_FIXUP_F32       : VOP3_Real_Base_gfx11<0x227>;
-defm V_DIV_FIXUP_F64       : VOP3_Real_Base_gfx11<0x228>;
-defm V_DIV_FMAS_F32        : VOP3_Real_Base_gfx11<0x237>;
-defm V_DIV_FMAS_F64        : VOP3_Real_Base_gfx11<0x238>;
-defm V_MSAD_U8             : VOP3_Realtriple_gfx11<0x239>;
-defm V_QSAD_PK_U16_U8      : VOP3_Real_Base_gfx11<0x23a>;
-defm V_MQSAD_PK_U16_U8     : VOP3_Real_Base_gfx11<0x23b>;
-defm V_MQSAD_U32_U8        : VOP3_Real_Base_gfx11<0x23d>;
-defm V_XOR3_B32            : VOP3_Realtriple_gfx11<0x240>;
-defm V_MAD_U16             : VOP3_Realtriple_with_name_gfx11<0x241, "V_MAD_U16_gfx9", "v_mad_u16">;
-defm V_PERM_B32            : VOP3_Realtriple_gfx11<0x244>;
-defm V_XAD_U32             : VOP3_Realtriple_gfx11<0x245>;
-defm V_LSHL_ADD_U32        : VOP3_Realtriple_gfx11<0x246>;
-defm V_ADD_LSHL_U32        : VOP3_Realtriple_gfx11<0x247>;
-defm V_FMA_F16             : VOP3_Realtriple_with_name_gfx11<0x248, "V_FMA_F16_gfx9", "v_fma_f16">;
+defm V_MED3_I32            : VOP3_Realtriple_gfx11_gfx12<0x220>;
+defm V_MED3_U32            : VOP3_Realtriple_gfx11_gfx12<0x221>;
+defm V_SAD_U8              : VOP3_Realtriple_gfx11_gfx12<0x222>;
+defm V_SAD_HI_U8           : VOP3_Realtriple_gfx11_gfx12<0x223>;
+defm V_SAD_U16             : VOP3_Realtriple_gfx11_gfx12<0x224>;
+defm V_SAD_U32             : VOP3_Realtriple_gfx11_gfx12<0x225>;
+defm V_CVT_PK_U8_F32       : VOP3_Realtriple_gfx11_gfx12<0x226>;
+defm V_DIV_FIXUP_F32       : VOP3_Real_Base_gfx11_gfx12<0x227>;
+defm V_DIV_FIXUP_F64       : VOP3_Real_Base_gfx11_gfx12<0x228>;
+defm V_DIV_FMAS_F32        : VOP3_Real_Base_gfx11_gfx12<0x237>;
+defm V_DIV_FMAS_F64        : VOP3_Real_Base_gfx11_gfx12<0x238>;
+defm V_MSAD_U8             : VOP3_Realtriple_gfx11_gfx12<0x239>;
+defm V_QSAD_PK_U16_U8      : VOP3_Real_Base_gfx11_gfx12<0x23a>;
+defm V_MQSAD_PK_U16_U8     : VOP3_Real_Base_gfx11_gfx12<0x23b>;
+defm V_MQSAD_U32_U8        : VOP3_Real_Base_gfx11_gfx12<0x23d>;
+defm V_XOR3_B32            : VOP3_Realtriple_gfx11_gfx12<0x240>;
+defm V_MAD_U16             : VOP3_Realtriple_with_name_gfx11_gfx12<0x241, "V_MAD_U16_gfx9", "v_mad_u16">;
+defm V_PERM_B32            : VOP3_Realtriple_gfx11_gfx12<0x244>;
+defm V_XAD_U32             : VOP3_Realtriple_gfx11_gfx12<0x245>;
+defm V_LSHL_ADD_U32        : VOP3_Realtriple_gfx11_gfx12<0x246>;
+defm V_ADD_LSHL_U32        : VOP3_Realtriple_gfx11_gfx12<0x247>;
+defm V_FMA_F16             : VOP3_Realtriple_with_name_gfx11_gfx12<0x248, "V_FMA_F16_gfx9", "v_fma_f16">;
 defm V_MIN3_F16            : VOP3_Realtriple_gfx11<0x249>;
-defm V_MIN3_I16            : VOP3_Realtriple_gfx11<0x24a>;
-defm V_MIN3_U16            : VOP3_Realtriple_gfx11<0x24b>;
+defm V_MIN3_I16            : VOP3_Realtriple_gfx11_gfx12<0x24a>;
+defm V_MIN3_U16            : VOP3_Realtriple_gfx11_gfx12<0x24b>;
 defm V_MAX3_F16            : VOP3_Realtriple_gfx11<0x24c>;
-defm V_MAX3_I16            : VOP3_Realtriple_gfx11<0x24d>;
-defm V_MAX3_U16            : VOP3_Realtriple_gfx11<0x24e>;
+defm V_MAX3_I16            : VOP3_Realtriple_gfx11_gfx12<0x24d>;
+defm V_MAX3_U16            : VOP3_Realtriple_gfx11_gfx12<0x24e>;
 defm V_MED3_F16            : VOP3_Realtriple_gfx11<0x24f>;
-defm V_MED3_I16            : VOP3_Realtriple_gfx11<0x250>;
-defm V_MED3_U16            : VOP3_Realtriple_gfx11<0x251>;
-defm V_MAD_I16             : VOP3_Realtriple_with_name_gfx11<0x253, "V_MAD_I16_gfx9", "v_mad_i16">;
-defm V_DIV_FIXUP_F16       : VOP3_Realtriple_with_name_gfx11<0x254, "V_DIV_FIXUP_F16_gfx9", "v_div_fixup_f16">;
-defm V_ADD3_U32            : VOP3_Realtriple_gfx11<0x255>;
-defm V_LSHL_OR_B32         : VOP3_Realtriple_gfx11<0x256>;
-defm V_AND_OR_B32          : VOP3_Realtriple_gfx11<0x257>;
-defm V_OR3_B32             : VOP3_Realtriple_gfx11<0x258>;
-defm V_MAD_U32_U16         : VOP3_Realtriple_gfx11<0x259>;
-defm V_MAD_I32_I16         : VOP3_Realtriple_gfx11<0x25a>;
-defm V_PERMLANE16_B32      : VOP3_Real_Base_gfx11<0x25b>;
-defm V_PERMLANEX16_B32     : VOP3_Real_Base_gfx11<0x25c>;
+defm V_MED3_I16            : VOP3_Realtriple_gfx11_gfx12<0x250>;
+defm V_MED3_U16            : VOP3_Realtriple_gfx11_gfx12<0x251>;
+defm V_MAD_I16             : VOP3_Realtriple_with_name_gfx11_gfx12<0x253, "V_MAD_I16_gfx9", "v_mad_i16">;
+defm V_DIV_FIXUP_F16       : VOP3_Realtriple_with_name_gfx11_gfx12<0x254, "V_DIV_FIXUP_F16_gfx9", "v_div_fixup_f16">;
+defm V_ADD3_U32            : VOP3_Realtriple_gfx11_gfx12<0x255>;
+defm V_LSHL_OR_B32         : VOP3_Realtriple_gfx11_gfx12<0x256>;
+defm V_AND_OR_B32          : VOP3_Realtriple_gfx11_gfx12<0x257>;
+defm V_OR3_B32             : VOP3_Realtriple_gfx11_gfx12<0x258>;
+defm V_MAD_U32_U16         : VOP3_Realtriple_gfx11_gfx12<0x259>;
+defm V_MAD_I32_I16         : VOP3_Realtriple_gfx11_gfx12<0x25a>;
+defm V_PERMLANE16_B32      : VOP3_Real_Base_gfx11_gfx12<0x25b>;
+defm V_PERMLANEX16_B32     : VOP3_Real_Base_gfx11_gfx12<0x25c>;
 defm V_MAXMIN_F32          : VOP3_Realtriple_gfx11<0x25e>;
 defm V_MINMAX_F32          : VOP3_Realtriple_gfx11<0x25f>;
 defm V_MAXMIN_F16          : VOP3_Realtriple_gfx11<0x260>;
 defm V_MINMAX_F16          : VOP3_Realtriple_gfx11<0x261>;
-defm V_MAXMIN_U32          : VOP3_Realtriple_gfx11<0x262>;
-defm V_MINMAX_U32          : VOP3_Realtriple_gfx11<0x263>;
-defm V_MAXMIN_I32          : VOP3_Realtriple_gfx11<0x264>;
-defm V_MINMAX_I32          : VOP3_Realtriple_gfx11<0x265>;
-defm V_DOT2_F16_F16        : VOP3Dot_Realtriple_gfx11<0x266>;
-defm V_DOT2_BF16_BF16      : VOP3Dot_Realtriple_gfx11<0x267>;
-defm V_DIV_SCALE_F32       : VOP3be_Real_gfx11<0x2fc, "V_DIV_SCALE_F32", "v_div_scale_f32">;
-defm V_DIV_SCALE_F64       : VOP3be_Real_gfx11<0x2fd, "V_DIV_SCALE_F64", "v_div_scale_f64">;
+defm V_MAXMIN_U32          : VOP3_Realtriple_gfx11_gfx12<0x262>;
+defm V_MINMAX_U32          : VOP3_Realtriple_gfx11_gfx12<0x263>;
+defm V_MAXMIN_I32          : VOP3_Realtriple_gfx11_gfx12<0x264>;
+defm V_MINMAX_I32          : VOP3_Realtriple_gfx11_gfx12<0x265>;
+defm V_DOT2_F16_F16        : VOP3Dot_Realtriple_gfx11_gfx12<0x266>;
+defm V_DOT2_BF16_BF16      : VOP3Dot_Realtriple_gfx11_gfx12<0x267>;
+defm V_DIV_SCALE_F32       : VOP3be_Real_gfx11_gfx12<0x2fc, "V_DIV_SCALE_F32", "v_div_scale_f32">;
+defm V_DIV_SCALE_F64       : VOP3be_Real_gfx11_gfx12<0x2fd, "V_DIV_SCALE_F64", "v_div_scale_f64">;
 defm V_MAD_U64_U32_gfx11   : VOP3be_Real_gfx11<0x2fe, "V_MAD_U64_U32_gfx11", "v_mad_u64_u32">;
 defm V_MAD_I64_I32_gfx11   : VOP3be_Real_gfx11<0x2ff, "V_MAD_I64_I32_gfx11", "v_mad_i64_i32">;
-defm V_ADD_NC_U16          : VOP3Only_Realtriple_gfx11<0x303>;
-defm V_SUB_NC_U16          : VOP3Only_Realtriple_gfx11<0x304>;
-defm V_MUL_LO_U16_t16      : VOP3Only_Realtriple_t16_gfx11<0x305, "v_mul_lo_u16">;
-defm V_CVT_PK_I16_F32      : VOP3_Realtriple_gfx11<0x306>;
-defm V_CVT_PK_U16_F32      : VOP3_Realtriple_gfx11<0x307>;
-defm V_MAX_U16_t16         : VOP3Only_Realtriple_t16_gfx11<0x309, "v_max_u16">;
-defm V_MAX_I16_t16         : VOP3Only_Realtriple_t16_gfx11<0x30a, "v_max_i16">;
-defm V_MIN_U16_t16         : VOP3Only_Realtriple_t16_gfx11<0x30b, "v_min_u16">;
-defm V_MIN_I16_t16         : VOP3Only_Realtriple_t16_gfx11<0x30c, "v_min_i16">;
-defm V_ADD_NC_I16          : VOP3_Realtriple_with_name_gfx11<0x30d, "V_ADD_I16", "v_add_nc_i16">;
-defm V_SUB_NC_I16          : VOP3_Realtriple_with_name_gfx11<0x30e, "V_SUB_I16", "v_sub_nc_i16">;
-defm V_PACK_B32_F16        : VOP3_Realtriple_gfx11<0x311>;
-defm V_CVT_PK_NORM_I16_F16 : VOP3_Realtriple_with_name_gfx11<0x312, "V_CVT_PKNORM_I16_F16" , "v_cvt_pk_norm_i16_f16" >;
-defm V_CVT_PK_NORM_U16_F16 : VOP3_Realtriple_with_name_gfx11<0x313, "V_CVT_PKNORM_U16_F16" , "v_cvt_pk_norm_u16_f16" >;
-defm V_SUB_NC_I32          : VOP3_Realtriple_with_name_gfx11<0x325, "V_SUB_I32", "v_sub_nc_i32">;
-defm V_ADD_NC_I32          : VOP3_Realtriple_with_name_gfx11<0x326, "V_ADD_I32", "v_add_nc_i32">;
+defm V_ADD_NC_U16          : VOP3Only_Realtriple_gfx11_gfx12<0x303>;
+defm V_SUB_NC_U16          : VOP3Only_Realtriple_gfx11_gfx12<0x304>;
+defm V_MUL_LO_U16_t16      : VOP3Only_Realtriple_t16_gfx11_gfx12<0x305, "v_mul_lo_u16">;
+defm V_CVT_PK_I16_F32      : VOP3_Realtriple_gfx11_gfx12<0x306>;
+defm V_CVT_PK_U16_F32      : VOP3_Realtriple_gfx11_gfx12<0x307>;
+defm V_MAX_U16_t16         : VOP3Only_Realtriple_t16_gfx11_gfx12<0x309, "v_max_u16">;
+defm V_MAX_I16_t16         : VOP3Only_Realtriple_t16_gfx11_gfx12<0x30a, "v_max_i16">;
+defm V_MIN_U16_t16         : VOP3Only_Realtriple_t16_gfx11_gfx12<0x30b, "v_min_u16">;
+defm V_MIN_I16_t16         : VOP3Only_Realtriple_t16_gfx11_gfx12<0x30c, "v_min_i16">;
+defm V_ADD_NC_I16          : VOP3_Realtriple_with_name_gfx11_gfx12<0x30d, "V_ADD_I16", "v_add_nc_i16">;
+defm V_SUB_NC_I16          : VOP3_Realtriple_with_name_gfx11_gfx12<0x30e, "V_SUB_I16", "v_sub_nc_i16">;
+defm V_PACK_B32_F16        : VOP3_Realtriple_gfx11_gfx12<0x311>;
+defm V_CVT_PK_NORM_I16_F16 : VOP3_Realtriple_with_name_gfx11_gfx12<0x312, "V_CVT_PKNORM_I16_F16" , "v_cvt_pk_norm_i16_f16" >;
+defm V_CVT_PK_NORM_U16_F16 : VOP3_Realtriple_with_name_gfx11_gfx12<0x313, "V_CVT_PKNORM_U16_F16" , "v_cvt_pk_norm_u16_f16" >;
+defm V_SUB_NC_I32          : VOP3_Realtriple_with_name_gfx11_gfx12<0x325, "V_SUB_I32", "v_sub_nc_i32">;
+defm V_ADD_NC_I32          : VOP3_Realtriple_with_name_gfx11_gfx12<0x326, "V_ADD_I32", "v_add_nc_i32">;
 defm V_ADD_F64             : VOP3_Real_Base_gfx11<0x327>;
 defm V_MUL_F64             : VOP3_Real_Base_gfx11<0x328>;
 defm V_MIN_F64             : VOP3_Real_Base_gfx11<0x329>;
 defm V_MAX_F64             : VOP3_Real_Base_gfx11<0x32a>;
-defm V_LDEXP_F64           : VOP3_Real_Base_gfx11<0x32b>;
-defm V_MUL_LO_U32          : VOP3_Real_Base_gfx11<0x32c>;
-defm V_MUL_HI_U32          : VOP3_Real_Base_gfx11<0x32d>;
-defm V_MUL_HI_I32          : VOP3_Real_Base_gfx11<0x32e>;
-defm V_TRIG_PREOP_F64      : VOP3_Real_Base_gfx11<0x32f>;
-defm V_LSHLREV_B16_t16     : VOP3Only_Realtriple_t16_gfx11<0x338, "v_lshlrev_b16">;
-defm V_LSHRREV_B16_t16     : VOP3Only_Realtriple_t16_gfx11<0x339, "v_lshrrev_b16">;
-defm V_ASHRREV_I16_t16     : VOP3Only_Realtriple_t16_gfx11<0x33a, "v_ashrrev_i16">;
+defm V_LDEXP_F64           : VOP3_Real_Base_gfx11_gfx12<0x32b>;
+defm V_MUL_LO_U32          : VOP3_Real_Base_gfx11_gfx12<0x32c>;
+defm V_MUL_HI_U32          : VOP3_Real_Base_gfx11_gfx12<0x32d>;
+defm V_MUL_HI_I32          : VOP3_Real_Base_gfx11_gfx12<0x32e>;
+defm V_TRIG_PREOP_F64      : VOP3_Real_Base_gfx11_gfx12<0x32f>;
+defm V_LSHLREV_B16_t16     : VOP3Only_Realtriple_t16_gfx11_gfx12<0x338, "v_lshlrev_b16">;
+defm V_LSHRREV_B16_t16     : VOP3Only_Realtriple_t16_gfx11_gfx12<0x339, "v_lshrrev_b16">;
+defm V_ASHRREV_I16_t16     : VOP3Only_Realtriple_t16_gfx11_gfx12<0x33a, "v_ashrrev_i16">;
 defm V_LSHLREV_B64         : VOP3_Real_Base_gfx11<0x33c>;
-defm V_LSHRREV_B64         : VOP3_Real_Base_gfx11<0x33d>;
-defm V_ASHRREV_I64         : VOP3_Real_Base_gfx11<0x33e>;
-defm V_READLANE_B32        : VOP3_Real_No_Suffix_gfx11<0x360>; // Pseudo in VOP2
+defm V_LSHRREV_B64         : VOP3_Real_Base_gfx11_gfx12<0x33d>;
+defm V_ASHRREV_I64         : VOP3_Real_Base_gfx11_gfx12<0x33e>;
+defm V_READLANE_B32        : VOP3_Real_No_Suffix_gfx11_gfx12<0x360>; // Pseudo in VOP2
 let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in {
-  defm V_WRITELANE_B32     : VOP3_Real_No_Suffix_gfx11<0x361>; // Pseudo in VOP2
+  defm V_WRITELANE_B32     : VOP3_Real_No_Suffix_gfx11_gfx12<0x361>; // Pseudo in VOP2
 } // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in)
-defm V_AND_B16_t16         : VOP3Only_Realtriple_t16_gfx11<0x362, "v_and_b16">;
-defm V_OR_B16_t16          : VOP3Only_Realtriple_t16_gfx11<0x363, "v_or_b16">;
-defm V_XOR_B16_t16         : VOP3Only_Realtriple_t16_gfx11<0x364, "v_xor_b16">;
+defm V_AND_B16_t16         : VOP3Only_Realtriple_t16_gfx11_gfx12<0x362, "v_and_b16">;
+defm V_OR_B16_t16          : VOP3Only_Realtriple_t16_gfx11_gfx12<0x363, "v_or_b16">;
+defm V_XOR_B16_t16         : VOP3Only_Realtriple_t16_gfx11_gfx12<0x364, "v_xor_b16">;
 
 //===----------------------------------------------------------------------===//
 // GFX10.
diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
index 07f69f68a1cf..eb8990238268 100644
--- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
@@ -940,56 +940,86 @@ class VOP3P_DPP8_Base<bits<7> op, VOP_Pseudo ps, string opName = ps.OpName>
 }
 
 //===----------------------------------------------------------------------===//
-// GFX11.
+// GFX11, GFX12
 //===----------------------------------------------------------------------===//
 
-let AssemblerPredicate = isGFX11Plus,
-    DecoderNamespace = "GFX11" in {
+multiclass VOP3P_Real_Base<GFXGen Gen, bits<7> op, string backing_ps_name = NAME,
+                      string asmName = !cast<VOP3P_Pseudo>(NAME).Mnemonic> {
+  def Gen.Suffix :
+    VOP3P_Real_Gen<!cast<VOP3P_Pseudo>(backing_ps_name), Gen, asmName>,
+    VOP3Pe_gfx11_gfx12<op, !cast<VOP3P_Pseudo>(backing_ps_name).Pfl>;
+}
 
-  multiclass VOP3P_Real_gfx11<bits<7> op, string backing_ps_name = NAME,
-                       string asmName = !cast<VOP3P_Pseudo>(NAME).Mnemonic> {
-    def _gfx11 : VOP3P_Real<!cast<VOP3P_Pseudo>(backing_ps_name),
-                            SIEncodingFamily.GFX11, asmName>,
-                 VOP3Pe_gfx11<op, !cast<VOP3P_Pseudo>(backing_ps_name).Pfl>;
-  }
+multiclass VOP3P_Real_with_name<GFXGen Gen, bits<7> op,
+                          string backing_ps_name = NAME,
+                          string asmName = !cast<VOP3P_Pseudo>(NAME).Mnemonic> {
+  defvar ps = !cast<VOP3P_Pseudo>(backing_ps_name);
+  let AsmString = asmName # ps.AsmOperands in
+    def Gen.Suffix :
+      VOP3P_Real_Gen<!cast<VOP3P_Pseudo>(backing_ps_name), Gen, asmName>,
+      VOP3Pe_gfx11_gfx12<op, !cast<VOP3P_Pseudo>(backing_ps_name).Pfl>,
+      MnemonicAlias<ps.Mnemonic, asmName>, Requires<[Gen.AssemblerPredicate]>;
+}
 
-  multiclass VOP3P_Real_dpp_gfx11<bits<7> op, string backing_ps_name = NAME,
-                       string asmName = !cast<VOP3P_Pseudo>(NAME).Mnemonic> {
-    defvar ps = !cast<VOP3P_Pseudo>(backing_ps_name);
-    def _dpp_gfx11
-        : VOP3P_DPP16<op, !cast<VOP_DPP_Pseudo>(backing_ps_name #"_dpp"),
-                      SIEncodingFamily.GFX11> {
-      let AsmString = asmName #ps.Pfl.AsmVOP3DPP16;
-      let DecoderNamespace = "DPPGFX11";
-    }
+multiclass VOP3P_Real_dpp<GFXGen Gen, bits<7> op, string backing_ps_name = NAME,
+                          string asmName = !cast<VOP3P_Pseudo>(NAME).Mnemonic> {
+  defvar ps = !cast<VOP3P_Pseudo>(backing_ps_name);
+  def _dpp#Gen.Suffix
+      : VOP3P_DPP16<op, !cast<VOP_DPP_Pseudo>(backing_ps_name #"_dpp"),
+                    Gen.Subtarget> {
+    let AsmString = asmName #ps.Pfl.AsmVOP3DPP16;
+    let DecoderNamespace = "DPP"#Gen.DecoderNamespace;
+    let AssemblerPredicate = Gen.AssemblerPredicate;
   }
+}
 
-  multiclass VOP3P_Real_dpp8_gfx11<bits<7> op, string backing_ps_name = NAME,
-                       string asmName = !cast<VOP3P_Pseudo>(NAME).Mnemonic> {
-    defvar ps = !cast<VOP3P_Pseudo>(backing_ps_name);
-    def _dpp8_gfx11 : VOP3P_DPP8_Base<op, ps> {
-      let AsmString = asmName #ps.Pfl.AsmVOP3DPP8;
-      let DecoderNamespace = "DPP8GFX11";
-    }
+multiclass VOP3P_Real_dpp8<GFXGen Gen, bits<7> op, string backing_ps_name = NAME,
+                           string asmName = !cast<VOP3P_Pseudo>(NAME).Mnemonic> {
+  defvar ps = !cast<VOP3P_Pseudo>(backing_ps_name);
+  def _dpp8#Gen.Suffix : VOP3P_DPP8_Base<op, ps> {
+    let AsmString = asmName #ps.Pfl.AsmVOP3DPP8;
+    let DecoderNamespace = "DPP8"#Gen.DecoderNamespace;
+    let AssemblerPredicate = Gen.AssemblerPredicate;
   }
+}
+
+multiclass VOP3P_Realtriple<GFXGen Gen, bits<7> op, string backing_ps_name = NAME,
+                            string asmName = !cast<VOP3P_Pseudo>(NAME).Mnemonic>
+    : VOP3P_Real_Base<Gen, op, backing_ps_name, asmName>,
+      VOP3P_Real_dpp<Gen, op, backing_ps_name, asmName>,
+      VOP3P_Real_dpp8<Gen, op, backing_ps_name, asmName>;
+
+//===----------------------------------------------------------------------===//
+// GFX12
+//===----------------------------------------------------------------------===//
+
+multiclass VOP3P_Real_gfx12<bits<7> op> : VOP3P_Real_Base<GFX12Gen, op>;
+
+multiclass VOP3P_Real_with_name_gfx12<bits<7> op,
+                          string backing_ps_name = NAME,
+                          string asmName = !cast<VOP3P_Pseudo>(NAME).Mnemonic> :
+  VOP3P_Real_with_name<GFX12Gen, op, backing_ps_name, asmName>;
+
+defm V_PK_MIN_NUM_F16 : VOP3P_Real_with_name_gfx12<0x1b, "V_PK_MIN_F16", "v_pk_min_num_f16">;
+defm V_PK_MAX_NUM_F16 : VOP3P_Real_with_name_gfx12<0x1c, "V_PK_MAX_F16", "v_pk_max_num_f16">;
+
+//===----------------------------------------------------------------------===//
+// GFX11
+//===----------------------------------------------------------------------===//
 
-  multiclass VOP3P_Realtriple_gfx11<bits<7> op, string backing_ps_name = NAME,
-                        string asmName = !cast<VOP3P_Pseudo>(NAME).Mnemonic>
-      : VOP3P_Real_gfx11<op, backing_ps_name, asmName>,
-        VOP3P_Real_dpp_gfx11<op, backing_ps_name, asmName>,
-        VOP3P_Real_dpp8_gfx11<op, backing_ps_name, asmName>;
-} // End AssemblerPredicate = isGFX11Plus, DecoderNamespace = "GFX11"
+multiclass VOP3P_Real_gfx11_gfx12<bits<7> op> :
+   VOP3P_Real_Base<GFX11Gen, op>, VOP3P_Real_Base<GFX12Gen, op>;
 
-defm V_DOT4_I32_IU8              : VOP3P_Real_gfx11 <0x16>;
-defm V_DOT8_I32_IU4              : VOP3P_Real_gfx11 <0x18>;
-defm V_DOT2_F32_BF16             : VOP3P_Real_gfx11 <0x1a>;
+defm V_DOT4_I32_IU8  : VOP3P_Real_gfx11_gfx12<0x16>;
+defm V_DOT8_I32_IU4  : VOP3P_Real_gfx11_gfx12<0x18>;
+defm V_DOT2_F32_BF16 : VOP3P_Real_gfx11_gfx12<0x1a>;
 
 multiclass VOP3P_Real_WMMA <bits<7> op> {
   let WaveSizePredicate = isWave32, DecoderNamespace = "GFX11" in {
-    defm _twoaddr_w32 : VOP3P_Real_gfx11 <op>;
+    defm _twoaddr_w32 : VOP3P_Real_Base <GFX11Gen, op>;
   }
   let WaveSizePredicate = isWave64, DecoderNamespace = "WMMAGFX11" in {
-    defm _twoaddr_w64 : VOP3P_Real_gfx11 <op>;
+    defm _twoaddr_w64 : VOP3P_Real_Base <GFX11Gen, op>;
   }
 }
 
@@ -1240,41 +1270,45 @@ let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10", VOP3P = 1 in {
   }
 } // End AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10", VOP3P = 1
 
-multiclass VOP3P_Real_gfx10_gfx11<bits<7> op>
-  : VOP3P_Real_gfx10<op>, VOP3P_Real_gfx11<op>;
-
-multiclass VOP3P_Real_gfx10_gfx11_Triple<bits<7> op>
-  : VOP3P_Real_gfx10<op>, VOP3P_Realtriple_gfx11<op>;
-
-defm V_PK_MAD_I16     : VOP3P_Real_gfx10_gfx11<0x00>;
-defm V_PK_MUL_LO_U16  : VOP3P_Real_gfx10_gfx11<0x01>;
-defm V_PK_ADD_I16     : VOP3P_Real_gfx10_gfx11<0x02>;
-defm V_PK_SUB_I16     : VOP3P_Real_gfx10_gfx11<0x03>;
-defm V_PK_LSHLREV_B16 : VOP3P_Real_gfx10_gfx11<0x04>;
-defm V_PK_LSHRREV_B16 : VOP3P_Real_gfx10_gfx11<0x05>;
-defm V_PK_ASHRREV_I16 : VOP3P_Real_gfx10_gfx11<0x06>;
-defm V_PK_MAX_I16     : VOP3P_Real_gfx10_gfx11<0x07>;
-defm V_PK_MIN_I16     : VOP3P_Real_gfx10_gfx11<0x08>;
-defm V_PK_MAD_U16     : VOP3P_Real_gfx10_gfx11<0x09>;
-defm V_PK_ADD_U16     : VOP3P_Real_gfx10_gfx11<0x0a>;
-defm V_PK_SUB_U16     : VOP3P_Real_gfx10_gfx11<0x0b>;
-defm V_PK_MAX_U16     : VOP3P_Real_gfx10_gfx11<0x0c>;
-defm V_PK_MIN_U16     : VOP3P_Real_gfx10_gfx11<0x0d>;
-defm V_PK_FMA_F16     : VOP3P_Real_gfx10_gfx11<0x0e>;
-defm V_PK_ADD_F16     : VOP3P_Real_gfx10_gfx11<0x0f>;
-defm V_PK_MUL_F16     : VOP3P_Real_gfx10_gfx11<0x10>;
+multiclass VOP3P_Real_gfx10_gfx11<bits<7> op> :
+  VOP3P_Real_gfx10<op>, VOP3P_Real_Base<GFX11Gen, op>;
+
+multiclass VOP3P_Real_gfx10_gfx11_gfx12<bits<7> op> :
+  VOP3P_Real_gfx10_gfx11<op>, VOP3P_Real_Base<GFX12Gen, op>;
+
+multiclass VOP3P_Real_gfx10_gfx11_gfx12_Triple<bits<7> op> :
+  VOP3P_Real_gfx10<op>, VOP3P_Realtriple<GFX11Gen, op>,
+  VOP3P_Realtriple<GFX12Gen, op>;
+
+defm V_PK_MAD_I16     : VOP3P_Real_gfx10_gfx11_gfx12<0x00>;
+defm V_PK_MUL_LO_U16  : VOP3P_Real_gfx10_gfx11_gfx12<0x01>;
+defm V_PK_ADD_I16     : VOP3P_Real_gfx10_gfx11_gfx12<0x02>;
+defm V_PK_SUB_I16     : VOP3P_Real_gfx10_gfx11_gfx12<0x03>;
+defm V_PK_LSHLREV_B16 : VOP3P_Real_gfx10_gfx11_gfx12<0x04>;
+defm V_PK_LSHRREV_B16 : VOP3P_Real_gfx10_gfx11_gfx12<0x05>;
+defm V_PK_ASHRREV_I16 : VOP3P_Real_gfx10_gfx11_gfx12<0x06>;
+defm V_PK_MAX_I16     : VOP3P_Real_gfx10_gfx11_gfx12<0x07>;
+defm V_PK_MIN_I16     : VOP3P_Real_gfx10_gfx11_gfx12<0x08>;
+defm V_PK_MAD_U16     : VOP3P_Real_gfx10_gfx11_gfx12<0x09>;
+defm V_PK_ADD_U16     : VOP3P_Real_gfx10_gfx11_gfx12<0x0a>;
+defm V_PK_SUB_U16     : VOP3P_Real_gfx10_gfx11_gfx12<0x0b>;
+defm V_PK_MAX_U16     : VOP3P_Real_gfx10_gfx11_gfx12<0x0c>;
+defm V_PK_MIN_U16     : VOP3P_Real_gfx10_gfx11_gfx12<0x0d>;
+defm V_PK_FMA_F16     : VOP3P_Real_gfx10_gfx11_gfx12<0x0e>;
+defm V_PK_ADD_F16     : VOP3P_Real_gfx10_gfx11_gfx12<0x0f>;
+defm V_PK_MUL_F16     : VOP3P_Real_gfx10_gfx11_gfx12<0x10>;
 defm V_PK_MIN_F16     : VOP3P_Real_gfx10_gfx11<0x11>;
 defm V_PK_MAX_F16     : VOP3P_Real_gfx10_gfx11<0x12>;
-defm V_FMA_MIX_F32    : VOP3P_Real_gfx10_gfx11_Triple <0x20>;
-defm V_FMA_MIXLO_F16  : VOP3P_Real_gfx10_gfx11_Triple <0x21>;
-defm V_FMA_MIXHI_F16  : VOP3P_Real_gfx10_gfx11_Triple <0x22>;
+defm V_FMA_MIX_F32    : VOP3P_Real_gfx10_gfx11_gfx12_Triple<0x20>;
+defm V_FMA_MIXLO_F16  : VOP3P_Real_gfx10_gfx11_gfx12_Triple<0x21>;
+defm V_FMA_MIXHI_F16  : VOP3P_Real_gfx10_gfx11_gfx12_Triple<0x22>;
 
 defm V_DOT2_I32_I16 : VOP3P_Real_gfx10 <0x14>;
 defm V_DOT2_U32_U16 : VOP3P_Real_gfx10 <0x15>;
 
-defm V_DOT2_F32_F16 : VOP3P_Real_gfx10_gfx11_Triple <0x13>;
-defm V_DOT4_U32_U8  : VOP3P_Real_gfx10_gfx11 <0x17>;
-defm V_DOT8_U32_U4  : VOP3P_Real_gfx10_gfx11 <0x19>;
+defm V_DOT2_F32_F16 : VOP3P_Real_gfx10_gfx11_gfx12_Triple<0x13>;
+defm V_DOT4_U32_U8  : VOP3P_Real_gfx10_gfx11_gfx12<0x17>;
+defm V_DOT8_U32_U4  : VOP3P_Real_gfx10_gfx11_gfx12<0x19>;
 
 defm V_DOT4_I32_I8  : VOP3P_Real_gfx10 <0x16>;
 defm V_DOT8_I32_I4  : VOP3P_Real_gfx10 <0x18>;
diff --git a/llvm/lib/Target/AMDGPU/VOPCInstructions.td b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
index cbea380ab28c..e5b801048e6d 100644
--- a/llvm/lib/Target/AMDGPU/VOPCInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
@@ -1323,53 +1323,52 @@ class VOPC64_DPP8_NoDst<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName>
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
-// GFX11.
+// GFX11, GFX12
 //===----------------------------------------------------------------------===//
 
-let AssemblerPredicate = isGFX11Only in {
-  multiclass VOPC_Real_gfx11<bits<9> op> {
+multiclass VOPC_Real_Base<GFXGen Gen, bits<9> op> {
+  let AssemblerPredicate = Gen.AssemblerPredicate in {
     defvar ps32 = !cast<VOPC_Pseudo>(NAME#"_e32");
     defvar ps64 = !cast<VOP3_Pseudo>(NAME#"_e64");
-    let DecoderNamespace = "GFX11" in {
-      def _e32_gfx11 : VOPC_Real<ps32, SIEncodingFamily.GFX11>,
-                       VOPCe<op{7-0}>;
-      def _e64_gfx11 : VOP3_Real<ps64, SIEncodingFamily.GFX11>,
-                       VOP3a_gfx11<{0, op}, ps64.Pfl> {
+    let DecoderNamespace = Gen.DecoderNamespace in {
+      def _e32#Gen.Suffix : VOPC_Real<ps32, Gen.Subtarget>,
+                            VOPCe<op{7-0}>;
+      def _e64#Gen.Suffix : VOP3_Real<ps64, Gen.Subtarget>,
+                            VOP3a_gfx11_gfx12<{0, op}, ps64.Pfl> {
         // Encoding used for VOPC instructions encoded as VOP3 differs from
         // VOP3e by destination name (sdst) as VOPC doesn't have vector dst.
         bits<8> sdst;
         let Inst{7-0} = sdst;
       }
-    } // End DecoderNamespace = "GFX11"
+    } // End DecoderNamespace = Gen.DecoderNamespace
 
-    defm : VOPCInstAliases<NAME, "gfx11">;
+    defm : VOPCInstAliases<NAME, !substr(Gen.Suffix,1)>;
 
     if ps32.Pfl.HasExtDPP then {
       defvar psDPP = !cast<VOP_DPP_Pseudo>(NAME #"_e32" #"_dpp");
       defvar AsmDPP = ps32.Pfl.AsmDPP16;
-      let DecoderNamespace = "DPPGFX11" in {
-        def _e32_dpp_gfx11 : VOPC_DPP16_SIMC<op{7-0}, psDPP,
-                                             SIEncodingFamily.GFX11>;
-        def _e32_dpp_w32_gfx11 : VOPC_DPP16<op{7-0}, psDPP> {
+      let DecoderNamespace = "DPP"#Gen.DecoderNamespace in {
+        def _e32_dpp#Gen.Suffix : VOPC_DPP16_SIMC<op{7-0}, psDPP, Gen.Subtarget>;
+        def _e32_dpp_w32#Gen.Suffix : VOPC_DPP16<op{7-0}, psDPP> {
           let AsmString = psDPP.OpName # " vcc_lo, " # AsmDPP;
           let isAsmParserOnly = 1;
           let WaveSizePredicate = isWave32;
         }
-        def _e32_dpp_w64_gfx11 : VOPC_DPP16<op{7-0}, psDPP> {
+        def _e32_dpp_w64#Gen.Suffix : VOPC_DPP16<op{7-0}, psDPP> {
           let AsmString = psDPP.OpName # " vcc, " # AsmDPP;
           let isAsmParserOnly = 1;
           let WaveSizePredicate = isWave64;
         }
       }
       defvar AsmDPP8 = ps32.Pfl.AsmDPP8;
-      let DecoderNamespace = "DPP8GFX11" in {
-        def _e32_dpp8_gfx11 : VOPC_DPP8<op{7-0}, ps32>;
-        def _e32_dpp8_w32_gfx11 : VOPC_DPP8<op{7-0}, ps32> {
+      let DecoderNamespace = "DPP8"#Gen.DecoderNamespace in {
+        def _e32_dpp8#Gen.Suffix : VOPC_DPP8<op{7-0}, ps32>;
+        def _e32_dpp8_w32#Gen.Suffix : VOPC_DPP8<op{7-0}, ps32> {
           let AsmString = ps32.OpName # " vcc_lo, " # AsmDPP8;
           let isAsmParserOnly = 1;
           let WaveSizePredicate = isWave32;
         }
-        def _e32_dpp8_w64_gfx11 : VOPC_DPP8<op{7-0}, ps32> {
+        def _e32_dpp8_w64#Gen.Suffix : VOPC_DPP8<op{7-0}, ps32> {
           let AsmString = ps32.OpName # " vcc, " # AsmDPP8;
           let isAsmParserOnly = 1;
           let WaveSizePredicate = isWave64;
@@ -1379,83 +1378,84 @@ let AssemblerPredicate = isGFX11Only in {
     if ps64.Pfl.HasExtVOP3DPP then {
       defvar psDPP = !cast<VOP_DPP_Pseudo>(NAME #"_e64" #"_dpp");
       defvar AsmDPP = ps64.Pfl.AsmVOP3DPP16;
-      let DecoderNamespace = "DPPGFX11" in {
-        def _e64_dpp_gfx11 : VOPC64_DPP16_Dst<{0, op}, psDPP>,
-                             SIMCInstr<psDPP.PseudoInstr, SIEncodingFamily.GFX11>;
-        def _e64_dpp_w32_gfx11 : VOPC64_DPP16_Dst<{0, op}, psDPP> {
+      let DecoderNamespace = "DPP"#Gen.DecoderNamespace in {
+        def _e64_dpp#Gen.Suffix : VOPC64_DPP16_Dst<{0, op}, psDPP>,
+                                  SIMCInstr<psDPP.PseudoInstr, Gen.Subtarget>;
+        def _e64_dpp_w32#Gen.Suffix : VOPC64_DPP16_Dst<{0, op}, psDPP> {
           let AsmString = psDPP.OpName # " vcc_lo, " # AsmDPP;
           let isAsmParserOnly = 1;
           let WaveSizePredicate = isWave32;
         }
-        def _e64_dpp_w64_gfx11 : VOPC64_DPP16_Dst<{0, op}, psDPP> {
+        def _e64_dpp_w64#Gen.Suffix : VOPC64_DPP16_Dst<{0, op}, psDPP> {
           let AsmString = psDPP.OpName # " vcc, " # AsmDPP;
           let isAsmParserOnly = 1;
           let WaveSizePredicate = isWave64;
         }
       }
       defvar AsmDPP8 = ps64.Pfl.AsmVOP3DPP8;
-      let DecoderNamespace = "DPP8GFX11" in {
-        def _e64_dpp8_gfx11 : VOPC64_DPP8_Dst<{0, op}, ps64>;
-        def _e64_dpp8_w32_gfx11 : VOPC64_DPP8_Dst<{0, op}, ps64> {
+      let DecoderNamespace = "DPP8"#Gen.DecoderNamespace in {
+        def _e64_dpp8#Gen.Suffix : VOPC64_DPP8_Dst<{0, op}, ps64>;
+        def _e64_dpp8_w32#Gen.Suffix : VOPC64_DPP8_Dst<{0, op}, ps64> {
           let AsmString = ps32.OpName # " vcc_lo, " # AsmDPP8;
           let isAsmParserOnly = 1;
           let WaveSizePredicate = isWave32;
         }
-        def _e64_dpp8_w64_gfx11 : VOPC64_DPP8_Dst<{0, op}, ps64> {
+        def _e64_dpp8_w64#Gen.Suffix : VOPC64_DPP8_Dst<{0, op}, ps64> {
           let AsmString = ps32.OpName # " vcc, " # AsmDPP8;
           let isAsmParserOnly = 1;
           let WaveSizePredicate = isWave64;
         }
       }
     }
+  } // AssemblerPredicate = Gen.AssemblerPredicate
+}
 
-  }
-
-  multiclass VOPC_Real_with_name_gfx11<bits<9> op, string OpName,
-        string asm_name, string pseudo_mnemonic = ""> {
+multiclass VOPC_Real_with_name<GFXGen Gen, bits<9> op, string OpName,
+                               string asm_name, string pseudo_mnemonic = ""> {
+  let AssemblerPredicate = Gen.AssemblerPredicate in {
     defvar ps32 = !cast<VOPC_Pseudo>(OpName#"_e32");
     defvar ps64 = !cast<VOP3_Pseudo>(OpName#"_e64");
-    let DecoderNamespace = "GFX11" in {
-      def _e32_gfx11 :
+    let DecoderNamespace = Gen.DecoderNamespace in {
+      def _e32#Gen.Suffix :
         // 32 and 64 bit forms of the instruction have _e32 and _e64
         // respectively appended to their assembly mnemonic.
         // _e64 is printed as part of the VOPDstS64orS32 operand, whereas
         // the destination-less 32bit forms add it to the asmString here.
-        VOPC_Real<ps32, SIEncodingFamily.GFX11, asm_name#"_e32">,
+        VOPC_Real<ps32, Gen.Subtarget, asm_name#"_e32">,
         VOPCe<op{7-0}>,
         MnemonicAlias<!if(!empty(pseudo_mnemonic), ps32.Mnemonic,
                           pseudo_mnemonic),
                       asm_name, ps32.AsmVariantName>,
-        Requires<[isGFX11Plus]>;
-      def _e64_gfx11 :
-            VOP3_Real<ps64, SIEncodingFamily.GFX11, asm_name>,
-            VOP3a_gfx11<{0, op}, ps64.Pfl>,
+        Requires<[Gen.AssemblerPredicate]>;
+      def _e64#Gen.Suffix :
+            VOP3_Real<ps64, Gen.Subtarget, asm_name>,
+            VOP3a_gfx11_gfx12<{0, op}, ps64.Pfl>,
             MnemonicAlias<!if(!empty(pseudo_mnemonic), ps64.Mnemonic,
                               pseudo_mnemonic),
                           asm_name, ps64.AsmVariantName>,
-            Requires<[isGFX11Plus]> {
+            Requires<[Gen.AssemblerPredicate]> {
         // Encoding used for VOPC instructions encoded as VOP3 differs from
         // VOP3e by destination name (sdst) as VOPC doesn't have vector dst.
         bits<8> sdst;
         let Inst{7-0} = sdst;
       }
-    } // End DecoderNamespace = "GFX11"
+    } // End DecoderNamespace = Gen.DecoderNamespace
 
-    defm : VOPCInstAliases<OpName, "gfx11", NAME, asm_name>;
+    defm : VOPCInstAliases<OpName, !substr(Gen.Suffix, 1), NAME, asm_name>;
 
     if ps32.Pfl.HasExtDPP then {
       defvar psDPP = !cast<VOP_DPP_Pseudo>(OpName #"_e32" #"_dpp");
       defvar AsmDPP = ps32.Pfl.AsmDPP16;
-      let DecoderNamespace = "DPPGFX11" in {
-        def _e32_dpp_gfx11 : VOPC_DPP16_SIMC<op{7-0}, psDPP,
-                                             SIEncodingFamily.GFX11, asm_name>;
-        def _e32_dpp_w32_gfx11
+      let DecoderNamespace = "DPP"#Gen.DecoderNamespace in {
+        def _e32_dpp#Gen.Suffix : VOPC_DPP16_SIMC<op{7-0}, psDPP,
+                                                  Gen.Subtarget, asm_name>;
+        def _e32_dpp_w32#Gen.Suffix
             : VOPC_DPP16<op{7-0}, psDPP, asm_name> {
           let AsmString = asm_name # " vcc_lo, " # AsmDPP;
           let isAsmParserOnly = 1;
           let WaveSizePredicate = isWave32;
         }
-        def _e32_dpp_w64_gfx11
+        def _e32_dpp_w64#Gen.Suffix
             : VOPC_DPP16<op{7-0}, psDPP, asm_name> {
           let AsmString = asm_name # " vcc, " # AsmDPP;
           let isAsmParserOnly = 1;
@@ -1463,15 +1463,15 @@ let AssemblerPredicate = isGFX11Only in {
         }
       }
       defvar AsmDPP8 = ps32.Pfl.AsmDPP8;
-      let DecoderNamespace = "DPP8GFX11" in {
-        def _e32_dpp8_gfx11 : VOPC_DPP8<op{7-0}, ps32, asm_name>;
-        def _e32_dpp8_w32_gfx11
+      let DecoderNamespace = "DPP8"#Gen.DecoderNamespace in {
+        def _e32_dpp8#Gen.Suffix : VOPC_DPP8<op{7-0}, ps32, asm_name>;
+        def _e32_dpp8_w32#Gen.Suffix
             : VOPC_DPP8<op{7-0}, ps32, asm_name> {
           let AsmString = asm_name # " vcc_lo, " # AsmDPP8;
           let isAsmParserOnly = 1;
           let WaveSizePredicate = isWave32;
         }
-        def _e32_dpp8_w64_gfx11
+        def _e32_dpp8_w64#Gen.Suffix
             : VOPC_DPP8<op{7-0}, ps32, asm_name> {
           let AsmString = asm_name # " vcc, " # AsmDPP8;
           let isAsmParserOnly = 1;
@@ -1483,16 +1483,16 @@ let AssemblerPredicate = isGFX11Only in {
     if ps64.Pfl.HasExtVOP3DPP then {
       defvar psDPP = !cast<VOP_DPP_Pseudo>(OpName #"_e64" #"_dpp");
       defvar AsmDPP = ps64.Pfl.AsmVOP3DPP16;
-      let DecoderNamespace = "DPPGFX11" in {
-        def _e64_dpp_gfx11 : VOPC64_DPP16_Dst<{0, op}, psDPP, asm_name>,
-                             SIMCInstr<psDPP.PseudoInstr, SIEncodingFamily.GFX11>;
-        def _e64_dpp_w32_gfx11
+      let DecoderNamespace = "DPP"#Gen.DecoderNamespace in {
+        def _e64_dpp#Gen.Suffix : VOPC64_DPP16_Dst<{0, op}, psDPP, asm_name>,
+                                  SIMCInstr<psDPP.PseudoInstr, Gen.Subtarget>;
+        def _e64_dpp_w32#Gen.Suffix
             : VOPC64_DPP16_Dst<{0, op}, psDPP, asm_name> {
           let AsmString = asm_name # " vcc_lo, " # AsmDPP;
           let isAsmParserOnly = 1;
           let WaveSizePredicate = isWave32;
         }
-        def _e64_dpp_w64_gfx11
+        def _e64_dpp_w64#Gen.Suffix
             : VOPC64_DPP16_Dst<{0, op}, psDPP, asm_name> {
           let AsmString = asm_name # " vcc, " # AsmDPP;
           let isAsmParserOnly = 1;
@@ -1500,15 +1500,15 @@ let AssemblerPredicate = isGFX11Only in {
         }
       }
       defvar AsmDPP8 = ps64.Pfl.AsmVOP3DPP8;
-      let DecoderNamespace = "DPP8GFX11" in {
-        def _e64_dpp8_gfx11 : VOPC64_DPP8_Dst<{0, op}, ps64, asm_name>;
-        def _e64_dpp8_w32_gfx11
+      let DecoderNamespace = "DPP8"#Gen.DecoderNamespace in {
+        def _e64_dpp8#Gen.Suffix : VOPC64_DPP8_Dst<{0, op}, ps64, asm_name>;
+        def _e64_dpp8_w32#Gen.Suffix
             : VOPC64_DPP8_Dst<{0, op}, ps64, asm_name> {
           let AsmString = asm_name # " vcc_lo, " # AsmDPP8;
           let isAsmParserOnly = 1;
           let WaveSizePredicate = isWave32;
         }
-        def _e64_dpp8_w64_gfx11
+        def _e64_dpp8_w64#Gen.Suffix
             : VOPC64_DPP8_Dst<{0, op}, ps64, asm_name> {
           let AsmString = asm_name # " vcc, " # AsmDPP8;
           let isAsmParserOnly = 1;
@@ -1516,44 +1516,47 @@ let AssemblerPredicate = isGFX11Only in {
         }
       }
     }
-  }
+  } // AssemblerPredicate = Gen.AssemblerPredicate
+}
 
-  multiclass VOPC_Real_t16_gfx11<bits<9> op, string asm_name,
-        string OpName = NAME> : VOPC_Real_with_name_gfx11<op, OpName, asm_name>;
+multiclass VOPC_Real_t16<GFXGen Gen, bits<9> op, string asm_name,
+                         string OpName = NAME, string pseudo_mnemonic = ""> :
+  VOPC_Real_with_name<Gen, op, OpName, asm_name, pseudo_mnemonic>;
 
-  multiclass VOPCX_Real_gfx11<bits<9> op> {
+multiclass VOPCX_Real<GFXGen Gen, bits<9> op> {
+  let AssemblerPredicate = Gen.AssemblerPredicate in {
     defvar ps32 = !cast<VOPC_Pseudo>(NAME#"_nosdst_e32");
     defvar ps64 = !cast<VOP3_Pseudo>(NAME#"_nosdst_e64");
-    let DecoderNamespace = "GFX11" in {
-      def _e32_gfx11 :
-        VOPC_Real<ps32, SIEncodingFamily.GFX11>,
+    let DecoderNamespace = Gen.DecoderNamespace in {
+      def _e32#Gen.Suffix :
+        VOPC_Real<ps32, Gen.Subtarget>,
         VOPCe<op{7-0}> {
           let AsmString = !subst("_nosdst", "", ps32.PseudoInstr)
                           # " " # ps32.AsmOperands;
         }
-      def _e64_gfx11 :
-        VOP3_Real<ps64, SIEncodingFamily.GFX11>,
-        VOP3a_gfx11<{0, op}, ps64.Pfl> {
+      def _e64#Gen.Suffix :
+        VOP3_Real<ps64, Gen.Subtarget>,
+        VOP3a_gfx11_gfx12<{0, op}, ps64.Pfl> {
           let Inst{7-0} = ?; // sdst
           let AsmString = !subst("_nosdst", "", ps64.Mnemonic)
                           # "{_e64} " # ps64.AsmOperands;
         }
-    } // End DecoderNamespace = "GFX11"
+    } // End DecoderNamespace = Gen.DecoderNamespace
 
-    defm : VOPCXInstAliases<NAME, "gfx11">;
+    defm : VOPCXInstAliases<NAME, !substr(Gen.Suffix, 1)>;
 
     if ps32.Pfl.HasExtDPP then {
       defvar psDPP = !cast<VOP_DPP_Pseudo>(NAME #"_nosdst_e32" #"_dpp");
       defvar AsmDPP = ps32.Pfl.AsmDPP16;
-      let DecoderNamespace = "DPPGFX11" in {
-        def _e32_dpp_gfx11
-            : VOPC_DPP16_SIMC<op{7-0}, psDPP, SIEncodingFamily.GFX11> {
+      let DecoderNamespace = "DPP"#Gen.DecoderNamespace in {
+        def _e32_dpp#Gen.Suffix
+            : VOPC_DPP16_SIMC<op{7-0}, psDPP, Gen.Subtarget> {
           let AsmString = !subst("_nosdst", "", psDPP.OpName) # " " # AsmDPP;
         }
       }
       defvar AsmDPP8 = ps32.Pfl.AsmDPP8;
-      let DecoderNamespace = "DPP8GFX11" in {
-        def _e32_dpp8_gfx11 : VOPC_DPP8<op{7-0}, ps32> {
+      let DecoderNamespace = "DPP8"#Gen.DecoderNamespace in {
+        def _e32_dpp8#Gen.Suffix : VOPC_DPP8<op{7-0}, ps32> {
           let AsmString = !subst("_nosdst", "", ps32.OpName) # " " # AsmDPP8;
         }
       }
@@ -1562,268 +1565,305 @@ let AssemblerPredicate = isGFX11Only in {
     if ps64.Pfl.HasExtVOP3DPP then {
       defvar psDPP = !cast<VOP_DPP_Pseudo>(NAME #"_nosdst_e64" #"_dpp");
       defvar AsmDPP = ps64.Pfl.AsmVOP3DPP16;
-      let DecoderNamespace = "DPPGFX11" in {
-        def _e64_dpp_gfx11
+      let DecoderNamespace = "DPP"#Gen.DecoderNamespace in {
+        def _e64_dpp#Gen.Suffix
             : VOPC64_DPP16_NoDst<{0, op}, psDPP>,
-              SIMCInstr<psDPP.PseudoInstr, SIEncodingFamily.GFX11> {
+              SIMCInstr<psDPP.PseudoInstr, Gen.Subtarget> {
           let AsmString = !subst("_nosdst", "", psDPP.OpName)
                           # "{_e64_dpp} " # AsmDPP;
         }
       }
       defvar AsmDPP8 = ps64.Pfl.AsmVOP3DPP8;
-      let DecoderNamespace = "DPP8GFX11" in {
-        def _e64_dpp8_gfx11 : VOPC64_DPP8_NoDst<{0, op}, ps64> {
+      let DecoderNamespace = "DPP8"#Gen.DecoderNamespace in {
+        def _e64_dpp8#Gen.Suffix : VOPC64_DPP8_NoDst<{0, op}, ps64> {
           let AsmString = !subst("_nosdst", "", ps64.OpName)
                           # "{_e64_dpp} " # AsmDPP8;
         }
       }
     }
-  }
+  } // AssemblerPredicate = Gen.AssemblerPredicate
+}
 
-  multiclass VOPCX_Real_with_name_gfx11<bits<9> op, string OpName,
-        string asm_name, string pseudo_mnemonic = ""> {
+multiclass VOPCX_Real_with_name<GFXGen Gen, bits<9> op, string OpName,
+      string asm_name, string pseudo_mnemonic = ""> {
+  let AssemblerPredicate = Gen.AssemblerPredicate in {
     defvar ps32 = !cast<VOPC_Pseudo>(OpName#"_nosdst_e32");
     defvar ps64 = !cast<VOP3_Pseudo>(OpName#"_nosdst_e64");
-    let DecoderNamespace = "GFX11" in {
-      def _e32_gfx11
-          : VOPC_Real<ps32, SIEncodingFamily.GFX11, asm_name>,
+    let DecoderNamespace = Gen.DecoderNamespace in {
+      def _e32#Gen.Suffix
+          : VOPC_Real<ps32, Gen.Subtarget, asm_name>,
             MnemonicAlias<!if(!empty(pseudo_mnemonic), !subst("_nosdst", "", ps32.Mnemonic),
                               pseudo_mnemonic),
                           asm_name, ps32.AsmVariantName>,
-            Requires<[isGFX11Plus]>,
+            Requires<[Gen.AssemblerPredicate]>,
             VOPCe<op{7-0}> {
         let AsmString = asm_name # "{_e32} " # ps32.AsmOperands;
       }
-      def _e64_gfx11
-          : VOP3_Real<ps64, SIEncodingFamily.GFX11, asm_name>,
+      def _e64#Gen.Suffix
+          : VOP3_Real<ps64, Gen.Subtarget, asm_name>,
             MnemonicAlias<!if(!empty(pseudo_mnemonic), !subst("_nosdst", "", ps64.Mnemonic),
                               pseudo_mnemonic),
                           asm_name, ps64.AsmVariantName>,
-            Requires<[isGFX11Plus]>,
-            VOP3a_gfx11<{0, op}, ps64.Pfl> {
+            Requires<[Gen.AssemblerPredicate]>,
+            VOP3a_gfx11_gfx12<{0, op}, ps64.Pfl> {
         let Inst{7-0} = ? ; // sdst
         let AsmString = asm_name # "{_e64} " # ps64.AsmOperands;
       }
-    } // End DecoderNamespace = "GFX11"
+    } // End DecoderNamespace = Gen.DecoderNamespace
 
-    defm : VOPCXInstAliases<OpName, "gfx11", NAME, asm_name>;
+    defm : VOPCXInstAliases<OpName, !substr(Gen.Suffix, 1), NAME, asm_name>;
 
     if ps32.Pfl.HasExtDPP then {
       defvar psDPP = !cast<VOP_DPP_Pseudo>(OpName#"_nosdst_e32"#"_dpp");
-      let DecoderNamespace = "DPPGFX11" in {
-        def _e32_dpp_gfx11 : VOPC_DPP16_SIMC<op{7-0}, psDPP,
-                                             SIEncodingFamily.GFX11, asm_name>;
+      let DecoderNamespace = "DPP"#Gen.DecoderNamespace in {
+        def _e32_dpp#Gen.Suffix : VOPC_DPP16_SIMC<op{7-0}, psDPP,
+                                              Gen.Subtarget, asm_name>;
       }
-      let DecoderNamespace = "DPP8GFX11" in {
-        def _e32_dpp8_gfx11 : VOPC_DPP8<op{7-0}, ps32, asm_name>;
+      let DecoderNamespace = "DPP8"#Gen.DecoderNamespace in {
+        def _e32_dpp8#Gen.Suffix : VOPC_DPP8<op{7-0}, ps32, asm_name>;
       }
     }
     if ps64.Pfl.HasExtVOP3DPP then {
       defvar psDPP = !cast<VOP_DPP_Pseudo>(OpName#"_nosdst_e64"#"_dpp");
       defvar AsmDPP = ps64.Pfl.AsmVOP3DPP16;
-      let DecoderNamespace = "DPPGFX11" in {
-        def _e64_dpp_gfx11
+      let DecoderNamespace = "DPP"#Gen.DecoderNamespace in {
+        def _e64_dpp#Gen.Suffix
             : VOPC64_DPP16_NoDst<{0, op}, psDPP, asm_name>,
-              SIMCInstr<psDPP.PseudoInstr, SIEncodingFamily.GFX11> {
+              SIMCInstr<psDPP.PseudoInstr, Gen.Subtarget> {
           let AsmString = asm_name # "{_e64_dpp} " # AsmDPP;
         }
       }
       defvar AsmDPP8 = ps64.Pfl.AsmVOP3DPP8;
-      let DecoderNamespace = "DPP8GFX11" in {
-        def _e64_dpp8_gfx11 : VOPC64_DPP8_NoDst<{0, op}, ps64, asm_name> {
+      let DecoderNamespace = "DPP8"#Gen.DecoderNamespace in {
+        def _e64_dpp8#Gen.Suffix : VOPC64_DPP8_NoDst<{0, op}, ps64, asm_name> {
           let AsmString = asm_name # "{_e64_dpp} " # AsmDPP8;
         }
       }
     }
-  }
+  } // AssemblerPredicate = Gen.AssemblerPredicate
+}
 
-  multiclass VOPCX_Real_t16_gfx11<bits<9> op, string asm_name,
-        string OpName = NAME> : VOPCX_Real_with_name_gfx11<op, OpName, asm_name>;
+multiclass VOPCX_Real_t16<GFXGen Gen, bits<9> op, string asm_name,
+      string OpName = NAME, string pseudo_mnemonic = ""> :
+  VOPCX_Real_with_name<Gen, op, OpName, asm_name, pseudo_mnemonic>;
 
+multiclass VOPC_Real_gfx11<bits<9> op> : VOPC_Real_Base<GFX11Gen, op>;
 
-} // End AssemblerPredicate = isGFX11Only
+multiclass VOPC_Real_with_name_gfx11<bits<9> op, string OpName, string asm_name,
+                                     string pseudo_mnemonic = "">
+  : VOPC_Real_with_name<GFX11Gen, op, OpName, asm_name, pseudo_mnemonic>;
+
+multiclass VOPCX_Real_gfx11<bits<9> op> : VOPCX_Real<GFX11Gen, op>;
+
+multiclass VOPCX_Real_with_name_gfx11<bits<9> op, string OpName,
+    string asm_name, string pseudo_mnemonic = ""> :
+  VOPCX_Real_with_name<GFX11Gen, op, OpName, asm_name, pseudo_mnemonic>;
+
+multiclass VOPC_Real_gfx11_gfx12<bits<9> op> :
+  VOPC_Real_Base<GFX11Gen, op>, VOPC_Real_Base<GFX12Gen, op>;
+
+multiclass VOPCX_Real_gfx11_gfx12<bits<9> op> :
+  VOPCX_Real<GFX11Gen, op>, VOPCX_Real<GFX12Gen, op>;
+
+multiclass VOPC_Real_t16_gfx11<bits <9> op, string asm_name,
+    string OpName = NAME, string pseudo_mnemonic = ""> :
+  VOPC_Real_t16<GFX11Gen, op, asm_name, OpName, pseudo_mnemonic>;
+
+multiclass VOPC_Real_t16_gfx11_gfx12<bits <9> op, string asm_name,
+    string OpName = NAME, string pseudo_mnemonic = ""> :
+  VOPC_Real_t16<GFX11Gen, op, asm_name, OpName, pseudo_mnemonic>,
+  VOPC_Real_t16<GFX12Gen, op, asm_name, OpName, pseudo_mnemonic>;
+
+multiclass VOPCX_Real_t16_gfx11<bits<9> op, string asm_name,
+    string OpName = NAME, string pseudo_mnemonic = ""> :
+  VOPCX_Real_t16<GFX11Gen, op, asm_name, OpName, pseudo_mnemonic>;
+
+multiclass VOPCX_Real_t16_gfx11_gfx12<bits<9> op, string asm_name,
+    string OpName = NAME, string pseudo_mnemonic = ""> :
+  VOPCX_Real_t16<GFX11Gen, op, asm_name, OpName, pseudo_mnemonic>,
+  VOPCX_Real_t16<GFX12Gen, op, asm_name, OpName, pseudo_mnemonic>;
 
 defm V_CMP_F_F16_t16      : VOPC_Real_t16_gfx11<0x000, "v_cmp_f_f16">;
-defm V_CMP_LT_F16_t16     : VOPC_Real_t16_gfx11<0x001, "v_cmp_lt_f16">;
-defm V_CMP_EQ_F16_t16     : VOPC_Real_t16_gfx11<0x002, "v_cmp_eq_f16">;
-defm V_CMP_LE_F16_t16     : VOPC_Real_t16_gfx11<0x003, "v_cmp_le_f16">;
-defm V_CMP_GT_F16_t16     : VOPC_Real_t16_gfx11<0x004, "v_cmp_gt_f16">;
-defm V_CMP_LG_F16_t16     : VOPC_Real_t16_gfx11<0x005, "v_cmp_lg_f16">;
-defm V_CMP_GE_F16_t16     : VOPC_Real_t16_gfx11<0x006, "v_cmp_ge_f16">;
-defm V_CMP_O_F16_t16      : VOPC_Real_t16_gfx11<0x007, "v_cmp_o_f16">;
-defm V_CMP_U_F16_t16      : VOPC_Real_t16_gfx11<0x008, "v_cmp_u_f16">;
-defm V_CMP_NGE_F16_t16    : VOPC_Real_t16_gfx11<0x009, "v_cmp_nge_f16">;
-defm V_CMP_NLG_F16_t16    : VOPC_Real_t16_gfx11<0x00a, "v_cmp_nlg_f16">;
-defm V_CMP_NGT_F16_t16    : VOPC_Real_t16_gfx11<0x00b, "v_cmp_ngt_f16">;
-defm V_CMP_NLE_F16_t16    : VOPC_Real_t16_gfx11<0x00c, "v_cmp_nle_f16">;
-defm V_CMP_NEQ_F16_t16    : VOPC_Real_t16_gfx11<0x00d, "v_cmp_neq_f16">;
-defm V_CMP_NLT_F16_t16    : VOPC_Real_t16_gfx11<0x00e, "v_cmp_nlt_f16">;
+defm V_CMP_LT_F16_t16     : VOPC_Real_t16_gfx11_gfx12<0x001, "v_cmp_lt_f16">;
+defm V_CMP_EQ_F16_t16     : VOPC_Real_t16_gfx11_gfx12<0x002, "v_cmp_eq_f16">;
+defm V_CMP_LE_F16_t16     : VOPC_Real_t16_gfx11_gfx12<0x003, "v_cmp_le_f16">;
+defm V_CMP_GT_F16_t16     : VOPC_Real_t16_gfx11_gfx12<0x004, "v_cmp_gt_f16">;
+defm V_CMP_LG_F16_t16     : VOPC_Real_t16_gfx11_gfx12<0x005, "v_cmp_lg_f16">;
+defm V_CMP_GE_F16_t16     : VOPC_Real_t16_gfx11_gfx12<0x006, "v_cmp_ge_f16">;
+defm V_CMP_O_F16_t16      : VOPC_Real_t16_gfx11_gfx12<0x007, "v_cmp_o_f16">;
+defm V_CMP_U_F16_t16      : VOPC_Real_t16_gfx11_gfx12<0x008, "v_cmp_u_f16">;
+defm V_CMP_NGE_F16_t16    : VOPC_Real_t16_gfx11_gfx12<0x009, "v_cmp_nge_f16">;
+defm V_CMP_NLG_F16_t16    : VOPC_Real_t16_gfx11_gfx12<0x00a, "v_cmp_nlg_f16">;
+defm V_CMP_NGT_F16_t16    : VOPC_Real_t16_gfx11_gfx12<0x00b, "v_cmp_ngt_f16">;
+defm V_CMP_NLE_F16_t16    : VOPC_Real_t16_gfx11_gfx12<0x00c, "v_cmp_nle_f16">;
+defm V_CMP_NEQ_F16_t16    : VOPC_Real_t16_gfx11_gfx12<0x00d, "v_cmp_neq_f16">;
+defm V_CMP_NLT_F16_t16    : VOPC_Real_t16_gfx11_gfx12<0x00e, "v_cmp_nlt_f16">;
 defm V_CMP_T_F16_t16      : VOPC_Real_with_name_gfx11<0x00f, "V_CMP_TRU_F16_t16", "v_cmp_t_f16", "v_cmp_tru_f16">;
 defm V_CMP_F_F32      : VOPC_Real_gfx11<0x010>;
-defm V_CMP_LT_F32     : VOPC_Real_gfx11<0x011>;
-defm V_CMP_EQ_F32     : VOPC_Real_gfx11<0x012>;
-defm V_CMP_LE_F32     : VOPC_Real_gfx11<0x013>;
-defm V_CMP_GT_F32     : VOPC_Real_gfx11<0x014>;
-defm V_CMP_LG_F32     : VOPC_Real_gfx11<0x015>;
-defm V_CMP_GE_F32     : VOPC_Real_gfx11<0x016>;
-defm V_CMP_O_F32      : VOPC_Real_gfx11<0x017>;
-defm V_CMP_U_F32      : VOPC_Real_gfx11<0x018>;
-defm V_CMP_NGE_F32    : VOPC_Real_gfx11<0x019>;
-defm V_CMP_NLG_F32    : VOPC_Real_gfx11<0x01a>;
-defm V_CMP_NGT_F32    : VOPC_Real_gfx11<0x01b>;
-defm V_CMP_NLE_F32    : VOPC_Real_gfx11<0x01c>;
-defm V_CMP_NEQ_F32    : VOPC_Real_gfx11<0x01d>;
-defm V_CMP_NLT_F32    : VOPC_Real_gfx11<0x01e>;
+defm V_CMP_LT_F32     : VOPC_Real_gfx11_gfx12<0x011>;
+defm V_CMP_EQ_F32     : VOPC_Real_gfx11_gfx12<0x012>;
+defm V_CMP_LE_F32     : VOPC_Real_gfx11_gfx12<0x013>;
+defm V_CMP_GT_F32     : VOPC_Real_gfx11_gfx12<0x014>;
+defm V_CMP_LG_F32     : VOPC_Real_gfx11_gfx12<0x015>;
+defm V_CMP_GE_F32     : VOPC_Real_gfx11_gfx12<0x016>;
+defm V_CMP_O_F32      : VOPC_Real_gfx11_gfx12<0x017>;
+defm V_CMP_U_F32      : VOPC_Real_gfx11_gfx12<0x018>;
+defm V_CMP_NGE_F32    : VOPC_Real_gfx11_gfx12<0x019>;
+defm V_CMP_NLG_F32    : VOPC_Real_gfx11_gfx12<0x01a>;
+defm V_CMP_NGT_F32    : VOPC_Real_gfx11_gfx12<0x01b>;
+defm V_CMP_NLE_F32    : VOPC_Real_gfx11_gfx12<0x01c>;
+defm V_CMP_NEQ_F32    : VOPC_Real_gfx11_gfx12<0x01d>;
+defm V_CMP_NLT_F32    : VOPC_Real_gfx11_gfx12<0x01e>;
 defm V_CMP_T_F32      : VOPC_Real_with_name_gfx11<0x01f, "V_CMP_TRU_F32", "v_cmp_t_f32">;
 defm V_CMP_T_F64      : VOPC_Real_with_name_gfx11<0x02f, "V_CMP_TRU_F64", "v_cmp_t_f64">;
-defm V_CMP_LT_I16_t16     : VOPC_Real_t16_gfx11<0x031, "v_cmp_lt_i16">;
-defm V_CMP_EQ_I16_t16     : VOPC_Real_t16_gfx11<0x032, "v_cmp_eq_i16">;
-defm V_CMP_LE_I16_t16     : VOPC_Real_t16_gfx11<0x033, "v_cmp_le_i16">;
-defm V_CMP_GT_I16_t16     : VOPC_Real_t16_gfx11<0x034, "v_cmp_gt_i16">;
-defm V_CMP_NE_I16_t16     : VOPC_Real_t16_gfx11<0x035, "v_cmp_ne_i16">;
-defm V_CMP_GE_I16_t16     : VOPC_Real_t16_gfx11<0x036, "v_cmp_ge_i16">;
-defm V_CMP_LT_U16_t16     : VOPC_Real_t16_gfx11<0x039, "v_cmp_lt_u16">;
-defm V_CMP_EQ_U16_t16     : VOPC_Real_t16_gfx11<0x03a, "v_cmp_eq_u16">;
-defm V_CMP_LE_U16_t16     : VOPC_Real_t16_gfx11<0x03b, "v_cmp_le_u16">;
-defm V_CMP_GT_U16_t16     : VOPC_Real_t16_gfx11<0x03c, "v_cmp_gt_u16">;
-defm V_CMP_NE_U16_t16     : VOPC_Real_t16_gfx11<0x03d, "v_cmp_ne_u16">;
-defm V_CMP_GE_U16_t16     : VOPC_Real_t16_gfx11<0x03e, "v_cmp_ge_u16">;
+defm V_CMP_LT_I16_t16     : VOPC_Real_t16_gfx11_gfx12<0x031, "v_cmp_lt_i16">;
+defm V_CMP_EQ_I16_t16     : VOPC_Real_t16_gfx11_gfx12<0x032, "v_cmp_eq_i16">;
+defm V_CMP_LE_I16_t16     : VOPC_Real_t16_gfx11_gfx12<0x033, "v_cmp_le_i16">;
+defm V_CMP_GT_I16_t16     : VOPC_Real_t16_gfx11_gfx12<0x034, "v_cmp_gt_i16">;
+defm V_CMP_NE_I16_t16     : VOPC_Real_t16_gfx11_gfx12<0x035, "v_cmp_ne_i16">;
+defm V_CMP_GE_I16_t16     : VOPC_Real_t16_gfx11_gfx12<0x036, "v_cmp_ge_i16">;
+defm V_CMP_LT_U16_t16     : VOPC_Real_t16_gfx11_gfx12<0x039, "v_cmp_lt_u16">;
+defm V_CMP_EQ_U16_t16     : VOPC_Real_t16_gfx11_gfx12<0x03a, "v_cmp_eq_u16">;
+defm V_CMP_LE_U16_t16     : VOPC_Real_t16_gfx11_gfx12<0x03b, "v_cmp_le_u16">;
+defm V_CMP_GT_U16_t16     : VOPC_Real_t16_gfx11_gfx12<0x03c, "v_cmp_gt_u16">;
+defm V_CMP_NE_U16_t16     : VOPC_Real_t16_gfx11_gfx12<0x03d, "v_cmp_ne_u16">;
+defm V_CMP_GE_U16_t16     : VOPC_Real_t16_gfx11_gfx12<0x03e, "v_cmp_ge_u16">;
 defm V_CMP_F_I32      : VOPC_Real_gfx11<0x040>;
-defm V_CMP_LT_I32     : VOPC_Real_gfx11<0x041>;
-defm V_CMP_EQ_I32     : VOPC_Real_gfx11<0x042>;
-defm V_CMP_LE_I32     : VOPC_Real_gfx11<0x043>;
-defm V_CMP_GT_I32     : VOPC_Real_gfx11<0x044>;
-defm V_CMP_NE_I32     : VOPC_Real_gfx11<0x045>;
-defm V_CMP_GE_I32     : VOPC_Real_gfx11<0x046>;
+defm V_CMP_LT_I32     : VOPC_Real_gfx11_gfx12<0x041>;
+defm V_CMP_EQ_I32     : VOPC_Real_gfx11_gfx12<0x042>;
+defm V_CMP_LE_I32     : VOPC_Real_gfx11_gfx12<0x043>;
+defm V_CMP_GT_I32     : VOPC_Real_gfx11_gfx12<0x044>;
+defm V_CMP_NE_I32     : VOPC_Real_gfx11_gfx12<0x045>;
+defm V_CMP_GE_I32     : VOPC_Real_gfx11_gfx12<0x046>;
 defm V_CMP_T_I32      : VOPC_Real_gfx11<0x047>;
 defm V_CMP_F_U32      : VOPC_Real_gfx11<0x048>;
-defm V_CMP_LT_U32     : VOPC_Real_gfx11<0x049>;
-defm V_CMP_EQ_U32     : VOPC_Real_gfx11<0x04a>;
-defm V_CMP_LE_U32     : VOPC_Real_gfx11<0x04b>;
-defm V_CMP_GT_U32     : VOPC_Real_gfx11<0x04c>;
-defm V_CMP_NE_U32     : VOPC_Real_gfx11<0x04d>;
-defm V_CMP_GE_U32     : VOPC_Real_gfx11<0x04e>;
+defm V_CMP_LT_U32     : VOPC_Real_gfx11_gfx12<0x049>;
+defm V_CMP_EQ_U32     : VOPC_Real_gfx11_gfx12<0x04a>;
+defm V_CMP_LE_U32     : VOPC_Real_gfx11_gfx12<0x04b>;
+defm V_CMP_GT_U32     : VOPC_Real_gfx11_gfx12<0x04c>;
+defm V_CMP_NE_U32     : VOPC_Real_gfx11_gfx12<0x04d>;
+defm V_CMP_GE_U32     : VOPC_Real_gfx11_gfx12<0x04e>;
 defm V_CMP_T_U32      : VOPC_Real_gfx11<0x04f>;
 
 defm V_CMP_F_I64      : VOPC_Real_gfx11<0x050>;
-defm V_CMP_LT_I64     : VOPC_Real_gfx11<0x051>;
-defm V_CMP_EQ_I64     : VOPC_Real_gfx11<0x052>;
-defm V_CMP_LE_I64     : VOPC_Real_gfx11<0x053>;
-defm V_CMP_GT_I64     : VOPC_Real_gfx11<0x054>;
-defm V_CMP_NE_I64     : VOPC_Real_gfx11<0x055>;
-defm V_CMP_GE_I64     : VOPC_Real_gfx11<0x056>;
+defm V_CMP_LT_I64     : VOPC_Real_gfx11_gfx12<0x051>;
+defm V_CMP_EQ_I64     : VOPC_Real_gfx11_gfx12<0x052>;
+defm V_CMP_LE_I64     : VOPC_Real_gfx11_gfx12<0x053>;
+defm V_CMP_GT_I64     : VOPC_Real_gfx11_gfx12<0x054>;
+defm V_CMP_NE_I64     : VOPC_Real_gfx11_gfx12<0x055>;
+defm V_CMP_GE_I64     : VOPC_Real_gfx11_gfx12<0x056>;
 defm V_CMP_T_I64      : VOPC_Real_gfx11<0x057>;
 defm V_CMP_F_U64      : VOPC_Real_gfx11<0x058>;
-defm V_CMP_LT_U64     : VOPC_Real_gfx11<0x059>;
-defm V_CMP_EQ_U64     : VOPC_Real_gfx11<0x05a>;
-defm V_CMP_LE_U64     : VOPC_Real_gfx11<0x05b>;
-defm V_CMP_GT_U64     : VOPC_Real_gfx11<0x05c>;
-defm V_CMP_NE_U64     : VOPC_Real_gfx11<0x05d>;
-defm V_CMP_GE_U64     : VOPC_Real_gfx11<0x05e>;
+defm V_CMP_LT_U64     : VOPC_Real_gfx11_gfx12<0x059>;
+defm V_CMP_EQ_U64     : VOPC_Real_gfx11_gfx12<0x05a>;
+defm V_CMP_LE_U64     : VOPC_Real_gfx11_gfx12<0x05b>;
+defm V_CMP_GT_U64     : VOPC_Real_gfx11_gfx12<0x05c>;
+defm V_CMP_NE_U64     : VOPC_Real_gfx11_gfx12<0x05d>;
+defm V_CMP_GE_U64     : VOPC_Real_gfx11_gfx12<0x05e>;
 defm V_CMP_T_U64      : VOPC_Real_gfx11<0x05f>;
 
-defm V_CMP_CLASS_F16_t16  : VOPC_Real_t16_gfx11<0x07d, "v_cmp_class_f16">;
-defm V_CMP_CLASS_F32  : VOPC_Real_gfx11<0x07e>;
-defm V_CMP_CLASS_F64  : VOPC_Real_gfx11<0x07f>;
+defm V_CMP_CLASS_F16_t16 : VOPC_Real_t16_gfx11_gfx12<0x07d, "v_cmp_class_f16">;
+defm V_CMP_CLASS_F32     : VOPC_Real_gfx11_gfx12<0x07e>;
+defm V_CMP_CLASS_F64     : VOPC_Real_gfx11_gfx12<0x07f>;
 
 defm V_CMPX_F_F16_t16     : VOPCX_Real_t16_gfx11<0x080, "v_cmpx_f_f16">;
-defm V_CMPX_LT_F16_t16    : VOPCX_Real_t16_gfx11<0x081, "v_cmpx_lt_f16">;
-defm V_CMPX_EQ_F16_t16    : VOPCX_Real_t16_gfx11<0x082, "v_cmpx_eq_f16">;
-defm V_CMPX_LE_F16_t16    : VOPCX_Real_t16_gfx11<0x083, "v_cmpx_le_f16">;
-defm V_CMPX_GT_F16_t16    : VOPCX_Real_t16_gfx11<0x084, "v_cmpx_gt_f16">;
-defm V_CMPX_LG_F16_t16    : VOPCX_Real_t16_gfx11<0x085, "v_cmpx_lg_f16">;
-defm V_CMPX_GE_F16_t16    : VOPCX_Real_t16_gfx11<0x086, "v_cmpx_ge_f16">;
-defm V_CMPX_O_F16_t16     : VOPCX_Real_t16_gfx11<0x087, "v_cmpx_o_f16">;
-defm V_CMPX_U_F16_t16     : VOPCX_Real_t16_gfx11<0x088, "v_cmpx_u_f16">;
-defm V_CMPX_NGE_F16_t16   : VOPCX_Real_t16_gfx11<0x089, "v_cmpx_nge_f16">;
-defm V_CMPX_NLG_F16_t16   : VOPCX_Real_t16_gfx11<0x08a, "v_cmpx_nlg_f16">;
-defm V_CMPX_NGT_F16_t16   : VOPCX_Real_t16_gfx11<0x08b, "v_cmpx_ngt_f16">;
-defm V_CMPX_NLE_F16_t16   : VOPCX_Real_t16_gfx11<0x08c, "v_cmpx_nle_f16">;
-defm V_CMPX_NEQ_F16_t16   : VOPCX_Real_t16_gfx11<0x08d, "v_cmpx_neq_f16">;
-defm V_CMPX_NLT_F16_t16   : VOPCX_Real_t16_gfx11<0x08e, "v_cmpx_nlt_f16">;
+defm V_CMPX_LT_F16_t16    : VOPCX_Real_t16_gfx11_gfx12<0x081, "v_cmpx_lt_f16">;
+defm V_CMPX_EQ_F16_t16    : VOPCX_Real_t16_gfx11_gfx12<0x082, "v_cmpx_eq_f16">;
+defm V_CMPX_LE_F16_t16    : VOPCX_Real_t16_gfx11_gfx12<0x083, "v_cmpx_le_f16">;
+defm V_CMPX_GT_F16_t16    : VOPCX_Real_t16_gfx11_gfx12<0x084, "v_cmpx_gt_f16">;
+defm V_CMPX_LG_F16_t16    : VOPCX_Real_t16_gfx11_gfx12<0x085, "v_cmpx_lg_f16">;
+defm V_CMPX_GE_F16_t16    : VOPCX_Real_t16_gfx11_gfx12<0x086, "v_cmpx_ge_f16">;
+defm V_CMPX_O_F16_t16     : VOPCX_Real_t16_gfx11_gfx12<0x087, "v_cmpx_o_f16">;
+defm V_CMPX_U_F16_t16     : VOPCX_Real_t16_gfx11_gfx12<0x088, "v_cmpx_u_f16">;
+defm V_CMPX_NGE_F16_t16   : VOPCX_Real_t16_gfx11_gfx12<0x089, "v_cmpx_nge_f16">;
+defm V_CMPX_NLG_F16_t16   : VOPCX_Real_t16_gfx11_gfx12<0x08a, "v_cmpx_nlg_f16">;
+defm V_CMPX_NGT_F16_t16   : VOPCX_Real_t16_gfx11_gfx12<0x08b, "v_cmpx_ngt_f16">;
+defm V_CMPX_NLE_F16_t16   : VOPCX_Real_t16_gfx11_gfx12<0x08c, "v_cmpx_nle_f16">;
+defm V_CMPX_NEQ_F16_t16   : VOPCX_Real_t16_gfx11_gfx12<0x08d, "v_cmpx_neq_f16">;
+defm V_CMPX_NLT_F16_t16   : VOPCX_Real_t16_gfx11_gfx12<0x08e, "v_cmpx_nlt_f16">;
 defm V_CMPX_T_F16_t16     : VOPCX_Real_with_name_gfx11<0x08f, "V_CMPX_TRU_F16_t16", "v_cmpx_t_f16", "v_cmpx_tru_f16">;
 defm V_CMPX_F_F32     : VOPCX_Real_gfx11<0x090>;
-defm V_CMPX_LT_F32    : VOPCX_Real_gfx11<0x091>;
-defm V_CMPX_EQ_F32    : VOPCX_Real_gfx11<0x092>;
-defm V_CMPX_LE_F32    : VOPCX_Real_gfx11<0x093>;
-defm V_CMPX_GT_F32    : VOPCX_Real_gfx11<0x094>;
-defm V_CMPX_LG_F32    : VOPCX_Real_gfx11<0x095>;
-defm V_CMPX_GE_F32    : VOPCX_Real_gfx11<0x096>;
-defm V_CMPX_O_F32     : VOPCX_Real_gfx11<0x097>;
-defm V_CMPX_U_F32     : VOPCX_Real_gfx11<0x098>;
-defm V_CMPX_NGE_F32   : VOPCX_Real_gfx11<0x099>;
-defm V_CMPX_NLG_F32   : VOPCX_Real_gfx11<0x09a>;
-defm V_CMPX_NGT_F32   : VOPCX_Real_gfx11<0x09b>;
-defm V_CMPX_NLE_F32   : VOPCX_Real_gfx11<0x09c>;
-defm V_CMPX_NEQ_F32   : VOPCX_Real_gfx11<0x09d>;
-defm V_CMPX_NLT_F32   : VOPCX_Real_gfx11<0x09e>;
+defm V_CMPX_LT_F32    : VOPCX_Real_gfx11_gfx12<0x091>;
+defm V_CMPX_EQ_F32    : VOPCX_Real_gfx11_gfx12<0x092>;
+defm V_CMPX_LE_F32    : VOPCX_Real_gfx11_gfx12<0x093>;
+defm V_CMPX_GT_F32    : VOPCX_Real_gfx11_gfx12<0x094>;
+defm V_CMPX_LG_F32    : VOPCX_Real_gfx11_gfx12<0x095>;
+defm V_CMPX_GE_F32    : VOPCX_Real_gfx11_gfx12<0x096>;
+defm V_CMPX_O_F32     : VOPCX_Real_gfx11_gfx12<0x097>;
+defm V_CMPX_U_F32     : VOPCX_Real_gfx11_gfx12<0x098>;
+defm V_CMPX_NGE_F32   : VOPCX_Real_gfx11_gfx12<0x099>;
+defm V_CMPX_NLG_F32   : VOPCX_Real_gfx11_gfx12<0x09a>;
+defm V_CMPX_NGT_F32   : VOPCX_Real_gfx11_gfx12<0x09b>;
+defm V_CMPX_NLE_F32   : VOPCX_Real_gfx11_gfx12<0x09c>;
+defm V_CMPX_NEQ_F32   : VOPCX_Real_gfx11_gfx12<0x09d>;
+defm V_CMPX_NLT_F32   : VOPCX_Real_gfx11_gfx12<0x09e>;
 defm V_CMPX_T_F32     : VOPCX_Real_with_name_gfx11<0x09f, "V_CMPX_TRU_F32", "v_cmpx_t_f32">;
 
 defm V_CMPX_F_F64     : VOPCX_Real_gfx11<0x0a0>;
-defm V_CMPX_LT_F64    : VOPCX_Real_gfx11<0x0a1>;
-defm V_CMPX_EQ_F64    : VOPCX_Real_gfx11<0x0a2>;
-defm V_CMPX_LE_F64    : VOPCX_Real_gfx11<0x0a3>;
-defm V_CMPX_GT_F64    : VOPCX_Real_gfx11<0x0a4>;
-defm V_CMPX_LG_F64    : VOPCX_Real_gfx11<0x0a5>;
-defm V_CMPX_GE_F64    : VOPCX_Real_gfx11<0x0a6>;
-defm V_CMPX_O_F64     : VOPCX_Real_gfx11<0x0a7>;
-defm V_CMPX_U_F64     : VOPCX_Real_gfx11<0x0a8>;
-defm V_CMPX_NGE_F64   : VOPCX_Real_gfx11<0x0a9>;
-defm V_CMPX_NLG_F64   : VOPCX_Real_gfx11<0x0aa>;
-defm V_CMPX_NGT_F64   : VOPCX_Real_gfx11<0x0ab>;
-defm V_CMPX_NLE_F64   : VOPCX_Real_gfx11<0x0ac>;
-defm V_CMPX_NEQ_F64   : VOPCX_Real_gfx11<0x0ad>;
-defm V_CMPX_NLT_F64   : VOPCX_Real_gfx11<0x0ae>;
+defm V_CMPX_LT_F64    : VOPCX_Real_gfx11_gfx12<0x0a1>;
+defm V_CMPX_EQ_F64    : VOPCX_Real_gfx11_gfx12<0x0a2>;
+defm V_CMPX_LE_F64    : VOPCX_Real_gfx11_gfx12<0x0a3>;
+defm V_CMPX_GT_F64    : VOPCX_Real_gfx11_gfx12<0x0a4>;
+defm V_CMPX_LG_F64    : VOPCX_Real_gfx11_gfx12<0x0a5>;
+defm V_CMPX_GE_F64    : VOPCX_Real_gfx11_gfx12<0x0a6>;
+defm V_CMPX_O_F64     : VOPCX_Real_gfx11_gfx12<0x0a7>;
+defm V_CMPX_U_F64     : VOPCX_Real_gfx11_gfx12<0x0a8>;
+defm V_CMPX_NGE_F64   : VOPCX_Real_gfx11_gfx12<0x0a9>;
+defm V_CMPX_NLG_F64   : VOPCX_Real_gfx11_gfx12<0x0aa>;
+defm V_CMPX_NGT_F64   : VOPCX_Real_gfx11_gfx12<0x0ab>;
+defm V_CMPX_NLE_F64   : VOPCX_Real_gfx11_gfx12<0x0ac>;
+defm V_CMPX_NEQ_F64   : VOPCX_Real_gfx11_gfx12<0x0ad>;
+defm V_CMPX_NLT_F64   : VOPCX_Real_gfx11_gfx12<0x0ae>;
 defm V_CMPX_T_F64     : VOPCX_Real_with_name_gfx11<0x0af, "V_CMPX_TRU_F64", "v_cmpx_t_f64">;
 
-defm V_CMPX_LT_I16_t16    : VOPCX_Real_t16_gfx11<0x0b1, "v_cmpx_lt_i16">;
-defm V_CMPX_EQ_I16_t16    : VOPCX_Real_t16_gfx11<0x0b2, "v_cmpx_eq_i16">;
-defm V_CMPX_LE_I16_t16    : VOPCX_Real_t16_gfx11<0x0b3, "v_cmpx_le_i16">;
-defm V_CMPX_GT_I16_t16    : VOPCX_Real_t16_gfx11<0x0b4, "v_cmpx_gt_i16">;
-defm V_CMPX_NE_I16_t16    : VOPCX_Real_t16_gfx11<0x0b5, "v_cmpx_ne_i16">;
-defm V_CMPX_GE_I16_t16    : VOPCX_Real_t16_gfx11<0x0b6, "v_cmpx_ge_i16">;
-defm V_CMPX_LT_U16_t16    : VOPCX_Real_t16_gfx11<0x0b9, "v_cmpx_lt_u16">;
-defm V_CMPX_EQ_U16_t16    : VOPCX_Real_t16_gfx11<0x0ba, "v_cmpx_eq_u16">;
-defm V_CMPX_LE_U16_t16    : VOPCX_Real_t16_gfx11<0x0bb, "v_cmpx_le_u16">;
-defm V_CMPX_GT_U16_t16    : VOPCX_Real_t16_gfx11<0x0bc, "v_cmpx_gt_u16">;
-defm V_CMPX_NE_U16_t16    : VOPCX_Real_t16_gfx11<0x0bd, "v_cmpx_ne_u16">;
-defm V_CMPX_GE_U16_t16    : VOPCX_Real_t16_gfx11<0x0be, "v_cmpx_ge_u16">;
+defm V_CMPX_LT_I16_t16    : VOPCX_Real_t16_gfx11_gfx12<0x0b1, "v_cmpx_lt_i16">;
+defm V_CMPX_EQ_I16_t16    : VOPCX_Real_t16_gfx11_gfx12<0x0b2, "v_cmpx_eq_i16">;
+defm V_CMPX_LE_I16_t16    : VOPCX_Real_t16_gfx11_gfx12<0x0b3, "v_cmpx_le_i16">;
+defm V_CMPX_GT_I16_t16    : VOPCX_Real_t16_gfx11_gfx12<0x0b4, "v_cmpx_gt_i16">;
+defm V_CMPX_NE_I16_t16    : VOPCX_Real_t16_gfx11_gfx12<0x0b5, "v_cmpx_ne_i16">;
+defm V_CMPX_GE_I16_t16    : VOPCX_Real_t16_gfx11_gfx12<0x0b6, "v_cmpx_ge_i16">;
+defm V_CMPX_LT_U16_t16    : VOPCX_Real_t16_gfx11_gfx12<0x0b9, "v_cmpx_lt_u16">;
+defm V_CMPX_EQ_U16_t16    : VOPCX_Real_t16_gfx11_gfx12<0x0ba, "v_cmpx_eq_u16">;
+defm V_CMPX_LE_U16_t16    : VOPCX_Real_t16_gfx11_gfx12<0x0bb, "v_cmpx_le_u16">;
+defm V_CMPX_GT_U16_t16    : VOPCX_Real_t16_gfx11_gfx12<0x0bc, "v_cmpx_gt_u16">;
+defm V_CMPX_NE_U16_t16    : VOPCX_Real_t16_gfx11_gfx12<0x0bd, "v_cmpx_ne_u16">;
+defm V_CMPX_GE_U16_t16    : VOPCX_Real_t16_gfx11_gfx12<0x0be, "v_cmpx_ge_u16">;
 defm V_CMPX_F_I32     : VOPCX_Real_gfx11<0x0c0>;
-defm V_CMPX_LT_I32    : VOPCX_Real_gfx11<0x0c1>;
-defm V_CMPX_EQ_I32    : VOPCX_Real_gfx11<0x0c2>;
-defm V_CMPX_LE_I32    : VOPCX_Real_gfx11<0x0c3>;
-defm V_CMPX_GT_I32    : VOPCX_Real_gfx11<0x0c4>;
-defm V_CMPX_NE_I32    : VOPCX_Real_gfx11<0x0c5>;
-defm V_CMPX_GE_I32    : VOPCX_Real_gfx11<0x0c6>;
+defm V_CMPX_LT_I32    : VOPCX_Real_gfx11_gfx12<0x0c1>;
+defm V_CMPX_EQ_I32    : VOPCX_Real_gfx11_gfx12<0x0c2>;
+defm V_CMPX_LE_I32    : VOPCX_Real_gfx11_gfx12<0x0c3>;
+defm V_CMPX_GT_I32    : VOPCX_Real_gfx11_gfx12<0x0c4>;
+defm V_CMPX_NE_I32    : VOPCX_Real_gfx11_gfx12<0x0c5>;
+defm V_CMPX_GE_I32    : VOPCX_Real_gfx11_gfx12<0x0c6>;
 defm V_CMPX_T_I32     : VOPCX_Real_gfx11<0x0c7>;
 defm V_CMPX_F_U32     : VOPCX_Real_gfx11<0x0c8>;
-defm V_CMPX_LT_U32    : VOPCX_Real_gfx11<0x0c9>;
-defm V_CMPX_EQ_U32    : VOPCX_Real_gfx11<0x0ca>;
-defm V_CMPX_LE_U32    : VOPCX_Real_gfx11<0x0cb>;
-defm V_CMPX_GT_U32    : VOPCX_Real_gfx11<0x0cc>;
-defm V_CMPX_NE_U32    : VOPCX_Real_gfx11<0x0cd>;
-defm V_CMPX_GE_U32    : VOPCX_Real_gfx11<0x0ce>;
+defm V_CMPX_LT_U32    : VOPCX_Real_gfx11_gfx12<0x0c9>;
+defm V_CMPX_EQ_U32    : VOPCX_Real_gfx11_gfx12<0x0ca>;
+defm V_CMPX_LE_U32    : VOPCX_Real_gfx11_gfx12<0x0cb>;
+defm V_CMPX_GT_U32    : VOPCX_Real_gfx11_gfx12<0x0cc>;
+defm V_CMPX_NE_U32    : VOPCX_Real_gfx11_gfx12<0x0cd>;
+defm V_CMPX_GE_U32    : VOPCX_Real_gfx11_gfx12<0x0ce>;
 defm V_CMPX_T_U32     : VOPCX_Real_gfx11<0x0cf>;
 
 defm V_CMPX_F_I64     : VOPCX_Real_gfx11<0x0d0>;
-defm V_CMPX_LT_I64    : VOPCX_Real_gfx11<0x0d1>;
-defm V_CMPX_EQ_I64    : VOPCX_Real_gfx11<0x0d2>;
-defm V_CMPX_LE_I64    : VOPCX_Real_gfx11<0x0d3>;
-defm V_CMPX_GT_I64    : VOPCX_Real_gfx11<0x0d4>;
-defm V_CMPX_NE_I64    : VOPCX_Real_gfx11<0x0d5>;
-defm V_CMPX_GE_I64    : VOPCX_Real_gfx11<0x0d6>;
+defm V_CMPX_LT_I64    : VOPCX_Real_gfx11_gfx12<0x0d1>;
+defm V_CMPX_EQ_I64    : VOPCX_Real_gfx11_gfx12<0x0d2>;
+defm V_CMPX_LE_I64    : VOPCX_Real_gfx11_gfx12<0x0d3>;
+defm V_CMPX_GT_I64    : VOPCX_Real_gfx11_gfx12<0x0d4>;
+defm V_CMPX_NE_I64    : VOPCX_Real_gfx11_gfx12<0x0d5>;
+defm V_CMPX_GE_I64    : VOPCX_Real_gfx11_gfx12<0x0d6>;
 defm V_CMPX_T_I64     : VOPCX_Real_gfx11<0x0d7>;
 defm V_CMPX_F_U64     : VOPCX_Real_gfx11<0x0d8>;
-defm V_CMPX_LT_U64    : VOPCX_Real_gfx11<0x0d9>;
-defm V_CMPX_EQ_U64    : VOPCX_Real_gfx11<0x0da>;
-defm V_CMPX_LE_U64    : VOPCX_Real_gfx11<0x0db>;
-defm V_CMPX_GT_U64    : VOPCX_Real_gfx11<0x0dc>;
-defm V_CMPX_NE_U64    : VOPCX_Real_gfx11<0x0dd>;
-defm V_CMPX_GE_U64    : VOPCX_Real_gfx11<0x0de>;
+defm V_CMPX_LT_U64    : VOPCX_Real_gfx11_gfx12<0x0d9>;
+defm V_CMPX_EQ_U64    : VOPCX_Real_gfx11_gfx12<0x0da>;
+defm V_CMPX_LE_U64    : VOPCX_Real_gfx11_gfx12<0x0db>;
+defm V_CMPX_GT_U64    : VOPCX_Real_gfx11_gfx12<0x0dc>;
+defm V_CMPX_NE_U64    : VOPCX_Real_gfx11_gfx12<0x0dd>;
+defm V_CMPX_GE_U64    : VOPCX_Real_gfx11_gfx12<0x0de>;
 defm V_CMPX_T_U64     : VOPCX_Real_gfx11<0x0df>;
-defm V_CMPX_CLASS_F16_t16 : VOPCX_Real_t16_gfx11<0x0fd, "v_cmpx_class_f16">;
-defm V_CMPX_CLASS_F32 : VOPCX_Real_gfx11<0x0fe>;
-defm V_CMPX_CLASS_F64 : VOPCX_Real_gfx11<0x0ff>;
+defm V_CMPX_CLASS_F16_t16 : VOPCX_Real_t16_gfx11_gfx12<0x0fd, "v_cmpx_class_f16">;
+defm V_CMPX_CLASS_F32     : VOPCX_Real_gfx11_gfx12<0x0fe>;
+defm V_CMPX_CLASS_F64     : VOPCX_Real_gfx11_gfx12<0x0ff>;
 
 //===----------------------------------------------------------------------===//
 // GFX10.
@@ -1976,10 +2016,13 @@ multiclass VOPCX_Real_gfx6_gfx7_gfx10 <bits<9> op> :
   VOPC_Real_gfx6_gfx7<op>, VOPCX_Real_gfx10<op>;
 
 multiclass VOPC_Real_gfx6_gfx7_gfx10_gfx11<bits<9> op> :
-  VOPC_Real_gfx6_gfx7_gfx10<op>, VOPC_Real_gfx11<op>;
+  VOPC_Real_gfx6_gfx7_gfx10<op>, VOPC_Real_Base<GFX11Gen, op>;
 
 multiclass VOPCX_Real_gfx6_gfx7_gfx10_gfx11<bits<9> op> :
-  VOPCX_Real_gfx6_gfx7_gfx10<op>, VOPCX_Real_gfx11<op>;
+  VOPCX_Real_gfx6_gfx7_gfx10<op>, VOPCX_Real<GFX11Gen, op>;
+
+multiclass VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<bits<9> op> :
+  VOPC_Real_gfx6_gfx7_gfx10_gfx11<op>, VOPC_Real_Base<GFX12Gen, op>;
 
 defm V_CMP_F_F32      : VOPC_Real_gfx6_gfx7_gfx10<0x000>;
 defm V_CMP_LT_F32     : VOPC_Real_gfx6_gfx7_gfx10<0x001>;
@@ -2014,20 +2057,20 @@ defm V_CMPX_NEQ_F32   : VOPCX_Real_gfx6_gfx7_gfx10<0x01d>;
 defm V_CMPX_NLT_F32   : VOPCX_Real_gfx6_gfx7_gfx10<0x01e>;
 defm V_CMPX_TRU_F32   : VOPCX_Real_gfx6_gfx7_gfx10<0x01f>;
 defm V_CMP_F_F64      : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x020>;
-defm V_CMP_LT_F64     : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x021>;
-defm V_CMP_EQ_F64     : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x022>;
-defm V_CMP_LE_F64     : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x023>;
-defm V_CMP_GT_F64     : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x024>;
-defm V_CMP_LG_F64     : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x025>;
-defm V_CMP_GE_F64     : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x026>;
-defm V_CMP_O_F64      : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x027>;
-defm V_CMP_U_F64      : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x028>;
-defm V_CMP_NGE_F64    : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x029>;
-defm V_CMP_NLG_F64    : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x02a>;
-defm V_CMP_NGT_F64    : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x02b>;
-defm V_CMP_NLE_F64    : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x02c>;
-defm V_CMP_NEQ_F64    : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x02d>;
-defm V_CMP_NLT_F64    : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x02e>;
+defm V_CMP_LT_F64     : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x021>;
+defm V_CMP_EQ_F64     : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x022>;
+defm V_CMP_LE_F64     : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x023>;
+defm V_CMP_GT_F64     : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x024>;
+defm V_CMP_LG_F64     : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x025>;
+defm V_CMP_GE_F64     : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x026>;
+defm V_CMP_O_F64      : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x027>;
+defm V_CMP_U_F64      : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x028>;
+defm V_CMP_NGE_F64    : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x029>;
+defm V_CMP_NLG_F64    : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x02a>;
+defm V_CMP_NGT_F64    : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x02b>;
+defm V_CMP_NLE_F64    : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x02c>;
+defm V_CMP_NEQ_F64    : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x02d>;
+defm V_CMP_NLT_F64    : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x02e>;
 defm V_CMP_TRU_F64    : VOPC_Real_gfx6_gfx7_gfx10<0x02f>;
 defm V_CMPX_F_F64     : VOPCX_Real_gfx6_gfx7_gfx10<0x030>;
 defm V_CMPX_LT_F64    : VOPCX_Real_gfx6_gfx7_gfx10<0x031>;
diff --git a/llvm/lib/Target/AMDGPU/VOPDInstructions.td b/llvm/lib/Target/AMDGPU/VOPDInstructions.td
index c6dc4dd765e5..c6af3d67c560 100644
--- a/llvm/lib/Target/AMDGPU/VOPDInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPDInstructions.td
@@ -54,23 +54,34 @@ class VOPD_MADKe<bits<4> opX, bits<5> opY> : Enc96 {
 // VOPD classes
 //===----------------------------------------------------------------------===//
 
+
+class GFXGenD<GFXGen Gen, list<string> DXPseudos, list<string> DYPseudos,
+              Predicate subtargetPred = Gen.AssemblerPredicate> :
+    GFXGen<Gen.AssemblerPredicate, Gen.DecoderNamespace, Gen.Suffix,
+           Gen.Subtarget> {
+  list<string> VOPDXPseudos = DXPseudos;
+  list<string> VOPDYPseudos = DYPseudos;
+  Predicate SubtargetPredicate = subtargetPred;
+}
+
 class VOPD_Base<dag outs, dag ins, string asm, VOP_Pseudo VDX, VOP_Pseudo VDY,
-                VOPD_Component XasVC, VOPD_Component YasVC>
+                VOPD_Component XasVC, VOPD_Component YasVC, GFXGenD Gen>
     : VOPAnyCommon<outs, ins, asm, []>,
       VOP<NAME>,
-      SIMCInstr<NAME, SIEncodingFamily.GFX11> {
+      SIMCInstr<NAME, Gen.Subtarget> {
   // Fields for table indexing
   Instruction Opcode = !cast<Instruction>(NAME);
   bits<5> OpX = XasVC.VOPDOp;
   bits<5> OpY = YasVC.VOPDOp;
+  bits<4> SubTgt = Gen.Subtarget;
 
   let VALU = 1;
 
-  let DecoderNamespace = "GFX11";
-  let AssemblerPredicate = isGFX11Plus;
+  let DecoderNamespace = Gen.DecoderNamespace;
+  let AssemblerPredicate = Gen.AssemblerPredicate;
   let WaveSizePredicate = isWave32;
   let isCodeGenOnly = 0;
-  let SubtargetPredicate = isGFX11Plus;
+  let SubtargetPredicate = Gen.SubtargetPredicate;
   let AsmMatchConverter  = "cvtVOPD";
   let Size = 8;
   let ReadsModeReg = !or(VDX.ReadsModeReg, VDY.ReadsModeReg);
@@ -97,16 +108,16 @@ class VOPD_Base<dag outs, dag ins, string asm, VOP_Pseudo VDX, VOP_Pseudo VDY,
 }
 
 class VOPD<dag outs, dag ins, string asm, VOP_Pseudo VDX, VOP_Pseudo VDY,
-           VOPD_Component XasVC, VOPD_Component YasVC>
-    : VOPD_Base<outs, ins, asm, VDX, VDY, XasVC, YasVC>,
+           VOPD_Component XasVC, VOPD_Component YasVC, GFXGenD Gen>
+    : VOPD_Base<outs, ins, asm, VDX, VDY, XasVC, YasVC, Gen>,
       VOPDe<XasVC.VOPDOp{3-0}, YasVC.VOPDOp> {
   let Inst{16-9} = !if (!eq(VDX.Mnemonic, "v_mov_b32"), 0x0, vsrc1X);
   let Inst{48-41} = !if (!eq(VDY.Mnemonic, "v_mov_b32"), 0x0, vsrc1Y);
 }
 
 class VOPD_MADK<dag outs, dag ins, string asm, VOP_Pseudo VDX, VOP_Pseudo VDY,
-                VOPD_Component XasVC, VOPD_Component YasVC>
-    : VOPD_Base<outs, ins, asm, VDX, VDY, XasVC, YasVC>,
+                VOPD_Component XasVC, VOPD_Component YasVC, GFXGenD Gen>
+    : VOPD_Base<outs, ins, asm, VDX, VDY, XasVC, YasVC, Gen>,
       VOPD_MADKe<XasVC.VOPDOp{3-0}, YasVC.VOPDOp> {
   let Inst{16-9} = !if (!eq(VDX.Mnemonic, "v_mov_b32"), 0x0, vsrc1X);
   let Inst{48-41} = !if (!eq(VDY.Mnemonic, "v_mov_b32"), 0x0, vsrc1Y);
@@ -115,60 +126,85 @@ class VOPD_MADK<dag outs, dag ins, string asm, VOP_Pseudo VDX, VOP_Pseudo VDY,
 }
 
 // V_DUAL_DOT2ACC_F32_BF16 is a legal instruction, but V_DOT2ACC_F32_BF16 is
-// not. Since we generate the DUAL form by converting from the normal form we
-// will never generate it.
-defvar VOPDYPseudos = [
+// not. V_DUAL_DOT2C_F32_BF16 is a legal instruction on GFX12, but
+// V_DOT2C_F32_F16_e32 is not. Since we generate the DUAL form by converting
+// from the normal form we will never generate them.
+defvar VOPDPseudosCommon = [
   "V_FMAC_F32_e32", "V_FMAAK_F32", "V_FMAMK_F32", "V_MUL_F32_e32",
   "V_ADD_F32_e32", "V_SUB_F32_e32", "V_SUBREV_F32_e32", "V_MUL_LEGACY_F32_e32",
-  "V_MOV_B32_e32", "V_CNDMASK_B32_e32", "V_MAX_F32_e32", "V_MIN_F32_e32",
-  "V_DOT2C_F32_F16_e32", "V_ADD_U32_e32", "V_LSHLREV_B32_e32", "V_AND_B32_e32"
+  "V_MOV_B32_e32", "V_CNDMASK_B32_e32", "V_MAX_F32_e32", "V_MIN_F32_e32"
 ];
-defvar VOPDXPseudos = VOPDYPseudos[0...VOPDX_Max_Index];
+defvar VOPDPseudosGFX11 = ["V_DOT2C_F32_F16_e32"];
+defvar VOPDYOnlyPseudosCommon = ["V_ADD_U32_e32", "V_LSHLREV_B32_e32",
+                                 "V_AND_B32_e32"];
+
+defvar VOPDXPseudosGFX11 = !listconcat(VOPDPseudosCommon, VOPDPseudosGFX11);
+defvar VOPDXPseudosGFX12 = VOPDPseudosCommon;
+defvar VOPDYPseudosGFX11 = !listconcat(VOPDXPseudosGFX11, VOPDYOnlyPseudosCommon);
+defvar VOPDYPseudosGFX12 = !listconcat(VOPDXPseudosGFX12, VOPDYOnlyPseudosCommon);
+
+def GFX11GenD : GFXGenD<GFX11Gen, VOPDXPseudosGFX11, VOPDYPseudosGFX11>;
+def GFX12GenD : GFXGenD<GFX12Gen, VOPDXPseudosGFX12, VOPDYPseudosGFX12>;
+
 
 def VOPDDstYOperand : RegisterOperand<VGPR_32, "printRegularOperand"> {
   let DecoderMethod = "decodeOperandVOPDDstY";
 }
 
-foreach x = VOPDXPseudos in {
-  foreach y = VOPDYPseudos in {
-    defvar xInst = !cast<VOP_Pseudo>(x);
-    defvar yInst = !cast<VOP_Pseudo>(y);
-    defvar XasVC = !cast<VOPD_Component>(x);
-    defvar YasVC = !cast<VOPD_Component>(y);
-    defvar isMADK = !or(!eq(x, "V_FMAAK_F32"), !eq(x, "V_FMAMK_F32"),
-                        !eq(y, "V_FMAAK_F32"), !eq(y, "V_FMAMK_F32"));
-    // If X or Y is MADK (have a mandatory immediate), all src operands which
-    // may contain an optional literal must use the VSrc_*_Deferred operand
-    // type. Optional literal operands in MADK VOPD components always use this
-    // operand form. If Both X and Y are MADK, the mandatory literal of X
-    // additionally must use an alternate operand format which defers to the
-    // 'real' Y literal
-    defvar isOpXMADK = !or(!eq(x, "V_FMAAK_F32"), !eq(x, "V_FMAMK_F32"));
-    defvar isOpYMADK = !or(!eq(y, "V_FMAAK_F32"), !eq(y, "V_FMAMK_F32"));
-    defvar OpName = "V_DUAL_" # !substr(x,2) # "_X_" # !substr(y,2);
-    defvar outs = (outs VGPRSrc_32:$vdstX, VOPDDstYOperand:$vdstY);
-    if !or(isOpXMADK, isOpYMADK) then {
-      if !and(isOpXMADK, isOpYMADK) then {
-        defvar X_MADK_Pfl = !cast<VOP_MADK_Base>(xInst.Pfl);
-        defvar ins = !con(xInst.Pfl.InsVOPDXDeferred, yInst.Pfl.InsVOPDY);
-        defvar asm = XasVC.VOPDName #" "# X_MADK_Pfl.AsmVOPDXDeferred #" :: "# YasVC.VOPDName #" "# yInst.Pfl.AsmVOPDY;
-        def OpName : VOPD_MADK<outs, ins, asm, xInst, yInst, XasVC, YasVC>;
-      } else {
-        defvar asm = XasVC.VOPDName #" "# xInst.Pfl.AsmVOPDX #" :: "# YasVC.VOPDName #" "# yInst.Pfl.AsmVOPDY;
-        if isOpXMADK then {
-          assert !not(isOpYMADK), "Expected only OpX as MADK";
-          defvar ins = !con(xInst.Pfl.InsVOPDX, yInst.Pfl.InsVOPDYDeferred);
-          def OpName : VOPD_MADK<outs, ins, asm, xInst, yInst, XasVC, YasVC>;
-        } else {
-          assert !not(isOpXMADK), "Expected only OpY as MADK";
+class getRenamed<string VOPDName, GFXGen Gen> {
+  string ret = !if(!eq(Gen.Subtarget, GFX12Gen.Subtarget),
+                   !if(!eq(VOPDName, "v_dual_max_f32"),
+                       "v_dual_max_num_f32",
+                       !if(!eq(VOPDName, "v_dual_min_f32"),
+                           "v_dual_min_num_f32",
+                           VOPDName)),
+                   VOPDName);
+}
+
+foreach Gen = [GFX11GenD, GFX12GenD] in {
+  foreach x = Gen.VOPDXPseudos in {
+    foreach y = Gen.VOPDYPseudos in {
+      defvar xInst = !cast<VOP_Pseudo>(x);
+      defvar yInst = !cast<VOP_Pseudo>(y);
+      defvar XasVC = !cast<VOPD_Component>(x);
+      defvar YasVC = !cast<VOPD_Component>(y);
+      defvar xAsmName = getRenamed<XasVC.VOPDName, Gen>.ret;
+      defvar yAsmName = getRenamed<YasVC.VOPDName, Gen>.ret;
+      defvar isMADK = !or(!eq(x, "V_FMAAK_F32"), !eq(x, "V_FMAMK_F32"),
+                          !eq(y, "V_FMAAK_F32"), !eq(y, "V_FMAMK_F32"));
+      // If X or Y is MADK (have a mandatory immediate), all src operands which
+      // may contain an optional literal must use the VSrc_*_Deferred operand
+      // type. Optional literal operands in MADK VOPD components always use this
+      // operand form. If Both X and Y are MADK, the mandatory literal of X
+      // additionally must use an alternate operand format which defers to the
+      // 'real' Y literal
+      defvar isOpXMADK = !or(!eq(x, "V_FMAAK_F32"), !eq(x, "V_FMAMK_F32"));
+      defvar isOpYMADK = !or(!eq(y, "V_FMAAK_F32"), !eq(y, "V_FMAMK_F32"));
+      defvar OpName = "V_DUAL_" # !substr(x,2) # "_X_" # !substr(y,2) # Gen.Suffix;
+      defvar outs = (outs VGPRSrc_32:$vdstX, VOPDDstYOperand:$vdstY);
+      if !or(isOpXMADK, isOpYMADK) then {
+        if !and(isOpXMADK, isOpYMADK) then {
+          defvar X_MADK_Pfl = !cast<VOP_MADK_Base>(xInst.Pfl);
           defvar ins = !con(xInst.Pfl.InsVOPDXDeferred, yInst.Pfl.InsVOPDY);
-          def OpName : VOPD_MADK<outs, ins, asm, xInst, yInst, XasVC, YasVC>;
+          defvar asm = xAsmName #" "# X_MADK_Pfl.AsmVOPDXDeferred #" :: "# yAsmName #" "# yInst.Pfl.AsmVOPDY;
+          def OpName : VOPD_MADK<outs, ins, asm, xInst, yInst, XasVC, YasVC, Gen>;
+        } else {
+          defvar asm = xAsmName #" "# xInst.Pfl.AsmVOPDX #" :: "# yAsmName #" "# yInst.Pfl.AsmVOPDY;
+          if isOpXMADK then {
+            assert !not(isOpYMADK), "Expected only OpX as MADK";
+            defvar ins = !con(xInst.Pfl.InsVOPDX, yInst.Pfl.InsVOPDYDeferred);
+            def OpName : VOPD_MADK<outs, ins, asm, xInst, yInst, XasVC, YasVC, Gen>;
+          } else {
+            assert !not(isOpXMADK), "Expected only OpY as MADK";
+            defvar ins = !con(xInst.Pfl.InsVOPDXDeferred, yInst.Pfl.InsVOPDY);
+            def OpName : VOPD_MADK<outs, ins, asm, xInst, yInst, XasVC, YasVC, Gen>;
+          }
         }
+      } else {
+        defvar ins = !con(xInst.Pfl.InsVOPDX, yInst.Pfl.InsVOPDY);
+        defvar asm = xAsmName #" "# xInst.Pfl.AsmVOPDX #" :: "# yAsmName #" "# yInst.Pfl.AsmVOPDY;
+        def OpName : VOPD<outs, ins, asm, xInst, yInst, XasVC, YasVC, Gen>;
       }
-    } else {
-      defvar ins = !con(xInst.Pfl.InsVOPDX, yInst.Pfl.InsVOPDY);
-      defvar asm = XasVC.VOPDName #" "# xInst.Pfl.AsmVOPDX #" :: "# YasVC.VOPDName #" "# yInst.Pfl.AsmVOPDY;
-      def OpName : VOPD<outs, ins, asm, xInst, yInst, XasVC, YasVC>;
     }
   }
 }
diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td
index 395bb01f867c..96184486e06f 100644
--- a/llvm/lib/Target/AMDGPU/VOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td
@@ -29,6 +29,22 @@ class LetDummies {
   string DecoderNamespace;
 }
 
+//===----------------------------------------------------------------------===//
+// VOP Subtarget info
+//===----------------------------------------------------------------------===//
+
+class GFXGen<Predicate pred, string dn, string suffix, int sub> {
+  Predicate AssemblerPredicate = pred;
+  string DecoderNamespace = dn;
+  string Suffix = suffix;
+  int Subtarget = sub;
+}
+
+def GFX12Gen : GFXGen<isGFX12Only, "GFX12", "_gfx12", SIEncodingFamily.GFX12>;
+def GFX11Gen : GFXGen<isGFX11Only, "GFX11", "_gfx11", SIEncodingFamily.GFX11>;
+
+//===----------------------------------------------------------------------===//
+
 class VOP <string opName> {
   string OpName = opName;
 }
@@ -190,6 +206,14 @@ class VOP3_Real <VOP_Pseudo ps, int EncodingFamily, string asm_name = ps.Mnemoni
   VOPProfile Pfl = ps.Pfl;
 }
 
+class VOP3_Real_Gen <VOP_Pseudo ps, GFXGen Gen, string asm_name = ps.Mnemonic> :
+  VOP3_Real <ps, Gen.Subtarget, asm_name> {
+  let AssemblerPredicate = !if(ps.Pfl.IsRealTrue16, UseRealTrue16Insts,
+                               Gen.AssemblerPredicate);
+  let DecoderNamespace = Gen.DecoderNamespace#
+                         !if(ps.Pfl.IsRealTrue16, "", "_FAKE16");
+}
+
 // XXX - Is there any reason to distinguish this from regular VOP3
 // here?
 class VOP3P_Real<VOP_Pseudo ps, int EncodingFamily, string asm_name = ps.Mnemonic> :
@@ -199,6 +223,12 @@ class VOP3P_Real<VOP_Pseudo ps, int EncodingFamily, string asm_name = ps.Mnemoni
   let Constraints        = !if(!eq(!substr(ps.Mnemonic,0,6), "v_wmma"), "", ps.Constraints);
 }
 
+class VOP3P_Real_Gen<VOP_Pseudo ps, GFXGen Gen, string asm_name = ps.Mnemonic> :
+  VOP3P_Real<ps, Gen.Subtarget, asm_name> {
+  let AssemblerPredicate = Gen.AssemblerPredicate;
+  let DecoderNamespace = Gen.DecoderNamespace;
+}
+
 class VOP3a<VOPProfile P> : Enc64 {
   bits<4> src0_modifiers;
   bits<9> src0;
@@ -234,7 +264,7 @@ class VOP3a_gfx10<bits<10> op, VOPProfile p> : VOP3a<p> {
   let Inst{31-26} = 0x35;
 }
 
-class VOP3a_gfx11<bits<10> op, VOPProfile p> : VOP3a_gfx10<op, p>;
+class VOP3a_gfx11_gfx12<bits<10> op, VOPProfile p> : VOP3a_gfx10<op, p>;
 
 class VOP3a_vi <bits<10> op, VOPProfile P> : VOP3a<P> {
   let Inst{25-16} = op;
@@ -251,7 +281,7 @@ class VOP3e_gfx10<bits<10> op, VOPProfile p> : VOP3a_gfx10<op, p> {
   let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0);
 }
 
-class VOP3e_gfx11<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p>;
+class VOP3e_gfx11_gfx12<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p>;
 
 class VOP3e_vi <bits<10> op, VOPProfile P> : VOP3a_vi <op, P> {
   bits<8> vdst;
@@ -272,9 +302,9 @@ class VOP3OpSel_gfx10<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> {
   let Inst{14} = !if(p.HasDst,  src0_modifiers{3}, 0);
 }
 
-class VOP3OpSel_gfx11<bits<10> op, VOPProfile p> : VOP3OpSel_gfx10<op, p>;
+class VOP3OpSel_gfx11_gfx12<bits<10> op, VOPProfile p> : VOP3OpSel_gfx10<op, p>;
 
-class VOP3DotOpSel_gfx11<bits<10> op, VOPProfile p> : VOP3OpSel_gfx11<op, p>{
+class VOP3DotOpSel_gfx11_gfx12<bits<10> op, VOPProfile p> : VOP3OpSel_gfx11_gfx12<op, p>{
   let Inst{11} = ?;
   let Inst{12} = ?;
 }
@@ -435,7 +465,7 @@ class VOP3Pe_gfx10 <bits<7> op, VOPProfile P> : VOP3Pe<op, P> {
   let Inst{31-23} = 0x198; //encoding
 }
 
-class VOP3Pe_gfx11<bits<7> op, VOPProfile P> : VOP3Pe_gfx10<op, P>;
+class VOP3Pe_gfx11_gfx12<bits<7> op, VOPProfile P> : VOP3Pe_gfx10<op, P>;
 
 class VOP3be_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3be<p> {
   let Inst{25-17} = op;
@@ -448,7 +478,7 @@ class VOP3be_gfx10<bits<10> op, VOPProfile p> : VOP3be<p> {
   let Inst{31-26} = 0x35;
 }
 
-class VOP3be_gfx11<bits<10> op, VOPProfile p> : VOP3be_gfx10<op, p>;
+class VOP3be_gfx11_gfx12<bits<10> op, VOPProfile p> : VOP3be_gfx10<op, p>;
 
 class VOP3be_vi <bits<10> op, VOPProfile P> : VOP3be<P> {
   bits<1> clamp;
@@ -1294,6 +1324,15 @@ class VOP3_DPP16<bits<10> op, VOP_DPP_Pseudo ps, int subtarget,
                  string opName = ps.OpName>
     : Base_VOP3_DPP16<op, ps, opName>, SIMCInstr<ps.PseudoInstr, subtarget>;
 
+class VOP3_DPP16_Gen<bits<10> op, VOP_DPP_Pseudo ps, GFXGen Gen,
+                     string opName = ps.OpName> :
+  VOP3_DPP16 <op, ps, Gen.Subtarget, opName> {
+  let AssemblerPredicate = !if(ps.Pfl.IsRealTrue16, UseRealTrue16Insts,
+                               Gen.AssemblerPredicate);
+  let DecoderNamespace = "DPP"#Gen.DecoderNamespace#
+                         !if(ps.Pfl.IsRealTrue16, "", "_FAKE16");
+}
+
 class Base_VOP3_DPP8<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName>
     : VOP3_DPP8<op, opName, ps.Pfl> {
   let VOP3_OPSEL = ps.Pfl.HasOpSel;
@@ -1320,170 +1359,240 @@ class VOP3b_DPP8_Base<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName>
 }
 
 //===----------------------------------------------------------------------===//
-// VOP3 GFX11
+// VOP3 GFX11, GFX12
 //===----------------------------------------------------------------------===//
 
-let AssemblerPredicate = isGFX11Only,
-    DecoderNamespace = "GFX11" in {
-  multiclass VOP3_Real_Base_gfx11<bits<10> op, string opName = NAME,
-                                  bit isSingle = 0> {
-    defvar ps = !cast<VOP_Pseudo>(opName#"_e64");
-    let IsSingle = !or(isSingle, ps.Pfl.IsSingle) in {
-    if ps.Pfl.HasOpSel then
-      def _e64_gfx11 :
-        VOP3_Real<ps, SIEncodingFamily.GFX11>,
-        VOP3OpSel_gfx11<op, ps.Pfl>;
-    if !not(ps.Pfl.HasOpSel) then
-      def _e64_gfx11 :
-        VOP3_Real<ps, SIEncodingFamily.GFX11>,
-        VOP3e_gfx11<op, ps.Pfl>;
-    }
-  }
-  multiclass VOP3Dot_Real_Base_gfx11<bits<10> op, string opName = NAME,
-                                     bit isSingle = 0> {
-    defvar ps = !cast<VOP_Pseudo>(opName#"_e64");
-    let IsSingle = !or(isSingle, ps.Pfl.IsSingle) in {
-      def _e64_gfx11 :
-        VOP3_Real<ps, SIEncodingFamily.GFX11>,
-        VOP3DotOpSel_gfx11<op, ps.Pfl>;
-    }
-  }
-  multiclass VOP3_Real_with_name_gfx11<bits<10> op, string opName,
-                                       string asmName, bit isSingle = 0> {
-    defvar ps = !cast<VOP_Pseudo>(opName#"_e64");
-    let AsmString = asmName # ps.AsmOperands,
-        IsSingle = !or(isSingle, ps.Pfl.IsSingle) in {
-    if ps.Pfl.HasOpSel then
-      def _e64_gfx11 :
-        VOP3_Real<ps, SIEncodingFamily.GFX11>,
-        VOP3OpSel_gfx11<op, ps.Pfl>;
-    if !not(ps.Pfl.HasOpSel) then
-      let DecoderNamespace = !if(ps.Pfl.IsRealTrue16, "GFX11", "GFX11_FAKE16"),
-          AssemblerPredicate = !if(ps.Pfl.IsRealTrue16, UseRealTrue16Insts, isGFX11Only) in
-      def _e64_gfx11 :
-        VOP3_Real<ps, SIEncodingFamily.GFX11>,
-        VOP3e_gfx11<op, ps.Pfl>;
-    }
-    def _gfx11_VOP3_alias : MnemonicAlias<ps.Mnemonic, asmName>, Requires<[isGFX11Plus]>, LetDummies;
-  }
-  // for READLANE/WRITELANE
-  multiclass VOP3_Real_No_Suffix_gfx11<bits<10> op, string opName = NAME> {
-    defvar ps = !cast<VOP_Pseudo>(opName);
-      def _e64_gfx11 :
-        VOP3_Real<ps, SIEncodingFamily.GFX11>,
-        VOP3e_gfx11<op, ps.Pfl>;
-  }
-  multiclass VOP3_Real_dpp_Base_gfx11<bits<10> op, string opName = NAME> {
-    def _e64_dpp_gfx11 : VOP3_DPP16<op, !cast<VOP_DPP_Pseudo>(opName#"_e64"#"_dpp"), SIEncodingFamily.GFX11> {
-      let DecoderNamespace = "DPPGFX11";
-      }
+multiclass VOP3_Real_Base<GFXGen Gen, bits<10> op, string opName = NAME,
+                          bit isSingle = 0> {
+  defvar ps = !cast<VOP_Pseudo>(opName#"_e64");
+  let IsSingle = !or(isSingle, ps.Pfl.IsSingle) in {
+  if ps.Pfl.HasOpSel then
+    def _e64#Gen.Suffix :
+      VOP3_Real_Gen<ps, Gen>,
+      VOP3OpSel_gfx11_gfx12<op, ps.Pfl>;
+  if !not(ps.Pfl.HasOpSel) then
+    def _e64#Gen.Suffix :
+      VOP3_Real_Gen<ps, Gen>,
+      VOP3e_gfx11_gfx12<op, ps.Pfl>;
   }
+}
 
-  multiclass VOP3Dot_Real_dpp_Base_gfx11<bits<10> op, string opName = NAME> {
-    def _e64_dpp_gfx11 : VOP3_DPP16<op, !cast<VOP_DPP_Pseudo>(opName#"_e64"#"_dpp"), SIEncodingFamily.GFX11> {
-      let Inst{11} = ?;
-      let Inst{12} = ?;
-      let DecoderNamespace = "DPPGFX11";
-      }
+multiclass VOP3Dot_Real_Base<GFXGen Gen, bits<10> op, string opName = NAME,
+                             bit isSingle = 0> {
+  defvar ps = !cast<VOP_Pseudo>(opName#"_e64");
+  let IsSingle = !or(isSingle, ps.Pfl.IsSingle) in {
+    def _e64#Gen.Suffix :
+      VOP3_Real_Gen<ps, Gen>,
+      VOP3DotOpSel_gfx11_gfx12<op, ps.Pfl>;
   }
+}
 
-  multiclass VOP3_Real_dpp_with_name_gfx11<bits<10> op, string opName,
-                                           string asmName> {
-    defvar ps = !cast<VOP3_Pseudo>(opName#"_e64");
-    let AsmString = asmName # ps.Pfl.AsmVOP3DPP16,
-        DecoderNamespace = !if(ps.Pfl.IsRealTrue16, "DPPGFX11", "DPPGFX11_FAKE16"),
-        AssemblerPredicate = !if(ps.Pfl.IsRealTrue16, UseRealTrue16Insts, isGFX11Only) in {
-      defm NAME : VOP3_Real_dpp_Base_gfx11<op, opName>;
-    }
-  }
-  multiclass VOP3_Real_dpp8_Base_gfx11<bits<10> op, string opName = NAME> {
-    defvar ps = !cast<VOP3_Pseudo>(opName#"_e64");
-    def _e64_dpp8_gfx11 : Base_VOP3_DPP8<op, ps> {
-      let DecoderNamespace = "DPP8GFX11";
-    }
+multiclass VOP3_Real_with_name<GFXGen Gen, bits<10> op, string opName,
+                               string asmName, bit isSingle = 0> {
+  defvar ps = !cast<VOP_Pseudo>(opName#"_e64");
+  let AsmString = asmName # ps.AsmOperands,
+      IsSingle = !or(isSingle, ps.Pfl.IsSingle) in {
+  if ps.Pfl.HasOpSel then
+    def _e64#Gen.Suffix :
+      VOP3_Real_Gen<ps, Gen>,
+      VOP3OpSel_gfx11_gfx12<op, ps.Pfl>;
+  if !not(ps.Pfl.HasOpSel) then
+    def _e64#Gen.Suffix :
+      VOP3_Real_Gen<ps, Gen>,
+      VOP3e_gfx11_gfx12<op, ps.Pfl>;
   }
+  def Gen.Suffix#"_VOP3_alias" : MnemonicAlias<ps.Mnemonic, asmName>, Requires<[Gen.AssemblerPredicate]>, LetDummies;
+}
+
+// for READLANE/WRITELANE
+multiclass VOP3_Real_No_Suffix<GFXGen Gen, bits<10> op, string opName = NAME> {
+  defvar ps = !cast<VOP_Pseudo>(opName);
+    def _e64#Gen.Suffix :
+      VOP3_Real_Gen<ps, Gen>,
+      VOP3e_gfx11_gfx12<op, ps.Pfl>;
+}
+
+multiclass VOP3_Real_dpp_Base<GFXGen Gen, bits<10> op, string opName = NAME> {
+  def _e64_dpp#Gen.Suffix :
+    VOP3_DPP16_Gen<op, !cast<VOP_DPP_Pseudo>(opName#"_e64"#"_dpp"), Gen>;
+}
 
-  multiclass VOP3Dot_Real_dpp8_Base_gfx11<bits<10> op, string opName = NAME> {
-    defvar ps = !cast<VOP3_Pseudo>(opName#"_e64");
-    def _e64_dpp8_gfx11 : Base_VOP3_DPP8<op, ps> {
+multiclass VOP3Dot_Real_dpp_Base<GFXGen Gen, bits<10> op, string opName = NAME> {
+  def _e64_dpp#Gen.Suffix :
+    VOP3_DPP16_Gen<op, !cast<VOP_DPP_Pseudo>(opName#"_e64"#"_dpp"), Gen> {
       let Inst{11} = ?;
       let Inst{12} = ?;
-      let DecoderNamespace = "DPP8GFX11";
     }
+}
+
+multiclass VOP3_Real_dpp_with_name<GFXGen Gen, bits<10> op, string opName,
+                                   string asmName> {
+  defvar ps = !cast<VOP3_Pseudo>(opName#"_e64");
+  let AsmString = asmName # ps.Pfl.AsmVOP3DPP16 in {
+    defm NAME : VOP3_Real_dpp_Base<Gen, op, opName>;
   }
+}
 
-  multiclass VOP3_Real_dpp8_with_name_gfx11<bits<10> op, string opName,
-                                           string asmName> {
-    defvar ps = !cast<VOP3_Pseudo>(opName#"_e64");
-    let AsmString = asmName # ps.Pfl.AsmVOP3DPP8,
-        DecoderNamespace = !if(ps.Pfl.IsRealTrue16, "DPP8GFX11", "DPP8GFX11_FAKE16"),
-        AssemblerPredicate = !if(ps.Pfl.IsRealTrue16, UseRealTrue16Insts, isGFX11Only) in {
-      defm NAME : VOP3_Real_dpp8_Base_gfx11<op, opName>;
-    }
+multiclass VOP3_Real_dpp8_Base<GFXGen Gen, bits<10> op, string opName = NAME> {
+  defvar ps = !cast<VOP3_Pseudo>(opName#"_e64");
+  def _e64_dpp8#Gen.Suffix : Base_VOP3_DPP8<op, ps> {
+    let DecoderNamespace = "DPP8"#Gen.DecoderNamespace;
+    let AssemblerPredicate = Gen.AssemblerPredicate;
   }
-  multiclass VOP3be_Real_gfx11<bits<10> op, string opName, string asmName,
-                               bit isSingle = 0> {
-    defvar ps = !cast<VOP3_Pseudo>(opName#"_e64");
-    let IsSingle = !or(isSingle, ps.Pfl.IsSingle) in
-      def _e64_gfx11 :
-        VOP3_Real<ps, SIEncodingFamily.GFX11, asmName>,
-        VOP3be_gfx11<op, ps.Pfl> ;
+}
+
+multiclass VOP3Dot_Real_dpp8_Base<GFXGen Gen, bits<10> op, string opName = NAME> {
+  defvar ps = !cast<VOP3_Pseudo>(opName#"_e64");
+  def _e64_dpp8#Gen.Suffix : Base_VOP3_DPP8<op, ps> {
+    let Inst{11} = ?;
+    let Inst{12} = ?;
+    let DecoderNamespace = "DPP8"#Gen.DecoderNamespace;
+    let AssemblerPredicate = Gen.AssemblerPredicate;
   }
-  multiclass VOP3be_Real_dpp_gfx11<bits<10> op, string opName, string asmName> {
-    defvar ps = !cast<VOP3_Pseudo>(opName #"_e64");
-    defvar dpp_ps = !cast<VOP_DPP_Pseudo>(opName #"_e64" #"_dpp");
-    def _e64_dpp_gfx11 : Base_VOP3b_DPP16<op, dpp_ps, asmName>,
-                         SIMCInstr<dpp_ps.PseudoInstr, SIEncodingFamily.GFX11> {
-      let DecoderNamespace = "DPPGFX11";
-    }
+}
+
+multiclass VOP3_Real_dpp8_with_name<GFXGen Gen, bits<10> op, string opName,
+                                    string asmName> {
+  defvar ps = !cast<VOP3_Pseudo>(opName#"_e64");
+  let AsmString = asmName # ps.Pfl.AsmVOP3DPP8,
+      DecoderNamespace = "DPP8"#Gen.DecoderNamespace#
+                         !if(ps.Pfl.IsRealTrue16, "", "_FAKE16"),
+      AssemblerPredicate = !if(ps.Pfl.IsRealTrue16, UseRealTrue16Insts,
+                               Gen.AssemblerPredicate) in {
+
+    defm NAME : VOP3_Real_dpp8_Base<Gen, op, opName>;
   }
-  multiclass VOP3be_Real_dpp8_gfx11<bits<10> op, string opName, string asmName> {
-    defvar ps = !cast<VOP3_Pseudo>(opName #"_e64");
-    def _e64_dpp8_gfx11 : VOP3b_DPP8_Base<op, ps, asmName> {
-      let DecoderNamespace = "DPP8GFX11";
-    }
+}
+
+multiclass VOP3be_Real<GFXGen Gen, bits<10> op, string opName, string asmName,
+                      bit isSingle = 0> {
+  defvar ps = !cast<VOP3_Pseudo>(opName#"_e64");
+  let IsSingle = !or(isSingle, ps.Pfl.IsSingle) in
+    def _e64#Gen.Suffix :
+      VOP3_Real_Gen<ps, Gen, asmName>,
+      VOP3be_gfx11_gfx12<op, ps.Pfl> ;
+}
+
+multiclass VOP3be_Real_dpp<GFXGen Gen, bits<10> op, string opName,
+                           string asmName> {
+  defvar ps = !cast<VOP3_Pseudo>(opName #"_e64");
+  defvar dpp_ps = !cast<VOP_DPP_Pseudo>(opName #"_e64" #"_dpp");
+  def _e64_dpp#Gen.Suffix : Base_VOP3b_DPP16<op, dpp_ps, asmName>,
+                            SIMCInstr<dpp_ps.PseudoInstr, Gen.Subtarget> {
+    let DecoderNamespace = "DPP"#Gen.DecoderNamespace;
+    let AssemblerPredicate = Gen.AssemblerPredicate;
   }
-} // End AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11"
+}
+
+multiclass VOP3be_Real_dpp8<GFXGen Gen, bits<10> op, string opName,
+                            string asmName> {
+  defvar ps = !cast<VOP3_Pseudo>(opName #"_e64");
+  def _e64_dpp8#Gen.Suffix : VOP3b_DPP8_Base<op, ps, asmName> {
+    let DecoderNamespace = "DPP8"#Gen.DecoderNamespace;
+    let AssemblerPredicate = Gen.AssemblerPredicate;
+  }
+}
 
 // VOP1 and VOP2 depend on these triple defs
-multiclass VOP3_Realtriple_gfx11<bits<10> op,
-                                 bit isSingle = 0, string opName = NAME> :
-  VOP3_Real_Base_gfx11<op, opName, isSingle>,
-  VOP3_Real_dpp_Base_gfx11<op, opName>,
-  VOP3_Real_dpp8_Base_gfx11<op, opName>;
-
-multiclass VOP3Dot_Realtriple_gfx11<bits<10> op,
-                                 bit isSingle = 0, string opName = NAME> :
-  VOP3Dot_Real_Base_gfx11<op, opName, isSingle>,
-  VOP3Dot_Real_dpp_Base_gfx11<op, opName>,
-  VOP3Dot_Real_dpp8_Base_gfx11<op, opName>;
-
-multiclass VOP3Only_Realtriple_gfx11<bits<10> op> :
-  VOP3_Realtriple_gfx11<op, 1>;
-
-multiclass VOP3_Realtriple_with_name_gfx11<bits<10> op, string opName,
-                                           string asmName, bit isSingle = 0> :
-  VOP3_Real_with_name_gfx11<op, opName, asmName, isSingle>,
-  VOP3_Real_dpp_with_name_gfx11<op, opName, asmName>,
-  VOP3_Real_dpp8_with_name_gfx11<op, opName, asmName>;
+multiclass VOP3_Realtriple<GFXGen Gen, bits<10> op, bit isSingle = 0,
+                           string opName = NAME> :
+  VOP3_Real_Base<Gen, op, opName, isSingle>,
+  VOP3_Real_dpp_Base<Gen, op, opName>,
+  VOP3_Real_dpp8_Base<Gen, op, opName>;
+
+multiclass VOP3Dot_Realtriple<GFXGen Gen, bits<10> op, bit isSingle = 0,
+                              string opName = NAME> :
+  VOP3Dot_Real_Base<Gen, op, opName, isSingle>,
+  VOP3Dot_Real_dpp_Base<Gen, op, opName>,
+  VOP3Dot_Real_dpp8_Base<Gen, op, opName>;
+
+multiclass VOP3Only_Realtriple<GFXGen Gen, bits<10> op> :
+  VOP3_Realtriple<Gen, op, 1>;
+
+multiclass VOP3_Realtriple_with_name<GFXGen Gen, bits<10> op, string opName,
+                                     string asmName, bit isSingle = 0> :
+  VOP3_Real_with_name<Gen, op, opName, asmName, isSingle>,
+  VOP3_Real_dpp_with_name<Gen, op, opName, asmName>,
+  VOP3_Real_dpp8_with_name<Gen, op, opName, asmName>;
+
+multiclass VOP3Only_Realtriple_with_name<GFXGen Gen, bits<10> op, string opName,
+                                         string asmName> :
+  VOP3_Realtriple_with_name<Gen, op, opName, asmName, 1>;
+
+multiclass VOP3Only_Realtriple_t16<GFXGen Gen, bits<10> op, string asmName,
+                                   string opName = NAME>
+    : VOP3Only_Realtriple_with_name<Gen, op, opName, asmName>;
+
+multiclass VOP3be_Realtriple<
+    GFXGen Gen, bits<10> op, bit isSingle = 0, string opName = NAME,
+    string asmName = !cast<VOP_Pseudo>(opName#"_e64").Mnemonic> :
+  VOP3be_Real<Gen, op, opName, asmName, isSingle>,
+  VOP3be_Real_dpp<Gen, op, opName, asmName>,
+  VOP3be_Real_dpp8<Gen, op, opName, asmName>;
 
-multiclass VOP3Only_Realtriple_with_name_gfx11<bits<10> op, string opName,
-                                               string asmName> :
-  VOP3_Realtriple_with_name_gfx11<op, opName, asmName, 1>;
+multiclass VOP3beOnly_Realtriple<GFXGen Gen, bits<10> op> :
+  VOP3be_Realtriple<Gen, op, 1>;
+
+//===----------------------------------------------------------------------===//
+// VOP3 GFX11
+//===----------------------------------------------------------------------===//
+
+multiclass VOP3be_Real_gfx11<bits<10> op, string opName, string asmName,
+                             bit isSingle = 0> :
+  VOP3be_Real<GFX11Gen, op, opName, asmName, isSingle>;
+
+multiclass VOP3_Real_Base_gfx11<bits<10> op, string opName = NAME,
+                                bit isSingle = 0> :
+  VOP3_Real_Base<GFX11Gen, op, opName, isSingle>;
+
+multiclass VOP3_Realtriple_gfx11<bits<10> op, bit isSingle = 0,
+                                 string opName = NAME> :
+  VOP3_Realtriple<GFX11Gen, op, isSingle, opName>;
 
 multiclass VOP3Only_Realtriple_t16_gfx11<bits<10> op, string asmName,
                                      string opName = NAME>
-    : VOP3Only_Realtriple_with_name_gfx11<op, opName, asmName>;
+    : VOP3Only_Realtriple_with_name<GFX11Gen, op, opName, asmName>;
 
-multiclass VOP3be_Realtriple_gfx11<
-    bits<10> op, bit isSingle = 0, string opName = NAME,
-    string asmName = !cast<VOP_Pseudo>(opName#"_e64").Mnemonic> :
-  VOP3be_Real_gfx11<op, opName, asmName, isSingle>,
-  VOP3be_Real_dpp_gfx11<op, opName, asmName>,
-  VOP3be_Real_dpp8_gfx11<op, opName, asmName>;
+//===----------------------------------------------------------------------===//
+// VOP3 GFX12
+//===----------------------------------------------------------------------===//
+
+multiclass VOP3Only_Realtriple_gfx12<bits<10> op, bit isSingle = 0> :
+  VOP3_Realtriple<GFX12Gen, op, isSingle>;
+
+// IsSingle is captured from the vopprofile for these instructions, but the
+// following alternative is more explicit
+multiclass VOP3Only_Real_Base_gfx12<bits<10> op> :
+  VOP3_Real_Base<GFX12Gen, op, NAME, 1/*IsSingle*/>;
+
+multiclass VOP3Only_Realtriple_t16_gfx12<bits<10> op> :
+  VOP3Only_Realtriple<GFX12Gen, op>;
 
-multiclass VOP3beOnly_Realtriple_gfx11<bits<10> op> :
-  VOP3be_Realtriple_gfx11<op, 1>;
+multiclass VOP3be_Real_with_name_gfx12<bits<10> op, string opName,
+                                       string asmName, bit isSingle = 0> {
+  defvar ps = !cast<VOP3_Pseudo>(opName#"_e64");
+  let AsmString = asmName # ps.AsmOperands,
+      IsSingle = !or(isSingle, ps.Pfl.IsSingle) in
+    def _e64_gfx12 :
+      VOP3_Real_Gen<ps, GFX12Gen, asmName>,
+      VOP3be_gfx11_gfx12<op, ps.Pfl>,
+      MnemonicAlias<ps.Mnemonic, asmName>, Requires<[isGFX12Only]>;
+}
+
+multiclass VOP3_Realtriple_with_name_gfx12<bits<10> op, string opName,
+                                           string asmName, bit isSingle = 0> :
+  VOP3_Realtriple_with_name<GFX12Gen, op, opName, asmName, isSingle>;
+
+multiclass VOP3Only_Realtriple_with_name_gfx11_gfx12<bits<10> op, string opName,
+                                                     string asmName> :
+  VOP3Only_Realtriple_with_name<GFX11Gen, op, opName, asmName>,
+  VOP3Only_Realtriple_with_name<GFX12Gen, op, opName, asmName>;
+
+multiclass VOP3Only_Realtriple_with_name_t16_gfx12<bits<10> op, string asmName,
+                                     string opName = NAME>
+    : VOP3Only_Realtriple_with_name<GFX12Gen, op, opName, asmName>;
+
+//===----------------------------------------------------------------------===//
 
 include "VOPCInstructions.td"
 include "VOP1Instructions.td"
diff --git a/llvm/test/CodeGen/AMDGPU/move-to-valu-lshlrev.mir b/llvm/test/CodeGen/AMDGPU/move-to-valu-lshlrev.mir
new file mode 100644
index 000000000000..a81d2ab44c17
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/move-to-valu-lshlrev.mir
@@ -0,0 +1,32 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefix=GFX8 %s
+# RUN: llc -march=amdgcn -mcpu=gfx1200 -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefix=GFX12 %s
+
+---
+name:            lshlrev_b64
+body:             |
+  bb.0:
+    ; GFX8-LABEL: name: lshlrev_b64
+    ; GFX8: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
+    ; GFX8-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+    ; GFX8-NEXT: [[DEF2:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
+    ; GFX8-NEXT: [[V_LSHL_ADD_U64_e64_:%[0-9]+]]:vreg_64 = V_LSHL_ADD_U64_e64 [[DEF]], [[DEF1]], [[DEF2]], implicit $exec
+    ; GFX8-NEXT: [[DEF3:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+    ; GFX8-NEXT: [[DEF4:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+    ; GFX8-NEXT: [[V_LSHLREV_B64_e64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64_e64 [[DEF4]], [[V_LSHL_ADD_U64_e64_]], implicit $exec
+    ; GFX12-LABEL: name: lshlrev_b64
+    ; GFX12: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
+    ; GFX12-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+    ; GFX12-NEXT: [[DEF2:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
+    ; GFX12-NEXT: [[V_LSHL_ADD_U64_e64_:%[0-9]+]]:vreg_64 = V_LSHL_ADD_U64_e64 [[DEF]], [[DEF1]], [[DEF2]], implicit $exec
+    ; GFX12-NEXT: [[DEF3:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+    ; GFX12-NEXT: [[DEF4:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+    ; GFX12-NEXT: [[V_LSHLREV_B64_pseudo_e64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64_pseudo_e64 [[DEF4]], [[V_LSHL_ADD_U64_e64_]], implicit $exec
+    %0:vreg_64 = IMPLICIT_DEF
+    %1:vgpr_32 = IMPLICIT_DEF
+    %2:vreg_64 = IMPLICIT_DEF
+    %3:vreg_64 = V_LSHL_ADD_U64_e64 %0:vreg_64, %1:vgpr_32, %2:vreg_64, implicit $exec
+    %4:sreg_64 = COPY %3:vreg_64
+    %5:sreg_32 = IMPLICIT_DEF
+    %6:sreg_64 = S_LSHL_B64 killed %4:sreg_64, %5:sreg_32, implicit-def dead $scc
+...
diff --git a/llvm/test/CodeGen/AMDGPU/verify-vopd-gfx12.mir b/llvm/test/CodeGen/AMDGPU/verify-vopd-gfx12.mir
new file mode 100644
index 000000000000..e217a1993905
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/verify-vopd-gfx12.mir
@@ -0,0 +1,11 @@
+# RUN: not --crash llc -march=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -run-pass machineverifier -o /dev/null %s 2>&1 | FileCheck -check-prefix=GFX12-ERR %s
+
+# GFX12-ERR: *** Bad machine code: VOP* instruction violates constant bus restriction ***
+# GFX12-ERR: $vgpr2, $vgpr3 = V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx12 $sgpr0, $vgpr0, $sgpr1, $vgpr1, implicit $exec, implicit $mode, implicit $vcc, implicit $vcc_lo
+---
+name: vopd_cndmask_2sgpr
+body:            |
+  bb.0:
+    liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
+    $vgpr2, $vgpr3 = V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx12 $sgpr0, $vgpr0, $sgpr1, $vgpr1, implicit $exec, implicit $mode, implicit $vcc, implicit $vcc_lo
+...
diff --git a/llvm/test/CodeGen/AMDGPU/verify-vopd.mir b/llvm/test/CodeGen/AMDGPU/verify-vopd.mir
index 5cc9503d88e9..f14a541ae14d 100644
--- a/llvm/test/CodeGen/AMDGPU/verify-vopd.mir
+++ b/llvm/test/CodeGen/AMDGPU/verify-vopd.mir
@@ -1,11 +1,11 @@
 # RUN: not --crash llc -march=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -run-pass machineverifier -o /dev/null %s 2>&1 | FileCheck -check-prefix=GFX11-ERR %s
 
 # GFX11-ERR: *** Bad machine code: VOP* instruction violates constant bus restriction ***
-# GFX11-ERR: $vgpr2, $vgpr3 = V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32 $sgpr0, $vgpr0, $sgpr1, $vgpr1, implicit $exec, implicit $mode, implicit $vcc, implicit $vcc_lo
+# GFX11-ERR: $vgpr2, $vgpr3 = V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx11 $sgpr0, $vgpr0, $sgpr1, $vgpr1, implicit $exec, implicit $mode, implicit $vcc, implicit $vcc_lo
 ---
 name: vopd_cndmask_2sgpr
 body:            |
   bb.0:
     liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
-    $vgpr2, $vgpr3 = V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32 $sgpr0, $vgpr0, $sgpr1, $vgpr1, implicit $exec, implicit $mode, implicit $vcc, implicit $vcc_lo
+    $vgpr2, $vgpr3 = V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx11 $sgpr0, $vgpr0, $sgpr1, $vgpr1, implicit $exec, implicit $mode, implicit $vcc, implicit $vcc_lo
 ...
diff --git a/llvm/test/CodeGen/AMDGPU/vopd-combine.mir b/llvm/test/CodeGen/AMDGPU/vopd-combine.mir
index 2cbabe61d1fe..0175b87a09d9 100644
--- a/llvm/test/CodeGen/AMDGPU/vopd-combine.mir
+++ b/llvm/test/CodeGen/AMDGPU/vopd-combine.mir
@@ -1,6 +1,8 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs -run-pass=postmisched %s -o - | FileCheck -check-prefix=SCHED %s
-# RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs -run-pass=postmisched,gcn-create-vopd %s -o - | FileCheck -check-prefix=PAIR %s
+# RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs -run-pass=postmisched,gcn-create-vopd %s -o - | FileCheck -check-prefixes=PAIR,PAIR-GFX11 %s
+# RUN: llc -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs -run-pass=postmisched %s -o - | FileCheck -check-prefix=SCHED %s
+# RUN: llc -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs -run-pass=postmisched,gcn-create-vopd %s -o - | FileCheck -check-prefixes=PAIR,PAIR-GFX12 %s
 
 --- |
   @lds = external addrspace(3) global [8 x i8]
@@ -20,6 +22,7 @@
   define void @vopd_mov_fixup() { ret void }
   define void @vopd_mov_fixup_fail() { ret void }
   define void @vopd_no_combine_dependent_subreg() { ret void }
+  define void @vopd_mov_mov_same_src_bank() { ret void }
 ...
 
 ---
@@ -35,12 +38,18 @@ body:             |
     ; SCHED-NEXT: $vgpr3 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
     ; SCHED-NEXT: $vgpr6 = V_MUL_F32_e32 killed $vgpr0, $vgpr0, implicit $mode, implicit $exec
     ; SCHED-NEXT: $vgpr4 = V_SUB_F32_e32 killed $vgpr1, $vgpr1, implicit $mode, implicit $exec
-    ; PAIR-LABEL: name: vopd_schedule
-    ; PAIR: $vgpr0 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr1 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
-    ; PAIR-NEXT: $vgpr3, $vgpr6 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32 $vgpr1, $vgpr1, killed $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
-    ; PAIR-NEXT: $vgpr4 = V_SUB_F32_e32 killed $vgpr1, $vgpr1, implicit $mode, implicit $exec
+    ; PAIR-GFX11-LABEL: name: vopd_schedule
+    ; PAIR-GFX11: $vgpr0 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr1 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+    ; PAIR-GFX11-NEXT: $vgpr3, $vgpr6 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx11 $vgpr1, $vgpr1, killed $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; PAIR-GFX11-NEXT: $vgpr4 = V_SUB_F32_e32 killed $vgpr1, $vgpr1, implicit $mode, implicit $exec
+    ; PAIR-GFX12-LABEL: name: vopd_schedule
+    ; PAIR-GFX12: $vgpr0 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr1 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+    ; PAIR-GFX12-NEXT: $vgpr3, $vgpr6 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx12 $vgpr1, $vgpr1, killed $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; PAIR-GFX12-NEXT: $vgpr4 = V_SUB_F32_e32 killed $vgpr1, $vgpr1, implicit $mode, implicit $exec
     $vgpr0 = IMPLICIT_DEF
     $vgpr1 = IMPLICIT_DEF
     $vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
@@ -64,12 +73,18 @@ body:             |
     ; SCHED-NEXT: $vgpr3 = IMPLICIT_DEF
     ; SCHED-NEXT: $vgpr5 = V_FMAMK_F32 killed $vgpr0, 10, killed $vgpr3, implicit $mode, implicit $exec
     ; SCHED-NEXT: $vgpr2 = V_FMAC_F32_e32 killed $vgpr1, $vgpr1, killed $vgpr2, implicit $mode, implicit $exec
-    ; PAIR-LABEL: name: vopd_fmamk
-    ; PAIR: $vgpr2 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr0 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr1 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr3 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr5, $vgpr2 = V_DUAL_FMAMK_F32_X_FMAC_F32_e32 killed $vgpr0, 10, killed $vgpr3, killed $vgpr1, $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; PAIR-GFX11-LABEL: name: vopd_fmamk
+    ; PAIR-GFX11: $vgpr2 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr0 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr1 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr3 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr5, $vgpr2 = V_DUAL_FMAMK_F32_X_FMAC_F32_e32_gfx11 killed $vgpr0, 10, killed $vgpr3, killed $vgpr1, $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; PAIR-GFX12-LABEL: name: vopd_fmamk
+    ; PAIR-GFX12: $vgpr2 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr0 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr1 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr3 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr5, $vgpr2 = V_DUAL_FMAMK_F32_X_FMAC_F32_e32_gfx12 killed $vgpr0, 10, killed $vgpr3, killed $vgpr1, $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
     $vgpr0 = IMPLICIT_DEF
     $vgpr1 = IMPLICIT_DEF
     $vgpr2 = IMPLICIT_DEF
@@ -127,17 +142,28 @@ body:             |
     ; SCHED-NEXT: $vgpr7 = V_CNDMASK_B32_e32 killed $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc
     ; SCHED-NEXT: $vgpr6 = V_ADD_F32_e32 $sgpr20, $vgpr3, implicit $mode, implicit $exec
     ; SCHED-NEXT: $vgpr9 = V_CNDMASK_B32_e32 killed $sgpr20, killed $vgpr3, implicit $mode, implicit $exec, implicit $vcc
-    ; PAIR-LABEL: name: vopd_cndmask
-    ; PAIR: $vgpr2 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr0 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr1 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr3 = IMPLICIT_DEF
-    ; PAIR-NEXT: $sgpr20 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr4 = V_FMAMK_F32 $sgpr20, 12345, $vgpr3, implicit $mode, implicit $exec
-    ; PAIR-NEXT: $vgpr2, $vgpr5 = V_DUAL_FMAC_F32_e32_X_CNDMASK_B32_e32 $sgpr20, killed $vgpr1, killed $vgpr2, $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc
-    ; PAIR-NEXT: $vgpr7 = V_CNDMASK_B32_e32 killed $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc
-    ; PAIR-NEXT: $vgpr6 = V_ADD_F32_e32 $sgpr20, $vgpr3, implicit $mode, implicit $exec
-    ; PAIR-NEXT: $vgpr9 = V_CNDMASK_B32_e32 killed $sgpr20, killed $vgpr3, implicit $mode, implicit $exec, implicit $vcc
+    ; PAIR-GFX11-LABEL: name: vopd_cndmask
+    ; PAIR-GFX11: $vgpr2 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr0 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr1 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr3 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $sgpr20 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr4 = V_FMAMK_F32 $sgpr20, 12345, $vgpr3, implicit $mode, implicit $exec
+    ; PAIR-GFX11-NEXT: $vgpr2, $vgpr5 = V_DUAL_FMAC_F32_e32_X_CNDMASK_B32_e32_gfx11 $sgpr20, killed $vgpr1, killed $vgpr2, $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc
+    ; PAIR-GFX11-NEXT: $vgpr7 = V_CNDMASK_B32_e32 killed $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc
+    ; PAIR-GFX11-NEXT: $vgpr6 = V_ADD_F32_e32 $sgpr20, $vgpr3, implicit $mode, implicit $exec
+    ; PAIR-GFX11-NEXT: $vgpr9 = V_CNDMASK_B32_e32 killed $sgpr20, killed $vgpr3, implicit $mode, implicit $exec, implicit $vcc
+    ; PAIR-GFX12-LABEL: name: vopd_cndmask
+    ; PAIR-GFX12: $vgpr2 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr0 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr1 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr3 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $sgpr20 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr4 = V_FMAMK_F32 $sgpr20, 12345, $vgpr3, implicit $mode, implicit $exec
+    ; PAIR-GFX12-NEXT: $vgpr2, $vgpr5 = V_DUAL_FMAC_F32_e32_X_CNDMASK_B32_e32_gfx12 $sgpr20, killed $vgpr1, killed $vgpr2, $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc
+    ; PAIR-GFX12-NEXT: $vgpr7 = V_CNDMASK_B32_e32 killed $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc
+    ; PAIR-GFX12-NEXT: $vgpr6 = V_ADD_F32_e32 $sgpr20, $vgpr3, implicit $mode, implicit $exec
+    ; PAIR-GFX12-NEXT: $vgpr9 = V_CNDMASK_B32_e32 killed $sgpr20, killed $vgpr3, implicit $mode, implicit $exec, implicit $vcc
     $vgpr0 = IMPLICIT_DEF
     $vgpr1 = IMPLICIT_DEF
     $vgpr2 = IMPLICIT_DEF
@@ -166,10 +192,14 @@ body:             |
     ; SCHED-NEXT: $vgpr1 = IMPLICIT_DEF
     ; SCHED-NEXT: $vgpr2 = V_MOV_B32_e32 killed $vgpr0, implicit $exec
     ; SCHED-NEXT: $vgpr3 = V_ADD_F32_e32 killed $vgpr1, $vgpr1, implicit $mode, implicit $exec
-    ; PAIR-LABEL: name: vopd_mov
-    ; PAIR: $vgpr0 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr1 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr2, $vgpr3 = V_DUAL_MOV_B32_e32_X_ADD_F32_e32 killed $vgpr0, killed $vgpr1, $vgpr1, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; PAIR-GFX11-LABEL: name: vopd_mov
+    ; PAIR-GFX11: $vgpr0 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr1 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr2, $vgpr3 = V_DUAL_MOV_B32_e32_X_ADD_F32_e32_gfx11 killed $vgpr0, killed $vgpr1, $vgpr1, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; PAIR-GFX12-LABEL: name: vopd_mov
+    ; PAIR-GFX12: $vgpr0 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr1 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr2, $vgpr3 = V_DUAL_MOV_B32_e32_X_ADD_F32_e32_gfx12 killed $vgpr0, killed $vgpr1, $vgpr1, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
     $vgpr0 = IMPLICIT_DEF
     $vgpr1 = IMPLICIT_DEF
     $vgpr2 = V_MOV_B32_e32 $vgpr0, implicit $exec
@@ -188,10 +218,14 @@ body:             |
     ; SCHED-NEXT: $sgpr7 = IMPLICIT_DEF
     ; SCHED-NEXT: $vgpr2 = V_MOV_B32_e32 killed $sgpr0, implicit $exec
     ; SCHED-NEXT: $vgpr3 = V_MOV_B32_e32 killed $sgpr7, implicit $exec
-    ; PAIR-LABEL: name: vopd_mov_mov
-    ; PAIR: $sgpr0 = IMPLICIT_DEF
-    ; PAIR-NEXT: $sgpr7 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr2, $vgpr3 = V_DUAL_MOV_B32_e32_X_MOV_B32_e32 killed $sgpr0, killed $sgpr7, implicit $exec, implicit $exec, implicit $exec
+    ; PAIR-GFX11-LABEL: name: vopd_mov_mov
+    ; PAIR-GFX11: $sgpr0 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $sgpr7 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr2, $vgpr3 = V_DUAL_MOV_B32_e32_X_MOV_B32_e32_gfx11 killed $sgpr0, killed $sgpr7, implicit $exec, implicit $exec, implicit $exec
+    ; PAIR-GFX12-LABEL: name: vopd_mov_mov
+    ; PAIR-GFX12: $sgpr0 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $sgpr7 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr2, $vgpr3 = V_DUAL_MOV_B32_e32_X_MOV_B32_e32_gfx12 killed $sgpr0, killed $sgpr7, implicit $exec, implicit $exec, implicit $exec
     $sgpr0 = IMPLICIT_DEF
     $sgpr7 = IMPLICIT_DEF
     $vgpr2 = V_MOV_B32_e32 $sgpr0, implicit $exec
@@ -242,12 +276,18 @@ body:             |
     ; SCHED-NEXT: $vgpr3 = IMPLICIT_DEF
     ; SCHED-NEXT: $vgpr5 = V_FMAMK_F32 killed $vgpr0, 100, killed $vgpr3, implicit $mode, implicit $exec
     ; SCHED-NEXT: $vgpr2 = V_FMAC_F32_e32 4, killed $vgpr1, killed $vgpr2, implicit $mode, implicit $exec
-    ; PAIR-LABEL: name: vopd_constants_inlinable
-    ; PAIR: $vgpr2 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr0 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr1 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr3 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr5, $vgpr2 = V_DUAL_FMAMK_F32_X_FMAC_F32_e32 killed $vgpr0, 100, killed $vgpr3, 4, killed $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; PAIR-GFX11-LABEL: name: vopd_constants_inlinable
+    ; PAIR-GFX11: $vgpr2 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr0 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr1 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr3 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr5, $vgpr2 = V_DUAL_FMAMK_F32_X_FMAC_F32_e32_gfx11 killed $vgpr0, 100, killed $vgpr3, 4, killed $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; PAIR-GFX12-LABEL: name: vopd_constants_inlinable
+    ; PAIR-GFX12: $vgpr2 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr0 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr1 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr3 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr5, $vgpr2 = V_DUAL_FMAMK_F32_X_FMAC_F32_e32_gfx12 killed $vgpr0, 100, killed $vgpr3, 4, killed $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
     $vgpr0 = IMPLICIT_DEF
     $vgpr1 = IMPLICIT_DEF
     $vgpr2 = IMPLICIT_DEF
@@ -272,12 +312,18 @@ body:             |
     ; SCHED-NEXT: $vgpr3 = IMPLICIT_DEF
     ; SCHED-NEXT: $vgpr5 = V_FMAMK_F32 killed $vgpr0, 100, killed $vgpr3, implicit $mode, implicit $exec
     ; SCHED-NEXT: $vgpr2 = V_FMAC_F32_e32 100, killed $vgpr1, killed $vgpr2, implicit $mode, implicit $exec
-    ; PAIR-LABEL: name: vopd_constants_same
-    ; PAIR: $vgpr2 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr0 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr1 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr3 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr5, $vgpr2 = V_DUAL_FMAMK_F32_X_FMAC_F32_e32 killed $vgpr0, 100, killed $vgpr3, 100, killed $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; PAIR-GFX11-LABEL: name: vopd_constants_same
+    ; PAIR-GFX11: $vgpr2 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr0 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr1 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr3 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr5, $vgpr2 = V_DUAL_FMAMK_F32_X_FMAC_F32_e32_gfx11 killed $vgpr0, 100, killed $vgpr3, 100, killed $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; PAIR-GFX12-LABEL: name: vopd_constants_same
+    ; PAIR-GFX12: $vgpr2 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr0 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr1 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr3 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr5, $vgpr2 = V_DUAL_FMAMK_F32_X_FMAC_F32_e32_gfx12 killed $vgpr0, 100, killed $vgpr3, 100, killed $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
     $vgpr0 = IMPLICIT_DEF
     $vgpr1 = IMPLICIT_DEF
     $vgpr2 = IMPLICIT_DEF
@@ -299,10 +345,14 @@ body:             |
     ; SCHED-NEXT: $sgpr0 = IMPLICIT_DEF
     ; SCHED-NEXT: $vgpr1 = V_MOV_B32_e32 981467136, implicit $exec
     ; SCHED-NEXT: $vgpr2 = V_FMAAK_F32 killed $sgpr0, killed $vgpr0, 981467136, implicit $mode, implicit $exec
-    ; PAIR-LABEL: name: vopd_mov_fmaak_constants_same
-    ; PAIR: $vgpr0 = IMPLICIT_DEF
-    ; PAIR-NEXT: $sgpr0 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr1, $vgpr2 = V_DUAL_MOV_B32_e32_X_FMAAK_F32 981467136, killed $sgpr0, killed $vgpr0, 981467136, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; PAIR-GFX11-LABEL: name: vopd_mov_fmaak_constants_same
+    ; PAIR-GFX11: $vgpr0 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $sgpr0 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr1, $vgpr2 = V_DUAL_MOV_B32_e32_X_FMAAK_F32_gfx11 981467136, killed $sgpr0, killed $vgpr0, 981467136, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; PAIR-GFX12-LABEL: name: vopd_mov_fmaak_constants_same
+    ; PAIR-GFX12: $vgpr0 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $sgpr0 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr1, $vgpr2 = V_DUAL_MOV_B32_e32_X_FMAAK_F32_gfx12 981467136, killed $sgpr0, killed $vgpr0, 981467136, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
     $vgpr0 = IMPLICIT_DEF
     $sgpr0 = IMPLICIT_DEF
     ; should be able to pair using 1 deduplicated literal
@@ -323,11 +373,16 @@ body:             |
     ; SCHED-NEXT: $vgpr3 = V_SUB_F32_e32 killed $vgpr1, $vgpr1, implicit $mode, implicit $exec
     ; SCHED-NEXT: DBG_VALUE $vgpr0, 0, 0
     ; SCHED-NEXT: $vgpr6 = V_MUL_F32_e32 killed $vgpr0, $vgpr0, implicit $mode, implicit $exec
-    ; PAIR-LABEL: name: vopd_debug
-    ; PAIR: $vgpr0 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr1 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr3, $vgpr6 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32 killed $vgpr1, $vgpr1, killed $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
-    ; PAIR-NEXT: DBG_VALUE $vgpr0, 0, 0
+    ; PAIR-GFX11-LABEL: name: vopd_debug
+    ; PAIR-GFX11: $vgpr0 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr1 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr3, $vgpr6 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx11 killed $vgpr1, $vgpr1, killed $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; PAIR-GFX11-NEXT: DBG_VALUE $vgpr0, 0, 0
+    ; PAIR-GFX12-LABEL: name: vopd_debug
+    ; PAIR-GFX12: $vgpr0 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr1 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr3, $vgpr6 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx12 killed $vgpr1, $vgpr1, killed $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; PAIR-GFX12-NEXT: DBG_VALUE $vgpr0, 0, 0
     $vgpr0 = IMPLICIT_DEF
     $vgpr1 = IMPLICIT_DEF
     ; TODO Debug values disable VOPD creation
@@ -361,21 +416,36 @@ body:             |
     ; SCHED-NEXT: $vgpr15 = V_CNDMASK_B32_e32 $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit $vcc
     ; SCHED-NEXT: $vgpr16 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
     ; SCHED-NEXT: $vgpr14 = V_SUB_F32_e32 killed $vgpr1, $vgpr1, implicit $mode, implicit $exec
-    ; PAIR-LABEL: name: vopd_schedule_unconstrained
-    ; PAIR: $vgpr2 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr3 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr0 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr1 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr4 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
-    ; PAIR-NEXT: $vgpr3, $vgpr6 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32 $vgpr1, $vgpr1, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
-    ; PAIR-NEXT: $vgpr2 = V_FMAC_F32_e32 10, $vgpr1, killed $vgpr2, implicit $mode, implicit $exec
-    ; PAIR-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
-    ; PAIR-NEXT: $vgpr12, $vgpr19 = V_DUAL_ADD_F32_e32_X_CNDMASK_B32_e32 $vgpr1, $vgpr1, $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc
-    ; PAIR-NEXT: $vgpr11 = V_CNDMASK_B32_e32 $vgpr0, killed $vgpr3, implicit $mode, implicit $exec, implicit $vcc
-    ; PAIR-NEXT: $vgpr17, $vgpr10 = V_DUAL_MUL_F32_e32_X_CNDMASK_B32_e32 killed $vgpr0, $vgpr0, $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc
-    ; PAIR-NEXT: $vgpr15 = V_CNDMASK_B32_e32 $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit $vcc
-    ; PAIR-NEXT: $vgpr16 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
-    ; PAIR-NEXT: $vgpr14 = V_SUB_F32_e32 killed $vgpr1, $vgpr1, implicit $mode, implicit $exec
+    ; PAIR-GFX11-LABEL: name: vopd_schedule_unconstrained
+    ; PAIR-GFX11: $vgpr2 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr3 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr0 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr1 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr4 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+    ; PAIR-GFX11-NEXT: $vgpr3, $vgpr6 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx11 $vgpr1, $vgpr1, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; PAIR-GFX11-NEXT: $vgpr2 = V_FMAC_F32_e32 10, $vgpr1, killed $vgpr2, implicit $mode, implicit $exec
+    ; PAIR-GFX11-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+    ; PAIR-GFX11-NEXT: $vgpr12, $vgpr19 = V_DUAL_ADD_F32_e32_X_CNDMASK_B32_e32_gfx11 $vgpr1, $vgpr1, $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc
+    ; PAIR-GFX11-NEXT: $vgpr11 = V_CNDMASK_B32_e32 $vgpr0, killed $vgpr3, implicit $mode, implicit $exec, implicit $vcc
+    ; PAIR-GFX11-NEXT: $vgpr17, $vgpr10 = V_DUAL_MUL_F32_e32_X_CNDMASK_B32_e32_gfx11 killed $vgpr0, $vgpr0, $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc
+    ; PAIR-GFX11-NEXT: $vgpr15 = V_CNDMASK_B32_e32 $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit $vcc
+    ; PAIR-GFX11-NEXT: $vgpr16 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+    ; PAIR-GFX11-NEXT: $vgpr14 = V_SUB_F32_e32 killed $vgpr1, $vgpr1, implicit $mode, implicit $exec
+    ; PAIR-GFX12-LABEL: name: vopd_schedule_unconstrained
+    ; PAIR-GFX12: $vgpr2 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr3 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr0 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr1 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr4 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+    ; PAIR-GFX12-NEXT: $vgpr3, $vgpr6 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx12 $vgpr1, $vgpr1, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; PAIR-GFX12-NEXT: $vgpr2 = V_FMAC_F32_e32 10, $vgpr1, killed $vgpr2, implicit $mode, implicit $exec
+    ; PAIR-GFX12-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+    ; PAIR-GFX12-NEXT: $vgpr12, $vgpr19 = V_DUAL_ADD_F32_e32_X_CNDMASK_B32_e32_gfx12 $vgpr1, $vgpr1, $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc
+    ; PAIR-GFX12-NEXT: $vgpr11 = V_CNDMASK_B32_e32 $vgpr0, killed $vgpr3, implicit $mode, implicit $exec, implicit $vcc
+    ; PAIR-GFX12-NEXT: $vgpr17, $vgpr10 = V_DUAL_MUL_F32_e32_X_CNDMASK_B32_e32_gfx12 killed $vgpr0, $vgpr0, $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc
+    ; PAIR-GFX12-NEXT: $vgpr15 = V_CNDMASK_B32_e32 $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit $vcc
+    ; PAIR-GFX12-NEXT: $vgpr16 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+    ; PAIR-GFX12-NEXT: $vgpr14 = V_SUB_F32_e32 killed $vgpr1, $vgpr1, implicit $mode, implicit $exec
     $vgpr0 = IMPLICIT_DEF
     $vgpr1 = IMPLICIT_DEF
     $vgpr2 = IMPLICIT_DEF
@@ -437,30 +507,54 @@ body:             |
     ; SCHED-NEXT: $vgpr33 = V_CNDMASK_B32_e32 $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit $vcc
     ; SCHED-NEXT: $vgpr34 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
     ; SCHED-NEXT: $vgpr32 = V_SUB_F32_e32 killed $vgpr1, $vgpr1, implicit $mode, implicit $exec
-    ; PAIR-LABEL: name: vopd_schedule_unconstrained_2
-    ; PAIR: $vgpr2 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr3 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr0 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr1 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr20 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr16, $vgpr35 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32 $vgpr1, $vgpr1, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
-    ; PAIR-NEXT: $vgpr3, $vgpr6 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32 $vgpr1, $vgpr1, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
-    ; PAIR-NEXT: $vgpr2 = V_FMAC_F32_e32 10, $vgpr1, killed $vgpr2, implicit $mode, implicit $exec
-    ; PAIR-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
-    ; PAIR-NEXT: $vgpr4, $vgpr29 = V_DUAL_SUB_F32_e32_X_CNDMASK_B32_e32 $vgpr1, $vgpr1, $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc
-    ; PAIR-NEXT: $vgpr19, $vgpr20 = V_DUAL_CNDMASK_B32_e32_X_FMAC_F32_e32 $vgpr0, $vgpr3, 10, $vgpr1, killed $vgpr20, implicit $vcc, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec
-    ; PAIR-NEXT: $vgpr15 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc
-    ; PAIR-NEXT: $vgpr10, $vgpr17 = V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32 $vgpr1, $vgpr2, $vgpr0, $vgpr0, implicit $vcc, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec
-    ; PAIR-NEXT: $vgpr11, $vgpr12 = V_DUAL_CNDMASK_B32_e32_X_ADD_F32_e32 $vgpr0, $vgpr3, $vgpr1, $vgpr1, implicit $vcc, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec
-    ; PAIR-NEXT: $vgpr37, $vgpr14 = V_DUAL_CNDMASK_B32_e32_X_SUB_F32_e32 $vgpr0, killed $vgpr3, $vgpr1, $vgpr1, implicit $vcc, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec
-    ; PAIR-NEXT: $vgpr20 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
-    ; PAIR-NEXT: $vgpr21, $vgpr24 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32 $vgpr1, $vgpr1, killed $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
-    ; PAIR-NEXT: $vgpr28 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc
-    ; PAIR-NEXT: $vgpr22 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
-    ; PAIR-NEXT: $vgpr31 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
-    ; PAIR-NEXT: $vgpr33 = V_CNDMASK_B32_e32 $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit $vcc
-    ; PAIR-NEXT: $vgpr34 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
-    ; PAIR-NEXT: $vgpr32 = V_SUB_F32_e32 killed $vgpr1, $vgpr1, implicit $mode, implicit $exec
+    ; PAIR-GFX11-LABEL: name: vopd_schedule_unconstrained_2
+    ; PAIR-GFX11: $vgpr2 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr3 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr0 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr1 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr20 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr16, $vgpr35 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx11 $vgpr1, $vgpr1, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; PAIR-GFX11-NEXT: $vgpr3, $vgpr6 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx11 $vgpr1, $vgpr1, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; PAIR-GFX11-NEXT: $vgpr2 = V_FMAC_F32_e32 10, $vgpr1, killed $vgpr2, implicit $mode, implicit $exec
+    ; PAIR-GFX11-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+    ; PAIR-GFX11-NEXT: $vgpr4, $vgpr29 = V_DUAL_SUB_F32_e32_X_CNDMASK_B32_e32_gfx11 $vgpr1, $vgpr1, $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc
+    ; PAIR-GFX11-NEXT: $vgpr19, $vgpr20 = V_DUAL_CNDMASK_B32_e32_X_FMAC_F32_e32_gfx11 $vgpr0, $vgpr3, 10, $vgpr1, killed $vgpr20, implicit $vcc, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec
+    ; PAIR-GFX11-NEXT: $vgpr15 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc
+    ; PAIR-GFX11-NEXT: $vgpr10, $vgpr17 = V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx11 $vgpr1, $vgpr2, $vgpr0, $vgpr0, implicit $vcc, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec
+    ; PAIR-GFX11-NEXT: $vgpr11, $vgpr12 = V_DUAL_CNDMASK_B32_e32_X_ADD_F32_e32_gfx11 $vgpr0, $vgpr3, $vgpr1, $vgpr1, implicit $vcc, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec
+    ; PAIR-GFX11-NEXT: $vgpr37, $vgpr14 = V_DUAL_CNDMASK_B32_e32_X_SUB_F32_e32_gfx11 $vgpr0, killed $vgpr3, $vgpr1, $vgpr1, implicit $vcc, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec
+    ; PAIR-GFX11-NEXT: $vgpr20 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+    ; PAIR-GFX11-NEXT: $vgpr21, $vgpr24 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx11 $vgpr1, $vgpr1, killed $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; PAIR-GFX11-NEXT: $vgpr28 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc
+    ; PAIR-GFX11-NEXT: $vgpr22 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+    ; PAIR-GFX11-NEXT: $vgpr31 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+    ; PAIR-GFX11-NEXT: $vgpr33 = V_CNDMASK_B32_e32 $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit $vcc
+    ; PAIR-GFX11-NEXT: $vgpr34 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+    ; PAIR-GFX11-NEXT: $vgpr32 = V_SUB_F32_e32 killed $vgpr1, $vgpr1, implicit $mode, implicit $exec
+    ; PAIR-GFX12-LABEL: name: vopd_schedule_unconstrained_2
+    ; PAIR-GFX12: $vgpr2 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr3 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr0 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr1 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr20 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr16, $vgpr35 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx12 $vgpr1, $vgpr1, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; PAIR-GFX12-NEXT: $vgpr3, $vgpr6 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx12 $vgpr1, $vgpr1, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; PAIR-GFX12-NEXT: $vgpr2 = V_FMAC_F32_e32 10, $vgpr1, killed $vgpr2, implicit $mode, implicit $exec
+    ; PAIR-GFX12-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+    ; PAIR-GFX12-NEXT: $vgpr4, $vgpr29 = V_DUAL_SUB_F32_e32_X_CNDMASK_B32_e32_gfx12 $vgpr1, $vgpr1, $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc
+    ; PAIR-GFX12-NEXT: $vgpr19, $vgpr20 = V_DUAL_CNDMASK_B32_e32_X_FMAC_F32_e32_gfx12 $vgpr0, $vgpr3, 10, $vgpr1, killed $vgpr20, implicit $vcc, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec
+    ; PAIR-GFX12-NEXT: $vgpr15 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc
+    ; PAIR-GFX12-NEXT: $vgpr10, $vgpr17 = V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx12 $vgpr1, $vgpr2, $vgpr0, $vgpr0, implicit $vcc, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec
+    ; PAIR-GFX12-NEXT: $vgpr11, $vgpr12 = V_DUAL_CNDMASK_B32_e32_X_ADD_F32_e32_gfx12 $vgpr0, $vgpr3, $vgpr1, $vgpr1, implicit $vcc, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec
+    ; PAIR-GFX12-NEXT: $vgpr37, $vgpr14 = V_DUAL_CNDMASK_B32_e32_X_SUB_F32_e32_gfx12 $vgpr0, killed $vgpr3, $vgpr1, $vgpr1, implicit $vcc, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec
+    ; PAIR-GFX12-NEXT: $vgpr20 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+    ; PAIR-GFX12-NEXT: $vgpr21, $vgpr24 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx12 $vgpr1, $vgpr1, killed $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; PAIR-GFX12-NEXT: $vgpr28 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc
+    ; PAIR-GFX12-NEXT: $vgpr22 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+    ; PAIR-GFX12-NEXT: $vgpr31 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+    ; PAIR-GFX12-NEXT: $vgpr33 = V_CNDMASK_B32_e32 $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit $vcc
+    ; PAIR-GFX12-NEXT: $vgpr34 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
+    ; PAIR-GFX12-NEXT: $vgpr32 = V_SUB_F32_e32 killed $vgpr1, $vgpr1, implicit $mode, implicit $exec
     $vgpr0 = IMPLICIT_DEF
     $vgpr1 = IMPLICIT_DEF
     $vgpr2 = IMPLICIT_DEF
@@ -513,11 +607,16 @@ body: |
     ; SCHED-NEXT: $vgpr3 = V_ADD_F32_e32 killed $vgpr0, killed $vgpr1, implicit $mode, implicit $exec
     ; SCHED-NEXT: $vgpr4 = V_MOV_B32_e32 target-flags(amdgpu-abs32-lo) @lds, implicit $exec
     ; SCHED-NEXT: $vgpr5 = V_MOV_B32_e32 target-flags(amdgpu-abs32-lo) @lds, implicit $exec
-    ; PAIR-LABEL: name: vopd_mov_fixup
-    ; PAIR: $vgpr0 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr1 = IMPLICIT_DEF
-    ; PAIR-NEXT: $vgpr2, $vgpr3 = V_DUAL_MOV_B32_e32_X_ADD_F32_e32 target-flags(amdgpu-abs32-lo) @lds, killed $vgpr0, killed $vgpr1, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
-    ; PAIR-NEXT: $vgpr4, $vgpr5 = V_DUAL_MOV_B32_e32_X_MOV_B32_e32 target-flags(amdgpu-abs32-lo) @lds, target-flags(amdgpu-abs32-lo) @lds, implicit $exec, implicit $exec, implicit $exec
+    ; PAIR-GFX11-LABEL: name: vopd_mov_fixup
+    ; PAIR-GFX11: $vgpr0 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr1 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr2, $vgpr3 = V_DUAL_MOV_B32_e32_X_ADD_F32_e32_gfx11 target-flags(amdgpu-abs32-lo) @lds, killed $vgpr0, killed $vgpr1, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; PAIR-GFX11-NEXT: $vgpr4, $vgpr5 = V_DUAL_MOV_B32_e32_X_MOV_B32_e32_gfx11 target-flags(amdgpu-abs32-lo) @lds, target-flags(amdgpu-abs32-lo) @lds, implicit $exec, implicit $exec, implicit $exec
+    ; PAIR-GFX12-LABEL: name: vopd_mov_fixup
+    ; PAIR-GFX12: $vgpr0 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr1 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr2, $vgpr3 = V_DUAL_MOV_B32_e32_X_ADD_F32_e32_gfx12 target-flags(amdgpu-abs32-lo) @lds, killed $vgpr0, killed $vgpr1, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; PAIR-GFX12-NEXT: $vgpr4, $vgpr5 = V_DUAL_MOV_B32_e32_X_MOV_B32_e32_gfx12 target-flags(amdgpu-abs32-lo) @lds, target-flags(amdgpu-abs32-lo) @lds, implicit $exec, implicit $exec, implicit $exec
     $vgpr0 = IMPLICIT_DEF
     $vgpr1 = IMPLICIT_DEF
     ; should pair
@@ -561,3 +660,29 @@ body:             |
     $vgpr2 = V_MOV_B32_e32 0, implicit-def $vgpr2_vgpr3, implicit $exec
     $vgpr5 = V_ADD_F32_e32 $vgpr0, $vgpr3, implicit $mode, implicit $exec
 ...
+
+---
+name:            vopd_mov_mov_same_src_bank
+tracksRegLiveness: true
+body:             |
+  bb.0:
+
+    ; SCHED-LABEL: name: vopd_mov_mov_same_src_bank
+    ; SCHED: $vgpr1 = IMPLICIT_DEF
+    ; SCHED-NEXT: $vgpr5 = IMPLICIT_DEF
+    ; SCHED-NEXT: $vgpr2 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
+    ; SCHED-NEXT: $vgpr3 = V_MOV_B32_e32 killed $vgpr5, implicit $exec
+    ; PAIR-GFX11-LABEL: name: vopd_mov_mov_same_src_bank
+    ; PAIR-GFX11: $vgpr1 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr5 = IMPLICIT_DEF
+    ; PAIR-GFX11-NEXT: $vgpr2 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
+    ; PAIR-GFX11-NEXT: $vgpr3 = V_MOV_B32_e32 killed $vgpr5, implicit $exec
+    ; PAIR-GFX12-LABEL: name: vopd_mov_mov_same_src_bank
+    ; PAIR-GFX12: $vgpr1 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr5 = IMPLICIT_DEF
+    ; PAIR-GFX12-NEXT: $vgpr2, $vgpr3 = V_DUAL_MOV_B32_e32_X_MOV_B32_e32_gfx12 killed $vgpr1, killed $vgpr5, implicit $exec, implicit $exec, implicit $exec
+    $vgpr1 = IMPLICIT_DEF
+    $vgpr5 = IMPLICIT_DEF
+    $vgpr2 = V_MOV_B32_e32 $vgpr1, implicit $exec
+    $vgpr3 = V_MOV_B32_e32 $vgpr5, implicit $exec
+...
diff --git a/llvm/test/CodeGen/AMDGPU/vopd-src2acc-delay.mir b/llvm/test/CodeGen/AMDGPU/vopd-src2acc-delay.mir
index 72c9242481f5..00974ad51f06 100644
--- a/llvm/test/CodeGen/AMDGPU/vopd-src2acc-delay.mir
+++ b/llvm/test/CodeGen/AMDGPU/vopd-src2acc-delay.mir
@@ -12,9 +12,9 @@ body: |
     ; CHECK-NEXT: $vgpr2 = IMPLICIT_DEF
     ; CHECK-NEXT: $vgpr3 = IMPLICIT_DEF
     ; CHECK-NEXT: $vgpr4 = IMPLICIT_DEF
-    ; CHECK-NEXT: $vgpr0, $vgpr1 = V_DUAL_FMAC_F32_e32_X_FMAC_F32_e32 $vgpr2, $vgpr3, $vgpr0, $vgpr3, $vgpr4, $vgpr1, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; CHECK-NEXT: $vgpr0, $vgpr1 = V_DUAL_FMAC_F32_e32_X_FMAC_F32_e32_gfx11 $vgpr2, $vgpr3, $vgpr0, $vgpr3, $vgpr4, $vgpr1, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
     ; CHECK-NEXT: S_DELAY_ALU 1
-    ; CHECK-NEXT: $vgpr0, $vgpr1 = V_DUAL_FMAC_F32_e32_X_FMAC_F32_e32 $vgpr2, $vgpr3, $vgpr0, $vgpr3, $vgpr4, $vgpr1, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; CHECK-NEXT: $vgpr0, $vgpr1 = V_DUAL_FMAC_F32_e32_X_FMAC_F32_e32_gfx11 $vgpr2, $vgpr3, $vgpr0, $vgpr3, $vgpr4, $vgpr1, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
     $vgpr0 = IMPLICIT_DEF
     $vgpr1 = IMPLICIT_DEF
     $vgpr2 = IMPLICIT_DEF
@@ -36,9 +36,9 @@ body: |
     ; CHECK-NEXT: $vgpr2 = IMPLICIT_DEF
     ; CHECK-NEXT: $vgpr3 = IMPLICIT_DEF
     ; CHECK-NEXT: $vgpr4 = IMPLICIT_DEF
-    ; CHECK-NEXT: $vgpr0, $vgpr1 = V_DUAL_DOT2C_F32_F16_e32_X_DOT2C_F32_F16_e32 $vgpr2, $vgpr3, $vgpr0, $vgpr3, $vgpr4, $vgpr1, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; CHECK-NEXT: $vgpr0, $vgpr1 = V_DUAL_DOT2C_F32_F16_e32_X_DOT2C_F32_F16_e32_gfx11 $vgpr2, $vgpr3, $vgpr0, $vgpr3, $vgpr4, $vgpr1, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
     ; CHECK-NEXT: S_DELAY_ALU 1
-    ; CHECK-NEXT: $vgpr0, $vgpr1 = V_DUAL_DOT2C_F32_F16_e32_X_DOT2C_F32_F16_e32 $vgpr2, $vgpr3, $vgpr0, $vgpr3, $vgpr4, $vgpr1, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
+    ; CHECK-NEXT: $vgpr0, $vgpr1 = V_DUAL_DOT2C_F32_F16_e32_X_DOT2C_F32_F16_e32_gfx11 $vgpr2, $vgpr3, $vgpr0, $vgpr3, $vgpr4, $vgpr1, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec
     $vgpr0 = IMPLICIT_DEF
     $vgpr1 = IMPLICIT_DEF
     $vgpr2 = IMPLICIT_DEF
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop1.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop1.s
new file mode 100644
index 000000000000..35411ee0ba2a
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop1.s
@@ -0,0 +1,3545 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX12 %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX12 %s
+
+v_bfrev_b32_e32 v5, v1
+// GFX12: encoding: [0x01,0x71,0x0a,0x7e]
+
+v_bfrev_b32 v5, v255
+// GFX12: encoding: [0xff,0x71,0x0a,0x7e]
+
+v_bfrev_b32 v5, s1
+// GFX12: encoding: [0x01,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, s105
+// GFX12: encoding: [0x69,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, m0
+// GFX12: encoding: [0x7d,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, null
+// GFX12: encoding: [0x7c,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, -1
+// GFX12: encoding: [0xc1,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, 0.5
+// GFX12: encoding: [0xf0,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, src_scc
+// GFX12: encoding: [0xfd,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x70,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_ceil_f16 v5, v1
+// GFX12: encoding: [0x01,0xb9,0x0a,0x7e]
+
+v_ceil_f16 v5, v127
+// GFX12: encoding: [0x7f,0xb9,0x0a,0x7e]
+
+v_ceil_f16 v5, s1
+// GFX12: encoding: [0x01,0xb8,0x0a,0x7e]
+
+v_ceil_f16 v5, s105
+// GFX12: encoding: [0x69,0xb8,0x0a,0x7e]
+
+v_ceil_f16 v5, vcc_lo
+// GFX12: encoding: [0x6a,0xb8,0x0a,0x7e]
+
+v_ceil_f16 v5, vcc_hi
+// GFX12: encoding: [0x6b,0xb8,0x0a,0x7e]
+
+v_ceil_f16 v5, ttmp15
+// GFX12: encoding: [0x7b,0xb8,0x0a,0x7e]
+
+v_ceil_f16 v5, m0
+// GFX12: encoding: [0x7d,0xb8,0x0a,0x7e]
+
+v_ceil_f16 v5, exec_lo
+// GFX12: encoding: [0x7e,0xb8,0x0a,0x7e]
+
+v_ceil_f16 v5, exec_hi
+// GFX12: encoding: [0x7f,0xb8,0x0a,0x7e]
+
+v_ceil_f16 v5, null
+// GFX12: encoding: [0x7c,0xb8,0x0a,0x7e]
+
+v_ceil_f16 v5, -1
+// GFX12: encoding: [0xc1,0xb8,0x0a,0x7e]
+
+v_ceil_f16 v5, 0.5
+// GFX12: encoding: [0xf0,0xb8,0x0a,0x7e]
+
+v_ceil_f16 v5, src_scc
+// GFX12: encoding: [0xfd,0xb8,0x0a,0x7e]
+
+v_ceil_f16 v127, 0xfe0b
+// GFX12: encoding: [0xff,0xb8,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_ceil_f32 v5, v1
+// GFX12: encoding: [0x01,0x45,0x0a,0x7e]
+
+v_ceil_f32 v5, v255
+// GFX12: encoding: [0xff,0x45,0x0a,0x7e]
+
+v_ceil_f32 v5, s1
+// GFX12: encoding: [0x01,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, s105
+// GFX12: encoding: [0x69,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, m0
+// GFX12: encoding: [0x7d,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, null
+// GFX12: encoding: [0x7c,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, -1
+// GFX12: encoding: [0xc1,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, 0.5
+// GFX12: encoding: [0xf0,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, src_scc
+// GFX12: encoding: [0xfd,0x44,0x0a,0x7e]
+
+v_ceil_f32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x44,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_ceil_f64 v[5:6], v[1:2]
+// GFX12: encoding: [0x01,0x31,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], v[254:255]
+// GFX12: encoding: [0xfe,0x31,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], s[2:3]
+// GFX12: encoding: [0x02,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], s[104:105]
+// GFX12: encoding: [0x68,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], vcc
+// GFX12: encoding: [0x6a,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], ttmp[14:15]
+// GFX12: encoding: [0x7a,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], exec
+// GFX12: encoding: [0x7e,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], null
+// GFX12: encoding: [0x7c,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], -1
+// GFX12: encoding: [0xc1,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], 0.5
+// GFX12: encoding: [0xf0,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], src_scc
+// GFX12: encoding: [0xfd,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[254:255], 0xaf123456
+// GFX12: encoding: [0xff,0x30,0xfc,0x7f,0x56,0x34,0x12,0xaf]
+
+v_cls_i32 v5, v1
+// GFX12: encoding: [0x01,0x77,0x0a,0x7e]
+
+v_cls_i32 v5, v255
+// GFX12: encoding: [0xff,0x77,0x0a,0x7e]
+
+v_cls_i32 v5, s1
+// GFX12: encoding: [0x01,0x76,0x0a,0x7e]
+
+v_cls_i32 v5, s105
+// GFX12: encoding: [0x69,0x76,0x0a,0x7e]
+
+v_cls_i32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x76,0x0a,0x7e]
+
+v_cls_i32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x76,0x0a,0x7e]
+
+v_cls_i32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x76,0x0a,0x7e]
+
+v_cls_i32 v5, m0
+// GFX12: encoding: [0x7d,0x76,0x0a,0x7e]
+
+v_cls_i32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x76,0x0a,0x7e]
+
+v_cls_i32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x76,0x0a,0x7e]
+
+v_cls_i32 v5, null
+// GFX12: encoding: [0x7c,0x76,0x0a,0x7e]
+
+v_cls_i32 v5, -1
+// GFX12: encoding: [0xc1,0x76,0x0a,0x7e]
+
+v_cls_i32 v5, 0.5
+// GFX12: encoding: [0xf0,0x76,0x0a,0x7e]
+
+v_cls_i32 v5, src_scc
+// GFX12: encoding: [0xfd,0x76,0x0a,0x7e]
+
+v_cls_i32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x76,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_clz_i32_u32 v5, v1
+// GFX12: encoding: [0x01,0x73,0x0a,0x7e]
+
+v_clz_i32_u32 v5, v255
+// GFX12: encoding: [0xff,0x73,0x0a,0x7e]
+
+v_clz_i32_u32 v5, s1
+// GFX12: encoding: [0x01,0x72,0x0a,0x7e]
+
+v_clz_i32_u32 v5, s105
+// GFX12: encoding: [0x69,0x72,0x0a,0x7e]
+
+v_clz_i32_u32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x72,0x0a,0x7e]
+
+v_clz_i32_u32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x72,0x0a,0x7e]
+
+v_clz_i32_u32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x72,0x0a,0x7e]
+
+v_clz_i32_u32 v5, m0
+// GFX12: encoding: [0x7d,0x72,0x0a,0x7e]
+
+v_clz_i32_u32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x72,0x0a,0x7e]
+
+v_clz_i32_u32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x72,0x0a,0x7e]
+
+v_clz_i32_u32 v5, null
+// GFX12: encoding: [0x7c,0x72,0x0a,0x7e]
+
+v_clz_i32_u32 v5, -1
+// GFX12: encoding: [0xc1,0x72,0x0a,0x7e]
+
+v_clz_i32_u32 v5, 0.5
+// GFX12: encoding: [0xf0,0x72,0x0a,0x7e]
+
+v_clz_i32_u32 v5, src_scc
+// GFX12: encoding: [0xfd,0x72,0x0a,0x7e]
+
+v_clz_i32_u32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x72,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_cos_f16 v5, v1
+// GFX12: encoding: [0x01,0xc3,0x0a,0x7e]
+
+v_cos_f16 v5, v127
+// GFX12: encoding: [0x7f,0xc3,0x0a,0x7e]
+
+v_cos_f16 v5, s1
+// GFX12: encoding: [0x01,0xc2,0x0a,0x7e]
+
+v_cos_f16 v5, s105
+// GFX12: encoding: [0x69,0xc2,0x0a,0x7e]
+
+v_cos_f16 v5, vcc_lo
+// GFX12: encoding: [0x6a,0xc2,0x0a,0x7e]
+
+v_cos_f16 v5, vcc_hi
+// GFX12: encoding: [0x6b,0xc2,0x0a,0x7e]
+
+v_cos_f16 v5, ttmp15
+// GFX12: encoding: [0x7b,0xc2,0x0a,0x7e]
+
+v_cos_f16 v5, m0
+// GFX12: encoding: [0x7d,0xc2,0x0a,0x7e]
+
+v_cos_f16 v5, exec_lo
+// GFX12: encoding: [0x7e,0xc2,0x0a,0x7e]
+
+v_cos_f16 v5, exec_hi
+// GFX12: encoding: [0x7f,0xc2,0x0a,0x7e]
+
+v_cos_f16 v5, null
+// GFX12: encoding: [0x7c,0xc2,0x0a,0x7e]
+
+v_cos_f16 v5, -1
+// GFX12: encoding: [0xc1,0xc2,0x0a,0x7e]
+
+v_cos_f16 v5, 0.5
+// GFX12: encoding: [0xf0,0xc2,0x0a,0x7e]
+
+v_cos_f16 v5, src_scc
+// GFX12: encoding: [0xfd,0xc2,0x0a,0x7e]
+
+v_cos_f16 v127, 0xfe0b
+// GFX12: encoding: [0xff,0xc2,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_cos_f32 v5, v1
+// GFX12: encoding: [0x01,0x6d,0x0a,0x7e]
+
+v_cos_f32 v5, v255
+// GFX12: encoding: [0xff,0x6d,0x0a,0x7e]
+
+v_cos_f32 v5, s1
+// GFX12: encoding: [0x01,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, s105
+// GFX12: encoding: [0x69,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, m0
+// GFX12: encoding: [0x7d,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, null
+// GFX12: encoding: [0x7c,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, -1
+// GFX12: encoding: [0xc1,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, 0.5
+// GFX12: encoding: [0xf0,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, src_scc
+// GFX12: encoding: [0xfd,0x6c,0x0a,0x7e]
+
+v_cos_f32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x6c,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_ctz_i32_b32 v5, v1
+// GFX12: encoding: [0x01,0x75,0x0a,0x7e]
+
+v_ctz_i32_b32 v5, v255
+// GFX12: encoding: [0xff,0x75,0x0a,0x7e]
+
+v_ctz_i32_b32 v5, s1
+// GFX12: encoding: [0x01,0x74,0x0a,0x7e]
+
+v_ctz_i32_b32 v5, s105
+// GFX12: encoding: [0x69,0x74,0x0a,0x7e]
+
+v_ctz_i32_b32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x74,0x0a,0x7e]
+
+v_ctz_i32_b32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x74,0x0a,0x7e]
+
+v_ctz_i32_b32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x74,0x0a,0x7e]
+
+v_ctz_i32_b32 v5, m0
+// GFX12: encoding: [0x7d,0x74,0x0a,0x7e]
+
+v_ctz_i32_b32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x74,0x0a,0x7e]
+
+v_ctz_i32_b32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x74,0x0a,0x7e]
+
+v_ctz_i32_b32 v5, null
+// GFX12: encoding: [0x7c,0x74,0x0a,0x7e]
+
+v_ctz_i32_b32 v5, -1
+// GFX12: encoding: [0xc1,0x74,0x0a,0x7e]
+
+v_ctz_i32_b32 v5, 0.5
+// GFX12: encoding: [0xf0,0x74,0x0a,0x7e]
+
+v_ctz_i32_b32 v5, src_scc
+// GFX12: encoding: [0xfd,0x74,0x0a,0x7e]
+
+v_ctz_i32_b32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x74,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_cvt_f16_f32 v5, v1
+// GFX12: encoding: [0x01,0x15,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, v255
+// GFX12: encoding: [0xff,0x15,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, s1
+// GFX12: encoding: [0x01,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, s105
+// GFX12: encoding: [0x69,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, m0
+// GFX12: encoding: [0x7d,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, null
+// GFX12: encoding: [0x7c,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, -1
+// GFX12: encoding: [0xc1,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, 0.5
+// GFX12: encoding: [0xf0,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, src_scc
+// GFX12: encoding: [0xfd,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v127, 0xaf123456
+// GFX12: encoding: [0xff,0x14,0xfe,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f16_i16 v5, v1
+// GFX12: encoding: [0x01,0xa3,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, v127
+// GFX12: encoding: [0x7f,0xa3,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, s1
+// GFX12: encoding: [0x01,0xa2,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, s105
+// GFX12: encoding: [0x69,0xa2,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, vcc_lo
+// GFX12: encoding: [0x6a,0xa2,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, vcc_hi
+// GFX12: encoding: [0x6b,0xa2,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, ttmp15
+// GFX12: encoding: [0x7b,0xa2,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, m0
+// GFX12: encoding: [0x7d,0xa2,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, exec_lo
+// GFX12: encoding: [0x7e,0xa2,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, exec_hi
+// GFX12: encoding: [0x7f,0xa2,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, null
+// GFX12: encoding: [0x7c,0xa2,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, -1
+// GFX12: encoding: [0xc1,0xa2,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, 0.5
+// GFX12: encoding: [0xff,0xa2,0x0a,0x7e,0x00,0x38,0x00,0x00]
+
+v_cvt_f16_i16 v5, src_scc
+// GFX12: encoding: [0xfd,0xa2,0x0a,0x7e]
+
+v_cvt_f16_i16 v127, 0xfe0b
+// GFX12: encoding: [0xff,0xa2,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_cvt_f16_u16 v5, v1
+// GFX12: encoding: [0x01,0xa1,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, v127
+// GFX12: encoding: [0x7f,0xa1,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, s1
+// GFX12: encoding: [0x01,0xa0,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, s105
+// GFX12: encoding: [0x69,0xa0,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, vcc_lo
+// GFX12: encoding: [0x6a,0xa0,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, vcc_hi
+// GFX12: encoding: [0x6b,0xa0,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, ttmp15
+// GFX12: encoding: [0x7b,0xa0,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, m0
+// GFX12: encoding: [0x7d,0xa0,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, exec_lo
+// GFX12: encoding: [0x7e,0xa0,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, exec_hi
+// GFX12: encoding: [0x7f,0xa0,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, null
+// GFX12: encoding: [0x7c,0xa0,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, -1
+// GFX12: encoding: [0xc1,0xa0,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, 0.5
+// GFX12: encoding: [0xff,0xa0,0x0a,0x7e,0x00,0x38,0x00,0x00]
+
+v_cvt_f16_u16 v5, src_scc
+// GFX12: encoding: [0xfd,0xa0,0x0a,0x7e]
+
+v_cvt_f16_u16 v127, 0xfe0b
+// GFX12: encoding: [0xff,0xa0,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_cvt_f32_f16 v5, v1
+// GFX12: encoding: [0x01,0x17,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, v127
+// GFX12: encoding: [0x7f,0x17,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, s1
+// GFX12: encoding: [0x01,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, s105
+// GFX12: encoding: [0x69,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, ttmp15
+// GFX12: encoding: [0x7b,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, m0
+// GFX12: encoding: [0x7d,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, exec_lo
+// GFX12: encoding: [0x7e,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, exec_hi
+// GFX12: encoding: [0x7f,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, null
+// GFX12: encoding: [0x7c,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, -1
+// GFX12: encoding: [0xc1,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, 0.5
+// GFX12: encoding: [0xf0,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, src_scc
+// GFX12: encoding: [0xfd,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v255, 0xfe0b
+// GFX12: encoding: [0xff,0x16,0xfe,0x7f,0x0b,0xfe,0x00,0x00]
+
+v_cvt_f32_f64 v5, v[1:2]
+// GFX12: encoding: [0x01,0x1f,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, v[254:255]
+// GFX12: encoding: [0xfe,0x1f,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, s[2:3]
+// GFX12: encoding: [0x02,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, s[104:105]
+// GFX12: encoding: [0x68,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, vcc
+// GFX12: encoding: [0x6a,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, ttmp[14:15]
+// GFX12: encoding: [0x7a,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, exec
+// GFX12: encoding: [0x7e,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, null
+// GFX12: encoding: [0x7c,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, -1
+// GFX12: encoding: [0xc1,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, 0.5
+// GFX12: encoding: [0xf0,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, src_scc
+// GFX12: encoding: [0xfd,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x1e,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_i32 v5, v1
+// GFX12: encoding: [0x01,0x0b,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, v255
+// GFX12: encoding: [0xff,0x0b,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, s1
+// GFX12: encoding: [0x01,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, s105
+// GFX12: encoding: [0x69,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, m0
+// GFX12: encoding: [0x7d,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, null
+// GFX12: encoding: [0x7c,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, -1
+// GFX12: encoding: [0xc1,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, 0.5
+// GFX12: encoding: [0xf0,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, src_scc
+// GFX12: encoding: [0xfd,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x0a,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_u32 v5, v1
+// GFX12: encoding: [0x01,0x0d,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, v255
+// GFX12: encoding: [0xff,0x0d,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, s1
+// GFX12: encoding: [0x01,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, s105
+// GFX12: encoding: [0x69,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, m0
+// GFX12: encoding: [0x7d,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, null
+// GFX12: encoding: [0x7c,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, -1
+// GFX12: encoding: [0xc1,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, 0.5
+// GFX12: encoding: [0xf0,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, src_scc
+// GFX12: encoding: [0xfd,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x0c,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_ubyte0 v5, v1
+// GFX12: encoding: [0x01,0x23,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, v255
+// GFX12: encoding: [0xff,0x23,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, s1
+// GFX12: encoding: [0x01,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, s105
+// GFX12: encoding: [0x69,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, ttmp15
+// GFX12: encoding: [0x7b,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, m0
+// GFX12: encoding: [0x7d,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, exec_lo
+// GFX12: encoding: [0x7e,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, exec_hi
+// GFX12: encoding: [0x7f,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, null
+// GFX12: encoding: [0x7c,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, -1
+// GFX12: encoding: [0xc1,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, 0.5
+// GFX12: encoding: [0xf0,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, src_scc
+// GFX12: encoding: [0xfd,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x22,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_ubyte1 v5, v1
+// GFX12: encoding: [0x01,0x25,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, v255
+// GFX12: encoding: [0xff,0x25,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, s1
+// GFX12: encoding: [0x01,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, s105
+// GFX12: encoding: [0x69,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, ttmp15
+// GFX12: encoding: [0x7b,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, m0
+// GFX12: encoding: [0x7d,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, exec_lo
+// GFX12: encoding: [0x7e,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, exec_hi
+// GFX12: encoding: [0x7f,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, null
+// GFX12: encoding: [0x7c,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, -1
+// GFX12: encoding: [0xc1,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, 0.5
+// GFX12: encoding: [0xf0,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, src_scc
+// GFX12: encoding: [0xfd,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x24,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_ubyte2 v5, v1
+// GFX12: encoding: [0x01,0x27,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, v255
+// GFX12: encoding: [0xff,0x27,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, s1
+// GFX12: encoding: [0x01,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, s105
+// GFX12: encoding: [0x69,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, ttmp15
+// GFX12: encoding: [0x7b,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, m0
+// GFX12: encoding: [0x7d,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, exec_lo
+// GFX12: encoding: [0x7e,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, exec_hi
+// GFX12: encoding: [0x7f,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, null
+// GFX12: encoding: [0x7c,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, -1
+// GFX12: encoding: [0xc1,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, 0.5
+// GFX12: encoding: [0xf0,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, src_scc
+// GFX12: encoding: [0xfd,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x26,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_ubyte3 v5, v1
+// GFX12: encoding: [0x01,0x29,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, v255
+// GFX12: encoding: [0xff,0x29,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, s1
+// GFX12: encoding: [0x01,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, s105
+// GFX12: encoding: [0x69,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, ttmp15
+// GFX12: encoding: [0x7b,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, m0
+// GFX12: encoding: [0x7d,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, exec_lo
+// GFX12: encoding: [0x7e,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, exec_hi
+// GFX12: encoding: [0x7f,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, null
+// GFX12: encoding: [0x7c,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, -1
+// GFX12: encoding: [0xc1,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, 0.5
+// GFX12: encoding: [0xf0,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, src_scc
+// GFX12: encoding: [0xfd,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x28,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_cvt_f64_f32 v[5:6], v1
+// GFX12: encoding: [0x01,0x21,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], v255
+// GFX12: encoding: [0xff,0x21,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], s1
+// GFX12: encoding: [0x01,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], s105
+// GFX12: encoding: [0x69,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], vcc_lo
+// GFX12: encoding: [0x6a,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], vcc_hi
+// GFX12: encoding: [0x6b,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], ttmp15
+// GFX12: encoding: [0x7b,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], m0
+// GFX12: encoding: [0x7d,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], exec_lo
+// GFX12: encoding: [0x7e,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], exec_hi
+// GFX12: encoding: [0x7f,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], null
+// GFX12: encoding: [0x7c,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], -1
+// GFX12: encoding: [0xc1,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], 0.5
+// GFX12: encoding: [0xf0,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], src_scc
+// GFX12: encoding: [0xfd,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[254:255], 0xaf123456
+// GFX12: encoding: [0xff,0x20,0xfc,0x7f,0x56,0x34,0x12,0xaf]
+
+v_cvt_f64_i32 v[5:6], v1
+// GFX12: encoding: [0x01,0x09,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], v255
+// GFX12: encoding: [0xff,0x09,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], s1
+// GFX12: encoding: [0x01,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], s105
+// GFX12: encoding: [0x69,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], vcc_lo
+// GFX12: encoding: [0x6a,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], vcc_hi
+// GFX12: encoding: [0x6b,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], ttmp15
+// GFX12: encoding: [0x7b,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], m0
+// GFX12: encoding: [0x7d,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], exec_lo
+// GFX12: encoding: [0x7e,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], exec_hi
+// GFX12: encoding: [0x7f,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], null
+// GFX12: encoding: [0x7c,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], -1
+// GFX12: encoding: [0xc1,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], 0.5
+// GFX12: encoding: [0xf0,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], src_scc
+// GFX12: encoding: [0xfd,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[254:255], 0xaf123456
+// GFX12: encoding: [0xff,0x08,0xfc,0x7f,0x56,0x34,0x12,0xaf]
+
+v_cvt_f64_u32 v[5:6], v1
+// GFX12: encoding: [0x01,0x2d,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], v255
+// GFX12: encoding: [0xff,0x2d,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], s1
+// GFX12: encoding: [0x01,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], s105
+// GFX12: encoding: [0x69,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], vcc_lo
+// GFX12: encoding: [0x6a,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], vcc_hi
+// GFX12: encoding: [0x6b,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], ttmp15
+// GFX12: encoding: [0x7b,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], m0
+// GFX12: encoding: [0x7d,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], exec_lo
+// GFX12: encoding: [0x7e,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], exec_hi
+// GFX12: encoding: [0x7f,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], null
+// GFX12: encoding: [0x7c,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], -1
+// GFX12: encoding: [0xc1,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], 0.5
+// GFX12: encoding: [0xf0,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], src_scc
+// GFX12: encoding: [0xfd,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[254:255], 0xaf123456
+// GFX12: encoding: [0xff,0x2c,0xfc,0x7f,0x56,0x34,0x12,0xaf]
+
+v_cvt_floor_i32_f32 v5, v1
+// GFX12: encoding: [0x01,0x1b,0x0a,0x7e]
+
+v_cvt_floor_i32_f32 v5, v255
+// GFX12: encoding: [0xff,0x1b,0x0a,0x7e]
+
+v_cvt_floor_i32_f32 v5, s1
+// GFX12: encoding: [0x01,0x1a,0x0a,0x7e]
+
+v_cvt_floor_i32_f32 v5, s105
+// GFX12: encoding: [0x69,0x1a,0x0a,0x7e]
+
+v_cvt_floor_i32_f32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x1a,0x0a,0x7e]
+
+v_cvt_floor_i32_f32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x1a,0x0a,0x7e]
+
+v_cvt_floor_i32_f32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x1a,0x0a,0x7e]
+
+v_cvt_floor_i32_f32 v5, m0
+// GFX12: encoding: [0x7d,0x1a,0x0a,0x7e]
+
+v_cvt_floor_i32_f32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x1a,0x0a,0x7e]
+
+v_cvt_floor_i32_f32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x1a,0x0a,0x7e]
+
+v_cvt_floor_i32_f32 v5, null
+// GFX12: encoding: [0x7c,0x1a,0x0a,0x7e]
+
+v_cvt_floor_i32_f32 v5, -1
+// GFX12: encoding: [0xc1,0x1a,0x0a,0x7e]
+
+v_cvt_floor_i32_f32 v5, 0.5
+// GFX12: encoding: [0xf0,0x1a,0x0a,0x7e]
+
+v_cvt_floor_i32_f32 v5, src_scc
+// GFX12: encoding: [0xfd,0x1a,0x0a,0x7e]
+
+v_cvt_floor_i32_f32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x1a,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_cvt_flr_i32_f32 v5, v1
+// GFX12: encoding: [0x01,0x1b,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, v255
+// GFX12: encoding: [0xff,0x1b,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, s1
+// GFX12: encoding: [0x01,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, s105
+// GFX12: encoding: [0x69,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, m0
+// GFX12: encoding: [0x7d,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, null
+// GFX12: encoding: [0x7c,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, -1
+// GFX12: encoding: [0xc1,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, 0.5
+// GFX12: encoding: [0xf0,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, src_scc
+// GFX12: encoding: [0xfd,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x1a,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_cvt_i16_f16 v5, v1
+// GFX12: encoding: [0x01,0xa7,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, v127
+// GFX12: encoding: [0x7f,0xa7,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, s1
+// GFX12: encoding: [0x01,0xa6,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, s105
+// GFX12: encoding: [0x69,0xa6,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, vcc_lo
+// GFX12: encoding: [0x6a,0xa6,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, vcc_hi
+// GFX12: encoding: [0x6b,0xa6,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, ttmp15
+// GFX12: encoding: [0x7b,0xa6,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, m0
+// GFX12: encoding: [0x7d,0xa6,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, exec_lo
+// GFX12: encoding: [0x7e,0xa6,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, exec_hi
+// GFX12: encoding: [0x7f,0xa6,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, null
+// GFX12: encoding: [0x7c,0xa6,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, -1
+// GFX12: encoding: [0xc1,0xa6,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, 0.5
+// GFX12: encoding: [0xf0,0xa6,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, src_scc
+// GFX12: encoding: [0xfd,0xa6,0x0a,0x7e]
+
+v_cvt_i16_f16 v127, 0xfe0b
+// GFX12: encoding: [0xff,0xa6,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_cvt_i32_f32 v5, v1
+// GFX12: encoding: [0x01,0x11,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, v255
+// GFX12: encoding: [0xff,0x11,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, s1
+// GFX12: encoding: [0x01,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, s105
+// GFX12: encoding: [0x69,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, m0
+// GFX12: encoding: [0x7d,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, null
+// GFX12: encoding: [0x7c,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, -1
+// GFX12: encoding: [0xc1,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, 0.5
+// GFX12: encoding: [0xf0,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, src_scc
+// GFX12: encoding: [0xfd,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x10,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_cvt_i32_f64 v5, v[1:2]
+// GFX12: encoding: [0x01,0x07,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, v[254:255]
+// GFX12: encoding: [0xfe,0x07,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, s[2:3]
+// GFX12: encoding: [0x02,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, s[104:105]
+// GFX12: encoding: [0x68,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, vcc
+// GFX12: encoding: [0x6a,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, ttmp[14:15]
+// GFX12: encoding: [0x7a,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, exec
+// GFX12: encoding: [0x7e,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, null
+// GFX12: encoding: [0x7c,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, -1
+// GFX12: encoding: [0xc1,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, 0.5
+// GFX12: encoding: [0xf0,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, src_scc
+// GFX12: encoding: [0xfd,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x06,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_cvt_i32_i16 v5, v1
+// GFX12: encoding: [0x01,0xd5,0x0a,0x7e]
+
+v_cvt_i32_i16 v5, v127
+// GFX12: encoding: [0x7f,0xd5,0x0a,0x7e]
+
+v_cvt_i32_i16 v5, s1
+// GFX12: encoding: [0x01,0xd4,0x0a,0x7e]
+
+v_cvt_i32_i16 v5, s105
+// GFX12: encoding: [0x69,0xd4,0x0a,0x7e]
+
+v_cvt_i32_i16 v5, vcc_lo
+// GFX12: encoding: [0x6a,0xd4,0x0a,0x7e]
+
+v_cvt_i32_i16 v5, vcc_hi
+// GFX12: encoding: [0x6b,0xd4,0x0a,0x7e]
+
+v_cvt_i32_i16 v5, ttmp15
+// GFX12: encoding: [0x7b,0xd4,0x0a,0x7e]
+
+v_cvt_i32_i16 v5, m0
+// GFX12: encoding: [0x7d,0xd4,0x0a,0x7e]
+
+v_cvt_i32_i16 v5, exec_lo
+// GFX12: encoding: [0x7e,0xd4,0x0a,0x7e]
+
+v_cvt_i32_i16 v5, exec_hi
+// GFX12: encoding: [0x7f,0xd4,0x0a,0x7e]
+
+v_cvt_i32_i16 v5, null
+// GFX12: encoding: [0x7c,0xd4,0x0a,0x7e]
+
+v_cvt_i32_i16 v5, -1
+// GFX12: encoding: [0xc1,0xd4,0x0a,0x7e]
+
+v_cvt_i32_i16 v5, 0.5
+// GFX12: encoding: [0xff,0xd4,0x0a,0x7e,0x00,0x38,0x00,0x00]
+
+v_cvt_i32_i16 v5, src_scc
+// GFX12: encoding: [0xfd,0xd4,0x0a,0x7e]
+
+v_cvt_i32_i16 v255, 0xfe0b
+// GFX12: encoding: [0xff,0xd4,0xfe,0x7f,0x0b,0xfe,0x00,0x00]
+
+v_cvt_nearest_i32_f32 v5, v1
+// GFX12: encoding: [0x01,0x19,0x0a,0x7e]
+
+v_cvt_nearest_i32_f32 v5, v255
+// GFX12: encoding: [0xff,0x19,0x0a,0x7e]
+
+v_cvt_nearest_i32_f32 v5, s1
+// GFX12: encoding: [0x01,0x18,0x0a,0x7e]
+
+v_cvt_nearest_i32_f32 v5, s105
+// GFX12: encoding: [0x69,0x18,0x0a,0x7e]
+
+v_cvt_nearest_i32_f32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x18,0x0a,0x7e]
+
+v_cvt_nearest_i32_f32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x18,0x0a,0x7e]
+
+v_cvt_nearest_i32_f32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x18,0x0a,0x7e]
+
+v_cvt_nearest_i32_f32 v5, m0
+// GFX12: encoding: [0x7d,0x18,0x0a,0x7e]
+
+v_cvt_nearest_i32_f32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x18,0x0a,0x7e]
+
+v_cvt_nearest_i32_f32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x18,0x0a,0x7e]
+
+v_cvt_nearest_i32_f32 v5, null
+// GFX12: encoding: [0x7c,0x18,0x0a,0x7e]
+
+v_cvt_nearest_i32_f32 v5, -1
+// GFX12: encoding: [0xc1,0x18,0x0a,0x7e]
+
+v_cvt_nearest_i32_f32 v5, 0.5
+// GFX12: encoding: [0xf0,0x18,0x0a,0x7e]
+
+v_cvt_nearest_i32_f32 v5, src_scc
+// GFX12: encoding: [0xfd,0x18,0x0a,0x7e]
+
+v_cvt_nearest_i32_f32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x18,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_cvt_norm_i16_f16 v5, v1
+// GFX12: encoding: [0x01,0xc7,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, v127
+// GFX12: encoding: [0x7f,0xc7,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, s1
+// GFX12: encoding: [0x01,0xc6,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, s105
+// GFX12: encoding: [0x69,0xc6,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, vcc_lo
+// GFX12: encoding: [0x6a,0xc6,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, vcc_hi
+// GFX12: encoding: [0x6b,0xc6,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, ttmp15
+// GFX12: encoding: [0x7b,0xc6,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, m0
+// GFX12: encoding: [0x7d,0xc6,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, exec_lo
+// GFX12: encoding: [0x7e,0xc6,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, exec_hi
+// GFX12: encoding: [0x7f,0xc6,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, null
+// GFX12: encoding: [0x7c,0xc6,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, -1
+// GFX12: encoding: [0xc1,0xc6,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, 0.5
+// GFX12: encoding: [0xf0,0xc6,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, src_scc
+// GFX12: encoding: [0xfd,0xc6,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v127, 0xfe0b
+// GFX12: encoding: [0xff,0xc6,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_cvt_norm_u16_f16 v5, v1
+// GFX12: encoding: [0x01,0xc9,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, v127
+// GFX12: encoding: [0x7f,0xc9,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, s1
+// GFX12: encoding: [0x01,0xc8,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, s105
+// GFX12: encoding: [0x69,0xc8,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, vcc_lo
+// GFX12: encoding: [0x6a,0xc8,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, vcc_hi
+// GFX12: encoding: [0x6b,0xc8,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, ttmp15
+// GFX12: encoding: [0x7b,0xc8,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, m0
+// GFX12: encoding: [0x7d,0xc8,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, exec_lo
+// GFX12: encoding: [0x7e,0xc8,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, exec_hi
+// GFX12: encoding: [0x7f,0xc8,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, null
+// GFX12: encoding: [0x7c,0xc8,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, -1
+// GFX12: encoding: [0xc1,0xc8,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, 0.5
+// GFX12: encoding: [0xf0,0xc8,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, src_scc
+// GFX12: encoding: [0xfd,0xc8,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v127, 0xfe0b
+// GFX12: encoding: [0xff,0xc8,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_cvt_off_f32_i4 v5, v1
+// GFX12: encoding: [0x01,0x1d,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, v255
+// GFX12: encoding: [0xff,0x1d,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, s1
+// GFX12: encoding: [0x01,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, s105
+// GFX12: encoding: [0x69,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, ttmp15
+// GFX12: encoding: [0x7b,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, m0
+// GFX12: encoding: [0x7d,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, exec_lo
+// GFX12: encoding: [0x7e,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, exec_hi
+// GFX12: encoding: [0x7f,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, null
+// GFX12: encoding: [0x7c,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, -1
+// GFX12: encoding: [0xc1,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, 0.5
+// GFX12: encoding: [0xf0,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, src_scc
+// GFX12: encoding: [0xfd,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v255, 0x4f
+// GFX12: encoding: [0xff,0x1c,0xfe,0x7f,0x4f,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32 v5, v1
+// GFX12: encoding: [0x01,0x19,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, v255
+// GFX12: encoding: [0xff,0x19,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, s1
+// GFX12: encoding: [0x01,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, s105
+// GFX12: encoding: [0x69,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, m0
+// GFX12: encoding: [0x7d,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, null
+// GFX12: encoding: [0x7c,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, -1
+// GFX12: encoding: [0xc1,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, 0.5
+// GFX12: encoding: [0xf0,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, src_scc
+// GFX12: encoding: [0xfd,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x18,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_cvt_u16_f16 v5, v1
+// GFX12: encoding: [0x01,0xa5,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, v127
+// GFX12: encoding: [0x7f,0xa5,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, s1
+// GFX12: encoding: [0x01,0xa4,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, s105
+// GFX12: encoding: [0x69,0xa4,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, vcc_lo
+// GFX12: encoding: [0x6a,0xa4,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, vcc_hi
+// GFX12: encoding: [0x6b,0xa4,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, ttmp15
+// GFX12: encoding: [0x7b,0xa4,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, m0
+// GFX12: encoding: [0x7d,0xa4,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, exec_lo
+// GFX12: encoding: [0x7e,0xa4,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, exec_hi
+// GFX12: encoding: [0x7f,0xa4,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, null
+// GFX12: encoding: [0x7c,0xa4,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, -1
+// GFX12: encoding: [0xc1,0xa4,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, 0.5
+// GFX12: encoding: [0xf0,0xa4,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, src_scc
+// GFX12: encoding: [0xfd,0xa4,0x0a,0x7e]
+
+v_cvt_u16_f16 v127, 0xfe0b
+// GFX12: encoding: [0xff,0xa4,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_cvt_u32_f32 v5, v1
+// GFX12: encoding: [0x01,0x0f,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, v255
+// GFX12: encoding: [0xff,0x0f,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, s1
+// GFX12: encoding: [0x01,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, s105
+// GFX12: encoding: [0x69,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, m0
+// GFX12: encoding: [0x7d,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, null
+// GFX12: encoding: [0x7c,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, -1
+// GFX12: encoding: [0xc1,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, 0.5
+// GFX12: encoding: [0xf0,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, src_scc
+// GFX12: encoding: [0xfd,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x0e,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_cvt_u32_f64 v5, v[1:2]
+// GFX12: encoding: [0x01,0x2b,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, v[254:255]
+// GFX12: encoding: [0xfe,0x2b,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, s[2:3]
+// GFX12: encoding: [0x02,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, s[104:105]
+// GFX12: encoding: [0x68,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, vcc
+// GFX12: encoding: [0x6a,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, ttmp[14:15]
+// GFX12: encoding: [0x7a,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, exec
+// GFX12: encoding: [0x7e,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, null
+// GFX12: encoding: [0x7c,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, -1
+// GFX12: encoding: [0xc1,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, 0.5
+// GFX12: encoding: [0xf0,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, src_scc
+// GFX12: encoding: [0xfd,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x2a,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_cvt_u32_u16 v5, v1
+// GFX12: encoding: [0x01,0xd7,0x0a,0x7e]
+
+v_cvt_u32_u16 v5, v127
+// GFX12: encoding: [0x7f,0xd7,0x0a,0x7e]
+
+v_cvt_u32_u16 v5, s1
+// GFX12: encoding: [0x01,0xd6,0x0a,0x7e]
+
+v_cvt_u32_u16 v5, s105
+// GFX12: encoding: [0x69,0xd6,0x0a,0x7e]
+
+v_cvt_u32_u16 v5, vcc_lo
+// GFX12: encoding: [0x6a,0xd6,0x0a,0x7e]
+
+v_cvt_u32_u16 v5, vcc_hi
+// GFX12: encoding: [0x6b,0xd6,0x0a,0x7e]
+
+v_cvt_u32_u16 v5, ttmp15
+// GFX12: encoding: [0x7b,0xd6,0x0a,0x7e]
+
+v_cvt_u32_u16 v5, m0
+// GFX12: encoding: [0x7d,0xd6,0x0a,0x7e]
+
+v_cvt_u32_u16 v5, exec_lo
+// GFX12: encoding: [0x7e,0xd6,0x0a,0x7e]
+
+v_cvt_u32_u16 v5, exec_hi
+// GFX12: encoding: [0x7f,0xd6,0x0a,0x7e]
+
+v_cvt_u32_u16 v5, null
+// GFX12: encoding: [0x7c,0xd6,0x0a,0x7e]
+
+v_cvt_u32_u16 v5, -1
+// GFX12: encoding: [0xc1,0xd6,0x0a,0x7e]
+
+v_cvt_u32_u16 v5, 0.5
+// GFX12: encoding: [0xff,0xd6,0x0a,0x7e,0x00,0x38,0x00,0x00]
+
+v_cvt_u32_u16 v5, src_scc
+// GFX12: encoding: [0xfd,0xd6,0x0a,0x7e]
+
+v_cvt_u32_u16 v255, 0xfe0b
+// GFX12: encoding: [0xff,0xd6,0xfe,0x7f,0x0b,0xfe,0x00,0x00]
+
+v_exp_f16 v5, v1
+// GFX12: encoding: [0x01,0xb1,0x0a,0x7e]
+
+v_exp_f16 v5, v127
+// GFX12: encoding: [0x7f,0xb1,0x0a,0x7e]
+
+v_exp_f16 v5, s1
+// GFX12: encoding: [0x01,0xb0,0x0a,0x7e]
+
+v_exp_f16 v5, s105
+// GFX12: encoding: [0x69,0xb0,0x0a,0x7e]
+
+v_exp_f16 v5, vcc_lo
+// GFX12: encoding: [0x6a,0xb0,0x0a,0x7e]
+
+v_exp_f16 v5, vcc_hi
+// GFX12: encoding: [0x6b,0xb0,0x0a,0x7e]
+
+v_exp_f16 v5, ttmp15
+// GFX12: encoding: [0x7b,0xb0,0x0a,0x7e]
+
+v_exp_f16 v5, m0
+// GFX12: encoding: [0x7d,0xb0,0x0a,0x7e]
+
+v_exp_f16 v5, exec_lo
+// GFX12: encoding: [0x7e,0xb0,0x0a,0x7e]
+
+v_exp_f16 v5, exec_hi
+// GFX12: encoding: [0x7f,0xb0,0x0a,0x7e]
+
+v_exp_f16 v5, null
+// GFX12: encoding: [0x7c,0xb0,0x0a,0x7e]
+
+v_exp_f16 v5, -1
+// GFX12: encoding: [0xc1,0xb0,0x0a,0x7e]
+
+v_exp_f16 v5, 0.5
+// GFX12: encoding: [0xf0,0xb0,0x0a,0x7e]
+
+v_exp_f16 v5, src_scc
+// GFX12: encoding: [0xfd,0xb0,0x0a,0x7e]
+
+v_exp_f16 v127, 0xfe0b
+// GFX12: encoding: [0xff,0xb0,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_exp_f32 v5, v1
+// GFX12: encoding: [0x01,0x4b,0x0a,0x7e]
+
+v_exp_f32 v5, v255
+// GFX12: encoding: [0xff,0x4b,0x0a,0x7e]
+
+v_exp_f32 v5, s1
+// GFX12: encoding: [0x01,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, s105
+// GFX12: encoding: [0x69,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, m0
+// GFX12: encoding: [0x7d,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, null
+// GFX12: encoding: [0x7c,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, -1
+// GFX12: encoding: [0xc1,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, 0.5
+// GFX12: encoding: [0xf0,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, src_scc
+// GFX12: encoding: [0xfd,0x4a,0x0a,0x7e]
+
+v_exp_f32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x4a,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_ffbh_i32 v5, v1
+// GFX12: encoding: [0x01,0x77,0x0a,0x7e]
+
+v_ffbh_i32 v5, v255
+// GFX12: encoding: [0xff,0x77,0x0a,0x7e]
+
+v_ffbh_i32 v5, s1
+// GFX12: encoding: [0x01,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, s105
+// GFX12: encoding: [0x69,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, m0
+// GFX12: encoding: [0x7d,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, null
+// GFX12: encoding: [0x7c,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, -1
+// GFX12: encoding: [0xc1,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, 0.5
+// GFX12: encoding: [0xf0,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, src_scc
+// GFX12: encoding: [0xfd,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x76,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_ffbh_u32 v5, v1
+// GFX12: encoding: [0x01,0x73,0x0a,0x7e]
+
+v_ffbh_u32 v5, v255
+// GFX12: encoding: [0xff,0x73,0x0a,0x7e]
+
+v_ffbh_u32 v5, s1
+// GFX12: encoding: [0x01,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, s105
+// GFX12: encoding: [0x69,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, m0
+// GFX12: encoding: [0x7d,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, null
+// GFX12: encoding: [0x7c,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, -1
+// GFX12: encoding: [0xc1,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, 0.5
+// GFX12: encoding: [0xf0,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, src_scc
+// GFX12: encoding: [0xfd,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x72,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_ffbl_b32 v5, v1
+// GFX12: encoding: [0x01,0x75,0x0a,0x7e]
+
+v_ffbl_b32 v5, v255
+// GFX12: encoding: [0xff,0x75,0x0a,0x7e]
+
+v_ffbl_b32 v5, s1
+// GFX12: encoding: [0x01,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, s105
+// GFX12: encoding: [0x69,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, m0
+// GFX12: encoding: [0x7d,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, null
+// GFX12: encoding: [0x7c,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, -1
+// GFX12: encoding: [0xc1,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, 0.5
+// GFX12: encoding: [0xf0,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, src_scc
+// GFX12: encoding: [0xfd,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x74,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_floor_f16 v5, v1
+// GFX12: encoding: [0x01,0xb7,0x0a,0x7e]
+
+v_floor_f16 v5, v127
+// GFX12: encoding: [0x7f,0xb7,0x0a,0x7e]
+
+v_floor_f16 v5, s1
+// GFX12: encoding: [0x01,0xb6,0x0a,0x7e]
+
+v_floor_f16 v5, s105
+// GFX12: encoding: [0x69,0xb6,0x0a,0x7e]
+
+v_floor_f16 v5, vcc_lo
+// GFX12: encoding: [0x6a,0xb6,0x0a,0x7e]
+
+v_floor_f16 v5, vcc_hi
+// GFX12: encoding: [0x6b,0xb6,0x0a,0x7e]
+
+v_floor_f16 v5, ttmp15
+// GFX12: encoding: [0x7b,0xb6,0x0a,0x7e]
+
+v_floor_f16 v5, m0
+// GFX12: encoding: [0x7d,0xb6,0x0a,0x7e]
+
+v_floor_f16 v5, exec_lo
+// GFX12: encoding: [0x7e,0xb6,0x0a,0x7e]
+
+v_floor_f16 v5, exec_hi
+// GFX12: encoding: [0x7f,0xb6,0x0a,0x7e]
+
+v_floor_f16 v5, null
+// GFX12: encoding: [0x7c,0xb6,0x0a,0x7e]
+
+v_floor_f16 v5, -1
+// GFX12: encoding: [0xc1,0xb6,0x0a,0x7e]
+
+v_floor_f16 v5, 0.5
+// GFX12: encoding: [0xf0,0xb6,0x0a,0x7e]
+
+v_floor_f16 v5, src_scc
+// GFX12: encoding: [0xfd,0xb6,0x0a,0x7e]
+
+v_floor_f16 v127, 0xfe0b
+// GFX12: encoding: [0xff,0xb6,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_floor_f32 v5, v1
+// GFX12: encoding: [0x01,0x49,0x0a,0x7e]
+
+v_floor_f32 v5, v255
+// GFX12: encoding: [0xff,0x49,0x0a,0x7e]
+
+v_floor_f32 v5, s1
+// GFX12: encoding: [0x01,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, s105
+// GFX12: encoding: [0x69,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, m0
+// GFX12: encoding: [0x7d,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, null
+// GFX12: encoding: [0x7c,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, -1
+// GFX12: encoding: [0xc1,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, 0.5
+// GFX12: encoding: [0xf0,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, src_scc
+// GFX12: encoding: [0xfd,0x48,0x0a,0x7e]
+
+v_floor_f32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x48,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_floor_f64 v[5:6], v[1:2]
+// GFX12: encoding: [0x01,0x35,0x0a,0x7e]
+
+v_floor_f64 v[5:6], v[254:255]
+// GFX12: encoding: [0xfe,0x35,0x0a,0x7e]
+
+v_floor_f64 v[5:6], s[2:3]
+// GFX12: encoding: [0x02,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], s[104:105]
+// GFX12: encoding: [0x68,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], vcc
+// GFX12: encoding: [0x6a,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], ttmp[14:15]
+// GFX12: encoding: [0x7a,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], exec
+// GFX12: encoding: [0x7e,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], null
+// GFX12: encoding: [0x7c,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], -1
+// GFX12: encoding: [0xc1,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], 0.5
+// GFX12: encoding: [0xf0,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], src_scc
+// GFX12: encoding: [0xfd,0x34,0x0a,0x7e]
+
+v_floor_f64 v[254:255], 0xaf123456
+// GFX12: encoding: [0xff,0x34,0xfc,0x7f,0x56,0x34,0x12,0xaf]
+
+v_fract_f16 v5, v1
+// GFX12: encoding: [0x01,0xbf,0x0a,0x7e]
+
+v_fract_f16 v5, v127
+// GFX12: encoding: [0x7f,0xbf,0x0a,0x7e]
+
+v_fract_f16 v5, s1
+// GFX12: encoding: [0x01,0xbe,0x0a,0x7e]
+
+v_fract_f16 v5, s105
+// GFX12: encoding: [0x69,0xbe,0x0a,0x7e]
+
+v_fract_f16 v5, vcc_lo
+// GFX12: encoding: [0x6a,0xbe,0x0a,0x7e]
+
+v_fract_f16 v5, vcc_hi
+// GFX12: encoding: [0x6b,0xbe,0x0a,0x7e]
+
+v_fract_f16 v5, ttmp15
+// GFX12: encoding: [0x7b,0xbe,0x0a,0x7e]
+
+v_fract_f16 v5, m0
+// GFX12: encoding: [0x7d,0xbe,0x0a,0x7e]
+
+v_fract_f16 v5, exec_lo
+// GFX12: encoding: [0x7e,0xbe,0x0a,0x7e]
+
+v_fract_f16 v5, exec_hi
+// GFX12: encoding: [0x7f,0xbe,0x0a,0x7e]
+
+v_fract_f16 v5, null
+// GFX12: encoding: [0x7c,0xbe,0x0a,0x7e]
+
+v_fract_f16 v5, -1
+// GFX12: encoding: [0xc1,0xbe,0x0a,0x7e]
+
+v_fract_f16 v5, 0.5
+// GFX12: encoding: [0xf0,0xbe,0x0a,0x7e]
+
+v_fract_f16 v5, src_scc
+// GFX12: encoding: [0xfd,0xbe,0x0a,0x7e]
+
+v_fract_f16 v127, 0xfe0b
+// GFX12: encoding: [0xff,0xbe,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_fract_f32 v5, v1
+// GFX12: encoding: [0x01,0x41,0x0a,0x7e]
+
+v_fract_f32 v5, v255
+// GFX12: encoding: [0xff,0x41,0x0a,0x7e]
+
+v_fract_f32 v5, s1
+// GFX12: encoding: [0x01,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, s105
+// GFX12: encoding: [0x69,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, m0
+// GFX12: encoding: [0x7d,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, null
+// GFX12: encoding: [0x7c,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, -1
+// GFX12: encoding: [0xc1,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, 0.5
+// GFX12: encoding: [0xf0,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, src_scc
+// GFX12: encoding: [0xfd,0x40,0x0a,0x7e]
+
+v_fract_f32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x40,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_fract_f64 v[5:6], v[1:2]
+// GFX12: encoding: [0x01,0x7d,0x0a,0x7e]
+
+v_fract_f64 v[5:6], v[254:255]
+// GFX12: encoding: [0xfe,0x7d,0x0a,0x7e]
+
+v_fract_f64 v[5:6], s[2:3]
+// GFX12: encoding: [0x02,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], s[104:105]
+// GFX12: encoding: [0x68,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], vcc
+// GFX12: encoding: [0x6a,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], ttmp[14:15]
+// GFX12: encoding: [0x7a,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], exec
+// GFX12: encoding: [0x7e,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], null
+// GFX12: encoding: [0x7c,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], -1
+// GFX12: encoding: [0xc1,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], 0.5
+// GFX12: encoding: [0xf0,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], src_scc
+// GFX12: encoding: [0xfd,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[254:255], 0xaf123456
+// GFX12: encoding: [0xff,0x7c,0xfc,0x7f,0x56,0x34,0x12,0xaf]
+
+v_frexp_exp_i16_f16 v5, v1
+// GFX12: encoding: [0x01,0xb5,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, v127
+// GFX12: encoding: [0x7f,0xb5,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, s1
+// GFX12: encoding: [0x01,0xb4,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, s105
+// GFX12: encoding: [0x69,0xb4,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, vcc_lo
+// GFX12: encoding: [0x6a,0xb4,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, vcc_hi
+// GFX12: encoding: [0x6b,0xb4,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, ttmp15
+// GFX12: encoding: [0x7b,0xb4,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, m0
+// GFX12: encoding: [0x7d,0xb4,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, exec_lo
+// GFX12: encoding: [0x7e,0xb4,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, exec_hi
+// GFX12: encoding: [0x7f,0xb4,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, null
+// GFX12: encoding: [0x7c,0xb4,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, -1
+// GFX12: encoding: [0xc1,0xb4,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, 0.5
+// GFX12: encoding: [0xf0,0xb4,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, src_scc
+// GFX12: encoding: [0xfd,0xb4,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v127, 0xfe0b
+// GFX12: encoding: [0xff,0xb4,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_frexp_exp_i32_f32 v5, v1
+// GFX12: encoding: [0x01,0x7f,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, v255
+// GFX12: encoding: [0xff,0x7f,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, s1
+// GFX12: encoding: [0x01,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, s105
+// GFX12: encoding: [0x69,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, m0
+// GFX12: encoding: [0x7d,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, null
+// GFX12: encoding: [0x7c,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, -1
+// GFX12: encoding: [0xc1,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, 0.5
+// GFX12: encoding: [0xf0,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, src_scc
+// GFX12: encoding: [0xfd,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x7e,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_frexp_exp_i32_f64 v5, v[1:2]
+// GFX12: encoding: [0x01,0x79,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, v[254:255]
+// GFX12: encoding: [0xfe,0x79,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, s[2:3]
+// GFX12: encoding: [0x02,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, s[104:105]
+// GFX12: encoding: [0x68,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, vcc
+// GFX12: encoding: [0x6a,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, ttmp[14:15]
+// GFX12: encoding: [0x7a,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, exec
+// GFX12: encoding: [0x7e,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, null
+// GFX12: encoding: [0x7c,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, -1
+// GFX12: encoding: [0xc1,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, 0.5
+// GFX12: encoding: [0xf0,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, src_scc
+// GFX12: encoding: [0xfd,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x78,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_frexp_mant_f16 v5, v1
+// GFX12: encoding: [0x01,0xb3,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, v127
+// GFX12: encoding: [0x7f,0xb3,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, s1
+// GFX12: encoding: [0x01,0xb2,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, s105
+// GFX12: encoding: [0x69,0xb2,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, vcc_lo
+// GFX12: encoding: [0x6a,0xb2,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, vcc_hi
+// GFX12: encoding: [0x6b,0xb2,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, ttmp15
+// GFX12: encoding: [0x7b,0xb2,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, m0
+// GFX12: encoding: [0x7d,0xb2,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, exec_lo
+// GFX12: encoding: [0x7e,0xb2,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, exec_hi
+// GFX12: encoding: [0x7f,0xb2,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, null
+// GFX12: encoding: [0x7c,0xb2,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, -1
+// GFX12: encoding: [0xc1,0xb2,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, 0.5
+// GFX12: encoding: [0xf0,0xb2,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, src_scc
+// GFX12: encoding: [0xfd,0xb2,0x0a,0x7e]
+
+v_frexp_mant_f16 v127, 0xfe0b
+// GFX12: encoding: [0xff,0xb2,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_frexp_mant_f32 v5, v1
+// GFX12: encoding: [0x01,0x81,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, v255
+// GFX12: encoding: [0xff,0x81,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, s1
+// GFX12: encoding: [0x01,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, s105
+// GFX12: encoding: [0x69,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, m0
+// GFX12: encoding: [0x7d,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, null
+// GFX12: encoding: [0x7c,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, -1
+// GFX12: encoding: [0xc1,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, 0.5
+// GFX12: encoding: [0xf0,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, src_scc
+// GFX12: encoding: [0xfd,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x80,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_frexp_mant_f64 v[5:6], v[1:2]
+// GFX12: encoding: [0x01,0x7b,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], v[254:255]
+// GFX12: encoding: [0xfe,0x7b,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], s[2:3]
+// GFX12: encoding: [0x02,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], s[104:105]
+// GFX12: encoding: [0x68,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], vcc
+// GFX12: encoding: [0x6a,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], ttmp[14:15]
+// GFX12: encoding: [0x7a,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], exec
+// GFX12: encoding: [0x7e,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], null
+// GFX12: encoding: [0x7c,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], -1
+// GFX12: encoding: [0xc1,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], 0.5
+// GFX12: encoding: [0xf0,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], src_scc
+// GFX12: encoding: [0xfd,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[254:255], 0xaf123456
+// GFX12: encoding: [0xff,0x7a,0xfc,0x7f,0x56,0x34,0x12,0xaf]
+
+v_log_f16 v5, v1
+// GFX12: encoding: [0x01,0xaf,0x0a,0x7e]
+
+v_log_f16 v5, v127
+// GFX12: encoding: [0x7f,0xaf,0x0a,0x7e]
+
+v_log_f16 v5, s1
+// GFX12: encoding: [0x01,0xae,0x0a,0x7e]
+
+v_log_f16 v5, s105
+// GFX12: encoding: [0x69,0xae,0x0a,0x7e]
+
+v_log_f16 v5, vcc_lo
+// GFX12: encoding: [0x6a,0xae,0x0a,0x7e]
+
+v_log_f16 v5, vcc_hi
+// GFX12: encoding: [0x6b,0xae,0x0a,0x7e]
+
+v_log_f16 v5, ttmp15
+// GFX12: encoding: [0x7b,0xae,0x0a,0x7e]
+
+v_log_f16 v5, m0
+// GFX12: encoding: [0x7d,0xae,0x0a,0x7e]
+
+v_log_f16 v5, exec_lo
+// GFX12: encoding: [0x7e,0xae,0x0a,0x7e]
+
+v_log_f16 v5, exec_hi
+// GFX12: encoding: [0x7f,0xae,0x0a,0x7e]
+
+v_log_f16 v5, null
+// GFX12: encoding: [0x7c,0xae,0x0a,0x7e]
+
+v_log_f16 v5, -1
+// GFX12: encoding: [0xc1,0xae,0x0a,0x7e]
+
+v_log_f16 v5, 0.5
+// GFX12: encoding: [0xf0,0xae,0x0a,0x7e]
+
+v_log_f16 v5, src_scc
+// GFX12: encoding: [0xfd,0xae,0x0a,0x7e]
+
+v_log_f16 v127, 0xfe0b
+// GFX12: encoding: [0xff,0xae,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_log_f32 v5, v1
+// GFX12: encoding: [0x01,0x4f,0x0a,0x7e]
+
+v_log_f32 v5, v255
+// GFX12: encoding: [0xff,0x4f,0x0a,0x7e]
+
+v_log_f32 v5, s1
+// GFX12: encoding: [0x01,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, s105
+// GFX12: encoding: [0x69,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, m0
+// GFX12: encoding: [0x7d,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, null
+// GFX12: encoding: [0x7c,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, -1
+// GFX12: encoding: [0xc1,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, 0.5
+// GFX12: encoding: [0xf0,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, src_scc
+// GFX12: encoding: [0xfd,0x4e,0x0a,0x7e]
+
+v_log_f32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x4e,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_mov_b32 v5, v1
+// GFX12: encoding: [0x01,0x03,0x0a,0x7e]
+
+v_mov_b32 v5, v255
+// GFX12: encoding: [0xff,0x03,0x0a,0x7e]
+
+v_mov_b32 v5, s1
+// GFX12: encoding: [0x01,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, s105
+// GFX12: encoding: [0x69,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, m0
+// GFX12: encoding: [0x7d,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, null
+// GFX12: encoding: [0x7c,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, -1
+// GFX12: encoding: [0xc1,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, 0.5
+// GFX12: encoding: [0xf0,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, src_scc
+// GFX12: encoding: [0xfd,0x02,0x0a,0x7e]
+
+v_mov_b32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x02,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_movreld_b32 v5, v1
+// GFX12: encoding: [0x01,0x85,0x0a,0x7e]
+
+v_movreld_b32 v5, v255
+// GFX12: encoding: [0xff,0x85,0x0a,0x7e]
+
+v_movreld_b32 v5, s1
+// GFX12: encoding: [0x01,0x84,0x0a,0x7e]
+
+v_movreld_b32 v5, s105
+// GFX12: encoding: [0x69,0x84,0x0a,0x7e]
+
+v_movreld_b32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x84,0x0a,0x7e]
+
+v_movreld_b32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x84,0x0a,0x7e]
+
+v_movreld_b32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x84,0x0a,0x7e]
+
+v_movreld_b32 v5, m0
+// GFX12: encoding: [0x7d,0x84,0x0a,0x7e]
+
+v_movreld_b32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x84,0x0a,0x7e]
+
+v_movreld_b32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x84,0x0a,0x7e]
+
+v_movreld_b32 v5, null
+// GFX12: encoding: [0x7c,0x84,0x0a,0x7e]
+
+v_movreld_b32 v5, -1
+// GFX12: encoding: [0xc1,0x84,0x0a,0x7e]
+
+v_movreld_b32 v5, 0.5
+// GFX12: encoding: [0xf0,0x84,0x0a,0x7e]
+
+v_movreld_b32 v5, src_scc
+// GFX12: encoding: [0xfd,0x84,0x0a,0x7e]
+
+v_movreld_b32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x84,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_movrels_b32 v5, v1
+// GFX12: encoding: [0x01,0x87,0x0a,0x7e]
+
+v_movrels_b32 v255, v255
+// GFX12: encoding: [0xff,0x87,0xfe,0x7f]
+
+v_movrelsd_2_b32 v5, v1
+// GFX12: encoding: [0x01,0x91,0x0a,0x7e]
+
+v_movrelsd_2_b32 v255, v255
+// GFX12: encoding: [0xff,0x91,0xfe,0x7f]
+
+v_movrelsd_b32 v5, v1
+// GFX12: encoding: [0x01,0x89,0x0a,0x7e]
+
+v_movrelsd_b32 v255, v255
+// GFX12: encoding: [0xff,0x89,0xfe,0x7f]
+
+v_nop
+// GFX12: encoding: [0x00,0x00,0x00,0x7e]
+
+v_not_b16 v5, v1
+// GFX12: encoding: [0x01,0xd3,0x0a,0x7e]
+
+v_not_b16 v5, v127
+// GFX12: encoding: [0x7f,0xd3,0x0a,0x7e]
+
+v_not_b16 v5, s1
+// GFX12: encoding: [0x01,0xd2,0x0a,0x7e]
+
+v_not_b16 v5, s105
+// GFX12: encoding: [0x69,0xd2,0x0a,0x7e]
+
+v_not_b16 v5, vcc_lo
+// GFX12: encoding: [0x6a,0xd2,0x0a,0x7e]
+
+v_not_b16 v5, vcc_hi
+// GFX12: encoding: [0x6b,0xd2,0x0a,0x7e]
+
+v_not_b16 v5, ttmp15
+// GFX12: encoding: [0x7b,0xd2,0x0a,0x7e]
+
+v_not_b16 v5, m0
+// GFX12: encoding: [0x7d,0xd2,0x0a,0x7e]
+
+v_not_b16 v5, exec_lo
+// GFX12: encoding: [0x7e,0xd2,0x0a,0x7e]
+
+v_not_b16 v5, exec_hi
+// GFX12: encoding: [0x7f,0xd2,0x0a,0x7e]
+
+v_not_b16 v5, null
+// GFX12: encoding: [0x7c,0xd2,0x0a,0x7e]
+
+v_not_b16 v5, -1
+// GFX12: encoding: [0xc1,0xd2,0x0a,0x7e]
+
+v_not_b16 v5, 0.5
+// GFX12: encoding: [0xff,0xd2,0x0a,0x7e,0x00,0x38,0x00,0x00]
+
+v_not_b16 v5, src_scc
+// GFX12: encoding: [0xfd,0xd2,0x0a,0x7e]
+
+v_not_b16 v127, 0xfe0b
+// GFX12: encoding: [0xff,0xd2,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_not_b32 v5, v1
+// GFX12: encoding: [0x01,0x6f,0x0a,0x7e]
+
+v_not_b32 v5, v255
+// GFX12: encoding: [0xff,0x6f,0x0a,0x7e]
+
+v_not_b32 v5, s1
+// GFX12: encoding: [0x01,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, s105
+// GFX12: encoding: [0x69,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, m0
+// GFX12: encoding: [0x7d,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, null
+// GFX12: encoding: [0x7c,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, -1
+// GFX12: encoding: [0xc1,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, 0.5
+// GFX12: encoding: [0xf0,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, src_scc
+// GFX12: encoding: [0xfd,0x6e,0x0a,0x7e]
+
+v_not_b32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x6e,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_permlane64_b32 v5, v1
+// GFX12: encoding: [0x01,0xcf,0x0a,0x7e]
+
+v_permlane64_b32 v255, v255
+// GFX12: encoding: [0xff,0xcf,0xfe,0x7f]
+
+v_pipeflush
+// GFX12: encoding: [0x00,0x36,0x00,0x7e]
+
+v_rcp_f16 v5, v1
+// GFX12: encoding: [0x01,0xa9,0x0a,0x7e]
+
+v_rcp_f16 v5, v127
+// GFX12: encoding: [0x7f,0xa9,0x0a,0x7e]
+
+v_rcp_f16 v5, s1
+// GFX12: encoding: [0x01,0xa8,0x0a,0x7e]
+
+v_rcp_f16 v5, s105
+// GFX12: encoding: [0x69,0xa8,0x0a,0x7e]
+
+v_rcp_f16 v5, vcc_lo
+// GFX12: encoding: [0x6a,0xa8,0x0a,0x7e]
+
+v_rcp_f16 v5, vcc_hi
+// GFX12: encoding: [0x6b,0xa8,0x0a,0x7e]
+
+v_rcp_f16 v5, ttmp15
+// GFX12: encoding: [0x7b,0xa8,0x0a,0x7e]
+
+v_rcp_f16 v5, m0
+// GFX12: encoding: [0x7d,0xa8,0x0a,0x7e]
+
+v_rcp_f16 v5, exec_lo
+// GFX12: encoding: [0x7e,0xa8,0x0a,0x7e]
+
+v_rcp_f16 v5, exec_hi
+// GFX12: encoding: [0x7f,0xa8,0x0a,0x7e]
+
+v_rcp_f16 v5, null
+// GFX12: encoding: [0x7c,0xa8,0x0a,0x7e]
+
+v_rcp_f16 v5, -1
+// GFX12: encoding: [0xc1,0xa8,0x0a,0x7e]
+
+v_rcp_f16 v5, 0.5
+// GFX12: encoding: [0xf0,0xa8,0x0a,0x7e]
+
+v_rcp_f16 v5, src_scc
+// GFX12: encoding: [0xfd,0xa8,0x0a,0x7e]
+
+v_rcp_f16 v127, 0xfe0b
+// GFX12: encoding: [0xff,0xa8,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_rcp_f32 v5, v1
+// GFX12: encoding: [0x01,0x55,0x0a,0x7e]
+
+v_rcp_f32 v5, v255
+// GFX12: encoding: [0xff,0x55,0x0a,0x7e]
+
+v_rcp_f32 v5, s1
+// GFX12: encoding: [0x01,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, s105
+// GFX12: encoding: [0x69,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, m0
+// GFX12: encoding: [0x7d,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, null
+// GFX12: encoding: [0x7c,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, -1
+// GFX12: encoding: [0xc1,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, 0.5
+// GFX12: encoding: [0xf0,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, src_scc
+// GFX12: encoding: [0xfd,0x54,0x0a,0x7e]
+
+v_rcp_f32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x54,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_rcp_f64 v[5:6], v[1:2]
+// GFX12: encoding: [0x01,0x5f,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], v[254:255]
+// GFX12: encoding: [0xfe,0x5f,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], s[2:3]
+// GFX12: encoding: [0x02,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], s[104:105]
+// GFX12: encoding: [0x68,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], vcc
+// GFX12: encoding: [0x6a,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], ttmp[14:15]
+// GFX12: encoding: [0x7a,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], exec
+// GFX12: encoding: [0x7e,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], null
+// GFX12: encoding: [0x7c,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], -1
+// GFX12: encoding: [0xc1,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], 0.5
+// GFX12: encoding: [0xf0,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], src_scc
+// GFX12: encoding: [0xfd,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[254:255], 0xaf123456
+// GFX12: encoding: [0xff,0x5e,0xfc,0x7f,0x56,0x34,0x12,0xaf]
+
+v_rcp_iflag_f32 v5, v1
+// GFX12: encoding: [0x01,0x57,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, v255
+// GFX12: encoding: [0xff,0x57,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, s1
+// GFX12: encoding: [0x01,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, s105
+// GFX12: encoding: [0x69,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, m0
+// GFX12: encoding: [0x7d,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, null
+// GFX12: encoding: [0x7c,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, -1
+// GFX12: encoding: [0xc1,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, 0.5
+// GFX12: encoding: [0xf0,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, src_scc
+// GFX12: encoding: [0xfd,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x56,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_readfirstlane_b32 s5, v1
+// GFX12: encoding: [0x01,0x05,0x0a,0x7e]
+
+v_readfirstlane_b32 s105, v1
+// GFX12: encoding: [0x01,0x05,0xd2,0x7e]
+
+v_readfirstlane_b32 vcc_lo, v1
+// GFX12: encoding: [0x01,0x05,0xd4,0x7e]
+
+v_readfirstlane_b32 vcc_hi, v1
+// GFX12: encoding: [0x01,0x05,0xd6,0x7e]
+
+v_readfirstlane_b32 ttmp15, v1
+// GFX12: encoding: [0x01,0x05,0xf6,0x7e]
+
+v_readfirstlane_b32 null, v255
+// GFX12: encoding: [0xff,0x05,0xf8,0x7e]
+
+v_rndne_f16 v5, v1
+// GFX12: encoding: [0x01,0xbd,0x0a,0x7e]
+
+v_rndne_f16 v5, v127
+// GFX12: encoding: [0x7f,0xbd,0x0a,0x7e]
+
+v_rndne_f16 v5, s1
+// GFX12: encoding: [0x01,0xbc,0x0a,0x7e]
+
+v_rndne_f16 v5, s105
+// GFX12: encoding: [0x69,0xbc,0x0a,0x7e]
+
+v_rndne_f16 v5, vcc_lo
+// GFX12: encoding: [0x6a,0xbc,0x0a,0x7e]
+
+v_rndne_f16 v5, vcc_hi
+// GFX12: encoding: [0x6b,0xbc,0x0a,0x7e]
+
+v_rndne_f16 v5, ttmp15
+// GFX12: encoding: [0x7b,0xbc,0x0a,0x7e]
+
+v_rndne_f16 v5, m0
+// GFX12: encoding: [0x7d,0xbc,0x0a,0x7e]
+
+v_rndne_f16 v5, exec_lo
+// GFX12: encoding: [0x7e,0xbc,0x0a,0x7e]
+
+v_rndne_f16 v5, exec_hi
+// GFX12: encoding: [0x7f,0xbc,0x0a,0x7e]
+
+v_rndne_f16 v5, null
+// GFX12: encoding: [0x7c,0xbc,0x0a,0x7e]
+
+v_rndne_f16 v5, -1
+// GFX12: encoding: [0xc1,0xbc,0x0a,0x7e]
+
+v_rndne_f16 v5, 0.5
+// GFX12: encoding: [0xf0,0xbc,0x0a,0x7e]
+
+v_rndne_f16 v5, src_scc
+// GFX12: encoding: [0xfd,0xbc,0x0a,0x7e]
+
+v_rndne_f16 v127, 0xfe0b
+// GFX12: encoding: [0xff,0xbc,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_rndne_f32 v5, v1
+// GFX12: encoding: [0x01,0x47,0x0a,0x7e]
+
+v_rndne_f32 v5, v255
+// GFX12: encoding: [0xff,0x47,0x0a,0x7e]
+
+v_rndne_f32 v5, s1
+// GFX12: encoding: [0x01,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, s105
+// GFX12: encoding: [0x69,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, m0
+// GFX12: encoding: [0x7d,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, null
+// GFX12: encoding: [0x7c,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, -1
+// GFX12: encoding: [0xc1,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, 0.5
+// GFX12: encoding: [0xf0,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, src_scc
+// GFX12: encoding: [0xfd,0x46,0x0a,0x7e]
+
+v_rndne_f32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x46,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_rndne_f64 v[5:6], v[1:2]
+// GFX12: encoding: [0x01,0x33,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], v[254:255]
+// GFX12: encoding: [0xfe,0x33,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], s[2:3]
+// GFX12: encoding: [0x02,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], s[104:105]
+// GFX12: encoding: [0x68,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], vcc
+// GFX12: encoding: [0x6a,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], ttmp[14:15]
+// GFX12: encoding: [0x7a,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], exec
+// GFX12: encoding: [0x7e,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], null
+// GFX12: encoding: [0x7c,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], -1
+// GFX12: encoding: [0xc1,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], 0.5
+// GFX12: encoding: [0xf0,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], src_scc
+// GFX12: encoding: [0xfd,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[254:255], 0xaf123456
+// GFX12: encoding: [0xff,0x32,0xfc,0x7f,0x56,0x34,0x12,0xaf]
+
+v_rsq_f16 v5, v1
+// GFX12: encoding: [0x01,0xad,0x0a,0x7e]
+
+v_rsq_f16 v5, v127
+// GFX12: encoding: [0x7f,0xad,0x0a,0x7e]
+
+v_rsq_f16 v5, s1
+// GFX12: encoding: [0x01,0xac,0x0a,0x7e]
+
+v_rsq_f16 v5, s105
+// GFX12: encoding: [0x69,0xac,0x0a,0x7e]
+
+v_rsq_f16 v5, vcc_lo
+// GFX12: encoding: [0x6a,0xac,0x0a,0x7e]
+
+v_rsq_f16 v5, vcc_hi
+// GFX12: encoding: [0x6b,0xac,0x0a,0x7e]
+
+v_rsq_f16 v5, ttmp15
+// GFX12: encoding: [0x7b,0xac,0x0a,0x7e]
+
+v_rsq_f16 v5, m0
+// GFX12: encoding: [0x7d,0xac,0x0a,0x7e]
+
+v_rsq_f16 v5, exec_lo
+// GFX12: encoding: [0x7e,0xac,0x0a,0x7e]
+
+v_rsq_f16 v5, exec_hi
+// GFX12: encoding: [0x7f,0xac,0x0a,0x7e]
+
+v_rsq_f16 v5, null
+// GFX12: encoding: [0x7c,0xac,0x0a,0x7e]
+
+v_rsq_f16 v5, -1
+// GFX12: encoding: [0xc1,0xac,0x0a,0x7e]
+
+v_rsq_f16 v5, 0.5
+// GFX12: encoding: [0xf0,0xac,0x0a,0x7e]
+
+v_rsq_f16 v5, src_scc
+// GFX12: encoding: [0xfd,0xac,0x0a,0x7e]
+
+v_rsq_f16 v127, 0xfe0b
+// GFX12: encoding: [0xff,0xac,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_rsq_f32 v5, v1
+// GFX12: encoding: [0x01,0x5d,0x0a,0x7e]
+
+v_rsq_f32 v5, v255
+// GFX12: encoding: [0xff,0x5d,0x0a,0x7e]
+
+v_rsq_f32 v5, s1
+// GFX12: encoding: [0x01,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, s105
+// GFX12: encoding: [0x69,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, m0
+// GFX12: encoding: [0x7d,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, null
+// GFX12: encoding: [0x7c,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, -1
+// GFX12: encoding: [0xc1,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, 0.5
+// GFX12: encoding: [0xf0,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, src_scc
+// GFX12: encoding: [0xfd,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x5c,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_rsq_f64 v[5:6], v[1:2]
+// GFX12: encoding: [0x01,0x63,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], v[254:255]
+// GFX12: encoding: [0xfe,0x63,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], s[2:3]
+// GFX12: encoding: [0x02,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], s[104:105]
+// GFX12: encoding: [0x68,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], vcc
+// GFX12: encoding: [0x6a,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], ttmp[14:15]
+// GFX12: encoding: [0x7a,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], exec
+// GFX12: encoding: [0x7e,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], null
+// GFX12: encoding: [0x7c,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], -1
+// GFX12: encoding: [0xc1,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], 0.5
+// GFX12: encoding: [0xf0,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], src_scc
+// GFX12: encoding: [0xfd,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[254:255], 0xaf123456
+// GFX12: encoding: [0xff,0x62,0xfc,0x7f,0x56,0x34,0x12,0xaf]
+
+v_sat_pk_u8_i16 v5, v1
+// GFX12: encoding: [0x01,0xc5,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, v255
+// GFX12: encoding: [0xff,0xc5,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, s1
+// GFX12: encoding: [0x01,0xc4,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, s105
+// GFX12: encoding: [0x69,0xc4,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, vcc_lo
+// GFX12: encoding: [0x6a,0xc4,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, vcc_hi
+// GFX12: encoding: [0x6b,0xc4,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, ttmp15
+// GFX12: encoding: [0x7b,0xc4,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, m0
+// GFX12: encoding: [0x7d,0xc4,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, exec_lo
+// GFX12: encoding: [0x7e,0xc4,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, exec_hi
+// GFX12: encoding: [0x7f,0xc4,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, null
+// GFX12: encoding: [0x7c,0xc4,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, -1
+// GFX12: encoding: [0xc1,0xc4,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, 0.5
+// GFX12: encoding: [0xf0,0xc4,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, src_scc
+// GFX12: encoding: [0xfd,0xc4,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v127, 0xfe0b
+// GFX12: encoding: [0xff,0xc4,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_sin_f16 v5, v1
+// GFX12: encoding: [0x01,0xc1,0x0a,0x7e]
+
+v_sin_f16 v5, v127
+// GFX12: encoding: [0x7f,0xc1,0x0a,0x7e]
+
+v_sin_f16 v5, s1
+// GFX12: encoding: [0x01,0xc0,0x0a,0x7e]
+
+v_sin_f16 v5, s105
+// GFX12: encoding: [0x69,0xc0,0x0a,0x7e]
+
+v_sin_f16 v5, vcc_lo
+// GFX12: encoding: [0x6a,0xc0,0x0a,0x7e]
+
+v_sin_f16 v5, vcc_hi
+// GFX12: encoding: [0x6b,0xc0,0x0a,0x7e]
+
+v_sin_f16 v5, ttmp15
+// GFX12: encoding: [0x7b,0xc0,0x0a,0x7e]
+
+v_sin_f16 v5, m0
+// GFX12: encoding: [0x7d,0xc0,0x0a,0x7e]
+
+v_sin_f16 v5, exec_lo
+// GFX12: encoding: [0x7e,0xc0,0x0a,0x7e]
+
+v_sin_f16 v5, exec_hi
+// GFX12: encoding: [0x7f,0xc0,0x0a,0x7e]
+
+v_sin_f16 v5, null
+// GFX12: encoding: [0x7c,0xc0,0x0a,0x7e]
+
+v_sin_f16 v5, -1
+// GFX12: encoding: [0xc1,0xc0,0x0a,0x7e]
+
+v_sin_f16 v5, 0.5
+// GFX12: encoding: [0xf0,0xc0,0x0a,0x7e]
+
+v_sin_f16 v5, src_scc
+// GFX12: encoding: [0xfd,0xc0,0x0a,0x7e]
+
+v_sin_f16 v127, 0xfe0b
+// GFX12: encoding: [0xff,0xc0,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_sin_f32 v5, v1
+// GFX12: encoding: [0x01,0x6b,0x0a,0x7e]
+
+v_sin_f32 v5, v255
+// GFX12: encoding: [0xff,0x6b,0x0a,0x7e]
+
+v_sin_f32 v5, s1
+// GFX12: encoding: [0x01,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, s105
+// GFX12: encoding: [0x69,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, m0
+// GFX12: encoding: [0x7d,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, null
+// GFX12: encoding: [0x7c,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, -1
+// GFX12: encoding: [0xc1,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, 0.5
+// GFX12: encoding: [0xf0,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, src_scc
+// GFX12: encoding: [0xfd,0x6a,0x0a,0x7e]
+
+v_sin_f32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x6a,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_sqrt_f16 v5, v1
+// GFX12: encoding: [0x01,0xab,0x0a,0x7e]
+
+v_sqrt_f16 v5, v127
+// GFX12: encoding: [0x7f,0xab,0x0a,0x7e]
+
+v_sqrt_f16 v5, s1
+// GFX12: encoding: [0x01,0xaa,0x0a,0x7e]
+
+v_sqrt_f16 v5, s105
+// GFX12: encoding: [0x69,0xaa,0x0a,0x7e]
+
+v_sqrt_f16 v5, vcc_lo
+// GFX12: encoding: [0x6a,0xaa,0x0a,0x7e]
+
+v_sqrt_f16 v5, vcc_hi
+// GFX12: encoding: [0x6b,0xaa,0x0a,0x7e]
+
+v_sqrt_f16 v5, ttmp15
+// GFX12: encoding: [0x7b,0xaa,0x0a,0x7e]
+
+v_sqrt_f16 v5, m0
+// GFX12: encoding: [0x7d,0xaa,0x0a,0x7e]
+
+v_sqrt_f16 v5, exec_lo
+// GFX12: encoding: [0x7e,0xaa,0x0a,0x7e]
+
+v_sqrt_f16 v5, exec_hi
+// GFX12: encoding: [0x7f,0xaa,0x0a,0x7e]
+
+v_sqrt_f16 v5, null
+// GFX12: encoding: [0x7c,0xaa,0x0a,0x7e]
+
+v_sqrt_f16 v5, -1
+// GFX12: encoding: [0xc1,0xaa,0x0a,0x7e]
+
+v_sqrt_f16 v5, 0.5
+// GFX12: encoding: [0xf0,0xaa,0x0a,0x7e]
+
+v_sqrt_f16 v5, src_scc
+// GFX12: encoding: [0xfd,0xaa,0x0a,0x7e]
+
+v_sqrt_f16 v127, 0xfe0b
+// GFX12: encoding: [0xff,0xaa,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_sqrt_f32 v5, v1
+// GFX12: encoding: [0x01,0x67,0x0a,0x7e]
+
+v_sqrt_f32 v5, v255
+// GFX12: encoding: [0xff,0x67,0x0a,0x7e]
+
+v_sqrt_f32 v5, s1
+// GFX12: encoding: [0x01,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, s105
+// GFX12: encoding: [0x69,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, m0
+// GFX12: encoding: [0x7d,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, null
+// GFX12: encoding: [0x7c,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, -1
+// GFX12: encoding: [0xc1,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, 0.5
+// GFX12: encoding: [0xf0,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, src_scc
+// GFX12: encoding: [0xfd,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x66,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_sqrt_f64 v[5:6], v[1:2]
+// GFX12: encoding: [0x01,0x69,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], v[254:255]
+// GFX12: encoding: [0xfe,0x69,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], s[2:3]
+// GFX12: encoding: [0x02,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], s[104:105]
+// GFX12: encoding: [0x68,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], vcc
+// GFX12: encoding: [0x6a,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], ttmp[14:15]
+// GFX12: encoding: [0x7a,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], exec
+// GFX12: encoding: [0x7e,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], null
+// GFX12: encoding: [0x7c,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], -1
+// GFX12: encoding: [0xc1,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], 0.5
+// GFX12: encoding: [0xf0,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], src_scc
+// GFX12: encoding: [0xfd,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[254:255], 0xaf123456
+// GFX12: encoding: [0xff,0x68,0xfc,0x7f,0x56,0x34,0x12,0xaf]
+
+v_swap_b32 v5, v1
+// GFX12: encoding: [0x01,0xcb,0x0a,0x7e]
+
+v_swap_b32 v255, v255
+// GFX12: encoding: [0xff,0xcb,0xfe,0x7f]
+
+v_swaprel_b32 v5, v1
+// GFX12: encoding: [0x01,0xd1,0x0a,0x7e]
+
+v_swaprel_b32 v255, v255
+// GFX12: encoding: [0xff,0xd1,0xfe,0x7f]
+
+v_trunc_f16 v5, v1
+// GFX12: encoding: [0x01,0xbb,0x0a,0x7e]
+
+v_trunc_f16 v5, v127
+// GFX12: encoding: [0x7f,0xbb,0x0a,0x7e]
+
+v_trunc_f16 v5, s1
+// GFX12: encoding: [0x01,0xba,0x0a,0x7e]
+
+v_trunc_f16 v5, s105
+// GFX12: encoding: [0x69,0xba,0x0a,0x7e]
+
+v_trunc_f16 v5, vcc_lo
+// GFX12: encoding: [0x6a,0xba,0x0a,0x7e]
+
+v_trunc_f16 v5, vcc_hi
+// GFX12: encoding: [0x6b,0xba,0x0a,0x7e]
+
+v_trunc_f16 v5, ttmp15
+// GFX12: encoding: [0x7b,0xba,0x0a,0x7e]
+
+v_trunc_f16 v5, m0
+// GFX12: encoding: [0x7d,0xba,0x0a,0x7e]
+
+v_trunc_f16 v5, exec_lo
+// GFX12: encoding: [0x7e,0xba,0x0a,0x7e]
+
+v_trunc_f16 v5, exec_hi
+// GFX12: encoding: [0x7f,0xba,0x0a,0x7e]
+
+v_trunc_f16 v5, null
+// GFX12: encoding: [0x7c,0xba,0x0a,0x7e]
+
+v_trunc_f16 v5, -1
+// GFX12: encoding: [0xc1,0xba,0x0a,0x7e]
+
+v_trunc_f16 v5, 0.5
+// GFX12: encoding: [0xf0,0xba,0x0a,0x7e]
+
+v_trunc_f16 v5, src_scc
+// GFX12: encoding: [0xfd,0xba,0x0a,0x7e]
+
+v_trunc_f16 v127, 0xfe0b
+// GFX12: encoding: [0xff,0xba,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_trunc_f32 v5, v1
+// GFX12: encoding: [0x01,0x43,0x0a,0x7e]
+
+v_trunc_f32 v5, v255
+// GFX12: encoding: [0xff,0x43,0x0a,0x7e]
+
+v_trunc_f32 v5, s1
+// GFX12: encoding: [0x01,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, s105
+// GFX12: encoding: [0x69,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, vcc_lo
+// GFX12: encoding: [0x6a,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, vcc_hi
+// GFX12: encoding: [0x6b,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, ttmp15
+// GFX12: encoding: [0x7b,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, m0
+// GFX12: encoding: [0x7d,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, exec_lo
+// GFX12: encoding: [0x7e,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, exec_hi
+// GFX12: encoding: [0x7f,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, null
+// GFX12: encoding: [0x7c,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, -1
+// GFX12: encoding: [0xc1,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, 0.5
+// GFX12: encoding: [0xf0,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, src_scc
+// GFX12: encoding: [0xfd,0x42,0x0a,0x7e]
+
+v_trunc_f32 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x42,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+
+v_trunc_f64 v[5:6], v[1:2]
+// GFX12: encoding: [0x01,0x2f,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], v[254:255]
+// GFX12: encoding: [0xfe,0x2f,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], s[2:3]
+// GFX12: encoding: [0x02,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], s[104:105]
+// GFX12: encoding: [0x68,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], vcc
+// GFX12: encoding: [0x6a,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], ttmp[14:15]
+// GFX12: encoding: [0x7a,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], exec
+// GFX12: encoding: [0x7e,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], null
+// GFX12: encoding: [0x7c,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], -1
+// GFX12: encoding: [0xc1,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], 0.5
+// GFX12: encoding: [0xf0,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], src_scc
+// GFX12: encoding: [0xfd,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[254:255], 0xaf123456
+// GFX12: encoding: [0xff,0x2e,0xfc,0x7f,0x56,0x34,0x12,0xaf]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp16.s
new file mode 100644
index 000000000000..dd6afb28c396
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp16.s
@@ -0,0 +1,2816 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_bfrev_b32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_bfrev_b32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_bfrev_b32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_bfrev_b32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_bfrev_b32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_bfrev_b32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_bfrev_b32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_bfrev_b32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_bfrev_b32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_bfrev_b32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_bfrev_b32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_bfrev_b32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_bfrev_b32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x70,0xfe,0x7f,0xff,0x6f,0x05,0x30]
+
+v_ceil_f16 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_ceil_f16 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_ceil_f16 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_ceil_f16 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_ceil_f16 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_ceil_f16 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_ceil_f16 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_ceil_f16 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_ceil_f16 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_ceil_f16 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_ceil_f16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_ceil_f16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_ceil_f16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_ceil_f16 v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xb8,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
+
+v_ceil_f32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_ceil_f32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_ceil_f32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_ceil_f32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_ceil_f32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_ceil_f32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_ceil_f32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_ceil_f32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_ceil_f32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_ceil_f32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_ceil_f32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_ceil_f32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_ceil_f32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_ceil_f32 v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x44,0xfe,0x7f,0xff,0x6f,0x35,0x30]
+
+v_cls_i32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_cls_i32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_cls_i32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_cls_i32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_cls_i32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_cls_i32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_cls_i32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_cls_i32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_cls_i32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_cls_i32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_cls_i32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_cls_i32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_cls_i32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_cls_i32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x76,0xfe,0x7f,0xff,0x6f,0x05,0x30]
+
+v_clz_i32_u32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_clz_i32_u32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_clz_i32_u32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_clz_i32_u32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_clz_i32_u32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_clz_i32_u32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_clz_i32_u32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_clz_i32_u32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_clz_i32_u32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_clz_i32_u32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_clz_i32_u32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_clz_i32_u32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_clz_i32_u32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_clz_i32_u32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x72,0xfe,0x7f,0xff,0x6f,0x05,0x30]
+
+v_cos_f16 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_cos_f16 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_cos_f16 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_cos_f16 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_cos_f16 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_cos_f16 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_cos_f16 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_cos_f16 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_cos_f16 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_cos_f16 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_cos_f16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_cos_f16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_cos_f16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_cos_f16 v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xc2,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
+
+v_cos_f32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_cos_f32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_cos_f32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_cos_f32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_cos_f32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_cos_f32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_cos_f32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_cos_f32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_cos_f32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_cos_f32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_cos_f32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_cos_f32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_cos_f32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_cos_f32 v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x6c,0xfe,0x7f,0xff,0x6f,0x35,0x30]
+
+v_ctz_i32_b32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_ctz_i32_b32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_ctz_i32_b32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_ctz_i32_b32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_ctz_i32_b32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_ctz_i32_b32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_ctz_i32_b32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_ctz_i32_b32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_ctz_i32_b32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_ctz_i32_b32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_ctz_i32_b32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_ctz_i32_b32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_ctz_i32_b32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_ctz_i32_b32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x74,0xfe,0x7f,0xff,0x6f,0x05,0x30]
+
+v_cvt_f16_f32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_cvt_f16_f32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_cvt_f16_f32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_cvt_f16_f32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_cvt_f16_f32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_cvt_f16_f32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_cvt_f16_f32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_cvt_f16_f32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_cvt_f16_f32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_cvt_f16_f32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_cvt_f16_f32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_cvt_f16_f32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_cvt_f16_f32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_cvt_f16_f32 v127, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x14,0xfe,0x7e,0xff,0x6f,0x35,0x30]
+
+v_cvt_f16_i16 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_cvt_f16_i16 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_cvt_f16_i16 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_cvt_f16_i16 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_cvt_f16_i16 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_cvt_f16_i16 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_cvt_f16_i16 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_cvt_f16_i16 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_cvt_f16_i16 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_cvt_f16_i16 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_cvt_f16_i16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_cvt_f16_i16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_cvt_f16_i16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_cvt_f16_i16 v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xa2,0xfe,0x7e,0x7f,0x6f,0x05,0x30]
+
+v_cvt_f16_u16 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_cvt_f16_u16 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_cvt_f16_u16 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_cvt_f16_u16 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_cvt_f16_u16 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_cvt_f16_u16 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_cvt_f16_u16 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_cvt_f16_u16 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_cvt_f16_u16 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_cvt_f16_u16 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_cvt_f16_u16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_cvt_f16_u16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_cvt_f16_u16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_cvt_f16_u16 v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xa0,0xfe,0x7e,0x7f,0x6f,0x05,0x30]
+
+v_cvt_f32_f16 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_cvt_f32_f16 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_cvt_f32_f16 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_cvt_f32_f16 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_cvt_f32_f16 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_cvt_f32_f16 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_cvt_f32_f16 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_cvt_f32_f16 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_cvt_f32_f16 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_cvt_f32_f16 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_cvt_f32_f16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_cvt_f32_f16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_cvt_f32_f16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_cvt_f32_f16 v255, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x16,0xfe,0x7f,0x7f,0x6f,0x35,0x30]
+
+v_cvt_f32_i32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_cvt_f32_i32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_cvt_f32_i32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_cvt_f32_i32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_cvt_f32_i32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_cvt_f32_i32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_cvt_f32_i32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_cvt_f32_i32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_cvt_f32_i32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_cvt_f32_i32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_cvt_f32_i32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_cvt_f32_i32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_cvt_f32_i32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_cvt_f32_i32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x0a,0xfe,0x7f,0xff,0x6f,0x05,0x30]
+
+v_cvt_f32_u32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_cvt_f32_u32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_cvt_f32_u32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_cvt_f32_u32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_cvt_f32_u32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_cvt_f32_u32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_cvt_f32_u32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_cvt_f32_u32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_cvt_f32_u32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_cvt_f32_u32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_cvt_f32_u32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_cvt_f32_u32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_cvt_f32_u32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_cvt_f32_u32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x0c,0xfe,0x7f,0xff,0x6f,0x05,0x30]
+
+v_cvt_f32_ubyte0 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_cvt_f32_ubyte0 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_cvt_f32_ubyte0 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_cvt_f32_ubyte0 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_cvt_f32_ubyte0 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_cvt_f32_ubyte0 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_cvt_f32_ubyte0 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_cvt_f32_ubyte0 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_cvt_f32_ubyte0 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_cvt_f32_ubyte0 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_cvt_f32_ubyte0 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_cvt_f32_ubyte0 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_cvt_f32_ubyte0 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_cvt_f32_ubyte0 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x22,0xfe,0x7f,0xff,0x6f,0x05,0x30]
+
+v_cvt_f32_ubyte1 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_cvt_f32_ubyte1 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_cvt_f32_ubyte1 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_cvt_f32_ubyte1 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_cvt_f32_ubyte1 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_cvt_f32_ubyte1 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_cvt_f32_ubyte1 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_cvt_f32_ubyte1 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_cvt_f32_ubyte1 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_cvt_f32_ubyte1 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_cvt_f32_ubyte1 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_cvt_f32_ubyte1 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_cvt_f32_ubyte1 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_cvt_f32_ubyte1 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x24,0xfe,0x7f,0xff,0x6f,0x05,0x30]
+
+v_cvt_f32_ubyte2 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_cvt_f32_ubyte2 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_cvt_f32_ubyte2 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_cvt_f32_ubyte2 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_cvt_f32_ubyte2 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_cvt_f32_ubyte2 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_cvt_f32_ubyte2 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_cvt_f32_ubyte2 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_cvt_f32_ubyte2 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_cvt_f32_ubyte2 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_cvt_f32_ubyte2 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_cvt_f32_ubyte2 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_cvt_f32_ubyte2 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_cvt_f32_ubyte2 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x26,0xfe,0x7f,0xff,0x6f,0x05,0x30]
+
+v_cvt_f32_ubyte3 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_cvt_f32_ubyte3 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_cvt_f32_ubyte3 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_cvt_f32_ubyte3 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_cvt_f32_ubyte3 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_cvt_f32_ubyte3 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_cvt_f32_ubyte3 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_cvt_f32_ubyte3 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_cvt_f32_ubyte3 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_cvt_f32_ubyte3 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_cvt_f32_ubyte3 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_cvt_f32_ubyte3 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_cvt_f32_ubyte3 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_cvt_f32_ubyte3 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x28,0xfe,0x7f,0xff,0x6f,0x05,0x30]
+
+v_cvt_floor_i32_f32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_cvt_floor_i32_f32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_cvt_floor_i32_f32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_cvt_floor_i32_f32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_cvt_floor_i32_f32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_cvt_floor_i32_f32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_cvt_floor_i32_f32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_cvt_floor_i32_f32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_cvt_floor_i32_f32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_cvt_floor_i32_f32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_cvt_floor_i32_f32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_cvt_floor_i32_f32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_cvt_floor_i32_f32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_cvt_floor_i32_f32 v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x1a,0xfe,0x7f,0xff,0x6f,0x35,0x30]
+
+v_cvt_flr_i32_f32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_cvt_flr_i32_f32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_cvt_flr_i32_f32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_cvt_flr_i32_f32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_cvt_flr_i32_f32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_cvt_flr_i32_f32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_cvt_flr_i32_f32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_cvt_flr_i32_f32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_cvt_flr_i32_f32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_cvt_flr_i32_f32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_cvt_flr_i32_f32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_cvt_flr_i32_f32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_cvt_flr_i32_f32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_cvt_flr_i32_f32 v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x1a,0xfe,0x7f,0xff,0x6f,0x35,0x30]
+
+v_cvt_i16_f16 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_cvt_i16_f16 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_cvt_i16_f16 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_cvt_i16_f16 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_cvt_i16_f16 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_cvt_i16_f16 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_cvt_i16_f16 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_cvt_i16_f16 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_cvt_i16_f16 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_cvt_i16_f16 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_cvt_i16_f16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_cvt_i16_f16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_cvt_i16_f16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_cvt_i16_f16 v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xa6,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
+
+v_cvt_i32_f32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_cvt_i32_f32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_cvt_i32_f32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_cvt_i32_f32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_cvt_i32_f32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_cvt_i32_f32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_cvt_i32_f32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_cvt_i32_f32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_cvt_i32_f32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_cvt_i32_f32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_cvt_i32_f32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_cvt_i32_f32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_cvt_i32_f32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_cvt_i32_f32 v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x10,0xfe,0x7f,0xff,0x6f,0x35,0x30]
+
+v_cvt_i32_i16 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0xd4,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_cvt_i32_i16 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0xd4,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_cvt_i32_i16 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0xd4,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_cvt_i32_i16 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0xd4,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_cvt_i32_i16 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0xd4,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_cvt_i32_i16 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0xd4,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_cvt_i32_i16 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0xd4,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_cvt_i32_i16 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0xd4,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_cvt_i32_i16 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0xd4,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_cvt_i32_i16 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0xd4,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_cvt_i32_i16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0xd4,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_cvt_i32_i16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0xd4,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_cvt_i32_i16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0xd4,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_cvt_i32_i16 v255, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xd4,0xfe,0x7f,0x7f,0x6f,0x05,0x30]
+
+v_cvt_nearest_i32_f32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_cvt_nearest_i32_f32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_cvt_nearest_i32_f32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_cvt_nearest_i32_f32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_cvt_nearest_i32_f32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_cvt_nearest_i32_f32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_cvt_nearest_i32_f32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_cvt_nearest_i32_f32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_cvt_nearest_i32_f32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_cvt_nearest_i32_f32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_cvt_nearest_i32_f32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_cvt_nearest_i32_f32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_cvt_nearest_i32_f32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_cvt_nearest_i32_f32 v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x18,0xfe,0x7f,0xff,0x6f,0x35,0x30]
+
+v_cvt_norm_i16_f16 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_cvt_norm_i16_f16 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_cvt_norm_i16_f16 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_cvt_norm_i16_f16 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_cvt_norm_i16_f16 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_cvt_norm_i16_f16 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_cvt_norm_i16_f16 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_cvt_norm_i16_f16 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_cvt_norm_i16_f16 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_cvt_norm_i16_f16 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_cvt_norm_i16_f16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_cvt_norm_i16_f16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_cvt_norm_i16_f16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_cvt_norm_i16_f16 v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xc6,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
+
+v_cvt_norm_u16_f16 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_cvt_norm_u16_f16 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_cvt_norm_u16_f16 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_cvt_norm_u16_f16 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_cvt_norm_u16_f16 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_cvt_norm_u16_f16 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_cvt_norm_u16_f16 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_cvt_norm_u16_f16 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_cvt_norm_u16_f16 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_cvt_norm_u16_f16 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_cvt_norm_u16_f16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_cvt_norm_u16_f16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_cvt_norm_u16_f16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_cvt_norm_u16_f16 v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xc8,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
+
+v_cvt_off_f32_i4 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_cvt_off_f32_i4 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_cvt_off_f32_i4 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_cvt_off_f32_i4 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_cvt_off_f32_i4 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_cvt_off_f32_i4 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_cvt_off_f32_i4 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_cvt_off_f32_i4 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_cvt_off_f32_i4 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_cvt_off_f32_i4 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_cvt_off_f32_i4 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_cvt_off_f32_i4 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_cvt_off_f32_i4 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_cvt_off_f32_i4 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x1c,0xfe,0x7f,0xff,0x6f,0x05,0x30]
+
+v_cvt_rpi_i32_f32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_cvt_rpi_i32_f32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_cvt_rpi_i32_f32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_cvt_rpi_i32_f32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_cvt_rpi_i32_f32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_cvt_rpi_i32_f32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_cvt_rpi_i32_f32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_cvt_rpi_i32_f32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_cvt_rpi_i32_f32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_cvt_rpi_i32_f32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_cvt_rpi_i32_f32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_cvt_rpi_i32_f32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_cvt_rpi_i32_f32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_cvt_rpi_i32_f32 v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x18,0xfe,0x7f,0xff,0x6f,0x35,0x30]
+
+v_cvt_u16_f16 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_cvt_u16_f16 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_cvt_u16_f16 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_cvt_u16_f16 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_cvt_u16_f16 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_cvt_u16_f16 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_cvt_u16_f16 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_cvt_u16_f16 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_cvt_u16_f16 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_cvt_u16_f16 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_cvt_u16_f16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_cvt_u16_f16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_cvt_u16_f16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_cvt_u16_f16 v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xa4,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
+
+v_cvt_u32_f32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_cvt_u32_f32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_cvt_u32_f32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_cvt_u32_f32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_cvt_u32_f32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_cvt_u32_f32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_cvt_u32_f32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_cvt_u32_f32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_cvt_u32_f32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_cvt_u32_f32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_cvt_u32_f32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_cvt_u32_f32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_cvt_u32_f32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_cvt_u32_f32 v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x0e,0xfe,0x7f,0xff,0x6f,0x35,0x30]
+
+v_cvt_u32_u16 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0xd6,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_cvt_u32_u16 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0xd6,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_cvt_u32_u16 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0xd6,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_cvt_u32_u16 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0xd6,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_cvt_u32_u16 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0xd6,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_cvt_u32_u16 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0xd6,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_cvt_u32_u16 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0xd6,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_cvt_u32_u16 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0xd6,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_cvt_u32_u16 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0xd6,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_cvt_u32_u16 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0xd6,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_cvt_u32_u16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0xd6,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_cvt_u32_u16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0xd6,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_cvt_u32_u16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0xd6,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_cvt_u32_u16 v255, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xd6,0xfe,0x7f,0x7f,0x6f,0x05,0x30]
+
+v_exp_f16 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_exp_f16 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_exp_f16 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_exp_f16 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_exp_f16 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_exp_f16 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_exp_f16 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_exp_f16 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_exp_f16 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_exp_f16 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_exp_f16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_exp_f16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_exp_f16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_exp_f16 v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xb0,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
+
+v_exp_f32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_exp_f32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_exp_f32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_exp_f32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_exp_f32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_exp_f32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_exp_f32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_exp_f32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_exp_f32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_exp_f32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_exp_f32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_exp_f32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_exp_f32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_exp_f32 v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x4a,0xfe,0x7f,0xff,0x6f,0x35,0x30]
+
+v_ffbh_i32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_ffbh_i32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_ffbh_i32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_ffbh_i32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_ffbh_i32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_ffbh_i32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_ffbh_i32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_ffbh_i32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_ffbh_i32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_ffbh_i32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_ffbh_i32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_ffbh_i32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_ffbh_i32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_ffbh_i32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x76,0xfe,0x7f,0xff,0x6f,0x05,0x30]
+
+v_ffbh_u32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_ffbh_u32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_ffbh_u32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_ffbh_u32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_ffbh_u32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_ffbh_u32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_ffbh_u32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_ffbh_u32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_ffbh_u32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_ffbh_u32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_ffbh_u32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_ffbh_u32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_ffbh_u32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_ffbh_u32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x72,0xfe,0x7f,0xff,0x6f,0x05,0x30]
+
+v_ffbl_b32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_ffbl_b32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_ffbl_b32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_ffbl_b32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_ffbl_b32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_ffbl_b32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_ffbl_b32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_ffbl_b32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_ffbl_b32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_ffbl_b32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_ffbl_b32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_ffbl_b32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_ffbl_b32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_ffbl_b32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x74,0xfe,0x7f,0xff,0x6f,0x05,0x30]
+
+v_floor_f16 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_floor_f16 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_floor_f16 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_floor_f16 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_floor_f16 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_floor_f16 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_floor_f16 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_floor_f16 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_floor_f16 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_floor_f16 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_floor_f16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_floor_f16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_floor_f16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_floor_f16 v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xb6,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
+
+v_floor_f32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_floor_f32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_floor_f32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_floor_f32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_floor_f32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_floor_f32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_floor_f32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_floor_f32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_floor_f32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_floor_f32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_floor_f32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_floor_f32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_floor_f32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_floor_f32 v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x48,0xfe,0x7f,0xff,0x6f,0x35,0x30]
+
+v_fract_f16 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_fract_f16 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_fract_f16 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_fract_f16 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_fract_f16 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_fract_f16 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_fract_f16 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_fract_f16 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_fract_f16 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_fract_f16 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_fract_f16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_fract_f16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_fract_f16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_fract_f16 v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xbe,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
+
+v_fract_f32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_fract_f32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_fract_f32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_fract_f32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_fract_f32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_fract_f32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_fract_f32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_fract_f32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_fract_f32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_fract_f32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_fract_f32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_fract_f32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_fract_f32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_fract_f32 v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x40,0xfe,0x7f,0xff,0x6f,0x35,0x30]
+
+v_frexp_exp_i16_f16 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_frexp_exp_i16_f16 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_frexp_exp_i16_f16 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_frexp_exp_i16_f16 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_frexp_exp_i16_f16 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_frexp_exp_i16_f16 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_frexp_exp_i16_f16 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_frexp_exp_i16_f16 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_frexp_exp_i16_f16 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_frexp_exp_i16_f16 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_frexp_exp_i16_f16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_frexp_exp_i16_f16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_frexp_exp_i16_f16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_frexp_exp_i16_f16 v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xb4,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
+
+v_frexp_exp_i32_f32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_frexp_exp_i32_f32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_frexp_exp_i32_f32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_frexp_exp_i32_f32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_frexp_exp_i32_f32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_frexp_exp_i32_f32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_frexp_exp_i32_f32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_frexp_exp_i32_f32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_frexp_exp_i32_f32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_frexp_exp_i32_f32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_frexp_exp_i32_f32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_frexp_exp_i32_f32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_frexp_exp_i32_f32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_frexp_exp_i32_f32 v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x7e,0xfe,0x7f,0xff,0x6f,0x35,0x30]
+
+v_frexp_mant_f16 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_frexp_mant_f16 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_frexp_mant_f16 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_frexp_mant_f16 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_frexp_mant_f16 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_frexp_mant_f16 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_frexp_mant_f16 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_frexp_mant_f16 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_frexp_mant_f16 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_frexp_mant_f16 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_frexp_mant_f16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_frexp_mant_f16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_frexp_mant_f16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_frexp_mant_f16 v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xb2,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
+
+v_frexp_mant_f32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_frexp_mant_f32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_frexp_mant_f32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_frexp_mant_f32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_frexp_mant_f32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_frexp_mant_f32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_frexp_mant_f32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_frexp_mant_f32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_frexp_mant_f32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_frexp_mant_f32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_frexp_mant_f32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_frexp_mant_f32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_frexp_mant_f32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_frexp_mant_f32 v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x80,0xfe,0x7f,0xff,0x6f,0x35,0x30]
+
+v_log_f16 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_log_f16 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_log_f16 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_log_f16 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_log_f16 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_log_f16 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_log_f16 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_log_f16 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_log_f16 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_log_f16 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_log_f16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_log_f16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_log_f16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_log_f16 v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xae,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
+
+v_log_f32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_log_f32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_log_f32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_log_f32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_log_f32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_log_f32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_log_f32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_log_f32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_log_f32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_log_f32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_log_f32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_log_f32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_log_f32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_log_f32 v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x4e,0xfe,0x7f,0xff,0x6f,0x35,0x30]
+
+v_mov_b32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_mov_b32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_mov_b32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_mov_b32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_mov_b32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_mov_b32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_mov_b32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_mov_b32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_mov_b32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_mov_b32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_mov_b32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_mov_b32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_mov_b32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_mov_b32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x02,0xfe,0x7f,0xff,0x6f,0x05,0x30]
+
+v_movreld_b32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x84,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_movreld_b32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_movreld_b32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x84,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_movreld_b32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x84,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_movreld_b32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x84,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_movreld_b32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x84,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_movreld_b32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x84,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_movreld_b32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x84,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_movreld_b32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x84,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_movreld_b32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x84,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_movreld_b32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x84,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_movreld_b32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x84,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_movreld_b32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x84,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_movreld_b32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x84,0xfe,0x7f,0xff,0x6f,0x05,0x30]
+
+v_movrels_b32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x86,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_movrels_b32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_movrels_b32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x86,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_movrels_b32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x86,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_movrels_b32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x86,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_movrels_b32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x86,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_movrels_b32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x86,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_movrels_b32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x86,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_movrels_b32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x86,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_movrels_b32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x86,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_movrels_b32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x86,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_movrels_b32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x86,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_movrels_b32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x86,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_movrels_b32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x86,0xfe,0x7f,0xff,0x6f,0x05,0x30]
+
+v_movrelsd_2_b32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x90,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_movrelsd_2_b32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_movrelsd_2_b32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x90,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_movrelsd_2_b32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x90,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_movrelsd_2_b32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x90,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_movrelsd_2_b32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x90,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_movrelsd_2_b32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x90,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_movrelsd_2_b32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x90,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_movrelsd_2_b32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x90,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_movrelsd_2_b32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x90,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_movrelsd_2_b32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x90,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_movrelsd_2_b32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x90,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_movrelsd_2_b32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x90,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_movrelsd_2_b32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x90,0xfe,0x7f,0xff,0x6f,0x05,0x30]
+
+v_movrelsd_b32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x88,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_movrelsd_b32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_movrelsd_b32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x88,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_movrelsd_b32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x88,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_movrelsd_b32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x88,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_movrelsd_b32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x88,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_movrelsd_b32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x88,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_movrelsd_b32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x88,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_movrelsd_b32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x88,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_movrelsd_b32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x88,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_movrelsd_b32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x88,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_movrelsd_b32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x88,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_movrelsd_b32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x88,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_movrelsd_b32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x88,0xfe,0x7f,0xff,0x6f,0x05,0x30]
+
+v_not_b16 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0xd2,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_not_b16 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0xd2,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_not_b16 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0xd2,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_not_b16 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0xd2,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_not_b16 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0xd2,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_not_b16 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0xd2,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_not_b16 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0xd2,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_not_b16 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0xd2,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_not_b16 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0xd2,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_not_b16 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0xd2,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_not_b16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0xd2,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_not_b16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0xd2,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_not_b16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0xd2,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_not_b16 v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xd2,0xfe,0x7e,0x7f,0x6f,0x05,0x30]
+
+v_not_b32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_not_b32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_not_b32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_not_b32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_not_b32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_not_b32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_not_b32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_not_b32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_not_b32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_not_b32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_not_b32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_not_b32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_not_b32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_not_b32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x6e,0xfe,0x7f,0xff,0x6f,0x05,0x30]
+
+v_rcp_f16 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_rcp_f16 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_rcp_f16 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_rcp_f16 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_rcp_f16 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_rcp_f16 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_rcp_f16 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_rcp_f16 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_rcp_f16 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_rcp_f16 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_rcp_f16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_rcp_f16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_rcp_f16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_rcp_f16 v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xa8,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
+
+v_rcp_f32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_rcp_f32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_rcp_f32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_rcp_f32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_rcp_f32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_rcp_f32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_rcp_f32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_rcp_f32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_rcp_f32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_rcp_f32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_rcp_f32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_rcp_f32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_rcp_f32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_rcp_f32 v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x54,0xfe,0x7f,0xff,0x6f,0x35,0x30]
+
+v_rcp_iflag_f32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_rcp_iflag_f32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_rcp_iflag_f32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_rcp_iflag_f32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_rcp_iflag_f32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_rcp_iflag_f32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_rcp_iflag_f32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_rcp_iflag_f32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_rcp_iflag_f32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_rcp_iflag_f32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_rcp_iflag_f32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_rcp_iflag_f32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_rcp_iflag_f32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_rcp_iflag_f32 v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x56,0xfe,0x7f,0xff,0x6f,0x35,0x30]
+
+v_rndne_f16 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_rndne_f16 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_rndne_f16 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_rndne_f16 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_rndne_f16 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_rndne_f16 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_rndne_f16 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_rndne_f16 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_rndne_f16 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_rndne_f16 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_rndne_f16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_rndne_f16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_rndne_f16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_rndne_f16 v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xbc,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
+
+v_rndne_f32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_rndne_f32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_rndne_f32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_rndne_f32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_rndne_f32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_rndne_f32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_rndne_f32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_rndne_f32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_rndne_f32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_rndne_f32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_rndne_f32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_rndne_f32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_rndne_f32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_rndne_f32 v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x46,0xfe,0x7f,0xff,0x6f,0x35,0x30]
+
+v_rsq_f16 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_rsq_f16 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_rsq_f16 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_rsq_f16 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_rsq_f16 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_rsq_f16 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_rsq_f16 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_rsq_f16 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_rsq_f16 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_rsq_f16 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_rsq_f16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_rsq_f16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_rsq_f16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_rsq_f16 v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xac,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
+
+v_rsq_f32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_rsq_f32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_rsq_f32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_rsq_f32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_rsq_f32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_rsq_f32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_rsq_f32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_rsq_f32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_rsq_f32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_rsq_f32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_rsq_f32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_rsq_f32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_rsq_f32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_rsq_f32 v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x5c,0xfe,0x7f,0xff,0x6f,0x35,0x30]
+
+v_sat_pk_u8_i16 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0xc4,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_sat_pk_u8_i16 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0xc4,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_sat_pk_u8_i16 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0xc4,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_sat_pk_u8_i16 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0xc4,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_sat_pk_u8_i16 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0xc4,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_sat_pk_u8_i16 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0xc4,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_sat_pk_u8_i16 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0xc4,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_sat_pk_u8_i16 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0xc4,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_sat_pk_u8_i16 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0xc4,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_sat_pk_u8_i16 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0xc4,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_sat_pk_u8_i16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0xc4,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_sat_pk_u8_i16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0xc4,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_sat_pk_u8_i16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0xc4,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_sat_pk_u8_i16 v127, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xc4,0xfe,0x7e,0xff,0x6f,0x05,0x30]
+
+v_sin_f16 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_sin_f16 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_sin_f16 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_sin_f16 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_sin_f16 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_sin_f16 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_sin_f16 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_sin_f16 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_sin_f16 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_sin_f16 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_sin_f16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_sin_f16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_sin_f16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_sin_f16 v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xc0,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
+
+v_sin_f32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_sin_f32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_sin_f32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_sin_f32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_sin_f32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_sin_f32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_sin_f32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_sin_f32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_sin_f32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_sin_f32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_sin_f32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_sin_f32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_sin_f32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_sin_f32 v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x6a,0xfe,0x7f,0xff,0x6f,0x35,0x30]
+
+v_sqrt_f16 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_sqrt_f16 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_sqrt_f16 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_sqrt_f16 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_sqrt_f16 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_sqrt_f16 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_sqrt_f16 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_sqrt_f16 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_sqrt_f16 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_sqrt_f16 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_sqrt_f16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_sqrt_f16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_sqrt_f16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_sqrt_f16 v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xaa,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
+
+v_sqrt_f32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_sqrt_f32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_sqrt_f32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_sqrt_f32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_sqrt_f32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_sqrt_f32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_sqrt_f32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_sqrt_f32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_sqrt_f32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_sqrt_f32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_sqrt_f32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_sqrt_f32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_sqrt_f32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_sqrt_f32 v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x66,0xfe,0x7f,0xff,0x6f,0x35,0x30]
+
+v_trunc_f16 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_trunc_f16 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_trunc_f16 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_trunc_f16 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_trunc_f16 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_trunc_f16 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_trunc_f16 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_trunc_f16 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_trunc_f16 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_trunc_f16 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_trunc_f16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_trunc_f16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_trunc_f16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_trunc_f16 v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xba,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
+
+v_trunc_f32 v5, v1 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+v_trunc_f32 v5, v1 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+v_trunc_f32 v5, v1 row_mirror
+// GFX12: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+v_trunc_f32 v5, v1 row_half_mirror
+// GFX12: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+v_trunc_f32 v5, v1 row_shl:1
+// GFX12: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+v_trunc_f32 v5, v1 row_shl:15
+// GFX12: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+v_trunc_f32 v5, v1 row_shr:1
+// GFX12: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+v_trunc_f32 v5, v1 row_shr:15
+// GFX12: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+v_trunc_f32 v5, v1 row_ror:1
+// GFX12: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+v_trunc_f32 v5, v1 row_ror:15
+// GFX12: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+v_trunc_f32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+v_trunc_f32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+v_trunc_f32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+v_trunc_f32 v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0x42,0xfe,0x7f,0xff,0x6f,0x35,0x30]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp8.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp8.s
new file mode 100644
index 000000000000..6530de026845
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp8.s
@@ -0,0 +1,605 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
+
+v_bfrev_b32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x70,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_bfrev_b32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x70,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_bfrev_b32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x70,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_ceil_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0xb8,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_ceil_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0xb8,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_ceil_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xb8,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+
+v_ceil_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x44,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_ceil_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x44,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_ceil_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x44,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_cls_i32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x76,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cls_i32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x76,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cls_i32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x76,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_clz_i32_u32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x72,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_clz_i32_u32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x72,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_clz_i32_u32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x72,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_cos_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0xc2,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cos_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0xc2,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cos_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xc2,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+
+v_cos_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x6c,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cos_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x6c,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cos_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x6c,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_ctz_i32_b32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x74,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_ctz_i32_b32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x74,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_ctz_i32_b32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x74,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_cvt_f16_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x14,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_f16_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x14,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_f16_f32 v127, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x14,0xfe,0x7e,0xff,0x00,0x00,0x00]
+
+v_cvt_f16_i16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0xa2,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_f16_i16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0xa2,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_f16_i16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xa2,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+
+v_cvt_f16_u16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0xa0,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_f16_u16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0xa0,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_f16_u16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xa0,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x16,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x16,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_f16 v255, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x16,0xfe,0x7f,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_i32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x0a,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_i32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x0a,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_i32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x0a,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_cvt_f32_u32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x0c,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_u32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x0c,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_u32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x0c,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x22,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_ubyte0 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x22,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_ubyte0 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x22,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x24,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_ubyte1 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x24,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_ubyte1 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x24,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x26,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_ubyte2 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x26,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_ubyte2 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x26,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x28,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_ubyte3 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x28,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_ubyte3 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x28,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_cvt_floor_i32_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x1a,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_floor_i32_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x1a,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_floor_i32_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x1a,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x1a,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_flr_i32_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x1a,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_flr_i32_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x1a,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_cvt_i16_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0xa6,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_i16_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0xa6,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_i16_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xa6,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+
+v_cvt_i32_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x10,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_i32_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x10,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_i32_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x10,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_cvt_i32_i16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0xd4,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_i32_i16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0xd4,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_i32_i16 v255, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xd4,0xfe,0x7f,0x7f,0x00,0x00,0x00]
+
+v_cvt_nearest_i32_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x18,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_nearest_i32_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x18,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_nearest_i32_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x18,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0xc6,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_norm_i16_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0xc6,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_norm_i16_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xc6,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0xc8,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_norm_u16_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0xc8,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_norm_u16_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xc8,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x1c,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_off_f32_i4 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x1c,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_off_f32_i4 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x1c,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x18,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_rpi_i32_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x18,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_rpi_i32_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x18,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_cvt_u16_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0xa4,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_u16_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0xa4,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_u16_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xa4,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+
+v_cvt_u32_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x0e,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_u32_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x0e,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_u32_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x0e,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_cvt_u32_u16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0xd6,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_u32_u16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0xd6,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_cvt_u32_u16 v255, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xd6,0xfe,0x7f,0x7f,0x00,0x00,0x00]
+
+v_exp_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0xb0,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_exp_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0xb0,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_exp_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xb0,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+
+v_exp_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x4a,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_exp_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x4a,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_exp_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x4a,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_ffbh_i32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x76,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_ffbh_i32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x76,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_ffbh_i32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x76,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_ffbh_u32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x72,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_ffbh_u32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x72,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_ffbh_u32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x72,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_ffbl_b32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x74,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_ffbl_b32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x74,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_ffbl_b32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x74,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_floor_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0xb6,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_floor_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0xb6,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_floor_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xb6,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+
+v_floor_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x48,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_floor_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x48,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_floor_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x48,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_fract_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0xbe,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_fract_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0xbe,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_fract_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xbe,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+
+v_fract_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x40,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_fract_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x40,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_fract_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x40,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0xb4,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_frexp_exp_i16_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0xb4,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_frexp_exp_i16_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xb4,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x7e,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_frexp_exp_i32_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x7e,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_frexp_exp_i32_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x7e,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_frexp_mant_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0xb2,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_frexp_mant_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0xb2,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_frexp_mant_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xb2,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+
+v_frexp_mant_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x80,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_frexp_mant_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x80,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_frexp_mant_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x80,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_log_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0xae,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_log_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0xae,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_log_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xae,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+
+v_log_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x4e,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_log_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x4e,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_log_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x4e,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_mov_b32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x02,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_mov_b32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x02,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_mov_b32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x02,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_movreld_b32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x84,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_movreld_b32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x84,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_movreld_b32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x84,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_movrels_b32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x86,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_movrels_b32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x86,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_movrels_b32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x86,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_movrelsd_2_b32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x90,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_movrelsd_2_b32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x90,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_movrelsd_2_b32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x90,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_movrelsd_b32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x88,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_movrelsd_b32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x88,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_movrelsd_b32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x88,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_not_b16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0xd2,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_not_b16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0xd2,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_not_b16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xd2,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+
+v_not_b32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x6e,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_not_b32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x6e,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_not_b32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x6e,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_rcp_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0xa8,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_rcp_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0xa8,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_rcp_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xa8,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+
+v_rcp_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x54,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_rcp_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x54,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_rcp_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x54,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_rcp_iflag_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x56,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_rcp_iflag_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x56,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_rcp_iflag_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x56,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_rndne_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0xbc,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_rndne_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0xbc,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_rndne_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xbc,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+
+v_rndne_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x46,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_rndne_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x46,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_rndne_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x46,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_rsq_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0xac,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_rsq_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0xac,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_rsq_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xac,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+
+v_rsq_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x5c,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_rsq_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x5c,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_rsq_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x5c,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0xc4,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_sat_pk_u8_i16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0xc4,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_sat_pk_u8_i16 v127, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xc4,0xfe,0x7e,0xff,0x00,0x00,0x00]
+
+v_sin_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0xc0,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_sin_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0xc0,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_sin_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xc0,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+
+v_sin_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x6a,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_sin_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x6a,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_sin_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x6a,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_sqrt_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0xaa,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_sqrt_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0xaa,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_sqrt_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xaa,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+
+v_sqrt_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x66,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_sqrt_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x66,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_sqrt_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x66,0xfe,0x7f,0xff,0x00,0x00,0x00]
+
+v_trunc_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0xba,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_trunc_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0xba,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_trunc_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xba,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+
+v_trunc_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x42,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_trunc_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x42,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+v_trunc_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0x42,0xfe,0x7f,0xff,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_err.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_err.s
new file mode 100644
index 000000000000..f34d029e02da
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_err.s
@@ -0,0 +1,505 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX12 --implicit-check-not=error %s
+
+v_ceil_f16_e32 v128, 0xfe0b
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_ceil_f16_e32 v255, v1
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_ceil_f16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cos_f16_e32 v128, 0xfe0b
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cos_f16_e32 v255, v1
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cos_f16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cvt_f16_f32_e32 v128, 0xaf123456
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cvt_f16_f32_e32 v255, v1
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cvt_f16_f32_e32 v255, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cvt_f16_i16_e32 v128, 0xfe0b
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cvt_f16_i16_e32 v255, v1
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cvt_f16_i16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cvt_f16_u16_e32 v128, 0xfe0b
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cvt_f16_u16_e32 v255, v1
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cvt_f16_u16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cvt_f32_f16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cvt_i16_f16_e32 v128, 0xfe0b
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cvt_i16_f16_e32 v255, v1
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cvt_i16_f16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cvt_i32_i16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_norm_i16_f16_e32 v128, 0xfe0b
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cvt_norm_i16_f16_e32 v255, v1
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cvt_norm_i16_f16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cvt_norm_u16_f16_e32 v128, 0xfe0b
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cvt_norm_u16_f16_e32 v255, v1
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cvt_norm_u16_f16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cvt_u16_f16_e32 v128, 0xfe0b
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cvt_u16_f16_e32 v255, v1
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cvt_u16_f16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cvt_u32_u16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_exp_f16_e32 v128, 0xfe0b
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_exp_f16_e32 v255, v1
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_exp_f16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_floor_f16_e32 v128, 0xfe0b
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_floor_f16_e32 v255, v1
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_floor_f16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_fract_f16_e32 v128, 0xfe0b
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_fract_f16_e32 v255, v1
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_fract_f16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_frexp_exp_i16_f16_e32 v128, 0xfe0b
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_frexp_exp_i16_f16_e32 v255, v1
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_frexp_exp_i16_f16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_frexp_mant_f16_e32 v128, 0xfe0b
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_frexp_mant_f16_e32 v255, v1
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_frexp_mant_f16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_log_f16_e32 v128, 0xfe0b
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_log_f16_e32 v255, v1
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_log_f16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_not_b16_e32 v128, 0xfe0b
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_not_b16_e32 v255, v1
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_not_b16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_rcp_f16_e32 v128, 0xfe0b
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_rcp_f16_e32 v255, v1
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_rcp_f16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_rndne_f16_e32 v128, 0xfe0b
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_rndne_f16_e32 v255, v1
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_rndne_f16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_rsq_f16_e32 v128, 0xfe0b
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_rsq_f16_e32 v255, v1
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_rsq_f16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sat_pk_u8_i16_e32 v199, v5
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sin_f16_e32 v128, 0xfe0b
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sin_f16_e32 v255, v1
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sin_f16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sqrt_f16_e32 v128, 0xfe0b
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sqrt_f16_e32 v255, v1
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sqrt_f16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_trunc_f16_e32 v128, 0xfe0b
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_trunc_f16_e32 v255, v1
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_trunc_f16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_ceil_f16_e32 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_ceil_f16_e32 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cos_f16_e32 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cos_f16_e32 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_f16_f32_e32 v128, 0xaf123456 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_f16_f32_e32 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_f16_f32_e32 v255, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_f16_i16_e32 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_f16_i16_e32 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_f16_u16_e32 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_f16_u16_e32 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_f32_f16_e32 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_i16_f16_e32 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_i16_f16_e32 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_i32_i16_e32 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_norm_i16_f16_e32 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_norm_i16_f16_e32 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_norm_u16_f16_e32 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_norm_u16_f16_e32 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_u16_f16_e32 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_u16_f16_e32 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_u32_u16_e32 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_exp_f16_e32 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_exp_f16_e32 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_floor_f16_e32 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_floor_f16_e32 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_fract_f16_e32 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_fract_f16_e32 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_frexp_exp_i16_f16_e32 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_frexp_exp_i16_f16_e32 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_frexp_mant_f16_e32 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_frexp_mant_f16_e32 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_log_f16_e32 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_log_f16_e32 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_not_b16_e32 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_not_b16_e32 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_rcp_f16_e32 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_rcp_f16_e32 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_rndne_f16_e32 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_rndne_f16_e32 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_rsq_f16_e32 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_rsq_f16_e32 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sat_pk_u8_i16_e32 v199, v5 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sin_f16_e32 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sin_f16_e32 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sqrt_f16_e32 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sqrt_f16_e32 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_trunc_f16_e32 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_trunc_f16_e32 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_ceil_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_ceil_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cos_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cos_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_f16_f32_e32 v128, 0xaf123456 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_f16_f32_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_f16_f32_e32 v255, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_f16_i16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_f16_i16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_f16_u16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_f16_u16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_f32_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_i16_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_i16_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_i32_i16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_norm_i16_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_norm_i16_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_norm_u16_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_norm_u16_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_u16_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_u16_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_u32_u16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_exp_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_exp_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_floor_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_floor_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_fract_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_fract_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_frexp_exp_i16_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_frexp_exp_i16_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_frexp_mant_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_frexp_mant_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_log_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_log_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_not_b16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_not_b16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_rcp_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_rcp_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_rndne_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_rndne_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_rsq_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_rsq_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sat_pk_u8_i16_e32 v199, v5 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sin_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sin_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sqrt_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sqrt_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_trunc_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_trunc_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_promote.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_promote.s
new file mode 100644
index 000000000000..dce0b0378993
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_promote.s
@@ -0,0 +1,1480 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -show-encoding %s | FileCheck --check-prefix=GFX12 --implicit-check-not=_e32 %s
+
+v_ceil_f16 v128, 0xfe0b
+// GFX12: v_ceil_f16_e64
+
+v_ceil_f16 v255, -1
+// GFX12: v_ceil_f16_e64
+
+v_ceil_f16 v255, 0.5
+// GFX12: v_ceil_f16_e64
+
+v_ceil_f16 v255, exec_hi
+// GFX12: v_ceil_f16_e64
+
+v_ceil_f16 v255, exec_lo
+// GFX12: v_ceil_f16_e64
+
+v_ceil_f16 v255, m0
+// GFX12: v_ceil_f16_e64
+
+v_ceil_f16 v255, null
+// GFX12: v_ceil_f16_e64
+
+v_ceil_f16 v255, s1
+// GFX12: v_ceil_f16_e64
+
+v_ceil_f16 v255, s105
+// GFX12: v_ceil_f16_e64
+
+v_ceil_f16 v255, src_scc
+// GFX12: v_ceil_f16_e64
+
+v_ceil_f16 v255, ttmp15
+// GFX12: v_ceil_f16_e64
+
+v_ceil_f16 v255, v1
+// GFX12: v_ceil_f16_e64
+
+v_ceil_f16 v255, v127
+// GFX12: v_ceil_f16_e64
+
+v_ceil_f16 v255, vcc_hi
+// GFX12: v_ceil_f16_e64
+
+v_ceil_f16 v255, vcc_lo
+// GFX12: v_ceil_f16_e64
+
+v_ceil_f16 v5, v199
+// GFX12: v_ceil_f16_e64
+
+v_cos_f16 v128, 0xfe0b
+// GFX12: v_cos_f16_e64
+
+v_cos_f16 v255, -1
+// GFX12: v_cos_f16_e64
+
+v_cos_f16 v255, 0.5
+// GFX12: v_cos_f16_e64
+
+v_cos_f16 v255, exec_hi
+// GFX12: v_cos_f16_e64
+
+v_cos_f16 v255, exec_lo
+// GFX12: v_cos_f16_e64
+
+v_cos_f16 v255, m0
+// GFX12: v_cos_f16_e64
+
+v_cos_f16 v255, null
+// GFX12: v_cos_f16_e64
+
+v_cos_f16 v255, s1
+// GFX12: v_cos_f16_e64
+
+v_cos_f16 v255, s105
+// GFX12: v_cos_f16_e64
+
+v_cos_f16 v255, src_scc
+// GFX12: v_cos_f16_e64
+
+v_cos_f16 v255, ttmp15
+// GFX12: v_cos_f16_e64
+
+v_cos_f16 v255, v1
+// GFX12: v_cos_f16_e64
+
+v_cos_f16 v255, v127
+// GFX12: v_cos_f16_e64
+
+v_cos_f16 v255, vcc_hi
+// GFX12: v_cos_f16_e64
+
+v_cos_f16 v255, vcc_lo
+// GFX12: v_cos_f16_e64
+
+v_cos_f16 v5, v199
+// GFX12: v_cos_f16_e64
+
+v_cvt_f16_f32 v128, 0xaf123456
+// GFX12: v_cvt_f16_f32_e64
+
+v_cvt_f16_f32 v255, -1
+// GFX12: v_cvt_f16_f32_e64
+
+v_cvt_f16_f32 v255, 0.5
+// GFX12: v_cvt_f16_f32_e64
+
+v_cvt_f16_f32 v255, exec_hi
+// GFX12: v_cvt_f16_f32_e64
+
+v_cvt_f16_f32 v255, exec_lo
+// GFX12: v_cvt_f16_f32_e64
+
+v_cvt_f16_f32 v255, m0
+// GFX12: v_cvt_f16_f32_e64
+
+v_cvt_f16_f32 v255, null
+// GFX12: v_cvt_f16_f32_e64
+
+v_cvt_f16_f32 v255, s1
+// GFX12: v_cvt_f16_f32_e64
+
+v_cvt_f16_f32 v255, s105
+// GFX12: v_cvt_f16_f32_e64
+
+v_cvt_f16_f32 v255, src_scc
+// GFX12: v_cvt_f16_f32_e64
+
+v_cvt_f16_f32 v255, ttmp15
+// GFX12: v_cvt_f16_f32_e64
+
+v_cvt_f16_f32 v255, v1
+// GFX12: v_cvt_f16_f32_e64
+
+v_cvt_f16_f32 v255, v255
+// GFX12: v_cvt_f16_f32_e64
+
+v_cvt_f16_f32 v255, vcc_hi
+// GFX12: v_cvt_f16_f32_e64
+
+v_cvt_f16_f32 v255, vcc_lo
+// GFX12: v_cvt_f16_f32_e64
+
+v_cvt_f16_i16 v128, 0xfe0b
+// GFX12: v_cvt_f16_i16_e64
+
+v_cvt_f16_i16 v255, -1
+// GFX12: v_cvt_f16_i16_e64
+
+v_cvt_f16_i16 v255, 0.5
+// GFX12: v_cvt_f16_i16_e64
+
+v_cvt_f16_i16 v255, exec_hi
+// GFX12: v_cvt_f16_i16_e64
+
+v_cvt_f16_i16 v255, exec_lo
+// GFX12: v_cvt_f16_i16_e64
+
+v_cvt_f16_i16 v255, m0
+// GFX12: v_cvt_f16_i16_e64
+
+v_cvt_f16_i16 v255, null
+// GFX12: v_cvt_f16_i16_e64
+
+v_cvt_f16_i16 v255, s1
+// GFX12: v_cvt_f16_i16_e64
+
+v_cvt_f16_i16 v255, s105
+// GFX12: v_cvt_f16_i16_e64
+
+v_cvt_f16_i16 v255, src_scc
+// GFX12: v_cvt_f16_i16_e64
+
+v_cvt_f16_i16 v255, ttmp15
+// GFX12: v_cvt_f16_i16_e64
+
+v_cvt_f16_i16 v255, v1
+// GFX12: v_cvt_f16_i16_e64
+
+v_cvt_f16_i16 v255, v127
+// GFX12: v_cvt_f16_i16_e64
+
+v_cvt_f16_i16 v255, vcc_hi
+// GFX12: v_cvt_f16_i16_e64
+
+v_cvt_f16_i16 v255, vcc_lo
+// GFX12: v_cvt_f16_i16_e64
+
+v_cvt_f16_i16 v5, v199
+// GFX12: v_cvt_f16_i16_e64
+
+v_cvt_f16_u16 v128, 0xfe0b
+// GFX12: v_cvt_f16_u16_e64
+
+v_cvt_f16_u16 v255, -1
+// GFX12: v_cvt_f16_u16_e64
+
+v_cvt_f16_u16 v255, 0.5
+// GFX12: v_cvt_f16_u16_e64
+
+v_cvt_f16_u16 v255, exec_hi
+// GFX12: v_cvt_f16_u16_e64
+
+v_cvt_f16_u16 v255, exec_lo
+// GFX12: v_cvt_f16_u16_e64
+
+v_cvt_f16_u16 v255, m0
+// GFX12: v_cvt_f16_u16_e64
+
+v_cvt_f16_u16 v255, null
+// GFX12: v_cvt_f16_u16_e64
+
+v_cvt_f16_u16 v255, s1
+// GFX12: v_cvt_f16_u16_e64
+
+v_cvt_f16_u16 v255, s105
+// GFX12: v_cvt_f16_u16_e64
+
+v_cvt_f16_u16 v255, src_scc
+// GFX12: v_cvt_f16_u16_e64
+
+v_cvt_f16_u16 v255, ttmp15
+// GFX12: v_cvt_f16_u16_e64
+
+v_cvt_f16_u16 v255, v1
+// GFX12: v_cvt_f16_u16_e64
+
+v_cvt_f16_u16 v255, v127
+// GFX12: v_cvt_f16_u16_e64
+
+v_cvt_f16_u16 v255, vcc_hi
+// GFX12: v_cvt_f16_u16_e64
+
+v_cvt_f16_u16 v255, vcc_lo
+// GFX12: v_cvt_f16_u16_e64
+
+v_cvt_f16_u16 v5, v199
+// GFX12: v_cvt_f16_u16_e64
+
+v_cvt_f32_f16 v5, v199
+// GFX12: v_cvt_f32_f16_e64
+
+v_cvt_i16_f16 v128, 0xfe0b
+// GFX12: v_cvt_i16_f16_e64
+
+v_cvt_i16_f16 v255, -1
+// GFX12: v_cvt_i16_f16_e64
+
+v_cvt_i16_f16 v255, 0.5
+// GFX12: v_cvt_i16_f16_e64
+
+v_cvt_i16_f16 v255, exec_hi
+// GFX12: v_cvt_i16_f16_e64
+
+v_cvt_i16_f16 v255, exec_lo
+// GFX12: v_cvt_i16_f16_e64
+
+v_cvt_i16_f16 v255, m0
+// GFX12: v_cvt_i16_f16_e64
+
+v_cvt_i16_f16 v255, null
+// GFX12: v_cvt_i16_f16_e64
+
+v_cvt_i16_f16 v255, s1
+// GFX12: v_cvt_i16_f16_e64
+
+v_cvt_i16_f16 v255, s105
+// GFX12: v_cvt_i16_f16_e64
+
+v_cvt_i16_f16 v255, src_scc
+// GFX12: v_cvt_i16_f16_e64
+
+v_cvt_i16_f16 v255, ttmp15
+// GFX12: v_cvt_i16_f16_e64
+
+v_cvt_i16_f16 v255, v1
+// GFX12: v_cvt_i16_f16_e64
+
+v_cvt_i16_f16 v255, v127
+// GFX12: v_cvt_i16_f16_e64
+
+v_cvt_i16_f16 v255, vcc_hi
+// GFX12: v_cvt_i16_f16_e64
+
+v_cvt_i16_f16 v255, vcc_lo
+// GFX12: v_cvt_i16_f16_e64
+
+v_cvt_i16_f16 v5, v199
+// GFX12: v_cvt_i16_f16_e64
+
+v_cvt_i32_i16 v5, v199
+// GFX12: v_cvt_i32_i16_e64
+
+v_cvt_norm_i16_f16 v128, 0xfe0b
+// GFX12: v_cvt_norm_i16_f16_e64
+
+v_cvt_norm_i16_f16 v255, -1
+// GFX12: v_cvt_norm_i16_f16_e64
+
+v_cvt_norm_i16_f16 v255, 0.5
+// GFX12: v_cvt_norm_i16_f16_e64
+
+v_cvt_norm_i16_f16 v255, exec_hi
+// GFX12: v_cvt_norm_i16_f16_e64
+
+v_cvt_norm_i16_f16 v255, exec_lo
+// GFX12: v_cvt_norm_i16_f16_e64
+
+v_cvt_norm_i16_f16 v255, m0
+// GFX12: v_cvt_norm_i16_f16_e64
+
+v_cvt_norm_i16_f16 v255, null
+// GFX12: v_cvt_norm_i16_f16_e64
+
+v_cvt_norm_i16_f16 v255, s1
+// GFX12: v_cvt_norm_i16_f16_e64
+
+v_cvt_norm_i16_f16 v255, s105
+// GFX12: v_cvt_norm_i16_f16_e64
+
+v_cvt_norm_i16_f16 v255, src_scc
+// GFX12: v_cvt_norm_i16_f16_e64
+
+v_cvt_norm_i16_f16 v255, ttmp15
+// GFX12: v_cvt_norm_i16_f16_e64
+
+v_cvt_norm_i16_f16 v255, v1
+// GFX12: v_cvt_norm_i16_f16_e64
+
+v_cvt_norm_i16_f16 v255, v127
+// GFX12: v_cvt_norm_i16_f16_e64
+
+v_cvt_norm_i16_f16 v255, vcc_hi
+// GFX12: v_cvt_norm_i16_f16_e64
+
+v_cvt_norm_i16_f16 v255, vcc_lo
+// GFX12: v_cvt_norm_i16_f16_e64
+
+v_cvt_norm_i16_f16 v5, v199
+// GFX12: v_cvt_norm_i16_f16_e64
+
+v_cvt_norm_u16_f16 v128, 0xfe0b
+// GFX12: v_cvt_norm_u16_f16_e64
+
+v_cvt_norm_u16_f16 v255, -1
+// GFX12: v_cvt_norm_u16_f16_e64
+
+v_cvt_norm_u16_f16 v255, 0.5
+// GFX12: v_cvt_norm_u16_f16_e64
+
+v_cvt_norm_u16_f16 v255, exec_hi
+// GFX12: v_cvt_norm_u16_f16_e64
+
+v_cvt_norm_u16_f16 v255, exec_lo
+// GFX12: v_cvt_norm_u16_f16_e64
+
+v_cvt_norm_u16_f16 v255, m0
+// GFX12: v_cvt_norm_u16_f16_e64
+
+v_cvt_norm_u16_f16 v255, null
+// GFX12: v_cvt_norm_u16_f16_e64
+
+v_cvt_norm_u16_f16 v255, s1
+// GFX12: v_cvt_norm_u16_f16_e64
+
+v_cvt_norm_u16_f16 v255, s105
+// GFX12: v_cvt_norm_u16_f16_e64
+
+v_cvt_norm_u16_f16 v255, src_scc
+// GFX12: v_cvt_norm_u16_f16_e64
+
+v_cvt_norm_u16_f16 v255, ttmp15
+// GFX12: v_cvt_norm_u16_f16_e64
+
+v_cvt_norm_u16_f16 v255, v1
+// GFX12: v_cvt_norm_u16_f16_e64
+
+v_cvt_norm_u16_f16 v255, v127
+// GFX12: v_cvt_norm_u16_f16_e64
+
+v_cvt_norm_u16_f16 v255, vcc_hi
+// GFX12: v_cvt_norm_u16_f16_e64
+
+v_cvt_norm_u16_f16 v255, vcc_lo
+// GFX12: v_cvt_norm_u16_f16_e64
+
+v_cvt_norm_u16_f16 v5, v199
+// GFX12: v_cvt_norm_u16_f16_e64
+
+v_cvt_u16_f16 v128, 0xfe0b
+// GFX12: v_cvt_u16_f16_e64
+
+v_cvt_u16_f16 v255, -1
+// GFX12: v_cvt_u16_f16_e64
+
+v_cvt_u16_f16 v255, 0.5
+// GFX12: v_cvt_u16_f16_e64
+
+v_cvt_u16_f16 v255, exec_hi
+// GFX12: v_cvt_u16_f16_e64
+
+v_cvt_u16_f16 v255, exec_lo
+// GFX12: v_cvt_u16_f16_e64
+
+v_cvt_u16_f16 v255, m0
+// GFX12: v_cvt_u16_f16_e64
+
+v_cvt_u16_f16 v255, null
+// GFX12: v_cvt_u16_f16_e64
+
+v_cvt_u16_f16 v255, s1
+// GFX12: v_cvt_u16_f16_e64
+
+v_cvt_u16_f16 v255, s105
+// GFX12: v_cvt_u16_f16_e64
+
+v_cvt_u16_f16 v255, src_scc
+// GFX12: v_cvt_u16_f16_e64
+
+v_cvt_u16_f16 v255, ttmp15
+// GFX12: v_cvt_u16_f16_e64
+
+v_cvt_u16_f16 v255, v1
+// GFX12: v_cvt_u16_f16_e64
+
+v_cvt_u16_f16 v255, v127
+// GFX12: v_cvt_u16_f16_e64
+
+v_cvt_u16_f16 v255, vcc_hi
+// GFX12: v_cvt_u16_f16_e64
+
+v_cvt_u16_f16 v255, vcc_lo
+// GFX12: v_cvt_u16_f16_e64
+
+v_cvt_u16_f16 v5, v199
+// GFX12: v_cvt_u16_f16_e64
+
+v_cvt_u32_u16 v5, v199
+// GFX12: v_cvt_u32_u16_e64
+
+v_exp_f16 v128, 0xfe0b
+// GFX12: v_exp_f16_e64
+
+v_exp_f16 v255, -1
+// GFX12: v_exp_f16_e64
+
+v_exp_f16 v255, 0.5
+// GFX12: v_exp_f16_e64
+
+v_exp_f16 v255, exec_hi
+// GFX12: v_exp_f16_e64
+
+v_exp_f16 v255, exec_lo
+// GFX12: v_exp_f16_e64
+
+v_exp_f16 v255, m0
+// GFX12: v_exp_f16_e64
+
+v_exp_f16 v255, null
+// GFX12: v_exp_f16_e64
+
+v_exp_f16 v255, s1
+// GFX12: v_exp_f16_e64
+
+v_exp_f16 v255, s105
+// GFX12: v_exp_f16_e64
+
+v_exp_f16 v255, src_scc
+// GFX12: v_exp_f16_e64
+
+v_exp_f16 v255, ttmp15
+// GFX12: v_exp_f16_e64
+
+v_exp_f16 v255, v1
+// GFX12: v_exp_f16_e64
+
+v_exp_f16 v255, v127
+// GFX12: v_exp_f16_e64
+
+v_exp_f16 v255, vcc_hi
+// GFX12: v_exp_f16_e64
+
+v_exp_f16 v255, vcc_lo
+// GFX12: v_exp_f16_e64
+
+v_exp_f16 v5, v199
+// GFX12: v_exp_f16_e64
+
+v_floor_f16 v128, 0xfe0b
+// GFX12: v_floor_f16_e64
+
+v_floor_f16 v255, -1
+// GFX12: v_floor_f16_e64
+
+v_floor_f16 v255, 0.5
+// GFX12: v_floor_f16_e64
+
+v_floor_f16 v255, exec_hi
+// GFX12: v_floor_f16_e64
+
+v_floor_f16 v255, exec_lo
+// GFX12: v_floor_f16_e64
+
+v_floor_f16 v255, m0
+// GFX12: v_floor_f16_e64
+
+v_floor_f16 v255, null
+// GFX12: v_floor_f16_e64
+
+v_floor_f16 v255, s1
+// GFX12: v_floor_f16_e64
+
+v_floor_f16 v255, s105
+// GFX12: v_floor_f16_e64
+
+v_floor_f16 v255, src_scc
+// GFX12: v_floor_f16_e64
+
+v_floor_f16 v255, ttmp15
+// GFX12: v_floor_f16_e64
+
+v_floor_f16 v255, v1
+// GFX12: v_floor_f16_e64
+
+v_floor_f16 v255, v127
+// GFX12: v_floor_f16_e64
+
+v_floor_f16 v255, vcc_hi
+// GFX12: v_floor_f16_e64
+
+v_floor_f16 v255, vcc_lo
+// GFX12: v_floor_f16_e64
+
+v_floor_f16 v5, v199
+// GFX12: v_floor_f16_e64
+
+v_fract_f16 v128, 0xfe0b
+// GFX12: v_fract_f16_e64
+
+v_fract_f16 v255, -1
+// GFX12: v_fract_f16_e64
+
+v_fract_f16 v255, 0.5
+// GFX12: v_fract_f16_e64
+
+v_fract_f16 v255, exec_hi
+// GFX12: v_fract_f16_e64
+
+v_fract_f16 v255, exec_lo
+// GFX12: v_fract_f16_e64
+
+v_fract_f16 v255, m0
+// GFX12: v_fract_f16_e64
+
+v_fract_f16 v255, null
+// GFX12: v_fract_f16_e64
+
+v_fract_f16 v255, s1
+// GFX12: v_fract_f16_e64
+
+v_fract_f16 v255, s105
+// GFX12: v_fract_f16_e64
+
+v_fract_f16 v255, src_scc
+// GFX12: v_fract_f16_e64
+
+v_fract_f16 v255, ttmp15
+// GFX12: v_fract_f16_e64
+
+v_fract_f16 v255, v1
+// GFX12: v_fract_f16_e64
+
+v_fract_f16 v255, v127
+// GFX12: v_fract_f16_e64
+
+v_fract_f16 v255, vcc_hi
+// GFX12: v_fract_f16_e64
+
+v_fract_f16 v255, vcc_lo
+// GFX12: v_fract_f16_e64
+
+v_fract_f16 v5, v199
+// GFX12: v_fract_f16_e64
+
+v_frexp_exp_i16_f16 v128, 0xfe0b
+// GFX12: v_frexp_exp_i16_f16_e64
+
+v_frexp_exp_i16_f16 v255, -1
+// GFX12: v_frexp_exp_i16_f16_e64
+
+v_frexp_exp_i16_f16 v255, 0.5
+// GFX12: v_frexp_exp_i16_f16_e64
+
+v_frexp_exp_i16_f16 v255, exec_hi
+// GFX12: v_frexp_exp_i16_f16_e64
+
+v_frexp_exp_i16_f16 v255, exec_lo
+// GFX12: v_frexp_exp_i16_f16_e64
+
+v_frexp_exp_i16_f16 v255, m0
+// GFX12: v_frexp_exp_i16_f16_e64
+
+v_frexp_exp_i16_f16 v255, null
+// GFX12: v_frexp_exp_i16_f16_e64
+
+v_frexp_exp_i16_f16 v255, s1
+// GFX12: v_frexp_exp_i16_f16_e64
+
+v_frexp_exp_i16_f16 v255, s105
+// GFX12: v_frexp_exp_i16_f16_e64
+
+v_frexp_exp_i16_f16 v255, src_scc
+// GFX12: v_frexp_exp_i16_f16_e64
+
+v_frexp_exp_i16_f16 v255, ttmp15
+// GFX12: v_frexp_exp_i16_f16_e64
+
+v_frexp_exp_i16_f16 v255, v1
+// GFX12: v_frexp_exp_i16_f16_e64
+
+v_frexp_exp_i16_f16 v255, v127
+// GFX12: v_frexp_exp_i16_f16_e64
+
+v_frexp_exp_i16_f16 v255, vcc_hi
+// GFX12: v_frexp_exp_i16_f16_e64
+
+v_frexp_exp_i16_f16 v255, vcc_lo
+// GFX12: v_frexp_exp_i16_f16_e64
+
+v_frexp_exp_i16_f16 v5, v199
+// GFX12: v_frexp_exp_i16_f16_e64
+
+v_frexp_mant_f16 v128, 0xfe0b
+// GFX12: v_frexp_mant_f16_e64
+
+v_frexp_mant_f16 v255, -1
+// GFX12: v_frexp_mant_f16_e64
+
+v_frexp_mant_f16 v255, 0.5
+// GFX12: v_frexp_mant_f16_e64
+
+v_frexp_mant_f16 v255, exec_hi
+// GFX12: v_frexp_mant_f16_e64
+
+v_frexp_mant_f16 v255, exec_lo
+// GFX12: v_frexp_mant_f16_e64
+
+v_frexp_mant_f16 v255, m0
+// GFX12: v_frexp_mant_f16_e64
+
+v_frexp_mant_f16 v255, null
+// GFX12: v_frexp_mant_f16_e64
+
+v_frexp_mant_f16 v255, s1
+// GFX12: v_frexp_mant_f16_e64
+
+v_frexp_mant_f16 v255, s105
+// GFX12: v_frexp_mant_f16_e64
+
+v_frexp_mant_f16 v255, src_scc
+// GFX12: v_frexp_mant_f16_e64
+
+v_frexp_mant_f16 v255, ttmp15
+// GFX12: v_frexp_mant_f16_e64
+
+v_frexp_mant_f16 v255, v1
+// GFX12: v_frexp_mant_f16_e64
+
+v_frexp_mant_f16 v255, v127
+// GFX12: v_frexp_mant_f16_e64
+
+v_frexp_mant_f16 v255, vcc_hi
+// GFX12: v_frexp_mant_f16_e64
+
+v_frexp_mant_f16 v255, vcc_lo
+// GFX12: v_frexp_mant_f16_e64
+
+v_frexp_mant_f16 v5, v199
+// GFX12: v_frexp_mant_f16_e64
+
+v_log_f16 v128, 0xfe0b
+// GFX12: v_log_f16_e64
+
+v_log_f16 v255, -1
+// GFX12: v_log_f16_e64
+
+v_log_f16 v255, 0.5
+// GFX12: v_log_f16_e64
+
+v_log_f16 v255, exec_hi
+// GFX12: v_log_f16_e64
+
+v_log_f16 v255, exec_lo
+// GFX12: v_log_f16_e64
+
+v_log_f16 v255, m0
+// GFX12: v_log_f16_e64
+
+v_log_f16 v255, null
+// GFX12: v_log_f16_e64
+
+v_log_f16 v255, s1
+// GFX12: v_log_f16_e64
+
+v_log_f16 v255, s105
+// GFX12: v_log_f16_e64
+
+v_log_f16 v255, src_scc
+// GFX12: v_log_f16_e64
+
+v_log_f16 v255, ttmp15
+// GFX12: v_log_f16_e64
+
+v_log_f16 v255, v1
+// GFX12: v_log_f16_e64
+
+v_log_f16 v255, v127
+// GFX12: v_log_f16_e64
+
+v_log_f16 v255, vcc_hi
+// GFX12: v_log_f16_e64
+
+v_log_f16 v255, vcc_lo
+// GFX12: v_log_f16_e64
+
+v_log_f16 v5, v199
+// GFX12: v_log_f16_e64
+
+v_not_b16 v128, 0xfe0b
+// GFX12: v_not_b16_e64
+
+v_not_b16 v255, -1
+// GFX12: v_not_b16_e64
+
+v_not_b16 v255, 0.5
+// GFX12: v_not_b16_e64
+
+v_not_b16 v255, exec_hi
+// GFX12: v_not_b16_e64
+
+v_not_b16 v255, exec_lo
+// GFX12: v_not_b16_e64
+
+v_not_b16 v255, m0
+// GFX12: v_not_b16_e64
+
+v_not_b16 v255, null
+// GFX12: v_not_b16_e64
+
+v_not_b16 v255, s1
+// GFX12: v_not_b16_e64
+
+v_not_b16 v255, s105
+// GFX12: v_not_b16_e64
+
+v_not_b16 v255, src_scc
+// GFX12: v_not_b16_e64
+
+v_not_b16 v255, ttmp15
+// GFX12: v_not_b16_e64
+
+v_not_b16 v255, v1
+// GFX12: v_not_b16_e64
+
+v_not_b16 v255, v127
+// GFX12: v_not_b16_e64
+
+v_not_b16 v255, vcc_hi
+// GFX12: v_not_b16_e64
+
+v_not_b16 v255, vcc_lo
+// GFX12: v_not_b16_e64
+
+v_not_b16 v5, v199
+// GFX12: v_not_b16_e64
+
+v_rcp_f16 v128, 0xfe0b
+// GFX12: v_rcp_f16_e64
+
+v_rcp_f16 v255, -1
+// GFX12: v_rcp_f16_e64
+
+v_rcp_f16 v255, 0.5
+// GFX12: v_rcp_f16_e64
+
+v_rcp_f16 v255, exec_hi
+// GFX12: v_rcp_f16_e64
+
+v_rcp_f16 v255, exec_lo
+// GFX12: v_rcp_f16_e64
+
+v_rcp_f16 v255, m0
+// GFX12: v_rcp_f16_e64
+
+v_rcp_f16 v255, null
+// GFX12: v_rcp_f16_e64
+
+v_rcp_f16 v255, s1
+// GFX12: v_rcp_f16_e64
+
+v_rcp_f16 v255, s105
+// GFX12: v_rcp_f16_e64
+
+v_rcp_f16 v255, src_scc
+// GFX12: v_rcp_f16_e64
+
+v_rcp_f16 v255, ttmp15
+// GFX12: v_rcp_f16_e64
+
+v_rcp_f16 v255, v1
+// GFX12: v_rcp_f16_e64
+
+v_rcp_f16 v255, v127
+// GFX12: v_rcp_f16_e64
+
+v_rcp_f16 v255, vcc_hi
+// GFX12: v_rcp_f16_e64
+
+v_rcp_f16 v255, vcc_lo
+// GFX12: v_rcp_f16_e64
+
+v_rcp_f16 v5, v199
+// GFX12: v_rcp_f16_e64
+
+v_rndne_f16 v128, 0xfe0b
+// GFX12: v_rndne_f16_e64
+
+v_rndne_f16 v255, -1
+// GFX12: v_rndne_f16_e64
+
+v_rndne_f16 v255, 0.5
+// GFX12: v_rndne_f16_e64
+
+v_rndne_f16 v255, exec_hi
+// GFX12: v_rndne_f16_e64
+
+v_rndne_f16 v255, exec_lo
+// GFX12: v_rndne_f16_e64
+
+v_rndne_f16 v255, m0
+// GFX12: v_rndne_f16_e64
+
+v_rndne_f16 v255, null
+// GFX12: v_rndne_f16_e64
+
+v_rndne_f16 v255, s1
+// GFX12: v_rndne_f16_e64
+
+v_rndne_f16 v255, s105
+// GFX12: v_rndne_f16_e64
+
+v_rndne_f16 v255, src_scc
+// GFX12: v_rndne_f16_e64
+
+v_rndne_f16 v255, ttmp15
+// GFX12: v_rndne_f16_e64
+
+v_rndne_f16 v255, v1
+// GFX12: v_rndne_f16_e64
+
+v_rndne_f16 v255, v127
+// GFX12: v_rndne_f16_e64
+
+v_rndne_f16 v255, vcc_hi
+// GFX12: v_rndne_f16_e64
+
+v_rndne_f16 v255, vcc_lo
+// GFX12: v_rndne_f16_e64
+
+v_rndne_f16 v5, v199
+// GFX12: v_rndne_f16_e64
+
+v_rsq_f16 v128, 0xfe0b
+// GFX12: v_rsq_f16_e64
+
+v_rsq_f16 v255, -1
+// GFX12: v_rsq_f16_e64
+
+v_rsq_f16 v255, 0.5
+// GFX12: v_rsq_f16_e64
+
+v_rsq_f16 v255, exec_hi
+// GFX12: v_rsq_f16_e64
+
+v_rsq_f16 v255, exec_lo
+// GFX12: v_rsq_f16_e64
+
+v_rsq_f16 v255, m0
+// GFX12: v_rsq_f16_e64
+
+v_rsq_f16 v255, null
+// GFX12: v_rsq_f16_e64
+
+v_rsq_f16 v255, s1
+// GFX12: v_rsq_f16_e64
+
+v_rsq_f16 v255, s105
+// GFX12: v_rsq_f16_e64
+
+v_rsq_f16 v255, src_scc
+// GFX12: v_rsq_f16_e64
+
+v_rsq_f16 v255, ttmp15
+// GFX12: v_rsq_f16_e64
+
+v_rsq_f16 v255, v1
+// GFX12: v_rsq_f16_e64
+
+v_rsq_f16 v255, v127
+// GFX12: v_rsq_f16_e64
+
+v_rsq_f16 v255, vcc_hi
+// GFX12: v_rsq_f16_e64
+
+v_rsq_f16 v255, vcc_lo
+// GFX12: v_rsq_f16_e64
+
+v_rsq_f16 v5, v199
+// GFX12: v_rsq_f16_e64
+
+v_sat_pk_u8_i16 v199, v5
+// GFX12: v_sat_pk_u8_i16_e64
+
+v_sin_f16 v128, 0xfe0b
+// GFX12: v_sin_f16_e64
+
+v_sin_f16 v255, -1
+// GFX12: v_sin_f16_e64
+
+v_sin_f16 v255, 0.5
+// GFX12: v_sin_f16_e64
+
+v_sin_f16 v255, exec_hi
+// GFX12: v_sin_f16_e64
+
+v_sin_f16 v255, exec_lo
+// GFX12: v_sin_f16_e64
+
+v_sin_f16 v255, m0
+// GFX12: v_sin_f16_e64
+
+v_sin_f16 v255, null
+// GFX12: v_sin_f16_e64
+
+v_sin_f16 v255, s1
+// GFX12: v_sin_f16_e64
+
+v_sin_f16 v255, s105
+// GFX12: v_sin_f16_e64
+
+v_sin_f16 v255, src_scc
+// GFX12: v_sin_f16_e64
+
+v_sin_f16 v255, ttmp15
+// GFX12: v_sin_f16_e64
+
+v_sin_f16 v255, v1
+// GFX12: v_sin_f16_e64
+
+v_sin_f16 v255, v127
+// GFX12: v_sin_f16_e64
+
+v_sin_f16 v255, vcc_hi
+// GFX12: v_sin_f16_e64
+
+v_sin_f16 v255, vcc_lo
+// GFX12: v_sin_f16_e64
+
+v_sin_f16 v5, v199
+// GFX12: v_sin_f16_e64
+
+v_sqrt_f16 v128, 0xfe0b
+// GFX12: v_sqrt_f16_e64
+
+v_sqrt_f16 v255, -1
+// GFX12: v_sqrt_f16_e64
+
+v_sqrt_f16 v255, 0.5
+// GFX12: v_sqrt_f16_e64
+
+v_sqrt_f16 v255, exec_hi
+// GFX12: v_sqrt_f16_e64
+
+v_sqrt_f16 v255, exec_lo
+// GFX12: v_sqrt_f16_e64
+
+v_sqrt_f16 v255, m0
+// GFX12: v_sqrt_f16_e64
+
+v_sqrt_f16 v255, null
+// GFX12: v_sqrt_f16_e64
+
+v_sqrt_f16 v255, s1
+// GFX12: v_sqrt_f16_e64
+
+v_sqrt_f16 v255, s105
+// GFX12: v_sqrt_f16_e64
+
+v_sqrt_f16 v255, src_scc
+// GFX12: v_sqrt_f16_e64
+
+v_sqrt_f16 v255, ttmp15
+// GFX12: v_sqrt_f16_e64
+
+v_sqrt_f16 v255, v1
+// GFX12: v_sqrt_f16_e64
+
+v_sqrt_f16 v255, v127
+// GFX12: v_sqrt_f16_e64
+
+v_sqrt_f16 v255, vcc_hi
+// GFX12: v_sqrt_f16_e64
+
+v_sqrt_f16 v255, vcc_lo
+// GFX12: v_sqrt_f16_e64
+
+v_sqrt_f16 v5, v199
+// GFX12: v_sqrt_f16_e64
+
+v_trunc_f16 v128, 0xfe0b
+// GFX12: v_trunc_f16_e64
+
+v_trunc_f16 v255, -1
+// GFX12: v_trunc_f16_e64
+
+v_trunc_f16 v255, 0.5
+// GFX12: v_trunc_f16_e64
+
+v_trunc_f16 v255, exec_hi
+// GFX12: v_trunc_f16_e64
+
+v_trunc_f16 v255, exec_lo
+// GFX12: v_trunc_f16_e64
+
+v_trunc_f16 v255, m0
+// GFX12: v_trunc_f16_e64
+
+v_trunc_f16 v255, null
+// GFX12: v_trunc_f16_e64
+
+v_trunc_f16 v255, s1
+// GFX12: v_trunc_f16_e64
+
+v_trunc_f16 v255, s105
+// GFX12: v_trunc_f16_e64
+
+v_trunc_f16 v255, src_scc
+// GFX12: v_trunc_f16_e64
+
+v_trunc_f16 v255, ttmp15
+// GFX12: v_trunc_f16_e64
+
+v_trunc_f16 v255, v1
+// GFX12: v_trunc_f16_e64
+
+v_trunc_f16 v255, v127
+// GFX12: v_trunc_f16_e64
+
+v_trunc_f16 v255, vcc_hi
+// GFX12: v_trunc_f16_e64
+
+v_trunc_f16 v255, vcc_lo
+// GFX12: v_trunc_f16_e64
+
+v_trunc_f16 v5, v199
+// GFX12: v_trunc_f16_e64
+
+v_ceil_f16 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: v_ceil_f16_e64
+
+v_ceil_f16 v255, v127 quad_perm:[3,2,1,0]
+// GFX12: v_ceil_f16_e64
+
+v_ceil_f16 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: v_ceil_f16_e64
+
+v_cos_f16 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: v_cos_f16_e64
+
+v_cos_f16 v255, v127 quad_perm:[3,2,1,0]
+// GFX12: v_cos_f16_e64
+
+v_cos_f16 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: v_cos_f16_e64
+
+v_cvt_f16_f32 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: v_cvt_f16_f32_e64
+
+v_cvt_f16_f32 v255, v255 quad_perm:[3,2,1,0]
+// GFX12: v_cvt_f16_f32_e64
+
+v_cvt_f16_i16 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: v_cvt_f16_i16_e64
+
+v_cvt_f16_i16 v255, v127 quad_perm:[3,2,1,0]
+// GFX12: v_cvt_f16_i16_e64
+
+v_cvt_f16_i16 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: v_cvt_f16_i16_e64
+
+v_cvt_f16_u16 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: v_cvt_f16_u16_e64
+
+v_cvt_f16_u16 v255, v127 quad_perm:[3,2,1,0]
+// GFX12: v_cvt_f16_u16_e64
+
+v_cvt_f16_u16 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: v_cvt_f16_u16_e64
+
+v_cvt_f32_f16 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: v_cvt_f32_f16_e64
+
+v_cvt_i16_f16 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: v_cvt_i16_f16_e64
+
+v_cvt_i16_f16 v255, v127 quad_perm:[3,2,1,0]
+// GFX12: v_cvt_i16_f16_e64
+
+v_cvt_i16_f16 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: v_cvt_i16_f16_e64
+
+v_cvt_i32_i16 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: v_cvt_i32_i16_e64
+
+v_cvt_norm_i16_f16 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: v_cvt_norm_i16_f16_e64
+
+v_cvt_norm_i16_f16 v255, v127 quad_perm:[3,2,1,0]
+// GFX12: v_cvt_norm_i16_f16_e64
+
+v_cvt_norm_i16_f16 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: v_cvt_norm_i16_f16_e64
+
+v_cvt_norm_u16_f16 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: v_cvt_norm_u16_f16_e64
+
+v_cvt_norm_u16_f16 v255, v127 quad_perm:[3,2,1,0]
+// GFX12: v_cvt_norm_u16_f16_e64
+
+v_cvt_norm_u16_f16 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: v_cvt_norm_u16_f16_e64
+
+v_cvt_u16_f16 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: v_cvt_u16_f16_e64
+
+v_cvt_u16_f16 v255, v127 quad_perm:[3,2,1,0]
+// GFX12: v_cvt_u16_f16_e64
+
+v_cvt_u16_f16 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: v_cvt_u16_f16_e64
+
+v_cvt_u32_u16 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: v_cvt_u32_u16_e64
+
+v_exp_f16 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: v_exp_f16_e64
+
+v_exp_f16 v255, v127 quad_perm:[3,2,1,0]
+// GFX12: v_exp_f16_e64
+
+v_exp_f16 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: v_exp_f16_e64
+
+v_floor_f16 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: v_floor_f16_e64
+
+v_floor_f16 v255, v127 quad_perm:[3,2,1,0]
+// GFX12: v_floor_f16_e64
+
+v_floor_f16 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: v_floor_f16_e64
+
+v_fract_f16 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: v_fract_f16_e64
+
+v_fract_f16 v255, v127 quad_perm:[3,2,1,0]
+// GFX12: v_fract_f16_e64
+
+v_fract_f16 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: v_fract_f16_e64
+
+v_frexp_exp_i16_f16 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: v_frexp_exp_i16_f16_e64
+
+v_frexp_exp_i16_f16 v255, v127 quad_perm:[3,2,1,0]
+// GFX12: v_frexp_exp_i16_f16_e64
+
+v_frexp_exp_i16_f16 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: v_frexp_exp_i16_f16_e64
+
+v_frexp_mant_f16 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: v_frexp_mant_f16_e64
+
+v_frexp_mant_f16 v255, v127 quad_perm:[3,2,1,0]
+// GFX12: v_frexp_mant_f16_e64
+
+v_frexp_mant_f16 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: v_frexp_mant_f16_e64
+
+v_log_f16 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: v_log_f16_e64
+
+v_log_f16 v255, v127 quad_perm:[3,2,1,0]
+// GFX12: v_log_f16_e64
+
+v_log_f16 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: v_log_f16_e64
+
+v_not_b16 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: v_not_b16_e64
+
+v_not_b16 v255, v127 quad_perm:[3,2,1,0]
+// GFX12: v_not_b16_e64
+
+v_not_b16 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: v_not_b16_e64
+
+v_rcp_f16 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: v_rcp_f16_e64
+
+v_rcp_f16 v255, v127 quad_perm:[3,2,1,0]
+// GFX12: v_rcp_f16_e64
+
+v_rcp_f16 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: v_rcp_f16_e64
+
+v_rndne_f16 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: v_rndne_f16_e64
+
+v_rndne_f16 v255, v127 quad_perm:[3,2,1,0]
+// GFX12: v_rndne_f16_e64
+
+v_rndne_f16 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: v_rndne_f16_e64
+
+v_rsq_f16 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: v_rsq_f16_e64
+
+v_rsq_f16 v255, v127 quad_perm:[3,2,1,0]
+// GFX12: v_rsq_f16_e64
+
+v_rsq_f16 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: v_rsq_f16_e64
+
+v_sat_pk_u8_i16 v199, v5 quad_perm:[3,2,1,0]
+// GFX12: v_sat_pk_u8_i16_e64
+
+v_sin_f16 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: v_sin_f16_e64
+
+v_sin_f16 v255, v127 quad_perm:[3,2,1,0]
+// GFX12: v_sin_f16_e64
+
+v_sin_f16 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: v_sin_f16_e64
+
+v_sqrt_f16 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: v_sqrt_f16_e64
+
+v_sqrt_f16 v255, v127 quad_perm:[3,2,1,0]
+// GFX12: v_sqrt_f16_e64
+
+v_sqrt_f16 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: v_sqrt_f16_e64
+
+v_trunc_f16 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: v_trunc_f16_e64
+
+v_trunc_f16 v255, v127 quad_perm:[3,2,1,0]
+// GFX12: v_trunc_f16_e64
+
+v_trunc_f16 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: v_trunc_f16_e64
+
+v_ceil_f16 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_ceil_f16_e64
+
+v_ceil_f16 v255, v127 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_ceil_f16_e64
+
+v_ceil_f16 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_ceil_f16_e64
+
+v_cos_f16 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cos_f16_e64
+
+v_cos_f16 v255, v127 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cos_f16_e64
+
+v_cos_f16 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cos_f16_e64
+
+v_cvt_f16_f32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cvt_f16_f32_e64
+
+v_cvt_f16_f32 v255, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cvt_f16_f32_e64
+
+v_cvt_f16_i16 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cvt_f16_i16_e64
+
+v_cvt_f16_i16 v255, v127 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cvt_f16_i16_e64
+
+v_cvt_f16_i16 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cvt_f16_i16_e64
+
+v_cvt_f16_u16 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cvt_f16_u16_e64
+
+v_cvt_f16_u16 v255, v127 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cvt_f16_u16_e64
+
+v_cvt_f16_u16 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cvt_f16_u16_e64
+
+v_cvt_f32_f16 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cvt_f32_f16_e64
+
+v_cvt_i16_f16 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cvt_i16_f16_e64
+
+v_cvt_i16_f16 v255, v127 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cvt_i16_f16_e64
+
+v_cvt_i16_f16 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cvt_i16_f16_e64
+
+v_cvt_i32_i16 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cvt_i32_i16_e64
+
+v_cvt_norm_i16_f16 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cvt_norm_i16_f16_e64
+
+v_cvt_norm_i16_f16 v255, v127 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cvt_norm_i16_f16_e64
+
+v_cvt_norm_i16_f16 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cvt_norm_i16_f16_e64
+
+v_cvt_norm_u16_f16 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cvt_norm_u16_f16_e64
+
+v_cvt_norm_u16_f16 v255, v127 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cvt_norm_u16_f16_e64
+
+v_cvt_norm_u16_f16 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cvt_norm_u16_f16_e64
+
+v_cvt_u16_f16 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cvt_u16_f16_e64
+
+v_cvt_u16_f16 v255, v127 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cvt_u16_f16_e64
+
+v_cvt_u16_f16 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cvt_u16_f16_e64
+
+v_cvt_u32_u16 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cvt_u32_u16_e64
+
+v_exp_f16 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_exp_f16_e64
+
+v_exp_f16 v255, v127 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_exp_f16_e64
+
+v_exp_f16 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_exp_f16_e64
+
+v_floor_f16 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_floor_f16_e64
+
+v_floor_f16 v255, v127 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_floor_f16_e64
+
+v_floor_f16 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_floor_f16_e64
+
+v_fract_f16 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_fract_f16_e64
+
+v_fract_f16 v255, v127 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_fract_f16_e64
+
+v_fract_f16 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_fract_f16_e64
+
+v_frexp_exp_i16_f16 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_frexp_exp_i16_f16_e64
+
+v_frexp_exp_i16_f16 v255, v127 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_frexp_exp_i16_f16_e64
+
+v_frexp_exp_i16_f16 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_frexp_exp_i16_f16_e64
+
+v_frexp_mant_f16 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_frexp_mant_f16_e64
+
+v_frexp_mant_f16 v255, v127 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_frexp_mant_f16_e64
+
+v_frexp_mant_f16 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_frexp_mant_f16_e64
+
+v_log_f16 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_log_f16_e64
+
+v_log_f16 v255, v127 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_log_f16_e64
+
+v_log_f16 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_log_f16_e64
+
+v_not_b16 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_not_b16_e64
+
+v_not_b16 v255, v127 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_not_b16_e64
+
+v_not_b16 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_not_b16_e64
+
+v_rcp_f16 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_rcp_f16_e64
+
+v_rcp_f16 v255, v127 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_rcp_f16_e64
+
+v_rcp_f16 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_rcp_f16_e64
+
+v_rndne_f16 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_rndne_f16_e64
+
+v_rndne_f16 v255, v127 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_rndne_f16_e64
+
+v_rndne_f16 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_rndne_f16_e64
+
+v_rsq_f16 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_rsq_f16_e64
+
+v_rsq_f16 v255, v127 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_rsq_f16_e64
+
+v_rsq_f16 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_rsq_f16_e64
+
+v_sat_pk_u8_i16 v199, v5 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_sat_pk_u8_i16_e64
+
+v_sin_f16 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_sin_f16_e64
+
+v_sin_f16 v255, v127 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_sin_f16_e64
+
+v_sin_f16 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_sin_f16_e64
+
+v_sqrt_f16 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_sqrt_f16_e64
+
+v_sqrt_f16 v255, v127 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_sqrt_f16_e64
+
+v_sqrt_f16 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_sqrt_f16_e64
+
+v_trunc_f16 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_trunc_f16_e64
+
+v_trunc_f16 v255, v127 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_trunc_f16_e64
+
+v_trunc_f16 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_trunc_f16_e64
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop2.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop2.s
new file mode 100644
index 000000000000..2cf98c9e6106
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop2.s
@@ -0,0 +1,2560 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W32 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W64 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+
+v_add_co_ci_u32_e32 v5, vcc_lo, v1, v2, vcc_lo
+// W32: encoding: [0x01,0x05,0x0a,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc_lo, v255, v2, vcc_lo
+// W32: encoding: [0xff,0x05,0x0a,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc_lo, s1, v2, vcc_lo
+// W32: encoding: [0x01,0x04,0x0a,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc_lo, s105, v2, vcc_lo
+// W32: encoding: [0x69,0x04,0x0a,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc_lo, vcc_lo, v2, vcc_lo
+// W32: encoding: [0x6a,0x04,0x0a,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc_lo, vcc_hi, v2, vcc_lo
+// W32: encoding: [0x6b,0x04,0x0a,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc_lo, ttmp15, v2, vcc_lo
+// W32: encoding: [0x7b,0x04,0x0a,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc_lo, m0, v2, vcc_lo
+// W32: encoding: [0x7d,0x04,0x0a,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc_lo, exec_lo, v2, vcc_lo
+// W32: encoding: [0x7e,0x04,0x0a,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc_lo, exec_hi, v2, vcc_lo
+// W32: encoding: [0x7f,0x04,0x0a,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc_lo, null, v2, vcc_lo
+// W32: encoding: [0x7c,0x04,0x0a,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc_lo, -1, v2, vcc_lo
+// W32: encoding: [0xc1,0x04,0x0a,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc_lo, 0.5, v2, vcc_lo
+// W32: encoding: [0xf0,0x04,0x0a,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc_lo, src_scc, v2, vcc_lo
+// W32: encoding: [0xfd,0x04,0x0a,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v255, vcc_lo, 0xaf123456, v255, vcc_lo
+// W32: encoding: [0xff,0xfe,0xff,0x41,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, v1, v2, vcc
+// W64: encoding: [0x01,0x05,0x0a,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, v255, v2, vcc
+// W64: encoding: [0xff,0x05,0x0a,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, s1, v2, vcc
+// W64: encoding: [0x01,0x04,0x0a,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, s105, v2, vcc
+// W64: encoding: [0x69,0x04,0x0a,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, vcc_lo, v2, vcc
+// W64: encoding: [0x6a,0x04,0x0a,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, vcc_hi, v2, vcc
+// W64: encoding: [0x6b,0x04,0x0a,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, ttmp15, v2, vcc
+// W64: encoding: [0x7b,0x04,0x0a,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, m0, v2, vcc
+// W64: encoding: [0x7d,0x04,0x0a,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, exec_lo, v2, vcc
+// W64: encoding: [0x7e,0x04,0x0a,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, exec_hi, v2, vcc
+// W64: encoding: [0x7f,0x04,0x0a,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, null, v2, vcc
+// W64: encoding: [0x7c,0x04,0x0a,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, -1, v2, vcc
+// W64: encoding: [0xc1,0x04,0x0a,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, 0.5, v2, vcc
+// W64: encoding: [0xf0,0x04,0x0a,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, src_scc, v2, vcc
+// W64: encoding: [0xfd,0x04,0x0a,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v255, vcc, 0xaf123456, v255, vcc
+// W64: encoding: [0xff,0xfe,0xff,0x41,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_f16 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x64]
+
+v_add_f16 v5, v127, v2
+// GFX12: encoding: [0x7f,0x05,0x0a,0x64]
+
+v_add_f16 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x64]
+
+v_add_f16 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x64]
+
+v_add_f16 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x64]
+
+v_add_f16 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x64]
+
+v_add_f16 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x64]
+
+v_add_f16 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x64]
+
+v_add_f16 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x64]
+
+v_add_f16 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x64]
+
+v_add_f16 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x64]
+
+v_add_f16 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x64]
+
+v_add_f16 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x64]
+
+v_add_f16 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x64]
+
+v_add_f16 v127, 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0xfe,0x64,0x0b,0xfe,0x00,0x00]
+
+v_add_f32 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x06]
+
+v_add_f32 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x06]
+
+v_add_f32 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x06]
+
+v_add_f32 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x06]
+
+v_add_f32 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x06]
+
+v_add_f32 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x06]
+
+v_add_f32 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x06]
+
+v_add_f32 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x06]
+
+v_add_f32 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x06]
+
+v_add_f32 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x06]
+
+v_add_f32 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x06]
+
+v_add_f32 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x06]
+
+v_add_f32 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x06]
+
+v_add_f32 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x06]
+
+v_add_f32 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x07,0x56,0x34,0x12,0xaf]
+
+v_add_f64 v[5:6], v[1:2], v[3:4]
+// GFX12: encoding: [0x01,0x07,0x0a,0x04]
+
+v_add_f64 v[5:6], v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0x0a,0x04]
+
+v_add_f64 v[5:6], s[0:1], v[2:3]
+// GFX12: encoding: [0x00,0x04,0x0a,0x04]
+
+v_add_f64 v[5:6], s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0x0a,0x04]
+
+v_add_f64 v[5:6], vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0x0a,0x04]
+
+v_add_f64 v[5:6], ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0x0a,0x04]
+
+v_add_f64 v[5:6], exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0x0a,0x04]
+
+v_add_f64 v[5:6], null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0x0a,0x04]
+
+v_add_f64 v[5:6], -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0x0a,0x04]
+
+v_add_f64 v[5:6], 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0x0a,0x04]
+
+v_add_f64 v[5:6], src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0x0a,0x04]
+
+v_add_f64 v[254:255], 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0xfd,0x05,0x56,0x34,0x12,0xaf]
+
+v_add_nc_u32 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x4a]
+
+v_add_nc_u32 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x4a]
+
+v_add_nc_u32 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x4a]
+
+v_add_nc_u32 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x4a]
+
+v_add_nc_u32 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x4a]
+
+v_add_nc_u32 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x4a]
+
+v_add_nc_u32 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x4a]
+
+v_add_nc_u32 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x4a]
+
+v_add_nc_u32 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x4a]
+
+v_add_nc_u32 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x4a]
+
+v_add_nc_u32 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x4a]
+
+v_add_nc_u32 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x4a]
+
+v_add_nc_u32 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x4a]
+
+v_add_nc_u32 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x4a]
+
+v_add_nc_u32 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x4b,0x56,0x34,0x12,0xaf]
+
+v_and_b32 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x36]
+
+v_and_b32 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x36]
+
+v_and_b32 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x36]
+
+v_and_b32 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x36]
+
+v_and_b32 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x36]
+
+v_and_b32 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x36]
+
+v_and_b32 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x36]
+
+v_and_b32 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x36]
+
+v_and_b32 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x36]
+
+v_and_b32 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x36]
+
+v_and_b32 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x36]
+
+v_and_b32 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x36]
+
+v_and_b32 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x36]
+
+v_and_b32 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x36]
+
+v_and_b32 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x37,0x56,0x34,0x12,0xaf]
+
+v_ashrrev_i32 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x34]
+
+v_ashrrev_i32 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x34]
+
+v_ashrrev_i32 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x34]
+
+v_ashrrev_i32 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x34]
+
+v_ashrrev_i32 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x34]
+
+v_ashrrev_i32 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x34]
+
+v_ashrrev_i32 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x34]
+
+v_ashrrev_i32 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x34]
+
+v_ashrrev_i32 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x34]
+
+v_ashrrev_i32 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x34]
+
+v_ashrrev_i32 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x34]
+
+v_ashrrev_i32 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x34]
+
+v_ashrrev_i32 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x34]
+
+v_ashrrev_i32 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x34]
+
+v_ashrrev_i32 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x35,0x56,0x34,0x12,0xaf]
+
+v_cndmask_b32 v5, v1, v2, vcc_lo
+// W32: encoding: [0x01,0x05,0x0a,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v255, v2, vcc_lo
+// W32: encoding: [0xff,0x05,0x0a,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, s1, v2, vcc_lo
+// W32: encoding: [0x01,0x04,0x0a,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, s105, v2, vcc_lo
+// W32: encoding: [0x69,0x04,0x0a,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, vcc_lo, v2, vcc_lo
+// W32: encoding: [0x6a,0x04,0x0a,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, vcc_hi, v2, vcc_lo
+// W32: encoding: [0x6b,0x04,0x0a,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, ttmp15, v2, vcc_lo
+// W32: encoding: [0x7b,0x04,0x0a,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, m0, v2, vcc_lo
+// W32: encoding: [0x7d,0x04,0x0a,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, exec_lo, v2, vcc_lo
+// W32: encoding: [0x7e,0x04,0x0a,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, exec_hi, v2, vcc_lo
+// W32: encoding: [0x7f,0x04,0x0a,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, null, v2, vcc_lo
+// W32: encoding: [0x7c,0x04,0x0a,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, -1, v2, vcc_lo
+// W32: encoding: [0xc1,0x04,0x0a,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, 0.5, v2, vcc_lo
+// W32: encoding: [0xf0,0x04,0x0a,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, src_scc, v2, vcc_lo
+// W32: encoding: [0xfd,0x04,0x0a,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v255, 0xaf123456, v255, vcc_lo
+// W32: encoding: [0xff,0xfe,0xff,0x03,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc
+// W64: encoding: [0x01,0x05,0x0a,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v255, v2, vcc
+// W64: encoding: [0xff,0x05,0x0a,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, s1, v2, vcc
+// W64: encoding: [0x01,0x04,0x0a,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, s105, v2, vcc
+// W64: encoding: [0x69,0x04,0x0a,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, vcc_lo, v2, vcc
+// W64: encoding: [0x6a,0x04,0x0a,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, vcc_hi, v2, vcc
+// W64: encoding: [0x6b,0x04,0x0a,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, ttmp15, v2, vcc
+// W64: encoding: [0x7b,0x04,0x0a,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, m0, v2, vcc
+// W64: encoding: [0x7d,0x04,0x0a,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, exec_lo, v2, vcc
+// W64: encoding: [0x7e,0x04,0x0a,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, exec_hi, v2, vcc
+// W64: encoding: [0x7f,0x04,0x0a,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, null, v2, vcc
+// W64: encoding: [0x7c,0x04,0x0a,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, -1, v2, vcc
+// W64: encoding: [0xc1,0x04,0x0a,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, 0.5, v2, vcc
+// W64: encoding: [0xf0,0x04,0x0a,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, src_scc, v2, vcc
+// W64: encoding: [0xfd,0x04,0x0a,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v255, 0xaf123456, v255, vcc
+// W64: encoding: [0xff,0xfe,0xff,0x03,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cvt_pk_rtz_f16_f32 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x5e]
+
+v_cvt_pk_rtz_f16_f32 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x5e]
+
+v_cvt_pk_rtz_f16_f32 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x5e]
+
+v_cvt_pk_rtz_f16_f32 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x5e]
+
+v_cvt_pk_rtz_f16_f32 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x5e]
+
+v_cvt_pk_rtz_f16_f32 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x5e]
+
+v_cvt_pk_rtz_f16_f32 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x5e]
+
+v_cvt_pk_rtz_f16_f32 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x5e]
+
+v_cvt_pk_rtz_f16_f32 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x5e]
+
+v_cvt_pk_rtz_f16_f32 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x5e]
+
+v_cvt_pk_rtz_f16_f32 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x5e]
+
+v_cvt_pk_rtz_f16_f32 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x5e]
+
+v_cvt_pk_rtz_f16_f32 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x5e]
+
+v_cvt_pk_rtz_f16_f32 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x5e]
+
+v_cvt_pk_rtz_f16_f32 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x5f,0x56,0x34,0x12,0xaf]
+
+v_cvt_pkrtz_f16_f32 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x5f,0x56,0x34,0x12,0xaf]
+
+v_fmaak_f16 v5, v1, v2, 0xfe0b
+// GFX12: encoding: [0x01,0x05,0x0a,0x70,0x0b,0xfe,0x00,0x00]
+
+v_fmaak_f16 v5, v127, v2, 0xfe0b
+// GFX12: encoding: [0x7f,0x05,0x0a,0x70,0x0b,0xfe,0x00,0x00]
+
+v_fmaak_f16 v5, s1, v2, 0xfe0b
+// GFX12: encoding: [0x01,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00]
+
+v_fmaak_f16 v5, s105, v2, 0xfe0b
+// GFX12: encoding: [0x69,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00]
+
+v_fmaak_f16 v5, vcc_lo, v2, 0xfe0b
+// GFX12: encoding: [0x6a,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00]
+
+v_fmaak_f16 v5, vcc_hi, v2, 0xfe0b
+// GFX12: encoding: [0x6b,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00]
+
+v_fmaak_f16 v5, ttmp15, v2, 0xfe0b
+// GFX12: encoding: [0x7b,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00]
+
+v_fmaak_f16 v5, m0, v2, 0xfe0b
+// GFX12: encoding: [0x7d,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00]
+
+v_fmaak_f16 v5, exec_lo, v2, 0xfe0b
+// GFX12: encoding: [0x7e,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00]
+
+v_fmaak_f16 v5, exec_hi, v2, 0xfe0b
+// GFX12: encoding: [0x7f,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00]
+
+v_fmaak_f16 v5, null, v2, 0xfe0b
+// GFX12: encoding: [0x7c,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00]
+
+v_fmaak_f16 v5, -1, v2, 0xfe0b
+// GFX12: encoding: [0xc1,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00]
+
+v_fmaak_f16 v5, 0.5, v2, 0xfe0b
+// GFX12: encoding: [0xf0,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00]
+
+v_fmaak_f16 v5, src_scc, v2, 0xfe0b
+// GFX12: encoding: [0xfd,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00]
+
+v_fmaak_f16 v127, 0xfe0b, v127, 0xfe0b
+// GFX12: encoding: [0xff,0xfe,0xfe,0x70,0x0b,0xfe,0x00,0x00]
+
+v_fmaak_f32 v5, v1, v2, 0xaf123456
+// GFX12: encoding: [0x01,0x05,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+
+v_fmaak_f32 v5, v255, v2, 0xaf123456
+// GFX12: encoding: [0xff,0x05,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+
+v_fmaak_f32 v5, s1, v2, 0xaf123456
+// GFX12: encoding: [0x01,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+
+v_fmaak_f32 v5, s105, v2, 0xaf123456
+// GFX12: encoding: [0x69,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+
+v_fmaak_f32 v5, vcc_lo, v2, 0xaf123456
+// GFX12: encoding: [0x6a,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+
+v_fmaak_f32 v5, vcc_hi, v2, 0xaf123456
+// GFX12: encoding: [0x6b,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+
+v_fmaak_f32 v5, ttmp15, v2, 0xaf123456
+// GFX12: encoding: [0x7b,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+
+v_fmaak_f32 v5, m0, v2, 0xaf123456
+// GFX12: encoding: [0x7d,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+
+v_fmaak_f32 v5, exec_lo, v2, 0xaf123456
+// GFX12: encoding: [0x7e,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+
+v_fmaak_f32 v5, exec_hi, v2, 0xaf123456
+// GFX12: encoding: [0x7f,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+
+v_fmaak_f32 v5, null, v2, 0xaf123456
+// GFX12: encoding: [0x7c,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+
+v_fmaak_f32 v5, -1, v2, 0xaf123456
+// GFX12: encoding: [0xc1,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+
+v_fmaak_f32 v5, 0.5, v2, 0xaf123456
+// GFX12: encoding: [0xf0,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+
+v_fmaak_f32 v5, src_scc, v2, 0xaf123456
+// GFX12: encoding: [0xfd,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+
+v_fmaak_f32 v255, 0xaf123456, v255, 0xaf123456
+// GFX12: encoding: [0xff,0xfe,0xff,0x5b,0x56,0x34,0x12,0xaf]
+
+v_fmac_f16 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x6c]
+
+v_fmac_f16 v5, v127, v2
+// GFX12: encoding: [0x7f,0x05,0x0a,0x6c]
+
+v_fmac_f16 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x6c]
+
+v_fmac_f16 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x6c]
+
+v_fmac_f16 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x6c]
+
+v_fmac_f16 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x6c]
+
+v_fmac_f16 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x6c]
+
+v_fmac_f16 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x6c]
+
+v_fmac_f16 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x6c]
+
+v_fmac_f16 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x6c]
+
+v_fmac_f16 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x6c]
+
+v_fmac_f16 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x6c]
+
+v_fmac_f16 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x6c]
+
+v_fmac_f16 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x6c]
+
+v_fmac_f16 v127, 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0xfe,0x6c,0x0b,0xfe,0x00,0x00]
+
+v_fmac_f32 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x56]
+
+v_fmac_f32 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x56]
+
+v_fmac_f32 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x56]
+
+v_fmac_f32 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x56]
+
+v_fmac_f32 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x56]
+
+v_fmac_f32 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x56]
+
+v_fmac_f32 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x56]
+
+v_fmac_f32 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x56]
+
+v_fmac_f32 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x56]
+
+v_fmac_f32 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x56]
+
+v_fmac_f32 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x56]
+
+v_fmac_f32 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x56]
+
+v_fmac_f32 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x56]
+
+v_fmac_f32 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x56]
+
+v_fmac_f32 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x57,0x56,0x34,0x12,0xaf]
+
+v_fmamk_f16 v5, v1, 0xfe0b, v3
+// GFX12: encoding: [0x01,0x07,0x0a,0x6e,0x0b,0xfe,0x00,0x00]
+
+v_fmamk_f16 v5, v127, 0xfe0b, v3
+// GFX12: encoding: [0x7f,0x07,0x0a,0x6e,0x0b,0xfe,0x00,0x00]
+
+v_fmamk_f16 v5, s1, 0xfe0b, v3
+// GFX12: encoding: [0x01,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00]
+
+v_fmamk_f16 v5, s105, 0xfe0b, v3
+// GFX12: encoding: [0x69,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00]
+
+v_fmamk_f16 v5, vcc_lo, 0xfe0b, v3
+// GFX12: encoding: [0x6a,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00]
+
+v_fmamk_f16 v5, vcc_hi, 0xfe0b, v3
+// GFX12: encoding: [0x6b,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00]
+
+v_fmamk_f16 v5, ttmp15, 0xfe0b, v3
+// GFX12: encoding: [0x7b,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00]
+
+v_fmamk_f16 v5, m0, 0xfe0b, v3
+// GFX12: encoding: [0x7d,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00]
+
+v_fmamk_f16 v5, exec_lo, 0xfe0b, v3
+// GFX12: encoding: [0x7e,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00]
+
+v_fmamk_f16 v5, exec_hi, 0xfe0b, v3
+// GFX12: encoding: [0x7f,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00]
+
+v_fmamk_f16 v5, null, 0xfe0b, v3
+// GFX12: encoding: [0x7c,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00]
+
+v_fmamk_f16 v5, -1, 0xfe0b, v3
+// GFX12: encoding: [0xc1,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00]
+
+v_fmamk_f16 v5, 0.5, 0xfe0b, v3
+// GFX12: encoding: [0xf0,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00]
+
+v_fmamk_f16 v5, src_scc, 0xfe0b, v3
+// GFX12: encoding: [0xfd,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00]
+
+v_fmamk_f16 v127, 0xfe0b, 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0xfe,0x6e,0x0b,0xfe,0x00,0x00]
+
+v_fmamk_f32 v5, v1, 0xaf123456, v3
+// GFX12: encoding: [0x01,0x07,0x0a,0x58,0x56,0x34,0x12,0xaf]
+
+v_fmamk_f32 v5, v255, 0xaf123456, v3
+// GFX12: encoding: [0xff,0x07,0x0a,0x58,0x56,0x34,0x12,0xaf]
+
+v_fmamk_f32 v5, s1, 0xaf123456, v3
+// GFX12: encoding: [0x01,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf]
+
+v_fmamk_f32 v5, s105, 0xaf123456, v3
+// GFX12: encoding: [0x69,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf]
+
+v_fmamk_f32 v5, vcc_lo, 0xaf123456, v3
+// GFX12: encoding: [0x6a,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf]
+
+v_fmamk_f32 v5, vcc_hi, 0xaf123456, v3
+// GFX12: encoding: [0x6b,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf]
+
+v_fmamk_f32 v5, ttmp15, 0xaf123456, v3
+// GFX12: encoding: [0x7b,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf]
+
+v_fmamk_f32 v5, m0, 0xaf123456, v3
+// GFX12: encoding: [0x7d,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf]
+
+v_fmamk_f32 v5, exec_lo, 0xaf123456, v3
+// GFX12: encoding: [0x7e,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf]
+
+v_fmamk_f32 v5, exec_hi, 0xaf123456, v3
+// GFX12: encoding: [0x7f,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf]
+
+v_fmamk_f32 v5, null, 0xaf123456, v3
+// GFX12: encoding: [0x7c,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf]
+
+v_fmamk_f32 v5, -1, 0xaf123456, v3
+// GFX12: encoding: [0xc1,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf]
+
+v_fmamk_f32 v5, 0.5, 0xaf123456, v3
+// GFX12: encoding: [0xf0,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf]
+
+v_fmamk_f32 v5, src_scc, 0xaf123456, v3
+// GFX12: encoding: [0xfd,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf]
+
+v_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x59,0x56,0x34,0x12,0xaf]
+
+v_ldexp_f16 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x76]
+
+v_ldexp_f16 v5, v127, v2
+// GFX12: encoding: [0x7f,0x05,0x0a,0x76]
+
+v_ldexp_f16 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x76]
+
+v_ldexp_f16 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x76]
+
+v_ldexp_f16 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x76]
+
+v_ldexp_f16 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x76]
+
+v_ldexp_f16 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x76]
+
+v_ldexp_f16 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x76]
+
+v_ldexp_f16 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x76]
+
+v_ldexp_f16 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x76]
+
+v_ldexp_f16 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x76]
+
+v_ldexp_f16 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x76]
+
+v_ldexp_f16 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x76]
+
+v_ldexp_f16 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x76]
+
+v_ldexp_f16 v127, 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0xfe,0x76,0x0b,0xfe,0x00,0x00]
+
+v_lshlrev_b32 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x30]
+
+v_lshlrev_b32 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x30]
+
+v_lshlrev_b32 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x30]
+
+v_lshlrev_b32 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x30]
+
+v_lshlrev_b32 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x30]
+
+v_lshlrev_b32 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x30]
+
+v_lshlrev_b32 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x30]
+
+v_lshlrev_b32 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x30]
+
+v_lshlrev_b32 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x30]
+
+v_lshlrev_b32 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x30]
+
+v_lshlrev_b32 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x30]
+
+v_lshlrev_b32 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x30]
+
+v_lshlrev_b32 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x30]
+
+v_lshlrev_b32 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x30]
+
+v_lshlrev_b32 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x31,0x56,0x34,0x12,0xaf]
+
+v_lshlrev_b64 v[5:6], v1, v[3:4]
+// GFX12: encoding: [0x01,0x07,0x0a,0x3e]
+
+v_lshlrev_b64 v[5:6], v255, v[2:3]
+// GFX12: encoding: [0xff,0x05,0x0a,0x3e]
+
+v_lshlrev_b64 v[5:6], s1, v[2:3]
+// GFX12: encoding: [0x01,0x04,0x0a,0x3e]
+
+v_lshlrev_b64 v[5:6], s105, v[2:3]
+// GFX12: encoding: [0x69,0x04,0x0a,0x3e]
+
+v_lshlrev_b64 v[5:6], vcc_lo, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0x0a,0x3e]
+
+v_lshlrev_b64 v[5:6], vcc_hi, v[2:3]
+// GFX12: encoding: [0x6b,0x04,0x0a,0x3e]
+
+v_lshlrev_b64 v[5:6], ttmp15, v[2:3]
+// GFX12: encoding: [0x7b,0x04,0x0a,0x3e]
+
+v_lshlrev_b64 v[5:6], exec_lo, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0x0a,0x3e]
+
+v_lshlrev_b64 v[5:6], exec_hi, v[2:3]
+// GFX12: encoding: [0x7f,0x04,0x0a,0x3e]
+
+v_lshlrev_b64 v[5:6], null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0x0a,0x3e]
+
+v_lshlrev_b64 v[5:6], -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0x0a,0x3e]
+
+v_lshlrev_b64 v[5:6], 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0x0a,0x3e]
+
+v_lshlrev_b64 v[5:6], src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0x0a,0x3e]
+
+v_lshlrev_b64 v[254:255], 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0xfd,0x3f,0x56,0x34,0x12,0xaf]
+
+v_lshrrev_b32 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x32]
+
+v_lshrrev_b32 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x32]
+
+v_lshrrev_b32 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x32]
+
+v_lshrrev_b32 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x32]
+
+v_lshrrev_b32 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x32]
+
+v_lshrrev_b32 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x32]
+
+v_lshrrev_b32 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x32]
+
+v_lshrrev_b32 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x32]
+
+v_lshrrev_b32 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x32]
+
+v_lshrrev_b32 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x32]
+
+v_lshrrev_b32 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x32]
+
+v_lshrrev_b32 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x32]
+
+v_lshrrev_b32 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x32]
+
+v_lshrrev_b32 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x32]
+
+v_lshrrev_b32 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x33,0x56,0x34,0x12,0xaf]
+
+v_max_num_f16 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x62]
+
+v_max_num_f16 v5, v127, v2
+// GFX12: encoding: [0x7f,0x05,0x0a,0x62]
+
+v_max_num_f16 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x62]
+
+v_max_num_f16 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x62]
+
+v_max_num_f16 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x62]
+
+v_max_num_f16 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x62]
+
+v_max_num_f16 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x62]
+
+v_max_num_f16 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x62]
+
+v_max_num_f16 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x62]
+
+v_max_num_f16 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x62]
+
+v_max_num_f16 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x62]
+
+v_max_num_f16 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x62]
+
+v_max_num_f16 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x62]
+
+v_max_num_f16 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x62]
+
+v_max_num_f16 v127, 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0xfe,0x62,0x0b,0xfe,0x00,0x00]
+
+v_max_num_f32 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x2c]
+
+v_max_num_f32 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x2c]
+
+v_max_num_f32 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x2c]
+
+v_max_num_f32 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x2c]
+
+v_max_num_f32 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x2c]
+
+v_max_num_f32 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x2c]
+
+v_max_num_f32 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x2c]
+
+v_max_num_f32 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x2c]
+
+v_max_num_f32 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x2c]
+
+v_max_num_f32 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x2c]
+
+v_max_num_f32 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x2c]
+
+v_max_num_f32 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x2c]
+
+v_max_num_f32 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x2c]
+
+v_max_num_f32 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x2c]
+
+v_max_num_f32 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x2d,0x56,0x34,0x12,0xaf]
+
+v_max_num_f64 v[5:6], v[1:2], v[3:4]
+// GFX12: encoding: [0x01,0x07,0x0a,0x1c]
+
+v_max_num_f64 v[5:6], v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0x0a,0x1c]
+
+v_max_num_f64 v[5:6], s[0:1], v[2:3]
+// GFX12: encoding: [0x00,0x04,0x0a,0x1c]
+
+v_max_num_f64 v[5:6], s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0x0a,0x1c]
+
+v_max_num_f64 v[5:6], vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0x0a,0x1c]
+
+v_max_num_f64 v[5:6], ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0x0a,0x1c]
+
+v_max_num_f64 v[5:6], exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0x0a,0x1c]
+
+v_max_num_f64 v[5:6], null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0x0a,0x1c]
+
+v_max_num_f64 v[5:6], -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0x0a,0x1c]
+
+v_max_num_f64 v[5:6], 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0x0a,0x1c]
+
+v_max_num_f64 v[5:6], src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0x0a,0x1c]
+
+v_max_num_f64 v[254:255], 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0xfd,0x1d,0x56,0x34,0x12,0xaf]
+
+v_max_i32 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x24]
+
+v_max_i32 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x24]
+
+v_max_i32 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x24]
+
+v_max_i32 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x24]
+
+v_max_i32 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x24]
+
+v_max_i32 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x24]
+
+v_max_i32 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x24]
+
+v_max_i32 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x24]
+
+v_max_i32 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x24]
+
+v_max_i32 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x24]
+
+v_max_i32 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x24]
+
+v_max_i32 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x24]
+
+v_max_i32 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x24]
+
+v_max_i32 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x24]
+
+v_max_i32 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x25,0x56,0x34,0x12,0xaf]
+
+v_max_u32 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x28]
+
+v_max_u32 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x28]
+
+v_max_u32 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x28]
+
+v_max_u32 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x28]
+
+v_max_u32 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x28]
+
+v_max_u32 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x28]
+
+v_max_u32 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x28]
+
+v_max_u32 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x28]
+
+v_max_u32 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x28]
+
+v_max_u32 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x28]
+
+v_max_u32 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x28]
+
+v_max_u32 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x28]
+
+v_max_u32 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x28]
+
+v_max_u32 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x28]
+
+v_max_u32 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x29,0x56,0x34,0x12,0xaf]
+
+v_min_num_f16 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x60]
+
+v_min_num_f16 v5, v127, v2
+// GFX12: encoding: [0x7f,0x05,0x0a,0x60]
+
+v_min_num_f16 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x60]
+
+v_min_num_f16 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x60]
+
+v_min_num_f16 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x60]
+
+v_min_num_f16 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x60]
+
+v_min_num_f16 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x60]
+
+v_min_num_f16 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x60]
+
+v_min_num_f16 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x60]
+
+v_min_num_f16 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x60]
+
+v_min_num_f16 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x60]
+
+v_min_num_f16 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x60]
+
+v_min_num_f16 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x60]
+
+v_min_num_f16 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x60]
+
+v_min_num_f16 v127, 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0xfe,0x60,0x0b,0xfe,0x00,0x00]
+
+v_min_num_f32 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x2a]
+
+v_min_num_f32 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x2a]
+
+v_min_num_f32 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x2a]
+
+v_min_num_f32 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x2a]
+
+v_min_num_f32 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x2a]
+
+v_min_num_f32 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x2a]
+
+v_min_num_f32 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x2a]
+
+v_min_num_f32 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x2a]
+
+v_min_num_f32 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x2a]
+
+v_min_num_f32 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x2a]
+
+v_min_num_f32 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x2a]
+
+v_min_num_f32 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x2a]
+
+v_min_num_f32 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x2a]
+
+v_min_num_f32 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x2a]
+
+v_min_num_f32 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x2b,0x56,0x34,0x12,0xaf]
+
+v_min_num_f64 v[5:6], v[1:2], v[3:4]
+// GFX12: encoding: [0x01,0x07,0x0a,0x1a]
+
+v_min_num_f64 v[5:6], v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0x0a,0x1a]
+
+v_min_num_f64 v[5:6], s[0:1], v[2:3]
+// GFX12: encoding: [0x00,0x04,0x0a,0x1a]
+
+v_min_num_f64 v[5:6], s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0x0a,0x1a]
+
+v_min_num_f64 v[5:6], vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0x0a,0x1a]
+
+v_min_num_f64 v[5:6], ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0x0a,0x1a]
+
+v_min_num_f64 v[5:6], exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0x0a,0x1a]
+
+v_min_num_f64 v[5:6], null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0x0a,0x1a]
+
+v_min_num_f64 v[5:6], -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0x0a,0x1a]
+
+v_min_num_f64 v[5:6], 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0x0a,0x1a]
+
+v_min_num_f64 v[5:6], src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0x0a,0x1a]
+
+v_min_num_f64 v[254:255], 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0xfd,0x1b,0x56,0x34,0x12,0xaf]
+
+v_min_i32 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x22]
+
+v_min_i32 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x22]
+
+v_min_i32 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x22]
+
+v_min_i32 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x22]
+
+v_min_i32 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x22]
+
+v_min_i32 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x22]
+
+v_min_i32 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x22]
+
+v_min_i32 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x22]
+
+v_min_i32 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x22]
+
+v_min_i32 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x22]
+
+v_min_i32 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x22]
+
+v_min_i32 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x22]
+
+v_min_i32 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x22]
+
+v_min_i32 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x22]
+
+v_min_i32 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x23,0x56,0x34,0x12,0xaf]
+
+v_min_u32 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x26]
+
+v_min_u32 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x26]
+
+v_min_u32 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x26]
+
+v_min_u32 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x26]
+
+v_min_u32 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x26]
+
+v_min_u32 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x26]
+
+v_min_u32 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x26]
+
+v_min_u32 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x26]
+
+v_min_u32 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x26]
+
+v_min_u32 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x26]
+
+v_min_u32 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x26]
+
+v_min_u32 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x26]
+
+v_min_u32 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x26]
+
+v_min_u32 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x26]
+
+v_min_u32 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x27,0x56,0x34,0x12,0xaf]
+
+v_mul_dx9_zero_f32 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x0e]
+
+v_mul_dx9_zero_f32 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x0e]
+
+v_mul_dx9_zero_f32 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x0e]
+
+v_mul_dx9_zero_f32 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x0e]
+
+v_mul_dx9_zero_f32 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x0e]
+
+v_mul_dx9_zero_f32 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x0e]
+
+v_mul_dx9_zero_f32 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x0e]
+
+v_mul_dx9_zero_f32 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x0e]
+
+v_mul_dx9_zero_f32 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x0e]
+
+v_mul_dx9_zero_f32 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x0e]
+
+v_mul_dx9_zero_f32 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x0e]
+
+v_mul_dx9_zero_f32 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x0e]
+
+v_mul_dx9_zero_f32 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x0e]
+
+v_mul_dx9_zero_f32 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x0e]
+
+v_mul_dx9_zero_f32 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x0f,0x56,0x34,0x12,0xaf]
+
+v_mul_f16 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x6a]
+
+v_mul_f16 v5, v127, v2
+// GFX12: encoding: [0x7f,0x05,0x0a,0x6a]
+
+v_mul_f16 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x6a]
+
+v_mul_f16 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x6a]
+
+v_mul_f16 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x6a]
+
+v_mul_f16 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x6a]
+
+v_mul_f16 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x6a]
+
+v_mul_f16 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x6a]
+
+v_mul_f16 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x6a]
+
+v_mul_f16 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x6a]
+
+v_mul_f16 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x6a]
+
+v_mul_f16 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x6a]
+
+v_mul_f16 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x6a]
+
+v_mul_f16 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x6a]
+
+v_mul_f16 v127, 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00]
+
+v_mul_f32 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x10]
+
+v_mul_f32 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x10]
+
+v_mul_f32 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x10]
+
+v_mul_f32 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x10]
+
+v_mul_f32 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x10]
+
+v_mul_f32 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x10]
+
+v_mul_f32 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x10]
+
+v_mul_f32 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x10]
+
+v_mul_f32 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x10]
+
+v_mul_f32 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x10]
+
+v_mul_f32 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x10]
+
+v_mul_f32 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x10]
+
+v_mul_f32 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x10]
+
+v_mul_f32 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x10]
+
+v_mul_f32 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x11,0x56,0x34,0x12,0xaf]
+
+v_mul_f64 v[5:6], v[1:2], v[3:4]
+// GFX12: encoding: [0x01,0x07,0x0a,0x0c]
+
+v_mul_f64 v[5:6], v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0x0a,0x0c]
+
+v_mul_f64 v[5:6], s[0:1], v[2:3]
+// GFX12: encoding: [0x00,0x04,0x0a,0x0c]
+
+v_mul_f64 v[5:6], s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0x0a,0x0c]
+
+v_mul_f64 v[5:6], vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0x0a,0x0c]
+
+v_mul_f64 v[5:6], ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0x0a,0x0c]
+
+v_mul_f64 v[5:6], exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0x0a,0x0c]
+
+v_mul_f64 v[5:6], null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0x0a,0x0c]
+
+v_mul_f64 v[5:6], -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0x0a,0x0c]
+
+v_mul_f64 v[5:6], 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0x0a,0x0c]
+
+v_mul_f64 v[5:6], src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0x0a,0x0c]
+
+v_mul_f64 v[254:255], 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0xfd,0x0d,0x56,0x34,0x12,0xaf]
+
+v_mul_hi_i32_i24 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x15,0x56,0x34,0x12,0xaf]
+
+v_mul_hi_u32_u24 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x19,0x56,0x34,0x12,0xaf]
+
+v_mul_i32_i24 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x12]
+
+v_mul_i32_i24 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x12]
+
+v_mul_i32_i24 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x13,0x56,0x34,0x12,0xaf]
+
+v_mul_legacy_f32 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x0f,0x56,0x34,0x12,0xaf]
+
+v_mul_u32_u24 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x16]
+
+v_mul_u32_u24 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x16]
+
+v_mul_u32_u24 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x17,0x56,0x34,0x12,0xaf]
+
+v_or_b32 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x38]
+
+v_or_b32 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x38]
+
+v_or_b32 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x38]
+
+v_or_b32 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x38]
+
+v_or_b32 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x38]
+
+v_or_b32 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x38]
+
+v_or_b32 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x38]
+
+v_or_b32 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x38]
+
+v_or_b32 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x38]
+
+v_or_b32 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x38]
+
+v_or_b32 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x38]
+
+v_or_b32 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x38]
+
+v_or_b32 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x38]
+
+v_or_b32 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x38]
+
+v_or_b32 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x39,0x56,0x34,0x12,0xaf]
+
+v_pk_fmac_f16 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x78]
+
+v_pk_fmac_f16 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x78]
+
+v_pk_fmac_f16 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x78]
+
+v_pk_fmac_f16 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x78]
+
+v_pk_fmac_f16 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x78]
+
+v_pk_fmac_f16 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x78]
+
+v_pk_fmac_f16 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x78]
+
+v_pk_fmac_f16 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x78]
+
+v_pk_fmac_f16 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x78]
+
+v_pk_fmac_f16 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x78]
+
+v_pk_fmac_f16 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x78]
+
+v_pk_fmac_f16 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x78]
+
+v_pk_fmac_f16 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x78]
+
+v_pk_fmac_f16 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x78]
+
+v_pk_fmac_f16 v255, 0xfe0b, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x79,0x0b,0xfe,0x00,0x00]
+
+v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo
+// W32: encoding: [0x01,0x05,0x0a,0x42]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc_lo, v255, v2, vcc_lo
+// W32: encoding: [0xff,0x05,0x0a,0x42]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc_lo, s1, v2, vcc_lo
+// W32: encoding: [0x01,0x04,0x0a,0x42]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc_lo, s105, v2, vcc_lo
+// W32: encoding: [0x69,0x04,0x0a,0x42]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc_lo, vcc_lo, v2, vcc_lo
+// W32: encoding: [0x6a,0x04,0x0a,0x42]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc_lo, vcc_hi, v2, vcc_lo
+// W32: encoding: [0x6b,0x04,0x0a,0x42]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc_lo, ttmp15, v2, vcc_lo
+// W32: encoding: [0x7b,0x04,0x0a,0x42]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc_lo, m0, v2, vcc_lo
+// W32: encoding: [0x7d,0x04,0x0a,0x42]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc_lo, exec_lo, v2, vcc_lo
+// W32: encoding: [0x7e,0x04,0x0a,0x42]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc_lo, exec_hi, v2, vcc_lo
+// W32: encoding: [0x7f,0x04,0x0a,0x42]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc_lo, null, v2, vcc_lo
+// W32: encoding: [0x7c,0x04,0x0a,0x42]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc_lo, -1, v2, vcc_lo
+// W32: encoding: [0xc1,0x04,0x0a,0x42]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc_lo, 0.5, v2, vcc_lo
+// W32: encoding: [0xf0,0x04,0x0a,0x42]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc_lo, src_scc, v2, vcc_lo
+// W32: encoding: [0xfd,0x04,0x0a,0x42]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v255, vcc_lo, 0xaf123456, v255, vcc_lo
+// W32: encoding: [0xff,0xfe,0xff,0x43,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, v1, v2, vcc
+// W64: encoding: [0x01,0x05,0x0a,0x42]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, v255, v2, vcc
+// W64: encoding: [0xff,0x05,0x0a,0x42]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, s1, v2, vcc
+// W64: encoding: [0x01,0x04,0x0a,0x42]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, s105, v2, vcc
+// W64: encoding: [0x69,0x04,0x0a,0x42]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, vcc_lo, v2, vcc
+// W64: encoding: [0x6a,0x04,0x0a,0x42]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, vcc_hi, v2, vcc
+// W64: encoding: [0x6b,0x04,0x0a,0x42]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, ttmp15, v2, vcc
+// W64: encoding: [0x7b,0x04,0x0a,0x42]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, m0, v2, vcc
+// W64: encoding: [0x7d,0x04,0x0a,0x42]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, exec_lo, v2, vcc
+// W64: encoding: [0x7e,0x04,0x0a,0x42]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, exec_hi, v2, vcc
+// W64: encoding: [0x7f,0x04,0x0a,0x42]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, null, v2, vcc
+// W64: encoding: [0x7c,0x04,0x0a,0x42]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, -1, v2, vcc
+// W64: encoding: [0xc1,0x04,0x0a,0x42]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, 0.5, v2, vcc
+// W64: encoding: [0xf0,0x04,0x0a,0x42]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, src_scc, v2, vcc
+// W64: encoding: [0xfd,0x04,0x0a,0x42]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v255, vcc, 0xaf123456, v255, vcc
+// W64: encoding: [0xff,0xfe,0xff,0x43,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_f16 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x66]
+
+v_sub_f16 v5, v127, v2
+// GFX12: encoding: [0x7f,0x05,0x0a,0x66]
+
+v_sub_f16 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x66]
+
+v_sub_f16 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x66]
+
+v_sub_f16 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x66]
+
+v_sub_f16 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x66]
+
+v_sub_f16 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x66]
+
+v_sub_f16 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x66]
+
+v_sub_f16 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x66]
+
+v_sub_f16 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x66]
+
+v_sub_f16 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x66]
+
+v_sub_f16 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x66]
+
+v_sub_f16 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x66]
+
+v_sub_f16 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x66]
+
+v_sub_f16 v127, 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0xfe,0x66,0x0b,0xfe,0x00,0x00]
+
+v_sub_f32 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x08]
+
+v_sub_f32 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x08]
+
+v_sub_f32 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x08]
+
+v_sub_f32 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x08]
+
+v_sub_f32 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x08]
+
+v_sub_f32 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x08]
+
+v_sub_f32 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x08]
+
+v_sub_f32 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x08]
+
+v_sub_f32 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x08]
+
+v_sub_f32 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x08]
+
+v_sub_f32 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x08]
+
+v_sub_f32 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x08]
+
+v_sub_f32 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x08]
+
+v_sub_f32 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x08]
+
+v_sub_f32 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x09,0x56,0x34,0x12,0xaf]
+
+v_sub_nc_u32 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x4c]
+
+v_sub_nc_u32 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x4c]
+
+v_sub_nc_u32 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x4c]
+
+v_sub_nc_u32 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x4c]
+
+v_sub_nc_u32 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x4c]
+
+v_sub_nc_u32 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x4c]
+
+v_sub_nc_u32 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x4c]
+
+v_sub_nc_u32 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x4c]
+
+v_sub_nc_u32 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x4c]
+
+v_sub_nc_u32 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x4c]
+
+v_sub_nc_u32 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x4c]
+
+v_sub_nc_u32 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x4c]
+
+v_sub_nc_u32 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x4c]
+
+v_sub_nc_u32 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x4c]
+
+v_sub_nc_u32 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x4d,0x56,0x34,0x12,0xaf]
+
+v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo
+// W32: encoding: [0x01,0x05,0x0a,0x44]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc_lo, v255, v2, vcc_lo
+// W32: encoding: [0xff,0x05,0x0a,0x44]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc_lo, s1, v2, vcc_lo
+// W32: encoding: [0x01,0x04,0x0a,0x44]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc_lo, s105, v2, vcc_lo
+// W32: encoding: [0x69,0x04,0x0a,0x44]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc_lo, vcc_lo, v2, vcc_lo
+// W32: encoding: [0x6a,0x04,0x0a,0x44]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc_lo, vcc_hi, v2, vcc_lo
+// W32: encoding: [0x6b,0x04,0x0a,0x44]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc_lo, ttmp15, v2, vcc_lo
+// W32: encoding: [0x7b,0x04,0x0a,0x44]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc_lo, m0, v2, vcc_lo
+// W32: encoding: [0x7d,0x04,0x0a,0x44]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc_lo, exec_lo, v2, vcc_lo
+// W32: encoding: [0x7e,0x04,0x0a,0x44]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc_lo, exec_hi, v2, vcc_lo
+// W32: encoding: [0x7f,0x04,0x0a,0x44]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc_lo, null, v2, vcc_lo
+// W32: encoding: [0x7c,0x04,0x0a,0x44]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc_lo, -1, v2, vcc_lo
+// W32: encoding: [0xc1,0x04,0x0a,0x44]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc_lo, 0.5, v2, vcc_lo
+// W32: encoding: [0xf0,0x04,0x0a,0x44]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc_lo, src_scc, v2, vcc_lo
+// W32: encoding: [0xfd,0x04,0x0a,0x44]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v255, vcc_lo, 0xaf123456, v255, vcc_lo
+// W32: encoding: [0xff,0xfe,0xff,0x45,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc
+// W64: encoding: [0x01,0x05,0x0a,0x44]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, v255, v2, vcc
+// W64: encoding: [0xff,0x05,0x0a,0x44]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, s1, v2, vcc
+// W64: encoding: [0x01,0x04,0x0a,0x44]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, s105, v2, vcc
+// W64: encoding: [0x69,0x04,0x0a,0x44]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, vcc_lo, v2, vcc
+// W64: encoding: [0x6a,0x04,0x0a,0x44]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, vcc_hi, v2, vcc
+// W64: encoding: [0x6b,0x04,0x0a,0x44]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, ttmp15, v2, vcc
+// W64: encoding: [0x7b,0x04,0x0a,0x44]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, m0, v2, vcc
+// W64: encoding: [0x7d,0x04,0x0a,0x44]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, exec_lo, v2, vcc
+// W64: encoding: [0x7e,0x04,0x0a,0x44]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, exec_hi, v2, vcc
+// W64: encoding: [0x7f,0x04,0x0a,0x44]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, null, v2, vcc
+// W64: encoding: [0x7c,0x04,0x0a,0x44]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, -1, v2, vcc
+// W64: encoding: [0xc1,0x04,0x0a,0x44]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, 0.5, v2, vcc
+// W64: encoding: [0xf0,0x04,0x0a,0x44]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, src_scc, v2, vcc
+// W64: encoding: [0xfd,0x04,0x0a,0x44]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v255, vcc, 0xaf123456, v255, vcc
+// W64: encoding: [0xff,0xfe,0xff,0x45,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_f16 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x68]
+
+v_subrev_f16 v5, v127, v2
+// GFX12: encoding: [0x7f,0x05,0x0a,0x68]
+
+v_subrev_f16 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x68]
+
+v_subrev_f16 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x68]
+
+v_subrev_f16 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x68]
+
+v_subrev_f16 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x68]
+
+v_subrev_f16 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x68]
+
+v_subrev_f16 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x68]
+
+v_subrev_f16 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x68]
+
+v_subrev_f16 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x68]
+
+v_subrev_f16 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x68]
+
+v_subrev_f16 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x68]
+
+v_subrev_f16 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x68]
+
+v_subrev_f16 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x68]
+
+v_subrev_f16 v127, 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0xfe,0x68,0x0b,0xfe,0x00,0x00]
+
+v_subrev_f32 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x0a]
+
+v_subrev_f32 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x0a]
+
+v_subrev_f32 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x0a]
+
+v_subrev_f32 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x0b,0x56,0x34,0x12,0xaf]
+
+v_subrev_nc_u32 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x4e]
+
+v_subrev_nc_u32 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x4e]
+
+v_subrev_nc_u32 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x4e]
+
+v_subrev_nc_u32 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x4e]
+
+v_subrev_nc_u32 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x4e]
+
+v_subrev_nc_u32 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x4e]
+
+v_subrev_nc_u32 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x4e]
+
+v_subrev_nc_u32 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x4e]
+
+v_subrev_nc_u32 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x4e]
+
+v_subrev_nc_u32 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x4e]
+
+v_subrev_nc_u32 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x4e]
+
+v_subrev_nc_u32 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x4e]
+
+v_subrev_nc_u32 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x4e]
+
+v_subrev_nc_u32 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x4e]
+
+v_subrev_nc_u32 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x4f,0x56,0x34,0x12,0xaf]
+
+v_xnor_b32 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x3c]
+
+v_xnor_b32 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x3c]
+
+v_xnor_b32 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x3c]
+
+v_xnor_b32 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x3c]
+
+v_xnor_b32 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x3c]
+
+v_xnor_b32 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x3c]
+
+v_xnor_b32 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x3c]
+
+v_xnor_b32 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x3c]
+
+v_xnor_b32 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x3c]
+
+v_xnor_b32 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x3c]
+
+v_xnor_b32 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x3c]
+
+v_xnor_b32 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x3c]
+
+v_xnor_b32 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x3c]
+
+v_xnor_b32 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x3c]
+
+v_xnor_b32 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x3d,0x56,0x34,0x12,0xaf]
+
+v_xor_b32 v5, v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x3a]
+
+v_xor_b32 v5, v255, v2
+// GFX12: encoding: [0xff,0x05,0x0a,0x3a]
+
+v_xor_b32 v5, s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x3a]
+
+v_xor_b32 v255, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x3b,0x56,0x34,0x12,0xaf]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_aliases.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_aliases.s
new file mode 100644
index 000000000000..53bd4649fd3a
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_aliases.s
@@ -0,0 +1,19 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
+
+v_min_f32 v5, v1, v2
+// GFX12: v_min_num_f32_e32 v5, v1, v2            ; encoding: [0x01,0x05,0x0a,0x2a]
+
+v_max_f32 v5, v1, v2
+// GFX12: v_max_num_f32_e32 v5, v1, v2            ; encoding: [0x01,0x05,0x0a,0x2c]
+
+v_min_f16 v5, v1, v2
+// GFX12: v_min_num_f16_e32 v5, v1, v2            ; encoding: [0x01,0x05,0x0a,0x60]
+
+v_max_f16 v5, v1, v2
+// GFX12: v_max_num_f16_e32 v5, v1, v2            ; encoding: [0x01,0x05,0x0a,0x62]
+
+v_max_f64 v[5:6], v[1:2], v[2:3]
+// GFX12: v_max_num_f64_e32 v[5:6], v[1:2], v[2:3] ; encoding: [0x01,0x05,0x0a,0x1c]
+
+v_min_f64 v[5:6], v[1:2], v[2:3]
+// GFX12: v_min_num_f64_e32 v[5:6], v[1:2], v[2:3] ; encoding: [0x01,0x05,0x0a,0x1a]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s
new file mode 100644
index 000000000000..0c9a3f4f3359
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s
@@ -0,0 +1,2006 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W32 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W64 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+
+v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_mirror
+// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_half_mirror
+// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shl:1
+// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shl:15
+// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shr:1
+// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shr:15
+// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_ror:1
+// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_ror:15
+// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v255, vcc_lo, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0xff,0x41,0xff,0x6f,0x05,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_mirror
+// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_half_mirror
+// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_shl:1
+// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_shl:15
+// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_shr:1
+// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_shr:15
+// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_ror:1
+// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_ror:15
+// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0xff,0x41,0xff,0x6f,0x05,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_f16 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0xff]
+
+v_add_f16 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0xff]
+
+v_add_f16 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x40,0x01,0xff]
+
+v_add_f16 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x41,0x01,0xff]
+
+v_add_f16 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x01,0x01,0xff]
+
+v_add_f16 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x0f,0x01,0xff]
+
+v_add_f16 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x11,0x01,0xff]
+
+v_add_f16 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1f,0x01,0xff]
+
+v_add_f16 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x21,0x01,0xff]
+
+v_add_f16 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x2f,0x01,0xff]
+
+v_add_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x50,0x01,0xff]
+
+v_add_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x5f,0x01,0x01]
+
+v_add_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x60,0x09,0x13]
+
+v_add_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xfe,0x64,0x7f,0x6f,0xf5,0x30]
+
+v_add_f32 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x00,0xff]
+
+v_add_f32 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0xff]
+
+v_add_f32 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x40,0x01,0xff]
+
+v_add_f32 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x41,0x01,0xff]
+
+v_add_f32 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x01,0x01,0xff]
+
+v_add_f32 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x0f,0x01,0xff]
+
+v_add_f32 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x11,0x01,0xff]
+
+v_add_f32 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x1f,0x01,0xff]
+
+v_add_f32 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x21,0x01,0xff]
+
+v_add_f32 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x2f,0x01,0xff]
+
+v_add_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x50,0x01,0xff]
+
+v_add_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x5f,0x01,0x01]
+
+v_add_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x60,0x09,0x13]
+
+v_add_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x07,0xff,0x6f,0xf5,0x30]
+
+v_add_nc_u32 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x1b,0x00,0xff]
+
+v_add_nc_u32 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0xe4,0x00,0xff]
+
+v_add_nc_u32 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x40,0x01,0xff]
+
+v_add_nc_u32 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x41,0x01,0xff]
+
+v_add_nc_u32 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x01,0x01,0xff]
+
+v_add_nc_u32 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x0f,0x01,0xff]
+
+v_add_nc_u32 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x11,0x01,0xff]
+
+v_add_nc_u32 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x1f,0x01,0xff]
+
+v_add_nc_u32 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x21,0x01,0xff]
+
+v_add_nc_u32 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x2f,0x01,0xff]
+
+v_add_nc_u32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x50,0x01,0xff]
+
+v_add_nc_u32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x5f,0x01,0x01]
+
+v_add_nc_u32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x60,0x09,0x13]
+
+v_add_nc_u32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x4b,0xff,0x6f,0x05,0x30]
+
+v_and_b32 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x1b,0x00,0xff]
+
+v_and_b32 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0xff]
+
+v_and_b32 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x40,0x01,0xff]
+
+v_and_b32 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x41,0x01,0xff]
+
+v_and_b32 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x01,0x01,0xff]
+
+v_and_b32 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x0f,0x01,0xff]
+
+v_and_b32 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x11,0x01,0xff]
+
+v_and_b32 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x1f,0x01,0xff]
+
+v_and_b32 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x21,0x01,0xff]
+
+v_and_b32 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x2f,0x01,0xff]
+
+v_and_b32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x50,0x01,0xff]
+
+v_and_b32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x5f,0x01,0x01]
+
+v_and_b32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x60,0x09,0x13]
+
+v_and_b32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x37,0xff,0x6f,0x05,0x30]
+
+v_ashrrev_i32 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x1b,0x00,0xff]
+
+v_ashrrev_i32 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0xff]
+
+v_ashrrev_i32 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x40,0x01,0xff]
+
+v_ashrrev_i32 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x41,0x01,0xff]
+
+v_ashrrev_i32 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x01,0x01,0xff]
+
+v_ashrrev_i32 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x0f,0x01,0xff]
+
+v_ashrrev_i32 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x11,0x01,0xff]
+
+v_ashrrev_i32 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x1f,0x01,0xff]
+
+v_ashrrev_i32 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x21,0x01,0xff]
+
+v_ashrrev_i32 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x2f,0x01,0xff]
+
+v_ashrrev_i32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x50,0x01,0xff]
+
+v_ashrrev_i32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x5f,0x01,0x01]
+
+v_ashrrev_i32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x60,0x09,0x13]
+
+v_ashrrev_i32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x35,0xff,0x6f,0x05,0x30]
+
+v_cndmask_b32 v5, v1, v2, vcc_lo quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc_lo quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc_lo row_mirror
+// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc_lo row_half_mirror
+// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc_lo row_shl:1
+// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc_lo row_shl:15
+// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc_lo row_shr:1
+// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc_lo row_shr:15
+// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc_lo row_ror:1
+// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc_lo row_ror:15
+// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v255, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0xff,0x03,0xff,0x6f,0x05,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc row_mirror
+// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc row_half_mirror
+// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc row_shl:1
+// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc row_shl:15
+// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc row_shr:1
+// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc row_shr:15
+// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc row_ror:1
+// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc row_ror:15
+// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v255, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0xff,0x03,0xff,0x6f,0x05,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cvt_pk_rtz_f16_f32 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1b,0x00,0xff]
+
+v_cvt_pk_rtz_f16_f32 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xff]
+
+v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x40,0x01,0xff]
+
+v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x41,0x01,0xff]
+
+v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x01,0x01,0xff]
+
+v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x0f,0x01,0xff]
+
+v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x11,0x01,0xff]
+
+v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1f,0x01,0xff]
+
+v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x21,0x01,0xff]
+
+v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x2f,0x01,0xff]
+
+v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x50,0x01,0xff]
+
+v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x5f,0x01,0x01]
+
+v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x60,0x09,0x13]
+
+v_cvt_pk_rtz_f16_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x5f,0xff,0x6f,0xf5,0x30]
+
+v_cvt_pkrtz_f16_f32 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1b,0x00,0xff]
+
+v_cvt_pkrtz_f16_f32 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xff]
+
+v_cvt_pkrtz_f16_f32 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x40,0x01,0xff]
+
+v_cvt_pkrtz_f16_f32 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x41,0x01,0xff]
+
+v_cvt_pkrtz_f16_f32 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x01,0x01,0xff]
+
+v_cvt_pkrtz_f16_f32 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x0f,0x01,0xff]
+
+v_cvt_pkrtz_f16_f32 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x11,0x01,0xff]
+
+v_cvt_pkrtz_f16_f32 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1f,0x01,0xff]
+
+v_cvt_pkrtz_f16_f32 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x21,0x01,0xff]
+
+v_cvt_pkrtz_f16_f32 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x2f,0x01,0xff]
+
+v_cvt_pkrtz_f16_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x50,0x01,0xff]
+
+v_cvt_pkrtz_f16_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x5f,0x01,0x01]
+
+v_cvt_pkrtz_f16_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x60,0x09,0x13]
+
+v_cvt_pkrtz_f16_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x5f,0xff,0x6f,0xf5,0x30]
+
+v_fmac_f16 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x1b,0x00,0xff]
+
+v_fmac_f16 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0xff]
+
+v_fmac_f16 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x40,0x01,0xff]
+
+v_fmac_f16 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x41,0x01,0xff]
+
+v_fmac_f16 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x01,0x01,0xff]
+
+v_fmac_f16 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x0f,0x01,0xff]
+
+v_fmac_f16 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x11,0x01,0xff]
+
+v_fmac_f16 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x1f,0x01,0xff]
+
+v_fmac_f16 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x21,0x01,0xff]
+
+v_fmac_f16 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x2f,0x01,0xff]
+
+v_fmac_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x50,0x01,0xff]
+
+v_fmac_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x5f,0x01,0x01]
+
+v_fmac_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x60,0x09,0x13]
+
+v_fmac_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xfe,0x6c,0x7f,0x6f,0xf5,0x30]
+
+v_fmac_f32 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x1b,0x00,0xff]
+
+v_fmac_f32 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0xff]
+
+v_fmac_f32 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x40,0x01,0xff]
+
+v_fmac_f32 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x41,0x01,0xff]
+
+v_fmac_f32 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x01,0x01,0xff]
+
+v_fmac_f32 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x0f,0x01,0xff]
+
+v_fmac_f32 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x11,0x01,0xff]
+
+v_fmac_f32 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x1f,0x01,0xff]
+
+v_fmac_f32 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x21,0x01,0xff]
+
+v_fmac_f32 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x2f,0x01,0xff]
+
+v_fmac_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x50,0x01,0xff]
+
+v_fmac_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x5f,0x01,0x01]
+
+v_fmac_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x60,0x09,0x13]
+
+v_fmac_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x57,0xff,0x6f,0xf5,0x30]
+
+v_ldexp_f16 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x1b,0x00,0xff]
+
+v_ldexp_f16 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0xff]
+
+v_ldexp_f16 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x40,0x01,0xff]
+
+v_ldexp_f16 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x41,0x01,0xff]
+
+v_ldexp_f16 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x01,0x01,0xff]
+
+v_ldexp_f16 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x0f,0x01,0xff]
+
+v_ldexp_f16 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x11,0x01,0xff]
+
+v_ldexp_f16 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x1f,0x01,0xff]
+
+v_ldexp_f16 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x21,0x01,0xff]
+
+v_ldexp_f16 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x2f,0x01,0xff]
+
+v_ldexp_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x50,0x01,0xff]
+
+v_ldexp_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x5f,0x01,0x01]
+
+v_ldexp_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x60,0x09,0x13]
+
+v_ldexp_f16 v127, -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xfe,0x76,0x7f,0x6f,0x35,0x30]
+
+v_lshlrev_b32 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x1b,0x00,0xff]
+
+v_lshlrev_b32 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0xff]
+
+v_lshlrev_b32 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x40,0x01,0xff]
+
+v_lshlrev_b32 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x41,0x01,0xff]
+
+v_lshlrev_b32 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x01,0x01,0xff]
+
+v_lshlrev_b32 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x0f,0x01,0xff]
+
+v_lshlrev_b32 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x11,0x01,0xff]
+
+v_lshlrev_b32 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x1f,0x01,0xff]
+
+v_lshlrev_b32 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x21,0x01,0xff]
+
+v_lshlrev_b32 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x2f,0x01,0xff]
+
+v_lshlrev_b32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x50,0x01,0xff]
+
+v_lshlrev_b32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x5f,0x01,0x01]
+
+v_lshlrev_b32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x60,0x09,0x13]
+
+v_lshlrev_b32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x31,0xff,0x6f,0x05,0x30]
+
+v_lshrrev_b32 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x1b,0x00,0xff]
+
+v_lshrrev_b32 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0xff]
+
+v_lshrrev_b32 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x40,0x01,0xff]
+
+v_lshrrev_b32 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x41,0x01,0xff]
+
+v_lshrrev_b32 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x01,0x01,0xff]
+
+v_lshrrev_b32 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x0f,0x01,0xff]
+
+v_lshrrev_b32 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x11,0x01,0xff]
+
+v_lshrrev_b32 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x1f,0x01,0xff]
+
+v_lshrrev_b32 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x21,0x01,0xff]
+
+v_lshrrev_b32 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x2f,0x01,0xff]
+
+v_lshrrev_b32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x50,0x01,0xff]
+
+v_lshrrev_b32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x5f,0x01,0x01]
+
+v_lshrrev_b32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x60,0x09,0x13]
+
+v_lshrrev_b32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x33,0xff,0x6f,0x05,0x30]
+
+v_max_num_f16 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x62,0x01,0x1b,0x00,0xff]
+
+v_max_num_f16 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0xff]
+
+v_max_num_f16 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x62,0x01,0x40,0x01,0xff]
+
+v_max_num_f16 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x62,0x01,0x41,0x01,0xff]
+
+v_max_num_f16 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x62,0x01,0x01,0x01,0xff]
+
+v_max_num_f16 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x62,0x01,0x0f,0x01,0xff]
+
+v_max_num_f16 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x62,0x01,0x11,0x01,0xff]
+
+v_max_num_f16 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x62,0x01,0x1f,0x01,0xff]
+
+v_max_num_f16 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x62,0x01,0x21,0x01,0xff]
+
+v_max_num_f16 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x62,0x01,0x2f,0x01,0xff]
+
+v_max_num_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x62,0x01,0x50,0x01,0xff]
+
+v_max_num_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x62,0x01,0x5f,0x01,0x01]
+
+v_max_num_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x62,0x01,0x60,0x09,0x13]
+
+v_max_num_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xfe,0x62,0x7f,0x6f,0xf5,0x30]
+
+v_max_num_f32 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x1b,0x00,0xff]
+
+v_max_num_f32 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0xff]
+
+v_max_num_f32 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x40,0x01,0xff]
+
+v_max_num_f32 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x41,0x01,0xff]
+
+v_max_num_f32 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x01,0x01,0xff]
+
+v_max_num_f32 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x0f,0x01,0xff]
+
+v_max_num_f32 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x11,0x01,0xff]
+
+v_max_num_f32 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x1f,0x01,0xff]
+
+v_max_num_f32 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x21,0x01,0xff]
+
+v_max_num_f32 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x2f,0x01,0xff]
+
+v_max_num_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x50,0x01,0xff]
+
+v_max_num_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x5f,0x01,0x01]
+
+v_max_num_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x60,0x09,0x13]
+
+v_max_num_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x2d,0xff,0x6f,0xf5,0x30]
+
+v_max_i32 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x1b,0x00,0xff]
+
+v_max_i32 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0xff]
+
+v_max_i32 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x40,0x01,0xff]
+
+v_max_i32 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x41,0x01,0xff]
+
+v_max_i32 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x01,0x01,0xff]
+
+v_max_i32 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x0f,0x01,0xff]
+
+v_max_i32 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x11,0x01,0xff]
+
+v_max_i32 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x1f,0x01,0xff]
+
+v_max_i32 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x21,0x01,0xff]
+
+v_max_i32 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x2f,0x01,0xff]
+
+v_max_i32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x50,0x01,0xff]
+
+v_max_i32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x5f,0x01,0x01]
+
+v_max_i32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x60,0x09,0x13]
+
+v_max_i32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x25,0xff,0x6f,0x05,0x30]
+
+v_max_u32 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x1b,0x00,0xff]
+
+v_max_u32 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0xff]
+
+v_max_u32 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x40,0x01,0xff]
+
+v_max_u32 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x41,0x01,0xff]
+
+v_max_u32 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x01,0x01,0xff]
+
+v_max_u32 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x0f,0x01,0xff]
+
+v_max_u32 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x11,0x01,0xff]
+
+v_max_u32 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x1f,0x01,0xff]
+
+v_max_u32 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x21,0x01,0xff]
+
+v_max_u32 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x2f,0x01,0xff]
+
+v_max_u32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x50,0x01,0xff]
+
+v_max_u32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x5f,0x01,0x01]
+
+v_max_u32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x60,0x09,0x13]
+
+v_max_u32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x29,0xff,0x6f,0x05,0x30]
+
+v_min_num_f16 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x60,0x01,0x1b,0x00,0xff]
+
+v_min_num_f16 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0xff]
+
+v_min_num_f16 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x60,0x01,0x40,0x01,0xff]
+
+v_min_num_f16 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x60,0x01,0x41,0x01,0xff]
+
+v_min_num_f16 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x60,0x01,0x01,0x01,0xff]
+
+v_min_num_f16 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x60,0x01,0x0f,0x01,0xff]
+
+v_min_num_f16 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x60,0x01,0x11,0x01,0xff]
+
+v_min_num_f16 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x60,0x01,0x1f,0x01,0xff]
+
+v_min_num_f16 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x60,0x01,0x21,0x01,0xff]
+
+v_min_num_f16 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x60,0x01,0x2f,0x01,0xff]
+
+v_min_num_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x60,0x01,0x50,0x01,0xff]
+
+v_min_num_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x60,0x01,0x5f,0x01,0x01]
+
+v_min_num_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x60,0x01,0x60,0x09,0x13]
+
+v_min_num_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xfe,0x60,0x7f,0x6f,0xf5,0x30]
+
+v_min_num_f32 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x1b,0x00,0xff]
+
+v_min_num_f32 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0xff]
+
+v_min_num_f32 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x40,0x01,0xff]
+
+v_min_num_f32 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x41,0x01,0xff]
+
+v_min_num_f32 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x01,0x01,0xff]
+
+v_min_num_f32 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x0f,0x01,0xff]
+
+v_min_num_f32 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x11,0x01,0xff]
+
+v_min_num_f32 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x1f,0x01,0xff]
+
+v_min_num_f32 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x21,0x01,0xff]
+
+v_min_num_f32 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x2f,0x01,0xff]
+
+v_min_num_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x50,0x01,0xff]
+
+v_min_num_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x5f,0x01,0x01]
+
+v_min_num_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x60,0x09,0x13]
+
+v_min_num_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x2b,0xff,0x6f,0xf5,0x30]
+
+v_min_i32 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x1b,0x00,0xff]
+
+v_min_i32 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0xff]
+
+v_min_i32 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x40,0x01,0xff]
+
+v_min_i32 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x41,0x01,0xff]
+
+v_min_i32 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x01,0x01,0xff]
+
+v_min_i32 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x0f,0x01,0xff]
+
+v_min_i32 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x11,0x01,0xff]
+
+v_min_i32 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x1f,0x01,0xff]
+
+v_min_i32 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x21,0x01,0xff]
+
+v_min_i32 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x2f,0x01,0xff]
+
+v_min_i32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x50,0x01,0xff]
+
+v_min_i32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x5f,0x01,0x01]
+
+v_min_i32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x60,0x09,0x13]
+
+v_min_i32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x23,0xff,0x6f,0x05,0x30]
+
+v_min_u32 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x1b,0x00,0xff]
+
+v_min_u32 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0xff]
+
+v_min_u32 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x40,0x01,0xff]
+
+v_min_u32 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x41,0x01,0xff]
+
+v_min_u32 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x01,0x01,0xff]
+
+v_min_u32 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x0f,0x01,0xff]
+
+v_min_u32 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x11,0x01,0xff]
+
+v_min_u32 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x1f,0x01,0xff]
+
+v_min_u32 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x21,0x01,0xff]
+
+v_min_u32 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x2f,0x01,0xff]
+
+v_min_u32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x50,0x01,0xff]
+
+v_min_u32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x5f,0x01,0x01]
+
+v_min_u32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x60,0x09,0x13]
+
+v_min_u32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x27,0xff,0x6f,0x05,0x30]
+
+v_mul_dx9_zero_f32 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1b,0x00,0xff]
+
+v_mul_dx9_zero_f32 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0xff]
+
+v_mul_dx9_zero_f32 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x40,0x01,0xff]
+
+v_mul_dx9_zero_f32 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x41,0x01,0xff]
+
+v_mul_dx9_zero_f32 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x01,0x01,0xff]
+
+v_mul_dx9_zero_f32 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x0f,0x01,0xff]
+
+v_mul_dx9_zero_f32 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x11,0x01,0xff]
+
+v_mul_dx9_zero_f32 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1f,0x01,0xff]
+
+v_mul_dx9_zero_f32 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x21,0x01,0xff]
+
+v_mul_dx9_zero_f32 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x2f,0x01,0xff]
+
+v_mul_dx9_zero_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x50,0x01,0xff]
+
+v_mul_dx9_zero_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x5f,0x01,0x01]
+
+v_mul_dx9_zero_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x60,0x09,0x13]
+
+v_mul_dx9_zero_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x0f,0xff,0x6f,0xf5,0x30]
+
+v_mul_f16 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0xff]
+
+v_mul_f16 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xff]
+
+v_mul_f16 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x40,0x01,0xff]
+
+v_mul_f16 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x41,0x01,0xff]
+
+v_mul_f16 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x01,0x01,0xff]
+
+v_mul_f16 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x0f,0x01,0xff]
+
+v_mul_f16 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x11,0x01,0xff]
+
+v_mul_f16 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1f,0x01,0xff]
+
+v_mul_f16 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x21,0x01,0xff]
+
+v_mul_f16 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x2f,0x01,0xff]
+
+v_mul_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x50,0x01,0xff]
+
+v_mul_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x5f,0x01,0x01]
+
+v_mul_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x60,0x09,0x13]
+
+v_mul_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xfe,0x6a,0x7f,0x6f,0xf5,0x30]
+
+v_mul_f32 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x1b,0x00,0xff]
+
+v_mul_f32 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0xff]
+
+v_mul_f32 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x40,0x01,0xff]
+
+v_mul_f32 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x41,0x01,0xff]
+
+v_mul_f32 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x01,0x01,0xff]
+
+v_mul_f32 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x0f,0x01,0xff]
+
+v_mul_f32 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x11,0x01,0xff]
+
+v_mul_f32 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x1f,0x01,0xff]
+
+v_mul_f32 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x21,0x01,0xff]
+
+v_mul_f32 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x2f,0x01,0xff]
+
+v_mul_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x50,0x01,0xff]
+
+v_mul_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x5f,0x01,0x01]
+
+v_mul_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x60,0x09,0x13]
+
+v_mul_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x11,0xff,0x6f,0xf5,0x30]
+
+v_mul_hi_i32_i24 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x1b,0x00,0xff]
+
+v_mul_hi_i32_i24 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0xff]
+
+v_mul_hi_i32_i24 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x40,0x01,0xff]
+
+v_mul_hi_i32_i24 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x41,0x01,0xff]
+
+v_mul_hi_i32_i24 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x01,0x01,0xff]
+
+v_mul_hi_i32_i24 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x0f,0x01,0xff]
+
+v_mul_hi_i32_i24 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x11,0x01,0xff]
+
+v_mul_hi_i32_i24 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x1f,0x01,0xff]
+
+v_mul_hi_i32_i24 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x21,0x01,0xff]
+
+v_mul_hi_i32_i24 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x2f,0x01,0xff]
+
+v_mul_hi_i32_i24 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x50,0x01,0xff]
+
+v_mul_hi_i32_i24 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x5f,0x01,0x01]
+
+v_mul_hi_i32_i24 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x60,0x09,0x13]
+
+v_mul_hi_i32_i24 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x15,0xff,0x6f,0x05,0x30]
+
+v_mul_hi_u32_u24 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x1b,0x00,0xff]
+
+v_mul_hi_u32_u24 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0xff]
+
+v_mul_hi_u32_u24 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x40,0x01,0xff]
+
+v_mul_hi_u32_u24 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x41,0x01,0xff]
+
+v_mul_hi_u32_u24 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x01,0x01,0xff]
+
+v_mul_hi_u32_u24 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x0f,0x01,0xff]
+
+v_mul_hi_u32_u24 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x11,0x01,0xff]
+
+v_mul_hi_u32_u24 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x1f,0x01,0xff]
+
+v_mul_hi_u32_u24 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x21,0x01,0xff]
+
+v_mul_hi_u32_u24 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x2f,0x01,0xff]
+
+v_mul_hi_u32_u24 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x50,0x01,0xff]
+
+v_mul_hi_u32_u24 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x5f,0x01,0x01]
+
+v_mul_hi_u32_u24 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x60,0x09,0x13]
+
+v_mul_hi_u32_u24 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x19,0xff,0x6f,0x05,0x30]
+
+v_mul_i32_i24 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x1b,0x00,0xff]
+
+v_mul_i32_i24 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0xff]
+
+v_mul_i32_i24 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x40,0x01,0xff]
+
+v_mul_i32_i24 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x41,0x01,0xff]
+
+v_mul_i32_i24 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x01,0x01,0xff]
+
+v_mul_i32_i24 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x0f,0x01,0xff]
+
+v_mul_i32_i24 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x11,0x01,0xff]
+
+v_mul_i32_i24 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x1f,0x01,0xff]
+
+v_mul_i32_i24 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x21,0x01,0xff]
+
+v_mul_i32_i24 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x2f,0x01,0xff]
+
+v_mul_i32_i24 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x50,0x01,0xff]
+
+v_mul_i32_i24 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x5f,0x01,0x01]
+
+v_mul_i32_i24 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x60,0x09,0x13]
+
+v_mul_i32_i24 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x13,0xff,0x6f,0x05,0x30]
+
+v_mul_dx9_zero_f32 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1b,0x00,0xff]
+
+v_mul_dx9_zero_f32 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0xff]
+
+v_mul_dx9_zero_f32 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x40,0x01,0xff]
+
+v_mul_dx9_zero_f32 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x41,0x01,0xff]
+
+v_mul_dx9_zero_f32 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x01,0x01,0xff]
+
+v_mul_dx9_zero_f32 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x0f,0x01,0xff]
+
+v_mul_dx9_zero_f32 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x11,0x01,0xff]
+
+v_mul_dx9_zero_f32 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1f,0x01,0xff]
+
+v_mul_dx9_zero_f32 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x21,0x01,0xff]
+
+v_mul_dx9_zero_f32 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x2f,0x01,0xff]
+
+v_mul_dx9_zero_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x50,0x01,0xff]
+
+v_mul_dx9_zero_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x5f,0x01,0x01]
+
+v_mul_dx9_zero_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x60,0x09,0x13]
+
+v_mul_dx9_zero_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x0f,0xff,0x6f,0xf5,0x30]
+
+v_mul_u32_u24 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x1b,0x00,0xff]
+
+v_mul_u32_u24 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0xff]
+
+v_mul_u32_u24 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x40,0x01,0xff]
+
+v_mul_u32_u24 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x41,0x01,0xff]
+
+v_mul_u32_u24 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x01,0x01,0xff]
+
+v_mul_u32_u24 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x0f,0x01,0xff]
+
+v_mul_u32_u24 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x11,0x01,0xff]
+
+v_mul_u32_u24 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x1f,0x01,0xff]
+
+v_mul_u32_u24 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x21,0x01,0xff]
+
+v_mul_u32_u24 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x2f,0x01,0xff]
+
+v_mul_u32_u24 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x50,0x01,0xff]
+
+v_mul_u32_u24 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x5f,0x01,0x01]
+
+v_mul_u32_u24 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x60,0x09,0x13]
+
+v_mul_u32_u24 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x17,0xff,0x6f,0x05,0x30]
+
+v_or_b32 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x1b,0x00,0xff]
+
+v_or_b32 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0xff]
+
+v_or_b32 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x40,0x01,0xff]
+
+v_or_b32 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x41,0x01,0xff]
+
+v_or_b32 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x01,0x01,0xff]
+
+v_or_b32 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x0f,0x01,0xff]
+
+v_or_b32 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x11,0x01,0xff]
+
+v_or_b32 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x1f,0x01,0xff]
+
+v_or_b32 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x21,0x01,0xff]
+
+v_or_b32 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x2f,0x01,0xff]
+
+v_or_b32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x50,0x01,0xff]
+
+v_or_b32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x5f,0x01,0x01]
+
+v_or_b32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x60,0x09,0x13]
+
+v_or_b32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x39,0xff,0x6f,0x05,0x30]
+
+v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_mirror
+// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_half_mirror
+// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shl:1
+// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shl:15
+// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shr:1
+// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shr:15
+// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_ror:1
+// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_ror:15
+// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v255, vcc_lo, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0xff,0x43,0xff,0x6f,0x05,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_mirror
+// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_half_mirror
+// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_shl:1
+// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_shl:15
+// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_shr:1
+// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_shr:15
+// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_ror:1
+// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_ror:15
+// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0xff,0x43,0xff,0x6f,0x05,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_f16 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1b,0x00,0xff]
+
+v_sub_f16 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0xff]
+
+v_sub_f16 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x40,0x01,0xff]
+
+v_sub_f16 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x41,0x01,0xff]
+
+v_sub_f16 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x01,0x01,0xff]
+
+v_sub_f16 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x0f,0x01,0xff]
+
+v_sub_f16 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x11,0x01,0xff]
+
+v_sub_f16 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1f,0x01,0xff]
+
+v_sub_f16 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x21,0x01,0xff]
+
+v_sub_f16 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x2f,0x01,0xff]
+
+v_sub_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x50,0x01,0xff]
+
+v_sub_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x5f,0x01,0x01]
+
+v_sub_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x60,0x09,0x13]
+
+v_sub_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xfe,0x66,0x7f,0x6f,0xf5,0x30]
+
+v_sub_f32 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x1b,0x00,0xff]
+
+v_sub_f32 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0xff]
+
+v_sub_f32 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x40,0x01,0xff]
+
+v_sub_f32 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x41,0x01,0xff]
+
+v_sub_f32 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x01,0x01,0xff]
+
+v_sub_f32 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x0f,0x01,0xff]
+
+v_sub_f32 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x11,0x01,0xff]
+
+v_sub_f32 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x1f,0x01,0xff]
+
+v_sub_f32 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x21,0x01,0xff]
+
+v_sub_f32 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x2f,0x01,0xff]
+
+v_sub_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x50,0x01,0xff]
+
+v_sub_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x5f,0x01,0x01]
+
+v_sub_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x60,0x09,0x13]
+
+v_sub_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x09,0xff,0x6f,0xf5,0x30]
+
+v_sub_nc_u32 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x1b,0x00,0xff]
+
+v_sub_nc_u32 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0xff]
+
+v_sub_nc_u32 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x40,0x01,0xff]
+
+v_sub_nc_u32 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x41,0x01,0xff]
+
+v_sub_nc_u32 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x01,0x01,0xff]
+
+v_sub_nc_u32 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x0f,0x01,0xff]
+
+v_sub_nc_u32 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x11,0x01,0xff]
+
+v_sub_nc_u32 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x1f,0x01,0xff]
+
+v_sub_nc_u32 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x21,0x01,0xff]
+
+v_sub_nc_u32 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x2f,0x01,0xff]
+
+v_sub_nc_u32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x50,0x01,0xff]
+
+v_sub_nc_u32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x5f,0x01,0x01]
+
+v_sub_nc_u32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x60,0x09,0x13]
+
+v_sub_nc_u32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x4d,0xff,0x6f,0x05,0x30]
+
+v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_mirror
+// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_half_mirror
+// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shl:1
+// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shl:15
+// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shr:1
+// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shr:15
+// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_ror:1
+// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_ror:15
+// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v255, vcc_lo, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0xff,0x45,0xff,0x6f,0x05,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_mirror
+// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_half_mirror
+// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_shl:1
+// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_shl:15
+// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_shr:1
+// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_shr:15
+// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_ror:1
+// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_ror:15
+// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0xff,0x45,0xff,0x6f,0x05,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_f16 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1b,0x00,0xff]
+
+v_subrev_f16 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0xff]
+
+v_subrev_f16 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x40,0x01,0xff]
+
+v_subrev_f16 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x41,0x01,0xff]
+
+v_subrev_f16 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x01,0x01,0xff]
+
+v_subrev_f16 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x0f,0x01,0xff]
+
+v_subrev_f16 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x11,0x01,0xff]
+
+v_subrev_f16 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1f,0x01,0xff]
+
+v_subrev_f16 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x21,0x01,0xff]
+
+v_subrev_f16 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x2f,0x01,0xff]
+
+v_subrev_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x50,0x01,0xff]
+
+v_subrev_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x5f,0x01,0x01]
+
+v_subrev_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x60,0x09,0x13]
+
+v_subrev_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xfe,0x68,0x7f,0x6f,0xf5,0x30]
+
+v_subrev_f32 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x1b,0x00,0xff]
+
+v_subrev_f32 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0xff]
+
+v_subrev_f32 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x40,0x01,0xff]
+
+v_subrev_f32 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x41,0x01,0xff]
+
+v_subrev_f32 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x01,0x01,0xff]
+
+v_subrev_f32 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x0f,0x01,0xff]
+
+v_subrev_f32 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x11,0x01,0xff]
+
+v_subrev_f32 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x1f,0x01,0xff]
+
+v_subrev_f32 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x21,0x01,0xff]
+
+v_subrev_f32 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x2f,0x01,0xff]
+
+v_subrev_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x50,0x01,0xff]
+
+v_subrev_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x5f,0x01,0x01]
+
+v_subrev_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x60,0x09,0x13]
+
+v_subrev_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x0b,0xff,0x6f,0xf5,0x30]
+
+v_subrev_nc_u32 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x00,0xff]
+
+v_subrev_nc_u32 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0xff]
+
+v_subrev_nc_u32 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x40,0x01,0xff]
+
+v_subrev_nc_u32 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x41,0x01,0xff]
+
+v_subrev_nc_u32 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x01,0x01,0xff]
+
+v_subrev_nc_u32 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x0f,0x01,0xff]
+
+v_subrev_nc_u32 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x11,0x01,0xff]
+
+v_subrev_nc_u32 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x1f,0x01,0xff]
+
+v_subrev_nc_u32 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x21,0x01,0xff]
+
+v_subrev_nc_u32 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x2f,0x01,0xff]
+
+v_subrev_nc_u32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x50,0x01,0xff]
+
+v_subrev_nc_u32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x5f,0x01,0x01]
+
+v_subrev_nc_u32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x60,0x09,0x13]
+
+v_subrev_nc_u32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x4f,0xff,0x6f,0x05,0x30]
+
+v_xnor_b32 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x1b,0x00,0xff]
+
+v_xnor_b32 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0xff]
+
+v_xnor_b32 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x40,0x01,0xff]
+
+v_xnor_b32 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x41,0x01,0xff]
+
+v_xnor_b32 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x01,0x01,0xff]
+
+v_xnor_b32 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x0f,0x01,0xff]
+
+v_xnor_b32 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x11,0x01,0xff]
+
+v_xnor_b32 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x1f,0x01,0xff]
+
+v_xnor_b32 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x21,0x01,0xff]
+
+v_xnor_b32 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x2f,0x01,0xff]
+
+v_xnor_b32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x50,0x01,0xff]
+
+v_xnor_b32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x5f,0x01,0x01]
+
+v_xnor_b32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x60,0x09,0x13]
+
+v_xnor_b32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x3d,0xff,0x6f,0x05,0x30]
+
+v_xor_b32 v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x1b,0x00,0xff]
+
+v_xor_b32 v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0xff]
+
+v_xor_b32 v5, v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x40,0x01,0xff]
+
+v_xor_b32 v5, v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x41,0x01,0xff]
+
+v_xor_b32 v5, v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x01,0x01,0xff]
+
+v_xor_b32 v5, v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x0f,0x01,0xff]
+
+v_xor_b32 v5, v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x11,0x01,0xff]
+
+v_xor_b32 v5, v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x1f,0x01,0xff]
+
+v_xor_b32 v5, v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x21,0x01,0xff]
+
+v_xor_b32 v5, v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x2f,0x01,0xff]
+
+v_xor_b32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x50,0x01,0xff]
+
+v_xor_b32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x5f,0x01,0x01]
+
+v_xor_b32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x60,0x09,0x13]
+
+v_xor_b32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xff,0x3b,0xff,0x6f,0x05,0x30]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s
new file mode 100644
index 000000000000..423fcf307470
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s
@@ -0,0 +1,433 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W32 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W64 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+
+v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x0a,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x0a,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v255, vcc_lo, v255, v255, vcc_lo dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0xff,0x41,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x0a,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x0a,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32 v255, vcc, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0xff,0x41,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x64,0x01,0x77,0x39,0x05]
+
+v_add_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x64,0x01,0x77,0x39,0x05]
+
+v_add_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xfe,0x64,0x7f,0x00,0x00,0x00]
+
+v_add_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x06,0x01,0x77,0x39,0x05]
+
+v_add_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x06,0x01,0x77,0x39,0x05]
+
+v_add_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x07,0xff,0x00,0x00,0x00]
+
+v_add_nc_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x4a,0x01,0x77,0x39,0x05]
+
+v_add_nc_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x4a,0x01,0x77,0x39,0x05]
+
+v_add_nc_u32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x4b,0xff,0x00,0x00,0x00]
+
+v_and_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x36,0x01,0x77,0x39,0x05]
+
+v_and_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x36,0x01,0x77,0x39,0x05]
+
+v_and_b32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x37,0xff,0x00,0x00,0x00]
+
+v_ashrrev_i32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x34,0x01,0x77,0x39,0x05]
+
+v_ashrrev_i32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x34,0x01,0x77,0x39,0x05]
+
+v_ashrrev_i32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x35,0xff,0x00,0x00,0x00]
+
+v_cndmask_b32 v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x0a,0x02,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x0a,0x02,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v255, v255, v255, vcc_lo dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0xff,0x03,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x0a,0x02,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x0a,0x02,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v255, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0xff,0x03,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cvt_pk_rtz_f16_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x5e,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_rtz_f16_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x5e,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_rtz_f16_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x5f,0xff,0x00,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x5e,0x01,0x77,0x39,0x05]
+
+v_cvt_pkrtz_f16_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x5e,0x01,0x77,0x39,0x05]
+
+v_cvt_pkrtz_f16_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x5f,0xff,0x00,0x00,0x00]
+
+v_fmac_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x6c,0x01,0x77,0x39,0x05]
+
+v_fmac_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x6c,0x01,0x77,0x39,0x05]
+
+v_fmac_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xfe,0x6c,0x7f,0x00,0x00,0x00]
+
+v_fmac_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x56,0x01,0x77,0x39,0x05]
+
+v_fmac_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x56,0x01,0x77,0x39,0x05]
+
+v_fmac_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x57,0xff,0x00,0x00,0x00]
+
+v_ldexp_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x76,0x01,0x77,0x39,0x05]
+
+v_ldexp_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x76,0x01,0x77,0x39,0x05]
+
+v_ldexp_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xfe,0x76,0x7f,0x00,0x00,0x00]
+
+v_lshlrev_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x30,0x01,0x77,0x39,0x05]
+
+v_lshlrev_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x30,0x01,0x77,0x39,0x05]
+
+v_lshlrev_b32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x31,0xff,0x00,0x00,0x00]
+
+v_lshrrev_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x32,0x01,0x77,0x39,0x05]
+
+v_lshrrev_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x32,0x01,0x77,0x39,0x05]
+
+v_lshrrev_b32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x33,0xff,0x00,0x00,0x00]
+
+v_max_num_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x62,0x01,0x77,0x39,0x05]
+
+v_max_num_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x62,0x01,0x77,0x39,0x05]
+
+v_max_num_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xfe,0x62,0x7f,0x00,0x00,0x00]
+
+v_max_num_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x2c,0x01,0x77,0x39,0x05]
+
+v_max_num_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x2c,0x01,0x77,0x39,0x05]
+
+v_max_num_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x2d,0xff,0x00,0x00,0x00]
+
+v_max_i32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x24,0x01,0x77,0x39,0x05]
+
+v_max_i32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x24,0x01,0x77,0x39,0x05]
+
+v_max_i32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x25,0xff,0x00,0x00,0x00]
+
+v_max_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x28,0x01,0x77,0x39,0x05]
+
+v_max_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x28,0x01,0x77,0x39,0x05]
+
+v_max_u32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x29,0xff,0x00,0x00,0x00]
+
+v_min_num_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x60,0x01,0x77,0x39,0x05]
+
+v_min_num_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x60,0x01,0x77,0x39,0x05]
+
+v_min_num_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xfe,0x60,0x7f,0x00,0x00,0x00]
+
+v_min_num_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x2a,0x01,0x77,0x39,0x05]
+
+v_min_num_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x2a,0x01,0x77,0x39,0x05]
+
+v_min_num_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x2b,0xff,0x00,0x00,0x00]
+
+v_min_i32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x22,0x01,0x77,0x39,0x05]
+
+v_min_i32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x22,0x01,0x77,0x39,0x05]
+
+v_min_i32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x23,0xff,0x00,0x00,0x00]
+
+v_min_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x26,0x01,0x77,0x39,0x05]
+
+v_min_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x26,0x01,0x77,0x39,0x05]
+
+v_min_u32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x27,0xff,0x00,0x00,0x00]
+
+v_mul_dx9_zero_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x0e,0x01,0x77,0x39,0x05]
+
+v_mul_dx9_zero_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x0e,0x01,0x77,0x39,0x05]
+
+v_mul_dx9_zero_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x0f,0xff,0x00,0x00,0x00]
+
+v_mul_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05]
+
+v_mul_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05]
+
+v_mul_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xfe,0x6a,0x7f,0x00,0x00,0x00]
+
+v_mul_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x10,0x01,0x77,0x39,0x05]
+
+v_mul_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x10,0x01,0x77,0x39,0x05]
+
+v_mul_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x11,0xff,0x00,0x00,0x00]
+
+v_mul_hi_i32_i24 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x14,0x01,0x77,0x39,0x05]
+
+v_mul_hi_i32_i24 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x14,0x01,0x77,0x39,0x05]
+
+v_mul_hi_i32_i24 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x15,0xff,0x00,0x00,0x00]
+
+v_mul_hi_u32_u24 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x18,0x01,0x77,0x39,0x05]
+
+v_mul_hi_u32_u24 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x18,0x01,0x77,0x39,0x05]
+
+v_mul_hi_u32_u24 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x19,0xff,0x00,0x00,0x00]
+
+v_mul_i32_i24 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x12,0x01,0x77,0x39,0x05]
+
+v_mul_i32_i24 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x12,0x01,0x77,0x39,0x05]
+
+v_mul_i32_i24 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x13,0xff,0x00,0x00,0x00]
+
+v_mul_dx9_zero_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x0e,0x01,0x77,0x39,0x05]
+
+v_mul_dx9_zero_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x0e,0x01,0x77,0x39,0x05]
+
+v_mul_dx9_zero_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x0f,0xff,0x00,0x00,0x00]
+
+v_mul_u32_u24 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x16,0x01,0x77,0x39,0x05]
+
+v_mul_u32_u24 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x16,0x01,0x77,0x39,0x05]
+
+v_mul_u32_u24 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x17,0xff,0x00,0x00,0x00]
+
+v_or_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x38,0x01,0x77,0x39,0x05]
+
+v_or_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x38,0x01,0x77,0x39,0x05]
+
+v_or_b32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x39,0xff,0x00,0x00,0x00]
+
+v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x0a,0x42,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x0a,0x42,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v255, vcc_lo, v255, v255, vcc_lo dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0xff,0x43,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x0a,0x42,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x0a,0x42,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32 v255, vcc, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0xff,0x43,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x66,0x01,0x77,0x39,0x05]
+
+v_sub_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x66,0x01,0x77,0x39,0x05]
+
+v_sub_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xfe,0x66,0x7f,0x00,0x00,0x00]
+
+v_sub_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x08,0x01,0x77,0x39,0x05]
+
+v_sub_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x08,0x01,0x77,0x39,0x05]
+
+v_sub_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x09,0xff,0x00,0x00,0x00]
+
+v_sub_nc_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x4c,0x01,0x77,0x39,0x05]
+
+v_sub_nc_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x4c,0x01,0x77,0x39,0x05]
+
+v_sub_nc_u32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x4d,0xff,0x00,0x00,0x00]
+
+v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x0a,0x44,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x0a,0x44,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v255, vcc_lo, v255, v255, vcc_lo dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0xff,0x45,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x0a,0x44,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x0a,0x44,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32 v255, vcc, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0xff,0x45,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x68,0x01,0x77,0x39,0x05]
+
+v_subrev_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x68,0x01,0x77,0x39,0x05]
+
+v_subrev_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xfe,0x68,0x7f,0x00,0x00,0x00]
+
+v_subrev_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x0a,0x01,0x77,0x39,0x05]
+
+v_subrev_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x0a,0x01,0x77,0x39,0x05]
+
+v_subrev_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x0b,0xff,0x00,0x00,0x00]
+
+v_subrev_nc_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x4e,0x01,0x77,0x39,0x05]
+
+v_subrev_nc_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x4e,0x01,0x77,0x39,0x05]
+
+v_subrev_nc_u32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x4f,0xff,0x00,0x00,0x00]
+
+v_xnor_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x3c,0x01,0x77,0x39,0x05]
+
+v_xnor_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x3c,0x01,0x77,0x39,0x05]
+
+v_xnor_b32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x3d,0xff,0x00,0x00,0x00]
+
+v_xor_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x3a,0x01,0x77,0x39,0x05]
+
+v_xor_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x3a,0x01,0x77,0x39,0x05]
+
+v_xor_b32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xff,0x3b,0xff,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_err.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_err.s
new file mode 100644
index 000000000000..d25411b5bfd2
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_err.s
@@ -0,0 +1,226 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX12 --implicit-check-not=error %s
+
+v_add_f16_e32 v255, v1, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_fmaak_f16_e32 v255, v1, v2, 0xfe0b
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_fmac_f16_e32 v255, v1, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_fmamk_f16_e32 v255, v1, 0xfe0b, v3
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_ldexp_f16_e32 v255, v1, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_max_num_f16_e32 v255, v1, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_min_num_f16_e32 v255, v1, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mul_f16_e32 v255, v1, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_f16_e32 v255, v1, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_f16_e32 v255, v1, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_f16_e32 v5, v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_fmaak_f16_e32 v5, v255, v2, 0xfe0b
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_fmac_f16_e32 v5, v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_fmamk_f16_e32 v5, v255, 0xfe0b, v3
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_ldexp_f16_e32 v5, v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_max_num_f16_e32 v5, v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_min_num_f16_e32 v5, v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mul_f16_e32 v5, v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_f16_e32 v5, v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_f16_e32 v5, v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_f16_e32 v5, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_fmaak_f16_e32 v5, v1, v255, 0xfe0b
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_fmac_f16_e32 v5, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_fmamk_f16_e32 v5, v1, 0xfe0b, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_max_num_f16_e32 v5, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_min_num_f16_e32 v5, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mul_f16_e32 v5, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_f16_e32 v5, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_f16_e32 v5, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_fmac_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_ldexp_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_max_num_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_min_num_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mul_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_fmac_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_ldexp_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_max_num_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_min_num_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mul_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_fmac_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_max_num_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_min_num_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mul_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_fmac_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_ldexp_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_max_num_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_min_num_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mul_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_fmac_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_ldexp_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_max_num_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_min_num_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mul_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_fmac_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_max_num_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_min_num_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mul_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s
new file mode 100644
index 000000000000..febc6311c18a
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s
@@ -0,0 +1,190 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX12 --implicit-check-not=_e32 %s
+
+v_add_f16 v255, v1, v2
+// GFX12: v_add_f16_e64
+
+v_fmac_f16 v255, v1, v2
+// GFX12: v_fmac_f16_e64
+
+v_ldexp_f16 v255, v1, v2
+// GFX12: v_ldexp_f16_e64
+
+v_max_num_f16 v255, v1, v2
+// GFX12: v_max_num_f16_e64
+
+v_min_num_f16 v255, v1, v2
+// GFX12: v_min_num_f16_e64
+
+v_mul_f16 v255, v1, v2
+// GFX12: v_mul_f16_e64
+
+v_sub_f16 v255, v1, v2
+// GFX12: v_sub_f16_e64
+
+v_subrev_f16 v255, v1, v2
+// GFX12: v_subrev_f16_e64
+
+v_add_f16 v5, v255, v2
+// GFX12: v_add_f16_e64
+
+v_fmac_f16 v5, v255, v2
+// GFX12: v_fmac_f16_e64
+
+v_ldexp_f16 v5, v255, v2
+// GFX12: v_ldexp_f16_e64
+
+v_max_num_f16 v5, v255, v2
+// GFX12: v_max_num_f16_e64
+
+v_min_num_f16 v5, v255, v2
+// GFX12: v_min_num_f16_e64
+
+v_mul_f16 v5, v255, v2
+// GFX12: v_mul_f16_e64
+
+v_sub_f16 v5, v255, v2
+// GFX12: v_sub_f16_e64
+
+v_subrev_f16 v5, v255, v2
+// GFX12: v_subrev_f16_e64
+
+v_add_f16 v5, v1, v255
+// GFX12: v_add_f16_e64
+
+v_fmac_f16 v5, v1, v255
+// GFX12: v_fmac_f16_e64
+
+v_max_num_f16 v5, v1, v255
+// GFX12: v_max_num_f16_e64
+
+v_min_num_f16 v5, v1, v255
+// GFX12: v_min_num_f16_e64
+
+v_mul_f16 v5, v1, v255
+// GFX12: v_mul_f16_e64
+
+v_sub_f16 v5, v1, v255
+// GFX12: v_sub_f16_e64
+
+v_subrev_f16 v5, v1, v255
+// GFX12: v_subrev_f16_e64
+
+v_add_f16 v255, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: v_add_f16_e64
+
+v_ldexp_f16 v255, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: v_ldexp_f16_e64
+
+v_max_num_f16 v255, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: v_max_num_f16_e64
+
+v_min_num_f16 v255, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: v_min_num_f16_e64
+
+v_mul_f16 v255, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: v_mul_f16_e64
+
+v_sub_f16 v255, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: v_sub_f16_e64
+
+v_subrev_f16 v255, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: v_subrev_f16_e64
+
+v_add_f16 v5, v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_add_f16_e64
+
+v_ldexp_f16 v5, v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_ldexp_f16_e64
+
+v_max_num_f16 v5, v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_max_num_f16_e64
+
+v_min_num_f16 v5, v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_min_num_f16_e64
+
+v_mul_f16 v5, v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_mul_f16_e64
+
+v_sub_f16 v5, v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_sub_f16_e64
+
+v_subrev_f16 v5, v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_subrev_f16_e64
+
+v_add_f16 v5, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_add_f16_e64
+
+v_max_num_f16 v5, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_max_num_f16_e64
+
+v_min_num_f16 v5, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_min_num_f16_e64
+
+v_mul_f16 v5, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_mul_f16_e64
+
+v_sub_f16 v5, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_sub_f16_e64
+
+v_subrev_f16 v5, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_subrev_f16_e64
+
+v_add_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_add_f16_e64
+
+v_ldexp_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_ldexp_f16_e64
+
+v_max_num_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_max_num_f16_e64
+
+v_min_num_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_min_num_f16_e64
+
+v_mul_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_mul_f16_e64
+
+v_sub_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_sub_f16_e64
+
+v_subrev_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_subrev_f16_e64
+
+v_add_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_add_f16_e64
+
+v_ldexp_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_ldexp_f16_e64
+
+v_max_num_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_max_num_f16_e64
+
+v_min_num_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_min_num_f16_e64
+
+v_mul_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_mul_f16_e64
+
+v_sub_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_sub_f16_e64
+
+v_subrev_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_subrev_f16_e64
+
+v_add_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_add_f16_e64
+
+v_max_num_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_max_num_f16_e64
+
+v_min_num_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_min_num_f16_e64
+
+v_mul_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_mul_f16_e64
+
+v_sub_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_sub_f16_e64
+
+v_subrev_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_subrev_f16_e64
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
new file mode 100644
index 000000000000..71b2c442460f
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
@@ -0,0 +1,5983 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W32 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W64 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+
+v_add3_u32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x55,0xd6,0x01,0x05,0x0e,0x00]
+
+v_add3_u32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x55,0xd6,0xff,0x05,0xa4,0x01]
+
+v_add3_u32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x55,0xd6,0x01,0xfe,0xff,0x01]
+
+v_add3_u32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x55,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_add3_u32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x55,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_add3_u32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x55,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_add3_u32 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x55,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_add3_u32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x55,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_add3_u32 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x55,0xd6,0x7e,0x82,0xad,0x01]
+
+v_add3_u32 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x55,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_add3_u32 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x55,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_add3_u32 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x55,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_add3_u32 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x55,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_add3_u32 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x55,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_add3_u32 v255, 0xaf123456, vcc_hi, null
+// GFX12: encoding: [0xff,0x00,0x55,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_add_co_u32 v5, s6, v1, v2
+// W32: encoding: [0x05,0x06,0x00,0xd7,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s6, v255, v255
+// W32: encoding: [0x05,0x06,0x00,0xd7,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s6, s1, s2
+// W32: encoding: [0x05,0x06,0x00,0xd7,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s6, s105, s105
+// W32: encoding: [0x05,0x06,0x00,0xd7,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s6, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x06,0x00,0xd7,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s6, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x06,0x00,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s6, ttmp15, src_scc
+// W32: encoding: [0x05,0x06,0x00,0xd7,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s6, m0, 0.5
+// W32: encoding: [0x05,0x06,0x00,0xd7,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s6, exec_lo, -1
+// W32: encoding: [0x05,0x06,0x00,0xd7,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s6, exec_hi, null
+// W32: encoding: [0x05,0x06,0x00,0xd7,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s105, null, exec_lo
+// W32: encoding: [0x05,0x69,0x00,0xd7,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, vcc_lo, -1, exec_hi
+// W32: encoding: [0x05,0x6a,0x00,0xd7,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, vcc_hi, 0.5, m0
+// W32: encoding: [0x05,0x6b,0x00,0xd7,0xf0,0xfa,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x05,0x7b,0x00,0xd7,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[12:13], v1, v2
+// W64: encoding: [0x05,0x0c,0x00,0xd7,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[12:13], v255, v255
+// W64: encoding: [0x05,0x0c,0x00,0xd7,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[12:13], s1, s2
+// W64: encoding: [0x05,0x0c,0x00,0xd7,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[12:13], s105, s105
+// W64: encoding: [0x05,0x0c,0x00,0xd7,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[12:13], vcc_lo, ttmp15
+// W64: encoding: [0x05,0x0c,0x00,0xd7,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[12:13], vcc_hi, 0xaf123456
+// W64: encoding: [0x05,0x0c,0x00,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[12:13], ttmp15, src_scc
+// W64: encoding: [0x05,0x0c,0x00,0xd7,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[12:13], m0, 0.5
+// W64: encoding: [0x05,0x0c,0x00,0xd7,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[12:13], exec_lo, -1
+// W64: encoding: [0x05,0x0c,0x00,0xd7,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[12:13], exec_hi, null
+// W64: encoding: [0x05,0x0c,0x00,0xd7,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[12:13], null, exec_lo
+// W64: encoding: [0x05,0x0c,0x00,0xd7,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[104:105], -1, exec_hi
+// W64: encoding: [0x05,0x68,0x00,0xd7,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, vcc, 0.5, m0
+// W64: encoding: [0x05,0x6a,0x00,0xd7,0xf0,0xfa,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_u32 v5, ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x05,0x7a,0x00,0xd7,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v255, null, 0xaf123456, vcc_hi clamp
+// GFX12: encoding: [0xff,0xfc,0x00,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_add_lshl_u32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x47,0xd6,0x01,0x05,0x0e,0x00]
+
+v_add_lshl_u32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x47,0xd6,0xff,0x05,0xa4,0x01]
+
+v_add_lshl_u32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x47,0xd6,0x01,0xfe,0xff,0x01]
+
+v_add_lshl_u32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x47,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_add_lshl_u32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x47,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_add_lshl_u32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x47,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_add_lshl_u32 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x47,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_add_lshl_u32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x47,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_add_lshl_u32 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x47,0xd6,0x7e,0x82,0xad,0x01]
+
+v_add_lshl_u32 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x47,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_add_lshl_u32 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x47,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_add_lshl_u32 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x47,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_add_lshl_u32 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x47,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_add_lshl_u32 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x47,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_add_lshl_u32 v255, 0xaf123456, vcc_hi, null
+// GFX12: encoding: [0xff,0x00,0x47,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_add_nc_i16 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x0d,0xd7,0x01,0x05,0x02,0x00]
+
+v_add_nc_i16 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x0d,0xd7,0xff,0xff,0x03,0x00]
+
+v_add_nc_i16 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x0d,0xd7,0x01,0x04,0x00,0x00]
+
+v_add_nc_i16 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x0d,0xd7,0x69,0xd2,0x00,0x00]
+
+v_add_nc_i16 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x0d,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_add_nc_i16 v5, vcc_hi, 0xfe0b
+// GFX12: encoding: [0x05,0x00,0x0d,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_add_nc_i16 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x0d,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_add_nc_i16 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x0d,0xd7,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_add_nc_i16 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x0d,0xd7,0x7e,0x82,0x01,0x00]
+
+v_add_nc_i16 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x0d,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_add_nc_i16 v5, null, exec_lo op_sel:[1,1,1]
+// GFX12: encoding: [0x05,0x58,0x0d,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_add_nc_i16 v5, -1, exec_hi op_sel:[0,0,0]
+// GFX12: encoding: [0x05,0x00,0x0d,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_add_nc_i16 v5, 0.5, m0 op_sel:[1,0,0]
+// GFX12: encoding: [0x05,0x08,0x0d,0xd7,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_add_nc_i16 v5, src_scc, vcc_lo op_sel:[0,1,0]
+// GFX12: encoding: [0x05,0x10,0x0d,0xd7,0xfd,0xd4,0x00,0x00]
+
+v_add_nc_i16 v255, 0xfe0b, vcc_hi op_sel:[0,0,1] clamp
+// GFX12: encoding: [0xff,0xc0,0x0d,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_add_nc_i32 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x26,0xd7,0x01,0x05,0x02,0x00]
+
+v_add_nc_i32 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x26,0xd7,0xff,0xff,0x03,0x00]
+
+v_add_nc_i32 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x26,0xd7,0x01,0x04,0x00,0x00]
+
+v_add_nc_i32 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x26,0xd7,0x69,0xd2,0x00,0x00]
+
+v_add_nc_i32 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x26,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_add_nc_i32 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x26,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_add_nc_i32 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x26,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_add_nc_i32 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x26,0xd7,0x7d,0xe0,0x01,0x00]
+
+v_add_nc_i32 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x26,0xd7,0x7e,0x82,0x01,0x00]
+
+v_add_nc_i32 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x26,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_add_nc_i32 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x26,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_add_nc_i32 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x26,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_add_nc_i32 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x26,0xd7,0xf0,0xfa,0x00,0x00]
+
+v_add_nc_i32 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x26,0xd7,0xfd,0xd4,0x00,0x00]
+
+v_add_nc_i32 v255, 0xaf123456, vcc_hi clamp
+// GFX12: encoding: [0xff,0x80,0x26,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_add_nc_u16 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x03,0xd7,0x01,0x05,0x02,0x00]
+
+v_add_nc_u16 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x03,0xd7,0xff,0xff,0x03,0x00]
+
+v_add_nc_u16 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x03,0xd7,0x01,0x04,0x00,0x00]
+
+v_add_nc_u16 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x03,0xd7,0x69,0xd2,0x00,0x00]
+
+v_add_nc_u16 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x03,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_add_nc_u16 v5, vcc_hi, 0xfe0b
+// GFX12: encoding: [0x05,0x00,0x03,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_add_nc_u16 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x03,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_add_nc_u16 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x03,0xd7,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_add_nc_u16 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x03,0xd7,0x7e,0x82,0x01,0x00]
+
+v_add_nc_u16 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x03,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_add_nc_u16 v5, null, exec_lo op_sel:[1,1,1]
+// GFX12: encoding: [0x05,0x58,0x03,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_add_nc_u16 v5, -1, exec_hi op_sel:[0,0,0]
+// GFX12: encoding: [0x05,0x00,0x03,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_add_nc_u16 v5, 0.5, m0 op_sel:[1,0,0]
+// GFX12: encoding: [0x05,0x08,0x03,0xd7,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_add_nc_u16 v5, src_scc, vcc_lo op_sel:[0,1,0]
+// GFX12: encoding: [0x05,0x10,0x03,0xd7,0xfd,0xd4,0x00,0x00]
+
+v_add_nc_u16 v255, 0xfe0b, vcc_hi op_sel:[0,0,1] clamp
+// GFX12: encoding: [0xff,0xc0,0x03,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_alignbit_b32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x16,0xd6,0x01,0x05,0x0e,0x00]
+
+v_alignbit_b32 v5, v255, s2, s3
+// GFX12: encoding: [0x05,0x00,0x16,0xd6,0xff,0x05,0x0c,0x00]
+
+v_alignbit_b32 v5, s1, v255, s3
+// GFX12: encoding: [0x05,0x00,0x16,0xd6,0x01,0xfe,0x0f,0x00]
+
+v_alignbit_b32 v5, s105, s105, s105
+// GFX12: encoding: [0x05,0x00,0x16,0xd6,0x69,0xd2,0xa4,0x01]
+
+v_alignbit_b32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x16,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_alignbit_b32 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x16,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_alignbit_b32 v5, m0, 0.5, exec_lo
+// GFX12: encoding: [0x05,0x00,0x16,0xd6,0x7d,0xe0,0xf9,0x01]
+
+v_alignbit_b32 v5, exec_lo, -1, m0
+// GFX12: encoding: [0x05,0x00,0x16,0xd6,0x7e,0x82,0xf5,0x01]
+
+v_alignbit_b32 v5, exec_hi, null, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x16,0xd6,0x7f,0xf8,0xac,0x01]
+
+v_alignbit_b32 v5, null, exec_lo, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x16,0xd6,0x7c,0xfc,0xa8,0x01]
+
+v_alignbit_b32 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x16,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_alignbit_b32 v5, 0.5, m0, exec_hi
+// GFX12: encoding: [0x05,0x00,0x16,0xd6,0xf0,0xfa,0xfc,0x01]
+
+v_alignbit_b32 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x16,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_alignbit_b32 v255, 0xaf123456, vcc_hi, null
+// GFX12: encoding: [0xff,0x00,0x16,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_alignbyte_b32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x17,0xd6,0x01,0x05,0x0e,0x00]
+
+v_alignbyte_b32 v5, v255, s2, s3
+// GFX12: encoding: [0x05,0x00,0x17,0xd6,0xff,0x05,0x0c,0x00]
+
+v_alignbyte_b32 v5, s1, v255, s3
+// GFX12: encoding: [0x05,0x00,0x17,0xd6,0x01,0xfe,0x0f,0x00]
+
+v_alignbyte_b32 v5, s105, s105, s105
+// GFX12: encoding: [0x05,0x00,0x17,0xd6,0x69,0xd2,0xa4,0x01]
+
+v_alignbyte_b32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x17,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_alignbyte_b32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x17,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_alignbyte_b32 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x17,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_alignbyte_b32 v5, m0, 0.5, exec_lo
+// GFX12: encoding: [0x05,0x00,0x17,0xd6,0x7d,0xe0,0xf9,0x01]
+
+v_alignbyte_b32 v5, exec_lo, -1, m0
+// GFX12: encoding: [0x05,0x00,0x17,0xd6,0x7e,0x82,0xf5,0x01]
+
+v_alignbyte_b32 v5, exec_hi, null, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x17,0xd6,0x7f,0xf8,0xac,0x01]
+
+v_alignbyte_b32 v5, null, exec_lo, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x17,0xd6,0x7c,0xfc,0xa8,0x01]
+
+v_alignbyte_b32 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x17,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_alignbyte_b32 v5, 0.5, m0, exec_hi
+// GFX12: encoding: [0x05,0x00,0x17,0xd6,0xf0,0xfa,0xfc,0x01]
+
+v_alignbyte_b32 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x17,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_alignbyte_b32 v255, 0xaf123456, vcc_hi, null
+// GFX12: encoding: [0xff,0x00,0x17,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_and_b16 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x62,0xd7,0x01,0x05,0x02,0x00]
+
+v_and_b16 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x62,0xd7,0xff,0xff,0x03,0x00]
+
+v_and_b16 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x62,0xd7,0x01,0x04,0x00,0x00]
+
+v_and_b16 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x62,0xd7,0x69,0xd2,0x00,0x00]
+
+v_and_b16 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x62,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_and_b16 v5, vcc_hi, 0xfe0b
+// GFX12: encoding: [0x05,0x00,0x62,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_and_b16 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x62,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_and_b16 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x62,0xd7,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_and_b16 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x62,0xd7,0x7e,0x82,0x01,0x00]
+
+v_and_b16 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x62,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_and_b16 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x62,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_and_b16 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x62,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_and_b16 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x62,0xd7,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_and_b16 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x62,0xd7,0xfd,0xd4,0x00,0x00]
+
+v_and_b16 v255, 0xfe0b, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x62,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_and_or_b32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x57,0xd6,0x01,0x05,0x0e,0x00]
+
+v_and_or_b32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x57,0xd6,0xff,0x05,0xa4,0x01]
+
+v_and_or_b32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x57,0xd6,0x01,0xfe,0xff,0x01]
+
+v_and_or_b32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x57,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_and_or_b32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x57,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_and_or_b32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x57,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_and_or_b32 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x57,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_and_or_b32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x57,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_and_or_b32 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x57,0xd6,0x7e,0x82,0xad,0x01]
+
+v_and_or_b32 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x57,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_and_or_b32 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x57,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_and_or_b32 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x57,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_and_or_b32 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x57,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_and_or_b32 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x57,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_and_or_b32 v255, 0xaf123456, vcc_hi, null
+// GFX12: encoding: [0xff,0x00,0x57,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_ashrrev_i16 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x3a,0xd7,0x01,0x05,0x02,0x00]
+
+v_ashrrev_i16 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x3a,0xd7,0xff,0xff,0x03,0x00]
+
+v_ashrrev_i16 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x3a,0xd7,0x01,0x04,0x00,0x00]
+
+v_ashrrev_i16 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x3a,0xd7,0x69,0xd2,0x00,0x00]
+
+v_ashrrev_i16 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x3a,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_ashrrev_i16 v5, vcc_hi, 0xfe0b
+// GFX12: encoding: [0x05,0x00,0x3a,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_ashrrev_i16 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x3a,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_ashrrev_i16 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x3a,0xd7,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_ashrrev_i16 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x3a,0xd7,0x7e,0x82,0x01,0x00]
+
+v_ashrrev_i16 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x3a,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_ashrrev_i16 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x3a,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_ashrrev_i16 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x3a,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_ashrrev_i16 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x3a,0xd7,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_ashrrev_i16 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x3a,0xd7,0xfd,0xd4,0x00,0x00]
+
+v_ashrrev_i16 v255, 0xfe0b, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x3a,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_ashrrev_i64 v[5:6], v1, vcc
+// GFX12: encoding: [0x05,0x00,0x3e,0xd7,0x01,0xd5,0x00,0x00]
+
+v_ashrrev_i64 v[5:6], v255, exec
+// GFX12: encoding: [0x05,0x00,0x3e,0xd7,0xff,0xfd,0x00,0x00]
+
+v_ashrrev_i64 v[5:6], exec_lo, v[2:3]
+// GFX12: encoding: [0x05,0x00,0x3e,0xd7,0x7e,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], exec_hi, v[254:255]
+// GFX12: encoding: [0x05,0x00,0x3e,0xd7,0x7f,0xfc,0x03,0x00]
+
+v_ashrrev_i64 v[5:6], null, null
+// GFX12: encoding: [0x05,0x00,0x3e,0xd7,0x7c,0xf8,0x00,0x00]
+
+v_ashrrev_i64 v[5:6], -1, -1
+// GFX12: encoding: [0x05,0x00,0x3e,0xd7,0xc1,0x82,0x01,0x00]
+
+v_ashrrev_i64 v[5:6], 0.5, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x3e,0xd7,0xf0,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_ashrrev_i64 v[5:6], src_scc, src_scc
+// GFX12: encoding: [0x05,0x00,0x3e,0xd7,0xfd,0xfa,0x01,0x00]
+
+v_ashrrev_i64 v[254:255], 0xaf123456, 0.5
+// GFX12: encoding: [0xfe,0x00,0x3e,0xd7,0xff,0xe0,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_bcnt_u32_b32 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x1e,0xd7,0x01,0x05,0x02,0x00]
+
+v_bcnt_u32_b32 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x1e,0xd7,0xff,0xff,0x03,0x00]
+
+v_bcnt_u32_b32 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x1e,0xd7,0x01,0x04,0x00,0x00]
+
+v_bcnt_u32_b32 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x1e,0xd7,0x69,0xd2,0x00,0x00]
+
+v_bcnt_u32_b32 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x1e,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_bcnt_u32_b32 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x1e,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_bcnt_u32_b32 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x1e,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_bcnt_u32_b32 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x1e,0xd7,0x7d,0xe0,0x01,0x00]
+
+v_bcnt_u32_b32 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x1e,0xd7,0x7e,0x82,0x01,0x00]
+
+v_bcnt_u32_b32 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x1e,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_bcnt_u32_b32 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x1e,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_bcnt_u32_b32 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x1e,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_bcnt_u32_b32 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x1e,0xd7,0xf0,0xfa,0x00,0x00]
+
+v_bcnt_u32_b32 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x1e,0xd7,0xfd,0xd4,0x00,0x00]
+
+v_bcnt_u32_b32 v255, 0xaf123456, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x1e,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_bfe_i32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x11,0xd6,0x01,0x05,0x0e,0x00]
+
+v_bfe_i32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x11,0xd6,0xff,0x05,0xa4,0x01]
+
+v_bfe_i32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x11,0xd6,0x01,0xfe,0xff,0x01]
+
+v_bfe_i32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x11,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_bfe_i32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x11,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_bfe_i32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x11,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_bfe_i32 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x11,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_bfe_i32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x11,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_bfe_i32 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x11,0xd6,0x7e,0x82,0xad,0x01]
+
+v_bfe_i32 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x11,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_bfe_i32 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x11,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_bfe_i32 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x11,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_bfe_i32 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x11,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_bfe_i32 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x11,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_bfe_i32 v255, 0xaf123456, vcc_hi, null
+// GFX12: encoding: [0xff,0x00,0x11,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_bfe_u32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x10,0xd6,0x01,0x05,0x0e,0x00]
+
+v_bfe_u32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x10,0xd6,0xff,0x05,0xa4,0x01]
+
+v_bfe_u32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x10,0xd6,0x01,0xfe,0xff,0x01]
+
+v_bfe_u32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x10,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_bfe_u32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x10,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_bfe_u32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x10,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_bfe_u32 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x10,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_bfe_u32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x10,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_bfe_u32 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x10,0xd6,0x7e,0x82,0xad,0x01]
+
+v_bfe_u32 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x10,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_bfe_u32 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x10,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_bfe_u32 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x10,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_bfe_u32 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x10,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_bfe_u32 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x10,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_bfe_u32 v255, 0xaf123456, vcc_hi, null
+// GFX12: encoding: [0xff,0x00,0x10,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_bfi_b32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x12,0xd6,0x01,0x05,0x0e,0x00]
+
+v_bfi_b32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x12,0xd6,0xff,0x05,0xa4,0x01]
+
+v_bfi_b32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x12,0xd6,0x01,0xfe,0xff,0x01]
+
+v_bfi_b32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x12,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_bfi_b32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x12,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_bfi_b32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x12,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_bfi_b32 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x12,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_bfi_b32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x12,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_bfi_b32 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x12,0xd6,0x7e,0x82,0xad,0x01]
+
+v_bfi_b32 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x12,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_bfi_b32 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x12,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_bfi_b32 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x12,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_bfi_b32 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x12,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_bfi_b32 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x12,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_bfi_b32 v255, 0xaf123456, vcc_hi, null
+// GFX12: encoding: [0xff,0x00,0x12,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_bfm_b32 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x1d,0xd7,0x01,0x05,0x02,0x00]
+
+v_bfm_b32 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x1d,0xd7,0xff,0xff,0x03,0x00]
+
+v_bfm_b32 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x1d,0xd7,0x01,0x04,0x00,0x00]
+
+v_bfm_b32 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x1d,0xd7,0x69,0xd2,0x00,0x00]
+
+v_bfm_b32 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x1d,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_bfm_b32 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x1d,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_bfm_b32 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x1d,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_bfm_b32 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x1d,0xd7,0x7d,0xe0,0x01,0x00]
+
+v_bfm_b32 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x1d,0xd7,0x7e,0x82,0x01,0x00]
+
+v_bfm_b32 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x1d,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_bfm_b32 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x1d,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_bfm_b32 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x1d,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_bfm_b32 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x1d,0xd7,0xf0,0xfa,0x00,0x00]
+
+v_bfm_b32 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x1d,0xd7,0xfd,0xd4,0x00,0x00]
+
+v_bfm_b32 v255, 0xaf123456, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x1d,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cndmask_b16 v5, v1, src_scc, s3
+// W32: encoding: [0x05,0x00,0x5d,0xd6,0x01,0xfb,0x0d,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16 v5, v255, 0.5, s3
+// W32: encoding: [0x05,0x00,0x5d,0xd6,0xff,0xff,0x0d,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16 v5, s105, s105, s3
+// W32: encoding: [0x05,0x00,0x5d,0xd6,0x69,0xd2,0x0c,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16 v5, vcc_hi, v2, s3
+// W32: encoding: [0x05,0x00,0x5d,0xd6,0x6b,0x04,0x0e,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16 v5, ttmp15, ttmp15, s3
+// W32: encoding: [0x05,0x00,0x5d,0xd6,0x7b,0xf6,0x0c,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16 v5, m0, v255, s3
+// W32: encoding: [0x05,0x00,0x5d,0xd6,0x7d,0xfe,0x0f,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16 v5, exec_lo, exec_lo, s3
+// W32: encoding: [0x05,0x00,0x5d,0xd6,0x7e,0xfc,0x0c,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16 v5, exec_hi, exec_hi, s3
+// W32: encoding: [0x05,0x00,0x5d,0xd6,0x7f,0xfe,0x0c,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16 v5, null, m0, s105
+// W32: encoding: [0x05,0x00,0x5d,0xd6,0x7c,0xfa,0xa4,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16 v5, -1, -|vcc_lo|, vcc_lo
+// W32: encoding: [0x05,0x02,0x5d,0xd6,0xc1,0xd4,0xa8,0x41]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16 v5, 0.5, -1, vcc_hi
+// W32: encoding: [0x05,0x00,0x5d,0xd6,0xff,0x82,0xad,0x01,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16 v5, -|src_scc|, null, ttmp15
+// W32: encoding: [0x05,0x01,0x5d,0xd6,0xfd,0xf8,0xec,0x21]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16 v5, v1, src_scc, s[6:7]
+// W64: encoding: [0x05,0x00,0x5d,0xd6,0x01,0xfb,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16 v5, v255, 0.5, s[6:7]
+// W64: encoding: [0x05,0x00,0x5d,0xd6,0xff,0xff,0x19,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16 v5, s105, s105, s[6:7]
+// W64: encoding: [0x05,0x00,0x5d,0xd6,0x69,0xd2,0x18,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16 v5, vcc_hi, v2, s[6:7]
+// W64: encoding: [0x05,0x00,0x5d,0xd6,0x6b,0x04,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16 v5, ttmp15, ttmp15, s[6:7]
+// W64: encoding: [0x05,0x00,0x5d,0xd6,0x7b,0xf6,0x18,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16 v5, m0, v255, s[6:7]
+// W64: encoding: [0x05,0x00,0x5d,0xd6,0x7d,0xfe,0x1b,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16 v5, exec_lo, exec_lo, s[6:7]
+// W64: encoding: [0x05,0x00,0x5d,0xd6,0x7e,0xfc,0x18,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16 v5, exec_hi, exec_hi, s[6:7]
+// W64: encoding: [0x05,0x00,0x5d,0xd6,0x7f,0xfe,0x18,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16 v5, null, m0, s[6:7]
+// W64: encoding: [0x05,0x00,0x5d,0xd6,0x7c,0xfa,0x18,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16 v5, -1, -|vcc_lo|, s[104:105]
+// W64: encoding: [0x05,0x02,0x5d,0xd6,0xc1,0xd4,0xa0,0x41]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16 v5, 0.5, -1, vcc
+// W64: encoding: [0x05,0x00,0x5d,0xd6,0xff,0x82,0xa9,0x01,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16 v5, -|src_scc|, null, ttmp[14:15]
+// W64: encoding: [0x05,0x01,0x5d,0xd6,0xfd,0xf8,0xe8,0x21]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16 v255, -|0xfe0b|, -|vcc_hi|, null
+// GFX12: encoding: [0xff,0x03,0x5d,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
+
+v_cubeid_f32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x0c,0xd6,0x01,0x05,0x0e,0x00]
+
+v_cubeid_f32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x0c,0xd6,0xff,0x05,0xa4,0x01]
+
+v_cubeid_f32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x0c,0xd6,0x01,0xfe,0xff,0x01]
+
+v_cubeid_f32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x0c,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_cubeid_f32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x0c,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_cubeid_f32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x0c,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_cubeid_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15|
+// GFX12: encoding: [0x05,0x07,0x0c,0xd6,0x7b,0xfa,0xed,0xe1]
+
+v_cubeid_f32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x0c,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_cubeid_f32 v5, |exec_lo|, -1, vcc_hi
+// GFX12: encoding: [0x05,0x01,0x0c,0xd6,0x7e,0x82,0xad,0x01]
+
+v_cubeid_f32 v5, -|exec_hi|, null, -|vcc_lo|
+// GFX12: encoding: [0x05,0x05,0x0c,0xd6,0x7f,0xf8,0xa8,0xa1]
+
+v_cubeid_f32 v5, null, exec_lo, -|0xaf123456|
+// GFX12: encoding: [0x05,0x04,0x0c,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+
+v_cubeid_f32 v5, -1, -|exec_hi|, -|src_scc|
+// GFX12: encoding: [0x05,0x06,0x0c,0xd6,0xc1,0xfe,0xf4,0xc3]
+
+v_cubeid_f32 v5, 0.5, -m0, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x0c,0xd6,0xf0,0xfa,0xc0,0x4b]
+
+v_cubeid_f32 v5, -src_scc, |vcc_lo|, -1 mul:4
+// GFX12: encoding: [0x05,0x02,0x0c,0xd6,0xfd,0xd4,0x04,0x33]
+
+v_cubeid_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2
+// GFX12: encoding: [0xff,0x83,0x0c,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+
+v_cubema_f32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x0f,0xd6,0x01,0x05,0x0e,0x00]
+
+v_cubema_f32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x0f,0xd6,0xff,0x05,0xa4,0x01]
+
+v_cubema_f32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x0f,0xd6,0x01,0xfe,0xff,0x01]
+
+v_cubema_f32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x0f,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_cubema_f32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x0f,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_cubema_f32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x0f,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_cubema_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15|
+// GFX12: encoding: [0x05,0x07,0x0f,0xd6,0x7b,0xfa,0xed,0xe1]
+
+v_cubema_f32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x0f,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_cubema_f32 v5, |exec_lo|, -1, vcc_hi
+// GFX12: encoding: [0x05,0x01,0x0f,0xd6,0x7e,0x82,0xad,0x01]
+
+v_cubema_f32 v5, -|exec_hi|, null, -|vcc_lo|
+// GFX12: encoding: [0x05,0x05,0x0f,0xd6,0x7f,0xf8,0xa8,0xa1]
+
+v_cubema_f32 v5, null, exec_lo, -|0xaf123456|
+// GFX12: encoding: [0x05,0x04,0x0f,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+
+v_cubema_f32 v5, -1, -|exec_hi|, -|src_scc|
+// GFX12: encoding: [0x05,0x06,0x0f,0xd6,0xc1,0xfe,0xf4,0xc3]
+
+v_cubema_f32 v5, 0.5, -m0, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x0f,0xd6,0xf0,0xfa,0xc0,0x4b]
+
+v_cubema_f32 v5, -src_scc, |vcc_lo|, -1 mul:4
+// GFX12: encoding: [0x05,0x02,0x0f,0xd6,0xfd,0xd4,0x04,0x33]
+
+v_cubema_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2
+// GFX12: encoding: [0xff,0x83,0x0f,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+
+v_cubesc_f32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x0d,0xd6,0x01,0x05,0x0e,0x00]
+
+v_cubesc_f32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x0d,0xd6,0xff,0x05,0xa4,0x01]
+
+v_cubesc_f32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x0d,0xd6,0x01,0xfe,0xff,0x01]
+
+v_cubesc_f32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x0d,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_cubesc_f32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x0d,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_cubesc_f32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x0d,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_cubesc_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15|
+// GFX12: encoding: [0x05,0x07,0x0d,0xd6,0x7b,0xfa,0xed,0xe1]
+
+v_cubesc_f32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x0d,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_cubesc_f32 v5, |exec_lo|, -1, vcc_hi
+// GFX12: encoding: [0x05,0x01,0x0d,0xd6,0x7e,0x82,0xad,0x01]
+
+v_cubesc_f32 v5, -|exec_hi|, null, -|vcc_lo|
+// GFX12: encoding: [0x05,0x05,0x0d,0xd6,0x7f,0xf8,0xa8,0xa1]
+
+v_cubesc_f32 v5, null, exec_lo, -|0xaf123456|
+// GFX12: encoding: [0x05,0x04,0x0d,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+
+v_cubesc_f32 v5, -1, -|exec_hi|, -|src_scc|
+// GFX12: encoding: [0x05,0x06,0x0d,0xd6,0xc1,0xfe,0xf4,0xc3]
+
+v_cubesc_f32 v5, 0.5, -m0, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x0d,0xd6,0xf0,0xfa,0xc0,0x4b]
+
+v_cubesc_f32 v5, -src_scc, |vcc_lo|, -1 mul:4
+// GFX12: encoding: [0x05,0x02,0x0d,0xd6,0xfd,0xd4,0x04,0x33]
+
+v_cubesc_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2
+// GFX12: encoding: [0xff,0x83,0x0d,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+
+v_cubetc_f32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x0e,0xd6,0x01,0x05,0x0e,0x00]
+
+v_cubetc_f32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x0e,0xd6,0xff,0x05,0xa4,0x01]
+
+v_cubetc_f32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x0e,0xd6,0x01,0xfe,0xff,0x01]
+
+v_cubetc_f32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x0e,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_cubetc_f32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x0e,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_cubetc_f32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x0e,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_cubetc_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15|
+// GFX12: encoding: [0x05,0x07,0x0e,0xd6,0x7b,0xfa,0xed,0xe1]
+
+v_cubetc_f32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x0e,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_cubetc_f32 v5, |exec_lo|, -1, vcc_hi
+// GFX12: encoding: [0x05,0x01,0x0e,0xd6,0x7e,0x82,0xad,0x01]
+
+v_cubetc_f32 v5, -|exec_hi|, null, -|vcc_lo|
+// GFX12: encoding: [0x05,0x05,0x0e,0xd6,0x7f,0xf8,0xa8,0xa1]
+
+v_cubetc_f32 v5, null, exec_lo, -|0xaf123456|
+// GFX12: encoding: [0x05,0x04,0x0e,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+
+v_cubetc_f32 v5, -1, -|exec_hi|, -|src_scc|
+// GFX12: encoding: [0x05,0x06,0x0e,0xd6,0xc1,0xfe,0xf4,0xc3]
+
+v_cubetc_f32 v5, 0.5, -m0, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x0e,0xd6,0xf0,0xfa,0xc0,0x4b]
+
+v_cubetc_f32 v5, -src_scc, |vcc_lo|, -1 mul:4
+// GFX12: encoding: [0x05,0x02,0x0e,0xd6,0xfd,0xd4,0x04,0x33]
+
+v_cubetc_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2
+// GFX12: encoding: [0xff,0x83,0x0e,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+
+v_cvt_pk_i16_f32 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x06,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_i16_f32 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x06,0xd7,0xff,0xff,0x03,0x00]
+
+v_cvt_pk_i16_f32 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x06,0xd7,0x01,0x04,0x00,0x00]
+
+v_cvt_pk_i16_f32 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x06,0xd7,0x69,0xd2,0x00,0x00]
+
+v_cvt_pk_i16_f32 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x06,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_cvt_pk_i16_f32 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x06,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cvt_pk_i16_f32 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x06,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_cvt_pk_i16_f32 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x06,0xd7,0x7d,0xe0,0x01,0x00]
+
+v_cvt_pk_i16_f32 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x06,0xd7,0x7e,0x82,0x01,0x00]
+
+v_cvt_pk_i16_f32 v5, |exec_hi|, null
+// GFX12: encoding: [0x05,0x01,0x06,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_cvt_pk_i16_f32 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x06,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_cvt_pk_i16_f32 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x06,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_cvt_pk_i16_f32 v5, 0.5, -m0
+// GFX12: encoding: [0x05,0x00,0x06,0xd7,0xf0,0xfa,0x00,0x40]
+
+v_cvt_pk_i16_f32 v5, -src_scc, |vcc_lo|
+// GFX12: encoding: [0x05,0x02,0x06,0xd7,0xfd,0xd4,0x00,0x20]
+
+v_cvt_pk_i16_f32 v255, -|0xaf123456|, -|vcc_hi|
+// GFX12: encoding: [0xff,0x03,0x06,0xd7,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cvt_pk_i16_i32 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x24,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x24,0xd7,0xff,0xff,0x03,0x00]
+
+v_cvt_pk_i16_i32 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x24,0xd7,0x01,0x04,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x24,0xd7,0x69,0xd2,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x24,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x24,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cvt_pk_i16_i32 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x24,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_cvt_pk_i16_i32 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x24,0xd7,0x7d,0xe0,0x01,0x00]
+
+v_cvt_pk_i16_i32 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x24,0xd7,0x7e,0x82,0x01,0x00]
+
+v_cvt_pk_i16_i32 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x24,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x24,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x24,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x24,0xd7,0xf0,0xfa,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x24,0xd7,0xfd,0xd4,0x00,0x00]
+
+v_cvt_pk_i16_i32 v255, 0xaf123456, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x24,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cvt_pk_norm_i16_f16 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x12,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_norm_i16_f16 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x12,0xd7,0xff,0xff,0x03,0x00]
+
+v_cvt_pk_norm_i16_f16 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x12,0xd7,0x01,0x04,0x00,0x00]
+
+v_cvt_pk_norm_i16_f16 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x12,0xd7,0x69,0xd2,0x00,0x00]
+
+v_cvt_pk_norm_i16_f16 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x12,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_cvt_pk_norm_i16_f16 v5, vcc_hi, 0xfe0b
+// GFX12: encoding: [0x05,0x00,0x12,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cvt_pk_norm_i16_f16 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x12,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_cvt_pk_norm_i16_f16 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x12,0xd7,0x7d,0xe0,0x01,0x00]
+
+v_cvt_pk_norm_i16_f16 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x12,0xd7,0x7e,0x82,0x01,0x00]
+
+v_cvt_pk_norm_i16_f16 v5, |exec_hi|, null
+// GFX12: encoding: [0x05,0x01,0x12,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_cvt_pk_norm_i16_f16 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x12,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_cvt_pk_norm_i16_f16 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x12,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_cvt_pk_norm_i16_f16 v5, 0.5, -m0 op_sel:[0,0,0]
+// GFX12: encoding: [0x05,0x00,0x12,0xd7,0xf0,0xfa,0x00,0x40]
+
+v_cvt_pk_norm_i16_f16 v5, -src_scc, |vcc_lo| op_sel:[1,0,0]
+// GFX12: encoding: [0x05,0x0a,0x12,0xd7,0xfd,0xd4,0x00,0x20]
+
+v_cvt_pk_norm_i16_f16 v255, -|0xfe0b|, -|vcc_hi| op_sel:[0,1,0]
+// GFX12: encoding: [0xff,0x13,0x12,0xd7,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cvt_pk_norm_u16_f16 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x13,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_norm_u16_f16 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x13,0xd7,0xff,0xff,0x03,0x00]
+
+v_cvt_pk_norm_u16_f16 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x13,0xd7,0x01,0x04,0x00,0x00]
+
+v_cvt_pk_norm_u16_f16 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x13,0xd7,0x69,0xd2,0x00,0x00]
+
+v_cvt_pk_norm_u16_f16 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x13,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_cvt_pk_norm_u16_f16 v5, vcc_hi, 0xfe0b
+// GFX12: encoding: [0x05,0x00,0x13,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cvt_pk_norm_u16_f16 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x13,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_cvt_pk_norm_u16_f16 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x13,0xd7,0x7d,0xe0,0x01,0x00]
+
+v_cvt_pk_norm_u16_f16 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x13,0xd7,0x7e,0x82,0x01,0x00]
+
+v_cvt_pk_norm_u16_f16 v5, |exec_hi|, null
+// GFX12: encoding: [0x05,0x01,0x13,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_cvt_pk_norm_u16_f16 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x13,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_cvt_pk_norm_u16_f16 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x13,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_cvt_pk_norm_u16_f16 v5, 0.5, -m0 op_sel:[0,0,0]
+// GFX12: encoding: [0x05,0x00,0x13,0xd7,0xf0,0xfa,0x00,0x40]
+
+v_cvt_pk_norm_u16_f16 v5, -src_scc, |vcc_lo| op_sel:[1,0,0]
+// GFX12: encoding: [0x05,0x0a,0x13,0xd7,0xfd,0xd4,0x00,0x20]
+
+v_cvt_pk_norm_u16_f16 v255, -|0xfe0b|, -|vcc_hi| op_sel:[0,1,0]
+// GFX12: encoding: [0xff,0x13,0x13,0xd7,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cvt_pk_u16_f32 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x07,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_u16_f32 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x07,0xd7,0xff,0xff,0x03,0x00]
+
+v_cvt_pk_u16_f32 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x07,0xd7,0x01,0x04,0x00,0x00]
+
+v_cvt_pk_u16_f32 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x07,0xd7,0x69,0xd2,0x00,0x00]
+
+v_cvt_pk_u16_f32 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x07,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_cvt_pk_u16_f32 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x07,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cvt_pk_u16_f32 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x07,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_cvt_pk_u16_f32 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x07,0xd7,0x7d,0xe0,0x01,0x00]
+
+v_cvt_pk_u16_f32 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x07,0xd7,0x7e,0x82,0x01,0x00]
+
+v_cvt_pk_u16_f32 v5, |exec_hi|, null
+// GFX12: encoding: [0x05,0x01,0x07,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_cvt_pk_u16_f32 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x07,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_cvt_pk_u16_f32 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x07,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_cvt_pk_u16_f32 v5, 0.5, -m0
+// GFX12: encoding: [0x05,0x00,0x07,0xd7,0xf0,0xfa,0x00,0x40]
+
+v_cvt_pk_u16_f32 v5, -src_scc, |vcc_lo|
+// GFX12: encoding: [0x05,0x02,0x07,0xd7,0xfd,0xd4,0x00,0x20]
+
+v_cvt_pk_u16_f32 v255, -|0xaf123456|, -|vcc_hi|
+// GFX12: encoding: [0xff,0x03,0x07,0xd7,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cvt_pk_u16_u32 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x23,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x23,0xd7,0xff,0xff,0x03,0x00]
+
+v_cvt_pk_u16_u32 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x23,0xd7,0x01,0x04,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x23,0xd7,0x69,0xd2,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x23,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x23,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cvt_pk_u16_u32 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x23,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_cvt_pk_u16_u32 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x23,0xd7,0x7d,0xe0,0x01,0x00]
+
+v_cvt_pk_u16_u32 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x23,0xd7,0x7e,0x82,0x01,0x00]
+
+v_cvt_pk_u16_u32 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x23,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x23,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x23,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x23,0xd7,0xf0,0xfa,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x23,0xd7,0xfd,0xd4,0x00,0x00]
+
+v_cvt_pk_u16_u32 v255, 0xaf123456, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x23,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cvt_pk_u8_f32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x26,0xd6,0x01,0x05,0x0e,0x00]
+
+v_cvt_pk_u8_f32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x26,0xd6,0xff,0x05,0xa4,0x01]
+
+v_cvt_pk_u8_f32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x26,0xd6,0x01,0xfe,0xff,0x01]
+
+v_cvt_pk_u8_f32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x26,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_cvt_pk_u8_f32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x26,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x26,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_cvt_pk_u8_f32 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x26,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_cvt_pk_u8_f32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x26,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_cvt_pk_u8_f32 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x26,0xd6,0x7e,0x82,0xad,0x01]
+
+v_cvt_pk_u8_f32 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x26,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_cvt_pk_u8_f32 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x26,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_cvt_pk_u8_f32 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x26,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_cvt_pk_u8_f32 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x26,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_cvt_pk_u8_f32 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x26,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_cvt_pk_u8_f32 v255, -|0xaf123456|, vcc_hi, null
+// GFX12: encoding: [0xff,0x01,0x26,0xd6,0xff,0xd6,0xf0,0x21,0x56,0x34,0x12,0xaf]
+
+v_cvt_pk_norm_i16_f16 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x12,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_norm_i16_f16 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x12,0xd7,0xff,0xff,0x03,0x00]
+
+v_cvt_pk_norm_i16_f16 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x12,0xd7,0x01,0x04,0x00,0x00]
+
+v_cvt_pk_norm_i16_f16 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x12,0xd7,0x69,0xd2,0x00,0x00]
+
+v_cvt_pk_norm_i16_f16 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x12,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_cvt_pk_norm_i16_f16 v5, vcc_hi, 0xfe0b
+// GFX12: encoding: [0x05,0x00,0x12,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cvt_pk_norm_i16_f16 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x12,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_cvt_pk_norm_i16_f16 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x12,0xd7,0x7d,0xe0,0x01,0x00]
+
+v_cvt_pk_norm_i16_f16 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x12,0xd7,0x7e,0x82,0x01,0x00]
+
+v_cvt_pk_norm_i16_f16 v5, |exec_hi|, null
+// GFX12: encoding: [0x05,0x01,0x12,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_cvt_pk_norm_i16_f16 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x12,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_cvt_pk_norm_i16_f16 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x12,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_cvt_pk_norm_i16_f16 v5, 0.5, -m0 op_sel:[0,0,0]
+// GFX12: encoding: [0x05,0x00,0x12,0xd7,0xf0,0xfa,0x00,0x40]
+
+v_cvt_pk_norm_i16_f16 v5, -src_scc, |vcc_lo| op_sel:[1,0,0]
+// GFX12: encoding: [0x05,0x0a,0x12,0xd7,0xfd,0xd4,0x00,0x20]
+
+v_cvt_pk_norm_i16_f16 v255, -|0xfe0b|, -|vcc_hi| op_sel:[0,1,0]
+// GFX12: encoding: [0xff,0x13,0x12,0xd7,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cvt_pk_norm_i16_f32 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x21,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_norm_i16_f32 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x21,0xd7,0xff,0xff,0x03,0x00]
+
+v_cvt_pk_norm_i16_f32 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x21,0xd7,0x01,0x04,0x00,0x00]
+
+v_cvt_pk_norm_i16_f32 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x21,0xd7,0x69,0xd2,0x00,0x00]
+
+v_cvt_pk_norm_i16_f32 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x21,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_cvt_pk_norm_i16_f32 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x21,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cvt_pk_norm_i16_f32 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x21,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_cvt_pk_norm_i16_f32 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x21,0xd7,0x7d,0xe0,0x01,0x00]
+
+v_cvt_pk_norm_i16_f32 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x21,0xd7,0x7e,0x82,0x01,0x00]
+
+v_cvt_pk_norm_i16_f32 v5, |exec_hi|, null
+// GFX12: encoding: [0x05,0x01,0x21,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_cvt_pk_norm_i16_f32 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x21,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_cvt_pk_norm_i16_f32 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x21,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_cvt_pk_norm_i16_f32 v5, 0.5, -m0
+// GFX12: encoding: [0x05,0x00,0x21,0xd7,0xf0,0xfa,0x00,0x40]
+
+v_cvt_pk_norm_i16_f32 v5, -src_scc, |vcc_lo|
+// GFX12: encoding: [0x05,0x02,0x21,0xd7,0xfd,0xd4,0x00,0x20]
+
+v_cvt_pk_norm_i16_f32 v255, -|0xaf123456|, -|vcc_hi|
+// GFX12: encoding: [0xff,0x03,0x21,0xd7,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cvt_pk_norm_u16_f16 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x13,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_norm_u16_f16 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x13,0xd7,0xff,0xff,0x03,0x00]
+
+v_cvt_pk_norm_u16_f16 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x13,0xd7,0x01,0x04,0x00,0x00]
+
+v_cvt_pk_norm_u16_f16 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x13,0xd7,0x69,0xd2,0x00,0x00]
+
+v_cvt_pk_norm_u16_f16 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x13,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_cvt_pk_norm_u16_f16 v5, vcc_hi, 0xfe0b
+// GFX12: encoding: [0x05,0x00,0x13,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cvt_pk_norm_u16_f16 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x13,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_cvt_pk_norm_u16_f16 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x13,0xd7,0x7d,0xe0,0x01,0x00]
+
+v_cvt_pk_norm_u16_f16 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x13,0xd7,0x7e,0x82,0x01,0x00]
+
+v_cvt_pk_norm_u16_f16 v5, |exec_hi|, null
+// GFX12: encoding: [0x05,0x01,0x13,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_cvt_pk_norm_u16_f16 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x13,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_cvt_pk_norm_u16_f16 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x13,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_cvt_pk_norm_u16_f16 v5, 0.5, -m0 op_sel:[0,0,0]
+// GFX12: encoding: [0x05,0x00,0x13,0xd7,0xf0,0xfa,0x00,0x40]
+
+v_cvt_pk_norm_u16_f16 v5, -src_scc, |vcc_lo| op_sel:[1,0,0]
+// GFX12: encoding: [0x05,0x0a,0x13,0xd7,0xfd,0xd4,0x00,0x20]
+
+v_cvt_pk_norm_u16_f16 v255, -|0xfe0b|, -|vcc_hi| op_sel:[0,1,0]
+// GFX12: encoding: [0xff,0x13,0x13,0xd7,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cvt_pk_norm_u16_f32 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x22,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_norm_u16_f32 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x22,0xd7,0xff,0xff,0x03,0x00]
+
+v_cvt_pk_norm_u16_f32 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x22,0xd7,0x01,0x04,0x00,0x00]
+
+v_cvt_pk_norm_u16_f32 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x22,0xd7,0x69,0xd2,0x00,0x00]
+
+v_cvt_pk_norm_u16_f32 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x22,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_cvt_pk_norm_u16_f32 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x22,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cvt_pk_norm_u16_f32 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x22,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_cvt_pk_norm_u16_f32 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x22,0xd7,0x7d,0xe0,0x01,0x00]
+
+v_cvt_pk_norm_u16_f32 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x22,0xd7,0x7e,0x82,0x01,0x00]
+
+v_cvt_pk_norm_u16_f32 v5, |exec_hi|, null
+// GFX12: encoding: [0x05,0x01,0x22,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_cvt_pk_norm_u16_f32 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x22,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_cvt_pk_norm_u16_f32 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x22,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_cvt_pk_norm_u16_f32 v5, 0.5, -m0
+// GFX12: encoding: [0x05,0x00,0x22,0xd7,0xf0,0xfa,0x00,0x40]
+
+v_cvt_pk_norm_u16_f32 v5, -src_scc, |vcc_lo|
+// GFX12: encoding: [0x05,0x02,0x22,0xd7,0xfd,0xd4,0x00,0x20]
+
+v_cvt_pk_norm_u16_f32 v255, -|0xaf123456|, -|vcc_hi|
+// GFX12: encoding: [0xff,0x03,0x22,0xd7,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_div_fixup_f16 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x54,0xd6,0x01,0x05,0x0e,0x00]
+
+v_div_fixup_f16 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x54,0xd6,0xff,0x05,0xa4,0x01]
+
+v_div_fixup_f16 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x54,0xd6,0x01,0xfe,0xff,0x01]
+
+v_div_fixup_f16 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x54,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_div_fixup_f16 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x54,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_div_fixup_f16 v5, vcc_hi, 0xfe0b, v255
+// GFX12: encoding: [0x05,0x00,0x54,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+
+v_div_fixup_f16 v5, -|ttmp15|, -|src_scc|, -|ttmp15|
+// GFX12: encoding: [0x05,0x07,0x54,0xd6,0x7b,0xfa,0xed,0xe1]
+
+v_div_fixup_f16 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x54,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_div_fixup_f16 v5, |exec_lo|, -1, vcc_hi
+// GFX12: encoding: [0x05,0x01,0x54,0xd6,0x7e,0x82,0xad,0x01]
+
+v_div_fixup_f16 v5, -|exec_hi|, null, -|vcc_lo| op_sel:[1,1,1,1]
+// GFX12: encoding: [0x05,0x7d,0x54,0xd6,0x7f,0xf8,0xa8,0xa1]
+
+v_div_fixup_f16 v5, null, exec_lo, -|0xfe0b| op_sel:[0,0,0,0]
+// GFX12: encoding: [0x05,0x04,0x54,0xd6,0x7c,0xfc,0xfc,0x83,0x0b,0xfe,0x00,0x00]
+
+v_div_fixup_f16 v5, -1, -|exec_hi|, -|src_scc| op_sel:[1,0,0,0]
+// GFX12: encoding: [0x05,0x0e,0x54,0xd6,0xc1,0xfe,0xf4,0xc3]
+
+v_div_fixup_f16 v5, 0.5, -m0, 0.5 op_sel:[0,1,0,0]
+// GFX12: encoding: [0x05,0x10,0x54,0xd6,0xf0,0xfa,0xc0,0x43]
+
+v_div_fixup_f16 v5, -src_scc, |vcc_lo|, -1 op_sel:[0,0,1,0]
+// GFX12: encoding: [0x05,0x22,0x54,0xd6,0xfd,0xd4,0x04,0x23]
+
+v_div_fixup_f16 v255, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] clamp
+// GFX12: encoding: [0xff,0xc3,0x54,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
+
+v_div_fixup_f32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x27,0xd6,0x01,0x05,0x0e,0x00]
+
+v_div_fixup_f32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x27,0xd6,0xff,0x05,0xa4,0x01]
+
+v_div_fixup_f32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x27,0xd6,0x01,0xfe,0xff,0x01]
+
+v_div_fixup_f32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x27,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_div_fixup_f32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x27,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_div_fixup_f32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x27,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_div_fixup_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15|
+// GFX12: encoding: [0x05,0x07,0x27,0xd6,0x7b,0xfa,0xed,0xe1]
+
+v_div_fixup_f32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x27,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_div_fixup_f32 v5, |exec_lo|, -1, vcc_hi
+// GFX12: encoding: [0x05,0x01,0x27,0xd6,0x7e,0x82,0xad,0x01]
+
+v_div_fixup_f32 v5, -|exec_hi|, null, -|vcc_lo|
+// GFX12: encoding: [0x05,0x05,0x27,0xd6,0x7f,0xf8,0xa8,0xa1]
+
+v_div_fixup_f32 v5, null, exec_lo, -|0xaf123456|
+// GFX12: encoding: [0x05,0x04,0x27,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+
+v_div_fixup_f32 v5, -1, -|exec_hi|, -|src_scc|
+// GFX12: encoding: [0x05,0x06,0x27,0xd6,0xc1,0xfe,0xf4,0xc3]
+
+v_div_fixup_f32 v5, 0.5, -m0, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x27,0xd6,0xf0,0xfa,0xc0,0x4b]
+
+v_div_fixup_f32 v5, -src_scc, |vcc_lo|, -1 mul:4
+// GFX12: encoding: [0x05,0x02,0x27,0xd6,0xfd,0xd4,0x04,0x33]
+
+v_div_fixup_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2
+// GFX12: encoding: [0xff,0x83,0x27,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4]
+// GFX12: encoding: [0x05,0x00,0x28,0xd6,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], v[254:255], v[254:255], s[6:7]
+// GFX12: encoding: [0x05,0x00,0x28,0xd6,0xfe,0xfd,0x1b,0x00]
+
+v_div_fixup_f64 v[5:6], s[2:3], s[4:5], v[254:255]
+// GFX12: encoding: [0x05,0x00,0x28,0xd6,0x02,0x08,0xf8,0x07]
+
+v_div_fixup_f64 v[5:6], -|s[104:105]|, s[104:105], -|s[104:105]|
+// GFX12: encoding: [0x05,0x05,0x28,0xd6,0x68,0xd0,0xa0,0xa1]
+
+v_div_fixup_f64 v[5:6], vcc, -|ttmp[14:15]|, -|ttmp[14:15]|
+// GFX12: encoding: [0x05,0x06,0x28,0xd6,0x6a,0xf4,0xe8,0xc1]
+
+v_div_fixup_f64 v[5:6], -|ttmp[14:15]|, 0xaf123456, null
+// GFX12: encoding: [0x05,0x01,0x28,0xd6,0x7a,0xfe,0xf1,0x21,0x56,0x34,0x12,0xaf]
+
+v_div_fixup_f64 v[5:6], -|exec|, -|src_scc|, -|exec|
+// GFX12: encoding: [0x05,0x07,0x28,0xd6,0x7e,0xfa,0xf9,0xe1]
+
+v_div_fixup_f64 v[5:6], null, 0.5, vcc
+// GFX12: encoding: [0x05,0x00,0x28,0xd6,0x7c,0xe0,0xa9,0x01]
+
+v_div_fixup_f64 v[5:6], -1, -1, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x28,0xd6,0xc1,0x82,0xfd,0x03,0x56,0x34,0x12,0xaf]
+
+v_div_fixup_f64 v[5:6], 0.5, null, -|src_scc| mul:2
+// GFX12: encoding: [0x05,0x04,0x28,0xd6,0xf0,0xf8,0xf4,0x8b]
+
+v_div_fixup_f64 v[5:6], -|src_scc|, -|exec|, 0.5 mul:4
+// GFX12: encoding: [0x05,0x03,0x28,0xd6,0xfd,0xfc,0xc0,0x73]
+
+v_div_fixup_f64 v[254:255], 0xaf123456, -|vcc|, -1 clamp div:2
+// GFX12: encoding: [0xfe,0x82,0x28,0xd6,0xff,0xd4,0x04,0x5b,0x56,0x34,0x12,0xaf]
+
+v_div_fmas_f32 v5, vcc_lo, v2, vcc_lo
+// W32: encoding: [0x05,0x00,0x37,0xd6,0x6a,0x04,0xaa,0x01]
+
+v_div_fmas_f32 v5, ttmp15, ttmp15, ttmp15
+// W32: encoding: [0x05,0x00,0x37,0xd6,0x7b,0xf6,0xec,0x01]
+
+v_div_fmas_f32 v5, -|m0|, -|v255|, v3
+// W32: encoding: [0x05,0x03,0x37,0xd6,0x7d,0xfe,0x0f,0x64]
+
+v_div_fmas_f32 v5, -|exec_lo|, -|exec_lo|, -|exec_lo|
+// W32: encoding: [0x05,0x07,0x37,0xd6,0x7e,0xfc,0xf8,0xe1]
+
+v_div_fmas_f32 v5, -|exec_hi|, 0.5, -|v255|
+// W32: encoding: [0x05,0x05,0x37,0xd6,0x7f,0xe0,0xfd,0xa7]
+
+v_div_fmas_f32 v5, null, exec_hi, -|exec_hi|
+// W32: encoding: [0x05,0x04,0x37,0xd6,0x7c,0xfe,0xfc,0x81]
+
+v_div_fmas_f32 v5, -1, -|m0|, -|m0|
+// W32: encoding: [0x05,0x06,0x37,0xd6,0xc1,0xfa,0xf4,0xc1]
+
+v_div_fmas_f32 v5, 0.5, -|vcc_lo|, 0.5 mul:2
+// W32: encoding: [0x05,0x02,0x37,0xd6,0xf0,0xd4,0xc0,0x4b]
+
+v_div_fmas_f32 v5, vcc_lo, v2, v3
+// W64: encoding: [0x05,0x00,0x37,0xd6,0x6a,0x04,0x0e,0x04]
+
+v_div_fmas_f32 v5, vcc_hi, v255, vcc_hi
+// W64: encoding: [0x05,0x00,0x37,0xd6,0x6b,0xfe,0xaf,0x01]
+
+v_div_fmas_f32 v5, -|ttmp15|, -|ttmp15|, ttmp15
+// W64: encoding: [0x05,0x03,0x37,0xd6,0x7b,0xf6,0xec,0x61]
+
+v_div_fmas_f32 v5, m0, 0.5, v255
+// W64: encoding: [0x05,0x00,0x37,0xd6,0x7d,0xe0,0xfd,0x07]
+
+v_div_fmas_f32 v5, -|exec_lo|, exec_lo, -|exec_lo|
+// W64: encoding: [0x05,0x05,0x37,0xd6,0x7e,0xfc,0xf8,0xa1]
+
+v_div_fmas_f32 v5, -|exec_hi|, -|exec_hi|, -|exec_hi|
+// W64: encoding: [0x05,0x07,0x37,0xd6,0x7f,0xfe,0xfc,0xe1]
+
+v_div_fmas_f32 v5, null, m0, -|m0|
+// W64: encoding: [0x05,0x04,0x37,0xd6,0x7c,0xfa,0xf4,0x81]
+
+v_div_fmas_f32 v5, -1, -|vcc_lo|, -|vcc_lo|
+// W64: encoding: [0x05,0x06,0x37,0xd6,0xc1,0xd4,0xa8,0xc1]
+
+v_div_fmas_f32 v5, 0.5, -|vcc_hi|, 0.5 mul:2
+// W64: encoding: [0x05,0x02,0x37,0xd6,0xf0,0xd6,0xc0,0x4b]
+
+v_div_fmas_f32 v5, v1, 0xaf123456, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x37,0xd6,0x01,0xff,0xfd,0x03,0x56,0x34,0x12,0xaf]
+
+v_div_fmas_f32 v5, v255, src_scc, src_scc
+// GFX12: encoding: [0x05,0x00,0x37,0xd6,0xff,0xfb,0xf5,0x03]
+
+v_div_fmas_f32 v5, s105, s105, s105
+// GFX12: encoding: [0x05,0x00,0x37,0xd6,0x69,0xd2,0xa4,0x01]
+
+v_div_fmas_f32 v5, src_scc, -1, -1 mul:4
+// GFX12: encoding: [0x05,0x00,0x37,0xd6,0xfd,0x82,0x05,0x13]
+
+v_div_fmas_f32 v255, -|0xaf123456|, null, null clamp div:2
+// GFX12: encoding: [0xff,0x81,0x37,0xd6,0xff,0xf8,0xf0,0x39,0x56,0x34,0x12,0xaf]
+
+v_div_fmas_f64 v[5:6], v[1:2], 0xaf123456, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x38,0xd6,0x01,0xff,0xfd,0x03,0x56,0x34,0x12,0xaf]
+
+v_div_fmas_f64 v[5:6], v[254:255], src_scc, v[3:4]
+// GFX12: encoding: [0x05,0x00,0x38,0xd6,0xfe,0xfb,0x0d,0x04]
+
+v_div_fmas_f64 v[5:6], s[104:105], |s[104:105]|, s[104:105]
+// GFX12: encoding: [0x05,0x02,0x38,0xd6,0x68,0xd0,0xa0,0x01]
+
+v_div_fmas_f64 v[5:6], -|vcc|, v[2:3], -|v[254:255]|
+// GFX12: encoding: [0x05,0x05,0x38,0xd6,0x6a,0x04,0xfa,0xa7]
+
+v_div_fmas_f64 v[5:6], -|ttmp[14:15]|, -|ttmp[14:15]|, -|ttmp[14:15]|
+// GFX12: encoding: [0x05,0x07,0x38,0xd6,0x7a,0xf4,0xe8,0xe1]
+
+v_div_fmas_f64 v[5:6], -|exec|, -|v[254:255]|, null
+// GFX12: encoding: [0x05,0x03,0x38,0xd6,0x7e,0xfc,0xf3,0x61]
+
+v_div_fmas_f64 v[5:6], null, 0.5, -src_scc
+// GFX12: encoding: [0x05,0x00,0x38,0xd6,0x7c,0xe0,0xf5,0x83]
+
+v_div_fmas_f64 v[5:6], -1, -exec, |exec|
+// GFX12: encoding: [0x05,0x04,0x38,0xd6,0xc1,0xfc,0xf8,0x41]
+
+v_div_fmas_f64 v[5:6], 0.5, -|vcc|, -|vcc| mul:2
+// GFX12: encoding: [0x05,0x06,0x38,0xd6,0xf0,0xd4,0xa8,0xc9]
+
+v_div_fmas_f64 v[5:6], -|src_scc|, -1, 0.5 mul:4
+// GFX12: encoding: [0x05,0x01,0x38,0xd6,0xfd,0x82,0xc1,0x33]
+
+v_div_fmas_f64 v[254:255], 0xaf123456, null, -1 clamp div:2
+// GFX12: encoding: [0xfe,0x80,0x38,0xd6,0xff,0xf8,0x04,0x1b,0x56,0x34,0x12,0xaf]
+
+v_div_scale_f32 v5, vcc_lo, v1, v2, s3
+// W32: encoding: [0x05,0x6a,0xfc,0xd6,0x01,0x05,0x0e,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, vcc_lo, v255, s2, s105
+// W32: encoding: [0x05,0x6a,0xfc,0xd6,0xff,0x05,0xa4,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, vcc_lo, s1, v255, exec_hi
+// W32: encoding: [0x05,0x6a,0xfc,0xd6,0x01,0xfe,0xff,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, vcc_lo, s105, s105, exec_lo
+// W32: encoding: [0x05,0x6a,0xfc,0xd6,0x69,0xd2,0xf8,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, vcc_lo, vcc_lo, ttmp15, v3
+// W32: encoding: [0x05,0x6a,0xfc,0xd6,0x6a,0xf6,0x0c,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, vcc_lo, vcc_hi, 0xaf123456, v255
+// W32: encoding: [0x05,0x6a,0xfc,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, vcc_lo, -ttmp15, -src_scc, -ttmp15
+// W32: encoding: [0x05,0x6a,0xfc,0xd6,0x7b,0xfa,0xed,0xe1]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, vcc_lo, m0, 0.5, m0
+// W32: encoding: [0x05,0x6a,0xfc,0xd6,0x7d,0xe0,0xf5,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, vcc_lo, exec_lo, -1, vcc_hi
+// W32: encoding: [0x05,0x6a,0xfc,0xd6,0x7e,0x82,0xad,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, vcc_lo, -exec_hi, null, -vcc_lo
+// W32: encoding: [0x05,0x6a,0xfc,0xd6,0x7f,0xf8,0xa8,0xa1]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, vcc_lo, null, exec_lo, neg(0xaf123456)
+// W32: encoding: [0x05,0x6a,0xfc,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, vcc_lo, -1, -exec_hi, -src_scc
+// W32: encoding: [0x05,0x6a,0xfc,0xd6,0xc1,0xfe,0xf4,0xc3]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, vcc_lo, 0.5, -m0, 0.5 mul:2
+// W32: encoding: [0x05,0x6a,0xfc,0xd6,0xf0,0xfa,0xc0,0x4b]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, vcc_lo, -src_scc, vcc_lo, -1 mul:4
+// W32: encoding: [0x05,0x6a,0xfc,0xd6,0xfd,0xd4,0x04,0x33]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v255, vcc_lo, neg(0xaf123456), -vcc_hi, null clamp div:2
+// W32: encoding: [0xff,0xea,0xfc,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, vcc, v1, v2, s3
+// W64: encoding: [0x05,0x6a,0xfc,0xd6,0x01,0x05,0x0e,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, vcc, v255, s2, s105
+// W64: encoding: [0x05,0x6a,0xfc,0xd6,0xff,0x05,0xa4,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, vcc, s1, v255, exec_hi
+// W64: encoding: [0x05,0x6a,0xfc,0xd6,0x01,0xfe,0xff,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, vcc, s105, s105, exec_lo
+// W64: encoding: [0x05,0x6a,0xfc,0xd6,0x69,0xd2,0xf8,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, vcc, vcc_lo, ttmp15, v3
+// W64: encoding: [0x05,0x6a,0xfc,0xd6,0x6a,0xf6,0x0c,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, vcc, vcc_hi, 0xaf123456, v255
+// W64: encoding: [0x05,0x6a,0xfc,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, vcc, -ttmp15, -src_scc, -ttmp15
+// W64: encoding: [0x05,0x6a,0xfc,0xd6,0x7b,0xfa,0xed,0xe1]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, vcc, m0, 0.5, m0
+// W64: encoding: [0x05,0x6a,0xfc,0xd6,0x7d,0xe0,0xf5,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, vcc, exec_lo, -1, vcc_hi
+// W64: encoding: [0x05,0x6a,0xfc,0xd6,0x7e,0x82,0xad,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, vcc, -exec_hi, null, -vcc_lo
+// W64: encoding: [0x05,0x6a,0xfc,0xd6,0x7f,0xf8,0xa8,0xa1]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, vcc, null, exec_lo, neg(0xaf123456)
+// W64: encoding: [0x05,0x6a,0xfc,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, vcc, -1, -exec_hi, -src_scc
+// W64: encoding: [0x05,0x6a,0xfc,0xd6,0xc1,0xfe,0xf4,0xc3]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, vcc, 0.5, -m0, 0.5 mul:2
+// W64: encoding: [0x05,0x6a,0xfc,0xd6,0xf0,0xfa,0xc0,0x4b]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, vcc, -src_scc, vcc_lo, -1 mul:4
+// W64: encoding: [0x05,0x6a,0xfc,0xd6,0xfd,0xd4,0x04,0x33]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v255, vcc, neg(0xaf123456), -vcc_hi, null clamp div:2
+// W64: encoding: [0xff,0xea,0xfc,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f64 v[5:6], vcc_lo, v[1:2], v[2:3], v[3:4]
+// W32: encoding: [0x05,0x6a,0xfd,0xd6,0x01,0x05,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f64 v[5:6], vcc_lo, v[254:255], v[254:255], s[6:7]
+// W32: encoding: [0x05,0x6a,0xfd,0xd6,0xfe,0xfd,0x1b,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f64 v[5:6], vcc_lo, s[2:3], s[4:5], v[254:255]
+// W32: encoding: [0x05,0x6a,0xfd,0xd6,0x02,0x08,0xf8,0x07]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f64 v[5:6], vcc_lo, -s[104:105], s[104:105], -s[104:105]
+// W32: encoding: [0x05,0x6a,0xfd,0xd6,0x68,0xd0,0xa0,0xa1]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f64 v[5:6], vcc_lo, vcc, -ttmp[14:15], -ttmp[14:15]
+// W32: encoding: [0x05,0x6a,0xfd,0xd6,0x6a,0xf4,0xe8,0xc1]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f64 v[5:6], vcc_lo, -ttmp[14:15], 0xaf123456, null
+// W32: encoding: [0x05,0x6a,0xfd,0xd6,0x7a,0xfe,0xf1,0x21,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f64 v[5:6], vcc_lo, -exec, -src_scc, -exec
+// W32: encoding: [0x05,0x6a,0xfd,0xd6,0x7e,0xfa,0xf9,0xe1]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f64 v[5:6], vcc_lo, null, 0.5, vcc
+// W32: encoding: [0x05,0x6a,0xfd,0xd6,0x7c,0xe0,0xa9,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f64 v[5:6], vcc_lo, -1, -1, 0xaf123456
+// W32: encoding: [0x05,0x6a,0xfd,0xd6,0xc1,0x82,0xfd,0x03,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f64 v[5:6], vcc_lo, 0.5, null, -src_scc mul:2
+// W32: encoding: [0x05,0x6a,0xfd,0xd6,0xf0,0xf8,0xf4,0x8b]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f64 v[5:6], vcc_lo, -src_scc, -exec, 0.5 mul:4
+// W32: encoding: [0x05,0x6a,0xfd,0xd6,0xfd,0xfc,0xc0,0x73]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f64 v[254:255], vcc_lo, 0xaf123456, -vcc, -1 clamp div:2
+// W32: encoding: [0xfe,0xea,0xfd,0xd6,0xff,0xd4,0x04,0x5b,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], v[3:4]
+// W64: encoding: [0x05,0x6a,0xfd,0xd6,0x01,0x05,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f64 v[5:6], vcc, v[254:255], v[254:255], s[6:7]
+// W64: encoding: [0x05,0x6a,0xfd,0xd6,0xfe,0xfd,0x1b,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f64 v[5:6], vcc, s[2:3], s[4:5], v[254:255]
+// W64: encoding: [0x05,0x6a,0xfd,0xd6,0x02,0x08,0xf8,0x07]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f64 v[5:6], vcc, -s[104:105], s[104:105], -s[104:105]
+// W64: encoding: [0x05,0x6a,0xfd,0xd6,0x68,0xd0,0xa0,0xa1]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f64 v[5:6], vcc, vcc, -ttmp[14:15], -ttmp[14:15]
+// W64: encoding: [0x05,0x6a,0xfd,0xd6,0x6a,0xf4,0xe8,0xc1]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f64 v[5:6], vcc, -ttmp[14:15], 0xaf123456, null
+// W64: encoding: [0x05,0x6a,0xfd,0xd6,0x7a,0xfe,0xf1,0x21,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f64 v[5:6], vcc, -exec, -src_scc, -exec
+// W64: encoding: [0x05,0x6a,0xfd,0xd6,0x7e,0xfa,0xf9,0xe1]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f64 v[5:6], vcc, null, 0.5, vcc
+// W64: encoding: [0x05,0x6a,0xfd,0xd6,0x7c,0xe0,0xa9,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f64 v[5:6], vcc, -1, -1, 0xaf123456
+// W64: encoding: [0x05,0x6a,0xfd,0xd6,0xc1,0x82,0xfd,0x03,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f64 v[5:6], vcc, 0.5, null, -src_scc mul:2
+// W64: encoding: [0x05,0x6a,0xfd,0xd6,0xf0,0xf8,0xf4,0x8b]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f64 v[5:6], vcc, -src_scc, -exec, 0.5 mul:4
+// W64: encoding: [0x05,0x6a,0xfd,0xd6,0xfd,0xfc,0xc0,0x73]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f64 v[254:255], vcc, 0xaf123456, -vcc, -1 clamp div:2
+// W64: encoding: [0xfe,0xea,0xfd,0xd6,0xff,0xd4,0x04,0x5b,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_dot2_bf16_bf16 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x67,0xd6,0x01,0x05,0x0e,0x00]
+
+v_dot2_bf16_bf16 v5, v255, v255, s105
+// GFX12: encoding: [0x05,0x00,0x67,0xd6,0xff,0xff,0xa7,0x01]
+
+v_dot2_bf16_bf16 v5, s1, s2, v3
+// GFX12: encoding: [0x05,0x00,0x67,0xd6,0x01,0x04,0x0c,0x04]
+
+v_dot2_bf16_bf16 v5, s105, s105, m0
+// GFX12: encoding: [0x05,0x00,0x67,0xd6,0x69,0xd2,0xf4,0x01]
+
+v_dot2_bf16_bf16 v5, vcc_lo, ttmp15, v255
+// GFX12: encoding: [0x05,0x00,0x67,0xd6,0x6a,0xf6,0xfc,0x07]
+
+v_dot2_bf16_bf16 v5, vcc_hi, 0xfe0b, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x67,0xd6,0x6b,0xfe,0xad,0x01,0x0b,0xfe,0x00,0x00]
+
+v_dot2_bf16_bf16 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x67,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_dot2_bf16_bf16 v5, |m0|, -1, -vcc_lo
+// GFX12: encoding: [0x05,0x01,0x67,0xd6,0x7d,0x82,0xa9,0x81]
+
+v_dot2_bf16_bf16 v5, -|exec_lo|, null, -|0xfe0b|
+// GFX12: encoding: [0x05,0x05,0x67,0xd6,0x7e,0xf8,0xfc,0xa3,0x0b,0xfe,0x00,0x00]
+
+v_dot2_bf16_bf16 v5, -|exec_hi|, -|exec_lo|, -|exec_lo|
+// GFX12: encoding: [0x05,0x07,0x67,0xd6,0x7f,0xfc,0xf8,0xe1]
+
+v_dot2_bf16_bf16 v5, null, -exec_hi, |src_scc|
+// GFX12: encoding: [0x05,0x04,0x67,0xd6,0x7c,0xfe,0xf4,0x43]
+
+v_dot2_bf16_bf16 v5, -1, -|m0|, -|exec_hi| op_sel:[0,0,0,0]
+// GFX12: encoding: [0x05,0x06,0x67,0xd6,0xc1,0xfa,0xfc,0xc1]
+
+v_dot2_bf16_bf16 v5, -src_scc, |vcc_lo|, -1 op_sel:[0,0,1,0]
+// GFX12: encoding: [0x05,0x22,0x67,0xd6,0xfd,0xd4,0x04,0x23]
+
+v_dot2_bf16_bf16 v255, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1]
+// GFX12: encoding: [0xff,0x43,0x67,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
+
+v_dot2_f16_f16 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x66,0xd6,0x01,0x05,0x0e,0x00]
+
+v_dot2_f16_f16 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x66,0xd6,0xff,0x05,0xa4,0x01]
+
+v_dot2_f16_f16 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x66,0xd6,0x01,0xfe,0xff,0x01]
+
+v_dot2_f16_f16 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x66,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_dot2_f16_f16 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x66,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_dot2_f16_f16 v5, vcc_hi, 0xfe0b, v255
+// GFX12: encoding: [0x05,0x00,0x66,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+
+v_dot2_f16_f16 v5, -|ttmp15|, -|src_scc|, -|ttmp15|
+// GFX12: encoding: [0x05,0x07,0x66,0xd6,0x7b,0xfa,0xed,0xe1]
+
+v_dot2_f16_f16 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x66,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_dot2_f16_f16 v5, |exec_lo|, -1, vcc_hi
+// GFX12: encoding: [0x05,0x01,0x66,0xd6,0x7e,0x82,0xad,0x01]
+
+v_dot2_f16_f16 v5, -|exec_hi|, null, -|vcc_lo|
+// GFX12: encoding: [0x05,0x05,0x66,0xd6,0x7f,0xf8,0xa8,0xa1]
+
+v_dot2_f16_f16 v5, null, exec_lo, -|0xfe0b|
+// GFX12: encoding: [0x05,0x04,0x66,0xd6,0x7c,0xfc,0xfc,0x83,0x0b,0xfe,0x00,0x00]
+
+v_dot2_f16_f16 v5, -1, -|exec_hi|, -|src_scc|
+// GFX12: encoding: [0x05,0x06,0x66,0xd6,0xc1,0xfe,0xf4,0xc3]
+
+v_dot2_f16_f16 v5, 0.5, -m0, 0.5 op_sel:[0,0,0,0]
+// GFX12: encoding: [0x05,0x00,0x66,0xd6,0xf0,0xfa,0xc0,0x43]
+
+v_dot2_f16_f16 v5, -src_scc, |vcc_lo|, -1 op_sel:[0,0,1,0]
+// GFX12: encoding: [0x05,0x22,0x66,0xd6,0xfd,0xd4,0x04,0x23]
+
+v_dot2_f16_f16 v255, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1]
+// GFX12: encoding: [0xff,0x43,0x66,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
+
+v_fma_dx9_zero_f32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x09,0xd6,0x01,0x05,0x0e,0x00]
+
+v_fma_dx9_zero_f32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x09,0xd6,0xff,0x05,0xa4,0x01]
+
+v_fma_dx9_zero_f32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x09,0xd6,0x01,0xfe,0xff,0x01]
+
+v_fma_dx9_zero_f32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x09,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_fma_dx9_zero_f32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x09,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_fma_dx9_zero_f32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x09,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_fma_dx9_zero_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15|
+// GFX12: encoding: [0x05,0x07,0x09,0xd6,0x7b,0xfa,0xed,0xe1]
+
+v_fma_dx9_zero_f32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x09,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_fma_dx9_zero_f32 v5, |exec_lo|, -1, vcc_hi
+// GFX12: encoding: [0x05,0x01,0x09,0xd6,0x7e,0x82,0xad,0x01]
+
+v_fma_dx9_zero_f32 v5, -|exec_hi|, null, -|vcc_lo|
+// GFX12: encoding: [0x05,0x05,0x09,0xd6,0x7f,0xf8,0xa8,0xa1]
+
+v_fma_dx9_zero_f32 v5, null, exec_lo, -|0xaf123456|
+// GFX12: encoding: [0x05,0x04,0x09,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+
+v_fma_dx9_zero_f32 v5, -1, -|exec_hi|, -|src_scc|
+// GFX12: encoding: [0x05,0x06,0x09,0xd6,0xc1,0xfe,0xf4,0xc3]
+
+v_fma_dx9_zero_f32 v5, 0.5, -m0, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x09,0xd6,0xf0,0xfa,0xc0,0x4b]
+
+v_fma_dx9_zero_f32 v5, -src_scc, |vcc_lo|, -1 mul:4
+// GFX12: encoding: [0x05,0x02,0x09,0xd6,0xfd,0xd4,0x04,0x33]
+
+v_fma_dx9_zero_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2
+// GFX12: encoding: [0xff,0x83,0x09,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+
+v_fma_f16 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x48,0xd6,0x01,0x05,0x0e,0x00]
+
+v_fma_f16 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x48,0xd6,0xff,0x05,0xa4,0x01]
+
+v_fma_f16 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x48,0xd6,0x01,0xfe,0xff,0x01]
+
+v_fma_f16 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x48,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_fma_f16 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x48,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_fma_f16 v5, vcc_hi, 0xfe0b, v255
+// GFX12: encoding: [0x05,0x00,0x48,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+
+v_fma_f16 v5, -|ttmp15|, -|src_scc|, -|ttmp15|
+// GFX12: encoding: [0x05,0x07,0x48,0xd6,0x7b,0xfa,0xed,0xe1]
+
+v_fma_f16 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x48,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_fma_f16 v5, |exec_lo|, -1, vcc_hi
+// GFX12: encoding: [0x05,0x01,0x48,0xd6,0x7e,0x82,0xad,0x01]
+
+v_fma_f16 v5, -|exec_hi|, null, -|vcc_lo| op_sel:[1,1,1,1]
+// GFX12: encoding: [0x05,0x7d,0x48,0xd6,0x7f,0xf8,0xa8,0xa1]
+
+v_fma_f16 v5, null, exec_lo, -|0xfe0b| op_sel:[0,0,0,0]
+// GFX12: encoding: [0x05,0x04,0x48,0xd6,0x7c,0xfc,0xfc,0x83,0x0b,0xfe,0x00,0x00]
+
+v_fma_f16 v5, -1, -|exec_hi|, -|src_scc| op_sel:[1,0,0,0]
+// GFX12: encoding: [0x05,0x0e,0x48,0xd6,0xc1,0xfe,0xf4,0xc3]
+
+v_fma_f16 v5, 0.5, -m0, 0.5 op_sel:[0,1,0,0]
+// GFX12: encoding: [0x05,0x10,0x48,0xd6,0xf0,0xfa,0xc0,0x43]
+
+v_fma_f16 v5, -src_scc, |vcc_lo|, -1 op_sel:[0,0,1,0]
+// GFX12: encoding: [0x05,0x22,0x48,0xd6,0xfd,0xd4,0x04,0x23]
+
+v_fma_f16 v255, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] clamp
+// GFX12: encoding: [0xff,0xc3,0x48,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
+
+v_fma_f32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x13,0xd6,0x01,0x05,0x0e,0x00]
+
+v_fma_f32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x13,0xd6,0xff,0x05,0xa4,0x01]
+
+v_fma_f32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x13,0xd6,0x01,0xfe,0xff,0x01]
+
+v_fma_f32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x13,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_fma_f32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x13,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_fma_f32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x13,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_fma_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15|
+// GFX12: encoding: [0x05,0x07,0x13,0xd6,0x7b,0xfa,0xed,0xe1]
+
+v_fma_f32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x13,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_fma_f32 v5, |exec_lo|, -1, vcc_hi
+// GFX12: encoding: [0x05,0x01,0x13,0xd6,0x7e,0x82,0xad,0x01]
+
+v_fma_f32 v5, -|exec_hi|, null, -|vcc_lo|
+// GFX12: encoding: [0x05,0x05,0x13,0xd6,0x7f,0xf8,0xa8,0xa1]
+
+v_fma_f32 v5, null, exec_lo, -|0xaf123456|
+// GFX12: encoding: [0x05,0x04,0x13,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+
+v_fma_f32 v5, -1, -|exec_hi|, -|src_scc|
+// GFX12: encoding: [0x05,0x06,0x13,0xd6,0xc1,0xfe,0xf4,0xc3]
+
+v_fma_f32 v5, 0.5, -m0, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x13,0xd6,0xf0,0xfa,0xc0,0x4b]
+
+v_fma_f32 v5, -src_scc, |vcc_lo|, -1 mul:4
+// GFX12: encoding: [0x05,0x02,0x13,0xd6,0xfd,0xd4,0x04,0x33]
+
+v_fma_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2
+// GFX12: encoding: [0xff,0x83,0x13,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4]
+// GFX12: encoding: [0x05,0x00,0x14,0xd6,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], v[254:255], v[254:255], s[6:7]
+// GFX12: encoding: [0x05,0x00,0x14,0xd6,0xfe,0xfd,0x1b,0x00]
+
+v_fma_f64 v[5:6], s[2:3], s[4:5], v[254:255]
+// GFX12: encoding: [0x05,0x00,0x14,0xd6,0x02,0x08,0xf8,0x07]
+
+v_fma_f64 v[5:6], -|s[104:105]|, s[104:105], -|s[104:105]|
+// GFX12: encoding: [0x05,0x05,0x14,0xd6,0x68,0xd0,0xa0,0xa1]
+
+v_fma_f64 v[5:6], vcc, -|ttmp[14:15]|, -|ttmp[14:15]|
+// GFX12: encoding: [0x05,0x06,0x14,0xd6,0x6a,0xf4,0xe8,0xc1]
+
+v_fma_f64 v[5:6], -|ttmp[14:15]|, 0xaf123456, null
+// GFX12: encoding: [0x05,0x01,0x14,0xd6,0x7a,0xfe,0xf1,0x21,0x56,0x34,0x12,0xaf]
+
+v_fma_f64 v[5:6], -|exec|, -|src_scc|, -|exec|
+// GFX12: encoding: [0x05,0x07,0x14,0xd6,0x7e,0xfa,0xf9,0xe1]
+
+v_fma_f64 v[5:6], null, 0.5, vcc
+// GFX12: encoding: [0x05,0x00,0x14,0xd6,0x7c,0xe0,0xa9,0x01]
+
+v_fma_f64 v[5:6], -1, -1, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x14,0xd6,0xc1,0x82,0xfd,0x03,0x56,0x34,0x12,0xaf]
+
+v_fma_f64 v[5:6], 0.5, null, -|src_scc| mul:2
+// GFX12: encoding: [0x05,0x04,0x14,0xd6,0xf0,0xf8,0xf4,0x8b]
+
+v_fma_f64 v[5:6], -|src_scc|, -|exec|, 0.5 mul:4
+// GFX12: encoding: [0x05,0x03,0x14,0xd6,0xfd,0xfc,0xc0,0x73]
+
+v_fma_f64 v[254:255], 0xaf123456, -|vcc|, -1 clamp div:2
+// GFX12: encoding: [0xfe,0x82,0x14,0xd6,0xff,0xd4,0x04,0x5b,0x56,0x34,0x12,0xaf]
+
+v_fma_dx9_zero_f32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x09,0xd6,0x01,0x05,0x0e,0x00]
+
+v_fma_dx9_zero_f32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x09,0xd6,0xff,0x05,0xa4,0x01]
+
+v_fma_dx9_zero_f32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x09,0xd6,0x01,0xfe,0xff,0x01]
+
+v_fma_dx9_zero_f32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x09,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_fma_dx9_zero_f32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x09,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_fma_dx9_zero_f32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x09,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_fma_dx9_zero_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15|
+// GFX12: encoding: [0x05,0x07,0x09,0xd6,0x7b,0xfa,0xed,0xe1]
+
+v_fma_dx9_zero_f32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x09,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_fma_dx9_zero_f32 v5, |exec_lo|, -1, vcc_hi
+// GFX12: encoding: [0x05,0x01,0x09,0xd6,0x7e,0x82,0xad,0x01]
+
+v_fma_dx9_zero_f32 v5, -|exec_hi|, null, -|vcc_lo|
+// GFX12: encoding: [0x05,0x05,0x09,0xd6,0x7f,0xf8,0xa8,0xa1]
+
+v_fma_dx9_zero_f32 v5, null, exec_lo, -|0xaf123456|
+// GFX12: encoding: [0x05,0x04,0x09,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+
+v_fma_dx9_zero_f32 v5, -1, -|exec_hi|, -|src_scc|
+// GFX12: encoding: [0x05,0x06,0x09,0xd6,0xc1,0xfe,0xf4,0xc3]
+
+v_fma_dx9_zero_f32 v5, 0.5, -m0, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x09,0xd6,0xf0,0xfa,0xc0,0x4b]
+
+v_fma_dx9_zero_f32 v5, -src_scc, |vcc_lo|, -1 mul:4
+// GFX12: encoding: [0x05,0x02,0x09,0xd6,0xfd,0xd4,0x04,0x33]
+
+v_fma_dx9_zero_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2
+// GFX12: encoding: [0xff,0x83,0x09,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+
+v_ldexp_f32 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x1c,0xd7,0x01,0x05,0x02,0x00]
+
+v_ldexp_f32 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x1c,0xd7,0xff,0xff,0x03,0x00]
+
+v_ldexp_f32 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x1c,0xd7,0x01,0x04,0x00,0x00]
+
+v_ldexp_f32 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x1c,0xd7,0x69,0xd2,0x00,0x00]
+
+v_ldexp_f32 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x1c,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_ldexp_f32 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x1c,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_ldexp_f32 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x1c,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_ldexp_f32 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x1c,0xd7,0x7d,0xe0,0x01,0x00]
+
+v_ldexp_f32 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x1c,0xd7,0x7e,0x82,0x01,0x00]
+
+v_ldexp_f32 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x1c,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_ldexp_f32 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x1c,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_ldexp_f32 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x1c,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_ldexp_f32 v5, 0.5, m0 mul:2
+// GFX12: encoding: [0x05,0x00,0x1c,0xd7,0xf0,0xfa,0x00,0x08]
+
+v_ldexp_f32 v5, src_scc, vcc_lo mul:4
+// GFX12: encoding: [0x05,0x00,0x1c,0xd7,0xfd,0xd4,0x00,0x10]
+
+v_ldexp_f32 v255, -|0xaf123456|, vcc_hi clamp div:2
+// GFX12: encoding: [0xff,0x81,0x1c,0xd7,0xff,0xd6,0x00,0x38,0x56,0x34,0x12,0xaf]
+
+v_ldexp_f64 v[5:6], v[1:2], v2
+// GFX12: encoding: [0x05,0x00,0x2b,0xd7,0x01,0x05,0x02,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], v255
+// GFX12: encoding: [0x05,0x00,0x2b,0xd7,0x01,0xff,0x03,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], s2
+// GFX12: encoding: [0x05,0x00,0x2b,0xd7,0x01,0x05,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], s105
+// GFX12: encoding: [0x05,0x00,0x2b,0xd7,0x01,0xd3,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[254:255], ttmp15
+// GFX12: encoding: [0x05,0x00,0x2b,0xd7,0xfe,0xf7,0x00,0x00]
+
+v_ldexp_f64 v[5:6], s[2:3], vcc_hi
+// GFX12: encoding: [0x05,0x00,0x2b,0xd7,0x02,0xd6,0x00,0x00]
+
+v_ldexp_f64 v[5:6], s[104:105], vcc_lo
+// GFX12: encoding: [0x05,0x00,0x2b,0xd7,0x68,0xd4,0x00,0x00]
+
+v_ldexp_f64 v[5:6], vcc, m0
+// GFX12: encoding: [0x05,0x00,0x2b,0xd7,0x6a,0xfa,0x00,0x00]
+
+v_ldexp_f64 v[5:6], ttmp[14:15], exec_hi
+// GFX12: encoding: [0x05,0x00,0x2b,0xd7,0x7a,0xfe,0x00,0x00]
+
+v_ldexp_f64 v[5:6], exec, exec_lo
+// GFX12: encoding: [0x05,0x00,0x2b,0xd7,0x7e,0xfc,0x00,0x00]
+
+v_ldexp_f64 v[5:6], null, null
+// GFX12: encoding: [0x05,0x00,0x2b,0xd7,0x7c,0xf8,0x00,0x00]
+
+v_ldexp_f64 v[5:6], -1, -1
+// GFX12: encoding: [0x05,0x00,0x2b,0xd7,0xc1,0x82,0x01,0x00]
+
+v_ldexp_f64 v[5:6], 0.5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x2b,0xd7,0xf0,0xe0,0x01,0x08]
+
+v_ldexp_f64 v[5:6], -|src_scc|, src_scc mul:4
+// GFX12: encoding: [0x05,0x01,0x2b,0xd7,0xfd,0xfa,0x01,0x30]
+
+v_ldexp_f64 v[254:255], 0xaf123456, 0xaf123456 clamp div:2
+// GFX12: encoding: [0xfe,0x80,0x2b,0xd7,0xff,0xfe,0x01,0x18,0x56,0x34,0x12,0xaf]
+
+v_lerp_u8 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x15,0xd6,0x01,0x05,0x0e,0x00]
+
+v_lerp_u8 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x15,0xd6,0xff,0x05,0xa4,0x01]
+
+v_lerp_u8 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x15,0xd6,0x01,0xfe,0xff,0x01]
+
+v_lerp_u8 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x15,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_lerp_u8 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x15,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_lerp_u8 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x15,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_lerp_u8 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x15,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_lerp_u8 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x15,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_lerp_u8 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x15,0xd6,0x7e,0x82,0xad,0x01]
+
+v_lerp_u8 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x15,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_lerp_u8 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x15,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_lerp_u8 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x15,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_lerp_u8 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x15,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_lerp_u8 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x15,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_lerp_u8 v255, 0xaf123456, vcc_hi, null
+// GFX12: encoding: [0xff,0x00,0x15,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_lshl_add_u32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x46,0xd6,0x01,0x05,0x0e,0x00]
+
+v_lshl_add_u32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x46,0xd6,0xff,0x05,0xa4,0x01]
+
+v_lshl_add_u32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x46,0xd6,0x01,0xfe,0xff,0x01]
+
+v_lshl_add_u32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x46,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_lshl_add_u32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x46,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_lshl_add_u32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x46,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_lshl_add_u32 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x46,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_lshl_add_u32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x46,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_lshl_add_u32 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x46,0xd6,0x7e,0x82,0xad,0x01]
+
+v_lshl_add_u32 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x46,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_lshl_add_u32 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x46,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_lshl_add_u32 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x46,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_lshl_add_u32 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x46,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_lshl_add_u32 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x46,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_lshl_add_u32 v255, 0xaf123456, vcc_hi, null
+// GFX12: encoding: [0xff,0x00,0x46,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_lshl_or_b32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x56,0xd6,0x01,0x05,0x0e,0x00]
+
+v_lshl_or_b32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x56,0xd6,0xff,0x05,0xa4,0x01]
+
+v_lshl_or_b32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x56,0xd6,0x01,0xfe,0xff,0x01]
+
+v_lshl_or_b32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x56,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_lshl_or_b32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x56,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_lshl_or_b32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x56,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_lshl_or_b32 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x56,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_lshl_or_b32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x56,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_lshl_or_b32 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x56,0xd6,0x7e,0x82,0xad,0x01]
+
+v_lshl_or_b32 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x56,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_lshl_or_b32 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x56,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_lshl_or_b32 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x56,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_lshl_or_b32 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x56,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_lshl_or_b32 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x56,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_lshl_or_b32 v255, 0xaf123456, vcc_hi, null
+// GFX12: encoding: [0xff,0x00,0x56,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_lshlrev_b16 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x38,0xd7,0x01,0x05,0x02,0x00]
+
+v_lshlrev_b16 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x38,0xd7,0xff,0xff,0x03,0x00]
+
+v_lshlrev_b16 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x38,0xd7,0x01,0x04,0x00,0x00]
+
+v_lshlrev_b16 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x38,0xd7,0x69,0xd2,0x00,0x00]
+
+v_lshlrev_b16 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x38,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_lshlrev_b16 v5, vcc_hi, 0xfe0b
+// GFX12: encoding: [0x05,0x00,0x38,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_lshlrev_b16 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x38,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_lshlrev_b16 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x38,0xd7,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_lshlrev_b16 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x38,0xd7,0x7e,0x82,0x01,0x00]
+
+v_lshlrev_b16 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x38,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_lshlrev_b16 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x38,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_lshlrev_b16 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x38,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_lshlrev_b16 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x38,0xd7,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_lshlrev_b16 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x38,0xd7,0xfd,0xd4,0x00,0x00]
+
+v_lshlrev_b16 v255, 0xfe0b, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x38,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_lshrrev_b16 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x39,0xd7,0x01,0x05,0x02,0x00]
+
+v_lshrrev_b16 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x39,0xd7,0xff,0xff,0x03,0x00]
+
+v_lshrrev_b16 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x39,0xd7,0x01,0x04,0x00,0x00]
+
+v_lshrrev_b16 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x39,0xd7,0x69,0xd2,0x00,0x00]
+
+v_lshrrev_b16 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x39,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_lshrrev_b16 v5, vcc_hi, 0xfe0b
+// GFX12: encoding: [0x05,0x00,0x39,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_lshrrev_b16 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x39,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_lshrrev_b16 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x39,0xd7,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_lshrrev_b16 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x39,0xd7,0x7e,0x82,0x01,0x00]
+
+v_lshrrev_b16 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x39,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_lshrrev_b16 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x39,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_lshrrev_b16 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x39,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_lshrrev_b16 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x39,0xd7,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_lshrrev_b16 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x39,0xd7,0xfd,0xd4,0x00,0x00]
+
+v_lshrrev_b16 v255, 0xfe0b, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x39,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_lshrrev_b64 v[5:6], v1, vcc
+// GFX12: encoding: [0x05,0x00,0x3d,0xd7,0x01,0xd5,0x00,0x00]
+
+v_lshrrev_b64 v[5:6], v255, exec
+// GFX12: encoding: [0x05,0x00,0x3d,0xd7,0xff,0xfd,0x00,0x00]
+
+v_lshrrev_b64 v[5:6], exec_lo, v[2:3]
+// GFX12: encoding: [0x05,0x00,0x3d,0xd7,0x7e,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], exec_hi, v[254:255]
+// GFX12: encoding: [0x05,0x00,0x3d,0xd7,0x7f,0xfc,0x03,0x00]
+
+v_lshrrev_b64 v[5:6], null, null
+// GFX12: encoding: [0x05,0x00,0x3d,0xd7,0x7c,0xf8,0x00,0x00]
+
+v_lshrrev_b64 v[5:6], -1, -1
+// GFX12: encoding: [0x05,0x00,0x3d,0xd7,0xc1,0x82,0x01,0x00]
+
+v_lshrrev_b64 v[5:6], 0.5, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x3d,0xd7,0xf0,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_lshrrev_b64 v[5:6], src_scc, src_scc
+// GFX12: encoding: [0x05,0x00,0x3d,0xd7,0xfd,0xfa,0x01,0x00]
+
+v_lshrrev_b64 v[254:255], 0xaf123456, 0.5
+// GFX12: encoding: [0xfe,0x00,0x3d,0xd7,0xff,0xe0,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_mad_i16 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x53,0xd6,0x01,0x05,0x0e,0x00]
+
+v_mad_i16 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x53,0xd6,0xff,0x05,0xa4,0x01]
+
+v_mad_i16 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x53,0xd6,0x01,0xfe,0xff,0x01]
+
+v_mad_i16 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x53,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_mad_i16 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x53,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_mad_i16 v5, vcc_hi, 0xfe0b, v255
+// GFX12: encoding: [0x05,0x00,0x53,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+
+v_mad_i16 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x53,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_mad_i16 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x53,0xd6,0x7d,0xfe,0xf5,0x01,0x00,0x38,0x00,0x00]
+
+v_mad_i16 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x53,0xd6,0x7e,0x82,0xad,0x01]
+
+v_mad_i16 v5, exec_hi, null, vcc_lo op_sel:[1,1,1,1]
+// GFX12: encoding: [0x05,0x78,0x53,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_mad_i16 v5, null, exec_lo, 0xfe0b op_sel:[0,0,0,0]
+// GFX12: encoding: [0x05,0x00,0x53,0xd6,0x7c,0xfc,0xfc,0x03,0x0b,0xfe,0x00,0x00]
+
+v_mad_i16 v5, -1, exec_hi, src_scc op_sel:[1,0,0,0]
+// GFX12: encoding: [0x05,0x08,0x53,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_mad_i16 v5, 0.5, m0, 0.5 op_sel:[0,1,0,0]
+// GFX12: encoding: [0x05,0x10,0x53,0xd6,0xff,0xfa,0xfc,0x03,0x00,0x38,0x00,0x00]
+
+v_mad_i16 v5, src_scc, vcc_lo, -1 op_sel:[0,0,1,0]
+// GFX12: encoding: [0x05,0x20,0x53,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_mad_i16 v255, 0xfe0b, vcc_hi, null op_sel:[0,0,0,1] clamp
+// GFX12: encoding: [0xff,0xc0,0x53,0xd6,0xff,0xd6,0xf0,0x01,0x0b,0xfe,0x00,0x00]
+
+v_mad_i32_i16 v5, v1, v2, v3
+// GFX12: encoding: [0x05,0x00,0x5a,0xd6,0x01,0x05,0x0e,0x04]
+
+v_mad_i32_i16 v5, v255, v255, s3
+// GFX12: encoding: [0x05,0x00,0x5a,0xd6,0xff,0xff,0x0f,0x00]
+
+v_mad_i32_i16 v5, s1, s2, v255
+// GFX12: encoding: [0x05,0x00,0x5a,0xd6,0x01,0x04,0xfc,0x07]
+
+v_mad_i32_i16 v5, s105, s105, s105
+// GFX12: encoding: [0x05,0x00,0x5a,0xd6,0x69,0xd2,0xa4,0x01]
+
+v_mad_i32_i16 v5, vcc_lo, ttmp15, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x5a,0xd6,0x6a,0xf6,0xa8,0x01]
+
+v_mad_i32_i16 v5, vcc_hi, 0xfe0b, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x5a,0xd6,0x6b,0xfe,0xad,0x01,0x0b,0xfe,0x00,0x00]
+
+v_mad_i32_i16 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x5a,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_mad_i32_i16 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x5a,0xd6,0x7d,0xfe,0xf5,0x01,0x00,0x38,0x00,0x00]
+
+v_mad_i32_i16 v5, exec_lo, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x5a,0xd6,0x7e,0x82,0xfd,0x01]
+
+v_mad_i32_i16 v5, exec_hi, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x5a,0xd6,0x7f,0xf8,0xf8,0x01]
+
+v_mad_i32_i16 v5, null, exec_lo, null
+// GFX12: encoding: [0x05,0x00,0x5a,0xd6,0x7c,0xfc,0xf0,0x01]
+
+v_mad_i32_i16 v5, -1, exec_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x5a,0xd6,0xc1,0xfe,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_mad_i32_i16 v5, 0.5, m0, -1 op_sel:[0,0,0,0]
+// GFX12: encoding: [0x05,0x00,0x5a,0xd6,0xff,0xfa,0x04,0x03,0x00,0x38,0x00,0x00]
+
+v_mad_i32_i16 v5, src_scc, vcc_lo, src_scc op_sel:[1,0,0,0]
+// GFX12: encoding: [0x05,0x08,0x5a,0xd6,0xfd,0xd4,0xf4,0x03]
+
+v_mad_i32_i16 v255, 0xfe0b, vcc_hi, 0.5 op_sel:[0,1,0,0] clamp
+// GFX12: encoding: [0xff,0x90,0x5a,0xd6,0xff,0xd6,0xc0,0x03,0x0b,0xfe,0x00,0x00]
+
+v_mad_i32_i24 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x0a,0xd6,0x01,0x05,0x0e,0x00]
+
+v_mad_i32_i24 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x0a,0xd6,0xff,0x05,0xa4,0x01]
+
+v_mad_i32_i24 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x0a,0xd6,0x01,0xfe,0xff,0x01]
+
+v_mad_i32_i24 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x0a,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_mad_i32_i24 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x0a,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_mad_i32_i24 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x0a,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_mad_i32_i24 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x0a,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_mad_i32_i24 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x0a,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_mad_i32_i24 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x0a,0xd6,0x7e,0x82,0xad,0x01]
+
+v_mad_i32_i24 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x0a,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_mad_i32_i24 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x0a,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_mad_i32_i24 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x0a,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_mad_i32_i24 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x0a,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_mad_i32_i24 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x0a,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_mad_i32_i24 v255, 0xaf123456, vcc_hi, null clamp
+// GFX12: encoding: [0xff,0x80,0x0a,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_mad_co_i64_i32 v[5:6], s6, s105, s105, s[6:7]
+// W32: encoding: [0x05,0x06,0xff,0xd6,0x69,0xd2,0x18,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_i64_i32 v[5:6], s6, ttmp15, ttmp15, s[104:105]
+// W32: encoding: [0x05,0x06,0xff,0xd6,0x7b,0xf6,0xa0,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_i64_i32 v[5:6], s6, m0, 0.5, ttmp[14:15]
+// W32: encoding: [0x05,0x06,0xff,0xd6,0x7d,0xe0,0xe9,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_i64_i32 v[5:6], s6, exec_lo, -1, exec
+// W32: encoding: [0x05,0x06,0xff,0xd6,0x7e,0x82,0xf9,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_i64_i32 v[5:6], s6, exec_hi, null, vcc
+// W32: encoding: [0x05,0x06,0xff,0xd6,0x7f,0xf8,0xa8,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_i64_i32 v[5:6], s105, null, exec_lo, null
+// W32: encoding: [0x05,0x69,0xff,0xd6,0x7c,0xfc,0xf0,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_i64_i32 v[5:6], vcc_lo, -1, exec_hi, -1
+// W32: encoding: [0x05,0x6a,0xff,0xd6,0xc1,0xfe,0x04,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_i64_i32 v[5:6], vcc_hi, 0.5, m0, 0xaf123456
+// W32: encoding: [0x05,0x6b,0xff,0xd6,0xf0,0xfa,0xfc,0x03,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_i64_i32 v[5:6], ttmp15, src_scc, vcc_lo, src_scc
+// W32: encoding: [0x05,0x7b,0xff,0xd6,0xfd,0xd4,0xf4,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_i64_i32 v[5:6], s[12:13], s105, s105, s[6:7]
+// W64: encoding: [0x05,0x0c,0xff,0xd6,0x69,0xd2,0x18,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_i64_i32 v[5:6], s[12:13], ttmp15, ttmp15, s[104:105]
+// W64: encoding: [0x05,0x0c,0xff,0xd6,0x7b,0xf6,0xa0,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_i64_i32 v[5:6], s[12:13], m0, 0.5, ttmp[14:15]
+// W64: encoding: [0x05,0x0c,0xff,0xd6,0x7d,0xe0,0xe9,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_i64_i32 v[5:6], s[12:13], exec_lo, -1, exec
+// W64: encoding: [0x05,0x0c,0xff,0xd6,0x7e,0x82,0xf9,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_i64_i32 v[5:6], s[12:13], exec_hi, null, vcc
+// W64: encoding: [0x05,0x0c,0xff,0xd6,0x7f,0xf8,0xa8,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_i64_i32 v[5:6], s[12:13], null, exec_lo, null
+// W64: encoding: [0x05,0x0c,0xff,0xd6,0x7c,0xfc,0xf0,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_i64_i32 v[5:6], s[104:105], -1, exec_hi, -1
+// W64: encoding: [0x05,0x68,0xff,0xd6,0xc1,0xfe,0x04,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_i64_i32 v[5:6], vcc, 0.5, m0, 0xaf123456
+// W64: encoding: [0x05,0x6a,0xff,0xd6,0xf0,0xfa,0xfc,0x03,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_i64_i32 v[5:6], ttmp[14:15], src_scc, vcc_lo, src_scc
+// W64: encoding: [0x05,0x7a,0xff,0xd6,0xfd,0xd4,0xf4,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_i64_i32 v[254:255], null, 0xaf123456, vcc_hi, 0.5 clamp
+// GFX12: encoding: [0xfe,0xfc,0xff,0xd6,0xff,0xd6,0xc0,0x03,0x56,0x34,0x12,0xaf]
+
+v_mad_u16 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x41,0xd6,0x01,0x05,0x0e,0x00]
+
+v_mad_u16 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x41,0xd6,0xff,0x05,0xa4,0x01]
+
+v_mad_u16 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x41,0xd6,0x01,0xfe,0xff,0x01]
+
+v_mad_u16 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x41,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_mad_u16 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x41,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_mad_u16 v5, vcc_hi, 0xfe0b, v255
+// GFX12: encoding: [0x05,0x00,0x41,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+
+v_mad_u16 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x41,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_mad_u16 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x41,0xd6,0x7d,0xfe,0xf5,0x01,0x00,0x38,0x00,0x00]
+
+v_mad_u16 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x41,0xd6,0x7e,0x82,0xad,0x01]
+
+v_mad_u16 v5, exec_hi, null, vcc_lo op_sel:[1,1,1,1]
+// GFX12: encoding: [0x05,0x78,0x41,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_mad_u16 v5, null, exec_lo, 0xfe0b op_sel:[0,0,0,0]
+// GFX12: encoding: [0x05,0x00,0x41,0xd6,0x7c,0xfc,0xfc,0x03,0x0b,0xfe,0x00,0x00]
+
+v_mad_u16 v5, -1, exec_hi, src_scc op_sel:[1,0,0,0]
+// GFX12: encoding: [0x05,0x08,0x41,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_mad_u16 v5, 0.5, m0, 0.5 op_sel:[0,1,0,0]
+// GFX12: encoding: [0x05,0x10,0x41,0xd6,0xff,0xfa,0xfc,0x03,0x00,0x38,0x00,0x00]
+
+v_mad_u16 v5, src_scc, vcc_lo, -1 op_sel:[0,0,1,0]
+// GFX12: encoding: [0x05,0x20,0x41,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_mad_u16 v255, 0xfe0b, vcc_hi, null op_sel:[0,0,0,1] clamp
+// GFX12: encoding: [0xff,0xc0,0x41,0xd6,0xff,0xd6,0xf0,0x01,0x0b,0xfe,0x00,0x00]
+
+v_mad_u32_u16 v5, v1, v2, v3
+// GFX12: encoding: [0x05,0x00,0x59,0xd6,0x01,0x05,0x0e,0x04]
+
+v_mad_u32_u16 v5, v255, v255, s3
+// GFX12: encoding: [0x05,0x00,0x59,0xd6,0xff,0xff,0x0f,0x00]
+
+v_mad_u32_u16 v5, s1, s2, v255
+// GFX12: encoding: [0x05,0x00,0x59,0xd6,0x01,0x04,0xfc,0x07]
+
+v_mad_u32_u16 v5, s105, s105, s105
+// GFX12: encoding: [0x05,0x00,0x59,0xd6,0x69,0xd2,0xa4,0x01]
+
+v_mad_u32_u16 v5, vcc_lo, ttmp15, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x59,0xd6,0x6a,0xf6,0xa8,0x01]
+
+v_mad_u32_u16 v5, vcc_hi, 0xfe0b, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x59,0xd6,0x6b,0xfe,0xad,0x01,0x0b,0xfe,0x00,0x00]
+
+v_mad_u32_u16 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x59,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_mad_u32_u16 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x59,0xd6,0x7d,0xfe,0xf5,0x01,0x00,0x38,0x00,0x00]
+
+v_mad_u32_u16 v5, exec_lo, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x59,0xd6,0x7e,0x82,0xfd,0x01]
+
+v_mad_u32_u16 v5, exec_hi, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x59,0xd6,0x7f,0xf8,0xf8,0x01]
+
+v_mad_u32_u16 v5, null, exec_lo, null
+// GFX12: encoding: [0x05,0x00,0x59,0xd6,0x7c,0xfc,0xf0,0x01]
+
+v_mad_u32_u16 v5, -1, exec_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x59,0xd6,0xc1,0xfe,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_mad_u32_u16 v5, 0.5, m0, -1 op_sel:[0,0,0,0]
+// GFX12: encoding: [0x05,0x00,0x59,0xd6,0xff,0xfa,0x04,0x03,0x00,0x38,0x00,0x00]
+
+v_mad_u32_u16 v5, src_scc, vcc_lo, src_scc op_sel:[1,0,0,0]
+// GFX12: encoding: [0x05,0x08,0x59,0xd6,0xfd,0xd4,0xf4,0x03]
+
+v_mad_u32_u16 v255, 0xfe0b, vcc_hi, 0.5 op_sel:[0,1,0,0] clamp
+// GFX12: encoding: [0xff,0x90,0x59,0xd6,0xff,0xd6,0xc0,0x03,0x0b,0xfe,0x00,0x00]
+
+v_mad_u32_u24 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x0b,0xd6,0x01,0x05,0x0e,0x00]
+
+v_mad_u32_u24 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x0b,0xd6,0xff,0x05,0xa4,0x01]
+
+v_mad_u32_u24 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x0b,0xd6,0x01,0xfe,0xff,0x01]
+
+v_mad_u32_u24 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x0b,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_mad_u32_u24 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x0b,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_mad_u32_u24 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x0b,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_mad_u32_u24 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x0b,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_mad_u32_u24 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x0b,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_mad_u32_u24 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x0b,0xd6,0x7e,0x82,0xad,0x01]
+
+v_mad_u32_u24 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x0b,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_mad_u32_u24 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x0b,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_mad_u32_u24 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x0b,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_mad_u32_u24 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x0b,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_mad_u32_u24 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x0b,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_mad_u32_u24 v255, 0xaf123456, vcc_hi, null clamp
+// GFX12: encoding: [0xff,0x80,0x0b,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_mad_co_u64_u32 v[5:6], s6, s105, s105, s[6:7]
+// W32: encoding: [0x05,0x06,0xfe,0xd6,0x69,0xd2,0x18,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_u64_u32 v[5:6], s6, ttmp15, ttmp15, s[104:105]
+// W32: encoding: [0x05,0x06,0xfe,0xd6,0x7b,0xf6,0xa0,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_u64_u32 v[5:6], s6, m0, 0.5, ttmp[14:15]
+// W32: encoding: [0x05,0x06,0xfe,0xd6,0x7d,0xe0,0xe9,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_u64_u32 v[5:6], s6, exec_lo, -1, exec
+// W32: encoding: [0x05,0x06,0xfe,0xd6,0x7e,0x82,0xf9,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_u64_u32 v[5:6], s6, exec_hi, null, vcc
+// W32: encoding: [0x05,0x06,0xfe,0xd6,0x7f,0xf8,0xa8,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_u64_u32 v[5:6], s105, null, exec_lo, null
+// W32: encoding: [0x05,0x69,0xfe,0xd6,0x7c,0xfc,0xf0,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_u64_u32 v[5:6], vcc_lo, -1, exec_hi, -1
+// W32: encoding: [0x05,0x6a,0xfe,0xd6,0xc1,0xfe,0x04,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_u64_u32 v[5:6], vcc_hi, 0.5, m0, 0xaf123456
+// W32: encoding: [0x05,0x6b,0xfe,0xd6,0xf0,0xfa,0xfc,0x03,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_u64_u32 v[5:6], ttmp15, src_scc, vcc_lo, src_scc
+// W32: encoding: [0x05,0x7b,0xfe,0xd6,0xfd,0xd4,0xf4,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_u64_u32 v[5:6], s[12:13], s105, s105, s[6:7]
+// W64: encoding: [0x05,0x0c,0xfe,0xd6,0x69,0xd2,0x18,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_u64_u32 v[5:6], s[12:13], ttmp15, ttmp15, s[104:105]
+// W64: encoding: [0x05,0x0c,0xfe,0xd6,0x7b,0xf6,0xa0,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_u64_u32 v[5:6], s[12:13], m0, 0.5, ttmp[14:15]
+// W64: encoding: [0x05,0x0c,0xfe,0xd6,0x7d,0xe0,0xe9,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_u64_u32 v[5:6], s[12:13], exec_lo, -1, exec
+// W64: encoding: [0x05,0x0c,0xfe,0xd6,0x7e,0x82,0xf9,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_u64_u32 v[5:6], s[12:13], exec_hi, null, vcc
+// W64: encoding: [0x05,0x0c,0xfe,0xd6,0x7f,0xf8,0xa8,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_u64_u32 v[5:6], s[12:13], null, exec_lo, null
+// W64: encoding: [0x05,0x0c,0xfe,0xd6,0x7c,0xfc,0xf0,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_u64_u32 v[5:6], s[104:105], -1, exec_hi, -1
+// W64: encoding: [0x05,0x68,0xfe,0xd6,0xc1,0xfe,0x04,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_u64_u32 v[5:6], vcc, 0.5, m0, 0xaf123456
+// W64: encoding: [0x05,0x6a,0xfe,0xd6,0xf0,0xfa,0xfc,0x03,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_u64_u32 v[5:6], ttmp[14:15], src_scc, vcc_lo, src_scc
+// W64: encoding: [0x05,0x7a,0xfe,0xd6,0xfd,0xd4,0xf4,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_co_u64_u32 v[254:255], null, 0xaf123456, vcc_hi, 0.5 clamp
+// GFX12: encoding: [0xfe,0xfc,0xfe,0xd6,0xff,0xd6,0xc0,0x03,0x56,0x34,0x12,0xaf]
+
+v_max3_num_f16 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x2c,0xd6,0x01,0x05,0x0e,0x00]
+
+v_max3_num_f16 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x2c,0xd6,0xff,0x05,0xa4,0x01]
+
+v_max3_num_f16 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x2c,0xd6,0x01,0xfe,0xff,0x01]
+
+v_max3_num_f16 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x2c,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_max3_num_f16 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x2c,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_max3_num_f16 v5, vcc_hi, 0xfe0b, v255
+// GFX12: encoding: [0x05,0x00,0x2c,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+
+v_max3_num_f16 v5, -|ttmp15|, -|src_scc|, -|ttmp15|
+// GFX12: encoding: [0x05,0x07,0x2c,0xd6,0x7b,0xfa,0xed,0xe1]
+
+v_max3_num_f16 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x2c,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_max3_num_f16 v5, |exec_lo|, -1, vcc_hi
+// GFX12: encoding: [0x05,0x01,0x2c,0xd6,0x7e,0x82,0xad,0x01]
+
+v_max3_num_f16 v5, -|exec_hi|, null, -|vcc_lo| op_sel:[1,1,1,1]
+// GFX12: encoding: [0x05,0x7d,0x2c,0xd6,0x7f,0xf8,0xa8,0xa1]
+
+v_max3_num_f16 v5, null, exec_lo, -|0xfe0b| op_sel:[0,0,0,0]
+// GFX12: encoding: [0x05,0x04,0x2c,0xd6,0x7c,0xfc,0xfc,0x83,0x0b,0xfe,0x00,0x00]
+
+v_max3_num_f16 v5, -1, -|exec_hi|, -|src_scc| op_sel:[1,0,0,0]
+// GFX12: encoding: [0x05,0x0e,0x2c,0xd6,0xc1,0xfe,0xf4,0xc3]
+
+v_max3_num_f16 v5, 0.5, -m0, 0.5 op_sel:[0,1,0,0]
+// GFX12: encoding: [0x05,0x10,0x2c,0xd6,0xf0,0xfa,0xc0,0x43]
+
+v_max3_num_f16 v5, -src_scc, |vcc_lo|, -1 op_sel:[0,0,1,0]
+// GFX12: encoding: [0x05,0x22,0x2c,0xd6,0xfd,0xd4,0x04,0x23]
+
+v_max3_num_f16 v255, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] clamp
+// GFX12: encoding: [0xff,0xc3,0x2c,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
+
+v_max3_num_f32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x2a,0xd6,0x01,0x05,0x0e,0x00]
+
+v_max3_num_f32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x2a,0xd6,0xff,0x05,0xa4,0x01]
+
+v_max3_num_f32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x2a,0xd6,0x01,0xfe,0xff,0x01]
+
+v_max3_num_f32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x2a,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_max3_num_f32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x2a,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_max3_num_f32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x2a,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_max3_num_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15|
+// GFX12: encoding: [0x05,0x07,0x2a,0xd6,0x7b,0xfa,0xed,0xe1]
+
+v_max3_num_f32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x2a,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_max3_num_f32 v5, |exec_lo|, -1, vcc_hi
+// GFX12: encoding: [0x05,0x01,0x2a,0xd6,0x7e,0x82,0xad,0x01]
+
+v_max3_num_f32 v5, -|exec_hi|, null, -|vcc_lo|
+// GFX12: encoding: [0x05,0x05,0x2a,0xd6,0x7f,0xf8,0xa8,0xa1]
+
+v_max3_num_f32 v5, null, exec_lo, -|0xaf123456|
+// GFX12: encoding: [0x05,0x04,0x2a,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+
+v_max3_num_f32 v5, -1, -|exec_hi|, -|src_scc|
+// GFX12: encoding: [0x05,0x06,0x2a,0xd6,0xc1,0xfe,0xf4,0xc3]
+
+v_max3_num_f32 v5, 0.5, -m0, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x2a,0xd6,0xf0,0xfa,0xc0,0x4b]
+
+v_max3_num_f32 v5, -src_scc, |vcc_lo|, -1 mul:4
+// GFX12: encoding: [0x05,0x02,0x2a,0xd6,0xfd,0xd4,0x04,0x33]
+
+v_max3_num_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2
+// GFX12: encoding: [0xff,0x83,0x2a,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+
+v_max3_i16 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x4d,0xd6,0x01,0x05,0x0e,0x00]
+
+v_max3_i16 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x4d,0xd6,0xff,0x05,0xa4,0x01]
+
+v_max3_i16 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x4d,0xd6,0x01,0xfe,0xff,0x01]
+
+v_max3_i16 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x4d,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_max3_i16 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x4d,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_max3_i16 v5, vcc_hi, 0xfe0b, v255
+// GFX12: encoding: [0x05,0x00,0x4d,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+
+v_max3_i16 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x4d,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_max3_i16 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x4d,0xd6,0x7d,0xfe,0xf5,0x01,0x00,0x38,0x00,0x00]
+
+v_max3_i16 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x4d,0xd6,0x7e,0x82,0xad,0x01]
+
+v_max3_i16 v5, exec_hi, null, vcc_lo op_sel:[1,1,1,1]
+// GFX12: encoding: [0x05,0x78,0x4d,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_max3_i16 v5, null, exec_lo, 0xfe0b op_sel:[0,0,0,0]
+// GFX12: encoding: [0x05,0x00,0x4d,0xd6,0x7c,0xfc,0xfc,0x03,0x0b,0xfe,0x00,0x00]
+
+v_max3_i16 v5, -1, exec_hi, src_scc op_sel:[1,0,0,0]
+// GFX12: encoding: [0x05,0x08,0x4d,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_max3_i16 v5, 0.5, m0, 0.5 op_sel:[0,1,0,0]
+// GFX12: encoding: [0x05,0x10,0x4d,0xd6,0xff,0xfa,0xfc,0x03,0x00,0x38,0x00,0x00]
+
+v_max3_i16 v5, src_scc, vcc_lo, -1 op_sel:[0,0,1,0]
+// GFX12: encoding: [0x05,0x20,0x4d,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_max3_i16 v255, 0xfe0b, vcc_hi, null op_sel:[0,0,0,1]
+// GFX12: encoding: [0xff,0x40,0x4d,0xd6,0xff,0xd6,0xf0,0x01,0x0b,0xfe,0x00,0x00]
+
+v_max3_i32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x1d,0xd6,0x01,0x05,0x0e,0x00]
+
+v_max3_i32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x1d,0xd6,0xff,0x05,0xa4,0x01]
+
+v_max3_i32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x1d,0xd6,0x01,0xfe,0xff,0x01]
+
+v_max3_i32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x1d,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_max3_i32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x1d,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_max3_i32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x1d,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_max3_i32 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x1d,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_max3_i32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x1d,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_max3_i32 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x1d,0xd6,0x7e,0x82,0xad,0x01]
+
+v_max3_i32 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x1d,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_max3_i32 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x1d,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_max3_i32 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x1d,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_max3_i32 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x1d,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_max3_i32 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x1d,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_max3_i32 v255, 0xaf123456, vcc_hi, null
+// GFX12: encoding: [0xff,0x00,0x1d,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_max3_u16 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x4e,0xd6,0x01,0x05,0x0e,0x00]
+
+v_max3_u16 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x4e,0xd6,0xff,0x05,0xa4,0x01]
+
+v_max3_u16 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x4e,0xd6,0x01,0xfe,0xff,0x01]
+
+v_max3_u16 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x4e,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_max3_u16 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x4e,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_max3_u16 v5, vcc_hi, 0xfe0b, v255
+// GFX12: encoding: [0x05,0x00,0x4e,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+
+v_max3_u16 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x4e,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_max3_u16 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x4e,0xd6,0x7d,0xfe,0xf5,0x01,0x00,0x38,0x00,0x00]
+
+v_max3_u16 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x4e,0xd6,0x7e,0x82,0xad,0x01]
+
+v_max3_u16 v5, exec_hi, null, vcc_lo op_sel:[1,1,1,1]
+// GFX12: encoding: [0x05,0x78,0x4e,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_max3_u16 v5, null, exec_lo, 0xfe0b op_sel:[0,0,0,0]
+// GFX12: encoding: [0x05,0x00,0x4e,0xd6,0x7c,0xfc,0xfc,0x03,0x0b,0xfe,0x00,0x00]
+
+v_max3_u16 v5, -1, exec_hi, src_scc op_sel:[1,0,0,0]
+// GFX12: encoding: [0x05,0x08,0x4e,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_max3_u16 v5, 0.5, m0, 0.5 op_sel:[0,1,0,0]
+// GFX12: encoding: [0x05,0x10,0x4e,0xd6,0xff,0xfa,0xfc,0x03,0x00,0x38,0x00,0x00]
+
+v_max3_u16 v5, src_scc, vcc_lo, -1 op_sel:[0,0,1,0]
+// GFX12: encoding: [0x05,0x20,0x4e,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_max3_u16 v255, 0xfe0b, vcc_hi, null op_sel:[0,0,0,1]
+// GFX12: encoding: [0xff,0x40,0x4e,0xd6,0xff,0xd6,0xf0,0x01,0x0b,0xfe,0x00,0x00]
+
+v_max3_u32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x1e,0xd6,0x01,0x05,0x0e,0x00]
+
+v_max3_u32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x1e,0xd6,0xff,0x05,0xa4,0x01]
+
+v_max3_u32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x1e,0xd6,0x01,0xfe,0xff,0x01]
+
+v_max3_u32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x1e,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_max3_u32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x1e,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_max3_u32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x1e,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_max3_u32 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x1e,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_max3_u32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x1e,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_max3_u32 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x1e,0xd6,0x7e,0x82,0xad,0x01]
+
+v_max3_u32 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x1e,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_max3_u32 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x1e,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_max3_u32 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x1e,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_max3_u32 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x1e,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_max3_u32 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x1e,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_max3_u32 v255, 0xaf123456, vcc_hi, null
+// GFX12: encoding: [0xff,0x00,0x1e,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_max_i16 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x0a,0xd7,0x01,0x05,0x02,0x00]
+
+v_max_i16 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x0a,0xd7,0xff,0xff,0x03,0x00]
+
+v_max_i16 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x0a,0xd7,0x01,0x04,0x00,0x00]
+
+v_max_i16 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x0a,0xd7,0x69,0xd2,0x00,0x00]
+
+v_max_i16 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x0a,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_max_i16 v5, vcc_hi, 0xfe0b
+// GFX12: encoding: [0x05,0x00,0x0a,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_max_i16 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x0a,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_max_i16 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x0a,0xd7,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_max_i16 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x0a,0xd7,0x7e,0x82,0x01,0x00]
+
+v_max_i16 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x0a,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_max_i16 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x0a,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_max_i16 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x0a,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_max_i16 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x0a,0xd7,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_max_i16 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x0a,0xd7,0xfd,0xd4,0x00,0x00]
+
+v_max_i16 v255, 0xfe0b, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x0a,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_max_u16 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x09,0xd7,0x01,0x05,0x02,0x00]
+
+v_max_u16 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x09,0xd7,0xff,0xff,0x03,0x00]
+
+v_max_u16 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x09,0xd7,0x01,0x04,0x00,0x00]
+
+v_max_u16 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x09,0xd7,0x69,0xd2,0x00,0x00]
+
+v_max_u16 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x09,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_max_u16 v5, vcc_hi, 0xfe0b
+// GFX12: encoding: [0x05,0x00,0x09,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_max_u16 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x09,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_max_u16 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x09,0xd7,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_max_u16 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x09,0xd7,0x7e,0x82,0x01,0x00]
+
+v_max_u16 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x09,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_max_u16 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x09,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_max_u16 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x09,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_max_u16 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x09,0xd7,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_max_u16 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x09,0xd7,0xfd,0xd4,0x00,0x00]
+
+v_max_u16 v255, 0xfe0b, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x09,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_maxmin_num_f16 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x6b,0xd6,0x01,0x05,0x0e,0x00]
+
+v_maxmin_num_f16 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x6b,0xd6,0xff,0x05,0xa4,0x01]
+
+v_maxmin_num_f16 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x6b,0xd6,0x01,0xfe,0xff,0x01]
+
+v_maxmin_num_f16 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x6b,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_maxmin_num_f16 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x6b,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_maxmin_num_f16 v5, vcc_hi, 0xfe0b, v255
+// GFX12: encoding: [0x05,0x00,0x6b,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+
+v_maxmin_num_f16 v5, -|ttmp15|, -|src_scc|, -|ttmp15|
+// GFX12: encoding: [0x05,0x07,0x6b,0xd6,0x7b,0xfa,0xed,0xe1]
+
+v_maxmin_num_f16 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x6b,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_maxmin_num_f16 v5, |exec_lo|, -1, vcc_hi
+// GFX12: encoding: [0x05,0x01,0x6b,0xd6,0x7e,0x82,0xad,0x01]
+
+v_maxmin_num_f16 v5, -|exec_hi|, null, -|vcc_lo|
+// GFX12: encoding: [0x05,0x05,0x6b,0xd6,0x7f,0xf8,0xa8,0xa1]
+
+v_maxmin_num_f16 v5, null, exec_lo, -|0xfe0b|
+// GFX12: encoding: [0x05,0x04,0x6b,0xd6,0x7c,0xfc,0xfc,0x83,0x0b,0xfe,0x00,0x00]
+
+v_maxmin_num_f16 v5, -1, -|exec_hi|, -|src_scc|
+// GFX12: encoding: [0x05,0x06,0x6b,0xd6,0xc1,0xfe,0xf4,0xc3]
+
+v_maxmin_num_f16 v5, 0.5, -m0, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x6b,0xd6,0xf0,0xfa,0xc0,0x4b]
+
+v_maxmin_num_f16 v5, -src_scc, |vcc_lo|, -1 mul:4
+// GFX12: encoding: [0x05,0x02,0x6b,0xd6,0xfd,0xd4,0x04,0x33]
+
+v_maxmin_num_f16 v255, -|0xfe0b|, -|vcc_hi|, null clamp div:2
+// GFX12: encoding: [0xff,0x83,0x6b,0xd6,0xff,0xd6,0xf0,0x79,0x0b,0xfe,0x00,0x00]
+
+v_maxmin_num_f32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x69,0xd6,0x01,0x05,0x0e,0x00]
+
+v_maxmin_num_f32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x69,0xd6,0xff,0x05,0xa4,0x01]
+
+v_maxmin_num_f32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x69,0xd6,0x01,0xfe,0xff,0x01]
+
+v_maxmin_num_f32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x69,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_maxmin_num_f32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x69,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_maxmin_num_f32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x69,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_maxmin_num_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15|
+// GFX12: encoding: [0x05,0x07,0x69,0xd6,0x7b,0xfa,0xed,0xe1]
+
+v_maxmin_num_f32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x69,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_maxmin_num_f32 v5, |exec_lo|, -1, vcc_hi
+// GFX12: encoding: [0x05,0x01,0x69,0xd6,0x7e,0x82,0xad,0x01]
+
+v_maxmin_num_f32 v5, -|exec_hi|, null, -|vcc_lo|
+// GFX12: encoding: [0x05,0x05,0x69,0xd6,0x7f,0xf8,0xa8,0xa1]
+
+v_maxmin_num_f32 v5, null, exec_lo, -|0xaf123456|
+// GFX12: encoding: [0x05,0x04,0x69,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+
+v_maxmin_num_f32 v5, -1, -|exec_hi|, -|src_scc|
+// GFX12: encoding: [0x05,0x06,0x69,0xd6,0xc1,0xfe,0xf4,0xc3]
+
+v_maxmin_num_f32 v5, 0.5, -m0, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x69,0xd6,0xf0,0xfa,0xc0,0x4b]
+
+v_maxmin_num_f32 v5, -src_scc, |vcc_lo|, -1 mul:4
+// GFX12: encoding: [0x05,0x02,0x69,0xd6,0xfd,0xd4,0x04,0x33]
+
+v_maxmin_num_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2
+// GFX12: encoding: [0xff,0x83,0x69,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+
+v_maxmin_i32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x64,0xd6,0x01,0x05,0x0e,0x00]
+
+v_maxmin_i32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x64,0xd6,0xff,0x05,0xa4,0x01]
+
+v_maxmin_i32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x64,0xd6,0x01,0xfe,0xff,0x01]
+
+v_maxmin_i32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x64,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_maxmin_i32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x64,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_maxmin_i32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x64,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_maxmin_i32 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x64,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_maxmin_i32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x64,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_maxmin_i32 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x64,0xd6,0x7e,0x82,0xad,0x01]
+
+v_maxmin_i32 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x64,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_maxmin_i32 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x64,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_maxmin_i32 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x64,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_maxmin_i32 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x64,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_maxmin_i32 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x64,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_maxmin_i32 v255, 0xaf123456, vcc_hi, null
+// GFX12: encoding: [0xff,0x00,0x64,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_maxmin_u32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x62,0xd6,0x01,0x05,0x0e,0x00]
+
+v_maxmin_u32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x62,0xd6,0xff,0x05,0xa4,0x01]
+
+v_maxmin_u32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x62,0xd6,0x01,0xfe,0xff,0x01]
+
+v_maxmin_u32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x62,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_maxmin_u32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x62,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_maxmin_u32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x62,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_maxmin_u32 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x62,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_maxmin_u32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x62,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_maxmin_u32 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x62,0xd6,0x7e,0x82,0xad,0x01]
+
+v_maxmin_u32 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x62,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_maxmin_u32 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x62,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_maxmin_u32 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x62,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_maxmin_u32 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x62,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_maxmin_u32 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x62,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_maxmin_u32 v255, 0xaf123456, vcc_hi, null
+// GFX12: encoding: [0xff,0x00,0x62,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_mbcnt_hi_u32_b32 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x20,0xd7,0x01,0x05,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x20,0xd7,0xff,0xff,0x03,0x00]
+
+v_mbcnt_hi_u32_b32 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x20,0xd7,0x01,0x04,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x20,0xd7,0x69,0xd2,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x20,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x20,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_mbcnt_hi_u32_b32 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x20,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_mbcnt_hi_u32_b32 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x20,0xd7,0x7d,0xe0,0x01,0x00]
+
+v_mbcnt_hi_u32_b32 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x20,0xd7,0x7e,0x82,0x01,0x00]
+
+v_mbcnt_hi_u32_b32 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x20,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x20,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x20,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x20,0xd7,0xf0,0xfa,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x20,0xd7,0xfd,0xd4,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v255, 0xaf123456, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x20,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_mbcnt_lo_u32_b32 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x1f,0xd7,0x01,0x05,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x1f,0xd7,0xff,0xff,0x03,0x00]
+
+v_mbcnt_lo_u32_b32 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x1f,0xd7,0x01,0x04,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x1f,0xd7,0x69,0xd2,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x1f,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x1f,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_mbcnt_lo_u32_b32 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x1f,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_mbcnt_lo_u32_b32 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x1f,0xd7,0x7d,0xe0,0x01,0x00]
+
+v_mbcnt_lo_u32_b32 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x1f,0xd7,0x7e,0x82,0x01,0x00]
+
+v_mbcnt_lo_u32_b32 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x1f,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x1f,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x1f,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x1f,0xd7,0xf0,0xfa,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x1f,0xd7,0xfd,0xd4,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v255, 0xaf123456, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x1f,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_med3_num_f16 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x32,0xd6,0x01,0x05,0x0e,0x00]
+
+v_med3_num_f16 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x32,0xd6,0xff,0x05,0xa4,0x01]
+
+v_med3_num_f16 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x32,0xd6,0x01,0xfe,0xff,0x01]
+
+v_med3_num_f16 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x32,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_med3_num_f16 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x32,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_med3_num_f16 v5, vcc_hi, 0xfe0b, v255
+// GFX12: encoding: [0x05,0x00,0x32,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+
+v_med3_num_f16 v5, -|ttmp15|, -|src_scc|, -|ttmp15|
+// GFX12: encoding: [0x05,0x07,0x32,0xd6,0x7b,0xfa,0xed,0xe1]
+
+v_med3_num_f16 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x32,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_med3_num_f16 v5, |exec_lo|, -1, vcc_hi
+// GFX12: encoding: [0x05,0x01,0x32,0xd6,0x7e,0x82,0xad,0x01]
+
+v_med3_num_f16 v5, -|exec_hi|, null, -|vcc_lo| op_sel:[1,1,1,1]
+// GFX12: encoding: [0x05,0x7d,0x32,0xd6,0x7f,0xf8,0xa8,0xa1]
+
+v_med3_num_f16 v5, null, exec_lo, -|0xfe0b| op_sel:[0,0,0,0]
+// GFX12: encoding: [0x05,0x04,0x32,0xd6,0x7c,0xfc,0xfc,0x83,0x0b,0xfe,0x00,0x00]
+
+v_med3_num_f16 v5, -1, -|exec_hi|, -|src_scc| op_sel:[1,0,0,0]
+// GFX12: encoding: [0x05,0x0e,0x32,0xd6,0xc1,0xfe,0xf4,0xc3]
+
+v_med3_num_f16 v5, 0.5, -m0, 0.5 op_sel:[0,1,0,0]
+// GFX12: encoding: [0x05,0x10,0x32,0xd6,0xf0,0xfa,0xc0,0x43]
+
+v_med3_num_f16 v5, -src_scc, |vcc_lo|, -1 op_sel:[0,0,1,0]
+// GFX12: encoding: [0x05,0x22,0x32,0xd6,0xfd,0xd4,0x04,0x23]
+
+v_med3_num_f16 v255, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] clamp
+// GFX12: encoding: [0xff,0xc3,0x32,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
+
+v_med3_num_f32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x31,0xd6,0x01,0x05,0x0e,0x00]
+
+v_med3_num_f32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x31,0xd6,0xff,0x05,0xa4,0x01]
+
+v_med3_num_f32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x31,0xd6,0x01,0xfe,0xff,0x01]
+
+v_med3_num_f32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x31,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_med3_num_f32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x31,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_med3_num_f32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x31,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_med3_num_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15|
+// GFX12: encoding: [0x05,0x07,0x31,0xd6,0x7b,0xfa,0xed,0xe1]
+
+v_med3_num_f32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x31,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_med3_num_f32 v5, |exec_lo|, -1, vcc_hi
+// GFX12: encoding: [0x05,0x01,0x31,0xd6,0x7e,0x82,0xad,0x01]
+
+v_med3_num_f32 v5, -|exec_hi|, null, -|vcc_lo|
+// GFX12: encoding: [0x05,0x05,0x31,0xd6,0x7f,0xf8,0xa8,0xa1]
+
+v_med3_num_f32 v5, null, exec_lo, -|0xaf123456|
+// GFX12: encoding: [0x05,0x04,0x31,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+
+v_med3_num_f32 v5, -1, -|exec_hi|, -|src_scc|
+// GFX12: encoding: [0x05,0x06,0x31,0xd6,0xc1,0xfe,0xf4,0xc3]
+
+v_med3_num_f32 v5, 0.5, -m0, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x31,0xd6,0xf0,0xfa,0xc0,0x4b]
+
+v_med3_num_f32 v5, -src_scc, |vcc_lo|, -1 mul:4
+// GFX12: encoding: [0x05,0x02,0x31,0xd6,0xfd,0xd4,0x04,0x33]
+
+v_med3_num_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2
+// GFX12: encoding: [0xff,0x83,0x31,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+
+v_med3_i16 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x50,0xd6,0x01,0x05,0x0e,0x00]
+
+v_med3_i16 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x50,0xd6,0xff,0x05,0xa4,0x01]
+
+v_med3_i16 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x50,0xd6,0x01,0xfe,0xff,0x01]
+
+v_med3_i16 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x50,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_med3_i16 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x50,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_med3_i16 v5, vcc_hi, 0xfe0b, v255
+// GFX12: encoding: [0x05,0x00,0x50,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+
+v_med3_i16 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x50,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_med3_i16 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x50,0xd6,0x7d,0xfe,0xf5,0x01,0x00,0x38,0x00,0x00]
+
+v_med3_i16 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x50,0xd6,0x7e,0x82,0xad,0x01]
+
+v_med3_i16 v5, exec_hi, null, vcc_lo op_sel:[1,1,1,1]
+// GFX12: encoding: [0x05,0x78,0x50,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_med3_i16 v5, null, exec_lo, 0xfe0b op_sel:[0,0,0,0]
+// GFX12: encoding: [0x05,0x00,0x50,0xd6,0x7c,0xfc,0xfc,0x03,0x0b,0xfe,0x00,0x00]
+
+v_med3_i16 v5, -1, exec_hi, src_scc op_sel:[1,0,0,0]
+// GFX12: encoding: [0x05,0x08,0x50,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_med3_i16 v5, 0.5, m0, 0.5 op_sel:[0,1,0,0]
+// GFX12: encoding: [0x05,0x10,0x50,0xd6,0xff,0xfa,0xfc,0x03,0x00,0x38,0x00,0x00]
+
+v_med3_i16 v5, src_scc, vcc_lo, -1 op_sel:[0,0,1,0]
+// GFX12: encoding: [0x05,0x20,0x50,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_med3_i16 v255, 0xfe0b, vcc_hi, null op_sel:[0,0,0,1]
+// GFX12: encoding: [0xff,0x40,0x50,0xd6,0xff,0xd6,0xf0,0x01,0x0b,0xfe,0x00,0x00]
+
+v_med3_i32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x20,0xd6,0x01,0x05,0x0e,0x00]
+
+v_med3_i32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x20,0xd6,0xff,0x05,0xa4,0x01]
+
+v_med3_i32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x20,0xd6,0x01,0xfe,0xff,0x01]
+
+v_med3_i32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x20,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_med3_i32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x20,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_med3_i32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x20,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_med3_i32 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x20,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_med3_i32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x20,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_med3_i32 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x20,0xd6,0x7e,0x82,0xad,0x01]
+
+v_med3_i32 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x20,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_med3_i32 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x20,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_med3_i32 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x20,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_med3_i32 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x20,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_med3_i32 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x20,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_med3_i32 v255, 0xaf123456, vcc_hi, null
+// GFX12: encoding: [0xff,0x00,0x20,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_med3_u16 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x51,0xd6,0x01,0x05,0x0e,0x00]
+
+v_med3_u16 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x51,0xd6,0xff,0x05,0xa4,0x01]
+
+v_med3_u16 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x51,0xd6,0x01,0xfe,0xff,0x01]
+
+v_med3_u16 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x51,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_med3_u16 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x51,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_med3_u16 v5, vcc_hi, 0xfe0b, v255
+// GFX12: encoding: [0x05,0x00,0x51,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+
+v_med3_u16 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x51,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_med3_u16 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x51,0xd6,0x7d,0xfe,0xf5,0x01,0x00,0x38,0x00,0x00]
+
+v_med3_u16 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x51,0xd6,0x7e,0x82,0xad,0x01]
+
+v_med3_u16 v5, exec_hi, null, vcc_lo op_sel:[1,1,1,1]
+// GFX12: encoding: [0x05,0x78,0x51,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_med3_u16 v5, null, exec_lo, 0xfe0b op_sel:[0,0,0,0]
+// GFX12: encoding: [0x05,0x00,0x51,0xd6,0x7c,0xfc,0xfc,0x03,0x0b,0xfe,0x00,0x00]
+
+v_med3_u16 v5, -1, exec_hi, src_scc op_sel:[1,0,0,0]
+// GFX12: encoding: [0x05,0x08,0x51,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_med3_u16 v5, 0.5, m0, 0.5 op_sel:[0,1,0,0]
+// GFX12: encoding: [0x05,0x10,0x51,0xd6,0xff,0xfa,0xfc,0x03,0x00,0x38,0x00,0x00]
+
+v_med3_u16 v5, src_scc, vcc_lo, -1 op_sel:[0,0,1,0]
+// GFX12: encoding: [0x05,0x20,0x51,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_med3_u16 v255, 0xfe0b, vcc_hi, null op_sel:[0,0,0,1]
+// GFX12: encoding: [0xff,0x40,0x51,0xd6,0xff,0xd6,0xf0,0x01,0x0b,0xfe,0x00,0x00]
+
+v_med3_u32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x21,0xd6,0x01,0x05,0x0e,0x00]
+
+v_med3_u32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x21,0xd6,0xff,0x05,0xa4,0x01]
+
+v_med3_u32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x21,0xd6,0x01,0xfe,0xff,0x01]
+
+v_med3_u32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x21,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_med3_u32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x21,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_med3_u32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x21,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_med3_u32 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x21,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_med3_u32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x21,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_med3_u32 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x21,0xd6,0x7e,0x82,0xad,0x01]
+
+v_med3_u32 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x21,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_med3_u32 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x21,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_med3_u32 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x21,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_med3_u32 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x21,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_med3_u32 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x21,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_med3_u32 v255, 0xaf123456, vcc_hi, null
+// GFX12: encoding: [0xff,0x00,0x21,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_min3_num_f16 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x2b,0xd6,0x01,0x05,0x0e,0x00]
+
+v_min3_num_f16 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x2b,0xd6,0xff,0x05,0xa4,0x01]
+
+v_min3_num_f16 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x2b,0xd6,0x01,0xfe,0xff,0x01]
+
+v_min3_num_f16 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x2b,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_min3_num_f16 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x2b,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_min3_num_f16 v5, vcc_hi, 0xfe0b, v255
+// GFX12: encoding: [0x05,0x00,0x2b,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+
+v_min3_num_f16 v5, -|ttmp15|, -|src_scc|, -|ttmp15|
+// GFX12: encoding: [0x05,0x07,0x2b,0xd6,0x7b,0xfa,0xed,0xe1]
+
+v_min3_num_f16 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x2b,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_min3_num_f16 v5, |exec_lo|, -1, vcc_hi
+// GFX12: encoding: [0x05,0x01,0x2b,0xd6,0x7e,0x82,0xad,0x01]
+
+v_min3_num_f16 v5, -|exec_hi|, null, -|vcc_lo| op_sel:[1,1,1,1]
+// GFX12: encoding: [0x05,0x7d,0x2b,0xd6,0x7f,0xf8,0xa8,0xa1]
+
+v_min3_num_f16 v5, null, exec_lo, -|0xfe0b| op_sel:[0,0,0,0]
+// GFX12: encoding: [0x05,0x04,0x2b,0xd6,0x7c,0xfc,0xfc,0x83,0x0b,0xfe,0x00,0x00]
+
+v_min3_num_f16 v5, -1, -|exec_hi|, -|src_scc| op_sel:[1,0,0,0]
+// GFX12: encoding: [0x05,0x0e,0x2b,0xd6,0xc1,0xfe,0xf4,0xc3]
+
+v_min3_num_f16 v5, 0.5, -m0, 0.5 op_sel:[0,1,0,0]
+// GFX12: encoding: [0x05,0x10,0x2b,0xd6,0xf0,0xfa,0xc0,0x43]
+
+v_min3_num_f16 v5, -src_scc, |vcc_lo|, -1 op_sel:[0,0,1,0]
+// GFX12: encoding: [0x05,0x22,0x2b,0xd6,0xfd,0xd4,0x04,0x23]
+
+v_min3_num_f16 v255, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] clamp
+// GFX12: encoding: [0xff,0xc3,0x2b,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
+
+v_min3_num_f32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x29,0xd6,0x01,0x05,0x0e,0x00]
+
+v_min3_num_f32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x29,0xd6,0xff,0x05,0xa4,0x01]
+
+v_min3_num_f32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x29,0xd6,0x01,0xfe,0xff,0x01]
+
+v_min3_num_f32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x29,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_min3_num_f32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x29,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_min3_num_f32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x29,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_min3_num_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15|
+// GFX12: encoding: [0x05,0x07,0x29,0xd6,0x7b,0xfa,0xed,0xe1]
+
+v_min3_num_f32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x29,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_min3_num_f32 v5, |exec_lo|, -1, vcc_hi
+// GFX12: encoding: [0x05,0x01,0x29,0xd6,0x7e,0x82,0xad,0x01]
+
+v_min3_num_f32 v5, -|exec_hi|, null, -|vcc_lo|
+// GFX12: encoding: [0x05,0x05,0x29,0xd6,0x7f,0xf8,0xa8,0xa1]
+
+v_min3_num_f32 v5, null, exec_lo, -|0xaf123456|
+// GFX12: encoding: [0x05,0x04,0x29,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+
+v_min3_num_f32 v5, -1, -|exec_hi|, -|src_scc|
+// GFX12: encoding: [0x05,0x06,0x29,0xd6,0xc1,0xfe,0xf4,0xc3]
+
+v_min3_num_f32 v5, 0.5, -m0, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x29,0xd6,0xf0,0xfa,0xc0,0x4b]
+
+v_min3_num_f32 v5, -src_scc, |vcc_lo|, -1 mul:4
+// GFX12: encoding: [0x05,0x02,0x29,0xd6,0xfd,0xd4,0x04,0x33]
+
+v_min3_num_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2
+// GFX12: encoding: [0xff,0x83,0x29,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+
+v_min3_i16 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x4a,0xd6,0x01,0x05,0x0e,0x00]
+
+v_min3_i16 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x4a,0xd6,0xff,0x05,0xa4,0x01]
+
+v_min3_i16 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x4a,0xd6,0x01,0xfe,0xff,0x01]
+
+v_min3_i16 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x4a,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_min3_i16 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x4a,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_min3_i16 v5, vcc_hi, 0xfe0b, v255
+// GFX12: encoding: [0x05,0x00,0x4a,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+
+v_min3_i16 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x4a,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_min3_i16 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x4a,0xd6,0x7d,0xfe,0xf5,0x01,0x00,0x38,0x00,0x00]
+
+v_min3_i16 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x4a,0xd6,0x7e,0x82,0xad,0x01]
+
+v_min3_i16 v5, exec_hi, null, vcc_lo op_sel:[1,1,1,1]
+// GFX12: encoding: [0x05,0x78,0x4a,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_min3_i16 v5, null, exec_lo, 0xfe0b op_sel:[0,0,0,0]
+// GFX12: encoding: [0x05,0x00,0x4a,0xd6,0x7c,0xfc,0xfc,0x03,0x0b,0xfe,0x00,0x00]
+
+v_min3_i16 v5, -1, exec_hi, src_scc op_sel:[1,0,0,0]
+// GFX12: encoding: [0x05,0x08,0x4a,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_min3_i16 v5, 0.5, m0, 0.5 op_sel:[0,1,0,0]
+// GFX12: encoding: [0x05,0x10,0x4a,0xd6,0xff,0xfa,0xfc,0x03,0x00,0x38,0x00,0x00]
+
+v_min3_i16 v5, src_scc, vcc_lo, -1 op_sel:[0,0,1,0]
+// GFX12: encoding: [0x05,0x20,0x4a,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_min3_i16 v255, 0xfe0b, vcc_hi, null op_sel:[0,0,0,1]
+// GFX12: encoding: [0xff,0x40,0x4a,0xd6,0xff,0xd6,0xf0,0x01,0x0b,0xfe,0x00,0x00]
+
+v_min3_i32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x1a,0xd6,0x01,0x05,0x0e,0x00]
+
+v_min3_i32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x1a,0xd6,0xff,0x05,0xa4,0x01]
+
+v_min3_i32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x1a,0xd6,0x01,0xfe,0xff,0x01]
+
+v_min3_i32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x1a,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_min3_i32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x1a,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_min3_i32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x1a,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_min3_i32 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x1a,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_min3_i32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x1a,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_min3_i32 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x1a,0xd6,0x7e,0x82,0xad,0x01]
+
+v_min3_i32 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x1a,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_min3_i32 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x1a,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_min3_i32 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x1a,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_min3_i32 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x1a,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_min3_i32 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x1a,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_min3_i32 v255, 0xaf123456, vcc_hi, null
+// GFX12: encoding: [0xff,0x00,0x1a,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_min3_u16 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x4b,0xd6,0x01,0x05,0x0e,0x00]
+
+v_min3_u16 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x4b,0xd6,0xff,0x05,0xa4,0x01]
+
+v_min3_u16 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x4b,0xd6,0x01,0xfe,0xff,0x01]
+
+v_min3_u16 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x4b,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_min3_u16 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x4b,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_min3_u16 v5, vcc_hi, 0xfe0b, v255
+// GFX12: encoding: [0x05,0x00,0x4b,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+
+v_min3_u16 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x4b,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_min3_u16 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x4b,0xd6,0x7d,0xfe,0xf5,0x01,0x00,0x38,0x00,0x00]
+
+v_min3_u16 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x4b,0xd6,0x7e,0x82,0xad,0x01]
+
+v_min3_u16 v5, exec_hi, null, vcc_lo op_sel:[1,1,1,1]
+// GFX12: encoding: [0x05,0x78,0x4b,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_min3_u16 v5, null, exec_lo, 0xfe0b op_sel:[0,0,0,0]
+// GFX12: encoding: [0x05,0x00,0x4b,0xd6,0x7c,0xfc,0xfc,0x03,0x0b,0xfe,0x00,0x00]
+
+v_min3_u16 v5, -1, exec_hi, src_scc op_sel:[1,0,0,0]
+// GFX12: encoding: [0x05,0x08,0x4b,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_min3_u16 v5, 0.5, m0, 0.5 op_sel:[0,1,0,0]
+// GFX12: encoding: [0x05,0x10,0x4b,0xd6,0xff,0xfa,0xfc,0x03,0x00,0x38,0x00,0x00]
+
+v_min3_u16 v5, src_scc, vcc_lo, -1 op_sel:[0,0,1,0]
+// GFX12: encoding: [0x05,0x20,0x4b,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_min3_u16 v255, 0xfe0b, vcc_hi, null op_sel:[0,0,0,1]
+// GFX12: encoding: [0xff,0x40,0x4b,0xd6,0xff,0xd6,0xf0,0x01,0x0b,0xfe,0x00,0x00]
+
+v_min3_u32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x1b,0xd6,0x01,0x05,0x0e,0x00]
+
+v_min3_u32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x1b,0xd6,0xff,0x05,0xa4,0x01]
+
+v_min3_u32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x1b,0xd6,0x01,0xfe,0xff,0x01]
+
+v_min3_u32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x1b,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_min3_u32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x1b,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_min3_u32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x1b,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_min3_u32 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x1b,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_min3_u32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x1b,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_min3_u32 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x1b,0xd6,0x7e,0x82,0xad,0x01]
+
+v_min3_u32 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x1b,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_min3_u32 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x1b,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_min3_u32 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x1b,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_min3_u32 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x1b,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_min3_u32 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x1b,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_min3_u32 v255, 0xaf123456, vcc_hi, null
+// GFX12: encoding: [0xff,0x00,0x1b,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_min_i16 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x0c,0xd7,0x01,0x05,0x02,0x00]
+
+v_min_i16 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x0c,0xd7,0xff,0xff,0x03,0x00]
+
+v_min_i16 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x0c,0xd7,0x01,0x04,0x00,0x00]
+
+v_min_i16 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x0c,0xd7,0x69,0xd2,0x00,0x00]
+
+v_min_i16 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x0c,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_min_i16 v5, vcc_hi, 0xfe0b
+// GFX12: encoding: [0x05,0x00,0x0c,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_min_i16 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x0c,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_min_i16 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x0c,0xd7,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_min_i16 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x0c,0xd7,0x7e,0x82,0x01,0x00]
+
+v_min_i16 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x0c,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_min_i16 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x0c,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_min_i16 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x0c,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_min_i16 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x0c,0xd7,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_min_i16 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x0c,0xd7,0xfd,0xd4,0x00,0x00]
+
+v_min_i16 v255, 0xfe0b, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x0c,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_min_u16 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x0b,0xd7,0x01,0x05,0x02,0x00]
+
+v_min_u16 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x0b,0xd7,0xff,0xff,0x03,0x00]
+
+v_min_u16 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x0b,0xd7,0x01,0x04,0x00,0x00]
+
+v_min_u16 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x0b,0xd7,0x69,0xd2,0x00,0x00]
+
+v_min_u16 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x0b,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_min_u16 v5, vcc_hi, 0xfe0b
+// GFX12: encoding: [0x05,0x00,0x0b,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_min_u16 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x0b,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_min_u16 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x0b,0xd7,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_min_u16 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x0b,0xd7,0x7e,0x82,0x01,0x00]
+
+v_min_u16 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x0b,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_min_u16 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x0b,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_min_u16 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x0b,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_min_u16 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x0b,0xd7,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_min_u16 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x0b,0xd7,0xfd,0xd4,0x00,0x00]
+
+v_min_u16 v255, 0xfe0b, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x0b,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_minmax_num_f16 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x6a,0xd6,0x01,0x05,0x0e,0x00]
+
+v_minmax_num_f16 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x6a,0xd6,0xff,0x05,0xa4,0x01]
+
+v_minmax_num_f16 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x6a,0xd6,0x01,0xfe,0xff,0x01]
+
+v_minmax_num_f16 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x6a,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_minmax_num_f16 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x6a,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_minmax_num_f16 v5, vcc_hi, 0xfe0b, v255
+// GFX12: encoding: [0x05,0x00,0x6a,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+
+v_minmax_num_f16 v5, -|ttmp15|, -|src_scc|, -|ttmp15|
+// GFX12: encoding: [0x05,0x07,0x6a,0xd6,0x7b,0xfa,0xed,0xe1]
+
+v_minmax_num_f16 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x6a,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_minmax_num_f16 v5, |exec_lo|, -1, vcc_hi
+// GFX12: encoding: [0x05,0x01,0x6a,0xd6,0x7e,0x82,0xad,0x01]
+
+v_minmax_num_f16 v5, -|exec_hi|, null, -|vcc_lo|
+// GFX12: encoding: [0x05,0x05,0x6a,0xd6,0x7f,0xf8,0xa8,0xa1]
+
+v_minmax_num_f16 v5, null, exec_lo, -|0xfe0b|
+// GFX12: encoding: [0x05,0x04,0x6a,0xd6,0x7c,0xfc,0xfc,0x83,0x0b,0xfe,0x00,0x00]
+
+v_minmax_num_f16 v5, -1, -|exec_hi|, -|src_scc|
+// GFX12: encoding: [0x05,0x06,0x6a,0xd6,0xc1,0xfe,0xf4,0xc3]
+
+v_minmax_num_f16 v5, 0.5, -m0, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x6a,0xd6,0xf0,0xfa,0xc0,0x4b]
+
+v_minmax_num_f16 v5, -src_scc, |vcc_lo|, -1 mul:4
+// GFX12: encoding: [0x05,0x02,0x6a,0xd6,0xfd,0xd4,0x04,0x33]
+
+v_minmax_num_f16 v255, -|0xfe0b|, -|vcc_hi|, null clamp div:2
+// GFX12: encoding: [0xff,0x83,0x6a,0xd6,0xff,0xd6,0xf0,0x79,0x0b,0xfe,0x00,0x00]
+
+v_minmax_num_f32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x68,0xd6,0x01,0x05,0x0e,0x00]
+
+v_minmax_num_f32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x68,0xd6,0xff,0x05,0xa4,0x01]
+
+v_minmax_num_f32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x68,0xd6,0x01,0xfe,0xff,0x01]
+
+v_minmax_num_f32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x68,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_minmax_num_f32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x68,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_minmax_num_f32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x68,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_minmax_num_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15|
+// GFX12: encoding: [0x05,0x07,0x68,0xd6,0x7b,0xfa,0xed,0xe1]
+
+v_minmax_num_f32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x68,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_minmax_num_f32 v5, |exec_lo|, -1, vcc_hi
+// GFX12: encoding: [0x05,0x01,0x68,0xd6,0x7e,0x82,0xad,0x01]
+
+v_minmax_num_f32 v5, -|exec_hi|, null, -|vcc_lo|
+// GFX12: encoding: [0x05,0x05,0x68,0xd6,0x7f,0xf8,0xa8,0xa1]
+
+v_minmax_num_f32 v5, null, exec_lo, -|0xaf123456|
+// GFX12: encoding: [0x05,0x04,0x68,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+
+v_minmax_num_f32 v5, -1, -|exec_hi|, -|src_scc|
+// GFX12: encoding: [0x05,0x06,0x68,0xd6,0xc1,0xfe,0xf4,0xc3]
+
+v_minmax_num_f32 v5, 0.5, -m0, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x68,0xd6,0xf0,0xfa,0xc0,0x4b]
+
+v_minmax_num_f32 v5, -src_scc, |vcc_lo|, -1 mul:4
+// GFX12: encoding: [0x05,0x02,0x68,0xd6,0xfd,0xd4,0x04,0x33]
+
+v_minmax_num_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2
+// GFX12: encoding: [0xff,0x83,0x68,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+
+v_minmax_i32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x65,0xd6,0x01,0x05,0x0e,0x00]
+
+v_minmax_i32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x65,0xd6,0xff,0x05,0xa4,0x01]
+
+v_minmax_i32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x65,0xd6,0x01,0xfe,0xff,0x01]
+
+v_minmax_i32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x65,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_minmax_i32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x65,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_minmax_i32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x65,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_minmax_i32 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x65,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_minmax_i32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x65,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_minmax_i32 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x65,0xd6,0x7e,0x82,0xad,0x01]
+
+v_minmax_i32 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x65,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_minmax_i32 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x65,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_minmax_i32 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x65,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_minmax_i32 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x65,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_minmax_i32 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x65,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_minmax_i32 v255, 0xaf123456, vcc_hi, null
+// GFX12: encoding: [0xff,0x00,0x65,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_minmax_u32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x63,0xd6,0x01,0x05,0x0e,0x00]
+
+v_minmax_u32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x63,0xd6,0xff,0x05,0xa4,0x01]
+
+v_minmax_u32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x63,0xd6,0x01,0xfe,0xff,0x01]
+
+v_minmax_u32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x63,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_minmax_u32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x63,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_minmax_u32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x63,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_minmax_u32 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x63,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_minmax_u32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x63,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_minmax_u32 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x63,0xd6,0x7e,0x82,0xad,0x01]
+
+v_minmax_u32 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x63,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_minmax_u32 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x63,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_minmax_u32 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x63,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_minmax_u32 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x63,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_minmax_u32 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x63,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_minmax_u32 v255, 0xaf123456, vcc_hi, null
+// GFX12: encoding: [0xff,0x00,0x63,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, ttmp[14:15]
+// GFX12: encoding: [0x05,0x00,0x3b,0xd6,0x01,0x05,0xea,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v255, ttmp[14:15]
+// GFX12: encoding: [0x05,0x00,0x3b,0xd6,0x01,0xff,0xeb,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], s2, ttmp[14:15]
+// GFX12: encoding: [0x05,0x00,0x3b,0xd6,0x01,0x05,0xe8,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], s105, ttmp[14:15]
+// GFX12: encoding: [0x05,0x00,0x3b,0xd6,0x01,0xd3,0xe8,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], v[254:255], ttmp15, s[6:7]
+// GFX12: encoding: [0x05,0x00,0x3b,0xd6,0xfe,0xf7,0x18,0x00]
+
+v_mqsad_pk_u16_u8 v[5:6], s[2:3], vcc_hi, v[3:4]
+// GFX12: encoding: [0x05,0x00,0x3b,0xd6,0x02,0xd6,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], s[104:105], vcc_lo, s[104:105]
+// GFX12: encoding: [0x05,0x00,0x3b,0xd6,0x68,0xd4,0xa0,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], vcc, m0, v[254:255]
+// GFX12: encoding: [0x05,0x00,0x3b,0xd6,0x6a,0xfa,0xf8,0x07]
+
+v_mqsad_pk_u16_u8 v[5:6], ttmp[14:15], exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x3b,0xd6,0x7a,0xfe,0xf0,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], exec, exec_lo, exec
+// GFX12: encoding: [0x05,0x00,0x3b,0xd6,0x7e,0xfc,0xf8,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], null, null, vcc
+// GFX12: encoding: [0x05,0x00,0x3b,0xd6,0x7c,0xf8,0xa8,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], -1, -1, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x3b,0xd6,0xc1,0x82,0xfd,0x03,0x56,0x34,0x12,0xaf]
+
+v_mqsad_pk_u16_u8 v[5:6], 0.5, 0.5, src_scc
+// GFX12: encoding: [0x05,0x00,0x3b,0xd6,0xf0,0xe0,0xf5,0x03]
+
+v_mqsad_pk_u16_u8 v[5:6], src_scc, src_scc, 0.5
+// GFX12: encoding: [0x05,0x00,0x3b,0xd6,0xfd,0xfa,0xc1,0x03]
+
+v_mqsad_pk_u16_u8 v[254:255], 0xaf123456, 0xaf123456, -1 clamp
+// GFX12: encoding: [0xfe,0x80,0x3b,0xd6,0xff,0xfe,0x05,0x03,0x56,0x34,0x12,0xaf]
+
+v_mqsad_u32_u8 v[5:8], v[1:2], v2, v[252:255]
+// GFX12: encoding: [0x05,0x00,0x3d,0xd6,0x01,0x05,0xf2,0x07]
+
+v_mqsad_u32_u8 v[5:8], v[1:2], v255, v[252:255]
+// GFX12: encoding: [0x05,0x00,0x3d,0xd6,0x01,0xff,0xf3,0x07]
+
+v_mqsad_u32_u8 v[5:8], v[1:2], s2, v[252:255]
+// GFX12: encoding: [0x05,0x00,0x3d,0xd6,0x01,0x05,0xf0,0x07]
+
+v_mqsad_u32_u8 v[5:8], v[1:2], s105, v[252:255]
+// GFX12: encoding: [0x05,0x00,0x3d,0xd6,0x01,0xd3,0xf0,0x07]
+
+v_mqsad_u32_u8 v[5:8], v[254:255], ttmp15, v[252:255]
+// GFX12: encoding: [0x05,0x00,0x3d,0xd6,0xfe,0xf7,0xf0,0x07]
+
+v_mqsad_u32_u8 v[5:8], s[2:3], vcc_hi, v[252:255]
+// GFX12: encoding: [0x05,0x00,0x3d,0xd6,0x02,0xd6,0xf0,0x07]
+
+v_mqsad_u32_u8 v[5:8], s[104:105], vcc_lo, v[252:255]
+// GFX12: encoding: [0x05,0x00,0x3d,0xd6,0x68,0xd4,0xf0,0x07]
+
+v_mqsad_u32_u8 v[5:8], vcc, m0, v[252:255]
+// GFX12: encoding: [0x05,0x00,0x3d,0xd6,0x6a,0xfa,0xf0,0x07]
+
+v_mqsad_u32_u8 v[5:8], ttmp[14:15], exec_hi, v[252:255]
+// GFX12: encoding: [0x05,0x00,0x3d,0xd6,0x7a,0xfe,0xf0,0x07]
+
+v_mqsad_u32_u8 v[5:8], exec, exec_lo, v[252:255]
+// GFX12: encoding: [0x05,0x00,0x3d,0xd6,0x7e,0xfc,0xf0,0x07]
+
+v_mqsad_u32_u8 v[5:8], null, null, v[252:255]
+// GFX12: encoding: [0x05,0x00,0x3d,0xd6,0x7c,0xf8,0xf0,0x07]
+
+v_mqsad_u32_u8 v[5:8], -1, -1, v[252:255]
+// GFX12: encoding: [0x05,0x00,0x3d,0xd6,0xc1,0x82,0xf1,0x07]
+
+v_mqsad_u32_u8 v[5:8], 0.5, 0.5, v[252:255]
+// GFX12: encoding: [0x05,0x00,0x3d,0xd6,0xf0,0xe0,0xf1,0x07]
+
+v_mqsad_u32_u8 v[5:8], src_scc, src_scc, v[252:255]
+// GFX12: encoding: [0x05,0x00,0x3d,0xd6,0xfd,0xfa,0xf1,0x07]
+
+v_mqsad_u32_u8 v[252:255], 0xaf123456, 0xaf123456, v[3:6] clamp
+// GFX12: encoding: [0xfc,0x80,0x3d,0xd6,0xff,0xfe,0x0d,0x04,0x56,0x34,0x12,0xaf]
+
+v_msad_u8 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x39,0xd6,0x01,0x05,0x0e,0x00]
+
+v_msad_u8 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x39,0xd6,0xff,0x05,0xa4,0x01]
+
+v_msad_u8 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x39,0xd6,0x01,0xfe,0xff,0x01]
+
+v_msad_u8 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x39,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_msad_u8 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x39,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_msad_u8 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x39,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_msad_u8 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x39,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_msad_u8 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x39,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_msad_u8 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x39,0xd6,0x7e,0x82,0xad,0x01]
+
+v_msad_u8 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x39,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_msad_u8 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x39,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_msad_u8 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x39,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_msad_u8 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x39,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_msad_u8 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x39,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_msad_u8 v255, 0xaf123456, vcc_hi, null clamp
+// GFX12: encoding: [0xff,0x80,0x39,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_mul_hi_i32 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x2e,0xd7,0x01,0x05,0x02,0x00]
+
+v_mul_hi_i32 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x2e,0xd7,0xff,0xff,0x03,0x00]
+
+v_mul_hi_i32 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x2e,0xd7,0x01,0x04,0x00,0x00]
+
+v_mul_hi_i32 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x2e,0xd7,0x69,0xd2,0x00,0x00]
+
+v_mul_hi_i32 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x2e,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_mul_hi_i32 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x2e,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_mul_hi_i32 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x2e,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_mul_hi_i32 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x2e,0xd7,0x7d,0xe0,0x01,0x00]
+
+v_mul_hi_i32 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x2e,0xd7,0x7e,0x82,0x01,0x00]
+
+v_mul_hi_i32 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x2e,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_mul_hi_i32 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x2e,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_mul_hi_i32 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x2e,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_mul_hi_i32 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x2e,0xd7,0xf0,0xfa,0x00,0x00]
+
+v_mul_hi_i32 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x2e,0xd7,0xfd,0xd4,0x00,0x00]
+
+v_mul_hi_i32 v255, 0xaf123456, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x2e,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_mul_hi_u32 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x2d,0xd7,0x01,0x05,0x02,0x00]
+
+v_mul_hi_u32 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x2d,0xd7,0xff,0xff,0x03,0x00]
+
+v_mul_hi_u32 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x2d,0xd7,0x01,0x04,0x00,0x00]
+
+v_mul_hi_u32 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x2d,0xd7,0x69,0xd2,0x00,0x00]
+
+v_mul_hi_u32 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x2d,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_mul_hi_u32 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x2d,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_mul_hi_u32 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x2d,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_mul_hi_u32 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x2d,0xd7,0x7d,0xe0,0x01,0x00]
+
+v_mul_hi_u32 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x2d,0xd7,0x7e,0x82,0x01,0x00]
+
+v_mul_hi_u32 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x2d,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_mul_hi_u32 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x2d,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_mul_hi_u32 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x2d,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_mul_hi_u32 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x2d,0xd7,0xf0,0xfa,0x00,0x00]
+
+v_mul_hi_u32 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x2d,0xd7,0xfd,0xd4,0x00,0x00]
+
+v_mul_hi_u32 v255, 0xaf123456, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x2d,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_mul_lo_u16 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x05,0xd7,0x01,0x05,0x02,0x00]
+
+v_mul_lo_u16 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x05,0xd7,0xff,0xff,0x03,0x00]
+
+v_mul_lo_u16 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x05,0xd7,0x01,0x04,0x00,0x00]
+
+v_mul_lo_u16 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x05,0xd7,0x69,0xd2,0x00,0x00]
+
+v_mul_lo_u16 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x05,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_mul_lo_u16 v5, vcc_hi, 0xfe0b
+// GFX12: encoding: [0x05,0x00,0x05,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_mul_lo_u16 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x05,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_mul_lo_u16 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x05,0xd7,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_mul_lo_u16 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x05,0xd7,0x7e,0x82,0x01,0x00]
+
+v_mul_lo_u16 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x05,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_mul_lo_u16 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x05,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_mul_lo_u16 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x05,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_mul_lo_u16 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x05,0xd7,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_mul_lo_u16 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x05,0xd7,0xfd,0xd4,0x00,0x00]
+
+v_mul_lo_u16 v255, 0xfe0b, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x05,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x2c,0xd7,0x01,0x05,0x02,0x00]
+
+v_mul_lo_u32 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x2c,0xd7,0xff,0xff,0x03,0x00]
+
+v_mul_lo_u32 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x2c,0xd7,0x01,0x04,0x00,0x00]
+
+v_mul_lo_u32 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x2c,0xd7,0x69,0xd2,0x00,0x00]
+
+v_mul_lo_u32 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x2c,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_mul_lo_u32 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x2c,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_mul_lo_u32 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x2c,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_mul_lo_u32 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x2c,0xd7,0x7d,0xe0,0x01,0x00]
+
+v_mul_lo_u32 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x2c,0xd7,0x7e,0x82,0x01,0x00]
+
+v_mul_lo_u32 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x2c,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_mul_lo_u32 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x2c,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_mul_lo_u32 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x2c,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_mul_lo_u32 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x2c,0xd7,0xf0,0xfa,0x00,0x00]
+
+v_mul_lo_u32 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x2c,0xd7,0xfd,0xd4,0x00,0x00]
+
+v_mul_lo_u32 v255, 0xaf123456, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x2c,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_mullit_f32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x18,0xd6,0x01,0x05,0x0e,0x00]
+
+v_mullit_f32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x18,0xd6,0xff,0x05,0xa4,0x01]
+
+v_mullit_f32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x18,0xd6,0x01,0xfe,0xff,0x01]
+
+v_mullit_f32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x18,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_mullit_f32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x18,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_mullit_f32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x18,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_mullit_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15|
+// GFX12: encoding: [0x05,0x07,0x18,0xd6,0x7b,0xfa,0xed,0xe1]
+
+v_mullit_f32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x18,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_mullit_f32 v5, |exec_lo|, -1, vcc_hi
+// GFX12: encoding: [0x05,0x01,0x18,0xd6,0x7e,0x82,0xad,0x01]
+
+v_mullit_f32 v5, -|exec_hi|, null, -|vcc_lo|
+// GFX12: encoding: [0x05,0x05,0x18,0xd6,0x7f,0xf8,0xa8,0xa1]
+
+v_mullit_f32 v5, null, exec_lo, -|0xaf123456|
+// GFX12: encoding: [0x05,0x04,0x18,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+
+v_mullit_f32 v5, -1, -|exec_hi|, -|src_scc|
+// GFX12: encoding: [0x05,0x06,0x18,0xd6,0xc1,0xfe,0xf4,0xc3]
+
+v_mullit_f32 v5, 0.5, -m0, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x18,0xd6,0xf0,0xfa,0xc0,0x4b]
+
+v_mullit_f32 v5, -src_scc, |vcc_lo|, -1 mul:4
+// GFX12: encoding: [0x05,0x02,0x18,0xd6,0xfd,0xd4,0x04,0x33]
+
+v_mullit_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2
+// GFX12: encoding: [0xff,0x83,0x18,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+
+v_or3_b32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x58,0xd6,0x01,0x05,0x0e,0x00]
+
+v_or3_b32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x58,0xd6,0xff,0x05,0xa4,0x01]
+
+v_or3_b32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x58,0xd6,0x01,0xfe,0xff,0x01]
+
+v_or3_b32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x58,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_or3_b32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x58,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_or3_b32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x58,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_or3_b32 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x58,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_or3_b32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x58,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_or3_b32 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x58,0xd6,0x7e,0x82,0xad,0x01]
+
+v_or3_b32 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x58,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_or3_b32 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x58,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_or3_b32 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x58,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_or3_b32 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x58,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_or3_b32 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x58,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_or3_b32 v255, 0xaf123456, vcc_hi, null
+// GFX12: encoding: [0xff,0x00,0x58,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_or_b16 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x63,0xd7,0x01,0x05,0x02,0x00]
+
+v_or_b16 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x63,0xd7,0xff,0xff,0x03,0x00]
+
+v_or_b16 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x63,0xd7,0x01,0x04,0x00,0x00]
+
+v_or_b16 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x63,0xd7,0x69,0xd2,0x00,0x00]
+
+v_or_b16 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x63,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_or_b16 v5, vcc_hi, 0xfe0b
+// GFX12: encoding: [0x05,0x00,0x63,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_or_b16 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x63,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_or_b16 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x63,0xd7,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_or_b16 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x63,0xd7,0x7e,0x82,0x01,0x00]
+
+v_or_b16 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x63,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_or_b16 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x63,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_or_b16 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x63,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_or_b16 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x63,0xd7,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_or_b16 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x63,0xd7,0xfd,0xd4,0x00,0x00]
+
+v_or_b16 v255, 0xfe0b, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x63,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_pack_b32_f16 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x11,0xd7,0x01,0x05,0x02,0x00]
+
+v_pack_b32_f16 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x11,0xd7,0xff,0xff,0x03,0x00]
+
+v_pack_b32_f16 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x11,0xd7,0x01,0x04,0x00,0x00]
+
+v_pack_b32_f16 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x11,0xd7,0x69,0xd2,0x00,0x00]
+
+v_pack_b32_f16 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x11,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_pack_b32_f16 v5, vcc_hi, 0xfe0b
+// GFX12: encoding: [0x05,0x00,0x11,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_pack_b32_f16 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x11,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_pack_b32_f16 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x11,0xd7,0x7d,0xe0,0x01,0x00]
+
+v_pack_b32_f16 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x11,0xd7,0x7e,0x82,0x01,0x00]
+
+v_pack_b32_f16 v5, |exec_hi|, null
+// GFX12: encoding: [0x05,0x01,0x11,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_pack_b32_f16 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x11,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_pack_b32_f16 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x11,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_pack_b32_f16 v5, 0.5, -m0 op_sel:[0,0,0]
+// GFX12: encoding: [0x05,0x00,0x11,0xd7,0xf0,0xfa,0x00,0x40]
+
+v_pack_b32_f16 v5, -src_scc, |vcc_lo| op_sel:[1,0,0]
+// GFX12: encoding: [0x05,0x0a,0x11,0xd7,0xfd,0xd4,0x00,0x20]
+
+v_pack_b32_f16 v255, -|0xfe0b|, -|vcc_hi| op_sel:[0,1,0]
+// GFX12: encoding: [0xff,0x13,0x11,0xd7,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_perm_b32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x44,0xd6,0x01,0x05,0x0e,0x00]
+
+v_perm_b32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x44,0xd6,0xff,0x05,0xa4,0x01]
+
+v_perm_b32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x44,0xd6,0x01,0xfe,0xff,0x01]
+
+v_perm_b32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x44,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_perm_b32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x44,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_perm_b32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x44,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_perm_b32 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x44,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_perm_b32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x44,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_perm_b32 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x44,0xd6,0x7e,0x82,0xad,0x01]
+
+v_perm_b32 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x44,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_perm_b32 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x44,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_perm_b32 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x44,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_perm_b32 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x44,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_perm_b32 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x44,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_perm_b32 v255, 0xaf123456, vcc_hi, null
+// GFX12: encoding: [0xff,0x00,0x44,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_permlane16_b32 v5, v1, s2, s3
+// GFX12: encoding: [0x05,0x00,0x5b,0xd6,0x01,0x05,0x0c,0x00]
+
+v_permlane16_b32 v5, v1, s105, s105
+// GFX12: encoding: [0x05,0x00,0x5b,0xd6,0x01,0xd3,0xa4,0x01]
+
+v_permlane16_b32 v5, v1, ttmp15, ttmp15
+// GFX12: encoding: [0x05,0x00,0x5b,0xd6,0x01,0xf7,0xec,0x01]
+
+v_permlane16_b32 v5, v1, vcc_hi, exec_lo
+// GFX12: encoding: [0x05,0x00,0x5b,0xd6,0x01,0xd7,0xf8,0x01]
+
+v_permlane16_b32 v5, v1, vcc_lo, m0
+// GFX12: encoding: [0x05,0x00,0x5b,0xd6,0x01,0xd5,0xf4,0x01]
+
+v_permlane16_b32 v5, v1, m0, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x5b,0xd6,0x01,0xfb,0xac,0x01]
+
+v_permlane16_b32 v5, v1, exec_hi, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x5b,0xd6,0x01,0xff,0xa8,0x01]
+
+v_permlane16_b32 v5, v1, exec_lo, src_scc
+// GFX12: encoding: [0x05,0x00,0x5b,0xd6,0x01,0xfd,0xf4,0x03]
+
+v_permlane16_b32 v5, v1, null, 0.5 op_sel:[1,1]
+// GFX12: encoding: [0x05,0x18,0x5b,0xd6,0x01,0xf9,0xc0,0x03]
+
+v_permlane16_b32 v5, v1, -1, -1 op_sel:[0,0]
+// GFX12: encoding: [0x05,0x00,0x5b,0xd6,0x01,0x83,0x05,0x03]
+
+v_permlane16_b32 v5, v1, 0.5, null op_sel:[1,0]
+// GFX12: encoding: [0x05,0x08,0x5b,0xd6,0x01,0xe1,0xf1,0x01]
+
+v_permlane16_b32 v255, v255, src_scc, exec_hi op_sel:[0,1]
+// GFX12: encoding: [0xff,0x10,0x5b,0xd6,0xff,0xfb,0xfd,0x01]
+
+v_permlanex16_b32 v5, v1, s2, s3
+// GFX12: encoding: [0x05,0x00,0x5c,0xd6,0x01,0x05,0x0c,0x00]
+
+v_permlanex16_b32 v5, v1, s105, s105
+// GFX12: encoding: [0x05,0x00,0x5c,0xd6,0x01,0xd3,0xa4,0x01]
+
+v_permlanex16_b32 v5, v1, ttmp15, ttmp15
+// GFX12: encoding: [0x05,0x00,0x5c,0xd6,0x01,0xf7,0xec,0x01]
+
+v_permlanex16_b32 v5, v1, vcc_hi, exec_lo
+// GFX12: encoding: [0x05,0x00,0x5c,0xd6,0x01,0xd7,0xf8,0x01]
+
+v_permlanex16_b32 v5, v1, vcc_lo, m0
+// GFX12: encoding: [0x05,0x00,0x5c,0xd6,0x01,0xd5,0xf4,0x01]
+
+v_permlanex16_b32 v5, v1, m0, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x5c,0xd6,0x01,0xfb,0xac,0x01]
+
+v_permlanex16_b32 v5, v1, exec_hi, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x5c,0xd6,0x01,0xff,0xa8,0x01]
+
+v_permlanex16_b32 v5, v1, exec_lo, src_scc
+// GFX12: encoding: [0x05,0x00,0x5c,0xd6,0x01,0xfd,0xf4,0x03]
+
+v_permlanex16_b32 v5, v1, null, 0.5 op_sel:[1,1]
+// GFX12: encoding: [0x05,0x18,0x5c,0xd6,0x01,0xf9,0xc0,0x03]
+
+v_permlanex16_b32 v5, v1, -1, -1 op_sel:[0,0]
+// GFX12: encoding: [0x05,0x00,0x5c,0xd6,0x01,0x83,0x05,0x03]
+
+v_permlanex16_b32 v5, v1, 0.5, null op_sel:[1,0]
+// GFX12: encoding: [0x05,0x08,0x5c,0xd6,0x01,0xe1,0xf1,0x01]
+
+v_permlanex16_b32 v255, v255, src_scc, exec_hi op_sel:[0,1]
+// GFX12: encoding: [0xff,0x10,0x5c,0xd6,0xff,0xfb,0xfd,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, ttmp[14:15]
+// GFX12: encoding: [0x05,0x00,0x3a,0xd6,0x01,0x05,0xea,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v255, ttmp[14:15]
+// GFX12: encoding: [0x05,0x00,0x3a,0xd6,0x01,0xff,0xeb,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], s2, ttmp[14:15]
+// GFX12: encoding: [0x05,0x00,0x3a,0xd6,0x01,0x05,0xe8,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], s105, ttmp[14:15]
+// GFX12: encoding: [0x05,0x00,0x3a,0xd6,0x01,0xd3,0xe8,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], v[254:255], ttmp15, s[6:7]
+// GFX12: encoding: [0x05,0x00,0x3a,0xd6,0xfe,0xf7,0x18,0x00]
+
+v_qsad_pk_u16_u8 v[5:6], s[2:3], vcc_hi, v[3:4]
+// GFX12: encoding: [0x05,0x00,0x3a,0xd6,0x02,0xd6,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], s[104:105], vcc_lo, s[104:105]
+// GFX12: encoding: [0x05,0x00,0x3a,0xd6,0x68,0xd4,0xa0,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], vcc, m0, v[254:255]
+// GFX12: encoding: [0x05,0x00,0x3a,0xd6,0x6a,0xfa,0xf8,0x07]
+
+v_qsad_pk_u16_u8 v[5:6], ttmp[14:15], exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x3a,0xd6,0x7a,0xfe,0xf0,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], exec, exec_lo, exec
+// GFX12: encoding: [0x05,0x00,0x3a,0xd6,0x7e,0xfc,0xf8,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], null, null, vcc
+// GFX12: encoding: [0x05,0x00,0x3a,0xd6,0x7c,0xf8,0xa8,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], -1, -1, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x3a,0xd6,0xc1,0x82,0xfd,0x03,0x56,0x34,0x12,0xaf]
+
+v_qsad_pk_u16_u8 v[5:6], 0.5, 0.5, src_scc
+// GFX12: encoding: [0x05,0x00,0x3a,0xd6,0xf0,0xe0,0xf5,0x03]
+
+v_qsad_pk_u16_u8 v[5:6], src_scc, src_scc, 0.5
+// GFX12: encoding: [0x05,0x00,0x3a,0xd6,0xfd,0xfa,0xc1,0x03]
+
+v_qsad_pk_u16_u8 v[254:255], 0xaf123456, 0xaf123456, -1 clamp
+// GFX12: encoding: [0xfe,0x80,0x3a,0xd6,0xff,0xfe,0x05,0x03,0x56,0x34,0x12,0xaf]
+
+v_readlane_b32 s5, v1, s2
+// GFX12: encoding: [0x05,0x00,0x60,0xd7,0x01,0x05,0x00,0x00]
+
+v_readlane_b32 s5, v1, s105
+// GFX12: encoding: [0x05,0x00,0x60,0xd7,0x01,0xd3,0x00,0x00]
+
+v_readlane_b32 s105, v1, ttmp15
+// GFX12: encoding: [0x69,0x00,0x60,0xd7,0x01,0xf7,0x00,0x00]
+
+v_readlane_b32 vcc_lo, v1, vcc_hi
+// GFX12: encoding: [0x6a,0x00,0x60,0xd7,0x01,0xd7,0x00,0x00]
+
+v_readlane_b32 vcc_hi, v1, vcc_lo
+// GFX12: encoding: [0x6b,0x00,0x60,0xd7,0x01,0xd5,0x00,0x00]
+
+v_readlane_b32 ttmp15, v1, m0
+// GFX12: encoding: [0x7b,0x00,0x60,0xd7,0x01,0xfb,0x00,0x00]
+
+v_readlane_b32 null, v255, null
+// GFX12: encoding: [0x7c,0x00,0x60,0xd7,0xff,0xf9,0x00,0x00]
+
+v_sad_hi_u8 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x23,0xd6,0x01,0x05,0x0e,0x00]
+
+v_sad_hi_u8 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x23,0xd6,0xff,0x05,0xa4,0x01]
+
+v_sad_hi_u8 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x23,0xd6,0x01,0xfe,0xff,0x01]
+
+v_sad_hi_u8 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x23,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_sad_hi_u8 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x23,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_sad_hi_u8 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x23,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_sad_hi_u8 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x23,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_sad_hi_u8 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x23,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_sad_hi_u8 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x23,0xd6,0x7e,0x82,0xad,0x01]
+
+v_sad_hi_u8 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x23,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_sad_hi_u8 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x23,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_sad_hi_u8 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x23,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_sad_hi_u8 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x23,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_sad_hi_u8 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x23,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_sad_hi_u8 v255, 0xaf123456, vcc_hi, null clamp
+// GFX12: encoding: [0xff,0x80,0x23,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_sad_u16 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x24,0xd6,0x01,0x05,0x0e,0x00]
+
+v_sad_u16 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x24,0xd6,0xff,0x05,0xa4,0x01]
+
+v_sad_u16 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x24,0xd6,0x01,0xfe,0xff,0x01]
+
+v_sad_u16 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x24,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_sad_u16 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x24,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_sad_u16 v5, vcc_hi, 0xfe0b, v255
+// GFX12: encoding: [0x05,0x00,0x24,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+
+v_sad_u16 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x24,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_sad_u16 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x24,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_sad_u16 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x24,0xd6,0x7e,0x82,0xad,0x01]
+
+v_sad_u16 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x24,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_sad_u16 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x24,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_sad_u16 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x24,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_sad_u16 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x24,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_sad_u16 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x24,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_sad_u16 v255, 0xfe0b, vcc_hi, null clamp
+// GFX12: encoding: [0xff,0x80,0x24,0xd6,0xff,0xd6,0xf0,0x01,0x0b,0xfe,0x00,0x00]
+
+v_sad_u32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x25,0xd6,0x01,0x05,0x0e,0x00]
+
+v_sad_u32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x25,0xd6,0xff,0x05,0xa4,0x01]
+
+v_sad_u32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x25,0xd6,0x01,0xfe,0xff,0x01]
+
+v_sad_u32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x25,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_sad_u32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x25,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_sad_u32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x25,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_sad_u32 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x25,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_sad_u32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x25,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_sad_u32 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x25,0xd6,0x7e,0x82,0xad,0x01]
+
+v_sad_u32 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x25,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_sad_u32 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x25,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_sad_u32 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x25,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_sad_u32 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x25,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_sad_u32 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x25,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_sad_u32 v255, 0xaf123456, vcc_hi, null clamp
+// GFX12: encoding: [0xff,0x80,0x25,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_sad_u8 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x22,0xd6,0x01,0x05,0x0e,0x00]
+
+v_sad_u8 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x22,0xd6,0xff,0x05,0xa4,0x01]
+
+v_sad_u8 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x22,0xd6,0x01,0xfe,0xff,0x01]
+
+v_sad_u8 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x22,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_sad_u8 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x22,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_sad_u8 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x22,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_sad_u8 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x22,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_sad_u8 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x22,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_sad_u8 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x22,0xd6,0x7e,0x82,0xad,0x01]
+
+v_sad_u8 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x22,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_sad_u8 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x22,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_sad_u8 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x22,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_sad_u8 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x22,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_sad_u8 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x22,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_sad_u8 v255, 0xaf123456, vcc_hi, null clamp
+// GFX12: encoding: [0xff,0x80,0x22,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_sub_co_u32 v5, s6, v1, v2
+// W32: encoding: [0x05,0x06,0x01,0xd7,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s6, v255, v255
+// W32: encoding: [0x05,0x06,0x01,0xd7,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s6, s1, s2
+// W32: encoding: [0x05,0x06,0x01,0xd7,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s6, s105, s105
+// W32: encoding: [0x05,0x06,0x01,0xd7,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s6, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x06,0x01,0xd7,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s6, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x06,0x01,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s6, ttmp15, src_scc
+// W32: encoding: [0x05,0x06,0x01,0xd7,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s6, m0, 0.5
+// W32: encoding: [0x05,0x06,0x01,0xd7,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s6, exec_lo, -1
+// W32: encoding: [0x05,0x06,0x01,0xd7,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s6, exec_hi, null
+// W32: encoding: [0x05,0x06,0x01,0xd7,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s105, null, exec_lo
+// W32: encoding: [0x05,0x69,0x01,0xd7,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, vcc_lo, -1, exec_hi
+// W32: encoding: [0x05,0x6a,0x01,0xd7,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, vcc_hi, 0.5, m0
+// W32: encoding: [0x05,0x6b,0x01,0xd7,0xf0,0xfa,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x05,0x7b,0x01,0xd7,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[12:13], v1, v2
+// W64: encoding: [0x05,0x0c,0x01,0xd7,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[12:13], v255, v255
+// W64: encoding: [0x05,0x0c,0x01,0xd7,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[12:13], s1, s2
+// W64: encoding: [0x05,0x0c,0x01,0xd7,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[12:13], s105, s105
+// W64: encoding: [0x05,0x0c,0x01,0xd7,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[12:13], vcc_lo, ttmp15
+// W64: encoding: [0x05,0x0c,0x01,0xd7,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[12:13], vcc_hi, 0xaf123456
+// W64: encoding: [0x05,0x0c,0x01,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[12:13], ttmp15, src_scc
+// W64: encoding: [0x05,0x0c,0x01,0xd7,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[12:13], m0, 0.5
+// W64: encoding: [0x05,0x0c,0x01,0xd7,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[12:13], exec_lo, -1
+// W64: encoding: [0x05,0x0c,0x01,0xd7,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[12:13], exec_hi, null
+// W64: encoding: [0x05,0x0c,0x01,0xd7,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[12:13], null, exec_lo
+// W64: encoding: [0x05,0x0c,0x01,0xd7,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[104:105], -1, exec_hi
+// W64: encoding: [0x05,0x68,0x01,0xd7,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, vcc, 0.5, m0
+// W64: encoding: [0x05,0x6a,0x01,0xd7,0xf0,0xfa,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_u32 v5, ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x05,0x7a,0x01,0xd7,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v255, null, 0xaf123456, vcc_hi clamp
+// GFX12: encoding: [0xff,0xfc,0x01,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_sub_nc_i16 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x0e,0xd7,0x01,0x05,0x02,0x00]
+
+v_sub_nc_i16 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x0e,0xd7,0xff,0xff,0x03,0x00]
+
+v_sub_nc_i16 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x0e,0xd7,0x01,0x04,0x00,0x00]
+
+v_sub_nc_i16 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x0e,0xd7,0x69,0xd2,0x00,0x00]
+
+v_sub_nc_i16 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x0e,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_sub_nc_i16 v5, vcc_hi, 0xfe0b
+// GFX12: encoding: [0x05,0x00,0x0e,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_sub_nc_i16 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x0e,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_sub_nc_i16 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x0e,0xd7,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_sub_nc_i16 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x0e,0xd7,0x7e,0x82,0x01,0x00]
+
+v_sub_nc_i16 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x0e,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_sub_nc_i16 v5, null, exec_lo op_sel:[1,1,1]
+// GFX12: encoding: [0x05,0x58,0x0e,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_sub_nc_i16 v5, -1, exec_hi op_sel:[0,0,0]
+// GFX12: encoding: [0x05,0x00,0x0e,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_sub_nc_i16 v5, 0.5, m0 op_sel:[1,0,0]
+// GFX12: encoding: [0x05,0x08,0x0e,0xd7,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_sub_nc_i16 v5, src_scc, vcc_lo op_sel:[0,1,0]
+// GFX12: encoding: [0x05,0x10,0x0e,0xd7,0xfd,0xd4,0x00,0x00]
+
+v_sub_nc_i16 v255, 0xfe0b, vcc_hi op_sel:[0,0,1] clamp
+// GFX12: encoding: [0xff,0xc0,0x0e,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_sub_nc_i32 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x25,0xd7,0x01,0x05,0x02,0x00]
+
+v_sub_nc_i32 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x25,0xd7,0xff,0xff,0x03,0x00]
+
+v_sub_nc_i32 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x25,0xd7,0x01,0x04,0x00,0x00]
+
+v_sub_nc_i32 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x25,0xd7,0x69,0xd2,0x00,0x00]
+
+v_sub_nc_i32 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x25,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_sub_nc_i32 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x25,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_sub_nc_i32 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x25,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_sub_nc_i32 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x25,0xd7,0x7d,0xe0,0x01,0x00]
+
+v_sub_nc_i32 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x25,0xd7,0x7e,0x82,0x01,0x00]
+
+v_sub_nc_i32 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x25,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_sub_nc_i32 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x25,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_sub_nc_i32 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x25,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_sub_nc_i32 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x25,0xd7,0xf0,0xfa,0x00,0x00]
+
+v_sub_nc_i32 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x25,0xd7,0xfd,0xd4,0x00,0x00]
+
+v_sub_nc_i32 v255, 0xaf123456, vcc_hi clamp
+// GFX12: encoding: [0xff,0x80,0x25,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_sub_nc_u16 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x04,0xd7,0x01,0x05,0x02,0x00]
+
+v_sub_nc_u16 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x04,0xd7,0xff,0xff,0x03,0x00]
+
+v_sub_nc_u16 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x04,0xd7,0x01,0x04,0x00,0x00]
+
+v_sub_nc_u16 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x04,0xd7,0x69,0xd2,0x00,0x00]
+
+v_sub_nc_u16 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x04,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_sub_nc_u16 v5, vcc_hi, 0xfe0b
+// GFX12: encoding: [0x05,0x00,0x04,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_sub_nc_u16 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x04,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_sub_nc_u16 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x04,0xd7,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_sub_nc_u16 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x04,0xd7,0x7e,0x82,0x01,0x00]
+
+v_sub_nc_u16 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x04,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_sub_nc_u16 v5, null, exec_lo op_sel:[1,1,1]
+// GFX12: encoding: [0x05,0x58,0x04,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_sub_nc_u16 v5, -1, exec_hi op_sel:[0,0,0]
+// GFX12: encoding: [0x05,0x00,0x04,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_sub_nc_u16 v5, 0.5, m0 op_sel:[1,0,0]
+// GFX12: encoding: [0x05,0x08,0x04,0xd7,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_sub_nc_u16 v5, src_scc, vcc_lo op_sel:[0,1,0]
+// GFX12: encoding: [0x05,0x10,0x04,0xd7,0xfd,0xd4,0x00,0x00]
+
+v_sub_nc_u16 v255, 0xfe0b, vcc_hi op_sel:[0,0,1] clamp
+// GFX12: encoding: [0xff,0xc0,0x04,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_subrev_co_u32 v5, s6, v1, v2
+// W32: encoding: [0x05,0x06,0x02,0xd7,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s6, v255, v255
+// W32: encoding: [0x05,0x06,0x02,0xd7,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s6, s1, s2
+// W32: encoding: [0x05,0x06,0x02,0xd7,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s6, s105, s105
+// W32: encoding: [0x05,0x06,0x02,0xd7,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s6, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x06,0x02,0xd7,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s6, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x06,0x02,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s6, ttmp15, src_scc
+// W32: encoding: [0x05,0x06,0x02,0xd7,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s6, m0, 0.5
+// W32: encoding: [0x05,0x06,0x02,0xd7,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s6, exec_lo, -1
+// W32: encoding: [0x05,0x06,0x02,0xd7,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s6, exec_hi, null
+// W32: encoding: [0x05,0x06,0x02,0xd7,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s105, null, exec_lo
+// W32: encoding: [0x05,0x69,0x02,0xd7,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, vcc_lo, -1, exec_hi
+// W32: encoding: [0x05,0x6a,0x02,0xd7,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, vcc_hi, 0.5, m0
+// W32: encoding: [0x05,0x6b,0x02,0xd7,0xf0,0xfa,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x05,0x7b,0x02,0xd7,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[12:13], v1, v2
+// W64: encoding: [0x05,0x0c,0x02,0xd7,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[12:13], v255, v255
+// W64: encoding: [0x05,0x0c,0x02,0xd7,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[12:13], s1, s2
+// W64: encoding: [0x05,0x0c,0x02,0xd7,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[12:13], s105, s105
+// W64: encoding: [0x05,0x0c,0x02,0xd7,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[12:13], vcc_lo, ttmp15
+// W64: encoding: [0x05,0x0c,0x02,0xd7,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[12:13], vcc_hi, 0xaf123456
+// W64: encoding: [0x05,0x0c,0x02,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[12:13], ttmp15, src_scc
+// W64: encoding: [0x05,0x0c,0x02,0xd7,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[12:13], m0, 0.5
+// W64: encoding: [0x05,0x0c,0x02,0xd7,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[12:13], exec_lo, -1
+// W64: encoding: [0x05,0x0c,0x02,0xd7,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[12:13], exec_hi, null
+// W64: encoding: [0x05,0x0c,0x02,0xd7,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[12:13], null, exec_lo
+// W64: encoding: [0x05,0x0c,0x02,0xd7,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[104:105], -1, exec_hi
+// W64: encoding: [0x05,0x68,0x02,0xd7,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, vcc, 0.5, m0
+// W64: encoding: [0x05,0x6a,0x02,0xd7,0xf0,0xfa,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_u32 v5, ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x05,0x7a,0x02,0xd7,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v255, null, 0xaf123456, vcc_hi clamp
+// GFX12: encoding: [0xff,0xfc,0x02,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_trig_preop_f64 v[5:6], v[1:2], v2
+// GFX12: encoding: [0x05,0x00,0x2f,0xd7,0x01,0x05,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], v255
+// GFX12: encoding: [0x05,0x00,0x2f,0xd7,0x01,0xff,0x03,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], s2
+// GFX12: encoding: [0x05,0x00,0x2f,0xd7,0x01,0x05,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], s105
+// GFX12: encoding: [0x05,0x00,0x2f,0xd7,0x01,0xd3,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[254:255], ttmp15
+// GFX12: encoding: [0x05,0x00,0x2f,0xd7,0xfe,0xf7,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], s[2:3], vcc_hi
+// GFX12: encoding: [0x05,0x00,0x2f,0xd7,0x02,0xd6,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], s[104:105], vcc_lo
+// GFX12: encoding: [0x05,0x00,0x2f,0xd7,0x68,0xd4,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], vcc, m0
+// GFX12: encoding: [0x05,0x00,0x2f,0xd7,0x6a,0xfa,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], ttmp[14:15], exec_hi
+// GFX12: encoding: [0x05,0x00,0x2f,0xd7,0x7a,0xfe,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], exec, exec_lo
+// GFX12: encoding: [0x05,0x00,0x2f,0xd7,0x7e,0xfc,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], null, null
+// GFX12: encoding: [0x05,0x00,0x2f,0xd7,0x7c,0xf8,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], -1, -1
+// GFX12: encoding: [0x05,0x00,0x2f,0xd7,0xc1,0x82,0x01,0x00]
+
+v_trig_preop_f64 v[5:6], 0.5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x2f,0xd7,0xf0,0xe0,0x01,0x08]
+
+v_trig_preop_f64 v[5:6], -|src_scc|, src_scc mul:4
+// GFX12: encoding: [0x05,0x01,0x2f,0xd7,0xfd,0xfa,0x01,0x30]
+
+v_trig_preop_f64 v[254:255], 0xaf123456, 0xaf123456 clamp div:2
+// GFX12: encoding: [0xfe,0x80,0x2f,0xd7,0xff,0xfe,0x01,0x18,0x56,0x34,0x12,0xaf]
+
+v_writelane_b32 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x61,0xd7,0x01,0x04,0x00,0x00]
+
+v_writelane_b32 v5, s105, s2
+// GFX12: encoding: [0x05,0x00,0x61,0xd7,0x69,0x04,0x00,0x00]
+
+v_writelane_b32 v5, vcc_lo, s2
+// GFX12: encoding: [0x05,0x00,0x61,0xd7,0x6a,0x04,0x00,0x00]
+
+v_writelane_b32 v5, vcc_hi, s2
+// GFX12: encoding: [0x05,0x00,0x61,0xd7,0x6b,0x04,0x00,0x00]
+
+v_writelane_b32 v5, ttmp15, s2
+// GFX12: encoding: [0x05,0x00,0x61,0xd7,0x7b,0x04,0x00,0x00]
+
+v_writelane_b32 v5, m0, s2
+// GFX12: encoding: [0x05,0x00,0x61,0xd7,0x7d,0x04,0x00,0x00]
+
+v_writelane_b32 v5, exec_lo, s2
+// GFX12: encoding: [0x05,0x00,0x61,0xd7,0x7e,0x04,0x00,0x00]
+
+v_writelane_b32 v5, exec_hi, s105
+// GFX12: encoding: [0x05,0x00,0x61,0xd7,0x7f,0xd2,0x00,0x00]
+
+v_writelane_b32 v5, null, ttmp15
+// GFX12: encoding: [0x05,0x00,0x61,0xd7,0x7c,0xf6,0x00,0x00]
+
+v_writelane_b32 v5, -1, null
+// GFX12: encoding: [0x05,0x00,0x61,0xd7,0xc1,0xf8,0x00,0x00]
+
+v_writelane_b32 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x61,0xd7,0xf0,0xfa,0x00,0x00]
+
+v_writelane_b32 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x61,0xd7,0xfd,0xd4,0x00,0x00]
+
+v_writelane_b32 v255, 0xaf123456, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x61,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_xad_u32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x45,0xd6,0x01,0x05,0x0e,0x00]
+
+v_xad_u32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x45,0xd6,0xff,0x05,0xa4,0x01]
+
+v_xad_u32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x45,0xd6,0x01,0xfe,0xff,0x01]
+
+v_xad_u32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x45,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_xad_u32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x45,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_xad_u32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x45,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_xad_u32 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x45,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_xad_u32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x45,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_xad_u32 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x45,0xd6,0x7e,0x82,0xad,0x01]
+
+v_xad_u32 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x45,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_xad_u32 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x45,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_xad_u32 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x45,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_xad_u32 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x45,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_xad_u32 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x45,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_xad_u32 v255, 0xaf123456, vcc_hi, null
+// GFX12: encoding: [0xff,0x00,0x45,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_xor3_b32 v5, v1, v2, s3
+// GFX12: encoding: [0x05,0x00,0x40,0xd6,0x01,0x05,0x0e,0x00]
+
+v_xor3_b32 v5, v255, s2, s105
+// GFX12: encoding: [0x05,0x00,0x40,0xd6,0xff,0x05,0xa4,0x01]
+
+v_xor3_b32 v5, s1, v255, exec_hi
+// GFX12: encoding: [0x05,0x00,0x40,0xd6,0x01,0xfe,0xff,0x01]
+
+v_xor3_b32 v5, s105, s105, exec_lo
+// GFX12: encoding: [0x05,0x00,0x40,0xd6,0x69,0xd2,0xf8,0x01]
+
+v_xor3_b32 v5, vcc_lo, ttmp15, v3
+// GFX12: encoding: [0x05,0x00,0x40,0xd6,0x6a,0xf6,0x0c,0x04]
+
+v_xor3_b32 v5, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x05,0x00,0x40,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
+v_xor3_b32 v5, ttmp15, src_scc, ttmp15
+// GFX12: encoding: [0x05,0x00,0x40,0xd6,0x7b,0xfa,0xed,0x01]
+
+v_xor3_b32 v5, m0, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x40,0xd6,0x7d,0xe0,0xf5,0x01]
+
+v_xor3_b32 v5, exec_lo, -1, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x40,0xd6,0x7e,0x82,0xad,0x01]
+
+v_xor3_b32 v5, exec_hi, null, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x40,0xd6,0x7f,0xf8,0xa8,0x01]
+
+v_xor3_b32 v5, null, exec_lo, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x40,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+
+v_xor3_b32 v5, -1, exec_hi, src_scc
+// GFX12: encoding: [0x05,0x00,0x40,0xd6,0xc1,0xfe,0xf4,0x03]
+
+v_xor3_b32 v5, 0.5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x40,0xd6,0xf0,0xfa,0xc0,0x03]
+
+v_xor3_b32 v5, src_scc, vcc_lo, -1
+// GFX12: encoding: [0x05,0x00,0x40,0xd6,0xfd,0xd4,0x04,0x03]
+
+v_xor3_b32 v255, 0xaf123456, vcc_hi, null
+// GFX12: encoding: [0xff,0x00,0x40,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_xor_b16 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x64,0xd7,0x01,0x05,0x02,0x00]
+
+v_xor_b16 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x64,0xd7,0xff,0xff,0x03,0x00]
+
+v_xor_b16 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x64,0xd7,0x01,0x04,0x00,0x00]
+
+v_xor_b16 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x64,0xd7,0x69,0xd2,0x00,0x00]
+
+v_xor_b16 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x64,0xd7,0x6a,0xf6,0x00,0x00]
+
+v_xor_b16 v5, vcc_hi, 0xfe0b
+// GFX12: encoding: [0x05,0x00,0x64,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_xor_b16 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x64,0xd7,0x7b,0xfa,0x01,0x00]
+
+v_xor_b16 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x64,0xd7,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_xor_b16 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x64,0xd7,0x7e,0x82,0x01,0x00]
+
+v_xor_b16 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x64,0xd7,0x7f,0xf8,0x00,0x00]
+
+v_xor_b16 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x64,0xd7,0x7c,0xfc,0x00,0x00]
+
+v_xor_b16 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x64,0xd7,0xc1,0xfe,0x00,0x00]
+
+v_xor_b16 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x64,0xd7,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_xor_b16 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x64,0xd7,0xfd,0xd4,0x00,0x00]
+
+v_xor_b16 v255, 0xfe0b, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x64,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_aliases.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_aliases.s
new file mode 100644
index 000000000000..9211877774aa
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_aliases.s
@@ -0,0 +1,49 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
+
+v_min3_f32 v5, v1, v2, v3
+// GFX12: v_min3_num_f32 v5, v1, v2, v3           ; encoding: [0x05,0x00,0x29,0xd6,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v5, v1, v2, v3
+// GFX12: v_max3_num_f32 v5, v1, v2, v3           ; encoding: [0x05,0x00,0x2a,0xd6,0x01,0x05,0x0e,0x04]
+
+v_min3_f16 v5, v1, v2, v3
+// GFX12: v_min3_num_f16 v5, v1, v2, v3           ; encoding: [0x05,0x00,0x2b,0xd6,0x01,0x05,0x0e,0x04]
+
+v_max3_f16 v5, v1, v2, v3
+// GFX12: v_max3_num_f16 v5, v1, v2, v3           ; encoding: [0x05,0x00,0x2c,0xd6,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v5, v1, v2, v3
+// GFX12: v_med3_num_f32 v5, v1, v2, v3           ; encoding: [0x05,0x00,0x31,0xd6,0x01,0x05,0x0e,0x04]
+
+v_med3_f16 v5, v1, v2, v3
+// GFX12: v_med3_num_f16 v5, v1, v2, v3           ; encoding: [0x05,0x00,0x32,0xd6,0x01,0x05,0x0e,0x04]
+
+v_minmax_f32_e64_dpp v0, -v1, -v2, -v3 dpp8:[0,1,2,3,4,5,6,7]
+// GFX12: v_minmax_num_f32_e64_dpp v0, -v1, -v2, -v3 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0x00,0x00,0x68,0xd6,0xe9,0x04,0x0e,0xe4,0x01,0x88,0xc6,0xfa]
+
+v_maxmin_f32_e64_dpp v0, v1, v2, v3 clamp dpp8:[0,1,2,3,4,5,6,7]
+// GFX12: v_maxmin_num_f32_e64_dpp v0, v1, v2, v3 clamp dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0x00,0x80,0x69,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x88,0xc6,0xfa]
+
+v_minmax_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: v_minmax_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_maxmin_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: v_maxmin_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_mad_i64_i32 v[5:6], s12, v1, v2, v[3:4]
+// GFX12: v_mad_co_i64_i32 v[5:6], s12, v1, v2, v[3:4] ; encoding: [0x05,0x0c,0xff,0xd6,0x01,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s12, v1, v2, v[3:4]
+// GFX12: v_mad_co_u64_u32 v[5:6], s12, v1, v2, v[3:4] ; encoding: [0x05,0x0c,0xfe,0xd6,0x01,0x05,0x0e,0x04]
+
+v_max_f64 v[5:6], s[2:3], s[4:5]
+// GFX12: v_max_num_f64_e64 v[5:6], s[2:3], s[4:5] ; encoding: [0x05,0x00,0x0e,0xd5,0x02,0x08,0x00,0x00]
+
+v_min_f64 v[5:6], s[2:3], s[4:5]
+// GFX12: v_min_num_f64_e64 v[5:6], s[2:3], s[4:5] ; encoding: [0x05,0x00,0x0d,0xd5,0x02,0x08,0x00,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, v2
+// GFX11: v_cvt_pk_norm_i16_f16 {{.*}} encoding: [0x05,0x00,0x12,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, v2
+// GFX11: v_cvt_pk_norm_u16_f16 {{.*}} encoding: [0x05,0x00,0x13,0xd7,0x01,0x05,0x02,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
new file mode 100644
index 000000000000..63087442c464
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
@@ -0,0 +1,4695 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W32 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W64 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX12-ERR,W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX12-ERR,W64-ERR --implicit-check-not=error: %s
+
+v_add3_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x55,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_add3_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x55,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_add3_u32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x55,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_add3_u32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_add3_u32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_add3_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_add3_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_add3_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_add3_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_add3_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_add3_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_add3_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x55,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_add3_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_add3_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x55,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_add_co_u32_e64_dpp v5, s6, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x06,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, s6, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x06,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, s6, v1, v2 row_mirror
+// W32: [0x05,0x06,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, s6, v1, v2 row_half_mirror
+// W32: [0x05,0x06,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, s6, v1, v2 row_shl:1
+// W32: [0x05,0x06,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, s6, v1, v2 row_shl:15
+// W32: [0x05,0x06,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, s6, v1, v2 row_shr:1
+// W32: [0x05,0x06,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, s6, v1, v2 row_shr:15
+// W32: [0x05,0x06,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, s6, v1, v2 row_ror:1
+// W32: [0x05,0x06,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, s105, v1, v2 row_ror:15
+// W32: [0x05,0x69,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x05,0x6a,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x05,0x6b,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x05,0x7b,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 row_mirror
+// W64: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 row_half_mirror
+// W64: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shl:1
+// W64: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shl:15
+// W64: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shr:1
+// W64: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shr:15
+// W64: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 row_ror:1
+// W64: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 row_ror:15
+// W64: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x05,0x68,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x05,0x6a,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x05,0x7a,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v255, null, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0xfc,0x00,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_add_lshl_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x47,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_add_lshl_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x47,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_add_lshl_u32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x47,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_add_lshl_u32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_add_lshl_u32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_add_lshl_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_add_lshl_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_add_lshl_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_add_lshl_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_add_lshl_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_add_lshl_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_add_lshl_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x47,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_add_lshl_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_add_lshl_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x47,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_add_nc_i16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_add_nc_i16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_add_nc_i16_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_add_nc_i16_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_add_nc_i16_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_add_nc_i16_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_add_nc_i16_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_add_nc_i16_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_add_nc_i16_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_add_nc_i16_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_add_nc_i16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_add_nc_i16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_add_nc_i16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_add_nc_i16_e64_dpp v255, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x0d,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_add_nc_i32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_add_nc_i32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_add_nc_i32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_add_nc_i32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_add_nc_i32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_add_nc_i32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_add_nc_i32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_add_nc_i32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_add_nc_i32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_add_nc_i32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_add_nc_i32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_add_nc_i32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_add_nc_i32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_add_nc_i32_e64_dpp v255, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x26,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_add_nc_u16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_add_nc_u16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_add_nc_u16_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_add_nc_u16_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_add_nc_u16_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_add_nc_u16_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_add_nc_u16_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_add_nc_u16_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_add_nc_u16_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_add_nc_u16_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_add_nc_u16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_add_nc_u16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_add_nc_u16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_add_nc_u16_e64_dpp v255, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x03,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, v3 row_half_mirror
+// GFX12: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, v255 row_shl:1
+// GFX12: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, s105 row_shl:15
+// GFX12: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, vcc_hi row_shr:1
+// GFX12: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, vcc_lo row_shr:15
+// GFX12: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, ttmp15 row_ror:1
+// GFX12: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, exec_hi row_ror:15
+// GFX12: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, exec_lo row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, null row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, -1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13]
+
+v_alignbit_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x16,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_alignbyte_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x17,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_alignbyte_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x17,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_alignbyte_b32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x17,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_alignbyte_b32_e64_dpp v5, v1, v2, v3 row_half_mirror
+// GFX12: [0x05,0x00,0x17,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
+
+v_alignbyte_b32_e64_dpp v5, v1, v2, v255 row_shl:1
+// GFX12: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
+
+v_alignbyte_b32_e64_dpp v5, v1, v2, s105 row_shl:15
+// GFX12: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff]
+
+v_alignbyte_b32_e64_dpp v5, v1, v2, vcc_hi row_shr:1
+// GFX12: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
+
+v_alignbyte_b32_e64_dpp v5, v1, v2, vcc_lo row_shr:15
+// GFX12: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
+
+v_alignbyte_b32_e64_dpp v5, v1, v2, ttmp15 row_ror:1
+// GFX12: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff]
+
+v_alignbyte_b32_e64_dpp v5, v1, v2, exec_hi row_ror:15
+// GFX12: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
+
+v_alignbyte_b32_e64_dpp v5, v1, v2, exec_lo row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
+
+v_alignbyte_b32_e64_dpp v5, v1, v2, null row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
+
+v_alignbyte_b32_e64_dpp v5, v1, v2, -1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x17,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13]
+
+v_alignbyte_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x17,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_and_b16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_and_b16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_and_b16_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_and_b16_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_and_b16_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_and_b16_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_and_b16_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_and_b16_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_and_b16_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_and_b16_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_and_b16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_and_b16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_and_b16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_and_b16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x62,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_and_or_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x57,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_and_or_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x57,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_and_or_b32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x57,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_and_or_b32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_and_or_b32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_and_or_b32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_and_or_b32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_and_or_b32_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_and_or_b32_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_and_or_b32_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_and_or_b32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_and_or_b32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x57,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_and_or_b32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_and_or_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x57,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_ashrrev_i16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_ashrrev_i16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_ashrrev_i16_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_ashrrev_i16_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_ashrrev_i16_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_ashrrev_i16_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_ashrrev_i16_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_ashrrev_i16_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_ashrrev_i16_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_ashrrev_i16_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_ashrrev_i16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_ashrrev_i16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_ashrrev_i16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_ashrrev_i16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x3a,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_bcnt_u32_b32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_bcnt_u32_b32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_bcnt_u32_b32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x1e,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_bfe_i32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x11,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_bfe_i32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x11,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_bfe_i32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x11,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_bfe_i32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_bfe_i32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_bfe_i32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_bfe_i32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_bfe_i32_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_bfe_i32_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_bfe_i32_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_bfe_i32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_bfe_i32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x11,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_bfe_i32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_bfe_i32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x11,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_bfe_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x10,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_bfe_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x10,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_bfe_u32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x10,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_bfe_u32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_bfe_u32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_bfe_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_bfe_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_bfe_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_bfe_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_bfe_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_bfe_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_bfe_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x10,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_bfe_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_bfe_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x10,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_bfi_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x12,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_bfi_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x12,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_bfi_b32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x12,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_bfi_b32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_bfi_b32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_bfi_b32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_bfi_b32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_bfi_b32_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_bfi_b32_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_bfi_b32_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_bfi_b32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_bfi_b32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x12,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_bfi_b32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_bfi_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x12,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_bfm_b32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_bfm_b32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_bfm_b32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_bfm_b32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_bfm_b32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_bfm_b32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_bfm_b32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_bfm_b32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_bfm_b32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_bfm_b32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_bfm_b32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_bfm_b32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_bfm_b32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_bfm_b32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x1d,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cndmask_b16_e64_dpp v5, v1, v2, s3 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, v1, v2, s3 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, v1, v2, s3 row_mirror
+// W32: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, v1, v2, s3 row_half_mirror
+// W32: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, v1, v2, s3 row_shl:1
+// W32: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, v1, v2, s3 row_shl:15
+// W32: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, v1, v2, s3 row_shr:1
+// W32: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, v1, v2, s3 row_shr:15
+// W32: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, v1, v2, s3 row_ror:1
+// W32: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, v1, v2, s105 row_ror:15
+// W32: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, v1, v2, vcc_hi row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0xae,0x01,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, |v1|, -v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x05,0x01,0x5d,0xd6,0xfa,0x04,0xaa,0x41,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, -v1, |v2|, ttmp15 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x05,0x02,0x5d,0xd6,0xfa,0x04,0xee,0x21,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] quad_perm:[3,2,1,0]
+// W64: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] quad_perm:[0,1,2,3]
+// W64: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] row_mirror
+// W64: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] row_half_mirror
+// W64: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] row_shl:1
+// W64: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] row_shl:15
+// W64: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] row_shr:1
+// W64: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] row_shr:15
+// W64: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] row_ror:1
+// W64: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] row_ror:15
+// W64: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, v1, v2, s[104:105] row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0xa2,0x01,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, |v1|, -v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x05,0x01,0x5d,0xd6,0xfa,0x04,0xaa,0x41,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, -v1, |v2|, ttmp[14:15] row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x05,0x02,0x5d,0xd6,0xfa,0x04,0xea,0x21,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v255, -|v255|, -|v255|, null row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x03,0x5d,0xd6,0xfa,0xfe,0xf3,0x61,0xff,0x6f,0x05,0x30]
+
+v_cubeid_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_cubeid_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_cubeid_f32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_cubeid_f32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_cubeid_f32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_cubeid_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_cubeid_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_cubeid_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15
+// GFX12: [0x05,0x01,0x0c,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+
+v_cubeid_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1
+// GFX12: [0x05,0x02,0x0c,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+
+v_cubeid_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15
+// GFX12: [0x05,0x04,0x0c,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+
+v_cubeid_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x03,0x0c,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+
+v_cubeid_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x05,0x0c,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
+
+v_cubeid_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x06,0x0c,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13]
+
+v_cubeid_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x87,0x0c,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30]
+
+v_cubema_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_cubema_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_cubema_f32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_cubema_f32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_cubema_f32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_cubema_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_cubema_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_cubema_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15
+// GFX12: [0x05,0x01,0x0f,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+
+v_cubema_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1
+// GFX12: [0x05,0x02,0x0f,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+
+v_cubema_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15
+// GFX12: [0x05,0x04,0x0f,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+
+v_cubema_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x03,0x0f,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+
+v_cubema_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x05,0x0f,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
+
+v_cubema_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x06,0x0f,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13]
+
+v_cubema_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x87,0x0f,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30]
+
+v_cubesc_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_cubesc_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_cubesc_f32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_cubesc_f32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_cubesc_f32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_cubesc_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_cubesc_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_cubesc_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15
+// GFX12: [0x05,0x01,0x0d,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+
+v_cubesc_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1
+// GFX12: [0x05,0x02,0x0d,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+
+v_cubesc_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15
+// GFX12: [0x05,0x04,0x0d,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+
+v_cubesc_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x03,0x0d,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+
+v_cubesc_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x05,0x0d,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
+
+v_cubesc_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x06,0x0d,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13]
+
+v_cubesc_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x87,0x0d,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30]
+
+v_cubetc_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_cubetc_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_cubetc_f32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_cubetc_f32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_cubetc_f32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_cubetc_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_cubetc_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_cubetc_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15
+// GFX12: [0x05,0x01,0x0e,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+
+v_cubetc_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1
+// GFX12: [0x05,0x02,0x0e,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+
+v_cubetc_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15
+// GFX12: [0x05,0x04,0x0e,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+
+v_cubetc_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x03,0x0e,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+
+v_cubetc_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x05,0x0e,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
+
+v_cubetc_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x06,0x0e,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13]
+
+v_cubetc_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x87,0x0e,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30]
+
+v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_pk_i16_f32_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x01,0x06,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cvt_pk_i16_f32_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x02,0x06,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cvt_pk_i16_f32_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x03,0x06,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cvt_pk_i16_i32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x24,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x01,0x12,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x02,0x12,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x03,0x12,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x01,0x13,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x02,0x13,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x03,0x13,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_pk_u16_f32_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x01,0x07,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cvt_pk_u16_f32_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x02,0x07,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cvt_pk_u16_f32_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x03,0x07,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cvt_pk_u16_u32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x23,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x26,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x26,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x26,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x26,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_cvt_pk_u8_f32_e64_dpp v255, -|v255|, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x01,0x26,0xd6,0xfa,0xfe,0xf7,0x23,0xff,0x6f,0x05,0x30]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x01,0x12,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x02,0x12,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x03,0x12,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_pk_norm_i16_f32_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x01,0x21,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cvt_pk_norm_i16_f32_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x02,0x21,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cvt_pk_norm_i16_f32_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x03,0x21,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x01,0x13,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x02,0x13,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x03,0x13,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_pk_norm_u16_f32_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x01,0x22,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cvt_pk_norm_u16_f32_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x02,0x22,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cvt_pk_norm_u16_f32_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x03,0x22,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_div_fixup_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x54,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_div_fixup_f16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x54,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_div_fixup_f16_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x54,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_div_fixup_f16_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x54,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_div_fixup_f16_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x54,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_div_fixup_f16_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x54,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_div_fixup_f16_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x54,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_div_fixup_f16_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15
+// GFX12: [0x05,0x01,0x54,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+
+v_div_fixup_f16_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1
+// GFX12: [0x05,0x02,0x54,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+
+v_div_fixup_f16_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15
+// GFX12: [0x05,0x04,0x54,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+
+v_div_fixup_f16_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x03,0x54,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+
+v_div_fixup_f16_e64_dpp v5, -|v1|, v2, -|-1| row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x05,0x54,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01]
+
+v_div_fixup_f16_e64_dpp v5, v1, -|v2|, -|0.5| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x06,0x54,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13]
+
+v_div_fixup_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x87,0x54,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x05,0x30]
+
+v_fma_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x48,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_fma_f16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x48,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_fma_f16_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x48,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_fma_f16_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x48,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_fma_f16_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x48,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_fma_f16_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x48,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_fma_f16_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x48,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_fma_f16_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15
+// GFX12: [0x05,0x01,0x48,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+
+v_fma_f16_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1
+// GFX12: [0x05,0x02,0x48,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+
+v_fma_f16_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15
+// GFX12: [0x05,0x04,0x48,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+
+v_fma_f16_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x03,0x48,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+
+v_fma_f16_e64_dpp v5, -|v1|, v2, -|-1| row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x05,0x48,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01]
+
+v_fma_f16_e64_dpp v5, v1, -|v2|, -|0.5| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x06,0x48,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13]
+
+v_fma_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x87,0x48,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x05,0x30]
+
+v_fma_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x13,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_fma_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x13,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_fma_f32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x13,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_fma_f32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x13,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_fma_f32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x13,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_fma_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x13,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_fma_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x13,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_fma_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15
+// GFX12: [0x05,0x01,0x13,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+
+v_fma_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1
+// GFX12: [0x05,0x02,0x13,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+
+v_fma_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15
+// GFX12: [0x05,0x04,0x13,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+
+v_fma_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x03,0x13,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+
+v_fma_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x05,0x13,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
+
+v_fma_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x06,0x13,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13]
+
+v_fma_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x87,0x13,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30]
+
+v_ldexp_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_ldexp_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_ldexp_f32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_ldexp_f32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_ldexp_f32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_ldexp_f32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_ldexp_f32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_ldexp_f32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_ldexp_f32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_ldexp_f32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_ldexp_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_ldexp_f32_e64_dpp v5, v1, v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x08,0x01,0x5f,0x01,0x01]
+
+v_ldexp_f32_e64_dpp v5, v1, v2 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x10,0x01,0x60,0x09,0x13]
+
+v_ldexp_f32_e64_dpp v255, -|v255|, v255 clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0x1c,0xd7,0xfa,0xfe,0x03,0x38,0xff,0x6f,0x05,0x30]
+
+v_lerp_u8_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x15,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_lerp_u8_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x15,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_lerp_u8_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x15,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_lerp_u8_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_lerp_u8_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_lerp_u8_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_lerp_u8_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_lerp_u8_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_lerp_u8_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_lerp_u8_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_lerp_u8_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_lerp_u8_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x15,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_lerp_u8_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_lerp_u8_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x15,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_lshl_add_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x46,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_lshl_add_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x46,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_lshl_add_u32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x46,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_lshl_add_u32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_lshl_add_u32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_lshl_add_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_lshl_add_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_lshl_add_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_lshl_add_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_lshl_add_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_lshl_add_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_lshl_add_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x46,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_lshl_add_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_lshl_add_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x46,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_lshl_or_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x56,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_lshl_or_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x56,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_lshl_or_b32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x56,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_lshl_or_b32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_lshl_or_b32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_lshl_or_b32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_lshl_or_b32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_lshl_or_b32_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_lshl_or_b32_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_lshl_or_b32_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_lshl_or_b32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_lshl_or_b32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x56,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_lshl_or_b32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_lshl_or_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x56,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_lshlrev_b16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_lshlrev_b16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_lshlrev_b16_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_lshlrev_b16_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_lshlrev_b16_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_lshlrev_b16_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_lshlrev_b16_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_lshlrev_b16_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_lshlrev_b16_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_lshlrev_b16_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_lshlrev_b16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_lshlrev_b16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_lshlrev_b16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_lshlrev_b16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x38,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_lshrrev_b16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_lshrrev_b16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_lshrrev_b16_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_lshrrev_b16_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_lshrrev_b16_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_lshrrev_b16_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_lshrrev_b16_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_lshrrev_b16_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_lshrrev_b16_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_lshrrev_b16_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_lshrrev_b16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_lshrrev_b16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_lshrrev_b16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_lshrrev_b16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x39,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_mad_i16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x53,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_mad_i16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x53,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_mad_i16_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x53,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_mad_i16_e64_dpp v5, v1, v2, v3 row_half_mirror
+// GFX12: [0x05,0x00,0x53,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
+
+v_mad_i16_e64_dpp v5, v1, v2, v255 row_shl:1
+// GFX12: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
+
+v_mad_i16_e64_dpp v5, v1, v2, s105 row_shl:15
+// GFX12: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff]
+
+v_mad_i16_e64_dpp v5, v1, v2, vcc_hi row_shr:1
+// GFX12: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
+
+v_mad_i16_e64_dpp v5, v1, v2, vcc_lo row_shr:15
+// GFX12: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
+
+v_mad_i16_e64_dpp v5, v1, v2, ttmp15 row_ror:1
+// GFX12: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff]
+
+v_mad_i16_e64_dpp v5, v1, v2, exec_hi row_ror:15
+// GFX12: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
+
+v_mad_i16_e64_dpp v5, v1, v2, exec_lo row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
+
+v_mad_i16_e64_dpp v5, v1, v2, null row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
+
+v_mad_i16_e64_dpp v5, v1, v2, -1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x53,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13]
+
+v_mad_i16_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x53,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_mad_i32_i16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_mad_i32_i16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_mad_i32_i16_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_mad_i32_i16_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_mad_i32_i16_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_mad_i32_i16_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_mad_i32_i16_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_mad_i32_i16_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_mad_i32_i16_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_mad_i32_i16_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_mad_i32_i16_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_mad_i32_i16_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_mad_i32_i16_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_mad_i32_i16_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x5a,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_mad_i32_i24_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_mad_i32_i24_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_mad_i32_i24_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_mad_i32_i24_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_mad_i32_i24_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_mad_i32_i24_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_mad_i32_i24_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_mad_i32_i24_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_mad_i32_i24_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_mad_i32_i24_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_mad_i32_i24_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_mad_i32_i24_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_mad_i32_i24_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_mad_i32_i24_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x0a,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_mad_u16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x41,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_mad_u16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x41,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_mad_u16_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x41,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_mad_u16_e64_dpp v5, v1, v2, v3 row_half_mirror
+// GFX12: [0x05,0x00,0x41,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
+
+v_mad_u16_e64_dpp v5, v1, v2, v255 row_shl:1
+// GFX12: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
+
+v_mad_u16_e64_dpp v5, v1, v2, s105 row_shl:15
+// GFX12: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff]
+
+v_mad_u16_e64_dpp v5, v1, v2, vcc_hi row_shr:1
+// GFX12: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
+
+v_mad_u16_e64_dpp v5, v1, v2, vcc_lo row_shr:15
+// GFX12: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
+
+v_mad_u16_e64_dpp v5, v1, v2, ttmp15 row_ror:1
+// GFX12: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff]
+
+v_mad_u16_e64_dpp v5, v1, v2, exec_hi row_ror:15
+// GFX12: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
+
+v_mad_u16_e64_dpp v5, v1, v2, exec_lo row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
+
+v_mad_u16_e64_dpp v5, v1, v2, null row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
+
+v_mad_u16_e64_dpp v5, v1, v2, -1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x41,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13]
+
+v_mad_u16_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x41,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_mad_u32_u16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x59,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_mad_u32_u16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x59,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_mad_u32_u16_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x59,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_mad_u32_u16_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_mad_u32_u16_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_mad_u32_u16_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_mad_u32_u16_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_mad_u32_u16_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_mad_u32_u16_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_mad_u32_u16_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_mad_u32_u16_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_mad_u32_u16_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x59,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_mad_u32_u16_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_mad_u32_u16_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x59,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_mad_u32_u24_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_mad_u32_u24_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_mad_u32_u24_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_mad_u32_u24_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_mad_u32_u24_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_mad_u32_u24_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_mad_u32_u24_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_mad_u32_u24_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_mad_u32_u24_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_mad_u32_u24_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_mad_u32_u24_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_mad_u32_u24_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_mad_u32_u24_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_mad_u32_u24_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x0b,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_max3_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x2c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_max3_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x2c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_max3_num_f16_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x2c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_max3_num_f16_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x2c,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_max3_num_f16_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x2c,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_max3_num_f16_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x2c,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_max3_num_f16_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x2c,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_max3_num_f16_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15
+// GFX12: [0x05,0x01,0x2c,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+
+v_max3_num_f16_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1
+// GFX12: [0x05,0x02,0x2c,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+
+v_max3_num_f16_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15
+// GFX12: [0x05,0x04,0x2c,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+
+v_max3_num_f16_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x03,0x2c,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+
+v_max3_num_f16_e64_dpp v5, -|v1|, v2, -|-1| row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x05,0x2c,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01]
+
+v_max3_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x06,0x2c,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13]
+
+v_max3_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x87,0x2c,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x05,0x30]
+
+v_max3_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x2a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_max3_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x2a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_max3_num_f32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x2a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_max3_num_f32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x2a,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_max3_num_f32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x2a,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_max3_num_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x2a,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_max3_num_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x2a,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_max3_num_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15
+// GFX12: [0x05,0x01,0x2a,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+
+v_max3_num_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1
+// GFX12: [0x05,0x02,0x2a,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+
+v_max3_num_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15
+// GFX12: [0x05,0x04,0x2a,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+
+v_max3_num_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x03,0x2a,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+
+v_max3_num_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x05,0x2a,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
+
+v_max3_num_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x06,0x2a,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13]
+
+v_max3_num_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x87,0x2a,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30]
+
+v_max3_i16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_max3_i16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_max3_i16_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_max3_i16_e64_dpp v5, v1, v2, v3 row_half_mirror
+// GFX12: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
+
+v_max3_i16_e64_dpp v5, v1, v2, v255 row_shl:1
+// GFX12: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
+
+v_max3_i16_e64_dpp v5, v1, v2, s105 row_shl:15
+// GFX12: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff]
+
+v_max3_i16_e64_dpp v5, v1, v2, vcc_hi row_shr:1
+// GFX12: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
+
+v_max3_i16_e64_dpp v5, v1, v2, vcc_lo row_shr:15
+// GFX12: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
+
+v_max3_i16_e64_dpp v5, v1, v2, ttmp15 row_ror:1
+// GFX12: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff]
+
+v_max3_i16_e64_dpp v5, v1, v2, exec_hi row_ror:15
+// GFX12: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
+
+v_max3_i16_e64_dpp v5, v1, v2, exec_lo row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
+
+v_max3_i16_e64_dpp v5, v1, v2, null row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
+
+v_max3_i16_e64_dpp v5, v1, v2, -1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13]
+
+v_max3_i16_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x4d,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_max3_i32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_max3_i32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_max3_i32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_max3_i32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_max3_i32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_max3_i32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_max3_i32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_max3_i32_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_max3_i32_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_max3_i32_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_max3_i32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_max3_i32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_max3_i32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_max3_i32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x1d,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_max3_u16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_max3_u16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_max3_u16_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_max3_u16_e64_dpp v5, v1, v2, v3 row_half_mirror
+// GFX12: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
+
+v_max3_u16_e64_dpp v5, v1, v2, v255 row_shl:1
+// GFX12: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
+
+v_max3_u16_e64_dpp v5, v1, v2, s105 row_shl:15
+// GFX12: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff]
+
+v_max3_u16_e64_dpp v5, v1, v2, vcc_hi row_shr:1
+// GFX12: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
+
+v_max3_u16_e64_dpp v5, v1, v2, vcc_lo row_shr:15
+// GFX12: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
+
+v_max3_u16_e64_dpp v5, v1, v2, ttmp15 row_ror:1
+// GFX12: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff]
+
+v_max3_u16_e64_dpp v5, v1, v2, exec_hi row_ror:15
+// GFX12: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
+
+v_max3_u16_e64_dpp v5, v1, v2, exec_lo row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
+
+v_max3_u16_e64_dpp v5, v1, v2, null row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
+
+v_max3_u16_e64_dpp v5, v1, v2, -1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13]
+
+v_max3_u16_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x4e,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_max3_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_max3_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_max3_u32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_max3_u32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_max3_u32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_max3_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_max3_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_max3_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_max3_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_max3_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_max3_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_max3_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_max3_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_max3_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x1e,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_max_i16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_max_i16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_max_i16_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_max_i16_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_max_i16_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_max_i16_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_max_i16_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_max_i16_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_max_i16_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_max_i16_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_max_i16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_max_i16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_max_i16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_max_i16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x0a,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_max_u16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_max_u16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_max_u16_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_max_u16_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_max_u16_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_max_u16_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_max_u16_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_max_u16_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_max_u16_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_max_u16_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_max_u16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_max_u16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_max_u16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_max_u16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x09,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_maxmin_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x6b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_maxmin_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x6b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_maxmin_num_f16_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x6b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_maxmin_num_f16_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x6b,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_maxmin_num_f16_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x6b,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_maxmin_num_f16_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x6b,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_maxmin_num_f16_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x6b,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_maxmin_num_f16_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15
+// GFX12: [0x05,0x01,0x6b,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+
+v_maxmin_num_f16_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1
+// GFX12: [0x05,0x02,0x6b,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+
+v_maxmin_num_f16_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15
+// GFX12: [0x05,0x04,0x6b,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+
+v_maxmin_num_f16_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x03,0x6b,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+
+v_maxmin_num_f16_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x05,0x6b,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
+
+v_maxmin_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x06,0x6b,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13]
+
+v_maxmin_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x87,0x6b,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30]
+
+v_maxmin_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x69,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_maxmin_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x69,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_maxmin_num_f32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x69,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_maxmin_num_f32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x69,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_maxmin_num_f32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x69,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_maxmin_num_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x69,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_maxmin_num_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x69,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_maxmin_num_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15
+// GFX12: [0x05,0x01,0x69,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+
+v_maxmin_num_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1
+// GFX12: [0x05,0x02,0x69,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+
+v_maxmin_num_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15
+// GFX12: [0x05,0x04,0x69,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+
+v_maxmin_num_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x03,0x69,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+
+v_maxmin_num_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x05,0x69,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
+
+v_maxmin_num_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x06,0x69,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13]
+
+v_maxmin_num_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x87,0x69,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30]
+
+v_maxmin_i32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x64,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_maxmin_i32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x64,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_maxmin_i32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x64,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_maxmin_i32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_maxmin_i32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_maxmin_i32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_maxmin_i32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_maxmin_i32_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_maxmin_i32_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_maxmin_i32_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_maxmin_i32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_maxmin_i32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x64,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_maxmin_i32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_maxmin_i32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x64,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_maxmin_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x62,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_maxmin_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x62,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_maxmin_u32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x62,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_maxmin_u32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_maxmin_u32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_maxmin_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_maxmin_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_maxmin_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_maxmin_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_maxmin_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_maxmin_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_maxmin_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x62,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_maxmin_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_maxmin_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x62,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_mbcnt_hi_u32_b32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x20,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_mbcnt_lo_u32_b32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x1f,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_med3_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x32,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_med3_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x32,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_med3_num_f16_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x32,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_med3_num_f16_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x32,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_med3_num_f16_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x32,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_med3_num_f16_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x32,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_med3_num_f16_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x32,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_med3_num_f16_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15
+// GFX12: [0x05,0x01,0x32,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+
+v_med3_num_f16_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1
+// GFX12: [0x05,0x02,0x32,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+
+v_med3_num_f16_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15
+// GFX12: [0x05,0x04,0x32,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+
+v_med3_num_f16_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x03,0x32,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+
+v_med3_num_f16_e64_dpp v5, -|v1|, v2, -|-1| row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x05,0x32,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01]
+
+v_med3_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x06,0x32,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13]
+
+v_med3_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x87,0x32,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x05,0x30]
+
+v_med3_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x31,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_med3_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x31,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_med3_num_f32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x31,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_med3_num_f32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x31,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_med3_num_f32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x31,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_med3_num_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x31,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_med3_num_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x31,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_med3_num_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15
+// GFX12: [0x05,0x01,0x31,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+
+v_med3_num_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1
+// GFX12: [0x05,0x02,0x31,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+
+v_med3_num_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15
+// GFX12: [0x05,0x04,0x31,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+
+v_med3_num_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x03,0x31,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+
+v_med3_num_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x05,0x31,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
+
+v_med3_num_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x06,0x31,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13]
+
+v_med3_num_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x87,0x31,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30]
+
+v_med3_i16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x50,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_med3_i16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x50,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_med3_i16_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x50,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_med3_i16_e64_dpp v5, v1, v2, v3 row_half_mirror
+// GFX12: [0x05,0x00,0x50,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
+
+v_med3_i16_e64_dpp v5, v1, v2, v255 row_shl:1
+// GFX12: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
+
+v_med3_i16_e64_dpp v5, v1, v2, s105 row_shl:15
+// GFX12: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff]
+
+v_med3_i16_e64_dpp v5, v1, v2, vcc_hi row_shr:1
+// GFX12: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
+
+v_med3_i16_e64_dpp v5, v1, v2, vcc_lo row_shr:15
+// GFX12: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
+
+v_med3_i16_e64_dpp v5, v1, v2, ttmp15 row_ror:1
+// GFX12: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff]
+
+v_med3_i16_e64_dpp v5, v1, v2, exec_hi row_ror:15
+// GFX12: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
+
+v_med3_i16_e64_dpp v5, v1, v2, exec_lo row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
+
+v_med3_i16_e64_dpp v5, v1, v2, null row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
+
+v_med3_i16_e64_dpp v5, v1, v2, -1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x50,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13]
+
+v_med3_i16_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x50,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_med3_i32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x20,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_med3_i32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x20,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_med3_i32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x20,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_med3_i32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_med3_i32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_med3_i32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_med3_i32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_med3_i32_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_med3_i32_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_med3_i32_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_med3_i32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_med3_i32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x20,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_med3_i32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_med3_i32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x20,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_med3_u16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x51,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_med3_u16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x51,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_med3_u16_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x51,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_med3_u16_e64_dpp v5, v1, v2, v3 row_half_mirror
+// GFX12: [0x05,0x00,0x51,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
+
+v_med3_u16_e64_dpp v5, v1, v2, v255 row_shl:1
+// GFX12: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
+
+v_med3_u16_e64_dpp v5, v1, v2, s105 row_shl:15
+// GFX12: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff]
+
+v_med3_u16_e64_dpp v5, v1, v2, vcc_hi row_shr:1
+// GFX12: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
+
+v_med3_u16_e64_dpp v5, v1, v2, vcc_lo row_shr:15
+// GFX12: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
+
+v_med3_u16_e64_dpp v5, v1, v2, ttmp15 row_ror:1
+// GFX12: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff]
+
+v_med3_u16_e64_dpp v5, v1, v2, exec_hi row_ror:15
+// GFX12: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
+
+v_med3_u16_e64_dpp v5, v1, v2, exec_lo row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
+
+v_med3_u16_e64_dpp v5, v1, v2, null row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
+
+v_med3_u16_e64_dpp v5, v1, v2, -1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x51,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13]
+
+v_med3_u16_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x51,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_med3_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x21,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_med3_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x21,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_med3_u32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x21,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_med3_u32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_med3_u32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_med3_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_med3_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_med3_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_med3_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_med3_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_med3_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_med3_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x21,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_med3_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_med3_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x21,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_min3_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x2b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_min3_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x2b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_min3_num_f16_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x2b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_min3_num_f16_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x2b,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_min3_num_f16_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x2b,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_min3_num_f16_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x2b,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_min3_num_f16_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x2b,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_min3_num_f16_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15
+// GFX12: [0x05,0x01,0x2b,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+
+v_min3_num_f16_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1
+// GFX12: [0x05,0x02,0x2b,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+
+v_min3_num_f16_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15
+// GFX12: [0x05,0x04,0x2b,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+
+v_min3_num_f16_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x03,0x2b,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+
+v_min3_num_f16_e64_dpp v5, -|v1|, v2, -|-1| row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x05,0x2b,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01]
+
+v_min3_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x06,0x2b,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13]
+
+v_min3_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x87,0x2b,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x05,0x30]
+
+v_min3_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x29,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_min3_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x29,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_min3_num_f32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x29,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_min3_num_f32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x29,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_min3_num_f32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x29,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_min3_num_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x29,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_min3_num_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x29,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_min3_num_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15
+// GFX12: [0x05,0x01,0x29,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+
+v_min3_num_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1
+// GFX12: [0x05,0x02,0x29,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+
+v_min3_num_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15
+// GFX12: [0x05,0x04,0x29,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+
+v_min3_num_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x03,0x29,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+
+v_min3_num_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x05,0x29,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
+
+v_min3_num_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x06,0x29,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13]
+
+v_min3_num_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x87,0x29,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30]
+
+v_min3_i16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_min3_i16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_min3_i16_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_min3_i16_e64_dpp v5, v1, v2, v3 row_half_mirror
+// GFX12: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
+
+v_min3_i16_e64_dpp v5, v1, v2, v255 row_shl:1
+// GFX12: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
+
+v_min3_i16_e64_dpp v5, v1, v2, s105 row_shl:15
+// GFX12: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff]
+
+v_min3_i16_e64_dpp v5, v1, v2, vcc_hi row_shr:1
+// GFX12: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
+
+v_min3_i16_e64_dpp v5, v1, v2, vcc_lo row_shr:15
+// GFX12: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
+
+v_min3_i16_e64_dpp v5, v1, v2, ttmp15 row_ror:1
+// GFX12: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff]
+
+v_min3_i16_e64_dpp v5, v1, v2, exec_hi row_ror:15
+// GFX12: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
+
+v_min3_i16_e64_dpp v5, v1, v2, exec_lo row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
+
+v_min3_i16_e64_dpp v5, v1, v2, null row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
+
+v_min3_i16_e64_dpp v5, v1, v2, -1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13]
+
+v_min3_i16_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x4a,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_min3_i32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_min3_i32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_min3_i32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_min3_i32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_min3_i32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_min3_i32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_min3_i32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_min3_i32_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_min3_i32_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_min3_i32_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_min3_i32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_min3_i32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_min3_i32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_min3_i32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x1a,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_min3_u16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_min3_u16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_min3_u16_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_min3_u16_e64_dpp v5, v1, v2, v3 row_half_mirror
+// GFX12: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
+
+v_min3_u16_e64_dpp v5, v1, v2, v255 row_shl:1
+// GFX12: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
+
+v_min3_u16_e64_dpp v5, v1, v2, s105 row_shl:15
+// GFX12: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff]
+
+v_min3_u16_e64_dpp v5, v1, v2, vcc_hi row_shr:1
+// GFX12: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
+
+v_min3_u16_e64_dpp v5, v1, v2, vcc_lo row_shr:15
+// GFX12: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
+
+v_min3_u16_e64_dpp v5, v1, v2, ttmp15 row_ror:1
+// GFX12: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff]
+
+v_min3_u16_e64_dpp v5, v1, v2, exec_hi row_ror:15
+// GFX12: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
+
+v_min3_u16_e64_dpp v5, v1, v2, exec_lo row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
+
+v_min3_u16_e64_dpp v5, v1, v2, null row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
+
+v_min3_u16_e64_dpp v5, v1, v2, -1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13]
+
+v_min3_u16_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x4b,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_min3_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_min3_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_min3_u32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_min3_u32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_min3_u32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_min3_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_min3_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_min3_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_min3_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_min3_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_min3_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_min3_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_min3_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_min3_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x1b,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_min_i16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_min_i16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_min_i16_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_min_i16_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_min_i16_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_min_i16_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_min_i16_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_min_i16_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_min_i16_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_min_i16_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_min_i16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_min_i16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_min_i16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_min_i16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x0c,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_min_u16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_min_u16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_min_u16_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_min_u16_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_min_u16_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_min_u16_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_min_u16_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_min_u16_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_min_u16_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_min_u16_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_min_u16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_min_u16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_min_u16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_min_u16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x0b,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_minmax_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x6a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_minmax_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x6a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_minmax_num_f16_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x6a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_minmax_num_f16_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x6a,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_minmax_num_f16_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x6a,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_minmax_num_f16_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x6a,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_minmax_num_f16_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x6a,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_minmax_num_f16_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15
+// GFX12: [0x05,0x01,0x6a,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+
+v_minmax_num_f16_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1
+// GFX12: [0x05,0x02,0x6a,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+
+v_minmax_num_f16_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15
+// GFX12: [0x05,0x04,0x6a,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+
+v_minmax_num_f16_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x03,0x6a,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+
+v_minmax_num_f16_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x05,0x6a,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
+
+v_minmax_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x06,0x6a,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13]
+
+v_minmax_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x87,0x6a,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30]
+
+v_minmax_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x68,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_minmax_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x68,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_minmax_num_f32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x68,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_minmax_num_f32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x68,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_minmax_num_f32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x68,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_minmax_num_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x68,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_minmax_num_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x68,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_minmax_num_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15
+// GFX12: [0x05,0x01,0x68,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+
+v_minmax_num_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1
+// GFX12: [0x05,0x02,0x68,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+
+v_minmax_num_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15
+// GFX12: [0x05,0x04,0x68,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+
+v_minmax_num_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x03,0x68,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+
+v_minmax_num_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x05,0x68,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
+
+v_minmax_num_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x06,0x68,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13]
+
+v_minmax_num_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x87,0x68,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30]
+
+v_minmax_i32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x65,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_minmax_i32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x65,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_minmax_i32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x65,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_minmax_i32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_minmax_i32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_minmax_i32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_minmax_i32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_minmax_i32_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_minmax_i32_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_minmax_i32_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_minmax_i32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_minmax_i32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x65,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_minmax_i32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_minmax_i32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x65,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_minmax_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x63,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_minmax_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x63,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_minmax_u32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x63,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_minmax_u32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_minmax_u32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_minmax_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_minmax_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_minmax_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_minmax_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_minmax_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_minmax_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_minmax_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x63,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_minmax_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_minmax_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x63,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_msad_u8_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x39,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_msad_u8_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x39,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_msad_u8_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x39,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_msad_u8_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_msad_u8_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_msad_u8_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_msad_u8_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_msad_u8_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_msad_u8_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_msad_u8_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_msad_u8_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_msad_u8_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x39,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_msad_u8_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_msad_u8_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x39,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_mul_lo_u16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_mul_lo_u16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_mul_lo_u16_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_mul_lo_u16_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_mul_lo_u16_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_mul_lo_u16_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_mul_lo_u16_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_mul_lo_u16_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_mul_lo_u16_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_mul_lo_u16_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_mul_lo_u16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_mul_lo_u16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_mul_lo_u16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_mul_lo_u16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x05,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_mullit_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x18,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_mullit_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x18,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_mullit_f32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x18,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_mullit_f32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x18,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_mullit_f32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x18,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_mullit_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x18,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_mullit_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x18,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_mullit_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15
+// GFX12: [0x05,0x01,0x18,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+
+v_mullit_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1
+// GFX12: [0x05,0x02,0x18,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+
+v_mullit_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15
+// GFX12: [0x05,0x04,0x18,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+
+v_mullit_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x03,0x18,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+
+v_mullit_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x05,0x18,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
+
+v_mullit_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x06,0x18,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13]
+
+v_mullit_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x87,0x18,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30]
+
+v_or3_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x58,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_or3_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x58,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_or3_b32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x58,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_or3_b32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_or3_b32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_or3_b32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_or3_b32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_or3_b32_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_or3_b32_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_or3_b32_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_or3_b32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_or3_b32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x58,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_or3_b32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_or3_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x58,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_or_b16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_or_b16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_or_b16_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_or_b16_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_or_b16_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_or_b16_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_or_b16_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_or_b16_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_or_b16_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_or_b16_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_or_b16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_or_b16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_or_b16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_or_b16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x63,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_pack_b32_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_pack_b32_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_pack_b32_f16_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_pack_b32_f16_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_pack_b32_f16_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_pack_b32_f16_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_pack_b32_f16_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_pack_b32_f16_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_pack_b32_f16_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_pack_b32_f16_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_pack_b32_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_pack_b32_f16_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x01,0x11,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_pack_b32_f16_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x02,0x11,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_pack_b32_f16_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x03,0x11,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_perm_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x44,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_perm_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x44,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_perm_b32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x44,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_perm_b32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_perm_b32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_perm_b32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_perm_b32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_perm_b32_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_perm_b32_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_perm_b32_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_perm_b32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_perm_b32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x44,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_perm_b32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_perm_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x44,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_sad_hi_u8_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x23,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_sad_hi_u8_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x23,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_sad_hi_u8_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x23,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_sad_hi_u8_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_sad_hi_u8_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_sad_hi_u8_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_sad_hi_u8_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_sad_hi_u8_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_sad_hi_u8_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_sad_hi_u8_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_sad_hi_u8_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_sad_hi_u8_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x23,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_sad_hi_u8_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_sad_hi_u8_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x23,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_sad_u16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x24,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_sad_u16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x24,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_sad_u16_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x24,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_sad_u16_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_sad_u16_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_sad_u16_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_sad_u16_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_sad_u16_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_sad_u16_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_sad_u16_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_sad_u16_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_sad_u16_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x24,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_sad_u16_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_sad_u16_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x24,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_sad_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x25,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_sad_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x25,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_sad_u32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x25,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_sad_u32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_sad_u32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_sad_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_sad_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_sad_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_sad_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_sad_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_sad_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_sad_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x25,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_sad_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_sad_u32_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x25,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_sad_u8_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x22,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_sad_u8_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x22,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_sad_u8_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x22,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_sad_u8_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_sad_u8_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_sad_u8_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_sad_u8_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_sad_u8_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_sad_u8_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_sad_u8_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_sad_u8_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_sad_u8_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x22,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_sad_u8_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_sad_u8_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x22,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_sub_co_u32_e64_dpp v5, s6, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x06,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, s6, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x06,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, s6, v1, v2 row_mirror
+// W32: [0x05,0x06,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, s6, v1, v2 row_half_mirror
+// W32: [0x05,0x06,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, s6, v1, v2 row_shl:1
+// W32: [0x05,0x06,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, s6, v1, v2 row_shl:15
+// W32: [0x05,0x06,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, s6, v1, v2 row_shr:1
+// W32: [0x05,0x06,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, s6, v1, v2 row_shr:15
+// W32: [0x05,0x06,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, s6, v1, v2 row_ror:1
+// W32: [0x05,0x06,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, s105, v1, v2 row_ror:15
+// W32: [0x05,0x69,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x05,0x6a,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x05,0x6b,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x05,0x7b,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 row_mirror
+// W64: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 row_half_mirror
+// W64: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shl:1
+// W64: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shl:15
+// W64: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shr:1
+// W64: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shr:15
+// W64: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 row_ror:1
+// W64: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 row_ror:15
+// W64: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x05,0x68,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x05,0x6a,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x05,0x7a,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v255, null, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0xfc,0x01,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_sub_nc_i16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_sub_nc_i16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_sub_nc_i16_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_sub_nc_i16_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_sub_nc_i16_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_sub_nc_i16_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_sub_nc_i16_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_sub_nc_i16_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_sub_nc_i16_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_sub_nc_i16_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_sub_nc_i16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_sub_nc_i16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_sub_nc_i16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_sub_nc_i16_e64_dpp v255, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x0e,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_sub_nc_i32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_sub_nc_i32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_sub_nc_i32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_sub_nc_i32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_sub_nc_i32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_sub_nc_i32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_sub_nc_i32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_sub_nc_i32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_sub_nc_i32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_sub_nc_i32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_sub_nc_i32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_sub_nc_i32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_sub_nc_i32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_sub_nc_i32_e64_dpp v255, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x25,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_sub_nc_u16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_sub_nc_u16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_sub_nc_u16_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_sub_nc_u16_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_sub_nc_u16_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_sub_nc_u16_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_sub_nc_u16_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_sub_nc_u16_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_sub_nc_u16_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_sub_nc_u16_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_sub_nc_u16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_sub_nc_u16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_sub_nc_u16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_sub_nc_u16_e64_dpp v255, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x04,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_subrev_co_u32_e64_dpp v5, s6, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x06,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, s6, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x06,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, s6, v1, v2 row_mirror
+// W32: [0x05,0x06,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, s6, v1, v2 row_half_mirror
+// W32: [0x05,0x06,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, s6, v1, v2 row_shl:1
+// W32: [0x05,0x06,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, s6, v1, v2 row_shl:15
+// W32: [0x05,0x06,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, s6, v1, v2 row_shr:1
+// W32: [0x05,0x06,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, s6, v1, v2 row_shr:15
+// W32: [0x05,0x06,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, s6, v1, v2 row_ror:1
+// W32: [0x05,0x06,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, s105, v1, v2 row_ror:15
+// W32: [0x05,0x69,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x05,0x6a,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x05,0x6b,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x05,0x7b,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 row_mirror
+// W64: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 row_half_mirror
+// W64: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shl:1
+// W64: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shl:15
+// W64: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shr:1
+// W64: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shr:15
+// W64: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 row_ror:1
+// W64: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 row_ror:15
+// W64: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x05,0x68,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x05,0x6a,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x05,0x7a,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v255, null, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0xfc,0x02,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_xad_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x45,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_xad_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x45,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_xad_u32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x45,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_xad_u32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_xad_u32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_xad_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_xad_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_xad_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_xad_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_xad_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_xad_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_xad_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x45,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_xad_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_xad_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x45,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_xor3_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x40,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+
+v_xor3_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x40,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+
+v_xor3_b32_e64_dpp v5, v1, v2, v3 row_mirror
+// GFX12: [0x05,0x00,0x40,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+
+v_xor3_b32_e64_dpp v5, v1, v2, v255 row_half_mirror
+// GFX12: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+
+v_xor3_b32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX12: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_xor3_b32_e64_dpp v5, v1, v2, vcc_hi row_shl:15
+// GFX12: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+
+v_xor3_b32_e64_dpp v5, v1, v2, vcc_lo row_shr:1
+// GFX12: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+
+v_xor3_b32_e64_dpp v5, v1, v2, ttmp15 row_shr:15
+// GFX12: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+
+v_xor3_b32_e64_dpp v5, v1, v2, exec_hi row_ror:1
+// GFX12: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+
+v_xor3_b32_e64_dpp v5, v1, v2, exec_lo row_ror:15
+// GFX12: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+
+v_xor3_b32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+
+v_xor3_b32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x40,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+
+v_xor3_b32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
+
+v_xor3_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x40,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+
+v_xor_b16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_xor_b16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_xor_b16_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_xor_b16_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_xor_b16_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_xor_b16_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_xor_b16_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_xor_b16_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_xor_b16_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_xor_b16_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_xor_b16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_xor_b16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_xor_b16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_xor_b16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x64,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_add_nc_i16_e64_dpp v5, v1, v2 op_sel:[1,1,1] row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x58,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_add_nc_i16_e64_dpp v5, v1, v2 op_sel:[1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x08,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_add_nc_i16_e64_dpp v5, v1, v2 op_sel:[0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3
+// GFX12: [0x05,0x10,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+
+v_add_nc_i16_e64_dpp v255, v255, v255 op_sel:[0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1
+// GFX12: [0xff,0xc0,0x0d,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+
+v_add_nc_u16_e64_dpp v5, v1, v2 op_sel:[1,1,1] row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x58,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_add_nc_u16_e64_dpp v5, v1, v2 op_sel:[1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x08,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_add_nc_u16_e64_dpp v5, v1, v2 op_sel:[0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3
+// GFX12: [0x05,0x10,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+
+v_add_nc_u16_e64_dpp v255, v255, v255 op_sel:[0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1
+// GFX12: [0xff,0xc0,0x03,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, -v1, |v2| op_sel:[1,0,0] row_xmask:0 row_mask:0x1 bank_mask:0x3
+// GFX12: [0x05,0x0a,0x12,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v255, -|v255|, -|v255| op_sel:[0,1,0] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1
+// GFX12: [0xff,0x13,0x12,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, -v1, |v2| op_sel:[1,0,0] row_xmask:0 row_mask:0x1 bank_mask:0x3
+// GFX12: [0x05,0x0a,0x13,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v255, -|v255|, -|v255| op_sel:[0,1,0] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1
+// GFX12: [0xff,0x13,0x13,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+
+v_div_fixup_f16_e64_dpp v5, -v1, v2, |exec_lo| op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x7c,0x54,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+
+v_div_fixup_f16_e64_dpp v5, -|v1|, -|v2|, null op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x0b,0x54,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+
+v_div_fixup_f16_e64_dpp v5, -|v1|, v2, -|-1| op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x15,0x54,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01]
+
+v_div_fixup_f16_e64_dpp v5, v1, -|v2|, -|0.5| op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3
+// GFX12: [0x05,0x26,0x54,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x01,0x13]
+
+v_div_fixup_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1
+// GFX12: [0xff,0xc7,0x54,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30]
+
+v_fma_f16_e64_dpp v5, -v1, v2, |exec_lo| op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x7c,0x48,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+
+v_fma_f16_e64_dpp v5, -|v1|, -|v2|, null op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x0b,0x48,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+
+v_fma_f16_e64_dpp v5, -|v1|, v2, -|-1| op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x15,0x48,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01]
+
+v_fma_f16_e64_dpp v5, v1, -|v2|, -|0.5| op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3
+// GFX12: [0x05,0x26,0x48,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x01,0x13]
+
+v_fma_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1
+// GFX12: [0xff,0xc7,0x48,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30]
+
+v_mad_i16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x78,0x53,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
+
+v_mad_i16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x08,0x53,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
+
+v_mad_i16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x10,0x53,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
+
+v_mad_i16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3
+// GFX12: [0x05,0x20,0x53,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13]
+
+v_mad_i16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1
+// GFX12: [0xff,0xc0,0x53,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+
+v_mad_i32_i16_e64_dpp v5, v1, v2, 0.5 op_sel:[1,0,0,0] row_xmask:0 row_mask:0x1 bank_mask:0x3
+// GFX12: [0x05,0x08,0x5a,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+
+v_mad_i32_i16_e64_dpp v255, v255, v255, src_scc op_sel:[0,1,0,0] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1
+// GFX12: [0xff,0x90,0x5a,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+
+v_mad_u16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x78,0x41,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
+
+v_mad_u16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x08,0x41,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
+
+v_mad_u16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x10,0x41,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
+
+v_mad_u16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3
+// GFX12: [0x05,0x20,0x41,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13]
+
+v_mad_u16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1
+// GFX12: [0xff,0xc0,0x41,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+
+v_mad_u32_u16_e64_dpp v5, v1, v2, 0.5 op_sel:[1,0,0,0] row_xmask:0 row_mask:0x1 bank_mask:0x3
+// GFX12: [0x05,0x08,0x59,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+
+v_mad_u32_u16_e64_dpp v255, v255, v255, src_scc op_sel:[0,1,0,0] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1
+// GFX12: [0xff,0x90,0x59,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+
+v_max3_num_f16_e64_dpp v5, -v1, v2, |exec_lo| op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x7c,0x2c,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+
+v_max3_num_f16_e64_dpp v5, -|v1|, -|v2|, null op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x0b,0x2c,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+
+v_max3_num_f16_e64_dpp v5, -|v1|, v2, -|-1| op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x15,0x2c,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01]
+
+v_max3_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3
+// GFX12: [0x05,0x26,0x2c,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x01,0x13]
+
+v_max3_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1
+// GFX12: [0xff,0xc7,0x2c,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30]
+
+v_max3_i16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x78,0x4d,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
+
+v_max3_i16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x08,0x4d,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
+
+v_max3_i16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x10,0x4d,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
+
+v_max3_i16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3
+// GFX12: [0x05,0x20,0x4d,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13]
+
+v_max3_i16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1
+// GFX12: [0xff,0x40,0x4d,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+
+v_max3_u16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x78,0x4e,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
+
+v_max3_u16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x08,0x4e,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
+
+v_max3_u16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x10,0x4e,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
+
+v_max3_u16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3
+// GFX12: [0x05,0x20,0x4e,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13]
+
+v_max3_u16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1
+// GFX12: [0xff,0x40,0x4e,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+
+v_med3_num_f16_e64_dpp v5, -v1, v2, |exec_lo| op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x7c,0x32,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+
+v_med3_num_f16_e64_dpp v5, -|v1|, -|v2|, null op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x0b,0x32,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+
+v_med3_num_f16_e64_dpp v5, -|v1|, v2, -|-1| op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x15,0x32,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01]
+
+v_med3_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3
+// GFX12: [0x05,0x26,0x32,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x01,0x13]
+
+v_med3_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1
+// GFX12: [0xff,0xc7,0x32,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30]
+
+v_med3_i16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x78,0x50,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
+
+v_med3_i16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x08,0x50,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
+
+v_med3_i16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x10,0x50,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
+
+v_med3_i16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3
+// GFX12: [0x05,0x20,0x50,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13]
+
+v_med3_i16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1
+// GFX12: [0xff,0x40,0x50,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+
+v_med3_u16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x78,0x51,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
+
+v_med3_u16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x08,0x51,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
+
+v_med3_u16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x10,0x51,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
+
+v_med3_u16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3
+// GFX12: [0x05,0x20,0x51,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13]
+
+v_med3_u16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1
+// GFX12: [0xff,0x40,0x51,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+
+v_min3_num_f16_e64_dpp v5, -v1, v2, |exec_lo| op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x7c,0x2b,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+
+v_min3_num_f16_e64_dpp v5, -|v1|, -|v2|, null op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x0b,0x2b,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+
+v_min3_num_f16_e64_dpp v5, -|v1|, v2, -|-1| op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x15,0x2b,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01]
+
+v_min3_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3
+// GFX12: [0x05,0x26,0x2b,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x01,0x13]
+
+v_min3_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1
+// GFX12: [0xff,0xc7,0x2b,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30]
+
+v_min3_i16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x78,0x4a,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
+
+v_min3_i16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x08,0x4a,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
+
+v_min3_i16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x10,0x4a,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
+
+v_min3_i16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3
+// GFX12: [0x05,0x20,0x4a,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13]
+
+v_min3_i16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1
+// GFX12: [0xff,0x40,0x4a,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+
+v_min3_u16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x78,0x4b,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
+
+v_min3_u16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x08,0x4b,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
+
+v_min3_u16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x10,0x4b,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
+
+v_min3_u16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3
+// GFX12: [0x05,0x20,0x4b,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13]
+
+v_min3_u16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1
+// GFX12: [0xff,0x40,0x4b,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+
+v_pack_b32_f16_e64_dpp v5, -v1, |v2| op_sel:[1,0,0] row_xmask:0 row_mask:0x1 bank_mask:0x3
+// GFX12: [0x05,0x0a,0x11,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+
+v_pack_b32_f16_e64_dpp v255, -|v255|, -|v255| op_sel:[0,1,0] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1
+// GFX12: [0xff,0x13,0x11,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+
+v_sub_nc_i16_e64_dpp v5, v1, v2 op_sel:[1,1,1] row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x58,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_sub_nc_i16_e64_dpp v5, v1, v2 op_sel:[1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x08,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_sub_nc_i16_e64_dpp v5, v1, v2 op_sel:[0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3
+// GFX12: [0x05,0x10,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+
+v_sub_nc_i16_e64_dpp v255, v255, v255 op_sel:[0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1
+// GFX12: [0xff,0xc0,0x0e,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+
+v_sub_nc_u16_e64_dpp v5, v1, v2 op_sel:[1,1,1] row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x58,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_sub_nc_u16_e64_dpp v5, v1, v2 op_sel:[1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x08,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_sub_nc_u16_e64_dpp v5, v1, v2 op_sel:[0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3
+// GFX12: [0x05,0x10,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+
+v_sub_nc_u16_e64_dpp v255, v255, v255 op_sel:[0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1
+// GFX12: [0xff,0xc0,0x04,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+
+v_dot2_f16_f16_e64_dpp v0, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1
+// GFX12: [0x00,0x00,0x66,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x04,0x00]
+
+v_dot2_f16_f16_e64_dpp v0, v1, v2, v3 op_sel:[1,1,0,0] quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1
+// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid op_sel operand
+
+v_dot2_f16_f16_e64_dpp v0, s1, v2, v3 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1
+// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_dot2_f16_f16_e64_dpp v0, v1, s2, v3 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1
+// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_dot2_f16_f16_e64_dpp v0, v1, v2, v3 op_sel:[0,0,1,1] quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1
+// GFX12: [0x00,0x60,0x66,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x04,0x00]
+
+v_dot2_f16_f16_e64_dpp v0, |v1|, -v2, -|s3| op_sel:[0,0,1,1] quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1
+// GFX12: [0x00,0x65,0x66,0xd6,0xfa,0x04,0x0e,0xc0,0x01,0xe4,0x04,0x00]
+
+v_dot2_f16_f16_e64_dpp v5, v1, v2, 0.5 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x66,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x1b,0x00,0xff]
+
+v_dot2_bf16_bf16_e64_dpp v0, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1
+// GFX12: [0x00,0x00,0x67,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x04,0x00]
+
+v_dot2_bf16_bf16_e64_dpp v0, v1, v2, v3 op_sel:[1,1,0,0] quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1
+// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid op_sel operand
+
+v_dot2_bf16_bf16_e64_dpp v0, s1, v2, v3 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_dot2_bf16_bf16_e64_dpp v0, v1, s2, v3 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_dot2_bf16_bf16_e64_dpp v0, v1, v2, v3 op_sel:[0,0,1,1] quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1
+// GFX12: [0x00,0x60,0x67,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x04,0x00]
+
+v_dot2_bf16_bf16_e64_dpp v0, |v1|, -v2, -|s3| op_sel:[0,0,1,1] quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1
+// GFX12: [0x00,0x65,0x67,0xd6,0xfa,0x04,0x0e,0xc0,0x01,0xe4,0x04,0x00]
+
+v_dot2_bf16_bf16_e64_dpp v5, v1, v2, 0 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x67,0xd6,0xfa,0x04,0x02,0x02,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
new file mode 100644
index 000000000000..82807aca0e7b
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
@@ -0,0 +1,2968 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W32 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W64 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX12-ERR,W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX12-ERR,W64-ERR --implicit-check-not=error: %s
+
+v_add3_u32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x55,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_add3_u32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x55,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_add3_u32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x55,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_add3_u32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x55,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_add3_u32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x55,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_add3_u32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x55,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_add3_u32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x55,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_add3_u32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x55,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_add3_u32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x55,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_add3_u32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x55,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_add3_u32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x55,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_add3_u32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x55,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_add_co_u32_e64_dpp v5, s6, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x06,0x00,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x69,0x00,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x6a,0x00,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x6b,0x00,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x05,0x7b,0x00,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x05,0x0c,0x00,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x05,0x68,0x00,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x05,0x6a,0x00,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v5, ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x05,0x7a,0x00,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32_e64_dpp v255, null, v255, v255 clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0xfc,0x00,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_add_lshl_u32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x47,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_add_lshl_u32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x47,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_add_lshl_u32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x47,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_add_lshl_u32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x47,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_add_lshl_u32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x47,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_add_lshl_u32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x47,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_add_lshl_u32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x47,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_add_lshl_u32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x47,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_add_lshl_u32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x47,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_add_lshl_u32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x47,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_add_lshl_u32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x47,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_add_lshl_u32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x47,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_add_nc_i16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0d,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_add_nc_i16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x0d,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_add_nc_i16_e64_dpp v255, v255, v255 clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x0d,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_add_nc_i32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x26,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_add_nc_i32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x26,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_add_nc_i32_e64_dpp v255, v255, v255 clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x26,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_add_nc_u16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x03,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_add_nc_u16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x03,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_add_nc_u16_e64_dpp v255, v255, v255 clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x03,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x16,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x16,0xd6,0xea,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_alignbit_b32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x16,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_alignbyte_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x17,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_alignbyte_b32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x17,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_alignbyte_b32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x17,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_alignbyte_b32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x17,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_alignbyte_b32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x17,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_alignbyte_b32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x17,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_alignbyte_b32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x17,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_alignbyte_b32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x17,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_alignbyte_b32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x17,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_alignbyte_b32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x17,0xd6,0xea,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_alignbyte_b32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x17,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_and_b16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x62,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_and_b16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x62,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_and_b16_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x62,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_and_or_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x57,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_and_or_b32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x57,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_and_or_b32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x57,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_and_or_b32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x57,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_and_or_b32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x57,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_and_or_b32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x57,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_and_or_b32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x57,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_and_or_b32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x57,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_and_or_b32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x57,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_and_or_b32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x57,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_and_or_b32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x57,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_and_or_b32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x57,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_ashrrev_i16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x3a,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_ashrrev_i16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x3a,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_ashrrev_i16_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x3a,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_bcnt_u32_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1e,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_bcnt_u32_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x1e,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_bcnt_u32_b32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x1e,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_bfe_i32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x11,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_bfe_i32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x11,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_bfe_i32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x11,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_bfe_i32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x11,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_bfe_i32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x11,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_bfe_i32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x11,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_bfe_i32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x11,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_bfe_i32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x11,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_bfe_i32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x11,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_bfe_i32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x11,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_bfe_i32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x11,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_bfe_i32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x11,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_bfe_u32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x10,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_bfe_u32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x10,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_bfe_u32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x10,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_bfe_u32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x10,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_bfe_u32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x10,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_bfe_u32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x10,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_bfe_u32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x10,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_bfe_u32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x10,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_bfe_u32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x10,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_bfe_u32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x10,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_bfe_u32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x10,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_bfe_u32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x10,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_bfi_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x12,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_bfi_b32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x12,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_bfi_b32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x12,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_bfi_b32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x12,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_bfi_b32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x12,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_bfi_b32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x12,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_bfi_b32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x12,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_bfi_b32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x12,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_bfi_b32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x12,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_bfi_b32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x12,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_bfi_b32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x12,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_bfi_b32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x12,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_bfm_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1d,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_bfm_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x1d,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_bfm_b32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x1d,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cndmask_b16_e64_dpp v5, v1, v2, s3 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x5d,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x5d,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x5d,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, |v1|, -v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x01,0x5d,0xd6,0xe9,0x04,0xaa,0x41,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, -v1, |v2|, ttmp15 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x05,0x02,0x5d,0xd6,0xea,0x04,0xee,0x21,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x05,0x00,0x5d,0xd6,0xe9,0x04,0x1a,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, v1, v2, s[104:105] dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x05,0x00,0x5d,0xd6,0xe9,0x04,0xa2,0x01,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, |v1|, -v2, vcc dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x05,0x01,0x5d,0xd6,0xe9,0x04,0xaa,0x41,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v5, -v1, |v2|, ttmp[14:15] dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x05,0x02,0x5d,0xd6,0xea,0x04,0xea,0x21,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b16_e64_dpp v255, -|v255|, -|v255|, null dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x03,0x5d,0xd6,0xe9,0xfe,0xf3,0x61,0xff,0x00,0x00,0x00]
+
+v_cubeid_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0c,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_cubeid_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0c,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_cubeid_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0c,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_cubeid_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0c,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_cubeid_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0c,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_cubeid_f32_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x0c,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+
+v_cubeid_f32_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x02,0x0c,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+
+v_cubeid_f32_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x04,0x0c,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+
+v_cubeid_f32_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x03,0x0c,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+
+v_cubeid_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x05,0x0c,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05]
+
+v_cubeid_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x06,0x0c,0xd6,0xea,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05]
+
+v_cubeid_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x87,0x0c,0xd6,0xe9,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00]
+
+v_cubema_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0f,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_cubema_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0f,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_cubema_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0f,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_cubema_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0f,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_cubema_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0f,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_cubema_f32_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x0f,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+
+v_cubema_f32_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x02,0x0f,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+
+v_cubema_f32_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x04,0x0f,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+
+v_cubema_f32_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x03,0x0f,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+
+v_cubema_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x05,0x0f,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05]
+
+v_cubema_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x06,0x0f,0xd6,0xea,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05]
+
+v_cubema_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x87,0x0f,0xd6,0xe9,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00]
+
+v_cubesc_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0d,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_cubesc_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0d,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_cubesc_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0d,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_cubesc_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0d,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_cubesc_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0d,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_cubesc_f32_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x0d,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+
+v_cubesc_f32_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x02,0x0d,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+
+v_cubesc_f32_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x04,0x0d,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+
+v_cubesc_f32_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x03,0x0d,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+
+v_cubesc_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x05,0x0d,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05]
+
+v_cubesc_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x06,0x0d,0xd6,0xea,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05]
+
+v_cubesc_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x87,0x0d,0xd6,0xe9,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00]
+
+v_cubetc_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0e,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_cubetc_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0e,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_cubetc_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0e,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_cubetc_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0e,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_cubetc_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0e,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_cubetc_f32_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x0e,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+
+v_cubetc_f32_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x02,0x0e,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+
+v_cubetc_f32_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x04,0x0e,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+
+v_cubetc_f32_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x03,0x0e,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+
+v_cubetc_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x05,0x0e,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05]
+
+v_cubetc_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x06,0x0e,0xd6,0xea,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05]
+
+v_cubetc_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x87,0x0e,0xd6,0xe9,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00]
+
+v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x06,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_i16_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x06,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_i16_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x02,0x06,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_i16_f32_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x03,0x06,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x24,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x24,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_i16_i32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x24,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x12,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x12,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x02,0x12,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x03,0x12,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x13,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x13,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x02,0x13,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x03,0x13,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x07,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_u16_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x07,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_u16_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x02,0x07,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_u16_f32_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x03,0x07,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x23,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x23,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_u16_u32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x23,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x26,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x26,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x26,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x26,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x26,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x26,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x26,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x26,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x26,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x26,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x26,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_u8_f32_e64_dpp v255, -|v255|, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x01,0x26,0xd6,0xe9,0xfe,0xf7,0x23,0xff,0x00,0x00,0x00]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x12,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x12,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x02,0x12,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x03,0x12,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x21,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_norm_i16_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x21,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_norm_i16_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x02,0x21,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_norm_i16_f32_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x03,0x21,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x13,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x13,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x02,0x13,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x03,0x13,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x22,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_norm_u16_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x22,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_norm_u16_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x02,0x22,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_norm_u16_f32_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x03,0x22,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_div_fixup_f16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x54,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_div_fixup_f16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x54,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_div_fixup_f16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x54,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_div_fixup_f16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x54,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_div_fixup_f16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x54,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_div_fixup_f16_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x54,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+
+v_div_fixup_f16_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x02,0x54,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+
+v_div_fixup_f16_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x04,0x54,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+
+v_div_fixup_f16_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x03,0x54,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+
+v_div_fixup_f16_e64_dpp v5, -|v1|, v2, -|-1| dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x05,0x54,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05]
+
+v_div_fixup_f16_e64_dpp v5, v1, -|v2|, -|0.5| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x06,0x54,0xd6,0xea,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05]
+
+v_div_fixup_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x87,0x54,0xd6,0xe9,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00]
+
+v_fma_f16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x48,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_fma_f16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x48,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_fma_f16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x48,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_fma_f16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x48,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_fma_f16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x48,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_fma_f16_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x48,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+
+v_fma_f16_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x02,0x48,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+
+v_fma_f16_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x04,0x48,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+
+v_fma_f16_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x03,0x48,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+
+v_fma_f16_e64_dpp v5, -|v1|, v2, -|-1| dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x05,0x48,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05]
+
+v_fma_f16_e64_dpp v5, v1, -|v2|, -|0.5| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x06,0x48,0xd6,0xea,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05]
+
+v_fma_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x87,0x48,0xd6,0xe9,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00]
+
+v_fma_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x13,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_fma_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x13,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_fma_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x13,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_fma_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x13,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_fma_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x13,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_fma_f32_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x13,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+
+v_fma_f32_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x02,0x13,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+
+v_fma_f32_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x04,0x13,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+
+v_fma_f32_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x03,0x13,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+
+v_fma_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x05,0x13,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05]
+
+v_fma_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x06,0x13,0xd6,0xea,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05]
+
+v_fma_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x87,0x13,0xd6,0xe9,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00]
+
+v_ldexp_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1c,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_ldexp_f32_e64_dpp v5, v1, v2 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1c,0xd7,0xe9,0x04,0x02,0x08,0x01,0x77,0x39,0x05]
+
+v_ldexp_f32_e64_dpp v5, v1, v2 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x1c,0xd7,0xea,0x04,0x02,0x10,0x01,0x77,0x39,0x05]
+
+v_ldexp_f32_e64_dpp v255, -|v255|, v255 clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0x1c,0xd7,0xe9,0xfe,0x03,0x38,0xff,0x00,0x00,0x00]
+
+v_lerp_u8_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x15,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_lerp_u8_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x15,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_lerp_u8_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x15,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_lerp_u8_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x15,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_lerp_u8_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x15,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_lerp_u8_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x15,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_lerp_u8_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x15,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_lerp_u8_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x15,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_lerp_u8_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x15,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_lerp_u8_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x15,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_lerp_u8_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x15,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_lerp_u8_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x15,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_lshl_add_u32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x46,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_lshl_add_u32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x46,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_lshl_add_u32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x46,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_lshl_add_u32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x46,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_lshl_add_u32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x46,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_lshl_add_u32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x46,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_lshl_add_u32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x46,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_lshl_add_u32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x46,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_lshl_add_u32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x46,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_lshl_add_u32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x46,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_lshl_add_u32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x46,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_lshl_add_u32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x46,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_lshl_or_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x56,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_lshl_or_b32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x56,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_lshl_or_b32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x56,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_lshl_or_b32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x56,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_lshl_or_b32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x56,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_lshl_or_b32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x56,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_lshl_or_b32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x56,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_lshl_or_b32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x56,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_lshl_or_b32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x56,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_lshl_or_b32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x56,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_lshl_or_b32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x56,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_lshl_or_b32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x56,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_lshlrev_b16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x38,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_lshlrev_b16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x38,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_lshlrev_b16_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x38,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_lshrrev_b16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x39,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_lshrrev_b16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x39,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_lshrrev_b16_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x39,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_mad_i16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x53,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_mad_i16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x53,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_mad_i16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x53,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_i16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x53,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_i16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x53,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_i16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x53,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_i16_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x53,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_i16_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x53,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_i16_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x53,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_i16_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x53,0xd6,0xea,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_mad_i16_e64_dpp v255, v255, v255, src_scc clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x53,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_mad_i32_i16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x5a,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_mad_i32_i16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x5a,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_mad_i32_i16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x5a,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_i32_i16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x5a,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_i32_i16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x5a,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_i32_i16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x5a,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_i32_i16_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x5a,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_i32_i16_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x5a,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_i32_i16_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x5a,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_i32_i16_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x5a,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_mad_i32_i16_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x5a,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_mad_i32_i16_e64_dpp v255, v255, v255, src_scc clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x5a,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_mad_i32_i24_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0a,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_mad_i32_i24_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0a,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_mad_i32_i24_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0a,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_i32_i24_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0a,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_i32_i24_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0a,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_i32_i24_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0a,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_i32_i24_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0a,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_i32_i24_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0a,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_i32_i24_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0a,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_i32_i24_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0a,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_mad_i32_i24_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x0a,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_mad_i32_i24_e64_dpp v255, v255, v255, src_scc clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x0a,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_mad_u16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x41,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_mad_u16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x41,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_mad_u16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x41,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_u16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x41,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_u16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x41,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_u16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x41,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_u16_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x41,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_u16_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x41,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_u16_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x41,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_u16_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x41,0xd6,0xea,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_mad_u16_e64_dpp v255, v255, v255, src_scc clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x41,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_mad_u32_u16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x59,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_mad_u32_u16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x59,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_mad_u32_u16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x59,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_u32_u16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x59,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_u32_u16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x59,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_u32_u16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x59,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_u32_u16_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x59,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_u32_u16_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x59,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_u32_u16_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x59,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_u32_u16_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x59,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_mad_u32_u16_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x59,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_mad_u32_u16_e64_dpp v255, v255, v255, src_scc clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x59,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_mad_u32_u24_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0b,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_mad_u32_u24_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0b,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_mad_u32_u24_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0b,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_u32_u24_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0b,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_u32_u24_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0b,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_u32_u24_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0b,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_u32_u24_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0b,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_u32_u24_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0b,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_u32_u24_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0b,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_u32_u24_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0b,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_mad_u32_u24_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x0b,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_mad_u32_u24_e64_dpp v255, v255, v255, src_scc clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x0b,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_max3_num_f16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x2c,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_max3_num_f16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x2c,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_max3_num_f16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x2c,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_num_f16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x2c,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_num_f16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x2c,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_num_f16_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x2c,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+
+v_max3_num_f16_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x02,0x2c,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+
+v_max3_num_f16_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x04,0x2c,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+
+v_max3_num_f16_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x03,0x2c,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+
+v_max3_num_f16_e64_dpp v5, -|v1|, v2, -|-1| dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x05,0x2c,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05]
+
+v_max3_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x06,0x2c,0xd6,0xea,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05]
+
+v_max3_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp dpp8:[0,0,0,0,0,0,0,0]
+// GFX12: [0xff,0x87,0x2c,0xd6,0xe9,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00]
+
+v_max3_num_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x2a,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_max3_num_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x2a,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_max3_num_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x2a,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_num_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x2a,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_num_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x2a,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_num_f32_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x2a,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+
+v_max3_num_f32_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x02,0x2a,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+
+v_max3_num_f32_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x04,0x2a,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+
+v_max3_num_f32_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x03,0x2a,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+
+v_max3_num_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x05,0x2a,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05]
+
+v_max3_num_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x06,0x2a,0xd6,0xea,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05]
+
+v_max3_num_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0]
+// GFX12: [0xff,0x87,0x2a,0xd6,0xe9,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00]
+
+v_max3_i16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4d,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_max3_i16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4d,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_max3_i16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4d,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_i16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4d,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_i16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4d,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_i16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4d,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_i16_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4d,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_i16_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4d,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_i16_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4d,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_i16_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x4d,0xd6,0xea,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_max3_i16_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x4d,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_max3_i32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1d,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_max3_i32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1d,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_max3_i32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1d,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_i32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1d,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_i32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1d,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_i32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1d,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_i32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1d,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_i32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1d,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_i32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1d,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_i32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1d,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_max3_i32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x1d,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_max3_i32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x1d,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_max3_u16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4e,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_max3_u16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4e,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_max3_u16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4e,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_u16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4e,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_u16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4e,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_u16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4e,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_u16_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4e,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_u16_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4e,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_u16_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4e,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_u16_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x4e,0xd6,0xea,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_max3_u16_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x4e,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_max3_u32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1e,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_max3_u32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1e,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_max3_u32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1e,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_u32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1e,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_u32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1e,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_u32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1e,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_u32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1e,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_u32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1e,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_u32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1e,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_u32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1e,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_max3_u32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x1e,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_max3_u32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x1e,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_max_i16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0a,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_max_i16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x0a,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_max_i16_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x0a,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_max_u16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x09,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_max_u16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x09,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_max_u16_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x09,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_maxmin_num_f16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x6b,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_maxmin_num_f16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x6b,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_maxmin_num_f16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x6b,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_maxmin_num_f16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x6b,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_maxmin_num_f16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x6b,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_maxmin_num_f16_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x6b,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+
+v_maxmin_num_f16_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x02,0x6b,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+
+v_maxmin_num_f16_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x04,0x6b,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+
+v_maxmin_num_f16_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x03,0x6b,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+
+v_maxmin_num_f16_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x05,0x6b,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05]
+
+v_maxmin_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x06,0x6b,0xd6,0xea,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05]
+
+v_maxmin_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0]
+// GFX12: [0xff,0x87,0x6b,0xd6,0xe9,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00]
+
+v_maxmin_num_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x69,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_maxmin_num_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x69,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_maxmin_num_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x69,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_maxmin_num_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x69,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_maxmin_num_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x69,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_maxmin_num_f32_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x69,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+
+v_maxmin_num_f32_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x02,0x69,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+
+v_maxmin_num_f32_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x04,0x69,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+
+v_maxmin_num_f32_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x03,0x69,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+
+v_maxmin_num_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x05,0x69,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05]
+
+v_maxmin_num_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x06,0x69,0xd6,0xea,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05]
+
+v_maxmin_num_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0]
+// GFX12: [0xff,0x87,0x69,0xd6,0xe9,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00]
+
+v_maxmin_i32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x64,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_maxmin_i32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x64,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_maxmin_i32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x64,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_maxmin_i32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x64,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_maxmin_i32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x64,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_maxmin_i32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x64,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_maxmin_i32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x64,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_maxmin_i32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x64,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_maxmin_i32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x64,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_maxmin_i32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x64,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_maxmin_i32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x64,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_maxmin_i32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x64,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_maxmin_u32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x62,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_maxmin_u32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x62,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_maxmin_u32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x62,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_maxmin_u32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x62,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_maxmin_u32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x62,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_maxmin_u32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x62,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_maxmin_u32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x62,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_maxmin_u32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x62,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_maxmin_u32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x62,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_maxmin_u32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x62,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_maxmin_u32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x62,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_maxmin_u32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x62,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x20,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x20,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_mbcnt_hi_u32_b32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x20,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1f,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x1f,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_mbcnt_lo_u32_b32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x1f,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_med3_num_f16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x32,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_med3_num_f16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x32,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_med3_num_f16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x32,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_num_f16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x32,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_num_f16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x32,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_num_f16_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x32,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+
+v_med3_num_f16_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x02,0x32,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+
+v_med3_num_f16_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x04,0x32,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+
+v_med3_num_f16_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x03,0x32,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+
+v_med3_num_f16_e64_dpp v5, -|v1|, v2, -|-1| dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x05,0x32,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05]
+
+v_med3_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x06,0x32,0xd6,0xea,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05]
+
+v_med3_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp dpp8:[0,0,0,0,0,0,0,0]
+// GFX12: [0xff,0x87,0x32,0xd6,0xe9,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00]
+
+v_med3_num_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x31,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_med3_num_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x31,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_med3_num_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x31,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_num_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x31,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_num_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x31,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_num_f32_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x31,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+
+v_med3_num_f32_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x02,0x31,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+
+v_med3_num_f32_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x04,0x31,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+
+v_med3_num_f32_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x03,0x31,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+
+v_med3_num_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x05,0x31,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05]
+
+v_med3_num_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x06,0x31,0xd6,0xea,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05]
+
+v_med3_num_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0]
+// GFX12: [0xff,0x87,0x31,0xd6,0xe9,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00]
+
+v_med3_i16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x50,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_med3_i16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x50,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_med3_i16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x50,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_i16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x50,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_i16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x50,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_i16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x50,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_i16_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x50,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_i16_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x50,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_i16_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x50,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_i16_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x50,0xd6,0xea,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_med3_i16_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x50,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_med3_i32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x20,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_med3_i32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x20,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_med3_i32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x20,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_i32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x20,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_i32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x20,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_i32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x20,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_i32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x20,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_i32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x20,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_i32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x20,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_i32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x20,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_med3_i32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x20,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_med3_i32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x20,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_med3_u16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x51,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_med3_u16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x51,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_med3_u16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x51,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_u16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x51,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_u16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x51,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_u16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x51,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_u16_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x51,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_u16_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x51,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_u16_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x51,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_u16_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x51,0xd6,0xea,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_med3_u16_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x51,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_med3_u32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x21,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_med3_u32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x21,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_med3_u32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x21,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_u32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x21,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_u32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x21,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_u32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x21,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_u32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x21,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_u32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x21,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_u32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x21,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_u32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x21,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_med3_u32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x21,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_med3_u32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x21,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_min3_num_f16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x2b,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_min3_num_f16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x2b,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_min3_num_f16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x2b,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_num_f16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x2b,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_num_f16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x2b,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_num_f16_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x2b,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+
+v_min3_num_f16_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x02,0x2b,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+
+v_min3_num_f16_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x04,0x2b,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+
+v_min3_num_f16_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x03,0x2b,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+
+v_min3_num_f16_e64_dpp v5, -|v1|, v2, -|-1| dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x05,0x2b,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05]
+
+v_min3_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x06,0x2b,0xd6,0xea,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05]
+
+v_min3_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp dpp8:[0,0,0,0,0,0,0,0]
+// GFX12: [0xff,0x87,0x2b,0xd6,0xe9,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00]
+
+v_min3_num_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x29,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_min3_num_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x29,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_min3_num_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x29,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_num_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x29,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_num_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x29,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_num_f32_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x29,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+
+v_min3_num_f32_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x02,0x29,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+
+v_min3_num_f32_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x04,0x29,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+
+v_min3_num_f32_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x03,0x29,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+
+v_min3_num_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x05,0x29,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05]
+
+v_min3_num_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x06,0x29,0xd6,0xea,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05]
+
+v_min3_num_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0]
+// GFX12: [0xff,0x87,0x29,0xd6,0xe9,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00]
+
+v_min3_i16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4a,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_min3_i16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4a,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_min3_i16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4a,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_i16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4a,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_i16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4a,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_i16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4a,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_i16_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4a,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_i16_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4a,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_i16_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4a,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_i16_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x4a,0xd6,0xea,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_min3_i16_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x4a,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_min3_i32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1a,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_min3_i32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1a,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_min3_i32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1a,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_i32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1a,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_i32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1a,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_i32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1a,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_i32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1a,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_i32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1a,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_i32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1a,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_i32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1a,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_min3_i32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x1a,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_min3_i32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x1a,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_min3_u16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4b,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_min3_u16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4b,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_min3_u16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4b,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_u16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4b,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_u16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4b,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_u16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4b,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_u16_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4b,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_u16_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4b,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_u16_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x4b,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_u16_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x4b,0xd6,0xea,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_min3_u16_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x4b,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_min3_u32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1b,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_min3_u32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1b,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_min3_u32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1b,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_u32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1b,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_u32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1b,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_u32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1b,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_u32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1b,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_u32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1b,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_u32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1b,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_u32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1b,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_min3_u32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x1b,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_min3_u32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x1b,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_min_i16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0c,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_min_i16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x0c,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_min_i16_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x0c,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_min_u16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0b,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_min_u16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x0b,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_min_u16_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x0b,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_minmax_num_f16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x6a,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_minmax_num_f16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x6a,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_minmax_num_f16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x6a,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_minmax_num_f16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x6a,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_minmax_num_f16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x6a,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_minmax_num_f16_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x6a,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+
+v_minmax_num_f16_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x02,0x6a,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+
+v_minmax_num_f16_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x04,0x6a,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+
+v_minmax_num_f16_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x03,0x6a,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+
+v_minmax_num_f16_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x05,0x6a,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05]
+
+v_minmax_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x06,0x6a,0xd6,0xea,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05]
+
+v_minmax_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0]
+// GFX12: [0xff,0x87,0x6a,0xd6,0xe9,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00]
+
+v_minmax_num_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x68,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_minmax_num_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x68,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_minmax_num_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x68,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_minmax_num_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x68,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_minmax_num_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x68,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_minmax_num_f32_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x68,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+
+v_minmax_num_f32_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x02,0x68,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+
+v_minmax_num_f32_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x04,0x68,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+
+v_minmax_num_f32_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x03,0x68,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+
+v_minmax_num_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x05,0x68,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05]
+
+v_minmax_num_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x06,0x68,0xd6,0xea,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05]
+
+v_minmax_num_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0]
+// GFX12: [0xff,0x87,0x68,0xd6,0xe9,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00]
+
+v_minmax_i32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x65,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_minmax_i32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x65,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_minmax_i32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x65,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_minmax_i32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x65,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_minmax_i32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x65,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_minmax_i32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x65,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_minmax_i32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x65,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_minmax_i32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x65,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_minmax_i32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x65,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_minmax_i32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x65,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_minmax_i32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x65,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_minmax_i32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x65,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_minmax_u32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x63,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_minmax_u32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x63,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_minmax_u32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x63,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_minmax_u32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x63,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_minmax_u32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x63,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_minmax_u32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x63,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_minmax_u32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x63,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_minmax_u32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x63,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_minmax_u32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x63,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_minmax_u32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x63,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_minmax_u32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x63,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_minmax_u32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x63,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_msad_u8_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x39,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_msad_u8_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x39,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_msad_u8_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x39,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_msad_u8_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x39,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_msad_u8_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x39,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_msad_u8_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x39,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_msad_u8_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x39,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_msad_u8_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x39,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_msad_u8_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x39,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_msad_u8_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x39,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_msad_u8_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x39,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_msad_u8_e64_dpp v255, v255, v255, src_scc clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x39,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_mul_lo_u16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x05,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_mul_lo_u16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x05,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_mul_lo_u16_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x05,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_mullit_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x18,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_mullit_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x18,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_mullit_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x18,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_mullit_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x18,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_mullit_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x18,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_mullit_f32_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x18,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+
+v_mullit_f32_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x02,0x18,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+
+v_mullit_f32_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x04,0x18,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+
+v_mullit_f32_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x03,0x18,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+
+v_mullit_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x05,0x18,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05]
+
+v_mullit_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x06,0x18,0xd6,0xea,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05]
+
+v_mullit_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x87,0x18,0xd6,0xe9,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00]
+
+v_or3_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x58,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_or3_b32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x58,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_or3_b32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x58,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_or3_b32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x58,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_or3_b32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x58,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_or3_b32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x58,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_or3_b32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x58,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_or3_b32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x58,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_or3_b32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x58,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_or3_b32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x58,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_or3_b32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x58,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_or3_b32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x58,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_or_b16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x63,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_or_b16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x63,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_or_b16_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x63,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_pack_b32_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x11,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_pack_b32_f16_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x11,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_pack_b32_f16_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x02,0x11,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_pack_b32_f16_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x03,0x11,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_perm_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x44,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_perm_b32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x44,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_perm_b32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x44,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_perm_b32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x44,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_perm_b32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x44,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_perm_b32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x44,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_perm_b32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x44,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_perm_b32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x44,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_perm_b32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x44,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_perm_b32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x44,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_perm_b32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x44,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_perm_b32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x44,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_sad_hi_u8_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x23,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_sad_hi_u8_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x23,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_sad_hi_u8_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x23,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_sad_hi_u8_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x23,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_sad_hi_u8_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x23,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_sad_hi_u8_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x23,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_sad_hi_u8_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x23,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_sad_hi_u8_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x23,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_sad_hi_u8_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x23,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_sad_hi_u8_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x23,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_sad_hi_u8_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x23,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_sad_hi_u8_e64_dpp v255, v255, v255, src_scc clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x23,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_sad_u16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x24,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_sad_u16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x24,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_sad_u16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x24,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_sad_u16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x24,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_sad_u16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x24,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_sad_u16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x24,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_sad_u16_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x24,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_sad_u16_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x24,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_sad_u16_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x24,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_sad_u16_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x24,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_sad_u16_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x24,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_sad_u16_e64_dpp v255, v255, v255, src_scc clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x24,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_sad_u32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x25,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_sad_u32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x25,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_sad_u32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x25,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_sad_u32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x25,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_sad_u32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x25,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_sad_u32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x25,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_sad_u32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x25,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_sad_u32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x25,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_sad_u32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x25,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_sad_u32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x25,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_sad_u32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x25,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_sad_u32_e64_dpp v255, v255, v255, src_scc clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x25,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_sad_u8_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x22,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_sad_u8_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x22,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_sad_u8_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x22,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_sad_u8_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x22,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_sad_u8_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x22,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_sad_u8_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x22,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_sad_u8_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x22,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_sad_u8_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x22,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_sad_u8_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x22,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_sad_u8_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x22,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_sad_u8_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x22,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_sad_u8_e64_dpp v255, v255, v255, src_scc clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x22,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_sub_co_u32_e64_dpp v5, s6, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x06,0x01,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x69,0x01,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x6a,0x01,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x6b,0x01,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x05,0x7b,0x01,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x05,0x0c,0x01,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x05,0x68,0x01,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x05,0x6a,0x01,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v5, ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x05,0x7a,0x01,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32_e64_dpp v255, null, v255, v255 clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0xfc,0x01,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_sub_nc_i16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0e,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_sub_nc_i16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x0e,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_sub_nc_i16_e64_dpp v255, v255, v255 clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x0e,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_sub_nc_i32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x25,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_sub_nc_i32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x25,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_sub_nc_i32_e64_dpp v255, v255, v255 clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x25,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_sub_nc_u16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x04,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_sub_nc_u16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x04,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_sub_nc_u16_e64_dpp v255, v255, v255 clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x04,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_subrev_co_u32_e64_dpp v5, s6, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x06,0x02,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x69,0x02,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x6a,0x02,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x6b,0x02,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x05,0x7b,0x02,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x05,0x0c,0x02,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x05,0x68,0x02,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x05,0x6a,0x02,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v5, ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x05,0x7a,0x02,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32_e64_dpp v255, null, v255, v255 clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0xfc,0x02,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_xad_u32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x45,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_xad_u32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x45,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_xad_u32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x45,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_xad_u32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x45,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_xad_u32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x45,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_xad_u32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x45,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_xad_u32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x45,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_xad_u32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x45,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_xad_u32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x45,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_xad_u32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x45,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_xad_u32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x45,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_xad_u32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x45,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_xor3_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x40,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+
+v_xor3_b32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x40,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
+v_xor3_b32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x40,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+
+v_xor3_b32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x40,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+
+v_xor3_b32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x40,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+
+v_xor3_b32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x40,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+
+v_xor3_b32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x40,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_xor3_b32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x40,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_xor3_b32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x40,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_xor3_b32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x40,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_xor3_b32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x40,0xd6,0xea,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_xor3_b32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x40,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_xor_b16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x64,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_xor_b16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x64,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_xor_b16_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x64,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_add_nc_i16_e64_dpp v5, v1, v2 op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x58,0x0d,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_add_nc_i16_e64_dpp v5, v1, v2 op_sel:[1,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x08,0x0d,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_add_nc_i16_e64_dpp v5, v1, v2 op_sel:[0,1,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x10,0x0d,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_add_nc_i16_e64_dpp v255, v255, v255 op_sel:[0,0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1
+// GFX12: [0xff,0xc0,0x0d,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_add_nc_u16_e64_dpp v5, v1, v2 op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x58,0x03,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_add_nc_u16_e64_dpp v5, v1, v2 op_sel:[1,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x08,0x03,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_add_nc_u16_e64_dpp v5, v1, v2 op_sel:[0,1,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x10,0x03,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_add_nc_u16_e64_dpp v255, v255, v255 op_sel:[0,0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1
+// GFX12: [0xff,0xc0,0x03,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v5, -v1, |v2| op_sel:[1,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x0a,0x12,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_norm_i16_f16_e64_dpp v255, -|v255|, -|v255| op_sel:[0,1,0] dpp8:[0,0,0,0,0,0,0,0] fi:1
+// GFX12: [0xff,0x13,0x12,0xd7,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v5, -v1, |v2| op_sel:[1,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x0a,0x13,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_norm_u16_f16_e64_dpp v255, -|v255|, -|v255| op_sel:[0,1,0] dpp8:[0,0,0,0,0,0,0,0] fi:1
+// GFX12: [0xff,0x13,0x13,0xd7,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_div_fixup_f16_e64_dpp v5, -v1, v2, |exec_lo| op_sel:[1,1,1,1] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x7c,0x54,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+
+v_div_fixup_f16_e64_dpp v5, -|v1|, -|v2|, null op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x0b,0x54,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+
+v_div_fixup_f16_e64_dpp v5, -|v1|, v2, -|-1| op_sel:[0,1,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x15,0x54,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05]
+
+v_div_fixup_f16_e64_dpp v5, v1, -|v2|, -|0.5| op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x26,0x54,0xd6,0xe9,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05]
+
+v_div_fixup_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1
+// GFX12: [0xff,0xc7,0x54,0xd6,0xea,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00]
+
+v_fma_f16_e64_dpp v5, -v1, v2, |exec_lo| op_sel:[1,1,1,1] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x7c,0x48,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+
+v_fma_f16_e64_dpp v5, -|v1|, -|v2|, null op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x0b,0x48,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+
+v_fma_f16_e64_dpp v5, -|v1|, v2, -|-1| op_sel:[0,1,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x15,0x48,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05]
+
+v_fma_f16_e64_dpp v5, v1, -|v2|, -|0.5| op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x26,0x48,0xd6,0xe9,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05]
+
+v_fma_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1
+// GFX12: [0xff,0xc7,0x48,0xd6,0xea,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00]
+
+v_mad_i16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x78,0x53,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_i16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x08,0x53,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_i16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x10,0x53,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_i16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x20,0x53,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_mad_i16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1
+// GFX12: [0xff,0xc0,0x53,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_mad_i32_i16_e64_dpp v5, v1, v2, 0.5 op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x08,0x5a,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_mad_i32_i16_e64_dpp v255, v255, v255, src_scc op_sel:[0,1,0,0] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1
+// GFX12: [0xff,0x90,0x5a,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_mad_u16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x78,0x41,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_u16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x08,0x41,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_u16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x10,0x41,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_mad_u16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x20,0x41,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_mad_u16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1
+// GFX12: [0xff,0xc0,0x41,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_mad_u32_u16_e64_dpp v5, v1, v2, 0.5 op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x08,0x59,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_mad_u32_u16_e64_dpp v255, v255, v255, src_scc op_sel:[0,1,0,0] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1
+// GFX12: [0xff,0x90,0x59,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_max3_num_f16_e64_dpp v5, -v1, v2, |exec_lo| op_sel:[1,1,1,1] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x7c,0x2c,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+
+v_max3_num_f16_e64_dpp v5, -|v1|, -|v2|, null op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x0b,0x2c,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+
+v_max3_num_f16_e64_dpp v5, -|v1|, v2, -|-1| op_sel:[0,1,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x15,0x2c,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05]
+
+v_max3_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x26,0x2c,0xd6,0xe9,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05]
+
+v_max3_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1
+// GFX12: [0xff,0xc7,0x2c,0xd6,0xea,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00]
+
+v_max3_i16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x78,0x4d,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_i16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x08,0x4d,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_i16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x10,0x4d,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_i16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x20,0x4d,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_max3_i16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] dpp8:[0,0,0,0,0,0,0,0] fi:1
+// GFX12: [0xff,0x40,0x4d,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_max3_u16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x78,0x4e,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_u16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x08,0x4e,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_u16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x10,0x4e,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_max3_u16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x20,0x4e,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_max3_u16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] dpp8:[0,0,0,0,0,0,0,0] fi:1
+// GFX12: [0xff,0x40,0x4e,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_med3_num_f16_e64_dpp v5, -v1, v2, |exec_lo| op_sel:[1,1,1,1] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x7c,0x32,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+
+v_med3_num_f16_e64_dpp v5, -|v1|, -|v2|, null op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x0b,0x32,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+
+v_med3_num_f16_e64_dpp v5, -|v1|, v2, -|-1| op_sel:[0,1,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x15,0x32,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05]
+
+v_med3_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x26,0x32,0xd6,0xe9,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05]
+
+v_med3_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1
+// GFX12: [0xff,0xc7,0x32,0xd6,0xea,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00]
+
+v_med3_i16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x78,0x50,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_i16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x08,0x50,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_i16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x10,0x50,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_i16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x20,0x50,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_med3_i16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] dpp8:[0,0,0,0,0,0,0,0] fi:1
+// GFX12: [0xff,0x40,0x50,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_med3_u16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x78,0x51,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_u16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x08,0x51,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_u16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x10,0x51,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_med3_u16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x20,0x51,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_med3_u16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] dpp8:[0,0,0,0,0,0,0,0] fi:1
+// GFX12: [0xff,0x40,0x51,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_min3_num_f16_e64_dpp v5, -v1, v2, |exec_lo| op_sel:[1,1,1,1] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x7c,0x2b,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+
+v_min3_num_f16_e64_dpp v5, -|v1|, -|v2|, null op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x0b,0x2b,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+
+v_min3_num_f16_e64_dpp v5, -|v1|, v2, -|-1| op_sel:[0,1,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x15,0x2b,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05]
+
+v_min3_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x26,0x2b,0xd6,0xe9,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05]
+
+v_min3_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1
+// GFX12: [0xff,0xc7,0x2b,0xd6,0xea,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00]
+
+v_min3_i16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x78,0x4a,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_i16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x08,0x4a,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_i16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x10,0x4a,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_i16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x20,0x4a,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_min3_i16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] dpp8:[0,0,0,0,0,0,0,0] fi:1
+// GFX12: [0xff,0x40,0x4a,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_min3_u16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x78,0x4b,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_u16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x08,0x4b,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_u16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x10,0x4b,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+
+v_min3_u16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x20,0x4b,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+
+v_min3_u16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] dpp8:[0,0,0,0,0,0,0,0] fi:1
+// GFX12: [0xff,0x40,0x4b,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+
+v_pack_b32_f16_e64_dpp v5, -v1, |v2| op_sel:[1,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x0a,0x11,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_pack_b32_f16_e64_dpp v255, -|v255|, -|v255| op_sel:[0,1,0] dpp8:[0,0,0,0,0,0,0,0] fi:1
+// GFX12: [0xff,0x13,0x11,0xd7,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_sub_nc_i16_e64_dpp v5, v1, v2 op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x58,0x0e,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_sub_nc_i16_e64_dpp v5, v1, v2 op_sel:[1,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x08,0x0e,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_sub_nc_i16_e64_dpp v5, v1, v2 op_sel:[0,1,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x10,0x0e,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_sub_nc_i16_e64_dpp v255, v255, v255 op_sel:[0,0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1
+// GFX12: [0xff,0xc0,0x0e,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_sub_nc_u16_e64_dpp v5, v1, v2 op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x58,0x04,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_sub_nc_u16_e64_dpp v5, v1, v2 op_sel:[1,0,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x08,0x04,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_sub_nc_u16_e64_dpp v5, v1, v2 op_sel:[0,1,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x10,0x04,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_sub_nc_u16_e64_dpp v255, v255, v255 op_sel:[0,0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1
+// GFX12: [0xff,0xc0,0x04,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_dot2_f16_f16_e64_dpp v0, v1, v2, v3 dpp8:[0,1,2,3,4,4,4,4]
+// GFX12: [0x00,0x00,0x66,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x88,0x46,0x92]
+
+v_dot2_f16_f16_e64_dpp v0, v1, v2, v3 op_sel:[1,1,0,0] dpp8:[0,1,2,3,4,4,4,4]
+// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid op_sel operand
+
+v_dot2_f16_f16_e64_dpp v0, s1, v2, v3 dpp8:[0,1,2,3,4,4,4,4]
+// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_dot2_f16_f16_e64_dpp v0, v1, s2, v3 dpp8:[0,1,2,3,4,4,4,4]
+// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_dot2_f16_f16_e64_dpp v0, v1, v2, v3 op_sel:[0,0,1,1] dpp8:[0,1,2,3,4,4,4,4]
+// GFX12: [0x00,0x60,0x66,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x88,0x46,0x92]
+
+v_dot2_f16_f16_e64_dpp v0, |v1|, -v2, -|s3| op_sel:[0,0,1,1] dpp8:[0,1,2,3,4,4,4,4]
+// GFX12: [0x00,0x65,0x66,0xd6,0xe9,0x04,0x0e,0xc0,0x01,0x88,0x46,0x92]
+
+v_dot2_f16_f16_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x66,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+
+v_dot2_bf16_bf16_e64_dpp v0, v1, v2, v3 dpp8:[0,1,2,3,4,4,4,4]
+// GFX12: [0x00,0x00,0x67,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x88,0x46,0x92]
+
+v_dot2_bf16_bf16_e64_dpp v0, v1, v2, v3 op_sel:[1,1,0,0] dpp8:[0,1,2,3,4,4,4,4]
+// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid op_sel operand
+
+v_dot2_bf16_bf16_e64_dpp v0, s1, v2, v3 dpp8:[0,1,2,3,4,4,4,4]
+// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_dot2_bf16_bf16_e64_dpp v0, v1, s2, v3 dpp8:[0,1,2,3,4,4,4,4]
+// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_dot2_bf16_bf16_e64_dpp v0, v1, v2, v3 op_sel:[0,0,1,1] dpp8:[0,1,2,3,4,4,4,4]
+// GFX12: [0x00,0x60,0x67,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x88,0x46,0x92]
+
+v_dot2_bf16_bf16_e64_dpp v0, |v1|, -v2, -|s3| op_sel:[0,0,1,1] dpp8:[0,1,2,3,4,4,4,4]
+// GFX12: [0x00,0x65,0x67,0xd6,0xe9,0x04,0x0e,0xc0,0x01,0x88,0x46,0x92]
+
+v_dot2_bf16_bf16_e64_dpp v5, v1, v2, 0 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x67,0xd6,0xe9,0x04,0x02,0x02,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s
new file mode 100644
index 000000000000..bd1ed4042fda
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s
@@ -0,0 +1,8 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX12 --strict-whitespace --implicit-check-not=error %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX12 --strict-whitespace --implicit-check-not=error %s
+
+v_permlane16_b32 v5, v1, s2, s3 op_sel:[0, 0, 0, 1]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid op_sel operand
+
+v_permlanex16_b32 v5, v1, s2, s3 op_sel:[0, 0, 1, 0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid op_sel operand
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1.s
new file mode 100644
index 000000000000..e35bb6329067
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1.s
@@ -0,0 +1,3508 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX12 %s
+
+v_bfrev_b32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xb8,0xd5,0x01,0x01,0x00,0x00]
+
+v_bfrev_b32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xb8,0xd5,0xff,0x01,0x00,0x00]
+
+v_bfrev_b32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xb8,0xd5,0x01,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xb8,0xd5,0x69,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xb8,0xd5,0x6a,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xb8,0xd5,0x6b,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xb8,0xd5,0x7b,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xb8,0xd5,0x7d,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xb8,0xd5,0x7e,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xb8,0xd5,0x7f,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xb8,0xd5,0x7c,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xb8,0xd5,0xc1,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0xb8,0xd5,0xf0,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, src_scc
+// GFX12: encoding: [0x05,0x00,0xb8,0xd5,0xfd,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x00,0xb8,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_ceil_f16_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xdc,0xd5,0x01,0x01,0x00,0x00]
+
+v_ceil_f16_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xdc,0xd5,0xff,0x01,0x00,0x00]
+
+v_ceil_f16_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xdc,0xd5,0x01,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xdc,0xd5,0x69,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xdc,0xd5,0x6a,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xdc,0xd5,0x6b,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xdc,0xd5,0x7b,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xdc,0xd5,0x7d,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xdc,0xd5,0x7e,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xdc,0xd5,0x7f,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xdc,0xd5,0x7c,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xdc,0xd5,0xc1,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xdc,0xd5,0xf0,0x00,0x00,0x08]
+
+v_ceil_f16_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xdc,0xd5,0xfd,0x00,0x00,0x10]
+
+v_ceil_f16_e64 v255, -|0xfe0b| clamp div:2
+// GFX12: encoding: [0xff,0x81,0xdc,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00]
+
+v_ceil_f32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xa2,0xd5,0x01,0x01,0x00,0x00]
+
+v_ceil_f32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xa2,0xd5,0xff,0x01,0x00,0x00]
+
+v_ceil_f32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xa2,0xd5,0x01,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xa2,0xd5,0x69,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xa2,0xd5,0x6a,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xa2,0xd5,0x6b,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xa2,0xd5,0x7b,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xa2,0xd5,0x7d,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xa2,0xd5,0x7e,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xa2,0xd5,0x7f,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xa2,0xd5,0x7c,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xa2,0xd5,0xc1,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xa2,0xd5,0xf0,0x00,0x00,0x08]
+
+v_ceil_f32_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xa2,0xd5,0xfd,0x00,0x00,0x10]
+
+v_ceil_f32_e64 v255, -|0xaf123456| clamp div:2
+// GFX12: encoding: [0xff,0x81,0xa2,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+
+v_ceil_f64_e64 v[5:6], v[1:2]
+// GFX12: encoding: [0x05,0x00,0x98,0xd5,0x01,0x01,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], v[254:255]
+// GFX12: encoding: [0x05,0x00,0x98,0xd5,0xfe,0x01,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], s[2:3]
+// GFX12: encoding: [0x05,0x00,0x98,0xd5,0x02,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], s[104:105]
+// GFX12: encoding: [0x05,0x00,0x98,0xd5,0x68,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], vcc
+// GFX12: encoding: [0x05,0x00,0x98,0xd5,0x6a,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], ttmp[14:15]
+// GFX12: encoding: [0x05,0x00,0x98,0xd5,0x7a,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], exec
+// GFX12: encoding: [0x05,0x00,0x98,0xd5,0x7e,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], null
+// GFX12: encoding: [0x05,0x00,0x98,0xd5,0x7c,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], -1
+// GFX12: encoding: [0x05,0x00,0x98,0xd5,0xc1,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x98,0xd5,0xf0,0x00,0x00,0x08]
+
+v_ceil_f64_e64 v[5:6], -|src_scc| mul:4
+// GFX12: encoding: [0x05,0x01,0x98,0xd5,0xfd,0x00,0x00,0x30]
+
+v_ceil_f64_e64 v[254:255], 0xaf123456 clamp div:2
+// GFX12: encoding: [0xfe,0x80,0x98,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+
+v_cls_i32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xbb,0xd5,0x01,0x01,0x00,0x00]
+
+v_cls_i32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xbb,0xd5,0xff,0x01,0x00,0x00]
+
+v_cls_i32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xbb,0xd5,0x01,0x00,0x00,0x00]
+
+v_cls_i32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xbb,0xd5,0x69,0x00,0x00,0x00]
+
+v_cls_i32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xbb,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cls_i32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xbb,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cls_i32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xbb,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cls_i32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xbb,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cls_i32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xbb,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cls_i32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xbb,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cls_i32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xbb,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cls_i32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xbb,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cls_i32_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0xbb,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cls_i32_e64 v5, src_scc
+// GFX12: encoding: [0x05,0x00,0xbb,0xd5,0xfd,0x00,0x00,0x00]
+
+v_cls_i32_e64 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x00,0xbb,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_clz_i32_u32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xb9,0xd5,0x01,0x01,0x00,0x00]
+
+v_clz_i32_u32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xb9,0xd5,0xff,0x01,0x00,0x00]
+
+v_clz_i32_u32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xb9,0xd5,0x01,0x00,0x00,0x00]
+
+v_clz_i32_u32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xb9,0xd5,0x69,0x00,0x00,0x00]
+
+v_clz_i32_u32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xb9,0xd5,0x6a,0x00,0x00,0x00]
+
+v_clz_i32_u32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xb9,0xd5,0x6b,0x00,0x00,0x00]
+
+v_clz_i32_u32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xb9,0xd5,0x7b,0x00,0x00,0x00]
+
+v_clz_i32_u32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xb9,0xd5,0x7d,0x00,0x00,0x00]
+
+v_clz_i32_u32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xb9,0xd5,0x7e,0x00,0x00,0x00]
+
+v_clz_i32_u32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xb9,0xd5,0x7f,0x00,0x00,0x00]
+
+v_clz_i32_u32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xb9,0xd5,0x7c,0x00,0x00,0x00]
+
+v_clz_i32_u32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xb9,0xd5,0xc1,0x00,0x00,0x00]
+
+v_clz_i32_u32_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0xb9,0xd5,0xf0,0x00,0x00,0x00]
+
+v_clz_i32_u32_e64 v5, src_scc
+// GFX12: encoding: [0x05,0x00,0xb9,0xd5,0xfd,0x00,0x00,0x00]
+
+v_clz_i32_u32_e64 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x00,0xb9,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cos_f16_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xe1,0xd5,0x01,0x01,0x00,0x00]
+
+v_cos_f16_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xe1,0xd5,0xff,0x01,0x00,0x00]
+
+v_cos_f16_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xe1,0xd5,0x01,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xe1,0xd5,0x69,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xe1,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xe1,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xe1,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xe1,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xe1,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xe1,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xe1,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xe1,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xe1,0xd5,0xf0,0x00,0x00,0x08]
+
+v_cos_f16_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xe1,0xd5,0xfd,0x00,0x00,0x10]
+
+v_cos_f16_e64 v255, -|0xfe0b| clamp div:2
+// GFX12: encoding: [0xff,0x81,0xe1,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00]
+
+v_cos_f32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xb6,0xd5,0x01,0x01,0x00,0x00]
+
+v_cos_f32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xb6,0xd5,0xff,0x01,0x00,0x00]
+
+v_cos_f32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xb6,0xd5,0x01,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xb6,0xd5,0x69,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xb6,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xb6,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xb6,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xb6,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xb6,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xb6,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xb6,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xb6,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xb6,0xd5,0xf0,0x00,0x00,0x08]
+
+v_cos_f32_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xb6,0xd5,0xfd,0x00,0x00,0x10]
+
+v_cos_f32_e64 v255, -|0xaf123456| clamp div:2
+// GFX12: encoding: [0xff,0x81,0xb6,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+
+v_ctz_i32_b32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xba,0xd5,0x01,0x01,0x00,0x00]
+
+v_ctz_i32_b32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xba,0xd5,0xff,0x01,0x00,0x00]
+
+v_ctz_i32_b32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xba,0xd5,0x01,0x00,0x00,0x00]
+
+v_ctz_i32_b32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xba,0xd5,0x69,0x00,0x00,0x00]
+
+v_ctz_i32_b32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xba,0xd5,0x6a,0x00,0x00,0x00]
+
+v_ctz_i32_b32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xba,0xd5,0x6b,0x00,0x00,0x00]
+
+v_ctz_i32_b32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xba,0xd5,0x7b,0x00,0x00,0x00]
+
+v_ctz_i32_b32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xba,0xd5,0x7d,0x00,0x00,0x00]
+
+v_ctz_i32_b32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xba,0xd5,0x7e,0x00,0x00,0x00]
+
+v_ctz_i32_b32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xba,0xd5,0x7f,0x00,0x00,0x00]
+
+v_ctz_i32_b32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xba,0xd5,0x7c,0x00,0x00,0x00]
+
+v_ctz_i32_b32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xba,0xd5,0xc1,0x00,0x00,0x00]
+
+v_ctz_i32_b32_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0xba,0xd5,0xf0,0x00,0x00,0x00]
+
+v_ctz_i32_b32_e64 v5, src_scc
+// GFX12: encoding: [0x05,0x00,0xba,0xd5,0xfd,0x00,0x00,0x00]
+
+v_ctz_i32_b32_e64 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x00,0xba,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cvt_f16_f32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0x8a,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0x8a,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0x8a,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0x8a,0xd5,0x69,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x8a,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x8a,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0x8a,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0x8a,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0x8a,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0x8a,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0x8a,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0x8a,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x8a,0xd5,0xf0,0x00,0x00,0x08]
+
+v_cvt_f16_f32_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0x8a,0xd5,0xfd,0x00,0x00,0x10]
+
+v_cvt_f16_f32_e64 v255, -|0xaf123456| clamp div:2
+// GFX12: encoding: [0xff,0x81,0x8a,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+
+v_cvt_f16_i16_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xd1,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xd1,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xd1,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xd1,0xd5,0x69,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xd1,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xd1,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xd1,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xd1,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xd1,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xd1,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xd1,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xd1,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xd1,0xd5,0xff,0x00,0x00,0x08,0x00,0x38,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xd1,0xd5,0xfd,0x00,0x00,0x10]
+
+v_cvt_f16_i16_e64 v255, 0xfe0b clamp div:2
+// GFX12: encoding: [0xff,0x80,0xd1,0xd5,0xff,0x00,0x00,0x18,0x0b,0xfe,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xd0,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xd0,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xd0,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xd0,0xd5,0x69,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xd0,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xd0,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xd0,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xd0,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xd0,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xd0,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xd0,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xd0,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xd0,0xd5,0xff,0x00,0x00,0x08,0x00,0x38,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xd0,0xd5,0xfd,0x00,0x00,0x10]
+
+v_cvt_f16_u16_e64 v255, 0xfe0b clamp div:2
+// GFX12: encoding: [0xff,0x80,0xd0,0xd5,0xff,0x00,0x00,0x18,0x0b,0xfe,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0x8b,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0x8b,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0x8b,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0x8b,0xd5,0x69,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x8b,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x8b,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0x8b,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0x8b,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0x8b,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0x8b,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0x8b,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0x8b,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x8b,0xd5,0xf0,0x00,0x00,0x08]
+
+v_cvt_f32_f16_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0x8b,0xd5,0xfd,0x00,0x00,0x10]
+
+v_cvt_f32_f16_e64 v255, -|0xfe0b| clamp div:2
+// GFX12: encoding: [0xff,0x81,0x8b,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, v[1:2]
+// GFX12: encoding: [0x05,0x00,0x8f,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, v[254:255]
+// GFX12: encoding: [0x05,0x00,0x8f,0xd5,0xfe,0x01,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, s[2:3]
+// GFX12: encoding: [0x05,0x00,0x8f,0xd5,0x02,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, s[104:105]
+// GFX12: encoding: [0x05,0x00,0x8f,0xd5,0x68,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, vcc
+// GFX12: encoding: [0x05,0x00,0x8f,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, ttmp[14:15]
+// GFX12: encoding: [0x05,0x00,0x8f,0xd5,0x7a,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, exec
+// GFX12: encoding: [0x05,0x00,0x8f,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0x8f,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0x8f,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x8f,0xd5,0xf0,0x00,0x00,0x08]
+
+v_cvt_f32_f64_e64 v5, -|src_scc| mul:4
+// GFX12: encoding: [0x05,0x01,0x8f,0xd5,0xfd,0x00,0x00,0x30]
+
+v_cvt_f32_f64_e64 v255, 0xaf123456 clamp div:2
+// GFX12: encoding: [0xff,0x80,0x8f,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_i32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0x85,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0x85,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0x85,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0x85,0xd5,0x69,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x85,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x85,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0x85,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0x85,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0x85,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0x85,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0x85,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0x85,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x85,0xd5,0xf0,0x00,0x00,0x08]
+
+v_cvt_f32_i32_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0x85,0xd5,0xfd,0x00,0x00,0x10]
+
+v_cvt_f32_i32_e64 v255, 0xaf123456 clamp div:2
+// GFX12: encoding: [0xff,0x80,0x85,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_u32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0x86,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0x86,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0x86,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0x86,0xd5,0x69,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x86,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x86,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0x86,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0x86,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0x86,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0x86,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0x86,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0x86,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x86,0xd5,0xf0,0x00,0x00,0x08]
+
+v_cvt_f32_u32_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0x86,0xd5,0xfd,0x00,0x00,0x10]
+
+v_cvt_f32_u32_e64 v255, 0xaf123456 clamp div:2
+// GFX12: encoding: [0xff,0x80,0x86,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_ubyte0_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0x91,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0x91,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0x91,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0x91,0xd5,0x69,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x91,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x91,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0x91,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0x91,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0x91,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0x91,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0x91,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0x91,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x91,0xd5,0xf0,0x00,0x00,0x08]
+
+v_cvt_f32_ubyte0_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0x91,0xd5,0xfd,0x00,0x00,0x10]
+
+v_cvt_f32_ubyte0_e64 v255, 0xaf123456 clamp div:2
+// GFX12: encoding: [0xff,0x80,0x91,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_ubyte1_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0x92,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0x92,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0x92,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0x92,0xd5,0x69,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x92,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x92,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0x92,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0x92,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0x92,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0x92,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0x92,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0x92,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x92,0xd5,0xf0,0x00,0x00,0x08]
+
+v_cvt_f32_ubyte1_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0x92,0xd5,0xfd,0x00,0x00,0x10]
+
+v_cvt_f32_ubyte1_e64 v255, 0xaf123456 clamp div:2
+// GFX12: encoding: [0xff,0x80,0x92,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_ubyte2_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0x93,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0x93,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0x93,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0x93,0xd5,0x69,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x93,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x93,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0x93,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0x93,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0x93,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0x93,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0x93,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0x93,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x93,0xd5,0xf0,0x00,0x00,0x08]
+
+v_cvt_f32_ubyte2_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0x93,0xd5,0xfd,0x00,0x00,0x10]
+
+v_cvt_f32_ubyte2_e64 v255, 0xaf123456 clamp div:2
+// GFX12: encoding: [0xff,0x80,0x93,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_ubyte3_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0x94,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0x94,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0x94,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0x94,0xd5,0x69,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x94,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x94,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0x94,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0x94,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0x94,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0x94,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0x94,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0x94,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x94,0xd5,0xf0,0x00,0x00,0x08]
+
+v_cvt_f32_ubyte3_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0x94,0xd5,0xfd,0x00,0x00,0x10]
+
+v_cvt_f32_ubyte3_e64 v255, 0xaf123456 clamp div:2
+// GFX12: encoding: [0xff,0x80,0x94,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+
+v_cvt_f64_f32_e64 v[5:6], v1
+// GFX12: encoding: [0x05,0x00,0x90,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], v255
+// GFX12: encoding: [0x05,0x00,0x90,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], s1
+// GFX12: encoding: [0x05,0x00,0x90,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], s105
+// GFX12: encoding: [0x05,0x00,0x90,0xd5,0x69,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], vcc_lo
+// GFX12: encoding: [0x05,0x00,0x90,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], vcc_hi
+// GFX12: encoding: [0x05,0x00,0x90,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], ttmp15
+// GFX12: encoding: [0x05,0x00,0x90,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], m0
+// GFX12: encoding: [0x05,0x00,0x90,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], exec_lo
+// GFX12: encoding: [0x05,0x00,0x90,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], exec_hi
+// GFX12: encoding: [0x05,0x00,0x90,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], null
+// GFX12: encoding: [0x05,0x00,0x90,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], -1
+// GFX12: encoding: [0x05,0x00,0x90,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x90,0xd5,0xf0,0x00,0x00,0x08]
+
+v_cvt_f64_f32_e64 v[5:6], src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0x90,0xd5,0xfd,0x00,0x00,0x10]
+
+v_cvt_f64_f32_e64 v[254:255], -|0xaf123456| clamp div:2
+// GFX12: encoding: [0xfe,0x81,0x90,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+
+v_cvt_f64_i32_e64 v[5:6], v1
+// GFX12: encoding: [0x05,0x00,0x84,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], v255
+// GFX12: encoding: [0x05,0x00,0x84,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], s1
+// GFX12: encoding: [0x05,0x00,0x84,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], s105
+// GFX12: encoding: [0x05,0x00,0x84,0xd5,0x69,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], vcc_lo
+// GFX12: encoding: [0x05,0x00,0x84,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], vcc_hi
+// GFX12: encoding: [0x05,0x00,0x84,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], ttmp15
+// GFX12: encoding: [0x05,0x00,0x84,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], m0
+// GFX12: encoding: [0x05,0x00,0x84,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], exec_lo
+// GFX12: encoding: [0x05,0x00,0x84,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], exec_hi
+// GFX12: encoding: [0x05,0x00,0x84,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], null
+// GFX12: encoding: [0x05,0x00,0x84,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], -1
+// GFX12: encoding: [0x05,0x00,0x84,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x84,0xd5,0xf0,0x00,0x00,0x08]
+
+v_cvt_f64_i32_e64 v[5:6], src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0x84,0xd5,0xfd,0x00,0x00,0x10]
+
+v_cvt_f64_i32_e64 v[254:255], 0xaf123456 clamp div:2
+// GFX12: encoding: [0xfe,0x80,0x84,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+
+v_cvt_f64_u32_e64 v[5:6], v1
+// GFX12: encoding: [0x05,0x00,0x96,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], v255
+// GFX12: encoding: [0x05,0x00,0x96,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], s1
+// GFX12: encoding: [0x05,0x00,0x96,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], s105
+// GFX12: encoding: [0x05,0x00,0x96,0xd5,0x69,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], vcc_lo
+// GFX12: encoding: [0x05,0x00,0x96,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], vcc_hi
+// GFX12: encoding: [0x05,0x00,0x96,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], ttmp15
+// GFX12: encoding: [0x05,0x00,0x96,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], m0
+// GFX12: encoding: [0x05,0x00,0x96,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], exec_lo
+// GFX12: encoding: [0x05,0x00,0x96,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], exec_hi
+// GFX12: encoding: [0x05,0x00,0x96,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], null
+// GFX12: encoding: [0x05,0x00,0x96,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], -1
+// GFX12: encoding: [0x05,0x00,0x96,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x96,0xd5,0xf0,0x00,0x00,0x08]
+
+v_cvt_f64_u32_e64 v[5:6], src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0x96,0xd5,0xfd,0x00,0x00,0x10]
+
+v_cvt_f64_u32_e64 v[254:255], 0xaf123456 clamp div:2
+// GFX12: encoding: [0xfe,0x80,0x96,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+
+v_cvt_floor_i32_f32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0x8d,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_floor_i32_f32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0x8d,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_floor_i32_f32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0x8d,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_floor_i32_f32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0x8d,0xd5,0x69,0x00,0x00,0x00]
+
+v_cvt_floor_i32_f32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x8d,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_floor_i32_f32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x8d,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_floor_i32_f32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0x8d,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cvt_floor_i32_f32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0x8d,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cvt_floor_i32_f32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0x8d,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_floor_i32_f32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0x8d,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_floor_i32_f32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0x8d,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_floor_i32_f32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0x8d,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_floor_i32_f32_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0x8d,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_floor_i32_f32_e64 v5, src_scc
+// GFX12: encoding: [0x05,0x00,0x8d,0xd5,0xfd,0x00,0x00,0x00]
+
+v_cvt_floor_i32_f32_e64 v255, -|0xaf123456|
+// GFX12: encoding: [0xff,0x01,0x8d,0xd5,0xff,0x00,0x00,0x20,0x56,0x34,0x12,0xaf]
+
+v_cvt_flr_i32_f32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0x8d,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0x8d,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0x8d,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0x8d,0xd5,0x69,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x8d,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x8d,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0x8d,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0x8d,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0x8d,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0x8d,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0x8d,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0x8d,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0x8d,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, src_scc
+// GFX12: encoding: [0x05,0x00,0x8d,0xd5,0xfd,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v255, -|0xaf123456|
+// GFX12: encoding: [0xff,0x01,0x8d,0xd5,0xff,0x00,0x00,0x20,0x56,0x34,0x12,0xaf]
+
+v_cvt_i16_f16_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xd3,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xd3,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xd3,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xd3,0xd5,0x69,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xd3,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xd3,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xd3,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xd3,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xd3,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xd3,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xd3,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xd3,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0xd3,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, src_scc
+// GFX12: encoding: [0x05,0x00,0xd3,0xd5,0xfd,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v255, -|0xfe0b| clamp
+// GFX12: encoding: [0xff,0x81,0xd3,0xd5,0xff,0x00,0x00,0x20,0x0b,0xfe,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0x88,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0x88,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0x88,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0x88,0xd5,0x69,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x88,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x88,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0x88,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0x88,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0x88,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0x88,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0x88,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0x88,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0x88,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, src_scc
+// GFX12: encoding: [0x05,0x00,0x88,0xd5,0xfd,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v255, -|0xaf123456| clamp
+// GFX12: encoding: [0xff,0x81,0x88,0xd5,0xff,0x00,0x00,0x20,0x56,0x34,0x12,0xaf]
+
+v_cvt_i32_f64_e64 v5, v[1:2]
+// GFX12: encoding: [0x05,0x00,0x83,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, v[254:255]
+// GFX12: encoding: [0x05,0x00,0x83,0xd5,0xfe,0x01,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, s[2:3]
+// GFX12: encoding: [0x05,0x00,0x83,0xd5,0x02,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, s[104:105]
+// GFX12: encoding: [0x05,0x00,0x83,0xd5,0x68,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, vcc
+// GFX12: encoding: [0x05,0x00,0x83,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, ttmp[14:15]
+// GFX12: encoding: [0x05,0x00,0x83,0xd5,0x7a,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, exec
+// GFX12: encoding: [0x05,0x00,0x83,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0x83,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0x83,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0x83,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, -|src_scc|
+// GFX12: encoding: [0x05,0x01,0x83,0xd5,0xfd,0x00,0x00,0x20]
+
+v_cvt_i32_f64_e64 v255, 0xaf123456 clamp
+// GFX12: encoding: [0xff,0x80,0x83,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cvt_i32_i16_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xea,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_i32_i16_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xea,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_i32_i16_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xea,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_i32_i16_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xea,0xd5,0x69,0x00,0x00,0x00]
+
+v_cvt_i32_i16_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xea,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_i32_i16_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xea,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_i32_i16_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xea,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cvt_i32_i16_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xea,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cvt_i32_i16_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xea,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_i32_i16_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xea,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_i32_i16_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xea,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_i32_i16_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xea,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_i32_i16_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0xea,0xd5,0xff,0x00,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_cvt_i32_i16_e64 v5, src_scc
+// GFX12: encoding: [0x05,0x00,0xea,0xd5,0xfd,0x00,0x00,0x00]
+
+v_cvt_i32_i16_e64 v255, 0xfe0b
+// GFX12: encoding: [0xff,0x00,0xea,0xd5,0xff,0x00,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cvt_nearest_i32_f32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0x8c,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_nearest_i32_f32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0x8c,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_nearest_i32_f32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0x8c,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_nearest_i32_f32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0x8c,0xd5,0x69,0x00,0x00,0x00]
+
+v_cvt_nearest_i32_f32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x8c,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_nearest_i32_f32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x8c,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_nearest_i32_f32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0x8c,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cvt_nearest_i32_f32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0x8c,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cvt_nearest_i32_f32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0x8c,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_nearest_i32_f32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0x8c,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_nearest_i32_f32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0x8c,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_nearest_i32_f32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0x8c,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_nearest_i32_f32_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0x8c,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_nearest_i32_f32_e64 v5, src_scc
+// GFX12: encoding: [0x05,0x00,0x8c,0xd5,0xfd,0x00,0x00,0x00]
+
+v_cvt_nearest_i32_f32_e64 v255, -|0xaf123456|
+// GFX12: encoding: [0xff,0x01,0x8c,0xd5,0xff,0x00,0x00,0x20,0x56,0x34,0x12,0xaf]
+
+v_cvt_norm_i16_f16_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xe3,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xe3,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xe3,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xe3,0xd5,0x69,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xe3,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xe3,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xe3,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xe3,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xe3,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xe3,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xe3,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xe3,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0xe3,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, src_scc
+// GFX12: encoding: [0x05,0x00,0xe3,0xd5,0xfd,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v255, -|0xfe0b|
+// GFX12: encoding: [0xff,0x01,0xe3,0xd5,0xff,0x00,0x00,0x20,0x0b,0xfe,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xe4,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xe4,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xe4,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xe4,0xd5,0x69,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xe4,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xe4,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xe4,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xe4,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xe4,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xe4,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xe4,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xe4,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0xe4,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, src_scc
+// GFX12: encoding: [0x05,0x00,0xe4,0xd5,0xfd,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v255, -|0xfe0b|
+// GFX12: encoding: [0xff,0x01,0xe4,0xd5,0xff,0x00,0x00,0x20,0x0b,0xfe,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0x8e,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0x8e,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0x8e,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0x8e,0xd5,0x69,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x8e,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x8e,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0x8e,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0x8e,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0x8e,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0x8e,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0x8e,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0x8e,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x8e,0xd5,0xf0,0x00,0x00,0x08]
+
+v_cvt_off_f32_i4_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0x8e,0xd5,0xfd,0x00,0x00,0x10]
+
+v_cvt_off_f32_i4_e64 v255, 0x4f clamp div:2
+// GFX12: encoding: [0xff,0x80,0x8e,0xd5,0xff,0x00,0x00,0x18,0x4f,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0x8c,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0x8c,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0x8c,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0x8c,0xd5,0x69,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x8c,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x8c,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0x8c,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0x8c,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0x8c,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0x8c,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0x8c,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0x8c,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0x8c,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, src_scc
+// GFX12: encoding: [0x05,0x00,0x8c,0xd5,0xfd,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v255, -|0xaf123456|
+// GFX12: encoding: [0xff,0x01,0x8c,0xd5,0xff,0x00,0x00,0x20,0x56,0x34,0x12,0xaf]
+
+v_cvt_u16_f16_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xd2,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xd2,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xd2,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xd2,0xd5,0x69,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xd2,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xd2,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xd2,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xd2,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xd2,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xd2,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xd2,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xd2,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0xd2,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, src_scc
+// GFX12: encoding: [0x05,0x00,0xd2,0xd5,0xfd,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v255, -|0xfe0b| clamp
+// GFX12: encoding: [0xff,0x81,0xd2,0xd5,0xff,0x00,0x00,0x20,0x0b,0xfe,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0x87,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0x87,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0x87,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0x87,0xd5,0x69,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x87,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x87,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0x87,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0x87,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0x87,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0x87,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0x87,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0x87,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0x87,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, src_scc
+// GFX12: encoding: [0x05,0x00,0x87,0xd5,0xfd,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v255, -|0xaf123456| clamp
+// GFX12: encoding: [0xff,0x81,0x87,0xd5,0xff,0x00,0x00,0x20,0x56,0x34,0x12,0xaf]
+
+v_cvt_u32_f64_e64 v5, v[1:2]
+// GFX12: encoding: [0x05,0x00,0x95,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, v[254:255]
+// GFX12: encoding: [0x05,0x00,0x95,0xd5,0xfe,0x01,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, s[2:3]
+// GFX12: encoding: [0x05,0x00,0x95,0xd5,0x02,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, s[104:105]
+// GFX12: encoding: [0x05,0x00,0x95,0xd5,0x68,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, vcc
+// GFX12: encoding: [0x05,0x00,0x95,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, ttmp[14:15]
+// GFX12: encoding: [0x05,0x00,0x95,0xd5,0x7a,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, exec
+// GFX12: encoding: [0x05,0x00,0x95,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0x95,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0x95,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0x95,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, -|src_scc|
+// GFX12: encoding: [0x05,0x01,0x95,0xd5,0xfd,0x00,0x00,0x20]
+
+v_cvt_u32_f64_e64 v255, 0xaf123456 clamp
+// GFX12: encoding: [0xff,0x80,0x95,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cvt_u32_u16_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xeb,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_u32_u16_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xeb,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_u32_u16_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xeb,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_u32_u16_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xeb,0xd5,0x69,0x00,0x00,0x00]
+
+v_cvt_u32_u16_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xeb,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_u32_u16_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xeb,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_u32_u16_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xeb,0xd5,0x7b,0x00,0x00,0x00]
+
+v_cvt_u32_u16_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xeb,0xd5,0x7d,0x00,0x00,0x00]
+
+v_cvt_u32_u16_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xeb,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_u32_u16_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xeb,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_u32_u16_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xeb,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_u32_u16_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xeb,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_u32_u16_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0xeb,0xd5,0xff,0x00,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_cvt_u32_u16_e64 v5, src_scc
+// GFX12: encoding: [0x05,0x00,0xeb,0xd5,0xfd,0x00,0x00,0x00]
+
+v_cvt_u32_u16_e64 v255, 0xfe0b
+// GFX12: encoding: [0xff,0x00,0xeb,0xd5,0xff,0x00,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_exp_f16_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xd8,0xd5,0x01,0x01,0x00,0x00]
+
+v_exp_f16_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xd8,0xd5,0xff,0x01,0x00,0x00]
+
+v_exp_f16_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xd8,0xd5,0x01,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xd8,0xd5,0x69,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xd8,0xd5,0x6a,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xd8,0xd5,0x6b,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xd8,0xd5,0x7b,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xd8,0xd5,0x7d,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xd8,0xd5,0x7e,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xd8,0xd5,0x7f,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xd8,0xd5,0x7c,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xd8,0xd5,0xc1,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xd8,0xd5,0xf0,0x00,0x00,0x08]
+
+v_exp_f16_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xd8,0xd5,0xfd,0x00,0x00,0x10]
+
+v_exp_f16_e64 v255, -|0xfe0b| clamp div:2
+// GFX12: encoding: [0xff,0x81,0xd8,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00]
+
+v_exp_f32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xa5,0xd5,0x01,0x01,0x00,0x00]
+
+v_exp_f32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xa5,0xd5,0xff,0x01,0x00,0x00]
+
+v_exp_f32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xa5,0xd5,0x01,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xa5,0xd5,0x69,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xa5,0xd5,0x6a,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xa5,0xd5,0x6b,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xa5,0xd5,0x7b,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xa5,0xd5,0x7d,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xa5,0xd5,0x7e,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xa5,0xd5,0x7f,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xa5,0xd5,0x7c,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xa5,0xd5,0xc1,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xa5,0xd5,0xf0,0x00,0x00,0x08]
+
+v_exp_f32_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xa5,0xd5,0xfd,0x00,0x00,0x10]
+
+v_exp_f32_e64 v255, -|0xaf123456| clamp div:2
+// GFX12: encoding: [0xff,0x81,0xa5,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+
+v_ffbh_i32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xbb,0xd5,0x01,0x01,0x00,0x00]
+
+v_ffbh_i32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xbb,0xd5,0xff,0x01,0x00,0x00]
+
+v_ffbh_i32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xbb,0xd5,0x01,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xbb,0xd5,0x69,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xbb,0xd5,0x6a,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xbb,0xd5,0x6b,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xbb,0xd5,0x7b,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xbb,0xd5,0x7d,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xbb,0xd5,0x7e,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xbb,0xd5,0x7f,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xbb,0xd5,0x7c,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xbb,0xd5,0xc1,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0xbb,0xd5,0xf0,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, src_scc
+// GFX12: encoding: [0x05,0x00,0xbb,0xd5,0xfd,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x00,0xbb,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_ffbh_u32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xb9,0xd5,0x01,0x01,0x00,0x00]
+
+v_ffbh_u32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xb9,0xd5,0xff,0x01,0x00,0x00]
+
+v_ffbh_u32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xb9,0xd5,0x01,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xb9,0xd5,0x69,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xb9,0xd5,0x6a,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xb9,0xd5,0x6b,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xb9,0xd5,0x7b,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xb9,0xd5,0x7d,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xb9,0xd5,0x7e,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xb9,0xd5,0x7f,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xb9,0xd5,0x7c,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xb9,0xd5,0xc1,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0xb9,0xd5,0xf0,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, src_scc
+// GFX12: encoding: [0x05,0x00,0xb9,0xd5,0xfd,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x00,0xb9,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_ffbl_b32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xba,0xd5,0x01,0x01,0x00,0x00]
+
+v_ffbl_b32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xba,0xd5,0xff,0x01,0x00,0x00]
+
+v_ffbl_b32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xba,0xd5,0x01,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xba,0xd5,0x69,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xba,0xd5,0x6a,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xba,0xd5,0x6b,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xba,0xd5,0x7b,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xba,0xd5,0x7d,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xba,0xd5,0x7e,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xba,0xd5,0x7f,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xba,0xd5,0x7c,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xba,0xd5,0xc1,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0xba,0xd5,0xf0,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, src_scc
+// GFX12: encoding: [0x05,0x00,0xba,0xd5,0xfd,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x00,0xba,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_floor_f16_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xdb,0xd5,0x01,0x01,0x00,0x00]
+
+v_floor_f16_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xdb,0xd5,0xff,0x01,0x00,0x00]
+
+v_floor_f16_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xdb,0xd5,0x01,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xdb,0xd5,0x69,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xdb,0xd5,0x6a,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xdb,0xd5,0x6b,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xdb,0xd5,0x7b,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xdb,0xd5,0x7d,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xdb,0xd5,0x7e,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xdb,0xd5,0x7f,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xdb,0xd5,0x7c,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xdb,0xd5,0xc1,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xdb,0xd5,0xf0,0x00,0x00,0x08]
+
+v_floor_f16_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xdb,0xd5,0xfd,0x00,0x00,0x10]
+
+v_floor_f16_e64 v255, -|0xfe0b| clamp div:2
+// GFX12: encoding: [0xff,0x81,0xdb,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00]
+
+v_floor_f32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xa4,0xd5,0x01,0x01,0x00,0x00]
+
+v_floor_f32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xa4,0xd5,0xff,0x01,0x00,0x00]
+
+v_floor_f32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xa4,0xd5,0x01,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xa4,0xd5,0x69,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xa4,0xd5,0x6a,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xa4,0xd5,0x6b,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xa4,0xd5,0x7b,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xa4,0xd5,0x7d,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xa4,0xd5,0x7e,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xa4,0xd5,0x7f,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xa4,0xd5,0x7c,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xa4,0xd5,0xc1,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xa4,0xd5,0xf0,0x00,0x00,0x08]
+
+v_floor_f32_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xa4,0xd5,0xfd,0x00,0x00,0x10]
+
+v_floor_f32_e64 v255, -|0xaf123456| clamp div:2
+// GFX12: encoding: [0xff,0x81,0xa4,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+
+v_floor_f64_e64 v[5:6], v[1:2]
+// GFX12: encoding: [0x05,0x00,0x9a,0xd5,0x01,0x01,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], v[254:255]
+// GFX12: encoding: [0x05,0x00,0x9a,0xd5,0xfe,0x01,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], s[2:3]
+// GFX12: encoding: [0x05,0x00,0x9a,0xd5,0x02,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], s[104:105]
+// GFX12: encoding: [0x05,0x00,0x9a,0xd5,0x68,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], vcc
+// GFX12: encoding: [0x05,0x00,0x9a,0xd5,0x6a,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], ttmp[14:15]
+// GFX12: encoding: [0x05,0x00,0x9a,0xd5,0x7a,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], exec
+// GFX12: encoding: [0x05,0x00,0x9a,0xd5,0x7e,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], null
+// GFX12: encoding: [0x05,0x00,0x9a,0xd5,0x7c,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], -1
+// GFX12: encoding: [0x05,0x00,0x9a,0xd5,0xc1,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x9a,0xd5,0xf0,0x00,0x00,0x08]
+
+v_floor_f64_e64 v[5:6], -|src_scc| mul:4
+// GFX12: encoding: [0x05,0x01,0x9a,0xd5,0xfd,0x00,0x00,0x30]
+
+v_floor_f64_e64 v[254:255], 0xaf123456 clamp div:2
+// GFX12: encoding: [0xfe,0x80,0x9a,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+
+v_fract_f16_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xdf,0xd5,0x01,0x01,0x00,0x00]
+
+v_fract_f16_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xdf,0xd5,0xff,0x01,0x00,0x00]
+
+v_fract_f16_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xdf,0xd5,0x01,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xdf,0xd5,0x69,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xdf,0xd5,0x6a,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xdf,0xd5,0x6b,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xdf,0xd5,0x7b,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xdf,0xd5,0x7d,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xdf,0xd5,0x7e,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xdf,0xd5,0x7f,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xdf,0xd5,0x7c,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xdf,0xd5,0xc1,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xdf,0xd5,0xf0,0x00,0x00,0x08]
+
+v_fract_f16_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xdf,0xd5,0xfd,0x00,0x00,0x10]
+
+v_fract_f16_e64 v255, -|0xfe0b| clamp div:2
+// GFX12: encoding: [0xff,0x81,0xdf,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00]
+
+v_fract_f32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xa0,0xd5,0x01,0x01,0x00,0x00]
+
+v_fract_f32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xa0,0xd5,0xff,0x01,0x00,0x00]
+
+v_fract_f32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xa0,0xd5,0x01,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xa0,0xd5,0x69,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xa0,0xd5,0x6a,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xa0,0xd5,0x6b,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xa0,0xd5,0x7b,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xa0,0xd5,0x7d,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xa0,0xd5,0x7e,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xa0,0xd5,0x7f,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xa0,0xd5,0x7c,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xa0,0xd5,0xc1,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xa0,0xd5,0xf0,0x00,0x00,0x08]
+
+v_fract_f32_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xa0,0xd5,0xfd,0x00,0x00,0x10]
+
+v_fract_f32_e64 v255, -|0xaf123456| clamp div:2
+// GFX12: encoding: [0xff,0x81,0xa0,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+
+v_fract_f64_e64 v[5:6], v[1:2]
+// GFX12: encoding: [0x05,0x00,0xbe,0xd5,0x01,0x01,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], v[254:255]
+// GFX12: encoding: [0x05,0x00,0xbe,0xd5,0xfe,0x01,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], s[2:3]
+// GFX12: encoding: [0x05,0x00,0xbe,0xd5,0x02,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], s[104:105]
+// GFX12: encoding: [0x05,0x00,0xbe,0xd5,0x68,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], vcc
+// GFX12: encoding: [0x05,0x00,0xbe,0xd5,0x6a,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], ttmp[14:15]
+// GFX12: encoding: [0x05,0x00,0xbe,0xd5,0x7a,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], exec
+// GFX12: encoding: [0x05,0x00,0xbe,0xd5,0x7e,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], null
+// GFX12: encoding: [0x05,0x00,0xbe,0xd5,0x7c,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], -1
+// GFX12: encoding: [0x05,0x00,0xbe,0xd5,0xc1,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xbe,0xd5,0xf0,0x00,0x00,0x08]
+
+v_fract_f64_e64 v[5:6], -|src_scc| mul:4
+// GFX12: encoding: [0x05,0x01,0xbe,0xd5,0xfd,0x00,0x00,0x30]
+
+v_fract_f64_e64 v[254:255], 0xaf123456 clamp div:2
+// GFX12: encoding: [0xfe,0x80,0xbe,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+
+v_frexp_exp_i16_f16_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xda,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xda,0xd5,0xff,0x01,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xda,0xd5,0x01,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xda,0xd5,0x69,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xda,0xd5,0x6a,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xda,0xd5,0x6b,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xda,0xd5,0x7b,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xda,0xd5,0x7d,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xda,0xd5,0x7e,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xda,0xd5,0x7f,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xda,0xd5,0x7c,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xda,0xd5,0xc1,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0xda,0xd5,0xf0,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, src_scc
+// GFX12: encoding: [0x05,0x00,0xda,0xd5,0xfd,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v255, -|0xfe0b|
+// GFX12: encoding: [0xff,0x01,0xda,0xd5,0xff,0x00,0x00,0x20,0x0b,0xfe,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xbf,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xbf,0xd5,0xff,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xbf,0xd5,0x01,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xbf,0xd5,0x69,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xbf,0xd5,0x6a,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xbf,0xd5,0x6b,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xbf,0xd5,0x7b,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xbf,0xd5,0x7d,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xbf,0xd5,0x7e,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xbf,0xd5,0x7f,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xbf,0xd5,0x7c,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xbf,0xd5,0xc1,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0xbf,0xd5,0xf0,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, src_scc
+// GFX12: encoding: [0x05,0x00,0xbf,0xd5,0xfd,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v255, -|0xaf123456|
+// GFX12: encoding: [0xff,0x01,0xbf,0xd5,0xff,0x00,0x00,0x20,0x56,0x34,0x12,0xaf]
+
+v_frexp_exp_i32_f64_e64 v5, v[1:2]
+// GFX12: encoding: [0x05,0x00,0xbc,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, v[254:255]
+// GFX12: encoding: [0x05,0x00,0xbc,0xd5,0xfe,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, s[2:3]
+// GFX12: encoding: [0x05,0x00,0xbc,0xd5,0x02,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, s[104:105]
+// GFX12: encoding: [0x05,0x00,0xbc,0xd5,0x68,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, vcc
+// GFX12: encoding: [0x05,0x00,0xbc,0xd5,0x6a,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, ttmp[14:15]
+// GFX12: encoding: [0x05,0x00,0xbc,0xd5,0x7a,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, exec
+// GFX12: encoding: [0x05,0x00,0xbc,0xd5,0x7e,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xbc,0xd5,0x7c,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xbc,0xd5,0xc1,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0xbc,0xd5,0xf0,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, -|src_scc|
+// GFX12: encoding: [0x05,0x01,0xbc,0xd5,0xfd,0x00,0x00,0x20]
+
+v_frexp_exp_i32_f64_e64 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x00,0xbc,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_frexp_mant_f16_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xd9,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xd9,0xd5,0xff,0x01,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xd9,0xd5,0x01,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xd9,0xd5,0x69,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xd9,0xd5,0x6a,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xd9,0xd5,0x6b,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xd9,0xd5,0x7b,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xd9,0xd5,0x7d,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xd9,0xd5,0x7e,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xd9,0xd5,0x7f,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xd9,0xd5,0x7c,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xd9,0xd5,0xc1,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xd9,0xd5,0xf0,0x00,0x00,0x08]
+
+v_frexp_mant_f16_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xd9,0xd5,0xfd,0x00,0x00,0x10]
+
+v_frexp_mant_f16_e64 v255, -|0xfe0b| clamp div:2
+// GFX12: encoding: [0xff,0x81,0xd9,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xc0,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xc0,0xd5,0xff,0x01,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xc0,0xd5,0x01,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xc0,0xd5,0x69,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xc0,0xd5,0x6a,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xc0,0xd5,0x6b,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xc0,0xd5,0x7b,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xc0,0xd5,0x7d,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xc0,0xd5,0x7e,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xc0,0xd5,0x7f,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xc0,0xd5,0x7c,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xc0,0xd5,0xc1,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xc0,0xd5,0xf0,0x00,0x00,0x08]
+
+v_frexp_mant_f32_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xc0,0xd5,0xfd,0x00,0x00,0x10]
+
+v_frexp_mant_f32_e64 v255, -|0xaf123456| clamp div:2
+// GFX12: encoding: [0xff,0x81,0xc0,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+
+v_frexp_mant_f64_e64 v[5:6], v[1:2]
+// GFX12: encoding: [0x05,0x00,0xbd,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], v[254:255]
+// GFX12: encoding: [0x05,0x00,0xbd,0xd5,0xfe,0x01,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], s[2:3]
+// GFX12: encoding: [0x05,0x00,0xbd,0xd5,0x02,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], s[104:105]
+// GFX12: encoding: [0x05,0x00,0xbd,0xd5,0x68,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], vcc
+// GFX12: encoding: [0x05,0x00,0xbd,0xd5,0x6a,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], ttmp[14:15]
+// GFX12: encoding: [0x05,0x00,0xbd,0xd5,0x7a,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], exec
+// GFX12: encoding: [0x05,0x00,0xbd,0xd5,0x7e,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], null
+// GFX12: encoding: [0x05,0x00,0xbd,0xd5,0x7c,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], -1
+// GFX12: encoding: [0x05,0x00,0xbd,0xd5,0xc1,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xbd,0xd5,0xf0,0x00,0x00,0x08]
+
+v_frexp_mant_f64_e64 v[5:6], -|src_scc| mul:4
+// GFX12: encoding: [0x05,0x01,0xbd,0xd5,0xfd,0x00,0x00,0x30]
+
+v_frexp_mant_f64_e64 v[254:255], 0xaf123456 clamp div:2
+// GFX12: encoding: [0xfe,0x80,0xbd,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+
+v_log_f16_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xd7,0xd5,0x01,0x01,0x00,0x00]
+
+v_log_f16_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xd7,0xd5,0xff,0x01,0x00,0x00]
+
+v_log_f16_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xd7,0xd5,0x01,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xd7,0xd5,0x69,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xd7,0xd5,0x6a,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xd7,0xd5,0x6b,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xd7,0xd5,0x7b,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xd7,0xd5,0x7d,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xd7,0xd5,0x7e,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xd7,0xd5,0x7f,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xd7,0xd5,0x7c,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xd7,0xd5,0xc1,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xd7,0xd5,0xf0,0x00,0x00,0x08]
+
+v_log_f16_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xd7,0xd5,0xfd,0x00,0x00,0x10]
+
+v_log_f16_e64 v255, -|0xfe0b| clamp div:2
+// GFX12: encoding: [0xff,0x81,0xd7,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00]
+
+v_log_f32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xa7,0xd5,0x01,0x01,0x00,0x00]
+
+v_log_f32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xa7,0xd5,0xff,0x01,0x00,0x00]
+
+v_log_f32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xa7,0xd5,0x01,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xa7,0xd5,0x69,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xa7,0xd5,0x6a,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xa7,0xd5,0x6b,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xa7,0xd5,0x7b,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xa7,0xd5,0x7d,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xa7,0xd5,0x7e,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xa7,0xd5,0x7f,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xa7,0xd5,0x7c,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xa7,0xd5,0xc1,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xa7,0xd5,0xf0,0x00,0x00,0x08]
+
+v_log_f32_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xa7,0xd5,0xfd,0x00,0x00,0x10]
+
+v_log_f32_e64 v255, -|0xaf123456| clamp div:2
+// GFX12: encoding: [0xff,0x81,0xa7,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+
+v_mov_b32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0x81,0xd5,0x01,0x01,0x00,0x00]
+
+v_mov_b32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0x81,0xd5,0xff,0x01,0x00,0x00]
+
+v_mov_b32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0x81,0xd5,0x01,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0x81,0xd5,0x69,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x81,0xd5,0x6a,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0x81,0xd5,0x6b,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0x81,0xd5,0x7b,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0x81,0xd5,0x7d,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0x81,0xd5,0x7e,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0x81,0xd5,0x7f,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0x81,0xd5,0x7c,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0x81,0xd5,0xc1,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0x81,0xd5,0xf0,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, src_scc
+// GFX12: encoding: [0x05,0x00,0x81,0xd5,0xfd,0x00,0x00,0x00]
+
+v_mov_b32_e64 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x00,0x81,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_movreld_b32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xc2,0xd5,0x01,0x01,0x00,0x00]
+
+v_movreld_b32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xc2,0xd5,0xff,0x01,0x00,0x00]
+
+v_movreld_b32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xc2,0xd5,0x01,0x00,0x00,0x00]
+
+v_movreld_b32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xc2,0xd5,0x69,0x00,0x00,0x00]
+
+v_movreld_b32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xc2,0xd5,0x6a,0x00,0x00,0x00]
+
+v_movreld_b32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xc2,0xd5,0x6b,0x00,0x00,0x00]
+
+v_movreld_b32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xc2,0xd5,0x7b,0x00,0x00,0x00]
+
+v_movreld_b32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xc2,0xd5,0x7d,0x00,0x00,0x00]
+
+v_movreld_b32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xc2,0xd5,0x7e,0x00,0x00,0x00]
+
+v_movreld_b32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xc2,0xd5,0x7f,0x00,0x00,0x00]
+
+v_movreld_b32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xc2,0xd5,0x7c,0x00,0x00,0x00]
+
+v_movreld_b32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xc2,0xd5,0xc1,0x00,0x00,0x00]
+
+v_movreld_b32_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0xc2,0xd5,0xf0,0x00,0x00,0x00]
+
+v_movreld_b32_e64 v5, src_scc
+// GFX12: encoding: [0x05,0x00,0xc2,0xd5,0xfd,0x00,0x00,0x00]
+
+v_movreld_b32_e64 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x00,0xc2,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_movrels_b32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xc3,0xd5,0x01,0x01,0x00,0x00]
+
+v_movrels_b32_e64 v255, v255
+// GFX12: encoding: [0xff,0x00,0xc3,0xd5,0xff,0x01,0x00,0x00]
+
+v_movrelsd_2_b32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xc8,0xd5,0x01,0x01,0x00,0x00]
+
+v_movrelsd_2_b32_e64 v255, v255
+// GFX12: encoding: [0xff,0x00,0xc8,0xd5,0xff,0x01,0x00,0x00]
+
+v_movrelsd_b32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xc4,0xd5,0x01,0x01,0x00,0x00]
+
+v_movrelsd_b32_e64 v255, v255
+// GFX12: encoding: [0xff,0x00,0xc4,0xd5,0xff,0x01,0x00,0x00]
+
+v_nop_e64
+// GFX12: encoding: [0x00,0x00,0x80,0xd5,0x00,0x00,0x00,0x00]
+
+v_not_b16_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xe9,0xd5,0x01,0x01,0x00,0x00]
+
+v_not_b16_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xe9,0xd5,0xff,0x01,0x00,0x00]
+
+v_not_b16_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xe9,0xd5,0x01,0x00,0x00,0x00]
+
+v_not_b16_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xe9,0xd5,0x69,0x00,0x00,0x00]
+
+v_not_b16_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xe9,0xd5,0x6a,0x00,0x00,0x00]
+
+v_not_b16_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xe9,0xd5,0x6b,0x00,0x00,0x00]
+
+v_not_b16_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xe9,0xd5,0x7b,0x00,0x00,0x00]
+
+v_not_b16_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xe9,0xd5,0x7d,0x00,0x00,0x00]
+
+v_not_b16_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xe9,0xd5,0x7e,0x00,0x00,0x00]
+
+v_not_b16_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xe9,0xd5,0x7f,0x00,0x00,0x00]
+
+v_not_b16_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xe9,0xd5,0x7c,0x00,0x00,0x00]
+
+v_not_b16_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xe9,0xd5,0xc1,0x00,0x00,0x00]
+
+v_not_b16_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0xe9,0xd5,0xff,0x00,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_not_b16_e64 v5, src_scc
+// GFX12: encoding: [0x05,0x00,0xe9,0xd5,0xfd,0x00,0x00,0x00]
+
+v_not_b16_e64 v255, 0xfe0b
+// GFX12: encoding: [0xff,0x00,0xe9,0xd5,0xff,0x00,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_not_b32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xb7,0xd5,0x01,0x01,0x00,0x00]
+
+v_not_b32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xb7,0xd5,0xff,0x01,0x00,0x00]
+
+v_not_b32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xb7,0xd5,0x01,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xb7,0xd5,0x69,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xb7,0xd5,0x6a,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xb7,0xd5,0x6b,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xb7,0xd5,0x7b,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xb7,0xd5,0x7d,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xb7,0xd5,0x7e,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xb7,0xd5,0x7f,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xb7,0xd5,0x7c,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xb7,0xd5,0xc1,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0xb7,0xd5,0xf0,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, src_scc
+// GFX12: encoding: [0x05,0x00,0xb7,0xd5,0xfd,0x00,0x00,0x00]
+
+v_not_b32_e64 v255, 0xaf123456
+// GFX12: encoding: [0xff,0x00,0xb7,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_pipeflush_e64
+// GFX12: encoding: [0x00,0x00,0x9b,0xd5,0x00,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xd4,0xd5,0x01,0x01,0x00,0x00]
+
+v_rcp_f16_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xd4,0xd5,0xff,0x01,0x00,0x00]
+
+v_rcp_f16_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xd4,0xd5,0x01,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xd4,0xd5,0x69,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xd4,0xd5,0x6a,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xd4,0xd5,0x6b,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xd4,0xd5,0x7b,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xd4,0xd5,0x7d,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xd4,0xd5,0x7e,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xd4,0xd5,0x7f,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xd4,0xd5,0x7c,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xd4,0xd5,0xc1,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xd4,0xd5,0xf0,0x00,0x00,0x08]
+
+v_rcp_f16_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xd4,0xd5,0xfd,0x00,0x00,0x10]
+
+v_rcp_f16_e64 v255, -|0xfe0b| clamp div:2
+// GFX12: encoding: [0xff,0x81,0xd4,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00]
+
+v_rcp_f32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xaa,0xd5,0x01,0x01,0x00,0x00]
+
+v_rcp_f32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xaa,0xd5,0xff,0x01,0x00,0x00]
+
+v_rcp_f32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xaa,0xd5,0x01,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xaa,0xd5,0x69,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xaa,0xd5,0x6a,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xaa,0xd5,0x6b,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xaa,0xd5,0x7b,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xaa,0xd5,0x7d,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xaa,0xd5,0x7e,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xaa,0xd5,0x7f,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xaa,0xd5,0x7c,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xaa,0xd5,0xc1,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xaa,0xd5,0xf0,0x00,0x00,0x08]
+
+v_rcp_f32_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xaa,0xd5,0xfd,0x00,0x00,0x10]
+
+v_rcp_f32_e64 v255, -|0xaf123456| clamp div:2
+// GFX12: encoding: [0xff,0x81,0xaa,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+
+v_rcp_f64_e64 v[5:6], v[1:2]
+// GFX12: encoding: [0x05,0x00,0xaf,0xd5,0x01,0x01,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], v[254:255]
+// GFX12: encoding: [0x05,0x00,0xaf,0xd5,0xfe,0x01,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], s[2:3]
+// GFX12: encoding: [0x05,0x00,0xaf,0xd5,0x02,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], s[104:105]
+// GFX12: encoding: [0x05,0x00,0xaf,0xd5,0x68,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], vcc
+// GFX12: encoding: [0x05,0x00,0xaf,0xd5,0x6a,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], ttmp[14:15]
+// GFX12: encoding: [0x05,0x00,0xaf,0xd5,0x7a,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], exec
+// GFX12: encoding: [0x05,0x00,0xaf,0xd5,0x7e,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], null
+// GFX12: encoding: [0x05,0x00,0xaf,0xd5,0x7c,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], -1
+// GFX12: encoding: [0x05,0x00,0xaf,0xd5,0xc1,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xaf,0xd5,0xf0,0x00,0x00,0x08]
+
+v_rcp_f64_e64 v[5:6], -|src_scc| mul:4
+// GFX12: encoding: [0x05,0x01,0xaf,0xd5,0xfd,0x00,0x00,0x30]
+
+v_rcp_f64_e64 v[254:255], 0xaf123456 clamp div:2
+// GFX12: encoding: [0xfe,0x80,0xaf,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+
+v_rcp_iflag_f32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xab,0xd5,0x01,0x01,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xab,0xd5,0xff,0x01,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xab,0xd5,0x01,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xab,0xd5,0x69,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xab,0xd5,0x6a,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xab,0xd5,0x6b,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xab,0xd5,0x7b,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xab,0xd5,0x7d,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xab,0xd5,0x7e,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xab,0xd5,0x7f,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xab,0xd5,0x7c,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xab,0xd5,0xc1,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xab,0xd5,0xf0,0x00,0x00,0x08]
+
+v_rcp_iflag_f32_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xab,0xd5,0xfd,0x00,0x00,0x10]
+
+v_rcp_iflag_f32_e64 v255, -|0xaf123456| clamp div:2
+// GFX12: encoding: [0xff,0x81,0xab,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+
+v_rndne_f16_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xde,0xd5,0x01,0x01,0x00,0x00]
+
+v_rndne_f16_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xde,0xd5,0xff,0x01,0x00,0x00]
+
+v_rndne_f16_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xde,0xd5,0x01,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xde,0xd5,0x69,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xde,0xd5,0x6a,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xde,0xd5,0x6b,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xde,0xd5,0x7b,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xde,0xd5,0x7d,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xde,0xd5,0x7e,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xde,0xd5,0x7f,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xde,0xd5,0x7c,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xde,0xd5,0xc1,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xde,0xd5,0xf0,0x00,0x00,0x08]
+
+v_rndne_f16_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xde,0xd5,0xfd,0x00,0x00,0x10]
+
+v_rndne_f16_e64 v255, -|0xfe0b| clamp div:2
+// GFX12: encoding: [0xff,0x81,0xde,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00]
+
+v_rndne_f32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xa3,0xd5,0x01,0x01,0x00,0x00]
+
+v_rndne_f32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xa3,0xd5,0xff,0x01,0x00,0x00]
+
+v_rndne_f32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xa3,0xd5,0x01,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xa3,0xd5,0x69,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xa3,0xd5,0x6a,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xa3,0xd5,0x6b,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xa3,0xd5,0x7b,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xa3,0xd5,0x7d,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xa3,0xd5,0x7e,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xa3,0xd5,0x7f,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xa3,0xd5,0x7c,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xa3,0xd5,0xc1,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xa3,0xd5,0xf0,0x00,0x00,0x08]
+
+v_rndne_f32_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xa3,0xd5,0xfd,0x00,0x00,0x10]
+
+v_rndne_f32_e64 v255, -|0xaf123456| clamp div:2
+// GFX12: encoding: [0xff,0x81,0xa3,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+
+v_rndne_f64_e64 v[5:6], v[1:2]
+// GFX12: encoding: [0x05,0x00,0x99,0xd5,0x01,0x01,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], v[254:255]
+// GFX12: encoding: [0x05,0x00,0x99,0xd5,0xfe,0x01,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], s[2:3]
+// GFX12: encoding: [0x05,0x00,0x99,0xd5,0x02,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], s[104:105]
+// GFX12: encoding: [0x05,0x00,0x99,0xd5,0x68,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], vcc
+// GFX12: encoding: [0x05,0x00,0x99,0xd5,0x6a,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], ttmp[14:15]
+// GFX12: encoding: [0x05,0x00,0x99,0xd5,0x7a,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], exec
+// GFX12: encoding: [0x05,0x00,0x99,0xd5,0x7e,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], null
+// GFX12: encoding: [0x05,0x00,0x99,0xd5,0x7c,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], -1
+// GFX12: encoding: [0x05,0x00,0x99,0xd5,0xc1,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x99,0xd5,0xf0,0x00,0x00,0x08]
+
+v_rndne_f64_e64 v[5:6], -|src_scc| mul:4
+// GFX12: encoding: [0x05,0x01,0x99,0xd5,0xfd,0x00,0x00,0x30]
+
+v_rndne_f64_e64 v[254:255], 0xaf123456 clamp div:2
+// GFX12: encoding: [0xfe,0x80,0x99,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+
+v_rsq_f16_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xd6,0xd5,0x01,0x01,0x00,0x00]
+
+v_rsq_f16_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xd6,0xd5,0xff,0x01,0x00,0x00]
+
+v_rsq_f16_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xd6,0xd5,0x01,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xd6,0xd5,0x69,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xd6,0xd5,0x6a,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xd6,0xd5,0x6b,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xd6,0xd5,0x7b,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xd6,0xd5,0x7d,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xd6,0xd5,0x7e,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xd6,0xd5,0x7f,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xd6,0xd5,0x7c,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xd6,0xd5,0xc1,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xd6,0xd5,0xf0,0x00,0x00,0x08]
+
+v_rsq_f16_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xd6,0xd5,0xfd,0x00,0x00,0x10]
+
+v_rsq_f16_e64 v255, -|0xfe0b| clamp div:2
+// GFX12: encoding: [0xff,0x81,0xd6,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00]
+
+v_rsq_f32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xae,0xd5,0x01,0x01,0x00,0x00]
+
+v_rsq_f32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xae,0xd5,0xff,0x01,0x00,0x00]
+
+v_rsq_f32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xae,0xd5,0x01,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xae,0xd5,0x69,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xae,0xd5,0x6a,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xae,0xd5,0x6b,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xae,0xd5,0x7b,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xae,0xd5,0x7d,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xae,0xd5,0x7e,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xae,0xd5,0x7f,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xae,0xd5,0x7c,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xae,0xd5,0xc1,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xae,0xd5,0xf0,0x00,0x00,0x08]
+
+v_rsq_f32_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xae,0xd5,0xfd,0x00,0x00,0x10]
+
+v_rsq_f32_e64 v255, -|0xaf123456| clamp div:2
+// GFX12: encoding: [0xff,0x81,0xae,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+
+v_rsq_f64_e64 v[5:6], v[1:2]
+// GFX12: encoding: [0x05,0x00,0xb1,0xd5,0x01,0x01,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], v[254:255]
+// GFX12: encoding: [0x05,0x00,0xb1,0xd5,0xfe,0x01,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], s[2:3]
+// GFX12: encoding: [0x05,0x00,0xb1,0xd5,0x02,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], s[104:105]
+// GFX12: encoding: [0x05,0x00,0xb1,0xd5,0x68,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], vcc
+// GFX12: encoding: [0x05,0x00,0xb1,0xd5,0x6a,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], ttmp[14:15]
+// GFX12: encoding: [0x05,0x00,0xb1,0xd5,0x7a,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], exec
+// GFX12: encoding: [0x05,0x00,0xb1,0xd5,0x7e,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], null
+// GFX12: encoding: [0x05,0x00,0xb1,0xd5,0x7c,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], -1
+// GFX12: encoding: [0x05,0x00,0xb1,0xd5,0xc1,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xb1,0xd5,0xf0,0x00,0x00,0x08]
+
+v_rsq_f64_e64 v[5:6], -|src_scc| mul:4
+// GFX12: encoding: [0x05,0x01,0xb1,0xd5,0xfd,0x00,0x00,0x30]
+
+v_rsq_f64_e64 v[254:255], 0xaf123456 clamp div:2
+// GFX12: encoding: [0xfe,0x80,0xb1,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+
+v_sat_pk_u8_i16_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xe2,0xd5,0x01,0x01,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xe2,0xd5,0xff,0x01,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xe2,0xd5,0x01,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xe2,0xd5,0x69,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xe2,0xd5,0x6a,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xe2,0xd5,0x6b,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xe2,0xd5,0x7b,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xe2,0xd5,0x7d,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xe2,0xd5,0x7e,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xe2,0xd5,0x7f,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xe2,0xd5,0x7c,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xe2,0xd5,0xc1,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, 0.5
+// GFX12: encoding: [0x05,0x00,0xe2,0xd5,0xf0,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, src_scc
+// GFX12: encoding: [0x05,0x00,0xe2,0xd5,0xfd,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v255, 0xfe0b
+// GFX12: encoding: [0xff,0x00,0xe2,0xd5,0xff,0x00,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_sin_f16_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xe0,0xd5,0x01,0x01,0x00,0x00]
+
+v_sin_f16_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xe0,0xd5,0xff,0x01,0x00,0x00]
+
+v_sin_f16_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xe0,0xd5,0x01,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xe0,0xd5,0x69,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xe0,0xd5,0x6a,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xe0,0xd5,0x6b,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xe0,0xd5,0x7b,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xe0,0xd5,0x7d,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xe0,0xd5,0x7e,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xe0,0xd5,0x7f,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xe0,0xd5,0x7c,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xe0,0xd5,0xc1,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xe0,0xd5,0xf0,0x00,0x00,0x08]
+
+v_sin_f16_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xe0,0xd5,0xfd,0x00,0x00,0x10]
+
+v_sin_f16_e64 v255, -|0xfe0b| clamp div:2
+// GFX12: encoding: [0xff,0x81,0xe0,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00]
+
+v_sin_f32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xb5,0xd5,0x01,0x01,0x00,0x00]
+
+v_sin_f32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xb5,0xd5,0xff,0x01,0x00,0x00]
+
+v_sin_f32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xb5,0xd5,0x01,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xb5,0xd5,0x69,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xb5,0xd5,0x6a,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xb5,0xd5,0x6b,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xb5,0xd5,0x7b,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xb5,0xd5,0x7d,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xb5,0xd5,0x7e,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xb5,0xd5,0x7f,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xb5,0xd5,0x7c,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xb5,0xd5,0xc1,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xb5,0xd5,0xf0,0x00,0x00,0x08]
+
+v_sin_f32_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xb5,0xd5,0xfd,0x00,0x00,0x10]
+
+v_sin_f32_e64 v255, -|0xaf123456| clamp div:2
+// GFX12: encoding: [0xff,0x81,0xb5,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+
+v_sqrt_f16_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xd5,0xd5,0x01,0x01,0x00,0x00]
+
+v_sqrt_f16_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xd5,0xd5,0xff,0x01,0x00,0x00]
+
+v_sqrt_f16_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xd5,0xd5,0x01,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xd5,0xd5,0x69,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xd5,0xd5,0x6a,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xd5,0xd5,0x6b,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xd5,0xd5,0x7b,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xd5,0xd5,0x7d,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xd5,0xd5,0x7e,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xd5,0xd5,0x7f,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xd5,0xd5,0x7c,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xd5,0xd5,0xc1,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xd5,0xd5,0xf0,0x00,0x00,0x08]
+
+v_sqrt_f16_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xd5,0xd5,0xfd,0x00,0x00,0x10]
+
+v_sqrt_f16_e64 v255, -|0xfe0b| clamp div:2
+// GFX12: encoding: [0xff,0x81,0xd5,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00]
+
+v_sqrt_f32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xb3,0xd5,0x01,0x01,0x00,0x00]
+
+v_sqrt_f32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xb3,0xd5,0xff,0x01,0x00,0x00]
+
+v_sqrt_f32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xb3,0xd5,0x01,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xb3,0xd5,0x69,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xb3,0xd5,0x6a,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xb3,0xd5,0x6b,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xb3,0xd5,0x7b,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xb3,0xd5,0x7d,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xb3,0xd5,0x7e,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xb3,0xd5,0x7f,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xb3,0xd5,0x7c,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xb3,0xd5,0xc1,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xb3,0xd5,0xf0,0x00,0x00,0x08]
+
+v_sqrt_f32_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xb3,0xd5,0xfd,0x00,0x00,0x10]
+
+v_sqrt_f32_e64 v255, -|0xaf123456| clamp div:2
+// GFX12: encoding: [0xff,0x81,0xb3,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+
+v_sqrt_f64_e64 v[5:6], v[1:2]
+// GFX12: encoding: [0x05,0x00,0xb4,0xd5,0x01,0x01,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], v[254:255]
+// GFX12: encoding: [0x05,0x00,0xb4,0xd5,0xfe,0x01,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], s[2:3]
+// GFX12: encoding: [0x05,0x00,0xb4,0xd5,0x02,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], s[104:105]
+// GFX12: encoding: [0x05,0x00,0xb4,0xd5,0x68,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], vcc
+// GFX12: encoding: [0x05,0x00,0xb4,0xd5,0x6a,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], ttmp[14:15]
+// GFX12: encoding: [0x05,0x00,0xb4,0xd5,0x7a,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], exec
+// GFX12: encoding: [0x05,0x00,0xb4,0xd5,0x7e,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], null
+// GFX12: encoding: [0x05,0x00,0xb4,0xd5,0x7c,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], -1
+// GFX12: encoding: [0x05,0x00,0xb4,0xd5,0xc1,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xb4,0xd5,0xf0,0x00,0x00,0x08]
+
+v_sqrt_f64_e64 v[5:6], -|src_scc| mul:4
+// GFX12: encoding: [0x05,0x01,0xb4,0xd5,0xfd,0x00,0x00,0x30]
+
+v_sqrt_f64_e64 v[254:255], 0xaf123456 clamp div:2
+// GFX12: encoding: [0xfe,0x80,0xb4,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+
+v_trunc_f16_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xdd,0xd5,0x01,0x01,0x00,0x00]
+
+v_trunc_f16_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xdd,0xd5,0xff,0x01,0x00,0x00]
+
+v_trunc_f16_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xdd,0xd5,0x01,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xdd,0xd5,0x69,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xdd,0xd5,0x6a,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xdd,0xd5,0x6b,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xdd,0xd5,0x7b,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xdd,0xd5,0x7d,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xdd,0xd5,0x7e,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xdd,0xd5,0x7f,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xdd,0xd5,0x7c,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xdd,0xd5,0xc1,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xdd,0xd5,0xf0,0x00,0x00,0x08]
+
+v_trunc_f16_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xdd,0xd5,0xfd,0x00,0x00,0x10]
+
+v_trunc_f16_e64 v255, -|0xfe0b| clamp div:2
+// GFX12: encoding: [0xff,0x81,0xdd,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00]
+
+v_trunc_f32_e64 v5, v1
+// GFX12: encoding: [0x05,0x00,0xa1,0xd5,0x01,0x01,0x00,0x00]
+
+v_trunc_f32_e64 v5, v255
+// GFX12: encoding: [0x05,0x00,0xa1,0xd5,0xff,0x01,0x00,0x00]
+
+v_trunc_f32_e64 v5, s1
+// GFX12: encoding: [0x05,0x00,0xa1,0xd5,0x01,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, s105
+// GFX12: encoding: [0x05,0x00,0xa1,0xd5,0x69,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, vcc_lo
+// GFX12: encoding: [0x05,0x00,0xa1,0xd5,0x6a,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, vcc_hi
+// GFX12: encoding: [0x05,0x00,0xa1,0xd5,0x6b,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, ttmp15
+// GFX12: encoding: [0x05,0x00,0xa1,0xd5,0x7b,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, m0
+// GFX12: encoding: [0x05,0x00,0xa1,0xd5,0x7d,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, exec_lo
+// GFX12: encoding: [0x05,0x00,0xa1,0xd5,0x7e,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, exec_hi
+// GFX12: encoding: [0x05,0x00,0xa1,0xd5,0x7f,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, null
+// GFX12: encoding: [0x05,0x00,0xa1,0xd5,0x7c,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, -1
+// GFX12: encoding: [0x05,0x00,0xa1,0xd5,0xc1,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0xa1,0xd5,0xf0,0x00,0x00,0x08]
+
+v_trunc_f32_e64 v5, src_scc mul:4
+// GFX12: encoding: [0x05,0x00,0xa1,0xd5,0xfd,0x00,0x00,0x10]
+
+v_trunc_f32_e64 v255, -|0xaf123456| clamp div:2
+// GFX12: encoding: [0xff,0x81,0xa1,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+
+v_trunc_f64_e64 v[5:6], v[1:2]
+// GFX12: encoding: [0x05,0x00,0x97,0xd5,0x01,0x01,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], v[254:255]
+// GFX12: encoding: [0x05,0x00,0x97,0xd5,0xfe,0x01,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], s[2:3]
+// GFX12: encoding: [0x05,0x00,0x97,0xd5,0x02,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], s[104:105]
+// GFX12: encoding: [0x05,0x00,0x97,0xd5,0x68,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], vcc
+// GFX12: encoding: [0x05,0x00,0x97,0xd5,0x6a,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], ttmp[14:15]
+// GFX12: encoding: [0x05,0x00,0x97,0xd5,0x7a,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], exec
+// GFX12: encoding: [0x05,0x00,0x97,0xd5,0x7e,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], null
+// GFX12: encoding: [0x05,0x00,0x97,0xd5,0x7c,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], -1
+// GFX12: encoding: [0x05,0x00,0x97,0xd5,0xc1,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], 0.5 mul:2
+// GFX12: encoding: [0x05,0x00,0x97,0xd5,0xf0,0x00,0x00,0x08]
+
+v_trunc_f64_e64 v[5:6], -|src_scc| mul:4
+// GFX12: encoding: [0x05,0x01,0x97,0xd5,0xfd,0x00,0x00,0x30]
+
+v_trunc_f64_e64 v[254:255], 0xaf123456 clamp div:2
+// GFX12: encoding: [0xfe,0x80,0x97,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp16.s
new file mode 100644
index 000000000000..6b915bd14683
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp16.s
@@ -0,0 +1,2689 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX12 %s
+
+v_bfrev_b32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_bfrev_b32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_bfrev_b32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_bfrev_b32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_bfrev_b32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_bfrev_b32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_bfrev_b32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_bfrev_b32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_bfrev_b32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_bfrev_b32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_bfrev_b32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_bfrev_b32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+
+v_bfrev_b32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x09,0x13]
+
+v_bfrev_b32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x05,0x30]
+
+v_ceil_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_ceil_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_ceil_f16_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_ceil_f16_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_ceil_f16_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_ceil_f16_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_ceil_f16_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_ceil_f16_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_ceil_f16_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_ceil_f16_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_ceil_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_ceil_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_ceil_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_ceil_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xdc,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+v_ceil_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_ceil_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_ceil_f32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_ceil_f32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_ceil_f32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_ceil_f32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_ceil_f32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_ceil_f32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_ceil_f32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_ceil_f32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_ceil_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_ceil_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_ceil_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_ceil_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xa2,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+v_cls_i32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_cls_i32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_cls_i32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_cls_i32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_cls_i32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_cls_i32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_cls_i32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_cls_i32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_cls_i32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_cls_i32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_cls_i32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_cls_i32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+
+v_cls_i32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x09,0x13]
+
+v_cls_i32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x05,0x30]
+
+v_clz_i32_u32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_clz_i32_u32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_clz_i32_u32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_clz_i32_u32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_clz_i32_u32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_clz_i32_u32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_clz_i32_u32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_clz_i32_u32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_clz_i32_u32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_clz_i32_u32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_clz_i32_u32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_clz_i32_u32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+
+v_clz_i32_u32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x09,0x13]
+
+v_clz_i32_u32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x05,0x30]
+
+v_cos_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_cos_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_cos_f16_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_cos_f16_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_cos_f16_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_cos_f16_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_cos_f16_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_cos_f16_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_cos_f16_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_cos_f16_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_cos_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_cos_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_cos_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_cos_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xe1,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+v_cos_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_cos_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_cos_f32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_cos_f32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_cos_f32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_cos_f32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_cos_f32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_cos_f32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_cos_f32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_cos_f32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_cos_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_cos_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_cos_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_cos_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xb6,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+v_ctz_i32_b32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_ctz_i32_b32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_ctz_i32_b32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_ctz_i32_b32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_ctz_i32_b32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_ctz_i32_b32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_ctz_i32_b32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_ctz_i32_b32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_ctz_i32_b32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_ctz_i32_b32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_ctz_i32_b32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_ctz_i32_b32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+
+v_ctz_i32_b32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x09,0x13]
+
+v_ctz_i32_b32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x05,0x30]
+
+v_cvt_f16_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_f16_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_f16_f32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_f16_f32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_f16_f32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_f16_f32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_f16_f32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_f16_f32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_f16_f32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_f16_f32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_f16_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_f16_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_cvt_f16_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_cvt_f16_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0x8a,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+v_cvt_f16_i16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_f16_i16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_f16_i16_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_f16_i16_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_f16_i16_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_f16_i16_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_f16_i16_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_f16_i16_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_f16_i16_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_f16_i16_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_f16_i16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_f16_i16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_cvt_f16_i16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_cvt_f16_i16_e64_dpp v255, v255 clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0xd1,0xd5,0xfa,0x00,0x00,0x18,0xff,0x6f,0x05,0x30]
+
+v_cvt_f16_u16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_f16_u16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_f16_u16_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_f16_u16_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_f16_u16_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_f16_u16_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_f16_u16_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_f16_u16_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_f16_u16_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_f16_u16_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_f16_u16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_f16_u16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_cvt_f16_u16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_cvt_f16_u16_e64_dpp v255, v255 clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0xd0,0xd5,0xfa,0x00,0x00,0x18,0xff,0x6f,0x05,0x30]
+
+v_cvt_f32_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_f32_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_f32_f16_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_f32_f16_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_f32_f16_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_f32_f16_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_f32_f16_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_f32_f16_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_f32_f16_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_f32_f16_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_f32_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_f32_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_cvt_f32_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_cvt_f32_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0x8b,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+v_cvt_f32_i32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_f32_i32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_f32_i32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_f32_i32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_f32_i32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_f32_i32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_f32_i32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_f32_i32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_f32_i32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_f32_i32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_f32_i32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_f32_i32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_cvt_f32_i32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_cvt_f32_i32_e64_dpp v255, v255 clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x85,0xd5,0xfa,0x00,0x00,0x18,0xff,0x6f,0x05,0x30]
+
+v_cvt_f32_u32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_f32_u32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_f32_u32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_f32_u32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_f32_u32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_f32_u32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_f32_u32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_f32_u32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_f32_u32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_f32_u32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_f32_u32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_f32_u32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_cvt_f32_u32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_cvt_f32_u32_e64_dpp v255, v255 clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x86,0xd5,0xfa,0x00,0x00,0x18,0xff,0x6f,0x05,0x30]
+
+v_cvt_f32_ubyte0_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_f32_ubyte0_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_f32_ubyte0_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_f32_ubyte0_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_f32_ubyte0_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_f32_ubyte0_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_f32_ubyte0_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_f32_ubyte0_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_f32_ubyte0_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_f32_ubyte0_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_f32_ubyte0_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_f32_ubyte0_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_cvt_f32_ubyte0_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_cvt_f32_ubyte0_e64_dpp v255, v255 clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x91,0xd5,0xfa,0x00,0x00,0x18,0xff,0x6f,0x05,0x30]
+
+v_cvt_f32_ubyte1_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_f32_ubyte1_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_f32_ubyte1_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_f32_ubyte1_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_f32_ubyte1_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_f32_ubyte1_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_f32_ubyte1_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_f32_ubyte1_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_f32_ubyte1_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_f32_ubyte1_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_f32_ubyte1_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_f32_ubyte1_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_cvt_f32_ubyte1_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_cvt_f32_ubyte1_e64_dpp v255, v255 clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x92,0xd5,0xfa,0x00,0x00,0x18,0xff,0x6f,0x05,0x30]
+
+v_cvt_f32_ubyte2_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_f32_ubyte2_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_f32_ubyte2_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_f32_ubyte2_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_f32_ubyte2_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_f32_ubyte2_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_f32_ubyte2_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_f32_ubyte2_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_f32_ubyte2_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_f32_ubyte2_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_f32_ubyte2_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_f32_ubyte2_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_cvt_f32_ubyte2_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_cvt_f32_ubyte2_e64_dpp v255, v255 clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x93,0xd5,0xfa,0x00,0x00,0x18,0xff,0x6f,0x05,0x30]
+
+v_cvt_f32_ubyte3_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_f32_ubyte3_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_f32_ubyte3_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_f32_ubyte3_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_f32_ubyte3_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_f32_ubyte3_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_f32_ubyte3_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_f32_ubyte3_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_f32_ubyte3_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_f32_ubyte3_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_f32_ubyte3_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_f32_ubyte3_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_cvt_f32_ubyte3_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_cvt_f32_ubyte3_e64_dpp v255, v255 clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x94,0xd5,0xfa,0x00,0x00,0x18,0xff,0x6f,0x05,0x30]
+
+v_cvt_floor_i32_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_floor_i32_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_floor_i32_f32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_floor_i32_f32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_floor_i32_f32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_floor_i32_f32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_floor_i32_f32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_floor_i32_f32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_floor_i32_f32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_floor_i32_f32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_floor_i32_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_floor_i32_f32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+
+v_cvt_floor_i32_f32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x09,0x13]
+
+v_cvt_floor_i32_f32_e64_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x01,0x8d,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x05,0x30]
+
+v_cvt_flr_i32_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_flr_i32_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_flr_i32_f32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_flr_i32_f32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_flr_i32_f32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_flr_i32_f32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_flr_i32_f32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_flr_i32_f32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_flr_i32_f32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_flr_i32_f32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_flr_i32_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_flr_i32_f32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+
+v_cvt_flr_i32_f32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x09,0x13]
+
+v_cvt_flr_i32_f32_e64_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x01,0x8d,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x05,0x30]
+
+v_cvt_i16_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_i16_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_i16_f16_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_i16_f16_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_i16_f16_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_i16_f16_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_i16_f16_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_i16_f16_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_i16_f16_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_i16_f16_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_i16_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_i16_f16_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+
+v_cvt_i16_f16_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x09,0x13]
+
+v_cvt_i16_f16_e64_dpp v255, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xd3,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x05,0x30]
+
+v_cvt_i32_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_i32_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_i32_f32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_i32_f32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_i32_f32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_i32_f32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_i32_f32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_i32_f32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_i32_f32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_i32_f32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_i32_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_i32_f32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+
+v_cvt_i32_f32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x09,0x13]
+
+v_cvt_i32_f32_e64_dpp v255, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0x88,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x05,0x30]
+
+v_cvt_i32_i16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_i32_i16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_i32_i16_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_i32_i16_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_i32_i16_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_i32_i16_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_i32_i16_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_i32_i16_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_i32_i16_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_i32_i16_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_i32_i16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_i32_i16_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+
+v_cvt_i32_i16_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x09,0x13]
+
+v_cvt_i32_i16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x05,0x30]
+
+v_cvt_nearest_i32_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_nearest_i32_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_nearest_i32_f32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_nearest_i32_f32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_nearest_i32_f32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_nearest_i32_f32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_nearest_i32_f32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_nearest_i32_f32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_nearest_i32_f32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_nearest_i32_f32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_nearest_i32_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_nearest_i32_f32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+
+v_cvt_nearest_i32_f32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x09,0x13]
+
+v_cvt_nearest_i32_f32_e64_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x01,0x8c,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x05,0x30]
+
+v_cvt_norm_i16_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_norm_i16_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_norm_i16_f16_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_norm_i16_f16_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_norm_i16_f16_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_norm_i16_f16_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_norm_i16_f16_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_norm_i16_f16_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_norm_i16_f16_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_norm_i16_f16_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_norm_i16_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_norm_i16_f16_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+
+v_cvt_norm_i16_f16_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x09,0x13]
+
+v_cvt_norm_i16_f16_e64_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x01,0xe3,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x05,0x30]
+
+v_cvt_norm_u16_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_norm_u16_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_norm_u16_f16_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_norm_u16_f16_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_norm_u16_f16_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_norm_u16_f16_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_norm_u16_f16_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_norm_u16_f16_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_norm_u16_f16_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_norm_u16_f16_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_norm_u16_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_norm_u16_f16_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+
+v_cvt_norm_u16_f16_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x09,0x13]
+
+v_cvt_norm_u16_f16_e64_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x01,0xe4,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x05,0x30]
+
+v_cvt_off_f32_i4_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_off_f32_i4_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_off_f32_i4_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_off_f32_i4_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_off_f32_i4_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_off_f32_i4_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_off_f32_i4_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_off_f32_i4_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_off_f32_i4_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_off_f32_i4_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_off_f32_i4_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_off_f32_i4_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_cvt_off_f32_i4_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_cvt_off_f32_i4_e64_dpp v255, v255 clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x8e,0xd5,0xfa,0x00,0x00,0x18,0xff,0x6f,0x05,0x30]
+
+v_cvt_rpi_i32_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_rpi_i32_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_rpi_i32_f32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_rpi_i32_f32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_rpi_i32_f32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_rpi_i32_f32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_rpi_i32_f32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_rpi_i32_f32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_rpi_i32_f32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_rpi_i32_f32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_rpi_i32_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_rpi_i32_f32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+
+v_cvt_rpi_i32_f32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x09,0x13]
+
+v_cvt_rpi_i32_f32_e64_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x01,0x8c,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x05,0x30]
+
+v_cvt_u16_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_u16_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_u16_f16_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_u16_f16_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_u16_f16_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_u16_f16_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_u16_f16_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_u16_f16_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_u16_f16_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_u16_f16_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_u16_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_u16_f16_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+
+v_cvt_u16_f16_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x09,0x13]
+
+v_cvt_u16_f16_e64_dpp v255, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xd2,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x05,0x30]
+
+v_cvt_u32_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_u32_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_u32_f32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_u32_f32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_u32_f32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_u32_f32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_u32_f32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_u32_f32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_u32_f32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_u32_f32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_u32_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_u32_f32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+
+v_cvt_u32_f32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x09,0x13]
+
+v_cvt_u32_f32_e64_dpp v255, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0x87,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x05,0x30]
+
+v_cvt_u32_u16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_u32_u16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_u32_u16_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_u32_u16_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_u32_u16_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_u32_u16_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_u32_u16_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_u32_u16_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_u32_u16_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_u32_u16_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_u32_u16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_u32_u16_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+
+v_cvt_u32_u16_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x09,0x13]
+
+v_cvt_u32_u16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x05,0x30]
+
+v_exp_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_exp_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_exp_f16_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_exp_f16_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_exp_f16_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_exp_f16_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_exp_f16_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_exp_f16_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_exp_f16_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_exp_f16_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_exp_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_exp_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_exp_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_exp_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xd8,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+v_exp_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_exp_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_exp_f32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_exp_f32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_exp_f32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_exp_f32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_exp_f32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_exp_f32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_exp_f32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_exp_f32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_exp_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_exp_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_exp_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_exp_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xa5,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+v_ffbh_i32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_ffbh_i32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_ffbh_i32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_ffbh_i32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_ffbh_i32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_ffbh_i32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_ffbh_i32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_ffbh_i32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_ffbh_i32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_ffbh_i32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_ffbh_i32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_ffbh_i32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+
+v_ffbh_i32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x09,0x13]
+
+v_ffbh_i32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x05,0x30]
+
+v_ffbh_u32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_ffbh_u32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_ffbh_u32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_ffbh_u32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_ffbh_u32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_ffbh_u32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_ffbh_u32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_ffbh_u32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_ffbh_u32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_ffbh_u32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_ffbh_u32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_ffbh_u32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+
+v_ffbh_u32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x09,0x13]
+
+v_ffbh_u32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x05,0x30]
+
+v_ffbl_b32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_ffbl_b32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_ffbl_b32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_ffbl_b32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_ffbl_b32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_ffbl_b32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_ffbl_b32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_ffbl_b32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_ffbl_b32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_ffbl_b32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_ffbl_b32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_ffbl_b32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+
+v_ffbl_b32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x09,0x13]
+
+v_ffbl_b32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x05,0x30]
+
+v_floor_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_floor_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_floor_f16_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_floor_f16_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_floor_f16_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_floor_f16_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_floor_f16_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_floor_f16_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_floor_f16_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_floor_f16_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_floor_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_floor_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_floor_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_floor_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xdb,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+v_floor_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_floor_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_floor_f32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_floor_f32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_floor_f32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_floor_f32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_floor_f32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_floor_f32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_floor_f32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_floor_f32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_floor_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_floor_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_floor_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_floor_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xa4,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+v_fract_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_fract_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_fract_f16_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_fract_f16_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_fract_f16_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_fract_f16_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_fract_f16_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_fract_f16_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_fract_f16_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_fract_f16_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_fract_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_fract_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_fract_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_fract_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xdf,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+v_fract_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_fract_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_fract_f32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_fract_f32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_fract_f32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_fract_f32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_fract_f32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_fract_f32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_fract_f32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_fract_f32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_fract_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_fract_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_fract_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_fract_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xa0,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+v_frexp_exp_i16_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_frexp_exp_i16_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_frexp_exp_i16_f16_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_frexp_exp_i16_f16_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_frexp_exp_i16_f16_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_frexp_exp_i16_f16_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_frexp_exp_i16_f16_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_frexp_exp_i16_f16_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_frexp_exp_i16_f16_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_frexp_exp_i16_f16_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_frexp_exp_i16_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_frexp_exp_i16_f16_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+
+v_frexp_exp_i16_f16_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x09,0x13]
+
+v_frexp_exp_i16_f16_e64_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x01,0xda,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x05,0x30]
+
+v_frexp_exp_i32_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_frexp_exp_i32_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_frexp_exp_i32_f32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_frexp_exp_i32_f32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_frexp_exp_i32_f32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_frexp_exp_i32_f32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_frexp_exp_i32_f32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_frexp_exp_i32_f32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_frexp_exp_i32_f32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_frexp_exp_i32_f32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_frexp_exp_i32_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_frexp_exp_i32_f32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+
+v_frexp_exp_i32_f32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x09,0x13]
+
+v_frexp_exp_i32_f32_e64_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x01,0xbf,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x05,0x30]
+
+v_frexp_mant_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_frexp_mant_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_frexp_mant_f16_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_frexp_mant_f16_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_frexp_mant_f16_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_frexp_mant_f16_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_frexp_mant_f16_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_frexp_mant_f16_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_frexp_mant_f16_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_frexp_mant_f16_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_frexp_mant_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_frexp_mant_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_frexp_mant_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_frexp_mant_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xd9,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+v_frexp_mant_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_frexp_mant_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_frexp_mant_f32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_frexp_mant_f32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_frexp_mant_f32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_frexp_mant_f32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_frexp_mant_f32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_frexp_mant_f32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_frexp_mant_f32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_frexp_mant_f32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_frexp_mant_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_frexp_mant_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_frexp_mant_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_frexp_mant_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xc0,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+v_log_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_log_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_log_f16_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_log_f16_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_log_f16_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_log_f16_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_log_f16_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_log_f16_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_log_f16_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_log_f16_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_log_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_log_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_log_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_log_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xd7,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+v_log_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_log_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_log_f32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_log_f32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_log_f32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_log_f32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_log_f32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_log_f32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_log_f32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_log_f32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_log_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_log_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_log_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_log_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xa7,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+v_mov_b32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_mov_b32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_mov_b32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_mov_b32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_mov_b32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_mov_b32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_mov_b32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_mov_b32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_mov_b32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_mov_b32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_mov_b32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_mov_b32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+
+v_mov_b32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x09,0x13]
+
+v_mov_b32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x05,0x30]
+
+v_movrels_b32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_movrels_b32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_movrels_b32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_movrels_b32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_movrels_b32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_movrels_b32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_movrels_b32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_movrels_b32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_movrels_b32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_movrels_b32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_movrels_b32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_movrels_b32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+
+v_movrels_b32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x09,0x13]
+
+v_movrels_b32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x05,0x30]
+
+v_not_b16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_not_b16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_not_b16_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_not_b16_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_not_b16_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_not_b16_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_not_b16_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_not_b16_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_not_b16_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_not_b16_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_not_b16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_not_b16_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+
+v_not_b16_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x09,0x13]
+
+v_not_b16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x05,0x30]
+
+v_not_b32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_not_b32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_not_b32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_not_b32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_not_b32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_not_b32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_not_b32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_not_b32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_not_b32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_not_b32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_not_b32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_not_b32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+
+v_not_b32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x09,0x13]
+
+v_not_b32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x05,0x30]
+
+v_rcp_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_rcp_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_rcp_f16_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_rcp_f16_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_rcp_f16_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_rcp_f16_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_rcp_f16_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_rcp_f16_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_rcp_f16_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_rcp_f16_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_rcp_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_rcp_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_rcp_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_rcp_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xd4,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+v_rcp_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_rcp_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_rcp_f32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_rcp_f32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_rcp_f32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_rcp_f32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_rcp_f32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_rcp_f32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_rcp_f32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_rcp_f32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_rcp_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_rcp_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_rcp_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_rcp_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xaa,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+v_rcp_iflag_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_rcp_iflag_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_rcp_iflag_f32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_rcp_iflag_f32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_rcp_iflag_f32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_rcp_iflag_f32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_rcp_iflag_f32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_rcp_iflag_f32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_rcp_iflag_f32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_rcp_iflag_f32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_rcp_iflag_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_rcp_iflag_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_rcp_iflag_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_rcp_iflag_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xab,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+v_rndne_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_rndne_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_rndne_f16_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_rndne_f16_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_rndne_f16_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_rndne_f16_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_rndne_f16_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_rndne_f16_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_rndne_f16_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_rndne_f16_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_rndne_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_rndne_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_rndne_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_rndne_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xde,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+v_rndne_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_rndne_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_rndne_f32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_rndne_f32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_rndne_f32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_rndne_f32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_rndne_f32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_rndne_f32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_rndne_f32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_rndne_f32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_rndne_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_rndne_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_rndne_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_rndne_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xa3,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+v_rsq_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_rsq_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_rsq_f16_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_rsq_f16_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_rsq_f16_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_rsq_f16_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_rsq_f16_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_rsq_f16_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_rsq_f16_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_rsq_f16_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_rsq_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_rsq_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_rsq_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_rsq_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xd6,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+v_rsq_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_rsq_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_rsq_f32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_rsq_f32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_rsq_f32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_rsq_f32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_rsq_f32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_rsq_f32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_rsq_f32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_rsq_f32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_rsq_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_rsq_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_rsq_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_rsq_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xae,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+v_sat_pk_u8_i16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_sat_pk_u8_i16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_sat_pk_u8_i16_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_sat_pk_u8_i16_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_sat_pk_u8_i16_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_sat_pk_u8_i16_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_sat_pk_u8_i16_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_sat_pk_u8_i16_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_sat_pk_u8_i16_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_sat_pk_u8_i16_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_sat_pk_u8_i16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_sat_pk_u8_i16_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+
+v_sat_pk_u8_i16_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x09,0x13]
+
+v_sat_pk_u8_i16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x05,0x30]
+
+v_sin_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_sin_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_sin_f16_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_sin_f16_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_sin_f16_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_sin_f16_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_sin_f16_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_sin_f16_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_sin_f16_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_sin_f16_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_sin_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_sin_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_sin_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_sin_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xe0,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+v_sin_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_sin_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_sin_f32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_sin_f32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_sin_f32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_sin_f32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_sin_f32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_sin_f32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_sin_f32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_sin_f32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_sin_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_sin_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_sin_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_sin_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xb5,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+v_sqrt_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_sqrt_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_sqrt_f16_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_sqrt_f16_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_sqrt_f16_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_sqrt_f16_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_sqrt_f16_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_sqrt_f16_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_sqrt_f16_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_sqrt_f16_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_sqrt_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_sqrt_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_sqrt_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_sqrt_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xd5,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+v_sqrt_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_sqrt_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_sqrt_f32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_sqrt_f32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_sqrt_f32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_sqrt_f32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_sqrt_f32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_sqrt_f32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_sqrt_f32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_sqrt_f32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_sqrt_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_sqrt_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_sqrt_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_sqrt_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xb3,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+v_trunc_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_trunc_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_trunc_f16_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_trunc_f16_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_trunc_f16_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_trunc_f16_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_trunc_f16_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_trunc_f16_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_trunc_f16_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_trunc_f16_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_trunc_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_trunc_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_trunc_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_trunc_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xdd,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+v_trunc_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+v_trunc_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+v_trunc_f32_e64_dpp v5, v1 row_mirror
+// GFX12: [0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+v_trunc_f32_e64_dpp v5, v1 row_half_mirror
+// GFX12: [0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+v_trunc_f32_e64_dpp v5, v1 row_shl:1
+// GFX12: [0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+v_trunc_f32_e64_dpp v5, v1 row_shl:15
+// GFX12: [0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+v_trunc_f32_e64_dpp v5, v1 row_shr:1
+// GFX12: [0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+v_trunc_f32_e64_dpp v5, v1 row_shr:15
+// GFX12: [0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+v_trunc_f32_e64_dpp v5, v1 row_ror:1
+// GFX12: [0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+v_trunc_f32_e64_dpp v5, v1 row_ror:15
+// GFX12: [0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+v_trunc_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+v_trunc_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+v_trunc_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+v_trunc_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0xa1,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp8.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp8.s
new file mode 100644
index 000000000000..61266f3776c2
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp8.s
@@ -0,0 +1,691 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX12 %s
+
+v_bfrev_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xb8,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_bfrev_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xb8,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_bfrev_b32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0xb8,0xd5,0xe9,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
+
+v_ceil_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xdc,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_ceil_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xdc,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_ceil_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xdc,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_ceil_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xdc,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+v_ceil_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xa2,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_ceil_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xa2,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_ceil_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xa2,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_ceil_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xa2,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+v_cls_i32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xbb,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cls_i32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xbb,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cls_i32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0xbb,0xd5,0xe9,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
+
+v_clz_i32_u32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xb9,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_clz_i32_u32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xb9,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_clz_i32_u32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0xb9,0xd5,0xe9,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
+
+v_cos_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xe1,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cos_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xe1,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_cos_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xe1,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_cos_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xe1,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+v_cos_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xb6,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cos_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xb6,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_cos_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xb6,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_cos_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xb6,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+v_ctz_i32_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xba,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_ctz_i32_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xba,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_ctz_i32_b32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0xba,0xd5,0xe9,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x8a,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_f16_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x8a,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_cvt_f16_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x8a,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_cvt_f16_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0x8a,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xd1,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_f16_i16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xd1,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_cvt_f16_i16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xd1,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_cvt_f16_i16_e64_dpp v255, v255 clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0xd1,0xd5,0xe9,0x00,0x00,0x18,0xff,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xd0,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_f16_u16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xd0,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_cvt_f16_u16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xd0,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_cvt_f16_u16_e64_dpp v255, v255 clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0xd0,0xd5,0xe9,0x00,0x00,0x18,0xff,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x8b,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x8b,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x8b,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0x8b,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x85,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_i32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x85,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_i32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x85,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_i32_e64_dpp v255, v255 clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x85,0xd5,0xe9,0x00,0x00,0x18,0xff,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x86,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_u32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x86,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_u32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x86,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_u32_e64_dpp v255, v255 clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x86,0xd5,0xe9,0x00,0x00,0x18,0xff,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x91,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_ubyte0_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x91,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_ubyte0_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x91,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_ubyte0_e64_dpp v255, v255 clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x91,0xd5,0xe9,0x00,0x00,0x18,0xff,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x92,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_ubyte1_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x92,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_ubyte1_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x92,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_ubyte1_e64_dpp v255, v255 clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x92,0xd5,0xe9,0x00,0x00,0x18,0xff,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x93,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_ubyte2_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x93,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_ubyte2_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x93,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_ubyte2_e64_dpp v255, v255 clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x93,0xd5,0xe9,0x00,0x00,0x18,0xff,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x94,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_ubyte3_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x94,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_ubyte3_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x94,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_cvt_f32_ubyte3_e64_dpp v255, v255 clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x94,0xd5,0xe9,0x00,0x00,0x18,0xff,0x00,0x00,0x00]
+
+v_cvt_floor_i32_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x8d,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_floor_i32_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x8d,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_floor_i32_f32_e64_dpp v255, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x01,0x8d,0xd5,0xe9,0x00,0x00,0x20,0xff,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x8d,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_flr_i32_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x8d,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_flr_i32_f32_e64_dpp v255, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x01,0x8d,0xd5,0xe9,0x00,0x00,0x20,0xff,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xd3,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_i16_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xd3,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_i16_f16_e64_dpp v255, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xd3,0xd5,0xe9,0x00,0x00,0x20,0xff,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x88,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_i32_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x88,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_i32_f32_e64_dpp v255, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0x88,0xd5,0xe9,0x00,0x00,0x20,0xff,0x00,0x00,0x00]
+
+v_cvt_i32_i16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xea,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_i32_i16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xea,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_i32_i16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0xea,0xd5,0xe9,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
+
+v_cvt_nearest_i32_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x8c,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_nearest_i32_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x8c,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_nearest_i32_f32_e64_dpp v255, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x01,0x8c,0xd5,0xe9,0x00,0x00,0x20,0xff,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xe3,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_norm_i16_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xe3,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_norm_i16_f16_e64_dpp v255, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x01,0xe3,0xd5,0xe9,0x00,0x00,0x20,0xff,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xe4,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_norm_u16_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xe4,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_norm_u16_f16_e64_dpp v255, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x01,0xe4,0xd5,0xe9,0x00,0x00,0x20,0xff,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x8e,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_off_f32_i4_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x8e,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_cvt_off_f32_i4_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x8e,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_cvt_off_f32_i4_e64_dpp v255, v255 clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x8e,0xd5,0xe9,0x00,0x00,0x18,0xff,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x8c,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_rpi_i32_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x8c,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_rpi_i32_f32_e64_dpp v255, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x01,0x8c,0xd5,0xe9,0x00,0x00,0x20,0xff,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xd2,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_u16_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xd2,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_u16_f16_e64_dpp v255, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xd2,0xd5,0xe9,0x00,0x00,0x20,0xff,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x87,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_u32_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x87,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_u32_f32_e64_dpp v255, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0x87,0xd5,0xe9,0x00,0x00,0x20,0xff,0x00,0x00,0x00]
+
+v_cvt_u32_u16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xeb,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_u32_u16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xeb,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_u32_u16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0xeb,0xd5,0xe9,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
+
+v_exp_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xd8,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_exp_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xd8,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_exp_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xd8,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_exp_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xd8,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+v_exp_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xa5,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_exp_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xa5,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_exp_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xa5,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_exp_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xa5,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+v_ffbh_i32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xbb,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_ffbh_i32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xbb,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_ffbh_i32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0xbb,0xd5,0xe9,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
+
+v_ffbh_u32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xb9,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_ffbh_u32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xb9,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_ffbh_u32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0xb9,0xd5,0xe9,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
+
+v_ffbl_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xba,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_ffbl_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xba,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_ffbl_b32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0xba,0xd5,0xe9,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
+
+v_floor_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xdb,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_floor_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xdb,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_floor_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xdb,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_floor_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xdb,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+v_floor_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xa4,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_floor_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xa4,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_floor_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xa4,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_floor_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xa4,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+v_fract_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xdf,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_fract_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xdf,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_fract_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xdf,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_fract_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xdf,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+v_fract_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xa0,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_fract_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xa0,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_fract_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xa0,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_fract_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xa0,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xda,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_frexp_exp_i16_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xda,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_frexp_exp_i16_f16_e64_dpp v255, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x01,0xda,0xd5,0xe9,0x00,0x00,0x20,0xff,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xbf,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_frexp_exp_i32_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xbf,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_frexp_exp_i32_f32_e64_dpp v255, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x01,0xbf,0xd5,0xe9,0x00,0x00,0x20,0xff,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xd9,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_frexp_mant_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xd9,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_frexp_mant_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xd9,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_frexp_mant_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xd9,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xc0,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_frexp_mant_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xc0,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_frexp_mant_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xc0,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_frexp_mant_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xc0,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+v_log_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xd7,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_log_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xd7,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_log_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xd7,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_log_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xd7,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+v_log_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xa7,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_log_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xa7,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_log_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xa7,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_log_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xa7,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+v_mov_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x81,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_mov_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x81,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_mov_b32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x81,0xd5,0xe9,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
+
+v_movrels_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xc3,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_movrels_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xc3,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_movrels_b32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0xc3,0xd5,0xe9,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
+
+v_not_b16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xe9,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_not_b16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xe9,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_not_b16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0xe9,0xd5,0xe9,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
+
+v_not_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xb7,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_not_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xb7,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_not_b32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0xb7,0xd5,0xe9,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
+
+v_rcp_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xd4,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_rcp_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xd4,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_rcp_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xd4,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_rcp_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xd4,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+v_rcp_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xaa,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_rcp_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xaa,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_rcp_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xaa,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_rcp_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xaa,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xab,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_rcp_iflag_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xab,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_rcp_iflag_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xab,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_rcp_iflag_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xab,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+v_rndne_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xde,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_rndne_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xde,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_rndne_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xde,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_rndne_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xde,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+v_rndne_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xa3,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_rndne_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xa3,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_rndne_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xa3,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_rndne_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xa3,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+v_rsq_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xd6,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_rsq_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xd6,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_rsq_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xd6,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_rsq_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xd6,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+v_rsq_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xae,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_rsq_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xae,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_rsq_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xae,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_rsq_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xae,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xe2,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_sat_pk_u8_i16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xe2,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_sat_pk_u8_i16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0xe2,0xd5,0xe9,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
+
+v_sin_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xe0,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_sin_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xe0,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_sin_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xe0,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_sin_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xe0,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+v_sin_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xb5,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_sin_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xb5,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_sin_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xb5,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_sin_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xb5,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+v_sqrt_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xd5,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_sqrt_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xd5,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_sqrt_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xd5,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_sqrt_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xd5,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+v_sqrt_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xb3,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_sqrt_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xb3,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_sqrt_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xb3,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_sqrt_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xb3,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+v_trunc_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xdd,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_trunc_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xdd,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_trunc_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xdd,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_trunc_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xdd,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+v_trunc_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xa1,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+v_trunc_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0xa1,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+v_trunc_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0xa1,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+v_trunc_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0xa1,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s
new file mode 100644
index 000000000000..7ba33bc9170e
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s
@@ -0,0 +1,2268 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W32 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W64 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+
+v_add_co_ci_u32_e64 v5, s6, v1, 0xaf123456, s3
+// W32: encoding: [0x05,0x06,0x20,0xd5,0x01,0xff,0x0d,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s6, v255, src_scc, s3
+// W32: encoding: [0x05,0x06,0x20,0xd5,0xff,0xfb,0x0d,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s6, s105, s105, s3
+// W32: encoding: [0x05,0x06,0x20,0xd5,0x69,0xd2,0x0c,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s6, vcc_lo, v2, s3
+// W32: encoding: [0x05,0x06,0x20,0xd5,0x6a,0x04,0x0e,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s6, vcc_hi, v255, s3
+// W32: encoding: [0x05,0x06,0x20,0xd5,0x6b,0xfe,0x0f,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s6, ttmp15, ttmp15, s3
+// W32: encoding: [0x05,0x06,0x20,0xd5,0x7b,0xf6,0x0c,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s6, m0, 0.5, s3
+// W32: encoding: [0x05,0x06,0x20,0xd5,0x7d,0xe0,0x0d,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s6, exec_lo, exec_lo, s3
+// W32: encoding: [0x05,0x06,0x20,0xd5,0x7e,0xfc,0x0c,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s6, exec_hi, -1, s3
+// W32: encoding: [0x05,0x06,0x20,0xd5,0x7f,0x82,0x0d,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s105, null, exec_hi, s105
+// W32: encoding: [0x05,0x69,0x20,0xd5,0x7c,0xfe,0xa4,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, vcc_lo, -1, m0, vcc_lo
+// W32: encoding: [0x05,0x6a,0x20,0xd5,0xc1,0xfa,0xa8,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, vcc_hi, 0.5, vcc_lo, vcc_hi
+// W32: encoding: [0x05,0x6b,0x20,0xd5,0xf0,0xd4,0xac,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, ttmp15, src_scc, null, ttmp15
+// W32: encoding: [0x05,0x7b,0x20,0xd5,0xfd,0xf8,0xec,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s[12:13], v1, 0xaf123456, s[6:7]
+// W64: encoding: [0x05,0x0c,0x20,0xd5,0x01,0xff,0x19,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s[12:13], v255, src_scc, s[6:7]
+// W64: encoding: [0x05,0x0c,0x20,0xd5,0xff,0xfb,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s[12:13], s105, s105, s[6:7]
+// W64: encoding: [0x05,0x0c,0x20,0xd5,0x69,0xd2,0x18,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s[12:13], vcc_lo, v2, s[6:7]
+// W64: encoding: [0x05,0x0c,0x20,0xd5,0x6a,0x04,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s[12:13], vcc_hi, v255, s[6:7]
+// W64: encoding: [0x05,0x0c,0x20,0xd5,0x6b,0xfe,0x1b,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s[12:13], ttmp15, ttmp15, s[6:7]
+// W64: encoding: [0x05,0x0c,0x20,0xd5,0x7b,0xf6,0x18,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s[12:13], m0, 0.5, s[6:7]
+// W64: encoding: [0x05,0x0c,0x20,0xd5,0x7d,0xe0,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s[12:13], exec_lo, exec_lo, s[6:7]
+// W64: encoding: [0x05,0x0c,0x20,0xd5,0x7e,0xfc,0x18,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s[12:13], exec_hi, -1, s[6:7]
+// W64: encoding: [0x05,0x0c,0x20,0xd5,0x7f,0x82,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s[12:13], null, exec_hi, s[6:7]
+// W64: encoding: [0x05,0x0c,0x20,0xd5,0x7c,0xfe,0x18,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s[104:105], -1, m0, s[104:105]
+// W64: encoding: [0x05,0x68,0x20,0xd5,0xc1,0xfa,0xa0,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, vcc, 0.5, vcc_lo, vcc
+// W64: encoding: [0x05,0x6a,0x20,0xd5,0xf0,0xd4,0xa8,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, ttmp[14:15], src_scc, null, ttmp[14:15]
+// W64: encoding: [0x05,0x7a,0x20,0xd5,0xfd,0xf8,0xe8,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v255, null, 0xaf123456, vcc_hi, null clamp
+// GFX12: encoding: [0xff,0xfc,0x20,0xd5,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_add_f16_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x32,0xd5,0x01,0x05,0x02,0x00]
+
+v_add_f16_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x32,0xd5,0xff,0xff,0x03,0x00]
+
+v_add_f16_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x32,0xd5,0x01,0x04,0x00,0x00]
+
+v_add_f16_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x32,0xd5,0x69,0xd2,0x00,0x00]
+
+v_add_f16_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x32,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_add_f16_e64 v5, vcc_hi, 0xfe0b
+// GFX12: encoding: [0x05,0x00,0x32,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_add_f16_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x32,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_add_f16_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x32,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_add_f16_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x32,0xd5,0x7e,0x82,0x01,0x00]
+
+v_add_f16_e64 v5, |exec_hi|, null
+// GFX12: encoding: [0x05,0x01,0x32,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_add_f16_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x32,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_add_f16_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x32,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_add_f16_e64 v5, 0.5, -m0 mul:2
+// GFX12: encoding: [0x05,0x00,0x32,0xd5,0xf0,0xfa,0x00,0x48]
+
+v_add_f16_e64 v5, -src_scc, |vcc_lo| mul:4
+// GFX12: encoding: [0x05,0x02,0x32,0xd5,0xfd,0xd4,0x00,0x30]
+
+v_add_f16_e64 v255, -|0xfe0b|, -|vcc_hi| clamp div:2
+// GFX12: encoding: [0xff,0x83,0x32,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00]
+
+v_add_f32_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x03,0xd5,0x01,0x05,0x02,0x00]
+
+v_add_f32_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x03,0xd5,0xff,0xff,0x03,0x00]
+
+v_add_f32_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x03,0xd5,0x01,0x04,0x00,0x00]
+
+v_add_f32_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x03,0xd5,0x69,0xd2,0x00,0x00]
+
+v_add_f32_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x03,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_add_f32_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x03,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_add_f32_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x03,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_add_f32_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x03,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_add_f32_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x03,0xd5,0x7e,0x82,0x01,0x00]
+
+v_add_f32_e64 v5, |exec_hi|, null
+// GFX12: encoding: [0x05,0x01,0x03,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_add_f32_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x03,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_add_f32_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x03,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_add_f32_e64 v5, 0.5, -m0 mul:2
+// GFX12: encoding: [0x05,0x00,0x03,0xd5,0xf0,0xfa,0x00,0x48]
+
+v_add_f32_e64 v5, -src_scc, |vcc_lo| mul:4
+// GFX12: encoding: [0x05,0x02,0x03,0xd5,0xfd,0xd4,0x00,0x30]
+
+v_add_f32_e64 v255, -|0xaf123456|, -|vcc_hi| clamp div:2
+// GFX12: encoding: [0xff,0x83,0x03,0xd5,0xff,0xd6,0x00,0x78,0x56,0x34,0x12,0xaf]
+
+v_add_f64_e64 v[5:6], v[2:3], v[4:5]
+// GFX12: encoding: [0x05,0x00,0x02,0xd5,0x02,0x09,0x02,0x00]
+
+v_add_f64_e64 v[5:6], v[104:105], v[104:105]
+// GFX12: encoding: [0x05,0x00,0x02,0xd5,0x68,0xd1,0x02,0x00]
+
+v_add_f64_e64 v[5:6], s[2:3], s[4:5]
+// GFX12: encoding: [0x05,0x00,0x02,0xd5,0x02,0x08,0x00,0x00]
+
+v_add_f64_e64 v[5:6], s[104:105], s[104:105]
+// GFX12: encoding: [0x05,0x00,0x02,0xd5,0x68,0xd0,0x00,0x00]
+
+v_add_f64_e64 v[5:6], vcc, ttmp[14:15]
+// GFX12: encoding: [0x05,0x00,0x02,0xd5,0x6a,0xf4,0x00,0x00]
+
+v_add_f64_e64 v[5:6], ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x02,0xd5,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_add_f64_e64 v[5:6], -|exec|, src_scc
+// GFX12: encoding: [0x05,0x01,0x02,0xd5,0x7e,0xfa,0x01,0x20]
+
+v_add_f64_e64 v[5:6], null, 0.5
+// GFX12: encoding: [0x05,0x00,0x02,0xd5,0x7c,0xe0,0x01,0x00]
+
+v_add_f64_e64 v[5:6], -1, -1
+// GFX12: encoding: [0x05,0x00,0x02,0xd5,0xc1,0x82,0x01,0x00]
+
+v_add_f64_e64 v[5:6], 0.5, null mul:2
+// GFX12: encoding: [0x05,0x00,0x02,0xd5,0xf0,0xf8,0x00,0x08]
+
+v_add_f64_e64 v[5:6], -|src_scc|, -|exec| mul:4
+// GFX12: encoding: [0x05,0x03,0x02,0xd5,0xfd,0xfc,0x00,0x70]
+
+v_add_f64_e64 v[254:255], 0xaf123456, -|vcc| clamp div:2
+// GFX12: encoding: [0xfe,0x82,0x02,0xd5,0xff,0xd4,0x00,0x58,0x56,0x34,0x12,0xaf]
+
+v_add_nc_u32_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x25,0xd5,0x01,0x05,0x02,0x00]
+
+v_add_nc_u32_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x25,0xd5,0xff,0xff,0x03,0x00]
+
+v_add_nc_u32_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x25,0xd5,0x01,0x04,0x00,0x00]
+
+v_add_nc_u32_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x25,0xd5,0x69,0xd2,0x00,0x00]
+
+v_add_nc_u32_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x25,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_add_nc_u32_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x25,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_add_nc_u32_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x25,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_add_nc_u32_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x25,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_add_nc_u32_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x25,0xd5,0x7e,0x82,0x01,0x00]
+
+v_add_nc_u32_e64 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x25,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_add_nc_u32_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x25,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_add_nc_u32_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x25,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_add_nc_u32_e64 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x25,0xd5,0xf0,0xfa,0x00,0x00]
+
+v_add_nc_u32_e64 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x25,0xd5,0xfd,0xd4,0x00,0x00]
+
+v_add_nc_u32_e64 v255, 0xaf123456, vcc_hi clamp
+// GFX12: encoding: [0xff,0x80,0x25,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_and_b32_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x1b,0xd5,0x01,0x05,0x02,0x00]
+
+v_and_b32_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x1b,0xd5,0xff,0xff,0x03,0x00]
+
+v_and_b32_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x1b,0xd5,0x01,0x04,0x00,0x00]
+
+v_and_b32_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x1b,0xd5,0x69,0xd2,0x00,0x00]
+
+v_and_b32_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x1b,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_and_b32_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x1b,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_and_b32_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x1b,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_and_b32_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x1b,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_and_b32_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x1b,0xd5,0x7e,0x82,0x01,0x00]
+
+v_and_b32_e64 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x1b,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_and_b32_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x1b,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_and_b32_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x1b,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_and_b32_e64 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x1b,0xd5,0xf0,0xfa,0x00,0x00]
+
+v_and_b32_e64 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x1b,0xd5,0xfd,0xd4,0x00,0x00]
+
+v_and_b32_e64 v255, 0xaf123456, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x1b,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_ashrrev_i32_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x1a,0xd5,0x01,0x05,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x1a,0xd5,0xff,0xff,0x03,0x00]
+
+v_ashrrev_i32_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x1a,0xd5,0x01,0x04,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x1a,0xd5,0x69,0xd2,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x1a,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x1a,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_ashrrev_i32_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x1a,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_ashrrev_i32_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x1a,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_ashrrev_i32_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x1a,0xd5,0x7e,0x82,0x01,0x00]
+
+v_ashrrev_i32_e64 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x1a,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x1a,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x1a,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x1a,0xd5,0xf0,0xfa,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x1a,0xd5,0xfd,0xd4,0x00,0x00]
+
+v_ashrrev_i32_e64 v255, 0xaf123456, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x1a,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cndmask_b32_e64 v5, v1, 0xaf123456, s3
+// W32: encoding: [0x05,0x00,0x01,0xd5,0x01,0xff,0x0d,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, v255, src_scc, s3
+// W32: encoding: [0x05,0x00,0x01,0xd5,0xff,0xfb,0x0d,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, s105, s105, s3
+// W32: encoding: [0x05,0x00,0x01,0xd5,0x69,0xd2,0x0c,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, vcc_lo, v2, s3
+// W32: encoding: [0x05,0x00,0x01,0xd5,0x6a,0x04,0x0e,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, vcc_hi, v255, s3
+// W32: encoding: [0x05,0x00,0x01,0xd5,0x6b,0xfe,0x0f,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, ttmp15, ttmp15, s3
+// W32: encoding: [0x05,0x00,0x01,0xd5,0x7b,0xf6,0x0c,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, m0, 0.5, s3
+// W32: encoding: [0x05,0x00,0x01,0xd5,0x7d,0xe0,0x0d,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, exec_lo, exec_lo, s3
+// W32: encoding: [0x05,0x00,0x01,0xd5,0x7e,0xfc,0x0c,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, exec_hi, -1, s3
+// W32: encoding: [0x05,0x00,0x01,0xd5,0x7f,0x82,0x0d,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, null, exec_hi, s105
+// W32: encoding: [0x05,0x00,0x01,0xd5,0x7c,0xfe,0xa4,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, -1, m0, vcc_lo
+// W32: encoding: [0x05,0x00,0x01,0xd5,0xc1,0xfa,0xa8,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, 0.5, -|vcc_lo|, vcc_hi
+// W32: encoding: [0x05,0x02,0x01,0xd5,0xf0,0xd4,0xac,0x41]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, -|src_scc|, null, ttmp15
+// W32: encoding: [0x05,0x01,0x01,0xd5,0xfd,0xf8,0xec,0x21]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, v1, 0xaf123456, s[6:7]
+// W64: encoding: [0x05,0x00,0x01,0xd5,0x01,0xff,0x19,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, v255, src_scc, s[6:7]
+// W64: encoding: [0x05,0x00,0x01,0xd5,0xff,0xfb,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, s105, s105, s[6:7]
+// W64: encoding: [0x05,0x00,0x01,0xd5,0x69,0xd2,0x18,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, vcc_lo, v2, s[6:7]
+// W64: encoding: [0x05,0x00,0x01,0xd5,0x6a,0x04,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, vcc_hi, v255, s[6:7]
+// W64: encoding: [0x05,0x00,0x01,0xd5,0x6b,0xfe,0x1b,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, ttmp15, ttmp15, s[6:7]
+// W64: encoding: [0x05,0x00,0x01,0xd5,0x7b,0xf6,0x18,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, m0, 0.5, s[6:7]
+// W64: encoding: [0x05,0x00,0x01,0xd5,0x7d,0xe0,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, exec_lo, exec_lo, s[6:7]
+// W64: encoding: [0x05,0x00,0x01,0xd5,0x7e,0xfc,0x18,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, exec_hi, -1, s[6:7]
+// W64: encoding: [0x05,0x00,0x01,0xd5,0x7f,0x82,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, null, exec_hi, s[6:7]
+// W64: encoding: [0x05,0x00,0x01,0xd5,0x7c,0xfe,0x18,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, -1, m0, s[104:105]
+// W64: encoding: [0x05,0x00,0x01,0xd5,0xc1,0xfa,0xa0,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, 0.5, -|vcc_lo|, vcc
+// W64: encoding: [0x05,0x02,0x01,0xd5,0xf0,0xd4,0xa8,0x41]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, -|src_scc|, null, ttmp[14:15]
+// W64: encoding: [0x05,0x01,0x01,0xd5,0xfd,0xf8,0xe8,0x21]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v255, -|0xaf123456|, -|vcc_hi|, null
+// GFX12: encoding: [0xff,0x03,0x01,0xd5,0xff,0xd6,0xf0,0x61,0x56,0x34,0x12,0xaf]
+
+v_cvt_pk_rtz_f16_f32_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x2f,0xd5,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_rtz_f16_f32_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x2f,0xd5,0xff,0xff,0x03,0x00]
+
+v_cvt_pk_rtz_f16_f32_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x2f,0xd5,0x01,0x04,0x00,0x00]
+
+v_cvt_pk_rtz_f16_f32_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x2f,0xd5,0x69,0xd2,0x00,0x00]
+
+v_cvt_pk_rtz_f16_f32_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x2f,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_cvt_pk_rtz_f16_f32_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x2f,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cvt_pk_rtz_f16_f32_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x2f,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_cvt_pk_rtz_f16_f32_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x2f,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_cvt_pk_rtz_f16_f32_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x2f,0xd5,0x7e,0x82,0x01,0x00]
+
+v_cvt_pk_rtz_f16_f32_e64 v5, |exec_hi|, null
+// GFX12: encoding: [0x05,0x01,0x2f,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_cvt_pk_rtz_f16_f32_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x2f,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_cvt_pk_rtz_f16_f32_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x2f,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_cvt_pk_rtz_f16_f32_e64 v5, 0.5, -m0
+// GFX12: encoding: [0x05,0x00,0x2f,0xd5,0xf0,0xfa,0x00,0x40]
+
+v_cvt_pk_rtz_f16_f32_e64 v5, -src_scc, |vcc_lo|
+// GFX12: encoding: [0x05,0x02,0x2f,0xd5,0xfd,0xd4,0x00,0x20]
+
+v_cvt_pk_rtz_f16_f32_e64 v255, -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0xff,0x83,0x2f,0xd5,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x2f,0xd5,0x01,0x05,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x2f,0xd5,0xff,0xff,0x03,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x2f,0xd5,0x01,0x04,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x2f,0xd5,0x69,0xd2,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x2f,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x2f,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cvt_pkrtz_f16_f32_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x2f,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x2f,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x2f,0xd5,0x7e,0x82,0x01,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, |exec_hi|, null
+// GFX12: encoding: [0x05,0x01,0x2f,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x2f,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x2f,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, 0.5, -m0
+// GFX12: encoding: [0x05,0x00,0x2f,0xd5,0xf0,0xfa,0x00,0x40]
+
+v_cvt_pkrtz_f16_f32_e64 v5, -src_scc, |vcc_lo|
+// GFX12: encoding: [0x05,0x02,0x2f,0xd5,0xfd,0xd4,0x00,0x20]
+
+v_cvt_pkrtz_f16_f32_e64 v255, -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0xff,0x83,0x2f,0xd5,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_fmac_f16_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x36,0xd5,0x01,0x05,0x02,0x00]
+
+v_fmac_f16_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x36,0xd5,0xff,0xff,0x03,0x00]
+
+v_fmac_f16_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x36,0xd5,0x01,0x04,0x00,0x00]
+
+v_fmac_f16_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x36,0xd5,0x69,0xd2,0x00,0x00]
+
+v_fmac_f16_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x36,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_fmac_f16_e64 v5, vcc_hi, 0xfe0b
+// GFX12: encoding: [0x05,0x00,0x36,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_fmac_f16_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x36,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_fmac_f16_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x36,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_fmac_f16_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x36,0xd5,0x7e,0x82,0x01,0x00]
+
+v_fmac_f16_e64 v5, |exec_hi|, null
+// GFX12: encoding: [0x05,0x01,0x36,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_fmac_f16_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x36,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_fmac_f16_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x36,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_fmac_f16_e64 v5, 0.5, -m0 mul:2
+// GFX12: encoding: [0x05,0x00,0x36,0xd5,0xf0,0xfa,0x00,0x48]
+
+v_fmac_f16_e64 v5, -src_scc, |vcc_lo| mul:4
+// GFX12: encoding: [0x05,0x02,0x36,0xd5,0xfd,0xd4,0x00,0x30]
+
+v_fmac_f16_e64 v255, -|0xfe0b|, -|vcc_hi| clamp div:2
+// GFX12: encoding: [0xff,0x83,0x36,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00]
+
+v_fmac_f32_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x2b,0xd5,0x01,0x05,0x02,0x00]
+
+v_fmac_f32_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x2b,0xd5,0xff,0xff,0x03,0x00]
+
+v_fmac_f32_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x2b,0xd5,0x01,0x04,0x00,0x00]
+
+v_fmac_f32_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x2b,0xd5,0x69,0xd2,0x00,0x00]
+
+v_fmac_f32_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x2b,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_fmac_f32_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x2b,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_fmac_f32_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x2b,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_fmac_f32_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x2b,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_fmac_f32_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x2b,0xd5,0x7e,0x82,0x01,0x00]
+
+v_fmac_f32_e64 v5, |exec_hi|, null
+// GFX12: encoding: [0x05,0x01,0x2b,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_fmac_f32_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x2b,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_fmac_f32_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x2b,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_fmac_f32_e64 v5, 0.5, -m0 mul:2
+// GFX12: encoding: [0x05,0x00,0x2b,0xd5,0xf0,0xfa,0x00,0x48]
+
+v_fmac_f32_e64 v5, -src_scc, |vcc_lo| mul:4
+// GFX12: encoding: [0x05,0x02,0x2b,0xd5,0xfd,0xd4,0x00,0x30]
+
+v_fmac_f32_e64 v255, -|0xaf123456|, -|vcc_hi| clamp div:2
+// GFX12: encoding: [0xff,0x83,0x2b,0xd5,0xff,0xd6,0x00,0x78,0x56,0x34,0x12,0xaf]
+
+v_ldexp_f16_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x3b,0xd5,0x01,0x05,0x02,0x00]
+
+v_ldexp_f16_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x3b,0xd5,0xff,0xff,0x03,0x00]
+
+v_ldexp_f16_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x3b,0xd5,0x01,0x04,0x00,0x00]
+
+v_ldexp_f16_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x3b,0xd5,0x69,0xd2,0x00,0x00]
+
+v_ldexp_f16_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x3b,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_ldexp_f16_e64 v5, vcc_hi, 0xfe0b
+// GFX12: encoding: [0x05,0x00,0x3b,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_ldexp_f16_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x3b,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_ldexp_f16_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x3b,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_ldexp_f16_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x3b,0xd5,0x7e,0x82,0x01,0x00]
+
+v_ldexp_f16_e64 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x3b,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_ldexp_f16_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x3b,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_ldexp_f16_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x3b,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_ldexp_f16_e64 v5, 0.5, m0 mul:2
+// GFX12: encoding: [0x05,0x00,0x3b,0xd5,0xf0,0xfa,0x00,0x08]
+
+v_ldexp_f16_e64 v5, src_scc, vcc_lo mul:4
+// GFX12: encoding: [0x05,0x00,0x3b,0xd5,0xfd,0xd4,0x00,0x10]
+
+v_ldexp_f16_e64 v255, -|0xfe0b|, vcc_hi clamp div:2
+// GFX12: encoding: [0xff,0x81,0x3b,0xd5,0xff,0xd6,0x00,0x38,0x0b,0xfe,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x18,0xd5,0x01,0x05,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x18,0xd5,0xff,0xff,0x03,0x00]
+
+v_lshlrev_b32_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x18,0xd5,0x01,0x04,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x18,0xd5,0x69,0xd2,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x18,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x18,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_lshlrev_b32_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x18,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_lshlrev_b32_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x18,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_lshlrev_b32_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x18,0xd5,0x7e,0x82,0x01,0x00]
+
+v_lshlrev_b32_e64 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x18,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x18,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x18,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x18,0xd5,0xf0,0xfa,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x18,0xd5,0xfd,0xd4,0x00,0x00]
+
+v_lshlrev_b32_e64 v255, 0xaf123456, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x18,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_lshlrev_b64_e64 v[5:6], v1, v[2:3]
+// GFX12: encoding: [0x05,0x00,0x1f,0xd5,0x01,0x05,0x02,0x00]
+
+v_lshlrev_b64_e64 v[5:6], v255, v[254:255]
+// GFX12: encoding: [0x05,0x00,0x1f,0xd5,0xff,0xfd,0x03,0x00]
+
+v_lshlrev_b64_e64 v[5:6], v1, vcc
+// GFX12: encoding: [0x05,0x00,0x1f,0xd5,0x01,0xd5,0x00,0x00]
+
+v_lshlrev_b64_e64 v[5:6], v255, exec
+// GFX12: encoding: [0x05,0x00,0x1f,0xd5,0xff,0xfd,0x00,0x00]
+
+v_lshlrev_b64_e64 v[5:6], null, null
+// GFX12: encoding: [0x05,0x00,0x1f,0xd5,0x7c,0xf8,0x00,0x00]
+
+v_lshlrev_b64_e64 v[5:6], -1, -1
+// GFX12: encoding: [0x05,0x00,0x1f,0xd5,0xc1,0x82,0x01,0x00]
+
+v_lshlrev_b64_e64 v[5:6], 0.5, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x1f,0xd5,0xf0,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_lshlrev_b64_e64 v[5:6], src_scc, src_scc
+// GFX12: encoding: [0x05,0x00,0x1f,0xd5,0xfd,0xfa,0x01,0x00]
+
+v_lshlrev_b64_e64 v[254:255], 0xaf123456, 0.5
+// GFX12: encoding: [0xfe,0x00,0x1f,0xd5,0xff,0xe0,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_lshrrev_b32_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x19,0xd5,0x01,0x05,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x19,0xd5,0xff,0xff,0x03,0x00]
+
+v_lshrrev_b32_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x19,0xd5,0x01,0x04,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x19,0xd5,0x69,0xd2,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x19,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x19,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_lshrrev_b32_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x19,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_lshrrev_b32_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x19,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_lshrrev_b32_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x19,0xd5,0x7e,0x82,0x01,0x00]
+
+v_lshrrev_b32_e64 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x19,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x19,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x19,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x19,0xd5,0xf0,0xfa,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x19,0xd5,0xfd,0xd4,0x00,0x00]
+
+v_lshrrev_b32_e64 v255, 0xaf123456, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x19,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_max_num_f16_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x31,0xd5,0x01,0x05,0x02,0x00]
+
+v_max_num_f16_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x31,0xd5,0xff,0xff,0x03,0x00]
+
+v_max_num_f16_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x31,0xd5,0x01,0x04,0x00,0x00]
+
+v_max_num_f16_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x31,0xd5,0x69,0xd2,0x00,0x00]
+
+v_max_num_f16_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x31,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_max_num_f16_e64 v5, vcc_hi, 0xfe0b
+// GFX12: encoding: [0x05,0x00,0x31,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_max_num_f16_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x31,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_max_num_f16_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x31,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_max_num_f16_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x31,0xd5,0x7e,0x82,0x01,0x00]
+
+v_max_num_f16_e64 v5, |exec_hi|, null
+// GFX12: encoding: [0x05,0x01,0x31,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_max_num_f16_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x31,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_max_num_f16_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x31,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_max_num_f16_e64 v5, 0.5, -m0 mul:2
+// GFX12: encoding: [0x05,0x00,0x31,0xd5,0xf0,0xfa,0x00,0x48]
+
+v_max_num_f16_e64 v5, -src_scc, |vcc_lo| mul:4
+// GFX12: encoding: [0x05,0x02,0x31,0xd5,0xfd,0xd4,0x00,0x30]
+
+v_max_num_f16_e64 v255, -|0xfe0b|, -|vcc_hi| clamp div:2
+// GFX12: encoding: [0xff,0x83,0x31,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00]
+
+v_max_num_f32_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x16,0xd5,0x01,0x05,0x02,0x00]
+
+v_max_num_f32_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x16,0xd5,0xff,0xff,0x03,0x00]
+
+v_max_num_f32_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x16,0xd5,0x01,0x04,0x00,0x00]
+
+v_max_num_f32_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x16,0xd5,0x69,0xd2,0x00,0x00]
+
+v_max_num_f32_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x16,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_max_num_f32_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x16,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_max_num_f32_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x16,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_max_num_f32_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x16,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_max_num_f32_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x16,0xd5,0x7e,0x82,0x01,0x00]
+
+v_max_num_f32_e64 v5, |exec_hi|, null
+// GFX12: encoding: [0x05,0x01,0x16,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_max_num_f32_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x16,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_max_num_f32_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x16,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_max_num_f32_e64 v5, 0.5, -m0 mul:2
+// GFX12: encoding: [0x05,0x00,0x16,0xd5,0xf0,0xfa,0x00,0x48]
+
+v_max_num_f32_e64 v5, -src_scc, |vcc_lo| mul:4
+// GFX12: encoding: [0x05,0x02,0x16,0xd5,0xfd,0xd4,0x00,0x30]
+
+v_max_num_f32_e64 v255, -|0xaf123456|, -|vcc_hi| clamp div:2
+// GFX12: encoding: [0xff,0x83,0x16,0xd5,0xff,0xd6,0x00,0x78,0x56,0x34,0x12,0xaf]
+
+v_max_num_f64_e64 v[5:6], v[2:3], v[4:5]
+// GFX12: encoding: [0x05,0x00,0x0e,0xd5,0x02,0x09,0x02,0x00]
+
+v_max_num_f64_e64 v[5:6], v[104:105], v[104:105]
+// GFX12: encoding: [0x05,0x00,0x0e,0xd5,0x68,0xd1,0x02,0x00]
+
+v_max_num_f64_e64 v[5:6], s[2:3], s[4:5]
+// GFX12: encoding: [0x05,0x00,0x0e,0xd5,0x02,0x08,0x00,0x00]
+
+v_max_num_f64_e64 v[5:6], s[104:105], s[104:105]
+// GFX12: encoding: [0x05,0x00,0x0e,0xd5,0x68,0xd0,0x00,0x00]
+
+v_max_num_f64_e64 v[5:6], vcc, ttmp[14:15]
+// GFX12: encoding: [0x05,0x00,0x0e,0xd5,0x6a,0xf4,0x00,0x00]
+
+v_max_num_f64_e64 v[5:6], ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x0e,0xd5,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_max_num_f64_e64 v[5:6], -|exec|, src_scc
+// GFX12: encoding: [0x05,0x01,0x0e,0xd5,0x7e,0xfa,0x01,0x20]
+
+v_max_num_f64_e64 v[5:6], null, 0.5
+// GFX12: encoding: [0x05,0x00,0x0e,0xd5,0x7c,0xe0,0x01,0x00]
+
+v_max_num_f64_e64 v[5:6], -1, -1
+// GFX12: encoding: [0x05,0x00,0x0e,0xd5,0xc1,0x82,0x01,0x00]
+
+v_max_num_f64_e64 v[5:6], 0.5, null mul:2
+// GFX12: encoding: [0x05,0x00,0x0e,0xd5,0xf0,0xf8,0x00,0x08]
+
+v_max_num_f64_e64 v[5:6], -|src_scc|, -|exec| mul:4
+// GFX12: encoding: [0x05,0x03,0x0e,0xd5,0xfd,0xfc,0x00,0x70]
+
+v_max_num_f64_e64 v[254:255], 0xaf123456, -|vcc| clamp div:2
+// GFX12: encoding: [0xfe,0x82,0x0e,0xd5,0xff,0xd4,0x00,0x58,0x56,0x34,0x12,0xaf]
+
+v_max_i32_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x12,0xd5,0x01,0x05,0x02,0x00]
+
+v_max_i32_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x12,0xd5,0xff,0xff,0x03,0x00]
+
+v_max_i32_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x12,0xd5,0x01,0x04,0x00,0x00]
+
+v_max_i32_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x12,0xd5,0x69,0xd2,0x00,0x00]
+
+v_max_i32_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x12,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_max_i32_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x12,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_max_i32_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x12,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_max_i32_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x12,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_max_i32_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x12,0xd5,0x7e,0x82,0x01,0x00]
+
+v_max_i32_e64 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x12,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_max_i32_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x12,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_max_i32_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x12,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_max_i32_e64 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x12,0xd5,0xf0,0xfa,0x00,0x00]
+
+v_max_i32_e64 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x12,0xd5,0xfd,0xd4,0x00,0x00]
+
+v_max_i32_e64 v255, 0xaf123456, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x12,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_max_u32_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x14,0xd5,0x01,0x05,0x02,0x00]
+
+v_max_u32_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x14,0xd5,0xff,0xff,0x03,0x00]
+
+v_max_u32_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x14,0xd5,0x01,0x04,0x00,0x00]
+
+v_max_u32_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x14,0xd5,0x69,0xd2,0x00,0x00]
+
+v_max_u32_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x14,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_max_u32_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x14,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_max_u32_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x14,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_max_u32_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x14,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_max_u32_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x14,0xd5,0x7e,0x82,0x01,0x00]
+
+v_max_u32_e64 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x14,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_max_u32_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x14,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_max_u32_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x14,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_max_u32_e64 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x14,0xd5,0xf0,0xfa,0x00,0x00]
+
+v_max_u32_e64 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x14,0xd5,0xfd,0xd4,0x00,0x00]
+
+v_max_u32_e64 v255, 0xaf123456, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x14,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_min_num_f16_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x30,0xd5,0x01,0x05,0x02,0x00]
+
+v_min_num_f16_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x30,0xd5,0xff,0xff,0x03,0x00]
+
+v_min_num_f16_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x30,0xd5,0x01,0x04,0x00,0x00]
+
+v_min_num_f16_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x30,0xd5,0x69,0xd2,0x00,0x00]
+
+v_min_num_f16_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x30,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_min_num_f16_e64 v5, vcc_hi, 0xfe0b
+// GFX12: encoding: [0x05,0x00,0x30,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_min_num_f16_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x30,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_min_num_f16_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x30,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_min_num_f16_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x30,0xd5,0x7e,0x82,0x01,0x00]
+
+v_min_num_f16_e64 v5, |exec_hi|, null
+// GFX12: encoding: [0x05,0x01,0x30,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_min_num_f16_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x30,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_min_num_f16_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x30,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_min_num_f16_e64 v5, 0.5, -m0 mul:2
+// GFX12: encoding: [0x05,0x00,0x30,0xd5,0xf0,0xfa,0x00,0x48]
+
+v_min_num_f16_e64 v5, -src_scc, |vcc_lo| mul:4
+// GFX12: encoding: [0x05,0x02,0x30,0xd5,0xfd,0xd4,0x00,0x30]
+
+v_min_num_f16_e64 v255, -|0xfe0b|, -|vcc_hi| clamp div:2
+// GFX12: encoding: [0xff,0x83,0x30,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00]
+
+v_min_num_f32_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x15,0xd5,0x01,0x05,0x02,0x00]
+
+v_min_num_f32_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x15,0xd5,0xff,0xff,0x03,0x00]
+
+v_min_num_f32_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x15,0xd5,0x01,0x04,0x00,0x00]
+
+v_min_num_f32_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x15,0xd5,0x69,0xd2,0x00,0x00]
+
+v_min_num_f32_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x15,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_min_num_f32_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x15,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_min_num_f32_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x15,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_min_num_f32_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x15,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_min_num_f32_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x15,0xd5,0x7e,0x82,0x01,0x00]
+
+v_min_num_f32_e64 v5, |exec_hi|, null
+// GFX12: encoding: [0x05,0x01,0x15,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_min_num_f32_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x15,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_min_num_f32_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x15,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_min_num_f32_e64 v5, 0.5, -m0 mul:2
+// GFX12: encoding: [0x05,0x00,0x15,0xd5,0xf0,0xfa,0x00,0x48]
+
+v_min_num_f32_e64 v5, -src_scc, |vcc_lo| mul:4
+// GFX12: encoding: [0x05,0x02,0x15,0xd5,0xfd,0xd4,0x00,0x30]
+
+v_min_num_f32_e64 v255, -|0xaf123456|, -|vcc_hi| clamp div:2
+// GFX12: encoding: [0xff,0x83,0x15,0xd5,0xff,0xd6,0x00,0x78,0x56,0x34,0x12,0xaf]
+
+v_min_num_f64_e64 v[5:6], v[2:3], v[4:5]
+// GFX12: encoding: [0x05,0x00,0x0d,0xd5,0x02,0x09,0x02,0x00]
+
+v_min_num_f64_e64 v[5:6], v[104:105], v[104:105]
+// GFX12: encoding: [0x05,0x00,0x0d,0xd5,0x68,0xd1,0x02,0x00]
+
+v_min_num_f64_e64 v[5:6], s[2:3], s[4:5]
+// GFX12: encoding: [0x05,0x00,0x0d,0xd5,0x02,0x08,0x00,0x00]
+
+v_min_num_f64_e64 v[5:6], s[104:105], s[104:105]
+// GFX12: encoding: [0x05,0x00,0x0d,0xd5,0x68,0xd0,0x00,0x00]
+
+v_min_num_f64_e64 v[5:6], vcc, ttmp[14:15]
+// GFX12: encoding: [0x05,0x00,0x0d,0xd5,0x6a,0xf4,0x00,0x00]
+
+v_min_num_f64_e64 v[5:6], ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x0d,0xd5,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_min_num_f64_e64 v[5:6], -|exec|, src_scc
+// GFX12: encoding: [0x05,0x01,0x0d,0xd5,0x7e,0xfa,0x01,0x20]
+
+v_min_num_f64_e64 v[5:6], null, 0.5
+// GFX12: encoding: [0x05,0x00,0x0d,0xd5,0x7c,0xe0,0x01,0x00]
+
+v_min_num_f64_e64 v[5:6], -1, -1
+// GFX12: encoding: [0x05,0x00,0x0d,0xd5,0xc1,0x82,0x01,0x00]
+
+v_min_num_f64_e64 v[5:6], 0.5, null mul:2
+// GFX12: encoding: [0x05,0x00,0x0d,0xd5,0xf0,0xf8,0x00,0x08]
+
+v_min_num_f64_e64 v[5:6], -|src_scc|, -|exec| mul:4
+// GFX12: encoding: [0x05,0x03,0x0d,0xd5,0xfd,0xfc,0x00,0x70]
+
+v_min_num_f64_e64 v[254:255], 0xaf123456, -|vcc| clamp div:2
+// GFX12: encoding: [0xfe,0x82,0x0d,0xd5,0xff,0xd4,0x00,0x58,0x56,0x34,0x12,0xaf]
+
+v_min_i32_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x11,0xd5,0x01,0x05,0x02,0x00]
+
+v_min_i32_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x11,0xd5,0xff,0xff,0x03,0x00]
+
+v_min_i32_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x11,0xd5,0x01,0x04,0x00,0x00]
+
+v_min_i32_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x11,0xd5,0x69,0xd2,0x00,0x00]
+
+v_min_i32_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x11,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_min_i32_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x11,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_min_i32_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x11,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_min_i32_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x11,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_min_i32_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x11,0xd5,0x7e,0x82,0x01,0x00]
+
+v_min_i32_e64 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x11,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_min_i32_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x11,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_min_i32_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x11,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_min_i32_e64 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x11,0xd5,0xf0,0xfa,0x00,0x00]
+
+v_min_i32_e64 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x11,0xd5,0xfd,0xd4,0x00,0x00]
+
+v_min_i32_e64 v255, 0xaf123456, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x11,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_min_u32_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x13,0xd5,0x01,0x05,0x02,0x00]
+
+v_min_u32_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x13,0xd5,0xff,0xff,0x03,0x00]
+
+v_min_u32_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x13,0xd5,0x01,0x04,0x00,0x00]
+
+v_min_u32_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x13,0xd5,0x69,0xd2,0x00,0x00]
+
+v_min_u32_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x13,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_min_u32_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x13,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_min_u32_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x13,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_min_u32_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x13,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_min_u32_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x13,0xd5,0x7e,0x82,0x01,0x00]
+
+v_min_u32_e64 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x13,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_min_u32_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x13,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_min_u32_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x13,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_min_u32_e64 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x13,0xd5,0xf0,0xfa,0x00,0x00]
+
+v_min_u32_e64 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x13,0xd5,0xfd,0xd4,0x00,0x00]
+
+v_min_u32_e64 v255, 0xaf123456, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x13,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_mul_dx9_zero_f32_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x07,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_dx9_zero_f32_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x07,0xd5,0xff,0xff,0x03,0x00]
+
+v_mul_dx9_zero_f32_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x07,0xd5,0x01,0x04,0x00,0x00]
+
+v_mul_dx9_zero_f32_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x07,0xd5,0x69,0xd2,0x00,0x00]
+
+v_mul_dx9_zero_f32_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x07,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_mul_dx9_zero_f32_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x07,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_mul_dx9_zero_f32_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x07,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_mul_dx9_zero_f32_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x07,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_mul_dx9_zero_f32_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x07,0xd5,0x7e,0x82,0x01,0x00]
+
+v_mul_dx9_zero_f32_e64 v5, |exec_hi|, null
+// GFX12: encoding: [0x05,0x01,0x07,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_mul_dx9_zero_f32_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x07,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_mul_dx9_zero_f32_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x07,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_mul_dx9_zero_f32_e64 v5, 0.5, -m0 mul:2
+// GFX12: encoding: [0x05,0x00,0x07,0xd5,0xf0,0xfa,0x00,0x48]
+
+v_mul_dx9_zero_f32_e64 v5, -src_scc, |vcc_lo| mul:4
+// GFX12: encoding: [0x05,0x02,0x07,0xd5,0xfd,0xd4,0x00,0x30]
+
+v_mul_dx9_zero_f32_e64 v255, -|0xaf123456|, -|vcc_hi| clamp div:2
+// GFX12: encoding: [0xff,0x83,0x07,0xd5,0xff,0xd6,0x00,0x78,0x56,0x34,0x12,0xaf]
+
+v_mul_f16_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x35,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_f16_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x35,0xd5,0xff,0xff,0x03,0x00]
+
+v_mul_f16_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x35,0xd5,0x01,0x04,0x00,0x00]
+
+v_mul_f16_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x35,0xd5,0x69,0xd2,0x00,0x00]
+
+v_mul_f16_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x35,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_mul_f16_e64 v5, vcc_hi, 0xfe0b
+// GFX12: encoding: [0x05,0x00,0x35,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_mul_f16_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x35,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_mul_f16_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x35,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_mul_f16_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x35,0xd5,0x7e,0x82,0x01,0x00]
+
+v_mul_f16_e64 v5, |exec_hi|, null
+// GFX12: encoding: [0x05,0x01,0x35,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_mul_f16_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x35,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_mul_f16_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x35,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_mul_f16_e64 v5, 0.5, -m0 mul:2
+// GFX12: encoding: [0x05,0x00,0x35,0xd5,0xf0,0xfa,0x00,0x48]
+
+v_mul_f16_e64 v5, -src_scc, |vcc_lo| mul:4
+// GFX12: encoding: [0x05,0x02,0x35,0xd5,0xfd,0xd4,0x00,0x30]
+
+v_mul_f16_e64 v255, -|0xfe0b|, -|vcc_hi| clamp div:2
+// GFX12: encoding: [0xff,0x83,0x35,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x08,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_f32_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x08,0xd5,0xff,0xff,0x03,0x00]
+
+v_mul_f32_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x08,0xd5,0x01,0x04,0x00,0x00]
+
+v_mul_f32_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x08,0xd5,0x69,0xd2,0x00,0x00]
+
+v_mul_f32_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x08,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_mul_f32_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x08,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_mul_f32_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x08,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_mul_f32_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x08,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_mul_f32_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x08,0xd5,0x7e,0x82,0x01,0x00]
+
+v_mul_f32_e64 v5, |exec_hi|, null
+// GFX12: encoding: [0x05,0x01,0x08,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_mul_f32_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x08,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_mul_f32_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x08,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_mul_f32_e64 v5, 0.5, -m0 mul:2
+// GFX12: encoding: [0x05,0x00,0x08,0xd5,0xf0,0xfa,0x00,0x48]
+
+v_mul_f32_e64 v5, -src_scc, |vcc_lo| mul:4
+// GFX12: encoding: [0x05,0x02,0x08,0xd5,0xfd,0xd4,0x00,0x30]
+
+v_mul_f32_e64 v255, -|0xaf123456|, -|vcc_hi| clamp div:2
+// GFX12: encoding: [0xff,0x83,0x08,0xd5,0xff,0xd6,0x00,0x78,0x56,0x34,0x12,0xaf]
+
+v_mul_f64_e64 v[5:6], v[2:3], v[4:5]
+// GFX12: encoding: [0x05,0x00,0x06,0xd5,0x02,0x09,0x02,0x00]
+
+v_mul_f64_e64 v[5:6], v[104:105], v[104:105]
+// GFX12: encoding: [0x05,0x00,0x06,0xd5,0x68,0xd1,0x02,0x00]
+
+v_mul_f64_e64 v[5:6], s[2:3], s[4:5]
+// GFX12: encoding: [0x05,0x00,0x06,0xd5,0x02,0x08,0x00,0x00]
+
+v_mul_f64_e64 v[5:6], s[104:105], s[104:105]
+// GFX12: encoding: [0x05,0x00,0x06,0xd5,0x68,0xd0,0x00,0x00]
+
+v_mul_f64_e64 v[5:6], vcc, ttmp[14:15]
+// GFX12: encoding: [0x05,0x00,0x06,0xd5,0x6a,0xf4,0x00,0x00]
+
+v_mul_f64_e64 v[5:6], ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x06,0xd5,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_mul_f64_e64 v[5:6], -|exec|, src_scc
+// GFX12: encoding: [0x05,0x01,0x06,0xd5,0x7e,0xfa,0x01,0x20]
+
+v_mul_f64_e64 v[5:6], null, 0.5
+// GFX12: encoding: [0x05,0x00,0x06,0xd5,0x7c,0xe0,0x01,0x00]
+
+v_mul_f64_e64 v[5:6], -1, -1
+// GFX12: encoding: [0x05,0x00,0x06,0xd5,0xc1,0x82,0x01,0x00]
+
+v_mul_f64_e64 v[5:6], 0.5, null mul:2
+// GFX12: encoding: [0x05,0x00,0x06,0xd5,0xf0,0xf8,0x00,0x08]
+
+v_mul_f64_e64 v[5:6], -|src_scc|, -|exec| mul:4
+// GFX12: encoding: [0x05,0x03,0x06,0xd5,0xfd,0xfc,0x00,0x70]
+
+v_mul_f64_e64 v[254:255], 0xaf123456, -|vcc| clamp div:2
+// GFX12: encoding: [0xfe,0x82,0x06,0xd5,0xff,0xd4,0x00,0x58,0x56,0x34,0x12,0xaf]
+
+v_mul_hi_i32_i24_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x0a,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x0a,0xd5,0xff,0xff,0x03,0x00]
+
+v_mul_hi_i32_i24_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x0a,0xd5,0x01,0x04,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x0a,0xd5,0x69,0xd2,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x0a,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x0a,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_mul_hi_i32_i24_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x0a,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_mul_hi_i32_i24_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x0a,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_mul_hi_i32_i24_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x0a,0xd5,0x7e,0x82,0x01,0x00]
+
+v_mul_hi_i32_i24_e64 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x0a,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x0a,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x0a,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x0a,0xd5,0xf0,0xfa,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x0a,0xd5,0xfd,0xd4,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v255, 0xaf123456, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x0a,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_mul_hi_u32_u24_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x0c,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x0c,0xd5,0xff,0xff,0x03,0x00]
+
+v_mul_hi_u32_u24_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x0c,0xd5,0x01,0x04,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x0c,0xd5,0x69,0xd2,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x0c,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x0c,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_mul_hi_u32_u24_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x0c,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_mul_hi_u32_u24_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x0c,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_mul_hi_u32_u24_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x0c,0xd5,0x7e,0x82,0x01,0x00]
+
+v_mul_hi_u32_u24_e64 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x0c,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x0c,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x0c,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x0c,0xd5,0xf0,0xfa,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x0c,0xd5,0xfd,0xd4,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v255, 0xaf123456, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x0c,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_mul_i32_i24_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x09,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x09,0xd5,0xff,0xff,0x03,0x00]
+
+v_mul_i32_i24_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x09,0xd5,0x01,0x04,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x09,0xd5,0x69,0xd2,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x09,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x09,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_mul_i32_i24_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x09,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_mul_i32_i24_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x09,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_mul_i32_i24_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x09,0xd5,0x7e,0x82,0x01,0x00]
+
+v_mul_i32_i24_e64 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x09,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x09,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x09,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x09,0xd5,0xf0,0xfa,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x09,0xd5,0xfd,0xd4,0x00,0x00]
+
+v_mul_i32_i24_e64 v255, 0xaf123456, vcc_hi clamp
+// GFX12: encoding: [0xff,0x80,0x09,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_mul_legacy_f32_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x07,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x07,0xd5,0xff,0xff,0x03,0x00]
+
+v_mul_legacy_f32_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x07,0xd5,0x01,0x04,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x07,0xd5,0x69,0xd2,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x07,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x07,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_mul_legacy_f32_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x07,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_mul_legacy_f32_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x07,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_mul_legacy_f32_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x07,0xd5,0x7e,0x82,0x01,0x00]
+
+v_mul_legacy_f32_e64 v5, |exec_hi|, null
+// GFX12: encoding: [0x05,0x01,0x07,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x07,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x07,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, 0.5, -m0 mul:2
+// GFX12: encoding: [0x05,0x00,0x07,0xd5,0xf0,0xfa,0x00,0x48]
+
+v_mul_legacy_f32_e64 v5, -src_scc, |vcc_lo| mul:4
+// GFX12: encoding: [0x05,0x02,0x07,0xd5,0xfd,0xd4,0x00,0x30]
+
+v_mul_legacy_f32_e64 v255, -|0xaf123456|, -|vcc_hi| clamp div:2
+// GFX12: encoding: [0xff,0x83,0x07,0xd5,0xff,0xd6,0x00,0x78,0x56,0x34,0x12,0xaf]
+
+v_mul_u32_u24_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x0b,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x0b,0xd5,0xff,0xff,0x03,0x00]
+
+v_mul_u32_u24_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x0b,0xd5,0x01,0x04,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x0b,0xd5,0x69,0xd2,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x0b,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x0b,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_mul_u32_u24_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x0b,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x0b,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x0b,0xd5,0x7e,0x82,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x0b,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x0b,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x0b,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x0b,0xd5,0xf0,0xfa,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x0b,0xd5,0xfd,0xd4,0x00,0x00]
+
+v_mul_u32_u24_e64 v255, 0xaf123456, vcc_hi clamp
+// GFX12: encoding: [0xff,0x80,0x0b,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_or_b32_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x1c,0xd5,0x01,0x05,0x02,0x00]
+
+v_or_b32_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x1c,0xd5,0xff,0xff,0x03,0x00]
+
+v_or_b32_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x1c,0xd5,0x01,0x04,0x00,0x00]
+
+v_or_b32_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x1c,0xd5,0x69,0xd2,0x00,0x00]
+
+v_or_b32_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x1c,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_or_b32_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x1c,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_or_b32_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x1c,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_or_b32_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x1c,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_or_b32_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x1c,0xd5,0x7e,0x82,0x01,0x00]
+
+v_or_b32_e64 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x1c,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_or_b32_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x1c,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_or_b32_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x1c,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_or_b32_e64 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x1c,0xd5,0xf0,0xfa,0x00,0x00]
+
+v_or_b32_e64 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x1c,0xd5,0xfd,0xd4,0x00,0x00]
+
+v_or_b32_e64 v255, 0xaf123456, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x1c,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_sub_co_ci_u32_e64 v5, s6, v1, 0xaf123456, s3
+// W32: encoding: [0x05,0x06,0x21,0xd5,0x01,0xff,0x0d,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s6, v255, src_scc, s3
+// W32: encoding: [0x05,0x06,0x21,0xd5,0xff,0xfb,0x0d,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s6, s105, s105, s3
+// W32: encoding: [0x05,0x06,0x21,0xd5,0x69,0xd2,0x0c,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s6, vcc_lo, v2, s3
+// W32: encoding: [0x05,0x06,0x21,0xd5,0x6a,0x04,0x0e,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s6, vcc_hi, v255, s3
+// W32: encoding: [0x05,0x06,0x21,0xd5,0x6b,0xfe,0x0f,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s6, ttmp15, ttmp15, s3
+// W32: encoding: [0x05,0x06,0x21,0xd5,0x7b,0xf6,0x0c,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s6, m0, 0.5, s3
+// W32: encoding: [0x05,0x06,0x21,0xd5,0x7d,0xe0,0x0d,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s6, exec_lo, exec_lo, s3
+// W32: encoding: [0x05,0x06,0x21,0xd5,0x7e,0xfc,0x0c,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s6, exec_hi, -1, s3
+// W32: encoding: [0x05,0x06,0x21,0xd5,0x7f,0x82,0x0d,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s105, null, exec_hi, s105
+// W32: encoding: [0x05,0x69,0x21,0xd5,0x7c,0xfe,0xa4,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, vcc_lo, -1, m0, vcc_lo
+// W32: encoding: [0x05,0x6a,0x21,0xd5,0xc1,0xfa,0xa8,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, vcc_hi, 0.5, vcc_lo, vcc_hi
+// W32: encoding: [0x05,0x6b,0x21,0xd5,0xf0,0xd4,0xac,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, ttmp15, src_scc, null, ttmp15
+// W32: encoding: [0x05,0x7b,0x21,0xd5,0xfd,0xf8,0xec,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s[12:13], v1, 0xaf123456, s[6:7]
+// W64: encoding: [0x05,0x0c,0x21,0xd5,0x01,0xff,0x19,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s[12:13], v255, src_scc, s[6:7]
+// W64: encoding: [0x05,0x0c,0x21,0xd5,0xff,0xfb,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s[12:13], s105, s105, s[6:7]
+// W64: encoding: [0x05,0x0c,0x21,0xd5,0x69,0xd2,0x18,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s[12:13], vcc_lo, v2, s[6:7]
+// W64: encoding: [0x05,0x0c,0x21,0xd5,0x6a,0x04,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s[12:13], vcc_hi, v255, s[6:7]
+// W64: encoding: [0x05,0x0c,0x21,0xd5,0x6b,0xfe,0x1b,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s[12:13], ttmp15, ttmp15, s[6:7]
+// W64: encoding: [0x05,0x0c,0x21,0xd5,0x7b,0xf6,0x18,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s[12:13], m0, 0.5, s[6:7]
+// W64: encoding: [0x05,0x0c,0x21,0xd5,0x7d,0xe0,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s[12:13], exec_lo, exec_lo, s[6:7]
+// W64: encoding: [0x05,0x0c,0x21,0xd5,0x7e,0xfc,0x18,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s[12:13], exec_hi, -1, s[6:7]
+// W64: encoding: [0x05,0x0c,0x21,0xd5,0x7f,0x82,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s[12:13], null, exec_hi, s[6:7]
+// W64: encoding: [0x05,0x0c,0x21,0xd5,0x7c,0xfe,0x18,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s[104:105], -1, m0, s[104:105]
+// W64: encoding: [0x05,0x68,0x21,0xd5,0xc1,0xfa,0xa0,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, vcc, 0.5, vcc_lo, vcc
+// W64: encoding: [0x05,0x6a,0x21,0xd5,0xf0,0xd4,0xa8,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, ttmp[14:15], src_scc, null, ttmp[14:15]
+// W64: encoding: [0x05,0x7a,0x21,0xd5,0xfd,0xf8,0xe8,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v255, null, 0xaf123456, vcc_hi, null clamp
+// GFX12: encoding: [0xff,0xfc,0x21,0xd5,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_sub_f16_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x33,0xd5,0x01,0x05,0x02,0x00]
+
+v_sub_f16_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x33,0xd5,0xff,0xff,0x03,0x00]
+
+v_sub_f16_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x33,0xd5,0x01,0x04,0x00,0x00]
+
+v_sub_f16_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x33,0xd5,0x69,0xd2,0x00,0x00]
+
+v_sub_f16_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x33,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_sub_f16_e64 v5, vcc_hi, 0xfe0b
+// GFX12: encoding: [0x05,0x00,0x33,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_sub_f16_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x33,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_sub_f16_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x33,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_sub_f16_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x33,0xd5,0x7e,0x82,0x01,0x00]
+
+v_sub_f16_e64 v5, |exec_hi|, null
+// GFX12: encoding: [0x05,0x01,0x33,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_sub_f16_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x33,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_sub_f16_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x33,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_sub_f16_e64 v5, 0.5, -m0 mul:2
+// GFX12: encoding: [0x05,0x00,0x33,0xd5,0xf0,0xfa,0x00,0x48]
+
+v_sub_f16_e64 v5, -src_scc, |vcc_lo| mul:4
+// GFX12: encoding: [0x05,0x02,0x33,0xd5,0xfd,0xd4,0x00,0x30]
+
+v_sub_f16_e64 v255, -|0xfe0b|, -|vcc_hi| clamp div:2
+// GFX12: encoding: [0xff,0x83,0x33,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x04,0xd5,0x01,0x05,0x02,0x00]
+
+v_sub_f32_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x04,0xd5,0xff,0xff,0x03,0x00]
+
+v_sub_f32_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x04,0xd5,0x01,0x04,0x00,0x00]
+
+v_sub_f32_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x04,0xd5,0x69,0xd2,0x00,0x00]
+
+v_sub_f32_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x04,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_sub_f32_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x04,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_sub_f32_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x04,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_sub_f32_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x04,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_sub_f32_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x04,0xd5,0x7e,0x82,0x01,0x00]
+
+v_sub_f32_e64 v5, |exec_hi|, null
+// GFX12: encoding: [0x05,0x01,0x04,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_sub_f32_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x04,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_sub_f32_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x04,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_sub_f32_e64 v5, 0.5, -m0 mul:2
+// GFX12: encoding: [0x05,0x00,0x04,0xd5,0xf0,0xfa,0x00,0x48]
+
+v_sub_f32_e64 v5, -src_scc, |vcc_lo| mul:4
+// GFX12: encoding: [0x05,0x02,0x04,0xd5,0xfd,0xd4,0x00,0x30]
+
+v_sub_f32_e64 v255, -|0xaf123456|, -|vcc_hi| clamp div:2
+// GFX12: encoding: [0xff,0x83,0x04,0xd5,0xff,0xd6,0x00,0x78,0x56,0x34,0x12,0xaf]
+
+v_sub_nc_u32_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x26,0xd5,0x01,0x05,0x02,0x00]
+
+v_sub_nc_u32_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x26,0xd5,0xff,0xff,0x03,0x00]
+
+v_sub_nc_u32_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x26,0xd5,0x01,0x04,0x00,0x00]
+
+v_sub_nc_u32_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x26,0xd5,0x69,0xd2,0x00,0x00]
+
+v_sub_nc_u32_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x26,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_sub_nc_u32_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x26,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_sub_nc_u32_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x26,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_sub_nc_u32_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x26,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_sub_nc_u32_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x26,0xd5,0x7e,0x82,0x01,0x00]
+
+v_sub_nc_u32_e64 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x26,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_sub_nc_u32_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x26,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_sub_nc_u32_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x26,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_sub_nc_u32_e64 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x26,0xd5,0xf0,0xfa,0x00,0x00]
+
+v_sub_nc_u32_e64 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x26,0xd5,0xfd,0xd4,0x00,0x00]
+
+v_sub_nc_u32_e64 v255, 0xaf123456, vcc_hi clamp
+// GFX12: encoding: [0xff,0x80,0x26,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_subrev_co_ci_u32_e64 v5, s6, v1, 0xaf123456, s3
+// W32: encoding: [0x05,0x06,0x22,0xd5,0x01,0xff,0x0d,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s6, v255, src_scc, s3
+// W32: encoding: [0x05,0x06,0x22,0xd5,0xff,0xfb,0x0d,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s6, s105, s105, s3
+// W32: encoding: [0x05,0x06,0x22,0xd5,0x69,0xd2,0x0c,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s6, vcc_lo, v2, s3
+// W32: encoding: [0x05,0x06,0x22,0xd5,0x6a,0x04,0x0e,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s6, vcc_hi, v255, s3
+// W32: encoding: [0x05,0x06,0x22,0xd5,0x6b,0xfe,0x0f,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s6, ttmp15, ttmp15, s3
+// W32: encoding: [0x05,0x06,0x22,0xd5,0x7b,0xf6,0x0c,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s6, m0, 0.5, s3
+// W32: encoding: [0x05,0x06,0x22,0xd5,0x7d,0xe0,0x0d,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s6, exec_lo, exec_lo, s3
+// W32: encoding: [0x05,0x06,0x22,0xd5,0x7e,0xfc,0x0c,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s6, exec_hi, -1, s3
+// W32: encoding: [0x05,0x06,0x22,0xd5,0x7f,0x82,0x0d,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s105, null, exec_hi, s105
+// W32: encoding: [0x05,0x69,0x22,0xd5,0x7c,0xfe,0xa4,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, vcc_lo, -1, m0, vcc_lo
+// W32: encoding: [0x05,0x6a,0x22,0xd5,0xc1,0xfa,0xa8,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, vcc_hi, 0.5, vcc_lo, vcc_hi
+// W32: encoding: [0x05,0x6b,0x22,0xd5,0xf0,0xd4,0xac,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, ttmp15, src_scc, null, ttmp15
+// W32: encoding: [0x05,0x7b,0x22,0xd5,0xfd,0xf8,0xec,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s[12:13], v1, 0xaf123456, s[6:7]
+// W64: encoding: [0x05,0x0c,0x22,0xd5,0x01,0xff,0x19,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s[12:13], v255, src_scc, s[6:7]
+// W64: encoding: [0x05,0x0c,0x22,0xd5,0xff,0xfb,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s[12:13], s105, s105, s[6:7]
+// W64: encoding: [0x05,0x0c,0x22,0xd5,0x69,0xd2,0x18,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s[12:13], vcc_lo, v2, s[6:7]
+// W64: encoding: [0x05,0x0c,0x22,0xd5,0x6a,0x04,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s[12:13], vcc_hi, v255, s[6:7]
+// W64: encoding: [0x05,0x0c,0x22,0xd5,0x6b,0xfe,0x1b,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s[12:13], ttmp15, ttmp15, s[6:7]
+// W64: encoding: [0x05,0x0c,0x22,0xd5,0x7b,0xf6,0x18,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s[12:13], m0, 0.5, s[6:7]
+// W64: encoding: [0x05,0x0c,0x22,0xd5,0x7d,0xe0,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s[12:13], exec_lo, exec_lo, s[6:7]
+// W64: encoding: [0x05,0x0c,0x22,0xd5,0x7e,0xfc,0x18,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s[12:13], exec_hi, -1, s[6:7]
+// W64: encoding: [0x05,0x0c,0x22,0xd5,0x7f,0x82,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s[12:13], null, exec_hi, s[6:7]
+// W64: encoding: [0x05,0x0c,0x22,0xd5,0x7c,0xfe,0x18,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s[104:105], -1, m0, s[104:105]
+// W64: encoding: [0x05,0x68,0x22,0xd5,0xc1,0xfa,0xa0,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, vcc, 0.5, vcc_lo, vcc
+// W64: encoding: [0x05,0x6a,0x22,0xd5,0xf0,0xd4,0xa8,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, ttmp[14:15], src_scc, null, ttmp[14:15]
+// W64: encoding: [0x05,0x7a,0x22,0xd5,0xfd,0xf8,0xe8,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v255, null, 0xaf123456, vcc_hi, null clamp
+// GFX12: encoding: [0xff,0xfc,0x22,0xd5,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+
+v_subrev_f16_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x34,0xd5,0x01,0x05,0x02,0x00]
+
+v_subrev_f16_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x34,0xd5,0xff,0xff,0x03,0x00]
+
+v_subrev_f16_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x34,0xd5,0x01,0x04,0x00,0x00]
+
+v_subrev_f16_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x34,0xd5,0x69,0xd2,0x00,0x00]
+
+v_subrev_f16_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x34,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_subrev_f16_e64 v5, vcc_hi, 0xfe0b
+// GFX12: encoding: [0x05,0x00,0x34,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_subrev_f16_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x34,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_subrev_f16_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x34,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_subrev_f16_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x34,0xd5,0x7e,0x82,0x01,0x00]
+
+v_subrev_f16_e64 v5, |exec_hi|, null
+// GFX12: encoding: [0x05,0x01,0x34,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_subrev_f16_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x34,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_subrev_f16_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x34,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_subrev_f16_e64 v5, 0.5, -m0 mul:2
+// GFX12: encoding: [0x05,0x00,0x34,0xd5,0xf0,0xfa,0x00,0x48]
+
+v_subrev_f16_e64 v5, -src_scc, |vcc_lo| mul:4
+// GFX12: encoding: [0x05,0x02,0x34,0xd5,0xfd,0xd4,0x00,0x30]
+
+v_subrev_f16_e64 v255, -|0xfe0b|, -|vcc_hi| clamp div:2
+// GFX12: encoding: [0xff,0x83,0x34,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x05,0xd5,0x01,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x05,0xd5,0xff,0xff,0x03,0x00]
+
+v_subrev_f32_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x05,0xd5,0x01,0x04,0x00,0x00]
+
+v_subrev_f32_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x05,0xd5,0x69,0xd2,0x00,0x00]
+
+v_subrev_f32_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x05,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_subrev_f32_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x05,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_subrev_f32_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x05,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_subrev_f32_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x05,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_subrev_f32_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x05,0xd5,0x7e,0x82,0x01,0x00]
+
+v_subrev_f32_e64 v5, |exec_hi|, null
+// GFX12: encoding: [0x05,0x01,0x05,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_subrev_f32_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x05,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_subrev_f32_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x05,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_subrev_f32_e64 v5, 0.5, -m0 mul:2
+// GFX12: encoding: [0x05,0x00,0x05,0xd5,0xf0,0xfa,0x00,0x48]
+
+v_subrev_f32_e64 v5, -src_scc, |vcc_lo| mul:4
+// GFX12: encoding: [0x05,0x02,0x05,0xd5,0xfd,0xd4,0x00,0x30]
+
+v_subrev_f32_e64 v255, -|0xaf123456|, -|vcc_hi| clamp div:2
+// GFX12: encoding: [0xff,0x83,0x05,0xd5,0xff,0xd6,0x00,0x78,0x56,0x34,0x12,0xaf]
+
+v_subrev_nc_u32_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x27,0xd5,0x01,0x05,0x02,0x00]
+
+v_subrev_nc_u32_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x27,0xd5,0xff,0xff,0x03,0x00]
+
+v_subrev_nc_u32_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x27,0xd5,0x01,0x04,0x00,0x00]
+
+v_subrev_nc_u32_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x27,0xd5,0x69,0xd2,0x00,0x00]
+
+v_subrev_nc_u32_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x27,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_subrev_nc_u32_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x27,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_subrev_nc_u32_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x27,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_subrev_nc_u32_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x27,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_subrev_nc_u32_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x27,0xd5,0x7e,0x82,0x01,0x00]
+
+v_subrev_nc_u32_e64 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x27,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_subrev_nc_u32_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x27,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_subrev_nc_u32_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x27,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_subrev_nc_u32_e64 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x27,0xd5,0xf0,0xfa,0x00,0x00]
+
+v_subrev_nc_u32_e64 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x27,0xd5,0xfd,0xd4,0x00,0x00]
+
+v_subrev_nc_u32_e64 v255, 0xaf123456, vcc_hi clamp
+// GFX12: encoding: [0xff,0x80,0x27,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_xnor_b32_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x1e,0xd5,0x01,0x05,0x02,0x00]
+
+v_xnor_b32_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x1e,0xd5,0xff,0xff,0x03,0x00]
+
+v_xnor_b32_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x1e,0xd5,0x01,0x04,0x00,0x00]
+
+v_xnor_b32_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x1e,0xd5,0x69,0xd2,0x00,0x00]
+
+v_xnor_b32_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x1e,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_xnor_b32_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x1e,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_xnor_b32_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x1e,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_xnor_b32_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x1e,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_xnor_b32_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x1e,0xd5,0x7e,0x82,0x01,0x00]
+
+v_xnor_b32_e64 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x1e,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_xnor_b32_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x1e,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_xnor_b32_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x1e,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_xnor_b32_e64 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x1e,0xd5,0xf0,0xfa,0x00,0x00]
+
+v_xnor_b32_e64 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x1e,0xd5,0xfd,0xd4,0x00,0x00]
+
+v_xnor_b32_e64 v255, 0xaf123456, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x1e,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_xor_b32_e64 v5, v1, v2
+// GFX12: encoding: [0x05,0x00,0x1d,0xd5,0x01,0x05,0x02,0x00]
+
+v_xor_b32_e64 v5, v255, v255
+// GFX12: encoding: [0x05,0x00,0x1d,0xd5,0xff,0xff,0x03,0x00]
+
+v_xor_b32_e64 v5, s1, s2
+// GFX12: encoding: [0x05,0x00,0x1d,0xd5,0x01,0x04,0x00,0x00]
+
+v_xor_b32_e64 v5, s105, s105
+// GFX12: encoding: [0x05,0x00,0x1d,0xd5,0x69,0xd2,0x00,0x00]
+
+v_xor_b32_e64 v5, vcc_lo, ttmp15
+// GFX12: encoding: [0x05,0x00,0x1d,0xd5,0x6a,0xf6,0x00,0x00]
+
+v_xor_b32_e64 v5, vcc_hi, 0xaf123456
+// GFX12: encoding: [0x05,0x00,0x1d,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_xor_b32_e64 v5, ttmp15, src_scc
+// GFX12: encoding: [0x05,0x00,0x1d,0xd5,0x7b,0xfa,0x01,0x00]
+
+v_xor_b32_e64 v5, m0, 0.5
+// GFX12: encoding: [0x05,0x00,0x1d,0xd5,0x7d,0xe0,0x01,0x00]
+
+v_xor_b32_e64 v5, exec_lo, -1
+// GFX12: encoding: [0x05,0x00,0x1d,0xd5,0x7e,0x82,0x01,0x00]
+
+v_xor_b32_e64 v5, exec_hi, null
+// GFX12: encoding: [0x05,0x00,0x1d,0xd5,0x7f,0xf8,0x00,0x00]
+
+v_xor_b32_e64 v5, null, exec_lo
+// GFX12: encoding: [0x05,0x00,0x1d,0xd5,0x7c,0xfc,0x00,0x00]
+
+v_xor_b32_e64 v5, -1, exec_hi
+// GFX12: encoding: [0x05,0x00,0x1d,0xd5,0xc1,0xfe,0x00,0x00]
+
+v_xor_b32_e64 v5, 0.5, m0
+// GFX12: encoding: [0x05,0x00,0x1d,0xd5,0xf0,0xfa,0x00,0x00]
+
+v_xor_b32_e64 v5, src_scc, vcc_lo
+// GFX12: encoding: [0x05,0x00,0x1d,0xd5,0xfd,0xd4,0x00,0x00]
+
+v_xor_b32_e64 v255, 0xaf123456, vcc_hi
+// GFX12: encoding: [0xff,0x00,0x1d,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s
new file mode 100644
index 000000000000..1b8eb5a7f169
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s
@@ -0,0 +1,1902 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W32 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W64 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+
+v_add_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 quad_perm:[3,2,1,0]
+// W32: [0x05,0x06,0x20,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 quad_perm:[0,1,2,3]
+// W32: [0x05,0x06,0x20,0xd5,0xfa,0x04,0x0e,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 row_mirror
+// W32: [0x05,0x06,0x20,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 row_half_mirror
+// W32: [0x05,0x06,0x20,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 row_shl:1
+// W32: [0x05,0x06,0x20,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 row_shl:15
+// W32: [0x05,0x06,0x20,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 row_shr:1
+// W32: [0x05,0x06,0x20,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 row_shr:15
+// W32: [0x05,0x06,0x20,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 row_ror:1
+// W32: [0x05,0x06,0x20,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, s105, v1, v2, s105 row_ror:15
+// W32: [0x05,0x69,0x20,0xd5,0xfa,0x04,0xa6,0x01,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, vcc_lo, v1, v2, vcc_hi row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x05,0x6a,0x20,0xd5,0xfa,0x04,0xae,0x01,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, vcc_hi, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x05,0x6b,0x20,0xd5,0xfa,0x04,0xaa,0x01,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, ttmp15, v1, v2, ttmp15 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x05,0x7b,0x20,0xd5,0xfa,0x04,0xee,0x01,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] quad_perm:[3,2,1,0]
+// W64: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] quad_perm:[0,1,2,3]
+// W64: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_mirror
+// W64: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_half_mirror
+// W64: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_shl:1
+// W64: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_shl:15
+// W64: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_shr:1
+// W64: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_shr:15
+// W64: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_ror:1
+// W64: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_ror:15
+// W64: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, s[104:105], v1, v2, s[104:105] row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x05,0x68,0x20,0xd5,0xfa,0x04,0xa2,0x01,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x05,0x6a,0x20,0xd5,0xfa,0x04,0xaa,0x01,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, ttmp[14:15], v1, v2, ttmp[14:15] row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x05,0x7a,0x20,0xd5,0xfa,0x04,0xea,0x01,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v255, null, v255, v255, null clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0xfc,0x20,0xd5,0xfa,0xfe,0xf3,0x01,0xff,0x6f,0x05,0x30]
+
+v_add_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_add_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_add_f16_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_add_f16_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_add_f16_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_add_f16_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_add_f16_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_add_f16_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_add_f16_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_add_f16_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_add_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_add_f16_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x01,0x32,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+
+v_add_f16_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x02,0x32,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x09,0x13]
+
+v_add_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x83,0x32,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x05,0x30]
+
+v_add_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_add_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_add_f32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_add_f32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_add_f32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_add_f32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_add_f32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_add_f32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_add_f32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_add_f32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_add_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_add_f32_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x01,0x03,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+
+v_add_f32_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x02,0x03,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x09,0x13]
+
+v_add_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x83,0x03,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x05,0x30]
+
+v_add_nc_u32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_add_nc_u32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_add_nc_u32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_add_nc_u32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_add_nc_u32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_add_nc_u32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_add_nc_u32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_add_nc_u32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_add_nc_u32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_add_nc_u32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_add_nc_u32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_add_nc_u32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_add_nc_u32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_add_nc_u32_e64_dpp v255, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x25,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_and_b32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_and_b32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_and_b32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_and_b32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_and_b32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_and_b32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_and_b32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_and_b32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_and_b32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_and_b32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_and_b32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_and_b32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_and_b32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_and_b32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x1b,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_ashrrev_i32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_ashrrev_i32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_ashrrev_i32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_ashrrev_i32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_ashrrev_i32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_ashrrev_i32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_ashrrev_i32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_ashrrev_i32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_ashrrev_i32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_ashrrev_i32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_ashrrev_i32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_ashrrev_i32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_ashrrev_i32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_ashrrev_i32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x1a,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cndmask_b32_e64_dpp v5, v1, v2, s3 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, v1, v2, s3 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x0e,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, v1, v2, s3 row_mirror
+// W32: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, v1, v2, s3 row_half_mirror
+// W32: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, v1, v2, s3 row_shl:1
+// W32: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, v1, v2, s3 row_shl:15
+// W32: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, v1, v2, s3 row_shr:1
+// W32: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, v1, v2, s3 row_shr:15
+// W32: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, v1, v2, s3 row_ror:1
+// W32: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, v1, v2, s105 row_ror:15
+// W32: [0x05,0x00,0x01,0xd5,0xfa,0x04,0xa6,0x01,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, v1, v2, vcc_hi row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x05,0x00,0x01,0xd5,0xfa,0x04,0xae,0x01,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, |v1|, -v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x05,0x01,0x01,0xd5,0xfa,0x04,0xaa,0x41,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, -v1, |v2|, ttmp15 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x05,0x02,0x01,0xd5,0xfa,0x04,0xee,0x21,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, v1, v2, s[6:7] quad_perm:[3,2,1,0]
+// W64: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, v1, v2, s[6:7] quad_perm:[0,1,2,3]
+// W64: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, v1, v2, s[6:7] row_mirror
+// W64: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, v1, v2, s[6:7] row_half_mirror
+// W64: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, v1, v2, s[6:7] row_shl:1
+// W64: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, v1, v2, s[6:7] row_shl:15
+// W64: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, v1, v2, s[6:7] row_shr:1
+// W64: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, v1, v2, s[6:7] row_shr:15
+// W64: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, v1, v2, s[6:7] row_ror:1
+// W64: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, v1, v2, s[6:7] row_ror:15
+// W64: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, v1, v2, s[104:105] row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x05,0x00,0x01,0xd5,0xfa,0x04,0xa2,0x01,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, |v1|, -v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x05,0x01,0x01,0xd5,0xfa,0x04,0xaa,0x41,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, -v1, |v2|, ttmp[14:15] row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x05,0x02,0x01,0xd5,0xfa,0x04,0xea,0x21,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v255, -|v255|, -|v255|, null row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x03,0x01,0xd5,0xfa,0xfe,0xf3,0x61,0xff,0x6f,0x05,0x30]
+
+v_cvt_pk_rtz_f16_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_pk_rtz_f16_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_pk_rtz_f16_f32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_pk_rtz_f16_f32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_pk_rtz_f16_f32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_pk_rtz_f16_f32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_pk_rtz_f16_f32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_pk_rtz_f16_f32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_pk_rtz_f16_f32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_pk_rtz_f16_f32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_pk_rtz_f16_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_pk_rtz_f16_f32_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x01,0x2f,0xd5,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cvt_pk_rtz_f16_f32_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x02,0x2f,0xd5,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cvt_pk_rtz_f16_f32_e64_dpp v255, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x83,0x2f,0xd5,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cvt_pkrtz_f16_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cvt_pkrtz_f16_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cvt_pkrtz_f16_f32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cvt_pkrtz_f16_f32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cvt_pkrtz_f16_f32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cvt_pkrtz_f16_f32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cvt_pkrtz_f16_f32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cvt_pkrtz_f16_f32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cvt_pkrtz_f16_f32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cvt_pkrtz_f16_f32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cvt_pkrtz_f16_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cvt_pkrtz_f16_f32_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x01,0x2f,0xd5,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cvt_pkrtz_f16_f32_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x02,0x2f,0xd5,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cvt_pkrtz_f16_f32_e64_dpp v255, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x83,0x2f,0xd5,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_ldexp_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_ldexp_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_ldexp_f16_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_ldexp_f16_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_ldexp_f16_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_ldexp_f16_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_ldexp_f16_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_ldexp_f16_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_ldexp_f16_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_ldexp_f16_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_ldexp_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_ldexp_f16_e64_dpp v5, v1, v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x08,0x01,0x5f,0x01,0x01]
+
+v_ldexp_f16_e64_dpp v5, v1, v2 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x10,0x01,0x60,0x09,0x13]
+
+v_ldexp_f16_e64_dpp v255, -|v255|, v255 clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x81,0x3b,0xd5,0xfa,0xfe,0x03,0x38,0xff,0x6f,0x05,0x30]
+
+v_lshlrev_b32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_lshlrev_b32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_lshlrev_b32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_lshlrev_b32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_lshlrev_b32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_lshlrev_b32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_lshlrev_b32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_lshlrev_b32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_lshlrev_b32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_lshlrev_b32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_lshlrev_b32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_lshlrev_b32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_lshlrev_b32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_lshlrev_b32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x18,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_lshrrev_b32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_lshrrev_b32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_lshrrev_b32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_lshrrev_b32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_lshrrev_b32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_lshrrev_b32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_lshrrev_b32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_lshrrev_b32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_lshrrev_b32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_lshrrev_b32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_lshrrev_b32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_lshrrev_b32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_lshrrev_b32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_lshrrev_b32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x19,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_max_num_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_max_num_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_max_num_f16_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_max_num_f16_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_max_num_f16_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_max_num_f16_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_max_num_f16_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_max_num_f16_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_max_num_f16_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_max_num_f16_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_max_num_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_max_num_f16_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x01,0x31,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+
+v_max_num_f16_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x02,0x31,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x09,0x13]
+
+v_max_num_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x83,0x31,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x05,0x30]
+
+v_max_num_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_max_num_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_max_num_f32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_max_num_f32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_max_num_f32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_max_num_f32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_max_num_f32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_max_num_f32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_max_num_f32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_max_num_f32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_max_num_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_max_num_f32_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x01,0x16,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+
+v_max_num_f32_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x02,0x16,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x09,0x13]
+
+v_max_num_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x83,0x16,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x05,0x30]
+
+v_max_i32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_max_i32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_max_i32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_max_i32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_max_i32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_max_i32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_max_i32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_max_i32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_max_i32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_max_i32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_max_i32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_max_i32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_max_i32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_max_i32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x12,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_max_u32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_max_u32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_max_u32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_max_u32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_max_u32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_max_u32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_max_u32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_max_u32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_max_u32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_max_u32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_max_u32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_max_u32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_max_u32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_max_u32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x14,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_min_num_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_min_num_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_min_num_f16_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_min_num_f16_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_min_num_f16_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_min_num_f16_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_min_num_f16_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_min_num_f16_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_min_num_f16_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_min_num_f16_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_min_num_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_min_num_f16_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x01,0x30,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+
+v_min_num_f16_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x02,0x30,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x09,0x13]
+
+v_min_num_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x83,0x30,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x05,0x30]
+
+v_min_num_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_min_num_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_min_num_f32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_min_num_f32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_min_num_f32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_min_num_f32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_min_num_f32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_min_num_f32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_min_num_f32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_min_num_f32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_min_num_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_min_num_f32_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x01,0x15,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+
+v_min_num_f32_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x02,0x15,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x09,0x13]
+
+v_min_num_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x83,0x15,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x05,0x30]
+
+v_min_i32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_min_i32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_min_i32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_min_i32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_min_i32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_min_i32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_min_i32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_min_i32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_min_i32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_min_i32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_min_i32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_min_i32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_min_i32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_min_i32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x11,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_min_u32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_min_u32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_min_u32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_min_u32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_min_u32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_min_u32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_min_u32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_min_u32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_min_u32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_min_u32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_min_u32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_min_u32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_min_u32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_min_u32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x13,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_mul_dx9_zero_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_mul_dx9_zero_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_mul_dx9_zero_f32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_mul_dx9_zero_f32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_mul_dx9_zero_f32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_mul_dx9_zero_f32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_mul_dx9_zero_f32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_mul_dx9_zero_f32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_mul_dx9_zero_f32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_mul_dx9_zero_f32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_mul_dx9_zero_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_mul_dx9_zero_f32_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x01,0x07,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+
+v_mul_dx9_zero_f32_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x02,0x07,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x09,0x13]
+
+v_mul_dx9_zero_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x83,0x07,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x05,0x30]
+
+v_mul_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_mul_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_mul_f16_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_mul_f16_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_mul_f16_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_mul_f16_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_mul_f16_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_mul_f16_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_mul_f16_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_mul_f16_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_mul_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_mul_f16_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x01,0x35,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+
+v_mul_f16_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x02,0x35,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x09,0x13]
+
+v_mul_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x83,0x35,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x05,0x30]
+
+v_mul_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_mul_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_mul_f32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_mul_f32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_mul_f32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_mul_f32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_mul_f32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_mul_f32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_mul_f32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_mul_f32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_mul_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_mul_f32_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x01,0x08,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+
+v_mul_f32_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x02,0x08,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x09,0x13]
+
+v_mul_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x83,0x08,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x05,0x30]
+
+v_mul_hi_i32_i24_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_mul_hi_i32_i24_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_mul_hi_i32_i24_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_mul_hi_i32_i24_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_mul_hi_i32_i24_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_mul_hi_i32_i24_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_mul_hi_i32_i24_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_mul_hi_i32_i24_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_mul_hi_i32_i24_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_mul_hi_i32_i24_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_mul_hi_i32_i24_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_mul_hi_i32_i24_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_mul_hi_i32_i24_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_mul_hi_i32_i24_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x0a,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_mul_hi_u32_u24_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_mul_hi_u32_u24_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_mul_hi_u32_u24_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_mul_hi_u32_u24_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_mul_hi_u32_u24_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_mul_hi_u32_u24_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_mul_hi_u32_u24_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_mul_hi_u32_u24_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_mul_hi_u32_u24_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_mul_hi_u32_u24_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_mul_hi_u32_u24_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_mul_hi_u32_u24_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_mul_hi_u32_u24_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_mul_hi_u32_u24_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x0c,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_mul_i32_i24_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_mul_i32_i24_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_mul_i32_i24_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_mul_i32_i24_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_mul_i32_i24_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_mul_i32_i24_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_mul_i32_i24_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_mul_i32_i24_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_mul_i32_i24_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_mul_i32_i24_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_mul_i32_i24_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_mul_i32_i24_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_mul_i32_i24_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_mul_i32_i24_e64_dpp v255, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x09,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_mul_legacy_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_mul_legacy_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_mul_legacy_f32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_mul_legacy_f32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_mul_legacy_f32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_mul_legacy_f32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_mul_legacy_f32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_mul_legacy_f32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_mul_legacy_f32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_mul_legacy_f32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_mul_legacy_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_mul_legacy_f32_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x01,0x07,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+
+v_mul_legacy_f32_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x02,0x07,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x09,0x13]
+
+v_mul_legacy_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x83,0x07,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x05,0x30]
+
+v_mul_u32_u24_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_mul_u32_u24_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_mul_u32_u24_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_mul_u32_u24_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_mul_u32_u24_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_mul_u32_u24_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_mul_u32_u24_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_mul_u32_u24_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_mul_u32_u24_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_mul_u32_u24_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_mul_u32_u24_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_mul_u32_u24_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_mul_u32_u24_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_mul_u32_u24_e64_dpp v255, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x0b,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_or_b32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_or_b32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_or_b32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_or_b32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_or_b32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_or_b32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_or_b32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_or_b32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_or_b32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_or_b32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_or_b32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_or_b32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_or_b32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_or_b32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x1c,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_sub_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 quad_perm:[3,2,1,0]
+// W32: [0x05,0x06,0x21,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 quad_perm:[0,1,2,3]
+// W32: [0x05,0x06,0x21,0xd5,0xfa,0x04,0x0e,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 row_mirror
+// W32: [0x05,0x06,0x21,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 row_half_mirror
+// W32: [0x05,0x06,0x21,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 row_shl:1
+// W32: [0x05,0x06,0x21,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 row_shl:15
+// W32: [0x05,0x06,0x21,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 row_shr:1
+// W32: [0x05,0x06,0x21,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 row_shr:15
+// W32: [0x05,0x06,0x21,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 row_ror:1
+// W32: [0x05,0x06,0x21,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, s105, v1, v2, s105 row_ror:15
+// W32: [0x05,0x69,0x21,0xd5,0xfa,0x04,0xa6,0x01,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, vcc_lo, v1, v2, vcc_hi row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x05,0x6a,0x21,0xd5,0xfa,0x04,0xae,0x01,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, vcc_hi, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x05,0x6b,0x21,0xd5,0xfa,0x04,0xaa,0x01,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, ttmp15, v1, v2, ttmp15 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x05,0x7b,0x21,0xd5,0xfa,0x04,0xee,0x01,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] quad_perm:[3,2,1,0]
+// W64: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] quad_perm:[0,1,2,3]
+// W64: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_mirror
+// W64: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_half_mirror
+// W64: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_shl:1
+// W64: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_shl:15
+// W64: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_shr:1
+// W64: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_shr:15
+// W64: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_ror:1
+// W64: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_ror:15
+// W64: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, s[104:105], v1, v2, s[104:105] row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x05,0x68,0x21,0xd5,0xfa,0x04,0xa2,0x01,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x05,0x6a,0x21,0xd5,0xfa,0x04,0xaa,0x01,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, ttmp[14:15], v1, v2, ttmp[14:15] row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x05,0x7a,0x21,0xd5,0xfa,0x04,0xea,0x01,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v255, null, v255, v255, null clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0xfc,0x21,0xd5,0xfa,0xfe,0xf3,0x01,0xff,0x6f,0x05,0x30]
+
+v_sub_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_sub_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_sub_f16_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_sub_f16_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_sub_f16_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_sub_f16_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_sub_f16_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_sub_f16_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_sub_f16_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_sub_f16_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_sub_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_sub_f16_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x01,0x33,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+
+v_sub_f16_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x02,0x33,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x09,0x13]
+
+v_sub_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x83,0x33,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x05,0x30]
+
+v_sub_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_sub_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_sub_f32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_sub_f32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_sub_f32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_sub_f32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_sub_f32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_sub_f32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_sub_f32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_sub_f32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_sub_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_sub_f32_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x01,0x04,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+
+v_sub_f32_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x02,0x04,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x09,0x13]
+
+v_sub_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x83,0x04,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x05,0x30]
+
+v_sub_nc_u32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_sub_nc_u32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_sub_nc_u32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_sub_nc_u32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_sub_nc_u32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_sub_nc_u32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_sub_nc_u32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_sub_nc_u32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_sub_nc_u32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_sub_nc_u32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_sub_nc_u32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_sub_nc_u32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_sub_nc_u32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_sub_nc_u32_e64_dpp v255, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x26,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_subrev_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 quad_perm:[3,2,1,0]
+// W32: [0x05,0x06,0x22,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 quad_perm:[0,1,2,3]
+// W32: [0x05,0x06,0x22,0xd5,0xfa,0x04,0x0e,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 row_mirror
+// W32: [0x05,0x06,0x22,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 row_half_mirror
+// W32: [0x05,0x06,0x22,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 row_shl:1
+// W32: [0x05,0x06,0x22,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 row_shl:15
+// W32: [0x05,0x06,0x22,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 row_shr:1
+// W32: [0x05,0x06,0x22,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 row_shr:15
+// W32: [0x05,0x06,0x22,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 row_ror:1
+// W32: [0x05,0x06,0x22,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, s105, v1, v2, s105 row_ror:15
+// W32: [0x05,0x69,0x22,0xd5,0xfa,0x04,0xa6,0x01,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, vcc_lo, v1, v2, vcc_hi row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x05,0x6a,0x22,0xd5,0xfa,0x04,0xae,0x01,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, vcc_hi, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x05,0x6b,0x22,0xd5,0xfa,0x04,0xaa,0x01,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, ttmp15, v1, v2, ttmp15 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x05,0x7b,0x22,0xd5,0xfa,0x04,0xee,0x01,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] quad_perm:[3,2,1,0]
+// W64: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] quad_perm:[0,1,2,3]
+// W64: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_mirror
+// W64: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_half_mirror
+// W64: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_shl:1
+// W64: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_shl:15
+// W64: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_shr:1
+// W64: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_shr:15
+// W64: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_ror:1
+// W64: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_ror:15
+// W64: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, s[104:105], v1, v2, s[104:105] row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x05,0x68,0x22,0xd5,0xfa,0x04,0xa2,0x01,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x05,0x6a,0x22,0xd5,0xfa,0x04,0xaa,0x01,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, ttmp[14:15], v1, v2, ttmp[14:15] row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x05,0x7a,0x22,0xd5,0xfa,0x04,0xea,0x01,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v255, null, v255, v255, null clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0xfc,0x22,0xd5,0xfa,0xfe,0xf3,0x01,0xff,0x6f,0x05,0x30]
+
+v_subrev_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_subrev_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_subrev_f16_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_subrev_f16_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_subrev_f16_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_subrev_f16_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_subrev_f16_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_subrev_f16_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_subrev_f16_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_subrev_f16_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_subrev_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_subrev_f16_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x01,0x34,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+
+v_subrev_f16_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x02,0x34,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x09,0x13]
+
+v_subrev_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x83,0x34,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x05,0x30]
+
+v_subrev_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_subrev_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_subrev_f32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_subrev_f32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_subrev_f32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_subrev_f32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_subrev_f32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_subrev_f32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_subrev_f32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_subrev_f32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_subrev_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_subrev_f32_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x01,0x05,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+
+v_subrev_f32_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x02,0x05,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x09,0x13]
+
+v_subrev_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x83,0x05,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x05,0x30]
+
+v_subrev_nc_u32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_subrev_nc_u32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_subrev_nc_u32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_subrev_nc_u32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_subrev_nc_u32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_subrev_nc_u32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_subrev_nc_u32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_subrev_nc_u32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_subrev_nc_u32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_subrev_nc_u32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_subrev_nc_u32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_subrev_nc_u32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_subrev_nc_u32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_subrev_nc_u32_e64_dpp v255, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x80,0x27,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_xnor_b32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_xnor_b32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_xnor_b32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_xnor_b32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_xnor_b32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_xnor_b32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_xnor_b32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_xnor_b32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_xnor_b32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_xnor_b32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_xnor_b32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_xnor_b32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_xnor_b32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_xnor_b32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x1e,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_xor_b32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_xor_b32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_xor_b32_e64_dpp v5, v1, v2 row_mirror
+// GFX12: [0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_xor_b32_e64_dpp v5, v1, v2 row_half_mirror
+// GFX12: [0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_xor_b32_e64_dpp v5, v1, v2 row_shl:1
+// GFX12: [0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_xor_b32_e64_dpp v5, v1, v2 row_shl:15
+// GFX12: [0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_xor_b32_e64_dpp v5, v1, v2 row_shr:1
+// GFX12: [0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_xor_b32_e64_dpp v5, v1, v2 row_shr:15
+// GFX12: [0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_xor_b32_e64_dpp v5, v1, v2 row_ror:1
+// GFX12: [0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_xor_b32_e64_dpp v5, v1, v2 row_ror:15
+// GFX12: [0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_xor_b32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_xor_b32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_xor_b32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_xor_b32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0xff,0x00,0x1d,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s
new file mode 100644
index 000000000000..cbe7d774cf62
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s
@@ -0,0 +1,526 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W32 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W64 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+
+v_add_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x06,0x20,0xd5,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, s105, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x69,0x20,0xd5,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, vcc_lo, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x6a,0x20,0xd5,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, vcc_hi, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x6b,0x20,0xd5,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, ttmp15, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x05,0x7b,0x20,0xd5,0xea,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x05,0x0c,0x20,0xd5,0xe9,0x04,0x1a,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, s[104:105], v1, v2, s[104:105] dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x05,0x68,0x20,0xd5,0xe9,0x04,0xa2,0x01,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x05,0x6a,0x20,0xd5,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v5, ttmp[14:15], v1, v2, ttmp[14:15] dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x05,0x7a,0x20,0xd5,0xea,0x04,0xea,0x01,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64_dpp v255, null, v255, v255, null clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0xfc,0x20,0xd5,0xe9,0xfe,0xf3,0x01,0xff,0x00,0x00,0x00]
+
+v_add_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x32,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_add_f16_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x32,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+
+v_add_f16_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x02,0x32,0xd5,0xea,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+
+v_add_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x83,0x32,0xd5,0xe9,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+
+v_add_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x03,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_add_f32_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x03,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+
+v_add_f32_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x02,0x03,0xd5,0xea,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+
+v_add_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x83,0x03,0xd5,0xe9,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+
+v_add_nc_u32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x25,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_add_nc_u32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x25,0xd5,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_add_nc_u32_e64_dpp v255, v255, v255 clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x25,0xd5,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_and_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1b,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_and_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x1b,0xd5,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_and_b32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x1b,0xd5,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_ashrrev_i32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1a,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_ashrrev_i32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x1a,0xd5,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_ashrrev_i32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x1a,0xd5,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cndmask_b32_e64_dpp v5, v1, v2, s3 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x01,0xd5,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x01,0xd5,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x01,0xd5,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, |v1|, -v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x01,0x01,0xd5,0xe9,0x04,0xaa,0x41,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, -v1, |v2|, ttmp15 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x05,0x02,0x01,0xd5,0xea,0x04,0xee,0x21,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, v1, v2, s[6:7] dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x05,0x00,0x01,0xd5,0xe9,0x04,0x1a,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, v1, v2, s[104:105] dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x05,0x00,0x01,0xd5,0xe9,0x04,0xa2,0x01,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, |v1|, -v2, vcc dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x05,0x01,0x01,0xd5,0xe9,0x04,0xaa,0x41,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v5, -v1, |v2|, ttmp[14:15] dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x05,0x02,0x01,0xd5,0xea,0x04,0xea,0x21,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64_dpp v255, -|v255|, -|v255|, null dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x03,0x01,0xd5,0xe9,0xfe,0xf3,0x61,0xff,0x00,0x00,0x00]
+
+v_cvt_pk_rtz_f16_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x2f,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_rtz_f16_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x2f,0xd5,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_rtz_f16_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x02,0x2f,0xd5,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cvt_pk_rtz_f16_f32_e64_dpp v255, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x83,0x2f,0xd5,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x2f,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cvt_pkrtz_f16_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x2f,0xd5,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cvt_pkrtz_f16_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x02,0x2f,0xd5,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cvt_pkrtz_f16_f32_e64_dpp v255, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x83,0x2f,0xd5,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_ldexp_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x3b,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_ldexp_f16_e64_dpp v5, v1, v2 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x3b,0xd5,0xe9,0x04,0x02,0x08,0x01,0x77,0x39,0x05]
+
+v_ldexp_f16_e64_dpp v5, v1, v2 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x3b,0xd5,0xea,0x04,0x02,0x10,0x01,0x77,0x39,0x05]
+
+v_ldexp_f16_e64_dpp v255, -|v255|, v255 clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x81,0x3b,0xd5,0xe9,0xfe,0x03,0x38,0xff,0x00,0x00,0x00]
+
+v_lshlrev_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x18,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_lshlrev_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x18,0xd5,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_lshlrev_b32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x18,0xd5,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_lshrrev_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x19,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_lshrrev_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x19,0xd5,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_lshrrev_b32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x19,0xd5,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_max_num_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x31,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_max_num_f16_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x31,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+
+v_max_num_f16_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x02,0x31,0xd5,0xea,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+
+v_max_num_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x83,0x31,0xd5,0xe9,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+
+v_max_num_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x16,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_max_num_f32_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x16,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+
+v_max_num_f32_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x02,0x16,0xd5,0xea,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+
+v_max_num_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x83,0x16,0xd5,0xe9,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+
+v_max_i32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x12,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_max_i32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x12,0xd5,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_max_i32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x12,0xd5,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_max_u32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x14,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_max_u32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x14,0xd5,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_max_u32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x14,0xd5,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_min_num_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x30,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_min_num_f16_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x30,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+
+v_min_num_f16_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x02,0x30,0xd5,0xea,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+
+v_min_num_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x83,0x30,0xd5,0xe9,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+
+v_min_num_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x15,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_min_num_f32_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x15,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+
+v_min_num_f32_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x02,0x15,0xd5,0xea,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+
+v_min_num_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x83,0x15,0xd5,0xe9,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+
+v_min_i32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x11,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_min_i32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x11,0xd5,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_min_i32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x11,0xd5,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_min_u32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x13,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_min_u32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x13,0xd5,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_min_u32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x13,0xd5,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_mul_dx9_zero_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x07,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_mul_dx9_zero_f32_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x07,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+
+v_mul_dx9_zero_f32_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x02,0x07,0xd5,0xea,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+
+v_mul_dx9_zero_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x83,0x07,0xd5,0xe9,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+
+v_mul_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x35,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_mul_f16_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x35,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+
+v_mul_f16_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x02,0x35,0xd5,0xea,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+
+v_mul_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x83,0x35,0xd5,0xe9,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+
+v_mul_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x08,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_mul_f32_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x08,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+
+v_mul_f32_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x02,0x08,0xd5,0xea,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+
+v_mul_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x83,0x08,0xd5,0xe9,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+
+v_mul_hi_i32_i24_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0a,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_mul_hi_i32_i24_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x0a,0xd5,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_mul_hi_i32_i24_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x0a,0xd5,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_mul_hi_u32_u24_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0c,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_mul_hi_u32_u24_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x0c,0xd5,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_mul_hi_u32_u24_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x0c,0xd5,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_mul_i32_i24_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x09,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_mul_i32_i24_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x09,0xd5,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_mul_i32_i24_e64_dpp v255, v255, v255 clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x09,0xd5,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_mul_legacy_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x07,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_mul_legacy_f32_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x07,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+
+v_mul_legacy_f32_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x02,0x07,0xd5,0xea,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+
+v_mul_legacy_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x83,0x07,0xd5,0xe9,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+
+v_mul_u32_u24_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x0b,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_mul_u32_u24_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x0b,0xd5,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_mul_u32_u24_e64_dpp v255, v255, v255 clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x0b,0xd5,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_or_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1c,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_or_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x1c,0xd5,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_or_b32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x1c,0xd5,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_sub_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x06,0x21,0xd5,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, s105, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x69,0x21,0xd5,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, vcc_lo, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x6a,0x21,0xd5,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, vcc_hi, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x6b,0x21,0xd5,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, ttmp15, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x05,0x7b,0x21,0xd5,0xea,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x05,0x0c,0x21,0xd5,0xe9,0x04,0x1a,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, s[104:105], v1, v2, s[104:105] dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x05,0x68,0x21,0xd5,0xe9,0x04,0xa2,0x01,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x05,0x6a,0x21,0xd5,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v5, ttmp[14:15], v1, v2, ttmp[14:15] dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x05,0x7a,0x21,0xd5,0xea,0x04,0xea,0x01,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64_dpp v255, null, v255, v255, null clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0xfc,0x21,0xd5,0xe9,0xfe,0xf3,0x01,0xff,0x00,0x00,0x00]
+
+v_sub_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x33,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_sub_f16_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x33,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+
+v_sub_f16_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x02,0x33,0xd5,0xea,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+
+v_sub_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x83,0x33,0xd5,0xe9,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+
+v_sub_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x04,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_sub_f32_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x04,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+
+v_sub_f32_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x02,0x04,0xd5,0xea,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+
+v_sub_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x83,0x04,0xd5,0xe9,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+
+v_sub_nc_u32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x26,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_sub_nc_u32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x26,0xd5,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_sub_nc_u32_e64_dpp v255, v255, v255 clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x26,0xd5,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_subrev_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x06,0x22,0xd5,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, s105, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x69,0x22,0xd5,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, vcc_lo, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x6a,0x22,0xd5,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, vcc_hi, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x6b,0x22,0xd5,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, ttmp15, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x05,0x7b,0x22,0xd5,0xea,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x05,0x0c,0x22,0xd5,0xe9,0x04,0x1a,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, s[104:105], v1, v2, s[104:105] dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x05,0x68,0x22,0xd5,0xe9,0x04,0xa2,0x01,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x05,0x6a,0x22,0xd5,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v5, ttmp[14:15], v1, v2, ttmp[14:15] dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x05,0x7a,0x22,0xd5,0xea,0x04,0xea,0x01,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64_dpp v255, null, v255, v255, null clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0xfc,0x22,0xd5,0xe9,0xfe,0xf3,0x01,0xff,0x00,0x00,0x00]
+
+v_subrev_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x34,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_subrev_f16_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x34,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+
+v_subrev_f16_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x02,0x34,0xd5,0xea,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+
+v_subrev_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x83,0x34,0xd5,0xe9,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+
+v_subrev_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x05,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_subrev_f32_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x01,0x05,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+
+v_subrev_f32_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x02,0x05,0xd5,0xea,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+
+v_subrev_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x83,0x05,0xd5,0xe9,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+
+v_subrev_nc_u32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x27,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_subrev_nc_u32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x27,0xd5,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_subrev_nc_u32_e64_dpp v255, v255, v255 clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x80,0x27,0xd5,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_xnor_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1e,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_xnor_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x1e,0xd5,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_xnor_b32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x1e,0xd5,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_xor_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x05,0x00,0x1d,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_xor_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x05,0x00,0x1d,0xd5,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_xor_b32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0xff,0x00,0x1d,0xd5,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s
new file mode 100644
index 000000000000..c674f120ec4d
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s
@@ -0,0 +1,8695 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W32 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W64 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+
+v_cmp_class_f16_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s5, v255, v2
+// W32: encoding: [0x05,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s5, s1, v2
+// W32: encoding: [0x05,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s5, s105, v255
+// W32: encoding: [0x05,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s5, vcc_lo, s2
+// W32: encoding: [0x05,0x00,0x7d,0xd4,0x6a,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s5, vcc_hi, s105
+// W32: encoding: [0x05,0x00,0x7d,0xd4,0x6b,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s5, ttmp15, ttmp15
+// W32: encoding: [0x05,0x00,0x7d,0xd4,0x7b,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s5, m0, src_scc
+// W32: encoding: [0x05,0x00,0x7d,0xd4,0x7d,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x7d,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s5, exec_hi, null
+// W32: encoding: [0x05,0x00,0x7d,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x7d,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x7d,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 vcc_hi, 0.5, m0
+// W32: encoding: [0x6b,0x00,0x7d,0xd4,0xf0,0xfa,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x7b,0x00,0x7d,0xd4,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], s105, v255
+// W64: encoding: [0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], vcc_lo, s2
+// W64: encoding: [0x0a,0x00,0x7d,0xd4,0x6a,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], vcc_hi, s105
+// W64: encoding: [0x0a,0x00,0x7d,0xd4,0x6b,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], ttmp15, ttmp15
+// W64: encoding: [0x0a,0x00,0x7d,0xd4,0x7b,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], m0, src_scc
+// W64: encoding: [0x0a,0x00,0x7d,0xd4,0x7d,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x7d,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], exec_hi, null
+// W64: encoding: [0x0a,0x00,0x7d,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x7d,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x7d,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 vcc, 0.5, m0
+// W64: encoding: [0x6a,0x00,0x7d,0xd4,0xf0,0xfa,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x7a,0x00,0x7d,0xd4,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 null, -|0xfe0b|, vcc_hi
+// GFX12: encoding: [0x7c,0x01,0x7d,0xd4,0xff,0xd6,0x00,0x20,0x0b,0xfe,0x00,0x00]
+
+v_cmp_class_f32_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x7e,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x7e,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x7e,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x7e,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x7e,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s5, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x00,0x7e,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x7e,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x7e,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x7e,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s5, exec_hi, null
+// W32: encoding: [0x05,0x00,0x7e,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x7e,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x7e,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 vcc_hi, 0.5, m0
+// W32: encoding: [0x6b,0x00,0x7e,0xd4,0xf0,0xfa,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x7b,0x00,0x7e,0xd4,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x7e,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x7e,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x7e,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x7e,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x7e,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], vcc_hi, 0xaf123456
+// W64: encoding: [0x0a,0x00,0x7e,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x7e,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x7e,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x7e,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], exec_hi, null
+// W64: encoding: [0x0a,0x00,0x7e,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x7e,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x7e,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 vcc, 0.5, m0
+// W64: encoding: [0x6a,0x00,0x7e,0xd4,0xf0,0xfa,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x7a,0x00,0x7e,0xd4,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 null, -|0xaf123456|, vcc_hi
+// GFX12: encoding: [0x7c,0x01,0x7e,0xd4,0xff,0xd6,0x00,0x20,0x56,0x34,0x12,0xaf]
+
+v_cmp_class_f64_e64 s5, v[1:2], v2
+// W32: encoding: [0x05,0x00,0x7f,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s5, v[1:2], v255
+// W32: encoding: [0x05,0x00,0x7f,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s5, v[1:2], s2
+// W32: encoding: [0x05,0x00,0x7f,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s5, v[1:2], s105
+// W32: encoding: [0x05,0x00,0x7f,0xd4,0x01,0xd3,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s5, v[254:255], ttmp15
+// W32: encoding: [0x05,0x00,0x7f,0xd4,0xfe,0xf7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s5, s[2:3], vcc_hi
+// W32: encoding: [0x05,0x00,0x7f,0xd4,0x02,0xd6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s5, s[104:105], vcc_lo
+// W32: encoding: [0x05,0x00,0x7f,0xd4,0x68,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s5, vcc, m0
+// W32: encoding: [0x05,0x00,0x7f,0xd4,0x6a,0xfa,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s5, ttmp[14:15], exec_hi
+// W32: encoding: [0x05,0x00,0x7f,0xd4,0x7a,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s5, exec, exec_lo
+// W32: encoding: [0x05,0x00,0x7f,0xd4,0x7e,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s105, null, null
+// W32: encoding: [0x69,0x00,0x7f,0xd4,0x7c,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 vcc_lo, -1, -1
+// W32: encoding: [0x6a,0x00,0x7f,0xd4,0xc1,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 vcc_hi, 0.5, 0.5
+// W32: encoding: [0x6b,0x00,0x7f,0xd4,0xf0,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 ttmp15, -|src_scc|, src_scc
+// W32: encoding: [0x7b,0x01,0x7f,0xd4,0xfd,0xfa,0x01,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], v2
+// W64: encoding: [0x0a,0x00,0x7f,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], v255
+// W64: encoding: [0x0a,0x00,0x7f,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], s2
+// W64: encoding: [0x0a,0x00,0x7f,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], s105
+// W64: encoding: [0x0a,0x00,0x7f,0xd4,0x01,0xd3,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], v[254:255], ttmp15
+// W64: encoding: [0x0a,0x00,0x7f,0xd4,0xfe,0xf7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], s[2:3], vcc_hi
+// W64: encoding: [0x0a,0x00,0x7f,0xd4,0x02,0xd6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], s[104:105], vcc_lo
+// W64: encoding: [0x0a,0x00,0x7f,0xd4,0x68,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], vcc, m0
+// W64: encoding: [0x0a,0x00,0x7f,0xd4,0x6a,0xfa,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], ttmp[14:15], exec_hi
+// W64: encoding: [0x0a,0x00,0x7f,0xd4,0x7a,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], exec, exec_lo
+// W64: encoding: [0x0a,0x00,0x7f,0xd4,0x7e,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], null, null
+// W64: encoding: [0x0a,0x00,0x7f,0xd4,0x7c,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[104:105], -1, -1
+// W64: encoding: [0x68,0x00,0x7f,0xd4,0xc1,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 vcc, 0.5, 0.5
+// W64: encoding: [0x6a,0x00,0x7f,0xd4,0xf0,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 ttmp[14:15], -|src_scc|, src_scc
+// W64: encoding: [0x7a,0x01,0x7f,0xd4,0xfd,0xfa,0x01,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 null, 0xaf123456, 0xaf123456
+// GFX12: encoding: [0x7c,0x00,0x7f,0xd4,0xff,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmp_eq_f16_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x02,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x02,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x02,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x02,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s5, vcc_hi, 0xfe0b
+// W32: encoding: [0x05,0x00,0x02,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x02,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x02,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x02,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s5, |exec_hi|, null
+// W32: encoding: [0x05,0x01,0x02,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x02,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x02,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 vcc_hi, 0.5, -m0
+// W32: encoding: [0x6b,0x00,0x02,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 ttmp15, -src_scc, |vcc_lo|
+// W32: encoding: [0x7b,0x02,0x02,0xd4,0xfd,0xd4,0x00,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], vcc_hi, 0xfe0b
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], |exec_hi|, null
+// W64: encoding: [0x0a,0x01,0x02,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x02,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 vcc, 0.5, -m0
+// W64: encoding: [0x6a,0x00,0x02,0xd4,0xf0,0xfa,0x00,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 ttmp[14:15], -src_scc, |vcc_lo|
+// W64: encoding: [0x7a,0x02,0x02,0xd4,0xfd,0xd4,0x00,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7c,0x83,0x02,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cmp_eq_f32_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x12,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x12,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x12,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x12,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x12,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s5, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x00,0x12,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x12,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x12,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x12,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s5, |exec_hi|, null
+// W32: encoding: [0x05,0x01,0x12,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x12,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x12,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 vcc_hi, 0.5, -m0
+// W32: encoding: [0x6b,0x00,0x12,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 ttmp15, -src_scc, |vcc_lo|
+// W32: encoding: [0x7b,0x02,0x12,0xd4,0xfd,0xd4,0x00,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x12,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x12,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x12,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x12,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x12,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], vcc_hi, 0xaf123456
+// W64: encoding: [0x0a,0x00,0x12,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x12,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x12,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x12,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], |exec_hi|, null
+// W64: encoding: [0x0a,0x01,0x12,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x12,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x12,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 vcc, 0.5, -m0
+// W64: encoding: [0x6a,0x00,0x12,0xd4,0xf0,0xfa,0x00,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 ttmp[14:15], -src_scc, |vcc_lo|
+// W64: encoding: [0x7a,0x02,0x12,0xd4,0xfd,0xd4,0x00,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 null, -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7c,0x83,0x12,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cmp_eq_f64_e64 s5, v[1:2], v[2:3]
+// W32: encoding: [0x05,0x00,0x22,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s5, v[254:255], v[254:255]
+// W32: encoding: [0x05,0x00,0x22,0xd4,0xfe,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s5, s[2:3], s[4:5]
+// W32: encoding: [0x05,0x00,0x22,0xd4,0x02,0x08,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s5, s[104:105], s[104:105]
+// W32: encoding: [0x05,0x00,0x22,0xd4,0x68,0xd0,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s5, vcc, ttmp[14:15]
+// W32: encoding: [0x05,0x00,0x22,0xd4,0x6a,0xf4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s5, ttmp[14:15], 0xaf123456
+// W32: encoding: [0x05,0x00,0x22,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s5, -|exec|, src_scc
+// W32: encoding: [0x05,0x01,0x22,0xd4,0x7e,0xfa,0x01,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s105, null, 0.5
+// W32: encoding: [0x69,0x00,0x22,0xd4,0x7c,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 vcc_lo, -1, -1
+// W32: encoding: [0x6a,0x00,0x22,0xd4,0xc1,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 vcc_hi, 0.5, null
+// W32: encoding: [0x6b,0x00,0x22,0xd4,0xf0,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 ttmp15, -|src_scc|, -|exec|
+// W32: encoding: [0x7b,0x03,0x22,0xd4,0xfd,0xfc,0x00,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], v[254:255], v[254:255]
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0xfe,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], s[2:3], s[4:5]
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0x02,0x08,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], s[104:105], s[104:105]
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0x68,0xd0,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], vcc, ttmp[14:15]
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0x6a,0xf4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], ttmp[14:15], 0xaf123456
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], -|exec|, src_scc
+// W64: encoding: [0x0a,0x01,0x22,0xd4,0x7e,0xfa,0x01,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], null, 0.5
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0x7c,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[104:105], -1, -1
+// W64: encoding: [0x68,0x00,0x22,0xd4,0xc1,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 vcc, 0.5, null
+// W64: encoding: [0x6a,0x00,0x22,0xd4,0xf0,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 ttmp[14:15], -|src_scc|, -|exec|
+// W64: encoding: [0x7a,0x03,0x22,0xd4,0xfd,0xfc,0x00,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 null, 0xaf123456, -|vcc| clamp
+// GFX12: encoding: [0x7c,0x82,0x22,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+
+v_cmp_eq_i16_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x32,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x32,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x32,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x32,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x32,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s5, vcc_hi, 0xfe0b
+// W32: encoding: [0x05,0x00,0x32,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x32,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x32,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x32,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s5, exec_hi, null
+// W32: encoding: [0x05,0x00,0x32,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x32,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x32,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 vcc_hi, 0.5, m0
+// W32: encoding: [0x6b,0x00,0x32,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x7b,0x00,0x32,0xd4,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x32,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x32,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x32,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x32,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x32,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], vcc_hi, 0xfe0b
+// W64: encoding: [0x0a,0x00,0x32,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x32,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x32,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x32,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], exec_hi, null
+// W64: encoding: [0x0a,0x00,0x32,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x32,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x32,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 vcc, 0.5, m0
+// W64: encoding: [0x6a,0x00,0x32,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x7a,0x00,0x32,0xd4,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 null, 0xfe0b, vcc_hi
+// GFX12: encoding: [0x7c,0x00,0x32,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmp_eq_i32_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x42,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x42,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x42,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x42,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x42,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s5, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x00,0x42,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x42,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x42,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x42,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s5, exec_hi, null
+// W32: encoding: [0x05,0x00,0x42,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x42,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x42,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 vcc_hi, 0.5, m0
+// W32: encoding: [0x6b,0x00,0x42,0xd4,0xf0,0xfa,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x7b,0x00,0x42,0xd4,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x42,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x42,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x42,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x42,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x42,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], vcc_hi, 0xaf123456
+// W64: encoding: [0x0a,0x00,0x42,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x42,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x42,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x42,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], exec_hi, null
+// W64: encoding: [0x0a,0x00,0x42,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x42,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x42,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 vcc, 0.5, m0
+// W64: encoding: [0x6a,0x00,0x42,0xd4,0xf0,0xfa,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x7a,0x00,0x42,0xd4,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 null, 0xaf123456, vcc_hi
+// GFX12: encoding: [0x7c,0x00,0x42,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmp_eq_i64_e64 s5, v[1:2], v[2:3]
+// W32: encoding: [0x05,0x00,0x52,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s5, v[254:255], v[254:255]
+// W32: encoding: [0x05,0x00,0x52,0xd4,0xfe,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s5, s[2:3], s[4:5]
+// W32: encoding: [0x05,0x00,0x52,0xd4,0x02,0x08,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s5, s[104:105], s[104:105]
+// W32: encoding: [0x05,0x00,0x52,0xd4,0x68,0xd0,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s5, vcc, ttmp[14:15]
+// W32: encoding: [0x05,0x00,0x52,0xd4,0x6a,0xf4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s5, ttmp[14:15], 0xaf123456
+// W32: encoding: [0x05,0x00,0x52,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s5, exec, src_scc
+// W32: encoding: [0x05,0x00,0x52,0xd4,0x7e,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s105, null, 0.5
+// W32: encoding: [0x69,0x00,0x52,0xd4,0x7c,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 vcc_lo, -1, -1
+// W32: encoding: [0x6a,0x00,0x52,0xd4,0xc1,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 vcc_hi, 0.5, null
+// W32: encoding: [0x6b,0x00,0x52,0xd4,0xf0,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 ttmp15, src_scc, exec
+// W32: encoding: [0x7b,0x00,0x52,0xd4,0xfd,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x52,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], v[254:255], v[254:255]
+// W64: encoding: [0x0a,0x00,0x52,0xd4,0xfe,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], s[2:3], s[4:5]
+// W64: encoding: [0x0a,0x00,0x52,0xd4,0x02,0x08,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], s[104:105], s[104:105]
+// W64: encoding: [0x0a,0x00,0x52,0xd4,0x68,0xd0,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], vcc, ttmp[14:15]
+// W64: encoding: [0x0a,0x00,0x52,0xd4,0x6a,0xf4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], ttmp[14:15], 0xaf123456
+// W64: encoding: [0x0a,0x00,0x52,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], exec, src_scc
+// W64: encoding: [0x0a,0x00,0x52,0xd4,0x7e,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], null, 0.5
+// W64: encoding: [0x0a,0x00,0x52,0xd4,0x7c,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[104:105], -1, -1
+// W64: encoding: [0x68,0x00,0x52,0xd4,0xc1,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 vcc, 0.5, null
+// W64: encoding: [0x6a,0x00,0x52,0xd4,0xf0,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 ttmp[14:15], src_scc, exec
+// W64: encoding: [0x7a,0x00,0x52,0xd4,0xfd,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 null, 0xaf123456, vcc
+// GFX12: encoding: [0x7c,0x00,0x52,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmp_eq_u16_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x3a,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x3a,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x3a,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x3a,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x3a,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s5, vcc_hi, 0xfe0b
+// W32: encoding: [0x05,0x00,0x3a,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x3a,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x3a,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x3a,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s5, exec_hi, null
+// W32: encoding: [0x05,0x00,0x3a,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x3a,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x3a,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 vcc_hi, 0.5, m0
+// W32: encoding: [0x6b,0x00,0x3a,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x7b,0x00,0x3a,0xd4,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x3a,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x3a,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x3a,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x3a,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x3a,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], vcc_hi, 0xfe0b
+// W64: encoding: [0x0a,0x00,0x3a,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x3a,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x3a,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x3a,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], exec_hi, null
+// W64: encoding: [0x0a,0x00,0x3a,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x3a,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x3a,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 vcc, 0.5, m0
+// W64: encoding: [0x6a,0x00,0x3a,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x7a,0x00,0x3a,0xd4,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 null, 0xfe0b, vcc_hi
+// GFX12: encoding: [0x7c,0x00,0x3a,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmp_eq_u32_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x4a,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x4a,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x4a,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x4a,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x4a,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s5, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x00,0x4a,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x4a,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x4a,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x4a,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s5, exec_hi, null
+// W32: encoding: [0x05,0x00,0x4a,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x4a,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x4a,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 vcc_hi, 0.5, m0
+// W32: encoding: [0x6b,0x00,0x4a,0xd4,0xf0,0xfa,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x7b,0x00,0x4a,0xd4,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x4a,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x4a,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x4a,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x4a,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x4a,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], vcc_hi, 0xaf123456
+// W64: encoding: [0x0a,0x00,0x4a,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x4a,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x4a,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x4a,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], exec_hi, null
+// W64: encoding: [0x0a,0x00,0x4a,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x4a,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x4a,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 vcc, 0.5, m0
+// W64: encoding: [0x6a,0x00,0x4a,0xd4,0xf0,0xfa,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x7a,0x00,0x4a,0xd4,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 null, 0xaf123456, vcc_hi
+// GFX12: encoding: [0x7c,0x00,0x4a,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmp_eq_u64_e64 s5, v[1:2], v[2:3]
+// W32: encoding: [0x05,0x00,0x5a,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s5, v[254:255], v[254:255]
+// W32: encoding: [0x05,0x00,0x5a,0xd4,0xfe,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s5, s[2:3], s[4:5]
+// W32: encoding: [0x05,0x00,0x5a,0xd4,0x02,0x08,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s5, s[104:105], s[104:105]
+// W32: encoding: [0x05,0x00,0x5a,0xd4,0x68,0xd0,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s5, vcc, ttmp[14:15]
+// W32: encoding: [0x05,0x00,0x5a,0xd4,0x6a,0xf4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s5, ttmp[14:15], 0xaf123456
+// W32: encoding: [0x05,0x00,0x5a,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s5, exec, src_scc
+// W32: encoding: [0x05,0x00,0x5a,0xd4,0x7e,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s105, null, 0.5
+// W32: encoding: [0x69,0x00,0x5a,0xd4,0x7c,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 vcc_lo, -1, -1
+// W32: encoding: [0x6a,0x00,0x5a,0xd4,0xc1,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 vcc_hi, 0.5, null
+// W32: encoding: [0x6b,0x00,0x5a,0xd4,0xf0,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 ttmp15, src_scc, exec
+// W32: encoding: [0x7b,0x00,0x5a,0xd4,0xfd,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x5a,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], v[254:255], v[254:255]
+// W64: encoding: [0x0a,0x00,0x5a,0xd4,0xfe,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], s[2:3], s[4:5]
+// W64: encoding: [0x0a,0x00,0x5a,0xd4,0x02,0x08,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], s[104:105], s[104:105]
+// W64: encoding: [0x0a,0x00,0x5a,0xd4,0x68,0xd0,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], vcc, ttmp[14:15]
+// W64: encoding: [0x0a,0x00,0x5a,0xd4,0x6a,0xf4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], ttmp[14:15], 0xaf123456
+// W64: encoding: [0x0a,0x00,0x5a,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], exec, src_scc
+// W64: encoding: [0x0a,0x00,0x5a,0xd4,0x7e,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], null, 0.5
+// W64: encoding: [0x0a,0x00,0x5a,0xd4,0x7c,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[104:105], -1, -1
+// W64: encoding: [0x68,0x00,0x5a,0xd4,0xc1,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 vcc, 0.5, null
+// W64: encoding: [0x6a,0x00,0x5a,0xd4,0xf0,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 ttmp[14:15], src_scc, exec
+// W64: encoding: [0x7a,0x00,0x5a,0xd4,0xfd,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 null, 0xaf123456, vcc
+// GFX12: encoding: [0x7c,0x00,0x5a,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmp_ge_f16_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x06,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x06,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x06,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x06,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x06,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s5, vcc_hi, 0xfe0b
+// W32: encoding: [0x05,0x00,0x06,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x06,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x06,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x06,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s5, |exec_hi|, null
+// W32: encoding: [0x05,0x01,0x06,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x06,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x06,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 vcc_hi, 0.5, -m0
+// W32: encoding: [0x6b,0x00,0x06,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 ttmp15, -src_scc, |vcc_lo|
+// W32: encoding: [0x7b,0x02,0x06,0xd4,0xfd,0xd4,0x00,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], vcc_hi, 0xfe0b
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], |exec_hi|, null
+// W64: encoding: [0x0a,0x01,0x06,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x06,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 vcc, 0.5, -m0
+// W64: encoding: [0x6a,0x00,0x06,0xd4,0xf0,0xfa,0x00,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 ttmp[14:15], -src_scc, |vcc_lo|
+// W64: encoding: [0x7a,0x02,0x06,0xd4,0xfd,0xd4,0x00,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7c,0x83,0x06,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cmp_ge_f32_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x16,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x16,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x16,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x16,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x16,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s5, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x00,0x16,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x16,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x16,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x16,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s5, |exec_hi|, null
+// W32: encoding: [0x05,0x01,0x16,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x16,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x16,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 vcc_hi, 0.5, -m0
+// W32: encoding: [0x6b,0x00,0x16,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 ttmp15, -src_scc, |vcc_lo|
+// W32: encoding: [0x7b,0x02,0x16,0xd4,0xfd,0xd4,0x00,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x16,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x16,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x16,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x16,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x16,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], vcc_hi, 0xaf123456
+// W64: encoding: [0x0a,0x00,0x16,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x16,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x16,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x16,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], |exec_hi|, null
+// W64: encoding: [0x0a,0x01,0x16,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x16,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x16,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 vcc, 0.5, -m0
+// W64: encoding: [0x6a,0x00,0x16,0xd4,0xf0,0xfa,0x00,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 ttmp[14:15], -src_scc, |vcc_lo|
+// W64: encoding: [0x7a,0x02,0x16,0xd4,0xfd,0xd4,0x00,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 null, -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7c,0x83,0x16,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cmp_ge_f64_e64 s5, v[1:2], v[2:3]
+// W32: encoding: [0x05,0x00,0x26,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s5, v[254:255], v[254:255]
+// W32: encoding: [0x05,0x00,0x26,0xd4,0xfe,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s5, s[2:3], s[4:5]
+// W32: encoding: [0x05,0x00,0x26,0xd4,0x02,0x08,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s5, s[104:105], s[104:105]
+// W32: encoding: [0x05,0x00,0x26,0xd4,0x68,0xd0,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s5, vcc, ttmp[14:15]
+// W32: encoding: [0x05,0x00,0x26,0xd4,0x6a,0xf4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s5, ttmp[14:15], 0xaf123456
+// W32: encoding: [0x05,0x00,0x26,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s5, -|exec|, src_scc
+// W32: encoding: [0x05,0x01,0x26,0xd4,0x7e,0xfa,0x01,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s105, null, 0.5
+// W32: encoding: [0x69,0x00,0x26,0xd4,0x7c,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 vcc_lo, -1, -1
+// W32: encoding: [0x6a,0x00,0x26,0xd4,0xc1,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 vcc_hi, 0.5, null
+// W32: encoding: [0x6b,0x00,0x26,0xd4,0xf0,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 ttmp15, -|src_scc|, -|exec|
+// W32: encoding: [0x7b,0x03,0x26,0xd4,0xfd,0xfc,0x00,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], v[254:255], v[254:255]
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0xfe,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], s[2:3], s[4:5]
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0x02,0x08,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], s[104:105], s[104:105]
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0x68,0xd0,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], vcc, ttmp[14:15]
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0x6a,0xf4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], ttmp[14:15], 0xaf123456
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], -|exec|, src_scc
+// W64: encoding: [0x0a,0x01,0x26,0xd4,0x7e,0xfa,0x01,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], null, 0.5
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0x7c,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[104:105], -1, -1
+// W64: encoding: [0x68,0x00,0x26,0xd4,0xc1,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 vcc, 0.5, null
+// W64: encoding: [0x6a,0x00,0x26,0xd4,0xf0,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 ttmp[14:15], -|src_scc|, -|exec|
+// W64: encoding: [0x7a,0x03,0x26,0xd4,0xfd,0xfc,0x00,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 null, 0xaf123456, -|vcc| clamp
+// GFX12: encoding: [0x7c,0x82,0x26,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+
+v_cmp_ge_i16_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x36,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x36,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x36,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x36,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x36,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s5, vcc_hi, 0xfe0b
+// W32: encoding: [0x05,0x00,0x36,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x36,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x36,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x36,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s5, exec_hi, null
+// W32: encoding: [0x05,0x00,0x36,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x36,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x36,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 vcc_hi, 0.5, m0
+// W32: encoding: [0x6b,0x00,0x36,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x7b,0x00,0x36,0xd4,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x36,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x36,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x36,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x36,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x36,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], vcc_hi, 0xfe0b
+// W64: encoding: [0x0a,0x00,0x36,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x36,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x36,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x36,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], exec_hi, null
+// W64: encoding: [0x0a,0x00,0x36,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x36,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x36,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 vcc, 0.5, m0
+// W64: encoding: [0x6a,0x00,0x36,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x7a,0x00,0x36,0xd4,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 null, 0xfe0b, vcc_hi
+// GFX12: encoding: [0x7c,0x00,0x36,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmp_ge_i32_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x46,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x46,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x46,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x46,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x46,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s5, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x00,0x46,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x46,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x46,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x46,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s5, exec_hi, null
+// W32: encoding: [0x05,0x00,0x46,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x46,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x46,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 vcc_hi, 0.5, m0
+// W32: encoding: [0x6b,0x00,0x46,0xd4,0xf0,0xfa,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x7b,0x00,0x46,0xd4,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x46,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x46,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x46,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x46,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x46,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], vcc_hi, 0xaf123456
+// W64: encoding: [0x0a,0x00,0x46,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x46,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x46,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x46,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], exec_hi, null
+// W64: encoding: [0x0a,0x00,0x46,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x46,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x46,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 vcc, 0.5, m0
+// W64: encoding: [0x6a,0x00,0x46,0xd4,0xf0,0xfa,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x7a,0x00,0x46,0xd4,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 null, 0xaf123456, vcc_hi
+// GFX12: encoding: [0x7c,0x00,0x46,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmp_ge_i64_e64 s5, v[1:2], v[2:3]
+// W32: encoding: [0x05,0x00,0x56,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s5, v[254:255], v[254:255]
+// W32: encoding: [0x05,0x00,0x56,0xd4,0xfe,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s5, s[2:3], s[4:5]
+// W32: encoding: [0x05,0x00,0x56,0xd4,0x02,0x08,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s5, s[104:105], s[104:105]
+// W32: encoding: [0x05,0x00,0x56,0xd4,0x68,0xd0,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s5, vcc, ttmp[14:15]
+// W32: encoding: [0x05,0x00,0x56,0xd4,0x6a,0xf4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s5, ttmp[14:15], 0xaf123456
+// W32: encoding: [0x05,0x00,0x56,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s5, exec, src_scc
+// W32: encoding: [0x05,0x00,0x56,0xd4,0x7e,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s105, null, 0.5
+// W32: encoding: [0x69,0x00,0x56,0xd4,0x7c,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 vcc_lo, -1, -1
+// W32: encoding: [0x6a,0x00,0x56,0xd4,0xc1,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 vcc_hi, 0.5, null
+// W32: encoding: [0x6b,0x00,0x56,0xd4,0xf0,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 ttmp15, src_scc, exec
+// W32: encoding: [0x7b,0x00,0x56,0xd4,0xfd,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x56,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], v[254:255], v[254:255]
+// W64: encoding: [0x0a,0x00,0x56,0xd4,0xfe,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], s[2:3], s[4:5]
+// W64: encoding: [0x0a,0x00,0x56,0xd4,0x02,0x08,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], s[104:105], s[104:105]
+// W64: encoding: [0x0a,0x00,0x56,0xd4,0x68,0xd0,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], vcc, ttmp[14:15]
+// W64: encoding: [0x0a,0x00,0x56,0xd4,0x6a,0xf4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], ttmp[14:15], 0xaf123456
+// W64: encoding: [0x0a,0x00,0x56,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], exec, src_scc
+// W64: encoding: [0x0a,0x00,0x56,0xd4,0x7e,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], null, 0.5
+// W64: encoding: [0x0a,0x00,0x56,0xd4,0x7c,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[104:105], -1, -1
+// W64: encoding: [0x68,0x00,0x56,0xd4,0xc1,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 vcc, 0.5, null
+// W64: encoding: [0x6a,0x00,0x56,0xd4,0xf0,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 ttmp[14:15], src_scc, exec
+// W64: encoding: [0x7a,0x00,0x56,0xd4,0xfd,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 null, 0xaf123456, vcc
+// GFX12: encoding: [0x7c,0x00,0x56,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmp_ge_u16_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x3e,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x3e,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x3e,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x3e,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x3e,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s5, vcc_hi, 0xfe0b
+// W32: encoding: [0x05,0x00,0x3e,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x3e,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x3e,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x3e,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s5, exec_hi, null
+// W32: encoding: [0x05,0x00,0x3e,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x3e,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x3e,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 vcc_hi, 0.5, m0
+// W32: encoding: [0x6b,0x00,0x3e,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x7b,0x00,0x3e,0xd4,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x3e,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x3e,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x3e,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x3e,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x3e,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], vcc_hi, 0xfe0b
+// W64: encoding: [0x0a,0x00,0x3e,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x3e,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x3e,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x3e,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], exec_hi, null
+// W64: encoding: [0x0a,0x00,0x3e,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x3e,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x3e,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 vcc, 0.5, m0
+// W64: encoding: [0x6a,0x00,0x3e,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x7a,0x00,0x3e,0xd4,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 null, 0xfe0b, vcc_hi
+// GFX12: encoding: [0x7c,0x00,0x3e,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmp_ge_u32_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x4e,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x4e,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x4e,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x4e,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x4e,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s5, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x00,0x4e,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x4e,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x4e,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x4e,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s5, exec_hi, null
+// W32: encoding: [0x05,0x00,0x4e,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x4e,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x4e,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 vcc_hi, 0.5, m0
+// W32: encoding: [0x6b,0x00,0x4e,0xd4,0xf0,0xfa,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x7b,0x00,0x4e,0xd4,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x4e,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x4e,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x4e,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x4e,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x4e,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], vcc_hi, 0xaf123456
+// W64: encoding: [0x0a,0x00,0x4e,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x4e,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x4e,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x4e,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], exec_hi, null
+// W64: encoding: [0x0a,0x00,0x4e,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x4e,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x4e,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 vcc, 0.5, m0
+// W64: encoding: [0x6a,0x00,0x4e,0xd4,0xf0,0xfa,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x7a,0x00,0x4e,0xd4,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 null, 0xaf123456, vcc_hi
+// GFX12: encoding: [0x7c,0x00,0x4e,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmp_ge_u64_e64 s5, v[1:2], v[2:3]
+// W32: encoding: [0x05,0x00,0x5e,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s5, v[254:255], v[254:255]
+// W32: encoding: [0x05,0x00,0x5e,0xd4,0xfe,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s5, s[2:3], s[4:5]
+// W32: encoding: [0x05,0x00,0x5e,0xd4,0x02,0x08,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s5, s[104:105], s[104:105]
+// W32: encoding: [0x05,0x00,0x5e,0xd4,0x68,0xd0,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s5, vcc, ttmp[14:15]
+// W32: encoding: [0x05,0x00,0x5e,0xd4,0x6a,0xf4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s5, ttmp[14:15], 0xaf123456
+// W32: encoding: [0x05,0x00,0x5e,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s5, exec, src_scc
+// W32: encoding: [0x05,0x00,0x5e,0xd4,0x7e,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s105, null, 0.5
+// W32: encoding: [0x69,0x00,0x5e,0xd4,0x7c,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 vcc_lo, -1, -1
+// W32: encoding: [0x6a,0x00,0x5e,0xd4,0xc1,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 vcc_hi, 0.5, null
+// W32: encoding: [0x6b,0x00,0x5e,0xd4,0xf0,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 ttmp15, src_scc, exec
+// W32: encoding: [0x7b,0x00,0x5e,0xd4,0xfd,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x5e,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], v[254:255], v[254:255]
+// W64: encoding: [0x0a,0x00,0x5e,0xd4,0xfe,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], s[2:3], s[4:5]
+// W64: encoding: [0x0a,0x00,0x5e,0xd4,0x02,0x08,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], s[104:105], s[104:105]
+// W64: encoding: [0x0a,0x00,0x5e,0xd4,0x68,0xd0,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], vcc, ttmp[14:15]
+// W64: encoding: [0x0a,0x00,0x5e,0xd4,0x6a,0xf4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], ttmp[14:15], 0xaf123456
+// W64: encoding: [0x0a,0x00,0x5e,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], exec, src_scc
+// W64: encoding: [0x0a,0x00,0x5e,0xd4,0x7e,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], null, 0.5
+// W64: encoding: [0x0a,0x00,0x5e,0xd4,0x7c,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[104:105], -1, -1
+// W64: encoding: [0x68,0x00,0x5e,0xd4,0xc1,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 vcc, 0.5, null
+// W64: encoding: [0x6a,0x00,0x5e,0xd4,0xf0,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 ttmp[14:15], src_scc, exec
+// W64: encoding: [0x7a,0x00,0x5e,0xd4,0xfd,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 null, 0xaf123456, vcc
+// GFX12: encoding: [0x7c,0x00,0x5e,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmp_gt_f16_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x04,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x04,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x04,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x04,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x04,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s5, vcc_hi, 0xfe0b
+// W32: encoding: [0x05,0x00,0x04,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x04,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x04,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x04,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s5, |exec_hi|, null
+// W32: encoding: [0x05,0x01,0x04,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x04,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x04,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 vcc_hi, 0.5, -m0
+// W32: encoding: [0x6b,0x00,0x04,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 ttmp15, -src_scc, |vcc_lo|
+// W32: encoding: [0x7b,0x02,0x04,0xd4,0xfd,0xd4,0x00,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], vcc_hi, 0xfe0b
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], |exec_hi|, null
+// W64: encoding: [0x0a,0x01,0x04,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x04,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 vcc, 0.5, -m0
+// W64: encoding: [0x6a,0x00,0x04,0xd4,0xf0,0xfa,0x00,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 ttmp[14:15], -src_scc, |vcc_lo|
+// W64: encoding: [0x7a,0x02,0x04,0xd4,0xfd,0xd4,0x00,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7c,0x83,0x04,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cmp_gt_f32_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x14,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x14,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x14,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x14,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x14,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s5, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x00,0x14,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x14,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x14,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x14,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s5, |exec_hi|, null
+// W32: encoding: [0x05,0x01,0x14,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x14,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x14,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 vcc_hi, 0.5, -m0
+// W32: encoding: [0x6b,0x00,0x14,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 ttmp15, -src_scc, |vcc_lo|
+// W32: encoding: [0x7b,0x02,0x14,0xd4,0xfd,0xd4,0x00,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x14,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x14,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x14,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x14,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x14,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], vcc_hi, 0xaf123456
+// W64: encoding: [0x0a,0x00,0x14,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x14,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x14,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x14,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], |exec_hi|, null
+// W64: encoding: [0x0a,0x01,0x14,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x14,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x14,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 vcc, 0.5, -m0
+// W64: encoding: [0x6a,0x00,0x14,0xd4,0xf0,0xfa,0x00,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 ttmp[14:15], -src_scc, |vcc_lo|
+// W64: encoding: [0x7a,0x02,0x14,0xd4,0xfd,0xd4,0x00,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 null, -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7c,0x83,0x14,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cmp_gt_f64_e64 s5, v[1:2], v[2:3]
+// W32: encoding: [0x05,0x00,0x24,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s5, v[254:255], v[254:255]
+// W32: encoding: [0x05,0x00,0x24,0xd4,0xfe,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s5, s[2:3], s[4:5]
+// W32: encoding: [0x05,0x00,0x24,0xd4,0x02,0x08,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s5, s[104:105], s[104:105]
+// W32: encoding: [0x05,0x00,0x24,0xd4,0x68,0xd0,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s5, vcc, ttmp[14:15]
+// W32: encoding: [0x05,0x00,0x24,0xd4,0x6a,0xf4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s5, ttmp[14:15], 0xaf123456
+// W32: encoding: [0x05,0x00,0x24,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s5, -|exec|, src_scc
+// W32: encoding: [0x05,0x01,0x24,0xd4,0x7e,0xfa,0x01,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s105, null, 0.5
+// W32: encoding: [0x69,0x00,0x24,0xd4,0x7c,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 vcc_lo, -1, -1
+// W32: encoding: [0x6a,0x00,0x24,0xd4,0xc1,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 vcc_hi, 0.5, null
+// W32: encoding: [0x6b,0x00,0x24,0xd4,0xf0,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 ttmp15, -|src_scc|, -|exec|
+// W32: encoding: [0x7b,0x03,0x24,0xd4,0xfd,0xfc,0x00,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], v[254:255], v[254:255]
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0xfe,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], s[2:3], s[4:5]
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0x02,0x08,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], s[104:105], s[104:105]
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0x68,0xd0,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], vcc, ttmp[14:15]
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0x6a,0xf4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], ttmp[14:15], 0xaf123456
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], -|exec|, src_scc
+// W64: encoding: [0x0a,0x01,0x24,0xd4,0x7e,0xfa,0x01,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], null, 0.5
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0x7c,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[104:105], -1, -1
+// W64: encoding: [0x68,0x00,0x24,0xd4,0xc1,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 vcc, 0.5, null
+// W64: encoding: [0x6a,0x00,0x24,0xd4,0xf0,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 ttmp[14:15], -|src_scc|, -|exec|
+// W64: encoding: [0x7a,0x03,0x24,0xd4,0xfd,0xfc,0x00,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 null, 0xaf123456, -|vcc| clamp
+// GFX12: encoding: [0x7c,0x82,0x24,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+
+v_cmp_gt_i16_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x34,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x34,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x34,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x34,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x34,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s5, vcc_hi, 0xfe0b
+// W32: encoding: [0x05,0x00,0x34,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x34,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x34,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x34,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s5, exec_hi, null
+// W32: encoding: [0x05,0x00,0x34,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x34,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x34,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 vcc_hi, 0.5, m0
+// W32: encoding: [0x6b,0x00,0x34,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x7b,0x00,0x34,0xd4,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x34,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x34,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x34,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x34,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x34,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], vcc_hi, 0xfe0b
+// W64: encoding: [0x0a,0x00,0x34,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x34,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x34,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x34,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], exec_hi, null
+// W64: encoding: [0x0a,0x00,0x34,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x34,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x34,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 vcc, 0.5, m0
+// W64: encoding: [0x6a,0x00,0x34,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x7a,0x00,0x34,0xd4,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 null, 0xfe0b, vcc_hi
+// GFX12: encoding: [0x7c,0x00,0x34,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmp_gt_i32_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x44,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x44,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x44,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x44,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x44,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s5, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x00,0x44,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x44,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x44,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x44,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s5, exec_hi, null
+// W32: encoding: [0x05,0x00,0x44,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x44,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x44,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 vcc_hi, 0.5, m0
+// W32: encoding: [0x6b,0x00,0x44,0xd4,0xf0,0xfa,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x7b,0x00,0x44,0xd4,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x44,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x44,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x44,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x44,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x44,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], vcc_hi, 0xaf123456
+// W64: encoding: [0x0a,0x00,0x44,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x44,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x44,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x44,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], exec_hi, null
+// W64: encoding: [0x0a,0x00,0x44,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x44,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x44,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 vcc, 0.5, m0
+// W64: encoding: [0x6a,0x00,0x44,0xd4,0xf0,0xfa,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x7a,0x00,0x44,0xd4,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 null, 0xaf123456, vcc_hi
+// GFX12: encoding: [0x7c,0x00,0x44,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmp_gt_i64_e64 s5, v[1:2], v[2:3]
+// W32: encoding: [0x05,0x00,0x54,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s5, v[254:255], v[254:255]
+// W32: encoding: [0x05,0x00,0x54,0xd4,0xfe,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s5, s[2:3], s[4:5]
+// W32: encoding: [0x05,0x00,0x54,0xd4,0x02,0x08,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s5, s[104:105], s[104:105]
+// W32: encoding: [0x05,0x00,0x54,0xd4,0x68,0xd0,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s5, vcc, ttmp[14:15]
+// W32: encoding: [0x05,0x00,0x54,0xd4,0x6a,0xf4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s5, ttmp[14:15], 0xaf123456
+// W32: encoding: [0x05,0x00,0x54,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s5, exec, src_scc
+// W32: encoding: [0x05,0x00,0x54,0xd4,0x7e,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s105, null, 0.5
+// W32: encoding: [0x69,0x00,0x54,0xd4,0x7c,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 vcc_lo, -1, -1
+// W32: encoding: [0x6a,0x00,0x54,0xd4,0xc1,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 vcc_hi, 0.5, null
+// W32: encoding: [0x6b,0x00,0x54,0xd4,0xf0,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 ttmp15, src_scc, exec
+// W32: encoding: [0x7b,0x00,0x54,0xd4,0xfd,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x54,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], v[254:255], v[254:255]
+// W64: encoding: [0x0a,0x00,0x54,0xd4,0xfe,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], s[2:3], s[4:5]
+// W64: encoding: [0x0a,0x00,0x54,0xd4,0x02,0x08,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], s[104:105], s[104:105]
+// W64: encoding: [0x0a,0x00,0x54,0xd4,0x68,0xd0,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], vcc, ttmp[14:15]
+// W64: encoding: [0x0a,0x00,0x54,0xd4,0x6a,0xf4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], ttmp[14:15], 0xaf123456
+// W64: encoding: [0x0a,0x00,0x54,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], exec, src_scc
+// W64: encoding: [0x0a,0x00,0x54,0xd4,0x7e,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], null, 0.5
+// W64: encoding: [0x0a,0x00,0x54,0xd4,0x7c,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[104:105], -1, -1
+// W64: encoding: [0x68,0x00,0x54,0xd4,0xc1,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 vcc, 0.5, null
+// W64: encoding: [0x6a,0x00,0x54,0xd4,0xf0,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 ttmp[14:15], src_scc, exec
+// W64: encoding: [0x7a,0x00,0x54,0xd4,0xfd,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 null, 0xaf123456, vcc
+// GFX12: encoding: [0x7c,0x00,0x54,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmp_gt_u16_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x3c,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x3c,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x3c,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x3c,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x3c,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s5, vcc_hi, 0xfe0b
+// W32: encoding: [0x05,0x00,0x3c,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x3c,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x3c,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x3c,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s5, exec_hi, null
+// W32: encoding: [0x05,0x00,0x3c,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x3c,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x3c,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 vcc_hi, 0.5, m0
+// W32: encoding: [0x6b,0x00,0x3c,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x7b,0x00,0x3c,0xd4,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x3c,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x3c,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x3c,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x3c,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x3c,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], vcc_hi, 0xfe0b
+// W64: encoding: [0x0a,0x00,0x3c,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x3c,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x3c,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x3c,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], exec_hi, null
+// W64: encoding: [0x0a,0x00,0x3c,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x3c,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x3c,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 vcc, 0.5, m0
+// W64: encoding: [0x6a,0x00,0x3c,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x7a,0x00,0x3c,0xd4,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 null, 0xfe0b, vcc_hi
+// GFX12: encoding: [0x7c,0x00,0x3c,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmp_gt_u32_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x4c,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x4c,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x4c,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x4c,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x4c,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s5, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x00,0x4c,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x4c,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x4c,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x4c,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s5, exec_hi, null
+// W32: encoding: [0x05,0x00,0x4c,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x4c,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x4c,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 vcc_hi, 0.5, m0
+// W32: encoding: [0x6b,0x00,0x4c,0xd4,0xf0,0xfa,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x7b,0x00,0x4c,0xd4,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x4c,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x4c,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x4c,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x4c,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x4c,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], vcc_hi, 0xaf123456
+// W64: encoding: [0x0a,0x00,0x4c,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x4c,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x4c,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x4c,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], exec_hi, null
+// W64: encoding: [0x0a,0x00,0x4c,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x4c,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x4c,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 vcc, 0.5, m0
+// W64: encoding: [0x6a,0x00,0x4c,0xd4,0xf0,0xfa,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x7a,0x00,0x4c,0xd4,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 null, 0xaf123456, vcc_hi
+// GFX12: encoding: [0x7c,0x00,0x4c,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmp_gt_u64_e64 s5, v[1:2], v[2:3]
+// W32: encoding: [0x05,0x00,0x5c,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s5, v[254:255], v[254:255]
+// W32: encoding: [0x05,0x00,0x5c,0xd4,0xfe,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s5, s[2:3], s[4:5]
+// W32: encoding: [0x05,0x00,0x5c,0xd4,0x02,0x08,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s5, s[104:105], s[104:105]
+// W32: encoding: [0x05,0x00,0x5c,0xd4,0x68,0xd0,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s5, vcc, ttmp[14:15]
+// W32: encoding: [0x05,0x00,0x5c,0xd4,0x6a,0xf4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s5, ttmp[14:15], 0xaf123456
+// W32: encoding: [0x05,0x00,0x5c,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s5, exec, src_scc
+// W32: encoding: [0x05,0x00,0x5c,0xd4,0x7e,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s105, null, 0.5
+// W32: encoding: [0x69,0x00,0x5c,0xd4,0x7c,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 vcc_lo, -1, -1
+// W32: encoding: [0x6a,0x00,0x5c,0xd4,0xc1,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 vcc_hi, 0.5, null
+// W32: encoding: [0x6b,0x00,0x5c,0xd4,0xf0,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 ttmp15, src_scc, exec
+// W32: encoding: [0x7b,0x00,0x5c,0xd4,0xfd,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x5c,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], v[254:255], v[254:255]
+// W64: encoding: [0x0a,0x00,0x5c,0xd4,0xfe,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], s[2:3], s[4:5]
+// W64: encoding: [0x0a,0x00,0x5c,0xd4,0x02,0x08,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], s[104:105], s[104:105]
+// W64: encoding: [0x0a,0x00,0x5c,0xd4,0x68,0xd0,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], vcc, ttmp[14:15]
+// W64: encoding: [0x0a,0x00,0x5c,0xd4,0x6a,0xf4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], ttmp[14:15], 0xaf123456
+// W64: encoding: [0x0a,0x00,0x5c,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], exec, src_scc
+// W64: encoding: [0x0a,0x00,0x5c,0xd4,0x7e,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], null, 0.5
+// W64: encoding: [0x0a,0x00,0x5c,0xd4,0x7c,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[104:105], -1, -1
+// W64: encoding: [0x68,0x00,0x5c,0xd4,0xc1,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 vcc, 0.5, null
+// W64: encoding: [0x6a,0x00,0x5c,0xd4,0xf0,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 ttmp[14:15], src_scc, exec
+// W64: encoding: [0x7a,0x00,0x5c,0xd4,0xfd,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 null, 0xaf123456, vcc
+// GFX12: encoding: [0x7c,0x00,0x5c,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmp_le_f16_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x03,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x03,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x03,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x03,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x03,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s5, vcc_hi, 0xfe0b
+// W32: encoding: [0x05,0x00,0x03,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x03,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x03,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x03,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s5, |exec_hi|, null
+// W32: encoding: [0x05,0x01,0x03,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x03,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x03,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 vcc_hi, 0.5, -m0
+// W32: encoding: [0x6b,0x00,0x03,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 ttmp15, -src_scc, |vcc_lo|
+// W32: encoding: [0x7b,0x02,0x03,0xd4,0xfd,0xd4,0x00,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], vcc_hi, 0xfe0b
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], |exec_hi|, null
+// W64: encoding: [0x0a,0x01,0x03,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x03,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 vcc, 0.5, -m0
+// W64: encoding: [0x6a,0x00,0x03,0xd4,0xf0,0xfa,0x00,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 ttmp[14:15], -src_scc, |vcc_lo|
+// W64: encoding: [0x7a,0x02,0x03,0xd4,0xfd,0xd4,0x00,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7c,0x83,0x03,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cmp_le_f32_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x13,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x13,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x13,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x13,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x13,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s5, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x00,0x13,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x13,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x13,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x13,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s5, |exec_hi|, null
+// W32: encoding: [0x05,0x01,0x13,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x13,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x13,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 vcc_hi, 0.5, -m0
+// W32: encoding: [0x6b,0x00,0x13,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 ttmp15, -src_scc, |vcc_lo|
+// W32: encoding: [0x7b,0x02,0x13,0xd4,0xfd,0xd4,0x00,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x13,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x13,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x13,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x13,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x13,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], vcc_hi, 0xaf123456
+// W64: encoding: [0x0a,0x00,0x13,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x13,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x13,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x13,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], |exec_hi|, null
+// W64: encoding: [0x0a,0x01,0x13,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x13,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x13,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 vcc, 0.5, -m0
+// W64: encoding: [0x6a,0x00,0x13,0xd4,0xf0,0xfa,0x00,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 ttmp[14:15], -src_scc, |vcc_lo|
+// W64: encoding: [0x7a,0x02,0x13,0xd4,0xfd,0xd4,0x00,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 null, -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7c,0x83,0x13,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cmp_le_f64_e64 s5, v[1:2], v[2:3]
+// W32: encoding: [0x05,0x00,0x23,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s5, v[254:255], v[254:255]
+// W32: encoding: [0x05,0x00,0x23,0xd4,0xfe,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s5, s[2:3], s[4:5]
+// W32: encoding: [0x05,0x00,0x23,0xd4,0x02,0x08,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s5, s[104:105], s[104:105]
+// W32: encoding: [0x05,0x00,0x23,0xd4,0x68,0xd0,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s5, vcc, ttmp[14:15]
+// W32: encoding: [0x05,0x00,0x23,0xd4,0x6a,0xf4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s5, ttmp[14:15], 0xaf123456
+// W32: encoding: [0x05,0x00,0x23,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s5, -|exec|, src_scc
+// W32: encoding: [0x05,0x01,0x23,0xd4,0x7e,0xfa,0x01,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s105, null, 0.5
+// W32: encoding: [0x69,0x00,0x23,0xd4,0x7c,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 vcc_lo, -1, -1
+// W32: encoding: [0x6a,0x00,0x23,0xd4,0xc1,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 vcc_hi, 0.5, null
+// W32: encoding: [0x6b,0x00,0x23,0xd4,0xf0,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 ttmp15, -|src_scc|, -|exec|
+// W32: encoding: [0x7b,0x03,0x23,0xd4,0xfd,0xfc,0x00,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], v[254:255], v[254:255]
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0xfe,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], s[2:3], s[4:5]
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0x02,0x08,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], s[104:105], s[104:105]
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0x68,0xd0,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], vcc, ttmp[14:15]
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0x6a,0xf4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], ttmp[14:15], 0xaf123456
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], -|exec|, src_scc
+// W64: encoding: [0x0a,0x01,0x23,0xd4,0x7e,0xfa,0x01,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], null, 0.5
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0x7c,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[104:105], -1, -1
+// W64: encoding: [0x68,0x00,0x23,0xd4,0xc1,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 vcc, 0.5, null
+// W64: encoding: [0x6a,0x00,0x23,0xd4,0xf0,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 ttmp[14:15], -|src_scc|, -|exec|
+// W64: encoding: [0x7a,0x03,0x23,0xd4,0xfd,0xfc,0x00,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 null, 0xaf123456, -|vcc| clamp
+// GFX12: encoding: [0x7c,0x82,0x23,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+
+v_cmp_le_i16_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x33,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x33,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x33,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x33,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x33,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s5, vcc_hi, 0xfe0b
+// W32: encoding: [0x05,0x00,0x33,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x33,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x33,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x33,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s5, exec_hi, null
+// W32: encoding: [0x05,0x00,0x33,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x33,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x33,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 vcc_hi, 0.5, m0
+// W32: encoding: [0x6b,0x00,0x33,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x7b,0x00,0x33,0xd4,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x33,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x33,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x33,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x33,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x33,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], vcc_hi, 0xfe0b
+// W64: encoding: [0x0a,0x00,0x33,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x33,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x33,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x33,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], exec_hi, null
+// W64: encoding: [0x0a,0x00,0x33,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x33,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x33,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 vcc, 0.5, m0
+// W64: encoding: [0x6a,0x00,0x33,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x7a,0x00,0x33,0xd4,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 null, 0xfe0b, vcc_hi
+// GFX12: encoding: [0x7c,0x00,0x33,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmp_le_i32_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x43,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x43,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x43,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x43,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x43,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s5, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x00,0x43,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x43,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x43,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x43,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s5, exec_hi, null
+// W32: encoding: [0x05,0x00,0x43,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x43,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x43,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 vcc_hi, 0.5, m0
+// W32: encoding: [0x6b,0x00,0x43,0xd4,0xf0,0xfa,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x7b,0x00,0x43,0xd4,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x43,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x43,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x43,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x43,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x43,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], vcc_hi, 0xaf123456
+// W64: encoding: [0x0a,0x00,0x43,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x43,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x43,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x43,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], exec_hi, null
+// W64: encoding: [0x0a,0x00,0x43,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x43,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x43,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 vcc, 0.5, m0
+// W64: encoding: [0x6a,0x00,0x43,0xd4,0xf0,0xfa,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x7a,0x00,0x43,0xd4,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 null, 0xaf123456, vcc_hi
+// GFX12: encoding: [0x7c,0x00,0x43,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmp_le_i64_e64 s5, v[1:2], v[2:3]
+// W32: encoding: [0x05,0x00,0x53,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s5, v[254:255], v[254:255]
+// W32: encoding: [0x05,0x00,0x53,0xd4,0xfe,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s5, s[2:3], s[4:5]
+// W32: encoding: [0x05,0x00,0x53,0xd4,0x02,0x08,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s5, s[104:105], s[104:105]
+// W32: encoding: [0x05,0x00,0x53,0xd4,0x68,0xd0,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s5, vcc, ttmp[14:15]
+// W32: encoding: [0x05,0x00,0x53,0xd4,0x6a,0xf4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s5, ttmp[14:15], 0xaf123456
+// W32: encoding: [0x05,0x00,0x53,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s5, exec, src_scc
+// W32: encoding: [0x05,0x00,0x53,0xd4,0x7e,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s105, null, 0.5
+// W32: encoding: [0x69,0x00,0x53,0xd4,0x7c,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 vcc_lo, -1, -1
+// W32: encoding: [0x6a,0x00,0x53,0xd4,0xc1,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 vcc_hi, 0.5, null
+// W32: encoding: [0x6b,0x00,0x53,0xd4,0xf0,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 ttmp15, src_scc, exec
+// W32: encoding: [0x7b,0x00,0x53,0xd4,0xfd,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x53,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], v[254:255], v[254:255]
+// W64: encoding: [0x0a,0x00,0x53,0xd4,0xfe,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], s[2:3], s[4:5]
+// W64: encoding: [0x0a,0x00,0x53,0xd4,0x02,0x08,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], s[104:105], s[104:105]
+// W64: encoding: [0x0a,0x00,0x53,0xd4,0x68,0xd0,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], vcc, ttmp[14:15]
+// W64: encoding: [0x0a,0x00,0x53,0xd4,0x6a,0xf4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], ttmp[14:15], 0xaf123456
+// W64: encoding: [0x0a,0x00,0x53,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], exec, src_scc
+// W64: encoding: [0x0a,0x00,0x53,0xd4,0x7e,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], null, 0.5
+// W64: encoding: [0x0a,0x00,0x53,0xd4,0x7c,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[104:105], -1, -1
+// W64: encoding: [0x68,0x00,0x53,0xd4,0xc1,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 vcc, 0.5, null
+// W64: encoding: [0x6a,0x00,0x53,0xd4,0xf0,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 ttmp[14:15], src_scc, exec
+// W64: encoding: [0x7a,0x00,0x53,0xd4,0xfd,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 null, 0xaf123456, vcc
+// GFX12: encoding: [0x7c,0x00,0x53,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmp_le_u16_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x3b,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x3b,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x3b,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x3b,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x3b,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s5, vcc_hi, 0xfe0b
+// W32: encoding: [0x05,0x00,0x3b,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x3b,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x3b,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x3b,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s5, exec_hi, null
+// W32: encoding: [0x05,0x00,0x3b,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x3b,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x3b,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 vcc_hi, 0.5, m0
+// W32: encoding: [0x6b,0x00,0x3b,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x7b,0x00,0x3b,0xd4,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x3b,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x3b,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x3b,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x3b,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x3b,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], vcc_hi, 0xfe0b
+// W64: encoding: [0x0a,0x00,0x3b,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x3b,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x3b,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x3b,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], exec_hi, null
+// W64: encoding: [0x0a,0x00,0x3b,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x3b,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x3b,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 vcc, 0.5, m0
+// W64: encoding: [0x6a,0x00,0x3b,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x7a,0x00,0x3b,0xd4,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 null, 0xfe0b, vcc_hi
+// GFX12: encoding: [0x7c,0x00,0x3b,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmp_le_u32_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x4b,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x4b,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x4b,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x4b,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x4b,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s5, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x00,0x4b,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x4b,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x4b,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x4b,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s5, exec_hi, null
+// W32: encoding: [0x05,0x00,0x4b,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x4b,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x4b,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 vcc_hi, 0.5, m0
+// W32: encoding: [0x6b,0x00,0x4b,0xd4,0xf0,0xfa,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x7b,0x00,0x4b,0xd4,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x4b,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x4b,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x4b,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x4b,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x4b,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], vcc_hi, 0xaf123456
+// W64: encoding: [0x0a,0x00,0x4b,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x4b,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x4b,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x4b,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], exec_hi, null
+// W64: encoding: [0x0a,0x00,0x4b,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x4b,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x4b,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 vcc, 0.5, m0
+// W64: encoding: [0x6a,0x00,0x4b,0xd4,0xf0,0xfa,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x7a,0x00,0x4b,0xd4,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 null, 0xaf123456, vcc_hi
+// GFX12: encoding: [0x7c,0x00,0x4b,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmp_le_u64_e64 s5, v[1:2], v[2:3]
+// W32: encoding: [0x05,0x00,0x5b,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s5, v[254:255], v[254:255]
+// W32: encoding: [0x05,0x00,0x5b,0xd4,0xfe,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s5, s[2:3], s[4:5]
+// W32: encoding: [0x05,0x00,0x5b,0xd4,0x02,0x08,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s5, s[104:105], s[104:105]
+// W32: encoding: [0x05,0x00,0x5b,0xd4,0x68,0xd0,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s5, vcc, ttmp[14:15]
+// W32: encoding: [0x05,0x00,0x5b,0xd4,0x6a,0xf4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s5, ttmp[14:15], 0xaf123456
+// W32: encoding: [0x05,0x00,0x5b,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s5, exec, src_scc
+// W32: encoding: [0x05,0x00,0x5b,0xd4,0x7e,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s105, null, 0.5
+// W32: encoding: [0x69,0x00,0x5b,0xd4,0x7c,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 vcc_lo, -1, -1
+// W32: encoding: [0x6a,0x00,0x5b,0xd4,0xc1,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 vcc_hi, 0.5, null
+// W32: encoding: [0x6b,0x00,0x5b,0xd4,0xf0,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 ttmp15, src_scc, exec
+// W32: encoding: [0x7b,0x00,0x5b,0xd4,0xfd,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x5b,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], v[254:255], v[254:255]
+// W64: encoding: [0x0a,0x00,0x5b,0xd4,0xfe,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], s[2:3], s[4:5]
+// W64: encoding: [0x0a,0x00,0x5b,0xd4,0x02,0x08,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], s[104:105], s[104:105]
+// W64: encoding: [0x0a,0x00,0x5b,0xd4,0x68,0xd0,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], vcc, ttmp[14:15]
+// W64: encoding: [0x0a,0x00,0x5b,0xd4,0x6a,0xf4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], ttmp[14:15], 0xaf123456
+// W64: encoding: [0x0a,0x00,0x5b,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], exec, src_scc
+// W64: encoding: [0x0a,0x00,0x5b,0xd4,0x7e,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], null, 0.5
+// W64: encoding: [0x0a,0x00,0x5b,0xd4,0x7c,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[104:105], -1, -1
+// W64: encoding: [0x68,0x00,0x5b,0xd4,0xc1,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 vcc, 0.5, null
+// W64: encoding: [0x6a,0x00,0x5b,0xd4,0xf0,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 ttmp[14:15], src_scc, exec
+// W64: encoding: [0x7a,0x00,0x5b,0xd4,0xfd,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 null, 0xaf123456, vcc
+// GFX12: encoding: [0x7c,0x00,0x5b,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmp_lg_f16_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x05,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x05,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x05,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x05,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x05,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s5, vcc_hi, 0xfe0b
+// W32: encoding: [0x05,0x00,0x05,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x05,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x05,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x05,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s5, |exec_hi|, null
+// W32: encoding: [0x05,0x01,0x05,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x05,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x05,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 vcc_hi, 0.5, -m0
+// W32: encoding: [0x6b,0x00,0x05,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 ttmp15, -src_scc, |vcc_lo|
+// W32: encoding: [0x7b,0x02,0x05,0xd4,0xfd,0xd4,0x00,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], vcc_hi, 0xfe0b
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], |exec_hi|, null
+// W64: encoding: [0x0a,0x01,0x05,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x05,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 vcc, 0.5, -m0
+// W64: encoding: [0x6a,0x00,0x05,0xd4,0xf0,0xfa,0x00,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 ttmp[14:15], -src_scc, |vcc_lo|
+// W64: encoding: [0x7a,0x02,0x05,0xd4,0xfd,0xd4,0x00,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7c,0x83,0x05,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cmp_lg_f32_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x15,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x15,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x15,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x15,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x15,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s5, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x00,0x15,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x15,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x15,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x15,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s5, |exec_hi|, null
+// W32: encoding: [0x05,0x01,0x15,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x15,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x15,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 vcc_hi, 0.5, -m0
+// W32: encoding: [0x6b,0x00,0x15,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 ttmp15, -src_scc, |vcc_lo|
+// W32: encoding: [0x7b,0x02,0x15,0xd4,0xfd,0xd4,0x00,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x15,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x15,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x15,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x15,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x15,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], vcc_hi, 0xaf123456
+// W64: encoding: [0x0a,0x00,0x15,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x15,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x15,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x15,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], |exec_hi|, null
+// W64: encoding: [0x0a,0x01,0x15,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x15,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x15,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 vcc, 0.5, -m0
+// W64: encoding: [0x6a,0x00,0x15,0xd4,0xf0,0xfa,0x00,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 ttmp[14:15], -src_scc, |vcc_lo|
+// W64: encoding: [0x7a,0x02,0x15,0xd4,0xfd,0xd4,0x00,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 null, -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7c,0x83,0x15,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cmp_lg_f64_e64 s5, v[1:2], v[2:3]
+// W32: encoding: [0x05,0x00,0x25,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s5, v[254:255], v[254:255]
+// W32: encoding: [0x05,0x00,0x25,0xd4,0xfe,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s5, s[2:3], s[4:5]
+// W32: encoding: [0x05,0x00,0x25,0xd4,0x02,0x08,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s5, s[104:105], s[104:105]
+// W32: encoding: [0x05,0x00,0x25,0xd4,0x68,0xd0,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s5, vcc, ttmp[14:15]
+// W32: encoding: [0x05,0x00,0x25,0xd4,0x6a,0xf4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s5, ttmp[14:15], 0xaf123456
+// W32: encoding: [0x05,0x00,0x25,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s5, -|exec|, src_scc
+// W32: encoding: [0x05,0x01,0x25,0xd4,0x7e,0xfa,0x01,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s105, null, 0.5
+// W32: encoding: [0x69,0x00,0x25,0xd4,0x7c,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 vcc_lo, -1, -1
+// W32: encoding: [0x6a,0x00,0x25,0xd4,0xc1,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 vcc_hi, 0.5, null
+// W32: encoding: [0x6b,0x00,0x25,0xd4,0xf0,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 ttmp15, -|src_scc|, -|exec|
+// W32: encoding: [0x7b,0x03,0x25,0xd4,0xfd,0xfc,0x00,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], v[254:255], v[254:255]
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0xfe,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], s[2:3], s[4:5]
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0x02,0x08,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], s[104:105], s[104:105]
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0x68,0xd0,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], vcc, ttmp[14:15]
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0x6a,0xf4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], ttmp[14:15], 0xaf123456
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], -|exec|, src_scc
+// W64: encoding: [0x0a,0x01,0x25,0xd4,0x7e,0xfa,0x01,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], null, 0.5
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0x7c,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[104:105], -1, -1
+// W64: encoding: [0x68,0x00,0x25,0xd4,0xc1,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 vcc, 0.5, null
+// W64: encoding: [0x6a,0x00,0x25,0xd4,0xf0,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 ttmp[14:15], -|src_scc|, -|exec|
+// W64: encoding: [0x7a,0x03,0x25,0xd4,0xfd,0xfc,0x00,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 null, 0xaf123456, -|vcc| clamp
+// GFX12: encoding: [0x7c,0x82,0x25,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+
+v_cmp_lt_f16_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x01,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x01,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x01,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x01,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x01,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s5, vcc_hi, 0xfe0b
+// W32: encoding: [0x05,0x00,0x01,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x01,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x01,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x01,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s5, |exec_hi|, null
+// W32: encoding: [0x05,0x01,0x01,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x01,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x01,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 vcc_hi, 0.5, -m0
+// W32: encoding: [0x6b,0x00,0x01,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 ttmp15, -src_scc, |vcc_lo|
+// W32: encoding: [0x7b,0x02,0x01,0xd4,0xfd,0xd4,0x00,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], vcc_hi, 0xfe0b
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], |exec_hi|, null
+// W64: encoding: [0x0a,0x01,0x01,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x01,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 vcc, 0.5, -m0
+// W64: encoding: [0x6a,0x00,0x01,0xd4,0xf0,0xfa,0x00,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 ttmp[14:15], -src_scc, |vcc_lo|
+// W64: encoding: [0x7a,0x02,0x01,0xd4,0xfd,0xd4,0x00,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7c,0x83,0x01,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cmp_lt_f32_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x11,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x11,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x11,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x11,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x11,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s5, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x00,0x11,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x11,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x11,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x11,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s5, |exec_hi|, null
+// W32: encoding: [0x05,0x01,0x11,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x11,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x11,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 vcc_hi, 0.5, -m0
+// W32: encoding: [0x6b,0x00,0x11,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 ttmp15, -src_scc, |vcc_lo|
+// W32: encoding: [0x7b,0x02,0x11,0xd4,0xfd,0xd4,0x00,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x11,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x11,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x11,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x11,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x11,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], vcc_hi, 0xaf123456
+// W64: encoding: [0x0a,0x00,0x11,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x11,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x11,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x11,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], |exec_hi|, null
+// W64: encoding: [0x0a,0x01,0x11,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x11,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x11,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 vcc, 0.5, -m0
+// W64: encoding: [0x6a,0x00,0x11,0xd4,0xf0,0xfa,0x00,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 ttmp[14:15], -src_scc, |vcc_lo|
+// W64: encoding: [0x7a,0x02,0x11,0xd4,0xfd,0xd4,0x00,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 null, -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7c,0x83,0x11,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cmp_lt_f64_e64 s5, v[1:2], v[2:3]
+// W32: encoding: [0x05,0x00,0x21,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s5, v[254:255], v[254:255]
+// W32: encoding: [0x05,0x00,0x21,0xd4,0xfe,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s5, s[2:3], s[4:5]
+// W32: encoding: [0x05,0x00,0x21,0xd4,0x02,0x08,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s5, s[104:105], s[104:105]
+// W32: encoding: [0x05,0x00,0x21,0xd4,0x68,0xd0,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s5, vcc, ttmp[14:15]
+// W32: encoding: [0x05,0x00,0x21,0xd4,0x6a,0xf4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s5, ttmp[14:15], 0xaf123456
+// W32: encoding: [0x05,0x00,0x21,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s5, -|exec|, src_scc
+// W32: encoding: [0x05,0x01,0x21,0xd4,0x7e,0xfa,0x01,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s105, null, 0.5
+// W32: encoding: [0x69,0x00,0x21,0xd4,0x7c,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 vcc_lo, -1, -1
+// W32: encoding: [0x6a,0x00,0x21,0xd4,0xc1,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 vcc_hi, 0.5, null
+// W32: encoding: [0x6b,0x00,0x21,0xd4,0xf0,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 ttmp15, -|src_scc|, -|exec|
+// W32: encoding: [0x7b,0x03,0x21,0xd4,0xfd,0xfc,0x00,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], v[254:255], v[254:255]
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0xfe,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], s[2:3], s[4:5]
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0x02,0x08,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], s[104:105], s[104:105]
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0x68,0xd0,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], vcc, ttmp[14:15]
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0x6a,0xf4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], ttmp[14:15], 0xaf123456
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], -|exec|, src_scc
+// W64: encoding: [0x0a,0x01,0x21,0xd4,0x7e,0xfa,0x01,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], null, 0.5
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0x7c,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[104:105], -1, -1
+// W64: encoding: [0x68,0x00,0x21,0xd4,0xc1,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 vcc, 0.5, null
+// W64: encoding: [0x6a,0x00,0x21,0xd4,0xf0,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 ttmp[14:15], -|src_scc|, -|exec|
+// W64: encoding: [0x7a,0x03,0x21,0xd4,0xfd,0xfc,0x00,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 null, 0xaf123456, -|vcc| clamp
+// GFX12: encoding: [0x7c,0x82,0x21,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+
+v_cmp_lt_i16_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x31,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x31,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x31,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x31,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x31,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s5, vcc_hi, 0xfe0b
+// W32: encoding: [0x05,0x00,0x31,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x31,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x31,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x31,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s5, exec_hi, null
+// W32: encoding: [0x05,0x00,0x31,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x31,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x31,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 vcc_hi, 0.5, m0
+// W32: encoding: [0x6b,0x00,0x31,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x7b,0x00,0x31,0xd4,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x31,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x31,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x31,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x31,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x31,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], vcc_hi, 0xfe0b
+// W64: encoding: [0x0a,0x00,0x31,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x31,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x31,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x31,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], exec_hi, null
+// W64: encoding: [0x0a,0x00,0x31,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x31,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x31,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 vcc, 0.5, m0
+// W64: encoding: [0x6a,0x00,0x31,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x7a,0x00,0x31,0xd4,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 null, 0xfe0b, vcc_hi
+// GFX12: encoding: [0x7c,0x00,0x31,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmp_lt_i32_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x41,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x41,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x41,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x41,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x41,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s5, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x00,0x41,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x41,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x41,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x41,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s5, exec_hi, null
+// W32: encoding: [0x05,0x00,0x41,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x41,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x41,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 vcc_hi, 0.5, m0
+// W32: encoding: [0x6b,0x00,0x41,0xd4,0xf0,0xfa,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x7b,0x00,0x41,0xd4,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x41,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x41,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x41,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x41,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x41,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], vcc_hi, 0xaf123456
+// W64: encoding: [0x0a,0x00,0x41,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x41,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x41,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x41,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], exec_hi, null
+// W64: encoding: [0x0a,0x00,0x41,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x41,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x41,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 vcc, 0.5, m0
+// W64: encoding: [0x6a,0x00,0x41,0xd4,0xf0,0xfa,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x7a,0x00,0x41,0xd4,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 null, 0xaf123456, vcc_hi
+// GFX12: encoding: [0x7c,0x00,0x41,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmp_lt_i64_e64 s5, v[1:2], v[2:3]
+// W32: encoding: [0x05,0x00,0x51,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s5, v[254:255], v[254:255]
+// W32: encoding: [0x05,0x00,0x51,0xd4,0xfe,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s5, s[2:3], s[4:5]
+// W32: encoding: [0x05,0x00,0x51,0xd4,0x02,0x08,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s5, s[104:105], s[104:105]
+// W32: encoding: [0x05,0x00,0x51,0xd4,0x68,0xd0,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s5, vcc, ttmp[14:15]
+// W32: encoding: [0x05,0x00,0x51,0xd4,0x6a,0xf4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s5, ttmp[14:15], 0xaf123456
+// W32: encoding: [0x05,0x00,0x51,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s5, exec, src_scc
+// W32: encoding: [0x05,0x00,0x51,0xd4,0x7e,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s105, null, 0.5
+// W32: encoding: [0x69,0x00,0x51,0xd4,0x7c,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 vcc_lo, -1, -1
+// W32: encoding: [0x6a,0x00,0x51,0xd4,0xc1,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 vcc_hi, 0.5, null
+// W32: encoding: [0x6b,0x00,0x51,0xd4,0xf0,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 ttmp15, src_scc, exec
+// W32: encoding: [0x7b,0x00,0x51,0xd4,0xfd,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x51,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], v[254:255], v[254:255]
+// W64: encoding: [0x0a,0x00,0x51,0xd4,0xfe,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], s[2:3], s[4:5]
+// W64: encoding: [0x0a,0x00,0x51,0xd4,0x02,0x08,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], s[104:105], s[104:105]
+// W64: encoding: [0x0a,0x00,0x51,0xd4,0x68,0xd0,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], vcc, ttmp[14:15]
+// W64: encoding: [0x0a,0x00,0x51,0xd4,0x6a,0xf4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], ttmp[14:15], 0xaf123456
+// W64: encoding: [0x0a,0x00,0x51,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], exec, src_scc
+// W64: encoding: [0x0a,0x00,0x51,0xd4,0x7e,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], null, 0.5
+// W64: encoding: [0x0a,0x00,0x51,0xd4,0x7c,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[104:105], -1, -1
+// W64: encoding: [0x68,0x00,0x51,0xd4,0xc1,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 vcc, 0.5, null
+// W64: encoding: [0x6a,0x00,0x51,0xd4,0xf0,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 ttmp[14:15], src_scc, exec
+// W64: encoding: [0x7a,0x00,0x51,0xd4,0xfd,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 null, 0xaf123456, vcc
+// GFX12: encoding: [0x7c,0x00,0x51,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmp_lt_u16_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x39,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x39,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x39,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x39,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x39,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s5, vcc_hi, 0xfe0b
+// W32: encoding: [0x05,0x00,0x39,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x39,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x39,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x39,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s5, exec_hi, null
+// W32: encoding: [0x05,0x00,0x39,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x39,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x39,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 vcc_hi, 0.5, m0
+// W32: encoding: [0x6b,0x00,0x39,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x7b,0x00,0x39,0xd4,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x39,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x39,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x39,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x39,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x39,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], vcc_hi, 0xfe0b
+// W64: encoding: [0x0a,0x00,0x39,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x39,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x39,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x39,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], exec_hi, null
+// W64: encoding: [0x0a,0x00,0x39,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x39,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x39,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 vcc, 0.5, m0
+// W64: encoding: [0x6a,0x00,0x39,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x7a,0x00,0x39,0xd4,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 null, 0xfe0b, vcc_hi
+// GFX12: encoding: [0x7c,0x00,0x39,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmp_lt_u32_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x49,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x49,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x49,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x49,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x49,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s5, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x00,0x49,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x49,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x49,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x49,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s5, exec_hi, null
+// W32: encoding: [0x05,0x00,0x49,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x49,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x49,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 vcc_hi, 0.5, m0
+// W32: encoding: [0x6b,0x00,0x49,0xd4,0xf0,0xfa,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x7b,0x00,0x49,0xd4,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x49,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x49,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x49,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x49,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x49,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], vcc_hi, 0xaf123456
+// W64: encoding: [0x0a,0x00,0x49,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x49,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x49,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x49,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], exec_hi, null
+// W64: encoding: [0x0a,0x00,0x49,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x49,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x49,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 vcc, 0.5, m0
+// W64: encoding: [0x6a,0x00,0x49,0xd4,0xf0,0xfa,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x7a,0x00,0x49,0xd4,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 null, 0xaf123456, vcc_hi
+// GFX12: encoding: [0x7c,0x00,0x49,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmp_lt_u64_e64 s5, v[1:2], v[2:3]
+// W32: encoding: [0x05,0x00,0x59,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s5, v[254:255], v[254:255]
+// W32: encoding: [0x05,0x00,0x59,0xd4,0xfe,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s5, s[2:3], s[4:5]
+// W32: encoding: [0x05,0x00,0x59,0xd4,0x02,0x08,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s5, s[104:105], s[104:105]
+// W32: encoding: [0x05,0x00,0x59,0xd4,0x68,0xd0,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s5, vcc, ttmp[14:15]
+// W32: encoding: [0x05,0x00,0x59,0xd4,0x6a,0xf4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s5, ttmp[14:15], 0xaf123456
+// W32: encoding: [0x05,0x00,0x59,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s5, exec, src_scc
+// W32: encoding: [0x05,0x00,0x59,0xd4,0x7e,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s105, null, 0.5
+// W32: encoding: [0x69,0x00,0x59,0xd4,0x7c,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 vcc_lo, -1, -1
+// W32: encoding: [0x6a,0x00,0x59,0xd4,0xc1,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 vcc_hi, 0.5, null
+// W32: encoding: [0x6b,0x00,0x59,0xd4,0xf0,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 ttmp15, src_scc, exec
+// W32: encoding: [0x7b,0x00,0x59,0xd4,0xfd,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x59,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], v[254:255], v[254:255]
+// W64: encoding: [0x0a,0x00,0x59,0xd4,0xfe,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], s[2:3], s[4:5]
+// W64: encoding: [0x0a,0x00,0x59,0xd4,0x02,0x08,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], s[104:105], s[104:105]
+// W64: encoding: [0x0a,0x00,0x59,0xd4,0x68,0xd0,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], vcc, ttmp[14:15]
+// W64: encoding: [0x0a,0x00,0x59,0xd4,0x6a,0xf4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], ttmp[14:15], 0xaf123456
+// W64: encoding: [0x0a,0x00,0x59,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], exec, src_scc
+// W64: encoding: [0x0a,0x00,0x59,0xd4,0x7e,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], null, 0.5
+// W64: encoding: [0x0a,0x00,0x59,0xd4,0x7c,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[104:105], -1, -1
+// W64: encoding: [0x68,0x00,0x59,0xd4,0xc1,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 vcc, 0.5, null
+// W64: encoding: [0x6a,0x00,0x59,0xd4,0xf0,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 ttmp[14:15], src_scc, exec
+// W64: encoding: [0x7a,0x00,0x59,0xd4,0xfd,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 null, 0xaf123456, vcc
+// GFX12: encoding: [0x7c,0x00,0x59,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmp_ne_i16_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x35,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x35,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x35,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x35,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x35,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s5, vcc_hi, 0xfe0b
+// W32: encoding: [0x05,0x00,0x35,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x35,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x35,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x35,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s5, exec_hi, null
+// W32: encoding: [0x05,0x00,0x35,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x35,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x35,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 vcc_hi, 0.5, m0
+// W32: encoding: [0x6b,0x00,0x35,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x7b,0x00,0x35,0xd4,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x35,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x35,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x35,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x35,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x35,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], vcc_hi, 0xfe0b
+// W64: encoding: [0x0a,0x00,0x35,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x35,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x35,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x35,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], exec_hi, null
+// W64: encoding: [0x0a,0x00,0x35,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x35,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x35,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 vcc, 0.5, m0
+// W64: encoding: [0x6a,0x00,0x35,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x7a,0x00,0x35,0xd4,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 null, 0xfe0b, vcc_hi
+// GFX12: encoding: [0x7c,0x00,0x35,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmp_ne_i32_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x45,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x45,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x45,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x45,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x45,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s5, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x00,0x45,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x45,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x45,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x45,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s5, exec_hi, null
+// W32: encoding: [0x05,0x00,0x45,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x45,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x45,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 vcc_hi, 0.5, m0
+// W32: encoding: [0x6b,0x00,0x45,0xd4,0xf0,0xfa,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x7b,0x00,0x45,0xd4,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x45,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x45,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x45,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x45,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x45,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], vcc_hi, 0xaf123456
+// W64: encoding: [0x0a,0x00,0x45,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x45,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x45,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x45,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], exec_hi, null
+// W64: encoding: [0x0a,0x00,0x45,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x45,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x45,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 vcc, 0.5, m0
+// W64: encoding: [0x6a,0x00,0x45,0xd4,0xf0,0xfa,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x7a,0x00,0x45,0xd4,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 null, 0xaf123456, vcc_hi
+// GFX12: encoding: [0x7c,0x00,0x45,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmp_ne_i64_e64 s5, v[1:2], v[2:3]
+// W32: encoding: [0x05,0x00,0x55,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s5, v[254:255], v[254:255]
+// W32: encoding: [0x05,0x00,0x55,0xd4,0xfe,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s5, s[2:3], s[4:5]
+// W32: encoding: [0x05,0x00,0x55,0xd4,0x02,0x08,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s5, s[104:105], s[104:105]
+// W32: encoding: [0x05,0x00,0x55,0xd4,0x68,0xd0,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s5, vcc, ttmp[14:15]
+// W32: encoding: [0x05,0x00,0x55,0xd4,0x6a,0xf4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s5, ttmp[14:15], 0xaf123456
+// W32: encoding: [0x05,0x00,0x55,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s5, exec, src_scc
+// W32: encoding: [0x05,0x00,0x55,0xd4,0x7e,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s105, null, 0.5
+// W32: encoding: [0x69,0x00,0x55,0xd4,0x7c,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 vcc_lo, -1, -1
+// W32: encoding: [0x6a,0x00,0x55,0xd4,0xc1,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 vcc_hi, 0.5, null
+// W32: encoding: [0x6b,0x00,0x55,0xd4,0xf0,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 ttmp15, src_scc, exec
+// W32: encoding: [0x7b,0x00,0x55,0xd4,0xfd,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x55,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], v[254:255], v[254:255]
+// W64: encoding: [0x0a,0x00,0x55,0xd4,0xfe,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], s[2:3], s[4:5]
+// W64: encoding: [0x0a,0x00,0x55,0xd4,0x02,0x08,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], s[104:105], s[104:105]
+// W64: encoding: [0x0a,0x00,0x55,0xd4,0x68,0xd0,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], vcc, ttmp[14:15]
+// W64: encoding: [0x0a,0x00,0x55,0xd4,0x6a,0xf4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], ttmp[14:15], 0xaf123456
+// W64: encoding: [0x0a,0x00,0x55,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], exec, src_scc
+// W64: encoding: [0x0a,0x00,0x55,0xd4,0x7e,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], null, 0.5
+// W64: encoding: [0x0a,0x00,0x55,0xd4,0x7c,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[104:105], -1, -1
+// W64: encoding: [0x68,0x00,0x55,0xd4,0xc1,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 vcc, 0.5, null
+// W64: encoding: [0x6a,0x00,0x55,0xd4,0xf0,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 ttmp[14:15], src_scc, exec
+// W64: encoding: [0x7a,0x00,0x55,0xd4,0xfd,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 null, 0xaf123456, vcc
+// GFX12: encoding: [0x7c,0x00,0x55,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmp_ne_u16_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x3d,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x3d,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x3d,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x3d,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x3d,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s5, vcc_hi, 0xfe0b
+// W32: encoding: [0x05,0x00,0x3d,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x3d,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x3d,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x3d,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s5, exec_hi, null
+// W32: encoding: [0x05,0x00,0x3d,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x3d,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x3d,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 vcc_hi, 0.5, m0
+// W32: encoding: [0x6b,0x00,0x3d,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x7b,0x00,0x3d,0xd4,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x3d,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x3d,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x3d,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x3d,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x3d,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], vcc_hi, 0xfe0b
+// W64: encoding: [0x0a,0x00,0x3d,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x3d,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x3d,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x3d,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], exec_hi, null
+// W64: encoding: [0x0a,0x00,0x3d,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x3d,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x3d,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 vcc, 0.5, m0
+// W64: encoding: [0x6a,0x00,0x3d,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x7a,0x00,0x3d,0xd4,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 null, 0xfe0b, vcc_hi
+// GFX12: encoding: [0x7c,0x00,0x3d,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmp_ne_u32_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x4d,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x4d,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x4d,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x4d,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x4d,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s5, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x00,0x4d,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x4d,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x4d,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x4d,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s5, exec_hi, null
+// W32: encoding: [0x05,0x00,0x4d,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x4d,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x4d,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 vcc_hi, 0.5, m0
+// W32: encoding: [0x6b,0x00,0x4d,0xd4,0xf0,0xfa,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 ttmp15, src_scc, vcc_lo
+// W32: encoding: [0x7b,0x00,0x4d,0xd4,0xfd,0xd4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x4d,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x4d,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x4d,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x4d,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x4d,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], vcc_hi, 0xaf123456
+// W64: encoding: [0x0a,0x00,0x4d,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x4d,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x4d,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x4d,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], exec_hi, null
+// W64: encoding: [0x0a,0x00,0x4d,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x4d,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x4d,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 vcc, 0.5, m0
+// W64: encoding: [0x6a,0x00,0x4d,0xd4,0xf0,0xfa,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 ttmp[14:15], src_scc, vcc_lo
+// W64: encoding: [0x7a,0x00,0x4d,0xd4,0xfd,0xd4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 null, 0xaf123456, vcc_hi
+// GFX12: encoding: [0x7c,0x00,0x4d,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmp_ne_u64_e64 s5, v[1:2], v[2:3]
+// W32: encoding: [0x05,0x00,0x5d,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s5, v[254:255], v[254:255]
+// W32: encoding: [0x05,0x00,0x5d,0xd4,0xfe,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s5, s[2:3], s[4:5]
+// W32: encoding: [0x05,0x00,0x5d,0xd4,0x02,0x08,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s5, s[104:105], s[104:105]
+// W32: encoding: [0x05,0x00,0x5d,0xd4,0x68,0xd0,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s5, vcc, ttmp[14:15]
+// W32: encoding: [0x05,0x00,0x5d,0xd4,0x6a,0xf4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s5, ttmp[14:15], 0xaf123456
+// W32: encoding: [0x05,0x00,0x5d,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s5, exec, src_scc
+// W32: encoding: [0x05,0x00,0x5d,0xd4,0x7e,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s105, null, 0.5
+// W32: encoding: [0x69,0x00,0x5d,0xd4,0x7c,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 vcc_lo, -1, -1
+// W32: encoding: [0x6a,0x00,0x5d,0xd4,0xc1,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 vcc_hi, 0.5, null
+// W32: encoding: [0x6b,0x00,0x5d,0xd4,0xf0,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 ttmp15, src_scc, exec
+// W32: encoding: [0x7b,0x00,0x5d,0xd4,0xfd,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x5d,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], v[254:255], v[254:255]
+// W64: encoding: [0x0a,0x00,0x5d,0xd4,0xfe,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], s[2:3], s[4:5]
+// W64: encoding: [0x0a,0x00,0x5d,0xd4,0x02,0x08,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], s[104:105], s[104:105]
+// W64: encoding: [0x0a,0x00,0x5d,0xd4,0x68,0xd0,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], vcc, ttmp[14:15]
+// W64: encoding: [0x0a,0x00,0x5d,0xd4,0x6a,0xf4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], ttmp[14:15], 0xaf123456
+// W64: encoding: [0x0a,0x00,0x5d,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], exec, src_scc
+// W64: encoding: [0x0a,0x00,0x5d,0xd4,0x7e,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], null, 0.5
+// W64: encoding: [0x0a,0x00,0x5d,0xd4,0x7c,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[104:105], -1, -1
+// W64: encoding: [0x68,0x00,0x5d,0xd4,0xc1,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 vcc, 0.5, null
+// W64: encoding: [0x6a,0x00,0x5d,0xd4,0xf0,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 ttmp[14:15], src_scc, exec
+// W64: encoding: [0x7a,0x00,0x5d,0xd4,0xfd,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 null, 0xaf123456, vcc
+// GFX12: encoding: [0x7c,0x00,0x5d,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmp_neq_f16_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x0d,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x0d,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x0d,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x0d,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x0d,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s5, vcc_hi, 0xfe0b
+// W32: encoding: [0x05,0x00,0x0d,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x0d,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x0d,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x0d,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s5, |exec_hi|, null
+// W32: encoding: [0x05,0x01,0x0d,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x0d,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x0d,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 vcc_hi, 0.5, -m0
+// W32: encoding: [0x6b,0x00,0x0d,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 ttmp15, -src_scc, |vcc_lo|
+// W32: encoding: [0x7b,0x02,0x0d,0xd4,0xfd,0xd4,0x00,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], vcc_hi, 0xfe0b
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], |exec_hi|, null
+// W64: encoding: [0x0a,0x01,0x0d,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x0d,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 vcc, 0.5, -m0
+// W64: encoding: [0x6a,0x00,0x0d,0xd4,0xf0,0xfa,0x00,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 ttmp[14:15], -src_scc, |vcc_lo|
+// W64: encoding: [0x7a,0x02,0x0d,0xd4,0xfd,0xd4,0x00,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7c,0x83,0x0d,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cmp_neq_f32_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x1d,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x1d,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x1d,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x1d,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x1d,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s5, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x00,0x1d,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x1d,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x1d,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x1d,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s5, |exec_hi|, null
+// W32: encoding: [0x05,0x01,0x1d,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x1d,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x1d,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 vcc_hi, 0.5, -m0
+// W32: encoding: [0x6b,0x00,0x1d,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 ttmp15, -src_scc, |vcc_lo|
+// W32: encoding: [0x7b,0x02,0x1d,0xd4,0xfd,0xd4,0x00,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x1d,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x1d,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x1d,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x1d,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x1d,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], vcc_hi, 0xaf123456
+// W64: encoding: [0x0a,0x00,0x1d,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x1d,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x1d,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x1d,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], |exec_hi|, null
+// W64: encoding: [0x0a,0x01,0x1d,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x1d,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x1d,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 vcc, 0.5, -m0
+// W64: encoding: [0x6a,0x00,0x1d,0xd4,0xf0,0xfa,0x00,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 ttmp[14:15], -src_scc, |vcc_lo|
+// W64: encoding: [0x7a,0x02,0x1d,0xd4,0xfd,0xd4,0x00,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 null, -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7c,0x83,0x1d,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cmp_neq_f64_e64 s5, v[1:2], v[2:3]
+// W32: encoding: [0x05,0x00,0x2d,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s5, v[254:255], v[254:255]
+// W32: encoding: [0x05,0x00,0x2d,0xd4,0xfe,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s5, s[2:3], s[4:5]
+// W32: encoding: [0x05,0x00,0x2d,0xd4,0x02,0x08,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s5, s[104:105], s[104:105]
+// W32: encoding: [0x05,0x00,0x2d,0xd4,0x68,0xd0,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s5, vcc, ttmp[14:15]
+// W32: encoding: [0x05,0x00,0x2d,0xd4,0x6a,0xf4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s5, ttmp[14:15], 0xaf123456
+// W32: encoding: [0x05,0x00,0x2d,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s5, -|exec|, src_scc
+// W32: encoding: [0x05,0x01,0x2d,0xd4,0x7e,0xfa,0x01,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s105, null, 0.5
+// W32: encoding: [0x69,0x00,0x2d,0xd4,0x7c,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 vcc_lo, -1, -1
+// W32: encoding: [0x6a,0x00,0x2d,0xd4,0xc1,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 vcc_hi, 0.5, null
+// W32: encoding: [0x6b,0x00,0x2d,0xd4,0xf0,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 ttmp15, -|src_scc|, -|exec|
+// W32: encoding: [0x7b,0x03,0x2d,0xd4,0xfd,0xfc,0x00,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], v[254:255], v[254:255]
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0xfe,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], s[2:3], s[4:5]
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x02,0x08,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], s[104:105], s[104:105]
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x68,0xd0,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], vcc, ttmp[14:15]
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x6a,0xf4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], ttmp[14:15], 0xaf123456
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], -|exec|, src_scc
+// W64: encoding: [0x0a,0x01,0x2d,0xd4,0x7e,0xfa,0x01,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], null, 0.5
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x7c,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[104:105], -1, -1
+// W64: encoding: [0x68,0x00,0x2d,0xd4,0xc1,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 vcc, 0.5, null
+// W64: encoding: [0x6a,0x00,0x2d,0xd4,0xf0,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 ttmp[14:15], -|src_scc|, -|exec|
+// W64: encoding: [0x7a,0x03,0x2d,0xd4,0xfd,0xfc,0x00,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 null, 0xaf123456, -|vcc| clamp
+// GFX12: encoding: [0x7c,0x82,0x2d,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+
+v_cmp_nge_f16_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x09,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x09,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x09,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x09,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x09,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s5, vcc_hi, 0xfe0b
+// W32: encoding: [0x05,0x00,0x09,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x09,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x09,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x09,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s5, |exec_hi|, null
+// W32: encoding: [0x05,0x01,0x09,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x09,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x09,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 vcc_hi, 0.5, -m0
+// W32: encoding: [0x6b,0x00,0x09,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 ttmp15, -src_scc, |vcc_lo|
+// W32: encoding: [0x7b,0x02,0x09,0xd4,0xfd,0xd4,0x00,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], vcc_hi, 0xfe0b
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], |exec_hi|, null
+// W64: encoding: [0x0a,0x01,0x09,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x09,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 vcc, 0.5, -m0
+// W64: encoding: [0x6a,0x00,0x09,0xd4,0xf0,0xfa,0x00,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 ttmp[14:15], -src_scc, |vcc_lo|
+// W64: encoding: [0x7a,0x02,0x09,0xd4,0xfd,0xd4,0x00,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7c,0x83,0x09,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cmp_nge_f32_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x19,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x19,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x19,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x19,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x19,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s5, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x00,0x19,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x19,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x19,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x19,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s5, |exec_hi|, null
+// W32: encoding: [0x05,0x01,0x19,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x19,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x19,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 vcc_hi, 0.5, -m0
+// W32: encoding: [0x6b,0x00,0x19,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 ttmp15, -src_scc, |vcc_lo|
+// W32: encoding: [0x7b,0x02,0x19,0xd4,0xfd,0xd4,0x00,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x19,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x19,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x19,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x19,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x19,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], vcc_hi, 0xaf123456
+// W64: encoding: [0x0a,0x00,0x19,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x19,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x19,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x19,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], |exec_hi|, null
+// W64: encoding: [0x0a,0x01,0x19,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x19,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x19,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 vcc, 0.5, -m0
+// W64: encoding: [0x6a,0x00,0x19,0xd4,0xf0,0xfa,0x00,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 ttmp[14:15], -src_scc, |vcc_lo|
+// W64: encoding: [0x7a,0x02,0x19,0xd4,0xfd,0xd4,0x00,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 null, -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7c,0x83,0x19,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cmp_nge_f64_e64 s5, v[1:2], v[2:3]
+// W32: encoding: [0x05,0x00,0x29,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s5, v[254:255], v[254:255]
+// W32: encoding: [0x05,0x00,0x29,0xd4,0xfe,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s5, s[2:3], s[4:5]
+// W32: encoding: [0x05,0x00,0x29,0xd4,0x02,0x08,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s5, s[104:105], s[104:105]
+// W32: encoding: [0x05,0x00,0x29,0xd4,0x68,0xd0,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s5, vcc, ttmp[14:15]
+// W32: encoding: [0x05,0x00,0x29,0xd4,0x6a,0xf4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s5, ttmp[14:15], 0xaf123456
+// W32: encoding: [0x05,0x00,0x29,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s5, -|exec|, src_scc
+// W32: encoding: [0x05,0x01,0x29,0xd4,0x7e,0xfa,0x01,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s105, null, 0.5
+// W32: encoding: [0x69,0x00,0x29,0xd4,0x7c,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 vcc_lo, -1, -1
+// W32: encoding: [0x6a,0x00,0x29,0xd4,0xc1,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 vcc_hi, 0.5, null
+// W32: encoding: [0x6b,0x00,0x29,0xd4,0xf0,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 ttmp15, -|src_scc|, -|exec|
+// W32: encoding: [0x7b,0x03,0x29,0xd4,0xfd,0xfc,0x00,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], v[254:255], v[254:255]
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0xfe,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], s[2:3], s[4:5]
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0x02,0x08,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], s[104:105], s[104:105]
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0x68,0xd0,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], vcc, ttmp[14:15]
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0x6a,0xf4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], ttmp[14:15], 0xaf123456
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], -|exec|, src_scc
+// W64: encoding: [0x0a,0x01,0x29,0xd4,0x7e,0xfa,0x01,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], null, 0.5
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0x7c,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[104:105], -1, -1
+// W64: encoding: [0x68,0x00,0x29,0xd4,0xc1,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 vcc, 0.5, null
+// W64: encoding: [0x6a,0x00,0x29,0xd4,0xf0,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 ttmp[14:15], -|src_scc|, -|exec|
+// W64: encoding: [0x7a,0x03,0x29,0xd4,0xfd,0xfc,0x00,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 null, 0xaf123456, -|vcc| clamp
+// GFX12: encoding: [0x7c,0x82,0x29,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+
+v_cmp_ngt_f16_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x0b,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x0b,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x0b,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x0b,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x0b,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s5, vcc_hi, 0xfe0b
+// W32: encoding: [0x05,0x00,0x0b,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x0b,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x0b,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x0b,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s5, |exec_hi|, null
+// W32: encoding: [0x05,0x01,0x0b,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x0b,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x0b,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 vcc_hi, 0.5, -m0
+// W32: encoding: [0x6b,0x00,0x0b,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 ttmp15, -src_scc, |vcc_lo|
+// W32: encoding: [0x7b,0x02,0x0b,0xd4,0xfd,0xd4,0x00,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], vcc_hi, 0xfe0b
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], |exec_hi|, null
+// W64: encoding: [0x0a,0x01,0x0b,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x0b,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 vcc, 0.5, -m0
+// W64: encoding: [0x6a,0x00,0x0b,0xd4,0xf0,0xfa,0x00,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 ttmp[14:15], -src_scc, |vcc_lo|
+// W64: encoding: [0x7a,0x02,0x0b,0xd4,0xfd,0xd4,0x00,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7c,0x83,0x0b,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x1b,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x1b,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x1b,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x1b,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x1b,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s5, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x00,0x1b,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x1b,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x1b,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x1b,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s5, |exec_hi|, null
+// W32: encoding: [0x05,0x01,0x1b,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x1b,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x1b,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 vcc_hi, 0.5, -m0
+// W32: encoding: [0x6b,0x00,0x1b,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 ttmp15, -src_scc, |vcc_lo|
+// W32: encoding: [0x7b,0x02,0x1b,0xd4,0xfd,0xd4,0x00,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x1b,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x1b,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x1b,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x1b,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x1b,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], vcc_hi, 0xaf123456
+// W64: encoding: [0x0a,0x00,0x1b,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x1b,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x1b,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x1b,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], |exec_hi|, null
+// W64: encoding: [0x0a,0x01,0x1b,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x1b,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x1b,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 vcc, 0.5, -m0
+// W64: encoding: [0x6a,0x00,0x1b,0xd4,0xf0,0xfa,0x00,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 ttmp[14:15], -src_scc, |vcc_lo|
+// W64: encoding: [0x7a,0x02,0x1b,0xd4,0xfd,0xd4,0x00,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 null, -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7c,0x83,0x1b,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cmp_ngt_f64_e64 s5, v[1:2], v[2:3]
+// W32: encoding: [0x05,0x00,0x2b,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s5, v[254:255], v[254:255]
+// W32: encoding: [0x05,0x00,0x2b,0xd4,0xfe,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s5, s[2:3], s[4:5]
+// W32: encoding: [0x05,0x00,0x2b,0xd4,0x02,0x08,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s5, s[104:105], s[104:105]
+// W32: encoding: [0x05,0x00,0x2b,0xd4,0x68,0xd0,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s5, vcc, ttmp[14:15]
+// W32: encoding: [0x05,0x00,0x2b,0xd4,0x6a,0xf4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s5, ttmp[14:15], 0xaf123456
+// W32: encoding: [0x05,0x00,0x2b,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s5, -|exec|, src_scc
+// W32: encoding: [0x05,0x01,0x2b,0xd4,0x7e,0xfa,0x01,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s105, null, 0.5
+// W32: encoding: [0x69,0x00,0x2b,0xd4,0x7c,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 vcc_lo, -1, -1
+// W32: encoding: [0x6a,0x00,0x2b,0xd4,0xc1,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 vcc_hi, 0.5, null
+// W32: encoding: [0x6b,0x00,0x2b,0xd4,0xf0,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 ttmp15, -|src_scc|, -|exec|
+// W32: encoding: [0x7b,0x03,0x2b,0xd4,0xfd,0xfc,0x00,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], v[254:255], v[254:255]
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0xfe,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], s[2:3], s[4:5]
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x02,0x08,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], s[104:105], s[104:105]
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x68,0xd0,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], vcc, ttmp[14:15]
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x6a,0xf4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], ttmp[14:15], 0xaf123456
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], -|exec|, src_scc
+// W64: encoding: [0x0a,0x01,0x2b,0xd4,0x7e,0xfa,0x01,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], null, 0.5
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x7c,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[104:105], -1, -1
+// W64: encoding: [0x68,0x00,0x2b,0xd4,0xc1,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 vcc, 0.5, null
+// W64: encoding: [0x6a,0x00,0x2b,0xd4,0xf0,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 ttmp[14:15], -|src_scc|, -|exec|
+// W64: encoding: [0x7a,0x03,0x2b,0xd4,0xfd,0xfc,0x00,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 null, 0xaf123456, -|vcc| clamp
+// GFX12: encoding: [0x7c,0x82,0x2b,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+
+v_cmp_nle_f16_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x0c,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x0c,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x0c,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x0c,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x0c,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s5, vcc_hi, 0xfe0b
+// W32: encoding: [0x05,0x00,0x0c,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x0c,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x0c,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x0c,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s5, |exec_hi|, null
+// W32: encoding: [0x05,0x01,0x0c,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x0c,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x0c,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 vcc_hi, 0.5, -m0
+// W32: encoding: [0x6b,0x00,0x0c,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 ttmp15, -src_scc, |vcc_lo|
+// W32: encoding: [0x7b,0x02,0x0c,0xd4,0xfd,0xd4,0x00,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], vcc_hi, 0xfe0b
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], |exec_hi|, null
+// W64: encoding: [0x0a,0x01,0x0c,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x0c,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 vcc, 0.5, -m0
+// W64: encoding: [0x6a,0x00,0x0c,0xd4,0xf0,0xfa,0x00,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 ttmp[14:15], -src_scc, |vcc_lo|
+// W64: encoding: [0x7a,0x02,0x0c,0xd4,0xfd,0xd4,0x00,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7c,0x83,0x0c,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cmp_nle_f32_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x1c,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x1c,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x1c,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x1c,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x1c,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s5, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x00,0x1c,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x1c,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x1c,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x1c,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s5, |exec_hi|, null
+// W32: encoding: [0x05,0x01,0x1c,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x1c,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x1c,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 vcc_hi, 0.5, -m0
+// W32: encoding: [0x6b,0x00,0x1c,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 ttmp15, -src_scc, |vcc_lo|
+// W32: encoding: [0x7b,0x02,0x1c,0xd4,0xfd,0xd4,0x00,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x1c,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x1c,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x1c,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x1c,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x1c,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], vcc_hi, 0xaf123456
+// W64: encoding: [0x0a,0x00,0x1c,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x1c,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x1c,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x1c,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], |exec_hi|, null
+// W64: encoding: [0x0a,0x01,0x1c,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x1c,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x1c,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 vcc, 0.5, -m0
+// W64: encoding: [0x6a,0x00,0x1c,0xd4,0xf0,0xfa,0x00,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 ttmp[14:15], -src_scc, |vcc_lo|
+// W64: encoding: [0x7a,0x02,0x1c,0xd4,0xfd,0xd4,0x00,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 null, -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7c,0x83,0x1c,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cmp_nle_f64_e64 s5, v[1:2], v[2:3]
+// W32: encoding: [0x05,0x00,0x2c,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s5, v[254:255], v[254:255]
+// W32: encoding: [0x05,0x00,0x2c,0xd4,0xfe,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s5, s[2:3], s[4:5]
+// W32: encoding: [0x05,0x00,0x2c,0xd4,0x02,0x08,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s5, s[104:105], s[104:105]
+// W32: encoding: [0x05,0x00,0x2c,0xd4,0x68,0xd0,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s5, vcc, ttmp[14:15]
+// W32: encoding: [0x05,0x00,0x2c,0xd4,0x6a,0xf4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s5, ttmp[14:15], 0xaf123456
+// W32: encoding: [0x05,0x00,0x2c,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s5, -|exec|, src_scc
+// W32: encoding: [0x05,0x01,0x2c,0xd4,0x7e,0xfa,0x01,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s105, null, 0.5
+// W32: encoding: [0x69,0x00,0x2c,0xd4,0x7c,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 vcc_lo, -1, -1
+// W32: encoding: [0x6a,0x00,0x2c,0xd4,0xc1,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 vcc_hi, 0.5, null
+// W32: encoding: [0x6b,0x00,0x2c,0xd4,0xf0,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 ttmp15, -|src_scc|, -|exec|
+// W32: encoding: [0x7b,0x03,0x2c,0xd4,0xfd,0xfc,0x00,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], v[254:255], v[254:255]
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0xfe,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], s[2:3], s[4:5]
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x02,0x08,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], s[104:105], s[104:105]
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x68,0xd0,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], vcc, ttmp[14:15]
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x6a,0xf4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], ttmp[14:15], 0xaf123456
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], -|exec|, src_scc
+// W64: encoding: [0x0a,0x01,0x2c,0xd4,0x7e,0xfa,0x01,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], null, 0.5
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x7c,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[104:105], -1, -1
+// W64: encoding: [0x68,0x00,0x2c,0xd4,0xc1,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 vcc, 0.5, null
+// W64: encoding: [0x6a,0x00,0x2c,0xd4,0xf0,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 ttmp[14:15], -|src_scc|, -|exec|
+// W64: encoding: [0x7a,0x03,0x2c,0xd4,0xfd,0xfc,0x00,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 null, 0xaf123456, -|vcc| clamp
+// GFX12: encoding: [0x7c,0x82,0x2c,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+
+v_cmp_nlg_f16_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x0a,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x0a,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x0a,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x0a,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x0a,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s5, vcc_hi, 0xfe0b
+// W32: encoding: [0x05,0x00,0x0a,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x0a,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x0a,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x0a,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s5, |exec_hi|, null
+// W32: encoding: [0x05,0x01,0x0a,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x0a,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x0a,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 vcc_hi, 0.5, -m0
+// W32: encoding: [0x6b,0x00,0x0a,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 ttmp15, -src_scc, |vcc_lo|
+// W32: encoding: [0x7b,0x02,0x0a,0xd4,0xfd,0xd4,0x00,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], vcc_hi, 0xfe0b
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], |exec_hi|, null
+// W64: encoding: [0x0a,0x01,0x0a,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x0a,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 vcc, 0.5, -m0
+// W64: encoding: [0x6a,0x00,0x0a,0xd4,0xf0,0xfa,0x00,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 ttmp[14:15], -src_scc, |vcc_lo|
+// W64: encoding: [0x7a,0x02,0x0a,0xd4,0xfd,0xd4,0x00,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7c,0x83,0x0a,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x1a,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x1a,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x1a,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x1a,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x1a,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s5, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x00,0x1a,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x1a,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x1a,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x1a,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s5, |exec_hi|, null
+// W32: encoding: [0x05,0x01,0x1a,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x1a,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x1a,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 vcc_hi, 0.5, -m0
+// W32: encoding: [0x6b,0x00,0x1a,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 ttmp15, -src_scc, |vcc_lo|
+// W32: encoding: [0x7b,0x02,0x1a,0xd4,0xfd,0xd4,0x00,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x1a,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x1a,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x1a,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x1a,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x1a,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], vcc_hi, 0xaf123456
+// W64: encoding: [0x0a,0x00,0x1a,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x1a,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x1a,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x1a,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], |exec_hi|, null
+// W64: encoding: [0x0a,0x01,0x1a,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x1a,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x1a,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 vcc, 0.5, -m0
+// W64: encoding: [0x6a,0x00,0x1a,0xd4,0xf0,0xfa,0x00,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 ttmp[14:15], -src_scc, |vcc_lo|
+// W64: encoding: [0x7a,0x02,0x1a,0xd4,0xfd,0xd4,0x00,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 null, -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7c,0x83,0x1a,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cmp_nlg_f64_e64 s5, v[1:2], v[2:3]
+// W32: encoding: [0x05,0x00,0x2a,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s5, v[254:255], v[254:255]
+// W32: encoding: [0x05,0x00,0x2a,0xd4,0xfe,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s5, s[2:3], s[4:5]
+// W32: encoding: [0x05,0x00,0x2a,0xd4,0x02,0x08,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s5, s[104:105], s[104:105]
+// W32: encoding: [0x05,0x00,0x2a,0xd4,0x68,0xd0,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s5, vcc, ttmp[14:15]
+// W32: encoding: [0x05,0x00,0x2a,0xd4,0x6a,0xf4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s5, ttmp[14:15], 0xaf123456
+// W32: encoding: [0x05,0x00,0x2a,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s5, -|exec|, src_scc
+// W32: encoding: [0x05,0x01,0x2a,0xd4,0x7e,0xfa,0x01,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s105, null, 0.5
+// W32: encoding: [0x69,0x00,0x2a,0xd4,0x7c,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 vcc_lo, -1, -1
+// W32: encoding: [0x6a,0x00,0x2a,0xd4,0xc1,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 vcc_hi, 0.5, null
+// W32: encoding: [0x6b,0x00,0x2a,0xd4,0xf0,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 ttmp15, -|src_scc|, -|exec|
+// W32: encoding: [0x7b,0x03,0x2a,0xd4,0xfd,0xfc,0x00,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], v[254:255], v[254:255]
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0xfe,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], s[2:3], s[4:5]
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x02,0x08,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], s[104:105], s[104:105]
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x68,0xd0,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], vcc, ttmp[14:15]
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x6a,0xf4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], ttmp[14:15], 0xaf123456
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], -|exec|, src_scc
+// W64: encoding: [0x0a,0x01,0x2a,0xd4,0x7e,0xfa,0x01,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], null, 0.5
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x7c,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[104:105], -1, -1
+// W64: encoding: [0x68,0x00,0x2a,0xd4,0xc1,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 vcc, 0.5, null
+// W64: encoding: [0x6a,0x00,0x2a,0xd4,0xf0,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 ttmp[14:15], -|src_scc|, -|exec|
+// W64: encoding: [0x7a,0x03,0x2a,0xd4,0xfd,0xfc,0x00,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 null, 0xaf123456, -|vcc| clamp
+// GFX12: encoding: [0x7c,0x82,0x2a,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+
+v_cmp_nlt_f16_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x0e,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x0e,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x0e,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x0e,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x0e,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s5, vcc_hi, 0xfe0b
+// W32: encoding: [0x05,0x00,0x0e,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x0e,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x0e,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x0e,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s5, |exec_hi|, null
+// W32: encoding: [0x05,0x01,0x0e,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x0e,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x0e,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 vcc_hi, 0.5, -m0
+// W32: encoding: [0x6b,0x00,0x0e,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 ttmp15, -src_scc, |vcc_lo|
+// W32: encoding: [0x7b,0x02,0x0e,0xd4,0xfd,0xd4,0x00,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], vcc_hi, 0xfe0b
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], |exec_hi|, null
+// W64: encoding: [0x0a,0x01,0x0e,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x0e,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 vcc, 0.5, -m0
+// W64: encoding: [0x6a,0x00,0x0e,0xd4,0xf0,0xfa,0x00,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 ttmp[14:15], -src_scc, |vcc_lo|
+// W64: encoding: [0x7a,0x02,0x0e,0xd4,0xfd,0xd4,0x00,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7c,0x83,0x0e,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x1e,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x1e,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x1e,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x1e,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x1e,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s5, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x00,0x1e,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x1e,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x1e,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x1e,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s5, |exec_hi|, null
+// W32: encoding: [0x05,0x01,0x1e,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x1e,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x1e,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 vcc_hi, 0.5, -m0
+// W32: encoding: [0x6b,0x00,0x1e,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 ttmp15, -src_scc, |vcc_lo|
+// W32: encoding: [0x7b,0x02,0x1e,0xd4,0xfd,0xd4,0x00,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x1e,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x1e,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x1e,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x1e,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x1e,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], vcc_hi, 0xaf123456
+// W64: encoding: [0x0a,0x00,0x1e,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x1e,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x1e,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x1e,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], |exec_hi|, null
+// W64: encoding: [0x0a,0x01,0x1e,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x1e,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x1e,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 vcc, 0.5, -m0
+// W64: encoding: [0x6a,0x00,0x1e,0xd4,0xf0,0xfa,0x00,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 ttmp[14:15], -src_scc, |vcc_lo|
+// W64: encoding: [0x7a,0x02,0x1e,0xd4,0xfd,0xd4,0x00,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 null, -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7c,0x83,0x1e,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cmp_nlt_f64_e64 s5, v[1:2], v[2:3]
+// W32: encoding: [0x05,0x00,0x2e,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s5, v[254:255], v[254:255]
+// W32: encoding: [0x05,0x00,0x2e,0xd4,0xfe,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s5, s[2:3], s[4:5]
+// W32: encoding: [0x05,0x00,0x2e,0xd4,0x02,0x08,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s5, s[104:105], s[104:105]
+// W32: encoding: [0x05,0x00,0x2e,0xd4,0x68,0xd0,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s5, vcc, ttmp[14:15]
+// W32: encoding: [0x05,0x00,0x2e,0xd4,0x6a,0xf4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s5, ttmp[14:15], 0xaf123456
+// W32: encoding: [0x05,0x00,0x2e,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s5, -|exec|, src_scc
+// W32: encoding: [0x05,0x01,0x2e,0xd4,0x7e,0xfa,0x01,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s105, null, 0.5
+// W32: encoding: [0x69,0x00,0x2e,0xd4,0x7c,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 vcc_lo, -1, -1
+// W32: encoding: [0x6a,0x00,0x2e,0xd4,0xc1,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 vcc_hi, 0.5, null
+// W32: encoding: [0x6b,0x00,0x2e,0xd4,0xf0,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 ttmp15, -|src_scc|, -|exec|
+// W32: encoding: [0x7b,0x03,0x2e,0xd4,0xfd,0xfc,0x00,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], v[254:255], v[254:255]
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0xfe,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], s[2:3], s[4:5]
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x02,0x08,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], s[104:105], s[104:105]
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x68,0xd0,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], vcc, ttmp[14:15]
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x6a,0xf4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], ttmp[14:15], 0xaf123456
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], -|exec|, src_scc
+// W64: encoding: [0x0a,0x01,0x2e,0xd4,0x7e,0xfa,0x01,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], null, 0.5
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x7c,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[104:105], -1, -1
+// W64: encoding: [0x68,0x00,0x2e,0xd4,0xc1,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 vcc, 0.5, null
+// W64: encoding: [0x6a,0x00,0x2e,0xd4,0xf0,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 ttmp[14:15], -|src_scc|, -|exec|
+// W64: encoding: [0x7a,0x03,0x2e,0xd4,0xfd,0xfc,0x00,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 null, 0xaf123456, -|vcc| clamp
+// GFX12: encoding: [0x7c,0x82,0x2e,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+
+v_cmp_o_f16_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x07,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x07,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x07,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x07,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x07,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s5, vcc_hi, 0xfe0b
+// W32: encoding: [0x05,0x00,0x07,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x07,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x07,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x07,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s5, |exec_hi|, null
+// W32: encoding: [0x05,0x01,0x07,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x07,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x07,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 vcc_hi, 0.5, -m0
+// W32: encoding: [0x6b,0x00,0x07,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 ttmp15, -src_scc, |vcc_lo|
+// W32: encoding: [0x7b,0x02,0x07,0xd4,0xfd,0xd4,0x00,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], vcc_hi, 0xfe0b
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], |exec_hi|, null
+// W64: encoding: [0x0a,0x01,0x07,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x07,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 vcc, 0.5, -m0
+// W64: encoding: [0x6a,0x00,0x07,0xd4,0xf0,0xfa,0x00,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 ttmp[14:15], -src_scc, |vcc_lo|
+// W64: encoding: [0x7a,0x02,0x07,0xd4,0xfd,0xd4,0x00,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7c,0x83,0x07,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cmp_o_f32_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x17,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x17,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x17,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x17,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x17,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s5, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x00,0x17,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x17,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x17,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x17,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s5, |exec_hi|, null
+// W32: encoding: [0x05,0x01,0x17,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x17,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x17,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 vcc_hi, 0.5, -m0
+// W32: encoding: [0x6b,0x00,0x17,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 ttmp15, -src_scc, |vcc_lo|
+// W32: encoding: [0x7b,0x02,0x17,0xd4,0xfd,0xd4,0x00,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x17,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x17,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x17,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x17,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x17,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], vcc_hi, 0xaf123456
+// W64: encoding: [0x0a,0x00,0x17,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x17,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x17,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x17,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], |exec_hi|, null
+// W64: encoding: [0x0a,0x01,0x17,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x17,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x17,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 vcc, 0.5, -m0
+// W64: encoding: [0x6a,0x00,0x17,0xd4,0xf0,0xfa,0x00,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 ttmp[14:15], -src_scc, |vcc_lo|
+// W64: encoding: [0x7a,0x02,0x17,0xd4,0xfd,0xd4,0x00,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 null, -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7c,0x83,0x17,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cmp_o_f64_e64 s5, v[1:2], v[2:3]
+// W32: encoding: [0x05,0x00,0x27,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s5, v[254:255], v[254:255]
+// W32: encoding: [0x05,0x00,0x27,0xd4,0xfe,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s5, s[2:3], s[4:5]
+// W32: encoding: [0x05,0x00,0x27,0xd4,0x02,0x08,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s5, s[104:105], s[104:105]
+// W32: encoding: [0x05,0x00,0x27,0xd4,0x68,0xd0,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s5, vcc, ttmp[14:15]
+// W32: encoding: [0x05,0x00,0x27,0xd4,0x6a,0xf4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s5, ttmp[14:15], 0xaf123456
+// W32: encoding: [0x05,0x00,0x27,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s5, -|exec|, src_scc
+// W32: encoding: [0x05,0x01,0x27,0xd4,0x7e,0xfa,0x01,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s105, null, 0.5
+// W32: encoding: [0x69,0x00,0x27,0xd4,0x7c,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 vcc_lo, -1, -1
+// W32: encoding: [0x6a,0x00,0x27,0xd4,0xc1,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 vcc_hi, 0.5, null
+// W32: encoding: [0x6b,0x00,0x27,0xd4,0xf0,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 ttmp15, -|src_scc|, -|exec|
+// W32: encoding: [0x7b,0x03,0x27,0xd4,0xfd,0xfc,0x00,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], v[254:255], v[254:255]
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0xfe,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], s[2:3], s[4:5]
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0x02,0x08,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], s[104:105], s[104:105]
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0x68,0xd0,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], vcc, ttmp[14:15]
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0x6a,0xf4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], ttmp[14:15], 0xaf123456
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], -|exec|, src_scc
+// W64: encoding: [0x0a,0x01,0x27,0xd4,0x7e,0xfa,0x01,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], null, 0.5
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0x7c,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[104:105], -1, -1
+// W64: encoding: [0x68,0x00,0x27,0xd4,0xc1,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 vcc, 0.5, null
+// W64: encoding: [0x6a,0x00,0x27,0xd4,0xf0,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 ttmp[14:15], -|src_scc|, -|exec|
+// W64: encoding: [0x7a,0x03,0x27,0xd4,0xfd,0xfc,0x00,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 null, 0xaf123456, -|vcc| clamp
+// GFX12: encoding: [0x7c,0x82,0x27,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+
+v_cmp_u_f16_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x08,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x08,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x08,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x08,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x08,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s5, vcc_hi, 0xfe0b
+// W32: encoding: [0x05,0x00,0x08,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x08,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x08,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x08,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s5, |exec_hi|, null
+// W32: encoding: [0x05,0x01,0x08,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x08,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x08,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 vcc_hi, 0.5, -m0
+// W32: encoding: [0x6b,0x00,0x08,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 ttmp15, -src_scc, |vcc_lo|
+// W32: encoding: [0x7b,0x02,0x08,0xd4,0xfd,0xd4,0x00,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], vcc_hi, 0xfe0b
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], |exec_hi|, null
+// W64: encoding: [0x0a,0x01,0x08,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x08,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 vcc, 0.5, -m0
+// W64: encoding: [0x6a,0x00,0x08,0xd4,0xf0,0xfa,0x00,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 ttmp[14:15], -src_scc, |vcc_lo|
+// W64: encoding: [0x7a,0x02,0x08,0xd4,0xfd,0xd4,0x00,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7c,0x83,0x08,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cmp_u_f32_e64 s5, v1, v2
+// W32: encoding: [0x05,0x00,0x18,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s5, v255, v255
+// W32: encoding: [0x05,0x00,0x18,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s5, s1, s2
+// W32: encoding: [0x05,0x00,0x18,0xd4,0x01,0x04,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s5, s105, s105
+// W32: encoding: [0x05,0x00,0x18,0xd4,0x69,0xd2,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s5, vcc_lo, ttmp15
+// W32: encoding: [0x05,0x00,0x18,0xd4,0x6a,0xf6,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s5, vcc_hi, 0xaf123456
+// W32: encoding: [0x05,0x00,0x18,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s5, ttmp15, src_scc
+// W32: encoding: [0x05,0x00,0x18,0xd4,0x7b,0xfa,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s5, m0, 0.5
+// W32: encoding: [0x05,0x00,0x18,0xd4,0x7d,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s5, exec_lo, -1
+// W32: encoding: [0x05,0x00,0x18,0xd4,0x7e,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s5, |exec_hi|, null
+// W32: encoding: [0x05,0x01,0x18,0xd4,0x7f,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s105, null, exec_lo
+// W32: encoding: [0x69,0x00,0x18,0xd4,0x7c,0xfc,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 vcc_lo, -1, exec_hi
+// W32: encoding: [0x6a,0x00,0x18,0xd4,0xc1,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 vcc_hi, 0.5, -m0
+// W32: encoding: [0x6b,0x00,0x18,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 ttmp15, -src_scc, |vcc_lo|
+// W32: encoding: [0x7b,0x02,0x18,0xd4,0xfd,0xd4,0x00,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x18,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], v255, v255
+// W64: encoding: [0x0a,0x00,0x18,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], s1, s2
+// W64: encoding: [0x0a,0x00,0x18,0xd4,0x01,0x04,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], s105, s105
+// W64: encoding: [0x0a,0x00,0x18,0xd4,0x69,0xd2,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], vcc_lo, ttmp15
+// W64: encoding: [0x0a,0x00,0x18,0xd4,0x6a,0xf6,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], vcc_hi, 0xaf123456
+// W64: encoding: [0x0a,0x00,0x18,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], ttmp15, src_scc
+// W64: encoding: [0x0a,0x00,0x18,0xd4,0x7b,0xfa,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], m0, 0.5
+// W64: encoding: [0x0a,0x00,0x18,0xd4,0x7d,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], exec_lo, -1
+// W64: encoding: [0x0a,0x00,0x18,0xd4,0x7e,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], |exec_hi|, null
+// W64: encoding: [0x0a,0x01,0x18,0xd4,0x7f,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], null, exec_lo
+// W64: encoding: [0x0a,0x00,0x18,0xd4,0x7c,0xfc,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[104:105], -1, exec_hi
+// W64: encoding: [0x68,0x00,0x18,0xd4,0xc1,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 vcc, 0.5, -m0
+// W64: encoding: [0x6a,0x00,0x18,0xd4,0xf0,0xfa,0x00,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 ttmp[14:15], -src_scc, |vcc_lo|
+// W64: encoding: [0x7a,0x02,0x18,0xd4,0xfd,0xd4,0x00,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 null, -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7c,0x83,0x18,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cmp_u_f64_e64 s5, v[1:2], v[2:3]
+// W32: encoding: [0x05,0x00,0x28,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s5, v[254:255], v[254:255]
+// W32: encoding: [0x05,0x00,0x28,0xd4,0xfe,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s5, s[2:3], s[4:5]
+// W32: encoding: [0x05,0x00,0x28,0xd4,0x02,0x08,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s5, s[104:105], s[104:105]
+// W32: encoding: [0x05,0x00,0x28,0xd4,0x68,0xd0,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s5, vcc, ttmp[14:15]
+// W32: encoding: [0x05,0x00,0x28,0xd4,0x6a,0xf4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s5, ttmp[14:15], 0xaf123456
+// W32: encoding: [0x05,0x00,0x28,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s5, -|exec|, src_scc
+// W32: encoding: [0x05,0x01,0x28,0xd4,0x7e,0xfa,0x01,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s105, null, 0.5
+// W32: encoding: [0x69,0x00,0x28,0xd4,0x7c,0xe0,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 vcc_lo, -1, -1
+// W32: encoding: [0x6a,0x00,0x28,0xd4,0xc1,0x82,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 vcc_hi, 0.5, null
+// W32: encoding: [0x6b,0x00,0x28,0xd4,0xf0,0xf8,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 ttmp15, -|src_scc|, -|exec|
+// W32: encoding: [0x7b,0x03,0x28,0xd4,0xfd,0xfc,0x00,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], v[254:255], v[254:255]
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0xfe,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], s[2:3], s[4:5]
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0x02,0x08,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], s[104:105], s[104:105]
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0x68,0xd0,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], vcc, ttmp[14:15]
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0x6a,0xf4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], ttmp[14:15], 0xaf123456
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], -|exec|, src_scc
+// W64: encoding: [0x0a,0x01,0x28,0xd4,0x7e,0xfa,0x01,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], null, 0.5
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0x7c,0xe0,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[104:105], -1, -1
+// W64: encoding: [0x68,0x00,0x28,0xd4,0xc1,0x82,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 vcc, 0.5, null
+// W64: encoding: [0x6a,0x00,0x28,0xd4,0xf0,0xf8,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 ttmp[14:15], -|src_scc|, -|exec|
+// W64: encoding: [0x7a,0x03,0x28,0xd4,0xfd,0xfc,0x00,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 null, 0xaf123456, -|vcc| clamp
+// GFX12: encoding: [0x7c,0x82,0x28,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16.s
new file mode 100644
index 000000000000..ed4718ab29aa
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16.s
@@ -0,0 +1,5782 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W32 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W64 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+
+v_cmp_class_f16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp null, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x01,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x05,0x30]
+
+v_cmp_class_f32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp null, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x01,0x7e,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x05,0x30]
+
+v_cmp_eq_f16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x83,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_eq_f32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x01,0x12,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x02,0x12,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x01,0x12,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x02,0x12,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x83,0x12,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_eq_i16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x00,0x32,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmp_eq_i32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x00,0x42,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmp_eq_u16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x00,0x3a,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmp_eq_u32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x00,0x4a,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmp_ge_f16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x01,0x06,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x02,0x06,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x01,0x06,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x02,0x06,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x83,0x06,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_ge_f32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x01,0x16,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x02,0x16,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x01,0x16,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x02,0x16,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x83,0x16,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_ge_i16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x00,0x36,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmp_ge_i32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x00,0x46,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmp_ge_u16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x00,0x3e,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmp_ge_u32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x00,0x4e,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmp_gt_f16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x01,0x04,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x02,0x04,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x01,0x04,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x02,0x04,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x83,0x04,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_gt_f32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x01,0x14,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x02,0x14,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x01,0x14,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x02,0x14,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x83,0x14,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_gt_i16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x00,0x34,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmp_gt_i32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x00,0x44,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmp_gt_u16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x00,0x3c,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmp_gt_u32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x00,0x4c,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmp_le_f16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x01,0x03,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x02,0x03,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x01,0x03,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x02,0x03,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x83,0x03,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_le_f32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x01,0x13,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x02,0x13,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x01,0x13,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x02,0x13,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x83,0x13,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_le_i16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x00,0x33,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmp_le_i32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x00,0x43,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmp_le_u16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x00,0x3b,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmp_le_u32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x00,0x4b,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmp_lg_f16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x01,0x05,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x02,0x05,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x01,0x05,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x02,0x05,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x83,0x05,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_lg_f32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x01,0x15,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x02,0x15,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x01,0x15,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x02,0x15,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x83,0x15,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_lt_f16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x83,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_lt_f32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x01,0x11,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x02,0x11,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x01,0x11,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x02,0x11,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x83,0x11,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_lt_i16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x00,0x31,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmp_lt_i32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x00,0x41,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmp_lt_u16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x00,0x39,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmp_lt_u32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x00,0x49,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmp_ne_i16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x00,0x35,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmp_ne_i32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x00,0x45,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmp_ne_u16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x00,0x3d,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmp_ne_u32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x00,0x4d,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmp_neq_f16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x01,0x0d,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x02,0x0d,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x01,0x0d,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x02,0x0d,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x83,0x0d,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_neq_f32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x01,0x1d,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x02,0x1d,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x01,0x1d,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x02,0x1d,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x83,0x1d,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_nge_f16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x01,0x09,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x02,0x09,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x01,0x09,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x02,0x09,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x83,0x09,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_nge_f32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x01,0x19,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x02,0x19,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x01,0x19,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x02,0x19,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x83,0x19,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_ngt_f16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x01,0x0b,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x02,0x0b,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x01,0x0b,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x02,0x0b,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x83,0x0b,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_ngt_f32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x01,0x1b,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x02,0x1b,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x01,0x1b,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x02,0x1b,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x83,0x1b,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_nle_f16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x01,0x0c,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x02,0x0c,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x01,0x0c,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x02,0x0c,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x83,0x0c,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_nle_f32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x01,0x1c,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x02,0x1c,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x01,0x1c,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x02,0x1c,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x83,0x1c,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_nlg_f16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x01,0x0a,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x02,0x0a,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x01,0x0a,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x02,0x0a,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x83,0x0a,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_nlg_f32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x01,0x1a,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x02,0x1a,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x01,0x1a,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x02,0x1a,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x83,0x1a,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_nlt_f16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x01,0x0e,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x02,0x0e,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x01,0x0e,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x02,0x0e,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x83,0x0e,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_nlt_f32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x01,0x1e,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x02,0x1e,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x01,0x1e,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x02,0x1e,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x83,0x1e,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_o_f16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x01,0x07,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x02,0x07,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x01,0x07,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x02,0x07,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x83,0x07,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_o_f32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x01,0x17,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x02,0x17,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x01,0x17,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x02,0x17,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x83,0x17,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_u_f16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x01,0x08,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x02,0x08,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x01,0x08,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x02,0x08,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x83,0x08,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_u_f32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
+// W32: [0x05,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
+// W32: [0x05,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp s5, v1, v2 row_mirror
+// W32: [0x05,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp s5, v1, v2 row_half_mirror
+// W32: [0x05,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp s5, v1, v2 row_shl:1
+// W32: [0x05,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp s5, v1, v2 row_shl:15
+// W32: [0x05,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp s5, v1, v2 row_shr:1
+// W32: [0x05,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp s5, v1, v2 row_shr:15
+// W32: [0x05,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp s5, v1, v2 row_ror:1
+// W32: [0x05,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp s105, v1, v2 row_ror:15
+// W32: [0x69,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: [0x6a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: [0x6b,0x01,0x18,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: [0x7b,0x02,0x18,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
+// W64: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
+// W64: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp s[10:11], v1, v2 row_mirror
+// W64: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp s[10:11], v1, v2 row_half_mirror
+// W64: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp s[10:11], v1, v2 row_shl:1
+// W64: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp s[10:11], v1, v2 row_shl:15
+// W64: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp s[10:11], v1, v2 row_shr:1
+// W64: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp s[10:11], v1, v2 row_shr:15
+// W64: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp s[10:11], v1, v2 row_ror:1
+// W64: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp s[10:11], v1, v2 row_ror:15
+// W64: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: [0x68,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: [0x6a,0x01,0x18,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: [0x7a,0x02,0x18,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7c,0x83,0x18,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp8.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp8.s
new file mode 100644
index 000000000000..d3474a339d55
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp8.s
@@ -0,0 +1,2110 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W32 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W64 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+
+v_cmp_class_f16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x00,0x7d,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x00,0x7d,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64_dpp null, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x01,0x7d,0xd4,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00]
+
+v_cmp_class_f32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x7e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x7e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x7e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x00,0x7e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x00,0x7e,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x7e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x7e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x00,0x7e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x00,0x7e,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64_dpp null, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x01,0x7e,0xd4,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00]
+
+v_cmp_eq_f16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x02,0x02,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x02,0x02,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x83,0x02,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_eq_f32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x12,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x12,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x12,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x01,0x12,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x02,0x12,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x12,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x12,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x01,0x12,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x02,0x12,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x83,0x12,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_eq_i16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x32,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x32,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x32,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x00,0x32,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x00,0x32,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x32,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x32,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x00,0x32,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x00,0x32,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x00,0x32,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmp_eq_i32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x42,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x42,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x42,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x00,0x42,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x00,0x42,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x42,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x42,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x00,0x42,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x00,0x42,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x00,0x42,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmp_eq_u16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x3a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x3a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x3a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x00,0x3a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x00,0x3a,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x3a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x3a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x00,0x3a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x00,0x3a,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x00,0x3a,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmp_eq_u32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x4a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x4a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x4a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x00,0x4a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x00,0x4a,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x4a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x4a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x00,0x4a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x00,0x4a,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x00,0x4a,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmp_ge_f16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x06,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x06,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x06,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x01,0x06,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x02,0x06,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x06,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x06,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x01,0x06,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x02,0x06,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x83,0x06,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_ge_f32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x16,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x16,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x16,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x01,0x16,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x02,0x16,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x16,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x16,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x01,0x16,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x02,0x16,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x83,0x16,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_ge_i16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x36,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x36,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x36,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x00,0x36,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x00,0x36,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x36,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x36,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x00,0x36,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x00,0x36,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x00,0x36,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmp_ge_i32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x46,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x46,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x46,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x00,0x46,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x00,0x46,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x46,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x46,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x00,0x46,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x00,0x46,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x00,0x46,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmp_ge_u16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x3e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x3e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x3e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x00,0x3e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x00,0x3e,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x3e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x3e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x00,0x3e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x00,0x3e,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x00,0x3e,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmp_ge_u32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x4e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x4e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x4e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x00,0x4e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x00,0x4e,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x4e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x4e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x00,0x4e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x00,0x4e,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x00,0x4e,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmp_gt_f16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x04,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x04,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x04,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x01,0x04,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x02,0x04,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x04,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x04,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x01,0x04,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x02,0x04,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x83,0x04,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_gt_f32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x14,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x14,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x14,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x01,0x14,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x02,0x14,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x14,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x14,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x01,0x14,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x02,0x14,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x83,0x14,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_gt_i16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x34,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x34,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x34,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x00,0x34,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x00,0x34,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x34,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x34,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x00,0x34,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x00,0x34,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x00,0x34,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmp_gt_i32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x44,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x44,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x44,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x00,0x44,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x00,0x44,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x44,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x44,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x00,0x44,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x00,0x44,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x00,0x44,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmp_gt_u16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x3c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x3c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x3c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x00,0x3c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x00,0x3c,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x3c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x3c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x00,0x3c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x00,0x3c,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x00,0x3c,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmp_gt_u32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x4c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x4c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x4c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x00,0x4c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x00,0x4c,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x4c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x4c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x00,0x4c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x00,0x4c,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x00,0x4c,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmp_le_f16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x03,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x03,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x03,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x01,0x03,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x02,0x03,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x03,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x03,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x01,0x03,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x02,0x03,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x83,0x03,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_le_f32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x13,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x13,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x13,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x01,0x13,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x02,0x13,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x13,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x13,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x01,0x13,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x02,0x13,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x83,0x13,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_le_i16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x33,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x33,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x33,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x00,0x33,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x00,0x33,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x33,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x33,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x00,0x33,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x00,0x33,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x00,0x33,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmp_le_i32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x43,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x43,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x43,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x00,0x43,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x00,0x43,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x43,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x43,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x00,0x43,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x00,0x43,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x00,0x43,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmp_le_u16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x3b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x3b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x3b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x00,0x3b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x00,0x3b,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x3b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x3b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x00,0x3b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x00,0x3b,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x00,0x3b,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmp_le_u32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x4b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x4b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x4b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x00,0x4b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x00,0x4b,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x4b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x4b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x00,0x4b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x00,0x4b,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x00,0x4b,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmp_lg_f16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x05,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x05,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x05,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x01,0x05,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x02,0x05,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x05,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x05,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x01,0x05,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x02,0x05,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x83,0x05,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_lg_f32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x15,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x15,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x15,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x01,0x15,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x02,0x15,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x15,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x15,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x01,0x15,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x02,0x15,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x83,0x15,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_lt_f16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x02,0x01,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x02,0x01,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x83,0x01,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_lt_f32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x11,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x11,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x11,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x01,0x11,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x02,0x11,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x11,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x11,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x01,0x11,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x02,0x11,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x83,0x11,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_lt_i16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x31,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x31,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x31,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x00,0x31,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x00,0x31,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x31,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x31,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x00,0x31,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x00,0x31,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x00,0x31,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmp_lt_i32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x41,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x41,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x41,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x00,0x41,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x00,0x41,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x41,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x41,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x00,0x41,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x00,0x41,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x00,0x41,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmp_lt_u16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x39,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x39,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x39,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x00,0x39,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x00,0x39,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x39,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x39,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x00,0x39,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x00,0x39,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x00,0x39,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmp_lt_u32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x49,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x49,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x49,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x00,0x49,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x00,0x49,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x49,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x49,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x00,0x49,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x00,0x49,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x00,0x49,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmp_ne_i16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x35,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x35,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x35,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x00,0x35,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x00,0x35,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x35,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x35,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x00,0x35,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x00,0x35,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x00,0x35,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmp_ne_i32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x45,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x45,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x45,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x00,0x45,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x00,0x45,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x45,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x45,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x00,0x45,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x00,0x45,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x00,0x45,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmp_ne_u16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x3d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x3d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x3d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x00,0x3d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x00,0x3d,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x3d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x3d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x00,0x3d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x00,0x3d,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x00,0x3d,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmp_ne_u32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x4d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x4d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x4d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp vcc_hi, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x00,0x4d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp ttmp15, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x00,0x4d,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x4d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x4d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x00,0x4d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x00,0x4d,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x00,0x4d,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmp_neq_f16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x0d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x0d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x0d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x01,0x0d,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x02,0x0d,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x0d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x0d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x01,0x0d,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x02,0x0d,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x83,0x0d,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_neq_f32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x1d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x1d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x1d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x01,0x1d,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x02,0x1d,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x1d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x1d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x01,0x1d,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x02,0x1d,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x83,0x1d,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_nge_f16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x09,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x09,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x09,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x01,0x09,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x02,0x09,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x09,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x09,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x01,0x09,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x02,0x09,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x83,0x09,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_nge_f32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x19,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x19,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x19,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x01,0x19,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x02,0x19,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x19,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x19,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x01,0x19,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x02,0x19,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x83,0x19,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_ngt_f16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x0b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x0b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x0b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x01,0x0b,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x02,0x0b,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x0b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x0b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x01,0x0b,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x02,0x0b,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x83,0x0b,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_ngt_f32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x1b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x1b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x1b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x01,0x1b,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x02,0x1b,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x1b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x1b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x01,0x1b,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x02,0x1b,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x83,0x1b,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_nle_f16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x0c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x0c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x0c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x01,0x0c,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x02,0x0c,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x0c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x0c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x01,0x0c,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x02,0x0c,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x83,0x0c,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_nle_f32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x1c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x1c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x1c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x01,0x1c,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x02,0x1c,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x1c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x1c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x01,0x1c,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x02,0x1c,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x83,0x1c,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_nlg_f16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x0a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x0a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x0a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x01,0x0a,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x02,0x0a,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x0a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x0a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x01,0x0a,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x02,0x0a,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x83,0x0a,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_nlg_f32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x1a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x1a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x1a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x01,0x1a,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x02,0x1a,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x1a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x1a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x01,0x1a,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x02,0x1a,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x83,0x1a,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_nlt_f16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x0e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x0e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x0e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x01,0x0e,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x02,0x0e,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x0e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x0e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x01,0x0e,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x02,0x0e,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x83,0x0e,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_nlt_f32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x1e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x1e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x1e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x01,0x1e,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x02,0x1e,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x1e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x1e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x01,0x1e,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x02,0x1e,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x83,0x1e,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_o_f16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x07,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x07,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x07,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x01,0x07,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x02,0x07,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x07,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x07,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x01,0x07,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x02,0x07,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x83,0x07,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_o_f32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x17,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x17,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x17,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x01,0x17,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x02,0x17,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x17,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x17,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x01,0x17,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x02,0x17,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x83,0x17,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_u_f16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x08,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x08,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x08,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x01,0x08,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x02,0x08,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x08,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x08,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x01,0x08,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x02,0x08,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x83,0x08,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_u_f32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x05,0x00,0x18,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x69,0x00,0x18,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6a,0x00,0x18,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: [0x6b,0x01,0x18,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: [0x7b,0x02,0x18,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x0a,0x00,0x18,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x68,0x00,0x18,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: [0x6a,0x01,0x18,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: [0x7a,0x02,0x18,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7c,0x83,0x18,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3cx.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3cx.s
new file mode 100644
index 000000000000..c6ee72a99c02
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3cx.s
@@ -0,0 +1,3413 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
+
+v_cmpx_class_f16_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0xfd,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f16_e64 v255, v2
+// GFX12: encoding: [0x7e,0x00,0xfd,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_class_f16_e64 s1, v2
+// GFX12: encoding: [0x7e,0x00,0xfd,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s105, v255
+// GFX12: encoding: [0x7e,0x00,0xfd,0xd4,0x69,0xfe,0x03,0x00]
+
+v_cmpx_class_f16_e64 vcc_lo, s2
+// GFX12: encoding: [0x7e,0x00,0xfd,0xd4,0x6a,0x04,0x00,0x00]
+
+v_cmpx_class_f16_e64 vcc_hi, s105
+// GFX12: encoding: [0x7e,0x00,0xfd,0xd4,0x6b,0xd2,0x00,0x00]
+
+v_cmpx_class_f16_e64 ttmp15, ttmp15
+// GFX12: encoding: [0x7e,0x00,0xfd,0xd4,0x7b,0xf6,0x00,0x00]
+
+v_cmpx_class_f16_e64 m0, src_scc
+// GFX12: encoding: [0x7e,0x00,0xfd,0xd4,0x7d,0xfa,0x01,0x00]
+
+v_cmpx_class_f16_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0xfd,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_class_f16_e64 exec_hi, null
+// GFX12: encoding: [0x7e,0x00,0xfd,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_class_f16_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0xfd,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_class_f16_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0xfd,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_class_f16_e64 0.5, m0
+// GFX12: encoding: [0x7e,0x00,0xfd,0xd4,0xf0,0xfa,0x00,0x00]
+
+v_cmpx_class_f16_e64 src_scc, vcc_lo
+// GFX12: encoding: [0x7e,0x00,0xfd,0xd4,0xfd,0xd4,0x00,0x00]
+
+v_cmpx_class_f16_e64 -|0xfe0b|, vcc_hi
+// GFX12: encoding: [0x7e,0x01,0xfd,0xd4,0xff,0xd6,0x00,0x20,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_class_f32_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0xfe,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0xfe,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_class_f32_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0xfe,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_class_f32_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0xfe,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_class_f32_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0xfe,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_class_f32_e64 vcc_hi, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xfe,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_class_f32_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0xfe,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_class_f32_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0xfe,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_class_f32_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0xfe,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_class_f32_e64 exec_hi, null
+// GFX12: encoding: [0x7e,0x00,0xfe,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_class_f32_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0xfe,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_class_f32_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0xfe,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_class_f32_e64 0.5, m0
+// GFX12: encoding: [0x7e,0x00,0xfe,0xd4,0xf0,0xfa,0x00,0x00]
+
+v_cmpx_class_f32_e64 src_scc, vcc_lo
+// GFX12: encoding: [0x7e,0x00,0xfe,0xd4,0xfd,0xd4,0x00,0x00]
+
+v_cmpx_class_f32_e64 -|0xaf123456|, vcc_hi
+// GFX12: encoding: [0x7e,0x01,0xfe,0xd4,0xff,0xd6,0x00,0x20,0x56,0x34,0x12,0xaf]
+
+v_cmpx_class_f64_e64 v[1:2], v2
+// GFX12: encoding: [0x7e,0x00,0xff,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 v[1:2], v255
+// GFX12: encoding: [0x7e,0x00,0xff,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_class_f64_e64 v[1:2], s2
+// GFX12: encoding: [0x7e,0x00,0xff,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_class_f64_e64 v[1:2], s105
+// GFX12: encoding: [0x7e,0x00,0xff,0xd4,0x01,0xd3,0x00,0x00]
+
+v_cmpx_class_f64_e64 v[254:255], ttmp15
+// GFX12: encoding: [0x7e,0x00,0xff,0xd4,0xfe,0xf7,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[2:3], vcc_hi
+// GFX12: encoding: [0x7e,0x00,0xff,0xd4,0x02,0xd6,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[104:105], vcc_lo
+// GFX12: encoding: [0x7e,0x00,0xff,0xd4,0x68,0xd4,0x00,0x00]
+
+v_cmpx_class_f64_e64 vcc, m0
+// GFX12: encoding: [0x7e,0x00,0xff,0xd4,0x6a,0xfa,0x00,0x00]
+
+v_cmpx_class_f64_e64 ttmp[14:15], exec_hi
+// GFX12: encoding: [0x7e,0x00,0xff,0xd4,0x7a,0xfe,0x00,0x00]
+
+v_cmpx_class_f64_e64 exec, exec_lo
+// GFX12: encoding: [0x7e,0x00,0xff,0xd4,0x7e,0xfc,0x00,0x00]
+
+v_cmpx_class_f64_e64 null, null
+// GFX12: encoding: [0x7e,0x00,0xff,0xd4,0x7c,0xf8,0x00,0x00]
+
+v_cmpx_class_f64_e64 -1, -1
+// GFX12: encoding: [0x7e,0x00,0xff,0xd4,0xc1,0x82,0x01,0x00]
+
+v_cmpx_class_f64_e64 0.5, 0.5
+// GFX12: encoding: [0x7e,0x00,0xff,0xd4,0xf0,0xe0,0x01,0x00]
+
+v_cmpx_class_f64_e64 -|src_scc|, src_scc
+// GFX12: encoding: [0x7e,0x01,0xff,0xd4,0xfd,0xfa,0x01,0x20]
+
+v_cmpx_class_f64_e64 0xaf123456, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xff,0xd4,0xff,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_f16_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0x82,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f16_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0x82,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_eq_f16_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0x82,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_eq_f16_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0x82,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_eq_f16_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x82,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_eq_f16_e64 vcc_hi, 0xfe0b
+// GFX12: encoding: [0x7e,0x00,0x82,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_eq_f16_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0x82,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_eq_f16_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0x82,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_eq_f16_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0x82,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_eq_f16_e64 |exec_hi|, null
+// GFX12: encoding: [0x7e,0x01,0x82,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_eq_f16_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0x82,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_eq_f16_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0x82,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_eq_f16_e64 0.5, -m0
+// GFX12: encoding: [0x7e,0x00,0x82,0xd4,0xf0,0xfa,0x00,0x40]
+
+v_cmpx_eq_f16_e64 -src_scc, |vcc_lo|
+// GFX12: encoding: [0x7e,0x02,0x82,0xd4,0xfd,0xd4,0x00,0x20]
+
+v_cmpx_eq_f16_e64 -|0xfe0b|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7e,0x83,0x82,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_eq_f32_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0x92,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0x92,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_eq_f32_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0x92,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0x92,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_eq_f32_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x92,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_eq_f32_e64 vcc_hi, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0x92,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_f32_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0x92,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_eq_f32_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0x92,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_eq_f32_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0x92,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_eq_f32_e64 |exec_hi|, null
+// GFX12: encoding: [0x7e,0x01,0x92,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_eq_f32_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0x92,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_eq_f32_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0x92,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_eq_f32_e64 0.5, -m0
+// GFX12: encoding: [0x7e,0x00,0x92,0xd4,0xf0,0xfa,0x00,0x40]
+
+v_cmpx_eq_f32_e64 -src_scc, |vcc_lo|
+// GFX12: encoding: [0x7e,0x02,0x92,0xd4,0xfd,0xd4,0x00,0x20]
+
+v_cmpx_eq_f32_e64 -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7e,0x83,0x92,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_f64_e64 v[1:2], v[2:3]
+// GFX12: encoding: [0x7e,0x00,0xa2,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 v[254:255], v[254:255]
+// GFX12: encoding: [0x7e,0x00,0xa2,0xd4,0xfe,0xfd,0x03,0x00]
+
+v_cmpx_eq_f64_e64 s[2:3], s[4:5]
+// GFX12: encoding: [0x7e,0x00,0xa2,0xd4,0x02,0x08,0x00,0x00]
+
+v_cmpx_eq_f64_e64 s[104:105], s[104:105]
+// GFX12: encoding: [0x7e,0x00,0xa2,0xd4,0x68,0xd0,0x00,0x00]
+
+v_cmpx_eq_f64_e64 vcc, ttmp[14:15]
+// GFX12: encoding: [0x7e,0x00,0xa2,0xd4,0x6a,0xf4,0x00,0x00]
+
+v_cmpx_eq_f64_e64 ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xa2,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_f64_e64 -|exec|, src_scc
+// GFX12: encoding: [0x7e,0x01,0xa2,0xd4,0x7e,0xfa,0x01,0x20]
+
+v_cmpx_eq_f64_e64 null, 0.5
+// GFX12: encoding: [0x7e,0x00,0xa2,0xd4,0x7c,0xe0,0x01,0x00]
+
+v_cmpx_eq_f64_e64 -1, -1
+// GFX12: encoding: [0x7e,0x00,0xa2,0xd4,0xc1,0x82,0x01,0x00]
+
+v_cmpx_eq_f64_e64 0.5, null
+// GFX12: encoding: [0x7e,0x00,0xa2,0xd4,0xf0,0xf8,0x00,0x00]
+
+v_cmpx_eq_f64_e64 -|src_scc|, -|exec|
+// GFX12: encoding: [0x7e,0x03,0xa2,0xd4,0xfd,0xfc,0x00,0x60]
+
+v_cmpx_eq_f64_e64 0xaf123456, -|vcc| clamp
+// GFX12: encoding: [0x7e,0x82,0xa2,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_i16_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0xb2,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i16_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0xb2,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_eq_i16_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0xb2,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_eq_i16_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0xb2,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_eq_i16_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0xb2,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_eq_i16_e64 vcc_hi, 0xfe0b
+// GFX12: encoding: [0x7e,0x00,0xb2,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_eq_i16_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0xb2,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_eq_i16_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0xb2,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_eq_i16_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0xb2,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_eq_i16_e64 exec_hi, null
+// GFX12: encoding: [0x7e,0x00,0xb2,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_eq_i16_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0xb2,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_eq_i16_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0xb2,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_eq_i16_e64 0.5, m0
+// GFX12: encoding: [0x7e,0x00,0xb2,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_eq_i16_e64 src_scc, vcc_lo
+// GFX12: encoding: [0x7e,0x00,0xb2,0xd4,0xfd,0xd4,0x00,0x00]
+
+v_cmpx_eq_i16_e64 0xfe0b, vcc_hi
+// GFX12: encoding: [0x7e,0x00,0xb2,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_eq_i32_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0xc2,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0xc2,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_eq_i32_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0xc2,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0xc2,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_eq_i32_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0xc2,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_eq_i32_e64 vcc_hi, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xc2,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_i32_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0xc2,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_eq_i32_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0xc2,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_eq_i32_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0xc2,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_eq_i32_e64 exec_hi, null
+// GFX12: encoding: [0x7e,0x00,0xc2,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_eq_i32_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0xc2,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_eq_i32_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0xc2,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_eq_i32_e64 0.5, m0
+// GFX12: encoding: [0x7e,0x00,0xc2,0xd4,0xf0,0xfa,0x00,0x00]
+
+v_cmpx_eq_i32_e64 src_scc, vcc_lo
+// GFX12: encoding: [0x7e,0x00,0xc2,0xd4,0xfd,0xd4,0x00,0x00]
+
+v_cmpx_eq_i32_e64 0xaf123456, vcc_hi
+// GFX12: encoding: [0x7e,0x00,0xc2,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_i64_e64 v[1:2], v[2:3]
+// GFX12: encoding: [0x7e,0x00,0xd2,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 v[254:255], v[254:255]
+// GFX12: encoding: [0x7e,0x00,0xd2,0xd4,0xfe,0xfd,0x03,0x00]
+
+v_cmpx_eq_i64_e64 s[2:3], s[4:5]
+// GFX12: encoding: [0x7e,0x00,0xd2,0xd4,0x02,0x08,0x00,0x00]
+
+v_cmpx_eq_i64_e64 s[104:105], s[104:105]
+// GFX12: encoding: [0x7e,0x00,0xd2,0xd4,0x68,0xd0,0x00,0x00]
+
+v_cmpx_eq_i64_e64 vcc, ttmp[14:15]
+// GFX12: encoding: [0x7e,0x00,0xd2,0xd4,0x6a,0xf4,0x00,0x00]
+
+v_cmpx_eq_i64_e64 ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xd2,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_i64_e64 exec, src_scc
+// GFX12: encoding: [0x7e,0x00,0xd2,0xd4,0x7e,0xfa,0x01,0x00]
+
+v_cmpx_eq_i64_e64 null, 0.5
+// GFX12: encoding: [0x7e,0x00,0xd2,0xd4,0x7c,0xe0,0x01,0x00]
+
+v_cmpx_eq_i64_e64 -1, -1
+// GFX12: encoding: [0x7e,0x00,0xd2,0xd4,0xc1,0x82,0x01,0x00]
+
+v_cmpx_eq_i64_e64 0.5, null
+// GFX12: encoding: [0x7e,0x00,0xd2,0xd4,0xf0,0xf8,0x00,0x00]
+
+v_cmpx_eq_i64_e64 src_scc, exec
+// GFX12: encoding: [0x7e,0x00,0xd2,0xd4,0xfd,0xfc,0x00,0x00]
+
+v_cmpx_eq_i64_e64 0xaf123456, vcc
+// GFX12: encoding: [0x7e,0x00,0xd2,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_u16_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0xba,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u16_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0xba,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_eq_u16_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0xba,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_eq_u16_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0xba,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_eq_u16_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0xba,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_eq_u16_e64 vcc_hi, 0xfe0b
+// GFX12: encoding: [0x7e,0x00,0xba,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_eq_u16_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0xba,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_eq_u16_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0xba,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_eq_u16_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0xba,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_eq_u16_e64 exec_hi, null
+// GFX12: encoding: [0x7e,0x00,0xba,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_eq_u16_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0xba,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_eq_u16_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0xba,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_eq_u16_e64 0.5, m0
+// GFX12: encoding: [0x7e,0x00,0xba,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_eq_u16_e64 src_scc, vcc_lo
+// GFX12: encoding: [0x7e,0x00,0xba,0xd4,0xfd,0xd4,0x00,0x00]
+
+v_cmpx_eq_u16_e64 0xfe0b, vcc_hi
+// GFX12: encoding: [0x7e,0x00,0xba,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_eq_u32_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0xca,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0xca,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_eq_u32_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0xca,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0xca,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_eq_u32_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0xca,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_eq_u32_e64 vcc_hi, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xca,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_u32_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0xca,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_eq_u32_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0xca,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_eq_u32_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0xca,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_eq_u32_e64 exec_hi, null
+// GFX12: encoding: [0x7e,0x00,0xca,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_eq_u32_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0xca,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_eq_u32_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0xca,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_eq_u32_e64 0.5, m0
+// GFX12: encoding: [0x7e,0x00,0xca,0xd4,0xf0,0xfa,0x00,0x00]
+
+v_cmpx_eq_u32_e64 src_scc, vcc_lo
+// GFX12: encoding: [0x7e,0x00,0xca,0xd4,0xfd,0xd4,0x00,0x00]
+
+v_cmpx_eq_u32_e64 0xaf123456, vcc_hi
+// GFX12: encoding: [0x7e,0x00,0xca,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_u64_e64 v[1:2], v[2:3]
+// GFX12: encoding: [0x7e,0x00,0xda,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 v[254:255], v[254:255]
+// GFX12: encoding: [0x7e,0x00,0xda,0xd4,0xfe,0xfd,0x03,0x00]
+
+v_cmpx_eq_u64_e64 s[2:3], s[4:5]
+// GFX12: encoding: [0x7e,0x00,0xda,0xd4,0x02,0x08,0x00,0x00]
+
+v_cmpx_eq_u64_e64 s[104:105], s[104:105]
+// GFX12: encoding: [0x7e,0x00,0xda,0xd4,0x68,0xd0,0x00,0x00]
+
+v_cmpx_eq_u64_e64 vcc, ttmp[14:15]
+// GFX12: encoding: [0x7e,0x00,0xda,0xd4,0x6a,0xf4,0x00,0x00]
+
+v_cmpx_eq_u64_e64 ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xda,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_u64_e64 exec, src_scc
+// GFX12: encoding: [0x7e,0x00,0xda,0xd4,0x7e,0xfa,0x01,0x00]
+
+v_cmpx_eq_u64_e64 null, 0.5
+// GFX12: encoding: [0x7e,0x00,0xda,0xd4,0x7c,0xe0,0x01,0x00]
+
+v_cmpx_eq_u64_e64 -1, -1
+// GFX12: encoding: [0x7e,0x00,0xda,0xd4,0xc1,0x82,0x01,0x00]
+
+v_cmpx_eq_u64_e64 0.5, null
+// GFX12: encoding: [0x7e,0x00,0xda,0xd4,0xf0,0xf8,0x00,0x00]
+
+v_cmpx_eq_u64_e64 src_scc, exec
+// GFX12: encoding: [0x7e,0x00,0xda,0xd4,0xfd,0xfc,0x00,0x00]
+
+v_cmpx_eq_u64_e64 0xaf123456, vcc
+// GFX12: encoding: [0x7e,0x00,0xda,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_f16_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0x86,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f16_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0x86,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_ge_f16_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0x86,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_ge_f16_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0x86,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_ge_f16_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x86,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_ge_f16_e64 vcc_hi, 0xfe0b
+// GFX12: encoding: [0x7e,0x00,0x86,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ge_f16_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0x86,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_ge_f16_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0x86,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_ge_f16_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0x86,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_ge_f16_e64 |exec_hi|, null
+// GFX12: encoding: [0x7e,0x01,0x86,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_ge_f16_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0x86,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_ge_f16_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0x86,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_ge_f16_e64 0.5, -m0
+// GFX12: encoding: [0x7e,0x00,0x86,0xd4,0xf0,0xfa,0x00,0x40]
+
+v_cmpx_ge_f16_e64 -src_scc, |vcc_lo|
+// GFX12: encoding: [0x7e,0x02,0x86,0xd4,0xfd,0xd4,0x00,0x20]
+
+v_cmpx_ge_f16_e64 -|0xfe0b|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7e,0x83,0x86,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ge_f32_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0x96,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0x96,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_ge_f32_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0x96,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0x96,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_ge_f32_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x96,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_ge_f32_e64 vcc_hi, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0x96,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_f32_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0x96,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_ge_f32_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0x96,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_ge_f32_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0x96,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_ge_f32_e64 |exec_hi|, null
+// GFX12: encoding: [0x7e,0x01,0x96,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_ge_f32_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0x96,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_ge_f32_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0x96,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_ge_f32_e64 0.5, -m0
+// GFX12: encoding: [0x7e,0x00,0x96,0xd4,0xf0,0xfa,0x00,0x40]
+
+v_cmpx_ge_f32_e64 -src_scc, |vcc_lo|
+// GFX12: encoding: [0x7e,0x02,0x96,0xd4,0xfd,0xd4,0x00,0x20]
+
+v_cmpx_ge_f32_e64 -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7e,0x83,0x96,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_f64_e64 v[1:2], v[2:3]
+// GFX12: encoding: [0x7e,0x00,0xa6,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 v[254:255], v[254:255]
+// GFX12: encoding: [0x7e,0x00,0xa6,0xd4,0xfe,0xfd,0x03,0x00]
+
+v_cmpx_ge_f64_e64 s[2:3], s[4:5]
+// GFX12: encoding: [0x7e,0x00,0xa6,0xd4,0x02,0x08,0x00,0x00]
+
+v_cmpx_ge_f64_e64 s[104:105], s[104:105]
+// GFX12: encoding: [0x7e,0x00,0xa6,0xd4,0x68,0xd0,0x00,0x00]
+
+v_cmpx_ge_f64_e64 vcc, ttmp[14:15]
+// GFX12: encoding: [0x7e,0x00,0xa6,0xd4,0x6a,0xf4,0x00,0x00]
+
+v_cmpx_ge_f64_e64 ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xa6,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_f64_e64 -|exec|, src_scc
+// GFX12: encoding: [0x7e,0x01,0xa6,0xd4,0x7e,0xfa,0x01,0x20]
+
+v_cmpx_ge_f64_e64 null, 0.5
+// GFX12: encoding: [0x7e,0x00,0xa6,0xd4,0x7c,0xe0,0x01,0x00]
+
+v_cmpx_ge_f64_e64 -1, -1
+// GFX12: encoding: [0x7e,0x00,0xa6,0xd4,0xc1,0x82,0x01,0x00]
+
+v_cmpx_ge_f64_e64 0.5, null
+// GFX12: encoding: [0x7e,0x00,0xa6,0xd4,0xf0,0xf8,0x00,0x00]
+
+v_cmpx_ge_f64_e64 -|src_scc|, -|exec|
+// GFX12: encoding: [0x7e,0x03,0xa6,0xd4,0xfd,0xfc,0x00,0x60]
+
+v_cmpx_ge_f64_e64 0xaf123456, -|vcc| clamp
+// GFX12: encoding: [0x7e,0x82,0xa6,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_i16_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0xb6,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i16_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0xb6,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_ge_i16_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0xb6,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_ge_i16_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0xb6,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_ge_i16_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0xb6,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_ge_i16_e64 vcc_hi, 0xfe0b
+// GFX12: encoding: [0x7e,0x00,0xb6,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ge_i16_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0xb6,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_ge_i16_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0xb6,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_ge_i16_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0xb6,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_ge_i16_e64 exec_hi, null
+// GFX12: encoding: [0x7e,0x00,0xb6,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_ge_i16_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0xb6,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_ge_i16_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0xb6,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_ge_i16_e64 0.5, m0
+// GFX12: encoding: [0x7e,0x00,0xb6,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_ge_i16_e64 src_scc, vcc_lo
+// GFX12: encoding: [0x7e,0x00,0xb6,0xd4,0xfd,0xd4,0x00,0x00]
+
+v_cmpx_ge_i16_e64 0xfe0b, vcc_hi
+// GFX12: encoding: [0x7e,0x00,0xb6,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ge_i32_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0xc6,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0xc6,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_ge_i32_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0xc6,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0xc6,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_ge_i32_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0xc6,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_ge_i32_e64 vcc_hi, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xc6,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_i32_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0xc6,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_ge_i32_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0xc6,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_ge_i32_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0xc6,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_ge_i32_e64 exec_hi, null
+// GFX12: encoding: [0x7e,0x00,0xc6,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_ge_i32_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0xc6,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_ge_i32_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0xc6,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_ge_i32_e64 0.5, m0
+// GFX12: encoding: [0x7e,0x00,0xc6,0xd4,0xf0,0xfa,0x00,0x00]
+
+v_cmpx_ge_i32_e64 src_scc, vcc_lo
+// GFX12: encoding: [0x7e,0x00,0xc6,0xd4,0xfd,0xd4,0x00,0x00]
+
+v_cmpx_ge_i32_e64 0xaf123456, vcc_hi
+// GFX12: encoding: [0x7e,0x00,0xc6,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_i64_e64 v[1:2], v[2:3]
+// GFX12: encoding: [0x7e,0x00,0xd6,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 v[254:255], v[254:255]
+// GFX12: encoding: [0x7e,0x00,0xd6,0xd4,0xfe,0xfd,0x03,0x00]
+
+v_cmpx_ge_i64_e64 s[2:3], s[4:5]
+// GFX12: encoding: [0x7e,0x00,0xd6,0xd4,0x02,0x08,0x00,0x00]
+
+v_cmpx_ge_i64_e64 s[104:105], s[104:105]
+// GFX12: encoding: [0x7e,0x00,0xd6,0xd4,0x68,0xd0,0x00,0x00]
+
+v_cmpx_ge_i64_e64 vcc, ttmp[14:15]
+// GFX12: encoding: [0x7e,0x00,0xd6,0xd4,0x6a,0xf4,0x00,0x00]
+
+v_cmpx_ge_i64_e64 ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xd6,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_i64_e64 exec, src_scc
+// GFX12: encoding: [0x7e,0x00,0xd6,0xd4,0x7e,0xfa,0x01,0x00]
+
+v_cmpx_ge_i64_e64 null, 0.5
+// GFX12: encoding: [0x7e,0x00,0xd6,0xd4,0x7c,0xe0,0x01,0x00]
+
+v_cmpx_ge_i64_e64 -1, -1
+// GFX12: encoding: [0x7e,0x00,0xd6,0xd4,0xc1,0x82,0x01,0x00]
+
+v_cmpx_ge_i64_e64 0.5, null
+// GFX12: encoding: [0x7e,0x00,0xd6,0xd4,0xf0,0xf8,0x00,0x00]
+
+v_cmpx_ge_i64_e64 src_scc, exec
+// GFX12: encoding: [0x7e,0x00,0xd6,0xd4,0xfd,0xfc,0x00,0x00]
+
+v_cmpx_ge_i64_e64 0xaf123456, vcc
+// GFX12: encoding: [0x7e,0x00,0xd6,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_u16_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0xbe,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u16_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0xbe,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_ge_u16_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0xbe,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_ge_u16_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0xbe,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_ge_u16_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0xbe,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_ge_u16_e64 vcc_hi, 0xfe0b
+// GFX12: encoding: [0x7e,0x00,0xbe,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ge_u16_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0xbe,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_ge_u16_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0xbe,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_ge_u16_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0xbe,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_ge_u16_e64 exec_hi, null
+// GFX12: encoding: [0x7e,0x00,0xbe,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_ge_u16_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0xbe,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_ge_u16_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0xbe,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_ge_u16_e64 0.5, m0
+// GFX12: encoding: [0x7e,0x00,0xbe,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_ge_u16_e64 src_scc, vcc_lo
+// GFX12: encoding: [0x7e,0x00,0xbe,0xd4,0xfd,0xd4,0x00,0x00]
+
+v_cmpx_ge_u16_e64 0xfe0b, vcc_hi
+// GFX12: encoding: [0x7e,0x00,0xbe,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ge_u32_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0xce,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0xce,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_ge_u32_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0xce,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0xce,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_ge_u32_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0xce,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_ge_u32_e64 vcc_hi, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xce,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_u32_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0xce,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_ge_u32_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0xce,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_ge_u32_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0xce,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_ge_u32_e64 exec_hi, null
+// GFX12: encoding: [0x7e,0x00,0xce,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_ge_u32_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0xce,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_ge_u32_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0xce,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_ge_u32_e64 0.5, m0
+// GFX12: encoding: [0x7e,0x00,0xce,0xd4,0xf0,0xfa,0x00,0x00]
+
+v_cmpx_ge_u32_e64 src_scc, vcc_lo
+// GFX12: encoding: [0x7e,0x00,0xce,0xd4,0xfd,0xd4,0x00,0x00]
+
+v_cmpx_ge_u32_e64 0xaf123456, vcc_hi
+// GFX12: encoding: [0x7e,0x00,0xce,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_u64_e64 v[1:2], v[2:3]
+// GFX12: encoding: [0x7e,0x00,0xde,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 v[254:255], v[254:255]
+// GFX12: encoding: [0x7e,0x00,0xde,0xd4,0xfe,0xfd,0x03,0x00]
+
+v_cmpx_ge_u64_e64 s[2:3], s[4:5]
+// GFX12: encoding: [0x7e,0x00,0xde,0xd4,0x02,0x08,0x00,0x00]
+
+v_cmpx_ge_u64_e64 s[104:105], s[104:105]
+// GFX12: encoding: [0x7e,0x00,0xde,0xd4,0x68,0xd0,0x00,0x00]
+
+v_cmpx_ge_u64_e64 vcc, ttmp[14:15]
+// GFX12: encoding: [0x7e,0x00,0xde,0xd4,0x6a,0xf4,0x00,0x00]
+
+v_cmpx_ge_u64_e64 ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xde,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_u64_e64 exec, src_scc
+// GFX12: encoding: [0x7e,0x00,0xde,0xd4,0x7e,0xfa,0x01,0x00]
+
+v_cmpx_ge_u64_e64 null, 0.5
+// GFX12: encoding: [0x7e,0x00,0xde,0xd4,0x7c,0xe0,0x01,0x00]
+
+v_cmpx_ge_u64_e64 -1, -1
+// GFX12: encoding: [0x7e,0x00,0xde,0xd4,0xc1,0x82,0x01,0x00]
+
+v_cmpx_ge_u64_e64 0.5, null
+// GFX12: encoding: [0x7e,0x00,0xde,0xd4,0xf0,0xf8,0x00,0x00]
+
+v_cmpx_ge_u64_e64 src_scc, exec
+// GFX12: encoding: [0x7e,0x00,0xde,0xd4,0xfd,0xfc,0x00,0x00]
+
+v_cmpx_ge_u64_e64 0xaf123456, vcc
+// GFX12: encoding: [0x7e,0x00,0xde,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_f16_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0x84,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f16_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0x84,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_gt_f16_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0x84,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_gt_f16_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0x84,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_gt_f16_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x84,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_gt_f16_e64 vcc_hi, 0xfe0b
+// GFX12: encoding: [0x7e,0x00,0x84,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_gt_f16_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0x84,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_gt_f16_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0x84,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_gt_f16_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0x84,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_gt_f16_e64 |exec_hi|, null
+// GFX12: encoding: [0x7e,0x01,0x84,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_gt_f16_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0x84,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_gt_f16_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0x84,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_gt_f16_e64 0.5, -m0
+// GFX12: encoding: [0x7e,0x00,0x84,0xd4,0xf0,0xfa,0x00,0x40]
+
+v_cmpx_gt_f16_e64 -src_scc, |vcc_lo|
+// GFX12: encoding: [0x7e,0x02,0x84,0xd4,0xfd,0xd4,0x00,0x20]
+
+v_cmpx_gt_f16_e64 -|0xfe0b|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7e,0x83,0x84,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_gt_f32_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0x94,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0x94,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_gt_f32_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0x94,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0x94,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_gt_f32_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x94,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_gt_f32_e64 vcc_hi, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0x94,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_f32_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0x94,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_gt_f32_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0x94,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_gt_f32_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0x94,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_gt_f32_e64 |exec_hi|, null
+// GFX12: encoding: [0x7e,0x01,0x94,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_gt_f32_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0x94,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_gt_f32_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0x94,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_gt_f32_e64 0.5, -m0
+// GFX12: encoding: [0x7e,0x00,0x94,0xd4,0xf0,0xfa,0x00,0x40]
+
+v_cmpx_gt_f32_e64 -src_scc, |vcc_lo|
+// GFX12: encoding: [0x7e,0x02,0x94,0xd4,0xfd,0xd4,0x00,0x20]
+
+v_cmpx_gt_f32_e64 -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7e,0x83,0x94,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_f64_e64 v[1:2], v[2:3]
+// GFX12: encoding: [0x7e,0x00,0xa4,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 v[254:255], v[254:255]
+// GFX12: encoding: [0x7e,0x00,0xa4,0xd4,0xfe,0xfd,0x03,0x00]
+
+v_cmpx_gt_f64_e64 s[2:3], s[4:5]
+// GFX12: encoding: [0x7e,0x00,0xa4,0xd4,0x02,0x08,0x00,0x00]
+
+v_cmpx_gt_f64_e64 s[104:105], s[104:105]
+// GFX12: encoding: [0x7e,0x00,0xa4,0xd4,0x68,0xd0,0x00,0x00]
+
+v_cmpx_gt_f64_e64 vcc, ttmp[14:15]
+// GFX12: encoding: [0x7e,0x00,0xa4,0xd4,0x6a,0xf4,0x00,0x00]
+
+v_cmpx_gt_f64_e64 ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xa4,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_f64_e64 -|exec|, src_scc
+// GFX12: encoding: [0x7e,0x01,0xa4,0xd4,0x7e,0xfa,0x01,0x20]
+
+v_cmpx_gt_f64_e64 null, 0.5
+// GFX12: encoding: [0x7e,0x00,0xa4,0xd4,0x7c,0xe0,0x01,0x00]
+
+v_cmpx_gt_f64_e64 -1, -1
+// GFX12: encoding: [0x7e,0x00,0xa4,0xd4,0xc1,0x82,0x01,0x00]
+
+v_cmpx_gt_f64_e64 0.5, null
+// GFX12: encoding: [0x7e,0x00,0xa4,0xd4,0xf0,0xf8,0x00,0x00]
+
+v_cmpx_gt_f64_e64 -|src_scc|, -|exec|
+// GFX12: encoding: [0x7e,0x03,0xa4,0xd4,0xfd,0xfc,0x00,0x60]
+
+v_cmpx_gt_f64_e64 0xaf123456, -|vcc| clamp
+// GFX12: encoding: [0x7e,0x82,0xa4,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_i16_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0xb4,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i16_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0xb4,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_gt_i16_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0xb4,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_gt_i16_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0xb4,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_gt_i16_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0xb4,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_gt_i16_e64 vcc_hi, 0xfe0b
+// GFX12: encoding: [0x7e,0x00,0xb4,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_gt_i16_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0xb4,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_gt_i16_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0xb4,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_gt_i16_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0xb4,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_gt_i16_e64 exec_hi, null
+// GFX12: encoding: [0x7e,0x00,0xb4,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_gt_i16_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0xb4,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_gt_i16_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0xb4,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_gt_i16_e64 0.5, m0
+// GFX12: encoding: [0x7e,0x00,0xb4,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_gt_i16_e64 src_scc, vcc_lo
+// GFX12: encoding: [0x7e,0x00,0xb4,0xd4,0xfd,0xd4,0x00,0x00]
+
+v_cmpx_gt_i16_e64 0xfe0b, vcc_hi
+// GFX12: encoding: [0x7e,0x00,0xb4,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_gt_i32_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0xc4,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0xc4,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_gt_i32_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0xc4,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0xc4,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_gt_i32_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0xc4,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_gt_i32_e64 vcc_hi, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xc4,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_i32_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0xc4,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_gt_i32_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0xc4,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_gt_i32_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0xc4,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_gt_i32_e64 exec_hi, null
+// GFX12: encoding: [0x7e,0x00,0xc4,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_gt_i32_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0xc4,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_gt_i32_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0xc4,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_gt_i32_e64 0.5, m0
+// GFX12: encoding: [0x7e,0x00,0xc4,0xd4,0xf0,0xfa,0x00,0x00]
+
+v_cmpx_gt_i32_e64 src_scc, vcc_lo
+// GFX12: encoding: [0x7e,0x00,0xc4,0xd4,0xfd,0xd4,0x00,0x00]
+
+v_cmpx_gt_i32_e64 0xaf123456, vcc_hi
+// GFX12: encoding: [0x7e,0x00,0xc4,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_i64_e64 v[1:2], v[2:3]
+// GFX12: encoding: [0x7e,0x00,0xd4,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 v[254:255], v[254:255]
+// GFX12: encoding: [0x7e,0x00,0xd4,0xd4,0xfe,0xfd,0x03,0x00]
+
+v_cmpx_gt_i64_e64 s[2:3], s[4:5]
+// GFX12: encoding: [0x7e,0x00,0xd4,0xd4,0x02,0x08,0x00,0x00]
+
+v_cmpx_gt_i64_e64 s[104:105], s[104:105]
+// GFX12: encoding: [0x7e,0x00,0xd4,0xd4,0x68,0xd0,0x00,0x00]
+
+v_cmpx_gt_i64_e64 vcc, ttmp[14:15]
+// GFX12: encoding: [0x7e,0x00,0xd4,0xd4,0x6a,0xf4,0x00,0x00]
+
+v_cmpx_gt_i64_e64 ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xd4,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_i64_e64 exec, src_scc
+// GFX12: encoding: [0x7e,0x00,0xd4,0xd4,0x7e,0xfa,0x01,0x00]
+
+v_cmpx_gt_i64_e64 null, 0.5
+// GFX12: encoding: [0x7e,0x00,0xd4,0xd4,0x7c,0xe0,0x01,0x00]
+
+v_cmpx_gt_i64_e64 -1, -1
+// GFX12: encoding: [0x7e,0x00,0xd4,0xd4,0xc1,0x82,0x01,0x00]
+
+v_cmpx_gt_i64_e64 0.5, null
+// GFX12: encoding: [0x7e,0x00,0xd4,0xd4,0xf0,0xf8,0x00,0x00]
+
+v_cmpx_gt_i64_e64 src_scc, exec
+// GFX12: encoding: [0x7e,0x00,0xd4,0xd4,0xfd,0xfc,0x00,0x00]
+
+v_cmpx_gt_i64_e64 0xaf123456, vcc
+// GFX12: encoding: [0x7e,0x00,0xd4,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_u16_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0xbc,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u16_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0xbc,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_gt_u16_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0xbc,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_gt_u16_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0xbc,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_gt_u16_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0xbc,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_gt_u16_e64 vcc_hi, 0xfe0b
+// GFX12: encoding: [0x7e,0x00,0xbc,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_gt_u16_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0xbc,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_gt_u16_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0xbc,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_gt_u16_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0xbc,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_gt_u16_e64 exec_hi, null
+// GFX12: encoding: [0x7e,0x00,0xbc,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_gt_u16_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0xbc,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_gt_u16_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0xbc,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_gt_u16_e64 0.5, m0
+// GFX12: encoding: [0x7e,0x00,0xbc,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_gt_u16_e64 src_scc, vcc_lo
+// GFX12: encoding: [0x7e,0x00,0xbc,0xd4,0xfd,0xd4,0x00,0x00]
+
+v_cmpx_gt_u16_e64 0xfe0b, vcc_hi
+// GFX12: encoding: [0x7e,0x00,0xbc,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_gt_u32_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0xcc,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0xcc,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_gt_u32_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0xcc,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0xcc,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_gt_u32_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0xcc,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_gt_u32_e64 vcc_hi, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xcc,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_u32_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0xcc,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_gt_u32_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0xcc,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_gt_u32_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0xcc,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_gt_u32_e64 exec_hi, null
+// GFX12: encoding: [0x7e,0x00,0xcc,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_gt_u32_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0xcc,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_gt_u32_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0xcc,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_gt_u32_e64 0.5, m0
+// GFX12: encoding: [0x7e,0x00,0xcc,0xd4,0xf0,0xfa,0x00,0x00]
+
+v_cmpx_gt_u32_e64 src_scc, vcc_lo
+// GFX12: encoding: [0x7e,0x00,0xcc,0xd4,0xfd,0xd4,0x00,0x00]
+
+v_cmpx_gt_u32_e64 0xaf123456, vcc_hi
+// GFX12: encoding: [0x7e,0x00,0xcc,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_u64_e64 v[1:2], v[2:3]
+// GFX12: encoding: [0x7e,0x00,0xdc,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 v[254:255], v[254:255]
+// GFX12: encoding: [0x7e,0x00,0xdc,0xd4,0xfe,0xfd,0x03,0x00]
+
+v_cmpx_gt_u64_e64 s[2:3], s[4:5]
+// GFX12: encoding: [0x7e,0x00,0xdc,0xd4,0x02,0x08,0x00,0x00]
+
+v_cmpx_gt_u64_e64 s[104:105], s[104:105]
+// GFX12: encoding: [0x7e,0x00,0xdc,0xd4,0x68,0xd0,0x00,0x00]
+
+v_cmpx_gt_u64_e64 vcc, ttmp[14:15]
+// GFX12: encoding: [0x7e,0x00,0xdc,0xd4,0x6a,0xf4,0x00,0x00]
+
+v_cmpx_gt_u64_e64 ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xdc,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_u64_e64 exec, src_scc
+// GFX12: encoding: [0x7e,0x00,0xdc,0xd4,0x7e,0xfa,0x01,0x00]
+
+v_cmpx_gt_u64_e64 null, 0.5
+// GFX12: encoding: [0x7e,0x00,0xdc,0xd4,0x7c,0xe0,0x01,0x00]
+
+v_cmpx_gt_u64_e64 -1, -1
+// GFX12: encoding: [0x7e,0x00,0xdc,0xd4,0xc1,0x82,0x01,0x00]
+
+v_cmpx_gt_u64_e64 0.5, null
+// GFX12: encoding: [0x7e,0x00,0xdc,0xd4,0xf0,0xf8,0x00,0x00]
+
+v_cmpx_gt_u64_e64 src_scc, exec
+// GFX12: encoding: [0x7e,0x00,0xdc,0xd4,0xfd,0xfc,0x00,0x00]
+
+v_cmpx_gt_u64_e64 0xaf123456, vcc
+// GFX12: encoding: [0x7e,0x00,0xdc,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_f16_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0x83,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f16_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0x83,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_le_f16_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0x83,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_le_f16_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0x83,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_le_f16_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x83,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_le_f16_e64 vcc_hi, 0xfe0b
+// GFX12: encoding: [0x7e,0x00,0x83,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_le_f16_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0x83,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_le_f16_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0x83,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_le_f16_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0x83,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_le_f16_e64 |exec_hi|, null
+// GFX12: encoding: [0x7e,0x01,0x83,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_le_f16_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0x83,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_le_f16_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0x83,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_le_f16_e64 0.5, -m0
+// GFX12: encoding: [0x7e,0x00,0x83,0xd4,0xf0,0xfa,0x00,0x40]
+
+v_cmpx_le_f16_e64 -src_scc, |vcc_lo|
+// GFX12: encoding: [0x7e,0x02,0x83,0xd4,0xfd,0xd4,0x00,0x20]
+
+v_cmpx_le_f16_e64 -|0xfe0b|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7e,0x83,0x83,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_le_f32_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0x93,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0x93,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_le_f32_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0x93,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_le_f32_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0x93,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_le_f32_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x93,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_le_f32_e64 vcc_hi, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0x93,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_f32_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0x93,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_le_f32_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0x93,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_le_f32_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0x93,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_le_f32_e64 |exec_hi|, null
+// GFX12: encoding: [0x7e,0x01,0x93,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_le_f32_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0x93,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_le_f32_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0x93,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_le_f32_e64 0.5, -m0
+// GFX12: encoding: [0x7e,0x00,0x93,0xd4,0xf0,0xfa,0x00,0x40]
+
+v_cmpx_le_f32_e64 -src_scc, |vcc_lo|
+// GFX12: encoding: [0x7e,0x02,0x93,0xd4,0xfd,0xd4,0x00,0x20]
+
+v_cmpx_le_f32_e64 -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7e,0x83,0x93,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_f64_e64 v[1:2], v[2:3]
+// GFX12: encoding: [0x7e,0x00,0xa3,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 v[254:255], v[254:255]
+// GFX12: encoding: [0x7e,0x00,0xa3,0xd4,0xfe,0xfd,0x03,0x00]
+
+v_cmpx_le_f64_e64 s[2:3], s[4:5]
+// GFX12: encoding: [0x7e,0x00,0xa3,0xd4,0x02,0x08,0x00,0x00]
+
+v_cmpx_le_f64_e64 s[104:105], s[104:105]
+// GFX12: encoding: [0x7e,0x00,0xa3,0xd4,0x68,0xd0,0x00,0x00]
+
+v_cmpx_le_f64_e64 vcc, ttmp[14:15]
+// GFX12: encoding: [0x7e,0x00,0xa3,0xd4,0x6a,0xf4,0x00,0x00]
+
+v_cmpx_le_f64_e64 ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xa3,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_f64_e64 -|exec|, src_scc
+// GFX12: encoding: [0x7e,0x01,0xa3,0xd4,0x7e,0xfa,0x01,0x20]
+
+v_cmpx_le_f64_e64 null, 0.5
+// GFX12: encoding: [0x7e,0x00,0xa3,0xd4,0x7c,0xe0,0x01,0x00]
+
+v_cmpx_le_f64_e64 -1, -1
+// GFX12: encoding: [0x7e,0x00,0xa3,0xd4,0xc1,0x82,0x01,0x00]
+
+v_cmpx_le_f64_e64 0.5, null
+// GFX12: encoding: [0x7e,0x00,0xa3,0xd4,0xf0,0xf8,0x00,0x00]
+
+v_cmpx_le_f64_e64 -|src_scc|, -|exec|
+// GFX12: encoding: [0x7e,0x03,0xa3,0xd4,0xfd,0xfc,0x00,0x60]
+
+v_cmpx_le_f64_e64 0xaf123456, -|vcc| clamp
+// GFX12: encoding: [0x7e,0x82,0xa3,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_i16_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0xb3,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i16_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0xb3,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_le_i16_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0xb3,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_le_i16_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0xb3,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_le_i16_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0xb3,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_le_i16_e64 vcc_hi, 0xfe0b
+// GFX12: encoding: [0x7e,0x00,0xb3,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_le_i16_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0xb3,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_le_i16_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0xb3,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_le_i16_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0xb3,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_le_i16_e64 exec_hi, null
+// GFX12: encoding: [0x7e,0x00,0xb3,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_le_i16_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0xb3,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_le_i16_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0xb3,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_le_i16_e64 0.5, m0
+// GFX12: encoding: [0x7e,0x00,0xb3,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_le_i16_e64 src_scc, vcc_lo
+// GFX12: encoding: [0x7e,0x00,0xb3,0xd4,0xfd,0xd4,0x00,0x00]
+
+v_cmpx_le_i16_e64 0xfe0b, vcc_hi
+// GFX12: encoding: [0x7e,0x00,0xb3,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_le_i32_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0xc3,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0xc3,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_le_i32_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0xc3,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_le_i32_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0xc3,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_le_i32_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0xc3,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_le_i32_e64 vcc_hi, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xc3,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_i32_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0xc3,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_le_i32_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0xc3,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_le_i32_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0xc3,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_le_i32_e64 exec_hi, null
+// GFX12: encoding: [0x7e,0x00,0xc3,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_le_i32_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0xc3,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_le_i32_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0xc3,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_le_i32_e64 0.5, m0
+// GFX12: encoding: [0x7e,0x00,0xc3,0xd4,0xf0,0xfa,0x00,0x00]
+
+v_cmpx_le_i32_e64 src_scc, vcc_lo
+// GFX12: encoding: [0x7e,0x00,0xc3,0xd4,0xfd,0xd4,0x00,0x00]
+
+v_cmpx_le_i32_e64 0xaf123456, vcc_hi
+// GFX12: encoding: [0x7e,0x00,0xc3,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_i64_e64 v[1:2], v[2:3]
+// GFX12: encoding: [0x7e,0x00,0xd3,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 v[254:255], v[254:255]
+// GFX12: encoding: [0x7e,0x00,0xd3,0xd4,0xfe,0xfd,0x03,0x00]
+
+v_cmpx_le_i64_e64 s[2:3], s[4:5]
+// GFX12: encoding: [0x7e,0x00,0xd3,0xd4,0x02,0x08,0x00,0x00]
+
+v_cmpx_le_i64_e64 s[104:105], s[104:105]
+// GFX12: encoding: [0x7e,0x00,0xd3,0xd4,0x68,0xd0,0x00,0x00]
+
+v_cmpx_le_i64_e64 vcc, ttmp[14:15]
+// GFX12: encoding: [0x7e,0x00,0xd3,0xd4,0x6a,0xf4,0x00,0x00]
+
+v_cmpx_le_i64_e64 ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xd3,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_i64_e64 exec, src_scc
+// GFX12: encoding: [0x7e,0x00,0xd3,0xd4,0x7e,0xfa,0x01,0x00]
+
+v_cmpx_le_i64_e64 null, 0.5
+// GFX12: encoding: [0x7e,0x00,0xd3,0xd4,0x7c,0xe0,0x01,0x00]
+
+v_cmpx_le_i64_e64 -1, -1
+// GFX12: encoding: [0x7e,0x00,0xd3,0xd4,0xc1,0x82,0x01,0x00]
+
+v_cmpx_le_i64_e64 0.5, null
+// GFX12: encoding: [0x7e,0x00,0xd3,0xd4,0xf0,0xf8,0x00,0x00]
+
+v_cmpx_le_i64_e64 src_scc, exec
+// GFX12: encoding: [0x7e,0x00,0xd3,0xd4,0xfd,0xfc,0x00,0x00]
+
+v_cmpx_le_i64_e64 0xaf123456, vcc
+// GFX12: encoding: [0x7e,0x00,0xd3,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_u16_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0xbb,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u16_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0xbb,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_le_u16_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0xbb,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_le_u16_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0xbb,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_le_u16_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0xbb,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_le_u16_e64 vcc_hi, 0xfe0b
+// GFX12: encoding: [0x7e,0x00,0xbb,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_le_u16_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0xbb,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_le_u16_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0xbb,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_le_u16_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0xbb,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_le_u16_e64 exec_hi, null
+// GFX12: encoding: [0x7e,0x00,0xbb,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_le_u16_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0xbb,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_le_u16_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0xbb,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_le_u16_e64 0.5, m0
+// GFX12: encoding: [0x7e,0x00,0xbb,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_le_u16_e64 src_scc, vcc_lo
+// GFX12: encoding: [0x7e,0x00,0xbb,0xd4,0xfd,0xd4,0x00,0x00]
+
+v_cmpx_le_u16_e64 0xfe0b, vcc_hi
+// GFX12: encoding: [0x7e,0x00,0xbb,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_le_u32_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0xcb,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0xcb,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_le_u32_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0xcb,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_le_u32_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0xcb,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_le_u32_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0xcb,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_le_u32_e64 vcc_hi, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xcb,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_u32_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0xcb,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_le_u32_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0xcb,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_le_u32_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0xcb,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_le_u32_e64 exec_hi, null
+// GFX12: encoding: [0x7e,0x00,0xcb,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_le_u32_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0xcb,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_le_u32_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0xcb,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_le_u32_e64 0.5, m0
+// GFX12: encoding: [0x7e,0x00,0xcb,0xd4,0xf0,0xfa,0x00,0x00]
+
+v_cmpx_le_u32_e64 src_scc, vcc_lo
+// GFX12: encoding: [0x7e,0x00,0xcb,0xd4,0xfd,0xd4,0x00,0x00]
+
+v_cmpx_le_u32_e64 0xaf123456, vcc_hi
+// GFX12: encoding: [0x7e,0x00,0xcb,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_u64_e64 v[1:2], v[2:3]
+// GFX12: encoding: [0x7e,0x00,0xdb,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 v[254:255], v[254:255]
+// GFX12: encoding: [0x7e,0x00,0xdb,0xd4,0xfe,0xfd,0x03,0x00]
+
+v_cmpx_le_u64_e64 s[2:3], s[4:5]
+// GFX12: encoding: [0x7e,0x00,0xdb,0xd4,0x02,0x08,0x00,0x00]
+
+v_cmpx_le_u64_e64 s[104:105], s[104:105]
+// GFX12: encoding: [0x7e,0x00,0xdb,0xd4,0x68,0xd0,0x00,0x00]
+
+v_cmpx_le_u64_e64 vcc, ttmp[14:15]
+// GFX12: encoding: [0x7e,0x00,0xdb,0xd4,0x6a,0xf4,0x00,0x00]
+
+v_cmpx_le_u64_e64 ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xdb,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_u64_e64 exec, src_scc
+// GFX12: encoding: [0x7e,0x00,0xdb,0xd4,0x7e,0xfa,0x01,0x00]
+
+v_cmpx_le_u64_e64 null, 0.5
+// GFX12: encoding: [0x7e,0x00,0xdb,0xd4,0x7c,0xe0,0x01,0x00]
+
+v_cmpx_le_u64_e64 -1, -1
+// GFX12: encoding: [0x7e,0x00,0xdb,0xd4,0xc1,0x82,0x01,0x00]
+
+v_cmpx_le_u64_e64 0.5, null
+// GFX12: encoding: [0x7e,0x00,0xdb,0xd4,0xf0,0xf8,0x00,0x00]
+
+v_cmpx_le_u64_e64 src_scc, exec
+// GFX12: encoding: [0x7e,0x00,0xdb,0xd4,0xfd,0xfc,0x00,0x00]
+
+v_cmpx_le_u64_e64 0xaf123456, vcc
+// GFX12: encoding: [0x7e,0x00,0xdb,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lg_f16_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0x85,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f16_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0x85,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_lg_f16_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0x85,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_lg_f16_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0x85,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_lg_f16_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x85,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_lg_f16_e64 vcc_hi, 0xfe0b
+// GFX12: encoding: [0x7e,0x00,0x85,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_lg_f16_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0x85,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_lg_f16_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0x85,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_lg_f16_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0x85,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_lg_f16_e64 |exec_hi|, null
+// GFX12: encoding: [0x7e,0x01,0x85,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_lg_f16_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0x85,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_lg_f16_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0x85,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_lg_f16_e64 0.5, -m0
+// GFX12: encoding: [0x7e,0x00,0x85,0xd4,0xf0,0xfa,0x00,0x40]
+
+v_cmpx_lg_f16_e64 -src_scc, |vcc_lo|
+// GFX12: encoding: [0x7e,0x02,0x85,0xd4,0xfd,0xd4,0x00,0x20]
+
+v_cmpx_lg_f16_e64 -|0xfe0b|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7e,0x83,0x85,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_lg_f32_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0x95,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0x95,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_lg_f32_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0x95,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0x95,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_lg_f32_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x95,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_lg_f32_e64 vcc_hi, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0x95,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lg_f32_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0x95,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_lg_f32_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0x95,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_lg_f32_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0x95,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_lg_f32_e64 |exec_hi|, null
+// GFX12: encoding: [0x7e,0x01,0x95,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_lg_f32_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0x95,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_lg_f32_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0x95,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_lg_f32_e64 0.5, -m0
+// GFX12: encoding: [0x7e,0x00,0x95,0xd4,0xf0,0xfa,0x00,0x40]
+
+v_cmpx_lg_f32_e64 -src_scc, |vcc_lo|
+// GFX12: encoding: [0x7e,0x02,0x95,0xd4,0xfd,0xd4,0x00,0x20]
+
+v_cmpx_lg_f32_e64 -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7e,0x83,0x95,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lg_f64_e64 v[1:2], v[2:3]
+// GFX12: encoding: [0x7e,0x00,0xa5,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 v[254:255], v[254:255]
+// GFX12: encoding: [0x7e,0x00,0xa5,0xd4,0xfe,0xfd,0x03,0x00]
+
+v_cmpx_lg_f64_e64 s[2:3], s[4:5]
+// GFX12: encoding: [0x7e,0x00,0xa5,0xd4,0x02,0x08,0x00,0x00]
+
+v_cmpx_lg_f64_e64 s[104:105], s[104:105]
+// GFX12: encoding: [0x7e,0x00,0xa5,0xd4,0x68,0xd0,0x00,0x00]
+
+v_cmpx_lg_f64_e64 vcc, ttmp[14:15]
+// GFX12: encoding: [0x7e,0x00,0xa5,0xd4,0x6a,0xf4,0x00,0x00]
+
+v_cmpx_lg_f64_e64 ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xa5,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lg_f64_e64 -|exec|, src_scc
+// GFX12: encoding: [0x7e,0x01,0xa5,0xd4,0x7e,0xfa,0x01,0x20]
+
+v_cmpx_lg_f64_e64 null, 0.5
+// GFX12: encoding: [0x7e,0x00,0xa5,0xd4,0x7c,0xe0,0x01,0x00]
+
+v_cmpx_lg_f64_e64 -1, -1
+// GFX12: encoding: [0x7e,0x00,0xa5,0xd4,0xc1,0x82,0x01,0x00]
+
+v_cmpx_lg_f64_e64 0.5, null
+// GFX12: encoding: [0x7e,0x00,0xa5,0xd4,0xf0,0xf8,0x00,0x00]
+
+v_cmpx_lg_f64_e64 -|src_scc|, -|exec|
+// GFX12: encoding: [0x7e,0x03,0xa5,0xd4,0xfd,0xfc,0x00,0x60]
+
+v_cmpx_lg_f64_e64 0xaf123456, -|vcc| clamp
+// GFX12: encoding: [0x7e,0x82,0xa5,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_f16_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0x81,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f16_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0x81,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_lt_f16_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0x81,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_lt_f16_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0x81,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_lt_f16_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x81,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_lt_f16_e64 vcc_hi, 0xfe0b
+// GFX12: encoding: [0x7e,0x00,0x81,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_lt_f16_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0x81,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_lt_f16_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0x81,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_lt_f16_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0x81,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_lt_f16_e64 |exec_hi|, null
+// GFX12: encoding: [0x7e,0x01,0x81,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_lt_f16_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0x81,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_lt_f16_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0x81,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_lt_f16_e64 0.5, -m0
+// GFX12: encoding: [0x7e,0x00,0x81,0xd4,0xf0,0xfa,0x00,0x40]
+
+v_cmpx_lt_f16_e64 -src_scc, |vcc_lo|
+// GFX12: encoding: [0x7e,0x02,0x81,0xd4,0xfd,0xd4,0x00,0x20]
+
+v_cmpx_lt_f16_e64 -|0xfe0b|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7e,0x83,0x81,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_lt_f32_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0x91,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0x91,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_lt_f32_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0x91,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0x91,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_lt_f32_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x91,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_lt_f32_e64 vcc_hi, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0x91,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_f32_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0x91,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_lt_f32_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0x91,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_lt_f32_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0x91,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_lt_f32_e64 |exec_hi|, null
+// GFX12: encoding: [0x7e,0x01,0x91,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_lt_f32_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0x91,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_lt_f32_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0x91,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_lt_f32_e64 0.5, -m0
+// GFX12: encoding: [0x7e,0x00,0x91,0xd4,0xf0,0xfa,0x00,0x40]
+
+v_cmpx_lt_f32_e64 -src_scc, |vcc_lo|
+// GFX12: encoding: [0x7e,0x02,0x91,0xd4,0xfd,0xd4,0x00,0x20]
+
+v_cmpx_lt_f32_e64 -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7e,0x83,0x91,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_f64_e64 v[1:2], v[2:3]
+// GFX12: encoding: [0x7e,0x00,0xa1,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 v[254:255], v[254:255]
+// GFX12: encoding: [0x7e,0x00,0xa1,0xd4,0xfe,0xfd,0x03,0x00]
+
+v_cmpx_lt_f64_e64 s[2:3], s[4:5]
+// GFX12: encoding: [0x7e,0x00,0xa1,0xd4,0x02,0x08,0x00,0x00]
+
+v_cmpx_lt_f64_e64 s[104:105], s[104:105]
+// GFX12: encoding: [0x7e,0x00,0xa1,0xd4,0x68,0xd0,0x00,0x00]
+
+v_cmpx_lt_f64_e64 vcc, ttmp[14:15]
+// GFX12: encoding: [0x7e,0x00,0xa1,0xd4,0x6a,0xf4,0x00,0x00]
+
+v_cmpx_lt_f64_e64 ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xa1,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_f64_e64 -|exec|, src_scc
+// GFX12: encoding: [0x7e,0x01,0xa1,0xd4,0x7e,0xfa,0x01,0x20]
+
+v_cmpx_lt_f64_e64 null, 0.5
+// GFX12: encoding: [0x7e,0x00,0xa1,0xd4,0x7c,0xe0,0x01,0x00]
+
+v_cmpx_lt_f64_e64 -1, -1
+// GFX12: encoding: [0x7e,0x00,0xa1,0xd4,0xc1,0x82,0x01,0x00]
+
+v_cmpx_lt_f64_e64 0.5, null
+// GFX12: encoding: [0x7e,0x00,0xa1,0xd4,0xf0,0xf8,0x00,0x00]
+
+v_cmpx_lt_f64_e64 -|src_scc|, -|exec|
+// GFX12: encoding: [0x7e,0x03,0xa1,0xd4,0xfd,0xfc,0x00,0x60]
+
+v_cmpx_lt_f64_e64 0xaf123456, -|vcc| clamp
+// GFX12: encoding: [0x7e,0x82,0xa1,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_i16_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0xb1,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i16_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0xb1,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_lt_i16_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0xb1,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_lt_i16_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0xb1,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_lt_i16_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0xb1,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_lt_i16_e64 vcc_hi, 0xfe0b
+// GFX12: encoding: [0x7e,0x00,0xb1,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_lt_i16_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0xb1,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_lt_i16_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0xb1,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_lt_i16_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0xb1,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_lt_i16_e64 exec_hi, null
+// GFX12: encoding: [0x7e,0x00,0xb1,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_lt_i16_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0xb1,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_lt_i16_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0xb1,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_lt_i16_e64 0.5, m0
+// GFX12: encoding: [0x7e,0x00,0xb1,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_lt_i16_e64 src_scc, vcc_lo
+// GFX12: encoding: [0x7e,0x00,0xb1,0xd4,0xfd,0xd4,0x00,0x00]
+
+v_cmpx_lt_i16_e64 0xfe0b, vcc_hi
+// GFX12: encoding: [0x7e,0x00,0xb1,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_lt_i32_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0xc1,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0xc1,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_lt_i32_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0xc1,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0xc1,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_lt_i32_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0xc1,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_lt_i32_e64 vcc_hi, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xc1,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_i32_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0xc1,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_lt_i32_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0xc1,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_lt_i32_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0xc1,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_lt_i32_e64 exec_hi, null
+// GFX12: encoding: [0x7e,0x00,0xc1,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_lt_i32_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0xc1,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_lt_i32_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0xc1,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_lt_i32_e64 0.5, m0
+// GFX12: encoding: [0x7e,0x00,0xc1,0xd4,0xf0,0xfa,0x00,0x00]
+
+v_cmpx_lt_i32_e64 src_scc, vcc_lo
+// GFX12: encoding: [0x7e,0x00,0xc1,0xd4,0xfd,0xd4,0x00,0x00]
+
+v_cmpx_lt_i32_e64 0xaf123456, vcc_hi
+// GFX12: encoding: [0x7e,0x00,0xc1,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_i64_e64 v[1:2], v[2:3]
+// GFX12: encoding: [0x7e,0x00,0xd1,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 v[254:255], v[254:255]
+// GFX12: encoding: [0x7e,0x00,0xd1,0xd4,0xfe,0xfd,0x03,0x00]
+
+v_cmpx_lt_i64_e64 s[2:3], s[4:5]
+// GFX12: encoding: [0x7e,0x00,0xd1,0xd4,0x02,0x08,0x00,0x00]
+
+v_cmpx_lt_i64_e64 s[104:105], s[104:105]
+// GFX12: encoding: [0x7e,0x00,0xd1,0xd4,0x68,0xd0,0x00,0x00]
+
+v_cmpx_lt_i64_e64 vcc, ttmp[14:15]
+// GFX12: encoding: [0x7e,0x00,0xd1,0xd4,0x6a,0xf4,0x00,0x00]
+
+v_cmpx_lt_i64_e64 ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xd1,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_i64_e64 exec, src_scc
+// GFX12: encoding: [0x7e,0x00,0xd1,0xd4,0x7e,0xfa,0x01,0x00]
+
+v_cmpx_lt_i64_e64 null, 0.5
+// GFX12: encoding: [0x7e,0x00,0xd1,0xd4,0x7c,0xe0,0x01,0x00]
+
+v_cmpx_lt_i64_e64 -1, -1
+// GFX12: encoding: [0x7e,0x00,0xd1,0xd4,0xc1,0x82,0x01,0x00]
+
+v_cmpx_lt_i64_e64 0.5, null
+// GFX12: encoding: [0x7e,0x00,0xd1,0xd4,0xf0,0xf8,0x00,0x00]
+
+v_cmpx_lt_i64_e64 src_scc, exec
+// GFX12: encoding: [0x7e,0x00,0xd1,0xd4,0xfd,0xfc,0x00,0x00]
+
+v_cmpx_lt_i64_e64 0xaf123456, vcc
+// GFX12: encoding: [0x7e,0x00,0xd1,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_u16_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0xb9,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u16_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0xb9,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_lt_u16_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0xb9,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_lt_u16_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0xb9,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_lt_u16_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0xb9,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_lt_u16_e64 vcc_hi, 0xfe0b
+// GFX12: encoding: [0x7e,0x00,0xb9,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_lt_u16_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0xb9,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_lt_u16_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0xb9,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_lt_u16_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0xb9,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_lt_u16_e64 exec_hi, null
+// GFX12: encoding: [0x7e,0x00,0xb9,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_lt_u16_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0xb9,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_lt_u16_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0xb9,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_lt_u16_e64 0.5, m0
+// GFX12: encoding: [0x7e,0x00,0xb9,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_lt_u16_e64 src_scc, vcc_lo
+// GFX12: encoding: [0x7e,0x00,0xb9,0xd4,0xfd,0xd4,0x00,0x00]
+
+v_cmpx_lt_u16_e64 0xfe0b, vcc_hi
+// GFX12: encoding: [0x7e,0x00,0xb9,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_lt_u32_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0xc9,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0xc9,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_lt_u32_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0xc9,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0xc9,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_lt_u32_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0xc9,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_lt_u32_e64 vcc_hi, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xc9,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_u32_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0xc9,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_lt_u32_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0xc9,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_lt_u32_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0xc9,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_lt_u32_e64 exec_hi, null
+// GFX12: encoding: [0x7e,0x00,0xc9,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_lt_u32_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0xc9,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_lt_u32_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0xc9,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_lt_u32_e64 0.5, m0
+// GFX12: encoding: [0x7e,0x00,0xc9,0xd4,0xf0,0xfa,0x00,0x00]
+
+v_cmpx_lt_u32_e64 src_scc, vcc_lo
+// GFX12: encoding: [0x7e,0x00,0xc9,0xd4,0xfd,0xd4,0x00,0x00]
+
+v_cmpx_lt_u32_e64 0xaf123456, vcc_hi
+// GFX12: encoding: [0x7e,0x00,0xc9,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_u64_e64 v[1:2], v[2:3]
+// GFX12: encoding: [0x7e,0x00,0xd9,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 v[254:255], v[254:255]
+// GFX12: encoding: [0x7e,0x00,0xd9,0xd4,0xfe,0xfd,0x03,0x00]
+
+v_cmpx_lt_u64_e64 s[2:3], s[4:5]
+// GFX12: encoding: [0x7e,0x00,0xd9,0xd4,0x02,0x08,0x00,0x00]
+
+v_cmpx_lt_u64_e64 s[104:105], s[104:105]
+// GFX12: encoding: [0x7e,0x00,0xd9,0xd4,0x68,0xd0,0x00,0x00]
+
+v_cmpx_lt_u64_e64 vcc, ttmp[14:15]
+// GFX12: encoding: [0x7e,0x00,0xd9,0xd4,0x6a,0xf4,0x00,0x00]
+
+v_cmpx_lt_u64_e64 ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xd9,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_u64_e64 exec, src_scc
+// GFX12: encoding: [0x7e,0x00,0xd9,0xd4,0x7e,0xfa,0x01,0x00]
+
+v_cmpx_lt_u64_e64 null, 0.5
+// GFX12: encoding: [0x7e,0x00,0xd9,0xd4,0x7c,0xe0,0x01,0x00]
+
+v_cmpx_lt_u64_e64 -1, -1
+// GFX12: encoding: [0x7e,0x00,0xd9,0xd4,0xc1,0x82,0x01,0x00]
+
+v_cmpx_lt_u64_e64 0.5, null
+// GFX12: encoding: [0x7e,0x00,0xd9,0xd4,0xf0,0xf8,0x00,0x00]
+
+v_cmpx_lt_u64_e64 src_scc, exec
+// GFX12: encoding: [0x7e,0x00,0xd9,0xd4,0xfd,0xfc,0x00,0x00]
+
+v_cmpx_lt_u64_e64 0xaf123456, vcc
+// GFX12: encoding: [0x7e,0x00,0xd9,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ne_i16_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0xb5,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i16_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0xb5,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_ne_i16_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0xb5,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_ne_i16_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0xb5,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_ne_i16_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0xb5,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_ne_i16_e64 vcc_hi, 0xfe0b
+// GFX12: encoding: [0x7e,0x00,0xb5,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ne_i16_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0xb5,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_ne_i16_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0xb5,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_ne_i16_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0xb5,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_ne_i16_e64 exec_hi, null
+// GFX12: encoding: [0x7e,0x00,0xb5,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_ne_i16_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0xb5,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_ne_i16_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0xb5,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_ne_i16_e64 0.5, m0
+// GFX12: encoding: [0x7e,0x00,0xb5,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_ne_i16_e64 src_scc, vcc_lo
+// GFX12: encoding: [0x7e,0x00,0xb5,0xd4,0xfd,0xd4,0x00,0x00]
+
+v_cmpx_ne_i16_e64 0xfe0b, vcc_hi
+// GFX12: encoding: [0x7e,0x00,0xb5,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ne_i32_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0xc5,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0xc5,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_ne_i32_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0xc5,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0xc5,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_ne_i32_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0xc5,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_ne_i32_e64 vcc_hi, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xc5,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ne_i32_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0xc5,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_ne_i32_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0xc5,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_ne_i32_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0xc5,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_ne_i32_e64 exec_hi, null
+// GFX12: encoding: [0x7e,0x00,0xc5,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_ne_i32_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0xc5,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_ne_i32_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0xc5,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_ne_i32_e64 0.5, m0
+// GFX12: encoding: [0x7e,0x00,0xc5,0xd4,0xf0,0xfa,0x00,0x00]
+
+v_cmpx_ne_i32_e64 src_scc, vcc_lo
+// GFX12: encoding: [0x7e,0x00,0xc5,0xd4,0xfd,0xd4,0x00,0x00]
+
+v_cmpx_ne_i32_e64 0xaf123456, vcc_hi
+// GFX12: encoding: [0x7e,0x00,0xc5,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ne_i64_e64 v[1:2], v[2:3]
+// GFX12: encoding: [0x7e,0x00,0xd5,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 v[254:255], v[254:255]
+// GFX12: encoding: [0x7e,0x00,0xd5,0xd4,0xfe,0xfd,0x03,0x00]
+
+v_cmpx_ne_i64_e64 s[2:3], s[4:5]
+// GFX12: encoding: [0x7e,0x00,0xd5,0xd4,0x02,0x08,0x00,0x00]
+
+v_cmpx_ne_i64_e64 s[104:105], s[104:105]
+// GFX12: encoding: [0x7e,0x00,0xd5,0xd4,0x68,0xd0,0x00,0x00]
+
+v_cmpx_ne_i64_e64 vcc, ttmp[14:15]
+// GFX12: encoding: [0x7e,0x00,0xd5,0xd4,0x6a,0xf4,0x00,0x00]
+
+v_cmpx_ne_i64_e64 ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xd5,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ne_i64_e64 exec, src_scc
+// GFX12: encoding: [0x7e,0x00,0xd5,0xd4,0x7e,0xfa,0x01,0x00]
+
+v_cmpx_ne_i64_e64 null, 0.5
+// GFX12: encoding: [0x7e,0x00,0xd5,0xd4,0x7c,0xe0,0x01,0x00]
+
+v_cmpx_ne_i64_e64 -1, -1
+// GFX12: encoding: [0x7e,0x00,0xd5,0xd4,0xc1,0x82,0x01,0x00]
+
+v_cmpx_ne_i64_e64 0.5, null
+// GFX12: encoding: [0x7e,0x00,0xd5,0xd4,0xf0,0xf8,0x00,0x00]
+
+v_cmpx_ne_i64_e64 src_scc, exec
+// GFX12: encoding: [0x7e,0x00,0xd5,0xd4,0xfd,0xfc,0x00,0x00]
+
+v_cmpx_ne_i64_e64 0xaf123456, vcc
+// GFX12: encoding: [0x7e,0x00,0xd5,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ne_u16_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0xbd,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u16_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0xbd,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_ne_u16_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0xbd,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_ne_u16_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0xbd,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_ne_u16_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0xbd,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_ne_u16_e64 vcc_hi, 0xfe0b
+// GFX12: encoding: [0x7e,0x00,0xbd,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ne_u16_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0xbd,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_ne_u16_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0xbd,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_ne_u16_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0xbd,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_ne_u16_e64 exec_hi, null
+// GFX12: encoding: [0x7e,0x00,0xbd,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_ne_u16_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0xbd,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_ne_u16_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0xbd,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_ne_u16_e64 0.5, m0
+// GFX12: encoding: [0x7e,0x00,0xbd,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_ne_u16_e64 src_scc, vcc_lo
+// GFX12: encoding: [0x7e,0x00,0xbd,0xd4,0xfd,0xd4,0x00,0x00]
+
+v_cmpx_ne_u16_e64 0xfe0b, vcc_hi
+// GFX12: encoding: [0x7e,0x00,0xbd,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ne_u32_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0xcd,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0xcd,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_ne_u32_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0xcd,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0xcd,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_ne_u32_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0xcd,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_ne_u32_e64 vcc_hi, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xcd,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ne_u32_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0xcd,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_ne_u32_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0xcd,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_ne_u32_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0xcd,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_ne_u32_e64 exec_hi, null
+// GFX12: encoding: [0x7e,0x00,0xcd,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_ne_u32_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0xcd,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_ne_u32_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0xcd,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_ne_u32_e64 0.5, m0
+// GFX12: encoding: [0x7e,0x00,0xcd,0xd4,0xf0,0xfa,0x00,0x00]
+
+v_cmpx_ne_u32_e64 src_scc, vcc_lo
+// GFX12: encoding: [0x7e,0x00,0xcd,0xd4,0xfd,0xd4,0x00,0x00]
+
+v_cmpx_ne_u32_e64 0xaf123456, vcc_hi
+// GFX12: encoding: [0x7e,0x00,0xcd,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ne_u64_e64 v[1:2], v[2:3]
+// GFX12: encoding: [0x7e,0x00,0xdd,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 v[254:255], v[254:255]
+// GFX12: encoding: [0x7e,0x00,0xdd,0xd4,0xfe,0xfd,0x03,0x00]
+
+v_cmpx_ne_u64_e64 s[2:3], s[4:5]
+// GFX12: encoding: [0x7e,0x00,0xdd,0xd4,0x02,0x08,0x00,0x00]
+
+v_cmpx_ne_u64_e64 s[104:105], s[104:105]
+// GFX12: encoding: [0x7e,0x00,0xdd,0xd4,0x68,0xd0,0x00,0x00]
+
+v_cmpx_ne_u64_e64 vcc, ttmp[14:15]
+// GFX12: encoding: [0x7e,0x00,0xdd,0xd4,0x6a,0xf4,0x00,0x00]
+
+v_cmpx_ne_u64_e64 ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xdd,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ne_u64_e64 exec, src_scc
+// GFX12: encoding: [0x7e,0x00,0xdd,0xd4,0x7e,0xfa,0x01,0x00]
+
+v_cmpx_ne_u64_e64 null, 0.5
+// GFX12: encoding: [0x7e,0x00,0xdd,0xd4,0x7c,0xe0,0x01,0x00]
+
+v_cmpx_ne_u64_e64 -1, -1
+// GFX12: encoding: [0x7e,0x00,0xdd,0xd4,0xc1,0x82,0x01,0x00]
+
+v_cmpx_ne_u64_e64 0.5, null
+// GFX12: encoding: [0x7e,0x00,0xdd,0xd4,0xf0,0xf8,0x00,0x00]
+
+v_cmpx_ne_u64_e64 src_scc, exec
+// GFX12: encoding: [0x7e,0x00,0xdd,0xd4,0xfd,0xfc,0x00,0x00]
+
+v_cmpx_ne_u64_e64 0xaf123456, vcc
+// GFX12: encoding: [0x7e,0x00,0xdd,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_neq_f16_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0x8d,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f16_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0x8d,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_neq_f16_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0x8d,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_neq_f16_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0x8d,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_neq_f16_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x8d,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_neq_f16_e64 vcc_hi, 0xfe0b
+// GFX12: encoding: [0x7e,0x00,0x8d,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_neq_f16_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0x8d,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_neq_f16_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0x8d,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_neq_f16_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0x8d,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_neq_f16_e64 |exec_hi|, null
+// GFX12: encoding: [0x7e,0x01,0x8d,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_neq_f16_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0x8d,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_neq_f16_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0x8d,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_neq_f16_e64 0.5, -m0
+// GFX12: encoding: [0x7e,0x00,0x8d,0xd4,0xf0,0xfa,0x00,0x40]
+
+v_cmpx_neq_f16_e64 -src_scc, |vcc_lo|
+// GFX12: encoding: [0x7e,0x02,0x8d,0xd4,0xfd,0xd4,0x00,0x20]
+
+v_cmpx_neq_f16_e64 -|0xfe0b|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7e,0x83,0x8d,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_neq_f32_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0x9d,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0x9d,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_neq_f32_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0x9d,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0x9d,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_neq_f32_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x9d,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_neq_f32_e64 vcc_hi, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0x9d,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_neq_f32_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0x9d,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_neq_f32_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0x9d,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_neq_f32_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0x9d,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_neq_f32_e64 |exec_hi|, null
+// GFX12: encoding: [0x7e,0x01,0x9d,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_neq_f32_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0x9d,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_neq_f32_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0x9d,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_neq_f32_e64 0.5, -m0
+// GFX12: encoding: [0x7e,0x00,0x9d,0xd4,0xf0,0xfa,0x00,0x40]
+
+v_cmpx_neq_f32_e64 -src_scc, |vcc_lo|
+// GFX12: encoding: [0x7e,0x02,0x9d,0xd4,0xfd,0xd4,0x00,0x20]
+
+v_cmpx_neq_f32_e64 -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7e,0x83,0x9d,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cmpx_neq_f64_e64 v[1:2], v[2:3]
+// GFX12: encoding: [0x7e,0x00,0xad,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 v[254:255], v[254:255]
+// GFX12: encoding: [0x7e,0x00,0xad,0xd4,0xfe,0xfd,0x03,0x00]
+
+v_cmpx_neq_f64_e64 s[2:3], s[4:5]
+// GFX12: encoding: [0x7e,0x00,0xad,0xd4,0x02,0x08,0x00,0x00]
+
+v_cmpx_neq_f64_e64 s[104:105], s[104:105]
+// GFX12: encoding: [0x7e,0x00,0xad,0xd4,0x68,0xd0,0x00,0x00]
+
+v_cmpx_neq_f64_e64 vcc, ttmp[14:15]
+// GFX12: encoding: [0x7e,0x00,0xad,0xd4,0x6a,0xf4,0x00,0x00]
+
+v_cmpx_neq_f64_e64 ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xad,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_neq_f64_e64 -|exec|, src_scc
+// GFX12: encoding: [0x7e,0x01,0xad,0xd4,0x7e,0xfa,0x01,0x20]
+
+v_cmpx_neq_f64_e64 null, 0.5
+// GFX12: encoding: [0x7e,0x00,0xad,0xd4,0x7c,0xe0,0x01,0x00]
+
+v_cmpx_neq_f64_e64 -1, -1
+// GFX12: encoding: [0x7e,0x00,0xad,0xd4,0xc1,0x82,0x01,0x00]
+
+v_cmpx_neq_f64_e64 0.5, null
+// GFX12: encoding: [0x7e,0x00,0xad,0xd4,0xf0,0xf8,0x00,0x00]
+
+v_cmpx_neq_f64_e64 -|src_scc|, -|exec|
+// GFX12: encoding: [0x7e,0x03,0xad,0xd4,0xfd,0xfc,0x00,0x60]
+
+v_cmpx_neq_f64_e64 0xaf123456, -|vcc| clamp
+// GFX12: encoding: [0x7e,0x82,0xad,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nge_f16_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0x89,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f16_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0x89,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_nge_f16_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0x89,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_nge_f16_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0x89,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_nge_f16_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x89,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_nge_f16_e64 vcc_hi, 0xfe0b
+// GFX12: encoding: [0x7e,0x00,0x89,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_nge_f16_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0x89,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_nge_f16_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0x89,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_nge_f16_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0x89,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_nge_f16_e64 |exec_hi|, null
+// GFX12: encoding: [0x7e,0x01,0x89,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_nge_f16_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0x89,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_nge_f16_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0x89,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_nge_f16_e64 0.5, -m0
+// GFX12: encoding: [0x7e,0x00,0x89,0xd4,0xf0,0xfa,0x00,0x40]
+
+v_cmpx_nge_f16_e64 -src_scc, |vcc_lo|
+// GFX12: encoding: [0x7e,0x02,0x89,0xd4,0xfd,0xd4,0x00,0x20]
+
+v_cmpx_nge_f16_e64 -|0xfe0b|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7e,0x83,0x89,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_nge_f32_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0x99,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0x99,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_nge_f32_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0x99,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0x99,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_nge_f32_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x99,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_nge_f32_e64 vcc_hi, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0x99,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nge_f32_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0x99,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_nge_f32_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0x99,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_nge_f32_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0x99,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_nge_f32_e64 |exec_hi|, null
+// GFX12: encoding: [0x7e,0x01,0x99,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_nge_f32_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0x99,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_nge_f32_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0x99,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_nge_f32_e64 0.5, -m0
+// GFX12: encoding: [0x7e,0x00,0x99,0xd4,0xf0,0xfa,0x00,0x40]
+
+v_cmpx_nge_f32_e64 -src_scc, |vcc_lo|
+// GFX12: encoding: [0x7e,0x02,0x99,0xd4,0xfd,0xd4,0x00,0x20]
+
+v_cmpx_nge_f32_e64 -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7e,0x83,0x99,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nge_f64_e64 v[1:2], v[2:3]
+// GFX12: encoding: [0x7e,0x00,0xa9,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 v[254:255], v[254:255]
+// GFX12: encoding: [0x7e,0x00,0xa9,0xd4,0xfe,0xfd,0x03,0x00]
+
+v_cmpx_nge_f64_e64 s[2:3], s[4:5]
+// GFX12: encoding: [0x7e,0x00,0xa9,0xd4,0x02,0x08,0x00,0x00]
+
+v_cmpx_nge_f64_e64 s[104:105], s[104:105]
+// GFX12: encoding: [0x7e,0x00,0xa9,0xd4,0x68,0xd0,0x00,0x00]
+
+v_cmpx_nge_f64_e64 vcc, ttmp[14:15]
+// GFX12: encoding: [0x7e,0x00,0xa9,0xd4,0x6a,0xf4,0x00,0x00]
+
+v_cmpx_nge_f64_e64 ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xa9,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nge_f64_e64 -|exec|, src_scc
+// GFX12: encoding: [0x7e,0x01,0xa9,0xd4,0x7e,0xfa,0x01,0x20]
+
+v_cmpx_nge_f64_e64 null, 0.5
+// GFX12: encoding: [0x7e,0x00,0xa9,0xd4,0x7c,0xe0,0x01,0x00]
+
+v_cmpx_nge_f64_e64 -1, -1
+// GFX12: encoding: [0x7e,0x00,0xa9,0xd4,0xc1,0x82,0x01,0x00]
+
+v_cmpx_nge_f64_e64 0.5, null
+// GFX12: encoding: [0x7e,0x00,0xa9,0xd4,0xf0,0xf8,0x00,0x00]
+
+v_cmpx_nge_f64_e64 -|src_scc|, -|exec|
+// GFX12: encoding: [0x7e,0x03,0xa9,0xd4,0xfd,0xfc,0x00,0x60]
+
+v_cmpx_nge_f64_e64 0xaf123456, -|vcc| clamp
+// GFX12: encoding: [0x7e,0x82,0xa9,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ngt_f16_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0x8b,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0x8b,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_ngt_f16_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0x8b,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0x8b,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x8b,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 vcc_hi, 0xfe0b
+// GFX12: encoding: [0x7e,0x00,0x8b,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0x8b,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_ngt_f16_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0x8b,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_ngt_f16_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0x8b,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_ngt_f16_e64 |exec_hi|, null
+// GFX12: encoding: [0x7e,0x01,0x8b,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0x8b,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0x8b,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 0.5, -m0
+// GFX12: encoding: [0x7e,0x00,0x8b,0xd4,0xf0,0xfa,0x00,0x40]
+
+v_cmpx_ngt_f16_e64 -src_scc, |vcc_lo|
+// GFX12: encoding: [0x7e,0x02,0x8b,0xd4,0xfd,0xd4,0x00,0x20]
+
+v_cmpx_ngt_f16_e64 -|0xfe0b|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7e,0x83,0x8b,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0x9b,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0x9b,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_ngt_f32_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0x9b,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0x9b,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x9b,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 vcc_hi, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0x9b,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ngt_f32_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0x9b,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_ngt_f32_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0x9b,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_ngt_f32_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0x9b,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_ngt_f32_e64 |exec_hi|, null
+// GFX12: encoding: [0x7e,0x01,0x9b,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0x9b,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0x9b,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 0.5, -m0
+// GFX12: encoding: [0x7e,0x00,0x9b,0xd4,0xf0,0xfa,0x00,0x40]
+
+v_cmpx_ngt_f32_e64 -src_scc, |vcc_lo|
+// GFX12: encoding: [0x7e,0x02,0x9b,0xd4,0xfd,0xd4,0x00,0x20]
+
+v_cmpx_ngt_f32_e64 -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7e,0x83,0x9b,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ngt_f64_e64 v[1:2], v[2:3]
+// GFX12: encoding: [0x7e,0x00,0xab,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 v[254:255], v[254:255]
+// GFX12: encoding: [0x7e,0x00,0xab,0xd4,0xfe,0xfd,0x03,0x00]
+
+v_cmpx_ngt_f64_e64 s[2:3], s[4:5]
+// GFX12: encoding: [0x7e,0x00,0xab,0xd4,0x02,0x08,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 s[104:105], s[104:105]
+// GFX12: encoding: [0x7e,0x00,0xab,0xd4,0x68,0xd0,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 vcc, ttmp[14:15]
+// GFX12: encoding: [0x7e,0x00,0xab,0xd4,0x6a,0xf4,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xab,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ngt_f64_e64 -|exec|, src_scc
+// GFX12: encoding: [0x7e,0x01,0xab,0xd4,0x7e,0xfa,0x01,0x20]
+
+v_cmpx_ngt_f64_e64 null, 0.5
+// GFX12: encoding: [0x7e,0x00,0xab,0xd4,0x7c,0xe0,0x01,0x00]
+
+v_cmpx_ngt_f64_e64 -1, -1
+// GFX12: encoding: [0x7e,0x00,0xab,0xd4,0xc1,0x82,0x01,0x00]
+
+v_cmpx_ngt_f64_e64 0.5, null
+// GFX12: encoding: [0x7e,0x00,0xab,0xd4,0xf0,0xf8,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 -|src_scc|, -|exec|
+// GFX12: encoding: [0x7e,0x03,0xab,0xd4,0xfd,0xfc,0x00,0x60]
+
+v_cmpx_ngt_f64_e64 0xaf123456, -|vcc| clamp
+// GFX12: encoding: [0x7e,0x82,0xab,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nle_f16_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0x8c,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f16_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0x8c,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_nle_f16_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0x8c,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_nle_f16_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0x8c,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_nle_f16_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x8c,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_nle_f16_e64 vcc_hi, 0xfe0b
+// GFX12: encoding: [0x7e,0x00,0x8c,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_nle_f16_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0x8c,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_nle_f16_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0x8c,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_nle_f16_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0x8c,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_nle_f16_e64 |exec_hi|, null
+// GFX12: encoding: [0x7e,0x01,0x8c,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_nle_f16_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0x8c,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_nle_f16_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0x8c,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_nle_f16_e64 0.5, -m0
+// GFX12: encoding: [0x7e,0x00,0x8c,0xd4,0xf0,0xfa,0x00,0x40]
+
+v_cmpx_nle_f16_e64 -src_scc, |vcc_lo|
+// GFX12: encoding: [0x7e,0x02,0x8c,0xd4,0xfd,0xd4,0x00,0x20]
+
+v_cmpx_nle_f16_e64 -|0xfe0b|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7e,0x83,0x8c,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_nle_f32_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0x9c,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0x9c,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_nle_f32_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0x9c,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0x9c,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_nle_f32_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x9c,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_nle_f32_e64 vcc_hi, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0x9c,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nle_f32_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0x9c,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_nle_f32_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0x9c,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_nle_f32_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0x9c,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_nle_f32_e64 |exec_hi|, null
+// GFX12: encoding: [0x7e,0x01,0x9c,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_nle_f32_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0x9c,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_nle_f32_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0x9c,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_nle_f32_e64 0.5, -m0
+// GFX12: encoding: [0x7e,0x00,0x9c,0xd4,0xf0,0xfa,0x00,0x40]
+
+v_cmpx_nle_f32_e64 -src_scc, |vcc_lo|
+// GFX12: encoding: [0x7e,0x02,0x9c,0xd4,0xfd,0xd4,0x00,0x20]
+
+v_cmpx_nle_f32_e64 -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7e,0x83,0x9c,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nle_f64_e64 v[1:2], v[2:3]
+// GFX12: encoding: [0x7e,0x00,0xac,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 v[254:255], v[254:255]
+// GFX12: encoding: [0x7e,0x00,0xac,0xd4,0xfe,0xfd,0x03,0x00]
+
+v_cmpx_nle_f64_e64 s[2:3], s[4:5]
+// GFX12: encoding: [0x7e,0x00,0xac,0xd4,0x02,0x08,0x00,0x00]
+
+v_cmpx_nle_f64_e64 s[104:105], s[104:105]
+// GFX12: encoding: [0x7e,0x00,0xac,0xd4,0x68,0xd0,0x00,0x00]
+
+v_cmpx_nle_f64_e64 vcc, ttmp[14:15]
+// GFX12: encoding: [0x7e,0x00,0xac,0xd4,0x6a,0xf4,0x00,0x00]
+
+v_cmpx_nle_f64_e64 ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xac,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nle_f64_e64 -|exec|, src_scc
+// GFX12: encoding: [0x7e,0x01,0xac,0xd4,0x7e,0xfa,0x01,0x20]
+
+v_cmpx_nle_f64_e64 null, 0.5
+// GFX12: encoding: [0x7e,0x00,0xac,0xd4,0x7c,0xe0,0x01,0x00]
+
+v_cmpx_nle_f64_e64 -1, -1
+// GFX12: encoding: [0x7e,0x00,0xac,0xd4,0xc1,0x82,0x01,0x00]
+
+v_cmpx_nle_f64_e64 0.5, null
+// GFX12: encoding: [0x7e,0x00,0xac,0xd4,0xf0,0xf8,0x00,0x00]
+
+v_cmpx_nle_f64_e64 -|src_scc|, -|exec|
+// GFX12: encoding: [0x7e,0x03,0xac,0xd4,0xfd,0xfc,0x00,0x60]
+
+v_cmpx_nle_f64_e64 0xaf123456, -|vcc| clamp
+// GFX12: encoding: [0x7e,0x82,0xac,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nlg_f16_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0x8a,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0x8a,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_nlg_f16_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0x8a,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0x8a,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x8a,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 vcc_hi, 0xfe0b
+// GFX12: encoding: [0x7e,0x00,0x8a,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0x8a,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_nlg_f16_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0x8a,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_nlg_f16_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0x8a,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_nlg_f16_e64 |exec_hi|, null
+// GFX12: encoding: [0x7e,0x01,0x8a,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0x8a,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0x8a,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 0.5, -m0
+// GFX12: encoding: [0x7e,0x00,0x8a,0xd4,0xf0,0xfa,0x00,0x40]
+
+v_cmpx_nlg_f16_e64 -src_scc, |vcc_lo|
+// GFX12: encoding: [0x7e,0x02,0x8a,0xd4,0xfd,0xd4,0x00,0x20]
+
+v_cmpx_nlg_f16_e64 -|0xfe0b|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7e,0x83,0x8a,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0x9a,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0x9a,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_nlg_f32_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0x9a,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0x9a,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x9a,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 vcc_hi, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0x9a,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nlg_f32_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0x9a,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_nlg_f32_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0x9a,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_nlg_f32_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0x9a,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_nlg_f32_e64 |exec_hi|, null
+// GFX12: encoding: [0x7e,0x01,0x9a,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0x9a,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0x9a,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 0.5, -m0
+// GFX12: encoding: [0x7e,0x00,0x9a,0xd4,0xf0,0xfa,0x00,0x40]
+
+v_cmpx_nlg_f32_e64 -src_scc, |vcc_lo|
+// GFX12: encoding: [0x7e,0x02,0x9a,0xd4,0xfd,0xd4,0x00,0x20]
+
+v_cmpx_nlg_f32_e64 -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7e,0x83,0x9a,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nlg_f64_e64 v[1:2], v[2:3]
+// GFX12: encoding: [0x7e,0x00,0xaa,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 v[254:255], v[254:255]
+// GFX12: encoding: [0x7e,0x00,0xaa,0xd4,0xfe,0xfd,0x03,0x00]
+
+v_cmpx_nlg_f64_e64 s[2:3], s[4:5]
+// GFX12: encoding: [0x7e,0x00,0xaa,0xd4,0x02,0x08,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 s[104:105], s[104:105]
+// GFX12: encoding: [0x7e,0x00,0xaa,0xd4,0x68,0xd0,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 vcc, ttmp[14:15]
+// GFX12: encoding: [0x7e,0x00,0xaa,0xd4,0x6a,0xf4,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xaa,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nlg_f64_e64 -|exec|, src_scc
+// GFX12: encoding: [0x7e,0x01,0xaa,0xd4,0x7e,0xfa,0x01,0x20]
+
+v_cmpx_nlg_f64_e64 null, 0.5
+// GFX12: encoding: [0x7e,0x00,0xaa,0xd4,0x7c,0xe0,0x01,0x00]
+
+v_cmpx_nlg_f64_e64 -1, -1
+// GFX12: encoding: [0x7e,0x00,0xaa,0xd4,0xc1,0x82,0x01,0x00]
+
+v_cmpx_nlg_f64_e64 0.5, null
+// GFX12: encoding: [0x7e,0x00,0xaa,0xd4,0xf0,0xf8,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 -|src_scc|, -|exec|
+// GFX12: encoding: [0x7e,0x03,0xaa,0xd4,0xfd,0xfc,0x00,0x60]
+
+v_cmpx_nlg_f64_e64 0xaf123456, -|vcc| clamp
+// GFX12: encoding: [0x7e,0x82,0xaa,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nlt_f16_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0x8e,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0x8e,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_nlt_f16_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0x8e,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0x8e,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x8e,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 vcc_hi, 0xfe0b
+// GFX12: encoding: [0x7e,0x00,0x8e,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0x8e,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_nlt_f16_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0x8e,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_nlt_f16_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0x8e,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_nlt_f16_e64 |exec_hi|, null
+// GFX12: encoding: [0x7e,0x01,0x8e,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0x8e,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0x8e,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 0.5, -m0
+// GFX12: encoding: [0x7e,0x00,0x8e,0xd4,0xf0,0xfa,0x00,0x40]
+
+v_cmpx_nlt_f16_e64 -src_scc, |vcc_lo|
+// GFX12: encoding: [0x7e,0x02,0x8e,0xd4,0xfd,0xd4,0x00,0x20]
+
+v_cmpx_nlt_f16_e64 -|0xfe0b|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7e,0x83,0x8e,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0x9e,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0x9e,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_nlt_f32_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0x9e,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0x9e,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x9e,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 vcc_hi, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0x9e,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nlt_f32_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0x9e,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_nlt_f32_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0x9e,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_nlt_f32_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0x9e,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_nlt_f32_e64 |exec_hi|, null
+// GFX12: encoding: [0x7e,0x01,0x9e,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0x9e,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0x9e,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 0.5, -m0
+// GFX12: encoding: [0x7e,0x00,0x9e,0xd4,0xf0,0xfa,0x00,0x40]
+
+v_cmpx_nlt_f32_e64 -src_scc, |vcc_lo|
+// GFX12: encoding: [0x7e,0x02,0x9e,0xd4,0xfd,0xd4,0x00,0x20]
+
+v_cmpx_nlt_f32_e64 -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7e,0x83,0x9e,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nlt_f64_e64 v[1:2], v[2:3]
+// GFX12: encoding: [0x7e,0x00,0xae,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 v[254:255], v[254:255]
+// GFX12: encoding: [0x7e,0x00,0xae,0xd4,0xfe,0xfd,0x03,0x00]
+
+v_cmpx_nlt_f64_e64 s[2:3], s[4:5]
+// GFX12: encoding: [0x7e,0x00,0xae,0xd4,0x02,0x08,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 s[104:105], s[104:105]
+// GFX12: encoding: [0x7e,0x00,0xae,0xd4,0x68,0xd0,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 vcc, ttmp[14:15]
+// GFX12: encoding: [0x7e,0x00,0xae,0xd4,0x6a,0xf4,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xae,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nlt_f64_e64 -|exec|, src_scc
+// GFX12: encoding: [0x7e,0x01,0xae,0xd4,0x7e,0xfa,0x01,0x20]
+
+v_cmpx_nlt_f64_e64 null, 0.5
+// GFX12: encoding: [0x7e,0x00,0xae,0xd4,0x7c,0xe0,0x01,0x00]
+
+v_cmpx_nlt_f64_e64 -1, -1
+// GFX12: encoding: [0x7e,0x00,0xae,0xd4,0xc1,0x82,0x01,0x00]
+
+v_cmpx_nlt_f64_e64 0.5, null
+// GFX12: encoding: [0x7e,0x00,0xae,0xd4,0xf0,0xf8,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 -|src_scc|, -|exec|
+// GFX12: encoding: [0x7e,0x03,0xae,0xd4,0xfd,0xfc,0x00,0x60]
+
+v_cmpx_nlt_f64_e64 0xaf123456, -|vcc| clamp
+// GFX12: encoding: [0x7e,0x82,0xae,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+
+v_cmpx_o_f16_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0x87,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f16_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0x87,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_o_f16_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0x87,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_o_f16_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0x87,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_o_f16_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x87,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_o_f16_e64 vcc_hi, 0xfe0b
+// GFX12: encoding: [0x7e,0x00,0x87,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_o_f16_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0x87,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_o_f16_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0x87,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_o_f16_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0x87,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_o_f16_e64 |exec_hi|, null
+// GFX12: encoding: [0x7e,0x01,0x87,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_o_f16_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0x87,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_o_f16_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0x87,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_o_f16_e64 0.5, -m0
+// GFX12: encoding: [0x7e,0x00,0x87,0xd4,0xf0,0xfa,0x00,0x40]
+
+v_cmpx_o_f16_e64 -src_scc, |vcc_lo|
+// GFX12: encoding: [0x7e,0x02,0x87,0xd4,0xfd,0xd4,0x00,0x20]
+
+v_cmpx_o_f16_e64 -|0xfe0b|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7e,0x83,0x87,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_o_f32_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0x97,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0x97,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_o_f32_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0x97,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_o_f32_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0x97,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_o_f32_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x97,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_o_f32_e64 vcc_hi, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0x97,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_o_f32_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0x97,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_o_f32_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0x97,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_o_f32_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0x97,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_o_f32_e64 |exec_hi|, null
+// GFX12: encoding: [0x7e,0x01,0x97,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_o_f32_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0x97,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_o_f32_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0x97,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_o_f32_e64 0.5, -m0
+// GFX12: encoding: [0x7e,0x00,0x97,0xd4,0xf0,0xfa,0x00,0x40]
+
+v_cmpx_o_f32_e64 -src_scc, |vcc_lo|
+// GFX12: encoding: [0x7e,0x02,0x97,0xd4,0xfd,0xd4,0x00,0x20]
+
+v_cmpx_o_f32_e64 -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7e,0x83,0x97,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cmpx_o_f64_e64 v[1:2], v[2:3]
+// GFX12: encoding: [0x7e,0x00,0xa7,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 v[254:255], v[254:255]
+// GFX12: encoding: [0x7e,0x00,0xa7,0xd4,0xfe,0xfd,0x03,0x00]
+
+v_cmpx_o_f64_e64 s[2:3], s[4:5]
+// GFX12: encoding: [0x7e,0x00,0xa7,0xd4,0x02,0x08,0x00,0x00]
+
+v_cmpx_o_f64_e64 s[104:105], s[104:105]
+// GFX12: encoding: [0x7e,0x00,0xa7,0xd4,0x68,0xd0,0x00,0x00]
+
+v_cmpx_o_f64_e64 vcc, ttmp[14:15]
+// GFX12: encoding: [0x7e,0x00,0xa7,0xd4,0x6a,0xf4,0x00,0x00]
+
+v_cmpx_o_f64_e64 ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xa7,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_o_f64_e64 -|exec|, src_scc
+// GFX12: encoding: [0x7e,0x01,0xa7,0xd4,0x7e,0xfa,0x01,0x20]
+
+v_cmpx_o_f64_e64 null, 0.5
+// GFX12: encoding: [0x7e,0x00,0xa7,0xd4,0x7c,0xe0,0x01,0x00]
+
+v_cmpx_o_f64_e64 -1, -1
+// GFX12: encoding: [0x7e,0x00,0xa7,0xd4,0xc1,0x82,0x01,0x00]
+
+v_cmpx_o_f64_e64 0.5, null
+// GFX12: encoding: [0x7e,0x00,0xa7,0xd4,0xf0,0xf8,0x00,0x00]
+
+v_cmpx_o_f64_e64 -|src_scc|, -|exec|
+// GFX12: encoding: [0x7e,0x03,0xa7,0xd4,0xfd,0xfc,0x00,0x60]
+
+v_cmpx_o_f64_e64 0xaf123456, -|vcc| clamp
+// GFX12: encoding: [0x7e,0x82,0xa7,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+
+v_cmpx_u_f16_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0x88,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f16_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0x88,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_u_f16_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0x88,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_u_f16_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0x88,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_u_f16_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x88,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_u_f16_e64 vcc_hi, 0xfe0b
+// GFX12: encoding: [0x7e,0x00,0x88,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_u_f16_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0x88,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_u_f16_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0x88,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_u_f16_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0x88,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_u_f16_e64 |exec_hi|, null
+// GFX12: encoding: [0x7e,0x01,0x88,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_u_f16_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0x88,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_u_f16_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0x88,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_u_f16_e64 0.5, -m0
+// GFX12: encoding: [0x7e,0x00,0x88,0xd4,0xf0,0xfa,0x00,0x40]
+
+v_cmpx_u_f16_e64 -src_scc, |vcc_lo|
+// GFX12: encoding: [0x7e,0x02,0x88,0xd4,0xfd,0xd4,0x00,0x20]
+
+v_cmpx_u_f16_e64 -|0xfe0b|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7e,0x83,0x88,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_u_f32_e64 v1, v2
+// GFX12: encoding: [0x7e,0x00,0x98,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 v255, v255
+// GFX12: encoding: [0x7e,0x00,0x98,0xd4,0xff,0xff,0x03,0x00]
+
+v_cmpx_u_f32_e64 s1, s2
+// GFX12: encoding: [0x7e,0x00,0x98,0xd4,0x01,0x04,0x00,0x00]
+
+v_cmpx_u_f32_e64 s105, s105
+// GFX12: encoding: [0x7e,0x00,0x98,0xd4,0x69,0xd2,0x00,0x00]
+
+v_cmpx_u_f32_e64 vcc_lo, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x98,0xd4,0x6a,0xf6,0x00,0x00]
+
+v_cmpx_u_f32_e64 vcc_hi, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0x98,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_u_f32_e64 ttmp15, src_scc
+// GFX12: encoding: [0x7e,0x00,0x98,0xd4,0x7b,0xfa,0x01,0x00]
+
+v_cmpx_u_f32_e64 m0, 0.5
+// GFX12: encoding: [0x7e,0x00,0x98,0xd4,0x7d,0xe0,0x01,0x00]
+
+v_cmpx_u_f32_e64 exec_lo, -1
+// GFX12: encoding: [0x7e,0x00,0x98,0xd4,0x7e,0x82,0x01,0x00]
+
+v_cmpx_u_f32_e64 |exec_hi|, null
+// GFX12: encoding: [0x7e,0x01,0x98,0xd4,0x7f,0xf8,0x00,0x00]
+
+v_cmpx_u_f32_e64 null, exec_lo
+// GFX12: encoding: [0x7e,0x00,0x98,0xd4,0x7c,0xfc,0x00,0x00]
+
+v_cmpx_u_f32_e64 -1, exec_hi
+// GFX12: encoding: [0x7e,0x00,0x98,0xd4,0xc1,0xfe,0x00,0x00]
+
+v_cmpx_u_f32_e64 0.5, -m0
+// GFX12: encoding: [0x7e,0x00,0x98,0xd4,0xf0,0xfa,0x00,0x40]
+
+v_cmpx_u_f32_e64 -src_scc, |vcc_lo|
+// GFX12: encoding: [0x7e,0x02,0x98,0xd4,0xfd,0xd4,0x00,0x20]
+
+v_cmpx_u_f32_e64 -|0xaf123456|, -|vcc_hi| clamp
+// GFX12: encoding: [0x7e,0x83,0x98,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+
+v_cmpx_u_f64_e64 v[1:2], v[2:3]
+// GFX12: encoding: [0x7e,0x00,0xa8,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 v[254:255], v[254:255]
+// GFX12: encoding: [0x7e,0x00,0xa8,0xd4,0xfe,0xfd,0x03,0x00]
+
+v_cmpx_u_f64_e64 s[2:3], s[4:5]
+// GFX12: encoding: [0x7e,0x00,0xa8,0xd4,0x02,0x08,0x00,0x00]
+
+v_cmpx_u_f64_e64 s[104:105], s[104:105]
+// GFX12: encoding: [0x7e,0x00,0xa8,0xd4,0x68,0xd0,0x00,0x00]
+
+v_cmpx_u_f64_e64 vcc, ttmp[14:15]
+// GFX12: encoding: [0x7e,0x00,0xa8,0xd4,0x6a,0xf4,0x00,0x00]
+
+v_cmpx_u_f64_e64 ttmp[14:15], 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0xa8,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+
+v_cmpx_u_f64_e64 -|exec|, src_scc
+// GFX12: encoding: [0x7e,0x01,0xa8,0xd4,0x7e,0xfa,0x01,0x20]
+
+v_cmpx_u_f64_e64 null, 0.5
+// GFX12: encoding: [0x7e,0x00,0xa8,0xd4,0x7c,0xe0,0x01,0x00]
+
+v_cmpx_u_f64_e64 -1, -1
+// GFX12: encoding: [0x7e,0x00,0xa8,0xd4,0xc1,0x82,0x01,0x00]
+
+v_cmpx_u_f64_e64 0.5, null
+// GFX12: encoding: [0x7e,0x00,0xa8,0xd4,0xf0,0xf8,0x00,0x00]
+
+v_cmpx_u_f64_e64 -|src_scc|, -|exec|
+// GFX12: encoding: [0x7e,0x03,0xa8,0xd4,0xfd,0xfc,0x00,0x60]
+
+v_cmpx_u_f64_e64 0xaf123456, -|vcc| clamp
+// GFX12: encoding: [0x7e,0x82,0xa8,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp16.s
new file mode 100644
index 000000000000..bae502f8210d
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp16.s
@@ -0,0 +1,2270 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
+
+v_cmpx_class_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_class_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_class_f16_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_class_f16_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_class_f16_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_class_f16_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_class_f16_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_class_f16_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_class_f16_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_class_f16_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_class_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_class_f16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cmpx_class_f16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cmpx_class_f16_e64_dpp -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x01,0xfd,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x05,0x30]
+
+v_cmpx_class_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_class_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_class_f32_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_class_f32_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_class_f32_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_class_f32_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_class_f32_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_class_f32_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_class_f32_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_class_f32_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_class_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_class_f32_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cmpx_class_f32_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cmpx_class_f32_e64_dpp -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x01,0xfe,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x05,0x30]
+
+v_cmpx_eq_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_eq_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_eq_f16_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_eq_f16_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_eq_f16_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_eq_f16_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_eq_f16_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_eq_f16_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_eq_f16_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_eq_f16_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_eq_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_eq_f16_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x01,0x82,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cmpx_eq_f16_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x02,0x82,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cmpx_eq_f16_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x83,0x82,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmpx_eq_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_eq_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_eq_f32_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_eq_f32_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_eq_f32_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_eq_f32_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_eq_f32_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_eq_f32_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_eq_f32_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_eq_f32_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_eq_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_eq_f32_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x01,0x92,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cmpx_eq_f32_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x02,0x92,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cmpx_eq_f32_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x83,0x92,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmpx_eq_i16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_eq_i16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_eq_i16_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_eq_i16_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_eq_i16_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_eq_i16_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_eq_i16_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_eq_i16_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_eq_i16_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_eq_i16_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_eq_i16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_eq_i16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cmpx_eq_i16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cmpx_eq_i16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x00,0xb2,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmpx_eq_i32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_eq_i32_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_eq_i32_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_eq_i32_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_eq_i32_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_eq_i32_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_eq_i32_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_eq_i32_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_eq_i32_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_eq_i32_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_eq_i32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_eq_i32_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cmpx_eq_i32_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cmpx_eq_i32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x00,0xc2,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmpx_eq_u16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_eq_u16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_eq_u16_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_eq_u16_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_eq_u16_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_eq_u16_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_eq_u16_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_eq_u16_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_eq_u16_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_eq_u16_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_eq_u16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_eq_u16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cmpx_eq_u16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cmpx_eq_u16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x00,0xba,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmpx_eq_u32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_eq_u32_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_eq_u32_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_eq_u32_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_eq_u32_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_eq_u32_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_eq_u32_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_eq_u32_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_eq_u32_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_eq_u32_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_eq_u32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_eq_u32_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cmpx_eq_u32_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cmpx_eq_u32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x00,0xca,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmpx_ge_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_ge_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_ge_f16_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_ge_f16_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_ge_f16_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_ge_f16_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_ge_f16_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_ge_f16_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_ge_f16_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_ge_f16_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_ge_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_ge_f16_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x01,0x86,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cmpx_ge_f16_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x02,0x86,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cmpx_ge_f16_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x83,0x86,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmpx_ge_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_ge_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_ge_f32_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_ge_f32_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_ge_f32_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_ge_f32_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_ge_f32_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_ge_f32_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_ge_f32_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_ge_f32_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_ge_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_ge_f32_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x01,0x96,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cmpx_ge_f32_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x02,0x96,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cmpx_ge_f32_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x83,0x96,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmpx_ge_i16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_ge_i16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_ge_i16_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_ge_i16_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_ge_i16_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_ge_i16_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_ge_i16_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_ge_i16_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_ge_i16_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_ge_i16_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_ge_i16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_ge_i16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cmpx_ge_i16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cmpx_ge_i16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x00,0xb6,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmpx_ge_i32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_ge_i32_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_ge_i32_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_ge_i32_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_ge_i32_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_ge_i32_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_ge_i32_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_ge_i32_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_ge_i32_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_ge_i32_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_ge_i32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_ge_i32_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cmpx_ge_i32_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cmpx_ge_i32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x00,0xc6,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmpx_ge_u16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_ge_u16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_ge_u16_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_ge_u16_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_ge_u16_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_ge_u16_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_ge_u16_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_ge_u16_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_ge_u16_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_ge_u16_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_ge_u16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_ge_u16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cmpx_ge_u16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cmpx_ge_u16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x00,0xbe,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmpx_ge_u32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_ge_u32_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_ge_u32_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_ge_u32_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_ge_u32_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_ge_u32_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_ge_u32_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_ge_u32_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_ge_u32_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_ge_u32_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_ge_u32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_ge_u32_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cmpx_ge_u32_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cmpx_ge_u32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x00,0xce,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmpx_gt_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_gt_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_gt_f16_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_gt_f16_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_gt_f16_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_gt_f16_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_gt_f16_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_gt_f16_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_gt_f16_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_gt_f16_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_gt_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_gt_f16_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x01,0x84,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cmpx_gt_f16_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x02,0x84,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cmpx_gt_f16_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x83,0x84,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmpx_gt_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_gt_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_gt_f32_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_gt_f32_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_gt_f32_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_gt_f32_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_gt_f32_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_gt_f32_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_gt_f32_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_gt_f32_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_gt_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_gt_f32_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x01,0x94,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cmpx_gt_f32_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x02,0x94,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cmpx_gt_f32_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x83,0x94,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmpx_gt_i16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_gt_i16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_gt_i16_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_gt_i16_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_gt_i16_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_gt_i16_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_gt_i16_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_gt_i16_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_gt_i16_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_gt_i16_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_gt_i16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_gt_i16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cmpx_gt_i16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cmpx_gt_i16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x00,0xb4,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmpx_gt_i32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_gt_i32_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_gt_i32_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_gt_i32_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_gt_i32_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_gt_i32_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_gt_i32_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_gt_i32_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_gt_i32_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_gt_i32_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_gt_i32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_gt_i32_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cmpx_gt_i32_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cmpx_gt_i32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x00,0xc4,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmpx_gt_u16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_gt_u16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_gt_u16_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_gt_u16_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_gt_u16_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_gt_u16_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_gt_u16_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_gt_u16_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_gt_u16_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_gt_u16_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_gt_u16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_gt_u16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cmpx_gt_u16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cmpx_gt_u16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x00,0xbc,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmpx_gt_u32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_gt_u32_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_gt_u32_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_gt_u32_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_gt_u32_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_gt_u32_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_gt_u32_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_gt_u32_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_gt_u32_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_gt_u32_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_gt_u32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_gt_u32_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cmpx_gt_u32_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cmpx_gt_u32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x00,0xcc,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmpx_le_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_le_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_le_f16_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_le_f16_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_le_f16_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_le_f16_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_le_f16_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_le_f16_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_le_f16_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_le_f16_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_le_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_le_f16_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x01,0x83,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cmpx_le_f16_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x02,0x83,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cmpx_le_f16_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x83,0x83,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmpx_le_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_le_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_le_f32_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_le_f32_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_le_f32_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_le_f32_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_le_f32_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_le_f32_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_le_f32_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_le_f32_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_le_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_le_f32_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x01,0x93,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cmpx_le_f32_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x02,0x93,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cmpx_le_f32_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x83,0x93,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmpx_le_i16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_le_i16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_le_i16_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_le_i16_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_le_i16_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_le_i16_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_le_i16_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_le_i16_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_le_i16_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_le_i16_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_le_i16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_le_i16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cmpx_le_i16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cmpx_le_i16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x00,0xb3,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmpx_le_i32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_le_i32_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_le_i32_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_le_i32_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_le_i32_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_le_i32_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_le_i32_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_le_i32_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_le_i32_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_le_i32_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_le_i32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_le_i32_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cmpx_le_i32_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cmpx_le_i32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x00,0xc3,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmpx_le_u16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_le_u16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_le_u16_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_le_u16_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_le_u16_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_le_u16_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_le_u16_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_le_u16_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_le_u16_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_le_u16_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_le_u16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_le_u16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cmpx_le_u16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cmpx_le_u16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x00,0xbb,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmpx_le_u32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_le_u32_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_le_u32_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_le_u32_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_le_u32_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_le_u32_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_le_u32_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_le_u32_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_le_u32_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_le_u32_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_le_u32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_le_u32_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cmpx_le_u32_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cmpx_le_u32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x00,0xcb,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmpx_lg_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_lg_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_lg_f16_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_lg_f16_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_lg_f16_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_lg_f16_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_lg_f16_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_lg_f16_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_lg_f16_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_lg_f16_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_lg_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_lg_f16_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x01,0x85,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cmpx_lg_f16_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x02,0x85,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cmpx_lg_f16_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x83,0x85,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmpx_lg_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_lg_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_lg_f32_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_lg_f32_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_lg_f32_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_lg_f32_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_lg_f32_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_lg_f32_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_lg_f32_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_lg_f32_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_lg_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_lg_f32_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x01,0x95,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cmpx_lg_f32_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x02,0x95,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cmpx_lg_f32_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x83,0x95,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmpx_lt_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_lt_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_lt_f16_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_lt_f16_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_lt_f16_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_lt_f16_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_lt_f16_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_lt_f16_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_lt_f16_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_lt_f16_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_lt_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_lt_f16_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x01,0x81,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cmpx_lt_f16_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x02,0x81,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cmpx_lt_f16_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x83,0x81,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmpx_lt_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_lt_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_lt_f32_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_lt_f32_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_lt_f32_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_lt_f32_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_lt_f32_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_lt_f32_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_lt_f32_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_lt_f32_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_lt_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_lt_f32_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x01,0x91,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cmpx_lt_f32_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x02,0x91,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cmpx_lt_f32_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x83,0x91,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmpx_lt_i16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_lt_i16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_lt_i16_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_lt_i16_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_lt_i16_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_lt_i16_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_lt_i16_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_lt_i16_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_lt_i16_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_lt_i16_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_lt_i16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_lt_i16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cmpx_lt_i16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cmpx_lt_i16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x00,0xb1,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmpx_lt_i32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_lt_i32_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_lt_i32_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_lt_i32_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_lt_i32_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_lt_i32_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_lt_i32_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_lt_i32_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_lt_i32_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_lt_i32_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_lt_i32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_lt_i32_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cmpx_lt_i32_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cmpx_lt_i32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x00,0xc1,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmpx_lt_u16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_lt_u16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_lt_u16_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_lt_u16_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_lt_u16_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_lt_u16_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_lt_u16_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_lt_u16_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_lt_u16_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_lt_u16_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_lt_u16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_lt_u16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cmpx_lt_u16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cmpx_lt_u16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x00,0xb9,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmpx_lt_u32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_lt_u32_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_lt_u32_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_lt_u32_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_lt_u32_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_lt_u32_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_lt_u32_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_lt_u32_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_lt_u32_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_lt_u32_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_lt_u32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_lt_u32_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cmpx_lt_u32_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cmpx_lt_u32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x00,0xc9,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmpx_ne_i16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_ne_i16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_ne_i16_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_ne_i16_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_ne_i16_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_ne_i16_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_ne_i16_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_ne_i16_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_ne_i16_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_ne_i16_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_ne_i16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_ne_i16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cmpx_ne_i16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cmpx_ne_i16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x00,0xb5,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmpx_ne_i32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_ne_i32_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_ne_i32_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_ne_i32_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_ne_i32_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_ne_i32_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_ne_i32_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_ne_i32_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_ne_i32_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_ne_i32_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_ne_i32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_ne_i32_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cmpx_ne_i32_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cmpx_ne_i32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x00,0xc5,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmpx_ne_u16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_ne_u16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_ne_u16_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_ne_u16_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_ne_u16_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_ne_u16_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_ne_u16_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_ne_u16_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_ne_u16_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_ne_u16_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_ne_u16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_ne_u16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cmpx_ne_u16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cmpx_ne_u16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x00,0xbd,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmpx_ne_u32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_ne_u32_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_ne_u32_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_ne_u32_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_ne_u32_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_ne_u32_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_ne_u32_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_ne_u32_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_ne_u32_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_ne_u32_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_ne_u32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_ne_u32_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cmpx_ne_u32_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cmpx_ne_u32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x00,0xcd,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+
+v_cmpx_neq_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_neq_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_neq_f16_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_neq_f16_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_neq_f16_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_neq_f16_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_neq_f16_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_neq_f16_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_neq_f16_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_neq_f16_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_neq_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_neq_f16_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x01,0x8d,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cmpx_neq_f16_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x02,0x8d,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cmpx_neq_f16_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x83,0x8d,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmpx_neq_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_neq_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_neq_f32_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_neq_f32_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_neq_f32_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_neq_f32_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_neq_f32_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_neq_f32_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_neq_f32_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_neq_f32_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_neq_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_neq_f32_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x01,0x9d,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cmpx_neq_f32_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x02,0x9d,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cmpx_neq_f32_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x83,0x9d,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmpx_nge_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_nge_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_nge_f16_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_nge_f16_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_nge_f16_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_nge_f16_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_nge_f16_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_nge_f16_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_nge_f16_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_nge_f16_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_nge_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_nge_f16_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x01,0x89,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cmpx_nge_f16_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x02,0x89,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cmpx_nge_f16_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x83,0x89,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmpx_nge_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_nge_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_nge_f32_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_nge_f32_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_nge_f32_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_nge_f32_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_nge_f32_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_nge_f32_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_nge_f32_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_nge_f32_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_nge_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_nge_f32_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x01,0x99,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cmpx_nge_f32_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x02,0x99,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cmpx_nge_f32_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x83,0x99,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmpx_ngt_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_ngt_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_ngt_f16_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_ngt_f16_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_ngt_f16_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_ngt_f16_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_ngt_f16_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_ngt_f16_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_ngt_f16_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_ngt_f16_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_ngt_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_ngt_f16_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x01,0x8b,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cmpx_ngt_f16_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x02,0x8b,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cmpx_ngt_f16_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x83,0x8b,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmpx_ngt_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_ngt_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_ngt_f32_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_ngt_f32_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_ngt_f32_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_ngt_f32_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_ngt_f32_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_ngt_f32_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_ngt_f32_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_ngt_f32_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_ngt_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_ngt_f32_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x01,0x9b,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cmpx_ngt_f32_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x02,0x9b,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cmpx_ngt_f32_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x83,0x9b,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmpx_nle_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_nle_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_nle_f16_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_nle_f16_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_nle_f16_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_nle_f16_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_nle_f16_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_nle_f16_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_nle_f16_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_nle_f16_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_nle_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_nle_f16_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x01,0x8c,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cmpx_nle_f16_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x02,0x8c,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cmpx_nle_f16_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x83,0x8c,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmpx_nle_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_nle_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_nle_f32_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_nle_f32_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_nle_f32_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_nle_f32_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_nle_f32_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_nle_f32_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_nle_f32_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_nle_f32_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_nle_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_nle_f32_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x01,0x9c,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cmpx_nle_f32_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x02,0x9c,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cmpx_nle_f32_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x83,0x9c,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmpx_nlg_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_nlg_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_nlg_f16_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_nlg_f16_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_nlg_f16_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_nlg_f16_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_nlg_f16_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_nlg_f16_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_nlg_f16_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_nlg_f16_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_nlg_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_nlg_f16_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x01,0x8a,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cmpx_nlg_f16_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x02,0x8a,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cmpx_nlg_f16_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x83,0x8a,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmpx_nlg_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_nlg_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_nlg_f32_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_nlg_f32_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_nlg_f32_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_nlg_f32_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_nlg_f32_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_nlg_f32_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_nlg_f32_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_nlg_f32_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_nlg_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_nlg_f32_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x01,0x9a,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cmpx_nlg_f32_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x02,0x9a,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cmpx_nlg_f32_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x83,0x9a,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmpx_nlt_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_nlt_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_nlt_f16_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_nlt_f16_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_nlt_f16_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_nlt_f16_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_nlt_f16_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_nlt_f16_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_nlt_f16_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_nlt_f16_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_nlt_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_nlt_f16_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x01,0x8e,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cmpx_nlt_f16_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x02,0x8e,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cmpx_nlt_f16_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x83,0x8e,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmpx_nlt_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_nlt_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_nlt_f32_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_nlt_f32_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_nlt_f32_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_nlt_f32_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_nlt_f32_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_nlt_f32_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_nlt_f32_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_nlt_f32_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_nlt_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_nlt_f32_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x01,0x9e,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cmpx_nlt_f32_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x02,0x9e,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cmpx_nlt_f32_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x83,0x9e,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmpx_o_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_o_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_o_f16_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_o_f16_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_o_f16_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_o_f16_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_o_f16_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_o_f16_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_o_f16_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_o_f16_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_o_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_o_f16_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x01,0x87,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cmpx_o_f16_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x02,0x87,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cmpx_o_f16_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x83,0x87,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmpx_o_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_o_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_o_f32_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_o_f32_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_o_f32_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_o_f32_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_o_f32_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_o_f32_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_o_f32_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_o_f32_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_o_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_o_f32_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x01,0x97,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cmpx_o_f32_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x02,0x97,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cmpx_o_f32_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x83,0x97,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmpx_u_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_u_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_u_f16_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_u_f16_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_u_f16_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_u_f16_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_u_f16_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_u_f16_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_u_f16_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_u_f16_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_u_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_u_f16_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x01,0x88,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cmpx_u_f16_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x02,0x88,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cmpx_u_f16_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x83,0x88,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmpx_u_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: [0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_u_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3]
+// GFX12: [0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+
+v_cmpx_u_f32_e64_dpp v1, v2 row_mirror
+// GFX12: [0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+
+v_cmpx_u_f32_e64_dpp v1, v2 row_half_mirror
+// GFX12: [0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+
+v_cmpx_u_f32_e64_dpp v1, v2 row_shl:1
+// GFX12: [0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+
+v_cmpx_u_f32_e64_dpp v1, v2 row_shl:15
+// GFX12: [0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+
+v_cmpx_u_f32_e64_dpp v1, v2 row_shr:1
+// GFX12: [0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+
+v_cmpx_u_f32_e64_dpp v1, v2 row_shr:15
+// GFX12: [0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+
+v_cmpx_u_f32_e64_dpp v1, v2 row_ror:1
+// GFX12: [0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+
+v_cmpx_u_f32_e64_dpp v1, v2 row_ror:15
+// GFX12: [0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+
+v_cmpx_u_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: [0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_cmpx_u_f32_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: [0x7e,0x01,0x98,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+
+v_cmpx_u_f32_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: [0x7e,0x02,0x98,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+
+v_cmpx_u_f32_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: [0x7e,0x83,0x98,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp8.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp8.s
new file mode 100644
index 000000000000..9f4b825ae47d
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp8.s
@@ -0,0 +1,572 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
+
+v_cmpx_class_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0xfd,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_class_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x00,0xfd,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_class_f16_e64_dpp -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x01,0xfd,0xd4,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00]
+
+v_cmpx_class_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0xfe,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_class_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x00,0xfe,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_class_f32_e64_dpp -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x01,0xfe,0xd4,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00]
+
+v_cmpx_eq_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0x82,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_eq_f16_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x01,0x82,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cmpx_eq_f16_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x02,0x82,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cmpx_eq_f16_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x83,0x82,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmpx_eq_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0x92,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_eq_f32_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x01,0x92,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cmpx_eq_f32_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x02,0x92,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cmpx_eq_f32_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x83,0x92,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmpx_eq_i16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0xb2,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_eq_i16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x00,0xb2,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_eq_i16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x00,0xb2,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmpx_eq_i32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0xc2,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_eq_i32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x00,0xc2,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_eq_i32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x00,0xc2,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmpx_eq_u16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0xba,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_eq_u16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x00,0xba,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_eq_u16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x00,0xba,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmpx_eq_u32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0xca,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_eq_u32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x00,0xca,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_eq_u32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x00,0xca,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmpx_ge_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0x86,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_ge_f16_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x01,0x86,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cmpx_ge_f16_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x02,0x86,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cmpx_ge_f16_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x83,0x86,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmpx_ge_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0x96,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_ge_f32_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x01,0x96,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cmpx_ge_f32_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x02,0x96,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cmpx_ge_f32_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x83,0x96,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmpx_ge_i16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0xb6,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_ge_i16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x00,0xb6,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_ge_i16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x00,0xb6,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmpx_ge_i32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0xc6,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_ge_i32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x00,0xc6,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_ge_i32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x00,0xc6,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmpx_ge_u16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0xbe,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_ge_u16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x00,0xbe,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_ge_u16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x00,0xbe,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmpx_ge_u32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0xce,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_ge_u32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x00,0xce,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_ge_u32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x00,0xce,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmpx_gt_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0x84,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_gt_f16_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x01,0x84,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cmpx_gt_f16_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x02,0x84,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cmpx_gt_f16_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x83,0x84,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmpx_gt_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0x94,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_gt_f32_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x01,0x94,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cmpx_gt_f32_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x02,0x94,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cmpx_gt_f32_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x83,0x94,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmpx_gt_i16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0xb4,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_gt_i16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x00,0xb4,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_gt_i16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x00,0xb4,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmpx_gt_i32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0xc4,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_gt_i32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x00,0xc4,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_gt_i32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x00,0xc4,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmpx_gt_u16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0xbc,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_gt_u16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x00,0xbc,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_gt_u16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x00,0xbc,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmpx_gt_u32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0xcc,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_gt_u32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x00,0xcc,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_gt_u32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x00,0xcc,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmpx_le_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0x83,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_le_f16_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x01,0x83,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cmpx_le_f16_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x02,0x83,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cmpx_le_f16_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x83,0x83,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmpx_le_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0x93,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_le_f32_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x01,0x93,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cmpx_le_f32_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x02,0x93,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cmpx_le_f32_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x83,0x93,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmpx_le_i16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0xb3,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_le_i16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x00,0xb3,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_le_i16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x00,0xb3,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmpx_le_i32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0xc3,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_le_i32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x00,0xc3,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_le_i32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x00,0xc3,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmpx_le_u16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0xbb,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_le_u16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x00,0xbb,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_le_u16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x00,0xbb,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmpx_le_u32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0xcb,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_le_u32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x00,0xcb,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_le_u32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x00,0xcb,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmpx_lg_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0x85,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_lg_f16_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x01,0x85,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cmpx_lg_f16_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x02,0x85,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cmpx_lg_f16_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x83,0x85,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmpx_lg_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0x95,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_lg_f32_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x01,0x95,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cmpx_lg_f32_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x02,0x95,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cmpx_lg_f32_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x83,0x95,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmpx_lt_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0x81,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_lt_f16_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x01,0x81,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cmpx_lt_f16_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x02,0x81,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cmpx_lt_f16_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x83,0x81,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmpx_lt_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0x91,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_lt_f32_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x01,0x91,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cmpx_lt_f32_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x02,0x91,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cmpx_lt_f32_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x83,0x91,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmpx_lt_i16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0xb1,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_lt_i16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x00,0xb1,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_lt_i16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x00,0xb1,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmpx_lt_i32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0xc1,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_lt_i32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x00,0xc1,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_lt_i32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x00,0xc1,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmpx_lt_u16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0xb9,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_lt_u16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x00,0xb9,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_lt_u16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x00,0xb9,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmpx_lt_u32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0xc9,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_lt_u32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x00,0xc9,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_lt_u32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x00,0xc9,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmpx_ne_i16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0xb5,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_ne_i16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x00,0xb5,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_ne_i16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x00,0xb5,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmpx_ne_i32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0xc5,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_ne_i32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x00,0xc5,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_ne_i32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x00,0xc5,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmpx_ne_u16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0xbd,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_ne_u16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x00,0xbd,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_ne_u16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x00,0xbd,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmpx_ne_u32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0xcd,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_ne_u32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x00,0xcd,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_ne_u32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x00,0xcd,0xd4,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+
+v_cmpx_neq_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0x8d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_neq_f16_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x01,0x8d,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cmpx_neq_f16_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x02,0x8d,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cmpx_neq_f16_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x83,0x8d,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmpx_neq_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0x9d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_neq_f32_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x01,0x9d,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cmpx_neq_f32_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x02,0x9d,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cmpx_neq_f32_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x83,0x9d,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmpx_nge_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0x89,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_nge_f16_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x01,0x89,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cmpx_nge_f16_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x02,0x89,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cmpx_nge_f16_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x83,0x89,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmpx_nge_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0x99,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_nge_f32_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x01,0x99,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cmpx_nge_f32_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x02,0x99,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cmpx_nge_f32_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x83,0x99,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmpx_ngt_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0x8b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_ngt_f16_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x01,0x8b,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cmpx_ngt_f16_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x02,0x8b,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cmpx_ngt_f16_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x83,0x8b,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmpx_ngt_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0x9b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_ngt_f32_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x01,0x9b,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cmpx_ngt_f32_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x02,0x9b,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cmpx_ngt_f32_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x83,0x9b,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmpx_nle_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0x8c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_nle_f16_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x01,0x8c,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cmpx_nle_f16_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x02,0x8c,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cmpx_nle_f16_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x83,0x8c,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmpx_nle_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0x9c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_nle_f32_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x01,0x9c,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cmpx_nle_f32_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x02,0x9c,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cmpx_nle_f32_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x83,0x9c,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmpx_nlg_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0x8a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_nlg_f16_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x01,0x8a,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cmpx_nlg_f16_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x02,0x8a,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cmpx_nlg_f16_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x83,0x8a,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmpx_nlg_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0x9a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_nlg_f32_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x01,0x9a,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cmpx_nlg_f32_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x02,0x9a,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cmpx_nlg_f32_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x83,0x9a,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmpx_nlt_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0x8e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_nlt_f16_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x01,0x8e,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cmpx_nlt_f16_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x02,0x8e,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cmpx_nlt_f16_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x83,0x8e,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmpx_nlt_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0x9e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_nlt_f32_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x01,0x9e,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cmpx_nlt_f32_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x02,0x9e,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cmpx_nlt_f32_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x83,0x9e,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmpx_o_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0x87,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_o_f16_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x01,0x87,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cmpx_o_f16_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x02,0x87,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cmpx_o_f16_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x83,0x87,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmpx_o_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0x97,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_o_f32_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x01,0x97,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cmpx_o_f32_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x02,0x97,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cmpx_o_f32_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x83,0x97,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmpx_u_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0x88,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_u_f16_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x01,0x88,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cmpx_u_f16_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x02,0x88,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cmpx_u_f16_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x83,0x88,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmpx_u_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x00,0x98,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_u_f32_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: [0x7e,0x01,0x98,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+
+v_cmpx_u_f32_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: [0x7e,0x02,0x98,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+v_cmpx_u_f32_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: [0x7e,0x83,0x98,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3p.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3p.s
new file mode 100644
index 000000000000..7a4687b34f8f
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3p.s
@@ -0,0 +1,1252 @@
+// RUN: llvm-mc -arch=amdgcn -show-encoding -mcpu=gfx1200 %s | FileCheck --check-prefix=GFX12 %s
+
+v_dot2_f32_bf16 v5, v1, v2, v3
+// GFX12: [0x05,0x40,0x1a,0xcc,0x01,0x05,0x0e,0x1c]
+
+v_dot2_f32_bf16 v5, v1, v2, s3
+// GFX12: [0x05,0x40,0x1a,0xcc,0x01,0x05,0x0e,0x18]
+
+v_dot2_f32_bf16 v5, v255, v255, s105
+// GFX12: [0x05,0x40,0x1a,0xcc,0xff,0xff,0xa7,0x19]
+
+v_dot2_f32_bf16 v5, s1, s2, v255
+// GFX12: [0x05,0x40,0x1a,0xcc,0x01,0x04,0xfc,0x1f]
+
+v_dot2_f32_bf16 v5, s105, s105, m0
+// GFX12: [0x05,0x40,0x1a,0xcc,0x69,0xd2,0xf4,0x19]
+
+v_dot2_f32_bf16 v5, vcc_lo, ttmp15, vcc_lo
+// GFX12: [0x05,0x40,0x1a,0xcc,0x6a,0xf6,0xa8,0x19]
+
+v_dot2_f32_bf16 v5, vcc_hi, 0xfe0b, vcc_hi
+// GFX12: [0x05,0x40,0x1a,0xcc,0x6b,0xfe,0xad,0x19,0x0b,0xfe,0x00,0x00]
+
+v_dot2_f32_bf16 v5, ttmp15, src_scc, ttmp15
+// GFX12: [0x05,0x40,0x1a,0xcc,0x7b,0xfa,0xed,0x19]
+
+v_dot2_f32_bf16 v5, m0, -1, exec_hi
+// GFX12: [0x05,0x40,0x1a,0xcc,0x7d,0x82,0xfd,0x19]
+
+v_dot2_f32_bf16 v5, exec_lo, null, exec_lo
+// GFX12: [0x05,0x40,0x1a,0xcc,0x7e,0xf8,0xf8,0x19]
+
+v_dot2_f32_bf16 v5, exec_hi, exec_lo, null
+// GFX12: [0x05,0x40,0x1a,0xcc,0x7f,0xfc,0xf0,0x19]
+
+v_dot2_f32_bf16 v5, null, exec_hi, -1
+// GFX12: [0x05,0x40,0x1a,0xcc,0x7c,0xfe,0x04,0x1b]
+
+v_dot2_f32_bf16 v5, -1, m0, 0xaf123456
+// GFX12: [0x05,0x40,0x1a,0xcc,0xc1,0xfa,0xfc,0x1b,0x56,0x34,0x12,0xaf]
+
+v_dot2_f32_bf16 v5, src_scc, vcc_lo, src_scc neg_lo:[1,0,0] neg_hi:[1,0,0]
+// GFX12: [0x05,0x41,0x1a,0xcc,0xfd,0xd4,0xf4,0x3b]
+
+v_dot2_f32_bf16 v255, 0xfe0b, vcc_hi, 0.5 neg_lo:[0,0,0] neg_hi:[0,0,0] clamp
+// GFX12: [0xff,0xc0,0x1a,0xcc,0xff,0xd6,0xc0,0x1b,0x0b,0xfe,0x00,0x00]
+
+v_dot2_f32_f16 v5, v1, v2, s3
+// GFX12: [0x05,0x40,0x13,0xcc,0x01,0x05,0x0e,0x18]
+
+v_dot2_f32_f16 v5, v255, s2, s105
+// GFX12: [0x05,0x40,0x13,0xcc,0xff,0x05,0xa4,0x19]
+
+v_dot2_f32_f16 v5, s1, v255, exec_hi
+// GFX12: [0x05,0x40,0x13,0xcc,0x01,0xfe,0xff,0x19]
+
+v_dot2_f32_f16 v5, s105, s105, exec_lo
+// GFX12: [0x05,0x40,0x13,0xcc,0x69,0xd2,0xf8,0x19]
+
+v_dot2_f32_f16 v5, vcc_lo, ttmp15, v3
+// GFX12: [0x05,0x40,0x13,0xcc,0x6a,0xf6,0x0c,0x1c]
+
+v_dot2_f32_f16 v5, vcc_hi, 0xfe0b, v255
+// GFX12: [0x05,0x40,0x13,0xcc,0x6b,0xfe,0xfd,0x1f,0x0b,0xfe,0x00,0x00]
+
+v_dot2_f32_f16 v5, ttmp15, src_scc, ttmp15
+// GFX12: [0x05,0x40,0x13,0xcc,0x7b,0xfa,0xed,0x19]
+
+v_dot2_f32_f16 v5, m0, 0.5, m0
+// GFX12: [0x05,0x40,0x13,0xcc,0x7d,0xe0,0xf5,0x19]
+
+v_dot2_f32_f16 v5, exec_lo, -1, vcc_hi
+// GFX12: [0x05,0x40,0x13,0xcc,0x7e,0x82,0xad,0x19]
+
+v_dot2_f32_f16 v5, exec_hi, null, vcc_lo
+// GFX12: [0x05,0x40,0x13,0xcc,0x7f,0xf8,0xa8,0x19]
+
+v_dot2_f32_f16 v5, null, exec_lo, 0xaf123456
+// GFX12: [0x05,0x40,0x13,0xcc,0x7c,0xfc,0xfc,0x1b,0x56,0x34,0x12,0xaf]
+
+v_dot2_f32_f16 v5, -1, exec_hi, src_scc
+// GFX12: [0x05,0x40,0x13,0xcc,0xc1,0xfe,0xf4,0x1b]
+
+v_dot2_f32_f16 v5, 0.5, m0, 0.5 neg_lo:[1,0,0] neg_hi:[1,0,0]
+// GFX12: [0x05,0x41,0x13,0xcc,0xf0,0xfa,0xc0,0x3b]
+
+v_dot2_f32_f16 v5, src_scc, vcc_lo, -1 neg_lo:[0,1,0] neg_hi:[0,1,0]
+// GFX12: [0x05,0x42,0x13,0xcc,0xfd,0xd4,0x04,0x5b]
+
+v_dot2_f32_f16 v255, 0xfe0b, vcc_hi, null neg_lo:[0,0,0] neg_hi:[0,0,0] clamp
+// GFX12: [0xff,0xc0,0x13,0xcc,0xff,0xd6,0xf0,0x19,0x0b,0xfe,0x00,0x00]
+
+v_dot4_i32_iu8 v5, v1, v2, s3
+// GFX12: [0x05,0x40,0x16,0xcc,0x01,0x05,0x0e,0x18]
+
+v_dot4_i32_iu8 v5, v255, s2, s105
+// GFX12: [0x05,0x40,0x16,0xcc,0xff,0x05,0xa4,0x19]
+
+v_dot4_i32_iu8 v5, s1, v255, exec_hi
+// GFX12: [0x05,0x40,0x16,0xcc,0x01,0xfe,0xff,0x19]
+
+v_dot4_i32_iu8 v5, s105, s105, exec_lo
+// GFX12: [0x05,0x40,0x16,0xcc,0x69,0xd2,0xf8,0x19]
+
+v_dot4_i32_iu8 v5, vcc_lo, ttmp15, v3
+// GFX12: [0x05,0x40,0x16,0xcc,0x6a,0xf6,0x0c,0x1c]
+
+v_dot4_i32_iu8 v5, vcc_hi, 0xaf123456, v255
+// GFX12: [0x05,0x40,0x16,0xcc,0x6b,0xfe,0xfd,0x1f,0x56,0x34,0x12,0xaf]
+
+v_dot4_i32_iu8 v5, ttmp15, src_scc, ttmp15
+// GFX12: [0x05,0x40,0x16,0xcc,0x7b,0xfa,0xed,0x19]
+
+v_dot4_i32_iu8 v5, m0, 0.5, m0
+// GFX12: [0x05,0x40,0x16,0xcc,0x7d,0xe0,0xf5,0x19]
+
+v_dot4_i32_iu8 v5, exec_lo, -1, vcc_hi
+// GFX12: [0x05,0x40,0x16,0xcc,0x7e,0x82,0xad,0x19]
+
+v_dot4_i32_iu8 v5, exec_hi, null, vcc_lo
+// GFX12: [0x05,0x40,0x16,0xcc,0x7f,0xf8,0xa8,0x19]
+
+v_dot4_i32_iu8 v5, null, exec_lo, 0xaf123456
+// GFX12: [0x05,0x40,0x16,0xcc,0x7c,0xfc,0xfc,0x1b,0x56,0x34,0x12,0xaf]
+
+v_dot4_i32_iu8 v5, -1, exec_hi, src_scc
+// GFX12: [0x05,0x40,0x16,0xcc,0xc1,0xfe,0xf4,0x1b]
+
+v_dot4_i32_iu8 v5, 0.5, m0, 0.5 neg_lo:[1,0,0]
+// GFX12: [0x05,0x40,0x16,0xcc,0xf0,0xfa,0xc0,0x3b]
+
+v_dot4_i32_iu8 v5, src_scc, vcc_lo, -1 neg_lo:[0,1,0]
+// GFX12: [0x05,0x40,0x16,0xcc,0xfd,0xd4,0x04,0x5b]
+
+v_dot4_i32_iu8 v255, 0xaf123456, vcc_hi, null neg_lo:[0,0,0]
+// GFX12: [0xff,0x40,0x16,0xcc,0xff,0xd6,0xf0,0x19,0x56,0x34,0x12,0xaf]
+
+v_dot4_u32_u8 v5, v1, v2, s3
+// GFX12: [0x05,0x40,0x17,0xcc,0x01,0x05,0x0e,0x18]
+
+v_dot4_u32_u8 v5, v255, s2, s105
+// GFX12: [0x05,0x40,0x17,0xcc,0xff,0x05,0xa4,0x19]
+
+v_dot4_u32_u8 v5, s1, v255, exec_hi
+// GFX12: [0x05,0x40,0x17,0xcc,0x01,0xfe,0xff,0x19]
+
+v_dot4_u32_u8 v5, s105, s105, exec_lo
+// GFX12: [0x05,0x40,0x17,0xcc,0x69,0xd2,0xf8,0x19]
+
+v_dot4_u32_u8 v5, vcc_lo, ttmp15, v3
+// GFX12: [0x05,0x40,0x17,0xcc,0x6a,0xf6,0x0c,0x1c]
+
+v_dot4_u32_u8 v5, vcc_hi, 0xaf123456, v255
+// GFX12: [0x05,0x40,0x17,0xcc,0x6b,0xfe,0xfd,0x1f,0x56,0x34,0x12,0xaf]
+
+v_dot4_u32_u8 v5, ttmp15, src_scc, ttmp15
+// GFX12: [0x05,0x40,0x17,0xcc,0x7b,0xfa,0xed,0x19]
+
+v_dot4_u32_u8 v5, m0, 0.5, m0
+// GFX12: [0x05,0x40,0x17,0xcc,0x7d,0xe0,0xf5,0x19]
+
+v_dot4_u32_u8 v5, exec_lo, -1, vcc_hi
+// GFX12: [0x05,0x40,0x17,0xcc,0x7e,0x82,0xad,0x19]
+
+v_dot4_u32_u8 v5, exec_hi, null, vcc_lo
+// GFX12: [0x05,0x40,0x17,0xcc,0x7f,0xf8,0xa8,0x19]
+
+v_dot4_u32_u8 v5, null, exec_lo, 0xaf123456
+// GFX12: [0x05,0x40,0x17,0xcc,0x7c,0xfc,0xfc,0x1b,0x56,0x34,0x12,0xaf]
+
+v_dot4_u32_u8 v5, -1, exec_hi, src_scc
+// GFX12: [0x05,0x40,0x17,0xcc,0xc1,0xfe,0xf4,0x1b]
+
+v_dot4_u32_u8 v5, 0.5, m0, 0.5
+// GFX12: [0x05,0x40,0x17,0xcc,0xf0,0xfa,0xc0,0x1b]
+
+v_dot4_u32_u8 v5, src_scc, vcc_lo, -1
+// GFX12: [0x05,0x40,0x17,0xcc,0xfd,0xd4,0x04,0x1b]
+
+v_dot4_u32_u8 v255, 0xaf123456, vcc_hi, null
+// GFX12: [0xff,0x40,0x17,0xcc,0xff,0xd6,0xf0,0x19,0x56,0x34,0x12,0xaf]
+
+v_dot8_i32_iu4 v5, v1, v2, s3
+// GFX12: [0x05,0x40,0x18,0xcc,0x01,0x05,0x0e,0x18]
+
+v_dot8_i32_iu4 v5, v255, s2, s105
+// GFX12: [0x05,0x40,0x18,0xcc,0xff,0x05,0xa4,0x19]
+
+v_dot8_i32_iu4 v5, s1, v255, exec_hi
+// GFX12: [0x05,0x40,0x18,0xcc,0x01,0xfe,0xff,0x19]
+
+v_dot8_i32_iu4 v5, s105, s105, exec_lo
+// GFX12: [0x05,0x40,0x18,0xcc,0x69,0xd2,0xf8,0x19]
+
+v_dot8_i32_iu4 v5, vcc_lo, ttmp15, v3
+// GFX12: [0x05,0x40,0x18,0xcc,0x6a,0xf6,0x0c,0x1c]
+
+v_dot8_i32_iu4 v5, vcc_hi, 0xaf123456, v255
+// GFX12: [0x05,0x40,0x18,0xcc,0x6b,0xfe,0xfd,0x1f,0x56,0x34,0x12,0xaf]
+
+v_dot8_i32_iu4 v5, ttmp15, src_scc, ttmp15
+// GFX12: [0x05,0x40,0x18,0xcc,0x7b,0xfa,0xed,0x19]
+
+v_dot8_i32_iu4 v5, m0, 0.5, m0
+// GFX12: [0x05,0x40,0x18,0xcc,0x7d,0xe0,0xf5,0x19]
+
+v_dot8_i32_iu4 v5, exec_lo, -1, vcc_hi
+// GFX12: [0x05,0x40,0x18,0xcc,0x7e,0x82,0xad,0x19]
+
+v_dot8_i32_iu4 v5, exec_hi, null, vcc_lo
+// GFX12: [0x05,0x40,0x18,0xcc,0x7f,0xf8,0xa8,0x19]
+
+v_dot8_i32_iu4 v5, null, exec_lo, 0xaf123456
+// GFX12: [0x05,0x40,0x18,0xcc,0x7c,0xfc,0xfc,0x1b,0x56,0x34,0x12,0xaf]
+
+v_dot8_i32_iu4 v5, -1, exec_hi, src_scc
+// GFX12: [0x05,0x40,0x18,0xcc,0xc1,0xfe,0xf4,0x1b]
+
+v_dot8_i32_iu4 v5, 0.5, m0, 0.5 neg_lo:[1,0,0]
+// GFX12: [0x05,0x40,0x18,0xcc,0xf0,0xfa,0xc0,0x3b]
+
+v_dot8_i32_iu4 v5, src_scc, vcc_lo, -1 neg_lo:[0,1,0]
+// GFX12: [0x05,0x40,0x18,0xcc,0xfd,0xd4,0x04,0x5b]
+
+v_dot8_i32_iu4 v255, 0xaf123456, vcc_hi, null neg_lo:[0,0,0] clamp
+// GFX12: [0xff,0xc0,0x18,0xcc,0xff,0xd6,0xf0,0x19,0x56,0x34,0x12,0xaf]
+
+v_dot8_u32_u4 v5, v1, v2, s3
+// GFX12: [0x05,0x40,0x19,0xcc,0x01,0x05,0x0e,0x18]
+
+v_dot8_u32_u4 v5, v255, s2, s105
+// GFX12: [0x05,0x40,0x19,0xcc,0xff,0x05,0xa4,0x19]
+
+v_dot8_u32_u4 v5, s1, v255, exec_hi
+// GFX12: [0x05,0x40,0x19,0xcc,0x01,0xfe,0xff,0x19]
+
+v_dot8_u32_u4 v5, s105, s105, exec_lo
+// GFX12: [0x05,0x40,0x19,0xcc,0x69,0xd2,0xf8,0x19]
+
+v_dot8_u32_u4 v5, vcc_lo, ttmp15, v3
+// GFX12: [0x05,0x40,0x19,0xcc,0x6a,0xf6,0x0c,0x1c]
+
+v_dot8_u32_u4 v5, vcc_hi, 0xaf123456, v255
+// GFX12: [0x05,0x40,0x19,0xcc,0x6b,0xfe,0xfd,0x1f,0x56,0x34,0x12,0xaf]
+
+v_dot8_u32_u4 v5, ttmp15, src_scc, ttmp15
+// GFX12: [0x05,0x40,0x19,0xcc,0x7b,0xfa,0xed,0x19]
+
+v_dot8_u32_u4 v5, m0, 0.5, m0
+// GFX12: [0x05,0x40,0x19,0xcc,0x7d,0xe0,0xf5,0x19]
+
+v_dot8_u32_u4 v5, exec_lo, -1, vcc_hi
+// GFX12: [0x05,0x40,0x19,0xcc,0x7e,0x82,0xad,0x19]
+
+v_dot8_u32_u4 v5, exec_hi, null, vcc_lo
+// GFX12: [0x05,0x40,0x19,0xcc,0x7f,0xf8,0xa8,0x19]
+
+v_dot8_u32_u4 v5, null, exec_lo, 0xaf123456
+// GFX12: [0x05,0x40,0x19,0xcc,0x7c,0xfc,0xfc,0x1b,0x56,0x34,0x12,0xaf]
+
+v_dot8_u32_u4 v5, -1, exec_hi, src_scc
+// GFX12: [0x05,0x40,0x19,0xcc,0xc1,0xfe,0xf4,0x1b]
+
+v_dot8_u32_u4 v5, 0.5, m0, 0.5
+// GFX12: [0x05,0x40,0x19,0xcc,0xf0,0xfa,0xc0,0x1b]
+
+v_dot8_u32_u4 v5, src_scc, vcc_lo, -1
+// GFX12: [0x05,0x40,0x19,0xcc,0xfd,0xd4,0x04,0x1b]
+
+v_dot8_u32_u4 v255, 0xaf123456, vcc_hi, null clamp
+// GFX12: [0xff,0xc0,0x19,0xcc,0xff,0xd6,0xf0,0x19,0x56,0x34,0x12,0xaf]
+
+v_fma_mix_f32 v5, v1, v2, s3
+// GFX12: [0x05,0x00,0x20,0xcc,0x01,0x05,0x0e,0x00]
+
+v_fma_mix_f32 v5, v255, v255, s105
+// GFX12: [0x05,0x00,0x20,0xcc,0xff,0xff,0xa7,0x01]
+
+v_fma_mix_f32 v5, s1, s2, v3
+// GFX12: [0x05,0x00,0x20,0xcc,0x01,0x04,0x0c,0x04]
+
+v_fma_mix_f32 v5, s105, s105, m0
+// GFX12: [0x05,0x00,0x20,0xcc,0x69,0xd2,0xf4,0x01]
+
+v_fma_mix_f32 v5, vcc_lo, ttmp15, ttmp15
+// GFX12: [0x05,0x00,0x20,0xcc,0x6a,0xf6,0xec,0x01]
+
+v_fma_mix_f32 v5, vcc_hi, src_scc, v255
+// GFX12: [0x05,0x00,0x20,0xcc,0x6b,0xfa,0xfd,0x07]
+
+v_fma_mix_f32 v5, |ttmp15|, 0.5, -vcc_hi
+// GFX12: [0x05,0x01,0x20,0xcc,0x7b,0xe0,0xad,0x81]
+
+v_fma_mix_f32 v5, -m0, -1, |vcc_lo|
+// GFX12: [0x05,0x04,0x20,0xcc,0x7d,0x82,0xa9,0x21]
+
+v_fma_mix_f32 v5, -|exec_lo|, null, -|src_scc|
+// GFX12: [0x05,0x05,0x20,0xcc,0x7e,0xf8,0xf4,0xa3]
+
+v_fma_mix_f32 v5, -|exec_hi|, -|exec_lo|, -|exec_lo| op_sel:[1,1,1] op_sel_hi:[1,1,1]
+// GFX12: [0x05,0x7f,0x20,0xcc,0x7f,0xfc,0xf8,0xf9]
+
+v_fma_mix_f32 v5, null, exec_hi, 0.5 op_sel:[0,0,0] op_sel_hi:[0,0,1]
+// GFX12: [0x05,0x40,0x20,0xcc,0x7c,0xfe,0xc0,0x03]
+
+v_fma_mix_f32 v5, -1, -|m0|, -1 op_sel:[1,0,0] op_sel_hi:[0,1,0]
+// GFX12: [0x05,0x0a,0x20,0xcc,0xc1,0xfa,0x04,0x53]
+
+v_fma_mix_f32 v5, 0.5, -|vcc_lo|, -|exec_hi| op_sel:[0,1,0] op_sel_hi:[1,0,0]
+// GFX12: [0x05,0x16,0x20,0xcc,0xf0,0xd4,0xfc,0xc9]
+
+v_fma_mix_f32 v255, -|src_scc|, -|vcc_hi|, null op_sel:[0,0,1] op_sel_hi:[0,0,0] clamp
+// GFX12: [0xff,0xa3,0x20,0xcc,0xfd,0xd6,0xf0,0x61]
+
+v_fma_mixhi_f16 v5, v1, v2, s3
+// GFX12: [0x05,0x00,0x22,0xcc,0x01,0x05,0x0e,0x00]
+
+v_fma_mixhi_f16 v5, v255, v255, s105
+// GFX12: [0x05,0x00,0x22,0xcc,0xff,0xff,0xa7,0x01]
+
+v_fma_mixhi_f16 v5, s1, s2, v3
+// GFX12: [0x05,0x00,0x22,0xcc,0x01,0x04,0x0c,0x04]
+
+v_fma_mixhi_f16 v5, s105, s105, m0
+// GFX12: [0x05,0x00,0x22,0xcc,0x69,0xd2,0xf4,0x01]
+
+v_fma_mixhi_f16 v5, vcc_lo, ttmp15, ttmp15
+// GFX12: [0x05,0x00,0x22,0xcc,0x6a,0xf6,0xec,0x01]
+
+v_fma_mixhi_f16 v5, vcc_hi, src_scc, v255
+// GFX12: [0x05,0x00,0x22,0xcc,0x6b,0xfa,0xfd,0x07]
+
+v_fma_mixhi_f16 v5, |ttmp15|, 0.5, -vcc_hi
+// GFX12: [0x05,0x01,0x22,0xcc,0x7b,0xe0,0xad,0x81]
+
+v_fma_mixhi_f16 v5, -m0, -1, |vcc_lo|
+// GFX12: [0x05,0x04,0x22,0xcc,0x7d,0x82,0xa9,0x21]
+
+v_fma_mixhi_f16 v5, -|exec_lo|, null, -|src_scc|
+// GFX12: [0x05,0x05,0x22,0xcc,0x7e,0xf8,0xf4,0xa3]
+
+v_fma_mixhi_f16 v5, -|exec_hi|, -|exec_lo|, -|exec_lo| op_sel:[1,1,1] op_sel_hi:[1,1,1]
+// GFX12: [0x05,0x7f,0x22,0xcc,0x7f,0xfc,0xf8,0xf9]
+
+v_fma_mixhi_f16 v5, null, exec_hi, 0.5 op_sel:[0,0,0] op_sel_hi:[0,0,1]
+// GFX12: [0x05,0x40,0x22,0xcc,0x7c,0xfe,0xc0,0x03]
+
+v_fma_mixhi_f16 v5, -1, -|m0|, -1 op_sel:[1,0,0] op_sel_hi:[0,1,0]
+// GFX12: [0x05,0x0a,0x22,0xcc,0xc1,0xfa,0x04,0x53]
+
+v_fma_mixhi_f16 v5, 0.5, -|vcc_lo|, -|exec_hi| op_sel:[0,1,0] op_sel_hi:[1,0,0]
+// GFX12: [0x05,0x16,0x22,0xcc,0xf0,0xd4,0xfc,0xc9]
+
+v_fma_mixhi_f16 v255, -|src_scc|, -|vcc_hi|, null op_sel:[0,0,1] op_sel_hi:[0,0,0] clamp
+// GFX12: [0xff,0xa3,0x22,0xcc,0xfd,0xd6,0xf0,0x61]
+
+v_fma_mixlo_f16 v5, v1, v2, s3
+// GFX12: [0x05,0x00,0x21,0xcc,0x01,0x05,0x0e,0x00]
+
+v_fma_mixlo_f16 v5, v255, v255, s105
+// GFX12: [0x05,0x00,0x21,0xcc,0xff,0xff,0xa7,0x01]
+
+v_fma_mixlo_f16 v5, s1, s2, v3
+// GFX12: [0x05,0x00,0x21,0xcc,0x01,0x04,0x0c,0x04]
+
+v_fma_mixlo_f16 v5, s105, s105, m0
+// GFX12: [0x05,0x00,0x21,0xcc,0x69,0xd2,0xf4,0x01]
+
+v_fma_mixlo_f16 v5, vcc_lo, ttmp15, ttmp15
+// GFX12: [0x05,0x00,0x21,0xcc,0x6a,0xf6,0xec,0x01]
+
+v_fma_mixlo_f16 v5, vcc_hi, src_scc, v255
+// GFX12: [0x05,0x00,0x21,0xcc,0x6b,0xfa,0xfd,0x07]
+
+v_fma_mixlo_f16 v5, |ttmp15|, 0.5, -vcc_hi
+// GFX12: [0x05,0x01,0x21,0xcc,0x7b,0xe0,0xad,0x81]
+
+v_fma_mixlo_f16 v5, -m0, -1, |vcc_lo|
+// GFX12: [0x05,0x04,0x21,0xcc,0x7d,0x82,0xa9,0x21]
+
+v_fma_mixlo_f16 v5, -|exec_lo|, null, -|src_scc|
+// GFX12: [0x05,0x05,0x21,0xcc,0x7e,0xf8,0xf4,0xa3]
+
+v_fma_mixlo_f16 v5, -|exec_hi|, -|exec_lo|, -|exec_lo| op_sel:[1,1,1] op_sel_hi:[1,1,1]
+// GFX12: [0x05,0x7f,0x21,0xcc,0x7f,0xfc,0xf8,0xf9]
+
+v_fma_mixlo_f16 v5, null, exec_hi, 0.5 op_sel:[0,0,0] op_sel_hi:[0,0,1]
+// GFX12: [0x05,0x40,0x21,0xcc,0x7c,0xfe,0xc0,0x03]
+
+v_fma_mixlo_f16 v5, -1, -|m0|, -1 op_sel:[1,0,0] op_sel_hi:[0,1,0]
+// GFX12: [0x05,0x0a,0x21,0xcc,0xc1,0xfa,0x04,0x53]
+
+v_fma_mixlo_f16 v5, 0.5, -|vcc_lo|, -|exec_hi| op_sel:[0,1,0] op_sel_hi:[1,0,0]
+// GFX12: [0x05,0x16,0x21,0xcc,0xf0,0xd4,0xfc,0xc9]
+
+v_fma_mixlo_f16 v255, -|src_scc|, -|vcc_hi|, null op_sel:[0,0,1] op_sel_hi:[0,0,0] clamp
+// GFX12: [0xff,0xa3,0x21,0xcc,0xfd,0xd6,0xf0,0x61]
+
+v_pk_add_f16 v5, v1, v2
+// GFX12: [0x05,0x40,0x0f,0xcc,0x01,0x05,0x02,0x18]
+
+v_pk_add_f16 v5, v255, v255
+// GFX12: [0x05,0x40,0x0f,0xcc,0xff,0xff,0x03,0x18]
+
+v_pk_add_f16 v5, s1, s2
+// GFX12: [0x05,0x40,0x0f,0xcc,0x01,0x04,0x00,0x18]
+
+v_pk_add_f16 v5, s105, s105
+// GFX12: [0x05,0x40,0x0f,0xcc,0x69,0xd2,0x00,0x18]
+
+v_pk_add_f16 v5, vcc_lo, ttmp15
+// GFX12: [0x05,0x40,0x0f,0xcc,0x6a,0xf6,0x00,0x18]
+
+v_pk_add_f16 v5, vcc_hi, 0xfe0b
+// GFX12: [0x05,0x40,0x0f,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+
+v_pk_add_f16 v5, ttmp15, src_scc
+// GFX12: [0x05,0x40,0x0f,0xcc,0x7b,0xfa,0x01,0x18]
+
+v_pk_add_f16 v5, m0, 0.5
+// GFX12: [0x05,0x40,0x0f,0xcc,0x7d,0xe0,0x01,0x18]
+
+v_pk_add_f16 v5, exec_lo, -1
+// GFX12: [0x05,0x40,0x0f,0xcc,0x7e,0x82,0x01,0x18]
+
+v_pk_add_f16 v5, exec_hi, null
+// GFX12: [0x05,0x40,0x0f,0xcc,0x7f,0xf8,0x00,0x18]
+
+v_pk_add_f16 v5, null, exec_lo
+// GFX12: [0x05,0x40,0x0f,0xcc,0x7c,0xfc,0x00,0x18]
+
+v_pk_add_f16 v5, -1, exec_hi op_sel:[1,1] op_sel_hi:[0,0] neg_lo:[1,0] neg_hi:[1,0]
+// GFX12: [0x05,0x59,0x0f,0xcc,0xc1,0xfe,0x00,0x20]
+
+v_pk_add_f16 v5, 0.5, m0 op_sel:[0,0] op_sel_hi:[1,1] neg_lo:[0,1] neg_hi:[0,1]
+// GFX12: [0x05,0x42,0x0f,0xcc,0xf0,0xfa,0x00,0x58]
+
+v_pk_add_f16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1] neg_lo:[0,0] neg_hi:[0,0]
+// GFX12: [0x05,0x48,0x0f,0xcc,0xfd,0xd4,0x00,0x10]
+
+v_pk_add_f16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] neg_lo:[1,1] neg_hi:[1,1] clamp
+// GFX12: [0xff,0xd3,0x0f,0xcc,0xff,0xd6,0x00,0x68,0x0b,0xfe,0x00,0x00]
+
+v_pk_add_i16 v5, v1, v2
+// GFX12: [0x05,0x40,0x02,0xcc,0x01,0x05,0x02,0x18]
+
+v_pk_add_i16 v5, v255, v255
+// GFX12: [0x05,0x40,0x02,0xcc,0xff,0xff,0x03,0x18]
+
+v_pk_add_i16 v5, s1, s2
+// GFX12: [0x05,0x40,0x02,0xcc,0x01,0x04,0x00,0x18]
+
+v_pk_add_i16 v5, s105, s105
+// GFX12: [0x05,0x40,0x02,0xcc,0x69,0xd2,0x00,0x18]
+
+v_pk_add_i16 v5, vcc_lo, ttmp15
+// GFX12: [0x05,0x40,0x02,0xcc,0x6a,0xf6,0x00,0x18]
+
+v_pk_add_i16 v5, vcc_hi, 0xfe0b
+// GFX12: [0x05,0x40,0x02,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+
+v_pk_add_i16 v5, ttmp15, src_scc
+// GFX12: [0x05,0x40,0x02,0xcc,0x7b,0xfa,0x01,0x18]
+
+v_pk_add_i16 v5, m0, 0.5
+// GFX12: [0x05,0x40,0x02,0xcc,0x7d,0xfe,0x01,0x18,0x00,0x38,0x00,0x00]
+
+v_pk_add_i16 v5, exec_lo, -1
+// GFX12: [0x05,0x40,0x02,0xcc,0x7e,0x82,0x01,0x18]
+
+v_pk_add_i16 v5, exec_hi, null
+// GFX12: [0x05,0x40,0x02,0xcc,0x7f,0xf8,0x00,0x18]
+
+v_pk_add_i16 v5, null, exec_lo
+// GFX12: [0x05,0x40,0x02,0xcc,0x7c,0xfc,0x00,0x18]
+
+v_pk_add_i16 v5, -1, exec_hi op_sel:[1,1] op_sel_hi:[0,0]
+// GFX12: [0x05,0x58,0x02,0xcc,0xc1,0xfe,0x00,0x00]
+
+v_pk_add_i16 v5, 0.5, m0 op_sel:[0,0] op_sel_hi:[1,1]
+// GFX12: [0x05,0x40,0x02,0xcc,0xff,0xfa,0x00,0x18,0x00,0x38,0x00,0x00]
+
+v_pk_add_i16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1]
+// GFX12: [0x05,0x48,0x02,0xcc,0xfd,0xd4,0x00,0x10]
+
+v_pk_add_i16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] clamp
+// GFX12: [0xff,0xd0,0x02,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00]
+
+v_pk_add_u16 v5, v1, v2
+// GFX12: [0x05,0x40,0x0a,0xcc,0x01,0x05,0x02,0x18]
+
+v_pk_add_u16 v5, v255, v255
+// GFX12: [0x05,0x40,0x0a,0xcc,0xff,0xff,0x03,0x18]
+
+v_pk_add_u16 v5, s1, s2
+// GFX12: [0x05,0x40,0x0a,0xcc,0x01,0x04,0x00,0x18]
+
+v_pk_add_u16 v5, s105, s105
+// GFX12: [0x05,0x40,0x0a,0xcc,0x69,0xd2,0x00,0x18]
+
+v_pk_add_u16 v5, vcc_lo, ttmp15
+// GFX12: [0x05,0x40,0x0a,0xcc,0x6a,0xf6,0x00,0x18]
+
+v_pk_add_u16 v5, vcc_hi, 0xfe0b
+// GFX12: [0x05,0x40,0x0a,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+
+v_pk_add_u16 v5, ttmp15, src_scc
+// GFX12: [0x05,0x40,0x0a,0xcc,0x7b,0xfa,0x01,0x18]
+
+v_pk_add_u16 v5, m0, 0.5
+// GFX12: [0x05,0x40,0x0a,0xcc,0x7d,0xfe,0x01,0x18,0x00,0x38,0x00,0x00]
+
+v_pk_add_u16 v5, exec_lo, -1
+// GFX12: [0x05,0x40,0x0a,0xcc,0x7e,0x82,0x01,0x18]
+
+v_pk_add_u16 v5, exec_hi, null
+// GFX12: [0x05,0x40,0x0a,0xcc,0x7f,0xf8,0x00,0x18]
+
+v_pk_add_u16 v5, null, exec_lo
+// GFX12: [0x05,0x40,0x0a,0xcc,0x7c,0xfc,0x00,0x18]
+
+v_pk_add_u16 v5, -1, exec_hi op_sel:[1,1] op_sel_hi:[0,0]
+// GFX12: [0x05,0x58,0x0a,0xcc,0xc1,0xfe,0x00,0x00]
+
+v_pk_add_u16 v5, 0.5, m0 op_sel:[0,0] op_sel_hi:[1,1]
+// GFX12: [0x05,0x40,0x0a,0xcc,0xff,0xfa,0x00,0x18,0x00,0x38,0x00,0x00]
+
+v_pk_add_u16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1]
+// GFX12: [0x05,0x48,0x0a,0xcc,0xfd,0xd4,0x00,0x10]
+
+v_pk_add_u16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] clamp
+// GFX12: [0xff,0xd0,0x0a,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00]
+
+v_pk_ashrrev_i16 v5, v1, v2
+// GFX12: [0x05,0x40,0x06,0xcc,0x01,0x05,0x02,0x18]
+
+v_pk_ashrrev_i16 v5, v255, v255
+// GFX12: [0x05,0x40,0x06,0xcc,0xff,0xff,0x03,0x18]
+
+v_pk_ashrrev_i16 v5, s1, s2
+// GFX12: [0x05,0x40,0x06,0xcc,0x01,0x04,0x00,0x18]
+
+v_pk_ashrrev_i16 v5, s105, s105
+// GFX12: [0x05,0x40,0x06,0xcc,0x69,0xd2,0x00,0x18]
+
+v_pk_ashrrev_i16 v5, vcc_lo, ttmp15
+// GFX12: [0x05,0x40,0x06,0xcc,0x6a,0xf6,0x00,0x18]
+
+v_pk_ashrrev_i16 v5, vcc_hi, 0xfe0b
+// GFX12: [0x05,0x40,0x06,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+
+v_pk_ashrrev_i16 v5, ttmp15, src_scc
+// GFX12: [0x05,0x40,0x06,0xcc,0x7b,0xfa,0x01,0x18]
+
+v_pk_ashrrev_i16 v5, m0, 0.5
+// GFX12: [0x05,0x40,0x06,0xcc,0x7d,0xfe,0x01,0x18,0x00,0x38,0x00,0x00]
+
+v_pk_ashrrev_i16 v5, exec_lo, -1
+// GFX12: [0x05,0x40,0x06,0xcc,0x7e,0x82,0x01,0x18]
+
+v_pk_ashrrev_i16 v5, exec_hi, null
+// GFX12: [0x05,0x40,0x06,0xcc,0x7f,0xf8,0x00,0x18]
+
+v_pk_ashrrev_i16 v5, null, exec_lo
+// GFX12: [0x05,0x40,0x06,0xcc,0x7c,0xfc,0x00,0x18]
+
+v_pk_ashrrev_i16 v5, -1, exec_hi op_sel:[1,1] op_sel_hi:[0,0]
+// GFX12: [0x05,0x58,0x06,0xcc,0xc1,0xfe,0x00,0x00]
+
+v_pk_ashrrev_i16 v5, 0.5, m0 op_sel:[0,0] op_sel_hi:[1,1]
+// GFX12: [0x05,0x40,0x06,0xcc,0xff,0xfa,0x00,0x18,0x00,0x38,0x00,0x00]
+
+v_pk_ashrrev_i16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1]
+// GFX12: [0x05,0x48,0x06,0xcc,0xfd,0xd4,0x00,0x10]
+
+v_pk_ashrrev_i16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0]
+// GFX12: [0xff,0x50,0x06,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00]
+
+v_pk_fma_f16 v5, v1, v2, s3
+// GFX12: [0x05,0x40,0x0e,0xcc,0x01,0x05,0x0e,0x18]
+
+v_pk_fma_f16 v5, v255, s2, s105
+// GFX12: [0x05,0x40,0x0e,0xcc,0xff,0x05,0xa4,0x19]
+
+v_pk_fma_f16 v5, s1, v255, exec_hi
+// GFX12: [0x05,0x40,0x0e,0xcc,0x01,0xfe,0xff,0x19]
+
+v_pk_fma_f16 v5, s105, s105, exec_lo
+// GFX12: [0x05,0x40,0x0e,0xcc,0x69,0xd2,0xf8,0x19]
+
+v_pk_fma_f16 v5, vcc_lo, ttmp15, v3
+// GFX12: [0x05,0x40,0x0e,0xcc,0x6a,0xf6,0x0c,0x1c]
+
+v_pk_fma_f16 v5, vcc_hi, 0xfe0b, v255
+// GFX12: [0x05,0x40,0x0e,0xcc,0x6b,0xfe,0xfd,0x1f,0x0b,0xfe,0x00,0x00]
+
+v_pk_fma_f16 v5, ttmp15, src_scc, ttmp15
+// GFX12: [0x05,0x40,0x0e,0xcc,0x7b,0xfa,0xed,0x19]
+
+v_pk_fma_f16 v5, m0, 0.5, m0 op_sel_hi:[0,0,0]
+// GFX12: [0x05,0x00,0x0e,0xcc,0x7d,0xe0,0xf5,0x01]
+
+v_pk_fma_f16 v5, exec_lo, -1, vcc_hi op_sel_hi:[0,0,1]
+// GFX12: [0x05,0x40,0x0e,0xcc,0x7e,0x82,0xad,0x01]
+
+v_pk_fma_f16 v5, exec_hi, null, vcc_lo op_sel_hi:[0,1,0]
+// GFX12: [0x05,0x00,0x0e,0xcc,0x7f,0xf8,0xa8,0x11]
+
+v_pk_fma_f16 v5, null, exec_lo, 0xfe0b op_sel:[1,1,1] op_sel_hi:[1,0,0] neg_lo:[1,0,0] neg_hi:[1,0,0]
+// GFX12: [0x05,0x39,0x0e,0xcc,0x7c,0xfc,0xfc,0x2b,0x0b,0xfe,0x00,0x00]
+
+v_pk_fma_f16 v5, -1, exec_hi, src_scc op_sel:[0,0,0] op_sel_hi:[1,1,1] neg_lo:[0,1,0] neg_hi:[0,1,0]
+// GFX12: [0x05,0x42,0x0e,0xcc,0xc1,0xfe,0xf4,0x5b]
+
+v_pk_fma_f16 v5, 0.5, m0, 0.5 op_sel:[1,0,0] op_sel_hi:[0,1,1] neg_lo:[0,0,1] neg_hi:[0,0,1]
+// GFX12: [0x05,0x4c,0x0e,0xcc,0xf0,0xfa,0xc0,0x93]
+
+v_pk_fma_f16 v5, src_scc, vcc_lo, -1 op_sel:[0,1,0] op_sel_hi:[1,0,1] neg_lo:[0,0,0] neg_hi:[0,0,0]
+// GFX12: [0x05,0x50,0x0e,0xcc,0xfd,0xd4,0x04,0x0b]
+
+v_pk_fma_f16 v255, 0xfe0b, vcc_hi, null op_sel:[0,0,1] op_sel_hi:[1,1,0] neg_lo:[1,1,1] neg_hi:[1,1,1] clamp
+// GFX12: [0xff,0xa7,0x0e,0xcc,0xff,0xd6,0xf0,0xf9,0x0b,0xfe,0x00,0x00]
+
+v_pk_lshlrev_b16 v5, v1, v2
+// GFX12: [0x05,0x40,0x04,0xcc,0x01,0x05,0x02,0x18]
+
+v_pk_lshlrev_b16 v5, v255, v255
+// GFX12: [0x05,0x40,0x04,0xcc,0xff,0xff,0x03,0x18]
+
+v_pk_lshlrev_b16 v5, s1, s2
+// GFX12: [0x05,0x40,0x04,0xcc,0x01,0x04,0x00,0x18]
+
+v_pk_lshlrev_b16 v5, s105, s105
+// GFX12: [0x05,0x40,0x04,0xcc,0x69,0xd2,0x00,0x18]
+
+v_pk_lshlrev_b16 v5, vcc_lo, ttmp15
+// GFX12: [0x05,0x40,0x04,0xcc,0x6a,0xf6,0x00,0x18]
+
+v_pk_lshlrev_b16 v5, vcc_hi, 0xfe0b
+// GFX12: [0x05,0x40,0x04,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+
+v_pk_lshlrev_b16 v5, ttmp15, src_scc
+// GFX12: [0x05,0x40,0x04,0xcc,0x7b,0xfa,0x01,0x18]
+
+v_pk_lshlrev_b16 v5, m0, 0.5
+// GFX12: [0x05,0x40,0x04,0xcc,0x7d,0xfe,0x01,0x18,0x00,0x38,0x00,0x00]
+
+v_pk_lshlrev_b16 v5, exec_lo, -1
+// GFX12: [0x05,0x40,0x04,0xcc,0x7e,0x82,0x01,0x18]
+
+v_pk_lshlrev_b16 v5, exec_hi, null
+// GFX12: [0x05,0x40,0x04,0xcc,0x7f,0xf8,0x00,0x18]
+
+v_pk_lshlrev_b16 v5, null, exec_lo
+// GFX12: [0x05,0x40,0x04,0xcc,0x7c,0xfc,0x00,0x18]
+
+v_pk_lshlrev_b16 v5, -1, exec_hi op_sel:[1,1] op_sel_hi:[0,0]
+// GFX12: [0x05,0x58,0x04,0xcc,0xc1,0xfe,0x00,0x00]
+
+v_pk_lshlrev_b16 v5, 0.5, m0 op_sel:[0,0] op_sel_hi:[1,1]
+// GFX12: [0x05,0x40,0x04,0xcc,0xff,0xfa,0x00,0x18,0x00,0x38,0x00,0x00]
+
+v_pk_lshlrev_b16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1]
+// GFX12: [0x05,0x48,0x04,0xcc,0xfd,0xd4,0x00,0x10]
+
+v_pk_lshlrev_b16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0]
+// GFX12: [0xff,0x50,0x04,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00]
+
+v_pk_lshrrev_b16 v5, v1, v2
+// GFX12: [0x05,0x40,0x05,0xcc,0x01,0x05,0x02,0x18]
+
+v_pk_lshrrev_b16 v5, v255, v255
+// GFX12: [0x05,0x40,0x05,0xcc,0xff,0xff,0x03,0x18]
+
+v_pk_lshrrev_b16 v5, s1, s2
+// GFX12: [0x05,0x40,0x05,0xcc,0x01,0x04,0x00,0x18]
+
+v_pk_lshrrev_b16 v5, s105, s105
+// GFX12: [0x05,0x40,0x05,0xcc,0x69,0xd2,0x00,0x18]
+
+v_pk_lshrrev_b16 v5, vcc_lo, ttmp15
+// GFX12: [0x05,0x40,0x05,0xcc,0x6a,0xf6,0x00,0x18]
+
+v_pk_lshrrev_b16 v5, vcc_hi, 0xfe0b
+// GFX12: [0x05,0x40,0x05,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+
+v_pk_lshrrev_b16 v5, ttmp15, src_scc
+// GFX12: [0x05,0x40,0x05,0xcc,0x7b,0xfa,0x01,0x18]
+
+v_pk_lshrrev_b16 v5, m0, 0.5
+// GFX12: [0x05,0x40,0x05,0xcc,0x7d,0xfe,0x01,0x18,0x00,0x38,0x00,0x00]
+
+v_pk_lshrrev_b16 v5, exec_lo, -1
+// GFX12: [0x05,0x40,0x05,0xcc,0x7e,0x82,0x01,0x18]
+
+v_pk_lshrrev_b16 v5, exec_hi, null
+// GFX12: [0x05,0x40,0x05,0xcc,0x7f,0xf8,0x00,0x18]
+
+v_pk_lshrrev_b16 v5, null, exec_lo
+// GFX12: [0x05,0x40,0x05,0xcc,0x7c,0xfc,0x00,0x18]
+
+v_pk_lshrrev_b16 v5, -1, exec_hi op_sel:[1,1] op_sel_hi:[0,0]
+// GFX12: [0x05,0x58,0x05,0xcc,0xc1,0xfe,0x00,0x00]
+
+v_pk_lshrrev_b16 v5, 0.5, m0 op_sel:[0,0] op_sel_hi:[1,1]
+// GFX12: [0x05,0x40,0x05,0xcc,0xff,0xfa,0x00,0x18,0x00,0x38,0x00,0x00]
+
+v_pk_lshrrev_b16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1]
+// GFX12: [0x05,0x48,0x05,0xcc,0xfd,0xd4,0x00,0x10]
+
+v_pk_lshrrev_b16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0]
+// GFX12: [0xff,0x50,0x05,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00]
+
+v_pk_mad_i16 v5, v1, v2, s3
+// GFX12: [0x05,0x40,0x00,0xcc,0x01,0x05,0x0e,0x18]
+
+v_pk_mad_i16 v5, v255, s2, s105
+// GFX12: [0x05,0x40,0x00,0xcc,0xff,0x05,0xa4,0x19]
+
+v_pk_mad_i16 v5, s1, v255, exec_hi
+// GFX12: [0x05,0x40,0x00,0xcc,0x01,0xfe,0xff,0x19]
+
+v_pk_mad_i16 v5, s105, s105, exec_lo
+// GFX12: [0x05,0x40,0x00,0xcc,0x69,0xd2,0xf8,0x19]
+
+v_pk_mad_i16 v5, vcc_lo, ttmp15, v3
+// GFX12: [0x05,0x40,0x00,0xcc,0x6a,0xf6,0x0c,0x1c]
+
+v_pk_mad_i16 v5, vcc_hi, 0xfe0b, v255
+// GFX12: [0x05,0x40,0x00,0xcc,0x6b,0xfe,0xfd,0x1f,0x0b,0xfe,0x00,0x00]
+
+v_pk_mad_i16 v5, ttmp15, src_scc, ttmp15
+// GFX12: [0x05,0x40,0x00,0xcc,0x7b,0xfa,0xed,0x19]
+
+v_pk_mad_i16 v5, m0, 0.5, m0 op_sel_hi:[0,0,0]
+// GFX12: [0x05,0x00,0x00,0xcc,0x7d,0xfe,0xf5,0x01,0x00,0x38,0x00,0x00]
+
+v_pk_mad_i16 v5, exec_lo, -1, vcc_hi op_sel_hi:[0,0,1]
+// GFX12: [0x05,0x40,0x00,0xcc,0x7e,0x82,0xad,0x01]
+
+v_pk_mad_i16 v5, exec_hi, null, vcc_lo op_sel_hi:[0,1,0]
+// GFX12: [0x05,0x00,0x00,0xcc,0x7f,0xf8,0xa8,0x11]
+
+v_pk_mad_i16 v5, null, exec_lo, 0xfe0b op_sel:[1,1,1] op_sel_hi:[1,0,0]
+// GFX12: [0x05,0x38,0x00,0xcc,0x7c,0xfc,0xfc,0x0b,0x0b,0xfe,0x00,0x00]
+
+v_pk_mad_i16 v5, -1, exec_hi, src_scc op_sel:[0,0,0] op_sel_hi:[1,1,1]
+// GFX12: [0x05,0x40,0x00,0xcc,0xc1,0xfe,0xf4,0x1b]
+
+v_pk_mad_i16 v5, 0.5, m0, 0.5 op_sel:[1,0,0] op_sel_hi:[0,1,1]
+// GFX12: [0x05,0x48,0x00,0xcc,0xff,0xfa,0xfc,0x13,0x00,0x38,0x00,0x00]
+
+v_pk_mad_i16 v5, src_scc, vcc_lo, -1 op_sel:[0,1,0] op_sel_hi:[1,0,1]
+// GFX12: [0x05,0x50,0x00,0xcc,0xfd,0xd4,0x04,0x0b]
+
+v_pk_mad_i16 v255, 0xfe0b, vcc_hi, null op_sel:[0,0,1] op_sel_hi:[1,1,0] clamp
+// GFX12: [0xff,0xa0,0x00,0xcc,0xff,0xd6,0xf0,0x19,0x0b,0xfe,0x00,0x00]
+
+v_pk_mad_u16 v5, v1, v2, s3
+// GFX12: [0x05,0x40,0x09,0xcc,0x01,0x05,0x0e,0x18]
+
+v_pk_mad_u16 v5, v255, s2, s105
+// GFX12: [0x05,0x40,0x09,0xcc,0xff,0x05,0xa4,0x19]
+
+v_pk_mad_u16 v5, s1, v255, exec_hi
+// GFX12: [0x05,0x40,0x09,0xcc,0x01,0xfe,0xff,0x19]
+
+v_pk_mad_u16 v5, s105, s105, exec_lo
+// GFX12: [0x05,0x40,0x09,0xcc,0x69,0xd2,0xf8,0x19]
+
+v_pk_mad_u16 v5, vcc_lo, ttmp15, v3
+// GFX12: [0x05,0x40,0x09,0xcc,0x6a,0xf6,0x0c,0x1c]
+
+v_pk_mad_u16 v5, vcc_hi, 0xfe0b, v255
+// GFX12: [0x05,0x40,0x09,0xcc,0x6b,0xfe,0xfd,0x1f,0x0b,0xfe,0x00,0x00]
+
+v_pk_mad_u16 v5, ttmp15, src_scc, ttmp15
+// GFX12: [0x05,0x40,0x09,0xcc,0x7b,0xfa,0xed,0x19]
+
+v_pk_mad_u16 v5, m0, 0.5, m0 op_sel_hi:[0,0,0]
+// GFX12: [0x05,0x00,0x09,0xcc,0x7d,0xfe,0xf5,0x01,0x00,0x38,0x00,0x00]
+
+v_pk_mad_u16 v5, exec_lo, -1, vcc_hi op_sel_hi:[0,0,1]
+// GFX12: [0x05,0x40,0x09,0xcc,0x7e,0x82,0xad,0x01]
+
+v_pk_mad_u16 v5, exec_hi, null, vcc_lo op_sel_hi:[0,1,0]
+// GFX12: [0x05,0x00,0x09,0xcc,0x7f,0xf8,0xa8,0x11]
+
+v_pk_mad_u16 v5, null, exec_lo, 0xfe0b op_sel:[1,1,1] op_sel_hi:[1,0,0]
+// GFX12: [0x05,0x38,0x09,0xcc,0x7c,0xfc,0xfc,0x0b,0x0b,0xfe,0x00,0x00]
+
+v_pk_mad_u16 v5, -1, exec_hi, src_scc op_sel:[0,0,0] op_sel_hi:[1,1,1]
+// GFX12: [0x05,0x40,0x09,0xcc,0xc1,0xfe,0xf4,0x1b]
+
+v_pk_mad_u16 v5, 0.5, m0, 0.5 op_sel:[1,0,0] op_sel_hi:[0,1,1]
+// GFX12: [0x05,0x48,0x09,0xcc,0xff,0xfa,0xfc,0x13,0x00,0x38,0x00,0x00]
+
+v_pk_mad_u16 v5, src_scc, vcc_lo, -1 op_sel:[0,1,0] op_sel_hi:[1,0,1]
+// GFX12: [0x05,0x50,0x09,0xcc,0xfd,0xd4,0x04,0x0b]
+
+v_pk_mad_u16 v255, 0xfe0b, vcc_hi, null op_sel:[0,0,1] op_sel_hi:[1,1,0] clamp
+// GFX12: [0xff,0xa0,0x09,0xcc,0xff,0xd6,0xf0,0x19,0x0b,0xfe,0x00,0x00]
+
+v_pk_max_num_f16 v5, v1, v2
+// GFX12: [0x05,0x40,0x1c,0xcc,0x01,0x05,0x02,0x18]
+
+v_pk_max_num_f16 v5, v255, v255
+// GFX12: [0x05,0x40,0x1c,0xcc,0xff,0xff,0x03,0x18]
+
+v_pk_max_num_f16 v5, s1, s2
+// GFX12: [0x05,0x40,0x1c,0xcc,0x01,0x04,0x00,0x18]
+
+v_pk_max_num_f16 v5, s105, s105
+// GFX12: [0x05,0x40,0x1c,0xcc,0x69,0xd2,0x00,0x18]
+
+v_pk_max_num_f16 v5, vcc_lo, ttmp15
+// GFX12: [0x05,0x40,0x1c,0xcc,0x6a,0xf6,0x00,0x18]
+
+v_pk_max_num_f16 v5, vcc_hi, 0xfe0b
+// GFX12: [0x05,0x40,0x1c,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+
+v_pk_max_num_f16 v5, ttmp15, src_scc
+// GFX12: [0x05,0x40,0x1c,0xcc,0x7b,0xfa,0x01,0x18]
+
+v_pk_max_num_f16 v5, m0, 0.5
+// GFX12: [0x05,0x40,0x1c,0xcc,0x7d,0xe0,0x01,0x18]
+
+v_pk_max_num_f16 v5, exec_lo, -1
+// GFX12: [0x05,0x40,0x1c,0xcc,0x7e,0x82,0x01,0x18]
+
+v_pk_max_num_f16 v5, exec_hi, null
+// GFX12: [0x05,0x40,0x1c,0xcc,0x7f,0xf8,0x00,0x18]
+
+v_pk_max_num_f16 v5, null, exec_lo
+// GFX12: [0x05,0x40,0x1c,0xcc,0x7c,0xfc,0x00,0x18]
+
+v_pk_max_num_f16 v5, -1, exec_hi op_sel:[1,1] op_sel_hi:[0,0] neg_lo:[1,0] neg_hi:[1,0]
+// GFX12: [0x05,0x59,0x1c,0xcc,0xc1,0xfe,0x00,0x20]
+
+v_pk_max_num_f16 v5, 0.5, m0 op_sel:[0,0] op_sel_hi:[1,1] neg_lo:[0,1] neg_hi:[0,1]
+// GFX12: [0x05,0x42,0x1c,0xcc,0xf0,0xfa,0x00,0x58]
+
+v_pk_max_num_f16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1] neg_lo:[0,0] neg_hi:[0,0]
+// GFX12: [0x05,0x48,0x1c,0xcc,0xfd,0xd4,0x00,0x10]
+
+v_pk_max_num_f16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] neg_lo:[1,1] neg_hi:[1,1] clamp
+// GFX12: [0xff,0xd3,0x1c,0xcc,0xff,0xd6,0x00,0x68,0x0b,0xfe,0x00,0x00]
+
+v_pk_max_i16 v5, v1, v2
+// GFX12: [0x05,0x40,0x07,0xcc,0x01,0x05,0x02,0x18]
+
+v_pk_max_i16 v5, v255, v255
+// GFX12: [0x05,0x40,0x07,0xcc,0xff,0xff,0x03,0x18]
+
+v_pk_max_i16 v5, s1, s2
+// GFX12: [0x05,0x40,0x07,0xcc,0x01,0x04,0x00,0x18]
+
+v_pk_max_i16 v5, s105, s105
+// GFX12: [0x05,0x40,0x07,0xcc,0x69,0xd2,0x00,0x18]
+
+v_pk_max_i16 v5, vcc_lo, ttmp15
+// GFX12: [0x05,0x40,0x07,0xcc,0x6a,0xf6,0x00,0x18]
+
+v_pk_max_i16 v5, vcc_hi, 0xfe0b
+// GFX12: [0x05,0x40,0x07,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+
+v_pk_max_i16 v5, ttmp15, src_scc
+// GFX12: [0x05,0x40,0x07,0xcc,0x7b,0xfa,0x01,0x18]
+
+v_pk_max_i16 v5, m0, 0.5
+// GFX12: [0x05,0x40,0x07,0xcc,0x7d,0xfe,0x01,0x18,0x00,0x38,0x00,0x00]
+
+v_pk_max_i16 v5, exec_lo, -1
+// GFX12: [0x05,0x40,0x07,0xcc,0x7e,0x82,0x01,0x18]
+
+v_pk_max_i16 v5, exec_hi, null
+// GFX12: [0x05,0x40,0x07,0xcc,0x7f,0xf8,0x00,0x18]
+
+v_pk_max_i16 v5, null, exec_lo
+// GFX12: [0x05,0x40,0x07,0xcc,0x7c,0xfc,0x00,0x18]
+
+v_pk_max_i16 v5, -1, exec_hi op_sel:[1,1] op_sel_hi:[0,0]
+// GFX12: [0x05,0x58,0x07,0xcc,0xc1,0xfe,0x00,0x00]
+
+v_pk_max_i16 v5, 0.5, m0 op_sel:[0,0] op_sel_hi:[1,1]
+// GFX12: [0x05,0x40,0x07,0xcc,0xff,0xfa,0x00,0x18,0x00,0x38,0x00,0x00]
+
+v_pk_max_i16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1]
+// GFX12: [0x05,0x48,0x07,0xcc,0xfd,0xd4,0x00,0x10]
+
+v_pk_max_i16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0]
+// GFX12: [0xff,0x50,0x07,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00]
+
+v_pk_max_u16 v5, v1, v2
+// GFX12: [0x05,0x40,0x0c,0xcc,0x01,0x05,0x02,0x18]
+
+v_pk_max_u16 v5, v255, v255
+// GFX12: [0x05,0x40,0x0c,0xcc,0xff,0xff,0x03,0x18]
+
+v_pk_max_u16 v5, s1, s2
+// GFX12: [0x05,0x40,0x0c,0xcc,0x01,0x04,0x00,0x18]
+
+v_pk_max_u16 v5, s105, s105
+// GFX12: [0x05,0x40,0x0c,0xcc,0x69,0xd2,0x00,0x18]
+
+v_pk_max_u16 v5, vcc_lo, ttmp15
+// GFX12: [0x05,0x40,0x0c,0xcc,0x6a,0xf6,0x00,0x18]
+
+v_pk_max_u16 v5, vcc_hi, 0xfe0b
+// GFX12: [0x05,0x40,0x0c,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+
+v_pk_max_u16 v5, ttmp15, src_scc
+// GFX12: [0x05,0x40,0x0c,0xcc,0x7b,0xfa,0x01,0x18]
+
+v_pk_max_u16 v5, m0, 0.5
+// GFX12: [0x05,0x40,0x0c,0xcc,0x7d,0xfe,0x01,0x18,0x00,0x38,0x00,0x00]
+
+v_pk_max_u16 v5, exec_lo, -1
+// GFX12: [0x05,0x40,0x0c,0xcc,0x7e,0x82,0x01,0x18]
+
+v_pk_max_u16 v5, exec_hi, null
+// GFX12: [0x05,0x40,0x0c,0xcc,0x7f,0xf8,0x00,0x18]
+
+v_pk_max_u16 v5, null, exec_lo
+// GFX12: [0x05,0x40,0x0c,0xcc,0x7c,0xfc,0x00,0x18]
+
+v_pk_max_u16 v5, -1, exec_hi op_sel:[1,1] op_sel_hi:[0,0]
+// GFX12: [0x05,0x58,0x0c,0xcc,0xc1,0xfe,0x00,0x00]
+
+v_pk_max_u16 v5, 0.5, m0 op_sel:[0,0] op_sel_hi:[1,1]
+// GFX12: [0x05,0x40,0x0c,0xcc,0xff,0xfa,0x00,0x18,0x00,0x38,0x00,0x00]
+
+v_pk_max_u16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1]
+// GFX12: [0x05,0x48,0x0c,0xcc,0xfd,0xd4,0x00,0x10]
+
+v_pk_max_u16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0]
+// GFX12: [0xff,0x50,0x0c,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00]
+
+v_pk_min_num_f16 v5, v1, v2
+// GFX12: [0x05,0x40,0x1b,0xcc,0x01,0x05,0x02,0x18]
+
+v_pk_min_num_f16 v5, v255, v255
+// GFX12: [0x05,0x40,0x1b,0xcc,0xff,0xff,0x03,0x18]
+
+v_pk_min_num_f16 v5, s1, s2
+// GFX12: [0x05,0x40,0x1b,0xcc,0x01,0x04,0x00,0x18]
+
+v_pk_min_num_f16 v5, s105, s105
+// GFX12: [0x05,0x40,0x1b,0xcc,0x69,0xd2,0x00,0x18]
+
+v_pk_min_num_f16 v5, vcc_lo, ttmp15
+// GFX12: [0x05,0x40,0x1b,0xcc,0x6a,0xf6,0x00,0x18]
+
+v_pk_min_num_f16 v5, vcc_hi, 0xfe0b
+// GFX12: [0x05,0x40,0x1b,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+
+v_pk_min_num_f16 v5, ttmp15, src_scc
+// GFX12: [0x05,0x40,0x1b,0xcc,0x7b,0xfa,0x01,0x18]
+
+v_pk_min_num_f16 v5, m0, 0.5
+// GFX12: [0x05,0x40,0x1b,0xcc,0x7d,0xe0,0x01,0x18]
+
+v_pk_min_num_f16 v5, exec_lo, -1
+// GFX12: [0x05,0x40,0x1b,0xcc,0x7e,0x82,0x01,0x18]
+
+v_pk_min_num_f16 v5, exec_hi, null
+// GFX12: [0x05,0x40,0x1b,0xcc,0x7f,0xf8,0x00,0x18]
+
+v_pk_min_num_f16 v5, null, exec_lo
+// GFX12: [0x05,0x40,0x1b,0xcc,0x7c,0xfc,0x00,0x18]
+
+v_pk_min_num_f16 v5, -1, exec_hi op_sel:[1,1] op_sel_hi:[0,0] neg_lo:[1,0] neg_hi:[1,0]
+// GFX12: [0x05,0x59,0x1b,0xcc,0xc1,0xfe,0x00,0x20]
+
+v_pk_min_num_f16 v5, 0.5, m0 op_sel:[0,0] op_sel_hi:[1,1] neg_lo:[0,1] neg_hi:[0,1]
+// GFX12: [0x05,0x42,0x1b,0xcc,0xf0,0xfa,0x00,0x58]
+
+v_pk_min_num_f16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1] neg_lo:[0,0] neg_hi:[0,0]
+// GFX12: [0x05,0x48,0x1b,0xcc,0xfd,0xd4,0x00,0x10]
+
+v_pk_min_num_f16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] neg_lo:[1,1] neg_hi:[1,1] clamp
+// GFX12: [0xff,0xd3,0x1b,0xcc,0xff,0xd6,0x00,0x68,0x0b,0xfe,0x00,0x00]
+
+v_pk_min_i16 v5, v1, v2
+// GFX12: [0x05,0x40,0x08,0xcc,0x01,0x05,0x02,0x18]
+
+v_pk_min_i16 v5, v255, v255
+// GFX12: [0x05,0x40,0x08,0xcc,0xff,0xff,0x03,0x18]
+
+v_pk_min_i16 v5, s1, s2
+// GFX12: [0x05,0x40,0x08,0xcc,0x01,0x04,0x00,0x18]
+
+v_pk_min_i16 v5, s105, s105
+// GFX12: [0x05,0x40,0x08,0xcc,0x69,0xd2,0x00,0x18]
+
+v_pk_min_i16 v5, vcc_lo, ttmp15
+// GFX12: [0x05,0x40,0x08,0xcc,0x6a,0xf6,0x00,0x18]
+
+v_pk_min_i16 v5, vcc_hi, 0xfe0b
+// GFX12: [0x05,0x40,0x08,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+
+v_pk_min_i16 v5, ttmp15, src_scc
+// GFX12: [0x05,0x40,0x08,0xcc,0x7b,0xfa,0x01,0x18]
+
+v_pk_min_i16 v5, m0, 0.5
+// GFX12: [0x05,0x40,0x08,0xcc,0x7d,0xfe,0x01,0x18,0x00,0x38,0x00,0x00]
+
+v_pk_min_i16 v5, exec_lo, -1
+// GFX12: [0x05,0x40,0x08,0xcc,0x7e,0x82,0x01,0x18]
+
+v_pk_min_i16 v5, exec_hi, null
+// GFX12: [0x05,0x40,0x08,0xcc,0x7f,0xf8,0x00,0x18]
+
+v_pk_min_i16 v5, null, exec_lo
+// GFX12: [0x05,0x40,0x08,0xcc,0x7c,0xfc,0x00,0x18]
+
+v_pk_min_i16 v5, -1, exec_hi op_sel:[1,1] op_sel_hi:[0,0]
+// GFX12: [0x05,0x58,0x08,0xcc,0xc1,0xfe,0x00,0x00]
+
+v_pk_min_i16 v5, 0.5, m0 op_sel:[0,0] op_sel_hi:[1,1]
+// GFX12: [0x05,0x40,0x08,0xcc,0xff,0xfa,0x00,0x18,0x00,0x38,0x00,0x00]
+
+v_pk_min_i16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1]
+// GFX12: [0x05,0x48,0x08,0xcc,0xfd,0xd4,0x00,0x10]
+
+v_pk_min_i16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0]
+// GFX12: [0xff,0x50,0x08,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00]
+
+v_pk_min_u16 v5, v1, v2
+// GFX12: [0x05,0x40,0x0d,0xcc,0x01,0x05,0x02,0x18]
+
+v_pk_min_u16 v5, v255, v255
+// GFX12: [0x05,0x40,0x0d,0xcc,0xff,0xff,0x03,0x18]
+
+v_pk_min_u16 v5, s1, s2
+// GFX12: [0x05,0x40,0x0d,0xcc,0x01,0x04,0x00,0x18]
+
+v_pk_min_u16 v5, s105, s105
+// GFX12: [0x05,0x40,0x0d,0xcc,0x69,0xd2,0x00,0x18]
+
+v_pk_min_u16 v5, vcc_lo, ttmp15
+// GFX12: [0x05,0x40,0x0d,0xcc,0x6a,0xf6,0x00,0x18]
+
+v_pk_min_u16 v5, vcc_hi, 0xfe0b
+// GFX12: [0x05,0x40,0x0d,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+
+v_pk_min_u16 v5, ttmp15, src_scc
+// GFX12: [0x05,0x40,0x0d,0xcc,0x7b,0xfa,0x01,0x18]
+
+v_pk_min_u16 v5, m0, 0.5
+// GFX12: [0x05,0x40,0x0d,0xcc,0x7d,0xfe,0x01,0x18,0x00,0x38,0x00,0x00]
+
+v_pk_min_u16 v5, exec_lo, -1
+// GFX12: [0x05,0x40,0x0d,0xcc,0x7e,0x82,0x01,0x18]
+
+v_pk_min_u16 v5, exec_hi, null
+// GFX12: [0x05,0x40,0x0d,0xcc,0x7f,0xf8,0x00,0x18]
+
+v_pk_min_u16 v5, null, exec_lo
+// GFX12: [0x05,0x40,0x0d,0xcc,0x7c,0xfc,0x00,0x18]
+
+v_pk_min_u16 v5, -1, exec_hi op_sel:[1,1] op_sel_hi:[0,0]
+// GFX12: [0x05,0x58,0x0d,0xcc,0xc1,0xfe,0x00,0x00]
+
+v_pk_min_u16 v5, 0.5, m0 op_sel:[0,0] op_sel_hi:[1,1]
+// GFX12: [0x05,0x40,0x0d,0xcc,0xff,0xfa,0x00,0x18,0x00,0x38,0x00,0x00]
+
+v_pk_min_u16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1]
+// GFX12: [0x05,0x48,0x0d,0xcc,0xfd,0xd4,0x00,0x10]
+
+v_pk_min_u16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0]
+// GFX12: [0xff,0x50,0x0d,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00]
+
+v_pk_mul_f16 v5, v1, v2
+// GFX12: [0x05,0x40,0x10,0xcc,0x01,0x05,0x02,0x18]
+
+v_pk_mul_f16 v5, v255, v255
+// GFX12: [0x05,0x40,0x10,0xcc,0xff,0xff,0x03,0x18]
+
+v_pk_mul_f16 v5, s1, s2
+// GFX12: [0x05,0x40,0x10,0xcc,0x01,0x04,0x00,0x18]
+
+v_pk_mul_f16 v5, s105, s105
+// GFX12: [0x05,0x40,0x10,0xcc,0x69,0xd2,0x00,0x18]
+
+v_pk_mul_f16 v5, vcc_lo, ttmp15
+// GFX12: [0x05,0x40,0x10,0xcc,0x6a,0xf6,0x00,0x18]
+
+v_pk_mul_f16 v5, vcc_hi, 0xfe0b
+// GFX12: [0x05,0x40,0x10,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+
+v_pk_mul_f16 v5, ttmp15, src_scc
+// GFX12: [0x05,0x40,0x10,0xcc,0x7b,0xfa,0x01,0x18]
+
+v_pk_mul_f16 v5, m0, 0.5
+// GFX12: [0x05,0x40,0x10,0xcc,0x7d,0xe0,0x01,0x18]
+
+v_pk_mul_f16 v5, exec_lo, -1
+// GFX12: [0x05,0x40,0x10,0xcc,0x7e,0x82,0x01,0x18]
+
+v_pk_mul_f16 v5, exec_hi, null
+// GFX12: [0x05,0x40,0x10,0xcc,0x7f,0xf8,0x00,0x18]
+
+v_pk_mul_f16 v5, null, exec_lo
+// GFX12: [0x05,0x40,0x10,0xcc,0x7c,0xfc,0x00,0x18]
+
+v_pk_mul_f16 v5, -1, exec_hi op_sel:[1,1] op_sel_hi:[0,0] neg_lo:[1,0] neg_hi:[1,0]
+// GFX12: [0x05,0x59,0x10,0xcc,0xc1,0xfe,0x00,0x20]
+
+v_pk_mul_f16 v5, 0.5, m0 op_sel:[0,0] op_sel_hi:[1,1] neg_lo:[0,1] neg_hi:[0,1]
+// GFX12: [0x05,0x42,0x10,0xcc,0xf0,0xfa,0x00,0x58]
+
+v_pk_mul_f16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1] neg_lo:[0,0] neg_hi:[0,0]
+// GFX12: [0x05,0x48,0x10,0xcc,0xfd,0xd4,0x00,0x10]
+
+v_pk_mul_f16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] neg_lo:[1,1] neg_hi:[1,1] clamp
+// GFX12: [0xff,0xd3,0x10,0xcc,0xff,0xd6,0x00,0x68,0x0b,0xfe,0x00,0x00]
+
+v_pk_mul_lo_u16 v5, v1, v2
+// GFX12: [0x05,0x40,0x01,0xcc,0x01,0x05,0x02,0x18]
+
+v_pk_mul_lo_u16 v5, v255, v255
+// GFX12: [0x05,0x40,0x01,0xcc,0xff,0xff,0x03,0x18]
+
+v_pk_mul_lo_u16 v5, s1, s2
+// GFX12: [0x05,0x40,0x01,0xcc,0x01,0x04,0x00,0x18]
+
+v_pk_mul_lo_u16 v5, s105, s105
+// GFX12: [0x05,0x40,0x01,0xcc,0x69,0xd2,0x00,0x18]
+
+v_pk_mul_lo_u16 v5, vcc_lo, ttmp15
+// GFX12: [0x05,0x40,0x01,0xcc,0x6a,0xf6,0x00,0x18]
+
+v_pk_mul_lo_u16 v5, vcc_hi, 0xfe0b
+// GFX12: [0x05,0x40,0x01,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+
+v_pk_mul_lo_u16 v5, ttmp15, src_scc
+// GFX12: [0x05,0x40,0x01,0xcc,0x7b,0xfa,0x01,0x18]
+
+v_pk_mul_lo_u16 v5, m0, 0.5
+// GFX12: [0x05,0x40,0x01,0xcc,0x7d,0xfe,0x01,0x18,0x00,0x38,0x00,0x00]
+
+v_pk_mul_lo_u16 v5, exec_lo, -1
+// GFX12: [0x05,0x40,0x01,0xcc,0x7e,0x82,0x01,0x18]
+
+v_pk_mul_lo_u16 v5, exec_hi, null
+// GFX12: [0x05,0x40,0x01,0xcc,0x7f,0xf8,0x00,0x18]
+
+v_pk_mul_lo_u16 v5, null, exec_lo
+// GFX12: [0x05,0x40,0x01,0xcc,0x7c,0xfc,0x00,0x18]
+
+v_pk_mul_lo_u16 v5, -1, exec_hi op_sel:[1,1] op_sel_hi:[0,0]
+// GFX12: [0x05,0x58,0x01,0xcc,0xc1,0xfe,0x00,0x00]
+
+v_pk_mul_lo_u16 v5, 0.5, m0 op_sel:[0,0] op_sel_hi:[1,1]
+// GFX12: [0x05,0x40,0x01,0xcc,0xff,0xfa,0x00,0x18,0x00,0x38,0x00,0x00]
+
+v_pk_mul_lo_u16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1]
+// GFX12: [0x05,0x48,0x01,0xcc,0xfd,0xd4,0x00,0x10]
+
+v_pk_mul_lo_u16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0]
+// GFX12: [0xff,0x50,0x01,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00]
+
+v_pk_sub_i16 v5, v1, v2
+// GFX12: [0x05,0x40,0x03,0xcc,0x01,0x05,0x02,0x18]
+
+v_pk_sub_i16 v5, v255, v255
+// GFX12: [0x05,0x40,0x03,0xcc,0xff,0xff,0x03,0x18]
+
+v_pk_sub_i16 v5, s1, s2
+// GFX12: [0x05,0x40,0x03,0xcc,0x01,0x04,0x00,0x18]
+
+v_pk_sub_i16 v5, s105, s105
+// GFX12: [0x05,0x40,0x03,0xcc,0x69,0xd2,0x00,0x18]
+
+v_pk_sub_i16 v5, vcc_lo, ttmp15
+// GFX12: [0x05,0x40,0x03,0xcc,0x6a,0xf6,0x00,0x18]
+
+v_pk_sub_i16 v5, vcc_hi, 0xfe0b
+// GFX12: [0x05,0x40,0x03,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+
+v_pk_sub_i16 v5, ttmp15, src_scc
+// GFX12: [0x05,0x40,0x03,0xcc,0x7b,0xfa,0x01,0x18]
+
+v_pk_sub_i16 v5, m0, 0.5
+// GFX12: [0x05,0x40,0x03,0xcc,0x7d,0xfe,0x01,0x18,0x00,0x38,0x00,0x00]
+
+v_pk_sub_i16 v5, exec_lo, -1
+// GFX12: [0x05,0x40,0x03,0xcc,0x7e,0x82,0x01,0x18]
+
+v_pk_sub_i16 v5, exec_hi, null
+// GFX12: [0x05,0x40,0x03,0xcc,0x7f,0xf8,0x00,0x18]
+
+v_pk_sub_i16 v5, null, exec_lo
+// GFX12: [0x05,0x40,0x03,0xcc,0x7c,0xfc,0x00,0x18]
+
+v_pk_sub_i16 v5, -1, exec_hi op_sel:[1,1] op_sel_hi:[0,0]
+// GFX12: [0x05,0x58,0x03,0xcc,0xc1,0xfe,0x00,0x00]
+
+v_pk_sub_i16 v5, 0.5, m0 op_sel:[0,0] op_sel_hi:[1,1]
+// GFX12: [0x05,0x40,0x03,0xcc,0xff,0xfa,0x00,0x18,0x00,0x38,0x00,0x00]
+
+v_pk_sub_i16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1]
+// GFX12: [0x05,0x48,0x03,0xcc,0xfd,0xd4,0x00,0x10]
+
+v_pk_sub_i16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] clamp
+// GFX12: [0xff,0xd0,0x03,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00]
+
+v_pk_sub_u16 v5, v1, v2
+// GFX12: [0x05,0x40,0x0b,0xcc,0x01,0x05,0x02,0x18]
+
+v_pk_sub_u16 v5, v255, v255
+// GFX12: [0x05,0x40,0x0b,0xcc,0xff,0xff,0x03,0x18]
+
+v_pk_sub_u16 v5, s1, s2
+// GFX12: [0x05,0x40,0x0b,0xcc,0x01,0x04,0x00,0x18]
+
+v_pk_sub_u16 v5, s105, s105
+// GFX12: [0x05,0x40,0x0b,0xcc,0x69,0xd2,0x00,0x18]
+
+v_pk_sub_u16 v5, vcc_lo, ttmp15
+// GFX12: [0x05,0x40,0x0b,0xcc,0x6a,0xf6,0x00,0x18]
+
+v_pk_sub_u16 v5, vcc_hi, 0xfe0b
+// GFX12: [0x05,0x40,0x0b,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+
+v_pk_sub_u16 v5, ttmp15, src_scc
+// GFX12: [0x05,0x40,0x0b,0xcc,0x7b,0xfa,0x01,0x18]
+
+v_pk_sub_u16 v5, m0, 0.5
+// GFX12: [0x05,0x40,0x0b,0xcc,0x7d,0xfe,0x01,0x18,0x00,0x38,0x00,0x00]
+
+v_pk_sub_u16 v5, exec_lo, -1
+// GFX12: [0x05,0x40,0x0b,0xcc,0x7e,0x82,0x01,0x18]
+
+v_pk_sub_u16 v5, exec_hi, null
+// GFX12: [0x05,0x40,0x0b,0xcc,0x7f,0xf8,0x00,0x18]
+
+v_pk_sub_u16 v5, null, exec_lo
+// GFX12: [0x05,0x40,0x0b,0xcc,0x7c,0xfc,0x00,0x18]
+
+v_pk_sub_u16 v5, -1, exec_hi op_sel:[1,1] op_sel_hi:[0,0]
+// GFX12: [0x05,0x58,0x0b,0xcc,0xc1,0xfe,0x00,0x00]
+
+v_pk_sub_u16 v5, 0.5, m0 op_sel:[0,0] op_sel_hi:[1,1]
+// GFX12: [0x05,0x40,0x0b,0xcc,0xff,0xfa,0x00,0x18,0x00,0x38,0x00,0x00]
+
+v_pk_sub_u16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1]
+// GFX12: [0x05,0x48,0x0b,0xcc,0xfd,0xd4,0x00,0x10]
+
+v_pk_sub_u16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] clamp
+// GFX12: [0xff,0xd0,0x0b,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3p_aliases.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3p_aliases.s
new file mode 100644
index 000000000000..eca35691af50
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3p_aliases.s
@@ -0,0 +1,7 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
+
+v_pk_min_f16 v0, v1, v2
+// GFX12: v_pk_min_num_f16 v0, v1, v2             ; encoding: [0x00,0x40,0x1b,0xcc,0x01,0x05,0x02,0x18]
+
+v_pk_max_f16 v0, v1, v2
+// GFX12: v_pk_max_num_f16 v0, v1, v2             ; encoding: [0x00,0x40,0x1c,0xcc,0x01,0x05,0x02,0x18]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3p_dpp16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3p_dpp16.s
new file mode 100644
index 000000000000..3b4bbff1efeb
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3p_dpp16.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
+
+v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[0,0,0] neg_hi:[0,0,0] quad_perm:[2,2,3,1] bound_ctrl:0 fi:1
+// GFX12: v_dot2_f32_f16_e64_dpp v0, v1, v2, v3 quad_perm:[2,2,3,1] row_mask:0xf bank_mask:0xf fi:1 ; encoding: [0x00,0x00,0x13,0xcc,0xfa,0x04,0x0e,0x04,0x01,0x7a,0x04,0xff]
+
+v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[1,1,0] neg_hi:[1,0,1] quad_perm:[3,2,1,0] bank_mask:0xe
+// GFX12: v_dot2_f32_f16_e64_dpp v0, v1, v2, v3 neg_lo:[1,1,0] neg_hi:[1,0,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xe ; encoding: [0x00,0x05,0x13,0xcc,0xfa,0x04,0x0e,0x64,0x01,0x1b,0x00,0xfe]
+
+v_fma_mix_f32 v0, v1, v2, v3 op_sel:[0,0,0] row_ror:7 bank_mask:0x1 bound_ctrl:0
+// GFX12: v_fma_mix_f32_e64_dpp v0, v1, v2, v3 row_ror:7 row_mask:0xf bank_mask:0x1 ; encoding: [0x00,0x00,0x20,0xcc,0xfa,0x04,0x0e,0x04,0x01,0x27,0x01,0xf1]
+
+v_fma_mixhi_f16 v0, v1, v2, v3 op_sel_hi:[1,1,1] clamp quad_perm:[0,2,3,1] row_mask:0x0
+// GFX12: v_fma_mixhi_f16_e64_dpp v0, v1, v2, v3 op_sel_hi:[1,1,1] clamp quad_perm:[0,2,3,1] row_mask:0x0 bank_mask:0xf ; encoding: [0x00,0xc0,0x22,0xcc,0xfa,0x04,0x0e,0x1c,0x01,0x78,0x00,0x0f]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3p_dpp8.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3p_dpp8.s
new file mode 100644
index 000000000000..71eea18bc13d
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3p_dpp8.s
@@ -0,0 +1,18 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
+
+v_fma_mix_f32 v0, v1, v2, v3 dpp8:[2,2,2,2,4,4,4,4]
+// GFX12: encoding: [0x00,0x00,0x20,0xcc,0xe9,0x04,0x0e,0x04,0x01,0x92,0x44,0x92]
+
+v_fma_mix_f32 v0, v1, v2, v3 clamp dpp8:[2,2,2,2,4,4,4,4] fi:1
+// GFX12: encoding: [0x00,0x80,0x20,0xcc,0xea,0x04,0x0e,0x04,0x01,0x92,0x44,0x92]
+
+v_fma_mixlo_f16 v0, abs(v1), -v2, abs(v3) dpp8:[2,2,2,2,4,4,4,4]
+// GFX12: encoding: [0x00,0x05,0x21,0xcc,0xe9,0x04,0x0e,0x44,0x01,0x92,0x44,0x92]
+
+// For test purpose only. OP_SEL has to be set to all 0 and OP_SEL_HI has to be set to all 1
+v_fma_mixlo_f16 v0, abs(v1), -v2, abs(v3) op_sel:[1,0,0] op_sel_hi:[1,0,0] dpp8:[2,2,2,2,4,4,4,4]
+// GFX12: encoding: [0x00,0x0d,0x21,0xcc,0xe9,0x04,0x0e,0x4c,0x01,0x92,0x44,0x92]
+
+v_dot2_f32_f16_e64_dpp v0, v1, v2, v3 neg_lo:[0,1,1] neg_hi:[1,0,1] dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0x00,0x05,0x13,0xcc,0xe9,0x04,0x0e,0xc4,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3p_features.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3p_features.s
new file mode 100644
index 000000000000..f52dff263c63
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3p_features.s
@@ -0,0 +1,143 @@
+// RUN: llvm-mc -arch=amdgcn -show-encoding -mcpu=gfx1200 %s | FileCheck --check-prefix=GFX12 %s
+
+//
+// Test op_sel/op_sel_hi
+//
+
+v_pk_add_u16 v1, v2, v3
+// GFX12: encoding: [0x01,0x40,0x0a,0xcc,0x02,0x07,0x02,0x18]
+
+v_pk_add_u16 v1, v2, v3 op_sel:[0,0]
+// GFX12: v_pk_add_u16 v1, v2, v3 ; encoding: [0x01,0x40,0x0a,0xcc,0x02,0x07,0x02,0x18]
+
+v_pk_add_u16 v1, v2, v3 op_sel_hi:[1,1]
+// GFX12: v_pk_add_u16 v1, v2, v3 ; encoding: [0x01,0x40,0x0a,0xcc,0x02,0x07,0x02,0x18]
+
+v_pk_add_u16 v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,1]
+// GFX12: v_pk_add_u16 v1, v2, v3 ; encoding: [0x01,0x40,0x0a,0xcc,0x02,0x07,0x02,0x18]
+
+v_pk_add_u16 v1, v2, v3 op_sel_hi:[0,0]
+// GFX12: v_pk_add_u16 v1, v2, v3 op_sel_hi:[0,0] ; encoding: [0x01,0x40,0x0a,0xcc,0x02,0x07,0x02,0x00]
+
+v_pk_add_u16 v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,0]
+// GFX12: v_pk_add_u16 v1, v2, v3 op_sel_hi:[0,0] ; encoding: [0x01,0x40,0x0a,0xcc,0x02,0x07,0x02,0x00]
+
+v_pk_add_u16 v1, v2, v3 op_sel:[1,0]
+// GFX12: v_pk_add_u16 v1, v2, v3 op_sel:[1,0] ; encoding: [0x01,0x48,0x0a,0xcc,0x02,0x07,0x02,0x18]
+
+v_pk_add_u16 v1, v2, v3 op_sel:[0,1]
+// GFX12: v_pk_add_u16 v1, v2, v3 op_sel:[0,1] ; encoding: [0x01,0x50,0x0a,0xcc,0x02,0x07,0x02,0x18]
+
+v_pk_add_u16 v1, v2, v3 op_sel:[1,1]
+// GFX12: v_pk_add_u16 v1, v2, v3 op_sel:[1,1] ; encoding: [0x01,0x58,0x0a,0xcc,0x02,0x07,0x02,0x18]
+
+v_pk_add_u16 v1, v2, v3 op_sel_hi:[0,1]
+// GFX12: v_pk_add_u16 v1, v2, v3 op_sel_hi:[0,1] ; encoding: [0x01,0x40,0x0a,0xcc,0x02,0x07,0x02,0x10]
+
+v_pk_add_u16 v1, v2, v3 op_sel_hi:[1,0]
+// GFX12: v_pk_add_u16 v1, v2, v3 op_sel_hi:[1,0] ; encoding: [0x01,0x40,0x0a,0xcc,0x02,0x07,0x02,0x08]
+
+v_pk_add_u16 v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,1]
+// GFX12: v_pk_add_u16 v1, v2, v3 op_sel:[1,1] ; encoding: [0x01,0x58,0x0a,0xcc,0x02,0x07,0x02,0x18]
+
+v_pk_add_u16 v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,0]
+// GFX12: v_pk_add_u16 v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,0] ; encoding: [0x01,0x48,0x0a,0xcc,0x02,0x07,0x02,0x08]
+
+v_pk_add_u16 v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,1]
+// GFX12: v_pk_add_u16 v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,1] ; encoding: [0x01,0x50,0x0a,0xcc,0x02,0x07,0x02,0x10]
+
+v_pk_add_u16 v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,1]
+// GFX12: v_pk_add_u16 v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,1] ; encoding: [0x01,0x48,0x0a,0xcc,0x02,0x07,0x02,0x10]
+
+v_pk_add_u16 v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,0]
+// GFX12: v_pk_add_u16 v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,0] ; encoding: [0x01,0x50,0x0a,0xcc,0x02,0x07,0x02,0x08]
+
+//
+// Test src2 op_sel/op_sel_hi
+//
+
+v_pk_fma_f16 v8, v0, s0, v1
+// GFX12: encoding: [0x08,0x40,0x0e,0xcc,0x00,0x01,0x04,0x1c]
+
+v_pk_fma_f16 v8, v0, s0, v1 neg_lo:[0,0,0] neg_hi:[0,0,0]
+// GFX12: v_pk_fma_f16 v8, v0, s0, v1 ; encoding: [0x08,0x40,0x0e,0xcc,0x00,0x01,0x04,0x1c]
+
+v_pk_fma_f16 v8, v0, s0, v1 op_sel:[0,0,0] op_sel_hi:[1,1,1] neg_lo:[0,0,0] neg_hi:[0,0,0]
+// GFX12: v_pk_fma_f16 v8, v0, s0, v1 ; encoding: [0x08,0x40,0x0e,0xcc,0x00,0x01,0x04,0x1c]
+
+v_pk_fma_f16 v8, v0, s0, v1 op_sel:[0,0,0] op_sel_hi:[1,1,1]
+// GFX12: v_pk_fma_f16 v8, v0, s0, v1 ; encoding: [0x08,0x40,0x0e,0xcc,0x00,0x01,0x04,0x1c]
+
+v_pk_fma_f16 v8, v0, s0, v1 op_sel:[0,0,0] op_sel_hi:[0,0,0]
+// GFX12: v_pk_fma_f16 v8, v0, s0, v1 op_sel_hi:[0,0,0] ; encoding: [0x08,0x00,0x0e,0xcc,0x00,0x01,0x04,0x04]
+
+v_pk_fma_f16 v8, v0, s0, v1 op_sel:[0,0,1] op_sel_hi:[0,0,1]
+// GFX12: v_pk_fma_f16 v8, v0, s0, v1 op_sel:[0,0,1] op_sel_hi:[0,0,1] ; encoding: [0x08,0x60,0x0e,0xcc,0x00,0x01,0x04,0x04]
+
+//
+// Test neg_lo/neg_hi
+//
+
+v_pk_fma_f16 v8, v0, s0, v1 neg_lo:[1,1,1]
+// GFX12: v_pk_fma_f16 v8, v0, s0, v1 neg_lo:[1,1,1] ; encoding: [0x08,0x40,0x0e,0xcc,0x00,0x01,0x04,0xfc]
+
+v_pk_fma_f16 v8, v0, s0, v1 neg_hi:[1,1,1]
+// GFX12: v_pk_fma_f16 v8, v0, s0, v1 neg_hi:[1,1,1] ; encoding: [0x08,0x47,0x0e,0xcc,0x00,0x01,0x04,0x1c]
+
+v_pk_fma_f16 v8, v0, s0, v1 neg_lo:[1,1,1] neg_hi:[1,1,1]
+// GFX12: v_pk_fma_f16 v8, v0, s0, v1 neg_lo:[1,1,1] neg_hi:[1,1,1] ; encoding: [0x08,0x47,0x0e,0xcc,0x00,0x01,0x04,0xfc]
+
+v_pk_fma_f16 v8, v0, s0, v1 neg_lo:[1,0,0]
+// GFX12: v_pk_fma_f16 v8, v0, s0, v1 neg_lo:[1,0,0] ; encoding: [0x08,0x40,0x0e,0xcc,0x00,0x01,0x04,0x3c]
+
+v_pk_fma_f16 v8, v0, s0, v1 neg_lo:[0,1,0]
+// GFX12: v_pk_fma_f16 v8, v0, s0, v1 neg_lo:[0,1,0] ; encoding: [0x08,0x40,0x0e,0xcc,0x00,0x01,0x04,0x5c]
+
+v_pk_fma_f16 v8, v0, s0, v1 neg_lo:[0,0,1]
+// GFX12: v_pk_fma_f16 v8, v0, s0, v1 neg_lo:[0,0,1] ; encoding: [0x08,0x40,0x0e,0xcc,0x00,0x01,0x04,0x9c]
+
+v_pk_fma_f16 v8, v0, s0, v1 neg_hi:[1,0,0]
+// GFX12: v_pk_fma_f16 v8, v0, s0, v1 neg_hi:[1,0,0] ; encoding: [0x08,0x41,0x0e,0xcc,0x00,0x01,0x04,0x1c]
+
+v_pk_fma_f16 v8, v0, s0, v1 neg_hi:[0,1,0]
+// GFX12: v_pk_fma_f16 v8, v0, s0, v1 neg_hi:[0,1,0] ; encoding: [0x08,0x42,0x0e,0xcc,0x00,0x01,0x04,0x1c]
+
+v_pk_fma_f16 v8, v0, s0, v1 neg_hi:[0,0,1]
+// GFX12: v_pk_fma_f16 v8, v0, s0, v1 neg_hi:[0,0,1] ; encoding: [0x08,0x44,0x0e,0xcc,0x00,0x01,0x04,0x1c]
+
+//
+// DOT
+//
+
+v_dot4_i32_iu8 v3, v4, v5, v6
+// GFX12: v_dot4_i32_iu8 v3, v4, v5, v6                ; encoding: [0x03,0x40,0x16,0xcc,0x04,0x0b,0x1a,0x1c]
+
+v_dot4_i32_iu8 v3, v4, v5, 0xf neg_lo:[1,1]
+// GFX12: v_dot4_i32_iu8 v3, v4, v5, 15 neg_lo:[1,1,0] ; encoding: [0x03,0x40,0x16,0xcc,0x04,0x0b,0x3e,0x7a]
+
+v_dot4_u32_u8 v3, v4, v5, v6
+// GFX12: v_dot4_u32_u8 v3, v4, v5, v6            ; encoding: [0x03,0x40,0x17,0xcc,0x04,0x0b,0x1a,0x1c]
+
+v_dot4_i32_iu8 v3, v4, v5, 0xf
+// GFX12: v_dot4_i32_iu8 v3, v4, v5, 15                ; encoding: [0x03,0x40,0x16,0xcc,0x04,0x0b,0x3e,0x1a]
+
+v_dot8_i32_iu4 v3, v4, v5, 0xf neg_lo:[1,0]
+// GFX12: v_dot8_i32_iu4 v3, v4, v5, 15 neg_lo:[1,0,0] ; encoding: [0x03,0x40,0x18,0xcc,0x04,0x0b,0x3e,0x3a]
+
+v_dot8_i32_iu4 v3, v4, v5, v0 neg_lo:[0,0]
+// GFX12: v_dot8_i32_iu4 v3, v4, v5, v0                ; encoding: [0x03,0x40,0x18,0xcc,0x04,0x0b,0x02,0x1c]
+
+v_dot8_u32_u4 v0, v1, v2, v3
+// GFX12: v_dot8_u32_u4 v0, v1, v2, v3            ; encoding: [0x00,0x40,0x19,0xcc,0x01,0x05,0x0e,0x1c]
+
+v_dot2_f32_f16 v0, v1, v2, v3
+// GFX12: v_dot2_f32_f16 v0, v1, v2, v3                ; encoding: [0x00,0x40,0x13,0xcc,0x01,0x05,0x0e,0x1c]
+
+v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[1,1,0] neg_hi:[1,0,1]
+// GFX12: v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[1,1,0] neg_hi:[1,0,1] ; encoding: [0x00,0x45,0x13,0xcc,0x01,0x05,0x0e,0x7c]
+
+v_dot2_f32_bf16 v0, v1, v2, v3
+// GFX12: v_dot2_f32_bf16 v0, v1, v2, v3          ; encoding: [0x00,0x40,0x1a,0xcc,0x01,0x05,0x0e,0x1c]
+
+v_dot2_f32_bf16 v0, v1, v2, v3 neg_lo:[1,1,0] neg_hi:[1,0,1]
+// GFX12: v_dot2_f32_bf16 v0, v1, v2, v3 neg_lo:[1,1,0] neg_hi:[1,0,1] ; encoding: [0x00,0x45,0x1a,0xcc,0x01,0x05,0x0e,0x7c]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopc.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopc.s
new file mode 100644
index 000000000000..18d83ad7ef4a
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopc.s
@@ -0,0 +1,9076 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W32 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W64 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+
+v_cmp_class_f16_e32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0xfa,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, v127, v2
+// W32: encoding: [0x7f,0x05,0xfa,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0xfa,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0xfa,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0xfa,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0xfa,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0xfa,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0xfa,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0xfa,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0xfa,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0xfa,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0xfa,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0xfa,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0xfa,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, 0xfe0b, v127
+// W32: encoding: [0xff,0xfe,0xfa,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0xfa,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, v127, v2
+// W64: encoding: [0x7f,0x05,0xfa,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0xfa,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0xfa,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0xfa,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0xfa,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0xfa,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0xfa,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0xfa,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0xfa,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0xfa,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0xfa,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0xfa,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0xfa,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, 0xfe0b, v127
+// W64: encoding: [0xff,0xfe,0xfa,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0xfc,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0xfc,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0xfc,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0xfc,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0xfc,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0xfc,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0xfc,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0xfc,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0xfc,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0xfc,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0xfc,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0xfc,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0xfc,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0xfc,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, 0xaf123456, v255
+// W32: encoding: [0xff,0xfe,0xfd,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0xfc,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0xfc,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0xfc,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0xfc,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0xfc,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0xfc,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0xfc,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0xfc,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0xfc,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0xfc,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0xfc,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0xfc,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0xfc,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0xfc,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, 0xaf123456, v255
+// W64: encoding: [0xff,0xfe,0xfd,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc_lo, v[1:2], v2
+// W32: encoding: [0x01,0x05,0xfe,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc_lo, v[254:255], v2
+// W32: encoding: [0xfe,0x05,0xfe,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc_lo, s[2:3], v2
+// W32: encoding: [0x02,0x04,0xfe,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc_lo, s[104:105], v2
+// W32: encoding: [0x68,0x04,0xfe,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc_lo, vcc, v2
+// W32: encoding: [0x6a,0x04,0xfe,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc_lo, ttmp[14:15], v2
+// W32: encoding: [0x7a,0x04,0xfe,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc_lo, exec, v2
+// W32: encoding: [0x7e,0x04,0xfe,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0xfe,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0xfe,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0xfe,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0xfe,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc_lo, 0xaf123456, v255
+// W32: encoding: [0xff,0xfe,0xff,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc, v[1:2], v2
+// W64: encoding: [0x01,0x05,0xfe,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc, v[254:255], v2
+// W64: encoding: [0xfe,0x05,0xfe,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc, s[2:3], v2
+// W64: encoding: [0x02,0x04,0xfe,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc, s[104:105], v2
+// W64: encoding: [0x68,0x04,0xfe,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc, vcc, v2
+// W64: encoding: [0x6a,0x04,0xfe,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc, ttmp[14:15], v2
+// W64: encoding: [0x7a,0x04,0xfe,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc, exec, v2
+// W64: encoding: [0x7e,0x04,0xfe,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0xfe,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0xfe,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0xfe,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0xfe,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc, 0xaf123456, v255
+// W64: encoding: [0xff,0xfe,0xff,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v127, v2
+// W32: encoding: [0x7f,0x05,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, 0xfe0b, v127
+// W32: encoding: [0xff,0xfe,0x04,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v127, v2
+// W64: encoding: [0x7f,0x05,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, 0xfe0b, v127
+// W64: encoding: [0xff,0xfe,0x04,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x24,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x24,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x24,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x24,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x24,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x24,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x24,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x24,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x24,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x24,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x24,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x24,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x24,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x24,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, 0xaf123456, v255
+// W32: encoding: [0xff,0xfe,0x25,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x24,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x24,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x24,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x24,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x24,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x24,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x24,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x24,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x24,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x24,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x24,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x24,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x24,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x24,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, 0xaf123456, v255
+// W64: encoding: [0xff,0xfe,0x25,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x44,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x44,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x44,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc_lo, s[104:105], v[2:3]
+// W32: encoding: [0x68,0x04,0x44,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x44,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc_lo, ttmp[14:15], v[2:3]
+// W32: encoding: [0x7a,0x04,0x44,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x44,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc_lo, null, v[2:3]
+// W32: encoding: [0x7c,0x04,0x44,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x44,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x44,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc_lo, src_scc, v[2:3]
+// W32: encoding: [0xfd,0x04,0x44,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc_lo, 0xaf123456, v[254:255]
+// W32: encoding: [0xff,0xfc,0x45,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x44,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x44,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x44,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc, s[104:105], v[2:3]
+// W64: encoding: [0x68,0x04,0x44,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x44,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc, ttmp[14:15], v[2:3]
+// W64: encoding: [0x7a,0x04,0x44,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x44,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc, null, v[2:3]
+// W64: encoding: [0x7c,0x04,0x44,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x44,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x44,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc, src_scc, v[2:3]
+// W64: encoding: [0xfd,0x04,0x44,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc, 0xaf123456, v[254:255]
+// W64: encoding: [0xff,0xfc,0x45,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x64,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, v127, v2
+// W32: encoding: [0x7f,0x05,0x64,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x64,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x64,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x64,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x64,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x64,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x64,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x64,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x64,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x64,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x64,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, 0.5, v2
+// W32: encoding: [0xff,0x04,0x64,0x7c,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x64,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, 0xfe0b, v127
+// W32: encoding: [0xff,0xfe,0x64,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x64,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, v127, v2
+// W64: encoding: [0x7f,0x05,0x64,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x64,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x64,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x64,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x64,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x64,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x64,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x64,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x64,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x64,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x64,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, 0.5, v2
+// W64: encoding: [0xff,0x04,0x64,0x7c,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x64,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, 0xfe0b, v127
+// W64: encoding: [0xff,0xfe,0x64,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x84,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x84,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x84,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x84,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x84,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x84,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x84,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x84,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x84,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x84,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x84,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x84,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x84,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x84,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, 0xaf123456, v255
+// W32: encoding: [0xff,0xfe,0x85,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x84,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x84,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x84,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x84,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x84,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x84,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x84,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x84,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x84,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x84,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x84,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x84,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x84,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x84,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, 0xaf123456, v255
+// W64: encoding: [0xff,0xfe,0x85,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0xa4,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0xa4,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0xa4,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc_lo, s[104:105], v[2:3]
+// W32: encoding: [0x68,0x04,0xa4,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0xa4,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc_lo, ttmp[14:15], v[2:3]
+// W32: encoding: [0x7a,0x04,0xa4,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0xa4,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc_lo, null, v[2:3]
+// W32: encoding: [0x7c,0x04,0xa4,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0xa4,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0xa4,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc_lo, src_scc, v[2:3]
+// W32: encoding: [0xfd,0x04,0xa4,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc_lo, 0xaf123456, v[254:255]
+// W32: encoding: [0xff,0xfc,0xa5,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0xa4,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0xa4,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0xa4,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc, s[104:105], v[2:3]
+// W64: encoding: [0x68,0x04,0xa4,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0xa4,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc, ttmp[14:15], v[2:3]
+// W64: encoding: [0x7a,0x04,0xa4,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0xa4,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc, null, v[2:3]
+// W64: encoding: [0x7c,0x04,0xa4,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0xa4,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0xa4,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc, src_scc, v[2:3]
+// W64: encoding: [0xfd,0x04,0xa4,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc, 0xaf123456, v[254:255]
+// W64: encoding: [0xff,0xfc,0xa5,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x74,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, v127, v2
+// W32: encoding: [0x7f,0x05,0x74,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x74,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x74,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x74,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x74,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x74,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x74,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x74,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x74,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x74,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x74,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, 0.5, v2
+// W32: encoding: [0xff,0x04,0x74,0x7c,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x74,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, 0xfe0b, v127
+// W32: encoding: [0xff,0xfe,0x74,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x74,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, v127, v2
+// W64: encoding: [0x7f,0x05,0x74,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x74,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x74,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x74,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x74,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x74,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x74,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x74,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x74,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x74,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x74,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, 0.5, v2
+// W64: encoding: [0xff,0x04,0x74,0x7c,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x74,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, 0xfe0b, v127
+// W64: encoding: [0xff,0xfe,0x74,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x94,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x94,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x94,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x94,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x94,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x94,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x94,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x94,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x94,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x94,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x94,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x94,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x94,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x94,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, 0xaf123456, v255
+// W32: encoding: [0xff,0xfe,0x95,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x94,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x94,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x94,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x94,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x94,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x94,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x94,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x94,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x94,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x94,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x94,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x94,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x94,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x94,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, 0xaf123456, v255
+// W64: encoding: [0xff,0xfe,0x95,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0xb4,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0xb4,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0xb4,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc_lo, s[104:105], v[2:3]
+// W32: encoding: [0x68,0x04,0xb4,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0xb4,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc_lo, ttmp[14:15], v[2:3]
+// W32: encoding: [0x7a,0x04,0xb4,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0xb4,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc_lo, null, v[2:3]
+// W32: encoding: [0x7c,0x04,0xb4,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0xb4,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0xb4,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc_lo, src_scc, v[2:3]
+// W32: encoding: [0xfd,0x04,0xb4,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc_lo, 0xaf123456, v[254:255]
+// W32: encoding: [0xff,0xfc,0xb5,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0xb4,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0xb4,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0xb4,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc, s[104:105], v[2:3]
+// W64: encoding: [0x68,0x04,0xb4,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0xb4,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc, ttmp[14:15], v[2:3]
+// W64: encoding: [0x7a,0x04,0xb4,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0xb4,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc, null, v[2:3]
+// W64: encoding: [0x7c,0x04,0xb4,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0xb4,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0xb4,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc, src_scc, v[2:3]
+// W64: encoding: [0xfd,0x04,0xb4,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc, 0xaf123456, v[254:255]
+// W64: encoding: [0xff,0xfc,0xb5,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x0c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, v127, v2
+// W32: encoding: [0x7f,0x05,0x0c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x0c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x0c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x0c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x0c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x0c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x0c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x0c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x0c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x0c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x0c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x0c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x0c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, 0xfe0b, v127
+// W32: encoding: [0xff,0xfe,0x0c,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x0c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, v127, v2
+// W64: encoding: [0x7f,0x05,0x0c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x0c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x0c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x0c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x0c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x0c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x0c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x0c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x0c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x0c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x0c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x0c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x0c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, 0xfe0b, v127
+// W64: encoding: [0xff,0xfe,0x0c,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x2c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x2c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x2c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x2c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x2c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x2c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x2c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x2c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x2c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x2c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x2c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x2c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x2c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x2c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, 0xaf123456, v255
+// W32: encoding: [0xff,0xfe,0x2d,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x2c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x2c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x2c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x2c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x2c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x2c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x2c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x2c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x2c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x2c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x2c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x2c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x2c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x2c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, 0xaf123456, v255
+// W64: encoding: [0xff,0xfe,0x2d,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x4c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x4c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x4c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc_lo, s[104:105], v[2:3]
+// W32: encoding: [0x68,0x04,0x4c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x4c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc_lo, ttmp[14:15], v[2:3]
+// W32: encoding: [0x7a,0x04,0x4c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x4c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc_lo, null, v[2:3]
+// W32: encoding: [0x7c,0x04,0x4c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x4c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x4c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc_lo, src_scc, v[2:3]
+// W32: encoding: [0xfd,0x04,0x4c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc_lo, 0xaf123456, v[254:255]
+// W32: encoding: [0xff,0xfc,0x4d,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x4c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x4c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x4c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc, s[104:105], v[2:3]
+// W64: encoding: [0x68,0x04,0x4c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x4c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc, ttmp[14:15], v[2:3]
+// W64: encoding: [0x7a,0x04,0x4c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x4c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc, null, v[2:3]
+// W64: encoding: [0x7c,0x04,0x4c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x4c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x4c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc, src_scc, v[2:3]
+// W64: encoding: [0xfd,0x04,0x4c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc, 0xaf123456, v[254:255]
+// W64: encoding: [0xff,0xfc,0x4d,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x6c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, v127, v2
+// W32: encoding: [0x7f,0x05,0x6c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x6c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x6c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x6c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x6c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x6c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x6c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x6c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x6c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x6c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x6c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, 0.5, v2
+// W32: encoding: [0xff,0x04,0x6c,0x7c,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x6c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, 0xfe0b, v127
+// W32: encoding: [0xff,0xfe,0x6c,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x6c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, v127, v2
+// W64: encoding: [0x7f,0x05,0x6c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x6c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x6c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x6c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x6c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x6c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x6c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x6c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x6c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x6c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x6c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, 0.5, v2
+// W64: encoding: [0xff,0x04,0x6c,0x7c,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x6c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, 0xfe0b, v127
+// W64: encoding: [0xff,0xfe,0x6c,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x8c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x8c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x8c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x8c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x8c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x8c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x8c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x8c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x8c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x8c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x8c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x8c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x8c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x8c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, 0xaf123456, v255
+// W32: encoding: [0xff,0xfe,0x8d,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x8c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x8c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x8c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x8c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x8c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x8c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x8c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x8c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x8c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x8c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x8c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x8c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x8c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x8c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, 0xaf123456, v255
+// W64: encoding: [0xff,0xfe,0x8d,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0xac,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0xac,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0xac,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc_lo, s[104:105], v[2:3]
+// W32: encoding: [0x68,0x04,0xac,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0xac,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc_lo, ttmp[14:15], v[2:3]
+// W32: encoding: [0x7a,0x04,0xac,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0xac,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc_lo, null, v[2:3]
+// W32: encoding: [0x7c,0x04,0xac,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0xac,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0xac,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc_lo, src_scc, v[2:3]
+// W32: encoding: [0xfd,0x04,0xac,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc_lo, 0xaf123456, v[254:255]
+// W32: encoding: [0xff,0xfc,0xad,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0xac,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0xac,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0xac,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc, s[104:105], v[2:3]
+// W64: encoding: [0x68,0x04,0xac,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0xac,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc, ttmp[14:15], v[2:3]
+// W64: encoding: [0x7a,0x04,0xac,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0xac,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc, null, v[2:3]
+// W64: encoding: [0x7c,0x04,0xac,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0xac,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0xac,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc, src_scc, v[2:3]
+// W64: encoding: [0xfd,0x04,0xac,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc, 0xaf123456, v[254:255]
+// W64: encoding: [0xff,0xfc,0xad,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x7c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, v127, v2
+// W32: encoding: [0x7f,0x05,0x7c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x7c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x7c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x7c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x7c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x7c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x7c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x7c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x7c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x7c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x7c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, 0.5, v2
+// W32: encoding: [0xff,0x04,0x7c,0x7c,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x7c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, 0xfe0b, v127
+// W32: encoding: [0xff,0xfe,0x7c,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x7c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, v127, v2
+// W64: encoding: [0x7f,0x05,0x7c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x7c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x7c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x7c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x7c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x7c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x7c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x7c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x7c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x7c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x7c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, 0.5, v2
+// W64: encoding: [0xff,0x04,0x7c,0x7c,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x7c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, 0xfe0b, v127
+// W64: encoding: [0xff,0xfe,0x7c,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x9c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x9c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x9c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x9c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x9c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x9c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x9c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x9c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x9c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x9c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x9c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x9c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x9c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x9c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, 0xaf123456, v255
+// W32: encoding: [0xff,0xfe,0x9d,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x9c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x9c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x9c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x9c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x9c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x9c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x9c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x9c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x9c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x9c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x9c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x9c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x9c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x9c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, 0xaf123456, v255
+// W64: encoding: [0xff,0xfe,0x9d,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0xbc,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0xbc,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0xbc,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc_lo, s[104:105], v[2:3]
+// W32: encoding: [0x68,0x04,0xbc,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0xbc,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc_lo, ttmp[14:15], v[2:3]
+// W32: encoding: [0x7a,0x04,0xbc,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0xbc,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc_lo, null, v[2:3]
+// W32: encoding: [0x7c,0x04,0xbc,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0xbc,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0xbc,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc_lo, src_scc, v[2:3]
+// W32: encoding: [0xfd,0x04,0xbc,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc_lo, 0xaf123456, v[254:255]
+// W32: encoding: [0xff,0xfc,0xbd,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0xbc,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0xbc,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0xbc,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc, s[104:105], v[2:3]
+// W64: encoding: [0x68,0x04,0xbc,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0xbc,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc, ttmp[14:15], v[2:3]
+// W64: encoding: [0x7a,0x04,0xbc,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0xbc,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc, null, v[2:3]
+// W64: encoding: [0x7c,0x04,0xbc,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0xbc,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0xbc,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc, src_scc, v[2:3]
+// W64: encoding: [0xfd,0x04,0xbc,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc, 0xaf123456, v[254:255]
+// W64: encoding: [0xff,0xfc,0xbd,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x08,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, v127, v2
+// W32: encoding: [0x7f,0x05,0x08,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x08,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x08,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x08,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x08,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x08,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x08,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x08,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x08,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x08,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x08,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x08,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x08,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, 0xfe0b, v127
+// W32: encoding: [0xff,0xfe,0x08,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x08,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, v127, v2
+// W64: encoding: [0x7f,0x05,0x08,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x08,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x08,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x08,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x08,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x08,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x08,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x08,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x08,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x08,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x08,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x08,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x08,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, 0xfe0b, v127
+// W64: encoding: [0xff,0xfe,0x08,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x28,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x28,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x28,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x28,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x28,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x28,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x28,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x28,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x28,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x28,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x28,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x28,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x28,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x28,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, 0xaf123456, v255
+// W32: encoding: [0xff,0xfe,0x29,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x28,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x28,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x28,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x28,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x28,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x28,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x28,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x28,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x28,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x28,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x28,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x28,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x28,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x28,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, 0xaf123456, v255
+// W64: encoding: [0xff,0xfe,0x29,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x48,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x48,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x48,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc_lo, s[104:105], v[2:3]
+// W32: encoding: [0x68,0x04,0x48,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x48,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc_lo, ttmp[14:15], v[2:3]
+// W32: encoding: [0x7a,0x04,0x48,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x48,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc_lo, null, v[2:3]
+// W32: encoding: [0x7c,0x04,0x48,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x48,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x48,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc_lo, src_scc, v[2:3]
+// W32: encoding: [0xfd,0x04,0x48,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc_lo, 0xaf123456, v[254:255]
+// W32: encoding: [0xff,0xfc,0x49,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x48,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x48,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x48,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc, s[104:105], v[2:3]
+// W64: encoding: [0x68,0x04,0x48,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x48,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc, ttmp[14:15], v[2:3]
+// W64: encoding: [0x7a,0x04,0x48,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x48,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc, null, v[2:3]
+// W64: encoding: [0x7c,0x04,0x48,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x48,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x48,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc, src_scc, v[2:3]
+// W64: encoding: [0xfd,0x04,0x48,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc, 0xaf123456, v[254:255]
+// W64: encoding: [0xff,0xfc,0x49,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x68,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, v127, v2
+// W32: encoding: [0x7f,0x05,0x68,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x68,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x68,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x68,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x68,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x68,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x68,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x68,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x68,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x68,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x68,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, 0.5, v2
+// W32: encoding: [0xff,0x04,0x68,0x7c,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x68,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, 0xfe0b, v127
+// W32: encoding: [0xff,0xfe,0x68,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x68,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, v127, v2
+// W64: encoding: [0x7f,0x05,0x68,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x68,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x68,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x68,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x68,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x68,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x68,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x68,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x68,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x68,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x68,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, 0.5, v2
+// W64: encoding: [0xff,0x04,0x68,0x7c,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x68,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, 0xfe0b, v127
+// W64: encoding: [0xff,0xfe,0x68,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x88,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x88,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x88,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x88,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x88,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x88,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x88,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x88,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x88,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x88,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x88,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x88,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x88,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x88,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, 0xaf123456, v255
+// W32: encoding: [0xff,0xfe,0x89,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x88,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x88,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x88,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x88,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x88,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x88,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x88,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x88,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x88,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x88,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x88,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x88,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x88,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x88,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, 0xaf123456, v255
+// W64: encoding: [0xff,0xfe,0x89,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0xa8,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0xa8,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0xa8,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc_lo, s[104:105], v[2:3]
+// W32: encoding: [0x68,0x04,0xa8,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0xa8,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc_lo, ttmp[14:15], v[2:3]
+// W32: encoding: [0x7a,0x04,0xa8,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0xa8,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc_lo, null, v[2:3]
+// W32: encoding: [0x7c,0x04,0xa8,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0xa8,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0xa8,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc_lo, src_scc, v[2:3]
+// W32: encoding: [0xfd,0x04,0xa8,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc_lo, 0xaf123456, v[254:255]
+// W32: encoding: [0xff,0xfc,0xa9,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0xa8,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0xa8,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0xa8,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc, s[104:105], v[2:3]
+// W64: encoding: [0x68,0x04,0xa8,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0xa8,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc, ttmp[14:15], v[2:3]
+// W64: encoding: [0x7a,0x04,0xa8,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0xa8,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc, null, v[2:3]
+// W64: encoding: [0x7c,0x04,0xa8,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0xa8,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0xa8,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc, src_scc, v[2:3]
+// W64: encoding: [0xfd,0x04,0xa8,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc, 0xaf123456, v[254:255]
+// W64: encoding: [0xff,0xfc,0xa9,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x78,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, v127, v2
+// W32: encoding: [0x7f,0x05,0x78,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x78,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x78,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x78,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x78,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x78,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x78,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x78,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x78,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x78,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x78,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, 0.5, v2
+// W32: encoding: [0xff,0x04,0x78,0x7c,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x78,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, 0xfe0b, v127
+// W32: encoding: [0xff,0xfe,0x78,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x78,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, v127, v2
+// W64: encoding: [0x7f,0x05,0x78,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x78,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x78,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x78,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x78,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x78,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x78,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x78,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x78,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x78,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x78,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, 0.5, v2
+// W64: encoding: [0xff,0x04,0x78,0x7c,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x78,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, 0xfe0b, v127
+// W64: encoding: [0xff,0xfe,0x78,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x98,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x98,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x98,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x98,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x98,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x98,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x98,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x98,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x98,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x98,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x98,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x98,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x98,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x98,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, 0xaf123456, v255
+// W32: encoding: [0xff,0xfe,0x99,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x98,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x98,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x98,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x98,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x98,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x98,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x98,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x98,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x98,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x98,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x98,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x98,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x98,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x98,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, 0xaf123456, v255
+// W64: encoding: [0xff,0xfe,0x99,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0xb8,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0xb8,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0xb8,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc_lo, s[104:105], v[2:3]
+// W32: encoding: [0x68,0x04,0xb8,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0xb8,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc_lo, ttmp[14:15], v[2:3]
+// W32: encoding: [0x7a,0x04,0xb8,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0xb8,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc_lo, null, v[2:3]
+// W32: encoding: [0x7c,0x04,0xb8,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0xb8,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0xb8,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc_lo, src_scc, v[2:3]
+// W32: encoding: [0xfd,0x04,0xb8,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc_lo, 0xaf123456, v[254:255]
+// W32: encoding: [0xff,0xfc,0xb9,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0xb8,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0xb8,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0xb8,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc, s[104:105], v[2:3]
+// W64: encoding: [0x68,0x04,0xb8,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0xb8,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc, ttmp[14:15], v[2:3]
+// W64: encoding: [0x7a,0x04,0xb8,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0xb8,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc, null, v[2:3]
+// W64: encoding: [0x7c,0x04,0xb8,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0xb8,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0xb8,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc, src_scc, v[2:3]
+// W64: encoding: [0xfd,0x04,0xb8,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc, 0xaf123456, v[254:255]
+// W64: encoding: [0xff,0xfc,0xb9,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x06,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, v127, v2
+// W32: encoding: [0x7f,0x05,0x06,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x06,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x06,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x06,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x06,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x06,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x06,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x06,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x06,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x06,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x06,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x06,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x06,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, 0xfe0b, v127
+// W32: encoding: [0xff,0xfe,0x06,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x06,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, v127, v2
+// W64: encoding: [0x7f,0x05,0x06,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x06,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x06,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x06,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x06,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x06,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x06,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x06,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x06,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x06,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x06,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x06,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x06,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, 0xfe0b, v127
+// W64: encoding: [0xff,0xfe,0x06,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x26,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x26,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x26,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x26,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x26,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x26,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x26,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x26,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x26,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x26,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x26,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x26,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x26,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x26,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, 0xaf123456, v255
+// W32: encoding: [0xff,0xfe,0x27,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x26,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x26,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x26,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x26,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x26,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x26,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x26,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x26,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x26,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x26,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x26,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x26,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x26,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x26,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, 0xaf123456, v255
+// W64: encoding: [0xff,0xfe,0x27,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x46,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x46,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x46,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc_lo, s[104:105], v[2:3]
+// W32: encoding: [0x68,0x04,0x46,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x46,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc_lo, ttmp[14:15], v[2:3]
+// W32: encoding: [0x7a,0x04,0x46,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x46,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc_lo, null, v[2:3]
+// W32: encoding: [0x7c,0x04,0x46,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x46,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x46,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc_lo, src_scc, v[2:3]
+// W32: encoding: [0xfd,0x04,0x46,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc_lo, 0xaf123456, v[254:255]
+// W32: encoding: [0xff,0xfc,0x47,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x46,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x46,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x46,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc, s[104:105], v[2:3]
+// W64: encoding: [0x68,0x04,0x46,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x46,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc, ttmp[14:15], v[2:3]
+// W64: encoding: [0x7a,0x04,0x46,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x46,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc, null, v[2:3]
+// W64: encoding: [0x7c,0x04,0x46,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x46,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x46,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc, src_scc, v[2:3]
+// W64: encoding: [0xfd,0x04,0x46,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc, 0xaf123456, v[254:255]
+// W64: encoding: [0xff,0xfc,0x47,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x66,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, v127, v2
+// W32: encoding: [0x7f,0x05,0x66,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x66,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x66,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x66,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x66,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x66,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x66,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x66,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x66,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x66,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x66,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, 0.5, v2
+// W32: encoding: [0xff,0x04,0x66,0x7c,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x66,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, 0xfe0b, v127
+// W32: encoding: [0xff,0xfe,0x66,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x66,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, v127, v2
+// W64: encoding: [0x7f,0x05,0x66,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x66,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x66,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x66,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x66,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x66,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x66,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x66,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x66,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x66,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x66,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, 0.5, v2
+// W64: encoding: [0xff,0x04,0x66,0x7c,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x66,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, 0xfe0b, v127
+// W64: encoding: [0xff,0xfe,0x66,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x86,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x86,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x86,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x86,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x86,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x86,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x86,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x86,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x86,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x86,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x86,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x86,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x86,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x86,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, 0xaf123456, v255
+// W32: encoding: [0xff,0xfe,0x87,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x86,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x86,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x86,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x86,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x86,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x86,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x86,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x86,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x86,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x86,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x86,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x86,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x86,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x86,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, 0xaf123456, v255
+// W64: encoding: [0xff,0xfe,0x87,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0xa6,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0xa6,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0xa6,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc_lo, s[104:105], v[2:3]
+// W32: encoding: [0x68,0x04,0xa6,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0xa6,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc_lo, ttmp[14:15], v[2:3]
+// W32: encoding: [0x7a,0x04,0xa6,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0xa6,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc_lo, null, v[2:3]
+// W32: encoding: [0x7c,0x04,0xa6,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0xa6,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0xa6,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc_lo, src_scc, v[2:3]
+// W32: encoding: [0xfd,0x04,0xa6,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc_lo, 0xaf123456, v[254:255]
+// W32: encoding: [0xff,0xfc,0xa7,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0xa6,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0xa6,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0xa6,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc, s[104:105], v[2:3]
+// W64: encoding: [0x68,0x04,0xa6,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0xa6,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc, ttmp[14:15], v[2:3]
+// W64: encoding: [0x7a,0x04,0xa6,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0xa6,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc, null, v[2:3]
+// W64: encoding: [0x7c,0x04,0xa6,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0xa6,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0xa6,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc, src_scc, v[2:3]
+// W64: encoding: [0xfd,0x04,0xa6,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc, 0xaf123456, v[254:255]
+// W64: encoding: [0xff,0xfc,0xa7,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x76,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, v127, v2
+// W32: encoding: [0x7f,0x05,0x76,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x76,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x76,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x76,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x76,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x76,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x76,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x76,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x76,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x76,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x76,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, 0.5, v2
+// W32: encoding: [0xff,0x04,0x76,0x7c,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x76,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, 0xfe0b, v127
+// W32: encoding: [0xff,0xfe,0x76,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x76,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, v127, v2
+// W64: encoding: [0x7f,0x05,0x76,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x76,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x76,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x76,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x76,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x76,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x76,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x76,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x76,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x76,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x76,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, 0.5, v2
+// W64: encoding: [0xff,0x04,0x76,0x7c,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x76,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, 0xfe0b, v127
+// W64: encoding: [0xff,0xfe,0x76,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x96,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x96,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x96,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x96,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x96,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x96,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x96,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x96,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x96,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x96,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x96,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x96,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x96,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x96,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, 0xaf123456, v255
+// W32: encoding: [0xff,0xfe,0x97,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x96,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x96,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x96,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x96,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x96,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x96,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x96,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x96,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x96,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x96,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x96,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x96,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x96,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x96,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, 0xaf123456, v255
+// W64: encoding: [0xff,0xfe,0x97,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0xb6,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0xb6,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0xb6,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc_lo, s[104:105], v[2:3]
+// W32: encoding: [0x68,0x04,0xb6,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0xb6,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc_lo, ttmp[14:15], v[2:3]
+// W32: encoding: [0x7a,0x04,0xb6,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0xb6,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc_lo, null, v[2:3]
+// W32: encoding: [0x7c,0x04,0xb6,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0xb6,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0xb6,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc_lo, src_scc, v[2:3]
+// W32: encoding: [0xfd,0x04,0xb6,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc_lo, 0xaf123456, v[254:255]
+// W32: encoding: [0xff,0xfc,0xb7,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0xb6,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0xb6,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0xb6,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc, s[104:105], v[2:3]
+// W64: encoding: [0x68,0x04,0xb6,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0xb6,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc, ttmp[14:15], v[2:3]
+// W64: encoding: [0x7a,0x04,0xb6,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0xb6,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc, null, v[2:3]
+// W64: encoding: [0x7c,0x04,0xb6,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0xb6,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0xb6,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc, src_scc, v[2:3]
+// W64: encoding: [0xfd,0x04,0xb6,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc, 0xaf123456, v[254:255]
+// W64: encoding: [0xff,0xfc,0xb7,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x0a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, v127, v2
+// W32: encoding: [0x7f,0x05,0x0a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x0a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x0a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x0a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x0a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x0a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x0a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x0a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x0a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x0a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x0a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x0a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x0a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, 0xfe0b, v127
+// W32: encoding: [0xff,0xfe,0x0a,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x0a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, v127, v2
+// W64: encoding: [0x7f,0x05,0x0a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x0a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x0a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x0a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x0a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x0a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x0a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x0a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x0a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x0a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x0a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x0a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x0a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, 0xfe0b, v127
+// W64: encoding: [0xff,0xfe,0x0a,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x2a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x2a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x2a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x2a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x2a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x2a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x2a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x2a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x2a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x2a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x2a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x2a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x2a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x2a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, 0xaf123456, v255
+// W32: encoding: [0xff,0xfe,0x2b,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x2a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x2a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x2a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x2a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x2a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x2a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x2a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x2a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x2a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x2a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x2a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x2a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x2a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x2a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, 0xaf123456, v255
+// W64: encoding: [0xff,0xfe,0x2b,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x4a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x4a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x4a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc_lo, s[104:105], v[2:3]
+// W32: encoding: [0x68,0x04,0x4a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x4a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc_lo, ttmp[14:15], v[2:3]
+// W32: encoding: [0x7a,0x04,0x4a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x4a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc_lo, null, v[2:3]
+// W32: encoding: [0x7c,0x04,0x4a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x4a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x4a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc_lo, src_scc, v[2:3]
+// W32: encoding: [0xfd,0x04,0x4a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc_lo, 0xaf123456, v[254:255]
+// W32: encoding: [0xff,0xfc,0x4b,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x4a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x4a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x4a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc, s[104:105], v[2:3]
+// W64: encoding: [0x68,0x04,0x4a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x4a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc, ttmp[14:15], v[2:3]
+// W64: encoding: [0x7a,0x04,0x4a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x4a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc, null, v[2:3]
+// W64: encoding: [0x7c,0x04,0x4a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x4a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x4a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc, src_scc, v[2:3]
+// W64: encoding: [0xfd,0x04,0x4a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc, 0xaf123456, v[254:255]
+// W64: encoding: [0xff,0xfc,0x4b,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x02,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, v127, v2
+// W32: encoding: [0x7f,0x05,0x02,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x02,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x02,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x02,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x02,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x02,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x02,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x02,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x02,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x02,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x02,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x02,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x02,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, 0xfe0b, v127
+// W32: encoding: [0xff,0xfe,0x02,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x02,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, v127, v2
+// W64: encoding: [0x7f,0x05,0x02,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x02,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x02,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x02,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x02,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x02,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x02,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x02,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x02,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x02,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x02,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x02,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x02,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, 0xfe0b, v127
+// W64: encoding: [0xff,0xfe,0x02,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x22,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x22,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x22,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x22,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x22,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x22,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x22,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x22,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x22,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x22,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x22,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x22,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x22,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x22,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, 0xaf123456, v255
+// W32: encoding: [0xff,0xfe,0x23,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x22,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x22,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x22,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x22,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x22,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x22,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x22,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x22,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x22,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x22,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x22,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x22,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x22,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x22,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, 0xaf123456, v255
+// W64: encoding: [0xff,0xfe,0x23,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x42,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x42,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x42,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc_lo, s[104:105], v[2:3]
+// W32: encoding: [0x68,0x04,0x42,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x42,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc_lo, ttmp[14:15], v[2:3]
+// W32: encoding: [0x7a,0x04,0x42,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x42,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc_lo, null, v[2:3]
+// W32: encoding: [0x7c,0x04,0x42,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x42,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x42,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc_lo, src_scc, v[2:3]
+// W32: encoding: [0xfd,0x04,0x42,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc_lo, 0xaf123456, v[254:255]
+// W32: encoding: [0xff,0xfc,0x43,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x42,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x42,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x42,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc, s[104:105], v[2:3]
+// W64: encoding: [0x68,0x04,0x42,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x42,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc, ttmp[14:15], v[2:3]
+// W64: encoding: [0x7a,0x04,0x42,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x42,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc, null, v[2:3]
+// W64: encoding: [0x7c,0x04,0x42,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x42,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x42,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc, src_scc, v[2:3]
+// W64: encoding: [0xfd,0x04,0x42,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc, 0xaf123456, v[254:255]
+// W64: encoding: [0xff,0xfc,0x43,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x62,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, v127, v2
+// W32: encoding: [0x7f,0x05,0x62,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x62,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x62,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x62,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x62,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x62,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x62,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x62,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x62,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x62,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x62,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, 0.5, v2
+// W32: encoding: [0xff,0x04,0x62,0x7c,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x62,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, 0xfe0b, v127
+// W32: encoding: [0xff,0xfe,0x62,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x62,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, v127, v2
+// W64: encoding: [0x7f,0x05,0x62,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x62,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x62,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x62,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x62,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x62,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x62,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x62,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x62,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x62,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x62,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, 0.5, v2
+// W64: encoding: [0xff,0x04,0x62,0x7c,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x62,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, 0xfe0b, v127
+// W64: encoding: [0xff,0xfe,0x62,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x82,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x82,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x82,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x82,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x82,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x82,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x82,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x82,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x82,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x82,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x82,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x82,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x82,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x82,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, 0xaf123456, v255
+// W32: encoding: [0xff,0xfe,0x83,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x82,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x82,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x82,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x82,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x82,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x82,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x82,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x82,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x82,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x82,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x82,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x82,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x82,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x82,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, 0xaf123456, v255
+// W64: encoding: [0xff,0xfe,0x83,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0xa2,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0xa2,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0xa2,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc_lo, s[104:105], v[2:3]
+// W32: encoding: [0x68,0x04,0xa2,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0xa2,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc_lo, ttmp[14:15], v[2:3]
+// W32: encoding: [0x7a,0x04,0xa2,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0xa2,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc_lo, null, v[2:3]
+// W32: encoding: [0x7c,0x04,0xa2,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0xa2,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0xa2,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc_lo, src_scc, v[2:3]
+// W32: encoding: [0xfd,0x04,0xa2,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc_lo, 0xaf123456, v[254:255]
+// W32: encoding: [0xff,0xfc,0xa3,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0xa2,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0xa2,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0xa2,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc, s[104:105], v[2:3]
+// W64: encoding: [0x68,0x04,0xa2,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0xa2,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc, ttmp[14:15], v[2:3]
+// W64: encoding: [0x7a,0x04,0xa2,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0xa2,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc, null, v[2:3]
+// W64: encoding: [0x7c,0x04,0xa2,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0xa2,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0xa2,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc, src_scc, v[2:3]
+// W64: encoding: [0xfd,0x04,0xa2,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc, 0xaf123456, v[254:255]
+// W64: encoding: [0xff,0xfc,0xa3,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x72,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, v127, v2
+// W32: encoding: [0x7f,0x05,0x72,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x72,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x72,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x72,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x72,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x72,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x72,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x72,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x72,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x72,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x72,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, 0.5, v2
+// W32: encoding: [0xff,0x04,0x72,0x7c,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x72,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, 0xfe0b, v127
+// W32: encoding: [0xff,0xfe,0x72,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x72,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, v127, v2
+// W64: encoding: [0x7f,0x05,0x72,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x72,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x72,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x72,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x72,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x72,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x72,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x72,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x72,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x72,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x72,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, 0.5, v2
+// W64: encoding: [0xff,0x04,0x72,0x7c,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x72,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, 0xfe0b, v127
+// W64: encoding: [0xff,0xfe,0x72,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x92,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x92,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x92,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x92,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x92,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x92,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x92,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x92,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x92,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x92,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x92,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x92,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x92,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x92,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, 0xaf123456, v255
+// W32: encoding: [0xff,0xfe,0x93,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x92,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x92,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x92,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x92,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x92,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x92,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x92,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x92,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x92,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x92,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x92,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x92,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x92,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x92,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, 0xaf123456, v255
+// W64: encoding: [0xff,0xfe,0x93,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0xb2,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0xb2,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0xb2,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc_lo, s[104:105], v[2:3]
+// W32: encoding: [0x68,0x04,0xb2,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0xb2,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc_lo, ttmp[14:15], v[2:3]
+// W32: encoding: [0x7a,0x04,0xb2,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0xb2,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc_lo, null, v[2:3]
+// W32: encoding: [0x7c,0x04,0xb2,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0xb2,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0xb2,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc_lo, src_scc, v[2:3]
+// W32: encoding: [0xfd,0x04,0xb2,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc_lo, 0xaf123456, v[254:255]
+// W32: encoding: [0xff,0xfc,0xb3,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0xb2,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0xb2,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0xb2,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc, s[104:105], v[2:3]
+// W64: encoding: [0x68,0x04,0xb2,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0xb2,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc, ttmp[14:15], v[2:3]
+// W64: encoding: [0x7a,0x04,0xb2,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0xb2,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc, null, v[2:3]
+// W64: encoding: [0x7c,0x04,0xb2,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0xb2,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0xb2,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc, src_scc, v[2:3]
+// W64: encoding: [0xfd,0x04,0xb2,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc, 0xaf123456, v[254:255]
+// W64: encoding: [0xff,0xfc,0xb3,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x6a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, v127, v2
+// W32: encoding: [0x7f,0x05,0x6a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x6a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x6a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x6a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x6a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x6a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x6a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x6a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x6a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x6a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x6a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, 0.5, v2
+// W32: encoding: [0xff,0x04,0x6a,0x7c,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x6a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, 0xfe0b, v127
+// W32: encoding: [0xff,0xfe,0x6a,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x6a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, v127, v2
+// W64: encoding: [0x7f,0x05,0x6a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x6a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x6a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x6a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x6a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x6a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x6a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x6a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x6a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x6a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x6a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, 0.5, v2
+// W64: encoding: [0xff,0x04,0x6a,0x7c,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x6a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, 0xfe0b, v127
+// W64: encoding: [0xff,0xfe,0x6a,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x8a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x8a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x8a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x8a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x8a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x8a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x8a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x8a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x8a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x8a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x8a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x8a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x8a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x8a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, 0xaf123456, v255
+// W32: encoding: [0xff,0xfe,0x8b,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x8a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x8a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x8a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x8a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x8a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x8a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x8a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x8a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x8a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x8a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x8a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x8a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x8a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x8a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, 0xaf123456, v255
+// W64: encoding: [0xff,0xfe,0x8b,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0xaa,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0xaa,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0xaa,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc_lo, s[104:105], v[2:3]
+// W32: encoding: [0x68,0x04,0xaa,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0xaa,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc_lo, ttmp[14:15], v[2:3]
+// W32: encoding: [0x7a,0x04,0xaa,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0xaa,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc_lo, null, v[2:3]
+// W32: encoding: [0x7c,0x04,0xaa,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0xaa,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0xaa,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc_lo, src_scc, v[2:3]
+// W32: encoding: [0xfd,0x04,0xaa,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc_lo, 0xaf123456, v[254:255]
+// W32: encoding: [0xff,0xfc,0xab,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0xaa,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0xaa,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0xaa,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc, s[104:105], v[2:3]
+// W64: encoding: [0x68,0x04,0xaa,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0xaa,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc, ttmp[14:15], v[2:3]
+// W64: encoding: [0x7a,0x04,0xaa,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0xaa,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc, null, v[2:3]
+// W64: encoding: [0x7c,0x04,0xaa,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0xaa,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0xaa,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc, src_scc, v[2:3]
+// W64: encoding: [0xfd,0x04,0xaa,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc, 0xaf123456, v[254:255]
+// W64: encoding: [0xff,0xfc,0xab,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x7a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, v127, v2
+// W32: encoding: [0x7f,0x05,0x7a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x7a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x7a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x7a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x7a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x7a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x7a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x7a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x7a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x7a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x7a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, 0.5, v2
+// W32: encoding: [0xff,0x04,0x7a,0x7c,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x7a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, 0xfe0b, v127
+// W32: encoding: [0xff,0xfe,0x7a,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x7a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, v127, v2
+// W64: encoding: [0x7f,0x05,0x7a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x7a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x7a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x7a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x7a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x7a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x7a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x7a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x7a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x7a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x7a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, 0.5, v2
+// W64: encoding: [0xff,0x04,0x7a,0x7c,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x7a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, 0xfe0b, v127
+// W64: encoding: [0xff,0xfe,0x7a,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x9a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x9a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x9a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x9a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x9a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x9a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x9a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x9a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x9a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x9a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x9a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x9a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x9a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x9a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, 0xaf123456, v255
+// W32: encoding: [0xff,0xfe,0x9b,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x9a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x9a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x9a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x9a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x9a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x9a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x9a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x9a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x9a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x9a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x9a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x9a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x9a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x9a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, 0xaf123456, v255
+// W64: encoding: [0xff,0xfe,0x9b,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0xba,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0xba,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0xba,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc_lo, s[104:105], v[2:3]
+// W32: encoding: [0x68,0x04,0xba,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0xba,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc_lo, ttmp[14:15], v[2:3]
+// W32: encoding: [0x7a,0x04,0xba,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0xba,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc_lo, null, v[2:3]
+// W32: encoding: [0x7c,0x04,0xba,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0xba,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0xba,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc_lo, src_scc, v[2:3]
+// W32: encoding: [0xfd,0x04,0xba,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc_lo, 0xaf123456, v[254:255]
+// W32: encoding: [0xff,0xfc,0xbb,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0xba,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0xba,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0xba,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc, s[104:105], v[2:3]
+// W64: encoding: [0x68,0x04,0xba,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0xba,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc, ttmp[14:15], v[2:3]
+// W64: encoding: [0x7a,0x04,0xba,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0xba,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc, null, v[2:3]
+// W64: encoding: [0x7c,0x04,0xba,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0xba,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0xba,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc, src_scc, v[2:3]
+// W64: encoding: [0xfd,0x04,0xba,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc, 0xaf123456, v[254:255]
+// W64: encoding: [0xff,0xfc,0xbb,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x1a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, v127, v2
+// W32: encoding: [0x7f,0x05,0x1a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x1a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x1a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x1a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x1a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x1a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x1a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x1a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x1a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x1a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x1a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x1a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x1a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, 0xfe0b, v127
+// W32: encoding: [0xff,0xfe,0x1a,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x1a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, v127, v2
+// W64: encoding: [0x7f,0x05,0x1a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x1a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x1a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x1a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x1a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x1a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x1a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x1a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x1a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x1a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x1a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x1a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x1a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, 0xfe0b, v127
+// W64: encoding: [0xff,0xfe,0x1a,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x3a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x3a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x3a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x3a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x3a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x3a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x3a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x3a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x3a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x3a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x3a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x3a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x3a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x3a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, 0xaf123456, v255
+// W32: encoding: [0xff,0xfe,0x3b,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x3a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x3a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x3a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x3a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x3a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x3a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x3a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x3a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x3a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x3a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x3a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x3a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x3a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x3a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, 0xaf123456, v255
+// W64: encoding: [0xff,0xfe,0x3b,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x5a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x5a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x5a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc_lo, s[104:105], v[2:3]
+// W32: encoding: [0x68,0x04,0x5a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x5a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc_lo, ttmp[14:15], v[2:3]
+// W32: encoding: [0x7a,0x04,0x5a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x5a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc_lo, null, v[2:3]
+// W32: encoding: [0x7c,0x04,0x5a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x5a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x5a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc_lo, src_scc, v[2:3]
+// W32: encoding: [0xfd,0x04,0x5a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc_lo, 0xaf123456, v[254:255]
+// W32: encoding: [0xff,0xfc,0x5b,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x5a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x5a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x5a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc, s[104:105], v[2:3]
+// W64: encoding: [0x68,0x04,0x5a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x5a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc, ttmp[14:15], v[2:3]
+// W64: encoding: [0x7a,0x04,0x5a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x5a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc, null, v[2:3]
+// W64: encoding: [0x7c,0x04,0x5a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x5a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x5a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc, src_scc, v[2:3]
+// W64: encoding: [0xfd,0x04,0x5a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc, 0xaf123456, v[254:255]
+// W64: encoding: [0xff,0xfc,0x5b,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x12,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, v127, v2
+// W32: encoding: [0x7f,0x05,0x12,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x12,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x12,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x12,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x12,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x12,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x12,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x12,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x12,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x12,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x12,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x12,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x12,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, 0xfe0b, v127
+// W32: encoding: [0xff,0xfe,0x12,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x12,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, v127, v2
+// W64: encoding: [0x7f,0x05,0x12,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x12,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x12,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x12,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x12,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x12,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x12,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x12,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x12,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x12,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x12,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x12,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x12,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, 0xfe0b, v127
+// W64: encoding: [0xff,0xfe,0x12,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x32,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x32,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x32,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x32,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x32,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x32,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x32,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x32,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x32,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x32,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x32,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x32,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x32,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x32,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, 0xaf123456, v255
+// W32: encoding: [0xff,0xfe,0x33,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x32,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x32,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x32,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x32,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x32,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x32,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x32,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x32,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x32,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x32,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x32,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x32,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x32,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x32,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, 0xaf123456, v255
+// W64: encoding: [0xff,0xfe,0x33,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x52,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x52,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x52,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc_lo, s[104:105], v[2:3]
+// W32: encoding: [0x68,0x04,0x52,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x52,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc_lo, ttmp[14:15], v[2:3]
+// W32: encoding: [0x7a,0x04,0x52,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x52,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc_lo, null, v[2:3]
+// W32: encoding: [0x7c,0x04,0x52,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x52,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x52,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc_lo, src_scc, v[2:3]
+// W32: encoding: [0xfd,0x04,0x52,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc_lo, 0xaf123456, v[254:255]
+// W32: encoding: [0xff,0xfc,0x53,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x52,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x52,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x52,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc, s[104:105], v[2:3]
+// W64: encoding: [0x68,0x04,0x52,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x52,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc, ttmp[14:15], v[2:3]
+// W64: encoding: [0x7a,0x04,0x52,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x52,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc, null, v[2:3]
+// W64: encoding: [0x7c,0x04,0x52,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x52,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x52,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc, src_scc, v[2:3]
+// W64: encoding: [0xfd,0x04,0x52,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc, 0xaf123456, v[254:255]
+// W64: encoding: [0xff,0xfc,0x53,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x16,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, v127, v2
+// W32: encoding: [0x7f,0x05,0x16,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x16,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x16,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x16,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x16,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x16,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x16,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x16,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x16,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x16,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x16,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x16,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x16,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, 0xfe0b, v127
+// W32: encoding: [0xff,0xfe,0x16,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x16,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, v127, v2
+// W64: encoding: [0x7f,0x05,0x16,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x16,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x16,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x16,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x16,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x16,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x16,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x16,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x16,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x16,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x16,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x16,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x16,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, 0xfe0b, v127
+// W64: encoding: [0xff,0xfe,0x16,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x36,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x36,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x36,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x36,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x36,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x36,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x36,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x36,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x36,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x36,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x36,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x36,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x36,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x36,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, 0xaf123456, v255
+// W32: encoding: [0xff,0xfe,0x37,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x36,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x36,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x36,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x36,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x36,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x36,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x36,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x36,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x36,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x36,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x36,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x36,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x36,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x36,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, 0xaf123456, v255
+// W64: encoding: [0xff,0xfe,0x37,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x56,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x56,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x56,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc_lo, s[104:105], v[2:3]
+// W32: encoding: [0x68,0x04,0x56,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x56,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc_lo, ttmp[14:15], v[2:3]
+// W32: encoding: [0x7a,0x04,0x56,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x56,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc_lo, null, v[2:3]
+// W32: encoding: [0x7c,0x04,0x56,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x56,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x56,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc_lo, src_scc, v[2:3]
+// W32: encoding: [0xfd,0x04,0x56,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc_lo, 0xaf123456, v[254:255]
+// W32: encoding: [0xff,0xfc,0x57,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x56,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x56,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x56,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc, s[104:105], v[2:3]
+// W64: encoding: [0x68,0x04,0x56,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x56,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc, ttmp[14:15], v[2:3]
+// W64: encoding: [0x7a,0x04,0x56,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x56,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc, null, v[2:3]
+// W64: encoding: [0x7c,0x04,0x56,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x56,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x56,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc, src_scc, v[2:3]
+// W64: encoding: [0xfd,0x04,0x56,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc, 0xaf123456, v[254:255]
+// W64: encoding: [0xff,0xfc,0x57,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x18,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, v127, v2
+// W32: encoding: [0x7f,0x05,0x18,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x18,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x18,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x18,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x18,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x18,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x18,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x18,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x18,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x18,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x18,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x18,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x18,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, 0xfe0b, v127
+// W32: encoding: [0xff,0xfe,0x18,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x18,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, v127, v2
+// W64: encoding: [0x7f,0x05,0x18,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x18,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x18,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x18,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x18,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x18,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x18,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x18,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x18,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x18,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x18,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x18,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x18,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, 0xfe0b, v127
+// W64: encoding: [0xff,0xfe,0x18,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x38,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x38,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x38,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x38,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x38,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x38,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x38,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x38,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x38,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x38,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x38,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x38,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x38,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x38,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, 0xaf123456, v255
+// W32: encoding: [0xff,0xfe,0x39,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x38,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x38,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x38,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x38,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x38,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x38,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x38,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x38,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x38,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x38,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x38,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x38,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x38,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x38,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, 0xaf123456, v255
+// W64: encoding: [0xff,0xfe,0x39,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x58,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x58,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x58,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc_lo, s[104:105], v[2:3]
+// W32: encoding: [0x68,0x04,0x58,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x58,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc_lo, ttmp[14:15], v[2:3]
+// W32: encoding: [0x7a,0x04,0x58,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x58,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc_lo, null, v[2:3]
+// W32: encoding: [0x7c,0x04,0x58,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x58,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x58,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc_lo, src_scc, v[2:3]
+// W32: encoding: [0xfd,0x04,0x58,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc_lo, 0xaf123456, v[254:255]
+// W32: encoding: [0xff,0xfc,0x59,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x58,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x58,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x58,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc, s[104:105], v[2:3]
+// W64: encoding: [0x68,0x04,0x58,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x58,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc, ttmp[14:15], v[2:3]
+// W64: encoding: [0x7a,0x04,0x58,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x58,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc, null, v[2:3]
+// W64: encoding: [0x7c,0x04,0x58,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x58,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x58,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc, src_scc, v[2:3]
+// W64: encoding: [0xfd,0x04,0x58,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc, 0xaf123456, v[254:255]
+// W64: encoding: [0xff,0xfc,0x59,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x14,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, v127, v2
+// W32: encoding: [0x7f,0x05,0x14,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x14,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x14,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x14,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x14,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x14,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x14,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x14,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x14,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x14,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x14,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x14,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x14,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, 0xfe0b, v127
+// W32: encoding: [0xff,0xfe,0x14,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x14,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, v127, v2
+// W64: encoding: [0x7f,0x05,0x14,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x14,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x14,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x14,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x14,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x14,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x14,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x14,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x14,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x14,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x14,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x14,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x14,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, 0xfe0b, v127
+// W64: encoding: [0xff,0xfe,0x14,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x34,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x34,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x34,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x34,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x34,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x34,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x34,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x34,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x34,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x34,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x34,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x34,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x34,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x34,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, 0xaf123456, v255
+// W32: encoding: [0xff,0xfe,0x35,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x34,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x34,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x34,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x34,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x34,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x34,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x34,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x34,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x34,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x34,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x34,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x34,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x34,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x34,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, 0xaf123456, v255
+// W64: encoding: [0xff,0xfe,0x35,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x54,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x54,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x54,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc_lo, s[104:105], v[2:3]
+// W32: encoding: [0x68,0x04,0x54,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x54,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc_lo, ttmp[14:15], v[2:3]
+// W32: encoding: [0x7a,0x04,0x54,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x54,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc_lo, null, v[2:3]
+// W32: encoding: [0x7c,0x04,0x54,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x54,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x54,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc_lo, src_scc, v[2:3]
+// W32: encoding: [0xfd,0x04,0x54,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc_lo, 0xaf123456, v[254:255]
+// W32: encoding: [0xff,0xfc,0x55,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x54,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x54,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x54,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc, s[104:105], v[2:3]
+// W64: encoding: [0x68,0x04,0x54,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x54,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc, ttmp[14:15], v[2:3]
+// W64: encoding: [0x7a,0x04,0x54,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x54,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc, null, v[2:3]
+// W64: encoding: [0x7c,0x04,0x54,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x54,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x54,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc, src_scc, v[2:3]
+// W64: encoding: [0xfd,0x04,0x54,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc, 0xaf123456, v[254:255]
+// W64: encoding: [0xff,0xfc,0x55,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x1c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, v127, v2
+// W32: encoding: [0x7f,0x05,0x1c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x1c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x1c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x1c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x1c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x1c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x1c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x1c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x1c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x1c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x1c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x1c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x1c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, 0xfe0b, v127
+// W32: encoding: [0xff,0xfe,0x1c,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x1c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, v127, v2
+// W64: encoding: [0x7f,0x05,0x1c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x1c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x1c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x1c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x1c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x1c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x1c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x1c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x1c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x1c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x1c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x1c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x1c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, 0xfe0b, v127
+// W64: encoding: [0xff,0xfe,0x1c,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x3c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x3c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x3c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x3c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x3c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x3c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x3c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x3c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x3c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x3c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x3c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x3c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x3c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x3c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, 0xaf123456, v255
+// W32: encoding: [0xff,0xfe,0x3d,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x3c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x3c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x3c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x3c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x3c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x3c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x3c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x3c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x3c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x3c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x3c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x3c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x3c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x3c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, 0xaf123456, v255
+// W64: encoding: [0xff,0xfe,0x3d,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x5c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x5c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x5c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc_lo, s[104:105], v[2:3]
+// W32: encoding: [0x68,0x04,0x5c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x5c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc_lo, ttmp[14:15], v[2:3]
+// W32: encoding: [0x7a,0x04,0x5c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x5c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc_lo, null, v[2:3]
+// W32: encoding: [0x7c,0x04,0x5c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x5c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x5c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc_lo, src_scc, v[2:3]
+// W32: encoding: [0xfd,0x04,0x5c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc_lo, 0xaf123456, v[254:255]
+// W32: encoding: [0xff,0xfc,0x5d,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x5c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x5c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x5c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc, s[104:105], v[2:3]
+// W64: encoding: [0x68,0x04,0x5c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x5c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc, ttmp[14:15], v[2:3]
+// W64: encoding: [0x7a,0x04,0x5c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x5c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc, null, v[2:3]
+// W64: encoding: [0x7c,0x04,0x5c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x5c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x5c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc, src_scc, v[2:3]
+// W64: encoding: [0xfd,0x04,0x5c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc, 0xaf123456, v[254:255]
+// W64: encoding: [0xff,0xfc,0x5d,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x0e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, v127, v2
+// W32: encoding: [0x7f,0x05,0x0e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x0e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x0e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x0e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x0e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x0e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x0e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x0e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x0e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x0e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x0e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x0e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x0e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, 0xfe0b, v127
+// W32: encoding: [0xff,0xfe,0x0e,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x0e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, v127, v2
+// W64: encoding: [0x7f,0x05,0x0e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x0e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x0e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x0e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x0e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x0e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x0e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x0e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x0e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x0e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x0e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x0e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x0e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, 0xfe0b, v127
+// W64: encoding: [0xff,0xfe,0x0e,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x2e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x2e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x2e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x2e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x2e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x2e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x2e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x2e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x2e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x2e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x2e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x2e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x2e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x2e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, 0xaf123456, v255
+// W32: encoding: [0xff,0xfe,0x2f,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x2e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x2e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x2e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x2e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x2e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x2e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x2e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x2e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x2e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x2e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x2e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x2e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x2e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x2e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, 0xaf123456, v255
+// W64: encoding: [0xff,0xfe,0x2f,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x4e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x4e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x4e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc_lo, s[104:105], v[2:3]
+// W32: encoding: [0x68,0x04,0x4e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x4e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc_lo, ttmp[14:15], v[2:3]
+// W32: encoding: [0x7a,0x04,0x4e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x4e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc_lo, null, v[2:3]
+// W32: encoding: [0x7c,0x04,0x4e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x4e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x4e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc_lo, src_scc, v[2:3]
+// W32: encoding: [0xfd,0x04,0x4e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc_lo, 0xaf123456, v[254:255]
+// W32: encoding: [0xff,0xfc,0x4f,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x4e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x4e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x4e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc, s[104:105], v[2:3]
+// W64: encoding: [0x68,0x04,0x4e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x4e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc, ttmp[14:15], v[2:3]
+// W64: encoding: [0x7a,0x04,0x4e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x4e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc, null, v[2:3]
+// W64: encoding: [0x7c,0x04,0x4e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x4e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x4e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc, src_scc, v[2:3]
+// W64: encoding: [0xfd,0x04,0x4e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc, 0xaf123456, v[254:255]
+// W64: encoding: [0xff,0xfc,0x4f,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x10,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, v127, v2
+// W32: encoding: [0x7f,0x05,0x10,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x10,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x10,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x10,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x10,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x10,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x10,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x10,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x10,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x10,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x10,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x10,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x10,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, 0xfe0b, v127
+// W32: encoding: [0xff,0xfe,0x10,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x10,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, v127, v2
+// W64: encoding: [0x7f,0x05,0x10,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x10,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x10,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x10,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x10,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x10,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x10,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x10,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x10,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x10,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x10,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x10,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x10,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, 0xfe0b, v127
+// W64: encoding: [0xff,0xfe,0x10,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x30,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x30,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x30,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, s105, v2
+// W32: encoding: [0x69,0x04,0x30,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x30,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x30,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, ttmp15, v2
+// W32: encoding: [0x7b,0x04,0x30,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7d,0x04,0x30,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x30,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x30,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, null, v2
+// W32: encoding: [0x7c,0x04,0x30,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x30,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x30,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, src_scc, v2
+// W32: encoding: [0xfd,0x04,0x30,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, 0xaf123456, v255
+// W32: encoding: [0xff,0xfe,0x31,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x30,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x30,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x30,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, s105, v2
+// W64: encoding: [0x69,0x04,0x30,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x30,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x30,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, ttmp15, v2
+// W64: encoding: [0x7b,0x04,0x30,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, m0, v2
+// W64: encoding: [0x7d,0x04,0x30,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x30,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x30,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, null, v2
+// W64: encoding: [0x7c,0x04,0x30,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x30,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x30,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, src_scc, v2
+// W64: encoding: [0xfd,0x04,0x30,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, 0xaf123456, v255
+// W64: encoding: [0xff,0xfe,0x31,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x50,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x50,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x50,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc_lo, s[104:105], v[2:3]
+// W32: encoding: [0x68,0x04,0x50,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x50,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc_lo, ttmp[14:15], v[2:3]
+// W32: encoding: [0x7a,0x04,0x50,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x50,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc_lo, null, v[2:3]
+// W32: encoding: [0x7c,0x04,0x50,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x50,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x50,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc_lo, src_scc, v[2:3]
+// W32: encoding: [0xfd,0x04,0x50,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc_lo, 0xaf123456, v[254:255]
+// W32: encoding: [0xff,0xfc,0x51,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x50,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x50,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x50,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc, s[104:105], v[2:3]
+// W64: encoding: [0x68,0x04,0x50,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x50,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc, ttmp[14:15], v[2:3]
+// W64: encoding: [0x7a,0x04,0x50,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x50,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc, null, v[2:3]
+// W64: encoding: [0x7c,0x04,0x50,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x50,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x50,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc, src_scc, v[2:3]
+// W64: encoding: [0xfd,0x04,0x50,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc, 0xaf123456, v[254:255]
+// W64: encoding: [0xff,0xfc,0x51,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp16.s
new file mode 100644
index 000000000000..bebf149a9b85
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp16.s
@@ -0,0 +1,6052 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W32 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W64 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+
+v_cmp_class_f16_dpp vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x6f,0x35,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x6f,0x35,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0xfc,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0xfd,0x7c,0xff,0x6f,0x35,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0xfc,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0xfd,0x7c,0xff,0x6f,0x35,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x04,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x04,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x04,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x04,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x04,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x04,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x24,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x24,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x24,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x24,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x24,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x24,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x24,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x24,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x24,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x24,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x24,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x24,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x24,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x25,0x7c,0xff,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x24,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x24,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x24,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x24,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x24,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x24,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x24,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x24,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x24,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x24,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x24,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x24,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x24,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x25,0x7c,0xff,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x64,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x64,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x64,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x64,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x64,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x64,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x64,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x64,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x64,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x64,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x64,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x64,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x64,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x64,0x7c,0x7f,0x6f,0x05,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x64,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x64,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x64,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x64,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x64,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x64,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x64,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x64,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x64,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x64,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x64,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x64,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x64,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x64,0x7c,0x7f,0x6f,0x05,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x84,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x84,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x84,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x84,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x84,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x84,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x84,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x84,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x84,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x84,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x84,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x84,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x84,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x85,0x7c,0xff,0x6f,0x05,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x84,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x84,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x84,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x84,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x84,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x84,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x84,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x84,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x84,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x84,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x84,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x84,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x84,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x85,0x7c,0xff,0x6f,0x05,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x74,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x74,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x74,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x74,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x74,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x74,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x74,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x74,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x74,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x74,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x74,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x74,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x74,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x74,0x7c,0x7f,0x6f,0x05,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x74,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x74,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x74,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x74,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x74,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x74,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x74,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x74,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x74,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x74,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x74,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x74,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x74,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x74,0x7c,0x7f,0x6f,0x05,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x94,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x94,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x94,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x94,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x94,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x94,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x94,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x94,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x94,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x94,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x94,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x94,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x94,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x95,0x7c,0xff,0x6f,0x05,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x94,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x94,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x94,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x94,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x94,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x94,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x94,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x94,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x94,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x94,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x94,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x94,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x94,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x95,0x7c,0xff,0x6f,0x05,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x0c,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x0c,0x7c,0x7f,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x0c,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x0c,0x7c,0x7f,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x2c,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x2d,0x7c,0xff,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x2c,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x2d,0x7c,0xff,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x6c,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x6c,0x7c,0x7f,0x6f,0x05,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x6c,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x6c,0x7c,0x7f,0x6f,0x05,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x8c,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x8d,0x7c,0xff,0x6f,0x05,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x8c,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x8d,0x7c,0xff,0x6f,0x05,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x7c,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x7c,0x7c,0x7f,0x6f,0x05,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x7c,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x7c,0x7c,0x7f,0x6f,0x05,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x9c,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x9d,0x7c,0xff,0x6f,0x05,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x9c,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x9d,0x7c,0xff,0x6f,0x05,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x08,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x08,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x08,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x08,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x08,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x08,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x08,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x08,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x08,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x08,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x08,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x08,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x08,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x08,0x7c,0x7f,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x08,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x08,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x08,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x08,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x08,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x08,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x08,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x08,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x08,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x08,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x08,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x08,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x08,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x08,0x7c,0x7f,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x28,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x28,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x28,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x28,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x28,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x28,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x28,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x28,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x28,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x28,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x28,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x28,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x28,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x29,0x7c,0xff,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x28,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x28,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x28,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x28,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x28,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x28,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x28,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x28,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x28,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x28,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x28,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x28,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x28,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x29,0x7c,0xff,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x68,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x68,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x68,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x68,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x68,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x68,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x68,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x68,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x68,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x68,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x68,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x68,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x68,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x68,0x7c,0x7f,0x6f,0x05,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x68,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x68,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x68,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x68,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x68,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x68,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x68,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x68,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x68,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x68,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x68,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x68,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x68,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x68,0x7c,0x7f,0x6f,0x05,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x88,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x88,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x88,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x88,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x88,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x88,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x88,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x88,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x88,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x88,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x88,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x88,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x88,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x89,0x7c,0xff,0x6f,0x05,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x88,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x88,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x88,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x88,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x88,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x88,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x88,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x88,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x88,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x88,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x88,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x88,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x88,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x89,0x7c,0xff,0x6f,0x05,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x78,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x78,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x78,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x78,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x78,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x78,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x78,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x78,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x78,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x78,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x78,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x78,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x78,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x78,0x7c,0x7f,0x6f,0x05,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x78,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x78,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x78,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x78,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x78,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x78,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x78,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x78,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x78,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x78,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x78,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x78,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x78,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x78,0x7c,0x7f,0x6f,0x05,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x98,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x98,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x98,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x98,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x98,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x98,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x98,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x98,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x98,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x98,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x98,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x98,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x98,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x99,0x7c,0xff,0x6f,0x05,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x98,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x98,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x98,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x98,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x98,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x98,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x98,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x98,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x98,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x98,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x98,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x98,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x98,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x99,0x7c,0xff,0x6f,0x05,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x06,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x06,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x06,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x06,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x06,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x06,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x06,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x06,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x06,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x06,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x06,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x06,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x06,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x06,0x7c,0x7f,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x06,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x06,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x06,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x06,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x06,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x06,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x06,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x06,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x06,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x06,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x06,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x06,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x06,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x06,0x7c,0x7f,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x26,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x26,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x26,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x26,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x26,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x26,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x26,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x26,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x26,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x26,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x26,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x26,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x26,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x27,0x7c,0xff,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x26,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x26,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x26,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x26,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x26,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x26,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x26,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x26,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x26,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x26,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x26,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x26,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x26,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x27,0x7c,0xff,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x66,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x66,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x66,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x66,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x66,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x66,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x66,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x66,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x66,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x66,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x66,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x66,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x66,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x66,0x7c,0x7f,0x6f,0x05,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x66,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x66,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x66,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x66,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x66,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x66,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x66,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x66,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x66,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x66,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x66,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x66,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x66,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x66,0x7c,0x7f,0x6f,0x05,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x86,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x86,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x86,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x86,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x86,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x86,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x86,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x86,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x86,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x86,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x86,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x86,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x86,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x87,0x7c,0xff,0x6f,0x05,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x86,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x86,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x86,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x86,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x86,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x86,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x86,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x86,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x86,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x86,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x86,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x86,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x86,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x87,0x7c,0xff,0x6f,0x05,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x76,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x76,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x76,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x76,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x76,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x76,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x76,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x76,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x76,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x76,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x76,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x76,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x76,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x76,0x7c,0x7f,0x6f,0x05,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x76,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x76,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x76,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x76,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x76,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x76,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x76,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x76,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x76,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x76,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x76,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x76,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x76,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x76,0x7c,0x7f,0x6f,0x05,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x96,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x96,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x96,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x96,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x96,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x96,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x96,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x96,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x96,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x96,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x96,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x96,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x96,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x97,0x7c,0xff,0x6f,0x05,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x96,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x96,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x96,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x96,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x96,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x96,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x96,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x96,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x96,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x96,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x96,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x96,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x96,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x97,0x7c,0xff,0x6f,0x05,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x0a,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x0a,0x7c,0x7f,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x0a,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x0a,0x7c,0x7f,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x2a,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x2b,0x7c,0xff,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x2a,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x2b,0x7c,0xff,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x02,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x02,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x02,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x02,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x02,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x02,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x22,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x22,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x22,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x22,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x22,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x22,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x22,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x22,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x22,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x22,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x22,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x22,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x22,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x23,0x7c,0xff,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x22,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x22,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x22,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x22,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x22,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x22,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x22,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x22,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x22,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x22,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x22,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x22,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x22,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x23,0x7c,0xff,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x62,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x62,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x62,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x62,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x62,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x62,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x62,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x62,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x62,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x62,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x62,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x62,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x62,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x62,0x7c,0x7f,0x6f,0x05,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x62,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x62,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x62,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x62,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x62,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x62,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x62,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x62,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x62,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x62,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x62,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x62,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x62,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x62,0x7c,0x7f,0x6f,0x05,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x82,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x82,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x82,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x82,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x82,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x82,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x82,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x82,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x82,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x82,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x82,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x82,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x82,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x83,0x7c,0xff,0x6f,0x05,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x82,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x82,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x82,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x82,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x82,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x82,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x82,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x82,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x82,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x82,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x82,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x82,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x82,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x83,0x7c,0xff,0x6f,0x05,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x72,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x72,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x72,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x72,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x72,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x72,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x72,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x72,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x72,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x72,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x72,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x72,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x72,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x72,0x7c,0x7f,0x6f,0x05,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x72,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x72,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x72,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x72,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x72,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x72,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x72,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x72,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x72,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x72,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x72,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x72,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x72,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x72,0x7c,0x7f,0x6f,0x05,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x92,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x92,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x92,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x92,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x92,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x92,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x92,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x92,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x92,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x92,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x92,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x92,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x92,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x93,0x7c,0xff,0x6f,0x05,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x92,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x92,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x92,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x92,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x92,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x92,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x92,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x92,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x92,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x92,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x92,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x92,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x92,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x93,0x7c,0xff,0x6f,0x05,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x6a,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x6a,0x7c,0x7f,0x6f,0x05,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x6a,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x6a,0x7c,0x7f,0x6f,0x05,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x8a,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x8b,0x7c,0xff,0x6f,0x05,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x8a,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x8b,0x7c,0xff,0x6f,0x05,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x7a,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x7a,0x7c,0x7f,0x6f,0x05,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x7a,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x7a,0x7c,0x7f,0x6f,0x05,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x9a,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x9b,0x7c,0xff,0x6f,0x05,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x9a,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x9b,0x7c,0xff,0x6f,0x05,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x1a,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x1a,0x7c,0x7f,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x1a,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x1a,0x7c,0x7f,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x3a,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x3b,0x7c,0xff,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x3a,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x3b,0x7c,0xff,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x12,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x12,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x12,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x12,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x12,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x12,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x12,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x12,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x12,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x12,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x12,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x12,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x12,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x12,0x7c,0x7f,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x12,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x12,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x12,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x12,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x12,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x12,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x12,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x12,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x12,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x12,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x12,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x12,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x12,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x12,0x7c,0x7f,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x32,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x32,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x32,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x32,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x32,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x32,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x32,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x32,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x32,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x32,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x32,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x32,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x32,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x33,0x7c,0xff,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x32,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x32,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x32,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x32,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x32,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x32,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x32,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x32,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x32,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x32,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x32,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x32,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x32,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x33,0x7c,0xff,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x16,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x16,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x16,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x16,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x16,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x16,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x16,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x16,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x16,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x16,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x16,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x16,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x16,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x16,0x7c,0x7f,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x16,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x16,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x16,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x16,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x16,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x16,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x16,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x16,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x16,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x16,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x16,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x16,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x16,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x16,0x7c,0x7f,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x36,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x36,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x36,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x36,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x36,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x36,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x36,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x36,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x36,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x36,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x36,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x36,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x36,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x37,0x7c,0xff,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x36,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x36,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x36,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x36,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x36,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x36,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x36,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x36,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x36,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x36,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x36,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x36,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x36,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x37,0x7c,0xff,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x18,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x18,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x18,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x18,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x18,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x18,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x18,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x18,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x18,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x18,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x18,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x18,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x18,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x18,0x7c,0x7f,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x18,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x18,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x18,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x18,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x18,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x18,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x18,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x18,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x18,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x18,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x18,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x18,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x18,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x18,0x7c,0x7f,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x38,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x38,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x38,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x38,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x38,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x38,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x38,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x38,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x38,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x38,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x38,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x38,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x38,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x39,0x7c,0xff,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x38,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x38,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x38,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x38,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x38,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x38,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x38,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x38,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x38,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x38,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x38,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x38,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x38,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x39,0x7c,0xff,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x14,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x14,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x14,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x14,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x14,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x14,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x14,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x14,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x14,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x14,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x14,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x14,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x14,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x14,0x7c,0x7f,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x14,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x14,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x14,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x14,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x14,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x14,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x14,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x14,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x14,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x14,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x14,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x14,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x14,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x14,0x7c,0x7f,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x34,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x34,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x34,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x34,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x34,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x34,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x34,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x34,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x34,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x34,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x34,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x34,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x34,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x35,0x7c,0xff,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x34,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x34,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x34,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x34,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x34,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x34,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x34,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x34,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x34,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x34,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x34,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x34,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x34,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x35,0x7c,0xff,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x1c,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x1c,0x7c,0x7f,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x1c,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x1c,0x7c,0x7f,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x3c,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x3d,0x7c,0xff,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x3c,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x3d,0x7c,0xff,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x0e,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x0e,0x7c,0x7f,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x0e,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x0e,0x7c,0x7f,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x2e,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x2f,0x7c,0xff,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x2e,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x2f,0x7c,0xff,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x10,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x10,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x10,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x10,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x10,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x10,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x10,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x10,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x10,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x10,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x10,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x10,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x10,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x10,0x7c,0x7f,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x10,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x10,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x10,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x10,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x10,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x10,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x10,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x10,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x10,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x10,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x10,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x10,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x10,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x10,0x7c,0x7f,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
+// W32: encoding: [0xfa,0x04,0x30,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
+// W32: encoding: [0xfa,0x04,0x30,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, v1, v2 row_mirror
+// W32: encoding: [0xfa,0x04,0x30,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, v1, v2 row_half_mirror
+// W32: encoding: [0xfa,0x04,0x30,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, v1, v2 row_shl:1
+// W32: encoding: [0xfa,0x04,0x30,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, v1, v2 row_shl:15
+// W32: encoding: [0xfa,0x04,0x30,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, v1, v2 row_shr:1
+// W32: encoding: [0xfa,0x04,0x30,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, v1, v2 row_shr:15
+// W32: encoding: [0xfa,0x04,0x30,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, v1, v2 row_ror:1
+// W32: encoding: [0xfa,0x04,0x30,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, v1, v2 row_ror:15
+// W32: encoding: [0xfa,0x04,0x30,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W32: encoding: [0xfa,0x04,0x30,0x7c,0x01,0x50,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: encoding: [0xfa,0x04,0x30,0x7c,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: encoding: [0xfa,0x04,0x30,0x7c,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: encoding: [0xfa,0xfe,0x31,0x7c,0xff,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, v1, v2 quad_perm:[3,2,1,0]
+// W64: encoding: [0xfa,0x04,0x30,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, v1, v2 quad_perm:[0,1,2,3]
+// W64: encoding: [0xfa,0x04,0x30,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, v1, v2 row_mirror
+// W64: encoding: [0xfa,0x04,0x30,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, v1, v2 row_half_mirror
+// W64: encoding: [0xfa,0x04,0x30,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, v1, v2 row_shl:1
+// W64: encoding: [0xfa,0x04,0x30,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, v1, v2 row_shl:15
+// W64: encoding: [0xfa,0x04,0x30,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, v1, v2 row_shr:1
+// W64: encoding: [0xfa,0x04,0x30,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, v1, v2 row_shr:15
+// W64: encoding: [0xfa,0x04,0x30,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, v1, v2 row_ror:1
+// W64: encoding: [0xfa,0x04,0x30,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, v1, v2 row_ror:15
+// W64: encoding: [0xfa,0x04,0x30,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// W64: encoding: [0xfa,0x04,0x30,0x7c,0x01,0x50,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: encoding: [0xfa,0x04,0x30,0x7c,0x01,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: encoding: [0xfa,0x04,0x30,0x7c,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: encoding: [0xfa,0xfe,0x31,0x7c,0xff,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp8.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp8.s
new file mode 100644
index 000000000000..57a30964a848
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp8.s
@@ -0,0 +1,1300 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W32 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W64 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+
+v_cmp_class_f16_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0xfc,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0xfc,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0xfd,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0xfc,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0xfc,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0xfd,0x7c,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x04,0x7c,0x7f,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x04,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x24,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x24,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x25,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x24,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x24,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x25,0x7c,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x64,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x64,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x64,0x7c,0x7f,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x64,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x64,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x64,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x84,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x84,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x85,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x84,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x84,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x85,0x7c,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x74,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x74,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x74,0x7c,0x7f,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x74,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x74,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x74,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x94,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x94,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x95,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x94,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x94,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x95,0x7c,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x0c,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x0c,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x0c,0x7c,0x7f,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x0c,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x0c,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x0c,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x2c,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x2c,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x2d,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x2c,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x2c,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x2d,0x7c,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x6c,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x6c,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x6c,0x7c,0x7f,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x6c,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x6c,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x6c,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x8c,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x8c,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x8d,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x8c,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x8c,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x8d,0x7c,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x7c,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x7c,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x7c,0x7c,0x7f,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x7c,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x7c,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x7c,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x9c,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x9c,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x9d,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x9c,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x9c,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x9d,0x7c,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x08,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x08,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x08,0x7c,0x7f,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x08,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x08,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x08,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x28,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x28,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x29,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x28,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x28,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x29,0x7c,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x68,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x68,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x68,0x7c,0x7f,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x68,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x68,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x68,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x88,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x88,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x89,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x88,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x88,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x89,0x7c,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x78,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x78,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x78,0x7c,0x7f,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x78,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x78,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x78,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x98,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x98,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x99,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x98,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x98,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x99,0x7c,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x06,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x06,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x06,0x7c,0x7f,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x06,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x06,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x06,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x26,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x26,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x27,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x26,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x26,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x27,0x7c,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x66,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x66,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x66,0x7c,0x7f,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x66,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x66,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x66,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x86,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x86,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x87,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x86,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x86,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x87,0x7c,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x76,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x76,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x76,0x7c,0x7f,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x76,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x76,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x76,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x96,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x96,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x97,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x96,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x96,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x97,0x7c,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x0a,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x0a,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x0a,0x7c,0x7f,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x0a,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x0a,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x0a,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x2a,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x2a,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x2b,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x2a,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x2a,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x2b,0x7c,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x02,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x02,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x02,0x7c,0x7f,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x02,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x02,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x02,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x22,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x22,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x23,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x22,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x22,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x23,0x7c,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x62,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x62,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x62,0x7c,0x7f,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x62,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x62,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x62,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x82,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x82,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x83,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x82,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x82,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x83,0x7c,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x72,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x72,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x72,0x7c,0x7f,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x72,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x72,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x72,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x92,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x92,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x93,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x92,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x92,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x93,0x7c,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x6a,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x6a,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x6a,0x7c,0x7f,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x6a,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x6a,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x6a,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x8a,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x8a,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x8b,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x8a,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x8a,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x8b,0x7c,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x7a,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x7a,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x7a,0x7c,0x7f,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x7a,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x7a,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x7a,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x9a,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x9a,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x9b,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x9a,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x9a,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x9b,0x7c,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x1a,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x1a,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x1a,0x7c,0x7f,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x1a,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x1a,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x1a,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x3a,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x3a,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x3b,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x3a,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x3a,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x3b,0x7c,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x12,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x12,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x12,0x7c,0x7f,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x12,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x12,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x12,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x32,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x32,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x33,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x32,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x32,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x33,0x7c,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x16,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x16,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x16,0x7c,0x7f,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x16,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x16,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x16,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x36,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x36,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x37,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x36,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x36,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x37,0x7c,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x18,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x18,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x18,0x7c,0x7f,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x18,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x18,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x18,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x38,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x38,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x39,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x38,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x38,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x39,0x7c,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x14,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x14,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x14,0x7c,0x7f,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x14,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x14,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x14,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x34,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x34,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x35,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x34,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x34,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x35,0x7c,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x1c,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x1c,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x1c,0x7c,0x7f,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x1c,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x1c,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x1c,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x3c,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x3c,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x3d,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x3c,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x3c,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x3d,0x7c,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x0e,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x0e,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x0e,0x7c,0x7f,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x0e,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x0e,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x0e,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x2e,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x2e,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x2f,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x2e,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x2e,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x2f,0x7c,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x10,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x10,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x10,0x7c,0x7f,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x10,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x10,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x10,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: encoding: [0xe9,0x04,0x30,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: encoding: [0xea,0x04,0x30,0x7c,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: encoding: [0xe9,0xfe,0x31,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: encoding: [0xe9,0x04,0x30,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: encoding: [0xea,0x04,0x30,0x7c,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: encoding: [0xe9,0xfe,0x31,0x7c,0xff,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_err.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_err.s
new file mode 100644
index 000000000000..3b76c26a2f40
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_err.s
@@ -0,0 +1,1774 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX12 --implicit-check-not=error %s
+
+v_cmp_class_f16_e32 vcc, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16_e32 vcc, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16_e32 vcc, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16_e32 vcc, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16_e32 vcc_lo, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16_e32 vcc_lo, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16_e32 vcc_lo, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16_e32 vcc, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16_e32 vcc, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16_e32 vcc, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16_e32 vcc, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16_e32 vcc_lo, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16_e32 vcc_lo, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16_e32 vcc_lo, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16_e32 vcc_lo, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16_e32 vcc, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16_e32 vcc, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16_e32 vcc, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16_e32 vcc, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16_e32 vcc_lo, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16_e32 vcc_lo, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16_e32 vcc_lo, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16_e32 vcc_lo, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16_e32 vcc, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16_e32 vcc, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16_e32 vcc, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16_e32 vcc, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16_e32 vcc_lo, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16_e32 vcc_lo, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16_e32 vcc_lo, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16_e32 vcc_lo, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16_e32 vcc, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16_e32 vcc, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16_e32 vcc, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16_e32 vcc, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16_e32 vcc_lo, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16_e32 vcc_lo, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16_e32 vcc_lo, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16_e32 vcc_lo, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16_e32 vcc, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16_e32 vcc, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16_e32 vcc, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16_e32 vcc, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16_e32 vcc_lo, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16_e32 vcc_lo, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16_e32 vcc_lo, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16_e32 vcc_lo, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16_e32 vcc, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16_e32 vcc, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16_e32 vcc, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16_e32 vcc, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16_e32 vcc_lo, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16_e32 vcc_lo, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16_e32 vcc_lo, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16_e32 vcc_lo, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16_e32 vcc, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16_e32 vcc, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16_e32 vcc, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16_e32 vcc, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16_e32 vcc_lo, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16_e32 vcc_lo, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16_e32 vcc_lo, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16_e32 vcc_lo, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16_e32 vcc, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16_e32 vcc, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16_e32 vcc, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16_e32 vcc, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16_e32 vcc_lo, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16_e32 vcc_lo, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16_e32 vcc_lo, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16_e32 vcc_lo, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16_e32 vcc, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16_e32 vcc, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16_e32 vcc, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16_e32 vcc, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16_e32 vcc_lo, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16_e32 vcc_lo, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16_e32 vcc_lo, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16_e32 vcc_lo, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16_e32 vcc, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16_e32 vcc, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16_e32 vcc, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16_e32 vcc, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16_e32 vcc_lo, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16_e32 vcc_lo, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16_e32 vcc_lo, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16_e32 vcc_lo, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16_e32 vcc, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16_e32 vcc, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16_e32 vcc, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16_e32 vcc, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16_e32 vcc_lo, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16_e32 vcc_lo, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16_e32 vcc_lo, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16_e32 vcc_lo, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16_e32 vcc, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16_e32 vcc, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16_e32 vcc, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16_e32 vcc, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16_e32 vcc_lo, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16_e32 vcc_lo, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16_e32 vcc_lo, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16_e32 vcc_lo, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16_e32 vcc, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16_e32 vcc, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16_e32 vcc, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16_e32 vcc, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16_e32 vcc_lo, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16_e32 vcc_lo, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16_e32 vcc_lo, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16_e32 vcc_lo, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16_e32 vcc, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16_e32 vcc, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16_e32 vcc, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16_e32 vcc, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16_e32 vcc_lo, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16_e32 vcc_lo, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16_e32 vcc_lo, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16_e32 vcc_lo, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16_e32 vcc, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16_e32 vcc, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16_e32 vcc, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16_e32 vcc, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16_e32 vcc_lo, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16_e32 vcc_lo, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16_e32 vcc_lo, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16_e32 vcc_lo, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16_e32 vcc, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16_e32 vcc, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16_e32 vcc, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16_e32 vcc, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16_e32 vcc_lo, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16_e32 vcc_lo, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16_e32 vcc_lo, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16_e32 vcc_lo, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16_e32 vcc, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16_e32 vcc, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16_e32 vcc, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16_e32 vcc, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16_e32 vcc_lo, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16_e32 vcc_lo, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16_e32 vcc_lo, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16_e32 vcc_lo, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16_e32 vcc, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16_e32 vcc, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16_e32 vcc, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16_e32 vcc, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16_e32 vcc_lo, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16_e32 vcc_lo, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16_e32 vcc_lo, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16_e32 vcc_lo, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16_e32 vcc, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16_e32 vcc, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16_e32 vcc, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16_e32 vcc, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16_e32 vcc_lo, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16_e32 vcc_lo, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16_e32 vcc_lo, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16_e32 vcc_lo, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16_e32 vcc, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16_e32 vcc, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16_e32 vcc, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16_e32 vcc, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16_e32 vcc_lo, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16_e32 vcc_lo, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16_e32 vcc_lo, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16_e32 vcc_lo, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16_e32 vcc, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16_e32 vcc, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16_e32 vcc, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16_e32 vcc, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16_e32 vcc_lo, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16_e32 vcc_lo, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16_e32 vcc_lo, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16_e32 vcc_lo, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16_e32 vcc, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16_e32 vcc, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16_e32 vcc, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16_e32 vcc, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16_e32 vcc_lo, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16_e32 vcc_lo, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16_e32 vcc_lo, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16_e32 vcc_lo, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16_e32 vcc, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16_e32 vcc, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16_e32 vcc, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16_e32 vcc, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16_e32 vcc_lo, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16_e32 vcc_lo, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16_e32 vcc_lo, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16_e32 vcc_lo, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16_e32 vcc, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16_e32 vcc, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16_e32 vcc, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16_e32 vcc, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16_e32 vcc_lo, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16_e32 vcc_lo, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16_e32 vcc_lo, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16_e32 vcc_lo, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16_e32 vcc, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16_e32 vcc, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16_e32 vcc, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16_e32 vcc, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16_e32 vcc_lo, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16_e32 vcc_lo, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16_e32 vcc_lo, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16_e32 vcc_lo, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16_e32 vcc, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16_e32 vcc, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16_e32 vcc, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16_e32 vcc, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16_e32 vcc_lo, v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16_e32 vcc_lo, v127, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16_e32 vcc_lo, vcc_hi, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16_e32 vcc_lo, vcc_lo, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16_e32 vcc, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16_e32 vcc_lo, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16_e32 vcc, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16_e32 vcc_lo, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16_e32 vcc, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16_e32 vcc_lo, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16_e32 vcc, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16_e32 vcc_lo, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16_e32 vcc, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16_e32 vcc_lo, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16_e32 vcc, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16_e32 vcc_lo, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16_e32 vcc, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16_e32 vcc_lo, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16_e32 vcc, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16_e32 vcc_lo, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16_e32 vcc, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16_e32 vcc_lo, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16_e32 vcc, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16_e32 vcc_lo, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16_e32 vcc, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16_e32 vcc_lo, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16_e32 vcc, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16_e32 vcc_lo, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16_e32 vcc, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16_e32 vcc_lo, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16_e32 vcc, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16_e32 vcc_lo, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16_e32 vcc, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16_e32 vcc_lo, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16_e32 vcc, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16_e32 vcc_lo, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16_e32 vcc, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16_e32 vcc_lo, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16_e32 vcc, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16_e32 vcc_lo, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16_e32 vcc, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16_e32 vcc_lo, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16_e32 vcc, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16_e32 vcc_lo, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16_e32 vcc, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16_e32 vcc_lo, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16_e32 vcc, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16_e32 vcc_lo, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16_e32 vcc, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16_e32 vcc_lo, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16_e32 vcc, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16_e32 vcc_lo, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16_e32 vcc, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16_e32 vcc_lo, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16_e32 vcc, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16_e32 vcc_lo, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16_e32 vcc, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16_e32 vcc_lo, v128, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s
new file mode 100644
index 000000000000..bec31a47ec37
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s
@@ -0,0 +1,2368 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W32 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W64 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+
+v_cmp_class_f16 vcc, v1, v255
+// W64: v_cmp_class_f16_e64 vcc, v1, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, v127, v255
+// W64: v_cmp_class_f16_e64 vcc, v127, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, vcc_hi, v255
+// W64: v_cmp_class_f16_e64 vcc, vcc_hi, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, vcc_lo, v255
+// W64: v_cmp_class_f16_e64 vcc, vcc_lo, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, v127, v255
+// W32: v_cmp_class_f16_e64 vcc_lo, v127, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, vcc_hi, v255
+// W32: v_cmp_class_f16_e64 vcc_lo, vcc_hi, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, vcc_lo, v255
+// W32: v_cmp_class_f16_e64 vcc_lo, vcc_lo, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1, v255
+// W64: v_cmp_eq_f16_e64 vcc, v1, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v127, v255
+// W64: v_cmp_eq_f16_e64 vcc, v127, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, vcc_hi, v255
+// W64: v_cmp_eq_f16_e64 vcc, vcc_hi, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, vcc_lo, v255
+// W64: v_cmp_eq_f16_e64 vcc, vcc_lo, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1, v255
+// W32: v_cmp_eq_f16_e64 vcc_lo, v1, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v127, v255
+// W32: v_cmp_eq_f16_e64 vcc_lo, v127, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, vcc_hi, v255
+// W32: v_cmp_eq_f16_e64 vcc_lo, vcc_hi, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, vcc_lo, v255
+// W32: v_cmp_eq_f16_e64 vcc_lo, vcc_lo, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, v1, v255
+// W64: v_cmp_eq_i16_e64 vcc, v1, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, v127, v255
+// W64: v_cmp_eq_i16_e64 vcc, v127, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, vcc_hi, v255
+// W64: v_cmp_eq_i16_e64 vcc, vcc_hi, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, vcc_lo, v255
+// W64: v_cmp_eq_i16_e64 vcc, vcc_lo, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, v1, v255
+// W32: v_cmp_eq_i16_e64 vcc_lo, v1, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, v127, v255
+// W32: v_cmp_eq_i16_e64 vcc_lo, v127, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, vcc_hi, v255
+// W32: v_cmp_eq_i16_e64 vcc_lo, vcc_hi, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, vcc_lo, v255
+// W32: v_cmp_eq_i16_e64 vcc_lo, vcc_lo, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, v1, v255
+// W64: v_cmp_eq_u16_e64 vcc, v1, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, v127, v255
+// W64: v_cmp_eq_u16_e64 vcc, v127, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, vcc_hi, v255
+// W64: v_cmp_eq_u16_e64 vcc, vcc_hi, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, vcc_lo, v255
+// W64: v_cmp_eq_u16_e64 vcc, vcc_lo, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, v1, v255
+// W32: v_cmp_eq_u16_e64 vcc_lo, v1, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, v127, v255
+// W32: v_cmp_eq_u16_e64 vcc_lo, v127, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, vcc_hi, v255
+// W32: v_cmp_eq_u16_e64 vcc_lo, vcc_hi, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, vcc_lo, v255
+// W32: v_cmp_eq_u16_e64 vcc_lo, vcc_lo, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, v1, v255
+// W64: v_cmp_ge_f16_e64 vcc, v1, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, v127, v255
+// W64: v_cmp_ge_f16_e64 vcc, v127, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, vcc_hi, v255
+// W64: v_cmp_ge_f16_e64 vcc, vcc_hi, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, vcc_lo, v255
+// W64: v_cmp_ge_f16_e64 vcc, vcc_lo, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, v1, v255
+// W32: v_cmp_ge_f16_e64 vcc_lo, v1, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, v127, v255
+// W32: v_cmp_ge_f16_e64 vcc_lo, v127, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, vcc_hi, v255
+// W32: v_cmp_ge_f16_e64 vcc_lo, vcc_hi, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, vcc_lo, v255
+// W32: v_cmp_ge_f16_e64 vcc_lo, vcc_lo, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, v1, v255
+// W64: v_cmp_ge_i16_e64 vcc, v1, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, v127, v255
+// W64: v_cmp_ge_i16_e64 vcc, v127, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, vcc_hi, v255
+// W64: v_cmp_ge_i16_e64 vcc, vcc_hi, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, vcc_lo, v255
+// W64: v_cmp_ge_i16_e64 vcc, vcc_lo, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, v1, v255
+// W32: v_cmp_ge_i16_e64 vcc_lo, v1, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, v127, v255
+// W32: v_cmp_ge_i16_e64 vcc_lo, v127, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, vcc_hi, v255
+// W32: v_cmp_ge_i16_e64 vcc_lo, vcc_hi, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, vcc_lo, v255
+// W32: v_cmp_ge_i16_e64 vcc_lo, vcc_lo, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, v1, v255
+// W64: v_cmp_ge_u16_e64 vcc, v1, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, v127, v255
+// W64: v_cmp_ge_u16_e64 vcc, v127, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, vcc_hi, v255
+// W64: v_cmp_ge_u16_e64 vcc, vcc_hi, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, vcc_lo, v255
+// W64: v_cmp_ge_u16_e64 vcc, vcc_lo, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, v1, v255
+// W32: v_cmp_ge_u16_e64 vcc_lo, v1, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, v127, v255
+// W32: v_cmp_ge_u16_e64 vcc_lo, v127, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, vcc_hi, v255
+// W32: v_cmp_ge_u16_e64 vcc_lo, vcc_hi, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, vcc_lo, v255
+// W32: v_cmp_ge_u16_e64 vcc_lo, vcc_lo, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, v1, v255
+// W64: v_cmp_gt_f16_e64 vcc, v1, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, v127, v255
+// W64: v_cmp_gt_f16_e64 vcc, v127, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, vcc_hi, v255
+// W64: v_cmp_gt_f16_e64 vcc, vcc_hi, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, vcc_lo, v255
+// W64: v_cmp_gt_f16_e64 vcc, vcc_lo, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, v1, v255
+// W32: v_cmp_gt_f16_e64 vcc_lo, v1, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, v127, v255
+// W32: v_cmp_gt_f16_e64 vcc_lo, v127, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, vcc_hi, v255
+// W32: v_cmp_gt_f16_e64 vcc_lo, vcc_hi, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, vcc_lo, v255
+// W32: v_cmp_gt_f16_e64 vcc_lo, vcc_lo, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, v1, v255
+// W64: v_cmp_gt_i16_e64 vcc, v1, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, v127, v255
+// W64: v_cmp_gt_i16_e64 vcc, v127, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, vcc_hi, v255
+// W64: v_cmp_gt_i16_e64 vcc, vcc_hi, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, vcc_lo, v255
+// W64: v_cmp_gt_i16_e64 vcc, vcc_lo, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, v1, v255
+// W32: v_cmp_gt_i16_e64 vcc_lo, v1, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, v127, v255
+// W32: v_cmp_gt_i16_e64 vcc_lo, v127, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, vcc_hi, v255
+// W32: v_cmp_gt_i16_e64 vcc_lo, vcc_hi, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, vcc_lo, v255
+// W32: v_cmp_gt_i16_e64 vcc_lo, vcc_lo, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, v1, v255
+// W64: v_cmp_gt_u16_e64 vcc, v1, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, v127, v255
+// W64: v_cmp_gt_u16_e64 vcc, v127, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, vcc_hi, v255
+// W64: v_cmp_gt_u16_e64 vcc, vcc_hi, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, vcc_lo, v255
+// W64: v_cmp_gt_u16_e64 vcc, vcc_lo, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, v1, v255
+// W32: v_cmp_gt_u16_e64 vcc_lo, v1, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, v127, v255
+// W32: v_cmp_gt_u16_e64 vcc_lo, v127, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, vcc_hi, v255
+// W32: v_cmp_gt_u16_e64 vcc_lo, vcc_hi, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, vcc_lo, v255
+// W32: v_cmp_gt_u16_e64 vcc_lo, vcc_lo, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, v1, v255
+// W64: v_cmp_le_f16_e64 vcc, v1, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, v127, v255
+// W64: v_cmp_le_f16_e64 vcc, v127, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, vcc_hi, v255
+// W64: v_cmp_le_f16_e64 vcc, vcc_hi, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, vcc_lo, v255
+// W64: v_cmp_le_f16_e64 vcc, vcc_lo, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, v1, v255
+// W32: v_cmp_le_f16_e64 vcc_lo, v1, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, v127, v255
+// W32: v_cmp_le_f16_e64 vcc_lo, v127, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, vcc_hi, v255
+// W32: v_cmp_le_f16_e64 vcc_lo, vcc_hi, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, vcc_lo, v255
+// W32: v_cmp_le_f16_e64 vcc_lo, vcc_lo, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, v1, v255
+// W64: v_cmp_le_i16_e64 vcc, v1, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, v127, v255
+// W64: v_cmp_le_i16_e64 vcc, v127, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, vcc_hi, v255
+// W64: v_cmp_le_i16_e64 vcc, vcc_hi, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, vcc_lo, v255
+// W64: v_cmp_le_i16_e64 vcc, vcc_lo, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, v1, v255
+// W32: v_cmp_le_i16_e64 vcc_lo, v1, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, v127, v255
+// W32: v_cmp_le_i16_e64 vcc_lo, v127, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, vcc_hi, v255
+// W32: v_cmp_le_i16_e64 vcc_lo, vcc_hi, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, vcc_lo, v255
+// W32: v_cmp_le_i16_e64 vcc_lo, vcc_lo, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, v1, v255
+// W64: v_cmp_le_u16_e64 vcc, v1, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, v127, v255
+// W64: v_cmp_le_u16_e64 vcc, v127, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, vcc_hi, v255
+// W64: v_cmp_le_u16_e64 vcc, vcc_hi, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, vcc_lo, v255
+// W64: v_cmp_le_u16_e64 vcc, vcc_lo, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, v1, v255
+// W32: v_cmp_le_u16_e64 vcc_lo, v1, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, v127, v255
+// W32: v_cmp_le_u16_e64 vcc_lo, v127, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, vcc_hi, v255
+// W32: v_cmp_le_u16_e64 vcc_lo, vcc_hi, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, vcc_lo, v255
+// W32: v_cmp_le_u16_e64 vcc_lo, vcc_lo, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, v1, v255
+// W64: v_cmp_lg_f16_e64 vcc, v1, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, v127, v255
+// W64: v_cmp_lg_f16_e64 vcc, v127, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, vcc_hi, v255
+// W64: v_cmp_lg_f16_e64 vcc, vcc_hi, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, vcc_lo, v255
+// W64: v_cmp_lg_f16_e64 vcc, vcc_lo, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, v1, v255
+// W32: v_cmp_lg_f16_e64 vcc_lo, v1, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, v127, v255
+// W32: v_cmp_lg_f16_e64 vcc_lo, v127, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, vcc_hi, v255
+// W32: v_cmp_lg_f16_e64 vcc_lo, vcc_hi, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, vcc_lo, v255
+// W32: v_cmp_lg_f16_e64 vcc_lo, vcc_lo, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, v1, v255
+// W64: v_cmp_lt_f16_e64 vcc, v1, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, v127, v255
+// W64: v_cmp_lt_f16_e64 vcc, v127, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, vcc_hi, v255
+// W64: v_cmp_lt_f16_e64 vcc, vcc_hi, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, vcc_lo, v255
+// W64: v_cmp_lt_f16_e64 vcc, vcc_lo, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, v1, v255
+// W32: v_cmp_lt_f16_e64 vcc_lo, v1, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, v127, v255
+// W32: v_cmp_lt_f16_e64 vcc_lo, v127, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, vcc_hi, v255
+// W32: v_cmp_lt_f16_e64 vcc_lo, vcc_hi, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, vcc_lo, v255
+// W32: v_cmp_lt_f16_e64 vcc_lo, vcc_lo, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, v1, v255
+// W64: v_cmp_lt_i16_e64 vcc, v1, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, v127, v255
+// W64: v_cmp_lt_i16_e64 vcc, v127, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, vcc_hi, v255
+// W64: v_cmp_lt_i16_e64 vcc, vcc_hi, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, vcc_lo, v255
+// W64: v_cmp_lt_i16_e64 vcc, vcc_lo, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, v1, v255
+// W32: v_cmp_lt_i16_e64 vcc_lo, v1, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, v127, v255
+// W32: v_cmp_lt_i16_e64 vcc_lo, v127, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, vcc_hi, v255
+// W32: v_cmp_lt_i16_e64 vcc_lo, vcc_hi, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, vcc_lo, v255
+// W32: v_cmp_lt_i16_e64 vcc_lo, vcc_lo, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, v1, v255
+// W64: v_cmp_lt_u16_e64 vcc, v1, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, v127, v255
+// W64: v_cmp_lt_u16_e64 vcc, v127, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, vcc_hi, v255
+// W64: v_cmp_lt_u16_e64 vcc, vcc_hi, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, vcc_lo, v255
+// W64: v_cmp_lt_u16_e64 vcc, vcc_lo, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, v1, v255
+// W32: v_cmp_lt_u16_e64 vcc_lo, v1, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, v127, v255
+// W32: v_cmp_lt_u16_e64 vcc_lo, v127, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, vcc_hi, v255
+// W32: v_cmp_lt_u16_e64 vcc_lo, vcc_hi, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, vcc_lo, v255
+// W32: v_cmp_lt_u16_e64 vcc_lo, vcc_lo, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, v1, v255
+// W64: v_cmp_ne_i16_e64 vcc, v1, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, v127, v255
+// W64: v_cmp_ne_i16_e64 vcc, v127, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, vcc_hi, v255
+// W64: v_cmp_ne_i16_e64 vcc, vcc_hi, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, vcc_lo, v255
+// W64: v_cmp_ne_i16_e64 vcc, vcc_lo, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, v1, v255
+// W32: v_cmp_ne_i16_e64 vcc_lo, v1, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, v127, v255
+// W32: v_cmp_ne_i16_e64 vcc_lo, v127, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, vcc_hi, v255
+// W32: v_cmp_ne_i16_e64 vcc_lo, vcc_hi, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, vcc_lo, v255
+// W32: v_cmp_ne_i16_e64 vcc_lo, vcc_lo, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, v1, v255
+// W64: v_cmp_ne_u16_e64 vcc, v1, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, v127, v255
+// W64: v_cmp_ne_u16_e64 vcc, v127, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, vcc_hi, v255
+// W64: v_cmp_ne_u16_e64 vcc, vcc_hi, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, vcc_lo, v255
+// W64: v_cmp_ne_u16_e64 vcc, vcc_lo, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, v1, v255
+// W32: v_cmp_ne_u16_e64 vcc_lo, v1, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, v127, v255
+// W32: v_cmp_ne_u16_e64 vcc_lo, v127, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, vcc_hi, v255
+// W32: v_cmp_ne_u16_e64 vcc_lo, vcc_hi, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, vcc_lo, v255
+// W32: v_cmp_ne_u16_e64 vcc_lo, vcc_lo, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, v1, v255
+// W64: v_cmp_neq_f16_e64 vcc, v1, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, v127, v255
+// W64: v_cmp_neq_f16_e64 vcc, v127, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, vcc_hi, v255
+// W64: v_cmp_neq_f16_e64 vcc, vcc_hi, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, vcc_lo, v255
+// W64: v_cmp_neq_f16_e64 vcc, vcc_lo, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, v1, v255
+// W32: v_cmp_neq_f16_e64 vcc_lo, v1, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, v127, v255
+// W32: v_cmp_neq_f16_e64 vcc_lo, v127, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, vcc_hi, v255
+// W32: v_cmp_neq_f16_e64 vcc_lo, vcc_hi, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, vcc_lo, v255
+// W32: v_cmp_neq_f16_e64 vcc_lo, vcc_lo, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, v1, v255
+// W64: v_cmp_nge_f16_e64 vcc, v1, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, v127, v255
+// W64: v_cmp_nge_f16_e64 vcc, v127, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, vcc_hi, v255
+// W64: v_cmp_nge_f16_e64 vcc, vcc_hi, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, vcc_lo, v255
+// W64: v_cmp_nge_f16_e64 vcc, vcc_lo, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, v1, v255
+// W32: v_cmp_nge_f16_e64 vcc_lo, v1, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, v127, v255
+// W32: v_cmp_nge_f16_e64 vcc_lo, v127, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, vcc_hi, v255
+// W32: v_cmp_nge_f16_e64 vcc_lo, vcc_hi, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, vcc_lo, v255
+// W32: v_cmp_nge_f16_e64 vcc_lo, vcc_lo, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, v1, v255
+// W64: v_cmp_ngt_f16_e64 vcc, v1, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, v127, v255
+// W64: v_cmp_ngt_f16_e64 vcc, v127, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, vcc_hi, v255
+// W64: v_cmp_ngt_f16_e64 vcc, vcc_hi, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, vcc_lo, v255
+// W64: v_cmp_ngt_f16_e64 vcc, vcc_lo, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, v1, v255
+// W32: v_cmp_ngt_f16_e64 vcc_lo, v1, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, v127, v255
+// W32: v_cmp_ngt_f16_e64 vcc_lo, v127, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, vcc_hi, v255
+// W32: v_cmp_ngt_f16_e64 vcc_lo, vcc_hi, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, vcc_lo, v255
+// W32: v_cmp_ngt_f16_e64 vcc_lo, vcc_lo, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, v1, v255
+// W64: v_cmp_nle_f16_e64 vcc, v1, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, v127, v255
+// W64: v_cmp_nle_f16_e64 vcc, v127, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, vcc_hi, v255
+// W64: v_cmp_nle_f16_e64 vcc, vcc_hi, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, vcc_lo, v255
+// W64: v_cmp_nle_f16_e64 vcc, vcc_lo, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, v1, v255
+// W32: v_cmp_nle_f16_e64 vcc_lo, v1, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, v127, v255
+// W32: v_cmp_nle_f16_e64 vcc_lo, v127, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, vcc_hi, v255
+// W32: v_cmp_nle_f16_e64 vcc_lo, vcc_hi, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, vcc_lo, v255
+// W32: v_cmp_nle_f16_e64 vcc_lo, vcc_lo, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, v1, v255
+// W64: v_cmp_nlg_f16_e64 vcc, v1, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, v127, v255
+// W64: v_cmp_nlg_f16_e64 vcc, v127, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, vcc_hi, v255
+// W64: v_cmp_nlg_f16_e64 vcc, vcc_hi, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, vcc_lo, v255
+// W64: v_cmp_nlg_f16_e64 vcc, vcc_lo, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, v1, v255
+// W32: v_cmp_nlg_f16_e64 vcc_lo, v1, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, v127, v255
+// W32: v_cmp_nlg_f16_e64 vcc_lo, v127, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, vcc_hi, v255
+// W32: v_cmp_nlg_f16_e64 vcc_lo, vcc_hi, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, vcc_lo, v255
+// W32: v_cmp_nlg_f16_e64 vcc_lo, vcc_lo, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, v1, v255
+// W64: v_cmp_nlt_f16_e64 vcc, v1, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, v127, v255
+// W64: v_cmp_nlt_f16_e64 vcc, v127, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, vcc_hi, v255
+// W64: v_cmp_nlt_f16_e64 vcc, vcc_hi, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, vcc_lo, v255
+// W64: v_cmp_nlt_f16_e64 vcc, vcc_lo, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, v1, v255
+// W32: v_cmp_nlt_f16_e64 vcc_lo, v1, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, v127, v255
+// W32: v_cmp_nlt_f16_e64 vcc_lo, v127, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, vcc_hi, v255
+// W32: v_cmp_nlt_f16_e64 vcc_lo, vcc_hi, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, vcc_lo, v255
+// W32: v_cmp_nlt_f16_e64 vcc_lo, vcc_lo, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, v1, v255
+// W64: v_cmp_o_f16_e64 vcc, v1, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, v127, v255
+// W64: v_cmp_o_f16_e64 vcc, v127, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, vcc_hi, v255
+// W64: v_cmp_o_f16_e64 vcc, vcc_hi, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, vcc_lo, v255
+// W64: v_cmp_o_f16_e64 vcc, vcc_lo, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, v1, v255
+// W32: v_cmp_o_f16_e64 vcc_lo, v1, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, v127, v255
+// W32: v_cmp_o_f16_e64 vcc_lo, v127, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, vcc_hi, v255
+// W32: v_cmp_o_f16_e64 vcc_lo, vcc_hi, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, vcc_lo, v255
+// W32: v_cmp_o_f16_e64 vcc_lo, vcc_lo, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, v1, v255
+// W64: v_cmp_u_f16_e64 vcc, v1, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, v127, v255
+// W64: v_cmp_u_f16_e64 vcc, v127, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, vcc_hi, v255
+// W64: v_cmp_u_f16_e64 vcc, vcc_hi, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, vcc_lo, v255
+// W64: v_cmp_u_f16_e64 vcc, vcc_lo, v255
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, v1, v255
+// W32: v_cmp_u_f16_e64 vcc_lo, v1, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, v127, v255
+// W32: v_cmp_u_f16_e64 vcc_lo, v127, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, vcc_hi, v255
+// W32: v_cmp_u_f16_e64 vcc_lo, vcc_hi, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, vcc_lo, v255
+// W32: v_cmp_u_f16_e64 vcc_lo, vcc_lo, v255
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, v128, v2
+// W64: v_cmp_class_f16_e64 vcc, v128, v2
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc_lo, v128, v2
+// W32: v_cmp_class_f16_e64 vcc_lo, v128, v2
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v128, v2
+// W64: v_cmp_eq_f16_e64 vcc, v128, v2
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v128, v2
+// W32: v_cmp_eq_f16_e64 vcc_lo, v128, v2
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, v128, v2
+// W64: v_cmp_eq_i16_e64 vcc, v128, v2
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, v128, v2
+// W32: v_cmp_eq_i16_e64 vcc_lo, v128, v2
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, v128, v2
+// W64: v_cmp_eq_u16_e64 vcc, v128, v2
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, v128, v2
+// W32: v_cmp_eq_u16_e64 vcc_lo, v128, v2
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, v128, v2
+// W64: v_cmp_ge_f16_e64 vcc, v128, v2
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, v128, v2
+// W32: v_cmp_ge_f16_e64 vcc_lo, v128, v2
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, v128, v2
+// W64: v_cmp_ge_i16_e64 vcc, v128, v2
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, v128, v2
+// W32: v_cmp_ge_i16_e64 vcc_lo, v128, v2
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, v128, v2
+// W64: v_cmp_ge_u16_e64 vcc, v128, v2
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, v128, v2
+// W32: v_cmp_ge_u16_e64 vcc_lo, v128, v2
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, v128, v2
+// W64: v_cmp_gt_f16_e64 vcc, v128, v2
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, v128, v2
+// W32: v_cmp_gt_f16_e64 vcc_lo, v128, v2
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, v128, v2
+// W64: v_cmp_gt_i16_e64 vcc, v128, v2
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, v128, v2
+// W32: v_cmp_gt_i16_e64 vcc_lo, v128, v2
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, v128, v2
+// W64: v_cmp_gt_u16_e64 vcc, v128, v2
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, v128, v2
+// W32: v_cmp_gt_u16_e64 vcc_lo, v128, v2
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, v128, v2
+// W64: v_cmp_le_f16_e64 vcc, v128, v2
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, v128, v2
+// W32: v_cmp_le_f16_e64 vcc_lo, v128, v2
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, v128, v2
+// W64: v_cmp_le_i16_e64 vcc, v128, v2
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, v128, v2
+// W32: v_cmp_le_i16_e64 vcc_lo, v128, v2
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, v128, v2
+// W64: v_cmp_le_u16_e64 vcc, v128, v2
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, v128, v2
+// W32: v_cmp_le_u16_e64 vcc_lo, v128, v2
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, v128, v2
+// W64: v_cmp_lg_f16_e64 vcc, v128, v2
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, v128, v2
+// W32: v_cmp_lg_f16_e64 vcc_lo, v128, v2
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, v128, v2
+// W64: v_cmp_lt_f16_e64 vcc, v128, v2
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, v128, v2
+// W32: v_cmp_lt_f16_e64 vcc_lo, v128, v2
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, v128, v2
+// W64: v_cmp_lt_i16_e64 vcc, v128, v2
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, v128, v2
+// W32: v_cmp_lt_i16_e64 vcc_lo, v128, v2
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, v128, v2
+// W64: v_cmp_lt_u16_e64 vcc, v128, v2
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, v128, v2
+// W32: v_cmp_lt_u16_e64 vcc_lo, v128, v2
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, v128, v2
+// W64: v_cmp_ne_i16_e64 vcc, v128, v2
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, v128, v2
+// W32: v_cmp_ne_i16_e64 vcc_lo, v128, v2
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, v128, v2
+// W64: v_cmp_ne_u16_e64 vcc, v128, v2
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, v128, v2
+// W32: v_cmp_ne_u16_e64 vcc_lo, v128, v2
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, v128, v2
+// W64: v_cmp_neq_f16_e64 vcc, v128, v2
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, v128, v2
+// W32: v_cmp_neq_f16_e64 vcc_lo, v128, v2
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, v128, v2
+// W64: v_cmp_nge_f16_e64 vcc, v128, v2
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, v128, v2
+// W32: v_cmp_nge_f16_e64 vcc_lo, v128, v2
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, v128, v2
+// W64: v_cmp_ngt_f16_e64 vcc, v128, v2
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, v128, v2
+// W32: v_cmp_ngt_f16_e64 vcc_lo, v128, v2
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, v128, v2
+// W64: v_cmp_nle_f16_e64 vcc, v128, v2
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, v128, v2
+// W32: v_cmp_nle_f16_e64 vcc_lo, v128, v2
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, v128, v2
+// W64: v_cmp_nlg_f16_e64 vcc, v128, v2
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, v128, v2
+// W32: v_cmp_nlg_f16_e64 vcc_lo, v128, v2
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, v128, v2
+// W64: v_cmp_nlt_f16_e64 vcc, v128, v2
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, v128, v2
+// W32: v_cmp_nlt_f16_e64 vcc_lo, v128, v2
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, v128, v2
+// W64: v_cmp_o_f16_e64 vcc, v128, v2
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, v128, v2
+// W32: v_cmp_o_f16_e64 vcc_lo, v128, v2
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, v128, v2
+// W64: v_cmp_u_f16_e64 vcc, v128, v2
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, v128, v2
+// W32: v_cmp_u_f16_e64 vcc_lo, v128, v2
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, v1, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_class_f16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16 vcc, v127, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_class_f16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_class_f16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc, v1, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc, v127, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16 vcc, v1, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_eq_i16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16 vcc, v127, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_eq_i16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_eq_i16_e64_dpp vcc_lo, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_eq_i16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16 vcc, v1, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_eq_u16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16 vcc, v127, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_eq_u16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_eq_u16_e64_dpp vcc_lo, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_eq_u16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16 vcc, v1, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_ge_f16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16 vcc, v127, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_ge_f16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_ge_f16_e64_dpp vcc_lo, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_ge_f16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16 vcc, v1, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_ge_i16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16 vcc, v127, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_ge_i16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_ge_i16_e64_dpp vcc_lo, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_ge_i16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16 vcc, v1, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_ge_u16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16 vcc, v127, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_ge_u16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_ge_u16_e64_dpp vcc_lo, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_ge_u16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16 vcc, v1, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_gt_f16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16 vcc, v127, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_gt_f16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_gt_f16_e64_dpp vcc_lo, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_gt_f16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16 vcc, v1, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_gt_i16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16 vcc, v127, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_gt_i16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_gt_i16_e64_dpp vcc_lo, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_gt_i16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16 vcc, v1, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_gt_u16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16 vcc, v127, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_gt_u16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_gt_u16_e64_dpp vcc_lo, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_gt_u16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16 vcc, v1, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_le_f16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16 vcc, v127, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_le_f16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_le_f16_e64_dpp vcc_lo, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_le_f16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16 vcc, v1, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_le_i16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16 vcc, v127, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_le_i16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_le_i16_e64_dpp vcc_lo, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_le_i16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16 vcc, v1, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_le_u16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16 vcc, v127, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_le_u16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_le_u16_e64_dpp vcc_lo, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_le_u16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16 vcc, v1, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_lg_f16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16 vcc, v127, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_lg_f16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_lg_f16_e64_dpp vcc_lo, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_lg_f16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16 vcc, v1, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_lt_f16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16 vcc, v127, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_lt_f16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16 vcc, v1, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_lt_i16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16 vcc, v127, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_lt_i16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_lt_i16_e64_dpp vcc_lo, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_lt_i16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16 vcc, v1, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_lt_u16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16 vcc, v127, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_lt_u16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_lt_u16_e64_dpp vcc_lo, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_lt_u16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16 vcc, v1, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_ne_i16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16 vcc, v127, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_ne_i16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_ne_i16_e64_dpp vcc_lo, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_ne_i16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16 vcc, v1, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_ne_u16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16 vcc, v127, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_ne_u16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_ne_u16_e64_dpp vcc_lo, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_ne_u16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16 vcc, v1, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_neq_f16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16 vcc, v127, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_neq_f16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_neq_f16_e64_dpp vcc_lo, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_neq_f16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16 vcc, v1, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_nge_f16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16 vcc, v127, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_nge_f16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_nge_f16_e64_dpp vcc_lo, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_nge_f16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16 vcc, v1, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_ngt_f16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16 vcc, v127, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_ngt_f16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_ngt_f16_e64_dpp vcc_lo, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_ngt_f16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16 vcc, v1, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_nle_f16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16 vcc, v127, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_nle_f16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_nle_f16_e64_dpp vcc_lo, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_nle_f16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16 vcc, v1, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_nlg_f16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16 vcc, v127, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_nlg_f16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_nlg_f16_e64_dpp vcc_lo, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_nlg_f16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16 vcc, v1, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_nlt_f16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16 vcc, v127, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_nlt_f16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_nlt_f16_e64_dpp vcc_lo, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_nlt_f16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16 vcc, v1, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_o_f16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16 vcc, v127, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_o_f16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_o_f16_e64_dpp vcc_lo, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_o_f16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16 vcc, v1, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_u_f16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16 vcc, v127, v255 quad_perm:[3,2,1,0]
+// W64: v_cmp_u_f16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_u_f16_e64_dpp vcc_lo, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
+// W32: v_cmp_u_f16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16 vcc, v128, v2 quad_perm:[3,2,1,0]
+// W64: v_cmp_class_f16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// W32: v_cmp_class_f16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc, v128, v2 quad_perm:[3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16 vcc, v128, v2 quad_perm:[3,2,1,0]
+// W64: v_cmp_eq_i16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// W32: v_cmp_eq_i16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16 vcc, v128, v2 quad_perm:[3,2,1,0]
+// W64: v_cmp_eq_u16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// W32: v_cmp_eq_u16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16 vcc, v128, v2 quad_perm:[3,2,1,0]
+// W64: v_cmp_ge_f16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// W32: v_cmp_ge_f16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16 vcc, v128, v2 quad_perm:[3,2,1,0]
+// W64: v_cmp_ge_i16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// W32: v_cmp_ge_i16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16 vcc, v128, v2 quad_perm:[3,2,1,0]
+// W64: v_cmp_ge_u16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// W32: v_cmp_ge_u16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16 vcc, v128, v2 quad_perm:[3,2,1,0]
+// W64: v_cmp_gt_f16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// W32: v_cmp_gt_f16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16 vcc, v128, v2 quad_perm:[3,2,1,0]
+// W64: v_cmp_gt_i16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// W32: v_cmp_gt_i16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16 vcc, v128, v2 quad_perm:[3,2,1,0]
+// W64: v_cmp_gt_u16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// W32: v_cmp_gt_u16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16 vcc, v128, v2 quad_perm:[3,2,1,0]
+// W64: v_cmp_le_f16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// W32: v_cmp_le_f16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16 vcc, v128, v2 quad_perm:[3,2,1,0]
+// W64: v_cmp_le_i16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// W32: v_cmp_le_i16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16 vcc, v128, v2 quad_perm:[3,2,1,0]
+// W64: v_cmp_le_u16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// W32: v_cmp_le_u16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16 vcc, v128, v2 quad_perm:[3,2,1,0]
+// W64: v_cmp_lg_f16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// W32: v_cmp_lg_f16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16 vcc, v128, v2 quad_perm:[3,2,1,0]
+// W64: v_cmp_lt_f16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16 vcc, v128, v2 quad_perm:[3,2,1,0]
+// W64: v_cmp_lt_i16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// W32: v_cmp_lt_i16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16 vcc, v128, v2 quad_perm:[3,2,1,0]
+// W64: v_cmp_lt_u16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// W32: v_cmp_lt_u16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16 vcc, v128, v2 quad_perm:[3,2,1,0]
+// W64: v_cmp_ne_i16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// W32: v_cmp_ne_i16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16 vcc, v128, v2 quad_perm:[3,2,1,0]
+// W64: v_cmp_ne_u16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// W32: v_cmp_ne_u16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16 vcc, v128, v2 quad_perm:[3,2,1,0]
+// W64: v_cmp_neq_f16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// W32: v_cmp_neq_f16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16 vcc, v128, v2 quad_perm:[3,2,1,0]
+// W64: v_cmp_nge_f16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// W32: v_cmp_nge_f16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16 vcc, v128, v2 quad_perm:[3,2,1,0]
+// W64: v_cmp_ngt_f16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// W32: v_cmp_ngt_f16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16 vcc, v128, v2 quad_perm:[3,2,1,0]
+// W64: v_cmp_nle_f16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// W32: v_cmp_nle_f16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16 vcc, v128, v2 quad_perm:[3,2,1,0]
+// W64: v_cmp_nlg_f16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// W32: v_cmp_nlg_f16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16 vcc, v128, v2 quad_perm:[3,2,1,0]
+// W64: v_cmp_nlt_f16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// W32: v_cmp_nlt_f16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16 vcc, v128, v2 quad_perm:[3,2,1,0]
+// W64: v_cmp_o_f16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// W32: v_cmp_o_f16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16 vcc, v128, v2 quad_perm:[3,2,1,0]
+// W64: v_cmp_u_f16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
+// W32: v_cmp_u_f16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_class_f16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_class_f16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_class_f16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_eq_i16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_eq_i16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_i16_e64_dpp vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_i16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_eq_u16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_eq_u16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_u16_e64_dpp vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_u16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_ge_f16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_ge_f16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_ge_f16_e64_dpp vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_ge_f16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_ge_i16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_ge_i16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_ge_i16_e64_dpp vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_ge_i16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_ge_u16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_ge_u16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_ge_u16_e64_dpp vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_ge_u16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_gt_f16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_gt_f16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_gt_f16_e64_dpp vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_gt_f16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_gt_i16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_gt_i16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_gt_i16_e64_dpp vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_gt_i16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_gt_u16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_gt_u16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_gt_u16_e64_dpp vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_gt_u16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_le_f16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_le_f16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_le_f16_e64_dpp vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_le_f16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_le_i16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_le_i16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_le_i16_e64_dpp vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_le_i16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_le_u16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_le_u16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_le_u16_e64_dpp vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_le_u16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_lg_f16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_lg_f16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_lg_f16_e64_dpp vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_lg_f16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_lt_f16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_lt_f16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_lt_i16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_lt_i16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_lt_i16_e64_dpp vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_lt_i16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_lt_u16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_lt_u16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_lt_u16_e64_dpp vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_lt_u16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_ne_i16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_ne_i16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_ne_i16_e64_dpp vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_ne_i16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_ne_u16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_ne_u16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_ne_u16_e64_dpp vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_ne_u16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_neq_f16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_neq_f16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_neq_f16_e64_dpp vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_neq_f16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_nge_f16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_nge_f16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_nge_f16_e64_dpp vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_nge_f16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_ngt_f16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_ngt_f16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_ngt_f16_e64_dpp vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_ngt_f16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_nle_f16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_nle_f16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_nle_f16_e64_dpp vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_nle_f16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_nlg_f16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_nlg_f16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_nlg_f16_e64_dpp vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_nlg_f16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_nlt_f16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_nlt_f16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_nlt_f16_e64_dpp vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_nlt_f16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_o_f16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_o_f16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_o_f16_e64_dpp vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_o_f16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_u_f16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_u_f16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_u_f16_e64_dpp vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_u_f16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_class_f16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_class_f16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_eq_i16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_i16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_eq_u16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_u16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_ge_f16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_ge_f16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_ge_i16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_ge_i16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_ge_u16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_ge_u16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_gt_f16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_gt_f16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_gt_i16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_gt_i16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_gt_u16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_gt_u16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_le_f16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_le_f16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_le_i16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_le_i16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_le_u16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_le_u16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_lg_f16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_lg_f16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_lt_f16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_lt_i16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_lt_i16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_lt_u16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_lt_u16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_ne_i16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_ne_i16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_ne_u16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_ne_u16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_neq_f16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_neq_f16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_nge_f16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_nge_f16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_ngt_f16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_ngt_f16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_nle_f16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_nle_f16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_nlg_f16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_nlg_f16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_nlt_f16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_nlt_f16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_o_f16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_o_f16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_u_f16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_u_f16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopcx.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopcx.s
new file mode 100644
index 000000000000..73fee99592a1
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopcx.s
@@ -0,0 +1,3404 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
+
+v_cmpx_class_f16_e32 v1, v2
+// GFX12: encoding: [0x01,0x05,0xfa,0x7d]
+
+v_cmpx_class_f16 v127, v2
+// GFX12: encoding: [0x7f,0x05,0xfa,0x7d]
+
+v_cmpx_class_f16 s1, v2
+// GFX12: encoding: [0x01,0x04,0xfa,0x7d]
+
+v_cmpx_class_f16 s105, v2
+// GFX12: encoding: [0x69,0x04,0xfa,0x7d]
+
+v_cmpx_class_f16 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0xfa,0x7d]
+
+v_cmpx_class_f16 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0xfa,0x7d]
+
+v_cmpx_class_f16 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0xfa,0x7d]
+
+v_cmpx_class_f16 m0, v2
+// GFX12: encoding: [0x7d,0x04,0xfa,0x7d]
+
+v_cmpx_class_f16 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0xfa,0x7d]
+
+v_cmpx_class_f16 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0xfa,0x7d]
+
+v_cmpx_class_f16 null, v2
+// GFX12: encoding: [0x7c,0x04,0xfa,0x7d]
+
+v_cmpx_class_f16 -1, v2
+// GFX12: encoding: [0xc1,0x04,0xfa,0x7d]
+
+v_cmpx_class_f16 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0xfa,0x7d]
+
+v_cmpx_class_f16 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0xfa,0x7d]
+
+v_cmpx_class_f16 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0xfa,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_class_f32 v1, v2
+// GFX12: encoding: [0x01,0x05,0xfc,0x7d]
+
+v_cmpx_class_f32 v255, v2
+// GFX12: encoding: [0xff,0x05,0xfc,0x7d]
+
+v_cmpx_class_f32 s1, v2
+// GFX12: encoding: [0x01,0x04,0xfc,0x7d]
+
+v_cmpx_class_f32 s105, v2
+// GFX12: encoding: [0x69,0x04,0xfc,0x7d]
+
+v_cmpx_class_f32 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0xfc,0x7d]
+
+v_cmpx_class_f32 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0xfc,0x7d]
+
+v_cmpx_class_f32 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0xfc,0x7d]
+
+v_cmpx_class_f32 m0, v2
+// GFX12: encoding: [0x7d,0x04,0xfc,0x7d]
+
+v_cmpx_class_f32 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0xfc,0x7d]
+
+v_cmpx_class_f32 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0xfc,0x7d]
+
+v_cmpx_class_f32 null, v2
+// GFX12: encoding: [0x7c,0x04,0xfc,0x7d]
+
+v_cmpx_class_f32 -1, v2
+// GFX12: encoding: [0xc1,0x04,0xfc,0x7d]
+
+v_cmpx_class_f32 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0xfc,0x7d]
+
+v_cmpx_class_f32 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0xfc,0x7d]
+
+v_cmpx_class_f32 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xfd,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_class_f64 v[1:2], v2
+// GFX12: encoding: [0x01,0x05,0xfe,0x7d]
+
+v_cmpx_class_f64 v[254:255], v2
+// GFX12: encoding: [0xfe,0x05,0xfe,0x7d]
+
+v_cmpx_class_f64 s[2:3], v2
+// GFX12: encoding: [0x02,0x04,0xfe,0x7d]
+
+v_cmpx_class_f64 s[104:105], v2
+// GFX12: encoding: [0x68,0x04,0xfe,0x7d]
+
+v_cmpx_class_f64 vcc, v2
+// GFX12: encoding: [0x6a,0x04,0xfe,0x7d]
+
+v_cmpx_class_f64 ttmp[14:15], v2
+// GFX12: encoding: [0x7a,0x04,0xfe,0x7d]
+
+v_cmpx_class_f64 exec, v2
+// GFX12: encoding: [0x7e,0x04,0xfe,0x7d]
+
+v_cmpx_class_f64 null, v2
+// GFX12: encoding: [0x7c,0x04,0xfe,0x7d]
+
+v_cmpx_class_f64 -1, v2
+// GFX12: encoding: [0xc1,0x04,0xfe,0x7d]
+
+v_cmpx_class_f64 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0xfe,0x7d]
+
+v_cmpx_class_f64 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0xfe,0x7d]
+
+v_cmpx_class_f64 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xff,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_f16 v1, v2
+// GFX12: encoding: [0x01,0x05,0x04,0x7d]
+
+v_cmpx_eq_f16 v127, v2
+// GFX12: encoding: [0x7f,0x05,0x04,0x7d]
+
+v_cmpx_eq_f16 s1, v2
+// GFX12: encoding: [0x01,0x04,0x04,0x7d]
+
+v_cmpx_eq_f16 s105, v2
+// GFX12: encoding: [0x69,0x04,0x04,0x7d]
+
+v_cmpx_eq_f16 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x04,0x7d]
+
+v_cmpx_eq_f16 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x04,0x7d]
+
+v_cmpx_eq_f16 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x04,0x7d]
+
+v_cmpx_eq_f16 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x04,0x7d]
+
+v_cmpx_eq_f16 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x04,0x7d]
+
+v_cmpx_eq_f16 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x04,0x7d]
+
+v_cmpx_eq_f16 null, v2
+// GFX12: encoding: [0x7c,0x04,0x04,0x7d]
+
+v_cmpx_eq_f16 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x04,0x7d]
+
+v_cmpx_eq_f16 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x04,0x7d]
+
+v_cmpx_eq_f16 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x04,0x7d]
+
+v_cmpx_eq_f16 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0x04,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_eq_f32 v1, v2
+// GFX12: encoding: [0x01,0x05,0x24,0x7d]
+
+v_cmpx_eq_f32 v255, v2
+// GFX12: encoding: [0xff,0x05,0x24,0x7d]
+
+v_cmpx_eq_f32 s1, v2
+// GFX12: encoding: [0x01,0x04,0x24,0x7d]
+
+v_cmpx_eq_f32 s105, v2
+// GFX12: encoding: [0x69,0x04,0x24,0x7d]
+
+v_cmpx_eq_f32 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x24,0x7d]
+
+v_cmpx_eq_f32 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x24,0x7d]
+
+v_cmpx_eq_f32 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x24,0x7d]
+
+v_cmpx_eq_f32 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x24,0x7d]
+
+v_cmpx_eq_f32 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x24,0x7d]
+
+v_cmpx_eq_f32 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x24,0x7d]
+
+v_cmpx_eq_f32 null, v2
+// GFX12: encoding: [0x7c,0x04,0x24,0x7d]
+
+v_cmpx_eq_f32 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x24,0x7d]
+
+v_cmpx_eq_f32 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x24,0x7d]
+
+v_cmpx_eq_f32 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x24,0x7d]
+
+v_cmpx_eq_f32 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x25,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_f64 v[1:2], v[2:3]
+// GFX12: encoding: [0x01,0x05,0x44,0x7d]
+
+v_cmpx_eq_f64 v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0x44,0x7d]
+
+v_cmpx_eq_f64 s[2:3], v[2:3]
+// GFX12: encoding: [0x02,0x04,0x44,0x7d]
+
+v_cmpx_eq_f64 s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0x44,0x7d]
+
+v_cmpx_eq_f64 vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0x44,0x7d]
+
+v_cmpx_eq_f64 ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0x44,0x7d]
+
+v_cmpx_eq_f64 exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0x44,0x7d]
+
+v_cmpx_eq_f64 null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0x44,0x7d]
+
+v_cmpx_eq_f64 -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0x44,0x7d]
+
+v_cmpx_eq_f64 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0x44,0x7d]
+
+v_cmpx_eq_f64 src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0x44,0x7d]
+
+v_cmpx_eq_f64 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0x45,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_i16 v1, v2
+// GFX12: encoding: [0x01,0x05,0x64,0x7d]
+
+v_cmpx_eq_i16 v127, v2
+// GFX12: encoding: [0x7f,0x05,0x64,0x7d]
+
+v_cmpx_eq_i16 s1, v2
+// GFX12: encoding: [0x01,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 s105, v2
+// GFX12: encoding: [0x69,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 null, v2
+// GFX12: encoding: [0x7c,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 0.5, v2
+// GFX12: encoding: [0xff,0x04,0x64,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_eq_i16 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0x64,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_eq_i32 v1, v2
+// GFX12: encoding: [0x01,0x05,0x84,0x7d]
+
+v_cmpx_eq_i32 v255, v2
+// GFX12: encoding: [0xff,0x05,0x84,0x7d]
+
+v_cmpx_eq_i32 s1, v2
+// GFX12: encoding: [0x01,0x04,0x84,0x7d]
+
+v_cmpx_eq_i32 s105, v2
+// GFX12: encoding: [0x69,0x04,0x84,0x7d]
+
+v_cmpx_eq_i32 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x84,0x7d]
+
+v_cmpx_eq_i32 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x84,0x7d]
+
+v_cmpx_eq_i32 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x84,0x7d]
+
+v_cmpx_eq_i32 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x84,0x7d]
+
+v_cmpx_eq_i32 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x84,0x7d]
+
+v_cmpx_eq_i32 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x84,0x7d]
+
+v_cmpx_eq_i32 null, v2
+// GFX12: encoding: [0x7c,0x04,0x84,0x7d]
+
+v_cmpx_eq_i32 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x84,0x7d]
+
+v_cmpx_eq_i32 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x84,0x7d]
+
+v_cmpx_eq_i32 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x84,0x7d]
+
+v_cmpx_eq_i32 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x85,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_i64 v[1:2], v[2:3]
+// GFX12: encoding: [0x01,0x05,0xa4,0x7d]
+
+v_cmpx_eq_i64 v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0xa4,0x7d]
+
+v_cmpx_eq_i64 s[2:3], v[2:3]
+// GFX12: encoding: [0x02,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i64 s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i64 vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i64 ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i64 exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i64 null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i64 -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i64 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i64 src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i64 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0xa5,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_u16 v1, v2
+// GFX12: encoding: [0x01,0x05,0x74,0x7d]
+
+v_cmpx_eq_u16 v127, v2
+// GFX12: encoding: [0x7f,0x05,0x74,0x7d]
+
+v_cmpx_eq_u16 s1, v2
+// GFX12: encoding: [0x01,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 s105, v2
+// GFX12: encoding: [0x69,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 null, v2
+// GFX12: encoding: [0x7c,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 0.5, v2
+// GFX12: encoding: [0xff,0x04,0x74,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_eq_u16 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0x74,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_eq_u32 v1, v2
+// GFX12: encoding: [0x01,0x05,0x94,0x7d]
+
+v_cmpx_eq_u32 v255, v2
+// GFX12: encoding: [0xff,0x05,0x94,0x7d]
+
+v_cmpx_eq_u32 s1, v2
+// GFX12: encoding: [0x01,0x04,0x94,0x7d]
+
+v_cmpx_eq_u32 s105, v2
+// GFX12: encoding: [0x69,0x04,0x94,0x7d]
+
+v_cmpx_eq_u32 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x94,0x7d]
+
+v_cmpx_eq_u32 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x94,0x7d]
+
+v_cmpx_eq_u32 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x94,0x7d]
+
+v_cmpx_eq_u32 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x94,0x7d]
+
+v_cmpx_eq_u32 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x94,0x7d]
+
+v_cmpx_eq_u32 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x94,0x7d]
+
+v_cmpx_eq_u32 null, v2
+// GFX12: encoding: [0x7c,0x04,0x94,0x7d]
+
+v_cmpx_eq_u32 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x94,0x7d]
+
+v_cmpx_eq_u32 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x94,0x7d]
+
+v_cmpx_eq_u32 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x94,0x7d]
+
+v_cmpx_eq_u32 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x95,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_u64 v[1:2], v[2:3]
+// GFX12: encoding: [0x01,0x05,0xb4,0x7d]
+
+v_cmpx_eq_u64 v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0xb4,0x7d]
+
+v_cmpx_eq_u64 s[2:3], v[2:3]
+// GFX12: encoding: [0x02,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u64 s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u64 vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u64 ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u64 exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u64 null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u64 -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u64 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u64 src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u64 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0xb5,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_f16 v1, v2
+// GFX12: encoding: [0x01,0x05,0x0c,0x7d]
+
+v_cmpx_ge_f16 v127, v2
+// GFX12: encoding: [0x7f,0x05,0x0c,0x7d]
+
+v_cmpx_ge_f16 s1, v2
+// GFX12: encoding: [0x01,0x04,0x0c,0x7d]
+
+v_cmpx_ge_f16 s105, v2
+// GFX12: encoding: [0x69,0x04,0x0c,0x7d]
+
+v_cmpx_ge_f16 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0c,0x7d]
+
+v_cmpx_ge_f16 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0c,0x7d]
+
+v_cmpx_ge_f16 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0c,0x7d]
+
+v_cmpx_ge_f16 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0c,0x7d]
+
+v_cmpx_ge_f16 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0c,0x7d]
+
+v_cmpx_ge_f16 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0c,0x7d]
+
+v_cmpx_ge_f16 null, v2
+// GFX12: encoding: [0x7c,0x04,0x0c,0x7d]
+
+v_cmpx_ge_f16 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0c,0x7d]
+
+v_cmpx_ge_f16 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0c,0x7d]
+
+v_cmpx_ge_f16 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0c,0x7d]
+
+v_cmpx_ge_f16 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0x0c,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ge_f32 v1, v2
+// GFX12: encoding: [0x01,0x05,0x2c,0x7d]
+
+v_cmpx_ge_f32 v255, v2
+// GFX12: encoding: [0xff,0x05,0x2c,0x7d]
+
+v_cmpx_ge_f32 s1, v2
+// GFX12: encoding: [0x01,0x04,0x2c,0x7d]
+
+v_cmpx_ge_f32 s105, v2
+// GFX12: encoding: [0x69,0x04,0x2c,0x7d]
+
+v_cmpx_ge_f32 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x2c,0x7d]
+
+v_cmpx_ge_f32 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x2c,0x7d]
+
+v_cmpx_ge_f32 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x2c,0x7d]
+
+v_cmpx_ge_f32 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x2c,0x7d]
+
+v_cmpx_ge_f32 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x2c,0x7d]
+
+v_cmpx_ge_f32 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x2c,0x7d]
+
+v_cmpx_ge_f32 null, v2
+// GFX12: encoding: [0x7c,0x04,0x2c,0x7d]
+
+v_cmpx_ge_f32 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x2c,0x7d]
+
+v_cmpx_ge_f32 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x2c,0x7d]
+
+v_cmpx_ge_f32 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x2c,0x7d]
+
+v_cmpx_ge_f32 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x2d,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_f64 v[1:2], v[2:3]
+// GFX12: encoding: [0x01,0x05,0x4c,0x7d]
+
+v_cmpx_ge_f64 v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0x4c,0x7d]
+
+v_cmpx_ge_f64 s[2:3], v[2:3]
+// GFX12: encoding: [0x02,0x04,0x4c,0x7d]
+
+v_cmpx_ge_f64 s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0x4c,0x7d]
+
+v_cmpx_ge_f64 vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0x4c,0x7d]
+
+v_cmpx_ge_f64 ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0x4c,0x7d]
+
+v_cmpx_ge_f64 exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0x4c,0x7d]
+
+v_cmpx_ge_f64 null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0x4c,0x7d]
+
+v_cmpx_ge_f64 -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0x4c,0x7d]
+
+v_cmpx_ge_f64 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0x4c,0x7d]
+
+v_cmpx_ge_f64 src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0x4c,0x7d]
+
+v_cmpx_ge_f64 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0x4d,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_i16 v1, v2
+// GFX12: encoding: [0x01,0x05,0x6c,0x7d]
+
+v_cmpx_ge_i16 v127, v2
+// GFX12: encoding: [0x7f,0x05,0x6c,0x7d]
+
+v_cmpx_ge_i16 s1, v2
+// GFX12: encoding: [0x01,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 s105, v2
+// GFX12: encoding: [0x69,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 null, v2
+// GFX12: encoding: [0x7c,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 0.5, v2
+// GFX12: encoding: [0xff,0x04,0x6c,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_ge_i16 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0x6c,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ge_i32 v1, v2
+// GFX12: encoding: [0x01,0x05,0x8c,0x7d]
+
+v_cmpx_ge_i32 v255, v2
+// GFX12: encoding: [0xff,0x05,0x8c,0x7d]
+
+v_cmpx_ge_i32 s1, v2
+// GFX12: encoding: [0x01,0x04,0x8c,0x7d]
+
+v_cmpx_ge_i32 s105, v2
+// GFX12: encoding: [0x69,0x04,0x8c,0x7d]
+
+v_cmpx_ge_i32 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x8c,0x7d]
+
+v_cmpx_ge_i32 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x8c,0x7d]
+
+v_cmpx_ge_i32 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x8c,0x7d]
+
+v_cmpx_ge_i32 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x8c,0x7d]
+
+v_cmpx_ge_i32 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x8c,0x7d]
+
+v_cmpx_ge_i32 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x8c,0x7d]
+
+v_cmpx_ge_i32 null, v2
+// GFX12: encoding: [0x7c,0x04,0x8c,0x7d]
+
+v_cmpx_ge_i32 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x8c,0x7d]
+
+v_cmpx_ge_i32 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x8c,0x7d]
+
+v_cmpx_ge_i32 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x8c,0x7d]
+
+v_cmpx_ge_i32 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x8d,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_i64 v[1:2], v[2:3]
+// GFX12: encoding: [0x01,0x05,0xac,0x7d]
+
+v_cmpx_ge_i64 v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0xac,0x7d]
+
+v_cmpx_ge_i64 s[2:3], v[2:3]
+// GFX12: encoding: [0x02,0x04,0xac,0x7d]
+
+v_cmpx_ge_i64 s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0xac,0x7d]
+
+v_cmpx_ge_i64 vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0xac,0x7d]
+
+v_cmpx_ge_i64 ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0xac,0x7d]
+
+v_cmpx_ge_i64 exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0xac,0x7d]
+
+v_cmpx_ge_i64 null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0xac,0x7d]
+
+v_cmpx_ge_i64 -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0xac,0x7d]
+
+v_cmpx_ge_i64 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0xac,0x7d]
+
+v_cmpx_ge_i64 src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0xac,0x7d]
+
+v_cmpx_ge_i64 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0xad,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_u16 v1, v2
+// GFX12: encoding: [0x01,0x05,0x7c,0x7d]
+
+v_cmpx_ge_u16 v127, v2
+// GFX12: encoding: [0x7f,0x05,0x7c,0x7d]
+
+v_cmpx_ge_u16 s1, v2
+// GFX12: encoding: [0x01,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 s105, v2
+// GFX12: encoding: [0x69,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 null, v2
+// GFX12: encoding: [0x7c,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 0.5, v2
+// GFX12: encoding: [0xff,0x04,0x7c,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_ge_u16 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0x7c,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ge_u32 v1, v2
+// GFX12: encoding: [0x01,0x05,0x9c,0x7d]
+
+v_cmpx_ge_u32 v255, v2
+// GFX12: encoding: [0xff,0x05,0x9c,0x7d]
+
+v_cmpx_ge_u32 s1, v2
+// GFX12: encoding: [0x01,0x04,0x9c,0x7d]
+
+v_cmpx_ge_u32 s105, v2
+// GFX12: encoding: [0x69,0x04,0x9c,0x7d]
+
+v_cmpx_ge_u32 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x9c,0x7d]
+
+v_cmpx_ge_u32 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x9c,0x7d]
+
+v_cmpx_ge_u32 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x9c,0x7d]
+
+v_cmpx_ge_u32 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x9c,0x7d]
+
+v_cmpx_ge_u32 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x9c,0x7d]
+
+v_cmpx_ge_u32 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x9c,0x7d]
+
+v_cmpx_ge_u32 null, v2
+// GFX12: encoding: [0x7c,0x04,0x9c,0x7d]
+
+v_cmpx_ge_u32 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x9c,0x7d]
+
+v_cmpx_ge_u32 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x9c,0x7d]
+
+v_cmpx_ge_u32 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x9c,0x7d]
+
+v_cmpx_ge_u32 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x9d,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_u64 v[1:2], v[2:3]
+// GFX12: encoding: [0x01,0x05,0xbc,0x7d]
+
+v_cmpx_ge_u64 v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0xbc,0x7d]
+
+v_cmpx_ge_u64 s[2:3], v[2:3]
+// GFX12: encoding: [0x02,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u64 s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u64 vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u64 ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u64 exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u64 null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u64 -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u64 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u64 src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u64 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0xbd,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_f16 v1, v2
+// GFX12: encoding: [0x01,0x05,0x08,0x7d]
+
+v_cmpx_gt_f16 v127, v2
+// GFX12: encoding: [0x7f,0x05,0x08,0x7d]
+
+v_cmpx_gt_f16 s1, v2
+// GFX12: encoding: [0x01,0x04,0x08,0x7d]
+
+v_cmpx_gt_f16 s105, v2
+// GFX12: encoding: [0x69,0x04,0x08,0x7d]
+
+v_cmpx_gt_f16 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x08,0x7d]
+
+v_cmpx_gt_f16 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x08,0x7d]
+
+v_cmpx_gt_f16 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x08,0x7d]
+
+v_cmpx_gt_f16 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x08,0x7d]
+
+v_cmpx_gt_f16 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x08,0x7d]
+
+v_cmpx_gt_f16 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x08,0x7d]
+
+v_cmpx_gt_f16 null, v2
+// GFX12: encoding: [0x7c,0x04,0x08,0x7d]
+
+v_cmpx_gt_f16 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x08,0x7d]
+
+v_cmpx_gt_f16 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x08,0x7d]
+
+v_cmpx_gt_f16 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x08,0x7d]
+
+v_cmpx_gt_f16 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0x08,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_gt_f32 v1, v2
+// GFX12: encoding: [0x01,0x05,0x28,0x7d]
+
+v_cmpx_gt_f32 v255, v2
+// GFX12: encoding: [0xff,0x05,0x28,0x7d]
+
+v_cmpx_gt_f32 s1, v2
+// GFX12: encoding: [0x01,0x04,0x28,0x7d]
+
+v_cmpx_gt_f32 s105, v2
+// GFX12: encoding: [0x69,0x04,0x28,0x7d]
+
+v_cmpx_gt_f32 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x28,0x7d]
+
+v_cmpx_gt_f32 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x28,0x7d]
+
+v_cmpx_gt_f32 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x28,0x7d]
+
+v_cmpx_gt_f32 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x28,0x7d]
+
+v_cmpx_gt_f32 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x28,0x7d]
+
+v_cmpx_gt_f32 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x28,0x7d]
+
+v_cmpx_gt_f32 null, v2
+// GFX12: encoding: [0x7c,0x04,0x28,0x7d]
+
+v_cmpx_gt_f32 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x28,0x7d]
+
+v_cmpx_gt_f32 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x28,0x7d]
+
+v_cmpx_gt_f32 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x28,0x7d]
+
+v_cmpx_gt_f32 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x29,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_f64 v[1:2], v[2:3]
+// GFX12: encoding: [0x01,0x05,0x48,0x7d]
+
+v_cmpx_gt_f64 v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0x48,0x7d]
+
+v_cmpx_gt_f64 s[2:3], v[2:3]
+// GFX12: encoding: [0x02,0x04,0x48,0x7d]
+
+v_cmpx_gt_f64 s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0x48,0x7d]
+
+v_cmpx_gt_f64 vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0x48,0x7d]
+
+v_cmpx_gt_f64 ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0x48,0x7d]
+
+v_cmpx_gt_f64 exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0x48,0x7d]
+
+v_cmpx_gt_f64 null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0x48,0x7d]
+
+v_cmpx_gt_f64 -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0x48,0x7d]
+
+v_cmpx_gt_f64 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0x48,0x7d]
+
+v_cmpx_gt_f64 src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0x48,0x7d]
+
+v_cmpx_gt_f64 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0x49,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_i16 v1, v2
+// GFX12: encoding: [0x01,0x05,0x68,0x7d]
+
+v_cmpx_gt_i16 v127, v2
+// GFX12: encoding: [0x7f,0x05,0x68,0x7d]
+
+v_cmpx_gt_i16 s1, v2
+// GFX12: encoding: [0x01,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 s105, v2
+// GFX12: encoding: [0x69,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 null, v2
+// GFX12: encoding: [0x7c,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 0.5, v2
+// GFX12: encoding: [0xff,0x04,0x68,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_gt_i16 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0x68,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_gt_i32 v1, v2
+// GFX12: encoding: [0x01,0x05,0x88,0x7d]
+
+v_cmpx_gt_i32 v255, v2
+// GFX12: encoding: [0xff,0x05,0x88,0x7d]
+
+v_cmpx_gt_i32 s1, v2
+// GFX12: encoding: [0x01,0x04,0x88,0x7d]
+
+v_cmpx_gt_i32 s105, v2
+// GFX12: encoding: [0x69,0x04,0x88,0x7d]
+
+v_cmpx_gt_i32 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x88,0x7d]
+
+v_cmpx_gt_i32 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x88,0x7d]
+
+v_cmpx_gt_i32 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x88,0x7d]
+
+v_cmpx_gt_i32 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x88,0x7d]
+
+v_cmpx_gt_i32 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x88,0x7d]
+
+v_cmpx_gt_i32 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x88,0x7d]
+
+v_cmpx_gt_i32 null, v2
+// GFX12: encoding: [0x7c,0x04,0x88,0x7d]
+
+v_cmpx_gt_i32 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x88,0x7d]
+
+v_cmpx_gt_i32 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x88,0x7d]
+
+v_cmpx_gt_i32 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x88,0x7d]
+
+v_cmpx_gt_i32 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x89,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_i64 v[1:2], v[2:3]
+// GFX12: encoding: [0x01,0x05,0xa8,0x7d]
+
+v_cmpx_gt_i64 v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0xa8,0x7d]
+
+v_cmpx_gt_i64 s[2:3], v[2:3]
+// GFX12: encoding: [0x02,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i64 s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i64 vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i64 ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i64 exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i64 null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i64 -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i64 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i64 src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i64 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0xa9,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_u16 v1, v2
+// GFX12: encoding: [0x01,0x05,0x78,0x7d]
+
+v_cmpx_gt_u16 v127, v2
+// GFX12: encoding: [0x7f,0x05,0x78,0x7d]
+
+v_cmpx_gt_u16 s1, v2
+// GFX12: encoding: [0x01,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 s105, v2
+// GFX12: encoding: [0x69,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 null, v2
+// GFX12: encoding: [0x7c,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 0.5, v2
+// GFX12: encoding: [0xff,0x04,0x78,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_gt_u16 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0x78,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_gt_u32 v1, v2
+// GFX12: encoding: [0x01,0x05,0x98,0x7d]
+
+v_cmpx_gt_u32 v255, v2
+// GFX12: encoding: [0xff,0x05,0x98,0x7d]
+
+v_cmpx_gt_u32 s1, v2
+// GFX12: encoding: [0x01,0x04,0x98,0x7d]
+
+v_cmpx_gt_u32 s105, v2
+// GFX12: encoding: [0x69,0x04,0x98,0x7d]
+
+v_cmpx_gt_u32 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x98,0x7d]
+
+v_cmpx_gt_u32 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x98,0x7d]
+
+v_cmpx_gt_u32 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x98,0x7d]
+
+v_cmpx_gt_u32 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x98,0x7d]
+
+v_cmpx_gt_u32 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x98,0x7d]
+
+v_cmpx_gt_u32 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x98,0x7d]
+
+v_cmpx_gt_u32 null, v2
+// GFX12: encoding: [0x7c,0x04,0x98,0x7d]
+
+v_cmpx_gt_u32 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x98,0x7d]
+
+v_cmpx_gt_u32 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x98,0x7d]
+
+v_cmpx_gt_u32 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x98,0x7d]
+
+v_cmpx_gt_u32 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x99,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_u64 v[1:2], v[2:3]
+// GFX12: encoding: [0x01,0x05,0xb8,0x7d]
+
+v_cmpx_gt_u64 v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0xb8,0x7d]
+
+v_cmpx_gt_u64 s[2:3], v[2:3]
+// GFX12: encoding: [0x02,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u64 s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u64 vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u64 ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u64 exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u64 null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u64 -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u64 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u64 src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u64 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0xb9,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_f16 v1, v2
+// GFX12: encoding: [0x01,0x05,0x06,0x7d]
+
+v_cmpx_le_f16 v127, v2
+// GFX12: encoding: [0x7f,0x05,0x06,0x7d]
+
+v_cmpx_le_f16 s1, v2
+// GFX12: encoding: [0x01,0x04,0x06,0x7d]
+
+v_cmpx_le_f16 s105, v2
+// GFX12: encoding: [0x69,0x04,0x06,0x7d]
+
+v_cmpx_le_f16 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x06,0x7d]
+
+v_cmpx_le_f16 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x06,0x7d]
+
+v_cmpx_le_f16 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x06,0x7d]
+
+v_cmpx_le_f16 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x06,0x7d]
+
+v_cmpx_le_f16 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x06,0x7d]
+
+v_cmpx_le_f16 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x06,0x7d]
+
+v_cmpx_le_f16 null, v2
+// GFX12: encoding: [0x7c,0x04,0x06,0x7d]
+
+v_cmpx_le_f16 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x06,0x7d]
+
+v_cmpx_le_f16 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x06,0x7d]
+
+v_cmpx_le_f16 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x06,0x7d]
+
+v_cmpx_le_f16 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0x06,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_le_f32 v1, v2
+// GFX12: encoding: [0x01,0x05,0x26,0x7d]
+
+v_cmpx_le_f32 v255, v2
+// GFX12: encoding: [0xff,0x05,0x26,0x7d]
+
+v_cmpx_le_f32 s1, v2
+// GFX12: encoding: [0x01,0x04,0x26,0x7d]
+
+v_cmpx_le_f32 s105, v2
+// GFX12: encoding: [0x69,0x04,0x26,0x7d]
+
+v_cmpx_le_f32 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x26,0x7d]
+
+v_cmpx_le_f32 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x26,0x7d]
+
+v_cmpx_le_f32 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x26,0x7d]
+
+v_cmpx_le_f32 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x26,0x7d]
+
+v_cmpx_le_f32 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x26,0x7d]
+
+v_cmpx_le_f32 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x26,0x7d]
+
+v_cmpx_le_f32 null, v2
+// GFX12: encoding: [0x7c,0x04,0x26,0x7d]
+
+v_cmpx_le_f32 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x26,0x7d]
+
+v_cmpx_le_f32 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x26,0x7d]
+
+v_cmpx_le_f32 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x26,0x7d]
+
+v_cmpx_le_f32 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x27,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_f64 v[1:2], v[2:3]
+// GFX12: encoding: [0x01,0x05,0x46,0x7d]
+
+v_cmpx_le_f64 v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0x46,0x7d]
+
+v_cmpx_le_f64 s[2:3], v[2:3]
+// GFX12: encoding: [0x02,0x04,0x46,0x7d]
+
+v_cmpx_le_f64 s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0x46,0x7d]
+
+v_cmpx_le_f64 vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0x46,0x7d]
+
+v_cmpx_le_f64 ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0x46,0x7d]
+
+v_cmpx_le_f64 exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0x46,0x7d]
+
+v_cmpx_le_f64 null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0x46,0x7d]
+
+v_cmpx_le_f64 -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0x46,0x7d]
+
+v_cmpx_le_f64 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0x46,0x7d]
+
+v_cmpx_le_f64 src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0x46,0x7d]
+
+v_cmpx_le_f64 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0x47,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_i16 v1, v2
+// GFX12: encoding: [0x01,0x05,0x66,0x7d]
+
+v_cmpx_le_i16 v127, v2
+// GFX12: encoding: [0x7f,0x05,0x66,0x7d]
+
+v_cmpx_le_i16 s1, v2
+// GFX12: encoding: [0x01,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 s105, v2
+// GFX12: encoding: [0x69,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 null, v2
+// GFX12: encoding: [0x7c,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 0.5, v2
+// GFX12: encoding: [0xff,0x04,0x66,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_le_i16 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0x66,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_le_i32 v1, v2
+// GFX12: encoding: [0x01,0x05,0x86,0x7d]
+
+v_cmpx_le_i32 v255, v2
+// GFX12: encoding: [0xff,0x05,0x86,0x7d]
+
+v_cmpx_le_i32 s1, v2
+// GFX12: encoding: [0x01,0x04,0x86,0x7d]
+
+v_cmpx_le_i32 s105, v2
+// GFX12: encoding: [0x69,0x04,0x86,0x7d]
+
+v_cmpx_le_i32 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x86,0x7d]
+
+v_cmpx_le_i32 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x86,0x7d]
+
+v_cmpx_le_i32 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x86,0x7d]
+
+v_cmpx_le_i32 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x86,0x7d]
+
+v_cmpx_le_i32 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x86,0x7d]
+
+v_cmpx_le_i32 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x86,0x7d]
+
+v_cmpx_le_i32 null, v2
+// GFX12: encoding: [0x7c,0x04,0x86,0x7d]
+
+v_cmpx_le_i32 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x86,0x7d]
+
+v_cmpx_le_i32 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x86,0x7d]
+
+v_cmpx_le_i32 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x86,0x7d]
+
+v_cmpx_le_i32 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x87,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_i64 v[1:2], v[2:3]
+// GFX12: encoding: [0x01,0x05,0xa6,0x7d]
+
+v_cmpx_le_i64 v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0xa6,0x7d]
+
+v_cmpx_le_i64 s[2:3], v[2:3]
+// GFX12: encoding: [0x02,0x04,0xa6,0x7d]
+
+v_cmpx_le_i64 s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0xa6,0x7d]
+
+v_cmpx_le_i64 vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0xa6,0x7d]
+
+v_cmpx_le_i64 ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0xa6,0x7d]
+
+v_cmpx_le_i64 exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0xa6,0x7d]
+
+v_cmpx_le_i64 null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0xa6,0x7d]
+
+v_cmpx_le_i64 -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0xa6,0x7d]
+
+v_cmpx_le_i64 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0xa6,0x7d]
+
+v_cmpx_le_i64 src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0xa6,0x7d]
+
+v_cmpx_le_i64 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0xa7,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_u16 v1, v2
+// GFX12: encoding: [0x01,0x05,0x76,0x7d]
+
+v_cmpx_le_u16 v127, v2
+// GFX12: encoding: [0x7f,0x05,0x76,0x7d]
+
+v_cmpx_le_u16 s1, v2
+// GFX12: encoding: [0x01,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 s105, v2
+// GFX12: encoding: [0x69,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 null, v2
+// GFX12: encoding: [0x7c,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 0.5, v2
+// GFX12: encoding: [0xff,0x04,0x76,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_le_u16 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0x76,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_le_u32 v1, v2
+// GFX12: encoding: [0x01,0x05,0x96,0x7d]
+
+v_cmpx_le_u32 v255, v2
+// GFX12: encoding: [0xff,0x05,0x96,0x7d]
+
+v_cmpx_le_u32 s1, v2
+// GFX12: encoding: [0x01,0x04,0x96,0x7d]
+
+v_cmpx_le_u32 s105, v2
+// GFX12: encoding: [0x69,0x04,0x96,0x7d]
+
+v_cmpx_le_u32 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x96,0x7d]
+
+v_cmpx_le_u32 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x96,0x7d]
+
+v_cmpx_le_u32 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x96,0x7d]
+
+v_cmpx_le_u32 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x96,0x7d]
+
+v_cmpx_le_u32 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x96,0x7d]
+
+v_cmpx_le_u32 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x96,0x7d]
+
+v_cmpx_le_u32 null, v2
+// GFX12: encoding: [0x7c,0x04,0x96,0x7d]
+
+v_cmpx_le_u32 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x96,0x7d]
+
+v_cmpx_le_u32 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x96,0x7d]
+
+v_cmpx_le_u32 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x96,0x7d]
+
+v_cmpx_le_u32 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x97,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_u64 v[1:2], v[2:3]
+// GFX12: encoding: [0x01,0x05,0xb6,0x7d]
+
+v_cmpx_le_u64 v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0xb6,0x7d]
+
+v_cmpx_le_u64 s[2:3], v[2:3]
+// GFX12: encoding: [0x02,0x04,0xb6,0x7d]
+
+v_cmpx_le_u64 s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0xb6,0x7d]
+
+v_cmpx_le_u64 vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0xb6,0x7d]
+
+v_cmpx_le_u64 ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0xb6,0x7d]
+
+v_cmpx_le_u64 exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0xb6,0x7d]
+
+v_cmpx_le_u64 null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0xb6,0x7d]
+
+v_cmpx_le_u64 -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0xb6,0x7d]
+
+v_cmpx_le_u64 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0xb6,0x7d]
+
+v_cmpx_le_u64 src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0xb6,0x7d]
+
+v_cmpx_le_u64 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0xb7,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lg_f16 v1, v2
+// GFX12: encoding: [0x01,0x05,0x0a,0x7d]
+
+v_cmpx_lg_f16 v127, v2
+// GFX12: encoding: [0x7f,0x05,0x0a,0x7d]
+
+v_cmpx_lg_f16 s1, v2
+// GFX12: encoding: [0x01,0x04,0x0a,0x7d]
+
+v_cmpx_lg_f16 s105, v2
+// GFX12: encoding: [0x69,0x04,0x0a,0x7d]
+
+v_cmpx_lg_f16 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0a,0x7d]
+
+v_cmpx_lg_f16 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0a,0x7d]
+
+v_cmpx_lg_f16 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0a,0x7d]
+
+v_cmpx_lg_f16 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0a,0x7d]
+
+v_cmpx_lg_f16 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0a,0x7d]
+
+v_cmpx_lg_f16 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0a,0x7d]
+
+v_cmpx_lg_f16 null, v2
+// GFX12: encoding: [0x7c,0x04,0x0a,0x7d]
+
+v_cmpx_lg_f16 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0a,0x7d]
+
+v_cmpx_lg_f16 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0a,0x7d]
+
+v_cmpx_lg_f16 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0a,0x7d]
+
+v_cmpx_lg_f16 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0x0a,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_lg_f32 v1, v2
+// GFX12: encoding: [0x01,0x05,0x2a,0x7d]
+
+v_cmpx_lg_f32 v255, v2
+// GFX12: encoding: [0xff,0x05,0x2a,0x7d]
+
+v_cmpx_lg_f32 s1, v2
+// GFX12: encoding: [0x01,0x04,0x2a,0x7d]
+
+v_cmpx_lg_f32 s105, v2
+// GFX12: encoding: [0x69,0x04,0x2a,0x7d]
+
+v_cmpx_lg_f32 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x2a,0x7d]
+
+v_cmpx_lg_f32 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x2a,0x7d]
+
+v_cmpx_lg_f32 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x2a,0x7d]
+
+v_cmpx_lg_f32 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x2a,0x7d]
+
+v_cmpx_lg_f32 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x2a,0x7d]
+
+v_cmpx_lg_f32 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x2a,0x7d]
+
+v_cmpx_lg_f32 null, v2
+// GFX12: encoding: [0x7c,0x04,0x2a,0x7d]
+
+v_cmpx_lg_f32 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x2a,0x7d]
+
+v_cmpx_lg_f32 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x2a,0x7d]
+
+v_cmpx_lg_f32 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x2a,0x7d]
+
+v_cmpx_lg_f32 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x2b,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lg_f64 v[1:2], v[2:3]
+// GFX12: encoding: [0x01,0x05,0x4a,0x7d]
+
+v_cmpx_lg_f64 v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0x4a,0x7d]
+
+v_cmpx_lg_f64 s[2:3], v[2:3]
+// GFX12: encoding: [0x02,0x04,0x4a,0x7d]
+
+v_cmpx_lg_f64 s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0x4a,0x7d]
+
+v_cmpx_lg_f64 vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0x4a,0x7d]
+
+v_cmpx_lg_f64 ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0x4a,0x7d]
+
+v_cmpx_lg_f64 exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0x4a,0x7d]
+
+v_cmpx_lg_f64 null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0x4a,0x7d]
+
+v_cmpx_lg_f64 -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0x4a,0x7d]
+
+v_cmpx_lg_f64 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0x4a,0x7d]
+
+v_cmpx_lg_f64 src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0x4a,0x7d]
+
+v_cmpx_lg_f64 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0x4b,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_f16 v1, v2
+// GFX12: encoding: [0x01,0x05,0x02,0x7d]
+
+v_cmpx_lt_f16 v127, v2
+// GFX12: encoding: [0x7f,0x05,0x02,0x7d]
+
+v_cmpx_lt_f16 s1, v2
+// GFX12: encoding: [0x01,0x04,0x02,0x7d]
+
+v_cmpx_lt_f16 s105, v2
+// GFX12: encoding: [0x69,0x04,0x02,0x7d]
+
+v_cmpx_lt_f16 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x02,0x7d]
+
+v_cmpx_lt_f16 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x02,0x7d]
+
+v_cmpx_lt_f16 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x02,0x7d]
+
+v_cmpx_lt_f16 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x02,0x7d]
+
+v_cmpx_lt_f16 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x02,0x7d]
+
+v_cmpx_lt_f16 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x02,0x7d]
+
+v_cmpx_lt_f16 null, v2
+// GFX12: encoding: [0x7c,0x04,0x02,0x7d]
+
+v_cmpx_lt_f16 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x02,0x7d]
+
+v_cmpx_lt_f16 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x02,0x7d]
+
+v_cmpx_lt_f16 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x02,0x7d]
+
+v_cmpx_lt_f16 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0x02,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_lt_f32 v1, v2
+// GFX12: encoding: [0x01,0x05,0x22,0x7d]
+
+v_cmpx_lt_f32 v255, v2
+// GFX12: encoding: [0xff,0x05,0x22,0x7d]
+
+v_cmpx_lt_f32 s1, v2
+// GFX12: encoding: [0x01,0x04,0x22,0x7d]
+
+v_cmpx_lt_f32 s105, v2
+// GFX12: encoding: [0x69,0x04,0x22,0x7d]
+
+v_cmpx_lt_f32 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x22,0x7d]
+
+v_cmpx_lt_f32 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x22,0x7d]
+
+v_cmpx_lt_f32 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x22,0x7d]
+
+v_cmpx_lt_f32 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x22,0x7d]
+
+v_cmpx_lt_f32 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x22,0x7d]
+
+v_cmpx_lt_f32 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x22,0x7d]
+
+v_cmpx_lt_f32 null, v2
+// GFX12: encoding: [0x7c,0x04,0x22,0x7d]
+
+v_cmpx_lt_f32 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x22,0x7d]
+
+v_cmpx_lt_f32 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x22,0x7d]
+
+v_cmpx_lt_f32 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x22,0x7d]
+
+v_cmpx_lt_f32 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x23,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_f64 v[1:2], v[2:3]
+// GFX12: encoding: [0x01,0x05,0x42,0x7d]
+
+v_cmpx_lt_f64 v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0x42,0x7d]
+
+v_cmpx_lt_f64 s[2:3], v[2:3]
+// GFX12: encoding: [0x02,0x04,0x42,0x7d]
+
+v_cmpx_lt_f64 s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0x42,0x7d]
+
+v_cmpx_lt_f64 vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0x42,0x7d]
+
+v_cmpx_lt_f64 ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0x42,0x7d]
+
+v_cmpx_lt_f64 exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0x42,0x7d]
+
+v_cmpx_lt_f64 null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0x42,0x7d]
+
+v_cmpx_lt_f64 -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0x42,0x7d]
+
+v_cmpx_lt_f64 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0x42,0x7d]
+
+v_cmpx_lt_f64 src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0x42,0x7d]
+
+v_cmpx_lt_f64 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0x43,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_i16 v1, v2
+// GFX12: encoding: [0x01,0x05,0x62,0x7d]
+
+v_cmpx_lt_i16 v127, v2
+// GFX12: encoding: [0x7f,0x05,0x62,0x7d]
+
+v_cmpx_lt_i16 s1, v2
+// GFX12: encoding: [0x01,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 s105, v2
+// GFX12: encoding: [0x69,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 null, v2
+// GFX12: encoding: [0x7c,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 0.5, v2
+// GFX12: encoding: [0xff,0x04,0x62,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_lt_i16 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0x62,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_lt_i32 v1, v2
+// GFX12: encoding: [0x01,0x05,0x82,0x7d]
+
+v_cmpx_lt_i32 v255, v2
+// GFX12: encoding: [0xff,0x05,0x82,0x7d]
+
+v_cmpx_lt_i32 s1, v2
+// GFX12: encoding: [0x01,0x04,0x82,0x7d]
+
+v_cmpx_lt_i32 s105, v2
+// GFX12: encoding: [0x69,0x04,0x82,0x7d]
+
+v_cmpx_lt_i32 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x82,0x7d]
+
+v_cmpx_lt_i32 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x82,0x7d]
+
+v_cmpx_lt_i32 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x82,0x7d]
+
+v_cmpx_lt_i32 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x82,0x7d]
+
+v_cmpx_lt_i32 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x82,0x7d]
+
+v_cmpx_lt_i32 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x82,0x7d]
+
+v_cmpx_lt_i32 null, v2
+// GFX12: encoding: [0x7c,0x04,0x82,0x7d]
+
+v_cmpx_lt_i32 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x82,0x7d]
+
+v_cmpx_lt_i32 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x82,0x7d]
+
+v_cmpx_lt_i32 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x82,0x7d]
+
+v_cmpx_lt_i32 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x83,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_i64 v[1:2], v[2:3]
+// GFX12: encoding: [0x01,0x05,0xa2,0x7d]
+
+v_cmpx_lt_i64 v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0xa2,0x7d]
+
+v_cmpx_lt_i64 s[2:3], v[2:3]
+// GFX12: encoding: [0x02,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i64 s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i64 vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i64 ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i64 exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i64 null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i64 -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i64 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i64 src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i64 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0xa3,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_u16 v1, v2
+// GFX12: encoding: [0x01,0x05,0x72,0x7d]
+
+v_cmpx_lt_u16 v127, v2
+// GFX12: encoding: [0x7f,0x05,0x72,0x7d]
+
+v_cmpx_lt_u16 s1, v2
+// GFX12: encoding: [0x01,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 s105, v2
+// GFX12: encoding: [0x69,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 null, v2
+// GFX12: encoding: [0x7c,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 0.5, v2
+// GFX12: encoding: [0xff,0x04,0x72,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_lt_u16 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0x72,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_lt_u32 v1, v2
+// GFX12: encoding: [0x01,0x05,0x92,0x7d]
+
+v_cmpx_lt_u32 v255, v2
+// GFX12: encoding: [0xff,0x05,0x92,0x7d]
+
+v_cmpx_lt_u32 s1, v2
+// GFX12: encoding: [0x01,0x04,0x92,0x7d]
+
+v_cmpx_lt_u32 s105, v2
+// GFX12: encoding: [0x69,0x04,0x92,0x7d]
+
+v_cmpx_lt_u32 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x92,0x7d]
+
+v_cmpx_lt_u32 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x92,0x7d]
+
+v_cmpx_lt_u32 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x92,0x7d]
+
+v_cmpx_lt_u32 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x92,0x7d]
+
+v_cmpx_lt_u32 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x92,0x7d]
+
+v_cmpx_lt_u32 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x92,0x7d]
+
+v_cmpx_lt_u32 null, v2
+// GFX12: encoding: [0x7c,0x04,0x92,0x7d]
+
+v_cmpx_lt_u32 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x92,0x7d]
+
+v_cmpx_lt_u32 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x92,0x7d]
+
+v_cmpx_lt_u32 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x92,0x7d]
+
+v_cmpx_lt_u32 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x93,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_u64 v[1:2], v[2:3]
+// GFX12: encoding: [0x01,0x05,0xb2,0x7d]
+
+v_cmpx_lt_u64 v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0xb2,0x7d]
+
+v_cmpx_lt_u64 s[2:3], v[2:3]
+// GFX12: encoding: [0x02,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u64 s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u64 vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u64 ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u64 exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u64 null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u64 -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u64 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u64 src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u64 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0xb3,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ne_i16 v1, v2
+// GFX12: encoding: [0x01,0x05,0x6a,0x7d]
+
+v_cmpx_ne_i16 v127, v2
+// GFX12: encoding: [0x7f,0x05,0x6a,0x7d]
+
+v_cmpx_ne_i16 s1, v2
+// GFX12: encoding: [0x01,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 s105, v2
+// GFX12: encoding: [0x69,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 null, v2
+// GFX12: encoding: [0x7c,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 0.5, v2
+// GFX12: encoding: [0xff,0x04,0x6a,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_ne_i16 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0x6a,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ne_i32 v1, v2
+// GFX12: encoding: [0x01,0x05,0x8a,0x7d]
+
+v_cmpx_ne_i32 v255, v2
+// GFX12: encoding: [0xff,0x05,0x8a,0x7d]
+
+v_cmpx_ne_i32 s1, v2
+// GFX12: encoding: [0x01,0x04,0x8a,0x7d]
+
+v_cmpx_ne_i32 s105, v2
+// GFX12: encoding: [0x69,0x04,0x8a,0x7d]
+
+v_cmpx_ne_i32 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x8a,0x7d]
+
+v_cmpx_ne_i32 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x8a,0x7d]
+
+v_cmpx_ne_i32 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x8a,0x7d]
+
+v_cmpx_ne_i32 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x8a,0x7d]
+
+v_cmpx_ne_i32 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x8a,0x7d]
+
+v_cmpx_ne_i32 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x8a,0x7d]
+
+v_cmpx_ne_i32 null, v2
+// GFX12: encoding: [0x7c,0x04,0x8a,0x7d]
+
+v_cmpx_ne_i32 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x8a,0x7d]
+
+v_cmpx_ne_i32 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x8a,0x7d]
+
+v_cmpx_ne_i32 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x8a,0x7d]
+
+v_cmpx_ne_i32 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x8b,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ne_i64 v[1:2], v[2:3]
+// GFX12: encoding: [0x01,0x05,0xaa,0x7d]
+
+v_cmpx_ne_i64 v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0xaa,0x7d]
+
+v_cmpx_ne_i64 s[2:3], v[2:3]
+// GFX12: encoding: [0x02,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i64 s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i64 vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i64 ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i64 exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i64 null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i64 -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i64 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i64 src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i64 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0xab,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ne_u16 v1, v2
+// GFX12: encoding: [0x01,0x05,0x7a,0x7d]
+
+v_cmpx_ne_u16 v127, v2
+// GFX12: encoding: [0x7f,0x05,0x7a,0x7d]
+
+v_cmpx_ne_u16 s1, v2
+// GFX12: encoding: [0x01,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 s105, v2
+// GFX12: encoding: [0x69,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 null, v2
+// GFX12: encoding: [0x7c,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 0.5, v2
+// GFX12: encoding: [0xff,0x04,0x7a,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_ne_u16 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0x7a,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ne_u32 v1, v2
+// GFX12: encoding: [0x01,0x05,0x9a,0x7d]
+
+v_cmpx_ne_u32 v255, v2
+// GFX12: encoding: [0xff,0x05,0x9a,0x7d]
+
+v_cmpx_ne_u32 s1, v2
+// GFX12: encoding: [0x01,0x04,0x9a,0x7d]
+
+v_cmpx_ne_u32 s105, v2
+// GFX12: encoding: [0x69,0x04,0x9a,0x7d]
+
+v_cmpx_ne_u32 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x9a,0x7d]
+
+v_cmpx_ne_u32 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x9a,0x7d]
+
+v_cmpx_ne_u32 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x9a,0x7d]
+
+v_cmpx_ne_u32 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x9a,0x7d]
+
+v_cmpx_ne_u32 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x9a,0x7d]
+
+v_cmpx_ne_u32 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x9a,0x7d]
+
+v_cmpx_ne_u32 null, v2
+// GFX12: encoding: [0x7c,0x04,0x9a,0x7d]
+
+v_cmpx_ne_u32 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x9a,0x7d]
+
+v_cmpx_ne_u32 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x9a,0x7d]
+
+v_cmpx_ne_u32 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x9a,0x7d]
+
+v_cmpx_ne_u32 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x9b,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ne_u64 v[1:2], v[2:3]
+// GFX12: encoding: [0x01,0x05,0xba,0x7d]
+
+v_cmpx_ne_u64 v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0xba,0x7d]
+
+v_cmpx_ne_u64 s[2:3], v[2:3]
+// GFX12: encoding: [0x02,0x04,0xba,0x7d]
+
+v_cmpx_ne_u64 s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0xba,0x7d]
+
+v_cmpx_ne_u64 vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0xba,0x7d]
+
+v_cmpx_ne_u64 ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0xba,0x7d]
+
+v_cmpx_ne_u64 exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0xba,0x7d]
+
+v_cmpx_ne_u64 null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0xba,0x7d]
+
+v_cmpx_ne_u64 -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0xba,0x7d]
+
+v_cmpx_ne_u64 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0xba,0x7d]
+
+v_cmpx_ne_u64 src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0xba,0x7d]
+
+v_cmpx_ne_u64 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0xbb,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_neq_f16 v1, v2
+// GFX12: encoding: [0x01,0x05,0x1a,0x7d]
+
+v_cmpx_neq_f16 v127, v2
+// GFX12: encoding: [0x7f,0x05,0x1a,0x7d]
+
+v_cmpx_neq_f16 s1, v2
+// GFX12: encoding: [0x01,0x04,0x1a,0x7d]
+
+v_cmpx_neq_f16 s105, v2
+// GFX12: encoding: [0x69,0x04,0x1a,0x7d]
+
+v_cmpx_neq_f16 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x1a,0x7d]
+
+v_cmpx_neq_f16 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x1a,0x7d]
+
+v_cmpx_neq_f16 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x1a,0x7d]
+
+v_cmpx_neq_f16 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x1a,0x7d]
+
+v_cmpx_neq_f16 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x1a,0x7d]
+
+v_cmpx_neq_f16 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x1a,0x7d]
+
+v_cmpx_neq_f16 null, v2
+// GFX12: encoding: [0x7c,0x04,0x1a,0x7d]
+
+v_cmpx_neq_f16 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x1a,0x7d]
+
+v_cmpx_neq_f16 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x1a,0x7d]
+
+v_cmpx_neq_f16 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x1a,0x7d]
+
+v_cmpx_neq_f16 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0x1a,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_neq_f32 v1, v2
+// GFX12: encoding: [0x01,0x05,0x3a,0x7d]
+
+v_cmpx_neq_f32 v255, v2
+// GFX12: encoding: [0xff,0x05,0x3a,0x7d]
+
+v_cmpx_neq_f32 s1, v2
+// GFX12: encoding: [0x01,0x04,0x3a,0x7d]
+
+v_cmpx_neq_f32 s105, v2
+// GFX12: encoding: [0x69,0x04,0x3a,0x7d]
+
+v_cmpx_neq_f32 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x3a,0x7d]
+
+v_cmpx_neq_f32 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x3a,0x7d]
+
+v_cmpx_neq_f32 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x3a,0x7d]
+
+v_cmpx_neq_f32 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x3a,0x7d]
+
+v_cmpx_neq_f32 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x3a,0x7d]
+
+v_cmpx_neq_f32 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x3a,0x7d]
+
+v_cmpx_neq_f32 null, v2
+// GFX12: encoding: [0x7c,0x04,0x3a,0x7d]
+
+v_cmpx_neq_f32 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x3a,0x7d]
+
+v_cmpx_neq_f32 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x3a,0x7d]
+
+v_cmpx_neq_f32 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x3a,0x7d]
+
+v_cmpx_neq_f32 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x3b,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_neq_f64 v[1:2], v[2:3]
+// GFX12: encoding: [0x01,0x05,0x5a,0x7d]
+
+v_cmpx_neq_f64 v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0x5a,0x7d]
+
+v_cmpx_neq_f64 s[2:3], v[2:3]
+// GFX12: encoding: [0x02,0x04,0x5a,0x7d]
+
+v_cmpx_neq_f64 s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0x5a,0x7d]
+
+v_cmpx_neq_f64 vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0x5a,0x7d]
+
+v_cmpx_neq_f64 ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0x5a,0x7d]
+
+v_cmpx_neq_f64 exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0x5a,0x7d]
+
+v_cmpx_neq_f64 null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0x5a,0x7d]
+
+v_cmpx_neq_f64 -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0x5a,0x7d]
+
+v_cmpx_neq_f64 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0x5a,0x7d]
+
+v_cmpx_neq_f64 src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0x5a,0x7d]
+
+v_cmpx_neq_f64 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0x5b,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nge_f16 v1, v2
+// GFX12: encoding: [0x01,0x05,0x12,0x7d]
+
+v_cmpx_nge_f16 v127, v2
+// GFX12: encoding: [0x7f,0x05,0x12,0x7d]
+
+v_cmpx_nge_f16 s1, v2
+// GFX12: encoding: [0x01,0x04,0x12,0x7d]
+
+v_cmpx_nge_f16 s105, v2
+// GFX12: encoding: [0x69,0x04,0x12,0x7d]
+
+v_cmpx_nge_f16 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x12,0x7d]
+
+v_cmpx_nge_f16 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x12,0x7d]
+
+v_cmpx_nge_f16 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x12,0x7d]
+
+v_cmpx_nge_f16 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x12,0x7d]
+
+v_cmpx_nge_f16 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x12,0x7d]
+
+v_cmpx_nge_f16 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x12,0x7d]
+
+v_cmpx_nge_f16 null, v2
+// GFX12: encoding: [0x7c,0x04,0x12,0x7d]
+
+v_cmpx_nge_f16 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x12,0x7d]
+
+v_cmpx_nge_f16 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x12,0x7d]
+
+v_cmpx_nge_f16 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x12,0x7d]
+
+v_cmpx_nge_f16 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0x12,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_nge_f32 v1, v2
+// GFX12: encoding: [0x01,0x05,0x32,0x7d]
+
+v_cmpx_nge_f32 v255, v2
+// GFX12: encoding: [0xff,0x05,0x32,0x7d]
+
+v_cmpx_nge_f32 s1, v2
+// GFX12: encoding: [0x01,0x04,0x32,0x7d]
+
+v_cmpx_nge_f32 s105, v2
+// GFX12: encoding: [0x69,0x04,0x32,0x7d]
+
+v_cmpx_nge_f32 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x32,0x7d]
+
+v_cmpx_nge_f32 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x32,0x7d]
+
+v_cmpx_nge_f32 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x32,0x7d]
+
+v_cmpx_nge_f32 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x32,0x7d]
+
+v_cmpx_nge_f32 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x32,0x7d]
+
+v_cmpx_nge_f32 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x32,0x7d]
+
+v_cmpx_nge_f32 null, v2
+// GFX12: encoding: [0x7c,0x04,0x32,0x7d]
+
+v_cmpx_nge_f32 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x32,0x7d]
+
+v_cmpx_nge_f32 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x32,0x7d]
+
+v_cmpx_nge_f32 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x32,0x7d]
+
+v_cmpx_nge_f32 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x33,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nge_f64 v[1:2], v[2:3]
+// GFX12: encoding: [0x01,0x05,0x52,0x7d]
+
+v_cmpx_nge_f64 v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0x52,0x7d]
+
+v_cmpx_nge_f64 s[2:3], v[2:3]
+// GFX12: encoding: [0x02,0x04,0x52,0x7d]
+
+v_cmpx_nge_f64 s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0x52,0x7d]
+
+v_cmpx_nge_f64 vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0x52,0x7d]
+
+v_cmpx_nge_f64 ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0x52,0x7d]
+
+v_cmpx_nge_f64 exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0x52,0x7d]
+
+v_cmpx_nge_f64 null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0x52,0x7d]
+
+v_cmpx_nge_f64 -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0x52,0x7d]
+
+v_cmpx_nge_f64 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0x52,0x7d]
+
+v_cmpx_nge_f64 src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0x52,0x7d]
+
+v_cmpx_nge_f64 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0x53,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ngt_f16 v1, v2
+// GFX12: encoding: [0x01,0x05,0x16,0x7d]
+
+v_cmpx_ngt_f16 v127, v2
+// GFX12: encoding: [0x7f,0x05,0x16,0x7d]
+
+v_cmpx_ngt_f16 s1, v2
+// GFX12: encoding: [0x01,0x04,0x16,0x7d]
+
+v_cmpx_ngt_f16 s105, v2
+// GFX12: encoding: [0x69,0x04,0x16,0x7d]
+
+v_cmpx_ngt_f16 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x16,0x7d]
+
+v_cmpx_ngt_f16 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x16,0x7d]
+
+v_cmpx_ngt_f16 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x16,0x7d]
+
+v_cmpx_ngt_f16 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x16,0x7d]
+
+v_cmpx_ngt_f16 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x16,0x7d]
+
+v_cmpx_ngt_f16 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x16,0x7d]
+
+v_cmpx_ngt_f16 null, v2
+// GFX12: encoding: [0x7c,0x04,0x16,0x7d]
+
+v_cmpx_ngt_f16 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x16,0x7d]
+
+v_cmpx_ngt_f16 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x16,0x7d]
+
+v_cmpx_ngt_f16 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x16,0x7d]
+
+v_cmpx_ngt_f16 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0x16,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ngt_f32 v1, v2
+// GFX12: encoding: [0x01,0x05,0x36,0x7d]
+
+v_cmpx_ngt_f32 v255, v2
+// GFX12: encoding: [0xff,0x05,0x36,0x7d]
+
+v_cmpx_ngt_f32 s1, v2
+// GFX12: encoding: [0x01,0x04,0x36,0x7d]
+
+v_cmpx_ngt_f32 s105, v2
+// GFX12: encoding: [0x69,0x04,0x36,0x7d]
+
+v_cmpx_ngt_f32 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x36,0x7d]
+
+v_cmpx_ngt_f32 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x36,0x7d]
+
+v_cmpx_ngt_f32 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x36,0x7d]
+
+v_cmpx_ngt_f32 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x36,0x7d]
+
+v_cmpx_ngt_f32 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x36,0x7d]
+
+v_cmpx_ngt_f32 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x36,0x7d]
+
+v_cmpx_ngt_f32 null, v2
+// GFX12: encoding: [0x7c,0x04,0x36,0x7d]
+
+v_cmpx_ngt_f32 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x36,0x7d]
+
+v_cmpx_ngt_f32 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x36,0x7d]
+
+v_cmpx_ngt_f32 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x36,0x7d]
+
+v_cmpx_ngt_f32 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x37,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ngt_f64 v[1:2], v[2:3]
+// GFX12: encoding: [0x01,0x05,0x56,0x7d]
+
+v_cmpx_ngt_f64 v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0x56,0x7d]
+
+v_cmpx_ngt_f64 s[2:3], v[2:3]
+// GFX12: encoding: [0x02,0x04,0x56,0x7d]
+
+v_cmpx_ngt_f64 s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0x56,0x7d]
+
+v_cmpx_ngt_f64 vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0x56,0x7d]
+
+v_cmpx_ngt_f64 ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0x56,0x7d]
+
+v_cmpx_ngt_f64 exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0x56,0x7d]
+
+v_cmpx_ngt_f64 null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0x56,0x7d]
+
+v_cmpx_ngt_f64 -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0x56,0x7d]
+
+v_cmpx_ngt_f64 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0x56,0x7d]
+
+v_cmpx_ngt_f64 src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0x56,0x7d]
+
+v_cmpx_ngt_f64 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0x57,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nle_f16 v1, v2
+// GFX12: encoding: [0x01,0x05,0x18,0x7d]
+
+v_cmpx_nle_f16 v127, v2
+// GFX12: encoding: [0x7f,0x05,0x18,0x7d]
+
+v_cmpx_nle_f16 s1, v2
+// GFX12: encoding: [0x01,0x04,0x18,0x7d]
+
+v_cmpx_nle_f16 s105, v2
+// GFX12: encoding: [0x69,0x04,0x18,0x7d]
+
+v_cmpx_nle_f16 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x18,0x7d]
+
+v_cmpx_nle_f16 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x18,0x7d]
+
+v_cmpx_nle_f16 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x18,0x7d]
+
+v_cmpx_nle_f16 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x18,0x7d]
+
+v_cmpx_nle_f16 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x18,0x7d]
+
+v_cmpx_nle_f16 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x18,0x7d]
+
+v_cmpx_nle_f16 null, v2
+// GFX12: encoding: [0x7c,0x04,0x18,0x7d]
+
+v_cmpx_nle_f16 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x18,0x7d]
+
+v_cmpx_nle_f16 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x18,0x7d]
+
+v_cmpx_nle_f16 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x18,0x7d]
+
+v_cmpx_nle_f16 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0x18,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_nle_f32 v1, v2
+// GFX12: encoding: [0x01,0x05,0x38,0x7d]
+
+v_cmpx_nle_f32 v255, v2
+// GFX12: encoding: [0xff,0x05,0x38,0x7d]
+
+v_cmpx_nle_f32 s1, v2
+// GFX12: encoding: [0x01,0x04,0x38,0x7d]
+
+v_cmpx_nle_f32 s105, v2
+// GFX12: encoding: [0x69,0x04,0x38,0x7d]
+
+v_cmpx_nle_f32 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x38,0x7d]
+
+v_cmpx_nle_f32 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x38,0x7d]
+
+v_cmpx_nle_f32 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x38,0x7d]
+
+v_cmpx_nle_f32 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x38,0x7d]
+
+v_cmpx_nle_f32 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x38,0x7d]
+
+v_cmpx_nle_f32 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x38,0x7d]
+
+v_cmpx_nle_f32 null, v2
+// GFX12: encoding: [0x7c,0x04,0x38,0x7d]
+
+v_cmpx_nle_f32 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x38,0x7d]
+
+v_cmpx_nle_f32 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x38,0x7d]
+
+v_cmpx_nle_f32 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x38,0x7d]
+
+v_cmpx_nle_f32 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x39,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nle_f64 v[1:2], v[2:3]
+// GFX12: encoding: [0x01,0x05,0x58,0x7d]
+
+v_cmpx_nle_f64 v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0x58,0x7d]
+
+v_cmpx_nle_f64 s[2:3], v[2:3]
+// GFX12: encoding: [0x02,0x04,0x58,0x7d]
+
+v_cmpx_nle_f64 s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0x58,0x7d]
+
+v_cmpx_nle_f64 vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0x58,0x7d]
+
+v_cmpx_nle_f64 ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0x58,0x7d]
+
+v_cmpx_nle_f64 exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0x58,0x7d]
+
+v_cmpx_nle_f64 null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0x58,0x7d]
+
+v_cmpx_nle_f64 -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0x58,0x7d]
+
+v_cmpx_nle_f64 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0x58,0x7d]
+
+v_cmpx_nle_f64 src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0x58,0x7d]
+
+v_cmpx_nle_f64 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0x59,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nlg_f16 v1, v2
+// GFX12: encoding: [0x01,0x05,0x14,0x7d]
+
+v_cmpx_nlg_f16 v127, v2
+// GFX12: encoding: [0x7f,0x05,0x14,0x7d]
+
+v_cmpx_nlg_f16 s1, v2
+// GFX12: encoding: [0x01,0x04,0x14,0x7d]
+
+v_cmpx_nlg_f16 s105, v2
+// GFX12: encoding: [0x69,0x04,0x14,0x7d]
+
+v_cmpx_nlg_f16 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x14,0x7d]
+
+v_cmpx_nlg_f16 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x14,0x7d]
+
+v_cmpx_nlg_f16 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x14,0x7d]
+
+v_cmpx_nlg_f16 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x14,0x7d]
+
+v_cmpx_nlg_f16 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x14,0x7d]
+
+v_cmpx_nlg_f16 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x14,0x7d]
+
+v_cmpx_nlg_f16 null, v2
+// GFX12: encoding: [0x7c,0x04,0x14,0x7d]
+
+v_cmpx_nlg_f16 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x14,0x7d]
+
+v_cmpx_nlg_f16 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x14,0x7d]
+
+v_cmpx_nlg_f16 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x14,0x7d]
+
+v_cmpx_nlg_f16 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0x14,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_nlg_f32 v1, v2
+// GFX12: encoding: [0x01,0x05,0x34,0x7d]
+
+v_cmpx_nlg_f32 v255, v2
+// GFX12: encoding: [0xff,0x05,0x34,0x7d]
+
+v_cmpx_nlg_f32 s1, v2
+// GFX12: encoding: [0x01,0x04,0x34,0x7d]
+
+v_cmpx_nlg_f32 s105, v2
+// GFX12: encoding: [0x69,0x04,0x34,0x7d]
+
+v_cmpx_nlg_f32 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x34,0x7d]
+
+v_cmpx_nlg_f32 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x34,0x7d]
+
+v_cmpx_nlg_f32 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x34,0x7d]
+
+v_cmpx_nlg_f32 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x34,0x7d]
+
+v_cmpx_nlg_f32 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x34,0x7d]
+
+v_cmpx_nlg_f32 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x34,0x7d]
+
+v_cmpx_nlg_f32 null, v2
+// GFX12: encoding: [0x7c,0x04,0x34,0x7d]
+
+v_cmpx_nlg_f32 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x34,0x7d]
+
+v_cmpx_nlg_f32 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x34,0x7d]
+
+v_cmpx_nlg_f32 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x34,0x7d]
+
+v_cmpx_nlg_f32 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x35,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nlg_f64 v[1:2], v[2:3]
+// GFX12: encoding: [0x01,0x05,0x54,0x7d]
+
+v_cmpx_nlg_f64 v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0x54,0x7d]
+
+v_cmpx_nlg_f64 s[2:3], v[2:3]
+// GFX12: encoding: [0x02,0x04,0x54,0x7d]
+
+v_cmpx_nlg_f64 s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0x54,0x7d]
+
+v_cmpx_nlg_f64 vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0x54,0x7d]
+
+v_cmpx_nlg_f64 ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0x54,0x7d]
+
+v_cmpx_nlg_f64 exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0x54,0x7d]
+
+v_cmpx_nlg_f64 null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0x54,0x7d]
+
+v_cmpx_nlg_f64 -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0x54,0x7d]
+
+v_cmpx_nlg_f64 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0x54,0x7d]
+
+v_cmpx_nlg_f64 src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0x54,0x7d]
+
+v_cmpx_nlg_f64 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0x55,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nlt_f16 v1, v2
+// GFX12: encoding: [0x01,0x05,0x1c,0x7d]
+
+v_cmpx_nlt_f16 v127, v2
+// GFX12: encoding: [0x7f,0x05,0x1c,0x7d]
+
+v_cmpx_nlt_f16 s1, v2
+// GFX12: encoding: [0x01,0x04,0x1c,0x7d]
+
+v_cmpx_nlt_f16 s105, v2
+// GFX12: encoding: [0x69,0x04,0x1c,0x7d]
+
+v_cmpx_nlt_f16 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x1c,0x7d]
+
+v_cmpx_nlt_f16 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x1c,0x7d]
+
+v_cmpx_nlt_f16 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x1c,0x7d]
+
+v_cmpx_nlt_f16 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x1c,0x7d]
+
+v_cmpx_nlt_f16 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x1c,0x7d]
+
+v_cmpx_nlt_f16 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x1c,0x7d]
+
+v_cmpx_nlt_f16 null, v2
+// GFX12: encoding: [0x7c,0x04,0x1c,0x7d]
+
+v_cmpx_nlt_f16 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x1c,0x7d]
+
+v_cmpx_nlt_f16 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x1c,0x7d]
+
+v_cmpx_nlt_f16 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x1c,0x7d]
+
+v_cmpx_nlt_f16 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0x1c,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_nlt_f32 v1, v2
+// GFX12: encoding: [0x01,0x05,0x3c,0x7d]
+
+v_cmpx_nlt_f32 v255, v2
+// GFX12: encoding: [0xff,0x05,0x3c,0x7d]
+
+v_cmpx_nlt_f32 s1, v2
+// GFX12: encoding: [0x01,0x04,0x3c,0x7d]
+
+v_cmpx_nlt_f32 s105, v2
+// GFX12: encoding: [0x69,0x04,0x3c,0x7d]
+
+v_cmpx_nlt_f32 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x3c,0x7d]
+
+v_cmpx_nlt_f32 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x3c,0x7d]
+
+v_cmpx_nlt_f32 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x3c,0x7d]
+
+v_cmpx_nlt_f32 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x3c,0x7d]
+
+v_cmpx_nlt_f32 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x3c,0x7d]
+
+v_cmpx_nlt_f32 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x3c,0x7d]
+
+v_cmpx_nlt_f32 null, v2
+// GFX12: encoding: [0x7c,0x04,0x3c,0x7d]
+
+v_cmpx_nlt_f32 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x3c,0x7d]
+
+v_cmpx_nlt_f32 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x3c,0x7d]
+
+v_cmpx_nlt_f32 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x3c,0x7d]
+
+v_cmpx_nlt_f32 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x3d,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nlt_f64 v[1:2], v[2:3]
+// GFX12: encoding: [0x01,0x05,0x5c,0x7d]
+
+v_cmpx_nlt_f64 v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0x5c,0x7d]
+
+v_cmpx_nlt_f64 s[2:3], v[2:3]
+// GFX12: encoding: [0x02,0x04,0x5c,0x7d]
+
+v_cmpx_nlt_f64 s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0x5c,0x7d]
+
+v_cmpx_nlt_f64 vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0x5c,0x7d]
+
+v_cmpx_nlt_f64 ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0x5c,0x7d]
+
+v_cmpx_nlt_f64 exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0x5c,0x7d]
+
+v_cmpx_nlt_f64 null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0x5c,0x7d]
+
+v_cmpx_nlt_f64 -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0x5c,0x7d]
+
+v_cmpx_nlt_f64 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0x5c,0x7d]
+
+v_cmpx_nlt_f64 src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0x5c,0x7d]
+
+v_cmpx_nlt_f64 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0x5d,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_o_f16 v1, v2
+// GFX12: encoding: [0x01,0x05,0x0e,0x7d]
+
+v_cmpx_o_f16 v127, v2
+// GFX12: encoding: [0x7f,0x05,0x0e,0x7d]
+
+v_cmpx_o_f16 s1, v2
+// GFX12: encoding: [0x01,0x04,0x0e,0x7d]
+
+v_cmpx_o_f16 s105, v2
+// GFX12: encoding: [0x69,0x04,0x0e,0x7d]
+
+v_cmpx_o_f16 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x0e,0x7d]
+
+v_cmpx_o_f16 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x0e,0x7d]
+
+v_cmpx_o_f16 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x0e,0x7d]
+
+v_cmpx_o_f16 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x0e,0x7d]
+
+v_cmpx_o_f16 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x0e,0x7d]
+
+v_cmpx_o_f16 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x0e,0x7d]
+
+v_cmpx_o_f16 null, v2
+// GFX12: encoding: [0x7c,0x04,0x0e,0x7d]
+
+v_cmpx_o_f16 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x0e,0x7d]
+
+v_cmpx_o_f16 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x0e,0x7d]
+
+v_cmpx_o_f16 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x0e,0x7d]
+
+v_cmpx_o_f16 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0x0e,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_o_f32 v1, v2
+// GFX12: encoding: [0x01,0x05,0x2e,0x7d]
+
+v_cmpx_o_f32 v255, v2
+// GFX12: encoding: [0xff,0x05,0x2e,0x7d]
+
+v_cmpx_o_f32 s1, v2
+// GFX12: encoding: [0x01,0x04,0x2e,0x7d]
+
+v_cmpx_o_f32 s105, v2
+// GFX12: encoding: [0x69,0x04,0x2e,0x7d]
+
+v_cmpx_o_f32 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x2e,0x7d]
+
+v_cmpx_o_f32 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x2e,0x7d]
+
+v_cmpx_o_f32 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x2e,0x7d]
+
+v_cmpx_o_f32 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x2e,0x7d]
+
+v_cmpx_o_f32 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x2e,0x7d]
+
+v_cmpx_o_f32 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x2e,0x7d]
+
+v_cmpx_o_f32 null, v2
+// GFX12: encoding: [0x7c,0x04,0x2e,0x7d]
+
+v_cmpx_o_f32 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x2e,0x7d]
+
+v_cmpx_o_f32 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x2e,0x7d]
+
+v_cmpx_o_f32 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x2e,0x7d]
+
+v_cmpx_o_f32 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x2f,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_o_f64 v[1:2], v[2:3]
+// GFX12: encoding: [0x01,0x05,0x4e,0x7d]
+
+v_cmpx_o_f64 v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0x4e,0x7d]
+
+v_cmpx_o_f64 s[2:3], v[2:3]
+// GFX12: encoding: [0x02,0x04,0x4e,0x7d]
+
+v_cmpx_o_f64 s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0x4e,0x7d]
+
+v_cmpx_o_f64 vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0x4e,0x7d]
+
+v_cmpx_o_f64 ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0x4e,0x7d]
+
+v_cmpx_o_f64 exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0x4e,0x7d]
+
+v_cmpx_o_f64 null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0x4e,0x7d]
+
+v_cmpx_o_f64 -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0x4e,0x7d]
+
+v_cmpx_o_f64 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0x4e,0x7d]
+
+v_cmpx_o_f64 src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0x4e,0x7d]
+
+v_cmpx_o_f64 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0x4f,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_u_f16 v1, v2
+// GFX12: encoding: [0x01,0x05,0x10,0x7d]
+
+v_cmpx_u_f16 v127, v2
+// GFX12: encoding: [0x7f,0x05,0x10,0x7d]
+
+v_cmpx_u_f16 s1, v2
+// GFX12: encoding: [0x01,0x04,0x10,0x7d]
+
+v_cmpx_u_f16 s105, v2
+// GFX12: encoding: [0x69,0x04,0x10,0x7d]
+
+v_cmpx_u_f16 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x10,0x7d]
+
+v_cmpx_u_f16 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x10,0x7d]
+
+v_cmpx_u_f16 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x10,0x7d]
+
+v_cmpx_u_f16 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x10,0x7d]
+
+v_cmpx_u_f16 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x10,0x7d]
+
+v_cmpx_u_f16 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x10,0x7d]
+
+v_cmpx_u_f16 null, v2
+// GFX12: encoding: [0x7c,0x04,0x10,0x7d]
+
+v_cmpx_u_f16 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x10,0x7d]
+
+v_cmpx_u_f16 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x10,0x7d]
+
+v_cmpx_u_f16 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x10,0x7d]
+
+v_cmpx_u_f16 0xfe0b, v127
+// GFX12: encoding: [0xff,0xfe,0x10,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_u_f32 v1, v2
+// GFX12: encoding: [0x01,0x05,0x30,0x7d]
+
+v_cmpx_u_f32 v255, v2
+// GFX12: encoding: [0xff,0x05,0x30,0x7d]
+
+v_cmpx_u_f32 s1, v2
+// GFX12: encoding: [0x01,0x04,0x30,0x7d]
+
+v_cmpx_u_f32 s105, v2
+// GFX12: encoding: [0x69,0x04,0x30,0x7d]
+
+v_cmpx_u_f32 vcc_lo, v2
+// GFX12: encoding: [0x6a,0x04,0x30,0x7d]
+
+v_cmpx_u_f32 vcc_hi, v2
+// GFX12: encoding: [0x6b,0x04,0x30,0x7d]
+
+v_cmpx_u_f32 ttmp15, v2
+// GFX12: encoding: [0x7b,0x04,0x30,0x7d]
+
+v_cmpx_u_f32 m0, v2
+// GFX12: encoding: [0x7d,0x04,0x30,0x7d]
+
+v_cmpx_u_f32 exec_lo, v2
+// GFX12: encoding: [0x7e,0x04,0x30,0x7d]
+
+v_cmpx_u_f32 exec_hi, v2
+// GFX12: encoding: [0x7f,0x04,0x30,0x7d]
+
+v_cmpx_u_f32 null, v2
+// GFX12: encoding: [0x7c,0x04,0x30,0x7d]
+
+v_cmpx_u_f32 -1, v2
+// GFX12: encoding: [0xc1,0x04,0x30,0x7d]
+
+v_cmpx_u_f32 0.5, v2
+// GFX12: encoding: [0xf0,0x04,0x30,0x7d]
+
+v_cmpx_u_f32 src_scc, v2
+// GFX12: encoding: [0xfd,0x04,0x30,0x7d]
+
+v_cmpx_u_f32 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x31,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_u_f64 v[1:2], v[2:3]
+// GFX12: encoding: [0x01,0x05,0x50,0x7d]
+
+v_cmpx_u_f64 v[254:255], v[2:3]
+// GFX12: encoding: [0xfe,0x05,0x50,0x7d]
+
+v_cmpx_u_f64 s[2:3], v[2:3]
+// GFX12: encoding: [0x02,0x04,0x50,0x7d]
+
+v_cmpx_u_f64 s[104:105], v[2:3]
+// GFX12: encoding: [0x68,0x04,0x50,0x7d]
+
+v_cmpx_u_f64 vcc, v[2:3]
+// GFX12: encoding: [0x6a,0x04,0x50,0x7d]
+
+v_cmpx_u_f64 ttmp[14:15], v[2:3]
+// GFX12: encoding: [0x7a,0x04,0x50,0x7d]
+
+v_cmpx_u_f64 exec, v[2:3]
+// GFX12: encoding: [0x7e,0x04,0x50,0x7d]
+
+v_cmpx_u_f64 null, v[2:3]
+// GFX12: encoding: [0x7c,0x04,0x50,0x7d]
+
+v_cmpx_u_f64 -1, v[2:3]
+// GFX12: encoding: [0xc1,0x04,0x50,0x7d]
+
+v_cmpx_u_f64 0.5, v[2:3]
+// GFX12: encoding: [0xf0,0x04,0x50,0x7d]
+
+v_cmpx_u_f64 src_scc, v[2:3]
+// GFX12: encoding: [0xfd,0x04,0x50,0x7d]
+
+v_cmpx_u_f64 0xaf123456, v[254:255]
+// GFX12: encoding: [0xff,0xfc,0x51,0x7d,0x56,0x34,0x12,0xaf]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp16.s
new file mode 100644
index 000000000000..1243e6b0cecb
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp16.s
@@ -0,0 +1,2270 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
+
+v_cmpx_class_f16_dpp v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_class_f16 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0xfa,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_class_f16 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_class_f16 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_class_f16 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_class_f16 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_class_f16 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_class_f16 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_class_f16 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_class_f16 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_class_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_class_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_class_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_class_f16 -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xfa,0x7d,0x7f,0x6f,0x35,0x30]
+
+v_cmpx_class_f32 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0xfc,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_class_f32 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0xfc,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_class_f32 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0xfc,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_class_f32 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0xfc,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_class_f32 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0xfc,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_class_f32 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0xfc,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_class_f32 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0xfc,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_class_f32 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0xfc,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_class_f32 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0xfc,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_class_f32 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0xfc,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_class_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0xfc,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_class_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0xfc,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_class_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0xfc,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_class_f32 -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0xfd,0x7d,0xff,0x6f,0x35,0x30]
+
+v_cmpx_eq_f16 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x04,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_eq_f16 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x04,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_eq_f16 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x04,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_eq_f16 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x04,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_eq_f16 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x04,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_eq_f16 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x04,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_eq_f16 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x04,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_eq_f16 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x04,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_eq_f16 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x04,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_eq_f16 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x04,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_eq_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x04,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_eq_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x04,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_eq_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x04,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_eq_f16 -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x04,0x7d,0x7f,0x6f,0xf5,0x30]
+
+v_cmpx_eq_f32 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x24,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_eq_f32 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x24,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_eq_f32 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x24,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_eq_f32 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x24,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_eq_f32 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x24,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_eq_f32 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x24,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_eq_f32 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x24,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_eq_f32 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x24,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_eq_f32 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x24,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_eq_f32 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x24,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_eq_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x24,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_eq_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x24,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_eq_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x24,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_eq_f32 -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x25,0x7d,0xff,0x6f,0xf5,0x30]
+
+v_cmpx_eq_i16 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x64,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_eq_i16 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x64,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_eq_i16 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x64,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_eq_i16 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x64,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_eq_i16 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x64,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_eq_i16 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x64,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_eq_i16 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x64,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_eq_i16 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x64,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_eq_i16 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x64,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_eq_i16 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x64,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_eq_i16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x64,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_eq_i16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x64,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_eq_i16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x64,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_eq_i16 v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x64,0x7d,0x7f,0x6f,0x05,0x30]
+
+v_cmpx_eq_i32 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x84,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_eq_i32 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x84,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_eq_i32 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x84,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_eq_i32 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x84,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_eq_i32 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x84,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_eq_i32 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x84,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_eq_i32 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x84,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_eq_i32 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x84,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_eq_i32 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x84,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_eq_i32 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x84,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_eq_i32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x84,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_eq_i32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x84,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_eq_i32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x84,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_eq_i32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x85,0x7d,0xff,0x6f,0x05,0x30]
+
+v_cmpx_eq_u16 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x74,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_eq_u16 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x74,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_eq_u16 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x74,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_eq_u16 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x74,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_eq_u16 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x74,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_eq_u16 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x74,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_eq_u16 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x74,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_eq_u16 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x74,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_eq_u16 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x74,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_eq_u16 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x74,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_eq_u16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x74,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_eq_u16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x74,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_eq_u16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x74,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_eq_u16 v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x74,0x7d,0x7f,0x6f,0x05,0x30]
+
+v_cmpx_eq_u32 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x94,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_eq_u32 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x94,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_eq_u32 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x94,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_eq_u32 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x94,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_eq_u32 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x94,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_eq_u32 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x94,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_eq_u32 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x94,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_eq_u32 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x94,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_eq_u32 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x94,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_eq_u32 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x94,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_eq_u32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x94,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_eq_u32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x94,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_eq_u32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x94,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_eq_u32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x95,0x7d,0xff,0x6f,0x05,0x30]
+
+v_cmpx_ge_f16 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0c,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_ge_f16 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0c,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_ge_f16 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0c,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_ge_f16 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0c,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_ge_f16 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0c,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_ge_f16 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0c,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_ge_f16 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0c,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_ge_f16 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0c,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_ge_f16 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0c,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_ge_f16 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0c,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_ge_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0c,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_ge_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0c,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_ge_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0c,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_ge_f16 -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x0c,0x7d,0x7f,0x6f,0xf5,0x30]
+
+v_cmpx_ge_f32 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x2c,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_ge_f32 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x2c,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_ge_f32 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x2c,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_ge_f32 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x2c,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_ge_f32 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x2c,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_ge_f32 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x2c,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_ge_f32 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x2c,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_ge_f32 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x2c,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_ge_f32 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x2c,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_ge_f32 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x2c,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_ge_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x2c,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_ge_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x2c,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_ge_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x2c,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_ge_f32 -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x2d,0x7d,0xff,0x6f,0xf5,0x30]
+
+v_cmpx_ge_i16 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x6c,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_ge_i16 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x6c,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_ge_i16 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x6c,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_ge_i16 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x6c,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_ge_i16 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x6c,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_ge_i16 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x6c,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_ge_i16 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x6c,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_ge_i16 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x6c,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_ge_i16 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x6c,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_ge_i16 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x6c,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_ge_i16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x6c,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_ge_i16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x6c,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_ge_i16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x6c,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_ge_i16 v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x6c,0x7d,0x7f,0x6f,0x05,0x30]
+
+v_cmpx_ge_i32 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x8c,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_ge_i32 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x8c,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_ge_i32 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x8c,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_ge_i32 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x8c,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_ge_i32 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x8c,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_ge_i32 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x8c,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_ge_i32 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x8c,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_ge_i32 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x8c,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_ge_i32 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x8c,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_ge_i32 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x8c,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_ge_i32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x8c,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_ge_i32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x8c,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_ge_i32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x8c,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_ge_i32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x8d,0x7d,0xff,0x6f,0x05,0x30]
+
+v_cmpx_ge_u16 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x7c,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_ge_u16 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x7c,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_ge_u16 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x7c,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_ge_u16 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x7c,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_ge_u16 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x7c,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_ge_u16 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x7c,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_ge_u16 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x7c,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_ge_u16 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x7c,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_ge_u16 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x7c,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_ge_u16 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x7c,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_ge_u16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x7c,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_ge_u16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x7c,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_ge_u16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x7c,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_ge_u16 v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x7c,0x7d,0x7f,0x6f,0x05,0x30]
+
+v_cmpx_ge_u32 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x9c,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_ge_u32 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x9c,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_ge_u32 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x9c,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_ge_u32 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x9c,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_ge_u32 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x9c,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_ge_u32 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x9c,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_ge_u32 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x9c,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_ge_u32 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x9c,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_ge_u32 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x9c,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_ge_u32 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x9c,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_ge_u32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x9c,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_ge_u32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x9c,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_ge_u32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x9c,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_ge_u32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x9d,0x7d,0xff,0x6f,0x05,0x30]
+
+v_cmpx_gt_f16 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x08,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_gt_f16 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x08,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_gt_f16 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x08,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_gt_f16 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x08,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_gt_f16 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x08,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_gt_f16 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x08,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_gt_f16 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x08,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_gt_f16 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x08,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_gt_f16 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x08,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_gt_f16 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x08,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_gt_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x08,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_gt_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x08,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_gt_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x08,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_gt_f16 -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x08,0x7d,0x7f,0x6f,0xf5,0x30]
+
+v_cmpx_gt_f32 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x28,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_gt_f32 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x28,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_gt_f32 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x28,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_gt_f32 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x28,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_gt_f32 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x28,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_gt_f32 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x28,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_gt_f32 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x28,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_gt_f32 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x28,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_gt_f32 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x28,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_gt_f32 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x28,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_gt_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x28,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_gt_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x28,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_gt_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x28,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_gt_f32 -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x29,0x7d,0xff,0x6f,0xf5,0x30]
+
+v_cmpx_gt_i16 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x68,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_gt_i16 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x68,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_gt_i16 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x68,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_gt_i16 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x68,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_gt_i16 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x68,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_gt_i16 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x68,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_gt_i16 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x68,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_gt_i16 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x68,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_gt_i16 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x68,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_gt_i16 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x68,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_gt_i16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x68,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_gt_i16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x68,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_gt_i16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x68,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_gt_i16 v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x68,0x7d,0x7f,0x6f,0x05,0x30]
+
+v_cmpx_gt_i32 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x88,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_gt_i32 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x88,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_gt_i32 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x88,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_gt_i32 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x88,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_gt_i32 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x88,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_gt_i32 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x88,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_gt_i32 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x88,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_gt_i32 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x88,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_gt_i32 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x88,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_gt_i32 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x88,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_gt_i32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x88,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_gt_i32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x88,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_gt_i32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x88,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_gt_i32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x89,0x7d,0xff,0x6f,0x05,0x30]
+
+v_cmpx_gt_u16 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x78,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_gt_u16 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x78,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_gt_u16 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x78,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_gt_u16 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x78,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_gt_u16 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x78,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_gt_u16 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x78,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_gt_u16 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x78,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_gt_u16 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x78,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_gt_u16 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x78,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_gt_u16 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x78,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_gt_u16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x78,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_gt_u16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x78,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_gt_u16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x78,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_gt_u16 v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x78,0x7d,0x7f,0x6f,0x05,0x30]
+
+v_cmpx_gt_u32 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x98,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_gt_u32 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x98,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_gt_u32 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x98,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_gt_u32 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x98,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_gt_u32 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x98,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_gt_u32 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x98,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_gt_u32 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x98,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_gt_u32 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x98,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_gt_u32 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x98,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_gt_u32 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x98,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_gt_u32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x98,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_gt_u32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x98,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_gt_u32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x98,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_gt_u32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x99,0x7d,0xff,0x6f,0x05,0x30]
+
+v_cmpx_le_f16 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x06,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_le_f16 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x06,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_le_f16 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x06,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_le_f16 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x06,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_le_f16 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x06,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_le_f16 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x06,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_le_f16 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x06,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_le_f16 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x06,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_le_f16 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x06,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_le_f16 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x06,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_le_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x06,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_le_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x06,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_le_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x06,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_le_f16 -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x06,0x7d,0x7f,0x6f,0xf5,0x30]
+
+v_cmpx_le_f32 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x26,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_le_f32 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x26,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_le_f32 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x26,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_le_f32 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x26,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_le_f32 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x26,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_le_f32 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x26,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_le_f32 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x26,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_le_f32 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x26,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_le_f32 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x26,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_le_f32 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x26,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_le_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x26,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_le_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x26,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_le_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x26,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_le_f32 -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x27,0x7d,0xff,0x6f,0xf5,0x30]
+
+v_cmpx_le_i16 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x66,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_le_i16 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x66,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_le_i16 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x66,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_le_i16 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x66,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_le_i16 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x66,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_le_i16 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x66,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_le_i16 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x66,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_le_i16 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x66,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_le_i16 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x66,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_le_i16 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x66,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_le_i16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x66,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_le_i16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x66,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_le_i16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x66,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_le_i16 v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x66,0x7d,0x7f,0x6f,0x05,0x30]
+
+v_cmpx_le_i32 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x86,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_le_i32 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x86,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_le_i32 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x86,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_le_i32 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x86,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_le_i32 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x86,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_le_i32 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x86,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_le_i32 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x86,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_le_i32 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x86,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_le_i32 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x86,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_le_i32 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x86,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_le_i32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x86,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_le_i32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x86,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_le_i32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x86,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_le_i32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x87,0x7d,0xff,0x6f,0x05,0x30]
+
+v_cmpx_le_u16 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x76,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_le_u16 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x76,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_le_u16 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x76,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_le_u16 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x76,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_le_u16 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x76,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_le_u16 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x76,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_le_u16 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x76,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_le_u16 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x76,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_le_u16 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x76,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_le_u16 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x76,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_le_u16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x76,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_le_u16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x76,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_le_u16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x76,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_le_u16 v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x76,0x7d,0x7f,0x6f,0x05,0x30]
+
+v_cmpx_le_u32 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x96,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_le_u32 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x96,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_le_u32 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x96,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_le_u32 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x96,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_le_u32 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x96,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_le_u32 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x96,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_le_u32 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x96,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_le_u32 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x96,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_le_u32 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x96,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_le_u32 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x96,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_le_u32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x96,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_le_u32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x96,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_le_u32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x96,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_le_u32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x97,0x7d,0xff,0x6f,0x05,0x30]
+
+v_cmpx_lg_f16 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_lg_f16 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0a,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_lg_f16 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_lg_f16 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0a,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_lg_f16 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_lg_f16 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_lg_f16 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_lg_f16 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_lg_f16 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_lg_f16 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0a,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_lg_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0a,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_lg_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0a,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_lg_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0a,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_lg_f16 -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x0a,0x7d,0x7f,0x6f,0xf5,0x30]
+
+v_cmpx_lg_f32 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x2a,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_lg_f32 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x2a,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_lg_f32 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x2a,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_lg_f32 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x2a,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_lg_f32 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x2a,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_lg_f32 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x2a,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_lg_f32 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x2a,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_lg_f32 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x2a,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_lg_f32 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x2a,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_lg_f32 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x2a,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_lg_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x2a,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_lg_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x2a,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_lg_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x2a,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_lg_f32 -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x2b,0x7d,0xff,0x6f,0xf5,0x30]
+
+v_cmpx_lt_f16 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x02,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_lt_f16 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x02,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_lt_f16 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x02,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_lt_f16 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x02,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_lt_f16 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x02,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_lt_f16 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x02,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_lt_f16 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x02,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_lt_f16 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x02,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_lt_f16 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x02,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_lt_f16 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x02,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_lt_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x02,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_lt_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x02,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_lt_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x02,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_lt_f16 -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x02,0x7d,0x7f,0x6f,0xf5,0x30]
+
+v_cmpx_lt_f32 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x22,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_lt_f32 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x22,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_lt_f32 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x22,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_lt_f32 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x22,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_lt_f32 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x22,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_lt_f32 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x22,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_lt_f32 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x22,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_lt_f32 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x22,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_lt_f32 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x22,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_lt_f32 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x22,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_lt_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x22,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_lt_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x22,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_lt_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x22,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_lt_f32 -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x23,0x7d,0xff,0x6f,0xf5,0x30]
+
+v_cmpx_lt_i16 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x62,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_lt_i16 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x62,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_lt_i16 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x62,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_lt_i16 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x62,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_lt_i16 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x62,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_lt_i16 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x62,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_lt_i16 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x62,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_lt_i16 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x62,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_lt_i16 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x62,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_lt_i16 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x62,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_lt_i16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x62,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_lt_i16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x62,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_lt_i16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x62,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_lt_i16 v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x62,0x7d,0x7f,0x6f,0x05,0x30]
+
+v_cmpx_lt_i32 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x82,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_lt_i32 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x82,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_lt_i32 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x82,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_lt_i32 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x82,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_lt_i32 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x82,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_lt_i32 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x82,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_lt_i32 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x82,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_lt_i32 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x82,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_lt_i32 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x82,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_lt_i32 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x82,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_lt_i32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x82,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_lt_i32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x82,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_lt_i32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x82,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_lt_i32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x83,0x7d,0xff,0x6f,0x05,0x30]
+
+v_cmpx_lt_u16 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x72,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_lt_u16 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x72,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_lt_u16 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x72,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_lt_u16 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x72,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_lt_u16 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x72,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_lt_u16 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x72,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_lt_u16 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x72,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_lt_u16 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x72,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_lt_u16 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x72,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_lt_u16 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x72,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_lt_u16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x72,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_lt_u16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x72,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_lt_u16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x72,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_lt_u16 v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x72,0x7d,0x7f,0x6f,0x05,0x30]
+
+v_cmpx_lt_u32 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x92,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_lt_u32 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x92,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_lt_u32 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x92,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_lt_u32 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x92,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_lt_u32 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x92,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_lt_u32 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x92,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_lt_u32 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x92,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_lt_u32 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x92,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_lt_u32 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x92,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_lt_u32 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x92,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_lt_u32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x92,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_lt_u32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x92,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_lt_u32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x92,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_lt_u32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x93,0x7d,0xff,0x6f,0x05,0x30]
+
+v_cmpx_ne_i16 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x6a,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_ne_i16 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x6a,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_ne_i16 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x6a,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_ne_i16 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x6a,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_ne_i16 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x6a,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_ne_i16 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x6a,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_ne_i16 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x6a,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_ne_i16 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x6a,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_ne_i16 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x6a,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_ne_i16 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x6a,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_ne_i16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x6a,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_ne_i16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x6a,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_ne_i16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x6a,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_ne_i16 v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x6a,0x7d,0x7f,0x6f,0x05,0x30]
+
+v_cmpx_ne_i32 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x8a,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_ne_i32 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x8a,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_ne_i32 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x8a,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_ne_i32 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x8a,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_ne_i32 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x8a,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_ne_i32 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x8a,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_ne_i32 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x8a,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_ne_i32 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x8a,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_ne_i32 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x8a,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_ne_i32 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x8a,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_ne_i32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x8a,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_ne_i32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x8a,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_ne_i32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x8a,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_ne_i32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x8b,0x7d,0xff,0x6f,0x05,0x30]
+
+v_cmpx_ne_u16 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x7a,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_ne_u16 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x7a,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_ne_u16 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x7a,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_ne_u16 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x7a,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_ne_u16 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x7a,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_ne_u16 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x7a,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_ne_u16 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x7a,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_ne_u16 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x7a,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_ne_u16 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x7a,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_ne_u16 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x7a,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_ne_u16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x7a,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_ne_u16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x7a,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_ne_u16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x7a,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_ne_u16 v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x7a,0x7d,0x7f,0x6f,0x05,0x30]
+
+v_cmpx_ne_u32 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x9a,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_ne_u32 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x9a,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_ne_u32 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x9a,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_ne_u32 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x9a,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_ne_u32 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x9a,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_ne_u32 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x9a,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_ne_u32 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x9a,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_ne_u32 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x9a,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_ne_u32 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x9a,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_ne_u32 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x9a,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_ne_u32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x9a,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_ne_u32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x9a,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_ne_u32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x9a,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_ne_u32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x9b,0x7d,0xff,0x6f,0x05,0x30]
+
+v_cmpx_neq_f16 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x1a,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_neq_f16 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x1a,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_neq_f16 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x1a,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_neq_f16 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x1a,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_neq_f16 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x1a,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_neq_f16 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x1a,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_neq_f16 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x1a,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_neq_f16 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x1a,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_neq_f16 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x1a,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_neq_f16 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x1a,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_neq_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x1a,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_neq_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x1a,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_neq_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x1a,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_neq_f16 -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x1a,0x7d,0x7f,0x6f,0xf5,0x30]
+
+v_cmpx_neq_f32 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x3a,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_neq_f32 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x3a,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_neq_f32 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x3a,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_neq_f32 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x3a,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_neq_f32 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x3a,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_neq_f32 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x3a,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_neq_f32 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x3a,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_neq_f32 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x3a,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_neq_f32 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x3a,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_neq_f32 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x3a,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_neq_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x3a,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_neq_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x3a,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_neq_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x3a,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_neq_f32 -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x3b,0x7d,0xff,0x6f,0xf5,0x30]
+
+v_cmpx_nge_f16 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x12,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_nge_f16 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x12,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_nge_f16 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x12,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_nge_f16 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x12,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_nge_f16 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x12,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_nge_f16 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x12,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_nge_f16 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x12,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_nge_f16 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x12,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_nge_f16 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x12,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_nge_f16 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x12,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_nge_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x12,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_nge_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x12,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_nge_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x12,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_nge_f16 -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x12,0x7d,0x7f,0x6f,0xf5,0x30]
+
+v_cmpx_nge_f32 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x32,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_nge_f32 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x32,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_nge_f32 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x32,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_nge_f32 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x32,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_nge_f32 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x32,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_nge_f32 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x32,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_nge_f32 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x32,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_nge_f32 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x32,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_nge_f32 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x32,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_nge_f32 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x32,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_nge_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x32,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_nge_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x32,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_nge_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x32,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_nge_f32 -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x33,0x7d,0xff,0x6f,0xf5,0x30]
+
+v_cmpx_ngt_f16 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x16,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_ngt_f16 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x16,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_ngt_f16 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x16,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_ngt_f16 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x16,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_ngt_f16 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x16,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_ngt_f16 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x16,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_ngt_f16 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x16,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_ngt_f16 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x16,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_ngt_f16 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x16,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_ngt_f16 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x16,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_ngt_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x16,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_ngt_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x16,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_ngt_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x16,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_ngt_f16 -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x16,0x7d,0x7f,0x6f,0xf5,0x30]
+
+v_cmpx_ngt_f32 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x36,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_ngt_f32 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x36,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_ngt_f32 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x36,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_ngt_f32 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x36,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_ngt_f32 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x36,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_ngt_f32 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x36,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_ngt_f32 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x36,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_ngt_f32 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x36,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_ngt_f32 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x36,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_ngt_f32 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x36,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_ngt_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x36,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_ngt_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x36,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_ngt_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x36,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_ngt_f32 -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x37,0x7d,0xff,0x6f,0xf5,0x30]
+
+v_cmpx_nle_f16 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x18,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_nle_f16 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x18,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_nle_f16 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x18,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_nle_f16 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x18,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_nle_f16 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x18,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_nle_f16 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x18,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_nle_f16 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x18,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_nle_f16 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x18,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_nle_f16 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x18,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_nle_f16 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x18,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_nle_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x18,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_nle_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x18,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_nle_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x18,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_nle_f16 -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x18,0x7d,0x7f,0x6f,0xf5,0x30]
+
+v_cmpx_nle_f32 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x38,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_nle_f32 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x38,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_nle_f32 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x38,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_nle_f32 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x38,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_nle_f32 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x38,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_nle_f32 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x38,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_nle_f32 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x38,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_nle_f32 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x38,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_nle_f32 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x38,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_nle_f32 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x38,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_nle_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x38,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_nle_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x38,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_nle_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x38,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_nle_f32 -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x39,0x7d,0xff,0x6f,0xf5,0x30]
+
+v_cmpx_nlg_f16 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x14,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_nlg_f16 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x14,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_nlg_f16 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x14,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_nlg_f16 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x14,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_nlg_f16 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x14,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_nlg_f16 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x14,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_nlg_f16 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x14,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_nlg_f16 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x14,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_nlg_f16 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x14,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_nlg_f16 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x14,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_nlg_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x14,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_nlg_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x14,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_nlg_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x14,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_nlg_f16 -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x14,0x7d,0x7f,0x6f,0xf5,0x30]
+
+v_cmpx_nlg_f32 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x34,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_nlg_f32 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x34,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_nlg_f32 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x34,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_nlg_f32 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x34,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_nlg_f32 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x34,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_nlg_f32 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x34,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_nlg_f32 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x34,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_nlg_f32 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x34,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_nlg_f32 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x34,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_nlg_f32 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x34,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_nlg_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x34,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_nlg_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x34,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_nlg_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x34,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_nlg_f32 -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x35,0x7d,0xff,0x6f,0xf5,0x30]
+
+v_cmpx_nlt_f16 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x1c,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_nlt_f16 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x1c,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_nlt_f16 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x1c,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_nlt_f16 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x1c,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_nlt_f16 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x1c,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_nlt_f16 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x1c,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_nlt_f16 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x1c,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_nlt_f16 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x1c,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_nlt_f16 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x1c,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_nlt_f16 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x1c,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_nlt_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x1c,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_nlt_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x1c,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_nlt_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x1c,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_nlt_f16 -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x1c,0x7d,0x7f,0x6f,0xf5,0x30]
+
+v_cmpx_nlt_f32 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x3c,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_nlt_f32 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x3c,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_nlt_f32 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x3c,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_nlt_f32 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x3c,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_nlt_f32 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x3c,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_nlt_f32 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x3c,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_nlt_f32 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x3c,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_nlt_f32 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x3c,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_nlt_f32 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x3c,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_nlt_f32 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x3c,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_nlt_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x3c,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_nlt_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x3c,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_nlt_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x3c,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_nlt_f32 -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x3d,0x7d,0xff,0x6f,0xf5,0x30]
+
+v_cmpx_o_f16 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x0e,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_o_f16 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x0e,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_o_f16 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x0e,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_o_f16 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x0e,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_o_f16 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x0e,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_o_f16 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x0e,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_o_f16 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x0e,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_o_f16 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x0e,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_o_f16 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x0e,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_o_f16 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x0e,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_o_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x0e,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_o_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x0e,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_o_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x0e,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_o_f16 -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x0e,0x7d,0x7f,0x6f,0xf5,0x30]
+
+v_cmpx_o_f32 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x2e,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_o_f32 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x2e,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_o_f32 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x2e,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_o_f32 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x2e,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_o_f32 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x2e,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_o_f32 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x2e,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_o_f32 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x2e,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_o_f32 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x2e,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_o_f32 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x2e,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_o_f32 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x2e,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_o_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x2e,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_o_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x2e,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_o_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x2e,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_o_f32 -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x2f,0x7d,0xff,0x6f,0xf5,0x30]
+
+v_cmpx_u_f16 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x10,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_u_f16 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x10,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_u_f16 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x10,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_u_f16 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x10,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_u_f16 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x10,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_u_f16 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x10,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_u_f16 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x10,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_u_f16 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x10,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_u_f16 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x10,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_u_f16 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x10,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_u_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x10,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_u_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x10,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_u_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x10,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_u_f16 -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x10,0x7d,0x7f,0x6f,0xf5,0x30]
+
+v_cmpx_u_f32 v1, v2 quad_perm:[3,2,1,0]
+// GFX12: encoding: [0xfa,0x04,0x30,0x7d,0x01,0x1b,0x00,0xff]
+
+v_cmpx_u_f32 v1, v2 quad_perm:[0,1,2,3]
+// GFX12: encoding: [0xfa,0x04,0x30,0x7d,0x01,0xe4,0x00,0xff]
+
+v_cmpx_u_f32 v1, v2 row_mirror
+// GFX12: encoding: [0xfa,0x04,0x30,0x7d,0x01,0x40,0x01,0xff]
+
+v_cmpx_u_f32 v1, v2 row_half_mirror
+// GFX12: encoding: [0xfa,0x04,0x30,0x7d,0x01,0x41,0x01,0xff]
+
+v_cmpx_u_f32 v1, v2 row_shl:1
+// GFX12: encoding: [0xfa,0x04,0x30,0x7d,0x01,0x01,0x01,0xff]
+
+v_cmpx_u_f32 v1, v2 row_shl:15
+// GFX12: encoding: [0xfa,0x04,0x30,0x7d,0x01,0x0f,0x01,0xff]
+
+v_cmpx_u_f32 v1, v2 row_shr:1
+// GFX12: encoding: [0xfa,0x04,0x30,0x7d,0x01,0x11,0x01,0xff]
+
+v_cmpx_u_f32 v1, v2 row_shr:15
+// GFX12: encoding: [0xfa,0x04,0x30,0x7d,0x01,0x1f,0x01,0xff]
+
+v_cmpx_u_f32 v1, v2 row_ror:1
+// GFX12: encoding: [0xfa,0x04,0x30,0x7d,0x01,0x21,0x01,0xff]
+
+v_cmpx_u_f32 v1, v2 row_ror:15
+// GFX12: encoding: [0xfa,0x04,0x30,0x7d,0x01,0x2f,0x01,0xff]
+
+v_cmpx_u_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: encoding: [0xfa,0x04,0x30,0x7d,0x01,0x50,0x01,0xff]
+
+v_cmpx_u_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: encoding: [0xfa,0x04,0x30,0x7d,0x01,0x5f,0x01,0x01]
+
+v_cmpx_u_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: encoding: [0xfa,0x04,0x30,0x7d,0x01,0x60,0x09,0x13]
+
+v_cmpx_u_f32 -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: encoding: [0xfa,0xfe,0x31,0x7d,0xff,0x6f,0xf5,0x30]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp8.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp8.s
new file mode 100644
index 000000000000..91a6e2e1de51
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp8.s
@@ -0,0 +1,488 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
+
+v_cmpx_class_f16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0xfa,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_class_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0xfa,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_class_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xfa,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_class_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0xfc,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_class_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0xfc,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_class_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0xfd,0x7d,0xff,0x00,0x00,0x00]
+
+v_cmpx_eq_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x04,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_eq_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x04,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_eq_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x04,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_eq_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x24,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_eq_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x24,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_eq_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x25,0x7d,0xff,0x00,0x00,0x00]
+
+v_cmpx_eq_i16 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x64,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_eq_i16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x64,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_eq_i16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x64,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_eq_i32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x84,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_eq_i32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x84,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_eq_i32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x85,0x7d,0xff,0x00,0x00,0x00]
+
+v_cmpx_eq_u16 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x74,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_eq_u16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x74,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_eq_u16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x74,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_eq_u32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x94,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_eq_u32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x94,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_eq_u32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x95,0x7d,0xff,0x00,0x00,0x00]
+
+v_cmpx_ge_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0c,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_ge_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0c,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_ge_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x0c,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_ge_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x2c,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_ge_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x2c,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_ge_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x2d,0x7d,0xff,0x00,0x00,0x00]
+
+v_cmpx_ge_i16 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x6c,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_ge_i16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x6c,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_ge_i16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x6c,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_ge_i32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x8c,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_ge_i32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x8c,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_ge_i32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x8d,0x7d,0xff,0x00,0x00,0x00]
+
+v_cmpx_ge_u16 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x7c,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_ge_u16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x7c,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_ge_u16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x7c,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_ge_u32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x9c,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_ge_u32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x9c,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_ge_u32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x9d,0x7d,0xff,0x00,0x00,0x00]
+
+v_cmpx_gt_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x08,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_gt_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x08,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_gt_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x08,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_gt_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x28,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_gt_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x28,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_gt_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x29,0x7d,0xff,0x00,0x00,0x00]
+
+v_cmpx_gt_i16 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x68,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_gt_i16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x68,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_gt_i16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x68,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_gt_i32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x88,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_gt_i32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x88,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_gt_i32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x89,0x7d,0xff,0x00,0x00,0x00]
+
+v_cmpx_gt_u16 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x78,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_gt_u16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x78,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_gt_u16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x78,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_gt_u32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x98,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_gt_u32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x98,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_gt_u32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x99,0x7d,0xff,0x00,0x00,0x00]
+
+v_cmpx_le_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x06,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_le_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x06,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_le_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x06,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_le_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x26,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_le_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x26,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_le_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x27,0x7d,0xff,0x00,0x00,0x00]
+
+v_cmpx_le_i16 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x66,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_le_i16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x66,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_le_i16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x66,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_le_i32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x86,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_le_i32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x86,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_le_i32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x87,0x7d,0xff,0x00,0x00,0x00]
+
+v_cmpx_le_u16 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x76,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_le_u16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x76,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_le_u16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x76,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_le_u32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x96,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_le_u32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x96,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_le_u32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x97,0x7d,0xff,0x00,0x00,0x00]
+
+v_cmpx_lg_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0a,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_lg_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0a,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_lg_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x0a,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_lg_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x2a,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_lg_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x2a,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_lg_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x2b,0x7d,0xff,0x00,0x00,0x00]
+
+v_cmpx_lt_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x02,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_lt_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x02,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_lt_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x02,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_lt_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x22,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_lt_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x22,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_lt_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x23,0x7d,0xff,0x00,0x00,0x00]
+
+v_cmpx_lt_i16 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x62,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_lt_i16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x62,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_lt_i16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x62,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_lt_i32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x82,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_lt_i32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x82,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_lt_i32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x83,0x7d,0xff,0x00,0x00,0x00]
+
+v_cmpx_lt_u16 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x72,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_lt_u16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x72,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_lt_u16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x72,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_lt_u32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x92,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_lt_u32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x92,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_lt_u32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x93,0x7d,0xff,0x00,0x00,0x00]
+
+v_cmpx_ne_i16 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x6a,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_ne_i16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x6a,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_ne_i16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x6a,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_ne_i32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x8a,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_ne_i32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x8a,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_ne_i32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x8b,0x7d,0xff,0x00,0x00,0x00]
+
+v_cmpx_ne_u16 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x7a,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_ne_u16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x7a,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_ne_u16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x7a,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_ne_u32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x9a,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_ne_u32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x9a,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_ne_u32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x9b,0x7d,0xff,0x00,0x00,0x00]
+
+v_cmpx_neq_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x1a,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_neq_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x1a,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_neq_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x1a,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_neq_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x3a,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_neq_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x3a,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_neq_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x3b,0x7d,0xff,0x00,0x00,0x00]
+
+v_cmpx_nge_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x12,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_nge_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x12,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_nge_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x12,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_nge_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x32,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_nge_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x32,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_nge_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x33,0x7d,0xff,0x00,0x00,0x00]
+
+v_cmpx_ngt_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x16,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_ngt_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x16,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_ngt_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x16,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_ngt_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x36,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_ngt_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x36,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_ngt_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x37,0x7d,0xff,0x00,0x00,0x00]
+
+v_cmpx_nle_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x18,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_nle_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x18,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_nle_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x18,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_nle_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x38,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_nle_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x38,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_nle_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x39,0x7d,0xff,0x00,0x00,0x00]
+
+v_cmpx_nlg_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x14,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_nlg_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x14,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_nlg_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x14,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_nlg_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x34,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_nlg_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x34,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_nlg_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x35,0x7d,0xff,0x00,0x00,0x00]
+
+v_cmpx_nlt_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x1c,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_nlt_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x1c,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_nlt_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x1c,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_nlt_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x3c,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_nlt_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x3c,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_nlt_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x3d,0x7d,0xff,0x00,0x00,0x00]
+
+v_cmpx_o_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x0e,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_o_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x0e,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_o_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x0e,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_o_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x2e,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_o_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x2e,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_o_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x2f,0x7d,0xff,0x00,0x00,0x00]
+
+v_cmpx_u_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x10,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_u_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x10,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_u_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x10,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_u_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: encoding: [0xe9,0x04,0x30,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_u_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: encoding: [0xea,0x04,0x30,0x7d,0x01,0x77,0x39,0x05]
+
+v_cmpx_u_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: encoding: [0xe9,0xfe,0x31,0x7d,0xff,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_err.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_err.s
new file mode 100644
index 000000000000..b3b7f1340517
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_err.s
@@ -0,0 +1,487 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX12 --implicit-check-not=error %s
+
+v_cmpx_class_f16_e32 v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_eq_f16_e32 v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_eq_i16_e32 v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_eq_u16_e32 v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_ge_f16_e32 v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_ge_i16_e32 v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_ge_u16_e32 v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_gt_f16_e32 v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_gt_i16_e32 v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_gt_u16_e32 v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_le_f16_e32 v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_le_i16_e32 v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_le_u16_e32 v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_lg_f16_e32 v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_lt_f16_e32 v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_lt_i16_e32 v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_lt_u16_e32 v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_ne_i16_e32 v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_ne_u16_e32 v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_neq_f16_e32 v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_nge_f16_e32 v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_ngt_f16_e32 v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_nle_f16_e32 v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_nlg_f16_e32 v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_nlt_f16_e32 v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_o_f16_e32 v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_u_f16_e32 v1, v255
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_class_f16_e32 v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_eq_f16_e32 v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_eq_i16_e32 v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_eq_u16_e32 v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_ge_f16_e32 v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_ge_i16_e32 v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_ge_u16_e32 v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_gt_f16_e32 v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_gt_i16_e32 v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_gt_u16_e32 v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_le_f16_e32 v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_le_i16_e32 v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_le_u16_e32 v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_lg_f16_e32 v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_lt_f16_e32 v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_lt_i16_e32 v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_lt_u16_e32 v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_ne_i16_e32 v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_ne_u16_e32 v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_neq_f16_e32 v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_nge_f16_e32 v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_ngt_f16_e32 v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_nle_f16_e32 v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_nlg_f16_e32 v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_nlt_f16_e32 v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_o_f16_e32 v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_u_f16_e32 v255, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmpx_class_f16_e32 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_eq_f16_e32 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_eq_i16_e32 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_eq_u16_e32 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_ge_f16_e32 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_ge_i16_e32 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_ge_u16_e32 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_gt_f16_e32 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_gt_i16_e32 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_gt_u16_e32 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_le_f16_e32 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_le_i16_e32 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_le_u16_e32 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_lg_f16_e32 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_lt_f16_e32 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_lt_i16_e32 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_lt_u16_e32 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_ne_i16_e32 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_ne_u16_e32 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_neq_f16_e32 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_nge_f16_e32 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_ngt_f16_e32 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_nle_f16_e32 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_nlg_f16_e32 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_nlt_f16_e32 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_o_f16_e32 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_u_f16_e32 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_class_f16_e32 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_eq_f16_e32 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_eq_i16_e32 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_eq_u16_e32 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_ge_f16_e32 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_ge_i16_e32 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_ge_u16_e32 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_gt_f16_e32 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_gt_i16_e32 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_gt_u16_e32 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_le_f16_e32 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_le_i16_e32 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_le_u16_e32 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_lg_f16_e32 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_lt_f16_e32 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_lt_i16_e32 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_lt_u16_e32 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_ne_i16_e32 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_ne_u16_e32 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_neq_f16_e32 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_nge_f16_e32 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_ngt_f16_e32 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_nle_f16_e32 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_nlg_f16_e32 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_nlt_f16_e32 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_o_f16_e32 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_u_f16_e32 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_class_f16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_eq_f16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_eq_i16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_eq_u16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_ge_f16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_ge_i16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_ge_u16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_gt_f16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_gt_i16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_gt_u16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_le_f16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_le_i16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_le_u16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_lg_f16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_lt_f16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_lt_i16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_lt_u16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_ne_i16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_ne_u16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_neq_f16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_nge_f16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_ngt_f16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_nle_f16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_nlg_f16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_nlt_f16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_o_f16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_u_f16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_class_f16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_eq_f16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_eq_i16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_eq_u16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_ge_f16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_ge_i16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_ge_u16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_gt_f16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_gt_i16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_gt_u16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_le_f16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_le_i16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_le_u16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_lg_f16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_lt_f16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_lt_i16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_lt_u16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_ne_i16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_ne_u16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_neq_f16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_nge_f16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_ngt_f16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_nle_f16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_nlg_f16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_nlt_f16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_o_f16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_u_f16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_promote.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_promote.s
new file mode 100644
index 000000000000..1d9603b884e4
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_promote.s
@@ -0,0 +1,487 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX12 %s
+
+v_cmpx_class_f16 v1, v255
+// GFX12: v_cmpx_class_f16_e64
+
+v_cmpx_eq_f16 v1, v255
+// GFX12: v_cmpx_eq_f16_e64
+
+v_cmpx_eq_i16 v1, v255
+// GFX12: v_cmpx_eq_i16_e64
+
+v_cmpx_eq_u16 v1, v255
+// GFX12: v_cmpx_eq_u16_e64
+
+v_cmpx_ge_f16 v1, v255
+// GFX12: v_cmpx_ge_f16_e64
+
+v_cmpx_ge_i16 v1, v255
+// GFX12: v_cmpx_ge_i16_e64
+
+v_cmpx_ge_u16 v1, v255
+// GFX12: v_cmpx_ge_u16_e64
+
+v_cmpx_gt_f16 v1, v255
+// GFX12: v_cmpx_gt_f16_e64
+
+v_cmpx_gt_i16 v1, v255
+// GFX12: v_cmpx_gt_i16_e64
+
+v_cmpx_gt_u16 v1, v255
+// GFX12: v_cmpx_gt_u16_e64
+
+v_cmpx_le_f16 v1, v255
+// GFX12: v_cmpx_le_f16_e64
+
+v_cmpx_le_i16 v1, v255
+// GFX12: v_cmpx_le_i16_e64
+
+v_cmpx_le_u16 v1, v255
+// GFX12: v_cmpx_le_u16_e64
+
+v_cmpx_lg_f16 v1, v255
+// GFX12: v_cmpx_lg_f16_e64
+
+v_cmpx_lt_f16 v1, v255
+// GFX12: v_cmpx_lt_f16_e64
+
+v_cmpx_lt_i16 v1, v255
+// GFX12: v_cmpx_lt_i16_e64
+
+v_cmpx_lt_u16 v1, v255
+// GFX12: v_cmpx_lt_u16_e64
+
+v_cmpx_ne_i16 v1, v255
+// GFX12: v_cmpx_ne_i16_e64
+
+v_cmpx_ne_u16 v1, v255
+// GFX12: v_cmpx_ne_u16_e64
+
+v_cmpx_neq_f16 v1, v255
+// GFX12: v_cmpx_neq_f16_e64
+
+v_cmpx_nge_f16 v1, v255
+// GFX12: v_cmpx_nge_f16_e64
+
+v_cmpx_ngt_f16 v1, v255
+// GFX12: v_cmpx_ngt_f16_e64
+
+v_cmpx_nle_f16 v1, v255
+// GFX12: v_cmpx_nle_f16_e64
+
+v_cmpx_nlg_f16 v1, v255
+// GFX12: v_cmpx_nlg_f16_e64
+
+v_cmpx_nlt_f16 v1, v255
+// GFX12: v_cmpx_nlt_f16_e64
+
+v_cmpx_o_f16 v1, v255
+// GFX12: v_cmpx_o_f16_e64
+
+v_cmpx_u_f16 v1, v255
+// GFX12: v_cmpx_u_f16_e64
+
+v_cmpx_class_f16 v255, v2
+// GFX12: v_cmpx_class_f16_e64
+
+v_cmpx_eq_f16 v255, v2
+// GFX12: v_cmpx_eq_f16_e64
+
+v_cmpx_eq_i16 v255, v2
+// GFX12: v_cmpx_eq_i16_e64
+
+v_cmpx_eq_u16 v255, v2
+// GFX12: v_cmpx_eq_u16_e64
+
+v_cmpx_ge_f16 v255, v2
+// GFX12: v_cmpx_ge_f16_e64
+
+v_cmpx_ge_i16 v255, v2
+// GFX12: v_cmpx_ge_i16_e64
+
+v_cmpx_ge_u16 v255, v2
+// GFX12: v_cmpx_ge_u16_e64
+
+v_cmpx_gt_f16 v255, v2
+// GFX12: v_cmpx_gt_f16_e64
+
+v_cmpx_gt_i16 v255, v2
+// GFX12: v_cmpx_gt_i16_e64
+
+v_cmpx_gt_u16 v255, v2
+// GFX12: v_cmpx_gt_u16_e64
+
+v_cmpx_le_f16 v255, v2
+// GFX12: v_cmpx_le_f16_e64
+
+v_cmpx_le_i16 v255, v2
+// GFX12: v_cmpx_le_i16_e64
+
+v_cmpx_le_u16 v255, v2
+// GFX12: v_cmpx_le_u16_e64
+
+v_cmpx_lg_f16 v255, v2
+// GFX12: v_cmpx_lg_f16_e64
+
+v_cmpx_lt_f16 v255, v2
+// GFX12: v_cmpx_lt_f16_e64
+
+v_cmpx_lt_i16 v255, v2
+// GFX12: v_cmpx_lt_i16_e64
+
+v_cmpx_lt_u16 v255, v2
+// GFX12: v_cmpx_lt_u16_e64
+
+v_cmpx_ne_i16 v255, v2
+// GFX12: v_cmpx_ne_i16_e64
+
+v_cmpx_ne_u16 v255, v2
+// GFX12: v_cmpx_ne_u16_e64
+
+v_cmpx_neq_f16 v255, v2
+// GFX12: v_cmpx_neq_f16_e64
+
+v_cmpx_nge_f16 v255, v2
+// GFX12: v_cmpx_nge_f16_e64
+
+v_cmpx_ngt_f16 v255, v2
+// GFX12: v_cmpx_ngt_f16_e64
+
+v_cmpx_nle_f16 v255, v2
+// GFX12: v_cmpx_nle_f16_e64
+
+v_cmpx_nlg_f16 v255, v2
+// GFX12: v_cmpx_nlg_f16_e64
+
+v_cmpx_nlt_f16 v255, v2
+// GFX12: v_cmpx_nlt_f16_e64
+
+v_cmpx_o_f16 v255, v2
+// GFX12: v_cmpx_o_f16_e64
+
+v_cmpx_u_f16 v255, v2
+// GFX12: v_cmpx_u_f16_e64
+
+v_cmpx_class_f16 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_class_f16_e64
+
+v_cmpx_eq_f16 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_eq_f16_e64
+
+v_cmpx_eq_i16 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_eq_i16_e64
+
+v_cmpx_eq_u16 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_eq_u16_e64
+
+v_cmpx_ge_f16 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_ge_f16_e64
+
+v_cmpx_ge_i16 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_ge_i16_e64
+
+v_cmpx_ge_u16 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_ge_u16_e64
+
+v_cmpx_gt_f16 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_gt_f16_e64
+
+v_cmpx_gt_i16 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_gt_i16_e64
+
+v_cmpx_gt_u16 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_gt_u16_e64
+
+v_cmpx_le_f16 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_le_f16_e64
+
+v_cmpx_le_i16 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_le_i16_e64
+
+v_cmpx_le_u16 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_le_u16_e64
+
+v_cmpx_lg_f16 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_lg_f16_e64
+
+v_cmpx_lt_f16 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_lt_f16_e64
+
+v_cmpx_lt_i16 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_lt_i16_e64
+
+v_cmpx_lt_u16 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_lt_u16_e64
+
+v_cmpx_ne_i16 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_ne_i16_e64
+
+v_cmpx_ne_u16 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_ne_u16_e64
+
+v_cmpx_neq_f16 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_neq_f16_e64
+
+v_cmpx_nge_f16 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_nge_f16_e64
+
+v_cmpx_ngt_f16 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_ngt_f16_e64
+
+v_cmpx_nle_f16 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_nle_f16_e64
+
+v_cmpx_nlg_f16 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_nlg_f16_e64
+
+v_cmpx_nlt_f16 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_nlt_f16_e64
+
+v_cmpx_o_f16 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_o_f16_e64
+
+v_cmpx_u_f16 v1, v255 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_u_f16_e64
+
+v_cmpx_class_f16 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_class_f16_e64
+
+v_cmpx_eq_f16 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_eq_f16_e64
+
+v_cmpx_eq_i16 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_eq_i16_e64
+
+v_cmpx_eq_u16 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_eq_u16_e64
+
+v_cmpx_ge_f16 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_ge_f16_e64
+
+v_cmpx_ge_i16 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_ge_i16_e64
+
+v_cmpx_ge_u16 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_ge_u16_e64
+
+v_cmpx_gt_f16 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_gt_f16_e64
+
+v_cmpx_gt_i16 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_gt_i16_e64
+
+v_cmpx_gt_u16 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_gt_u16_e64
+
+v_cmpx_le_f16 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_le_f16_e64
+
+v_cmpx_le_i16 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_le_i16_e64
+
+v_cmpx_le_u16 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_le_u16_e64
+
+v_cmpx_lg_f16 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_lg_f16_e64
+
+v_cmpx_lt_f16 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_lt_f16_e64
+
+v_cmpx_lt_i16 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_lt_i16_e64
+
+v_cmpx_lt_u16 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_lt_u16_e64
+
+v_cmpx_ne_i16 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_ne_i16_e64
+
+v_cmpx_ne_u16 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_ne_u16_e64
+
+v_cmpx_neq_f16 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_neq_f16_e64
+
+v_cmpx_nge_f16 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_nge_f16_e64
+
+v_cmpx_ngt_f16 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_ngt_f16_e64
+
+v_cmpx_nle_f16 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_nle_f16_e64
+
+v_cmpx_nlg_f16 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_nlg_f16_e64
+
+v_cmpx_nlt_f16 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_nlt_f16_e64
+
+v_cmpx_o_f16 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_o_f16_e64
+
+v_cmpx_u_f16 v255, v2 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_u_f16_e64
+
+v_cmpx_class_f16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_class_f16_e64
+
+v_cmpx_eq_f16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_eq_f16_e64
+
+v_cmpx_eq_i16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_eq_i16_e64
+
+v_cmpx_eq_u16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_eq_u16_e64
+
+v_cmpx_ge_f16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_ge_f16_e64
+
+v_cmpx_ge_i16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_ge_i16_e64
+
+v_cmpx_ge_u16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_ge_u16_e64
+
+v_cmpx_gt_f16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_gt_f16_e64
+
+v_cmpx_gt_i16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_gt_i16_e64
+
+v_cmpx_gt_u16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_gt_u16_e64
+
+v_cmpx_le_f16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_le_f16_e64
+
+v_cmpx_le_i16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_le_i16_e64
+
+v_cmpx_le_u16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_le_u16_e64
+
+v_cmpx_lg_f16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_lg_f16_e64
+
+v_cmpx_lt_f16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_lt_f16_e64
+
+v_cmpx_lt_i16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_lt_i16_e64
+
+v_cmpx_lt_u16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_lt_u16_e64
+
+v_cmpx_ne_i16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_ne_i16_e64
+
+v_cmpx_ne_u16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_ne_u16_e64
+
+v_cmpx_neq_f16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_neq_f16_e64
+
+v_cmpx_nge_f16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_nge_f16_e64
+
+v_cmpx_ngt_f16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_ngt_f16_e64
+
+v_cmpx_nle_f16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_nle_f16_e64
+
+v_cmpx_nlg_f16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_nlg_f16_e64
+
+v_cmpx_nlt_f16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_nlt_f16_e64
+
+v_cmpx_o_f16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_o_f16_e64
+
+v_cmpx_u_f16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_u_f16_e64
+
+v_cmpx_class_f16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_class_f16_e64
+
+v_cmpx_eq_f16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_eq_f16_e64
+
+v_cmpx_eq_i16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_eq_i16_e64
+
+v_cmpx_eq_u16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_eq_u16_e64
+
+v_cmpx_ge_f16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_ge_f16_e64
+
+v_cmpx_ge_i16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_ge_i16_e64
+
+v_cmpx_ge_u16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_ge_u16_e64
+
+v_cmpx_gt_f16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_gt_f16_e64
+
+v_cmpx_gt_i16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_gt_i16_e64
+
+v_cmpx_gt_u16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_gt_u16_e64
+
+v_cmpx_le_f16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_le_f16_e64
+
+v_cmpx_le_i16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_le_i16_e64
+
+v_cmpx_le_u16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_le_u16_e64
+
+v_cmpx_lg_f16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_lg_f16_e64
+
+v_cmpx_lt_f16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_lt_f16_e64
+
+v_cmpx_lt_i16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_lt_i16_e64
+
+v_cmpx_lt_u16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_lt_u16_e64
+
+v_cmpx_ne_i16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_ne_i16_e64
+
+v_cmpx_ne_u16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_ne_u16_e64
+
+v_cmpx_neq_f16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_neq_f16_e64
+
+v_cmpx_nge_f16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_nge_f16_e64
+
+v_cmpx_ngt_f16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_ngt_f16_e64
+
+v_cmpx_nle_f16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_nle_f16_e64
+
+v_cmpx_nlg_f16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_nlg_f16_e64
+
+v_cmpx_nlt_f16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_nlt_f16_e64
+
+v_cmpx_o_f16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_o_f16_e64
+
+v_cmpx_u_f16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_u_f16_e64
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopd.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopd.s
new file mode 100644
index 000000000000..5fb0d2f0d4eb
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopd.s
@@ -0,0 +1,12819 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefixes=W64-ERR --implicit-check-not=error: %s
+
+v_dual_add_f32 v255, v4, v2 :: v_dual_add_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x08,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v1, v2 :: v_dual_add_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x08,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v255, v2 :: v_dual_add_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x08,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v2, v2 :: v_dual_add_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x08,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v3, v2 :: v_dual_add_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x08,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s105, v2 :: v_dual_add_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x08,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s1, v2 :: v_dual_add_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x08,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, ttmp15, v2 :: v_dual_add_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x08,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_hi, v2 :: v_dual_add_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x08,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_lo, v2 :: v_dual_add_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x08,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, m0, v2 :: v_dual_add_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x08,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_hi, v2 :: v_dual_add_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x08,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_add_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x08,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0xaf123456, v2 :: v_dual_add_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x08,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, src_scc, v2 :: v_dual_add_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x08,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0.5, v3 :: v_dual_add_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x08,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, -1, v4 :: v_dual_add_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x08,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v6, null, v5 :: v_dual_add_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x08,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v4, v2 :: v_dual_add_nc_u32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x20,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v1, v2 :: v_dual_add_nc_u32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x20,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v255, v2 :: v_dual_add_nc_u32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x20,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v2, v2 :: v_dual_add_nc_u32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x20,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v3, v2 :: v_dual_add_nc_u32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x20,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s105, v2 :: v_dual_add_nc_u32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x20,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s1, v2 :: v_dual_add_nc_u32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x20,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, ttmp15, v2 :: v_dual_add_nc_u32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x20,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_hi, v2 :: v_dual_add_nc_u32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x20,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_lo, v2 :: v_dual_add_nc_u32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x20,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, m0, v2 :: v_dual_add_nc_u32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x20,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_hi, v2 :: v_dual_add_nc_u32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x20,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_add_nc_u32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x20,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0xaf123456, v2 :: v_dual_add_nc_u32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x20,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, src_scc, v2 :: v_dual_add_nc_u32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x20,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0.5, v3 :: v_dual_add_nc_u32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x20,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, -1, v4 :: v_dual_add_nc_u32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x20,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v6, null, v5 :: v_dual_add_nc_u32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x20,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v4, v2 :: v_dual_and_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x24,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v1, v2 :: v_dual_and_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x24,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v255, v2 :: v_dual_and_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x24,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v2, v2 :: v_dual_and_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x24,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v3, v2 :: v_dual_and_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x24,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s105, v2 :: v_dual_and_b32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x24,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s1, v2 :: v_dual_and_b32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x24,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, ttmp15, v2 :: v_dual_and_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x24,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_hi, v2 :: v_dual_and_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x24,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_lo, v2 :: v_dual_and_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x24,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, m0, v2 :: v_dual_and_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x24,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_hi, v2 :: v_dual_and_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x24,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_and_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x24,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0xaf123456, v2 :: v_dual_and_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x24,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, src_scc, v2 :: v_dual_and_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x24,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0.5, v3 :: v_dual_and_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x24,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, -1, v4 :: v_dual_and_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x24,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v6, null, v5 :: v_dual_and_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x24,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v4, v2 :: v_dual_cndmask_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x12,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v1, v2 :: v_dual_cndmask_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x12,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v255, v2 :: v_dual_cndmask_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x12,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v2, v2 :: v_dual_cndmask_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x12,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v3, v2 :: v_dual_cndmask_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x12,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s105, v2 :: v_dual_cndmask_b32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x12,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s1, v2 :: v_dual_cndmask_b32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x12,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, ttmp15, v2 :: v_dual_cndmask_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0x12,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_hi, v2 :: v_dual_cndmask_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x12,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_lo, v2 :: v_dual_cndmask_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0x12,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, m0, v2 :: v_dual_cndmask_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x12,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_hi, v2 :: v_dual_cndmask_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0x12,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_cndmask_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0x12,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0xaf123456, v2 :: v_dual_cndmask_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x12,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, src_scc, v2 :: v_dual_cndmask_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x12,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0.5, v3 :: v_dual_cndmask_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x12,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, -1, v4 :: v_dual_cndmask_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x12,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v6, null, v5 :: v_dual_cndmask_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x12,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v4, v2 :: v_dual_fmaak_f32 v6, v1, v3, 0xaf123456
+// GFX12: encoding: [0x04,0x05,0x02,0xc9,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v1, v2 :: v_dual_fmaak_f32 v6, v255, v3, 0xaf123456
+// GFX12: encoding: [0x01,0x05,0x02,0xc9,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v255, v2 :: v_dual_fmaak_f32 v6, v2, v3, 0xaf123456
+// GFX12: encoding: [0xff,0x05,0x02,0xc9,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v2, v2 :: v_dual_fmaak_f32 v6, v3, v3, 0xaf123456
+// GFX12: encoding: [0x02,0x05,0x02,0xc9,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v3, v2 :: v_dual_fmaak_f32 v6, v4, v3, 0xaf123456
+// GFX12: encoding: [0x03,0x05,0x02,0xc9,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s105, v2 :: v_dual_fmaak_f32 v6, s105, v3, 0xaf123456
+// GFX12: encoding: [0x69,0x04,0x02,0xc9,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s1, v2 :: v_dual_fmaak_f32 v6, s1, v3, 0xaf123456
+// GFX12: encoding: [0x01,0x04,0x02,0xc9,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, ttmp15, v2 :: v_dual_fmaak_f32 v6, ttmp15, v3, 0xaf123456
+// GFX12: encoding: [0x7b,0x04,0x02,0xc9,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_hi, v2 :: v_dual_fmaak_f32 v6, exec_hi, v3, 0xaf123456
+// GFX12: encoding: [0x7f,0x04,0x02,0xc9,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_lo, v2 :: v_dual_fmaak_f32 v6, exec_lo, v3, 0xaf123456
+// GFX12: encoding: [0x7e,0x04,0x02,0xc9,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, m0, v2 :: v_dual_fmaak_f32 v6, m0, v3, 0xaf123456
+// GFX12: encoding: [0x7d,0x04,0x02,0xc9,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_hi, v2 :: v_dual_fmaak_f32 v6, vcc_hi, v3, 0xaf123456
+// GFX12: encoding: [0x6b,0x04,0x02,0xc9,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_fmaak_f32 v6, vcc_lo, v3, 0xaf123456
+// GFX12: encoding: [0x6a,0x04,0x02,0xc9,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, null, v3, 0xaf123456
+// GFX12: encoding: [0xff,0x04,0x02,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, src_scc, v2 :: v_dual_fmaak_f32 v6, -1, v3, 0xaf123456
+// GFX12: encoding: [0xfd,0x04,0x02,0xc9,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0.5, v3 :: v_dual_fmaak_f32 v6, 0.5, v2, 0xaf123456
+// GFX12: encoding: [0xf0,0x06,0x02,0xc9,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, -1, v4 :: v_dual_fmaak_f32 v6, src_scc, v5, 0xaf123456
+// GFX12: encoding: [0xc1,0x08,0x02,0xc9,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v6, null, v5 :: v_dual_fmaak_f32 v255, 0xaf123456, v4, 0xaf123456
+// GFX12: encoding: [0x7c,0x0a,0x02,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v4, v2 :: v_dual_fmac_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x00,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v1, v2 :: v_dual_fmac_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x00,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v255, v2 :: v_dual_fmac_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x00,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v2, v2 :: v_dual_fmac_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x00,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v3, v2 :: v_dual_fmac_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x00,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s105, v2 :: v_dual_fmac_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x00,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s1, v2 :: v_dual_fmac_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x00,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, ttmp15, v2 :: v_dual_fmac_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x00,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_hi, v2 :: v_dual_fmac_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x00,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_lo, v2 :: v_dual_fmac_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x00,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, m0, v2 :: v_dual_fmac_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x00,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_hi, v2 :: v_dual_fmac_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x00,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_fmac_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x00,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0xaf123456, v2 :: v_dual_fmac_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x00,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, src_scc, v2 :: v_dual_fmac_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x00,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0.5, v3 :: v_dual_fmac_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x00,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, -1, v4 :: v_dual_fmac_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x00,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v6, null, v5 :: v_dual_fmac_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x00,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v4, v255 :: v_dual_fmamk_f32 v6, v1, 0xaf123456, v255
+// GFX12: encoding: [0x04,0xff,0x05,0xc9,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v1, v255 :: v_dual_fmamk_f32 v6, v255, 0xaf123456, v255
+// GFX12: encoding: [0x01,0xff,0x05,0xc9,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v255, v255 :: v_dual_fmamk_f32 v6, v2, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xff,0x05,0xc9,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v2, v255 :: v_dual_fmamk_f32 v6, v3, 0xaf123456, v255
+// GFX12: encoding: [0x02,0xff,0x05,0xc9,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v3, v255 :: v_dual_fmamk_f32 v6, v4, 0xaf123456, v255
+// GFX12: encoding: [0x03,0xff,0x05,0xc9,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s105, v255 :: v_dual_fmamk_f32 v6, s105, 0xaf123456, v255
+// GFX12: encoding: [0x69,0xfe,0x05,0xc9,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s1, v255 :: v_dual_fmamk_f32 v6, s1, 0xaf123456, v255
+// GFX12: encoding: [0x01,0xfe,0x05,0xc9,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, ttmp15, v255 :: v_dual_fmamk_f32 v6, ttmp15, 0xaf123456, v255
+// GFX12: encoding: [0x7b,0xfe,0x05,0xc9,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_hi, v255 :: v_dual_fmamk_f32 v6, exec_hi, 0xaf123456, v255
+// GFX12: encoding: [0x7f,0xfe,0x05,0xc9,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_lo, v255 :: v_dual_fmamk_f32 v6, exec_lo, 0xaf123456, v255
+// GFX12: encoding: [0x7e,0xfe,0x05,0xc9,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, m0, v255 :: v_dual_fmamk_f32 v6, m0, 0xaf123456, v255
+// GFX12: encoding: [0x7d,0xfe,0x05,0xc9,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_hi, v255 :: v_dual_fmamk_f32 v6, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x6b,0xfe,0x05,0xc9,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_lo, v255 :: v_dual_fmamk_f32 v6, vcc_lo, 0xaf123456, v255
+// GFX12: encoding: [0x6a,0xfe,0x05,0xc9,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, null, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x05,0xc9,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, src_scc, v255 :: v_dual_fmamk_f32 v6, -1, 0xaf123456, v255
+// GFX12: encoding: [0xfd,0xfe,0x05,0xc9,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0.5, v3 :: v_dual_fmamk_f32 v6, 0.5, 0xaf123456, v255
+// GFX12: encoding: [0xf0,0x06,0x04,0xc9,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, -1, v4 :: v_dual_fmamk_f32 v6, src_scc, 0xaf123456, v255
+// GFX12: encoding: [0xc1,0x08,0x04,0xc9,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v6, null, v5 :: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x04,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v4, v2 :: v_dual_lshlrev_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x22,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v1, v2 :: v_dual_lshlrev_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x22,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v255, v2 :: v_dual_lshlrev_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x22,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v2, v2 :: v_dual_lshlrev_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x22,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v3, v2 :: v_dual_lshlrev_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x22,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s105, v2 :: v_dual_lshlrev_b32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x22,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s1, v2 :: v_dual_lshlrev_b32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x22,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, ttmp15, v2 :: v_dual_lshlrev_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x22,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_hi, v2 :: v_dual_lshlrev_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x22,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_lo, v2 :: v_dual_lshlrev_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x22,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, m0, v2 :: v_dual_lshlrev_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x22,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_hi, v2 :: v_dual_lshlrev_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x22,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_lshlrev_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x22,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0xaf123456, v2 :: v_dual_lshlrev_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x22,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, src_scc, v2 :: v_dual_lshlrev_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x22,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0.5, v3 :: v_dual_lshlrev_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x22,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, -1, v4 :: v_dual_lshlrev_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x22,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v6, null, v5 :: v_dual_lshlrev_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x22,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v4, v2 :: v_dual_max_num_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x14,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v1, v2 :: v_dual_max_num_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x14,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v255, v2 :: v_dual_max_num_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x14,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v2, v2 :: v_dual_max_num_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x14,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v3, v2 :: v_dual_max_num_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x14,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s105, v2 :: v_dual_max_num_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x14,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s1, v2 :: v_dual_max_num_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x14,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, ttmp15, v2 :: v_dual_max_num_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x14,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_hi, v2 :: v_dual_max_num_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x14,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_lo, v2 :: v_dual_max_num_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x14,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, m0, v2 :: v_dual_max_num_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x14,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_hi, v2 :: v_dual_max_num_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x14,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_max_num_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x14,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0xaf123456, v2 :: v_dual_max_num_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x14,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, src_scc, v2 :: v_dual_max_num_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x14,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0.5, v3 :: v_dual_max_num_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x14,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, -1, v4 :: v_dual_max_num_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x14,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v6, null, v5 :: v_dual_max_num_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x14,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v4, v2 :: v_dual_min_num_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x16,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v1, v2 :: v_dual_min_num_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x16,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v255, v2 :: v_dual_min_num_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x16,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v2, v2 :: v_dual_min_num_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x16,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v3, v2 :: v_dual_min_num_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x16,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s105, v2 :: v_dual_min_num_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x16,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s1, v2 :: v_dual_min_num_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x16,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, ttmp15, v2 :: v_dual_min_num_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x16,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_hi, v2 :: v_dual_min_num_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x16,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_lo, v2 :: v_dual_min_num_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x16,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, m0, v2 :: v_dual_min_num_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x16,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_hi, v2 :: v_dual_min_num_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x16,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_min_num_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x16,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0xaf123456, v2 :: v_dual_min_num_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x16,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, src_scc, v2 :: v_dual_min_num_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x16,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0.5, v3 :: v_dual_min_num_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x16,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, -1, v4 :: v_dual_min_num_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x16,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v6, null, v5 :: v_dual_min_num_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x16,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v4, v255 :: v_dual_mov_b32 v6, v1
+// GFX12: encoding: [0x04,0xff,0x11,0xc9,0x01,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v1, v255 :: v_dual_mov_b32 v6, v255
+// GFX12: encoding: [0x01,0xff,0x11,0xc9,0xff,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v255, v255 :: v_dual_mov_b32 v6, v2
+// GFX12: encoding: [0xff,0xff,0x11,0xc9,0x02,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v2, v255 :: v_dual_mov_b32 v6, v3
+// GFX12: encoding: [0x02,0xff,0x11,0xc9,0x03,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v3, v255 :: v_dual_mov_b32 v6, v4
+// GFX12: encoding: [0x03,0xff,0x11,0xc9,0x04,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s105, v255 :: v_dual_mov_b32 v6, s1
+// GFX12: encoding: [0x69,0xfe,0x11,0xc9,0x01,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s1, v255 :: v_dual_mov_b32 v6, s105
+// GFX12: encoding: [0x01,0xfe,0x11,0xc9,0x69,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, ttmp15, v255 :: v_dual_mov_b32 v6, vcc_lo
+// GFX12: encoding: [0x7b,0xfe,0x11,0xc9,0x6a,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_hi, v255 :: v_dual_mov_b32 v6, vcc_hi
+// GFX12: encoding: [0x7f,0xfe,0x11,0xc9,0x6b,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_lo, v255 :: v_dual_mov_b32 v6, ttmp15
+// GFX12: encoding: [0x7e,0xfe,0x11,0xc9,0x7b,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, m0, v255 :: v_dual_mov_b32 v6, m0
+// GFX12: encoding: [0x7d,0xfe,0x11,0xc9,0x7d,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_hi, v255 :: v_dual_mov_b32 v6, exec_lo
+// GFX12: encoding: [0x6b,0xfe,0x11,0xc9,0x7e,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_lo, v255 :: v_dual_mov_b32 v6, exec_hi
+// GFX12: encoding: [0x6a,0xfe,0x11,0xc9,0x7f,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0xaf123456, v255 :: v_dual_mov_b32 v6, null
+// GFX12: encoding: [0xff,0xfe,0x11,0xc9,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, src_scc, v255 :: v_dual_mov_b32 v6, -1
+// GFX12: encoding: [0xfd,0xfe,0x11,0xc9,0xc1,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0.5, v3 :: v_dual_mov_b32 v6, 0.5
+// GFX12: encoding: [0xf0,0x06,0x10,0xc9,0xf0,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, -1, v4 :: v_dual_mov_b32 v6, src_scc
+// GFX12: encoding: [0xc1,0x08,0x10,0xc9,0xfd,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v6, null, v5 :: v_dual_mov_b32 v255, 0xaf123456
+// GFX12: encoding: [0x7c,0x0a,0x10,0xc9,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v4, v2 :: v_dual_mul_dx9_zero_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x0e,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v1, v2 :: v_dual_mul_dx9_zero_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x0e,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v255, v2 :: v_dual_mul_dx9_zero_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x0e,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v2, v2 :: v_dual_mul_dx9_zero_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x0e,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v3, v2 :: v_dual_mul_dx9_zero_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x0e,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s105, v2 :: v_dual_mul_dx9_zero_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x0e,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s1, v2 :: v_dual_mul_dx9_zero_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x0e,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, ttmp15, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x0e,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x0e,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x0e,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, m0, v2 :: v_dual_mul_dx9_zero_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x0e,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x0e,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x0e,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0xaf123456, v2 :: v_dual_mul_dx9_zero_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x0e,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, src_scc, v2 :: v_dual_mul_dx9_zero_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x0e,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0.5, v3 :: v_dual_mul_dx9_zero_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x0e,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, -1, v4 :: v_dual_mul_dx9_zero_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x0e,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v6, null, v5 :: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x0e,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v4, v2 :: v_dual_mul_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x06,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v1, v2 :: v_dual_mul_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x06,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v255, v2 :: v_dual_mul_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x06,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v2, v2 :: v_dual_mul_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x06,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v3, v2 :: v_dual_mul_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x06,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s105, v2 :: v_dual_mul_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x06,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s1, v2 :: v_dual_mul_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x06,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, ttmp15, v2 :: v_dual_mul_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x06,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_hi, v2 :: v_dual_mul_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x06,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_lo, v2 :: v_dual_mul_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x06,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, m0, v2 :: v_dual_mul_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x06,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_hi, v2 :: v_dual_mul_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x06,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_mul_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x06,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0xaf123456, v2 :: v_dual_mul_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x06,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, src_scc, v2 :: v_dual_mul_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x06,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0.5, v3 :: v_dual_mul_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x06,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, -1, v4 :: v_dual_mul_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x06,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v6, null, v5 :: v_dual_mul_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x06,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v4, v2 :: v_dual_sub_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x0a,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v1, v2 :: v_dual_sub_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x0a,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v255, v2 :: v_dual_sub_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x0a,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v2, v2 :: v_dual_sub_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x0a,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v3, v2 :: v_dual_sub_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x0a,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s105, v2 :: v_dual_sub_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x0a,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s1, v2 :: v_dual_sub_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x0a,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, ttmp15, v2 :: v_dual_sub_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x0a,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_hi, v2 :: v_dual_sub_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x0a,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_lo, v2 :: v_dual_sub_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x0a,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, m0, v2 :: v_dual_sub_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x0a,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_hi, v2 :: v_dual_sub_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x0a,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_sub_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x0a,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0xaf123456, v2 :: v_dual_sub_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x0a,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, src_scc, v2 :: v_dual_sub_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x0a,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0.5, v3 :: v_dual_sub_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x0a,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, -1, v4 :: v_dual_sub_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x0a,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v6, null, v5 :: v_dual_sub_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x0a,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v4, v2 :: v_dual_subrev_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x0c,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v1, v2 :: v_dual_subrev_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x0c,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v255, v2 :: v_dual_subrev_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x0c,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v2, v2 :: v_dual_subrev_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x0c,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, v3, v2 :: v_dual_subrev_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x0c,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s105, v2 :: v_dual_subrev_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x0c,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, s1, v2 :: v_dual_subrev_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x0c,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, ttmp15, v2 :: v_dual_subrev_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x0c,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_hi, v2 :: v_dual_subrev_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x0c,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, exec_lo, v2 :: v_dual_subrev_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x0c,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, m0, v2 :: v_dual_subrev_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x0c,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_hi, v2 :: v_dual_subrev_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x0c,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_subrev_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x0c,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0xaf123456, v2 :: v_dual_subrev_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x0c,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, src_scc, v2 :: v_dual_subrev_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x0c,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, 0.5, v3 :: v_dual_subrev_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x0c,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v255, -1, v4 :: v_dual_subrev_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x0c,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_add_f32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x0c,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v4, v2 :: v_dual_add_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x48,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v1, v2 :: v_dual_add_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x48,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v255, v2 :: v_dual_add_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x48,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v2, v2 :: v_dual_add_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x48,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v3, v2 :: v_dual_add_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x48,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, s105, v2 :: v_dual_add_f32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x48,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, s1, v2 :: v_dual_add_f32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x48,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, ttmp15, v2 :: v_dual_add_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0x48,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, exec_hi, v2 :: v_dual_add_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x48,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, exec_lo, v2 :: v_dual_add_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0x48,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, m0, v2 :: v_dual_add_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x48,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, vcc_hi, v2 :: v_dual_add_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0x48,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, vcc_lo, v2 :: v_dual_add_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0x48,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0xaf123456, v2 :: v_dual_add_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x48,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, src_scc, v2 :: v_dual_add_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x48,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_add_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x48,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, -1, v4 :: v_dual_add_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x48,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v6, null, v5 :: v_dual_add_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x48,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v4, v2 :: v_dual_add_nc_u32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x60,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v1, v2 :: v_dual_add_nc_u32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x60,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v255, v2 :: v_dual_add_nc_u32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x60,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v2, v2 :: v_dual_add_nc_u32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x60,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v3, v2 :: v_dual_add_nc_u32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x60,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, s105, v2 :: v_dual_add_nc_u32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x60,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, s1, v2 :: v_dual_add_nc_u32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x60,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, ttmp15, v2 :: v_dual_add_nc_u32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0x60,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, exec_hi, v2 :: v_dual_add_nc_u32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x60,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, exec_lo, v2 :: v_dual_add_nc_u32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0x60,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, m0, v2 :: v_dual_add_nc_u32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x60,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, vcc_hi, v2 :: v_dual_add_nc_u32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0x60,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, vcc_lo, v2 :: v_dual_add_nc_u32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0x60,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0xaf123456, v2 :: v_dual_add_nc_u32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x60,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, src_scc, v2 :: v_dual_add_nc_u32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x60,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_add_nc_u32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x60,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, -1, v4 :: v_dual_add_nc_u32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x60,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v6, null, v5 :: v_dual_add_nc_u32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x60,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v4, v2 :: v_dual_and_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x64,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v1, v2 :: v_dual_and_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x64,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v255, v2 :: v_dual_and_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x64,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v2, v2 :: v_dual_and_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x64,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v3, v2 :: v_dual_and_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x64,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, s105, v2 :: v_dual_and_b32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x64,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, s1, v2 :: v_dual_and_b32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x64,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, ttmp15, v2 :: v_dual_and_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0x64,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, exec_hi, v2 :: v_dual_and_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x64,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, exec_lo, v2 :: v_dual_and_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0x64,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, m0, v2 :: v_dual_and_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x64,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, vcc_hi, v2 :: v_dual_and_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0x64,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, vcc_lo, v2 :: v_dual_and_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0x64,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0xaf123456, v2 :: v_dual_and_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x64,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, src_scc, v2 :: v_dual_and_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x64,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_and_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x64,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, -1, v4 :: v_dual_and_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x64,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v6, null, v5 :: v_dual_and_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x64,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v4, v2 :: v_dual_cndmask_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x52,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v1, v2 :: v_dual_cndmask_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x52,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v255, v2 :: v_dual_cndmask_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x52,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v2, v2 :: v_dual_cndmask_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x52,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v3, v2 :: v_dual_cndmask_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x52,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, s105, v2 :: v_dual_cndmask_b32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x52,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, s1, v2 :: v_dual_cndmask_b32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x52,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, ttmp15, v2 :: v_dual_cndmask_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0x52,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, exec_hi, v2 :: v_dual_cndmask_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x52,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, exec_lo, v2 :: v_dual_cndmask_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0x52,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, m0, v2 :: v_dual_cndmask_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x52,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, vcc_hi, v2 :: v_dual_cndmask_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0x52,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, vcc_lo, v2 :: v_dual_cndmask_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0x52,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0xaf123456, v2 :: v_dual_cndmask_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x52,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, src_scc, v2 :: v_dual_cndmask_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x52,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_cndmask_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x52,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, -1, v4 :: v_dual_cndmask_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x52,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v6, null, v5 :: v_dual_cndmask_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x52,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v4, v2 :: v_dual_fmaak_f32 v6, v1, v3, 0xaf123456
+// GFX12: encoding: [0x04,0x05,0x42,0xca,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v1, v2 :: v_dual_fmaak_f32 v6, v255, v3, 0xaf123456
+// GFX12: encoding: [0x01,0x05,0x42,0xca,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v255, v2 :: v_dual_fmaak_f32 v6, v2, v3, 0xaf123456
+// GFX12: encoding: [0xff,0x05,0x42,0xca,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v2, v2 :: v_dual_fmaak_f32 v6, v3, v3, 0xaf123456
+// GFX12: encoding: [0x02,0x05,0x42,0xca,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v3, v2 :: v_dual_fmaak_f32 v6, v4, v3, 0xaf123456
+// GFX12: encoding: [0x03,0x05,0x42,0xca,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, null, v3, 0xaf123456
+// GFX12: encoding: [0xff,0x04,0x42,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_fmaak_f32 v6, -1, v2, 0xaf123456
+// GFX12: encoding: [0xf0,0x06,0x42,0xca,0xc1,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, -1, v4 :: v_dual_fmaak_f32 v6, 0.5, v5, 0xaf123456
+// GFX12: encoding: [0xc1,0x08,0x42,0xca,0xf0,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v6, null, v5 :: v_dual_fmaak_f32 v255, 0xaf123456, v4, 0xaf123456
+// GFX12: encoding: [0x7c,0x0a,0x42,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v4, v2 :: v_dual_fmac_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x40,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v1, v2 :: v_dual_fmac_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x40,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v255, v2 :: v_dual_fmac_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x40,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v2, v2 :: v_dual_fmac_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x40,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v3, v2 :: v_dual_fmac_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x40,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, s105, v2 :: v_dual_fmac_f32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x40,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, s1, v2 :: v_dual_fmac_f32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x40,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, ttmp15, v2 :: v_dual_fmac_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0x40,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, exec_hi, v2 :: v_dual_fmac_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x40,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, exec_lo, v2 :: v_dual_fmac_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0x40,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, m0, v2 :: v_dual_fmac_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x40,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, vcc_hi, v2 :: v_dual_fmac_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0x40,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, vcc_lo, v2 :: v_dual_fmac_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0x40,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0xaf123456, v2 :: v_dual_fmac_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x40,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, src_scc, v2 :: v_dual_fmac_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x40,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_fmac_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x40,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, -1, v4 :: v_dual_fmac_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x40,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v6, null, v5 :: v_dual_fmac_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x40,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v4, v255 :: v_dual_fmamk_f32 v6, v1, 0xaf123456, v255
+// GFX12: encoding: [0x04,0xff,0x45,0xca,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v1, v255 :: v_dual_fmamk_f32 v6, v255, 0xaf123456, v255
+// GFX12: encoding: [0x01,0xff,0x45,0xca,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v255, v255 :: v_dual_fmamk_f32 v6, v2, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xff,0x45,0xca,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v2, v255 :: v_dual_fmamk_f32 v6, v3, 0xaf123456, v255
+// GFX12: encoding: [0x02,0xff,0x45,0xca,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v3, v255 :: v_dual_fmamk_f32 v6, v4, 0xaf123456, v255
+// GFX12: encoding: [0x03,0xff,0x45,0xca,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, null, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x45,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_fmamk_f32 v6, -1, 0xaf123456, v255
+// GFX12: encoding: [0xf0,0x06,0x44,0xca,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, -1, v4 :: v_dual_fmamk_f32 v6, 0.5, 0xaf123456, v255
+// GFX12: encoding: [0xc1,0x08,0x44,0xca,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v6, null, v5 :: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x44,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v4, v2 :: v_dual_lshlrev_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x62,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v1, v2 :: v_dual_lshlrev_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x62,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v255, v2 :: v_dual_lshlrev_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x62,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v2, v2 :: v_dual_lshlrev_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x62,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v3, v2 :: v_dual_lshlrev_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x62,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, s105, v2 :: v_dual_lshlrev_b32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x62,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, s1, v2 :: v_dual_lshlrev_b32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x62,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, ttmp15, v2 :: v_dual_lshlrev_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0x62,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, exec_hi, v2 :: v_dual_lshlrev_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x62,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, exec_lo, v2 :: v_dual_lshlrev_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0x62,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, m0, v2 :: v_dual_lshlrev_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x62,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, vcc_hi, v2 :: v_dual_lshlrev_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0x62,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, vcc_lo, v2 :: v_dual_lshlrev_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0x62,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0xaf123456, v2 :: v_dual_lshlrev_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x62,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, src_scc, v2 :: v_dual_lshlrev_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x62,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_lshlrev_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x62,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, -1, v4 :: v_dual_lshlrev_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x62,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v6, null, v5 :: v_dual_lshlrev_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x62,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v4, v2 :: v_dual_max_num_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x54,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v1, v2 :: v_dual_max_num_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x54,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v255, v2 :: v_dual_max_num_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x54,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v2, v2 :: v_dual_max_num_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x54,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v3, v2 :: v_dual_max_num_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x54,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, s105, v2 :: v_dual_max_num_f32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x54,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, s1, v2 :: v_dual_max_num_f32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x54,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, ttmp15, v2 :: v_dual_max_num_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0x54,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, exec_hi, v2 :: v_dual_max_num_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x54,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, exec_lo, v2 :: v_dual_max_num_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0x54,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, m0, v2 :: v_dual_max_num_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x54,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, vcc_hi, v2 :: v_dual_max_num_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0x54,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, vcc_lo, v2 :: v_dual_max_num_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0x54,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0xaf123456, v2 :: v_dual_max_num_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x54,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, src_scc, v2 :: v_dual_max_num_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x54,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_max_num_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x54,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, -1, v4 :: v_dual_max_num_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x54,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v6, null, v5 :: v_dual_max_num_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x54,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v4, v2 :: v_dual_min_num_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x56,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v1, v2 :: v_dual_min_num_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x56,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v255, v2 :: v_dual_min_num_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x56,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v2, v2 :: v_dual_min_num_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x56,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v3, v2 :: v_dual_min_num_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x56,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, s105, v2 :: v_dual_min_num_f32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x56,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, s1, v2 :: v_dual_min_num_f32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x56,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, ttmp15, v2 :: v_dual_min_num_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0x56,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, exec_hi, v2 :: v_dual_min_num_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x56,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, exec_lo, v2 :: v_dual_min_num_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0x56,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, m0, v2 :: v_dual_min_num_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x56,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, vcc_hi, v2 :: v_dual_min_num_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0x56,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, vcc_lo, v2 :: v_dual_min_num_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0x56,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0xaf123456, v2 :: v_dual_min_num_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x56,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, src_scc, v2 :: v_dual_min_num_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x56,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_min_num_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x56,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, -1, v4 :: v_dual_min_num_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x56,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v6, null, v5 :: v_dual_min_num_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x56,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v4, v255 :: v_dual_mov_b32 v6, v1
+// GFX12: encoding: [0x04,0xff,0x51,0xca,0x01,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v1, v255 :: v_dual_mov_b32 v6, v255
+// GFX12: encoding: [0x01,0xff,0x51,0xca,0xff,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v255, v255 :: v_dual_mov_b32 v6, v2
+// GFX12: encoding: [0xff,0xff,0x51,0xca,0x02,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v2, v255 :: v_dual_mov_b32 v6, v3
+// GFX12: encoding: [0x02,0xff,0x51,0xca,0x03,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v3, v255 :: v_dual_mov_b32 v6, v4
+// GFX12: encoding: [0x03,0xff,0x51,0xca,0x04,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, s105, v255 :: v_dual_mov_b32 v6, s105
+// GFX12: encoding: [0x69,0xfe,0x51,0xca,0x69,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, s1, v255 :: v_dual_mov_b32 v6, s1
+// GFX12: encoding: [0x01,0xfe,0x51,0xca,0x01,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, ttmp15, v255 :: v_dual_mov_b32 v6, ttmp15
+// GFX12: encoding: [0x7b,0xfe,0x51,0xca,0x7b,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, exec_hi, v255 :: v_dual_mov_b32 v6, exec_hi
+// GFX12: encoding: [0x7f,0xfe,0x51,0xca,0x7f,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, exec_lo, v255 :: v_dual_mov_b32 v6, exec_lo
+// GFX12: encoding: [0x7e,0xfe,0x51,0xca,0x7e,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, m0, v255 :: v_dual_mov_b32 v6, m0
+// GFX12: encoding: [0x7d,0xfe,0x51,0xca,0x7d,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, vcc_hi, v255 :: v_dual_mov_b32 v6, vcc_hi
+// GFX12: encoding: [0x6b,0xfe,0x51,0xca,0x6b,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, vcc_lo, v255 :: v_dual_mov_b32 v6, vcc_lo
+// GFX12: encoding: [0x6a,0xfe,0x51,0xca,0x6a,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0xaf123456, v255 :: v_dual_mov_b32 v6, null
+// GFX12: encoding: [0xff,0xfe,0x51,0xca,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, src_scc, v255 :: v_dual_mov_b32 v6, -1
+// GFX12: encoding: [0xfd,0xfe,0x51,0xca,0xc1,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_mov_b32 v6, 0.5
+// GFX12: encoding: [0xf0,0x06,0x50,0xca,0xf0,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, -1, v4 :: v_dual_mov_b32 v6, src_scc
+// GFX12: encoding: [0xc1,0x08,0x50,0xca,0xfd,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v6, null, v5 :: v_dual_mov_b32 v255, 0xaf123456
+// GFX12: encoding: [0x7c,0x0a,0x50,0xca,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v4, v2 :: v_dual_mul_dx9_zero_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x4e,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v1, v2 :: v_dual_mul_dx9_zero_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x4e,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v255, v2 :: v_dual_mul_dx9_zero_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x4e,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v2, v2 :: v_dual_mul_dx9_zero_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x4e,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v3, v2 :: v_dual_mul_dx9_zero_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x4e,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, s105, v2 :: v_dual_mul_dx9_zero_f32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x4e,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, s1, v2 :: v_dual_mul_dx9_zero_f32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x4e,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, ttmp15, v2 :: v_dual_mul_dx9_zero_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0x4e,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, exec_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x4e,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, exec_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0x4e,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, m0, v2 :: v_dual_mul_dx9_zero_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x4e,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, vcc_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0x4e,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, vcc_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0x4e,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0xaf123456, v2 :: v_dual_mul_dx9_zero_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x4e,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, src_scc, v2 :: v_dual_mul_dx9_zero_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x4e,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_mul_dx9_zero_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x4e,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, -1, v4 :: v_dual_mul_dx9_zero_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x4e,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v6, null, v5 :: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x4e,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v4, v2 :: v_dual_mul_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x46,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v1, v2 :: v_dual_mul_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x46,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v255, v2 :: v_dual_mul_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x46,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v2, v2 :: v_dual_mul_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x46,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v3, v2 :: v_dual_mul_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x46,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, s105, v2 :: v_dual_mul_f32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x46,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, s1, v2 :: v_dual_mul_f32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x46,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, ttmp15, v2 :: v_dual_mul_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0x46,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, exec_hi, v2 :: v_dual_mul_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x46,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, exec_lo, v2 :: v_dual_mul_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0x46,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, m0, v2 :: v_dual_mul_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x46,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, vcc_hi, v2 :: v_dual_mul_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0x46,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, vcc_lo, v2 :: v_dual_mul_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0x46,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0xaf123456, v2 :: v_dual_mul_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x46,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, src_scc, v2 :: v_dual_mul_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x46,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_mul_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x46,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, -1, v4 :: v_dual_mul_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x46,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v6, null, v5 :: v_dual_mul_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x46,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v4, v2 :: v_dual_sub_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x4a,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v1, v2 :: v_dual_sub_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x4a,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v255, v2 :: v_dual_sub_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x4a,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v2, v2 :: v_dual_sub_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x4a,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v3, v2 :: v_dual_sub_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x4a,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, s105, v2 :: v_dual_sub_f32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x4a,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, s1, v2 :: v_dual_sub_f32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x4a,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, ttmp15, v2 :: v_dual_sub_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0x4a,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, exec_hi, v2 :: v_dual_sub_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x4a,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, exec_lo, v2 :: v_dual_sub_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0x4a,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, m0, v2 :: v_dual_sub_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x4a,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, vcc_hi, v2 :: v_dual_sub_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0x4a,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, vcc_lo, v2 :: v_dual_sub_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0x4a,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0xaf123456, v2 :: v_dual_sub_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x4a,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, src_scc, v2 :: v_dual_sub_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x4a,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_sub_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x4a,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, -1, v4 :: v_dual_sub_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x4a,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v6, null, v5 :: v_dual_sub_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x4a,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v4, v2 :: v_dual_subrev_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x4c,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v1, v2 :: v_dual_subrev_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x4c,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v255, v2 :: v_dual_subrev_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x4c,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v2, v2 :: v_dual_subrev_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x4c,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, v3, v2 :: v_dual_subrev_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x4c,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, s105, v2 :: v_dual_subrev_f32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x4c,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, s1, v2 :: v_dual_subrev_f32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x4c,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, ttmp15, v2 :: v_dual_subrev_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0x4c,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, exec_hi, v2 :: v_dual_subrev_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x4c,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, exec_lo, v2 :: v_dual_subrev_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0x4c,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, m0, v2 :: v_dual_subrev_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x4c,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, vcc_hi, v2 :: v_dual_subrev_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0x4c,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, vcc_lo, v2 :: v_dual_subrev_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0x4c,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0xaf123456, v2 :: v_dual_subrev_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x4c,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, src_scc, v2 :: v_dual_subrev_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x4c,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_subrev_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x4c,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v255, -1, v4 :: v_dual_subrev_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x4c,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_cndmask_b32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x4c,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v4, v2, 0xaf123456 :: v_dual_add_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x48,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v1, v2, 0xaf123456 :: v_dual_add_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x48,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v255, v2, 0xaf123456 :: v_dual_add_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x48,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v2, v2, 0xaf123456 :: v_dual_add_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x48,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v3, v2, 0xaf123456 :: v_dual_add_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x48,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, s105, v2, 0xaf123456 :: v_dual_add_f32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x48,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, s1, v2, 0xaf123456 :: v_dual_add_f32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x48,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, ttmp15, v2, 0xaf123456 :: v_dual_add_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0x48,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, exec_hi, v2, 0xaf123456 :: v_dual_add_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x48,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, exec_lo, v2, 0xaf123456 :: v_dual_add_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0x48,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, m0, v2, 0xaf123456 :: v_dual_add_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x48,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, vcc_hi, v2, 0xaf123456 :: v_dual_add_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0x48,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, vcc_lo, v2, 0xaf123456 :: v_dual_add_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0x48,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0xaf123456, v2, 0xaf123456 :: v_dual_add_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x48,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, src_scc, v2, 0xaf123456 :: v_dual_add_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x48,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_add_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x48,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_add_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x48,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_add_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x48,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v4, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x60,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v1, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x60,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v255, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x60,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v2, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x60,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v3, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x60,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, s105, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x60,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, s1, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x60,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, ttmp15, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0x60,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, exec_hi, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x60,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, exec_lo, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0x60,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, m0, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x60,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, vcc_hi, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0x60,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, vcc_lo, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0x60,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0xaf123456, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x60,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, src_scc, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x60,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_add_nc_u32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x60,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_add_nc_u32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x60,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_add_nc_u32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x60,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v4, v2, 0xaf123456 :: v_dual_and_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x64,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v1, v2, 0xaf123456 :: v_dual_and_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x64,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v255, v2, 0xaf123456 :: v_dual_and_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x64,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v2, v2, 0xaf123456 :: v_dual_and_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x64,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v3, v2, 0xaf123456 :: v_dual_and_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x64,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, s105, v2, 0xaf123456 :: v_dual_and_b32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x64,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, s1, v2, 0xaf123456 :: v_dual_and_b32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x64,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, ttmp15, v2, 0xaf123456 :: v_dual_and_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0x64,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, exec_hi, v2, 0xaf123456 :: v_dual_and_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x64,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, exec_lo, v2, 0xaf123456 :: v_dual_and_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0x64,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, m0, v2, 0xaf123456 :: v_dual_and_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x64,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, vcc_hi, v2, 0xaf123456 :: v_dual_and_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0x64,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, vcc_lo, v2, 0xaf123456 :: v_dual_and_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0x64,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0xaf123456, v2, 0xaf123456 :: v_dual_and_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x64,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, src_scc, v2, 0xaf123456 :: v_dual_and_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x64,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_and_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x64,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_and_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x64,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_and_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x64,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v4, v2, 0xaf123456 :: v_dual_cndmask_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x52,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v1, v2, 0xaf123456 :: v_dual_cndmask_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x52,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v255, v2, 0xaf123456 :: v_dual_cndmask_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x52,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v2, v2, 0xaf123456 :: v_dual_cndmask_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x52,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v3, v2, 0xaf123456 :: v_dual_cndmask_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x52,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0xaf123456, v2, 0xaf123456 :: v_dual_cndmask_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x52,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_cndmask_b32 v6, -1, v2
+// GFX12: encoding: [0xf0,0x06,0x52,0xc8,0xc1,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_cndmask_b32 v6, 0.5, v5
+// GFX12: encoding: [0xc1,0x08,0x52,0xc8,0xf0,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_cndmask_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x52,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v4, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, v1, v3, 0xaf123456
+// GFX12: encoding: [0x04,0x05,0x42,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v1, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, v255, v3, 0xaf123456
+// GFX12: encoding: [0x01,0x05,0x42,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v255, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, v2, v3, 0xaf123456
+// GFX12: encoding: [0xff,0x05,0x42,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v2, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, v3, v3, 0xaf123456
+// GFX12: encoding: [0x02,0x05,0x42,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v3, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, v4, v3, 0xaf123456
+// GFX12: encoding: [0x03,0x05,0x42,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, s105, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, s105, v3, 0xaf123456
+// GFX12: encoding: [0x69,0x04,0x42,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, s1, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, s1, v3, 0xaf123456
+// GFX12: encoding: [0x01,0x04,0x42,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, ttmp15, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, ttmp15, v3, 0xaf123456
+// GFX12: encoding: [0x7b,0x04,0x42,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, exec_hi, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, exec_hi, v3, 0xaf123456
+// GFX12: encoding: [0x7f,0x04,0x42,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, exec_lo, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, exec_lo, v3, 0xaf123456
+// GFX12: encoding: [0x7e,0x04,0x42,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, m0, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, m0, v3, 0xaf123456
+// GFX12: encoding: [0x7d,0x04,0x42,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, vcc_hi, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, vcc_hi, v3, 0xaf123456
+// GFX12: encoding: [0x6b,0x04,0x42,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, vcc_lo, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, vcc_lo, v3, 0xaf123456
+// GFX12: encoding: [0x6a,0x04,0x42,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0xaf123456, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, null, v3, 0xaf123456
+// GFX12: encoding: [0xff,0x04,0x42,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, src_scc, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, -1, v3, 0xaf123456
+// GFX12: encoding: [0xfd,0x04,0x42,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_fmaak_f32 v6, 0.5, v2, 0xaf123456
+// GFX12: encoding: [0xf0,0x06,0x42,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_fmaak_f32 v6, src_scc, v5, 0xaf123456
+// GFX12: encoding: [0xc1,0x08,0x42,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_fmaak_f32 v255, 0xaf123456, v4, 0xaf123456
+// GFX12: encoding: [0x7c,0x0a,0x42,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v4, v2, 0xaf123456 :: v_dual_fmac_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x40,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v1, v2, 0xaf123456 :: v_dual_fmac_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x40,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v255, v2, 0xaf123456 :: v_dual_fmac_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x40,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v2, v2, 0xaf123456 :: v_dual_fmac_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x40,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v3, v2, 0xaf123456 :: v_dual_fmac_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x40,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, s105, v2, 0xaf123456 :: v_dual_fmac_f32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x40,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, s1, v2, 0xaf123456 :: v_dual_fmac_f32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x40,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, ttmp15, v2, 0xaf123456 :: v_dual_fmac_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0x40,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, exec_hi, v2, 0xaf123456 :: v_dual_fmac_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x40,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, exec_lo, v2, 0xaf123456 :: v_dual_fmac_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0x40,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, m0, v2, 0xaf123456 :: v_dual_fmac_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x40,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, vcc_hi, v2, 0xaf123456 :: v_dual_fmac_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0x40,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, vcc_lo, v2, 0xaf123456 :: v_dual_fmac_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0x40,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0xaf123456, v2, 0xaf123456 :: v_dual_fmac_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x40,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, src_scc, v2, 0xaf123456 :: v_dual_fmac_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x40,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_fmac_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x40,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_fmac_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x40,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_fmac_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x40,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v4, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, v1, 0xaf123456, v255
+// GFX12: encoding: [0x04,0xff,0x45,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v1, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, v255, 0xaf123456, v255
+// GFX12: encoding: [0x01,0xff,0x45,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v255, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, v2, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xff,0x45,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v2, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, v3, 0xaf123456, v255
+// GFX12: encoding: [0x02,0xff,0x45,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v3, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, v4, 0xaf123456, v255
+// GFX12: encoding: [0x03,0xff,0x45,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, s105, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, s105, 0xaf123456, v255
+// GFX12: encoding: [0x69,0xfe,0x45,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, s1, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, s1, 0xaf123456, v255
+// GFX12: encoding: [0x01,0xfe,0x45,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, ttmp15, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, ttmp15, 0xaf123456, v255
+// GFX12: encoding: [0x7b,0xfe,0x45,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, exec_hi, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, exec_hi, 0xaf123456, v255
+// GFX12: encoding: [0x7f,0xfe,0x45,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, exec_lo, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, exec_lo, 0xaf123456, v255
+// GFX12: encoding: [0x7e,0xfe,0x45,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, m0, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, m0, 0xaf123456, v255
+// GFX12: encoding: [0x7d,0xfe,0x45,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, vcc_hi, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x6b,0xfe,0x45,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, vcc_lo, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, vcc_lo, 0xaf123456, v255
+// GFX12: encoding: [0x6a,0xfe,0x45,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0xaf123456, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, null, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x45,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, src_scc, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, -1, 0xaf123456, v255
+// GFX12: encoding: [0xfd,0xfe,0x45,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_fmamk_f32 v6, 0.5, 0xaf123456, v255
+// GFX12: encoding: [0xf0,0x06,0x44,0xc8,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_fmamk_f32 v6, src_scc, 0xaf123456, v255
+// GFX12: encoding: [0xc1,0x08,0x44,0xc8,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x44,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v4, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x62,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v1, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x62,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v255, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x62,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v2, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x62,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v3, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x62,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, s105, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x62,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, s1, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x62,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, ttmp15, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0x62,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, exec_hi, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x62,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, exec_lo, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0x62,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, m0, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x62,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, vcc_hi, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0x62,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, vcc_lo, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0x62,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0xaf123456, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x62,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, src_scc, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x62,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_lshlrev_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x62,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_lshlrev_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x62,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_lshlrev_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x62,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v4, v2, 0xaf123456 :: v_dual_max_num_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x54,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v1, v2, 0xaf123456 :: v_dual_max_num_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x54,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v255, v2, 0xaf123456 :: v_dual_max_num_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x54,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v2, v2, 0xaf123456 :: v_dual_max_num_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x54,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v3, v2, 0xaf123456 :: v_dual_max_num_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x54,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, s105, v2, 0xaf123456 :: v_dual_max_num_f32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x54,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, s1, v2, 0xaf123456 :: v_dual_max_num_f32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x54,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, ttmp15, v2, 0xaf123456 :: v_dual_max_num_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0x54,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, exec_hi, v2, 0xaf123456 :: v_dual_max_num_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x54,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, exec_lo, v2, 0xaf123456 :: v_dual_max_num_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0x54,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, m0, v2, 0xaf123456 :: v_dual_max_num_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x54,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, vcc_hi, v2, 0xaf123456 :: v_dual_max_num_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0x54,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, vcc_lo, v2, 0xaf123456 :: v_dual_max_num_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0x54,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0xaf123456, v2, 0xaf123456 :: v_dual_max_num_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x54,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, src_scc, v2, 0xaf123456 :: v_dual_max_num_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x54,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_max_num_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x54,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_max_num_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x54,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_max_num_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x54,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v4, v2, 0xaf123456 :: v_dual_min_num_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x56,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v1, v2, 0xaf123456 :: v_dual_min_num_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x56,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v255, v2, 0xaf123456 :: v_dual_min_num_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x56,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v2, v2, 0xaf123456 :: v_dual_min_num_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x56,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v3, v2, 0xaf123456 :: v_dual_min_num_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x56,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, s105, v2, 0xaf123456 :: v_dual_min_num_f32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x56,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, s1, v2, 0xaf123456 :: v_dual_min_num_f32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x56,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, ttmp15, v2, 0xaf123456 :: v_dual_min_num_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0x56,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, exec_hi, v2, 0xaf123456 :: v_dual_min_num_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x56,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, exec_lo, v2, 0xaf123456 :: v_dual_min_num_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0x56,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, m0, v2, 0xaf123456 :: v_dual_min_num_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x56,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, vcc_hi, v2, 0xaf123456 :: v_dual_min_num_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0x56,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, vcc_lo, v2, 0xaf123456 :: v_dual_min_num_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0x56,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0xaf123456, v2, 0xaf123456 :: v_dual_min_num_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x56,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, src_scc, v2, 0xaf123456 :: v_dual_min_num_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x56,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_min_num_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x56,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_min_num_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x56,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_min_num_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x56,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v4, v255, 0xaf123456 :: v_dual_mov_b32 v6, v1
+// GFX12: encoding: [0x04,0xff,0x51,0xc8,0x01,0x01,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v1, v255, 0xaf123456 :: v_dual_mov_b32 v6, v255
+// GFX12: encoding: [0x01,0xff,0x51,0xc8,0xff,0x01,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v255, v255, 0xaf123456 :: v_dual_mov_b32 v6, v2
+// GFX12: encoding: [0xff,0xff,0x51,0xc8,0x02,0x01,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v2, v255, 0xaf123456 :: v_dual_mov_b32 v6, v3
+// GFX12: encoding: [0x02,0xff,0x51,0xc8,0x03,0x01,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v3, v255, 0xaf123456 :: v_dual_mov_b32 v6, v4
+// GFX12: encoding: [0x03,0xff,0x51,0xc8,0x04,0x01,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, s105, v255, 0xaf123456 :: v_dual_mov_b32 v6, s105
+// GFX12: encoding: [0x69,0xfe,0x51,0xc8,0x69,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, s1, v255, 0xaf123456 :: v_dual_mov_b32 v6, s1
+// GFX12: encoding: [0x01,0xfe,0x51,0xc8,0x01,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, ttmp15, v255, 0xaf123456 :: v_dual_mov_b32 v6, ttmp15
+// GFX12: encoding: [0x7b,0xfe,0x51,0xc8,0x7b,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, exec_hi, v255, 0xaf123456 :: v_dual_mov_b32 v6, exec_hi
+// GFX12: encoding: [0x7f,0xfe,0x51,0xc8,0x7f,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, exec_lo, v255, 0xaf123456 :: v_dual_mov_b32 v6, exec_lo
+// GFX12: encoding: [0x7e,0xfe,0x51,0xc8,0x7e,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, m0, v255, 0xaf123456 :: v_dual_mov_b32 v6, m0
+// GFX12: encoding: [0x7d,0xfe,0x51,0xc8,0x7d,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, vcc_hi, v255, 0xaf123456 :: v_dual_mov_b32 v6, vcc_hi
+// GFX12: encoding: [0x6b,0xfe,0x51,0xc8,0x6b,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, vcc_lo, v255, 0xaf123456 :: v_dual_mov_b32 v6, vcc_lo
+// GFX12: encoding: [0x6a,0xfe,0x51,0xc8,0x6a,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0xaf123456, v255, 0xaf123456 :: v_dual_mov_b32 v6, null
+// GFX12: encoding: [0xff,0xfe,0x51,0xc8,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, src_scc, v255, 0xaf123456 :: v_dual_mov_b32 v6, -1
+// GFX12: encoding: [0xfd,0xfe,0x51,0xc8,0xc1,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_mov_b32 v6, 0.5
+// GFX12: encoding: [0xf0,0x06,0x50,0xc8,0xf0,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_mov_b32 v6, src_scc
+// GFX12: encoding: [0xc1,0x08,0x50,0xc8,0xfd,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_mov_b32 v255, 0xaf123456
+// GFX12: encoding: [0x7c,0x0a,0x50,0xc8,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v4, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x4e,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v1, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x4e,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v255, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x4e,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v2, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x4e,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v3, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x4e,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, s105, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x4e,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, s1, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x4e,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, ttmp15, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0x4e,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, exec_hi, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x4e,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, exec_lo, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0x4e,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, m0, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x4e,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, vcc_hi, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0x4e,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, vcc_lo, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0x4e,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0xaf123456, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x4e,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, src_scc, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x4e,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x4e,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x4e,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x4e,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v4, v2, 0xaf123456 :: v_dual_mul_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x46,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v1, v2, 0xaf123456 :: v_dual_mul_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x46,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v255, v2, 0xaf123456 :: v_dual_mul_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x46,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v2, v2, 0xaf123456 :: v_dual_mul_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x46,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v3, v2, 0xaf123456 :: v_dual_mul_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x46,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, s105, v2, 0xaf123456 :: v_dual_mul_f32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x46,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, s1, v2, 0xaf123456 :: v_dual_mul_f32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x46,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, ttmp15, v2, 0xaf123456 :: v_dual_mul_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0x46,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, exec_hi, v2, 0xaf123456 :: v_dual_mul_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x46,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, exec_lo, v2, 0xaf123456 :: v_dual_mul_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0x46,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, m0, v2, 0xaf123456 :: v_dual_mul_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x46,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, vcc_hi, v2, 0xaf123456 :: v_dual_mul_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0x46,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, vcc_lo, v2, 0xaf123456 :: v_dual_mul_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0x46,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0xaf123456, v2, 0xaf123456 :: v_dual_mul_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x46,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, src_scc, v2, 0xaf123456 :: v_dual_mul_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x46,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_mul_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x46,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_mul_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x46,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_mul_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x46,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v4, v2, 0xaf123456 :: v_dual_sub_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x4a,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v1, v2, 0xaf123456 :: v_dual_sub_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x4a,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v255, v2, 0xaf123456 :: v_dual_sub_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x4a,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v2, v2, 0xaf123456 :: v_dual_sub_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x4a,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v3, v2, 0xaf123456 :: v_dual_sub_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x4a,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, s105, v2, 0xaf123456 :: v_dual_sub_f32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x4a,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, s1, v2, 0xaf123456 :: v_dual_sub_f32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x4a,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, ttmp15, v2, 0xaf123456 :: v_dual_sub_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0x4a,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, exec_hi, v2, 0xaf123456 :: v_dual_sub_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x4a,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, exec_lo, v2, 0xaf123456 :: v_dual_sub_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0x4a,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, m0, v2, 0xaf123456 :: v_dual_sub_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x4a,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, vcc_hi, v2, 0xaf123456 :: v_dual_sub_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0x4a,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, vcc_lo, v2, 0xaf123456 :: v_dual_sub_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0x4a,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0xaf123456, v2, 0xaf123456 :: v_dual_sub_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x4a,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, src_scc, v2, 0xaf123456 :: v_dual_sub_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x4a,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_sub_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x4a,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_sub_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x4a,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_sub_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x4a,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v4, v2, 0xaf123456 :: v_dual_subrev_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x4c,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v1, v2, 0xaf123456 :: v_dual_subrev_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x4c,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v255, v2, 0xaf123456 :: v_dual_subrev_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x4c,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v2, v2, 0xaf123456 :: v_dual_subrev_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x4c,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, v3, v2, 0xaf123456 :: v_dual_subrev_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x4c,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, s105, v2, 0xaf123456 :: v_dual_subrev_f32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x4c,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, s1, v2, 0xaf123456 :: v_dual_subrev_f32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x4c,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, ttmp15, v2, 0xaf123456 :: v_dual_subrev_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0x4c,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, exec_hi, v2, 0xaf123456 :: v_dual_subrev_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x4c,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, exec_lo, v2, 0xaf123456 :: v_dual_subrev_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0x4c,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, m0, v2, 0xaf123456 :: v_dual_subrev_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x4c,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, vcc_hi, v2, 0xaf123456 :: v_dual_subrev_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0x4c,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, vcc_lo, v2, 0xaf123456 :: v_dual_subrev_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0x4c,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0xaf123456, v2, 0xaf123456 :: v_dual_subrev_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x4c,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, src_scc, v2, 0xaf123456 :: v_dual_subrev_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x4c,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_subrev_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x4c,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_subrev_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x4c,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_subrev_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x4c,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v4, v2 :: v_dual_add_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x08,0xc8,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v1, v2 :: v_dual_add_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x08,0xc8,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v255, v2 :: v_dual_add_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x08,0xc8,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v2, v2 :: v_dual_add_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x08,0xc8,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v3, v2 :: v_dual_add_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x08,0xc8,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s105, v2 :: v_dual_add_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x08,0xc8,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s1, v2 :: v_dual_add_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x08,0xc8,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, ttmp15, v2 :: v_dual_add_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x08,0xc8,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_hi, v2 :: v_dual_add_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x08,0xc8,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_lo, v2 :: v_dual_add_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x08,0xc8,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, m0, v2 :: v_dual_add_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x08,0xc8,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_hi, v2 :: v_dual_add_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x08,0xc8,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_lo, v2 :: v_dual_add_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x08,0xc8,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0xaf123456, v2 :: v_dual_add_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x08,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, src_scc, v2 :: v_dual_add_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x08,0xc8,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_add_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x08,0xc8,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, -1, v4 :: v_dual_add_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x08,0xc8,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v6, null, v5 :: v_dual_add_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x08,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v4, v2 :: v_dual_add_nc_u32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x20,0xc8,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v1, v2 :: v_dual_add_nc_u32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x20,0xc8,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v255, v2 :: v_dual_add_nc_u32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x20,0xc8,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v2, v2 :: v_dual_add_nc_u32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x20,0xc8,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v3, v2 :: v_dual_add_nc_u32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x20,0xc8,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s105, v2 :: v_dual_add_nc_u32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x20,0xc8,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s1, v2 :: v_dual_add_nc_u32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x20,0xc8,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, ttmp15, v2 :: v_dual_add_nc_u32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x20,0xc8,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_hi, v2 :: v_dual_add_nc_u32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x20,0xc8,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_lo, v2 :: v_dual_add_nc_u32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x20,0xc8,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, m0, v2 :: v_dual_add_nc_u32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x20,0xc8,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_hi, v2 :: v_dual_add_nc_u32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x20,0xc8,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_lo, v2 :: v_dual_add_nc_u32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x20,0xc8,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0xaf123456, v2 :: v_dual_add_nc_u32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x20,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, src_scc, v2 :: v_dual_add_nc_u32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x20,0xc8,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_add_nc_u32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x20,0xc8,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, -1, v4 :: v_dual_add_nc_u32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x20,0xc8,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v6, null, v5 :: v_dual_add_nc_u32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x20,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v4, v2 :: v_dual_and_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x24,0xc8,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v1, v2 :: v_dual_and_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x24,0xc8,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v255, v2 :: v_dual_and_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x24,0xc8,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v2, v2 :: v_dual_and_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x24,0xc8,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v3, v2 :: v_dual_and_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x24,0xc8,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s105, v2 :: v_dual_and_b32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x24,0xc8,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s1, v2 :: v_dual_and_b32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x24,0xc8,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, ttmp15, v2 :: v_dual_and_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x24,0xc8,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_hi, v2 :: v_dual_and_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x24,0xc8,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_lo, v2 :: v_dual_and_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x24,0xc8,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, m0, v2 :: v_dual_and_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x24,0xc8,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_hi, v2 :: v_dual_and_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x24,0xc8,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_lo, v2 :: v_dual_and_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x24,0xc8,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0xaf123456, v2 :: v_dual_and_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x24,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, src_scc, v2 :: v_dual_and_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x24,0xc8,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_and_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x24,0xc8,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, -1, v4 :: v_dual_and_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x24,0xc8,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v6, null, v5 :: v_dual_and_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x24,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v4, v2 :: v_dual_cndmask_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x12,0xc8,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v1, v2 :: v_dual_cndmask_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x12,0xc8,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v255, v2 :: v_dual_cndmask_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x12,0xc8,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v2, v2 :: v_dual_cndmask_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x12,0xc8,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v3, v2 :: v_dual_cndmask_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x12,0xc8,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s105, v2 :: v_dual_cndmask_b32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x12,0xc8,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s1, v2 :: v_dual_cndmask_b32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x12,0xc8,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, ttmp15, v2 :: v_dual_cndmask_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0x12,0xc8,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_hi, v2 :: v_dual_cndmask_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x12,0xc8,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_lo, v2 :: v_dual_cndmask_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0x12,0xc8,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, m0, v2 :: v_dual_cndmask_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x12,0xc8,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_hi, v2 :: v_dual_cndmask_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0x12,0xc8,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_lo, v2 :: v_dual_cndmask_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0x12,0xc8,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0xaf123456, v2 :: v_dual_cndmask_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x12,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, src_scc, v2 :: v_dual_cndmask_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x12,0xc8,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_cndmask_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x12,0xc8,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, -1, v4 :: v_dual_cndmask_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x12,0xc8,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v6, null, v5 :: v_dual_cndmask_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x12,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v4, v2 :: v_dual_fmaak_f32 v6, v1, v3, 0xaf123456
+// GFX12: encoding: [0x04,0x05,0x02,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v1, v2 :: v_dual_fmaak_f32 v6, v255, v3, 0xaf123456
+// GFX12: encoding: [0x01,0x05,0x02,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v255, v2 :: v_dual_fmaak_f32 v6, v2, v3, 0xaf123456
+// GFX12: encoding: [0xff,0x05,0x02,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v2, v2 :: v_dual_fmaak_f32 v6, v3, v3, 0xaf123456
+// GFX12: encoding: [0x02,0x05,0x02,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v3, v2 :: v_dual_fmaak_f32 v6, v4, v3, 0xaf123456
+// GFX12: encoding: [0x03,0x05,0x02,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s105, v2 :: v_dual_fmaak_f32 v6, s105, v3, 0xaf123456
+// GFX12: encoding: [0x69,0x04,0x02,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s1, v2 :: v_dual_fmaak_f32 v6, s1, v3, 0xaf123456
+// GFX12: encoding: [0x01,0x04,0x02,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, ttmp15, v2 :: v_dual_fmaak_f32 v6, ttmp15, v3, 0xaf123456
+// GFX12: encoding: [0x7b,0x04,0x02,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_hi, v2 :: v_dual_fmaak_f32 v6, exec_hi, v3, 0xaf123456
+// GFX12: encoding: [0x7f,0x04,0x02,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_lo, v2 :: v_dual_fmaak_f32 v6, exec_lo, v3, 0xaf123456
+// GFX12: encoding: [0x7e,0x04,0x02,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, m0, v2 :: v_dual_fmaak_f32 v6, m0, v3, 0xaf123456
+// GFX12: encoding: [0x7d,0x04,0x02,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_hi, v2 :: v_dual_fmaak_f32 v6, vcc_hi, v3, 0xaf123456
+// GFX12: encoding: [0x6b,0x04,0x02,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_lo, v2 :: v_dual_fmaak_f32 v6, vcc_lo, v3, 0xaf123456
+// GFX12: encoding: [0x6a,0x04,0x02,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, null, v3, 0xaf123456
+// GFX12: encoding: [0xff,0x04,0x02,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, src_scc, v2 :: v_dual_fmaak_f32 v6, -1, v3, 0xaf123456
+// GFX12: encoding: [0xfd,0x04,0x02,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_fmaak_f32 v6, 0.5, v2, 0xaf123456
+// GFX12: encoding: [0xf0,0x06,0x02,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, -1, v4 :: v_dual_fmaak_f32 v6, src_scc, v5, 0xaf123456
+// GFX12: encoding: [0xc1,0x08,0x02,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v6, null, v5 :: v_dual_fmaak_f32 v255, 0xaf123456, v4, 0xaf123456
+// GFX12: encoding: [0x7c,0x0a,0x02,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v4, v2 :: v_dual_fmac_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x00,0xc8,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v1, v2 :: v_dual_fmac_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x00,0xc8,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v255, v2 :: v_dual_fmac_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x00,0xc8,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v2, v2 :: v_dual_fmac_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x00,0xc8,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v3, v2 :: v_dual_fmac_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x00,0xc8,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s105, v2 :: v_dual_fmac_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x00,0xc8,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s1, v2 :: v_dual_fmac_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x00,0xc8,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, ttmp15, v2 :: v_dual_fmac_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x00,0xc8,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_hi, v2 :: v_dual_fmac_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x00,0xc8,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_lo, v2 :: v_dual_fmac_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x00,0xc8,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, m0, v2 :: v_dual_fmac_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x00,0xc8,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_hi, v2 :: v_dual_fmac_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x00,0xc8,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_lo, v2 :: v_dual_fmac_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x00,0xc8,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0xaf123456, v2 :: v_dual_fmac_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x00,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, src_scc, v2 :: v_dual_fmac_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x00,0xc8,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_fmac_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x00,0xc8,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, -1, v4 :: v_dual_fmac_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x00,0xc8,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v6, null, v5 :: v_dual_fmac_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x00,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v4, v255 :: v_dual_fmamk_f32 v6, v1, 0xaf123456, v4
+// GFX12: encoding: [0x04,0xff,0x05,0xc8,0x01,0x09,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v1, v255 :: v_dual_fmamk_f32 v6, v255, 0xaf123456, v4
+// GFX12: encoding: [0x01,0xff,0x05,0xc8,0xff,0x09,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v255, v255 :: v_dual_fmamk_f32 v6, v2, 0xaf123456, v4
+// GFX12: encoding: [0xff,0xff,0x05,0xc8,0x02,0x09,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v2, v255 :: v_dual_fmamk_f32 v6, v3, 0xaf123456, v4
+// GFX12: encoding: [0x02,0xff,0x05,0xc8,0x03,0x09,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v3, v255 :: v_dual_fmamk_f32 v6, v4, 0xaf123456, v4
+// GFX12: encoding: [0x03,0xff,0x05,0xc8,0x04,0x09,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s105, v255 :: v_dual_fmamk_f32 v6, s105, 0xaf123456, v4
+// GFX12: encoding: [0x69,0xfe,0x05,0xc8,0x69,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s1, v255 :: v_dual_fmamk_f32 v6, s1, 0xaf123456, v4
+// GFX12: encoding: [0x01,0xfe,0x05,0xc8,0x01,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, ttmp15, v255 :: v_dual_fmamk_f32 v6, ttmp15, 0xaf123456, v4
+// GFX12: encoding: [0x7b,0xfe,0x05,0xc8,0x7b,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_hi, v255 :: v_dual_fmamk_f32 v6, exec_hi, 0xaf123456, v4
+// GFX12: encoding: [0x7f,0xfe,0x05,0xc8,0x7f,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_lo, v255 :: v_dual_fmamk_f32 v6, exec_lo, 0xaf123456, v4
+// GFX12: encoding: [0x7e,0xfe,0x05,0xc8,0x7e,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, m0, v255 :: v_dual_fmamk_f32 v6, m0, 0xaf123456, v4
+// GFX12: encoding: [0x7d,0xfe,0x05,0xc8,0x7d,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_hi, v255 :: v_dual_fmamk_f32 v6, vcc_hi, 0xaf123456, v4
+// GFX12: encoding: [0x6b,0xfe,0x05,0xc8,0x6b,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_lo, v255 :: v_dual_fmamk_f32 v6, vcc_lo, 0xaf123456, v4
+// GFX12: encoding: [0x6a,0xfe,0x05,0xc8,0x6a,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, null, 0xaf123456, v4
+// GFX12: encoding: [0xff,0xfe,0x05,0xc8,0x7c,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, src_scc, v255 :: v_dual_fmamk_f32 v6, -1, 0xaf123456, v4
+// GFX12: encoding: [0xfd,0xfe,0x05,0xc8,0xc1,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_fmamk_f32 v6, 0.5, 0xaf123456, v4
+// GFX12: encoding: [0xf0,0x06,0x04,0xc8,0xf0,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, -1, v4 :: v_dual_fmamk_f32 v6, src_scc, 0xaf123456, v4
+// GFX12: encoding: [0xc1,0x08,0x04,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v6, null, v5 :: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255
+// GFX12: encoding: [0x7c,0x0a,0x04,0xc8,0xff,0xfe,0xff,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v4, v2 :: v_dual_lshlrev_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x22,0xc8,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v1, v2 :: v_dual_lshlrev_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x22,0xc8,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v255, v2 :: v_dual_lshlrev_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x22,0xc8,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v2, v2 :: v_dual_lshlrev_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x22,0xc8,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v3, v2 :: v_dual_lshlrev_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x22,0xc8,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s105, v2 :: v_dual_lshlrev_b32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x22,0xc8,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s1, v2 :: v_dual_lshlrev_b32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x22,0xc8,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, ttmp15, v2 :: v_dual_lshlrev_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x22,0xc8,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_hi, v2 :: v_dual_lshlrev_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x22,0xc8,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_lo, v2 :: v_dual_lshlrev_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x22,0xc8,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, m0, v2 :: v_dual_lshlrev_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x22,0xc8,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_hi, v2 :: v_dual_lshlrev_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x22,0xc8,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_lo, v2 :: v_dual_lshlrev_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x22,0xc8,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0xaf123456, v2 :: v_dual_lshlrev_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x22,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, src_scc, v2 :: v_dual_lshlrev_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x22,0xc8,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_lshlrev_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x22,0xc8,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, -1, v4 :: v_dual_lshlrev_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x22,0xc8,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v6, null, v5 :: v_dual_lshlrev_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x22,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v4, v2 :: v_dual_max_num_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x14,0xc8,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v1, v2 :: v_dual_max_num_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x14,0xc8,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v255, v2 :: v_dual_max_num_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x14,0xc8,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v2, v2 :: v_dual_max_num_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x14,0xc8,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v3, v2 :: v_dual_max_num_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x14,0xc8,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s105, v2 :: v_dual_max_num_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x14,0xc8,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s1, v2 :: v_dual_max_num_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x14,0xc8,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, ttmp15, v2 :: v_dual_max_num_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x14,0xc8,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_hi, v2 :: v_dual_max_num_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x14,0xc8,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_lo, v2 :: v_dual_max_num_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x14,0xc8,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, m0, v2 :: v_dual_max_num_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x14,0xc8,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_hi, v2 :: v_dual_max_num_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x14,0xc8,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_lo, v2 :: v_dual_max_num_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x14,0xc8,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0xaf123456, v2 :: v_dual_max_num_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x14,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, src_scc, v2 :: v_dual_max_num_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x14,0xc8,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_max_num_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x14,0xc8,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, -1, v4 :: v_dual_max_num_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x14,0xc8,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v6, null, v5 :: v_dual_max_num_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x14,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v4, v2 :: v_dual_min_num_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x16,0xc8,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v1, v2 :: v_dual_min_num_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x16,0xc8,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v255, v2 :: v_dual_min_num_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x16,0xc8,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v2, v2 :: v_dual_min_num_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x16,0xc8,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v3, v2 :: v_dual_min_num_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x16,0xc8,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s105, v2 :: v_dual_min_num_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x16,0xc8,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s1, v2 :: v_dual_min_num_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x16,0xc8,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, ttmp15, v2 :: v_dual_min_num_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x16,0xc8,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_hi, v2 :: v_dual_min_num_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x16,0xc8,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_lo, v2 :: v_dual_min_num_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x16,0xc8,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, m0, v2 :: v_dual_min_num_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x16,0xc8,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_hi, v2 :: v_dual_min_num_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x16,0xc8,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_lo, v2 :: v_dual_min_num_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x16,0xc8,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0xaf123456, v2 :: v_dual_min_num_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x16,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, src_scc, v2 :: v_dual_min_num_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x16,0xc8,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_min_num_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x16,0xc8,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, -1, v4 :: v_dual_min_num_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x16,0xc8,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v6, null, v5 :: v_dual_min_num_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x16,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v4, v255 :: v_dual_mov_b32 v6, v1
+// GFX12: encoding: [0x04,0xff,0x11,0xc8,0x01,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v1, v255 :: v_dual_mov_b32 v6, v255
+// GFX12: encoding: [0x01,0xff,0x11,0xc8,0xff,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v255, v255 :: v_dual_mov_b32 v6, v2
+// GFX12: encoding: [0xff,0xff,0x11,0xc8,0x02,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v2, v255 :: v_dual_mov_b32 v6, v3
+// GFX12: encoding: [0x02,0xff,0x11,0xc8,0x03,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v3, v255 :: v_dual_mov_b32 v6, v4
+// GFX12: encoding: [0x03,0xff,0x11,0xc8,0x04,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s105, v255 :: v_dual_mov_b32 v6, s1
+// GFX12: encoding: [0x69,0xfe,0x11,0xc8,0x01,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s1, v255 :: v_dual_mov_b32 v6, s105
+// GFX12: encoding: [0x01,0xfe,0x11,0xc8,0x69,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, ttmp15, v255 :: v_dual_mov_b32 v6, vcc_lo
+// GFX12: encoding: [0x7b,0xfe,0x11,0xc8,0x6a,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_hi, v255 :: v_dual_mov_b32 v6, vcc_hi
+// GFX12: encoding: [0x7f,0xfe,0x11,0xc8,0x6b,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_lo, v255 :: v_dual_mov_b32 v6, ttmp15
+// GFX12: encoding: [0x7e,0xfe,0x11,0xc8,0x7b,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, m0, v255 :: v_dual_mov_b32 v6, m0
+// GFX12: encoding: [0x7d,0xfe,0x11,0xc8,0x7d,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_hi, v255 :: v_dual_mov_b32 v6, exec_lo
+// GFX12: encoding: [0x6b,0xfe,0x11,0xc8,0x7e,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_lo, v255 :: v_dual_mov_b32 v6, exec_hi
+// GFX12: encoding: [0x6a,0xfe,0x11,0xc8,0x7f,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0xaf123456, v255 :: v_dual_mov_b32 v6, null
+// GFX12: encoding: [0xff,0xfe,0x11,0xc8,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, src_scc, v255 :: v_dual_mov_b32 v6, -1
+// GFX12: encoding: [0xfd,0xfe,0x11,0xc8,0xc1,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_mov_b32 v6, 0.5
+// GFX12: encoding: [0xf0,0x06,0x10,0xc8,0xf0,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, -1, v4 :: v_dual_mov_b32 v6, src_scc
+// GFX12: encoding: [0xc1,0x08,0x10,0xc8,0xfd,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v6, null, v5 :: v_dual_mov_b32 v255, 0xaf123456
+// GFX12: encoding: [0x7c,0x0a,0x10,0xc8,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v4, v2 :: v_dual_mul_dx9_zero_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x0e,0xc8,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v1, v2 :: v_dual_mul_dx9_zero_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x0e,0xc8,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v255, v2 :: v_dual_mul_dx9_zero_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x0e,0xc8,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v2, v2 :: v_dual_mul_dx9_zero_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x0e,0xc8,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v3, v2 :: v_dual_mul_dx9_zero_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x0e,0xc8,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s105, v2 :: v_dual_mul_dx9_zero_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x0e,0xc8,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s1, v2 :: v_dual_mul_dx9_zero_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x0e,0xc8,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, ttmp15, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x0e,0xc8,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x0e,0xc8,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x0e,0xc8,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, m0, v2 :: v_dual_mul_dx9_zero_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x0e,0xc8,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x0e,0xc8,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x0e,0xc8,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0xaf123456, v2 :: v_dual_mul_dx9_zero_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x0e,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, src_scc, v2 :: v_dual_mul_dx9_zero_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x0e,0xc8,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_mul_dx9_zero_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x0e,0xc8,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, -1, v4 :: v_dual_mul_dx9_zero_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x0e,0xc8,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v6, null, v5 :: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x0e,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v4, v2 :: v_dual_mul_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x06,0xc8,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v1, v2 :: v_dual_mul_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x06,0xc8,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v255, v2 :: v_dual_mul_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x06,0xc8,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v2, v2 :: v_dual_mul_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x06,0xc8,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v3, v2 :: v_dual_mul_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x06,0xc8,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s105, v2 :: v_dual_mul_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x06,0xc8,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s1, v2 :: v_dual_mul_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x06,0xc8,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, ttmp15, v2 :: v_dual_mul_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x06,0xc8,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_hi, v2 :: v_dual_mul_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x06,0xc8,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_lo, v2 :: v_dual_mul_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x06,0xc8,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, m0, v2 :: v_dual_mul_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x06,0xc8,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_hi, v2 :: v_dual_mul_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x06,0xc8,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_lo, v2 :: v_dual_mul_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x06,0xc8,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0xaf123456, v2 :: v_dual_mul_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x06,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, src_scc, v2 :: v_dual_mul_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x06,0xc8,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_mul_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x06,0xc8,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, -1, v4 :: v_dual_mul_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x06,0xc8,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v6, null, v5 :: v_dual_mul_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x06,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v4, v2 :: v_dual_sub_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x0a,0xc8,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v1, v2 :: v_dual_sub_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x0a,0xc8,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v255, v2 :: v_dual_sub_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x0a,0xc8,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v2, v2 :: v_dual_sub_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x0a,0xc8,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v3, v2 :: v_dual_sub_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x0a,0xc8,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s105, v2 :: v_dual_sub_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x0a,0xc8,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s1, v2 :: v_dual_sub_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x0a,0xc8,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, ttmp15, v2 :: v_dual_sub_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x0a,0xc8,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_hi, v2 :: v_dual_sub_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x0a,0xc8,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_lo, v2 :: v_dual_sub_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x0a,0xc8,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, m0, v2 :: v_dual_sub_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x0a,0xc8,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_hi, v2 :: v_dual_sub_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x0a,0xc8,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_lo, v2 :: v_dual_sub_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x0a,0xc8,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0xaf123456, v2 :: v_dual_sub_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x0a,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, src_scc, v2 :: v_dual_sub_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x0a,0xc8,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_sub_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x0a,0xc8,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, -1, v4 :: v_dual_sub_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x0a,0xc8,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v6, null, v5 :: v_dual_sub_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x0a,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v4, v2 :: v_dual_subrev_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x0c,0xc8,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v1, v2 :: v_dual_subrev_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x0c,0xc8,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v255, v2 :: v_dual_subrev_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x0c,0xc8,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v2, v2 :: v_dual_subrev_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x0c,0xc8,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, v3, v2 :: v_dual_subrev_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x0c,0xc8,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s105, v2 :: v_dual_subrev_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x0c,0xc8,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, s1, v2 :: v_dual_subrev_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x0c,0xc8,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, ttmp15, v2 :: v_dual_subrev_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x0c,0xc8,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_hi, v2 :: v_dual_subrev_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x0c,0xc8,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, exec_lo, v2 :: v_dual_subrev_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x0c,0xc8,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, m0, v2 :: v_dual_subrev_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x0c,0xc8,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_hi, v2 :: v_dual_subrev_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x0c,0xc8,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, vcc_lo, v2 :: v_dual_subrev_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x0c,0xc8,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0xaf123456, v2 :: v_dual_subrev_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x0c,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, src_scc, v2 :: v_dual_subrev_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x0c,0xc8,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_subrev_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x0c,0xc8,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v255, -1, v4 :: v_dual_subrev_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x0c,0xc8,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmac_f32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x0c,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_add_f32 v6, v1, v255
+// GFX12: encoding: [0x04,0xff,0x89,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_add_f32 v6, v255, v255
+// GFX12: encoding: [0x01,0xff,0x89,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_add_f32 v6, v2, v255
+// GFX12: encoding: [0xff,0xff,0x89,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_add_f32 v6, v3, v255
+// GFX12: encoding: [0x02,0xff,0x89,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_add_f32 v6, v4, v255
+// GFX12: encoding: [0x03,0xff,0x89,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, s105, 0xaf123456, v255 :: v_dual_add_f32 v6, s105, v255
+// GFX12: encoding: [0x69,0xfe,0x89,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, s1, 0xaf123456, v255 :: v_dual_add_f32 v6, s1, v255
+// GFX12: encoding: [0x01,0xfe,0x89,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, ttmp15, 0xaf123456, v255 :: v_dual_add_f32 v6, ttmp15, v255
+// GFX12: encoding: [0x7b,0xfe,0x89,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, exec_hi, 0xaf123456, v255 :: v_dual_add_f32 v6, exec_hi, v255
+// GFX12: encoding: [0x7f,0xfe,0x89,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, exec_lo, 0xaf123456, v255 :: v_dual_add_f32 v6, exec_lo, v255
+// GFX12: encoding: [0x7e,0xfe,0x89,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, m0, 0xaf123456, v255 :: v_dual_add_f32 v6, m0, v255
+// GFX12: encoding: [0x7d,0xfe,0x89,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, vcc_hi, 0xaf123456, v255 :: v_dual_add_f32 v6, vcc_hi, v255
+// GFX12: encoding: [0x6b,0xfe,0x89,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, vcc_lo, 0xaf123456, v255 :: v_dual_add_f32 v6, vcc_lo, v255
+// GFX12: encoding: [0x6a,0xfe,0x89,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_add_f32 v6, null, v255
+// GFX12: encoding: [0xff,0xfe,0x89,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, src_scc, 0xaf123456, v255 :: v_dual_add_f32 v6, -1, v255
+// GFX12: encoding: [0xfd,0xfe,0x89,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_add_f32 v6, 0.5, v3
+// GFX12: encoding: [0xf0,0xfe,0x89,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_add_f32 v6, src_scc, v4
+// GFX12: encoding: [0xc1,0xfe,0x89,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_add_f32 v255, 0xaf123456, v5
+// GFX12: encoding: [0x7c,0x08,0x88,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, v1, v255
+// GFX12: encoding: [0x04,0xff,0xa1,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, v255, v255
+// GFX12: encoding: [0x01,0xff,0xa1,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, v2, v255
+// GFX12: encoding: [0xff,0xff,0xa1,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, v3, v255
+// GFX12: encoding: [0x02,0xff,0xa1,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, v4, v255
+// GFX12: encoding: [0x03,0xff,0xa1,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, s105, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, s105, v255
+// GFX12: encoding: [0x69,0xfe,0xa1,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, s1, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, s1, v255
+// GFX12: encoding: [0x01,0xfe,0xa1,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, ttmp15, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, ttmp15, v255
+// GFX12: encoding: [0x7b,0xfe,0xa1,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, exec_hi, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, exec_hi, v255
+// GFX12: encoding: [0x7f,0xfe,0xa1,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, exec_lo, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, exec_lo, v255
+// GFX12: encoding: [0x7e,0xfe,0xa1,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, m0, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, m0, v255
+// GFX12: encoding: [0x7d,0xfe,0xa1,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, vcc_hi, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, vcc_hi, v255
+// GFX12: encoding: [0x6b,0xfe,0xa1,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, vcc_lo, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, vcc_lo, v255
+// GFX12: encoding: [0x6a,0xfe,0xa1,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, null, v255
+// GFX12: encoding: [0xff,0xfe,0xa1,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, src_scc, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, -1, v255
+// GFX12: encoding: [0xfd,0xfe,0xa1,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, 0.5, v3
+// GFX12: encoding: [0xf0,0xfe,0xa1,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, src_scc, v4
+// GFX12: encoding: [0xc1,0xfe,0xa1,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_add_nc_u32 v255, 0xaf123456, v5
+// GFX12: encoding: [0x7c,0x08,0xa0,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_and_b32 v6, v1, v255
+// GFX12: encoding: [0x04,0xff,0xa5,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_and_b32 v6, v255, v255
+// GFX12: encoding: [0x01,0xff,0xa5,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_and_b32 v6, v2, v255
+// GFX12: encoding: [0xff,0xff,0xa5,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_and_b32 v6, v3, v255
+// GFX12: encoding: [0x02,0xff,0xa5,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_and_b32 v6, v4, v255
+// GFX12: encoding: [0x03,0xff,0xa5,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, s105, 0xaf123456, v255 :: v_dual_and_b32 v6, s105, v255
+// GFX12: encoding: [0x69,0xfe,0xa5,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, s1, 0xaf123456, v255 :: v_dual_and_b32 v6, s1, v255
+// GFX12: encoding: [0x01,0xfe,0xa5,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, ttmp15, 0xaf123456, v255 :: v_dual_and_b32 v6, ttmp15, v255
+// GFX12: encoding: [0x7b,0xfe,0xa5,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, exec_hi, 0xaf123456, v255 :: v_dual_and_b32 v6, exec_hi, v255
+// GFX12: encoding: [0x7f,0xfe,0xa5,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, exec_lo, 0xaf123456, v255 :: v_dual_and_b32 v6, exec_lo, v255
+// GFX12: encoding: [0x7e,0xfe,0xa5,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, m0, 0xaf123456, v255 :: v_dual_and_b32 v6, m0, v255
+// GFX12: encoding: [0x7d,0xfe,0xa5,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, vcc_hi, 0xaf123456, v255 :: v_dual_and_b32 v6, vcc_hi, v255
+// GFX12: encoding: [0x6b,0xfe,0xa5,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, vcc_lo, 0xaf123456, v255 :: v_dual_and_b32 v6, vcc_lo, v255
+// GFX12: encoding: [0x6a,0xfe,0xa5,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_and_b32 v6, null, v255
+// GFX12: encoding: [0xff,0xfe,0xa5,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, src_scc, 0xaf123456, v255 :: v_dual_and_b32 v6, -1, v255
+// GFX12: encoding: [0xfd,0xfe,0xa5,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_and_b32 v6, 0.5, v3
+// GFX12: encoding: [0xf0,0xfe,0xa5,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_and_b32 v6, src_scc, v4
+// GFX12: encoding: [0xc1,0xfe,0xa5,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_and_b32 v255, 0xaf123456, v5
+// GFX12: encoding: [0x7c,0x08,0xa4,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_cndmask_b32 v6, v1, v255
+// GFX12: encoding: [0x04,0xff,0x93,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_cndmask_b32 v6, v255, v255
+// GFX12: encoding: [0x01,0xff,0x93,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_cndmask_b32 v6, v2, v255
+// GFX12: encoding: [0xff,0xff,0x93,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_cndmask_b32 v6, v3, v255
+// GFX12: encoding: [0x02,0xff,0x93,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_cndmask_b32 v6, v4, v255
+// GFX12: encoding: [0x03,0xff,0x93,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_cndmask_b32 v6, null, v255
+// GFX12: encoding: [0xff,0xfe,0x93,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_cndmask_b32 v6, -1, v3
+// GFX12: encoding: [0xf0,0xfe,0x93,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_cndmask_b32 v6, 0.5, v4
+// GFX12: encoding: [0xc1,0xfe,0x93,0xc8,0xf0,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_cndmask_b32 v255, 0xaf123456, v5
+// GFX12: encoding: [0x7c,0x08,0x92,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, v1, v255, 0xaf123456
+// GFX12: encoding: [0x04,0xff,0x83,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, v255, v255, 0xaf123456
+// GFX12: encoding: [0x01,0xff,0x83,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, v2, v255, 0xaf123456
+// GFX12: encoding: [0xff,0xff,0x83,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, v3, v255, 0xaf123456
+// GFX12: encoding: [0x02,0xff,0x83,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, v4, v255, 0xaf123456
+// GFX12: encoding: [0x03,0xff,0x83,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, s105, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, s105, v255, 0xaf123456
+// GFX12: encoding: [0x69,0xfe,0x83,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, s1, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, s1, v255, 0xaf123456
+// GFX12: encoding: [0x01,0xfe,0x83,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, ttmp15, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, ttmp15, v255, 0xaf123456
+// GFX12: encoding: [0x7b,0xfe,0x83,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, exec_hi, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, exec_hi, v255, 0xaf123456
+// GFX12: encoding: [0x7f,0xfe,0x83,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, exec_lo, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, exec_lo, v255, 0xaf123456
+// GFX12: encoding: [0x7e,0xfe,0x83,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, m0, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, m0, v255, 0xaf123456
+// GFX12: encoding: [0x7d,0xfe,0x83,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, vcc_hi, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, vcc_hi, v255, 0xaf123456
+// GFX12: encoding: [0x6b,0xfe,0x83,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, vcc_lo, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, vcc_lo, v255, 0xaf123456
+// GFX12: encoding: [0x6a,0xfe,0x83,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, null, v255, 0xaf123456
+// GFX12: encoding: [0xff,0xfe,0x83,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, src_scc, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, -1, v255, 0xaf123456
+// GFX12: encoding: [0xfd,0xfe,0x83,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, 0.5, v3, 0xaf123456
+// GFX12: encoding: [0xf0,0xfe,0x83,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, src_scc, v4, 0xaf123456
+// GFX12: encoding: [0xc1,0xfe,0x83,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_fmaak_f32 v255, 0xaf123456, v5, 0xaf123456
+// GFX12: encoding: [0x7c,0x08,0x82,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_fmac_f32 v6, v1, v255
+// GFX12: encoding: [0x04,0xff,0x81,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_fmac_f32 v6, v255, v255
+// GFX12: encoding: [0x01,0xff,0x81,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_fmac_f32 v6, v2, v255
+// GFX12: encoding: [0xff,0xff,0x81,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_fmac_f32 v6, v3, v255
+// GFX12: encoding: [0x02,0xff,0x81,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_fmac_f32 v6, v4, v255
+// GFX12: encoding: [0x03,0xff,0x81,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, s105, 0xaf123456, v255 :: v_dual_fmac_f32 v6, s105, v255
+// GFX12: encoding: [0x69,0xfe,0x81,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, s1, 0xaf123456, v255 :: v_dual_fmac_f32 v6, s1, v255
+// GFX12: encoding: [0x01,0xfe,0x81,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, ttmp15, 0xaf123456, v255 :: v_dual_fmac_f32 v6, ttmp15, v255
+// GFX12: encoding: [0x7b,0xfe,0x81,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, exec_hi, 0xaf123456, v255 :: v_dual_fmac_f32 v6, exec_hi, v255
+// GFX12: encoding: [0x7f,0xfe,0x81,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, exec_lo, 0xaf123456, v255 :: v_dual_fmac_f32 v6, exec_lo, v255
+// GFX12: encoding: [0x7e,0xfe,0x81,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, m0, 0xaf123456, v255 :: v_dual_fmac_f32 v6, m0, v255
+// GFX12: encoding: [0x7d,0xfe,0x81,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, vcc_hi, 0xaf123456, v255 :: v_dual_fmac_f32 v6, vcc_hi, v255
+// GFX12: encoding: [0x6b,0xfe,0x81,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, vcc_lo, 0xaf123456, v255 :: v_dual_fmac_f32 v6, vcc_lo, v255
+// GFX12: encoding: [0x6a,0xfe,0x81,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_fmac_f32 v6, null, v255
+// GFX12: encoding: [0xff,0xfe,0x81,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, src_scc, 0xaf123456, v255 :: v_dual_fmac_f32 v6, -1, v255
+// GFX12: encoding: [0xfd,0xfe,0x81,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_fmac_f32 v6, 0.5, v3
+// GFX12: encoding: [0xf0,0xfe,0x81,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_fmac_f32 v6, src_scc, v4
+// GFX12: encoding: [0xc1,0xfe,0x81,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_fmac_f32 v255, 0xaf123456, v5
+// GFX12: encoding: [0x7c,0x08,0x80,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, v1, 0xaf123456, v4
+// GFX12: encoding: [0x04,0xff,0x85,0xc8,0x01,0x09,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, v255, 0xaf123456, v4
+// GFX12: encoding: [0x01,0xff,0x85,0xc8,0xff,0x09,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, v2, 0xaf123456, v4
+// GFX12: encoding: [0xff,0xff,0x85,0xc8,0x02,0x09,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, v3, 0xaf123456, v4
+// GFX12: encoding: [0x02,0xff,0x85,0xc8,0x03,0x09,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, v4, 0xaf123456, v4
+// GFX12: encoding: [0x03,0xff,0x85,0xc8,0x04,0x09,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, s105, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, s105, 0xaf123456, v4
+// GFX12: encoding: [0x69,0xfe,0x85,0xc8,0x69,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, s1, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, s1, 0xaf123456, v4
+// GFX12: encoding: [0x01,0xfe,0x85,0xc8,0x01,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, ttmp15, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, ttmp15, 0xaf123456, v4
+// GFX12: encoding: [0x7b,0xfe,0x85,0xc8,0x7b,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, exec_hi, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, exec_hi, 0xaf123456, v4
+// GFX12: encoding: [0x7f,0xfe,0x85,0xc8,0x7f,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, exec_lo, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, exec_lo, 0xaf123456, v4
+// GFX12: encoding: [0x7e,0xfe,0x85,0xc8,0x7e,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, m0, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, m0, 0xaf123456, v4
+// GFX12: encoding: [0x7d,0xfe,0x85,0xc8,0x7d,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, vcc_hi, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, vcc_hi, 0xaf123456, v4
+// GFX12: encoding: [0x6b,0xfe,0x85,0xc8,0x6b,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, vcc_lo, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, vcc_lo, 0xaf123456, v4
+// GFX12: encoding: [0x6a,0xfe,0x85,0xc8,0x6a,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, null, 0xaf123456, v4
+// GFX12: encoding: [0xff,0xfe,0x85,0xc8,0x7c,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, src_scc, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, -1, 0xaf123456, v4
+// GFX12: encoding: [0xfd,0xfe,0x85,0xc8,0xc1,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, 0.5, 0xaf123456, v4
+// GFX12: encoding: [0xf0,0xfe,0x85,0xc8,0xf0,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, src_scc, 0xaf123456, v4
+// GFX12: encoding: [0xc1,0xfe,0x85,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255
+// GFX12: encoding: [0x7c,0x08,0x84,0xc8,0xff,0xfe,0xff,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, v1, v255
+// GFX12: encoding: [0x04,0xff,0xa3,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, v255, v255
+// GFX12: encoding: [0x01,0xff,0xa3,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, v2, v255
+// GFX12: encoding: [0xff,0xff,0xa3,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, v3, v255
+// GFX12: encoding: [0x02,0xff,0xa3,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, v4, v255
+// GFX12: encoding: [0x03,0xff,0xa3,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, s105, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, s105, v255
+// GFX12: encoding: [0x69,0xfe,0xa3,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, s1, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, s1, v255
+// GFX12: encoding: [0x01,0xfe,0xa3,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, ttmp15, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, ttmp15, v255
+// GFX12: encoding: [0x7b,0xfe,0xa3,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, exec_hi, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, exec_hi, v255
+// GFX12: encoding: [0x7f,0xfe,0xa3,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, exec_lo, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, exec_lo, v255
+// GFX12: encoding: [0x7e,0xfe,0xa3,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, m0, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, m0, v255
+// GFX12: encoding: [0x7d,0xfe,0xa3,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, vcc_hi, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, vcc_hi, v255
+// GFX12: encoding: [0x6b,0xfe,0xa3,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, vcc_lo, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, vcc_lo, v255
+// GFX12: encoding: [0x6a,0xfe,0xa3,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, null, v255
+// GFX12: encoding: [0xff,0xfe,0xa3,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, src_scc, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, -1, v255
+// GFX12: encoding: [0xfd,0xfe,0xa3,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, 0.5, v3
+// GFX12: encoding: [0xf0,0xfe,0xa3,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, src_scc, v4
+// GFX12: encoding: [0xc1,0xfe,0xa3,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_lshlrev_b32 v255, 0xaf123456, v5
+// GFX12: encoding: [0x7c,0x08,0xa2,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_max_num_f32 v6, v1, v255
+// GFX12: encoding: [0x04,0xff,0x95,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_max_num_f32 v6, v255, v255
+// GFX12: encoding: [0x01,0xff,0x95,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_max_num_f32 v6, v2, v255
+// GFX12: encoding: [0xff,0xff,0x95,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_max_num_f32 v6, v3, v255
+// GFX12: encoding: [0x02,0xff,0x95,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_max_num_f32 v6, v4, v255
+// GFX12: encoding: [0x03,0xff,0x95,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, s105, 0xaf123456, v255 :: v_dual_max_num_f32 v6, s105, v255
+// GFX12: encoding: [0x69,0xfe,0x95,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, s1, 0xaf123456, v255 :: v_dual_max_num_f32 v6, s1, v255
+// GFX12: encoding: [0x01,0xfe,0x95,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, ttmp15, 0xaf123456, v255 :: v_dual_max_num_f32 v6, ttmp15, v255
+// GFX12: encoding: [0x7b,0xfe,0x95,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, exec_hi, 0xaf123456, v255 :: v_dual_max_num_f32 v6, exec_hi, v255
+// GFX12: encoding: [0x7f,0xfe,0x95,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, exec_lo, 0xaf123456, v255 :: v_dual_max_num_f32 v6, exec_lo, v255
+// GFX12: encoding: [0x7e,0xfe,0x95,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, m0, 0xaf123456, v255 :: v_dual_max_num_f32 v6, m0, v255
+// GFX12: encoding: [0x7d,0xfe,0x95,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, vcc_hi, 0xaf123456, v255 :: v_dual_max_num_f32 v6, vcc_hi, v255
+// GFX12: encoding: [0x6b,0xfe,0x95,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, vcc_lo, 0xaf123456, v255 :: v_dual_max_num_f32 v6, vcc_lo, v255
+// GFX12: encoding: [0x6a,0xfe,0x95,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_max_num_f32 v6, null, v255
+// GFX12: encoding: [0xff,0xfe,0x95,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, src_scc, 0xaf123456, v255 :: v_dual_max_num_f32 v6, -1, v255
+// GFX12: encoding: [0xfd,0xfe,0x95,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_max_num_f32 v6, 0.5, v3
+// GFX12: encoding: [0xf0,0xfe,0x95,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_max_num_f32 v6, src_scc, v4
+// GFX12: encoding: [0xc1,0xfe,0x95,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_max_num_f32 v255, 0xaf123456, v5
+// GFX12: encoding: [0x7c,0x08,0x94,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_min_num_f32 v6, v1, v255
+// GFX12: encoding: [0x04,0xff,0x97,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_min_num_f32 v6, v255, v255
+// GFX12: encoding: [0x01,0xff,0x97,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_min_num_f32 v6, v2, v255
+// GFX12: encoding: [0xff,0xff,0x97,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_min_num_f32 v6, v3, v255
+// GFX12: encoding: [0x02,0xff,0x97,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_min_num_f32 v6, v4, v255
+// GFX12: encoding: [0x03,0xff,0x97,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, s105, 0xaf123456, v255 :: v_dual_min_num_f32 v6, s105, v255
+// GFX12: encoding: [0x69,0xfe,0x97,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, s1, 0xaf123456, v255 :: v_dual_min_num_f32 v6, s1, v255
+// GFX12: encoding: [0x01,0xfe,0x97,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, ttmp15, 0xaf123456, v255 :: v_dual_min_num_f32 v6, ttmp15, v255
+// GFX12: encoding: [0x7b,0xfe,0x97,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, exec_hi, 0xaf123456, v255 :: v_dual_min_num_f32 v6, exec_hi, v255
+// GFX12: encoding: [0x7f,0xfe,0x97,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, exec_lo, 0xaf123456, v255 :: v_dual_min_num_f32 v6, exec_lo, v255
+// GFX12: encoding: [0x7e,0xfe,0x97,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, m0, 0xaf123456, v255 :: v_dual_min_num_f32 v6, m0, v255
+// GFX12: encoding: [0x7d,0xfe,0x97,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, vcc_hi, 0xaf123456, v255 :: v_dual_min_num_f32 v6, vcc_hi, v255
+// GFX12: encoding: [0x6b,0xfe,0x97,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, vcc_lo, 0xaf123456, v255 :: v_dual_min_num_f32 v6, vcc_lo, v255
+// GFX12: encoding: [0x6a,0xfe,0x97,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_min_num_f32 v6, null, v255
+// GFX12: encoding: [0xff,0xfe,0x97,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, src_scc, 0xaf123456, v255 :: v_dual_min_num_f32 v6, -1, v255
+// GFX12: encoding: [0xfd,0xfe,0x97,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_min_num_f32 v6, 0.5, v3
+// GFX12: encoding: [0xf0,0xfe,0x97,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_min_num_f32 v6, src_scc, v4
+// GFX12: encoding: [0xc1,0xfe,0x97,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_min_num_f32 v255, 0xaf123456, v5
+// GFX12: encoding: [0x7c,0x08,0x96,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_mov_b32 v6, v1
+// GFX12: encoding: [0x04,0xff,0x91,0xc8,0x01,0x01,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_mov_b32 v6, v255
+// GFX12: encoding: [0x01,0xff,0x91,0xc8,0xff,0x01,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_mov_b32 v6, v2
+// GFX12: encoding: [0xff,0xff,0x91,0xc8,0x02,0x01,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_mov_b32 v6, v3
+// GFX12: encoding: [0x02,0xff,0x91,0xc8,0x03,0x01,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_mov_b32 v6, v4
+// GFX12: encoding: [0x03,0xff,0x91,0xc8,0x04,0x01,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, s105, 0xaf123456, v255 :: v_dual_mov_b32 v6, s105
+// GFX12: encoding: [0x69,0xfe,0x91,0xc8,0x69,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, s1, 0xaf123456, v255 :: v_dual_mov_b32 v6, s1
+// GFX12: encoding: [0x01,0xfe,0x91,0xc8,0x01,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, ttmp15, 0xaf123456, v255 :: v_dual_mov_b32 v6, ttmp15
+// GFX12: encoding: [0x7b,0xfe,0x91,0xc8,0x7b,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, exec_hi, 0xaf123456, v255 :: v_dual_mov_b32 v6, exec_hi
+// GFX12: encoding: [0x7f,0xfe,0x91,0xc8,0x7f,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, exec_lo, 0xaf123456, v255 :: v_dual_mov_b32 v6, exec_lo
+// GFX12: encoding: [0x7e,0xfe,0x91,0xc8,0x7e,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, m0, 0xaf123456, v255 :: v_dual_mov_b32 v6, m0
+// GFX12: encoding: [0x7d,0xfe,0x91,0xc8,0x7d,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, vcc_hi, 0xaf123456, v255 :: v_dual_mov_b32 v6, vcc_hi
+// GFX12: encoding: [0x6b,0xfe,0x91,0xc8,0x6b,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, vcc_lo, 0xaf123456, v255 :: v_dual_mov_b32 v6, vcc_lo
+// GFX12: encoding: [0x6a,0xfe,0x91,0xc8,0x6a,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_mov_b32 v6, null
+// GFX12: encoding: [0xff,0xfe,0x91,0xc8,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, src_scc, 0xaf123456, v255 :: v_dual_mov_b32 v6, -1
+// GFX12: encoding: [0xfd,0xfe,0x91,0xc8,0xc1,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_mov_b32 v6, 0.5
+// GFX12: encoding: [0xf0,0xfe,0x91,0xc8,0xf0,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_mov_b32 v6, src_scc
+// GFX12: encoding: [0xc1,0xfe,0x91,0xc8,0xfd,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_mov_b32 v255, 0xaf123456
+// GFX12: encoding: [0x7c,0x08,0x90,0xc8,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, v1, v255
+// GFX12: encoding: [0x04,0xff,0x8f,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, v255, v255
+// GFX12: encoding: [0x01,0xff,0x8f,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, v2, v255
+// GFX12: encoding: [0xff,0xff,0x8f,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, v3, v255
+// GFX12: encoding: [0x02,0xff,0x8f,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, v4, v255
+// GFX12: encoding: [0x03,0xff,0x8f,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, s105, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, s105, v255
+// GFX12: encoding: [0x69,0xfe,0x8f,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, s1, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, s1, v255
+// GFX12: encoding: [0x01,0xfe,0x8f,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, ttmp15, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, ttmp15, v255
+// GFX12: encoding: [0x7b,0xfe,0x8f,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, exec_hi, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, exec_hi, v255
+// GFX12: encoding: [0x7f,0xfe,0x8f,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, exec_lo, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, exec_lo, v255
+// GFX12: encoding: [0x7e,0xfe,0x8f,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, m0, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, m0, v255
+// GFX12: encoding: [0x7d,0xfe,0x8f,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, vcc_hi, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, vcc_hi, v255
+// GFX12: encoding: [0x6b,0xfe,0x8f,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, vcc_lo, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, vcc_lo, v255
+// GFX12: encoding: [0x6a,0xfe,0x8f,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, null, v255
+// GFX12: encoding: [0xff,0xfe,0x8f,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, src_scc, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, -1, v255
+// GFX12: encoding: [0xfd,0xfe,0x8f,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, 0.5, v3
+// GFX12: encoding: [0xf0,0xfe,0x8f,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, src_scc, v4
+// GFX12: encoding: [0xc1,0xfe,0x8f,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v5
+// GFX12: encoding: [0x7c,0x08,0x8e,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_mul_f32 v6, v1, v255
+// GFX12: encoding: [0x04,0xff,0x87,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_mul_f32 v6, v255, v255
+// GFX12: encoding: [0x01,0xff,0x87,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_mul_f32 v6, v2, v255
+// GFX12: encoding: [0xff,0xff,0x87,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_mul_f32 v6, v3, v255
+// GFX12: encoding: [0x02,0xff,0x87,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_mul_f32 v6, v4, v255
+// GFX12: encoding: [0x03,0xff,0x87,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, s105, 0xaf123456, v255 :: v_dual_mul_f32 v6, s105, v255
+// GFX12: encoding: [0x69,0xfe,0x87,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, s1, 0xaf123456, v255 :: v_dual_mul_f32 v6, s1, v255
+// GFX12: encoding: [0x01,0xfe,0x87,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, ttmp15, 0xaf123456, v255 :: v_dual_mul_f32 v6, ttmp15, v255
+// GFX12: encoding: [0x7b,0xfe,0x87,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, exec_hi, 0xaf123456, v255 :: v_dual_mul_f32 v6, exec_hi, v255
+// GFX12: encoding: [0x7f,0xfe,0x87,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, exec_lo, 0xaf123456, v255 :: v_dual_mul_f32 v6, exec_lo, v255
+// GFX12: encoding: [0x7e,0xfe,0x87,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, m0, 0xaf123456, v255 :: v_dual_mul_f32 v6, m0, v255
+// GFX12: encoding: [0x7d,0xfe,0x87,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, vcc_hi, 0xaf123456, v255 :: v_dual_mul_f32 v6, vcc_hi, v255
+// GFX12: encoding: [0x6b,0xfe,0x87,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, vcc_lo, 0xaf123456, v255 :: v_dual_mul_f32 v6, vcc_lo, v255
+// GFX12: encoding: [0x6a,0xfe,0x87,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_mul_f32 v6, null, v255
+// GFX12: encoding: [0xff,0xfe,0x87,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, src_scc, 0xaf123456, v255 :: v_dual_mul_f32 v6, -1, v255
+// GFX12: encoding: [0xfd,0xfe,0x87,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_mul_f32 v6, 0.5, v3
+// GFX12: encoding: [0xf0,0xfe,0x87,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_mul_f32 v6, src_scc, v4
+// GFX12: encoding: [0xc1,0xfe,0x87,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_mul_f32 v255, 0xaf123456, v5
+// GFX12: encoding: [0x7c,0x08,0x86,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_sub_f32 v6, v1, v255
+// GFX12: encoding: [0x04,0xff,0x8b,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_sub_f32 v6, v255, v255
+// GFX12: encoding: [0x01,0xff,0x8b,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_sub_f32 v6, v2, v255
+// GFX12: encoding: [0xff,0xff,0x8b,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_sub_f32 v6, v3, v255
+// GFX12: encoding: [0x02,0xff,0x8b,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_sub_f32 v6, v4, v255
+// GFX12: encoding: [0x03,0xff,0x8b,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, s105, 0xaf123456, v255 :: v_dual_sub_f32 v6, s105, v255
+// GFX12: encoding: [0x69,0xfe,0x8b,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, s1, 0xaf123456, v255 :: v_dual_sub_f32 v6, s1, v255
+// GFX12: encoding: [0x01,0xfe,0x8b,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, ttmp15, 0xaf123456, v255 :: v_dual_sub_f32 v6, ttmp15, v255
+// GFX12: encoding: [0x7b,0xfe,0x8b,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, exec_hi, 0xaf123456, v255 :: v_dual_sub_f32 v6, exec_hi, v255
+// GFX12: encoding: [0x7f,0xfe,0x8b,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, exec_lo, 0xaf123456, v255 :: v_dual_sub_f32 v6, exec_lo, v255
+// GFX12: encoding: [0x7e,0xfe,0x8b,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, m0, 0xaf123456, v255 :: v_dual_sub_f32 v6, m0, v255
+// GFX12: encoding: [0x7d,0xfe,0x8b,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, vcc_hi, 0xaf123456, v255 :: v_dual_sub_f32 v6, vcc_hi, v255
+// GFX12: encoding: [0x6b,0xfe,0x8b,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, vcc_lo, 0xaf123456, v255 :: v_dual_sub_f32 v6, vcc_lo, v255
+// GFX12: encoding: [0x6a,0xfe,0x8b,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_sub_f32 v6, null, v255
+// GFX12: encoding: [0xff,0xfe,0x8b,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, src_scc, 0xaf123456, v255 :: v_dual_sub_f32 v6, -1, v255
+// GFX12: encoding: [0xfd,0xfe,0x8b,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_sub_f32 v6, 0.5, v3
+// GFX12: encoding: [0xf0,0xfe,0x8b,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_sub_f32 v6, src_scc, v4
+// GFX12: encoding: [0xc1,0xfe,0x8b,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_sub_f32 v255, 0xaf123456, v5
+// GFX12: encoding: [0x7c,0x08,0x8a,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_subrev_f32 v6, v1, v255
+// GFX12: encoding: [0x04,0xff,0x8d,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_subrev_f32 v6, v255, v255
+// GFX12: encoding: [0x01,0xff,0x8d,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_subrev_f32 v6, v2, v255
+// GFX12: encoding: [0xff,0xff,0x8d,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_subrev_f32 v6, v3, v255
+// GFX12: encoding: [0x02,0xff,0x8d,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_subrev_f32 v6, v4, v255
+// GFX12: encoding: [0x03,0xff,0x8d,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, s105, 0xaf123456, v255 :: v_dual_subrev_f32 v6, s105, v255
+// GFX12: encoding: [0x69,0xfe,0x8d,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, s1, 0xaf123456, v255 :: v_dual_subrev_f32 v6, s1, v255
+// GFX12: encoding: [0x01,0xfe,0x8d,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, ttmp15, 0xaf123456, v255 :: v_dual_subrev_f32 v6, ttmp15, v255
+// GFX12: encoding: [0x7b,0xfe,0x8d,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, exec_hi, 0xaf123456, v255 :: v_dual_subrev_f32 v6, exec_hi, v255
+// GFX12: encoding: [0x7f,0xfe,0x8d,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, exec_lo, 0xaf123456, v255 :: v_dual_subrev_f32 v6, exec_lo, v255
+// GFX12: encoding: [0x7e,0xfe,0x8d,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, m0, 0xaf123456, v255 :: v_dual_subrev_f32 v6, m0, v255
+// GFX12: encoding: [0x7d,0xfe,0x8d,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, vcc_hi, 0xaf123456, v255 :: v_dual_subrev_f32 v6, vcc_hi, v255
+// GFX12: encoding: [0x6b,0xfe,0x8d,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, vcc_lo, 0xaf123456, v255 :: v_dual_subrev_f32 v6, vcc_lo, v255
+// GFX12: encoding: [0x6a,0xfe,0x8d,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_subrev_f32 v6, null, v255
+// GFX12: encoding: [0xff,0xfe,0x8d,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, src_scc, 0xaf123456, v255 :: v_dual_subrev_f32 v6, -1, v255
+// GFX12: encoding: [0xfd,0xfe,0x8d,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_subrev_f32 v6, 0.5, v3
+// GFX12: encoding: [0xf0,0xfe,0x8d,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_subrev_f32 v6, src_scc, v4
+// GFX12: encoding: [0xc1,0xfe,0x8d,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_subrev_f32 v255, 0xaf123456, v5
+// GFX12: encoding: [0x7c,0x08,0x8c,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v4, v2 :: v_dual_add_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x88,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v1, v2 :: v_dual_add_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x88,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v255, v2 :: v_dual_add_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x88,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v2, v2 :: v_dual_add_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x88,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v3, v2 :: v_dual_add_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x88,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s105, v2 :: v_dual_add_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x88,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s1, v2 :: v_dual_add_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x88,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, ttmp15, v2 :: v_dual_add_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x88,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_hi, v2 :: v_dual_add_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x88,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_lo, v2 :: v_dual_add_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x88,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, m0, v2 :: v_dual_add_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x88,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_hi, v2 :: v_dual_add_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x88,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_lo, v2 :: v_dual_add_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x88,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0xaf123456, v2 :: v_dual_add_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x88,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, src_scc, v2 :: v_dual_add_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x88,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_add_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x88,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, -1, v4 :: v_dual_add_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x88,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v6, null, v5 :: v_dual_add_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x88,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v4, v2 :: v_dual_add_nc_u32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xa0,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v1, v2 :: v_dual_add_nc_u32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xa0,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v255, v2 :: v_dual_add_nc_u32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xa0,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v2, v2 :: v_dual_add_nc_u32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xa0,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v3, v2 :: v_dual_add_nc_u32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xa0,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s105, v2 :: v_dual_add_nc_u32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xa0,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s1, v2 :: v_dual_add_nc_u32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xa0,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, ttmp15, v2 :: v_dual_add_nc_u32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xa0,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_hi, v2 :: v_dual_add_nc_u32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xa0,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_lo, v2 :: v_dual_add_nc_u32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xa0,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, m0, v2 :: v_dual_add_nc_u32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xa0,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_hi, v2 :: v_dual_add_nc_u32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xa0,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_lo, v2 :: v_dual_add_nc_u32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xa0,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0xaf123456, v2 :: v_dual_add_nc_u32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xa0,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, src_scc, v2 :: v_dual_add_nc_u32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xa0,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_add_nc_u32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xa0,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, -1, v4 :: v_dual_add_nc_u32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xa0,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v6, null, v5 :: v_dual_add_nc_u32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xa0,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v4, v2 :: v_dual_and_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xa4,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v1, v2 :: v_dual_and_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xa4,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v255, v2 :: v_dual_and_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xa4,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v2, v2 :: v_dual_and_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xa4,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v3, v2 :: v_dual_and_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xa4,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s105, v2 :: v_dual_and_b32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xa4,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s1, v2 :: v_dual_and_b32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xa4,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, ttmp15, v2 :: v_dual_and_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xa4,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_hi, v2 :: v_dual_and_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xa4,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_lo, v2 :: v_dual_and_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xa4,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, m0, v2 :: v_dual_and_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xa4,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_hi, v2 :: v_dual_and_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xa4,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_lo, v2 :: v_dual_and_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xa4,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0xaf123456, v2 :: v_dual_and_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xa4,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, src_scc, v2 :: v_dual_and_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xa4,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_and_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xa4,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, -1, v4 :: v_dual_and_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xa4,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v6, null, v5 :: v_dual_and_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xa4,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v4, v2 :: v_dual_cndmask_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x92,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v1, v2 :: v_dual_cndmask_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x92,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v255, v2 :: v_dual_cndmask_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x92,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v2, v2 :: v_dual_cndmask_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x92,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v3, v2 :: v_dual_cndmask_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x92,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s105, v2 :: v_dual_cndmask_b32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x92,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s1, v2 :: v_dual_cndmask_b32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x92,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, ttmp15, v2 :: v_dual_cndmask_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0x92,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_hi, v2 :: v_dual_cndmask_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x92,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_lo, v2 :: v_dual_cndmask_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0x92,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, m0, v2 :: v_dual_cndmask_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x92,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_hi, v2 :: v_dual_cndmask_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0x92,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_lo, v2 :: v_dual_cndmask_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0x92,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0xaf123456, v2 :: v_dual_cndmask_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x92,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, src_scc, v2 :: v_dual_cndmask_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x92,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_cndmask_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x92,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, -1, v4 :: v_dual_cndmask_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x92,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v6, null, v5 :: v_dual_cndmask_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x92,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v4, v2 :: v_dual_fmaak_f32 v6, v1, v3, 0xaf123456
+// GFX12: encoding: [0x04,0x05,0x82,0xca,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v1, v2 :: v_dual_fmaak_f32 v6, v255, v3, 0xaf123456
+// GFX12: encoding: [0x01,0x05,0x82,0xca,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v255, v2 :: v_dual_fmaak_f32 v6, v2, v3, 0xaf123456
+// GFX12: encoding: [0xff,0x05,0x82,0xca,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v2, v2 :: v_dual_fmaak_f32 v6, v3, v3, 0xaf123456
+// GFX12: encoding: [0x02,0x05,0x82,0xca,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v3, v2 :: v_dual_fmaak_f32 v6, v4, v3, 0xaf123456
+// GFX12: encoding: [0x03,0x05,0x82,0xca,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s105, v2 :: v_dual_fmaak_f32 v6, s105, v3, 0xaf123456
+// GFX12: encoding: [0x69,0x04,0x82,0xca,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s1, v2 :: v_dual_fmaak_f32 v6, s1, v3, 0xaf123456
+// GFX12: encoding: [0x01,0x04,0x82,0xca,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, ttmp15, v2 :: v_dual_fmaak_f32 v6, ttmp15, v3, 0xaf123456
+// GFX12: encoding: [0x7b,0x04,0x82,0xca,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_hi, v2 :: v_dual_fmaak_f32 v6, exec_hi, v3, 0xaf123456
+// GFX12: encoding: [0x7f,0x04,0x82,0xca,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_lo, v2 :: v_dual_fmaak_f32 v6, exec_lo, v3, 0xaf123456
+// GFX12: encoding: [0x7e,0x04,0x82,0xca,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, m0, v2 :: v_dual_fmaak_f32 v6, m0, v3, 0xaf123456
+// GFX12: encoding: [0x7d,0x04,0x82,0xca,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_hi, v2 :: v_dual_fmaak_f32 v6, vcc_hi, v3, 0xaf123456
+// GFX12: encoding: [0x6b,0x04,0x82,0xca,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_lo, v2 :: v_dual_fmaak_f32 v6, vcc_lo, v3, 0xaf123456
+// GFX12: encoding: [0x6a,0x04,0x82,0xca,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, null, v3, 0xaf123456
+// GFX12: encoding: [0xff,0x04,0x82,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, src_scc, v2 :: v_dual_fmaak_f32 v6, -1, v3, 0xaf123456
+// GFX12: encoding: [0xfd,0x04,0x82,0xca,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_fmaak_f32 v6, 0.5, v2, 0xaf123456
+// GFX12: encoding: [0xf0,0x06,0x82,0xca,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, -1, v4 :: v_dual_fmaak_f32 v6, src_scc, v5, 0xaf123456
+// GFX12: encoding: [0xc1,0x08,0x82,0xca,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v6, null, v5 :: v_dual_fmaak_f32 v255, 0xaf123456, v4, 0xaf123456
+// GFX12: encoding: [0x7c,0x0a,0x82,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v4, v2 :: v_dual_fmac_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x80,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v1, v2 :: v_dual_fmac_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x80,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v255, v2 :: v_dual_fmac_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x80,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v2, v2 :: v_dual_fmac_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x80,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v3, v2 :: v_dual_fmac_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x80,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s105, v2 :: v_dual_fmac_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x80,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s1, v2 :: v_dual_fmac_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x80,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, ttmp15, v2 :: v_dual_fmac_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x80,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_hi, v2 :: v_dual_fmac_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x80,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_lo, v2 :: v_dual_fmac_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x80,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, m0, v2 :: v_dual_fmac_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x80,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_hi, v2 :: v_dual_fmac_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x80,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_lo, v2 :: v_dual_fmac_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x80,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0xaf123456, v2 :: v_dual_fmac_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x80,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, src_scc, v2 :: v_dual_fmac_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x80,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_fmac_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x80,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, -1, v4 :: v_dual_fmac_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x80,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v6, null, v5 :: v_dual_fmac_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x80,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v4, v255 :: v_dual_fmamk_f32 v6, v1, 0xaf123456, v255
+// GFX12: encoding: [0x04,0xff,0x85,0xca,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v1, v255 :: v_dual_fmamk_f32 v6, v255, 0xaf123456, v255
+// GFX12: encoding: [0x01,0xff,0x85,0xca,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v255, v255 :: v_dual_fmamk_f32 v6, v2, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xff,0x85,0xca,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v2, v255 :: v_dual_fmamk_f32 v6, v3, 0xaf123456, v255
+// GFX12: encoding: [0x02,0xff,0x85,0xca,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v3, v255 :: v_dual_fmamk_f32 v6, v4, 0xaf123456, v255
+// GFX12: encoding: [0x03,0xff,0x85,0xca,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s105, v255 :: v_dual_fmamk_f32 v6, s105, 0xaf123456, v255
+// GFX12: encoding: [0x69,0xfe,0x85,0xca,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s1, v255 :: v_dual_fmamk_f32 v6, s1, 0xaf123456, v255
+// GFX12: encoding: [0x01,0xfe,0x85,0xca,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, ttmp15, v255 :: v_dual_fmamk_f32 v6, ttmp15, 0xaf123456, v255
+// GFX12: encoding: [0x7b,0xfe,0x85,0xca,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_hi, v255 :: v_dual_fmamk_f32 v6, exec_hi, 0xaf123456, v255
+// GFX12: encoding: [0x7f,0xfe,0x85,0xca,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_lo, v255 :: v_dual_fmamk_f32 v6, exec_lo, 0xaf123456, v255
+// GFX12: encoding: [0x7e,0xfe,0x85,0xca,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, m0, v255 :: v_dual_fmamk_f32 v6, m0, 0xaf123456, v255
+// GFX12: encoding: [0x7d,0xfe,0x85,0xca,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_hi, v255 :: v_dual_fmamk_f32 v6, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x6b,0xfe,0x85,0xca,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_lo, v255 :: v_dual_fmamk_f32 v6, vcc_lo, 0xaf123456, v255
+// GFX12: encoding: [0x6a,0xfe,0x85,0xca,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, null, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x85,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, src_scc, v255 :: v_dual_fmamk_f32 v6, -1, 0xaf123456, v255
+// GFX12: encoding: [0xfd,0xfe,0x85,0xca,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_fmamk_f32 v6, 0.5, 0xaf123456, v255
+// GFX12: encoding: [0xf0,0x06,0x84,0xca,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, -1, v4 :: v_dual_fmamk_f32 v6, src_scc, 0xaf123456, v255
+// GFX12: encoding: [0xc1,0x08,0x84,0xca,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v6, null, v5 :: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x84,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v4, v2 :: v_dual_lshlrev_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xa2,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v1, v2 :: v_dual_lshlrev_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xa2,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v255, v2 :: v_dual_lshlrev_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xa2,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v2, v2 :: v_dual_lshlrev_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xa2,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v3, v2 :: v_dual_lshlrev_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xa2,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s105, v2 :: v_dual_lshlrev_b32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xa2,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s1, v2 :: v_dual_lshlrev_b32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xa2,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, ttmp15, v2 :: v_dual_lshlrev_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xa2,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_hi, v2 :: v_dual_lshlrev_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xa2,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_lo, v2 :: v_dual_lshlrev_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xa2,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, m0, v2 :: v_dual_lshlrev_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xa2,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_hi, v2 :: v_dual_lshlrev_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xa2,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_lo, v2 :: v_dual_lshlrev_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xa2,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0xaf123456, v2 :: v_dual_lshlrev_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xa2,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, src_scc, v2 :: v_dual_lshlrev_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xa2,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_lshlrev_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xa2,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, -1, v4 :: v_dual_lshlrev_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xa2,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v6, null, v5 :: v_dual_lshlrev_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xa2,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v4, v2 :: v_dual_max_num_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x94,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v1, v2 :: v_dual_max_num_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x94,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v255, v2 :: v_dual_max_num_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x94,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v2, v2 :: v_dual_max_num_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x94,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v3, v2 :: v_dual_max_num_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x94,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s105, v2 :: v_dual_max_num_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x94,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s1, v2 :: v_dual_max_num_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x94,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, ttmp15, v2 :: v_dual_max_num_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x94,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_hi, v2 :: v_dual_max_num_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x94,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_lo, v2 :: v_dual_max_num_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x94,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, m0, v2 :: v_dual_max_num_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x94,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_hi, v2 :: v_dual_max_num_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x94,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_lo, v2 :: v_dual_max_num_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x94,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0xaf123456, v2 :: v_dual_max_num_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x94,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, src_scc, v2 :: v_dual_max_num_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x94,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_max_num_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x94,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, -1, v4 :: v_dual_max_num_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x94,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v6, null, v5 :: v_dual_max_num_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x94,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v4, v2 :: v_dual_min_num_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x96,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v1, v2 :: v_dual_min_num_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x96,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v255, v2 :: v_dual_min_num_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x96,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v2, v2 :: v_dual_min_num_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x96,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v3, v2 :: v_dual_min_num_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x96,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s105, v2 :: v_dual_min_num_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x96,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s1, v2 :: v_dual_min_num_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x96,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, ttmp15, v2 :: v_dual_min_num_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x96,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_hi, v2 :: v_dual_min_num_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x96,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_lo, v2 :: v_dual_min_num_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x96,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, m0, v2 :: v_dual_min_num_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x96,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_hi, v2 :: v_dual_min_num_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x96,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_lo, v2 :: v_dual_min_num_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x96,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0xaf123456, v2 :: v_dual_min_num_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x96,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, src_scc, v2 :: v_dual_min_num_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x96,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_min_num_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x96,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, -1, v4 :: v_dual_min_num_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x96,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v6, null, v5 :: v_dual_min_num_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x96,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v4, v255 :: v_dual_mov_b32 v6, v1
+// GFX12: encoding: [0x04,0xff,0x91,0xca,0x01,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v1, v255 :: v_dual_mov_b32 v6, v255
+// GFX12: encoding: [0x01,0xff,0x91,0xca,0xff,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v255, v255 :: v_dual_mov_b32 v6, v2
+// GFX12: encoding: [0xff,0xff,0x91,0xca,0x02,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v2, v255 :: v_dual_mov_b32 v6, v3
+// GFX12: encoding: [0x02,0xff,0x91,0xca,0x03,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v3, v255 :: v_dual_mov_b32 v6, v4
+// GFX12: encoding: [0x03,0xff,0x91,0xca,0x04,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s105, v255 :: v_dual_mov_b32 v6, s1
+// GFX12: encoding: [0x69,0xfe,0x91,0xca,0x01,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s1, v255 :: v_dual_mov_b32 v6, s105
+// GFX12: encoding: [0x01,0xfe,0x91,0xca,0x69,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, ttmp15, v255 :: v_dual_mov_b32 v6, vcc_lo
+// GFX12: encoding: [0x7b,0xfe,0x91,0xca,0x6a,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_hi, v255 :: v_dual_mov_b32 v6, vcc_hi
+// GFX12: encoding: [0x7f,0xfe,0x91,0xca,0x6b,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_lo, v255 :: v_dual_mov_b32 v6, ttmp15
+// GFX12: encoding: [0x7e,0xfe,0x91,0xca,0x7b,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, m0, v255 :: v_dual_mov_b32 v6, m0
+// GFX12: encoding: [0x7d,0xfe,0x91,0xca,0x7d,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_hi, v255 :: v_dual_mov_b32 v6, exec_lo
+// GFX12: encoding: [0x6b,0xfe,0x91,0xca,0x7e,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_lo, v255 :: v_dual_mov_b32 v6, exec_hi
+// GFX12: encoding: [0x6a,0xfe,0x91,0xca,0x7f,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0xaf123456, v255 :: v_dual_mov_b32 v6, null
+// GFX12: encoding: [0xff,0xfe,0x91,0xca,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, src_scc, v255 :: v_dual_mov_b32 v6, -1
+// GFX12: encoding: [0xfd,0xfe,0x91,0xca,0xc1,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_mov_b32 v6, 0.5
+// GFX12: encoding: [0xf0,0x06,0x90,0xca,0xf0,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, -1, v4 :: v_dual_mov_b32 v6, src_scc
+// GFX12: encoding: [0xc1,0x08,0x90,0xca,0xfd,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v6, null, v5 :: v_dual_mov_b32 v255, 0xaf123456
+// GFX12: encoding: [0x7c,0x0a,0x90,0xca,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v4, v2 :: v_dual_mul_dx9_zero_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x8e,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v1, v2 :: v_dual_mul_dx9_zero_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x8e,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v255, v2 :: v_dual_mul_dx9_zero_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x8e,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v2, v2 :: v_dual_mul_dx9_zero_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x8e,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v3, v2 :: v_dual_mul_dx9_zero_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x8e,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s105, v2 :: v_dual_mul_dx9_zero_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x8e,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s1, v2 :: v_dual_mul_dx9_zero_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x8e,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, ttmp15, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x8e,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x8e,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x8e,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, m0, v2 :: v_dual_mul_dx9_zero_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x8e,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x8e,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x8e,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0xaf123456, v2 :: v_dual_mul_dx9_zero_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x8e,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, src_scc, v2 :: v_dual_mul_dx9_zero_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x8e,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_mul_dx9_zero_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x8e,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, -1, v4 :: v_dual_mul_dx9_zero_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x8e,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v6, null, v5 :: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x8e,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v4, v2 :: v_dual_mul_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x86,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v1, v2 :: v_dual_mul_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x86,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v255, v2 :: v_dual_mul_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x86,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v2, v2 :: v_dual_mul_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x86,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v3, v2 :: v_dual_mul_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x86,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s105, v2 :: v_dual_mul_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x86,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s1, v2 :: v_dual_mul_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x86,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, ttmp15, v2 :: v_dual_mul_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x86,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_hi, v2 :: v_dual_mul_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x86,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_lo, v2 :: v_dual_mul_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x86,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, m0, v2 :: v_dual_mul_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x86,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_hi, v2 :: v_dual_mul_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x86,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_lo, v2 :: v_dual_mul_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x86,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0xaf123456, v2 :: v_dual_mul_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x86,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, src_scc, v2 :: v_dual_mul_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x86,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_mul_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x86,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, -1, v4 :: v_dual_mul_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x86,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v6, null, v5 :: v_dual_mul_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x86,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v4, v2 :: v_dual_sub_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x8a,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v1, v2 :: v_dual_sub_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x8a,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v255, v2 :: v_dual_sub_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x8a,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v2, v2 :: v_dual_sub_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x8a,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v3, v2 :: v_dual_sub_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x8a,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s105, v2 :: v_dual_sub_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x8a,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s1, v2 :: v_dual_sub_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x8a,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, ttmp15, v2 :: v_dual_sub_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x8a,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_hi, v2 :: v_dual_sub_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x8a,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_lo, v2 :: v_dual_sub_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x8a,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, m0, v2 :: v_dual_sub_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x8a,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_hi, v2 :: v_dual_sub_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x8a,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_lo, v2 :: v_dual_sub_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x8a,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0xaf123456, v2 :: v_dual_sub_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x8a,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, src_scc, v2 :: v_dual_sub_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x8a,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_sub_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x8a,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, -1, v4 :: v_dual_sub_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x8a,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v6, null, v5 :: v_dual_sub_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x8a,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v4, v2 :: v_dual_subrev_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x8c,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v1, v2 :: v_dual_subrev_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x8c,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v255, v2 :: v_dual_subrev_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x8c,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v2, v2 :: v_dual_subrev_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x8c,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, v3, v2 :: v_dual_subrev_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x8c,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s105, v2 :: v_dual_subrev_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x8c,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, s1, v2 :: v_dual_subrev_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x8c,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, ttmp15, v2 :: v_dual_subrev_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x8c,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_hi, v2 :: v_dual_subrev_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x8c,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, exec_lo, v2 :: v_dual_subrev_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x8c,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, m0, v2 :: v_dual_subrev_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x8c,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_hi, v2 :: v_dual_subrev_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x8c,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, vcc_lo, v2 :: v_dual_subrev_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x8c,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0xaf123456, v2 :: v_dual_subrev_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x8c,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, src_scc, v2 :: v_dual_subrev_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x8c,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_subrev_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x8c,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v255, -1, v4 :: v_dual_subrev_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x8c,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_max_num_f32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x8c,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v4, v2 :: v_dual_add_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xc8,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v1, v2 :: v_dual_add_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xc8,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v255, v2 :: v_dual_add_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xc8,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v2, v2 :: v_dual_add_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xc8,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v3, v2 :: v_dual_add_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xc8,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s105, v2 :: v_dual_add_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xc8,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s1, v2 :: v_dual_add_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xc8,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, ttmp15, v2 :: v_dual_add_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xc8,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_hi, v2 :: v_dual_add_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xc8,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_lo, v2 :: v_dual_add_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xc8,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, m0, v2 :: v_dual_add_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xc8,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_hi, v2 :: v_dual_add_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xc8,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_lo, v2 :: v_dual_add_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xc8,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0xaf123456, v2 :: v_dual_add_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xc8,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, src_scc, v2 :: v_dual_add_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xc8,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_add_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xc8,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, -1, v4 :: v_dual_add_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xc8,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v6, null, v5 :: v_dual_add_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xc8,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v4, v2 :: v_dual_add_nc_u32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xe0,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v1, v2 :: v_dual_add_nc_u32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xe0,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v255, v2 :: v_dual_add_nc_u32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xe0,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v2, v2 :: v_dual_add_nc_u32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xe0,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v3, v2 :: v_dual_add_nc_u32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xe0,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s105, v2 :: v_dual_add_nc_u32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xe0,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s1, v2 :: v_dual_add_nc_u32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xe0,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, ttmp15, v2 :: v_dual_add_nc_u32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xe0,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_hi, v2 :: v_dual_add_nc_u32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xe0,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_lo, v2 :: v_dual_add_nc_u32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xe0,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, m0, v2 :: v_dual_add_nc_u32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xe0,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_hi, v2 :: v_dual_add_nc_u32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xe0,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_lo, v2 :: v_dual_add_nc_u32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xe0,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0xaf123456, v2 :: v_dual_add_nc_u32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xe0,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, src_scc, v2 :: v_dual_add_nc_u32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xe0,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_add_nc_u32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xe0,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, -1, v4 :: v_dual_add_nc_u32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xe0,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v6, null, v5 :: v_dual_add_nc_u32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xe0,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v4, v2 :: v_dual_and_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xe4,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v1, v2 :: v_dual_and_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xe4,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v255, v2 :: v_dual_and_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xe4,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v2, v2 :: v_dual_and_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xe4,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v3, v2 :: v_dual_and_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xe4,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s105, v2 :: v_dual_and_b32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xe4,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s1, v2 :: v_dual_and_b32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xe4,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, ttmp15, v2 :: v_dual_and_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xe4,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_hi, v2 :: v_dual_and_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xe4,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_lo, v2 :: v_dual_and_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xe4,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, m0, v2 :: v_dual_and_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xe4,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_hi, v2 :: v_dual_and_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xe4,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_lo, v2 :: v_dual_and_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xe4,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0xaf123456, v2 :: v_dual_and_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xe4,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, src_scc, v2 :: v_dual_and_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xe4,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_and_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xe4,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, -1, v4 :: v_dual_and_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xe4,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v6, null, v5 :: v_dual_and_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xe4,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v4, v2 :: v_dual_cndmask_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xd2,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v1, v2 :: v_dual_cndmask_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xd2,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v255, v2 :: v_dual_cndmask_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xd2,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v2, v2 :: v_dual_cndmask_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xd2,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v3, v2 :: v_dual_cndmask_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xd2,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s105, v2 :: v_dual_cndmask_b32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0xd2,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s1, v2 :: v_dual_cndmask_b32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0xd2,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, ttmp15, v2 :: v_dual_cndmask_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0xd2,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_hi, v2 :: v_dual_cndmask_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xd2,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_lo, v2 :: v_dual_cndmask_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0xd2,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, m0, v2 :: v_dual_cndmask_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xd2,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_hi, v2 :: v_dual_cndmask_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0xd2,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_lo, v2 :: v_dual_cndmask_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0xd2,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0xaf123456, v2 :: v_dual_cndmask_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xd2,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, src_scc, v2 :: v_dual_cndmask_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xd2,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_cndmask_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xd2,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, -1, v4 :: v_dual_cndmask_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xd2,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v6, null, v5 :: v_dual_cndmask_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xd2,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v4, v2 :: v_dual_fmaak_f32 v6, v1, v3, 0xaf123456
+// GFX12: encoding: [0x04,0x05,0xc2,0xca,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v1, v2 :: v_dual_fmaak_f32 v6, v255, v3, 0xaf123456
+// GFX12: encoding: [0x01,0x05,0xc2,0xca,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v255, v2 :: v_dual_fmaak_f32 v6, v2, v3, 0xaf123456
+// GFX12: encoding: [0xff,0x05,0xc2,0xca,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v2, v2 :: v_dual_fmaak_f32 v6, v3, v3, 0xaf123456
+// GFX12: encoding: [0x02,0x05,0xc2,0xca,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v3, v2 :: v_dual_fmaak_f32 v6, v4, v3, 0xaf123456
+// GFX12: encoding: [0x03,0x05,0xc2,0xca,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s105, v2 :: v_dual_fmaak_f32 v6, s105, v3, 0xaf123456
+// GFX12: encoding: [0x69,0x04,0xc2,0xca,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s1, v2 :: v_dual_fmaak_f32 v6, s1, v3, 0xaf123456
+// GFX12: encoding: [0x01,0x04,0xc2,0xca,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, ttmp15, v2 :: v_dual_fmaak_f32 v6, ttmp15, v3, 0xaf123456
+// GFX12: encoding: [0x7b,0x04,0xc2,0xca,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_hi, v2 :: v_dual_fmaak_f32 v6, exec_hi, v3, 0xaf123456
+// GFX12: encoding: [0x7f,0x04,0xc2,0xca,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_lo, v2 :: v_dual_fmaak_f32 v6, exec_lo, v3, 0xaf123456
+// GFX12: encoding: [0x7e,0x04,0xc2,0xca,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, m0, v2 :: v_dual_fmaak_f32 v6, m0, v3, 0xaf123456
+// GFX12: encoding: [0x7d,0x04,0xc2,0xca,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_hi, v2 :: v_dual_fmaak_f32 v6, vcc_hi, v3, 0xaf123456
+// GFX12: encoding: [0x6b,0x04,0xc2,0xca,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_lo, v2 :: v_dual_fmaak_f32 v6, vcc_lo, v3, 0xaf123456
+// GFX12: encoding: [0x6a,0x04,0xc2,0xca,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, null, v3, 0xaf123456
+// GFX12: encoding: [0xff,0x04,0xc2,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, src_scc, v2 :: v_dual_fmaak_f32 v6, -1, v3, 0xaf123456
+// GFX12: encoding: [0xfd,0x04,0xc2,0xca,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_fmaak_f32 v6, 0.5, v2, 0xaf123456
+// GFX12: encoding: [0xf0,0x06,0xc2,0xca,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, -1, v4 :: v_dual_fmaak_f32 v6, src_scc, v5, 0xaf123456
+// GFX12: encoding: [0xc1,0x08,0xc2,0xca,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v6, null, v5 :: v_dual_fmaak_f32 v255, 0xaf123456, v4, 0xaf123456
+// GFX12: encoding: [0x7c,0x0a,0xc2,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v4, v2 :: v_dual_fmac_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xc0,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v1, v2 :: v_dual_fmac_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xc0,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v255, v2 :: v_dual_fmac_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xc0,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v2, v2 :: v_dual_fmac_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xc0,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v3, v2 :: v_dual_fmac_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xc0,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s105, v2 :: v_dual_fmac_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xc0,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s1, v2 :: v_dual_fmac_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xc0,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, ttmp15, v2 :: v_dual_fmac_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xc0,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_hi, v2 :: v_dual_fmac_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xc0,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_lo, v2 :: v_dual_fmac_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xc0,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, m0, v2 :: v_dual_fmac_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xc0,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_hi, v2 :: v_dual_fmac_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xc0,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_lo, v2 :: v_dual_fmac_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xc0,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0xaf123456, v2 :: v_dual_fmac_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xc0,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, src_scc, v2 :: v_dual_fmac_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xc0,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_fmac_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xc0,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, -1, v4 :: v_dual_fmac_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xc0,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v6, null, v5 :: v_dual_fmac_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xc0,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v4, v255 :: v_dual_fmamk_f32 v6, v1, 0xaf123456, v255
+// GFX12: encoding: [0x04,0xff,0xc5,0xca,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v1, v255 :: v_dual_fmamk_f32 v6, v255, 0xaf123456, v255
+// GFX12: encoding: [0x01,0xff,0xc5,0xca,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v255, v255 :: v_dual_fmamk_f32 v6, v2, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xff,0xc5,0xca,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v2, v255 :: v_dual_fmamk_f32 v6, v3, 0xaf123456, v255
+// GFX12: encoding: [0x02,0xff,0xc5,0xca,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v3, v255 :: v_dual_fmamk_f32 v6, v4, 0xaf123456, v255
+// GFX12: encoding: [0x03,0xff,0xc5,0xca,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s105, v255 :: v_dual_fmamk_f32 v6, s105, 0xaf123456, v255
+// GFX12: encoding: [0x69,0xfe,0xc5,0xca,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s1, v255 :: v_dual_fmamk_f32 v6, s1, 0xaf123456, v255
+// GFX12: encoding: [0x01,0xfe,0xc5,0xca,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, ttmp15, v255 :: v_dual_fmamk_f32 v6, ttmp15, 0xaf123456, v255
+// GFX12: encoding: [0x7b,0xfe,0xc5,0xca,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_hi, v255 :: v_dual_fmamk_f32 v6, exec_hi, 0xaf123456, v255
+// GFX12: encoding: [0x7f,0xfe,0xc5,0xca,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_lo, v255 :: v_dual_fmamk_f32 v6, exec_lo, 0xaf123456, v255
+// GFX12: encoding: [0x7e,0xfe,0xc5,0xca,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, m0, v255 :: v_dual_fmamk_f32 v6, m0, 0xaf123456, v255
+// GFX12: encoding: [0x7d,0xfe,0xc5,0xca,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_hi, v255 :: v_dual_fmamk_f32 v6, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x6b,0xfe,0xc5,0xca,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_lo, v255 :: v_dual_fmamk_f32 v6, vcc_lo, 0xaf123456, v255
+// GFX12: encoding: [0x6a,0xfe,0xc5,0xca,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, null, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xc5,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, src_scc, v255 :: v_dual_fmamk_f32 v6, -1, 0xaf123456, v255
+// GFX12: encoding: [0xfd,0xfe,0xc5,0xca,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_fmamk_f32 v6, 0.5, 0xaf123456, v255
+// GFX12: encoding: [0xf0,0x06,0xc4,0xca,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, -1, v4 :: v_dual_fmamk_f32 v6, src_scc, 0xaf123456, v255
+// GFX12: encoding: [0xc1,0x08,0xc4,0xca,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v6, null, v5 :: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xc4,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v4, v2 :: v_dual_lshlrev_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xe2,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v1, v2 :: v_dual_lshlrev_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xe2,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v255, v2 :: v_dual_lshlrev_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xe2,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v2, v2 :: v_dual_lshlrev_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xe2,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v3, v2 :: v_dual_lshlrev_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xe2,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s105, v2 :: v_dual_lshlrev_b32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xe2,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s1, v2 :: v_dual_lshlrev_b32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xe2,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, ttmp15, v2 :: v_dual_lshlrev_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xe2,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_hi, v2 :: v_dual_lshlrev_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xe2,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_lo, v2 :: v_dual_lshlrev_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xe2,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, m0, v2 :: v_dual_lshlrev_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xe2,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_hi, v2 :: v_dual_lshlrev_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xe2,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_lo, v2 :: v_dual_lshlrev_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xe2,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0xaf123456, v2 :: v_dual_lshlrev_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xe2,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, src_scc, v2 :: v_dual_lshlrev_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xe2,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_lshlrev_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xe2,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, -1, v4 :: v_dual_lshlrev_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xe2,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v6, null, v5 :: v_dual_lshlrev_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xe2,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v4, v2 :: v_dual_max_num_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xd4,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v1, v2 :: v_dual_max_num_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xd4,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v255, v2 :: v_dual_max_num_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xd4,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v2, v2 :: v_dual_max_num_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xd4,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v3, v2 :: v_dual_max_num_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xd4,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s105, v2 :: v_dual_max_num_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xd4,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s1, v2 :: v_dual_max_num_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xd4,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, ttmp15, v2 :: v_dual_max_num_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xd4,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_hi, v2 :: v_dual_max_num_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xd4,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_lo, v2 :: v_dual_max_num_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xd4,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, m0, v2 :: v_dual_max_num_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xd4,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_hi, v2 :: v_dual_max_num_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xd4,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_lo, v2 :: v_dual_max_num_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xd4,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0xaf123456, v2 :: v_dual_max_num_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xd4,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, src_scc, v2 :: v_dual_max_num_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xd4,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_max_num_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xd4,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, -1, v4 :: v_dual_max_num_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xd4,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v6, null, v5 :: v_dual_max_num_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xd4,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v4, v2 :: v_dual_min_num_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xd6,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v1, v2 :: v_dual_min_num_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xd6,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v255, v2 :: v_dual_min_num_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xd6,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v2, v2 :: v_dual_min_num_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xd6,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v3, v2 :: v_dual_min_num_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xd6,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s105, v2 :: v_dual_min_num_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xd6,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s1, v2 :: v_dual_min_num_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xd6,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, ttmp15, v2 :: v_dual_min_num_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xd6,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_hi, v2 :: v_dual_min_num_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xd6,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_lo, v2 :: v_dual_min_num_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xd6,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, m0, v2 :: v_dual_min_num_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xd6,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_hi, v2 :: v_dual_min_num_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xd6,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_lo, v2 :: v_dual_min_num_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xd6,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0xaf123456, v2 :: v_dual_min_num_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xd6,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, src_scc, v2 :: v_dual_min_num_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xd6,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_min_num_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xd6,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, -1, v4 :: v_dual_min_num_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xd6,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v6, null, v5 :: v_dual_min_num_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xd6,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v4, v255 :: v_dual_mov_b32 v6, v1
+// GFX12: encoding: [0x04,0xff,0xd1,0xca,0x01,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v1, v255 :: v_dual_mov_b32 v6, v255
+// GFX12: encoding: [0x01,0xff,0xd1,0xca,0xff,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v255, v255 :: v_dual_mov_b32 v6, v2
+// GFX12: encoding: [0xff,0xff,0xd1,0xca,0x02,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v2, v255 :: v_dual_mov_b32 v6, v3
+// GFX12: encoding: [0x02,0xff,0xd1,0xca,0x03,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v3, v255 :: v_dual_mov_b32 v6, v4
+// GFX12: encoding: [0x03,0xff,0xd1,0xca,0x04,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s105, v255 :: v_dual_mov_b32 v6, s1
+// GFX12: encoding: [0x69,0xfe,0xd1,0xca,0x01,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s1, v255 :: v_dual_mov_b32 v6, s105
+// GFX12: encoding: [0x01,0xfe,0xd1,0xca,0x69,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, ttmp15, v255 :: v_dual_mov_b32 v6, vcc_lo
+// GFX12: encoding: [0x7b,0xfe,0xd1,0xca,0x6a,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_hi, v255 :: v_dual_mov_b32 v6, vcc_hi
+// GFX12: encoding: [0x7f,0xfe,0xd1,0xca,0x6b,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_lo, v255 :: v_dual_mov_b32 v6, ttmp15
+// GFX12: encoding: [0x7e,0xfe,0xd1,0xca,0x7b,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, m0, v255 :: v_dual_mov_b32 v6, m0
+// GFX12: encoding: [0x7d,0xfe,0xd1,0xca,0x7d,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_hi, v255 :: v_dual_mov_b32 v6, exec_lo
+// GFX12: encoding: [0x6b,0xfe,0xd1,0xca,0x7e,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_lo, v255 :: v_dual_mov_b32 v6, exec_hi
+// GFX12: encoding: [0x6a,0xfe,0xd1,0xca,0x7f,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0xaf123456, v255 :: v_dual_mov_b32 v6, null
+// GFX12: encoding: [0xff,0xfe,0xd1,0xca,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, src_scc, v255 :: v_dual_mov_b32 v6, -1
+// GFX12: encoding: [0xfd,0xfe,0xd1,0xca,0xc1,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_mov_b32 v6, 0.5
+// GFX12: encoding: [0xf0,0x06,0xd0,0xca,0xf0,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, -1, v4 :: v_dual_mov_b32 v6, src_scc
+// GFX12: encoding: [0xc1,0x08,0xd0,0xca,0xfd,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v6, null, v5 :: v_dual_mov_b32 v255, 0xaf123456
+// GFX12: encoding: [0x7c,0x0a,0xd0,0xca,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v4, v2 :: v_dual_mul_dx9_zero_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xce,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v1, v2 :: v_dual_mul_dx9_zero_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xce,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v255, v2 :: v_dual_mul_dx9_zero_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xce,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v2, v2 :: v_dual_mul_dx9_zero_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xce,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v3, v2 :: v_dual_mul_dx9_zero_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xce,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s105, v2 :: v_dual_mul_dx9_zero_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xce,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s1, v2 :: v_dual_mul_dx9_zero_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xce,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, ttmp15, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xce,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xce,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xce,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, m0, v2 :: v_dual_mul_dx9_zero_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xce,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xce,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xce,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0xaf123456, v2 :: v_dual_mul_dx9_zero_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xce,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, src_scc, v2 :: v_dual_mul_dx9_zero_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xce,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_mul_dx9_zero_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xce,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, -1, v4 :: v_dual_mul_dx9_zero_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xce,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v6, null, v5 :: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xce,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v4, v2 :: v_dual_mul_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xc6,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v1, v2 :: v_dual_mul_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xc6,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v255, v2 :: v_dual_mul_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xc6,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v2, v2 :: v_dual_mul_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xc6,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v3, v2 :: v_dual_mul_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xc6,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s105, v2 :: v_dual_mul_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xc6,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s1, v2 :: v_dual_mul_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xc6,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, ttmp15, v2 :: v_dual_mul_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xc6,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_hi, v2 :: v_dual_mul_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xc6,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_lo, v2 :: v_dual_mul_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xc6,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, m0, v2 :: v_dual_mul_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xc6,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_hi, v2 :: v_dual_mul_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xc6,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_lo, v2 :: v_dual_mul_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xc6,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0xaf123456, v2 :: v_dual_mul_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xc6,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, src_scc, v2 :: v_dual_mul_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xc6,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_mul_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xc6,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, -1, v4 :: v_dual_mul_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xc6,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v6, null, v5 :: v_dual_mul_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xc6,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v4, v2 :: v_dual_sub_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xca,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v1, v2 :: v_dual_sub_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xca,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v255, v2 :: v_dual_sub_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xca,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v2, v2 :: v_dual_sub_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xca,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v3, v2 :: v_dual_sub_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xca,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s105, v2 :: v_dual_sub_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xca,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s1, v2 :: v_dual_sub_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xca,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, ttmp15, v2 :: v_dual_sub_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xca,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_hi, v2 :: v_dual_sub_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xca,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_lo, v2 :: v_dual_sub_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xca,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, m0, v2 :: v_dual_sub_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xca,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_hi, v2 :: v_dual_sub_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xca,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_lo, v2 :: v_dual_sub_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xca,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0xaf123456, v2 :: v_dual_sub_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xca,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, src_scc, v2 :: v_dual_sub_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xca,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_sub_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xca,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, -1, v4 :: v_dual_sub_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xca,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v6, null, v5 :: v_dual_sub_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xca,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v4, v2 :: v_dual_subrev_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xcc,0xca,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v1, v2 :: v_dual_subrev_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xcc,0xca,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v255, v2 :: v_dual_subrev_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xcc,0xca,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v2, v2 :: v_dual_subrev_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xcc,0xca,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, v3, v2 :: v_dual_subrev_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xcc,0xca,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s105, v2 :: v_dual_subrev_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xcc,0xca,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, s1, v2 :: v_dual_subrev_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xcc,0xca,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, ttmp15, v2 :: v_dual_subrev_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xcc,0xca,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_hi, v2 :: v_dual_subrev_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xcc,0xca,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, exec_lo, v2 :: v_dual_subrev_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xcc,0xca,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, m0, v2 :: v_dual_subrev_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xcc,0xca,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_hi, v2 :: v_dual_subrev_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xcc,0xca,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, vcc_lo, v2 :: v_dual_subrev_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xcc,0xca,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0xaf123456, v2 :: v_dual_subrev_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xcc,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, src_scc, v2 :: v_dual_subrev_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xcc,0xca,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_subrev_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xcc,0xca,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v255, -1, v4 :: v_dual_subrev_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xcc,0xca,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_min_num_f32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xcc,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v4 :: v_dual_add_f32 v6, v1, v255
+// GFX12: encoding: [0x04,0x01,0x08,0xca,0x01,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v1 :: v_dual_add_f32 v6, v255, v255
+// GFX12: encoding: [0x01,0x01,0x08,0xca,0xff,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v255 :: v_dual_add_f32 v6, v2, v255
+// GFX12: encoding: [0xff,0x01,0x08,0xca,0x02,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v2 :: v_dual_add_f32 v6, v3, v255
+// GFX12: encoding: [0x02,0x01,0x08,0xca,0x03,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v3 :: v_dual_add_f32 v6, v4, v255
+// GFX12: encoding: [0x03,0x01,0x08,0xca,0x04,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s105 :: v_dual_add_f32 v6, s1, v255
+// GFX12: encoding: [0x69,0x00,0x08,0xca,0x01,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s1 :: v_dual_add_f32 v6, s105, v255
+// GFX12: encoding: [0x01,0x00,0x08,0xca,0x69,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, ttmp15 :: v_dual_add_f32 v6, vcc_lo, v255
+// GFX12: encoding: [0x7b,0x00,0x08,0xca,0x6a,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_hi :: v_dual_add_f32 v6, vcc_hi, v255
+// GFX12: encoding: [0x7f,0x00,0x08,0xca,0x6b,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_lo :: v_dual_add_f32 v6, ttmp15, v255
+// GFX12: encoding: [0x7e,0x00,0x08,0xca,0x7b,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, m0 :: v_dual_add_f32 v6, m0, v255
+// GFX12: encoding: [0x7d,0x00,0x08,0xca,0x7d,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_hi :: v_dual_add_f32 v6, exec_lo, v255
+// GFX12: encoding: [0x6b,0x00,0x08,0xca,0x7e,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_lo :: v_dual_add_f32 v6, exec_hi, v255
+// GFX12: encoding: [0x6a,0x00,0x08,0xca,0x7f,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0xaf123456 :: v_dual_add_f32 v6, null, v255
+// GFX12: encoding: [0xff,0x00,0x08,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, src_scc :: v_dual_add_f32 v6, -1, v255
+// GFX12: encoding: [0xfd,0x00,0x08,0xca,0xc1,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0.5 :: v_dual_add_f32 v6, 0.5, v3
+// GFX12: encoding: [0xf0,0x00,0x08,0xca,0xf0,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, -1 :: v_dual_add_f32 v6, src_scc, v4
+// GFX12: encoding: [0xc1,0x00,0x08,0xca,0xfd,0x08,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v6, null :: v_dual_add_f32 v255, 0xaf123456, v5
+// GFX12: encoding: [0x7c,0x00,0x08,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v4 :: v_dual_add_nc_u32 v6, v1, v255
+// GFX12: encoding: [0x04,0x01,0x20,0xca,0x01,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v1 :: v_dual_add_nc_u32 v6, v255, v255
+// GFX12: encoding: [0x01,0x01,0x20,0xca,0xff,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v255 :: v_dual_add_nc_u32 v6, v2, v255
+// GFX12: encoding: [0xff,0x01,0x20,0xca,0x02,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v2 :: v_dual_add_nc_u32 v6, v3, v255
+// GFX12: encoding: [0x02,0x01,0x20,0xca,0x03,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v3 :: v_dual_add_nc_u32 v6, v4, v255
+// GFX12: encoding: [0x03,0x01,0x20,0xca,0x04,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s105 :: v_dual_add_nc_u32 v6, s1, v255
+// GFX12: encoding: [0x69,0x00,0x20,0xca,0x01,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s1 :: v_dual_add_nc_u32 v6, s105, v255
+// GFX12: encoding: [0x01,0x00,0x20,0xca,0x69,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, ttmp15 :: v_dual_add_nc_u32 v6, vcc_lo, v255
+// GFX12: encoding: [0x7b,0x00,0x20,0xca,0x6a,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_hi :: v_dual_add_nc_u32 v6, vcc_hi, v255
+// GFX12: encoding: [0x7f,0x00,0x20,0xca,0x6b,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_lo :: v_dual_add_nc_u32 v6, ttmp15, v255
+// GFX12: encoding: [0x7e,0x00,0x20,0xca,0x7b,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, m0 :: v_dual_add_nc_u32 v6, m0, v255
+// GFX12: encoding: [0x7d,0x00,0x20,0xca,0x7d,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_hi :: v_dual_add_nc_u32 v6, exec_lo, v255
+// GFX12: encoding: [0x6b,0x00,0x20,0xca,0x7e,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_lo :: v_dual_add_nc_u32 v6, exec_hi, v255
+// GFX12: encoding: [0x6a,0x00,0x20,0xca,0x7f,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0xaf123456 :: v_dual_add_nc_u32 v6, null, v255
+// GFX12: encoding: [0xff,0x00,0x20,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, src_scc :: v_dual_add_nc_u32 v6, -1, v255
+// GFX12: encoding: [0xfd,0x00,0x20,0xca,0xc1,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0.5 :: v_dual_add_nc_u32 v6, 0.5, v3
+// GFX12: encoding: [0xf0,0x00,0x20,0xca,0xf0,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, -1 :: v_dual_add_nc_u32 v6, src_scc, v4
+// GFX12: encoding: [0xc1,0x00,0x20,0xca,0xfd,0x08,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v6, null :: v_dual_add_nc_u32 v255, 0xaf123456, v5
+// GFX12: encoding: [0x7c,0x00,0x20,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v4 :: v_dual_and_b32 v6, v1, v255
+// GFX12: encoding: [0x04,0x01,0x24,0xca,0x01,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v1 :: v_dual_and_b32 v6, v255, v255
+// GFX12: encoding: [0x01,0x01,0x24,0xca,0xff,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v255 :: v_dual_and_b32 v6, v2, v255
+// GFX12: encoding: [0xff,0x01,0x24,0xca,0x02,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v2 :: v_dual_and_b32 v6, v3, v255
+// GFX12: encoding: [0x02,0x01,0x24,0xca,0x03,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v3 :: v_dual_and_b32 v6, v4, v255
+// GFX12: encoding: [0x03,0x01,0x24,0xca,0x04,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s105 :: v_dual_and_b32 v6, s1, v255
+// GFX12: encoding: [0x69,0x00,0x24,0xca,0x01,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s1 :: v_dual_and_b32 v6, s105, v255
+// GFX12: encoding: [0x01,0x00,0x24,0xca,0x69,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, ttmp15 :: v_dual_and_b32 v6, vcc_lo, v255
+// GFX12: encoding: [0x7b,0x00,0x24,0xca,0x6a,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_hi :: v_dual_and_b32 v6, vcc_hi, v255
+// GFX12: encoding: [0x7f,0x00,0x24,0xca,0x6b,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_lo :: v_dual_and_b32 v6, ttmp15, v255
+// GFX12: encoding: [0x7e,0x00,0x24,0xca,0x7b,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, m0 :: v_dual_and_b32 v6, m0, v255
+// GFX12: encoding: [0x7d,0x00,0x24,0xca,0x7d,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_hi :: v_dual_and_b32 v6, exec_lo, v255
+// GFX12: encoding: [0x6b,0x00,0x24,0xca,0x7e,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_lo :: v_dual_and_b32 v6, exec_hi, v255
+// GFX12: encoding: [0x6a,0x00,0x24,0xca,0x7f,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0xaf123456 :: v_dual_and_b32 v6, null, v255
+// GFX12: encoding: [0xff,0x00,0x24,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, src_scc :: v_dual_and_b32 v6, -1, v255
+// GFX12: encoding: [0xfd,0x00,0x24,0xca,0xc1,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0.5 :: v_dual_and_b32 v6, 0.5, v3
+// GFX12: encoding: [0xf0,0x00,0x24,0xca,0xf0,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, -1 :: v_dual_and_b32 v6, src_scc, v4
+// GFX12: encoding: [0xc1,0x00,0x24,0xca,0xfd,0x08,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v6, null :: v_dual_and_b32 v255, 0xaf123456, v5
+// GFX12: encoding: [0x7c,0x00,0x24,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v4 :: v_dual_cndmask_b32 v6, v1, v255
+// GFX12: encoding: [0x04,0x01,0x12,0xca,0x01,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v1 :: v_dual_cndmask_b32 v6, v255, v255
+// GFX12: encoding: [0x01,0x01,0x12,0xca,0xff,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v255 :: v_dual_cndmask_b32 v6, v2, v255
+// GFX12: encoding: [0xff,0x01,0x12,0xca,0x02,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v2 :: v_dual_cndmask_b32 v6, v3, v255
+// GFX12: encoding: [0x02,0x01,0x12,0xca,0x03,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v3 :: v_dual_cndmask_b32 v6, v4, v255
+// GFX12: encoding: [0x03,0x01,0x12,0xca,0x04,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s105 :: v_dual_cndmask_b32 v6, s105, v255
+// GFX12: encoding: [0x69,0x00,0x12,0xca,0x69,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s1 :: v_dual_cndmask_b32 v6, s1, v255
+// GFX12: encoding: [0x01,0x00,0x12,0xca,0x01,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, ttmp15 :: v_dual_cndmask_b32 v6, ttmp15, v255
+// GFX12: encoding: [0x7b,0x00,0x12,0xca,0x7b,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_hi :: v_dual_cndmask_b32 v6, exec_hi, v255
+// GFX12: encoding: [0x7f,0x00,0x12,0xca,0x7f,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_lo :: v_dual_cndmask_b32 v6, exec_lo, v255
+// GFX12: encoding: [0x7e,0x00,0x12,0xca,0x7e,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, m0 :: v_dual_cndmask_b32 v6, m0, v255
+// GFX12: encoding: [0x7d,0x00,0x12,0xca,0x7d,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_hi :: v_dual_cndmask_b32 v6, vcc_hi, v255
+// GFX12: encoding: [0x6b,0x00,0x12,0xca,0x6b,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_lo :: v_dual_cndmask_b32 v6, vcc_lo, v255
+// GFX12: encoding: [0x6a,0x00,0x12,0xca,0x6a,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0xaf123456 :: v_dual_cndmask_b32 v6, null, v255
+// GFX12: encoding: [0xff,0x00,0x12,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, src_scc :: v_dual_cndmask_b32 v6, -1, v255
+// GFX12: encoding: [0xfd,0x00,0x12,0xca,0xc1,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0.5 :: v_dual_cndmask_b32 v6, 0.5, v3
+// GFX12: encoding: [0xf0,0x00,0x12,0xca,0xf0,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, -1 :: v_dual_cndmask_b32 v6, src_scc, v4
+// GFX12: encoding: [0xc1,0x00,0x12,0xca,0xfd,0x08,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v6, null :: v_dual_cndmask_b32 v255, 0xaf123456, v5
+// GFX12: encoding: [0x7c,0x00,0x12,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v4 :: v_dual_fmaak_f32 v6, v1, v255, 0xaf123456
+// GFX12: encoding: [0x04,0x01,0x02,0xca,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v1 :: v_dual_fmaak_f32 v6, v255, v255, 0xaf123456
+// GFX12: encoding: [0x01,0x01,0x02,0xca,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v255 :: v_dual_fmaak_f32 v6, v2, v255, 0xaf123456
+// GFX12: encoding: [0xff,0x01,0x02,0xca,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v2 :: v_dual_fmaak_f32 v6, v3, v255, 0xaf123456
+// GFX12: encoding: [0x02,0x01,0x02,0xca,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v3 :: v_dual_fmaak_f32 v6, v4, v255, 0xaf123456
+// GFX12: encoding: [0x03,0x01,0x02,0xca,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s105 :: v_dual_fmaak_f32 v6, s105, v255, 0xaf123456
+// GFX12: encoding: [0x69,0x00,0x02,0xca,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s1 :: v_dual_fmaak_f32 v6, s1, v255, 0xaf123456
+// GFX12: encoding: [0x01,0x00,0x02,0xca,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, ttmp15 :: v_dual_fmaak_f32 v6, ttmp15, v255, 0xaf123456
+// GFX12: encoding: [0x7b,0x00,0x02,0xca,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_hi :: v_dual_fmaak_f32 v6, exec_hi, v255, 0xaf123456
+// GFX12: encoding: [0x7f,0x00,0x02,0xca,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_lo :: v_dual_fmaak_f32 v6, exec_lo, v255, 0xaf123456
+// GFX12: encoding: [0x7e,0x00,0x02,0xca,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, m0 :: v_dual_fmaak_f32 v6, m0, v255, 0xaf123456
+// GFX12: encoding: [0x7d,0x00,0x02,0xca,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_hi :: v_dual_fmaak_f32 v6, vcc_hi, v255, 0xaf123456
+// GFX12: encoding: [0x6b,0x00,0x02,0xca,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_lo :: v_dual_fmaak_f32 v6, vcc_lo, v255, 0xaf123456
+// GFX12: encoding: [0x6a,0x00,0x02,0xca,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0xaf123456 :: v_dual_fmaak_f32 v6, null, v255, 0xaf123456
+// GFX12: encoding: [0xff,0x00,0x02,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, src_scc :: v_dual_fmaak_f32 v6, -1, v255, 0xaf123456
+// GFX12: encoding: [0xfd,0x00,0x02,0xca,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0.5 :: v_dual_fmaak_f32 v6, 0.5, v3, 0xaf123456
+// GFX12: encoding: [0xf0,0x00,0x02,0xca,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, -1 :: v_dual_fmaak_f32 v6, src_scc, v4, 0xaf123456
+// GFX12: encoding: [0xc1,0x00,0x02,0xca,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v6, null :: v_dual_fmaak_f32 v255, 0xaf123456, v5, 0xaf123456
+// GFX12: encoding: [0x7c,0x00,0x02,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v4 :: v_dual_fmac_f32 v6, v1, v255
+// GFX12: encoding: [0x04,0x01,0x00,0xca,0x01,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v1 :: v_dual_fmac_f32 v6, v255, v255
+// GFX12: encoding: [0x01,0x01,0x00,0xca,0xff,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v255 :: v_dual_fmac_f32 v6, v2, v255
+// GFX12: encoding: [0xff,0x01,0x00,0xca,0x02,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v2 :: v_dual_fmac_f32 v6, v3, v255
+// GFX12: encoding: [0x02,0x01,0x00,0xca,0x03,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v3 :: v_dual_fmac_f32 v6, v4, v255
+// GFX12: encoding: [0x03,0x01,0x00,0xca,0x04,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s105 :: v_dual_fmac_f32 v6, s1, v255
+// GFX12: encoding: [0x69,0x00,0x00,0xca,0x01,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s1 :: v_dual_fmac_f32 v6, s105, v255
+// GFX12: encoding: [0x01,0x00,0x00,0xca,0x69,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, ttmp15 :: v_dual_fmac_f32 v6, vcc_lo, v255
+// GFX12: encoding: [0x7b,0x00,0x00,0xca,0x6a,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_hi :: v_dual_fmac_f32 v6, vcc_hi, v255
+// GFX12: encoding: [0x7f,0x00,0x00,0xca,0x6b,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_lo :: v_dual_fmac_f32 v6, ttmp15, v255
+// GFX12: encoding: [0x7e,0x00,0x00,0xca,0x7b,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, m0 :: v_dual_fmac_f32 v6, m0, v255
+// GFX12: encoding: [0x7d,0x00,0x00,0xca,0x7d,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_hi :: v_dual_fmac_f32 v6, exec_lo, v255
+// GFX12: encoding: [0x6b,0x00,0x00,0xca,0x7e,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_lo :: v_dual_fmac_f32 v6, exec_hi, v255
+// GFX12: encoding: [0x6a,0x00,0x00,0xca,0x7f,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0xaf123456 :: v_dual_fmac_f32 v6, null, v255
+// GFX12: encoding: [0xff,0x00,0x00,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, src_scc :: v_dual_fmac_f32 v6, -1, v255
+// GFX12: encoding: [0xfd,0x00,0x00,0xca,0xc1,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0.5 :: v_dual_fmac_f32 v6, 0.5, v3
+// GFX12: encoding: [0xf0,0x00,0x00,0xca,0xf0,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, -1 :: v_dual_fmac_f32 v6, src_scc, v4
+// GFX12: encoding: [0xc1,0x00,0x00,0xca,0xfd,0x08,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v6, null :: v_dual_fmac_f32 v255, 0xaf123456, v5
+// GFX12: encoding: [0x7c,0x00,0x00,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v4 :: v_dual_fmamk_f32 v6, v1, 0xaf123456, v255
+// GFX12: encoding: [0x04,0x01,0x04,0xca,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v1 :: v_dual_fmamk_f32 v6, v255, 0xaf123456, v255
+// GFX12: encoding: [0x01,0x01,0x04,0xca,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v255 :: v_dual_fmamk_f32 v6, v2, 0xaf123456, v255
+// GFX12: encoding: [0xff,0x01,0x04,0xca,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v2 :: v_dual_fmamk_f32 v6, v3, 0xaf123456, v255
+// GFX12: encoding: [0x02,0x01,0x04,0xca,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v3 :: v_dual_fmamk_f32 v6, v4, 0xaf123456, v255
+// GFX12: encoding: [0x03,0x01,0x04,0xca,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s105 :: v_dual_fmamk_f32 v6, s105, 0xaf123456, v255
+// GFX12: encoding: [0x69,0x00,0x04,0xca,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s1 :: v_dual_fmamk_f32 v6, s1, 0xaf123456, v255
+// GFX12: encoding: [0x01,0x00,0x04,0xca,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, ttmp15 :: v_dual_fmamk_f32 v6, ttmp15, 0xaf123456, v255
+// GFX12: encoding: [0x7b,0x00,0x04,0xca,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_hi :: v_dual_fmamk_f32 v6, exec_hi, 0xaf123456, v255
+// GFX12: encoding: [0x7f,0x00,0x04,0xca,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_lo :: v_dual_fmamk_f32 v6, exec_lo, 0xaf123456, v255
+// GFX12: encoding: [0x7e,0x00,0x04,0xca,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, m0 :: v_dual_fmamk_f32 v6, m0, 0xaf123456, v255
+// GFX12: encoding: [0x7d,0x00,0x04,0xca,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_hi :: v_dual_fmamk_f32 v6, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x6b,0x00,0x04,0xca,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_lo :: v_dual_fmamk_f32 v6, vcc_lo, 0xaf123456, v255
+// GFX12: encoding: [0x6a,0x00,0x04,0xca,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0xaf123456 :: v_dual_fmamk_f32 v6, null, 0xaf123456, v255
+// GFX12: encoding: [0xff,0x00,0x04,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, src_scc :: v_dual_fmamk_f32 v6, -1, 0xaf123456, v255
+// GFX12: encoding: [0xfd,0x00,0x04,0xca,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0.5 :: v_dual_fmamk_f32 v6, 0.5, 0xaf123456, v255
+// GFX12: encoding: [0xf0,0x00,0x04,0xca,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, -1 :: v_dual_fmamk_f32 v6, src_scc, 0xaf123456, v255
+// GFX12: encoding: [0xc1,0x00,0x04,0xca,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v6, null :: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x00,0x04,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v4 :: v_dual_lshlrev_b32 v6, v1, v255
+// GFX12: encoding: [0x04,0x01,0x22,0xca,0x01,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v1 :: v_dual_lshlrev_b32 v6, v255, v255
+// GFX12: encoding: [0x01,0x01,0x22,0xca,0xff,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v255 :: v_dual_lshlrev_b32 v6, v2, v255
+// GFX12: encoding: [0xff,0x01,0x22,0xca,0x02,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v2 :: v_dual_lshlrev_b32 v6, v3, v255
+// GFX12: encoding: [0x02,0x01,0x22,0xca,0x03,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v3 :: v_dual_lshlrev_b32 v6, v4, v255
+// GFX12: encoding: [0x03,0x01,0x22,0xca,0x04,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s105 :: v_dual_lshlrev_b32 v6, s1, v255
+// GFX12: encoding: [0x69,0x00,0x22,0xca,0x01,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s1 :: v_dual_lshlrev_b32 v6, s105, v255
+// GFX12: encoding: [0x01,0x00,0x22,0xca,0x69,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, ttmp15 :: v_dual_lshlrev_b32 v6, vcc_lo, v255
+// GFX12: encoding: [0x7b,0x00,0x22,0xca,0x6a,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_hi :: v_dual_lshlrev_b32 v6, vcc_hi, v255
+// GFX12: encoding: [0x7f,0x00,0x22,0xca,0x6b,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_lo :: v_dual_lshlrev_b32 v6, ttmp15, v255
+// GFX12: encoding: [0x7e,0x00,0x22,0xca,0x7b,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, m0 :: v_dual_lshlrev_b32 v6, m0, v255
+// GFX12: encoding: [0x7d,0x00,0x22,0xca,0x7d,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_hi :: v_dual_lshlrev_b32 v6, exec_lo, v255
+// GFX12: encoding: [0x6b,0x00,0x22,0xca,0x7e,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_lo :: v_dual_lshlrev_b32 v6, exec_hi, v255
+// GFX12: encoding: [0x6a,0x00,0x22,0xca,0x7f,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0xaf123456 :: v_dual_lshlrev_b32 v6, null, v255
+// GFX12: encoding: [0xff,0x00,0x22,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, src_scc :: v_dual_lshlrev_b32 v6, -1, v255
+// GFX12: encoding: [0xfd,0x00,0x22,0xca,0xc1,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0.5 :: v_dual_lshlrev_b32 v6, 0.5, v3
+// GFX12: encoding: [0xf0,0x00,0x22,0xca,0xf0,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, -1 :: v_dual_lshlrev_b32 v6, src_scc, v4
+// GFX12: encoding: [0xc1,0x00,0x22,0xca,0xfd,0x08,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v6, null :: v_dual_lshlrev_b32 v255, 0xaf123456, v5
+// GFX12: encoding: [0x7c,0x00,0x22,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v4 :: v_dual_max_num_f32 v6, v1, v255
+// GFX12: encoding: [0x04,0x01,0x14,0xca,0x01,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v1 :: v_dual_max_num_f32 v6, v255, v255
+// GFX12: encoding: [0x01,0x01,0x14,0xca,0xff,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v255 :: v_dual_max_num_f32 v6, v2, v255
+// GFX12: encoding: [0xff,0x01,0x14,0xca,0x02,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v2 :: v_dual_max_num_f32 v6, v3, v255
+// GFX12: encoding: [0x02,0x01,0x14,0xca,0x03,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v3 :: v_dual_max_num_f32 v6, v4, v255
+// GFX12: encoding: [0x03,0x01,0x14,0xca,0x04,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s105 :: v_dual_max_num_f32 v6, s1, v255
+// GFX12: encoding: [0x69,0x00,0x14,0xca,0x01,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s1 :: v_dual_max_num_f32 v6, s105, v255
+// GFX12: encoding: [0x01,0x00,0x14,0xca,0x69,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, ttmp15 :: v_dual_max_num_f32 v6, vcc_lo, v255
+// GFX12: encoding: [0x7b,0x00,0x14,0xca,0x6a,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_hi :: v_dual_max_num_f32 v6, vcc_hi, v255
+// GFX12: encoding: [0x7f,0x00,0x14,0xca,0x6b,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_lo :: v_dual_max_num_f32 v6, ttmp15, v255
+// GFX12: encoding: [0x7e,0x00,0x14,0xca,0x7b,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, m0 :: v_dual_max_num_f32 v6, m0, v255
+// GFX12: encoding: [0x7d,0x00,0x14,0xca,0x7d,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_hi :: v_dual_max_num_f32 v6, exec_lo, v255
+// GFX12: encoding: [0x6b,0x00,0x14,0xca,0x7e,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_lo :: v_dual_max_num_f32 v6, exec_hi, v255
+// GFX12: encoding: [0x6a,0x00,0x14,0xca,0x7f,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0xaf123456 :: v_dual_max_num_f32 v6, null, v255
+// GFX12: encoding: [0xff,0x00,0x14,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, src_scc :: v_dual_max_num_f32 v6, -1, v255
+// GFX12: encoding: [0xfd,0x00,0x14,0xca,0xc1,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0.5 :: v_dual_max_num_f32 v6, 0.5, v3
+// GFX12: encoding: [0xf0,0x00,0x14,0xca,0xf0,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, -1 :: v_dual_max_num_f32 v6, src_scc, v4
+// GFX12: encoding: [0xc1,0x00,0x14,0xca,0xfd,0x08,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v6, null :: v_dual_max_num_f32 v255, 0xaf123456, v5
+// GFX12: encoding: [0x7c,0x00,0x14,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v4 :: v_dual_min_num_f32 v6, v1, v255
+// GFX12: encoding: [0x04,0x01,0x16,0xca,0x01,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v1 :: v_dual_min_num_f32 v6, v255, v255
+// GFX12: encoding: [0x01,0x01,0x16,0xca,0xff,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v255 :: v_dual_min_num_f32 v6, v2, v255
+// GFX12: encoding: [0xff,0x01,0x16,0xca,0x02,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v2 :: v_dual_min_num_f32 v6, v3, v255
+// GFX12: encoding: [0x02,0x01,0x16,0xca,0x03,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v3 :: v_dual_min_num_f32 v6, v4, v255
+// GFX12: encoding: [0x03,0x01,0x16,0xca,0x04,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s105 :: v_dual_min_num_f32 v6, s1, v255
+// GFX12: encoding: [0x69,0x00,0x16,0xca,0x01,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s1 :: v_dual_min_num_f32 v6, s105, v255
+// GFX12: encoding: [0x01,0x00,0x16,0xca,0x69,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, ttmp15 :: v_dual_min_num_f32 v6, vcc_lo, v255
+// GFX12: encoding: [0x7b,0x00,0x16,0xca,0x6a,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_hi :: v_dual_min_num_f32 v6, vcc_hi, v255
+// GFX12: encoding: [0x7f,0x00,0x16,0xca,0x6b,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_lo :: v_dual_min_num_f32 v6, ttmp15, v255
+// GFX12: encoding: [0x7e,0x00,0x16,0xca,0x7b,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, m0 :: v_dual_min_num_f32 v6, m0, v255
+// GFX12: encoding: [0x7d,0x00,0x16,0xca,0x7d,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_hi :: v_dual_min_num_f32 v6, exec_lo, v255
+// GFX12: encoding: [0x6b,0x00,0x16,0xca,0x7e,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_lo :: v_dual_min_num_f32 v6, exec_hi, v255
+// GFX12: encoding: [0x6a,0x00,0x16,0xca,0x7f,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0xaf123456 :: v_dual_min_num_f32 v6, null, v255
+// GFX12: encoding: [0xff,0x00,0x16,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, src_scc :: v_dual_min_num_f32 v6, -1, v255
+// GFX12: encoding: [0xfd,0x00,0x16,0xca,0xc1,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0.5 :: v_dual_min_num_f32 v6, 0.5, v3
+// GFX12: encoding: [0xf0,0x00,0x16,0xca,0xf0,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, -1 :: v_dual_min_num_f32 v6, src_scc, v4
+// GFX12: encoding: [0xc1,0x00,0x16,0xca,0xfd,0x08,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v6, null :: v_dual_min_num_f32 v255, 0xaf123456, v5
+// GFX12: encoding: [0x7c,0x00,0x16,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v4 :: v_dual_mov_b32 v6, v1
+// GFX12: encoding: [0x04,0x01,0x10,0xca,0x01,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v1 :: v_dual_mov_b32 v6, v255
+// GFX12: encoding: [0x01,0x01,0x10,0xca,0xff,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v255 :: v_dual_mov_b32 v6, v2
+// GFX12: encoding: [0xff,0x01,0x10,0xca,0x02,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v2 :: v_dual_mov_b32 v6, v3
+// GFX12: encoding: [0x02,0x01,0x10,0xca,0x03,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v3 :: v_dual_mov_b32 v6, v4
+// GFX12: encoding: [0x03,0x01,0x10,0xca,0x04,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s105 :: v_dual_mov_b32 v6, s1
+// GFX12: encoding: [0x69,0x00,0x10,0xca,0x01,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s1 :: v_dual_mov_b32 v6, s105
+// GFX12: encoding: [0x01,0x00,0x10,0xca,0x69,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, ttmp15 :: v_dual_mov_b32 v6, vcc_lo
+// GFX12: encoding: [0x7b,0x00,0x10,0xca,0x6a,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_hi :: v_dual_mov_b32 v6, vcc_hi
+// GFX12: encoding: [0x7f,0x00,0x10,0xca,0x6b,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_lo :: v_dual_mov_b32 v6, ttmp15
+// GFX12: encoding: [0x7e,0x00,0x10,0xca,0x7b,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, m0 :: v_dual_mov_b32 v6, m0
+// GFX12: encoding: [0x7d,0x00,0x10,0xca,0x7d,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_hi :: v_dual_mov_b32 v6, exec_lo
+// GFX12: encoding: [0x6b,0x00,0x10,0xca,0x7e,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_lo :: v_dual_mov_b32 v6, exec_hi
+// GFX12: encoding: [0x6a,0x00,0x10,0xca,0x7f,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0xaf123456 :: v_dual_mov_b32 v6, null
+// GFX12: encoding: [0xff,0x00,0x10,0xca,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, src_scc :: v_dual_mov_b32 v6, -1
+// GFX12: encoding: [0xfd,0x00,0x10,0xca,0xc1,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0.5 :: v_dual_mov_b32 v6, 0.5
+// GFX12: encoding: [0xf0,0x00,0x10,0xca,0xf0,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, -1 :: v_dual_mov_b32 v6, src_scc
+// GFX12: encoding: [0xc1,0x00,0x10,0xca,0xfd,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v6, null :: v_dual_mov_b32 v255, 0xaf123456
+// GFX12: encoding: [0x7c,0x00,0x10,0xca,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v4 :: v_dual_mul_dx9_zero_f32 v6, v1, v255
+// GFX12: encoding: [0x04,0x01,0x0e,0xca,0x01,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v1 :: v_dual_mul_dx9_zero_f32 v6, v255, v255
+// GFX12: encoding: [0x01,0x01,0x0e,0xca,0xff,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v255 :: v_dual_mul_dx9_zero_f32 v6, v2, v255
+// GFX12: encoding: [0xff,0x01,0x0e,0xca,0x02,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v2 :: v_dual_mul_dx9_zero_f32 v6, v3, v255
+// GFX12: encoding: [0x02,0x01,0x0e,0xca,0x03,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v3 :: v_dual_mul_dx9_zero_f32 v6, v4, v255
+// GFX12: encoding: [0x03,0x01,0x0e,0xca,0x04,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s105 :: v_dual_mul_dx9_zero_f32 v6, s1, v255
+// GFX12: encoding: [0x69,0x00,0x0e,0xca,0x01,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s1 :: v_dual_mul_dx9_zero_f32 v6, s105, v255
+// GFX12: encoding: [0x01,0x00,0x0e,0xca,0x69,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, ttmp15 :: v_dual_mul_dx9_zero_f32 v6, vcc_lo, v255
+// GFX12: encoding: [0x7b,0x00,0x0e,0xca,0x6a,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_hi :: v_dual_mul_dx9_zero_f32 v6, vcc_hi, v255
+// GFX12: encoding: [0x7f,0x00,0x0e,0xca,0x6b,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_lo :: v_dual_mul_dx9_zero_f32 v6, ttmp15, v255
+// GFX12: encoding: [0x7e,0x00,0x0e,0xca,0x7b,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, m0 :: v_dual_mul_dx9_zero_f32 v6, m0, v255
+// GFX12: encoding: [0x7d,0x00,0x0e,0xca,0x7d,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_hi :: v_dual_mul_dx9_zero_f32 v6, exec_lo, v255
+// GFX12: encoding: [0x6b,0x00,0x0e,0xca,0x7e,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_lo :: v_dual_mul_dx9_zero_f32 v6, exec_hi, v255
+// GFX12: encoding: [0x6a,0x00,0x0e,0xca,0x7f,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, null, v255
+// GFX12: encoding: [0xff,0x00,0x0e,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, src_scc :: v_dual_mul_dx9_zero_f32 v6, -1, v255
+// GFX12: encoding: [0xfd,0x00,0x0e,0xca,0xc1,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0.5 :: v_dual_mul_dx9_zero_f32 v6, 0.5, v3
+// GFX12: encoding: [0xf0,0x00,0x0e,0xca,0xf0,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, -1 :: v_dual_mul_dx9_zero_f32 v6, src_scc, v4
+// GFX12: encoding: [0xc1,0x00,0x0e,0xca,0xfd,0x08,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v6, null :: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v5
+// GFX12: encoding: [0x7c,0x00,0x0e,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v4 :: v_dual_mul_f32 v6, v1, v255
+// GFX12: encoding: [0x04,0x01,0x06,0xca,0x01,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v1 :: v_dual_mul_f32 v6, v255, v255
+// GFX12: encoding: [0x01,0x01,0x06,0xca,0xff,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v255 :: v_dual_mul_f32 v6, v2, v255
+// GFX12: encoding: [0xff,0x01,0x06,0xca,0x02,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v2 :: v_dual_mul_f32 v6, v3, v255
+// GFX12: encoding: [0x02,0x01,0x06,0xca,0x03,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v3 :: v_dual_mul_f32 v6, v4, v255
+// GFX12: encoding: [0x03,0x01,0x06,0xca,0x04,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s105 :: v_dual_mul_f32 v6, s1, v255
+// GFX12: encoding: [0x69,0x00,0x06,0xca,0x01,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s1 :: v_dual_mul_f32 v6, s105, v255
+// GFX12: encoding: [0x01,0x00,0x06,0xca,0x69,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, ttmp15 :: v_dual_mul_f32 v6, vcc_lo, v255
+// GFX12: encoding: [0x7b,0x00,0x06,0xca,0x6a,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_hi :: v_dual_mul_f32 v6, vcc_hi, v255
+// GFX12: encoding: [0x7f,0x00,0x06,0xca,0x6b,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_lo :: v_dual_mul_f32 v6, ttmp15, v255
+// GFX12: encoding: [0x7e,0x00,0x06,0xca,0x7b,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, m0 :: v_dual_mul_f32 v6, m0, v255
+// GFX12: encoding: [0x7d,0x00,0x06,0xca,0x7d,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_hi :: v_dual_mul_f32 v6, exec_lo, v255
+// GFX12: encoding: [0x6b,0x00,0x06,0xca,0x7e,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_lo :: v_dual_mul_f32 v6, exec_hi, v255
+// GFX12: encoding: [0x6a,0x00,0x06,0xca,0x7f,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0xaf123456 :: v_dual_mul_f32 v6, null, v255
+// GFX12: encoding: [0xff,0x00,0x06,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, src_scc :: v_dual_mul_f32 v6, -1, v255
+// GFX12: encoding: [0xfd,0x00,0x06,0xca,0xc1,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0.5 :: v_dual_mul_f32 v6, 0.5, v3
+// GFX12: encoding: [0xf0,0x00,0x06,0xca,0xf0,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, -1 :: v_dual_mul_f32 v6, src_scc, v4
+// GFX12: encoding: [0xc1,0x00,0x06,0xca,0xfd,0x08,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v6, null :: v_dual_mul_f32 v255, 0xaf123456, v5
+// GFX12: encoding: [0x7c,0x00,0x06,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v4 :: v_dual_sub_f32 v6, v1, v255
+// GFX12: encoding: [0x04,0x01,0x0a,0xca,0x01,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v1 :: v_dual_sub_f32 v6, v255, v255
+// GFX12: encoding: [0x01,0x01,0x0a,0xca,0xff,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v255 :: v_dual_sub_f32 v6, v2, v255
+// GFX12: encoding: [0xff,0x01,0x0a,0xca,0x02,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v2 :: v_dual_sub_f32 v6, v3, v255
+// GFX12: encoding: [0x02,0x01,0x0a,0xca,0x03,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v3 :: v_dual_sub_f32 v6, v4, v255
+// GFX12: encoding: [0x03,0x01,0x0a,0xca,0x04,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s105 :: v_dual_sub_f32 v6, s1, v255
+// GFX12: encoding: [0x69,0x00,0x0a,0xca,0x01,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s1 :: v_dual_sub_f32 v6, s105, v255
+// GFX12: encoding: [0x01,0x00,0x0a,0xca,0x69,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, ttmp15 :: v_dual_sub_f32 v6, vcc_lo, v255
+// GFX12: encoding: [0x7b,0x00,0x0a,0xca,0x6a,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_hi :: v_dual_sub_f32 v6, vcc_hi, v255
+// GFX12: encoding: [0x7f,0x00,0x0a,0xca,0x6b,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_lo :: v_dual_sub_f32 v6, ttmp15, v255
+// GFX12: encoding: [0x7e,0x00,0x0a,0xca,0x7b,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, m0 :: v_dual_sub_f32 v6, m0, v255
+// GFX12: encoding: [0x7d,0x00,0x0a,0xca,0x7d,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_hi :: v_dual_sub_f32 v6, exec_lo, v255
+// GFX12: encoding: [0x6b,0x00,0x0a,0xca,0x7e,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_lo :: v_dual_sub_f32 v6, exec_hi, v255
+// GFX12: encoding: [0x6a,0x00,0x0a,0xca,0x7f,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0xaf123456 :: v_dual_sub_f32 v6, null, v255
+// GFX12: encoding: [0xff,0x00,0x0a,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, src_scc :: v_dual_sub_f32 v6, -1, v255
+// GFX12: encoding: [0xfd,0x00,0x0a,0xca,0xc1,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0.5 :: v_dual_sub_f32 v6, 0.5, v3
+// GFX12: encoding: [0xf0,0x00,0x0a,0xca,0xf0,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, -1 :: v_dual_sub_f32 v6, src_scc, v4
+// GFX12: encoding: [0xc1,0x00,0x0a,0xca,0xfd,0x08,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v6, null :: v_dual_sub_f32 v255, 0xaf123456, v5
+// GFX12: encoding: [0x7c,0x00,0x0a,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v4 :: v_dual_subrev_f32 v6, v1, v255
+// GFX12: encoding: [0x04,0x01,0x0c,0xca,0x01,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v1 :: v_dual_subrev_f32 v6, v255, v255
+// GFX12: encoding: [0x01,0x01,0x0c,0xca,0xff,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v255 :: v_dual_subrev_f32 v6, v2, v255
+// GFX12: encoding: [0xff,0x01,0x0c,0xca,0x02,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v2 :: v_dual_subrev_f32 v6, v3, v255
+// GFX12: encoding: [0x02,0x01,0x0c,0xca,0x03,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, v3 :: v_dual_subrev_f32 v6, v4, v255
+// GFX12: encoding: [0x03,0x01,0x0c,0xca,0x04,0xff,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s105 :: v_dual_subrev_f32 v6, s1, v255
+// GFX12: encoding: [0x69,0x00,0x0c,0xca,0x01,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, s1 :: v_dual_subrev_f32 v6, s105, v255
+// GFX12: encoding: [0x01,0x00,0x0c,0xca,0x69,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, ttmp15 :: v_dual_subrev_f32 v6, vcc_lo, v255
+// GFX12: encoding: [0x7b,0x00,0x0c,0xca,0x6a,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_hi :: v_dual_subrev_f32 v6, vcc_hi, v255
+// GFX12: encoding: [0x7f,0x00,0x0c,0xca,0x6b,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, exec_lo :: v_dual_subrev_f32 v6, ttmp15, v255
+// GFX12: encoding: [0x7e,0x00,0x0c,0xca,0x7b,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, m0 :: v_dual_subrev_f32 v6, m0, v255
+// GFX12: encoding: [0x7d,0x00,0x0c,0xca,0x7d,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_hi :: v_dual_subrev_f32 v6, exec_lo, v255
+// GFX12: encoding: [0x6b,0x00,0x0c,0xca,0x7e,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, vcc_lo :: v_dual_subrev_f32 v6, exec_hi, v255
+// GFX12: encoding: [0x6a,0x00,0x0c,0xca,0x7f,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0xaf123456 :: v_dual_subrev_f32 v6, null, v255
+// GFX12: encoding: [0xff,0x00,0x0c,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, src_scc :: v_dual_subrev_f32 v6, -1, v255
+// GFX12: encoding: [0xfd,0x00,0x0c,0xca,0xc1,0xfe,0x07,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, 0.5 :: v_dual_subrev_f32 v6, 0.5, v3
+// GFX12: encoding: [0xf0,0x00,0x0c,0xca,0xf0,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v255, -1 :: v_dual_subrev_f32 v6, src_scc, v4
+// GFX12: encoding: [0xc1,0x00,0x0c,0xca,0xfd,0x08,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mov_b32 v6, null :: v_dual_subrev_f32 v255, 0xaf123456, v5
+// GFX12: encoding: [0x7c,0x00,0x0c,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v4, v2 :: v_dual_add_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xc8,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v1, v2 :: v_dual_add_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xc8,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v255, v2 :: v_dual_add_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xc8,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v2, v2 :: v_dual_add_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xc8,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v3, v2 :: v_dual_add_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xc8,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s105, v2 :: v_dual_add_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xc8,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s1, v2 :: v_dual_add_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xc8,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, ttmp15, v2 :: v_dual_add_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xc8,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_hi, v2 :: v_dual_add_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xc8,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_lo, v2 :: v_dual_add_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xc8,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, m0, v2 :: v_dual_add_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xc8,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_hi, v2 :: v_dual_add_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xc8,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_lo, v2 :: v_dual_add_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xc8,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v2 :: v_dual_add_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xc8,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, src_scc, v2 :: v_dual_add_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xc8,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_add_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xc8,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_add_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xc8,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_add_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xc8,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v4, v2 :: v_dual_add_nc_u32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xe0,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v1, v2 :: v_dual_add_nc_u32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xe0,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v255, v2 :: v_dual_add_nc_u32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xe0,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v2, v2 :: v_dual_add_nc_u32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xe0,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v3, v2 :: v_dual_add_nc_u32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xe0,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s105, v2 :: v_dual_add_nc_u32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xe0,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s1, v2 :: v_dual_add_nc_u32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xe0,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, ttmp15, v2 :: v_dual_add_nc_u32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xe0,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_hi, v2 :: v_dual_add_nc_u32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xe0,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_lo, v2 :: v_dual_add_nc_u32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xe0,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, m0, v2 :: v_dual_add_nc_u32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xe0,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_hi, v2 :: v_dual_add_nc_u32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xe0,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_lo, v2 :: v_dual_add_nc_u32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xe0,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v2 :: v_dual_add_nc_u32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xe0,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, src_scc, v2 :: v_dual_add_nc_u32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xe0,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_add_nc_u32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xe0,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_add_nc_u32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xe0,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_add_nc_u32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xe0,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v4, v2 :: v_dual_and_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xe4,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v1, v2 :: v_dual_and_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xe4,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v255, v2 :: v_dual_and_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xe4,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v2, v2 :: v_dual_and_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xe4,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v3, v2 :: v_dual_and_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xe4,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s105, v2 :: v_dual_and_b32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xe4,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s1, v2 :: v_dual_and_b32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xe4,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, ttmp15, v2 :: v_dual_and_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xe4,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_hi, v2 :: v_dual_and_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xe4,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_lo, v2 :: v_dual_and_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xe4,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, m0, v2 :: v_dual_and_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xe4,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_hi, v2 :: v_dual_and_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xe4,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_lo, v2 :: v_dual_and_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xe4,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v2 :: v_dual_and_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xe4,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, src_scc, v2 :: v_dual_and_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xe4,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_and_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xe4,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_and_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xe4,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_and_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xe4,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v4, v2 :: v_dual_cndmask_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xd2,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v1, v2 :: v_dual_cndmask_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xd2,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v255, v2 :: v_dual_cndmask_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xd2,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v2, v2 :: v_dual_cndmask_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xd2,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v3, v2 :: v_dual_cndmask_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xd2,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s105, v2 :: v_dual_cndmask_b32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0xd2,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s1, v2 :: v_dual_cndmask_b32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0xd2,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, ttmp15, v2 :: v_dual_cndmask_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0xd2,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_hi, v2 :: v_dual_cndmask_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xd2,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_lo, v2 :: v_dual_cndmask_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0xd2,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, m0, v2 :: v_dual_cndmask_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xd2,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_hi, v2 :: v_dual_cndmask_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0xd2,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_lo, v2 :: v_dual_cndmask_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0xd2,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v2 :: v_dual_cndmask_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xd2,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, src_scc, v2 :: v_dual_cndmask_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xd2,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_cndmask_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xd2,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_cndmask_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xd2,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_cndmask_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xd2,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v4, v2 :: v_dual_fmaak_f32 v6, v1, v3, 0xaf123456
+// GFX12: encoding: [0x04,0x05,0xc2,0xc9,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v1, v2 :: v_dual_fmaak_f32 v6, v255, v3, 0xaf123456
+// GFX12: encoding: [0x01,0x05,0xc2,0xc9,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v255, v2 :: v_dual_fmaak_f32 v6, v2, v3, 0xaf123456
+// GFX12: encoding: [0xff,0x05,0xc2,0xc9,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v2, v2 :: v_dual_fmaak_f32 v6, v3, v3, 0xaf123456
+// GFX12: encoding: [0x02,0x05,0xc2,0xc9,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v3, v2 :: v_dual_fmaak_f32 v6, v4, v3, 0xaf123456
+// GFX12: encoding: [0x03,0x05,0xc2,0xc9,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s105, v2 :: v_dual_fmaak_f32 v6, s105, v3, 0xaf123456
+// GFX12: encoding: [0x69,0x04,0xc2,0xc9,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s1, v2 :: v_dual_fmaak_f32 v6, s1, v3, 0xaf123456
+// GFX12: encoding: [0x01,0x04,0xc2,0xc9,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, ttmp15, v2 :: v_dual_fmaak_f32 v6, ttmp15, v3, 0xaf123456
+// GFX12: encoding: [0x7b,0x04,0xc2,0xc9,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_hi, v2 :: v_dual_fmaak_f32 v6, exec_hi, v3, 0xaf123456
+// GFX12: encoding: [0x7f,0x04,0xc2,0xc9,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_lo, v2 :: v_dual_fmaak_f32 v6, exec_lo, v3, 0xaf123456
+// GFX12: encoding: [0x7e,0x04,0xc2,0xc9,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, m0, v2 :: v_dual_fmaak_f32 v6, m0, v3, 0xaf123456
+// GFX12: encoding: [0x7d,0x04,0xc2,0xc9,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_hi, v2 :: v_dual_fmaak_f32 v6, vcc_hi, v3, 0xaf123456
+// GFX12: encoding: [0x6b,0x04,0xc2,0xc9,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_lo, v2 :: v_dual_fmaak_f32 v6, vcc_lo, v3, 0xaf123456
+// GFX12: encoding: [0x6a,0x04,0xc2,0xc9,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, null, v3, 0xaf123456
+// GFX12: encoding: [0xff,0x04,0xc2,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, src_scc, v2 :: v_dual_fmaak_f32 v6, -1, v3, 0xaf123456
+// GFX12: encoding: [0xfd,0x04,0xc2,0xc9,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_fmaak_f32 v6, 0.5, v2, 0xaf123456
+// GFX12: encoding: [0xf0,0x06,0xc2,0xc9,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_fmaak_f32 v6, src_scc, v5, 0xaf123456
+// GFX12: encoding: [0xc1,0x08,0xc2,0xc9,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_fmaak_f32 v255, 0xaf123456, v4, 0xaf123456
+// GFX12: encoding: [0x7c,0x0a,0xc2,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v4, v2 :: v_dual_fmac_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xc0,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v1, v2 :: v_dual_fmac_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xc0,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v255, v2 :: v_dual_fmac_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xc0,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v2, v2 :: v_dual_fmac_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xc0,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v3, v2 :: v_dual_fmac_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xc0,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s105, v2 :: v_dual_fmac_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xc0,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s1, v2 :: v_dual_fmac_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xc0,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, ttmp15, v2 :: v_dual_fmac_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xc0,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_hi, v2 :: v_dual_fmac_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xc0,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_lo, v2 :: v_dual_fmac_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xc0,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, m0, v2 :: v_dual_fmac_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xc0,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_hi, v2 :: v_dual_fmac_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xc0,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_lo, v2 :: v_dual_fmac_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xc0,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v2 :: v_dual_fmac_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xc0,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, src_scc, v2 :: v_dual_fmac_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xc0,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_fmac_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xc0,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_fmac_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xc0,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_fmac_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xc0,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v4, v255 :: v_dual_fmamk_f32 v6, v1, 0xaf123456, v255
+// GFX12: encoding: [0x04,0xff,0xc5,0xc9,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v1, v255 :: v_dual_fmamk_f32 v6, v255, 0xaf123456, v255
+// GFX12: encoding: [0x01,0xff,0xc5,0xc9,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v255, v255 :: v_dual_fmamk_f32 v6, v2, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xff,0xc5,0xc9,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v2, v255 :: v_dual_fmamk_f32 v6, v3, 0xaf123456, v255
+// GFX12: encoding: [0x02,0xff,0xc5,0xc9,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v3, v255 :: v_dual_fmamk_f32 v6, v4, 0xaf123456, v255
+// GFX12: encoding: [0x03,0xff,0xc5,0xc9,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s105, v255 :: v_dual_fmamk_f32 v6, s105, 0xaf123456, v255
+// GFX12: encoding: [0x69,0xfe,0xc5,0xc9,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s1, v255 :: v_dual_fmamk_f32 v6, s1, 0xaf123456, v255
+// GFX12: encoding: [0x01,0xfe,0xc5,0xc9,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, ttmp15, v255 :: v_dual_fmamk_f32 v6, ttmp15, 0xaf123456, v255
+// GFX12: encoding: [0x7b,0xfe,0xc5,0xc9,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_hi, v255 :: v_dual_fmamk_f32 v6, exec_hi, 0xaf123456, v255
+// GFX12: encoding: [0x7f,0xfe,0xc5,0xc9,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_lo, v255 :: v_dual_fmamk_f32 v6, exec_lo, 0xaf123456, v255
+// GFX12: encoding: [0x7e,0xfe,0xc5,0xc9,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, m0, v255 :: v_dual_fmamk_f32 v6, m0, 0xaf123456, v255
+// GFX12: encoding: [0x7d,0xfe,0xc5,0xc9,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_hi, v255 :: v_dual_fmamk_f32 v6, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x6b,0xfe,0xc5,0xc9,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_lo, v255 :: v_dual_fmamk_f32 v6, vcc_lo, 0xaf123456, v255
+// GFX12: encoding: [0x6a,0xfe,0xc5,0xc9,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, null, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xc5,0xc9,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, src_scc, v255 :: v_dual_fmamk_f32 v6, -1, 0xaf123456, v255
+// GFX12: encoding: [0xfd,0xfe,0xc5,0xc9,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_fmamk_f32 v6, 0.5, 0xaf123456, v255
+// GFX12: encoding: [0xf0,0x06,0xc4,0xc9,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_fmamk_f32 v6, src_scc, 0xaf123456, v255
+// GFX12: encoding: [0xc1,0x08,0xc4,0xc9,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xc4,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v4, v2 :: v_dual_lshlrev_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xe2,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v1, v2 :: v_dual_lshlrev_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xe2,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v255, v2 :: v_dual_lshlrev_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xe2,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v2, v2 :: v_dual_lshlrev_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xe2,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v3, v2 :: v_dual_lshlrev_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xe2,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s105, v2 :: v_dual_lshlrev_b32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xe2,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s1, v2 :: v_dual_lshlrev_b32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xe2,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, ttmp15, v2 :: v_dual_lshlrev_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xe2,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_hi, v2 :: v_dual_lshlrev_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xe2,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_lo, v2 :: v_dual_lshlrev_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xe2,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, m0, v2 :: v_dual_lshlrev_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xe2,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_hi, v2 :: v_dual_lshlrev_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xe2,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_lo, v2 :: v_dual_lshlrev_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xe2,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v2 :: v_dual_lshlrev_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xe2,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, src_scc, v2 :: v_dual_lshlrev_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xe2,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_lshlrev_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xe2,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_lshlrev_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xe2,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_lshlrev_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xe2,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v4, v2 :: v_dual_max_num_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xd4,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v1, v2 :: v_dual_max_num_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xd4,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v255, v2 :: v_dual_max_num_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xd4,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v2, v2 :: v_dual_max_num_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xd4,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v3, v2 :: v_dual_max_num_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xd4,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s105, v2 :: v_dual_max_num_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xd4,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s1, v2 :: v_dual_max_num_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xd4,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, ttmp15, v2 :: v_dual_max_num_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xd4,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_hi, v2 :: v_dual_max_num_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xd4,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_lo, v2 :: v_dual_max_num_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xd4,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, m0, v2 :: v_dual_max_num_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xd4,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_hi, v2 :: v_dual_max_num_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xd4,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_lo, v2 :: v_dual_max_num_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xd4,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v2 :: v_dual_max_num_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xd4,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, src_scc, v2 :: v_dual_max_num_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xd4,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_max_num_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xd4,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_max_num_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xd4,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_max_num_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xd4,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v4, v2 :: v_dual_min_num_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xd6,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v1, v2 :: v_dual_min_num_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xd6,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v255, v2 :: v_dual_min_num_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xd6,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v2, v2 :: v_dual_min_num_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xd6,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v3, v2 :: v_dual_min_num_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xd6,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s105, v2 :: v_dual_min_num_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xd6,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s1, v2 :: v_dual_min_num_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xd6,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, ttmp15, v2 :: v_dual_min_num_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xd6,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_hi, v2 :: v_dual_min_num_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xd6,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_lo, v2 :: v_dual_min_num_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xd6,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, m0, v2 :: v_dual_min_num_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xd6,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_hi, v2 :: v_dual_min_num_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xd6,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_lo, v2 :: v_dual_min_num_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xd6,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v2 :: v_dual_min_num_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xd6,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, src_scc, v2 :: v_dual_min_num_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xd6,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_min_num_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xd6,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_min_num_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xd6,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_min_num_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xd6,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v4, v255 :: v_dual_mov_b32 v6, v1
+// GFX12: encoding: [0x04,0xff,0xd1,0xc9,0x01,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v1, v255 :: v_dual_mov_b32 v6, v255
+// GFX12: encoding: [0x01,0xff,0xd1,0xc9,0xff,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v255, v255 :: v_dual_mov_b32 v6, v2
+// GFX12: encoding: [0xff,0xff,0xd1,0xc9,0x02,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v2, v255 :: v_dual_mov_b32 v6, v3
+// GFX12: encoding: [0x02,0xff,0xd1,0xc9,0x03,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v3, v255 :: v_dual_mov_b32 v6, v4
+// GFX12: encoding: [0x03,0xff,0xd1,0xc9,0x04,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s105, v255 :: v_dual_mov_b32 v6, s1
+// GFX12: encoding: [0x69,0xfe,0xd1,0xc9,0x01,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s1, v255 :: v_dual_mov_b32 v6, s105
+// GFX12: encoding: [0x01,0xfe,0xd1,0xc9,0x69,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, ttmp15, v255 :: v_dual_mov_b32 v6, vcc_lo
+// GFX12: encoding: [0x7b,0xfe,0xd1,0xc9,0x6a,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_hi, v255 :: v_dual_mov_b32 v6, vcc_hi
+// GFX12: encoding: [0x7f,0xfe,0xd1,0xc9,0x6b,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_lo, v255 :: v_dual_mov_b32 v6, ttmp15
+// GFX12: encoding: [0x7e,0xfe,0xd1,0xc9,0x7b,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, m0, v255 :: v_dual_mov_b32 v6, m0
+// GFX12: encoding: [0x7d,0xfe,0xd1,0xc9,0x7d,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_hi, v255 :: v_dual_mov_b32 v6, exec_lo
+// GFX12: encoding: [0x6b,0xfe,0xd1,0xc9,0x7e,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_lo, v255 :: v_dual_mov_b32 v6, exec_hi
+// GFX12: encoding: [0x6a,0xfe,0xd1,0xc9,0x7f,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v255 :: v_dual_mov_b32 v6, null
+// GFX12: encoding: [0xff,0xfe,0xd1,0xc9,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, src_scc, v255 :: v_dual_mov_b32 v6, -1
+// GFX12: encoding: [0xfd,0xfe,0xd1,0xc9,0xc1,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_mov_b32 v6, 0.5
+// GFX12: encoding: [0xf0,0x06,0xd0,0xc9,0xf0,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_mov_b32 v6, src_scc
+// GFX12: encoding: [0xc1,0x08,0xd0,0xc9,0xfd,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_mov_b32 v255, 0xaf123456
+// GFX12: encoding: [0x7c,0x0a,0xd0,0xc9,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v4, v2 :: v_dual_mul_dx9_zero_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xce,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v1, v2 :: v_dual_mul_dx9_zero_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xce,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v255, v2 :: v_dual_mul_dx9_zero_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xce,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v2, v2 :: v_dual_mul_dx9_zero_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xce,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v3, v2 :: v_dual_mul_dx9_zero_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xce,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s105, v2 :: v_dual_mul_dx9_zero_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xce,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s1, v2 :: v_dual_mul_dx9_zero_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xce,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, ttmp15, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xce,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xce,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xce,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, m0, v2 :: v_dual_mul_dx9_zero_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xce,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xce,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xce,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v2 :: v_dual_mul_dx9_zero_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xce,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, src_scc, v2 :: v_dual_mul_dx9_zero_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xce,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_mul_dx9_zero_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xce,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_mul_dx9_zero_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xce,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xce,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v4, v2 :: v_dual_mul_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xc6,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v1, v2 :: v_dual_mul_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xc6,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v255, v2 :: v_dual_mul_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xc6,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v2, v2 :: v_dual_mul_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xc6,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v3, v2 :: v_dual_mul_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xc6,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s105, v2 :: v_dual_mul_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xc6,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s1, v2 :: v_dual_mul_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xc6,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, ttmp15, v2 :: v_dual_mul_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xc6,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_hi, v2 :: v_dual_mul_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xc6,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_lo, v2 :: v_dual_mul_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xc6,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, m0, v2 :: v_dual_mul_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xc6,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_hi, v2 :: v_dual_mul_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xc6,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_lo, v2 :: v_dual_mul_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xc6,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v2 :: v_dual_mul_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xc6,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, src_scc, v2 :: v_dual_mul_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xc6,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_mul_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xc6,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_mul_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xc6,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_mul_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xc6,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v4, v2 :: v_dual_sub_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xca,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v1, v2 :: v_dual_sub_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xca,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v255, v2 :: v_dual_sub_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xca,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v2, v2 :: v_dual_sub_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xca,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v3, v2 :: v_dual_sub_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xca,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s105, v2 :: v_dual_sub_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xca,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s1, v2 :: v_dual_sub_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xca,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, ttmp15, v2 :: v_dual_sub_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xca,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_hi, v2 :: v_dual_sub_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xca,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_lo, v2 :: v_dual_sub_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xca,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, m0, v2 :: v_dual_sub_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xca,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_hi, v2 :: v_dual_sub_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xca,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_lo, v2 :: v_dual_sub_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xca,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v2 :: v_dual_sub_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xca,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, src_scc, v2 :: v_dual_sub_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xca,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_sub_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xca,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_sub_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xca,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_sub_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xca,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v4, v2 :: v_dual_subrev_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xcc,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v1, v2 :: v_dual_subrev_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xcc,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v255, v2 :: v_dual_subrev_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xcc,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v2, v2 :: v_dual_subrev_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xcc,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, v3, v2 :: v_dual_subrev_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xcc,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s105, v2 :: v_dual_subrev_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xcc,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, s1, v2 :: v_dual_subrev_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xcc,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, ttmp15, v2 :: v_dual_subrev_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xcc,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_hi, v2 :: v_dual_subrev_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xcc,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, exec_lo, v2 :: v_dual_subrev_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xcc,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, m0, v2 :: v_dual_subrev_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xcc,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_hi, v2 :: v_dual_subrev_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xcc,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, vcc_lo, v2 :: v_dual_subrev_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xcc,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v2 :: v_dual_subrev_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xcc,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, src_scc, v2 :: v_dual_subrev_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xcc,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_subrev_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xcc,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_subrev_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xcc,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xcc,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v4, v2 :: v_dual_add_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xc8,0xc8,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v1, v2 :: v_dual_add_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xc8,0xc8,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v255, v2 :: v_dual_add_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xc8,0xc8,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v2, v2 :: v_dual_add_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xc8,0xc8,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v3, v2 :: v_dual_add_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xc8,0xc8,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s105, v2 :: v_dual_add_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xc8,0xc8,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s1, v2 :: v_dual_add_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xc8,0xc8,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, ttmp15, v2 :: v_dual_add_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xc8,0xc8,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_hi, v2 :: v_dual_add_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xc8,0xc8,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_lo, v2 :: v_dual_add_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xc8,0xc8,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, m0, v2 :: v_dual_add_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xc8,0xc8,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_hi, v2 :: v_dual_add_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xc8,0xc8,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_lo, v2 :: v_dual_add_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xc8,0xc8,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0xaf123456, v2 :: v_dual_add_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xc8,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, src_scc, v2 :: v_dual_add_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xc8,0xc8,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0.5, v3 :: v_dual_add_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xc8,0xc8,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, -1, v4 :: v_dual_add_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xc8,0xc8,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v6, null, v5 :: v_dual_add_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xc8,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v4, v2 :: v_dual_add_nc_u32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xe0,0xc8,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v1, v2 :: v_dual_add_nc_u32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xe0,0xc8,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v255, v2 :: v_dual_add_nc_u32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xe0,0xc8,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v2, v2 :: v_dual_add_nc_u32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xe0,0xc8,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v3, v2 :: v_dual_add_nc_u32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xe0,0xc8,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s105, v2 :: v_dual_add_nc_u32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xe0,0xc8,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s1, v2 :: v_dual_add_nc_u32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xe0,0xc8,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, ttmp15, v2 :: v_dual_add_nc_u32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xe0,0xc8,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_hi, v2 :: v_dual_add_nc_u32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xe0,0xc8,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_lo, v2 :: v_dual_add_nc_u32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xe0,0xc8,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, m0, v2 :: v_dual_add_nc_u32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xe0,0xc8,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_hi, v2 :: v_dual_add_nc_u32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xe0,0xc8,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_lo, v2 :: v_dual_add_nc_u32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xe0,0xc8,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0xaf123456, v2 :: v_dual_add_nc_u32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xe0,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, src_scc, v2 :: v_dual_add_nc_u32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xe0,0xc8,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0.5, v3 :: v_dual_add_nc_u32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xe0,0xc8,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, -1, v4 :: v_dual_add_nc_u32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xe0,0xc8,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v6, null, v5 :: v_dual_add_nc_u32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xe0,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v4, v2 :: v_dual_and_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xe4,0xc8,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v1, v2 :: v_dual_and_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xe4,0xc8,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v255, v2 :: v_dual_and_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xe4,0xc8,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v2, v2 :: v_dual_and_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xe4,0xc8,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v3, v2 :: v_dual_and_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xe4,0xc8,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s105, v2 :: v_dual_and_b32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xe4,0xc8,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s1, v2 :: v_dual_and_b32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xe4,0xc8,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, ttmp15, v2 :: v_dual_and_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xe4,0xc8,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_hi, v2 :: v_dual_and_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xe4,0xc8,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_lo, v2 :: v_dual_and_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xe4,0xc8,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, m0, v2 :: v_dual_and_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xe4,0xc8,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_hi, v2 :: v_dual_and_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xe4,0xc8,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_lo, v2 :: v_dual_and_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xe4,0xc8,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0xaf123456, v2 :: v_dual_and_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xe4,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, src_scc, v2 :: v_dual_and_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xe4,0xc8,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0.5, v3 :: v_dual_and_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xe4,0xc8,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, -1, v4 :: v_dual_and_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xe4,0xc8,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v6, null, v5 :: v_dual_and_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xe4,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v4, v2 :: v_dual_cndmask_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xd2,0xc8,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v1, v2 :: v_dual_cndmask_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xd2,0xc8,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v255, v2 :: v_dual_cndmask_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xd2,0xc8,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v2, v2 :: v_dual_cndmask_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xd2,0xc8,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v3, v2 :: v_dual_cndmask_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xd2,0xc8,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s105, v2 :: v_dual_cndmask_b32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0xd2,0xc8,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s1, v2 :: v_dual_cndmask_b32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0xd2,0xc8,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, ttmp15, v2 :: v_dual_cndmask_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0xd2,0xc8,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_hi, v2 :: v_dual_cndmask_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xd2,0xc8,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_lo, v2 :: v_dual_cndmask_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0xd2,0xc8,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, m0, v2 :: v_dual_cndmask_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xd2,0xc8,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_hi, v2 :: v_dual_cndmask_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0xd2,0xc8,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_lo, v2 :: v_dual_cndmask_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0xd2,0xc8,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0xaf123456, v2 :: v_dual_cndmask_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xd2,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, src_scc, v2 :: v_dual_cndmask_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xd2,0xc8,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0.5, v3 :: v_dual_cndmask_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xd2,0xc8,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, -1, v4 :: v_dual_cndmask_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xd2,0xc8,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v6, null, v5 :: v_dual_cndmask_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xd2,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v4, v2 :: v_dual_fmaak_f32 v6, v1, v3, 0xaf123456
+// GFX12: encoding: [0x04,0x05,0xc2,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v1, v2 :: v_dual_fmaak_f32 v6, v255, v3, 0xaf123456
+// GFX12: encoding: [0x01,0x05,0xc2,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v255, v2 :: v_dual_fmaak_f32 v6, v2, v3, 0xaf123456
+// GFX12: encoding: [0xff,0x05,0xc2,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v2, v2 :: v_dual_fmaak_f32 v6, v3, v3, 0xaf123456
+// GFX12: encoding: [0x02,0x05,0xc2,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v3, v2 :: v_dual_fmaak_f32 v6, v4, v3, 0xaf123456
+// GFX12: encoding: [0x03,0x05,0xc2,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s105, v2 :: v_dual_fmaak_f32 v6, s105, v3, 0xaf123456
+// GFX12: encoding: [0x69,0x04,0xc2,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s1, v2 :: v_dual_fmaak_f32 v6, s1, v3, 0xaf123456
+// GFX12: encoding: [0x01,0x04,0xc2,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, ttmp15, v2 :: v_dual_fmaak_f32 v6, ttmp15, v3, 0xaf123456
+// GFX12: encoding: [0x7b,0x04,0xc2,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_hi, v2 :: v_dual_fmaak_f32 v6, exec_hi, v3, 0xaf123456
+// GFX12: encoding: [0x7f,0x04,0xc2,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_lo, v2 :: v_dual_fmaak_f32 v6, exec_lo, v3, 0xaf123456
+// GFX12: encoding: [0x7e,0x04,0xc2,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, m0, v2 :: v_dual_fmaak_f32 v6, m0, v3, 0xaf123456
+// GFX12: encoding: [0x7d,0x04,0xc2,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_hi, v2 :: v_dual_fmaak_f32 v6, vcc_hi, v3, 0xaf123456
+// GFX12: encoding: [0x6b,0x04,0xc2,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_lo, v2 :: v_dual_fmaak_f32 v6, vcc_lo, v3, 0xaf123456
+// GFX12: encoding: [0x6a,0x04,0xc2,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, null, v3, 0xaf123456
+// GFX12: encoding: [0xff,0x04,0xc2,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, src_scc, v2 :: v_dual_fmaak_f32 v6, -1, v3, 0xaf123456
+// GFX12: encoding: [0xfd,0x04,0xc2,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0.5, v3 :: v_dual_fmaak_f32 v6, 0.5, v2, 0xaf123456
+// GFX12: encoding: [0xf0,0x06,0xc2,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, -1, v4 :: v_dual_fmaak_f32 v6, src_scc, v5, 0xaf123456
+// GFX12: encoding: [0xc1,0x08,0xc2,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v6, null, v5 :: v_dual_fmaak_f32 v255, 0xaf123456, v4, 0xaf123456
+// GFX12: encoding: [0x7c,0x0a,0xc2,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v4, v2 :: v_dual_fmac_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xc0,0xc8,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v1, v2 :: v_dual_fmac_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xc0,0xc8,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v255, v2 :: v_dual_fmac_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xc0,0xc8,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v2, v2 :: v_dual_fmac_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xc0,0xc8,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v3, v2 :: v_dual_fmac_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xc0,0xc8,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s105, v2 :: v_dual_fmac_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xc0,0xc8,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s1, v2 :: v_dual_fmac_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xc0,0xc8,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, ttmp15, v2 :: v_dual_fmac_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xc0,0xc8,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_hi, v2 :: v_dual_fmac_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xc0,0xc8,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_lo, v2 :: v_dual_fmac_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xc0,0xc8,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, m0, v2 :: v_dual_fmac_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xc0,0xc8,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_hi, v2 :: v_dual_fmac_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xc0,0xc8,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_lo, v2 :: v_dual_fmac_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xc0,0xc8,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0xaf123456, v2 :: v_dual_fmac_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xc0,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, src_scc, v2 :: v_dual_fmac_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xc0,0xc8,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0.5, v3 :: v_dual_fmac_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xc0,0xc8,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, -1, v4 :: v_dual_fmac_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xc0,0xc8,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v6, null, v5 :: v_dual_fmac_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xc0,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v4, v255 :: v_dual_fmamk_f32 v6, v1, 0xaf123456, v255
+// GFX12: encoding: [0x04,0xff,0xc5,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v1, v255 :: v_dual_fmamk_f32 v6, v255, 0xaf123456, v255
+// GFX12: encoding: [0x01,0xff,0xc5,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v255, v255 :: v_dual_fmamk_f32 v6, v2, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xff,0xc5,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v2, v255 :: v_dual_fmamk_f32 v6, v3, 0xaf123456, v255
+// GFX12: encoding: [0x02,0xff,0xc5,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v3, v255 :: v_dual_fmamk_f32 v6, v4, 0xaf123456, v255
+// GFX12: encoding: [0x03,0xff,0xc5,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s105, v255 :: v_dual_fmamk_f32 v6, s105, 0xaf123456, v255
+// GFX12: encoding: [0x69,0xfe,0xc5,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s1, v255 :: v_dual_fmamk_f32 v6, s1, 0xaf123456, v255
+// GFX12: encoding: [0x01,0xfe,0xc5,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, ttmp15, v255 :: v_dual_fmamk_f32 v6, ttmp15, 0xaf123456, v255
+// GFX12: encoding: [0x7b,0xfe,0xc5,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_hi, v255 :: v_dual_fmamk_f32 v6, exec_hi, 0xaf123456, v255
+// GFX12: encoding: [0x7f,0xfe,0xc5,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_lo, v255 :: v_dual_fmamk_f32 v6, exec_lo, 0xaf123456, v255
+// GFX12: encoding: [0x7e,0xfe,0xc5,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, m0, v255 :: v_dual_fmamk_f32 v6, m0, 0xaf123456, v255
+// GFX12: encoding: [0x7d,0xfe,0xc5,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_hi, v255 :: v_dual_fmamk_f32 v6, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x6b,0xfe,0xc5,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_lo, v255 :: v_dual_fmamk_f32 v6, vcc_lo, 0xaf123456, v255
+// GFX12: encoding: [0x6a,0xfe,0xc5,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, null, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0xc5,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, src_scc, v255 :: v_dual_fmamk_f32 v6, -1, 0xaf123456, v255
+// GFX12: encoding: [0xfd,0xfe,0xc5,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0.5, v3 :: v_dual_fmamk_f32 v6, 0.5, 0xaf123456, v255
+// GFX12: encoding: [0xf0,0x06,0xc4,0xc8,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, -1, v4 :: v_dual_fmamk_f32 v6, src_scc, 0xaf123456, v255
+// GFX12: encoding: [0xc1,0x08,0xc4,0xc8,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v6, null, v5 :: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xc4,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v4, v2 :: v_dual_lshlrev_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xe2,0xc8,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v1, v2 :: v_dual_lshlrev_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xe2,0xc8,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v255, v2 :: v_dual_lshlrev_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xe2,0xc8,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v2, v2 :: v_dual_lshlrev_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xe2,0xc8,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v3, v2 :: v_dual_lshlrev_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xe2,0xc8,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s105, v2 :: v_dual_lshlrev_b32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xe2,0xc8,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s1, v2 :: v_dual_lshlrev_b32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xe2,0xc8,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, ttmp15, v2 :: v_dual_lshlrev_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xe2,0xc8,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_hi, v2 :: v_dual_lshlrev_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xe2,0xc8,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_lo, v2 :: v_dual_lshlrev_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xe2,0xc8,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, m0, v2 :: v_dual_lshlrev_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xe2,0xc8,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_hi, v2 :: v_dual_lshlrev_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xe2,0xc8,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_lo, v2 :: v_dual_lshlrev_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xe2,0xc8,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0xaf123456, v2 :: v_dual_lshlrev_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xe2,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, src_scc, v2 :: v_dual_lshlrev_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xe2,0xc8,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0.5, v3 :: v_dual_lshlrev_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xe2,0xc8,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, -1, v4 :: v_dual_lshlrev_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xe2,0xc8,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v6, null, v5 :: v_dual_lshlrev_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xe2,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v4, v2 :: v_dual_max_num_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xd4,0xc8,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v1, v2 :: v_dual_max_num_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xd4,0xc8,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v255, v2 :: v_dual_max_num_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xd4,0xc8,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v2, v2 :: v_dual_max_num_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xd4,0xc8,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v3, v2 :: v_dual_max_num_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xd4,0xc8,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s105, v2 :: v_dual_max_num_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xd4,0xc8,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s1, v2 :: v_dual_max_num_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xd4,0xc8,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, ttmp15, v2 :: v_dual_max_num_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xd4,0xc8,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_hi, v2 :: v_dual_max_num_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xd4,0xc8,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_lo, v2 :: v_dual_max_num_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xd4,0xc8,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, m0, v2 :: v_dual_max_num_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xd4,0xc8,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_hi, v2 :: v_dual_max_num_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xd4,0xc8,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_lo, v2 :: v_dual_max_num_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xd4,0xc8,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0xaf123456, v2 :: v_dual_max_num_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xd4,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, src_scc, v2 :: v_dual_max_num_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xd4,0xc8,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0.5, v3 :: v_dual_max_num_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xd4,0xc8,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, -1, v4 :: v_dual_max_num_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xd4,0xc8,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v6, null, v5 :: v_dual_max_num_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xd4,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v4, v2 :: v_dual_min_num_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xd6,0xc8,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v1, v2 :: v_dual_min_num_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xd6,0xc8,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v255, v2 :: v_dual_min_num_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xd6,0xc8,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v2, v2 :: v_dual_min_num_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xd6,0xc8,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v3, v2 :: v_dual_min_num_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xd6,0xc8,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s105, v2 :: v_dual_min_num_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xd6,0xc8,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s1, v2 :: v_dual_min_num_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xd6,0xc8,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, ttmp15, v2 :: v_dual_min_num_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xd6,0xc8,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_hi, v2 :: v_dual_min_num_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xd6,0xc8,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_lo, v2 :: v_dual_min_num_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xd6,0xc8,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, m0, v2 :: v_dual_min_num_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xd6,0xc8,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_hi, v2 :: v_dual_min_num_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xd6,0xc8,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_lo, v2 :: v_dual_min_num_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xd6,0xc8,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0xaf123456, v2 :: v_dual_min_num_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xd6,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, src_scc, v2 :: v_dual_min_num_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xd6,0xc8,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0.5, v3 :: v_dual_min_num_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xd6,0xc8,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, -1, v4 :: v_dual_min_num_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xd6,0xc8,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v6, null, v5 :: v_dual_min_num_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xd6,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v4, v255 :: v_dual_mov_b32 v6, v1
+// GFX12: encoding: [0x04,0xff,0xd1,0xc8,0x01,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v1, v255 :: v_dual_mov_b32 v6, v255
+// GFX12: encoding: [0x01,0xff,0xd1,0xc8,0xff,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v255, v255 :: v_dual_mov_b32 v6, v2
+// GFX12: encoding: [0xff,0xff,0xd1,0xc8,0x02,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v2, v255 :: v_dual_mov_b32 v6, v3
+// GFX12: encoding: [0x02,0xff,0xd1,0xc8,0x03,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v3, v255 :: v_dual_mov_b32 v6, v4
+// GFX12: encoding: [0x03,0xff,0xd1,0xc8,0x04,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s105, v255 :: v_dual_mov_b32 v6, s1
+// GFX12: encoding: [0x69,0xfe,0xd1,0xc8,0x01,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s1, v255 :: v_dual_mov_b32 v6, s105
+// GFX12: encoding: [0x01,0xfe,0xd1,0xc8,0x69,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, ttmp15, v255 :: v_dual_mov_b32 v6, vcc_lo
+// GFX12: encoding: [0x7b,0xfe,0xd1,0xc8,0x6a,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_hi, v255 :: v_dual_mov_b32 v6, vcc_hi
+// GFX12: encoding: [0x7f,0xfe,0xd1,0xc8,0x6b,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_lo, v255 :: v_dual_mov_b32 v6, ttmp15
+// GFX12: encoding: [0x7e,0xfe,0xd1,0xc8,0x7b,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, m0, v255 :: v_dual_mov_b32 v6, m0
+// GFX12: encoding: [0x7d,0xfe,0xd1,0xc8,0x7d,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_hi, v255 :: v_dual_mov_b32 v6, exec_lo
+// GFX12: encoding: [0x6b,0xfe,0xd1,0xc8,0x7e,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_lo, v255 :: v_dual_mov_b32 v6, exec_hi
+// GFX12: encoding: [0x6a,0xfe,0xd1,0xc8,0x7f,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0xaf123456, v255 :: v_dual_mov_b32 v6, null
+// GFX12: encoding: [0xff,0xfe,0xd1,0xc8,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, src_scc, v255 :: v_dual_mov_b32 v6, -1
+// GFX12: encoding: [0xfd,0xfe,0xd1,0xc8,0xc1,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0.5, v3 :: v_dual_mov_b32 v6, 0.5
+// GFX12: encoding: [0xf0,0x06,0xd0,0xc8,0xf0,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, -1, v4 :: v_dual_mov_b32 v6, src_scc
+// GFX12: encoding: [0xc1,0x08,0xd0,0xc8,0xfd,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v6, null, v5 :: v_dual_mov_b32 v255, 0xaf123456
+// GFX12: encoding: [0x7c,0x0a,0xd0,0xc8,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v4, v2 :: v_dual_mul_dx9_zero_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xce,0xc8,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v1, v2 :: v_dual_mul_dx9_zero_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xce,0xc8,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v255, v2 :: v_dual_mul_dx9_zero_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xce,0xc8,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v2, v2 :: v_dual_mul_dx9_zero_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xce,0xc8,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v3, v2 :: v_dual_mul_dx9_zero_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xce,0xc8,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s105, v2 :: v_dual_mul_dx9_zero_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xce,0xc8,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s1, v2 :: v_dual_mul_dx9_zero_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xce,0xc8,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, ttmp15, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xce,0xc8,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xce,0xc8,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xce,0xc8,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, m0, v2 :: v_dual_mul_dx9_zero_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xce,0xc8,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xce,0xc8,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xce,0xc8,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0xaf123456, v2 :: v_dual_mul_dx9_zero_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xce,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, src_scc, v2 :: v_dual_mul_dx9_zero_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xce,0xc8,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0.5, v3 :: v_dual_mul_dx9_zero_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xce,0xc8,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, -1, v4 :: v_dual_mul_dx9_zero_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xce,0xc8,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v6, null, v5 :: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xce,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v4, v2 :: v_dual_mul_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xc6,0xc8,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v1, v2 :: v_dual_mul_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xc6,0xc8,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v255, v2 :: v_dual_mul_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xc6,0xc8,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v2, v2 :: v_dual_mul_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xc6,0xc8,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v3, v2 :: v_dual_mul_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xc6,0xc8,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s105, v2 :: v_dual_mul_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xc6,0xc8,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s1, v2 :: v_dual_mul_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xc6,0xc8,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, ttmp15, v2 :: v_dual_mul_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xc6,0xc8,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_hi, v2 :: v_dual_mul_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xc6,0xc8,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_lo, v2 :: v_dual_mul_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xc6,0xc8,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, m0, v2 :: v_dual_mul_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xc6,0xc8,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_hi, v2 :: v_dual_mul_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xc6,0xc8,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_lo, v2 :: v_dual_mul_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xc6,0xc8,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0xaf123456, v2 :: v_dual_mul_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xc6,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, src_scc, v2 :: v_dual_mul_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xc6,0xc8,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0.5, v3 :: v_dual_mul_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xc6,0xc8,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, -1, v4 :: v_dual_mul_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xc6,0xc8,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v6, null, v5 :: v_dual_mul_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xc6,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v4, v2 :: v_dual_sub_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xca,0xc8,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v1, v2 :: v_dual_sub_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xca,0xc8,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v255, v2 :: v_dual_sub_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xca,0xc8,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v2, v2 :: v_dual_sub_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xca,0xc8,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v3, v2 :: v_dual_sub_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xca,0xc8,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s105, v2 :: v_dual_sub_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xca,0xc8,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s1, v2 :: v_dual_sub_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xca,0xc8,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, ttmp15, v2 :: v_dual_sub_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xca,0xc8,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_hi, v2 :: v_dual_sub_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xca,0xc8,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_lo, v2 :: v_dual_sub_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xca,0xc8,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, m0, v2 :: v_dual_sub_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xca,0xc8,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_hi, v2 :: v_dual_sub_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xca,0xc8,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_lo, v2 :: v_dual_sub_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xca,0xc8,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0xaf123456, v2 :: v_dual_sub_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xca,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, src_scc, v2 :: v_dual_sub_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xca,0xc8,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0.5, v3 :: v_dual_sub_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xca,0xc8,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, -1, v4 :: v_dual_sub_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xca,0xc8,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v6, null, v5 :: v_dual_sub_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xca,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v4, v2 :: v_dual_subrev_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xcc,0xc8,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v1, v2 :: v_dual_subrev_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xcc,0xc8,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v255, v2 :: v_dual_subrev_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xcc,0xc8,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v2, v2 :: v_dual_subrev_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xcc,0xc8,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, v3, v2 :: v_dual_subrev_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xcc,0xc8,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s105, v2 :: v_dual_subrev_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xcc,0xc8,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, s1, v2 :: v_dual_subrev_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xcc,0xc8,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, ttmp15, v2 :: v_dual_subrev_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xcc,0xc8,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_hi, v2 :: v_dual_subrev_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xcc,0xc8,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, exec_lo, v2 :: v_dual_subrev_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xcc,0xc8,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, m0, v2 :: v_dual_subrev_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xcc,0xc8,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_hi, v2 :: v_dual_subrev_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xcc,0xc8,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, vcc_lo, v2 :: v_dual_subrev_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xcc,0xc8,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0xaf123456, v2 :: v_dual_subrev_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xcc,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, src_scc, v2 :: v_dual_subrev_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xcc,0xc8,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, 0.5, v3 :: v_dual_subrev_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xcc,0xc8,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v255, -1, v4 :: v_dual_subrev_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xcc,0xc8,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_mul_f32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xcc,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v4, v2 :: v_dual_add_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x48,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v1, v2 :: v_dual_add_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x48,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v255, v2 :: v_dual_add_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x48,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v2, v2 :: v_dual_add_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x48,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v3, v2 :: v_dual_add_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x48,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s105, v2 :: v_dual_add_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x48,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s1, v2 :: v_dual_add_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x48,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, ttmp15, v2 :: v_dual_add_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x48,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_hi, v2 :: v_dual_add_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x48,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_lo, v2 :: v_dual_add_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x48,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, m0, v2 :: v_dual_add_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x48,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_hi, v2 :: v_dual_add_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x48,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_lo, v2 :: v_dual_add_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x48,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0xaf123456, v2 :: v_dual_add_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x48,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, src_scc, v2 :: v_dual_add_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x48,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0.5, v3 :: v_dual_add_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x48,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, -1, v4 :: v_dual_add_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x48,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v6, null, v5 :: v_dual_add_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x48,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v4, v2 :: v_dual_add_nc_u32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x60,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v1, v2 :: v_dual_add_nc_u32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x60,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v255, v2 :: v_dual_add_nc_u32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x60,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v2, v2 :: v_dual_add_nc_u32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x60,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v3, v2 :: v_dual_add_nc_u32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x60,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s105, v2 :: v_dual_add_nc_u32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x60,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s1, v2 :: v_dual_add_nc_u32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x60,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, ttmp15, v2 :: v_dual_add_nc_u32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x60,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_hi, v2 :: v_dual_add_nc_u32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x60,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_lo, v2 :: v_dual_add_nc_u32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x60,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, m0, v2 :: v_dual_add_nc_u32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x60,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_hi, v2 :: v_dual_add_nc_u32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x60,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_lo, v2 :: v_dual_add_nc_u32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x60,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0xaf123456, v2 :: v_dual_add_nc_u32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x60,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, src_scc, v2 :: v_dual_add_nc_u32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x60,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0.5, v3 :: v_dual_add_nc_u32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x60,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, -1, v4 :: v_dual_add_nc_u32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x60,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v6, null, v5 :: v_dual_add_nc_u32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x60,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v4, v2 :: v_dual_and_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x64,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v1, v2 :: v_dual_and_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x64,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v255, v2 :: v_dual_and_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x64,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v2, v2 :: v_dual_and_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x64,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v3, v2 :: v_dual_and_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x64,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s105, v2 :: v_dual_and_b32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x64,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s1, v2 :: v_dual_and_b32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x64,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, ttmp15, v2 :: v_dual_and_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x64,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_hi, v2 :: v_dual_and_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x64,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_lo, v2 :: v_dual_and_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x64,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, m0, v2 :: v_dual_and_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x64,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_hi, v2 :: v_dual_and_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x64,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_lo, v2 :: v_dual_and_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x64,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0xaf123456, v2 :: v_dual_and_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x64,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, src_scc, v2 :: v_dual_and_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x64,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0.5, v3 :: v_dual_and_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x64,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, -1, v4 :: v_dual_and_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x64,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v6, null, v5 :: v_dual_and_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x64,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v4, v2 :: v_dual_cndmask_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x52,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v1, v2 :: v_dual_cndmask_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x52,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v255, v2 :: v_dual_cndmask_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x52,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v2, v2 :: v_dual_cndmask_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x52,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v3, v2 :: v_dual_cndmask_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x52,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s105, v2 :: v_dual_cndmask_b32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x52,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s1, v2 :: v_dual_cndmask_b32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x52,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, ttmp15, v2 :: v_dual_cndmask_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0x52,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_hi, v2 :: v_dual_cndmask_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x52,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_lo, v2 :: v_dual_cndmask_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0x52,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, m0, v2 :: v_dual_cndmask_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x52,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_hi, v2 :: v_dual_cndmask_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0x52,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_lo, v2 :: v_dual_cndmask_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0x52,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0xaf123456, v2 :: v_dual_cndmask_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x52,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, src_scc, v2 :: v_dual_cndmask_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x52,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0.5, v3 :: v_dual_cndmask_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x52,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, -1, v4 :: v_dual_cndmask_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x52,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v6, null, v5 :: v_dual_cndmask_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x52,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v4, v2 :: v_dual_fmaak_f32 v6, v1, v3, 0xaf123456
+// GFX12: encoding: [0x04,0x05,0x42,0xc9,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v1, v2 :: v_dual_fmaak_f32 v6, v255, v3, 0xaf123456
+// GFX12: encoding: [0x01,0x05,0x42,0xc9,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v255, v2 :: v_dual_fmaak_f32 v6, v2, v3, 0xaf123456
+// GFX12: encoding: [0xff,0x05,0x42,0xc9,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v2, v2 :: v_dual_fmaak_f32 v6, v3, v3, 0xaf123456
+// GFX12: encoding: [0x02,0x05,0x42,0xc9,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v3, v2 :: v_dual_fmaak_f32 v6, v4, v3, 0xaf123456
+// GFX12: encoding: [0x03,0x05,0x42,0xc9,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s105, v2 :: v_dual_fmaak_f32 v6, s105, v3, 0xaf123456
+// GFX12: encoding: [0x69,0x04,0x42,0xc9,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s1, v2 :: v_dual_fmaak_f32 v6, s1, v3, 0xaf123456
+// GFX12: encoding: [0x01,0x04,0x42,0xc9,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, ttmp15, v2 :: v_dual_fmaak_f32 v6, ttmp15, v3, 0xaf123456
+// GFX12: encoding: [0x7b,0x04,0x42,0xc9,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_hi, v2 :: v_dual_fmaak_f32 v6, exec_hi, v3, 0xaf123456
+// GFX12: encoding: [0x7f,0x04,0x42,0xc9,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_lo, v2 :: v_dual_fmaak_f32 v6, exec_lo, v3, 0xaf123456
+// GFX12: encoding: [0x7e,0x04,0x42,0xc9,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, m0, v2 :: v_dual_fmaak_f32 v6, m0, v3, 0xaf123456
+// GFX12: encoding: [0x7d,0x04,0x42,0xc9,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_hi, v2 :: v_dual_fmaak_f32 v6, vcc_hi, v3, 0xaf123456
+// GFX12: encoding: [0x6b,0x04,0x42,0xc9,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_lo, v2 :: v_dual_fmaak_f32 v6, vcc_lo, v3, 0xaf123456
+// GFX12: encoding: [0x6a,0x04,0x42,0xc9,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, null, v3, 0xaf123456
+// GFX12: encoding: [0xff,0x04,0x42,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, src_scc, v2 :: v_dual_fmaak_f32 v6, -1, v3, 0xaf123456
+// GFX12: encoding: [0xfd,0x04,0x42,0xc9,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0.5, v3 :: v_dual_fmaak_f32 v6, 0.5, v2, 0xaf123456
+// GFX12: encoding: [0xf0,0x06,0x42,0xc9,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, -1, v4 :: v_dual_fmaak_f32 v6, src_scc, v5, 0xaf123456
+// GFX12: encoding: [0xc1,0x08,0x42,0xc9,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v6, null, v5 :: v_dual_fmaak_f32 v255, 0xaf123456, v4, 0xaf123456
+// GFX12: encoding: [0x7c,0x0a,0x42,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v4, v2 :: v_dual_fmac_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x40,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v1, v2 :: v_dual_fmac_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x40,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v255, v2 :: v_dual_fmac_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x40,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v2, v2 :: v_dual_fmac_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x40,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v3, v2 :: v_dual_fmac_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x40,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s105, v2 :: v_dual_fmac_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x40,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s1, v2 :: v_dual_fmac_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x40,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, ttmp15, v2 :: v_dual_fmac_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x40,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_hi, v2 :: v_dual_fmac_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x40,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_lo, v2 :: v_dual_fmac_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x40,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, m0, v2 :: v_dual_fmac_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x40,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_hi, v2 :: v_dual_fmac_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x40,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_lo, v2 :: v_dual_fmac_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x40,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0xaf123456, v2 :: v_dual_fmac_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x40,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, src_scc, v2 :: v_dual_fmac_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x40,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0.5, v3 :: v_dual_fmac_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x40,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, -1, v4 :: v_dual_fmac_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x40,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v6, null, v5 :: v_dual_fmac_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x40,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v4, v255 :: v_dual_fmamk_f32 v6, v1, 0xaf123456, v255
+// GFX12: encoding: [0x04,0xff,0x45,0xc9,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v1, v255 :: v_dual_fmamk_f32 v6, v255, 0xaf123456, v255
+// GFX12: encoding: [0x01,0xff,0x45,0xc9,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v255, v255 :: v_dual_fmamk_f32 v6, v2, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xff,0x45,0xc9,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v2, v255 :: v_dual_fmamk_f32 v6, v3, 0xaf123456, v255
+// GFX12: encoding: [0x02,0xff,0x45,0xc9,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v3, v255 :: v_dual_fmamk_f32 v6, v4, 0xaf123456, v255
+// GFX12: encoding: [0x03,0xff,0x45,0xc9,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s105, v255 :: v_dual_fmamk_f32 v6, s105, 0xaf123456, v255
+// GFX12: encoding: [0x69,0xfe,0x45,0xc9,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s1, v255 :: v_dual_fmamk_f32 v6, s1, 0xaf123456, v255
+// GFX12: encoding: [0x01,0xfe,0x45,0xc9,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, ttmp15, v255 :: v_dual_fmamk_f32 v6, ttmp15, 0xaf123456, v255
+// GFX12: encoding: [0x7b,0xfe,0x45,0xc9,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_hi, v255 :: v_dual_fmamk_f32 v6, exec_hi, 0xaf123456, v255
+// GFX12: encoding: [0x7f,0xfe,0x45,0xc9,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_lo, v255 :: v_dual_fmamk_f32 v6, exec_lo, 0xaf123456, v255
+// GFX12: encoding: [0x7e,0xfe,0x45,0xc9,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, m0, v255 :: v_dual_fmamk_f32 v6, m0, 0xaf123456, v255
+// GFX12: encoding: [0x7d,0xfe,0x45,0xc9,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_hi, v255 :: v_dual_fmamk_f32 v6, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x6b,0xfe,0x45,0xc9,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_lo, v255 :: v_dual_fmamk_f32 v6, vcc_lo, 0xaf123456, v255
+// GFX12: encoding: [0x6a,0xfe,0x45,0xc9,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, null, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x45,0xc9,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, src_scc, v255 :: v_dual_fmamk_f32 v6, -1, 0xaf123456, v255
+// GFX12: encoding: [0xfd,0xfe,0x45,0xc9,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0.5, v3 :: v_dual_fmamk_f32 v6, 0.5, 0xaf123456, v255
+// GFX12: encoding: [0xf0,0x06,0x44,0xc9,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, -1, v4 :: v_dual_fmamk_f32 v6, src_scc, 0xaf123456, v255
+// GFX12: encoding: [0xc1,0x08,0x44,0xc9,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v6, null, v5 :: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x44,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v4, v2 :: v_dual_lshlrev_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x62,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v1, v2 :: v_dual_lshlrev_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x62,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v255, v2 :: v_dual_lshlrev_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x62,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v2, v2 :: v_dual_lshlrev_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x62,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v3, v2 :: v_dual_lshlrev_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x62,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s105, v2 :: v_dual_lshlrev_b32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x62,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s1, v2 :: v_dual_lshlrev_b32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x62,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, ttmp15, v2 :: v_dual_lshlrev_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x62,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_hi, v2 :: v_dual_lshlrev_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x62,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_lo, v2 :: v_dual_lshlrev_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x62,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, m0, v2 :: v_dual_lshlrev_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x62,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_hi, v2 :: v_dual_lshlrev_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x62,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_lo, v2 :: v_dual_lshlrev_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x62,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0xaf123456, v2 :: v_dual_lshlrev_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x62,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, src_scc, v2 :: v_dual_lshlrev_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x62,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0.5, v3 :: v_dual_lshlrev_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x62,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, -1, v4 :: v_dual_lshlrev_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x62,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v6, null, v5 :: v_dual_lshlrev_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x62,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v4, v2 :: v_dual_max_num_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x54,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v1, v2 :: v_dual_max_num_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x54,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v255, v2 :: v_dual_max_num_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x54,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v2, v2 :: v_dual_max_num_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x54,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v3, v2 :: v_dual_max_num_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x54,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s105, v2 :: v_dual_max_num_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x54,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s1, v2 :: v_dual_max_num_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x54,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, ttmp15, v2 :: v_dual_max_num_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x54,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_hi, v2 :: v_dual_max_num_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x54,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_lo, v2 :: v_dual_max_num_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x54,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, m0, v2 :: v_dual_max_num_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x54,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_hi, v2 :: v_dual_max_num_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x54,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_lo, v2 :: v_dual_max_num_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x54,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0xaf123456, v2 :: v_dual_max_num_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x54,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, src_scc, v2 :: v_dual_max_num_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x54,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0.5, v3 :: v_dual_max_num_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x54,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, -1, v4 :: v_dual_max_num_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x54,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v6, null, v5 :: v_dual_max_num_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x54,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v4, v2 :: v_dual_min_num_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x56,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v1, v2 :: v_dual_min_num_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x56,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v255, v2 :: v_dual_min_num_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x56,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v2, v2 :: v_dual_min_num_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x56,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v3, v2 :: v_dual_min_num_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x56,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s105, v2 :: v_dual_min_num_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x56,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s1, v2 :: v_dual_min_num_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x56,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, ttmp15, v2 :: v_dual_min_num_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x56,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_hi, v2 :: v_dual_min_num_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x56,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_lo, v2 :: v_dual_min_num_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x56,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, m0, v2 :: v_dual_min_num_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x56,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_hi, v2 :: v_dual_min_num_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x56,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_lo, v2 :: v_dual_min_num_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x56,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0xaf123456, v2 :: v_dual_min_num_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x56,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, src_scc, v2 :: v_dual_min_num_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x56,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0.5, v3 :: v_dual_min_num_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x56,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, -1, v4 :: v_dual_min_num_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x56,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v6, null, v5 :: v_dual_min_num_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x56,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v4, v255 :: v_dual_mov_b32 v6, v1
+// GFX12: encoding: [0x04,0xff,0x51,0xc9,0x01,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v1, v255 :: v_dual_mov_b32 v6, v255
+// GFX12: encoding: [0x01,0xff,0x51,0xc9,0xff,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v255, v255 :: v_dual_mov_b32 v6, v2
+// GFX12: encoding: [0xff,0xff,0x51,0xc9,0x02,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v2, v255 :: v_dual_mov_b32 v6, v3
+// GFX12: encoding: [0x02,0xff,0x51,0xc9,0x03,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v3, v255 :: v_dual_mov_b32 v6, v4
+// GFX12: encoding: [0x03,0xff,0x51,0xc9,0x04,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s105, v255 :: v_dual_mov_b32 v6, s1
+// GFX12: encoding: [0x69,0xfe,0x51,0xc9,0x01,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s1, v255 :: v_dual_mov_b32 v6, s105
+// GFX12: encoding: [0x01,0xfe,0x51,0xc9,0x69,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, ttmp15, v255 :: v_dual_mov_b32 v6, vcc_lo
+// GFX12: encoding: [0x7b,0xfe,0x51,0xc9,0x6a,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_hi, v255 :: v_dual_mov_b32 v6, vcc_hi
+// GFX12: encoding: [0x7f,0xfe,0x51,0xc9,0x6b,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_lo, v255 :: v_dual_mov_b32 v6, ttmp15
+// GFX12: encoding: [0x7e,0xfe,0x51,0xc9,0x7b,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, m0, v255 :: v_dual_mov_b32 v6, m0
+// GFX12: encoding: [0x7d,0xfe,0x51,0xc9,0x7d,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_hi, v255 :: v_dual_mov_b32 v6, exec_lo
+// GFX12: encoding: [0x6b,0xfe,0x51,0xc9,0x7e,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_lo, v255 :: v_dual_mov_b32 v6, exec_hi
+// GFX12: encoding: [0x6a,0xfe,0x51,0xc9,0x7f,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0xaf123456, v255 :: v_dual_mov_b32 v6, null
+// GFX12: encoding: [0xff,0xfe,0x51,0xc9,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, src_scc, v255 :: v_dual_mov_b32 v6, -1
+// GFX12: encoding: [0xfd,0xfe,0x51,0xc9,0xc1,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0.5, v3 :: v_dual_mov_b32 v6, 0.5
+// GFX12: encoding: [0xf0,0x06,0x50,0xc9,0xf0,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, -1, v4 :: v_dual_mov_b32 v6, src_scc
+// GFX12: encoding: [0xc1,0x08,0x50,0xc9,0xfd,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v6, null, v5 :: v_dual_mov_b32 v255, 0xaf123456
+// GFX12: encoding: [0x7c,0x0a,0x50,0xc9,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v4, v2 :: v_dual_mul_dx9_zero_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x4e,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v1, v2 :: v_dual_mul_dx9_zero_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x4e,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v255, v2 :: v_dual_mul_dx9_zero_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x4e,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v2, v2 :: v_dual_mul_dx9_zero_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x4e,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v3, v2 :: v_dual_mul_dx9_zero_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x4e,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s105, v2 :: v_dual_mul_dx9_zero_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x4e,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s1, v2 :: v_dual_mul_dx9_zero_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x4e,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, ttmp15, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x4e,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x4e,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x4e,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, m0, v2 :: v_dual_mul_dx9_zero_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x4e,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x4e,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x4e,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0xaf123456, v2 :: v_dual_mul_dx9_zero_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x4e,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, src_scc, v2 :: v_dual_mul_dx9_zero_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x4e,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0.5, v3 :: v_dual_mul_dx9_zero_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x4e,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, -1, v4 :: v_dual_mul_dx9_zero_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x4e,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v6, null, v5 :: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x4e,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v4, v2 :: v_dual_mul_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x46,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v1, v2 :: v_dual_mul_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x46,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v255, v2 :: v_dual_mul_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x46,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v2, v2 :: v_dual_mul_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x46,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v3, v2 :: v_dual_mul_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x46,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s105, v2 :: v_dual_mul_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x46,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s1, v2 :: v_dual_mul_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x46,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, ttmp15, v2 :: v_dual_mul_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x46,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_hi, v2 :: v_dual_mul_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x46,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_lo, v2 :: v_dual_mul_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x46,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, m0, v2 :: v_dual_mul_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x46,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_hi, v2 :: v_dual_mul_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x46,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_lo, v2 :: v_dual_mul_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x46,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0xaf123456, v2 :: v_dual_mul_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x46,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, src_scc, v2 :: v_dual_mul_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x46,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0.5, v3 :: v_dual_mul_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x46,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, -1, v4 :: v_dual_mul_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x46,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v6, null, v5 :: v_dual_mul_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x46,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v4, v2 :: v_dual_sub_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x4a,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v1, v2 :: v_dual_sub_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x4a,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v255, v2 :: v_dual_sub_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x4a,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v2, v2 :: v_dual_sub_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x4a,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v3, v2 :: v_dual_sub_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x4a,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s105, v2 :: v_dual_sub_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x4a,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s1, v2 :: v_dual_sub_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x4a,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, ttmp15, v2 :: v_dual_sub_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x4a,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_hi, v2 :: v_dual_sub_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x4a,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_lo, v2 :: v_dual_sub_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x4a,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, m0, v2 :: v_dual_sub_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x4a,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_hi, v2 :: v_dual_sub_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x4a,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_lo, v2 :: v_dual_sub_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x4a,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0xaf123456, v2 :: v_dual_sub_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x4a,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, src_scc, v2 :: v_dual_sub_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x4a,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0.5, v3 :: v_dual_sub_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x4a,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, -1, v4 :: v_dual_sub_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x4a,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v6, null, v5 :: v_dual_sub_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x4a,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v4, v2 :: v_dual_subrev_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x4c,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v1, v2 :: v_dual_subrev_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x4c,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v255, v2 :: v_dual_subrev_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x4c,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v2, v2 :: v_dual_subrev_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x4c,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, v3, v2 :: v_dual_subrev_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x4c,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s105, v2 :: v_dual_subrev_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x4c,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, s1, v2 :: v_dual_subrev_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x4c,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, ttmp15, v2 :: v_dual_subrev_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x4c,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_hi, v2 :: v_dual_subrev_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x4c,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, exec_lo, v2 :: v_dual_subrev_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x4c,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, m0, v2 :: v_dual_subrev_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x4c,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_hi, v2 :: v_dual_subrev_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x4c,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, vcc_lo, v2 :: v_dual_subrev_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x4c,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0xaf123456, v2 :: v_dual_subrev_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x4c,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, src_scc, v2 :: v_dual_subrev_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x4c,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, 0.5, v3 :: v_dual_subrev_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x4c,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v255, -1, v4 :: v_dual_subrev_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x4c,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_sub_f32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x4c,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v4, v2 :: v_dual_add_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x88,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v1, v2 :: v_dual_add_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x88,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v255, v2 :: v_dual_add_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x88,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v2, v2 :: v_dual_add_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x88,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v3, v2 :: v_dual_add_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x88,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s105, v2 :: v_dual_add_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x88,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s1, v2 :: v_dual_add_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x88,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, ttmp15, v2 :: v_dual_add_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x88,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_hi, v2 :: v_dual_add_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x88,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_lo, v2 :: v_dual_add_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x88,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, m0, v2 :: v_dual_add_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x88,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_hi, v2 :: v_dual_add_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x88,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_lo, v2 :: v_dual_add_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x88,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0xaf123456, v2 :: v_dual_add_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x88,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, src_scc, v2 :: v_dual_add_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x88,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_add_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x88,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, -1, v4 :: v_dual_add_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x88,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v6, null, v5 :: v_dual_add_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x88,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v4, v2 :: v_dual_add_nc_u32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xa0,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v1, v2 :: v_dual_add_nc_u32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xa0,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v255, v2 :: v_dual_add_nc_u32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xa0,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v2, v2 :: v_dual_add_nc_u32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xa0,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v3, v2 :: v_dual_add_nc_u32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xa0,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s105, v2 :: v_dual_add_nc_u32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xa0,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s1, v2 :: v_dual_add_nc_u32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xa0,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, ttmp15, v2 :: v_dual_add_nc_u32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xa0,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_hi, v2 :: v_dual_add_nc_u32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xa0,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_lo, v2 :: v_dual_add_nc_u32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xa0,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, m0, v2 :: v_dual_add_nc_u32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xa0,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_hi, v2 :: v_dual_add_nc_u32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xa0,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_lo, v2 :: v_dual_add_nc_u32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xa0,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0xaf123456, v2 :: v_dual_add_nc_u32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xa0,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, src_scc, v2 :: v_dual_add_nc_u32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xa0,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_add_nc_u32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xa0,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, -1, v4 :: v_dual_add_nc_u32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xa0,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v6, null, v5 :: v_dual_add_nc_u32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xa0,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v4, v2 :: v_dual_and_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xa4,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v1, v2 :: v_dual_and_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xa4,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v255, v2 :: v_dual_and_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xa4,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v2, v2 :: v_dual_and_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xa4,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v3, v2 :: v_dual_and_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xa4,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s105, v2 :: v_dual_and_b32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xa4,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s1, v2 :: v_dual_and_b32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xa4,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, ttmp15, v2 :: v_dual_and_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xa4,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_hi, v2 :: v_dual_and_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xa4,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_lo, v2 :: v_dual_and_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xa4,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, m0, v2 :: v_dual_and_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xa4,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_hi, v2 :: v_dual_and_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xa4,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_lo, v2 :: v_dual_and_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xa4,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0xaf123456, v2 :: v_dual_and_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xa4,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, src_scc, v2 :: v_dual_and_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xa4,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_and_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xa4,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, -1, v4 :: v_dual_and_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xa4,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v6, null, v5 :: v_dual_and_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xa4,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v4, v2 :: v_dual_cndmask_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x92,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v1, v2 :: v_dual_cndmask_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x92,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v255, v2 :: v_dual_cndmask_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x92,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v2, v2 :: v_dual_cndmask_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x92,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v3, v2 :: v_dual_cndmask_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x92,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s105, v2 :: v_dual_cndmask_b32 v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x92,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s1, v2 :: v_dual_cndmask_b32 v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x92,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, ttmp15, v2 :: v_dual_cndmask_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7b,0x04,0x92,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_hi, v2 :: v_dual_cndmask_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x92,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_lo, v2 :: v_dual_cndmask_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x7e,0x04,0x92,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, m0, v2 :: v_dual_cndmask_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x92,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_hi, v2 :: v_dual_cndmask_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x6b,0x04,0x92,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_lo, v2 :: v_dual_cndmask_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x6a,0x04,0x92,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0xaf123456, v2 :: v_dual_cndmask_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x92,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, src_scc, v2 :: v_dual_cndmask_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x92,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_cndmask_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x92,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, -1, v4 :: v_dual_cndmask_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x92,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v6, null, v5 :: v_dual_cndmask_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x92,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v4, v2 :: v_dual_fmaak_f32 v6, v1, v3, 0xaf123456
+// GFX12: encoding: [0x04,0x05,0x82,0xc9,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v1, v2 :: v_dual_fmaak_f32 v6, v255, v3, 0xaf123456
+// GFX12: encoding: [0x01,0x05,0x82,0xc9,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v255, v2 :: v_dual_fmaak_f32 v6, v2, v3, 0xaf123456
+// GFX12: encoding: [0xff,0x05,0x82,0xc9,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v2, v2 :: v_dual_fmaak_f32 v6, v3, v3, 0xaf123456
+// GFX12: encoding: [0x02,0x05,0x82,0xc9,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v3, v2 :: v_dual_fmaak_f32 v6, v4, v3, 0xaf123456
+// GFX12: encoding: [0x03,0x05,0x82,0xc9,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s105, v2 :: v_dual_fmaak_f32 v6, s105, v3, 0xaf123456
+// GFX12: encoding: [0x69,0x04,0x82,0xc9,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s1, v2 :: v_dual_fmaak_f32 v6, s1, v3, 0xaf123456
+// GFX12: encoding: [0x01,0x04,0x82,0xc9,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, ttmp15, v2 :: v_dual_fmaak_f32 v6, ttmp15, v3, 0xaf123456
+// GFX12: encoding: [0x7b,0x04,0x82,0xc9,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_hi, v2 :: v_dual_fmaak_f32 v6, exec_hi, v3, 0xaf123456
+// GFX12: encoding: [0x7f,0x04,0x82,0xc9,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_lo, v2 :: v_dual_fmaak_f32 v6, exec_lo, v3, 0xaf123456
+// GFX12: encoding: [0x7e,0x04,0x82,0xc9,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, m0, v2 :: v_dual_fmaak_f32 v6, m0, v3, 0xaf123456
+// GFX12: encoding: [0x7d,0x04,0x82,0xc9,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_hi, v2 :: v_dual_fmaak_f32 v6, vcc_hi, v3, 0xaf123456
+// GFX12: encoding: [0x6b,0x04,0x82,0xc9,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_lo, v2 :: v_dual_fmaak_f32 v6, vcc_lo, v3, 0xaf123456
+// GFX12: encoding: [0x6a,0x04,0x82,0xc9,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, null, v3, 0xaf123456
+// GFX12: encoding: [0xff,0x04,0x82,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, src_scc, v2 :: v_dual_fmaak_f32 v6, -1, v3, 0xaf123456
+// GFX12: encoding: [0xfd,0x04,0x82,0xc9,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_fmaak_f32 v6, 0.5, v2, 0xaf123456
+// GFX12: encoding: [0xf0,0x06,0x82,0xc9,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, -1, v4 :: v_dual_fmaak_f32 v6, src_scc, v5, 0xaf123456
+// GFX12: encoding: [0xc1,0x08,0x82,0xc9,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v6, null, v5 :: v_dual_fmaak_f32 v255, 0xaf123456, v4, 0xaf123456
+// GFX12: encoding: [0x7c,0x0a,0x82,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v4, v2 :: v_dual_fmac_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x80,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v1, v2 :: v_dual_fmac_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x80,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v255, v2 :: v_dual_fmac_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x80,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v2, v2 :: v_dual_fmac_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x80,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v3, v2 :: v_dual_fmac_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x80,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s105, v2 :: v_dual_fmac_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x80,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s1, v2 :: v_dual_fmac_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x80,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, ttmp15, v2 :: v_dual_fmac_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x80,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_hi, v2 :: v_dual_fmac_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x80,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_lo, v2 :: v_dual_fmac_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x80,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, m0, v2 :: v_dual_fmac_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x80,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_hi, v2 :: v_dual_fmac_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x80,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_lo, v2 :: v_dual_fmac_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x80,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0xaf123456, v2 :: v_dual_fmac_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x80,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, src_scc, v2 :: v_dual_fmac_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x80,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_fmac_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x80,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, -1, v4 :: v_dual_fmac_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x80,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v6, null, v5 :: v_dual_fmac_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x80,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v4, v255 :: v_dual_fmamk_f32 v6, v1, 0xaf123456, v255
+// GFX12: encoding: [0x04,0xff,0x85,0xc9,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v1, v255 :: v_dual_fmamk_f32 v6, v255, 0xaf123456, v255
+// GFX12: encoding: [0x01,0xff,0x85,0xc9,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v255, v255 :: v_dual_fmamk_f32 v6, v2, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xff,0x85,0xc9,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v2, v255 :: v_dual_fmamk_f32 v6, v3, 0xaf123456, v255
+// GFX12: encoding: [0x02,0xff,0x85,0xc9,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v3, v255 :: v_dual_fmamk_f32 v6, v4, 0xaf123456, v255
+// GFX12: encoding: [0x03,0xff,0x85,0xc9,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s105, v255 :: v_dual_fmamk_f32 v6, s105, 0xaf123456, v255
+// GFX12: encoding: [0x69,0xfe,0x85,0xc9,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s1, v255 :: v_dual_fmamk_f32 v6, s1, 0xaf123456, v255
+// GFX12: encoding: [0x01,0xfe,0x85,0xc9,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, ttmp15, v255 :: v_dual_fmamk_f32 v6, ttmp15, 0xaf123456, v255
+// GFX12: encoding: [0x7b,0xfe,0x85,0xc9,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_hi, v255 :: v_dual_fmamk_f32 v6, exec_hi, 0xaf123456, v255
+// GFX12: encoding: [0x7f,0xfe,0x85,0xc9,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_lo, v255 :: v_dual_fmamk_f32 v6, exec_lo, 0xaf123456, v255
+// GFX12: encoding: [0x7e,0xfe,0x85,0xc9,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, m0, v255 :: v_dual_fmamk_f32 v6, m0, 0xaf123456, v255
+// GFX12: encoding: [0x7d,0xfe,0x85,0xc9,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_hi, v255 :: v_dual_fmamk_f32 v6, vcc_hi, 0xaf123456, v255
+// GFX12: encoding: [0x6b,0xfe,0x85,0xc9,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_lo, v255 :: v_dual_fmamk_f32 v6, vcc_lo, 0xaf123456, v255
+// GFX12: encoding: [0x6a,0xfe,0x85,0xc9,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, null, 0xaf123456, v255
+// GFX12: encoding: [0xff,0xfe,0x85,0xc9,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, src_scc, v255 :: v_dual_fmamk_f32 v6, -1, 0xaf123456, v255
+// GFX12: encoding: [0xfd,0xfe,0x85,0xc9,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_fmamk_f32 v6, 0.5, 0xaf123456, v255
+// GFX12: encoding: [0xf0,0x06,0x84,0xc9,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, -1, v4 :: v_dual_fmamk_f32 v6, src_scc, 0xaf123456, v255
+// GFX12: encoding: [0xc1,0x08,0x84,0xc9,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v6, null, v5 :: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x84,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v4, v2 :: v_dual_lshlrev_b32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0xa2,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v1, v2 :: v_dual_lshlrev_b32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0xa2,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v255, v2 :: v_dual_lshlrev_b32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0xa2,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v2, v2 :: v_dual_lshlrev_b32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0xa2,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v3, v2 :: v_dual_lshlrev_b32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0xa2,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s105, v2 :: v_dual_lshlrev_b32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0xa2,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s1, v2 :: v_dual_lshlrev_b32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0xa2,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, ttmp15, v2 :: v_dual_lshlrev_b32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0xa2,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_hi, v2 :: v_dual_lshlrev_b32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0xa2,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_lo, v2 :: v_dual_lshlrev_b32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0xa2,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, m0, v2 :: v_dual_lshlrev_b32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0xa2,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_hi, v2 :: v_dual_lshlrev_b32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0xa2,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_lo, v2 :: v_dual_lshlrev_b32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0xa2,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0xaf123456, v2 :: v_dual_lshlrev_b32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0xa2,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, src_scc, v2 :: v_dual_lshlrev_b32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0xa2,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_lshlrev_b32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0xa2,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, -1, v4 :: v_dual_lshlrev_b32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0xa2,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v6, null, v5 :: v_dual_lshlrev_b32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0xa2,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v4, v2 :: v_dual_max_num_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x94,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v1, v2 :: v_dual_max_num_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x94,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v255, v2 :: v_dual_max_num_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x94,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v2, v2 :: v_dual_max_num_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x94,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v3, v2 :: v_dual_max_num_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x94,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s105, v2 :: v_dual_max_num_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x94,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s1, v2 :: v_dual_max_num_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x94,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, ttmp15, v2 :: v_dual_max_num_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x94,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_hi, v2 :: v_dual_max_num_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x94,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_lo, v2 :: v_dual_max_num_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x94,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, m0, v2 :: v_dual_max_num_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x94,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_hi, v2 :: v_dual_max_num_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x94,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_lo, v2 :: v_dual_max_num_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x94,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0xaf123456, v2 :: v_dual_max_num_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x94,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, src_scc, v2 :: v_dual_max_num_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x94,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_max_num_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x94,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, -1, v4 :: v_dual_max_num_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x94,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v6, null, v5 :: v_dual_max_num_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x94,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v4, v2 :: v_dual_min_num_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x96,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v1, v2 :: v_dual_min_num_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x96,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v255, v2 :: v_dual_min_num_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x96,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v2, v2 :: v_dual_min_num_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x96,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v3, v2 :: v_dual_min_num_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x96,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s105, v2 :: v_dual_min_num_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x96,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s1, v2 :: v_dual_min_num_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x96,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, ttmp15, v2 :: v_dual_min_num_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x96,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_hi, v2 :: v_dual_min_num_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x96,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_lo, v2 :: v_dual_min_num_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x96,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, m0, v2 :: v_dual_min_num_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x96,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_hi, v2 :: v_dual_min_num_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x96,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_lo, v2 :: v_dual_min_num_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x96,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0xaf123456, v2 :: v_dual_min_num_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x96,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, src_scc, v2 :: v_dual_min_num_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x96,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_min_num_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x96,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, -1, v4 :: v_dual_min_num_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x96,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v6, null, v5 :: v_dual_min_num_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x96,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v4, v255 :: v_dual_mov_b32 v6, v1
+// GFX12: encoding: [0x04,0xff,0x91,0xc9,0x01,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v1, v255 :: v_dual_mov_b32 v6, v255
+// GFX12: encoding: [0x01,0xff,0x91,0xc9,0xff,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v255, v255 :: v_dual_mov_b32 v6, v2
+// GFX12: encoding: [0xff,0xff,0x91,0xc9,0x02,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v2, v255 :: v_dual_mov_b32 v6, v3
+// GFX12: encoding: [0x02,0xff,0x91,0xc9,0x03,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v3, v255 :: v_dual_mov_b32 v6, v4
+// GFX12: encoding: [0x03,0xff,0x91,0xc9,0x04,0x01,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s105, v255 :: v_dual_mov_b32 v6, s1
+// GFX12: encoding: [0x69,0xfe,0x91,0xc9,0x01,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s1, v255 :: v_dual_mov_b32 v6, s105
+// GFX12: encoding: [0x01,0xfe,0x91,0xc9,0x69,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, ttmp15, v255 :: v_dual_mov_b32 v6, vcc_lo
+// GFX12: encoding: [0x7b,0xfe,0x91,0xc9,0x6a,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_hi, v255 :: v_dual_mov_b32 v6, vcc_hi
+// GFX12: encoding: [0x7f,0xfe,0x91,0xc9,0x6b,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_lo, v255 :: v_dual_mov_b32 v6, ttmp15
+// GFX12: encoding: [0x7e,0xfe,0x91,0xc9,0x7b,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, m0, v255 :: v_dual_mov_b32 v6, m0
+// GFX12: encoding: [0x7d,0xfe,0x91,0xc9,0x7d,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_hi, v255 :: v_dual_mov_b32 v6, exec_lo
+// GFX12: encoding: [0x6b,0xfe,0x91,0xc9,0x7e,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_lo, v255 :: v_dual_mov_b32 v6, exec_hi
+// GFX12: encoding: [0x6a,0xfe,0x91,0xc9,0x7f,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0xaf123456, v255 :: v_dual_mov_b32 v6, null
+// GFX12: encoding: [0xff,0xfe,0x91,0xc9,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, src_scc, v255 :: v_dual_mov_b32 v6, -1
+// GFX12: encoding: [0xfd,0xfe,0x91,0xc9,0xc1,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_mov_b32 v6, 0.5
+// GFX12: encoding: [0xf0,0x06,0x90,0xc9,0xf0,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, -1, v4 :: v_dual_mov_b32 v6, src_scc
+// GFX12: encoding: [0xc1,0x08,0x90,0xc9,0xfd,0x00,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v6, null, v5 :: v_dual_mov_b32 v255, 0xaf123456
+// GFX12: encoding: [0x7c,0x0a,0x90,0xc9,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v4, v2 :: v_dual_mul_dx9_zero_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x8e,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v1, v2 :: v_dual_mul_dx9_zero_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x8e,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v255, v2 :: v_dual_mul_dx9_zero_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x8e,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v2, v2 :: v_dual_mul_dx9_zero_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x8e,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v3, v2 :: v_dual_mul_dx9_zero_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x8e,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s105, v2 :: v_dual_mul_dx9_zero_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x8e,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s1, v2 :: v_dual_mul_dx9_zero_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x8e,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, ttmp15, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x8e,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x8e,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x8e,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, m0, v2 :: v_dual_mul_dx9_zero_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x8e,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x8e,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x8e,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0xaf123456, v2 :: v_dual_mul_dx9_zero_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x8e,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, src_scc, v2 :: v_dual_mul_dx9_zero_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x8e,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_mul_dx9_zero_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x8e,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, -1, v4 :: v_dual_mul_dx9_zero_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x8e,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v6, null, v5 :: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x8e,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v4, v2 :: v_dual_mul_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x86,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v1, v2 :: v_dual_mul_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x86,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v255, v2 :: v_dual_mul_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x86,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v2, v2 :: v_dual_mul_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x86,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v3, v2 :: v_dual_mul_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x86,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s105, v2 :: v_dual_mul_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x86,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s1, v2 :: v_dual_mul_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x86,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, ttmp15, v2 :: v_dual_mul_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x86,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_hi, v2 :: v_dual_mul_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x86,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_lo, v2 :: v_dual_mul_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x86,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, m0, v2 :: v_dual_mul_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x86,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_hi, v2 :: v_dual_mul_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x86,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_lo, v2 :: v_dual_mul_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x86,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0xaf123456, v2 :: v_dual_mul_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x86,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, src_scc, v2 :: v_dual_mul_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x86,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_mul_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x86,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, -1, v4 :: v_dual_mul_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x86,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v6, null, v5 :: v_dual_mul_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x86,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v4, v2 :: v_dual_sub_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x8a,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v1, v2 :: v_dual_sub_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x8a,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v255, v2 :: v_dual_sub_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x8a,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v2, v2 :: v_dual_sub_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x8a,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v3, v2 :: v_dual_sub_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x8a,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s105, v2 :: v_dual_sub_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x8a,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s1, v2 :: v_dual_sub_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x8a,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, ttmp15, v2 :: v_dual_sub_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x8a,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_hi, v2 :: v_dual_sub_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x8a,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_lo, v2 :: v_dual_sub_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x8a,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, m0, v2 :: v_dual_sub_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x8a,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_hi, v2 :: v_dual_sub_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x8a,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_lo, v2 :: v_dual_sub_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x8a,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0xaf123456, v2 :: v_dual_sub_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x8a,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, src_scc, v2 :: v_dual_sub_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x8a,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_sub_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x8a,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, -1, v4 :: v_dual_sub_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x8a,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v6, null, v5 :: v_dual_sub_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x8a,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v4, v2 :: v_dual_subrev_f32 v6, v1, v3
+// GFX12: encoding: [0x04,0x05,0x8c,0xc9,0x01,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v1, v2 :: v_dual_subrev_f32 v6, v255, v3
+// GFX12: encoding: [0x01,0x05,0x8c,0xc9,0xff,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v255, v2 :: v_dual_subrev_f32 v6, v2, v3
+// GFX12: encoding: [0xff,0x05,0x8c,0xc9,0x02,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v2, v2 :: v_dual_subrev_f32 v6, v3, v3
+// GFX12: encoding: [0x02,0x05,0x8c,0xc9,0x03,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, v3, v2 :: v_dual_subrev_f32 v6, v4, v3
+// GFX12: encoding: [0x03,0x05,0x8c,0xc9,0x04,0x07,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s105, v2 :: v_dual_subrev_f32 v6, s1, v3
+// GFX12: encoding: [0x69,0x04,0x8c,0xc9,0x01,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, s1, v2 :: v_dual_subrev_f32 v6, s105, v3
+// GFX12: encoding: [0x01,0x04,0x8c,0xc9,0x69,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, ttmp15, v2 :: v_dual_subrev_f32 v6, vcc_lo, v3
+// GFX12: encoding: [0x7b,0x04,0x8c,0xc9,0x6a,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_hi, v2 :: v_dual_subrev_f32 v6, vcc_hi, v3
+// GFX12: encoding: [0x7f,0x04,0x8c,0xc9,0x6b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, exec_lo, v2 :: v_dual_subrev_f32 v6, ttmp15, v3
+// GFX12: encoding: [0x7e,0x04,0x8c,0xc9,0x7b,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, m0, v2 :: v_dual_subrev_f32 v6, m0, v3
+// GFX12: encoding: [0x7d,0x04,0x8c,0xc9,0x7d,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_hi, v2 :: v_dual_subrev_f32 v6, exec_lo, v3
+// GFX12: encoding: [0x6b,0x04,0x8c,0xc9,0x7e,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, vcc_lo, v2 :: v_dual_subrev_f32 v6, exec_hi, v3
+// GFX12: encoding: [0x6a,0x04,0x8c,0xc9,0x7f,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0xaf123456, v2 :: v_dual_subrev_f32 v6, null, v3
+// GFX12: encoding: [0xff,0x04,0x8c,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, src_scc, v2 :: v_dual_subrev_f32 v6, -1, v3
+// GFX12: encoding: [0xfd,0x04,0x8c,0xc9,0xc1,0x06,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_subrev_f32 v6, 0.5, v2
+// GFX12: encoding: [0xf0,0x06,0x8c,0xc9,0xf0,0x04,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v255, -1, v4 :: v_dual_subrev_f32 v6, src_scc, v5
+// GFX12: encoding: [0xc1,0x08,0x8c,0xc9,0xfd,0x0a,0x06,0xff]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
+
+v_dual_subrev_f32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456, v4
+// GFX12: encoding: [0x7c,0x0a,0x8c,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopd_errs.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopd_errs.s
new file mode 100644
index 000000000000..0712814db955
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopd_errs.s
@@ -0,0 +1,143 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 %s 2>&1 | FileCheck %s -check-prefix=GFX12 --implicit-check-not=error: --strict-whitespace
+
+//===----------------------------------------------------------------------===//
+// A VOPD instruction can use only one literal.
+//===----------------------------------------------------------------------===//
+
+v_dual_mul_f32      v11, 0x24681357, v2          ::  v_dual_mul_f32      v10, 0xbabe, v5
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
+// GFX12-NEXT:{{^}}v_dual_mul_f32      v11, 0x24681357, v2          ::  v_dual_mul_f32      v10, 0xbabe, v5
+// GFX12-NEXT:{{^}}                                                                              ^
+
+//===----------------------------------------------------------------------===//
+// When 2 different literals are specified, show the location
+// of the last literal which is not a KImm, if any.
+//===----------------------------------------------------------------------===//
+
+v_dual_fmamk_f32    v122, v74, 0xa0172923, v161  ::  v_dual_lshlrev_b32  v247, 0xbabe, v99
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
+// GFX12-NEXT:{{^}}v_dual_fmamk_f32    v122, v74, 0xa0172923, v161  ::  v_dual_lshlrev_b32  v247, 0xbabe, v99
+// GFX12-NEXT:{{^}}                                                                               ^
+
+v_dual_add_f32      v5, 0xaf123456, v2           ::  v_dual_fmaak_f32     v6, v3, v1, 0xbabe
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
+// GFX12-NEXT:{{^}}v_dual_add_f32      v5, 0xaf123456, v2           ::  v_dual_fmaak_f32     v6, v3, v1, 0xbabe
+// GFX12-NEXT:{{^}}                        ^
+
+v_dual_add_f32      v5, 0xaf123456, v2           ::  v_dual_fmaak_f32     v6, 0xbabe, v1, 0xbabe
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
+// GFX12-NEXT:{{^}}v_dual_add_f32      v5, 0xaf123456, v2           ::  v_dual_fmaak_f32     v6, 0xbabe, v1, 0xbabe
+// GFX12-NEXT:{{^}}                                                                              ^
+
+v_dual_fmamk_f32    v122, 0xdeadbeef, 0xdeadbeef, v161 ::  v_dual_fmamk_f32  v123, 0xdeadbeef, 0x1234, v162
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
+// GFX12-NEXT:{{^}}v_dual_fmamk_f32    v122, 0xdeadbeef, 0xdeadbeef, v161 ::  v_dual_fmamk_f32  v123, 0xdeadbeef, 0x1234, v162
+// GFX12-NEXT:{{^}}                                                                                   ^
+
+v_dual_fmamk_f32    v122, 0xdeadbeef, 0xdeadbeef, v161 ::  v_dual_fmamk_f32  v123, s0, 0x1234, v162
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
+// GFX12-NEXT:{{^}}v_dual_fmamk_f32    v122, 0xdeadbeef, 0xdeadbeef, v161 ::  v_dual_fmamk_f32  v123, s0, 0x1234, v162
+// GFX12-NEXT:{{^}}                          ^
+
+//===----------------------------------------------------------------------===//
+// Check that assembler detects a different literal regardless of its location.
+//===----------------------------------------------------------------------===//
+
+v_dual_fmamk_f32    v122, 0xdeadbeef, 0xdeadbeef, v161 ::  v_dual_fmamk_f32  v123, 0xdeadbeef, 0x1234, v162
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
+// GFX12-NEXT:{{^}}v_dual_fmamk_f32    v122, 0xdeadbeef, 0xdeadbeef, v161 ::  v_dual_fmamk_f32  v123, 0xdeadbeef, 0x1234, v162
+// GFX12-NEXT:{{^}}                                                                                   ^
+
+v_dual_fmamk_f32    v122, 0xdeadbeef, 0xdeadbeef, v161 ::  v_dual_fmamk_f32  v123, 0x1234, 0xdeadbeef, v162
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
+// GFX12-NEXT:{{^}}v_dual_fmamk_f32    v122, 0xdeadbeef, 0xdeadbeef, v161 ::  v_dual_fmamk_f32  v123, 0x1234, 0xdeadbeef, v162
+// GFX12-NEXT:{{^}}                                                                                   ^
+
+v_dual_fmamk_f32    v122, 0xdeadbeef, 0x1234, v161     ::  v_dual_fmamk_f32  v123, 0xdeadbeef, 0xdeadbeef, v162
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
+// GFX12-NEXT:{{^}}v_dual_fmamk_f32    v122, 0xdeadbeef, 0x1234, v161     ::  v_dual_fmamk_f32  v123, 0xdeadbeef, 0xdeadbeef, v162
+// GFX12-NEXT:{{^}}                                                                                   ^
+
+v_dual_fmamk_f32    v122, 0x1234, 0xdeadbeef, v161     ::  v_dual_fmamk_f32  v123, 0xdeadbeef, 0xdeadbeef, v162
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
+// GFX12-NEXT:{{^}}v_dual_fmamk_f32    v122, 0x1234, 0xdeadbeef, v161     ::  v_dual_fmamk_f32  v123, 0xdeadbeef, 0xdeadbeef, v162
+// GFX12-NEXT:{{^}}                                                                                   ^
+
+//===----------------------------------------------------------------------===//
+// When 2 different literals are specified and all literals are KImm,
+// show the location of the last KImm literal.
+//===----------------------------------------------------------------------===//
+
+v_dual_fmamk_f32    v122, s0, 0xdeadbeef, v161   ::  v_dual_fmamk_f32  v123, s0, 0x1234, v162
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
+// GFX12-NEXT:{{^}}v_dual_fmamk_f32    v122, s0, 0xdeadbeef, v161   ::  v_dual_fmamk_f32  v123, s0, 0x1234, v162
+// GFX12-NEXT:{{^}}                                                                                 ^
+
+//===----------------------------------------------------------------------===//
+// A VOPD instruction cannot use more than 2 scalar operands
+//===----------------------------------------------------------------------===//
+
+// 2 different SGPRs + LITERAL
+
+v_dual_fmaak_f32    v122, s74, v161, 2.741       ::  v_dual_and_b32       v247, s75, v98
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
+// GFX12-NEXT:{{^}}v_dual_fmaak_f32    v122, s74, v161, 2.741       ::  v_dual_and_b32       v247, s75, v98
+// GFX12-NEXT:{{^}}                                                                                ^
+
+v_dual_mov_b32      v247, s73                    ::  v_dual_fmaak_f32     v122, s74, v161, 2.741
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
+// GFX12-NEXT:{{^}}v_dual_mov_b32      v247, s73                    ::  v_dual_fmaak_f32     v122, s74, v161, 2.741
+// GFX12-NEXT:{{^}}                                                                                ^
+
+v_dual_fmamk_f32    v122, s0, 0xbabe, v161       ::  v_dual_fmamk_f32     v123, s1, 0xbabe, v162
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
+// GFX12-NEXT:{{^}}v_dual_fmamk_f32    v122, s0, 0xbabe, v161       ::  v_dual_fmamk_f32     v123, s1, 0xbabe, v162
+// GFX12-NEXT:{{^}}                                                                                ^
+
+// 2 different SGPRs + VCC
+
+v_dual_add_f32      v255, s1, v2                 ::  v_dual_cndmask_b32   v6, s2, v3
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
+// GFX12-NEXT:{{^}}v_dual_add_f32      v255, s1, v2                 ::  v_dual_cndmask_b32   v6, s2, v3
+// GFX12-NEXT:{{^}}                                                                              ^
+
+v_dual_cndmask_b32   v6, s1, v3                  ::  v_dual_add_f32       v255, s2, v2
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
+// GFX12-NEXT:{{^}}v_dual_cndmask_b32   v6, s1, v3                  ::  v_dual_add_f32       v255, s2, v2
+// GFX12-NEXT:{{^}}                                                                                ^
+
+v_dual_cndmask_b32  v255, s1, v2                 ::  v_dual_cndmask_b32   v6, s2, v3
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
+// GFX12-NEXT:{{^}}v_dual_cndmask_b32  v255, s1, v2                 ::  v_dual_cndmask_b32   v6, s2, v3
+// GFX12-NEXT:{{^}}                                                                              ^
+
+// SGPR + LITERAL + VCC
+
+v_dual_cndmask_b32  v255, s1, v2                 ::  v_dual_mov_b32       v254, 0xbabe
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
+// GFX12-NEXT:{{^}}v_dual_cndmask_b32  v255, s1, v2                 ::  v_dual_mov_b32       v254, 0xbabe
+// GFX12-NEXT:{{^}}                                                                                ^
+
+v_dual_cndmask_b32  v255, 0xbabe, v2             ::  v_dual_mov_b32       v254, s1
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
+// GFX12-NEXT:{{^}}v_dual_cndmask_b32  v255, 0xbabe, v2             ::  v_dual_mov_b32       v254, s1
+// GFX12-NEXT:{{^}}                                                                                ^
+
+v_dual_cndmask_b32  v255, s3, v2                 ::  v_dual_fmamk_f32     v254, v1, 0xbabe, v162
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
+// GFX12-NEXT:{{^}}v_dual_cndmask_b32  v255, s3, v2                 ::  v_dual_fmamk_f32     v254, v1, 0xbabe, v162
+// GFX12-NEXT:{{^}}                          ^
+
+v_dual_cndmask_b32  v255, v1, v2                 ::  v_dual_fmamk_f32     v254, s3, 0xbabe, v162
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
+// GFX12-NEXT:{{^}}v_dual_cndmask_b32  v255, v1, v2                 ::  v_dual_fmamk_f32     v254, s3, 0xbabe, v162
+// GFX12-NEXT:{{^}}                                                                                ^
+
+// SGPR + VCC + VCC_LO
+// This is a special case because implicit VCC operand has 64 bit size.
+// SP3 does not accept this instruction as well.
+
+v_dual_add_f32      v255, vcc_lo, v2             ::  v_dual_cndmask_b32   v6, s1, v3
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
+// GFX12-NEXT:{{^}}v_dual_add_f32      v255, vcc_lo, v2             ::  v_dual_cndmask_b32   v6, s1, v3
+// GFX12-NEXT:{{^}}                                                                              ^
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopd_features.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopd_features.s
new file mode 100644
index 000000000000..840dc3f82f2b
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopd_features.s
@@ -0,0 +1,101 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -show-encoding %s | FileCheck -check-prefix=GFX12 %s
+
+//===----------------------------------------------------------------------===//
+// A VOPD instruction can use one or more literals,
+// provided that they are identical.
+//===----------------------------------------------------------------------===//
+
+// LITERAL
+
+v_dual_mul_f32      v11, v1, v2                  ::  v_dual_mul_f32      v10, 0x24681357, v5
+// GFX12: encoding: [0x01,0x05,0xc6,0xc8,0xff,0x0a,0x0a,0x0b,0x57,0x13,0x68,0x24]
+
+// LITERAL*2
+
+v_dual_mul_f32      v11, 0x24681357, v2          ::  v_dual_mul_f32      v10, 0x24681357, v5
+// GFX12: encoding: [0xff,0x04,0xc6,0xc8,0xff,0x0a,0x0a,0x0b,0x57,0x13,0x68,0x24]
+
+// LITERAL + KIMM
+
+v_dual_add_f32      v5, 0xaf123456, v2           ::  v_dual_fmaak_f32     v6, v3, v1, 0xaf123456 ;
+// GFX12: encoding: [0xff,0x04,0x02,0xc9,0x03,0x03,0x06,0x05,0x56,0x34,0x12,0xaf]
+
+// KIMM + LITERAL
+
+v_dual_fmamk_f32    v122, v74, 0xa0172923, v161  ::  v_dual_lshlrev_b32   v247, 0xa0172923, v99
+// GFX12: encoding: [0x4a,0x43,0xa3,0xc8,0xff,0xc6,0xf6,0x7a,0x23,0x29,0x17,0xa0]
+
+// KIMM*2
+
+v_dual_fmamk_f32    v122, 0xdeadbeef, 0xdeadbeef, v161 ::  v_dual_fmamk_f32  v123, 0xdeadbeef, 0xdeadbeef, v162
+// GFX12: encoding: [0xff,0x42,0x85,0xc8,0xff,0x44,0x7b,0x7a,0xef,0xbe,0xad,0xde]
+
+//===----------------------------------------------------------------------===//
+// A VOPD instruction can use 2 scalar operands,
+// but implicit VCC must be counted in.
+//===----------------------------------------------------------------------===//
+
+// 2 different SGPRs
+
+v_dual_mul_f32      v0, s1, v2                   ::  v_dual_mul_f32       v3, s4, v5
+// GFX12: encoding: [0x01,0x04,0xc6,0xc8,0x04,0x0a,0x02,0x00]
+
+// SGPR + LITERAL
+
+v_dual_fmaak_f32    v122, s74, v161, 2.741       ::  v_dual_and_b32       v247, v160, v98
+// GFX12: encoding: [0x4a,0x42,0x65,0xc8,0xa0,0xc5,0xf6,0x7a,0x8b,0x6c,0x2f,0x40]
+
+v_dual_mov_b32      v247, v160                   ::  v_dual_fmaak_f32     v122, s74, v161, 2.741
+// GFX12: encoding: [0xa0,0x01,0x02,0xca,0x4a,0x42,0x7b,0xf7,0x8b,0x6c,0x2f,0x40]
+
+// SGPR*2 + LITERAL
+
+v_dual_fmaak_f32    v122, s74, v161, 2.741       ::  v_dual_and_b32       v247, s74, v98
+// GFX12: encoding: [0x4a,0x42,0x65,0xc8,0x4a,0xc4,0xf6,0x7a,0x8b,0x6c,0x2f,0x40]
+
+// SGPR + LITERAL*2
+
+v_dual_fmaak_f32    v122, s74, v161, 2.741       ::  v_dual_fmamk_f32     v3, v6, 2.741, v1
+// GFX12: encoding: [0x4a,0x42,0x45,0xc8,0x06,0x03,0x02,0x7a,0x8b,0x6c,0x2f,0x40]
+
+// SGPR*2 + LITERAL*2
+
+v_dual_fmaak_f32    v122, s74, v161, 2.741       ::  v_dual_fmamk_f32     v3, s74, 2.741, v1
+// GFX12: encoding: [0x4a,0x42,0x45,0xc8,0x4a,0x02,0x02,0x7a,0x8b,0x6c,0x2f,0x40]
+
+// LITERAL + VCC
+
+v_dual_fmaak_f32    v122, v0, v161, 2.741       ::  v_dual_cndmask_b32   v1, v2, v3
+// GFX12: encoding: [0x00,0x43,0x53,0xc8,0x02,0x07,0x00,0x7a,0x8b,0x6c,0x2f,0x40]
+
+// LITERAL*2 + VCC
+
+v_dual_fmaak_f32    v122, v0, v161, 2.741       ::  v_dual_cndmask_b32   v1, 2.741, v3
+// GFX12: encoding: [0x00,0x43,0x53,0xc8,0xff,0x06,0x00,0x7a,0x8b,0x6c,0x2f,0x40]
+
+// LITERAL*2 + VCC*2
+
+v_dual_cndmask_b32  v255, 0xbabe, v2             ::  v_dual_cndmask_b32   v6, 0xbabe, v3
+// GFX12: encoding: [0xff,0x04,0x52,0xca,0xff,0x06,0x06,0xff,0xbe,0xba,0x00,0x00]
+
+// SGPR*2 + VCC
+
+v_dual_add_f32      v255, s105, v2               ::  v_dual_cndmask_b32   v6, s105, v3
+// GFX12: encoding: [0x69,0x04,0x12,0xc9,0x69,0x06,0x06,0xff]
+
+// SGPR*2 + VCC*2
+
+v_dual_cndmask_b32  v255, s1, v2                 ::  v_dual_cndmask_b32   v6, s1, v3
+// GFX12: encoding: [0x01,0x04,0x52,0xca,0x01,0x06,0x06,0xff]
+
+// VCC*2
+
+v_dual_add_f32      v255, vcc_lo, v2             ::  v_dual_cndmask_b32   v6, v1, v3
+// GFX12: encoding: [0x6a,0x04,0x12,0xc9,0x01,0x07,0x06,0xff]
+
+//===----------------------------------------------------------------------===//
+// A VOPD OpY mov_b32 instruction uses SRC2 source-cache if OpX is also mov_b32
+//===----------------------------------------------------------------------===//
+
+v_dual_mov_b32      v2, v5                       ::  v_dual_mov_b32       v3, v1
+// GFX12: encoding: [0x05,0x01,0x10,0xca,0x01,0x01,0x02,0x02]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1.txt
new file mode 100644
index 000000000000..a839f03c42ba
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1.txt
@@ -0,0 +1,3302 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX12 %s
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX12 %s
+
+# GFX12: v_bfrev_b32_e32 v5, v1                  ; encoding: [0x01,0x71,0x0a,0x7e]
+0x01,0x71,0x0a,0x7e
+
+# GFX12: v_bfrev_b32_e32 v5, v255                ; encoding: [0xff,0x71,0x0a,0x7e]
+0xff,0x71,0x0a,0x7e
+
+# GFX12: v_bfrev_b32_e32 v5, s1                  ; encoding: [0x01,0x70,0x0a,0x7e]
+0x01,0x70,0x0a,0x7e
+
+# GFX12: v_bfrev_b32_e32 v5, s105                ; encoding: [0x69,0x70,0x0a,0x7e]
+0x69,0x70,0x0a,0x7e
+
+# GFX12: v_bfrev_b32_e32 v5, vcc_lo              ; encoding: [0x6a,0x70,0x0a,0x7e]
+0x6a,0x70,0x0a,0x7e
+
+# GFX12: v_bfrev_b32_e32 v5, vcc_hi              ; encoding: [0x6b,0x70,0x0a,0x7e]
+0x6b,0x70,0x0a,0x7e
+
+# GFX12: v_bfrev_b32_e32 v5, ttmp15              ; encoding: [0x7b,0x70,0x0a,0x7e]
+0x7b,0x70,0x0a,0x7e
+
+# GFX12: v_bfrev_b32_e32 v5, m0                  ; encoding: [0x7d,0x70,0x0a,0x7e]
+0x7d,0x70,0x0a,0x7e
+
+# GFX12: v_bfrev_b32_e32 v5, exec_lo             ; encoding: [0x7e,0x70,0x0a,0x7e]
+0x7e,0x70,0x0a,0x7e
+
+# GFX12: v_bfrev_b32_e32 v5, exec_hi             ; encoding: [0x7f,0x70,0x0a,0x7e]
+0x7f,0x70,0x0a,0x7e
+
+# GFX12: v_bfrev_b32_e32 v5, null                ; encoding: [0x7c,0x70,0x0a,0x7e]
+0x7c,0x70,0x0a,0x7e
+
+# GFX12: v_bfrev_b32_e32 v5, -1                  ; encoding: [0xc1,0x70,0x0a,0x7e]
+0xc1,0x70,0x0a,0x7e
+
+# GFX12: v_bfrev_b32_e32 v5, 0.5                 ; encoding: [0xf0,0x70,0x0a,0x7e]
+0xf0,0x70,0x0a,0x7e
+
+# GFX12: v_bfrev_b32_e32 v5, src_scc             ; encoding: [0xfd,0x70,0x0a,0x7e]
+0xfd,0x70,0x0a,0x7e
+
+# GFX12: v_bfrev_b32_e32 v255, 0xaf123456        ; encoding: [0xff,0x70,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x70,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_ceil_f16_e32 v5, v1                   ; encoding: [0x01,0xb9,0x0a,0x7e]
+0x01,0xb9,0x0a,0x7e
+
+# GFX12: v_ceil_f16_e32 v5, v127                 ; encoding: [0x7f,0xb9,0x0a,0x7e]
+0x7f,0xb9,0x0a,0x7e
+
+# GFX12: v_ceil_f16_e32 v5, s1                   ; encoding: [0x01,0xb8,0x0a,0x7e]
+0x01,0xb8,0x0a,0x7e
+
+# GFX12: v_ceil_f16_e32 v5, s105                 ; encoding: [0x69,0xb8,0x0a,0x7e]
+0x69,0xb8,0x0a,0x7e
+
+# GFX12: v_ceil_f16_e32 v5, vcc_lo               ; encoding: [0x6a,0xb8,0x0a,0x7e]
+0x6a,0xb8,0x0a,0x7e
+
+# GFX12: v_ceil_f16_e32 v5, vcc_hi               ; encoding: [0x6b,0xb8,0x0a,0x7e]
+0x6b,0xb8,0x0a,0x7e
+
+# GFX12: v_ceil_f16_e32 v5, ttmp15               ; encoding: [0x7b,0xb8,0x0a,0x7e]
+0x7b,0xb8,0x0a,0x7e
+
+# GFX12: v_ceil_f16_e32 v5, m0                   ; encoding: [0x7d,0xb8,0x0a,0x7e]
+0x7d,0xb8,0x0a,0x7e
+
+# GFX12: v_ceil_f16_e32 v5, exec_lo              ; encoding: [0x7e,0xb8,0x0a,0x7e]
+0x7e,0xb8,0x0a,0x7e
+
+# GFX12: v_ceil_f16_e32 v5, exec_hi              ; encoding: [0x7f,0xb8,0x0a,0x7e]
+0x7f,0xb8,0x0a,0x7e
+
+# GFX12: v_ceil_f16_e32 v5, null                 ; encoding: [0x7c,0xb8,0x0a,0x7e]
+0x7c,0xb8,0x0a,0x7e
+
+# GFX12: v_ceil_f16_e32 v5, -1                   ; encoding: [0xc1,0xb8,0x0a,0x7e]
+0xc1,0xb8,0x0a,0x7e
+
+# GFX12: v_ceil_f16_e32 v5, 0.5                  ; encoding: [0xf0,0xb8,0x0a,0x7e]
+0xf0,0xb8,0x0a,0x7e
+
+# GFX12: v_ceil_f16_e32 v5, src_scc              ; encoding: [0xfd,0xb8,0x0a,0x7e]
+0xfd,0xb8,0x0a,0x7e
+
+# GFX12: v_ceil_f16_e32 v127, 0xfe0b             ; encoding: [0xff,0xb8,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+0xff,0xb8,0xfe,0x7e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_ceil_f32_e32 v5, v1                   ; encoding: [0x01,0x45,0x0a,0x7e]
+0x01,0x45,0x0a,0x7e
+
+# GFX12: v_ceil_f32_e32 v5, v255                 ; encoding: [0xff,0x45,0x0a,0x7e]
+0xff,0x45,0x0a,0x7e
+
+# GFX12: v_ceil_f32_e32 v5, s1                   ; encoding: [0x01,0x44,0x0a,0x7e]
+0x01,0x44,0x0a,0x7e
+
+# GFX12: v_ceil_f32_e32 v5, s105                 ; encoding: [0x69,0x44,0x0a,0x7e]
+0x69,0x44,0x0a,0x7e
+
+# GFX12: v_ceil_f32_e32 v5, vcc_lo               ; encoding: [0x6a,0x44,0x0a,0x7e]
+0x6a,0x44,0x0a,0x7e
+
+# GFX12: v_ceil_f32_e32 v5, vcc_hi               ; encoding: [0x6b,0x44,0x0a,0x7e]
+0x6b,0x44,0x0a,0x7e
+
+# GFX12: v_ceil_f32_e32 v5, ttmp15               ; encoding: [0x7b,0x44,0x0a,0x7e]
+0x7b,0x44,0x0a,0x7e
+
+# GFX12: v_ceil_f32_e32 v5, m0                   ; encoding: [0x7d,0x44,0x0a,0x7e]
+0x7d,0x44,0x0a,0x7e
+
+# GFX12: v_ceil_f32_e32 v5, exec_lo              ; encoding: [0x7e,0x44,0x0a,0x7e]
+0x7e,0x44,0x0a,0x7e
+
+# GFX12: v_ceil_f32_e32 v5, exec_hi              ; encoding: [0x7f,0x44,0x0a,0x7e]
+0x7f,0x44,0x0a,0x7e
+
+# GFX12: v_ceil_f32_e32 v5, null                 ; encoding: [0x7c,0x44,0x0a,0x7e]
+0x7c,0x44,0x0a,0x7e
+
+# GFX12: v_ceil_f32_e32 v5, -1                   ; encoding: [0xc1,0x44,0x0a,0x7e]
+0xc1,0x44,0x0a,0x7e
+
+# GFX12: v_ceil_f32_e32 v5, 0.5                  ; encoding: [0xf0,0x44,0x0a,0x7e]
+0xf0,0x44,0x0a,0x7e
+
+# GFX12: v_ceil_f32_e32 v5, src_scc              ; encoding: [0xfd,0x44,0x0a,0x7e]
+0xfd,0x44,0x0a,0x7e
+
+# GFX12: v_ceil_f32_e32 v255, 0xaf123456         ; encoding: [0xff,0x44,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x44,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_ceil_f64_e32 v[5:6], v[1:2]           ; encoding: [0x01,0x31,0x0a,0x7e]
+0x01,0x31,0x0a,0x7e
+
+# GFX12: v_ceil_f64_e32 v[5:6], v[254:255]       ; encoding: [0xfe,0x31,0x0a,0x7e]
+0xfe,0x31,0x0a,0x7e
+
+# GFX12: v_ceil_f64_e32 v[5:6], s[2:3]           ; encoding: [0x02,0x30,0x0a,0x7e]
+0x02,0x30,0x0a,0x7e
+
+# GFX12: v_ceil_f64_e32 v[5:6], s[104:105]       ; encoding: [0x68,0x30,0x0a,0x7e]
+0x68,0x30,0x0a,0x7e
+
+# GFX12: v_ceil_f64_e32 v[5:6], vcc              ; encoding: [0x6a,0x30,0x0a,0x7e]
+0x6a,0x30,0x0a,0x7e
+
+# GFX12: v_ceil_f64_e32 v[5:6], ttmp[14:15]      ; encoding: [0x7a,0x30,0x0a,0x7e]
+0x7a,0x30,0x0a,0x7e
+
+# GFX12: v_ceil_f64_e32 v[5:6], exec             ; encoding: [0x7e,0x30,0x0a,0x7e]
+0x7e,0x30,0x0a,0x7e
+
+# GFX12: v_ceil_f64_e32 v[5:6], null             ; encoding: [0x7c,0x30,0x0a,0x7e]
+0x7c,0x30,0x0a,0x7e
+
+# GFX12: v_ceil_f64_e32 v[5:6], -1               ; encoding: [0xc1,0x30,0x0a,0x7e]
+0xc1,0x30,0x0a,0x7e
+
+# GFX12: v_ceil_f64_e32 v[5:6], 0.5              ; encoding: [0xf0,0x30,0x0a,0x7e]
+0xf0,0x30,0x0a,0x7e
+
+# GFX12: v_ceil_f64_e32 v[5:6], src_scc          ; encoding: [0xfd,0x30,0x0a,0x7e]
+0xfd,0x30,0x0a,0x7e
+
+# GFX12: v_ceil_f64_e32 v[254:255], 0xaf123456   ; encoding: [0xff,0x30,0xfc,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x30,0xfc,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cls_i32_e32 v5, v1                    ; encoding: [0x01,0x77,0x0a,0x7e]
+0x01,0x77,0x0a,0x7e
+
+# GFX12: v_cls_i32_e32 v5, v255                  ; encoding: [0xff,0x77,0x0a,0x7e]
+0xff,0x77,0x0a,0x7e
+
+# GFX12: v_cls_i32_e32 v5, s1                    ; encoding: [0x01,0x76,0x0a,0x7e]
+0x01,0x76,0x0a,0x7e
+
+# GFX12: v_cls_i32_e32 v5, s105                  ; encoding: [0x69,0x76,0x0a,0x7e]
+0x69,0x76,0x0a,0x7e
+
+# GFX12: v_cls_i32_e32 v5, vcc_lo                ; encoding: [0x6a,0x76,0x0a,0x7e]
+0x6a,0x76,0x0a,0x7e
+
+# GFX12: v_cls_i32_e32 v5, vcc_hi                ; encoding: [0x6b,0x76,0x0a,0x7e]
+0x6b,0x76,0x0a,0x7e
+
+# GFX12: v_cls_i32_e32 v5, ttmp15                ; encoding: [0x7b,0x76,0x0a,0x7e]
+0x7b,0x76,0x0a,0x7e
+
+# GFX12: v_cls_i32_e32 v5, m0                    ; encoding: [0x7d,0x76,0x0a,0x7e]
+0x7d,0x76,0x0a,0x7e
+
+# GFX12: v_cls_i32_e32 v5, exec_lo               ; encoding: [0x7e,0x76,0x0a,0x7e]
+0x7e,0x76,0x0a,0x7e
+
+# GFX12: v_cls_i32_e32 v5, exec_hi               ; encoding: [0x7f,0x76,0x0a,0x7e]
+0x7f,0x76,0x0a,0x7e
+
+# GFX12: v_cls_i32_e32 v5, null                  ; encoding: [0x7c,0x76,0x0a,0x7e]
+0x7c,0x76,0x0a,0x7e
+
+# GFX12: v_cls_i32_e32 v5, -1                    ; encoding: [0xc1,0x76,0x0a,0x7e]
+0xc1,0x76,0x0a,0x7e
+
+# GFX12: v_cls_i32_e32 v5, 0.5                   ; encoding: [0xf0,0x76,0x0a,0x7e]
+0xf0,0x76,0x0a,0x7e
+
+# GFX12: v_cls_i32_e32 v5, src_scc               ; encoding: [0xfd,0x76,0x0a,0x7e]
+0xfd,0x76,0x0a,0x7e
+
+# GFX12: v_cls_i32_e32 v255, 0xaf123456          ; encoding: [0xff,0x76,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x76,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_clz_i32_u32_e32 v5, v1                ; encoding: [0x01,0x73,0x0a,0x7e]
+0x01,0x73,0x0a,0x7e
+
+# GFX12: v_clz_i32_u32_e32 v5, v255              ; encoding: [0xff,0x73,0x0a,0x7e]
+0xff,0x73,0x0a,0x7e
+
+# GFX12: v_clz_i32_u32_e32 v5, s1                ; encoding: [0x01,0x72,0x0a,0x7e]
+0x01,0x72,0x0a,0x7e
+
+# GFX12: v_clz_i32_u32_e32 v5, s105              ; encoding: [0x69,0x72,0x0a,0x7e]
+0x69,0x72,0x0a,0x7e
+
+# GFX12: v_clz_i32_u32_e32 v5, vcc_lo            ; encoding: [0x6a,0x72,0x0a,0x7e]
+0x6a,0x72,0x0a,0x7e
+
+# GFX12: v_clz_i32_u32_e32 v5, vcc_hi            ; encoding: [0x6b,0x72,0x0a,0x7e]
+0x6b,0x72,0x0a,0x7e
+
+# GFX12: v_clz_i32_u32_e32 v5, ttmp15            ; encoding: [0x7b,0x72,0x0a,0x7e]
+0x7b,0x72,0x0a,0x7e
+
+# GFX12: v_clz_i32_u32_e32 v5, m0                ; encoding: [0x7d,0x72,0x0a,0x7e]
+0x7d,0x72,0x0a,0x7e
+
+# GFX12: v_clz_i32_u32_e32 v5, exec_lo           ; encoding: [0x7e,0x72,0x0a,0x7e]
+0x7e,0x72,0x0a,0x7e
+
+# GFX12: v_clz_i32_u32_e32 v5, exec_hi           ; encoding: [0x7f,0x72,0x0a,0x7e]
+0x7f,0x72,0x0a,0x7e
+
+# GFX12: v_clz_i32_u32_e32 v5, null              ; encoding: [0x7c,0x72,0x0a,0x7e]
+0x7c,0x72,0x0a,0x7e
+
+# GFX12: v_clz_i32_u32_e32 v5, -1                ; encoding: [0xc1,0x72,0x0a,0x7e]
+0xc1,0x72,0x0a,0x7e
+
+# GFX12: v_clz_i32_u32_e32 v5, 0.5               ; encoding: [0xf0,0x72,0x0a,0x7e]
+0xf0,0x72,0x0a,0x7e
+
+# GFX12: v_clz_i32_u32_e32 v5, src_scc           ; encoding: [0xfd,0x72,0x0a,0x7e]
+0xfd,0x72,0x0a,0x7e
+
+# GFX12: v_clz_i32_u32_e32 v255, 0xaf123456      ; encoding: [0xff,0x72,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x72,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cos_f16_e32 v5, v1                    ; encoding: [0x01,0xc3,0x0a,0x7e]
+0x01,0xc3,0x0a,0x7e
+
+# GFX12: v_cos_f16_e32 v5, v127                  ; encoding: [0x7f,0xc3,0x0a,0x7e]
+0x7f,0xc3,0x0a,0x7e
+
+# GFX12: v_cos_f16_e32 v5, s1                    ; encoding: [0x01,0xc2,0x0a,0x7e]
+0x01,0xc2,0x0a,0x7e
+
+# GFX12: v_cos_f16_e32 v5, s105                  ; encoding: [0x69,0xc2,0x0a,0x7e]
+0x69,0xc2,0x0a,0x7e
+
+# GFX12: v_cos_f16_e32 v5, vcc_lo                ; encoding: [0x6a,0xc2,0x0a,0x7e]
+0x6a,0xc2,0x0a,0x7e
+
+# GFX12: v_cos_f16_e32 v5, vcc_hi                ; encoding: [0x6b,0xc2,0x0a,0x7e]
+0x6b,0xc2,0x0a,0x7e
+
+# GFX12: v_cos_f16_e32 v5, ttmp15                ; encoding: [0x7b,0xc2,0x0a,0x7e]
+0x7b,0xc2,0x0a,0x7e
+
+# GFX12: v_cos_f16_e32 v5, m0                    ; encoding: [0x7d,0xc2,0x0a,0x7e]
+0x7d,0xc2,0x0a,0x7e
+
+# GFX12: v_cos_f16_e32 v5, exec_lo               ; encoding: [0x7e,0xc2,0x0a,0x7e]
+0x7e,0xc2,0x0a,0x7e
+
+# GFX12: v_cos_f16_e32 v5, exec_hi               ; encoding: [0x7f,0xc2,0x0a,0x7e]
+0x7f,0xc2,0x0a,0x7e
+
+# GFX12: v_cos_f16_e32 v5, null                  ; encoding: [0x7c,0xc2,0x0a,0x7e]
+0x7c,0xc2,0x0a,0x7e
+
+# GFX12: v_cos_f16_e32 v5, -1                    ; encoding: [0xc1,0xc2,0x0a,0x7e]
+0xc1,0xc2,0x0a,0x7e
+
+# GFX12: v_cos_f16_e32 v5, 0.5                   ; encoding: [0xf0,0xc2,0x0a,0x7e]
+0xf0,0xc2,0x0a,0x7e
+
+# GFX12: v_cos_f16_e32 v5, src_scc               ; encoding: [0xfd,0xc2,0x0a,0x7e]
+0xfd,0xc2,0x0a,0x7e
+
+# GFX12: v_cos_f16_e32 v127, 0xfe0b              ; encoding: [0xff,0xc2,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+0xff,0xc2,0xfe,0x7e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cos_f32_e32 v5, v1                    ; encoding: [0x01,0x6d,0x0a,0x7e]
+0x01,0x6d,0x0a,0x7e
+
+# GFX12: v_cos_f32_e32 v5, v255                  ; encoding: [0xff,0x6d,0x0a,0x7e]
+0xff,0x6d,0x0a,0x7e
+
+# GFX12: v_cos_f32_e32 v5, s1                    ; encoding: [0x01,0x6c,0x0a,0x7e]
+0x01,0x6c,0x0a,0x7e
+
+# GFX12: v_cos_f32_e32 v5, s105                  ; encoding: [0x69,0x6c,0x0a,0x7e]
+0x69,0x6c,0x0a,0x7e
+
+# GFX12: v_cos_f32_e32 v5, vcc_lo                ; encoding: [0x6a,0x6c,0x0a,0x7e]
+0x6a,0x6c,0x0a,0x7e
+
+# GFX12: v_cos_f32_e32 v5, vcc_hi                ; encoding: [0x6b,0x6c,0x0a,0x7e]
+0x6b,0x6c,0x0a,0x7e
+
+# GFX12: v_cos_f32_e32 v5, ttmp15                ; encoding: [0x7b,0x6c,0x0a,0x7e]
+0x7b,0x6c,0x0a,0x7e
+
+# GFX12: v_cos_f32_e32 v5, m0                    ; encoding: [0x7d,0x6c,0x0a,0x7e]
+0x7d,0x6c,0x0a,0x7e
+
+# GFX12: v_cos_f32_e32 v5, exec_lo               ; encoding: [0x7e,0x6c,0x0a,0x7e]
+0x7e,0x6c,0x0a,0x7e
+
+# GFX12: v_cos_f32_e32 v5, exec_hi               ; encoding: [0x7f,0x6c,0x0a,0x7e]
+0x7f,0x6c,0x0a,0x7e
+
+# GFX12: v_cos_f32_e32 v5, null                  ; encoding: [0x7c,0x6c,0x0a,0x7e]
+0x7c,0x6c,0x0a,0x7e
+
+# GFX12: v_cos_f32_e32 v5, -1                    ; encoding: [0xc1,0x6c,0x0a,0x7e]
+0xc1,0x6c,0x0a,0x7e
+
+# GFX12: v_cos_f32_e32 v5, 0.5                   ; encoding: [0xf0,0x6c,0x0a,0x7e]
+0xf0,0x6c,0x0a,0x7e
+
+# GFX12: v_cos_f32_e32 v5, src_scc               ; encoding: [0xfd,0x6c,0x0a,0x7e]
+0xfd,0x6c,0x0a,0x7e
+
+# GFX12: v_cos_f32_e32 v255, 0xaf123456          ; encoding: [0xff,0x6c,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x6c,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_ctz_i32_b32_e32 v5, v1                ; encoding: [0x01,0x75,0x0a,0x7e]
+0x01,0x75,0x0a,0x7e
+
+# GFX12: v_ctz_i32_b32_e32 v5, v255              ; encoding: [0xff,0x75,0x0a,0x7e]
+0xff,0x75,0x0a,0x7e
+
+# GFX12: v_ctz_i32_b32_e32 v5, s1                ; encoding: [0x01,0x74,0x0a,0x7e]
+0x01,0x74,0x0a,0x7e
+
+# GFX12: v_ctz_i32_b32_e32 v5, s105              ; encoding: [0x69,0x74,0x0a,0x7e]
+0x69,0x74,0x0a,0x7e
+
+# GFX12: v_ctz_i32_b32_e32 v5, vcc_lo            ; encoding: [0x6a,0x74,0x0a,0x7e]
+0x6a,0x74,0x0a,0x7e
+
+# GFX12: v_ctz_i32_b32_e32 v5, vcc_hi            ; encoding: [0x6b,0x74,0x0a,0x7e]
+0x6b,0x74,0x0a,0x7e
+
+# GFX12: v_ctz_i32_b32_e32 v5, ttmp15            ; encoding: [0x7b,0x74,0x0a,0x7e]
+0x7b,0x74,0x0a,0x7e
+
+# GFX12: v_ctz_i32_b32_e32 v5, m0                ; encoding: [0x7d,0x74,0x0a,0x7e]
+0x7d,0x74,0x0a,0x7e
+
+# GFX12: v_ctz_i32_b32_e32 v5, exec_lo           ; encoding: [0x7e,0x74,0x0a,0x7e]
+0x7e,0x74,0x0a,0x7e
+
+# GFX12: v_ctz_i32_b32_e32 v5, exec_hi           ; encoding: [0x7f,0x74,0x0a,0x7e]
+0x7f,0x74,0x0a,0x7e
+
+# GFX12: v_ctz_i32_b32_e32 v5, null              ; encoding: [0x7c,0x74,0x0a,0x7e]
+0x7c,0x74,0x0a,0x7e
+
+# GFX12: v_ctz_i32_b32_e32 v5, -1                ; encoding: [0xc1,0x74,0x0a,0x7e]
+0xc1,0x74,0x0a,0x7e
+
+# GFX12: v_ctz_i32_b32_e32 v5, 0.5               ; encoding: [0xf0,0x74,0x0a,0x7e]
+0xf0,0x74,0x0a,0x7e
+
+# GFX12: v_ctz_i32_b32_e32 v5, src_scc           ; encoding: [0xfd,0x74,0x0a,0x7e]
+0xfd,0x74,0x0a,0x7e
+
+# GFX12: v_ctz_i32_b32_e32 v255, 0xaf123456      ; encoding: [0xff,0x74,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x74,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_f16_f32_e32 v5, v1                ; encoding: [0x01,0x15,0x0a,0x7e]
+0x01,0x15,0x0a,0x7e
+
+# GFX12: v_cvt_f16_f32_e32 v5, v255              ; encoding: [0xff,0x15,0x0a,0x7e]
+0xff,0x15,0x0a,0x7e
+
+# GFX12: v_cvt_f16_f32_e32 v5, s1                ; encoding: [0x01,0x14,0x0a,0x7e]
+0x01,0x14,0x0a,0x7e
+
+# GFX12: v_cvt_f16_f32_e32 v5, s105              ; encoding: [0x69,0x14,0x0a,0x7e]
+0x69,0x14,0x0a,0x7e
+
+# GFX12: v_cvt_f16_f32_e32 v5, vcc_lo            ; encoding: [0x6a,0x14,0x0a,0x7e]
+0x6a,0x14,0x0a,0x7e
+
+# GFX12: v_cvt_f16_f32_e32 v5, vcc_hi            ; encoding: [0x6b,0x14,0x0a,0x7e]
+0x6b,0x14,0x0a,0x7e
+
+# GFX12: v_cvt_f16_f32_e32 v5, ttmp15            ; encoding: [0x7b,0x14,0x0a,0x7e]
+0x7b,0x14,0x0a,0x7e
+
+# GFX12: v_cvt_f16_f32_e32 v5, m0                ; encoding: [0x7d,0x14,0x0a,0x7e]
+0x7d,0x14,0x0a,0x7e
+
+# GFX12: v_cvt_f16_f32_e32 v5, exec_lo           ; encoding: [0x7e,0x14,0x0a,0x7e]
+0x7e,0x14,0x0a,0x7e
+
+# GFX12: v_cvt_f16_f32_e32 v5, exec_hi           ; encoding: [0x7f,0x14,0x0a,0x7e]
+0x7f,0x14,0x0a,0x7e
+
+# GFX12: v_cvt_f16_f32_e32 v5, null              ; encoding: [0x7c,0x14,0x0a,0x7e]
+0x7c,0x14,0x0a,0x7e
+
+# GFX12: v_cvt_f16_f32_e32 v5, -1                ; encoding: [0xc1,0x14,0x0a,0x7e]
+0xc1,0x14,0x0a,0x7e
+
+# GFX12: v_cvt_f16_f32_e32 v5, 0.5               ; encoding: [0xf0,0x14,0x0a,0x7e]
+0xf0,0x14,0x0a,0x7e
+
+# GFX12: v_cvt_f16_f32_e32 v5, src_scc           ; encoding: [0xfd,0x14,0x0a,0x7e]
+0xfd,0x14,0x0a,0x7e
+
+# GFX12: v_cvt_f16_f32_e32 v127, 0xaf123456      ; encoding: [0xff,0x14,0xfe,0x7e,0x56,0x34,0x12,0xaf]
+0xff,0x14,0xfe,0x7e,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_f16_i16_e32 v5, v1                ; encoding: [0x01,0xa3,0x0a,0x7e]
+0x01,0xa3,0x0a,0x7e
+
+# GFX12: v_cvt_f16_i16_e32 v5, v127              ; encoding: [0x7f,0xa3,0x0a,0x7e]
+0x7f,0xa3,0x0a,0x7e
+
+# GFX12: v_cvt_f16_i16_e32 v5, s1                ; encoding: [0x01,0xa2,0x0a,0x7e]
+0x01,0xa2,0x0a,0x7e
+
+# GFX12: v_cvt_f16_i16_e32 v5, s105              ; encoding: [0x69,0xa2,0x0a,0x7e]
+0x69,0xa2,0x0a,0x7e
+
+# GFX12: v_cvt_f16_i16_e32 v5, vcc_lo            ; encoding: [0x6a,0xa2,0x0a,0x7e]
+0x6a,0xa2,0x0a,0x7e
+
+# GFX12: v_cvt_f16_i16_e32 v5, vcc_hi            ; encoding: [0x6b,0xa2,0x0a,0x7e]
+0x6b,0xa2,0x0a,0x7e
+
+# GFX12: v_cvt_f16_i16_e32 v5, ttmp15            ; encoding: [0x7b,0xa2,0x0a,0x7e]
+0x7b,0xa2,0x0a,0x7e
+
+# GFX12: v_cvt_f16_i16_e32 v5, m0                ; encoding: [0x7d,0xa2,0x0a,0x7e]
+0x7d,0xa2,0x0a,0x7e
+
+# GFX12: v_cvt_f16_i16_e32 v5, exec_lo           ; encoding: [0x7e,0xa2,0x0a,0x7e]
+0x7e,0xa2,0x0a,0x7e
+
+# GFX12: v_cvt_f16_i16_e32 v5, exec_hi           ; encoding: [0x7f,0xa2,0x0a,0x7e]
+0x7f,0xa2,0x0a,0x7e
+
+# GFX12: v_cvt_f16_i16_e32 v5, null              ; encoding: [0x7c,0xa2,0x0a,0x7e]
+0x7c,0xa2,0x0a,0x7e
+
+# GFX12: v_cvt_f16_i16_e32 v5, -1                ; encoding: [0xc1,0xa2,0x0a,0x7e]
+0xc1,0xa2,0x0a,0x7e
+
+# GFX12: v_cvt_f16_i16_e32 v5, 0x3800
+0xf0,0xa2,0x0a,0x7e
+
+# GFX12: v_cvt_f16_i16_e32 v5, src_scc           ; encoding: [0xfd,0xa2,0x0a,0x7e]
+0xfd,0xa2,0x0a,0x7e
+
+# GFX12: v_cvt_f16_i16_e32 v127, 0xfe0b          ; encoding: [0xff,0xa2,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+0xff,0xa2,0xfe,0x7e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cvt_f16_u16_e32 v5, v1                ; encoding: [0x01,0xa1,0x0a,0x7e]
+0x01,0xa1,0x0a,0x7e
+
+# GFX12: v_cvt_f16_u16_e32 v5, v127              ; encoding: [0x7f,0xa1,0x0a,0x7e]
+0x7f,0xa1,0x0a,0x7e
+
+# GFX12: v_cvt_f16_u16_e32 v5, s1                ; encoding: [0x01,0xa0,0x0a,0x7e]
+0x01,0xa0,0x0a,0x7e
+
+# GFX12: v_cvt_f16_u16_e32 v5, s105              ; encoding: [0x69,0xa0,0x0a,0x7e]
+0x69,0xa0,0x0a,0x7e
+
+# GFX12: v_cvt_f16_u16_e32 v5, vcc_lo            ; encoding: [0x6a,0xa0,0x0a,0x7e]
+0x6a,0xa0,0x0a,0x7e
+
+# GFX12: v_cvt_f16_u16_e32 v5, vcc_hi            ; encoding: [0x6b,0xa0,0x0a,0x7e]
+0x6b,0xa0,0x0a,0x7e
+
+# GFX12: v_cvt_f16_u16_e32 v5, ttmp15            ; encoding: [0x7b,0xa0,0x0a,0x7e]
+0x7b,0xa0,0x0a,0x7e
+
+# GFX12: v_cvt_f16_u16_e32 v5, m0                ; encoding: [0x7d,0xa0,0x0a,0x7e]
+0x7d,0xa0,0x0a,0x7e
+
+# GFX12: v_cvt_f16_u16_e32 v5, exec_lo           ; encoding: [0x7e,0xa0,0x0a,0x7e]
+0x7e,0xa0,0x0a,0x7e
+
+# GFX12: v_cvt_f16_u16_e32 v5, exec_hi           ; encoding: [0x7f,0xa0,0x0a,0x7e]
+0x7f,0xa0,0x0a,0x7e
+
+# GFX12: v_cvt_f16_u16_e32 v5, null              ; encoding: [0x7c,0xa0,0x0a,0x7e]
+0x7c,0xa0,0x0a,0x7e
+
+# GFX12: v_cvt_f16_u16_e32 v5, -1                ; encoding: [0xc1,0xa0,0x0a,0x7e]
+0xc1,0xa0,0x0a,0x7e
+
+# GFX12: v_cvt_f16_u16_e32 v5, 0x3800
+0xf0,0xa0,0x0a,0x7e
+
+# GFX12: v_cvt_f16_u16_e32 v5, src_scc           ; encoding: [0xfd,0xa0,0x0a,0x7e]
+0xfd,0xa0,0x0a,0x7e
+
+# GFX12: v_cvt_f16_u16_e32 v127, 0xfe0b          ; encoding: [0xff,0xa0,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+0xff,0xa0,0xfe,0x7e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cvt_f32_f16_e32 v5, v1                ; encoding: [0x01,0x17,0x0a,0x7e]
+0x01,0x17,0x0a,0x7e
+
+# GFX12: v_cvt_f32_f16_e32 v5, v127              ; encoding: [0x7f,0x17,0x0a,0x7e]
+0x7f,0x17,0x0a,0x7e
+
+# GFX12: v_cvt_f32_f16_e32 v5, s1                ; encoding: [0x01,0x16,0x0a,0x7e]
+0x01,0x16,0x0a,0x7e
+
+# GFX12: v_cvt_f32_f16_e32 v5, s105              ; encoding: [0x69,0x16,0x0a,0x7e]
+0x69,0x16,0x0a,0x7e
+
+# GFX12: v_cvt_f32_f16_e32 v5, vcc_lo            ; encoding: [0x6a,0x16,0x0a,0x7e]
+0x6a,0x16,0x0a,0x7e
+
+# GFX12: v_cvt_f32_f16_e32 v5, vcc_hi            ; encoding: [0x6b,0x16,0x0a,0x7e]
+0x6b,0x16,0x0a,0x7e
+
+# GFX12: v_cvt_f32_f16_e32 v5, ttmp15            ; encoding: [0x7b,0x16,0x0a,0x7e]
+0x7b,0x16,0x0a,0x7e
+
+# GFX12: v_cvt_f32_f16_e32 v5, m0                ; encoding: [0x7d,0x16,0x0a,0x7e]
+0x7d,0x16,0x0a,0x7e
+
+# GFX12: v_cvt_f32_f16_e32 v5, exec_lo           ; encoding: [0x7e,0x16,0x0a,0x7e]
+0x7e,0x16,0x0a,0x7e
+
+# GFX12: v_cvt_f32_f16_e32 v5, exec_hi           ; encoding: [0x7f,0x16,0x0a,0x7e]
+0x7f,0x16,0x0a,0x7e
+
+# GFX12: v_cvt_f32_f16_e32 v5, null              ; encoding: [0x7c,0x16,0x0a,0x7e]
+0x7c,0x16,0x0a,0x7e
+
+# GFX12: v_cvt_f32_f16_e32 v5, -1                ; encoding: [0xc1,0x16,0x0a,0x7e]
+0xc1,0x16,0x0a,0x7e
+
+# GFX12: v_cvt_f32_f16_e32 v5, 0.5               ; encoding: [0xf0,0x16,0x0a,0x7e]
+0xf0,0x16,0x0a,0x7e
+
+# GFX12: v_cvt_f32_f16_e32 v5, src_scc           ; encoding: [0xfd,0x16,0x0a,0x7e]
+0xfd,0x16,0x0a,0x7e
+
+# GFX12: v_cvt_f32_f16_e32 v255, 0xfe0b          ; encoding: [0xff,0x16,0xfe,0x7f,0x0b,0xfe,0x00,0x00]
+0xff,0x16,0xfe,0x7f,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cvt_f32_f64_e32 v5, v[1:2]            ; encoding: [0x01,0x1f,0x0a,0x7e]
+0x01,0x1f,0x0a,0x7e
+
+# GFX12: v_cvt_f32_f64_e32 v5, v[254:255]        ; encoding: [0xfe,0x1f,0x0a,0x7e]
+0xfe,0x1f,0x0a,0x7e
+
+# GFX12: v_cvt_f32_f64_e32 v5, s[2:3]            ; encoding: [0x02,0x1e,0x0a,0x7e]
+0x02,0x1e,0x0a,0x7e
+
+# GFX12: v_cvt_f32_f64_e32 v5, s[104:105]        ; encoding: [0x68,0x1e,0x0a,0x7e]
+0x68,0x1e,0x0a,0x7e
+
+# GFX12: v_cvt_f32_f64_e32 v5, vcc               ; encoding: [0x6a,0x1e,0x0a,0x7e]
+0x6a,0x1e,0x0a,0x7e
+
+# GFX12: v_cvt_f32_f64_e32 v5, ttmp[14:15]       ; encoding: [0x7a,0x1e,0x0a,0x7e]
+0x7a,0x1e,0x0a,0x7e
+
+# GFX12: v_cvt_f32_f64_e32 v5, exec              ; encoding: [0x7e,0x1e,0x0a,0x7e]
+0x7e,0x1e,0x0a,0x7e
+
+# GFX12: v_cvt_f32_f64_e32 v5, null              ; encoding: [0x7c,0x1e,0x0a,0x7e]
+0x7c,0x1e,0x0a,0x7e
+
+# GFX12: v_cvt_f32_f64_e32 v5, -1                ; encoding: [0xc1,0x1e,0x0a,0x7e]
+0xc1,0x1e,0x0a,0x7e
+
+# GFX12: v_cvt_f32_f64_e32 v5, 0.5               ; encoding: [0xf0,0x1e,0x0a,0x7e]
+0xf0,0x1e,0x0a,0x7e
+
+# GFX12: v_cvt_f32_f64_e32 v5, src_scc           ; encoding: [0xfd,0x1e,0x0a,0x7e]
+0xfd,0x1e,0x0a,0x7e
+
+# GFX12: v_cvt_f32_f64_e32 v255, 0xaf123456      ; encoding: [0xff,0x1e,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x1e,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_f32_i32_e32 v5, v1                ; encoding: [0x01,0x0b,0x0a,0x7e]
+0x01,0x0b,0x0a,0x7e
+
+# GFX12: v_cvt_f32_i32_e32 v5, v255              ; encoding: [0xff,0x0b,0x0a,0x7e]
+0xff,0x0b,0x0a,0x7e
+
+# GFX12: v_cvt_f32_i32_e32 v5, s1                ; encoding: [0x01,0x0a,0x0a,0x7e]
+0x01,0x0a,0x0a,0x7e
+
+# GFX12: v_cvt_f32_i32_e32 v5, s105              ; encoding: [0x69,0x0a,0x0a,0x7e]
+0x69,0x0a,0x0a,0x7e
+
+# GFX12: v_cvt_f32_i32_e32 v5, vcc_lo            ; encoding: [0x6a,0x0a,0x0a,0x7e]
+0x6a,0x0a,0x0a,0x7e
+
+# GFX12: v_cvt_f32_i32_e32 v5, vcc_hi            ; encoding: [0x6b,0x0a,0x0a,0x7e]
+0x6b,0x0a,0x0a,0x7e
+
+# GFX12: v_cvt_f32_i32_e32 v5, ttmp15            ; encoding: [0x7b,0x0a,0x0a,0x7e]
+0x7b,0x0a,0x0a,0x7e
+
+# GFX12: v_cvt_f32_i32_e32 v5, m0                ; encoding: [0x7d,0x0a,0x0a,0x7e]
+0x7d,0x0a,0x0a,0x7e
+
+# GFX12: v_cvt_f32_i32_e32 v5, exec_lo           ; encoding: [0x7e,0x0a,0x0a,0x7e]
+0x7e,0x0a,0x0a,0x7e
+
+# GFX12: v_cvt_f32_i32_e32 v5, exec_hi           ; encoding: [0x7f,0x0a,0x0a,0x7e]
+0x7f,0x0a,0x0a,0x7e
+
+# GFX12: v_cvt_f32_i32_e32 v5, null              ; encoding: [0x7c,0x0a,0x0a,0x7e]
+0x7c,0x0a,0x0a,0x7e
+
+# GFX12: v_cvt_f32_i32_e32 v5, -1                ; encoding: [0xc1,0x0a,0x0a,0x7e]
+0xc1,0x0a,0x0a,0x7e
+
+# GFX12: v_cvt_f32_i32_e32 v5, 0.5               ; encoding: [0xf0,0x0a,0x0a,0x7e]
+0xf0,0x0a,0x0a,0x7e
+
+# GFX12: v_cvt_f32_i32_e32 v5, src_scc           ; encoding: [0xfd,0x0a,0x0a,0x7e]
+0xfd,0x0a,0x0a,0x7e
+
+# GFX12: v_cvt_f32_i32_e32 v255, 0xaf123456      ; encoding: [0xff,0x0a,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x0a,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_f32_u32_e32 v5, v1                ; encoding: [0x01,0x0d,0x0a,0x7e]
+0x01,0x0d,0x0a,0x7e
+
+# GFX12: v_cvt_f32_u32_e32 v5, v255              ; encoding: [0xff,0x0d,0x0a,0x7e]
+0xff,0x0d,0x0a,0x7e
+
+# GFX12: v_cvt_f32_u32_e32 v5, s1                ; encoding: [0x01,0x0c,0x0a,0x7e]
+0x01,0x0c,0x0a,0x7e
+
+# GFX12: v_cvt_f32_u32_e32 v5, s105              ; encoding: [0x69,0x0c,0x0a,0x7e]
+0x69,0x0c,0x0a,0x7e
+
+# GFX12: v_cvt_f32_u32_e32 v5, vcc_lo            ; encoding: [0x6a,0x0c,0x0a,0x7e]
+0x6a,0x0c,0x0a,0x7e
+
+# GFX12: v_cvt_f32_u32_e32 v5, vcc_hi            ; encoding: [0x6b,0x0c,0x0a,0x7e]
+0x6b,0x0c,0x0a,0x7e
+
+# GFX12: v_cvt_f32_u32_e32 v5, ttmp15            ; encoding: [0x7b,0x0c,0x0a,0x7e]
+0x7b,0x0c,0x0a,0x7e
+
+# GFX12: v_cvt_f32_u32_e32 v5, m0                ; encoding: [0x7d,0x0c,0x0a,0x7e]
+0x7d,0x0c,0x0a,0x7e
+
+# GFX12: v_cvt_f32_u32_e32 v5, exec_lo           ; encoding: [0x7e,0x0c,0x0a,0x7e]
+0x7e,0x0c,0x0a,0x7e
+
+# GFX12: v_cvt_f32_u32_e32 v5, exec_hi           ; encoding: [0x7f,0x0c,0x0a,0x7e]
+0x7f,0x0c,0x0a,0x7e
+
+# GFX12: v_cvt_f32_u32_e32 v5, null              ; encoding: [0x7c,0x0c,0x0a,0x7e]
+0x7c,0x0c,0x0a,0x7e
+
+# GFX12: v_cvt_f32_u32_e32 v5, -1                ; encoding: [0xc1,0x0c,0x0a,0x7e]
+0xc1,0x0c,0x0a,0x7e
+
+# GFX12: v_cvt_f32_u32_e32 v5, 0.5               ; encoding: [0xf0,0x0c,0x0a,0x7e]
+0xf0,0x0c,0x0a,0x7e
+
+# GFX12: v_cvt_f32_u32_e32 v5, src_scc           ; encoding: [0xfd,0x0c,0x0a,0x7e]
+0xfd,0x0c,0x0a,0x7e
+
+# GFX12: v_cvt_f32_u32_e32 v255, 0xaf123456      ; encoding: [0xff,0x0c,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x0c,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_f32_ubyte0_e32 v5, v1             ; encoding: [0x01,0x23,0x0a,0x7e]
+0x01,0x23,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte0_e32 v5, v255           ; encoding: [0xff,0x23,0x0a,0x7e]
+0xff,0x23,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte0_e32 v5, s1             ; encoding: [0x01,0x22,0x0a,0x7e]
+0x01,0x22,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte0_e32 v5, s105           ; encoding: [0x69,0x22,0x0a,0x7e]
+0x69,0x22,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte0_e32 v5, vcc_lo         ; encoding: [0x6a,0x22,0x0a,0x7e]
+0x6a,0x22,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte0_e32 v5, vcc_hi         ; encoding: [0x6b,0x22,0x0a,0x7e]
+0x6b,0x22,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte0_e32 v5, ttmp15         ; encoding: [0x7b,0x22,0x0a,0x7e]
+0x7b,0x22,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte0_e32 v5, m0             ; encoding: [0x7d,0x22,0x0a,0x7e]
+0x7d,0x22,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte0_e32 v5, exec_lo        ; encoding: [0x7e,0x22,0x0a,0x7e]
+0x7e,0x22,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte0_e32 v5, exec_hi        ; encoding: [0x7f,0x22,0x0a,0x7e]
+0x7f,0x22,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte0_e32 v5, null           ; encoding: [0x7c,0x22,0x0a,0x7e]
+0x7c,0x22,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte0_e32 v5, -1             ; encoding: [0xc1,0x22,0x0a,0x7e]
+0xc1,0x22,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte0_e32 v5, 0.5            ; encoding: [0xf0,0x22,0x0a,0x7e]
+0xf0,0x22,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte0_e32 v5, src_scc        ; encoding: [0xfd,0x22,0x0a,0x7e]
+0xfd,0x22,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte0_e32 v255, 0xaf123456   ; encoding: [0xff,0x22,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x22,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_f32_ubyte1_e32 v5, v1             ; encoding: [0x01,0x25,0x0a,0x7e]
+0x01,0x25,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte1_e32 v5, v255           ; encoding: [0xff,0x25,0x0a,0x7e]
+0xff,0x25,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte1_e32 v5, s1             ; encoding: [0x01,0x24,0x0a,0x7e]
+0x01,0x24,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte1_e32 v5, s105           ; encoding: [0x69,0x24,0x0a,0x7e]
+0x69,0x24,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte1_e32 v5, vcc_lo         ; encoding: [0x6a,0x24,0x0a,0x7e]
+0x6a,0x24,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte1_e32 v5, vcc_hi         ; encoding: [0x6b,0x24,0x0a,0x7e]
+0x6b,0x24,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte1_e32 v5, ttmp15         ; encoding: [0x7b,0x24,0x0a,0x7e]
+0x7b,0x24,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte1_e32 v5, m0             ; encoding: [0x7d,0x24,0x0a,0x7e]
+0x7d,0x24,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte1_e32 v5, exec_lo        ; encoding: [0x7e,0x24,0x0a,0x7e]
+0x7e,0x24,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte1_e32 v5, exec_hi        ; encoding: [0x7f,0x24,0x0a,0x7e]
+0x7f,0x24,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte1_e32 v5, null           ; encoding: [0x7c,0x24,0x0a,0x7e]
+0x7c,0x24,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte1_e32 v5, -1             ; encoding: [0xc1,0x24,0x0a,0x7e]
+0xc1,0x24,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte1_e32 v5, 0.5            ; encoding: [0xf0,0x24,0x0a,0x7e]
+0xf0,0x24,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte1_e32 v5, src_scc        ; encoding: [0xfd,0x24,0x0a,0x7e]
+0xfd,0x24,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte1_e32 v255, 0xaf123456   ; encoding: [0xff,0x24,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x24,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_f32_ubyte2_e32 v5, v1             ; encoding: [0x01,0x27,0x0a,0x7e]
+0x01,0x27,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte2_e32 v5, v255           ; encoding: [0xff,0x27,0x0a,0x7e]
+0xff,0x27,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte2_e32 v5, s1             ; encoding: [0x01,0x26,0x0a,0x7e]
+0x01,0x26,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte2_e32 v5, s105           ; encoding: [0x69,0x26,0x0a,0x7e]
+0x69,0x26,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte2_e32 v5, vcc_lo         ; encoding: [0x6a,0x26,0x0a,0x7e]
+0x6a,0x26,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte2_e32 v5, vcc_hi         ; encoding: [0x6b,0x26,0x0a,0x7e]
+0x6b,0x26,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte2_e32 v5, ttmp15         ; encoding: [0x7b,0x26,0x0a,0x7e]
+0x7b,0x26,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte2_e32 v5, m0             ; encoding: [0x7d,0x26,0x0a,0x7e]
+0x7d,0x26,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte2_e32 v5, exec_lo        ; encoding: [0x7e,0x26,0x0a,0x7e]
+0x7e,0x26,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte2_e32 v5, exec_hi        ; encoding: [0x7f,0x26,0x0a,0x7e]
+0x7f,0x26,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte2_e32 v5, null           ; encoding: [0x7c,0x26,0x0a,0x7e]
+0x7c,0x26,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte2_e32 v5, -1             ; encoding: [0xc1,0x26,0x0a,0x7e]
+0xc1,0x26,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte2_e32 v5, 0.5            ; encoding: [0xf0,0x26,0x0a,0x7e]
+0xf0,0x26,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte2_e32 v5, src_scc        ; encoding: [0xfd,0x26,0x0a,0x7e]
+0xfd,0x26,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte2_e32 v255, 0xaf123456   ; encoding: [0xff,0x26,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x26,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_f32_ubyte3_e32 v5, v1             ; encoding: [0x01,0x29,0x0a,0x7e]
+0x01,0x29,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte3_e32 v5, v255           ; encoding: [0xff,0x29,0x0a,0x7e]
+0xff,0x29,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte3_e32 v5, s1             ; encoding: [0x01,0x28,0x0a,0x7e]
+0x01,0x28,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte3_e32 v5, s105           ; encoding: [0x69,0x28,0x0a,0x7e]
+0x69,0x28,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte3_e32 v5, vcc_lo         ; encoding: [0x6a,0x28,0x0a,0x7e]
+0x6a,0x28,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte3_e32 v5, vcc_hi         ; encoding: [0x6b,0x28,0x0a,0x7e]
+0x6b,0x28,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte3_e32 v5, ttmp15         ; encoding: [0x7b,0x28,0x0a,0x7e]
+0x7b,0x28,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte3_e32 v5, m0             ; encoding: [0x7d,0x28,0x0a,0x7e]
+0x7d,0x28,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte3_e32 v5, exec_lo        ; encoding: [0x7e,0x28,0x0a,0x7e]
+0x7e,0x28,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte3_e32 v5, exec_hi        ; encoding: [0x7f,0x28,0x0a,0x7e]
+0x7f,0x28,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte3_e32 v5, null           ; encoding: [0x7c,0x28,0x0a,0x7e]
+0x7c,0x28,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte3_e32 v5, -1             ; encoding: [0xc1,0x28,0x0a,0x7e]
+0xc1,0x28,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte3_e32 v5, 0.5            ; encoding: [0xf0,0x28,0x0a,0x7e]
+0xf0,0x28,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte3_e32 v5, src_scc        ; encoding: [0xfd,0x28,0x0a,0x7e]
+0xfd,0x28,0x0a,0x7e
+
+# GFX12: v_cvt_f32_ubyte3_e32 v255, 0xaf123456   ; encoding: [0xff,0x28,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x28,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_f64_f32_e32 v[5:6], v1            ; encoding: [0x01,0x21,0x0a,0x7e]
+0x01,0x21,0x0a,0x7e
+
+# GFX12: v_cvt_f64_f32_e32 v[5:6], v255          ; encoding: [0xff,0x21,0x0a,0x7e]
+0xff,0x21,0x0a,0x7e
+
+# GFX12: v_cvt_f64_f32_e32 v[5:6], s1            ; encoding: [0x01,0x20,0x0a,0x7e]
+0x01,0x20,0x0a,0x7e
+
+# GFX12: v_cvt_f64_f32_e32 v[5:6], s105          ; encoding: [0x69,0x20,0x0a,0x7e]
+0x69,0x20,0x0a,0x7e
+
+# GFX12: v_cvt_f64_f32_e32 v[5:6], vcc_lo        ; encoding: [0x6a,0x20,0x0a,0x7e]
+0x6a,0x20,0x0a,0x7e
+
+# GFX12: v_cvt_f64_f32_e32 v[5:6], vcc_hi        ; encoding: [0x6b,0x20,0x0a,0x7e]
+0x6b,0x20,0x0a,0x7e
+
+# GFX12: v_cvt_f64_f32_e32 v[5:6], ttmp15        ; encoding: [0x7b,0x20,0x0a,0x7e]
+0x7b,0x20,0x0a,0x7e
+
+# GFX12: v_cvt_f64_f32_e32 v[5:6], m0            ; encoding: [0x7d,0x20,0x0a,0x7e]
+0x7d,0x20,0x0a,0x7e
+
+# GFX12: v_cvt_f64_f32_e32 v[5:6], exec_lo       ; encoding: [0x7e,0x20,0x0a,0x7e]
+0x7e,0x20,0x0a,0x7e
+
+# GFX12: v_cvt_f64_f32_e32 v[5:6], exec_hi       ; encoding: [0x7f,0x20,0x0a,0x7e]
+0x7f,0x20,0x0a,0x7e
+
+# GFX12: v_cvt_f64_f32_e32 v[5:6], null          ; encoding: [0x7c,0x20,0x0a,0x7e]
+0x7c,0x20,0x0a,0x7e
+
+# GFX12: v_cvt_f64_f32_e32 v[5:6], -1            ; encoding: [0xc1,0x20,0x0a,0x7e]
+0xc1,0x20,0x0a,0x7e
+
+# GFX12: v_cvt_f64_f32_e32 v[5:6], 0.5           ; encoding: [0xf0,0x20,0x0a,0x7e]
+0xf0,0x20,0x0a,0x7e
+
+# GFX12: v_cvt_f64_f32_e32 v[5:6], src_scc       ; encoding: [0xfd,0x20,0x0a,0x7e]
+0xfd,0x20,0x0a,0x7e
+
+# GFX12: v_cvt_f64_f32_e32 v[254:255], 0xaf123456 ; encoding: [0xff,0x20,0xfc,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x20,0xfc,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_f64_i32_e32 v[5:6], v1            ; encoding: [0x01,0x09,0x0a,0x7e]
+0x01,0x09,0x0a,0x7e
+
+# GFX12: v_cvt_f64_i32_e32 v[5:6], v255          ; encoding: [0xff,0x09,0x0a,0x7e]
+0xff,0x09,0x0a,0x7e
+
+# GFX12: v_cvt_f64_i32_e32 v[5:6], s1            ; encoding: [0x01,0x08,0x0a,0x7e]
+0x01,0x08,0x0a,0x7e
+
+# GFX12: v_cvt_f64_i32_e32 v[5:6], s105          ; encoding: [0x69,0x08,0x0a,0x7e]
+0x69,0x08,0x0a,0x7e
+
+# GFX12: v_cvt_f64_i32_e32 v[5:6], vcc_lo        ; encoding: [0x6a,0x08,0x0a,0x7e]
+0x6a,0x08,0x0a,0x7e
+
+# GFX12: v_cvt_f64_i32_e32 v[5:6], vcc_hi        ; encoding: [0x6b,0x08,0x0a,0x7e]
+0x6b,0x08,0x0a,0x7e
+
+# GFX12: v_cvt_f64_i32_e32 v[5:6], ttmp15        ; encoding: [0x7b,0x08,0x0a,0x7e]
+0x7b,0x08,0x0a,0x7e
+
+# GFX12: v_cvt_f64_i32_e32 v[5:6], m0            ; encoding: [0x7d,0x08,0x0a,0x7e]
+0x7d,0x08,0x0a,0x7e
+
+# GFX12: v_cvt_f64_i32_e32 v[5:6], exec_lo       ; encoding: [0x7e,0x08,0x0a,0x7e]
+0x7e,0x08,0x0a,0x7e
+
+# GFX12: v_cvt_f64_i32_e32 v[5:6], exec_hi       ; encoding: [0x7f,0x08,0x0a,0x7e]
+0x7f,0x08,0x0a,0x7e
+
+# GFX12: v_cvt_f64_i32_e32 v[5:6], null          ; encoding: [0x7c,0x08,0x0a,0x7e]
+0x7c,0x08,0x0a,0x7e
+
+# GFX12: v_cvt_f64_i32_e32 v[5:6], -1            ; encoding: [0xc1,0x08,0x0a,0x7e]
+0xc1,0x08,0x0a,0x7e
+
+# GFX12: v_cvt_f64_i32_e32 v[5:6], 0.5           ; encoding: [0xf0,0x08,0x0a,0x7e]
+0xf0,0x08,0x0a,0x7e
+
+# GFX12: v_cvt_f64_i32_e32 v[5:6], src_scc       ; encoding: [0xfd,0x08,0x0a,0x7e]
+0xfd,0x08,0x0a,0x7e
+
+# GFX12: v_cvt_f64_i32_e32 v[254:255], 0xaf123456 ; encoding: [0xff,0x08,0xfc,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x08,0xfc,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_f64_u32_e32 v[5:6], v1            ; encoding: [0x01,0x2d,0x0a,0x7e]
+0x01,0x2d,0x0a,0x7e
+
+# GFX12: v_cvt_f64_u32_e32 v[5:6], v255          ; encoding: [0xff,0x2d,0x0a,0x7e]
+0xff,0x2d,0x0a,0x7e
+
+# GFX12: v_cvt_f64_u32_e32 v[5:6], s1            ; encoding: [0x01,0x2c,0x0a,0x7e]
+0x01,0x2c,0x0a,0x7e
+
+# GFX12: v_cvt_f64_u32_e32 v[5:6], s105          ; encoding: [0x69,0x2c,0x0a,0x7e]
+0x69,0x2c,0x0a,0x7e
+
+# GFX12: v_cvt_f64_u32_e32 v[5:6], vcc_lo        ; encoding: [0x6a,0x2c,0x0a,0x7e]
+0x6a,0x2c,0x0a,0x7e
+
+# GFX12: v_cvt_f64_u32_e32 v[5:6], vcc_hi        ; encoding: [0x6b,0x2c,0x0a,0x7e]
+0x6b,0x2c,0x0a,0x7e
+
+# GFX12: v_cvt_f64_u32_e32 v[5:6], ttmp15        ; encoding: [0x7b,0x2c,0x0a,0x7e]
+0x7b,0x2c,0x0a,0x7e
+
+# GFX12: v_cvt_f64_u32_e32 v[5:6], m0            ; encoding: [0x7d,0x2c,0x0a,0x7e]
+0x7d,0x2c,0x0a,0x7e
+
+# GFX12: v_cvt_f64_u32_e32 v[5:6], exec_lo       ; encoding: [0x7e,0x2c,0x0a,0x7e]
+0x7e,0x2c,0x0a,0x7e
+
+# GFX12: v_cvt_f64_u32_e32 v[5:6], exec_hi       ; encoding: [0x7f,0x2c,0x0a,0x7e]
+0x7f,0x2c,0x0a,0x7e
+
+# GFX12: v_cvt_f64_u32_e32 v[5:6], null          ; encoding: [0x7c,0x2c,0x0a,0x7e]
+0x7c,0x2c,0x0a,0x7e
+
+# GFX12: v_cvt_f64_u32_e32 v[5:6], -1            ; encoding: [0xc1,0x2c,0x0a,0x7e]
+0xc1,0x2c,0x0a,0x7e
+
+# GFX12: v_cvt_f64_u32_e32 v[5:6], 0.5           ; encoding: [0xf0,0x2c,0x0a,0x7e]
+0xf0,0x2c,0x0a,0x7e
+
+# GFX12: v_cvt_f64_u32_e32 v[5:6], src_scc       ; encoding: [0xfd,0x2c,0x0a,0x7e]
+0xfd,0x2c,0x0a,0x7e
+
+# GFX12: v_cvt_f64_u32_e32 v[254:255], 0xaf123456 ; encoding: [0xff,0x2c,0xfc,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x2c,0xfc,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_floor_i32_f32_e32 v5, v1          ; encoding: [0x01,0x1b,0x0a,0x7e]
+0x01,0x1b,0x0a,0x7e
+
+# GFX12: v_cvt_floor_i32_f32_e32 v5, v255        ; encoding: [0xff,0x1b,0x0a,0x7e]
+0xff,0x1b,0x0a,0x7e
+
+# GFX12: v_cvt_floor_i32_f32_e32 v5, s1          ; encoding: [0x01,0x1a,0x0a,0x7e]
+0x01,0x1a,0x0a,0x7e
+
+# GFX12: v_cvt_floor_i32_f32_e32 v5, s105        ; encoding: [0x69,0x1a,0x0a,0x7e]
+0x69,0x1a,0x0a,0x7e
+
+# GFX12: v_cvt_floor_i32_f32_e32 v5, vcc_lo      ; encoding: [0x6a,0x1a,0x0a,0x7e]
+0x6a,0x1a,0x0a,0x7e
+
+# GFX12: v_cvt_floor_i32_f32_e32 v5, vcc_hi      ; encoding: [0x6b,0x1a,0x0a,0x7e]
+0x6b,0x1a,0x0a,0x7e
+
+# GFX12: v_cvt_floor_i32_f32_e32 v5, ttmp15      ; encoding: [0x7b,0x1a,0x0a,0x7e]
+0x7b,0x1a,0x0a,0x7e
+
+# GFX12: v_cvt_floor_i32_f32_e32 v5, m0          ; encoding: [0x7d,0x1a,0x0a,0x7e]
+0x7d,0x1a,0x0a,0x7e
+
+# GFX12: v_cvt_floor_i32_f32_e32 v5, exec_lo     ; encoding: [0x7e,0x1a,0x0a,0x7e]
+0x7e,0x1a,0x0a,0x7e
+
+# GFX12: v_cvt_floor_i32_f32_e32 v5, exec_hi     ; encoding: [0x7f,0x1a,0x0a,0x7e]
+0x7f,0x1a,0x0a,0x7e
+
+# GFX12: v_cvt_floor_i32_f32_e32 v5, null        ; encoding: [0x7c,0x1a,0x0a,0x7e]
+0x7c,0x1a,0x0a,0x7e
+
+# GFX12: v_cvt_floor_i32_f32_e32 v5, -1          ; encoding: [0xc1,0x1a,0x0a,0x7e]
+0xc1,0x1a,0x0a,0x7e
+
+# GFX12: v_cvt_floor_i32_f32_e32 v5, 0.5         ; encoding: [0xf0,0x1a,0x0a,0x7e]
+0xf0,0x1a,0x0a,0x7e
+
+# GFX12: v_cvt_floor_i32_f32_e32 v5, src_scc     ; encoding: [0xfd,0x1a,0x0a,0x7e]
+0xfd,0x1a,0x0a,0x7e
+
+# GFX12: v_cvt_floor_i32_f32_e32 v255, 0xaf123456 ; encoding: [0xff,0x1a,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x1a,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_i16_f16_e32 v5, v1                ; encoding: [0x01,0xa7,0x0a,0x7e]
+0x01,0xa7,0x0a,0x7e
+
+# GFX12: v_cvt_i16_f16_e32 v5, v127              ; encoding: [0x7f,0xa7,0x0a,0x7e]
+0x7f,0xa7,0x0a,0x7e
+
+# GFX12: v_cvt_i16_f16_e32 v5, s1                ; encoding: [0x01,0xa6,0x0a,0x7e]
+0x01,0xa6,0x0a,0x7e
+
+# GFX12: v_cvt_i16_f16_e32 v5, s105              ; encoding: [0x69,0xa6,0x0a,0x7e]
+0x69,0xa6,0x0a,0x7e
+
+# GFX12: v_cvt_i16_f16_e32 v5, vcc_lo            ; encoding: [0x6a,0xa6,0x0a,0x7e]
+0x6a,0xa6,0x0a,0x7e
+
+# GFX12: v_cvt_i16_f16_e32 v5, vcc_hi            ; encoding: [0x6b,0xa6,0x0a,0x7e]
+0x6b,0xa6,0x0a,0x7e
+
+# GFX12: v_cvt_i16_f16_e32 v5, ttmp15            ; encoding: [0x7b,0xa6,0x0a,0x7e]
+0x7b,0xa6,0x0a,0x7e
+
+# GFX12: v_cvt_i16_f16_e32 v5, m0                ; encoding: [0x7d,0xa6,0x0a,0x7e]
+0x7d,0xa6,0x0a,0x7e
+
+# GFX12: v_cvt_i16_f16_e32 v5, exec_lo           ; encoding: [0x7e,0xa6,0x0a,0x7e]
+0x7e,0xa6,0x0a,0x7e
+
+# GFX12: v_cvt_i16_f16_e32 v5, exec_hi           ; encoding: [0x7f,0xa6,0x0a,0x7e]
+0x7f,0xa6,0x0a,0x7e
+
+# GFX12: v_cvt_i16_f16_e32 v5, null              ; encoding: [0x7c,0xa6,0x0a,0x7e]
+0x7c,0xa6,0x0a,0x7e
+
+# GFX12: v_cvt_i16_f16_e32 v5, -1                ; encoding: [0xc1,0xa6,0x0a,0x7e]
+0xc1,0xa6,0x0a,0x7e
+
+# GFX12: v_cvt_i16_f16_e32 v5, 0.5               ; encoding: [0xf0,0xa6,0x0a,0x7e]
+0xf0,0xa6,0x0a,0x7e
+
+# GFX12: v_cvt_i16_f16_e32 v5, src_scc           ; encoding: [0xfd,0xa6,0x0a,0x7e]
+0xfd,0xa6,0x0a,0x7e
+
+# GFX12: v_cvt_i16_f16_e32 v127, 0xfe0b          ; encoding: [0xff,0xa6,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+0xff,0xa6,0xfe,0x7e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cvt_i32_f32_e32 v5, v1                ; encoding: [0x01,0x11,0x0a,0x7e]
+0x01,0x11,0x0a,0x7e
+
+# GFX12: v_cvt_i32_f32_e32 v5, v255              ; encoding: [0xff,0x11,0x0a,0x7e]
+0xff,0x11,0x0a,0x7e
+
+# GFX12: v_cvt_i32_f32_e32 v5, s1                ; encoding: [0x01,0x10,0x0a,0x7e]
+0x01,0x10,0x0a,0x7e
+
+# GFX12: v_cvt_i32_f32_e32 v5, s105              ; encoding: [0x69,0x10,0x0a,0x7e]
+0x69,0x10,0x0a,0x7e
+
+# GFX12: v_cvt_i32_f32_e32 v5, vcc_lo            ; encoding: [0x6a,0x10,0x0a,0x7e]
+0x6a,0x10,0x0a,0x7e
+
+# GFX12: v_cvt_i32_f32_e32 v5, vcc_hi            ; encoding: [0x6b,0x10,0x0a,0x7e]
+0x6b,0x10,0x0a,0x7e
+
+# GFX12: v_cvt_i32_f32_e32 v5, ttmp15            ; encoding: [0x7b,0x10,0x0a,0x7e]
+0x7b,0x10,0x0a,0x7e
+
+# GFX12: v_cvt_i32_f32_e32 v5, m0                ; encoding: [0x7d,0x10,0x0a,0x7e]
+0x7d,0x10,0x0a,0x7e
+
+# GFX12: v_cvt_i32_f32_e32 v5, exec_lo           ; encoding: [0x7e,0x10,0x0a,0x7e]
+0x7e,0x10,0x0a,0x7e
+
+# GFX12: v_cvt_i32_f32_e32 v5, exec_hi           ; encoding: [0x7f,0x10,0x0a,0x7e]
+0x7f,0x10,0x0a,0x7e
+
+# GFX12: v_cvt_i32_f32_e32 v5, null              ; encoding: [0x7c,0x10,0x0a,0x7e]
+0x7c,0x10,0x0a,0x7e
+
+# GFX12: v_cvt_i32_f32_e32 v5, -1                ; encoding: [0xc1,0x10,0x0a,0x7e]
+0xc1,0x10,0x0a,0x7e
+
+# GFX12: v_cvt_i32_f32_e32 v5, 0.5               ; encoding: [0xf0,0x10,0x0a,0x7e]
+0xf0,0x10,0x0a,0x7e
+
+# GFX12: v_cvt_i32_f32_e32 v5, src_scc           ; encoding: [0xfd,0x10,0x0a,0x7e]
+0xfd,0x10,0x0a,0x7e
+
+# GFX12: v_cvt_i32_f32_e32 v255, 0xaf123456      ; encoding: [0xff,0x10,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x10,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_i32_f64_e32 v5, v[1:2]            ; encoding: [0x01,0x07,0x0a,0x7e]
+0x01,0x07,0x0a,0x7e
+
+# GFX12: v_cvt_i32_f64_e32 v5, v[254:255]        ; encoding: [0xfe,0x07,0x0a,0x7e]
+0xfe,0x07,0x0a,0x7e
+
+# GFX12: v_cvt_i32_f64_e32 v5, s[2:3]            ; encoding: [0x02,0x06,0x0a,0x7e]
+0x02,0x06,0x0a,0x7e
+
+# GFX12: v_cvt_i32_f64_e32 v5, s[104:105]        ; encoding: [0x68,0x06,0x0a,0x7e]
+0x68,0x06,0x0a,0x7e
+
+# GFX12: v_cvt_i32_f64_e32 v5, vcc               ; encoding: [0x6a,0x06,0x0a,0x7e]
+0x6a,0x06,0x0a,0x7e
+
+# GFX12: v_cvt_i32_f64_e32 v5, ttmp[14:15]       ; encoding: [0x7a,0x06,0x0a,0x7e]
+0x7a,0x06,0x0a,0x7e
+
+# GFX12: v_cvt_i32_f64_e32 v5, exec              ; encoding: [0x7e,0x06,0x0a,0x7e]
+0x7e,0x06,0x0a,0x7e
+
+# GFX12: v_cvt_i32_f64_e32 v5, null              ; encoding: [0x7c,0x06,0x0a,0x7e]
+0x7c,0x06,0x0a,0x7e
+
+# GFX12: v_cvt_i32_f64_e32 v5, -1                ; encoding: [0xc1,0x06,0x0a,0x7e]
+0xc1,0x06,0x0a,0x7e
+
+# GFX12: v_cvt_i32_f64_e32 v5, 0.5               ; encoding: [0xf0,0x06,0x0a,0x7e]
+0xf0,0x06,0x0a,0x7e
+
+# GFX12: v_cvt_i32_f64_e32 v5, src_scc           ; encoding: [0xfd,0x06,0x0a,0x7e]
+0xfd,0x06,0x0a,0x7e
+
+# GFX12: v_cvt_i32_f64_e32 v255, 0xaf123456      ; encoding: [0xff,0x06,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x06,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_i32_i16_e32 v5, v1                ; encoding: [0x01,0xd5,0x0a,0x7e]
+0x01,0xd5,0x0a,0x7e
+
+# GFX12: v_cvt_i32_i16_e32 v5, v127              ; encoding: [0x7f,0xd5,0x0a,0x7e]
+0x7f,0xd5,0x0a,0x7e
+
+# GFX12: v_cvt_i32_i16_e32 v5, s1                ; encoding: [0x01,0xd4,0x0a,0x7e]
+0x01,0xd4,0x0a,0x7e
+
+# GFX12: v_cvt_i32_i16_e32 v5, s105              ; encoding: [0x69,0xd4,0x0a,0x7e]
+0x69,0xd4,0x0a,0x7e
+
+# GFX12: v_cvt_i32_i16_e32 v5, vcc_lo            ; encoding: [0x6a,0xd4,0x0a,0x7e]
+0x6a,0xd4,0x0a,0x7e
+
+# GFX12: v_cvt_i32_i16_e32 v5, vcc_hi            ; encoding: [0x6b,0xd4,0x0a,0x7e]
+0x6b,0xd4,0x0a,0x7e
+
+# GFX12: v_cvt_i32_i16_e32 v5, ttmp15            ; encoding: [0x7b,0xd4,0x0a,0x7e]
+0x7b,0xd4,0x0a,0x7e
+
+# GFX12: v_cvt_i32_i16_e32 v5, m0                ; encoding: [0x7d,0xd4,0x0a,0x7e]
+0x7d,0xd4,0x0a,0x7e
+
+# GFX12: v_cvt_i32_i16_e32 v5, exec_lo           ; encoding: [0x7e,0xd4,0x0a,0x7e]
+0x7e,0xd4,0x0a,0x7e
+
+# GFX12: v_cvt_i32_i16_e32 v5, exec_hi           ; encoding: [0x7f,0xd4,0x0a,0x7e]
+0x7f,0xd4,0x0a,0x7e
+
+# GFX12: v_cvt_i32_i16_e32 v5, null              ; encoding: [0x7c,0xd4,0x0a,0x7e]
+0x7c,0xd4,0x0a,0x7e
+
+# GFX12: v_cvt_i32_i16_e32 v5, -1                ; encoding: [0xc1,0xd4,0x0a,0x7e]
+0xc1,0xd4,0x0a,0x7e
+
+# GFX12: v_cvt_i32_i16_e32 v5, 0x3800
+0xf0,0xd4,0x0a,0x7e
+
+# GFX12: v_cvt_i32_i16_e32 v5, src_scc           ; encoding: [0xfd,0xd4,0x0a,0x7e]
+0xfd,0xd4,0x0a,0x7e
+
+# GFX12: v_cvt_i32_i16_e32 v255, 0xfe0b          ; encoding: [0xff,0xd4,0xfe,0x7f,0x0b,0xfe,0x00,0x00]
+0xff,0xd4,0xfe,0x7f,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cvt_nearest_i32_f32_e32 v5, v1        ; encoding: [0x01,0x19,0x0a,0x7e]
+0x01,0x19,0x0a,0x7e
+
+# GFX12: v_cvt_nearest_i32_f32_e32 v5, v255      ; encoding: [0xff,0x19,0x0a,0x7e]
+0xff,0x19,0x0a,0x7e
+
+# GFX12: v_cvt_nearest_i32_f32_e32 v5, s1        ; encoding: [0x01,0x18,0x0a,0x7e]
+0x01,0x18,0x0a,0x7e
+
+# GFX12: v_cvt_nearest_i32_f32_e32 v5, s105      ; encoding: [0x69,0x18,0x0a,0x7e]
+0x69,0x18,0x0a,0x7e
+
+# GFX12: v_cvt_nearest_i32_f32_e32 v5, vcc_lo    ; encoding: [0x6a,0x18,0x0a,0x7e]
+0x6a,0x18,0x0a,0x7e
+
+# GFX12: v_cvt_nearest_i32_f32_e32 v5, vcc_hi    ; encoding: [0x6b,0x18,0x0a,0x7e]
+0x6b,0x18,0x0a,0x7e
+
+# GFX12: v_cvt_nearest_i32_f32_e32 v5, ttmp15    ; encoding: [0x7b,0x18,0x0a,0x7e]
+0x7b,0x18,0x0a,0x7e
+
+# GFX12: v_cvt_nearest_i32_f32_e32 v5, m0        ; encoding: [0x7d,0x18,0x0a,0x7e]
+0x7d,0x18,0x0a,0x7e
+
+# GFX12: v_cvt_nearest_i32_f32_e32 v5, exec_lo   ; encoding: [0x7e,0x18,0x0a,0x7e]
+0x7e,0x18,0x0a,0x7e
+
+# GFX12: v_cvt_nearest_i32_f32_e32 v5, exec_hi   ; encoding: [0x7f,0x18,0x0a,0x7e]
+0x7f,0x18,0x0a,0x7e
+
+# GFX12: v_cvt_nearest_i32_f32_e32 v5, null      ; encoding: [0x7c,0x18,0x0a,0x7e]
+0x7c,0x18,0x0a,0x7e
+
+# GFX12: v_cvt_nearest_i32_f32_e32 v5, -1        ; encoding: [0xc1,0x18,0x0a,0x7e]
+0xc1,0x18,0x0a,0x7e
+
+# GFX12: v_cvt_nearest_i32_f32_e32 v5, 0.5       ; encoding: [0xf0,0x18,0x0a,0x7e]
+0xf0,0x18,0x0a,0x7e
+
+# GFX12: v_cvt_nearest_i32_f32_e32 v5, src_scc   ; encoding: [0xfd,0x18,0x0a,0x7e]
+0xfd,0x18,0x0a,0x7e
+
+# GFX12: v_cvt_nearest_i32_f32_e32 v255, 0xaf123456 ; encoding: [0xff,0x18,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x18,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_norm_i16_f16_e32 v5, v1           ; encoding: [0x01,0xc7,0x0a,0x7e]
+0x01,0xc7,0x0a,0x7e
+
+# GFX12: v_cvt_norm_i16_f16_e32 v5, v127         ; encoding: [0x7f,0xc7,0x0a,0x7e]
+0x7f,0xc7,0x0a,0x7e
+
+# GFX12: v_cvt_norm_i16_f16_e32 v5, s1           ; encoding: [0x01,0xc6,0x0a,0x7e]
+0x01,0xc6,0x0a,0x7e
+
+# GFX12: v_cvt_norm_i16_f16_e32 v5, s105         ; encoding: [0x69,0xc6,0x0a,0x7e]
+0x69,0xc6,0x0a,0x7e
+
+# GFX12: v_cvt_norm_i16_f16_e32 v5, vcc_lo       ; encoding: [0x6a,0xc6,0x0a,0x7e]
+0x6a,0xc6,0x0a,0x7e
+
+# GFX12: v_cvt_norm_i16_f16_e32 v5, vcc_hi       ; encoding: [0x6b,0xc6,0x0a,0x7e]
+0x6b,0xc6,0x0a,0x7e
+
+# GFX12: v_cvt_norm_i16_f16_e32 v5, ttmp15       ; encoding: [0x7b,0xc6,0x0a,0x7e]
+0x7b,0xc6,0x0a,0x7e
+
+# GFX12: v_cvt_norm_i16_f16_e32 v5, m0           ; encoding: [0x7d,0xc6,0x0a,0x7e]
+0x7d,0xc6,0x0a,0x7e
+
+# GFX12: v_cvt_norm_i16_f16_e32 v5, exec_lo      ; encoding: [0x7e,0xc6,0x0a,0x7e]
+0x7e,0xc6,0x0a,0x7e
+
+# GFX12: v_cvt_norm_i16_f16_e32 v5, exec_hi      ; encoding: [0x7f,0xc6,0x0a,0x7e]
+0x7f,0xc6,0x0a,0x7e
+
+# GFX12: v_cvt_norm_i16_f16_e32 v5, null         ; encoding: [0x7c,0xc6,0x0a,0x7e]
+0x7c,0xc6,0x0a,0x7e
+
+# GFX12: v_cvt_norm_i16_f16_e32 v5, -1           ; encoding: [0xc1,0xc6,0x0a,0x7e]
+0xc1,0xc6,0x0a,0x7e
+
+# GFX12: v_cvt_norm_i16_f16_e32 v5, 0.5          ; encoding: [0xf0,0xc6,0x0a,0x7e]
+0xf0,0xc6,0x0a,0x7e
+
+# GFX12: v_cvt_norm_i16_f16_e32 v5, src_scc      ; encoding: [0xfd,0xc6,0x0a,0x7e]
+0xfd,0xc6,0x0a,0x7e
+
+# GFX12: v_cvt_norm_i16_f16_e32 v127, 0xfe0b     ; encoding: [0xff,0xc6,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+0xff,0xc6,0xfe,0x7e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cvt_norm_u16_f16_e32 v5, v1           ; encoding: [0x01,0xc9,0x0a,0x7e]
+0x01,0xc9,0x0a,0x7e
+
+# GFX12: v_cvt_norm_u16_f16_e32 v5, v127         ; encoding: [0x7f,0xc9,0x0a,0x7e]
+0x7f,0xc9,0x0a,0x7e
+
+# GFX12: v_cvt_norm_u16_f16_e32 v5, s1           ; encoding: [0x01,0xc8,0x0a,0x7e]
+0x01,0xc8,0x0a,0x7e
+
+# GFX12: v_cvt_norm_u16_f16_e32 v5, s105         ; encoding: [0x69,0xc8,0x0a,0x7e]
+0x69,0xc8,0x0a,0x7e
+
+# GFX12: v_cvt_norm_u16_f16_e32 v5, vcc_lo       ; encoding: [0x6a,0xc8,0x0a,0x7e]
+0x6a,0xc8,0x0a,0x7e
+
+# GFX12: v_cvt_norm_u16_f16_e32 v5, vcc_hi       ; encoding: [0x6b,0xc8,0x0a,0x7e]
+0x6b,0xc8,0x0a,0x7e
+
+# GFX12: v_cvt_norm_u16_f16_e32 v5, ttmp15       ; encoding: [0x7b,0xc8,0x0a,0x7e]
+0x7b,0xc8,0x0a,0x7e
+
+# GFX12: v_cvt_norm_u16_f16_e32 v5, m0           ; encoding: [0x7d,0xc8,0x0a,0x7e]
+0x7d,0xc8,0x0a,0x7e
+
+# GFX12: v_cvt_norm_u16_f16_e32 v5, exec_lo      ; encoding: [0x7e,0xc8,0x0a,0x7e]
+0x7e,0xc8,0x0a,0x7e
+
+# GFX12: v_cvt_norm_u16_f16_e32 v5, exec_hi      ; encoding: [0x7f,0xc8,0x0a,0x7e]
+0x7f,0xc8,0x0a,0x7e
+
+# GFX12: v_cvt_norm_u16_f16_e32 v5, null         ; encoding: [0x7c,0xc8,0x0a,0x7e]
+0x7c,0xc8,0x0a,0x7e
+
+# GFX12: v_cvt_norm_u16_f16_e32 v5, -1           ; encoding: [0xc1,0xc8,0x0a,0x7e]
+0xc1,0xc8,0x0a,0x7e
+
+# GFX12: v_cvt_norm_u16_f16_e32 v5, 0.5          ; encoding: [0xf0,0xc8,0x0a,0x7e]
+0xf0,0xc8,0x0a,0x7e
+
+# GFX12: v_cvt_norm_u16_f16_e32 v5, src_scc      ; encoding: [0xfd,0xc8,0x0a,0x7e]
+0xfd,0xc8,0x0a,0x7e
+
+# GFX12: v_cvt_norm_u16_f16_e32 v127, 0xfe0b     ; encoding: [0xff,0xc8,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+0xff,0xc8,0xfe,0x7e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cvt_off_f32_i4_e32 v5, v1             ; encoding: [0x01,0x1d,0x0a,0x7e]
+0x01,0x1d,0x0a,0x7e
+
+# GFX12: v_cvt_off_f32_i4_e32 v5, v255           ; encoding: [0xff,0x1d,0x0a,0x7e]
+0xff,0x1d,0x0a,0x7e
+
+# GFX12: v_cvt_off_f32_i4_e32 v5, s1             ; encoding: [0x01,0x1c,0x0a,0x7e]
+0x01,0x1c,0x0a,0x7e
+
+# GFX12: v_cvt_off_f32_i4_e32 v5, s105           ; encoding: [0x69,0x1c,0x0a,0x7e]
+0x69,0x1c,0x0a,0x7e
+
+# GFX12: v_cvt_off_f32_i4_e32 v5, vcc_lo         ; encoding: [0x6a,0x1c,0x0a,0x7e]
+0x6a,0x1c,0x0a,0x7e
+
+# GFX12: v_cvt_off_f32_i4_e32 v5, vcc_hi         ; encoding: [0x6b,0x1c,0x0a,0x7e]
+0x6b,0x1c,0x0a,0x7e
+
+# GFX12: v_cvt_off_f32_i4_e32 v5, ttmp15         ; encoding: [0x7b,0x1c,0x0a,0x7e]
+0x7b,0x1c,0x0a,0x7e
+
+# GFX12: v_cvt_off_f32_i4_e32 v5, m0             ; encoding: [0x7d,0x1c,0x0a,0x7e]
+0x7d,0x1c,0x0a,0x7e
+
+# GFX12: v_cvt_off_f32_i4_e32 v5, exec_lo        ; encoding: [0x7e,0x1c,0x0a,0x7e]
+0x7e,0x1c,0x0a,0x7e
+
+# GFX12: v_cvt_off_f32_i4_e32 v5, exec_hi        ; encoding: [0x7f,0x1c,0x0a,0x7e]
+0x7f,0x1c,0x0a,0x7e
+
+# GFX12: v_cvt_off_f32_i4_e32 v5, null           ; encoding: [0x7c,0x1c,0x0a,0x7e]
+0x7c,0x1c,0x0a,0x7e
+
+# GFX12: v_cvt_off_f32_i4_e32 v5, -1             ; encoding: [0xc1,0x1c,0x0a,0x7e]
+0xc1,0x1c,0x0a,0x7e
+
+# GFX12: v_cvt_off_f32_i4_e32 v5, 0.5            ; encoding: [0xf0,0x1c,0x0a,0x7e]
+0xf0,0x1c,0x0a,0x7e
+
+# GFX12: v_cvt_off_f32_i4_e32 v5, src_scc        ; encoding: [0xfd,0x1c,0x0a,0x7e]
+0xfd,0x1c,0x0a,0x7e
+
+# GFX12: v_cvt_off_f32_i4_e32 v255, 0x4f         ; encoding: [0xff,0x1c,0xfe,0x7f,0x4f,0x00,0x00,0x00]
+0xff,0x1c,0xfe,0x7f,0x4f,0x00,0x00,0x00
+
+# GFX12: v_cvt_u16_f16_e32 v5, v1                ; encoding: [0x01,0xa5,0x0a,0x7e]
+0x01,0xa5,0x0a,0x7e
+
+# GFX12: v_cvt_u16_f16_e32 v5, v127              ; encoding: [0x7f,0xa5,0x0a,0x7e]
+0x7f,0xa5,0x0a,0x7e
+
+# GFX12: v_cvt_u16_f16_e32 v5, s1                ; encoding: [0x01,0xa4,0x0a,0x7e]
+0x01,0xa4,0x0a,0x7e
+
+# GFX12: v_cvt_u16_f16_e32 v5, s105              ; encoding: [0x69,0xa4,0x0a,0x7e]
+0x69,0xa4,0x0a,0x7e
+
+# GFX12: v_cvt_u16_f16_e32 v5, vcc_lo            ; encoding: [0x6a,0xa4,0x0a,0x7e]
+0x6a,0xa4,0x0a,0x7e
+
+# GFX12: v_cvt_u16_f16_e32 v5, vcc_hi            ; encoding: [0x6b,0xa4,0x0a,0x7e]
+0x6b,0xa4,0x0a,0x7e
+
+# GFX12: v_cvt_u16_f16_e32 v5, ttmp15            ; encoding: [0x7b,0xa4,0x0a,0x7e]
+0x7b,0xa4,0x0a,0x7e
+
+# GFX12: v_cvt_u16_f16_e32 v5, m0                ; encoding: [0x7d,0xa4,0x0a,0x7e]
+0x7d,0xa4,0x0a,0x7e
+
+# GFX12: v_cvt_u16_f16_e32 v5, exec_lo           ; encoding: [0x7e,0xa4,0x0a,0x7e]
+0x7e,0xa4,0x0a,0x7e
+
+# GFX12: v_cvt_u16_f16_e32 v5, exec_hi           ; encoding: [0x7f,0xa4,0x0a,0x7e]
+0x7f,0xa4,0x0a,0x7e
+
+# GFX12: v_cvt_u16_f16_e32 v5, null              ; encoding: [0x7c,0xa4,0x0a,0x7e]
+0x7c,0xa4,0x0a,0x7e
+
+# GFX12: v_cvt_u16_f16_e32 v5, -1                ; encoding: [0xc1,0xa4,0x0a,0x7e]
+0xc1,0xa4,0x0a,0x7e
+
+# GFX12: v_cvt_u16_f16_e32 v5, 0.5               ; encoding: [0xf0,0xa4,0x0a,0x7e]
+0xf0,0xa4,0x0a,0x7e
+
+# GFX12: v_cvt_u16_f16_e32 v5, src_scc           ; encoding: [0xfd,0xa4,0x0a,0x7e]
+0xfd,0xa4,0x0a,0x7e
+
+# GFX12: v_cvt_u16_f16_e32 v127, 0xfe0b          ; encoding: [0xff,0xa4,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+0xff,0xa4,0xfe,0x7e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cvt_u32_f32_e32 v5, v1                ; encoding: [0x01,0x0f,0x0a,0x7e]
+0x01,0x0f,0x0a,0x7e
+
+# GFX12: v_cvt_u32_f32_e32 v5, v255              ; encoding: [0xff,0x0f,0x0a,0x7e]
+0xff,0x0f,0x0a,0x7e
+
+# GFX12: v_cvt_u32_f32_e32 v5, s1                ; encoding: [0x01,0x0e,0x0a,0x7e]
+0x01,0x0e,0x0a,0x7e
+
+# GFX12: v_cvt_u32_f32_e32 v5, s105              ; encoding: [0x69,0x0e,0x0a,0x7e]
+0x69,0x0e,0x0a,0x7e
+
+# GFX12: v_cvt_u32_f32_e32 v5, vcc_lo            ; encoding: [0x6a,0x0e,0x0a,0x7e]
+0x6a,0x0e,0x0a,0x7e
+
+# GFX12: v_cvt_u32_f32_e32 v5, vcc_hi            ; encoding: [0x6b,0x0e,0x0a,0x7e]
+0x6b,0x0e,0x0a,0x7e
+
+# GFX12: v_cvt_u32_f32_e32 v5, ttmp15            ; encoding: [0x7b,0x0e,0x0a,0x7e]
+0x7b,0x0e,0x0a,0x7e
+
+# GFX12: v_cvt_u32_f32_e32 v5, m0                ; encoding: [0x7d,0x0e,0x0a,0x7e]
+0x7d,0x0e,0x0a,0x7e
+
+# GFX12: v_cvt_u32_f32_e32 v5, exec_lo           ; encoding: [0x7e,0x0e,0x0a,0x7e]
+0x7e,0x0e,0x0a,0x7e
+
+# GFX12: v_cvt_u32_f32_e32 v5, exec_hi           ; encoding: [0x7f,0x0e,0x0a,0x7e]
+0x7f,0x0e,0x0a,0x7e
+
+# GFX12: v_cvt_u32_f32_e32 v5, null              ; encoding: [0x7c,0x0e,0x0a,0x7e]
+0x7c,0x0e,0x0a,0x7e
+
+# GFX12: v_cvt_u32_f32_e32 v5, -1                ; encoding: [0xc1,0x0e,0x0a,0x7e]
+0xc1,0x0e,0x0a,0x7e
+
+# GFX12: v_cvt_u32_f32_e32 v5, 0.5               ; encoding: [0xf0,0x0e,0x0a,0x7e]
+0xf0,0x0e,0x0a,0x7e
+
+# GFX12: v_cvt_u32_f32_e32 v5, src_scc           ; encoding: [0xfd,0x0e,0x0a,0x7e]
+0xfd,0x0e,0x0a,0x7e
+
+# GFX12: v_cvt_u32_f32_e32 v255, 0xaf123456      ; encoding: [0xff,0x0e,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x0e,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_u32_f64_e32 v5, v[1:2]            ; encoding: [0x01,0x2b,0x0a,0x7e]
+0x01,0x2b,0x0a,0x7e
+
+# GFX12: v_cvt_u32_f64_e32 v5, v[254:255]        ; encoding: [0xfe,0x2b,0x0a,0x7e]
+0xfe,0x2b,0x0a,0x7e
+
+# GFX12: v_cvt_u32_f64_e32 v5, s[2:3]            ; encoding: [0x02,0x2a,0x0a,0x7e]
+0x02,0x2a,0x0a,0x7e
+
+# GFX12: v_cvt_u32_f64_e32 v5, s[104:105]        ; encoding: [0x68,0x2a,0x0a,0x7e]
+0x68,0x2a,0x0a,0x7e
+
+# GFX12: v_cvt_u32_f64_e32 v5, vcc               ; encoding: [0x6a,0x2a,0x0a,0x7e]
+0x6a,0x2a,0x0a,0x7e
+
+# GFX12: v_cvt_u32_f64_e32 v5, ttmp[14:15]       ; encoding: [0x7a,0x2a,0x0a,0x7e]
+0x7a,0x2a,0x0a,0x7e
+
+# GFX12: v_cvt_u32_f64_e32 v5, exec              ; encoding: [0x7e,0x2a,0x0a,0x7e]
+0x7e,0x2a,0x0a,0x7e
+
+# GFX12: v_cvt_u32_f64_e32 v5, null              ; encoding: [0x7c,0x2a,0x0a,0x7e]
+0x7c,0x2a,0x0a,0x7e
+
+# GFX12: v_cvt_u32_f64_e32 v5, -1                ; encoding: [0xc1,0x2a,0x0a,0x7e]
+0xc1,0x2a,0x0a,0x7e
+
+# GFX12: v_cvt_u32_f64_e32 v5, 0.5               ; encoding: [0xf0,0x2a,0x0a,0x7e]
+0xf0,0x2a,0x0a,0x7e
+
+# GFX12: v_cvt_u32_f64_e32 v5, src_scc           ; encoding: [0xfd,0x2a,0x0a,0x7e]
+0xfd,0x2a,0x0a,0x7e
+
+# GFX12: v_cvt_u32_f64_e32 v255, 0xaf123456      ; encoding: [0xff,0x2a,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x2a,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_u32_u16_e32 v5, v1                ; encoding: [0x01,0xd7,0x0a,0x7e]
+0x01,0xd7,0x0a,0x7e
+
+# GFX12: v_cvt_u32_u16_e32 v5, v127              ; encoding: [0x7f,0xd7,0x0a,0x7e]
+0x7f,0xd7,0x0a,0x7e
+
+# GFX12: v_cvt_u32_u16_e32 v5, s1                ; encoding: [0x01,0xd6,0x0a,0x7e]
+0x01,0xd6,0x0a,0x7e
+
+# GFX12: v_cvt_u32_u16_e32 v5, s105              ; encoding: [0x69,0xd6,0x0a,0x7e]
+0x69,0xd6,0x0a,0x7e
+
+# GFX12: v_cvt_u32_u16_e32 v5, vcc_lo            ; encoding: [0x6a,0xd6,0x0a,0x7e]
+0x6a,0xd6,0x0a,0x7e
+
+# GFX12: v_cvt_u32_u16_e32 v5, vcc_hi            ; encoding: [0x6b,0xd6,0x0a,0x7e]
+0x6b,0xd6,0x0a,0x7e
+
+# GFX12: v_cvt_u32_u16_e32 v5, ttmp15            ; encoding: [0x7b,0xd6,0x0a,0x7e]
+0x7b,0xd6,0x0a,0x7e
+
+# GFX12: v_cvt_u32_u16_e32 v5, m0                ; encoding: [0x7d,0xd6,0x0a,0x7e]
+0x7d,0xd6,0x0a,0x7e
+
+# GFX12: v_cvt_u32_u16_e32 v5, exec_lo           ; encoding: [0x7e,0xd6,0x0a,0x7e]
+0x7e,0xd6,0x0a,0x7e
+
+# GFX12: v_cvt_u32_u16_e32 v5, exec_hi           ; encoding: [0x7f,0xd6,0x0a,0x7e]
+0x7f,0xd6,0x0a,0x7e
+
+# GFX12: v_cvt_u32_u16_e32 v5, null              ; encoding: [0x7c,0xd6,0x0a,0x7e]
+0x7c,0xd6,0x0a,0x7e
+
+# GFX12: v_cvt_u32_u16_e32 v5, -1                ; encoding: [0xc1,0xd6,0x0a,0x7e]
+0xc1,0xd6,0x0a,0x7e
+
+# GFX12: v_cvt_u32_u16_e32 v5, 0x3800
+0xf0,0xd6,0x0a,0x7e
+
+# GFX12: v_cvt_u32_u16_e32 v5, src_scc           ; encoding: [0xfd,0xd6,0x0a,0x7e]
+0xfd,0xd6,0x0a,0x7e
+
+# GFX12: v_cvt_u32_u16_e32 v255, 0xfe0b          ; encoding: [0xff,0xd6,0xfe,0x7f,0x0b,0xfe,0x00,0x00]
+0xff,0xd6,0xfe,0x7f,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_exp_f16_e32 v5, v1                    ; encoding: [0x01,0xb1,0x0a,0x7e]
+0x01,0xb1,0x0a,0x7e
+
+# GFX12: v_exp_f16_e32 v5, v127                  ; encoding: [0x7f,0xb1,0x0a,0x7e]
+0x7f,0xb1,0x0a,0x7e
+
+# GFX12: v_exp_f16_e32 v5, s1                    ; encoding: [0x01,0xb0,0x0a,0x7e]
+0x01,0xb0,0x0a,0x7e
+
+# GFX12: v_exp_f16_e32 v5, s105                  ; encoding: [0x69,0xb0,0x0a,0x7e]
+0x69,0xb0,0x0a,0x7e
+
+# GFX12: v_exp_f16_e32 v5, vcc_lo                ; encoding: [0x6a,0xb0,0x0a,0x7e]
+0x6a,0xb0,0x0a,0x7e
+
+# GFX12: v_exp_f16_e32 v5, vcc_hi                ; encoding: [0x6b,0xb0,0x0a,0x7e]
+0x6b,0xb0,0x0a,0x7e
+
+# GFX12: v_exp_f16_e32 v5, ttmp15                ; encoding: [0x7b,0xb0,0x0a,0x7e]
+0x7b,0xb0,0x0a,0x7e
+
+# GFX12: v_exp_f16_e32 v5, m0                    ; encoding: [0x7d,0xb0,0x0a,0x7e]
+0x7d,0xb0,0x0a,0x7e
+
+# GFX12: v_exp_f16_e32 v5, exec_lo               ; encoding: [0x7e,0xb0,0x0a,0x7e]
+0x7e,0xb0,0x0a,0x7e
+
+# GFX12: v_exp_f16_e32 v5, exec_hi               ; encoding: [0x7f,0xb0,0x0a,0x7e]
+0x7f,0xb0,0x0a,0x7e
+
+# GFX12: v_exp_f16_e32 v5, null                  ; encoding: [0x7c,0xb0,0x0a,0x7e]
+0x7c,0xb0,0x0a,0x7e
+
+# GFX12: v_exp_f16_e32 v5, -1                    ; encoding: [0xc1,0xb0,0x0a,0x7e]
+0xc1,0xb0,0x0a,0x7e
+
+# GFX12: v_exp_f16_e32 v5, 0.5                   ; encoding: [0xf0,0xb0,0x0a,0x7e]
+0xf0,0xb0,0x0a,0x7e
+
+# GFX12: v_exp_f16_e32 v5, src_scc               ; encoding: [0xfd,0xb0,0x0a,0x7e]
+0xfd,0xb0,0x0a,0x7e
+
+# GFX12: v_exp_f16_e32 v127, 0xfe0b              ; encoding: [0xff,0xb0,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+0xff,0xb0,0xfe,0x7e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_exp_f32_e32 v5, v1                    ; encoding: [0x01,0x4b,0x0a,0x7e]
+0x01,0x4b,0x0a,0x7e
+
+# GFX12: v_exp_f32_e32 v5, v255                  ; encoding: [0xff,0x4b,0x0a,0x7e]
+0xff,0x4b,0x0a,0x7e
+
+# GFX12: v_exp_f32_e32 v5, s1                    ; encoding: [0x01,0x4a,0x0a,0x7e]
+0x01,0x4a,0x0a,0x7e
+
+# GFX12: v_exp_f32_e32 v5, s105                  ; encoding: [0x69,0x4a,0x0a,0x7e]
+0x69,0x4a,0x0a,0x7e
+
+# GFX12: v_exp_f32_e32 v5, vcc_lo                ; encoding: [0x6a,0x4a,0x0a,0x7e]
+0x6a,0x4a,0x0a,0x7e
+
+# GFX12: v_exp_f32_e32 v5, vcc_hi                ; encoding: [0x6b,0x4a,0x0a,0x7e]
+0x6b,0x4a,0x0a,0x7e
+
+# GFX12: v_exp_f32_e32 v5, ttmp15                ; encoding: [0x7b,0x4a,0x0a,0x7e]
+0x7b,0x4a,0x0a,0x7e
+
+# GFX12: v_exp_f32_e32 v5, m0                    ; encoding: [0x7d,0x4a,0x0a,0x7e]
+0x7d,0x4a,0x0a,0x7e
+
+# GFX12: v_exp_f32_e32 v5, exec_lo               ; encoding: [0x7e,0x4a,0x0a,0x7e]
+0x7e,0x4a,0x0a,0x7e
+
+# GFX12: v_exp_f32_e32 v5, exec_hi               ; encoding: [0x7f,0x4a,0x0a,0x7e]
+0x7f,0x4a,0x0a,0x7e
+
+# GFX12: v_exp_f32_e32 v5, null                  ; encoding: [0x7c,0x4a,0x0a,0x7e]
+0x7c,0x4a,0x0a,0x7e
+
+# GFX12: v_exp_f32_e32 v5, -1                    ; encoding: [0xc1,0x4a,0x0a,0x7e]
+0xc1,0x4a,0x0a,0x7e
+
+# GFX12: v_exp_f32_e32 v5, 0.5                   ; encoding: [0xf0,0x4a,0x0a,0x7e]
+0xf0,0x4a,0x0a,0x7e
+
+# GFX12: v_exp_f32_e32 v5, src_scc               ; encoding: [0xfd,0x4a,0x0a,0x7e]
+0xfd,0x4a,0x0a,0x7e
+
+# GFX12: v_exp_f32_e32 v255, 0xaf123456          ; encoding: [0xff,0x4a,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x4a,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_floor_f16_e32 v5, v1                  ; encoding: [0x01,0xb7,0x0a,0x7e]
+0x01,0xb7,0x0a,0x7e
+
+# GFX12: v_floor_f16_e32 v5, v127                ; encoding: [0x7f,0xb7,0x0a,0x7e]
+0x7f,0xb7,0x0a,0x7e
+
+# GFX12: v_floor_f16_e32 v5, s1                  ; encoding: [0x01,0xb6,0x0a,0x7e]
+0x01,0xb6,0x0a,0x7e
+
+# GFX12: v_floor_f16_e32 v5, s105                ; encoding: [0x69,0xb6,0x0a,0x7e]
+0x69,0xb6,0x0a,0x7e
+
+# GFX12: v_floor_f16_e32 v5, vcc_lo              ; encoding: [0x6a,0xb6,0x0a,0x7e]
+0x6a,0xb6,0x0a,0x7e
+
+# GFX12: v_floor_f16_e32 v5, vcc_hi              ; encoding: [0x6b,0xb6,0x0a,0x7e]
+0x6b,0xb6,0x0a,0x7e
+
+# GFX12: v_floor_f16_e32 v5, ttmp15              ; encoding: [0x7b,0xb6,0x0a,0x7e]
+0x7b,0xb6,0x0a,0x7e
+
+# GFX12: v_floor_f16_e32 v5, m0                  ; encoding: [0x7d,0xb6,0x0a,0x7e]
+0x7d,0xb6,0x0a,0x7e
+
+# GFX12: v_floor_f16_e32 v5, exec_lo             ; encoding: [0x7e,0xb6,0x0a,0x7e]
+0x7e,0xb6,0x0a,0x7e
+
+# GFX12: v_floor_f16_e32 v5, exec_hi             ; encoding: [0x7f,0xb6,0x0a,0x7e]
+0x7f,0xb6,0x0a,0x7e
+
+# GFX12: v_floor_f16_e32 v5, null                ; encoding: [0x7c,0xb6,0x0a,0x7e]
+0x7c,0xb6,0x0a,0x7e
+
+# GFX12: v_floor_f16_e32 v5, -1                  ; encoding: [0xc1,0xb6,0x0a,0x7e]
+0xc1,0xb6,0x0a,0x7e
+
+# GFX12: v_floor_f16_e32 v5, 0.5                 ; encoding: [0xf0,0xb6,0x0a,0x7e]
+0xf0,0xb6,0x0a,0x7e
+
+# GFX12: v_floor_f16_e32 v5, src_scc             ; encoding: [0xfd,0xb6,0x0a,0x7e]
+0xfd,0xb6,0x0a,0x7e
+
+# GFX12: v_floor_f16_e32 v127, 0xfe0b            ; encoding: [0xff,0xb6,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+0xff,0xb6,0xfe,0x7e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_floor_f32_e32 v5, v1                  ; encoding: [0x01,0x49,0x0a,0x7e]
+0x01,0x49,0x0a,0x7e
+
+# GFX12: v_floor_f32_e32 v5, v255                ; encoding: [0xff,0x49,0x0a,0x7e]
+0xff,0x49,0x0a,0x7e
+
+# GFX12: v_floor_f32_e32 v5, s1                  ; encoding: [0x01,0x48,0x0a,0x7e]
+0x01,0x48,0x0a,0x7e
+
+# GFX12: v_floor_f32_e32 v5, s105                ; encoding: [0x69,0x48,0x0a,0x7e]
+0x69,0x48,0x0a,0x7e
+
+# GFX12: v_floor_f32_e32 v5, vcc_lo              ; encoding: [0x6a,0x48,0x0a,0x7e]
+0x6a,0x48,0x0a,0x7e
+
+# GFX12: v_floor_f32_e32 v5, vcc_hi              ; encoding: [0x6b,0x48,0x0a,0x7e]
+0x6b,0x48,0x0a,0x7e
+
+# GFX12: v_floor_f32_e32 v5, ttmp15              ; encoding: [0x7b,0x48,0x0a,0x7e]
+0x7b,0x48,0x0a,0x7e
+
+# GFX12: v_floor_f32_e32 v5, m0                  ; encoding: [0x7d,0x48,0x0a,0x7e]
+0x7d,0x48,0x0a,0x7e
+
+# GFX12: v_floor_f32_e32 v5, exec_lo             ; encoding: [0x7e,0x48,0x0a,0x7e]
+0x7e,0x48,0x0a,0x7e
+
+# GFX12: v_floor_f32_e32 v5, exec_hi             ; encoding: [0x7f,0x48,0x0a,0x7e]
+0x7f,0x48,0x0a,0x7e
+
+# GFX12: v_floor_f32_e32 v5, null                ; encoding: [0x7c,0x48,0x0a,0x7e]
+0x7c,0x48,0x0a,0x7e
+
+# GFX12: v_floor_f32_e32 v5, -1                  ; encoding: [0xc1,0x48,0x0a,0x7e]
+0xc1,0x48,0x0a,0x7e
+
+# GFX12: v_floor_f32_e32 v5, 0.5                 ; encoding: [0xf0,0x48,0x0a,0x7e]
+0xf0,0x48,0x0a,0x7e
+
+# GFX12: v_floor_f32_e32 v5, src_scc             ; encoding: [0xfd,0x48,0x0a,0x7e]
+0xfd,0x48,0x0a,0x7e
+
+# GFX12: v_floor_f32_e32 v255, 0xaf123456        ; encoding: [0xff,0x48,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x48,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_floor_f64_e32 v[5:6], v[1:2]          ; encoding: [0x01,0x35,0x0a,0x7e]
+0x01,0x35,0x0a,0x7e
+
+# GFX12: v_floor_f64_e32 v[5:6], v[254:255]      ; encoding: [0xfe,0x35,0x0a,0x7e]
+0xfe,0x35,0x0a,0x7e
+
+# GFX12: v_floor_f64_e32 v[5:6], s[2:3]          ; encoding: [0x02,0x34,0x0a,0x7e]
+0x02,0x34,0x0a,0x7e
+
+# GFX12: v_floor_f64_e32 v[5:6], s[104:105]      ; encoding: [0x68,0x34,0x0a,0x7e]
+0x68,0x34,0x0a,0x7e
+
+# GFX12: v_floor_f64_e32 v[5:6], vcc             ; encoding: [0x6a,0x34,0x0a,0x7e]
+0x6a,0x34,0x0a,0x7e
+
+# GFX12: v_floor_f64_e32 v[5:6], ttmp[14:15]     ; encoding: [0x7a,0x34,0x0a,0x7e]
+0x7a,0x34,0x0a,0x7e
+
+# GFX12: v_floor_f64_e32 v[5:6], exec            ; encoding: [0x7e,0x34,0x0a,0x7e]
+0x7e,0x34,0x0a,0x7e
+
+# GFX12: v_floor_f64_e32 v[5:6], null            ; encoding: [0x7c,0x34,0x0a,0x7e]
+0x7c,0x34,0x0a,0x7e
+
+# GFX12: v_floor_f64_e32 v[5:6], -1              ; encoding: [0xc1,0x34,0x0a,0x7e]
+0xc1,0x34,0x0a,0x7e
+
+# GFX12: v_floor_f64_e32 v[5:6], 0.5             ; encoding: [0xf0,0x34,0x0a,0x7e]
+0xf0,0x34,0x0a,0x7e
+
+# GFX12: v_floor_f64_e32 v[5:6], src_scc         ; encoding: [0xfd,0x34,0x0a,0x7e]
+0xfd,0x34,0x0a,0x7e
+
+# GFX12: v_floor_f64_e32 v[254:255], 0xaf123456  ; encoding: [0xff,0x34,0xfc,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x34,0xfc,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fract_f16_e32 v5, v1                  ; encoding: [0x01,0xbf,0x0a,0x7e]
+0x01,0xbf,0x0a,0x7e
+
+# GFX12: v_fract_f16_e32 v5, v127                ; encoding: [0x7f,0xbf,0x0a,0x7e]
+0x7f,0xbf,0x0a,0x7e
+
+# GFX12: v_fract_f16_e32 v5, s1                  ; encoding: [0x01,0xbe,0x0a,0x7e]
+0x01,0xbe,0x0a,0x7e
+
+# GFX12: v_fract_f16_e32 v5, s105                ; encoding: [0x69,0xbe,0x0a,0x7e]
+0x69,0xbe,0x0a,0x7e
+
+# GFX12: v_fract_f16_e32 v5, vcc_lo              ; encoding: [0x6a,0xbe,0x0a,0x7e]
+0x6a,0xbe,0x0a,0x7e
+
+# GFX12: v_fract_f16_e32 v5, vcc_hi              ; encoding: [0x6b,0xbe,0x0a,0x7e]
+0x6b,0xbe,0x0a,0x7e
+
+# GFX12: v_fract_f16_e32 v5, ttmp15              ; encoding: [0x7b,0xbe,0x0a,0x7e]
+0x7b,0xbe,0x0a,0x7e
+
+# GFX12: v_fract_f16_e32 v5, m0                  ; encoding: [0x7d,0xbe,0x0a,0x7e]
+0x7d,0xbe,0x0a,0x7e
+
+# GFX12: v_fract_f16_e32 v5, exec_lo             ; encoding: [0x7e,0xbe,0x0a,0x7e]
+0x7e,0xbe,0x0a,0x7e
+
+# GFX12: v_fract_f16_e32 v5, exec_hi             ; encoding: [0x7f,0xbe,0x0a,0x7e]
+0x7f,0xbe,0x0a,0x7e
+
+# GFX12: v_fract_f16_e32 v5, null                ; encoding: [0x7c,0xbe,0x0a,0x7e]
+0x7c,0xbe,0x0a,0x7e
+
+# GFX12: v_fract_f16_e32 v5, -1                  ; encoding: [0xc1,0xbe,0x0a,0x7e]
+0xc1,0xbe,0x0a,0x7e
+
+# GFX12: v_fract_f16_e32 v5, 0.5                 ; encoding: [0xf0,0xbe,0x0a,0x7e]
+0xf0,0xbe,0x0a,0x7e
+
+# GFX12: v_fract_f16_e32 v5, src_scc             ; encoding: [0xfd,0xbe,0x0a,0x7e]
+0xfd,0xbe,0x0a,0x7e
+
+# GFX12: v_fract_f16_e32 v127, 0xfe0b            ; encoding: [0xff,0xbe,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+0xff,0xbe,0xfe,0x7e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fract_f32_e32 v5, v1                  ; encoding: [0x01,0x41,0x0a,0x7e]
+0x01,0x41,0x0a,0x7e
+
+# GFX12: v_fract_f32_e32 v5, v255                ; encoding: [0xff,0x41,0x0a,0x7e]
+0xff,0x41,0x0a,0x7e
+
+# GFX12: v_fract_f32_e32 v5, s1                  ; encoding: [0x01,0x40,0x0a,0x7e]
+0x01,0x40,0x0a,0x7e
+
+# GFX12: v_fract_f32_e32 v5, s105                ; encoding: [0x69,0x40,0x0a,0x7e]
+0x69,0x40,0x0a,0x7e
+
+# GFX12: v_fract_f32_e32 v5, vcc_lo              ; encoding: [0x6a,0x40,0x0a,0x7e]
+0x6a,0x40,0x0a,0x7e
+
+# GFX12: v_fract_f32_e32 v5, vcc_hi              ; encoding: [0x6b,0x40,0x0a,0x7e]
+0x6b,0x40,0x0a,0x7e
+
+# GFX12: v_fract_f32_e32 v5, ttmp15              ; encoding: [0x7b,0x40,0x0a,0x7e]
+0x7b,0x40,0x0a,0x7e
+
+# GFX12: v_fract_f32_e32 v5, m0                  ; encoding: [0x7d,0x40,0x0a,0x7e]
+0x7d,0x40,0x0a,0x7e
+
+# GFX12: v_fract_f32_e32 v5, exec_lo             ; encoding: [0x7e,0x40,0x0a,0x7e]
+0x7e,0x40,0x0a,0x7e
+
+# GFX12: v_fract_f32_e32 v5, exec_hi             ; encoding: [0x7f,0x40,0x0a,0x7e]
+0x7f,0x40,0x0a,0x7e
+
+# GFX12: v_fract_f32_e32 v5, null                ; encoding: [0x7c,0x40,0x0a,0x7e]
+0x7c,0x40,0x0a,0x7e
+
+# GFX12: v_fract_f32_e32 v5, -1                  ; encoding: [0xc1,0x40,0x0a,0x7e]
+0xc1,0x40,0x0a,0x7e
+
+# GFX12: v_fract_f32_e32 v5, 0.5                 ; encoding: [0xf0,0x40,0x0a,0x7e]
+0xf0,0x40,0x0a,0x7e
+
+# GFX12: v_fract_f32_e32 v5, src_scc             ; encoding: [0xfd,0x40,0x0a,0x7e]
+0xfd,0x40,0x0a,0x7e
+
+# GFX12: v_fract_f32_e32 v255, 0xaf123456        ; encoding: [0xff,0x40,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x40,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fract_f64_e32 v[5:6], v[1:2]          ; encoding: [0x01,0x7d,0x0a,0x7e]
+0x01,0x7d,0x0a,0x7e
+
+# GFX12: v_fract_f64_e32 v[5:6], v[254:255]      ; encoding: [0xfe,0x7d,0x0a,0x7e]
+0xfe,0x7d,0x0a,0x7e
+
+# GFX12: v_fract_f64_e32 v[5:6], s[2:3]          ; encoding: [0x02,0x7c,0x0a,0x7e]
+0x02,0x7c,0x0a,0x7e
+
+# GFX12: v_fract_f64_e32 v[5:6], s[104:105]      ; encoding: [0x68,0x7c,0x0a,0x7e]
+0x68,0x7c,0x0a,0x7e
+
+# GFX12: v_fract_f64_e32 v[5:6], vcc             ; encoding: [0x6a,0x7c,0x0a,0x7e]
+0x6a,0x7c,0x0a,0x7e
+
+# GFX12: v_fract_f64_e32 v[5:6], ttmp[14:15]     ; encoding: [0x7a,0x7c,0x0a,0x7e]
+0x7a,0x7c,0x0a,0x7e
+
+# GFX12: v_fract_f64_e32 v[5:6], exec            ; encoding: [0x7e,0x7c,0x0a,0x7e]
+0x7e,0x7c,0x0a,0x7e
+
+# GFX12: v_fract_f64_e32 v[5:6], null            ; encoding: [0x7c,0x7c,0x0a,0x7e]
+0x7c,0x7c,0x0a,0x7e
+
+# GFX12: v_fract_f64_e32 v[5:6], -1              ; encoding: [0xc1,0x7c,0x0a,0x7e]
+0xc1,0x7c,0x0a,0x7e
+
+# GFX12: v_fract_f64_e32 v[5:6], 0.5             ; encoding: [0xf0,0x7c,0x0a,0x7e]
+0xf0,0x7c,0x0a,0x7e
+
+# GFX12: v_fract_f64_e32 v[5:6], src_scc         ; encoding: [0xfd,0x7c,0x0a,0x7e]
+0xfd,0x7c,0x0a,0x7e
+
+# GFX12: v_fract_f64_e32 v[254:255], 0xaf123456  ; encoding: [0xff,0x7c,0xfc,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x7c,0xfc,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_frexp_exp_i16_f16_e32 v5, v1          ; encoding: [0x01,0xb5,0x0a,0x7e]
+0x01,0xb5,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i16_f16_e32 v5, v127        ; encoding: [0x7f,0xb5,0x0a,0x7e]
+0x7f,0xb5,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i16_f16_e32 v5, s1          ; encoding: [0x01,0xb4,0x0a,0x7e]
+0x01,0xb4,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i16_f16_e32 v5, s105        ; encoding: [0x69,0xb4,0x0a,0x7e]
+0x69,0xb4,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i16_f16_e32 v5, vcc_lo      ; encoding: [0x6a,0xb4,0x0a,0x7e]
+0x6a,0xb4,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i16_f16_e32 v5, vcc_hi      ; encoding: [0x6b,0xb4,0x0a,0x7e]
+0x6b,0xb4,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i16_f16_e32 v5, ttmp15      ; encoding: [0x7b,0xb4,0x0a,0x7e]
+0x7b,0xb4,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i16_f16_e32 v5, m0          ; encoding: [0x7d,0xb4,0x0a,0x7e]
+0x7d,0xb4,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i16_f16_e32 v5, exec_lo     ; encoding: [0x7e,0xb4,0x0a,0x7e]
+0x7e,0xb4,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i16_f16_e32 v5, exec_hi     ; encoding: [0x7f,0xb4,0x0a,0x7e]
+0x7f,0xb4,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i16_f16_e32 v5, null        ; encoding: [0x7c,0xb4,0x0a,0x7e]
+0x7c,0xb4,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i16_f16_e32 v5, -1          ; encoding: [0xc1,0xb4,0x0a,0x7e]
+0xc1,0xb4,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i16_f16_e32 v5, 0.5         ; encoding: [0xf0,0xb4,0x0a,0x7e]
+0xf0,0xb4,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i16_f16_e32 v5, src_scc     ; encoding: [0xfd,0xb4,0x0a,0x7e]
+0xfd,0xb4,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i16_f16_e32 v127, 0xfe0b    ; encoding: [0xff,0xb4,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+0xff,0xb4,0xfe,0x7e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_frexp_exp_i32_f32_e32 v5, v1          ; encoding: [0x01,0x7f,0x0a,0x7e]
+0x01,0x7f,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i32_f32_e32 v5, v255        ; encoding: [0xff,0x7f,0x0a,0x7e]
+0xff,0x7f,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i32_f32_e32 v5, s1          ; encoding: [0x01,0x7e,0x0a,0x7e]
+0x01,0x7e,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i32_f32_e32 v5, s105        ; encoding: [0x69,0x7e,0x0a,0x7e]
+0x69,0x7e,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i32_f32_e32 v5, vcc_lo      ; encoding: [0x6a,0x7e,0x0a,0x7e]
+0x6a,0x7e,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i32_f32_e32 v5, vcc_hi      ; encoding: [0x6b,0x7e,0x0a,0x7e]
+0x6b,0x7e,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i32_f32_e32 v5, ttmp15      ; encoding: [0x7b,0x7e,0x0a,0x7e]
+0x7b,0x7e,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i32_f32_e32 v5, m0          ; encoding: [0x7d,0x7e,0x0a,0x7e]
+0x7d,0x7e,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i32_f32_e32 v5, exec_lo     ; encoding: [0x7e,0x7e,0x0a,0x7e]
+0x7e,0x7e,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i32_f32_e32 v5, exec_hi     ; encoding: [0x7f,0x7e,0x0a,0x7e]
+0x7f,0x7e,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i32_f32_e32 v5, null        ; encoding: [0x7c,0x7e,0x0a,0x7e]
+0x7c,0x7e,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i32_f32_e32 v5, -1          ; encoding: [0xc1,0x7e,0x0a,0x7e]
+0xc1,0x7e,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i32_f32_e32 v5, 0.5         ; encoding: [0xf0,0x7e,0x0a,0x7e]
+0xf0,0x7e,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i32_f32_e32 v5, src_scc     ; encoding: [0xfd,0x7e,0x0a,0x7e]
+0xfd,0x7e,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i32_f32_e32 v255, 0xaf123456 ; encoding: [0xff,0x7e,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x7e,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_frexp_exp_i32_f64_e32 v5, v[1:2]      ; encoding: [0x01,0x79,0x0a,0x7e]
+0x01,0x79,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i32_f64_e32 v5, v[254:255]  ; encoding: [0xfe,0x79,0x0a,0x7e]
+0xfe,0x79,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i32_f64_e32 v5, s[2:3]      ; encoding: [0x02,0x78,0x0a,0x7e]
+0x02,0x78,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i32_f64_e32 v5, s[104:105]  ; encoding: [0x68,0x78,0x0a,0x7e]
+0x68,0x78,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i32_f64_e32 v5, vcc         ; encoding: [0x6a,0x78,0x0a,0x7e]
+0x6a,0x78,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i32_f64_e32 v5, ttmp[14:15] ; encoding: [0x7a,0x78,0x0a,0x7e]
+0x7a,0x78,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i32_f64_e32 v5, exec        ; encoding: [0x7e,0x78,0x0a,0x7e]
+0x7e,0x78,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i32_f64_e32 v5, null        ; encoding: [0x7c,0x78,0x0a,0x7e]
+0x7c,0x78,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i32_f64_e32 v5, -1          ; encoding: [0xc1,0x78,0x0a,0x7e]
+0xc1,0x78,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i32_f64_e32 v5, 0.5         ; encoding: [0xf0,0x78,0x0a,0x7e]
+0xf0,0x78,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i32_f64_e32 v5, src_scc     ; encoding: [0xfd,0x78,0x0a,0x7e]
+0xfd,0x78,0x0a,0x7e
+
+# GFX12: v_frexp_exp_i32_f64_e32 v255, 0xaf123456 ; encoding: [0xff,0x78,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x78,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_frexp_mant_f16_e32 v5, v1             ; encoding: [0x01,0xb3,0x0a,0x7e]
+0x01,0xb3,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f16_e32 v5, v127           ; encoding: [0x7f,0xb3,0x0a,0x7e]
+0x7f,0xb3,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f16_e32 v5, s1             ; encoding: [0x01,0xb2,0x0a,0x7e]
+0x01,0xb2,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f16_e32 v5, s105           ; encoding: [0x69,0xb2,0x0a,0x7e]
+0x69,0xb2,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f16_e32 v5, vcc_lo         ; encoding: [0x6a,0xb2,0x0a,0x7e]
+0x6a,0xb2,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f16_e32 v5, vcc_hi         ; encoding: [0x6b,0xb2,0x0a,0x7e]
+0x6b,0xb2,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f16_e32 v5, ttmp15         ; encoding: [0x7b,0xb2,0x0a,0x7e]
+0x7b,0xb2,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f16_e32 v5, m0             ; encoding: [0x7d,0xb2,0x0a,0x7e]
+0x7d,0xb2,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f16_e32 v5, exec_lo        ; encoding: [0x7e,0xb2,0x0a,0x7e]
+0x7e,0xb2,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f16_e32 v5, exec_hi        ; encoding: [0x7f,0xb2,0x0a,0x7e]
+0x7f,0xb2,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f16_e32 v5, null           ; encoding: [0x7c,0xb2,0x0a,0x7e]
+0x7c,0xb2,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f16_e32 v5, -1             ; encoding: [0xc1,0xb2,0x0a,0x7e]
+0xc1,0xb2,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f16_e32 v5, 0.5            ; encoding: [0xf0,0xb2,0x0a,0x7e]
+0xf0,0xb2,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f16_e32 v5, src_scc        ; encoding: [0xfd,0xb2,0x0a,0x7e]
+0xfd,0xb2,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f16_e32 v127, 0xfe0b       ; encoding: [0xff,0xb2,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+0xff,0xb2,0xfe,0x7e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_frexp_mant_f32_e32 v5, v1             ; encoding: [0x01,0x81,0x0a,0x7e]
+0x01,0x81,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f32_e32 v5, v255           ; encoding: [0xff,0x81,0x0a,0x7e]
+0xff,0x81,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f32_e32 v5, s1             ; encoding: [0x01,0x80,0x0a,0x7e]
+0x01,0x80,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f32_e32 v5, s105           ; encoding: [0x69,0x80,0x0a,0x7e]
+0x69,0x80,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f32_e32 v5, vcc_lo         ; encoding: [0x6a,0x80,0x0a,0x7e]
+0x6a,0x80,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f32_e32 v5, vcc_hi         ; encoding: [0x6b,0x80,0x0a,0x7e]
+0x6b,0x80,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f32_e32 v5, ttmp15         ; encoding: [0x7b,0x80,0x0a,0x7e]
+0x7b,0x80,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f32_e32 v5, m0             ; encoding: [0x7d,0x80,0x0a,0x7e]
+0x7d,0x80,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f32_e32 v5, exec_lo        ; encoding: [0x7e,0x80,0x0a,0x7e]
+0x7e,0x80,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f32_e32 v5, exec_hi        ; encoding: [0x7f,0x80,0x0a,0x7e]
+0x7f,0x80,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f32_e32 v5, null           ; encoding: [0x7c,0x80,0x0a,0x7e]
+0x7c,0x80,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f32_e32 v5, -1             ; encoding: [0xc1,0x80,0x0a,0x7e]
+0xc1,0x80,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f32_e32 v5, 0.5            ; encoding: [0xf0,0x80,0x0a,0x7e]
+0xf0,0x80,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f32_e32 v5, src_scc        ; encoding: [0xfd,0x80,0x0a,0x7e]
+0xfd,0x80,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f32_e32 v255, 0xaf123456   ; encoding: [0xff,0x80,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x80,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_frexp_mant_f64_e32 v[5:6], v[1:2]     ; encoding: [0x01,0x7b,0x0a,0x7e]
+0x01,0x7b,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f64_e32 v[5:6], v[254:255] ; encoding: [0xfe,0x7b,0x0a,0x7e]
+0xfe,0x7b,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f64_e32 v[5:6], s[2:3]     ; encoding: [0x02,0x7a,0x0a,0x7e]
+0x02,0x7a,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f64_e32 v[5:6], s[104:105] ; encoding: [0x68,0x7a,0x0a,0x7e]
+0x68,0x7a,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f64_e32 v[5:6], vcc        ; encoding: [0x6a,0x7a,0x0a,0x7e]
+0x6a,0x7a,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f64_e32 v[5:6], ttmp[14:15] ; encoding: [0x7a,0x7a,0x0a,0x7e]
+0x7a,0x7a,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f64_e32 v[5:6], exec       ; encoding: [0x7e,0x7a,0x0a,0x7e]
+0x7e,0x7a,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f64_e32 v[5:6], null       ; encoding: [0x7c,0x7a,0x0a,0x7e]
+0x7c,0x7a,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f64_e32 v[5:6], -1         ; encoding: [0xc1,0x7a,0x0a,0x7e]
+0xc1,0x7a,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f64_e32 v[5:6], 0.5        ; encoding: [0xf0,0x7a,0x0a,0x7e]
+0xf0,0x7a,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f64_e32 v[5:6], src_scc    ; encoding: [0xfd,0x7a,0x0a,0x7e]
+0xfd,0x7a,0x0a,0x7e
+
+# GFX12: v_frexp_mant_f64_e32 v[254:255], 0xaf123456 ; encoding: [0xff,0x7a,0xfc,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x7a,0xfc,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_log_f16_e32 v5, v1                    ; encoding: [0x01,0xaf,0x0a,0x7e]
+0x01,0xaf,0x0a,0x7e
+
+# GFX12: v_log_f16_e32 v5, v127                  ; encoding: [0x7f,0xaf,0x0a,0x7e]
+0x7f,0xaf,0x0a,0x7e
+
+# GFX12: v_log_f16_e32 v5, s1                    ; encoding: [0x01,0xae,0x0a,0x7e]
+0x01,0xae,0x0a,0x7e
+
+# GFX12: v_log_f16_e32 v5, s105                  ; encoding: [0x69,0xae,0x0a,0x7e]
+0x69,0xae,0x0a,0x7e
+
+# GFX12: v_log_f16_e32 v5, vcc_lo                ; encoding: [0x6a,0xae,0x0a,0x7e]
+0x6a,0xae,0x0a,0x7e
+
+# GFX12: v_log_f16_e32 v5, vcc_hi                ; encoding: [0x6b,0xae,0x0a,0x7e]
+0x6b,0xae,0x0a,0x7e
+
+# GFX12: v_log_f16_e32 v5, ttmp15                ; encoding: [0x7b,0xae,0x0a,0x7e]
+0x7b,0xae,0x0a,0x7e
+
+# GFX12: v_log_f16_e32 v5, m0                    ; encoding: [0x7d,0xae,0x0a,0x7e]
+0x7d,0xae,0x0a,0x7e
+
+# GFX12: v_log_f16_e32 v5, exec_lo               ; encoding: [0x7e,0xae,0x0a,0x7e]
+0x7e,0xae,0x0a,0x7e
+
+# GFX12: v_log_f16_e32 v5, exec_hi               ; encoding: [0x7f,0xae,0x0a,0x7e]
+0x7f,0xae,0x0a,0x7e
+
+# GFX12: v_log_f16_e32 v5, null                  ; encoding: [0x7c,0xae,0x0a,0x7e]
+0x7c,0xae,0x0a,0x7e
+
+# GFX12: v_log_f16_e32 v5, -1                    ; encoding: [0xc1,0xae,0x0a,0x7e]
+0xc1,0xae,0x0a,0x7e
+
+# GFX12: v_log_f16_e32 v5, 0.5                   ; encoding: [0xf0,0xae,0x0a,0x7e]
+0xf0,0xae,0x0a,0x7e
+
+# GFX12: v_log_f16_e32 v5, src_scc               ; encoding: [0xfd,0xae,0x0a,0x7e]
+0xfd,0xae,0x0a,0x7e
+
+# GFX12: v_log_f16_e32 v127, 0xfe0b              ; encoding: [0xff,0xae,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+0xff,0xae,0xfe,0x7e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_log_f32_e32 v5, v1                    ; encoding: [0x01,0x4f,0x0a,0x7e]
+0x01,0x4f,0x0a,0x7e
+
+# GFX12: v_log_f32_e32 v5, v255                  ; encoding: [0xff,0x4f,0x0a,0x7e]
+0xff,0x4f,0x0a,0x7e
+
+# GFX12: v_log_f32_e32 v5, s1                    ; encoding: [0x01,0x4e,0x0a,0x7e]
+0x01,0x4e,0x0a,0x7e
+
+# GFX12: v_log_f32_e32 v5, s105                  ; encoding: [0x69,0x4e,0x0a,0x7e]
+0x69,0x4e,0x0a,0x7e
+
+# GFX12: v_log_f32_e32 v5, vcc_lo                ; encoding: [0x6a,0x4e,0x0a,0x7e]
+0x6a,0x4e,0x0a,0x7e
+
+# GFX12: v_log_f32_e32 v5, vcc_hi                ; encoding: [0x6b,0x4e,0x0a,0x7e]
+0x6b,0x4e,0x0a,0x7e
+
+# GFX12: v_log_f32_e32 v5, ttmp15                ; encoding: [0x7b,0x4e,0x0a,0x7e]
+0x7b,0x4e,0x0a,0x7e
+
+# GFX12: v_log_f32_e32 v5, m0                    ; encoding: [0x7d,0x4e,0x0a,0x7e]
+0x7d,0x4e,0x0a,0x7e
+
+# GFX12: v_log_f32_e32 v5, exec_lo               ; encoding: [0x7e,0x4e,0x0a,0x7e]
+0x7e,0x4e,0x0a,0x7e
+
+# GFX12: v_log_f32_e32 v5, exec_hi               ; encoding: [0x7f,0x4e,0x0a,0x7e]
+0x7f,0x4e,0x0a,0x7e
+
+# GFX12: v_log_f32_e32 v5, null                  ; encoding: [0x7c,0x4e,0x0a,0x7e]
+0x7c,0x4e,0x0a,0x7e
+
+# GFX12: v_log_f32_e32 v5, -1                    ; encoding: [0xc1,0x4e,0x0a,0x7e]
+0xc1,0x4e,0x0a,0x7e
+
+# GFX12: v_log_f32_e32 v5, 0.5                   ; encoding: [0xf0,0x4e,0x0a,0x7e]
+0xf0,0x4e,0x0a,0x7e
+
+# GFX12: v_log_f32_e32 v5, src_scc               ; encoding: [0xfd,0x4e,0x0a,0x7e]
+0xfd,0x4e,0x0a,0x7e
+
+# GFX12: v_log_f32_e32 v255, 0xaf123456          ; encoding: [0xff,0x4e,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x4e,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mov_b32_e32 v5, v1                    ; encoding: [0x01,0x03,0x0a,0x7e]
+0x01,0x03,0x0a,0x7e
+
+# GFX12: v_mov_b32_e32 v5, v255                  ; encoding: [0xff,0x03,0x0a,0x7e]
+0xff,0x03,0x0a,0x7e
+
+# GFX12: v_mov_b32_e32 v5, s1                    ; encoding: [0x01,0x02,0x0a,0x7e]
+0x01,0x02,0x0a,0x7e
+
+# GFX12: v_mov_b32_e32 v5, s105                  ; encoding: [0x69,0x02,0x0a,0x7e]
+0x69,0x02,0x0a,0x7e
+
+# GFX12: v_mov_b32_e32 v5, vcc_lo                ; encoding: [0x6a,0x02,0x0a,0x7e]
+0x6a,0x02,0x0a,0x7e
+
+# GFX12: v_mov_b32_e32 v5, vcc_hi                ; encoding: [0x6b,0x02,0x0a,0x7e]
+0x6b,0x02,0x0a,0x7e
+
+# GFX12: v_mov_b32_e32 v5, ttmp15                ; encoding: [0x7b,0x02,0x0a,0x7e]
+0x7b,0x02,0x0a,0x7e
+
+# GFX12: v_mov_b32_e32 v5, m0                    ; encoding: [0x7d,0x02,0x0a,0x7e]
+0x7d,0x02,0x0a,0x7e
+
+# GFX12: v_mov_b32_e32 v5, exec_lo               ; encoding: [0x7e,0x02,0x0a,0x7e]
+0x7e,0x02,0x0a,0x7e
+
+# GFX12: v_mov_b32_e32 v5, exec_hi               ; encoding: [0x7f,0x02,0x0a,0x7e]
+0x7f,0x02,0x0a,0x7e
+
+# GFX12: v_mov_b32_e32 v5, null                  ; encoding: [0x7c,0x02,0x0a,0x7e]
+0x7c,0x02,0x0a,0x7e
+
+# GFX12: v_mov_b32_e32 v5, -1                    ; encoding: [0xc1,0x02,0x0a,0x7e]
+0xc1,0x02,0x0a,0x7e
+
+# GFX12: v_mov_b32_e32 v5, 0.5                   ; encoding: [0xf0,0x02,0x0a,0x7e]
+0xf0,0x02,0x0a,0x7e
+
+# GFX12: v_mov_b32_e32 v5, src_scc               ; encoding: [0xfd,0x02,0x0a,0x7e]
+0xfd,0x02,0x0a,0x7e
+
+# GFX12: v_mov_b32_e32 v255, 0xaf123456          ; encoding: [0xff,0x02,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x02,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_movreld_b32_e32 v5, v1                ; encoding: [0x01,0x85,0x0a,0x7e]
+0x01,0x85,0x0a,0x7e
+
+# GFX12: v_movreld_b32_e32 v5, v255              ; encoding: [0xff,0x85,0x0a,0x7e]
+0xff,0x85,0x0a,0x7e
+
+# GFX12: v_movreld_b32_e32 v5, s1                ; encoding: [0x01,0x84,0x0a,0x7e]
+0x01,0x84,0x0a,0x7e
+
+# GFX12: v_movreld_b32_e32 v5, s105              ; encoding: [0x69,0x84,0x0a,0x7e]
+0x69,0x84,0x0a,0x7e
+
+# GFX12: v_movreld_b32_e32 v5, vcc_lo            ; encoding: [0x6a,0x84,0x0a,0x7e]
+0x6a,0x84,0x0a,0x7e
+
+# GFX12: v_movreld_b32_e32 v5, vcc_hi            ; encoding: [0x6b,0x84,0x0a,0x7e]
+0x6b,0x84,0x0a,0x7e
+
+# GFX12: v_movreld_b32_e32 v5, ttmp15            ; encoding: [0x7b,0x84,0x0a,0x7e]
+0x7b,0x84,0x0a,0x7e
+
+# GFX12: v_movreld_b32_e32 v5, m0                ; encoding: [0x7d,0x84,0x0a,0x7e]
+0x7d,0x84,0x0a,0x7e
+
+# GFX12: v_movreld_b32_e32 v5, exec_lo           ; encoding: [0x7e,0x84,0x0a,0x7e]
+0x7e,0x84,0x0a,0x7e
+
+# GFX12: v_movreld_b32_e32 v5, exec_hi           ; encoding: [0x7f,0x84,0x0a,0x7e]
+0x7f,0x84,0x0a,0x7e
+
+# GFX12: v_movreld_b32_e32 v5, null              ; encoding: [0x7c,0x84,0x0a,0x7e]
+0x7c,0x84,0x0a,0x7e
+
+# GFX12: v_movreld_b32_e32 v5, -1                ; encoding: [0xc1,0x84,0x0a,0x7e]
+0xc1,0x84,0x0a,0x7e
+
+# GFX12: v_movreld_b32_e32 v5, 0.5               ; encoding: [0xf0,0x84,0x0a,0x7e]
+0xf0,0x84,0x0a,0x7e
+
+# GFX12: v_movreld_b32_e32 v5, src_scc           ; encoding: [0xfd,0x84,0x0a,0x7e]
+0xfd,0x84,0x0a,0x7e
+
+# GFX12: v_movreld_b32_e32 v255, 0xaf123456      ; encoding: [0xff,0x84,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x84,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_movrels_b32_e32 v5, v1                ; encoding: [0x01,0x87,0x0a,0x7e]
+0x01,0x87,0x0a,0x7e
+
+# GFX12: v_movrels_b32_e32 v255, v255            ; encoding: [0xff,0x87,0xfe,0x7f]
+0xff,0x87,0xfe,0x7f
+
+# GFX12: v_movrelsd_2_b32_e32 v5, v1             ; encoding: [0x01,0x91,0x0a,0x7e]
+0x01,0x91,0x0a,0x7e
+
+# GFX12: v_movrelsd_2_b32_e32 v255, v255         ; encoding: [0xff,0x91,0xfe,0x7f]
+0xff,0x91,0xfe,0x7f
+
+# GFX12: v_movrelsd_b32_e32 v5, v1               ; encoding: [0x01,0x89,0x0a,0x7e]
+0x01,0x89,0x0a,0x7e
+
+# GFX12: v_movrelsd_b32_e32 v255, v255           ; encoding: [0xff,0x89,0xfe,0x7f]
+0xff,0x89,0xfe,0x7f
+
+# GFX12: v_nop                                   ; encoding: [0x00,0x00,0x00,0x7e]
+0x00,0x00,0x00,0x7e
+
+# GFX12: v_not_b16_e32 v5, v1                    ; encoding: [0x01,0xd3,0x0a,0x7e]
+0x01,0xd3,0x0a,0x7e
+
+# GFX12: v_not_b16_e32 v5, v127                  ; encoding: [0x7f,0xd3,0x0a,0x7e]
+0x7f,0xd3,0x0a,0x7e
+
+# GFX12: v_not_b16_e32 v5, s1                    ; encoding: [0x01,0xd2,0x0a,0x7e]
+0x01,0xd2,0x0a,0x7e
+
+# GFX12: v_not_b16_e32 v5, s105                  ; encoding: [0x69,0xd2,0x0a,0x7e]
+0x69,0xd2,0x0a,0x7e
+
+# GFX12: v_not_b16_e32 v5, vcc_lo                ; encoding: [0x6a,0xd2,0x0a,0x7e]
+0x6a,0xd2,0x0a,0x7e
+
+# GFX12: v_not_b16_e32 v5, vcc_hi                ; encoding: [0x6b,0xd2,0x0a,0x7e]
+0x6b,0xd2,0x0a,0x7e
+
+# GFX12: v_not_b16_e32 v5, ttmp15                ; encoding: [0x7b,0xd2,0x0a,0x7e]
+0x7b,0xd2,0x0a,0x7e
+
+# GFX12: v_not_b16_e32 v5, m0                    ; encoding: [0x7d,0xd2,0x0a,0x7e]
+0x7d,0xd2,0x0a,0x7e
+
+# GFX12: v_not_b16_e32 v5, exec_lo               ; encoding: [0x7e,0xd2,0x0a,0x7e]
+0x7e,0xd2,0x0a,0x7e
+
+# GFX12: v_not_b16_e32 v5, exec_hi               ; encoding: [0x7f,0xd2,0x0a,0x7e]
+0x7f,0xd2,0x0a,0x7e
+
+# GFX12: v_not_b16_e32 v5, null                  ; encoding: [0x7c,0xd2,0x0a,0x7e]
+0x7c,0xd2,0x0a,0x7e
+
+# GFX12: v_not_b16_e32 v5, -1                    ; encoding: [0xc1,0xd2,0x0a,0x7e]
+0xc1,0xd2,0x0a,0x7e
+
+# GFX12: v_not_b16_e32 v5, 0x3800
+0xf0,0xd2,0x0a,0x7e
+
+# GFX12: v_not_b16_e32 v5, src_scc               ; encoding: [0xfd,0xd2,0x0a,0x7e]
+0xfd,0xd2,0x0a,0x7e
+
+# GFX12: v_not_b16_e32 v127, 0xfe0b              ; encoding: [0xff,0xd2,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+0xff,0xd2,0xfe,0x7e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_not_b32_e32 v5, v1                    ; encoding: [0x01,0x6f,0x0a,0x7e]
+0x01,0x6f,0x0a,0x7e
+
+# GFX12: v_not_b32_e32 v5, v255                  ; encoding: [0xff,0x6f,0x0a,0x7e]
+0xff,0x6f,0x0a,0x7e
+
+# GFX12: v_not_b32_e32 v5, s1                    ; encoding: [0x01,0x6e,0x0a,0x7e]
+0x01,0x6e,0x0a,0x7e
+
+# GFX12: v_not_b32_e32 v5, s105                  ; encoding: [0x69,0x6e,0x0a,0x7e]
+0x69,0x6e,0x0a,0x7e
+
+# GFX12: v_not_b32_e32 v5, vcc_lo                ; encoding: [0x6a,0x6e,0x0a,0x7e]
+0x6a,0x6e,0x0a,0x7e
+
+# GFX12: v_not_b32_e32 v5, vcc_hi                ; encoding: [0x6b,0x6e,0x0a,0x7e]
+0x6b,0x6e,0x0a,0x7e
+
+# GFX12: v_not_b32_e32 v5, ttmp15                ; encoding: [0x7b,0x6e,0x0a,0x7e]
+0x7b,0x6e,0x0a,0x7e
+
+# GFX12: v_not_b32_e32 v5, m0                    ; encoding: [0x7d,0x6e,0x0a,0x7e]
+0x7d,0x6e,0x0a,0x7e
+
+# GFX12: v_not_b32_e32 v5, exec_lo               ; encoding: [0x7e,0x6e,0x0a,0x7e]
+0x7e,0x6e,0x0a,0x7e
+
+# GFX12: v_not_b32_e32 v5, exec_hi               ; encoding: [0x7f,0x6e,0x0a,0x7e]
+0x7f,0x6e,0x0a,0x7e
+
+# GFX12: v_not_b32_e32 v5, null                  ; encoding: [0x7c,0x6e,0x0a,0x7e]
+0x7c,0x6e,0x0a,0x7e
+
+# GFX12: v_not_b32_e32 v5, -1                    ; encoding: [0xc1,0x6e,0x0a,0x7e]
+0xc1,0x6e,0x0a,0x7e
+
+# GFX12: v_not_b32_e32 v5, 0.5                   ; encoding: [0xf0,0x6e,0x0a,0x7e]
+0xf0,0x6e,0x0a,0x7e
+
+# GFX12: v_not_b32_e32 v5, src_scc               ; encoding: [0xfd,0x6e,0x0a,0x7e]
+0xfd,0x6e,0x0a,0x7e
+
+# GFX12: v_not_b32_e32 v255, 0xaf123456          ; encoding: [0xff,0x6e,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x6e,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_permlane64_b32 v5, v1                 ; encoding: [0x01,0xcf,0x0a,0x7e]
+0x01,0xcf,0x0a,0x7e
+
+# GFX12: v_permlane64_b32 v255, v255             ; encoding: [0xff,0xcf,0xfe,0x7f]
+0xff,0xcf,0xfe,0x7f
+
+# GFX12: v_pipeflush                             ; encoding: [0x00,0x36,0x00,0x7e]
+0x00,0x36,0x00,0x7e
+
+# GFX12: v_rcp_f16_e32 v5, v1                    ; encoding: [0x01,0xa9,0x0a,0x7e]
+0x01,0xa9,0x0a,0x7e
+
+# GFX12: v_rcp_f16_e32 v5, v127                  ; encoding: [0x7f,0xa9,0x0a,0x7e]
+0x7f,0xa9,0x0a,0x7e
+
+# GFX12: v_rcp_f16_e32 v5, s1                    ; encoding: [0x01,0xa8,0x0a,0x7e]
+0x01,0xa8,0x0a,0x7e
+
+# GFX12: v_rcp_f16_e32 v5, s105                  ; encoding: [0x69,0xa8,0x0a,0x7e]
+0x69,0xa8,0x0a,0x7e
+
+# GFX12: v_rcp_f16_e32 v5, vcc_lo                ; encoding: [0x6a,0xa8,0x0a,0x7e]
+0x6a,0xa8,0x0a,0x7e
+
+# GFX12: v_rcp_f16_e32 v5, vcc_hi                ; encoding: [0x6b,0xa8,0x0a,0x7e]
+0x6b,0xa8,0x0a,0x7e
+
+# GFX12: v_rcp_f16_e32 v5, ttmp15                ; encoding: [0x7b,0xa8,0x0a,0x7e]
+0x7b,0xa8,0x0a,0x7e
+
+# GFX12: v_rcp_f16_e32 v5, m0                    ; encoding: [0x7d,0xa8,0x0a,0x7e]
+0x7d,0xa8,0x0a,0x7e
+
+# GFX12: v_rcp_f16_e32 v5, exec_lo               ; encoding: [0x7e,0xa8,0x0a,0x7e]
+0x7e,0xa8,0x0a,0x7e
+
+# GFX12: v_rcp_f16_e32 v5, exec_hi               ; encoding: [0x7f,0xa8,0x0a,0x7e]
+0x7f,0xa8,0x0a,0x7e
+
+# GFX12: v_rcp_f16_e32 v5, null                  ; encoding: [0x7c,0xa8,0x0a,0x7e]
+0x7c,0xa8,0x0a,0x7e
+
+# GFX12: v_rcp_f16_e32 v5, -1                    ; encoding: [0xc1,0xa8,0x0a,0x7e]
+0xc1,0xa8,0x0a,0x7e
+
+# GFX12: v_rcp_f16_e32 v5, 0.5                   ; encoding: [0xf0,0xa8,0x0a,0x7e]
+0xf0,0xa8,0x0a,0x7e
+
+# GFX12: v_rcp_f16_e32 v5, src_scc               ; encoding: [0xfd,0xa8,0x0a,0x7e]
+0xfd,0xa8,0x0a,0x7e
+
+# GFX12: v_rcp_f16_e32 v127, 0xfe0b              ; encoding: [0xff,0xa8,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+0xff,0xa8,0xfe,0x7e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_rcp_f32_e32 v5, v1                    ; encoding: [0x01,0x55,0x0a,0x7e]
+0x01,0x55,0x0a,0x7e
+
+# GFX12: v_rcp_f32_e32 v5, v255                  ; encoding: [0xff,0x55,0x0a,0x7e]
+0xff,0x55,0x0a,0x7e
+
+# GFX12: v_rcp_f32_e32 v5, s1                    ; encoding: [0x01,0x54,0x0a,0x7e]
+0x01,0x54,0x0a,0x7e
+
+# GFX12: v_rcp_f32_e32 v5, s105                  ; encoding: [0x69,0x54,0x0a,0x7e]
+0x69,0x54,0x0a,0x7e
+
+# GFX12: v_rcp_f32_e32 v5, vcc_lo                ; encoding: [0x6a,0x54,0x0a,0x7e]
+0x6a,0x54,0x0a,0x7e
+
+# GFX12: v_rcp_f32_e32 v5, vcc_hi                ; encoding: [0x6b,0x54,0x0a,0x7e]
+0x6b,0x54,0x0a,0x7e
+
+# GFX12: v_rcp_f32_e32 v5, ttmp15                ; encoding: [0x7b,0x54,0x0a,0x7e]
+0x7b,0x54,0x0a,0x7e
+
+# GFX12: v_rcp_f32_e32 v5, m0                    ; encoding: [0x7d,0x54,0x0a,0x7e]
+0x7d,0x54,0x0a,0x7e
+
+# GFX12: v_rcp_f32_e32 v5, exec_lo               ; encoding: [0x7e,0x54,0x0a,0x7e]
+0x7e,0x54,0x0a,0x7e
+
+# GFX12: v_rcp_f32_e32 v5, exec_hi               ; encoding: [0x7f,0x54,0x0a,0x7e]
+0x7f,0x54,0x0a,0x7e
+
+# GFX12: v_rcp_f32_e32 v5, null                  ; encoding: [0x7c,0x54,0x0a,0x7e]
+0x7c,0x54,0x0a,0x7e
+
+# GFX12: v_rcp_f32_e32 v5, -1                    ; encoding: [0xc1,0x54,0x0a,0x7e]
+0xc1,0x54,0x0a,0x7e
+
+# GFX12: v_rcp_f32_e32 v5, 0.5                   ; encoding: [0xf0,0x54,0x0a,0x7e]
+0xf0,0x54,0x0a,0x7e
+
+# GFX12: v_rcp_f32_e32 v5, src_scc               ; encoding: [0xfd,0x54,0x0a,0x7e]
+0xfd,0x54,0x0a,0x7e
+
+# GFX12: v_rcp_f32_e32 v255, 0xaf123456          ; encoding: [0xff,0x54,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x54,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_rcp_f64_e32 v[5:6], v[1:2]            ; encoding: [0x01,0x5f,0x0a,0x7e]
+0x01,0x5f,0x0a,0x7e
+
+# GFX12: v_rcp_f64_e32 v[5:6], v[254:255]        ; encoding: [0xfe,0x5f,0x0a,0x7e]
+0xfe,0x5f,0x0a,0x7e
+
+# GFX12: v_rcp_f64_e32 v[5:6], s[2:3]            ; encoding: [0x02,0x5e,0x0a,0x7e]
+0x02,0x5e,0x0a,0x7e
+
+# GFX12: v_rcp_f64_e32 v[5:6], s[104:105]        ; encoding: [0x68,0x5e,0x0a,0x7e]
+0x68,0x5e,0x0a,0x7e
+
+# GFX12: v_rcp_f64_e32 v[5:6], vcc               ; encoding: [0x6a,0x5e,0x0a,0x7e]
+0x6a,0x5e,0x0a,0x7e
+
+# GFX12: v_rcp_f64_e32 v[5:6], ttmp[14:15]       ; encoding: [0x7a,0x5e,0x0a,0x7e]
+0x7a,0x5e,0x0a,0x7e
+
+# GFX12: v_rcp_f64_e32 v[5:6], exec              ; encoding: [0x7e,0x5e,0x0a,0x7e]
+0x7e,0x5e,0x0a,0x7e
+
+# GFX12: v_rcp_f64_e32 v[5:6], null              ; encoding: [0x7c,0x5e,0x0a,0x7e]
+0x7c,0x5e,0x0a,0x7e
+
+# GFX12: v_rcp_f64_e32 v[5:6], -1                ; encoding: [0xc1,0x5e,0x0a,0x7e]
+0xc1,0x5e,0x0a,0x7e
+
+# GFX12: v_rcp_f64_e32 v[5:6], 0.5               ; encoding: [0xf0,0x5e,0x0a,0x7e]
+0xf0,0x5e,0x0a,0x7e
+
+# GFX12: v_rcp_f64_e32 v[5:6], src_scc           ; encoding: [0xfd,0x5e,0x0a,0x7e]
+0xfd,0x5e,0x0a,0x7e
+
+# GFX12: v_rcp_f64_e32 v[254:255], 0xaf123456    ; encoding: [0xff,0x5e,0xfc,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x5e,0xfc,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_rcp_iflag_f32_e32 v5, v1              ; encoding: [0x01,0x57,0x0a,0x7e]
+0x01,0x57,0x0a,0x7e
+
+# GFX12: v_rcp_iflag_f32_e32 v5, v255            ; encoding: [0xff,0x57,0x0a,0x7e]
+0xff,0x57,0x0a,0x7e
+
+# GFX12: v_rcp_iflag_f32_e32 v5, s1              ; encoding: [0x01,0x56,0x0a,0x7e]
+0x01,0x56,0x0a,0x7e
+
+# GFX12: v_rcp_iflag_f32_e32 v5, s105            ; encoding: [0x69,0x56,0x0a,0x7e]
+0x69,0x56,0x0a,0x7e
+
+# GFX12: v_rcp_iflag_f32_e32 v5, vcc_lo          ; encoding: [0x6a,0x56,0x0a,0x7e]
+0x6a,0x56,0x0a,0x7e
+
+# GFX12: v_rcp_iflag_f32_e32 v5, vcc_hi          ; encoding: [0x6b,0x56,0x0a,0x7e]
+0x6b,0x56,0x0a,0x7e
+
+# GFX12: v_rcp_iflag_f32_e32 v5, ttmp15          ; encoding: [0x7b,0x56,0x0a,0x7e]
+0x7b,0x56,0x0a,0x7e
+
+# GFX12: v_rcp_iflag_f32_e32 v5, m0              ; encoding: [0x7d,0x56,0x0a,0x7e]
+0x7d,0x56,0x0a,0x7e
+
+# GFX12: v_rcp_iflag_f32_e32 v5, exec_lo         ; encoding: [0x7e,0x56,0x0a,0x7e]
+0x7e,0x56,0x0a,0x7e
+
+# GFX12: v_rcp_iflag_f32_e32 v5, exec_hi         ; encoding: [0x7f,0x56,0x0a,0x7e]
+0x7f,0x56,0x0a,0x7e
+
+# GFX12: v_rcp_iflag_f32_e32 v5, null            ; encoding: [0x7c,0x56,0x0a,0x7e]
+0x7c,0x56,0x0a,0x7e
+
+# GFX12: v_rcp_iflag_f32_e32 v5, -1              ; encoding: [0xc1,0x56,0x0a,0x7e]
+0xc1,0x56,0x0a,0x7e
+
+# GFX12: v_rcp_iflag_f32_e32 v5, 0.5             ; encoding: [0xf0,0x56,0x0a,0x7e]
+0xf0,0x56,0x0a,0x7e
+
+# GFX12: v_rcp_iflag_f32_e32 v5, src_scc         ; encoding: [0xfd,0x56,0x0a,0x7e]
+0xfd,0x56,0x0a,0x7e
+
+# GFX12: v_rcp_iflag_f32_e32 v255, 0xaf123456    ; encoding: [0xff,0x56,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x56,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_rndne_f16_e32 v5, v1                  ; encoding: [0x01,0xbd,0x0a,0x7e]
+0x01,0xbd,0x0a,0x7e
+
+# GFX12: v_rndne_f16_e32 v5, v127                ; encoding: [0x7f,0xbd,0x0a,0x7e]
+0x7f,0xbd,0x0a,0x7e
+
+# GFX12: v_rndne_f16_e32 v5, s1                  ; encoding: [0x01,0xbc,0x0a,0x7e]
+0x01,0xbc,0x0a,0x7e
+
+# GFX12: v_rndne_f16_e32 v5, s105                ; encoding: [0x69,0xbc,0x0a,0x7e]
+0x69,0xbc,0x0a,0x7e
+
+# GFX12: v_rndne_f16_e32 v5, vcc_lo              ; encoding: [0x6a,0xbc,0x0a,0x7e]
+0x6a,0xbc,0x0a,0x7e
+
+# GFX12: v_rndne_f16_e32 v5, vcc_hi              ; encoding: [0x6b,0xbc,0x0a,0x7e]
+0x6b,0xbc,0x0a,0x7e
+
+# GFX12: v_rndne_f16_e32 v5, ttmp15              ; encoding: [0x7b,0xbc,0x0a,0x7e]
+0x7b,0xbc,0x0a,0x7e
+
+# GFX12: v_rndne_f16_e32 v5, m0                  ; encoding: [0x7d,0xbc,0x0a,0x7e]
+0x7d,0xbc,0x0a,0x7e
+
+# GFX12: v_rndne_f16_e32 v5, exec_lo             ; encoding: [0x7e,0xbc,0x0a,0x7e]
+0x7e,0xbc,0x0a,0x7e
+
+# GFX12: v_rndne_f16_e32 v5, exec_hi             ; encoding: [0x7f,0xbc,0x0a,0x7e]
+0x7f,0xbc,0x0a,0x7e
+
+# GFX12: v_rndne_f16_e32 v5, null                ; encoding: [0x7c,0xbc,0x0a,0x7e]
+0x7c,0xbc,0x0a,0x7e
+
+# GFX12: v_rndne_f16_e32 v5, -1                  ; encoding: [0xc1,0xbc,0x0a,0x7e]
+0xc1,0xbc,0x0a,0x7e
+
+# GFX12: v_rndne_f16_e32 v5, 0.5                 ; encoding: [0xf0,0xbc,0x0a,0x7e]
+0xf0,0xbc,0x0a,0x7e
+
+# GFX12: v_rndne_f16_e32 v5, src_scc             ; encoding: [0xfd,0xbc,0x0a,0x7e]
+0xfd,0xbc,0x0a,0x7e
+
+# GFX12: v_rndne_f16_e32 v127, 0xfe0b            ; encoding: [0xff,0xbc,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+0xff,0xbc,0xfe,0x7e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_rndne_f32_e32 v5, v1                  ; encoding: [0x01,0x47,0x0a,0x7e]
+0x01,0x47,0x0a,0x7e
+
+# GFX12: v_rndne_f32_e32 v5, v255                ; encoding: [0xff,0x47,0x0a,0x7e]
+0xff,0x47,0x0a,0x7e
+
+# GFX12: v_rndne_f32_e32 v5, s1                  ; encoding: [0x01,0x46,0x0a,0x7e]
+0x01,0x46,0x0a,0x7e
+
+# GFX12: v_rndne_f32_e32 v5, s105                ; encoding: [0x69,0x46,0x0a,0x7e]
+0x69,0x46,0x0a,0x7e
+
+# GFX12: v_rndne_f32_e32 v5, vcc_lo              ; encoding: [0x6a,0x46,0x0a,0x7e]
+0x6a,0x46,0x0a,0x7e
+
+# GFX12: v_rndne_f32_e32 v5, vcc_hi              ; encoding: [0x6b,0x46,0x0a,0x7e]
+0x6b,0x46,0x0a,0x7e
+
+# GFX12: v_rndne_f32_e32 v5, ttmp15              ; encoding: [0x7b,0x46,0x0a,0x7e]
+0x7b,0x46,0x0a,0x7e
+
+# GFX12: v_rndne_f32_e32 v5, m0                  ; encoding: [0x7d,0x46,0x0a,0x7e]
+0x7d,0x46,0x0a,0x7e
+
+# GFX12: v_rndne_f32_e32 v5, exec_lo             ; encoding: [0x7e,0x46,0x0a,0x7e]
+0x7e,0x46,0x0a,0x7e
+
+# GFX12: v_rndne_f32_e32 v5, exec_hi             ; encoding: [0x7f,0x46,0x0a,0x7e]
+0x7f,0x46,0x0a,0x7e
+
+# GFX12: v_rndne_f32_e32 v5, null                ; encoding: [0x7c,0x46,0x0a,0x7e]
+0x7c,0x46,0x0a,0x7e
+
+# GFX12: v_rndne_f32_e32 v5, -1                  ; encoding: [0xc1,0x46,0x0a,0x7e]
+0xc1,0x46,0x0a,0x7e
+
+# GFX12: v_rndne_f32_e32 v5, 0.5                 ; encoding: [0xf0,0x46,0x0a,0x7e]
+0xf0,0x46,0x0a,0x7e
+
+# GFX12: v_rndne_f32_e32 v5, src_scc             ; encoding: [0xfd,0x46,0x0a,0x7e]
+0xfd,0x46,0x0a,0x7e
+
+# GFX12: v_rndne_f32_e32 v255, 0xaf123456        ; encoding: [0xff,0x46,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x46,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_rndne_f64_e32 v[5:6], v[1:2]          ; encoding: [0x01,0x33,0x0a,0x7e]
+0x01,0x33,0x0a,0x7e
+
+# GFX12: v_rndne_f64_e32 v[5:6], v[254:255]      ; encoding: [0xfe,0x33,0x0a,0x7e]
+0xfe,0x33,0x0a,0x7e
+
+# GFX12: v_rndne_f64_e32 v[5:6], s[2:3]          ; encoding: [0x02,0x32,0x0a,0x7e]
+0x02,0x32,0x0a,0x7e
+
+# GFX12: v_rndne_f64_e32 v[5:6], s[104:105]      ; encoding: [0x68,0x32,0x0a,0x7e]
+0x68,0x32,0x0a,0x7e
+
+# GFX12: v_rndne_f64_e32 v[5:6], vcc             ; encoding: [0x6a,0x32,0x0a,0x7e]
+0x6a,0x32,0x0a,0x7e
+
+# GFX12: v_rndne_f64_e32 v[5:6], ttmp[14:15]     ; encoding: [0x7a,0x32,0x0a,0x7e]
+0x7a,0x32,0x0a,0x7e
+
+# GFX12: v_rndne_f64_e32 v[5:6], exec            ; encoding: [0x7e,0x32,0x0a,0x7e]
+0x7e,0x32,0x0a,0x7e
+
+# GFX12: v_rndne_f64_e32 v[5:6], null            ; encoding: [0x7c,0x32,0x0a,0x7e]
+0x7c,0x32,0x0a,0x7e
+
+# GFX12: v_rndne_f64_e32 v[5:6], -1              ; encoding: [0xc1,0x32,0x0a,0x7e]
+0xc1,0x32,0x0a,0x7e
+
+# GFX12: v_rndne_f64_e32 v[5:6], 0.5             ; encoding: [0xf0,0x32,0x0a,0x7e]
+0xf0,0x32,0x0a,0x7e
+
+# GFX12: v_rndne_f64_e32 v[5:6], src_scc         ; encoding: [0xfd,0x32,0x0a,0x7e]
+0xfd,0x32,0x0a,0x7e
+
+# GFX12: v_rndne_f64_e32 v[254:255], 0xaf123456  ; encoding: [0xff,0x32,0xfc,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x32,0xfc,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_rsq_f16_e32 v5, v1                    ; encoding: [0x01,0xad,0x0a,0x7e]
+0x01,0xad,0x0a,0x7e
+
+# GFX12: v_rsq_f16_e32 v5, v127                  ; encoding: [0x7f,0xad,0x0a,0x7e]
+0x7f,0xad,0x0a,0x7e
+
+# GFX12: v_rsq_f16_e32 v5, s1                    ; encoding: [0x01,0xac,0x0a,0x7e]
+0x01,0xac,0x0a,0x7e
+
+# GFX12: v_rsq_f16_e32 v5, s105                  ; encoding: [0x69,0xac,0x0a,0x7e]
+0x69,0xac,0x0a,0x7e
+
+# GFX12: v_rsq_f16_e32 v5, vcc_lo                ; encoding: [0x6a,0xac,0x0a,0x7e]
+0x6a,0xac,0x0a,0x7e
+
+# GFX12: v_rsq_f16_e32 v5, vcc_hi                ; encoding: [0x6b,0xac,0x0a,0x7e]
+0x6b,0xac,0x0a,0x7e
+
+# GFX12: v_rsq_f16_e32 v5, ttmp15                ; encoding: [0x7b,0xac,0x0a,0x7e]
+0x7b,0xac,0x0a,0x7e
+
+# GFX12: v_rsq_f16_e32 v5, m0                    ; encoding: [0x7d,0xac,0x0a,0x7e]
+0x7d,0xac,0x0a,0x7e
+
+# GFX12: v_rsq_f16_e32 v5, exec_lo               ; encoding: [0x7e,0xac,0x0a,0x7e]
+0x7e,0xac,0x0a,0x7e
+
+# GFX12: v_rsq_f16_e32 v5, exec_hi               ; encoding: [0x7f,0xac,0x0a,0x7e]
+0x7f,0xac,0x0a,0x7e
+
+# GFX12: v_rsq_f16_e32 v5, null                  ; encoding: [0x7c,0xac,0x0a,0x7e]
+0x7c,0xac,0x0a,0x7e
+
+# GFX12: v_rsq_f16_e32 v5, -1                    ; encoding: [0xc1,0xac,0x0a,0x7e]
+0xc1,0xac,0x0a,0x7e
+
+# GFX12: v_rsq_f16_e32 v5, 0.5                   ; encoding: [0xf0,0xac,0x0a,0x7e]
+0xf0,0xac,0x0a,0x7e
+
+# GFX12: v_rsq_f16_e32 v5, src_scc               ; encoding: [0xfd,0xac,0x0a,0x7e]
+0xfd,0xac,0x0a,0x7e
+
+# GFX12: v_rsq_f16_e32 v127, 0xfe0b              ; encoding: [0xff,0xac,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+0xff,0xac,0xfe,0x7e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_rsq_f32_e32 v5, v1                    ; encoding: [0x01,0x5d,0x0a,0x7e]
+0x01,0x5d,0x0a,0x7e
+
+# GFX12: v_rsq_f32_e32 v5, v255                  ; encoding: [0xff,0x5d,0x0a,0x7e]
+0xff,0x5d,0x0a,0x7e
+
+# GFX12: v_rsq_f32_e32 v5, s1                    ; encoding: [0x01,0x5c,0x0a,0x7e]
+0x01,0x5c,0x0a,0x7e
+
+# GFX12: v_rsq_f32_e32 v5, s105                  ; encoding: [0x69,0x5c,0x0a,0x7e]
+0x69,0x5c,0x0a,0x7e
+
+# GFX12: v_rsq_f32_e32 v5, vcc_lo                ; encoding: [0x6a,0x5c,0x0a,0x7e]
+0x6a,0x5c,0x0a,0x7e
+
+# GFX12: v_rsq_f32_e32 v5, vcc_hi                ; encoding: [0x6b,0x5c,0x0a,0x7e]
+0x6b,0x5c,0x0a,0x7e
+
+# GFX12: v_rsq_f32_e32 v5, ttmp15                ; encoding: [0x7b,0x5c,0x0a,0x7e]
+0x7b,0x5c,0x0a,0x7e
+
+# GFX12: v_rsq_f32_e32 v5, m0                    ; encoding: [0x7d,0x5c,0x0a,0x7e]
+0x7d,0x5c,0x0a,0x7e
+
+# GFX12: v_rsq_f32_e32 v5, exec_lo               ; encoding: [0x7e,0x5c,0x0a,0x7e]
+0x7e,0x5c,0x0a,0x7e
+
+# GFX12: v_rsq_f32_e32 v5, exec_hi               ; encoding: [0x7f,0x5c,0x0a,0x7e]
+0x7f,0x5c,0x0a,0x7e
+
+# GFX12: v_rsq_f32_e32 v5, null                  ; encoding: [0x7c,0x5c,0x0a,0x7e]
+0x7c,0x5c,0x0a,0x7e
+
+# GFX12: v_rsq_f32_e32 v5, -1                    ; encoding: [0xc1,0x5c,0x0a,0x7e]
+0xc1,0x5c,0x0a,0x7e
+
+# GFX12: v_rsq_f32_e32 v5, 0.5                   ; encoding: [0xf0,0x5c,0x0a,0x7e]
+0xf0,0x5c,0x0a,0x7e
+
+# GFX12: v_rsq_f32_e32 v5, src_scc               ; encoding: [0xfd,0x5c,0x0a,0x7e]
+0xfd,0x5c,0x0a,0x7e
+
+# GFX12: v_rsq_f32_e32 v255, 0xaf123456          ; encoding: [0xff,0x5c,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x5c,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_rsq_f64_e32 v[5:6], v[1:2]            ; encoding: [0x01,0x63,0x0a,0x7e]
+0x01,0x63,0x0a,0x7e
+
+# GFX12: v_rsq_f64_e32 v[5:6], v[254:255]        ; encoding: [0xfe,0x63,0x0a,0x7e]
+0xfe,0x63,0x0a,0x7e
+
+# GFX12: v_rsq_f64_e32 v[5:6], s[2:3]            ; encoding: [0x02,0x62,0x0a,0x7e]
+0x02,0x62,0x0a,0x7e
+
+# GFX12: v_rsq_f64_e32 v[5:6], s[104:105]        ; encoding: [0x68,0x62,0x0a,0x7e]
+0x68,0x62,0x0a,0x7e
+
+# GFX12: v_rsq_f64_e32 v[5:6], vcc               ; encoding: [0x6a,0x62,0x0a,0x7e]
+0x6a,0x62,0x0a,0x7e
+
+# GFX12: v_rsq_f64_e32 v[5:6], ttmp[14:15]       ; encoding: [0x7a,0x62,0x0a,0x7e]
+0x7a,0x62,0x0a,0x7e
+
+# GFX12: v_rsq_f64_e32 v[5:6], exec              ; encoding: [0x7e,0x62,0x0a,0x7e]
+0x7e,0x62,0x0a,0x7e
+
+# GFX12: v_rsq_f64_e32 v[5:6], null              ; encoding: [0x7c,0x62,0x0a,0x7e]
+0x7c,0x62,0x0a,0x7e
+
+# GFX12: v_rsq_f64_e32 v[5:6], -1                ; encoding: [0xc1,0x62,0x0a,0x7e]
+0xc1,0x62,0x0a,0x7e
+
+# GFX12: v_rsq_f64_e32 v[5:6], 0.5               ; encoding: [0xf0,0x62,0x0a,0x7e]
+0xf0,0x62,0x0a,0x7e
+
+# GFX12: v_rsq_f64_e32 v[5:6], src_scc           ; encoding: [0xfd,0x62,0x0a,0x7e]
+0xfd,0x62,0x0a,0x7e
+
+# GFX12: v_rsq_f64_e32 v[254:255], 0xaf123456    ; encoding: [0xff,0x62,0xfc,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x62,0xfc,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_sat_pk_u8_i16_e32 v5, v1              ; encoding: [0x01,0xc5,0x0a,0x7e]
+0x01,0xc5,0x0a,0x7e
+
+# GFX12: v_sat_pk_u8_i16_e32 v5, v255            ; encoding: [0xff,0xc5,0x0a,0x7e]
+0xff,0xc5,0x0a,0x7e
+
+# GFX12: v_sat_pk_u8_i16_e32 v5, s1              ; encoding: [0x01,0xc4,0x0a,0x7e]
+0x01,0xc4,0x0a,0x7e
+
+# GFX12: v_sat_pk_u8_i16_e32 v5, s105            ; encoding: [0x69,0xc4,0x0a,0x7e]
+0x69,0xc4,0x0a,0x7e
+
+# GFX12: v_sat_pk_u8_i16_e32 v5, vcc_lo          ; encoding: [0x6a,0xc4,0x0a,0x7e]
+0x6a,0xc4,0x0a,0x7e
+
+# GFX12: v_sat_pk_u8_i16_e32 v5, vcc_hi          ; encoding: [0x6b,0xc4,0x0a,0x7e]
+0x6b,0xc4,0x0a,0x7e
+
+# GFX12: v_sat_pk_u8_i16_e32 v5, ttmp15          ; encoding: [0x7b,0xc4,0x0a,0x7e]
+0x7b,0xc4,0x0a,0x7e
+
+# GFX12: v_sat_pk_u8_i16_e32 v5, m0              ; encoding: [0x7d,0xc4,0x0a,0x7e]
+0x7d,0xc4,0x0a,0x7e
+
+# GFX12: v_sat_pk_u8_i16_e32 v5, exec_lo         ; encoding: [0x7e,0xc4,0x0a,0x7e]
+0x7e,0xc4,0x0a,0x7e
+
+# GFX12: v_sat_pk_u8_i16_e32 v5, exec_hi         ; encoding: [0x7f,0xc4,0x0a,0x7e]
+0x7f,0xc4,0x0a,0x7e
+
+# GFX12: v_sat_pk_u8_i16_e32 v5, null            ; encoding: [0x7c,0xc4,0x0a,0x7e]
+0x7c,0xc4,0x0a,0x7e
+
+# GFX12: v_sat_pk_u8_i16_e32 v5, -1              ; encoding: [0xc1,0xc4,0x0a,0x7e]
+0xc1,0xc4,0x0a,0x7e
+
+# GFX12: v_sat_pk_u8_i16_e32 v5, 0.5             ; encoding: [0xf0,0xc4,0x0a,0x7e]
+0xf0,0xc4,0x0a,0x7e
+
+# GFX12: v_sat_pk_u8_i16_e32 v5, src_scc         ; encoding: [0xfd,0xc4,0x0a,0x7e]
+0xfd,0xc4,0x0a,0x7e
+
+# GFX12: v_sat_pk_u8_i16_e32 v127, 0xfe0b        ; encoding: [0xff,0xc4,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+0xff,0xc4,0xfe,0x7e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_sin_f16_e32 v5, v1                    ; encoding: [0x01,0xc1,0x0a,0x7e]
+0x01,0xc1,0x0a,0x7e
+
+# GFX12: v_sin_f16_e32 v5, v127                  ; encoding: [0x7f,0xc1,0x0a,0x7e]
+0x7f,0xc1,0x0a,0x7e
+
+# GFX12: v_sin_f16_e32 v5, s1                    ; encoding: [0x01,0xc0,0x0a,0x7e]
+0x01,0xc0,0x0a,0x7e
+
+# GFX12: v_sin_f16_e32 v5, s105                  ; encoding: [0x69,0xc0,0x0a,0x7e]
+0x69,0xc0,0x0a,0x7e
+
+# GFX12: v_sin_f16_e32 v5, vcc_lo                ; encoding: [0x6a,0xc0,0x0a,0x7e]
+0x6a,0xc0,0x0a,0x7e
+
+# GFX12: v_sin_f16_e32 v5, vcc_hi                ; encoding: [0x6b,0xc0,0x0a,0x7e]
+0x6b,0xc0,0x0a,0x7e
+
+# GFX12: v_sin_f16_e32 v5, ttmp15                ; encoding: [0x7b,0xc0,0x0a,0x7e]
+0x7b,0xc0,0x0a,0x7e
+
+# GFX12: v_sin_f16_e32 v5, m0                    ; encoding: [0x7d,0xc0,0x0a,0x7e]
+0x7d,0xc0,0x0a,0x7e
+
+# GFX12: v_sin_f16_e32 v5, exec_lo               ; encoding: [0x7e,0xc0,0x0a,0x7e]
+0x7e,0xc0,0x0a,0x7e
+
+# GFX12: v_sin_f16_e32 v5, exec_hi               ; encoding: [0x7f,0xc0,0x0a,0x7e]
+0x7f,0xc0,0x0a,0x7e
+
+# GFX12: v_sin_f16_e32 v5, null                  ; encoding: [0x7c,0xc0,0x0a,0x7e]
+0x7c,0xc0,0x0a,0x7e
+
+# GFX12: v_sin_f16_e32 v5, -1                    ; encoding: [0xc1,0xc0,0x0a,0x7e]
+0xc1,0xc0,0x0a,0x7e
+
+# GFX12: v_sin_f16_e32 v5, 0.5                   ; encoding: [0xf0,0xc0,0x0a,0x7e]
+0xf0,0xc0,0x0a,0x7e
+
+# GFX12: v_sin_f16_e32 v5, src_scc               ; encoding: [0xfd,0xc0,0x0a,0x7e]
+0xfd,0xc0,0x0a,0x7e
+
+# GFX12: v_sin_f16_e32 v127, 0xfe0b              ; encoding: [0xff,0xc0,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+0xff,0xc0,0xfe,0x7e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_sin_f32_e32 v5, v1                    ; encoding: [0x01,0x6b,0x0a,0x7e]
+0x01,0x6b,0x0a,0x7e
+
+# GFX12: v_sin_f32_e32 v5, v255                  ; encoding: [0xff,0x6b,0x0a,0x7e]
+0xff,0x6b,0x0a,0x7e
+
+# GFX12: v_sin_f32_e32 v5, s1                    ; encoding: [0x01,0x6a,0x0a,0x7e]
+0x01,0x6a,0x0a,0x7e
+
+# GFX12: v_sin_f32_e32 v5, s105                  ; encoding: [0x69,0x6a,0x0a,0x7e]
+0x69,0x6a,0x0a,0x7e
+
+# GFX12: v_sin_f32_e32 v5, vcc_lo                ; encoding: [0x6a,0x6a,0x0a,0x7e]
+0x6a,0x6a,0x0a,0x7e
+
+# GFX12: v_sin_f32_e32 v5, vcc_hi                ; encoding: [0x6b,0x6a,0x0a,0x7e]
+0x6b,0x6a,0x0a,0x7e
+
+# GFX12: v_sin_f32_e32 v5, ttmp15                ; encoding: [0x7b,0x6a,0x0a,0x7e]
+0x7b,0x6a,0x0a,0x7e
+
+# GFX12: v_sin_f32_e32 v5, m0                    ; encoding: [0x7d,0x6a,0x0a,0x7e]
+0x7d,0x6a,0x0a,0x7e
+
+# GFX12: v_sin_f32_e32 v5, exec_lo               ; encoding: [0x7e,0x6a,0x0a,0x7e]
+0x7e,0x6a,0x0a,0x7e
+
+# GFX12: v_sin_f32_e32 v5, exec_hi               ; encoding: [0x7f,0x6a,0x0a,0x7e]
+0x7f,0x6a,0x0a,0x7e
+
+# GFX12: v_sin_f32_e32 v5, null                  ; encoding: [0x7c,0x6a,0x0a,0x7e]
+0x7c,0x6a,0x0a,0x7e
+
+# GFX12: v_sin_f32_e32 v5, -1                    ; encoding: [0xc1,0x6a,0x0a,0x7e]
+0xc1,0x6a,0x0a,0x7e
+
+# GFX12: v_sin_f32_e32 v5, 0.5                   ; encoding: [0xf0,0x6a,0x0a,0x7e]
+0xf0,0x6a,0x0a,0x7e
+
+# GFX12: v_sin_f32_e32 v5, src_scc               ; encoding: [0xfd,0x6a,0x0a,0x7e]
+0xfd,0x6a,0x0a,0x7e
+
+# GFX12: v_sin_f32_e32 v255, 0xaf123456          ; encoding: [0xff,0x6a,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x6a,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_sqrt_f16_e32 v5, v1                   ; encoding: [0x01,0xab,0x0a,0x7e]
+0x01,0xab,0x0a,0x7e
+
+# GFX12: v_sqrt_f16_e32 v5, v127                 ; encoding: [0x7f,0xab,0x0a,0x7e]
+0x7f,0xab,0x0a,0x7e
+
+# GFX12: v_sqrt_f16_e32 v5, s1                   ; encoding: [0x01,0xaa,0x0a,0x7e]
+0x01,0xaa,0x0a,0x7e
+
+# GFX12: v_sqrt_f16_e32 v5, s105                 ; encoding: [0x69,0xaa,0x0a,0x7e]
+0x69,0xaa,0x0a,0x7e
+
+# GFX12: v_sqrt_f16_e32 v5, vcc_lo               ; encoding: [0x6a,0xaa,0x0a,0x7e]
+0x6a,0xaa,0x0a,0x7e
+
+# GFX12: v_sqrt_f16_e32 v5, vcc_hi               ; encoding: [0x6b,0xaa,0x0a,0x7e]
+0x6b,0xaa,0x0a,0x7e
+
+# GFX12: v_sqrt_f16_e32 v5, ttmp15               ; encoding: [0x7b,0xaa,0x0a,0x7e]
+0x7b,0xaa,0x0a,0x7e
+
+# GFX12: v_sqrt_f16_e32 v5, m0                   ; encoding: [0x7d,0xaa,0x0a,0x7e]
+0x7d,0xaa,0x0a,0x7e
+
+# GFX12: v_sqrt_f16_e32 v5, exec_lo              ; encoding: [0x7e,0xaa,0x0a,0x7e]
+0x7e,0xaa,0x0a,0x7e
+
+# GFX12: v_sqrt_f16_e32 v5, exec_hi              ; encoding: [0x7f,0xaa,0x0a,0x7e]
+0x7f,0xaa,0x0a,0x7e
+
+# GFX12: v_sqrt_f16_e32 v5, null                 ; encoding: [0x7c,0xaa,0x0a,0x7e]
+0x7c,0xaa,0x0a,0x7e
+
+# GFX12: v_sqrt_f16_e32 v5, -1                   ; encoding: [0xc1,0xaa,0x0a,0x7e]
+0xc1,0xaa,0x0a,0x7e
+
+# GFX12: v_sqrt_f16_e32 v5, 0.5                  ; encoding: [0xf0,0xaa,0x0a,0x7e]
+0xf0,0xaa,0x0a,0x7e
+
+# GFX12: v_sqrt_f16_e32 v5, src_scc              ; encoding: [0xfd,0xaa,0x0a,0x7e]
+0xfd,0xaa,0x0a,0x7e
+
+# GFX12: v_sqrt_f16_e32 v127, 0xfe0b             ; encoding: [0xff,0xaa,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+0xff,0xaa,0xfe,0x7e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_sqrt_f32_e32 v5, v1                   ; encoding: [0x01,0x67,0x0a,0x7e]
+0x01,0x67,0x0a,0x7e
+
+# GFX12: v_sqrt_f32_e32 v5, v255                 ; encoding: [0xff,0x67,0x0a,0x7e]
+0xff,0x67,0x0a,0x7e
+
+# GFX12: v_sqrt_f32_e32 v5, s1                   ; encoding: [0x01,0x66,0x0a,0x7e]
+0x01,0x66,0x0a,0x7e
+
+# GFX12: v_sqrt_f32_e32 v5, s105                 ; encoding: [0x69,0x66,0x0a,0x7e]
+0x69,0x66,0x0a,0x7e
+
+# GFX12: v_sqrt_f32_e32 v5, vcc_lo               ; encoding: [0x6a,0x66,0x0a,0x7e]
+0x6a,0x66,0x0a,0x7e
+
+# GFX12: v_sqrt_f32_e32 v5, vcc_hi               ; encoding: [0x6b,0x66,0x0a,0x7e]
+0x6b,0x66,0x0a,0x7e
+
+# GFX12: v_sqrt_f32_e32 v5, ttmp15               ; encoding: [0x7b,0x66,0x0a,0x7e]
+0x7b,0x66,0x0a,0x7e
+
+# GFX12: v_sqrt_f32_e32 v5, m0                   ; encoding: [0x7d,0x66,0x0a,0x7e]
+0x7d,0x66,0x0a,0x7e
+
+# GFX12: v_sqrt_f32_e32 v5, exec_lo              ; encoding: [0x7e,0x66,0x0a,0x7e]
+0x7e,0x66,0x0a,0x7e
+
+# GFX12: v_sqrt_f32_e32 v5, exec_hi              ; encoding: [0x7f,0x66,0x0a,0x7e]
+0x7f,0x66,0x0a,0x7e
+
+# GFX12: v_sqrt_f32_e32 v5, null                 ; encoding: [0x7c,0x66,0x0a,0x7e]
+0x7c,0x66,0x0a,0x7e
+
+# GFX12: v_sqrt_f32_e32 v5, -1                   ; encoding: [0xc1,0x66,0x0a,0x7e]
+0xc1,0x66,0x0a,0x7e
+
+# GFX12: v_sqrt_f32_e32 v5, 0.5                  ; encoding: [0xf0,0x66,0x0a,0x7e]
+0xf0,0x66,0x0a,0x7e
+
+# GFX12: v_sqrt_f32_e32 v5, src_scc              ; encoding: [0xfd,0x66,0x0a,0x7e]
+0xfd,0x66,0x0a,0x7e
+
+# GFX12: v_sqrt_f32_e32 v255, 0xaf123456         ; encoding: [0xff,0x66,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x66,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_sqrt_f64_e32 v[5:6], v[1:2]           ; encoding: [0x01,0x69,0x0a,0x7e]
+0x01,0x69,0x0a,0x7e
+
+# GFX12: v_sqrt_f64_e32 v[5:6], v[254:255]       ; encoding: [0xfe,0x69,0x0a,0x7e]
+0xfe,0x69,0x0a,0x7e
+
+# GFX12: v_sqrt_f64_e32 v[5:6], s[2:3]           ; encoding: [0x02,0x68,0x0a,0x7e]
+0x02,0x68,0x0a,0x7e
+
+# GFX12: v_sqrt_f64_e32 v[5:6], s[104:105]       ; encoding: [0x68,0x68,0x0a,0x7e]
+0x68,0x68,0x0a,0x7e
+
+# GFX12: v_sqrt_f64_e32 v[5:6], vcc              ; encoding: [0x6a,0x68,0x0a,0x7e]
+0x6a,0x68,0x0a,0x7e
+
+# GFX12: v_sqrt_f64_e32 v[5:6], ttmp[14:15]      ; encoding: [0x7a,0x68,0x0a,0x7e]
+0x7a,0x68,0x0a,0x7e
+
+# GFX12: v_sqrt_f64_e32 v[5:6], exec             ; encoding: [0x7e,0x68,0x0a,0x7e]
+0x7e,0x68,0x0a,0x7e
+
+# GFX12: v_sqrt_f64_e32 v[5:6], null             ; encoding: [0x7c,0x68,0x0a,0x7e]
+0x7c,0x68,0x0a,0x7e
+
+# GFX12: v_sqrt_f64_e32 v[5:6], -1               ; encoding: [0xc1,0x68,0x0a,0x7e]
+0xc1,0x68,0x0a,0x7e
+
+# GFX12: v_sqrt_f64_e32 v[5:6], 0.5              ; encoding: [0xf0,0x68,0x0a,0x7e]
+0xf0,0x68,0x0a,0x7e
+
+# GFX12: v_sqrt_f64_e32 v[5:6], src_scc          ; encoding: [0xfd,0x68,0x0a,0x7e]
+0xfd,0x68,0x0a,0x7e
+
+# GFX12: v_sqrt_f64_e32 v[254:255], 0xaf123456   ; encoding: [0xff,0x68,0xfc,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x68,0xfc,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_swap_b32 v5, v1                       ; encoding: [0x01,0xcb,0x0a,0x7e]
+0x01,0xcb,0x0a,0x7e
+
+# GFX12: v_swap_b32 v255, v255                   ; encoding: [0xff,0xcb,0xfe,0x7f]
+0xff,0xcb,0xfe,0x7f
+
+# GFX12: v_swaprel_b32 v5, v1                    ; encoding: [0x01,0xd1,0x0a,0x7e]
+0x01,0xd1,0x0a,0x7e
+
+# GFX12: v_swaprel_b32 v255, v255                ; encoding: [0xff,0xd1,0xfe,0x7f]
+0xff,0xd1,0xfe,0x7f
+
+# GFX12: v_trunc_f16_e32 v5, v1                  ; encoding: [0x01,0xbb,0x0a,0x7e]
+0x01,0xbb,0x0a,0x7e
+
+# GFX12: v_trunc_f16_e32 v5, v127                ; encoding: [0x7f,0xbb,0x0a,0x7e]
+0x7f,0xbb,0x0a,0x7e
+
+# GFX12: v_trunc_f16_e32 v5, s1                  ; encoding: [0x01,0xba,0x0a,0x7e]
+0x01,0xba,0x0a,0x7e
+
+# GFX12: v_trunc_f16_e32 v5, s105                ; encoding: [0x69,0xba,0x0a,0x7e]
+0x69,0xba,0x0a,0x7e
+
+# GFX12: v_trunc_f16_e32 v5, vcc_lo              ; encoding: [0x6a,0xba,0x0a,0x7e]
+0x6a,0xba,0x0a,0x7e
+
+# GFX12: v_trunc_f16_e32 v5, vcc_hi              ; encoding: [0x6b,0xba,0x0a,0x7e]
+0x6b,0xba,0x0a,0x7e
+
+# GFX12: v_trunc_f16_e32 v5, ttmp15              ; encoding: [0x7b,0xba,0x0a,0x7e]
+0x7b,0xba,0x0a,0x7e
+
+# GFX12: v_trunc_f16_e32 v5, m0                  ; encoding: [0x7d,0xba,0x0a,0x7e]
+0x7d,0xba,0x0a,0x7e
+
+# GFX12: v_trunc_f16_e32 v5, exec_lo             ; encoding: [0x7e,0xba,0x0a,0x7e]
+0x7e,0xba,0x0a,0x7e
+
+# GFX12: v_trunc_f16_e32 v5, exec_hi             ; encoding: [0x7f,0xba,0x0a,0x7e]
+0x7f,0xba,0x0a,0x7e
+
+# GFX12: v_trunc_f16_e32 v5, null                ; encoding: [0x7c,0xba,0x0a,0x7e]
+0x7c,0xba,0x0a,0x7e
+
+# GFX12: v_trunc_f16_e32 v5, -1                  ; encoding: [0xc1,0xba,0x0a,0x7e]
+0xc1,0xba,0x0a,0x7e
+
+# GFX12: v_trunc_f16_e32 v5, 0.5                 ; encoding: [0xf0,0xba,0x0a,0x7e]
+0xf0,0xba,0x0a,0x7e
+
+# GFX12: v_trunc_f16_e32 v5, src_scc             ; encoding: [0xfd,0xba,0x0a,0x7e]
+0xfd,0xba,0x0a,0x7e
+
+# GFX12: v_trunc_f16_e32 v127, 0xfe0b            ; encoding: [0xff,0xba,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
+0xff,0xba,0xfe,0x7e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_trunc_f32_e32 v5, v1                  ; encoding: [0x01,0x43,0x0a,0x7e]
+0x01,0x43,0x0a,0x7e
+
+# GFX12: v_trunc_f32_e32 v5, v255                ; encoding: [0xff,0x43,0x0a,0x7e]
+0xff,0x43,0x0a,0x7e
+
+# GFX12: v_trunc_f32_e32 v5, s1                  ; encoding: [0x01,0x42,0x0a,0x7e]
+0x01,0x42,0x0a,0x7e
+
+# GFX12: v_trunc_f32_e32 v5, s105                ; encoding: [0x69,0x42,0x0a,0x7e]
+0x69,0x42,0x0a,0x7e
+
+# GFX12: v_trunc_f32_e32 v5, vcc_lo              ; encoding: [0x6a,0x42,0x0a,0x7e]
+0x6a,0x42,0x0a,0x7e
+
+# GFX12: v_trunc_f32_e32 v5, vcc_hi              ; encoding: [0x6b,0x42,0x0a,0x7e]
+0x6b,0x42,0x0a,0x7e
+
+# GFX12: v_trunc_f32_e32 v5, ttmp15              ; encoding: [0x7b,0x42,0x0a,0x7e]
+0x7b,0x42,0x0a,0x7e
+
+# GFX12: v_trunc_f32_e32 v5, m0                  ; encoding: [0x7d,0x42,0x0a,0x7e]
+0x7d,0x42,0x0a,0x7e
+
+# GFX12: v_trunc_f32_e32 v5, exec_lo             ; encoding: [0x7e,0x42,0x0a,0x7e]
+0x7e,0x42,0x0a,0x7e
+
+# GFX12: v_trunc_f32_e32 v5, exec_hi             ; encoding: [0x7f,0x42,0x0a,0x7e]
+0x7f,0x42,0x0a,0x7e
+
+# GFX12: v_trunc_f32_e32 v5, null                ; encoding: [0x7c,0x42,0x0a,0x7e]
+0x7c,0x42,0x0a,0x7e
+
+# GFX12: v_trunc_f32_e32 v5, -1                  ; encoding: [0xc1,0x42,0x0a,0x7e]
+0xc1,0x42,0x0a,0x7e
+
+# GFX12: v_trunc_f32_e32 v5, 0.5                 ; encoding: [0xf0,0x42,0x0a,0x7e]
+0xf0,0x42,0x0a,0x7e
+
+# GFX12: v_trunc_f32_e32 v5, src_scc             ; encoding: [0xfd,0x42,0x0a,0x7e]
+0xfd,0x42,0x0a,0x7e
+
+# GFX12: v_trunc_f32_e32 v255, 0xaf123456        ; encoding: [0xff,0x42,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x42,0xfe,0x7f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_trunc_f64_e32 v[5:6], v[1:2]          ; encoding: [0x01,0x2f,0x0a,0x7e]
+0x01,0x2f,0x0a,0x7e
+
+# GFX12: v_trunc_f64_e32 v[5:6], v[254:255]      ; encoding: [0xfe,0x2f,0x0a,0x7e]
+0xfe,0x2f,0x0a,0x7e
+
+# GFX12: v_trunc_f64_e32 v[5:6], s[2:3]          ; encoding: [0x02,0x2e,0x0a,0x7e]
+0x02,0x2e,0x0a,0x7e
+
+# GFX12: v_trunc_f64_e32 v[5:6], s[104:105]      ; encoding: [0x68,0x2e,0x0a,0x7e]
+0x68,0x2e,0x0a,0x7e
+
+# GFX12: v_trunc_f64_e32 v[5:6], vcc             ; encoding: [0x6a,0x2e,0x0a,0x7e]
+0x6a,0x2e,0x0a,0x7e
+
+# GFX12: v_trunc_f64_e32 v[5:6], ttmp[14:15]     ; encoding: [0x7a,0x2e,0x0a,0x7e]
+0x7a,0x2e,0x0a,0x7e
+
+# GFX12: v_trunc_f64_e32 v[5:6], exec            ; encoding: [0x7e,0x2e,0x0a,0x7e]
+0x7e,0x2e,0x0a,0x7e
+
+# GFX12: v_trunc_f64_e32 v[5:6], null            ; encoding: [0x7c,0x2e,0x0a,0x7e]
+0x7c,0x2e,0x0a,0x7e
+
+# GFX12: v_trunc_f64_e32 v[5:6], -1              ; encoding: [0xc1,0x2e,0x0a,0x7e]
+0xc1,0x2e,0x0a,0x7e
+
+# GFX12: v_trunc_f64_e32 v[5:6], 0.5             ; encoding: [0xf0,0x2e,0x0a,0x7e]
+0xf0,0x2e,0x0a,0x7e
+
+# GFX12: v_trunc_f64_e32 v[5:6], src_scc         ; encoding: [0xfd,0x2e,0x0a,0x7e]
+0xfd,0x2e,0x0a,0x7e
+
+# GFX12: v_trunc_f64_e32 v[254:255], 0xaf123456  ; encoding: [0xff,0x2e,0xfc,0x7f,0x56,0x34,0x12,0xaf]
+0xff,0x2e,0xfc,0x7f,0x56,0x34,0x12,0xaf
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp16.txt
new file mode 100644
index 000000000000..bcb9ad9febb9
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp16.txt
@@ -0,0 +1,2606 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX12 %s
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX12 %s
+
+# GFX12: v_bfrev_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x70,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_bfrev_b32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x70,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_bfrev_b32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x70,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_bfrev_b32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x70,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_bfrev_b32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x70,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_bfrev_b32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x70,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_bfrev_b32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x70,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_bfrev_b32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x70,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_bfrev_b32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x70,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_bfrev_b32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x70,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_bfrev_b32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x70,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_bfrev_b32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x70,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_bfrev_b32_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x70,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
+0xfa,0x70,0xfe,0x7f,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_ceil_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0xb8,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_ceil_f16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0xb8,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_ceil_f16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0xb8,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_ceil_f16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0xb8,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_ceil_f16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0xb8,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_ceil_f16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0xb8,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_ceil_f16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0xb8,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_ceil_f16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0xb8,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_ceil_f16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0xb8,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_ceil_f16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0xb8,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_ceil_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0xb8,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_ceil_f16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0xb8,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_ceil_f16_dpp v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb8,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
+0xfa,0xb8,0xfe,0x7e,0x7f,0x6f,0x3d,0x30
+
+# GFX12: v_ceil_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x44,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_ceil_f32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x44,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_ceil_f32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x44,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_ceil_f32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x44,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_ceil_f32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x44,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_ceil_f32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x44,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_ceil_f32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x44,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_ceil_f32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x44,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_ceil_f32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x44,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_ceil_f32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x44,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_ceil_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x44,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_ceil_f32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x44,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_ceil_f32_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x44,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
+0xfa,0x44,0xfe,0x7f,0xff,0x6f,0x3d,0x30
+
+# GFX12: v_cls_i32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x76,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cls_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cls_i32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x76,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_cls_i32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x76,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_cls_i32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x76,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_cls_i32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x76,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cls_i32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x76,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_cls_i32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x76,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cls_i32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x76,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_cls_i32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x76,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cls_i32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x76,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_cls_i32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x76,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cls_i32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x76,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_cls_i32_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x76,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
+0xfa,0x76,0xfe,0x7f,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_clz_i32_u32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x72,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_clz_i32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_clz_i32_u32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x72,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_clz_i32_u32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x72,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_clz_i32_u32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x72,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_clz_i32_u32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x72,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_clz_i32_u32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x72,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_clz_i32_u32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x72,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_clz_i32_u32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x72,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_clz_i32_u32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x72,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_clz_i32_u32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x72,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_clz_i32_u32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x72,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_clz_i32_u32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x72,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_clz_i32_u32_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x72,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
+0xfa,0x72,0xfe,0x7f,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cos_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0xc2,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cos_f16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0xc2,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_cos_f16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0xc2,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_cos_f16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0xc2,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_cos_f16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0xc2,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cos_f16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0xc2,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_cos_f16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0xc2,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cos_f16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0xc2,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_cos_f16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0xc2,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cos_f16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0xc2,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_cos_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0xc2,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cos_f16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0xc2,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_cos_f16_dpp v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc2,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
+0xfa,0xc2,0xfe,0x7e,0x7f,0x6f,0x3d,0x30
+
+# GFX12: v_cos_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x6c,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cos_f32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x6c,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_cos_f32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x6c,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_cos_f32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x6c,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_cos_f32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x6c,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cos_f32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x6c,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_cos_f32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x6c,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cos_f32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x6c,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_cos_f32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x6c,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cos_f32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x6c,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_cos_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x6c,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cos_f32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x6c,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_cos_f32_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x6c,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
+0xfa,0x6c,0xfe,0x7f,0xff,0x6f,0x3d,0x30
+
+# GFX12: v_ctz_i32_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x74,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_ctz_i32_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_ctz_i32_b32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x74,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_ctz_i32_b32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x74,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_ctz_i32_b32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x74,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_ctz_i32_b32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x74,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_ctz_i32_b32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x74,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_ctz_i32_b32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x74,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_ctz_i32_b32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x74,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_ctz_i32_b32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x74,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_ctz_i32_b32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x74,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_ctz_i32_b32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x74,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_ctz_i32_b32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x74,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_ctz_i32_b32_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x74,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
+0xfa,0x74,0xfe,0x7f,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_f16_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x14,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_f16_f32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x14,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_f16_f32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x14,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_f16_f32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x14,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_f16_f32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x14,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_f16_f32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x14,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_f16_f32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x14,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_f16_f32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x14,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_f16_f32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x14,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_f16_f32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x14,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_f16_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x14,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_f16_f32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x14,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_f16_f32_dpp v127, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x14,0xfe,0x7e,0xff,0x6f,0x3d,0x30]
+0xfa,0x14,0xfe,0x7e,0xff,0x6f,0x3d,0x30
+
+# GFX12: v_cvt_f16_i16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0xa2,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_f16_i16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0xa2,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_f16_i16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0xa2,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_f16_i16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0xa2,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_f16_i16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0xa2,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_f16_i16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0xa2,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_f16_i16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0xa2,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_f16_i16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0xa2,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_f16_i16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0xa2,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_f16_i16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0xa2,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_f16_i16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0xa2,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_f16_i16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0xa2,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_f16_i16_dpp v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa2,0xfe,0x7e,0x7f,0x6f,0x0d,0x30]
+0xfa,0xa2,0xfe,0x7e,0x7f,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_f16_u16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0xa0,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_f16_u16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0xa0,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_f16_u16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0xa0,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_f16_u16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0xa0,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_f16_u16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0xa0,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_f16_u16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0xa0,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_f16_u16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0xa0,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_f16_u16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0xa0,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_f16_u16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0xa0,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_f16_u16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0xa0,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_f16_u16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0xa0,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_f16_u16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0xa0,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_f16_u16_dpp v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa0,0xfe,0x7e,0x7f,0x6f,0x0d,0x30]
+0xfa,0xa0,0xfe,0x7e,0x7f,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_f32_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x16,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_f32_f16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x16,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_f32_f16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x16,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_f32_f16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x16,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_f32_f16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x16,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_f32_f16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x16,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_f32_f16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x16,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_f32_f16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x16,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_f32_f16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x16,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_f32_f16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x16,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_f32_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x16,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_f32_f16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x16,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_f32_f16_dpp v255, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x16,0xfe,0x7f,0x7f,0x6f,0x3d,0x30]
+0xfa,0x16,0xfe,0x7f,0x7f,0x6f,0x3d,0x30
+
+# GFX12: v_cvt_f32_i32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x0a,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_f32_i32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x0a,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_f32_i32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x0a,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_f32_i32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x0a,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_f32_i32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x0a,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_f32_i32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x0a,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_f32_i32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x0a,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_f32_i32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x0a,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_f32_i32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x0a,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_f32_i32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x0a,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_f32_i32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x0a,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_f32_i32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x0a,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_f32_i32_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x0a,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
+0xfa,0x0a,0xfe,0x7f,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_f32_u32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x0c,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_f32_u32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x0c,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_f32_u32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x0c,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_f32_u32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x0c,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_f32_u32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x0c,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_f32_u32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x0c,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_f32_u32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x0c,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_f32_u32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x0c,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_f32_u32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x0c,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_f32_u32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x0c,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_f32_u32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x0c,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_f32_u32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x0c,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_f32_u32_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x0c,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
+0xfa,0x0c,0xfe,0x7f,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x22,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_f32_ubyte0_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x22,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte0_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x22,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte0_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x22,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte0_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x22,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte0_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x22,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte0_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x22,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte0_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x22,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte0_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x22,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte0_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x22,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte0_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x22,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_f32_ubyte0_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x22,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_f32_ubyte0_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x22,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
+0xfa,0x22,0xfe,0x7f,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x24,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_f32_ubyte1_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x24,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte1_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x24,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte1_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x24,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte1_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x24,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte1_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x24,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte1_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x24,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte1_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x24,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte1_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x24,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte1_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x24,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte1_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x24,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_f32_ubyte1_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x24,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_f32_ubyte1_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x24,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
+0xfa,0x24,0xfe,0x7f,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x26,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_f32_ubyte2_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x26,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte2_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x26,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte2_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x26,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte2_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x26,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte2_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x26,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte2_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x26,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte2_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x26,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte2_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x26,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte2_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x26,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte2_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x26,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_f32_ubyte2_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x26,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_f32_ubyte2_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x26,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
+0xfa,0x26,0xfe,0x7f,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x28,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_f32_ubyte3_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x28,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte3_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x28,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte3_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x28,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte3_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x28,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte3_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x28,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte3_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x28,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte3_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x28,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte3_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x28,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte3_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x28,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte3_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x28,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_f32_ubyte3_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x28,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_f32_ubyte3_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x28,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
+0xfa,0x28,0xfe,0x7f,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_floor_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x1a,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_floor_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_floor_i32_f32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x1a,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_floor_i32_f32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x1a,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_floor_i32_f32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x1a,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_floor_i32_f32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x1a,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_floor_i32_f32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x1a,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_floor_i32_f32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x1a,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_floor_i32_f32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x1a,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_floor_i32_f32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x1a,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_floor_i32_f32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x1a,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_floor_i32_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x1a,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_floor_i32_f32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x1a,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_floor_i32_f32_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x1a,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
+0xfa,0x1a,0xfe,0x7f,0xff,0x6f,0x3d,0x30
+
+# GFX12: v_cvt_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0xa6,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_i16_f16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0xa6,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_i16_f16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0xa6,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_i16_f16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0xa6,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_i16_f16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0xa6,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_i16_f16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0xa6,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_i16_f16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0xa6,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_i16_f16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0xa6,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_i16_f16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0xa6,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_i16_f16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0xa6,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_i16_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0xa6,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_i16_f16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0xa6,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_i16_f16_dpp v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa6,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
+0xfa,0xa6,0xfe,0x7e,0x7f,0x6f,0x3d,0x30
+
+# GFX12: v_cvt_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x10,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_i32_f32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x10,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_i32_f32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x10,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_i32_f32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x10,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_i32_f32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x10,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_i32_f32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x10,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_i32_f32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x10,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_i32_f32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x10,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_i32_f32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x10,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_i32_f32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x10,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_i32_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x10,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_i32_f32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x10,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_i32_f32_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x10,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
+0xfa,0x10,0xfe,0x7f,0xff,0x6f,0x3d,0x30
+
+# GFX12: v_cvt_i32_i16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd4,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0xd4,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_i32_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd4,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0xd4,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_i32_i16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd4,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0xd4,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_i32_i16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd4,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0xd4,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_i32_i16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd4,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0xd4,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_i32_i16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd4,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0xd4,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_i32_i16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd4,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0xd4,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_i32_i16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd4,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0xd4,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_i32_i16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd4,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0xd4,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_i32_i16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd4,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0xd4,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_i32_i16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd4,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0xd4,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_i32_i16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xd4,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0xd4,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_i32_i16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xd4,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0xd4,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_i32_i16_dpp v255, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xd4,0xfe,0x7f,0x7f,0x6f,0x0d,0x30]
+0xfa,0xd4,0xfe,0x7f,0x7f,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_nearest_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x18,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_nearest_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_nearest_i32_f32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x18,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_nearest_i32_f32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x18,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_nearest_i32_f32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x18,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_nearest_i32_f32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x18,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_nearest_i32_f32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x18,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_nearest_i32_f32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x18,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_nearest_i32_f32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x18,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_nearest_i32_f32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x18,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_nearest_i32_f32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x18,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_nearest_i32_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x18,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_nearest_i32_f32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x18,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_nearest_i32_f32_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x18,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
+0xfa,0x18,0xfe,0x7f,0xff,0x6f,0x3d,0x30
+
+# GFX12: v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0xc6,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_norm_i16_f16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0xc6,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_norm_i16_f16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0xc6,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_norm_i16_f16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0xc6,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_norm_i16_f16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0xc6,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_norm_i16_f16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0xc6,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_norm_i16_f16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0xc6,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_norm_i16_f16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0xc6,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_norm_i16_f16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0xc6,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_norm_i16_f16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0xc6,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_norm_i16_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0xc6,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_norm_i16_f16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0xc6,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_norm_i16_f16_dpp v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc6,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
+0xfa,0xc6,0xfe,0x7e,0x7f,0x6f,0x3d,0x30
+
+# GFX12: v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0xc8,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_norm_u16_f16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0xc8,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_norm_u16_f16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0xc8,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_norm_u16_f16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0xc8,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_norm_u16_f16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0xc8,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_norm_u16_f16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0xc8,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_norm_u16_f16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0xc8,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_norm_u16_f16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0xc8,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_norm_u16_f16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0xc8,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_norm_u16_f16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0xc8,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_norm_u16_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0xc8,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_norm_u16_f16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0xc8,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_norm_u16_f16_dpp v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc8,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
+0xfa,0xc8,0xfe,0x7e,0x7f,0x6f,0x3d,0x30
+
+# GFX12: v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x1c,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_off_f32_i4_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x1c,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_off_f32_i4_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x1c,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_off_f32_i4_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x1c,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_off_f32_i4_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x1c,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_off_f32_i4_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x1c,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_off_f32_i4_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x1c,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_off_f32_i4_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x1c,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_off_f32_i4_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x1c,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_off_f32_i4_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x1c,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_off_f32_i4_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x1c,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_off_f32_i4_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x1c,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_off_f32_i4_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x1c,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
+0xfa,0x1c,0xfe,0x7f,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0xa4,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_u16_f16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0xa4,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_u16_f16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0xa4,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_u16_f16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0xa4,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_u16_f16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0xa4,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_u16_f16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0xa4,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_u16_f16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0xa4,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_u16_f16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0xa4,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_u16_f16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0xa4,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_u16_f16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0xa4,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_u16_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0xa4,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_u16_f16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0xa4,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_u16_f16_dpp v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa4,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
+0xfa,0xa4,0xfe,0x7e,0x7f,0x6f,0x3d,0x30
+
+# GFX12: v_cvt_u32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x0e,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_u32_f32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x0e,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_u32_f32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x0e,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_u32_f32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x0e,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_u32_f32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x0e,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_u32_f32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x0e,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_u32_f32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x0e,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_u32_f32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x0e,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_u32_f32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x0e,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_u32_f32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x0e,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_u32_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x0e,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_u32_f32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x0e,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_u32_f32_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x0e,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
+0xfa,0x0e,0xfe,0x7f,0xff,0x6f,0x3d,0x30
+
+# GFX12: v_cvt_u32_u16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd6,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0xd6,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_u32_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd6,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0xd6,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_u32_u16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd6,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0xd6,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_u32_u16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd6,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0xd6,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_u32_u16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd6,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0xd6,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_u32_u16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd6,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0xd6,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_u32_u16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd6,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0xd6,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_u32_u16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd6,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0xd6,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_u32_u16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd6,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0xd6,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_u32_u16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd6,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0xd6,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_u32_u16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd6,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0xd6,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_u32_u16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xd6,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0xd6,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_u32_u16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xd6,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0xd6,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_u32_u16_dpp v255, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xd6,0xfe,0x7f,0x7f,0x6f,0x0d,0x30]
+0xfa,0xd6,0xfe,0x7f,0x7f,0x6f,0x0d,0x30
+
+# GFX12: v_exp_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0xb0,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_exp_f16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0xb0,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_exp_f16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0xb0,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_exp_f16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0xb0,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_exp_f16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0xb0,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_exp_f16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0xb0,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_exp_f16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0xb0,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_exp_f16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0xb0,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_exp_f16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0xb0,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_exp_f16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0xb0,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_exp_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0xb0,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_exp_f16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0xb0,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_exp_f16_dpp v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb0,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
+0xfa,0xb0,0xfe,0x7e,0x7f,0x6f,0x3d,0x30
+
+# GFX12: v_exp_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x4a,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_exp_f32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x4a,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_exp_f32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x4a,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_exp_f32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x4a,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_exp_f32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x4a,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_exp_f32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x4a,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_exp_f32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x4a,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_exp_f32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x4a,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_exp_f32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x4a,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_exp_f32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x4a,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_exp_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x4a,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_exp_f32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x4a,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_exp_f32_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x4a,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
+0xfa,0x4a,0xfe,0x7f,0xff,0x6f,0x3d,0x30
+
+# GFX12: v_floor_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0xb6,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_floor_f16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0xb6,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_floor_f16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0xb6,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_floor_f16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0xb6,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_floor_f16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0xb6,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_floor_f16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0xb6,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_floor_f16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0xb6,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_floor_f16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0xb6,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_floor_f16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0xb6,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_floor_f16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0xb6,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_floor_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0xb6,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_floor_f16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0xb6,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_floor_f16_dpp v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb6,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
+0xfa,0xb6,0xfe,0x7e,0x7f,0x6f,0x3d,0x30
+
+# GFX12: v_floor_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x48,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_floor_f32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x48,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_floor_f32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x48,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_floor_f32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x48,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_floor_f32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x48,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_floor_f32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x48,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_floor_f32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x48,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_floor_f32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x48,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_floor_f32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x48,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_floor_f32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x48,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_floor_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x48,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_floor_f32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x48,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_floor_f32_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x48,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
+0xfa,0x48,0xfe,0x7f,0xff,0x6f,0x3d,0x30
+
+# GFX12: v_fract_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0xbe,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_fract_f16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0xbe,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_fract_f16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0xbe,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_fract_f16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0xbe,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_fract_f16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0xbe,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_fract_f16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0xbe,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_fract_f16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0xbe,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_fract_f16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0xbe,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_fract_f16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0xbe,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_fract_f16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0xbe,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_fract_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0xbe,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_fract_f16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0xbe,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_fract_f16_dpp v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xbe,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
+0xfa,0xbe,0xfe,0x7e,0x7f,0x6f,0x3d,0x30
+
+# GFX12: v_fract_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x40,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_fract_f32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x40,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_fract_f32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x40,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_fract_f32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x40,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_fract_f32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x40,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_fract_f32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x40,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_fract_f32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x40,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_fract_f32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x40,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_fract_f32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x40,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_fract_f32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x40,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_fract_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x40,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_fract_f32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x40,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_fract_f32_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x40,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
+0xfa,0x40,0xfe,0x7f,0xff,0x6f,0x3d,0x30
+
+# GFX12: v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0xb4,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_frexp_exp_i16_f16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0xb4,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_frexp_exp_i16_f16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0xb4,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_frexp_exp_i16_f16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0xb4,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_frexp_exp_i16_f16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0xb4,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_frexp_exp_i16_f16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0xb4,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_frexp_exp_i16_f16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0xb4,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_frexp_exp_i16_f16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0xb4,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_frexp_exp_i16_f16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0xb4,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_frexp_exp_i16_f16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0xb4,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_frexp_exp_i16_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0xb4,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_frexp_exp_i16_f16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0xb4,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_frexp_exp_i16_f16_dpp v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb4,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
+0xfa,0xb4,0xfe,0x7e,0x7f,0x6f,0x3d,0x30
+
+# GFX12: v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x7e,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_frexp_exp_i32_f32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x7e,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_frexp_exp_i32_f32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x7e,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_frexp_exp_i32_f32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x7e,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_frexp_exp_i32_f32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x7e,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_frexp_exp_i32_f32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x7e,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_frexp_exp_i32_f32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x7e,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_frexp_exp_i32_f32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x7e,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_frexp_exp_i32_f32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x7e,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_frexp_exp_i32_f32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x7e,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_frexp_exp_i32_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x7e,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_frexp_exp_i32_f32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x7e,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_frexp_exp_i32_f32_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x7e,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
+0xfa,0x7e,0xfe,0x7f,0xff,0x6f,0x3d,0x30
+
+# GFX12: v_frexp_mant_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0xb2,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_frexp_mant_f16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0xb2,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_frexp_mant_f16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0xb2,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_frexp_mant_f16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0xb2,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_frexp_mant_f16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0xb2,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_frexp_mant_f16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0xb2,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_frexp_mant_f16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0xb2,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_frexp_mant_f16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0xb2,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_frexp_mant_f16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0xb2,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_frexp_mant_f16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0xb2,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_frexp_mant_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0xb2,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_frexp_mant_f16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0xb2,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_frexp_mant_f16_dpp v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xb2,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
+0xfa,0xb2,0xfe,0x7e,0x7f,0x6f,0x3d,0x30
+
+# GFX12: v_frexp_mant_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x80,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_frexp_mant_f32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x80,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_frexp_mant_f32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x80,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_frexp_mant_f32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x80,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_frexp_mant_f32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x80,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_frexp_mant_f32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x80,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_frexp_mant_f32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x80,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_frexp_mant_f32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x80,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_frexp_mant_f32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x80,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_frexp_mant_f32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x80,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_frexp_mant_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x80,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_frexp_mant_f32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x80,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_frexp_mant_f32_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x80,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
+0xfa,0x80,0xfe,0x7f,0xff,0x6f,0x3d,0x30
+
+# GFX12: v_log_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0xae,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_log_f16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0xae,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_log_f16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0xae,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_log_f16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0xae,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_log_f16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0xae,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_log_f16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0xae,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_log_f16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0xae,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_log_f16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0xae,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_log_f16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0xae,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_log_f16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0xae,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_log_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0xae,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_log_f16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0xae,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_log_f16_dpp v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xae,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
+0xfa,0xae,0xfe,0x7e,0x7f,0x6f,0x3d,0x30
+
+# GFX12: v_log_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x4e,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_log_f32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x4e,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_log_f32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x4e,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_log_f32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x4e,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_log_f32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x4e,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_log_f32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x4e,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_log_f32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x4e,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_log_f32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x4e,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_log_f32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x4e,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_log_f32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x4e,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_log_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x4e,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_log_f32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x4e,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_log_f32_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x4e,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
+0xfa,0x4e,0xfe,0x7f,0xff,0x6f,0x3d,0x30
+
+# GFX12: v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_mov_b32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x02,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_mov_b32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x02,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_mov_b32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x02,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_mov_b32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x02,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x02,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_mov_b32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x02,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_mov_b32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x02,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_mov_b32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x02,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_mov_b32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x02,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_mov_b32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x02,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_mov_b32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x02,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_mov_b32_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x02,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
+0xfa,0x02,0xfe,0x7f,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_movreld_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x84,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x84,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_movreld_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_movreld_b32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x84,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x84,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_movreld_b32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x84,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x84,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_movreld_b32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x84,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x84,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_movreld_b32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x84,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x84,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_movreld_b32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x84,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x84,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_movreld_b32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x84,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x84,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_movreld_b32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x84,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x84,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_movreld_b32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x84,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x84,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_movreld_b32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x84,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x84,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_movreld_b32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x84,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x84,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_movreld_b32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x84,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x84,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_movreld_b32_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x84,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
+0xfa,0x84,0xfe,0x7f,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_movrels_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x86,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x86,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_movrels_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_movrels_b32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x86,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x86,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_movrels_b32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x86,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x86,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_movrels_b32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x86,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x86,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_movrels_b32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x86,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x86,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_movrels_b32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x86,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x86,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_movrels_b32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x86,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x86,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_movrels_b32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x86,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x86,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_movrels_b32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x86,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x86,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_movrels_b32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x86,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x86,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_movrels_b32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x86,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x86,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_movrels_b32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x86,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x86,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_movrels_b32_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x86,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
+0xfa,0x86,0xfe,0x7f,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_movrelsd_2_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x90,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x90,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_movrelsd_2_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_movrelsd_2_b32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x90,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x90,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_movrelsd_2_b32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x90,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x90,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_movrelsd_2_b32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x90,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x90,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_movrelsd_2_b32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x90,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x90,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_movrelsd_2_b32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x90,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x90,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_movrelsd_2_b32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x90,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x90,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_movrelsd_2_b32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x90,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x90,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_movrelsd_2_b32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x90,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x90,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_movrelsd_2_b32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x90,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x90,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_movrelsd_2_b32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x90,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x90,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_movrelsd_2_b32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x90,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x90,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_movrelsd_2_b32_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x90,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
+0xfa,0x90,0xfe,0x7f,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_movrelsd_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x88,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x88,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_movrelsd_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_movrelsd_b32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x88,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x88,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_movrelsd_b32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x88,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x88,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_movrelsd_b32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x88,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x88,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_movrelsd_b32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x88,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x88,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_movrelsd_b32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x88,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x88,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_movrelsd_b32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x88,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x88,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_movrelsd_b32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x88,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x88,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_movrelsd_b32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x88,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x88,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_movrelsd_b32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x88,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x88,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_movrelsd_b32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x88,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x88,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_movrelsd_b32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x88,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x88,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_movrelsd_b32_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x88,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
+0xfa,0x88,0xfe,0x7f,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_not_b16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd2,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0xd2,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_not_b16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd2,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0xd2,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_not_b16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd2,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0xd2,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_not_b16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd2,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0xd2,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_not_b16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd2,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0xd2,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_not_b16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd2,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0xd2,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_not_b16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd2,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0xd2,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_not_b16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd2,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0xd2,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_not_b16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd2,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0xd2,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_not_b16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd2,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0xd2,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_not_b16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd2,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0xd2,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_not_b16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xd2,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0xd2,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_not_b16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xd2,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0xd2,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_not_b16_dpp v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xd2,0xfe,0x7e,0x7f,0x6f,0x0d,0x30]
+0xfa,0xd2,0xfe,0x7e,0x7f,0x6f,0x0d,0x30
+
+# GFX12: v_not_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x6e,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_not_b32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x6e,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_not_b32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x6e,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_not_b32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x6e,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_not_b32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x6e,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_not_b32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x6e,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_not_b32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x6e,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_not_b32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x6e,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_not_b32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x6e,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_not_b32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x6e,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_not_b32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x6e,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_not_b32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x6e,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_not_b32_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x6e,0xfe,0x7f,0xff,0x6f,0x0d,0x30]
+0xfa,0x6e,0xfe,0x7f,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_rcp_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0xa8,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_rcp_f16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0xa8,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_rcp_f16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0xa8,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_rcp_f16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0xa8,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_rcp_f16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0xa8,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_rcp_f16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0xa8,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_rcp_f16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0xa8,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_rcp_f16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0xa8,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_rcp_f16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0xa8,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_rcp_f16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0xa8,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_rcp_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0xa8,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_rcp_f16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0xa8,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_rcp_f16_dpp v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xa8,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
+0xfa,0xa8,0xfe,0x7e,0x7f,0x6f,0x3d,0x30
+
+# GFX12: v_rcp_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x54,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_rcp_f32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x54,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_rcp_f32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x54,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_rcp_f32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x54,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_rcp_f32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x54,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_rcp_f32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x54,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_rcp_f32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x54,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_rcp_f32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x54,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_rcp_f32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x54,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_rcp_f32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x54,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_rcp_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x54,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_rcp_f32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x54,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_rcp_f32_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x54,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
+0xfa,0x54,0xfe,0x7f,0xff,0x6f,0x3d,0x30
+
+# GFX12: v_rcp_iflag_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x56,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_rcp_iflag_f32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x56,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_rcp_iflag_f32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x56,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_rcp_iflag_f32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x56,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_rcp_iflag_f32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x56,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_rcp_iflag_f32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x56,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_rcp_iflag_f32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x56,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_rcp_iflag_f32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x56,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_rcp_iflag_f32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x56,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_rcp_iflag_f32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x56,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_rcp_iflag_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x56,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_rcp_iflag_f32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x56,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_rcp_iflag_f32_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x56,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
+0xfa,0x56,0xfe,0x7f,0xff,0x6f,0x3d,0x30
+
+# GFX12: v_rndne_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0xbc,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_rndne_f16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0xbc,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_rndne_f16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0xbc,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_rndne_f16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0xbc,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_rndne_f16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0xbc,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_rndne_f16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0xbc,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_rndne_f16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0xbc,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_rndne_f16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0xbc,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_rndne_f16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0xbc,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_rndne_f16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0xbc,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_rndne_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0xbc,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_rndne_f16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0xbc,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_rndne_f16_dpp v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xbc,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
+0xfa,0xbc,0xfe,0x7e,0x7f,0x6f,0x3d,0x30
+
+# GFX12: v_rndne_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x46,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_rndne_f32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x46,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_rndne_f32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x46,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_rndne_f32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x46,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_rndne_f32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x46,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_rndne_f32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x46,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_rndne_f32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x46,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_rndne_f32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x46,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_rndne_f32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x46,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_rndne_f32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x46,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_rndne_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x46,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_rndne_f32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x46,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_rndne_f32_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x46,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
+0xfa,0x46,0xfe,0x7f,0xff,0x6f,0x3d,0x30
+
+# GFX12: v_rsq_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0xac,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_rsq_f16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0xac,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_rsq_f16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0xac,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_rsq_f16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0xac,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_rsq_f16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0xac,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_rsq_f16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0xac,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_rsq_f16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0xac,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_rsq_f16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0xac,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_rsq_f16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0xac,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_rsq_f16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0xac,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_rsq_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0xac,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_rsq_f16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0xac,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_rsq_f16_dpp v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xac,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
+0xfa,0xac,0xfe,0x7e,0x7f,0x6f,0x3d,0x30
+
+# GFX12: v_rsq_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x5c,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_rsq_f32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x5c,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_rsq_f32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x5c,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_rsq_f32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x5c,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_rsq_f32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x5c,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_rsq_f32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x5c,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_rsq_f32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x5c,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_rsq_f32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x5c,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_rsq_f32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x5c,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_rsq_f32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x5c,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_rsq_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x5c,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_rsq_f32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x5c,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_rsq_f32_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x5c,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
+0xfa,0x5c,0xfe,0x7f,0xff,0x6f,0x3d,0x30
+
+# GFX12: v_sat_pk_u8_i16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc4,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0xc4,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_sat_pk_u8_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc4,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0xc4,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_sat_pk_u8_i16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc4,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0xc4,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_sat_pk_u8_i16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc4,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0xc4,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_sat_pk_u8_i16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc4,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0xc4,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_sat_pk_u8_i16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc4,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0xc4,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_sat_pk_u8_i16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc4,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0xc4,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_sat_pk_u8_i16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc4,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0xc4,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_sat_pk_u8_i16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc4,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0xc4,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_sat_pk_u8_i16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc4,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0xc4,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_sat_pk_u8_i16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc4,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0xc4,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_sat_pk_u8_i16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xc4,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0xc4,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_sat_pk_u8_i16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xc4,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0xc4,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_sat_pk_u8_i16_dpp v127, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc4,0xfe,0x7e,0xff,0x6f,0x0d,0x30]
+0xfa,0xc4,0xfe,0x7e,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_sin_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0xc0,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_sin_f16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0xc0,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_sin_f16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0xc0,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_sin_f16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0xc0,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_sin_f16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0xc0,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_sin_f16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0xc0,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_sin_f16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0xc0,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_sin_f16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0xc0,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_sin_f16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0xc0,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_sin_f16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0xc0,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_sin_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0xc0,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_sin_f16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0xc0,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_sin_f16_dpp v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xc0,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
+0xfa,0xc0,0xfe,0x7e,0x7f,0x6f,0x3d,0x30
+
+# GFX12: v_sin_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x6a,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_sin_f32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x6a,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_sin_f32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x6a,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_sin_f32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x6a,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_sin_f32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x6a,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_sin_f32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x6a,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_sin_f32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x6a,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_sin_f32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x6a,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_sin_f32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x6a,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_sin_f32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x6a,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_sin_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x6a,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_sin_f32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x6a,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_sin_f32_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x6a,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
+0xfa,0x6a,0xfe,0x7f,0xff,0x6f,0x3d,0x30
+
+# GFX12: v_sqrt_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0xaa,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_sqrt_f16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0xaa,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_sqrt_f16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0xaa,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_sqrt_f16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0xaa,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_sqrt_f16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0xaa,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_sqrt_f16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0xaa,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_sqrt_f16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0xaa,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_sqrt_f16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0xaa,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_sqrt_f16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0xaa,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_sqrt_f16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0xaa,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_sqrt_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0xaa,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_sqrt_f16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0xaa,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_sqrt_f16_dpp v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xaa,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
+0xfa,0xaa,0xfe,0x7e,0x7f,0x6f,0x3d,0x30
+
+# GFX12: v_sqrt_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x66,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_sqrt_f32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x66,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_sqrt_f32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x66,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_sqrt_f32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x66,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_sqrt_f32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x66,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_sqrt_f32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x66,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_sqrt_f32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x66,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_sqrt_f32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x66,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_sqrt_f32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x66,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_sqrt_f32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x66,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_sqrt_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x66,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_sqrt_f32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x66,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_sqrt_f32_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x66,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
+0xfa,0x66,0xfe,0x7f,0xff,0x6f,0x3d,0x30
+
+# GFX12: v_trunc_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0xba,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_trunc_f16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0xba,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_trunc_f16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0xba,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_trunc_f16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0xba,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_trunc_f16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0xba,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_trunc_f16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0xba,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_trunc_f16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0xba,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_trunc_f16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0xba,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_trunc_f16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0xba,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_trunc_f16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0xba,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_trunc_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0xba,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_trunc_f16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0xba,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_trunc_f16_dpp v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xba,0xfe,0x7e,0x7f,0x6f,0x3d,0x30]
+0xfa,0xba,0xfe,0x7e,0x7f,0x6f,0x3d,0x30
+
+# GFX12: v_trunc_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+0xfa,0x42,0x0a,0x7e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_trunc_f32_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x40,0x01,0xff]
+0xfa,0x42,0x0a,0x7e,0x01,0x40,0x01,0xff
+
+# GFX12: v_trunc_f32_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x41,0x01,0xff]
+0xfa,0x42,0x0a,0x7e,0x01,0x41,0x01,0xff
+
+# GFX12: v_trunc_f32_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x01,0x01,0xff]
+0xfa,0x42,0x0a,0x7e,0x01,0x01,0x01,0xff
+
+# GFX12: v_trunc_f32_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+0xfa,0x42,0x0a,0x7e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_trunc_f32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x11,0x01,0xff]
+0xfa,0x42,0x0a,0x7e,0x01,0x11,0x01,0xff
+
+# GFX12: v_trunc_f32_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+0xfa,0x42,0x0a,0x7e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_trunc_f32_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x21,0x01,0xff]
+0xfa,0x42,0x0a,0x7e,0x01,0x21,0x01,0xff
+
+# GFX12: v_trunc_f32_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+0xfa,0x42,0x0a,0x7e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_trunc_f32_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x50,0x01,0xff]
+0xfa,0x42,0x0a,0x7e,0x01,0x50,0x01,0xff
+
+# GFX12: v_trunc_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+0xfa,0x42,0x0a,0x7e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_trunc_f32_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x60,0x01,0x13]
+0xfa,0x42,0x0a,0x7e,0x01,0x60,0x01,0x13
+
+# GFX12: v_trunc_f32_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x42,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
+0xfa,0x42,0xfe,0x7f,0xff,0x6f,0x3d,0x30
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp8.txt
new file mode 100644
index 000000000000..928165997dd9
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp8.txt
@@ -0,0 +1,374 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX12 %s
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX12 %s
+
+# GFX12: v_bfrev_b32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x70,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x70,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfrev_b32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x70,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x70,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_ceil_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb8,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0xb8,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_ceil_f16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb8,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+0xea,0xb8,0xfe,0x7e,0x7f,0x00,0x00,0x00
+
+# GFX12: v_ceil_f32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x44,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x44,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_ceil_f32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x44,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x44,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_cls_i32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x76,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x76,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_cls_i32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x76,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x76,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_clz_i32_u32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x72,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x72,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_clz_i32_u32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x72,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x72,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_cos_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc2,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0xc2,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_cos_f16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc2,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+0xea,0xc2,0xfe,0x7e,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cos_f32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x6c,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x6c,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_cos_f32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x6c,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x6c,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_ctz_i32_b32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x74,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x74,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_ctz_i32_b32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x74,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x74,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_f32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x14,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x14,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f16_f32_dpp v127, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x14,0xfe,0x7e,0xff,0x00,0x00,0x00]
+0xea,0x14,0xfe,0x7e,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_i16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa2,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0xa2,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f16_i16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa2,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+0xea,0xa2,0xfe,0x7e,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_u16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa0,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0xa0,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f16_u16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa0,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+0xea,0xa0,0xfe,0x7e,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x16,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x16,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f32_f16_dpp v255, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x16,0xfe,0x7f,0x7f,0x00,0x00,0x00]
+0xea,0x16,0xfe,0x7f,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_i32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x0a,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x0a,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f32_i32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x0a,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x0a,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_u32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x0c,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x0c,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f32_u32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x0c,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x0c,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte0_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x22,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x22,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f32_ubyte0_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x22,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x22,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte1_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x24,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x24,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f32_ubyte1_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x24,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x24,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte2_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x26,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x26,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f32_ubyte2_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x26,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x26,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte3_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x28,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x28,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f32_ubyte3_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x28,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x28,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_floor_i32_f32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x1a,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x1a,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_floor_i32_f32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x1a,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x1a,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_i16_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa6,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0xa6,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_i16_f16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa6,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+0xea,0xa6,0xfe,0x7e,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_f32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x10,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x10,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_i32_f32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x10,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x10,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_i16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xd4,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0xd4,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_i32_i16_dpp v255, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xd4,0xfe,0x7f,0x7f,0x00,0x00,0x00]
+0xea,0xd4,0xfe,0x7f,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_nearest_i32_f32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x18,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x18,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_nearest_i32_f32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x18,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x18,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_norm_i16_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc6,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0xc6,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_norm_i16_f16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc6,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+0xea,0xc6,0xfe,0x7e,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_norm_u16_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc8,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0xc8,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_norm_u16_f16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc8,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+0xea,0xc8,0xfe,0x7e,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_off_f32_i4_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x1c,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x1c,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_off_f32_i4_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x1c,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x1c,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_u16_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa4,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0xa4,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_u16_f16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa4,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+0xea,0xa4,0xfe,0x7e,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_f32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x0e,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x0e,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_u32_f32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x0e,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x0e,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_u16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xd6,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0xd6,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_u32_u16_dpp v255, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xd6,0xfe,0x7f,0x7f,0x00,0x00,0x00]
+0xea,0xd6,0xfe,0x7f,0x7f,0x00,0x00,0x00
+
+# GFX12: v_exp_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb0,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0xb0,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_exp_f16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb0,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+0xea,0xb0,0xfe,0x7e,0x7f,0x00,0x00,0x00
+
+# GFX12: v_exp_f32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x4a,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x4a,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_exp_f32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x4a,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x4a,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_floor_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb6,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0xb6,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_floor_f16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb6,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+0xea,0xb6,0xfe,0x7e,0x7f,0x00,0x00,0x00
+
+# GFX12: v_floor_f32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x48,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x48,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_floor_f32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x48,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x48,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_fract_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xbe,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0xbe,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_fract_f16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xbe,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+0xea,0xbe,0xfe,0x7e,0x7f,0x00,0x00,0x00
+
+# GFX12: v_fract_f32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x40,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x40,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_fract_f32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x40,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x40,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i16_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb4,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0xb4,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_frexp_exp_i16_f16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb4,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+0xea,0xb4,0xfe,0x7e,0x7f,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i32_f32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x7e,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x7e,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_frexp_exp_i32_f32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x7e,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x7e,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb2,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0xb2,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_frexp_mant_f16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xb2,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+0xea,0xb2,0xfe,0x7e,0x7f,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x80,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x80,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_frexp_mant_f32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x80,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x80,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_log_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xae,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0xae,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_log_f16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xae,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+0xea,0xae,0xfe,0x7e,0x7f,0x00,0x00,0x00
+
+# GFX12: v_log_f32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x4e,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x4e,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_log_f32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x4e,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x4e,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_mov_b32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x02,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x02,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_mov_b32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x02,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x02,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_movreld_b32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x84,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x84,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_movreld_b32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x84,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x84,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_movrels_b32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x86,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x86,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_movrels_b32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x86,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x86,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_movrelsd_2_b32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x90,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x90,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_movrelsd_2_b32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x90,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x90,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_movrelsd_b32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x88,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x88,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_movrelsd_b32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x88,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x88,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_not_b16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xd2,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0xd2,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_not_b16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xd2,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+0xea,0xd2,0xfe,0x7e,0x7f,0x00,0x00,0x00
+
+# GFX12: v_not_b32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x6e,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x6e,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_not_b32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x6e,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x6e,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_rcp_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xa8,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0xa8,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_rcp_f16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xa8,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+0xea,0xa8,0xfe,0x7e,0x7f,0x00,0x00,0x00
+
+# GFX12: v_rcp_f32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x54,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x54,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_rcp_f32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x54,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x54,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_rcp_iflag_f32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x56,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x56,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_rcp_iflag_f32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x56,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x56,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_rndne_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xbc,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0xbc,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_rndne_f16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xbc,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+0xea,0xbc,0xfe,0x7e,0x7f,0x00,0x00,0x00
+
+# GFX12: v_rndne_f32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x46,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x46,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_rndne_f32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x46,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x46,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_rsq_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xac,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0xac,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_rsq_f16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xac,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+0xea,0xac,0xfe,0x7e,0x7f,0x00,0x00,0x00
+
+# GFX12: v_rsq_f32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x5c,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x5c,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_rsq_f32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x5c,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x5c,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_sat_pk_u8_i16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc4,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0xc4,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_sat_pk_u8_i16_dpp v127, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc4,0xfe,0x7e,0xff,0x00,0x00,0x00]
+0xea,0xc4,0xfe,0x7e,0xff,0x00,0x00,0x00
+
+# GFX12: v_sin_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc0,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0xc0,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_sin_f16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xc0,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+0xea,0xc0,0xfe,0x7e,0x7f,0x00,0x00,0x00
+
+# GFX12: v_sin_f32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x6a,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x6a,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_sin_f32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x6a,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x6a,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xaa,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0xaa,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_sqrt_f16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xaa,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+0xea,0xaa,0xfe,0x7e,0x7f,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x66,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x66,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_sqrt_f32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x66,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x66,0xfe,0x7f,0xff,0x00,0x00,0x00
+
+# GFX12: v_trunc_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xba,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0xba,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_trunc_f16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xba,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+0xea,0xba,0xfe,0x7e,0x7f,0x00,0x00,0x00
+
+# GFX12: v_trunc_f32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x42,0x0a,0x7e,0x01,0x77,0x39,0x05]
+0xe9,0x42,0x0a,0x7e,0x01,0x77,0x39,0x05
+
+# GFX12: v_trunc_f32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0x42,0xfe,0x7f,0xff,0x00,0x00,0x00]
+0xea,0x42,0xfe,0x7f,0xff,0x00,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2.txt
new file mode 100644
index 000000000000..05f4f184c903
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2.txt
@@ -0,0 +1,2228 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32 %s
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64 %s
+
+# W32: v_add_co_ci_u32_e32 v5, vcc_lo, v1, v2, vcc_lo ; encoding: [0x01,0x05,0x0a,0x40]
+# W64: v_add_co_ci_u32_e32 v5, vcc, v1, v2, vcc ; encoding: [0x01,0x05,0x0a,0x40]
+0x01,0x05,0x0a,0x40
+
+# W32: v_add_co_ci_u32_e32 v5, vcc_lo, v255, v2, vcc_lo ; encoding: [0xff,0x05,0x0a,0x40]
+# W64: v_add_co_ci_u32_e32 v5, vcc, v255, v2, vcc ; encoding: [0xff,0x05,0x0a,0x40]
+0xff,0x05,0x0a,0x40
+
+# W32: v_add_co_ci_u32_e32 v5, vcc_lo, s1, v2, vcc_lo ; encoding: [0x01,0x04,0x0a,0x40]
+# W64: v_add_co_ci_u32_e32 v5, vcc, s1, v2, vcc ; encoding: [0x01,0x04,0x0a,0x40]
+0x01,0x04,0x0a,0x40
+
+# W32: v_add_co_ci_u32_e32 v5, vcc_lo, s105, v2, vcc_lo ; encoding: [0x69,0x04,0x0a,0x40]
+# W64: v_add_co_ci_u32_e32 v5, vcc, s105, v2, vcc ; encoding: [0x69,0x04,0x0a,0x40]
+0x69,0x04,0x0a,0x40
+
+# W32: v_add_co_ci_u32_e32 v5, vcc_lo, vcc_lo, v2, vcc_lo ; encoding: [0x6a,0x04,0x0a,0x40]
+# W64: v_add_co_ci_u32_e32 v5, vcc, vcc_lo, v2, vcc ; encoding: [0x6a,0x04,0x0a,0x40]
+0x6a,0x04,0x0a,0x40
+
+# W32: v_add_co_ci_u32_e32 v5, vcc_lo, vcc_hi, v2, vcc_lo ; encoding: [0x6b,0x04,0x0a,0x40]
+# W64: v_add_co_ci_u32_e32 v5, vcc, vcc_hi, v2, vcc ; encoding: [0x6b,0x04,0x0a,0x40]
+0x6b,0x04,0x0a,0x40
+
+# W32: v_add_co_ci_u32_e32 v5, vcc_lo, ttmp15, v2, vcc_lo ; encoding: [0x7b,0x04,0x0a,0x40]
+# W64: v_add_co_ci_u32_e32 v5, vcc, ttmp15, v2, vcc ; encoding: [0x7b,0x04,0x0a,0x40]
+0x7b,0x04,0x0a,0x40
+
+# W32: v_add_co_ci_u32_e32 v5, vcc_lo, m0, v2, vcc_lo ; encoding: [0x7d,0x04,0x0a,0x40]
+# W64: v_add_co_ci_u32_e32 v5, vcc, m0, v2, vcc ; encoding: [0x7d,0x04,0x0a,0x40]
+0x7d,0x04,0x0a,0x40
+
+# W32: v_add_co_ci_u32_e32 v5, vcc_lo, exec_lo, v2, vcc_lo ; encoding: [0x7e,0x04,0x0a,0x40]
+# W64: v_add_co_ci_u32_e32 v5, vcc, exec_lo, v2, vcc ; encoding: [0x7e,0x04,0x0a,0x40]
+0x7e,0x04,0x0a,0x40
+
+# W32: v_add_co_ci_u32_e32 v5, vcc_lo, exec_hi, v2, vcc_lo ; encoding: [0x7f,0x04,0x0a,0x40]
+# W64: v_add_co_ci_u32_e32 v5, vcc, exec_hi, v2, vcc ; encoding: [0x7f,0x04,0x0a,0x40]
+0x7f,0x04,0x0a,0x40
+
+# W32: v_add_co_ci_u32_e32 v5, vcc_lo, null, v2, vcc_lo ; encoding: [0x7c,0x04,0x0a,0x40]
+# W64: v_add_co_ci_u32_e32 v5, vcc, null, v2, vcc ; encoding: [0x7c,0x04,0x0a,0x40]
+0x7c,0x04,0x0a,0x40
+
+# W32: v_add_co_ci_u32_e32 v5, vcc_lo, -1, v2, vcc_lo ; encoding: [0xc1,0x04,0x0a,0x40]
+# W64: v_add_co_ci_u32_e32 v5, vcc, -1, v2, vcc ; encoding: [0xc1,0x04,0x0a,0x40]
+0xc1,0x04,0x0a,0x40
+
+# W32: v_add_co_ci_u32_e32 v5, vcc_lo, 0.5, v2, vcc_lo ; encoding: [0xf0,0x04,0x0a,0x40]
+# W64: v_add_co_ci_u32_e32 v5, vcc, 0.5, v2, vcc ; encoding: [0xf0,0x04,0x0a,0x40]
+0xf0,0x04,0x0a,0x40
+
+# W32: v_add_co_ci_u32_e32 v5, vcc_lo, src_scc, v2, vcc_lo ; encoding: [0xfd,0x04,0x0a,0x40]
+# W64: v_add_co_ci_u32_e32 v5, vcc, src_scc, v2, vcc ; encoding: [0xfd,0x04,0x0a,0x40]
+0xfd,0x04,0x0a,0x40
+
+# W32: v_add_co_ci_u32_e32 v255, vcc_lo, 0xaf123456, v255, vcc_lo ; encoding: [0xff,0xfe,0xff,0x41,0x56,0x34,0x12,0xaf]
+# W64: v_add_co_ci_u32_e32 v255, vcc, 0xaf123456, v255, vcc ; encoding: [0xff,0xfe,0xff,0x41,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x41,0x56,0x34,0x12,0xaf
+
+# GFX12: v_add_f16_e32 v5, v1, v2                ; encoding: [0x01,0x05,0x0a,0x64]
+0x01,0x05,0x0a,0x64
+
+# GFX12: v_add_f16_e32 v5, v127, v2              ; encoding: [0x7f,0x05,0x0a,0x64]
+0x7f,0x05,0x0a,0x64
+
+# GFX12: v_add_f16_e32 v5, s1, v2                ; encoding: [0x01,0x04,0x0a,0x64]
+0x01,0x04,0x0a,0x64
+
+# GFX12: v_add_f16_e32 v5, s105, v2              ; encoding: [0x69,0x04,0x0a,0x64]
+0x69,0x04,0x0a,0x64
+
+# GFX12: v_add_f16_e32 v5, vcc_lo, v2            ; encoding: [0x6a,0x04,0x0a,0x64]
+0x6a,0x04,0x0a,0x64
+
+# GFX12: v_add_f16_e32 v5, vcc_hi, v2            ; encoding: [0x6b,0x04,0x0a,0x64]
+0x6b,0x04,0x0a,0x64
+
+# GFX12: v_add_f16_e32 v5, ttmp15, v2            ; encoding: [0x7b,0x04,0x0a,0x64]
+0x7b,0x04,0x0a,0x64
+
+# GFX12: v_add_f16_e32 v5, m0, v2                ; encoding: [0x7d,0x04,0x0a,0x64]
+0x7d,0x04,0x0a,0x64
+
+# GFX12: v_add_f16_e32 v5, exec_lo, v2           ; encoding: [0x7e,0x04,0x0a,0x64]
+0x7e,0x04,0x0a,0x64
+
+# GFX12: v_add_f16_e32 v5, exec_hi, v2           ; encoding: [0x7f,0x04,0x0a,0x64]
+0x7f,0x04,0x0a,0x64
+
+# GFX12: v_add_f16_e32 v5, null, v2              ; encoding: [0x7c,0x04,0x0a,0x64]
+0x7c,0x04,0x0a,0x64
+
+# GFX12: v_add_f16_e32 v5, -1, v2                ; encoding: [0xc1,0x04,0x0a,0x64]
+0xc1,0x04,0x0a,0x64
+
+# GFX12: v_add_f16_e32 v5, 0.5, v2               ; encoding: [0xf0,0x04,0x0a,0x64]
+0xf0,0x04,0x0a,0x64
+
+# GFX12: v_add_f16_e32 v5, src_scc, v2           ; encoding: [0xfd,0x04,0x0a,0x64]
+0xfd,0x04,0x0a,0x64
+
+# GFX12: v_add_f16_e32 v127, 0xfe0b, v127        ; encoding: [0xff,0xfe,0xfe,0x64,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0xfe,0x64,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_add_f32_e32 v5, v1, v2                ; encoding: [0x01,0x05,0x0a,0x06]
+0x01,0x05,0x0a,0x06
+
+# GFX12: v_add_f32_e32 v5, v255, v2              ; encoding: [0xff,0x05,0x0a,0x06]
+0xff,0x05,0x0a,0x06
+
+# GFX12: v_add_f32_e32 v5, s1, v2                ; encoding: [0x01,0x04,0x0a,0x06]
+0x01,0x04,0x0a,0x06
+
+# GFX12: v_add_f32_e32 v5, s105, v2              ; encoding: [0x69,0x04,0x0a,0x06]
+0x69,0x04,0x0a,0x06
+
+# GFX12: v_add_f32_e32 v5, vcc_lo, v2            ; encoding: [0x6a,0x04,0x0a,0x06]
+0x6a,0x04,0x0a,0x06
+
+# GFX12: v_add_f32_e32 v5, vcc_hi, v2            ; encoding: [0x6b,0x04,0x0a,0x06]
+0x6b,0x04,0x0a,0x06
+
+# GFX12: v_add_f32_e32 v5, ttmp15, v2            ; encoding: [0x7b,0x04,0x0a,0x06]
+0x7b,0x04,0x0a,0x06
+
+# GFX12: v_add_f32_e32 v5, m0, v2                ; encoding: [0x7d,0x04,0x0a,0x06]
+0x7d,0x04,0x0a,0x06
+
+# GFX12: v_add_f32_e32 v5, exec_lo, v2           ; encoding: [0x7e,0x04,0x0a,0x06]
+0x7e,0x04,0x0a,0x06
+
+# GFX12: v_add_f32_e32 v5, exec_hi, v2           ; encoding: [0x7f,0x04,0x0a,0x06]
+0x7f,0x04,0x0a,0x06
+
+# GFX12: v_add_f32_e32 v5, null, v2              ; encoding: [0x7c,0x04,0x0a,0x06]
+0x7c,0x04,0x0a,0x06
+
+# GFX12: v_add_f32_e32 v5, -1, v2                ; encoding: [0xc1,0x04,0x0a,0x06]
+0xc1,0x04,0x0a,0x06
+
+# GFX12: v_add_f32_e32 v5, 0.5, v2               ; encoding: [0xf0,0x04,0x0a,0x06]
+0xf0,0x04,0x0a,0x06
+
+# GFX12: v_add_f32_e32 v5, src_scc, v2           ; encoding: [0xfd,0x04,0x0a,0x06]
+0xfd,0x04,0x0a,0x06
+
+# GFX12: v_add_f32_e32 v255, 0xaf123456, v255    ; encoding: [0xff,0xfe,0xff,0x07,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_add_f64_e32 v[5:6], v[1:2], v[3:4]    ; encoding: [0x01,0x07,0x0a,0x04]
+0x01,0x07,0x0a,0x04
+
+# GFX12: v_add_f64_e32 v[5:6], v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x0a,0x04]
+0xfe,0x05,0x0a,0x04
+
+# GFX12: v_add_f64_e32 v[5:6], s[0:1], v[2:3]    ; encoding: [0x00,0x04,0x0a,0x04]
+0x00,0x04,0x0a,0x04
+
+# GFX12: v_add_f64_e32 v[5:6], s[104:105], v[2:3] ; encoding: [0x68,0x04,0x0a,0x04]
+0x68,0x04,0x0a,0x04
+
+# GFX12: v_add_f64_e32 v[5:6], vcc, v[2:3]       ; encoding: [0x6a,0x04,0x0a,0x04]
+0x6a,0x04,0x0a,0x04
+
+# GFX12: v_add_f64_e32 v[5:6], ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x0a,0x04]
+0x7a,0x04,0x0a,0x04
+
+# GFX12: v_add_f64_e32 v[5:6], exec, v[2:3]      ; encoding: [0x7e,0x04,0x0a,0x04]
+0x7e,0x04,0x0a,0x04
+
+# GFX12: v_add_f64_e32 v[5:6], null, v[2:3]      ; encoding: [0x7c,0x04,0x0a,0x04]
+0x7c,0x04,0x0a,0x04
+
+# GFX12: v_add_f64_e32 v[5:6], -1, v[2:3]        ; encoding: [0xc1,0x04,0x0a,0x04]
+0xc1,0x04,0x0a,0x04
+
+# GFX12: v_add_f64_e32 v[5:6], 0.5, v[2:3]       ; encoding: [0xf0,0x04,0x0a,0x04]
+0xf0,0x04,0x0a,0x04
+
+# GFX12: v_add_f64_e32 v[5:6], src_scc, v[2:3]   ; encoding: [0xfd,0x04,0x0a,0x04]
+0xfd,0x04,0x0a,0x04
+
+# GFX12: v_add_f64_e32 v[254:255], 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xfd,0x05,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xfd,0x05,0x56,0x34,0x12,0xaf
+
+# GFX12: v_add_nc_u32_e32 v5, v1, v2             ; encoding: [0x01,0x05,0x0a,0x4a]
+0x01,0x05,0x0a,0x4a
+
+# GFX12: v_add_nc_u32_e32 v5, v255, v2           ; encoding: [0xff,0x05,0x0a,0x4a]
+0xff,0x05,0x0a,0x4a
+
+# GFX12: v_add_nc_u32_e32 v5, s1, v2             ; encoding: [0x01,0x04,0x0a,0x4a]
+0x01,0x04,0x0a,0x4a
+
+# GFX12: v_add_nc_u32_e32 v5, s105, v2           ; encoding: [0x69,0x04,0x0a,0x4a]
+0x69,0x04,0x0a,0x4a
+
+# GFX12: v_add_nc_u32_e32 v5, vcc_lo, v2         ; encoding: [0x6a,0x04,0x0a,0x4a]
+0x6a,0x04,0x0a,0x4a
+
+# GFX12: v_add_nc_u32_e32 v5, vcc_hi, v2         ; encoding: [0x6b,0x04,0x0a,0x4a]
+0x6b,0x04,0x0a,0x4a
+
+# GFX12: v_add_nc_u32_e32 v5, ttmp15, v2         ; encoding: [0x7b,0x04,0x0a,0x4a]
+0x7b,0x04,0x0a,0x4a
+
+# GFX12: v_add_nc_u32_e32 v5, m0, v2             ; encoding: [0x7d,0x04,0x0a,0x4a]
+0x7d,0x04,0x0a,0x4a
+
+# GFX12: v_add_nc_u32_e32 v5, exec_lo, v2        ; encoding: [0x7e,0x04,0x0a,0x4a]
+0x7e,0x04,0x0a,0x4a
+
+# GFX12: v_add_nc_u32_e32 v5, exec_hi, v2        ; encoding: [0x7f,0x04,0x0a,0x4a]
+0x7f,0x04,0x0a,0x4a
+
+# GFX12: v_add_nc_u32_e32 v5, null, v2           ; encoding: [0x7c,0x04,0x0a,0x4a]
+0x7c,0x04,0x0a,0x4a
+
+# GFX12: v_add_nc_u32_e32 v5, -1, v2             ; encoding: [0xc1,0x04,0x0a,0x4a]
+0xc1,0x04,0x0a,0x4a
+
+# GFX12: v_add_nc_u32_e32 v5, 0.5, v2            ; encoding: [0xf0,0x04,0x0a,0x4a]
+0xf0,0x04,0x0a,0x4a
+
+# GFX12: v_add_nc_u32_e32 v5, src_scc, v2        ; encoding: [0xfd,0x04,0x0a,0x4a]
+0xfd,0x04,0x0a,0x4a
+
+# GFX12: v_add_nc_u32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x4b,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x4b,0x56,0x34,0x12,0xaf
+
+# GFX12: v_and_b32_e32 v5, v1, v2                ; encoding: [0x01,0x05,0x0a,0x36]
+0x01,0x05,0x0a,0x36
+
+# GFX12: v_and_b32_e32 v5, v255, v2              ; encoding: [0xff,0x05,0x0a,0x36]
+0xff,0x05,0x0a,0x36
+
+# GFX12: v_and_b32_e32 v5, s1, v2                ; encoding: [0x01,0x04,0x0a,0x36]
+0x01,0x04,0x0a,0x36
+
+# GFX12: v_and_b32_e32 v5, s105, v2              ; encoding: [0x69,0x04,0x0a,0x36]
+0x69,0x04,0x0a,0x36
+
+# GFX12: v_and_b32_e32 v5, vcc_lo, v2            ; encoding: [0x6a,0x04,0x0a,0x36]
+0x6a,0x04,0x0a,0x36
+
+# GFX12: v_and_b32_e32 v5, vcc_hi, v2            ; encoding: [0x6b,0x04,0x0a,0x36]
+0x6b,0x04,0x0a,0x36
+
+# GFX12: v_and_b32_e32 v5, ttmp15, v2            ; encoding: [0x7b,0x04,0x0a,0x36]
+0x7b,0x04,0x0a,0x36
+
+# GFX12: v_and_b32_e32 v5, m0, v2                ; encoding: [0x7d,0x04,0x0a,0x36]
+0x7d,0x04,0x0a,0x36
+
+# GFX12: v_and_b32_e32 v5, exec_lo, v2           ; encoding: [0x7e,0x04,0x0a,0x36]
+0x7e,0x04,0x0a,0x36
+
+# GFX12: v_and_b32_e32 v5, exec_hi, v2           ; encoding: [0x7f,0x04,0x0a,0x36]
+0x7f,0x04,0x0a,0x36
+
+# GFX12: v_and_b32_e32 v5, null, v2              ; encoding: [0x7c,0x04,0x0a,0x36]
+0x7c,0x04,0x0a,0x36
+
+# GFX12: v_and_b32_e32 v5, -1, v2                ; encoding: [0xc1,0x04,0x0a,0x36]
+0xc1,0x04,0x0a,0x36
+
+# GFX12: v_and_b32_e32 v5, 0.5, v2               ; encoding: [0xf0,0x04,0x0a,0x36]
+0xf0,0x04,0x0a,0x36
+
+# GFX12: v_and_b32_e32 v5, src_scc, v2           ; encoding: [0xfd,0x04,0x0a,0x36]
+0xfd,0x04,0x0a,0x36
+
+# GFX12: v_and_b32_e32 v255, 0xaf123456, v255    ; encoding: [0xff,0xfe,0xff,0x37,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x37,0x56,0x34,0x12,0xaf
+
+# GFX12: v_ashrrev_i32_e32 v5, v1, v2            ; encoding: [0x01,0x05,0x0a,0x34]
+0x01,0x05,0x0a,0x34
+
+# GFX12: v_ashrrev_i32_e32 v5, v255, v2          ; encoding: [0xff,0x05,0x0a,0x34]
+0xff,0x05,0x0a,0x34
+
+# GFX12: v_ashrrev_i32_e32 v5, s1, v2            ; encoding: [0x01,0x04,0x0a,0x34]
+0x01,0x04,0x0a,0x34
+
+# GFX12: v_ashrrev_i32_e32 v5, s105, v2          ; encoding: [0x69,0x04,0x0a,0x34]
+0x69,0x04,0x0a,0x34
+
+# GFX12: v_ashrrev_i32_e32 v5, vcc_lo, v2        ; encoding: [0x6a,0x04,0x0a,0x34]
+0x6a,0x04,0x0a,0x34
+
+# GFX12: v_ashrrev_i32_e32 v5, vcc_hi, v2        ; encoding: [0x6b,0x04,0x0a,0x34]
+0x6b,0x04,0x0a,0x34
+
+# GFX12: v_ashrrev_i32_e32 v5, ttmp15, v2        ; encoding: [0x7b,0x04,0x0a,0x34]
+0x7b,0x04,0x0a,0x34
+
+# GFX12: v_ashrrev_i32_e32 v5, m0, v2            ; encoding: [0x7d,0x04,0x0a,0x34]
+0x7d,0x04,0x0a,0x34
+
+# GFX12: v_ashrrev_i32_e32 v5, exec_lo, v2       ; encoding: [0x7e,0x04,0x0a,0x34]
+0x7e,0x04,0x0a,0x34
+
+# GFX12: v_ashrrev_i32_e32 v5, exec_hi, v2       ; encoding: [0x7f,0x04,0x0a,0x34]
+0x7f,0x04,0x0a,0x34
+
+# GFX12: v_ashrrev_i32_e32 v5, null, v2          ; encoding: [0x7c,0x04,0x0a,0x34]
+0x7c,0x04,0x0a,0x34
+
+# GFX12: v_ashrrev_i32_e32 v5, -1, v2            ; encoding: [0xc1,0x04,0x0a,0x34]
+0xc1,0x04,0x0a,0x34
+
+# GFX12: v_ashrrev_i32_e32 v5, 0.5, v2           ; encoding: [0xf0,0x04,0x0a,0x34]
+0xf0,0x04,0x0a,0x34
+
+# GFX12: v_ashrrev_i32_e32 v5, src_scc, v2       ; encoding: [0xfd,0x04,0x0a,0x34]
+0xfd,0x04,0x0a,0x34
+
+# GFX12: v_ashrrev_i32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x35,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x35,0x56,0x34,0x12,0xaf
+
+# W32: v_cndmask_b32_e32 v5, v1, v2, vcc_lo      ; encoding: [0x01,0x05,0x0a,0x02]
+# W64: v_cndmask_b32_e32 v5, v1, v2, vcc         ; encoding: [0x01,0x05,0x0a,0x02]
+0x01,0x05,0x0a,0x02
+
+# W32: v_cndmask_b32_e32 v5, v255, v2, vcc_lo    ; encoding: [0xff,0x05,0x0a,0x02]
+# W64: v_cndmask_b32_e32 v5, v255, v2, vcc       ; encoding: [0xff,0x05,0x0a,0x02]
+0xff,0x05,0x0a,0x02
+
+# W32: v_cndmask_b32_e32 v5, s1, v2, vcc_lo      ; encoding: [0x01,0x04,0x0a,0x02]
+# W64: v_cndmask_b32_e32 v5, s1, v2, vcc         ; encoding: [0x01,0x04,0x0a,0x02]
+0x01,0x04,0x0a,0x02
+
+# W32: v_cndmask_b32_e32 v5, s105, v2, vcc_lo    ; encoding: [0x69,0x04,0x0a,0x02]
+# W64: v_cndmask_b32_e32 v5, s105, v2, vcc       ; encoding: [0x69,0x04,0x0a,0x02]
+0x69,0x04,0x0a,0x02
+
+# W32: v_cndmask_b32_e32 v5, vcc_lo, v2, vcc_lo  ; encoding: [0x6a,0x04,0x0a,0x02]
+# W64: v_cndmask_b32_e32 v5, vcc_lo, v2, vcc     ; encoding: [0x6a,0x04,0x0a,0x02]
+0x6a,0x04,0x0a,0x02
+
+# W32: v_cndmask_b32_e32 v5, vcc_hi, v2, vcc_lo  ; encoding: [0x6b,0x04,0x0a,0x02]
+# W64: v_cndmask_b32_e32 v5, vcc_hi, v2, vcc     ; encoding: [0x6b,0x04,0x0a,0x02]
+0x6b,0x04,0x0a,0x02
+
+# W32: v_cndmask_b32_e32 v5, ttmp15, v2, vcc_lo  ; encoding: [0x7b,0x04,0x0a,0x02]
+# W64: v_cndmask_b32_e32 v5, ttmp15, v2, vcc     ; encoding: [0x7b,0x04,0x0a,0x02]
+0x7b,0x04,0x0a,0x02
+
+# W32: v_cndmask_b32_e32 v5, m0, v2, vcc_lo      ; encoding: [0x7d,0x04,0x0a,0x02]
+# W64: v_cndmask_b32_e32 v5, m0, v2, vcc         ; encoding: [0x7d,0x04,0x0a,0x02]
+0x7d,0x04,0x0a,0x02
+
+# W32: v_cndmask_b32_e32 v5, exec_lo, v2, vcc_lo ; encoding: [0x7e,0x04,0x0a,0x02]
+# W64: v_cndmask_b32_e32 v5, exec_lo, v2, vcc    ; encoding: [0x7e,0x04,0x0a,0x02]
+0x7e,0x04,0x0a,0x02
+
+# W32: v_cndmask_b32_e32 v5, exec_hi, v2, vcc_lo ; encoding: [0x7f,0x04,0x0a,0x02]
+# W64: v_cndmask_b32_e32 v5, exec_hi, v2, vcc    ; encoding: [0x7f,0x04,0x0a,0x02]
+0x7f,0x04,0x0a,0x02
+
+# W32: v_cndmask_b32_e32 v5, null, v2, vcc_lo    ; encoding: [0x7c,0x04,0x0a,0x02]
+# W64: v_cndmask_b32_e32 v5, null, v2, vcc       ; encoding: [0x7c,0x04,0x0a,0x02]
+0x7c,0x04,0x0a,0x02
+
+# W32: v_cndmask_b32_e32 v5, -1, v2, vcc_lo      ; encoding: [0xc1,0x04,0x0a,0x02]
+# W64: v_cndmask_b32_e32 v5, -1, v2, vcc         ; encoding: [0xc1,0x04,0x0a,0x02]
+0xc1,0x04,0x0a,0x02
+
+# W32: v_cndmask_b32_e32 v5, 0.5, v2, vcc_lo     ; encoding: [0xf0,0x04,0x0a,0x02]
+# W64: v_cndmask_b32_e32 v5, 0.5, v2, vcc        ; encoding: [0xf0,0x04,0x0a,0x02]
+0xf0,0x04,0x0a,0x02
+
+# W32: v_cndmask_b32_e32 v5, src_scc, v2, vcc_lo ; encoding: [0xfd,0x04,0x0a,0x02]
+# W64: v_cndmask_b32_e32 v5, src_scc, v2, vcc    ; encoding: [0xfd,0x04,0x0a,0x02]
+0xfd,0x04,0x0a,0x02
+
+# W32: v_cndmask_b32_e32 v255, 0xaf123456, v255, vcc_lo ; encoding: [0xff,0xfe,0xff,0x03,0x56,0x34,0x12,0xaf]
+# W64: v_cndmask_b32_e32 v255, 0xaf123456, v255, vcc ; encoding: [0xff,0xfe,0xff,0x03,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, v1, v2     ; encoding: [0x01,0x05,0x0a,0x5e]
+0x01,0x05,0x0a,0x5e
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, v255, v2   ; encoding: [0xff,0x05,0x0a,0x5e]
+0xff,0x05,0x0a,0x5e
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, s1, v2     ; encoding: [0x01,0x04,0x0a,0x5e]
+0x01,0x04,0x0a,0x5e
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, s105, v2   ; encoding: [0x69,0x04,0x0a,0x5e]
+0x69,0x04,0x0a,0x5e
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x5e]
+0x6a,0x04,0x0a,0x5e
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x5e]
+0x6b,0x04,0x0a,0x5e
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x5e]
+0x7b,0x04,0x0a,0x5e
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, m0, v2     ; encoding: [0x7d,0x04,0x0a,0x5e]
+0x7d,0x04,0x0a,0x5e
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x5e]
+0x7e,0x04,0x0a,0x5e
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x5e]
+0x7f,0x04,0x0a,0x5e
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, null, v2   ; encoding: [0x7c,0x04,0x0a,0x5e]
+0x7c,0x04,0x0a,0x5e
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, -1, v2     ; encoding: [0xc1,0x04,0x0a,0x5e]
+0xc1,0x04,0x0a,0x5e
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, 0.5, v2    ; encoding: [0xf0,0x04,0x0a,0x5e]
+0xf0,0x04,0x0a,0x5e
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x5e]
+0xfd,0x04,0x0a,0x5e
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x5f,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x5f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmaak_f16 v5, v1, v2, 0xfe0b          ; encoding: [0x01,0x05,0x0a,0x70,0x0b,0xfe,0x00,0x00]
+0x01,0x05,0x0a,0x70,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmaak_f16 v5, v127, v2, 0xfe0b        ; encoding: [0x7f,0x05,0x0a,0x70,0x0b,0xfe,0x00,0x00]
+0x7f,0x05,0x0a,0x70,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmaak_f16 v5, s1, v2, 0xfe0b          ; encoding: [0x01,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00]
+0x01,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmaak_f16 v5, s105, v2, 0xfe0b        ; encoding: [0x69,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00]
+0x69,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmaak_f16 v5, vcc_lo, v2, 0xfe0b      ; encoding: [0x6a,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00]
+0x6a,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmaak_f16 v5, vcc_hi, v2, 0xfe0b      ; encoding: [0x6b,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00]
+0x6b,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmaak_f16 v5, ttmp15, v2, 0xfe0b      ; encoding: [0x7b,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00]
+0x7b,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmaak_f16 v5, m0, v2, 0xfe0b          ; encoding: [0x7d,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00]
+0x7d,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmaak_f16 v5, exec_lo, v2, 0xfe0b     ; encoding: [0x7e,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00]
+0x7e,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmaak_f16 v5, exec_hi, v2, 0xfe0b     ; encoding: [0x7f,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00]
+0x7f,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmaak_f16 v5, null, v2, 0xfe0b        ; encoding: [0x7c,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00]
+0x7c,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmaak_f16 v5, -1, v2, 0xfe0b          ; encoding: [0xc1,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00]
+0xc1,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmaak_f16 v5, 0.5, v2, 0xfe0b         ; encoding: [0xf0,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00]
+0xf0,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmaak_f16 v5, src_scc, v2, 0xfe0b     ; encoding: [0xfd,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00]
+0xfd,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmaak_f16 v127, 0xfe0b, v127, 0xfe0b  ; encoding: [0xff,0xfe,0xfe,0x70,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0xfe,0x70,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmaak_f32 v5, v1, v2, 0xaf123456      ; encoding: [0x01,0x05,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+0x01,0x05,0x0a,0x5a,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmaak_f32 v5, v255, v2, 0xaf123456    ; encoding: [0xff,0x05,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+0xff,0x05,0x0a,0x5a,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmaak_f32 v5, s1, v2, 0xaf123456      ; encoding: [0x01,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+0x01,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmaak_f32 v5, s105, v2, 0xaf123456    ; encoding: [0x69,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+0x69,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmaak_f32 v5, vcc_lo, v2, 0xaf123456  ; encoding: [0x6a,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+0x6a,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmaak_f32 v5, vcc_hi, v2, 0xaf123456  ; encoding: [0x6b,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+0x6b,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmaak_f32 v5, ttmp15, v2, 0xaf123456  ; encoding: [0x7b,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+0x7b,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmaak_f32 v5, m0, v2, 0xaf123456      ; encoding: [0x7d,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+0x7d,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmaak_f32 v5, exec_lo, v2, 0xaf123456 ; encoding: [0x7e,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+0x7e,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmaak_f32 v5, exec_hi, v2, 0xaf123456 ; encoding: [0x7f,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+0x7f,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmaak_f32 v5, null, v2, 0xaf123456    ; encoding: [0x7c,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+0x7c,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmaak_f32 v5, -1, v2, 0xaf123456      ; encoding: [0xc1,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+0xc1,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmaak_f32 v5, 0.5, v2, 0xaf123456     ; encoding: [0xf0,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+0xf0,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmaak_f32 v5, src_scc, v2, 0xaf123456 ; encoding: [0xfd,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+0xfd,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmaak_f32 v255, 0xaf123456, v255, 0xaf123456 ; encoding: [0xff,0xfe,0xff,0x5b,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x5b,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmac_f16_e32 v5, v1, v2               ; encoding: [0x01,0x05,0x0a,0x6c]
+0x01,0x05,0x0a,0x6c
+
+# GFX12: v_fmac_f16_e32 v5, v127, v2             ; encoding: [0x7f,0x05,0x0a,0x6c]
+0x7f,0x05,0x0a,0x6c
+
+# GFX12: v_fmac_f16_e32 v5, s1, v2               ; encoding: [0x01,0x04,0x0a,0x6c]
+0x01,0x04,0x0a,0x6c
+
+# GFX12: v_fmac_f16_e32 v5, s105, v2             ; encoding: [0x69,0x04,0x0a,0x6c]
+0x69,0x04,0x0a,0x6c
+
+# GFX12: v_fmac_f16_e32 v5, vcc_lo, v2           ; encoding: [0x6a,0x04,0x0a,0x6c]
+0x6a,0x04,0x0a,0x6c
+
+# GFX12: v_fmac_f16_e32 v5, vcc_hi, v2           ; encoding: [0x6b,0x04,0x0a,0x6c]
+0x6b,0x04,0x0a,0x6c
+
+# GFX12: v_fmac_f16_e32 v5, ttmp15, v2           ; encoding: [0x7b,0x04,0x0a,0x6c]
+0x7b,0x04,0x0a,0x6c
+
+# GFX12: v_fmac_f16_e32 v5, m0, v2               ; encoding: [0x7d,0x04,0x0a,0x6c]
+0x7d,0x04,0x0a,0x6c
+
+# GFX12: v_fmac_f16_e32 v5, exec_lo, v2          ; encoding: [0x7e,0x04,0x0a,0x6c]
+0x7e,0x04,0x0a,0x6c
+
+# GFX12: v_fmac_f16_e32 v5, exec_hi, v2          ; encoding: [0x7f,0x04,0x0a,0x6c]
+0x7f,0x04,0x0a,0x6c
+
+# GFX12: v_fmac_f16_e32 v5, null, v2             ; encoding: [0x7c,0x04,0x0a,0x6c]
+0x7c,0x04,0x0a,0x6c
+
+# GFX12: v_fmac_f16_e32 v5, -1, v2               ; encoding: [0xc1,0x04,0x0a,0x6c]
+0xc1,0x04,0x0a,0x6c
+
+# GFX12: v_fmac_f16_e32 v5, 0.5, v2              ; encoding: [0xf0,0x04,0x0a,0x6c]
+0xf0,0x04,0x0a,0x6c
+
+# GFX12: v_fmac_f16_e32 v5, src_scc, v2          ; encoding: [0xfd,0x04,0x0a,0x6c]
+0xfd,0x04,0x0a,0x6c
+
+# GFX12: v_fmac_f16_e32 v127, 0xfe0b, v127       ; encoding: [0xff,0xfe,0xfe,0x6c,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0xfe,0x6c,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmac_f32_e32 v5, v1, v2               ; encoding: [0x01,0x05,0x0a,0x56]
+0x01,0x05,0x0a,0x56
+
+# GFX12: v_fmac_f32_e32 v5, v255, v2             ; encoding: [0xff,0x05,0x0a,0x56]
+0xff,0x05,0x0a,0x56
+
+# GFX12: v_fmac_f32_e32 v5, s1, v2               ; encoding: [0x01,0x04,0x0a,0x56]
+0x01,0x04,0x0a,0x56
+
+# GFX12: v_fmac_f32_e32 v5, s105, v2             ; encoding: [0x69,0x04,0x0a,0x56]
+0x69,0x04,0x0a,0x56
+
+# GFX12: v_fmac_f32_e32 v5, vcc_lo, v2           ; encoding: [0x6a,0x04,0x0a,0x56]
+0x6a,0x04,0x0a,0x56
+
+# GFX12: v_fmac_f32_e32 v5, vcc_hi, v2           ; encoding: [0x6b,0x04,0x0a,0x56]
+0x6b,0x04,0x0a,0x56
+
+# GFX12: v_fmac_f32_e32 v5, ttmp15, v2           ; encoding: [0x7b,0x04,0x0a,0x56]
+0x7b,0x04,0x0a,0x56
+
+# GFX12: v_fmac_f32_e32 v5, m0, v2               ; encoding: [0x7d,0x04,0x0a,0x56]
+0x7d,0x04,0x0a,0x56
+
+# GFX12: v_fmac_f32_e32 v5, exec_lo, v2          ; encoding: [0x7e,0x04,0x0a,0x56]
+0x7e,0x04,0x0a,0x56
+
+# GFX12: v_fmac_f32_e32 v5, exec_hi, v2          ; encoding: [0x7f,0x04,0x0a,0x56]
+0x7f,0x04,0x0a,0x56
+
+# GFX12: v_fmac_f32_e32 v5, null, v2             ; encoding: [0x7c,0x04,0x0a,0x56]
+0x7c,0x04,0x0a,0x56
+
+# GFX12: v_fmac_f32_e32 v5, -1, v2               ; encoding: [0xc1,0x04,0x0a,0x56]
+0xc1,0x04,0x0a,0x56
+
+# GFX12: v_fmac_f32_e32 v5, 0.5, v2              ; encoding: [0xf0,0x04,0x0a,0x56]
+0xf0,0x04,0x0a,0x56
+
+# GFX12: v_fmac_f32_e32 v5, src_scc, v2          ; encoding: [0xfd,0x04,0x0a,0x56]
+0xfd,0x04,0x0a,0x56
+
+# GFX12: v_fmac_f32_e32 v255, 0xaf123456, v255   ; encoding: [0xff,0xfe,0xff,0x57,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x57,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmamk_f16 v5, v1, 0xfe0b, v3          ; encoding: [0x01,0x07,0x0a,0x6e,0x0b,0xfe,0x00,0x00]
+0x01,0x07,0x0a,0x6e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmamk_f16 v5, v127, 0xfe0b, v3        ; encoding: [0x7f,0x07,0x0a,0x6e,0x0b,0xfe,0x00,0x00]
+0x7f,0x07,0x0a,0x6e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmamk_f16 v5, s1, 0xfe0b, v3          ; encoding: [0x01,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00]
+0x01,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmamk_f16 v5, s105, 0xfe0b, v3        ; encoding: [0x69,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00]
+0x69,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmamk_f16 v5, vcc_lo, 0xfe0b, v3      ; encoding: [0x6a,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00]
+0x6a,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmamk_f16 v5, vcc_hi, 0xfe0b, v3      ; encoding: [0x6b,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00]
+0x6b,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmamk_f16 v5, ttmp15, 0xfe0b, v3      ; encoding: [0x7b,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00]
+0x7b,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmamk_f16 v5, m0, 0xfe0b, v3          ; encoding: [0x7d,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00]
+0x7d,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmamk_f16 v5, exec_lo, 0xfe0b, v3     ; encoding: [0x7e,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00]
+0x7e,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmamk_f16 v5, exec_hi, 0xfe0b, v3     ; encoding: [0x7f,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00]
+0x7f,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmamk_f16 v5, null, 0xfe0b, v3        ; encoding: [0x7c,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00]
+0x7c,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmamk_f16 v5, -1, 0xfe0b, v3          ; encoding: [0xc1,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00]
+0xc1,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmamk_f16 v5, 0.5, 0xfe0b, v3         ; encoding: [0xf0,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00]
+0xf0,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmamk_f16 v5, src_scc, 0xfe0b, v3     ; encoding: [0xfd,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00]
+0xfd,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmamk_f16 v127, 0xfe0b, 0xfe0b, v127  ; encoding: [0xff,0xfe,0xfe,0x6e,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0xfe,0x6e,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmamk_f32 v5, v1, 0xaf123456, v3      ; encoding: [0x01,0x07,0x0a,0x58,0x56,0x34,0x12,0xaf]
+0x01,0x07,0x0a,0x58,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmamk_f32 v5, v255, 0xaf123456, v3    ; encoding: [0xff,0x07,0x0a,0x58,0x56,0x34,0x12,0xaf]
+0xff,0x07,0x0a,0x58,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmamk_f32 v5, s1, 0xaf123456, v3      ; encoding: [0x01,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf]
+0x01,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmamk_f32 v5, s105, 0xaf123456, v3    ; encoding: [0x69,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf]
+0x69,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmamk_f32 v5, vcc_lo, 0xaf123456, v3  ; encoding: [0x6a,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf]
+0x6a,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmamk_f32 v5, vcc_hi, 0xaf123456, v3  ; encoding: [0x6b,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf]
+0x6b,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmamk_f32 v5, ttmp15, 0xaf123456, v3  ; encoding: [0x7b,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf]
+0x7b,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmamk_f32 v5, m0, 0xaf123456, v3      ; encoding: [0x7d,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf]
+0x7d,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmamk_f32 v5, exec_lo, 0xaf123456, v3 ; encoding: [0x7e,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf]
+0x7e,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmamk_f32 v5, exec_hi, 0xaf123456, v3 ; encoding: [0x7f,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf]
+0x7f,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmamk_f32 v5, null, 0xaf123456, v3    ; encoding: [0x7c,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf]
+0x7c,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmamk_f32 v5, -1, 0xaf123456, v3      ; encoding: [0xc1,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf]
+0xc1,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmamk_f32 v5, 0.5, 0xaf123456, v3     ; encoding: [0xf0,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmamk_f32 v5, src_scc, 0xaf123456, v3 ; encoding: [0xfd,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf]
+0xfd,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x59,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x59,0x56,0x34,0x12,0xaf
+
+# GFX12: v_ldexp_f16_e32 v5, v1, v2              ; encoding: [0x01,0x05,0x0a,0x76]
+0x01,0x05,0x0a,0x76
+
+# GFX12: v_ldexp_f16_e32 v5, v127, v2            ; encoding: [0x7f,0x05,0x0a,0x76]
+0x7f,0x05,0x0a,0x76
+
+# GFX12: v_ldexp_f16_e32 v5, s1, v2              ; encoding: [0x01,0x04,0x0a,0x76]
+0x01,0x04,0x0a,0x76
+
+# GFX12: v_ldexp_f16_e32 v5, s105, v2            ; encoding: [0x69,0x04,0x0a,0x76]
+0x69,0x04,0x0a,0x76
+
+# GFX12: v_ldexp_f16_e32 v5, vcc_lo, v2          ; encoding: [0x6a,0x04,0x0a,0x76]
+0x6a,0x04,0x0a,0x76
+
+# GFX12: v_ldexp_f16_e32 v5, vcc_hi, v2          ; encoding: [0x6b,0x04,0x0a,0x76]
+0x6b,0x04,0x0a,0x76
+
+# GFX12: v_ldexp_f16_e32 v5, ttmp15, v2          ; encoding: [0x7b,0x04,0x0a,0x76]
+0x7b,0x04,0x0a,0x76
+
+# GFX12: v_ldexp_f16_e32 v5, m0, v2              ; encoding: [0x7d,0x04,0x0a,0x76]
+0x7d,0x04,0x0a,0x76
+
+# GFX12: v_ldexp_f16_e32 v5, exec_lo, v2         ; encoding: [0x7e,0x04,0x0a,0x76]
+0x7e,0x04,0x0a,0x76
+
+# GFX12: v_ldexp_f16_e32 v5, exec_hi, v2         ; encoding: [0x7f,0x04,0x0a,0x76]
+0x7f,0x04,0x0a,0x76
+
+# GFX12: v_ldexp_f16_e32 v5, null, v2            ; encoding: [0x7c,0x04,0x0a,0x76]
+0x7c,0x04,0x0a,0x76
+
+# GFX12: v_ldexp_f16_e32 v5, -1, v2              ; encoding: [0xc1,0x04,0x0a,0x76]
+0xc1,0x04,0x0a,0x76
+
+# GFX12: v_ldexp_f16_e32 v5, 0.5, v2             ; encoding: [0xf0,0x04,0x0a,0x76]
+0xf0,0x04,0x0a,0x76
+
+# GFX12: v_ldexp_f16_e32 v5, src_scc, v2         ; encoding: [0xfd,0x04,0x0a,0x76]
+0xfd,0x04,0x0a,0x76
+
+# GFX12: v_ldexp_f16_e32 v127, 0xfe0b, v127      ; encoding: [0xff,0xfe,0xfe,0x76,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0xfe,0x76,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_lshlrev_b32_e32 v5, v1, v2            ; encoding: [0x01,0x05,0x0a,0x30]
+0x01,0x05,0x0a,0x30
+
+# GFX12: v_lshlrev_b32_e32 v5, v255, v2          ; encoding: [0xff,0x05,0x0a,0x30]
+0xff,0x05,0x0a,0x30
+
+# GFX12: v_lshlrev_b32_e32 v5, s1, v2            ; encoding: [0x01,0x04,0x0a,0x30]
+0x01,0x04,0x0a,0x30
+
+# GFX12: v_lshlrev_b32_e32 v5, s105, v2          ; encoding: [0x69,0x04,0x0a,0x30]
+0x69,0x04,0x0a,0x30
+
+# GFX12: v_lshlrev_b32_e32 v5, vcc_lo, v2        ; encoding: [0x6a,0x04,0x0a,0x30]
+0x6a,0x04,0x0a,0x30
+
+# GFX12: v_lshlrev_b32_e32 v5, vcc_hi, v2        ; encoding: [0x6b,0x04,0x0a,0x30]
+0x6b,0x04,0x0a,0x30
+
+# GFX12: v_lshlrev_b32_e32 v5, ttmp15, v2        ; encoding: [0x7b,0x04,0x0a,0x30]
+0x7b,0x04,0x0a,0x30
+
+# GFX12: v_lshlrev_b32_e32 v5, m0, v2            ; encoding: [0x7d,0x04,0x0a,0x30]
+0x7d,0x04,0x0a,0x30
+
+# GFX12: v_lshlrev_b32_e32 v5, exec_lo, v2       ; encoding: [0x7e,0x04,0x0a,0x30]
+0x7e,0x04,0x0a,0x30
+
+# GFX12: v_lshlrev_b32_e32 v5, exec_hi, v2       ; encoding: [0x7f,0x04,0x0a,0x30]
+0x7f,0x04,0x0a,0x30
+
+# GFX12: v_lshlrev_b32_e32 v5, null, v2          ; encoding: [0x7c,0x04,0x0a,0x30]
+0x7c,0x04,0x0a,0x30
+
+# GFX12: v_lshlrev_b32_e32 v5, -1, v2            ; encoding: [0xc1,0x04,0x0a,0x30]
+0xc1,0x04,0x0a,0x30
+
+# GFX12: v_lshlrev_b32_e32 v5, 0.5, v2           ; encoding: [0xf0,0x04,0x0a,0x30]
+0xf0,0x04,0x0a,0x30
+
+# GFX12: v_lshlrev_b32_e32 v5, src_scc, v2       ; encoding: [0xfd,0x04,0x0a,0x30]
+0xfd,0x04,0x0a,0x30
+
+# GFX12: v_lshlrev_b32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x31,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x31,0x56,0x34,0x12,0xaf
+
+# GFX12: v_lshlrev_b64_e32 v[5:6], v1, v[3:4]    ; encoding: [0x01,0x07,0x0a,0x3e]
+0x01,0x07,0x0a,0x3e
+
+# GFX12: v_lshlrev_b64_e32 v[5:6], v255, v[2:3]  ; encoding: [0xff,0x05,0x0a,0x3e]
+0xff,0x05,0x0a,0x3e
+
+# GFX12: v_lshlrev_b64_e32 v[5:6], s1, v[2:3]    ; encoding: [0x01,0x04,0x0a,0x3e]
+0x01,0x04,0x0a,0x3e
+
+# GFX12: v_lshlrev_b64_e32 v[5:6], s105, v[2:3]  ; encoding: [0x69,0x04,0x0a,0x3e]
+0x69,0x04,0x0a,0x3e
+
+# GFX12: v_lshlrev_b64_e32 v[5:6], vcc_lo, v[2:3] ; encoding: [0x6a,0x04,0x0a,0x3e]
+0x6a,0x04,0x0a,0x3e
+
+# GFX12: v_lshlrev_b64_e32 v[5:6], vcc_hi, v[2:3] ; encoding: [0x6b,0x04,0x0a,0x3e]
+0x6b,0x04,0x0a,0x3e
+
+# GFX12: v_lshlrev_b64_e32 v[5:6], ttmp15, v[2:3] ; encoding: [0x7b,0x04,0x0a,0x3e]
+0x7b,0x04,0x0a,0x3e
+
+# GFX12: v_lshlrev_b64_e32 v[5:6], exec_lo, v[2:3] ; encoding: [0x7e,0x04,0x0a,0x3e]
+0x7e,0x04,0x0a,0x3e
+
+# GFX12: v_lshlrev_b64_e32 v[5:6], exec_hi, v[2:3] ; encoding: [0x7f,0x04,0x0a,0x3e]
+0x7f,0x04,0x0a,0x3e
+
+# GFX12: v_lshlrev_b64_e32 v[5:6], null, v[2:3]  ; encoding: [0x7c,0x04,0x0a,0x3e]
+0x7c,0x04,0x0a,0x3e
+
+# GFX12: v_lshlrev_b64_e32 v[5:6], -1, v[2:3]    ; encoding: [0xc1,0x04,0x0a,0x3e]
+0xc1,0x04,0x0a,0x3e
+
+# GFX12: v_lshlrev_b64_e32 v[5:6], 0.5, v[2:3]   ; encoding: [0xf0,0x04,0x0a,0x3e]
+0xf0,0x04,0x0a,0x3e
+
+# GFX12: v_lshlrev_b64_e32 v[5:6], src_scc, v[2:3] ; encoding: [0xfd,0x04,0x0a,0x3e]
+0xfd,0x04,0x0a,0x3e
+
+# GFX12: v_lshlrev_b64_e32 v[254:255], 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xfd,0x3f,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xfd,0x3f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_lshrrev_b32_e32 v5, v1, v2            ; encoding: [0x01,0x05,0x0a,0x32]
+0x01,0x05,0x0a,0x32
+
+# GFX12: v_lshrrev_b32_e32 v5, v255, v2          ; encoding: [0xff,0x05,0x0a,0x32]
+0xff,0x05,0x0a,0x32
+
+# GFX12: v_lshrrev_b32_e32 v5, s1, v2            ; encoding: [0x01,0x04,0x0a,0x32]
+0x01,0x04,0x0a,0x32
+
+# GFX12: v_lshrrev_b32_e32 v5, s105, v2          ; encoding: [0x69,0x04,0x0a,0x32]
+0x69,0x04,0x0a,0x32
+
+# GFX12: v_lshrrev_b32_e32 v5, vcc_lo, v2        ; encoding: [0x6a,0x04,0x0a,0x32]
+0x6a,0x04,0x0a,0x32
+
+# GFX12: v_lshrrev_b32_e32 v5, vcc_hi, v2        ; encoding: [0x6b,0x04,0x0a,0x32]
+0x6b,0x04,0x0a,0x32
+
+# GFX12: v_lshrrev_b32_e32 v5, ttmp15, v2        ; encoding: [0x7b,0x04,0x0a,0x32]
+0x7b,0x04,0x0a,0x32
+
+# GFX12: v_lshrrev_b32_e32 v5, m0, v2            ; encoding: [0x7d,0x04,0x0a,0x32]
+0x7d,0x04,0x0a,0x32
+
+# GFX12: v_lshrrev_b32_e32 v5, exec_lo, v2       ; encoding: [0x7e,0x04,0x0a,0x32]
+0x7e,0x04,0x0a,0x32
+
+# GFX12: v_lshrrev_b32_e32 v5, exec_hi, v2       ; encoding: [0x7f,0x04,0x0a,0x32]
+0x7f,0x04,0x0a,0x32
+
+# GFX12: v_lshrrev_b32_e32 v5, null, v2          ; encoding: [0x7c,0x04,0x0a,0x32]
+0x7c,0x04,0x0a,0x32
+
+# GFX12: v_lshrrev_b32_e32 v5, -1, v2            ; encoding: [0xc1,0x04,0x0a,0x32]
+0xc1,0x04,0x0a,0x32
+
+# GFX12: v_lshrrev_b32_e32 v5, 0.5, v2           ; encoding: [0xf0,0x04,0x0a,0x32]
+0xf0,0x04,0x0a,0x32
+
+# GFX12: v_lshrrev_b32_e32 v5, src_scc, v2       ; encoding: [0xfd,0x04,0x0a,0x32]
+0xfd,0x04,0x0a,0x32
+
+# GFX12: v_lshrrev_b32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x33,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x33,0x56,0x34,0x12,0xaf
+
+# GFX12: v_max_num_f16_e32 v5, v1, v2            ; encoding: [0x01,0x05,0x0a,0x62]
+0x01,0x05,0x0a,0x62
+
+# GFX12: v_max_num_f16_e32 v5, v127, v2          ; encoding: [0x7f,0x05,0x0a,0x62]
+0x7f,0x05,0x0a,0x62
+
+# GFX12: v_max_num_f16_e32 v5, s1, v2            ; encoding: [0x01,0x04,0x0a,0x62]
+0x01,0x04,0x0a,0x62
+
+# GFX12: v_max_num_f16_e32 v5, s105, v2          ; encoding: [0x69,0x04,0x0a,0x62]
+0x69,0x04,0x0a,0x62
+
+# GFX12: v_max_num_f16_e32 v5, vcc_lo, v2        ; encoding: [0x6a,0x04,0x0a,0x62]
+0x6a,0x04,0x0a,0x62
+
+# GFX12: v_max_num_f16_e32 v5, vcc_hi, v2        ; encoding: [0x6b,0x04,0x0a,0x62]
+0x6b,0x04,0x0a,0x62
+
+# GFX12: v_max_num_f16_e32 v5, ttmp15, v2        ; encoding: [0x7b,0x04,0x0a,0x62]
+0x7b,0x04,0x0a,0x62
+
+# GFX12: v_max_num_f16_e32 v5, m0, v2            ; encoding: [0x7d,0x04,0x0a,0x62]
+0x7d,0x04,0x0a,0x62
+
+# GFX12: v_max_num_f16_e32 v5, exec_lo, v2       ; encoding: [0x7e,0x04,0x0a,0x62]
+0x7e,0x04,0x0a,0x62
+
+# GFX12: v_max_num_f16_e32 v5, exec_hi, v2       ; encoding: [0x7f,0x04,0x0a,0x62]
+0x7f,0x04,0x0a,0x62
+
+# GFX12: v_max_num_f16_e32 v5, null, v2          ; encoding: [0x7c,0x04,0x0a,0x62]
+0x7c,0x04,0x0a,0x62
+
+# GFX12: v_max_num_f16_e32 v5, -1, v2            ; encoding: [0xc1,0x04,0x0a,0x62]
+0xc1,0x04,0x0a,0x62
+
+# GFX12: v_max_num_f16_e32 v5, 0.5, v2           ; encoding: [0xf0,0x04,0x0a,0x62]
+0xf0,0x04,0x0a,0x62
+
+# GFX12: v_max_num_f16_e32 v5, src_scc, v2       ; encoding: [0xfd,0x04,0x0a,0x62]
+0xfd,0x04,0x0a,0x62
+
+# GFX12: v_max_num_f16_e32 v127, 0xfe0b, v127    ; encoding: [0xff,0xfe,0xfe,0x62,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0xfe,0x62,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_max_num_f32_e32 v5, v1, v2            ; encoding: [0x01,0x05,0x0a,0x2c]
+0x01,0x05,0x0a,0x2c
+
+# GFX12: v_max_num_f32_e32 v5, v255, v2          ; encoding: [0xff,0x05,0x0a,0x2c]
+0xff,0x05,0x0a,0x2c
+
+# GFX12: v_max_num_f32_e32 v5, s1, v2            ; encoding: [0x01,0x04,0x0a,0x2c]
+0x01,0x04,0x0a,0x2c
+
+# GFX12: v_max_num_f32_e32 v5, s105, v2          ; encoding: [0x69,0x04,0x0a,0x2c]
+0x69,0x04,0x0a,0x2c
+
+# GFX12: v_max_num_f32_e32 v5, vcc_lo, v2        ; encoding: [0x6a,0x04,0x0a,0x2c]
+0x6a,0x04,0x0a,0x2c
+
+# GFX12: v_max_num_f32_e32 v5, vcc_hi, v2        ; encoding: [0x6b,0x04,0x0a,0x2c]
+0x6b,0x04,0x0a,0x2c
+
+# GFX12: v_max_num_f32_e32 v5, ttmp15, v2        ; encoding: [0x7b,0x04,0x0a,0x2c]
+0x7b,0x04,0x0a,0x2c
+
+# GFX12: v_max_num_f32_e32 v5, m0, v2            ; encoding: [0x7d,0x04,0x0a,0x2c]
+0x7d,0x04,0x0a,0x2c
+
+# GFX12: v_max_num_f32_e32 v5, exec_lo, v2       ; encoding: [0x7e,0x04,0x0a,0x2c]
+0x7e,0x04,0x0a,0x2c
+
+# GFX12: v_max_num_f32_e32 v5, exec_hi, v2       ; encoding: [0x7f,0x04,0x0a,0x2c]
+0x7f,0x04,0x0a,0x2c
+
+# GFX12: v_max_num_f32_e32 v5, null, v2          ; encoding: [0x7c,0x04,0x0a,0x2c]
+0x7c,0x04,0x0a,0x2c
+
+# GFX12: v_max_num_f32_e32 v5, -1, v2            ; encoding: [0xc1,0x04,0x0a,0x2c]
+0xc1,0x04,0x0a,0x2c
+
+# GFX12: v_max_num_f32_e32 v5, 0.5, v2           ; encoding: [0xf0,0x04,0x0a,0x2c]
+0xf0,0x04,0x0a,0x2c
+
+# GFX12: v_max_num_f32_e32 v5, src_scc, v2       ; encoding: [0xfd,0x04,0x0a,0x2c]
+0xfd,0x04,0x0a,0x2c
+
+# GFX12: v_max_num_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x2d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x2d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_max_num_f64_e32 v[5:6], v[1:2], v[3:4] ; encoding: [0x01,0x07,0x0a,0x1c]
+0x01,0x07,0x0a,0x1c
+
+# GFX12: v_max_num_f64_e32 v[5:6], v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x0a,0x1c]
+0xfe,0x05,0x0a,0x1c
+
+# GFX12: v_max_num_f64_e32 v[5:6], s[0:1], v[2:3] ; encoding: [0x00,0x04,0x0a,0x1c]
+0x00,0x04,0x0a,0x1c
+
+# GFX12: v_max_num_f64_e32 v[5:6], s[104:105], v[2:3] ; encoding: [0x68,0x04,0x0a,0x1c]
+0x68,0x04,0x0a,0x1c
+
+# GFX12: v_max_num_f64_e32 v[5:6], vcc, v[2:3]   ; encoding: [0x6a,0x04,0x0a,0x1c]
+0x6a,0x04,0x0a,0x1c
+
+# GFX12: v_max_num_f64_e32 v[5:6], ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x0a,0x1c]
+0x7a,0x04,0x0a,0x1c
+
+# GFX12: v_max_num_f64_e32 v[5:6], exec, v[2:3]  ; encoding: [0x7e,0x04,0x0a,0x1c]
+0x7e,0x04,0x0a,0x1c
+
+# GFX12: v_max_num_f64_e32 v[5:6], null, v[2:3]  ; encoding: [0x7c,0x04,0x0a,0x1c]
+0x7c,0x04,0x0a,0x1c
+
+# GFX12: v_max_num_f64_e32 v[5:6], -1, v[2:3]    ; encoding: [0xc1,0x04,0x0a,0x1c]
+0xc1,0x04,0x0a,0x1c
+
+# GFX12: v_max_num_f64_e32 v[5:6], 0.5, v[2:3]   ; encoding: [0xf0,0x04,0x0a,0x1c]
+0xf0,0x04,0x0a,0x1c
+
+# GFX12: v_max_num_f64_e32 v[5:6], src_scc, v[2:3] ; encoding: [0xfd,0x04,0x0a,0x1c]
+0xfd,0x04,0x0a,0x1c
+
+# GFX12: v_max_num_f64_e32 v[254:255], 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xfd,0x1d,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xfd,0x1d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_max_i32_e32 v5, v1, v2                ; encoding: [0x01,0x05,0x0a,0x24]
+0x01,0x05,0x0a,0x24
+
+# GFX12: v_max_i32_e32 v5, v255, v2              ; encoding: [0xff,0x05,0x0a,0x24]
+0xff,0x05,0x0a,0x24
+
+# GFX12: v_max_i32_e32 v5, s1, v2                ; encoding: [0x01,0x04,0x0a,0x24]
+0x01,0x04,0x0a,0x24
+
+# GFX12: v_max_i32_e32 v5, s105, v2              ; encoding: [0x69,0x04,0x0a,0x24]
+0x69,0x04,0x0a,0x24
+
+# GFX12: v_max_i32_e32 v5, vcc_lo, v2            ; encoding: [0x6a,0x04,0x0a,0x24]
+0x6a,0x04,0x0a,0x24
+
+# GFX12: v_max_i32_e32 v5, vcc_hi, v2            ; encoding: [0x6b,0x04,0x0a,0x24]
+0x6b,0x04,0x0a,0x24
+
+# GFX12: v_max_i32_e32 v5, ttmp15, v2            ; encoding: [0x7b,0x04,0x0a,0x24]
+0x7b,0x04,0x0a,0x24
+
+# GFX12: v_max_i32_e32 v5, m0, v2                ; encoding: [0x7d,0x04,0x0a,0x24]
+0x7d,0x04,0x0a,0x24
+
+# GFX12: v_max_i32_e32 v5, exec_lo, v2           ; encoding: [0x7e,0x04,0x0a,0x24]
+0x7e,0x04,0x0a,0x24
+
+# GFX12: v_max_i32_e32 v5, exec_hi, v2           ; encoding: [0x7f,0x04,0x0a,0x24]
+0x7f,0x04,0x0a,0x24
+
+# GFX12: v_max_i32_e32 v5, null, v2              ; encoding: [0x7c,0x04,0x0a,0x24]
+0x7c,0x04,0x0a,0x24
+
+# GFX12: v_max_i32_e32 v5, -1, v2                ; encoding: [0xc1,0x04,0x0a,0x24]
+0xc1,0x04,0x0a,0x24
+
+# GFX12: v_max_i32_e32 v5, 0.5, v2               ; encoding: [0xf0,0x04,0x0a,0x24]
+0xf0,0x04,0x0a,0x24
+
+# GFX12: v_max_i32_e32 v5, src_scc, v2           ; encoding: [0xfd,0x04,0x0a,0x24]
+0xfd,0x04,0x0a,0x24
+
+# GFX12: v_max_i32_e32 v255, 0xaf123456, v255    ; encoding: [0xff,0xfe,0xff,0x25,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x25,0x56,0x34,0x12,0xaf
+
+# GFX12: v_max_u32_e32 v5, v1, v2                ; encoding: [0x01,0x05,0x0a,0x28]
+0x01,0x05,0x0a,0x28
+
+# GFX12: v_max_u32_e32 v5, v255, v2              ; encoding: [0xff,0x05,0x0a,0x28]
+0xff,0x05,0x0a,0x28
+
+# GFX12: v_max_u32_e32 v5, s1, v2                ; encoding: [0x01,0x04,0x0a,0x28]
+0x01,0x04,0x0a,0x28
+
+# GFX12: v_max_u32_e32 v5, s105, v2              ; encoding: [0x69,0x04,0x0a,0x28]
+0x69,0x04,0x0a,0x28
+
+# GFX12: v_max_u32_e32 v5, vcc_lo, v2            ; encoding: [0x6a,0x04,0x0a,0x28]
+0x6a,0x04,0x0a,0x28
+
+# GFX12: v_max_u32_e32 v5, vcc_hi, v2            ; encoding: [0x6b,0x04,0x0a,0x28]
+0x6b,0x04,0x0a,0x28
+
+# GFX12: v_max_u32_e32 v5, ttmp15, v2            ; encoding: [0x7b,0x04,0x0a,0x28]
+0x7b,0x04,0x0a,0x28
+
+# GFX12: v_max_u32_e32 v5, m0, v2                ; encoding: [0x7d,0x04,0x0a,0x28]
+0x7d,0x04,0x0a,0x28
+
+# GFX12: v_max_u32_e32 v5, exec_lo, v2           ; encoding: [0x7e,0x04,0x0a,0x28]
+0x7e,0x04,0x0a,0x28
+
+# GFX12: v_max_u32_e32 v5, exec_hi, v2           ; encoding: [0x7f,0x04,0x0a,0x28]
+0x7f,0x04,0x0a,0x28
+
+# GFX12: v_max_u32_e32 v5, null, v2              ; encoding: [0x7c,0x04,0x0a,0x28]
+0x7c,0x04,0x0a,0x28
+
+# GFX12: v_max_u32_e32 v5, -1, v2                ; encoding: [0xc1,0x04,0x0a,0x28]
+0xc1,0x04,0x0a,0x28
+
+# GFX12: v_max_u32_e32 v5, 0.5, v2               ; encoding: [0xf0,0x04,0x0a,0x28]
+0xf0,0x04,0x0a,0x28
+
+# GFX12: v_max_u32_e32 v5, src_scc, v2           ; encoding: [0xfd,0x04,0x0a,0x28]
+0xfd,0x04,0x0a,0x28
+
+# GFX12: v_max_u32_e32 v255, 0xaf123456, v255    ; encoding: [0xff,0xfe,0xff,0x29,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x29,0x56,0x34,0x12,0xaf
+
+# GFX12: v_min_num_f16_e32 v5, v1, v2            ; encoding: [0x01,0x05,0x0a,0x60]
+0x01,0x05,0x0a,0x60
+
+# GFX12: v_min_num_f16_e32 v5, v127, v2          ; encoding: [0x7f,0x05,0x0a,0x60]
+0x7f,0x05,0x0a,0x60
+
+# GFX12: v_min_num_f16_e32 v5, s1, v2            ; encoding: [0x01,0x04,0x0a,0x60]
+0x01,0x04,0x0a,0x60
+
+# GFX12: v_min_num_f16_e32 v5, s105, v2          ; encoding: [0x69,0x04,0x0a,0x60]
+0x69,0x04,0x0a,0x60
+
+# GFX12: v_min_num_f16_e32 v5, vcc_lo, v2        ; encoding: [0x6a,0x04,0x0a,0x60]
+0x6a,0x04,0x0a,0x60
+
+# GFX12: v_min_num_f16_e32 v5, vcc_hi, v2        ; encoding: [0x6b,0x04,0x0a,0x60]
+0x6b,0x04,0x0a,0x60
+
+# GFX12: v_min_num_f16_e32 v5, ttmp15, v2        ; encoding: [0x7b,0x04,0x0a,0x60]
+0x7b,0x04,0x0a,0x60
+
+# GFX12: v_min_num_f16_e32 v5, m0, v2            ; encoding: [0x7d,0x04,0x0a,0x60]
+0x7d,0x04,0x0a,0x60
+
+# GFX12: v_min_num_f16_e32 v5, exec_lo, v2       ; encoding: [0x7e,0x04,0x0a,0x60]
+0x7e,0x04,0x0a,0x60
+
+# GFX12: v_min_num_f16_e32 v5, exec_hi, v2       ; encoding: [0x7f,0x04,0x0a,0x60]
+0x7f,0x04,0x0a,0x60
+
+# GFX12: v_min_num_f16_e32 v5, null, v2          ; encoding: [0x7c,0x04,0x0a,0x60]
+0x7c,0x04,0x0a,0x60
+
+# GFX12: v_min_num_f16_e32 v5, -1, v2            ; encoding: [0xc1,0x04,0x0a,0x60]
+0xc1,0x04,0x0a,0x60
+
+# GFX12: v_min_num_f16_e32 v5, 0.5, v2           ; encoding: [0xf0,0x04,0x0a,0x60]
+0xf0,0x04,0x0a,0x60
+
+# GFX12: v_min_num_f16_e32 v5, src_scc, v2       ; encoding: [0xfd,0x04,0x0a,0x60]
+0xfd,0x04,0x0a,0x60
+
+# GFX12: v_min_num_f16_e32 v127, 0xfe0b, v127    ; encoding: [0xff,0xfe,0xfe,0x60,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0xfe,0x60,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_min_num_f32_e32 v5, v1, v2            ; encoding: [0x01,0x05,0x0a,0x2a]
+0x01,0x05,0x0a,0x2a
+
+# GFX12: v_min_num_f32_e32 v5, v255, v2          ; encoding: [0xff,0x05,0x0a,0x2a]
+0xff,0x05,0x0a,0x2a
+
+# GFX12: v_min_num_f32_e32 v5, s1, v2            ; encoding: [0x01,0x04,0x0a,0x2a]
+0x01,0x04,0x0a,0x2a
+
+# GFX12: v_min_num_f32_e32 v5, s105, v2          ; encoding: [0x69,0x04,0x0a,0x2a]
+0x69,0x04,0x0a,0x2a
+
+# GFX12: v_min_num_f32_e32 v5, vcc_lo, v2        ; encoding: [0x6a,0x04,0x0a,0x2a]
+0x6a,0x04,0x0a,0x2a
+
+# GFX12: v_min_num_f32_e32 v5, vcc_hi, v2        ; encoding: [0x6b,0x04,0x0a,0x2a]
+0x6b,0x04,0x0a,0x2a
+
+# GFX12: v_min_num_f32_e32 v5, ttmp15, v2        ; encoding: [0x7b,0x04,0x0a,0x2a]
+0x7b,0x04,0x0a,0x2a
+
+# GFX12: v_min_num_f32_e32 v5, m0, v2            ; encoding: [0x7d,0x04,0x0a,0x2a]
+0x7d,0x04,0x0a,0x2a
+
+# GFX12: v_min_num_f32_e32 v5, exec_lo, v2       ; encoding: [0x7e,0x04,0x0a,0x2a]
+0x7e,0x04,0x0a,0x2a
+
+# GFX12: v_min_num_f32_e32 v5, exec_hi, v2       ; encoding: [0x7f,0x04,0x0a,0x2a]
+0x7f,0x04,0x0a,0x2a
+
+# GFX12: v_min_num_f32_e32 v5, null, v2          ; encoding: [0x7c,0x04,0x0a,0x2a]
+0x7c,0x04,0x0a,0x2a
+
+# GFX12: v_min_num_f32_e32 v5, -1, v2            ; encoding: [0xc1,0x04,0x0a,0x2a]
+0xc1,0x04,0x0a,0x2a
+
+# GFX12: v_min_num_f32_e32 v5, 0.5, v2           ; encoding: [0xf0,0x04,0x0a,0x2a]
+0xf0,0x04,0x0a,0x2a
+
+# GFX12: v_min_num_f32_e32 v5, src_scc, v2       ; encoding: [0xfd,0x04,0x0a,0x2a]
+0xfd,0x04,0x0a,0x2a
+
+# GFX12: v_min_num_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x2b,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x2b,0x56,0x34,0x12,0xaf
+
+# GFX12: v_min_num_f64_e32 v[5:6], v[1:2], v[3:4] ; encoding: [0x01,0x07,0x0a,0x1a]
+0x01,0x07,0x0a,0x1a
+
+# GFX12: v_min_num_f64_e32 v[5:6], v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x0a,0x1a]
+0xfe,0x05,0x0a,0x1a
+
+# GFX12: v_min_num_f64_e32 v[5:6], s[0:1], v[2:3] ; encoding: [0x00,0x04,0x0a,0x1a]
+0x00,0x04,0x0a,0x1a
+
+# GFX12: v_min_num_f64_e32 v[5:6], s[104:105], v[2:3] ; encoding: [0x68,0x04,0x0a,0x1a]
+0x68,0x04,0x0a,0x1a
+
+# GFX12: v_min_num_f64_e32 v[5:6], vcc, v[2:3]   ; encoding: [0x6a,0x04,0x0a,0x1a]
+0x6a,0x04,0x0a,0x1a
+
+# GFX12: v_min_num_f64_e32 v[5:6], ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x0a,0x1a]
+0x7a,0x04,0x0a,0x1a
+
+# GFX12: v_min_num_f64_e32 v[5:6], exec, v[2:3]  ; encoding: [0x7e,0x04,0x0a,0x1a]
+0x7e,0x04,0x0a,0x1a
+
+# GFX12: v_min_num_f64_e32 v[5:6], null, v[2:3]  ; encoding: [0x7c,0x04,0x0a,0x1a]
+0x7c,0x04,0x0a,0x1a
+
+# GFX12: v_min_num_f64_e32 v[5:6], -1, v[2:3]    ; encoding: [0xc1,0x04,0x0a,0x1a]
+0xc1,0x04,0x0a,0x1a
+
+# GFX12: v_min_num_f64_e32 v[5:6], 0.5, v[2:3]   ; encoding: [0xf0,0x04,0x0a,0x1a]
+0xf0,0x04,0x0a,0x1a
+
+# GFX12: v_min_num_f64_e32 v[5:6], src_scc, v[2:3] ; encoding: [0xfd,0x04,0x0a,0x1a]
+0xfd,0x04,0x0a,0x1a
+
+# GFX12: v_min_num_f64_e32 v[254:255], 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xfd,0x1b,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xfd,0x1b,0x56,0x34,0x12,0xaf
+
+# GFX12: v_min_i32_e32 v5, v1, v2                ; encoding: [0x01,0x05,0x0a,0x22]
+0x01,0x05,0x0a,0x22
+
+# GFX12: v_min_i32_e32 v5, v255, v2              ; encoding: [0xff,0x05,0x0a,0x22]
+0xff,0x05,0x0a,0x22
+
+# GFX12: v_min_i32_e32 v5, s1, v2                ; encoding: [0x01,0x04,0x0a,0x22]
+0x01,0x04,0x0a,0x22
+
+# GFX12: v_min_i32_e32 v5, s105, v2              ; encoding: [0x69,0x04,0x0a,0x22]
+0x69,0x04,0x0a,0x22
+
+# GFX12: v_min_i32_e32 v5, vcc_lo, v2            ; encoding: [0x6a,0x04,0x0a,0x22]
+0x6a,0x04,0x0a,0x22
+
+# GFX12: v_min_i32_e32 v5, vcc_hi, v2            ; encoding: [0x6b,0x04,0x0a,0x22]
+0x6b,0x04,0x0a,0x22
+
+# GFX12: v_min_i32_e32 v5, ttmp15, v2            ; encoding: [0x7b,0x04,0x0a,0x22]
+0x7b,0x04,0x0a,0x22
+
+# GFX12: v_min_i32_e32 v5, m0, v2                ; encoding: [0x7d,0x04,0x0a,0x22]
+0x7d,0x04,0x0a,0x22
+
+# GFX12: v_min_i32_e32 v5, exec_lo, v2           ; encoding: [0x7e,0x04,0x0a,0x22]
+0x7e,0x04,0x0a,0x22
+
+# GFX12: v_min_i32_e32 v5, exec_hi, v2           ; encoding: [0x7f,0x04,0x0a,0x22]
+0x7f,0x04,0x0a,0x22
+
+# GFX12: v_min_i32_e32 v5, null, v2              ; encoding: [0x7c,0x04,0x0a,0x22]
+0x7c,0x04,0x0a,0x22
+
+# GFX12: v_min_i32_e32 v5, -1, v2                ; encoding: [0xc1,0x04,0x0a,0x22]
+0xc1,0x04,0x0a,0x22
+
+# GFX12: v_min_i32_e32 v5, 0.5, v2               ; encoding: [0xf0,0x04,0x0a,0x22]
+0xf0,0x04,0x0a,0x22
+
+# GFX12: v_min_i32_e32 v5, src_scc, v2           ; encoding: [0xfd,0x04,0x0a,0x22]
+0xfd,0x04,0x0a,0x22
+
+# GFX12: v_min_i32_e32 v255, 0xaf123456, v255    ; encoding: [0xff,0xfe,0xff,0x23,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x23,0x56,0x34,0x12,0xaf
+
+# GFX12: v_min_u32_e32 v5, v1, v2                ; encoding: [0x01,0x05,0x0a,0x26]
+0x01,0x05,0x0a,0x26
+
+# GFX12: v_min_u32_e32 v5, v255, v2              ; encoding: [0xff,0x05,0x0a,0x26]
+0xff,0x05,0x0a,0x26
+
+# GFX12: v_min_u32_e32 v5, s1, v2                ; encoding: [0x01,0x04,0x0a,0x26]
+0x01,0x04,0x0a,0x26
+
+# GFX12: v_min_u32_e32 v5, s105, v2              ; encoding: [0x69,0x04,0x0a,0x26]
+0x69,0x04,0x0a,0x26
+
+# GFX12: v_min_u32_e32 v5, vcc_lo, v2            ; encoding: [0x6a,0x04,0x0a,0x26]
+0x6a,0x04,0x0a,0x26
+
+# GFX12: v_min_u32_e32 v5, vcc_hi, v2            ; encoding: [0x6b,0x04,0x0a,0x26]
+0x6b,0x04,0x0a,0x26
+
+# GFX12: v_min_u32_e32 v5, ttmp15, v2            ; encoding: [0x7b,0x04,0x0a,0x26]
+0x7b,0x04,0x0a,0x26
+
+# GFX12: v_min_u32_e32 v5, m0, v2                ; encoding: [0x7d,0x04,0x0a,0x26]
+0x7d,0x04,0x0a,0x26
+
+# GFX12: v_min_u32_e32 v5, exec_lo, v2           ; encoding: [0x7e,0x04,0x0a,0x26]
+0x7e,0x04,0x0a,0x26
+
+# GFX12: v_min_u32_e32 v5, exec_hi, v2           ; encoding: [0x7f,0x04,0x0a,0x26]
+0x7f,0x04,0x0a,0x26
+
+# GFX12: v_min_u32_e32 v5, null, v2              ; encoding: [0x7c,0x04,0x0a,0x26]
+0x7c,0x04,0x0a,0x26
+
+# GFX12: v_min_u32_e32 v5, -1, v2                ; encoding: [0xc1,0x04,0x0a,0x26]
+0xc1,0x04,0x0a,0x26
+
+# GFX12: v_min_u32_e32 v5, 0.5, v2               ; encoding: [0xf0,0x04,0x0a,0x26]
+0xf0,0x04,0x0a,0x26
+
+# GFX12: v_min_u32_e32 v5, src_scc, v2           ; encoding: [0xfd,0x04,0x0a,0x26]
+0xfd,0x04,0x0a,0x26
+
+# GFX12: v_min_u32_e32 v255, 0xaf123456, v255    ; encoding: [0xff,0xfe,0xff,0x27,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x27,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mul_dx9_zero_f32_e32 v5, v1, v2       ; encoding: [0x01,0x05,0x0a,0x0e]
+0x01,0x05,0x0a,0x0e
+
+# GFX12: v_mul_dx9_zero_f32_e32 v5, v255, v2     ; encoding: [0xff,0x05,0x0a,0x0e]
+0xff,0x05,0x0a,0x0e
+
+# GFX12: v_mul_dx9_zero_f32_e32 v5, s1, v2       ; encoding: [0x01,0x04,0x0a,0x0e]
+0x01,0x04,0x0a,0x0e
+
+# GFX12: v_mul_dx9_zero_f32_e32 v5, s105, v2     ; encoding: [0x69,0x04,0x0a,0x0e]
+0x69,0x04,0x0a,0x0e
+
+# GFX12: v_mul_dx9_zero_f32_e32 v5, vcc_lo, v2   ; encoding: [0x6a,0x04,0x0a,0x0e]
+0x6a,0x04,0x0a,0x0e
+
+# GFX12: v_mul_dx9_zero_f32_e32 v5, vcc_hi, v2   ; encoding: [0x6b,0x04,0x0a,0x0e]
+0x6b,0x04,0x0a,0x0e
+
+# GFX12: v_mul_dx9_zero_f32_e32 v5, ttmp15, v2   ; encoding: [0x7b,0x04,0x0a,0x0e]
+0x7b,0x04,0x0a,0x0e
+
+# GFX12: v_mul_dx9_zero_f32_e32 v5, m0, v2       ; encoding: [0x7d,0x04,0x0a,0x0e]
+0x7d,0x04,0x0a,0x0e
+
+# GFX12: v_mul_dx9_zero_f32_e32 v5, exec_lo, v2  ; encoding: [0x7e,0x04,0x0a,0x0e]
+0x7e,0x04,0x0a,0x0e
+
+# GFX12: v_mul_dx9_zero_f32_e32 v5, exec_hi, v2  ; encoding: [0x7f,0x04,0x0a,0x0e]
+0x7f,0x04,0x0a,0x0e
+
+# GFX12: v_mul_dx9_zero_f32_e32 v5, null, v2     ; encoding: [0x7c,0x04,0x0a,0x0e]
+0x7c,0x04,0x0a,0x0e
+
+# GFX12: v_mul_dx9_zero_f32_e32 v5, -1, v2       ; encoding: [0xc1,0x04,0x0a,0x0e]
+0xc1,0x04,0x0a,0x0e
+
+# GFX12: v_mul_dx9_zero_f32_e32 v5, 0.5, v2      ; encoding: [0xf0,0x04,0x0a,0x0e]
+0xf0,0x04,0x0a,0x0e
+
+# GFX12: v_mul_dx9_zero_f32_e32 v5, src_scc, v2  ; encoding: [0xfd,0x04,0x0a,0x0e]
+0xfd,0x04,0x0a,0x0e
+
+# GFX12: v_mul_dx9_zero_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x0f,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x0f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mul_f16_e32 v5, v1, v2                ; encoding: [0x01,0x05,0x0a,0x6a]
+0x01,0x05,0x0a,0x6a
+
+# GFX12: v_mul_f16_e32 v5, v127, v2              ; encoding: [0x7f,0x05,0x0a,0x6a]
+0x7f,0x05,0x0a,0x6a
+
+# GFX12: v_mul_f16_e32 v5, s1, v2                ; encoding: [0x01,0x04,0x0a,0x6a]
+0x01,0x04,0x0a,0x6a
+
+# GFX12: v_mul_f16_e32 v5, s105, v2              ; encoding: [0x69,0x04,0x0a,0x6a]
+0x69,0x04,0x0a,0x6a
+
+# GFX12: v_mul_f16_e32 v5, vcc_lo, v2            ; encoding: [0x6a,0x04,0x0a,0x6a]
+0x6a,0x04,0x0a,0x6a
+
+# GFX12: v_mul_f16_e32 v5, vcc_hi, v2            ; encoding: [0x6b,0x04,0x0a,0x6a]
+0x6b,0x04,0x0a,0x6a
+
+# GFX12: v_mul_f16_e32 v5, ttmp15, v2            ; encoding: [0x7b,0x04,0x0a,0x6a]
+0x7b,0x04,0x0a,0x6a
+
+# GFX12: v_mul_f16_e32 v5, m0, v2                ; encoding: [0x7d,0x04,0x0a,0x6a]
+0x7d,0x04,0x0a,0x6a
+
+# GFX12: v_mul_f16_e32 v5, exec_lo, v2           ; encoding: [0x7e,0x04,0x0a,0x6a]
+0x7e,0x04,0x0a,0x6a
+
+# GFX12: v_mul_f16_e32 v5, exec_hi, v2           ; encoding: [0x7f,0x04,0x0a,0x6a]
+0x7f,0x04,0x0a,0x6a
+
+# GFX12: v_mul_f16_e32 v5, null, v2              ; encoding: [0x7c,0x04,0x0a,0x6a]
+0x7c,0x04,0x0a,0x6a
+
+# GFX12: v_mul_f16_e32 v5, -1, v2                ; encoding: [0xc1,0x04,0x0a,0x6a]
+0xc1,0x04,0x0a,0x6a
+
+# GFX12: v_mul_f16_e32 v5, 0.5, v2               ; encoding: [0xf0,0x04,0x0a,0x6a]
+0xf0,0x04,0x0a,0x6a
+
+# GFX12: v_mul_f16_e32 v5, src_scc, v2           ; encoding: [0xfd,0x04,0x0a,0x6a]
+0xfd,0x04,0x0a,0x6a
+
+# GFX12: v_mul_f16_e32 v127, 0xfe0b, v127        ; encoding: [0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_mul_f32_e32 v5, v1, v2                ; encoding: [0x01,0x05,0x0a,0x10]
+0x01,0x05,0x0a,0x10
+
+# GFX12: v_mul_f32_e32 v5, v255, v2              ; encoding: [0xff,0x05,0x0a,0x10]
+0xff,0x05,0x0a,0x10
+
+# GFX12: v_mul_f32_e32 v5, s1, v2                ; encoding: [0x01,0x04,0x0a,0x10]
+0x01,0x04,0x0a,0x10
+
+# GFX12: v_mul_f32_e32 v5, s105, v2              ; encoding: [0x69,0x04,0x0a,0x10]
+0x69,0x04,0x0a,0x10
+
+# GFX12: v_mul_f32_e32 v5, vcc_lo, v2            ; encoding: [0x6a,0x04,0x0a,0x10]
+0x6a,0x04,0x0a,0x10
+
+# GFX12: v_mul_f32_e32 v5, vcc_hi, v2            ; encoding: [0x6b,0x04,0x0a,0x10]
+0x6b,0x04,0x0a,0x10
+
+# GFX12: v_mul_f32_e32 v5, ttmp15, v2            ; encoding: [0x7b,0x04,0x0a,0x10]
+0x7b,0x04,0x0a,0x10
+
+# GFX12: v_mul_f32_e32 v5, m0, v2                ; encoding: [0x7d,0x04,0x0a,0x10]
+0x7d,0x04,0x0a,0x10
+
+# GFX12: v_mul_f32_e32 v5, exec_lo, v2           ; encoding: [0x7e,0x04,0x0a,0x10]
+0x7e,0x04,0x0a,0x10
+
+# GFX12: v_mul_f32_e32 v5, exec_hi, v2           ; encoding: [0x7f,0x04,0x0a,0x10]
+0x7f,0x04,0x0a,0x10
+
+# GFX12: v_mul_f32_e32 v5, null, v2              ; encoding: [0x7c,0x04,0x0a,0x10]
+0x7c,0x04,0x0a,0x10
+
+# GFX12: v_mul_f32_e32 v5, -1, v2                ; encoding: [0xc1,0x04,0x0a,0x10]
+0xc1,0x04,0x0a,0x10
+
+# GFX12: v_mul_f32_e32 v5, 0.5, v2               ; encoding: [0xf0,0x04,0x0a,0x10]
+0xf0,0x04,0x0a,0x10
+
+# GFX12: v_mul_f32_e32 v5, src_scc, v2           ; encoding: [0xfd,0x04,0x0a,0x10]
+0xfd,0x04,0x0a,0x10
+
+# GFX12: v_mul_f32_e32 v255, 0xaf123456, v255    ; encoding: [0xff,0xfe,0xff,0x11,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x11,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mul_f64_e32 v[5:6], v[1:2], v[3:4]    ; encoding: [0x01,0x07,0x0a,0x0c]
+0x01,0x07,0x0a,0x0c
+
+# GFX12: v_mul_f64_e32 v[5:6], v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x0a,0x0c]
+0xfe,0x05,0x0a,0x0c
+
+# GFX12: v_mul_f64_e32 v[5:6], s[0:1], v[2:3]    ; encoding: [0x00,0x04,0x0a,0x0c]
+0x00,0x04,0x0a,0x0c
+
+# GFX12: v_mul_f64_e32 v[5:6], s[104:105], v[2:3] ; encoding: [0x68,0x04,0x0a,0x0c]
+0x68,0x04,0x0a,0x0c
+
+# GFX12: v_mul_f64_e32 v[5:6], vcc, v[2:3]       ; encoding: [0x6a,0x04,0x0a,0x0c]
+0x6a,0x04,0x0a,0x0c
+
+# GFX12: v_mul_f64_e32 v[5:6], ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x0a,0x0c]
+0x7a,0x04,0x0a,0x0c
+
+# GFX12: v_mul_f64_e32 v[5:6], exec, v[2:3]      ; encoding: [0x7e,0x04,0x0a,0x0c]
+0x7e,0x04,0x0a,0x0c
+
+# GFX12: v_mul_f64_e32 v[5:6], null, v[2:3]      ; encoding: [0x7c,0x04,0x0a,0x0c]
+0x7c,0x04,0x0a,0x0c
+
+# GFX12: v_mul_f64_e32 v[5:6], -1, v[2:3]        ; encoding: [0xc1,0x04,0x0a,0x0c]
+0xc1,0x04,0x0a,0x0c
+
+# GFX12: v_mul_f64_e32 v[5:6], 0.5, v[2:3]       ; encoding: [0xf0,0x04,0x0a,0x0c]
+0xf0,0x04,0x0a,0x0c
+
+# GFX12: v_mul_f64_e32 v[5:6], src_scc, v[2:3]   ; encoding: [0xfd,0x04,0x0a,0x0c]
+0xfd,0x04,0x0a,0x0c
+
+# GFX12: v_mul_f64_e32 v[254:255], 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xfd,0x0d,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xfd,0x0d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mul_hi_i32_i24_e32 v5, v1, v2         ; encoding: [0x01,0x05,0x0a,0x14]
+0x01,0x05,0x0a,0x14
+
+# GFX12: v_mul_hi_i32_i24_e32 v5, v255, v2       ; encoding: [0xff,0x05,0x0a,0x14]
+0xff,0x05,0x0a,0x14
+
+# GFX12: v_mul_hi_i32_i24_e32 v5, s1, v2         ; encoding: [0x01,0x04,0x0a,0x14]
+0x01,0x04,0x0a,0x14
+
+# GFX12: v_mul_hi_i32_i24_e32 v5, s105, v2       ; encoding: [0x69,0x04,0x0a,0x14]
+0x69,0x04,0x0a,0x14
+
+# GFX12: v_mul_hi_i32_i24_e32 v5, vcc_lo, v2     ; encoding: [0x6a,0x04,0x0a,0x14]
+0x6a,0x04,0x0a,0x14
+
+# GFX12: v_mul_hi_i32_i24_e32 v5, vcc_hi, v2     ; encoding: [0x6b,0x04,0x0a,0x14]
+0x6b,0x04,0x0a,0x14
+
+# GFX12: v_mul_hi_i32_i24_e32 v5, ttmp15, v2     ; encoding: [0x7b,0x04,0x0a,0x14]
+0x7b,0x04,0x0a,0x14
+
+# GFX12: v_mul_hi_i32_i24_e32 v5, m0, v2         ; encoding: [0x7d,0x04,0x0a,0x14]
+0x7d,0x04,0x0a,0x14
+
+# GFX12: v_mul_hi_i32_i24_e32 v5, exec_lo, v2    ; encoding: [0x7e,0x04,0x0a,0x14]
+0x7e,0x04,0x0a,0x14
+
+# GFX12: v_mul_hi_i32_i24_e32 v5, exec_hi, v2    ; encoding: [0x7f,0x04,0x0a,0x14]
+0x7f,0x04,0x0a,0x14
+
+# GFX12: v_mul_hi_i32_i24_e32 v5, null, v2       ; encoding: [0x7c,0x04,0x0a,0x14]
+0x7c,0x04,0x0a,0x14
+
+# GFX12: v_mul_hi_i32_i24_e32 v5, -1, v2         ; encoding: [0xc1,0x04,0x0a,0x14]
+0xc1,0x04,0x0a,0x14
+
+# GFX12: v_mul_hi_i32_i24_e32 v5, 0.5, v2        ; encoding: [0xf0,0x04,0x0a,0x14]
+0xf0,0x04,0x0a,0x14
+
+# GFX12: v_mul_hi_i32_i24_e32 v5, src_scc, v2    ; encoding: [0xfd,0x04,0x0a,0x14]
+0xfd,0x04,0x0a,0x14
+
+# GFX12: v_mul_hi_i32_i24_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x15,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x15,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mul_hi_u32_u24_e32 v5, v1, v2         ; encoding: [0x01,0x05,0x0a,0x18]
+0x01,0x05,0x0a,0x18
+
+# GFX12: v_mul_hi_u32_u24_e32 v5, v255, v2       ; encoding: [0xff,0x05,0x0a,0x18]
+0xff,0x05,0x0a,0x18
+
+# GFX12: v_mul_hi_u32_u24_e32 v5, s1, v2         ; encoding: [0x01,0x04,0x0a,0x18]
+0x01,0x04,0x0a,0x18
+
+# GFX12: v_mul_hi_u32_u24_e32 v5, s105, v2       ; encoding: [0x69,0x04,0x0a,0x18]
+0x69,0x04,0x0a,0x18
+
+# GFX12: v_mul_hi_u32_u24_e32 v5, vcc_lo, v2     ; encoding: [0x6a,0x04,0x0a,0x18]
+0x6a,0x04,0x0a,0x18
+
+# GFX12: v_mul_hi_u32_u24_e32 v5, vcc_hi, v2     ; encoding: [0x6b,0x04,0x0a,0x18]
+0x6b,0x04,0x0a,0x18
+
+# GFX12: v_mul_hi_u32_u24_e32 v5, ttmp15, v2     ; encoding: [0x7b,0x04,0x0a,0x18]
+0x7b,0x04,0x0a,0x18
+
+# GFX12: v_mul_hi_u32_u24_e32 v5, m0, v2         ; encoding: [0x7d,0x04,0x0a,0x18]
+0x7d,0x04,0x0a,0x18
+
+# GFX12: v_mul_hi_u32_u24_e32 v5, exec_lo, v2    ; encoding: [0x7e,0x04,0x0a,0x18]
+0x7e,0x04,0x0a,0x18
+
+# GFX12: v_mul_hi_u32_u24_e32 v5, exec_hi, v2    ; encoding: [0x7f,0x04,0x0a,0x18]
+0x7f,0x04,0x0a,0x18
+
+# GFX12: v_mul_hi_u32_u24_e32 v5, null, v2       ; encoding: [0x7c,0x04,0x0a,0x18]
+0x7c,0x04,0x0a,0x18
+
+# GFX12: v_mul_hi_u32_u24_e32 v5, -1, v2         ; encoding: [0xc1,0x04,0x0a,0x18]
+0xc1,0x04,0x0a,0x18
+
+# GFX12: v_mul_hi_u32_u24_e32 v5, 0.5, v2        ; encoding: [0xf0,0x04,0x0a,0x18]
+0xf0,0x04,0x0a,0x18
+
+# GFX12: v_mul_hi_u32_u24_e32 v5, src_scc, v2    ; encoding: [0xfd,0x04,0x0a,0x18]
+0xfd,0x04,0x0a,0x18
+
+# GFX12: v_mul_hi_u32_u24_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x19,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x19,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mul_i32_i24_e32 v5, v1, v2            ; encoding: [0x01,0x05,0x0a,0x12]
+0x01,0x05,0x0a,0x12
+
+# GFX12: v_mul_i32_i24_e32 v5, v255, v2          ; encoding: [0xff,0x05,0x0a,0x12]
+0xff,0x05,0x0a,0x12
+
+# GFX12: v_mul_i32_i24_e32 v5, s1, v2            ; encoding: [0x01,0x04,0x0a,0x12]
+0x01,0x04,0x0a,0x12
+
+# GFX12: v_mul_i32_i24_e32 v5, s105, v2          ; encoding: [0x69,0x04,0x0a,0x12]
+0x69,0x04,0x0a,0x12
+
+# GFX12: v_mul_i32_i24_e32 v5, vcc_lo, v2        ; encoding: [0x6a,0x04,0x0a,0x12]
+0x6a,0x04,0x0a,0x12
+
+# GFX12: v_mul_i32_i24_e32 v5, vcc_hi, v2        ; encoding: [0x6b,0x04,0x0a,0x12]
+0x6b,0x04,0x0a,0x12
+
+# GFX12: v_mul_i32_i24_e32 v5, ttmp15, v2        ; encoding: [0x7b,0x04,0x0a,0x12]
+0x7b,0x04,0x0a,0x12
+
+# GFX12: v_mul_i32_i24_e32 v5, m0, v2            ; encoding: [0x7d,0x04,0x0a,0x12]
+0x7d,0x04,0x0a,0x12
+
+# GFX12: v_mul_i32_i24_e32 v5, exec_lo, v2       ; encoding: [0x7e,0x04,0x0a,0x12]
+0x7e,0x04,0x0a,0x12
+
+# GFX12: v_mul_i32_i24_e32 v5, exec_hi, v2       ; encoding: [0x7f,0x04,0x0a,0x12]
+0x7f,0x04,0x0a,0x12
+
+# GFX12: v_mul_i32_i24_e32 v5, null, v2          ; encoding: [0x7c,0x04,0x0a,0x12]
+0x7c,0x04,0x0a,0x12
+
+# GFX12: v_mul_i32_i24_e32 v5, -1, v2            ; encoding: [0xc1,0x04,0x0a,0x12]
+0xc1,0x04,0x0a,0x12
+
+# GFX12: v_mul_i32_i24_e32 v5, 0.5, v2           ; encoding: [0xf0,0x04,0x0a,0x12]
+0xf0,0x04,0x0a,0x12
+
+# GFX12: v_mul_i32_i24_e32 v5, src_scc, v2       ; encoding: [0xfd,0x04,0x0a,0x12]
+0xfd,0x04,0x0a,0x12
+
+# GFX12: v_mul_i32_i24_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x13,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x13,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mul_u32_u24_e32 v5, v1, v2            ; encoding: [0x01,0x05,0x0a,0x16]
+0x01,0x05,0x0a,0x16
+
+# GFX12: v_mul_u32_u24_e32 v5, v255, v2          ; encoding: [0xff,0x05,0x0a,0x16]
+0xff,0x05,0x0a,0x16
+
+# GFX12: v_mul_u32_u24_e32 v5, s1, v2            ; encoding: [0x01,0x04,0x0a,0x16]
+0x01,0x04,0x0a,0x16
+
+# GFX12: v_mul_u32_u24_e32 v5, s105, v2          ; encoding: [0x69,0x04,0x0a,0x16]
+0x69,0x04,0x0a,0x16
+
+# GFX12: v_mul_u32_u24_e32 v5, vcc_lo, v2        ; encoding: [0x6a,0x04,0x0a,0x16]
+0x6a,0x04,0x0a,0x16
+
+# GFX12: v_mul_u32_u24_e32 v5, vcc_hi, v2        ; encoding: [0x6b,0x04,0x0a,0x16]
+0x6b,0x04,0x0a,0x16
+
+# GFX12: v_mul_u32_u24_e32 v5, ttmp15, v2        ; encoding: [0x7b,0x04,0x0a,0x16]
+0x7b,0x04,0x0a,0x16
+
+# GFX12: v_mul_u32_u24_e32 v5, m0, v2            ; encoding: [0x7d,0x04,0x0a,0x16]
+0x7d,0x04,0x0a,0x16
+
+# GFX12: v_mul_u32_u24_e32 v5, exec_lo, v2       ; encoding: [0x7e,0x04,0x0a,0x16]
+0x7e,0x04,0x0a,0x16
+
+# GFX12: v_mul_u32_u24_e32 v5, exec_hi, v2       ; encoding: [0x7f,0x04,0x0a,0x16]
+0x7f,0x04,0x0a,0x16
+
+# GFX12: v_mul_u32_u24_e32 v5, null, v2          ; encoding: [0x7c,0x04,0x0a,0x16]
+0x7c,0x04,0x0a,0x16
+
+# GFX12: v_mul_u32_u24_e32 v5, -1, v2            ; encoding: [0xc1,0x04,0x0a,0x16]
+0xc1,0x04,0x0a,0x16
+
+# GFX12: v_mul_u32_u24_e32 v5, 0.5, v2           ; encoding: [0xf0,0x04,0x0a,0x16]
+0xf0,0x04,0x0a,0x16
+
+# GFX12: v_mul_u32_u24_e32 v5, src_scc, v2       ; encoding: [0xfd,0x04,0x0a,0x16]
+0xfd,0x04,0x0a,0x16
+
+# GFX12: v_mul_u32_u24_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x17,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x17,0x56,0x34,0x12,0xaf
+
+# GFX12: v_or_b32_e32 v5, v1, v2                 ; encoding: [0x01,0x05,0x0a,0x38]
+0x01,0x05,0x0a,0x38
+
+# GFX12: v_or_b32_e32 v5, v255, v2               ; encoding: [0xff,0x05,0x0a,0x38]
+0xff,0x05,0x0a,0x38
+
+# GFX12: v_or_b32_e32 v5, s1, v2                 ; encoding: [0x01,0x04,0x0a,0x38]
+0x01,0x04,0x0a,0x38
+
+# GFX12: v_or_b32_e32 v5, s105, v2               ; encoding: [0x69,0x04,0x0a,0x38]
+0x69,0x04,0x0a,0x38
+
+# GFX12: v_or_b32_e32 v5, vcc_lo, v2             ; encoding: [0x6a,0x04,0x0a,0x38]
+0x6a,0x04,0x0a,0x38
+
+# GFX12: v_or_b32_e32 v5, vcc_hi, v2             ; encoding: [0x6b,0x04,0x0a,0x38]
+0x6b,0x04,0x0a,0x38
+
+# GFX12: v_or_b32_e32 v5, ttmp15, v2             ; encoding: [0x7b,0x04,0x0a,0x38]
+0x7b,0x04,0x0a,0x38
+
+# GFX12: v_or_b32_e32 v5, m0, v2                 ; encoding: [0x7d,0x04,0x0a,0x38]
+0x7d,0x04,0x0a,0x38
+
+# GFX12: v_or_b32_e32 v5, exec_lo, v2            ; encoding: [0x7e,0x04,0x0a,0x38]
+0x7e,0x04,0x0a,0x38
+
+# GFX12: v_or_b32_e32 v5, exec_hi, v2            ; encoding: [0x7f,0x04,0x0a,0x38]
+0x7f,0x04,0x0a,0x38
+
+# GFX12: v_or_b32_e32 v5, null, v2               ; encoding: [0x7c,0x04,0x0a,0x38]
+0x7c,0x04,0x0a,0x38
+
+# GFX12: v_or_b32_e32 v5, -1, v2                 ; encoding: [0xc1,0x04,0x0a,0x38]
+0xc1,0x04,0x0a,0x38
+
+# GFX12: v_or_b32_e32 v5, 0.5, v2                ; encoding: [0xf0,0x04,0x0a,0x38]
+0xf0,0x04,0x0a,0x38
+
+# GFX12: v_or_b32_e32 v5, src_scc, v2            ; encoding: [0xfd,0x04,0x0a,0x38]
+0xfd,0x04,0x0a,0x38
+
+# GFX12: v_or_b32_e32 v255, 0xaf123456, v255     ; encoding: [0xff,0xfe,0xff,0x39,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x39,0x56,0x34,0x12,0xaf
+
+# GFX12: v_pk_fmac_f16 v5, v1, v2                ; encoding: [0x01,0x05,0x0a,0x78]
+0x01,0x05,0x0a,0x78
+
+# GFX12: v_pk_fmac_f16 v5, v255, v2              ; encoding: [0xff,0x05,0x0a,0x78]
+0xff,0x05,0x0a,0x78
+
+# GFX12: v_pk_fmac_f16 v5, s1, v2                ; encoding: [0x01,0x04,0x0a,0x78]
+0x01,0x04,0x0a,0x78
+
+# GFX12: v_pk_fmac_f16 v5, s105, v2              ; encoding: [0x69,0x04,0x0a,0x78]
+0x69,0x04,0x0a,0x78
+
+# GFX12: v_pk_fmac_f16 v5, vcc_lo, v2            ; encoding: [0x6a,0x04,0x0a,0x78]
+0x6a,0x04,0x0a,0x78
+
+# GFX12: v_pk_fmac_f16 v5, vcc_hi, v2            ; encoding: [0x6b,0x04,0x0a,0x78]
+0x6b,0x04,0x0a,0x78
+
+# GFX12: v_pk_fmac_f16 v5, ttmp15, v2            ; encoding: [0x7b,0x04,0x0a,0x78]
+0x7b,0x04,0x0a,0x78
+
+# GFX12: v_pk_fmac_f16 v5, m0, v2                ; encoding: [0x7d,0x04,0x0a,0x78]
+0x7d,0x04,0x0a,0x78
+
+# GFX12: v_pk_fmac_f16 v5, exec_lo, v2           ; encoding: [0x7e,0x04,0x0a,0x78]
+0x7e,0x04,0x0a,0x78
+
+# GFX12: v_pk_fmac_f16 v5, exec_hi, v2           ; encoding: [0x7f,0x04,0x0a,0x78]
+0x7f,0x04,0x0a,0x78
+
+# GFX12: v_pk_fmac_f16 v5, null, v2              ; encoding: [0x7c,0x04,0x0a,0x78]
+0x7c,0x04,0x0a,0x78
+
+# GFX12: v_pk_fmac_f16 v5, -1, v2                ; encoding: [0xc1,0x04,0x0a,0x78]
+0xc1,0x04,0x0a,0x78
+
+# GFX12: v_pk_fmac_f16 v5, 0.5, v2               ; encoding: [0xf0,0x04,0x0a,0x78]
+0xf0,0x04,0x0a,0x78
+
+# GFX12: v_pk_fmac_f16 v5, src_scc, v2           ; encoding: [0xfd,0x04,0x0a,0x78]
+0xfd,0x04,0x0a,0x78
+
+# GFX12: v_pk_fmac_f16 v255, 0xfe0b, v255        ; encoding: [0xff,0xfe,0xff,0x79,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0xff,0x79,0x0b,0xfe,0x00,0x00
+
+# W32: v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v2, vcc_lo ; encoding: [0x01,0x05,0x0a,0x42]
+# W64: v_sub_co_ci_u32_e32 v5, vcc, v1, v2, vcc ; encoding: [0x01,0x05,0x0a,0x42]
+0x01,0x05,0x0a,0x42
+
+# W32: v_sub_co_ci_u32_e32 v5, vcc_lo, v255, v2, vcc_lo ; encoding: [0xff,0x05,0x0a,0x42]
+# W64: v_sub_co_ci_u32_e32 v5, vcc, v255, v2, vcc ; encoding: [0xff,0x05,0x0a,0x42]
+0xff,0x05,0x0a,0x42
+
+# W32: v_sub_co_ci_u32_e32 v5, vcc_lo, s1, v2, vcc_lo ; encoding: [0x01,0x04,0x0a,0x42]
+# W64: v_sub_co_ci_u32_e32 v5, vcc, s1, v2, vcc ; encoding: [0x01,0x04,0x0a,0x42]
+0x01,0x04,0x0a,0x42
+
+# W32: v_sub_co_ci_u32_e32 v5, vcc_lo, s105, v2, vcc_lo ; encoding: [0x69,0x04,0x0a,0x42]
+# W64: v_sub_co_ci_u32_e32 v5, vcc, s105, v2, vcc ; encoding: [0x69,0x04,0x0a,0x42]
+0x69,0x04,0x0a,0x42
+
+# W32: v_sub_co_ci_u32_e32 v5, vcc_lo, vcc_lo, v2, vcc_lo ; encoding: [0x6a,0x04,0x0a,0x42]
+# W64: v_sub_co_ci_u32_e32 v5, vcc, vcc_lo, v2, vcc ; encoding: [0x6a,0x04,0x0a,0x42]
+0x6a,0x04,0x0a,0x42
+
+# W32: v_sub_co_ci_u32_e32 v5, vcc_lo, vcc_hi, v2, vcc_lo ; encoding: [0x6b,0x04,0x0a,0x42]
+# W64: v_sub_co_ci_u32_e32 v5, vcc, vcc_hi, v2, vcc ; encoding: [0x6b,0x04,0x0a,0x42]
+0x6b,0x04,0x0a,0x42
+
+# W32: v_sub_co_ci_u32_e32 v5, vcc_lo, ttmp15, v2, vcc_lo ; encoding: [0x7b,0x04,0x0a,0x42]
+# W64: v_sub_co_ci_u32_e32 v5, vcc, ttmp15, v2, vcc ; encoding: [0x7b,0x04,0x0a,0x42]
+0x7b,0x04,0x0a,0x42
+
+# W32: v_sub_co_ci_u32_e32 v5, vcc_lo, m0, v2, vcc_lo ; encoding: [0x7d,0x04,0x0a,0x42]
+# W64: v_sub_co_ci_u32_e32 v5, vcc, m0, v2, vcc ; encoding: [0x7d,0x04,0x0a,0x42]
+0x7d,0x04,0x0a,0x42
+
+# W32: v_sub_co_ci_u32_e32 v5, vcc_lo, exec_lo, v2, vcc_lo ; encoding: [0x7e,0x04,0x0a,0x42]
+# W64: v_sub_co_ci_u32_e32 v5, vcc, exec_lo, v2, vcc ; encoding: [0x7e,0x04,0x0a,0x42]
+0x7e,0x04,0x0a,0x42
+
+# W32: v_sub_co_ci_u32_e32 v5, vcc_lo, exec_hi, v2, vcc_lo ; encoding: [0x7f,0x04,0x0a,0x42]
+# W64: v_sub_co_ci_u32_e32 v5, vcc, exec_hi, v2, vcc ; encoding: [0x7f,0x04,0x0a,0x42]
+0x7f,0x04,0x0a,0x42
+
+# W32: v_sub_co_ci_u32_e32 v5, vcc_lo, null, v2, vcc_lo ; encoding: [0x7c,0x04,0x0a,0x42]
+# W64: v_sub_co_ci_u32_e32 v5, vcc, null, v2, vcc ; encoding: [0x7c,0x04,0x0a,0x42]
+0x7c,0x04,0x0a,0x42
+
+# W32: v_sub_co_ci_u32_e32 v5, vcc_lo, -1, v2, vcc_lo ; encoding: [0xc1,0x04,0x0a,0x42]
+# W64: v_sub_co_ci_u32_e32 v5, vcc, -1, v2, vcc ; encoding: [0xc1,0x04,0x0a,0x42]
+0xc1,0x04,0x0a,0x42
+
+# W32: v_sub_co_ci_u32_e32 v5, vcc_lo, 0.5, v2, vcc_lo ; encoding: [0xf0,0x04,0x0a,0x42]
+# W64: v_sub_co_ci_u32_e32 v5, vcc, 0.5, v2, vcc ; encoding: [0xf0,0x04,0x0a,0x42]
+0xf0,0x04,0x0a,0x42
+
+# W32: v_sub_co_ci_u32_e32 v5, vcc_lo, src_scc, v2, vcc_lo ; encoding: [0xfd,0x04,0x0a,0x42]
+# W64: v_sub_co_ci_u32_e32 v5, vcc, src_scc, v2, vcc ; encoding: [0xfd,0x04,0x0a,0x42]
+0xfd,0x04,0x0a,0x42
+
+# W32: v_sub_co_ci_u32_e32 v255, vcc_lo, 0xaf123456, v255, vcc_lo ; encoding: [0xff,0xfe,0xff,0x43,0x56,0x34,0x12,0xaf]
+# W64: v_sub_co_ci_u32_e32 v255, vcc, 0xaf123456, v255, vcc ; encoding: [0xff,0xfe,0xff,0x43,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x43,0x56,0x34,0x12,0xaf
+
+# GFX12: v_sub_f16_e32 v5, v1, v2                ; encoding: [0x01,0x05,0x0a,0x66]
+0x01,0x05,0x0a,0x66
+
+# GFX12: v_sub_f16_e32 v5, v127, v2              ; encoding: [0x7f,0x05,0x0a,0x66]
+0x7f,0x05,0x0a,0x66
+
+# GFX12: v_sub_f16_e32 v5, s1, v2                ; encoding: [0x01,0x04,0x0a,0x66]
+0x01,0x04,0x0a,0x66
+
+# GFX12: v_sub_f16_e32 v5, s105, v2              ; encoding: [0x69,0x04,0x0a,0x66]
+0x69,0x04,0x0a,0x66
+
+# GFX12: v_sub_f16_e32 v5, vcc_lo, v2            ; encoding: [0x6a,0x04,0x0a,0x66]
+0x6a,0x04,0x0a,0x66
+
+# GFX12: v_sub_f16_e32 v5, vcc_hi, v2            ; encoding: [0x6b,0x04,0x0a,0x66]
+0x6b,0x04,0x0a,0x66
+
+# GFX12: v_sub_f16_e32 v5, ttmp15, v2            ; encoding: [0x7b,0x04,0x0a,0x66]
+0x7b,0x04,0x0a,0x66
+
+# GFX12: v_sub_f16_e32 v5, m0, v2                ; encoding: [0x7d,0x04,0x0a,0x66]
+0x7d,0x04,0x0a,0x66
+
+# GFX12: v_sub_f16_e32 v5, exec_lo, v2           ; encoding: [0x7e,0x04,0x0a,0x66]
+0x7e,0x04,0x0a,0x66
+
+# GFX12: v_sub_f16_e32 v5, exec_hi, v2           ; encoding: [0x7f,0x04,0x0a,0x66]
+0x7f,0x04,0x0a,0x66
+
+# GFX12: v_sub_f16_e32 v5, null, v2              ; encoding: [0x7c,0x04,0x0a,0x66]
+0x7c,0x04,0x0a,0x66
+
+# GFX12: v_sub_f16_e32 v5, -1, v2                ; encoding: [0xc1,0x04,0x0a,0x66]
+0xc1,0x04,0x0a,0x66
+
+# GFX12: v_sub_f16_e32 v5, 0.5, v2               ; encoding: [0xf0,0x04,0x0a,0x66]
+0xf0,0x04,0x0a,0x66
+
+# GFX12: v_sub_f16_e32 v5, src_scc, v2           ; encoding: [0xfd,0x04,0x0a,0x66]
+0xfd,0x04,0x0a,0x66
+
+# GFX12: v_sub_f16_e32 v127, 0xfe0b, v127        ; encoding: [0xff,0xfe,0xfe,0x66,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0xfe,0x66,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_sub_f32_e32 v5, v1, v2                ; encoding: [0x01,0x05,0x0a,0x08]
+0x01,0x05,0x0a,0x08
+
+# GFX12: v_sub_f32_e32 v5, v255, v2              ; encoding: [0xff,0x05,0x0a,0x08]
+0xff,0x05,0x0a,0x08
+
+# GFX12: v_sub_f32_e32 v5, s1, v2                ; encoding: [0x01,0x04,0x0a,0x08]
+0x01,0x04,0x0a,0x08
+
+# GFX12: v_sub_f32_e32 v5, s105, v2              ; encoding: [0x69,0x04,0x0a,0x08]
+0x69,0x04,0x0a,0x08
+
+# GFX12: v_sub_f32_e32 v5, vcc_lo, v2            ; encoding: [0x6a,0x04,0x0a,0x08]
+0x6a,0x04,0x0a,0x08
+
+# GFX12: v_sub_f32_e32 v5, vcc_hi, v2            ; encoding: [0x6b,0x04,0x0a,0x08]
+0x6b,0x04,0x0a,0x08
+
+# GFX12: v_sub_f32_e32 v5, ttmp15, v2            ; encoding: [0x7b,0x04,0x0a,0x08]
+0x7b,0x04,0x0a,0x08
+
+# GFX12: v_sub_f32_e32 v5, m0, v2                ; encoding: [0x7d,0x04,0x0a,0x08]
+0x7d,0x04,0x0a,0x08
+
+# GFX12: v_sub_f32_e32 v5, exec_lo, v2           ; encoding: [0x7e,0x04,0x0a,0x08]
+0x7e,0x04,0x0a,0x08
+
+# GFX12: v_sub_f32_e32 v5, exec_hi, v2           ; encoding: [0x7f,0x04,0x0a,0x08]
+0x7f,0x04,0x0a,0x08
+
+# GFX12: v_sub_f32_e32 v5, null, v2              ; encoding: [0x7c,0x04,0x0a,0x08]
+0x7c,0x04,0x0a,0x08
+
+# GFX12: v_sub_f32_e32 v5, -1, v2                ; encoding: [0xc1,0x04,0x0a,0x08]
+0xc1,0x04,0x0a,0x08
+
+# GFX12: v_sub_f32_e32 v5, 0.5, v2               ; encoding: [0xf0,0x04,0x0a,0x08]
+0xf0,0x04,0x0a,0x08
+
+# GFX12: v_sub_f32_e32 v5, src_scc, v2           ; encoding: [0xfd,0x04,0x0a,0x08]
+0xfd,0x04,0x0a,0x08
+
+# GFX12: v_sub_f32_e32 v255, 0xaf123456, v255    ; encoding: [0xff,0xfe,0xff,0x09,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x09,0x56,0x34,0x12,0xaf
+
+# GFX12: v_sub_nc_u32_e32 v5, v1, v2             ; encoding: [0x01,0x05,0x0a,0x4c]
+0x01,0x05,0x0a,0x4c
+
+# GFX12: v_sub_nc_u32_e32 v5, v255, v2           ; encoding: [0xff,0x05,0x0a,0x4c]
+0xff,0x05,0x0a,0x4c
+
+# GFX12: v_sub_nc_u32_e32 v5, s1, v2             ; encoding: [0x01,0x04,0x0a,0x4c]
+0x01,0x04,0x0a,0x4c
+
+# GFX12: v_sub_nc_u32_e32 v5, s105, v2           ; encoding: [0x69,0x04,0x0a,0x4c]
+0x69,0x04,0x0a,0x4c
+
+# GFX12: v_sub_nc_u32_e32 v5, vcc_lo, v2         ; encoding: [0x6a,0x04,0x0a,0x4c]
+0x6a,0x04,0x0a,0x4c
+
+# GFX12: v_sub_nc_u32_e32 v5, vcc_hi, v2         ; encoding: [0x6b,0x04,0x0a,0x4c]
+0x6b,0x04,0x0a,0x4c
+
+# GFX12: v_sub_nc_u32_e32 v5, ttmp15, v2         ; encoding: [0x7b,0x04,0x0a,0x4c]
+0x7b,0x04,0x0a,0x4c
+
+# GFX12: v_sub_nc_u32_e32 v5, m0, v2             ; encoding: [0x7d,0x04,0x0a,0x4c]
+0x7d,0x04,0x0a,0x4c
+
+# GFX12: v_sub_nc_u32_e32 v5, exec_lo, v2        ; encoding: [0x7e,0x04,0x0a,0x4c]
+0x7e,0x04,0x0a,0x4c
+
+# GFX12: v_sub_nc_u32_e32 v5, exec_hi, v2        ; encoding: [0x7f,0x04,0x0a,0x4c]
+0x7f,0x04,0x0a,0x4c
+
+# GFX12: v_sub_nc_u32_e32 v5, null, v2           ; encoding: [0x7c,0x04,0x0a,0x4c]
+0x7c,0x04,0x0a,0x4c
+
+# GFX12: v_sub_nc_u32_e32 v5, -1, v2             ; encoding: [0xc1,0x04,0x0a,0x4c]
+0xc1,0x04,0x0a,0x4c
+
+# GFX12: v_sub_nc_u32_e32 v5, 0.5, v2            ; encoding: [0xf0,0x04,0x0a,0x4c]
+0xf0,0x04,0x0a,0x4c
+
+# GFX12: v_sub_nc_u32_e32 v5, src_scc, v2        ; encoding: [0xfd,0x04,0x0a,0x4c]
+0xfd,0x04,0x0a,0x4c
+
+# GFX12: v_sub_nc_u32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x4d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x4d,0x56,0x34,0x12,0xaf
+
+# W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, v1, v2, vcc_lo ; encoding: [0x01,0x05,0x0a,0x44]
+# W64: v_subrev_co_ci_u32_e32 v5, vcc, v1, v2, vcc ; encoding: [0x01,0x05,0x0a,0x44]
+0x01,0x05,0x0a,0x44
+
+# W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, v255, v2, vcc_lo ; encoding: [0xff,0x05,0x0a,0x44]
+# W64: v_subrev_co_ci_u32_e32 v5, vcc, v255, v2, vcc ; encoding: [0xff,0x05,0x0a,0x44]
+0xff,0x05,0x0a,0x44
+
+# W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, s1, v2, vcc_lo ; encoding: [0x01,0x04,0x0a,0x44]
+# W64: v_subrev_co_ci_u32_e32 v5, vcc, s1, v2, vcc ; encoding: [0x01,0x04,0x0a,0x44]
+0x01,0x04,0x0a,0x44
+
+# W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, s105, v2, vcc_lo ; encoding: [0x69,0x04,0x0a,0x44]
+# W64: v_subrev_co_ci_u32_e32 v5, vcc, s105, v2, vcc ; encoding: [0x69,0x04,0x0a,0x44]
+0x69,0x04,0x0a,0x44
+
+# W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, vcc_lo, v2, vcc_lo ; encoding: [0x6a,0x04,0x0a,0x44]
+# W64: v_subrev_co_ci_u32_e32 v5, vcc, vcc_lo, v2, vcc ; encoding: [0x6a,0x04,0x0a,0x44]
+0x6a,0x04,0x0a,0x44
+
+# W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, vcc_hi, v2, vcc_lo ; encoding: [0x6b,0x04,0x0a,0x44]
+# W64: v_subrev_co_ci_u32_e32 v5, vcc, vcc_hi, v2, vcc ; encoding: [0x6b,0x04,0x0a,0x44]
+0x6b,0x04,0x0a,0x44
+
+# W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, ttmp15, v2, vcc_lo ; encoding: [0x7b,0x04,0x0a,0x44]
+# W64: v_subrev_co_ci_u32_e32 v5, vcc, ttmp15, v2, vcc ; encoding: [0x7b,0x04,0x0a,0x44]
+0x7b,0x04,0x0a,0x44
+
+# W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, m0, v2, vcc_lo ; encoding: [0x7d,0x04,0x0a,0x44]
+# W64: v_subrev_co_ci_u32_e32 v5, vcc, m0, v2, vcc ; encoding: [0x7d,0x04,0x0a,0x44]
+0x7d,0x04,0x0a,0x44
+
+# W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, exec_lo, v2, vcc_lo ; encoding: [0x7e,0x04,0x0a,0x44]
+# W64: v_subrev_co_ci_u32_e32 v5, vcc, exec_lo, v2, vcc ; encoding: [0x7e,0x04,0x0a,0x44]
+0x7e,0x04,0x0a,0x44
+
+# W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, exec_hi, v2, vcc_lo ; encoding: [0x7f,0x04,0x0a,0x44]
+# W64: v_subrev_co_ci_u32_e32 v5, vcc, exec_hi, v2, vcc ; encoding: [0x7f,0x04,0x0a,0x44]
+0x7f,0x04,0x0a,0x44
+
+# W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, null, v2, vcc_lo ; encoding: [0x7c,0x04,0x0a,0x44]
+# W64: v_subrev_co_ci_u32_e32 v5, vcc, null, v2, vcc ; encoding: [0x7c,0x04,0x0a,0x44]
+0x7c,0x04,0x0a,0x44
+
+# W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, -1, v2, vcc_lo ; encoding: [0xc1,0x04,0x0a,0x44]
+# W64: v_subrev_co_ci_u32_e32 v5, vcc, -1, v2, vcc ; encoding: [0xc1,0x04,0x0a,0x44]
+0xc1,0x04,0x0a,0x44
+
+# W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, 0.5, v2, vcc_lo ; encoding: [0xf0,0x04,0x0a,0x44]
+# W64: v_subrev_co_ci_u32_e32 v5, vcc, 0.5, v2, vcc ; encoding: [0xf0,0x04,0x0a,0x44]
+0xf0,0x04,0x0a,0x44
+
+# W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, src_scc, v2, vcc_lo ; encoding: [0xfd,0x04,0x0a,0x44]
+# W64: v_subrev_co_ci_u32_e32 v5, vcc, src_scc, v2, vcc ; encoding: [0xfd,0x04,0x0a,0x44]
+0xfd,0x04,0x0a,0x44
+
+# W32: v_subrev_co_ci_u32_e32 v255, vcc_lo, 0xaf123456, v255, vcc_lo ; encoding: [0xff,0xfe,0xff,0x45,0x56,0x34,0x12,0xaf]
+# W64: v_subrev_co_ci_u32_e32 v255, vcc, 0xaf123456, v255, vcc ; encoding: [0xff,0xfe,0xff,0x45,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x45,0x56,0x34,0x12,0xaf
+
+# GFX12: v_subrev_f16_e32 v5, v1, v2             ; encoding: [0x01,0x05,0x0a,0x68]
+0x01,0x05,0x0a,0x68
+
+# GFX12: v_subrev_f16_e32 v5, v127, v2           ; encoding: [0x7f,0x05,0x0a,0x68]
+0x7f,0x05,0x0a,0x68
+
+# GFX12: v_subrev_f16_e32 v5, s1, v2             ; encoding: [0x01,0x04,0x0a,0x68]
+0x01,0x04,0x0a,0x68
+
+# GFX12: v_subrev_f16_e32 v5, s105, v2           ; encoding: [0x69,0x04,0x0a,0x68]
+0x69,0x04,0x0a,0x68
+
+# GFX12: v_subrev_f16_e32 v5, vcc_lo, v2         ; encoding: [0x6a,0x04,0x0a,0x68]
+0x6a,0x04,0x0a,0x68
+
+# GFX12: v_subrev_f16_e32 v5, vcc_hi, v2         ; encoding: [0x6b,0x04,0x0a,0x68]
+0x6b,0x04,0x0a,0x68
+
+# GFX12: v_subrev_f16_e32 v5, ttmp15, v2         ; encoding: [0x7b,0x04,0x0a,0x68]
+0x7b,0x04,0x0a,0x68
+
+# GFX12: v_subrev_f16_e32 v5, m0, v2             ; encoding: [0x7d,0x04,0x0a,0x68]
+0x7d,0x04,0x0a,0x68
+
+# GFX12: v_subrev_f16_e32 v5, exec_lo, v2        ; encoding: [0x7e,0x04,0x0a,0x68]
+0x7e,0x04,0x0a,0x68
+
+# GFX12: v_subrev_f16_e32 v5, exec_hi, v2        ; encoding: [0x7f,0x04,0x0a,0x68]
+0x7f,0x04,0x0a,0x68
+
+# GFX12: v_subrev_f16_e32 v5, null, v2           ; encoding: [0x7c,0x04,0x0a,0x68]
+0x7c,0x04,0x0a,0x68
+
+# GFX12: v_subrev_f16_e32 v5, -1, v2             ; encoding: [0xc1,0x04,0x0a,0x68]
+0xc1,0x04,0x0a,0x68
+
+# GFX12: v_subrev_f16_e32 v5, 0.5, v2            ; encoding: [0xf0,0x04,0x0a,0x68]
+0xf0,0x04,0x0a,0x68
+
+# GFX12: v_subrev_f16_e32 v5, src_scc, v2        ; encoding: [0xfd,0x04,0x0a,0x68]
+0xfd,0x04,0x0a,0x68
+
+# GFX12: v_subrev_f16_e32 v127, 0xfe0b, v127     ; encoding: [0xff,0xfe,0xfe,0x68,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0xfe,0x68,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_subrev_f32_e32 v5, v1, v2             ; encoding: [0x01,0x05,0x0a,0x0a]
+0x01,0x05,0x0a,0x0a
+
+# GFX12: v_subrev_f32_e32 v5, v255, v2           ; encoding: [0xff,0x05,0x0a,0x0a]
+0xff,0x05,0x0a,0x0a
+
+# GFX12: v_subrev_f32_e32 v5, s1, v2             ; encoding: [0x01,0x04,0x0a,0x0a]
+0x01,0x04,0x0a,0x0a
+
+# GFX12: v_subrev_f32_e32 v5, s105, v2           ; encoding: [0x69,0x04,0x0a,0x0a]
+0x69,0x04,0x0a,0x0a
+
+# GFX12: v_subrev_f32_e32 v5, vcc_lo, v2         ; encoding: [0x6a,0x04,0x0a,0x0a]
+0x6a,0x04,0x0a,0x0a
+
+# GFX12: v_subrev_f32_e32 v5, vcc_hi, v2         ; encoding: [0x6b,0x04,0x0a,0x0a]
+0x6b,0x04,0x0a,0x0a
+
+# GFX12: v_subrev_f32_e32 v5, ttmp15, v2         ; encoding: [0x7b,0x04,0x0a,0x0a]
+0x7b,0x04,0x0a,0x0a
+
+# GFX12: v_subrev_f32_e32 v5, m0, v2             ; encoding: [0x7d,0x04,0x0a,0x0a]
+0x7d,0x04,0x0a,0x0a
+
+# GFX12: v_subrev_f32_e32 v5, exec_lo, v2        ; encoding: [0x7e,0x04,0x0a,0x0a]
+0x7e,0x04,0x0a,0x0a
+
+# GFX12: v_subrev_f32_e32 v5, exec_hi, v2        ; encoding: [0x7f,0x04,0x0a,0x0a]
+0x7f,0x04,0x0a,0x0a
+
+# GFX12: v_subrev_f32_e32 v5, null, v2           ; encoding: [0x7c,0x04,0x0a,0x0a]
+0x7c,0x04,0x0a,0x0a
+
+# GFX12: v_subrev_f32_e32 v5, -1, v2             ; encoding: [0xc1,0x04,0x0a,0x0a]
+0xc1,0x04,0x0a,0x0a
+
+# GFX12: v_subrev_f32_e32 v5, 0.5, v2            ; encoding: [0xf0,0x04,0x0a,0x0a]
+0xf0,0x04,0x0a,0x0a
+
+# GFX12: v_subrev_f32_e32 v5, src_scc, v2        ; encoding: [0xfd,0x04,0x0a,0x0a]
+0xfd,0x04,0x0a,0x0a
+
+# GFX12: v_subrev_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x0b,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x0b,0x56,0x34,0x12,0xaf
+
+# GFX12: v_subrev_nc_u32_e32 v5, v1, v2          ; encoding: [0x01,0x05,0x0a,0x4e]
+0x01,0x05,0x0a,0x4e
+
+# GFX12: v_subrev_nc_u32_e32 v5, v255, v2        ; encoding: [0xff,0x05,0x0a,0x4e]
+0xff,0x05,0x0a,0x4e
+
+# GFX12: v_subrev_nc_u32_e32 v5, s1, v2          ; encoding: [0x01,0x04,0x0a,0x4e]
+0x01,0x04,0x0a,0x4e
+
+# GFX12: v_subrev_nc_u32_e32 v5, s105, v2        ; encoding: [0x69,0x04,0x0a,0x4e]
+0x69,0x04,0x0a,0x4e
+
+# GFX12: v_subrev_nc_u32_e32 v5, vcc_lo, v2      ; encoding: [0x6a,0x04,0x0a,0x4e]
+0x6a,0x04,0x0a,0x4e
+
+# GFX12: v_subrev_nc_u32_e32 v5, vcc_hi, v2      ; encoding: [0x6b,0x04,0x0a,0x4e]
+0x6b,0x04,0x0a,0x4e
+
+# GFX12: v_subrev_nc_u32_e32 v5, ttmp15, v2      ; encoding: [0x7b,0x04,0x0a,0x4e]
+0x7b,0x04,0x0a,0x4e
+
+# GFX12: v_subrev_nc_u32_e32 v5, m0, v2          ; encoding: [0x7d,0x04,0x0a,0x4e]
+0x7d,0x04,0x0a,0x4e
+
+# GFX12: v_subrev_nc_u32_e32 v5, exec_lo, v2     ; encoding: [0x7e,0x04,0x0a,0x4e]
+0x7e,0x04,0x0a,0x4e
+
+# GFX12: v_subrev_nc_u32_e32 v5, exec_hi, v2     ; encoding: [0x7f,0x04,0x0a,0x4e]
+0x7f,0x04,0x0a,0x4e
+
+# GFX12: v_subrev_nc_u32_e32 v5, null, v2        ; encoding: [0x7c,0x04,0x0a,0x4e]
+0x7c,0x04,0x0a,0x4e
+
+# GFX12: v_subrev_nc_u32_e32 v5, -1, v2          ; encoding: [0xc1,0x04,0x0a,0x4e]
+0xc1,0x04,0x0a,0x4e
+
+# GFX12: v_subrev_nc_u32_e32 v5, 0.5, v2         ; encoding: [0xf0,0x04,0x0a,0x4e]
+0xf0,0x04,0x0a,0x4e
+
+# GFX12: v_subrev_nc_u32_e32 v5, src_scc, v2     ; encoding: [0xfd,0x04,0x0a,0x4e]
+0xfd,0x04,0x0a,0x4e
+
+# GFX12: v_subrev_nc_u32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x4f,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x4f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_xnor_b32_e32 v5, v1, v2               ; encoding: [0x01,0x05,0x0a,0x3c]
+0x01,0x05,0x0a,0x3c
+
+# GFX12: v_xnor_b32_e32 v5, v255, v2             ; encoding: [0xff,0x05,0x0a,0x3c]
+0xff,0x05,0x0a,0x3c
+
+# GFX12: v_xnor_b32_e32 v5, s1, v2               ; encoding: [0x01,0x04,0x0a,0x3c]
+0x01,0x04,0x0a,0x3c
+
+# GFX12: v_xnor_b32_e32 v5, s105, v2             ; encoding: [0x69,0x04,0x0a,0x3c]
+0x69,0x04,0x0a,0x3c
+
+# GFX12: v_xnor_b32_e32 v5, vcc_lo, v2           ; encoding: [0x6a,0x04,0x0a,0x3c]
+0x6a,0x04,0x0a,0x3c
+
+# GFX12: v_xnor_b32_e32 v5, vcc_hi, v2           ; encoding: [0x6b,0x04,0x0a,0x3c]
+0x6b,0x04,0x0a,0x3c
+
+# GFX12: v_xnor_b32_e32 v5, ttmp15, v2           ; encoding: [0x7b,0x04,0x0a,0x3c]
+0x7b,0x04,0x0a,0x3c
+
+# GFX12: v_xnor_b32_e32 v5, m0, v2               ; encoding: [0x7d,0x04,0x0a,0x3c]
+0x7d,0x04,0x0a,0x3c
+
+# GFX12: v_xnor_b32_e32 v5, exec_lo, v2          ; encoding: [0x7e,0x04,0x0a,0x3c]
+0x7e,0x04,0x0a,0x3c
+
+# GFX12: v_xnor_b32_e32 v5, exec_hi, v2          ; encoding: [0x7f,0x04,0x0a,0x3c]
+0x7f,0x04,0x0a,0x3c
+
+# GFX12: v_xnor_b32_e32 v5, null, v2             ; encoding: [0x7c,0x04,0x0a,0x3c]
+0x7c,0x04,0x0a,0x3c
+
+# GFX12: v_xnor_b32_e32 v5, -1, v2               ; encoding: [0xc1,0x04,0x0a,0x3c]
+0xc1,0x04,0x0a,0x3c
+
+# GFX12: v_xnor_b32_e32 v5, 0.5, v2              ; encoding: [0xf0,0x04,0x0a,0x3c]
+0xf0,0x04,0x0a,0x3c
+
+# GFX12: v_xnor_b32_e32 v5, src_scc, v2          ; encoding: [0xfd,0x04,0x0a,0x3c]
+0xfd,0x04,0x0a,0x3c
+
+# GFX12: v_xnor_b32_e32 v255, 0xaf123456, v255   ; encoding: [0xff,0xfe,0xff,0x3d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x3d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_xor_b32_e32 v5, v1, v2                ; encoding: [0x01,0x05,0x0a,0x3a]
+0x01,0x05,0x0a,0x3a
+
+# GFX12: v_xor_b32_e32 v5, v255, v2              ; encoding: [0xff,0x05,0x0a,0x3a]
+0xff,0x05,0x0a,0x3a
+
+# GFX12: v_xor_b32_e32 v5, s1, v2                ; encoding: [0x01,0x04,0x0a,0x3a]
+0x01,0x04,0x0a,0x3a
+
+# GFX12: v_xor_b32_e32 v5, s105, v2              ; encoding: [0x69,0x04,0x0a,0x3a]
+0x69,0x04,0x0a,0x3a
+
+# GFX12: v_xor_b32_e32 v5, vcc_lo, v2            ; encoding: [0x6a,0x04,0x0a,0x3a]
+0x6a,0x04,0x0a,0x3a
+
+# GFX12: v_xor_b32_e32 v5, vcc_hi, v2            ; encoding: [0x6b,0x04,0x0a,0x3a]
+0x6b,0x04,0x0a,0x3a
+
+# GFX12: v_xor_b32_e32 v5, ttmp15, v2            ; encoding: [0x7b,0x04,0x0a,0x3a]
+0x7b,0x04,0x0a,0x3a
+
+# GFX12: v_xor_b32_e32 v5, m0, v2                ; encoding: [0x7d,0x04,0x0a,0x3a]
+0x7d,0x04,0x0a,0x3a
+
+# GFX12: v_xor_b32_e32 v5, exec_lo, v2           ; encoding: [0x7e,0x04,0x0a,0x3a]
+0x7e,0x04,0x0a,0x3a
+
+# GFX12: v_xor_b32_e32 v5, exec_hi, v2           ; encoding: [0x7f,0x04,0x0a,0x3a]
+0x7f,0x04,0x0a,0x3a
+
+# GFX12: v_xor_b32_e32 v5, null, v2              ; encoding: [0x7c,0x04,0x0a,0x3a]
+0x7c,0x04,0x0a,0x3a
+
+# GFX12: v_xor_b32_e32 v5, -1, v2                ; encoding: [0xc1,0x04,0x0a,0x3a]
+0xc1,0x04,0x0a,0x3a
+
+# GFX12: v_xor_b32_e32 v5, 0.5, v2               ; encoding: [0xf0,0x04,0x0a,0x3a]
+0xf0,0x04,0x0a,0x3a
+
+# GFX12: v_xor_b32_e32 v5, src_scc, v2           ; encoding: [0xfd,0x04,0x0a,0x3a]
+0xfd,0x04,0x0a,0x3a
+
+# GFX12: v_xor_b32_e32 v255, 0xaf123456, v255    ; encoding: [0xff,0xfe,0xff,0x3b,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x3b,0x56,0x34,0x12,0xaf
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp16.txt
new file mode 100644
index 000000000000..7f7d76819306
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp16.txt
@@ -0,0 +1,1696 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32 %s
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64 %s
+
+# W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0xff]
+# W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0xff
+
+# W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xff]
+# W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xff
+
+# W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x40,0x01,0xff]
+# W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x40,0x01,0x40,0x01,0xff
+
+# W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x41,0x01,0xff]
+# W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x40,0x01,0x41,0x01,0xff
+
+# W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x01,0x01,0xff]
+# W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x40,0x01,0x01,0x01,0xff
+
+# W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x0f,0x01,0xff]
+# W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x40,0x01,0x0f,0x01,0xff
+
+# W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x11,0x01,0xff]
+# W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x40,0x01,0x11,0x01,0xff
+
+# W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1f,0x01,0xff]
+# W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x40,0x01,0x1f,0x01,0xff
+
+# W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x21,0x01,0xff]
+# W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x40,0x01,0x21,0x01,0xff
+
+# W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x2f,0x01,0xff]
+# W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x40,0x01,0x2f,0x01,0xff
+
+# W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x50,0x01,0xff]
+# W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x40,0x01,0x50,0x01,0xff
+
+# W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x60,0x01,0x13]
+# W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x40,0x01,0x60,0x01,0x13
+
+# W32: v_add_co_ci_u32_dpp v255, vcc_lo, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x41,0xff,0x6f,0x0d,0x30]
+# W64: v_add_co_ci_u32_dpp v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x41,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0xff,0x41,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_add_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0xff
+
+# GFX12: v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0xff
+
+# GFX12: v_add_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x64,0x01,0x40,0x01,0xff
+
+# GFX12: v_add_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x64,0x01,0x41,0x01,0xff
+
+# GFX12: v_add_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x64,0x01,0x01,0x01,0xff
+
+# GFX12: v_add_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x64,0x01,0x0f,0x01,0xff
+
+# GFX12: v_add_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x64,0x01,0x11,0x01,0xff
+
+# GFX12: v_add_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x64,0x01,0x1f,0x01,0xff
+
+# GFX12: v_add_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x64,0x01,0x21,0x01,0xff
+
+# GFX12: v_add_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x64,0x01,0x2f,0x01,0xff
+
+# GFX12: v_add_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x64,0x01,0x50,0x01,0xff
+
+# GFX12: v_add_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x64,0x01,0x5f,0x01,0x01
+
+# GFX12: v_add_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x64,0x01,0x60,0x01,0x13
+
+# GFX12: v_add_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x64,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0xfe,0x64,0x7f,0x6f,0xfd,0x30
+
+# GFX12: v_add_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x06,0x01,0x1b,0x00,0xff
+
+# GFX12: v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0xff
+
+# GFX12: v_add_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x06,0x01,0x40,0x01,0xff
+
+# GFX12: v_add_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x06,0x01,0x41,0x01,0xff
+
+# GFX12: v_add_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x06,0x01,0x01,0x01,0xff
+
+# GFX12: v_add_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x06,0x01,0x0f,0x01,0xff
+
+# GFX12: v_add_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x06,0x01,0x11,0x01,0xff
+
+# GFX12: v_add_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x06,0x01,0x1f,0x01,0xff
+
+# GFX12: v_add_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x06,0x01,0x21,0x01,0xff
+
+# GFX12: v_add_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x06,0x01,0x2f,0x01,0xff
+
+# GFX12: v_add_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x06,0x01,0x50,0x01,0xff
+
+# GFX12: v_add_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x06,0x01,0x5f,0x01,0x01
+
+# GFX12: v_add_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x06,0x01,0x60,0x01,0x13
+
+# GFX12: v_add_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x07,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0xff,0x07,0xff,0x6f,0xfd,0x30
+
+# GFX12: v_add_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x4a,0x01,0x1b,0x00,0xff
+
+# GFX12: v_add_nc_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x4a,0x01,0xe4,0x00,0xff
+
+# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x4a,0x01,0x40,0x01,0xff
+
+# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x4a,0x01,0x41,0x01,0xff
+
+# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x4a,0x01,0x01,0x01,0xff
+
+# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x4a,0x01,0x0f,0x01,0xff
+
+# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x4a,0x01,0x11,0x01,0xff
+
+# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x4a,0x01,0x1f,0x01,0xff
+
+# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x4a,0x01,0x21,0x01,0xff
+
+# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x4a,0x01,0x2f,0x01,0xff
+
+# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x4a,0x01,0x50,0x01,0xff
+
+# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x4a,0x01,0x5f,0x01,0x01
+
+# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x4a,0x01,0x60,0x01,0x13
+
+# GFX12: v_add_nc_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x4b,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0xff,0x4b,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_and_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x36,0x01,0x1b,0x00,0xff
+
+# GFX12: v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0xff
+
+# GFX12: v_and_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x36,0x01,0x40,0x01,0xff
+
+# GFX12: v_and_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x36,0x01,0x41,0x01,0xff
+
+# GFX12: v_and_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x36,0x01,0x01,0x01,0xff
+
+# GFX12: v_and_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x36,0x01,0x0f,0x01,0xff
+
+# GFX12: v_and_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x36,0x01,0x11,0x01,0xff
+
+# GFX12: v_and_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x36,0x01,0x1f,0x01,0xff
+
+# GFX12: v_and_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x36,0x01,0x21,0x01,0xff
+
+# GFX12: v_and_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x36,0x01,0x2f,0x01,0xff
+
+# GFX12: v_and_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x36,0x01,0x50,0x01,0xff
+
+# GFX12: v_and_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x36,0x01,0x5f,0x01,0x01
+
+# GFX12: v_and_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x36,0x01,0x60,0x01,0x13
+
+# GFX12: v_and_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x37,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0xff,0x37,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x34,0x01,0x1b,0x00,0xff
+
+# GFX12: v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0xff
+
+# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x34,0x01,0x40,0x01,0xff
+
+# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x34,0x01,0x41,0x01,0xff
+
+# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x34,0x01,0x01,0x01,0xff
+
+# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x34,0x01,0x0f,0x01,0xff
+
+# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x34,0x01,0x11,0x01,0xff
+
+# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x34,0x01,0x1f,0x01,0xff
+
+# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x34,0x01,0x21,0x01,0xff
+
+# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x34,0x01,0x2f,0x01,0xff
+
+# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x34,0x01,0x50,0x01,0xff
+
+# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x34,0x01,0x5f,0x01,0x01
+
+# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x34,0x01,0x60,0x01,0x13
+
+# GFX12: v_ashrrev_i32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x35,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0xff,0x35,0xff,0x6f,0x0d,0x30
+
+# W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1b,0x00,0xff]
+# W64: v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x02,0x01,0x1b,0x00,0xff
+
+# W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xff]
+# W64: v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xff
+
+# W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x40,0x01,0xff]
+# W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x02,0x01,0x40,0x01,0xff
+
+# W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x41,0x01,0xff]
+# W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x02,0x01,0x41,0x01,0xff
+
+# W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x01,0x01,0xff]
+# W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x02,0x01,0x01,0x01,0xff
+
+# W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x0f,0x01,0xff]
+# W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x02,0x01,0x0f,0x01,0xff
+
+# W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x11,0x01,0xff]
+# W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x02,0x01,0x11,0x01,0xff
+
+# W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1f,0x01,0xff]
+# W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x02,0x01,0x1f,0x01,0xff
+
+# W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x21,0x01,0xff]
+# W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x02,0x01,0x21,0x01,0xff
+
+# W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x2f,0x01,0xff]
+# W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x02,0x01,0x2f,0x01,0xff
+
+# W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x50,0x01,0xff]
+# W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x02,0x01,0x50,0x01,0xff
+
+# W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x5f,0x01,0x01]
+# W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x02,0x01,0x5f,0x01,0x01
+
+# W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x60,0x01,0x13]
+# W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x02,0x01,0x60,0x01,0x13
+
+# W32: v_cndmask_b32_dpp v255, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x03,0xff,0x6f,0x0d,0x30]
+# W64: v_cndmask_b32_dpp v255, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x03,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0xff,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x5e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x5e,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x5e,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x5e,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x5e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x5e,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x5e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x5e,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x5e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x5e,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x5e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x5e,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_pk_rtz_f16_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x5f,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0xff,0x5f,0xff,0x6f,0xfd,0x30
+
+# GFX12: v_fmac_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x6c,0x01,0x1b,0x00,0xff
+
+# GFX12: v_fmac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0xff
+
+# GFX12: v_fmac_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x6c,0x01,0x40,0x01,0xff
+
+# GFX12: v_fmac_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x6c,0x01,0x41,0x01,0xff
+
+# GFX12: v_fmac_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x6c,0x01,0x01,0x01,0xff
+
+# GFX12: v_fmac_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x6c,0x01,0x0f,0x01,0xff
+
+# GFX12: v_fmac_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x6c,0x01,0x11,0x01,0xff
+
+# GFX12: v_fmac_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x6c,0x01,0x1f,0x01,0xff
+
+# GFX12: v_fmac_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x6c,0x01,0x21,0x01,0xff
+
+# GFX12: v_fmac_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x6c,0x01,0x2f,0x01,0xff
+
+# GFX12: v_fmac_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x6c,0x01,0x50,0x01,0xff
+
+# GFX12: v_fmac_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x6c,0x01,0x5f,0x01,0x01
+
+# GFX12: v_fmac_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x6c,0x01,0x60,0x01,0x13
+
+# GFX12: v_fmac_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x6c,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0xfe,0x6c,0x7f,0x6f,0xfd,0x30
+
+# GFX12: v_fmac_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x56,0x01,0x1b,0x00,0xff
+
+# GFX12: v_fmac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0xff
+
+# GFX12: v_fmac_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x56,0x01,0x40,0x01,0xff
+
+# GFX12: v_fmac_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x56,0x01,0x41,0x01,0xff
+
+# GFX12: v_fmac_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x56,0x01,0x01,0x01,0xff
+
+# GFX12: v_fmac_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x56,0x01,0x0f,0x01,0xff
+
+# GFX12: v_fmac_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x56,0x01,0x11,0x01,0xff
+
+# GFX12: v_fmac_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x56,0x01,0x1f,0x01,0xff
+
+# GFX12: v_fmac_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x56,0x01,0x21,0x01,0xff
+
+# GFX12: v_fmac_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x56,0x01,0x2f,0x01,0xff
+
+# GFX12: v_fmac_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x56,0x01,0x50,0x01,0xff
+
+# GFX12: v_fmac_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x56,0x01,0x5f,0x01,0x01
+
+# GFX12: v_fmac_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x56,0x01,0x60,0x01,0x13
+
+# GFX12: v_fmac_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x57,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0xff,0x57,0xff,0x6f,0xfd,0x30
+
+# GFX12: v_ldexp_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x76,0x01,0x1b,0x00,0xff
+
+# GFX12: v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0xff
+
+# GFX12: v_ldexp_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x76,0x01,0x40,0x01,0xff
+
+# GFX12: v_ldexp_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x76,0x01,0x41,0x01,0xff
+
+# GFX12: v_ldexp_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x76,0x01,0x01,0x01,0xff
+
+# GFX12: v_ldexp_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x76,0x01,0x0f,0x01,0xff
+
+# GFX12: v_ldexp_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x76,0x01,0x11,0x01,0xff
+
+# GFX12: v_ldexp_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x76,0x01,0x1f,0x01,0xff
+
+# GFX12: v_ldexp_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x76,0x01,0x21,0x01,0xff
+
+# GFX12: v_ldexp_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x76,0x01,0x2f,0x01,0xff
+
+# GFX12: v_ldexp_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x76,0x01,0x50,0x01,0xff
+
+# GFX12: v_ldexp_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x76,0x01,0x5f,0x01,0x01
+
+# GFX12: v_ldexp_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x76,0x01,0x60,0x01,0x13
+
+# GFX12: v_ldexp_f16_dpp v127, -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x76,0x7f,0x6f,0x3d,0x30]
+0xfa,0xfe,0xfe,0x76,0x7f,0x6f,0x3d,0x30
+
+# GFX12: v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x30,0x01,0x1b,0x00,0xff
+
+# GFX12: v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0xff
+
+# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x30,0x01,0x40,0x01,0xff
+
+# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x30,0x01,0x41,0x01,0xff
+
+# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x30,0x01,0x01,0x01,0xff
+
+# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x30,0x01,0x0f,0x01,0xff
+
+# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x30,0x01,0x11,0x01,0xff
+
+# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x30,0x01,0x1f,0x01,0xff
+
+# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x30,0x01,0x21,0x01,0xff
+
+# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x30,0x01,0x2f,0x01,0xff
+
+# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x30,0x01,0x50,0x01,0xff
+
+# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x30,0x01,0x5f,0x01,0x01
+
+# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x30,0x01,0x60,0x01,0x13
+
+# GFX12: v_lshlrev_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x31,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0xff,0x31,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x32,0x01,0x1b,0x00,0xff
+
+# GFX12: v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0xff
+
+# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x32,0x01,0x40,0x01,0xff
+
+# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x32,0x01,0x41,0x01,0xff
+
+# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x32,0x01,0x01,0x01,0xff
+
+# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x32,0x01,0x0f,0x01,0xff
+
+# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x32,0x01,0x11,0x01,0xff
+
+# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x32,0x01,0x1f,0x01,0xff
+
+# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x32,0x01,0x21,0x01,0xff
+
+# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x32,0x01,0x2f,0x01,0xff
+
+# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x32,0x01,0x50,0x01,0xff
+
+# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x32,0x01,0x5f,0x01,0x01
+
+# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x32,0x01,0x60,0x01,0x13
+
+# GFX12: v_lshrrev_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x33,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0xff,0x33,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_max_num_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x62,0x01,0x1b,0x00,0xff
+
+# GFX12: v_max_num_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0xff
+
+# GFX12: v_max_num_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x62,0x01,0x40,0x01,0xff
+
+# GFX12: v_max_num_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x62,0x01,0x41,0x01,0xff
+
+# GFX12: v_max_num_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x62,0x01,0x01,0x01,0xff
+
+# GFX12: v_max_num_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x62,0x01,0x0f,0x01,0xff
+
+# GFX12: v_max_num_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x62,0x01,0x11,0x01,0xff
+
+# GFX12: v_max_num_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x62,0x01,0x1f,0x01,0xff
+
+# GFX12: v_max_num_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x62,0x01,0x21,0x01,0xff
+
+# GFX12: v_max_num_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x62,0x01,0x2f,0x01,0xff
+
+# GFX12: v_max_num_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x62,0x01,0x50,0x01,0xff
+
+# GFX12: v_max_num_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x62,0x01,0x5f,0x01,0x01
+
+# GFX12: v_max_num_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x62,0x01,0x60,0x01,0x13
+
+# GFX12: v_max_num_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x62,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0xfe,0x62,0x7f,0x6f,0xfd,0x30
+
+# GFX12: v_max_num_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x2c,0x01,0x1b,0x00,0xff
+
+# GFX12: v_max_num_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0xff
+
+# GFX12: v_max_num_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x2c,0x01,0x40,0x01,0xff
+
+# GFX12: v_max_num_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x2c,0x01,0x41,0x01,0xff
+
+# GFX12: v_max_num_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x2c,0x01,0x01,0x01,0xff
+
+# GFX12: v_max_num_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x2c,0x01,0x0f,0x01,0xff
+
+# GFX12: v_max_num_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x2c,0x01,0x11,0x01,0xff
+
+# GFX12: v_max_num_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x2c,0x01,0x1f,0x01,0xff
+
+# GFX12: v_max_num_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x2c,0x01,0x21,0x01,0xff
+
+# GFX12: v_max_num_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x2c,0x01,0x2f,0x01,0xff
+
+# GFX12: v_max_num_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x2c,0x01,0x50,0x01,0xff
+
+# GFX12: v_max_num_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x2c,0x01,0x5f,0x01,0x01
+
+# GFX12: v_max_num_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x2c,0x01,0x60,0x01,0x13
+
+# GFX12: v_max_num_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x2d,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0xff,0x2d,0xff,0x6f,0xfd,0x30
+
+# GFX12: v_max_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x24,0x01,0x1b,0x00,0xff
+
+# GFX12: v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0xff
+
+# GFX12: v_max_i32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x24,0x01,0x40,0x01,0xff
+
+# GFX12: v_max_i32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x24,0x01,0x41,0x01,0xff
+
+# GFX12: v_max_i32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x24,0x01,0x01,0x01,0xff
+
+# GFX12: v_max_i32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x24,0x01,0x0f,0x01,0xff
+
+# GFX12: v_max_i32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x24,0x01,0x11,0x01,0xff
+
+# GFX12: v_max_i32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x24,0x01,0x1f,0x01,0xff
+
+# GFX12: v_max_i32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x24,0x01,0x21,0x01,0xff
+
+# GFX12: v_max_i32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x24,0x01,0x2f,0x01,0xff
+
+# GFX12: v_max_i32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x24,0x01,0x50,0x01,0xff
+
+# GFX12: v_max_i32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x24,0x01,0x5f,0x01,0x01
+
+# GFX12: v_max_i32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x24,0x01,0x60,0x01,0x13
+
+# GFX12: v_max_i32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x25,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0xff,0x25,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_max_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x28,0x01,0x1b,0x00,0xff
+
+# GFX12: v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0xff
+
+# GFX12: v_max_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x28,0x01,0x40,0x01,0xff
+
+# GFX12: v_max_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x28,0x01,0x41,0x01,0xff
+
+# GFX12: v_max_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x28,0x01,0x01,0x01,0xff
+
+# GFX12: v_max_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x28,0x01,0x0f,0x01,0xff
+
+# GFX12: v_max_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x28,0x01,0x11,0x01,0xff
+
+# GFX12: v_max_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x28,0x01,0x1f,0x01,0xff
+
+# GFX12: v_max_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x28,0x01,0x21,0x01,0xff
+
+# GFX12: v_max_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x28,0x01,0x2f,0x01,0xff
+
+# GFX12: v_max_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x28,0x01,0x50,0x01,0xff
+
+# GFX12: v_max_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x28,0x01,0x5f,0x01,0x01
+
+# GFX12: v_max_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x28,0x01,0x60,0x01,0x13
+
+# GFX12: v_max_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x29,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0xff,0x29,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_min_num_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x60,0x01,0x1b,0x00,0xff
+
+# GFX12: v_min_num_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0xff
+
+# GFX12: v_min_num_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x60,0x01,0x40,0x01,0xff
+
+# GFX12: v_min_num_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x60,0x01,0x41,0x01,0xff
+
+# GFX12: v_min_num_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x60,0x01,0x01,0x01,0xff
+
+# GFX12: v_min_num_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x60,0x01,0x0f,0x01,0xff
+
+# GFX12: v_min_num_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x60,0x01,0x11,0x01,0xff
+
+# GFX12: v_min_num_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x60,0x01,0x1f,0x01,0xff
+
+# GFX12: v_min_num_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x60,0x01,0x21,0x01,0xff
+
+# GFX12: v_min_num_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x60,0x01,0x2f,0x01,0xff
+
+# GFX12: v_min_num_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x60,0x01,0x50,0x01,0xff
+
+# GFX12: v_min_num_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x60,0x01,0x5f,0x01,0x01
+
+# GFX12: v_min_num_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x60,0x01,0x60,0x01,0x13
+
+# GFX12: v_min_num_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x60,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0xfe,0x60,0x7f,0x6f,0xfd,0x30
+
+# GFX12: v_min_num_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x2a,0x01,0x1b,0x00,0xff
+
+# GFX12: v_min_num_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0xff
+
+# GFX12: v_min_num_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x2a,0x01,0x40,0x01,0xff
+
+# GFX12: v_min_num_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x2a,0x01,0x41,0x01,0xff
+
+# GFX12: v_min_num_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x2a,0x01,0x01,0x01,0xff
+
+# GFX12: v_min_num_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x2a,0x01,0x0f,0x01,0xff
+
+# GFX12: v_min_num_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x2a,0x01,0x11,0x01,0xff
+
+# GFX12: v_min_num_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x2a,0x01,0x1f,0x01,0xff
+
+# GFX12: v_min_num_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x2a,0x01,0x21,0x01,0xff
+
+# GFX12: v_min_num_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x2a,0x01,0x2f,0x01,0xff
+
+# GFX12: v_min_num_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x2a,0x01,0x50,0x01,0xff
+
+# GFX12: v_min_num_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x2a,0x01,0x5f,0x01,0x01
+
+# GFX12: v_min_num_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x2a,0x01,0x60,0x01,0x13
+
+# GFX12: v_min_num_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x2b,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0xff,0x2b,0xff,0x6f,0xfd,0x30
+
+# GFX12: v_min_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x22,0x01,0x1b,0x00,0xff
+
+# GFX12: v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0xff
+
+# GFX12: v_min_i32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x22,0x01,0x40,0x01,0xff
+
+# GFX12: v_min_i32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x22,0x01,0x41,0x01,0xff
+
+# GFX12: v_min_i32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x22,0x01,0x01,0x01,0xff
+
+# GFX12: v_min_i32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x22,0x01,0x0f,0x01,0xff
+
+# GFX12: v_min_i32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x22,0x01,0x11,0x01,0xff
+
+# GFX12: v_min_i32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x22,0x01,0x1f,0x01,0xff
+
+# GFX12: v_min_i32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x22,0x01,0x21,0x01,0xff
+
+# GFX12: v_min_i32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x22,0x01,0x2f,0x01,0xff
+
+# GFX12: v_min_i32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x22,0x01,0x50,0x01,0xff
+
+# GFX12: v_min_i32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x22,0x01,0x5f,0x01,0x01
+
+# GFX12: v_min_i32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x22,0x01,0x60,0x01,0x13
+
+# GFX12: v_min_i32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x23,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0xff,0x23,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_min_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x26,0x01,0x1b,0x00,0xff
+
+# GFX12: v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0xff
+
+# GFX12: v_min_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x26,0x01,0x40,0x01,0xff
+
+# GFX12: v_min_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x26,0x01,0x41,0x01,0xff
+
+# GFX12: v_min_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x26,0x01,0x01,0x01,0xff
+
+# GFX12: v_min_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x26,0x01,0x0f,0x01,0xff
+
+# GFX12: v_min_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x26,0x01,0x11,0x01,0xff
+
+# GFX12: v_min_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x26,0x01,0x1f,0x01,0xff
+
+# GFX12: v_min_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x26,0x01,0x21,0x01,0xff
+
+# GFX12: v_min_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x26,0x01,0x2f,0x01,0xff
+
+# GFX12: v_min_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x26,0x01,0x50,0x01,0xff
+
+# GFX12: v_min_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x26,0x01,0x5f,0x01,0x01
+
+# GFX12: v_min_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x26,0x01,0x60,0x01,0x13
+
+# GFX12: v_min_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x27,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0xff,0x27,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x0e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x0e,0x01,0x40,0x01,0xff
+
+# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x0e,0x01,0x41,0x01,0xff
+
+# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x0e,0x01,0x01,0x01,0xff
+
+# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x0e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x0e,0x01,0x11,0x01,0xff
+
+# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x0e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x0e,0x01,0x21,0x01,0xff
+
+# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x0e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x0e,0x01,0x50,0x01,0xff
+
+# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x0e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x0e,0x01,0x60,0x01,0x13
+
+# GFX12: v_mul_dx9_zero_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x0f,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0xff,0x0f,0xff,0x6f,0xfd,0x30
+
+# GFX12: v_mul_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0xff
+
+# GFX12: v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xff
+
+# GFX12: v_mul_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x6a,0x01,0x40,0x01,0xff
+
+# GFX12: v_mul_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x6a,0x01,0x41,0x01,0xff
+
+# GFX12: v_mul_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x6a,0x01,0x01,0x01,0xff
+
+# GFX12: v_mul_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x6a,0x01,0x0f,0x01,0xff
+
+# GFX12: v_mul_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x6a,0x01,0x11,0x01,0xff
+
+# GFX12: v_mul_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x6a,0x01,0x1f,0x01,0xff
+
+# GFX12: v_mul_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x6a,0x01,0x21,0x01,0xff
+
+# GFX12: v_mul_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x6a,0x01,0x2f,0x01,0xff
+
+# GFX12: v_mul_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x6a,0x01,0x50,0x01,0xff
+
+# GFX12: v_mul_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x6a,0x01,0x5f,0x01,0x01
+
+# GFX12: v_mul_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x6a,0x01,0x60,0x01,0x13
+
+# GFX12: v_mul_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x6a,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0xfe,0x6a,0x7f,0x6f,0xfd,0x30
+
+# GFX12: v_mul_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x10,0x01,0x1b,0x00,0xff
+
+# GFX12: v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0xff
+
+# GFX12: v_mul_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x10,0x01,0x40,0x01,0xff
+
+# GFX12: v_mul_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x10,0x01,0x41,0x01,0xff
+
+# GFX12: v_mul_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x10,0x01,0x01,0x01,0xff
+
+# GFX12: v_mul_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x10,0x01,0x0f,0x01,0xff
+
+# GFX12: v_mul_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x10,0x01,0x11,0x01,0xff
+
+# GFX12: v_mul_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x10,0x01,0x1f,0x01,0xff
+
+# GFX12: v_mul_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x10,0x01,0x21,0x01,0xff
+
+# GFX12: v_mul_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x10,0x01,0x2f,0x01,0xff
+
+# GFX12: v_mul_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x10,0x01,0x50,0x01,0xff
+
+# GFX12: v_mul_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x10,0x01,0x5f,0x01,0x01
+
+# GFX12: v_mul_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_mul_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x11,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0xff,0x11,0xff,0x6f,0xfd,0x30
+
+# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x14,0x01,0x1b,0x00,0xff
+
+# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0xff
+
+# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x14,0x01,0x40,0x01,0xff
+
+# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x14,0x01,0x41,0x01,0xff
+
+# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x14,0x01,0x01,0x01,0xff
+
+# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x14,0x01,0x0f,0x01,0xff
+
+# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x14,0x01,0x11,0x01,0xff
+
+# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x14,0x01,0x1f,0x01,0xff
+
+# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x14,0x01,0x21,0x01,0xff
+
+# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x14,0x01,0x2f,0x01,0xff
+
+# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x14,0x01,0x50,0x01,0xff
+
+# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x14,0x01,0x5f,0x01,0x01
+
+# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x14,0x01,0x60,0x01,0x13
+
+# GFX12: v_mul_hi_i32_i24_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x15,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0xff,0x15,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x18,0x01,0x1b,0x00,0xff
+
+# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0xff
+
+# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x18,0x01,0x40,0x01,0xff
+
+# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x18,0x01,0x41,0x01,0xff
+
+# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x18,0x01,0x01,0x01,0xff
+
+# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x18,0x01,0x0f,0x01,0xff
+
+# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x18,0x01,0x11,0x01,0xff
+
+# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x18,0x01,0x1f,0x01,0xff
+
+# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x18,0x01,0x21,0x01,0xff
+
+# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x18,0x01,0x2f,0x01,0xff
+
+# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x18,0x01,0x50,0x01,0xff
+
+# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x18,0x01,0x5f,0x01,0x01
+
+# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x18,0x01,0x60,0x01,0x13
+
+# GFX12: v_mul_hi_u32_u24_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x19,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0xff,0x19,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x12,0x01,0x1b,0x00,0xff
+
+# GFX12: v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0xff
+
+# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x12,0x01,0x40,0x01,0xff
+
+# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x12,0x01,0x41,0x01,0xff
+
+# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x12,0x01,0x01,0x01,0xff
+
+# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x12,0x01,0x0f,0x01,0xff
+
+# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x12,0x01,0x11,0x01,0xff
+
+# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x12,0x01,0x1f,0x01,0xff
+
+# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x12,0x01,0x21,0x01,0xff
+
+# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x12,0x01,0x2f,0x01,0xff
+
+# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x12,0x01,0x50,0x01,0xff
+
+# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x12,0x01,0x5f,0x01,0x01
+
+# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x12,0x01,0x60,0x01,0x13
+
+# GFX12: v_mul_i32_i24_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x13,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0xff,0x13,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x16,0x01,0x1b,0x00,0xff
+
+# GFX12: v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0xff
+
+# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x16,0x01,0x40,0x01,0xff
+
+# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x16,0x01,0x41,0x01,0xff
+
+# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x16,0x01,0x01,0x01,0xff
+
+# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x16,0x01,0x0f,0x01,0xff
+
+# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x16,0x01,0x11,0x01,0xff
+
+# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x16,0x01,0x1f,0x01,0xff
+
+# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x16,0x01,0x21,0x01,0xff
+
+# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x16,0x01,0x2f,0x01,0xff
+
+# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x16,0x01,0x50,0x01,0xff
+
+# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x16,0x01,0x5f,0x01,0x01
+
+# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x16,0x01,0x60,0x01,0x13
+
+# GFX12: v_mul_u32_u24_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x17,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0xff,0x17,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_or_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x38,0x01,0x1b,0x00,0xff
+
+# GFX12: v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0xff
+
+# GFX12: v_or_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x38,0x01,0x40,0x01,0xff
+
+# GFX12: v_or_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x38,0x01,0x41,0x01,0xff
+
+# GFX12: v_or_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x38,0x01,0x01,0x01,0xff
+
+# GFX12: v_or_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x38,0x01,0x0f,0x01,0xff
+
+# GFX12: v_or_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x38,0x01,0x11,0x01,0xff
+
+# GFX12: v_or_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x38,0x01,0x1f,0x01,0xff
+
+# GFX12: v_or_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x38,0x01,0x21,0x01,0xff
+
+# GFX12: v_or_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x38,0x01,0x2f,0x01,0xff
+
+# GFX12: v_or_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x38,0x01,0x50,0x01,0xff
+
+# GFX12: v_or_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x38,0x01,0x5f,0x01,0x01
+
+# GFX12: v_or_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x38,0x01,0x60,0x01,0x13
+
+# GFX12: v_or_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x39,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0xff,0x39,0xff,0x6f,0x0d,0x30
+
+# W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x1b,0x00,0xff]
+# W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x42,0x01,0x1b,0x00,0xff
+
+# W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xff]
+# W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xff
+
+# W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x40,0x01,0xff]
+# W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x42,0x01,0x40,0x01,0xff
+
+# W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x41,0x01,0xff]
+# W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x42,0x01,0x41,0x01,0xff
+
+# W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x01,0x01,0xff]
+# W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x42,0x01,0x01,0x01,0xff
+
+# W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x0f,0x01,0xff]
+# W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x42,0x01,0x0f,0x01,0xff
+
+# W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x11,0x01,0xff]
+# W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x42,0x01,0x11,0x01,0xff
+
+# W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x1f,0x01,0xff]
+# W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x42,0x01,0x1f,0x01,0xff
+
+# W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x21,0x01,0xff]
+# W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x42,0x01,0x21,0x01,0xff
+
+# W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x2f,0x01,0xff]
+# W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x42,0x01,0x2f,0x01,0xff
+
+# W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x50,0x01,0xff]
+# W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x42,0x01,0x50,0x01,0xff
+
+# W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x5f,0x01,0x01]
+# W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x42,0x01,0x5f,0x01,0x01
+
+# W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x60,0x01,0x13]
+# W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x42,0x01,0x60,0x01,0x13
+
+# W32: v_sub_co_ci_u32_dpp v255, vcc_lo, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x43,0xff,0x6f,0x0d,0x30]
+# W64: v_sub_co_ci_u32_dpp v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x43,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0xff,0x43,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_sub_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x66,0x01,0x1b,0x00,0xff
+
+# GFX12: v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0xff
+
+# GFX12: v_sub_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x66,0x01,0x40,0x01,0xff
+
+# GFX12: v_sub_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x66,0x01,0x41,0x01,0xff
+
+# GFX12: v_sub_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x66,0x01,0x01,0x01,0xff
+
+# GFX12: v_sub_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x66,0x01,0x0f,0x01,0xff
+
+# GFX12: v_sub_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x66,0x01,0x11,0x01,0xff
+
+# GFX12: v_sub_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x66,0x01,0x1f,0x01,0xff
+
+# GFX12: v_sub_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x66,0x01,0x21,0x01,0xff
+
+# GFX12: v_sub_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x66,0x01,0x2f,0x01,0xff
+
+# GFX12: v_sub_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x66,0x01,0x50,0x01,0xff
+
+# GFX12: v_sub_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x66,0x01,0x5f,0x01,0x01
+
+# GFX12: v_sub_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x66,0x01,0x60,0x01,0x13
+
+# GFX12: v_sub_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x66,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0xfe,0x66,0x7f,0x6f,0xfd,0x30
+
+# GFX12: v_sub_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x08,0x01,0x1b,0x00,0xff
+
+# GFX12: v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0xff
+
+# GFX12: v_sub_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x08,0x01,0x40,0x01,0xff
+
+# GFX12: v_sub_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x08,0x01,0x41,0x01,0xff
+
+# GFX12: v_sub_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x08,0x01,0x01,0x01,0xff
+
+# GFX12: v_sub_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x08,0x01,0x0f,0x01,0xff
+
+# GFX12: v_sub_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x08,0x01,0x11,0x01,0xff
+
+# GFX12: v_sub_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x08,0x01,0x1f,0x01,0xff
+
+# GFX12: v_sub_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x08,0x01,0x21,0x01,0xff
+
+# GFX12: v_sub_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x08,0x01,0x2f,0x01,0xff
+
+# GFX12: v_sub_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x08,0x01,0x50,0x01,0xff
+
+# GFX12: v_sub_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_sub_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x08,0x01,0x60,0x01,0x13
+
+# GFX12: v_sub_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x09,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0xff,0x09,0xff,0x6f,0xfd,0x30
+
+# GFX12: v_sub_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x4c,0x01,0x1b,0x00,0xff
+
+# GFX12: v_sub_nc_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0xff
+
+# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x4c,0x01,0x40,0x01,0xff
+
+# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x4c,0x01,0x41,0x01,0xff
+
+# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x4c,0x01,0x01,0x01,0xff
+
+# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x4c,0x01,0x0f,0x01,0xff
+
+# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x4c,0x01,0x11,0x01,0xff
+
+# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x4c,0x01,0x1f,0x01,0xff
+
+# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x4c,0x01,0x21,0x01,0xff
+
+# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x4c,0x01,0x2f,0x01,0xff
+
+# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x4c,0x01,0x50,0x01,0xff
+
+# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x4c,0x01,0x5f,0x01,0x01
+
+# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x4c,0x01,0x60,0x01,0x13
+
+# GFX12: v_sub_nc_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x4d,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0xff,0x4d,0xff,0x6f,0x0d,0x30
+
+# W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x1b,0x00,0xff]
+# W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x44,0x01,0x1b,0x00,0xff
+
+# W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xff]
+# W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xff
+
+# W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x40,0x01,0xff]
+# W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x44,0x01,0x40,0x01,0xff
+
+# W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x41,0x01,0xff]
+# W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x44,0x01,0x41,0x01,0xff
+
+# W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x01,0x01,0xff]
+# W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x44,0x01,0x01,0x01,0xff
+
+# W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x0f,0x01,0xff]
+# W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x44,0x01,0x0f,0x01,0xff
+
+# W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x11,0x01,0xff]
+# W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x44,0x01,0x11,0x01,0xff
+
+# W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x1f,0x01,0xff]
+# W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x44,0x01,0x1f,0x01,0xff
+
+# W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x21,0x01,0xff]
+# W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x44,0x01,0x21,0x01,0xff
+
+# W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x2f,0x01,0xff]
+# W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x44,0x01,0x2f,0x01,0xff
+
+# W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x50,0x01,0xff]
+# W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x44,0x01,0x50,0x01,0xff
+
+# W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x5f,0x01,0x01]
+# W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x44,0x01,0x5f,0x01,0x01
+
+# W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x60,0x01,0x13]
+# W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x44,0x01,0x60,0x01,0x13
+
+# W32: v_subrev_co_ci_u32_dpp v255, vcc_lo, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x45,0xff,0x6f,0x0d,0x30]
+# W64: v_subrev_co_ci_u32_dpp v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x45,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0xff,0x45,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_subrev_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x68,0x01,0x1b,0x00,0xff
+
+# GFX12: v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0xff
+
+# GFX12: v_subrev_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x68,0x01,0x40,0x01,0xff
+
+# GFX12: v_subrev_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x68,0x01,0x41,0x01,0xff
+
+# GFX12: v_subrev_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x68,0x01,0x01,0x01,0xff
+
+# GFX12: v_subrev_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x68,0x01,0x0f,0x01,0xff
+
+# GFX12: v_subrev_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x68,0x01,0x11,0x01,0xff
+
+# GFX12: v_subrev_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x68,0x01,0x1f,0x01,0xff
+
+# GFX12: v_subrev_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x68,0x01,0x21,0x01,0xff
+
+# GFX12: v_subrev_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x68,0x01,0x2f,0x01,0xff
+
+# GFX12: v_subrev_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x68,0x01,0x50,0x01,0xff
+
+# GFX12: v_subrev_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x68,0x01,0x5f,0x01,0x01
+
+# GFX12: v_subrev_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x68,0x01,0x60,0x01,0x13
+
+# GFX12: v_subrev_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x68,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0xfe,0x68,0x7f,0x6f,0xfd,0x30
+
+# GFX12: v_subrev_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x0a,0x01,0x1b,0x00,0xff
+
+# GFX12: v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0xff
+
+# GFX12: v_subrev_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x0a,0x01,0x40,0x01,0xff
+
+# GFX12: v_subrev_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x0a,0x01,0x41,0x01,0xff
+
+# GFX12: v_subrev_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x0a,0x01,0x01,0x01,0xff
+
+# GFX12: v_subrev_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x0a,0x01,0x0f,0x01,0xff
+
+# GFX12: v_subrev_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x0a,0x01,0x11,0x01,0xff
+
+# GFX12: v_subrev_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x0a,0x01,0x1f,0x01,0xff
+
+# GFX12: v_subrev_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x0a,0x01,0x21,0x01,0xff
+
+# GFX12: v_subrev_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x0a,0x01,0x2f,0x01,0xff
+
+# GFX12: v_subrev_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x0a,0x01,0x50,0x01,0xff
+
+# GFX12: v_subrev_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x0a,0x01,0x5f,0x01,0x01
+
+# GFX12: v_subrev_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x0a,0x01,0x60,0x01,0x13
+
+# GFX12: v_subrev_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x0b,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0xff,0x0b,0xff,0x6f,0xfd,0x30
+
+# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x00,0xff
+
+# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0xff
+
+# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x4e,0x01,0x40,0x01,0xff
+
+# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x4e,0x01,0x41,0x01,0xff
+
+# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x4e,0x01,0x01,0x01,0xff
+
+# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x4e,0x01,0x0f,0x01,0xff
+
+# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x4e,0x01,0x11,0x01,0xff
+
+# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x4e,0x01,0x1f,0x01,0xff
+
+# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x4e,0x01,0x21,0x01,0xff
+
+# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x4e,0x01,0x2f,0x01,0xff
+
+# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x4e,0x01,0x50,0x01,0xff
+
+# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x4e,0x01,0x5f,0x01,0x01
+
+# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x4e,0x01,0x60,0x01,0x13
+
+# GFX12: v_subrev_nc_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x4f,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0xff,0x4f,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_xnor_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x3c,0x01,0x1b,0x00,0xff
+
+# GFX12: v_xnor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0xff
+
+# GFX12: v_xnor_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x3c,0x01,0x40,0x01,0xff
+
+# GFX12: v_xnor_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x3c,0x01,0x41,0x01,0xff
+
+# GFX12: v_xnor_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x3c,0x01,0x01,0x01,0xff
+
+# GFX12: v_xnor_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x3c,0x01,0x0f,0x01,0xff
+
+# GFX12: v_xnor_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x3c,0x01,0x11,0x01,0xff
+
+# GFX12: v_xnor_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x3c,0x01,0x1f,0x01,0xff
+
+# GFX12: v_xnor_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x3c,0x01,0x21,0x01,0xff
+
+# GFX12: v_xnor_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x3c,0x01,0x2f,0x01,0xff
+
+# GFX12: v_xnor_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x3c,0x01,0x50,0x01,0xff
+
+# GFX12: v_xnor_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x3c,0x01,0x5f,0x01,0x01
+
+# GFX12: v_xnor_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x3c,0x01,0x60,0x01,0x13
+
+# GFX12: v_xnor_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x3d,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0xff,0x3d,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_xor_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x3a,0x01,0x1b,0x00,0xff
+
+# GFX12: v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0xff
+
+# GFX12: v_xor_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x3a,0x01,0x40,0x01,0xff
+
+# GFX12: v_xor_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x3a,0x01,0x41,0x01,0xff
+
+# GFX12: v_xor_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x3a,0x01,0x01,0x01,0xff
+
+# GFX12: v_xor_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x3a,0x01,0x0f,0x01,0xff
+
+# GFX12: v_xor_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x3a,0x01,0x11,0x01,0xff
+
+# GFX12: v_xor_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x3a,0x01,0x1f,0x01,0xff
+
+# GFX12: v_xor_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x3a,0x01,0x21,0x01,0xff
+
+# GFX12: v_xor_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x3a,0x01,0x2f,0x01,0xff
+
+# GFX12: v_xor_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x3a,0x01,0x50,0x01,0xff
+
+# GFX12: v_xor_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x3a,0x01,0x5f,0x01,0x01
+
+# GFX12: v_xor_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x3a,0x01,0x60,0x01,0x13
+
+# GFX12: v_xor_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x3b,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0xff,0x3b,0xff,0x6f,0x0d,0x30
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp8.txt
new file mode 100644
index 000000000000..27d59eced837
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp8.txt
@@ -0,0 +1,244 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32 %s
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64 %s
+
+# W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x40,0x01,0x77,0x39,0x05]
+# W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x40,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_add_co_ci_u32_dpp v255, vcc_lo, v255, v255, vcc_lo dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x41,0xff,0x00,0x00,0x00]
+# W64: v_add_co_ci_u32_dpp v255, vcc, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x41,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x41,0xff,0x00,0x00,0x00
+
+# GFX12: v_add_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x64,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x64,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x64,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0xfe,0x64,0x7f,0x00,0x00,0x00
+
+# GFX12: v_add_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x06,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x06,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x07,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x07,0xff,0x00,0x00,0x00
+
+# GFX12: v_add_nc_u32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x4a,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x4a,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_nc_u32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x4b,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x4b,0xff,0x00,0x00,0x00
+
+# GFX12: v_and_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x36,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x36,0x01,0x77,0x39,0x05
+
+# GFX12: v_and_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x37,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x37,0xff,0x00,0x00,0x00
+
+# GFX12: v_ashrrev_i32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x34,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x34,0x01,0x77,0x39,0x05
+
+# GFX12: v_ashrrev_i32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x35,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x35,0xff,0x00,0x00,0x00
+
+# W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x02,0x01,0x77,0x39,0x05]
+# W64: v_cndmask_b32_dpp v5, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x02,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x02,0x01,0x77,0x39,0x05
+
+# W32: v_cndmask_b32_dpp v255, v255, v255, vcc_lo dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x03,0xff,0x00,0x00,0x00]
+# W64: v_cndmask_b32_dpp v255, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x03,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x5e,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x5e,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_rtz_f16_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x5f,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x5f,0xff,0x00,0x00,0x00
+
+# GFX12: v_fmac_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x6c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x6c,0x01,0x77,0x39,0x05
+
+# GFX12: v_fmac_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x6c,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0xfe,0x6c,0x7f,0x00,0x00,0x00
+
+# GFX12: v_fmac_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x56,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x56,0x01,0x77,0x39,0x05
+
+# GFX12: v_fmac_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x57,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x57,0xff,0x00,0x00,0x00
+
+# GFX12: v_ldexp_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x76,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x76,0x01,0x77,0x39,0x05
+
+# GFX12: v_ldexp_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x76,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0xfe,0x76,0x7f,0x00,0x00,0x00
+
+# GFX12: v_lshlrev_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x30,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x30,0x01,0x77,0x39,0x05
+
+# GFX12: v_lshlrev_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x31,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x31,0xff,0x00,0x00,0x00
+
+# GFX12: v_lshrrev_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x32,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x32,0x01,0x77,0x39,0x05
+
+# GFX12: v_lshrrev_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x33,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x33,0xff,0x00,0x00,0x00
+
+# GFX12: v_max_num_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x62,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x62,0x01,0x77,0x39,0x05
+
+# GFX12: v_max_num_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x62,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0xfe,0x62,0x7f,0x00,0x00,0x00
+
+# GFX12: v_max_num_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x2c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x2c,0x01,0x77,0x39,0x05
+
+# GFX12: v_max_num_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x2d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x2d,0xff,0x00,0x00,0x00
+
+# GFX12: v_max_i32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x24,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x24,0x01,0x77,0x39,0x05
+
+# GFX12: v_max_i32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x25,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x25,0xff,0x00,0x00,0x00
+
+# GFX12: v_max_u32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x28,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x28,0x01,0x77,0x39,0x05
+
+# GFX12: v_max_u32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x29,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x29,0xff,0x00,0x00,0x00
+
+# GFX12: v_min_num_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x60,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x60,0x01,0x77,0x39,0x05
+
+# GFX12: v_min_num_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x60,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0xfe,0x60,0x7f,0x00,0x00,0x00
+
+# GFX12: v_min_num_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x2a,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x2a,0x01,0x77,0x39,0x05
+
+# GFX12: v_min_num_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x2b,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x2b,0xff,0x00,0x00,0x00
+
+# GFX12: v_min_i32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x22,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x22,0x01,0x77,0x39,0x05
+
+# GFX12: v_min_i32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x23,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x23,0xff,0x00,0x00,0x00
+
+# GFX12: v_min_u32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x26,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x26,0x01,0x77,0x39,0x05
+
+# GFX12: v_min_u32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x27,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x27,0xff,0x00,0x00,0x00
+
+# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x0e,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x0e,0x01,0x77,0x39,0x05
+
+# GFX12: v_mul_dx9_zero_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x0f,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x0f,0xff,0x00,0x00,0x00
+
+# GFX12: v_mul_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05
+
+# GFX12: v_mul_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x6a,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0xfe,0x6a,0x7f,0x00,0x00,0x00
+
+# GFX12: v_mul_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x10,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_mul_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x11,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x11,0xff,0x00,0x00,0x00
+
+# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x14,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x14,0x01,0x77,0x39,0x05
+
+# GFX12: v_mul_hi_i32_i24_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x15,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x15,0xff,0x00,0x00,0x00
+
+# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x18,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x18,0x01,0x77,0x39,0x05
+
+# GFX12: v_mul_hi_u32_u24_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x19,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x19,0xff,0x00,0x00,0x00
+
+# GFX12: v_mul_i32_i24_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x12,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x12,0x01,0x77,0x39,0x05
+
+# GFX12: v_mul_i32_i24_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x13,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x13,0xff,0x00,0x00,0x00
+
+# GFX12: v_mul_u32_u24_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x16,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x16,0x01,0x77,0x39,0x05
+
+# GFX12: v_mul_u32_u24_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x17,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x17,0xff,0x00,0x00,0x00
+
+# GFX12: v_or_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x38,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x38,0x01,0x77,0x39,0x05
+
+# GFX12: v_or_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x39,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x39,0xff,0x00,0x00,0x00
+
+# W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x42,0x01,0x77,0x39,0x05]
+# W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x42,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x42,0x01,0x77,0x39,0x05
+
+# W32: v_sub_co_ci_u32_dpp v255, vcc_lo, v255, v255, vcc_lo dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x43,0xff,0x00,0x00,0x00]
+# W64: v_sub_co_ci_u32_dpp v255, vcc, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x43,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x43,0xff,0x00,0x00,0x00
+
+# GFX12: v_sub_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x66,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x66,0x01,0x77,0x39,0x05
+
+# GFX12: v_sub_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x66,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0xfe,0x66,0x7f,0x00,0x00,0x00
+
+# GFX12: v_sub_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x08,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_sub_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x09,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x09,0xff,0x00,0x00,0x00
+
+# GFX12: v_sub_nc_u32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x4c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x4c,0x01,0x77,0x39,0x05
+
+# GFX12: v_sub_nc_u32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x4d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x4d,0xff,0x00,0x00,0x00
+
+# W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x44,0x01,0x77,0x39,0x05]
+# W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x44,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x44,0x01,0x77,0x39,0x05
+
+# W32: v_subrev_co_ci_u32_dpp v255, vcc_lo, v255, v255, vcc_lo dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x45,0xff,0x00,0x00,0x00]
+# W64: v_subrev_co_ci_u32_dpp v255, vcc, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x45,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x45,0xff,0x00,0x00,0x00
+
+# GFX12: v_subrev_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x68,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x68,0x01,0x77,0x39,0x05
+
+# GFX12: v_subrev_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x68,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0xfe,0x68,0x7f,0x00,0x00,0x00
+
+# GFX12: v_subrev_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x0a,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x0a,0x01,0x77,0x39,0x05
+
+# GFX12: v_subrev_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x0b,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x0b,0xff,0x00,0x00,0x00
+
+# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x4e,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x4e,0x01,0x77,0x39,0x05
+
+# GFX12: v_subrev_nc_u32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x4f,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x4f,0xff,0x00,0x00,0x00
+
+# GFX12: v_xnor_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x3c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x3c,0x01,0x77,0x39,0x05
+
+# GFX12: v_xnor_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x3d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x3d,0xff,0x00,0x00,0x00
+
+# GFX12: v_xor_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x3a,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x3a,0x01,0x77,0x39,0x05
+
+# GFX12: v_xor_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x3b,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xff,0x3b,0xff,0x00,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
new file mode 100644
index 000000000000..7f4f142d5bc1
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
@@ -0,0 +1,5497 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32 %s
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64 %s
+
+# GFX12: v_add3_u32 v5, v1, v2, s3               ; encoding: [0x05,0x00,0x55,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x55,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_add3_u32 v5, v255, s2, s105           ; encoding: [0x05,0x00,0x55,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x55,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_add3_u32 v5, s1, v255, exec_hi        ; encoding: [0x05,0x00,0x55,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x55,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_add3_u32 v5, s105, s105, exec_lo      ; encoding: [0x05,0x00,0x55,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x55,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_add3_u32 v5, vcc_lo, ttmp15, v3       ; encoding: [0x05,0x00,0x55,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x55,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_add3_u32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x55,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x55,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_add3_u32 v5, ttmp15, src_scc, ttmp15  ; encoding: [0x05,0x00,0x55,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x55,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_add3_u32 v5, m0, 0.5, m0              ; encoding: [0x05,0x00,0x55,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x55,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_add3_u32 v5, exec_lo, -1, vcc_hi      ; encoding: [0x05,0x00,0x55,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x55,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_add3_u32 v5, exec_hi, null, vcc_lo    ; encoding: [0x05,0x00,0x55,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x55,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_add3_u32 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x55,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x55,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_add3_u32 v5, -1, exec_hi, src_scc     ; encoding: [0x05,0x00,0x55,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x55,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_add3_u32 v5, 0.5, m0, 0.5             ; encoding: [0x05,0x00,0x55,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x55,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_add3_u32 v5, src_scc, vcc_lo, -1      ; encoding: [0x05,0x00,0x55,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x55,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_add3_u32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x55,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x55,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# W32: v_add_co_u32 v5, s12, v1, v2              ; encoding: [0x05,0x0c,0x00,0xd7,0x01,0x05,0x02,0x00]
+# W64: v_add_co_u32 v5, s[12:13], v1, v2         ; encoding: [0x05,0x0c,0x00,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x0c,0x00,0xd7,0x01,0x05,0x02,0x00
+
+# W32: v_add_co_u32 v5, s12, v255, v255          ; encoding: [0x05,0x0c,0x00,0xd7,0xff,0xff,0x03,0x00]
+# W64: v_add_co_u32 v5, s[12:13], v255, v255     ; encoding: [0x05,0x0c,0x00,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x0c,0x00,0xd7,0xff,0xff,0x03,0x00
+
+# W32: v_add_co_u32 v5, s12, s1, s2              ; encoding: [0x05,0x0c,0x00,0xd7,0x01,0x04,0x00,0x00]
+# W64: v_add_co_u32 v5, s[12:13], s1, s2         ; encoding: [0x05,0x0c,0x00,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x0c,0x00,0xd7,0x01,0x04,0x00,0x00
+
+# W32: v_add_co_u32 v5, s12, s105, s105          ; encoding: [0x05,0x0c,0x00,0xd7,0x69,0xd2,0x00,0x00]
+# W64: v_add_co_u32 v5, s[12:13], s105, s105     ; encoding: [0x05,0x0c,0x00,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x0c,0x00,0xd7,0x69,0xd2,0x00,0x00
+
+# W32: v_add_co_u32 v5, s12, vcc_lo, ttmp15      ; encoding: [0x05,0x0c,0x00,0xd7,0x6a,0xf6,0x00,0x00]
+# W64: v_add_co_u32 v5, s[12:13], vcc_lo, ttmp15 ; encoding: [0x05,0x0c,0x00,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x0c,0x00,0xd7,0x6a,0xf6,0x00,0x00
+
+# W32: v_add_co_u32 v5, s12, vcc_hi, 0xaf123456  ; encoding: [0x05,0x0c,0x00,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_add_co_u32 v5, s[12:13], vcc_hi, 0xaf123456 ; encoding: [0x05,0x0c,0x00,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x0c,0x00,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_add_co_u32 v5, s12, ttmp15, src_scc     ; encoding: [0x05,0x0c,0x00,0xd7,0x7b,0xfa,0x01,0x00]
+# W64: v_add_co_u32 v5, s[12:13], ttmp15, src_scc ; encoding: [0x05,0x0c,0x00,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x0c,0x00,0xd7,0x7b,0xfa,0x01,0x00
+
+# W32: v_add_co_u32 v5, s12, m0, 0.5             ; encoding: [0x05,0x0c,0x00,0xd7,0x7d,0xe0,0x01,0x00]
+# W64: v_add_co_u32 v5, s[12:13], m0, 0.5        ; encoding: [0x05,0x0c,0x00,0xd7,0x7d,0xe0,0x01,0x00]
+0x05,0x0c,0x00,0xd7,0x7d,0xe0,0x01,0x00
+
+# W32: v_add_co_u32 v5, s12, exec_lo, -1         ; encoding: [0x05,0x0c,0x00,0xd7,0x7e,0x82,0x01,0x00]
+# W64: v_add_co_u32 v5, s[12:13], exec_lo, -1    ; encoding: [0x05,0x0c,0x00,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x0c,0x00,0xd7,0x7e,0x82,0x01,0x00
+
+# W32: v_add_co_u32 v5, s12, exec_hi, null       ; encoding: [0x05,0x0c,0x00,0xd7,0x7f,0xf8,0x00,0x00]
+# W64: v_add_co_u32 v5, s[12:13], exec_hi, null  ; encoding: [0x05,0x0c,0x00,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x0c,0x00,0xd7,0x7f,0xf8,0x00,0x00
+
+# W32: v_add_co_u32 v5, s12, null, exec_lo       ; encoding: [0x05,0x0c,0x00,0xd7,0x7c,0xfc,0x00,0x00]
+# W64: v_add_co_u32 v5, s[12:13], null, exec_lo  ; encoding: [0x05,0x0c,0x00,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x0c,0x00,0xd7,0x7c,0xfc,0x00,0x00
+
+# W32: v_add_co_u32 v5, s104, -1, exec_hi        ; encoding: [0x05,0x68,0x00,0xd7,0xc1,0xfe,0x00,0x00]
+# W64: v_add_co_u32 v5, s[104:105], -1, exec_hi  ; encoding: [0x05,0x68,0x00,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x68,0x00,0xd7,0xc1,0xfe,0x00,0x00
+
+# W32: v_add_co_u32 v5, vcc_lo, 0.5, m0          ; encoding: [0x05,0x6a,0x00,0xd7,0xf0,0xfa,0x00,0x00]
+# W64: v_add_co_u32 v5, vcc, 0.5, m0             ; encoding: [0x05,0x6a,0x00,0xd7,0xf0,0xfa,0x00,0x00]
+0x05,0x6a,0x00,0xd7,0xf0,0xfa,0x00,0x00
+
+# W32: v_add_co_u32 v5, ttmp14, src_scc, vcc_lo  ; encoding: [0x05,0x7a,0x00,0xd7,0xfd,0xd4,0x00,0x00]
+# W64: v_add_co_u32 v5, ttmp[14:15], src_scc, vcc_lo ; encoding: [0x05,0x7a,0x00,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x7a,0x00,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_add_co_u32 v255, null, 0xaf123456, vcc_hi clamp ; encoding: [0xff,0xfc,0x00,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x00,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_add_lshl_u32 v5, v1, v2, s3           ; encoding: [0x05,0x00,0x47,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x47,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_add_lshl_u32 v5, v255, s2, s105       ; encoding: [0x05,0x00,0x47,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x47,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_add_lshl_u32 v5, s1, v255, exec_hi    ; encoding: [0x05,0x00,0x47,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x47,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_add_lshl_u32 v5, s105, s105, exec_lo  ; encoding: [0x05,0x00,0x47,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x47,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_add_lshl_u32 v5, vcc_lo, ttmp15, v3   ; encoding: [0x05,0x00,0x47,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x47,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_add_lshl_u32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x47,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x47,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_add_lshl_u32 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x00,0x47,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x47,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_add_lshl_u32 v5, m0, 0.5, m0          ; encoding: [0x05,0x00,0x47,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x47,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_add_lshl_u32 v5, exec_lo, -1, vcc_hi  ; encoding: [0x05,0x00,0x47,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x47,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_add_lshl_u32 v5, exec_hi, null, vcc_lo ; encoding: [0x05,0x00,0x47,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x47,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_add_lshl_u32 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x47,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x47,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_add_lshl_u32 v5, -1, exec_hi, src_scc ; encoding: [0x05,0x00,0x47,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x47,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_add_lshl_u32 v5, 0.5, m0, 0.5         ; encoding: [0x05,0x00,0x47,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x47,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_add_lshl_u32 v5, src_scc, vcc_lo, -1  ; encoding: [0x05,0x00,0x47,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x47,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_add_lshl_u32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x47,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x47,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_add_nc_i16 v5, v1, v2                 ; encoding: [0x05,0x00,0x0d,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x0d,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_add_nc_i16 v5, v255, v255             ; encoding: [0x05,0x00,0x0d,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x0d,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_add_nc_i16 v5, s1, s2                 ; encoding: [0x05,0x00,0x0d,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x0d,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_add_nc_i16 v5, s105, s105             ; encoding: [0x05,0x00,0x0d,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x0d,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_add_nc_i16 v5, vcc_lo, ttmp15         ; encoding: [0x05,0x00,0x0d,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x0d,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_add_nc_i16 v5, vcc_hi, 0xfe0b         ; encoding: [0x05,0x00,0x0d,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x0d,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_add_nc_i16 v5, ttmp15, src_scc        ; encoding: [0x05,0x00,0x0d,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x0d,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_add_nc_i16 v5, m0, 0x3800
+0x05,0x00,0x0d,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_add_nc_i16 v5, exec_lo, -1            ; encoding: [0x05,0x00,0x0d,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x0d,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_add_nc_i16 v5, exec_hi, null          ; encoding: [0x05,0x00,0x0d,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x0d,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_add_nc_i16 v5, null, exec_lo          ; encoding: [0x05,0x00,0x0d,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x0d,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_add_nc_i16 v5, -1, exec_hi op_sel:[1,1,1] ; encoding: [0x05,0x58,0x0d,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x58,0x0d,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_add_nc_i16 v5, 0x3800, m0 op_sel:[1,0,0]
+0x05,0x08,0x0d,0xd7,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_add_nc_i16 v5, src_scc, vcc_lo op_sel:[0,1,0] ; encoding: [0x05,0x10,0x0d,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x10,0x0d,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_add_nc_i16 v255, 0xfe0b, vcc_hi op_sel:[0,0,1] clamp ; encoding: [0xff,0xc0,0x0d,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0xff,0xc0,0x0d,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_add_nc_i32 v5, v1, v2                 ; encoding: [0x05,0x00,0x26,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x26,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_add_nc_i32 v5, v255, v255             ; encoding: [0x05,0x00,0x26,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x26,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_add_nc_i32 v5, s1, s2                 ; encoding: [0x05,0x00,0x26,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x26,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_add_nc_i32 v5, s105, s105             ; encoding: [0x05,0x00,0x26,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x26,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_add_nc_i32 v5, vcc_lo, ttmp15         ; encoding: [0x05,0x00,0x26,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x26,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_add_nc_i32 v5, vcc_hi, 0xaf123456     ; encoding: [0x05,0x00,0x26,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x26,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_add_nc_i32 v5, ttmp15, src_scc        ; encoding: [0x05,0x00,0x26,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x26,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_add_nc_i32 v5, m0, 0.5                ; encoding: [0x05,0x00,0x26,0xd7,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x26,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_add_nc_i32 v5, exec_lo, -1            ; encoding: [0x05,0x00,0x26,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x26,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_add_nc_i32 v5, exec_hi, null          ; encoding: [0x05,0x00,0x26,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x26,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_add_nc_i32 v5, null, exec_lo          ; encoding: [0x05,0x00,0x26,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x26,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_add_nc_i32 v5, -1, exec_hi            ; encoding: [0x05,0x00,0x26,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x26,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_add_nc_i32 v5, 0.5, m0                ; encoding: [0x05,0x00,0x26,0xd7,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x26,0xd7,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_add_nc_i32 v5, src_scc, vcc_lo        ; encoding: [0x05,0x00,0x26,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x26,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_add_nc_i32 v255, 0xaf123456, vcc_hi clamp ; encoding: [0xff,0x80,0x26,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x80,0x26,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_add_nc_u16 v5, v1, v2                 ; encoding: [0x05,0x00,0x03,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x03,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_add_nc_u16 v5, v255, v255             ; encoding: [0x05,0x00,0x03,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x03,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_add_nc_u16 v5, s1, s2                 ; encoding: [0x05,0x00,0x03,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x03,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_add_nc_u16 v5, s105, s105             ; encoding: [0x05,0x00,0x03,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x03,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_add_nc_u16 v5, vcc_lo, ttmp15         ; encoding: [0x05,0x00,0x03,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x03,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_add_nc_u16 v5, vcc_hi, 0xfe0b         ; encoding: [0x05,0x00,0x03,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x03,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_add_nc_u16 v5, ttmp15, src_scc        ; encoding: [0x05,0x00,0x03,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x03,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_add_nc_u16 v5, m0, 0x3800
+0x05,0x00,0x03,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_add_nc_u16 v5, exec_lo, -1            ; encoding: [0x05,0x00,0x03,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x03,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_add_nc_u16 v5, exec_hi, null          ; encoding: [0x05,0x00,0x03,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x03,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_add_nc_u16 v5, null, exec_lo          ; encoding: [0x05,0x00,0x03,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x03,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_add_nc_u16 v5, -1, exec_hi op_sel:[1,1,1] ; encoding: [0x05,0x58,0x03,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x58,0x03,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_add_nc_u16 v5, 0x3800, m0 op_sel:[1,0,0]
+0x05,0x08,0x03,0xd7,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_add_nc_u16 v5, src_scc, vcc_lo op_sel:[0,1,0] ; encoding: [0x05,0x10,0x03,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x10,0x03,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_add_nc_u16 v255, 0xfe0b, vcc_hi op_sel:[0,0,1] clamp ; encoding: [0xff,0xc0,0x03,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0xff,0xc0,0x03,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_alignbit_b32 v5, v1, v2, s3           ; encoding: [0x05,0x00,0x16,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x16,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_alignbit_b32 v5, v255, s2, s3         ; encoding: [0x05,0x00,0x16,0xd6,0xff,0x05,0x0c,0x00]
+0x05,0x00,0x16,0xd6,0xff,0x05,0x0c,0x00
+
+# GFX12: v_alignbit_b32 v5, s1, v255, s3         ; encoding: [0x05,0x00,0x16,0xd6,0x01,0xfe,0x0f,0x00]
+0x05,0x00,0x16,0xd6,0x01,0xfe,0x0f,0x00
+
+# GFX12: v_alignbit_b32 v5, s105, s105, s105     ; encoding: [0x05,0x00,0x16,0xd6,0x69,0xd2,0xa4,0x01]
+0x05,0x00,0x16,0xd6,0x69,0xd2,0xa4,0x01
+
+# GFX12: v_alignbit_b32 v5, vcc_lo, ttmp15, v3   ; encoding: [0x05,0x00,0x16,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x16,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_alignbit_b32 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x00,0x16,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x16,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_alignbit_b32 v5, m0, 0.5, exec_lo     ; encoding: [0x05,0x00,0x16,0xd6,0x7d,0xe0,0xf9,0x01]
+0x05,0x00,0x16,0xd6,0x7d,0xe0,0xf9,0x01
+
+# GFX12: v_alignbit_b32 v5, exec_lo, -1, m0      ; encoding: [0x05,0x00,0x16,0xd6,0x7e,0x82,0xf5,0x01]
+0x05,0x00,0x16,0xd6,0x7e,0x82,0xf5,0x01
+
+# GFX12: v_alignbit_b32 v5, exec_hi, null, vcc_hi ; encoding: [0x05,0x00,0x16,0xd6,0x7f,0xf8,0xac,0x01]
+0x05,0x00,0x16,0xd6,0x7f,0xf8,0xac,0x01
+
+# GFX12: v_alignbit_b32 v5, null, exec_lo, vcc_lo ; encoding: [0x05,0x00,0x16,0xd6,0x7c,0xfc,0xa8,0x01]
+0x05,0x00,0x16,0xd6,0x7c,0xfc,0xa8,0x01
+
+# GFX12: v_alignbit_b32 v5, -1, exec_hi, src_scc ; encoding: [0x05,0x00,0x16,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x16,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_alignbit_b32 v5, 0.5, m0, exec_hi     ; encoding: [0x05,0x00,0x16,0xd6,0xf0,0xfa,0xfc,0x01]
+0x05,0x00,0x16,0xd6,0xf0,0xfa,0xfc,0x01
+
+# GFX12: v_alignbit_b32 v5, src_scc, vcc_lo, -1  ; encoding: [0x05,0x00,0x16,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x16,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_alignbit_b32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x16,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x16,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_alignbyte_b32 v5, v1, v2, s3          ; encoding: [0x05,0x00,0x17,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x17,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_alignbyte_b32 v5, v255, s2, s3        ; encoding: [0x05,0x00,0x17,0xd6,0xff,0x05,0x0c,0x00]
+0x05,0x00,0x17,0xd6,0xff,0x05,0x0c,0x00
+
+# GFX12: v_alignbyte_b32 v5, s1, v255, s3        ; encoding: [0x05,0x00,0x17,0xd6,0x01,0xfe,0x0f,0x00]
+0x05,0x00,0x17,0xd6,0x01,0xfe,0x0f,0x00
+
+# GFX12: v_alignbyte_b32 v5, s105, s105, s105    ; encoding: [0x05,0x00,0x17,0xd6,0x69,0xd2,0xa4,0x01]
+0x05,0x00,0x17,0xd6,0x69,0xd2,0xa4,0x01
+
+# GFX12: v_alignbyte_b32 v5, vcc_lo, ttmp15, v3  ; encoding: [0x05,0x00,0x17,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x17,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_alignbyte_b32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x17,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x17,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_alignbyte_b32 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x00,0x17,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x17,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_alignbyte_b32 v5, m0, 0.5, exec_lo    ; encoding: [0x05,0x00,0x17,0xd6,0x7d,0xe0,0xf9,0x01]
+0x05,0x00,0x17,0xd6,0x7d,0xe0,0xf9,0x01
+
+# GFX12: v_alignbyte_b32 v5, exec_lo, -1, m0     ; encoding: [0x05,0x00,0x17,0xd6,0x7e,0x82,0xf5,0x01]
+0x05,0x00,0x17,0xd6,0x7e,0x82,0xf5,0x01
+
+# GFX12: v_alignbyte_b32 v5, exec_hi, null, vcc_hi ; encoding: [0x05,0x00,0x17,0xd6,0x7f,0xf8,0xac,0x01]
+0x05,0x00,0x17,0xd6,0x7f,0xf8,0xac,0x01
+
+# GFX12: v_alignbyte_b32 v5, null, exec_lo, vcc_lo ; encoding: [0x05,0x00,0x17,0xd6,0x7c,0xfc,0xa8,0x01]
+0x05,0x00,0x17,0xd6,0x7c,0xfc,0xa8,0x01
+
+# GFX12: v_alignbyte_b32 v5, -1, exec_hi, src_scc ; encoding: [0x05,0x00,0x17,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x17,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_alignbyte_b32 v5, 0.5, m0, exec_hi    ; encoding: [0x05,0x00,0x17,0xd6,0xf0,0xfa,0xfc,0x01]
+0x05,0x00,0x17,0xd6,0xf0,0xfa,0xfc,0x01
+
+# GFX12: v_alignbyte_b32 v5, src_scc, vcc_lo, -1 ; encoding: [0x05,0x00,0x17,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x17,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_alignbyte_b32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x17,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x17,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_and_b16 v5, v1, v2                    ; encoding: [0x05,0x00,0x62,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x62,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_and_b16 v5, v255, v255                ; encoding: [0x05,0x00,0x62,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x62,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_and_b16 v5, s1, s2                    ; encoding: [0x05,0x00,0x62,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x62,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_and_b16 v5, s105, s105                ; encoding: [0x05,0x00,0x62,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x62,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_and_b16 v5, vcc_lo, ttmp15            ; encoding: [0x05,0x00,0x62,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x62,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_and_b16 v5, vcc_hi, 0xfe0b            ; encoding: [0x05,0x00,0x62,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x62,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_and_b16 v5, ttmp15, src_scc           ; encoding: [0x05,0x00,0x62,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x62,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_and_b16 v5, m0, 0x3800
+0x05,0x00,0x62,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_and_b16 v5, exec_lo, -1               ; encoding: [0x05,0x00,0x62,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x62,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_and_b16 v5, exec_hi, null             ; encoding: [0x05,0x00,0x62,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x62,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_and_b16 v5, null, exec_lo             ; encoding: [0x05,0x00,0x62,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x62,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_and_b16 v5, -1, exec_hi               ; encoding: [0x05,0x00,0x62,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x62,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_and_b16 v5, 0x3800, m0
+0x05,0x00,0x62,0xd7,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_and_b16 v5, src_scc, vcc_lo           ; encoding: [0x05,0x00,0x62,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x62,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_and_b16 v255, 0xfe0b, vcc_hi          ; encoding: [0xff,0x00,0x62,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0xff,0x00,0x62,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_and_or_b32 v5, v1, v2, s3             ; encoding: [0x05,0x00,0x57,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x57,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_and_or_b32 v5, v255, s2, s105         ; encoding: [0x05,0x00,0x57,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x57,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_and_or_b32 v5, s1, v255, exec_hi      ; encoding: [0x05,0x00,0x57,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x57,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_and_or_b32 v5, s105, s105, exec_lo    ; encoding: [0x05,0x00,0x57,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x57,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_and_or_b32 v5, vcc_lo, ttmp15, v3     ; encoding: [0x05,0x00,0x57,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x57,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_and_or_b32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x57,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x57,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_and_or_b32 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x00,0x57,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x57,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_and_or_b32 v5, m0, 0.5, m0            ; encoding: [0x05,0x00,0x57,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x57,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_and_or_b32 v5, exec_lo, -1, vcc_hi    ; encoding: [0x05,0x00,0x57,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x57,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_and_or_b32 v5, exec_hi, null, vcc_lo  ; encoding: [0x05,0x00,0x57,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x57,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_and_or_b32 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x57,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x57,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_and_or_b32 v5, -1, exec_hi, src_scc   ; encoding: [0x05,0x00,0x57,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x57,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_and_or_b32 v5, 0.5, m0, 0.5           ; encoding: [0x05,0x00,0x57,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x57,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_and_or_b32 v5, src_scc, vcc_lo, -1    ; encoding: [0x05,0x00,0x57,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x57,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_and_or_b32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x57,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x57,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_ashrrev_i16 v5, v1, v2                ; encoding: [0x05,0x00,0x3a,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x3a,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_ashrrev_i16 v5, v255, v255            ; encoding: [0x05,0x00,0x3a,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x3a,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_ashrrev_i16 v5, s1, s2                ; encoding: [0x05,0x00,0x3a,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x3a,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_ashrrev_i16 v5, s105, s105            ; encoding: [0x05,0x00,0x3a,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x3a,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_ashrrev_i16 v5, vcc_lo, ttmp15        ; encoding: [0x05,0x00,0x3a,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x3a,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_ashrrev_i16 v5, vcc_hi, 0xfe0b        ; encoding: [0x05,0x00,0x3a,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x3a,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_ashrrev_i16 v5, ttmp15, src_scc       ; encoding: [0x05,0x00,0x3a,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x3a,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_ashrrev_i16 v5, m0, 0x3800
+0x05,0x00,0x3a,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_ashrrev_i16 v5, exec_lo, -1           ; encoding: [0x05,0x00,0x3a,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x3a,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_ashrrev_i16 v5, exec_hi, null         ; encoding: [0x05,0x00,0x3a,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x3a,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_ashrrev_i16 v5, null, exec_lo         ; encoding: [0x05,0x00,0x3a,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x3a,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_ashrrev_i16 v5, -1, exec_hi           ; encoding: [0x05,0x00,0x3a,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x3a,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_ashrrev_i16 v5, 0x3800, m0
+0x05,0x00,0x3a,0xd7,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_ashrrev_i16 v5, src_scc, vcc_lo       ; encoding: [0x05,0x00,0x3a,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x3a,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_ashrrev_i16 v255, 0xfe0b, vcc_hi      ; encoding: [0xff,0x00,0x3a,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0xff,0x00,0x3a,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_ashrrev_i64 v[5:6], v1, vcc           ; encoding: [0x05,0x00,0x3e,0xd7,0x01,0xd5,0x00,0x00]
+0x05,0x00,0x3e,0xd7,0x01,0xd5,0x00,0x00
+
+# GFX12: v_ashrrev_i64 v[5:6], v255, exec        ; encoding: [0x05,0x00,0x3e,0xd7,0xff,0xfd,0x00,0x00]
+0x05,0x00,0x3e,0xd7,0xff,0xfd,0x00,0x00
+
+# GFX12: v_ashrrev_i64 v[5:6], exec_lo, v[2:3]   ; encoding: [0x05,0x00,0x3e,0xd7,0x7e,0x04,0x02,0x00]
+0x05,0x00,0x3e,0xd7,0x7e,0x04,0x02,0x00
+
+# GFX12: v_ashrrev_i64 v[5:6], exec_hi, v[254:255] ; encoding: [0x05,0x00,0x3e,0xd7,0x7f,0xfc,0x03,0x00]
+0x05,0x00,0x3e,0xd7,0x7f,0xfc,0x03,0x00
+
+# GFX12: v_ashrrev_i64 v[5:6], null, null        ; encoding: [0x05,0x00,0x3e,0xd7,0x7c,0xf8,0x00,0x00]
+0x05,0x00,0x3e,0xd7,0x7c,0xf8,0x00,0x00
+
+# GFX12: v_ashrrev_i64 v[5:6], -1, -1            ; encoding: [0x05,0x00,0x3e,0xd7,0xc1,0x82,0x01,0x00]
+0x05,0x00,0x3e,0xd7,0xc1,0x82,0x01,0x00
+
+# GFX12: v_ashrrev_i64 v[5:6], 0.5, 0xaf123456   ; encoding: [0x05,0x00,0x3e,0xd7,0xf0,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x3e,0xd7,0xf0,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_ashrrev_i64 v[5:6], src_scc, src_scc  ; encoding: [0x05,0x00,0x3e,0xd7,0xfd,0xfa,0x01,0x00]
+0x05,0x00,0x3e,0xd7,0xfd,0xfa,0x01,0x00
+
+# GFX12: v_ashrrev_i64 v[254:255], 0xaf123456, 0.5 ; encoding: [0xfe,0x00,0x3e,0xd7,0xff,0xe0,0x01,0x00,0x56,0x34,0x12,0xaf]
+0xfe,0x00,0x3e,0xd7,0xff,0xe0,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_bcnt_u32_b32 v5, v1, v2               ; encoding: [0x05,0x00,0x1e,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x1e,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_bcnt_u32_b32 v5, v255, v255           ; encoding: [0x05,0x00,0x1e,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x1e,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_bcnt_u32_b32 v5, s1, s2               ; encoding: [0x05,0x00,0x1e,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x1e,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_bcnt_u32_b32 v5, s105, s105           ; encoding: [0x05,0x00,0x1e,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x1e,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_bcnt_u32_b32 v5, vcc_lo, ttmp15       ; encoding: [0x05,0x00,0x1e,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x1e,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_bcnt_u32_b32 v5, vcc_hi, 0xaf123456   ; encoding: [0x05,0x00,0x1e,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x1e,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_bcnt_u32_b32 v5, ttmp15, src_scc      ; encoding: [0x05,0x00,0x1e,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x1e,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_bcnt_u32_b32 v5, m0, 0.5              ; encoding: [0x05,0x00,0x1e,0xd7,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x1e,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_bcnt_u32_b32 v5, exec_lo, -1          ; encoding: [0x05,0x00,0x1e,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x1e,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_bcnt_u32_b32 v5, exec_hi, null        ; encoding: [0x05,0x00,0x1e,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x1e,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_bcnt_u32_b32 v5, null, exec_lo        ; encoding: [0x05,0x00,0x1e,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x1e,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_bcnt_u32_b32 v5, -1, exec_hi          ; encoding: [0x05,0x00,0x1e,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x1e,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_bcnt_u32_b32 v5, 0.5, m0              ; encoding: [0x05,0x00,0x1e,0xd7,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x1e,0xd7,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_bcnt_u32_b32 v5, src_scc, vcc_lo      ; encoding: [0x05,0x00,0x1e,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x1e,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_bcnt_u32_b32 v255, 0xaf123456, vcc_hi ; encoding: [0xff,0x00,0x1e,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x1e,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_bfe_i32 v5, v1, v2, s3                ; encoding: [0x05,0x00,0x11,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x11,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_bfe_i32 v5, v255, s2, s105            ; encoding: [0x05,0x00,0x11,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x11,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_bfe_i32 v5, s1, v255, exec_hi         ; encoding: [0x05,0x00,0x11,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x11,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_bfe_i32 v5, s105, s105, exec_lo       ; encoding: [0x05,0x00,0x11,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x11,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_bfe_i32 v5, vcc_lo, ttmp15, v3        ; encoding: [0x05,0x00,0x11,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x11,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_bfe_i32 v5, vcc_hi, 0xaf123456, v255  ; encoding: [0x05,0x00,0x11,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x11,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_bfe_i32 v5, ttmp15, src_scc, ttmp15   ; encoding: [0x05,0x00,0x11,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x11,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_bfe_i32 v5, m0, 0.5, m0               ; encoding: [0x05,0x00,0x11,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x11,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_bfe_i32 v5, exec_lo, -1, vcc_hi       ; encoding: [0x05,0x00,0x11,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x11,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_bfe_i32 v5, exec_hi, null, vcc_lo     ; encoding: [0x05,0x00,0x11,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x11,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_bfe_i32 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x11,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x11,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_bfe_i32 v5, -1, exec_hi, src_scc      ; encoding: [0x05,0x00,0x11,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x11,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_bfe_i32 v5, 0.5, m0, 0.5              ; encoding: [0x05,0x00,0x11,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x11,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_bfe_i32 v5, src_scc, vcc_lo, -1       ; encoding: [0x05,0x00,0x11,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x11,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_bfe_i32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x11,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x11,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_bfe_u32 v5, v1, v2, s3                ; encoding: [0x05,0x00,0x10,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x10,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_bfe_u32 v5, v255, s2, s105            ; encoding: [0x05,0x00,0x10,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x10,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_bfe_u32 v5, s1, v255, exec_hi         ; encoding: [0x05,0x00,0x10,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x10,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_bfe_u32 v5, s105, s105, exec_lo       ; encoding: [0x05,0x00,0x10,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x10,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_bfe_u32 v5, vcc_lo, ttmp15, v3        ; encoding: [0x05,0x00,0x10,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x10,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_bfe_u32 v5, vcc_hi, 0xaf123456, v255  ; encoding: [0x05,0x00,0x10,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x10,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_bfe_u32 v5, ttmp15, src_scc, ttmp15   ; encoding: [0x05,0x00,0x10,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x10,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_bfe_u32 v5, m0, 0.5, m0               ; encoding: [0x05,0x00,0x10,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x10,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_bfe_u32 v5, exec_lo, -1, vcc_hi       ; encoding: [0x05,0x00,0x10,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x10,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_bfe_u32 v5, exec_hi, null, vcc_lo     ; encoding: [0x05,0x00,0x10,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x10,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_bfe_u32 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x10,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x10,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_bfe_u32 v5, -1, exec_hi, src_scc      ; encoding: [0x05,0x00,0x10,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x10,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_bfe_u32 v5, 0.5, m0, 0.5              ; encoding: [0x05,0x00,0x10,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x10,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_bfe_u32 v5, src_scc, vcc_lo, -1       ; encoding: [0x05,0x00,0x10,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x10,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_bfe_u32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x10,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x10,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_bfi_b32 v5, v1, v2, s3                ; encoding: [0x05,0x00,0x12,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x12,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_bfi_b32 v5, v255, s2, s105            ; encoding: [0x05,0x00,0x12,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x12,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_bfi_b32 v5, s1, v255, exec_hi         ; encoding: [0x05,0x00,0x12,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x12,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_bfi_b32 v5, s105, s105, exec_lo       ; encoding: [0x05,0x00,0x12,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x12,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_bfi_b32 v5, vcc_lo, ttmp15, v3        ; encoding: [0x05,0x00,0x12,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x12,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_bfi_b32 v5, vcc_hi, 0xaf123456, v255  ; encoding: [0x05,0x00,0x12,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x12,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_bfi_b32 v5, ttmp15, src_scc, ttmp15   ; encoding: [0x05,0x00,0x12,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x12,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_bfi_b32 v5, m0, 0.5, m0               ; encoding: [0x05,0x00,0x12,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x12,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_bfi_b32 v5, exec_lo, -1, vcc_hi       ; encoding: [0x05,0x00,0x12,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x12,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_bfi_b32 v5, exec_hi, null, vcc_lo     ; encoding: [0x05,0x00,0x12,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x12,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_bfi_b32 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x12,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x12,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_bfi_b32 v5, -1, exec_hi, src_scc      ; encoding: [0x05,0x00,0x12,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x12,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_bfi_b32 v5, 0.5, m0, 0.5              ; encoding: [0x05,0x00,0x12,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x12,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_bfi_b32 v5, src_scc, vcc_lo, -1       ; encoding: [0x05,0x00,0x12,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x12,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_bfi_b32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x12,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x12,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_bfm_b32 v5, v1, v2                    ; encoding: [0x05,0x00,0x1d,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x1d,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_bfm_b32 v5, v255, v255                ; encoding: [0x05,0x00,0x1d,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x1d,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_bfm_b32 v5, s1, s2                    ; encoding: [0x05,0x00,0x1d,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x1d,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_bfm_b32 v5, s105, s105                ; encoding: [0x05,0x00,0x1d,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x1d,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_bfm_b32 v5, vcc_lo, ttmp15            ; encoding: [0x05,0x00,0x1d,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x1d,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_bfm_b32 v5, vcc_hi, 0xaf123456        ; encoding: [0x05,0x00,0x1d,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x1d,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_bfm_b32 v5, ttmp15, src_scc           ; encoding: [0x05,0x00,0x1d,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x1d,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_bfm_b32 v5, m0, 0.5                   ; encoding: [0x05,0x00,0x1d,0xd7,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x1d,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_bfm_b32 v5, exec_lo, -1               ; encoding: [0x05,0x00,0x1d,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x1d,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_bfm_b32 v5, exec_hi, null             ; encoding: [0x05,0x00,0x1d,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x1d,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_bfm_b32 v5, null, exec_lo             ; encoding: [0x05,0x00,0x1d,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x1d,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_bfm_b32 v5, -1, exec_hi               ; encoding: [0x05,0x00,0x1d,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x1d,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_bfm_b32 v5, 0.5, m0                   ; encoding: [0x05,0x00,0x1d,0xd7,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x1d,0xd7,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_bfm_b32 v5, src_scc, vcc_lo           ; encoding: [0x05,0x00,0x1d,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x1d,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_bfm_b32 v255, 0xaf123456, vcc_hi      ; encoding: [0xff,0x00,0x1d,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x1d,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cndmask_b16 v5, v1, src_scc, s6         ; encoding: [0x05,0x00,0x5d,0xd6,0x01,0xfb,0x19,0x00]
+# W64: v_cndmask_b16 v5, v1, src_scc, s[6:7]     ; encoding: [0x05,0x00,0x5d,0xd6,0x01,0xfb,0x19,0x00]
+0x05,0x00,0x5d,0xd6,0x01,0xfb,0x19,0x00
+
+# W32: v_cndmask_b16 v5, v255, 0x3800, s6        ; encoding: [0x05,0x00,0x5d,0xd6,0xff,0xff,0x19,0x00,0x00,0x38,0x00,0x00]
+# W64: v_cndmask_b16 v5, v255, 0x3800, s[6:7]    ; encoding: [0x05,0x00,0x5d,0xd6,0xff,0xff,0x19,0x00,0x00,0x38,0x00,0x00]
+0x05,0x00,0x5d,0xd6,0xff,0xe1,0x19,0x00
+
+# W32: v_cndmask_b16 v5, s105, s105, s6          ; encoding: [0x05,0x00,0x5d,0xd6,0x69,0xd2,0x18,0x00]
+# W64: v_cndmask_b16 v5, s105, s105, s[6:7]      ; encoding: [0x05,0x00,0x5d,0xd6,0x69,0xd2,0x18,0x00]
+0x05,0x00,0x5d,0xd6,0x69,0xd2,0x18,0x00
+
+# W32: v_cndmask_b16 v5, vcc_hi, v2, s6          ; encoding: [0x05,0x00,0x5d,0xd6,0x6b,0x04,0x1a,0x00]
+# W64: v_cndmask_b16 v5, vcc_hi, v2, s[6:7]      ; encoding: [0x05,0x00,0x5d,0xd6,0x6b,0x04,0x1a,0x00]
+0x05,0x00,0x5d,0xd6,0x6b,0x04,0x1a,0x00
+
+# W32: v_cndmask_b16 v5, ttmp15, ttmp15, s6      ; encoding: [0x05,0x00,0x5d,0xd6,0x7b,0xf6,0x18,0x00]
+# W64: v_cndmask_b16 v5, ttmp15, ttmp15, s[6:7]  ; encoding: [0x05,0x00,0x5d,0xd6,0x7b,0xf6,0x18,0x00]
+0x05,0x00,0x5d,0xd6,0x7b,0xf6,0x18,0x00
+
+# W32: v_cndmask_b16 v5, m0, v255, s6            ; encoding: [0x05,0x00,0x5d,0xd6,0x7d,0xfe,0x1b,0x00]
+# W64: v_cndmask_b16 v5, m0, v255, s[6:7]        ; encoding: [0x05,0x00,0x5d,0xd6,0x7d,0xfe,0x1b,0x00]
+0x05,0x00,0x5d,0xd6,0x7d,0xfe,0x1b,0x00
+
+# W32: v_cndmask_b16 v5, exec_lo, exec_lo, s6    ; encoding: [0x05,0x00,0x5d,0xd6,0x7e,0xfc,0x18,0x00]
+# W64: v_cndmask_b16 v5, exec_lo, exec_lo, s[6:7] ; encoding: [0x05,0x00,0x5d,0xd6,0x7e,0xfc,0x18,0x00]
+0x05,0x00,0x5d,0xd6,0x7e,0xfc,0x18,0x00
+
+# W32: v_cndmask_b16 v5, exec_hi, exec_hi, s6    ; encoding: [0x05,0x00,0x5d,0xd6,0x7f,0xfe,0x18,0x00]
+# W64: v_cndmask_b16 v5, exec_hi, exec_hi, s[6:7] ; encoding: [0x05,0x00,0x5d,0xd6,0x7f,0xfe,0x18,0x00]
+0x05,0x00,0x5d,0xd6,0x7f,0xfe,0x18,0x00
+
+# W32: v_cndmask_b16 v5, null, m0, s6            ; encoding: [0x05,0x00,0x5d,0xd6,0x7c,0xfa,0x18,0x00]
+# W64: v_cndmask_b16 v5, null, m0, s[6:7]        ; encoding: [0x05,0x00,0x5d,0xd6,0x7c,0xfa,0x18,0x00]
+0x05,0x00,0x5d,0xd6,0x7c,0xfa,0x18,0x00
+
+# W32: v_cndmask_b16 v5, -1, -|vcc_lo|, s104     ; encoding: [0x05,0x02,0x5d,0xd6,0xc1,0xd4,0xa0,0x41]
+# W64: v_cndmask_b16 v5, -1, -|vcc_lo|, s[104:105] ; encoding: [0x05,0x02,0x5d,0xd6,0xc1,0xd4,0xa0,0x41]
+0x05,0x02,0x5d,0xd6,0xc1,0xd4,0xa0,0x41
+
+# W32: v_cndmask_b16 v5, 0x3800, -1, vcc_lo      ; encoding: [0x05,0x00,0x5d,0xd6,0xff,0x82,0xa9,0x01,0x00,0x38,0x00,0x00]
+# W64: v_cndmask_b16 v5, 0x3800, -1, vcc         ; encoding: [0x05,0x00,0x5d,0xd6,0xff,0x82,0xa9,0x01,0x00,0x38,0x00,0x00]
+0x05,0x00,0x5d,0xd6,0xf0,0x82,0xa9,0x01
+
+# W32: v_cndmask_b16 v5, -|src_scc|, null, ttmp14 ; encoding: [0x05,0x01,0x5d,0xd6,0xfd,0xf8,0xe8,0x21]
+# W64: v_cndmask_b16 v5, -|src_scc|, null, ttmp[14:15] ; encoding: [0x05,0x01,0x5d,0xd6,0xfd,0xf8,0xe8,0x21]
+0x05,0x01,0x5d,0xd6,0xfd,0xf8,0xe8,0x21
+
+# GFX12: v_cndmask_b16 v255, -|0xfe0b|, -|vcc_hi|, null ; encoding: [0xff,0x03,0x5d,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
+0xff,0x03,0x5d,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cubeid_f32 v5, v1, v2, s3             ; encoding: [0x05,0x00,0x0c,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x0c,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_cubeid_f32 v5, v255, s2, s105         ; encoding: [0x05,0x00,0x0c,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x0c,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_cubeid_f32 v5, s1, v255, exec_hi      ; encoding: [0x05,0x00,0x0c,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x0c,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_cubeid_f32 v5, s105, s105, exec_lo    ; encoding: [0x05,0x00,0x0c,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x0c,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_cubeid_f32 v5, vcc_lo, ttmp15, v3     ; encoding: [0x05,0x00,0x0c,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x0c,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_cubeid_f32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x0c,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x0c,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cubeid_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x0c,0xd6,0x7b,0xfa,0xed,0xe1]
+0x05,0x07,0x0c,0xd6,0x7b,0xfa,0xed,0xe1
+
+# GFX12: v_cubeid_f32 v5, m0, 0.5, m0            ; encoding: [0x05,0x00,0x0c,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x0c,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_cubeid_f32 v5, |exec_lo|, -1, vcc_hi  ; encoding: [0x05,0x01,0x0c,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x01,0x0c,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_cubeid_f32 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x0c,0xd6,0x7f,0xf8,0xa8,0xa1]
+0x05,0x05,0x0c,0xd6,0x7f,0xf8,0xa8,0xa1
+
+# GFX12: v_cubeid_f32 v5, null, exec_lo, -|0xaf123456| ; encoding: [0x05,0x04,0x0c,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+0x05,0x04,0x0c,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cubeid_f32 v5, -1, -|exec_hi|, -|src_scc| ; encoding: [0x05,0x06,0x0c,0xd6,0xc1,0xfe,0xf4,0xc3]
+0x05,0x06,0x0c,0xd6,0xc1,0xfe,0xf4,0xc3
+
+# GFX12: v_cubeid_f32 v5, 0.5, -m0, 0.5 mul:2    ; encoding: [0x05,0x00,0x0c,0xd6,0xf0,0xfa,0xc0,0x4b]
+0x05,0x00,0x0c,0xd6,0xf0,0xfa,0xc0,0x4b
+
+# GFX12: v_cubeid_f32 v5, -src_scc, |vcc_lo|, -1 mul:4 ; encoding: [0x05,0x02,0x0c,0xd6,0xfd,0xd4,0x04,0x33]
+0x05,0x02,0x0c,0xd6,0xfd,0xd4,0x04,0x33
+
+# GFX12: v_cubeid_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2 ; encoding: [0xff,0x83,0x0c,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+0xff,0x83,0x0c,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cubema_f32 v5, v1, v2, s3             ; encoding: [0x05,0x00,0x0f,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x0f,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_cubema_f32 v5, v255, s2, s105         ; encoding: [0x05,0x00,0x0f,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x0f,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_cubema_f32 v5, s1, v255, exec_hi      ; encoding: [0x05,0x00,0x0f,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x0f,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_cubema_f32 v5, s105, s105, exec_lo    ; encoding: [0x05,0x00,0x0f,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x0f,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_cubema_f32 v5, vcc_lo, ttmp15, v3     ; encoding: [0x05,0x00,0x0f,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x0f,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_cubema_f32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x0f,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x0f,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cubema_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x0f,0xd6,0x7b,0xfa,0xed,0xe1]
+0x05,0x07,0x0f,0xd6,0x7b,0xfa,0xed,0xe1
+
+# GFX12: v_cubema_f32 v5, m0, 0.5, m0            ; encoding: [0x05,0x00,0x0f,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x0f,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_cubema_f32 v5, |exec_lo|, -1, vcc_hi  ; encoding: [0x05,0x01,0x0f,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x01,0x0f,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_cubema_f32 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x0f,0xd6,0x7f,0xf8,0xa8,0xa1]
+0x05,0x05,0x0f,0xd6,0x7f,0xf8,0xa8,0xa1
+
+# GFX12: v_cubema_f32 v5, null, exec_lo, -|0xaf123456| ; encoding: [0x05,0x04,0x0f,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+0x05,0x04,0x0f,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cubema_f32 v5, -1, -|exec_hi|, -|src_scc| ; encoding: [0x05,0x06,0x0f,0xd6,0xc1,0xfe,0xf4,0xc3]
+0x05,0x06,0x0f,0xd6,0xc1,0xfe,0xf4,0xc3
+
+# GFX12: v_cubema_f32 v5, 0.5, -m0, 0.5 mul:2    ; encoding: [0x05,0x00,0x0f,0xd6,0xf0,0xfa,0xc0,0x4b]
+0x05,0x00,0x0f,0xd6,0xf0,0xfa,0xc0,0x4b
+
+# GFX12: v_cubema_f32 v5, -src_scc, |vcc_lo|, -1 mul:4 ; encoding: [0x05,0x02,0x0f,0xd6,0xfd,0xd4,0x04,0x33]
+0x05,0x02,0x0f,0xd6,0xfd,0xd4,0x04,0x33
+
+# GFX12: v_cubema_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2 ; encoding: [0xff,0x83,0x0f,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+0xff,0x83,0x0f,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cubesc_f32 v5, v1, v2, s3             ; encoding: [0x05,0x00,0x0d,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x0d,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_cubesc_f32 v5, v255, s2, s105         ; encoding: [0x05,0x00,0x0d,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x0d,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_cubesc_f32 v5, s1, v255, exec_hi      ; encoding: [0x05,0x00,0x0d,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x0d,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_cubesc_f32 v5, s105, s105, exec_lo    ; encoding: [0x05,0x00,0x0d,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x0d,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_cubesc_f32 v5, vcc_lo, ttmp15, v3     ; encoding: [0x05,0x00,0x0d,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x0d,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_cubesc_f32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x0d,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x0d,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cubesc_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x0d,0xd6,0x7b,0xfa,0xed,0xe1]
+0x05,0x07,0x0d,0xd6,0x7b,0xfa,0xed,0xe1
+
+# GFX12: v_cubesc_f32 v5, m0, 0.5, m0            ; encoding: [0x05,0x00,0x0d,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x0d,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_cubesc_f32 v5, |exec_lo|, -1, vcc_hi  ; encoding: [0x05,0x01,0x0d,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x01,0x0d,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_cubesc_f32 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x0d,0xd6,0x7f,0xf8,0xa8,0xa1]
+0x05,0x05,0x0d,0xd6,0x7f,0xf8,0xa8,0xa1
+
+# GFX12: v_cubesc_f32 v5, null, exec_lo, -|0xaf123456| ; encoding: [0x05,0x04,0x0d,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+0x05,0x04,0x0d,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cubesc_f32 v5, -1, -|exec_hi|, -|src_scc| ; encoding: [0x05,0x06,0x0d,0xd6,0xc1,0xfe,0xf4,0xc3]
+0x05,0x06,0x0d,0xd6,0xc1,0xfe,0xf4,0xc3
+
+# GFX12: v_cubesc_f32 v5, 0.5, -m0, 0.5 mul:2    ; encoding: [0x05,0x00,0x0d,0xd6,0xf0,0xfa,0xc0,0x4b]
+0x05,0x00,0x0d,0xd6,0xf0,0xfa,0xc0,0x4b
+
+# GFX12: v_cubesc_f32 v5, -src_scc, |vcc_lo|, -1 mul:4 ; encoding: [0x05,0x02,0x0d,0xd6,0xfd,0xd4,0x04,0x33]
+0x05,0x02,0x0d,0xd6,0xfd,0xd4,0x04,0x33
+
+# GFX12: v_cubesc_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2 ; encoding: [0xff,0x83,0x0d,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+0xff,0x83,0x0d,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cubetc_f32 v5, v1, v2, s3             ; encoding: [0x05,0x00,0x0e,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x0e,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_cubetc_f32 v5, v255, s2, s105         ; encoding: [0x05,0x00,0x0e,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x0e,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_cubetc_f32 v5, s1, v255, exec_hi      ; encoding: [0x05,0x00,0x0e,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x0e,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_cubetc_f32 v5, s105, s105, exec_lo    ; encoding: [0x05,0x00,0x0e,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x0e,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_cubetc_f32 v5, vcc_lo, ttmp15, v3     ; encoding: [0x05,0x00,0x0e,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x0e,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_cubetc_f32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x0e,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x0e,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cubetc_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x0e,0xd6,0x7b,0xfa,0xed,0xe1]
+0x05,0x07,0x0e,0xd6,0x7b,0xfa,0xed,0xe1
+
+# GFX12: v_cubetc_f32 v5, m0, 0.5, m0            ; encoding: [0x05,0x00,0x0e,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x0e,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_cubetc_f32 v5, |exec_lo|, -1, vcc_hi  ; encoding: [0x05,0x01,0x0e,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x01,0x0e,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_cubetc_f32 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x0e,0xd6,0x7f,0xf8,0xa8,0xa1]
+0x05,0x05,0x0e,0xd6,0x7f,0xf8,0xa8,0xa1
+
+# GFX12: v_cubetc_f32 v5, null, exec_lo, -|0xaf123456| ; encoding: [0x05,0x04,0x0e,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+0x05,0x04,0x0e,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cubetc_f32 v5, -1, -|exec_hi|, -|src_scc| ; encoding: [0x05,0x06,0x0e,0xd6,0xc1,0xfe,0xf4,0xc3]
+0x05,0x06,0x0e,0xd6,0xc1,0xfe,0xf4,0xc3
+
+# GFX12: v_cubetc_f32 v5, 0.5, -m0, 0.5 mul:2    ; encoding: [0x05,0x00,0x0e,0xd6,0xf0,0xfa,0xc0,0x4b]
+0x05,0x00,0x0e,0xd6,0xf0,0xfa,0xc0,0x4b
+
+# GFX12: v_cubetc_f32 v5, -src_scc, |vcc_lo|, -1 mul:4 ; encoding: [0x05,0x02,0x0e,0xd6,0xfd,0xd4,0x04,0x33]
+0x05,0x02,0x0e,0xd6,0xfd,0xd4,0x04,0x33
+
+# GFX12: v_cubetc_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2 ; encoding: [0xff,0x83,0x0e,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+0xff,0x83,0x0e,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_pk_i16_f32 v5, v1, v2             ; encoding: [0x05,0x00,0x06,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x06,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_cvt_pk_i16_f32 v5, v255, v255         ; encoding: [0x05,0x00,0x06,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x06,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_cvt_pk_i16_f32 v5, s1, s2             ; encoding: [0x05,0x00,0x06,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x06,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_cvt_pk_i16_f32 v5, s105, s105         ; encoding: [0x05,0x00,0x06,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x06,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cvt_pk_i16_f32 v5, vcc_lo, ttmp15     ; encoding: [0x05,0x00,0x06,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x06,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cvt_pk_i16_f32 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x06,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x06,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_pk_i16_f32 v5, ttmp15, src_scc    ; encoding: [0x05,0x00,0x06,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x06,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cvt_pk_i16_f32 v5, m0, 0.5            ; encoding: [0x05,0x00,0x06,0xd7,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x06,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cvt_pk_i16_f32 v5, exec_lo, -1        ; encoding: [0x05,0x00,0x06,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x06,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cvt_pk_i16_f32 v5, |exec_hi|, null    ; encoding: [0x05,0x01,0x06,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x01,0x06,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cvt_pk_i16_f32 v5, null, exec_lo      ; encoding: [0x05,0x00,0x06,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x06,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cvt_pk_i16_f32 v5, -1, exec_hi        ; encoding: [0x05,0x00,0x06,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x06,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cvt_pk_i16_f32 v5, 0.5, -m0           ; encoding: [0x05,0x00,0x06,0xd7,0xf0,0xfa,0x00,0x40]
+0x05,0x00,0x06,0xd7,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cvt_pk_i16_f32 v5, -src_scc, |vcc_lo| ; encoding: [0x05,0x02,0x06,0xd7,0xfd,0xd4,0x00,0x20]
+0x05,0x02,0x06,0xd7,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cvt_pk_i16_f32 v255, -|0xaf123456|, -|vcc_hi| ; encoding: [0xff,0x03,0x06,0xd7,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0xff,0x03,0x06,0xd7,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_pk_i16_i32 v5, v1, v2             ; encoding: [0x05,0x00,0x24,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x24,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_cvt_pk_i16_i32 v5, v255, v255         ; encoding: [0x05,0x00,0x24,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x24,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_cvt_pk_i16_i32 v5, s1, s2             ; encoding: [0x05,0x00,0x24,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x24,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_cvt_pk_i16_i32 v5, s105, s105         ; encoding: [0x05,0x00,0x24,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x24,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cvt_pk_i16_i32 v5, vcc_lo, ttmp15     ; encoding: [0x05,0x00,0x24,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x24,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cvt_pk_i16_i32 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x24,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x24,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_pk_i16_i32 v5, ttmp15, src_scc    ; encoding: [0x05,0x00,0x24,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x24,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cvt_pk_i16_i32 v5, m0, 0.5            ; encoding: [0x05,0x00,0x24,0xd7,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x24,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cvt_pk_i16_i32 v5, exec_lo, -1        ; encoding: [0x05,0x00,0x24,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x24,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cvt_pk_i16_i32 v5, exec_hi, null      ; encoding: [0x05,0x00,0x24,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x24,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cvt_pk_i16_i32 v5, null, exec_lo      ; encoding: [0x05,0x00,0x24,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x24,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cvt_pk_i16_i32 v5, -1, exec_hi        ; encoding: [0x05,0x00,0x24,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x24,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cvt_pk_i16_i32 v5, 0.5, m0            ; encoding: [0x05,0x00,0x24,0xd7,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x24,0xd7,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_cvt_pk_i16_i32 v5, src_scc, vcc_lo    ; encoding: [0x05,0x00,0x24,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x24,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cvt_pk_i16_i32 v255, 0xaf123456, vcc_hi ; encoding: [0xff,0x00,0x24,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x24,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_pk_norm_i16_f16 v5, v1, v2        ; encoding: [0x05,0x00,0x12,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x12,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_cvt_pk_norm_i16_f16 v5, v255, v255    ; encoding: [0x05,0x00,0x12,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x12,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_cvt_pk_norm_i16_f16 v5, s1, s2        ; encoding: [0x05,0x00,0x12,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x12,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_i16_f16 v5, s105, s105    ; encoding: [0x05,0x00,0x12,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x12,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_i16_f16 v5, vcc_lo, ttmp15 ; encoding: [0x05,0x00,0x12,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x12,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_i16_f16 v5, vcc_hi, 0xfe0b ; encoding: [0x05,0x00,0x12,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x12,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_i16_f16 v5, ttmp15, src_scc ; encoding: [0x05,0x00,0x12,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x12,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cvt_pk_norm_i16_f16 v5, m0, 0.5       ; encoding: [0x05,0x00,0x12,0xd7,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x12,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cvt_pk_norm_i16_f16 v5, exec_lo, -1   ; encoding: [0x05,0x00,0x12,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x12,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cvt_pk_norm_i16_f16 v5, |exec_hi|, null ; encoding: [0x05,0x01,0x12,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x01,0x12,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_i16_f16 v5, null, exec_lo ; encoding: [0x05,0x00,0x12,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x12,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_i16_f16 v5, -1, exec_hi   ; encoding: [0x05,0x00,0x12,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x12,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_i16_f16 v5, 0.5, -m0      ; encoding: [0x05,0x00,0x12,0xd7,0xf0,0xfa,0x00,0x40]
+0x05,0x00,0x12,0xd7,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cvt_pk_norm_i16_f16 v5, -src_scc, |vcc_lo| op_sel:[1,0,0] ; encoding: [0x05,0x0a,0x12,0xd7,0xfd,0xd4,0x00,0x20]
+0x05,0x0a,0x12,0xd7,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cvt_pk_norm_i16_f16 v255, -|0xfe0b|, -|vcc_hi| op_sel:[0,1,0] ; encoding: [0xff,0x13,0x12,0xd7,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0xff,0x13,0x12,0xd7,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_u16_f16 v5, v1, v2        ; encoding: [0x05,0x00,0x13,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x13,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_cvt_pk_norm_u16_f16 v5, v255, v255    ; encoding: [0x05,0x00,0x13,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x13,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_cvt_pk_norm_u16_f16 v5, s1, s2        ; encoding: [0x05,0x00,0x13,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x13,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_u16_f16 v5, s105, s105    ; encoding: [0x05,0x00,0x13,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x13,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_u16_f16 v5, vcc_lo, ttmp15 ; encoding: [0x05,0x00,0x13,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x13,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_u16_f16 v5, vcc_hi, 0xfe0b ; encoding: [0x05,0x00,0x13,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x13,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_u16_f16 v5, ttmp15, src_scc ; encoding: [0x05,0x00,0x13,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x13,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cvt_pk_norm_u16_f16 v5, m0, 0.5       ; encoding: [0x05,0x00,0x13,0xd7,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x13,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cvt_pk_norm_u16_f16 v5, exec_lo, -1   ; encoding: [0x05,0x00,0x13,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x13,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cvt_pk_norm_u16_f16 v5, |exec_hi|, null ; encoding: [0x05,0x01,0x13,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x01,0x13,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_u16_f16 v5, null, exec_lo ; encoding: [0x05,0x00,0x13,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x13,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_u16_f16 v5, -1, exec_hi   ; encoding: [0x05,0x00,0x13,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x13,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_u16_f16 v5, 0.5, -m0      ; encoding: [0x05,0x00,0x13,0xd7,0xf0,0xfa,0x00,0x40]
+0x05,0x00,0x13,0xd7,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cvt_pk_norm_u16_f16 v5, -src_scc, |vcc_lo| op_sel:[1,0,0] ; encoding: [0x05,0x0a,0x13,0xd7,0xfd,0xd4,0x00,0x20]
+0x05,0x0a,0x13,0xd7,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cvt_pk_norm_u16_f16 v255, -|0xfe0b|, -|vcc_hi| op_sel:[0,1,0] ; encoding: [0xff,0x13,0x13,0xd7,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0xff,0x13,0x13,0xd7,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cvt_pk_u16_f32 v5, v1, v2             ; encoding: [0x05,0x00,0x07,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x07,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_cvt_pk_u16_f32 v5, v255, v255         ; encoding: [0x05,0x00,0x07,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x07,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_cvt_pk_u16_f32 v5, s1, s2             ; encoding: [0x05,0x00,0x07,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x07,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_cvt_pk_u16_f32 v5, s105, s105         ; encoding: [0x05,0x00,0x07,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x07,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cvt_pk_u16_f32 v5, vcc_lo, ttmp15     ; encoding: [0x05,0x00,0x07,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x07,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cvt_pk_u16_f32 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x07,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x07,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_pk_u16_f32 v5, ttmp15, src_scc    ; encoding: [0x05,0x00,0x07,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x07,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cvt_pk_u16_f32 v5, m0, 0.5            ; encoding: [0x05,0x00,0x07,0xd7,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x07,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cvt_pk_u16_f32 v5, exec_lo, -1        ; encoding: [0x05,0x00,0x07,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x07,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cvt_pk_u16_f32 v5, |exec_hi|, null    ; encoding: [0x05,0x01,0x07,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x01,0x07,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cvt_pk_u16_f32 v5, null, exec_lo      ; encoding: [0x05,0x00,0x07,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x07,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cvt_pk_u16_f32 v5, -1, exec_hi        ; encoding: [0x05,0x00,0x07,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x07,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cvt_pk_u16_f32 v5, 0.5, -m0           ; encoding: [0x05,0x00,0x07,0xd7,0xf0,0xfa,0x00,0x40]
+0x05,0x00,0x07,0xd7,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cvt_pk_u16_f32 v5, -src_scc, |vcc_lo| ; encoding: [0x05,0x02,0x07,0xd7,0xfd,0xd4,0x00,0x20]
+0x05,0x02,0x07,0xd7,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cvt_pk_u16_f32 v255, -|0xaf123456|, -|vcc_hi| ; encoding: [0xff,0x03,0x07,0xd7,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0xff,0x03,0x07,0xd7,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_pk_u16_u32 v5, v1, v2             ; encoding: [0x05,0x00,0x23,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x23,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_cvt_pk_u16_u32 v5, v255, v255         ; encoding: [0x05,0x00,0x23,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x23,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_cvt_pk_u16_u32 v5, s1, s2             ; encoding: [0x05,0x00,0x23,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x23,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_cvt_pk_u16_u32 v5, s105, s105         ; encoding: [0x05,0x00,0x23,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x23,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cvt_pk_u16_u32 v5, vcc_lo, ttmp15     ; encoding: [0x05,0x00,0x23,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x23,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cvt_pk_u16_u32 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x23,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x23,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_pk_u16_u32 v5, ttmp15, src_scc    ; encoding: [0x05,0x00,0x23,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x23,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cvt_pk_u16_u32 v5, m0, 0.5            ; encoding: [0x05,0x00,0x23,0xd7,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x23,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cvt_pk_u16_u32 v5, exec_lo, -1        ; encoding: [0x05,0x00,0x23,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x23,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cvt_pk_u16_u32 v5, exec_hi, null      ; encoding: [0x05,0x00,0x23,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x23,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cvt_pk_u16_u32 v5, null, exec_lo      ; encoding: [0x05,0x00,0x23,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x23,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cvt_pk_u16_u32 v5, -1, exec_hi        ; encoding: [0x05,0x00,0x23,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x23,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cvt_pk_u16_u32 v5, 0.5, m0            ; encoding: [0x05,0x00,0x23,0xd7,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x23,0xd7,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_cvt_pk_u16_u32 v5, src_scc, vcc_lo    ; encoding: [0x05,0x00,0x23,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x23,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cvt_pk_u16_u32 v255, 0xaf123456, vcc_hi ; encoding: [0xff,0x00,0x23,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x23,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_pk_u8_f32 v5, v1, v2, s3          ; encoding: [0x05,0x00,0x26,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x26,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_cvt_pk_u8_f32 v5, v255, s2, s105      ; encoding: [0x05,0x00,0x26,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x26,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_cvt_pk_u8_f32 v5, s1, v255, exec_hi   ; encoding: [0x05,0x00,0x26,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x26,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_cvt_pk_u8_f32 v5, s105, s105, exec_lo ; encoding: [0x05,0x00,0x26,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x26,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_cvt_pk_u8_f32 v5, vcc_lo, ttmp15, v3  ; encoding: [0x05,0x00,0x26,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x26,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_cvt_pk_u8_f32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x26,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x26,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_pk_u8_f32 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x00,0x26,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x26,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_cvt_pk_u8_f32 v5, m0, 0.5, m0         ; encoding: [0x05,0x00,0x26,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x26,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_cvt_pk_u8_f32 v5, exec_lo, -1, vcc_hi ; encoding: [0x05,0x00,0x26,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x26,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_cvt_pk_u8_f32 v5, exec_hi, null, vcc_lo ; encoding: [0x05,0x00,0x26,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x26,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_cvt_pk_u8_f32 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x26,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x26,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_pk_u8_f32 v5, -1, exec_hi, src_scc ; encoding: [0x05,0x00,0x26,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x26,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_cvt_pk_u8_f32 v5, 0.5, m0, 0.5        ; encoding: [0x05,0x00,0x26,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x26,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_cvt_pk_u8_f32 v5, src_scc, vcc_lo, -1 ; encoding: [0x05,0x00,0x26,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x26,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_cvt_pk_u8_f32 v255, -|0xaf123456|, vcc_hi, null ; encoding: [0xff,0x01,0x26,0xd6,0xff,0xd6,0xf0,0x21,0x56,0x34,0x12,0xaf]
+0xff,0x01,0x26,0xd6,0xff,0xd6,0xf0,0x21,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_pk_norm_i16_f32 v5, v1, v2        ; encoding: [0x05,0x00,0x21,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x21,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_cvt_pk_norm_i16_f32 v5, v255, v255    ; encoding: [0x05,0x00,0x21,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x21,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_cvt_pk_norm_i16_f32 v5, s1, s2        ; encoding: [0x05,0x00,0x21,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x21,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_i16_f32 v5, s105, s105    ; encoding: [0x05,0x00,0x21,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x21,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_i16_f32 v5, vcc_lo, ttmp15 ; encoding: [0x05,0x00,0x21,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x21,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_i16_f32 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x21,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x21,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_pk_norm_i16_f32 v5, ttmp15, src_scc ; encoding: [0x05,0x00,0x21,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x21,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cvt_pk_norm_i16_f32 v5, m0, 0.5       ; encoding: [0x05,0x00,0x21,0xd7,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x21,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cvt_pk_norm_i16_f32 v5, exec_lo, -1   ; encoding: [0x05,0x00,0x21,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x21,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cvt_pk_norm_i16_f32 v5, |exec_hi|, null ; encoding: [0x05,0x01,0x21,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x01,0x21,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_i16_f32 v5, null, exec_lo ; encoding: [0x05,0x00,0x21,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x21,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_i16_f32 v5, -1, exec_hi   ; encoding: [0x05,0x00,0x21,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x21,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_i16_f32 v5, 0.5, -m0      ; encoding: [0x05,0x00,0x21,0xd7,0xf0,0xfa,0x00,0x40]
+0x05,0x00,0x21,0xd7,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cvt_pk_norm_i16_f32 v5, -src_scc, |vcc_lo| ; encoding: [0x05,0x02,0x21,0xd7,0xfd,0xd4,0x00,0x20]
+0x05,0x02,0x21,0xd7,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cvt_pk_norm_i16_f32 v255, -|0xaf123456|, -|vcc_hi| ; encoding: [0xff,0x03,0x21,0xd7,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0xff,0x03,0x21,0xd7,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_pk_norm_u16_f32 v5, v1, v2        ; encoding: [0x05,0x00,0x22,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x22,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_cvt_pk_norm_u16_f32 v5, v255, v255    ; encoding: [0x05,0x00,0x22,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x22,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_cvt_pk_norm_u16_f32 v5, s1, s2        ; encoding: [0x05,0x00,0x22,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x22,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_u16_f32 v5, s105, s105    ; encoding: [0x05,0x00,0x22,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x22,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_u16_f32 v5, vcc_lo, ttmp15 ; encoding: [0x05,0x00,0x22,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x22,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_u16_f32 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x22,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x22,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_pk_norm_u16_f32 v5, ttmp15, src_scc ; encoding: [0x05,0x00,0x22,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x22,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cvt_pk_norm_u16_f32 v5, m0, 0.5       ; encoding: [0x05,0x00,0x22,0xd7,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x22,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cvt_pk_norm_u16_f32 v5, exec_lo, -1   ; encoding: [0x05,0x00,0x22,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x22,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cvt_pk_norm_u16_f32 v5, |exec_hi|, null ; encoding: [0x05,0x01,0x22,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x01,0x22,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_u16_f32 v5, null, exec_lo ; encoding: [0x05,0x00,0x22,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x22,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_u16_f32 v5, -1, exec_hi   ; encoding: [0x05,0x00,0x22,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x22,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_u16_f32 v5, 0.5, -m0      ; encoding: [0x05,0x00,0x22,0xd7,0xf0,0xfa,0x00,0x40]
+0x05,0x00,0x22,0xd7,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cvt_pk_norm_u16_f32 v5, -src_scc, |vcc_lo| ; encoding: [0x05,0x02,0x22,0xd7,0xfd,0xd4,0x00,0x20]
+0x05,0x02,0x22,0xd7,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cvt_pk_norm_u16_f32 v255, -|0xaf123456|, -|vcc_hi| ; encoding: [0xff,0x03,0x22,0xd7,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0xff,0x03,0x22,0xd7,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# GFX12: v_div_fixup_f16 v5, v1, v2, s3          ; encoding: [0x05,0x00,0x54,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x54,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_div_fixup_f16 v5, v255, s2, s105      ; encoding: [0x05,0x00,0x54,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x54,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_div_fixup_f16 v5, s1, v255, exec_hi   ; encoding: [0x05,0x00,0x54,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x54,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_div_fixup_f16 v5, s105, s105, exec_lo ; encoding: [0x05,0x00,0x54,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x54,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_div_fixup_f16 v5, vcc_lo, ttmp15, v3  ; encoding: [0x05,0x00,0x54,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x54,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_div_fixup_f16 v5, vcc_hi, 0xfe0b, v255 ; encoding: [0x05,0x00,0x54,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x54,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_div_fixup_f16 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x54,0xd6,0x7b,0xfa,0xed,0xe1]
+0x05,0x07,0x54,0xd6,0x7b,0xfa,0xed,0xe1
+
+# GFX12: v_div_fixup_f16 v5, m0, 0.5, m0         ; encoding: [0x05,0x00,0x54,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x54,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_div_fixup_f16 v5, |exec_lo|, -1, vcc_hi ; encoding: [0x05,0x01,0x54,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x01,0x54,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_div_fixup_f16 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x54,0xd6,0x7f,0xf8,0xa8,0xa1]
+0x05,0x05,0x54,0xd6,0x7f,0xf8,0xa8,0xa1
+
+# GFX12: v_div_fixup_f16 v5, null, exec_lo, -|0xfe0b| op_sel:[1,1,1,1] ; encoding: [0x05,0x7c,0x54,0xd6,0x7c,0xfc,0xfc,0x83,0x0b,0xfe,0x00,0x00]
+0x05,0x7c,0x54,0xd6,0x7c,0xfc,0xfc,0x83,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_div_fixup_f16 v5, -1, -|exec_hi|, -|src_scc| op_sel:[1,0,0,0] ; encoding: [0x05,0x0e,0x54,0xd6,0xc1,0xfe,0xf4,0xc3]
+0x05,0x0e,0x54,0xd6,0xc1,0xfe,0xf4,0xc3
+
+# GFX12: v_div_fixup_f16 v5, 0.5, -m0, 0.5 op_sel:[0,1,0,0] ; encoding: [0x05,0x10,0x54,0xd6,0xf0,0xfa,0xc0,0x43]
+0x05,0x10,0x54,0xd6,0xf0,0xfa,0xc0,0x43
+
+# GFX12: v_div_fixup_f16 v5, -src_scc, |vcc_lo|, -1 op_sel:[0,0,1,0] ; encoding: [0x05,0x22,0x54,0xd6,0xfd,0xd4,0x04,0x23]
+0x05,0x22,0x54,0xd6,0xfd,0xd4,0x04,0x23
+
+# GFX12: v_div_fixup_f16 v255, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] clamp ; encoding: [0xff,0xc3,0x54,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
+0xff,0xc3,0x54,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_div_fixup_f32 v5, v1, v2, s3          ; encoding: [0x05,0x00,0x27,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x27,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_div_fixup_f32 v5, v255, s2, s105      ; encoding: [0x05,0x00,0x27,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x27,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_div_fixup_f32 v5, s1, v255, exec_hi   ; encoding: [0x05,0x00,0x27,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x27,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_div_fixup_f32 v5, s105, s105, exec_lo ; encoding: [0x05,0x00,0x27,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x27,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_div_fixup_f32 v5, vcc_lo, ttmp15, v3  ; encoding: [0x05,0x00,0x27,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x27,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_div_fixup_f32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x27,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x27,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_div_fixup_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x27,0xd6,0x7b,0xfa,0xed,0xe1]
+0x05,0x07,0x27,0xd6,0x7b,0xfa,0xed,0xe1
+
+# GFX12: v_div_fixup_f32 v5, m0, 0.5, m0         ; encoding: [0x05,0x00,0x27,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x27,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_div_fixup_f32 v5, |exec_lo|, -1, vcc_hi ; encoding: [0x05,0x01,0x27,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x01,0x27,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_div_fixup_f32 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x27,0xd6,0x7f,0xf8,0xa8,0xa1]
+0x05,0x05,0x27,0xd6,0x7f,0xf8,0xa8,0xa1
+
+# GFX12: v_div_fixup_f32 v5, null, exec_lo, -|0xaf123456| ; encoding: [0x05,0x04,0x27,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+0x05,0x04,0x27,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf
+
+# GFX12: v_div_fixup_f32 v5, -1, -|exec_hi|, -|src_scc| ; encoding: [0x05,0x06,0x27,0xd6,0xc1,0xfe,0xf4,0xc3]
+0x05,0x06,0x27,0xd6,0xc1,0xfe,0xf4,0xc3
+
+# GFX12: v_div_fixup_f32 v5, 0.5, -m0, 0.5 mul:2 ; encoding: [0x05,0x00,0x27,0xd6,0xf0,0xfa,0xc0,0x4b]
+0x05,0x00,0x27,0xd6,0xf0,0xfa,0xc0,0x4b
+
+# GFX12: v_div_fixup_f32 v5, -src_scc, |vcc_lo|, -1 mul:4 ; encoding: [0x05,0x02,0x27,0xd6,0xfd,0xd4,0x04,0x33]
+0x05,0x02,0x27,0xd6,0xfd,0xd4,0x04,0x33
+
+# GFX12: v_div_fixup_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2 ; encoding: [0xff,0x83,0x27,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+0xff,0x83,0x27,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf
+
+# GFX12: v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] ; encoding: [0x05,0x00,0x28,0xd6,0x01,0x05,0x0e,0x04]
+0x05,0x00,0x28,0xd6,0x01,0x05,0x0e,0x04
+
+# GFX12: v_div_fixup_f64 v[5:6], v[254:255], v[254:255], s[6:7] ; encoding: [0x05,0x00,0x28,0xd6,0xfe,0xfd,0x1b,0x00]
+0x05,0x00,0x28,0xd6,0xfe,0xfd,0x1b,0x00
+
+# GFX12: v_div_fixup_f64 v[5:6], s[2:3], s[4:5], v[254:255] ; encoding: [0x05,0x00,0x28,0xd6,0x02,0x08,0xf8,0x07]
+0x05,0x00,0x28,0xd6,0x02,0x08,0xf8,0x07
+
+# GFX12: v_div_fixup_f64 v[5:6], -|s[104:105]|, s[104:105], -|s[104:105]| ; encoding: [0x05,0x05,0x28,0xd6,0x68,0xd0,0xa0,0xa1]
+0x05,0x05,0x28,0xd6,0x68,0xd0,0xa0,0xa1
+
+# GFX12: v_div_fixup_f64 v[5:6], vcc, -|ttmp[14:15]|, -|ttmp[14:15]| ; encoding: [0x05,0x06,0x28,0xd6,0x6a,0xf4,0xe8,0xc1]
+0x05,0x06,0x28,0xd6,0x6a,0xf4,0xe8,0xc1
+
+# GFX12: v_div_fixup_f64 v[5:6], -|ttmp[14:15]|, 0xaf123456, null ; encoding: [0x05,0x01,0x28,0xd6,0x7a,0xfe,0xf1,0x21,0x56,0x34,0x12,0xaf]
+0x05,0x01,0x28,0xd6,0x7a,0xfe,0xf1,0x21,0x56,0x34,0x12,0xaf
+
+# GFX12: v_div_fixup_f64 v[5:6], -|exec|, -|src_scc|, -|exec| ; encoding: [0x05,0x07,0x28,0xd6,0x7e,0xfa,0xf9,0xe1]
+0x05,0x07,0x28,0xd6,0x7e,0xfa,0xf9,0xe1
+
+# GFX12: v_div_fixup_f64 v[5:6], null, 0.5, vcc  ; encoding: [0x05,0x00,0x28,0xd6,0x7c,0xe0,0xa9,0x01]
+0x05,0x00,0x28,0xd6,0x7c,0xe0,0xa9,0x01
+
+# GFX12: v_div_fixup_f64 v[5:6], -1, -1, 0xaf123456 ; encoding: [0x05,0x00,0x28,0xd6,0xc1,0x82,0xfd,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x28,0xd6,0xc1,0x82,0xfd,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_div_fixup_f64 v[5:6], 0.5, null, -|src_scc| mul:2 ; encoding: [0x05,0x04,0x28,0xd6,0xf0,0xf8,0xf4,0x8b]
+0x05,0x04,0x28,0xd6,0xf0,0xf8,0xf4,0x8b
+
+# GFX12: v_div_fixup_f64 v[5:6], -|src_scc|, -|exec|, 0.5 mul:4 ; encoding: [0x05,0x03,0x28,0xd6,0xfd,0xfc,0xc0,0x73]
+0x05,0x03,0x28,0xd6,0xfd,0xfc,0xc0,0x73
+
+# GFX12: v_div_fixup_f64 v[254:255], 0xaf123456, -|vcc|, -1 clamp div:2 ; encoding: [0xfe,0x82,0x28,0xd6,0xff,0xd4,0x04,0x5b,0x56,0x34,0x12,0xaf]
+0xfe,0x82,0x28,0xd6,0xff,0xd4,0x04,0x5b,0x56,0x34,0x12,0xaf
+
+# GFX12: v_div_fmas_f32 v5, v1, 0xaf123456, 0xaf123456 ; encoding: [0x05,0x00,0x37,0xd6,0x01,0xff,0xfd,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x37,0xd6,0x01,0xff,0xfd,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_div_fmas_f32 v5, v255, src_scc, src_scc ; encoding: [0x05,0x00,0x37,0xd6,0xff,0xfb,0xf5,0x03]
+0x05,0x00,0x37,0xd6,0xff,0xfb,0xf5,0x03
+
+# GFX12: v_div_fmas_f32 v5, s105, s105, s105     ; encoding: [0x05,0x00,0x37,0xd6,0x69,0xd2,0xa4,0x01]
+0x05,0x00,0x37,0xd6,0x69,0xd2,0xa4,0x01
+
+# GFX12: v_div_fmas_f32 v5, vcc_lo, v2, v3       ; encoding: [0x05,0x00,0x37,0xd6,0x6a,0x04,0x0e,0x04]
+0x05,0x00,0x37,0xd6,0x6a,0x04,0x0e,0x04
+
+# GFX12: v_div_fmas_f32 v5, vcc_hi, v255, vcc_hi ; encoding: [0x05,0x00,0x37,0xd6,0x6b,0xfe,0xaf,0x01]
+0x05,0x00,0x37,0xd6,0x6b,0xfe,0xaf,0x01
+
+# GFX12: v_div_fmas_f32 v5, -|ttmp15|, -|ttmp15|, ttmp15 ; encoding: [0x05,0x03,0x37,0xd6,0x7b,0xf6,0xec,0x61]
+0x05,0x03,0x37,0xd6,0x7b,0xf6,0xec,0x61
+
+# GFX12: v_div_fmas_f32 v5, m0, 0.5, v255        ; encoding: [0x05,0x00,0x37,0xd6,0x7d,0xe0,0xfd,0x07]
+0x05,0x00,0x37,0xd6,0x7d,0xe0,0xfd,0x07
+
+# GFX12: v_div_fmas_f32 v5, -|exec_lo|, exec_lo, -|exec_lo| ; encoding: [0x05,0x05,0x37,0xd6,0x7e,0xfc,0xf8,0xa1]
+0x05,0x05,0x37,0xd6,0x7e,0xfc,0xf8,0xa1
+
+# GFX12: v_div_fmas_f32 v5, -|exec_hi|, -|exec_hi|, -|exec_hi| ; encoding: [0x05,0x07,0x37,0xd6,0x7f,0xfe,0xfc,0xe1]
+0x05,0x07,0x37,0xd6,0x7f,0xfe,0xfc,0xe1
+
+# GFX12: v_div_fmas_f32 v5, null, m0, -|m0|      ; encoding: [0x05,0x04,0x37,0xd6,0x7c,0xfa,0xf4,0x81]
+0x05,0x04,0x37,0xd6,0x7c,0xfa,0xf4,0x81
+
+# GFX12: v_div_fmas_f32 v5, -1, -|vcc_lo|, -|vcc_lo| ; encoding: [0x05,0x06,0x37,0xd6,0xc1,0xd4,0xa8,0xc1]
+0x05,0x06,0x37,0xd6,0xc1,0xd4,0xa8,0xc1
+
+# GFX12: v_div_fmas_f32 v5, 0.5, -|vcc_hi|, 0.5 mul:2 ; encoding: [0x05,0x02,0x37,0xd6,0xf0,0xd6,0xc0,0x4b]
+0x05,0x02,0x37,0xd6,0xf0,0xd6,0xc0,0x4b
+
+# GFX12: v_div_fmas_f32 v5, src_scc, -1, -1 mul:4 ; encoding: [0x05,0x00,0x37,0xd6,0xfd,0x82,0x05,0x13]
+0x05,0x00,0x37,0xd6,0xfd,0x82,0x05,0x13
+
+# GFX12: v_div_fmas_f32 v255, -|0xaf123456|, null, null clamp div:2 ; encoding: [0xff,0x81,0x37,0xd6,0xff,0xf8,0xf0,0x39,0x56,0x34,0x12,0xaf]
+0xff,0x81,0x37,0xd6,0xff,0xf8,0xf0,0x39,0x56,0x34,0x12,0xaf
+
+# GFX12: v_div_fmas_f64 v[5:6], v[1:2], 0xaf123456, 0xaf123456 ; encoding: [0x05,0x00,0x38,0xd6,0x01,0xff,0xfd,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x38,0xd6,0x01,0xff,0xfd,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_div_fmas_f64 v[5:6], v[254:255], src_scc, v[3:4] ; encoding: [0x05,0x00,0x38,0xd6,0xfe,0xfb,0x0d,0x04]
+0x05,0x00,0x38,0xd6,0xfe,0xfb,0x0d,0x04
+
+# GFX12: v_div_fmas_f64 v[5:6], s[104:105], |s[104:105]|, s[104:105] ; encoding: [0x05,0x02,0x38,0xd6,0x68,0xd0,0xa0,0x01]
+0x05,0x02,0x38,0xd6,0x68,0xd0,0xa0,0x01
+
+# GFX12: v_div_fmas_f64 v[5:6], -|vcc|, v[2:3], -|v[254:255]| ; encoding: [0x05,0x05,0x38,0xd6,0x6a,0x04,0xfa,0xa7]
+0x05,0x05,0x38,0xd6,0x6a,0x04,0xfa,0xa7
+
+# GFX12: v_div_fmas_f64 v[5:6], -|ttmp[14:15]|, -|ttmp[14:15]|, -|ttmp[14:15]| ; encoding: [0x05,0x07,0x38,0xd6,0x7a,0xf4,0xe8,0xe1]
+0x05,0x07,0x38,0xd6,0x7a,0xf4,0xe8,0xe1
+
+# GFX12: v_div_fmas_f64 v[5:6], -|exec|, -|v[254:255]|, null ; encoding: [0x05,0x03,0x38,0xd6,0x7e,0xfc,0xf3,0x61]
+0x05,0x03,0x38,0xd6,0x7e,0xfc,0xf3,0x61
+
+# GFX12: v_div_fmas_f64 v[5:6], null, 0.5, -src_scc ; encoding: [0x05,0x00,0x38,0xd6,0x7c,0xe0,0xf5,0x83]
+0x05,0x00,0x38,0xd6,0x7c,0xe0,0xf5,0x83
+
+# GFX12: v_div_fmas_f64 v[5:6], -1, -exec, |exec| ; encoding: [0x05,0x04,0x38,0xd6,0xc1,0xfc,0xf8,0x41]
+0x05,0x04,0x38,0xd6,0xc1,0xfc,0xf8,0x41
+
+# GFX12: v_div_fmas_f64 v[5:6], 0.5, -|vcc|, -|vcc| mul:2 ; encoding: [0x05,0x06,0x38,0xd6,0xf0,0xd4,0xa8,0xc9]
+0x05,0x06,0x38,0xd6,0xf0,0xd4,0xa8,0xc9
+
+# GFX12: v_div_fmas_f64 v[5:6], -|src_scc|, -1, 0.5 mul:4 ; encoding: [0x05,0x01,0x38,0xd6,0xfd,0x82,0xc1,0x33]
+0x05,0x01,0x38,0xd6,0xfd,0x82,0xc1,0x33
+
+# GFX12: v_div_fmas_f64 v[254:255], 0xaf123456, null, -1 clamp div:2 ; encoding: [0xfe,0x80,0x38,0xd6,0xff,0xf8,0x04,0x1b,0x56,0x34,0x12,0xaf]
+0xfe,0x80,0x38,0xd6,0xff,0xf8,0x04,0x1b,0x56,0x34,0x12,0xaf
+
+# W32: v_div_scale_f32 v5, vcc_lo, v1, v2, s3    ; encoding: [0x05,0x6a,0xfc,0xd6,0x01,0x05,0x0e,0x00]
+# W64: v_div_scale_f32 v5, vcc, v1, v2, s3       ; encoding: [0x05,0x6a,0xfc,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x6a,0xfc,0xd6,0x01,0x05,0x0e,0x00
+
+# W32: v_div_scale_f32 v5, vcc_lo, v255, s2, s105 ; encoding: [0x05,0x6a,0xfc,0xd6,0xff,0x05,0xa4,0x01]
+# W64: v_div_scale_f32 v5, vcc, v255, s2, s105   ; encoding: [0x05,0x6a,0xfc,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x6a,0xfc,0xd6,0xff,0x05,0xa4,0x01
+
+# W32: v_div_scale_f32 v5, vcc_lo, s1, v255, exec_hi ; encoding: [0x05,0x6a,0xfc,0xd6,0x01,0xfe,0xff,0x01]
+# W64: v_div_scale_f32 v5, vcc, s1, v255, exec_hi ; encoding: [0x05,0x6a,0xfc,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x6a,0xfc,0xd6,0x01,0xfe,0xff,0x01
+
+# W32: v_div_scale_f32 v5, vcc_lo, s105, s105, exec_lo ; encoding: [0x05,0x6a,0xfc,0xd6,0x69,0xd2,0xf8,0x01]
+# W64: v_div_scale_f32 v5, vcc, s105, s105, exec_lo ; encoding: [0x05,0x6a,0xfc,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x6a,0xfc,0xd6,0x69,0xd2,0xf8,0x01
+
+# W32: v_div_scale_f32 v5, vcc_lo, vcc_lo, ttmp15, v3 ; encoding: [0x05,0x6a,0xfc,0xd6,0x6a,0xf6,0x0c,0x04]
+# W64: v_div_scale_f32 v5, vcc, vcc_lo, ttmp15, v3 ; encoding: [0x05,0x6a,0xfc,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x6a,0xfc,0xd6,0x6a,0xf6,0x0c,0x04
+
+# W32: v_div_scale_f32 v5, vcc_lo, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x6a,0xfc,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+# W64: v_div_scale_f32 v5, vcc, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x6a,0xfc,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x6a,0xfc,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# W32: v_div_scale_f32 v5, vcc_lo, -ttmp15, -src_scc, -ttmp15 ; encoding: [0x05,0x6a,0xfc,0xd6,0x7b,0xfa,0xed,0xe1]
+# W64: v_div_scale_f32 v5, vcc, -ttmp15, -src_scc, -ttmp15 ; encoding: [0x05,0x6a,0xfc,0xd6,0x7b,0xfa,0xed,0xe1]
+0x05,0x6a,0xfc,0xd6,0x7b,0xfa,0xed,0xe1
+
+# W32: v_div_scale_f32 v5, vcc_lo, m0, 0.5, m0   ; encoding: [0x05,0x6a,0xfc,0xd6,0x7d,0xe0,0xf5,0x01]
+# W64: v_div_scale_f32 v5, vcc, m0, 0.5, m0      ; encoding: [0x05,0x6a,0xfc,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x6a,0xfc,0xd6,0x7d,0xe0,0xf5,0x01
+
+# W32: v_div_scale_f32 v5, vcc_lo, exec_lo, -1, vcc_hi ; encoding: [0x05,0x6a,0xfc,0xd6,0x7e,0x82,0xad,0x01]
+# W64: v_div_scale_f32 v5, vcc, exec_lo, -1, vcc_hi ; encoding: [0x05,0x6a,0xfc,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x6a,0xfc,0xd6,0x7e,0x82,0xad,0x01
+
+# W32: v_div_scale_f32 v5, vcc_lo, -exec_hi, null, -vcc_lo ; encoding: [0x05,0x6a,0xfc,0xd6,0x7f,0xf8,0xa8,0xa1]
+# W64: v_div_scale_f32 v5, vcc, -exec_hi, null, -vcc_lo ; encoding: [0x05,0x6a,0xfc,0xd6,0x7f,0xf8,0xa8,0xa1]
+0x05,0x6a,0xfc,0xd6,0x7f,0xf8,0xa8,0xa1
+
+# W32: v_div_scale_f32 v5, vcc_lo, null, exec_lo, neg(0xaf123456) ; encoding: [0x05,0x6a,0xfc,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+# W64: v_div_scale_f32 v5, vcc, null, exec_lo, neg(0xaf123456) ; encoding: [0x05,0x6a,0xfc,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+0x05,0x6a,0xfc,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf
+
+# W32: v_div_scale_f32 v5, vcc_lo, -1, -exec_hi, -src_scc ; encoding: [0x05,0x6a,0xfc,0xd6,0xc1,0xfe,0xf4,0xc3]
+# W64: v_div_scale_f32 v5, vcc, -1, -exec_hi, -src_scc ; encoding: [0x05,0x6a,0xfc,0xd6,0xc1,0xfe,0xf4,0xc3]
+0x05,0x6a,0xfc,0xd6,0xc1,0xfe,0xf4,0xc3
+
+# W32: v_div_scale_f32 v5, vcc_lo, 0.5, -m0, 0.5 mul:2 ; encoding: [0x05,0x6a,0xfc,0xd6,0xf0,0xfa,0xc0,0x4b]
+# W64: v_div_scale_f32 v5, vcc, 0.5, -m0, 0.5 mul:2 ; encoding: [0x05,0x6a,0xfc,0xd6,0xf0,0xfa,0xc0,0x4b]
+0x05,0x6a,0xfc,0xd6,0xf0,0xfa,0xc0,0x4b
+
+# W32: v_div_scale_f32 v5, vcc_lo, -src_scc, vcc_lo, -1 mul:4 ; encoding: [0x05,0x6a,0xfc,0xd6,0xfd,0xd4,0x04,0x33]
+# W64: v_div_scale_f32 v5, vcc, -src_scc, vcc_lo, -1 mul:4 ; encoding: [0x05,0x6a,0xfc,0xd6,0xfd,0xd4,0x04,0x33]
+0x05,0x6a,0xfc,0xd6,0xfd,0xd4,0x04,0x33
+
+# W32: v_div_scale_f32 v255, vcc_lo, neg(0xaf123456), -vcc_hi, null clamp div:2 ; encoding: [0xff,0xea,0xfc,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+# W64: v_div_scale_f32 v255, vcc, neg(0xaf123456), -vcc_hi, null clamp div:2 ; encoding: [0xff,0xea,0xfc,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+0xff,0xea,0xfc,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf
+
+# W32: v_div_scale_f64 v[5:6], vcc_lo, v[1:2], v[2:3], v[3:4] ; encoding: [0x05,0x6a,0xfd,0xd6,0x01,0x05,0x0e,0x04]
+# W64: v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], v[3:4] ; encoding: [0x05,0x6a,0xfd,0xd6,0x01,0x05,0x0e,0x04]
+0x05,0x6a,0xfd,0xd6,0x01,0x05,0x0e,0x04
+
+# W32: v_div_scale_f64 v[5:6], vcc_lo, v[254:255], v[254:255], s[6:7] ; encoding: [0x05,0x6a,0xfd,0xd6,0xfe,0xfd,0x1b,0x00]
+# W64: v_div_scale_f64 v[5:6], vcc, v[254:255], v[254:255], s[6:7] ; encoding: [0x05,0x6a,0xfd,0xd6,0xfe,0xfd,0x1b,0x00]
+0x05,0x6a,0xfd,0xd6,0xfe,0xfd,0x1b,0x00
+
+# W32: v_div_scale_f64 v[5:6], vcc_lo, s[2:3], s[4:5], v[254:255] ; encoding: [0x05,0x6a,0xfd,0xd6,0x02,0x08,0xf8,0x07]
+# W64: v_div_scale_f64 v[5:6], vcc, s[2:3], s[4:5], v[254:255] ; encoding: [0x05,0x6a,0xfd,0xd6,0x02,0x08,0xf8,0x07]
+0x05,0x6a,0xfd,0xd6,0x02,0x08,0xf8,0x07
+
+# W32: v_div_scale_f64 v[5:6], vcc_lo, -s[104:105], s[104:105], -s[104:105] ; encoding: [0x05,0x6a,0xfd,0xd6,0x68,0xd0,0xa0,0xa1]
+# W64: v_div_scale_f64 v[5:6], vcc, -s[104:105], s[104:105], -s[104:105] ; encoding: [0x05,0x6a,0xfd,0xd6,0x68,0xd0,0xa0,0xa1]
+0x05,0x6a,0xfd,0xd6,0x68,0xd0,0xa0,0xa1
+
+# W32: v_div_scale_f64 v[5:6], vcc_lo, vcc, -ttmp[14:15], -ttmp[14:15] ; encoding: [0x05,0x6a,0xfd,0xd6,0x6a,0xf4,0xe8,0xc1]
+# W64: v_div_scale_f64 v[5:6], vcc, vcc, -ttmp[14:15], -ttmp[14:15] ; encoding: [0x05,0x6a,0xfd,0xd6,0x6a,0xf4,0xe8,0xc1]
+0x05,0x6a,0xfd,0xd6,0x6a,0xf4,0xe8,0xc1
+
+# W32: v_div_scale_f64 v[5:6], vcc_lo, -ttmp[14:15], 0xaf123456, null ; encoding: [0x05,0x6a,0xfd,0xd6,0x7a,0xfe,0xf1,0x21,0x56,0x34,0x12,0xaf]
+# W64: v_div_scale_f64 v[5:6], vcc, -ttmp[14:15], 0xaf123456, null ; encoding: [0x05,0x6a,0xfd,0xd6,0x7a,0xfe,0xf1,0x21,0x56,0x34,0x12,0xaf]
+0x05,0x6a,0xfd,0xd6,0x7a,0xfe,0xf1,0x21,0x56,0x34,0x12,0xaf
+
+# W32: v_div_scale_f64 v[5:6], vcc_lo, -exec, -src_scc, -exec ; encoding: [0x05,0x6a,0xfd,0xd6,0x7e,0xfa,0xf9,0xe1]
+# W64: v_div_scale_f64 v[5:6], vcc, -exec, -src_scc, -exec ; encoding: [0x05,0x6a,0xfd,0xd6,0x7e,0xfa,0xf9,0xe1]
+0x05,0x6a,0xfd,0xd6,0x7e,0xfa,0xf9,0xe1
+
+# W32: v_div_scale_f64 v[5:6], vcc_lo, null, 0.5, vcc ; encoding: [0x05,0x6a,0xfd,0xd6,0x7c,0xe0,0xa9,0x01]
+# W64: v_div_scale_f64 v[5:6], vcc, null, 0.5, vcc ; encoding: [0x05,0x6a,0xfd,0xd6,0x7c,0xe0,0xa9,0x01]
+0x05,0x6a,0xfd,0xd6,0x7c,0xe0,0xa9,0x01
+
+# W32: v_div_scale_f64 v[5:6], vcc_lo, -1, -1, 0xaf123456 ; encoding: [0x05,0x6a,0xfd,0xd6,0xc1,0x82,0xfd,0x03,0x56,0x34,0x12,0xaf]
+# W64: v_div_scale_f64 v[5:6], vcc, -1, -1, 0xaf123456 ; encoding: [0x05,0x6a,0xfd,0xd6,0xc1,0x82,0xfd,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x6a,0xfd,0xd6,0xc1,0x82,0xfd,0x03,0x56,0x34,0x12,0xaf
+
+# W32: v_div_scale_f64 v[5:6], vcc_lo, 0.5, null, -src_scc mul:2 ; encoding: [0x05,0x6a,0xfd,0xd6,0xf0,0xf8,0xf4,0x8b]
+# W64: v_div_scale_f64 v[5:6], vcc, 0.5, null, -src_scc mul:2 ; encoding: [0x05,0x6a,0xfd,0xd6,0xf0,0xf8,0xf4,0x8b]
+0x05,0x6a,0xfd,0xd6,0xf0,0xf8,0xf4,0x8b
+
+# W32: v_div_scale_f64 v[5:6], vcc_lo, -src_scc, -exec, 0.5 mul:4 ; encoding: [0x05,0x6a,0xfd,0xd6,0xfd,0xfc,0xc0,0x73]
+# W64: v_div_scale_f64 v[5:6], vcc, -src_scc, -exec, 0.5 mul:4 ; encoding: [0x05,0x6a,0xfd,0xd6,0xfd,0xfc,0xc0,0x73]
+0x05,0x6a,0xfd,0xd6,0xfd,0xfc,0xc0,0x73
+
+# W32: v_div_scale_f64 v[254:255], vcc_lo, 0xaf123456, -vcc, -1 clamp div:2 ; encoding: [0xfe,0xea,0xfd,0xd6,0xff,0xd4,0x04,0x5b,0x56,0x34,0x12,0xaf]
+# W64: v_div_scale_f64 v[254:255], vcc, 0xaf123456, -vcc, -1 clamp div:2 ; encoding: [0xfe,0xea,0xfd,0xd6,0xff,0xd4,0x04,0x5b,0x56,0x34,0x12,0xaf]
+0xfe,0xea,0xfd,0xd6,0xff,0xd4,0x04,0x5b,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dot2_bf16_bf16 v5, v1, v2, s3         ; encoding: [0x05,0x00,0x67,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x67,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_dot2_bf16_bf16 v5, v255, v255, s105   ; encoding: [0x05,0x00,0x67,0xd6,0xff,0xff,0xa7,0x01]
+0x05,0x00,0x67,0xd6,0xff,0xff,0xa7,0x01
+
+# GFX12: v_dot2_bf16_bf16 v5, s1, s2, v3         ; encoding: [0x05,0x00,0x67,0xd6,0x01,0x04,0x0c,0x04]
+0x05,0x00,0x67,0xd6,0x01,0x04,0x0c,0x04
+
+# GFX12: v_dot2_bf16_bf16 v5, s105, s105, m0     ; encoding: [0x05,0x00,0x67,0xd6,0x69,0xd2,0xf4,0x01]
+0x05,0x00,0x67,0xd6,0x69,0xd2,0xf4,0x01
+
+# GFX12: v_dot2_bf16_bf16 v5, vcc_lo, ttmp15, v255 ; encoding: [0x05,0x00,0x67,0xd6,0x6a,0xf6,0xfc,0x07]
+0x05,0x00,0x67,0xd6,0x6a,0xf6,0xfc,0x07
+
+# GFX12: v_dot2_bf16_bf16 v5, vcc_hi, 0xfe0b, vcc_hi ; encoding: [0x05,0x00,0x67,0xd6,0x6b,0xfe,0xad,0x01,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x67,0xd6,0x6b,0xfe,0xad,0x01,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_dot2_bf16_bf16 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x00,0x67,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x67,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_dot2_bf16_bf16 v5, |m0|, -1, -vcc_lo  ; encoding: [0x05,0x01,0x67,0xd6,0x7d,0x82,0xa9,0x81]
+0x05,0x01,0x67,0xd6,0x7d,0x82,0xa9,0x81
+
+# GFX12: v_dot2_bf16_bf16 v5, -|exec_lo|, null, -|0xfe0b| ; encoding: [0x05,0x05,0x67,0xd6,0x7e,0xf8,0xfc,0xa3,0x0b,0xfe,0x00,0x00]
+0x05,0x05,0x67,0xd6,0x7e,0xf8,0xfc,0xa3,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_dot2_bf16_bf16 v5, -|exec_hi|, -|exec_lo|, -|exec_lo| ; encoding: [0x05,0x07,0x67,0xd6,0x7f,0xfc,0xf8,0xe1]
+0x05,0x07,0x67,0xd6,0x7f,0xfc,0xf8,0xe1
+
+# GFX12: v_dot2_bf16_bf16 v5, null, -exec_hi, |src_scc| ; encoding: [0x05,0x04,0x67,0xd6,0x7c,0xfe,0xf4,0x43]
+0x05,0x04,0x67,0xd6,0x7c,0xfe,0xf4,0x43
+
+# GFX12: v_dot2_bf16_bf16 v5, -1, -|m0|, -|exec_hi| ; encoding: [0x05,0x06,0x67,0xd6,0xc1,0xfa,0xfc,0xc1]
+0x05,0x06,0x67,0xd6,0xc1,0xfa,0xfc,0xc1
+
+# GFX12: v_dot2_bf16_bf16 v5, -src_scc, |vcc_lo|, -1 op_sel:[0,0,1,0] ; encoding: [0x05,0x22,0x67,0xd6,0xfd,0xd4,0x04,0x23]
+0x05,0x22,0x67,0xd6,0xfd,0xd4,0x04,0x23
+
+# GFX12: v_dot2_bf16_bf16 v255, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] ; encoding: [0xff,0x43,0x67,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
+0xff,0x43,0x67,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_dot2_f16_f16 v5, v1, v2, s3           ; encoding: [0x05,0x00,0x66,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x66,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_dot2_f16_f16 v5, v255, s2, s105       ; encoding: [0x05,0x00,0x66,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x66,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_dot2_f16_f16 v5, s1, v255, exec_hi    ; encoding: [0x05,0x00,0x66,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x66,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_dot2_f16_f16 v5, s105, s105, exec_lo  ; encoding: [0x05,0x00,0x66,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x66,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_dot2_f16_f16 v5, vcc_lo, ttmp15, v3   ; encoding: [0x05,0x00,0x66,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x66,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_dot2_f16_f16 v5, vcc_hi, 0xfe0b, v255 ; encoding: [0x05,0x00,0x66,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x66,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_dot2_f16_f16 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x66,0xd6,0x7b,0xfa,0xed,0xe1]
+0x05,0x07,0x66,0xd6,0x7b,0xfa,0xed,0xe1
+
+# GFX12: v_dot2_f16_f16 v5, m0, 0.5, m0          ; encoding: [0x05,0x00,0x66,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x66,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_dot2_f16_f16 v5, |exec_lo|, -1, vcc_hi ; encoding: [0x05,0x01,0x66,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x01,0x66,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_dot2_f16_f16 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x66,0xd6,0x7f,0xf8,0xa8,0xa1]
+0x05,0x05,0x66,0xd6,0x7f,0xf8,0xa8,0xa1
+
+# GFX12: v_dot2_f16_f16 v5, null, exec_lo, -|0xfe0b| ; encoding: [0x05,0x04,0x66,0xd6,0x7c,0xfc,0xfc,0x83,0x0b,0xfe,0x00,0x00]
+0x05,0x04,0x66,0xd6,0x7c,0xfc,0xfc,0x83,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_dot2_f16_f16 v5, -1, -|exec_hi|, -|src_scc| ; encoding: [0x05,0x06,0x66,0xd6,0xc1,0xfe,0xf4,0xc3]
+0x05,0x06,0x66,0xd6,0xc1,0xfe,0xf4,0xc3
+
+# GFX12: v_dot2_f16_f16 v5, 0.5, -m0, 0.5        ; encoding: [0x05,0x00,0x66,0xd6,0xf0,0xfa,0xc0,0x43]
+0x05,0x00,0x66,0xd6,0xf0,0xfa,0xc0,0x43
+
+# GFX12: v_dot2_f16_f16 v5, -src_scc, |vcc_lo|, -1 op_sel:[0,0,1,0] ; encoding: [0x05,0x22,0x66,0xd6,0xfd,0xd4,0x04,0x23]
+0x05,0x22,0x66,0xd6,0xfd,0xd4,0x04,0x23
+
+# GFX12: v_dot2_f16_f16 v255, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] ; encoding: [0xff,0x43,0x66,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
+0xff,0x43,0x66,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fma_dx9_zero_f32 v5, v1, v2, s3       ; encoding: [0x05,0x00,0x09,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x09,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_fma_dx9_zero_f32 v5, v255, s2, s105   ; encoding: [0x05,0x00,0x09,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x09,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_fma_dx9_zero_f32 v5, s1, v255, exec_hi ; encoding: [0x05,0x00,0x09,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x09,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_fma_dx9_zero_f32 v5, s105, s105, exec_lo ; encoding: [0x05,0x00,0x09,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x09,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_fma_dx9_zero_f32 v5, vcc_lo, ttmp15, v3 ; encoding: [0x05,0x00,0x09,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x09,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_fma_dx9_zero_f32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x09,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x09,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fma_dx9_zero_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x09,0xd6,0x7b,0xfa,0xed,0xe1]
+0x05,0x07,0x09,0xd6,0x7b,0xfa,0xed,0xe1
+
+# GFX12: v_fma_dx9_zero_f32 v5, m0, 0.5, m0      ; encoding: [0x05,0x00,0x09,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x09,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_fma_dx9_zero_f32 v5, |exec_lo|, -1, vcc_hi ; encoding: [0x05,0x01,0x09,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x01,0x09,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_fma_dx9_zero_f32 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x09,0xd6,0x7f,0xf8,0xa8,0xa1]
+0x05,0x05,0x09,0xd6,0x7f,0xf8,0xa8,0xa1
+
+# GFX12: v_fma_dx9_zero_f32 v5, null, exec_lo, -|0xaf123456| ; encoding: [0x05,0x04,0x09,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+0x05,0x04,0x09,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fma_dx9_zero_f32 v5, -1, -|exec_hi|, -|src_scc| ; encoding: [0x05,0x06,0x09,0xd6,0xc1,0xfe,0xf4,0xc3]
+0x05,0x06,0x09,0xd6,0xc1,0xfe,0xf4,0xc3
+
+# GFX12: v_fma_dx9_zero_f32 v5, 0.5, -m0, 0.5 mul:2 ; encoding: [0x05,0x00,0x09,0xd6,0xf0,0xfa,0xc0,0x4b]
+0x05,0x00,0x09,0xd6,0xf0,0xfa,0xc0,0x4b
+
+# GFX12: v_fma_dx9_zero_f32 v5, -src_scc, |vcc_lo|, -1 mul:4 ; encoding: [0x05,0x02,0x09,0xd6,0xfd,0xd4,0x04,0x33]
+0x05,0x02,0x09,0xd6,0xfd,0xd4,0x04,0x33
+
+# GFX12: v_fma_dx9_zero_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2 ; encoding: [0xff,0x83,0x09,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+0xff,0x83,0x09,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fma_f16 v5, v1, v2, s3                ; encoding: [0x05,0x00,0x48,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x48,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_fma_f16 v5, v255, s2, s105            ; encoding: [0x05,0x00,0x48,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x48,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_fma_f16 v5, s1, v255, exec_hi         ; encoding: [0x05,0x00,0x48,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x48,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_fma_f16 v5, s105, s105, exec_lo       ; encoding: [0x05,0x00,0x48,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x48,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_fma_f16 v5, vcc_lo, ttmp15, v3        ; encoding: [0x05,0x00,0x48,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x48,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_fma_f16 v5, vcc_hi, 0xfe0b, v255      ; encoding: [0x05,0x00,0x48,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x48,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fma_f16 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x48,0xd6,0x7b,0xfa,0xed,0xe1]
+0x05,0x07,0x48,0xd6,0x7b,0xfa,0xed,0xe1
+
+# GFX12: v_fma_f16 v5, m0, 0.5, m0               ; encoding: [0x05,0x00,0x48,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x48,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_fma_f16 v5, |exec_lo|, -1, vcc_hi     ; encoding: [0x05,0x01,0x48,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x01,0x48,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_fma_f16 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x48,0xd6,0x7f,0xf8,0xa8,0xa1]
+0x05,0x05,0x48,0xd6,0x7f,0xf8,0xa8,0xa1
+
+# GFX12: v_fma_f16 v5, null, exec_lo, -|0xfe0b| op_sel:[1,1,1,1] ; encoding: [0x05,0x7c,0x48,0xd6,0x7c,0xfc,0xfc,0x83,0x0b,0xfe,0x00,0x00]
+0x05,0x7c,0x48,0xd6,0x7c,0xfc,0xfc,0x83,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fma_f16 v5, -1, -|exec_hi|, -|src_scc| op_sel:[1,0,0,0] ; encoding: [0x05,0x0e,0x48,0xd6,0xc1,0xfe,0xf4,0xc3]
+0x05,0x0e,0x48,0xd6,0xc1,0xfe,0xf4,0xc3
+
+# GFX12: v_fma_f16 v5, 0.5, -m0, 0.5 op_sel:[0,1,0,0] ; encoding: [0x05,0x10,0x48,0xd6,0xf0,0xfa,0xc0,0x43]
+0x05,0x10,0x48,0xd6,0xf0,0xfa,0xc0,0x43
+
+# GFX12: v_fma_f16 v5, -src_scc, |vcc_lo|, -1 op_sel:[0,0,1,0] ; encoding: [0x05,0x22,0x48,0xd6,0xfd,0xd4,0x04,0x23]
+0x05,0x22,0x48,0xd6,0xfd,0xd4,0x04,0x23
+
+# GFX12: v_fma_f16 v255, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] clamp ; encoding: [0xff,0xc3,0x48,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
+0xff,0xc3,0x48,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fma_f32 v5, v1, v2, s3                ; encoding: [0x05,0x00,0x13,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x13,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_fma_f32 v5, v255, s2, s105            ; encoding: [0x05,0x00,0x13,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x13,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_fma_f32 v5, s1, v255, exec_hi         ; encoding: [0x05,0x00,0x13,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x13,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_fma_f32 v5, s105, s105, exec_lo       ; encoding: [0x05,0x00,0x13,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x13,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_fma_f32 v5, vcc_lo, ttmp15, v3        ; encoding: [0x05,0x00,0x13,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x13,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_fma_f32 v5, vcc_hi, 0xaf123456, v255  ; encoding: [0x05,0x00,0x13,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x13,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fma_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x13,0xd6,0x7b,0xfa,0xed,0xe1]
+0x05,0x07,0x13,0xd6,0x7b,0xfa,0xed,0xe1
+
+# GFX12: v_fma_f32 v5, m0, 0.5, m0               ; encoding: [0x05,0x00,0x13,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x13,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_fma_f32 v5, |exec_lo|, -1, vcc_hi     ; encoding: [0x05,0x01,0x13,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x01,0x13,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_fma_f32 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x13,0xd6,0x7f,0xf8,0xa8,0xa1]
+0x05,0x05,0x13,0xd6,0x7f,0xf8,0xa8,0xa1
+
+# GFX12: v_fma_f32 v5, null, exec_lo, -|0xaf123456| ; encoding: [0x05,0x04,0x13,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+0x05,0x04,0x13,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fma_f32 v5, -1, -|exec_hi|, -|src_scc| ; encoding: [0x05,0x06,0x13,0xd6,0xc1,0xfe,0xf4,0xc3]
+0x05,0x06,0x13,0xd6,0xc1,0xfe,0xf4,0xc3
+
+# GFX12: v_fma_f32 v5, 0.5, -m0, 0.5 mul:2       ; encoding: [0x05,0x00,0x13,0xd6,0xf0,0xfa,0xc0,0x4b]
+0x05,0x00,0x13,0xd6,0xf0,0xfa,0xc0,0x4b
+
+# GFX12: v_fma_f32 v5, -src_scc, |vcc_lo|, -1 mul:4 ; encoding: [0x05,0x02,0x13,0xd6,0xfd,0xd4,0x04,0x33]
+0x05,0x02,0x13,0xd6,0xfd,0xd4,0x04,0x33
+
+# GFX12: v_fma_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2 ; encoding: [0xff,0x83,0x13,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+0xff,0x83,0x13,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] ; encoding: [0x05,0x00,0x14,0xd6,0x01,0x05,0x0e,0x04]
+0x05,0x00,0x14,0xd6,0x01,0x05,0x0e,0x04
+
+# GFX12: v_fma_f64 v[5:6], v[254:255], v[254:255], s[6:7] ; encoding: [0x05,0x00,0x14,0xd6,0xfe,0xfd,0x1b,0x00]
+0x05,0x00,0x14,0xd6,0xfe,0xfd,0x1b,0x00
+
+# GFX12: v_fma_f64 v[5:6], s[2:3], s[4:5], v[254:255] ; encoding: [0x05,0x00,0x14,0xd6,0x02,0x08,0xf8,0x07]
+0x05,0x00,0x14,0xd6,0x02,0x08,0xf8,0x07
+
+# GFX12: v_fma_f64 v[5:6], -|s[104:105]|, s[104:105], -|s[104:105]| ; encoding: [0x05,0x05,0x14,0xd6,0x68,0xd0,0xa0,0xa1]
+0x05,0x05,0x14,0xd6,0x68,0xd0,0xa0,0xa1
+
+# GFX12: v_fma_f64 v[5:6], vcc, -|ttmp[14:15]|, -|ttmp[14:15]| ; encoding: [0x05,0x06,0x14,0xd6,0x6a,0xf4,0xe8,0xc1]
+0x05,0x06,0x14,0xd6,0x6a,0xf4,0xe8,0xc1
+
+# GFX12: v_fma_f64 v[5:6], -|ttmp[14:15]|, 0xaf123456, null ; encoding: [0x05,0x01,0x14,0xd6,0x7a,0xfe,0xf1,0x21,0x56,0x34,0x12,0xaf]
+0x05,0x01,0x14,0xd6,0x7a,0xfe,0xf1,0x21,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fma_f64 v[5:6], -|exec|, -|src_scc|, -|exec| ; encoding: [0x05,0x07,0x14,0xd6,0x7e,0xfa,0xf9,0xe1]
+0x05,0x07,0x14,0xd6,0x7e,0xfa,0xf9,0xe1
+
+# GFX12: v_fma_f64 v[5:6], null, 0.5, vcc        ; encoding: [0x05,0x00,0x14,0xd6,0x7c,0xe0,0xa9,0x01]
+0x05,0x00,0x14,0xd6,0x7c,0xe0,0xa9,0x01
+
+# GFX12: v_fma_f64 v[5:6], -1, -1, 0xaf123456    ; encoding: [0x05,0x00,0x14,0xd6,0xc1,0x82,0xfd,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x14,0xd6,0xc1,0x82,0xfd,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fma_f64 v[5:6], 0.5, null, -|src_scc| mul:2 ; encoding: [0x05,0x04,0x14,0xd6,0xf0,0xf8,0xf4,0x8b]
+0x05,0x04,0x14,0xd6,0xf0,0xf8,0xf4,0x8b
+
+# GFX12: v_fma_f64 v[5:6], -|src_scc|, -|exec|, 0.5 mul:4 ; encoding: [0x05,0x03,0x14,0xd6,0xfd,0xfc,0xc0,0x73]
+0x05,0x03,0x14,0xd6,0xfd,0xfc,0xc0,0x73
+
+# GFX12: v_fma_f64 v[254:255], 0xaf123456, -|vcc|, -1 clamp div:2 ; encoding: [0xfe,0x82,0x14,0xd6,0xff,0xd4,0x04,0x5b,0x56,0x34,0x12,0xaf]
+0xfe,0x82,0x14,0xd6,0xff,0xd4,0x04,0x5b,0x56,0x34,0x12,0xaf
+
+# GFX12: v_ldexp_f32 v5, v1, v2                  ; encoding: [0x05,0x00,0x1c,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x1c,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_ldexp_f32 v5, v255, v255              ; encoding: [0x05,0x00,0x1c,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x1c,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_ldexp_f32 v5, s1, s2                  ; encoding: [0x05,0x00,0x1c,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x1c,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_ldexp_f32 v5, s105, s105              ; encoding: [0x05,0x00,0x1c,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x1c,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_ldexp_f32 v5, vcc_lo, ttmp15          ; encoding: [0x05,0x00,0x1c,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x1c,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_ldexp_f32 v5, vcc_hi, 0xaf123456      ; encoding: [0x05,0x00,0x1c,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x1c,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_ldexp_f32 v5, ttmp15, src_scc         ; encoding: [0x05,0x00,0x1c,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x1c,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_ldexp_f32 v5, m0, 0.5                 ; encoding: [0x05,0x00,0x1c,0xd7,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x1c,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_ldexp_f32 v5, exec_lo, -1             ; encoding: [0x05,0x00,0x1c,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x1c,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_ldexp_f32 v5, exec_hi, null           ; encoding: [0x05,0x00,0x1c,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x1c,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_ldexp_f32 v5, null, exec_lo           ; encoding: [0x05,0x00,0x1c,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x1c,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_ldexp_f32 v5, -1, exec_hi             ; encoding: [0x05,0x00,0x1c,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x1c,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_ldexp_f32 v5, 0.5, m0 mul:2           ; encoding: [0x05,0x00,0x1c,0xd7,0xf0,0xfa,0x00,0x08]
+0x05,0x00,0x1c,0xd7,0xf0,0xfa,0x00,0x08
+
+# GFX12: v_ldexp_f32 v5, src_scc, vcc_lo mul:4   ; encoding: [0x05,0x00,0x1c,0xd7,0xfd,0xd4,0x00,0x10]
+0x05,0x00,0x1c,0xd7,0xfd,0xd4,0x00,0x10
+
+# GFX12: v_ldexp_f32 v255, -|0xaf123456|, vcc_hi clamp div:2 ; encoding: [0xff,0x81,0x1c,0xd7,0xff,0xd6,0x00,0x38,0x56,0x34,0x12,0xaf]
+0xff,0x81,0x1c,0xd7,0xff,0xd6,0x00,0x38,0x56,0x34,0x12,0xaf
+
+# GFX12: v_ldexp_f64 v[5:6], v[1:2], v2          ; encoding: [0x05,0x00,0x2b,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x2b,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_ldexp_f64 v[5:6], v[1:2], v255        ; encoding: [0x05,0x00,0x2b,0xd7,0x01,0xff,0x03,0x00]
+0x05,0x00,0x2b,0xd7,0x01,0xff,0x03,0x00
+
+# GFX12: v_ldexp_f64 v[5:6], v[1:2], s2          ; encoding: [0x05,0x00,0x2b,0xd7,0x01,0x05,0x00,0x00]
+0x05,0x00,0x2b,0xd7,0x01,0x05,0x00,0x00
+
+# GFX12: v_ldexp_f64 v[5:6], v[1:2], s105        ; encoding: [0x05,0x00,0x2b,0xd7,0x01,0xd3,0x00,0x00]
+0x05,0x00,0x2b,0xd7,0x01,0xd3,0x00,0x00
+
+# GFX12: v_ldexp_f64 v[5:6], v[254:255], ttmp15  ; encoding: [0x05,0x00,0x2b,0xd7,0xfe,0xf7,0x00,0x00]
+0x05,0x00,0x2b,0xd7,0xfe,0xf7,0x00,0x00
+
+# GFX12: v_ldexp_f64 v[5:6], s[2:3], vcc_hi      ; encoding: [0x05,0x00,0x2b,0xd7,0x02,0xd6,0x00,0x00]
+0x05,0x00,0x2b,0xd7,0x02,0xd6,0x00,0x00
+
+# GFX12: v_ldexp_f64 v[5:6], s[104:105], vcc_lo  ; encoding: [0x05,0x00,0x2b,0xd7,0x68,0xd4,0x00,0x00]
+0x05,0x00,0x2b,0xd7,0x68,0xd4,0x00,0x00
+
+# GFX12: v_ldexp_f64 v[5:6], vcc, m0             ; encoding: [0x05,0x00,0x2b,0xd7,0x6a,0xfa,0x00,0x00]
+0x05,0x00,0x2b,0xd7,0x6a,0xfa,0x00,0x00
+
+# GFX12: v_ldexp_f64 v[5:6], ttmp[14:15], exec_hi ; encoding: [0x05,0x00,0x2b,0xd7,0x7a,0xfe,0x00,0x00]
+0x05,0x00,0x2b,0xd7,0x7a,0xfe,0x00,0x00
+
+# GFX12: v_ldexp_f64 v[5:6], exec, exec_lo       ; encoding: [0x05,0x00,0x2b,0xd7,0x7e,0xfc,0x00,0x00]
+0x05,0x00,0x2b,0xd7,0x7e,0xfc,0x00,0x00
+
+# GFX12: v_ldexp_f64 v[5:6], null, null          ; encoding: [0x05,0x00,0x2b,0xd7,0x7c,0xf8,0x00,0x00]
+0x05,0x00,0x2b,0xd7,0x7c,0xf8,0x00,0x00
+
+# GFX12: v_ldexp_f64 v[5:6], -1, -1              ; encoding: [0x05,0x00,0x2b,0xd7,0xc1,0x82,0x01,0x00]
+0x05,0x00,0x2b,0xd7,0xc1,0x82,0x01,0x00
+
+# GFX12: v_ldexp_f64 v[5:6], 0.5, 0.5 mul:2      ; encoding: [0x05,0x00,0x2b,0xd7,0xf0,0xe0,0x01,0x08]
+0x05,0x00,0x2b,0xd7,0xf0,0xe0,0x01,0x08
+
+# GFX12: v_ldexp_f64 v[5:6], -|src_scc|, src_scc mul:4 ; encoding: [0x05,0x01,0x2b,0xd7,0xfd,0xfa,0x01,0x30]
+0x05,0x01,0x2b,0xd7,0xfd,0xfa,0x01,0x30
+
+# GFX12: v_ldexp_f64 v[254:255], 0xaf123456, 0xaf123456 clamp div:2 ; encoding: [0xfe,0x80,0x2b,0xd7,0xff,0xfe,0x01,0x18,0x56,0x34,0x12,0xaf]
+0xfe,0x80,0x2b,0xd7,0xff,0xfe,0x01,0x18,0x56,0x34,0x12,0xaf
+
+# GFX12: v_lerp_u8 v5, v1, v2, s3                ; encoding: [0x05,0x00,0x15,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x15,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_lerp_u8 v5, v255, s2, s105            ; encoding: [0x05,0x00,0x15,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x15,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_lerp_u8 v5, s1, v255, exec_hi         ; encoding: [0x05,0x00,0x15,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x15,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_lerp_u8 v5, s105, s105, exec_lo       ; encoding: [0x05,0x00,0x15,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x15,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_lerp_u8 v5, vcc_lo, ttmp15, v3        ; encoding: [0x05,0x00,0x15,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x15,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_lerp_u8 v5, vcc_hi, 0xaf123456, v255  ; encoding: [0x05,0x00,0x15,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x15,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_lerp_u8 v5, ttmp15, src_scc, ttmp15   ; encoding: [0x05,0x00,0x15,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x15,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_lerp_u8 v5, m0, 0.5, m0               ; encoding: [0x05,0x00,0x15,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x15,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_lerp_u8 v5, exec_lo, -1, vcc_hi       ; encoding: [0x05,0x00,0x15,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x15,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_lerp_u8 v5, exec_hi, null, vcc_lo     ; encoding: [0x05,0x00,0x15,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x15,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_lerp_u8 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x15,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x15,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_lerp_u8 v5, -1, exec_hi, src_scc      ; encoding: [0x05,0x00,0x15,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x15,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_lerp_u8 v5, 0.5, m0, 0.5              ; encoding: [0x05,0x00,0x15,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x15,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_lerp_u8 v5, src_scc, vcc_lo, -1       ; encoding: [0x05,0x00,0x15,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x15,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_lerp_u8 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x15,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x15,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_lshl_add_u32 v5, v1, v2, s3           ; encoding: [0x05,0x00,0x46,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x46,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_lshl_add_u32 v5, v255, s2, s105       ; encoding: [0x05,0x00,0x46,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x46,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_lshl_add_u32 v5, s1, v255, exec_hi    ; encoding: [0x05,0x00,0x46,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x46,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_lshl_add_u32 v5, s105, s105, exec_lo  ; encoding: [0x05,0x00,0x46,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x46,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_lshl_add_u32 v5, vcc_lo, ttmp15, v3   ; encoding: [0x05,0x00,0x46,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x46,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_lshl_add_u32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x46,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x46,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_lshl_add_u32 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x00,0x46,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x46,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_lshl_add_u32 v5, m0, 0.5, m0          ; encoding: [0x05,0x00,0x46,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x46,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_lshl_add_u32 v5, exec_lo, -1, vcc_hi  ; encoding: [0x05,0x00,0x46,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x46,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_lshl_add_u32 v5, exec_hi, null, vcc_lo ; encoding: [0x05,0x00,0x46,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x46,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_lshl_add_u32 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x46,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x46,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_lshl_add_u32 v5, -1, exec_hi, src_scc ; encoding: [0x05,0x00,0x46,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x46,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_lshl_add_u32 v5, 0.5, m0, 0.5         ; encoding: [0x05,0x00,0x46,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x46,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_lshl_add_u32 v5, src_scc, vcc_lo, -1  ; encoding: [0x05,0x00,0x46,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x46,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_lshl_add_u32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x46,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x46,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_lshl_or_b32 v5, v1, v2, s3            ; encoding: [0x05,0x00,0x56,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x56,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_lshl_or_b32 v5, v255, s2, s105        ; encoding: [0x05,0x00,0x56,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x56,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_lshl_or_b32 v5, s1, v255, exec_hi     ; encoding: [0x05,0x00,0x56,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x56,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_lshl_or_b32 v5, s105, s105, exec_lo   ; encoding: [0x05,0x00,0x56,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x56,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_lshl_or_b32 v5, vcc_lo, ttmp15, v3    ; encoding: [0x05,0x00,0x56,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x56,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_lshl_or_b32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x56,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x56,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_lshl_or_b32 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x00,0x56,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x56,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_lshl_or_b32 v5, m0, 0.5, m0           ; encoding: [0x05,0x00,0x56,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x56,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_lshl_or_b32 v5, exec_lo, -1, vcc_hi   ; encoding: [0x05,0x00,0x56,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x56,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_lshl_or_b32 v5, exec_hi, null, vcc_lo ; encoding: [0x05,0x00,0x56,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x56,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_lshl_or_b32 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x56,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x56,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_lshl_or_b32 v5, -1, exec_hi, src_scc  ; encoding: [0x05,0x00,0x56,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x56,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_lshl_or_b32 v5, 0.5, m0, 0.5          ; encoding: [0x05,0x00,0x56,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x56,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_lshl_or_b32 v5, src_scc, vcc_lo, -1   ; encoding: [0x05,0x00,0x56,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x56,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_lshl_or_b32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x56,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x56,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_lshlrev_b16 v5, v1, v2                ; encoding: [0x05,0x00,0x38,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x38,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_lshlrev_b16 v5, v255, v255            ; encoding: [0x05,0x00,0x38,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x38,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_lshlrev_b16 v5, s1, s2                ; encoding: [0x05,0x00,0x38,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x38,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_lshlrev_b16 v5, s105, s105            ; encoding: [0x05,0x00,0x38,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x38,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_lshlrev_b16 v5, vcc_lo, ttmp15        ; encoding: [0x05,0x00,0x38,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x38,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_lshlrev_b16 v5, vcc_hi, 0xfe0b        ; encoding: [0x05,0x00,0x38,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x38,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_lshlrev_b16 v5, ttmp15, src_scc       ; encoding: [0x05,0x00,0x38,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x38,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_lshlrev_b16 v5, m0, 0x3800
+0x05,0x00,0x38,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_lshlrev_b16 v5, exec_lo, -1           ; encoding: [0x05,0x00,0x38,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x38,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_lshlrev_b16 v5, exec_hi, null         ; encoding: [0x05,0x00,0x38,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x38,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_lshlrev_b16 v5, null, exec_lo         ; encoding: [0x05,0x00,0x38,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x38,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_lshlrev_b16 v5, -1, exec_hi           ; encoding: [0x05,0x00,0x38,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x38,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_lshlrev_b16 v5, 0x3800, m0
+0x05,0x00,0x38,0xd7,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_lshlrev_b16 v5, src_scc, vcc_lo       ; encoding: [0x05,0x00,0x38,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x38,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_lshlrev_b16 v255, 0xfe0b, vcc_hi      ; encoding: [0xff,0x00,0x38,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0xff,0x00,0x38,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_lshrrev_b16 v5, v1, v2                ; encoding: [0x05,0x00,0x39,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x39,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_lshrrev_b16 v5, v255, v255            ; encoding: [0x05,0x00,0x39,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x39,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_lshrrev_b16 v5, s1, s2                ; encoding: [0x05,0x00,0x39,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x39,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_lshrrev_b16 v5, s105, s105            ; encoding: [0x05,0x00,0x39,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x39,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_lshrrev_b16 v5, vcc_lo, ttmp15        ; encoding: [0x05,0x00,0x39,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x39,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_lshrrev_b16 v5, vcc_hi, 0xfe0b        ; encoding: [0x05,0x00,0x39,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x39,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_lshrrev_b16 v5, ttmp15, src_scc       ; encoding: [0x05,0x00,0x39,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x39,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_lshrrev_b16 v5, m0, 0x3800
+0x05,0x00,0x39,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_lshrrev_b16 v5, exec_lo, -1           ; encoding: [0x05,0x00,0x39,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x39,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_lshrrev_b16 v5, exec_hi, null         ; encoding: [0x05,0x00,0x39,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x39,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_lshrrev_b16 v5, null, exec_lo         ; encoding: [0x05,0x00,0x39,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x39,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_lshrrev_b16 v5, -1, exec_hi           ; encoding: [0x05,0x00,0x39,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x39,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_lshrrev_b16 v5, 0x3800, m0
+0x05,0x00,0x39,0xd7,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_lshrrev_b16 v5, src_scc, vcc_lo       ; encoding: [0x05,0x00,0x39,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x39,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_lshrrev_b16 v255, 0xfe0b, vcc_hi      ; encoding: [0xff,0x00,0x39,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0xff,0x00,0x39,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_lshrrev_b64 v[5:6], v1, vcc           ; encoding: [0x05,0x00,0x3d,0xd7,0x01,0xd5,0x00,0x00]
+0x05,0x00,0x3d,0xd7,0x01,0xd5,0x00,0x00
+
+# GFX12: v_lshrrev_b64 v[5:6], v255, exec        ; encoding: [0x05,0x00,0x3d,0xd7,0xff,0xfd,0x00,0x00]
+0x05,0x00,0x3d,0xd7,0xff,0xfd,0x00,0x00
+
+# GFX12: v_lshrrev_b64 v[5:6], exec_lo, v[2:3]   ; encoding: [0x05,0x00,0x3d,0xd7,0x7e,0x04,0x02,0x00]
+0x05,0x00,0x3d,0xd7,0x7e,0x04,0x02,0x00
+
+# GFX12: v_lshrrev_b64 v[5:6], exec_hi, v[254:255] ; encoding: [0x05,0x00,0x3d,0xd7,0x7f,0xfc,0x03,0x00]
+0x05,0x00,0x3d,0xd7,0x7f,0xfc,0x03,0x00
+
+# GFX12: v_lshrrev_b64 v[5:6], null, null        ; encoding: [0x05,0x00,0x3d,0xd7,0x7c,0xf8,0x00,0x00]
+0x05,0x00,0x3d,0xd7,0x7c,0xf8,0x00,0x00
+
+# GFX12: v_lshrrev_b64 v[5:6], -1, -1            ; encoding: [0x05,0x00,0x3d,0xd7,0xc1,0x82,0x01,0x00]
+0x05,0x00,0x3d,0xd7,0xc1,0x82,0x01,0x00
+
+# GFX12: v_lshrrev_b64 v[5:6], 0.5, 0xaf123456   ; encoding: [0x05,0x00,0x3d,0xd7,0xf0,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x3d,0xd7,0xf0,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_lshrrev_b64 v[5:6], src_scc, src_scc  ; encoding: [0x05,0x00,0x3d,0xd7,0xfd,0xfa,0x01,0x00]
+0x05,0x00,0x3d,0xd7,0xfd,0xfa,0x01,0x00
+
+# GFX12: v_lshrrev_b64 v[254:255], 0xaf123456, 0.5 ; encoding: [0xfe,0x00,0x3d,0xd7,0xff,0xe0,0x01,0x00,0x56,0x34,0x12,0xaf]
+0xfe,0x00,0x3d,0xd7,0xff,0xe0,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mad_i16 v5, v1, v2, s3                ; encoding: [0x05,0x00,0x53,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x53,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_mad_i16 v5, v255, s2, s105            ; encoding: [0x05,0x00,0x53,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x53,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_mad_i16 v5, s1, v255, exec_hi         ; encoding: [0x05,0x00,0x53,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x53,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_mad_i16 v5, s105, s105, exec_lo       ; encoding: [0x05,0x00,0x53,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x53,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_mad_i16 v5, vcc_lo, ttmp15, v3        ; encoding: [0x05,0x00,0x53,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x53,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_mad_i16 v5, vcc_hi, 0xfe0b, v255      ; encoding: [0x05,0x00,0x53,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x53,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_mad_i16 v5, ttmp15, src_scc, ttmp15   ; encoding: [0x05,0x00,0x53,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x53,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_mad_i16 v5, m0, 0x3800, m0
+0x05,0x00,0x53,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_mad_i16 v5, exec_lo, -1, vcc_hi       ; encoding: [0x05,0x00,0x53,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x53,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_mad_i16 v5, exec_hi, null, vcc_lo     ; encoding: [0x05,0x00,0x53,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x53,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_mad_i16 v5, null, exec_lo, 0xfe0b op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x53,0xd6,0x7c,0xfc,0xfc,0x03,0x0b,0xfe,0x00,0x00]
+0x05,0x78,0x53,0xd6,0x7c,0xfc,0xfc,0x03,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_mad_i16 v5, -1, exec_hi, src_scc op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x53,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x08,0x53,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_mad_i16 v5, 0x3800, m0, 0x3800 op_sel:[0,1,0,0]
+0x05,0x10,0x53,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_mad_i16 v5, src_scc, vcc_lo, -1 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x53,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x20,0x53,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_mad_i16 v255, 0xfe0b, vcc_hi, null op_sel:[0,0,0,1] clamp ; encoding: [0xff,0xc0,0x53,0xd6,0xff,0xd6,0xf0,0x01,0x0b,0xfe,0x00,0x00]
+0xff,0xc0,0x53,0xd6,0xff,0xd6,0xf0,0x01,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_mad_i32_i16 v5, v1, v2, v3            ; encoding: [0x05,0x00,0x5a,0xd6,0x01,0x05,0x0e,0x04]
+0x05,0x00,0x5a,0xd6,0x01,0x05,0x0e,0x04
+
+# GFX12: v_mad_i32_i16 v5, v255, v255, s3        ; encoding: [0x05,0x00,0x5a,0xd6,0xff,0xff,0x0f,0x00]
+0x05,0x00,0x5a,0xd6,0xff,0xff,0x0f,0x00
+
+# GFX12: v_mad_i32_i16 v5, s1, s2, v255          ; encoding: [0x05,0x00,0x5a,0xd6,0x01,0x04,0xfc,0x07]
+0x05,0x00,0x5a,0xd6,0x01,0x04,0xfc,0x07
+
+# GFX12: v_mad_i32_i16 v5, s105, s105, s105      ; encoding: [0x05,0x00,0x5a,0xd6,0x69,0xd2,0xa4,0x01]
+0x05,0x00,0x5a,0xd6,0x69,0xd2,0xa4,0x01
+
+# GFX12: v_mad_i32_i16 v5, vcc_lo, ttmp15, vcc_lo ; encoding: [0x05,0x00,0x5a,0xd6,0x6a,0xf6,0xa8,0x01]
+0x05,0x00,0x5a,0xd6,0x6a,0xf6,0xa8,0x01
+
+# GFX12: v_mad_i32_i16 v5, vcc_hi, 0xfe0b, vcc_hi ; encoding: [0x05,0x00,0x5a,0xd6,0x6b,0xfe,0xad,0x01,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x5a,0xd6,0x6b,0xfe,0xad,0x01,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_mad_i32_i16 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x00,0x5a,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x5a,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_mad_i32_i16 v5, m0, 0x3800, m0
+0x05,0x00,0x5a,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_mad_i32_i16 v5, exec_lo, -1, exec_hi  ; encoding: [0x05,0x00,0x5a,0xd6,0x7e,0x82,0xfd,0x01]
+0x05,0x00,0x5a,0xd6,0x7e,0x82,0xfd,0x01
+
+# GFX12: v_mad_i32_i16 v5, exec_hi, null, exec_lo ; encoding: [0x05,0x00,0x5a,0xd6,0x7f,0xf8,0xf8,0x01]
+0x05,0x00,0x5a,0xd6,0x7f,0xf8,0xf8,0x01
+
+# GFX12: v_mad_i32_i16 v5, null, exec_lo, null   ; encoding: [0x05,0x00,0x5a,0xd6,0x7c,0xfc,0xf0,0x01]
+0x05,0x00,0x5a,0xd6,0x7c,0xfc,0xf0,0x01
+
+# GFX12: v_mad_i32_i16 v5, -1, exec_hi, 0xaf123456 ; encoding: [0x05,0x00,0x5a,0xd6,0xc1,0xfe,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x5a,0xd6,0xc1,0xfe,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mad_i32_i16 v5, 0x3800, m0, -1
+0x05,0x00,0x5a,0xd6,0xf0,0xfa,0x04,0x03
+
+# GFX12: v_mad_i32_i16 v5, src_scc, vcc_lo, src_scc op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x5a,0xd6,0xfd,0xd4,0xf4,0x03]
+0x05,0x08,0x5a,0xd6,0xfd,0xd4,0xf4,0x03
+
+# GFX12: v_mad_i32_i16 v255, 0xfe0b, vcc_hi, 0.5 op_sel:[0,1,0,0] clamp ; encoding: [0xff,0x90,0x5a,0xd6,0xff,0xd6,0xc0,0x03,0x0b,0xfe,0x00,0x00]
+0xff,0x90,0x5a,0xd6,0xff,0xd6,0xc0,0x03,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_mad_i32_i24 v5, v1, v2, s3            ; encoding: [0x05,0x00,0x0a,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x0a,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_mad_i32_i24 v5, v255, s2, s105        ; encoding: [0x05,0x00,0x0a,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x0a,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_mad_i32_i24 v5, s1, v255, exec_hi     ; encoding: [0x05,0x00,0x0a,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x0a,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_mad_i32_i24 v5, s105, s105, exec_lo   ; encoding: [0x05,0x00,0x0a,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x0a,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_mad_i32_i24 v5, vcc_lo, ttmp15, v3    ; encoding: [0x05,0x00,0x0a,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x0a,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_mad_i32_i24 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x0a,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x0a,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mad_i32_i24 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x00,0x0a,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x0a,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_mad_i32_i24 v5, m0, 0.5, m0           ; encoding: [0x05,0x00,0x0a,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x0a,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_mad_i32_i24 v5, exec_lo, -1, vcc_hi   ; encoding: [0x05,0x00,0x0a,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x0a,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_mad_i32_i24 v5, exec_hi, null, vcc_lo ; encoding: [0x05,0x00,0x0a,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x0a,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_mad_i32_i24 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x0a,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x0a,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mad_i32_i24 v5, -1, exec_hi, src_scc  ; encoding: [0x05,0x00,0x0a,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x0a,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_mad_i32_i24 v5, 0.5, m0, 0.5          ; encoding: [0x05,0x00,0x0a,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x0a,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_mad_i32_i24 v5, src_scc, vcc_lo, -1   ; encoding: [0x05,0x00,0x0a,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x0a,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_mad_i32_i24 v255, 0xaf123456, vcc_hi, null clamp ; encoding: [0xff,0x80,0x0a,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x80,0x0a,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# W32: v_mad_co_i64_i32 v[5:6], s12, v1, s2, s[6:7] ; encoding: [0x05,0x0c,0xff,0xd6,0x01,0x05,0x18,0x00]
+# W64: v_mad_co_i64_i32 v[5:6], s[12:13], v1, s2, s[6:7] ; encoding: [0x05,0x0c,0xff,0xd6,0x01,0x05,0x18,0x00]
+0x05,0x0c,0xff,0xd6,0x01,0x05,0x18,0x00
+
+# W32: v_mad_co_i64_i32 v[5:6], s12, v255, ttmp15, s[6:7] ; encoding: [0x05,0x0c,0xff,0xd6,0xff,0xf7,0x18,0x00]
+# W64: v_mad_co_i64_i32 v[5:6], s[12:13], v255, ttmp15, s[6:7] ; encoding: [0x05,0x0c,0xff,0xd6,0xff,0xf7,0x18,0x00]
+0x05,0x0c,0xff,0xd6,0xff,0xf7,0x18,0x00
+
+# W32: v_mad_co_i64_i32 v[5:6], s12, s1, v2, s[6:7] ; encoding: [0x05,0x0c,0xff,0xd6,0x01,0x04,0x1a,0x00]
+# W64: v_mad_co_i64_i32 v[5:6], s[12:13], s1, v2, s[6:7] ; encoding: [0x05,0x0c,0xff,0xd6,0x01,0x04,0x1a,0x00]
+0x05,0x0c,0xff,0xd6,0x01,0x04,0x1a,0x00
+
+# W32: v_mad_co_i64_i32 v[5:6], s12, s105, s105, s[6:7] ; encoding: [0x05,0x0c,0xff,0xd6,0x69,0xd2,0x18,0x00]
+# W64: v_mad_co_i64_i32 v[5:6], s[12:13], s105, s105, s[6:7] ; encoding: [0x05,0x0c,0xff,0xd6,0x69,0xd2,0x18,0x00]
+0x05,0x0c,0xff,0xd6,0x69,0xd2,0x18,0x00
+
+# W32: v_mad_co_i64_i32 v[5:6], s12, vcc_lo, v255, s[104:105] ; encoding: [0x05,0x0c,0xff,0xd6,0x6a,0xfe,0xa3,0x01]
+# W64: v_mad_co_i64_i32 v[5:6], s[12:13], vcc_lo, v255, s[104:105] ; encoding: [0x05,0x0c,0xff,0xd6,0x6a,0xfe,0xa3,0x01]
+0x05,0x0c,0xff,0xd6,0x6a,0xfe,0xa3,0x01
+
+# W32: v_mad_co_i64_i32 v[5:6], s12, vcc_hi, 0xaf123456, v[3:4] ; encoding: [0x05,0x0c,0xff,0xd6,0x6b,0xfe,0x0d,0x04,0x56,0x34,0x12,0xaf]
+# W64: v_mad_co_i64_i32 v[5:6], s[12:13], vcc_hi, 0xaf123456, v[3:4] ; encoding: [0x05,0x0c,0xff,0xd6,0x6b,0xfe,0x0d,0x04,0x56,0x34,0x12,0xaf]
+0x05,0x0c,0xff,0xd6,0x6b,0xfe,0x0d,0x04,0x56,0x34,0x12,0xaf
+
+# W32: v_mad_co_i64_i32 v[5:6], s12, ttmp15, src_scc, v[254:255] ; encoding: [0x05,0x0c,0xff,0xd6,0x7b,0xfa,0xf9,0x07]
+# W64: v_mad_co_i64_i32 v[5:6], s[12:13], ttmp15, src_scc, v[254:255] ; encoding: [0x05,0x0c,0xff,0xd6,0x7b,0xfa,0xf9,0x07]
+0x05,0x0c,0xff,0xd6,0x7b,0xfa,0xf9,0x07
+
+# W32: v_mad_co_i64_i32 v[5:6], s12, m0, 0.5, ttmp[14:15] ; encoding: [0x05,0x0c,0xff,0xd6,0x7d,0xe0,0xe9,0x01]
+# W64: v_mad_co_i64_i32 v[5:6], s[12:13], m0, 0.5, ttmp[14:15] ; encoding: [0x05,0x0c,0xff,0xd6,0x7d,0xe0,0xe9,0x01]
+0x05,0x0c,0xff,0xd6,0x7d,0xe0,0xe9,0x01
+
+# W32: v_mad_co_i64_i32 v[5:6], s12, exec_lo, -1, exec ; encoding: [0x05,0x0c,0xff,0xd6,0x7e,0x82,0xf9,0x01]
+# W64: v_mad_co_i64_i32 v[5:6], s[12:13], exec_lo, -1, exec ; encoding: [0x05,0x0c,0xff,0xd6,0x7e,0x82,0xf9,0x01]
+0x05,0x0c,0xff,0xd6,0x7e,0x82,0xf9,0x01
+
+# W32: v_mad_co_i64_i32 v[5:6], s12, exec_hi, null, vcc ; encoding: [0x05,0x0c,0xff,0xd6,0x7f,0xf8,0xa8,0x01]
+# W64: v_mad_co_i64_i32 v[5:6], s[12:13], exec_hi, null, vcc ; encoding: [0x05,0x0c,0xff,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x0c,0xff,0xd6,0x7f,0xf8,0xa8,0x01
+
+# W32: v_mad_co_i64_i32 v[5:6], s12, null, exec_lo, null ; encoding: [0x05,0x0c,0xff,0xd6,0x7c,0xfc,0xf0,0x01]
+# W64: v_mad_co_i64_i32 v[5:6], s[12:13], null, exec_lo, null ; encoding: [0x05,0x0c,0xff,0xd6,0x7c,0xfc,0xf0,0x01]
+0x05,0x0c,0xff,0xd6,0x7c,0xfc,0xf0,0x01
+
+# W32: v_mad_co_i64_i32 v[5:6], s104, -1, exec_hi, -1 ; encoding: [0x05,0x68,0xff,0xd6,0xc1,0xfe,0x04,0x03]
+# W64: v_mad_co_i64_i32 v[5:6], s[104:105], -1, exec_hi, -1 ; encoding: [0x05,0x68,0xff,0xd6,0xc1,0xfe,0x04,0x03]
+0x05,0x68,0xff,0xd6,0xc1,0xfe,0x04,0x03
+
+# W32: v_mad_co_i64_i32 v[5:6], vcc_lo, 0.5, m0, 0xaf123456 ; encoding: [0x05,0x6a,0xff,0xd6,0xf0,0xfa,0xfc,0x03,0x56,0x34,0x12,0xaf]
+# W64: v_mad_co_i64_i32 v[5:6], vcc, 0.5, m0, 0xaf123456 ; encoding: [0x05,0x6a,0xff,0xd6,0xf0,0xfa,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x6a,0xff,0xd6,0xf0,0xfa,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# W32: v_mad_co_i64_i32 v[5:6], ttmp14, src_scc, vcc_lo, src_scc ; encoding: [0x05,0x7a,0xff,0xd6,0xfd,0xd4,0xf4,0x03]
+# W64: v_mad_co_i64_i32 v[5:6], ttmp[14:15], src_scc, vcc_lo, src_scc ; encoding: [0x05,0x7a,0xff,0xd6,0xfd,0xd4,0xf4,0x03]
+0x05,0x7a,0xff,0xd6,0xfd,0xd4,0xf4,0x03
+
+# GFX12: v_mad_co_i64_i32 v[254:255], null, 0xaf123456, vcc_hi, 0.5 clamp ; encoding: [0xfe,0xfc,0xff,0xd6,0xff,0xd6,0xc0,0x03,0x56,0x34,0x12,0xaf]
+0xfe,0xfc,0xff,0xd6,0xff,0xd6,0xc0,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mad_u16 v5, v1, v2, s3                ; encoding: [0x05,0x00,0x41,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x41,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_mad_u16 v5, v255, s2, s105            ; encoding: [0x05,0x00,0x41,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x41,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_mad_u16 v5, s1, v255, exec_hi         ; encoding: [0x05,0x00,0x41,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x41,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_mad_u16 v5, s105, s105, exec_lo       ; encoding: [0x05,0x00,0x41,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x41,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_mad_u16 v5, vcc_lo, ttmp15, v3        ; encoding: [0x05,0x00,0x41,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x41,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_mad_u16 v5, vcc_hi, 0xfe0b, v255      ; encoding: [0x05,0x00,0x41,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x41,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_mad_u16 v5, ttmp15, src_scc, ttmp15   ; encoding: [0x05,0x00,0x41,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x41,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_mad_u16 v5, m0, 0x3800, m0
+0x05,0x00,0x41,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_mad_u16 v5, exec_lo, -1, vcc_hi       ; encoding: [0x05,0x00,0x41,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x41,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_mad_u16 v5, exec_hi, null, vcc_lo     ; encoding: [0x05,0x00,0x41,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x41,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_mad_u16 v5, null, exec_lo, 0xfe0b op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x41,0xd6,0x7c,0xfc,0xfc,0x03,0x0b,0xfe,0x00,0x00]
+0x05,0x78,0x41,0xd6,0x7c,0xfc,0xfc,0x03,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_mad_u16 v5, -1, exec_hi, src_scc op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x41,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x08,0x41,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_mad_u16 v5, 0x3800, m0, 0x3800 op_sel:[0,1,0,0]
+0x05,0x10,0x41,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_mad_u16 v5, src_scc, vcc_lo, -1 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x41,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x20,0x41,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_mad_u16 v255, 0xfe0b, vcc_hi, null op_sel:[0,0,0,1] clamp ; encoding: [0xff,0xc0,0x41,0xd6,0xff,0xd6,0xf0,0x01,0x0b,0xfe,0x00,0x00]
+0xff,0xc0,0x41,0xd6,0xff,0xd6,0xf0,0x01,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_mad_u32_u16 v5, v1, v2, v3            ; encoding: [0x05,0x00,0x59,0xd6,0x01,0x05,0x0e,0x04]
+0x05,0x00,0x59,0xd6,0x01,0x05,0x0e,0x04
+
+# GFX12: v_mad_u32_u16 v5, v255, v255, s3        ; encoding: [0x05,0x00,0x59,0xd6,0xff,0xff,0x0f,0x00]
+0x05,0x00,0x59,0xd6,0xff,0xff,0x0f,0x00
+
+# GFX12: v_mad_u32_u16 v5, s1, s2, v255          ; encoding: [0x05,0x00,0x59,0xd6,0x01,0x04,0xfc,0x07]
+0x05,0x00,0x59,0xd6,0x01,0x04,0xfc,0x07
+
+# GFX12: v_mad_u32_u16 v5, s105, s105, s105      ; encoding: [0x05,0x00,0x59,0xd6,0x69,0xd2,0xa4,0x01]
+0x05,0x00,0x59,0xd6,0x69,0xd2,0xa4,0x01
+
+# GFX12: v_mad_u32_u16 v5, vcc_lo, ttmp15, vcc_lo ; encoding: [0x05,0x00,0x59,0xd6,0x6a,0xf6,0xa8,0x01]
+0x05,0x00,0x59,0xd6,0x6a,0xf6,0xa8,0x01
+
+# GFX12: v_mad_u32_u16 v5, vcc_hi, 0xfe0b, vcc_hi ; encoding: [0x05,0x00,0x59,0xd6,0x6b,0xfe,0xad,0x01,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x59,0xd6,0x6b,0xfe,0xad,0x01,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_mad_u32_u16 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x00,0x59,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x59,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_mad_u32_u16 v5, m0, 0x3800, m0
+0x05,0x00,0x59,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_mad_u32_u16 v5, exec_lo, -1, exec_hi  ; encoding: [0x05,0x00,0x59,0xd6,0x7e,0x82,0xfd,0x01]
+0x05,0x00,0x59,0xd6,0x7e,0x82,0xfd,0x01
+
+# GFX12: v_mad_u32_u16 v5, exec_hi, null, exec_lo ; encoding: [0x05,0x00,0x59,0xd6,0x7f,0xf8,0xf8,0x01]
+0x05,0x00,0x59,0xd6,0x7f,0xf8,0xf8,0x01
+
+# GFX12: v_mad_u32_u16 v5, null, exec_lo, null   ; encoding: [0x05,0x00,0x59,0xd6,0x7c,0xfc,0xf0,0x01]
+0x05,0x00,0x59,0xd6,0x7c,0xfc,0xf0,0x01
+
+# GFX12: v_mad_u32_u16 v5, -1, exec_hi, 0xaf123456 ; encoding: [0x05,0x00,0x59,0xd6,0xc1,0xfe,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x59,0xd6,0xc1,0xfe,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mad_u32_u16 v5, 0x3800, m0, -1
+0x05,0x00,0x59,0xd6,0xf0,0xfa,0x04,0x03
+
+# GFX12: v_mad_u32_u16 v5, src_scc, vcc_lo, src_scc op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x59,0xd6,0xfd,0xd4,0xf4,0x03]
+0x05,0x08,0x59,0xd6,0xfd,0xd4,0xf4,0x03
+
+# GFX12: v_mad_u32_u16 v255, 0xfe0b, vcc_hi, 0.5 op_sel:[0,1,0,0] clamp ; encoding: [0xff,0x90,0x59,0xd6,0xff,0xd6,0xc0,0x03,0x0b,0xfe,0x00,0x00]
+0xff,0x90,0x59,0xd6,0xff,0xd6,0xc0,0x03,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_mad_u32_u24 v5, v1, v2, s3            ; encoding: [0x05,0x00,0x0b,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x0b,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_mad_u32_u24 v5, v255, s2, s105        ; encoding: [0x05,0x00,0x0b,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x0b,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_mad_u32_u24 v5, s1, v255, exec_hi     ; encoding: [0x05,0x00,0x0b,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x0b,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_mad_u32_u24 v5, s105, s105, exec_lo   ; encoding: [0x05,0x00,0x0b,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x0b,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_mad_u32_u24 v5, vcc_lo, ttmp15, v3    ; encoding: [0x05,0x00,0x0b,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x0b,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_mad_u32_u24 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x0b,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x0b,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mad_u32_u24 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x00,0x0b,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x0b,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_mad_u32_u24 v5, m0, 0.5, m0           ; encoding: [0x05,0x00,0x0b,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x0b,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_mad_u32_u24 v5, exec_lo, -1, vcc_hi   ; encoding: [0x05,0x00,0x0b,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x0b,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_mad_u32_u24 v5, exec_hi, null, vcc_lo ; encoding: [0x05,0x00,0x0b,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x0b,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_mad_u32_u24 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x0b,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x0b,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mad_u32_u24 v5, -1, exec_hi, src_scc  ; encoding: [0x05,0x00,0x0b,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x0b,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_mad_u32_u24 v5, 0.5, m0, 0.5          ; encoding: [0x05,0x00,0x0b,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x0b,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_mad_u32_u24 v5, src_scc, vcc_lo, -1   ; encoding: [0x05,0x00,0x0b,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x0b,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_mad_u32_u24 v255, 0xaf123456, vcc_hi, null clamp ; encoding: [0xff,0x80,0x0b,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x80,0x0b,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# W32: v_mad_co_u64_u32 v[5:6], s12, v1, s2, s[6:7] ; encoding: [0x05,0x0c,0xfe,0xd6,0x01,0x05,0x18,0x00]
+# W64: v_mad_co_u64_u32 v[5:6], s[12:13], v1, s2, s[6:7] ; encoding: [0x05,0x0c,0xfe,0xd6,0x01,0x05,0x18,0x00]
+0x05,0x0c,0xfe,0xd6,0x01,0x05,0x18,0x00
+
+# W32: v_mad_co_u64_u32 v[5:6], s12, v255, ttmp15, s[6:7] ; encoding: [0x05,0x0c,0xfe,0xd6,0xff,0xf7,0x18,0x00]
+# W64: v_mad_co_u64_u32 v[5:6], s[12:13], v255, ttmp15, s[6:7] ; encoding: [0x05,0x0c,0xfe,0xd6,0xff,0xf7,0x18,0x00]
+0x05,0x0c,0xfe,0xd6,0xff,0xf7,0x18,0x00
+
+# W32: v_mad_co_u64_u32 v[5:6], s12, s1, v2, s[6:7] ; encoding: [0x05,0x0c,0xfe,0xd6,0x01,0x04,0x1a,0x00]
+# W64: v_mad_co_u64_u32 v[5:6], s[12:13], s1, v2, s[6:7] ; encoding: [0x05,0x0c,0xfe,0xd6,0x01,0x04,0x1a,0x00]
+0x05,0x0c,0xfe,0xd6,0x01,0x04,0x1a,0x00
+
+# W32: v_mad_co_u64_u32 v[5:6], s12, s105, s105, s[6:7] ; encoding: [0x05,0x0c,0xfe,0xd6,0x69,0xd2,0x18,0x00]
+# W64: v_mad_co_u64_u32 v[5:6], s[12:13], s105, s105, s[6:7] ; encoding: [0x05,0x0c,0xfe,0xd6,0x69,0xd2,0x18,0x00]
+0x05,0x0c,0xfe,0xd6,0x69,0xd2,0x18,0x00
+
+# W32: v_mad_co_u64_u32 v[5:6], s12, vcc_lo, v255, s[104:105] ; encoding: [0x05,0x0c,0xfe,0xd6,0x6a,0xfe,0xa3,0x01]
+# W64: v_mad_co_u64_u32 v[5:6], s[12:13], vcc_lo, v255, s[104:105] ; encoding: [0x05,0x0c,0xfe,0xd6,0x6a,0xfe,0xa3,0x01]
+0x05,0x0c,0xfe,0xd6,0x6a,0xfe,0xa3,0x01
+
+# W32: v_mad_co_u64_u32 v[5:6], s12, vcc_hi, 0xaf123456, v[3:4] ; encoding: [0x05,0x0c,0xfe,0xd6,0x6b,0xfe,0x0d,0x04,0x56,0x34,0x12,0xaf]
+# W64: v_mad_co_u64_u32 v[5:6], s[12:13], vcc_hi, 0xaf123456, v[3:4] ; encoding: [0x05,0x0c,0xfe,0xd6,0x6b,0xfe,0x0d,0x04,0x56,0x34,0x12,0xaf]
+0x05,0x0c,0xfe,0xd6,0x6b,0xfe,0x0d,0x04,0x56,0x34,0x12,0xaf
+
+# W32: v_mad_co_u64_u32 v[5:6], s12, ttmp15, src_scc, v[254:255] ; encoding: [0x05,0x0c,0xfe,0xd6,0x7b,0xfa,0xf9,0x07]
+# W64: v_mad_co_u64_u32 v[5:6], s[12:13], ttmp15, src_scc, v[254:255] ; encoding: [0x05,0x0c,0xfe,0xd6,0x7b,0xfa,0xf9,0x07]
+0x05,0x0c,0xfe,0xd6,0x7b,0xfa,0xf9,0x07
+
+# W32: v_mad_co_u64_u32 v[5:6], s12, m0, 0.5, ttmp[14:15] ; encoding: [0x05,0x0c,0xfe,0xd6,0x7d,0xe0,0xe9,0x01]
+# W64: v_mad_co_u64_u32 v[5:6], s[12:13], m0, 0.5, ttmp[14:15] ; encoding: [0x05,0x0c,0xfe,0xd6,0x7d,0xe0,0xe9,0x01]
+0x05,0x0c,0xfe,0xd6,0x7d,0xe0,0xe9,0x01
+
+# W32: v_mad_co_u64_u32 v[5:6], s12, exec_lo, -1, exec ; encoding: [0x05,0x0c,0xfe,0xd6,0x7e,0x82,0xf9,0x01]
+# W64: v_mad_co_u64_u32 v[5:6], s[12:13], exec_lo, -1, exec ; encoding: [0x05,0x0c,0xfe,0xd6,0x7e,0x82,0xf9,0x01]
+0x05,0x0c,0xfe,0xd6,0x7e,0x82,0xf9,0x01
+
+# W32: v_mad_co_u64_u32 v[5:6], s12, exec_hi, null, vcc ; encoding: [0x05,0x0c,0xfe,0xd6,0x7f,0xf8,0xa8,0x01]
+# W64: v_mad_co_u64_u32 v[5:6], s[12:13], exec_hi, null, vcc ; encoding: [0x05,0x0c,0xfe,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x0c,0xfe,0xd6,0x7f,0xf8,0xa8,0x01
+
+# W32: v_mad_co_u64_u32 v[5:6], s12, null, exec_lo, null ; encoding: [0x05,0x0c,0xfe,0xd6,0x7c,0xfc,0xf0,0x01]
+# W64: v_mad_co_u64_u32 v[5:6], s[12:13], null, exec_lo, null ; encoding: [0x05,0x0c,0xfe,0xd6,0x7c,0xfc,0xf0,0x01]
+0x05,0x0c,0xfe,0xd6,0x7c,0xfc,0xf0,0x01
+
+# W32: v_mad_co_u64_u32 v[5:6], s104, -1, exec_hi, -1 ; encoding: [0x05,0x68,0xfe,0xd6,0xc1,0xfe,0x04,0x03]
+# W64: v_mad_co_u64_u32 v[5:6], s[104:105], -1, exec_hi, -1 ; encoding: [0x05,0x68,0xfe,0xd6,0xc1,0xfe,0x04,0x03]
+0x05,0x68,0xfe,0xd6,0xc1,0xfe,0x04,0x03
+
+# W32: v_mad_co_u64_u32 v[5:6], vcc_lo, 0.5, m0, 0xaf123456 ; encoding: [0x05,0x6a,0xfe,0xd6,0xf0,0xfa,0xfc,0x03,0x56,0x34,0x12,0xaf]
+# W64: v_mad_co_u64_u32 v[5:6], vcc, 0.5, m0, 0xaf123456 ; encoding: [0x05,0x6a,0xfe,0xd6,0xf0,0xfa,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x6a,0xfe,0xd6,0xf0,0xfa,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# W32: v_mad_co_u64_u32 v[5:6], ttmp14, src_scc, vcc_lo, src_scc ; encoding: [0x05,0x7a,0xfe,0xd6,0xfd,0xd4,0xf4,0x03]
+# W64: v_mad_co_u64_u32 v[5:6], ttmp[14:15], src_scc, vcc_lo, src_scc ; encoding: [0x05,0x7a,0xfe,0xd6,0xfd,0xd4,0xf4,0x03]
+0x05,0x7a,0xfe,0xd6,0xfd,0xd4,0xf4,0x03
+
+# GFX12: v_mad_co_u64_u32 v[254:255], null, 0xaf123456, vcc_hi, 0.5 clamp ; encoding: [0xfe,0xfc,0xfe,0xd6,0xff,0xd6,0xc0,0x03,0x56,0x34,0x12,0xaf]
+0xfe,0xfc,0xfe,0xd6,0xff,0xd6,0xc0,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_max3_num_f16 v5, v1, v2, s3           ; encoding: [0x05,0x00,0x2c,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x2c,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_max3_num_f16 v5, v255, s2, s105       ; encoding: [0x05,0x00,0x2c,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x2c,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_max3_num_f16 v5, s1, v255, exec_hi    ; encoding: [0x05,0x00,0x2c,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x2c,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_max3_num_f16 v5, s105, s105, exec_lo  ; encoding: [0x05,0x00,0x2c,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x2c,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_max3_num_f16 v5, vcc_lo, ttmp15, v3   ; encoding: [0x05,0x00,0x2c,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x2c,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_max3_num_f16 v5, vcc_hi, 0xfe0b, v255 ; encoding: [0x05,0x00,0x2c,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x2c,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_max3_num_f16 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x2c,0xd6,0x7b,0xfa,0xed,0xe1]
+0x05,0x07,0x2c,0xd6,0x7b,0xfa,0xed,0xe1
+
+# GFX12: v_max3_num_f16 v5, m0, 0.5, m0          ; encoding: [0x05,0x00,0x2c,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x2c,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_max3_num_f16 v5, |exec_lo|, -1, vcc_hi ; encoding: [0x05,0x01,0x2c,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x01,0x2c,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_max3_num_f16 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x2c,0xd6,0x7f,0xf8,0xa8,0xa1]
+0x05,0x05,0x2c,0xd6,0x7f,0xf8,0xa8,0xa1
+
+# GFX12: v_max3_num_f16 v5, null, exec_lo, -|0xfe0b| op_sel:[1,1,1,1] ; encoding: [0x05,0x7c,0x2c,0xd6,0x7c,0xfc,0xfc,0x83,0x0b,0xfe,0x00,0x00]
+0x05,0x7c,0x2c,0xd6,0x7c,0xfc,0xfc,0x83,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_max3_num_f16 v5, -1, -|exec_hi|, -|src_scc| op_sel:[1,0,0,0] ; encoding: [0x05,0x0e,0x2c,0xd6,0xc1,0xfe,0xf4,0xc3]
+0x05,0x0e,0x2c,0xd6,0xc1,0xfe,0xf4,0xc3
+
+# GFX12: v_max3_num_f16 v5, 0.5, -m0, 0.5 op_sel:[0,1,0,0] ; encoding: [0x05,0x10,0x2c,0xd6,0xf0,0xfa,0xc0,0x43]
+0x05,0x10,0x2c,0xd6,0xf0,0xfa,0xc0,0x43
+
+# GFX12: v_max3_num_f16 v5, -src_scc, |vcc_lo|, -1 op_sel:[0,0,1,0] ; encoding: [0x05,0x22,0x2c,0xd6,0xfd,0xd4,0x04,0x23]
+0x05,0x22,0x2c,0xd6,0xfd,0xd4,0x04,0x23
+
+# GFX12: v_max3_num_f16 v255, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] clamp ; encoding: [0xff,0xc3,0x2c,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
+0xff,0xc3,0x2c,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_max3_num_f32 v5, v1, v2, s3           ; encoding: [0x05,0x00,0x2a,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x2a,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_max3_num_f32 v5, v255, s2, s105       ; encoding: [0x05,0x00,0x2a,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x2a,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_max3_num_f32 v5, s1, v255, exec_hi    ; encoding: [0x05,0x00,0x2a,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x2a,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_max3_num_f32 v5, s105, s105, exec_lo  ; encoding: [0x05,0x00,0x2a,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x2a,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_max3_num_f32 v5, vcc_lo, ttmp15, v3   ; encoding: [0x05,0x00,0x2a,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x2a,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_max3_num_f32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x2a,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x2a,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_max3_num_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x2a,0xd6,0x7b,0xfa,0xed,0xe1]
+0x05,0x07,0x2a,0xd6,0x7b,0xfa,0xed,0xe1
+
+# GFX12: v_max3_num_f32 v5, m0, 0.5, m0          ; encoding: [0x05,0x00,0x2a,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x2a,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_max3_num_f32 v5, |exec_lo|, -1, vcc_hi ; encoding: [0x05,0x01,0x2a,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x01,0x2a,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_max3_num_f32 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x2a,0xd6,0x7f,0xf8,0xa8,0xa1]
+0x05,0x05,0x2a,0xd6,0x7f,0xf8,0xa8,0xa1
+
+# GFX12: v_max3_num_f32 v5, null, exec_lo, -|0xaf123456| ; encoding: [0x05,0x04,0x2a,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+0x05,0x04,0x2a,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf
+
+# GFX12: v_max3_num_f32 v5, -1, -|exec_hi|, -|src_scc| ; encoding: [0x05,0x06,0x2a,0xd6,0xc1,0xfe,0xf4,0xc3]
+0x05,0x06,0x2a,0xd6,0xc1,0xfe,0xf4,0xc3
+
+# GFX12: v_max3_num_f32 v5, 0.5, -m0, 0.5 mul:2  ; encoding: [0x05,0x00,0x2a,0xd6,0xf0,0xfa,0xc0,0x4b]
+0x05,0x00,0x2a,0xd6,0xf0,0xfa,0xc0,0x4b
+
+# GFX12: v_max3_num_f32 v5, -src_scc, |vcc_lo|, -1 mul:4 ; encoding: [0x05,0x02,0x2a,0xd6,0xfd,0xd4,0x04,0x33]
+0x05,0x02,0x2a,0xd6,0xfd,0xd4,0x04,0x33
+
+# GFX12: v_max3_num_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2 ; encoding: [0xff,0x83,0x2a,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+0xff,0x83,0x2a,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf
+
+# GFX12: v_max3_i16 v5, v1, v2, s3               ; encoding: [0x05,0x00,0x4d,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x4d,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_max3_i16 v5, v255, s2, s105           ; encoding: [0x05,0x00,0x4d,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x4d,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_max3_i16 v5, s1, v255, exec_hi        ; encoding: [0x05,0x00,0x4d,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x4d,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_max3_i16 v5, s105, s105, exec_lo      ; encoding: [0x05,0x00,0x4d,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x4d,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_max3_i16 v5, vcc_lo, ttmp15, v3       ; encoding: [0x05,0x00,0x4d,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x4d,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_max3_i16 v5, vcc_hi, 0xfe0b, v255     ; encoding: [0x05,0x00,0x4d,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x4d,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_max3_i16 v5, ttmp15, src_scc, ttmp15  ; encoding: [0x05,0x00,0x4d,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x4d,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_max3_i16 v5, m0, 0x3800, m0
+0x05,0x00,0x4d,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_max3_i16 v5, exec_lo, -1, vcc_hi      ; encoding: [0x05,0x00,0x4d,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x4d,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_max3_i16 v5, exec_hi, null, vcc_lo    ; encoding: [0x05,0x00,0x4d,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x4d,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_max3_i16 v5, null, exec_lo, 0xfe0b op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x4d,0xd6,0x7c,0xfc,0xfc,0x03,0x0b,0xfe,0x00,0x00]
+0x05,0x78,0x4d,0xd6,0x7c,0xfc,0xfc,0x03,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_max3_i16 v5, -1, exec_hi, src_scc op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x4d,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x08,0x4d,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_max3_i16 v5, 0x3800, m0, 0x3800 op_sel:[0,1,0,0]
+0x05,0x10,0x4d,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_max3_i16 v5, src_scc, vcc_lo, -1 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x4d,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x20,0x4d,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_max3_i16 v255, 0xfe0b, vcc_hi, null op_sel:[0,0,0,1] ; encoding: [0xff,0x40,0x4d,0xd6,0xff,0xd6,0xf0,0x01,0x0b,0xfe,0x00,0x00]
+0xff,0x40,0x4d,0xd6,0xff,0xd6,0xf0,0x01,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_max3_i32 v5, v1, v2, s3               ; encoding: [0x05,0x00,0x1d,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x1d,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_max3_i32 v5, v255, s2, s105           ; encoding: [0x05,0x00,0x1d,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x1d,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_max3_i32 v5, s1, v255, exec_hi        ; encoding: [0x05,0x00,0x1d,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x1d,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_max3_i32 v5, s105, s105, exec_lo      ; encoding: [0x05,0x00,0x1d,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x1d,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_max3_i32 v5, vcc_lo, ttmp15, v3       ; encoding: [0x05,0x00,0x1d,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x1d,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_max3_i32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x1d,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x1d,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_max3_i32 v5, ttmp15, src_scc, ttmp15  ; encoding: [0x05,0x00,0x1d,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x1d,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_max3_i32 v5, m0, 0.5, m0              ; encoding: [0x05,0x00,0x1d,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x1d,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_max3_i32 v5, exec_lo, -1, vcc_hi      ; encoding: [0x05,0x00,0x1d,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x1d,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_max3_i32 v5, exec_hi, null, vcc_lo    ; encoding: [0x05,0x00,0x1d,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x1d,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_max3_i32 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x1d,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x1d,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_max3_i32 v5, -1, exec_hi, src_scc     ; encoding: [0x05,0x00,0x1d,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x1d,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_max3_i32 v5, 0.5, m0, 0.5             ; encoding: [0x05,0x00,0x1d,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x1d,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_max3_i32 v5, src_scc, vcc_lo, -1      ; encoding: [0x05,0x00,0x1d,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x1d,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_max3_i32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x1d,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x1d,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_max3_u16 v5, v1, v2, s3               ; encoding: [0x05,0x00,0x4e,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x4e,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_max3_u16 v5, v255, s2, s105           ; encoding: [0x05,0x00,0x4e,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x4e,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_max3_u16 v5, s1, v255, exec_hi        ; encoding: [0x05,0x00,0x4e,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x4e,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_max3_u16 v5, s105, s105, exec_lo      ; encoding: [0x05,0x00,0x4e,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x4e,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_max3_u16 v5, vcc_lo, ttmp15, v3       ; encoding: [0x05,0x00,0x4e,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x4e,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_max3_u16 v5, vcc_hi, 0xfe0b, v255     ; encoding: [0x05,0x00,0x4e,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x4e,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_max3_u16 v5, ttmp15, src_scc, ttmp15  ; encoding: [0x05,0x00,0x4e,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x4e,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_max3_u16 v5, m0, 0x3800, m0
+0x05,0x00,0x4e,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_max3_u16 v5, exec_lo, -1, vcc_hi      ; encoding: [0x05,0x00,0x4e,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x4e,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_max3_u16 v5, exec_hi, null, vcc_lo    ; encoding: [0x05,0x00,0x4e,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x4e,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_max3_u16 v5, null, exec_lo, 0xfe0b op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x4e,0xd6,0x7c,0xfc,0xfc,0x03,0x0b,0xfe,0x00,0x00]
+0x05,0x78,0x4e,0xd6,0x7c,0xfc,0xfc,0x03,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_max3_u16 v5, -1, exec_hi, src_scc op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x4e,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x08,0x4e,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_max3_u16 v5, 0x3800, m0, 0x3800 op_sel:[0,1,0,0]
+0x05,0x10,0x4e,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_max3_u16 v5, src_scc, vcc_lo, -1 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x4e,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x20,0x4e,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_max3_u16 v255, 0xfe0b, vcc_hi, null op_sel:[0,0,0,1] ; encoding: [0xff,0x40,0x4e,0xd6,0xff,0xd6,0xf0,0x01,0x0b,0xfe,0x00,0x00]
+0xff,0x40,0x4e,0xd6,0xff,0xd6,0xf0,0x01,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_max3_u32 v5, v1, v2, s3               ; encoding: [0x05,0x00,0x1e,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x1e,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_max3_u32 v5, v255, s2, s105           ; encoding: [0x05,0x00,0x1e,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x1e,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_max3_u32 v5, s1, v255, exec_hi        ; encoding: [0x05,0x00,0x1e,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x1e,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_max3_u32 v5, s105, s105, exec_lo      ; encoding: [0x05,0x00,0x1e,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x1e,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_max3_u32 v5, vcc_lo, ttmp15, v3       ; encoding: [0x05,0x00,0x1e,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x1e,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_max3_u32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x1e,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x1e,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_max3_u32 v5, ttmp15, src_scc, ttmp15  ; encoding: [0x05,0x00,0x1e,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x1e,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_max3_u32 v5, m0, 0.5, m0              ; encoding: [0x05,0x00,0x1e,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x1e,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_max3_u32 v5, exec_lo, -1, vcc_hi      ; encoding: [0x05,0x00,0x1e,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x1e,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_max3_u32 v5, exec_hi, null, vcc_lo    ; encoding: [0x05,0x00,0x1e,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x1e,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_max3_u32 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x1e,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x1e,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_max3_u32 v5, -1, exec_hi, src_scc     ; encoding: [0x05,0x00,0x1e,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x1e,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_max3_u32 v5, 0.5, m0, 0.5             ; encoding: [0x05,0x00,0x1e,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x1e,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_max3_u32 v5, src_scc, vcc_lo, -1      ; encoding: [0x05,0x00,0x1e,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x1e,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_max3_u32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x1e,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x1e,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_max_i16 v5, v1, v2                    ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x0a,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_max_i16 v5, v255, v255                ; encoding: [0x05,0x00,0x0a,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x0a,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_max_i16 v5, s1, s2                    ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x0a,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_max_i16 v5, s105, s105                ; encoding: [0x05,0x00,0x0a,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x0a,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_max_i16 v5, vcc_lo, ttmp15            ; encoding: [0x05,0x00,0x0a,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x0a,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_max_i16 v5, vcc_hi, 0xfe0b            ; encoding: [0x05,0x00,0x0a,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x0a,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_max_i16 v5, ttmp15, src_scc           ; encoding: [0x05,0x00,0x0a,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x0a,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_max_i16 v5, m0, 0x3800
+0x05,0x00,0x0a,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_max_i16 v5, exec_lo, -1               ; encoding: [0x05,0x00,0x0a,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x0a,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_max_i16 v5, exec_hi, null             ; encoding: [0x05,0x00,0x0a,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x0a,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_max_i16 v5, null, exec_lo             ; encoding: [0x05,0x00,0x0a,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x0a,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_max_i16 v5, -1, exec_hi               ; encoding: [0x05,0x00,0x0a,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x0a,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_max_i16 v5, 0x3800, m0
+0x05,0x00,0x0a,0xd7,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_max_i16 v5, src_scc, vcc_lo           ; encoding: [0x05,0x00,0x0a,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x0a,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_max_i16 v255, 0xfe0b, vcc_hi          ; encoding: [0xff,0x00,0x0a,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0xff,0x00,0x0a,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_max_u16 v5, v1, v2                    ; encoding: [0x05,0x00,0x09,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x09,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_max_u16 v5, v255, v255                ; encoding: [0x05,0x00,0x09,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x09,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_max_u16 v5, s1, s2                    ; encoding: [0x05,0x00,0x09,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x09,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_max_u16 v5, s105, s105                ; encoding: [0x05,0x00,0x09,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x09,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_max_u16 v5, vcc_lo, ttmp15            ; encoding: [0x05,0x00,0x09,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x09,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_max_u16 v5, vcc_hi, 0xfe0b            ; encoding: [0x05,0x00,0x09,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x09,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_max_u16 v5, ttmp15, src_scc           ; encoding: [0x05,0x00,0x09,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x09,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_max_u16 v5, m0, 0x3800
+0x05,0x00,0x09,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_max_u16 v5, exec_lo, -1               ; encoding: [0x05,0x00,0x09,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x09,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_max_u16 v5, exec_hi, null             ; encoding: [0x05,0x00,0x09,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x09,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_max_u16 v5, null, exec_lo             ; encoding: [0x05,0x00,0x09,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x09,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_max_u16 v5, -1, exec_hi               ; encoding: [0x05,0x00,0x09,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x09,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_max_u16 v5, 0x3800, m0
+0x05,0x00,0x09,0xd7,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_max_u16 v5, src_scc, vcc_lo           ; encoding: [0x05,0x00,0x09,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x09,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_max_u16 v255, 0xfe0b, vcc_hi          ; encoding: [0xff,0x00,0x09,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0xff,0x00,0x09,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_maxmin_num_f16 v5, v1, v2, s3         ; encoding: [0x05,0x00,0x6b,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x6b,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_maxmin_num_f16 v5, v255, s2, s105     ; encoding: [0x05,0x00,0x6b,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x6b,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_maxmin_num_f16 v5, s1, v255, exec_hi  ; encoding: [0x05,0x00,0x6b,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x6b,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_maxmin_num_f16 v5, s105, s105, exec_lo ; encoding: [0x05,0x00,0x6b,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x6b,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_maxmin_num_f16 v5, vcc_lo, ttmp15, v3 ; encoding: [0x05,0x00,0x6b,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x6b,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_maxmin_num_f16 v5, vcc_hi, 0xfe0b, v255 ; encoding: [0x05,0x00,0x6b,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x6b,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_maxmin_num_f16 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x6b,0xd6,0x7b,0xfa,0xed,0xe1]
+0x05,0x07,0x6b,0xd6,0x7b,0xfa,0xed,0xe1
+
+# GFX12: v_maxmin_num_f16 v5, m0, 0.5, m0        ; encoding: [0x05,0x00,0x6b,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x6b,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_maxmin_num_f16 v5, |exec_lo|, -1, vcc_hi ; encoding: [0x05,0x01,0x6b,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x01,0x6b,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_maxmin_num_f16 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x6b,0xd6,0x7f,0xf8,0xa8,0xa1]
+0x05,0x05,0x6b,0xd6,0x7f,0xf8,0xa8,0xa1
+
+# GFX12: v_maxmin_num_f16 v5, null, exec_lo, -|0xfe0b| ; encoding: [0x05,0x04,0x6b,0xd6,0x7c,0xfc,0xfc,0x83,0x0b,0xfe,0x00,0x00]
+0x05,0x04,0x6b,0xd6,0x7c,0xfc,0xfc,0x83,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_maxmin_num_f16 v5, -1, -|exec_hi|, -|src_scc| ; encoding: [0x05,0x06,0x6b,0xd6,0xc1,0xfe,0xf4,0xc3]
+0x05,0x06,0x6b,0xd6,0xc1,0xfe,0xf4,0xc3
+
+# GFX12: v_maxmin_num_f16 v5, 0.5, -m0, 0.5 mul:2 ; encoding: [0x05,0x00,0x6b,0xd6,0xf0,0xfa,0xc0,0x4b]
+0x05,0x00,0x6b,0xd6,0xf0,0xfa,0xc0,0x4b
+
+# GFX12: v_maxmin_num_f16 v5, -src_scc, |vcc_lo|, -1 mul:4 ; encoding: [0x05,0x02,0x6b,0xd6,0xfd,0xd4,0x04,0x33]
+0x05,0x02,0x6b,0xd6,0xfd,0xd4,0x04,0x33
+
+# GFX12: v_maxmin_num_f16 v255, -|0xfe0b|, -|vcc_hi|, null clamp div:2 ; encoding: [0xff,0x83,0x6b,0xd6,0xff,0xd6,0xf0,0x79,0x0b,0xfe,0x00,0x00]
+0xff,0x83,0x6b,0xd6,0xff,0xd6,0xf0,0x79,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_maxmin_num_f32 v5, v1, v2, s3         ; encoding: [0x05,0x00,0x69,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x69,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_maxmin_num_f32 v5, v255, s2, s105     ; encoding: [0x05,0x00,0x69,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x69,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_maxmin_num_f32 v5, s1, v255, exec_hi  ; encoding: [0x05,0x00,0x69,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x69,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_maxmin_num_f32 v5, s105, s105, exec_lo ; encoding: [0x05,0x00,0x69,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x69,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_maxmin_num_f32 v5, vcc_lo, ttmp15, v3 ; encoding: [0x05,0x00,0x69,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x69,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_maxmin_num_f32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x69,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x69,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_maxmin_num_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x69,0xd6,0x7b,0xfa,0xed,0xe1]
+0x05,0x07,0x69,0xd6,0x7b,0xfa,0xed,0xe1
+
+# GFX12: v_maxmin_num_f32 v5, m0, 0.5, m0        ; encoding: [0x05,0x00,0x69,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x69,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_maxmin_num_f32 v5, |exec_lo|, -1, vcc_hi ; encoding: [0x05,0x01,0x69,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x01,0x69,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_maxmin_num_f32 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x69,0xd6,0x7f,0xf8,0xa8,0xa1]
+0x05,0x05,0x69,0xd6,0x7f,0xf8,0xa8,0xa1
+
+# GFX12: v_maxmin_num_f32 v5, null, exec_lo, -|0xaf123456| ; encoding: [0x05,0x04,0x69,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+0x05,0x04,0x69,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf
+
+# GFX12: v_maxmin_num_f32 v5, -1, -|exec_hi|, -|src_scc| ; encoding: [0x05,0x06,0x69,0xd6,0xc1,0xfe,0xf4,0xc3]
+0x05,0x06,0x69,0xd6,0xc1,0xfe,0xf4,0xc3
+
+# GFX12: v_maxmin_num_f32 v5, 0.5, -m0, 0.5 mul:2 ; encoding: [0x05,0x00,0x69,0xd6,0xf0,0xfa,0xc0,0x4b]
+0x05,0x00,0x69,0xd6,0xf0,0xfa,0xc0,0x4b
+
+# GFX12: v_maxmin_num_f32 v5, -src_scc, |vcc_lo|, -1 mul:4 ; encoding: [0x05,0x02,0x69,0xd6,0xfd,0xd4,0x04,0x33]
+0x05,0x02,0x69,0xd6,0xfd,0xd4,0x04,0x33
+
+# GFX12: v_maxmin_num_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2 ; encoding: [0xff,0x83,0x69,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+0xff,0x83,0x69,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf
+
+# GFX12: v_maxmin_i32 v5, v1, v2, s3             ; encoding: [0x05,0x00,0x64,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x64,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_maxmin_i32 v5, v255, s2, s105         ; encoding: [0x05,0x00,0x64,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x64,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_maxmin_i32 v5, s1, v255, exec_hi      ; encoding: [0x05,0x00,0x64,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x64,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_maxmin_i32 v5, s105, s105, exec_lo    ; encoding: [0x05,0x00,0x64,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x64,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_maxmin_i32 v5, vcc_lo, ttmp15, v3     ; encoding: [0x05,0x00,0x64,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x64,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_maxmin_i32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x64,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x64,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_maxmin_i32 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x00,0x64,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x64,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_maxmin_i32 v5, m0, 0.5, m0            ; encoding: [0x05,0x00,0x64,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x64,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_maxmin_i32 v5, exec_lo, -1, vcc_hi    ; encoding: [0x05,0x00,0x64,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x64,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_maxmin_i32 v5, exec_hi, null, vcc_lo  ; encoding: [0x05,0x00,0x64,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x64,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_maxmin_i32 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x64,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x64,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_maxmin_i32 v5, -1, exec_hi, src_scc   ; encoding: [0x05,0x00,0x64,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x64,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_maxmin_i32 v5, 0.5, m0, 0.5           ; encoding: [0x05,0x00,0x64,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x64,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_maxmin_i32 v5, src_scc, vcc_lo, -1    ; encoding: [0x05,0x00,0x64,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x64,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_maxmin_i32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x64,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x64,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_maxmin_u32 v5, v1, v2, s3             ; encoding: [0x05,0x00,0x62,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x62,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_maxmin_u32 v5, v255, s2, s105         ; encoding: [0x05,0x00,0x62,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x62,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_maxmin_u32 v5, s1, v255, exec_hi      ; encoding: [0x05,0x00,0x62,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x62,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_maxmin_u32 v5, s105, s105, exec_lo    ; encoding: [0x05,0x00,0x62,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x62,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_maxmin_u32 v5, vcc_lo, ttmp15, v3     ; encoding: [0x05,0x00,0x62,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x62,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_maxmin_u32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x62,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x62,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_maxmin_u32 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x00,0x62,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x62,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_maxmin_u32 v5, m0, 0.5, m0            ; encoding: [0x05,0x00,0x62,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x62,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_maxmin_u32 v5, exec_lo, -1, vcc_hi    ; encoding: [0x05,0x00,0x62,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x62,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_maxmin_u32 v5, exec_hi, null, vcc_lo  ; encoding: [0x05,0x00,0x62,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x62,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_maxmin_u32 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x62,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x62,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_maxmin_u32 v5, -1, exec_hi, src_scc   ; encoding: [0x05,0x00,0x62,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x62,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_maxmin_u32 v5, 0.5, m0, 0.5           ; encoding: [0x05,0x00,0x62,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x62,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_maxmin_u32 v5, src_scc, vcc_lo, -1    ; encoding: [0x05,0x00,0x62,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x62,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_maxmin_u32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x62,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x62,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mbcnt_hi_u32_b32 v5, v1, v2           ; encoding: [0x05,0x00,0x20,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x20,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_mbcnt_hi_u32_b32 v5, v255, v255       ; encoding: [0x05,0x00,0x20,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x20,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_mbcnt_hi_u32_b32 v5, s1, s2           ; encoding: [0x05,0x00,0x20,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x20,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_mbcnt_hi_u32_b32 v5, s105, s105       ; encoding: [0x05,0x00,0x20,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x20,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_mbcnt_hi_u32_b32 v5, vcc_lo, ttmp15   ; encoding: [0x05,0x00,0x20,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x20,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_mbcnt_hi_u32_b32 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x20,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x20,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mbcnt_hi_u32_b32 v5, ttmp15, src_scc  ; encoding: [0x05,0x00,0x20,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x20,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_mbcnt_hi_u32_b32 v5, m0, 0.5          ; encoding: [0x05,0x00,0x20,0xd7,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x20,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_mbcnt_hi_u32_b32 v5, exec_lo, -1      ; encoding: [0x05,0x00,0x20,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x20,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_mbcnt_hi_u32_b32 v5, exec_hi, null    ; encoding: [0x05,0x00,0x20,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x20,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_mbcnt_hi_u32_b32 v5, null, exec_lo    ; encoding: [0x05,0x00,0x20,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x20,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_mbcnt_hi_u32_b32 v5, -1, exec_hi      ; encoding: [0x05,0x00,0x20,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x20,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_mbcnt_hi_u32_b32 v5, 0.5, m0          ; encoding: [0x05,0x00,0x20,0xd7,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x20,0xd7,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_mbcnt_hi_u32_b32 v5, src_scc, vcc_lo  ; encoding: [0x05,0x00,0x20,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x20,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_mbcnt_hi_u32_b32 v255, 0xaf123456, vcc_hi ; encoding: [0xff,0x00,0x20,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x20,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mbcnt_lo_u32_b32 v5, v1, v2           ; encoding: [0x05,0x00,0x1f,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x1f,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_mbcnt_lo_u32_b32 v5, v255, v255       ; encoding: [0x05,0x00,0x1f,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x1f,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_mbcnt_lo_u32_b32 v5, s1, s2           ; encoding: [0x05,0x00,0x1f,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x1f,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_mbcnt_lo_u32_b32 v5, s105, s105       ; encoding: [0x05,0x00,0x1f,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x1f,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_mbcnt_lo_u32_b32 v5, vcc_lo, ttmp15   ; encoding: [0x05,0x00,0x1f,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x1f,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_mbcnt_lo_u32_b32 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x1f,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x1f,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mbcnt_lo_u32_b32 v5, ttmp15, src_scc  ; encoding: [0x05,0x00,0x1f,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x1f,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_mbcnt_lo_u32_b32 v5, m0, 0.5          ; encoding: [0x05,0x00,0x1f,0xd7,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x1f,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_mbcnt_lo_u32_b32 v5, exec_lo, -1      ; encoding: [0x05,0x00,0x1f,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x1f,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_mbcnt_lo_u32_b32 v5, exec_hi, null    ; encoding: [0x05,0x00,0x1f,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x1f,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_mbcnt_lo_u32_b32 v5, null, exec_lo    ; encoding: [0x05,0x00,0x1f,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x1f,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_mbcnt_lo_u32_b32 v5, -1, exec_hi      ; encoding: [0x05,0x00,0x1f,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x1f,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_mbcnt_lo_u32_b32 v5, 0.5, m0          ; encoding: [0x05,0x00,0x1f,0xd7,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x1f,0xd7,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_mbcnt_lo_u32_b32 v5, src_scc, vcc_lo  ; encoding: [0x05,0x00,0x1f,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x1f,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_mbcnt_lo_u32_b32 v255, 0xaf123456, vcc_hi ; encoding: [0xff,0x00,0x1f,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x1f,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_med3_num_f16 v5, v1, v2, s3           ; encoding: [0x05,0x00,0x32,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x32,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_med3_num_f16 v5, v255, s2, s105       ; encoding: [0x05,0x00,0x32,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x32,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_med3_num_f16 v5, s1, v255, exec_hi    ; encoding: [0x05,0x00,0x32,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x32,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_med3_num_f16 v5, s105, s105, exec_lo  ; encoding: [0x05,0x00,0x32,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x32,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_med3_num_f16 v5, vcc_lo, ttmp15, v3   ; encoding: [0x05,0x00,0x32,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x32,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_med3_num_f16 v5, vcc_hi, 0xfe0b, v255 ; encoding: [0x05,0x00,0x32,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x32,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_med3_num_f16 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x32,0xd6,0x7b,0xfa,0xed,0xe1]
+0x05,0x07,0x32,0xd6,0x7b,0xfa,0xed,0xe1
+
+# GFX12: v_med3_num_f16 v5, m0, 0.5, m0          ; encoding: [0x05,0x00,0x32,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x32,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_med3_num_f16 v5, |exec_lo|, -1, vcc_hi ; encoding: [0x05,0x01,0x32,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x01,0x32,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_med3_num_f16 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x32,0xd6,0x7f,0xf8,0xa8,0xa1]
+0x05,0x05,0x32,0xd6,0x7f,0xf8,0xa8,0xa1
+
+# GFX12: v_med3_num_f16 v5, null, exec_lo, -|0xfe0b| op_sel:[1,1,1,1] ; encoding: [0x05,0x7c,0x32,0xd6,0x7c,0xfc,0xfc,0x83,0x0b,0xfe,0x00,0x00]
+0x05,0x7c,0x32,0xd6,0x7c,0xfc,0xfc,0x83,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_med3_num_f16 v5, -1, -|exec_hi|, -|src_scc| op_sel:[1,0,0,0] ; encoding: [0x05,0x0e,0x32,0xd6,0xc1,0xfe,0xf4,0xc3]
+0x05,0x0e,0x32,0xd6,0xc1,0xfe,0xf4,0xc3
+
+# GFX12: v_med3_num_f16 v5, 0.5, -m0, 0.5 op_sel:[0,1,0,0] ; encoding: [0x05,0x10,0x32,0xd6,0xf0,0xfa,0xc0,0x43]
+0x05,0x10,0x32,0xd6,0xf0,0xfa,0xc0,0x43
+
+# GFX12: v_med3_num_f16 v5, -src_scc, |vcc_lo|, -1 op_sel:[0,0,1,0] ; encoding: [0x05,0x22,0x32,0xd6,0xfd,0xd4,0x04,0x23]
+0x05,0x22,0x32,0xd6,0xfd,0xd4,0x04,0x23
+
+# GFX12: v_med3_num_f16 v255, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] clamp ; encoding: [0xff,0xc3,0x32,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
+0xff,0xc3,0x32,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_med3_num_f32 v5, v1, v2, s3           ; encoding: [0x05,0x00,0x31,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x31,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_med3_num_f32 v5, v255, s2, s105       ; encoding: [0x05,0x00,0x31,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x31,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_med3_num_f32 v5, s1, v255, exec_hi    ; encoding: [0x05,0x00,0x31,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x31,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_med3_num_f32 v5, s105, s105, exec_lo  ; encoding: [0x05,0x00,0x31,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x31,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_med3_num_f32 v5, vcc_lo, ttmp15, v3   ; encoding: [0x05,0x00,0x31,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x31,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_med3_num_f32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x31,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x31,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_med3_num_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x31,0xd6,0x7b,0xfa,0xed,0xe1]
+0x05,0x07,0x31,0xd6,0x7b,0xfa,0xed,0xe1
+
+# GFX12: v_med3_num_f32 v5, m0, 0.5, m0          ; encoding: [0x05,0x00,0x31,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x31,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_med3_num_f32 v5, |exec_lo|, -1, vcc_hi ; encoding: [0x05,0x01,0x31,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x01,0x31,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_med3_num_f32 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x31,0xd6,0x7f,0xf8,0xa8,0xa1]
+0x05,0x05,0x31,0xd6,0x7f,0xf8,0xa8,0xa1
+
+# GFX12: v_med3_num_f32 v5, null, exec_lo, -|0xaf123456| ; encoding: [0x05,0x04,0x31,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+0x05,0x04,0x31,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf
+
+# GFX12: v_med3_num_f32 v5, -1, -|exec_hi|, -|src_scc| ; encoding: [0x05,0x06,0x31,0xd6,0xc1,0xfe,0xf4,0xc3]
+0x05,0x06,0x31,0xd6,0xc1,0xfe,0xf4,0xc3
+
+# GFX12: v_med3_num_f32 v5, 0.5, -m0, 0.5 mul:2  ; encoding: [0x05,0x00,0x31,0xd6,0xf0,0xfa,0xc0,0x4b]
+0x05,0x00,0x31,0xd6,0xf0,0xfa,0xc0,0x4b
+
+# GFX12: v_med3_num_f32 v5, -src_scc, |vcc_lo|, -1 mul:4 ; encoding: [0x05,0x02,0x31,0xd6,0xfd,0xd4,0x04,0x33]
+0x05,0x02,0x31,0xd6,0xfd,0xd4,0x04,0x33
+
+# GFX12: v_med3_num_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2 ; encoding: [0xff,0x83,0x31,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+0xff,0x83,0x31,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf
+
+# GFX12: v_med3_i16 v5, v1, v2, s3               ; encoding: [0x05,0x00,0x50,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x50,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_med3_i16 v5, v255, s2, s105           ; encoding: [0x05,0x00,0x50,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x50,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_med3_i16 v5, s1, v255, exec_hi        ; encoding: [0x05,0x00,0x50,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x50,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_med3_i16 v5, s105, s105, exec_lo      ; encoding: [0x05,0x00,0x50,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x50,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_med3_i16 v5, vcc_lo, ttmp15, v3       ; encoding: [0x05,0x00,0x50,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x50,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_med3_i16 v5, vcc_hi, 0xfe0b, v255     ; encoding: [0x05,0x00,0x50,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x50,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_med3_i16 v5, ttmp15, src_scc, ttmp15  ; encoding: [0x05,0x00,0x50,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x50,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_med3_i16 v5, m0, 0x3800, m0
+0x05,0x00,0x50,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_med3_i16 v5, exec_lo, -1, vcc_hi      ; encoding: [0x05,0x00,0x50,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x50,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_med3_i16 v5, exec_hi, null, vcc_lo    ; encoding: [0x05,0x00,0x50,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x50,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_med3_i16 v5, null, exec_lo, 0xfe0b op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x50,0xd6,0x7c,0xfc,0xfc,0x03,0x0b,0xfe,0x00,0x00]
+0x05,0x78,0x50,0xd6,0x7c,0xfc,0xfc,0x03,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_med3_i16 v5, -1, exec_hi, src_scc op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x50,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x08,0x50,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_med3_i16 v5, 0x3800, m0, 0x3800 op_sel:[0,1,0,0]
+0x05,0x10,0x50,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_med3_i16 v5, src_scc, vcc_lo, -1 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x50,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x20,0x50,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_med3_i16 v255, 0xfe0b, vcc_hi, null op_sel:[0,0,0,1] ; encoding: [0xff,0x40,0x50,0xd6,0xff,0xd6,0xf0,0x01,0x0b,0xfe,0x00,0x00]
+0xff,0x40,0x50,0xd6,0xff,0xd6,0xf0,0x01,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_med3_i32 v5, v1, v2, s3               ; encoding: [0x05,0x00,0x20,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x20,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_med3_i32 v5, v255, s2, s105           ; encoding: [0x05,0x00,0x20,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x20,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_med3_i32 v5, s1, v255, exec_hi        ; encoding: [0x05,0x00,0x20,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x20,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_med3_i32 v5, s105, s105, exec_lo      ; encoding: [0x05,0x00,0x20,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x20,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_med3_i32 v5, vcc_lo, ttmp15, v3       ; encoding: [0x05,0x00,0x20,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x20,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_med3_i32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x20,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x20,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_med3_i32 v5, ttmp15, src_scc, ttmp15  ; encoding: [0x05,0x00,0x20,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x20,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_med3_i32 v5, m0, 0.5, m0              ; encoding: [0x05,0x00,0x20,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x20,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_med3_i32 v5, exec_lo, -1, vcc_hi      ; encoding: [0x05,0x00,0x20,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x20,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_med3_i32 v5, exec_hi, null, vcc_lo    ; encoding: [0x05,0x00,0x20,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x20,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_med3_i32 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x20,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x20,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_med3_i32 v5, -1, exec_hi, src_scc     ; encoding: [0x05,0x00,0x20,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x20,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_med3_i32 v5, 0.5, m0, 0.5             ; encoding: [0x05,0x00,0x20,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x20,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_med3_i32 v5, src_scc, vcc_lo, -1      ; encoding: [0x05,0x00,0x20,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x20,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_med3_i32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x20,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x20,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_med3_u16 v5, v1, v2, s3               ; encoding: [0x05,0x00,0x51,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x51,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_med3_u16 v5, v255, s2, s105           ; encoding: [0x05,0x00,0x51,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x51,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_med3_u16 v5, s1, v255, exec_hi        ; encoding: [0x05,0x00,0x51,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x51,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_med3_u16 v5, s105, s105, exec_lo      ; encoding: [0x05,0x00,0x51,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x51,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_med3_u16 v5, vcc_lo, ttmp15, v3       ; encoding: [0x05,0x00,0x51,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x51,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_med3_u16 v5, vcc_hi, 0xfe0b, v255     ; encoding: [0x05,0x00,0x51,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x51,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_med3_u16 v5, ttmp15, src_scc, ttmp15  ; encoding: [0x05,0x00,0x51,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x51,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_med3_u16 v5, m0, 0x3800, m0
+0x05,0x00,0x51,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_med3_u16 v5, exec_lo, -1, vcc_hi      ; encoding: [0x05,0x00,0x51,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x51,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_med3_u16 v5, exec_hi, null, vcc_lo    ; encoding: [0x05,0x00,0x51,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x51,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_med3_u16 v5, null, exec_lo, 0xfe0b op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x51,0xd6,0x7c,0xfc,0xfc,0x03,0x0b,0xfe,0x00,0x00]
+0x05,0x78,0x51,0xd6,0x7c,0xfc,0xfc,0x03,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_med3_u16 v5, -1, exec_hi, src_scc op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x51,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x08,0x51,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_med3_u16 v5, 0x3800, m0, 0x3800 op_sel:[0,1,0,0]
+0x05,0x10,0x51,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_med3_u16 v5, src_scc, vcc_lo, -1 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x51,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x20,0x51,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_med3_u16 v255, 0xfe0b, vcc_hi, null op_sel:[0,0,0,1] ; encoding: [0xff,0x40,0x51,0xd6,0xff,0xd6,0xf0,0x01,0x0b,0xfe,0x00,0x00]
+0xff,0x40,0x51,0xd6,0xff,0xd6,0xf0,0x01,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_med3_u32 v5, v1, v2, s3               ; encoding: [0x05,0x00,0x21,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x21,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_med3_u32 v5, v255, s2, s105           ; encoding: [0x05,0x00,0x21,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x21,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_med3_u32 v5, s1, v255, exec_hi        ; encoding: [0x05,0x00,0x21,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x21,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_med3_u32 v5, s105, s105, exec_lo      ; encoding: [0x05,0x00,0x21,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x21,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_med3_u32 v5, vcc_lo, ttmp15, v3       ; encoding: [0x05,0x00,0x21,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x21,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_med3_u32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x21,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x21,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_med3_u32 v5, ttmp15, src_scc, ttmp15  ; encoding: [0x05,0x00,0x21,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x21,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_med3_u32 v5, m0, 0.5, m0              ; encoding: [0x05,0x00,0x21,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x21,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_med3_u32 v5, exec_lo, -1, vcc_hi      ; encoding: [0x05,0x00,0x21,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x21,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_med3_u32 v5, exec_hi, null, vcc_lo    ; encoding: [0x05,0x00,0x21,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x21,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_med3_u32 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x21,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x21,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_med3_u32 v5, -1, exec_hi, src_scc     ; encoding: [0x05,0x00,0x21,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x21,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_med3_u32 v5, 0.5, m0, 0.5             ; encoding: [0x05,0x00,0x21,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x21,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_med3_u32 v5, src_scc, vcc_lo, -1      ; encoding: [0x05,0x00,0x21,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x21,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_med3_u32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x21,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x21,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_min3_num_f16 v5, v1, v2, s3           ; encoding: [0x05,0x00,0x2b,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x2b,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_min3_num_f16 v5, v255, s2, s105       ; encoding: [0x05,0x00,0x2b,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x2b,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_min3_num_f16 v5, s1, v255, exec_hi    ; encoding: [0x05,0x00,0x2b,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x2b,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_min3_num_f16 v5, s105, s105, exec_lo  ; encoding: [0x05,0x00,0x2b,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x2b,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_min3_num_f16 v5, vcc_lo, ttmp15, v3   ; encoding: [0x05,0x00,0x2b,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x2b,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_min3_num_f16 v5, vcc_hi, 0xfe0b, v255 ; encoding: [0x05,0x00,0x2b,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x2b,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_min3_num_f16 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x2b,0xd6,0x7b,0xfa,0xed,0xe1]
+0x05,0x07,0x2b,0xd6,0x7b,0xfa,0xed,0xe1
+
+# GFX12: v_min3_num_f16 v5, m0, 0.5, m0          ; encoding: [0x05,0x00,0x2b,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x2b,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_min3_num_f16 v5, |exec_lo|, -1, vcc_hi ; encoding: [0x05,0x01,0x2b,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x01,0x2b,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_min3_num_f16 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x2b,0xd6,0x7f,0xf8,0xa8,0xa1]
+0x05,0x05,0x2b,0xd6,0x7f,0xf8,0xa8,0xa1
+
+# GFX12: v_min3_num_f16 v5, null, exec_lo, -|0xfe0b| op_sel:[1,1,1,1] ; encoding: [0x05,0x7c,0x2b,0xd6,0x7c,0xfc,0xfc,0x83,0x0b,0xfe,0x00,0x00]
+0x05,0x7c,0x2b,0xd6,0x7c,0xfc,0xfc,0x83,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_min3_num_f16 v5, -1, -|exec_hi|, -|src_scc| op_sel:[1,0,0,0] ; encoding: [0x05,0x0e,0x2b,0xd6,0xc1,0xfe,0xf4,0xc3]
+0x05,0x0e,0x2b,0xd6,0xc1,0xfe,0xf4,0xc3
+
+# GFX12: v_min3_num_f16 v5, 0.5, -m0, 0.5 op_sel:[0,1,0,0] ; encoding: [0x05,0x10,0x2b,0xd6,0xf0,0xfa,0xc0,0x43]
+0x05,0x10,0x2b,0xd6,0xf0,0xfa,0xc0,0x43
+
+# GFX12: v_min3_num_f16 v5, -src_scc, |vcc_lo|, -1 op_sel:[0,0,1,0] ; encoding: [0x05,0x22,0x2b,0xd6,0xfd,0xd4,0x04,0x23]
+0x05,0x22,0x2b,0xd6,0xfd,0xd4,0x04,0x23
+
+# GFX12: v_min3_num_f16 v255, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] clamp ; encoding: [0xff,0xc3,0x2b,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
+0xff,0xc3,0x2b,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_min3_num_f32 v5, v1, v2, s3           ; encoding: [0x05,0x00,0x29,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x29,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_min3_num_f32 v5, v255, s2, s105       ; encoding: [0x05,0x00,0x29,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x29,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_min3_num_f32 v5, s1, v255, exec_hi    ; encoding: [0x05,0x00,0x29,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x29,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_min3_num_f32 v5, s105, s105, exec_lo  ; encoding: [0x05,0x00,0x29,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x29,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_min3_num_f32 v5, vcc_lo, ttmp15, v3   ; encoding: [0x05,0x00,0x29,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x29,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_min3_num_f32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x29,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x29,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_min3_num_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x29,0xd6,0x7b,0xfa,0xed,0xe1]
+0x05,0x07,0x29,0xd6,0x7b,0xfa,0xed,0xe1
+
+# GFX12: v_min3_num_f32 v5, m0, 0.5, m0          ; encoding: [0x05,0x00,0x29,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x29,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_min3_num_f32 v5, |exec_lo|, -1, vcc_hi ; encoding: [0x05,0x01,0x29,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x01,0x29,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_min3_num_f32 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x29,0xd6,0x7f,0xf8,0xa8,0xa1]
+0x05,0x05,0x29,0xd6,0x7f,0xf8,0xa8,0xa1
+
+# GFX12: v_min3_num_f32 v5, null, exec_lo, -|0xaf123456| ; encoding: [0x05,0x04,0x29,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+0x05,0x04,0x29,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf
+
+# GFX12: v_min3_num_f32 v5, -1, -|exec_hi|, -|src_scc| ; encoding: [0x05,0x06,0x29,0xd6,0xc1,0xfe,0xf4,0xc3]
+0x05,0x06,0x29,0xd6,0xc1,0xfe,0xf4,0xc3
+
+# GFX12: v_min3_num_f32 v5, 0.5, -m0, 0.5 mul:2  ; encoding: [0x05,0x00,0x29,0xd6,0xf0,0xfa,0xc0,0x4b]
+0x05,0x00,0x29,0xd6,0xf0,0xfa,0xc0,0x4b
+
+# GFX12: v_min3_num_f32 v5, -src_scc, |vcc_lo|, -1 mul:4 ; encoding: [0x05,0x02,0x29,0xd6,0xfd,0xd4,0x04,0x33]
+0x05,0x02,0x29,0xd6,0xfd,0xd4,0x04,0x33
+
+# GFX12: v_min3_num_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2 ; encoding: [0xff,0x83,0x29,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+0xff,0x83,0x29,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf
+
+# GFX12: v_min3_i16 v5, v1, v2, s3               ; encoding: [0x05,0x00,0x4a,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x4a,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_min3_i16 v5, v255, s2, s105           ; encoding: [0x05,0x00,0x4a,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x4a,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_min3_i16 v5, s1, v255, exec_hi        ; encoding: [0x05,0x00,0x4a,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x4a,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_min3_i16 v5, s105, s105, exec_lo      ; encoding: [0x05,0x00,0x4a,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x4a,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_min3_i16 v5, vcc_lo, ttmp15, v3       ; encoding: [0x05,0x00,0x4a,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x4a,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_min3_i16 v5, vcc_hi, 0xfe0b, v255     ; encoding: [0x05,0x00,0x4a,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x4a,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_min3_i16 v5, ttmp15, src_scc, ttmp15  ; encoding: [0x05,0x00,0x4a,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x4a,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_min3_i16 v5, m0, 0x3800, m0
+0x05,0x00,0x4a,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_min3_i16 v5, exec_lo, -1, vcc_hi      ; encoding: [0x05,0x00,0x4a,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x4a,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_min3_i16 v5, exec_hi, null, vcc_lo    ; encoding: [0x05,0x00,0x4a,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x4a,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_min3_i16 v5, null, exec_lo, 0xfe0b op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x4a,0xd6,0x7c,0xfc,0xfc,0x03,0x0b,0xfe,0x00,0x00]
+0x05,0x78,0x4a,0xd6,0x7c,0xfc,0xfc,0x03,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_min3_i16 v5, -1, exec_hi, src_scc op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x4a,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x08,0x4a,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_min3_i16 v5, 0x3800, m0, 0x3800 op_sel:[0,1,0,0]
+0x05,0x10,0x4a,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_min3_i16 v5, src_scc, vcc_lo, -1 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x4a,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x20,0x4a,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_min3_i16 v255, 0xfe0b, vcc_hi, null op_sel:[0,0,0,1] ; encoding: [0xff,0x40,0x4a,0xd6,0xff,0xd6,0xf0,0x01,0x0b,0xfe,0x00,0x00]
+0xff,0x40,0x4a,0xd6,0xff,0xd6,0xf0,0x01,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_min3_i32 v5, v1, v2, s3               ; encoding: [0x05,0x00,0x1a,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x1a,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_min3_i32 v5, v255, s2, s105           ; encoding: [0x05,0x00,0x1a,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x1a,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_min3_i32 v5, s1, v255, exec_hi        ; encoding: [0x05,0x00,0x1a,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x1a,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_min3_i32 v5, s105, s105, exec_lo      ; encoding: [0x05,0x00,0x1a,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x1a,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_min3_i32 v5, vcc_lo, ttmp15, v3       ; encoding: [0x05,0x00,0x1a,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x1a,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_min3_i32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x1a,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x1a,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_min3_i32 v5, ttmp15, src_scc, ttmp15  ; encoding: [0x05,0x00,0x1a,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x1a,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_min3_i32 v5, m0, 0.5, m0              ; encoding: [0x05,0x00,0x1a,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x1a,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_min3_i32 v5, exec_lo, -1, vcc_hi      ; encoding: [0x05,0x00,0x1a,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x1a,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_min3_i32 v5, exec_hi, null, vcc_lo    ; encoding: [0x05,0x00,0x1a,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x1a,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_min3_i32 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x1a,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x1a,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_min3_i32 v5, -1, exec_hi, src_scc     ; encoding: [0x05,0x00,0x1a,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x1a,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_min3_i32 v5, 0.5, m0, 0.5             ; encoding: [0x05,0x00,0x1a,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x1a,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_min3_i32 v5, src_scc, vcc_lo, -1      ; encoding: [0x05,0x00,0x1a,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x1a,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_min3_i32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x1a,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x1a,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_min3_u16 v5, v1, v2, s3               ; encoding: [0x05,0x00,0x4b,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x4b,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_min3_u16 v5, v255, s2, s105           ; encoding: [0x05,0x00,0x4b,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x4b,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_min3_u16 v5, s1, v255, exec_hi        ; encoding: [0x05,0x00,0x4b,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x4b,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_min3_u16 v5, s105, s105, exec_lo      ; encoding: [0x05,0x00,0x4b,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x4b,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_min3_u16 v5, vcc_lo, ttmp15, v3       ; encoding: [0x05,0x00,0x4b,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x4b,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_min3_u16 v5, vcc_hi, 0xfe0b, v255     ; encoding: [0x05,0x00,0x4b,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x4b,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_min3_u16 v5, ttmp15, src_scc, ttmp15  ; encoding: [0x05,0x00,0x4b,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x4b,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_min3_u16 v5, m0, 0x3800, m0
+0x05,0x00,0x4b,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_min3_u16 v5, exec_lo, -1, vcc_hi      ; encoding: [0x05,0x00,0x4b,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x4b,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_min3_u16 v5, exec_hi, null, vcc_lo    ; encoding: [0x05,0x00,0x4b,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x4b,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_min3_u16 v5, null, exec_lo, 0xfe0b op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x4b,0xd6,0x7c,0xfc,0xfc,0x03,0x0b,0xfe,0x00,0x00]
+0x05,0x78,0x4b,0xd6,0x7c,0xfc,0xfc,0x03,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_min3_u16 v5, -1, exec_hi, src_scc op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x4b,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x08,0x4b,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_min3_u16 v5, 0x3800, m0, 0x3800 op_sel:[0,1,0,0]
+0x05,0x10,0x4b,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_min3_u16 v5, src_scc, vcc_lo, -1 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x4b,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x20,0x4b,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_min3_u16 v255, 0xfe0b, vcc_hi, null op_sel:[0,0,0,1] ; encoding: [0xff,0x40,0x4b,0xd6,0xff,0xd6,0xf0,0x01,0x0b,0xfe,0x00,0x00]
+0xff,0x40,0x4b,0xd6,0xff,0xd6,0xf0,0x01,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_min3_u32 v5, v1, v2, s3               ; encoding: [0x05,0x00,0x1b,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x1b,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_min3_u32 v5, v255, s2, s105           ; encoding: [0x05,0x00,0x1b,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x1b,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_min3_u32 v5, s1, v255, exec_hi        ; encoding: [0x05,0x00,0x1b,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x1b,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_min3_u32 v5, s105, s105, exec_lo      ; encoding: [0x05,0x00,0x1b,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x1b,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_min3_u32 v5, vcc_lo, ttmp15, v3       ; encoding: [0x05,0x00,0x1b,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x1b,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_min3_u32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x1b,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x1b,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_min3_u32 v5, ttmp15, src_scc, ttmp15  ; encoding: [0x05,0x00,0x1b,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x1b,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_min3_u32 v5, m0, 0.5, m0              ; encoding: [0x05,0x00,0x1b,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x1b,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_min3_u32 v5, exec_lo, -1, vcc_hi      ; encoding: [0x05,0x00,0x1b,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x1b,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_min3_u32 v5, exec_hi, null, vcc_lo    ; encoding: [0x05,0x00,0x1b,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x1b,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_min3_u32 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x1b,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x1b,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_min3_u32 v5, -1, exec_hi, src_scc     ; encoding: [0x05,0x00,0x1b,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x1b,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_min3_u32 v5, 0.5, m0, 0.5             ; encoding: [0x05,0x00,0x1b,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x1b,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_min3_u32 v5, src_scc, vcc_lo, -1      ; encoding: [0x05,0x00,0x1b,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x1b,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_min3_u32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x1b,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x1b,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_min_i16 v5, v1, v2                    ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x0c,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_min_i16 v5, v255, v255                ; encoding: [0x05,0x00,0x0c,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x0c,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_min_i16 v5, s1, s2                    ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x0c,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_min_i16 v5, s105, s105                ; encoding: [0x05,0x00,0x0c,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x0c,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_min_i16 v5, vcc_lo, ttmp15            ; encoding: [0x05,0x00,0x0c,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x0c,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_min_i16 v5, vcc_hi, 0xfe0b            ; encoding: [0x05,0x00,0x0c,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x0c,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_min_i16 v5, ttmp15, src_scc           ; encoding: [0x05,0x00,0x0c,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x0c,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_min_i16 v5, m0, 0x3800
+0x05,0x00,0x0c,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_min_i16 v5, exec_lo, -1               ; encoding: [0x05,0x00,0x0c,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x0c,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_min_i16 v5, exec_hi, null             ; encoding: [0x05,0x00,0x0c,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x0c,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_min_i16 v5, null, exec_lo             ; encoding: [0x05,0x00,0x0c,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x0c,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_min_i16 v5, -1, exec_hi               ; encoding: [0x05,0x00,0x0c,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x0c,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_min_i16 v5, 0x3800, m0
+0x05,0x00,0x0c,0xd7,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_min_i16 v5, src_scc, vcc_lo           ; encoding: [0x05,0x00,0x0c,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x0c,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_min_i16 v255, 0xfe0b, vcc_hi          ; encoding: [0xff,0x00,0x0c,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0xff,0x00,0x0c,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_min_u16 v5, v1, v2                    ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x0b,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_min_u16 v5, v255, v255                ; encoding: [0x05,0x00,0x0b,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x0b,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_min_u16 v5, s1, s2                    ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x0b,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_min_u16 v5, s105, s105                ; encoding: [0x05,0x00,0x0b,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x0b,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_min_u16 v5, vcc_lo, ttmp15            ; encoding: [0x05,0x00,0x0b,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x0b,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_min_u16 v5, vcc_hi, 0xfe0b            ; encoding: [0x05,0x00,0x0b,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x0b,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_min_u16 v5, ttmp15, src_scc           ; encoding: [0x05,0x00,0x0b,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x0b,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_min_u16 v5, m0, 0x3800
+0x05,0x00,0x0b,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_min_u16 v5, exec_lo, -1               ; encoding: [0x05,0x00,0x0b,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x0b,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_min_u16 v5, exec_hi, null             ; encoding: [0x05,0x00,0x0b,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x0b,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_min_u16 v5, null, exec_lo             ; encoding: [0x05,0x00,0x0b,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x0b,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_min_u16 v5, -1, exec_hi               ; encoding: [0x05,0x00,0x0b,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x0b,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_min_u16 v5, 0x3800, m0
+0x05,0x00,0x0b,0xd7,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_min_u16 v5, src_scc, vcc_lo           ; encoding: [0x05,0x00,0x0b,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x0b,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_min_u16 v255, 0xfe0b, vcc_hi          ; encoding: [0xff,0x00,0x0b,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0xff,0x00,0x0b,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_minmax_num_f16 v5, v1, v2, s3         ; encoding: [0x05,0x00,0x6a,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x6a,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_minmax_num_f16 v5, v255, s2, s105     ; encoding: [0x05,0x00,0x6a,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x6a,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_minmax_num_f16 v5, s1, v255, exec_hi  ; encoding: [0x05,0x00,0x6a,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x6a,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_minmax_num_f16 v5, s105, s105, exec_lo ; encoding: [0x05,0x00,0x6a,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x6a,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_minmax_num_f16 v5, vcc_lo, ttmp15, v3 ; encoding: [0x05,0x00,0x6a,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x6a,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_minmax_num_f16 v5, vcc_hi, 0xfe0b, v255 ; encoding: [0x05,0x00,0x6a,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x6a,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_minmax_num_f16 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x6a,0xd6,0x7b,0xfa,0xed,0xe1]
+0x05,0x07,0x6a,0xd6,0x7b,0xfa,0xed,0xe1
+
+# GFX12: v_minmax_num_f16 v5, m0, 0.5, m0        ; encoding: [0x05,0x00,0x6a,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x6a,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_minmax_num_f16 v5, |exec_lo|, -1, vcc_hi ; encoding: [0x05,0x01,0x6a,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x01,0x6a,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_minmax_num_f16 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x6a,0xd6,0x7f,0xf8,0xa8,0xa1]
+0x05,0x05,0x6a,0xd6,0x7f,0xf8,0xa8,0xa1
+
+# GFX12: v_minmax_num_f16 v5, null, exec_lo, -|0xfe0b| ; encoding: [0x05,0x04,0x6a,0xd6,0x7c,0xfc,0xfc,0x83,0x0b,0xfe,0x00,0x00]
+0x05,0x04,0x6a,0xd6,0x7c,0xfc,0xfc,0x83,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_minmax_num_f16 v5, -1, -|exec_hi|, -|src_scc| ; encoding: [0x05,0x06,0x6a,0xd6,0xc1,0xfe,0xf4,0xc3]
+0x05,0x06,0x6a,0xd6,0xc1,0xfe,0xf4,0xc3
+
+# GFX12: v_minmax_num_f16 v5, 0.5, -m0, 0.5 mul:2 ; encoding: [0x05,0x00,0x6a,0xd6,0xf0,0xfa,0xc0,0x4b]
+0x05,0x00,0x6a,0xd6,0xf0,0xfa,0xc0,0x4b
+
+# GFX12: v_minmax_num_f16 v5, -src_scc, |vcc_lo|, -1 mul:4 ; encoding: [0x05,0x02,0x6a,0xd6,0xfd,0xd4,0x04,0x33]
+0x05,0x02,0x6a,0xd6,0xfd,0xd4,0x04,0x33
+
+# GFX12: v_minmax_num_f16 v255, -|0xfe0b|, -|vcc_hi|, null clamp div:2 ; encoding: [0xff,0x83,0x6a,0xd6,0xff,0xd6,0xf0,0x79,0x0b,0xfe,0x00,0x00]
+0xff,0x83,0x6a,0xd6,0xff,0xd6,0xf0,0x79,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_minmax_num_f32 v5, v1, v2, s3         ; encoding: [0x05,0x00,0x68,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x68,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_minmax_num_f32 v5, v255, s2, s105     ; encoding: [0x05,0x00,0x68,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x68,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_minmax_num_f32 v5, s1, v255, exec_hi  ; encoding: [0x05,0x00,0x68,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x68,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_minmax_num_f32 v5, s105, s105, exec_lo ; encoding: [0x05,0x00,0x68,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x68,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_minmax_num_f32 v5, vcc_lo, ttmp15, v3 ; encoding: [0x05,0x00,0x68,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x68,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_minmax_num_f32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x68,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x68,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_minmax_num_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x68,0xd6,0x7b,0xfa,0xed,0xe1]
+0x05,0x07,0x68,0xd6,0x7b,0xfa,0xed,0xe1
+
+# GFX12: v_minmax_num_f32 v5, m0, 0.5, m0        ; encoding: [0x05,0x00,0x68,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x68,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_minmax_num_f32 v5, |exec_lo|, -1, vcc_hi ; encoding: [0x05,0x01,0x68,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x01,0x68,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_minmax_num_f32 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x68,0xd6,0x7f,0xf8,0xa8,0xa1]
+0x05,0x05,0x68,0xd6,0x7f,0xf8,0xa8,0xa1
+
+# GFX12: v_minmax_num_f32 v5, null, exec_lo, -|0xaf123456| ; encoding: [0x05,0x04,0x68,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+0x05,0x04,0x68,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf
+
+# GFX12: v_minmax_num_f32 v5, -1, -|exec_hi|, -|src_scc| ; encoding: [0x05,0x06,0x68,0xd6,0xc1,0xfe,0xf4,0xc3]
+0x05,0x06,0x68,0xd6,0xc1,0xfe,0xf4,0xc3
+
+# GFX12: v_minmax_num_f32 v5, 0.5, -m0, 0.5 mul:2 ; encoding: [0x05,0x00,0x68,0xd6,0xf0,0xfa,0xc0,0x4b]
+0x05,0x00,0x68,0xd6,0xf0,0xfa,0xc0,0x4b
+
+# GFX12: v_minmax_num_f32 v5, -src_scc, |vcc_lo|, -1 mul:4 ; encoding: [0x05,0x02,0x68,0xd6,0xfd,0xd4,0x04,0x33]
+0x05,0x02,0x68,0xd6,0xfd,0xd4,0x04,0x33
+
+# GFX12: v_minmax_num_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2 ; encoding: [0xff,0x83,0x68,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+0xff,0x83,0x68,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf
+
+# GFX12: v_minmax_i32 v5, v1, v2, s3             ; encoding: [0x05,0x00,0x65,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x65,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_minmax_i32 v5, v255, s2, s105         ; encoding: [0x05,0x00,0x65,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x65,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_minmax_i32 v5, s1, v255, exec_hi      ; encoding: [0x05,0x00,0x65,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x65,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_minmax_i32 v5, s105, s105, exec_lo    ; encoding: [0x05,0x00,0x65,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x65,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_minmax_i32 v5, vcc_lo, ttmp15, v3     ; encoding: [0x05,0x00,0x65,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x65,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_minmax_i32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x65,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x65,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_minmax_i32 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x00,0x65,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x65,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_minmax_i32 v5, m0, 0.5, m0            ; encoding: [0x05,0x00,0x65,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x65,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_minmax_i32 v5, exec_lo, -1, vcc_hi    ; encoding: [0x05,0x00,0x65,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x65,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_minmax_i32 v5, exec_hi, null, vcc_lo  ; encoding: [0x05,0x00,0x65,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x65,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_minmax_i32 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x65,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x65,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_minmax_i32 v5, -1, exec_hi, src_scc   ; encoding: [0x05,0x00,0x65,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x65,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_minmax_i32 v5, 0.5, m0, 0.5           ; encoding: [0x05,0x00,0x65,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x65,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_minmax_i32 v5, src_scc, vcc_lo, -1    ; encoding: [0x05,0x00,0x65,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x65,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_minmax_i32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x65,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x65,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_minmax_u32 v5, v1, v2, s3             ; encoding: [0x05,0x00,0x63,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x63,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_minmax_u32 v5, v255, s2, s105         ; encoding: [0x05,0x00,0x63,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x63,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_minmax_u32 v5, s1, v255, exec_hi      ; encoding: [0x05,0x00,0x63,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x63,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_minmax_u32 v5, s105, s105, exec_lo    ; encoding: [0x05,0x00,0x63,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x63,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_minmax_u32 v5, vcc_lo, ttmp15, v3     ; encoding: [0x05,0x00,0x63,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x63,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_minmax_u32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x63,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x63,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_minmax_u32 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x00,0x63,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x63,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_minmax_u32 v5, m0, 0.5, m0            ; encoding: [0x05,0x00,0x63,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x63,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_minmax_u32 v5, exec_lo, -1, vcc_hi    ; encoding: [0x05,0x00,0x63,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x63,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_minmax_u32 v5, exec_hi, null, vcc_lo  ; encoding: [0x05,0x00,0x63,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x63,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_minmax_u32 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x63,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x63,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_minmax_u32 v5, -1, exec_hi, src_scc   ; encoding: [0x05,0x00,0x63,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x63,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_minmax_u32 v5, 0.5, m0, 0.5           ; encoding: [0x05,0x00,0x63,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x63,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_minmax_u32 v5, src_scc, vcc_lo, -1    ; encoding: [0x05,0x00,0x63,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x63,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_minmax_u32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x63,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x63,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, ttmp[14:15] ; encoding: [0x05,0x00,0x3b,0xd6,0x01,0x05,0xea,0x01]
+0x05,0x00,0x3b,0xd6,0x01,0x05,0xea,0x01
+
+# GFX12: v_mqsad_pk_u16_u8 v[5:6], v[1:2], v255, ttmp[14:15] ; encoding: [0x05,0x00,0x3b,0xd6,0x01,0xff,0xeb,0x01]
+0x05,0x00,0x3b,0xd6,0x01,0xff,0xeb,0x01
+
+# GFX12: v_mqsad_pk_u16_u8 v[5:6], v[1:2], s2, ttmp[14:15] ; encoding: [0x05,0x00,0x3b,0xd6,0x01,0x05,0xe8,0x01]
+0x05,0x00,0x3b,0xd6,0x01,0x05,0xe8,0x01
+
+# GFX12: v_mqsad_pk_u16_u8 v[5:6], v[1:2], s105, ttmp[14:15] ; encoding: [0x05,0x00,0x3b,0xd6,0x01,0xd3,0xe8,0x01]
+0x05,0x00,0x3b,0xd6,0x01,0xd3,0xe8,0x01
+
+# GFX12: v_mqsad_pk_u16_u8 v[5:6], v[254:255], ttmp15, s[6:7] ; encoding: [0x05,0x00,0x3b,0xd6,0xfe,0xf7,0x18,0x00]
+0x05,0x00,0x3b,0xd6,0xfe,0xf7,0x18,0x00
+
+# GFX12: v_mqsad_pk_u16_u8 v[5:6], s[2:3], vcc_hi, v[3:4] ; encoding: [0x05,0x00,0x3b,0xd6,0x02,0xd6,0x0c,0x04]
+0x05,0x00,0x3b,0xd6,0x02,0xd6,0x0c,0x04
+
+# GFX12: v_mqsad_pk_u16_u8 v[5:6], s[104:105], vcc_lo, s[104:105] ; encoding: [0x05,0x00,0x3b,0xd6,0x68,0xd4,0xa0,0x01]
+0x05,0x00,0x3b,0xd6,0x68,0xd4,0xa0,0x01
+
+# GFX12: v_mqsad_pk_u16_u8 v[5:6], vcc, m0, v[254:255] ; encoding: [0x05,0x00,0x3b,0xd6,0x6a,0xfa,0xf8,0x07]
+0x05,0x00,0x3b,0xd6,0x6a,0xfa,0xf8,0x07
+
+# GFX12: v_mqsad_pk_u16_u8 v[5:6], ttmp[14:15], exec_hi, null ; encoding: [0x05,0x00,0x3b,0xd6,0x7a,0xfe,0xf0,0x01]
+0x05,0x00,0x3b,0xd6,0x7a,0xfe,0xf0,0x01
+
+# GFX12: v_mqsad_pk_u16_u8 v[5:6], exec, exec_lo, exec ; encoding: [0x05,0x00,0x3b,0xd6,0x7e,0xfc,0xf8,0x01]
+0x05,0x00,0x3b,0xd6,0x7e,0xfc,0xf8,0x01
+
+# GFX12: v_mqsad_pk_u16_u8 v[5:6], null, null, vcc ; encoding: [0x05,0x00,0x3b,0xd6,0x7c,0xf8,0xa8,0x01]
+0x05,0x00,0x3b,0xd6,0x7c,0xf8,0xa8,0x01
+
+# GFX12: v_mqsad_pk_u16_u8 v[5:6], -1, -1, 0xaf123456 ; encoding: [0x05,0x00,0x3b,0xd6,0xc1,0x82,0xfd,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x3b,0xd6,0xc1,0x82,0xfd,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mqsad_pk_u16_u8 v[5:6], 0.5, 0.5, src_scc ; encoding: [0x05,0x00,0x3b,0xd6,0xf0,0xe0,0xf5,0x03]
+0x05,0x00,0x3b,0xd6,0xf0,0xe0,0xf5,0x03
+
+# GFX12: v_mqsad_pk_u16_u8 v[5:6], src_scc, src_scc, 0.5 ; encoding: [0x05,0x00,0x3b,0xd6,0xfd,0xfa,0xc1,0x03]
+0x05,0x00,0x3b,0xd6,0xfd,0xfa,0xc1,0x03
+
+# GFX12: v_mqsad_pk_u16_u8 v[254:255], 0xaf123456, 0xaf123456, -1 clamp ; encoding: [0xfe,0x80,0x3b,0xd6,0xff,0xfe,0x05,0x03,0x56,0x34,0x12,0xaf]
+0xfe,0x80,0x3b,0xd6,0xff,0xfe,0x05,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mqsad_u32_u8 v[5:8], v[1:2], v2, v[252:255] ; encoding: [0x05,0x00,0x3d,0xd6,0x01,0x05,0xf2,0x07]
+0x05,0x00,0x3d,0xd6,0x01,0x05,0xf2,0x07
+
+# GFX12: v_mqsad_u32_u8 v[5:8], v[1:2], v255, v[252:255] ; encoding: [0x05,0x00,0x3d,0xd6,0x01,0xff,0xf3,0x07]
+0x05,0x00,0x3d,0xd6,0x01,0xff,0xf3,0x07
+
+# GFX12: v_mqsad_u32_u8 v[5:8], v[1:2], s2, v[252:255] ; encoding: [0x05,0x00,0x3d,0xd6,0x01,0x05,0xf0,0x07]
+0x05,0x00,0x3d,0xd6,0x01,0x05,0xf0,0x07
+
+# GFX12: v_mqsad_u32_u8 v[5:8], v[1:2], s105, v[252:255] ; encoding: [0x05,0x00,0x3d,0xd6,0x01,0xd3,0xf0,0x07]
+0x05,0x00,0x3d,0xd6,0x01,0xd3,0xf0,0x07
+
+# GFX12: v_mqsad_u32_u8 v[5:8], v[254:255], ttmp15, v[252:255] ; encoding: [0x05,0x00,0x3d,0xd6,0xfe,0xf7,0xf0,0x07]
+0x05,0x00,0x3d,0xd6,0xfe,0xf7,0xf0,0x07
+
+# GFX12: v_mqsad_u32_u8 v[5:8], s[2:3], vcc_hi, v[252:255] ; encoding: [0x05,0x00,0x3d,0xd6,0x02,0xd6,0xf0,0x07]
+0x05,0x00,0x3d,0xd6,0x02,0xd6,0xf0,0x07
+
+# GFX12: v_mqsad_u32_u8 v[5:8], s[104:105], vcc_lo, v[252:255] ; encoding: [0x05,0x00,0x3d,0xd6,0x68,0xd4,0xf0,0x07]
+0x05,0x00,0x3d,0xd6,0x68,0xd4,0xf0,0x07
+
+# GFX12: v_mqsad_u32_u8 v[5:8], vcc, m0, v[252:255] ; encoding: [0x05,0x00,0x3d,0xd6,0x6a,0xfa,0xf0,0x07]
+0x05,0x00,0x3d,0xd6,0x6a,0xfa,0xf0,0x07
+
+# GFX12: v_mqsad_u32_u8 v[5:8], ttmp[14:15], exec_hi, v[252:255] ; encoding: [0x05,0x00,0x3d,0xd6,0x7a,0xfe,0xf0,0x07]
+0x05,0x00,0x3d,0xd6,0x7a,0xfe,0xf0,0x07
+
+# GFX12: v_mqsad_u32_u8 v[5:8], exec, exec_lo, v[252:255] ; encoding: [0x05,0x00,0x3d,0xd6,0x7e,0xfc,0xf0,0x07]
+0x05,0x00,0x3d,0xd6,0x7e,0xfc,0xf0,0x07
+
+# GFX12: v_mqsad_u32_u8 v[5:8], null, null, v[252:255] ; encoding: [0x05,0x00,0x3d,0xd6,0x7c,0xf8,0xf0,0x07]
+0x05,0x00,0x3d,0xd6,0x7c,0xf8,0xf0,0x07
+
+# GFX12: v_mqsad_u32_u8 v[5:8], -1, -1, v[252:255] ; encoding: [0x05,0x00,0x3d,0xd6,0xc1,0x82,0xf1,0x07]
+0x05,0x00,0x3d,0xd6,0xc1,0x82,0xf1,0x07
+
+# GFX12: v_mqsad_u32_u8 v[5:8], 0.5, 0.5, v[252:255] ; encoding: [0x05,0x00,0x3d,0xd6,0xf0,0xe0,0xf1,0x07]
+0x05,0x00,0x3d,0xd6,0xf0,0xe0,0xf1,0x07
+
+# GFX12: v_mqsad_u32_u8 v[5:8], src_scc, src_scc, v[252:255] ; encoding: [0x05,0x00,0x3d,0xd6,0xfd,0xfa,0xf1,0x07]
+0x05,0x00,0x3d,0xd6,0xfd,0xfa,0xf1,0x07
+
+# GFX12: v_mqsad_u32_u8 v[252:255], 0xaf123456, 0xaf123456, v[3:6] clamp ; encoding: [0xfc,0x80,0x3d,0xd6,0xff,0xfe,0x0d,0x04,0x56,0x34,0x12,0xaf]
+0xfc,0x80,0x3d,0xd6,0xff,0xfe,0x0d,0x04,0x56,0x34,0x12,0xaf
+
+# GFX12: v_msad_u8 v5, v1, v2, s3                ; encoding: [0x05,0x00,0x39,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x39,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_msad_u8 v5, v255, s2, s105            ; encoding: [0x05,0x00,0x39,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x39,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_msad_u8 v5, s1, v255, exec_hi         ; encoding: [0x05,0x00,0x39,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x39,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_msad_u8 v5, s105, s105, exec_lo       ; encoding: [0x05,0x00,0x39,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x39,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_msad_u8 v5, vcc_lo, ttmp15, v3        ; encoding: [0x05,0x00,0x39,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x39,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_msad_u8 v5, vcc_hi, 0xaf123456, v255  ; encoding: [0x05,0x00,0x39,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x39,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_msad_u8 v5, ttmp15, src_scc, ttmp15   ; encoding: [0x05,0x00,0x39,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x39,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_msad_u8 v5, m0, 0.5, m0               ; encoding: [0x05,0x00,0x39,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x39,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_msad_u8 v5, exec_lo, -1, vcc_hi       ; encoding: [0x05,0x00,0x39,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x39,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_msad_u8 v5, exec_hi, null, vcc_lo     ; encoding: [0x05,0x00,0x39,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x39,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_msad_u8 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x39,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x39,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_msad_u8 v5, -1, exec_hi, src_scc      ; encoding: [0x05,0x00,0x39,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x39,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_msad_u8 v5, 0.5, m0, 0.5              ; encoding: [0x05,0x00,0x39,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x39,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_msad_u8 v5, src_scc, vcc_lo, -1       ; encoding: [0x05,0x00,0x39,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x39,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_msad_u8 v255, 0xaf123456, vcc_hi, null clamp ; encoding: [0xff,0x80,0x39,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x80,0x39,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mul_hi_i32 v5, v1, v2                 ; encoding: [0x05,0x00,0x2e,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x2e,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_mul_hi_i32 v5, v255, v255             ; encoding: [0x05,0x00,0x2e,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x2e,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_mul_hi_i32 v5, s1, s2                 ; encoding: [0x05,0x00,0x2e,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x2e,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_mul_hi_i32 v5, s105, s105             ; encoding: [0x05,0x00,0x2e,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x2e,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_mul_hi_i32 v5, vcc_lo, ttmp15         ; encoding: [0x05,0x00,0x2e,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x2e,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_mul_hi_i32 v5, vcc_hi, 0xaf123456     ; encoding: [0x05,0x00,0x2e,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x2e,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mul_hi_i32 v5, ttmp15, src_scc        ; encoding: [0x05,0x00,0x2e,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x2e,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_mul_hi_i32 v5, m0, 0.5                ; encoding: [0x05,0x00,0x2e,0xd7,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x2e,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_mul_hi_i32 v5, exec_lo, -1            ; encoding: [0x05,0x00,0x2e,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x2e,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_mul_hi_i32 v5, exec_hi, null          ; encoding: [0x05,0x00,0x2e,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x2e,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_mul_hi_i32 v5, null, exec_lo          ; encoding: [0x05,0x00,0x2e,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x2e,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_mul_hi_i32 v5, -1, exec_hi            ; encoding: [0x05,0x00,0x2e,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x2e,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_mul_hi_i32 v5, 0.5, m0                ; encoding: [0x05,0x00,0x2e,0xd7,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x2e,0xd7,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_mul_hi_i32 v5, src_scc, vcc_lo        ; encoding: [0x05,0x00,0x2e,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x2e,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_mul_hi_i32 v255, 0xaf123456, vcc_hi   ; encoding: [0xff,0x00,0x2e,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x2e,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mul_hi_u32 v5, v1, v2                 ; encoding: [0x05,0x00,0x2d,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x2d,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_mul_hi_u32 v5, v255, v255             ; encoding: [0x05,0x00,0x2d,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x2d,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_mul_hi_u32 v5, s1, s2                 ; encoding: [0x05,0x00,0x2d,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x2d,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_mul_hi_u32 v5, s105, s105             ; encoding: [0x05,0x00,0x2d,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x2d,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_mul_hi_u32 v5, vcc_lo, ttmp15         ; encoding: [0x05,0x00,0x2d,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x2d,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_mul_hi_u32 v5, vcc_hi, 0xaf123456     ; encoding: [0x05,0x00,0x2d,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x2d,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mul_hi_u32 v5, ttmp15, src_scc        ; encoding: [0x05,0x00,0x2d,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x2d,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_mul_hi_u32 v5, m0, 0.5                ; encoding: [0x05,0x00,0x2d,0xd7,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x2d,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_mul_hi_u32 v5, exec_lo, -1            ; encoding: [0x05,0x00,0x2d,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x2d,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_mul_hi_u32 v5, exec_hi, null          ; encoding: [0x05,0x00,0x2d,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x2d,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_mul_hi_u32 v5, null, exec_lo          ; encoding: [0x05,0x00,0x2d,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x2d,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_mul_hi_u32 v5, -1, exec_hi            ; encoding: [0x05,0x00,0x2d,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x2d,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_mul_hi_u32 v5, 0.5, m0                ; encoding: [0x05,0x00,0x2d,0xd7,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x2d,0xd7,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_mul_hi_u32 v5, src_scc, vcc_lo        ; encoding: [0x05,0x00,0x2d,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x2d,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_mul_hi_u32 v255, 0xaf123456, vcc_hi   ; encoding: [0xff,0x00,0x2d,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x2d,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mul_lo_u16 v5, v1, v2                 ; encoding: [0x05,0x00,0x05,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x05,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_mul_lo_u16 v5, v255, v255             ; encoding: [0x05,0x00,0x05,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x05,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_mul_lo_u16 v5, s1, s2                 ; encoding: [0x05,0x00,0x05,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x05,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_mul_lo_u16 v5, s105, s105             ; encoding: [0x05,0x00,0x05,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x05,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_mul_lo_u16 v5, vcc_lo, ttmp15         ; encoding: [0x05,0x00,0x05,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x05,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_mul_lo_u16 v5, vcc_hi, 0xfe0b         ; encoding: [0x05,0x00,0x05,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x05,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_mul_lo_u16 v5, ttmp15, src_scc        ; encoding: [0x05,0x00,0x05,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x05,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_mul_lo_u16 v5, m0, 0x3800
+0x05,0x00,0x05,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_mul_lo_u16 v5, exec_lo, -1            ; encoding: [0x05,0x00,0x05,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x05,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_mul_lo_u16 v5, exec_hi, null          ; encoding: [0x05,0x00,0x05,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x05,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_mul_lo_u16 v5, null, exec_lo          ; encoding: [0x05,0x00,0x05,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x05,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_mul_lo_u16 v5, -1, exec_hi            ; encoding: [0x05,0x00,0x05,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x05,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_mul_lo_u16 v5, 0x3800, m0
+0x05,0x00,0x05,0xd7,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_mul_lo_u16 v5, src_scc, vcc_lo        ; encoding: [0x05,0x00,0x05,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x05,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_mul_lo_u16 v255, 0xfe0b, vcc_hi       ; encoding: [0xff,0x00,0x05,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0xff,0x00,0x05,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_mul_lo_u32 v5, v1, v2                 ; encoding: [0x05,0x00,0x2c,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x2c,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_mul_lo_u32 v5, v255, v255             ; encoding: [0x05,0x00,0x2c,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x2c,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_mul_lo_u32 v5, s1, s2                 ; encoding: [0x05,0x00,0x2c,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x2c,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_mul_lo_u32 v5, s105, s105             ; encoding: [0x05,0x00,0x2c,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x2c,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_mul_lo_u32 v5, vcc_lo, ttmp15         ; encoding: [0x05,0x00,0x2c,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x2c,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_mul_lo_u32 v5, vcc_hi, 0xaf123456     ; encoding: [0x05,0x00,0x2c,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x2c,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mul_lo_u32 v5, ttmp15, src_scc        ; encoding: [0x05,0x00,0x2c,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x2c,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_mul_lo_u32 v5, m0, 0.5                ; encoding: [0x05,0x00,0x2c,0xd7,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x2c,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_mul_lo_u32 v5, exec_lo, -1            ; encoding: [0x05,0x00,0x2c,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x2c,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_mul_lo_u32 v5, exec_hi, null          ; encoding: [0x05,0x00,0x2c,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x2c,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_mul_lo_u32 v5, null, exec_lo          ; encoding: [0x05,0x00,0x2c,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x2c,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_mul_lo_u32 v5, -1, exec_hi            ; encoding: [0x05,0x00,0x2c,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x2c,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_mul_lo_u32 v5, 0.5, m0                ; encoding: [0x05,0x00,0x2c,0xd7,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x2c,0xd7,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_mul_lo_u32 v5, src_scc, vcc_lo        ; encoding: [0x05,0x00,0x2c,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x2c,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_mul_lo_u32 v255, 0xaf123456, vcc_hi   ; encoding: [0xff,0x00,0x2c,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x2c,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mullit_f32 v5, v1, v2, s3             ; encoding: [0x05,0x00,0x18,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x18,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_mullit_f32 v5, v255, s2, s105         ; encoding: [0x05,0x00,0x18,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x18,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_mullit_f32 v5, s1, v255, exec_hi      ; encoding: [0x05,0x00,0x18,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x18,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_mullit_f32 v5, s105, s105, exec_lo    ; encoding: [0x05,0x00,0x18,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x18,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_mullit_f32 v5, vcc_lo, ttmp15, v3     ; encoding: [0x05,0x00,0x18,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x18,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_mullit_f32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x18,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x18,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mullit_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x18,0xd6,0x7b,0xfa,0xed,0xe1]
+0x05,0x07,0x18,0xd6,0x7b,0xfa,0xed,0xe1
+
+# GFX12: v_mullit_f32 v5, m0, 0.5, m0            ; encoding: [0x05,0x00,0x18,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x18,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_mullit_f32 v5, |exec_lo|, -1, vcc_hi  ; encoding: [0x05,0x01,0x18,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x01,0x18,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_mullit_f32 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x18,0xd6,0x7f,0xf8,0xa8,0xa1]
+0x05,0x05,0x18,0xd6,0x7f,0xf8,0xa8,0xa1
+
+# GFX12: v_mullit_f32 v5, null, exec_lo, -|0xaf123456| ; encoding: [0x05,0x04,0x18,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf]
+0x05,0x04,0x18,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mullit_f32 v5, -1, -|exec_hi|, -|src_scc| ; encoding: [0x05,0x06,0x18,0xd6,0xc1,0xfe,0xf4,0xc3]
+0x05,0x06,0x18,0xd6,0xc1,0xfe,0xf4,0xc3
+
+# GFX12: v_mullit_f32 v5, 0.5, -m0, 0.5 mul:2    ; encoding: [0x05,0x00,0x18,0xd6,0xf0,0xfa,0xc0,0x4b]
+0x05,0x00,0x18,0xd6,0xf0,0xfa,0xc0,0x4b
+
+# GFX12: v_mullit_f32 v5, -src_scc, |vcc_lo|, -1 mul:4 ; encoding: [0x05,0x02,0x18,0xd6,0xfd,0xd4,0x04,0x33]
+0x05,0x02,0x18,0xd6,0xfd,0xd4,0x04,0x33
+
+# GFX12: v_mullit_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2 ; encoding: [0xff,0x83,0x18,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
+0xff,0x83,0x18,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf
+
+# GFX12: v_nop                                   ; encoding: [0x00,0x00,0x80,0xd5,0x00,0x00,0x00,0x00]
+0x00,0x00,0x80,0xd5,0x00,0x00,0x00,0x00
+
+# GFX12: v_or3_b32 v5, v1, v2, s3                ; encoding: [0x05,0x00,0x58,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x58,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_or3_b32 v5, v255, s2, s105            ; encoding: [0x05,0x00,0x58,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x58,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_or3_b32 v5, s1, v255, exec_hi         ; encoding: [0x05,0x00,0x58,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x58,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_or3_b32 v5, s105, s105, exec_lo       ; encoding: [0x05,0x00,0x58,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x58,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_or3_b32 v5, vcc_lo, ttmp15, v3        ; encoding: [0x05,0x00,0x58,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x58,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_or3_b32 v5, vcc_hi, 0xaf123456, v255  ; encoding: [0x05,0x00,0x58,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x58,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_or3_b32 v5, ttmp15, src_scc, ttmp15   ; encoding: [0x05,0x00,0x58,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x58,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_or3_b32 v5, m0, 0.5, m0               ; encoding: [0x05,0x00,0x58,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x58,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_or3_b32 v5, exec_lo, -1, vcc_hi       ; encoding: [0x05,0x00,0x58,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x58,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_or3_b32 v5, exec_hi, null, vcc_lo     ; encoding: [0x05,0x00,0x58,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x58,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_or3_b32 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x58,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x58,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_or3_b32 v5, -1, exec_hi, src_scc      ; encoding: [0x05,0x00,0x58,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x58,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_or3_b32 v5, 0.5, m0, 0.5              ; encoding: [0x05,0x00,0x58,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x58,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_or3_b32 v5, src_scc, vcc_lo, -1       ; encoding: [0x05,0x00,0x58,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x58,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_or3_b32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x58,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x58,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_or_b16 v5, v1, v2                     ; encoding: [0x05,0x00,0x63,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x63,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_or_b16 v5, v255, v255                 ; encoding: [0x05,0x00,0x63,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x63,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_or_b16 v5, s1, s2                     ; encoding: [0x05,0x00,0x63,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x63,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_or_b16 v5, s105, s105                 ; encoding: [0x05,0x00,0x63,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x63,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_or_b16 v5, vcc_lo, ttmp15             ; encoding: [0x05,0x00,0x63,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x63,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_or_b16 v5, vcc_hi, 0xfe0b             ; encoding: [0x05,0x00,0x63,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x63,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_or_b16 v5, ttmp15, src_scc            ; encoding: [0x05,0x00,0x63,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x63,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_or_b16 v5, m0, 0x3800
+0x05,0x00,0x63,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_or_b16 v5, exec_lo, -1                ; encoding: [0x05,0x00,0x63,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x63,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_or_b16 v5, exec_hi, null              ; encoding: [0x05,0x00,0x63,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x63,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_or_b16 v5, null, exec_lo              ; encoding: [0x05,0x00,0x63,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x63,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_or_b16 v5, -1, exec_hi                ; encoding: [0x05,0x00,0x63,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x63,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_or_b16 v5, 0x3800, m0
+0x05,0x00,0x63,0xd7,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_or_b16 v5, src_scc, vcc_lo            ; encoding: [0x05,0x00,0x63,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x63,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_or_b16 v255, 0xfe0b, vcc_hi           ; encoding: [0xff,0x00,0x63,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0xff,0x00,0x63,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pack_b32_f16 v5, v1, v2               ; encoding: [0x05,0x00,0x11,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x11,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_pack_b32_f16 v5, v255, v255           ; encoding: [0x05,0x00,0x11,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x11,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_pack_b32_f16 v5, s1, s2               ; encoding: [0x05,0x00,0x11,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x11,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_pack_b32_f16 v5, s105, s105           ; encoding: [0x05,0x00,0x11,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x11,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_pack_b32_f16 v5, vcc_lo, ttmp15       ; encoding: [0x05,0x00,0x11,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x11,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_pack_b32_f16 v5, vcc_hi, 0xfe0b       ; encoding: [0x05,0x00,0x11,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x11,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pack_b32_f16 v5, ttmp15, src_scc      ; encoding: [0x05,0x00,0x11,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x11,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_pack_b32_f16 v5, m0, 0.5              ; encoding: [0x05,0x00,0x11,0xd7,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x11,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_pack_b32_f16 v5, exec_lo, -1          ; encoding: [0x05,0x00,0x11,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x11,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_pack_b32_f16 v5, |exec_hi|, null      ; encoding: [0x05,0x01,0x11,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x01,0x11,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_pack_b32_f16 v5, null, exec_lo        ; encoding: [0x05,0x00,0x11,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x11,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_pack_b32_f16 v5, -1, exec_hi          ; encoding: [0x05,0x00,0x11,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x11,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_pack_b32_f16 v5, 0.5, -m0             ; encoding: [0x05,0x00,0x11,0xd7,0xf0,0xfa,0x00,0x40]
+0x05,0x00,0x11,0xd7,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_pack_b32_f16 v5, -src_scc, |vcc_lo| op_sel:[1,0,0] ; encoding: [0x05,0x0a,0x11,0xd7,0xfd,0xd4,0x00,0x20]
+0x05,0x0a,0x11,0xd7,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_pack_b32_f16 v255, -|0xfe0b|, -|vcc_hi| op_sel:[0,1,0] ; encoding: [0xff,0x13,0x11,0xd7,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0xff,0x13,0x11,0xd7,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_perm_b32 v5, v1, v2, s3               ; encoding: [0x05,0x00,0x44,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x44,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_perm_b32 v5, v255, s2, s105           ; encoding: [0x05,0x00,0x44,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x44,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_perm_b32 v5, s1, v255, exec_hi        ; encoding: [0x05,0x00,0x44,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x44,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_perm_b32 v5, s105, s105, exec_lo      ; encoding: [0x05,0x00,0x44,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x44,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_perm_b32 v5, vcc_lo, ttmp15, v3       ; encoding: [0x05,0x00,0x44,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x44,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_perm_b32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x44,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x44,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_perm_b32 v5, ttmp15, src_scc, ttmp15  ; encoding: [0x05,0x00,0x44,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x44,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_perm_b32 v5, m0, 0.5, m0              ; encoding: [0x05,0x00,0x44,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x44,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_perm_b32 v5, exec_lo, -1, vcc_hi      ; encoding: [0x05,0x00,0x44,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x44,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_perm_b32 v5, exec_hi, null, vcc_lo    ; encoding: [0x05,0x00,0x44,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x44,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_perm_b32 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x44,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x44,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_perm_b32 v5, -1, exec_hi, src_scc     ; encoding: [0x05,0x00,0x44,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x44,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_perm_b32 v5, 0.5, m0, 0.5             ; encoding: [0x05,0x00,0x44,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x44,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_perm_b32 v5, src_scc, vcc_lo, -1      ; encoding: [0x05,0x00,0x44,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x44,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_perm_b32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x44,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x44,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_permlane16_b32 v5, v1, s2, s3         ; encoding: [0x05,0x00,0x5b,0xd6,0x01,0x05,0x0c,0x00]
+0x05,0x00,0x5b,0xd6,0x01,0x05,0x0c,0x00
+
+# GFX12: v_permlane16_b32 v5, v1, s105, s105     ; encoding: [0x05,0x00,0x5b,0xd6,0x01,0xd3,0xa4,0x01]
+0x05,0x00,0x5b,0xd6,0x01,0xd3,0xa4,0x01
+
+# GFX12: v_permlane16_b32 v5, v1, ttmp15, ttmp15 ; encoding: [0x05,0x00,0x5b,0xd6,0x01,0xf7,0xec,0x01]
+0x05,0x00,0x5b,0xd6,0x01,0xf7,0xec,0x01
+
+# GFX12: v_permlane16_b32 v5, v1, vcc_hi, exec_hi ; encoding: [0x05,0x00,0x5b,0xd6,0x01,0xd7,0xfc,0x01]
+0x05,0x00,0x5b,0xd6,0x01,0xd7,0xfc,0x01
+
+# GFX12: v_permlane16_b32 v5, v1, vcc_lo, exec_lo ; encoding: [0x05,0x00,0x5b,0xd6,0x01,0xd5,0xf8,0x01]
+0x05,0x00,0x5b,0xd6,0x01,0xd5,0xf8,0x01
+
+# GFX12: v_permlane16_b32 v5, v1, m0, m0         ; encoding: [0x05,0x00,0x5b,0xd6,0x01,0xfb,0xf4,0x01]
+0x05,0x00,0x5b,0xd6,0x01,0xfb,0xf4,0x01
+
+# GFX12: v_permlane16_b32 v5, v1, exec_hi, vcc_hi ; encoding: [0x05,0x00,0x5b,0xd6,0x01,0xff,0xac,0x01]
+0x05,0x00,0x5b,0xd6,0x01,0xff,0xac,0x01
+
+# GFX12: v_permlane16_b32 v5, v1, exec_lo, vcc_lo ; encoding: [0x05,0x00,0x5b,0xd6,0x01,0xfd,0xa8,0x01]
+0x05,0x00,0x5b,0xd6,0x01,0xfd,0xa8,0x01
+
+# GFX12: v_permlane16_b32 v5, v1, null, 0xaf123456 ; encoding: [0x05,0x00,0x5b,0xd6,0x01,0xf9,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x5b,0xd6,0x01,0xf9,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_permlane16_b32 v5, v1, -1, src_scc    ; encoding: [0x05,0x00,0x5b,0xd6,0x01,0x83,0xf5,0x03]
+0x05,0x00,0x5b,0xd6,0x01,0x83,0xf5,0x03
+
+# GFX12: v_permlane16_b32 v5, v1, 0.5, 0.5       ; encoding: [0x05,0x00,0x5b,0xd6,0x01,0xe1,0xc1,0x03]
+0x05,0x00,0x5b,0xd6,0x01,0xe1,0xc1,0x03
+
+# GFX12: v_permlane16_b32 v5, v1, src_scc, -1    ; encoding: [0x05,0x00,0x5b,0xd6,0x01,0xfb,0x05,0x03]
+0x05,0x00,0x5b,0xd6,0x01,0xfb,0x05,0x03
+
+# GFX12: v_permlane16_b32 v255, v255, 0xaf123456, null ; encoding: [0xff,0x00,0x5b,0xd6,0xff,0xff,0xf1,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x5b,0xd6,0xff,0xff,0xf1,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_permlanex16_b32 v5, v1, s2, s3        ; encoding: [0x05,0x00,0x5c,0xd6,0x01,0x05,0x0c,0x00]
+0x05,0x00,0x5c,0xd6,0x01,0x05,0x0c,0x00
+
+# GFX12: v_permlane16_b32 v5, v1, s2, s3 op_sel:[1,1] ; encoding: [0x05,0x18,0x5b,0xd6,0x01,0x05,0x0c,0x00]
+0x05,0x18,0x5b,0xd6,0x01,0x05,0x0c,0x00
+
+# GFX12: v_permlane16_b32 v5, v1, s2, s3 op_sel:[1,0] ; encoding: [0x05,0x08,0x5b,0xd6,0x01,0x05,0x0c,0x00]
+0x05,0x08,0x5b,0xd6,0x01,0x05,0x0c,0x00
+
+# GFX12: v_permlane16_b32 v5, v1, s2, s3 op_sel:[0,1] ; encoding: [0x05,0x10,0x5b,0xd6,0x01,0x05,0x0c,0x00]
+0x05,0x10,0x5b,0xd6,0x01,0x05,0x0c,0x00
+
+# GFX12: v_permlanex16_b32 v5, v1, s105, s105    ; encoding: [0x05,0x00,0x5c,0xd6,0x01,0xd3,0xa4,0x01]
+0x05,0x00,0x5c,0xd6,0x01,0xd3,0xa4,0x01
+
+# GFX12: v_permlanex16_b32 v5, v1, ttmp15, ttmp15 ; encoding: [0x05,0x00,0x5c,0xd6,0x01,0xf7,0xec,0x01]
+0x05,0x00,0x5c,0xd6,0x01,0xf7,0xec,0x01
+
+# GFX12: v_permlanex16_b32 v5, v1, vcc_hi, exec_hi ; encoding: [0x05,0x00,0x5c,0xd6,0x01,0xd7,0xfc,0x01]
+0x05,0x00,0x5c,0xd6,0x01,0xd7,0xfc,0x01
+
+# GFX12: v_permlanex16_b32 v5, v1, vcc_lo, exec_lo ; encoding: [0x05,0x00,0x5c,0xd6,0x01,0xd5,0xf8,0x01]
+0x05,0x00,0x5c,0xd6,0x01,0xd5,0xf8,0x01
+
+# GFX12: v_permlanex16_b32 v5, v1, m0, m0        ; encoding: [0x05,0x00,0x5c,0xd6,0x01,0xfb,0xf4,0x01]
+0x05,0x00,0x5c,0xd6,0x01,0xfb,0xf4,0x01
+
+# GFX12: v_permlanex16_b32 v5, v1, exec_hi, vcc_hi ; encoding: [0x05,0x00,0x5c,0xd6,0x01,0xff,0xac,0x01]
+0x05,0x00,0x5c,0xd6,0x01,0xff,0xac,0x01
+
+# GFX12: v_permlanex16_b32 v5, v1, exec_lo, vcc_lo ; encoding: [0x05,0x00,0x5c,0xd6,0x01,0xfd,0xa8,0x01]
+0x05,0x00,0x5c,0xd6,0x01,0xfd,0xa8,0x01
+
+# GFX12: v_permlanex16_b32 v5, v1, null, 0xaf123456 ; encoding: [0x05,0x00,0x5c,0xd6,0x01,0xf9,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x5c,0xd6,0x01,0xf9,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_permlanex16_b32 v5, v1, -1, src_scc   ; encoding: [0x05,0x00,0x5c,0xd6,0x01,0x83,0xf5,0x03]
+0x05,0x00,0x5c,0xd6,0x01,0x83,0xf5,0x03
+
+# GFX12: v_permlanex16_b32 v5, v1, 0.5, 0.5      ; encoding: [0x05,0x00,0x5c,0xd6,0x01,0xe1,0xc1,0x03]
+0x05,0x00,0x5c,0xd6,0x01,0xe1,0xc1,0x03
+
+# GFX12: v_permlanex16_b32 v5, v1, src_scc, -1   ; encoding: [0x05,0x00,0x5c,0xd6,0x01,0xfb,0x05,0x03]
+0x05,0x00,0x5c,0xd6,0x01,0xfb,0x05,0x03
+
+# GFX12: v_permlanex16_b32 v255, v255, 0xaf123456, null ; encoding: [0xff,0x00,0x5c,0xd6,0xff,0xff,0xf1,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x5c,0xd6,0xff,0xff,0xf1,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_permlanex16_b32 v5, v1, s2, s3 op_sel:[1,1] ; encoding: [0x05,0x18,0x5c,0xd6,0x01,0x05,0x0c,0x00]
+0x05,0x18,0x5c,0xd6,0x01,0x05,0x0c,0x00
+
+# GFX12: v_permlanex16_b32 v5, v1, s2, s3 op_sel:[1,0] ; encoding: [0x05,0x08,0x5c,0xd6,0x01,0x05,0x0c,0x00]
+0x05,0x08,0x5c,0xd6,0x01,0x05,0x0c,0x00
+
+# GFX12: v_permlanex16_b32 v5, v1, s2, s3 op_sel:[0,1] ; encoding: [0x05,0x10,0x5c,0xd6,0x01,0x05,0x0c,0x00]
+0x05,0x10,0x5c,0xd6,0x01,0x05,0x0c,0x00
+
+# GFX12: v_pipeflush                             ; encoding: [0x00,0x00,0x9b,0xd5,0x00,0x00,0x00,0x00]
+0x00,0x00,0x9b,0xd5,0x00,0x00,0x00,0x00
+
+# GFX12: v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, ttmp[14:15] ; encoding: [0x05,0x00,0x3a,0xd6,0x01,0x05,0xea,0x01]
+0x05,0x00,0x3a,0xd6,0x01,0x05,0xea,0x01
+
+# GFX12: v_qsad_pk_u16_u8 v[5:6], v[1:2], v255, ttmp[14:15] ; encoding: [0x05,0x00,0x3a,0xd6,0x01,0xff,0xeb,0x01]
+0x05,0x00,0x3a,0xd6,0x01,0xff,0xeb,0x01
+
+# GFX12: v_qsad_pk_u16_u8 v[5:6], v[1:2], s2, ttmp[14:15] ; encoding: [0x05,0x00,0x3a,0xd6,0x01,0x05,0xe8,0x01]
+0x05,0x00,0x3a,0xd6,0x01,0x05,0xe8,0x01
+
+# GFX12: v_qsad_pk_u16_u8 v[5:6], v[1:2], s105, ttmp[14:15] ; encoding: [0x05,0x00,0x3a,0xd6,0x01,0xd3,0xe8,0x01]
+0x05,0x00,0x3a,0xd6,0x01,0xd3,0xe8,0x01
+
+# GFX12: v_qsad_pk_u16_u8 v[5:6], v[254:255], ttmp15, s[6:7] ; encoding: [0x05,0x00,0x3a,0xd6,0xfe,0xf7,0x18,0x00]
+0x05,0x00,0x3a,0xd6,0xfe,0xf7,0x18,0x00
+
+# GFX12: v_qsad_pk_u16_u8 v[5:6], s[2:3], vcc_hi, v[3:4] ; encoding: [0x05,0x00,0x3a,0xd6,0x02,0xd6,0x0c,0x04]
+0x05,0x00,0x3a,0xd6,0x02,0xd6,0x0c,0x04
+
+# GFX12: v_qsad_pk_u16_u8 v[5:6], s[104:105], vcc_lo, s[104:105] ; encoding: [0x05,0x00,0x3a,0xd6,0x68,0xd4,0xa0,0x01]
+0x05,0x00,0x3a,0xd6,0x68,0xd4,0xa0,0x01
+
+# GFX12: v_qsad_pk_u16_u8 v[5:6], vcc, m0, v[254:255] ; encoding: [0x05,0x00,0x3a,0xd6,0x6a,0xfa,0xf8,0x07]
+0x05,0x00,0x3a,0xd6,0x6a,0xfa,0xf8,0x07
+
+# GFX12: v_qsad_pk_u16_u8 v[5:6], ttmp[14:15], exec_hi, null ; encoding: [0x05,0x00,0x3a,0xd6,0x7a,0xfe,0xf0,0x01]
+0x05,0x00,0x3a,0xd6,0x7a,0xfe,0xf0,0x01
+
+# GFX12: v_qsad_pk_u16_u8 v[5:6], exec, exec_lo, exec ; encoding: [0x05,0x00,0x3a,0xd6,0x7e,0xfc,0xf8,0x01]
+0x05,0x00,0x3a,0xd6,0x7e,0xfc,0xf8,0x01
+
+# GFX12: v_qsad_pk_u16_u8 v[5:6], null, null, vcc ; encoding: [0x05,0x00,0x3a,0xd6,0x7c,0xf8,0xa8,0x01]
+0x05,0x00,0x3a,0xd6,0x7c,0xf8,0xa8,0x01
+
+# GFX12: v_qsad_pk_u16_u8 v[5:6], -1, -1, 0xaf123456 ; encoding: [0x05,0x00,0x3a,0xd6,0xc1,0x82,0xfd,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x3a,0xd6,0xc1,0x82,0xfd,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_qsad_pk_u16_u8 v[5:6], 0.5, 0.5, src_scc ; encoding: [0x05,0x00,0x3a,0xd6,0xf0,0xe0,0xf5,0x03]
+0x05,0x00,0x3a,0xd6,0xf0,0xe0,0xf5,0x03
+
+# GFX12: v_qsad_pk_u16_u8 v[5:6], src_scc, src_scc, 0.5 ; encoding: [0x05,0x00,0x3a,0xd6,0xfd,0xfa,0xc1,0x03]
+0x05,0x00,0x3a,0xd6,0xfd,0xfa,0xc1,0x03
+
+# GFX12: v_qsad_pk_u16_u8 v[254:255], 0xaf123456, 0xaf123456, -1 clamp ; encoding: [0xfe,0x80,0x3a,0xd6,0xff,0xfe,0x05,0x03,0x56,0x34,0x12,0xaf]
+0xfe,0x80,0x3a,0xd6,0xff,0xfe,0x05,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_readlane_b32 s5, v1, s2               ; encoding: [0x05,0x00,0x60,0xd7,0x01,0x05,0x00,0x00]
+0x05,0x00,0x60,0xd7,0x01,0x05,0x00,0x00
+
+# GFX12: v_readlane_b32 s5, v1, s105             ; encoding: [0x05,0x00,0x60,0xd7,0x01,0xd3,0x00,0x00]
+0x05,0x00,0x60,0xd7,0x01,0xd3,0x00,0x00
+
+# GFX12: v_readlane_b32 s105, v1, ttmp15         ; encoding: [0x69,0x00,0x60,0xd7,0x01,0xf7,0x00,0x00]
+0x69,0x00,0x60,0xd7,0x01,0xf7,0x00,0x00
+
+# GFX12: v_readlane_b32 vcc_lo, v1, vcc_hi       ; encoding: [0x6a,0x00,0x60,0xd7,0x01,0xd7,0x00,0x00]
+0x6a,0x00,0x60,0xd7,0x01,0xd7,0x00,0x00
+
+# GFX12: v_readlane_b32 vcc_hi, v1, vcc_lo       ; encoding: [0x6b,0x00,0x60,0xd7,0x01,0xd5,0x00,0x00]
+0x6b,0x00,0x60,0xd7,0x01,0xd5,0x00,0x00
+
+# GFX12: v_readlane_b32 ttmp15, v1, m0           ; encoding: [0x7b,0x00,0x60,0xd7,0x01,0xfb,0x00,0x00]
+0x7b,0x00,0x60,0xd7,0x01,0xfb,0x00,0x00
+
+# GFX12: v_readlane_b32 null, v255, null         ; encoding: [0x7c,0x00,0x60,0xd7,0xff,0xf9,0x00,0x00]
+0x7c,0x00,0x60,0xd7,0xff,0xf9,0x00,0x00
+
+# GFX12: v_sad_hi_u8 v5, v1, v2, s3              ; encoding: [0x05,0x00,0x23,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x23,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_sad_hi_u8 v5, v255, s2, s105          ; encoding: [0x05,0x00,0x23,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x23,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_sad_hi_u8 v5, s1, v255, exec_hi       ; encoding: [0x05,0x00,0x23,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x23,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_sad_hi_u8 v5, s105, s105, exec_lo     ; encoding: [0x05,0x00,0x23,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x23,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_sad_hi_u8 v5, vcc_lo, ttmp15, v3      ; encoding: [0x05,0x00,0x23,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x23,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_sad_hi_u8 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x23,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x23,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_sad_hi_u8 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x00,0x23,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x23,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_sad_hi_u8 v5, m0, 0.5, m0             ; encoding: [0x05,0x00,0x23,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x23,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_sad_hi_u8 v5, exec_lo, -1, vcc_hi     ; encoding: [0x05,0x00,0x23,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x23,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_sad_hi_u8 v5, exec_hi, null, vcc_lo   ; encoding: [0x05,0x00,0x23,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x23,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_sad_hi_u8 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x23,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x23,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_sad_hi_u8 v5, -1, exec_hi, src_scc    ; encoding: [0x05,0x00,0x23,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x23,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_sad_hi_u8 v5, 0.5, m0, 0.5            ; encoding: [0x05,0x00,0x23,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x23,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_sad_hi_u8 v5, src_scc, vcc_lo, -1     ; encoding: [0x05,0x00,0x23,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x23,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_sad_hi_u8 v255, 0xaf123456, vcc_hi, null clamp ; encoding: [0xff,0x80,0x23,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x80,0x23,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_sad_u16 v5, v1, v2, s3                ; encoding: [0x05,0x00,0x24,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x24,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_sad_u16 v5, v255, s2, s105            ; encoding: [0x05,0x00,0x24,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x24,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_sad_u16 v5, s1, v255, exec_hi         ; encoding: [0x05,0x00,0x24,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x24,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_sad_u16 v5, s105, s105, exec_lo       ; encoding: [0x05,0x00,0x24,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x24,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_sad_u16 v5, vcc_lo, ttmp15, v3        ; encoding: [0x05,0x00,0x24,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x24,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_sad_u16 v5, vcc_hi, 0xfe0b, v255      ; encoding: [0x05,0x00,0x24,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x24,0xd6,0x6b,0xfe,0xfd,0x07,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_sad_u16 v5, ttmp15, src_scc, ttmp15   ; encoding: [0x05,0x00,0x24,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x24,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_sad_u16 v5, m0, 0.5, m0               ; encoding: [0x05,0x00,0x24,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x24,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_sad_u16 v5, exec_lo, -1, vcc_hi       ; encoding: [0x05,0x00,0x24,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x24,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_sad_u16 v5, exec_hi, null, vcc_lo     ; encoding: [0x05,0x00,0x24,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x24,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_sad_u16 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x24,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x24,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_sad_u16 v5, -1, exec_hi, src_scc      ; encoding: [0x05,0x00,0x24,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x24,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_sad_u16 v5, 0.5, m0, 0.5              ; encoding: [0x05,0x00,0x24,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x24,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_sad_u16 v5, src_scc, vcc_lo, -1       ; encoding: [0x05,0x00,0x24,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x24,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_sad_u16 v255, 0xfe0b, vcc_hi, null clamp ; encoding: [0xff,0x80,0x24,0xd6,0xff,0xd6,0xf0,0x01,0x0b,0xfe,0x00,0x00]
+0xff,0x80,0x24,0xd6,0xff,0xd6,0xf0,0x01,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_sad_u32 v5, v1, v2, s3                ; encoding: [0x05,0x00,0x25,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x25,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_sad_u32 v5, v255, s2, s105            ; encoding: [0x05,0x00,0x25,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x25,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_sad_u32 v5, s1, v255, exec_hi         ; encoding: [0x05,0x00,0x25,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x25,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_sad_u32 v5, s105, s105, exec_lo       ; encoding: [0x05,0x00,0x25,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x25,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_sad_u32 v5, vcc_lo, ttmp15, v3        ; encoding: [0x05,0x00,0x25,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x25,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_sad_u32 v5, vcc_hi, 0xaf123456, v255  ; encoding: [0x05,0x00,0x25,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x25,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_sad_u32 v5, ttmp15, src_scc, ttmp15   ; encoding: [0x05,0x00,0x25,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x25,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_sad_u32 v5, m0, 0.5, m0               ; encoding: [0x05,0x00,0x25,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x25,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_sad_u32 v5, exec_lo, -1, vcc_hi       ; encoding: [0x05,0x00,0x25,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x25,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_sad_u32 v5, exec_hi, null, vcc_lo     ; encoding: [0x05,0x00,0x25,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x25,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_sad_u32 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x25,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x25,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_sad_u32 v5, -1, exec_hi, src_scc      ; encoding: [0x05,0x00,0x25,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x25,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_sad_u32 v5, 0.5, m0, 0.5              ; encoding: [0x05,0x00,0x25,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x25,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_sad_u32 v5, src_scc, vcc_lo, -1       ; encoding: [0x05,0x00,0x25,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x25,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_sad_u32 v255, 0xaf123456, vcc_hi, null clamp ; encoding: [0xff,0x80,0x25,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x80,0x25,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_sad_u8 v5, v1, v2, s3                 ; encoding: [0x05,0x00,0x22,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x22,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_sad_u8 v5, v255, s2, s105             ; encoding: [0x05,0x00,0x22,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x22,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_sad_u8 v5, s1, v255, exec_hi          ; encoding: [0x05,0x00,0x22,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x22,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_sad_u8 v5, s105, s105, exec_lo        ; encoding: [0x05,0x00,0x22,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x22,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_sad_u8 v5, vcc_lo, ttmp15, v3         ; encoding: [0x05,0x00,0x22,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x22,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_sad_u8 v5, vcc_hi, 0xaf123456, v255   ; encoding: [0x05,0x00,0x22,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x22,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_sad_u8 v5, ttmp15, src_scc, ttmp15    ; encoding: [0x05,0x00,0x22,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x22,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_sad_u8 v5, m0, 0.5, m0                ; encoding: [0x05,0x00,0x22,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x22,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_sad_u8 v5, exec_lo, -1, vcc_hi        ; encoding: [0x05,0x00,0x22,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x22,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_sad_u8 v5, exec_hi, null, vcc_lo      ; encoding: [0x05,0x00,0x22,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x22,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_sad_u8 v5, null, exec_lo, 0xaf123456  ; encoding: [0x05,0x00,0x22,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x22,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_sad_u8 v5, -1, exec_hi, src_scc       ; encoding: [0x05,0x00,0x22,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x22,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_sad_u8 v5, 0.5, m0, 0.5               ; encoding: [0x05,0x00,0x22,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x22,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_sad_u8 v5, src_scc, vcc_lo, -1        ; encoding: [0x05,0x00,0x22,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x22,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_sad_u8 v255, 0xaf123456, vcc_hi, null clamp ; encoding: [0xff,0x80,0x22,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x80,0x22,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# W32: v_sub_co_u32 v5, s12, v1, v2              ; encoding: [0x05,0x0c,0x01,0xd7,0x01,0x05,0x02,0x00]
+# W64: v_sub_co_u32 v5, s[12:13], v1, v2         ; encoding: [0x05,0x0c,0x01,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x0c,0x01,0xd7,0x01,0x05,0x02,0x00
+
+# W32: v_sub_co_u32 v5, s12, v255, v255          ; encoding: [0x05,0x0c,0x01,0xd7,0xff,0xff,0x03,0x00]
+# W64: v_sub_co_u32 v5, s[12:13], v255, v255     ; encoding: [0x05,0x0c,0x01,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x0c,0x01,0xd7,0xff,0xff,0x03,0x00
+
+# W32: v_sub_co_u32 v5, s12, s1, s2              ; encoding: [0x05,0x0c,0x01,0xd7,0x01,0x04,0x00,0x00]
+# W64: v_sub_co_u32 v5, s[12:13], s1, s2         ; encoding: [0x05,0x0c,0x01,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x0c,0x01,0xd7,0x01,0x04,0x00,0x00
+
+# W32: v_sub_co_u32 v5, s12, s105, s105          ; encoding: [0x05,0x0c,0x01,0xd7,0x69,0xd2,0x00,0x00]
+# W64: v_sub_co_u32 v5, s[12:13], s105, s105     ; encoding: [0x05,0x0c,0x01,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x0c,0x01,0xd7,0x69,0xd2,0x00,0x00
+
+# W32: v_sub_co_u32 v5, s12, vcc_lo, ttmp15      ; encoding: [0x05,0x0c,0x01,0xd7,0x6a,0xf6,0x00,0x00]
+# W64: v_sub_co_u32 v5, s[12:13], vcc_lo, ttmp15 ; encoding: [0x05,0x0c,0x01,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x0c,0x01,0xd7,0x6a,0xf6,0x00,0x00
+
+# W32: v_sub_co_u32 v5, s12, vcc_hi, 0xaf123456  ; encoding: [0x05,0x0c,0x01,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_sub_co_u32 v5, s[12:13], vcc_hi, 0xaf123456 ; encoding: [0x05,0x0c,0x01,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x0c,0x01,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_sub_co_u32 v5, s12, ttmp15, src_scc     ; encoding: [0x05,0x0c,0x01,0xd7,0x7b,0xfa,0x01,0x00]
+# W64: v_sub_co_u32 v5, s[12:13], ttmp15, src_scc ; encoding: [0x05,0x0c,0x01,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x0c,0x01,0xd7,0x7b,0xfa,0x01,0x00
+
+# W32: v_sub_co_u32 v5, s12, m0, 0.5             ; encoding: [0x05,0x0c,0x01,0xd7,0x7d,0xe0,0x01,0x00]
+# W64: v_sub_co_u32 v5, s[12:13], m0, 0.5        ; encoding: [0x05,0x0c,0x01,0xd7,0x7d,0xe0,0x01,0x00]
+0x05,0x0c,0x01,0xd7,0x7d,0xe0,0x01,0x00
+
+# W32: v_sub_co_u32 v5, s12, exec_lo, -1         ; encoding: [0x05,0x0c,0x01,0xd7,0x7e,0x82,0x01,0x00]
+# W64: v_sub_co_u32 v5, s[12:13], exec_lo, -1    ; encoding: [0x05,0x0c,0x01,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x0c,0x01,0xd7,0x7e,0x82,0x01,0x00
+
+# W32: v_sub_co_u32 v5, s12, exec_hi, null       ; encoding: [0x05,0x0c,0x01,0xd7,0x7f,0xf8,0x00,0x00]
+# W64: v_sub_co_u32 v5, s[12:13], exec_hi, null  ; encoding: [0x05,0x0c,0x01,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x0c,0x01,0xd7,0x7f,0xf8,0x00,0x00
+
+# W32: v_sub_co_u32 v5, s12, null, exec_lo       ; encoding: [0x05,0x0c,0x01,0xd7,0x7c,0xfc,0x00,0x00]
+# W64: v_sub_co_u32 v5, s[12:13], null, exec_lo  ; encoding: [0x05,0x0c,0x01,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x0c,0x01,0xd7,0x7c,0xfc,0x00,0x00
+
+# W32: v_sub_co_u32 v5, s104, -1, exec_hi        ; encoding: [0x05,0x68,0x01,0xd7,0xc1,0xfe,0x00,0x00]
+# W64: v_sub_co_u32 v5, s[104:105], -1, exec_hi  ; encoding: [0x05,0x68,0x01,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x68,0x01,0xd7,0xc1,0xfe,0x00,0x00
+
+# W32: v_sub_co_u32 v5, vcc_lo, 0.5, m0          ; encoding: [0x05,0x6a,0x01,0xd7,0xf0,0xfa,0x00,0x00]
+# W64: v_sub_co_u32 v5, vcc, 0.5, m0             ; encoding: [0x05,0x6a,0x01,0xd7,0xf0,0xfa,0x00,0x00]
+0x05,0x6a,0x01,0xd7,0xf0,0xfa,0x00,0x00
+
+# W32: v_sub_co_u32 v5, ttmp14, src_scc, vcc_lo  ; encoding: [0x05,0x7a,0x01,0xd7,0xfd,0xd4,0x00,0x00]
+# W64: v_sub_co_u32 v5, ttmp[14:15], src_scc, vcc_lo ; encoding: [0x05,0x7a,0x01,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x7a,0x01,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_sub_co_u32 v255, null, 0xaf123456, vcc_hi clamp ; encoding: [0xff,0xfc,0x01,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x01,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_sub_nc_i16 v5, v1, v2                 ; encoding: [0x05,0x00,0x0e,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x0e,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_sub_nc_i16 v5, v255, v255             ; encoding: [0x05,0x00,0x0e,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x0e,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_sub_nc_i16 v5, s1, s2                 ; encoding: [0x05,0x00,0x0e,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x0e,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_sub_nc_i16 v5, s105, s105             ; encoding: [0x05,0x00,0x0e,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x0e,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_sub_nc_i16 v5, vcc_lo, ttmp15         ; encoding: [0x05,0x00,0x0e,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x0e,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_sub_nc_i16 v5, vcc_hi, 0xfe0b         ; encoding: [0x05,0x00,0x0e,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x0e,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_sub_nc_i16 v5, ttmp15, src_scc        ; encoding: [0x05,0x00,0x0e,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x0e,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_sub_nc_i16 v5, m0, 0x3800
+0x05,0x00,0x0e,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_sub_nc_i16 v5, exec_lo, -1            ; encoding: [0x05,0x00,0x0e,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x0e,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_sub_nc_i16 v5, exec_hi, null          ; encoding: [0x05,0x00,0x0e,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x0e,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_sub_nc_i16 v5, null, exec_lo          ; encoding: [0x05,0x00,0x0e,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x0e,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_sub_nc_i16 v5, -1, exec_hi op_sel:[1,1,1] ; encoding: [0x05,0x58,0x0e,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x58,0x0e,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_sub_nc_i16 v5, 0x3800, m0 op_sel:[1,0,0]
+0x05,0x08,0x0e,0xd7,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_sub_nc_i16 v5, src_scc, vcc_lo op_sel:[0,1,0] ; encoding: [0x05,0x10,0x0e,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x10,0x0e,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_sub_nc_i16 v255, 0xfe0b, vcc_hi op_sel:[0,0,1] clamp ; encoding: [0xff,0xc0,0x0e,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0xff,0xc0,0x0e,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_sub_nc_i32 v5, v1, v2                 ; encoding: [0x05,0x00,0x25,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x25,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_sub_nc_i32 v5, v255, v255             ; encoding: [0x05,0x00,0x25,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x25,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_sub_nc_i32 v5, s1, s2                 ; encoding: [0x05,0x00,0x25,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x25,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_sub_nc_i32 v5, s105, s105             ; encoding: [0x05,0x00,0x25,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x25,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_sub_nc_i32 v5, vcc_lo, ttmp15         ; encoding: [0x05,0x00,0x25,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x25,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_sub_nc_i32 v5, vcc_hi, 0xaf123456     ; encoding: [0x05,0x00,0x25,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x25,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_sub_nc_i32 v5, ttmp15, src_scc        ; encoding: [0x05,0x00,0x25,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x25,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_sub_nc_i32 v5, m0, 0.5                ; encoding: [0x05,0x00,0x25,0xd7,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x25,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_sub_nc_i32 v5, exec_lo, -1            ; encoding: [0x05,0x00,0x25,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x25,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_sub_nc_i32 v5, exec_hi, null          ; encoding: [0x05,0x00,0x25,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x25,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_sub_nc_i32 v5, null, exec_lo          ; encoding: [0x05,0x00,0x25,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x25,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_sub_nc_i32 v5, -1, exec_hi            ; encoding: [0x05,0x00,0x25,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x25,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_sub_nc_i32 v5, 0.5, m0                ; encoding: [0x05,0x00,0x25,0xd7,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x25,0xd7,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_sub_nc_i32 v5, src_scc, vcc_lo        ; encoding: [0x05,0x00,0x25,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x25,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_sub_nc_i32 v255, 0xaf123456, vcc_hi clamp ; encoding: [0xff,0x80,0x25,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x80,0x25,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_sub_nc_u16 v5, v1, v2                 ; encoding: [0x05,0x00,0x04,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x04,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_sub_nc_u16 v5, v255, v255             ; encoding: [0x05,0x00,0x04,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x04,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_sub_nc_u16 v5, s1, s2                 ; encoding: [0x05,0x00,0x04,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x04,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_sub_nc_u16 v5, s105, s105             ; encoding: [0x05,0x00,0x04,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x04,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_sub_nc_u16 v5, vcc_lo, ttmp15         ; encoding: [0x05,0x00,0x04,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x04,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_sub_nc_u16 v5, vcc_hi, 0xfe0b         ; encoding: [0x05,0x00,0x04,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x04,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_sub_nc_u16 v5, ttmp15, src_scc        ; encoding: [0x05,0x00,0x04,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x04,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_sub_nc_u16 v5, m0, 0x3800
+0x05,0x00,0x04,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_sub_nc_u16 v5, exec_lo, -1            ; encoding: [0x05,0x00,0x04,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x04,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_sub_nc_u16 v5, exec_hi, null          ; encoding: [0x05,0x00,0x04,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x04,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_sub_nc_u16 v5, null, exec_lo          ; encoding: [0x05,0x00,0x04,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x04,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_sub_nc_u16 v5, -1, exec_hi op_sel:[1,1,1] ; encoding: [0x05,0x58,0x04,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x58,0x04,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_sub_nc_u16 v5, 0x3800, m0 op_sel:[1,0,0]
+0x05,0x08,0x04,0xd7,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_sub_nc_u16 v5, src_scc, vcc_lo op_sel:[0,1,0] ; encoding: [0x05,0x10,0x04,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x10,0x04,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_sub_nc_u16 v255, 0xfe0b, vcc_hi op_sel:[0,0,1] clamp ; encoding: [0xff,0xc0,0x04,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0xff,0xc0,0x04,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_subrev_co_u32 v5, s12, v1, v2           ; encoding: [0x05,0x0c,0x02,0xd7,0x01,0x05,0x02,0x00]
+# W64: v_subrev_co_u32 v5, s[12:13], v1, v2      ; encoding: [0x05,0x0c,0x02,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x0c,0x02,0xd7,0x01,0x05,0x02,0x00
+
+# W32: v_subrev_co_u32 v5, s12, v255, v255       ; encoding: [0x05,0x0c,0x02,0xd7,0xff,0xff,0x03,0x00]
+# W64: v_subrev_co_u32 v5, s[12:13], v255, v255  ; encoding: [0x05,0x0c,0x02,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x0c,0x02,0xd7,0xff,0xff,0x03,0x00
+
+# W32: v_subrev_co_u32 v5, s12, s1, s2           ; encoding: [0x05,0x0c,0x02,0xd7,0x01,0x04,0x00,0x00]
+# W64: v_subrev_co_u32 v5, s[12:13], s1, s2      ; encoding: [0x05,0x0c,0x02,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x0c,0x02,0xd7,0x01,0x04,0x00,0x00
+
+# W32: v_subrev_co_u32 v5, s12, s105, s105       ; encoding: [0x05,0x0c,0x02,0xd7,0x69,0xd2,0x00,0x00]
+# W64: v_subrev_co_u32 v5, s[12:13], s105, s105  ; encoding: [0x05,0x0c,0x02,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x0c,0x02,0xd7,0x69,0xd2,0x00,0x00
+
+# W32: v_subrev_co_u32 v5, s12, vcc_lo, ttmp15   ; encoding: [0x05,0x0c,0x02,0xd7,0x6a,0xf6,0x00,0x00]
+# W64: v_subrev_co_u32 v5, s[12:13], vcc_lo, ttmp15 ; encoding: [0x05,0x0c,0x02,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x0c,0x02,0xd7,0x6a,0xf6,0x00,0x00
+
+# W32: v_subrev_co_u32 v5, s12, vcc_hi, 0xaf123456 ; encoding: [0x05,0x0c,0x02,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_subrev_co_u32 v5, s[12:13], vcc_hi, 0xaf123456 ; encoding: [0x05,0x0c,0x02,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x0c,0x02,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_subrev_co_u32 v5, s12, ttmp15, src_scc  ; encoding: [0x05,0x0c,0x02,0xd7,0x7b,0xfa,0x01,0x00]
+# W64: v_subrev_co_u32 v5, s[12:13], ttmp15, src_scc ; encoding: [0x05,0x0c,0x02,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x0c,0x02,0xd7,0x7b,0xfa,0x01,0x00
+
+# W32: v_subrev_co_u32 v5, s12, m0, 0.5          ; encoding: [0x05,0x0c,0x02,0xd7,0x7d,0xe0,0x01,0x00]
+# W64: v_subrev_co_u32 v5, s[12:13], m0, 0.5     ; encoding: [0x05,0x0c,0x02,0xd7,0x7d,0xe0,0x01,0x00]
+0x05,0x0c,0x02,0xd7,0x7d,0xe0,0x01,0x00
+
+# W32: v_subrev_co_u32 v5, s12, exec_lo, -1      ; encoding: [0x05,0x0c,0x02,0xd7,0x7e,0x82,0x01,0x00]
+# W64: v_subrev_co_u32 v5, s[12:13], exec_lo, -1 ; encoding: [0x05,0x0c,0x02,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x0c,0x02,0xd7,0x7e,0x82,0x01,0x00
+
+# W32: v_subrev_co_u32 v5, s12, exec_hi, null    ; encoding: [0x05,0x0c,0x02,0xd7,0x7f,0xf8,0x00,0x00]
+# W64: v_subrev_co_u32 v5, s[12:13], exec_hi, null ; encoding: [0x05,0x0c,0x02,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x0c,0x02,0xd7,0x7f,0xf8,0x00,0x00
+
+# W32: v_subrev_co_u32 v5, s12, null, exec_lo    ; encoding: [0x05,0x0c,0x02,0xd7,0x7c,0xfc,0x00,0x00]
+# W64: v_subrev_co_u32 v5, s[12:13], null, exec_lo ; encoding: [0x05,0x0c,0x02,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x0c,0x02,0xd7,0x7c,0xfc,0x00,0x00
+
+# W32: v_subrev_co_u32 v5, s104, -1, exec_hi     ; encoding: [0x05,0x68,0x02,0xd7,0xc1,0xfe,0x00,0x00]
+# W64: v_subrev_co_u32 v5, s[104:105], -1, exec_hi ; encoding: [0x05,0x68,0x02,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x68,0x02,0xd7,0xc1,0xfe,0x00,0x00
+
+# W32: v_subrev_co_u32 v5, vcc_lo, 0.5, m0       ; encoding: [0x05,0x6a,0x02,0xd7,0xf0,0xfa,0x00,0x00]
+# W64: v_subrev_co_u32 v5, vcc, 0.5, m0          ; encoding: [0x05,0x6a,0x02,0xd7,0xf0,0xfa,0x00,0x00]
+0x05,0x6a,0x02,0xd7,0xf0,0xfa,0x00,0x00
+
+# W32: v_subrev_co_u32 v5, ttmp14, src_scc, vcc_lo ; encoding: [0x05,0x7a,0x02,0xd7,0xfd,0xd4,0x00,0x00]
+# W64: v_subrev_co_u32 v5, ttmp[14:15], src_scc, vcc_lo ; encoding: [0x05,0x7a,0x02,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x7a,0x02,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_subrev_co_u32 v255, null, 0xaf123456, vcc_hi clamp ; encoding: [0xff,0xfc,0x02,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x02,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_trig_preop_f64 v[5:6], v[1:2], v2     ; encoding: [0x05,0x00,0x2f,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x2f,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_trig_preop_f64 v[5:6], v[1:2], v255   ; encoding: [0x05,0x00,0x2f,0xd7,0x01,0xff,0x03,0x00]
+0x05,0x00,0x2f,0xd7,0x01,0xff,0x03,0x00
+
+# GFX12: v_trig_preop_f64 v[5:6], v[1:2], s2     ; encoding: [0x05,0x00,0x2f,0xd7,0x01,0x05,0x00,0x00]
+0x05,0x00,0x2f,0xd7,0x01,0x05,0x00,0x00
+
+# GFX12: v_trig_preop_f64 v[5:6], v[1:2], s105   ; encoding: [0x05,0x00,0x2f,0xd7,0x01,0xd3,0x00,0x00]
+0x05,0x00,0x2f,0xd7,0x01,0xd3,0x00,0x00
+
+# GFX12: v_trig_preop_f64 v[5:6], v[254:255], ttmp15 ; encoding: [0x05,0x00,0x2f,0xd7,0xfe,0xf7,0x00,0x00]
+0x05,0x00,0x2f,0xd7,0xfe,0xf7,0x00,0x00
+
+# GFX12: v_trig_preop_f64 v[5:6], s[2:3], vcc_hi ; encoding: [0x05,0x00,0x2f,0xd7,0x02,0xd6,0x00,0x00]
+0x05,0x00,0x2f,0xd7,0x02,0xd6,0x00,0x00
+
+# GFX12: v_trig_preop_f64 v[5:6], s[104:105], vcc_lo ; encoding: [0x05,0x00,0x2f,0xd7,0x68,0xd4,0x00,0x00]
+0x05,0x00,0x2f,0xd7,0x68,0xd4,0x00,0x00
+
+# GFX12: v_trig_preop_f64 v[5:6], vcc, m0        ; encoding: [0x05,0x00,0x2f,0xd7,0x6a,0xfa,0x00,0x00]
+0x05,0x00,0x2f,0xd7,0x6a,0xfa,0x00,0x00
+
+# GFX12: v_trig_preop_f64 v[5:6], ttmp[14:15], exec_hi ; encoding: [0x05,0x00,0x2f,0xd7,0x7a,0xfe,0x00,0x00]
+0x05,0x00,0x2f,0xd7,0x7a,0xfe,0x00,0x00
+
+# GFX12: v_trig_preop_f64 v[5:6], exec, exec_lo  ; encoding: [0x05,0x00,0x2f,0xd7,0x7e,0xfc,0x00,0x00]
+0x05,0x00,0x2f,0xd7,0x7e,0xfc,0x00,0x00
+
+# GFX12: v_trig_preop_f64 v[5:6], null, null     ; encoding: [0x05,0x00,0x2f,0xd7,0x7c,0xf8,0x00,0x00]
+0x05,0x00,0x2f,0xd7,0x7c,0xf8,0x00,0x00
+
+# GFX12: v_trig_preop_f64 v[5:6], -1, -1         ; encoding: [0x05,0x00,0x2f,0xd7,0xc1,0x82,0x01,0x00]
+0x05,0x00,0x2f,0xd7,0xc1,0x82,0x01,0x00
+
+# GFX12: v_trig_preop_f64 v[5:6], 0.5, 0.5 mul:2 ; encoding: [0x05,0x00,0x2f,0xd7,0xf0,0xe0,0x01,0x08]
+0x05,0x00,0x2f,0xd7,0xf0,0xe0,0x01,0x08
+
+# GFX12: v_trig_preop_f64 v[5:6], -|src_scc|, src_scc mul:4 ; encoding: [0x05,0x01,0x2f,0xd7,0xfd,0xfa,0x01,0x30]
+0x05,0x01,0x2f,0xd7,0xfd,0xfa,0x01,0x30
+
+# GFX12: v_trig_preop_f64 v[254:255], 0xaf123456, 0xaf123456 clamp div:2 ; encoding: [0xfe,0x80,0x2f,0xd7,0xff,0xfe,0x01,0x18,0x56,0x34,0x12,0xaf]
+0xfe,0x80,0x2f,0xd7,0xff,0xfe,0x01,0x18,0x56,0x34,0x12,0xaf
+
+# GFX12: v_writelane_b32 v5, s1, s2              ; encoding: [0x05,0x00,0x61,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x61,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_writelane_b32 v5, s105, s2            ; encoding: [0x05,0x00,0x61,0xd7,0x69,0x04,0x00,0x00]
+0x05,0x00,0x61,0xd7,0x69,0x04,0x00,0x00
+
+# GFX12: v_writelane_b32 v5, vcc_lo, s2          ; encoding: [0x05,0x00,0x61,0xd7,0x6a,0x04,0x00,0x00]
+0x05,0x00,0x61,0xd7,0x6a,0x04,0x00,0x00
+
+# GFX12: v_writelane_b32 v5, vcc_hi, s2          ; encoding: [0x05,0x00,0x61,0xd7,0x6b,0x04,0x00,0x00]
+0x05,0x00,0x61,0xd7,0x6b,0x04,0x00,0x00
+
+# GFX12: v_writelane_b32 v5, ttmp15, s2          ; encoding: [0x05,0x00,0x61,0xd7,0x7b,0x04,0x00,0x00]
+0x05,0x00,0x61,0xd7,0x7b,0x04,0x00,0x00
+
+# GFX12: v_writelane_b32 v5, m0, s2              ; encoding: [0x05,0x00,0x61,0xd7,0x7d,0x04,0x00,0x00]
+0x05,0x00,0x61,0xd7,0x7d,0x04,0x00,0x00
+
+# GFX12: v_writelane_b32 v5, exec_lo, s2         ; encoding: [0x05,0x00,0x61,0xd7,0x7e,0x04,0x00,0x00]
+0x05,0x00,0x61,0xd7,0x7e,0x04,0x00,0x00
+
+# GFX12: v_writelane_b32 v5, exec_hi, s105       ; encoding: [0x05,0x00,0x61,0xd7,0x7f,0xd2,0x00,0x00]
+0x05,0x00,0x61,0xd7,0x7f,0xd2,0x00,0x00
+
+# GFX12: v_writelane_b32 v5, null, ttmp15        ; encoding: [0x05,0x00,0x61,0xd7,0x7c,0xf6,0x00,0x00]
+0x05,0x00,0x61,0xd7,0x7c,0xf6,0x00,0x00
+
+# GFX12: v_writelane_b32 v5, -1, null            ; encoding: [0x05,0x00,0x61,0xd7,0xc1,0xf8,0x00,0x00]
+0x05,0x00,0x61,0xd7,0xc1,0xf8,0x00,0x00
+
+# GFX12: v_writelane_b32 v5, 0.5, m0             ; encoding: [0x05,0x00,0x61,0xd7,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x61,0xd7,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_writelane_b32 v5, src_scc, vcc_lo     ; encoding: [0x05,0x00,0x61,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x61,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_writelane_b32 v255, 0xaf123456, vcc_hi ; encoding: [0xff,0x00,0x61,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x61,0xd7,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_xad_u32 v5, v1, v2, s3                ; encoding: [0x05,0x00,0x45,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x45,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_xad_u32 v5, v255, s2, s105            ; encoding: [0x05,0x00,0x45,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x45,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_xad_u32 v5, s1, v255, exec_hi         ; encoding: [0x05,0x00,0x45,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x45,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_xad_u32 v5, s105, s105, exec_lo       ; encoding: [0x05,0x00,0x45,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x45,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_xad_u32 v5, vcc_lo, ttmp15, v3        ; encoding: [0x05,0x00,0x45,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x45,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_xad_u32 v5, vcc_hi, 0xaf123456, v255  ; encoding: [0x05,0x00,0x45,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x45,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_xad_u32 v5, ttmp15, src_scc, ttmp15   ; encoding: [0x05,0x00,0x45,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x45,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_xad_u32 v5, m0, 0.5, m0               ; encoding: [0x05,0x00,0x45,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x45,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_xad_u32 v5, exec_lo, -1, vcc_hi       ; encoding: [0x05,0x00,0x45,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x45,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_xad_u32 v5, exec_hi, null, vcc_lo     ; encoding: [0x05,0x00,0x45,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x45,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_xad_u32 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x45,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x45,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_xad_u32 v5, -1, exec_hi, src_scc      ; encoding: [0x05,0x00,0x45,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x45,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_xad_u32 v5, 0.5, m0, 0.5              ; encoding: [0x05,0x00,0x45,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x45,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_xad_u32 v5, src_scc, vcc_lo, -1       ; encoding: [0x05,0x00,0x45,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x45,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_xad_u32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x45,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x45,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_xor3_b32 v5, v1, v2, s3               ; encoding: [0x05,0x00,0x40,0xd6,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x40,0xd6,0x01,0x05,0x0e,0x00
+
+# GFX12: v_xor3_b32 v5, v255, s2, s105           ; encoding: [0x05,0x00,0x40,0xd6,0xff,0x05,0xa4,0x01]
+0x05,0x00,0x40,0xd6,0xff,0x05,0xa4,0x01
+
+# GFX12: v_xor3_b32 v5, s1, v255, exec_hi        ; encoding: [0x05,0x00,0x40,0xd6,0x01,0xfe,0xff,0x01]
+0x05,0x00,0x40,0xd6,0x01,0xfe,0xff,0x01
+
+# GFX12: v_xor3_b32 v5, s105, s105, exec_lo      ; encoding: [0x05,0x00,0x40,0xd6,0x69,0xd2,0xf8,0x01]
+0x05,0x00,0x40,0xd6,0x69,0xd2,0xf8,0x01
+
+# GFX12: v_xor3_b32 v5, vcc_lo, ttmp15, v3       ; encoding: [0x05,0x00,0x40,0xd6,0x6a,0xf6,0x0c,0x04]
+0x05,0x00,0x40,0xd6,0x6a,0xf6,0x0c,0x04
+
+# GFX12: v_xor3_b32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x40,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x40,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+
+# GFX12: v_xor3_b32 v5, ttmp15, src_scc, ttmp15  ; encoding: [0x05,0x00,0x40,0xd6,0x7b,0xfa,0xed,0x01]
+0x05,0x00,0x40,0xd6,0x7b,0xfa,0xed,0x01
+
+# GFX12: v_xor3_b32 v5, m0, 0.5, m0              ; encoding: [0x05,0x00,0x40,0xd6,0x7d,0xe0,0xf5,0x01]
+0x05,0x00,0x40,0xd6,0x7d,0xe0,0xf5,0x01
+
+# GFX12: v_xor3_b32 v5, exec_lo, -1, vcc_hi      ; encoding: [0x05,0x00,0x40,0xd6,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x40,0xd6,0x7e,0x82,0xad,0x01
+
+# GFX12: v_xor3_b32 v5, exec_hi, null, vcc_lo    ; encoding: [0x05,0x00,0x40,0xd6,0x7f,0xf8,0xa8,0x01]
+0x05,0x00,0x40,0xd6,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_xor3_b32 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x00,0x40,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x40,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf
+
+# GFX12: v_xor3_b32 v5, -1, exec_hi, src_scc     ; encoding: [0x05,0x00,0x40,0xd6,0xc1,0xfe,0xf4,0x03]
+0x05,0x00,0x40,0xd6,0xc1,0xfe,0xf4,0x03
+
+# GFX12: v_xor3_b32 v5, 0.5, m0, 0.5             ; encoding: [0x05,0x00,0x40,0xd6,0xf0,0xfa,0xc0,0x03]
+0x05,0x00,0x40,0xd6,0xf0,0xfa,0xc0,0x03
+
+# GFX12: v_xor3_b32 v5, src_scc, vcc_lo, -1      ; encoding: [0x05,0x00,0x40,0xd6,0xfd,0xd4,0x04,0x03]
+0x05,0x00,0x40,0xd6,0xfd,0xd4,0x04,0x03
+
+# GFX12: v_xor3_b32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x40,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x40,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_xor_b16 v5, v1, v2                    ; encoding: [0x05,0x00,0x64,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x00,0x64,0xd7,0x01,0x05,0x02,0x00
+
+# GFX12: v_xor_b16 v5, v255, v255                ; encoding: [0x05,0x00,0x64,0xd7,0xff,0xff,0x03,0x00]
+0x05,0x00,0x64,0xd7,0xff,0xff,0x03,0x00
+
+# GFX12: v_xor_b16 v5, s1, s2                    ; encoding: [0x05,0x00,0x64,0xd7,0x01,0x04,0x00,0x00]
+0x05,0x00,0x64,0xd7,0x01,0x04,0x00,0x00
+
+# GFX12: v_xor_b16 v5, s105, s105                ; encoding: [0x05,0x00,0x64,0xd7,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x64,0xd7,0x69,0xd2,0x00,0x00
+
+# GFX12: v_xor_b16 v5, vcc_lo, ttmp15            ; encoding: [0x05,0x00,0x64,0xd7,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x64,0xd7,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_xor_b16 v5, vcc_hi, 0xfe0b            ; encoding: [0x05,0x00,0x64,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x64,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_xor_b16 v5, ttmp15, src_scc           ; encoding: [0x05,0x00,0x64,0xd7,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x64,0xd7,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_xor_b16 v5, m0, 0x3800
+0x05,0x00,0x64,0xd7,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_xor_b16 v5, exec_lo, -1               ; encoding: [0x05,0x00,0x64,0xd7,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x64,0xd7,0x7e,0x82,0x01,0x00
+
+# GFX12: v_xor_b16 v5, exec_hi, null             ; encoding: [0x05,0x00,0x64,0xd7,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x64,0xd7,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_xor_b16 v5, null, exec_lo             ; encoding: [0x05,0x00,0x64,0xd7,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x64,0xd7,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_xor_b16 v5, -1, exec_hi               ; encoding: [0x05,0x00,0x64,0xd7,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x64,0xd7,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_xor_b16 v5, 0x3800, m0
+0x05,0x00,0x64,0xd7,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_xor_b16 v5, src_scc, vcc_lo           ; encoding: [0x05,0x00,0x64,0xd7,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x64,0xd7,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_xor_b16 v255, 0xfe0b, vcc_hi          ; encoding: [0xff,0x00,0x64,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0xff,0x00,0x64,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt
new file mode 100644
index 000000000000..40204c0dfdf4
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt
@@ -0,0 +1,4112 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32 %s
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64 %s
+
+# GFX12: v_add3_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x55,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x55,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_add3_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x55,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x55,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_add3_u32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x55,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x55,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_add3_u32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x55,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_add3_u32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x55,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_add3_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x55,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_add3_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x55,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_add3_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x55,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_add3_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x55,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_add3_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x55,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_add3_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x55,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_add3_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x55,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x55,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_add3_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x55,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_add3_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x55,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x55,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# W32: v_add_co_u32_e64_dpp v5, s12, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_add_co_u32_e64_dpp v5, s12, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_add_co_u32_e64_dpp v5, s12, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_add_co_u32_e64_dpp v5, s12, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_add_co_u32_e64_dpp v5, s12, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_add_co_u32_e64_dpp v5, s12, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_add_co_u32_e64_dpp v5, s12, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_add_co_u32_e64_dpp v5, s12, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_add_co_u32_e64_dpp v5, s12, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_add_co_u32_e64_dpp v5, s12, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_add_co_u32_e64_dpp v5, s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x68,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_add_co_u32_e64_dpp v5, s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x68,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x68,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_add_co_u32_e64_dpp v5, vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x6a,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_add_co_u32_e64_dpp v5, vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x6a,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x6a,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_add_co_u32_e64_dpp v5, ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x7a,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_add_co_u32_e64_dpp v5, ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x7a,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x7a,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_add_co_u32_e64_dpp v255, null, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0xfc,0x00,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0xfc,0x00,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_add_lshl_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x47,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x47,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_add_lshl_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x47,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x47,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_add_lshl_u32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x47,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x47,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_add_lshl_u32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x47,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_add_lshl_u32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x47,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_add_lshl_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x47,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_add_lshl_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x47,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_add_lshl_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x47,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_add_lshl_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x47,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_add_lshl_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x47,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_add_lshl_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x47,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_add_lshl_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x47,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x47,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_add_lshl_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x47,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_add_lshl_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x47,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x47,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_add_nc_i32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_add_nc_i32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_add_nc_i32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_add_nc_i32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_add_nc_i32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_add_nc_i32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_add_nc_i32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_add_nc_i32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_add_nc_i32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_add_nc_i32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_add_nc_i32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_add_nc_i32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_add_nc_i32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_add_nc_i32_e64_dpp v255, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x80,0x26,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x80,0x26,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, v3 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
+0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff
+
+# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, v255 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
+0x05,0x00,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff
+
+# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, s105 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x16,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, vcc_hi row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x16,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, vcc_lo row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x16,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, ttmp15 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x16,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, exec_hi row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x16,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, exec_lo row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x16,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, null row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x16,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01
+
+# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, -1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x16,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_alignbit_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x16,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x16,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_alignbyte_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x17,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x17,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_alignbyte_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x17,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x17,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_alignbyte_b32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x17,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x17,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_alignbyte_b32_e64_dpp v5, v1, v2, v3 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x17,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
+0x05,0x00,0x17,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff
+
+# GFX12: v_alignbyte_b32_e64_dpp v5, v1, v2, v255 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
+0x05,0x00,0x17,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff
+
+# GFX12: v_alignbyte_b32_e64_dpp v5, v1, v2, s105 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x17,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_alignbyte_b32_e64_dpp v5, v1, v2, vcc_hi row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x17,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_alignbyte_b32_e64_dpp v5, v1, v2, vcc_lo row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x17,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_alignbyte_b32_e64_dpp v5, v1, v2, ttmp15 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x17,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_alignbyte_b32_e64_dpp v5, v1, v2, exec_hi row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x17,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_alignbyte_b32_e64_dpp v5, v1, v2, exec_lo row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x17,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_alignbyte_b32_e64_dpp v5, v1, v2, null row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x17,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01
+
+# GFX12: v_alignbyte_b32_e64_dpp v5, v1, v2, -1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x17,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x17,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_alignbyte_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x17,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x17,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_and_b16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_and_b16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_and_b16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_and_b16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_and_b16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_and_b16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_and_b16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_and_b16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_and_b16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_and_b16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_and_b16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_and_b16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_and_b16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_and_b16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x62,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x62,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_and_or_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x57,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x57,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_and_or_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x57,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x57,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_and_or_b32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x57,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x57,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_and_or_b32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x57,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_and_or_b32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x57,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_and_or_b32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x57,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_and_or_b32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x57,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_and_or_b32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x57,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_and_or_b32_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x57,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_and_or_b32_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x57,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_and_or_b32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x57,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_and_or_b32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x57,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x57,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_and_or_b32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x57,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_and_or_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x57,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x57,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_ashrrev_i16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_ashrrev_i16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_ashrrev_i16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_ashrrev_i16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_ashrrev_i16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_ashrrev_i16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_ashrrev_i16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_ashrrev_i16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_ashrrev_i16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_ashrrev_i16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_ashrrev_i16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_ashrrev_i16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_ashrrev_i16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_ashrrev_i16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x3a,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x3a,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_bcnt_u32_b32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_bcnt_u32_b32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_bcnt_u32_b32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x1e,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x1e,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_bfe_i32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x11,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_bfe_i32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x11,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_bfe_i32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x11,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_bfe_i32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x11,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_bfe_i32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x11,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_bfe_i32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x11,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_bfe_i32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x11,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_bfe_i32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x11,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_bfe_i32_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x11,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_bfe_i32_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x11,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_bfe_i32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x11,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_bfe_i32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x11,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x11,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_bfe_i32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x11,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_bfe_i32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x11,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x11,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_bfe_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x10,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x10,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_bfe_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x10,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x10,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_bfe_u32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x10,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x10,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_bfe_u32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x10,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_bfe_u32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x10,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_bfe_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x10,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_bfe_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x10,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_bfe_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x10,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_bfe_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x10,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_bfe_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x10,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_bfe_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x10,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_bfe_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x10,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x10,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_bfe_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x10,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_bfe_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x10,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x10,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_bfi_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x12,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_bfi_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x12,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_bfi_b32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x12,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_bfi_b32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x12,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_bfi_b32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x12,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_bfi_b32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x12,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_bfi_b32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x12,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_bfi_b32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x12,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_bfi_b32_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x12,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_bfi_b32_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x12,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_bfi_b32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x12,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_bfi_b32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x12,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x12,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_bfi_b32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x12,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_bfi_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x12,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x12,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_bfm_b32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_bfm_b32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_bfm_b32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_bfm_b32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_bfm_b32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_bfm_b32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_bfm_b32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_bfm_b32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_bfm_b32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_bfm_b32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_bfm_b32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_bfm_b32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_bfm_b32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_bfm_b32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x1d,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x1d,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_cndmask_b16_e64_dpp v5, v1, v2, s6 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cndmask_b16_e64_dpp v5, v1, v2, s6 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cndmask_b16_e64_dpp v5, v1, v2, s6 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cndmask_b16_e64_dpp v5, v1, v2, s6 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cndmask_b16_e64_dpp v5, v1, v2, s6 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cndmask_b16_e64_dpp v5, v1, v2, s6 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cndmask_b16_e64_dpp v5, v1, v2, s6 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cndmask_b16_e64_dpp v5, v1, v2, s6 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cndmask_b16_e64_dpp v5, v1, v2, s6 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cndmask_b16_e64_dpp v5, v1, v2, s6 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cndmask_b16_e64_dpp v5, v1, v2, s104 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0xa2,0x01,0x01,0x50,0x01,0xff]
+# W64: v_cndmask_b16_e64_dpp v5, v1, v2, s[104:105] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0xa2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x5d,0xd6,0xfa,0x04,0xa2,0x01,0x01,0x50,0x01,0xff
+
+# W32: v_cndmask_b16_e64_dpp v5, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x5f,0x01,0x01]
+# W64: v_cndmask_b16_e64_dpp v5, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x5d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x5f,0x01,0x01
+
+# W32: v_cndmask_b16_e64_dpp v5, v1, v2, ttmp14 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0xea,0x01,0x01,0x60,0x01,0x13]
+# W64: v_cndmask_b16_e64_dpp v5, v1, v2, ttmp[14:15] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0xea,0x01,0x01,0x60,0x01,0x13]
+0x05,0x00,0x5d,0xd6,0xfa,0x04,0xea,0x01,0x01,0x60,0x01,0x13
+
+# GFX12: v_cndmask_b16_e64_dpp v255, v255, v255, null row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x5d,0xd6,0xfa,0xfe,0xf3,0x01,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x5d,0xd6,0xfa,0xfe,0xf3,0x01,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cubeid_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x0c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cubeid_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x0c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cubeid_f32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x0c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_cubeid_f32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x0c,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_cubeid_f32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x0c,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_cubeid_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x0c,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cubeid_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x0c,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_cubeid_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x01,0x0c,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+0x05,0x01,0x0c,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cubeid_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x02,0x0c,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+0x05,0x02,0x0c,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff
+
+# GFX12: v_cubeid_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x04,0x0c,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+0x05,0x04,0x0c,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cubeid_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x03,0x0c,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+0x05,0x03,0x0c,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff
+
+# GFX12: v_cubeid_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x05,0x0c,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
+0x05,0x05,0x0c,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cubeid_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x06,0x0c,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x01,0x13]
+0x05,0x06,0x0c,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x01,0x13
+
+# GFX12: v_cubeid_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x87,0x0c,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30]
+0xff,0x87,0x0c,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cubema_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x0f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cubema_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x0f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cubema_f32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x0f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_cubema_f32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x0f,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_cubema_f32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x0f,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_cubema_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x0f,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cubema_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x0f,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_cubema_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x01,0x0f,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+0x05,0x01,0x0f,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cubema_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x02,0x0f,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+0x05,0x02,0x0f,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff
+
+# GFX12: v_cubema_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x04,0x0f,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+0x05,0x04,0x0f,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cubema_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x03,0x0f,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+0x05,0x03,0x0f,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff
+
+# GFX12: v_cubema_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x05,0x0f,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
+0x05,0x05,0x0f,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cubema_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x06,0x0f,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x01,0x13]
+0x05,0x06,0x0f,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x01,0x13
+
+# GFX12: v_cubema_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x87,0x0f,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30]
+0xff,0x87,0x0f,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cubesc_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x0d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cubesc_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x0d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cubesc_f32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x0d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_cubesc_f32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x0d,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_cubesc_f32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x0d,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_cubesc_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x0d,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cubesc_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x0d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_cubesc_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x01,0x0d,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+0x05,0x01,0x0d,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cubesc_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x02,0x0d,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+0x05,0x02,0x0d,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff
+
+# GFX12: v_cubesc_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x04,0x0d,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+0x05,0x04,0x0d,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cubesc_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x03,0x0d,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+0x05,0x03,0x0d,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff
+
+# GFX12: v_cubesc_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x05,0x0d,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
+0x05,0x05,0x0d,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cubesc_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x06,0x0d,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x01,0x13]
+0x05,0x06,0x0d,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x01,0x13
+
+# GFX12: v_cubesc_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x87,0x0d,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30]
+0xff,0x87,0x0d,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cubetc_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x0e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cubetc_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x0e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cubetc_f32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x0e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_cubetc_f32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x0e,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_cubetc_f32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x0e,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_cubetc_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x0e,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cubetc_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x0e,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_cubetc_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x01,0x0e,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+0x05,0x01,0x0e,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cubetc_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x02,0x0e,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+0x05,0x02,0x0e,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff
+
+# GFX12: v_cubetc_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x04,0x0e,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+0x05,0x04,0x0e,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cubetc_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x03,0x0e,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+0x05,0x03,0x0e,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff
+
+# GFX12: v_cubetc_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x05,0x0e,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
+0x05,0x05,0x0e,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cubetc_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x06,0x0e,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x01,0x13]
+0x05,0x06,0x0e,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x01,0x13
+
+# GFX12: v_cubetc_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x87,0x0e,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30]
+0xff,0x87,0x0e,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_pk_i16_f32_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x06,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x05,0x01,0x06,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_pk_i16_f32_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x02,0x06,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x05,0x02,0x06,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_pk_i16_f32_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x03,0x06,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0xff,0x03,0x06,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_pk_i16_i32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x24,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x24,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_pk_u16_f32_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x07,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x05,0x01,0x07,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_pk_u16_f32_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x02,0x07,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x05,0x02,0x07,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_pk_u16_f32_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x03,0x07,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0xff,0x03,0x07,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_pk_u16_u32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x23,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x23,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x26,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x26,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x26,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x26,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x26,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x26,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x26,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x26,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x26,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x26,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x26,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x26,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x26,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x26,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_pk_u8_f32_e64_dpp v255, -|v255|, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x01,0x26,0xd6,0xfa,0xfe,0xf7,0x23,0xff,0x6f,0x0d,0x30]
+0xff,0x01,0x26,0xd6,0xfa,0xfe,0xf7,0x23,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_i16_f32_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x21,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x05,0x01,0x21,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_pk_norm_i16_f32_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x02,0x21,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x05,0x02,0x21,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_pk_norm_i16_f32_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x03,0x21,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0xff,0x03,0x21,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_u16_f32_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x22,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x05,0x01,0x22,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_pk_norm_u16_f32_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x02,0x22,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x05,0x02,0x22,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_pk_norm_u16_f32_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x03,0x22,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0xff,0x03,0x22,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_fma_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x13,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_fma_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x13,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_fma_f32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x13,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_fma_f32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x13,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_fma_f32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x13,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_fma_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x13,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_fma_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x13,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_fma_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x01,0x13,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+0x05,0x01,0x13,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff
+
+# GFX12: v_fma_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x02,0x13,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+0x05,0x02,0x13,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff
+
+# GFX12: v_fma_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x04,0x13,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+0x05,0x04,0x13,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff
+
+# GFX12: v_fma_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x03,0x13,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+0x05,0x03,0x13,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff
+
+# GFX12: v_fma_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x05,0x13,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
+0x05,0x05,0x13,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01
+
+# GFX12: v_fma_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x06,0x13,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x01,0x13]
+0x05,0x06,0x13,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x01,0x13
+
+# GFX12: v_fma_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x87,0x13,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30]
+0xff,0x87,0x13,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_ldexp_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_ldexp_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_ldexp_f32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_ldexp_f32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_ldexp_f32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_ldexp_f32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_ldexp_f32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_ldexp_f32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_ldexp_f32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_ldexp_f32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_ldexp_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_ldexp_f32_e64_dpp v5, v1, v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_ldexp_f32_e64_dpp v5, v1, v2 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_ldexp_f32_e64_dpp v255, -|v255|, v255 clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0x1c,0xd7,0xfa,0xfe,0x03,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0x1c,0xd7,0xfa,0xfe,0x03,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_lerp_u8_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x15,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x15,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_lerp_u8_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x15,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x15,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_lerp_u8_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x15,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x15,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_lerp_u8_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x15,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_lerp_u8_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x15,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_lerp_u8_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x15,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_lerp_u8_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x15,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_lerp_u8_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x15,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_lerp_u8_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x15,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_lerp_u8_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x15,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_lerp_u8_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x15,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_lerp_u8_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x15,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x15,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_lerp_u8_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x15,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_lerp_u8_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x15,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x15,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_lshl_add_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x46,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x46,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_lshl_add_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x46,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x46,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_lshl_add_u32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x46,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x46,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_lshl_add_u32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x46,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_lshl_add_u32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x46,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_lshl_add_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x46,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_lshl_add_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x46,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_lshl_add_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x46,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_lshl_add_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x46,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_lshl_add_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x46,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_lshl_add_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x46,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_lshl_add_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x46,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x46,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_lshl_add_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x46,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_lshl_add_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x46,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x46,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_lshl_or_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x56,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x56,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_lshl_or_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x56,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x56,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_lshl_or_b32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x56,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x56,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_lshl_or_b32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x56,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_lshl_or_b32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x56,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_lshl_or_b32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x56,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_lshl_or_b32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x56,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_lshl_or_b32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x56,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_lshl_or_b32_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x56,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_lshl_or_b32_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x56,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_lshl_or_b32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x56,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_lshl_or_b32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x56,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x56,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_lshl_or_b32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x56,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_lshl_or_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x56,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x56,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_lshlrev_b16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_lshlrev_b16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_lshlrev_b16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_lshlrev_b16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_lshlrev_b16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_lshlrev_b16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_lshlrev_b16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_lshlrev_b16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_lshlrev_b16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_lshlrev_b16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_lshlrev_b16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_lshlrev_b16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_lshlrev_b16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_lshlrev_b16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x38,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x38,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_lshrrev_b16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_lshrrev_b16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_lshrrev_b16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_lshrrev_b16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_lshrrev_b16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_lshrrev_b16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_lshrrev_b16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_lshrrev_b16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_lshrrev_b16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_lshrrev_b16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_lshrrev_b16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_lshrrev_b16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_lshrrev_b16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_lshrrev_b16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x39,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x39,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_mad_i32_i24_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x0a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_mad_i32_i24_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x0a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_mad_i32_i24_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x0a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_mad_i32_i24_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x0a,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_mad_i32_i24_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x0a,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_mad_i32_i24_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x0a,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_mad_i32_i24_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x0a,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_mad_i32_i24_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x0a,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_mad_i32_i24_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x0a,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_mad_i32_i24_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x0a,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_mad_i32_i24_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x0a,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_mad_i32_i24_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x0a,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_mad_i32_i24_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x0a,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_mad_i32_i24_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x80,0x0a,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x80,0x0a,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_mad_u32_u24_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x0b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_mad_u32_u24_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x0b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_mad_u32_u24_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x0b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_mad_u32_u24_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x0b,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_mad_u32_u24_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x0b,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_mad_u32_u24_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x0b,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_mad_u32_u24_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x0b,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_mad_u32_u24_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x0b,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_mad_u32_u24_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x0b,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_mad_u32_u24_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x0b,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_mad_u32_u24_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x0b,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_mad_u32_u24_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x0b,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_mad_u32_u24_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x0b,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_mad_u32_u24_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x80,0x0b,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x80,0x0b,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_max3_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x2a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_max3_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x2a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_max3_num_f32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x2a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_max3_num_f32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2a,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x2a,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_max3_num_f32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2a,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x2a,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_max3_num_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2a,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x2a,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_max3_num_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2a,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x2a,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_max3_num_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x01,0x2a,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+0x05,0x01,0x2a,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff
+
+# GFX12: v_max3_num_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x02,0x2a,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+0x05,0x02,0x2a,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff
+
+# GFX12: v_max3_num_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x04,0x2a,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+0x05,0x04,0x2a,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff
+
+# GFX12: v_max3_num_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x03,0x2a,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+0x05,0x03,0x2a,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff
+
+# GFX12: v_max3_num_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x05,0x2a,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
+0x05,0x05,0x2a,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01
+
+# GFX12: v_max3_num_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x06,0x2a,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x01,0x13]
+0x05,0x06,0x2a,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x01,0x13
+
+# GFX12: v_max3_num_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x87,0x2a,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30]
+0xff,0x87,0x2a,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_max3_i32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x1d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_max3_i32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x1d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_max3_i32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x1d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_max3_i32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x1d,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_max3_i32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x1d,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_max3_i32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x1d,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_max3_i32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x1d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_max3_i32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x1d,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_max3_i32_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x1d,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_max3_i32_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x1d,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_max3_i32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x1d,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_max3_i32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x1d,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_max3_i32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x1d,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_max3_i32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x1d,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x1d,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_max3_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x1e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_max3_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x1e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_max3_u32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x1e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_max3_u32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x1e,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_max3_u32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x1e,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_max3_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x1e,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_max3_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x1e,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_max3_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x1e,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_max3_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x1e,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_max3_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x1e,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_max3_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x1e,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_max3_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x1e,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_max3_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x1e,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_max3_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x1e,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x1e,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_max_i16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_max_i16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_max_i16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_max_i16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_max_i16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_max_i16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_max_i16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_max_i16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_max_i16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_max_i16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_max_i16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_max_i16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_max_i16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_max_i16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x0a,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x0a,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_max_u16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_max_u16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_max_u16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_max_u16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_max_u16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_max_u16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_max_u16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_max_u16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_max_u16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_max_u16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_max_u16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_max_u16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_max_u16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_max_u16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x09,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x09,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_maxmin_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x6b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_maxmin_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x6b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_maxmin_num_f16_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x6b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_maxmin_num_f16_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6b,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x6b,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_maxmin_num_f16_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6b,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x6b,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_maxmin_num_f16_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6b,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x6b,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_maxmin_num_f16_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6b,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x6b,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_maxmin_num_f16_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x01,0x6b,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+0x05,0x01,0x6b,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff
+
+# GFX12: v_maxmin_num_f16_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x02,0x6b,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+0x05,0x02,0x6b,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff
+
+# GFX12: v_maxmin_num_f16_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x04,0x6b,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+0x05,0x04,0x6b,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff
+
+# GFX12: v_maxmin_num_f16_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x03,0x6b,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+0x05,0x03,0x6b,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff
+
+# GFX12: v_maxmin_num_f16_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x05,0x6b,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
+0x05,0x05,0x6b,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01
+
+# GFX12: v_maxmin_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x06,0x6b,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x01,0x13]
+0x05,0x06,0x6b,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x01,0x13
+
+# GFX12: v_maxmin_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x87,0x6b,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30]
+0xff,0x87,0x6b,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_maxmin_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x69,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x69,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_maxmin_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x69,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x69,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_maxmin_num_f32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x69,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x69,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_maxmin_num_f32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x69,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x69,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_maxmin_num_f32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x69,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x69,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_maxmin_num_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x69,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x69,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_maxmin_num_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x69,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x69,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_maxmin_num_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x01,0x69,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+0x05,0x01,0x69,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff
+
+# GFX12: v_maxmin_num_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x02,0x69,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+0x05,0x02,0x69,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff
+
+# GFX12: v_maxmin_num_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x04,0x69,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+0x05,0x04,0x69,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff
+
+# GFX12: v_maxmin_num_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x03,0x69,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+0x05,0x03,0x69,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff
+
+# GFX12: v_maxmin_num_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x05,0x69,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
+0x05,0x05,0x69,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01
+
+# GFX12: v_maxmin_num_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x06,0x69,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x01,0x13]
+0x05,0x06,0x69,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x01,0x13
+
+# GFX12: v_maxmin_num_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x87,0x69,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30]
+0xff,0x87,0x69,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_maxmin_i32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x64,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x64,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_maxmin_i32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x64,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x64,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_maxmin_i32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x64,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x64,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_maxmin_i32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x64,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_maxmin_i32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x64,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_maxmin_i32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x64,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_maxmin_i32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x64,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_maxmin_i32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x64,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_maxmin_i32_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x64,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_maxmin_i32_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x64,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_maxmin_i32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x64,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_maxmin_i32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x64,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x64,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_maxmin_i32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x64,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_maxmin_i32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x64,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x64,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_maxmin_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x62,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x62,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_maxmin_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x62,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x62,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_maxmin_u32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x62,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x62,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_maxmin_u32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x62,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_maxmin_u32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x62,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_maxmin_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x62,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_maxmin_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x62,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_maxmin_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x62,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_maxmin_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x62,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_maxmin_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x62,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_maxmin_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x62,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_maxmin_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x62,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x62,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_maxmin_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x62,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_maxmin_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x62,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x62,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_mbcnt_hi_u32_b32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x20,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x20,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_mbcnt_lo_u32_b32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x1f,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x1f,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_med3_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x31,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x31,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_med3_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x31,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x31,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_med3_num_f32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x31,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x31,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_med3_num_f32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x31,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x31,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_med3_num_f32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x31,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x31,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_med3_num_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x31,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x31,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_med3_num_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x31,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x31,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_med3_num_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x01,0x31,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+0x05,0x01,0x31,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff
+
+# GFX12: v_med3_num_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x02,0x31,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+0x05,0x02,0x31,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff
+
+# GFX12: v_med3_num_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x04,0x31,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+0x05,0x04,0x31,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff
+
+# GFX12: v_med3_num_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x03,0x31,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+0x05,0x03,0x31,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff
+
+# GFX12: v_med3_num_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x05,0x31,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
+0x05,0x05,0x31,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01
+
+# GFX12: v_med3_num_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x06,0x31,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x01,0x13]
+0x05,0x06,0x31,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x01,0x13
+
+# GFX12: v_med3_num_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x87,0x31,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30]
+0xff,0x87,0x31,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_med3_i32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x20,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x20,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_med3_i32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x20,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x20,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_med3_i32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x20,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x20,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_med3_i32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x20,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_med3_i32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x20,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_med3_i32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x20,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_med3_i32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x20,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_med3_i32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x20,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_med3_i32_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x20,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_med3_i32_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x20,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_med3_i32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x20,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_med3_i32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x20,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x20,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_med3_i32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x20,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_med3_i32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x20,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x20,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_med3_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x21,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_med3_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x21,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_med3_u32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x21,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_med3_u32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x21,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_med3_u32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x21,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_med3_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x21,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_med3_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x21,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_med3_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x21,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_med3_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x21,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_med3_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x21,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_med3_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x21,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_med3_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x21,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x21,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_med3_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x21,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_med3_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x21,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x21,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_min3_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x29,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x29,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_min3_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x29,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x29,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_min3_num_f32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x29,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x29,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_min3_num_f32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x29,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x29,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_min3_num_f32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x29,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x29,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_min3_num_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x29,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x29,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_min3_num_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x29,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x29,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_min3_num_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x01,0x29,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+0x05,0x01,0x29,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff
+
+# GFX12: v_min3_num_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x02,0x29,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+0x05,0x02,0x29,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff
+
+# GFX12: v_min3_num_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x04,0x29,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+0x05,0x04,0x29,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff
+
+# GFX12: v_min3_num_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x03,0x29,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+0x05,0x03,0x29,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff
+
+# GFX12: v_min3_num_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x05,0x29,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
+0x05,0x05,0x29,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01
+
+# GFX12: v_min3_num_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x06,0x29,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x01,0x13]
+0x05,0x06,0x29,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x01,0x13
+
+# GFX12: v_min3_num_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x87,0x29,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30]
+0xff,0x87,0x29,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_min3_i32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x1a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_min3_i32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x1a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_min3_i32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x1a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_min3_i32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x1a,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_min3_i32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x1a,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_min3_i32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x1a,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_min3_i32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x1a,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_min3_i32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x1a,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_min3_i32_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x1a,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_min3_i32_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x1a,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_min3_i32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x1a,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_min3_i32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x1a,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_min3_i32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x1a,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_min3_i32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x1a,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x1a,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_min3_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x1b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_min3_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x1b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_min3_u32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x1b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_min3_u32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x1b,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_min3_u32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x1b,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_min3_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x1b,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_min3_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x1b,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_min3_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x1b,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_min3_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x1b,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_min3_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x1b,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_min3_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x1b,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_min3_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x1b,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_min3_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x1b,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_min3_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x1b,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x1b,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_min_i16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_min_i16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_min_i16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_min_i16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_min_i16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_min_i16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_min_i16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_min_i16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_min_i16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_min_i16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_min_i16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_min_i16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_min_i16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_min_i16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x0c,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x0c,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_min_u16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_min_u16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_min_u16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_min_u16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_min_u16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_min_u16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_min_u16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_min_u16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_min_u16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_min_u16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_min_u16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_min_u16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_min_u16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_min_u16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x0b,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x0b,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_minmax_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x6a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_minmax_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x6a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_minmax_num_f16_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x6a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_minmax_num_f16_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6a,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x6a,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_minmax_num_f16_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6a,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x6a,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_minmax_num_f16_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6a,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x6a,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_minmax_num_f16_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6a,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x6a,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_minmax_num_f16_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x01,0x6a,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+0x05,0x01,0x6a,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff
+
+# GFX12: v_minmax_num_f16_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x02,0x6a,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+0x05,0x02,0x6a,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff
+
+# GFX12: v_minmax_num_f16_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x04,0x6a,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+0x05,0x04,0x6a,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff
+
+# GFX12: v_minmax_num_f16_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x03,0x6a,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+0x05,0x03,0x6a,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff
+
+# GFX12: v_minmax_num_f16_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x05,0x6a,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
+0x05,0x05,0x6a,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01
+
+# GFX12: v_minmax_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x06,0x6a,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x01,0x13]
+0x05,0x06,0x6a,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x01,0x13
+
+# GFX12: v_minmax_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x87,0x6a,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30]
+0xff,0x87,0x6a,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_minmax_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x68,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x68,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_minmax_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x68,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x68,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_minmax_num_f32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x68,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x68,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_minmax_num_f32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x68,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x68,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_minmax_num_f32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x68,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x68,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_minmax_num_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x68,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x68,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_minmax_num_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x68,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x68,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_minmax_num_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x01,0x68,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+0x05,0x01,0x68,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff
+
+# GFX12: v_minmax_num_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x02,0x68,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+0x05,0x02,0x68,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff
+
+# GFX12: v_minmax_num_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x04,0x68,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+0x05,0x04,0x68,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff
+
+# GFX12: v_minmax_num_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x03,0x68,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+0x05,0x03,0x68,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff
+
+# GFX12: v_minmax_num_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x05,0x68,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
+0x05,0x05,0x68,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01
+
+# GFX12: v_minmax_num_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x06,0x68,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x01,0x13]
+0x05,0x06,0x68,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x01,0x13
+
+# GFX12: v_minmax_num_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x87,0x68,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30]
+0xff,0x87,0x68,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_minmax_i32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x65,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x65,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_minmax_i32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x65,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x65,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_minmax_i32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x65,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x65,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_minmax_i32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x65,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_minmax_i32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x65,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_minmax_i32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x65,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_minmax_i32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x65,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_minmax_i32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x65,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_minmax_i32_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x65,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_minmax_i32_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x65,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_minmax_i32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x65,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_minmax_i32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x65,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x65,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_minmax_i32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x65,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_minmax_i32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x65,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x65,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_minmax_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x63,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x63,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_minmax_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x63,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x63,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_minmax_u32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x63,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x63,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_minmax_u32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x63,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_minmax_u32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x63,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_minmax_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x63,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_minmax_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x63,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_minmax_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x63,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_minmax_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x63,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_minmax_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x63,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_minmax_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x63,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_minmax_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x63,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x63,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_minmax_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x63,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_minmax_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x63,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x63,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_msad_u8_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x39,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x39,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_msad_u8_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x39,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x39,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_msad_u8_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x39,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x39,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_msad_u8_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x39,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_msad_u8_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x39,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_msad_u8_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x39,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_msad_u8_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x39,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_msad_u8_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x39,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_msad_u8_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x39,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_msad_u8_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x39,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_msad_u8_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x39,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_msad_u8_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x39,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x39,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_msad_u8_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x39,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_msad_u8_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x80,0x39,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x80,0x39,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_mul_lo_u16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_mul_lo_u16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_mul_lo_u16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_mul_lo_u16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_mul_lo_u16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_mul_lo_u16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_mul_lo_u16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_mul_lo_u16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_mul_lo_u16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_mul_lo_u16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_mul_lo_u16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_mul_lo_u16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_mul_lo_u16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_mul_lo_u16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x05,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x05,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_mullit_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x18,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x18,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_mullit_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x18,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x18,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_mullit_f32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x18,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x18,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_mullit_f32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x18,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x18,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_mullit_f32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x18,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x18,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_mullit_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x18,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x18,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_mullit_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x18,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x18,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_mullit_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x01,0x18,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
+0x05,0x01,0x18,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff
+
+# GFX12: v_mullit_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x02,0x18,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+0x05,0x02,0x18,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff
+
+# GFX12: v_mullit_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x04,0x18,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+0x05,0x04,0x18,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff
+
+# GFX12: v_mullit_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x03,0x18,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+0x05,0x03,0x18,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff
+
+# GFX12: v_mullit_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x05,0x18,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
+0x05,0x05,0x18,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01
+
+# GFX12: v_mullit_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x06,0x18,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x01,0x13]
+0x05,0x06,0x18,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x01,0x13
+
+# GFX12: v_mullit_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x87,0x18,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30]
+0xff,0x87,0x18,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_or3_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x58,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x58,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_or3_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x58,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x58,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_or3_b32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x58,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x58,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_or3_b32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x58,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_or3_b32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x58,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_or3_b32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x58,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_or3_b32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x58,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_or3_b32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x58,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_or3_b32_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x58,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_or3_b32_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x58,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_or3_b32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x58,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_or3_b32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x58,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x58,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_or3_b32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x58,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_or3_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x58,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x58,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_or_b16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_or_b16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_or_b16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_or_b16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_or_b16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_or_b16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_or_b16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_or_b16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_or_b16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_or_b16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_or_b16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_or_b16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_or_b16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_or_b16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x63,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x63,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_perm_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x44,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x44,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_perm_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x44,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x44,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_perm_b32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x44,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x44,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_perm_b32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x44,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_perm_b32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x44,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_perm_b32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x44,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_perm_b32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x44,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_perm_b32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x44,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_perm_b32_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x44,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_perm_b32_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x44,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_perm_b32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x44,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_perm_b32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x44,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x44,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_perm_b32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x44,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_perm_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x44,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x44,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_sad_hi_u8_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x23,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x23,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_sad_hi_u8_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x23,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x23,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_sad_hi_u8_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x23,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x23,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_sad_hi_u8_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x23,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_sad_hi_u8_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x23,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_sad_hi_u8_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x23,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_sad_hi_u8_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x23,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_sad_hi_u8_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x23,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_sad_hi_u8_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x23,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_sad_hi_u8_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x23,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_sad_hi_u8_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x23,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_sad_hi_u8_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x23,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x23,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_sad_hi_u8_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x23,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_sad_hi_u8_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x80,0x23,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x80,0x23,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_sad_u16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x24,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x24,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_sad_u16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x24,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x24,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_sad_u16_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x24,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x24,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_sad_u16_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x24,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_sad_u16_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x24,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_sad_u16_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x24,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_sad_u16_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x24,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_sad_u16_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x24,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_sad_u16_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x24,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_sad_u16_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x24,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_sad_u16_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x24,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_sad_u16_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x24,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x24,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_sad_u16_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x24,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_sad_u16_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x80,0x24,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x80,0x24,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_sad_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x25,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_sad_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x25,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_sad_u32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x25,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_sad_u32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x25,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_sad_u32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x25,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_sad_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x25,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_sad_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x25,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_sad_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x25,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_sad_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x25,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_sad_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x25,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_sad_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x25,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_sad_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x25,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x25,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_sad_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x25,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_sad_u32_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x80,0x25,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x80,0x25,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_sad_u8_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x22,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_sad_u8_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x22,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_sad_u8_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x22,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_sad_u8_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x22,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_sad_u8_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x22,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_sad_u8_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x22,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_sad_u8_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x22,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_sad_u8_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x22,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_sad_u8_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x22,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_sad_u8_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x22,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_sad_u8_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x22,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_sad_u8_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x22,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x22,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_sad_u8_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x22,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_sad_u8_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x80,0x22,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x80,0x22,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# W32: v_sub_co_u32_e64_dpp v5, s12, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_sub_co_u32_e64_dpp v5, s12, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_sub_co_u32_e64_dpp v5, s12, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_sub_co_u32_e64_dpp v5, s12, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_sub_co_u32_e64_dpp v5, s12, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_sub_co_u32_e64_dpp v5, s12, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_sub_co_u32_e64_dpp v5, s12, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_sub_co_u32_e64_dpp v5, s12, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_sub_co_u32_e64_dpp v5, s12, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_sub_co_u32_e64_dpp v5, s12, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_sub_co_u32_e64_dpp v5, s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x68,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_sub_co_u32_e64_dpp v5, s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x68,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x68,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_sub_co_u32_e64_dpp v5, vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x6a,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_sub_co_u32_e64_dpp v5, vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x6a,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x6a,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_sub_co_u32_e64_dpp v5, ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x7a,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_sub_co_u32_e64_dpp v5, ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x7a,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x7a,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_sub_co_u32_e64_dpp v255, null, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0xfc,0x01,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0xfc,0x01,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_sub_nc_i32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_sub_nc_i32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_sub_nc_i32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_sub_nc_i32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_sub_nc_i32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_sub_nc_i32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_sub_nc_i32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_sub_nc_i32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_sub_nc_i32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_sub_nc_i32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_sub_nc_i32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_sub_nc_i32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_sub_nc_i32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_sub_nc_i32_e64_dpp v255, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x80,0x25,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x80,0x25,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_subrev_co_u32_e64_dpp v5, s12, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_subrev_co_u32_e64_dpp v5, s12, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_subrev_co_u32_e64_dpp v5, s12, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_subrev_co_u32_e64_dpp v5, s12, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_subrev_co_u32_e64_dpp v5, s12, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_subrev_co_u32_e64_dpp v5, s12, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_subrev_co_u32_e64_dpp v5, s12, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_subrev_co_u32_e64_dpp v5, s12, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_subrev_co_u32_e64_dpp v5, s12, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_subrev_co_u32_e64_dpp v5, s12, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_subrev_co_u32_e64_dpp v5, s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x68,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_subrev_co_u32_e64_dpp v5, s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x68,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x68,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_subrev_co_u32_e64_dpp v5, vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x6a,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_subrev_co_u32_e64_dpp v5, vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x6a,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x6a,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_subrev_co_u32_e64_dpp v5, ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x7a,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_subrev_co_u32_e64_dpp v5, ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x7a,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x7a,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_subrev_co_u32_e64_dpp v255, null, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0xfc,0x02,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0xfc,0x02,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_xad_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x45,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x45,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_xad_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x45,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x45,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_xad_u32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x45,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x45,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_xad_u32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x45,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_xad_u32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x45,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_xad_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x45,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_xad_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x45,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_xad_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x45,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_xad_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x45,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_xad_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x45,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_xad_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x45,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_xad_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x45,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x45,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_xad_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x45,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_xad_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x45,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x45,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_xor3_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x40,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x40,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_xor3_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x40,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x40,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_xor3_b32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x40,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+0x05,0x00,0x40,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
+
+# GFX12: v_xor3_b32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
+0x05,0x00,0x40,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff
+
+# GFX12: v_xor3_b32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x40,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_xor3_b32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x40,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_xor3_b32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x40,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_xor3_b32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x40,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_xor3_b32_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x40,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_xor3_b32_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x40,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_xor3_b32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x40,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_xor3_b32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x40,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x40,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_xor3_b32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x00,0x40,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_xor3_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x40,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x40,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_xor_b16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_xor_b16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_xor_b16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_xor_b16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_xor_b16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_xor_b16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_xor_b16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_xor_b16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_xor_b16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_xor_b16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_xor_b16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_xor_b16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_xor_b16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_xor_b16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x64,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x64,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_add_nc_i16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_add_nc_i16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_add_nc_i16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_add_nc_i16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_add_nc_i16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_add_nc_i16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_add_nc_i16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_add_nc_i16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_add_nc_i16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_add_nc_i16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_add_nc_i16_e64_dpp v5, v1, v2 op_sel:[1,1,1] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x58,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x58,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_add_nc_i16_e64_dpp v5, v1, v2 op_sel:[1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x08,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x08,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_add_nc_i16_e64_dpp v5, v1, v2 op_sel:[0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x10,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x10,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_add_nc_i16_e64_dpp v255, v255, v255 op_sel:[0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0xc0,0x0d,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0xc0,0x0d,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_add_nc_u16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_add_nc_u16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_add_nc_u16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_add_nc_u16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_add_nc_u16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_add_nc_u16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_add_nc_u16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_add_nc_u16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_add_nc_u16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_add_nc_u16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_add_nc_u16_e64_dpp v5, v1, v2 op_sel:[1,1,1] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x58,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x58,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_add_nc_u16_e64_dpp v5, v1, v2 op_sel:[1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x08,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x08,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_add_nc_u16_e64_dpp v5, v1, v2 op_sel:[0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x10,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x10,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_add_nc_u16_e64_dpp v255, v255, v255 op_sel:[0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0xc0,0x03,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0xc0,0x03,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_i16_f16_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x12,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x05,0x01,0x12,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_pk_norm_i16_f16_e64_dpp v5, -v1, |v2| op_sel:[1,0,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x0a,0x12,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x05,0x0a,0x12,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_pk_norm_i16_f16_e64_dpp v255, -|v255|, -|v255| op_sel:[0,1,0] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x13,0x12,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0xff,0x13,0x12,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_pk_norm_u16_f16_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x13,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x05,0x01,0x13,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_pk_norm_u16_f16_e64_dpp v5, -v1, |v2| op_sel:[1,0,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x0a,0x13,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x05,0x0a,0x13,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_pk_norm_u16_f16_e64_dpp v255, -|v255|, -|v255| op_sel:[0,1,0] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x13,0x13,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0xff,0x13,0x13,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_div_fixup_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x54,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x54,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_div_fixup_f16_e64_dpp v5, v1, v2, v255 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x54,0xd6,0xfa,0x04,0xfe,0x07,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x54,0xd6,0xfa,0x04,0xfe,0x07,0x01,0xe4,0x00,0xff
+
+# GFX12: v_div_fixup_f16_e64_dpp v5, v1, v2, s3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x54,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x54,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_div_fixup_f16_e64_dpp v5, v1, v2, s105 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x54,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x41,0x01,0xff]
+0x05,0x00,0x54,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x41,0x01,0xff
+
+# GFX12: v_div_fixup_f16_e64_dpp v5, v1, v2, ttmp15 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x54,0xd6,0xfa,0x04,0xee,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x54,0xd6,0xfa,0x04,0xee,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_div_fixup_f16_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x54,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x54,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_div_fixup_f16_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x54,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x54,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_div_fixup_f16_e64_dpp v5, |v1|, v2, -m0 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x01,0x54,0xd6,0xfa,0x04,0xf6,0x81,0x01,0x1f,0x01,0xff]
+0x05,0x01,0x54,0xd6,0xfa,0x04,0xf6,0x81,0x01,0x1f,0x01,0xff
+
+# GFX12: v_div_fixup_f16_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x02,0x54,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+0x05,0x02,0x54,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff
+
+# GFX12: v_div_fixup_f16_e64_dpp v5, -v1, v2, |exec_lo| op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x7c,0x54,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+0x05,0x7c,0x54,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff
+
+# GFX12: v_div_fixup_f16_e64_dpp v5, -|v1|, -|v2|, null op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0b,0x54,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+0x05,0x0b,0x54,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff
+
+# GFX12: v_div_fixup_f16_e64_dpp v5, -|v1|, v2, -|-1| op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x15,0x54,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01]
+0x05,0x15,0x54,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01
+
+# GFX12: v_div_fixup_f16_e64_dpp v5, v1, -|v2|, -|0.5| op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x26,0x54,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x01,0x13]
+0x05,0x26,0x54,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x01,0x13
+
+# GFX12: v_div_fixup_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0xc7,0x54,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30]
+0xff,0xc7,0x54,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_fma_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x48,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x48,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_fma_f16_e64_dpp v5, v1, v2, v255 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x48,0xd6,0xfa,0x04,0xfe,0x07,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x48,0xd6,0xfa,0x04,0xfe,0x07,0x01,0xe4,0x00,0xff
+
+# GFX12: v_fma_f16_e64_dpp v5, v1, v2, s3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x48,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x48,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_fma_f16_e64_dpp v5, v1, v2, s105 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x48,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x41,0x01,0xff]
+0x05,0x00,0x48,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x41,0x01,0xff
+
+# GFX12: v_fma_f16_e64_dpp v5, v1, v2, ttmp15 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x48,0xd6,0xfa,0x04,0xee,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x48,0xd6,0xfa,0x04,0xee,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_fma_f16_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x48,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x48,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_fma_f16_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x48,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x48,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_fma_f16_e64_dpp v5, |v1|, v2, -m0 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x01,0x48,0xd6,0xfa,0x04,0xf6,0x81,0x01,0x1f,0x01,0xff]
+0x05,0x01,0x48,0xd6,0xfa,0x04,0xf6,0x81,0x01,0x1f,0x01,0xff
+
+# GFX12: v_fma_f16_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x02,0x48,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+0x05,0x02,0x48,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff
+
+# GFX12: v_fma_f16_e64_dpp v5, -v1, v2, |exec_lo| op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x7c,0x48,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+0x05,0x7c,0x48,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff
+
+# GFX12: v_fma_f16_e64_dpp v5, -|v1|, -|v2|, null op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0b,0x48,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+0x05,0x0b,0x48,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff
+
+# GFX12: v_fma_f16_e64_dpp v5, -|v1|, v2, -|-1| op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x15,0x48,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01]
+0x05,0x15,0x48,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01
+
+# GFX12: v_fma_f16_e64_dpp v5, v1, -|v2|, -|0.5| op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x26,0x48,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x01,0x13]
+0x05,0x26,0x48,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x01,0x13
+
+# GFX12: v_fma_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0xc7,0x48,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30]
+0xff,0xc7,0x48,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_mad_i16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x53,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x53,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_mad_i16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x53,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x53,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_mad_i16_e64_dpp v5, v1, v2, v255 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff]
+0x05,0x00,0x53,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff
+
+# GFX12: v_mad_i16_e64_dpp v5, v1, v2, s3 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x53,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x53,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_mad_i16_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x53,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_mad_i16_e64_dpp v5, v1, v2, ttmp15 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xee,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x53,0xd6,0xfa,0x04,0xee,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_mad_i16_e64_dpp v5, v1, v2, vcc_hi row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x53,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_mad_i16_e64_dpp v5, v1, v2, vcc_lo row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x53,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_mad_i16_e64_dpp v5, v1, v2, m0 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xf6,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x53,0xd6,0xfa,0x04,0xf6,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_mad_i16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x78,0x53,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x78,0x53,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_mad_i16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x08,0x53,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
+0x05,0x08,0x53,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_mad_i16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x10,0x53,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
+0x05,0x10,0x53,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01
+
+# GFX12: v_mad_i16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x20,0x53,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13]
+0x05,0x20,0x53,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_mad_i16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0xc0,0x53,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0xc0,0x53,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_mad_i32_i16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x5a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_mad_i32_i16_e64_dpp v5, v1, v2, v255 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xfe,0x07,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x5a,0xd6,0xfa,0x04,0xfe,0x07,0x01,0xe4,0x00,0xff
+
+# GFX12: v_mad_i32_i16_e64_dpp v5, v1, v2, s3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x5a,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_mad_i32_i16_e64_dpp v5, v1, v2, s105 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x41,0x01,0xff]
+0x05,0x00,0x5a,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x41,0x01,0xff
+
+# GFX12: v_mad_i32_i16_e64_dpp v5, v1, v2, ttmp15 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xee,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x5a,0xd6,0xfa,0x04,0xee,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_mad_i32_i16_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x5a,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_mad_i32_i16_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x5a,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_mad_i32_i16_e64_dpp v5, v1, v2, m0 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xf6,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x5a,0xd6,0xfa,0x04,0xf6,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_mad_i32_i16_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x5a,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_mad_i32_i16_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x5a,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_mad_i32_i16_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x5a,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_mad_i32_i16_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x5a,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_mad_i32_i16_e64_dpp v5, v1, v2, 0.5 op_sel:[1,0,0,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x08,0x5a,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x08,0x5a,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_mad_i32_i16_e64_dpp v255, v255, v255, src_scc op_sel:[0,1,0,0] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x90,0x5a,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x90,0x5a,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_mad_u16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x41,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x41,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_mad_u16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x41,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x41,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_mad_u16_e64_dpp v5, v1, v2, v255 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff]
+0x05,0x00,0x41,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff
+
+# GFX12: v_mad_u16_e64_dpp v5, v1, v2, s3 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x41,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x41,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_mad_u16_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x41,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_mad_u16_e64_dpp v5, v1, v2, ttmp15 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xee,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x41,0xd6,0xfa,0x04,0xee,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_mad_u16_e64_dpp v5, v1, v2, vcc_hi row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x41,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_mad_u16_e64_dpp v5, v1, v2, vcc_lo row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x41,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_mad_u16_e64_dpp v5, v1, v2, m0 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xf6,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x41,0xd6,0xfa,0x04,0xf6,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_mad_u16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x78,0x41,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x78,0x41,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_mad_u16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x08,0x41,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
+0x05,0x08,0x41,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_mad_u16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x10,0x41,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
+0x05,0x10,0x41,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01
+
+# GFX12: v_mad_u16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x20,0x41,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13]
+0x05,0x20,0x41,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_mad_u16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0xc0,0x41,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0xc0,0x41,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_mad_u32_u16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x59,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x59,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_mad_u32_u16_e64_dpp v5, v1, v2, v255 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xfe,0x07,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x59,0xd6,0xfa,0x04,0xfe,0x07,0x01,0xe4,0x00,0xff
+
+# GFX12: v_mad_u32_u16_e64_dpp v5, v1, v2, s3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x59,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x59,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_mad_u32_u16_e64_dpp v5, v1, v2, s105 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x41,0x01,0xff]
+0x05,0x00,0x59,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x41,0x01,0xff
+
+# GFX12: v_mad_u32_u16_e64_dpp v5, v1, v2, ttmp15 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xee,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x59,0xd6,0xfa,0x04,0xee,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_mad_u32_u16_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x59,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_mad_u32_u16_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x59,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_mad_u32_u16_e64_dpp v5, v1, v2, m0 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xf6,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x59,0xd6,0xfa,0x04,0xf6,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_mad_u32_u16_e64_dpp v5, v1, v2, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x59,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_mad_u32_u16_e64_dpp v5, v1, v2, exec_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x59,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_mad_u32_u16_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x59,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_mad_u32_u16_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x59,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x59,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01
+
+# GFX12: v_mad_u32_u16_e64_dpp v5, v1, v2, 0.5 op_sel:[1,0,0,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x08,0x59,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
+0x05,0x08,0x59,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_mad_u32_u16_e64_dpp v255, v255, v255, src_scc op_sel:[0,1,0,0] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x90,0x59,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x90,0x59,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_max3_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x2c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_max3_num_f16_e64_dpp v5, v1, v2, v255 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2c,0xd6,0xfa,0x04,0xfe,0x07,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x2c,0xd6,0xfa,0x04,0xfe,0x07,0x01,0xe4,0x00,0xff
+
+# GFX12: v_max3_num_f16_e64_dpp v5, v1, v2, s3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2c,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x2c,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_max3_num_f16_e64_dpp v5, v1, v2, s105 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2c,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x41,0x01,0xff]
+0x05,0x00,0x2c,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x41,0x01,0xff
+
+# GFX12: v_max3_num_f16_e64_dpp v5, v1, v2, ttmp15 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2c,0xd6,0xfa,0x04,0xee,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x2c,0xd6,0xfa,0x04,0xee,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_max3_num_f16_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2c,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x2c,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_max3_num_f16_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2c,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x2c,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_max3_num_f16_e64_dpp v5, |v1|, v2, -m0 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x01,0x2c,0xd6,0xfa,0x04,0xf6,0x81,0x01,0x1f,0x01,0xff]
+0x05,0x01,0x2c,0xd6,0xfa,0x04,0xf6,0x81,0x01,0x1f,0x01,0xff
+
+# GFX12: v_max3_num_f16_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x02,0x2c,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+0x05,0x02,0x2c,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff
+
+# GFX12: v_max3_num_f16_e64_dpp v5, -v1, v2, |exec_lo| op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x7c,0x2c,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+0x05,0x7c,0x2c,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff
+
+# GFX12: v_max3_num_f16_e64_dpp v5, -|v1|, -|v2|, null op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0b,0x2c,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+0x05,0x0b,0x2c,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff
+
+# GFX12: v_max3_num_f16_e64_dpp v5, -|v1|, v2, -|-1| op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x15,0x2c,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01]
+0x05,0x15,0x2c,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01
+
+# GFX12: v_max3_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x26,0x2c,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x01,0x13]
+0x05,0x26,0x2c,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x01,0x13
+
+# GFX12: v_max3_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0xc7,0x2c,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30]
+0xff,0xc7,0x2c,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_max3_i16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x4d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_max3_i16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x4d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_max3_i16_e64_dpp v5, v1, v2, v255 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff]
+0x05,0x00,0x4d,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff
+
+# GFX12: v_max3_i16_e64_dpp v5, v1, v2, s3 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x4d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_max3_i16_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x4d,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_max3_i16_e64_dpp v5, v1, v2, ttmp15 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xee,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x4d,0xd6,0xfa,0x04,0xee,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_max3_i16_e64_dpp v5, v1, v2, vcc_hi row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x4d,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_max3_i16_e64_dpp v5, v1, v2, vcc_lo row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x4d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_max3_i16_e64_dpp v5, v1, v2, m0 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xf6,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x4d,0xd6,0xfa,0x04,0xf6,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_max3_i16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x78,0x4d,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x78,0x4d,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_max3_i16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x08,0x4d,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
+0x05,0x08,0x4d,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_max3_i16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x10,0x4d,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
+0x05,0x10,0x4d,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01
+
+# GFX12: v_max3_i16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x20,0x4d,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13]
+0x05,0x20,0x4d,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_max3_i16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x40,0x4d,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x40,0x4d,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_max3_u16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x4e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_max3_u16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x4e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_max3_u16_e64_dpp v5, v1, v2, v255 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff]
+0x05,0x00,0x4e,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff
+
+# GFX12: v_max3_u16_e64_dpp v5, v1, v2, s3 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x4e,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_max3_u16_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x4e,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_max3_u16_e64_dpp v5, v1, v2, ttmp15 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xee,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x4e,0xd6,0xfa,0x04,0xee,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_max3_u16_e64_dpp v5, v1, v2, vcc_hi row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x4e,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_max3_u16_e64_dpp v5, v1, v2, vcc_lo row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x4e,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_max3_u16_e64_dpp v5, v1, v2, m0 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xf6,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x4e,0xd6,0xfa,0x04,0xf6,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_max3_u16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x78,0x4e,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x78,0x4e,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_max3_u16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x08,0x4e,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
+0x05,0x08,0x4e,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_max3_u16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x10,0x4e,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
+0x05,0x10,0x4e,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01
+
+# GFX12: v_max3_u16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x20,0x4e,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13]
+0x05,0x20,0x4e,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_max3_u16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x40,0x4e,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x40,0x4e,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_med3_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x32,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x32,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_med3_num_f16_e64_dpp v5, v1, v2, v255 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x32,0xd6,0xfa,0x04,0xfe,0x07,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x32,0xd6,0xfa,0x04,0xfe,0x07,0x01,0xe4,0x00,0xff
+
+# GFX12: v_med3_num_f16_e64_dpp v5, v1, v2, s3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x32,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x32,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_med3_num_f16_e64_dpp v5, v1, v2, s105 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x32,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x41,0x01,0xff]
+0x05,0x00,0x32,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x41,0x01,0xff
+
+# GFX12: v_med3_num_f16_e64_dpp v5, v1, v2, ttmp15 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x32,0xd6,0xfa,0x04,0xee,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x32,0xd6,0xfa,0x04,0xee,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_med3_num_f16_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x32,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x32,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_med3_num_f16_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x32,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x32,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_med3_num_f16_e64_dpp v5, |v1|, v2, -m0 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x01,0x32,0xd6,0xfa,0x04,0xf6,0x81,0x01,0x1f,0x01,0xff]
+0x05,0x01,0x32,0xd6,0xfa,0x04,0xf6,0x81,0x01,0x1f,0x01,0xff
+
+# GFX12: v_med3_num_f16_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x02,0x32,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+0x05,0x02,0x32,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff
+
+# GFX12: v_med3_num_f16_e64_dpp v5, -v1, v2, |exec_lo| op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x7c,0x32,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+0x05,0x7c,0x32,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff
+
+# GFX12: v_med3_num_f16_e64_dpp v5, -|v1|, -|v2|, null op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0b,0x32,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+0x05,0x0b,0x32,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff
+
+# GFX12: v_med3_num_f16_e64_dpp v5, -|v1|, v2, -|-1| op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x15,0x32,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01]
+0x05,0x15,0x32,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01
+
+# GFX12: v_med3_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x26,0x32,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x01,0x13]
+0x05,0x26,0x32,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x01,0x13
+
+# GFX12: v_med3_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0xc7,0x32,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30]
+0xff,0xc7,0x32,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_med3_i16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x50,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x50,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_med3_i16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x50,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x50,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_med3_i16_e64_dpp v5, v1, v2, v255 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff]
+0x05,0x00,0x50,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff
+
+# GFX12: v_med3_i16_e64_dpp v5, v1, v2, s3 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x50,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x50,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_med3_i16_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x50,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_med3_i16_e64_dpp v5, v1, v2, ttmp15 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xee,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x50,0xd6,0xfa,0x04,0xee,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_med3_i16_e64_dpp v5, v1, v2, vcc_hi row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x50,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_med3_i16_e64_dpp v5, v1, v2, vcc_lo row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x50,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_med3_i16_e64_dpp v5, v1, v2, m0 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xf6,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x50,0xd6,0xfa,0x04,0xf6,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_med3_i16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x78,0x50,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x78,0x50,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_med3_i16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x08,0x50,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
+0x05,0x08,0x50,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_med3_i16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x10,0x50,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
+0x05,0x10,0x50,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01
+
+# GFX12: v_med3_i16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x20,0x50,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13]
+0x05,0x20,0x50,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_med3_i16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x40,0x50,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x40,0x50,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_med3_u16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x51,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x51,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_med3_u16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x51,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x51,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_med3_u16_e64_dpp v5, v1, v2, v255 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff]
+0x05,0x00,0x51,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff
+
+# GFX12: v_med3_u16_e64_dpp v5, v1, v2, s3 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x51,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x51,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_med3_u16_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x51,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_med3_u16_e64_dpp v5, v1, v2, ttmp15 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xee,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x51,0xd6,0xfa,0x04,0xee,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_med3_u16_e64_dpp v5, v1, v2, vcc_hi row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x51,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_med3_u16_e64_dpp v5, v1, v2, vcc_lo row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x51,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_med3_u16_e64_dpp v5, v1, v2, m0 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xf6,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x51,0xd6,0xfa,0x04,0xf6,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_med3_u16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x78,0x51,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x78,0x51,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_med3_u16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x08,0x51,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
+0x05,0x08,0x51,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_med3_u16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x10,0x51,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
+0x05,0x10,0x51,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01
+
+# GFX12: v_med3_u16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x20,0x51,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13]
+0x05,0x20,0x51,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_med3_u16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x40,0x51,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x40,0x51,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_min3_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x2b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_min3_num_f16_e64_dpp v5, v1, v2, v255 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2b,0xd6,0xfa,0x04,0xfe,0x07,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x2b,0xd6,0xfa,0x04,0xfe,0x07,0x01,0xe4,0x00,0xff
+
+# GFX12: v_min3_num_f16_e64_dpp v5, v1, v2, s3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2b,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x2b,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_min3_num_f16_e64_dpp v5, v1, v2, s105 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2b,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x41,0x01,0xff]
+0x05,0x00,0x2b,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x41,0x01,0xff
+
+# GFX12: v_min3_num_f16_e64_dpp v5, v1, v2, ttmp15 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2b,0xd6,0xfa,0x04,0xee,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x2b,0xd6,0xfa,0x04,0xee,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_min3_num_f16_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2b,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x2b,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_min3_num_f16_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2b,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x2b,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_min3_num_f16_e64_dpp v5, |v1|, v2, -m0 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x01,0x2b,0xd6,0xfa,0x04,0xf6,0x81,0x01,0x1f,0x01,0xff]
+0x05,0x01,0x2b,0xd6,0xfa,0x04,0xf6,0x81,0x01,0x1f,0x01,0xff
+
+# GFX12: v_min3_num_f16_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x02,0x2b,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
+0x05,0x02,0x2b,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff
+
+# GFX12: v_min3_num_f16_e64_dpp v5, -v1, v2, |exec_lo| op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x7c,0x2b,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
+0x05,0x7c,0x2b,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff
+
+# GFX12: v_min3_num_f16_e64_dpp v5, -|v1|, -|v2|, null op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0b,0x2b,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
+0x05,0x0b,0x2b,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff
+
+# GFX12: v_min3_num_f16_e64_dpp v5, -|v1|, v2, -|-1| op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x15,0x2b,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01]
+0x05,0x15,0x2b,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01
+
+# GFX12: v_min3_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x26,0x2b,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x01,0x13]
+0x05,0x26,0x2b,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x01,0x13
+
+# GFX12: v_min3_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0xc7,0x2b,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30]
+0xff,0xc7,0x2b,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_min3_i16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x4a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_min3_i16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x4a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_min3_i16_e64_dpp v5, v1, v2, v255 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff]
+0x05,0x00,0x4a,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff
+
+# GFX12: v_min3_i16_e64_dpp v5, v1, v2, s3 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x4a,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_min3_i16_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x4a,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_min3_i16_e64_dpp v5, v1, v2, ttmp15 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xee,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x4a,0xd6,0xfa,0x04,0xee,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_min3_i16_e64_dpp v5, v1, v2, vcc_hi row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x4a,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_min3_i16_e64_dpp v5, v1, v2, vcc_lo row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x4a,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_min3_i16_e64_dpp v5, v1, v2, m0 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xf6,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x4a,0xd6,0xfa,0x04,0xf6,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_min3_i16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x78,0x4a,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x78,0x4a,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_min3_i16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x08,0x4a,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
+0x05,0x08,0x4a,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_min3_i16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x10,0x4a,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
+0x05,0x10,0x4a,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01
+
+# GFX12: v_min3_i16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x20,0x4a,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13]
+0x05,0x20,0x4a,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_min3_i16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x40,0x4a,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x40,0x4a,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_min3_u16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x4b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
+
+# GFX12: v_min3_u16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x4b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
+
+# GFX12: v_min3_u16_e64_dpp v5, v1, v2, v255 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff]
+0x05,0x00,0x4b,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff
+
+# GFX12: v_min3_u16_e64_dpp v5, v1, v2, s3 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x4b,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_min3_u16_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+0x05,0x00,0x4b,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff
+
+# GFX12: v_min3_u16_e64_dpp v5, v1, v2, ttmp15 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xee,0x01,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x4b,0xd6,0xfa,0x04,0xee,0x01,0x01,0x0f,0x01,0xff
+
+# GFX12: v_min3_u16_e64_dpp v5, v1, v2, vcc_hi row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
+0x05,0x00,0x4b,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff
+
+# GFX12: v_min3_u16_e64_dpp v5, v1, v2, vcc_lo row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x4b,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff
+
+# GFX12: v_min3_u16_e64_dpp v5, v1, v2, m0 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xf6,0x01,0x01,0x21,0x01,0xff]
+0x05,0x00,0x4b,0xd6,0xfa,0x04,0xf6,0x01,0x01,0x21,0x01,0xff
+
+# GFX12: v_min3_u16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x78,0x4b,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
+0x05,0x78,0x4b,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff
+
+# GFX12: v_min3_u16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x08,0x4b,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
+0x05,0x08,0x4b,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff
+
+# GFX12: v_min3_u16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x10,0x4b,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
+0x05,0x10,0x4b,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01
+
+# GFX12: v_min3_u16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x20,0x4b,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13]
+0x05,0x20,0x4b,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13
+
+# GFX12: v_min3_u16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x40,0x4b,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0xff,0x40,0x4b,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_pack_b32_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_pack_b32_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_pack_b32_f16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_pack_b32_f16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_pack_b32_f16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_pack_b32_f16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_pack_b32_f16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_pack_b32_f16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_pack_b32_f16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_pack_b32_f16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_pack_b32_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_pack_b32_f16_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x11,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x05,0x01,0x11,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_pack_b32_f16_e64_dpp v5, -v1, |v2| op_sel:[1,0,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x0a,0x11,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x05,0x0a,0x11,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_pack_b32_f16_e64_dpp v255, -|v255|, -|v255| op_sel:[0,1,0] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x13,0x11,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0xff,0x13,0x11,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_sub_nc_i16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_sub_nc_i16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_sub_nc_i16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_sub_nc_i16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_sub_nc_i16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_sub_nc_i16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_sub_nc_i16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_sub_nc_i16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_sub_nc_i16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_sub_nc_i16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_sub_nc_i16_e64_dpp v5, v1, v2 op_sel:[1,1,1] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x58,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x58,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_sub_nc_i16_e64_dpp v5, v1, v2 op_sel:[1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x08,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x08,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_sub_nc_i16_e64_dpp v5, v1, v2 op_sel:[0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x10,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x10,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_sub_nc_i16_e64_dpp v255, v255, v255 op_sel:[0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0xc0,0x0e,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0xc0,0x0e,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_sub_nc_u16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_sub_nc_u16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_sub_nc_u16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_sub_nc_u16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_sub_nc_u16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_sub_nc_u16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_sub_nc_u16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_sub_nc_u16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_sub_nc_u16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_sub_nc_u16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_sub_nc_u16_e64_dpp v5, v1, v2 op_sel:[1,1,1] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x58,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x58,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_sub_nc_u16_e64_dpp v5, v1, v2 op_sel:[1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x08,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x08,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_sub_nc_u16_e64_dpp v5, v1, v2 op_sel:[0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x10,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x10,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_sub_nc_u16_e64_dpp v255, v255, v255 op_sel:[0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0xc0,0x04,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0xc0,0x04,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_dot2_f16_f16_e64_dpp v0, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0x00,0x00,0x66,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x04,0x00]
+0x00,0x00,0x66,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x04,0x00
+
+# op_sel[1:0] are ignored
+# GFX12: v_dot2_f16_f16_e64_dpp v0, v1, v2, v3 op_sel:[0,0,1,1] quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0x00,0x60,0x66,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x04,0x00]
+0x00,0x78,0x66,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x04,0x00
+
+# GFX12: v_dot2_f16_f16_e64_dpp v0, v1, v2, v3 op_sel:[0,0,1,1] quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0x00,0x60,0x66,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x04,0x00]
+0x00,0x60,0x66,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x04,0x00
+
+# GFX12: v_dot2_f16_f16_e64_dpp v0, |v1|, -v2, -|s3| op_sel:[0,0,1,1] quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0x00,0x65,0x66,0xd6,0xfa,0x04,0x0e,0xc0,0x01,0xe4,0x04,0x00]
+0x00,0x65,0x66,0xd6,0xfa,0x04,0x0e,0xc0,0x01,0xe4,0x04,0x00
+
+# GFX12: v_dot2_bf16_bf16_e64_dpp v0, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0x00,0x00,0x67,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x04,0x00]
+0x00,0x00,0x67,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x04,0x00
+
+# op_sel[1:0] are ignored
+# GFX12: v_dot2_bf16_bf16_e64_dpp v0, v1, v2, v3 op_sel:[0,0,1,1] quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0x00,0x60,0x67,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x04,0x00]
+0x00,0x78,0x67,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x04,0x00
+
+# GFX12: v_dot2_bf16_bf16_e64_dpp v0, v1, v2, v3 op_sel:[0,0,1,1] quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0x00,0x60,0x67,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x04,0x00]
+0x00,0x60,0x67,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x04,0x00
+
+# GFX12: v_dot2_bf16_bf16_e64_dpp v0, |v1|, -v2, -|s3| op_sel:[0,0,1,1] quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0x00,0x65,0x67,0xd6,0xfa,0x04,0x0e,0xc0,0x01,0xe4,0x04,0x00]
+0x00,0x65,0x67,0xd6,0xfa,0x04,0x0e,0xc0,0x01,0xe4,0x04,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt
new file mode 100644
index 000000000000..904ec7c1347f
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt
@@ -0,0 +1,2631 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32 %s
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64 %s
+
+# GFX12: v_add3_u32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x55,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x55,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_add3_u32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x55,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x55,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_add3_u32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x55,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x55,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_add3_u32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x55,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x55,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_add3_u32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x55,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x55,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_add3_u32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x55,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x55,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_add3_u32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x55,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x55,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_add3_u32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x55,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x55,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_add3_u32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x55,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x55,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_add3_u32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x55,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x55,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_add3_u32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x55,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x55,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_add3_u32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x55,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x00,0x55,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# W32: v_add_co_u32_e64_dpp v5, s12, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x0c,0x00,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x0c,0x00,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x0c,0x00,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_add_co_u32_e64_dpp v5, s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x68,0x00,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_add_co_u32_e64_dpp v5, s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x68,0x00,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x68,0x00,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_add_co_u32_e64_dpp v5, vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x6a,0x00,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_add_co_u32_e64_dpp v5, vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x6a,0x00,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x6a,0x00,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_add_co_u32_e64_dpp v5, ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x7a,0x00,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_add_co_u32_e64_dpp v5, ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x7a,0x00,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x7a,0x00,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_co_u32_e64_dpp v255, null, v255, v255 clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0xfc,0x00,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0xfc,0x00,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_add_lshl_u32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x47,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x47,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_lshl_u32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x47,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x47,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_lshl_u32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x47,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x47,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_lshl_u32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x47,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x47,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_lshl_u32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x47,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x47,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_lshl_u32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x47,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x47,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_lshl_u32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x47,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x47,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_lshl_u32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x47,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x47,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_lshl_u32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x47,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x47,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_lshl_u32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x47,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x47,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_lshl_u32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x47,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x47,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_lshl_u32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x47,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x00,0x47,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_add_nc_i32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x26,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x26,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_nc_i32_e64_dpp v255, v255, v255 clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x80,0x26,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x80,0x26,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x16,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x16,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x16,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x16,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x16,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x16,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x16,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x16,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x16,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_alignbit_b32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x16,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x00,0x16,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_alignbyte_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x17,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x17,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_alignbyte_b32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x17,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x17,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_alignbyte_b32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x17,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x17,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_alignbyte_b32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x17,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x17,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_alignbyte_b32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x17,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x17,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_alignbyte_b32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x17,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x17,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_alignbyte_b32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x17,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x17,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_alignbyte_b32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x17,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x17,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_alignbyte_b32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x17,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x17,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_alignbyte_b32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x17,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x17,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_alignbyte_b32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x17,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x00,0x17,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_and_b16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x62,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x62,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_and_b16_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x62,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x62,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_and_or_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x57,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x57,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_and_or_b32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x57,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x57,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_and_or_b32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x57,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x57,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_and_or_b32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x57,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x57,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_and_or_b32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x57,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x57,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_and_or_b32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x57,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x57,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_and_or_b32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x57,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x57,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_and_or_b32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x57,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x57,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_and_or_b32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x57,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x57,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_and_or_b32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x57,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x57,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_and_or_b32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x57,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x57,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_and_or_b32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x57,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x00,0x57,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_ashrrev_i16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x3a,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x3a,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_ashrrev_i16_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x3a,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x3a,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_bcnt_u32_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1e,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1e,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_bcnt_u32_b32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x1e,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x1e,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_bfe_i32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x11,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x11,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfe_i32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x11,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x11,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfe_i32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x11,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x11,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfe_i32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x11,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x11,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfe_i32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x11,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x11,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfe_i32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x11,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x11,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfe_i32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x11,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x11,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfe_i32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x11,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x11,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfe_i32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x11,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x11,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfe_i32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x11,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x11,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfe_i32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x11,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x11,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfe_i32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x11,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x00,0x11,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_bfe_u32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x10,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x10,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfe_u32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x10,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x10,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfe_u32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x10,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x10,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfe_u32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x10,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x10,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfe_u32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x10,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x10,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfe_u32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x10,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x10,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfe_u32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x10,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x10,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfe_u32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x10,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x10,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfe_u32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x10,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x10,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfe_u32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x10,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x10,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfe_u32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x10,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x10,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfe_u32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x10,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x00,0x10,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_bfi_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x12,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x12,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfi_b32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x12,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x12,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfi_b32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x12,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x12,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfi_b32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x12,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x12,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfi_b32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x12,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x12,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfi_b32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x12,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x12,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfi_b32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x12,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x12,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfi_b32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x12,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x12,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfi_b32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x12,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x12,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfi_b32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x12,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x12,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfi_b32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x12,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x12,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfi_b32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x12,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x00,0x12,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_bfm_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1d,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1d,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfm_b32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x1d,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x1d,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_cndmask_b16_e64_dpp v5, v1, v2, s6 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x5d,0xd6,0xe9,0x04,0x1a,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x5d,0xd6,0xe9,0x04,0x1a,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x5d,0xd6,0xe9,0x04,0x1a,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cndmask_b16_e64_dpp v5, v1, v2, s104 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x5d,0xd6,0xe9,0x04,0xa2,0x01,0x01,0x77,0x39,0x05]
+# W64: v_cndmask_b16_e64_dpp v5, v1, v2, s[104:105] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x5d,0xd6,0xe9,0x04,0xa2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x5d,0xd6,0xe9,0x04,0xa2,0x01,0x01,0x77,0x39,0x05
+
+# W32: v_cndmask_b16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x5d,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+# W64: v_cndmask_b16_e64_dpp v5, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x5d,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x5d,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# W32: v_cndmask_b16_e64_dpp v5, v1, v2, ttmp14 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x5d,0xd6,0xe9,0x04,0xea,0x01,0x01,0x77,0x39,0x05]
+# W64: v_cndmask_b16_e64_dpp v5, v1, v2, ttmp[14:15] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x5d,0xd6,0xe9,0x04,0xea,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x5d,0xd6,0xe9,0x04,0xea,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_cndmask_b16_e64_dpp v255, v255, v255, null dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x5d,0xd6,0xea,0xfe,0xf3,0x01,0xff,0x00,0x00,0x00]
+0xff,0x00,0x5d,0xd6,0xea,0xfe,0xf3,0x01,0xff,0x00,0x00,0x00
+
+# GFX12: v_cubeid_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0c,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0c,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubeid_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0c,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0c,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubeid_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0c,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0c,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubeid_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0c,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0c,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubeid_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0c,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0c,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubeid_f32_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x0c,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+0x05,0x01,0x0c,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubeid_f32_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x0c,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+0x05,0x02,0x0c,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubeid_f32_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x04,0x0c,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+0x05,0x04,0x0c,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubeid_f32_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x03,0x0c,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+0x05,0x03,0x0c,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubeid_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x05,0x0c,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05]
+0x05,0x05,0x0c,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubeid_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x06,0x0c,0xd6,0xe9,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05]
+0x05,0x06,0x0c,0xd6,0xe9,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubeid_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x87,0x0c,0xd6,0xea,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00]
+0xff,0x87,0x0c,0xd6,0xea,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00
+
+# GFX12: v_cubema_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0f,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0f,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubema_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0f,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0f,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubema_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0f,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0f,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubema_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0f,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0f,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubema_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0f,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0f,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubema_f32_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x0f,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+0x05,0x01,0x0f,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubema_f32_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x0f,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+0x05,0x02,0x0f,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubema_f32_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x04,0x0f,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+0x05,0x04,0x0f,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubema_f32_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x03,0x0f,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+0x05,0x03,0x0f,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubema_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x05,0x0f,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05]
+0x05,0x05,0x0f,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubema_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x06,0x0f,0xd6,0xe9,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05]
+0x05,0x06,0x0f,0xd6,0xe9,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubema_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x87,0x0f,0xd6,0xea,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00]
+0xff,0x87,0x0f,0xd6,0xea,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00
+
+# GFX12: v_cubesc_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0d,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0d,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubesc_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0d,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0d,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubesc_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0d,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0d,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubesc_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0d,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0d,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubesc_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0d,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0d,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubesc_f32_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x0d,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+0x05,0x01,0x0d,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubesc_f32_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x0d,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+0x05,0x02,0x0d,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubesc_f32_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x04,0x0d,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+0x05,0x04,0x0d,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubesc_f32_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x03,0x0d,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+0x05,0x03,0x0d,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubesc_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x05,0x0d,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05]
+0x05,0x05,0x0d,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubesc_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x06,0x0d,0xd6,0xe9,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05]
+0x05,0x06,0x0d,0xd6,0xe9,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubesc_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x87,0x0d,0xd6,0xea,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00]
+0xff,0x87,0x0d,0xd6,0xea,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00
+
+# GFX12: v_cubetc_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0e,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0e,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubetc_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0e,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0e,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubetc_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0e,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0e,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubetc_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0e,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0e,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubetc_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0e,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0e,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubetc_f32_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x0e,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+0x05,0x01,0x0e,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubetc_f32_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x0e,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+0x05,0x02,0x0e,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubetc_f32_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x04,0x0e,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+0x05,0x04,0x0e,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubetc_f32_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x03,0x0e,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+0x05,0x03,0x0e,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubetc_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x05,0x0e,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05]
+0x05,0x05,0x0e,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubetc_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x06,0x0e,0xd6,0xe9,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05]
+0x05,0x06,0x0e,0xd6,0xe9,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05
+
+# GFX12: v_cubetc_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x87,0x0e,0xd6,0xea,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00]
+0xff,0x87,0x0e,0xd6,0xea,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x06,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x06,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_i16_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x06,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x05,0x01,0x06,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_i16_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x06,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x05,0x02,0x06,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_i16_f32_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x03,0x06,0xd7,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0xff,0x03,0x06,0xd7,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x24,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x24,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_i16_i32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x24,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x24,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x07,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x07,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_u16_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x07,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x05,0x01,0x07,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_u16_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x07,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x05,0x02,0x07,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_u16_f32_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x03,0x07,0xd7,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0xff,0x03,0x07,0xd7,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x23,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x23,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_u16_u32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x23,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x23,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x26,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x26,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x26,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x26,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x26,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x26,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x26,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x26,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x26,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x26,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x26,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x26,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x26,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x26,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x26,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x26,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x26,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x26,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x26,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x26,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x26,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x26,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_u8_f32_e64_dpp v255, -|v255|, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x01,0x26,0xd6,0xea,0xfe,0xf7,0x23,0xff,0x00,0x00,0x00]
+0xff,0x01,0x26,0xd6,0xea,0xfe,0xf7,0x23,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x21,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x21,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_norm_i16_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x21,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x05,0x01,0x21,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_norm_i16_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x21,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x05,0x02,0x21,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_norm_i16_f32_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x03,0x21,0xd7,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0xff,0x03,0x21,0xd7,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x22,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x22,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_norm_u16_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x22,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x05,0x01,0x22,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_norm_u16_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x22,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x05,0x02,0x22,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_norm_u16_f32_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x03,0x22,0xd7,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0xff,0x03,0x22,0xd7,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_fma_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x13,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x13,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_fma_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x13,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x13,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_fma_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x13,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x13,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_fma_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x13,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x13,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_fma_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x13,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x13,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_fma_f32_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x13,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+0x05,0x01,0x13,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05
+
+# GFX12: v_fma_f32_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x13,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+0x05,0x02,0x13,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05
+
+# GFX12: v_fma_f32_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x04,0x13,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+0x05,0x04,0x13,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05
+
+# GFX12: v_fma_f32_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x03,0x13,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+0x05,0x03,0x13,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05
+
+# GFX12: v_fma_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x05,0x13,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05]
+0x05,0x05,0x13,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05
+
+# GFX12: v_fma_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x06,0x13,0xd6,0xe9,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05]
+0x05,0x06,0x13,0xd6,0xe9,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05
+
+# GFX12: v_fma_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x87,0x13,0xd6,0xea,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00]
+0xff,0x87,0x13,0xd6,0xea,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00
+
+# GFX12: v_ldexp_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1c,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1c,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_ldexp_f32_e64_dpp v5, v1, v2 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1c,0xd7,0xe9,0x04,0x02,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1c,0xd7,0xe9,0x04,0x02,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_ldexp_f32_e64_dpp v5, v1, v2 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1c,0xd7,0xe9,0x04,0x02,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1c,0xd7,0xe9,0x04,0x02,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_ldexp_f32_e64_dpp v255, -|v255|, v255 clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0x1c,0xd7,0xea,0xfe,0x03,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0x1c,0xd7,0xea,0xfe,0x03,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_lerp_u8_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x15,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x15,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_lerp_u8_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x15,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x15,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_lerp_u8_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x15,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x15,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_lerp_u8_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x15,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x15,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_lerp_u8_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x15,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x15,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_lerp_u8_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x15,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x15,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_lerp_u8_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x15,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x15,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_lerp_u8_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x15,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x15,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_lerp_u8_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x15,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x15,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_lerp_u8_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x15,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x15,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_lerp_u8_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x15,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x15,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_lerp_u8_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x15,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x00,0x15,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_lshl_add_u32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x46,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x46,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_lshl_add_u32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x46,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x46,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_lshl_add_u32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x46,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x46,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_lshl_add_u32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x46,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x46,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_lshl_add_u32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x46,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x46,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_lshl_add_u32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x46,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x46,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_lshl_add_u32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x46,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x46,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_lshl_add_u32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x46,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x46,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_lshl_add_u32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x46,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x46,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_lshl_add_u32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x46,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x46,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_lshl_add_u32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x46,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x46,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_lshl_add_u32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x46,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x00,0x46,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_lshl_or_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x56,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x56,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_lshl_or_b32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x56,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x56,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_lshl_or_b32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x56,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x56,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_lshl_or_b32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x56,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x56,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_lshl_or_b32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x56,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x56,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_lshl_or_b32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x56,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x56,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_lshl_or_b32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x56,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x56,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_lshl_or_b32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x56,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x56,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_lshl_or_b32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x56,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x56,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_lshl_or_b32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x56,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x56,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_lshl_or_b32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x56,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x56,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_lshl_or_b32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x56,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x00,0x56,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_lshlrev_b16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x38,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x38,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_lshlrev_b16_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x38,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x38,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_lshrrev_b16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x39,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x39,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_lshrrev_b16_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x39,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x39,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_mad_i32_i24_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0a,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0a,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i32_i24_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0a,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0a,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i32_i24_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0a,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0a,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i32_i24_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0a,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0a,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i32_i24_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0a,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0a,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i32_i24_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0a,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0a,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i32_i24_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0a,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0a,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i32_i24_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0a,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0a,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i32_i24_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0a,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0a,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i32_i24_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0a,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0a,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i32_i24_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0a,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0a,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i32_i24_e64_dpp v255, v255, v255, src_scc clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x80,0x0a,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x80,0x0a,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_mad_u32_u24_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0b,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0b,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u32_u24_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0b,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0b,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u32_u24_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0b,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0b,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u32_u24_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0b,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0b,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u32_u24_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0b,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0b,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u32_u24_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0b,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0b,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u32_u24_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0b,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0b,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u32_u24_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0b,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0b,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u32_u24_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0b,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0b,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u32_u24_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0b,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0b,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u32_u24_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0b,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0b,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u32_u24_e64_dpp v255, v255, v255, src_scc clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x80,0x0b,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x80,0x0b,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_max3_num_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2a,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x2a,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_num_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2a,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x2a,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_num_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2a,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x2a,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_num_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2a,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x2a,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_num_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2a,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x2a,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_num_f32_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x2a,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+0x05,0x01,0x2a,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_num_f32_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x2a,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+0x05,0x02,0x2a,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_num_f32_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x04,0x2a,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+0x05,0x04,0x2a,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_num_f32_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x03,0x2a,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+0x05,0x03,0x2a,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_num_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x05,0x2a,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05]
+0x05,0x05,0x2a,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_num_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x06,0x2a,0xd6,0xe9,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05]
+0x05,0x06,0x2a,0xd6,0xe9,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_num_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x87,0x2a,0xd6,0xea,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00]
+0xff,0x87,0x2a,0xd6,0xea,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00
+
+# GFX12: v_max3_i32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1d,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1d,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_i32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1d,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1d,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_i32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1d,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1d,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_i32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1d,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1d,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_i32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1d,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1d,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_i32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1d,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1d,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_i32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1d,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1d,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_i32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1d,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1d,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_i32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1d,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1d,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_i32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1d,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1d,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_i32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1d,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1d,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_i32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x1d,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x00,0x1d,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_max3_u32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1e,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1e,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_u32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1e,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1e,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_u32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1e,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1e,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_u32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1e,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1e,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_u32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1e,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1e,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_u32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1e,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1e,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_u32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1e,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1e,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_u32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1e,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1e,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_u32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1e,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1e,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_u32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1e,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1e,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_u32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1e,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1e,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_u32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x1e,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x00,0x1e,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_max_i16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0a,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0a,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_max_i16_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x0a,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x0a,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_max_u16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x09,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x09,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_max_u16_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x09,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x09,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_maxmin_num_f16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6b,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x6b,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_num_f16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6b,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x6b,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_num_f16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6b,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x6b,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_num_f16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6b,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x6b,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_num_f16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6b,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x6b,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_num_f16_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x6b,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+0x05,0x01,0x6b,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_num_f16_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x6b,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+0x05,0x02,0x6b,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_num_f16_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x04,0x6b,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+0x05,0x04,0x6b,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_num_f16_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x03,0x6b,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+0x05,0x03,0x6b,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_num_f16_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x05,0x6b,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05]
+0x05,0x05,0x6b,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x06,0x6b,0xd6,0xe9,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05]
+0x05,0x06,0x6b,0xd6,0xe9,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x87,0x6b,0xd6,0xea,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00]
+0xff,0x87,0x6b,0xd6,0xea,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00
+
+# GFX12: v_maxmin_num_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x69,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x69,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_num_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x69,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x69,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_num_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x69,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x69,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_num_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x69,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x69,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_num_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x69,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x69,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_num_f32_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x69,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+0x05,0x01,0x69,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_num_f32_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x69,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+0x05,0x02,0x69,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_num_f32_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x04,0x69,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+0x05,0x04,0x69,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_num_f32_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x03,0x69,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+0x05,0x03,0x69,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_num_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x05,0x69,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05]
+0x05,0x05,0x69,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_num_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x06,0x69,0xd6,0xe9,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05]
+0x05,0x06,0x69,0xd6,0xe9,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_num_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x87,0x69,0xd6,0xea,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00]
+0xff,0x87,0x69,0xd6,0xea,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00
+
+# GFX12: v_maxmin_i32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x64,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x64,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_i32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x64,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x64,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_i32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x64,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x64,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_i32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x64,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x64,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_i32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x64,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x64,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_i32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x64,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x64,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_i32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x64,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x64,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_i32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x64,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x64,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_i32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x64,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x64,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_i32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x64,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x64,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_i32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x64,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x64,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_i32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x64,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x00,0x64,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_maxmin_u32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x62,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x62,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_u32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x62,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x62,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_u32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x62,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x62,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_u32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x62,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x62,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_u32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x62,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x62,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_u32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x62,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x62,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_u32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x62,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x62,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_u32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x62,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x62,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_u32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x62,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x62,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_u32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x62,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x62,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_u32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x62,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x62,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_maxmin_u32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x62,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x00,0x62,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x20,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x20,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_mbcnt_hi_u32_b32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x20,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x20,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1f,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1f,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_mbcnt_lo_u32_b32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x1f,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x1f,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_med3_num_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x31,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x31,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_num_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x31,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x31,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_num_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x31,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x31,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_num_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x31,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x31,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_num_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x31,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x31,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_num_f32_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x31,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+0x05,0x01,0x31,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_num_f32_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x31,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+0x05,0x02,0x31,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_num_f32_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x04,0x31,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+0x05,0x04,0x31,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_num_f32_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x03,0x31,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+0x05,0x03,0x31,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_num_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x05,0x31,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05]
+0x05,0x05,0x31,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_num_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x06,0x31,0xd6,0xe9,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05]
+0x05,0x06,0x31,0xd6,0xe9,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_num_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x87,0x31,0xd6,0xea,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00]
+0xff,0x87,0x31,0xd6,0xea,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00
+
+# GFX12: v_med3_i32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x20,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x20,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_i32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x20,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x20,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_i32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x20,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x20,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_i32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x20,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x20,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_i32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x20,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x20,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_i32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x20,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x20,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_i32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x20,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x20,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_i32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x20,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x20,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_i32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x20,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x20,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_i32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x20,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x20,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_i32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x20,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x20,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_i32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x20,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x00,0x20,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_med3_u32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x21,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x21,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_u32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x21,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x21,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_u32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x21,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x21,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_u32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x21,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x21,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_u32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x21,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x21,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_u32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x21,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x21,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_u32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x21,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x21,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_u32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x21,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x21,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_u32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x21,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x21,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_u32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x21,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x21,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_u32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x21,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x21,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_u32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x21,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x00,0x21,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_min3_num_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x29,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x29,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_num_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x29,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x29,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_num_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x29,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x29,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_num_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x29,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x29,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_num_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x29,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x29,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_num_f32_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x29,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+0x05,0x01,0x29,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_num_f32_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x29,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+0x05,0x02,0x29,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_num_f32_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x04,0x29,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+0x05,0x04,0x29,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_num_f32_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x03,0x29,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+0x05,0x03,0x29,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_num_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x05,0x29,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05]
+0x05,0x05,0x29,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_num_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x06,0x29,0xd6,0xe9,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05]
+0x05,0x06,0x29,0xd6,0xe9,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_num_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x87,0x29,0xd6,0xea,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00]
+0xff,0x87,0x29,0xd6,0xea,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00
+
+# GFX12: v_min3_i32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1a,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1a,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_i32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1a,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1a,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_i32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1a,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1a,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_i32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1a,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1a,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_i32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1a,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1a,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_i32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1a,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1a,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_i32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1a,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1a,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_i32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1a,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1a,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_i32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1a,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1a,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_i32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1a,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1a,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_i32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1a,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1a,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_i32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x1a,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x00,0x1a,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_min3_u32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1b,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1b,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_u32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1b,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1b,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_u32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1b,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1b,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_u32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1b,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1b,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_u32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1b,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1b,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_u32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1b,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1b,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_u32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1b,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1b,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_u32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1b,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1b,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_u32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1b,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1b,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_u32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1b,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1b,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_u32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1b,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1b,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_u32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x1b,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x00,0x1b,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_min_i16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0c,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0c,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_min_i16_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x0c,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x0c,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_min_u16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0b,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0b,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_min_u16_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x0b,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x0b,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_minmax_num_f16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6a,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x6a,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_num_f16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6a,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x6a,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_num_f16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6a,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x6a,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_num_f16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6a,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x6a,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_num_f16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6a,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x6a,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_num_f16_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x6a,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+0x05,0x01,0x6a,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_num_f16_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x6a,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+0x05,0x02,0x6a,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_num_f16_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x04,0x6a,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+0x05,0x04,0x6a,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_num_f16_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x03,0x6a,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+0x05,0x03,0x6a,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_num_f16_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x05,0x6a,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05]
+0x05,0x05,0x6a,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x06,0x6a,0xd6,0xe9,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05]
+0x05,0x06,0x6a,0xd6,0xe9,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x87,0x6a,0xd6,0xea,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00]
+0xff,0x87,0x6a,0xd6,0xea,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00
+
+# GFX12: v_minmax_num_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x68,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x68,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_num_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x68,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x68,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_num_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x68,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x68,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_num_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x68,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x68,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_num_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x68,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x68,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_num_f32_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x68,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+0x05,0x01,0x68,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_num_f32_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x68,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+0x05,0x02,0x68,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_num_f32_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x04,0x68,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+0x05,0x04,0x68,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_num_f32_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x03,0x68,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+0x05,0x03,0x68,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_num_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x05,0x68,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05]
+0x05,0x05,0x68,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_num_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x06,0x68,0xd6,0xe9,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05]
+0x05,0x06,0x68,0xd6,0xe9,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_num_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x87,0x68,0xd6,0xea,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00]
+0xff,0x87,0x68,0xd6,0xea,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00
+
+# GFX12: v_minmax_i32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x65,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x65,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_i32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x65,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x65,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_i32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x65,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x65,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_i32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x65,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x65,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_i32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x65,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x65,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_i32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x65,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x65,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_i32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x65,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x65,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_i32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x65,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x65,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_i32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x65,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x65,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_i32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x65,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x65,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_i32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x65,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x65,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_i32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x65,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x00,0x65,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_minmax_u32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x63,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x63,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_u32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x63,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x63,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_u32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x63,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x63,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_u32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x63,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x63,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_u32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x63,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x63,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_u32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x63,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x63,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_u32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x63,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x63,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_u32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x63,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x63,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_u32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x63,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x63,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_u32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x63,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x63,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_u32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x63,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x63,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_minmax_u32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x63,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x00,0x63,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_msad_u8_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x39,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x39,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_msad_u8_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x39,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x39,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_msad_u8_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x39,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x39,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_msad_u8_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x39,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x39,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_msad_u8_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x39,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x39,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_msad_u8_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x39,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x39,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_msad_u8_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x39,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x39,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_msad_u8_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x39,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x39,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_msad_u8_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x39,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x39,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_msad_u8_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x39,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x39,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_msad_u8_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x39,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x39,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_msad_u8_e64_dpp v255, v255, v255, src_scc clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x80,0x39,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x80,0x39,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_mul_lo_u16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x05,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x05,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_mul_lo_u16_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x05,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x05,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_mullit_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x18,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x18,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_mullit_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x18,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x18,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_mullit_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x18,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x18,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mullit_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x18,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x18,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mullit_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x18,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x18,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mullit_f32_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x18,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05]
+0x05,0x01,0x18,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05
+
+# GFX12: v_mullit_f32_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x18,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+0x05,0x02,0x18,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05
+
+# GFX12: v_mullit_f32_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x04,0x18,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+0x05,0x04,0x18,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05
+
+# GFX12: v_mullit_f32_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x03,0x18,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+0x05,0x03,0x18,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05
+
+# GFX12: v_mullit_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x05,0x18,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05]
+0x05,0x05,0x18,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05
+
+# GFX12: v_mullit_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x06,0x18,0xd6,0xe9,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05]
+0x05,0x06,0x18,0xd6,0xe9,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05
+
+# GFX12: v_mullit_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x87,0x18,0xd6,0xea,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00]
+0xff,0x87,0x18,0xd6,0xea,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00
+
+# GFX12: v_or3_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x58,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x58,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_or3_b32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x58,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x58,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_or3_b32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x58,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x58,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_or3_b32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x58,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x58,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_or3_b32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x58,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x58,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_or3_b32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x58,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x58,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_or3_b32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x58,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x58,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_or3_b32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x58,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x58,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_or3_b32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x58,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x58,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_or3_b32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x58,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x58,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_or3_b32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x58,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x58,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_or3_b32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x58,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x00,0x58,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_or_b16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x63,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x63,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_or_b16_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x63,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x63,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_perm_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x44,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x44,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_perm_b32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x44,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x44,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_perm_b32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x44,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x44,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_perm_b32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x44,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x44,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_perm_b32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x44,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x44,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_perm_b32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x44,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x44,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_perm_b32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x44,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x44,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_perm_b32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x44,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x44,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_perm_b32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x44,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x44,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_perm_b32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x44,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x44,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_perm_b32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x44,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x44,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_perm_b32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x44,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x00,0x44,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_sad_hi_u8_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x23,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x23,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_hi_u8_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x23,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x23,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_hi_u8_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x23,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x23,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_hi_u8_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x23,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x23,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_hi_u8_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x23,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x23,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_hi_u8_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x23,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x23,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_hi_u8_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x23,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x23,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_hi_u8_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x23,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x23,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_hi_u8_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x23,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x23,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_hi_u8_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x23,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x23,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_hi_u8_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x23,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x23,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_hi_u8_e64_dpp v255, v255, v255, src_scc clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x80,0x23,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x80,0x23,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_sad_u16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x24,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x24,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x24,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x24,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x24,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x24,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x24,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x24,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x24,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x24,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x24,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x24,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u16_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x24,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x24,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u16_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x24,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x24,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u16_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x24,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x24,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u16_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x24,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x24,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u16_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x24,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x24,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u16_e64_dpp v255, v255, v255, src_scc clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x80,0x24,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x80,0x24,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_sad_u32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x25,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x25,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x25,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x25,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x25,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x25,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x25,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x25,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x25,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x25,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x25,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x25,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x25,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x25,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x25,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x25,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x25,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x25,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x25,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x25,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x25,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x25,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u32_e64_dpp v255, v255, v255, src_scc clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x80,0x25,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x80,0x25,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_sad_u8_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x22,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x22,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u8_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x22,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x22,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u8_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x22,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x22,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u8_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x22,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x22,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u8_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x22,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x22,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u8_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x22,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x22,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u8_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x22,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x22,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u8_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x22,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x22,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u8_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x22,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x22,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u8_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x22,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x22,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u8_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x22,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x22,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_sad_u8_e64_dpp v255, v255, v255, src_scc clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x80,0x22,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x80,0x22,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# W32: v_sub_co_u32_e64_dpp v5, s12, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x0c,0x01,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x0c,0x01,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x0c,0x01,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_sub_co_u32_e64_dpp v5, s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x68,0x01,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_sub_co_u32_e64_dpp v5, s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x68,0x01,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x68,0x01,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_sub_co_u32_e64_dpp v5, vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x6a,0x01,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_sub_co_u32_e64_dpp v5, vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x6a,0x01,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x6a,0x01,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_sub_co_u32_e64_dpp v5, ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x7a,0x01,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_sub_co_u32_e64_dpp v5, ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x7a,0x01,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x7a,0x01,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_sub_co_u32_e64_dpp v255, null, v255, v255 clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0xfc,0x01,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0xfc,0x01,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_sub_nc_i32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x25,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x25,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_sub_nc_i32_e64_dpp v255, v255, v255 clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x80,0x25,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x80,0x25,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_subrev_co_u32_e64_dpp v5, s12, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x0c,0x02,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x0c,0x02,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x0c,0x02,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_subrev_co_u32_e64_dpp v5, s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x68,0x02,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_subrev_co_u32_e64_dpp v5, s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x68,0x02,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x68,0x02,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_subrev_co_u32_e64_dpp v5, vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x6a,0x02,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_subrev_co_u32_e64_dpp v5, vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x6a,0x02,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x6a,0x02,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_subrev_co_u32_e64_dpp v5, ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x7a,0x02,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_subrev_co_u32_e64_dpp v5, ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x7a,0x02,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x7a,0x02,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_subrev_co_u32_e64_dpp v255, null, v255, v255 clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0xfc,0x02,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0xfc,0x02,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_xad_u32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x45,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x45,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_xad_u32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x45,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x45,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_xad_u32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x45,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x45,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_xad_u32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x45,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x45,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_xad_u32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x45,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x45,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_xad_u32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x45,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x45,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_xad_u32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x45,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x45,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_xad_u32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x45,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x45,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_xad_u32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x45,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x45,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_xad_u32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x45,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x45,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_xad_u32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x45,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x45,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_xad_u32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x45,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x00,0x45,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_xor3_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x40,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x40,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_xor3_b32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x40,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x40,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_xor3_b32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x40,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x40,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_xor3_b32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x40,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x40,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_xor3_b32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x40,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x40,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_xor3_b32_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x40,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x40,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_xor3_b32_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x40,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x40,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_xor3_b32_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x40,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x40,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_xor3_b32_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x40,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x40,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_xor3_b32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x40,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x40,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_xor3_b32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x40,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x40,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_xor3_b32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x40,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x00,0x40,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_xor_b16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x64,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x64,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_xor_b16_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x64,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x64,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_add_nc_i16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0d,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0d,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_nc_i16_e64_dpp v5, v1, v2 op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x58,0x0d,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x58,0x0d,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_nc_i16_e64_dpp v5, v1, v2 op_sel:[1,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x08,0x0d,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x08,0x0d,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_nc_i16_e64_dpp v5, v1, v2 op_sel:[0,1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x10,0x0d,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x10,0x0d,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_nc_i16_e64_dpp v255, v255, v255 op_sel:[0,0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0xc0,0x0d,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0xc0,0x0d,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_add_nc_u16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x03,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x03,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_nc_u16_e64_dpp v5, v1, v2 op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x58,0x03,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x58,0x03,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_nc_u16_e64_dpp v5, v1, v2 op_sel:[1,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x08,0x03,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x08,0x03,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_nc_u16_e64_dpp v5, v1, v2 op_sel:[0,1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x10,0x03,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x10,0x03,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_nc_u16_e64_dpp v255, v255, v255 op_sel:[0,0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0xc0,0x03,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0xc0,0x03,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x12,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x12,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_norm_i16_f16_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x12,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x05,0x01,0x12,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_norm_i16_f16_e64_dpp v5, -v1, |v2| op_sel:[1,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x0a,0x12,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x05,0x0a,0x12,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_norm_i16_f16_e64_dpp v255, -|v255|, -|v255| op_sel:[0,1,0] dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x13,0x12,0xd7,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0xff,0x13,0x12,0xd7,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x13,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x13,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_norm_u16_f16_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x13,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x05,0x01,0x13,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_norm_u16_f16_e64_dpp v5, -v1, |v2| op_sel:[1,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x0a,0x13,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x05,0x0a,0x13,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_norm_u16_f16_e64_dpp v255, -|v255|, -|v255| op_sel:[0,1,0] dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x13,0x13,0xd7,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0xff,0x13,0x13,0xd7,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_div_fixup_f16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x54,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x54,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_div_fixup_f16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x54,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x54,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_div_fixup_f16_e64_dpp v5, v1, v2, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x54,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x54,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_div_fixup_f16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x54,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x54,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_div_fixup_f16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x54,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x54,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_div_fixup_f16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x54,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x54,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_div_fixup_f16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x54,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x54,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_div_fixup_f16_e64_dpp v5, |v1|, v2, -m0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x54,0xd6,0xe9,0x04,0xf6,0x81,0x01,0x77,0x39,0x05]
+0x05,0x01,0x54,0xd6,0xe9,0x04,0xf6,0x81,0x01,0x77,0x39,0x05
+
+# GFX12: v_div_fixup_f16_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x54,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+0x05,0x02,0x54,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05
+
+# GFX12: v_div_fixup_f16_e64_dpp v5, -v1, v2, |exec_lo| op_sel:[1,1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x7c,0x54,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+0x05,0x7c,0x54,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05
+
+# GFX12: v_div_fixup_f16_e64_dpp v5, -|v1|, -|v2|, null op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x0b,0x54,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+0x05,0x0b,0x54,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05
+
+# GFX12: v_div_fixup_f16_e64_dpp v5, -|v1|, v2, -|-1| op_sel:[0,1,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x15,0x54,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05]
+0x05,0x15,0x54,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05
+
+# GFX12: v_div_fixup_f16_e64_dpp v5, v1, -|v2|, -|0.5| op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x26,0x54,0xd6,0xe9,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05]
+0x05,0x26,0x54,0xd6,0xe9,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05
+
+# GFX12: v_div_fixup_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0xc7,0x54,0xd6,0xea,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00]
+0xff,0xc7,0x54,0xd6,0xea,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00
+
+# GFX12: v_fma_f16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x48,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x48,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_fma_f16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x48,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x48,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_fma_f16_e64_dpp v5, v1, v2, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x48,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x48,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_fma_f16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x48,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x48,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_fma_f16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x48,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x48,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_fma_f16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x48,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x48,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_fma_f16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x48,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x48,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_fma_f16_e64_dpp v5, |v1|, v2, -m0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x48,0xd6,0xe9,0x04,0xf6,0x81,0x01,0x77,0x39,0x05]
+0x05,0x01,0x48,0xd6,0xe9,0x04,0xf6,0x81,0x01,0x77,0x39,0x05
+
+# GFX12: v_fma_f16_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x48,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+0x05,0x02,0x48,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05
+
+# GFX12: v_fma_f16_e64_dpp v5, -v1, v2, |exec_lo| op_sel:[1,1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x7c,0x48,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+0x05,0x7c,0x48,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05
+
+# GFX12: v_fma_f16_e64_dpp v5, -|v1|, -|v2|, null op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x0b,0x48,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+0x05,0x0b,0x48,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05
+
+# GFX12: v_fma_f16_e64_dpp v5, -|v1|, v2, -|-1| op_sel:[0,1,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x15,0x48,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05]
+0x05,0x15,0x48,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05
+
+# GFX12: v_fma_f16_e64_dpp v5, v1, -|v2|, -|0.5| op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x26,0x48,0xd6,0xe9,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05]
+0x05,0x26,0x48,0xd6,0xe9,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05
+
+# GFX12: v_fma_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0xc7,0x48,0xd6,0xea,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00]
+0xff,0xc7,0x48,0xd6,0xea,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00
+
+# GFX12: v_mad_i16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x53,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x53,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x53,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x53,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i16_e64_dpp v5, v1, v2, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x53,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x53,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x53,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x53,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x53,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x53,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x53,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x53,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x53,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x53,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i16_e64_dpp v5, v1, v2, m0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x53,0xd6,0xe9,0x04,0xf6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x53,0xd6,0xe9,0x04,0xf6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x78,0x53,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x78,0x53,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x08,0x53,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x08,0x53,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x10,0x53,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x10,0x53,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x20,0x53,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x20,0x53,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0xc0,0x53,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0xc0,0x53,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_mad_i32_i16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x5a,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x5a,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i32_i16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x5a,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x5a,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i32_i16_e64_dpp v5, v1, v2, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x5a,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x5a,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i32_i16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x5a,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x5a,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i32_i16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x5a,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x5a,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i32_i16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x5a,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x5a,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i32_i16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x5a,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x5a,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i32_i16_e64_dpp v5, v1, v2, m0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x5a,0xd6,0xe9,0x04,0xf6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x5a,0xd6,0xe9,0x04,0xf6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i32_i16_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x5a,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x5a,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i32_i16_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x5a,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x5a,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i32_i16_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x5a,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x5a,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i32_i16_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x5a,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x5a,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i32_i16_e64_dpp v5, v1, v2, 0.5 op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x08,0x5a,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x08,0x5a,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_i32_i16_e64_dpp v255, v255, v255, src_scc op_sel:[0,1,0,0] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x90,0x5a,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x90,0x5a,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_mad_u16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x41,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x41,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x41,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x41,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u16_e64_dpp v5, v1, v2, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x41,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x41,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x41,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x41,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x41,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x41,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x41,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x41,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x41,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x41,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u16_e64_dpp v5, v1, v2, m0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x41,0xd6,0xe9,0x04,0xf6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x41,0xd6,0xe9,0x04,0xf6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x78,0x41,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x78,0x41,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x08,0x41,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x08,0x41,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x10,0x41,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x10,0x41,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x20,0x41,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x20,0x41,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0xc0,0x41,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0xc0,0x41,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_mad_u32_u16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x59,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x59,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u32_u16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x59,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x59,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u32_u16_e64_dpp v5, v1, v2, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x59,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x59,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u32_u16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x59,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x59,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u32_u16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x59,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x59,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u32_u16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x59,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x59,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u32_u16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x59,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x59,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u32_u16_e64_dpp v5, v1, v2, m0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x59,0xd6,0xe9,0x04,0xf6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x59,0xd6,0xe9,0x04,0xf6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u32_u16_e64_dpp v5, v1, v2, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x59,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x59,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u32_u16_e64_dpp v5, v1, v2, exec_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x59,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x59,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u32_u16_e64_dpp v5, v1, v2, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x59,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x59,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u32_u16_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x59,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x00,0x59,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u32_u16_e64_dpp v5, v1, v2, 0.5 op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x08,0x59,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05]
+0x05,0x08,0x59,0xd6,0xe9,0x04,0xc2,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_mad_u32_u16_e64_dpp v255, v255, v255, src_scc op_sel:[0,1,0,0] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x90,0x59,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x90,0x59,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_max3_num_f16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2c,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x2c,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_num_f16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2c,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x2c,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_num_f16_e64_dpp v5, v1, v2, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2c,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x2c,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_num_f16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2c,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x2c,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_num_f16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2c,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x2c,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_num_f16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2c,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x2c,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_num_f16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2c,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x2c,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_num_f16_e64_dpp v5, |v1|, v2, -m0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x2c,0xd6,0xe9,0x04,0xf6,0x81,0x01,0x77,0x39,0x05]
+0x05,0x01,0x2c,0xd6,0xe9,0x04,0xf6,0x81,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_num_f16_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x2c,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+0x05,0x02,0x2c,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_num_f16_e64_dpp v5, -v1, v2, |exec_lo| op_sel:[1,1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x7c,0x2c,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+0x05,0x7c,0x2c,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_num_f16_e64_dpp v5, -|v1|, -|v2|, null op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x0b,0x2c,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+0x05,0x0b,0x2c,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_num_f16_e64_dpp v5, -|v1|, v2, -|-1| op_sel:[0,1,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x15,0x2c,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05]
+0x05,0x15,0x2c,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x26,0x2c,0xd6,0xe9,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05]
+0x05,0x26,0x2c,0xd6,0xe9,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0xc7,0x2c,0xd6,0xea,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00]
+0xff,0xc7,0x2c,0xd6,0xea,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00
+
+# GFX12: v_max3_i16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4d,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4d,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_i16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4d,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4d,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_i16_e64_dpp v5, v1, v2, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4d,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4d,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_i16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4d,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4d,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_i16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4d,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4d,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_i16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4d,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4d,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_i16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4d,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4d,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_i16_e64_dpp v5, v1, v2, m0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4d,0xd6,0xe9,0x04,0xf6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4d,0xd6,0xe9,0x04,0xf6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_i16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x78,0x4d,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x78,0x4d,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_i16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x08,0x4d,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x08,0x4d,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_i16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x10,0x4d,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x10,0x4d,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_i16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x20,0x4d,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x20,0x4d,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_i16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x40,0x4d,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x40,0x4d,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_max3_u16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4e,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4e,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_u16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4e,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4e,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_u16_e64_dpp v5, v1, v2, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4e,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4e,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_u16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4e,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4e,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_u16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4e,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4e,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_u16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4e,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4e,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_u16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4e,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4e,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_u16_e64_dpp v5, v1, v2, m0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4e,0xd6,0xe9,0x04,0xf6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4e,0xd6,0xe9,0x04,0xf6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_u16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x78,0x4e,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x78,0x4e,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_u16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x08,0x4e,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x08,0x4e,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_u16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x10,0x4e,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x10,0x4e,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_u16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x20,0x4e,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x20,0x4e,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_max3_u16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x40,0x4e,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x40,0x4e,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_med3_num_f16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x32,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x32,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_num_f16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x32,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x32,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_num_f16_e64_dpp v5, v1, v2, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x32,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x32,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_num_f16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x32,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x32,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_num_f16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x32,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x32,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_num_f16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x32,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x32,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_num_f16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x32,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x32,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_num_f16_e64_dpp v5, |v1|, v2, -m0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x32,0xd6,0xe9,0x04,0xf6,0x81,0x01,0x77,0x39,0x05]
+0x05,0x01,0x32,0xd6,0xe9,0x04,0xf6,0x81,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_num_f16_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x32,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+0x05,0x02,0x32,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_num_f16_e64_dpp v5, -v1, v2, |exec_lo| op_sel:[1,1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x7c,0x32,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+0x05,0x7c,0x32,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_num_f16_e64_dpp v5, -|v1|, -|v2|, null op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x0b,0x32,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+0x05,0x0b,0x32,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_num_f16_e64_dpp v5, -|v1|, v2, -|-1| op_sel:[0,1,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x15,0x32,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05]
+0x05,0x15,0x32,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x26,0x32,0xd6,0xe9,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05]
+0x05,0x26,0x32,0xd6,0xe9,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0xc7,0x32,0xd6,0xea,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00]
+0xff,0xc7,0x32,0xd6,0xea,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00
+
+# GFX12: v_med3_i16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x50,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x50,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_i16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x50,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x50,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_i16_e64_dpp v5, v1, v2, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x50,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x50,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_i16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x50,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x50,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_i16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x50,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x50,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_i16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x50,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x50,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_i16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x50,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x50,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_i16_e64_dpp v5, v1, v2, m0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x50,0xd6,0xe9,0x04,0xf6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x50,0xd6,0xe9,0x04,0xf6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_i16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x78,0x50,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x78,0x50,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_i16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x08,0x50,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x08,0x50,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_i16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x10,0x50,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x10,0x50,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_i16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x20,0x50,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x20,0x50,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_i16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x40,0x50,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x40,0x50,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_med3_u16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x51,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x51,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_u16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x51,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x51,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_u16_e64_dpp v5, v1, v2, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x51,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x51,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_u16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x51,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x51,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_u16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x51,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x51,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_u16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x51,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x51,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_u16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x51,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x51,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_u16_e64_dpp v5, v1, v2, m0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x51,0xd6,0xe9,0x04,0xf6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x51,0xd6,0xe9,0x04,0xf6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_u16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x78,0x51,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x78,0x51,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_u16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x08,0x51,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x08,0x51,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_u16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x10,0x51,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x10,0x51,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_u16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x20,0x51,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x20,0x51,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_med3_u16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x40,0x51,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x40,0x51,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_min3_num_f16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2b,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x2b,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_num_f16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2b,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x2b,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_num_f16_e64_dpp v5, v1, v2, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2b,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x2b,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_num_f16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2b,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x2b,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_num_f16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2b,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x2b,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_num_f16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2b,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x2b,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_num_f16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2b,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x2b,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_num_f16_e64_dpp v5, |v1|, v2, -m0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x2b,0xd6,0xe9,0x04,0xf6,0x81,0x01,0x77,0x39,0x05]
+0x05,0x01,0x2b,0xd6,0xe9,0x04,0xf6,0x81,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_num_f16_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x2b,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05]
+0x05,0x02,0x2b,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_num_f16_e64_dpp v5, -v1, v2, |exec_lo| op_sel:[1,1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x7c,0x2b,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05]
+0x05,0x7c,0x2b,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_num_f16_e64_dpp v5, -|v1|, -|v2|, null op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x0b,0x2b,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05]
+0x05,0x0b,0x2b,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_num_f16_e64_dpp v5, -|v1|, v2, -|-1| op_sel:[0,1,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x15,0x2b,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05]
+0x05,0x15,0x2b,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x26,0x2b,0xd6,0xe9,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05]
+0x05,0x26,0x2b,0xd6,0xe9,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0xc7,0x2b,0xd6,0xea,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00]
+0xff,0xc7,0x2b,0xd6,0xea,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00
+
+# GFX12: v_min3_i16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4a,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4a,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_i16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4a,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4a,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_i16_e64_dpp v5, v1, v2, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4a,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4a,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_i16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4a,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4a,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_i16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4a,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4a,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_i16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4a,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4a,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_i16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4a,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4a,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_i16_e64_dpp v5, v1, v2, m0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4a,0xd6,0xe9,0x04,0xf6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4a,0xd6,0xe9,0x04,0xf6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_i16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x78,0x4a,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x78,0x4a,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_i16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x08,0x4a,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x08,0x4a,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_i16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x10,0x4a,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x10,0x4a,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_i16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x20,0x4a,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x20,0x4a,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_i16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x40,0x4a,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x40,0x4a,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_min3_u16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4b,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4b,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_u16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4b,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4b,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_u16_e64_dpp v5, v1, v2, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4b,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4b,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_u16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4b,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4b,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_u16_e64_dpp v5, v1, v2, ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4b,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4b,0xd6,0xe9,0x04,0xee,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_u16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4b,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4b,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_u16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4b,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4b,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_u16_e64_dpp v5, v1, v2, m0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x4b,0xd6,0xe9,0x04,0xf6,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x4b,0xd6,0xe9,0x04,0xf6,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_u16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x78,0x4b,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05]
+0x05,0x78,0x4b,0xd6,0xe9,0x04,0xfe,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_u16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x08,0x4b,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x08,0x4b,0xd6,0xe9,0x04,0xfa,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_u16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x10,0x4b,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x10,0x4b,0xd6,0xe9,0x04,0xf2,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_u16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x20,0x4b,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05]
+0x05,0x20,0x4b,0xd6,0xe9,0x04,0x06,0x03,0x01,0x77,0x39,0x05
+
+# GFX12: v_min3_u16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x40,0x4b,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0xff,0x40,0x4b,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
+
+# GFX12: v_pack_b32_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x11,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x11,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_pack_b32_f16_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x11,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x05,0x01,0x11,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_pack_b32_f16_e64_dpp v5, -v1, |v2| op_sel:[1,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x0a,0x11,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x05,0x0a,0x11,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_pack_b32_f16_e64_dpp v255, -|v255|, -|v255| op_sel:[0,1,0] dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x13,0x11,0xd7,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0xff,0x13,0x11,0xd7,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_sub_nc_i16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0e,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0e,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_sub_nc_i16_e64_dpp v5, v1, v2 op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x58,0x0e,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x58,0x0e,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_sub_nc_i16_e64_dpp v5, v1, v2 op_sel:[1,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x08,0x0e,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x08,0x0e,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_sub_nc_i16_e64_dpp v5, v1, v2 op_sel:[0,1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x10,0x0e,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x10,0x0e,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_sub_nc_i16_e64_dpp v255, v255, v255 op_sel:[0,0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0xc0,0x0e,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0xc0,0x0e,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_sub_nc_u16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x04,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x04,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_sub_nc_u16_e64_dpp v5, v1, v2 op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x58,0x04,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x58,0x04,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_sub_nc_u16_e64_dpp v5, v1, v2 op_sel:[1,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x08,0x04,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x08,0x04,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_sub_nc_u16_e64_dpp v5, v1, v2 op_sel:[0,1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x10,0x04,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x10,0x04,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_sub_nc_u16_e64_dpp v255, v255, v255 op_sel:[0,0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0xc0,0x04,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0xc0,0x04,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_dot2_f16_f16_e64_dpp v0, v1, v2, v3 dpp8:[0,1,2,3,4,4,4,4] ; encoding: [0x00,0x00,0x66,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x88,0x46,0x92]
+0x00,0x00,0x66,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x88,0x46,0x92
+
+# op_sel[1:0] are ignored
+# GFX12: v_dot2_f16_f16_e64_dpp v0, v1, v2, v3 op_sel:[0,0,1,1] dpp8:[0,1,2,3,4,4,4,4] ; encoding: [0x00,0x60,0x66,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x88,0x46,0x92]
+0x00,0x78,0x66,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x88,0x46,0x92
+
+# GFX12: v_dot2_f16_f16_e64_dpp v0, v1, v2, v3 op_sel:[0,0,1,1] dpp8:[0,1,2,3,4,4,4,4] ; encoding: [0x00,0x60,0x66,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x88,0x46,0x92]
+0x00,0x60,0x66,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x88,0x46,0x92
+
+# GFX12: v_dot2_f16_f16_e64_dpp v0, |v1|, -v2, -|s3| op_sel:[0,0,1,1] dpp8:[0,1,2,3,4,4,4,4] ; encoding: [0x00,0x65,0x66,0xd6,0xe9,0x04,0x0e,0xc0,0x01,0x88,0x46,0x92]
+0x00,0x65,0x66,0xd6,0xe9,0x04,0x0e,0xc0,0x01,0x88,0x46,0x92
+
+# GFX12: v_dot2_bf16_bf16_e64_dpp v0, v1, v2, v3 dpp8:[0,1,2,3,4,4,4,4] ; encoding: [0x00,0x00,0x67,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x88,0x46,0x92]
+0x00,0x00,0x67,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x88,0x46,0x92
+
+# op_sel[1:0] are ignored
+# GFX12: v_dot2_bf16_bf16_e64_dpp v0, v1, v2, v3 op_sel:[0,0,1,1] dpp8:[0,1,2,3,4,4,4,4] ; encoding: [0x00,0x60,0x67,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x88,0x46,0x92]
+0x00,0x78,0x67,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x88,0x46,0x92
+
+# GFX12: v_dot2_bf16_bf16_e64_dpp v0, v1, v2, v3 op_sel:[0,0,1,1] dpp8:[0,1,2,3,4,4,4,4] ; encoding: [0x00,0x60,0x67,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x88,0x46,0x92]
+0x00,0x60,0x67,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x88,0x46,0x92
+
+# GFX12: v_dot2_bf16_bf16_e64_dpp v0, |v1|, -v2, -|s3| op_sel:[0,0,1,1] dpp8:[0,1,2,3,4,4,4,4] ; encoding: [0x00,0x65,0x67,0xd6,0xe9,0x04,0x0e,0xc0,0x01,0x88,0x46,0x92]
+0x00,0x65,0x67,0xd6,0xe9,0x04,0x0e,0xc0,0x01,0x88,0x46,0x92
+
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1.txt
new file mode 100644
index 000000000000..4fe4284e8eb4
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1.txt
@@ -0,0 +1,3277 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX12 %s
+
+# GFX12: v_bfrev_b32_e64 v5, v1                  ; encoding: [0x05,0x00,0xb8,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xb8,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_bfrev_b32_e64 v5, v255                ; encoding: [0x05,0x00,0xb8,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xb8,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_bfrev_b32_e64 v5, s1                  ; encoding: [0x05,0x00,0xb8,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xb8,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_bfrev_b32_e64 v5, s105                ; encoding: [0x05,0x00,0xb8,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xb8,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_bfrev_b32_e64 v5, vcc_lo              ; encoding: [0x05,0x00,0xb8,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xb8,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_bfrev_b32_e64 v5, vcc_hi              ; encoding: [0x05,0x00,0xb8,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xb8,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_bfrev_b32_e64 v5, ttmp15              ; encoding: [0x05,0x00,0xb8,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xb8,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_bfrev_b32_e64 v5, m0                  ; encoding: [0x05,0x00,0xb8,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xb8,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_bfrev_b32_e64 v5, exec_lo             ; encoding: [0x05,0x00,0xb8,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xb8,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_bfrev_b32_e64 v5, exec_hi             ; encoding: [0x05,0x00,0xb8,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xb8,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_bfrev_b32_e64 v5, null                ; encoding: [0x05,0x00,0xb8,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xb8,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_bfrev_b32_e64 v5, -1                  ; encoding: [0x05,0x00,0xb8,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xb8,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_bfrev_b32_e64 v5, 0.5                 ; encoding: [0x05,0x00,0xb8,0xd5,0xf0,0x00,0x00,0x00]
+0x05,0x00,0xb8,0xd5,0xf0,0x00,0x00,0x00
+
+# GFX12: v_bfrev_b32_e64 v5, src_scc             ; encoding: [0x05,0x00,0xb8,0xd5,0xfd,0x00,0x00,0x00]
+0x05,0x00,0xb8,0xd5,0xfd,0x00,0x00,0x00
+
+# GFX12: v_bfrev_b32_e64 v255, 0xaf123456        ; encoding: [0xff,0x00,0xb8,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0xb8,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_ceil_f16_e64 v5, v1                   ; encoding: [0x05,0x00,0xdc,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xdc,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_ceil_f16_e64 v5, v255                 ; encoding: [0x05,0x00,0xdc,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xdc,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_ceil_f16_e64 v5, s1                   ; encoding: [0x05,0x00,0xdc,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xdc,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_ceil_f16_e64 v5, s105                 ; encoding: [0x05,0x00,0xdc,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xdc,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_ceil_f16_e64 v5, vcc_lo               ; encoding: [0x05,0x00,0xdc,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xdc,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_ceil_f16_e64 v5, vcc_hi               ; encoding: [0x05,0x00,0xdc,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xdc,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_ceil_f16_e64 v5, ttmp15               ; encoding: [0x05,0x00,0xdc,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xdc,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_ceil_f16_e64 v5, m0                   ; encoding: [0x05,0x00,0xdc,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xdc,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_ceil_f16_e64 v5, exec_lo              ; encoding: [0x05,0x00,0xdc,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xdc,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_ceil_f16_e64 v5, exec_hi              ; encoding: [0x05,0x00,0xdc,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xdc,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_ceil_f16_e64 v5, null                 ; encoding: [0x05,0x00,0xdc,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xdc,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_ceil_f16_e64 v5, -1                   ; encoding: [0x05,0x00,0xdc,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xdc,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_ceil_f16_e64 v5, 0.5 mul:2            ; encoding: [0x05,0x00,0xdc,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xdc,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_ceil_f16_e64 v5, src_scc mul:4        ; encoding: [0x05,0x00,0xdc,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xdc,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_ceil_f16_e64 v255, -|0xfe0b| clamp div:2 ; encoding: [0xff,0x81,0xdc,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00]
+0xff,0x81,0xdc,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_ceil_f32_e64 v5, v1                   ; encoding: [0x05,0x00,0xa2,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xa2,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_ceil_f32_e64 v5, v255                 ; encoding: [0x05,0x00,0xa2,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xa2,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_ceil_f32_e64 v5, s1                   ; encoding: [0x05,0x00,0xa2,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xa2,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_ceil_f32_e64 v5, s105                 ; encoding: [0x05,0x00,0xa2,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xa2,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_ceil_f32_e64 v5, vcc_lo               ; encoding: [0x05,0x00,0xa2,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xa2,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_ceil_f32_e64 v5, vcc_hi               ; encoding: [0x05,0x00,0xa2,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xa2,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_ceil_f32_e64 v5, ttmp15               ; encoding: [0x05,0x00,0xa2,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xa2,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_ceil_f32_e64 v5, m0                   ; encoding: [0x05,0x00,0xa2,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xa2,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_ceil_f32_e64 v5, exec_lo              ; encoding: [0x05,0x00,0xa2,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xa2,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_ceil_f32_e64 v5, exec_hi              ; encoding: [0x05,0x00,0xa2,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xa2,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_ceil_f32_e64 v5, null                 ; encoding: [0x05,0x00,0xa2,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xa2,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_ceil_f32_e64 v5, -1                   ; encoding: [0x05,0x00,0xa2,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xa2,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_ceil_f32_e64 v5, 0.5 mul:2            ; encoding: [0x05,0x00,0xa2,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xa2,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_ceil_f32_e64 v5, src_scc mul:4        ; encoding: [0x05,0x00,0xa2,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xa2,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_ceil_f32_e64 v255, -|0xaf123456| clamp div:2 ; encoding: [0xff,0x81,0xa2,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+0xff,0x81,0xa2,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf
+
+# GFX12: v_ceil_f64_e64 v[5:6], v[1:2]           ; encoding: [0x05,0x00,0x98,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0x98,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_ceil_f64_e64 v[5:6], v[254:255]       ; encoding: [0x05,0x00,0x98,0xd5,0xfe,0x01,0x00,0x00]
+0x05,0x00,0x98,0xd5,0xfe,0x01,0x00,0x00
+
+# GFX12: v_ceil_f64_e64 v[5:6], s[2:3]           ; encoding: [0x05,0x00,0x98,0xd5,0x02,0x00,0x00,0x00]
+0x05,0x00,0x98,0xd5,0x02,0x00,0x00,0x00
+
+# GFX12: v_ceil_f64_e64 v[5:6], s[104:105]       ; encoding: [0x05,0x00,0x98,0xd5,0x68,0x00,0x00,0x00]
+0x05,0x00,0x98,0xd5,0x68,0x00,0x00,0x00
+
+# GFX12: v_ceil_f64_e64 v[5:6], vcc              ; encoding: [0x05,0x00,0x98,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0x98,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_ceil_f64_e64 v[5:6], ttmp[14:15]      ; encoding: [0x05,0x00,0x98,0xd5,0x7a,0x00,0x00,0x00]
+0x05,0x00,0x98,0xd5,0x7a,0x00,0x00,0x00
+
+# GFX12: v_ceil_f64_e64 v[5:6], exec             ; encoding: [0x05,0x00,0x98,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0x98,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_ceil_f64_e64 v[5:6], null             ; encoding: [0x05,0x00,0x98,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0x98,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_ceil_f64_e64 v[5:6], -1               ; encoding: [0x05,0x00,0x98,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0x98,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_ceil_f64_e64 v[5:6], 0.5 mul:2        ; encoding: [0x05,0x00,0x98,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0x98,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_ceil_f64_e64 v[5:6], -|src_scc| mul:4 ; encoding: [0x05,0x01,0x98,0xd5,0xfd,0x00,0x00,0x30]
+0x05,0x01,0x98,0xd5,0xfd,0x00,0x00,0x30
+
+# GFX12: v_ceil_f64_e64 v[254:255], 0xaf123456 clamp div:2 ; encoding: [0xfe,0x80,0x98,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+0xfe,0x80,0x98,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cls_i32_e64 v5, v1                    ; encoding: [0x05,0x00,0xbb,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xbb,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cls_i32_e64 v5, v255                  ; encoding: [0x05,0x00,0xbb,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xbb,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_cls_i32_e64 v5, s1                    ; encoding: [0x05,0x00,0xbb,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xbb,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_cls_i32_e64 v5, s105                  ; encoding: [0x05,0x00,0xbb,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xbb,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_cls_i32_e64 v5, vcc_lo                ; encoding: [0x05,0x00,0xbb,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xbb,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cls_i32_e64 v5, vcc_hi                ; encoding: [0x05,0x00,0xbb,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xbb,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_cls_i32_e64 v5, ttmp15                ; encoding: [0x05,0x00,0xbb,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xbb,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_cls_i32_e64 v5, m0                    ; encoding: [0x05,0x00,0xbb,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xbb,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_cls_i32_e64 v5, exec_lo               ; encoding: [0x05,0x00,0xbb,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xbb,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cls_i32_e64 v5, exec_hi               ; encoding: [0x05,0x00,0xbb,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xbb,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cls_i32_e64 v5, null                  ; encoding: [0x05,0x00,0xbb,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xbb,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cls_i32_e64 v5, -1                    ; encoding: [0x05,0x00,0xbb,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xbb,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cls_i32_e64 v5, 0.5                   ; encoding: [0x05,0x00,0xbb,0xd5,0xf0,0x00,0x00,0x00]
+0x05,0x00,0xbb,0xd5,0xf0,0x00,0x00,0x00
+
+# GFX12: v_cls_i32_e64 v5, src_scc               ; encoding: [0x05,0x00,0xbb,0xd5,0xfd,0x00,0x00,0x00]
+0x05,0x00,0xbb,0xd5,0xfd,0x00,0x00,0x00
+
+# GFX12: v_cls_i32_e64 v255, 0xaf123456          ; encoding: [0xff,0x00,0xbb,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0xbb,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_clz_i32_u32_e64 v5, v1                ; encoding: [0x05,0x00,0xb9,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xb9,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_clz_i32_u32_e64 v5, v255              ; encoding: [0x05,0x00,0xb9,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xb9,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_clz_i32_u32_e64 v5, s1                ; encoding: [0x05,0x00,0xb9,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xb9,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_clz_i32_u32_e64 v5, s105              ; encoding: [0x05,0x00,0xb9,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xb9,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_clz_i32_u32_e64 v5, vcc_lo            ; encoding: [0x05,0x00,0xb9,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xb9,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_clz_i32_u32_e64 v5, vcc_hi            ; encoding: [0x05,0x00,0xb9,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xb9,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_clz_i32_u32_e64 v5, ttmp15            ; encoding: [0x05,0x00,0xb9,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xb9,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_clz_i32_u32_e64 v5, m0                ; encoding: [0x05,0x00,0xb9,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xb9,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_clz_i32_u32_e64 v5, exec_lo           ; encoding: [0x05,0x00,0xb9,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xb9,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_clz_i32_u32_e64 v5, exec_hi           ; encoding: [0x05,0x00,0xb9,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xb9,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_clz_i32_u32_e64 v5, null              ; encoding: [0x05,0x00,0xb9,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xb9,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_clz_i32_u32_e64 v5, -1                ; encoding: [0x05,0x00,0xb9,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xb9,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_clz_i32_u32_e64 v5, 0.5               ; encoding: [0x05,0x00,0xb9,0xd5,0xf0,0x00,0x00,0x00]
+0x05,0x00,0xb9,0xd5,0xf0,0x00,0x00,0x00
+
+# GFX12: v_clz_i32_u32_e64 v5, src_scc           ; encoding: [0x05,0x00,0xb9,0xd5,0xfd,0x00,0x00,0x00]
+0x05,0x00,0xb9,0xd5,0xfd,0x00,0x00,0x00
+
+# GFX12: v_clz_i32_u32_e64 v255, 0xaf123456      ; encoding: [0xff,0x00,0xb9,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0xb9,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cos_f16_e64 v5, v1                    ; encoding: [0x05,0x00,0xe1,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xe1,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cos_f16_e64 v5, v255                  ; encoding: [0x05,0x00,0xe1,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xe1,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_cos_f16_e64 v5, s1                    ; encoding: [0x05,0x00,0xe1,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xe1,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_cos_f16_e64 v5, s105                  ; encoding: [0x05,0x00,0xe1,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xe1,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_cos_f16_e64 v5, vcc_lo                ; encoding: [0x05,0x00,0xe1,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xe1,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cos_f16_e64 v5, vcc_hi                ; encoding: [0x05,0x00,0xe1,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xe1,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_cos_f16_e64 v5, ttmp15                ; encoding: [0x05,0x00,0xe1,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xe1,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_cos_f16_e64 v5, m0                    ; encoding: [0x05,0x00,0xe1,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xe1,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_cos_f16_e64 v5, exec_lo               ; encoding: [0x05,0x00,0xe1,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xe1,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cos_f16_e64 v5, exec_hi               ; encoding: [0x05,0x00,0xe1,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xe1,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cos_f16_e64 v5, null                  ; encoding: [0x05,0x00,0xe1,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xe1,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cos_f16_e64 v5, -1                    ; encoding: [0x05,0x00,0xe1,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xe1,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cos_f16_e64 v5, 0.5 mul:2             ; encoding: [0x05,0x00,0xe1,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xe1,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_cos_f16_e64 v5, src_scc mul:4         ; encoding: [0x05,0x00,0xe1,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xe1,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_cos_f16_e64 v255, -|0xfe0b| clamp div:2 ; encoding: [0xff,0x81,0xe1,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00]
+0xff,0x81,0xe1,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cos_f32_e64 v5, v1                    ; encoding: [0x05,0x00,0xb6,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xb6,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cos_f32_e64 v5, v255                  ; encoding: [0x05,0x00,0xb6,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xb6,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_cos_f32_e64 v5, s1                    ; encoding: [0x05,0x00,0xb6,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xb6,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_cos_f32_e64 v5, s105                  ; encoding: [0x05,0x00,0xb6,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xb6,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_cos_f32_e64 v5, vcc_lo                ; encoding: [0x05,0x00,0xb6,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xb6,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cos_f32_e64 v5, vcc_hi                ; encoding: [0x05,0x00,0xb6,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xb6,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_cos_f32_e64 v5, ttmp15                ; encoding: [0x05,0x00,0xb6,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xb6,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_cos_f32_e64 v5, m0                    ; encoding: [0x05,0x00,0xb6,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xb6,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_cos_f32_e64 v5, exec_lo               ; encoding: [0x05,0x00,0xb6,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xb6,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cos_f32_e64 v5, exec_hi               ; encoding: [0x05,0x00,0xb6,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xb6,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cos_f32_e64 v5, null                  ; encoding: [0x05,0x00,0xb6,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xb6,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cos_f32_e64 v5, -1                    ; encoding: [0x05,0x00,0xb6,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xb6,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cos_f32_e64 v5, 0.5 mul:2             ; encoding: [0x05,0x00,0xb6,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xb6,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_cos_f32_e64 v5, src_scc mul:4         ; encoding: [0x05,0x00,0xb6,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xb6,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_cos_f32_e64 v255, -|0xaf123456| clamp div:2 ; encoding: [0xff,0x81,0xb6,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+0xff,0x81,0xb6,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf
+
+# GFX12: v_ctz_i32_b32_e64 v5, v1                ; encoding: [0x05,0x00,0xba,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xba,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_ctz_i32_b32_e64 v5, v255              ; encoding: [0x05,0x00,0xba,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xba,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_ctz_i32_b32_e64 v5, s1                ; encoding: [0x05,0x00,0xba,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xba,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_ctz_i32_b32_e64 v5, s105              ; encoding: [0x05,0x00,0xba,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xba,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_ctz_i32_b32_e64 v5, vcc_lo            ; encoding: [0x05,0x00,0xba,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xba,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_ctz_i32_b32_e64 v5, vcc_hi            ; encoding: [0x05,0x00,0xba,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xba,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_ctz_i32_b32_e64 v5, ttmp15            ; encoding: [0x05,0x00,0xba,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xba,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_ctz_i32_b32_e64 v5, m0                ; encoding: [0x05,0x00,0xba,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xba,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_ctz_i32_b32_e64 v5, exec_lo           ; encoding: [0x05,0x00,0xba,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xba,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_ctz_i32_b32_e64 v5, exec_hi           ; encoding: [0x05,0x00,0xba,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xba,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_ctz_i32_b32_e64 v5, null              ; encoding: [0x05,0x00,0xba,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xba,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_ctz_i32_b32_e64 v5, -1                ; encoding: [0x05,0x00,0xba,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xba,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_ctz_i32_b32_e64 v5, 0.5               ; encoding: [0x05,0x00,0xba,0xd5,0xf0,0x00,0x00,0x00]
+0x05,0x00,0xba,0xd5,0xf0,0x00,0x00,0x00
+
+# GFX12: v_ctz_i32_b32_e64 v5, src_scc           ; encoding: [0x05,0x00,0xba,0xd5,0xfd,0x00,0x00,0x00]
+0x05,0x00,0xba,0xd5,0xfd,0x00,0x00,0x00
+
+# GFX12: v_ctz_i32_b32_e64 v255, 0xaf123456      ; encoding: [0xff,0x00,0xba,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0xba,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_f16_f32_e64 v5, v1                ; encoding: [0x05,0x00,0x8a,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0x8a,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cvt_f16_f32_e64 v5, v255              ; encoding: [0x05,0x00,0x8a,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0x8a,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_cvt_f16_f32_e64 v5, s1                ; encoding: [0x05,0x00,0x8a,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0x8a,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_f32_e64 v5, s105              ; encoding: [0x05,0x00,0x8a,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0x8a,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_f32_e64 v5, vcc_lo            ; encoding: [0x05,0x00,0x8a,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0x8a,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_f32_e64 v5, vcc_hi            ; encoding: [0x05,0x00,0x8a,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0x8a,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_f32_e64 v5, ttmp15            ; encoding: [0x05,0x00,0x8a,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0x8a,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_f32_e64 v5, m0                ; encoding: [0x05,0x00,0x8a,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0x8a,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_f32_e64 v5, exec_lo           ; encoding: [0x05,0x00,0x8a,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0x8a,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_f32_e64 v5, exec_hi           ; encoding: [0x05,0x00,0x8a,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0x8a,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_f32_e64 v5, null              ; encoding: [0x05,0x00,0x8a,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0x8a,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_f32_e64 v5, -1                ; encoding: [0x05,0x00,0x8a,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0x8a,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_f32_e64 v5, 0.5 mul:2         ; encoding: [0x05,0x00,0x8a,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0x8a,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_cvt_f16_f32_e64 v5, src_scc mul:4     ; encoding: [0x05,0x00,0x8a,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0x8a,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_cvt_f16_f32_e64 v255, -|0xaf123456| clamp div:2 ; encoding: [0xff,0x81,0x8a,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+0xff,0x81,0x8a,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_f16_i16_e64 v5, v1                ; encoding: [0x05,0x00,0xd1,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xd1,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cvt_f16_i16_e64 v5, v255              ; encoding: [0x05,0x00,0xd1,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xd1,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_cvt_f16_i16_e64 v5, s1                ; encoding: [0x05,0x00,0xd1,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xd1,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_i16_e64 v5, s105              ; encoding: [0x05,0x00,0xd1,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xd1,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_i16_e64 v5, vcc_lo            ; encoding: [0x05,0x00,0xd1,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xd1,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_i16_e64 v5, vcc_hi            ; encoding: [0x05,0x00,0xd1,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xd1,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_i16_e64 v5, ttmp15            ; encoding: [0x05,0x00,0xd1,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xd1,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_i16_e64 v5, m0                ; encoding: [0x05,0x00,0xd1,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xd1,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_i16_e64 v5, exec_lo           ; encoding: [0x05,0x00,0xd1,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xd1,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_i16_e64 v5, exec_hi           ; encoding: [0x05,0x00,0xd1,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xd1,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_i16_e64 v5, null              ; encoding: [0x05,0x00,0xd1,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xd1,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_i16_e64 v5, -1                ; encoding: [0x05,0x00,0xd1,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xd1,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_i16_e64 v5, 0x3800 mul:2
+0x05,0x00,0xd1,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_cvt_f16_i16_e64 v5, src_scc mul:4     ; encoding: [0x05,0x00,0xd1,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xd1,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_cvt_f16_i16_e64 v255, 0xfe0b clamp div:2 ; encoding: [0xff,0x80,0xd1,0xd5,0xff,0x00,0x00,0x18,0x0b,0xfe,0x00,0x00]
+0xff,0x80,0xd1,0xd5,0xff,0x00,0x00,0x18,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cvt_f16_u16_e64 v5, v1                ; encoding: [0x05,0x00,0xd0,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xd0,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cvt_f16_u16_e64 v5, v255              ; encoding: [0x05,0x00,0xd0,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xd0,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_cvt_f16_u16_e64 v5, s1                ; encoding: [0x05,0x00,0xd0,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xd0,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_u16_e64 v5, s105              ; encoding: [0x05,0x00,0xd0,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xd0,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_u16_e64 v5, vcc_lo            ; encoding: [0x05,0x00,0xd0,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xd0,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_u16_e64 v5, vcc_hi            ; encoding: [0x05,0x00,0xd0,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xd0,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_u16_e64 v5, ttmp15            ; encoding: [0x05,0x00,0xd0,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xd0,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_u16_e64 v5, m0                ; encoding: [0x05,0x00,0xd0,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xd0,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_u16_e64 v5, exec_lo           ; encoding: [0x05,0x00,0xd0,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xd0,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_u16_e64 v5, exec_hi           ; encoding: [0x05,0x00,0xd0,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xd0,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_u16_e64 v5, null              ; encoding: [0x05,0x00,0xd0,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xd0,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_u16_e64 v5, -1                ; encoding: [0x05,0x00,0xd0,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xd0,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_u16_e64 v5, 0x3800 mul:2
+0x05,0x00,0xd0,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_cvt_f16_u16_e64 v5, src_scc mul:4     ; encoding: [0x05,0x00,0xd0,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xd0,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_cvt_f16_u16_e64 v255, 0xfe0b clamp div:2 ; encoding: [0xff,0x80,0xd0,0xd5,0xff,0x00,0x00,0x18,0x0b,0xfe,0x00,0x00]
+0xff,0x80,0xd0,0xd5,0xff,0x00,0x00,0x18,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cvt_f32_f16_e64 v5, v1                ; encoding: [0x05,0x00,0x8b,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0x8b,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cvt_f32_f16_e64 v5, v255              ; encoding: [0x05,0x00,0x8b,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0x8b,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_cvt_f32_f16_e64 v5, s1                ; encoding: [0x05,0x00,0x8b,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0x8b,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_f16_e64 v5, s105              ; encoding: [0x05,0x00,0x8b,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0x8b,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_f16_e64 v5, vcc_lo            ; encoding: [0x05,0x00,0x8b,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0x8b,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_f16_e64 v5, vcc_hi            ; encoding: [0x05,0x00,0x8b,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0x8b,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_f16_e64 v5, ttmp15            ; encoding: [0x05,0x00,0x8b,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0x8b,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_f16_e64 v5, m0                ; encoding: [0x05,0x00,0x8b,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0x8b,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_f16_e64 v5, exec_lo           ; encoding: [0x05,0x00,0x8b,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0x8b,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_f16_e64 v5, exec_hi           ; encoding: [0x05,0x00,0x8b,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0x8b,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_f16_e64 v5, null              ; encoding: [0x05,0x00,0x8b,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0x8b,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_f16_e64 v5, -1                ; encoding: [0x05,0x00,0x8b,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0x8b,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_f16_e64 v5, 0.5 mul:2         ; encoding: [0x05,0x00,0x8b,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0x8b,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_cvt_f32_f16_e64 v5, src_scc mul:4     ; encoding: [0x05,0x00,0x8b,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0x8b,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_cvt_f32_f16_e64 v255, -|0xfe0b| clamp div:2 ; encoding: [0xff,0x81,0x8b,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00]
+0xff,0x81,0x8b,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cvt_f32_f64_e64 v5, v[1:2]            ; encoding: [0x05,0x00,0x8f,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0x8f,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cvt_f32_f64_e64 v5, v[254:255]        ; encoding: [0x05,0x00,0x8f,0xd5,0xfe,0x01,0x00,0x00]
+0x05,0x00,0x8f,0xd5,0xfe,0x01,0x00,0x00
+
+# GFX12: v_cvt_f32_f64_e64 v5, s[2:3]            ; encoding: [0x05,0x00,0x8f,0xd5,0x02,0x00,0x00,0x00]
+0x05,0x00,0x8f,0xd5,0x02,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_f64_e64 v5, s[104:105]        ; encoding: [0x05,0x00,0x8f,0xd5,0x68,0x00,0x00,0x00]
+0x05,0x00,0x8f,0xd5,0x68,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_f64_e64 v5, vcc               ; encoding: [0x05,0x00,0x8f,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0x8f,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_f64_e64 v5, ttmp[14:15]       ; encoding: [0x05,0x00,0x8f,0xd5,0x7a,0x00,0x00,0x00]
+0x05,0x00,0x8f,0xd5,0x7a,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_f64_e64 v5, exec              ; encoding: [0x05,0x00,0x8f,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0x8f,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_f64_e64 v5, null              ; encoding: [0x05,0x00,0x8f,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0x8f,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_f64_e64 v5, -1                ; encoding: [0x05,0x00,0x8f,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0x8f,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_f64_e64 v5, 0.5 mul:2         ; encoding: [0x05,0x00,0x8f,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0x8f,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_cvt_f32_f64_e64 v5, -|src_scc| mul:4  ; encoding: [0x05,0x01,0x8f,0xd5,0xfd,0x00,0x00,0x30]
+0x05,0x01,0x8f,0xd5,0xfd,0x00,0x00,0x30
+
+# GFX12: v_cvt_f32_f64_e64 v255, 0xaf123456 clamp div:2 ; encoding: [0xff,0x80,0x8f,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+0xff,0x80,0x8f,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_f32_i32_e64 v5, v1                ; encoding: [0x05,0x00,0x85,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0x85,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cvt_f32_i32_e64 v5, v255              ; encoding: [0x05,0x00,0x85,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0x85,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_cvt_f32_i32_e64 v5, s1                ; encoding: [0x05,0x00,0x85,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0x85,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_i32_e64 v5, s105              ; encoding: [0x05,0x00,0x85,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0x85,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_i32_e64 v5, vcc_lo            ; encoding: [0x05,0x00,0x85,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0x85,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_i32_e64 v5, vcc_hi            ; encoding: [0x05,0x00,0x85,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0x85,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_i32_e64 v5, ttmp15            ; encoding: [0x05,0x00,0x85,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0x85,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_i32_e64 v5, m0                ; encoding: [0x05,0x00,0x85,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0x85,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_i32_e64 v5, exec_lo           ; encoding: [0x05,0x00,0x85,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0x85,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_i32_e64 v5, exec_hi           ; encoding: [0x05,0x00,0x85,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0x85,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_i32_e64 v5, null              ; encoding: [0x05,0x00,0x85,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0x85,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_i32_e64 v5, -1                ; encoding: [0x05,0x00,0x85,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0x85,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_i32_e64 v5, 0.5 mul:2         ; encoding: [0x05,0x00,0x85,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0x85,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_cvt_f32_i32_e64 v5, src_scc mul:4     ; encoding: [0x05,0x00,0x85,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0x85,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_cvt_f32_i32_e64 v255, 0xaf123456 clamp div:2 ; encoding: [0xff,0x80,0x85,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+0xff,0x80,0x85,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_f32_u32_e64 v5, v1                ; encoding: [0x05,0x00,0x86,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0x86,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cvt_f32_u32_e64 v5, v255              ; encoding: [0x05,0x00,0x86,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0x86,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_cvt_f32_u32_e64 v5, s1                ; encoding: [0x05,0x00,0x86,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0x86,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_u32_e64 v5, s105              ; encoding: [0x05,0x00,0x86,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0x86,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_u32_e64 v5, vcc_lo            ; encoding: [0x05,0x00,0x86,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0x86,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_u32_e64 v5, vcc_hi            ; encoding: [0x05,0x00,0x86,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0x86,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_u32_e64 v5, ttmp15            ; encoding: [0x05,0x00,0x86,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0x86,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_u32_e64 v5, m0                ; encoding: [0x05,0x00,0x86,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0x86,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_u32_e64 v5, exec_lo           ; encoding: [0x05,0x00,0x86,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0x86,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_u32_e64 v5, exec_hi           ; encoding: [0x05,0x00,0x86,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0x86,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_u32_e64 v5, null              ; encoding: [0x05,0x00,0x86,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0x86,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_u32_e64 v5, -1                ; encoding: [0x05,0x00,0x86,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0x86,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_u32_e64 v5, 0.5 mul:2         ; encoding: [0x05,0x00,0x86,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0x86,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_cvt_f32_u32_e64 v5, src_scc mul:4     ; encoding: [0x05,0x00,0x86,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0x86,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_cvt_f32_u32_e64 v255, 0xaf123456 clamp div:2 ; encoding: [0xff,0x80,0x86,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+0xff,0x80,0x86,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_f32_ubyte0_e64 v5, v1             ; encoding: [0x05,0x00,0x91,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0x91,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte0_e64 v5, v255           ; encoding: [0x05,0x00,0x91,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0x91,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte0_e64 v5, s1             ; encoding: [0x05,0x00,0x91,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0x91,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte0_e64 v5, s105           ; encoding: [0x05,0x00,0x91,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0x91,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte0_e64 v5, vcc_lo         ; encoding: [0x05,0x00,0x91,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0x91,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte0_e64 v5, vcc_hi         ; encoding: [0x05,0x00,0x91,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0x91,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte0_e64 v5, ttmp15         ; encoding: [0x05,0x00,0x91,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0x91,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte0_e64 v5, m0             ; encoding: [0x05,0x00,0x91,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0x91,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte0_e64 v5, exec_lo        ; encoding: [0x05,0x00,0x91,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0x91,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte0_e64 v5, exec_hi        ; encoding: [0x05,0x00,0x91,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0x91,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte0_e64 v5, null           ; encoding: [0x05,0x00,0x91,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0x91,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte0_e64 v5, -1             ; encoding: [0x05,0x00,0x91,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0x91,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte0_e64 v5, 0.5 mul:2      ; encoding: [0x05,0x00,0x91,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0x91,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_cvt_f32_ubyte0_e64 v5, src_scc mul:4  ; encoding: [0x05,0x00,0x91,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0x91,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_cvt_f32_ubyte0_e64 v255, 0xaf123456 clamp div:2 ; encoding: [0xff,0x80,0x91,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+0xff,0x80,0x91,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_f32_ubyte1_e64 v5, v1             ; encoding: [0x05,0x00,0x92,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0x92,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte1_e64 v5, v255           ; encoding: [0x05,0x00,0x92,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0x92,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte1_e64 v5, s1             ; encoding: [0x05,0x00,0x92,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0x92,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte1_e64 v5, s105           ; encoding: [0x05,0x00,0x92,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0x92,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte1_e64 v5, vcc_lo         ; encoding: [0x05,0x00,0x92,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0x92,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte1_e64 v5, vcc_hi         ; encoding: [0x05,0x00,0x92,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0x92,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte1_e64 v5, ttmp15         ; encoding: [0x05,0x00,0x92,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0x92,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte1_e64 v5, m0             ; encoding: [0x05,0x00,0x92,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0x92,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte1_e64 v5, exec_lo        ; encoding: [0x05,0x00,0x92,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0x92,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte1_e64 v5, exec_hi        ; encoding: [0x05,0x00,0x92,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0x92,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte1_e64 v5, null           ; encoding: [0x05,0x00,0x92,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0x92,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte1_e64 v5, -1             ; encoding: [0x05,0x00,0x92,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0x92,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte1_e64 v5, 0.5 mul:2      ; encoding: [0x05,0x00,0x92,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0x92,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_cvt_f32_ubyte1_e64 v5, src_scc mul:4  ; encoding: [0x05,0x00,0x92,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0x92,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_cvt_f32_ubyte1_e64 v255, 0xaf123456 clamp div:2 ; encoding: [0xff,0x80,0x92,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+0xff,0x80,0x92,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_f32_ubyte2_e64 v5, v1             ; encoding: [0x05,0x00,0x93,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0x93,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte2_e64 v5, v255           ; encoding: [0x05,0x00,0x93,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0x93,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte2_e64 v5, s1             ; encoding: [0x05,0x00,0x93,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0x93,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte2_e64 v5, s105           ; encoding: [0x05,0x00,0x93,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0x93,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte2_e64 v5, vcc_lo         ; encoding: [0x05,0x00,0x93,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0x93,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte2_e64 v5, vcc_hi         ; encoding: [0x05,0x00,0x93,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0x93,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte2_e64 v5, ttmp15         ; encoding: [0x05,0x00,0x93,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0x93,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte2_e64 v5, m0             ; encoding: [0x05,0x00,0x93,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0x93,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte2_e64 v5, exec_lo        ; encoding: [0x05,0x00,0x93,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0x93,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte2_e64 v5, exec_hi        ; encoding: [0x05,0x00,0x93,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0x93,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte2_e64 v5, null           ; encoding: [0x05,0x00,0x93,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0x93,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte2_e64 v5, -1             ; encoding: [0x05,0x00,0x93,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0x93,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte2_e64 v5, 0.5 mul:2      ; encoding: [0x05,0x00,0x93,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0x93,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_cvt_f32_ubyte2_e64 v5, src_scc mul:4  ; encoding: [0x05,0x00,0x93,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0x93,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_cvt_f32_ubyte2_e64 v255, 0xaf123456 clamp div:2 ; encoding: [0xff,0x80,0x93,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+0xff,0x80,0x93,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_f32_ubyte3_e64 v5, v1             ; encoding: [0x05,0x00,0x94,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0x94,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte3_e64 v5, v255           ; encoding: [0x05,0x00,0x94,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0x94,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte3_e64 v5, s1             ; encoding: [0x05,0x00,0x94,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0x94,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte3_e64 v5, s105           ; encoding: [0x05,0x00,0x94,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0x94,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte3_e64 v5, vcc_lo         ; encoding: [0x05,0x00,0x94,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0x94,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte3_e64 v5, vcc_hi         ; encoding: [0x05,0x00,0x94,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0x94,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte3_e64 v5, ttmp15         ; encoding: [0x05,0x00,0x94,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0x94,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte3_e64 v5, m0             ; encoding: [0x05,0x00,0x94,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0x94,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte3_e64 v5, exec_lo        ; encoding: [0x05,0x00,0x94,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0x94,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte3_e64 v5, exec_hi        ; encoding: [0x05,0x00,0x94,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0x94,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte3_e64 v5, null           ; encoding: [0x05,0x00,0x94,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0x94,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte3_e64 v5, -1             ; encoding: [0x05,0x00,0x94,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0x94,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte3_e64 v5, 0.5 mul:2      ; encoding: [0x05,0x00,0x94,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0x94,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_cvt_f32_ubyte3_e64 v5, src_scc mul:4  ; encoding: [0x05,0x00,0x94,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0x94,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_cvt_f32_ubyte3_e64 v255, 0xaf123456 clamp div:2 ; encoding: [0xff,0x80,0x94,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+0xff,0x80,0x94,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_f64_f32_e64 v[5:6], v1            ; encoding: [0x05,0x00,0x90,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0x90,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cvt_f64_f32_e64 v[5:6], v255          ; encoding: [0x05,0x00,0x90,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0x90,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_cvt_f64_f32_e64 v[5:6], s1            ; encoding: [0x05,0x00,0x90,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0x90,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_f32_e64 v[5:6], s105          ; encoding: [0x05,0x00,0x90,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0x90,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_f32_e64 v[5:6], vcc_lo        ; encoding: [0x05,0x00,0x90,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0x90,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_f32_e64 v[5:6], vcc_hi        ; encoding: [0x05,0x00,0x90,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0x90,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_f32_e64 v[5:6], ttmp15        ; encoding: [0x05,0x00,0x90,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0x90,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_f32_e64 v[5:6], m0            ; encoding: [0x05,0x00,0x90,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0x90,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_f32_e64 v[5:6], exec_lo       ; encoding: [0x05,0x00,0x90,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0x90,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_f32_e64 v[5:6], exec_hi       ; encoding: [0x05,0x00,0x90,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0x90,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_f32_e64 v[5:6], null          ; encoding: [0x05,0x00,0x90,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0x90,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_f32_e64 v[5:6], -1            ; encoding: [0x05,0x00,0x90,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0x90,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_f32_e64 v[5:6], 0.5 mul:2     ; encoding: [0x05,0x00,0x90,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0x90,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_cvt_f64_f32_e64 v[5:6], src_scc mul:4 ; encoding: [0x05,0x00,0x90,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0x90,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_cvt_f64_f32_e64 v[254:255], -|0xaf123456| clamp div:2 ; encoding: [0xfe,0x81,0x90,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+0xfe,0x81,0x90,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_f64_i32_e64 v[5:6], v1            ; encoding: [0x05,0x00,0x84,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0x84,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cvt_f64_i32_e64 v[5:6], v255          ; encoding: [0x05,0x00,0x84,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0x84,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_cvt_f64_i32_e64 v[5:6], s1            ; encoding: [0x05,0x00,0x84,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0x84,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_i32_e64 v[5:6], s105          ; encoding: [0x05,0x00,0x84,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0x84,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_i32_e64 v[5:6], vcc_lo        ; encoding: [0x05,0x00,0x84,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0x84,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_i32_e64 v[5:6], vcc_hi        ; encoding: [0x05,0x00,0x84,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0x84,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_i32_e64 v[5:6], ttmp15        ; encoding: [0x05,0x00,0x84,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0x84,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_i32_e64 v[5:6], m0            ; encoding: [0x05,0x00,0x84,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0x84,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_i32_e64 v[5:6], exec_lo       ; encoding: [0x05,0x00,0x84,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0x84,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_i32_e64 v[5:6], exec_hi       ; encoding: [0x05,0x00,0x84,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0x84,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_i32_e64 v[5:6], null          ; encoding: [0x05,0x00,0x84,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0x84,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_i32_e64 v[5:6], -1            ; encoding: [0x05,0x00,0x84,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0x84,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_i32_e64 v[5:6], 0.5 mul:2     ; encoding: [0x05,0x00,0x84,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0x84,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_cvt_f64_i32_e64 v[5:6], src_scc mul:4 ; encoding: [0x05,0x00,0x84,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0x84,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_cvt_f64_i32_e64 v[254:255], 0xaf123456 clamp div:2 ; encoding: [0xfe,0x80,0x84,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+0xfe,0x80,0x84,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_f64_u32_e64 v[5:6], v1            ; encoding: [0x05,0x00,0x96,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0x96,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cvt_f64_u32_e64 v[5:6], v255          ; encoding: [0x05,0x00,0x96,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0x96,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_cvt_f64_u32_e64 v[5:6], s1            ; encoding: [0x05,0x00,0x96,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0x96,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_u32_e64 v[5:6], s105          ; encoding: [0x05,0x00,0x96,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0x96,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_u32_e64 v[5:6], vcc_lo        ; encoding: [0x05,0x00,0x96,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0x96,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_u32_e64 v[5:6], vcc_hi        ; encoding: [0x05,0x00,0x96,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0x96,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_u32_e64 v[5:6], ttmp15        ; encoding: [0x05,0x00,0x96,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0x96,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_u32_e64 v[5:6], m0            ; encoding: [0x05,0x00,0x96,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0x96,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_u32_e64 v[5:6], exec_lo       ; encoding: [0x05,0x00,0x96,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0x96,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_u32_e64 v[5:6], exec_hi       ; encoding: [0x05,0x00,0x96,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0x96,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_u32_e64 v[5:6], null          ; encoding: [0x05,0x00,0x96,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0x96,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_u32_e64 v[5:6], -1            ; encoding: [0x05,0x00,0x96,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0x96,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cvt_f64_u32_e64 v[5:6], 0.5 mul:2     ; encoding: [0x05,0x00,0x96,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0x96,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_cvt_f64_u32_e64 v[5:6], src_scc mul:4 ; encoding: [0x05,0x00,0x96,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0x96,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_cvt_f64_u32_e64 v[254:255], 0xaf123456 clamp div:2 ; encoding: [0xfe,0x80,0x96,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+0xfe,0x80,0x96,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_floor_i32_f32_e64 v5, v1          ; encoding: [0x05,0x00,0x8d,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0x8d,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cvt_floor_i32_f32_e64 v5, v255        ; encoding: [0x05,0x00,0x8d,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0x8d,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_cvt_floor_i32_f32_e64 v5, s1          ; encoding: [0x05,0x00,0x8d,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0x8d,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_cvt_floor_i32_f32_e64 v5, s105        ; encoding: [0x05,0x00,0x8d,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0x8d,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_cvt_floor_i32_f32_e64 v5, vcc_lo      ; encoding: [0x05,0x00,0x8d,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0x8d,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cvt_floor_i32_f32_e64 v5, vcc_hi      ; encoding: [0x05,0x00,0x8d,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0x8d,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_cvt_floor_i32_f32_e64 v5, ttmp15      ; encoding: [0x05,0x00,0x8d,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0x8d,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_cvt_floor_i32_f32_e64 v5, m0          ; encoding: [0x05,0x00,0x8d,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0x8d,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_cvt_floor_i32_f32_e64 v5, exec_lo     ; encoding: [0x05,0x00,0x8d,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0x8d,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cvt_floor_i32_f32_e64 v5, exec_hi     ; encoding: [0x05,0x00,0x8d,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0x8d,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_floor_i32_f32_e64 v5, null        ; encoding: [0x05,0x00,0x8d,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0x8d,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cvt_floor_i32_f32_e64 v5, -1          ; encoding: [0x05,0x00,0x8d,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0x8d,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cvt_floor_i32_f32_e64 v5, 0.5         ; encoding: [0x05,0x00,0x8d,0xd5,0xf0,0x00,0x00,0x00]
+0x05,0x00,0x8d,0xd5,0xf0,0x00,0x00,0x00
+
+# GFX12: v_cvt_floor_i32_f32_e64 v5, src_scc     ; encoding: [0x05,0x00,0x8d,0xd5,0xfd,0x00,0x00,0x00]
+0x05,0x00,0x8d,0xd5,0xfd,0x00,0x00,0x00
+
+# GFX12: v_cvt_floor_i32_f32_e64 v255, -|0xaf123456| ; encoding: [0xff,0x01,0x8d,0xd5,0xff,0x00,0x00,0x20,0x56,0x34,0x12,0xaf]
+0xff,0x01,0x8d,0xd5,0xff,0x00,0x00,0x20,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_i16_f16_e64 v5, v1                ; encoding: [0x05,0x00,0xd3,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xd3,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cvt_i16_f16_e64 v5, v255              ; encoding: [0x05,0x00,0xd3,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xd3,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_cvt_i16_f16_e64 v5, s1                ; encoding: [0x05,0x00,0xd3,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xd3,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_cvt_i16_f16_e64 v5, s105              ; encoding: [0x05,0x00,0xd3,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xd3,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_cvt_i16_f16_e64 v5, vcc_lo            ; encoding: [0x05,0x00,0xd3,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xd3,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cvt_i16_f16_e64 v5, vcc_hi            ; encoding: [0x05,0x00,0xd3,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xd3,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_cvt_i16_f16_e64 v5, ttmp15            ; encoding: [0x05,0x00,0xd3,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xd3,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_cvt_i16_f16_e64 v5, m0                ; encoding: [0x05,0x00,0xd3,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xd3,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_cvt_i16_f16_e64 v5, exec_lo           ; encoding: [0x05,0x00,0xd3,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xd3,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cvt_i16_f16_e64 v5, exec_hi           ; encoding: [0x05,0x00,0xd3,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xd3,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_i16_f16_e64 v5, null              ; encoding: [0x05,0x00,0xd3,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xd3,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cvt_i16_f16_e64 v5, -1                ; encoding: [0x05,0x00,0xd3,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xd3,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cvt_i16_f16_e64 v5, 0.5               ; encoding: [0x05,0x00,0xd3,0xd5,0xf0,0x00,0x00,0x00]
+0x05,0x00,0xd3,0xd5,0xf0,0x00,0x00,0x00
+
+# GFX12: v_cvt_i16_f16_e64 v5, src_scc           ; encoding: [0x05,0x00,0xd3,0xd5,0xfd,0x00,0x00,0x00]
+0x05,0x00,0xd3,0xd5,0xfd,0x00,0x00,0x00
+
+# GFX12: v_cvt_i16_f16_e64 v255, -|0xfe0b| clamp ; encoding: [0xff,0x81,0xd3,0xd5,0xff,0x00,0x00,0x20,0x0b,0xfe,0x00,0x00]
+0xff,0x81,0xd3,0xd5,0xff,0x00,0x00,0x20,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cvt_i32_f32_e64 v5, v1                ; encoding: [0x05,0x00,0x88,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0x88,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cvt_i32_f32_e64 v5, v255              ; encoding: [0x05,0x00,0x88,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0x88,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_cvt_i32_f32_e64 v5, s1                ; encoding: [0x05,0x00,0x88,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0x88,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_f32_e64 v5, s105              ; encoding: [0x05,0x00,0x88,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0x88,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_f32_e64 v5, vcc_lo            ; encoding: [0x05,0x00,0x88,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0x88,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_f32_e64 v5, vcc_hi            ; encoding: [0x05,0x00,0x88,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0x88,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_f32_e64 v5, ttmp15            ; encoding: [0x05,0x00,0x88,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0x88,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_f32_e64 v5, m0                ; encoding: [0x05,0x00,0x88,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0x88,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_f32_e64 v5, exec_lo           ; encoding: [0x05,0x00,0x88,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0x88,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_f32_e64 v5, exec_hi           ; encoding: [0x05,0x00,0x88,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0x88,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_f32_e64 v5, null              ; encoding: [0x05,0x00,0x88,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0x88,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_f32_e64 v5, -1                ; encoding: [0x05,0x00,0x88,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0x88,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_f32_e64 v5, 0.5               ; encoding: [0x05,0x00,0x88,0xd5,0xf0,0x00,0x00,0x00]
+0x05,0x00,0x88,0xd5,0xf0,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_f32_e64 v5, src_scc           ; encoding: [0x05,0x00,0x88,0xd5,0xfd,0x00,0x00,0x00]
+0x05,0x00,0x88,0xd5,0xfd,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_f32_e64 v255, -|0xaf123456| clamp ; encoding: [0xff,0x81,0x88,0xd5,0xff,0x00,0x00,0x20,0x56,0x34,0x12,0xaf]
+0xff,0x81,0x88,0xd5,0xff,0x00,0x00,0x20,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_i32_f64_e64 v5, v[1:2]            ; encoding: [0x05,0x00,0x83,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0x83,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cvt_i32_f64_e64 v5, v[254:255]        ; encoding: [0x05,0x00,0x83,0xd5,0xfe,0x01,0x00,0x00]
+0x05,0x00,0x83,0xd5,0xfe,0x01,0x00,0x00
+
+# GFX12: v_cvt_i32_f64_e64 v5, s[2:3]            ; encoding: [0x05,0x00,0x83,0xd5,0x02,0x00,0x00,0x00]
+0x05,0x00,0x83,0xd5,0x02,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_f64_e64 v5, s[104:105]        ; encoding: [0x05,0x00,0x83,0xd5,0x68,0x00,0x00,0x00]
+0x05,0x00,0x83,0xd5,0x68,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_f64_e64 v5, vcc               ; encoding: [0x05,0x00,0x83,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0x83,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_f64_e64 v5, ttmp[14:15]       ; encoding: [0x05,0x00,0x83,0xd5,0x7a,0x00,0x00,0x00]
+0x05,0x00,0x83,0xd5,0x7a,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_f64_e64 v5, exec              ; encoding: [0x05,0x00,0x83,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0x83,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_f64_e64 v5, null              ; encoding: [0x05,0x00,0x83,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0x83,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_f64_e64 v5, -1                ; encoding: [0x05,0x00,0x83,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0x83,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_f64_e64 v5, 0.5               ; encoding: [0x05,0x00,0x83,0xd5,0xf0,0x00,0x00,0x00]
+0x05,0x00,0x83,0xd5,0xf0,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_f64_e64 v5, -|src_scc|        ; encoding: [0x05,0x01,0x83,0xd5,0xfd,0x00,0x00,0x20]
+0x05,0x01,0x83,0xd5,0xfd,0x00,0x00,0x20
+
+# GFX12: v_cvt_i32_f64_e64 v255, 0xaf123456 clamp ; encoding: [0xff,0x80,0x83,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x80,0x83,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_i32_i16_e64 v5, v1                ; encoding: [0x05,0x00,0xea,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xea,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cvt_i32_i16_e64 v5, v255              ; encoding: [0x05,0x00,0xea,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xea,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_cvt_i32_i16_e64 v5, s1                ; encoding: [0x05,0x00,0xea,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xea,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_i16_e64 v5, s105              ; encoding: [0x05,0x00,0xea,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xea,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_i16_e64 v5, vcc_lo            ; encoding: [0x05,0x00,0xea,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xea,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_i16_e64 v5, vcc_hi            ; encoding: [0x05,0x00,0xea,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xea,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_i16_e64 v5, ttmp15            ; encoding: [0x05,0x00,0xea,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xea,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_i16_e64 v5, m0                ; encoding: [0x05,0x00,0xea,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xea,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_i16_e64 v5, exec_lo           ; encoding: [0x05,0x00,0xea,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xea,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_i16_e64 v5, exec_hi           ; encoding: [0x05,0x00,0xea,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xea,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_i16_e64 v5, null              ; encoding: [0x05,0x00,0xea,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xea,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_i16_e64 v5, -1                ; encoding: [0x05,0x00,0xea,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xea,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_i16_e64 v5, 0x3800
+0x05,0x00,0xea,0xd5,0xf0,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_i16_e64 v5, src_scc           ; encoding: [0x05,0x00,0xea,0xd5,0xfd,0x00,0x00,0x00]
+0x05,0x00,0xea,0xd5,0xfd,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_i16_e64 v255, 0xfe0b          ; encoding: [0xff,0x00,0xea,0xd5,0xff,0x00,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0xff,0x00,0xea,0xd5,0xff,0x00,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cvt_nearest_i32_f32_e64 v5, v1        ; encoding: [0x05,0x00,0x8c,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0x8c,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cvt_nearest_i32_f32_e64 v5, v255      ; encoding: [0x05,0x00,0x8c,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0x8c,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_cvt_nearest_i32_f32_e64 v5, s1        ; encoding: [0x05,0x00,0x8c,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0x8c,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_cvt_nearest_i32_f32_e64 v5, s105      ; encoding: [0x05,0x00,0x8c,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0x8c,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_cvt_nearest_i32_f32_e64 v5, vcc_lo    ; encoding: [0x05,0x00,0x8c,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0x8c,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cvt_nearest_i32_f32_e64 v5, vcc_hi    ; encoding: [0x05,0x00,0x8c,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0x8c,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_cvt_nearest_i32_f32_e64 v5, ttmp15    ; encoding: [0x05,0x00,0x8c,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0x8c,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_cvt_nearest_i32_f32_e64 v5, m0        ; encoding: [0x05,0x00,0x8c,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0x8c,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_cvt_nearest_i32_f32_e64 v5, exec_lo   ; encoding: [0x05,0x00,0x8c,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0x8c,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cvt_nearest_i32_f32_e64 v5, exec_hi   ; encoding: [0x05,0x00,0x8c,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0x8c,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_nearest_i32_f32_e64 v5, null      ; encoding: [0x05,0x00,0x8c,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0x8c,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cvt_nearest_i32_f32_e64 v5, -1        ; encoding: [0x05,0x00,0x8c,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0x8c,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cvt_nearest_i32_f32_e64 v5, 0.5       ; encoding: [0x05,0x00,0x8c,0xd5,0xf0,0x00,0x00,0x00]
+0x05,0x00,0x8c,0xd5,0xf0,0x00,0x00,0x00
+
+# GFX12: v_cvt_nearest_i32_f32_e64 v5, src_scc   ; encoding: [0x05,0x00,0x8c,0xd5,0xfd,0x00,0x00,0x00]
+0x05,0x00,0x8c,0xd5,0xfd,0x00,0x00,0x00
+
+# GFX12: v_cvt_nearest_i32_f32_e64 v255, -|0xaf123456| ; encoding: [0xff,0x01,0x8c,0xd5,0xff,0x00,0x00,0x20,0x56,0x34,0x12,0xaf]
+0xff,0x01,0x8c,0xd5,0xff,0x00,0x00,0x20,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_norm_i16_f16_e64 v5, v1           ; encoding: [0x05,0x00,0xe3,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xe3,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cvt_norm_i16_f16_e64 v5, v255         ; encoding: [0x05,0x00,0xe3,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xe3,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_cvt_norm_i16_f16_e64 v5, s1           ; encoding: [0x05,0x00,0xe3,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xe3,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_cvt_norm_i16_f16_e64 v5, s105         ; encoding: [0x05,0x00,0xe3,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xe3,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_cvt_norm_i16_f16_e64 v5, vcc_lo       ; encoding: [0x05,0x00,0xe3,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xe3,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cvt_norm_i16_f16_e64 v5, vcc_hi       ; encoding: [0x05,0x00,0xe3,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xe3,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_cvt_norm_i16_f16_e64 v5, ttmp15       ; encoding: [0x05,0x00,0xe3,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xe3,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_cvt_norm_i16_f16_e64 v5, m0           ; encoding: [0x05,0x00,0xe3,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xe3,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_cvt_norm_i16_f16_e64 v5, exec_lo      ; encoding: [0x05,0x00,0xe3,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xe3,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cvt_norm_i16_f16_e64 v5, exec_hi      ; encoding: [0x05,0x00,0xe3,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xe3,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_norm_i16_f16_e64 v5, null         ; encoding: [0x05,0x00,0xe3,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xe3,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cvt_norm_i16_f16_e64 v5, -1           ; encoding: [0x05,0x00,0xe3,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xe3,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cvt_norm_i16_f16_e64 v5, 0.5          ; encoding: [0x05,0x00,0xe3,0xd5,0xf0,0x00,0x00,0x00]
+0x05,0x00,0xe3,0xd5,0xf0,0x00,0x00,0x00
+
+# GFX12: v_cvt_norm_i16_f16_e64 v5, src_scc      ; encoding: [0x05,0x00,0xe3,0xd5,0xfd,0x00,0x00,0x00]
+0x05,0x00,0xe3,0xd5,0xfd,0x00,0x00,0x00
+
+# GFX12: v_cvt_norm_i16_f16_e64 v255, -|0xfe0b|  ; encoding: [0xff,0x01,0xe3,0xd5,0xff,0x00,0x00,0x20,0x0b,0xfe,0x00,0x00]
+0xff,0x01,0xe3,0xd5,0xff,0x00,0x00,0x20,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cvt_norm_u16_f16_e64 v5, v1           ; encoding: [0x05,0x00,0xe4,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xe4,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cvt_norm_u16_f16_e64 v5, v255         ; encoding: [0x05,0x00,0xe4,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xe4,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_cvt_norm_u16_f16_e64 v5, s1           ; encoding: [0x05,0x00,0xe4,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xe4,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_cvt_norm_u16_f16_e64 v5, s105         ; encoding: [0x05,0x00,0xe4,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xe4,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_cvt_norm_u16_f16_e64 v5, vcc_lo       ; encoding: [0x05,0x00,0xe4,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xe4,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cvt_norm_u16_f16_e64 v5, vcc_hi       ; encoding: [0x05,0x00,0xe4,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xe4,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_cvt_norm_u16_f16_e64 v5, ttmp15       ; encoding: [0x05,0x00,0xe4,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xe4,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_cvt_norm_u16_f16_e64 v5, m0           ; encoding: [0x05,0x00,0xe4,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xe4,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_cvt_norm_u16_f16_e64 v5, exec_lo      ; encoding: [0x05,0x00,0xe4,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xe4,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cvt_norm_u16_f16_e64 v5, exec_hi      ; encoding: [0x05,0x00,0xe4,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xe4,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_norm_u16_f16_e64 v5, null         ; encoding: [0x05,0x00,0xe4,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xe4,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cvt_norm_u16_f16_e64 v5, -1           ; encoding: [0x05,0x00,0xe4,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xe4,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cvt_norm_u16_f16_e64 v5, 0.5          ; encoding: [0x05,0x00,0xe4,0xd5,0xf0,0x00,0x00,0x00]
+0x05,0x00,0xe4,0xd5,0xf0,0x00,0x00,0x00
+
+# GFX12: v_cvt_norm_u16_f16_e64 v5, src_scc      ; encoding: [0x05,0x00,0xe4,0xd5,0xfd,0x00,0x00,0x00]
+0x05,0x00,0xe4,0xd5,0xfd,0x00,0x00,0x00
+
+# GFX12: v_cvt_norm_u16_f16_e64 v255, -|0xfe0b|  ; encoding: [0xff,0x01,0xe4,0xd5,0xff,0x00,0x00,0x20,0x0b,0xfe,0x00,0x00]
+0xff,0x01,0xe4,0xd5,0xff,0x00,0x00,0x20,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cvt_off_f32_i4_e64 v5, v1             ; encoding: [0x05,0x00,0x8e,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0x8e,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cvt_off_f32_i4_e64 v5, v255           ; encoding: [0x05,0x00,0x8e,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0x8e,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_cvt_off_f32_i4_e64 v5, s1             ; encoding: [0x05,0x00,0x8e,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0x8e,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_cvt_off_f32_i4_e64 v5, s105           ; encoding: [0x05,0x00,0x8e,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0x8e,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_cvt_off_f32_i4_e64 v5, vcc_lo         ; encoding: [0x05,0x00,0x8e,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0x8e,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cvt_off_f32_i4_e64 v5, vcc_hi         ; encoding: [0x05,0x00,0x8e,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0x8e,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_cvt_off_f32_i4_e64 v5, ttmp15         ; encoding: [0x05,0x00,0x8e,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0x8e,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_cvt_off_f32_i4_e64 v5, m0             ; encoding: [0x05,0x00,0x8e,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0x8e,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_cvt_off_f32_i4_e64 v5, exec_lo        ; encoding: [0x05,0x00,0x8e,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0x8e,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cvt_off_f32_i4_e64 v5, exec_hi        ; encoding: [0x05,0x00,0x8e,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0x8e,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_off_f32_i4_e64 v5, null           ; encoding: [0x05,0x00,0x8e,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0x8e,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cvt_off_f32_i4_e64 v5, -1             ; encoding: [0x05,0x00,0x8e,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0x8e,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cvt_off_f32_i4_e64 v5, 0.5 mul:2      ; encoding: [0x05,0x00,0x8e,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0x8e,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_cvt_off_f32_i4_e64 v5, src_scc mul:4  ; encoding: [0x05,0x00,0x8e,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0x8e,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_cvt_off_f32_i4_e64 v255, 0x4f clamp div:2 ; encoding: [0xff,0x80,0x8e,0xd5,0xff,0x00,0x00,0x18,0x4f,0x00,0x00,0x00]
+0xff,0x80,0x8e,0xd5,0xff,0x00,0x00,0x18,0x4f,0x00,0x00,0x00
+
+# GFX12: v_cvt_u16_f16_e64 v5, v1                ; encoding: [0x05,0x00,0xd2,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xd2,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cvt_u16_f16_e64 v5, v255              ; encoding: [0x05,0x00,0xd2,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xd2,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_cvt_u16_f16_e64 v5, s1                ; encoding: [0x05,0x00,0xd2,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xd2,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_cvt_u16_f16_e64 v5, s105              ; encoding: [0x05,0x00,0xd2,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xd2,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_cvt_u16_f16_e64 v5, vcc_lo            ; encoding: [0x05,0x00,0xd2,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xd2,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cvt_u16_f16_e64 v5, vcc_hi            ; encoding: [0x05,0x00,0xd2,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xd2,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_cvt_u16_f16_e64 v5, ttmp15            ; encoding: [0x05,0x00,0xd2,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xd2,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_cvt_u16_f16_e64 v5, m0                ; encoding: [0x05,0x00,0xd2,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xd2,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_cvt_u16_f16_e64 v5, exec_lo           ; encoding: [0x05,0x00,0xd2,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xd2,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cvt_u16_f16_e64 v5, exec_hi           ; encoding: [0x05,0x00,0xd2,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xd2,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_u16_f16_e64 v5, null              ; encoding: [0x05,0x00,0xd2,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xd2,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cvt_u16_f16_e64 v5, -1                ; encoding: [0x05,0x00,0xd2,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xd2,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cvt_u16_f16_e64 v5, 0.5               ; encoding: [0x05,0x00,0xd2,0xd5,0xf0,0x00,0x00,0x00]
+0x05,0x00,0xd2,0xd5,0xf0,0x00,0x00,0x00
+
+# GFX12: v_cvt_u16_f16_e64 v5, src_scc           ; encoding: [0x05,0x00,0xd2,0xd5,0xfd,0x00,0x00,0x00]
+0x05,0x00,0xd2,0xd5,0xfd,0x00,0x00,0x00
+
+# GFX12: v_cvt_u16_f16_e64 v255, -|0xfe0b| clamp ; encoding: [0xff,0x81,0xd2,0xd5,0xff,0x00,0x00,0x20,0x0b,0xfe,0x00,0x00]
+0xff,0x81,0xd2,0xd5,0xff,0x00,0x00,0x20,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cvt_u32_f32_e64 v5, v1                ; encoding: [0x05,0x00,0x87,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0x87,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cvt_u32_f32_e64 v5, v255              ; encoding: [0x05,0x00,0x87,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0x87,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_cvt_u32_f32_e64 v5, s1                ; encoding: [0x05,0x00,0x87,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0x87,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_f32_e64 v5, s105              ; encoding: [0x05,0x00,0x87,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0x87,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_f32_e64 v5, vcc_lo            ; encoding: [0x05,0x00,0x87,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0x87,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_f32_e64 v5, vcc_hi            ; encoding: [0x05,0x00,0x87,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0x87,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_f32_e64 v5, ttmp15            ; encoding: [0x05,0x00,0x87,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0x87,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_f32_e64 v5, m0                ; encoding: [0x05,0x00,0x87,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0x87,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_f32_e64 v5, exec_lo           ; encoding: [0x05,0x00,0x87,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0x87,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_f32_e64 v5, exec_hi           ; encoding: [0x05,0x00,0x87,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0x87,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_f32_e64 v5, null              ; encoding: [0x05,0x00,0x87,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0x87,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_f32_e64 v5, -1                ; encoding: [0x05,0x00,0x87,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0x87,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_f32_e64 v5, 0.5               ; encoding: [0x05,0x00,0x87,0xd5,0xf0,0x00,0x00,0x00]
+0x05,0x00,0x87,0xd5,0xf0,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_f32_e64 v5, src_scc           ; encoding: [0x05,0x00,0x87,0xd5,0xfd,0x00,0x00,0x00]
+0x05,0x00,0x87,0xd5,0xfd,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_f32_e64 v255, -|0xaf123456| clamp ; encoding: [0xff,0x81,0x87,0xd5,0xff,0x00,0x00,0x20,0x56,0x34,0x12,0xaf]
+0xff,0x81,0x87,0xd5,0xff,0x00,0x00,0x20,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_u32_f64_e64 v5, v[1:2]            ; encoding: [0x05,0x00,0x95,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0x95,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cvt_u32_f64_e64 v5, v[254:255]        ; encoding: [0x05,0x00,0x95,0xd5,0xfe,0x01,0x00,0x00]
+0x05,0x00,0x95,0xd5,0xfe,0x01,0x00,0x00
+
+# GFX12: v_cvt_u32_f64_e64 v5, s[2:3]            ; encoding: [0x05,0x00,0x95,0xd5,0x02,0x00,0x00,0x00]
+0x05,0x00,0x95,0xd5,0x02,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_f64_e64 v5, s[104:105]        ; encoding: [0x05,0x00,0x95,0xd5,0x68,0x00,0x00,0x00]
+0x05,0x00,0x95,0xd5,0x68,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_f64_e64 v5, vcc               ; encoding: [0x05,0x00,0x95,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0x95,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_f64_e64 v5, ttmp[14:15]       ; encoding: [0x05,0x00,0x95,0xd5,0x7a,0x00,0x00,0x00]
+0x05,0x00,0x95,0xd5,0x7a,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_f64_e64 v5, exec              ; encoding: [0x05,0x00,0x95,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0x95,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_f64_e64 v5, null              ; encoding: [0x05,0x00,0x95,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0x95,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_f64_e64 v5, -1                ; encoding: [0x05,0x00,0x95,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0x95,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_f64_e64 v5, 0.5               ; encoding: [0x05,0x00,0x95,0xd5,0xf0,0x00,0x00,0x00]
+0x05,0x00,0x95,0xd5,0xf0,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_f64_e64 v5, -|src_scc|        ; encoding: [0x05,0x01,0x95,0xd5,0xfd,0x00,0x00,0x20]
+0x05,0x01,0x95,0xd5,0xfd,0x00,0x00,0x20
+
+# GFX12: v_cvt_u32_f64_e64 v255, 0xaf123456 clamp ; encoding: [0xff,0x80,0x95,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x80,0x95,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_u32_u16_e64 v5, v1                ; encoding: [0x05,0x00,0xeb,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xeb,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_cvt_u32_u16_e64 v5, v255              ; encoding: [0x05,0x00,0xeb,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xeb,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_cvt_u32_u16_e64 v5, s1                ; encoding: [0x05,0x00,0xeb,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xeb,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_u16_e64 v5, s105              ; encoding: [0x05,0x00,0xeb,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xeb,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_u16_e64 v5, vcc_lo            ; encoding: [0x05,0x00,0xeb,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xeb,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_u16_e64 v5, vcc_hi            ; encoding: [0x05,0x00,0xeb,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xeb,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_u16_e64 v5, ttmp15            ; encoding: [0x05,0x00,0xeb,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xeb,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_u16_e64 v5, m0                ; encoding: [0x05,0x00,0xeb,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xeb,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_u16_e64 v5, exec_lo           ; encoding: [0x05,0x00,0xeb,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xeb,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_u16_e64 v5, exec_hi           ; encoding: [0x05,0x00,0xeb,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xeb,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_u16_e64 v5, null              ; encoding: [0x05,0x00,0xeb,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xeb,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_u16_e64 v5, -1                ; encoding: [0x05,0x00,0xeb,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xeb,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_u16_e64 v5, 0x3800
+0x05,0x00,0xeb,0xd5,0xf0,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_u16_e64 v5, src_scc           ; encoding: [0x05,0x00,0xeb,0xd5,0xfd,0x00,0x00,0x00]
+0x05,0x00,0xeb,0xd5,0xfd,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_u16_e64 v255, 0xfe0b          ; encoding: [0xff,0x00,0xeb,0xd5,0xff,0x00,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0xff,0x00,0xeb,0xd5,0xff,0x00,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_exp_f16_e64 v5, v1                    ; encoding: [0x05,0x00,0xd8,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xd8,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_exp_f16_e64 v5, v255                  ; encoding: [0x05,0x00,0xd8,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xd8,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_exp_f16_e64 v5, s1                    ; encoding: [0x05,0x00,0xd8,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xd8,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_exp_f16_e64 v5, s105                  ; encoding: [0x05,0x00,0xd8,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xd8,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_exp_f16_e64 v5, vcc_lo                ; encoding: [0x05,0x00,0xd8,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xd8,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_exp_f16_e64 v5, vcc_hi                ; encoding: [0x05,0x00,0xd8,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xd8,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_exp_f16_e64 v5, ttmp15                ; encoding: [0x05,0x00,0xd8,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xd8,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_exp_f16_e64 v5, m0                    ; encoding: [0x05,0x00,0xd8,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xd8,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_exp_f16_e64 v5, exec_lo               ; encoding: [0x05,0x00,0xd8,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xd8,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_exp_f16_e64 v5, exec_hi               ; encoding: [0x05,0x00,0xd8,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xd8,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_exp_f16_e64 v5, null                  ; encoding: [0x05,0x00,0xd8,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xd8,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_exp_f16_e64 v5, -1                    ; encoding: [0x05,0x00,0xd8,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xd8,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_exp_f16_e64 v5, 0.5 mul:2             ; encoding: [0x05,0x00,0xd8,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xd8,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_exp_f16_e64 v5, src_scc mul:4         ; encoding: [0x05,0x00,0xd8,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xd8,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_exp_f16_e64 v255, -|0xfe0b| clamp div:2 ; encoding: [0xff,0x81,0xd8,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00]
+0xff,0x81,0xd8,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_exp_f32_e64 v5, v1                    ; encoding: [0x05,0x00,0xa5,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xa5,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_exp_f32_e64 v5, v255                  ; encoding: [0x05,0x00,0xa5,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xa5,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_exp_f32_e64 v5, s1                    ; encoding: [0x05,0x00,0xa5,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xa5,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_exp_f32_e64 v5, s105                  ; encoding: [0x05,0x00,0xa5,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xa5,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_exp_f32_e64 v5, vcc_lo                ; encoding: [0x05,0x00,0xa5,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xa5,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_exp_f32_e64 v5, vcc_hi                ; encoding: [0x05,0x00,0xa5,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xa5,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_exp_f32_e64 v5, ttmp15                ; encoding: [0x05,0x00,0xa5,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xa5,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_exp_f32_e64 v5, m0                    ; encoding: [0x05,0x00,0xa5,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xa5,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_exp_f32_e64 v5, exec_lo               ; encoding: [0x05,0x00,0xa5,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xa5,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_exp_f32_e64 v5, exec_hi               ; encoding: [0x05,0x00,0xa5,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xa5,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_exp_f32_e64 v5, null                  ; encoding: [0x05,0x00,0xa5,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xa5,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_exp_f32_e64 v5, -1                    ; encoding: [0x05,0x00,0xa5,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xa5,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_exp_f32_e64 v5, 0.5 mul:2             ; encoding: [0x05,0x00,0xa5,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xa5,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_exp_f32_e64 v5, src_scc mul:4         ; encoding: [0x05,0x00,0xa5,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xa5,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_exp_f32_e64 v255, -|0xaf123456| clamp div:2 ; encoding: [0xff,0x81,0xa5,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+0xff,0x81,0xa5,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf
+
+# GFX12: v_floor_f16_e64 v5, v1                  ; encoding: [0x05,0x00,0xdb,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xdb,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_floor_f16_e64 v5, v255                ; encoding: [0x05,0x00,0xdb,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xdb,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_floor_f16_e64 v5, s1                  ; encoding: [0x05,0x00,0xdb,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xdb,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_floor_f16_e64 v5, s105                ; encoding: [0x05,0x00,0xdb,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xdb,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_floor_f16_e64 v5, vcc_lo              ; encoding: [0x05,0x00,0xdb,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xdb,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_floor_f16_e64 v5, vcc_hi              ; encoding: [0x05,0x00,0xdb,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xdb,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_floor_f16_e64 v5, ttmp15              ; encoding: [0x05,0x00,0xdb,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xdb,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_floor_f16_e64 v5, m0                  ; encoding: [0x05,0x00,0xdb,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xdb,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_floor_f16_e64 v5, exec_lo             ; encoding: [0x05,0x00,0xdb,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xdb,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_floor_f16_e64 v5, exec_hi             ; encoding: [0x05,0x00,0xdb,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xdb,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_floor_f16_e64 v5, null                ; encoding: [0x05,0x00,0xdb,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xdb,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_floor_f16_e64 v5, -1                  ; encoding: [0x05,0x00,0xdb,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xdb,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_floor_f16_e64 v5, 0.5 mul:2           ; encoding: [0x05,0x00,0xdb,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xdb,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_floor_f16_e64 v5, src_scc mul:4       ; encoding: [0x05,0x00,0xdb,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xdb,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_floor_f16_e64 v255, -|0xfe0b| clamp div:2 ; encoding: [0xff,0x81,0xdb,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00]
+0xff,0x81,0xdb,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_floor_f32_e64 v5, v1                  ; encoding: [0x05,0x00,0xa4,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xa4,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_floor_f32_e64 v5, v255                ; encoding: [0x05,0x00,0xa4,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xa4,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_floor_f32_e64 v5, s1                  ; encoding: [0x05,0x00,0xa4,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xa4,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_floor_f32_e64 v5, s105                ; encoding: [0x05,0x00,0xa4,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xa4,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_floor_f32_e64 v5, vcc_lo              ; encoding: [0x05,0x00,0xa4,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xa4,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_floor_f32_e64 v5, vcc_hi              ; encoding: [0x05,0x00,0xa4,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xa4,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_floor_f32_e64 v5, ttmp15              ; encoding: [0x05,0x00,0xa4,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xa4,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_floor_f32_e64 v5, m0                  ; encoding: [0x05,0x00,0xa4,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xa4,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_floor_f32_e64 v5, exec_lo             ; encoding: [0x05,0x00,0xa4,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xa4,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_floor_f32_e64 v5, exec_hi             ; encoding: [0x05,0x00,0xa4,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xa4,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_floor_f32_e64 v5, null                ; encoding: [0x05,0x00,0xa4,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xa4,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_floor_f32_e64 v5, -1                  ; encoding: [0x05,0x00,0xa4,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xa4,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_floor_f32_e64 v5, 0.5 mul:2           ; encoding: [0x05,0x00,0xa4,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xa4,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_floor_f32_e64 v5, src_scc mul:4       ; encoding: [0x05,0x00,0xa4,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xa4,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_floor_f32_e64 v255, -|0xaf123456| clamp div:2 ; encoding: [0xff,0x81,0xa4,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+0xff,0x81,0xa4,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf
+
+# GFX12: v_floor_f64_e64 v[5:6], v[1:2]          ; encoding: [0x05,0x00,0x9a,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0x9a,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_floor_f64_e64 v[5:6], v[254:255]      ; encoding: [0x05,0x00,0x9a,0xd5,0xfe,0x01,0x00,0x00]
+0x05,0x00,0x9a,0xd5,0xfe,0x01,0x00,0x00
+
+# GFX12: v_floor_f64_e64 v[5:6], s[2:3]          ; encoding: [0x05,0x00,0x9a,0xd5,0x02,0x00,0x00,0x00]
+0x05,0x00,0x9a,0xd5,0x02,0x00,0x00,0x00
+
+# GFX12: v_floor_f64_e64 v[5:6], s[104:105]      ; encoding: [0x05,0x00,0x9a,0xd5,0x68,0x00,0x00,0x00]
+0x05,0x00,0x9a,0xd5,0x68,0x00,0x00,0x00
+
+# GFX12: v_floor_f64_e64 v[5:6], vcc             ; encoding: [0x05,0x00,0x9a,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0x9a,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_floor_f64_e64 v[5:6], ttmp[14:15]     ; encoding: [0x05,0x00,0x9a,0xd5,0x7a,0x00,0x00,0x00]
+0x05,0x00,0x9a,0xd5,0x7a,0x00,0x00,0x00
+
+# GFX12: v_floor_f64_e64 v[5:6], exec            ; encoding: [0x05,0x00,0x9a,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0x9a,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_floor_f64_e64 v[5:6], null            ; encoding: [0x05,0x00,0x9a,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0x9a,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_floor_f64_e64 v[5:6], -1              ; encoding: [0x05,0x00,0x9a,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0x9a,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_floor_f64_e64 v[5:6], 0.5 mul:2       ; encoding: [0x05,0x00,0x9a,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0x9a,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_floor_f64_e64 v[5:6], -|src_scc| mul:4 ; encoding: [0x05,0x01,0x9a,0xd5,0xfd,0x00,0x00,0x30]
+0x05,0x01,0x9a,0xd5,0xfd,0x00,0x00,0x30
+
+# GFX12: v_floor_f64_e64 v[254:255], 0xaf123456 clamp div:2 ; encoding: [0xfe,0x80,0x9a,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+0xfe,0x80,0x9a,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fract_f16_e64 v5, v1                  ; encoding: [0x05,0x00,0xdf,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xdf,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_fract_f16_e64 v5, v255                ; encoding: [0x05,0x00,0xdf,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xdf,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_fract_f16_e64 v5, s1                  ; encoding: [0x05,0x00,0xdf,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xdf,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_fract_f16_e64 v5, s105                ; encoding: [0x05,0x00,0xdf,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xdf,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_fract_f16_e64 v5, vcc_lo              ; encoding: [0x05,0x00,0xdf,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xdf,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_fract_f16_e64 v5, vcc_hi              ; encoding: [0x05,0x00,0xdf,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xdf,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_fract_f16_e64 v5, ttmp15              ; encoding: [0x05,0x00,0xdf,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xdf,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_fract_f16_e64 v5, m0                  ; encoding: [0x05,0x00,0xdf,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xdf,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_fract_f16_e64 v5, exec_lo             ; encoding: [0x05,0x00,0xdf,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xdf,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_fract_f16_e64 v5, exec_hi             ; encoding: [0x05,0x00,0xdf,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xdf,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_fract_f16_e64 v5, null                ; encoding: [0x05,0x00,0xdf,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xdf,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_fract_f16_e64 v5, -1                  ; encoding: [0x05,0x00,0xdf,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xdf,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_fract_f16_e64 v5, 0.5 mul:2           ; encoding: [0x05,0x00,0xdf,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xdf,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_fract_f16_e64 v5, src_scc mul:4       ; encoding: [0x05,0x00,0xdf,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xdf,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_fract_f16_e64 v255, -|0xfe0b| clamp div:2 ; encoding: [0xff,0x81,0xdf,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00]
+0xff,0x81,0xdf,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fract_f32_e64 v5, v1                  ; encoding: [0x05,0x00,0xa0,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xa0,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_fract_f32_e64 v5, v255                ; encoding: [0x05,0x00,0xa0,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xa0,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_fract_f32_e64 v5, s1                  ; encoding: [0x05,0x00,0xa0,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xa0,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_fract_f32_e64 v5, s105                ; encoding: [0x05,0x00,0xa0,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xa0,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_fract_f32_e64 v5, vcc_lo              ; encoding: [0x05,0x00,0xa0,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xa0,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_fract_f32_e64 v5, vcc_hi              ; encoding: [0x05,0x00,0xa0,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xa0,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_fract_f32_e64 v5, ttmp15              ; encoding: [0x05,0x00,0xa0,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xa0,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_fract_f32_e64 v5, m0                  ; encoding: [0x05,0x00,0xa0,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xa0,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_fract_f32_e64 v5, exec_lo             ; encoding: [0x05,0x00,0xa0,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xa0,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_fract_f32_e64 v5, exec_hi             ; encoding: [0x05,0x00,0xa0,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xa0,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_fract_f32_e64 v5, null                ; encoding: [0x05,0x00,0xa0,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xa0,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_fract_f32_e64 v5, -1                  ; encoding: [0x05,0x00,0xa0,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xa0,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_fract_f32_e64 v5, 0.5 mul:2           ; encoding: [0x05,0x00,0xa0,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xa0,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_fract_f32_e64 v5, src_scc mul:4       ; encoding: [0x05,0x00,0xa0,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xa0,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_fract_f32_e64 v255, -|0xaf123456| clamp div:2 ; encoding: [0xff,0x81,0xa0,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+0xff,0x81,0xa0,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fract_f64_e64 v[5:6], v[1:2]          ; encoding: [0x05,0x00,0xbe,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xbe,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_fract_f64_e64 v[5:6], v[254:255]      ; encoding: [0x05,0x00,0xbe,0xd5,0xfe,0x01,0x00,0x00]
+0x05,0x00,0xbe,0xd5,0xfe,0x01,0x00,0x00
+
+# GFX12: v_fract_f64_e64 v[5:6], s[2:3]          ; encoding: [0x05,0x00,0xbe,0xd5,0x02,0x00,0x00,0x00]
+0x05,0x00,0xbe,0xd5,0x02,0x00,0x00,0x00
+
+# GFX12: v_fract_f64_e64 v[5:6], s[104:105]      ; encoding: [0x05,0x00,0xbe,0xd5,0x68,0x00,0x00,0x00]
+0x05,0x00,0xbe,0xd5,0x68,0x00,0x00,0x00
+
+# GFX12: v_fract_f64_e64 v[5:6], vcc             ; encoding: [0x05,0x00,0xbe,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xbe,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_fract_f64_e64 v[5:6], ttmp[14:15]     ; encoding: [0x05,0x00,0xbe,0xd5,0x7a,0x00,0x00,0x00]
+0x05,0x00,0xbe,0xd5,0x7a,0x00,0x00,0x00
+
+# GFX12: v_fract_f64_e64 v[5:6], exec            ; encoding: [0x05,0x00,0xbe,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xbe,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_fract_f64_e64 v[5:6], null            ; encoding: [0x05,0x00,0xbe,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xbe,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_fract_f64_e64 v[5:6], -1              ; encoding: [0x05,0x00,0xbe,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xbe,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_fract_f64_e64 v[5:6], 0.5 mul:2       ; encoding: [0x05,0x00,0xbe,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xbe,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_fract_f64_e64 v[5:6], -|src_scc| mul:4 ; encoding: [0x05,0x01,0xbe,0xd5,0xfd,0x00,0x00,0x30]
+0x05,0x01,0xbe,0xd5,0xfd,0x00,0x00,0x30
+
+# GFX12: v_fract_f64_e64 v[254:255], 0xaf123456 clamp div:2 ; encoding: [0xfe,0x80,0xbe,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+0xfe,0x80,0xbe,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf
+
+# GFX12: v_frexp_exp_i16_f16_e64 v5, v1          ; encoding: [0x05,0x00,0xda,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xda,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_frexp_exp_i16_f16_e64 v5, v255        ; encoding: [0x05,0x00,0xda,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xda,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_frexp_exp_i16_f16_e64 v5, s1          ; encoding: [0x05,0x00,0xda,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xda,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i16_f16_e64 v5, s105        ; encoding: [0x05,0x00,0xda,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xda,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i16_f16_e64 v5, vcc_lo      ; encoding: [0x05,0x00,0xda,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xda,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i16_f16_e64 v5, vcc_hi      ; encoding: [0x05,0x00,0xda,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xda,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i16_f16_e64 v5, ttmp15      ; encoding: [0x05,0x00,0xda,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xda,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i16_f16_e64 v5, m0          ; encoding: [0x05,0x00,0xda,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xda,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i16_f16_e64 v5, exec_lo     ; encoding: [0x05,0x00,0xda,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xda,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i16_f16_e64 v5, exec_hi     ; encoding: [0x05,0x00,0xda,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xda,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i16_f16_e64 v5, null        ; encoding: [0x05,0x00,0xda,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xda,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i16_f16_e64 v5, -1          ; encoding: [0x05,0x00,0xda,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xda,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i16_f16_e64 v5, 0.5         ; encoding: [0x05,0x00,0xda,0xd5,0xf0,0x00,0x00,0x00]
+0x05,0x00,0xda,0xd5,0xf0,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i16_f16_e64 v5, src_scc     ; encoding: [0x05,0x00,0xda,0xd5,0xfd,0x00,0x00,0x00]
+0x05,0x00,0xda,0xd5,0xfd,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i16_f16_e64 v255, -|0xfe0b| ; encoding: [0xff,0x01,0xda,0xd5,0xff,0x00,0x00,0x20,0x0b,0xfe,0x00,0x00]
+0xff,0x01,0xda,0xd5,0xff,0x00,0x00,0x20,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_frexp_exp_i32_f32_e64 v5, v1          ; encoding: [0x05,0x00,0xbf,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xbf,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_frexp_exp_i32_f32_e64 v5, v255        ; encoding: [0x05,0x00,0xbf,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xbf,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_frexp_exp_i32_f32_e64 v5, s1          ; encoding: [0x05,0x00,0xbf,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xbf,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i32_f32_e64 v5, s105        ; encoding: [0x05,0x00,0xbf,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xbf,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i32_f32_e64 v5, vcc_lo      ; encoding: [0x05,0x00,0xbf,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xbf,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i32_f32_e64 v5, vcc_hi      ; encoding: [0x05,0x00,0xbf,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xbf,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i32_f32_e64 v5, ttmp15      ; encoding: [0x05,0x00,0xbf,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xbf,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i32_f32_e64 v5, m0          ; encoding: [0x05,0x00,0xbf,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xbf,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i32_f32_e64 v5, exec_lo     ; encoding: [0x05,0x00,0xbf,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xbf,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i32_f32_e64 v5, exec_hi     ; encoding: [0x05,0x00,0xbf,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xbf,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i32_f32_e64 v5, null        ; encoding: [0x05,0x00,0xbf,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xbf,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i32_f32_e64 v5, -1          ; encoding: [0x05,0x00,0xbf,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xbf,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i32_f32_e64 v5, 0.5         ; encoding: [0x05,0x00,0xbf,0xd5,0xf0,0x00,0x00,0x00]
+0x05,0x00,0xbf,0xd5,0xf0,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i32_f32_e64 v5, src_scc     ; encoding: [0x05,0x00,0xbf,0xd5,0xfd,0x00,0x00,0x00]
+0x05,0x00,0xbf,0xd5,0xfd,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i32_f32_e64 v255, -|0xaf123456| ; encoding: [0xff,0x01,0xbf,0xd5,0xff,0x00,0x00,0x20,0x56,0x34,0x12,0xaf]
+0xff,0x01,0xbf,0xd5,0xff,0x00,0x00,0x20,0x56,0x34,0x12,0xaf
+
+# GFX12: v_frexp_exp_i32_f64_e64 v5, v[1:2]      ; encoding: [0x05,0x00,0xbc,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xbc,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_frexp_exp_i32_f64_e64 v5, v[254:255]  ; encoding: [0x05,0x00,0xbc,0xd5,0xfe,0x01,0x00,0x00]
+0x05,0x00,0xbc,0xd5,0xfe,0x01,0x00,0x00
+
+# GFX12: v_frexp_exp_i32_f64_e64 v5, s[2:3]      ; encoding: [0x05,0x00,0xbc,0xd5,0x02,0x00,0x00,0x00]
+0x05,0x00,0xbc,0xd5,0x02,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i32_f64_e64 v5, s[104:105]  ; encoding: [0x05,0x00,0xbc,0xd5,0x68,0x00,0x00,0x00]
+0x05,0x00,0xbc,0xd5,0x68,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i32_f64_e64 v5, vcc         ; encoding: [0x05,0x00,0xbc,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xbc,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i32_f64_e64 v5, ttmp[14:15] ; encoding: [0x05,0x00,0xbc,0xd5,0x7a,0x00,0x00,0x00]
+0x05,0x00,0xbc,0xd5,0x7a,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i32_f64_e64 v5, exec        ; encoding: [0x05,0x00,0xbc,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xbc,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i32_f64_e64 v5, null        ; encoding: [0x05,0x00,0xbc,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xbc,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i32_f64_e64 v5, -1          ; encoding: [0x05,0x00,0xbc,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xbc,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i32_f64_e64 v5, 0.5         ; encoding: [0x05,0x00,0xbc,0xd5,0xf0,0x00,0x00,0x00]
+0x05,0x00,0xbc,0xd5,0xf0,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i32_f64_e64 v5, -|src_scc|  ; encoding: [0x05,0x01,0xbc,0xd5,0xfd,0x00,0x00,0x20]
+0x05,0x01,0xbc,0xd5,0xfd,0x00,0x00,0x20
+
+# GFX12: v_frexp_exp_i32_f64_e64 v255, 0xaf123456 ; encoding: [0xff,0x00,0xbc,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0xbc,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_frexp_mant_f16_e64 v5, v1             ; encoding: [0x05,0x00,0xd9,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xd9,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_frexp_mant_f16_e64 v5, v255           ; encoding: [0x05,0x00,0xd9,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xd9,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_frexp_mant_f16_e64 v5, s1             ; encoding: [0x05,0x00,0xd9,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xd9,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f16_e64 v5, s105           ; encoding: [0x05,0x00,0xd9,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xd9,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f16_e64 v5, vcc_lo         ; encoding: [0x05,0x00,0xd9,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xd9,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f16_e64 v5, vcc_hi         ; encoding: [0x05,0x00,0xd9,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xd9,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f16_e64 v5, ttmp15         ; encoding: [0x05,0x00,0xd9,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xd9,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f16_e64 v5, m0             ; encoding: [0x05,0x00,0xd9,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xd9,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f16_e64 v5, exec_lo        ; encoding: [0x05,0x00,0xd9,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xd9,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f16_e64 v5, exec_hi        ; encoding: [0x05,0x00,0xd9,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xd9,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f16_e64 v5, null           ; encoding: [0x05,0x00,0xd9,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xd9,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f16_e64 v5, -1             ; encoding: [0x05,0x00,0xd9,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xd9,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f16_e64 v5, 0.5 mul:2      ; encoding: [0x05,0x00,0xd9,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xd9,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_frexp_mant_f16_e64 v5, src_scc mul:4  ; encoding: [0x05,0x00,0xd9,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xd9,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_frexp_mant_f16_e64 v255, -|0xfe0b| clamp div:2 ; encoding: [0xff,0x81,0xd9,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00]
+0xff,0x81,0xd9,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_frexp_mant_f32_e64 v5, v1             ; encoding: [0x05,0x00,0xc0,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xc0,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_frexp_mant_f32_e64 v5, v255           ; encoding: [0x05,0x00,0xc0,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xc0,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_frexp_mant_f32_e64 v5, s1             ; encoding: [0x05,0x00,0xc0,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xc0,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f32_e64 v5, s105           ; encoding: [0x05,0x00,0xc0,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xc0,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f32_e64 v5, vcc_lo         ; encoding: [0x05,0x00,0xc0,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xc0,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f32_e64 v5, vcc_hi         ; encoding: [0x05,0x00,0xc0,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xc0,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f32_e64 v5, ttmp15         ; encoding: [0x05,0x00,0xc0,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xc0,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f32_e64 v5, m0             ; encoding: [0x05,0x00,0xc0,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xc0,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f32_e64 v5, exec_lo        ; encoding: [0x05,0x00,0xc0,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xc0,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f32_e64 v5, exec_hi        ; encoding: [0x05,0x00,0xc0,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xc0,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f32_e64 v5, null           ; encoding: [0x05,0x00,0xc0,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xc0,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f32_e64 v5, -1             ; encoding: [0x05,0x00,0xc0,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xc0,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f32_e64 v5, 0.5 mul:2      ; encoding: [0x05,0x00,0xc0,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xc0,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_frexp_mant_f32_e64 v5, src_scc mul:4  ; encoding: [0x05,0x00,0xc0,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xc0,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_frexp_mant_f32_e64 v255, -|0xaf123456| clamp div:2 ; encoding: [0xff,0x81,0xc0,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+0xff,0x81,0xc0,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf
+
+# GFX12: v_frexp_mant_f64_e64 v[5:6], v[1:2]     ; encoding: [0x05,0x00,0xbd,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xbd,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_frexp_mant_f64_e64 v[5:6], v[254:255] ; encoding: [0x05,0x00,0xbd,0xd5,0xfe,0x01,0x00,0x00]
+0x05,0x00,0xbd,0xd5,0xfe,0x01,0x00,0x00
+
+# GFX12: v_frexp_mant_f64_e64 v[5:6], s[2:3]     ; encoding: [0x05,0x00,0xbd,0xd5,0x02,0x00,0x00,0x00]
+0x05,0x00,0xbd,0xd5,0x02,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f64_e64 v[5:6], s[104:105] ; encoding: [0x05,0x00,0xbd,0xd5,0x68,0x00,0x00,0x00]
+0x05,0x00,0xbd,0xd5,0x68,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f64_e64 v[5:6], vcc        ; encoding: [0x05,0x00,0xbd,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xbd,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f64_e64 v[5:6], ttmp[14:15] ; encoding: [0x05,0x00,0xbd,0xd5,0x7a,0x00,0x00,0x00]
+0x05,0x00,0xbd,0xd5,0x7a,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f64_e64 v[5:6], exec       ; encoding: [0x05,0x00,0xbd,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xbd,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f64_e64 v[5:6], null       ; encoding: [0x05,0x00,0xbd,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xbd,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f64_e64 v[5:6], -1         ; encoding: [0x05,0x00,0xbd,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xbd,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f64_e64 v[5:6], 0.5 mul:2  ; encoding: [0x05,0x00,0xbd,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xbd,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_frexp_mant_f64_e64 v[5:6], -|src_scc| mul:4 ; encoding: [0x05,0x01,0xbd,0xd5,0xfd,0x00,0x00,0x30]
+0x05,0x01,0xbd,0xd5,0xfd,0x00,0x00,0x30
+
+# GFX12: v_frexp_mant_f64_e64 v[254:255], 0xaf123456 clamp div:2 ; encoding: [0xfe,0x80,0xbd,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+0xfe,0x80,0xbd,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf
+
+# GFX12: v_log_f16_e64 v5, v1                    ; encoding: [0x05,0x00,0xd7,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xd7,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_log_f16_e64 v5, v255                  ; encoding: [0x05,0x00,0xd7,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xd7,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_log_f16_e64 v5, s1                    ; encoding: [0x05,0x00,0xd7,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xd7,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_log_f16_e64 v5, s105                  ; encoding: [0x05,0x00,0xd7,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xd7,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_log_f16_e64 v5, vcc_lo                ; encoding: [0x05,0x00,0xd7,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xd7,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_log_f16_e64 v5, vcc_hi                ; encoding: [0x05,0x00,0xd7,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xd7,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_log_f16_e64 v5, ttmp15                ; encoding: [0x05,0x00,0xd7,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xd7,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_log_f16_e64 v5, m0                    ; encoding: [0x05,0x00,0xd7,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xd7,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_log_f16_e64 v5, exec_lo               ; encoding: [0x05,0x00,0xd7,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xd7,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_log_f16_e64 v5, exec_hi               ; encoding: [0x05,0x00,0xd7,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xd7,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_log_f16_e64 v5, null                  ; encoding: [0x05,0x00,0xd7,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xd7,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_log_f16_e64 v5, -1                    ; encoding: [0x05,0x00,0xd7,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xd7,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_log_f16_e64 v5, 0.5 mul:2             ; encoding: [0x05,0x00,0xd7,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xd7,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_log_f16_e64 v5, src_scc mul:4         ; encoding: [0x05,0x00,0xd7,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xd7,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_log_f16_e64 v255, -|0xfe0b| clamp div:2 ; encoding: [0xff,0x81,0xd7,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00]
+0xff,0x81,0xd7,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_log_f32_e64 v5, v1                    ; encoding: [0x05,0x00,0xa7,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xa7,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_log_f32_e64 v5, v255                  ; encoding: [0x05,0x00,0xa7,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xa7,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_log_f32_e64 v5, s1                    ; encoding: [0x05,0x00,0xa7,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xa7,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_log_f32_e64 v5, s105                  ; encoding: [0x05,0x00,0xa7,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xa7,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_log_f32_e64 v5, vcc_lo                ; encoding: [0x05,0x00,0xa7,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xa7,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_log_f32_e64 v5, vcc_hi                ; encoding: [0x05,0x00,0xa7,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xa7,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_log_f32_e64 v5, ttmp15                ; encoding: [0x05,0x00,0xa7,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xa7,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_log_f32_e64 v5, m0                    ; encoding: [0x05,0x00,0xa7,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xa7,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_log_f32_e64 v5, exec_lo               ; encoding: [0x05,0x00,0xa7,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xa7,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_log_f32_e64 v5, exec_hi               ; encoding: [0x05,0x00,0xa7,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xa7,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_log_f32_e64 v5, null                  ; encoding: [0x05,0x00,0xa7,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xa7,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_log_f32_e64 v5, -1                    ; encoding: [0x05,0x00,0xa7,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xa7,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_log_f32_e64 v5, 0.5 mul:2             ; encoding: [0x05,0x00,0xa7,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xa7,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_log_f32_e64 v5, src_scc mul:4         ; encoding: [0x05,0x00,0xa7,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xa7,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_log_f32_e64 v255, -|0xaf123456| clamp div:2 ; encoding: [0xff,0x81,0xa7,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+0xff,0x81,0xa7,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mov_b32_e64 v5, v1                    ; encoding: [0x05,0x00,0x81,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0x81,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_mov_b32_e64 v5, v255                  ; encoding: [0x05,0x00,0x81,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0x81,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_mov_b32_e64 v5, s1                    ; encoding: [0x05,0x00,0x81,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0x81,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_mov_b32_e64 v5, s105                  ; encoding: [0x05,0x00,0x81,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0x81,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_mov_b32_e64 v5, vcc_lo                ; encoding: [0x05,0x00,0x81,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0x81,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_mov_b32_e64 v5, vcc_hi                ; encoding: [0x05,0x00,0x81,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0x81,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_mov_b32_e64 v5, ttmp15                ; encoding: [0x05,0x00,0x81,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0x81,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_mov_b32_e64 v5, m0                    ; encoding: [0x05,0x00,0x81,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0x81,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_mov_b32_e64 v5, exec_lo               ; encoding: [0x05,0x00,0x81,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0x81,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_mov_b32_e64 v5, exec_hi               ; encoding: [0x05,0x00,0x81,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0x81,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_mov_b32_e64 v5, null                  ; encoding: [0x05,0x00,0x81,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0x81,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_mov_b32_e64 v5, -1                    ; encoding: [0x05,0x00,0x81,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0x81,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_mov_b32_e64 v5, 0.5                   ; encoding: [0x05,0x00,0x81,0xd5,0xf0,0x00,0x00,0x00]
+0x05,0x00,0x81,0xd5,0xf0,0x00,0x00,0x00
+
+# GFX12: v_mov_b32_e64 v5, src_scc               ; encoding: [0x05,0x00,0x81,0xd5,0xfd,0x00,0x00,0x00]
+0x05,0x00,0x81,0xd5,0xfd,0x00,0x00,0x00
+
+# GFX12: v_mov_b32_e64 v255, 0xaf123456          ; encoding: [0xff,0x00,0x81,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x81,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_movreld_b32_e64 v5, v1                ; encoding: [0x05,0x00,0xc2,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xc2,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_movreld_b32_e64 v5, v255              ; encoding: [0x05,0x00,0xc2,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xc2,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_movreld_b32_e64 v5, s1                ; encoding: [0x05,0x00,0xc2,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xc2,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_movreld_b32_e64 v5, s105              ; encoding: [0x05,0x00,0xc2,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xc2,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_movreld_b32_e64 v5, vcc_lo            ; encoding: [0x05,0x00,0xc2,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xc2,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_movreld_b32_e64 v5, vcc_hi            ; encoding: [0x05,0x00,0xc2,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xc2,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_movreld_b32_e64 v5, ttmp15            ; encoding: [0x05,0x00,0xc2,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xc2,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_movreld_b32_e64 v5, m0                ; encoding: [0x05,0x00,0xc2,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xc2,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_movreld_b32_e64 v5, exec_lo           ; encoding: [0x05,0x00,0xc2,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xc2,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_movreld_b32_e64 v5, exec_hi           ; encoding: [0x05,0x00,0xc2,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xc2,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_movreld_b32_e64 v5, null              ; encoding: [0x05,0x00,0xc2,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xc2,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_movreld_b32_e64 v5, -1                ; encoding: [0x05,0x00,0xc2,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xc2,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_movreld_b32_e64 v5, 0.5               ; encoding: [0x05,0x00,0xc2,0xd5,0xf0,0x00,0x00,0x00]
+0x05,0x00,0xc2,0xd5,0xf0,0x00,0x00,0x00
+
+# GFX12: v_movreld_b32_e64 v5, src_scc           ; encoding: [0x05,0x00,0xc2,0xd5,0xfd,0x00,0x00,0x00]
+0x05,0x00,0xc2,0xd5,0xfd,0x00,0x00,0x00
+
+# GFX12: v_movreld_b32_e64 v255, 0xaf123456      ; encoding: [0xff,0x00,0xc2,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0xc2,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_movrels_b32_e64 v5, v1                ; encoding: [0x05,0x00,0xc3,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xc3,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_movrels_b32_e64 v255, v255            ; encoding: [0xff,0x00,0xc3,0xd5,0xff,0x01,0x00,0x00]
+0xff,0x00,0xc3,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_movrelsd_2_b32_e64 v5, v1             ; encoding: [0x05,0x00,0xc8,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xc8,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_movrelsd_2_b32_e64 v255, v255         ; encoding: [0xff,0x00,0xc8,0xd5,0xff,0x01,0x00,0x00]
+0xff,0x00,0xc8,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_movrelsd_b32_e64 v5, v1               ; encoding: [0x05,0x00,0xc4,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xc4,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_movrelsd_b32_e64 v255, v255           ; encoding: [0xff,0x00,0xc4,0xd5,0xff,0x01,0x00,0x00]
+0xff,0x00,0xc4,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_not_b16_e64 v5, v1                    ; encoding: [0x05,0x00,0xe9,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xe9,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_not_b16_e64 v5, v255                  ; encoding: [0x05,0x00,0xe9,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xe9,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_not_b16_e64 v5, s1                    ; encoding: [0x05,0x00,0xe9,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xe9,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_not_b16_e64 v5, s105                  ; encoding: [0x05,0x00,0xe9,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xe9,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_not_b16_e64 v5, vcc_lo                ; encoding: [0x05,0x00,0xe9,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xe9,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_not_b16_e64 v5, vcc_hi                ; encoding: [0x05,0x00,0xe9,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xe9,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_not_b16_e64 v5, ttmp15                ; encoding: [0x05,0x00,0xe9,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xe9,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_not_b16_e64 v5, m0                    ; encoding: [0x05,0x00,0xe9,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xe9,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_not_b16_e64 v5, exec_lo               ; encoding: [0x05,0x00,0xe9,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xe9,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_not_b16_e64 v5, exec_hi               ; encoding: [0x05,0x00,0xe9,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xe9,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_not_b16_e64 v5, null                  ; encoding: [0x05,0x00,0xe9,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xe9,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_not_b16_e64 v5, -1                    ; encoding: [0x05,0x00,0xe9,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xe9,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_not_b16_e64 v5, 0x3800
+0x05,0x00,0xe9,0xd5,0xf0,0x00,0x00,0x00
+
+# GFX12: v_not_b16_e64 v5, src_scc               ; encoding: [0x05,0x00,0xe9,0xd5,0xfd,0x00,0x00,0x00]
+0x05,0x00,0xe9,0xd5,0xfd,0x00,0x00,0x00
+
+# GFX12: v_not_b16_e64 v255, 0xfe0b              ; encoding: [0xff,0x00,0xe9,0xd5,0xff,0x00,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0xff,0x00,0xe9,0xd5,0xff,0x00,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_not_b32_e64 v5, v1                    ; encoding: [0x05,0x00,0xb7,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xb7,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_not_b32_e64 v5, v255                  ; encoding: [0x05,0x00,0xb7,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xb7,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_not_b32_e64 v5, s1                    ; encoding: [0x05,0x00,0xb7,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xb7,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_not_b32_e64 v5, s105                  ; encoding: [0x05,0x00,0xb7,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xb7,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_not_b32_e64 v5, vcc_lo                ; encoding: [0x05,0x00,0xb7,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xb7,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_not_b32_e64 v5, vcc_hi                ; encoding: [0x05,0x00,0xb7,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xb7,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_not_b32_e64 v5, ttmp15                ; encoding: [0x05,0x00,0xb7,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xb7,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_not_b32_e64 v5, m0                    ; encoding: [0x05,0x00,0xb7,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xb7,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_not_b32_e64 v5, exec_lo               ; encoding: [0x05,0x00,0xb7,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xb7,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_not_b32_e64 v5, exec_hi               ; encoding: [0x05,0x00,0xb7,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xb7,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_not_b32_e64 v5, null                  ; encoding: [0x05,0x00,0xb7,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xb7,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_not_b32_e64 v5, -1                    ; encoding: [0x05,0x00,0xb7,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xb7,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_not_b32_e64 v5, 0.5                   ; encoding: [0x05,0x00,0xb7,0xd5,0xf0,0x00,0x00,0x00]
+0x05,0x00,0xb7,0xd5,0xf0,0x00,0x00,0x00
+
+# GFX12: v_not_b32_e64 v5, src_scc               ; encoding: [0x05,0x00,0xb7,0xd5,0xfd,0x00,0x00,0x00]
+0x05,0x00,0xb7,0xd5,0xfd,0x00,0x00,0x00
+
+# GFX12: v_not_b32_e64 v255, 0xaf123456          ; encoding: [0xff,0x00,0xb7,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0xb7,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_rcp_f16_e64 v5, v1                    ; encoding: [0x05,0x00,0xd4,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xd4,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_rcp_f16_e64 v5, v255                  ; encoding: [0x05,0x00,0xd4,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xd4,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_rcp_f16_e64 v5, s1                    ; encoding: [0x05,0x00,0xd4,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xd4,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_rcp_f16_e64 v5, s105                  ; encoding: [0x05,0x00,0xd4,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xd4,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_rcp_f16_e64 v5, vcc_lo                ; encoding: [0x05,0x00,0xd4,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xd4,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_rcp_f16_e64 v5, vcc_hi                ; encoding: [0x05,0x00,0xd4,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xd4,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_rcp_f16_e64 v5, ttmp15                ; encoding: [0x05,0x00,0xd4,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xd4,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_rcp_f16_e64 v5, m0                    ; encoding: [0x05,0x00,0xd4,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xd4,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_rcp_f16_e64 v5, exec_lo               ; encoding: [0x05,0x00,0xd4,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xd4,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_rcp_f16_e64 v5, exec_hi               ; encoding: [0x05,0x00,0xd4,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xd4,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_rcp_f16_e64 v5, null                  ; encoding: [0x05,0x00,0xd4,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xd4,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_rcp_f16_e64 v5, -1                    ; encoding: [0x05,0x00,0xd4,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xd4,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_rcp_f16_e64 v5, 0.5 mul:2             ; encoding: [0x05,0x00,0xd4,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xd4,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_rcp_f16_e64 v5, src_scc mul:4         ; encoding: [0x05,0x00,0xd4,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xd4,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_rcp_f16_e64 v255, -|0xfe0b| clamp div:2 ; encoding: [0xff,0x81,0xd4,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00]
+0xff,0x81,0xd4,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_rcp_f32_e64 v5, v1                    ; encoding: [0x05,0x00,0xaa,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xaa,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_rcp_f32_e64 v5, v255                  ; encoding: [0x05,0x00,0xaa,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xaa,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_rcp_f32_e64 v5, s1                    ; encoding: [0x05,0x00,0xaa,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xaa,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_rcp_f32_e64 v5, s105                  ; encoding: [0x05,0x00,0xaa,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xaa,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_rcp_f32_e64 v5, vcc_lo                ; encoding: [0x05,0x00,0xaa,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xaa,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_rcp_f32_e64 v5, vcc_hi                ; encoding: [0x05,0x00,0xaa,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xaa,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_rcp_f32_e64 v5, ttmp15                ; encoding: [0x05,0x00,0xaa,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xaa,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_rcp_f32_e64 v5, m0                    ; encoding: [0x05,0x00,0xaa,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xaa,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_rcp_f32_e64 v5, exec_lo               ; encoding: [0x05,0x00,0xaa,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xaa,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_rcp_f32_e64 v5, exec_hi               ; encoding: [0x05,0x00,0xaa,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xaa,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_rcp_f32_e64 v5, null                  ; encoding: [0x05,0x00,0xaa,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xaa,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_rcp_f32_e64 v5, -1                    ; encoding: [0x05,0x00,0xaa,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xaa,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_rcp_f32_e64 v5, 0.5 mul:2             ; encoding: [0x05,0x00,0xaa,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xaa,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_rcp_f32_e64 v5, src_scc mul:4         ; encoding: [0x05,0x00,0xaa,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xaa,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_rcp_f32_e64 v255, -|0xaf123456| clamp div:2 ; encoding: [0xff,0x81,0xaa,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+0xff,0x81,0xaa,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf
+
+# GFX12: v_rcp_f64_e64 v[5:6], v[1:2]            ; encoding: [0x05,0x00,0xaf,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xaf,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_rcp_f64_e64 v[5:6], v[254:255]        ; encoding: [0x05,0x00,0xaf,0xd5,0xfe,0x01,0x00,0x00]
+0x05,0x00,0xaf,0xd5,0xfe,0x01,0x00,0x00
+
+# GFX12: v_rcp_f64_e64 v[5:6], s[2:3]            ; encoding: [0x05,0x00,0xaf,0xd5,0x02,0x00,0x00,0x00]
+0x05,0x00,0xaf,0xd5,0x02,0x00,0x00,0x00
+
+# GFX12: v_rcp_f64_e64 v[5:6], s[104:105]        ; encoding: [0x05,0x00,0xaf,0xd5,0x68,0x00,0x00,0x00]
+0x05,0x00,0xaf,0xd5,0x68,0x00,0x00,0x00
+
+# GFX12: v_rcp_f64_e64 v[5:6], vcc               ; encoding: [0x05,0x00,0xaf,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xaf,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_rcp_f64_e64 v[5:6], ttmp[14:15]       ; encoding: [0x05,0x00,0xaf,0xd5,0x7a,0x00,0x00,0x00]
+0x05,0x00,0xaf,0xd5,0x7a,0x00,0x00,0x00
+
+# GFX12: v_rcp_f64_e64 v[5:6], exec              ; encoding: [0x05,0x00,0xaf,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xaf,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_rcp_f64_e64 v[5:6], null              ; encoding: [0x05,0x00,0xaf,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xaf,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_rcp_f64_e64 v[5:6], -1                ; encoding: [0x05,0x00,0xaf,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xaf,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_rcp_f64_e64 v[5:6], 0.5 mul:2         ; encoding: [0x05,0x00,0xaf,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xaf,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_rcp_f64_e64 v[5:6], -|src_scc| mul:4  ; encoding: [0x05,0x01,0xaf,0xd5,0xfd,0x00,0x00,0x30]
+0x05,0x01,0xaf,0xd5,0xfd,0x00,0x00,0x30
+
+# GFX12: v_rcp_f64_e64 v[254:255], 0xaf123456 clamp div:2 ; encoding: [0xfe,0x80,0xaf,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+0xfe,0x80,0xaf,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf
+
+# GFX12: v_rcp_iflag_f32_e64 v5, v1              ; encoding: [0x05,0x00,0xab,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xab,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_rcp_iflag_f32_e64 v5, v255            ; encoding: [0x05,0x00,0xab,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xab,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_rcp_iflag_f32_e64 v5, s1              ; encoding: [0x05,0x00,0xab,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xab,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_rcp_iflag_f32_e64 v5, s105            ; encoding: [0x05,0x00,0xab,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xab,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_rcp_iflag_f32_e64 v5, vcc_lo          ; encoding: [0x05,0x00,0xab,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xab,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_rcp_iflag_f32_e64 v5, vcc_hi          ; encoding: [0x05,0x00,0xab,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xab,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_rcp_iflag_f32_e64 v5, ttmp15          ; encoding: [0x05,0x00,0xab,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xab,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_rcp_iflag_f32_e64 v5, m0              ; encoding: [0x05,0x00,0xab,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xab,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_rcp_iflag_f32_e64 v5, exec_lo         ; encoding: [0x05,0x00,0xab,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xab,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_rcp_iflag_f32_e64 v5, exec_hi         ; encoding: [0x05,0x00,0xab,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xab,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_rcp_iflag_f32_e64 v5, null            ; encoding: [0x05,0x00,0xab,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xab,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_rcp_iflag_f32_e64 v5, -1              ; encoding: [0x05,0x00,0xab,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xab,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_rcp_iflag_f32_e64 v5, 0.5 mul:2       ; encoding: [0x05,0x00,0xab,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xab,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_rcp_iflag_f32_e64 v5, src_scc mul:4   ; encoding: [0x05,0x00,0xab,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xab,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_rcp_iflag_f32_e64 v255, -|0xaf123456| clamp div:2 ; encoding: [0xff,0x81,0xab,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+0xff,0x81,0xab,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf
+
+# GFX12: v_rndne_f16_e64 v5, v1                  ; encoding: [0x05,0x00,0xde,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xde,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_rndne_f16_e64 v5, v255                ; encoding: [0x05,0x00,0xde,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xde,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_rndne_f16_e64 v5, s1                  ; encoding: [0x05,0x00,0xde,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xde,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_rndne_f16_e64 v5, s105                ; encoding: [0x05,0x00,0xde,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xde,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_rndne_f16_e64 v5, vcc_lo              ; encoding: [0x05,0x00,0xde,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xde,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_rndne_f16_e64 v5, vcc_hi              ; encoding: [0x05,0x00,0xde,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xde,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_rndne_f16_e64 v5, ttmp15              ; encoding: [0x05,0x00,0xde,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xde,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_rndne_f16_e64 v5, m0                  ; encoding: [0x05,0x00,0xde,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xde,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_rndne_f16_e64 v5, exec_lo             ; encoding: [0x05,0x00,0xde,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xde,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_rndne_f16_e64 v5, exec_hi             ; encoding: [0x05,0x00,0xde,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xde,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_rndne_f16_e64 v5, null                ; encoding: [0x05,0x00,0xde,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xde,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_rndne_f16_e64 v5, -1                  ; encoding: [0x05,0x00,0xde,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xde,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_rndne_f16_e64 v5, 0.5 mul:2           ; encoding: [0x05,0x00,0xde,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xde,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_rndne_f16_e64 v5, src_scc mul:4       ; encoding: [0x05,0x00,0xde,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xde,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_rndne_f16_e64 v255, -|0xfe0b| clamp div:2 ; encoding: [0xff,0x81,0xde,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00]
+0xff,0x81,0xde,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_rndne_f32_e64 v5, v1                  ; encoding: [0x05,0x00,0xa3,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xa3,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_rndne_f32_e64 v5, v255                ; encoding: [0x05,0x00,0xa3,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xa3,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_rndne_f32_e64 v5, s1                  ; encoding: [0x05,0x00,0xa3,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xa3,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_rndne_f32_e64 v5, s105                ; encoding: [0x05,0x00,0xa3,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xa3,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_rndne_f32_e64 v5, vcc_lo              ; encoding: [0x05,0x00,0xa3,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xa3,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_rndne_f32_e64 v5, vcc_hi              ; encoding: [0x05,0x00,0xa3,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xa3,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_rndne_f32_e64 v5, ttmp15              ; encoding: [0x05,0x00,0xa3,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xa3,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_rndne_f32_e64 v5, m0                  ; encoding: [0x05,0x00,0xa3,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xa3,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_rndne_f32_e64 v5, exec_lo             ; encoding: [0x05,0x00,0xa3,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xa3,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_rndne_f32_e64 v5, exec_hi             ; encoding: [0x05,0x00,0xa3,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xa3,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_rndne_f32_e64 v5, null                ; encoding: [0x05,0x00,0xa3,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xa3,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_rndne_f32_e64 v5, -1                  ; encoding: [0x05,0x00,0xa3,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xa3,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_rndne_f32_e64 v5, 0.5 mul:2           ; encoding: [0x05,0x00,0xa3,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xa3,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_rndne_f32_e64 v5, src_scc mul:4       ; encoding: [0x05,0x00,0xa3,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xa3,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_rndne_f32_e64 v255, -|0xaf123456| clamp div:2 ; encoding: [0xff,0x81,0xa3,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+0xff,0x81,0xa3,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf
+
+# GFX12: v_rndne_f64_e64 v[5:6], v[1:2]          ; encoding: [0x05,0x00,0x99,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0x99,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_rndne_f64_e64 v[5:6], v[254:255]      ; encoding: [0x05,0x00,0x99,0xd5,0xfe,0x01,0x00,0x00]
+0x05,0x00,0x99,0xd5,0xfe,0x01,0x00,0x00
+
+# GFX12: v_rndne_f64_e64 v[5:6], s[2:3]          ; encoding: [0x05,0x00,0x99,0xd5,0x02,0x00,0x00,0x00]
+0x05,0x00,0x99,0xd5,0x02,0x00,0x00,0x00
+
+# GFX12: v_rndne_f64_e64 v[5:6], s[104:105]      ; encoding: [0x05,0x00,0x99,0xd5,0x68,0x00,0x00,0x00]
+0x05,0x00,0x99,0xd5,0x68,0x00,0x00,0x00
+
+# GFX12: v_rndne_f64_e64 v[5:6], vcc             ; encoding: [0x05,0x00,0x99,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0x99,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_rndne_f64_e64 v[5:6], ttmp[14:15]     ; encoding: [0x05,0x00,0x99,0xd5,0x7a,0x00,0x00,0x00]
+0x05,0x00,0x99,0xd5,0x7a,0x00,0x00,0x00
+
+# GFX12: v_rndne_f64_e64 v[5:6], exec            ; encoding: [0x05,0x00,0x99,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0x99,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_rndne_f64_e64 v[5:6], null            ; encoding: [0x05,0x00,0x99,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0x99,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_rndne_f64_e64 v[5:6], -1              ; encoding: [0x05,0x00,0x99,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0x99,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_rndne_f64_e64 v[5:6], 0.5 mul:2       ; encoding: [0x05,0x00,0x99,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0x99,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_rndne_f64_e64 v[5:6], -|src_scc| mul:4 ; encoding: [0x05,0x01,0x99,0xd5,0xfd,0x00,0x00,0x30]
+0x05,0x01,0x99,0xd5,0xfd,0x00,0x00,0x30
+
+# GFX12: v_rndne_f64_e64 v[254:255], 0xaf123456 clamp div:2 ; encoding: [0xfe,0x80,0x99,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+0xfe,0x80,0x99,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf
+
+# GFX12: v_rsq_f16_e64 v5, v1                    ; encoding: [0x05,0x00,0xd6,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xd6,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_rsq_f16_e64 v5, v255                  ; encoding: [0x05,0x00,0xd6,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xd6,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_rsq_f16_e64 v5, s1                    ; encoding: [0x05,0x00,0xd6,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xd6,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_rsq_f16_e64 v5, s105                  ; encoding: [0x05,0x00,0xd6,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xd6,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_rsq_f16_e64 v5, vcc_lo                ; encoding: [0x05,0x00,0xd6,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xd6,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_rsq_f16_e64 v5, vcc_hi                ; encoding: [0x05,0x00,0xd6,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xd6,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_rsq_f16_e64 v5, ttmp15                ; encoding: [0x05,0x00,0xd6,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xd6,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_rsq_f16_e64 v5, m0                    ; encoding: [0x05,0x00,0xd6,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xd6,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_rsq_f16_e64 v5, exec_lo               ; encoding: [0x05,0x00,0xd6,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xd6,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_rsq_f16_e64 v5, exec_hi               ; encoding: [0x05,0x00,0xd6,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xd6,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_rsq_f16_e64 v5, null                  ; encoding: [0x05,0x00,0xd6,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xd6,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_rsq_f16_e64 v5, -1                    ; encoding: [0x05,0x00,0xd6,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xd6,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_rsq_f16_e64 v5, 0.5 mul:2             ; encoding: [0x05,0x00,0xd6,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xd6,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_rsq_f16_e64 v5, src_scc mul:4         ; encoding: [0x05,0x00,0xd6,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xd6,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_rsq_f16_e64 v255, -|0xfe0b| clamp div:2 ; encoding: [0xff,0x81,0xd6,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00]
+0xff,0x81,0xd6,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_rsq_f32_e64 v5, v1                    ; encoding: [0x05,0x00,0xae,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xae,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_rsq_f32_e64 v5, v255                  ; encoding: [0x05,0x00,0xae,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xae,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_rsq_f32_e64 v5, s1                    ; encoding: [0x05,0x00,0xae,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xae,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_rsq_f32_e64 v5, s105                  ; encoding: [0x05,0x00,0xae,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xae,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_rsq_f32_e64 v5, vcc_lo                ; encoding: [0x05,0x00,0xae,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xae,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_rsq_f32_e64 v5, vcc_hi                ; encoding: [0x05,0x00,0xae,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xae,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_rsq_f32_e64 v5, ttmp15                ; encoding: [0x05,0x00,0xae,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xae,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_rsq_f32_e64 v5, m0                    ; encoding: [0x05,0x00,0xae,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xae,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_rsq_f32_e64 v5, exec_lo               ; encoding: [0x05,0x00,0xae,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xae,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_rsq_f32_e64 v5, exec_hi               ; encoding: [0x05,0x00,0xae,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xae,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_rsq_f32_e64 v5, null                  ; encoding: [0x05,0x00,0xae,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xae,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_rsq_f32_e64 v5, -1                    ; encoding: [0x05,0x00,0xae,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xae,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_rsq_f32_e64 v5, 0.5 mul:2             ; encoding: [0x05,0x00,0xae,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xae,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_rsq_f32_e64 v5, src_scc mul:4         ; encoding: [0x05,0x00,0xae,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xae,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_rsq_f32_e64 v255, -|0xaf123456| clamp div:2 ; encoding: [0xff,0x81,0xae,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+0xff,0x81,0xae,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf
+
+# GFX12: v_rsq_f64_e64 v[5:6], v[1:2]            ; encoding: [0x05,0x00,0xb1,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xb1,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_rsq_f64_e64 v[5:6], v[254:255]        ; encoding: [0x05,0x00,0xb1,0xd5,0xfe,0x01,0x00,0x00]
+0x05,0x00,0xb1,0xd5,0xfe,0x01,0x00,0x00
+
+# GFX12: v_rsq_f64_e64 v[5:6], s[2:3]            ; encoding: [0x05,0x00,0xb1,0xd5,0x02,0x00,0x00,0x00]
+0x05,0x00,0xb1,0xd5,0x02,0x00,0x00,0x00
+
+# GFX12: v_rsq_f64_e64 v[5:6], s[104:105]        ; encoding: [0x05,0x00,0xb1,0xd5,0x68,0x00,0x00,0x00]
+0x05,0x00,0xb1,0xd5,0x68,0x00,0x00,0x00
+
+# GFX12: v_rsq_f64_e64 v[5:6], vcc               ; encoding: [0x05,0x00,0xb1,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xb1,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_rsq_f64_e64 v[5:6], ttmp[14:15]       ; encoding: [0x05,0x00,0xb1,0xd5,0x7a,0x00,0x00,0x00]
+0x05,0x00,0xb1,0xd5,0x7a,0x00,0x00,0x00
+
+# GFX12: v_rsq_f64_e64 v[5:6], exec              ; encoding: [0x05,0x00,0xb1,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xb1,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_rsq_f64_e64 v[5:6], null              ; encoding: [0x05,0x00,0xb1,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xb1,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_rsq_f64_e64 v[5:6], -1                ; encoding: [0x05,0x00,0xb1,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xb1,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_rsq_f64_e64 v[5:6], 0.5 mul:2         ; encoding: [0x05,0x00,0xb1,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xb1,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_rsq_f64_e64 v[5:6], -|src_scc| mul:4  ; encoding: [0x05,0x01,0xb1,0xd5,0xfd,0x00,0x00,0x30]
+0x05,0x01,0xb1,0xd5,0xfd,0x00,0x00,0x30
+
+# GFX12: v_rsq_f64_e64 v[254:255], 0xaf123456 clamp div:2 ; encoding: [0xfe,0x80,0xb1,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+0xfe,0x80,0xb1,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf
+
+# GFX12: v_sat_pk_u8_i16_e64 v5, v1              ; encoding: [0x05,0x00,0xe2,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xe2,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_sat_pk_u8_i16_e64 v5, v255            ; encoding: [0x05,0x00,0xe2,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xe2,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_sat_pk_u8_i16_e64 v5, s1              ; encoding: [0x05,0x00,0xe2,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xe2,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_sat_pk_u8_i16_e64 v5, s105            ; encoding: [0x05,0x00,0xe2,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xe2,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_sat_pk_u8_i16_e64 v5, vcc_lo          ; encoding: [0x05,0x00,0xe2,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xe2,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_sat_pk_u8_i16_e64 v5, vcc_hi          ; encoding: [0x05,0x00,0xe2,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xe2,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_sat_pk_u8_i16_e64 v5, ttmp15          ; encoding: [0x05,0x00,0xe2,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xe2,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_sat_pk_u8_i16_e64 v5, m0              ; encoding: [0x05,0x00,0xe2,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xe2,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_sat_pk_u8_i16_e64 v5, exec_lo         ; encoding: [0x05,0x00,0xe2,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xe2,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_sat_pk_u8_i16_e64 v5, exec_hi         ; encoding: [0x05,0x00,0xe2,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xe2,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_sat_pk_u8_i16_e64 v5, null            ; encoding: [0x05,0x00,0xe2,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xe2,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_sat_pk_u8_i16_e64 v5, -1              ; encoding: [0x05,0x00,0xe2,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xe2,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_sat_pk_u8_i16_e64 v5, 0.5             ; encoding: [0x05,0x00,0xe2,0xd5,0xf0,0x00,0x00,0x00]
+0x05,0x00,0xe2,0xd5,0xf0,0x00,0x00,0x00
+
+# GFX12: v_sat_pk_u8_i16_e64 v5, src_scc         ; encoding: [0x05,0x00,0xe2,0xd5,0xfd,0x00,0x00,0x00]
+0x05,0x00,0xe2,0xd5,0xfd,0x00,0x00,0x00
+
+# GFX12: v_sat_pk_u8_i16_e64 v255, 0xfe0b        ; encoding: [0xff,0x00,0xe2,0xd5,0xff,0x00,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0xff,0x00,0xe2,0xd5,0xff,0x00,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_sin_f16_e64 v5, v1                    ; encoding: [0x05,0x00,0xe0,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xe0,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_sin_f16_e64 v5, v255                  ; encoding: [0x05,0x00,0xe0,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xe0,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_sin_f16_e64 v5, s1                    ; encoding: [0x05,0x00,0xe0,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xe0,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_sin_f16_e64 v5, s105                  ; encoding: [0x05,0x00,0xe0,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xe0,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_sin_f16_e64 v5, vcc_lo                ; encoding: [0x05,0x00,0xe0,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xe0,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_sin_f16_e64 v5, vcc_hi                ; encoding: [0x05,0x00,0xe0,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xe0,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_sin_f16_e64 v5, ttmp15                ; encoding: [0x05,0x00,0xe0,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xe0,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_sin_f16_e64 v5, m0                    ; encoding: [0x05,0x00,0xe0,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xe0,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_sin_f16_e64 v5, exec_lo               ; encoding: [0x05,0x00,0xe0,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xe0,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_sin_f16_e64 v5, exec_hi               ; encoding: [0x05,0x00,0xe0,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xe0,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_sin_f16_e64 v5, null                  ; encoding: [0x05,0x00,0xe0,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xe0,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_sin_f16_e64 v5, -1                    ; encoding: [0x05,0x00,0xe0,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xe0,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_sin_f16_e64 v5, 0.5 mul:2             ; encoding: [0x05,0x00,0xe0,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xe0,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_sin_f16_e64 v5, src_scc mul:4         ; encoding: [0x05,0x00,0xe0,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xe0,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_sin_f16_e64 v255, -|0xfe0b| clamp div:2 ; encoding: [0xff,0x81,0xe0,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00]
+0xff,0x81,0xe0,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_sin_f32_e64 v5, v1                    ; encoding: [0x05,0x00,0xb5,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xb5,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_sin_f32_e64 v5, v255                  ; encoding: [0x05,0x00,0xb5,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xb5,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_sin_f32_e64 v5, s1                    ; encoding: [0x05,0x00,0xb5,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xb5,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_sin_f32_e64 v5, s105                  ; encoding: [0x05,0x00,0xb5,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xb5,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_sin_f32_e64 v5, vcc_lo                ; encoding: [0x05,0x00,0xb5,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xb5,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_sin_f32_e64 v5, vcc_hi                ; encoding: [0x05,0x00,0xb5,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xb5,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_sin_f32_e64 v5, ttmp15                ; encoding: [0x05,0x00,0xb5,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xb5,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_sin_f32_e64 v5, m0                    ; encoding: [0x05,0x00,0xb5,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xb5,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_sin_f32_e64 v5, exec_lo               ; encoding: [0x05,0x00,0xb5,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xb5,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_sin_f32_e64 v5, exec_hi               ; encoding: [0x05,0x00,0xb5,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xb5,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_sin_f32_e64 v5, null                  ; encoding: [0x05,0x00,0xb5,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xb5,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_sin_f32_e64 v5, -1                    ; encoding: [0x05,0x00,0xb5,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xb5,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_sin_f32_e64 v5, 0.5 mul:2             ; encoding: [0x05,0x00,0xb5,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xb5,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_sin_f32_e64 v5, src_scc mul:4         ; encoding: [0x05,0x00,0xb5,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xb5,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_sin_f32_e64 v255, -|0xaf123456| clamp div:2 ; encoding: [0xff,0x81,0xb5,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+0xff,0x81,0xb5,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf
+
+# GFX12: v_sqrt_f16_e64 v5, v1                   ; encoding: [0x05,0x00,0xd5,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xd5,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_sqrt_f16_e64 v5, v255                 ; encoding: [0x05,0x00,0xd5,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xd5,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_sqrt_f16_e64 v5, s1                   ; encoding: [0x05,0x00,0xd5,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xd5,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f16_e64 v5, s105                 ; encoding: [0x05,0x00,0xd5,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xd5,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f16_e64 v5, vcc_lo               ; encoding: [0x05,0x00,0xd5,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xd5,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f16_e64 v5, vcc_hi               ; encoding: [0x05,0x00,0xd5,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xd5,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f16_e64 v5, ttmp15               ; encoding: [0x05,0x00,0xd5,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xd5,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f16_e64 v5, m0                   ; encoding: [0x05,0x00,0xd5,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xd5,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f16_e64 v5, exec_lo              ; encoding: [0x05,0x00,0xd5,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xd5,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f16_e64 v5, exec_hi              ; encoding: [0x05,0x00,0xd5,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xd5,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f16_e64 v5, null                 ; encoding: [0x05,0x00,0xd5,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xd5,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f16_e64 v5, -1                   ; encoding: [0x05,0x00,0xd5,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xd5,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f16_e64 v5, 0.5 mul:2            ; encoding: [0x05,0x00,0xd5,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xd5,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_sqrt_f16_e64 v5, src_scc mul:4        ; encoding: [0x05,0x00,0xd5,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xd5,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_sqrt_f16_e64 v255, -|0xfe0b| clamp div:2 ; encoding: [0xff,0x81,0xd5,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00]
+0xff,0x81,0xd5,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_sqrt_f32_e64 v5, v1                   ; encoding: [0x05,0x00,0xb3,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xb3,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_sqrt_f32_e64 v5, v255                 ; encoding: [0x05,0x00,0xb3,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xb3,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_sqrt_f32_e64 v5, s1                   ; encoding: [0x05,0x00,0xb3,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xb3,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f32_e64 v5, s105                 ; encoding: [0x05,0x00,0xb3,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xb3,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f32_e64 v5, vcc_lo               ; encoding: [0x05,0x00,0xb3,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xb3,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f32_e64 v5, vcc_hi               ; encoding: [0x05,0x00,0xb3,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xb3,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f32_e64 v5, ttmp15               ; encoding: [0x05,0x00,0xb3,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xb3,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f32_e64 v5, m0                   ; encoding: [0x05,0x00,0xb3,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xb3,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f32_e64 v5, exec_lo              ; encoding: [0x05,0x00,0xb3,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xb3,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f32_e64 v5, exec_hi              ; encoding: [0x05,0x00,0xb3,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xb3,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f32_e64 v5, null                 ; encoding: [0x05,0x00,0xb3,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xb3,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f32_e64 v5, -1                   ; encoding: [0x05,0x00,0xb3,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xb3,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f32_e64 v5, 0.5 mul:2            ; encoding: [0x05,0x00,0xb3,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xb3,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_sqrt_f32_e64 v5, src_scc mul:4        ; encoding: [0x05,0x00,0xb3,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xb3,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_sqrt_f32_e64 v255, -|0xaf123456| clamp div:2 ; encoding: [0xff,0x81,0xb3,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+0xff,0x81,0xb3,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf
+
+# GFX12: v_sqrt_f64_e64 v[5:6], v[1:2]           ; encoding: [0x05,0x00,0xb4,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xb4,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_sqrt_f64_e64 v[5:6], v[254:255]       ; encoding: [0x05,0x00,0xb4,0xd5,0xfe,0x01,0x00,0x00]
+0x05,0x00,0xb4,0xd5,0xfe,0x01,0x00,0x00
+
+# GFX12: v_sqrt_f64_e64 v[5:6], s[2:3]           ; encoding: [0x05,0x00,0xb4,0xd5,0x02,0x00,0x00,0x00]
+0x05,0x00,0xb4,0xd5,0x02,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f64_e64 v[5:6], s[104:105]       ; encoding: [0x05,0x00,0xb4,0xd5,0x68,0x00,0x00,0x00]
+0x05,0x00,0xb4,0xd5,0x68,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f64_e64 v[5:6], vcc              ; encoding: [0x05,0x00,0xb4,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xb4,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f64_e64 v[5:6], ttmp[14:15]      ; encoding: [0x05,0x00,0xb4,0xd5,0x7a,0x00,0x00,0x00]
+0x05,0x00,0xb4,0xd5,0x7a,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f64_e64 v[5:6], exec             ; encoding: [0x05,0x00,0xb4,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xb4,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f64_e64 v[5:6], null             ; encoding: [0x05,0x00,0xb4,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xb4,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f64_e64 v[5:6], -1               ; encoding: [0x05,0x00,0xb4,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xb4,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f64_e64 v[5:6], 0.5 mul:2        ; encoding: [0x05,0x00,0xb4,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xb4,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_sqrt_f64_e64 v[5:6], -|src_scc| mul:4 ; encoding: [0x05,0x01,0xb4,0xd5,0xfd,0x00,0x00,0x30]
+0x05,0x01,0xb4,0xd5,0xfd,0x00,0x00,0x30
+
+# GFX12: v_sqrt_f64_e64 v[254:255], 0xaf123456 clamp div:2 ; encoding: [0xfe,0x80,0xb4,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+0xfe,0x80,0xb4,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf
+
+# GFX12: v_trunc_f16_e64 v5, v1                  ; encoding: [0x05,0x00,0xdd,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xdd,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_trunc_f16_e64 v5, v255                ; encoding: [0x05,0x00,0xdd,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xdd,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_trunc_f16_e64 v5, s1                  ; encoding: [0x05,0x00,0xdd,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xdd,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_trunc_f16_e64 v5, s105                ; encoding: [0x05,0x00,0xdd,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xdd,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_trunc_f16_e64 v5, vcc_lo              ; encoding: [0x05,0x00,0xdd,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xdd,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_trunc_f16_e64 v5, vcc_hi              ; encoding: [0x05,0x00,0xdd,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xdd,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_trunc_f16_e64 v5, ttmp15              ; encoding: [0x05,0x00,0xdd,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xdd,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_trunc_f16_e64 v5, m0                  ; encoding: [0x05,0x00,0xdd,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xdd,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_trunc_f16_e64 v5, exec_lo             ; encoding: [0x05,0x00,0xdd,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xdd,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_trunc_f16_e64 v5, exec_hi             ; encoding: [0x05,0x00,0xdd,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xdd,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_trunc_f16_e64 v5, null                ; encoding: [0x05,0x00,0xdd,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xdd,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_trunc_f16_e64 v5, -1                  ; encoding: [0x05,0x00,0xdd,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xdd,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_trunc_f16_e64 v5, 0.5 mul:2           ; encoding: [0x05,0x00,0xdd,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xdd,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_trunc_f16_e64 v5, src_scc mul:4       ; encoding: [0x05,0x00,0xdd,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xdd,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_trunc_f16_e64 v255, -|0xfe0b| clamp div:2 ; encoding: [0xff,0x81,0xdd,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00]
+0xff,0x81,0xdd,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_trunc_f32_e64 v5, v1                  ; encoding: [0x05,0x00,0xa1,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0xa1,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_trunc_f32_e64 v5, v255                ; encoding: [0x05,0x00,0xa1,0xd5,0xff,0x01,0x00,0x00]
+0x05,0x00,0xa1,0xd5,0xff,0x01,0x00,0x00
+
+# GFX12: v_trunc_f32_e64 v5, s1                  ; encoding: [0x05,0x00,0xa1,0xd5,0x01,0x00,0x00,0x00]
+0x05,0x00,0xa1,0xd5,0x01,0x00,0x00,0x00
+
+# GFX12: v_trunc_f32_e64 v5, s105                ; encoding: [0x05,0x00,0xa1,0xd5,0x69,0x00,0x00,0x00]
+0x05,0x00,0xa1,0xd5,0x69,0x00,0x00,0x00
+
+# GFX12: v_trunc_f32_e64 v5, vcc_lo              ; encoding: [0x05,0x00,0xa1,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0xa1,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_trunc_f32_e64 v5, vcc_hi              ; encoding: [0x05,0x00,0xa1,0xd5,0x6b,0x00,0x00,0x00]
+0x05,0x00,0xa1,0xd5,0x6b,0x00,0x00,0x00
+
+# GFX12: v_trunc_f32_e64 v5, ttmp15              ; encoding: [0x05,0x00,0xa1,0xd5,0x7b,0x00,0x00,0x00]
+0x05,0x00,0xa1,0xd5,0x7b,0x00,0x00,0x00
+
+# GFX12: v_trunc_f32_e64 v5, m0                  ; encoding: [0x05,0x00,0xa1,0xd5,0x7d,0x00,0x00,0x00]
+0x05,0x00,0xa1,0xd5,0x7d,0x00,0x00,0x00
+
+# GFX12: v_trunc_f32_e64 v5, exec_lo             ; encoding: [0x05,0x00,0xa1,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0xa1,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_trunc_f32_e64 v5, exec_hi             ; encoding: [0x05,0x00,0xa1,0xd5,0x7f,0x00,0x00,0x00]
+0x05,0x00,0xa1,0xd5,0x7f,0x00,0x00,0x00
+
+# GFX12: v_trunc_f32_e64 v5, null                ; encoding: [0x05,0x00,0xa1,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0xa1,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_trunc_f32_e64 v5, -1                  ; encoding: [0x05,0x00,0xa1,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0xa1,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_trunc_f32_e64 v5, 0.5 mul:2           ; encoding: [0x05,0x00,0xa1,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0xa1,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_trunc_f32_e64 v5, src_scc mul:4       ; encoding: [0x05,0x00,0xa1,0xd5,0xfd,0x00,0x00,0x10]
+0x05,0x00,0xa1,0xd5,0xfd,0x00,0x00,0x10
+
+# GFX12: v_trunc_f32_e64 v255, -|0xaf123456| clamp div:2 ; encoding: [0xff,0x81,0xa1,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf]
+0xff,0x81,0xa1,0xd5,0xff,0x00,0x00,0x38,0x56,0x34,0x12,0xaf
+
+# GFX12: v_trunc_f64_e64 v[5:6], v[1:2]          ; encoding: [0x05,0x00,0x97,0xd5,0x01,0x01,0x00,0x00]
+0x05,0x00,0x97,0xd5,0x01,0x01,0x00,0x00
+
+# GFX12: v_trunc_f64_e64 v[5:6], v[254:255]      ; encoding: [0x05,0x00,0x97,0xd5,0xfe,0x01,0x00,0x00]
+0x05,0x00,0x97,0xd5,0xfe,0x01,0x00,0x00
+
+# GFX12: v_trunc_f64_e64 v[5:6], s[2:3]          ; encoding: [0x05,0x00,0x97,0xd5,0x02,0x00,0x00,0x00]
+0x05,0x00,0x97,0xd5,0x02,0x00,0x00,0x00
+
+# GFX12: v_trunc_f64_e64 v[5:6], s[104:105]      ; encoding: [0x05,0x00,0x97,0xd5,0x68,0x00,0x00,0x00]
+0x05,0x00,0x97,0xd5,0x68,0x00,0x00,0x00
+
+# GFX12: v_trunc_f64_e64 v[5:6], vcc             ; encoding: [0x05,0x00,0x97,0xd5,0x6a,0x00,0x00,0x00]
+0x05,0x00,0x97,0xd5,0x6a,0x00,0x00,0x00
+
+# GFX12: v_trunc_f64_e64 v[5:6], ttmp[14:15]     ; encoding: [0x05,0x00,0x97,0xd5,0x7a,0x00,0x00,0x00]
+0x05,0x00,0x97,0xd5,0x7a,0x00,0x00,0x00
+
+# GFX12: v_trunc_f64_e64 v[5:6], exec            ; encoding: [0x05,0x00,0x97,0xd5,0x7e,0x00,0x00,0x00]
+0x05,0x00,0x97,0xd5,0x7e,0x00,0x00,0x00
+
+# GFX12: v_trunc_f64_e64 v[5:6], null            ; encoding: [0x05,0x00,0x97,0xd5,0x7c,0x00,0x00,0x00]
+0x05,0x00,0x97,0xd5,0x7c,0x00,0x00,0x00
+
+# GFX12: v_trunc_f64_e64 v[5:6], -1              ; encoding: [0x05,0x00,0x97,0xd5,0xc1,0x00,0x00,0x00]
+0x05,0x00,0x97,0xd5,0xc1,0x00,0x00,0x00
+
+# GFX12: v_trunc_f64_e64 v[5:6], 0.5 mul:2       ; encoding: [0x05,0x00,0x97,0xd5,0xf0,0x00,0x00,0x08]
+0x05,0x00,0x97,0xd5,0xf0,0x00,0x00,0x08
+
+# GFX12: v_trunc_f64_e64 v[5:6], -|src_scc| mul:4 ; encoding: [0x05,0x01,0x97,0xd5,0xfd,0x00,0x00,0x30]
+0x05,0x01,0x97,0xd5,0xfd,0x00,0x00,0x30
+
+# GFX12: v_trunc_f64_e64 v[254:255], 0xaf123456 clamp div:2 ; encoding: [0xfe,0x80,0x97,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf]
+0xfe,0x80,0x97,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp16.txt
new file mode 100644
index 000000000000..e914d139e240
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp16.txt
@@ -0,0 +1,2479 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX12 %s
+
+# GFX12: v_bfrev_b32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_bfrev_b32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_bfrev_b32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_bfrev_b32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_bfrev_b32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_bfrev_b32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_bfrev_b32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_bfrev_b32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_bfrev_b32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_bfrev_b32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_bfrev_b32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_bfrev_b32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_bfrev_b32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_bfrev_b32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_ceil_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_ceil_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_ceil_f16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_ceil_f16_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_ceil_f16_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_ceil_f16_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_ceil_f16_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_ceil_f16_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_ceil_f16_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_ceil_f16_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_ceil_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_ceil_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_ceil_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_ceil_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xdc,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xdc,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_ceil_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_ceil_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_ceil_f32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_ceil_f32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_ceil_f32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_ceil_f32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_ceil_f32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_ceil_f32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_ceil_f32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_ceil_f32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_ceil_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_ceil_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_ceil_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xa2,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_ceil_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xa2,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xa2,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cls_i32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cls_i32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cls_i32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cls_i32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cls_i32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cls_i32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cls_i32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cls_i32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cls_i32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cls_i32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cls_i32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cls_i32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cls_i32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cls_i32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0xbb,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_clz_i32_u32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_clz_i32_u32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_clz_i32_u32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_clz_i32_u32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_clz_i32_u32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_clz_i32_u32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_clz_i32_u32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_clz_i32_u32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_clz_i32_u32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_clz_i32_u32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_clz_i32_u32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_clz_i32_u32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_clz_i32_u32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_clz_i32_u32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0xb9,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cos_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cos_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cos_f16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cos_f16_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cos_f16_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cos_f16_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cos_f16_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cos_f16_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cos_f16_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cos_f16_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cos_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cos_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cos_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_cos_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xe1,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xe1,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cos_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cos_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cos_f32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cos_f32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cos_f32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cos_f32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cos_f32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cos_f32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cos_f32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cos_f32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cos_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cos_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cos_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xb6,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_cos_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xb6,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xb6,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_ctz_i32_b32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_ctz_i32_b32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_ctz_i32_b32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_ctz_i32_b32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_ctz_i32_b32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_ctz_i32_b32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_ctz_i32_b32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_ctz_i32_b32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_ctz_i32_b32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_ctz_i32_b32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_ctz_i32_b32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_ctz_i32_b32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_ctz_i32_b32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_ctz_i32_b32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0xba,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_f16_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_f16_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_f16_f32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_f16_f32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_f16_f32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_f16_f32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_f16_f32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_f16_f32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_f16_f32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_f16_f32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_f16_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_f16_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_f16_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0x8a,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_f16_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0x8a,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0x8a,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_f16_i16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_f16_i16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_f16_i16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_f16_i16_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_f16_i16_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_f16_i16_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_f16_i16_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_f16_i16_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_f16_i16_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_f16_i16_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_f16_i16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_f16_i16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_f16_i16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xd1,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_f16_i16_e64_dpp v255, v255 clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x80,0xd1,0xd5,0xfa,0x00,0x00,0x18,0xff,0x6f,0x0d,0x30]
+0xff,0x80,0xd1,0xd5,0xfa,0x00,0x00,0x18,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_f16_u16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_f16_u16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_f16_u16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_f16_u16_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_f16_u16_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_f16_u16_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_f16_u16_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_f16_u16_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_f16_u16_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_f16_u16_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_f16_u16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_f16_u16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_f16_u16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xd0,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_f16_u16_e64_dpp v255, v255 clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x80,0xd0,0xd5,0xfa,0x00,0x00,0x18,0xff,0x6f,0x0d,0x30]
+0xff,0x80,0xd0,0xd5,0xfa,0x00,0x00,0x18,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_f32_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_f32_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_f32_f16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_f32_f16_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_f32_f16_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_f32_f16_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_f32_f16_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_f32_f16_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_f32_f16_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_f32_f16_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_f32_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_f32_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_f32_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_f32_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0x8b,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0x8b,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_f32_i32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_f32_i32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_f32_i32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_f32_i32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_f32_i32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_f32_i32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_f32_i32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_f32_i32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_f32_i32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_f32_i32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_f32_i32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_f32_i32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_f32_i32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0x85,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_f32_i32_e64_dpp v255, v255 clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x80,0x85,0xd5,0xfa,0x00,0x00,0x18,0xff,0x6f,0x0d,0x30]
+0xff,0x80,0x85,0xd5,0xfa,0x00,0x00,0x18,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_f32_u32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_f32_u32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_f32_u32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_f32_u32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_f32_u32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_f32_u32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_f32_u32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_f32_u32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_f32_u32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_f32_u32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_f32_u32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_f32_u32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_f32_u32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0x86,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_f32_u32_e64_dpp v255, v255 clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x80,0x86,0xd5,0xfa,0x00,0x00,0x18,0xff,0x6f,0x0d,0x30]
+0xff,0x80,0x86,0xd5,0xfa,0x00,0x00,0x18,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_f32_ubyte0_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_f32_ubyte0_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_f32_ubyte0_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte0_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte0_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte0_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte0_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte0_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte0_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte0_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte0_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte0_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_f32_ubyte0_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0x91,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_f32_ubyte0_e64_dpp v255, v255 clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x80,0x91,0xd5,0xfa,0x00,0x00,0x18,0xff,0x6f,0x0d,0x30]
+0xff,0x80,0x91,0xd5,0xfa,0x00,0x00,0x18,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_f32_ubyte1_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_f32_ubyte1_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_f32_ubyte1_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte1_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte1_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte1_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte1_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte1_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte1_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte1_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte1_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte1_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_f32_ubyte1_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0x92,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_f32_ubyte1_e64_dpp v255, v255 clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x80,0x92,0xd5,0xfa,0x00,0x00,0x18,0xff,0x6f,0x0d,0x30]
+0xff,0x80,0x92,0xd5,0xfa,0x00,0x00,0x18,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_f32_ubyte2_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_f32_ubyte2_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_f32_ubyte2_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte2_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte2_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte2_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte2_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte2_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte2_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte2_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte2_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte2_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_f32_ubyte2_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0x93,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_f32_ubyte2_e64_dpp v255, v255 clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x80,0x93,0xd5,0xfa,0x00,0x00,0x18,0xff,0x6f,0x0d,0x30]
+0xff,0x80,0x93,0xd5,0xfa,0x00,0x00,0x18,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_f32_ubyte3_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_f32_ubyte3_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_f32_ubyte3_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte3_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte3_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte3_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte3_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte3_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte3_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte3_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte3_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_f32_ubyte3_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_f32_ubyte3_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0x94,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_f32_ubyte3_e64_dpp v255, v255 clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x80,0x94,0xd5,0xfa,0x00,0x00,0x18,0xff,0x6f,0x0d,0x30]
+0xff,0x80,0x94,0xd5,0xfa,0x00,0x00,0x18,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_floor_i32_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_floor_i32_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_floor_i32_f32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_floor_i32_f32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_floor_i32_f32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_floor_i32_f32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_floor_i32_f32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_floor_i32_f32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_floor_i32_f32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_floor_i32_f32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_floor_i32_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_floor_i32_f32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_floor_i32_f32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x8d,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_floor_i32_f32_e64_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x01,0x8d,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x0d,0x30]
+0xff,0x01,0x8d,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_i16_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_i16_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_i16_f16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_i16_f16_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_i16_f16_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_i16_f16_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_i16_f16_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_i16_f16_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_i16_f16_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_i16_f16_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_i16_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_i16_f16_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_i16_f16_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0xd3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_i16_f16_e64_dpp v255, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xd3,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xd3,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_i32_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_i32_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_i32_f32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_i32_f32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_i32_f32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_i32_f32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_i32_f32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_i32_f32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_i32_f32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_i32_f32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_i32_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_i32_f32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_i32_f32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x88,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_i32_f32_e64_dpp v255, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0x88,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0x88,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_i32_i16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_i32_i16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_i32_i16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_i32_i16_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_i32_i16_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_i32_i16_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_i32_i16_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_i32_i16_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_i32_i16_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_i32_i16_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_i32_i16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_i32_i16_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_i32_i16_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_i32_i16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0xea,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_nearest_i32_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_nearest_i32_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_nearest_i32_f32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_nearest_i32_f32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_nearest_i32_f32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_nearest_i32_f32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_nearest_i32_f32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_nearest_i32_f32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_nearest_i32_f32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_nearest_i32_f32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_nearest_i32_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_nearest_i32_f32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_nearest_i32_f32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x8c,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_nearest_i32_f32_e64_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x01,0x8c,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x0d,0x30]
+0xff,0x01,0x8c,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_norm_i16_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_norm_i16_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_norm_i16_f16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_norm_i16_f16_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_norm_i16_f16_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_norm_i16_f16_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_norm_i16_f16_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_norm_i16_f16_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_norm_i16_f16_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_norm_i16_f16_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_norm_i16_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_norm_i16_f16_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_norm_i16_f16_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0xe3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_norm_i16_f16_e64_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x01,0xe3,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x0d,0x30]
+0xff,0x01,0xe3,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_norm_u16_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_norm_u16_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_norm_u16_f16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_norm_u16_f16_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_norm_u16_f16_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_norm_u16_f16_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_norm_u16_f16_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_norm_u16_f16_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_norm_u16_f16_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_norm_u16_f16_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_norm_u16_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_norm_u16_f16_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_norm_u16_f16_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0xe4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_norm_u16_f16_e64_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x01,0xe4,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x0d,0x30]
+0xff,0x01,0xe4,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_off_f32_i4_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_off_f32_i4_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_off_f32_i4_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_off_f32_i4_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_off_f32_i4_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_off_f32_i4_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_off_f32_i4_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_off_f32_i4_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_off_f32_i4_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_off_f32_i4_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_off_f32_i4_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_off_f32_i4_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_off_f32_i4_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0x8e,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_off_f32_i4_e64_dpp v255, v255 clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x80,0x8e,0xd5,0xfa,0x00,0x00,0x18,0xff,0x6f,0x0d,0x30]
+0xff,0x80,0x8e,0xd5,0xfa,0x00,0x00,0x18,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_u16_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_u16_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_u16_f16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_u16_f16_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_u16_f16_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_u16_f16_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_u16_f16_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_u16_f16_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_u16_f16_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_u16_f16_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_u16_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_u16_f16_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_u16_f16_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0xd2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_u16_f16_e64_dpp v255, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xd2,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xd2,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_u32_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_u32_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_u32_f32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_u32_f32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_u32_f32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_u32_f32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_u32_f32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_u32_f32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_u32_f32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_u32_f32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_u32_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_u32_f32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_u32_f32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x87,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_u32_f32_e64_dpp v255, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0x87,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0x87,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_u32_u16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_u32_u16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_u32_u16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_u32_u16_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_u32_u16_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_u32_u16_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_u32_u16_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_u32_u16_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_u32_u16_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_u32_u16_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_u32_u16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_u32_u16_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_u32_u16_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_u32_u16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0xeb,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_exp_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_exp_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_exp_f16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_exp_f16_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_exp_f16_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_exp_f16_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_exp_f16_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_exp_f16_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_exp_f16_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_exp_f16_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_exp_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_exp_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_exp_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xd8,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_exp_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xd8,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xd8,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_exp_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_exp_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_exp_f32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_exp_f32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_exp_f32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_exp_f32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_exp_f32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_exp_f32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_exp_f32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_exp_f32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_exp_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_exp_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_exp_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xa5,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_exp_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xa5,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xa5,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_floor_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_floor_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_floor_f16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_floor_f16_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_floor_f16_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_floor_f16_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_floor_f16_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_floor_f16_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_floor_f16_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_floor_f16_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_floor_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_floor_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_floor_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xdb,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_floor_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xdb,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xdb,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_floor_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_floor_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_floor_f32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_floor_f32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_floor_f32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_floor_f32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_floor_f32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_floor_f32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_floor_f32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_floor_f32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_floor_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_floor_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_floor_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xa4,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_floor_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xa4,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xa4,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_fract_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_fract_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_fract_f16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_fract_f16_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_fract_f16_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_fract_f16_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_fract_f16_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_fract_f16_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_fract_f16_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_fract_f16_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_fract_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_fract_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_fract_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xdf,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_fract_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xdf,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xdf,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_fract_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_fract_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_fract_f32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_fract_f32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_fract_f32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_fract_f32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_fract_f32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_fract_f32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_fract_f32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_fract_f32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_fract_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_fract_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_fract_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xa0,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_fract_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xa0,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xa0,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_frexp_exp_i16_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_frexp_exp_i16_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_frexp_exp_i16_f16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_frexp_exp_i16_f16_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_frexp_exp_i16_f16_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_frexp_exp_i16_f16_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_frexp_exp_i16_f16_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_frexp_exp_i16_f16_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_frexp_exp_i16_f16_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_frexp_exp_i16_f16_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_frexp_exp_i16_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_frexp_exp_i16_f16_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_frexp_exp_i16_f16_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0xda,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_frexp_exp_i16_f16_e64_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x01,0xda,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x0d,0x30]
+0xff,0x01,0xda,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_frexp_exp_i32_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_frexp_exp_i32_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_frexp_exp_i32_f32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_frexp_exp_i32_f32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_frexp_exp_i32_f32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_frexp_exp_i32_f32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_frexp_exp_i32_f32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_frexp_exp_i32_f32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_frexp_exp_i32_f32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_frexp_exp_i32_f32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_frexp_exp_i32_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_frexp_exp_i32_f32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_frexp_exp_i32_f32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0xbf,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_frexp_exp_i32_f32_e64_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x01,0xbf,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x0d,0x30]
+0xff,0x01,0xbf,0xd5,0xfa,0x00,0x00,0x20,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_frexp_mant_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_frexp_mant_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_frexp_mant_f16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_frexp_mant_f16_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_frexp_mant_f16_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_frexp_mant_f16_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_frexp_mant_f16_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_frexp_mant_f16_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_frexp_mant_f16_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_frexp_mant_f16_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_frexp_mant_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_frexp_mant_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_frexp_mant_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xd9,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_frexp_mant_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xd9,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xd9,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_frexp_mant_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_frexp_mant_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_frexp_mant_f32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_frexp_mant_f32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_frexp_mant_f32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_frexp_mant_f32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_frexp_mant_f32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_frexp_mant_f32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_frexp_mant_f32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_frexp_mant_f32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_frexp_mant_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_frexp_mant_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_frexp_mant_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xc0,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_frexp_mant_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xc0,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xc0,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_log_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_log_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_log_f16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_log_f16_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_log_f16_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_log_f16_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_log_f16_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_log_f16_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_log_f16_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_log_f16_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_log_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_log_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_log_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xd7,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_log_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xd7,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xd7,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_log_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_log_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_log_f32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_log_f32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_log_f32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_log_f32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_log_f32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_log_f32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_log_f32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_log_f32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_log_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_log_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_log_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xa7,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_log_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xa7,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xa7,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_mov_b32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_mov_b32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_mov_b32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_mov_b32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_mov_b32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_mov_b32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_mov_b32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_mov_b32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_mov_b32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_mov_b32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_mov_b32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_mov_b32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_mov_b32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_mov_b32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x81,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_movrels_b32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_movrels_b32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_movrels_b32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_movrels_b32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_movrels_b32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_movrels_b32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_movrels_b32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_movrels_b32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_movrels_b32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_movrels_b32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_movrels_b32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_movrels_b32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_movrels_b32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_movrels_b32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0xc3,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_not_b16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_not_b16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_not_b16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_not_b16_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_not_b16_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_not_b16_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_not_b16_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_not_b16_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_not_b16_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_not_b16_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_not_b16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_not_b16_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_not_b16_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_not_b16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_not_b32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_not_b32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_not_b32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_not_b32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_not_b32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_not_b32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_not_b32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_not_b32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_not_b32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_not_b32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_not_b32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_not_b32_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_not_b32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_not_b32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0xb7,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_rcp_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_rcp_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_rcp_f16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_rcp_f16_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_rcp_f16_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_rcp_f16_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_rcp_f16_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_rcp_f16_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_rcp_f16_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_rcp_f16_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_rcp_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_rcp_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_rcp_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xd4,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_rcp_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xd4,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xd4,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_rcp_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_rcp_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_rcp_f32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_rcp_f32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_rcp_f32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_rcp_f32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_rcp_f32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_rcp_f32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_rcp_f32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_rcp_f32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_rcp_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_rcp_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_rcp_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xaa,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_rcp_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xaa,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xaa,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_rcp_iflag_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_rcp_iflag_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_rcp_iflag_f32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_rcp_iflag_f32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_rcp_iflag_f32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_rcp_iflag_f32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_rcp_iflag_f32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_rcp_iflag_f32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_rcp_iflag_f32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_rcp_iflag_f32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_rcp_iflag_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_rcp_iflag_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_rcp_iflag_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xab,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_rcp_iflag_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xab,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xab,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_rndne_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_rndne_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_rndne_f16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_rndne_f16_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_rndne_f16_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_rndne_f16_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_rndne_f16_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_rndne_f16_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_rndne_f16_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_rndne_f16_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_rndne_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_rndne_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_rndne_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xde,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_rndne_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xde,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xde,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_rndne_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_rndne_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_rndne_f32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_rndne_f32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_rndne_f32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_rndne_f32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_rndne_f32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_rndne_f32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_rndne_f32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_rndne_f32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_rndne_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_rndne_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_rndne_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xa3,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_rndne_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xa3,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xa3,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_rsq_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_rsq_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_rsq_f16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_rsq_f16_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_rsq_f16_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_rsq_f16_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_rsq_f16_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_rsq_f16_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_rsq_f16_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_rsq_f16_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_rsq_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_rsq_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_rsq_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xd6,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_rsq_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xd6,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xd6,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_rsq_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_rsq_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_rsq_f32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_rsq_f32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_rsq_f32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_rsq_f32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_rsq_f32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_rsq_f32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_rsq_f32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_rsq_f32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_rsq_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_rsq_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_rsq_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xae,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_rsq_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xae,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xae,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_sat_pk_u8_i16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_sat_pk_u8_i16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_sat_pk_u8_i16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_sat_pk_u8_i16_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_sat_pk_u8_i16_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_sat_pk_u8_i16_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_sat_pk_u8_i16_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_sat_pk_u8_i16_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_sat_pk_u8_i16_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_sat_pk_u8_i16_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_sat_pk_u8_i16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_sat_pk_u8_i16_e64_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_sat_pk_u8_i16_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_sat_pk_u8_i16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0xe2,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_sin_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_sin_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_sin_f16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_sin_f16_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_sin_f16_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_sin_f16_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_sin_f16_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_sin_f16_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_sin_f16_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_sin_f16_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_sin_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_sin_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_sin_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xe0,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_sin_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xe0,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xe0,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_sin_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_sin_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_sin_f32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_sin_f32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_sin_f32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_sin_f32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_sin_f32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_sin_f32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_sin_f32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_sin_f32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_sin_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_sin_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_sin_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xb5,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_sin_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xb5,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xb5,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_sqrt_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_sqrt_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_sqrt_f16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_sqrt_f16_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_sqrt_f16_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_sqrt_f16_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_sqrt_f16_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_sqrt_f16_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_sqrt_f16_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_sqrt_f16_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_sqrt_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_sqrt_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_sqrt_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xd5,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_sqrt_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xd5,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xd5,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_sqrt_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_sqrt_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_sqrt_f32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_sqrt_f32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_sqrt_f32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_sqrt_f32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_sqrt_f32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_sqrt_f32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_sqrt_f32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_sqrt_f32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_sqrt_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_sqrt_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_sqrt_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xb3,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_sqrt_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xb3,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xb3,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_trunc_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_trunc_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_trunc_f16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_trunc_f16_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_trunc_f16_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_trunc_f16_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_trunc_f16_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_trunc_f16_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_trunc_f16_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_trunc_f16_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_trunc_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_trunc_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_trunc_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xdd,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_trunc_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xdd,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xdd,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_trunc_f32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_trunc_f32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_trunc_f32_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_trunc_f32_e64_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_trunc_f32_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_trunc_f32_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_trunc_f32_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_trunc_f32_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_trunc_f32_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_trunc_f32_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_trunc_f32_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_trunc_f32_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_trunc_f32_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0xa1,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_trunc_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xa1,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0xa1,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp8.txt
new file mode 100644
index 000000000000..2a4b677620d3
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp8.txt
@@ -0,0 +1,583 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX12 %s
+
+# GFX12: v_bfrev_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xb8,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xb8,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_bfrev_b32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0xb8,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0xb8,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_ceil_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xdc,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xdc,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_ceil_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xdc,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xdc,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_ceil_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xdc,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xdc,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_ceil_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xdc,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0xdc,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_ceil_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xa2,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xa2,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_ceil_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xa2,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xa2,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_ceil_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xa2,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xa2,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_ceil_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xa2,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0xa2,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_cls_i32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xbb,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xbb,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cls_i32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0xbb,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0xbb,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_clz_i32_u32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xb9,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xb9,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_clz_i32_u32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0xb9,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0xb9,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cos_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xe1,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xe1,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cos_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xe1,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xe1,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_cos_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xe1,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xe1,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_cos_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xe1,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0xe1,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_cos_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xb6,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xb6,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cos_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xb6,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xb6,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_cos_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xb6,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xb6,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_cos_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xb6,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0xb6,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_ctz_i32_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xba,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xba,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_ctz_i32_b32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0xba,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0xba,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x8a,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x8a,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f16_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x8a,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0x8a,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f16_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x8a,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0x8a,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f16_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0x8a,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0x8a,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_i16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xd1,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xd1,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f16_i16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xd1,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xd1,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f16_i16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xd1,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xd1,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f16_i16_e64_dpp v255, v255 clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x80,0xd1,0xd5,0xea,0x00,0x00,0x18,0xff,0x00,0x00,0x00]
+0xff,0x80,0xd1,0xd5,0xea,0x00,0x00,0x18,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_f16_u16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xd0,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xd0,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f16_u16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xd0,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xd0,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f16_u16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xd0,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xd0,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f16_u16_e64_dpp v255, v255 clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x80,0xd0,0xd5,0xea,0x00,0x00,0x18,0xff,0x00,0x00,0x00]
+0xff,0x80,0xd0,0xd5,0xea,0x00,0x00,0x18,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x8b,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x8b,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f32_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x8b,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0x8b,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f32_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x8b,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0x8b,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f32_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0x8b,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0x8b,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_i32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x85,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x85,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f32_i32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x85,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0x85,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f32_i32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x85,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0x85,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f32_i32_e64_dpp v255, v255 clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x80,0x85,0xd5,0xea,0x00,0x00,0x18,0xff,0x00,0x00,0x00]
+0xff,0x80,0x85,0xd5,0xea,0x00,0x00,0x18,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_u32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x86,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x86,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f32_u32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x86,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0x86,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f32_u32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x86,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0x86,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f32_u32_e64_dpp v255, v255 clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x80,0x86,0xd5,0xea,0x00,0x00,0x18,0xff,0x00,0x00,0x00]
+0xff,0x80,0x86,0xd5,0xea,0x00,0x00,0x18,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte0_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x91,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x91,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f32_ubyte0_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x91,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0x91,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f32_ubyte0_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x91,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0x91,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f32_ubyte0_e64_dpp v255, v255 clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x80,0x91,0xd5,0xea,0x00,0x00,0x18,0xff,0x00,0x00,0x00]
+0xff,0x80,0x91,0xd5,0xea,0x00,0x00,0x18,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte1_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x92,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x92,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f32_ubyte1_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x92,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0x92,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f32_ubyte1_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x92,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0x92,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f32_ubyte1_e64_dpp v255, v255 clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x80,0x92,0xd5,0xea,0x00,0x00,0x18,0xff,0x00,0x00,0x00]
+0xff,0x80,0x92,0xd5,0xea,0x00,0x00,0x18,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte2_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x93,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x93,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f32_ubyte2_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x93,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0x93,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f32_ubyte2_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x93,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0x93,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f32_ubyte2_e64_dpp v255, v255 clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x80,0x93,0xd5,0xea,0x00,0x00,0x18,0xff,0x00,0x00,0x00]
+0xff,0x80,0x93,0xd5,0xea,0x00,0x00,0x18,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_f32_ubyte3_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x94,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x94,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f32_ubyte3_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x94,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0x94,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f32_ubyte3_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x94,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0x94,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_f32_ubyte3_e64_dpp v255, v255 clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x80,0x94,0xd5,0xea,0x00,0x00,0x18,0xff,0x00,0x00,0x00]
+0xff,0x80,0x94,0xd5,0xea,0x00,0x00,0x18,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_floor_i32_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x8d,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x8d,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_floor_i32_f32_e64_dpp v255, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x01,0x8d,0xd5,0xea,0x00,0x00,0x20,0xff,0x00,0x00,0x00]
+0xff,0x01,0x8d,0xd5,0xea,0x00,0x00,0x20,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_i16_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xd3,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xd3,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_i16_f16_e64_dpp v255, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xd3,0xd5,0xea,0x00,0x00,0x20,0xff,0x00,0x00,0x00]
+0xff,0x81,0xd3,0xd5,0xea,0x00,0x00,0x20,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x88,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x88,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_i32_f32_e64_dpp v255, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0x88,0xd5,0xea,0x00,0x00,0x20,0xff,0x00,0x00,0x00]
+0xff,0x81,0x88,0xd5,0xea,0x00,0x00,0x20,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_i32_i16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xea,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xea,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_i32_i16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0xea,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0xea,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_nearest_i32_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x8c,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x8c,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_nearest_i32_f32_e64_dpp v255, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x01,0x8c,0xd5,0xea,0x00,0x00,0x20,0xff,0x00,0x00,0x00]
+0xff,0x01,0x8c,0xd5,0xea,0x00,0x00,0x20,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_norm_i16_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xe3,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xe3,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_norm_i16_f16_e64_dpp v255, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x01,0xe3,0xd5,0xea,0x00,0x00,0x20,0xff,0x00,0x00,0x00]
+0xff,0x01,0xe3,0xd5,0xea,0x00,0x00,0x20,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_norm_u16_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xe4,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xe4,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_norm_u16_f16_e64_dpp v255, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x01,0xe4,0xd5,0xea,0x00,0x00,0x20,0xff,0x00,0x00,0x00]
+0xff,0x01,0xe4,0xd5,0xea,0x00,0x00,0x20,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_off_f32_i4_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x8e,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x8e,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_off_f32_i4_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x8e,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0x8e,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_off_f32_i4_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x8e,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0x8e,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_off_f32_i4_e64_dpp v255, v255 clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x80,0x8e,0xd5,0xea,0x00,0x00,0x18,0xff,0x00,0x00,0x00]
+0xff,0x80,0x8e,0xd5,0xea,0x00,0x00,0x18,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_u16_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xd2,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xd2,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_u16_f16_e64_dpp v255, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xd2,0xd5,0xea,0x00,0x00,0x20,0xff,0x00,0x00,0x00]
+0xff,0x81,0xd2,0xd5,0xea,0x00,0x00,0x20,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x87,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x87,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_u32_f32_e64_dpp v255, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0x87,0xd5,0xea,0x00,0x00,0x20,0xff,0x00,0x00,0x00]
+0xff,0x81,0x87,0xd5,0xea,0x00,0x00,0x20,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_u32_u16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xeb,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xeb,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_u32_u16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0xeb,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0xeb,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_exp_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xd8,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xd8,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_exp_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xd8,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xd8,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_exp_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xd8,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xd8,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_exp_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xd8,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0xd8,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_exp_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xa5,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xa5,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_exp_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xa5,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xa5,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_exp_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xa5,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xa5,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_exp_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xa5,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0xa5,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_floor_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xdb,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xdb,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_floor_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xdb,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xdb,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_floor_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xdb,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xdb,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_floor_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xdb,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0xdb,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_floor_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xa4,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xa4,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_floor_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xa4,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xa4,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_floor_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xa4,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xa4,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_floor_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xa4,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0xa4,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_fract_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xdf,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xdf,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_fract_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xdf,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xdf,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_fract_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xdf,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xdf,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_fract_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xdf,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0xdf,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_fract_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xa0,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xa0,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_fract_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xa0,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xa0,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_fract_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xa0,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xa0,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_fract_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xa0,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0xa0,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i16_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xda,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xda,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_frexp_exp_i16_f16_e64_dpp v255, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x01,0xda,0xd5,0xea,0x00,0x00,0x20,0xff,0x00,0x00,0x00]
+0xff,0x01,0xda,0xd5,0xea,0x00,0x00,0x20,0xff,0x00,0x00,0x00
+
+# GFX12: v_frexp_exp_i32_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xbf,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xbf,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_frexp_exp_i32_f32_e64_dpp v255, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x01,0xbf,0xd5,0xea,0x00,0x00,0x20,0xff,0x00,0x00,0x00]
+0xff,0x01,0xbf,0xd5,0xea,0x00,0x00,0x20,0xff,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xd9,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xd9,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_frexp_mant_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xd9,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xd9,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_frexp_mant_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xd9,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xd9,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_frexp_mant_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xd9,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0xd9,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_frexp_mant_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xc0,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xc0,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_frexp_mant_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xc0,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xc0,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_frexp_mant_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xc0,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xc0,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_frexp_mant_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xc0,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0xc0,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_log_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xd7,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xd7,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_log_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xd7,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xd7,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_log_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xd7,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xd7,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_log_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xd7,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0xd7,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_log_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xa7,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xa7,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_log_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xa7,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xa7,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_log_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xa7,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xa7,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_log_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xa7,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0xa7,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_mov_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x81,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x81,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_mov_b32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x81,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x81,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_movrels_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xc3,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xc3,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_movrels_b32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0xc3,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0xc3,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_not_b16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xe9,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xe9,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_not_b16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0xe9,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0xe9,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_not_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xb7,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xb7,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_not_b32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0xb7,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0xb7,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_rcp_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xd4,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xd4,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_rcp_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xd4,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xd4,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_rcp_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xd4,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xd4,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_rcp_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xd4,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0xd4,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_rcp_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xaa,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xaa,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_rcp_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xaa,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xaa,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_rcp_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xaa,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xaa,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_rcp_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xaa,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0xaa,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_rcp_iflag_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xab,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xab,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_rcp_iflag_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xab,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xab,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_rcp_iflag_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xab,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xab,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_rcp_iflag_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xab,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0xab,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_rndne_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xde,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xde,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_rndne_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xde,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xde,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_rndne_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xde,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xde,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_rndne_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xde,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0xde,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_rndne_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xa3,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xa3,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_rndne_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xa3,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xa3,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_rndne_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xa3,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xa3,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_rndne_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xa3,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0xa3,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_rsq_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xd6,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xd6,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_rsq_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xd6,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xd6,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_rsq_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xd6,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xd6,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_rsq_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xd6,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0xd6,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_rsq_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xae,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xae,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_rsq_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xae,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xae,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_rsq_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xae,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xae,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_rsq_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xae,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0xae,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_sat_pk_u8_i16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xe2,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xe2,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_sat_pk_u8_i16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0xe2,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0xe2,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_sin_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xe0,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xe0,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_sin_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xe0,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xe0,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_sin_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xe0,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xe0,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_sin_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xe0,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0xe0,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_sin_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xb5,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xb5,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_sin_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xb5,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xb5,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_sin_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xb5,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xb5,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_sin_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xb5,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0xb5,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xd5,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xd5,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_sqrt_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xd5,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xd5,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_sqrt_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xd5,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xd5,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_sqrt_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xd5,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0xd5,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_sqrt_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xb3,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xb3,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_sqrt_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xb3,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xb3,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_sqrt_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xb3,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xb3,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_sqrt_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xb3,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0xb3,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_trunc_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xdd,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xdd,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_trunc_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xdd,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xdd,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_trunc_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xdd,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xdd,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_trunc_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xdd,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0xdd,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_trunc_f32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xa1,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0xa1,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_trunc_f32_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xa1,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0xa1,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_trunc_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xa1,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0xa1,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_trunc_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0xa1,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0xa1,0xd5,0xea,0x00,0x00,0x38,0xff,0x00,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2.txt
new file mode 100644
index 000000000000..c14f82f9d985
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2.txt
@@ -0,0 +1,1968 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32 %s
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64 %s
+
+# W32: v_add_co_ci_u32_e64 v5, s12, v1, 0xaf123456, s6 ; encoding: [0x05,0x0c,0x20,0xd5,0x01,0xff,0x19,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_add_co_ci_u32_e64 v5, s[12:13], v1, 0xaf123456, s[6:7] ; encoding: [0x05,0x0c,0x20,0xd5,0x01,0xff,0x19,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x0c,0x20,0xd5,0x01,0xff,0x19,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_add_co_ci_u32_e64 v5, s12, v255, src_scc, s6 ; encoding: [0x05,0x0c,0x20,0xd5,0xff,0xfb,0x19,0x00]
+# W64: v_add_co_ci_u32_e64 v5, s[12:13], v255, src_scc, s[6:7] ; encoding: [0x05,0x0c,0x20,0xd5,0xff,0xfb,0x19,0x00]
+0x05,0x0c,0x20,0xd5,0xff,0xfb,0x19,0x00
+
+# W32: v_add_co_ci_u32_e64 v5, s12, s105, s105, s6 ; encoding: [0x05,0x0c,0x20,0xd5,0x69,0xd2,0x18,0x00]
+# W64: v_add_co_ci_u32_e64 v5, s[12:13], s105, s105, s[6:7] ; encoding: [0x05,0x0c,0x20,0xd5,0x69,0xd2,0x18,0x00]
+0x05,0x0c,0x20,0xd5,0x69,0xd2,0x18,0x00
+
+# W32: v_add_co_ci_u32_e64 v5, s12, vcc_lo, v2, s6 ; encoding: [0x05,0x0c,0x20,0xd5,0x6a,0x04,0x1a,0x00]
+# W64: v_add_co_ci_u32_e64 v5, s[12:13], vcc_lo, v2, s[6:7] ; encoding: [0x05,0x0c,0x20,0xd5,0x6a,0x04,0x1a,0x00]
+0x05,0x0c,0x20,0xd5,0x6a,0x04,0x1a,0x00
+
+# W32: v_add_co_ci_u32_e64 v5, s12, vcc_hi, v255, s6 ; encoding: [0x05,0x0c,0x20,0xd5,0x6b,0xfe,0x1b,0x00]
+# W64: v_add_co_ci_u32_e64 v5, s[12:13], vcc_hi, v255, s[6:7] ; encoding: [0x05,0x0c,0x20,0xd5,0x6b,0xfe,0x1b,0x00]
+0x05,0x0c,0x20,0xd5,0x6b,0xfe,0x1b,0x00
+
+# W32: v_add_co_ci_u32_e64 v5, s12, ttmp15, ttmp15, s6 ; encoding: [0x05,0x0c,0x20,0xd5,0x7b,0xf6,0x18,0x00]
+# W64: v_add_co_ci_u32_e64 v5, s[12:13], ttmp15, ttmp15, s[6:7] ; encoding: [0x05,0x0c,0x20,0xd5,0x7b,0xf6,0x18,0x00]
+0x05,0x0c,0x20,0xd5,0x7b,0xf6,0x18,0x00
+
+# W32: v_add_co_ci_u32_e64 v5, s12, m0, 0.5, s6  ; encoding: [0x05,0x0c,0x20,0xd5,0x7d,0xe0,0x19,0x00]
+# W64: v_add_co_ci_u32_e64 v5, s[12:13], m0, 0.5, s[6:7] ; encoding: [0x05,0x0c,0x20,0xd5,0x7d,0xe0,0x19,0x00]
+0x05,0x0c,0x20,0xd5,0x7d,0xe0,0x19,0x00
+
+# W32: v_add_co_ci_u32_e64 v5, s12, exec_lo, exec_lo, s6 ; encoding: [0x05,0x0c,0x20,0xd5,0x7e,0xfc,0x18,0x00]
+# W64: v_add_co_ci_u32_e64 v5, s[12:13], exec_lo, exec_lo, s[6:7] ; encoding: [0x05,0x0c,0x20,0xd5,0x7e,0xfc,0x18,0x00]
+0x05,0x0c,0x20,0xd5,0x7e,0xfc,0x18,0x00
+
+# W32: v_add_co_ci_u32_e64 v5, s12, exec_hi, -1, s6 ; encoding: [0x05,0x0c,0x20,0xd5,0x7f,0x82,0x19,0x00]
+# W64: v_add_co_ci_u32_e64 v5, s[12:13], exec_hi, -1, s[6:7] ; encoding: [0x05,0x0c,0x20,0xd5,0x7f,0x82,0x19,0x00]
+0x05,0x0c,0x20,0xd5,0x7f,0x82,0x19,0x00
+
+# W32: v_add_co_ci_u32_e64 v5, s12, null, exec_hi, s6 ; encoding: [0x05,0x0c,0x20,0xd5,0x7c,0xfe,0x18,0x00]
+# W64: v_add_co_ci_u32_e64 v5, s[12:13], null, exec_hi, s[6:7] ; encoding: [0x05,0x0c,0x20,0xd5,0x7c,0xfe,0x18,0x00]
+0x05,0x0c,0x20,0xd5,0x7c,0xfe,0x18,0x00
+
+# W32: v_add_co_ci_u32_e64 v5, s104, -1, m0, s104 ; encoding: [0x05,0x68,0x20,0xd5,0xc1,0xfa,0xa0,0x01]
+# W64: v_add_co_ci_u32_e64 v5, s[104:105], -1, m0, s[104:105] ; encoding: [0x05,0x68,0x20,0xd5,0xc1,0xfa,0xa0,0x01]
+0x05,0x68,0x20,0xd5,0xc1,0xfa,0xa0,0x01
+
+# W32: v_add_co_ci_u32_e64 v5, vcc_lo, 0.5, vcc_lo, vcc_lo ; encoding: [0x05,0x6a,0x20,0xd5,0xf0,0xd4,0xa8,0x01]
+# W64: v_add_co_ci_u32_e64 v5, vcc, 0.5, vcc_lo, vcc ; encoding: [0x05,0x6a,0x20,0xd5,0xf0,0xd4,0xa8,0x01]
+0x05,0x6a,0x20,0xd5,0xf0,0xd4,0xa8,0x01
+
+# W32: v_add_co_ci_u32_e64 v5, ttmp14, src_scc, null, ttmp14 ; encoding: [0x05,0x7a,0x20,0xd5,0xfd,0xf8,0xe8,0x01]
+# W64: v_add_co_ci_u32_e64 v5, ttmp[14:15], src_scc, null, ttmp[14:15] ; encoding: [0x05,0x7a,0x20,0xd5,0xfd,0xf8,0xe8,0x01]
+0x05,0x7a,0x20,0xd5,0xfd,0xf8,0xe8,0x01
+
+# GFX12: v_add_co_ci_u32_e64 v255, null, 0xaf123456, vcc_hi, null clamp ; encoding: [0xff,0xfc,0x20,0xd5,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x20,0xd5,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_add_f16_e64 v5, v1, v2                ; encoding: [0x05,0x00,0x32,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x32,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_add_f16_e64 v5, v255, v255            ; encoding: [0x05,0x00,0x32,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x32,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_add_f16_e64 v5, s1, s2                ; encoding: [0x05,0x00,0x32,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x32,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_add_f16_e64 v5, s105, s105            ; encoding: [0x05,0x00,0x32,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x32,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_add_f16_e64 v5, vcc_lo, ttmp15        ; encoding: [0x05,0x00,0x32,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x32,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_add_f16_e64 v5, vcc_hi, 0xfe0b        ; encoding: [0x05,0x00,0x32,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x32,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_add_f16_e64 v5, ttmp15, src_scc       ; encoding: [0x05,0x00,0x32,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x32,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_add_f16_e64 v5, m0, 0.5               ; encoding: [0x05,0x00,0x32,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x32,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_add_f16_e64 v5, exec_lo, -1           ; encoding: [0x05,0x00,0x32,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x32,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_add_f16_e64 v5, |exec_hi|, null       ; encoding: [0x05,0x01,0x32,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x01,0x32,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_add_f16_e64 v5, null, exec_lo         ; encoding: [0x05,0x00,0x32,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x32,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_add_f16_e64 v5, -1, exec_hi           ; encoding: [0x05,0x00,0x32,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x32,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_add_f16_e64 v5, 0.5, -m0 mul:2        ; encoding: [0x05,0x00,0x32,0xd5,0xf0,0xfa,0x00,0x48]
+0x05,0x00,0x32,0xd5,0xf0,0xfa,0x00,0x48
+
+# GFX12: v_add_f16_e64 v5, -src_scc, |vcc_lo| mul:4 ; encoding: [0x05,0x02,0x32,0xd5,0xfd,0xd4,0x00,0x30]
+0x05,0x02,0x32,0xd5,0xfd,0xd4,0x00,0x30
+
+# GFX12: v_add_f16_e64 v255, -|0xfe0b|, -|vcc_hi| clamp div:2 ; encoding: [0xff,0x83,0x32,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00]
+0xff,0x83,0x32,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_add_f32_e64 v5, v1, v2                ; encoding: [0x05,0x00,0x03,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x03,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_add_f32_e64 v5, v255, v255            ; encoding: [0x05,0x00,0x03,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x03,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_add_f32_e64 v5, s1, s2                ; encoding: [0x05,0x00,0x03,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x03,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_add_f32_e64 v5, s105, s105            ; encoding: [0x05,0x00,0x03,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x03,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_add_f32_e64 v5, vcc_lo, ttmp15        ; encoding: [0x05,0x00,0x03,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x03,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_add_f32_e64 v5, vcc_hi, 0xaf123456    ; encoding: [0x05,0x00,0x03,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x03,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_add_f32_e64 v5, ttmp15, src_scc       ; encoding: [0x05,0x00,0x03,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x03,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_add_f32_e64 v5, m0, 0.5               ; encoding: [0x05,0x00,0x03,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x03,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_add_f32_e64 v5, exec_lo, -1           ; encoding: [0x05,0x00,0x03,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x03,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_add_f32_e64 v5, |exec_hi|, null       ; encoding: [0x05,0x01,0x03,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x01,0x03,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_add_f32_e64 v5, null, exec_lo         ; encoding: [0x05,0x00,0x03,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x03,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_add_f32_e64 v5, -1, exec_hi           ; encoding: [0x05,0x00,0x03,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x03,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_add_f32_e64 v5, 0.5, -m0 mul:2        ; encoding: [0x05,0x00,0x03,0xd5,0xf0,0xfa,0x00,0x48]
+0x05,0x00,0x03,0xd5,0xf0,0xfa,0x00,0x48
+
+# GFX12: v_add_f32_e64 v5, -src_scc, |vcc_lo| mul:4 ; encoding: [0x05,0x02,0x03,0xd5,0xfd,0xd4,0x00,0x30]
+0x05,0x02,0x03,0xd5,0xfd,0xd4,0x00,0x30
+
+# GFX12: v_add_f32_e64 v255, -|0xaf123456|, -|vcc_hi| clamp div:2 ; encoding: [0xff,0x83,0x03,0xd5,0xff,0xd6,0x00,0x78,0x56,0x34,0x12,0xaf]
+0xff,0x83,0x03,0xd5,0xff,0xd6,0x00,0x78,0x56,0x34,0x12,0xaf
+
+# GFX12: v_add_f64_e64 v[5:6], v[2:3], v[4:5]    ; encoding: [0x05,0x00,0x02,0xd5,0x02,0x09,0x02,0x00]
+0x05,0x00,0x02,0xd5,0x02,0x09,0x02,0x00
+
+# GFX12: v_add_f64_e64 v[5:6], v[104:105], v[104:105] ; encoding: [0x05,0x00,0x02,0xd5,0x68,0xd1,0x02,0x00]
+0x05,0x00,0x02,0xd5,0x68,0xd1,0x02,0x00
+
+# GFX12: v_add_f64_e64 v[5:6], s[2:3], s[4:5]    ; encoding: [0x05,0x00,0x02,0xd5,0x02,0x08,0x00,0x00]
+0x05,0x00,0x02,0xd5,0x02,0x08,0x00,0x00
+
+# GFX12: v_add_f64_e64 v[5:6], s[104:105], s[104:105] ; encoding: [0x05,0x00,0x02,0xd5,0x68,0xd0,0x00,0x00]
+0x05,0x00,0x02,0xd5,0x68,0xd0,0x00,0x00
+
+# GFX12: v_add_f64_e64 v[5:6], vcc, ttmp[14:15]  ; encoding: [0x05,0x00,0x02,0xd5,0x6a,0xf4,0x00,0x00]
+0x05,0x00,0x02,0xd5,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_add_f64_e64 v[5:6], ttmp[14:15], 0xaf123456 ; encoding: [0x05,0x00,0x02,0xd5,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x02,0xd5,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_add_f64_e64 v[5:6], -|exec|, src_scc  ; encoding: [0x05,0x01,0x02,0xd5,0x7e,0xfa,0x01,0x20]
+0x05,0x01,0x02,0xd5,0x7e,0xfa,0x01,0x20
+
+# GFX12: v_add_f64_e64 v[5:6], null, 0.5         ; encoding: [0x05,0x00,0x02,0xd5,0x7c,0xe0,0x01,0x00]
+0x05,0x00,0x02,0xd5,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_add_f64_e64 v[5:6], -1, -1            ; encoding: [0x05,0x00,0x02,0xd5,0xc1,0x82,0x01,0x00]
+0x05,0x00,0x02,0xd5,0xc1,0x82,0x01,0x00
+
+# GFX12: v_add_f64_e64 v[5:6], 0.5, null mul:2   ; encoding: [0x05,0x00,0x02,0xd5,0xf0,0xf8,0x00,0x08]
+0x05,0x00,0x02,0xd5,0xf0,0xf8,0x00,0x08
+
+# GFX12: v_add_f64_e64 v[5:6], -|src_scc|, -|exec| mul:4 ; encoding: [0x05,0x03,0x02,0xd5,0xfd,0xfc,0x00,0x70]
+0x05,0x03,0x02,0xd5,0xfd,0xfc,0x00,0x70
+
+# GFX12: v_add_f64_e64 v[254:255], 0xaf123456, -|vcc| clamp div:2 ; encoding: [0xfe,0x82,0x02,0xd5,0xff,0xd4,0x00,0x58,0x56,0x34,0x12,0xaf]
+0xfe,0x82,0x02,0xd5,0xff,0xd4,0x00,0x58,0x56,0x34,0x12,0xaf
+
+# GFX12: v_add_nc_u32_e64 v5, v1, v2             ; encoding: [0x05,0x00,0x25,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x25,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_add_nc_u32_e64 v5, v255, v255         ; encoding: [0x05,0x00,0x25,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x25,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_add_nc_u32_e64 v5, s1, s2             ; encoding: [0x05,0x00,0x25,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x25,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_add_nc_u32_e64 v5, s105, s105         ; encoding: [0x05,0x00,0x25,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x25,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_add_nc_u32_e64 v5, vcc_lo, ttmp15     ; encoding: [0x05,0x00,0x25,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x25,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_add_nc_u32_e64 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x25,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x25,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_add_nc_u32_e64 v5, ttmp15, src_scc    ; encoding: [0x05,0x00,0x25,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x25,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_add_nc_u32_e64 v5, m0, 0.5            ; encoding: [0x05,0x00,0x25,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x25,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_add_nc_u32_e64 v5, exec_lo, -1        ; encoding: [0x05,0x00,0x25,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x25,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_add_nc_u32_e64 v5, exec_hi, null      ; encoding: [0x05,0x00,0x25,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x25,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_add_nc_u32_e64 v5, null, exec_lo      ; encoding: [0x05,0x00,0x25,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x25,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_add_nc_u32_e64 v5, -1, exec_hi        ; encoding: [0x05,0x00,0x25,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x25,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_add_nc_u32_e64 v5, 0.5, m0            ; encoding: [0x05,0x00,0x25,0xd5,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x25,0xd5,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_add_nc_u32_e64 v5, src_scc, vcc_lo    ; encoding: [0x05,0x00,0x25,0xd5,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x25,0xd5,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_add_nc_u32_e64 v255, 0xaf123456, vcc_hi clamp ; encoding: [0xff,0x80,0x25,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x80,0x25,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_and_b32_e64 v5, v1, v2                ; encoding: [0x05,0x00,0x1b,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x1b,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_and_b32_e64 v5, v255, v255            ; encoding: [0x05,0x00,0x1b,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x1b,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_and_b32_e64 v5, s1, s2                ; encoding: [0x05,0x00,0x1b,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x1b,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_and_b32_e64 v5, s105, s105            ; encoding: [0x05,0x00,0x1b,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x1b,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_and_b32_e64 v5, vcc_lo, ttmp15        ; encoding: [0x05,0x00,0x1b,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x1b,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_and_b32_e64 v5, vcc_hi, 0xaf123456    ; encoding: [0x05,0x00,0x1b,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x1b,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_and_b32_e64 v5, ttmp15, src_scc       ; encoding: [0x05,0x00,0x1b,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x1b,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_and_b32_e64 v5, m0, 0.5               ; encoding: [0x05,0x00,0x1b,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x1b,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_and_b32_e64 v5, exec_lo, -1           ; encoding: [0x05,0x00,0x1b,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x1b,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_and_b32_e64 v5, exec_hi, null         ; encoding: [0x05,0x00,0x1b,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x1b,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_and_b32_e64 v5, null, exec_lo         ; encoding: [0x05,0x00,0x1b,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x1b,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_and_b32_e64 v5, -1, exec_hi           ; encoding: [0x05,0x00,0x1b,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x1b,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_and_b32_e64 v5, 0.5, m0               ; encoding: [0x05,0x00,0x1b,0xd5,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x1b,0xd5,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_and_b32_e64 v5, src_scc, vcc_lo       ; encoding: [0x05,0x00,0x1b,0xd5,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x1b,0xd5,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_and_b32_e64 v255, 0xaf123456, vcc_hi  ; encoding: [0xff,0x00,0x1b,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x1b,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_ashrrev_i32_e64 v5, v1, v2            ; encoding: [0x05,0x00,0x1a,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x1a,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_ashrrev_i32_e64 v5, v255, v255        ; encoding: [0x05,0x00,0x1a,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x1a,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_ashrrev_i32_e64 v5, s1, s2            ; encoding: [0x05,0x00,0x1a,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x1a,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_ashrrev_i32_e64 v5, s105, s105        ; encoding: [0x05,0x00,0x1a,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x1a,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_ashrrev_i32_e64 v5, vcc_lo, ttmp15    ; encoding: [0x05,0x00,0x1a,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x1a,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_ashrrev_i32_e64 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x1a,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x1a,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_ashrrev_i32_e64 v5, ttmp15, src_scc   ; encoding: [0x05,0x00,0x1a,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x1a,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_ashrrev_i32_e64 v5, m0, 0.5           ; encoding: [0x05,0x00,0x1a,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x1a,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_ashrrev_i32_e64 v5, exec_lo, -1       ; encoding: [0x05,0x00,0x1a,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x1a,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_ashrrev_i32_e64 v5, exec_hi, null     ; encoding: [0x05,0x00,0x1a,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x1a,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_ashrrev_i32_e64 v5, null, exec_lo     ; encoding: [0x05,0x00,0x1a,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x1a,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_ashrrev_i32_e64 v5, -1, exec_hi       ; encoding: [0x05,0x00,0x1a,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x1a,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_ashrrev_i32_e64 v5, 0.5, m0           ; encoding: [0x05,0x00,0x1a,0xd5,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x1a,0xd5,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_ashrrev_i32_e64 v5, src_scc, vcc_lo   ; encoding: [0x05,0x00,0x1a,0xd5,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x1a,0xd5,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_ashrrev_i32_e64 v255, 0xaf123456, vcc_hi ; encoding: [0xff,0x00,0x1a,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x1a,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cndmask_b32_e64 v5, v1, 0xaf123456, s6  ; encoding: [0x05,0x00,0x01,0xd5,0x01,0xff,0x19,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cndmask_b32_e64 v5, v1, 0xaf123456, s[6:7] ; encoding: [0x05,0x00,0x01,0xd5,0x01,0xff,0x19,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x01,0xd5,0x01,0xff,0x19,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cndmask_b32_e64 v5, v255, src_scc, s6   ; encoding: [0x05,0x00,0x01,0xd5,0xff,0xfb,0x19,0x00]
+# W64: v_cndmask_b32_e64 v5, v255, src_scc, s[6:7] ; encoding: [0x05,0x00,0x01,0xd5,0xff,0xfb,0x19,0x00]
+0x05,0x00,0x01,0xd5,0xff,0xfb,0x19,0x00
+
+# W32: v_cndmask_b32_e64 v5, s105, s105, s6      ; encoding: [0x05,0x00,0x01,0xd5,0x69,0xd2,0x18,0x00]
+# W64: v_cndmask_b32_e64 v5, s105, s105, s[6:7]  ; encoding: [0x05,0x00,0x01,0xd5,0x69,0xd2,0x18,0x00]
+0x05,0x00,0x01,0xd5,0x69,0xd2,0x18,0x00
+
+# W32: v_cndmask_b32_e64 v5, vcc_lo, v2, s6      ; encoding: [0x05,0x00,0x01,0xd5,0x6a,0x04,0x1a,0x00]
+# W64: v_cndmask_b32_e64 v5, vcc_lo, v2, s[6:7]  ; encoding: [0x05,0x00,0x01,0xd5,0x6a,0x04,0x1a,0x00]
+0x05,0x00,0x01,0xd5,0x6a,0x04,0x1a,0x00
+
+# W32: v_cndmask_b32_e64 v5, vcc_hi, v255, s6    ; encoding: [0x05,0x00,0x01,0xd5,0x6b,0xfe,0x1b,0x00]
+# W64: v_cndmask_b32_e64 v5, vcc_hi, v255, s[6:7] ; encoding: [0x05,0x00,0x01,0xd5,0x6b,0xfe,0x1b,0x00]
+0x05,0x00,0x01,0xd5,0x6b,0xfe,0x1b,0x00
+
+# W32: v_cndmask_b32_e64 v5, ttmp15, ttmp15, s6  ; encoding: [0x05,0x00,0x01,0xd5,0x7b,0xf6,0x18,0x00]
+# W64: v_cndmask_b32_e64 v5, ttmp15, ttmp15, s[6:7] ; encoding: [0x05,0x00,0x01,0xd5,0x7b,0xf6,0x18,0x00]
+0x05,0x00,0x01,0xd5,0x7b,0xf6,0x18,0x00
+
+# W32: v_cndmask_b32_e64 v5, m0, 0.5, s6         ; encoding: [0x05,0x00,0x01,0xd5,0x7d,0xe0,0x19,0x00]
+# W64: v_cndmask_b32_e64 v5, m0, 0.5, s[6:7]     ; encoding: [0x05,0x00,0x01,0xd5,0x7d,0xe0,0x19,0x00]
+0x05,0x00,0x01,0xd5,0x7d,0xe0,0x19,0x00
+
+# W32: v_cndmask_b32_e64 v5, exec_lo, exec_lo, s6 ; encoding: [0x05,0x00,0x01,0xd5,0x7e,0xfc,0x18,0x00]
+# W64: v_cndmask_b32_e64 v5, exec_lo, exec_lo, s[6:7] ; encoding: [0x05,0x00,0x01,0xd5,0x7e,0xfc,0x18,0x00]
+0x05,0x00,0x01,0xd5,0x7e,0xfc,0x18,0x00
+
+# W32: v_cndmask_b32_e64 v5, exec_hi, -1, s6     ; encoding: [0x05,0x00,0x01,0xd5,0x7f,0x82,0x19,0x00]
+# W64: v_cndmask_b32_e64 v5, exec_hi, -1, s[6:7] ; encoding: [0x05,0x00,0x01,0xd5,0x7f,0x82,0x19,0x00]
+0x05,0x00,0x01,0xd5,0x7f,0x82,0x19,0x00
+
+# W32: v_cndmask_b32_e64 v5, null, exec_hi, s6   ; encoding: [0x05,0x00,0x01,0xd5,0x7c,0xfe,0x18,0x00]
+# W64: v_cndmask_b32_e64 v5, null, exec_hi, s[6:7] ; encoding: [0x05,0x00,0x01,0xd5,0x7c,0xfe,0x18,0x00]
+0x05,0x00,0x01,0xd5,0x7c,0xfe,0x18,0x00
+
+# W32: v_cndmask_b32_e64 v5, -1, m0, s104        ; encoding: [0x05,0x00,0x01,0xd5,0xc1,0xfa,0xa0,0x01]
+# W64: v_cndmask_b32_e64 v5, -1, m0, s[104:105]  ; encoding: [0x05,0x00,0x01,0xd5,0xc1,0xfa,0xa0,0x01]
+0x05,0x00,0x01,0xd5,0xc1,0xfa,0xa0,0x01
+
+# W32: v_cndmask_b32_e64 v5, 0.5, -|vcc_lo|, vcc_lo ; encoding: [0x05,0x02,0x01,0xd5,0xf0,0xd4,0xa8,0x41]
+# W64: v_cndmask_b32_e64 v5, 0.5, -|vcc_lo|, vcc ; encoding: [0x05,0x02,0x01,0xd5,0xf0,0xd4,0xa8,0x41]
+0x05,0x02,0x01,0xd5,0xf0,0xd4,0xa8,0x41
+
+# W32: v_cndmask_b32_e64 v5, -|src_scc|, null, ttmp14 ; encoding: [0x05,0x01,0x01,0xd5,0xfd,0xf8,0xe8,0x21]
+# W64: v_cndmask_b32_e64 v5, -|src_scc|, null, ttmp[14:15] ; encoding: [0x05,0x01,0x01,0xd5,0xfd,0xf8,0xe8,0x21]
+0x05,0x01,0x01,0xd5,0xfd,0xf8,0xe8,0x21
+
+# GFX12: v_cndmask_b32_e64 v255, -|0xaf123456|, -|vcc_hi|, null ; encoding: [0xff,0x03,0x01,0xd5,0xff,0xd6,0xf0,0x61,0x56,0x34,0x12,0xaf]
+0xff,0x03,0x01,0xd5,0xff,0xd6,0xf0,0x61,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64 v5, v1, v2     ; encoding: [0x05,0x00,0x2f,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x2f,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64 v5, v255, v255 ; encoding: [0x05,0x00,0x2f,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x2f,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64 v5, s1, s2     ; encoding: [0x05,0x00,0x2f,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x2f,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64 v5, s105, s105 ; encoding: [0x05,0x00,0x2f,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x2f,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64 v5, vcc_lo, ttmp15 ; encoding: [0x05,0x00,0x2f,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x2f,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x2f,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x2f,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64 v5, ttmp15, src_scc ; encoding: [0x05,0x00,0x2f,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x2f,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64 v5, m0, 0.5    ; encoding: [0x05,0x00,0x2f,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x2f,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64 v5, exec_lo, -1 ; encoding: [0x05,0x00,0x2f,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x2f,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64 v5, |exec_hi|, null ; encoding: [0x05,0x01,0x2f,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x01,0x2f,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64 v5, null, exec_lo ; encoding: [0x05,0x00,0x2f,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x2f,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64 v5, -1, exec_hi ; encoding: [0x05,0x00,0x2f,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x2f,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64 v5, 0.5, -m0   ; encoding: [0x05,0x00,0x2f,0xd5,0xf0,0xfa,0x00,0x40]
+0x05,0x00,0x2f,0xd5,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64 v5, -src_scc, |vcc_lo| ; encoding: [0x05,0x02,0x2f,0xd5,0xfd,0xd4,0x00,0x20]
+0x05,0x02,0x2f,0xd5,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64 v255, -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0xff,0x83,0x2f,0xd5,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0xff,0x83,0x2f,0xd5,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmac_f16_e64 v5, v1, v2               ; encoding: [0x05,0x00,0x36,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x36,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_fmac_f16_e64 v5, v255, v255           ; encoding: [0x05,0x00,0x36,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x36,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_fmac_f16_e64 v5, s1, s2               ; encoding: [0x05,0x00,0x36,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x36,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_fmac_f16_e64 v5, s105, s105           ; encoding: [0x05,0x00,0x36,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x36,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_fmac_f16_e64 v5, vcc_lo, ttmp15       ; encoding: [0x05,0x00,0x36,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x36,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_fmac_f16_e64 v5, vcc_hi, 0xfe0b       ; encoding: [0x05,0x00,0x36,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x36,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmac_f16_e64 v5, ttmp15, src_scc      ; encoding: [0x05,0x00,0x36,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x36,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_fmac_f16_e64 v5, m0, 0.5              ; encoding: [0x05,0x00,0x36,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x36,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_fmac_f16_e64 v5, exec_lo, -1          ; encoding: [0x05,0x00,0x36,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x36,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_fmac_f16_e64 v5, |exec_hi|, null      ; encoding: [0x05,0x01,0x36,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x01,0x36,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_fmac_f16_e64 v5, null, exec_lo        ; encoding: [0x05,0x00,0x36,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x36,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_fmac_f16_e64 v5, -1, exec_hi          ; encoding: [0x05,0x00,0x36,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x36,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_fmac_f16_e64 v5, 0.5, -m0 mul:2       ; encoding: [0x05,0x00,0x36,0xd5,0xf0,0xfa,0x00,0x48]
+0x05,0x00,0x36,0xd5,0xf0,0xfa,0x00,0x48
+
+# GFX12: v_fmac_f16_e64 v5, -src_scc, |vcc_lo| mul:4 ; encoding: [0x05,0x02,0x36,0xd5,0xfd,0xd4,0x00,0x30]
+0x05,0x02,0x36,0xd5,0xfd,0xd4,0x00,0x30
+
+# GFX12: v_fmac_f16_e64 v255, -|0xfe0b|, -|vcc_hi| clamp div:2 ; encoding: [0xff,0x83,0x36,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00]
+0xff,0x83,0x36,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_fmac_f32_e64 v5, v1, v2               ; encoding: [0x05,0x00,0x2b,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x2b,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_fmac_f32_e64 v5, v255, v255           ; encoding: [0x05,0x00,0x2b,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x2b,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_fmac_f32_e64 v5, s1, s2               ; encoding: [0x05,0x00,0x2b,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x2b,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_fmac_f32_e64 v5, s105, s105           ; encoding: [0x05,0x00,0x2b,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x2b,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_fmac_f32_e64 v5, vcc_lo, ttmp15       ; encoding: [0x05,0x00,0x2b,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x2b,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_fmac_f32_e64 v5, vcc_hi, 0xaf123456   ; encoding: [0x05,0x00,0x2b,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x2b,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fmac_f32_e64 v5, ttmp15, src_scc      ; encoding: [0x05,0x00,0x2b,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x2b,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_fmac_f32_e64 v5, m0, 0.5              ; encoding: [0x05,0x00,0x2b,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x2b,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_fmac_f32_e64 v5, exec_lo, -1          ; encoding: [0x05,0x00,0x2b,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x2b,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_fmac_f32_e64 v5, |exec_hi|, null      ; encoding: [0x05,0x01,0x2b,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x01,0x2b,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_fmac_f32_e64 v5, null, exec_lo        ; encoding: [0x05,0x00,0x2b,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x2b,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_fmac_f32_e64 v5, -1, exec_hi          ; encoding: [0x05,0x00,0x2b,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x2b,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_fmac_f32_e64 v5, 0.5, -m0 mul:2       ; encoding: [0x05,0x00,0x2b,0xd5,0xf0,0xfa,0x00,0x48]
+0x05,0x00,0x2b,0xd5,0xf0,0xfa,0x00,0x48
+
+# GFX12: v_fmac_f32_e64 v5, -src_scc, |vcc_lo| mul:4 ; encoding: [0x05,0x02,0x2b,0xd5,0xfd,0xd4,0x00,0x30]
+0x05,0x02,0x2b,0xd5,0xfd,0xd4,0x00,0x30
+
+# GFX12: v_fmac_f32_e64 v255, -|0xaf123456|, -|vcc_hi| clamp div:2 ; encoding: [0xff,0x83,0x2b,0xd5,0xff,0xd6,0x00,0x78,0x56,0x34,0x12,0xaf]
+0xff,0x83,0x2b,0xd5,0xff,0xd6,0x00,0x78,0x56,0x34,0x12,0xaf
+
+# GFX12: v_ldexp_f16_e64 v5, v1, v2              ; encoding: [0x05,0x00,0x3b,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x3b,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_ldexp_f16_e64 v5, v255, v255          ; encoding: [0x05,0x00,0x3b,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x3b,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_ldexp_f16_e64 v5, s1, s2              ; encoding: [0x05,0x00,0x3b,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x3b,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_ldexp_f16_e64 v5, s105, s105          ; encoding: [0x05,0x00,0x3b,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x3b,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_ldexp_f16_e64 v5, vcc_lo, ttmp15      ; encoding: [0x05,0x00,0x3b,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x3b,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_ldexp_f16_e64 v5, vcc_hi, 0xfe0b      ; encoding: [0x05,0x00,0x3b,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x3b,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_ldexp_f16_e64 v5, ttmp15, src_scc     ; encoding: [0x05,0x00,0x3b,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x3b,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_ldexp_f16_e64 v5, m0, 0.5             ; encoding: [0x05,0x00,0x3b,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x3b,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_ldexp_f16_e64 v5, exec_lo, -1         ; encoding: [0x05,0x00,0x3b,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x3b,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_ldexp_f16_e64 v5, exec_hi, null       ; encoding: [0x05,0x00,0x3b,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x3b,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_ldexp_f16_e64 v5, null, exec_lo       ; encoding: [0x05,0x00,0x3b,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x3b,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_ldexp_f16_e64 v5, -1, exec_hi         ; encoding: [0x05,0x00,0x3b,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x3b,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_ldexp_f16_e64 v5, 0.5, m0 mul:2       ; encoding: [0x05,0x00,0x3b,0xd5,0xf0,0xfa,0x00,0x08]
+0x05,0x00,0x3b,0xd5,0xf0,0xfa,0x00,0x08
+
+# GFX12: v_ldexp_f16_e64 v5, src_scc, vcc_lo mul:4 ; encoding: [0x05,0x00,0x3b,0xd5,0xfd,0xd4,0x00,0x10]
+0x05,0x00,0x3b,0xd5,0xfd,0xd4,0x00,0x10
+
+# GFX12: v_ldexp_f16_e64 v255, -|0xfe0b|, vcc_hi clamp div:2 ; encoding: [0xff,0x81,0x3b,0xd5,0xff,0xd6,0x00,0x38,0x0b,0xfe,0x00,0x00]
+0xff,0x81,0x3b,0xd5,0xff,0xd6,0x00,0x38,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_lshlrev_b32_e64 v5, v1, v2            ; encoding: [0x05,0x00,0x18,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x18,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_lshlrev_b32_e64 v5, v255, v255        ; encoding: [0x05,0x00,0x18,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x18,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_lshlrev_b32_e64 v5, s1, s2            ; encoding: [0x05,0x00,0x18,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x18,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_lshlrev_b32_e64 v5, s105, s105        ; encoding: [0x05,0x00,0x18,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x18,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_lshlrev_b32_e64 v5, vcc_lo, ttmp15    ; encoding: [0x05,0x00,0x18,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x18,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_lshlrev_b32_e64 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x18,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x18,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_lshlrev_b32_e64 v5, ttmp15, src_scc   ; encoding: [0x05,0x00,0x18,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x18,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_lshlrev_b32_e64 v5, m0, 0.5           ; encoding: [0x05,0x00,0x18,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x18,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_lshlrev_b32_e64 v5, exec_lo, -1       ; encoding: [0x05,0x00,0x18,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x18,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_lshlrev_b32_e64 v5, exec_hi, null     ; encoding: [0x05,0x00,0x18,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x18,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_lshlrev_b32_e64 v5, null, exec_lo     ; encoding: [0x05,0x00,0x18,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x18,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_lshlrev_b32_e64 v5, -1, exec_hi       ; encoding: [0x05,0x00,0x18,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x18,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_lshlrev_b32_e64 v5, 0.5, m0           ; encoding: [0x05,0x00,0x18,0xd5,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x18,0xd5,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_lshlrev_b32_e64 v5, src_scc, vcc_lo   ; encoding: [0x05,0x00,0x18,0xd5,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x18,0xd5,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_lshlrev_b32_e64 v255, 0xaf123456, vcc_hi ; encoding: [0xff,0x00,0x18,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x18,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_lshlrev_b64_e64 v[5:6], v1, v[2:3]    ; encoding: [0x05,0x00,0x1f,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x1f,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_lshlrev_b64_e64 v[5:6], v255, v[254:255] ; encoding: [0x05,0x00,0x1f,0xd5,0xff,0xfd,0x03,0x00]
+0x05,0x00,0x1f,0xd5,0xff,0xfd,0x03,0x00
+
+# GFX12: v_lshlrev_b64_e64 v[5:6], v1, vcc       ; encoding: [0x05,0x00,0x1f,0xd5,0x01,0xd5,0x00,0x00]
+0x05,0x00,0x1f,0xd5,0x01,0xd5,0x00,0x00
+
+# GFX12: v_lshlrev_b64_e64 v[5:6], v255, exec    ; encoding: [0x05,0x00,0x1f,0xd5,0xff,0xfd,0x00,0x00]
+0x05,0x00,0x1f,0xd5,0xff,0xfd,0x00,0x00
+
+# GFX12: v_lshlrev_b64_e64 v[5:6], null, null    ; encoding: [0x05,0x00,0x1f,0xd5,0x7c,0xf8,0x00,0x00]
+0x05,0x00,0x1f,0xd5,0x7c,0xf8,0x00,0x00
+
+# GFX12: v_lshlrev_b64_e64 v[5:6], -1, -1        ; encoding: [0x05,0x00,0x1f,0xd5,0xc1,0x82,0x01,0x00]
+0x05,0x00,0x1f,0xd5,0xc1,0x82,0x01,0x00
+
+# GFX12: v_lshlrev_b64_e64 v[5:6], 0.5, 0xaf123456 ; encoding: [0x05,0x00,0x1f,0xd5,0xf0,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x1f,0xd5,0xf0,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_lshlrev_b64_e64 v[5:6], src_scc, src_scc ; encoding: [0x05,0x00,0x1f,0xd5,0xfd,0xfa,0x01,0x00]
+0x05,0x00,0x1f,0xd5,0xfd,0xfa,0x01,0x00
+
+# GFX12: v_lshlrev_b64_e64 v[254:255], 0xaf123456, 0.5 ; encoding: [0xfe,0x00,0x1f,0xd5,0xff,0xe0,0x01,0x00,0x56,0x34,0x12,0xaf]
+0xfe,0x00,0x1f,0xd5,0xff,0xe0,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_lshrrev_b32_e64 v5, v1, v2            ; encoding: [0x05,0x00,0x19,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x19,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_lshrrev_b32_e64 v5, v255, v255        ; encoding: [0x05,0x00,0x19,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x19,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_lshrrev_b32_e64 v5, s1, s2            ; encoding: [0x05,0x00,0x19,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x19,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_lshrrev_b32_e64 v5, s105, s105        ; encoding: [0x05,0x00,0x19,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x19,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_lshrrev_b32_e64 v5, vcc_lo, ttmp15    ; encoding: [0x05,0x00,0x19,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x19,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_lshrrev_b32_e64 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x19,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x19,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_lshrrev_b32_e64 v5, ttmp15, src_scc   ; encoding: [0x05,0x00,0x19,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x19,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_lshrrev_b32_e64 v5, m0, 0.5           ; encoding: [0x05,0x00,0x19,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x19,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_lshrrev_b32_e64 v5, exec_lo, -1       ; encoding: [0x05,0x00,0x19,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x19,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_lshrrev_b32_e64 v5, exec_hi, null     ; encoding: [0x05,0x00,0x19,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x19,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_lshrrev_b32_e64 v5, null, exec_lo     ; encoding: [0x05,0x00,0x19,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x19,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_lshrrev_b32_e64 v5, -1, exec_hi       ; encoding: [0x05,0x00,0x19,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x19,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_lshrrev_b32_e64 v5, 0.5, m0           ; encoding: [0x05,0x00,0x19,0xd5,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x19,0xd5,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_lshrrev_b32_e64 v5, src_scc, vcc_lo   ; encoding: [0x05,0x00,0x19,0xd5,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x19,0xd5,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_lshrrev_b32_e64 v255, 0xaf123456, vcc_hi ; encoding: [0xff,0x00,0x19,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x19,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_max_num_f16_e64 v5, v1, v2            ; encoding: [0x05,0x00,0x31,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x31,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_max_num_f16_e64 v5, v255, v255        ; encoding: [0x05,0x00,0x31,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x31,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_max_num_f16_e64 v5, s1, s2            ; encoding: [0x05,0x00,0x31,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x31,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_max_num_f16_e64 v5, s105, s105        ; encoding: [0x05,0x00,0x31,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x31,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_max_num_f16_e64 v5, vcc_lo, ttmp15    ; encoding: [0x05,0x00,0x31,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x31,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_max_num_f16_e64 v5, vcc_hi, 0xfe0b    ; encoding: [0x05,0x00,0x31,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x31,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_max_num_f16_e64 v5, ttmp15, src_scc   ; encoding: [0x05,0x00,0x31,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x31,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_max_num_f16_e64 v5, m0, 0.5           ; encoding: [0x05,0x00,0x31,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x31,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_max_num_f16_e64 v5, exec_lo, -1       ; encoding: [0x05,0x00,0x31,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x31,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_max_num_f16_e64 v5, |exec_hi|, null   ; encoding: [0x05,0x01,0x31,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x01,0x31,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_max_num_f16_e64 v5, null, exec_lo     ; encoding: [0x05,0x00,0x31,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x31,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_max_num_f16_e64 v5, -1, exec_hi       ; encoding: [0x05,0x00,0x31,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x31,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_max_num_f16_e64 v5, 0.5, -m0 mul:2    ; encoding: [0x05,0x00,0x31,0xd5,0xf0,0xfa,0x00,0x48]
+0x05,0x00,0x31,0xd5,0xf0,0xfa,0x00,0x48
+
+# GFX12: v_max_num_f16_e64 v5, -src_scc, |vcc_lo| mul:4 ; encoding: [0x05,0x02,0x31,0xd5,0xfd,0xd4,0x00,0x30]
+0x05,0x02,0x31,0xd5,0xfd,0xd4,0x00,0x30
+
+# GFX12: v_max_num_f16_e64 v255, -|0xfe0b|, -|vcc_hi| clamp div:2 ; encoding: [0xff,0x83,0x31,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00]
+0xff,0x83,0x31,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_max_num_f32_e64 v5, v1, v2            ; encoding: [0x05,0x00,0x16,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x16,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_max_num_f32_e64 v5, v255, v255        ; encoding: [0x05,0x00,0x16,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x16,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_max_num_f32_e64 v5, s1, s2            ; encoding: [0x05,0x00,0x16,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x16,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_max_num_f32_e64 v5, s105, s105        ; encoding: [0x05,0x00,0x16,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x16,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_max_num_f32_e64 v5, vcc_lo, ttmp15    ; encoding: [0x05,0x00,0x16,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x16,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_max_num_f32_e64 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x16,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x16,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_max_num_f32_e64 v5, ttmp15, src_scc   ; encoding: [0x05,0x00,0x16,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x16,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_max_num_f32_e64 v5, m0, 0.5           ; encoding: [0x05,0x00,0x16,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x16,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_max_num_f32_e64 v5, exec_lo, -1       ; encoding: [0x05,0x00,0x16,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x16,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_max_num_f32_e64 v5, |exec_hi|, null   ; encoding: [0x05,0x01,0x16,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x01,0x16,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_max_num_f32_e64 v5, null, exec_lo     ; encoding: [0x05,0x00,0x16,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x16,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_max_num_f32_e64 v5, -1, exec_hi       ; encoding: [0x05,0x00,0x16,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x16,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_max_num_f32_e64 v5, 0.5, -m0 mul:2    ; encoding: [0x05,0x00,0x16,0xd5,0xf0,0xfa,0x00,0x48]
+0x05,0x00,0x16,0xd5,0xf0,0xfa,0x00,0x48
+
+# GFX12: v_max_num_f32_e64 v5, -src_scc, |vcc_lo| mul:4 ; encoding: [0x05,0x02,0x16,0xd5,0xfd,0xd4,0x00,0x30]
+0x05,0x02,0x16,0xd5,0xfd,0xd4,0x00,0x30
+
+# GFX12: v_max_num_f32_e64 v255, -|0xaf123456|, -|vcc_hi| clamp div:2 ; encoding: [0xff,0x83,0x16,0xd5,0xff,0xd6,0x00,0x78,0x56,0x34,0x12,0xaf]
+0xff,0x83,0x16,0xd5,0xff,0xd6,0x00,0x78,0x56,0x34,0x12,0xaf
+
+# GFX12: v_max_num_f64_e64 v[5:6], v[2:3], v[4:5] ; encoding: [0x05,0x00,0x0e,0xd5,0x02,0x09,0x02,0x00]
+0x05,0x00,0x0e,0xd5,0x02,0x09,0x02,0x00
+
+# GFX12: v_max_num_f64_e64 v[5:6], v[104:105], v[104:105] ; encoding: [0x05,0x00,0x0e,0xd5,0x68,0xd1,0x02,0x00]
+0x05,0x00,0x0e,0xd5,0x68,0xd1,0x02,0x00
+
+# GFX12: v_max_num_f64_e64 v[5:6], s[2:3], s[4:5] ; encoding: [0x05,0x00,0x0e,0xd5,0x02,0x08,0x00,0x00]
+0x05,0x00,0x0e,0xd5,0x02,0x08,0x00,0x00
+
+# GFX12: v_max_num_f64_e64 v[5:6], s[104:105], s[104:105] ; encoding: [0x05,0x00,0x0e,0xd5,0x68,0xd0,0x00,0x00]
+0x05,0x00,0x0e,0xd5,0x68,0xd0,0x00,0x00
+
+# GFX12: v_max_num_f64_e64 v[5:6], vcc, ttmp[14:15] ; encoding: [0x05,0x00,0x0e,0xd5,0x6a,0xf4,0x00,0x00]
+0x05,0x00,0x0e,0xd5,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_max_num_f64_e64 v[5:6], ttmp[14:15], 0xaf123456 ; encoding: [0x05,0x00,0x0e,0xd5,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x0e,0xd5,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_max_num_f64_e64 v[5:6], -|exec|, src_scc ; encoding: [0x05,0x01,0x0e,0xd5,0x7e,0xfa,0x01,0x20]
+0x05,0x01,0x0e,0xd5,0x7e,0xfa,0x01,0x20
+
+# GFX12: v_max_num_f64_e64 v[5:6], null, 0.5     ; encoding: [0x05,0x00,0x0e,0xd5,0x7c,0xe0,0x01,0x00]
+0x05,0x00,0x0e,0xd5,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_max_num_f64_e64 v[5:6], -1, -1        ; encoding: [0x05,0x00,0x0e,0xd5,0xc1,0x82,0x01,0x00]
+0x05,0x00,0x0e,0xd5,0xc1,0x82,0x01,0x00
+
+# GFX12: v_max_num_f64_e64 v[5:6], 0.5, null mul:2 ; encoding: [0x05,0x00,0x0e,0xd5,0xf0,0xf8,0x00,0x08]
+0x05,0x00,0x0e,0xd5,0xf0,0xf8,0x00,0x08
+
+# GFX12: v_max_num_f64_e64 v[5:6], -|src_scc|, -|exec| mul:4 ; encoding: [0x05,0x03,0x0e,0xd5,0xfd,0xfc,0x00,0x70]
+0x05,0x03,0x0e,0xd5,0xfd,0xfc,0x00,0x70
+
+# GFX12: v_max_num_f64_e64 v[254:255], 0xaf123456, -|vcc| clamp div:2 ; encoding: [0xfe,0x82,0x0e,0xd5,0xff,0xd4,0x00,0x58,0x56,0x34,0x12,0xaf]
+0xfe,0x82,0x0e,0xd5,0xff,0xd4,0x00,0x58,0x56,0x34,0x12,0xaf
+
+# GFX12: v_max_i32_e64 v5, v1, v2                ; encoding: [0x05,0x00,0x12,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x12,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_max_i32_e64 v5, v255, v255            ; encoding: [0x05,0x00,0x12,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x12,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_max_i32_e64 v5, s1, s2                ; encoding: [0x05,0x00,0x12,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x12,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_max_i32_e64 v5, s105, s105            ; encoding: [0x05,0x00,0x12,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x12,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_max_i32_e64 v5, vcc_lo, ttmp15        ; encoding: [0x05,0x00,0x12,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x12,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_max_i32_e64 v5, vcc_hi, 0xaf123456    ; encoding: [0x05,0x00,0x12,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x12,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_max_i32_e64 v5, ttmp15, src_scc       ; encoding: [0x05,0x00,0x12,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x12,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_max_i32_e64 v5, m0, 0.5               ; encoding: [0x05,0x00,0x12,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x12,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_max_i32_e64 v5, exec_lo, -1           ; encoding: [0x05,0x00,0x12,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x12,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_max_i32_e64 v5, exec_hi, null         ; encoding: [0x05,0x00,0x12,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x12,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_max_i32_e64 v5, null, exec_lo         ; encoding: [0x05,0x00,0x12,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x12,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_max_i32_e64 v5, -1, exec_hi           ; encoding: [0x05,0x00,0x12,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x12,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_max_i32_e64 v5, 0.5, m0               ; encoding: [0x05,0x00,0x12,0xd5,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x12,0xd5,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_max_i32_e64 v5, src_scc, vcc_lo       ; encoding: [0x05,0x00,0x12,0xd5,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x12,0xd5,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_max_i32_e64 v255, 0xaf123456, vcc_hi  ; encoding: [0xff,0x00,0x12,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x12,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_max_u32_e64 v5, v1, v2                ; encoding: [0x05,0x00,0x14,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x14,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_max_u32_e64 v5, v255, v255            ; encoding: [0x05,0x00,0x14,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x14,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_max_u32_e64 v5, s1, s2                ; encoding: [0x05,0x00,0x14,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x14,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_max_u32_e64 v5, s105, s105            ; encoding: [0x05,0x00,0x14,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x14,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_max_u32_e64 v5, vcc_lo, ttmp15        ; encoding: [0x05,0x00,0x14,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x14,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_max_u32_e64 v5, vcc_hi, 0xaf123456    ; encoding: [0x05,0x00,0x14,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x14,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_max_u32_e64 v5, ttmp15, src_scc       ; encoding: [0x05,0x00,0x14,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x14,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_max_u32_e64 v5, m0, 0.5               ; encoding: [0x05,0x00,0x14,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x14,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_max_u32_e64 v5, exec_lo, -1           ; encoding: [0x05,0x00,0x14,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x14,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_max_u32_e64 v5, exec_hi, null         ; encoding: [0x05,0x00,0x14,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x14,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_max_u32_e64 v5, null, exec_lo         ; encoding: [0x05,0x00,0x14,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x14,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_max_u32_e64 v5, -1, exec_hi           ; encoding: [0x05,0x00,0x14,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x14,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_max_u32_e64 v5, 0.5, m0               ; encoding: [0x05,0x00,0x14,0xd5,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x14,0xd5,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_max_u32_e64 v5, src_scc, vcc_lo       ; encoding: [0x05,0x00,0x14,0xd5,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x14,0xd5,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_max_u32_e64 v255, 0xaf123456, vcc_hi  ; encoding: [0xff,0x00,0x14,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x14,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_min_num_f16_e64 v5, v1, v2            ; encoding: [0x05,0x00,0x30,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x30,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_min_num_f16_e64 v5, v255, v255        ; encoding: [0x05,0x00,0x30,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x30,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_min_num_f16_e64 v5, s1, s2            ; encoding: [0x05,0x00,0x30,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x30,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_min_num_f16_e64 v5, s105, s105        ; encoding: [0x05,0x00,0x30,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x30,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_min_num_f16_e64 v5, vcc_lo, ttmp15    ; encoding: [0x05,0x00,0x30,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x30,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_min_num_f16_e64 v5, vcc_hi, 0xfe0b    ; encoding: [0x05,0x00,0x30,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x30,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_min_num_f16_e64 v5, ttmp15, src_scc   ; encoding: [0x05,0x00,0x30,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x30,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_min_num_f16_e64 v5, m0, 0.5           ; encoding: [0x05,0x00,0x30,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x30,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_min_num_f16_e64 v5, exec_lo, -1       ; encoding: [0x05,0x00,0x30,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x30,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_min_num_f16_e64 v5, |exec_hi|, null   ; encoding: [0x05,0x01,0x30,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x01,0x30,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_min_num_f16_e64 v5, null, exec_lo     ; encoding: [0x05,0x00,0x30,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x30,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_min_num_f16_e64 v5, -1, exec_hi       ; encoding: [0x05,0x00,0x30,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x30,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_min_num_f16_e64 v5, 0.5, -m0 mul:2    ; encoding: [0x05,0x00,0x30,0xd5,0xf0,0xfa,0x00,0x48]
+0x05,0x00,0x30,0xd5,0xf0,0xfa,0x00,0x48
+
+# GFX12: v_min_num_f16_e64 v5, -src_scc, |vcc_lo| mul:4 ; encoding: [0x05,0x02,0x30,0xd5,0xfd,0xd4,0x00,0x30]
+0x05,0x02,0x30,0xd5,0xfd,0xd4,0x00,0x30
+
+# GFX12: v_min_num_f16_e64 v255, -|0xfe0b|, -|vcc_hi| clamp div:2 ; encoding: [0xff,0x83,0x30,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00]
+0xff,0x83,0x30,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_min_num_f32_e64 v5, v1, v2            ; encoding: [0x05,0x00,0x15,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x15,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_min_num_f32_e64 v5, v255, v255        ; encoding: [0x05,0x00,0x15,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x15,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_min_num_f32_e64 v5, s1, s2            ; encoding: [0x05,0x00,0x15,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x15,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_min_num_f32_e64 v5, s105, s105        ; encoding: [0x05,0x00,0x15,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x15,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_min_num_f32_e64 v5, vcc_lo, ttmp15    ; encoding: [0x05,0x00,0x15,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x15,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_min_num_f32_e64 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x15,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x15,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_min_num_f32_e64 v5, ttmp15, src_scc   ; encoding: [0x05,0x00,0x15,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x15,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_min_num_f32_e64 v5, m0, 0.5           ; encoding: [0x05,0x00,0x15,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x15,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_min_num_f32_e64 v5, exec_lo, -1       ; encoding: [0x05,0x00,0x15,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x15,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_min_num_f32_e64 v5, |exec_hi|, null   ; encoding: [0x05,0x01,0x15,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x01,0x15,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_min_num_f32_e64 v5, null, exec_lo     ; encoding: [0x05,0x00,0x15,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x15,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_min_num_f32_e64 v5, -1, exec_hi       ; encoding: [0x05,0x00,0x15,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x15,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_min_num_f32_e64 v5, 0.5, -m0 mul:2    ; encoding: [0x05,0x00,0x15,0xd5,0xf0,0xfa,0x00,0x48]
+0x05,0x00,0x15,0xd5,0xf0,0xfa,0x00,0x48
+
+# GFX12: v_min_num_f32_e64 v5, -src_scc, |vcc_lo| mul:4 ; encoding: [0x05,0x02,0x15,0xd5,0xfd,0xd4,0x00,0x30]
+0x05,0x02,0x15,0xd5,0xfd,0xd4,0x00,0x30
+
+# GFX12: v_min_num_f32_e64 v255, -|0xaf123456|, -|vcc_hi| clamp div:2 ; encoding: [0xff,0x83,0x15,0xd5,0xff,0xd6,0x00,0x78,0x56,0x34,0x12,0xaf]
+0xff,0x83,0x15,0xd5,0xff,0xd6,0x00,0x78,0x56,0x34,0x12,0xaf
+
+# GFX12: v_min_num_f64_e64 v[5:6], v[2:3], v[4:5] ; encoding: [0x05,0x00,0x0d,0xd5,0x02,0x09,0x02,0x00]
+0x05,0x00,0x0d,0xd5,0x02,0x09,0x02,0x00
+
+# GFX12: v_min_num_f64_e64 v[5:6], v[104:105], v[104:105] ; encoding: [0x05,0x00,0x0d,0xd5,0x68,0xd1,0x02,0x00]
+0x05,0x00,0x0d,0xd5,0x68,0xd1,0x02,0x00
+
+# GFX12: v_min_num_f64_e64 v[5:6], s[2:3], s[4:5] ; encoding: [0x05,0x00,0x0d,0xd5,0x02,0x08,0x00,0x00]
+0x05,0x00,0x0d,0xd5,0x02,0x08,0x00,0x00
+
+# GFX12: v_min_num_f64_e64 v[5:6], s[104:105], s[104:105] ; encoding: [0x05,0x00,0x0d,0xd5,0x68,0xd0,0x00,0x00]
+0x05,0x00,0x0d,0xd5,0x68,0xd0,0x00,0x00
+
+# GFX12: v_min_num_f64_e64 v[5:6], vcc, ttmp[14:15] ; encoding: [0x05,0x00,0x0d,0xd5,0x6a,0xf4,0x00,0x00]
+0x05,0x00,0x0d,0xd5,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_min_num_f64_e64 v[5:6], ttmp[14:15], 0xaf123456 ; encoding: [0x05,0x00,0x0d,0xd5,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x0d,0xd5,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_min_num_f64_e64 v[5:6], -|exec|, src_scc ; encoding: [0x05,0x01,0x0d,0xd5,0x7e,0xfa,0x01,0x20]
+0x05,0x01,0x0d,0xd5,0x7e,0xfa,0x01,0x20
+
+# GFX12: v_min_num_f64_e64 v[5:6], null, 0.5     ; encoding: [0x05,0x00,0x0d,0xd5,0x7c,0xe0,0x01,0x00]
+0x05,0x00,0x0d,0xd5,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_min_num_f64_e64 v[5:6], -1, -1        ; encoding: [0x05,0x00,0x0d,0xd5,0xc1,0x82,0x01,0x00]
+0x05,0x00,0x0d,0xd5,0xc1,0x82,0x01,0x00
+
+# GFX12: v_min_num_f64_e64 v[5:6], 0.5, null mul:2 ; encoding: [0x05,0x00,0x0d,0xd5,0xf0,0xf8,0x00,0x08]
+0x05,0x00,0x0d,0xd5,0xf0,0xf8,0x00,0x08
+
+# GFX12: v_min_num_f64_e64 v[5:6], -|src_scc|, -|exec| mul:4 ; encoding: [0x05,0x03,0x0d,0xd5,0xfd,0xfc,0x00,0x70]
+0x05,0x03,0x0d,0xd5,0xfd,0xfc,0x00,0x70
+
+# GFX12: v_min_num_f64_e64 v[254:255], 0xaf123456, -|vcc| clamp div:2 ; encoding: [0xfe,0x82,0x0d,0xd5,0xff,0xd4,0x00,0x58,0x56,0x34,0x12,0xaf]
+0xfe,0x82,0x0d,0xd5,0xff,0xd4,0x00,0x58,0x56,0x34,0x12,0xaf
+
+# GFX12: v_min_i32_e64 v5, v1, v2                ; encoding: [0x05,0x00,0x11,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x11,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_min_i32_e64 v5, v255, v255            ; encoding: [0x05,0x00,0x11,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x11,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_min_i32_e64 v5, s1, s2                ; encoding: [0x05,0x00,0x11,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x11,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_min_i32_e64 v5, s105, s105            ; encoding: [0x05,0x00,0x11,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x11,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_min_i32_e64 v5, vcc_lo, ttmp15        ; encoding: [0x05,0x00,0x11,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x11,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_min_i32_e64 v5, vcc_hi, 0xaf123456    ; encoding: [0x05,0x00,0x11,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x11,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_min_i32_e64 v5, ttmp15, src_scc       ; encoding: [0x05,0x00,0x11,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x11,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_min_i32_e64 v5, m0, 0.5               ; encoding: [0x05,0x00,0x11,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x11,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_min_i32_e64 v5, exec_lo, -1           ; encoding: [0x05,0x00,0x11,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x11,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_min_i32_e64 v5, exec_hi, null         ; encoding: [0x05,0x00,0x11,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x11,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_min_i32_e64 v5, null, exec_lo         ; encoding: [0x05,0x00,0x11,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x11,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_min_i32_e64 v5, -1, exec_hi           ; encoding: [0x05,0x00,0x11,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x11,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_min_i32_e64 v5, 0.5, m0               ; encoding: [0x05,0x00,0x11,0xd5,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x11,0xd5,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_min_i32_e64 v5, src_scc, vcc_lo       ; encoding: [0x05,0x00,0x11,0xd5,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x11,0xd5,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_min_i32_e64 v255, 0xaf123456, vcc_hi  ; encoding: [0xff,0x00,0x11,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x11,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_min_u32_e64 v5, v1, v2                ; encoding: [0x05,0x00,0x13,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x13,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_min_u32_e64 v5, v255, v255            ; encoding: [0x05,0x00,0x13,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x13,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_min_u32_e64 v5, s1, s2                ; encoding: [0x05,0x00,0x13,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x13,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_min_u32_e64 v5, s105, s105            ; encoding: [0x05,0x00,0x13,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x13,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_min_u32_e64 v5, vcc_lo, ttmp15        ; encoding: [0x05,0x00,0x13,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x13,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_min_u32_e64 v5, vcc_hi, 0xaf123456    ; encoding: [0x05,0x00,0x13,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x13,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_min_u32_e64 v5, ttmp15, src_scc       ; encoding: [0x05,0x00,0x13,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x13,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_min_u32_e64 v5, m0, 0.5               ; encoding: [0x05,0x00,0x13,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x13,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_min_u32_e64 v5, exec_lo, -1           ; encoding: [0x05,0x00,0x13,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x13,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_min_u32_e64 v5, exec_hi, null         ; encoding: [0x05,0x00,0x13,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x13,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_min_u32_e64 v5, null, exec_lo         ; encoding: [0x05,0x00,0x13,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x13,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_min_u32_e64 v5, -1, exec_hi           ; encoding: [0x05,0x00,0x13,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x13,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_min_u32_e64 v5, 0.5, m0               ; encoding: [0x05,0x00,0x13,0xd5,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x13,0xd5,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_min_u32_e64 v5, src_scc, vcc_lo       ; encoding: [0x05,0x00,0x13,0xd5,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x13,0xd5,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_min_u32_e64 v255, 0xaf123456, vcc_hi  ; encoding: [0xff,0x00,0x13,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x13,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mul_dx9_zero_f32_e64 v5, v1, v2       ; encoding: [0x05,0x00,0x07,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x07,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_mul_dx9_zero_f32_e64 v5, v255, v255   ; encoding: [0x05,0x00,0x07,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x07,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_mul_dx9_zero_f32_e64 v5, s1, s2       ; encoding: [0x05,0x00,0x07,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x07,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_mul_dx9_zero_f32_e64 v5, s105, s105   ; encoding: [0x05,0x00,0x07,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x07,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_mul_dx9_zero_f32_e64 v5, vcc_lo, ttmp15 ; encoding: [0x05,0x00,0x07,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x07,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_mul_dx9_zero_f32_e64 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x07,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x07,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mul_dx9_zero_f32_e64 v5, ttmp15, src_scc ; encoding: [0x05,0x00,0x07,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x07,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_mul_dx9_zero_f32_e64 v5, m0, 0.5      ; encoding: [0x05,0x00,0x07,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x07,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_mul_dx9_zero_f32_e64 v5, exec_lo, -1  ; encoding: [0x05,0x00,0x07,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x07,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_mul_dx9_zero_f32_e64 v5, |exec_hi|, null ; encoding: [0x05,0x01,0x07,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x01,0x07,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_mul_dx9_zero_f32_e64 v5, null, exec_lo ; encoding: [0x05,0x00,0x07,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x07,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_mul_dx9_zero_f32_e64 v5, -1, exec_hi  ; encoding: [0x05,0x00,0x07,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x07,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_mul_dx9_zero_f32_e64 v5, 0.5, -m0 mul:2 ; encoding: [0x05,0x00,0x07,0xd5,0xf0,0xfa,0x00,0x48]
+0x05,0x00,0x07,0xd5,0xf0,0xfa,0x00,0x48
+
+# GFX12: v_mul_dx9_zero_f32_e64 v5, -src_scc, |vcc_lo| mul:4 ; encoding: [0x05,0x02,0x07,0xd5,0xfd,0xd4,0x00,0x30]
+0x05,0x02,0x07,0xd5,0xfd,0xd4,0x00,0x30
+
+# GFX12: v_mul_dx9_zero_f32_e64 v255, -|0xaf123456|, -|vcc_hi| clamp div:2 ; encoding: [0xff,0x83,0x07,0xd5,0xff,0xd6,0x00,0x78,0x56,0x34,0x12,0xaf]
+0xff,0x83,0x07,0xd5,0xff,0xd6,0x00,0x78,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mul_f16_e64 v5, v1, v2                ; encoding: [0x05,0x00,0x35,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x35,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_mul_f16_e64 v5, v255, v255            ; encoding: [0x05,0x00,0x35,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x35,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_mul_f16_e64 v5, s1, s2                ; encoding: [0x05,0x00,0x35,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x35,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_mul_f16_e64 v5, s105, s105            ; encoding: [0x05,0x00,0x35,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x35,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_mul_f16_e64 v5, vcc_lo, ttmp15        ; encoding: [0x05,0x00,0x35,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x35,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_mul_f16_e64 v5, vcc_hi, 0xfe0b        ; encoding: [0x05,0x00,0x35,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x35,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_mul_f16_e64 v5, ttmp15, src_scc       ; encoding: [0x05,0x00,0x35,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x35,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_mul_f16_e64 v5, m0, 0.5               ; encoding: [0x05,0x00,0x35,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x35,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_mul_f16_e64 v5, exec_lo, -1           ; encoding: [0x05,0x00,0x35,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x35,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_mul_f16_e64 v5, |exec_hi|, null       ; encoding: [0x05,0x01,0x35,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x01,0x35,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_mul_f16_e64 v5, null, exec_lo         ; encoding: [0x05,0x00,0x35,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x35,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_mul_f16_e64 v5, -1, exec_hi           ; encoding: [0x05,0x00,0x35,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x35,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_mul_f16_e64 v5, 0.5, -m0 mul:2        ; encoding: [0x05,0x00,0x35,0xd5,0xf0,0xfa,0x00,0x48]
+0x05,0x00,0x35,0xd5,0xf0,0xfa,0x00,0x48
+
+# GFX12: v_mul_f16_e64 v5, -src_scc, |vcc_lo| mul:4 ; encoding: [0x05,0x02,0x35,0xd5,0xfd,0xd4,0x00,0x30]
+0x05,0x02,0x35,0xd5,0xfd,0xd4,0x00,0x30
+
+# GFX12: v_mul_f16_e64 v255, -|0xfe0b|, -|vcc_hi| clamp div:2 ; encoding: [0xff,0x83,0x35,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00]
+0xff,0x83,0x35,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_mul_f32_e64 v5, v1, v2                ; encoding: [0x05,0x00,0x08,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x08,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_mul_f32_e64 v5, v255, v255            ; encoding: [0x05,0x00,0x08,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x08,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_mul_f32_e64 v5, s1, s2                ; encoding: [0x05,0x00,0x08,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x08,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_mul_f32_e64 v5, s105, s105            ; encoding: [0x05,0x00,0x08,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x08,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_mul_f32_e64 v5, vcc_lo, ttmp15        ; encoding: [0x05,0x00,0x08,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x08,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_mul_f32_e64 v5, vcc_hi, 0xaf123456    ; encoding: [0x05,0x00,0x08,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x08,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mul_f32_e64 v5, ttmp15, src_scc       ; encoding: [0x05,0x00,0x08,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x08,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_mul_f32_e64 v5, m0, 0.5               ; encoding: [0x05,0x00,0x08,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x08,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_mul_f32_e64 v5, exec_lo, -1           ; encoding: [0x05,0x00,0x08,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x08,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_mul_f32_e64 v5, |exec_hi|, null       ; encoding: [0x05,0x01,0x08,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x01,0x08,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_mul_f32_e64 v5, null, exec_lo         ; encoding: [0x05,0x00,0x08,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x08,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_mul_f32_e64 v5, -1, exec_hi           ; encoding: [0x05,0x00,0x08,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x08,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_mul_f32_e64 v5, 0.5, -m0 mul:2        ; encoding: [0x05,0x00,0x08,0xd5,0xf0,0xfa,0x00,0x48]
+0x05,0x00,0x08,0xd5,0xf0,0xfa,0x00,0x48
+
+# GFX12: v_mul_f32_e64 v5, -src_scc, |vcc_lo| mul:4 ; encoding: [0x05,0x02,0x08,0xd5,0xfd,0xd4,0x00,0x30]
+0x05,0x02,0x08,0xd5,0xfd,0xd4,0x00,0x30
+
+# GFX12: v_mul_f32_e64 v255, -|0xaf123456|, -|vcc_hi| clamp div:2 ; encoding: [0xff,0x83,0x08,0xd5,0xff,0xd6,0x00,0x78,0x56,0x34,0x12,0xaf]
+0xff,0x83,0x08,0xd5,0xff,0xd6,0x00,0x78,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mul_f64_e64 v[5:6], v[2:3], v[4:5]    ; encoding: [0x05,0x00,0x06,0xd5,0x02,0x09,0x02,0x00]
+0x05,0x00,0x06,0xd5,0x02,0x09,0x02,0x00
+
+# GFX12: v_mul_f64_e64 v[5:6], v[104:105], v[104:105] ; encoding: [0x05,0x00,0x06,0xd5,0x68,0xd1,0x02,0x00]
+0x05,0x00,0x06,0xd5,0x68,0xd1,0x02,0x00
+
+# GFX12: v_mul_f64_e64 v[5:6], s[2:3], s[4:5]    ; encoding: [0x05,0x00,0x06,0xd5,0x02,0x08,0x00,0x00]
+0x05,0x00,0x06,0xd5,0x02,0x08,0x00,0x00
+
+# GFX12: v_mul_f64_e64 v[5:6], s[104:105], s[104:105] ; encoding: [0x05,0x00,0x06,0xd5,0x68,0xd0,0x00,0x00]
+0x05,0x00,0x06,0xd5,0x68,0xd0,0x00,0x00
+
+# GFX12: v_mul_f64_e64 v[5:6], vcc, ttmp[14:15]  ; encoding: [0x05,0x00,0x06,0xd5,0x6a,0xf4,0x00,0x00]
+0x05,0x00,0x06,0xd5,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_mul_f64_e64 v[5:6], ttmp[14:15], 0xaf123456 ; encoding: [0x05,0x00,0x06,0xd5,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x06,0xd5,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mul_f64_e64 v[5:6], -|exec|, src_scc  ; encoding: [0x05,0x01,0x06,0xd5,0x7e,0xfa,0x01,0x20]
+0x05,0x01,0x06,0xd5,0x7e,0xfa,0x01,0x20
+
+# GFX12: v_mul_f64_e64 v[5:6], null, 0.5         ; encoding: [0x05,0x00,0x06,0xd5,0x7c,0xe0,0x01,0x00]
+0x05,0x00,0x06,0xd5,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_mul_f64_e64 v[5:6], -1, -1            ; encoding: [0x05,0x00,0x06,0xd5,0xc1,0x82,0x01,0x00]
+0x05,0x00,0x06,0xd5,0xc1,0x82,0x01,0x00
+
+# GFX12: v_mul_f64_e64 v[5:6], 0.5, null mul:2   ; encoding: [0x05,0x00,0x06,0xd5,0xf0,0xf8,0x00,0x08]
+0x05,0x00,0x06,0xd5,0xf0,0xf8,0x00,0x08
+
+# GFX12: v_mul_f64_e64 v[5:6], -|src_scc|, -|exec| mul:4 ; encoding: [0x05,0x03,0x06,0xd5,0xfd,0xfc,0x00,0x70]
+0x05,0x03,0x06,0xd5,0xfd,0xfc,0x00,0x70
+
+# GFX12: v_mul_f64_e64 v[254:255], 0xaf123456, -|vcc| clamp div:2 ; encoding: [0xfe,0x82,0x06,0xd5,0xff,0xd4,0x00,0x58,0x56,0x34,0x12,0xaf]
+0xfe,0x82,0x06,0xd5,0xff,0xd4,0x00,0x58,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mul_hi_i32_i24_e64 v5, v1, v2         ; encoding: [0x05,0x00,0x0a,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x0a,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_mul_hi_i32_i24_e64 v5, v255, v255     ; encoding: [0x05,0x00,0x0a,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x0a,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_mul_hi_i32_i24_e64 v5, s1, s2         ; encoding: [0x05,0x00,0x0a,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x0a,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_mul_hi_i32_i24_e64 v5, s105, s105     ; encoding: [0x05,0x00,0x0a,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x0a,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_mul_hi_i32_i24_e64 v5, vcc_lo, ttmp15 ; encoding: [0x05,0x00,0x0a,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x0a,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_mul_hi_i32_i24_e64 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x0a,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x0a,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mul_hi_i32_i24_e64 v5, ttmp15, src_scc ; encoding: [0x05,0x00,0x0a,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x0a,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_mul_hi_i32_i24_e64 v5, m0, 0.5        ; encoding: [0x05,0x00,0x0a,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x0a,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_mul_hi_i32_i24_e64 v5, exec_lo, -1    ; encoding: [0x05,0x00,0x0a,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x0a,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_mul_hi_i32_i24_e64 v5, exec_hi, null  ; encoding: [0x05,0x00,0x0a,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x0a,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_mul_hi_i32_i24_e64 v5, null, exec_lo  ; encoding: [0x05,0x00,0x0a,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x0a,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_mul_hi_i32_i24_e64 v5, -1, exec_hi    ; encoding: [0x05,0x00,0x0a,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x0a,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_mul_hi_i32_i24_e64 v5, 0.5, m0        ; encoding: [0x05,0x00,0x0a,0xd5,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x0a,0xd5,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_mul_hi_i32_i24_e64 v5, src_scc, vcc_lo ; encoding: [0x05,0x00,0x0a,0xd5,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x0a,0xd5,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_mul_hi_i32_i24_e64 v255, 0xaf123456, vcc_hi ; encoding: [0xff,0x00,0x0a,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x0a,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mul_hi_u32_u24_e64 v5, v1, v2         ; encoding: [0x05,0x00,0x0c,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x0c,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_mul_hi_u32_u24_e64 v5, v255, v255     ; encoding: [0x05,0x00,0x0c,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x0c,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_mul_hi_u32_u24_e64 v5, s1, s2         ; encoding: [0x05,0x00,0x0c,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x0c,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_mul_hi_u32_u24_e64 v5, s105, s105     ; encoding: [0x05,0x00,0x0c,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x0c,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_mul_hi_u32_u24_e64 v5, vcc_lo, ttmp15 ; encoding: [0x05,0x00,0x0c,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x0c,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_mul_hi_u32_u24_e64 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x0c,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x0c,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mul_hi_u32_u24_e64 v5, ttmp15, src_scc ; encoding: [0x05,0x00,0x0c,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x0c,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_mul_hi_u32_u24_e64 v5, m0, 0.5        ; encoding: [0x05,0x00,0x0c,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x0c,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_mul_hi_u32_u24_e64 v5, exec_lo, -1    ; encoding: [0x05,0x00,0x0c,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x0c,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_mul_hi_u32_u24_e64 v5, exec_hi, null  ; encoding: [0x05,0x00,0x0c,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x0c,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_mul_hi_u32_u24_e64 v5, null, exec_lo  ; encoding: [0x05,0x00,0x0c,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x0c,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_mul_hi_u32_u24_e64 v5, -1, exec_hi    ; encoding: [0x05,0x00,0x0c,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x0c,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_mul_hi_u32_u24_e64 v5, 0.5, m0        ; encoding: [0x05,0x00,0x0c,0xd5,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x0c,0xd5,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_mul_hi_u32_u24_e64 v5, src_scc, vcc_lo ; encoding: [0x05,0x00,0x0c,0xd5,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x0c,0xd5,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_mul_hi_u32_u24_e64 v255, 0xaf123456, vcc_hi ; encoding: [0xff,0x00,0x0c,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x0c,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mul_i32_i24_e64 v5, v1, v2            ; encoding: [0x05,0x00,0x09,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x09,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_mul_i32_i24_e64 v5, v255, v255        ; encoding: [0x05,0x00,0x09,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x09,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_mul_i32_i24_e64 v5, s1, s2            ; encoding: [0x05,0x00,0x09,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x09,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_mul_i32_i24_e64 v5, s105, s105        ; encoding: [0x05,0x00,0x09,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x09,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_mul_i32_i24_e64 v5, vcc_lo, ttmp15    ; encoding: [0x05,0x00,0x09,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x09,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_mul_i32_i24_e64 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x09,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x09,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mul_i32_i24_e64 v5, ttmp15, src_scc   ; encoding: [0x05,0x00,0x09,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x09,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_mul_i32_i24_e64 v5, m0, 0.5           ; encoding: [0x05,0x00,0x09,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x09,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_mul_i32_i24_e64 v5, exec_lo, -1       ; encoding: [0x05,0x00,0x09,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x09,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_mul_i32_i24_e64 v5, exec_hi, null     ; encoding: [0x05,0x00,0x09,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x09,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_mul_i32_i24_e64 v5, null, exec_lo     ; encoding: [0x05,0x00,0x09,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x09,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_mul_i32_i24_e64 v5, -1, exec_hi       ; encoding: [0x05,0x00,0x09,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x09,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_mul_i32_i24_e64 v5, 0.5, m0           ; encoding: [0x05,0x00,0x09,0xd5,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x09,0xd5,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_mul_i32_i24_e64 v5, src_scc, vcc_lo   ; encoding: [0x05,0x00,0x09,0xd5,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x09,0xd5,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_mul_i32_i24_e64 v255, 0xaf123456, vcc_hi clamp ; encoding: [0xff,0x80,0x09,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x80,0x09,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mul_u32_u24_e64 v5, v1, v2            ; encoding: [0x05,0x00,0x0b,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x0b,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_mul_u32_u24_e64 v5, v255, v255        ; encoding: [0x05,0x00,0x0b,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x0b,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_mul_u32_u24_e64 v5, s1, s2            ; encoding: [0x05,0x00,0x0b,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x0b,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_mul_u32_u24_e64 v5, s105, s105        ; encoding: [0x05,0x00,0x0b,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x0b,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_mul_u32_u24_e64 v5, vcc_lo, ttmp15    ; encoding: [0x05,0x00,0x0b,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x0b,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_mul_u32_u24_e64 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x0b,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x0b,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_mul_u32_u24_e64 v5, ttmp15, src_scc   ; encoding: [0x05,0x00,0x0b,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x0b,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_mul_u32_u24_e64 v5, m0, 0.5           ; encoding: [0x05,0x00,0x0b,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x0b,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_mul_u32_u24_e64 v5, exec_lo, -1       ; encoding: [0x05,0x00,0x0b,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x0b,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_mul_u32_u24_e64 v5, exec_hi, null     ; encoding: [0x05,0x00,0x0b,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x0b,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_mul_u32_u24_e64 v5, null, exec_lo     ; encoding: [0x05,0x00,0x0b,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x0b,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_mul_u32_u24_e64 v5, -1, exec_hi       ; encoding: [0x05,0x00,0x0b,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x0b,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_mul_u32_u24_e64 v5, 0.5, m0           ; encoding: [0x05,0x00,0x0b,0xd5,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x0b,0xd5,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_mul_u32_u24_e64 v5, src_scc, vcc_lo   ; encoding: [0x05,0x00,0x0b,0xd5,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x0b,0xd5,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_mul_u32_u24_e64 v255, 0xaf123456, vcc_hi clamp ; encoding: [0xff,0x80,0x0b,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x80,0x0b,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_or_b32_e64 v5, v1, v2                 ; encoding: [0x05,0x00,0x1c,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x1c,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_or_b32_e64 v5, v255, v255             ; encoding: [0x05,0x00,0x1c,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x1c,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_or_b32_e64 v5, s1, s2                 ; encoding: [0x05,0x00,0x1c,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x1c,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_or_b32_e64 v5, s105, s105             ; encoding: [0x05,0x00,0x1c,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x1c,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_or_b32_e64 v5, vcc_lo, ttmp15         ; encoding: [0x05,0x00,0x1c,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x1c,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_or_b32_e64 v5, vcc_hi, 0xaf123456     ; encoding: [0x05,0x00,0x1c,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x1c,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_or_b32_e64 v5, ttmp15, src_scc        ; encoding: [0x05,0x00,0x1c,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x1c,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_or_b32_e64 v5, m0, 0.5                ; encoding: [0x05,0x00,0x1c,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x1c,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_or_b32_e64 v5, exec_lo, -1            ; encoding: [0x05,0x00,0x1c,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x1c,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_or_b32_e64 v5, exec_hi, null          ; encoding: [0x05,0x00,0x1c,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x1c,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_or_b32_e64 v5, null, exec_lo          ; encoding: [0x05,0x00,0x1c,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x1c,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_or_b32_e64 v5, -1, exec_hi            ; encoding: [0x05,0x00,0x1c,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x1c,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_or_b32_e64 v5, 0.5, m0                ; encoding: [0x05,0x00,0x1c,0xd5,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x1c,0xd5,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_or_b32_e64 v5, src_scc, vcc_lo        ; encoding: [0x05,0x00,0x1c,0xd5,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x1c,0xd5,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_or_b32_e64 v255, 0xaf123456, vcc_hi   ; encoding: [0xff,0x00,0x1c,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x1c,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_sub_co_ci_u32_e64 v5, s12, v1, 0xaf123456, s6 ; encoding: [0x05,0x0c,0x21,0xd5,0x01,0xff,0x19,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_sub_co_ci_u32_e64 v5, s[12:13], v1, 0xaf123456, s[6:7] ; encoding: [0x05,0x0c,0x21,0xd5,0x01,0xff,0x19,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x0c,0x21,0xd5,0x01,0xff,0x19,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_sub_co_ci_u32_e64 v5, s12, v255, src_scc, s6 ; encoding: [0x05,0x0c,0x21,0xd5,0xff,0xfb,0x19,0x00]
+# W64: v_sub_co_ci_u32_e64 v5, s[12:13], v255, src_scc, s[6:7] ; encoding: [0x05,0x0c,0x21,0xd5,0xff,0xfb,0x19,0x00]
+0x05,0x0c,0x21,0xd5,0xff,0xfb,0x19,0x00
+
+# W32: v_sub_co_ci_u32_e64 v5, s12, s105, s105, s6 ; encoding: [0x05,0x0c,0x21,0xd5,0x69,0xd2,0x18,0x00]
+# W64: v_sub_co_ci_u32_e64 v5, s[12:13], s105, s105, s[6:7] ; encoding: [0x05,0x0c,0x21,0xd5,0x69,0xd2,0x18,0x00]
+0x05,0x0c,0x21,0xd5,0x69,0xd2,0x18,0x00
+
+# W32: v_sub_co_ci_u32_e64 v5, s12, vcc_lo, v2, s6 ; encoding: [0x05,0x0c,0x21,0xd5,0x6a,0x04,0x1a,0x00]
+# W64: v_sub_co_ci_u32_e64 v5, s[12:13], vcc_lo, v2, s[6:7] ; encoding: [0x05,0x0c,0x21,0xd5,0x6a,0x04,0x1a,0x00]
+0x05,0x0c,0x21,0xd5,0x6a,0x04,0x1a,0x00
+
+# W32: v_sub_co_ci_u32_e64 v5, s12, vcc_hi, v255, s6 ; encoding: [0x05,0x0c,0x21,0xd5,0x6b,0xfe,0x1b,0x00]
+# W64: v_sub_co_ci_u32_e64 v5, s[12:13], vcc_hi, v255, s[6:7] ; encoding: [0x05,0x0c,0x21,0xd5,0x6b,0xfe,0x1b,0x00]
+0x05,0x0c,0x21,0xd5,0x6b,0xfe,0x1b,0x00
+
+# W32: v_sub_co_ci_u32_e64 v5, s12, ttmp15, ttmp15, s6 ; encoding: [0x05,0x0c,0x21,0xd5,0x7b,0xf6,0x18,0x00]
+# W64: v_sub_co_ci_u32_e64 v5, s[12:13], ttmp15, ttmp15, s[6:7] ; encoding: [0x05,0x0c,0x21,0xd5,0x7b,0xf6,0x18,0x00]
+0x05,0x0c,0x21,0xd5,0x7b,0xf6,0x18,0x00
+
+# W32: v_sub_co_ci_u32_e64 v5, s12, m0, 0.5, s6  ; encoding: [0x05,0x0c,0x21,0xd5,0x7d,0xe0,0x19,0x00]
+# W64: v_sub_co_ci_u32_e64 v5, s[12:13], m0, 0.5, s[6:7] ; encoding: [0x05,0x0c,0x21,0xd5,0x7d,0xe0,0x19,0x00]
+0x05,0x0c,0x21,0xd5,0x7d,0xe0,0x19,0x00
+
+# W32: v_sub_co_ci_u32_e64 v5, s12, exec_lo, exec_lo, s6 ; encoding: [0x05,0x0c,0x21,0xd5,0x7e,0xfc,0x18,0x00]
+# W64: v_sub_co_ci_u32_e64 v5, s[12:13], exec_lo, exec_lo, s[6:7] ; encoding: [0x05,0x0c,0x21,0xd5,0x7e,0xfc,0x18,0x00]
+0x05,0x0c,0x21,0xd5,0x7e,0xfc,0x18,0x00
+
+# W32: v_sub_co_ci_u32_e64 v5, s12, exec_hi, -1, s6 ; encoding: [0x05,0x0c,0x21,0xd5,0x7f,0x82,0x19,0x00]
+# W64: v_sub_co_ci_u32_e64 v5, s[12:13], exec_hi, -1, s[6:7] ; encoding: [0x05,0x0c,0x21,0xd5,0x7f,0x82,0x19,0x00]
+0x05,0x0c,0x21,0xd5,0x7f,0x82,0x19,0x00
+
+# W32: v_sub_co_ci_u32_e64 v5, s12, null, exec_hi, s6 ; encoding: [0x05,0x0c,0x21,0xd5,0x7c,0xfe,0x18,0x00]
+# W64: v_sub_co_ci_u32_e64 v5, s[12:13], null, exec_hi, s[6:7] ; encoding: [0x05,0x0c,0x21,0xd5,0x7c,0xfe,0x18,0x00]
+0x05,0x0c,0x21,0xd5,0x7c,0xfe,0x18,0x00
+
+# W32: v_sub_co_ci_u32_e64 v5, s104, -1, m0, s104 ; encoding: [0x05,0x68,0x21,0xd5,0xc1,0xfa,0xa0,0x01]
+# W64: v_sub_co_ci_u32_e64 v5, s[104:105], -1, m0, s[104:105] ; encoding: [0x05,0x68,0x21,0xd5,0xc1,0xfa,0xa0,0x01]
+0x05,0x68,0x21,0xd5,0xc1,0xfa,0xa0,0x01
+
+# W32: v_sub_co_ci_u32_e64 v5, vcc_lo, 0.5, vcc_lo, vcc_lo ; encoding: [0x05,0x6a,0x21,0xd5,0xf0,0xd4,0xa8,0x01]
+# W64: v_sub_co_ci_u32_e64 v5, vcc, 0.5, vcc_lo, vcc ; encoding: [0x05,0x6a,0x21,0xd5,0xf0,0xd4,0xa8,0x01]
+0x05,0x6a,0x21,0xd5,0xf0,0xd4,0xa8,0x01
+
+# W32: v_sub_co_ci_u32_e64 v5, ttmp14, src_scc, null, ttmp14 ; encoding: [0x05,0x7a,0x21,0xd5,0xfd,0xf8,0xe8,0x01]
+# W64: v_sub_co_ci_u32_e64 v5, ttmp[14:15], src_scc, null, ttmp[14:15] ; encoding: [0x05,0x7a,0x21,0xd5,0xfd,0xf8,0xe8,0x01]
+0x05,0x7a,0x21,0xd5,0xfd,0xf8,0xe8,0x01
+
+# GFX12: v_sub_co_ci_u32_e64 v255, null, 0xaf123456, vcc_hi, null clamp ; encoding: [0xff,0xfc,0x21,0xd5,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x21,0xd5,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_sub_f16_e64 v5, v1, v2                ; encoding: [0x05,0x00,0x33,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x33,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_sub_f16_e64 v5, v255, v255            ; encoding: [0x05,0x00,0x33,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x33,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_sub_f16_e64 v5, s1, s2                ; encoding: [0x05,0x00,0x33,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x33,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_sub_f16_e64 v5, s105, s105            ; encoding: [0x05,0x00,0x33,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x33,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_sub_f16_e64 v5, vcc_lo, ttmp15        ; encoding: [0x05,0x00,0x33,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x33,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_sub_f16_e64 v5, vcc_hi, 0xfe0b        ; encoding: [0x05,0x00,0x33,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x33,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_sub_f16_e64 v5, ttmp15, src_scc       ; encoding: [0x05,0x00,0x33,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x33,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_sub_f16_e64 v5, m0, 0.5               ; encoding: [0x05,0x00,0x33,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x33,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_sub_f16_e64 v5, exec_lo, -1           ; encoding: [0x05,0x00,0x33,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x33,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_sub_f16_e64 v5, |exec_hi|, null       ; encoding: [0x05,0x01,0x33,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x01,0x33,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_sub_f16_e64 v5, null, exec_lo         ; encoding: [0x05,0x00,0x33,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x33,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_sub_f16_e64 v5, -1, exec_hi           ; encoding: [0x05,0x00,0x33,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x33,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_sub_f16_e64 v5, 0.5, -m0 mul:2        ; encoding: [0x05,0x00,0x33,0xd5,0xf0,0xfa,0x00,0x48]
+0x05,0x00,0x33,0xd5,0xf0,0xfa,0x00,0x48
+
+# GFX12: v_sub_f16_e64 v5, -src_scc, |vcc_lo| mul:4 ; encoding: [0x05,0x02,0x33,0xd5,0xfd,0xd4,0x00,0x30]
+0x05,0x02,0x33,0xd5,0xfd,0xd4,0x00,0x30
+
+# GFX12: v_sub_f16_e64 v255, -|0xfe0b|, -|vcc_hi| clamp div:2 ; encoding: [0xff,0x83,0x33,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00]
+0xff,0x83,0x33,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_sub_f32_e64 v5, v1, v2                ; encoding: [0x05,0x00,0x04,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x04,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_sub_f32_e64 v5, v255, v255            ; encoding: [0x05,0x00,0x04,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x04,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_sub_f32_e64 v5, s1, s2                ; encoding: [0x05,0x00,0x04,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x04,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_sub_f32_e64 v5, s105, s105            ; encoding: [0x05,0x00,0x04,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x04,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_sub_f32_e64 v5, vcc_lo, ttmp15        ; encoding: [0x05,0x00,0x04,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x04,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_sub_f32_e64 v5, vcc_hi, 0xaf123456    ; encoding: [0x05,0x00,0x04,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x04,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_sub_f32_e64 v5, ttmp15, src_scc       ; encoding: [0x05,0x00,0x04,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x04,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_sub_f32_e64 v5, m0, 0.5               ; encoding: [0x05,0x00,0x04,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x04,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_sub_f32_e64 v5, exec_lo, -1           ; encoding: [0x05,0x00,0x04,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x04,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_sub_f32_e64 v5, |exec_hi|, null       ; encoding: [0x05,0x01,0x04,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x01,0x04,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_sub_f32_e64 v5, null, exec_lo         ; encoding: [0x05,0x00,0x04,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x04,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_sub_f32_e64 v5, -1, exec_hi           ; encoding: [0x05,0x00,0x04,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x04,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_sub_f32_e64 v5, 0.5, -m0 mul:2        ; encoding: [0x05,0x00,0x04,0xd5,0xf0,0xfa,0x00,0x48]
+0x05,0x00,0x04,0xd5,0xf0,0xfa,0x00,0x48
+
+# GFX12: v_sub_f32_e64 v5, -src_scc, |vcc_lo| mul:4 ; encoding: [0x05,0x02,0x04,0xd5,0xfd,0xd4,0x00,0x30]
+0x05,0x02,0x04,0xd5,0xfd,0xd4,0x00,0x30
+
+# GFX12: v_sub_f32_e64 v255, -|0xaf123456|, -|vcc_hi| clamp div:2 ; encoding: [0xff,0x83,0x04,0xd5,0xff,0xd6,0x00,0x78,0x56,0x34,0x12,0xaf]
+0xff,0x83,0x04,0xd5,0xff,0xd6,0x00,0x78,0x56,0x34,0x12,0xaf
+
+# GFX12: v_sub_nc_u32_e64 v5, v1, v2             ; encoding: [0x05,0x00,0x26,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x26,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_sub_nc_u32_e64 v5, v255, v255         ; encoding: [0x05,0x00,0x26,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x26,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_sub_nc_u32_e64 v5, s1, s2             ; encoding: [0x05,0x00,0x26,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x26,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_sub_nc_u32_e64 v5, s105, s105         ; encoding: [0x05,0x00,0x26,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x26,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_sub_nc_u32_e64 v5, vcc_lo, ttmp15     ; encoding: [0x05,0x00,0x26,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x26,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_sub_nc_u32_e64 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x26,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x26,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_sub_nc_u32_e64 v5, ttmp15, src_scc    ; encoding: [0x05,0x00,0x26,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x26,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_sub_nc_u32_e64 v5, m0, 0.5            ; encoding: [0x05,0x00,0x26,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x26,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_sub_nc_u32_e64 v5, exec_lo, -1        ; encoding: [0x05,0x00,0x26,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x26,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_sub_nc_u32_e64 v5, exec_hi, null      ; encoding: [0x05,0x00,0x26,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x26,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_sub_nc_u32_e64 v5, null, exec_lo      ; encoding: [0x05,0x00,0x26,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x26,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_sub_nc_u32_e64 v5, -1, exec_hi        ; encoding: [0x05,0x00,0x26,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x26,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_sub_nc_u32_e64 v5, 0.5, m0            ; encoding: [0x05,0x00,0x26,0xd5,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x26,0xd5,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_sub_nc_u32_e64 v5, src_scc, vcc_lo    ; encoding: [0x05,0x00,0x26,0xd5,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x26,0xd5,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_sub_nc_u32_e64 v255, 0xaf123456, vcc_hi clamp ; encoding: [0xff,0x80,0x26,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x80,0x26,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_subrev_co_ci_u32_e64 v5, s12, v1, 0xaf123456, s6 ; encoding: [0x05,0x0c,0x22,0xd5,0x01,0xff,0x19,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_subrev_co_ci_u32_e64 v5, s[12:13], v1, 0xaf123456, s[6:7] ; encoding: [0x05,0x0c,0x22,0xd5,0x01,0xff,0x19,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x0c,0x22,0xd5,0x01,0xff,0x19,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_subrev_co_ci_u32_e64 v5, s12, v255, src_scc, s6 ; encoding: [0x05,0x0c,0x22,0xd5,0xff,0xfb,0x19,0x00]
+# W64: v_subrev_co_ci_u32_e64 v5, s[12:13], v255, src_scc, s[6:7] ; encoding: [0x05,0x0c,0x22,0xd5,0xff,0xfb,0x19,0x00]
+0x05,0x0c,0x22,0xd5,0xff,0xfb,0x19,0x00
+
+# W32: v_subrev_co_ci_u32_e64 v5, s12, s105, s105, s6 ; encoding: [0x05,0x0c,0x22,0xd5,0x69,0xd2,0x18,0x00]
+# W64: v_subrev_co_ci_u32_e64 v5, s[12:13], s105, s105, s[6:7] ; encoding: [0x05,0x0c,0x22,0xd5,0x69,0xd2,0x18,0x00]
+0x05,0x0c,0x22,0xd5,0x69,0xd2,0x18,0x00
+
+# W32: v_subrev_co_ci_u32_e64 v5, s12, vcc_lo, v2, s6 ; encoding: [0x05,0x0c,0x22,0xd5,0x6a,0x04,0x1a,0x00]
+# W64: v_subrev_co_ci_u32_e64 v5, s[12:13], vcc_lo, v2, s[6:7] ; encoding: [0x05,0x0c,0x22,0xd5,0x6a,0x04,0x1a,0x00]
+0x05,0x0c,0x22,0xd5,0x6a,0x04,0x1a,0x00
+
+# W32: v_subrev_co_ci_u32_e64 v5, s12, vcc_hi, v255, s6 ; encoding: [0x05,0x0c,0x22,0xd5,0x6b,0xfe,0x1b,0x00]
+# W64: v_subrev_co_ci_u32_e64 v5, s[12:13], vcc_hi, v255, s[6:7] ; encoding: [0x05,0x0c,0x22,0xd5,0x6b,0xfe,0x1b,0x00]
+0x05,0x0c,0x22,0xd5,0x6b,0xfe,0x1b,0x00
+
+# W32: v_subrev_co_ci_u32_e64 v5, s12, ttmp15, ttmp15, s6 ; encoding: [0x05,0x0c,0x22,0xd5,0x7b,0xf6,0x18,0x00]
+# W64: v_subrev_co_ci_u32_e64 v5, s[12:13], ttmp15, ttmp15, s[6:7] ; encoding: [0x05,0x0c,0x22,0xd5,0x7b,0xf6,0x18,0x00]
+0x05,0x0c,0x22,0xd5,0x7b,0xf6,0x18,0x00
+
+# W32: v_subrev_co_ci_u32_e64 v5, s12, m0, 0.5, s6 ; encoding: [0x05,0x0c,0x22,0xd5,0x7d,0xe0,0x19,0x00]
+# W64: v_subrev_co_ci_u32_e64 v5, s[12:13], m0, 0.5, s[6:7] ; encoding: [0x05,0x0c,0x22,0xd5,0x7d,0xe0,0x19,0x00]
+0x05,0x0c,0x22,0xd5,0x7d,0xe0,0x19,0x00
+
+# W32: v_subrev_co_ci_u32_e64 v5, s12, exec_lo, exec_lo, s6 ; encoding: [0x05,0x0c,0x22,0xd5,0x7e,0xfc,0x18,0x00]
+# W64: v_subrev_co_ci_u32_e64 v5, s[12:13], exec_lo, exec_lo, s[6:7] ; encoding: [0x05,0x0c,0x22,0xd5,0x7e,0xfc,0x18,0x00]
+0x05,0x0c,0x22,0xd5,0x7e,0xfc,0x18,0x00
+
+# W32: v_subrev_co_ci_u32_e64 v5, s12, exec_hi, -1, s6 ; encoding: [0x05,0x0c,0x22,0xd5,0x7f,0x82,0x19,0x00]
+# W64: v_subrev_co_ci_u32_e64 v5, s[12:13], exec_hi, -1, s[6:7] ; encoding: [0x05,0x0c,0x22,0xd5,0x7f,0x82,0x19,0x00]
+0x05,0x0c,0x22,0xd5,0x7f,0x82,0x19,0x00
+
+# W32: v_subrev_co_ci_u32_e64 v5, s12, null, exec_hi, s6 ; encoding: [0x05,0x0c,0x22,0xd5,0x7c,0xfe,0x18,0x00]
+# W64: v_subrev_co_ci_u32_e64 v5, s[12:13], null, exec_hi, s[6:7] ; encoding: [0x05,0x0c,0x22,0xd5,0x7c,0xfe,0x18,0x00]
+0x05,0x0c,0x22,0xd5,0x7c,0xfe,0x18,0x00
+
+# W32: v_subrev_co_ci_u32_e64 v5, s104, -1, m0, s104 ; encoding: [0x05,0x68,0x22,0xd5,0xc1,0xfa,0xa0,0x01]
+# W64: v_subrev_co_ci_u32_e64 v5, s[104:105], -1, m0, s[104:105] ; encoding: [0x05,0x68,0x22,0xd5,0xc1,0xfa,0xa0,0x01]
+0x05,0x68,0x22,0xd5,0xc1,0xfa,0xa0,0x01
+
+# W32: v_subrev_co_ci_u32_e64 v5, vcc_lo, 0.5, vcc_lo, vcc_lo ; encoding: [0x05,0x6a,0x22,0xd5,0xf0,0xd4,0xa8,0x01]
+# W64: v_subrev_co_ci_u32_e64 v5, vcc, 0.5, vcc_lo, vcc ; encoding: [0x05,0x6a,0x22,0xd5,0xf0,0xd4,0xa8,0x01]
+0x05,0x6a,0x22,0xd5,0xf0,0xd4,0xa8,0x01
+
+# W32: v_subrev_co_ci_u32_e64 v5, ttmp14, src_scc, null, ttmp14 ; encoding: [0x05,0x7a,0x22,0xd5,0xfd,0xf8,0xe8,0x01]
+# W64: v_subrev_co_ci_u32_e64 v5, ttmp[14:15], src_scc, null, ttmp[14:15] ; encoding: [0x05,0x7a,0x22,0xd5,0xfd,0xf8,0xe8,0x01]
+0x05,0x7a,0x22,0xd5,0xfd,0xf8,0xe8,0x01
+
+# GFX12: v_subrev_co_ci_u32_e64 v255, null, 0xaf123456, vcc_hi, null clamp ; encoding: [0xff,0xfc,0x22,0xd5,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x22,0xd5,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
+
+# GFX12: v_subrev_f16_e64 v5, v1, v2             ; encoding: [0x05,0x00,0x34,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x34,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_subrev_f16_e64 v5, v255, v255         ; encoding: [0x05,0x00,0x34,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x34,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_subrev_f16_e64 v5, s1, s2             ; encoding: [0x05,0x00,0x34,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x34,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_subrev_f16_e64 v5, s105, s105         ; encoding: [0x05,0x00,0x34,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x34,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_subrev_f16_e64 v5, vcc_lo, ttmp15     ; encoding: [0x05,0x00,0x34,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x34,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_subrev_f16_e64 v5, vcc_hi, 0xfe0b     ; encoding: [0x05,0x00,0x34,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x34,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_subrev_f16_e64 v5, ttmp15, src_scc    ; encoding: [0x05,0x00,0x34,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x34,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_subrev_f16_e64 v5, m0, 0.5            ; encoding: [0x05,0x00,0x34,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x34,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_subrev_f16_e64 v5, exec_lo, -1        ; encoding: [0x05,0x00,0x34,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x34,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_subrev_f16_e64 v5, |exec_hi|, null    ; encoding: [0x05,0x01,0x34,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x01,0x34,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_subrev_f16_e64 v5, null, exec_lo      ; encoding: [0x05,0x00,0x34,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x34,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_subrev_f16_e64 v5, -1, exec_hi        ; encoding: [0x05,0x00,0x34,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x34,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_subrev_f16_e64 v5, 0.5, -m0 mul:2     ; encoding: [0x05,0x00,0x34,0xd5,0xf0,0xfa,0x00,0x48]
+0x05,0x00,0x34,0xd5,0xf0,0xfa,0x00,0x48
+
+# GFX12: v_subrev_f16_e64 v5, -src_scc, |vcc_lo| mul:4 ; encoding: [0x05,0x02,0x34,0xd5,0xfd,0xd4,0x00,0x30]
+0x05,0x02,0x34,0xd5,0xfd,0xd4,0x00,0x30
+
+# GFX12: v_subrev_f16_e64 v255, -|0xfe0b|, -|vcc_hi| clamp div:2 ; encoding: [0xff,0x83,0x34,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00]
+0xff,0x83,0x34,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_subrev_f32_e64 v5, v1, v2             ; encoding: [0x05,0x00,0x05,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x05,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_subrev_f32_e64 v5, v255, v255         ; encoding: [0x05,0x00,0x05,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x05,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_subrev_f32_e64 v5, s1, s2             ; encoding: [0x05,0x00,0x05,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x05,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_subrev_f32_e64 v5, s105, s105         ; encoding: [0x05,0x00,0x05,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x05,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_subrev_f32_e64 v5, vcc_lo, ttmp15     ; encoding: [0x05,0x00,0x05,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x05,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_subrev_f32_e64 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x05,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x05,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_subrev_f32_e64 v5, ttmp15, src_scc    ; encoding: [0x05,0x00,0x05,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x05,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_subrev_f32_e64 v5, m0, 0.5            ; encoding: [0x05,0x00,0x05,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x05,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_subrev_f32_e64 v5, exec_lo, -1        ; encoding: [0x05,0x00,0x05,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x05,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_subrev_f32_e64 v5, |exec_hi|, null    ; encoding: [0x05,0x01,0x05,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x01,0x05,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_subrev_f32_e64 v5, null, exec_lo      ; encoding: [0x05,0x00,0x05,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x05,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_subrev_f32_e64 v5, -1, exec_hi        ; encoding: [0x05,0x00,0x05,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x05,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_subrev_f32_e64 v5, 0.5, -m0 mul:2     ; encoding: [0x05,0x00,0x05,0xd5,0xf0,0xfa,0x00,0x48]
+0x05,0x00,0x05,0xd5,0xf0,0xfa,0x00,0x48
+
+# GFX12: v_subrev_f32_e64 v5, -src_scc, |vcc_lo| mul:4 ; encoding: [0x05,0x02,0x05,0xd5,0xfd,0xd4,0x00,0x30]
+0x05,0x02,0x05,0xd5,0xfd,0xd4,0x00,0x30
+
+# GFX12: v_subrev_f32_e64 v255, -|0xaf123456|, -|vcc_hi| clamp div:2 ; encoding: [0xff,0x83,0x05,0xd5,0xff,0xd6,0x00,0x78,0x56,0x34,0x12,0xaf]
+0xff,0x83,0x05,0xd5,0xff,0xd6,0x00,0x78,0x56,0x34,0x12,0xaf
+
+# GFX12: v_subrev_nc_u32_e64 v5, v1, v2          ; encoding: [0x05,0x00,0x27,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x27,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_subrev_nc_u32_e64 v5, v255, v255      ; encoding: [0x05,0x00,0x27,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x27,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_subrev_nc_u32_e64 v5, s1, s2          ; encoding: [0x05,0x00,0x27,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x27,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_subrev_nc_u32_e64 v5, s105, s105      ; encoding: [0x05,0x00,0x27,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x27,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_subrev_nc_u32_e64 v5, vcc_lo, ttmp15  ; encoding: [0x05,0x00,0x27,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x27,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_subrev_nc_u32_e64 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x27,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x27,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_subrev_nc_u32_e64 v5, ttmp15, src_scc ; encoding: [0x05,0x00,0x27,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x27,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_subrev_nc_u32_e64 v5, m0, 0.5         ; encoding: [0x05,0x00,0x27,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x27,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_subrev_nc_u32_e64 v5, exec_lo, -1     ; encoding: [0x05,0x00,0x27,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x27,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_subrev_nc_u32_e64 v5, exec_hi, null   ; encoding: [0x05,0x00,0x27,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x27,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_subrev_nc_u32_e64 v5, null, exec_lo   ; encoding: [0x05,0x00,0x27,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x27,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_subrev_nc_u32_e64 v5, -1, exec_hi     ; encoding: [0x05,0x00,0x27,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x27,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_subrev_nc_u32_e64 v5, 0.5, m0         ; encoding: [0x05,0x00,0x27,0xd5,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x27,0xd5,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_subrev_nc_u32_e64 v5, src_scc, vcc_lo ; encoding: [0x05,0x00,0x27,0xd5,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x27,0xd5,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_subrev_nc_u32_e64 v255, 0xaf123456, vcc_hi clamp ; encoding: [0xff,0x80,0x27,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x80,0x27,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_xnor_b32_e64 v5, v1, v2               ; encoding: [0x05,0x00,0x1e,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x1e,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_xnor_b32_e64 v5, v255, v255           ; encoding: [0x05,0x00,0x1e,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x1e,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_xnor_b32_e64 v5, s1, s2               ; encoding: [0x05,0x00,0x1e,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x1e,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_xnor_b32_e64 v5, s105, s105           ; encoding: [0x05,0x00,0x1e,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x1e,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_xnor_b32_e64 v5, vcc_lo, ttmp15       ; encoding: [0x05,0x00,0x1e,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x1e,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_xnor_b32_e64 v5, vcc_hi, 0xaf123456   ; encoding: [0x05,0x00,0x1e,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x1e,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_xnor_b32_e64 v5, ttmp15, src_scc      ; encoding: [0x05,0x00,0x1e,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x1e,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_xnor_b32_e64 v5, m0, 0.5              ; encoding: [0x05,0x00,0x1e,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x1e,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_xnor_b32_e64 v5, exec_lo, -1          ; encoding: [0x05,0x00,0x1e,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x1e,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_xnor_b32_e64 v5, exec_hi, null        ; encoding: [0x05,0x00,0x1e,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x1e,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_xnor_b32_e64 v5, null, exec_lo        ; encoding: [0x05,0x00,0x1e,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x1e,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_xnor_b32_e64 v5, -1, exec_hi          ; encoding: [0x05,0x00,0x1e,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x1e,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_xnor_b32_e64 v5, 0.5, m0              ; encoding: [0x05,0x00,0x1e,0xd5,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x1e,0xd5,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_xnor_b32_e64 v5, src_scc, vcc_lo      ; encoding: [0x05,0x00,0x1e,0xd5,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x1e,0xd5,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_xnor_b32_e64 v255, 0xaf123456, vcc_hi ; encoding: [0xff,0x00,0x1e,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x1e,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_xor_b32_e64 v5, v1, v2                ; encoding: [0x05,0x00,0x1d,0xd5,0x01,0x05,0x02,0x00]
+0x05,0x00,0x1d,0xd5,0x01,0x05,0x02,0x00
+
+# GFX12: v_xor_b32_e64 v5, v255, v255            ; encoding: [0x05,0x00,0x1d,0xd5,0xff,0xff,0x03,0x00]
+0x05,0x00,0x1d,0xd5,0xff,0xff,0x03,0x00
+
+# GFX12: v_xor_b32_e64 v5, s1, s2                ; encoding: [0x05,0x00,0x1d,0xd5,0x01,0x04,0x00,0x00]
+0x05,0x00,0x1d,0xd5,0x01,0x04,0x00,0x00
+
+# GFX12: v_xor_b32_e64 v5, s105, s105            ; encoding: [0x05,0x00,0x1d,0xd5,0x69,0xd2,0x00,0x00]
+0x05,0x00,0x1d,0xd5,0x69,0xd2,0x00,0x00
+
+# GFX12: v_xor_b32_e64 v5, vcc_lo, ttmp15        ; encoding: [0x05,0x00,0x1d,0xd5,0x6a,0xf6,0x00,0x00]
+0x05,0x00,0x1d,0xd5,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_xor_b32_e64 v5, vcc_hi, 0xaf123456    ; encoding: [0x05,0x00,0x1d,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x05,0x00,0x1d,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_xor_b32_e64 v5, ttmp15, src_scc       ; encoding: [0x05,0x00,0x1d,0xd5,0x7b,0xfa,0x01,0x00]
+0x05,0x00,0x1d,0xd5,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_xor_b32_e64 v5, m0, 0.5               ; encoding: [0x05,0x00,0x1d,0xd5,0x7d,0xe0,0x01,0x00]
+0x05,0x00,0x1d,0xd5,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_xor_b32_e64 v5, exec_lo, -1           ; encoding: [0x05,0x00,0x1d,0xd5,0x7e,0x82,0x01,0x00]
+0x05,0x00,0x1d,0xd5,0x7e,0x82,0x01,0x00
+
+# GFX12: v_xor_b32_e64 v5, exec_hi, null         ; encoding: [0x05,0x00,0x1d,0xd5,0x7f,0xf8,0x00,0x00]
+0x05,0x00,0x1d,0xd5,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_xor_b32_e64 v5, null, exec_lo         ; encoding: [0x05,0x00,0x1d,0xd5,0x7c,0xfc,0x00,0x00]
+0x05,0x00,0x1d,0xd5,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_xor_b32_e64 v5, -1, exec_hi           ; encoding: [0x05,0x00,0x1d,0xd5,0xc1,0xfe,0x00,0x00]
+0x05,0x00,0x1d,0xd5,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_xor_b32_e64 v5, 0.5, m0               ; encoding: [0x05,0x00,0x1d,0xd5,0xf0,0xfa,0x00,0x00]
+0x05,0x00,0x1d,0xd5,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_xor_b32_e64 v5, src_scc, vcc_lo       ; encoding: [0x05,0x00,0x1d,0xd5,0xfd,0xd4,0x00,0x00]
+0x05,0x00,0x1d,0xd5,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_xor_b32_e64 v255, 0xaf123456, vcc_hi  ; encoding: [0xff,0x00,0x1d,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x1d,0xd5,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2_dpp16.txt
new file mode 100644
index 000000000000..49cd84b9e662
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2_dpp16.txt
@@ -0,0 +1,1608 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32 %s
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64 %s
+
+# W32: v_add_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_add_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_add_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_add_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_add_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x40,0x01,0xff]
+# W64: v_add_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x40,0x01,0xff]
+0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_add_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x41,0x01,0xff]
+# W64: v_add_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x41,0x01,0xff]
+0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_add_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x01,0x01,0xff]
+# W64: v_add_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x01,0x01,0xff]
+0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_add_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_add_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_add_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x11,0x01,0xff]
+# W64: v_add_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x11,0x01,0xff]
+0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_add_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_add_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_add_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x21,0x01,0xff]
+# W64: v_add_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x21,0x01,0xff]
+0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_add_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_add_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_add_co_ci_u32_e64_dpp v5, s104, v1, v2, s104 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x68,0x20,0xd5,0xfa,0x04,0xa2,0x01,0x01,0x50,0x01,0xff]
+# W64: v_add_co_ci_u32_e64_dpp v5, s[104:105], v1, v2, s[104:105] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x68,0x20,0xd5,0xfa,0x04,0xa2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x68,0x20,0xd5,0xfa,0x04,0xa2,0x01,0x01,0x50,0x01,0xff
+
+# W32: v_add_co_ci_u32_e64_dpp v5, vcc_lo, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x6a,0x20,0xd5,0xfa,0x04,0xaa,0x01,0x01,0x5f,0x01,0x01]
+# W64: v_add_co_ci_u32_e64_dpp v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x6a,0x20,0xd5,0xfa,0x04,0xaa,0x01,0x01,0x5f,0x01,0x01]
+0x05,0x6a,0x20,0xd5,0xfa,0x04,0xaa,0x01,0x01,0x5f,0x01,0x01
+
+# W32: v_add_co_ci_u32_e64_dpp v5, ttmp14, v1, v2, ttmp14 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x7a,0x20,0xd5,0xfa,0x04,0xea,0x01,0x01,0x60,0x01,0x13]
+# W64: v_add_co_ci_u32_e64_dpp v5, ttmp[14:15], v1, v2, ttmp[14:15] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x7a,0x20,0xd5,0xfa,0x04,0xea,0x01,0x01,0x60,0x01,0x13]
+0x05,0x7a,0x20,0xd5,0xfa,0x04,0xea,0x01,0x01,0x60,0x01,0x13
+
+# GFX12: v_add_co_ci_u32_e64_dpp v255, null, v255, v255, null clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0xfc,0x20,0xd5,0xfa,0xfe,0xf3,0x01,0xff,0x6f,0x0d,0x30]
+0xff,0xfc,0x20,0xd5,0xfa,0xfe,0xf3,0x01,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_add_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_add_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_add_f16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_add_f16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_add_f16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_add_f16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_add_f16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_add_f16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_add_f16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_add_f16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_add_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_add_f16_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x32,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+0x05,0x01,0x32,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01
+
+# GFX12: v_add_f16_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x02,0x32,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x01,0x13]
+0x05,0x02,0x32,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x01,0x13
+
+# GFX12: v_add_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x83,0x32,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x0d,0x30]
+0xff,0x83,0x32,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_add_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_add_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_add_f32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_add_f32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_add_f32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_add_f32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_add_f32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_add_f32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_add_f32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_add_f32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_add_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x03,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_add_f32_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x03,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+0x05,0x01,0x03,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01
+
+# GFX12: v_add_f32_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x02,0x03,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x01,0x13]
+0x05,0x02,0x03,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x01,0x13
+
+# GFX12: v_add_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x83,0x03,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x0d,0x30]
+0xff,0x83,0x03,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_add_nc_u32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_add_nc_u32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_add_nc_u32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_add_nc_u32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_add_nc_u32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_add_nc_u32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_add_nc_u32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_add_nc_u32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_add_nc_u32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_add_nc_u32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_add_nc_u32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_add_nc_u32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_add_nc_u32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x25,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_add_nc_u32_e64_dpp v255, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x80,0x25,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x80,0x25,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_and_b32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_and_b32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_and_b32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_and_b32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_and_b32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_and_b32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_and_b32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_and_b32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_and_b32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_and_b32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_and_b32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_and_b32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_and_b32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x1b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_and_b32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x1b,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x1b,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_ashrrev_i32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_ashrrev_i32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_ashrrev_i32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_ashrrev_i32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_ashrrev_i32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_ashrrev_i32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_ashrrev_i32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_ashrrev_i32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_ashrrev_i32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_ashrrev_i32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_ashrrev_i32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_ashrrev_i32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_ashrrev_i32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x1a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_ashrrev_i32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x1a,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x1a,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_cndmask_b32_e64_dpp v5, v1, v2, s6 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cndmask_b32_e64_dpp v5, v1, v2, s[6:7] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cndmask_b32_e64_dpp v5, v1, v2, s6 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cndmask_b32_e64_dpp v5, v1, v2, s[6:7] quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cndmask_b32_e64_dpp v5, v1, v2, s6 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cndmask_b32_e64_dpp v5, v1, v2, s[6:7] row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cndmask_b32_e64_dpp v5, v1, v2, s6 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cndmask_b32_e64_dpp v5, v1, v2, s[6:7] row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cndmask_b32_e64_dpp v5, v1, v2, s6 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cndmask_b32_e64_dpp v5, v1, v2, s[6:7] row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cndmask_b32_e64_dpp v5, v1, v2, s6 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cndmask_b32_e64_dpp v5, v1, v2, s[6:7] row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cndmask_b32_e64_dpp v5, v1, v2, s6 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cndmask_b32_e64_dpp v5, v1, v2, s[6:7] row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cndmask_b32_e64_dpp v5, v1, v2, s6 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cndmask_b32_e64_dpp v5, v1, v2, s[6:7] row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cndmask_b32_e64_dpp v5, v1, v2, s6 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cndmask_b32_e64_dpp v5, v1, v2, s[6:7] row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cndmask_b32_e64_dpp v5, v1, v2, s6 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cndmask_b32_e64_dpp v5, v1, v2, s[6:7] row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cndmask_b32_e64_dpp v5, v1, v2, s104 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0xa2,0x01,0x01,0x50,0x01,0xff]
+# W64: v_cndmask_b32_e64_dpp v5, v1, v2, s[104:105] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0xa2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x00,0x01,0xd5,0xfa,0x04,0xa2,0x01,0x01,0x50,0x01,0xff
+
+# W32: v_cndmask_b32_e64_dpp v5, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0xaa,0x01,0x01,0x5f,0x01,0x01]
+# W64: v_cndmask_b32_e64_dpp v5, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0xaa,0x01,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x01,0xd5,0xfa,0x04,0xaa,0x01,0x01,0x5f,0x01,0x01
+
+# W32: v_cndmask_b32_e64_dpp v5, v1, v2, ttmp14 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0xea,0x01,0x01,0x60,0x01,0x13]
+# W64: v_cndmask_b32_e64_dpp v5, v1, v2, ttmp[14:15] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0xea,0x01,0x01,0x60,0x01,0x13]
+0x05,0x00,0x01,0xd5,0xfa,0x04,0xea,0x01,0x01,0x60,0x01,0x13
+
+# GFX12: v_cndmask_b32_e64_dpp v255, v255, v255, null row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x01,0xd5,0xfa,0xfe,0xf3,0x01,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x01,0xd5,0xfa,0xfe,0xf3,0x01,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x2f,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x2f,0xd5,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x05,0x01,0x2f,0xd5,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x02,0x2f,0xd5,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x05,0x02,0x2f,0xd5,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64_dpp v255, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x83,0x2f,0xd5,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0xff,0x83,0x2f,0xd5,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_ldexp_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_ldexp_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_ldexp_f16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_ldexp_f16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_ldexp_f16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_ldexp_f16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_ldexp_f16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_ldexp_f16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_ldexp_f16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_ldexp_f16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_ldexp_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_ldexp_f16_e64_dpp v5, v1, v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x08,0x01,0x5f,0x01,0x01
+
+# GFX12: v_ldexp_f16_e64_dpp v5, v1, v2 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x10,0x01,0x60,0x01,0x13]
+0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x10,0x01,0x60,0x01,0x13
+
+# GFX12: v_ldexp_f16_e64_dpp v255, -|v255|, v255 clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0x3b,0xd5,0xfa,0xfe,0x03,0x38,0xff,0x6f,0x0d,0x30]
+0xff,0x81,0x3b,0xd5,0xfa,0xfe,0x03,0x38,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_lshlrev_b32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_lshlrev_b32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_lshlrev_b32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_lshlrev_b32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_lshlrev_b32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_lshlrev_b32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_lshlrev_b32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_lshlrev_b32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_lshlrev_b32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_lshlrev_b32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_lshlrev_b32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_lshlrev_b32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_lshlrev_b32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x18,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_lshlrev_b32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x18,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x18,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_lshrrev_b32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_lshrrev_b32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_lshrrev_b32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_lshrrev_b32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_lshrrev_b32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_lshrrev_b32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_lshrrev_b32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_lshrrev_b32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_lshrrev_b32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_lshrrev_b32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_lshrrev_b32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_lshrrev_b32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_lshrrev_b32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x19,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_lshrrev_b32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x19,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x19,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_max_num_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_max_num_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_max_num_f16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_max_num_f16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_max_num_f16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_max_num_f16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_max_num_f16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_max_num_f16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_max_num_f16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_max_num_f16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_max_num_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_max_num_f16_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x31,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+0x05,0x01,0x31,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01
+
+# GFX12: v_max_num_f16_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x02,0x31,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x01,0x13]
+0x05,0x02,0x31,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x01,0x13
+
+# GFX12: v_max_num_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x83,0x31,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x0d,0x30]
+0xff,0x83,0x31,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_max_num_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_max_num_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_max_num_f32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_max_num_f32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_max_num_f32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_max_num_f32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_max_num_f32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_max_num_f32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_max_num_f32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_max_num_f32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_max_num_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x16,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_max_num_f32_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x16,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+0x05,0x01,0x16,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01
+
+# GFX12: v_max_num_f32_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x02,0x16,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x01,0x13]
+0x05,0x02,0x16,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x01,0x13
+
+# GFX12: v_max_num_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x83,0x16,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x0d,0x30]
+0xff,0x83,0x16,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_max_i32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_max_i32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_max_i32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_max_i32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_max_i32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_max_i32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_max_i32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_max_i32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_max_i32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_max_i32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_max_i32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_max_i32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_max_i32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x12,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_max_i32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x12,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x12,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_max_u32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_max_u32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_max_u32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_max_u32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_max_u32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_max_u32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_max_u32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_max_u32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_max_u32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_max_u32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_max_u32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_max_u32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_max_u32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x14,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_max_u32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x14,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x14,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_min_num_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_min_num_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_min_num_f16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_min_num_f16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_min_num_f16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_min_num_f16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_min_num_f16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_min_num_f16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_min_num_f16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_min_num_f16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_min_num_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_min_num_f16_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x30,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+0x05,0x01,0x30,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01
+
+# GFX12: v_min_num_f16_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x02,0x30,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x01,0x13]
+0x05,0x02,0x30,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x01,0x13
+
+# GFX12: v_min_num_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x83,0x30,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x0d,0x30]
+0xff,0x83,0x30,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_min_num_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_min_num_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_min_num_f32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_min_num_f32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_min_num_f32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_min_num_f32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_min_num_f32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_min_num_f32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_min_num_f32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_min_num_f32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_min_num_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x15,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_min_num_f32_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x15,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+0x05,0x01,0x15,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01
+
+# GFX12: v_min_num_f32_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x02,0x15,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x01,0x13]
+0x05,0x02,0x15,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x01,0x13
+
+# GFX12: v_min_num_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x83,0x15,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x0d,0x30]
+0xff,0x83,0x15,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_min_i32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_min_i32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_min_i32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_min_i32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_min_i32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_min_i32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_min_i32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_min_i32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_min_i32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_min_i32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_min_i32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_min_i32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_min_i32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x11,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_min_i32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x11,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x11,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_min_u32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_min_u32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_min_u32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_min_u32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_min_u32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_min_u32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_min_u32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_min_u32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_min_u32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_min_u32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_min_u32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_min_u32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_min_u32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x13,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_min_u32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x13,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x13,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_mul_dx9_zero_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_mul_dx9_zero_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_mul_dx9_zero_f32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_mul_dx9_zero_f32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_mul_dx9_zero_f32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_mul_dx9_zero_f32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_mul_dx9_zero_f32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_mul_dx9_zero_f32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_mul_dx9_zero_f32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_mul_dx9_zero_f32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_mul_dx9_zero_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x07,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_mul_dx9_zero_f32_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x07,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+0x05,0x01,0x07,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01
+
+# GFX12: v_mul_dx9_zero_f32_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x02,0x07,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x01,0x13]
+0x05,0x02,0x07,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x01,0x13
+
+# GFX12: v_mul_dx9_zero_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x83,0x07,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x0d,0x30]
+0xff,0x83,0x07,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_mul_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_mul_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_mul_f16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_mul_f16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_mul_f16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_mul_f16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_mul_f16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_mul_f16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_mul_f16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_mul_f16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_mul_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_mul_f16_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x35,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+0x05,0x01,0x35,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01
+
+# GFX12: v_mul_f16_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x02,0x35,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x01,0x13]
+0x05,0x02,0x35,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x01,0x13
+
+# GFX12: v_mul_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x83,0x35,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x0d,0x30]
+0xff,0x83,0x35,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_mul_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_mul_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_mul_f32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_mul_f32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_mul_f32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_mul_f32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_mul_f32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_mul_f32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_mul_f32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_mul_f32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_mul_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x08,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_mul_f32_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x08,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+0x05,0x01,0x08,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01
+
+# GFX12: v_mul_f32_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x02,0x08,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x01,0x13]
+0x05,0x02,0x08,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x01,0x13
+
+# GFX12: v_mul_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x83,0x08,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x0d,0x30]
+0xff,0x83,0x08,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_mul_hi_i32_i24_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_mul_hi_i32_i24_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_mul_hi_i32_i24_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_mul_hi_i32_i24_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_mul_hi_i32_i24_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_mul_hi_i32_i24_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_mul_hi_i32_i24_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_mul_hi_i32_i24_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_mul_hi_i32_i24_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_mul_hi_i32_i24_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_mul_hi_i32_i24_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_mul_hi_i32_i24_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_mul_hi_i32_i24_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x0a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_mul_hi_i32_i24_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x0a,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x0a,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_mul_hi_u32_u24_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_mul_hi_u32_u24_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_mul_hi_u32_u24_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_mul_hi_u32_u24_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_mul_hi_u32_u24_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_mul_hi_u32_u24_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_mul_hi_u32_u24_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_mul_hi_u32_u24_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_mul_hi_u32_u24_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_mul_hi_u32_u24_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_mul_hi_u32_u24_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_mul_hi_u32_u24_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_mul_hi_u32_u24_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x0c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_mul_hi_u32_u24_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x0c,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x0c,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_mul_i32_i24_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_mul_i32_i24_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_mul_i32_i24_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_mul_i32_i24_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_mul_i32_i24_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_mul_i32_i24_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_mul_i32_i24_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_mul_i32_i24_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_mul_i32_i24_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_mul_i32_i24_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_mul_i32_i24_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_mul_i32_i24_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_mul_i32_i24_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x09,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_mul_i32_i24_e64_dpp v255, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x80,0x09,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x80,0x09,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_mul_u32_u24_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_mul_u32_u24_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_mul_u32_u24_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_mul_u32_u24_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_mul_u32_u24_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_mul_u32_u24_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_mul_u32_u24_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_mul_u32_u24_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_mul_u32_u24_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_mul_u32_u24_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_mul_u32_u24_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_mul_u32_u24_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_mul_u32_u24_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x0b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_mul_u32_u24_e64_dpp v255, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x80,0x0b,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x80,0x0b,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_or_b32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_or_b32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_or_b32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_or_b32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_or_b32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_or_b32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_or_b32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_or_b32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_or_b32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_or_b32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_or_b32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_or_b32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_or_b32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x1c,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_or_b32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x1c,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x1c,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_sub_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_sub_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_sub_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_sub_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_sub_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x40,0x01,0xff]
+# W64: v_sub_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x40,0x01,0xff]
+0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_sub_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x41,0x01,0xff]
+# W64: v_sub_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x41,0x01,0xff]
+0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_sub_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x01,0x01,0xff]
+# W64: v_sub_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x01,0x01,0xff]
+0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_sub_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_sub_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_sub_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x11,0x01,0xff]
+# W64: v_sub_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x11,0x01,0xff]
+0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_sub_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_sub_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_sub_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x21,0x01,0xff]
+# W64: v_sub_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x21,0x01,0xff]
+0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_sub_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_sub_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x0c,0x21,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_sub_co_ci_u32_e64_dpp v5, s104, v1, v2, s104 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x68,0x21,0xd5,0xfa,0x04,0xa2,0x01,0x01,0x50,0x01,0xff]
+# W64: v_sub_co_ci_u32_e64_dpp v5, s[104:105], v1, v2, s[104:105] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x68,0x21,0xd5,0xfa,0x04,0xa2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x68,0x21,0xd5,0xfa,0x04,0xa2,0x01,0x01,0x50,0x01,0xff
+
+# W32: v_sub_co_ci_u32_e64_dpp v5, vcc_lo, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x6a,0x21,0xd5,0xfa,0x04,0xaa,0x01,0x01,0x5f,0x01,0x01]
+# W64: v_sub_co_ci_u32_e64_dpp v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x6a,0x21,0xd5,0xfa,0x04,0xaa,0x01,0x01,0x5f,0x01,0x01]
+0x05,0x6a,0x21,0xd5,0xfa,0x04,0xaa,0x01,0x01,0x5f,0x01,0x01
+
+# W32: v_sub_co_ci_u32_e64_dpp v5, ttmp14, v1, v2, ttmp14 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x7a,0x21,0xd5,0xfa,0x04,0xea,0x01,0x01,0x60,0x01,0x13]
+# W64: v_sub_co_ci_u32_e64_dpp v5, ttmp[14:15], v1, v2, ttmp[14:15] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x7a,0x21,0xd5,0xfa,0x04,0xea,0x01,0x01,0x60,0x01,0x13]
+0x05,0x7a,0x21,0xd5,0xfa,0x04,0xea,0x01,0x01,0x60,0x01,0x13
+
+# GFX12: v_sub_co_ci_u32_e64_dpp v255, null, v255, v255, null clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0xfc,0x21,0xd5,0xfa,0xfe,0xf3,0x01,0xff,0x6f,0x0d,0x30]
+0xff,0xfc,0x21,0xd5,0xfa,0xfe,0xf3,0x01,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_sub_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_sub_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_sub_f16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_sub_f16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_sub_f16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_sub_f16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_sub_f16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_sub_f16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_sub_f16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_sub_f16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_sub_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_sub_f16_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x33,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+0x05,0x01,0x33,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01
+
+# GFX12: v_sub_f16_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x02,0x33,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x01,0x13]
+0x05,0x02,0x33,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x01,0x13
+
+# GFX12: v_sub_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x83,0x33,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x0d,0x30]
+0xff,0x83,0x33,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_sub_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_sub_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_sub_f32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_sub_f32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_sub_f32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_sub_f32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_sub_f32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_sub_f32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_sub_f32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_sub_f32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_sub_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x04,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_sub_f32_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x04,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+0x05,0x01,0x04,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01
+
+# GFX12: v_sub_f32_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x02,0x04,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x01,0x13]
+0x05,0x02,0x04,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x01,0x13
+
+# GFX12: v_sub_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x83,0x04,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x0d,0x30]
+0xff,0x83,0x04,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_sub_nc_u32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_sub_nc_u32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_sub_nc_u32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_sub_nc_u32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_sub_nc_u32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_sub_nc_u32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_sub_nc_u32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_sub_nc_u32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_sub_nc_u32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_sub_nc_u32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_sub_nc_u32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_sub_nc_u32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_sub_nc_u32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x26,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_sub_nc_u32_e64_dpp v255, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x80,0x26,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x80,0x26,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_subrev_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_subrev_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_subrev_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_subrev_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_subrev_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x40,0x01,0xff]
+# W64: v_subrev_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x40,0x01,0xff]
+0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_subrev_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x41,0x01,0xff]
+# W64: v_subrev_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x41,0x01,0xff]
+0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_subrev_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x01,0x01,0xff]
+# W64: v_subrev_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x01,0x01,0xff]
+0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_subrev_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_subrev_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_subrev_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x11,0x01,0xff]
+# W64: v_subrev_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x11,0x01,0xff]
+0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_subrev_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_subrev_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_subrev_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x21,0x01,0xff]
+# W64: v_subrev_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x21,0x01,0xff]
+0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_subrev_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_subrev_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x0c,0x22,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_subrev_co_ci_u32_e64_dpp v5, s104, v1, v2, s104 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x68,0x22,0xd5,0xfa,0x04,0xa2,0x01,0x01,0x50,0x01,0xff]
+# W64: v_subrev_co_ci_u32_e64_dpp v5, s[104:105], v1, v2, s[104:105] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x68,0x22,0xd5,0xfa,0x04,0xa2,0x01,0x01,0x50,0x01,0xff]
+0x05,0x68,0x22,0xd5,0xfa,0x04,0xa2,0x01,0x01,0x50,0x01,0xff
+
+# W32: v_subrev_co_ci_u32_e64_dpp v5, vcc_lo, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x6a,0x22,0xd5,0xfa,0x04,0xaa,0x01,0x01,0x5f,0x01,0x01]
+# W64: v_subrev_co_ci_u32_e64_dpp v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x6a,0x22,0xd5,0xfa,0x04,0xaa,0x01,0x01,0x5f,0x01,0x01]
+0x05,0x6a,0x22,0xd5,0xfa,0x04,0xaa,0x01,0x01,0x5f,0x01,0x01
+
+# W32: v_subrev_co_ci_u32_e64_dpp v5, ttmp14, v1, v2, ttmp14 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x7a,0x22,0xd5,0xfa,0x04,0xea,0x01,0x01,0x60,0x01,0x13]
+# W64: v_subrev_co_ci_u32_e64_dpp v5, ttmp[14:15], v1, v2, ttmp[14:15] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x7a,0x22,0xd5,0xfa,0x04,0xea,0x01,0x01,0x60,0x01,0x13]
+0x05,0x7a,0x22,0xd5,0xfa,0x04,0xea,0x01,0x01,0x60,0x01,0x13
+
+# GFX12: v_subrev_co_ci_u32_e64_dpp v255, null, v255, v255, null clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0xfc,0x22,0xd5,0xfa,0xfe,0xf3,0x01,0xff,0x6f,0x0d,0x30]
+0xff,0xfc,0x22,0xd5,0xfa,0xfe,0xf3,0x01,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_subrev_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_subrev_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_subrev_f16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_subrev_f16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_subrev_f16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_subrev_f16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_subrev_f16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_subrev_f16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_subrev_f16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_subrev_f16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_subrev_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_subrev_f16_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x34,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+0x05,0x01,0x34,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01
+
+# GFX12: v_subrev_f16_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x02,0x34,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x01,0x13]
+0x05,0x02,0x34,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x01,0x13
+
+# GFX12: v_subrev_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x83,0x34,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x0d,0x30]
+0xff,0x83,0x34,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_subrev_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_subrev_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_subrev_f32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_subrev_f32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_subrev_f32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_subrev_f32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_subrev_f32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_subrev_f32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_subrev_f32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_subrev_f32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_subrev_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_subrev_f32_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x05,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+0x05,0x01,0x05,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01
+
+# GFX12: v_subrev_f32_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x02,0x05,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x01,0x13]
+0x05,0x02,0x05,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x01,0x13
+
+# GFX12: v_subrev_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x83,0x05,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x0d,0x30]
+0xff,0x83,0x05,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_subrev_nc_u32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_subrev_nc_u32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_subrev_nc_u32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_subrev_nc_u32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_subrev_nc_u32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_subrev_nc_u32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_subrev_nc_u32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_subrev_nc_u32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_subrev_nc_u32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_subrev_nc_u32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_subrev_nc_u32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_subrev_nc_u32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_subrev_nc_u32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x27,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_subrev_nc_u32_e64_dpp v255, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x80,0x27,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x80,0x27,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_xnor_b32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_xnor_b32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_xnor_b32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_xnor_b32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_xnor_b32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_xnor_b32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_xnor_b32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_xnor_b32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_xnor_b32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_xnor_b32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_xnor_b32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_xnor_b32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_xnor_b32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x1e,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_xnor_b32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x1e,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x1e,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_xor_b32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_xor_b32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_xor_b32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_xor_b32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_xor_b32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_xor_b32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_xor_b32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_xor_b32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_xor_b32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_xor_b32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_xor_b32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_xor_b32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_xor_b32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x05,0x00,0x1d,0xd5,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_xor_b32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x1d,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0xff,0x00,0x1d,0xd5,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2_dpp8.txt
new file mode 100644
index 000000000000..3972cc7b9a61
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2_dpp8.txt
@@ -0,0 +1,366 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32 %s
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64 %s
+
+# W32: v_add_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x0c,0x20,0xd5,0xe9,0x04,0x1a,0x00,0x01,0x77,0x39,0x05]
+# W64: v_add_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x0c,0x20,0xd5,0xe9,0x04,0x1a,0x00,0x01,0x77,0x39,0x05]
+0x05,0x0c,0x20,0xd5,0xe9,0x04,0x1a,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_add_co_ci_u32_e64_dpp v5, s104, v1, v2, s104 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x68,0x20,0xd5,0xe9,0x04,0xa2,0x01,0x01,0x77,0x39,0x05]
+# W64: v_add_co_ci_u32_e64_dpp v5, s[104:105], v1, v2, s[104:105] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x68,0x20,0xd5,0xe9,0x04,0xa2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x68,0x20,0xd5,0xe9,0x04,0xa2,0x01,0x01,0x77,0x39,0x05
+
+# W32: v_add_co_ci_u32_e64_dpp v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x6a,0x20,0xd5,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+# W64: v_add_co_ci_u32_e64_dpp v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x6a,0x20,0xd5,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x6a,0x20,0xd5,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# W32: v_add_co_ci_u32_e64_dpp v5, ttmp14, v1, v2, ttmp14 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x7a,0x20,0xd5,0xe9,0x04,0xea,0x01,0x01,0x77,0x39,0x05]
+# W64: v_add_co_ci_u32_e64_dpp v5, ttmp[14:15], v1, v2, ttmp[14:15] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x7a,0x20,0xd5,0xe9,0x04,0xea,0x01,0x01,0x77,0x39,0x05]
+0x05,0x7a,0x20,0xd5,0xe9,0x04,0xea,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_co_ci_u32_e64_dpp v255, null, v255, v255, null clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0xfc,0x20,0xd5,0xea,0xfe,0xf3,0x01,0xff,0x00,0x00,0x00]
+0xff,0xfc,0x20,0xd5,0xea,0xfe,0xf3,0x01,0xff,0x00,0x00,0x00
+
+# GFX12: v_add_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x32,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x32,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_f16_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x32,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+0x05,0x01,0x32,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_f16_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x32,0xd5,0xe9,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+0x05,0x02,0x32,0xd5,0xe9,0x04,0x02,0x30,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x83,0x32,0xd5,0xea,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+0xff,0x83,0x32,0xd5,0xea,0xfe,0x03,0x78,0xff,0x00,0x00,0x00
+
+# GFX12: v_add_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x03,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x03,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_f32_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x03,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+0x05,0x01,0x03,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_f32_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x03,0xd5,0xe9,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+0x05,0x02,0x03,0xd5,0xe9,0x04,0x02,0x30,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x83,0x03,0xd5,0xea,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+0xff,0x83,0x03,0xd5,0xea,0xfe,0x03,0x78,0xff,0x00,0x00,0x00
+
+# GFX12: v_add_nc_u32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x25,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x25,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_add_nc_u32_e64_dpp v255, v255, v255 clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x80,0x25,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x80,0x25,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_and_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1b,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1b,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_and_b32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x1b,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x1b,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_ashrrev_i32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1a,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1a,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_ashrrev_i32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x1a,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x1a,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_cndmask_b32_e64_dpp v5, v1, v2, s6 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x01,0xd5,0xe9,0x04,0x1a,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cndmask_b32_e64_dpp v5, v1, v2, s[6:7] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x01,0xd5,0xe9,0x04,0x1a,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x01,0xd5,0xe9,0x04,0x1a,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cndmask_b32_e64_dpp v5, v1, v2, s104 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x01,0xd5,0xe9,0x04,0xa2,0x01,0x01,0x77,0x39,0x05]
+# W64: v_cndmask_b32_e64_dpp v5, v1, v2, s[104:105] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x01,0xd5,0xe9,0x04,0xa2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x01,0xd5,0xe9,0x04,0xa2,0x01,0x01,0x77,0x39,0x05
+
+# W32: v_cndmask_b32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x01,0xd5,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+# W64: v_cndmask_b32_e64_dpp v5, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x01,0xd5,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x01,0xd5,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# W32: v_cndmask_b32_e64_dpp v5, v1, v2, ttmp14 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x01,0xd5,0xe9,0x04,0xea,0x01,0x01,0x77,0x39,0x05]
+# W64: v_cndmask_b32_e64_dpp v5, v1, v2, ttmp[14:15] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x01,0xd5,0xe9,0x04,0xea,0x01,0x01,0x77,0x39,0x05]
+0x05,0x00,0x01,0xd5,0xe9,0x04,0xea,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_cndmask_b32_e64_dpp v255, v255, v255, null dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x01,0xd5,0xea,0xfe,0xf3,0x01,0xff,0x00,0x00,0x00]
+0xff,0x00,0x01,0xd5,0xea,0xfe,0xf3,0x01,0xff,0x00,0x00,0x00
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2f,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x2f,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x2f,0xd5,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x05,0x01,0x2f,0xd5,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x2f,0xd5,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x05,0x02,0x2f,0xd5,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cvt_pk_rtz_f16_f32_e64_dpp v255, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x83,0x2f,0xd5,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0xff,0x83,0x2f,0xd5,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_ldexp_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x3b,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x3b,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_ldexp_f16_e64_dpp v5, v1, v2 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x3b,0xd5,0xe9,0x04,0x02,0x08,0x01,0x77,0x39,0x05]
+0x05,0x00,0x3b,0xd5,0xe9,0x04,0x02,0x08,0x01,0x77,0x39,0x05
+
+# GFX12: v_ldexp_f16_e64_dpp v5, v1, v2 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x3b,0xd5,0xe9,0x04,0x02,0x10,0x01,0x77,0x39,0x05]
+0x05,0x00,0x3b,0xd5,0xe9,0x04,0x02,0x10,0x01,0x77,0x39,0x05
+
+# GFX12: v_ldexp_f16_e64_dpp v255, -|v255|, v255 clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x81,0x3b,0xd5,0xea,0xfe,0x03,0x38,0xff,0x00,0x00,0x00]
+0xff,0x81,0x3b,0xd5,0xea,0xfe,0x03,0x38,0xff,0x00,0x00,0x00
+
+# GFX12: v_lshlrev_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x18,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x18,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_lshlrev_b32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x18,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x18,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_lshrrev_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x19,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x19,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_lshrrev_b32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x19,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x19,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_max_num_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x31,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x31,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_max_num_f16_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x31,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+0x05,0x01,0x31,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05
+
+# GFX12: v_max_num_f16_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x31,0xd5,0xe9,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+0x05,0x02,0x31,0xd5,0xe9,0x04,0x02,0x30,0x01,0x77,0x39,0x05
+
+# GFX12: v_max_num_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x83,0x31,0xd5,0xea,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+0xff,0x83,0x31,0xd5,0xea,0xfe,0x03,0x78,0xff,0x00,0x00,0x00
+
+# GFX12: v_max_num_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x16,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_max_num_f32_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x16,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+0x05,0x01,0x16,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05
+
+# GFX12: v_max_num_f32_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x16,0xd5,0xe9,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+0x05,0x02,0x16,0xd5,0xe9,0x04,0x02,0x30,0x01,0x77,0x39,0x05
+
+# GFX12: v_max_num_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x83,0x16,0xd5,0xea,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+0xff,0x83,0x16,0xd5,0xea,0xfe,0x03,0x78,0xff,0x00,0x00,0x00
+
+# GFX12: v_max_i32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x12,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x12,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_max_i32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x12,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x12,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_max_u32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x14,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x14,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_max_u32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x14,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x14,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_min_num_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x30,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x30,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_min_num_f16_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x30,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+0x05,0x01,0x30,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05
+
+# GFX12: v_min_num_f16_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x30,0xd5,0xe9,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+0x05,0x02,0x30,0xd5,0xe9,0x04,0x02,0x30,0x01,0x77,0x39,0x05
+
+# GFX12: v_min_num_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x83,0x30,0xd5,0xea,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+0xff,0x83,0x30,0xd5,0xea,0xfe,0x03,0x78,0xff,0x00,0x00,0x00
+
+# GFX12: v_min_num_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x15,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x15,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_min_num_f32_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x15,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+0x05,0x01,0x15,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05
+
+# GFX12: v_min_num_f32_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x15,0xd5,0xe9,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+0x05,0x02,0x15,0xd5,0xe9,0x04,0x02,0x30,0x01,0x77,0x39,0x05
+
+# GFX12: v_min_num_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x83,0x15,0xd5,0xea,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+0xff,0x83,0x15,0xd5,0xea,0xfe,0x03,0x78,0xff,0x00,0x00,0x00
+
+# GFX12: v_min_i32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x11,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x11,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_min_i32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x11,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x11,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_min_u32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x13,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x13,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_min_u32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x13,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x13,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_mul_dx9_zero_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x07,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x07,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_mul_dx9_zero_f32_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x07,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+0x05,0x01,0x07,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05
+
+# GFX12: v_mul_dx9_zero_f32_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x07,0xd5,0xe9,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+0x05,0x02,0x07,0xd5,0xe9,0x04,0x02,0x30,0x01,0x77,0x39,0x05
+
+# GFX12: v_mul_dx9_zero_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x83,0x07,0xd5,0xea,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+0xff,0x83,0x07,0xd5,0xea,0xfe,0x03,0x78,0xff,0x00,0x00,0x00
+
+# GFX12: v_mul_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x35,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x35,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_mul_f16_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x35,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+0x05,0x01,0x35,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05
+
+# GFX12: v_mul_f16_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x35,0xd5,0xe9,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+0x05,0x02,0x35,0xd5,0xe9,0x04,0x02,0x30,0x01,0x77,0x39,0x05
+
+# GFX12: v_mul_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x83,0x35,0xd5,0xea,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+0xff,0x83,0x35,0xd5,0xea,0xfe,0x03,0x78,0xff,0x00,0x00,0x00
+
+# GFX12: v_mul_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x08,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x08,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_mul_f32_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x08,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+0x05,0x01,0x08,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05
+
+# GFX12: v_mul_f32_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x08,0xd5,0xe9,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+0x05,0x02,0x08,0xd5,0xe9,0x04,0x02,0x30,0x01,0x77,0x39,0x05
+
+# GFX12: v_mul_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x83,0x08,0xd5,0xea,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+0xff,0x83,0x08,0xd5,0xea,0xfe,0x03,0x78,0xff,0x00,0x00,0x00
+
+# GFX12: v_mul_hi_i32_i24_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0a,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0a,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_mul_hi_i32_i24_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x0a,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x0a,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_mul_hi_u32_u24_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0c,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0c,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_mul_hi_u32_u24_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x0c,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x0c,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_mul_i32_i24_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x09,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x09,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_mul_i32_i24_e64_dpp v255, v255, v255 clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x80,0x09,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x80,0x09,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_mul_u32_u24_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x0b,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x0b,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_mul_u32_u24_e64_dpp v255, v255, v255 clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x80,0x0b,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x80,0x0b,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_or_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1c,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1c,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_or_b32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x1c,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x1c,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_sub_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x0c,0x21,0xd5,0xe9,0x04,0x1a,0x00,0x01,0x77,0x39,0x05]
+# W64: v_sub_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x0c,0x21,0xd5,0xe9,0x04,0x1a,0x00,0x01,0x77,0x39,0x05]
+0x05,0x0c,0x21,0xd5,0xe9,0x04,0x1a,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_sub_co_ci_u32_e64_dpp v5, s104, v1, v2, s104 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x68,0x21,0xd5,0xe9,0x04,0xa2,0x01,0x01,0x77,0x39,0x05]
+# W64: v_sub_co_ci_u32_e64_dpp v5, s[104:105], v1, v2, s[104:105] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x68,0x21,0xd5,0xe9,0x04,0xa2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x68,0x21,0xd5,0xe9,0x04,0xa2,0x01,0x01,0x77,0x39,0x05
+
+# W32: v_sub_co_ci_u32_e64_dpp v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x6a,0x21,0xd5,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+# W64: v_sub_co_ci_u32_e64_dpp v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x6a,0x21,0xd5,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x6a,0x21,0xd5,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# W32: v_sub_co_ci_u32_e64_dpp v5, ttmp14, v1, v2, ttmp14 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x7a,0x21,0xd5,0xe9,0x04,0xea,0x01,0x01,0x77,0x39,0x05]
+# W64: v_sub_co_ci_u32_e64_dpp v5, ttmp[14:15], v1, v2, ttmp[14:15] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x7a,0x21,0xd5,0xe9,0x04,0xea,0x01,0x01,0x77,0x39,0x05]
+0x05,0x7a,0x21,0xd5,0xe9,0x04,0xea,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_sub_co_ci_u32_e64_dpp v255, null, v255, v255, null clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0xfc,0x21,0xd5,0xea,0xfe,0xf3,0x01,0xff,0x00,0x00,0x00]
+0xff,0xfc,0x21,0xd5,0xea,0xfe,0xf3,0x01,0xff,0x00,0x00,0x00
+
+# GFX12: v_sub_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x33,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x33,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_sub_f16_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x33,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+0x05,0x01,0x33,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05
+
+# GFX12: v_sub_f16_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x33,0xd5,0xe9,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+0x05,0x02,0x33,0xd5,0xe9,0x04,0x02,0x30,0x01,0x77,0x39,0x05
+
+# GFX12: v_sub_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x83,0x33,0xd5,0xea,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+0xff,0x83,0x33,0xd5,0xea,0xfe,0x03,0x78,0xff,0x00,0x00,0x00
+
+# GFX12: v_sub_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x04,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x04,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_sub_f32_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x04,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+0x05,0x01,0x04,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05
+
+# GFX12: v_sub_f32_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x04,0xd5,0xe9,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+0x05,0x02,0x04,0xd5,0xe9,0x04,0x02,0x30,0x01,0x77,0x39,0x05
+
+# GFX12: v_sub_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x83,0x04,0xd5,0xea,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+0xff,0x83,0x04,0xd5,0xea,0xfe,0x03,0x78,0xff,0x00,0x00,0x00
+
+# GFX12: v_sub_nc_u32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x26,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x26,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_sub_nc_u32_e64_dpp v255, v255, v255 clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x80,0x26,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x80,0x26,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_subrev_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x0c,0x22,0xd5,0xe9,0x04,0x1a,0x00,0x01,0x77,0x39,0x05]
+# W64: v_subrev_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x0c,0x22,0xd5,0xe9,0x04,0x1a,0x00,0x01,0x77,0x39,0x05]
+0x05,0x0c,0x22,0xd5,0xe9,0x04,0x1a,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_subrev_co_ci_u32_e64_dpp v5, s104, v1, v2, s104 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x68,0x22,0xd5,0xe9,0x04,0xa2,0x01,0x01,0x77,0x39,0x05]
+# W64: v_subrev_co_ci_u32_e64_dpp v5, s[104:105], v1, v2, s[104:105] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x68,0x22,0xd5,0xe9,0x04,0xa2,0x01,0x01,0x77,0x39,0x05]
+0x05,0x68,0x22,0xd5,0xe9,0x04,0xa2,0x01,0x01,0x77,0x39,0x05
+
+# W32: v_subrev_co_ci_u32_e64_dpp v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x6a,0x22,0xd5,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+# W64: v_subrev_co_ci_u32_e64_dpp v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x6a,0x22,0xd5,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
+0x05,0x6a,0x22,0xd5,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
+
+# W32: v_subrev_co_ci_u32_e64_dpp v5, ttmp14, v1, v2, ttmp14 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x7a,0x22,0xd5,0xe9,0x04,0xea,0x01,0x01,0x77,0x39,0x05]
+# W64: v_subrev_co_ci_u32_e64_dpp v5, ttmp[14:15], v1, v2, ttmp[14:15] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x7a,0x22,0xd5,0xe9,0x04,0xea,0x01,0x01,0x77,0x39,0x05]
+0x05,0x7a,0x22,0xd5,0xe9,0x04,0xea,0x01,0x01,0x77,0x39,0x05
+
+# GFX12: v_subrev_co_ci_u32_e64_dpp v255, null, v255, v255, null clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0xfc,0x22,0xd5,0xea,0xfe,0xf3,0x01,0xff,0x00,0x00,0x00]
+0xff,0xfc,0x22,0xd5,0xea,0xfe,0xf3,0x01,0xff,0x00,0x00,0x00
+
+# GFX12: v_subrev_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x34,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x34,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_subrev_f16_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x34,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+0x05,0x01,0x34,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05
+
+# GFX12: v_subrev_f16_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x34,0xd5,0xe9,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+0x05,0x02,0x34,0xd5,0xe9,0x04,0x02,0x30,0x01,0x77,0x39,0x05
+
+# GFX12: v_subrev_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x83,0x34,0xd5,0xea,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+0xff,0x83,0x34,0xd5,0xea,0xfe,0x03,0x78,0xff,0x00,0x00,0x00
+
+# GFX12: v_subrev_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x05,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x05,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_subrev_f32_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x05,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+0x05,0x01,0x05,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05
+
+# GFX12: v_subrev_f32_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x05,0xd5,0xe9,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+0x05,0x02,0x05,0xd5,0xe9,0x04,0x02,0x30,0x01,0x77,0x39,0x05
+
+# GFX12: v_subrev_f32_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x83,0x05,0xd5,0xea,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+0xff,0x83,0x05,0xd5,0xea,0xfe,0x03,0x78,0xff,0x00,0x00,0x00
+
+# GFX12: v_subrev_nc_u32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x27,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x27,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_subrev_nc_u32_e64_dpp v255, v255, v255 clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x80,0x27,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x80,0x27,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_xnor_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1e,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1e,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_xnor_b32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x1e,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x1e,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_xor_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x1d,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x05,0x00,0x1d,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_xor_b32_e64_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x1d,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0xff,0x00,0x1d,0xd5,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt
new file mode 100644
index 000000000000..3062124e36b8
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt
@@ -0,0 +1,4469 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32 %s
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64 %s
+
+# W32: v_cmp_class_f16_e64 s10, v1, v2           ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_class_f16_e64 s[10:11], v1, v2      ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_class_f16_e64 s10, v255, v2         ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00]
+# W64: v_cmp_class_f16_e64 s[10:11], v255, v2    ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00]
+0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00
+
+# W32: v_cmp_class_f16_e64 s10, s1, v2           ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00]
+# W64: v_cmp_class_f16_e64 s[10:11], s1, v2      ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00]
+0x0a,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00
+
+# W32: v_cmp_class_f16_e64 s10, s105, v255       ; encoding: [0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00]
+# W64: v_cmp_class_f16_e64 s[10:11], s105, v255  ; encoding: [0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00]
+0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00
+
+# W32: v_cmp_class_f16_e64 s10, vcc_lo, s2       ; encoding: [0x0a,0x00,0x7d,0xd4,0x6a,0x04,0x00,0x00]
+# W64: v_cmp_class_f16_e64 s[10:11], vcc_lo, s2  ; encoding: [0x0a,0x00,0x7d,0xd4,0x6a,0x04,0x00,0x00]
+0x0a,0x00,0x7d,0xd4,0x6a,0x04,0x00,0x00
+
+# W32: v_cmp_class_f16_e64 s10, vcc_hi, s105     ; encoding: [0x0a,0x00,0x7d,0xd4,0x6b,0xd2,0x00,0x00]
+# W64: v_cmp_class_f16_e64 s[10:11], vcc_hi, s105 ; encoding: [0x0a,0x00,0x7d,0xd4,0x6b,0xd2,0x00,0x00]
+0x0a,0x00,0x7d,0xd4,0x6b,0xd2,0x00,0x00
+
+# W32: v_cmp_class_f16_e64 s10, ttmp15, ttmp15   ; encoding: [0x0a,0x00,0x7d,0xd4,0x7b,0xf6,0x00,0x00]
+# W64: v_cmp_class_f16_e64 s[10:11], ttmp15, ttmp15 ; encoding: [0x0a,0x00,0x7d,0xd4,0x7b,0xf6,0x00,0x00]
+0x0a,0x00,0x7d,0xd4,0x7b,0xf6,0x00,0x00
+
+# W32: v_cmp_class_f16_e64 s10, m0, src_scc      ; encoding: [0x0a,0x00,0x7d,0xd4,0x7d,0xfa,0x01,0x00]
+# W64: v_cmp_class_f16_e64 s[10:11], m0, src_scc ; encoding: [0x0a,0x00,0x7d,0xd4,0x7d,0xfa,0x01,0x00]
+0x0a,0x00,0x7d,0xd4,0x7d,0xfa,0x01,0x00
+
+# W32: v_cmp_class_f16_e64 s10, exec_lo, -1      ; encoding: [0x0a,0x00,0x7d,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_class_f16_e64 s[10:11], exec_lo, -1 ; encoding: [0x0a,0x00,0x7d,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x7d,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_class_f16_e64 s10, exec_hi, null    ; encoding: [0x0a,0x00,0x7d,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_class_f16_e64 s[10:11], exec_hi, null ; encoding: [0x0a,0x00,0x7d,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x00,0x7d,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_class_f16_e64 s10, null, exec_lo    ; encoding: [0x0a,0x00,0x7d,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_class_f16_e64 s[10:11], null, exec_lo ; encoding: [0x0a,0x00,0x7d,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x7d,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_class_f16_e64 s104, -1, exec_hi     ; encoding: [0x68,0x00,0x7d,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_class_f16_e64 s[104:105], -1, exec_hi ; encoding: [0x68,0x00,0x7d,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x7d,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_class_f16_e64 vcc_lo, 0.5, m0       ; encoding: [0x6a,0x00,0x7d,0xd4,0xf0,0xfa,0x00,0x00]
+# W64: v_cmp_class_f16_e64 vcc, 0.5, m0          ; encoding: [0x6a,0x00,0x7d,0xd4,0xf0,0xfa,0x00,0x00]
+0x6a,0x00,0x7d,0xd4,0xf0,0xfa,0x00,0x00
+
+# W32: v_cmp_class_f16_e64 ttmp14, src_scc, vcc_lo ; encoding: [0x7a,0x00,0x7d,0xd4,0xfd,0xd4,0x00,0x00]
+# W64: v_cmp_class_f16_e64 ttmp[14:15], src_scc, vcc_lo ; encoding: [0x7a,0x00,0x7d,0xd4,0xfd,0xd4,0x00,0x00]
+0x7a,0x00,0x7d,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmp_class_f16_e64 null, -|0xfe0b|, vcc_hi ; encoding: [0x7c,0x01,0x7d,0xd4,0xff,0xd6,0x00,0x20,0x0b,0xfe,0x00,0x00]
+0x7c,0x01,0x7d,0xd4,0xff,0xd6,0x00,0x20,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_class_f32_e64 s10, v1, v2           ; encoding: [0x0a,0x00,0x7e,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_class_f32_e64 s[10:11], v1, v2      ; encoding: [0x0a,0x00,0x7e,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x7e,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_class_f32_e64 s10, v255, v255       ; encoding: [0x0a,0x00,0x7e,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_class_f32_e64 s[10:11], v255, v255  ; encoding: [0x0a,0x00,0x7e,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x7e,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_class_f32_e64 s10, s1, s2           ; encoding: [0x0a,0x00,0x7e,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_class_f32_e64 s[10:11], s1, s2      ; encoding: [0x0a,0x00,0x7e,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x7e,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_class_f32_e64 s10, s105, s105       ; encoding: [0x0a,0x00,0x7e,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_class_f32_e64 s[10:11], s105, s105  ; encoding: [0x0a,0x00,0x7e,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x7e,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_class_f32_e64 s10, vcc_lo, ttmp15   ; encoding: [0x0a,0x00,0x7e,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_class_f32_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x7e,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x7e,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_class_f32_e64 s10, vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x7e,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_class_f32_e64 s[10:11], vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x7e,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x7e,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_class_f32_e64 s10, ttmp15, src_scc  ; encoding: [0x0a,0x00,0x7e,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_class_f32_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x7e,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x7e,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_class_f32_e64 s10, m0, 0.5          ; encoding: [0x0a,0x00,0x7e,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_class_f32_e64 s[10:11], m0, 0.5     ; encoding: [0x0a,0x00,0x7e,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x7e,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_class_f32_e64 s10, exec_lo, -1      ; encoding: [0x0a,0x00,0x7e,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_class_f32_e64 s[10:11], exec_lo, -1 ; encoding: [0x0a,0x00,0x7e,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x7e,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_class_f32_e64 s10, exec_hi, null    ; encoding: [0x0a,0x00,0x7e,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_class_f32_e64 s[10:11], exec_hi, null ; encoding: [0x0a,0x00,0x7e,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x00,0x7e,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_class_f32_e64 s10, null, exec_lo    ; encoding: [0x0a,0x00,0x7e,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_class_f32_e64 s[10:11], null, exec_lo ; encoding: [0x0a,0x00,0x7e,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x7e,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_class_f32_e64 s104, -1, exec_hi     ; encoding: [0x68,0x00,0x7e,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_class_f32_e64 s[104:105], -1, exec_hi ; encoding: [0x68,0x00,0x7e,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x7e,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_class_f32_e64 vcc_lo, 0.5, m0       ; encoding: [0x6a,0x00,0x7e,0xd4,0xf0,0xfa,0x00,0x00]
+# W64: v_cmp_class_f32_e64 vcc, 0.5, m0          ; encoding: [0x6a,0x00,0x7e,0xd4,0xf0,0xfa,0x00,0x00]
+0x6a,0x00,0x7e,0xd4,0xf0,0xfa,0x00,0x00
+
+# W32: v_cmp_class_f32_e64 ttmp14, src_scc, vcc_lo ; encoding: [0x7a,0x00,0x7e,0xd4,0xfd,0xd4,0x00,0x00]
+# W64: v_cmp_class_f32_e64 ttmp[14:15], src_scc, vcc_lo ; encoding: [0x7a,0x00,0x7e,0xd4,0xfd,0xd4,0x00,0x00]
+0x7a,0x00,0x7e,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmp_class_f32_e64 null, -|0xaf123456|, vcc_hi ; encoding: [0x7c,0x01,0x7e,0xd4,0xff,0xd6,0x00,0x20,0x56,0x34,0x12,0xaf]
+0x7c,0x01,0x7e,0xd4,0xff,0xd6,0x00,0x20,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_class_f64_e64 s10, v[1:2], v2       ; encoding: [0x0a,0x00,0x7f,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_class_f64_e64 s[10:11], v[1:2], v2  ; encoding: [0x0a,0x00,0x7f,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x7f,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_class_f64_e64 s10, v[1:2], v255     ; encoding: [0x0a,0x00,0x7f,0xd4,0x01,0xff,0x03,0x00]
+# W64: v_cmp_class_f64_e64 s[10:11], v[1:2], v255 ; encoding: [0x0a,0x00,0x7f,0xd4,0x01,0xff,0x03,0x00]
+0x0a,0x00,0x7f,0xd4,0x01,0xff,0x03,0x00
+
+# W32: v_cmp_class_f64_e64 s10, v[1:2], s2       ; encoding: [0x0a,0x00,0x7f,0xd4,0x01,0x05,0x00,0x00]
+# W64: v_cmp_class_f64_e64 s[10:11], v[1:2], s2  ; encoding: [0x0a,0x00,0x7f,0xd4,0x01,0x05,0x00,0x00]
+0x0a,0x00,0x7f,0xd4,0x01,0x05,0x00,0x00
+
+# W32: v_cmp_class_f64_e64 s10, v[1:2], s105     ; encoding: [0x0a,0x00,0x7f,0xd4,0x01,0xd3,0x00,0x00]
+# W64: v_cmp_class_f64_e64 s[10:11], v[1:2], s105 ; encoding: [0x0a,0x00,0x7f,0xd4,0x01,0xd3,0x00,0x00]
+0x0a,0x00,0x7f,0xd4,0x01,0xd3,0x00,0x00
+
+# W32: v_cmp_class_f64_e64 s10, v[254:255], ttmp15 ; encoding: [0x0a,0x00,0x7f,0xd4,0xfe,0xf7,0x00,0x00]
+# W64: v_cmp_class_f64_e64 s[10:11], v[254:255], ttmp15 ; encoding: [0x0a,0x00,0x7f,0xd4,0xfe,0xf7,0x00,0x00]
+0x0a,0x00,0x7f,0xd4,0xfe,0xf7,0x00,0x00
+
+# W32: v_cmp_class_f64_e64 s10, s[2:3], vcc_hi   ; encoding: [0x0a,0x00,0x7f,0xd4,0x02,0xd6,0x00,0x00]
+# W64: v_cmp_class_f64_e64 s[10:11], s[2:3], vcc_hi ; encoding: [0x0a,0x00,0x7f,0xd4,0x02,0xd6,0x00,0x00]
+0x0a,0x00,0x7f,0xd4,0x02,0xd6,0x00,0x00
+
+# W32: v_cmp_class_f64_e64 s10, s[104:105], vcc_lo ; encoding: [0x0a,0x00,0x7f,0xd4,0x68,0xd4,0x00,0x00]
+# W64: v_cmp_class_f64_e64 s[10:11], s[104:105], vcc_lo ; encoding: [0x0a,0x00,0x7f,0xd4,0x68,0xd4,0x00,0x00]
+0x0a,0x00,0x7f,0xd4,0x68,0xd4,0x00,0x00
+
+# W32: v_cmp_class_f64_e64 s10, vcc, m0          ; encoding: [0x0a,0x00,0x7f,0xd4,0x6a,0xfa,0x00,0x00]
+# W64: v_cmp_class_f64_e64 s[10:11], vcc, m0     ; encoding: [0x0a,0x00,0x7f,0xd4,0x6a,0xfa,0x00,0x00]
+0x0a,0x00,0x7f,0xd4,0x6a,0xfa,0x00,0x00
+
+# W32: v_cmp_class_f64_e64 s10, ttmp[14:15], exec_hi ; encoding: [0x0a,0x00,0x7f,0xd4,0x7a,0xfe,0x00,0x00]
+# W64: v_cmp_class_f64_e64 s[10:11], ttmp[14:15], exec_hi ; encoding: [0x0a,0x00,0x7f,0xd4,0x7a,0xfe,0x00,0x00]
+0x0a,0x00,0x7f,0xd4,0x7a,0xfe,0x00,0x00
+
+# W32: v_cmp_class_f64_e64 s10, exec, exec_lo    ; encoding: [0x0a,0x00,0x7f,0xd4,0x7e,0xfc,0x00,0x00]
+# W64: v_cmp_class_f64_e64 s[10:11], exec, exec_lo ; encoding: [0x0a,0x00,0x7f,0xd4,0x7e,0xfc,0x00,0x00]
+0x0a,0x00,0x7f,0xd4,0x7e,0xfc,0x00,0x00
+
+# W32: v_cmp_class_f64_e64 s10, null, null       ; encoding: [0x0a,0x00,0x7f,0xd4,0x7c,0xf8,0x00,0x00]
+# W64: v_cmp_class_f64_e64 s[10:11], null, null  ; encoding: [0x0a,0x00,0x7f,0xd4,0x7c,0xf8,0x00,0x00]
+0x0a,0x00,0x7f,0xd4,0x7c,0xf8,0x00,0x00
+
+# W32: v_cmp_class_f64_e64 s104, -1, -1          ; encoding: [0x68,0x00,0x7f,0xd4,0xc1,0x82,0x01,0x00]
+# W64: v_cmp_class_f64_e64 s[104:105], -1, -1    ; encoding: [0x68,0x00,0x7f,0xd4,0xc1,0x82,0x01,0x00]
+0x68,0x00,0x7f,0xd4,0xc1,0x82,0x01,0x00
+
+# W32: v_cmp_class_f64_e64 vcc_lo, 0.5, 0.5      ; encoding: [0x6a,0x00,0x7f,0xd4,0xf0,0xe0,0x01,0x00]
+# W64: v_cmp_class_f64_e64 vcc, 0.5, 0.5         ; encoding: [0x6a,0x00,0x7f,0xd4,0xf0,0xe0,0x01,0x00]
+0x6a,0x00,0x7f,0xd4,0xf0,0xe0,0x01,0x00
+
+# W32: v_cmp_class_f64_e64 ttmp14, -|src_scc|, src_scc ; encoding: [0x7a,0x01,0x7f,0xd4,0xfd,0xfa,0x01,0x20]
+# W64: v_cmp_class_f64_e64 ttmp[14:15], -|src_scc|, src_scc ; encoding: [0x7a,0x01,0x7f,0xd4,0xfd,0xfa,0x01,0x20]
+0x7a,0x01,0x7f,0xd4,0xfd,0xfa,0x01,0x20
+
+# GFX12: v_cmp_class_f64_e64 null, 0xaf123456, 0xaf123456 ; encoding: [0x7c,0x00,0x7f,0xd4,0xff,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x7f,0xd4,0xff,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_eq_f16_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_eq_f16_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_eq_f16_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x02,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_eq_f16_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x02,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x02,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_eq_f16_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x02,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_eq_f16_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x02,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x02,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_eq_f16_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x02,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_eq_f16_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x02,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x02,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_eq_f16_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x02,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_eq_f16_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x02,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x02,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_eq_f16_e64 s10, vcc_hi, 0xfe0b      ; encoding: [0x0a,0x00,0x02,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_eq_f16_e64 s[10:11], vcc_hi, 0xfe0b ; encoding: [0x0a,0x00,0x02,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x0a,0x00,0x02,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_eq_f16_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x02,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_eq_f16_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x02,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x02,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_eq_f16_e64 s10, m0, 0.5             ; encoding: [0x0a,0x00,0x02,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_eq_f16_e64 s[10:11], m0, 0.5        ; encoding: [0x0a,0x00,0x02,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x02,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_eq_f16_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x02,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_eq_f16_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x02,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x02,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_eq_f16_e64 s10, |exec_hi|, null     ; encoding: [0x0a,0x01,0x02,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_eq_f16_e64 s[10:11], |exec_hi|, null ; encoding: [0x0a,0x01,0x02,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x01,0x02,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_eq_f16_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x02,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_eq_f16_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x02,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x02,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_eq_f16_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x02,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_eq_f16_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x02,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x02,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_eq_f16_e64 vcc_lo, 0.5, -m0         ; encoding: [0x6a,0x00,0x02,0xd4,0xf0,0xfa,0x00,0x40]
+# W64: v_cmp_eq_f16_e64 vcc, 0.5, -m0            ; encoding: [0x6a,0x00,0x02,0xd4,0xf0,0xfa,0x00,0x40]
+0x6a,0x00,0x02,0xd4,0xf0,0xfa,0x00,0x40
+
+# W32: v_cmp_eq_f16_e64 ttmp14, -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x02,0xd4,0xfd,0xd4,0x00,0x20]
+# W64: v_cmp_eq_f16_e64 ttmp[14:15], -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x02,0xd4,0xfd,0xd4,0x00,0x20]
+0x7a,0x02,0x02,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmp_eq_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x02,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x7c,0x83,0x02,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_eq_f32_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x12,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_eq_f32_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x12,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x12,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_eq_f32_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x12,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_eq_f32_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x12,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x12,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_eq_f32_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x12,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_eq_f32_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x12,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x12,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_eq_f32_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x12,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_eq_f32_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x12,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x12,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_eq_f32_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x12,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_eq_f32_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x12,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x12,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_eq_f32_e64 s10, vcc_hi, 0xaf123456  ; encoding: [0x0a,0x00,0x12,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_eq_f32_e64 s[10:11], vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x12,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x12,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_eq_f32_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x12,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_eq_f32_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x12,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x12,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_eq_f32_e64 s10, m0, 0.5             ; encoding: [0x0a,0x00,0x12,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_eq_f32_e64 s[10:11], m0, 0.5        ; encoding: [0x0a,0x00,0x12,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x12,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_eq_f32_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x12,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_eq_f32_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x12,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x12,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_eq_f32_e64 s10, |exec_hi|, null     ; encoding: [0x0a,0x01,0x12,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_eq_f32_e64 s[10:11], |exec_hi|, null ; encoding: [0x0a,0x01,0x12,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x01,0x12,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_eq_f32_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x12,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_eq_f32_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x12,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x12,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_eq_f32_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x12,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_eq_f32_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x12,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x12,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_eq_f32_e64 vcc_lo, 0.5, -m0         ; encoding: [0x6a,0x00,0x12,0xd4,0xf0,0xfa,0x00,0x40]
+# W64: v_cmp_eq_f32_e64 vcc, 0.5, -m0            ; encoding: [0x6a,0x00,0x12,0xd4,0xf0,0xfa,0x00,0x40]
+0x6a,0x00,0x12,0xd4,0xf0,0xfa,0x00,0x40
+
+# W32: v_cmp_eq_f32_e64 ttmp14, -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x12,0xd4,0xfd,0xd4,0x00,0x20]
+# W64: v_cmp_eq_f32_e64 ttmp[14:15], -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x12,0xd4,0xfd,0xd4,0x00,0x20]
+0x7a,0x02,0x12,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmp_eq_f32_e64 null, -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x12,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0x7c,0x83,0x12,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_eq_f64_e64 s10, v[1:2], v[2:3]      ; encoding: [0x0a,0x00,0x22,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_eq_f64_e64 s[10:11], v[1:2], v[2:3] ; encoding: [0x0a,0x00,0x22,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x22,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_eq_f64_e64 s10, v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x22,0xd4,0xfe,0xfd,0x03,0x00]
+# W64: v_cmp_eq_f64_e64 s[10:11], v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x22,0xd4,0xfe,0xfd,0x03,0x00]
+0x0a,0x00,0x22,0xd4,0xfe,0xfd,0x03,0x00
+
+# W32: v_cmp_eq_f64_e64 s10, s[2:3], s[4:5]      ; encoding: [0x0a,0x00,0x22,0xd4,0x02,0x08,0x00,0x00]
+# W64: v_cmp_eq_f64_e64 s[10:11], s[2:3], s[4:5] ; encoding: [0x0a,0x00,0x22,0xd4,0x02,0x08,0x00,0x00]
+0x0a,0x00,0x22,0xd4,0x02,0x08,0x00,0x00
+
+# W32: v_cmp_eq_f64_e64 s10, s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x22,0xd4,0x68,0xd0,0x00,0x00]
+# W64: v_cmp_eq_f64_e64 s[10:11], s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x22,0xd4,0x68,0xd0,0x00,0x00]
+0x0a,0x00,0x22,0xd4,0x68,0xd0,0x00,0x00
+
+# W32: v_cmp_eq_f64_e64 s10, vcc, ttmp[14:15]    ; encoding: [0x0a,0x00,0x22,0xd4,0x6a,0xf4,0x00,0x00]
+# W64: v_cmp_eq_f64_e64 s[10:11], vcc, ttmp[14:15] ; encoding: [0x0a,0x00,0x22,0xd4,0x6a,0xf4,0x00,0x00]
+0x0a,0x00,0x22,0xd4,0x6a,0xf4,0x00,0x00
+
+# W32: v_cmp_eq_f64_e64 s10, ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x22,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_eq_f64_e64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x22,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x22,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_eq_f64_e64 s10, -|exec|, src_scc    ; encoding: [0x0a,0x01,0x22,0xd4,0x7e,0xfa,0x01,0x20]
+# W64: v_cmp_eq_f64_e64 s[10:11], -|exec|, src_scc ; encoding: [0x0a,0x01,0x22,0xd4,0x7e,0xfa,0x01,0x20]
+0x0a,0x01,0x22,0xd4,0x7e,0xfa,0x01,0x20
+
+# W32: v_cmp_eq_f64_e64 s10, null, 0.5           ; encoding: [0x0a,0x00,0x22,0xd4,0x7c,0xe0,0x01,0x00]
+# W64: v_cmp_eq_f64_e64 s[10:11], null, 0.5      ; encoding: [0x0a,0x00,0x22,0xd4,0x7c,0xe0,0x01,0x00]
+0x0a,0x00,0x22,0xd4,0x7c,0xe0,0x01,0x00
+
+# W32: v_cmp_eq_f64_e64 s104, -1, -1             ; encoding: [0x68,0x00,0x22,0xd4,0xc1,0x82,0x01,0x00]
+# W64: v_cmp_eq_f64_e64 s[104:105], -1, -1       ; encoding: [0x68,0x00,0x22,0xd4,0xc1,0x82,0x01,0x00]
+0x68,0x00,0x22,0xd4,0xc1,0x82,0x01,0x00
+
+# W32: v_cmp_eq_f64_e64 vcc_lo, 0.5, null        ; encoding: [0x6a,0x00,0x22,0xd4,0xf0,0xf8,0x00,0x00]
+# W64: v_cmp_eq_f64_e64 vcc, 0.5, null           ; encoding: [0x6a,0x00,0x22,0xd4,0xf0,0xf8,0x00,0x00]
+0x6a,0x00,0x22,0xd4,0xf0,0xf8,0x00,0x00
+
+# W32: v_cmp_eq_f64_e64 ttmp14, -|src_scc|, -|exec| ; encoding: [0x7a,0x03,0x22,0xd4,0xfd,0xfc,0x00,0x60]
+# W64: v_cmp_eq_f64_e64 ttmp[14:15], -|src_scc|, -|exec| ; encoding: [0x7a,0x03,0x22,0xd4,0xfd,0xfc,0x00,0x60]
+0x7a,0x03,0x22,0xd4,0xfd,0xfc,0x00,0x60
+
+# GFX12: v_cmp_eq_f64_e64 null, 0xaf123456, -|vcc| clamp ; encoding: [0x7c,0x82,0x22,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+0x7c,0x82,0x22,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_eq_i16_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x32,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_eq_i16_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x32,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x32,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_eq_i16_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x32,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_eq_i16_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x32,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x32,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_eq_i16_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x32,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_eq_i16_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x32,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x32,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_eq_i16_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x32,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_eq_i16_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x32,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x32,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_eq_i16_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x32,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_eq_i16_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x32,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x32,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_eq_i16_e64 s10, vcc_hi, 0xfe0b      ; encoding: [0x0a,0x00,0x32,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_eq_i16_e64 s[10:11], vcc_hi, 0xfe0b ; encoding: [0x0a,0x00,0x32,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x0a,0x00,0x32,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_eq_i16_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x32,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_eq_i16_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x32,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x32,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_eq_i16_e64 s10, m0, 0x3800          ; encoding: [0x0a,0x00,0x32,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+# W64: v_cmp_eq_i16_e64 s[10:11], m0, 0x3800     ; encoding: [0x0a,0x00,0x32,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+0x0a,0x00,0x32,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_eq_i16_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x32,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_eq_i16_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x32,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x32,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_eq_i16_e64 s10, exec_hi, null       ; encoding: [0x0a,0x00,0x32,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_eq_i16_e64 s[10:11], exec_hi, null  ; encoding: [0x0a,0x00,0x32,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x00,0x32,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_eq_i16_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x32,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_eq_i16_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x32,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x32,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_eq_i16_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x32,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_eq_i16_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x32,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x32,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_eq_i16_e64 vcc_lo, 0x3800, m0       ; encoding: [0x6a,0x00,0x32,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+# W64: v_cmp_eq_i16_e64 vcc, 0x3800, m0          ; encoding: [0x6a,0x00,0x32,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+0x6a,0x00,0x32,0xd4,0xf0,0xfa,0x00,0x00
+
+# W32: v_cmp_eq_i16_e64 ttmp14, src_scc, vcc_lo  ; encoding: [0x7a,0x00,0x32,0xd4,0xfd,0xd4,0x00,0x00]
+# W64: v_cmp_eq_i16_e64 ttmp[14:15], src_scc, vcc_lo ; encoding: [0x7a,0x00,0x32,0xd4,0xfd,0xd4,0x00,0x00]
+0x7a,0x00,0x32,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmp_eq_i16_e64 null, 0xfe0b, vcc_hi   ; encoding: [0x7c,0x00,0x32,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0x7c,0x00,0x32,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_eq_i32_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x42,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_eq_i32_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x42,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x42,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_eq_i32_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x42,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_eq_i32_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x42,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x42,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_eq_i32_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x42,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_eq_i32_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x42,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x42,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_eq_i32_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x42,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_eq_i32_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x42,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x42,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_eq_i32_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x42,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_eq_i32_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x42,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x42,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_eq_i32_e64 s10, vcc_hi, 0xaf123456  ; encoding: [0x0a,0x00,0x42,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_eq_i32_e64 s[10:11], vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x42,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x42,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_eq_i32_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x42,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_eq_i32_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x42,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x42,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_eq_i32_e64 s10, m0, 0.5             ; encoding: [0x0a,0x00,0x42,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_eq_i32_e64 s[10:11], m0, 0.5        ; encoding: [0x0a,0x00,0x42,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x42,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_eq_i32_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x42,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_eq_i32_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x42,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x42,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_eq_i32_e64 s10, exec_hi, null       ; encoding: [0x0a,0x00,0x42,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_eq_i32_e64 s[10:11], exec_hi, null  ; encoding: [0x0a,0x00,0x42,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x00,0x42,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_eq_i32_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x42,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_eq_i32_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x42,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x42,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_eq_i32_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x42,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_eq_i32_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x42,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x42,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_eq_i32_e64 vcc_lo, 0.5, m0          ; encoding: [0x6a,0x00,0x42,0xd4,0xf0,0xfa,0x00,0x00]
+# W64: v_cmp_eq_i32_e64 vcc, 0.5, m0             ; encoding: [0x6a,0x00,0x42,0xd4,0xf0,0xfa,0x00,0x00]
+0x6a,0x00,0x42,0xd4,0xf0,0xfa,0x00,0x00
+
+# W32: v_cmp_eq_i32_e64 ttmp14, src_scc, vcc_lo  ; encoding: [0x7a,0x00,0x42,0xd4,0xfd,0xd4,0x00,0x00]
+# W64: v_cmp_eq_i32_e64 ttmp[14:15], src_scc, vcc_lo ; encoding: [0x7a,0x00,0x42,0xd4,0xfd,0xd4,0x00,0x00]
+0x7a,0x00,0x42,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmp_eq_i32_e64 null, 0xaf123456, vcc_hi ; encoding: [0x7c,0x00,0x42,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x42,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_eq_i64_e64 s10, v[1:2], v[2:3]      ; encoding: [0x0a,0x00,0x52,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_eq_i64_e64 s[10:11], v[1:2], v[2:3] ; encoding: [0x0a,0x00,0x52,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x52,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_eq_i64_e64 s10, v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x52,0xd4,0xfe,0xfd,0x03,0x00]
+# W64: v_cmp_eq_i64_e64 s[10:11], v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x52,0xd4,0xfe,0xfd,0x03,0x00]
+0x0a,0x00,0x52,0xd4,0xfe,0xfd,0x03,0x00
+
+# W32: v_cmp_eq_i64_e64 s10, s[2:3], s[4:5]      ; encoding: [0x0a,0x00,0x52,0xd4,0x02,0x08,0x00,0x00]
+# W64: v_cmp_eq_i64_e64 s[10:11], s[2:3], s[4:5] ; encoding: [0x0a,0x00,0x52,0xd4,0x02,0x08,0x00,0x00]
+0x0a,0x00,0x52,0xd4,0x02,0x08,0x00,0x00
+
+# W32: v_cmp_eq_i64_e64 s10, s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x52,0xd4,0x68,0xd0,0x00,0x00]
+# W64: v_cmp_eq_i64_e64 s[10:11], s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x52,0xd4,0x68,0xd0,0x00,0x00]
+0x0a,0x00,0x52,0xd4,0x68,0xd0,0x00,0x00
+
+# W32: v_cmp_eq_i64_e64 s10, vcc, ttmp[14:15]    ; encoding: [0x0a,0x00,0x52,0xd4,0x6a,0xf4,0x00,0x00]
+# W64: v_cmp_eq_i64_e64 s[10:11], vcc, ttmp[14:15] ; encoding: [0x0a,0x00,0x52,0xd4,0x6a,0xf4,0x00,0x00]
+0x0a,0x00,0x52,0xd4,0x6a,0xf4,0x00,0x00
+
+# W32: v_cmp_eq_i64_e64 s10, ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x52,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_eq_i64_e64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x52,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x52,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_eq_i64_e64 s10, exec, src_scc       ; encoding: [0x0a,0x00,0x52,0xd4,0x7e,0xfa,0x01,0x00]
+# W64: v_cmp_eq_i64_e64 s[10:11], exec, src_scc  ; encoding: [0x0a,0x00,0x52,0xd4,0x7e,0xfa,0x01,0x00]
+0x0a,0x00,0x52,0xd4,0x7e,0xfa,0x01,0x00
+
+# W32: v_cmp_eq_i64_e64 s10, null, 0.5           ; encoding: [0x0a,0x00,0x52,0xd4,0x7c,0xe0,0x01,0x00]
+# W64: v_cmp_eq_i64_e64 s[10:11], null, 0.5      ; encoding: [0x0a,0x00,0x52,0xd4,0x7c,0xe0,0x01,0x00]
+0x0a,0x00,0x52,0xd4,0x7c,0xe0,0x01,0x00
+
+# W32: v_cmp_eq_i64_e64 s104, -1, -1             ; encoding: [0x68,0x00,0x52,0xd4,0xc1,0x82,0x01,0x00]
+# W64: v_cmp_eq_i64_e64 s[104:105], -1, -1       ; encoding: [0x68,0x00,0x52,0xd4,0xc1,0x82,0x01,0x00]
+0x68,0x00,0x52,0xd4,0xc1,0x82,0x01,0x00
+
+# W32: v_cmp_eq_i64_e64 vcc_lo, 0.5, null        ; encoding: [0x6a,0x00,0x52,0xd4,0xf0,0xf8,0x00,0x00]
+# W64: v_cmp_eq_i64_e64 vcc, 0.5, null           ; encoding: [0x6a,0x00,0x52,0xd4,0xf0,0xf8,0x00,0x00]
+0x6a,0x00,0x52,0xd4,0xf0,0xf8,0x00,0x00
+
+# W32: v_cmp_eq_i64_e64 ttmp14, src_scc, exec    ; encoding: [0x7a,0x00,0x52,0xd4,0xfd,0xfc,0x00,0x00]
+# W64: v_cmp_eq_i64_e64 ttmp[14:15], src_scc, exec ; encoding: [0x7a,0x00,0x52,0xd4,0xfd,0xfc,0x00,0x00]
+0x7a,0x00,0x52,0xd4,0xfd,0xfc,0x00,0x00
+
+# GFX12: v_cmp_eq_i64_e64 null, 0xaf123456, vcc  ; encoding: [0x7c,0x00,0x52,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x52,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_eq_u16_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x3a,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_eq_u16_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x3a,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x3a,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_eq_u16_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x3a,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_eq_u16_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x3a,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x3a,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_eq_u16_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x3a,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_eq_u16_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x3a,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x3a,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_eq_u16_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x3a,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_eq_u16_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x3a,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x3a,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_eq_u16_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x3a,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_eq_u16_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x3a,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x3a,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_eq_u16_e64 s10, vcc_hi, 0xfe0b      ; encoding: [0x0a,0x00,0x3a,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_eq_u16_e64 s[10:11], vcc_hi, 0xfe0b ; encoding: [0x0a,0x00,0x3a,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x0a,0x00,0x3a,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_eq_u16_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x3a,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_eq_u16_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x3a,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x3a,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_eq_u16_e64 s10, m0, 0x3800          ; encoding: [0x0a,0x00,0x3a,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+# W64: v_cmp_eq_u16_e64 s[10:11], m0, 0x3800     ; encoding: [0x0a,0x00,0x3a,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+0x0a,0x00,0x3a,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_eq_u16_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x3a,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_eq_u16_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x3a,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x3a,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_eq_u16_e64 s10, exec_hi, null       ; encoding: [0x0a,0x00,0x3a,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_eq_u16_e64 s[10:11], exec_hi, null  ; encoding: [0x0a,0x00,0x3a,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x00,0x3a,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_eq_u16_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x3a,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_eq_u16_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x3a,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x3a,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_eq_u16_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x3a,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_eq_u16_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x3a,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x3a,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_eq_u16_e64 vcc_lo, 0x3800, m0       ; encoding: [0x6a,0x00,0x3a,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+# W64: v_cmp_eq_u16_e64 vcc, 0x3800, m0          ; encoding: [0x6a,0x00,0x3a,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+0x6a,0x00,0x3a,0xd4,0xf0,0xfa,0x00,0x00
+
+# W32: v_cmp_eq_u16_e64 ttmp14, src_scc, vcc_lo  ; encoding: [0x7a,0x00,0x3a,0xd4,0xfd,0xd4,0x00,0x00]
+# W64: v_cmp_eq_u16_e64 ttmp[14:15], src_scc, vcc_lo ; encoding: [0x7a,0x00,0x3a,0xd4,0xfd,0xd4,0x00,0x00]
+0x7a,0x00,0x3a,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmp_eq_u16_e64 null, 0xfe0b, vcc_hi   ; encoding: [0x7c,0x00,0x3a,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0x7c,0x00,0x3a,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_eq_u32_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x4a,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_eq_u32_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x4a,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x4a,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_eq_u32_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x4a,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_eq_u32_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x4a,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x4a,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_eq_u32_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x4a,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_eq_u32_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x4a,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x4a,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_eq_u32_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x4a,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_eq_u32_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x4a,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x4a,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_eq_u32_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x4a,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_eq_u32_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x4a,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x4a,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_eq_u32_e64 s10, vcc_hi, 0xaf123456  ; encoding: [0x0a,0x00,0x4a,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_eq_u32_e64 s[10:11], vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x4a,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x4a,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_eq_u32_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x4a,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_eq_u32_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x4a,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x4a,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_eq_u32_e64 s10, m0, 0.5             ; encoding: [0x0a,0x00,0x4a,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_eq_u32_e64 s[10:11], m0, 0.5        ; encoding: [0x0a,0x00,0x4a,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x4a,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_eq_u32_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x4a,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_eq_u32_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x4a,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x4a,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_eq_u32_e64 s10, exec_hi, null       ; encoding: [0x0a,0x00,0x4a,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_eq_u32_e64 s[10:11], exec_hi, null  ; encoding: [0x0a,0x00,0x4a,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x00,0x4a,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_eq_u32_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x4a,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_eq_u32_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x4a,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x4a,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_eq_u32_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x4a,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_eq_u32_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x4a,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x4a,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_eq_u32_e64 vcc_lo, 0.5, m0          ; encoding: [0x6a,0x00,0x4a,0xd4,0xf0,0xfa,0x00,0x00]
+# W64: v_cmp_eq_u32_e64 vcc, 0.5, m0             ; encoding: [0x6a,0x00,0x4a,0xd4,0xf0,0xfa,0x00,0x00]
+0x6a,0x00,0x4a,0xd4,0xf0,0xfa,0x00,0x00
+
+# W32: v_cmp_eq_u32_e64 ttmp14, src_scc, vcc_lo  ; encoding: [0x7a,0x00,0x4a,0xd4,0xfd,0xd4,0x00,0x00]
+# W64: v_cmp_eq_u32_e64 ttmp[14:15], src_scc, vcc_lo ; encoding: [0x7a,0x00,0x4a,0xd4,0xfd,0xd4,0x00,0x00]
+0x7a,0x00,0x4a,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmp_eq_u32_e64 null, 0xaf123456, vcc_hi ; encoding: [0x7c,0x00,0x4a,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x4a,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_eq_u64_e64 s10, v[1:2], v[2:3]      ; encoding: [0x0a,0x00,0x5a,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_eq_u64_e64 s[10:11], v[1:2], v[2:3] ; encoding: [0x0a,0x00,0x5a,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x5a,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_eq_u64_e64 s10, v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x5a,0xd4,0xfe,0xfd,0x03,0x00]
+# W64: v_cmp_eq_u64_e64 s[10:11], v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x5a,0xd4,0xfe,0xfd,0x03,0x00]
+0x0a,0x00,0x5a,0xd4,0xfe,0xfd,0x03,0x00
+
+# W32: v_cmp_eq_u64_e64 s10, s[2:3], s[4:5]      ; encoding: [0x0a,0x00,0x5a,0xd4,0x02,0x08,0x00,0x00]
+# W64: v_cmp_eq_u64_e64 s[10:11], s[2:3], s[4:5] ; encoding: [0x0a,0x00,0x5a,0xd4,0x02,0x08,0x00,0x00]
+0x0a,0x00,0x5a,0xd4,0x02,0x08,0x00,0x00
+
+# W32: v_cmp_eq_u64_e64 s10, s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x5a,0xd4,0x68,0xd0,0x00,0x00]
+# W64: v_cmp_eq_u64_e64 s[10:11], s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x5a,0xd4,0x68,0xd0,0x00,0x00]
+0x0a,0x00,0x5a,0xd4,0x68,0xd0,0x00,0x00
+
+# W32: v_cmp_eq_u64_e64 s10, vcc, ttmp[14:15]    ; encoding: [0x0a,0x00,0x5a,0xd4,0x6a,0xf4,0x00,0x00]
+# W64: v_cmp_eq_u64_e64 s[10:11], vcc, ttmp[14:15] ; encoding: [0x0a,0x00,0x5a,0xd4,0x6a,0xf4,0x00,0x00]
+0x0a,0x00,0x5a,0xd4,0x6a,0xf4,0x00,0x00
+
+# W32: v_cmp_eq_u64_e64 s10, ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x5a,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_eq_u64_e64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x5a,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x5a,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_eq_u64_e64 s10, exec, src_scc       ; encoding: [0x0a,0x00,0x5a,0xd4,0x7e,0xfa,0x01,0x00]
+# W64: v_cmp_eq_u64_e64 s[10:11], exec, src_scc  ; encoding: [0x0a,0x00,0x5a,0xd4,0x7e,0xfa,0x01,0x00]
+0x0a,0x00,0x5a,0xd4,0x7e,0xfa,0x01,0x00
+
+# W32: v_cmp_eq_u64_e64 s10, null, 0.5           ; encoding: [0x0a,0x00,0x5a,0xd4,0x7c,0xe0,0x01,0x00]
+# W64: v_cmp_eq_u64_e64 s[10:11], null, 0.5      ; encoding: [0x0a,0x00,0x5a,0xd4,0x7c,0xe0,0x01,0x00]
+0x0a,0x00,0x5a,0xd4,0x7c,0xe0,0x01,0x00
+
+# W32: v_cmp_eq_u64_e64 s104, -1, -1             ; encoding: [0x68,0x00,0x5a,0xd4,0xc1,0x82,0x01,0x00]
+# W64: v_cmp_eq_u64_e64 s[104:105], -1, -1       ; encoding: [0x68,0x00,0x5a,0xd4,0xc1,0x82,0x01,0x00]
+0x68,0x00,0x5a,0xd4,0xc1,0x82,0x01,0x00
+
+# W32: v_cmp_eq_u64_e64 vcc_lo, 0.5, null        ; encoding: [0x6a,0x00,0x5a,0xd4,0xf0,0xf8,0x00,0x00]
+# W64: v_cmp_eq_u64_e64 vcc, 0.5, null           ; encoding: [0x6a,0x00,0x5a,0xd4,0xf0,0xf8,0x00,0x00]
+0x6a,0x00,0x5a,0xd4,0xf0,0xf8,0x00,0x00
+
+# W32: v_cmp_eq_u64_e64 ttmp14, src_scc, exec    ; encoding: [0x7a,0x00,0x5a,0xd4,0xfd,0xfc,0x00,0x00]
+# W64: v_cmp_eq_u64_e64 ttmp[14:15], src_scc, exec ; encoding: [0x7a,0x00,0x5a,0xd4,0xfd,0xfc,0x00,0x00]
+0x7a,0x00,0x5a,0xd4,0xfd,0xfc,0x00,0x00
+
+# GFX12: v_cmp_eq_u64_e64 null, 0xaf123456, vcc  ; encoding: [0x7c,0x00,0x5a,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x5a,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ge_f16_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x06,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_ge_f16_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x06,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x06,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_ge_f16_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x06,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_ge_f16_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x06,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x06,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_ge_f16_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x06,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_ge_f16_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x06,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x06,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_ge_f16_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x06,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_ge_f16_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x06,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x06,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_ge_f16_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x06,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_ge_f16_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x06,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x06,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_ge_f16_e64 s10, vcc_hi, 0xfe0b      ; encoding: [0x0a,0x00,0x06,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_ge_f16_e64 s[10:11], vcc_hi, 0xfe0b ; encoding: [0x0a,0x00,0x06,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x0a,0x00,0x06,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_ge_f16_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x06,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_ge_f16_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x06,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x06,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_ge_f16_e64 s10, m0, 0.5             ; encoding: [0x0a,0x00,0x06,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_ge_f16_e64 s[10:11], m0, 0.5        ; encoding: [0x0a,0x00,0x06,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x06,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_ge_f16_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x06,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_ge_f16_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x06,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x06,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_ge_f16_e64 s10, |exec_hi|, null     ; encoding: [0x0a,0x01,0x06,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_ge_f16_e64 s[10:11], |exec_hi|, null ; encoding: [0x0a,0x01,0x06,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x01,0x06,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_ge_f16_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x06,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_ge_f16_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x06,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x06,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_ge_f16_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x06,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_ge_f16_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x06,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x06,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_ge_f16_e64 vcc_lo, 0.5, -m0         ; encoding: [0x6a,0x00,0x06,0xd4,0xf0,0xfa,0x00,0x40]
+# W64: v_cmp_ge_f16_e64 vcc, 0.5, -m0            ; encoding: [0x6a,0x00,0x06,0xd4,0xf0,0xfa,0x00,0x40]
+0x6a,0x00,0x06,0xd4,0xf0,0xfa,0x00,0x40
+
+# W32: v_cmp_ge_f16_e64 ttmp14, -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x06,0xd4,0xfd,0xd4,0x00,0x20]
+# W64: v_cmp_ge_f16_e64 ttmp[14:15], -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x06,0xd4,0xfd,0xd4,0x00,0x20]
+0x7a,0x02,0x06,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmp_ge_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x06,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x7c,0x83,0x06,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_ge_f32_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x16,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_ge_f32_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x16,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x16,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_ge_f32_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x16,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_ge_f32_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x16,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x16,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_ge_f32_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x16,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_ge_f32_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x16,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x16,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_ge_f32_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x16,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_ge_f32_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x16,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x16,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_ge_f32_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x16,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_ge_f32_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x16,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x16,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_ge_f32_e64 s10, vcc_hi, 0xaf123456  ; encoding: [0x0a,0x00,0x16,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_ge_f32_e64 s[10:11], vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x16,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x16,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ge_f32_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x16,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_ge_f32_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x16,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x16,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_ge_f32_e64 s10, m0, 0.5             ; encoding: [0x0a,0x00,0x16,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_ge_f32_e64 s[10:11], m0, 0.5        ; encoding: [0x0a,0x00,0x16,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x16,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_ge_f32_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x16,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_ge_f32_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x16,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x16,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_ge_f32_e64 s10, |exec_hi|, null     ; encoding: [0x0a,0x01,0x16,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_ge_f32_e64 s[10:11], |exec_hi|, null ; encoding: [0x0a,0x01,0x16,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x01,0x16,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_ge_f32_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x16,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_ge_f32_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x16,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x16,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_ge_f32_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x16,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_ge_f32_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x16,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x16,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_ge_f32_e64 vcc_lo, 0.5, -m0         ; encoding: [0x6a,0x00,0x16,0xd4,0xf0,0xfa,0x00,0x40]
+# W64: v_cmp_ge_f32_e64 vcc, 0.5, -m0            ; encoding: [0x6a,0x00,0x16,0xd4,0xf0,0xfa,0x00,0x40]
+0x6a,0x00,0x16,0xd4,0xf0,0xfa,0x00,0x40
+
+# W32: v_cmp_ge_f32_e64 ttmp14, -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x16,0xd4,0xfd,0xd4,0x00,0x20]
+# W64: v_cmp_ge_f32_e64 ttmp[14:15], -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x16,0xd4,0xfd,0xd4,0x00,0x20]
+0x7a,0x02,0x16,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmp_ge_f32_e64 null, -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x16,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0x7c,0x83,0x16,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ge_f64_e64 s10, v[1:2], v[2:3]      ; encoding: [0x0a,0x00,0x26,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_ge_f64_e64 s[10:11], v[1:2], v[2:3] ; encoding: [0x0a,0x00,0x26,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x26,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_ge_f64_e64 s10, v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x26,0xd4,0xfe,0xfd,0x03,0x00]
+# W64: v_cmp_ge_f64_e64 s[10:11], v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x26,0xd4,0xfe,0xfd,0x03,0x00]
+0x0a,0x00,0x26,0xd4,0xfe,0xfd,0x03,0x00
+
+# W32: v_cmp_ge_f64_e64 s10, s[2:3], s[4:5]      ; encoding: [0x0a,0x00,0x26,0xd4,0x02,0x08,0x00,0x00]
+# W64: v_cmp_ge_f64_e64 s[10:11], s[2:3], s[4:5] ; encoding: [0x0a,0x00,0x26,0xd4,0x02,0x08,0x00,0x00]
+0x0a,0x00,0x26,0xd4,0x02,0x08,0x00,0x00
+
+# W32: v_cmp_ge_f64_e64 s10, s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x26,0xd4,0x68,0xd0,0x00,0x00]
+# W64: v_cmp_ge_f64_e64 s[10:11], s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x26,0xd4,0x68,0xd0,0x00,0x00]
+0x0a,0x00,0x26,0xd4,0x68,0xd0,0x00,0x00
+
+# W32: v_cmp_ge_f64_e64 s10, vcc, ttmp[14:15]    ; encoding: [0x0a,0x00,0x26,0xd4,0x6a,0xf4,0x00,0x00]
+# W64: v_cmp_ge_f64_e64 s[10:11], vcc, ttmp[14:15] ; encoding: [0x0a,0x00,0x26,0xd4,0x6a,0xf4,0x00,0x00]
+0x0a,0x00,0x26,0xd4,0x6a,0xf4,0x00,0x00
+
+# W32: v_cmp_ge_f64_e64 s10, ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x26,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_ge_f64_e64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x26,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x26,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ge_f64_e64 s10, -|exec|, src_scc    ; encoding: [0x0a,0x01,0x26,0xd4,0x7e,0xfa,0x01,0x20]
+# W64: v_cmp_ge_f64_e64 s[10:11], -|exec|, src_scc ; encoding: [0x0a,0x01,0x26,0xd4,0x7e,0xfa,0x01,0x20]
+0x0a,0x01,0x26,0xd4,0x7e,0xfa,0x01,0x20
+
+# W32: v_cmp_ge_f64_e64 s10, null, 0.5           ; encoding: [0x0a,0x00,0x26,0xd4,0x7c,0xe0,0x01,0x00]
+# W64: v_cmp_ge_f64_e64 s[10:11], null, 0.5      ; encoding: [0x0a,0x00,0x26,0xd4,0x7c,0xe0,0x01,0x00]
+0x0a,0x00,0x26,0xd4,0x7c,0xe0,0x01,0x00
+
+# W32: v_cmp_ge_f64_e64 s104, -1, -1             ; encoding: [0x68,0x00,0x26,0xd4,0xc1,0x82,0x01,0x00]
+# W64: v_cmp_ge_f64_e64 s[104:105], -1, -1       ; encoding: [0x68,0x00,0x26,0xd4,0xc1,0x82,0x01,0x00]
+0x68,0x00,0x26,0xd4,0xc1,0x82,0x01,0x00
+
+# W32: v_cmp_ge_f64_e64 vcc_lo, 0.5, null        ; encoding: [0x6a,0x00,0x26,0xd4,0xf0,0xf8,0x00,0x00]
+# W64: v_cmp_ge_f64_e64 vcc, 0.5, null           ; encoding: [0x6a,0x00,0x26,0xd4,0xf0,0xf8,0x00,0x00]
+0x6a,0x00,0x26,0xd4,0xf0,0xf8,0x00,0x00
+
+# W32: v_cmp_ge_f64_e64 ttmp14, -|src_scc|, -|exec| ; encoding: [0x7a,0x03,0x26,0xd4,0xfd,0xfc,0x00,0x60]
+# W64: v_cmp_ge_f64_e64 ttmp[14:15], -|src_scc|, -|exec| ; encoding: [0x7a,0x03,0x26,0xd4,0xfd,0xfc,0x00,0x60]
+0x7a,0x03,0x26,0xd4,0xfd,0xfc,0x00,0x60
+
+# GFX12: v_cmp_ge_f64_e64 null, 0xaf123456, -|vcc| clamp ; encoding: [0x7c,0x82,0x26,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+0x7c,0x82,0x26,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ge_i16_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x36,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_ge_i16_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x36,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x36,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_ge_i16_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x36,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_ge_i16_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x36,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x36,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_ge_i16_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x36,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_ge_i16_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x36,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x36,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_ge_i16_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x36,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_ge_i16_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x36,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x36,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_ge_i16_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x36,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_ge_i16_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x36,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x36,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_ge_i16_e64 s10, vcc_hi, 0xfe0b      ; encoding: [0x0a,0x00,0x36,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_ge_i16_e64 s[10:11], vcc_hi, 0xfe0b ; encoding: [0x0a,0x00,0x36,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x0a,0x00,0x36,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_ge_i16_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x36,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_ge_i16_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x36,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x36,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_ge_i16_e64 s10, m0, 0x3800          ; encoding: [0x0a,0x00,0x36,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+# W64: v_cmp_ge_i16_e64 s[10:11], m0, 0x3800     ; encoding: [0x0a,0x00,0x36,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+0x0a,0x00,0x36,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_ge_i16_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x36,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_ge_i16_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x36,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x36,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_ge_i16_e64 s10, exec_hi, null       ; encoding: [0x0a,0x00,0x36,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_ge_i16_e64 s[10:11], exec_hi, null  ; encoding: [0x0a,0x00,0x36,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x00,0x36,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_ge_i16_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x36,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_ge_i16_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x36,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x36,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_ge_i16_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x36,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_ge_i16_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x36,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x36,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_ge_i16_e64 vcc_lo, 0x3800, m0       ; encoding: [0x6a,0x00,0x36,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+# W64: v_cmp_ge_i16_e64 vcc, 0x3800, m0          ; encoding: [0x6a,0x00,0x36,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+0x6a,0x00,0x36,0xd4,0xf0,0xfa,0x00,0x00
+
+# W32: v_cmp_ge_i16_e64 ttmp14, src_scc, vcc_lo  ; encoding: [0x7a,0x00,0x36,0xd4,0xfd,0xd4,0x00,0x00]
+# W64: v_cmp_ge_i16_e64 ttmp[14:15], src_scc, vcc_lo ; encoding: [0x7a,0x00,0x36,0xd4,0xfd,0xd4,0x00,0x00]
+0x7a,0x00,0x36,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmp_ge_i16_e64 null, 0xfe0b, vcc_hi   ; encoding: [0x7c,0x00,0x36,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0x7c,0x00,0x36,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_ge_i32_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x46,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_ge_i32_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x46,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x46,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_ge_i32_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x46,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_ge_i32_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x46,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x46,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_ge_i32_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x46,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_ge_i32_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x46,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x46,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_ge_i32_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x46,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_ge_i32_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x46,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x46,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_ge_i32_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x46,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_ge_i32_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x46,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x46,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_ge_i32_e64 s10, vcc_hi, 0xaf123456  ; encoding: [0x0a,0x00,0x46,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_ge_i32_e64 s[10:11], vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x46,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x46,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ge_i32_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x46,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_ge_i32_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x46,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x46,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_ge_i32_e64 s10, m0, 0.5             ; encoding: [0x0a,0x00,0x46,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_ge_i32_e64 s[10:11], m0, 0.5        ; encoding: [0x0a,0x00,0x46,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x46,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_ge_i32_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x46,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_ge_i32_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x46,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x46,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_ge_i32_e64 s10, exec_hi, null       ; encoding: [0x0a,0x00,0x46,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_ge_i32_e64 s[10:11], exec_hi, null  ; encoding: [0x0a,0x00,0x46,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x00,0x46,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_ge_i32_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x46,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_ge_i32_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x46,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x46,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_ge_i32_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x46,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_ge_i32_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x46,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x46,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_ge_i32_e64 vcc_lo, 0.5, m0          ; encoding: [0x6a,0x00,0x46,0xd4,0xf0,0xfa,0x00,0x00]
+# W64: v_cmp_ge_i32_e64 vcc, 0.5, m0             ; encoding: [0x6a,0x00,0x46,0xd4,0xf0,0xfa,0x00,0x00]
+0x6a,0x00,0x46,0xd4,0xf0,0xfa,0x00,0x00
+
+# W32: v_cmp_ge_i32_e64 ttmp14, src_scc, vcc_lo  ; encoding: [0x7a,0x00,0x46,0xd4,0xfd,0xd4,0x00,0x00]
+# W64: v_cmp_ge_i32_e64 ttmp[14:15], src_scc, vcc_lo ; encoding: [0x7a,0x00,0x46,0xd4,0xfd,0xd4,0x00,0x00]
+0x7a,0x00,0x46,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmp_ge_i32_e64 null, 0xaf123456, vcc_hi ; encoding: [0x7c,0x00,0x46,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x46,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ge_i64_e64 s10, v[1:2], v[2:3]      ; encoding: [0x0a,0x00,0x56,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_ge_i64_e64 s[10:11], v[1:2], v[2:3] ; encoding: [0x0a,0x00,0x56,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x56,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_ge_i64_e64 s10, v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x56,0xd4,0xfe,0xfd,0x03,0x00]
+# W64: v_cmp_ge_i64_e64 s[10:11], v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x56,0xd4,0xfe,0xfd,0x03,0x00]
+0x0a,0x00,0x56,0xd4,0xfe,0xfd,0x03,0x00
+
+# W32: v_cmp_ge_i64_e64 s10, s[2:3], s[4:5]      ; encoding: [0x0a,0x00,0x56,0xd4,0x02,0x08,0x00,0x00]
+# W64: v_cmp_ge_i64_e64 s[10:11], s[2:3], s[4:5] ; encoding: [0x0a,0x00,0x56,0xd4,0x02,0x08,0x00,0x00]
+0x0a,0x00,0x56,0xd4,0x02,0x08,0x00,0x00
+
+# W32: v_cmp_ge_i64_e64 s10, s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x56,0xd4,0x68,0xd0,0x00,0x00]
+# W64: v_cmp_ge_i64_e64 s[10:11], s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x56,0xd4,0x68,0xd0,0x00,0x00]
+0x0a,0x00,0x56,0xd4,0x68,0xd0,0x00,0x00
+
+# W32: v_cmp_ge_i64_e64 s10, vcc, ttmp[14:15]    ; encoding: [0x0a,0x00,0x56,0xd4,0x6a,0xf4,0x00,0x00]
+# W64: v_cmp_ge_i64_e64 s[10:11], vcc, ttmp[14:15] ; encoding: [0x0a,0x00,0x56,0xd4,0x6a,0xf4,0x00,0x00]
+0x0a,0x00,0x56,0xd4,0x6a,0xf4,0x00,0x00
+
+# W32: v_cmp_ge_i64_e64 s10, ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x56,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_ge_i64_e64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x56,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x56,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ge_i64_e64 s10, exec, src_scc       ; encoding: [0x0a,0x00,0x56,0xd4,0x7e,0xfa,0x01,0x00]
+# W64: v_cmp_ge_i64_e64 s[10:11], exec, src_scc  ; encoding: [0x0a,0x00,0x56,0xd4,0x7e,0xfa,0x01,0x00]
+0x0a,0x00,0x56,0xd4,0x7e,0xfa,0x01,0x00
+
+# W32: v_cmp_ge_i64_e64 s10, null, 0.5           ; encoding: [0x0a,0x00,0x56,0xd4,0x7c,0xe0,0x01,0x00]
+# W64: v_cmp_ge_i64_e64 s[10:11], null, 0.5      ; encoding: [0x0a,0x00,0x56,0xd4,0x7c,0xe0,0x01,0x00]
+0x0a,0x00,0x56,0xd4,0x7c,0xe0,0x01,0x00
+
+# W32: v_cmp_ge_i64_e64 s104, -1, -1             ; encoding: [0x68,0x00,0x56,0xd4,0xc1,0x82,0x01,0x00]
+# W64: v_cmp_ge_i64_e64 s[104:105], -1, -1       ; encoding: [0x68,0x00,0x56,0xd4,0xc1,0x82,0x01,0x00]
+0x68,0x00,0x56,0xd4,0xc1,0x82,0x01,0x00
+
+# W32: v_cmp_ge_i64_e64 vcc_lo, 0.5, null        ; encoding: [0x6a,0x00,0x56,0xd4,0xf0,0xf8,0x00,0x00]
+# W64: v_cmp_ge_i64_e64 vcc, 0.5, null           ; encoding: [0x6a,0x00,0x56,0xd4,0xf0,0xf8,0x00,0x00]
+0x6a,0x00,0x56,0xd4,0xf0,0xf8,0x00,0x00
+
+# W32: v_cmp_ge_i64_e64 ttmp14, src_scc, exec    ; encoding: [0x7a,0x00,0x56,0xd4,0xfd,0xfc,0x00,0x00]
+# W64: v_cmp_ge_i64_e64 ttmp[14:15], src_scc, exec ; encoding: [0x7a,0x00,0x56,0xd4,0xfd,0xfc,0x00,0x00]
+0x7a,0x00,0x56,0xd4,0xfd,0xfc,0x00,0x00
+
+# GFX12: v_cmp_ge_i64_e64 null, 0xaf123456, vcc  ; encoding: [0x7c,0x00,0x56,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x56,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ge_u16_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x3e,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_ge_u16_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x3e,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x3e,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_ge_u16_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x3e,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_ge_u16_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x3e,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x3e,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_ge_u16_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x3e,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_ge_u16_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x3e,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x3e,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_ge_u16_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x3e,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_ge_u16_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x3e,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x3e,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_ge_u16_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x3e,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_ge_u16_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x3e,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x3e,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_ge_u16_e64 s10, vcc_hi, 0xfe0b      ; encoding: [0x0a,0x00,0x3e,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_ge_u16_e64 s[10:11], vcc_hi, 0xfe0b ; encoding: [0x0a,0x00,0x3e,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x0a,0x00,0x3e,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_ge_u16_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x3e,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_ge_u16_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x3e,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x3e,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_ge_u16_e64 s10, m0, 0x3800          ; encoding: [0x0a,0x00,0x3e,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+# W64: v_cmp_ge_u16_e64 s[10:11], m0, 0x3800     ; encoding: [0x0a,0x00,0x3e,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+0x0a,0x00,0x3e,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_ge_u16_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x3e,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_ge_u16_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x3e,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x3e,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_ge_u16_e64 s10, exec_hi, null       ; encoding: [0x0a,0x00,0x3e,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_ge_u16_e64 s[10:11], exec_hi, null  ; encoding: [0x0a,0x00,0x3e,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x00,0x3e,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_ge_u16_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x3e,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_ge_u16_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x3e,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x3e,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_ge_u16_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x3e,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_ge_u16_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x3e,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x3e,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_ge_u16_e64 vcc_lo, 0x3800, m0       ; encoding: [0x6a,0x00,0x3e,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+# W64: v_cmp_ge_u16_e64 vcc, 0x3800, m0          ; encoding: [0x6a,0x00,0x3e,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+0x6a,0x00,0x3e,0xd4,0xf0,0xfa,0x00,0x00
+
+# W32: v_cmp_ge_u16_e64 ttmp14, src_scc, vcc_lo  ; encoding: [0x7a,0x00,0x3e,0xd4,0xfd,0xd4,0x00,0x00]
+# W64: v_cmp_ge_u16_e64 ttmp[14:15], src_scc, vcc_lo ; encoding: [0x7a,0x00,0x3e,0xd4,0xfd,0xd4,0x00,0x00]
+0x7a,0x00,0x3e,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmp_ge_u16_e64 null, 0xfe0b, vcc_hi   ; encoding: [0x7c,0x00,0x3e,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0x7c,0x00,0x3e,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_ge_u32_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x4e,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_ge_u32_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x4e,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x4e,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_ge_u32_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x4e,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_ge_u32_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x4e,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x4e,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_ge_u32_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x4e,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_ge_u32_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x4e,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x4e,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_ge_u32_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x4e,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_ge_u32_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x4e,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x4e,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_ge_u32_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x4e,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_ge_u32_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x4e,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x4e,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_ge_u32_e64 s10, vcc_hi, 0xaf123456  ; encoding: [0x0a,0x00,0x4e,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_ge_u32_e64 s[10:11], vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x4e,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x4e,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ge_u32_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x4e,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_ge_u32_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x4e,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x4e,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_ge_u32_e64 s10, m0, 0.5             ; encoding: [0x0a,0x00,0x4e,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_ge_u32_e64 s[10:11], m0, 0.5        ; encoding: [0x0a,0x00,0x4e,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x4e,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_ge_u32_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x4e,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_ge_u32_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x4e,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x4e,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_ge_u32_e64 s10, exec_hi, null       ; encoding: [0x0a,0x00,0x4e,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_ge_u32_e64 s[10:11], exec_hi, null  ; encoding: [0x0a,0x00,0x4e,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x00,0x4e,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_ge_u32_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x4e,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_ge_u32_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x4e,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x4e,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_ge_u32_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x4e,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_ge_u32_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x4e,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x4e,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_ge_u32_e64 vcc_lo, 0.5, m0          ; encoding: [0x6a,0x00,0x4e,0xd4,0xf0,0xfa,0x00,0x00]
+# W64: v_cmp_ge_u32_e64 vcc, 0.5, m0             ; encoding: [0x6a,0x00,0x4e,0xd4,0xf0,0xfa,0x00,0x00]
+0x6a,0x00,0x4e,0xd4,0xf0,0xfa,0x00,0x00
+
+# W32: v_cmp_ge_u32_e64 ttmp14, src_scc, vcc_lo  ; encoding: [0x7a,0x00,0x4e,0xd4,0xfd,0xd4,0x00,0x00]
+# W64: v_cmp_ge_u32_e64 ttmp[14:15], src_scc, vcc_lo ; encoding: [0x7a,0x00,0x4e,0xd4,0xfd,0xd4,0x00,0x00]
+0x7a,0x00,0x4e,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmp_ge_u32_e64 null, 0xaf123456, vcc_hi ; encoding: [0x7c,0x00,0x4e,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x4e,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ge_u64_e64 s10, v[1:2], v[2:3]      ; encoding: [0x0a,0x00,0x5e,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_ge_u64_e64 s[10:11], v[1:2], v[2:3] ; encoding: [0x0a,0x00,0x5e,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x5e,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_ge_u64_e64 s10, v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x5e,0xd4,0xfe,0xfd,0x03,0x00]
+# W64: v_cmp_ge_u64_e64 s[10:11], v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x5e,0xd4,0xfe,0xfd,0x03,0x00]
+0x0a,0x00,0x5e,0xd4,0xfe,0xfd,0x03,0x00
+
+# W32: v_cmp_ge_u64_e64 s10, s[2:3], s[4:5]      ; encoding: [0x0a,0x00,0x5e,0xd4,0x02,0x08,0x00,0x00]
+# W64: v_cmp_ge_u64_e64 s[10:11], s[2:3], s[4:5] ; encoding: [0x0a,0x00,0x5e,0xd4,0x02,0x08,0x00,0x00]
+0x0a,0x00,0x5e,0xd4,0x02,0x08,0x00,0x00
+
+# W32: v_cmp_ge_u64_e64 s10, s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x5e,0xd4,0x68,0xd0,0x00,0x00]
+# W64: v_cmp_ge_u64_e64 s[10:11], s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x5e,0xd4,0x68,0xd0,0x00,0x00]
+0x0a,0x00,0x5e,0xd4,0x68,0xd0,0x00,0x00
+
+# W32: v_cmp_ge_u64_e64 s10, vcc, ttmp[14:15]    ; encoding: [0x0a,0x00,0x5e,0xd4,0x6a,0xf4,0x00,0x00]
+# W64: v_cmp_ge_u64_e64 s[10:11], vcc, ttmp[14:15] ; encoding: [0x0a,0x00,0x5e,0xd4,0x6a,0xf4,0x00,0x00]
+0x0a,0x00,0x5e,0xd4,0x6a,0xf4,0x00,0x00
+
+# W32: v_cmp_ge_u64_e64 s10, ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x5e,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_ge_u64_e64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x5e,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x5e,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ge_u64_e64 s10, exec, src_scc       ; encoding: [0x0a,0x00,0x5e,0xd4,0x7e,0xfa,0x01,0x00]
+# W64: v_cmp_ge_u64_e64 s[10:11], exec, src_scc  ; encoding: [0x0a,0x00,0x5e,0xd4,0x7e,0xfa,0x01,0x00]
+0x0a,0x00,0x5e,0xd4,0x7e,0xfa,0x01,0x00
+
+# W32: v_cmp_ge_u64_e64 s10, null, 0.5           ; encoding: [0x0a,0x00,0x5e,0xd4,0x7c,0xe0,0x01,0x00]
+# W64: v_cmp_ge_u64_e64 s[10:11], null, 0.5      ; encoding: [0x0a,0x00,0x5e,0xd4,0x7c,0xe0,0x01,0x00]
+0x0a,0x00,0x5e,0xd4,0x7c,0xe0,0x01,0x00
+
+# W32: v_cmp_ge_u64_e64 s104, -1, -1             ; encoding: [0x68,0x00,0x5e,0xd4,0xc1,0x82,0x01,0x00]
+# W64: v_cmp_ge_u64_e64 s[104:105], -1, -1       ; encoding: [0x68,0x00,0x5e,0xd4,0xc1,0x82,0x01,0x00]
+0x68,0x00,0x5e,0xd4,0xc1,0x82,0x01,0x00
+
+# W32: v_cmp_ge_u64_e64 vcc_lo, 0.5, null        ; encoding: [0x6a,0x00,0x5e,0xd4,0xf0,0xf8,0x00,0x00]
+# W64: v_cmp_ge_u64_e64 vcc, 0.5, null           ; encoding: [0x6a,0x00,0x5e,0xd4,0xf0,0xf8,0x00,0x00]
+0x6a,0x00,0x5e,0xd4,0xf0,0xf8,0x00,0x00
+
+# W32: v_cmp_ge_u64_e64 ttmp14, src_scc, exec    ; encoding: [0x7a,0x00,0x5e,0xd4,0xfd,0xfc,0x00,0x00]
+# W64: v_cmp_ge_u64_e64 ttmp[14:15], src_scc, exec ; encoding: [0x7a,0x00,0x5e,0xd4,0xfd,0xfc,0x00,0x00]
+0x7a,0x00,0x5e,0xd4,0xfd,0xfc,0x00,0x00
+
+# GFX12: v_cmp_ge_u64_e64 null, 0xaf123456, vcc  ; encoding: [0x7c,0x00,0x5e,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x5e,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_gt_f16_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x04,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_gt_f16_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x04,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x04,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_gt_f16_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x04,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_gt_f16_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x04,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x04,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_gt_f16_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x04,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_gt_f16_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x04,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x04,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_gt_f16_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x04,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_gt_f16_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x04,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x04,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_gt_f16_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x04,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_gt_f16_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x04,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x04,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_gt_f16_e64 s10, vcc_hi, 0xfe0b      ; encoding: [0x0a,0x00,0x04,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_gt_f16_e64 s[10:11], vcc_hi, 0xfe0b ; encoding: [0x0a,0x00,0x04,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x0a,0x00,0x04,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_gt_f16_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x04,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_gt_f16_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x04,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x04,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_gt_f16_e64 s10, m0, 0.5             ; encoding: [0x0a,0x00,0x04,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_gt_f16_e64 s[10:11], m0, 0.5        ; encoding: [0x0a,0x00,0x04,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x04,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_gt_f16_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x04,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_gt_f16_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x04,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x04,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_gt_f16_e64 s10, |exec_hi|, null     ; encoding: [0x0a,0x01,0x04,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_gt_f16_e64 s[10:11], |exec_hi|, null ; encoding: [0x0a,0x01,0x04,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x01,0x04,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_gt_f16_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x04,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_gt_f16_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x04,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x04,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_gt_f16_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x04,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_gt_f16_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x04,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x04,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_gt_f16_e64 vcc_lo, 0.5, -m0         ; encoding: [0x6a,0x00,0x04,0xd4,0xf0,0xfa,0x00,0x40]
+# W64: v_cmp_gt_f16_e64 vcc, 0.5, -m0            ; encoding: [0x6a,0x00,0x04,0xd4,0xf0,0xfa,0x00,0x40]
+0x6a,0x00,0x04,0xd4,0xf0,0xfa,0x00,0x40
+
+# W32: v_cmp_gt_f16_e64 ttmp14, -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x04,0xd4,0xfd,0xd4,0x00,0x20]
+# W64: v_cmp_gt_f16_e64 ttmp[14:15], -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x04,0xd4,0xfd,0xd4,0x00,0x20]
+0x7a,0x02,0x04,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmp_gt_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x04,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x7c,0x83,0x04,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_gt_f32_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x14,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_gt_f32_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x14,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x14,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_gt_f32_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x14,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_gt_f32_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x14,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x14,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_gt_f32_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x14,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_gt_f32_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x14,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x14,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_gt_f32_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x14,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_gt_f32_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x14,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x14,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_gt_f32_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x14,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_gt_f32_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x14,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x14,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_gt_f32_e64 s10, vcc_hi, 0xaf123456  ; encoding: [0x0a,0x00,0x14,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_gt_f32_e64 s[10:11], vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x14,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x14,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_gt_f32_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x14,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_gt_f32_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x14,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x14,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_gt_f32_e64 s10, m0, 0.5             ; encoding: [0x0a,0x00,0x14,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_gt_f32_e64 s[10:11], m0, 0.5        ; encoding: [0x0a,0x00,0x14,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x14,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_gt_f32_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x14,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_gt_f32_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x14,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x14,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_gt_f32_e64 s10, |exec_hi|, null     ; encoding: [0x0a,0x01,0x14,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_gt_f32_e64 s[10:11], |exec_hi|, null ; encoding: [0x0a,0x01,0x14,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x01,0x14,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_gt_f32_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x14,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_gt_f32_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x14,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x14,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_gt_f32_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x14,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_gt_f32_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x14,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x14,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_gt_f32_e64 vcc_lo, 0.5, -m0         ; encoding: [0x6a,0x00,0x14,0xd4,0xf0,0xfa,0x00,0x40]
+# W64: v_cmp_gt_f32_e64 vcc, 0.5, -m0            ; encoding: [0x6a,0x00,0x14,0xd4,0xf0,0xfa,0x00,0x40]
+0x6a,0x00,0x14,0xd4,0xf0,0xfa,0x00,0x40
+
+# W32: v_cmp_gt_f32_e64 ttmp14, -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x14,0xd4,0xfd,0xd4,0x00,0x20]
+# W64: v_cmp_gt_f32_e64 ttmp[14:15], -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x14,0xd4,0xfd,0xd4,0x00,0x20]
+0x7a,0x02,0x14,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmp_gt_f32_e64 null, -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x14,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0x7c,0x83,0x14,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_gt_f64_e64 s10, v[1:2], v[2:3]      ; encoding: [0x0a,0x00,0x24,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_gt_f64_e64 s[10:11], v[1:2], v[2:3] ; encoding: [0x0a,0x00,0x24,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x24,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_gt_f64_e64 s10, v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x24,0xd4,0xfe,0xfd,0x03,0x00]
+# W64: v_cmp_gt_f64_e64 s[10:11], v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x24,0xd4,0xfe,0xfd,0x03,0x00]
+0x0a,0x00,0x24,0xd4,0xfe,0xfd,0x03,0x00
+
+# W32: v_cmp_gt_f64_e64 s10, s[2:3], s[4:5]      ; encoding: [0x0a,0x00,0x24,0xd4,0x02,0x08,0x00,0x00]
+# W64: v_cmp_gt_f64_e64 s[10:11], s[2:3], s[4:5] ; encoding: [0x0a,0x00,0x24,0xd4,0x02,0x08,0x00,0x00]
+0x0a,0x00,0x24,0xd4,0x02,0x08,0x00,0x00
+
+# W32: v_cmp_gt_f64_e64 s10, s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x24,0xd4,0x68,0xd0,0x00,0x00]
+# W64: v_cmp_gt_f64_e64 s[10:11], s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x24,0xd4,0x68,0xd0,0x00,0x00]
+0x0a,0x00,0x24,0xd4,0x68,0xd0,0x00,0x00
+
+# W32: v_cmp_gt_f64_e64 s10, vcc, ttmp[14:15]    ; encoding: [0x0a,0x00,0x24,0xd4,0x6a,0xf4,0x00,0x00]
+# W64: v_cmp_gt_f64_e64 s[10:11], vcc, ttmp[14:15] ; encoding: [0x0a,0x00,0x24,0xd4,0x6a,0xf4,0x00,0x00]
+0x0a,0x00,0x24,0xd4,0x6a,0xf4,0x00,0x00
+
+# W32: v_cmp_gt_f64_e64 s10, ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x24,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_gt_f64_e64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x24,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x24,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_gt_f64_e64 s10, -|exec|, src_scc    ; encoding: [0x0a,0x01,0x24,0xd4,0x7e,0xfa,0x01,0x20]
+# W64: v_cmp_gt_f64_e64 s[10:11], -|exec|, src_scc ; encoding: [0x0a,0x01,0x24,0xd4,0x7e,0xfa,0x01,0x20]
+0x0a,0x01,0x24,0xd4,0x7e,0xfa,0x01,0x20
+
+# W32: v_cmp_gt_f64_e64 s10, null, 0.5           ; encoding: [0x0a,0x00,0x24,0xd4,0x7c,0xe0,0x01,0x00]
+# W64: v_cmp_gt_f64_e64 s[10:11], null, 0.5      ; encoding: [0x0a,0x00,0x24,0xd4,0x7c,0xe0,0x01,0x00]
+0x0a,0x00,0x24,0xd4,0x7c,0xe0,0x01,0x00
+
+# W32: v_cmp_gt_f64_e64 s104, -1, -1             ; encoding: [0x68,0x00,0x24,0xd4,0xc1,0x82,0x01,0x00]
+# W64: v_cmp_gt_f64_e64 s[104:105], -1, -1       ; encoding: [0x68,0x00,0x24,0xd4,0xc1,0x82,0x01,0x00]
+0x68,0x00,0x24,0xd4,0xc1,0x82,0x01,0x00
+
+# W32: v_cmp_gt_f64_e64 vcc_lo, 0.5, null        ; encoding: [0x6a,0x00,0x24,0xd4,0xf0,0xf8,0x00,0x00]
+# W64: v_cmp_gt_f64_e64 vcc, 0.5, null           ; encoding: [0x6a,0x00,0x24,0xd4,0xf0,0xf8,0x00,0x00]
+0x6a,0x00,0x24,0xd4,0xf0,0xf8,0x00,0x00
+
+# W32: v_cmp_gt_f64_e64 ttmp14, -|src_scc|, -|exec| ; encoding: [0x7a,0x03,0x24,0xd4,0xfd,0xfc,0x00,0x60]
+# W64: v_cmp_gt_f64_e64 ttmp[14:15], -|src_scc|, -|exec| ; encoding: [0x7a,0x03,0x24,0xd4,0xfd,0xfc,0x00,0x60]
+0x7a,0x03,0x24,0xd4,0xfd,0xfc,0x00,0x60
+
+# GFX12: v_cmp_gt_f64_e64 null, 0xaf123456, -|vcc| clamp ; encoding: [0x7c,0x82,0x24,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+0x7c,0x82,0x24,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_gt_i16_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x34,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_gt_i16_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x34,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x34,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_gt_i16_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x34,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_gt_i16_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x34,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x34,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_gt_i16_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x34,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_gt_i16_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x34,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x34,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_gt_i16_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x34,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_gt_i16_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x34,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x34,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_gt_i16_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x34,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_gt_i16_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x34,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x34,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_gt_i16_e64 s10, vcc_hi, 0xfe0b      ; encoding: [0x0a,0x00,0x34,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_gt_i16_e64 s[10:11], vcc_hi, 0xfe0b ; encoding: [0x0a,0x00,0x34,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x0a,0x00,0x34,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_gt_i16_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x34,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_gt_i16_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x34,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x34,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_gt_i16_e64 s10, m0, 0x3800          ; encoding: [0x0a,0x00,0x34,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+# W64: v_cmp_gt_i16_e64 s[10:11], m0, 0x3800     ; encoding: [0x0a,0x00,0x34,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+0x0a,0x00,0x34,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_gt_i16_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x34,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_gt_i16_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x34,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x34,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_gt_i16_e64 s10, exec_hi, null       ; encoding: [0x0a,0x00,0x34,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_gt_i16_e64 s[10:11], exec_hi, null  ; encoding: [0x0a,0x00,0x34,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x00,0x34,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_gt_i16_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x34,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_gt_i16_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x34,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x34,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_gt_i16_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x34,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_gt_i16_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x34,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x34,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_gt_i16_e64 vcc_lo, 0x3800, m0       ; encoding: [0x6a,0x00,0x34,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+# W64: v_cmp_gt_i16_e64 vcc, 0x3800, m0          ; encoding: [0x6a,0x00,0x34,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+0x6a,0x00,0x34,0xd4,0xf0,0xfa,0x00,0x00
+
+# W32: v_cmp_gt_i16_e64 ttmp14, src_scc, vcc_lo  ; encoding: [0x7a,0x00,0x34,0xd4,0xfd,0xd4,0x00,0x00]
+# W64: v_cmp_gt_i16_e64 ttmp[14:15], src_scc, vcc_lo ; encoding: [0x7a,0x00,0x34,0xd4,0xfd,0xd4,0x00,0x00]
+0x7a,0x00,0x34,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmp_gt_i16_e64 null, 0xfe0b, vcc_hi   ; encoding: [0x7c,0x00,0x34,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0x7c,0x00,0x34,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_gt_i32_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x44,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_gt_i32_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x44,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x44,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_gt_i32_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x44,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_gt_i32_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x44,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x44,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_gt_i32_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x44,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_gt_i32_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x44,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x44,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_gt_i32_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x44,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_gt_i32_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x44,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x44,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_gt_i32_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x44,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_gt_i32_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x44,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x44,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_gt_i32_e64 s10, vcc_hi, 0xaf123456  ; encoding: [0x0a,0x00,0x44,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_gt_i32_e64 s[10:11], vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x44,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x44,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_gt_i32_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x44,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_gt_i32_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x44,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x44,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_gt_i32_e64 s10, m0, 0.5             ; encoding: [0x0a,0x00,0x44,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_gt_i32_e64 s[10:11], m0, 0.5        ; encoding: [0x0a,0x00,0x44,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x44,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_gt_i32_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x44,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_gt_i32_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x44,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x44,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_gt_i32_e64 s10, exec_hi, null       ; encoding: [0x0a,0x00,0x44,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_gt_i32_e64 s[10:11], exec_hi, null  ; encoding: [0x0a,0x00,0x44,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x00,0x44,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_gt_i32_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x44,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_gt_i32_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x44,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x44,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_gt_i32_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x44,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_gt_i32_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x44,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x44,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_gt_i32_e64 vcc_lo, 0.5, m0          ; encoding: [0x6a,0x00,0x44,0xd4,0xf0,0xfa,0x00,0x00]
+# W64: v_cmp_gt_i32_e64 vcc, 0.5, m0             ; encoding: [0x6a,0x00,0x44,0xd4,0xf0,0xfa,0x00,0x00]
+0x6a,0x00,0x44,0xd4,0xf0,0xfa,0x00,0x00
+
+# W32: v_cmp_gt_i32_e64 ttmp14, src_scc, vcc_lo  ; encoding: [0x7a,0x00,0x44,0xd4,0xfd,0xd4,0x00,0x00]
+# W64: v_cmp_gt_i32_e64 ttmp[14:15], src_scc, vcc_lo ; encoding: [0x7a,0x00,0x44,0xd4,0xfd,0xd4,0x00,0x00]
+0x7a,0x00,0x44,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmp_gt_i32_e64 null, 0xaf123456, vcc_hi ; encoding: [0x7c,0x00,0x44,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x44,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_gt_i64_e64 s10, v[1:2], v[2:3]      ; encoding: [0x0a,0x00,0x54,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_gt_i64_e64 s[10:11], v[1:2], v[2:3] ; encoding: [0x0a,0x00,0x54,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x54,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_gt_i64_e64 s10, v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x54,0xd4,0xfe,0xfd,0x03,0x00]
+# W64: v_cmp_gt_i64_e64 s[10:11], v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x54,0xd4,0xfe,0xfd,0x03,0x00]
+0x0a,0x00,0x54,0xd4,0xfe,0xfd,0x03,0x00
+
+# W32: v_cmp_gt_i64_e64 s10, s[2:3], s[4:5]      ; encoding: [0x0a,0x00,0x54,0xd4,0x02,0x08,0x00,0x00]
+# W64: v_cmp_gt_i64_e64 s[10:11], s[2:3], s[4:5] ; encoding: [0x0a,0x00,0x54,0xd4,0x02,0x08,0x00,0x00]
+0x0a,0x00,0x54,0xd4,0x02,0x08,0x00,0x00
+
+# W32: v_cmp_gt_i64_e64 s10, s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x54,0xd4,0x68,0xd0,0x00,0x00]
+# W64: v_cmp_gt_i64_e64 s[10:11], s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x54,0xd4,0x68,0xd0,0x00,0x00]
+0x0a,0x00,0x54,0xd4,0x68,0xd0,0x00,0x00
+
+# W32: v_cmp_gt_i64_e64 s10, vcc, ttmp[14:15]    ; encoding: [0x0a,0x00,0x54,0xd4,0x6a,0xf4,0x00,0x00]
+# W64: v_cmp_gt_i64_e64 s[10:11], vcc, ttmp[14:15] ; encoding: [0x0a,0x00,0x54,0xd4,0x6a,0xf4,0x00,0x00]
+0x0a,0x00,0x54,0xd4,0x6a,0xf4,0x00,0x00
+
+# W32: v_cmp_gt_i64_e64 s10, ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x54,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_gt_i64_e64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x54,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x54,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_gt_i64_e64 s10, exec, src_scc       ; encoding: [0x0a,0x00,0x54,0xd4,0x7e,0xfa,0x01,0x00]
+# W64: v_cmp_gt_i64_e64 s[10:11], exec, src_scc  ; encoding: [0x0a,0x00,0x54,0xd4,0x7e,0xfa,0x01,0x00]
+0x0a,0x00,0x54,0xd4,0x7e,0xfa,0x01,0x00
+
+# W32: v_cmp_gt_i64_e64 s10, null, 0.5           ; encoding: [0x0a,0x00,0x54,0xd4,0x7c,0xe0,0x01,0x00]
+# W64: v_cmp_gt_i64_e64 s[10:11], null, 0.5      ; encoding: [0x0a,0x00,0x54,0xd4,0x7c,0xe0,0x01,0x00]
+0x0a,0x00,0x54,0xd4,0x7c,0xe0,0x01,0x00
+
+# W32: v_cmp_gt_i64_e64 s104, -1, -1             ; encoding: [0x68,0x00,0x54,0xd4,0xc1,0x82,0x01,0x00]
+# W64: v_cmp_gt_i64_e64 s[104:105], -1, -1       ; encoding: [0x68,0x00,0x54,0xd4,0xc1,0x82,0x01,0x00]
+0x68,0x00,0x54,0xd4,0xc1,0x82,0x01,0x00
+
+# W32: v_cmp_gt_i64_e64 vcc_lo, 0.5, null        ; encoding: [0x6a,0x00,0x54,0xd4,0xf0,0xf8,0x00,0x00]
+# W64: v_cmp_gt_i64_e64 vcc, 0.5, null           ; encoding: [0x6a,0x00,0x54,0xd4,0xf0,0xf8,0x00,0x00]
+0x6a,0x00,0x54,0xd4,0xf0,0xf8,0x00,0x00
+
+# W32: v_cmp_gt_i64_e64 ttmp14, src_scc, exec    ; encoding: [0x7a,0x00,0x54,0xd4,0xfd,0xfc,0x00,0x00]
+# W64: v_cmp_gt_i64_e64 ttmp[14:15], src_scc, exec ; encoding: [0x7a,0x00,0x54,0xd4,0xfd,0xfc,0x00,0x00]
+0x7a,0x00,0x54,0xd4,0xfd,0xfc,0x00,0x00
+
+# GFX12: v_cmp_gt_i64_e64 null, 0xaf123456, vcc  ; encoding: [0x7c,0x00,0x54,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x54,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_gt_u16_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x3c,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_gt_u16_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x3c,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x3c,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_gt_u16_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x3c,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_gt_u16_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x3c,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x3c,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_gt_u16_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x3c,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_gt_u16_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x3c,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x3c,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_gt_u16_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x3c,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_gt_u16_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x3c,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x3c,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_gt_u16_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x3c,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_gt_u16_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x3c,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x3c,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_gt_u16_e64 s10, vcc_hi, 0xfe0b      ; encoding: [0x0a,0x00,0x3c,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_gt_u16_e64 s[10:11], vcc_hi, 0xfe0b ; encoding: [0x0a,0x00,0x3c,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x0a,0x00,0x3c,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_gt_u16_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x3c,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_gt_u16_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x3c,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x3c,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_gt_u16_e64 s10, m0, 0x3800          ; encoding: [0x0a,0x00,0x3c,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+# W64: v_cmp_gt_u16_e64 s[10:11], m0, 0x3800     ; encoding: [0x0a,0x00,0x3c,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+0x0a,0x00,0x3c,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_gt_u16_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x3c,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_gt_u16_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x3c,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x3c,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_gt_u16_e64 s10, exec_hi, null       ; encoding: [0x0a,0x00,0x3c,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_gt_u16_e64 s[10:11], exec_hi, null  ; encoding: [0x0a,0x00,0x3c,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x00,0x3c,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_gt_u16_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x3c,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_gt_u16_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x3c,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x3c,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_gt_u16_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x3c,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_gt_u16_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x3c,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x3c,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_gt_u16_e64 vcc_lo, 0x3800, m0       ; encoding: [0x6a,0x00,0x3c,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+# W64: v_cmp_gt_u16_e64 vcc, 0x3800, m0          ; encoding: [0x6a,0x00,0x3c,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+0x6a,0x00,0x3c,0xd4,0xf0,0xfa,0x00,0x00
+
+# W32: v_cmp_gt_u16_e64 ttmp14, src_scc, vcc_lo  ; encoding: [0x7a,0x00,0x3c,0xd4,0xfd,0xd4,0x00,0x00]
+# W64: v_cmp_gt_u16_e64 ttmp[14:15], src_scc, vcc_lo ; encoding: [0x7a,0x00,0x3c,0xd4,0xfd,0xd4,0x00,0x00]
+0x7a,0x00,0x3c,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmp_gt_u16_e64 null, 0xfe0b, vcc_hi   ; encoding: [0x7c,0x00,0x3c,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0x7c,0x00,0x3c,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_gt_u32_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x4c,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_gt_u32_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x4c,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x4c,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_gt_u32_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x4c,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_gt_u32_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x4c,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x4c,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_gt_u32_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x4c,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_gt_u32_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x4c,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x4c,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_gt_u32_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x4c,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_gt_u32_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x4c,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x4c,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_gt_u32_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x4c,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_gt_u32_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x4c,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x4c,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_gt_u32_e64 s10, vcc_hi, 0xaf123456  ; encoding: [0x0a,0x00,0x4c,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_gt_u32_e64 s[10:11], vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x4c,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x4c,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_gt_u32_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x4c,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_gt_u32_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x4c,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x4c,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_gt_u32_e64 s10, m0, 0.5             ; encoding: [0x0a,0x00,0x4c,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_gt_u32_e64 s[10:11], m0, 0.5        ; encoding: [0x0a,0x00,0x4c,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x4c,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_gt_u32_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x4c,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_gt_u32_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x4c,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x4c,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_gt_u32_e64 s10, exec_hi, null       ; encoding: [0x0a,0x00,0x4c,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_gt_u32_e64 s[10:11], exec_hi, null  ; encoding: [0x0a,0x00,0x4c,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x00,0x4c,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_gt_u32_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x4c,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_gt_u32_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x4c,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x4c,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_gt_u32_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x4c,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_gt_u32_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x4c,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x4c,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_gt_u32_e64 vcc_lo, 0.5, m0          ; encoding: [0x6a,0x00,0x4c,0xd4,0xf0,0xfa,0x00,0x00]
+# W64: v_cmp_gt_u32_e64 vcc, 0.5, m0             ; encoding: [0x6a,0x00,0x4c,0xd4,0xf0,0xfa,0x00,0x00]
+0x6a,0x00,0x4c,0xd4,0xf0,0xfa,0x00,0x00
+
+# W32: v_cmp_gt_u32_e64 ttmp14, src_scc, vcc_lo  ; encoding: [0x7a,0x00,0x4c,0xd4,0xfd,0xd4,0x00,0x00]
+# W64: v_cmp_gt_u32_e64 ttmp[14:15], src_scc, vcc_lo ; encoding: [0x7a,0x00,0x4c,0xd4,0xfd,0xd4,0x00,0x00]
+0x7a,0x00,0x4c,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmp_gt_u32_e64 null, 0xaf123456, vcc_hi ; encoding: [0x7c,0x00,0x4c,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x4c,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_gt_u64_e64 s10, v[1:2], v[2:3]      ; encoding: [0x0a,0x00,0x5c,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_gt_u64_e64 s[10:11], v[1:2], v[2:3] ; encoding: [0x0a,0x00,0x5c,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x5c,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_gt_u64_e64 s10, v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x5c,0xd4,0xfe,0xfd,0x03,0x00]
+# W64: v_cmp_gt_u64_e64 s[10:11], v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x5c,0xd4,0xfe,0xfd,0x03,0x00]
+0x0a,0x00,0x5c,0xd4,0xfe,0xfd,0x03,0x00
+
+# W32: v_cmp_gt_u64_e64 s10, s[2:3], s[4:5]      ; encoding: [0x0a,0x00,0x5c,0xd4,0x02,0x08,0x00,0x00]
+# W64: v_cmp_gt_u64_e64 s[10:11], s[2:3], s[4:5] ; encoding: [0x0a,0x00,0x5c,0xd4,0x02,0x08,0x00,0x00]
+0x0a,0x00,0x5c,0xd4,0x02,0x08,0x00,0x00
+
+# W32: v_cmp_gt_u64_e64 s10, s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x5c,0xd4,0x68,0xd0,0x00,0x00]
+# W64: v_cmp_gt_u64_e64 s[10:11], s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x5c,0xd4,0x68,0xd0,0x00,0x00]
+0x0a,0x00,0x5c,0xd4,0x68,0xd0,0x00,0x00
+
+# W32: v_cmp_gt_u64_e64 s10, vcc, ttmp[14:15]    ; encoding: [0x0a,0x00,0x5c,0xd4,0x6a,0xf4,0x00,0x00]
+# W64: v_cmp_gt_u64_e64 s[10:11], vcc, ttmp[14:15] ; encoding: [0x0a,0x00,0x5c,0xd4,0x6a,0xf4,0x00,0x00]
+0x0a,0x00,0x5c,0xd4,0x6a,0xf4,0x00,0x00
+
+# W32: v_cmp_gt_u64_e64 s10, ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x5c,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_gt_u64_e64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x5c,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x5c,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_gt_u64_e64 s10, exec, src_scc       ; encoding: [0x0a,0x00,0x5c,0xd4,0x7e,0xfa,0x01,0x00]
+# W64: v_cmp_gt_u64_e64 s[10:11], exec, src_scc  ; encoding: [0x0a,0x00,0x5c,0xd4,0x7e,0xfa,0x01,0x00]
+0x0a,0x00,0x5c,0xd4,0x7e,0xfa,0x01,0x00
+
+# W32: v_cmp_gt_u64_e64 s10, null, 0.5           ; encoding: [0x0a,0x00,0x5c,0xd4,0x7c,0xe0,0x01,0x00]
+# W64: v_cmp_gt_u64_e64 s[10:11], null, 0.5      ; encoding: [0x0a,0x00,0x5c,0xd4,0x7c,0xe0,0x01,0x00]
+0x0a,0x00,0x5c,0xd4,0x7c,0xe0,0x01,0x00
+
+# W32: v_cmp_gt_u64_e64 s104, -1, -1             ; encoding: [0x68,0x00,0x5c,0xd4,0xc1,0x82,0x01,0x00]
+# W64: v_cmp_gt_u64_e64 s[104:105], -1, -1       ; encoding: [0x68,0x00,0x5c,0xd4,0xc1,0x82,0x01,0x00]
+0x68,0x00,0x5c,0xd4,0xc1,0x82,0x01,0x00
+
+# W32: v_cmp_gt_u64_e64 vcc_lo, 0.5, null        ; encoding: [0x6a,0x00,0x5c,0xd4,0xf0,0xf8,0x00,0x00]
+# W64: v_cmp_gt_u64_e64 vcc, 0.5, null           ; encoding: [0x6a,0x00,0x5c,0xd4,0xf0,0xf8,0x00,0x00]
+0x6a,0x00,0x5c,0xd4,0xf0,0xf8,0x00,0x00
+
+# W32: v_cmp_gt_u64_e64 ttmp14, src_scc, exec    ; encoding: [0x7a,0x00,0x5c,0xd4,0xfd,0xfc,0x00,0x00]
+# W64: v_cmp_gt_u64_e64 ttmp[14:15], src_scc, exec ; encoding: [0x7a,0x00,0x5c,0xd4,0xfd,0xfc,0x00,0x00]
+0x7a,0x00,0x5c,0xd4,0xfd,0xfc,0x00,0x00
+
+# GFX12: v_cmp_gt_u64_e64 null, 0xaf123456, vcc  ; encoding: [0x7c,0x00,0x5c,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x5c,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_le_f16_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x03,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_le_f16_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x03,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x03,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_le_f16_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x03,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_le_f16_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x03,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x03,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_le_f16_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x03,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_le_f16_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x03,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x03,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_le_f16_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x03,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_le_f16_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x03,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x03,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_le_f16_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x03,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_le_f16_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x03,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x03,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_le_f16_e64 s10, vcc_hi, 0xfe0b      ; encoding: [0x0a,0x00,0x03,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_le_f16_e64 s[10:11], vcc_hi, 0xfe0b ; encoding: [0x0a,0x00,0x03,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x0a,0x00,0x03,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_le_f16_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x03,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_le_f16_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x03,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x03,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_le_f16_e64 s10, m0, 0.5             ; encoding: [0x0a,0x00,0x03,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_le_f16_e64 s[10:11], m0, 0.5        ; encoding: [0x0a,0x00,0x03,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x03,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_le_f16_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x03,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_le_f16_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x03,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x03,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_le_f16_e64 s10, |exec_hi|, null     ; encoding: [0x0a,0x01,0x03,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_le_f16_e64 s[10:11], |exec_hi|, null ; encoding: [0x0a,0x01,0x03,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x01,0x03,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_le_f16_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x03,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_le_f16_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x03,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x03,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_le_f16_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x03,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_le_f16_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x03,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x03,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_le_f16_e64 vcc_lo, 0.5, -m0         ; encoding: [0x6a,0x00,0x03,0xd4,0xf0,0xfa,0x00,0x40]
+# W64: v_cmp_le_f16_e64 vcc, 0.5, -m0            ; encoding: [0x6a,0x00,0x03,0xd4,0xf0,0xfa,0x00,0x40]
+0x6a,0x00,0x03,0xd4,0xf0,0xfa,0x00,0x40
+
+# W32: v_cmp_le_f16_e64 ttmp14, -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x03,0xd4,0xfd,0xd4,0x00,0x20]
+# W64: v_cmp_le_f16_e64 ttmp[14:15], -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x03,0xd4,0xfd,0xd4,0x00,0x20]
+0x7a,0x02,0x03,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmp_le_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x03,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x7c,0x83,0x03,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_le_f32_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x13,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_le_f32_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x13,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x13,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_le_f32_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x13,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_le_f32_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x13,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x13,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_le_f32_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x13,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_le_f32_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x13,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x13,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_le_f32_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x13,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_le_f32_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x13,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x13,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_le_f32_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x13,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_le_f32_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x13,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x13,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_le_f32_e64 s10, vcc_hi, 0xaf123456  ; encoding: [0x0a,0x00,0x13,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_le_f32_e64 s[10:11], vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x13,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x13,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_le_f32_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x13,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_le_f32_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x13,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x13,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_le_f32_e64 s10, m0, 0.5             ; encoding: [0x0a,0x00,0x13,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_le_f32_e64 s[10:11], m0, 0.5        ; encoding: [0x0a,0x00,0x13,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x13,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_le_f32_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x13,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_le_f32_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x13,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x13,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_le_f32_e64 s10, |exec_hi|, null     ; encoding: [0x0a,0x01,0x13,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_le_f32_e64 s[10:11], |exec_hi|, null ; encoding: [0x0a,0x01,0x13,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x01,0x13,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_le_f32_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x13,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_le_f32_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x13,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x13,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_le_f32_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x13,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_le_f32_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x13,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x13,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_le_f32_e64 vcc_lo, 0.5, -m0         ; encoding: [0x6a,0x00,0x13,0xd4,0xf0,0xfa,0x00,0x40]
+# W64: v_cmp_le_f32_e64 vcc, 0.5, -m0            ; encoding: [0x6a,0x00,0x13,0xd4,0xf0,0xfa,0x00,0x40]
+0x6a,0x00,0x13,0xd4,0xf0,0xfa,0x00,0x40
+
+# W32: v_cmp_le_f32_e64 ttmp14, -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x13,0xd4,0xfd,0xd4,0x00,0x20]
+# W64: v_cmp_le_f32_e64 ttmp[14:15], -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x13,0xd4,0xfd,0xd4,0x00,0x20]
+0x7a,0x02,0x13,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmp_le_f32_e64 null, -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x13,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0x7c,0x83,0x13,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_le_f64_e64 s10, v[1:2], v[2:3]      ; encoding: [0x0a,0x00,0x23,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_le_f64_e64 s[10:11], v[1:2], v[2:3] ; encoding: [0x0a,0x00,0x23,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x23,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_le_f64_e64 s10, v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x23,0xd4,0xfe,0xfd,0x03,0x00]
+# W64: v_cmp_le_f64_e64 s[10:11], v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x23,0xd4,0xfe,0xfd,0x03,0x00]
+0x0a,0x00,0x23,0xd4,0xfe,0xfd,0x03,0x00
+
+# W32: v_cmp_le_f64_e64 s10, s[2:3], s[4:5]      ; encoding: [0x0a,0x00,0x23,0xd4,0x02,0x08,0x00,0x00]
+# W64: v_cmp_le_f64_e64 s[10:11], s[2:3], s[4:5] ; encoding: [0x0a,0x00,0x23,0xd4,0x02,0x08,0x00,0x00]
+0x0a,0x00,0x23,0xd4,0x02,0x08,0x00,0x00
+
+# W32: v_cmp_le_f64_e64 s10, s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x23,0xd4,0x68,0xd0,0x00,0x00]
+# W64: v_cmp_le_f64_e64 s[10:11], s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x23,0xd4,0x68,0xd0,0x00,0x00]
+0x0a,0x00,0x23,0xd4,0x68,0xd0,0x00,0x00
+
+# W32: v_cmp_le_f64_e64 s10, vcc, ttmp[14:15]    ; encoding: [0x0a,0x00,0x23,0xd4,0x6a,0xf4,0x00,0x00]
+# W64: v_cmp_le_f64_e64 s[10:11], vcc, ttmp[14:15] ; encoding: [0x0a,0x00,0x23,0xd4,0x6a,0xf4,0x00,0x00]
+0x0a,0x00,0x23,0xd4,0x6a,0xf4,0x00,0x00
+
+# W32: v_cmp_le_f64_e64 s10, ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x23,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_le_f64_e64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x23,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x23,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_le_f64_e64 s10, -|exec|, src_scc    ; encoding: [0x0a,0x01,0x23,0xd4,0x7e,0xfa,0x01,0x20]
+# W64: v_cmp_le_f64_e64 s[10:11], -|exec|, src_scc ; encoding: [0x0a,0x01,0x23,0xd4,0x7e,0xfa,0x01,0x20]
+0x0a,0x01,0x23,0xd4,0x7e,0xfa,0x01,0x20
+
+# W32: v_cmp_le_f64_e64 s10, null, 0.5           ; encoding: [0x0a,0x00,0x23,0xd4,0x7c,0xe0,0x01,0x00]
+# W64: v_cmp_le_f64_e64 s[10:11], null, 0.5      ; encoding: [0x0a,0x00,0x23,0xd4,0x7c,0xe0,0x01,0x00]
+0x0a,0x00,0x23,0xd4,0x7c,0xe0,0x01,0x00
+
+# W32: v_cmp_le_f64_e64 s104, -1, -1             ; encoding: [0x68,0x00,0x23,0xd4,0xc1,0x82,0x01,0x00]
+# W64: v_cmp_le_f64_e64 s[104:105], -1, -1       ; encoding: [0x68,0x00,0x23,0xd4,0xc1,0x82,0x01,0x00]
+0x68,0x00,0x23,0xd4,0xc1,0x82,0x01,0x00
+
+# W32: v_cmp_le_f64_e64 vcc_lo, 0.5, null        ; encoding: [0x6a,0x00,0x23,0xd4,0xf0,0xf8,0x00,0x00]
+# W64: v_cmp_le_f64_e64 vcc, 0.5, null           ; encoding: [0x6a,0x00,0x23,0xd4,0xf0,0xf8,0x00,0x00]
+0x6a,0x00,0x23,0xd4,0xf0,0xf8,0x00,0x00
+
+# W32: v_cmp_le_f64_e64 ttmp14, -|src_scc|, -|exec| ; encoding: [0x7a,0x03,0x23,0xd4,0xfd,0xfc,0x00,0x60]
+# W64: v_cmp_le_f64_e64 ttmp[14:15], -|src_scc|, -|exec| ; encoding: [0x7a,0x03,0x23,0xd4,0xfd,0xfc,0x00,0x60]
+0x7a,0x03,0x23,0xd4,0xfd,0xfc,0x00,0x60
+
+# GFX12: v_cmp_le_f64_e64 null, 0xaf123456, -|vcc| clamp ; encoding: [0x7c,0x82,0x23,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+0x7c,0x82,0x23,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_le_i16_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x33,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_le_i16_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x33,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x33,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_le_i16_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x33,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_le_i16_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x33,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x33,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_le_i16_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x33,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_le_i16_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x33,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x33,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_le_i16_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x33,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_le_i16_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x33,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x33,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_le_i16_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x33,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_le_i16_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x33,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x33,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_le_i16_e64 s10, vcc_hi, 0xfe0b      ; encoding: [0x0a,0x00,0x33,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_le_i16_e64 s[10:11], vcc_hi, 0xfe0b ; encoding: [0x0a,0x00,0x33,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x0a,0x00,0x33,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_le_i16_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x33,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_le_i16_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x33,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x33,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_le_i16_e64 s10, m0, 0x3800          ; encoding: [0x0a,0x00,0x33,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+# W64: v_cmp_le_i16_e64 s[10:11], m0, 0x3800     ; encoding: [0x0a,0x00,0x33,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+0x0a,0x00,0x33,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_le_i16_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x33,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_le_i16_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x33,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x33,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_le_i16_e64 s10, exec_hi, null       ; encoding: [0x0a,0x00,0x33,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_le_i16_e64 s[10:11], exec_hi, null  ; encoding: [0x0a,0x00,0x33,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x00,0x33,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_le_i16_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x33,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_le_i16_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x33,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x33,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_le_i16_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x33,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_le_i16_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x33,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x33,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_le_i16_e64 vcc_lo, 0x3800, m0       ; encoding: [0x6a,0x00,0x33,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+# W64: v_cmp_le_i16_e64 vcc, 0x3800, m0          ; encoding: [0x6a,0x00,0x33,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+0x6a,0x00,0x33,0xd4,0xf0,0xfa,0x00,0x00
+
+# W32: v_cmp_le_i16_e64 ttmp14, src_scc, vcc_lo  ; encoding: [0x7a,0x00,0x33,0xd4,0xfd,0xd4,0x00,0x00]
+# W64: v_cmp_le_i16_e64 ttmp[14:15], src_scc, vcc_lo ; encoding: [0x7a,0x00,0x33,0xd4,0xfd,0xd4,0x00,0x00]
+0x7a,0x00,0x33,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmp_le_i16_e64 null, 0xfe0b, vcc_hi   ; encoding: [0x7c,0x00,0x33,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0x7c,0x00,0x33,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_le_i32_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x43,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_le_i32_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x43,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x43,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_le_i32_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x43,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_le_i32_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x43,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x43,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_le_i32_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x43,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_le_i32_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x43,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x43,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_le_i32_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x43,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_le_i32_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x43,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x43,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_le_i32_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x43,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_le_i32_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x43,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x43,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_le_i32_e64 s10, vcc_hi, 0xaf123456  ; encoding: [0x0a,0x00,0x43,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_le_i32_e64 s[10:11], vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x43,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x43,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_le_i32_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x43,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_le_i32_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x43,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x43,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_le_i32_e64 s10, m0, 0.5             ; encoding: [0x0a,0x00,0x43,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_le_i32_e64 s[10:11], m0, 0.5        ; encoding: [0x0a,0x00,0x43,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x43,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_le_i32_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x43,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_le_i32_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x43,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x43,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_le_i32_e64 s10, exec_hi, null       ; encoding: [0x0a,0x00,0x43,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_le_i32_e64 s[10:11], exec_hi, null  ; encoding: [0x0a,0x00,0x43,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x00,0x43,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_le_i32_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x43,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_le_i32_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x43,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x43,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_le_i32_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x43,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_le_i32_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x43,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x43,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_le_i32_e64 vcc_lo, 0.5, m0          ; encoding: [0x6a,0x00,0x43,0xd4,0xf0,0xfa,0x00,0x00]
+# W64: v_cmp_le_i32_e64 vcc, 0.5, m0             ; encoding: [0x6a,0x00,0x43,0xd4,0xf0,0xfa,0x00,0x00]
+0x6a,0x00,0x43,0xd4,0xf0,0xfa,0x00,0x00
+
+# W32: v_cmp_le_i32_e64 ttmp14, src_scc, vcc_lo  ; encoding: [0x7a,0x00,0x43,0xd4,0xfd,0xd4,0x00,0x00]
+# W64: v_cmp_le_i32_e64 ttmp[14:15], src_scc, vcc_lo ; encoding: [0x7a,0x00,0x43,0xd4,0xfd,0xd4,0x00,0x00]
+0x7a,0x00,0x43,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmp_le_i32_e64 null, 0xaf123456, vcc_hi ; encoding: [0x7c,0x00,0x43,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x43,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_le_i64_e64 s10, v[1:2], v[2:3]      ; encoding: [0x0a,0x00,0x53,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_le_i64_e64 s[10:11], v[1:2], v[2:3] ; encoding: [0x0a,0x00,0x53,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x53,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_le_i64_e64 s10, v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x53,0xd4,0xfe,0xfd,0x03,0x00]
+# W64: v_cmp_le_i64_e64 s[10:11], v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x53,0xd4,0xfe,0xfd,0x03,0x00]
+0x0a,0x00,0x53,0xd4,0xfe,0xfd,0x03,0x00
+
+# W32: v_cmp_le_i64_e64 s10, s[2:3], s[4:5]      ; encoding: [0x0a,0x00,0x53,0xd4,0x02,0x08,0x00,0x00]
+# W64: v_cmp_le_i64_e64 s[10:11], s[2:3], s[4:5] ; encoding: [0x0a,0x00,0x53,0xd4,0x02,0x08,0x00,0x00]
+0x0a,0x00,0x53,0xd4,0x02,0x08,0x00,0x00
+
+# W32: v_cmp_le_i64_e64 s10, s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x53,0xd4,0x68,0xd0,0x00,0x00]
+# W64: v_cmp_le_i64_e64 s[10:11], s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x53,0xd4,0x68,0xd0,0x00,0x00]
+0x0a,0x00,0x53,0xd4,0x68,0xd0,0x00,0x00
+
+# W32: v_cmp_le_i64_e64 s10, vcc, ttmp[14:15]    ; encoding: [0x0a,0x00,0x53,0xd4,0x6a,0xf4,0x00,0x00]
+# W64: v_cmp_le_i64_e64 s[10:11], vcc, ttmp[14:15] ; encoding: [0x0a,0x00,0x53,0xd4,0x6a,0xf4,0x00,0x00]
+0x0a,0x00,0x53,0xd4,0x6a,0xf4,0x00,0x00
+
+# W32: v_cmp_le_i64_e64 s10, ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x53,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_le_i64_e64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x53,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x53,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_le_i64_e64 s10, exec, src_scc       ; encoding: [0x0a,0x00,0x53,0xd4,0x7e,0xfa,0x01,0x00]
+# W64: v_cmp_le_i64_e64 s[10:11], exec, src_scc  ; encoding: [0x0a,0x00,0x53,0xd4,0x7e,0xfa,0x01,0x00]
+0x0a,0x00,0x53,0xd4,0x7e,0xfa,0x01,0x00
+
+# W32: v_cmp_le_i64_e64 s10, null, 0.5           ; encoding: [0x0a,0x00,0x53,0xd4,0x7c,0xe0,0x01,0x00]
+# W64: v_cmp_le_i64_e64 s[10:11], null, 0.5      ; encoding: [0x0a,0x00,0x53,0xd4,0x7c,0xe0,0x01,0x00]
+0x0a,0x00,0x53,0xd4,0x7c,0xe0,0x01,0x00
+
+# W32: v_cmp_le_i64_e64 s104, -1, -1             ; encoding: [0x68,0x00,0x53,0xd4,0xc1,0x82,0x01,0x00]
+# W64: v_cmp_le_i64_e64 s[104:105], -1, -1       ; encoding: [0x68,0x00,0x53,0xd4,0xc1,0x82,0x01,0x00]
+0x68,0x00,0x53,0xd4,0xc1,0x82,0x01,0x00
+
+# W32: v_cmp_le_i64_e64 vcc_lo, 0.5, null        ; encoding: [0x6a,0x00,0x53,0xd4,0xf0,0xf8,0x00,0x00]
+# W64: v_cmp_le_i64_e64 vcc, 0.5, null           ; encoding: [0x6a,0x00,0x53,0xd4,0xf0,0xf8,0x00,0x00]
+0x6a,0x00,0x53,0xd4,0xf0,0xf8,0x00,0x00
+
+# W32: v_cmp_le_i64_e64 ttmp14, src_scc, exec    ; encoding: [0x7a,0x00,0x53,0xd4,0xfd,0xfc,0x00,0x00]
+# W64: v_cmp_le_i64_e64 ttmp[14:15], src_scc, exec ; encoding: [0x7a,0x00,0x53,0xd4,0xfd,0xfc,0x00,0x00]
+0x7a,0x00,0x53,0xd4,0xfd,0xfc,0x00,0x00
+
+# GFX12: v_cmp_le_i64_e64 null, 0xaf123456, vcc  ; encoding: [0x7c,0x00,0x53,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x53,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_le_u16_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x3b,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_le_u16_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x3b,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x3b,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_le_u16_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x3b,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_le_u16_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x3b,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x3b,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_le_u16_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x3b,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_le_u16_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x3b,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x3b,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_le_u16_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x3b,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_le_u16_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x3b,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x3b,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_le_u16_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x3b,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_le_u16_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x3b,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x3b,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_le_u16_e64 s10, vcc_hi, 0xfe0b      ; encoding: [0x0a,0x00,0x3b,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_le_u16_e64 s[10:11], vcc_hi, 0xfe0b ; encoding: [0x0a,0x00,0x3b,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x0a,0x00,0x3b,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_le_u16_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x3b,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_le_u16_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x3b,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x3b,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_le_u16_e64 s10, m0, 0x3800          ; encoding: [0x0a,0x00,0x3b,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+# W64: v_cmp_le_u16_e64 s[10:11], m0, 0x3800     ; encoding: [0x0a,0x00,0x3b,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+0x0a,0x00,0x3b,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_le_u16_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x3b,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_le_u16_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x3b,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x3b,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_le_u16_e64 s10, exec_hi, null       ; encoding: [0x0a,0x00,0x3b,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_le_u16_e64 s[10:11], exec_hi, null  ; encoding: [0x0a,0x00,0x3b,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x00,0x3b,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_le_u16_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x3b,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_le_u16_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x3b,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x3b,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_le_u16_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x3b,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_le_u16_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x3b,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x3b,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_le_u16_e64 vcc_lo, 0x3800, m0       ; encoding: [0x6a,0x00,0x3b,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+# W64: v_cmp_le_u16_e64 vcc, 0x3800, m0          ; encoding: [0x6a,0x00,0x3b,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+0x6a,0x00,0x3b,0xd4,0xf0,0xfa,0x00,0x00
+
+# W32: v_cmp_le_u16_e64 ttmp14, src_scc, vcc_lo  ; encoding: [0x7a,0x00,0x3b,0xd4,0xfd,0xd4,0x00,0x00]
+# W64: v_cmp_le_u16_e64 ttmp[14:15], src_scc, vcc_lo ; encoding: [0x7a,0x00,0x3b,0xd4,0xfd,0xd4,0x00,0x00]
+0x7a,0x00,0x3b,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmp_le_u16_e64 null, 0xfe0b, vcc_hi   ; encoding: [0x7c,0x00,0x3b,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0x7c,0x00,0x3b,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_le_u32_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x4b,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_le_u32_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x4b,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x4b,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_le_u32_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x4b,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_le_u32_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x4b,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x4b,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_le_u32_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x4b,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_le_u32_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x4b,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x4b,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_le_u32_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x4b,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_le_u32_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x4b,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x4b,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_le_u32_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x4b,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_le_u32_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x4b,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x4b,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_le_u32_e64 s10, vcc_hi, 0xaf123456  ; encoding: [0x0a,0x00,0x4b,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_le_u32_e64 s[10:11], vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x4b,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x4b,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_le_u32_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x4b,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_le_u32_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x4b,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x4b,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_le_u32_e64 s10, m0, 0.5             ; encoding: [0x0a,0x00,0x4b,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_le_u32_e64 s[10:11], m0, 0.5        ; encoding: [0x0a,0x00,0x4b,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x4b,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_le_u32_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x4b,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_le_u32_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x4b,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x4b,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_le_u32_e64 s10, exec_hi, null       ; encoding: [0x0a,0x00,0x4b,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_le_u32_e64 s[10:11], exec_hi, null  ; encoding: [0x0a,0x00,0x4b,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x00,0x4b,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_le_u32_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x4b,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_le_u32_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x4b,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x4b,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_le_u32_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x4b,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_le_u32_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x4b,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x4b,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_le_u32_e64 vcc_lo, 0.5, m0          ; encoding: [0x6a,0x00,0x4b,0xd4,0xf0,0xfa,0x00,0x00]
+# W64: v_cmp_le_u32_e64 vcc, 0.5, m0             ; encoding: [0x6a,0x00,0x4b,0xd4,0xf0,0xfa,0x00,0x00]
+0x6a,0x00,0x4b,0xd4,0xf0,0xfa,0x00,0x00
+
+# W32: v_cmp_le_u32_e64 ttmp14, src_scc, vcc_lo  ; encoding: [0x7a,0x00,0x4b,0xd4,0xfd,0xd4,0x00,0x00]
+# W64: v_cmp_le_u32_e64 ttmp[14:15], src_scc, vcc_lo ; encoding: [0x7a,0x00,0x4b,0xd4,0xfd,0xd4,0x00,0x00]
+0x7a,0x00,0x4b,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmp_le_u32_e64 null, 0xaf123456, vcc_hi ; encoding: [0x7c,0x00,0x4b,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x4b,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_le_u64_e64 s10, v[1:2], v[2:3]      ; encoding: [0x0a,0x00,0x5b,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_le_u64_e64 s[10:11], v[1:2], v[2:3] ; encoding: [0x0a,0x00,0x5b,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x5b,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_le_u64_e64 s10, v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x5b,0xd4,0xfe,0xfd,0x03,0x00]
+# W64: v_cmp_le_u64_e64 s[10:11], v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x5b,0xd4,0xfe,0xfd,0x03,0x00]
+0x0a,0x00,0x5b,0xd4,0xfe,0xfd,0x03,0x00
+
+# W32: v_cmp_le_u64_e64 s10, s[2:3], s[4:5]      ; encoding: [0x0a,0x00,0x5b,0xd4,0x02,0x08,0x00,0x00]
+# W64: v_cmp_le_u64_e64 s[10:11], s[2:3], s[4:5] ; encoding: [0x0a,0x00,0x5b,0xd4,0x02,0x08,0x00,0x00]
+0x0a,0x00,0x5b,0xd4,0x02,0x08,0x00,0x00
+
+# W32: v_cmp_le_u64_e64 s10, s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x5b,0xd4,0x68,0xd0,0x00,0x00]
+# W64: v_cmp_le_u64_e64 s[10:11], s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x5b,0xd4,0x68,0xd0,0x00,0x00]
+0x0a,0x00,0x5b,0xd4,0x68,0xd0,0x00,0x00
+
+# W32: v_cmp_le_u64_e64 s10, vcc, ttmp[14:15]    ; encoding: [0x0a,0x00,0x5b,0xd4,0x6a,0xf4,0x00,0x00]
+# W64: v_cmp_le_u64_e64 s[10:11], vcc, ttmp[14:15] ; encoding: [0x0a,0x00,0x5b,0xd4,0x6a,0xf4,0x00,0x00]
+0x0a,0x00,0x5b,0xd4,0x6a,0xf4,0x00,0x00
+
+# W32: v_cmp_le_u64_e64 s10, ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x5b,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_le_u64_e64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x5b,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x5b,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_le_u64_e64 s10, exec, src_scc       ; encoding: [0x0a,0x00,0x5b,0xd4,0x7e,0xfa,0x01,0x00]
+# W64: v_cmp_le_u64_e64 s[10:11], exec, src_scc  ; encoding: [0x0a,0x00,0x5b,0xd4,0x7e,0xfa,0x01,0x00]
+0x0a,0x00,0x5b,0xd4,0x7e,0xfa,0x01,0x00
+
+# W32: v_cmp_le_u64_e64 s10, null, 0.5           ; encoding: [0x0a,0x00,0x5b,0xd4,0x7c,0xe0,0x01,0x00]
+# W64: v_cmp_le_u64_e64 s[10:11], null, 0.5      ; encoding: [0x0a,0x00,0x5b,0xd4,0x7c,0xe0,0x01,0x00]
+0x0a,0x00,0x5b,0xd4,0x7c,0xe0,0x01,0x00
+
+# W32: v_cmp_le_u64_e64 s104, -1, -1             ; encoding: [0x68,0x00,0x5b,0xd4,0xc1,0x82,0x01,0x00]
+# W64: v_cmp_le_u64_e64 s[104:105], -1, -1       ; encoding: [0x68,0x00,0x5b,0xd4,0xc1,0x82,0x01,0x00]
+0x68,0x00,0x5b,0xd4,0xc1,0x82,0x01,0x00
+
+# W32: v_cmp_le_u64_e64 vcc_lo, 0.5, null        ; encoding: [0x6a,0x00,0x5b,0xd4,0xf0,0xf8,0x00,0x00]
+# W64: v_cmp_le_u64_e64 vcc, 0.5, null           ; encoding: [0x6a,0x00,0x5b,0xd4,0xf0,0xf8,0x00,0x00]
+0x6a,0x00,0x5b,0xd4,0xf0,0xf8,0x00,0x00
+
+# W32: v_cmp_le_u64_e64 ttmp14, src_scc, exec    ; encoding: [0x7a,0x00,0x5b,0xd4,0xfd,0xfc,0x00,0x00]
+# W64: v_cmp_le_u64_e64 ttmp[14:15], src_scc, exec ; encoding: [0x7a,0x00,0x5b,0xd4,0xfd,0xfc,0x00,0x00]
+0x7a,0x00,0x5b,0xd4,0xfd,0xfc,0x00,0x00
+
+# GFX12: v_cmp_le_u64_e64 null, 0xaf123456, vcc  ; encoding: [0x7c,0x00,0x5b,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x5b,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_lg_f16_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x05,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_lg_f16_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x05,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x05,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_lg_f16_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x05,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_lg_f16_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x05,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x05,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_lg_f16_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x05,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_lg_f16_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x05,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x05,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_lg_f16_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x05,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_lg_f16_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x05,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x05,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_lg_f16_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x05,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_lg_f16_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x05,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x05,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_lg_f16_e64 s10, vcc_hi, 0xfe0b      ; encoding: [0x0a,0x00,0x05,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_lg_f16_e64 s[10:11], vcc_hi, 0xfe0b ; encoding: [0x0a,0x00,0x05,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x0a,0x00,0x05,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_lg_f16_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x05,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_lg_f16_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x05,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x05,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_lg_f16_e64 s10, m0, 0.5             ; encoding: [0x0a,0x00,0x05,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_lg_f16_e64 s[10:11], m0, 0.5        ; encoding: [0x0a,0x00,0x05,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x05,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_lg_f16_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x05,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_lg_f16_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x05,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x05,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_lg_f16_e64 s10, |exec_hi|, null     ; encoding: [0x0a,0x01,0x05,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_lg_f16_e64 s[10:11], |exec_hi|, null ; encoding: [0x0a,0x01,0x05,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x01,0x05,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_lg_f16_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x05,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_lg_f16_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x05,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x05,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_lg_f16_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x05,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_lg_f16_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x05,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x05,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_lg_f16_e64 vcc_lo, 0.5, -m0         ; encoding: [0x6a,0x00,0x05,0xd4,0xf0,0xfa,0x00,0x40]
+# W64: v_cmp_lg_f16_e64 vcc, 0.5, -m0            ; encoding: [0x6a,0x00,0x05,0xd4,0xf0,0xfa,0x00,0x40]
+0x6a,0x00,0x05,0xd4,0xf0,0xfa,0x00,0x40
+
+# W32: v_cmp_lg_f16_e64 ttmp14, -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x05,0xd4,0xfd,0xd4,0x00,0x20]
+# W64: v_cmp_lg_f16_e64 ttmp[14:15], -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x05,0xd4,0xfd,0xd4,0x00,0x20]
+0x7a,0x02,0x05,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmp_lg_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x05,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x7c,0x83,0x05,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_lg_f32_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x15,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_lg_f32_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x15,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x15,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_lg_f32_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x15,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_lg_f32_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x15,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x15,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_lg_f32_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x15,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_lg_f32_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x15,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x15,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_lg_f32_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x15,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_lg_f32_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x15,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x15,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_lg_f32_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x15,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_lg_f32_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x15,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x15,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_lg_f32_e64 s10, vcc_hi, 0xaf123456  ; encoding: [0x0a,0x00,0x15,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_lg_f32_e64 s[10:11], vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x15,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x15,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_lg_f32_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x15,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_lg_f32_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x15,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x15,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_lg_f32_e64 s10, m0, 0.5             ; encoding: [0x0a,0x00,0x15,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_lg_f32_e64 s[10:11], m0, 0.5        ; encoding: [0x0a,0x00,0x15,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x15,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_lg_f32_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x15,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_lg_f32_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x15,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x15,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_lg_f32_e64 s10, |exec_hi|, null     ; encoding: [0x0a,0x01,0x15,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_lg_f32_e64 s[10:11], |exec_hi|, null ; encoding: [0x0a,0x01,0x15,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x01,0x15,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_lg_f32_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x15,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_lg_f32_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x15,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x15,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_lg_f32_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x15,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_lg_f32_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x15,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x15,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_lg_f32_e64 vcc_lo, 0.5, -m0         ; encoding: [0x6a,0x00,0x15,0xd4,0xf0,0xfa,0x00,0x40]
+# W64: v_cmp_lg_f32_e64 vcc, 0.5, -m0            ; encoding: [0x6a,0x00,0x15,0xd4,0xf0,0xfa,0x00,0x40]
+0x6a,0x00,0x15,0xd4,0xf0,0xfa,0x00,0x40
+
+# W32: v_cmp_lg_f32_e64 ttmp14, -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x15,0xd4,0xfd,0xd4,0x00,0x20]
+# W64: v_cmp_lg_f32_e64 ttmp[14:15], -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x15,0xd4,0xfd,0xd4,0x00,0x20]
+0x7a,0x02,0x15,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmp_lg_f32_e64 null, -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x15,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0x7c,0x83,0x15,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_lg_f64_e64 s10, v[1:2], v[2:3]      ; encoding: [0x0a,0x00,0x25,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_lg_f64_e64 s[10:11], v[1:2], v[2:3] ; encoding: [0x0a,0x00,0x25,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x25,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_lg_f64_e64 s10, v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x25,0xd4,0xfe,0xfd,0x03,0x00]
+# W64: v_cmp_lg_f64_e64 s[10:11], v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x25,0xd4,0xfe,0xfd,0x03,0x00]
+0x0a,0x00,0x25,0xd4,0xfe,0xfd,0x03,0x00
+
+# W32: v_cmp_lg_f64_e64 s10, s[2:3], s[4:5]      ; encoding: [0x0a,0x00,0x25,0xd4,0x02,0x08,0x00,0x00]
+# W64: v_cmp_lg_f64_e64 s[10:11], s[2:3], s[4:5] ; encoding: [0x0a,0x00,0x25,0xd4,0x02,0x08,0x00,0x00]
+0x0a,0x00,0x25,0xd4,0x02,0x08,0x00,0x00
+
+# W32: v_cmp_lg_f64_e64 s10, s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x25,0xd4,0x68,0xd0,0x00,0x00]
+# W64: v_cmp_lg_f64_e64 s[10:11], s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x25,0xd4,0x68,0xd0,0x00,0x00]
+0x0a,0x00,0x25,0xd4,0x68,0xd0,0x00,0x00
+
+# W32: v_cmp_lg_f64_e64 s10, vcc, ttmp[14:15]    ; encoding: [0x0a,0x00,0x25,0xd4,0x6a,0xf4,0x00,0x00]
+# W64: v_cmp_lg_f64_e64 s[10:11], vcc, ttmp[14:15] ; encoding: [0x0a,0x00,0x25,0xd4,0x6a,0xf4,0x00,0x00]
+0x0a,0x00,0x25,0xd4,0x6a,0xf4,0x00,0x00
+
+# W32: v_cmp_lg_f64_e64 s10, ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x25,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_lg_f64_e64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x25,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x25,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_lg_f64_e64 s10, -|exec|, src_scc    ; encoding: [0x0a,0x01,0x25,0xd4,0x7e,0xfa,0x01,0x20]
+# W64: v_cmp_lg_f64_e64 s[10:11], -|exec|, src_scc ; encoding: [0x0a,0x01,0x25,0xd4,0x7e,0xfa,0x01,0x20]
+0x0a,0x01,0x25,0xd4,0x7e,0xfa,0x01,0x20
+
+# W32: v_cmp_lg_f64_e64 s10, null, 0.5           ; encoding: [0x0a,0x00,0x25,0xd4,0x7c,0xe0,0x01,0x00]
+# W64: v_cmp_lg_f64_e64 s[10:11], null, 0.5      ; encoding: [0x0a,0x00,0x25,0xd4,0x7c,0xe0,0x01,0x00]
+0x0a,0x00,0x25,0xd4,0x7c,0xe0,0x01,0x00
+
+# W32: v_cmp_lg_f64_e64 s104, -1, -1             ; encoding: [0x68,0x00,0x25,0xd4,0xc1,0x82,0x01,0x00]
+# W64: v_cmp_lg_f64_e64 s[104:105], -1, -1       ; encoding: [0x68,0x00,0x25,0xd4,0xc1,0x82,0x01,0x00]
+0x68,0x00,0x25,0xd4,0xc1,0x82,0x01,0x00
+
+# W32: v_cmp_lg_f64_e64 vcc_lo, 0.5, null        ; encoding: [0x6a,0x00,0x25,0xd4,0xf0,0xf8,0x00,0x00]
+# W64: v_cmp_lg_f64_e64 vcc, 0.5, null           ; encoding: [0x6a,0x00,0x25,0xd4,0xf0,0xf8,0x00,0x00]
+0x6a,0x00,0x25,0xd4,0xf0,0xf8,0x00,0x00
+
+# W32: v_cmp_lg_f64_e64 ttmp14, -|src_scc|, -|exec| ; encoding: [0x7a,0x03,0x25,0xd4,0xfd,0xfc,0x00,0x60]
+# W64: v_cmp_lg_f64_e64 ttmp[14:15], -|src_scc|, -|exec| ; encoding: [0x7a,0x03,0x25,0xd4,0xfd,0xfc,0x00,0x60]
+0x7a,0x03,0x25,0xd4,0xfd,0xfc,0x00,0x60
+
+# GFX12: v_cmp_lg_f64_e64 null, 0xaf123456, -|vcc| clamp ; encoding: [0x7c,0x82,0x25,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+0x7c,0x82,0x25,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_lt_f16_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_lt_f16_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_lt_f16_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x01,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_lt_f16_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x01,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x01,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_lt_f16_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x01,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_lt_f16_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x01,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x01,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_lt_f16_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x01,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_lt_f16_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x01,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x01,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_lt_f16_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x01,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_lt_f16_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x01,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x01,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_lt_f16_e64 s10, vcc_hi, 0xfe0b      ; encoding: [0x0a,0x00,0x01,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_lt_f16_e64 s[10:11], vcc_hi, 0xfe0b ; encoding: [0x0a,0x00,0x01,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x0a,0x00,0x01,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_lt_f16_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x01,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_lt_f16_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x01,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x01,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_lt_f16_e64 s10, m0, 0.5             ; encoding: [0x0a,0x00,0x01,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_lt_f16_e64 s[10:11], m0, 0.5        ; encoding: [0x0a,0x00,0x01,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x01,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_lt_f16_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x01,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_lt_f16_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x01,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x01,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_lt_f16_e64 s10, |exec_hi|, null     ; encoding: [0x0a,0x01,0x01,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_lt_f16_e64 s[10:11], |exec_hi|, null ; encoding: [0x0a,0x01,0x01,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x01,0x01,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_lt_f16_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x01,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_lt_f16_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x01,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x01,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_lt_f16_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x01,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_lt_f16_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x01,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x01,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_lt_f16_e64 vcc_lo, 0.5, -m0         ; encoding: [0x6a,0x00,0x01,0xd4,0xf0,0xfa,0x00,0x40]
+# W64: v_cmp_lt_f16_e64 vcc, 0.5, -m0            ; encoding: [0x6a,0x00,0x01,0xd4,0xf0,0xfa,0x00,0x40]
+0x6a,0x00,0x01,0xd4,0xf0,0xfa,0x00,0x40
+
+# W32: v_cmp_lt_f16_e64 ttmp14, -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x01,0xd4,0xfd,0xd4,0x00,0x20]
+# W64: v_cmp_lt_f16_e64 ttmp[14:15], -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x01,0xd4,0xfd,0xd4,0x00,0x20]
+0x7a,0x02,0x01,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmp_lt_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x01,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x7c,0x83,0x01,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_lt_f32_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x11,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_lt_f32_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x11,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x11,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_lt_f32_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x11,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_lt_f32_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x11,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x11,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_lt_f32_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x11,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_lt_f32_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x11,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x11,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_lt_f32_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x11,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_lt_f32_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x11,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x11,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_lt_f32_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x11,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_lt_f32_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x11,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x11,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_lt_f32_e64 s10, vcc_hi, 0xaf123456  ; encoding: [0x0a,0x00,0x11,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_lt_f32_e64 s[10:11], vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x11,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x11,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_lt_f32_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x11,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_lt_f32_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x11,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x11,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_lt_f32_e64 s10, m0, 0.5             ; encoding: [0x0a,0x00,0x11,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_lt_f32_e64 s[10:11], m0, 0.5        ; encoding: [0x0a,0x00,0x11,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x11,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_lt_f32_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x11,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_lt_f32_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x11,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x11,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_lt_f32_e64 s10, |exec_hi|, null     ; encoding: [0x0a,0x01,0x11,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_lt_f32_e64 s[10:11], |exec_hi|, null ; encoding: [0x0a,0x01,0x11,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x01,0x11,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_lt_f32_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x11,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_lt_f32_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x11,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x11,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_lt_f32_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x11,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_lt_f32_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x11,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x11,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_lt_f32_e64 vcc_lo, 0.5, -m0         ; encoding: [0x6a,0x00,0x11,0xd4,0xf0,0xfa,0x00,0x40]
+# W64: v_cmp_lt_f32_e64 vcc, 0.5, -m0            ; encoding: [0x6a,0x00,0x11,0xd4,0xf0,0xfa,0x00,0x40]
+0x6a,0x00,0x11,0xd4,0xf0,0xfa,0x00,0x40
+
+# W32: v_cmp_lt_f32_e64 ttmp14, -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x11,0xd4,0xfd,0xd4,0x00,0x20]
+# W64: v_cmp_lt_f32_e64 ttmp[14:15], -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x11,0xd4,0xfd,0xd4,0x00,0x20]
+0x7a,0x02,0x11,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmp_lt_f32_e64 null, -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x11,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0x7c,0x83,0x11,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_lt_f64_e64 s10, v[1:2], v[2:3]      ; encoding: [0x0a,0x00,0x21,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_lt_f64_e64 s[10:11], v[1:2], v[2:3] ; encoding: [0x0a,0x00,0x21,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x21,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_lt_f64_e64 s10, v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x21,0xd4,0xfe,0xfd,0x03,0x00]
+# W64: v_cmp_lt_f64_e64 s[10:11], v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x21,0xd4,0xfe,0xfd,0x03,0x00]
+0x0a,0x00,0x21,0xd4,0xfe,0xfd,0x03,0x00
+
+# W32: v_cmp_lt_f64_e64 s10, s[2:3], s[4:5]      ; encoding: [0x0a,0x00,0x21,0xd4,0x02,0x08,0x00,0x00]
+# W64: v_cmp_lt_f64_e64 s[10:11], s[2:3], s[4:5] ; encoding: [0x0a,0x00,0x21,0xd4,0x02,0x08,0x00,0x00]
+0x0a,0x00,0x21,0xd4,0x02,0x08,0x00,0x00
+
+# W32: v_cmp_lt_f64_e64 s10, s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x21,0xd4,0x68,0xd0,0x00,0x00]
+# W64: v_cmp_lt_f64_e64 s[10:11], s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x21,0xd4,0x68,0xd0,0x00,0x00]
+0x0a,0x00,0x21,0xd4,0x68,0xd0,0x00,0x00
+
+# W32: v_cmp_lt_f64_e64 s10, vcc, ttmp[14:15]    ; encoding: [0x0a,0x00,0x21,0xd4,0x6a,0xf4,0x00,0x00]
+# W64: v_cmp_lt_f64_e64 s[10:11], vcc, ttmp[14:15] ; encoding: [0x0a,0x00,0x21,0xd4,0x6a,0xf4,0x00,0x00]
+0x0a,0x00,0x21,0xd4,0x6a,0xf4,0x00,0x00
+
+# W32: v_cmp_lt_f64_e64 s10, ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x21,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_lt_f64_e64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x21,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x21,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_lt_f64_e64 s10, -|exec|, src_scc    ; encoding: [0x0a,0x01,0x21,0xd4,0x7e,0xfa,0x01,0x20]
+# W64: v_cmp_lt_f64_e64 s[10:11], -|exec|, src_scc ; encoding: [0x0a,0x01,0x21,0xd4,0x7e,0xfa,0x01,0x20]
+0x0a,0x01,0x21,0xd4,0x7e,0xfa,0x01,0x20
+
+# W32: v_cmp_lt_f64_e64 s10, null, 0.5           ; encoding: [0x0a,0x00,0x21,0xd4,0x7c,0xe0,0x01,0x00]
+# W64: v_cmp_lt_f64_e64 s[10:11], null, 0.5      ; encoding: [0x0a,0x00,0x21,0xd4,0x7c,0xe0,0x01,0x00]
+0x0a,0x00,0x21,0xd4,0x7c,0xe0,0x01,0x00
+
+# W32: v_cmp_lt_f64_e64 s104, -1, -1             ; encoding: [0x68,0x00,0x21,0xd4,0xc1,0x82,0x01,0x00]
+# W64: v_cmp_lt_f64_e64 s[104:105], -1, -1       ; encoding: [0x68,0x00,0x21,0xd4,0xc1,0x82,0x01,0x00]
+0x68,0x00,0x21,0xd4,0xc1,0x82,0x01,0x00
+
+# W32: v_cmp_lt_f64_e64 vcc_lo, 0.5, null        ; encoding: [0x6a,0x00,0x21,0xd4,0xf0,0xf8,0x00,0x00]
+# W64: v_cmp_lt_f64_e64 vcc, 0.5, null           ; encoding: [0x6a,0x00,0x21,0xd4,0xf0,0xf8,0x00,0x00]
+0x6a,0x00,0x21,0xd4,0xf0,0xf8,0x00,0x00
+
+# W32: v_cmp_lt_f64_e64 ttmp14, -|src_scc|, -|exec| ; encoding: [0x7a,0x03,0x21,0xd4,0xfd,0xfc,0x00,0x60]
+# W64: v_cmp_lt_f64_e64 ttmp[14:15], -|src_scc|, -|exec| ; encoding: [0x7a,0x03,0x21,0xd4,0xfd,0xfc,0x00,0x60]
+0x7a,0x03,0x21,0xd4,0xfd,0xfc,0x00,0x60
+
+# GFX12: v_cmp_lt_f64_e64 null, 0xaf123456, -|vcc| clamp ; encoding: [0x7c,0x82,0x21,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+0x7c,0x82,0x21,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_lt_i16_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x31,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_lt_i16_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x31,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x31,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_lt_i16_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x31,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_lt_i16_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x31,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x31,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_lt_i16_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x31,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_lt_i16_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x31,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x31,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_lt_i16_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x31,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_lt_i16_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x31,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x31,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_lt_i16_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x31,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_lt_i16_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x31,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x31,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_lt_i16_e64 s10, vcc_hi, 0xfe0b      ; encoding: [0x0a,0x00,0x31,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_lt_i16_e64 s[10:11], vcc_hi, 0xfe0b ; encoding: [0x0a,0x00,0x31,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x0a,0x00,0x31,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_lt_i16_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x31,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_lt_i16_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x31,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x31,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_lt_i16_e64 s10, m0, 0x3800          ; encoding: [0x0a,0x00,0x31,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+# W64: v_cmp_lt_i16_e64 s[10:11], m0, 0x3800     ; encoding: [0x0a,0x00,0x31,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+0x0a,0x00,0x31,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_lt_i16_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x31,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_lt_i16_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x31,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x31,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_lt_i16_e64 s10, exec_hi, null       ; encoding: [0x0a,0x00,0x31,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_lt_i16_e64 s[10:11], exec_hi, null  ; encoding: [0x0a,0x00,0x31,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x00,0x31,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_lt_i16_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x31,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_lt_i16_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x31,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x31,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_lt_i16_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x31,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_lt_i16_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x31,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x31,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_lt_i16_e64 vcc_lo, 0x3800, m0       ; encoding: [0x6a,0x00,0x31,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+# W64: v_cmp_lt_i16_e64 vcc, 0x3800, m0          ; encoding: [0x6a,0x00,0x31,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+0x6a,0x00,0x31,0xd4,0xf0,0xfa,0x00,0x00
+
+# W32: v_cmp_lt_i16_e64 ttmp14, src_scc, vcc_lo  ; encoding: [0x7a,0x00,0x31,0xd4,0xfd,0xd4,0x00,0x00]
+# W64: v_cmp_lt_i16_e64 ttmp[14:15], src_scc, vcc_lo ; encoding: [0x7a,0x00,0x31,0xd4,0xfd,0xd4,0x00,0x00]
+0x7a,0x00,0x31,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmp_lt_i16_e64 null, 0xfe0b, vcc_hi   ; encoding: [0x7c,0x00,0x31,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0x7c,0x00,0x31,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_lt_i32_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x41,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_lt_i32_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x41,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x41,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_lt_i32_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x41,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_lt_i32_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x41,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x41,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_lt_i32_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x41,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_lt_i32_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x41,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x41,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_lt_i32_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x41,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_lt_i32_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x41,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x41,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_lt_i32_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x41,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_lt_i32_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x41,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x41,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_lt_i32_e64 s10, vcc_hi, 0xaf123456  ; encoding: [0x0a,0x00,0x41,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_lt_i32_e64 s[10:11], vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x41,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x41,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_lt_i32_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x41,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_lt_i32_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x41,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x41,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_lt_i32_e64 s10, m0, 0.5             ; encoding: [0x0a,0x00,0x41,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_lt_i32_e64 s[10:11], m0, 0.5        ; encoding: [0x0a,0x00,0x41,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x41,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_lt_i32_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x41,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_lt_i32_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x41,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x41,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_lt_i32_e64 s10, exec_hi, null       ; encoding: [0x0a,0x00,0x41,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_lt_i32_e64 s[10:11], exec_hi, null  ; encoding: [0x0a,0x00,0x41,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x00,0x41,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_lt_i32_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x41,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_lt_i32_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x41,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x41,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_lt_i32_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x41,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_lt_i32_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x41,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x41,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_lt_i32_e64 vcc_lo, 0.5, m0          ; encoding: [0x6a,0x00,0x41,0xd4,0xf0,0xfa,0x00,0x00]
+# W64: v_cmp_lt_i32_e64 vcc, 0.5, m0             ; encoding: [0x6a,0x00,0x41,0xd4,0xf0,0xfa,0x00,0x00]
+0x6a,0x00,0x41,0xd4,0xf0,0xfa,0x00,0x00
+
+# W32: v_cmp_lt_i32_e64 ttmp14, src_scc, vcc_lo  ; encoding: [0x7a,0x00,0x41,0xd4,0xfd,0xd4,0x00,0x00]
+# W64: v_cmp_lt_i32_e64 ttmp[14:15], src_scc, vcc_lo ; encoding: [0x7a,0x00,0x41,0xd4,0xfd,0xd4,0x00,0x00]
+0x7a,0x00,0x41,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmp_lt_i32_e64 null, 0xaf123456, vcc_hi ; encoding: [0x7c,0x00,0x41,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x41,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_lt_i64_e64 s10, v[1:2], v[2:3]      ; encoding: [0x0a,0x00,0x51,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_lt_i64_e64 s[10:11], v[1:2], v[2:3] ; encoding: [0x0a,0x00,0x51,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x51,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_lt_i64_e64 s10, v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x51,0xd4,0xfe,0xfd,0x03,0x00]
+# W64: v_cmp_lt_i64_e64 s[10:11], v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x51,0xd4,0xfe,0xfd,0x03,0x00]
+0x0a,0x00,0x51,0xd4,0xfe,0xfd,0x03,0x00
+
+# W32: v_cmp_lt_i64_e64 s10, s[2:3], s[4:5]      ; encoding: [0x0a,0x00,0x51,0xd4,0x02,0x08,0x00,0x00]
+# W64: v_cmp_lt_i64_e64 s[10:11], s[2:3], s[4:5] ; encoding: [0x0a,0x00,0x51,0xd4,0x02,0x08,0x00,0x00]
+0x0a,0x00,0x51,0xd4,0x02,0x08,0x00,0x00
+
+# W32: v_cmp_lt_i64_e64 s10, s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x51,0xd4,0x68,0xd0,0x00,0x00]
+# W64: v_cmp_lt_i64_e64 s[10:11], s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x51,0xd4,0x68,0xd0,0x00,0x00]
+0x0a,0x00,0x51,0xd4,0x68,0xd0,0x00,0x00
+
+# W32: v_cmp_lt_i64_e64 s10, vcc, ttmp[14:15]    ; encoding: [0x0a,0x00,0x51,0xd4,0x6a,0xf4,0x00,0x00]
+# W64: v_cmp_lt_i64_e64 s[10:11], vcc, ttmp[14:15] ; encoding: [0x0a,0x00,0x51,0xd4,0x6a,0xf4,0x00,0x00]
+0x0a,0x00,0x51,0xd4,0x6a,0xf4,0x00,0x00
+
+# W32: v_cmp_lt_i64_e64 s10, ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x51,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_lt_i64_e64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x51,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x51,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_lt_i64_e64 s10, exec, src_scc       ; encoding: [0x0a,0x00,0x51,0xd4,0x7e,0xfa,0x01,0x00]
+# W64: v_cmp_lt_i64_e64 s[10:11], exec, src_scc  ; encoding: [0x0a,0x00,0x51,0xd4,0x7e,0xfa,0x01,0x00]
+0x0a,0x00,0x51,0xd4,0x7e,0xfa,0x01,0x00
+
+# W32: v_cmp_lt_i64_e64 s10, null, 0.5           ; encoding: [0x0a,0x00,0x51,0xd4,0x7c,0xe0,0x01,0x00]
+# W64: v_cmp_lt_i64_e64 s[10:11], null, 0.5      ; encoding: [0x0a,0x00,0x51,0xd4,0x7c,0xe0,0x01,0x00]
+0x0a,0x00,0x51,0xd4,0x7c,0xe0,0x01,0x00
+
+# W32: v_cmp_lt_i64_e64 s104, -1, -1             ; encoding: [0x68,0x00,0x51,0xd4,0xc1,0x82,0x01,0x00]
+# W64: v_cmp_lt_i64_e64 s[104:105], -1, -1       ; encoding: [0x68,0x00,0x51,0xd4,0xc1,0x82,0x01,0x00]
+0x68,0x00,0x51,0xd4,0xc1,0x82,0x01,0x00
+
+# W32: v_cmp_lt_i64_e64 vcc_lo, 0.5, null        ; encoding: [0x6a,0x00,0x51,0xd4,0xf0,0xf8,0x00,0x00]
+# W64: v_cmp_lt_i64_e64 vcc, 0.5, null           ; encoding: [0x6a,0x00,0x51,0xd4,0xf0,0xf8,0x00,0x00]
+0x6a,0x00,0x51,0xd4,0xf0,0xf8,0x00,0x00
+
+# W32: v_cmp_lt_i64_e64 ttmp14, src_scc, exec    ; encoding: [0x7a,0x00,0x51,0xd4,0xfd,0xfc,0x00,0x00]
+# W64: v_cmp_lt_i64_e64 ttmp[14:15], src_scc, exec ; encoding: [0x7a,0x00,0x51,0xd4,0xfd,0xfc,0x00,0x00]
+0x7a,0x00,0x51,0xd4,0xfd,0xfc,0x00,0x00
+
+# GFX12: v_cmp_lt_i64_e64 null, 0xaf123456, vcc  ; encoding: [0x7c,0x00,0x51,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x51,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_lt_u16_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x39,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_lt_u16_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x39,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x39,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_lt_u16_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x39,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_lt_u16_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x39,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x39,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_lt_u16_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x39,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_lt_u16_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x39,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x39,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_lt_u16_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x39,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_lt_u16_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x39,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x39,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_lt_u16_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x39,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_lt_u16_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x39,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x39,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_lt_u16_e64 s10, vcc_hi, 0xfe0b      ; encoding: [0x0a,0x00,0x39,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_lt_u16_e64 s[10:11], vcc_hi, 0xfe0b ; encoding: [0x0a,0x00,0x39,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x0a,0x00,0x39,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_lt_u16_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x39,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_lt_u16_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x39,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x39,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_lt_u16_e64 s10, m0, 0x3800          ; encoding: [0x0a,0x00,0x39,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+# W64: v_cmp_lt_u16_e64 s[10:11], m0, 0x3800     ; encoding: [0x0a,0x00,0x39,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+0x0a,0x00,0x39,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_lt_u16_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x39,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_lt_u16_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x39,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x39,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_lt_u16_e64 s10, exec_hi, null       ; encoding: [0x0a,0x00,0x39,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_lt_u16_e64 s[10:11], exec_hi, null  ; encoding: [0x0a,0x00,0x39,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x00,0x39,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_lt_u16_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x39,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_lt_u16_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x39,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x39,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_lt_u16_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x39,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_lt_u16_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x39,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x39,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_lt_u16_e64 vcc_lo, 0x3800, m0       ; encoding: [0x6a,0x00,0x39,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+# W64: v_cmp_lt_u16_e64 vcc, 0x3800, m0          ; encoding: [0x6a,0x00,0x39,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+0x6a,0x00,0x39,0xd4,0xf0,0xfa,0x00,0x00
+
+# W32: v_cmp_lt_u16_e64 ttmp14, src_scc, vcc_lo  ; encoding: [0x7a,0x00,0x39,0xd4,0xfd,0xd4,0x00,0x00]
+# W64: v_cmp_lt_u16_e64 ttmp[14:15], src_scc, vcc_lo ; encoding: [0x7a,0x00,0x39,0xd4,0xfd,0xd4,0x00,0x00]
+0x7a,0x00,0x39,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmp_lt_u16_e64 null, 0xfe0b, vcc_hi   ; encoding: [0x7c,0x00,0x39,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0x7c,0x00,0x39,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_lt_u32_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x49,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_lt_u32_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x49,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x49,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_lt_u32_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x49,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_lt_u32_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x49,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x49,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_lt_u32_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x49,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_lt_u32_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x49,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x49,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_lt_u32_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x49,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_lt_u32_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x49,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x49,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_lt_u32_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x49,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_lt_u32_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x49,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x49,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_lt_u32_e64 s10, vcc_hi, 0xaf123456  ; encoding: [0x0a,0x00,0x49,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_lt_u32_e64 s[10:11], vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x49,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x49,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_lt_u32_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x49,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_lt_u32_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x49,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x49,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_lt_u32_e64 s10, m0, 0.5             ; encoding: [0x0a,0x00,0x49,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_lt_u32_e64 s[10:11], m0, 0.5        ; encoding: [0x0a,0x00,0x49,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x49,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_lt_u32_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x49,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_lt_u32_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x49,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x49,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_lt_u32_e64 s10, exec_hi, null       ; encoding: [0x0a,0x00,0x49,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_lt_u32_e64 s[10:11], exec_hi, null  ; encoding: [0x0a,0x00,0x49,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x00,0x49,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_lt_u32_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x49,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_lt_u32_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x49,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x49,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_lt_u32_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x49,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_lt_u32_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x49,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x49,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_lt_u32_e64 vcc_lo, 0.5, m0          ; encoding: [0x6a,0x00,0x49,0xd4,0xf0,0xfa,0x00,0x00]
+# W64: v_cmp_lt_u32_e64 vcc, 0.5, m0             ; encoding: [0x6a,0x00,0x49,0xd4,0xf0,0xfa,0x00,0x00]
+0x6a,0x00,0x49,0xd4,0xf0,0xfa,0x00,0x00
+
+# W32: v_cmp_lt_u32_e64 ttmp14, src_scc, vcc_lo  ; encoding: [0x7a,0x00,0x49,0xd4,0xfd,0xd4,0x00,0x00]
+# W64: v_cmp_lt_u32_e64 ttmp[14:15], src_scc, vcc_lo ; encoding: [0x7a,0x00,0x49,0xd4,0xfd,0xd4,0x00,0x00]
+0x7a,0x00,0x49,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmp_lt_u32_e64 null, 0xaf123456, vcc_hi ; encoding: [0x7c,0x00,0x49,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x49,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_lt_u64_e64 s10, v[1:2], v[2:3]      ; encoding: [0x0a,0x00,0x59,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_lt_u64_e64 s[10:11], v[1:2], v[2:3] ; encoding: [0x0a,0x00,0x59,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x59,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_lt_u64_e64 s10, v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x59,0xd4,0xfe,0xfd,0x03,0x00]
+# W64: v_cmp_lt_u64_e64 s[10:11], v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x59,0xd4,0xfe,0xfd,0x03,0x00]
+0x0a,0x00,0x59,0xd4,0xfe,0xfd,0x03,0x00
+
+# W32: v_cmp_lt_u64_e64 s10, s[2:3], s[4:5]      ; encoding: [0x0a,0x00,0x59,0xd4,0x02,0x08,0x00,0x00]
+# W64: v_cmp_lt_u64_e64 s[10:11], s[2:3], s[4:5] ; encoding: [0x0a,0x00,0x59,0xd4,0x02,0x08,0x00,0x00]
+0x0a,0x00,0x59,0xd4,0x02,0x08,0x00,0x00
+
+# W32: v_cmp_lt_u64_e64 s10, s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x59,0xd4,0x68,0xd0,0x00,0x00]
+# W64: v_cmp_lt_u64_e64 s[10:11], s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x59,0xd4,0x68,0xd0,0x00,0x00]
+0x0a,0x00,0x59,0xd4,0x68,0xd0,0x00,0x00
+
+# W32: v_cmp_lt_u64_e64 s10, vcc, ttmp[14:15]    ; encoding: [0x0a,0x00,0x59,0xd4,0x6a,0xf4,0x00,0x00]
+# W64: v_cmp_lt_u64_e64 s[10:11], vcc, ttmp[14:15] ; encoding: [0x0a,0x00,0x59,0xd4,0x6a,0xf4,0x00,0x00]
+0x0a,0x00,0x59,0xd4,0x6a,0xf4,0x00,0x00
+
+# W32: v_cmp_lt_u64_e64 s10, ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x59,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_lt_u64_e64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x59,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x59,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_lt_u64_e64 s10, exec, src_scc       ; encoding: [0x0a,0x00,0x59,0xd4,0x7e,0xfa,0x01,0x00]
+# W64: v_cmp_lt_u64_e64 s[10:11], exec, src_scc  ; encoding: [0x0a,0x00,0x59,0xd4,0x7e,0xfa,0x01,0x00]
+0x0a,0x00,0x59,0xd4,0x7e,0xfa,0x01,0x00
+
+# W32: v_cmp_lt_u64_e64 s10, null, 0.5           ; encoding: [0x0a,0x00,0x59,0xd4,0x7c,0xe0,0x01,0x00]
+# W64: v_cmp_lt_u64_e64 s[10:11], null, 0.5      ; encoding: [0x0a,0x00,0x59,0xd4,0x7c,0xe0,0x01,0x00]
+0x0a,0x00,0x59,0xd4,0x7c,0xe0,0x01,0x00
+
+# W32: v_cmp_lt_u64_e64 s104, -1, -1             ; encoding: [0x68,0x00,0x59,0xd4,0xc1,0x82,0x01,0x00]
+# W64: v_cmp_lt_u64_e64 s[104:105], -1, -1       ; encoding: [0x68,0x00,0x59,0xd4,0xc1,0x82,0x01,0x00]
+0x68,0x00,0x59,0xd4,0xc1,0x82,0x01,0x00
+
+# W32: v_cmp_lt_u64_e64 vcc_lo, 0.5, null        ; encoding: [0x6a,0x00,0x59,0xd4,0xf0,0xf8,0x00,0x00]
+# W64: v_cmp_lt_u64_e64 vcc, 0.5, null           ; encoding: [0x6a,0x00,0x59,0xd4,0xf0,0xf8,0x00,0x00]
+0x6a,0x00,0x59,0xd4,0xf0,0xf8,0x00,0x00
+
+# W32: v_cmp_lt_u64_e64 ttmp14, src_scc, exec    ; encoding: [0x7a,0x00,0x59,0xd4,0xfd,0xfc,0x00,0x00]
+# W64: v_cmp_lt_u64_e64 ttmp[14:15], src_scc, exec ; encoding: [0x7a,0x00,0x59,0xd4,0xfd,0xfc,0x00,0x00]
+0x7a,0x00,0x59,0xd4,0xfd,0xfc,0x00,0x00
+
+# GFX12: v_cmp_lt_u64_e64 null, 0xaf123456, vcc  ; encoding: [0x7c,0x00,0x59,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x59,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ne_i16_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x35,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_ne_i16_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x35,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x35,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_ne_i16_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x35,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_ne_i16_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x35,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x35,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_ne_i16_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x35,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_ne_i16_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x35,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x35,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_ne_i16_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x35,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_ne_i16_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x35,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x35,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_ne_i16_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x35,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_ne_i16_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x35,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x35,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_ne_i16_e64 s10, vcc_hi, 0xfe0b      ; encoding: [0x0a,0x00,0x35,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_ne_i16_e64 s[10:11], vcc_hi, 0xfe0b ; encoding: [0x0a,0x00,0x35,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x0a,0x00,0x35,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_ne_i16_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x35,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_ne_i16_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x35,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x35,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_ne_i16_e64 s10, m0, 0x3800          ; encoding: [0x0a,0x00,0x35,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+# W64: v_cmp_ne_i16_e64 s[10:11], m0, 0x3800     ; encoding: [0x0a,0x00,0x35,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+0x0a,0x00,0x35,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_ne_i16_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x35,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_ne_i16_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x35,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x35,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_ne_i16_e64 s10, exec_hi, null       ; encoding: [0x0a,0x00,0x35,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_ne_i16_e64 s[10:11], exec_hi, null  ; encoding: [0x0a,0x00,0x35,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x00,0x35,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_ne_i16_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x35,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_ne_i16_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x35,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x35,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_ne_i16_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x35,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_ne_i16_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x35,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x35,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_ne_i16_e64 vcc_lo, 0x3800, m0       ; encoding: [0x6a,0x00,0x35,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+# W64: v_cmp_ne_i16_e64 vcc, 0x3800, m0          ; encoding: [0x6a,0x00,0x35,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+0x6a,0x00,0x35,0xd4,0xf0,0xfa,0x00,0x00
+
+# W32: v_cmp_ne_i16_e64 ttmp14, src_scc, vcc_lo  ; encoding: [0x7a,0x00,0x35,0xd4,0xfd,0xd4,0x00,0x00]
+# W64: v_cmp_ne_i16_e64 ttmp[14:15], src_scc, vcc_lo ; encoding: [0x7a,0x00,0x35,0xd4,0xfd,0xd4,0x00,0x00]
+0x7a,0x00,0x35,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmp_ne_i16_e64 null, 0xfe0b, vcc_hi   ; encoding: [0x7c,0x00,0x35,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0x7c,0x00,0x35,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_ne_i32_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x45,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_ne_i32_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x45,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x45,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_ne_i32_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x45,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_ne_i32_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x45,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x45,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_ne_i32_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x45,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_ne_i32_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x45,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x45,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_ne_i32_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x45,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_ne_i32_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x45,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x45,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_ne_i32_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x45,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_ne_i32_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x45,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x45,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_ne_i32_e64 s10, vcc_hi, 0xaf123456  ; encoding: [0x0a,0x00,0x45,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_ne_i32_e64 s[10:11], vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x45,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x45,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ne_i32_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x45,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_ne_i32_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x45,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x45,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_ne_i32_e64 s10, m0, 0.5             ; encoding: [0x0a,0x00,0x45,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_ne_i32_e64 s[10:11], m0, 0.5        ; encoding: [0x0a,0x00,0x45,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x45,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_ne_i32_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x45,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_ne_i32_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x45,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x45,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_ne_i32_e64 s10, exec_hi, null       ; encoding: [0x0a,0x00,0x45,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_ne_i32_e64 s[10:11], exec_hi, null  ; encoding: [0x0a,0x00,0x45,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x00,0x45,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_ne_i32_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x45,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_ne_i32_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x45,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x45,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_ne_i32_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x45,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_ne_i32_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x45,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x45,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_ne_i32_e64 vcc_lo, 0.5, m0          ; encoding: [0x6a,0x00,0x45,0xd4,0xf0,0xfa,0x00,0x00]
+# W64: v_cmp_ne_i32_e64 vcc, 0.5, m0             ; encoding: [0x6a,0x00,0x45,0xd4,0xf0,0xfa,0x00,0x00]
+0x6a,0x00,0x45,0xd4,0xf0,0xfa,0x00,0x00
+
+# W32: v_cmp_ne_i32_e64 ttmp14, src_scc, vcc_lo  ; encoding: [0x7a,0x00,0x45,0xd4,0xfd,0xd4,0x00,0x00]
+# W64: v_cmp_ne_i32_e64 ttmp[14:15], src_scc, vcc_lo ; encoding: [0x7a,0x00,0x45,0xd4,0xfd,0xd4,0x00,0x00]
+0x7a,0x00,0x45,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmp_ne_i32_e64 null, 0xaf123456, vcc_hi ; encoding: [0x7c,0x00,0x45,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x45,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ne_i64_e64 s10, v[1:2], v[2:3]      ; encoding: [0x0a,0x00,0x55,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_ne_i64_e64 s[10:11], v[1:2], v[2:3] ; encoding: [0x0a,0x00,0x55,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x55,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_ne_i64_e64 s10, v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x55,0xd4,0xfe,0xfd,0x03,0x00]
+# W64: v_cmp_ne_i64_e64 s[10:11], v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x55,0xd4,0xfe,0xfd,0x03,0x00]
+0x0a,0x00,0x55,0xd4,0xfe,0xfd,0x03,0x00
+
+# W32: v_cmp_ne_i64_e64 s10, s[2:3], s[4:5]      ; encoding: [0x0a,0x00,0x55,0xd4,0x02,0x08,0x00,0x00]
+# W64: v_cmp_ne_i64_e64 s[10:11], s[2:3], s[4:5] ; encoding: [0x0a,0x00,0x55,0xd4,0x02,0x08,0x00,0x00]
+0x0a,0x00,0x55,0xd4,0x02,0x08,0x00,0x00
+
+# W32: v_cmp_ne_i64_e64 s10, s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x55,0xd4,0x68,0xd0,0x00,0x00]
+# W64: v_cmp_ne_i64_e64 s[10:11], s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x55,0xd4,0x68,0xd0,0x00,0x00]
+0x0a,0x00,0x55,0xd4,0x68,0xd0,0x00,0x00
+
+# W32: v_cmp_ne_i64_e64 s10, vcc, ttmp[14:15]    ; encoding: [0x0a,0x00,0x55,0xd4,0x6a,0xf4,0x00,0x00]
+# W64: v_cmp_ne_i64_e64 s[10:11], vcc, ttmp[14:15] ; encoding: [0x0a,0x00,0x55,0xd4,0x6a,0xf4,0x00,0x00]
+0x0a,0x00,0x55,0xd4,0x6a,0xf4,0x00,0x00
+
+# W32: v_cmp_ne_i64_e64 s10, ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x55,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_ne_i64_e64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x55,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x55,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ne_i64_e64 s10, exec, src_scc       ; encoding: [0x0a,0x00,0x55,0xd4,0x7e,0xfa,0x01,0x00]
+# W64: v_cmp_ne_i64_e64 s[10:11], exec, src_scc  ; encoding: [0x0a,0x00,0x55,0xd4,0x7e,0xfa,0x01,0x00]
+0x0a,0x00,0x55,0xd4,0x7e,0xfa,0x01,0x00
+
+# W32: v_cmp_ne_i64_e64 s10, null, 0.5           ; encoding: [0x0a,0x00,0x55,0xd4,0x7c,0xe0,0x01,0x00]
+# W64: v_cmp_ne_i64_e64 s[10:11], null, 0.5      ; encoding: [0x0a,0x00,0x55,0xd4,0x7c,0xe0,0x01,0x00]
+0x0a,0x00,0x55,0xd4,0x7c,0xe0,0x01,0x00
+
+# W32: v_cmp_ne_i64_e64 s104, -1, -1             ; encoding: [0x68,0x00,0x55,0xd4,0xc1,0x82,0x01,0x00]
+# W64: v_cmp_ne_i64_e64 s[104:105], -1, -1       ; encoding: [0x68,0x00,0x55,0xd4,0xc1,0x82,0x01,0x00]
+0x68,0x00,0x55,0xd4,0xc1,0x82,0x01,0x00
+
+# W32: v_cmp_ne_i64_e64 vcc_lo, 0.5, null        ; encoding: [0x6a,0x00,0x55,0xd4,0xf0,0xf8,0x00,0x00]
+# W64: v_cmp_ne_i64_e64 vcc, 0.5, null           ; encoding: [0x6a,0x00,0x55,0xd4,0xf0,0xf8,0x00,0x00]
+0x6a,0x00,0x55,0xd4,0xf0,0xf8,0x00,0x00
+
+# W32: v_cmp_ne_i64_e64 ttmp14, src_scc, exec    ; encoding: [0x7a,0x00,0x55,0xd4,0xfd,0xfc,0x00,0x00]
+# W64: v_cmp_ne_i64_e64 ttmp[14:15], src_scc, exec ; encoding: [0x7a,0x00,0x55,0xd4,0xfd,0xfc,0x00,0x00]
+0x7a,0x00,0x55,0xd4,0xfd,0xfc,0x00,0x00
+
+# GFX12: v_cmp_ne_i64_e64 null, 0xaf123456, vcc  ; encoding: [0x7c,0x00,0x55,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x55,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ne_u16_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x3d,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_ne_u16_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x3d,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x3d,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_ne_u16_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x3d,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_ne_u16_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x3d,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x3d,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_ne_u16_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x3d,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_ne_u16_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x3d,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x3d,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_ne_u16_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x3d,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_ne_u16_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x3d,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x3d,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_ne_u16_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x3d,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_ne_u16_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x3d,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x3d,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_ne_u16_e64 s10, vcc_hi, 0xfe0b      ; encoding: [0x0a,0x00,0x3d,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_ne_u16_e64 s[10:11], vcc_hi, 0xfe0b ; encoding: [0x0a,0x00,0x3d,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x0a,0x00,0x3d,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_ne_u16_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x3d,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_ne_u16_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x3d,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x3d,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_ne_u16_e64 s10, m0, 0x3800          ; encoding: [0x0a,0x00,0x3d,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+# W64: v_cmp_ne_u16_e64 s[10:11], m0, 0x3800     ; encoding: [0x0a,0x00,0x3d,0xd4,0x7d,0xfe,0x01,0x00,0x00,0x38,0x00,0x00]
+0x0a,0x00,0x3d,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_ne_u16_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x3d,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_ne_u16_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x3d,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x3d,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_ne_u16_e64 s10, exec_hi, null       ; encoding: [0x0a,0x00,0x3d,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_ne_u16_e64 s[10:11], exec_hi, null  ; encoding: [0x0a,0x00,0x3d,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x00,0x3d,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_ne_u16_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x3d,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_ne_u16_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x3d,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x3d,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_ne_u16_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x3d,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_ne_u16_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x3d,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x3d,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_ne_u16_e64 vcc_lo, 0x3800, m0       ; encoding: [0x6a,0x00,0x3d,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+# W64: v_cmp_ne_u16_e64 vcc, 0x3800, m0          ; encoding: [0x6a,0x00,0x3d,0xd4,0xff,0xfa,0x00,0x00,0x00,0x38,0x00,0x00]
+0x6a,0x00,0x3d,0xd4,0xf0,0xfa,0x00,0x00
+
+# W32: v_cmp_ne_u16_e64 ttmp14, src_scc, vcc_lo  ; encoding: [0x7a,0x00,0x3d,0xd4,0xfd,0xd4,0x00,0x00]
+# W64: v_cmp_ne_u16_e64 ttmp[14:15], src_scc, vcc_lo ; encoding: [0x7a,0x00,0x3d,0xd4,0xfd,0xd4,0x00,0x00]
+0x7a,0x00,0x3d,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmp_ne_u16_e64 null, 0xfe0b, vcc_hi   ; encoding: [0x7c,0x00,0x3d,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0x7c,0x00,0x3d,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_ne_u32_e64 s10, v1, v2              ; encoding: [0x0a,0x00,0x4d,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_ne_u32_e64 s[10:11], v1, v2         ; encoding: [0x0a,0x00,0x4d,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x4d,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_ne_u32_e64 s10, v255, v255          ; encoding: [0x0a,0x00,0x4d,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_ne_u32_e64 s[10:11], v255, v255     ; encoding: [0x0a,0x00,0x4d,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x4d,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_ne_u32_e64 s10, s1, s2              ; encoding: [0x0a,0x00,0x4d,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_ne_u32_e64 s[10:11], s1, s2         ; encoding: [0x0a,0x00,0x4d,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x4d,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_ne_u32_e64 s10, s105, s105          ; encoding: [0x0a,0x00,0x4d,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_ne_u32_e64 s[10:11], s105, s105     ; encoding: [0x0a,0x00,0x4d,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x4d,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_ne_u32_e64 s10, vcc_lo, ttmp15      ; encoding: [0x0a,0x00,0x4d,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_ne_u32_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x4d,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x4d,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_ne_u32_e64 s10, vcc_hi, 0xaf123456  ; encoding: [0x0a,0x00,0x4d,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_ne_u32_e64 s[10:11], vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x4d,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x4d,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ne_u32_e64 s10, ttmp15, src_scc     ; encoding: [0x0a,0x00,0x4d,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_ne_u32_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x4d,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x4d,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_ne_u32_e64 s10, m0, 0.5             ; encoding: [0x0a,0x00,0x4d,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_ne_u32_e64 s[10:11], m0, 0.5        ; encoding: [0x0a,0x00,0x4d,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x4d,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_ne_u32_e64 s10, exec_lo, -1         ; encoding: [0x0a,0x00,0x4d,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_ne_u32_e64 s[10:11], exec_lo, -1    ; encoding: [0x0a,0x00,0x4d,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x4d,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_ne_u32_e64 s10, exec_hi, null       ; encoding: [0x0a,0x00,0x4d,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_ne_u32_e64 s[10:11], exec_hi, null  ; encoding: [0x0a,0x00,0x4d,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x00,0x4d,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_ne_u32_e64 s10, null, exec_lo       ; encoding: [0x0a,0x00,0x4d,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_ne_u32_e64 s[10:11], null, exec_lo  ; encoding: [0x0a,0x00,0x4d,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x4d,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_ne_u32_e64 s104, -1, exec_hi        ; encoding: [0x68,0x00,0x4d,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_ne_u32_e64 s[104:105], -1, exec_hi  ; encoding: [0x68,0x00,0x4d,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x4d,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_ne_u32_e64 vcc_lo, 0.5, m0          ; encoding: [0x6a,0x00,0x4d,0xd4,0xf0,0xfa,0x00,0x00]
+# W64: v_cmp_ne_u32_e64 vcc, 0.5, m0             ; encoding: [0x6a,0x00,0x4d,0xd4,0xf0,0xfa,0x00,0x00]
+0x6a,0x00,0x4d,0xd4,0xf0,0xfa,0x00,0x00
+
+# W32: v_cmp_ne_u32_e64 ttmp14, src_scc, vcc_lo  ; encoding: [0x7a,0x00,0x4d,0xd4,0xfd,0xd4,0x00,0x00]
+# W64: v_cmp_ne_u32_e64 ttmp[14:15], src_scc, vcc_lo ; encoding: [0x7a,0x00,0x4d,0xd4,0xfd,0xd4,0x00,0x00]
+0x7a,0x00,0x4d,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmp_ne_u32_e64 null, 0xaf123456, vcc_hi ; encoding: [0x7c,0x00,0x4d,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x4d,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ne_u64_e64 s10, v[1:2], v[2:3]      ; encoding: [0x0a,0x00,0x5d,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_ne_u64_e64 s[10:11], v[1:2], v[2:3] ; encoding: [0x0a,0x00,0x5d,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x5d,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_ne_u64_e64 s10, v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x5d,0xd4,0xfe,0xfd,0x03,0x00]
+# W64: v_cmp_ne_u64_e64 s[10:11], v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x5d,0xd4,0xfe,0xfd,0x03,0x00]
+0x0a,0x00,0x5d,0xd4,0xfe,0xfd,0x03,0x00
+
+# W32: v_cmp_ne_u64_e64 s10, s[2:3], s[4:5]      ; encoding: [0x0a,0x00,0x5d,0xd4,0x02,0x08,0x00,0x00]
+# W64: v_cmp_ne_u64_e64 s[10:11], s[2:3], s[4:5] ; encoding: [0x0a,0x00,0x5d,0xd4,0x02,0x08,0x00,0x00]
+0x0a,0x00,0x5d,0xd4,0x02,0x08,0x00,0x00
+
+# W32: v_cmp_ne_u64_e64 s10, s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x5d,0xd4,0x68,0xd0,0x00,0x00]
+# W64: v_cmp_ne_u64_e64 s[10:11], s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x5d,0xd4,0x68,0xd0,0x00,0x00]
+0x0a,0x00,0x5d,0xd4,0x68,0xd0,0x00,0x00
+
+# W32: v_cmp_ne_u64_e64 s10, vcc, ttmp[14:15]    ; encoding: [0x0a,0x00,0x5d,0xd4,0x6a,0xf4,0x00,0x00]
+# W64: v_cmp_ne_u64_e64 s[10:11], vcc, ttmp[14:15] ; encoding: [0x0a,0x00,0x5d,0xd4,0x6a,0xf4,0x00,0x00]
+0x0a,0x00,0x5d,0xd4,0x6a,0xf4,0x00,0x00
+
+# W32: v_cmp_ne_u64_e64 s10, ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x5d,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_ne_u64_e64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x5d,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x5d,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ne_u64_e64 s10, exec, src_scc       ; encoding: [0x0a,0x00,0x5d,0xd4,0x7e,0xfa,0x01,0x00]
+# W64: v_cmp_ne_u64_e64 s[10:11], exec, src_scc  ; encoding: [0x0a,0x00,0x5d,0xd4,0x7e,0xfa,0x01,0x00]
+0x0a,0x00,0x5d,0xd4,0x7e,0xfa,0x01,0x00
+
+# W32: v_cmp_ne_u64_e64 s10, null, 0.5           ; encoding: [0x0a,0x00,0x5d,0xd4,0x7c,0xe0,0x01,0x00]
+# W64: v_cmp_ne_u64_e64 s[10:11], null, 0.5      ; encoding: [0x0a,0x00,0x5d,0xd4,0x7c,0xe0,0x01,0x00]
+0x0a,0x00,0x5d,0xd4,0x7c,0xe0,0x01,0x00
+
+# W32: v_cmp_ne_u64_e64 s104, -1, -1             ; encoding: [0x68,0x00,0x5d,0xd4,0xc1,0x82,0x01,0x00]
+# W64: v_cmp_ne_u64_e64 s[104:105], -1, -1       ; encoding: [0x68,0x00,0x5d,0xd4,0xc1,0x82,0x01,0x00]
+0x68,0x00,0x5d,0xd4,0xc1,0x82,0x01,0x00
+
+# W32: v_cmp_ne_u64_e64 vcc_lo, 0.5, null        ; encoding: [0x6a,0x00,0x5d,0xd4,0xf0,0xf8,0x00,0x00]
+# W64: v_cmp_ne_u64_e64 vcc, 0.5, null           ; encoding: [0x6a,0x00,0x5d,0xd4,0xf0,0xf8,0x00,0x00]
+0x6a,0x00,0x5d,0xd4,0xf0,0xf8,0x00,0x00
+
+# W32: v_cmp_ne_u64_e64 ttmp14, src_scc, exec    ; encoding: [0x7a,0x00,0x5d,0xd4,0xfd,0xfc,0x00,0x00]
+# W64: v_cmp_ne_u64_e64 ttmp[14:15], src_scc, exec ; encoding: [0x7a,0x00,0x5d,0xd4,0xfd,0xfc,0x00,0x00]
+0x7a,0x00,0x5d,0xd4,0xfd,0xfc,0x00,0x00
+
+# GFX12: v_cmp_ne_u64_e64 null, 0xaf123456, vcc  ; encoding: [0x7c,0x00,0x5d,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x5d,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_neq_f16_e64 s10, v1, v2             ; encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_neq_f16_e64 s[10:11], v1, v2        ; encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x0d,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_neq_f16_e64 s10, v255, v255         ; encoding: [0x0a,0x00,0x0d,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_neq_f16_e64 s[10:11], v255, v255    ; encoding: [0x0a,0x00,0x0d,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x0d,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_neq_f16_e64 s10, s1, s2             ; encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_neq_f16_e64 s[10:11], s1, s2        ; encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x0d,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_neq_f16_e64 s10, s105, s105         ; encoding: [0x0a,0x00,0x0d,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_neq_f16_e64 s[10:11], s105, s105    ; encoding: [0x0a,0x00,0x0d,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x0d,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_neq_f16_e64 s10, vcc_lo, ttmp15     ; encoding: [0x0a,0x00,0x0d,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_neq_f16_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x0d,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x0d,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_neq_f16_e64 s10, vcc_hi, 0xfe0b     ; encoding: [0x0a,0x00,0x0d,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_neq_f16_e64 s[10:11], vcc_hi, 0xfe0b ; encoding: [0x0a,0x00,0x0d,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x0a,0x00,0x0d,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_neq_f16_e64 s10, ttmp15, src_scc    ; encoding: [0x0a,0x00,0x0d,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_neq_f16_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x0d,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x0d,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_neq_f16_e64 s10, m0, 0.5            ; encoding: [0x0a,0x00,0x0d,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_neq_f16_e64 s[10:11], m0, 0.5       ; encoding: [0x0a,0x00,0x0d,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x0d,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_neq_f16_e64 s10, exec_lo, -1        ; encoding: [0x0a,0x00,0x0d,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_neq_f16_e64 s[10:11], exec_lo, -1   ; encoding: [0x0a,0x00,0x0d,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x0d,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_neq_f16_e64 s10, |exec_hi|, null    ; encoding: [0x0a,0x01,0x0d,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_neq_f16_e64 s[10:11], |exec_hi|, null ; encoding: [0x0a,0x01,0x0d,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x01,0x0d,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_neq_f16_e64 s10, null, exec_lo      ; encoding: [0x0a,0x00,0x0d,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_neq_f16_e64 s[10:11], null, exec_lo ; encoding: [0x0a,0x00,0x0d,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x0d,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_neq_f16_e64 s104, -1, exec_hi       ; encoding: [0x68,0x00,0x0d,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_neq_f16_e64 s[104:105], -1, exec_hi ; encoding: [0x68,0x00,0x0d,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x0d,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_neq_f16_e64 vcc_lo, 0.5, -m0        ; encoding: [0x6a,0x00,0x0d,0xd4,0xf0,0xfa,0x00,0x40]
+# W64: v_cmp_neq_f16_e64 vcc, 0.5, -m0           ; encoding: [0x6a,0x00,0x0d,0xd4,0xf0,0xfa,0x00,0x40]
+0x6a,0x00,0x0d,0xd4,0xf0,0xfa,0x00,0x40
+
+# W32: v_cmp_neq_f16_e64 ttmp14, -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x0d,0xd4,0xfd,0xd4,0x00,0x20]
+# W64: v_cmp_neq_f16_e64 ttmp[14:15], -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x0d,0xd4,0xfd,0xd4,0x00,0x20]
+0x7a,0x02,0x0d,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmp_neq_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x0d,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x7c,0x83,0x0d,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_neq_f32_e64 s10, v1, v2             ; encoding: [0x0a,0x00,0x1d,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_neq_f32_e64 s[10:11], v1, v2        ; encoding: [0x0a,0x00,0x1d,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x1d,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_neq_f32_e64 s10, v255, v255         ; encoding: [0x0a,0x00,0x1d,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_neq_f32_e64 s[10:11], v255, v255    ; encoding: [0x0a,0x00,0x1d,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x1d,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_neq_f32_e64 s10, s1, s2             ; encoding: [0x0a,0x00,0x1d,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_neq_f32_e64 s[10:11], s1, s2        ; encoding: [0x0a,0x00,0x1d,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x1d,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_neq_f32_e64 s10, s105, s105         ; encoding: [0x0a,0x00,0x1d,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_neq_f32_e64 s[10:11], s105, s105    ; encoding: [0x0a,0x00,0x1d,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x1d,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_neq_f32_e64 s10, vcc_lo, ttmp15     ; encoding: [0x0a,0x00,0x1d,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_neq_f32_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x1d,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x1d,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_neq_f32_e64 s10, vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x1d,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_neq_f32_e64 s[10:11], vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x1d,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x1d,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_neq_f32_e64 s10, ttmp15, src_scc    ; encoding: [0x0a,0x00,0x1d,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_neq_f32_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x1d,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x1d,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_neq_f32_e64 s10, m0, 0.5            ; encoding: [0x0a,0x00,0x1d,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_neq_f32_e64 s[10:11], m0, 0.5       ; encoding: [0x0a,0x00,0x1d,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x1d,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_neq_f32_e64 s10, exec_lo, -1        ; encoding: [0x0a,0x00,0x1d,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_neq_f32_e64 s[10:11], exec_lo, -1   ; encoding: [0x0a,0x00,0x1d,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x1d,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_neq_f32_e64 s10, |exec_hi|, null    ; encoding: [0x0a,0x01,0x1d,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_neq_f32_e64 s[10:11], |exec_hi|, null ; encoding: [0x0a,0x01,0x1d,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x01,0x1d,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_neq_f32_e64 s10, null, exec_lo      ; encoding: [0x0a,0x00,0x1d,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_neq_f32_e64 s[10:11], null, exec_lo ; encoding: [0x0a,0x00,0x1d,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x1d,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_neq_f32_e64 s104, -1, exec_hi       ; encoding: [0x68,0x00,0x1d,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_neq_f32_e64 s[104:105], -1, exec_hi ; encoding: [0x68,0x00,0x1d,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x1d,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_neq_f32_e64 vcc_lo, 0.5, -m0        ; encoding: [0x6a,0x00,0x1d,0xd4,0xf0,0xfa,0x00,0x40]
+# W64: v_cmp_neq_f32_e64 vcc, 0.5, -m0           ; encoding: [0x6a,0x00,0x1d,0xd4,0xf0,0xfa,0x00,0x40]
+0x6a,0x00,0x1d,0xd4,0xf0,0xfa,0x00,0x40
+
+# W32: v_cmp_neq_f32_e64 ttmp14, -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x1d,0xd4,0xfd,0xd4,0x00,0x20]
+# W64: v_cmp_neq_f32_e64 ttmp[14:15], -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x1d,0xd4,0xfd,0xd4,0x00,0x20]
+0x7a,0x02,0x1d,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmp_neq_f32_e64 null, -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x1d,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0x7c,0x83,0x1d,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_neq_f64_e64 s10, v[1:2], v[2:3]     ; encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_neq_f64_e64 s[10:11], v[1:2], v[2:3] ; encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x2d,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_neq_f64_e64 s10, v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x2d,0xd4,0xfe,0xfd,0x03,0x00]
+# W64: v_cmp_neq_f64_e64 s[10:11], v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x2d,0xd4,0xfe,0xfd,0x03,0x00]
+0x0a,0x00,0x2d,0xd4,0xfe,0xfd,0x03,0x00
+
+# W32: v_cmp_neq_f64_e64 s10, s[2:3], s[4:5]     ; encoding: [0x0a,0x00,0x2d,0xd4,0x02,0x08,0x00,0x00]
+# W64: v_cmp_neq_f64_e64 s[10:11], s[2:3], s[4:5] ; encoding: [0x0a,0x00,0x2d,0xd4,0x02,0x08,0x00,0x00]
+0x0a,0x00,0x2d,0xd4,0x02,0x08,0x00,0x00
+
+# W32: v_cmp_neq_f64_e64 s10, s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x2d,0xd4,0x68,0xd0,0x00,0x00]
+# W64: v_cmp_neq_f64_e64 s[10:11], s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x2d,0xd4,0x68,0xd0,0x00,0x00]
+0x0a,0x00,0x2d,0xd4,0x68,0xd0,0x00,0x00
+
+# W32: v_cmp_neq_f64_e64 s10, vcc, ttmp[14:15]   ; encoding: [0x0a,0x00,0x2d,0xd4,0x6a,0xf4,0x00,0x00]
+# W64: v_cmp_neq_f64_e64 s[10:11], vcc, ttmp[14:15] ; encoding: [0x0a,0x00,0x2d,0xd4,0x6a,0xf4,0x00,0x00]
+0x0a,0x00,0x2d,0xd4,0x6a,0xf4,0x00,0x00
+
+# W32: v_cmp_neq_f64_e64 s10, ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x2d,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_neq_f64_e64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x2d,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x2d,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_neq_f64_e64 s10, -|exec|, src_scc   ; encoding: [0x0a,0x01,0x2d,0xd4,0x7e,0xfa,0x01,0x20]
+# W64: v_cmp_neq_f64_e64 s[10:11], -|exec|, src_scc ; encoding: [0x0a,0x01,0x2d,0xd4,0x7e,0xfa,0x01,0x20]
+0x0a,0x01,0x2d,0xd4,0x7e,0xfa,0x01,0x20
+
+# W32: v_cmp_neq_f64_e64 s10, null, 0.5          ; encoding: [0x0a,0x00,0x2d,0xd4,0x7c,0xe0,0x01,0x00]
+# W64: v_cmp_neq_f64_e64 s[10:11], null, 0.5     ; encoding: [0x0a,0x00,0x2d,0xd4,0x7c,0xe0,0x01,0x00]
+0x0a,0x00,0x2d,0xd4,0x7c,0xe0,0x01,0x00
+
+# W32: v_cmp_neq_f64_e64 s104, -1, -1            ; encoding: [0x68,0x00,0x2d,0xd4,0xc1,0x82,0x01,0x00]
+# W64: v_cmp_neq_f64_e64 s[104:105], -1, -1      ; encoding: [0x68,0x00,0x2d,0xd4,0xc1,0x82,0x01,0x00]
+0x68,0x00,0x2d,0xd4,0xc1,0x82,0x01,0x00
+
+# W32: v_cmp_neq_f64_e64 vcc_lo, 0.5, null       ; encoding: [0x6a,0x00,0x2d,0xd4,0xf0,0xf8,0x00,0x00]
+# W64: v_cmp_neq_f64_e64 vcc, 0.5, null          ; encoding: [0x6a,0x00,0x2d,0xd4,0xf0,0xf8,0x00,0x00]
+0x6a,0x00,0x2d,0xd4,0xf0,0xf8,0x00,0x00
+
+# W32: v_cmp_neq_f64_e64 ttmp14, -|src_scc|, -|exec| ; encoding: [0x7a,0x03,0x2d,0xd4,0xfd,0xfc,0x00,0x60]
+# W64: v_cmp_neq_f64_e64 ttmp[14:15], -|src_scc|, -|exec| ; encoding: [0x7a,0x03,0x2d,0xd4,0xfd,0xfc,0x00,0x60]
+0x7a,0x03,0x2d,0xd4,0xfd,0xfc,0x00,0x60
+
+# GFX12: v_cmp_neq_f64_e64 null, 0xaf123456, -|vcc| clamp ; encoding: [0x7c,0x82,0x2d,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+0x7c,0x82,0x2d,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_nge_f16_e64 s10, v1, v2             ; encoding: [0x0a,0x00,0x09,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_nge_f16_e64 s[10:11], v1, v2        ; encoding: [0x0a,0x00,0x09,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x09,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_nge_f16_e64 s10, v255, v255         ; encoding: [0x0a,0x00,0x09,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_nge_f16_e64 s[10:11], v255, v255    ; encoding: [0x0a,0x00,0x09,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x09,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_nge_f16_e64 s10, s1, s2             ; encoding: [0x0a,0x00,0x09,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_nge_f16_e64 s[10:11], s1, s2        ; encoding: [0x0a,0x00,0x09,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x09,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_nge_f16_e64 s10, s105, s105         ; encoding: [0x0a,0x00,0x09,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_nge_f16_e64 s[10:11], s105, s105    ; encoding: [0x0a,0x00,0x09,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x09,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_nge_f16_e64 s10, vcc_lo, ttmp15     ; encoding: [0x0a,0x00,0x09,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_nge_f16_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x09,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x09,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_nge_f16_e64 s10, vcc_hi, 0xfe0b     ; encoding: [0x0a,0x00,0x09,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_nge_f16_e64 s[10:11], vcc_hi, 0xfe0b ; encoding: [0x0a,0x00,0x09,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x0a,0x00,0x09,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_nge_f16_e64 s10, ttmp15, src_scc    ; encoding: [0x0a,0x00,0x09,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_nge_f16_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x09,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x09,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_nge_f16_e64 s10, m0, 0.5            ; encoding: [0x0a,0x00,0x09,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_nge_f16_e64 s[10:11], m0, 0.5       ; encoding: [0x0a,0x00,0x09,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x09,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_nge_f16_e64 s10, exec_lo, -1        ; encoding: [0x0a,0x00,0x09,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_nge_f16_e64 s[10:11], exec_lo, -1   ; encoding: [0x0a,0x00,0x09,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x09,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_nge_f16_e64 s10, |exec_hi|, null    ; encoding: [0x0a,0x01,0x09,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_nge_f16_e64 s[10:11], |exec_hi|, null ; encoding: [0x0a,0x01,0x09,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x01,0x09,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_nge_f16_e64 s10, null, exec_lo      ; encoding: [0x0a,0x00,0x09,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_nge_f16_e64 s[10:11], null, exec_lo ; encoding: [0x0a,0x00,0x09,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x09,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_nge_f16_e64 s104, -1, exec_hi       ; encoding: [0x68,0x00,0x09,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_nge_f16_e64 s[104:105], -1, exec_hi ; encoding: [0x68,0x00,0x09,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x09,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_nge_f16_e64 vcc_lo, 0.5, -m0        ; encoding: [0x6a,0x00,0x09,0xd4,0xf0,0xfa,0x00,0x40]
+# W64: v_cmp_nge_f16_e64 vcc, 0.5, -m0           ; encoding: [0x6a,0x00,0x09,0xd4,0xf0,0xfa,0x00,0x40]
+0x6a,0x00,0x09,0xd4,0xf0,0xfa,0x00,0x40
+
+# W32: v_cmp_nge_f16_e64 ttmp14, -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x09,0xd4,0xfd,0xd4,0x00,0x20]
+# W64: v_cmp_nge_f16_e64 ttmp[14:15], -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x09,0xd4,0xfd,0xd4,0x00,0x20]
+0x7a,0x02,0x09,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmp_nge_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x09,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x7c,0x83,0x09,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_nge_f32_e64 s10, v1, v2             ; encoding: [0x0a,0x00,0x19,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_nge_f32_e64 s[10:11], v1, v2        ; encoding: [0x0a,0x00,0x19,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x19,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_nge_f32_e64 s10, v255, v255         ; encoding: [0x0a,0x00,0x19,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_nge_f32_e64 s[10:11], v255, v255    ; encoding: [0x0a,0x00,0x19,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x19,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_nge_f32_e64 s10, s1, s2             ; encoding: [0x0a,0x00,0x19,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_nge_f32_e64 s[10:11], s1, s2        ; encoding: [0x0a,0x00,0x19,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x19,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_nge_f32_e64 s10, s105, s105         ; encoding: [0x0a,0x00,0x19,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_nge_f32_e64 s[10:11], s105, s105    ; encoding: [0x0a,0x00,0x19,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x19,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_nge_f32_e64 s10, vcc_lo, ttmp15     ; encoding: [0x0a,0x00,0x19,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_nge_f32_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x19,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x19,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_nge_f32_e64 s10, vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x19,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_nge_f32_e64 s[10:11], vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x19,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x19,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_nge_f32_e64 s10, ttmp15, src_scc    ; encoding: [0x0a,0x00,0x19,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_nge_f32_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x19,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x19,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_nge_f32_e64 s10, m0, 0.5            ; encoding: [0x0a,0x00,0x19,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_nge_f32_e64 s[10:11], m0, 0.5       ; encoding: [0x0a,0x00,0x19,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x19,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_nge_f32_e64 s10, exec_lo, -1        ; encoding: [0x0a,0x00,0x19,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_nge_f32_e64 s[10:11], exec_lo, -1   ; encoding: [0x0a,0x00,0x19,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x19,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_nge_f32_e64 s10, |exec_hi|, null    ; encoding: [0x0a,0x01,0x19,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_nge_f32_e64 s[10:11], |exec_hi|, null ; encoding: [0x0a,0x01,0x19,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x01,0x19,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_nge_f32_e64 s10, null, exec_lo      ; encoding: [0x0a,0x00,0x19,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_nge_f32_e64 s[10:11], null, exec_lo ; encoding: [0x0a,0x00,0x19,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x19,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_nge_f32_e64 s104, -1, exec_hi       ; encoding: [0x68,0x00,0x19,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_nge_f32_e64 s[104:105], -1, exec_hi ; encoding: [0x68,0x00,0x19,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x19,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_nge_f32_e64 vcc_lo, 0.5, -m0        ; encoding: [0x6a,0x00,0x19,0xd4,0xf0,0xfa,0x00,0x40]
+# W64: v_cmp_nge_f32_e64 vcc, 0.5, -m0           ; encoding: [0x6a,0x00,0x19,0xd4,0xf0,0xfa,0x00,0x40]
+0x6a,0x00,0x19,0xd4,0xf0,0xfa,0x00,0x40
+
+# W32: v_cmp_nge_f32_e64 ttmp14, -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x19,0xd4,0xfd,0xd4,0x00,0x20]
+# W64: v_cmp_nge_f32_e64 ttmp[14:15], -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x19,0xd4,0xfd,0xd4,0x00,0x20]
+0x7a,0x02,0x19,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmp_nge_f32_e64 null, -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x19,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0x7c,0x83,0x19,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_nge_f64_e64 s10, v[1:2], v[2:3]     ; encoding: [0x0a,0x00,0x29,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_nge_f64_e64 s[10:11], v[1:2], v[2:3] ; encoding: [0x0a,0x00,0x29,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x29,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_nge_f64_e64 s10, v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x29,0xd4,0xfe,0xfd,0x03,0x00]
+# W64: v_cmp_nge_f64_e64 s[10:11], v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x29,0xd4,0xfe,0xfd,0x03,0x00]
+0x0a,0x00,0x29,0xd4,0xfe,0xfd,0x03,0x00
+
+# W32: v_cmp_nge_f64_e64 s10, s[2:3], s[4:5]     ; encoding: [0x0a,0x00,0x29,0xd4,0x02,0x08,0x00,0x00]
+# W64: v_cmp_nge_f64_e64 s[10:11], s[2:3], s[4:5] ; encoding: [0x0a,0x00,0x29,0xd4,0x02,0x08,0x00,0x00]
+0x0a,0x00,0x29,0xd4,0x02,0x08,0x00,0x00
+
+# W32: v_cmp_nge_f64_e64 s10, s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x29,0xd4,0x68,0xd0,0x00,0x00]
+# W64: v_cmp_nge_f64_e64 s[10:11], s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x29,0xd4,0x68,0xd0,0x00,0x00]
+0x0a,0x00,0x29,0xd4,0x68,0xd0,0x00,0x00
+
+# W32: v_cmp_nge_f64_e64 s10, vcc, ttmp[14:15]   ; encoding: [0x0a,0x00,0x29,0xd4,0x6a,0xf4,0x00,0x00]
+# W64: v_cmp_nge_f64_e64 s[10:11], vcc, ttmp[14:15] ; encoding: [0x0a,0x00,0x29,0xd4,0x6a,0xf4,0x00,0x00]
+0x0a,0x00,0x29,0xd4,0x6a,0xf4,0x00,0x00
+
+# W32: v_cmp_nge_f64_e64 s10, ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x29,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_nge_f64_e64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x29,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x29,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_nge_f64_e64 s10, -|exec|, src_scc   ; encoding: [0x0a,0x01,0x29,0xd4,0x7e,0xfa,0x01,0x20]
+# W64: v_cmp_nge_f64_e64 s[10:11], -|exec|, src_scc ; encoding: [0x0a,0x01,0x29,0xd4,0x7e,0xfa,0x01,0x20]
+0x0a,0x01,0x29,0xd4,0x7e,0xfa,0x01,0x20
+
+# W32: v_cmp_nge_f64_e64 s10, null, 0.5          ; encoding: [0x0a,0x00,0x29,0xd4,0x7c,0xe0,0x01,0x00]
+# W64: v_cmp_nge_f64_e64 s[10:11], null, 0.5     ; encoding: [0x0a,0x00,0x29,0xd4,0x7c,0xe0,0x01,0x00]
+0x0a,0x00,0x29,0xd4,0x7c,0xe0,0x01,0x00
+
+# W32: v_cmp_nge_f64_e64 s104, -1, -1            ; encoding: [0x68,0x00,0x29,0xd4,0xc1,0x82,0x01,0x00]
+# W64: v_cmp_nge_f64_e64 s[104:105], -1, -1      ; encoding: [0x68,0x00,0x29,0xd4,0xc1,0x82,0x01,0x00]
+0x68,0x00,0x29,0xd4,0xc1,0x82,0x01,0x00
+
+# W32: v_cmp_nge_f64_e64 vcc_lo, 0.5, null       ; encoding: [0x6a,0x00,0x29,0xd4,0xf0,0xf8,0x00,0x00]
+# W64: v_cmp_nge_f64_e64 vcc, 0.5, null          ; encoding: [0x6a,0x00,0x29,0xd4,0xf0,0xf8,0x00,0x00]
+0x6a,0x00,0x29,0xd4,0xf0,0xf8,0x00,0x00
+
+# W32: v_cmp_nge_f64_e64 ttmp14, -|src_scc|, -|exec| ; encoding: [0x7a,0x03,0x29,0xd4,0xfd,0xfc,0x00,0x60]
+# W64: v_cmp_nge_f64_e64 ttmp[14:15], -|src_scc|, -|exec| ; encoding: [0x7a,0x03,0x29,0xd4,0xfd,0xfc,0x00,0x60]
+0x7a,0x03,0x29,0xd4,0xfd,0xfc,0x00,0x60
+
+# GFX12: v_cmp_nge_f64_e64 null, 0xaf123456, -|vcc| clamp ; encoding: [0x7c,0x82,0x29,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+0x7c,0x82,0x29,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ngt_f16_e64 s10, v1, v2             ; encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_ngt_f16_e64 s[10:11], v1, v2        ; encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x0b,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_ngt_f16_e64 s10, v255, v255         ; encoding: [0x0a,0x00,0x0b,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_ngt_f16_e64 s[10:11], v255, v255    ; encoding: [0x0a,0x00,0x0b,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x0b,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_ngt_f16_e64 s10, s1, s2             ; encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_ngt_f16_e64 s[10:11], s1, s2        ; encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x0b,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_ngt_f16_e64 s10, s105, s105         ; encoding: [0x0a,0x00,0x0b,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_ngt_f16_e64 s[10:11], s105, s105    ; encoding: [0x0a,0x00,0x0b,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x0b,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_ngt_f16_e64 s10, vcc_lo, ttmp15     ; encoding: [0x0a,0x00,0x0b,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_ngt_f16_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x0b,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x0b,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_ngt_f16_e64 s10, vcc_hi, 0xfe0b     ; encoding: [0x0a,0x00,0x0b,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_ngt_f16_e64 s[10:11], vcc_hi, 0xfe0b ; encoding: [0x0a,0x00,0x0b,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x0a,0x00,0x0b,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_ngt_f16_e64 s10, ttmp15, src_scc    ; encoding: [0x0a,0x00,0x0b,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_ngt_f16_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x0b,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x0b,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_ngt_f16_e64 s10, m0, 0.5            ; encoding: [0x0a,0x00,0x0b,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_ngt_f16_e64 s[10:11], m0, 0.5       ; encoding: [0x0a,0x00,0x0b,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x0b,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_ngt_f16_e64 s10, exec_lo, -1        ; encoding: [0x0a,0x00,0x0b,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_ngt_f16_e64 s[10:11], exec_lo, -1   ; encoding: [0x0a,0x00,0x0b,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x0b,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_ngt_f16_e64 s10, |exec_hi|, null    ; encoding: [0x0a,0x01,0x0b,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_ngt_f16_e64 s[10:11], |exec_hi|, null ; encoding: [0x0a,0x01,0x0b,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x01,0x0b,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_ngt_f16_e64 s10, null, exec_lo      ; encoding: [0x0a,0x00,0x0b,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_ngt_f16_e64 s[10:11], null, exec_lo ; encoding: [0x0a,0x00,0x0b,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x0b,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_ngt_f16_e64 s104, -1, exec_hi       ; encoding: [0x68,0x00,0x0b,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_ngt_f16_e64 s[104:105], -1, exec_hi ; encoding: [0x68,0x00,0x0b,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x0b,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_ngt_f16_e64 vcc_lo, 0.5, -m0        ; encoding: [0x6a,0x00,0x0b,0xd4,0xf0,0xfa,0x00,0x40]
+# W64: v_cmp_ngt_f16_e64 vcc, 0.5, -m0           ; encoding: [0x6a,0x00,0x0b,0xd4,0xf0,0xfa,0x00,0x40]
+0x6a,0x00,0x0b,0xd4,0xf0,0xfa,0x00,0x40
+
+# W32: v_cmp_ngt_f16_e64 ttmp14, -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x0b,0xd4,0xfd,0xd4,0x00,0x20]
+# W64: v_cmp_ngt_f16_e64 ttmp[14:15], -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x0b,0xd4,0xfd,0xd4,0x00,0x20]
+0x7a,0x02,0x0b,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmp_ngt_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x0b,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x7c,0x83,0x0b,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_ngt_f32_e64 s10, v1, v2             ; encoding: [0x0a,0x00,0x1b,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_ngt_f32_e64 s[10:11], v1, v2        ; encoding: [0x0a,0x00,0x1b,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x1b,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_ngt_f32_e64 s10, v255, v255         ; encoding: [0x0a,0x00,0x1b,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_ngt_f32_e64 s[10:11], v255, v255    ; encoding: [0x0a,0x00,0x1b,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x1b,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_ngt_f32_e64 s10, s1, s2             ; encoding: [0x0a,0x00,0x1b,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_ngt_f32_e64 s[10:11], s1, s2        ; encoding: [0x0a,0x00,0x1b,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x1b,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_ngt_f32_e64 s10, s105, s105         ; encoding: [0x0a,0x00,0x1b,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_ngt_f32_e64 s[10:11], s105, s105    ; encoding: [0x0a,0x00,0x1b,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x1b,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_ngt_f32_e64 s10, vcc_lo, ttmp15     ; encoding: [0x0a,0x00,0x1b,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_ngt_f32_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x1b,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x1b,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_ngt_f32_e64 s10, vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x1b,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_ngt_f32_e64 s[10:11], vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x1b,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x1b,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ngt_f32_e64 s10, ttmp15, src_scc    ; encoding: [0x0a,0x00,0x1b,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_ngt_f32_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x1b,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x1b,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_ngt_f32_e64 s10, m0, 0.5            ; encoding: [0x0a,0x00,0x1b,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_ngt_f32_e64 s[10:11], m0, 0.5       ; encoding: [0x0a,0x00,0x1b,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x1b,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_ngt_f32_e64 s10, exec_lo, -1        ; encoding: [0x0a,0x00,0x1b,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_ngt_f32_e64 s[10:11], exec_lo, -1   ; encoding: [0x0a,0x00,0x1b,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x1b,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_ngt_f32_e64 s10, |exec_hi|, null    ; encoding: [0x0a,0x01,0x1b,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_ngt_f32_e64 s[10:11], |exec_hi|, null ; encoding: [0x0a,0x01,0x1b,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x01,0x1b,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_ngt_f32_e64 s10, null, exec_lo      ; encoding: [0x0a,0x00,0x1b,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_ngt_f32_e64 s[10:11], null, exec_lo ; encoding: [0x0a,0x00,0x1b,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x1b,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_ngt_f32_e64 s104, -1, exec_hi       ; encoding: [0x68,0x00,0x1b,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_ngt_f32_e64 s[104:105], -1, exec_hi ; encoding: [0x68,0x00,0x1b,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x1b,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_ngt_f32_e64 vcc_lo, 0.5, -m0        ; encoding: [0x6a,0x00,0x1b,0xd4,0xf0,0xfa,0x00,0x40]
+# W64: v_cmp_ngt_f32_e64 vcc, 0.5, -m0           ; encoding: [0x6a,0x00,0x1b,0xd4,0xf0,0xfa,0x00,0x40]
+0x6a,0x00,0x1b,0xd4,0xf0,0xfa,0x00,0x40
+
+# W32: v_cmp_ngt_f32_e64 ttmp14, -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x1b,0xd4,0xfd,0xd4,0x00,0x20]
+# W64: v_cmp_ngt_f32_e64 ttmp[14:15], -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x1b,0xd4,0xfd,0xd4,0x00,0x20]
+0x7a,0x02,0x1b,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmp_ngt_f32_e64 null, -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x1b,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0x7c,0x83,0x1b,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ngt_f64_e64 s10, v[1:2], v[2:3]     ; encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_ngt_f64_e64 s[10:11], v[1:2], v[2:3] ; encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x2b,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_ngt_f64_e64 s10, v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x2b,0xd4,0xfe,0xfd,0x03,0x00]
+# W64: v_cmp_ngt_f64_e64 s[10:11], v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x2b,0xd4,0xfe,0xfd,0x03,0x00]
+0x0a,0x00,0x2b,0xd4,0xfe,0xfd,0x03,0x00
+
+# W32: v_cmp_ngt_f64_e64 s10, s[2:3], s[4:5]     ; encoding: [0x0a,0x00,0x2b,0xd4,0x02,0x08,0x00,0x00]
+# W64: v_cmp_ngt_f64_e64 s[10:11], s[2:3], s[4:5] ; encoding: [0x0a,0x00,0x2b,0xd4,0x02,0x08,0x00,0x00]
+0x0a,0x00,0x2b,0xd4,0x02,0x08,0x00,0x00
+
+# W32: v_cmp_ngt_f64_e64 s10, s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x2b,0xd4,0x68,0xd0,0x00,0x00]
+# W64: v_cmp_ngt_f64_e64 s[10:11], s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x2b,0xd4,0x68,0xd0,0x00,0x00]
+0x0a,0x00,0x2b,0xd4,0x68,0xd0,0x00,0x00
+
+# W32: v_cmp_ngt_f64_e64 s10, vcc, ttmp[14:15]   ; encoding: [0x0a,0x00,0x2b,0xd4,0x6a,0xf4,0x00,0x00]
+# W64: v_cmp_ngt_f64_e64 s[10:11], vcc, ttmp[14:15] ; encoding: [0x0a,0x00,0x2b,0xd4,0x6a,0xf4,0x00,0x00]
+0x0a,0x00,0x2b,0xd4,0x6a,0xf4,0x00,0x00
+
+# W32: v_cmp_ngt_f64_e64 s10, ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x2b,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_ngt_f64_e64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x2b,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x2b,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ngt_f64_e64 s10, -|exec|, src_scc   ; encoding: [0x0a,0x01,0x2b,0xd4,0x7e,0xfa,0x01,0x20]
+# W64: v_cmp_ngt_f64_e64 s[10:11], -|exec|, src_scc ; encoding: [0x0a,0x01,0x2b,0xd4,0x7e,0xfa,0x01,0x20]
+0x0a,0x01,0x2b,0xd4,0x7e,0xfa,0x01,0x20
+
+# W32: v_cmp_ngt_f64_e64 s10, null, 0.5          ; encoding: [0x0a,0x00,0x2b,0xd4,0x7c,0xe0,0x01,0x00]
+# W64: v_cmp_ngt_f64_e64 s[10:11], null, 0.5     ; encoding: [0x0a,0x00,0x2b,0xd4,0x7c,0xe0,0x01,0x00]
+0x0a,0x00,0x2b,0xd4,0x7c,0xe0,0x01,0x00
+
+# W32: v_cmp_ngt_f64_e64 s104, -1, -1            ; encoding: [0x68,0x00,0x2b,0xd4,0xc1,0x82,0x01,0x00]
+# W64: v_cmp_ngt_f64_e64 s[104:105], -1, -1      ; encoding: [0x68,0x00,0x2b,0xd4,0xc1,0x82,0x01,0x00]
+0x68,0x00,0x2b,0xd4,0xc1,0x82,0x01,0x00
+
+# W32: v_cmp_ngt_f64_e64 vcc_lo, 0.5, null       ; encoding: [0x6a,0x00,0x2b,0xd4,0xf0,0xf8,0x00,0x00]
+# W64: v_cmp_ngt_f64_e64 vcc, 0.5, null          ; encoding: [0x6a,0x00,0x2b,0xd4,0xf0,0xf8,0x00,0x00]
+0x6a,0x00,0x2b,0xd4,0xf0,0xf8,0x00,0x00
+
+# W32: v_cmp_ngt_f64_e64 ttmp14, -|src_scc|, -|exec| ; encoding: [0x7a,0x03,0x2b,0xd4,0xfd,0xfc,0x00,0x60]
+# W64: v_cmp_ngt_f64_e64 ttmp[14:15], -|src_scc|, -|exec| ; encoding: [0x7a,0x03,0x2b,0xd4,0xfd,0xfc,0x00,0x60]
+0x7a,0x03,0x2b,0xd4,0xfd,0xfc,0x00,0x60
+
+# GFX12: v_cmp_ngt_f64_e64 null, 0xaf123456, -|vcc| clamp ; encoding: [0x7c,0x82,0x2b,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+0x7c,0x82,0x2b,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_nle_f16_e64 s10, v1, v2             ; encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_nle_f16_e64 s[10:11], v1, v2        ; encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x0c,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_nle_f16_e64 s10, v255, v255         ; encoding: [0x0a,0x00,0x0c,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_nle_f16_e64 s[10:11], v255, v255    ; encoding: [0x0a,0x00,0x0c,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x0c,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_nle_f16_e64 s10, s1, s2             ; encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_nle_f16_e64 s[10:11], s1, s2        ; encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x0c,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_nle_f16_e64 s10, s105, s105         ; encoding: [0x0a,0x00,0x0c,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_nle_f16_e64 s[10:11], s105, s105    ; encoding: [0x0a,0x00,0x0c,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x0c,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_nle_f16_e64 s10, vcc_lo, ttmp15     ; encoding: [0x0a,0x00,0x0c,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_nle_f16_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x0c,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x0c,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_nle_f16_e64 s10, vcc_hi, 0xfe0b     ; encoding: [0x0a,0x00,0x0c,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_nle_f16_e64 s[10:11], vcc_hi, 0xfe0b ; encoding: [0x0a,0x00,0x0c,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x0a,0x00,0x0c,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_nle_f16_e64 s10, ttmp15, src_scc    ; encoding: [0x0a,0x00,0x0c,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_nle_f16_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x0c,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x0c,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_nle_f16_e64 s10, m0, 0.5            ; encoding: [0x0a,0x00,0x0c,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_nle_f16_e64 s[10:11], m0, 0.5       ; encoding: [0x0a,0x00,0x0c,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x0c,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_nle_f16_e64 s10, exec_lo, -1        ; encoding: [0x0a,0x00,0x0c,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_nle_f16_e64 s[10:11], exec_lo, -1   ; encoding: [0x0a,0x00,0x0c,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x0c,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_nle_f16_e64 s10, |exec_hi|, null    ; encoding: [0x0a,0x01,0x0c,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_nle_f16_e64 s[10:11], |exec_hi|, null ; encoding: [0x0a,0x01,0x0c,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x01,0x0c,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_nle_f16_e64 s10, null, exec_lo      ; encoding: [0x0a,0x00,0x0c,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_nle_f16_e64 s[10:11], null, exec_lo ; encoding: [0x0a,0x00,0x0c,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x0c,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_nle_f16_e64 s104, -1, exec_hi       ; encoding: [0x68,0x00,0x0c,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_nle_f16_e64 s[104:105], -1, exec_hi ; encoding: [0x68,0x00,0x0c,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x0c,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_nle_f16_e64 vcc_lo, 0.5, -m0        ; encoding: [0x6a,0x00,0x0c,0xd4,0xf0,0xfa,0x00,0x40]
+# W64: v_cmp_nle_f16_e64 vcc, 0.5, -m0           ; encoding: [0x6a,0x00,0x0c,0xd4,0xf0,0xfa,0x00,0x40]
+0x6a,0x00,0x0c,0xd4,0xf0,0xfa,0x00,0x40
+
+# W32: v_cmp_nle_f16_e64 ttmp14, -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x0c,0xd4,0xfd,0xd4,0x00,0x20]
+# W64: v_cmp_nle_f16_e64 ttmp[14:15], -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x0c,0xd4,0xfd,0xd4,0x00,0x20]
+0x7a,0x02,0x0c,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmp_nle_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x0c,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x7c,0x83,0x0c,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_nle_f32_e64 s10, v1, v2             ; encoding: [0x0a,0x00,0x1c,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_nle_f32_e64 s[10:11], v1, v2        ; encoding: [0x0a,0x00,0x1c,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x1c,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_nle_f32_e64 s10, v255, v255         ; encoding: [0x0a,0x00,0x1c,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_nle_f32_e64 s[10:11], v255, v255    ; encoding: [0x0a,0x00,0x1c,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x1c,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_nle_f32_e64 s10, s1, s2             ; encoding: [0x0a,0x00,0x1c,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_nle_f32_e64 s[10:11], s1, s2        ; encoding: [0x0a,0x00,0x1c,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x1c,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_nle_f32_e64 s10, s105, s105         ; encoding: [0x0a,0x00,0x1c,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_nle_f32_e64 s[10:11], s105, s105    ; encoding: [0x0a,0x00,0x1c,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x1c,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_nle_f32_e64 s10, vcc_lo, ttmp15     ; encoding: [0x0a,0x00,0x1c,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_nle_f32_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x1c,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x1c,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_nle_f32_e64 s10, vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x1c,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_nle_f32_e64 s[10:11], vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x1c,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x1c,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_nle_f32_e64 s10, ttmp15, src_scc    ; encoding: [0x0a,0x00,0x1c,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_nle_f32_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x1c,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x1c,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_nle_f32_e64 s10, m0, 0.5            ; encoding: [0x0a,0x00,0x1c,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_nle_f32_e64 s[10:11], m0, 0.5       ; encoding: [0x0a,0x00,0x1c,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x1c,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_nle_f32_e64 s10, exec_lo, -1        ; encoding: [0x0a,0x00,0x1c,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_nle_f32_e64 s[10:11], exec_lo, -1   ; encoding: [0x0a,0x00,0x1c,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x1c,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_nle_f32_e64 s10, |exec_hi|, null    ; encoding: [0x0a,0x01,0x1c,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_nle_f32_e64 s[10:11], |exec_hi|, null ; encoding: [0x0a,0x01,0x1c,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x01,0x1c,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_nle_f32_e64 s10, null, exec_lo      ; encoding: [0x0a,0x00,0x1c,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_nle_f32_e64 s[10:11], null, exec_lo ; encoding: [0x0a,0x00,0x1c,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x1c,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_nle_f32_e64 s104, -1, exec_hi       ; encoding: [0x68,0x00,0x1c,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_nle_f32_e64 s[104:105], -1, exec_hi ; encoding: [0x68,0x00,0x1c,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x1c,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_nle_f32_e64 vcc_lo, 0.5, -m0        ; encoding: [0x6a,0x00,0x1c,0xd4,0xf0,0xfa,0x00,0x40]
+# W64: v_cmp_nle_f32_e64 vcc, 0.5, -m0           ; encoding: [0x6a,0x00,0x1c,0xd4,0xf0,0xfa,0x00,0x40]
+0x6a,0x00,0x1c,0xd4,0xf0,0xfa,0x00,0x40
+
+# W32: v_cmp_nle_f32_e64 ttmp14, -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x1c,0xd4,0xfd,0xd4,0x00,0x20]
+# W64: v_cmp_nle_f32_e64 ttmp[14:15], -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x1c,0xd4,0xfd,0xd4,0x00,0x20]
+0x7a,0x02,0x1c,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmp_nle_f32_e64 null, -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x1c,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0x7c,0x83,0x1c,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_nle_f64_e64 s10, v[1:2], v[2:3]     ; encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_nle_f64_e64 s[10:11], v[1:2], v[2:3] ; encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x2c,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_nle_f64_e64 s10, v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x2c,0xd4,0xfe,0xfd,0x03,0x00]
+# W64: v_cmp_nle_f64_e64 s[10:11], v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x2c,0xd4,0xfe,0xfd,0x03,0x00]
+0x0a,0x00,0x2c,0xd4,0xfe,0xfd,0x03,0x00
+
+# W32: v_cmp_nle_f64_e64 s10, s[2:3], s[4:5]     ; encoding: [0x0a,0x00,0x2c,0xd4,0x02,0x08,0x00,0x00]
+# W64: v_cmp_nle_f64_e64 s[10:11], s[2:3], s[4:5] ; encoding: [0x0a,0x00,0x2c,0xd4,0x02,0x08,0x00,0x00]
+0x0a,0x00,0x2c,0xd4,0x02,0x08,0x00,0x00
+
+# W32: v_cmp_nle_f64_e64 s10, s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x2c,0xd4,0x68,0xd0,0x00,0x00]
+# W64: v_cmp_nle_f64_e64 s[10:11], s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x2c,0xd4,0x68,0xd0,0x00,0x00]
+0x0a,0x00,0x2c,0xd4,0x68,0xd0,0x00,0x00
+
+# W32: v_cmp_nle_f64_e64 s10, vcc, ttmp[14:15]   ; encoding: [0x0a,0x00,0x2c,0xd4,0x6a,0xf4,0x00,0x00]
+# W64: v_cmp_nle_f64_e64 s[10:11], vcc, ttmp[14:15] ; encoding: [0x0a,0x00,0x2c,0xd4,0x6a,0xf4,0x00,0x00]
+0x0a,0x00,0x2c,0xd4,0x6a,0xf4,0x00,0x00
+
+# W32: v_cmp_nle_f64_e64 s10, ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x2c,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_nle_f64_e64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x2c,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x2c,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_nle_f64_e64 s10, -|exec|, src_scc   ; encoding: [0x0a,0x01,0x2c,0xd4,0x7e,0xfa,0x01,0x20]
+# W64: v_cmp_nle_f64_e64 s[10:11], -|exec|, src_scc ; encoding: [0x0a,0x01,0x2c,0xd4,0x7e,0xfa,0x01,0x20]
+0x0a,0x01,0x2c,0xd4,0x7e,0xfa,0x01,0x20
+
+# W32: v_cmp_nle_f64_e64 s10, null, 0.5          ; encoding: [0x0a,0x00,0x2c,0xd4,0x7c,0xe0,0x01,0x00]
+# W64: v_cmp_nle_f64_e64 s[10:11], null, 0.5     ; encoding: [0x0a,0x00,0x2c,0xd4,0x7c,0xe0,0x01,0x00]
+0x0a,0x00,0x2c,0xd4,0x7c,0xe0,0x01,0x00
+
+# W32: v_cmp_nle_f64_e64 s104, -1, -1            ; encoding: [0x68,0x00,0x2c,0xd4,0xc1,0x82,0x01,0x00]
+# W64: v_cmp_nle_f64_e64 s[104:105], -1, -1      ; encoding: [0x68,0x00,0x2c,0xd4,0xc1,0x82,0x01,0x00]
+0x68,0x00,0x2c,0xd4,0xc1,0x82,0x01,0x00
+
+# W32: v_cmp_nle_f64_e64 vcc_lo, 0.5, null       ; encoding: [0x6a,0x00,0x2c,0xd4,0xf0,0xf8,0x00,0x00]
+# W64: v_cmp_nle_f64_e64 vcc, 0.5, null          ; encoding: [0x6a,0x00,0x2c,0xd4,0xf0,0xf8,0x00,0x00]
+0x6a,0x00,0x2c,0xd4,0xf0,0xf8,0x00,0x00
+
+# W32: v_cmp_nle_f64_e64 ttmp14, -|src_scc|, -|exec| ; encoding: [0x7a,0x03,0x2c,0xd4,0xfd,0xfc,0x00,0x60]
+# W64: v_cmp_nle_f64_e64 ttmp[14:15], -|src_scc|, -|exec| ; encoding: [0x7a,0x03,0x2c,0xd4,0xfd,0xfc,0x00,0x60]
+0x7a,0x03,0x2c,0xd4,0xfd,0xfc,0x00,0x60
+
+# GFX12: v_cmp_nle_f64_e64 null, 0xaf123456, -|vcc| clamp ; encoding: [0x7c,0x82,0x2c,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+0x7c,0x82,0x2c,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_nlg_f16_e64 s10, v1, v2             ; encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_nlg_f16_e64 s[10:11], v1, v2        ; encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x0a,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_nlg_f16_e64 s10, v255, v255         ; encoding: [0x0a,0x00,0x0a,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_nlg_f16_e64 s[10:11], v255, v255    ; encoding: [0x0a,0x00,0x0a,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x0a,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_nlg_f16_e64 s10, s1, s2             ; encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_nlg_f16_e64 s[10:11], s1, s2        ; encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x0a,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_nlg_f16_e64 s10, s105, s105         ; encoding: [0x0a,0x00,0x0a,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_nlg_f16_e64 s[10:11], s105, s105    ; encoding: [0x0a,0x00,0x0a,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x0a,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_nlg_f16_e64 s10, vcc_lo, ttmp15     ; encoding: [0x0a,0x00,0x0a,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_nlg_f16_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x0a,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x0a,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_nlg_f16_e64 s10, vcc_hi, 0xfe0b     ; encoding: [0x0a,0x00,0x0a,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_nlg_f16_e64 s[10:11], vcc_hi, 0xfe0b ; encoding: [0x0a,0x00,0x0a,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x0a,0x00,0x0a,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_nlg_f16_e64 s10, ttmp15, src_scc    ; encoding: [0x0a,0x00,0x0a,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_nlg_f16_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x0a,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x0a,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_nlg_f16_e64 s10, m0, 0.5            ; encoding: [0x0a,0x00,0x0a,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_nlg_f16_e64 s[10:11], m0, 0.5       ; encoding: [0x0a,0x00,0x0a,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x0a,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_nlg_f16_e64 s10, exec_lo, -1        ; encoding: [0x0a,0x00,0x0a,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_nlg_f16_e64 s[10:11], exec_lo, -1   ; encoding: [0x0a,0x00,0x0a,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x0a,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_nlg_f16_e64 s10, |exec_hi|, null    ; encoding: [0x0a,0x01,0x0a,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_nlg_f16_e64 s[10:11], |exec_hi|, null ; encoding: [0x0a,0x01,0x0a,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x01,0x0a,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_nlg_f16_e64 s10, null, exec_lo      ; encoding: [0x0a,0x00,0x0a,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_nlg_f16_e64 s[10:11], null, exec_lo ; encoding: [0x0a,0x00,0x0a,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x0a,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_nlg_f16_e64 s104, -1, exec_hi       ; encoding: [0x68,0x00,0x0a,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_nlg_f16_e64 s[104:105], -1, exec_hi ; encoding: [0x68,0x00,0x0a,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x0a,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_nlg_f16_e64 vcc_lo, 0.5, -m0        ; encoding: [0x6a,0x00,0x0a,0xd4,0xf0,0xfa,0x00,0x40]
+# W64: v_cmp_nlg_f16_e64 vcc, 0.5, -m0           ; encoding: [0x6a,0x00,0x0a,0xd4,0xf0,0xfa,0x00,0x40]
+0x6a,0x00,0x0a,0xd4,0xf0,0xfa,0x00,0x40
+
+# W32: v_cmp_nlg_f16_e64 ttmp14, -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x0a,0xd4,0xfd,0xd4,0x00,0x20]
+# W64: v_cmp_nlg_f16_e64 ttmp[14:15], -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x0a,0xd4,0xfd,0xd4,0x00,0x20]
+0x7a,0x02,0x0a,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmp_nlg_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x0a,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x7c,0x83,0x0a,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_nlg_f32_e64 s10, v1, v2             ; encoding: [0x0a,0x00,0x1a,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_nlg_f32_e64 s[10:11], v1, v2        ; encoding: [0x0a,0x00,0x1a,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x1a,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_nlg_f32_e64 s10, v255, v255         ; encoding: [0x0a,0x00,0x1a,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_nlg_f32_e64 s[10:11], v255, v255    ; encoding: [0x0a,0x00,0x1a,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x1a,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_nlg_f32_e64 s10, s1, s2             ; encoding: [0x0a,0x00,0x1a,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_nlg_f32_e64 s[10:11], s1, s2        ; encoding: [0x0a,0x00,0x1a,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x1a,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_nlg_f32_e64 s10, s105, s105         ; encoding: [0x0a,0x00,0x1a,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_nlg_f32_e64 s[10:11], s105, s105    ; encoding: [0x0a,0x00,0x1a,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x1a,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_nlg_f32_e64 s10, vcc_lo, ttmp15     ; encoding: [0x0a,0x00,0x1a,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_nlg_f32_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x1a,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x1a,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_nlg_f32_e64 s10, vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x1a,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_nlg_f32_e64 s[10:11], vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x1a,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x1a,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_nlg_f32_e64 s10, ttmp15, src_scc    ; encoding: [0x0a,0x00,0x1a,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_nlg_f32_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x1a,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x1a,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_nlg_f32_e64 s10, m0, 0.5            ; encoding: [0x0a,0x00,0x1a,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_nlg_f32_e64 s[10:11], m0, 0.5       ; encoding: [0x0a,0x00,0x1a,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x1a,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_nlg_f32_e64 s10, exec_lo, -1        ; encoding: [0x0a,0x00,0x1a,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_nlg_f32_e64 s[10:11], exec_lo, -1   ; encoding: [0x0a,0x00,0x1a,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x1a,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_nlg_f32_e64 s10, |exec_hi|, null    ; encoding: [0x0a,0x01,0x1a,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_nlg_f32_e64 s[10:11], |exec_hi|, null ; encoding: [0x0a,0x01,0x1a,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x01,0x1a,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_nlg_f32_e64 s10, null, exec_lo      ; encoding: [0x0a,0x00,0x1a,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_nlg_f32_e64 s[10:11], null, exec_lo ; encoding: [0x0a,0x00,0x1a,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x1a,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_nlg_f32_e64 s104, -1, exec_hi       ; encoding: [0x68,0x00,0x1a,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_nlg_f32_e64 s[104:105], -1, exec_hi ; encoding: [0x68,0x00,0x1a,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x1a,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_nlg_f32_e64 vcc_lo, 0.5, -m0        ; encoding: [0x6a,0x00,0x1a,0xd4,0xf0,0xfa,0x00,0x40]
+# W64: v_cmp_nlg_f32_e64 vcc, 0.5, -m0           ; encoding: [0x6a,0x00,0x1a,0xd4,0xf0,0xfa,0x00,0x40]
+0x6a,0x00,0x1a,0xd4,0xf0,0xfa,0x00,0x40
+
+# W32: v_cmp_nlg_f32_e64 ttmp14, -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x1a,0xd4,0xfd,0xd4,0x00,0x20]
+# W64: v_cmp_nlg_f32_e64 ttmp[14:15], -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x1a,0xd4,0xfd,0xd4,0x00,0x20]
+0x7a,0x02,0x1a,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmp_nlg_f32_e64 null, -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x1a,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0x7c,0x83,0x1a,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_nlg_f64_e64 s10, v[1:2], v[2:3]     ; encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_nlg_f64_e64 s[10:11], v[1:2], v[2:3] ; encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x2a,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_nlg_f64_e64 s10, v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x2a,0xd4,0xfe,0xfd,0x03,0x00]
+# W64: v_cmp_nlg_f64_e64 s[10:11], v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x2a,0xd4,0xfe,0xfd,0x03,0x00]
+0x0a,0x00,0x2a,0xd4,0xfe,0xfd,0x03,0x00
+
+# W32: v_cmp_nlg_f64_e64 s10, s[2:3], s[4:5]     ; encoding: [0x0a,0x00,0x2a,0xd4,0x02,0x08,0x00,0x00]
+# W64: v_cmp_nlg_f64_e64 s[10:11], s[2:3], s[4:5] ; encoding: [0x0a,0x00,0x2a,0xd4,0x02,0x08,0x00,0x00]
+0x0a,0x00,0x2a,0xd4,0x02,0x08,0x00,0x00
+
+# W32: v_cmp_nlg_f64_e64 s10, s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x2a,0xd4,0x68,0xd0,0x00,0x00]
+# W64: v_cmp_nlg_f64_e64 s[10:11], s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x2a,0xd4,0x68,0xd0,0x00,0x00]
+0x0a,0x00,0x2a,0xd4,0x68,0xd0,0x00,0x00
+
+# W32: v_cmp_nlg_f64_e64 s10, vcc, ttmp[14:15]   ; encoding: [0x0a,0x00,0x2a,0xd4,0x6a,0xf4,0x00,0x00]
+# W64: v_cmp_nlg_f64_e64 s[10:11], vcc, ttmp[14:15] ; encoding: [0x0a,0x00,0x2a,0xd4,0x6a,0xf4,0x00,0x00]
+0x0a,0x00,0x2a,0xd4,0x6a,0xf4,0x00,0x00
+
+# W32: v_cmp_nlg_f64_e64 s10, ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x2a,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_nlg_f64_e64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x2a,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x2a,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_nlg_f64_e64 s10, -|exec|, src_scc   ; encoding: [0x0a,0x01,0x2a,0xd4,0x7e,0xfa,0x01,0x20]
+# W64: v_cmp_nlg_f64_e64 s[10:11], -|exec|, src_scc ; encoding: [0x0a,0x01,0x2a,0xd4,0x7e,0xfa,0x01,0x20]
+0x0a,0x01,0x2a,0xd4,0x7e,0xfa,0x01,0x20
+
+# W32: v_cmp_nlg_f64_e64 s10, null, 0.5          ; encoding: [0x0a,0x00,0x2a,0xd4,0x7c,0xe0,0x01,0x00]
+# W64: v_cmp_nlg_f64_e64 s[10:11], null, 0.5     ; encoding: [0x0a,0x00,0x2a,0xd4,0x7c,0xe0,0x01,0x00]
+0x0a,0x00,0x2a,0xd4,0x7c,0xe0,0x01,0x00
+
+# W32: v_cmp_nlg_f64_e64 s104, -1, -1            ; encoding: [0x68,0x00,0x2a,0xd4,0xc1,0x82,0x01,0x00]
+# W64: v_cmp_nlg_f64_e64 s[104:105], -1, -1      ; encoding: [0x68,0x00,0x2a,0xd4,0xc1,0x82,0x01,0x00]
+0x68,0x00,0x2a,0xd4,0xc1,0x82,0x01,0x00
+
+# W32: v_cmp_nlg_f64_e64 vcc_lo, 0.5, null       ; encoding: [0x6a,0x00,0x2a,0xd4,0xf0,0xf8,0x00,0x00]
+# W64: v_cmp_nlg_f64_e64 vcc, 0.5, null          ; encoding: [0x6a,0x00,0x2a,0xd4,0xf0,0xf8,0x00,0x00]
+0x6a,0x00,0x2a,0xd4,0xf0,0xf8,0x00,0x00
+
+# W32: v_cmp_nlg_f64_e64 ttmp14, -|src_scc|, -|exec| ; encoding: [0x7a,0x03,0x2a,0xd4,0xfd,0xfc,0x00,0x60]
+# W64: v_cmp_nlg_f64_e64 ttmp[14:15], -|src_scc|, -|exec| ; encoding: [0x7a,0x03,0x2a,0xd4,0xfd,0xfc,0x00,0x60]
+0x7a,0x03,0x2a,0xd4,0xfd,0xfc,0x00,0x60
+
+# GFX12: v_cmp_nlg_f64_e64 null, 0xaf123456, -|vcc| clamp ; encoding: [0x7c,0x82,0x2a,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+0x7c,0x82,0x2a,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_nlt_f16_e64 s10, v1, v2             ; encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_nlt_f16_e64 s[10:11], v1, v2        ; encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x0e,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_nlt_f16_e64 s10, v255, v255         ; encoding: [0x0a,0x00,0x0e,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_nlt_f16_e64 s[10:11], v255, v255    ; encoding: [0x0a,0x00,0x0e,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x0e,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_nlt_f16_e64 s10, s1, s2             ; encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_nlt_f16_e64 s[10:11], s1, s2        ; encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x0e,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_nlt_f16_e64 s10, s105, s105         ; encoding: [0x0a,0x00,0x0e,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_nlt_f16_e64 s[10:11], s105, s105    ; encoding: [0x0a,0x00,0x0e,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x0e,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_nlt_f16_e64 s10, vcc_lo, ttmp15     ; encoding: [0x0a,0x00,0x0e,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_nlt_f16_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x0e,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x0e,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_nlt_f16_e64 s10, vcc_hi, 0xfe0b     ; encoding: [0x0a,0x00,0x0e,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_nlt_f16_e64 s[10:11], vcc_hi, 0xfe0b ; encoding: [0x0a,0x00,0x0e,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x0a,0x00,0x0e,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_nlt_f16_e64 s10, ttmp15, src_scc    ; encoding: [0x0a,0x00,0x0e,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_nlt_f16_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x0e,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x0e,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_nlt_f16_e64 s10, m0, 0.5            ; encoding: [0x0a,0x00,0x0e,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_nlt_f16_e64 s[10:11], m0, 0.5       ; encoding: [0x0a,0x00,0x0e,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x0e,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_nlt_f16_e64 s10, exec_lo, -1        ; encoding: [0x0a,0x00,0x0e,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_nlt_f16_e64 s[10:11], exec_lo, -1   ; encoding: [0x0a,0x00,0x0e,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x0e,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_nlt_f16_e64 s10, |exec_hi|, null    ; encoding: [0x0a,0x01,0x0e,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_nlt_f16_e64 s[10:11], |exec_hi|, null ; encoding: [0x0a,0x01,0x0e,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x01,0x0e,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_nlt_f16_e64 s10, null, exec_lo      ; encoding: [0x0a,0x00,0x0e,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_nlt_f16_e64 s[10:11], null, exec_lo ; encoding: [0x0a,0x00,0x0e,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x0e,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_nlt_f16_e64 s104, -1, exec_hi       ; encoding: [0x68,0x00,0x0e,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_nlt_f16_e64 s[104:105], -1, exec_hi ; encoding: [0x68,0x00,0x0e,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x0e,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_nlt_f16_e64 vcc_lo, 0.5, -m0        ; encoding: [0x6a,0x00,0x0e,0xd4,0xf0,0xfa,0x00,0x40]
+# W64: v_cmp_nlt_f16_e64 vcc, 0.5, -m0           ; encoding: [0x6a,0x00,0x0e,0xd4,0xf0,0xfa,0x00,0x40]
+0x6a,0x00,0x0e,0xd4,0xf0,0xfa,0x00,0x40
+
+# W32: v_cmp_nlt_f16_e64 ttmp14, -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x0e,0xd4,0xfd,0xd4,0x00,0x20]
+# W64: v_cmp_nlt_f16_e64 ttmp[14:15], -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x0e,0xd4,0xfd,0xd4,0x00,0x20]
+0x7a,0x02,0x0e,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmp_nlt_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x0e,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x7c,0x83,0x0e,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_nlt_f32_e64 s10, v1, v2             ; encoding: [0x0a,0x00,0x1e,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_nlt_f32_e64 s[10:11], v1, v2        ; encoding: [0x0a,0x00,0x1e,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x1e,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_nlt_f32_e64 s10, v255, v255         ; encoding: [0x0a,0x00,0x1e,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_nlt_f32_e64 s[10:11], v255, v255    ; encoding: [0x0a,0x00,0x1e,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x1e,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_nlt_f32_e64 s10, s1, s2             ; encoding: [0x0a,0x00,0x1e,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_nlt_f32_e64 s[10:11], s1, s2        ; encoding: [0x0a,0x00,0x1e,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x1e,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_nlt_f32_e64 s10, s105, s105         ; encoding: [0x0a,0x00,0x1e,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_nlt_f32_e64 s[10:11], s105, s105    ; encoding: [0x0a,0x00,0x1e,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x1e,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_nlt_f32_e64 s10, vcc_lo, ttmp15     ; encoding: [0x0a,0x00,0x1e,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_nlt_f32_e64 s[10:11], vcc_lo, ttmp15 ; encoding: [0x0a,0x00,0x1e,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x1e,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_nlt_f32_e64 s10, vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x1e,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_nlt_f32_e64 s[10:11], vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x1e,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x1e,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_nlt_f32_e64 s10, ttmp15, src_scc    ; encoding: [0x0a,0x00,0x1e,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_nlt_f32_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x1e,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x1e,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_nlt_f32_e64 s10, m0, 0.5            ; encoding: [0x0a,0x00,0x1e,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_nlt_f32_e64 s[10:11], m0, 0.5       ; encoding: [0x0a,0x00,0x1e,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x1e,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_nlt_f32_e64 s10, exec_lo, -1        ; encoding: [0x0a,0x00,0x1e,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_nlt_f32_e64 s[10:11], exec_lo, -1   ; encoding: [0x0a,0x00,0x1e,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x1e,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_nlt_f32_e64 s10, |exec_hi|, null    ; encoding: [0x0a,0x01,0x1e,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_nlt_f32_e64 s[10:11], |exec_hi|, null ; encoding: [0x0a,0x01,0x1e,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x01,0x1e,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_nlt_f32_e64 s10, null, exec_lo      ; encoding: [0x0a,0x00,0x1e,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_nlt_f32_e64 s[10:11], null, exec_lo ; encoding: [0x0a,0x00,0x1e,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x1e,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_nlt_f32_e64 s104, -1, exec_hi       ; encoding: [0x68,0x00,0x1e,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_nlt_f32_e64 s[104:105], -1, exec_hi ; encoding: [0x68,0x00,0x1e,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x1e,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_nlt_f32_e64 vcc_lo, 0.5, -m0        ; encoding: [0x6a,0x00,0x1e,0xd4,0xf0,0xfa,0x00,0x40]
+# W64: v_cmp_nlt_f32_e64 vcc, 0.5, -m0           ; encoding: [0x6a,0x00,0x1e,0xd4,0xf0,0xfa,0x00,0x40]
+0x6a,0x00,0x1e,0xd4,0xf0,0xfa,0x00,0x40
+
+# W32: v_cmp_nlt_f32_e64 ttmp14, -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x1e,0xd4,0xfd,0xd4,0x00,0x20]
+# W64: v_cmp_nlt_f32_e64 ttmp[14:15], -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x1e,0xd4,0xfd,0xd4,0x00,0x20]
+0x7a,0x02,0x1e,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmp_nlt_f32_e64 null, -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x1e,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0x7c,0x83,0x1e,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_nlt_f64_e64 s10, v[1:2], v[2:3]     ; encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_nlt_f64_e64 s[10:11], v[1:2], v[2:3] ; encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x2e,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_nlt_f64_e64 s10, v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x2e,0xd4,0xfe,0xfd,0x03,0x00]
+# W64: v_cmp_nlt_f64_e64 s[10:11], v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x2e,0xd4,0xfe,0xfd,0x03,0x00]
+0x0a,0x00,0x2e,0xd4,0xfe,0xfd,0x03,0x00
+
+# W32: v_cmp_nlt_f64_e64 s10, s[2:3], s[4:5]     ; encoding: [0x0a,0x00,0x2e,0xd4,0x02,0x08,0x00,0x00]
+# W64: v_cmp_nlt_f64_e64 s[10:11], s[2:3], s[4:5] ; encoding: [0x0a,0x00,0x2e,0xd4,0x02,0x08,0x00,0x00]
+0x0a,0x00,0x2e,0xd4,0x02,0x08,0x00,0x00
+
+# W32: v_cmp_nlt_f64_e64 s10, s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x2e,0xd4,0x68,0xd0,0x00,0x00]
+# W64: v_cmp_nlt_f64_e64 s[10:11], s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x2e,0xd4,0x68,0xd0,0x00,0x00]
+0x0a,0x00,0x2e,0xd4,0x68,0xd0,0x00,0x00
+
+# W32: v_cmp_nlt_f64_e64 s10, vcc, ttmp[14:15]   ; encoding: [0x0a,0x00,0x2e,0xd4,0x6a,0xf4,0x00,0x00]
+# W64: v_cmp_nlt_f64_e64 s[10:11], vcc, ttmp[14:15] ; encoding: [0x0a,0x00,0x2e,0xd4,0x6a,0xf4,0x00,0x00]
+0x0a,0x00,0x2e,0xd4,0x6a,0xf4,0x00,0x00
+
+# W32: v_cmp_nlt_f64_e64 s10, ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x2e,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_nlt_f64_e64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x2e,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x2e,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_nlt_f64_e64 s10, -|exec|, src_scc   ; encoding: [0x0a,0x01,0x2e,0xd4,0x7e,0xfa,0x01,0x20]
+# W64: v_cmp_nlt_f64_e64 s[10:11], -|exec|, src_scc ; encoding: [0x0a,0x01,0x2e,0xd4,0x7e,0xfa,0x01,0x20]
+0x0a,0x01,0x2e,0xd4,0x7e,0xfa,0x01,0x20
+
+# W32: v_cmp_nlt_f64_e64 s10, null, 0.5          ; encoding: [0x0a,0x00,0x2e,0xd4,0x7c,0xe0,0x01,0x00]
+# W64: v_cmp_nlt_f64_e64 s[10:11], null, 0.5     ; encoding: [0x0a,0x00,0x2e,0xd4,0x7c,0xe0,0x01,0x00]
+0x0a,0x00,0x2e,0xd4,0x7c,0xe0,0x01,0x00
+
+# W32: v_cmp_nlt_f64_e64 s104, -1, -1            ; encoding: [0x68,0x00,0x2e,0xd4,0xc1,0x82,0x01,0x00]
+# W64: v_cmp_nlt_f64_e64 s[104:105], -1, -1      ; encoding: [0x68,0x00,0x2e,0xd4,0xc1,0x82,0x01,0x00]
+0x68,0x00,0x2e,0xd4,0xc1,0x82,0x01,0x00
+
+# W32: v_cmp_nlt_f64_e64 vcc_lo, 0.5, null       ; encoding: [0x6a,0x00,0x2e,0xd4,0xf0,0xf8,0x00,0x00]
+# W64: v_cmp_nlt_f64_e64 vcc, 0.5, null          ; encoding: [0x6a,0x00,0x2e,0xd4,0xf0,0xf8,0x00,0x00]
+0x6a,0x00,0x2e,0xd4,0xf0,0xf8,0x00,0x00
+
+# W32: v_cmp_nlt_f64_e64 ttmp14, -|src_scc|, -|exec| ; encoding: [0x7a,0x03,0x2e,0xd4,0xfd,0xfc,0x00,0x60]
+# W64: v_cmp_nlt_f64_e64 ttmp[14:15], -|src_scc|, -|exec| ; encoding: [0x7a,0x03,0x2e,0xd4,0xfd,0xfc,0x00,0x60]
+0x7a,0x03,0x2e,0xd4,0xfd,0xfc,0x00,0x60
+
+# GFX12: v_cmp_nlt_f64_e64 null, 0xaf123456, -|vcc| clamp ; encoding: [0x7c,0x82,0x2e,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+0x7c,0x82,0x2e,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_o_f16_e64 s10, v1, v2               ; encoding: [0x0a,0x00,0x07,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_o_f16_e64 s[10:11], v1, v2          ; encoding: [0x0a,0x00,0x07,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x07,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_o_f16_e64 s10, v255, v255           ; encoding: [0x0a,0x00,0x07,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_o_f16_e64 s[10:11], v255, v255      ; encoding: [0x0a,0x00,0x07,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x07,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_o_f16_e64 s10, s1, s2               ; encoding: [0x0a,0x00,0x07,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_o_f16_e64 s[10:11], s1, s2          ; encoding: [0x0a,0x00,0x07,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x07,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_o_f16_e64 s10, s105, s105           ; encoding: [0x0a,0x00,0x07,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_o_f16_e64 s[10:11], s105, s105      ; encoding: [0x0a,0x00,0x07,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x07,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_o_f16_e64 s10, vcc_lo, ttmp15       ; encoding: [0x0a,0x00,0x07,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_o_f16_e64 s[10:11], vcc_lo, ttmp15  ; encoding: [0x0a,0x00,0x07,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x07,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_o_f16_e64 s10, vcc_hi, 0xfe0b       ; encoding: [0x0a,0x00,0x07,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_o_f16_e64 s[10:11], vcc_hi, 0xfe0b  ; encoding: [0x0a,0x00,0x07,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x0a,0x00,0x07,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_o_f16_e64 s10, ttmp15, src_scc      ; encoding: [0x0a,0x00,0x07,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_o_f16_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x07,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x07,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_o_f16_e64 s10, m0, 0.5              ; encoding: [0x0a,0x00,0x07,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_o_f16_e64 s[10:11], m0, 0.5         ; encoding: [0x0a,0x00,0x07,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x07,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_o_f16_e64 s10, exec_lo, -1          ; encoding: [0x0a,0x00,0x07,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_o_f16_e64 s[10:11], exec_lo, -1     ; encoding: [0x0a,0x00,0x07,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x07,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_o_f16_e64 s10, |exec_hi|, null      ; encoding: [0x0a,0x01,0x07,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_o_f16_e64 s[10:11], |exec_hi|, null ; encoding: [0x0a,0x01,0x07,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x01,0x07,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_o_f16_e64 s10, null, exec_lo        ; encoding: [0x0a,0x00,0x07,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_o_f16_e64 s[10:11], null, exec_lo   ; encoding: [0x0a,0x00,0x07,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x07,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_o_f16_e64 s104, -1, exec_hi         ; encoding: [0x68,0x00,0x07,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_o_f16_e64 s[104:105], -1, exec_hi   ; encoding: [0x68,0x00,0x07,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x07,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_o_f16_e64 vcc_lo, 0.5, -m0          ; encoding: [0x6a,0x00,0x07,0xd4,0xf0,0xfa,0x00,0x40]
+# W64: v_cmp_o_f16_e64 vcc, 0.5, -m0             ; encoding: [0x6a,0x00,0x07,0xd4,0xf0,0xfa,0x00,0x40]
+0x6a,0x00,0x07,0xd4,0xf0,0xfa,0x00,0x40
+
+# W32: v_cmp_o_f16_e64 ttmp14, -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x07,0xd4,0xfd,0xd4,0x00,0x20]
+# W64: v_cmp_o_f16_e64 ttmp[14:15], -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x07,0xd4,0xfd,0xd4,0x00,0x20]
+0x7a,0x02,0x07,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmp_o_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x07,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x7c,0x83,0x07,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_o_f32_e64 s10, v1, v2               ; encoding: [0x0a,0x00,0x17,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_o_f32_e64 s[10:11], v1, v2          ; encoding: [0x0a,0x00,0x17,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x17,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_o_f32_e64 s10, v255, v255           ; encoding: [0x0a,0x00,0x17,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_o_f32_e64 s[10:11], v255, v255      ; encoding: [0x0a,0x00,0x17,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x17,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_o_f32_e64 s10, s1, s2               ; encoding: [0x0a,0x00,0x17,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_o_f32_e64 s[10:11], s1, s2          ; encoding: [0x0a,0x00,0x17,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x17,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_o_f32_e64 s10, s105, s105           ; encoding: [0x0a,0x00,0x17,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_o_f32_e64 s[10:11], s105, s105      ; encoding: [0x0a,0x00,0x17,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x17,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_o_f32_e64 s10, vcc_lo, ttmp15       ; encoding: [0x0a,0x00,0x17,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_o_f32_e64 s[10:11], vcc_lo, ttmp15  ; encoding: [0x0a,0x00,0x17,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x17,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_o_f32_e64 s10, vcc_hi, 0xaf123456   ; encoding: [0x0a,0x00,0x17,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_o_f32_e64 s[10:11], vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x17,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x17,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_o_f32_e64 s10, ttmp15, src_scc      ; encoding: [0x0a,0x00,0x17,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_o_f32_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x17,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x17,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_o_f32_e64 s10, m0, 0.5              ; encoding: [0x0a,0x00,0x17,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_o_f32_e64 s[10:11], m0, 0.5         ; encoding: [0x0a,0x00,0x17,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x17,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_o_f32_e64 s10, exec_lo, -1          ; encoding: [0x0a,0x00,0x17,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_o_f32_e64 s[10:11], exec_lo, -1     ; encoding: [0x0a,0x00,0x17,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x17,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_o_f32_e64 s10, |exec_hi|, null      ; encoding: [0x0a,0x01,0x17,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_o_f32_e64 s[10:11], |exec_hi|, null ; encoding: [0x0a,0x01,0x17,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x01,0x17,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_o_f32_e64 s10, null, exec_lo        ; encoding: [0x0a,0x00,0x17,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_o_f32_e64 s[10:11], null, exec_lo   ; encoding: [0x0a,0x00,0x17,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x17,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_o_f32_e64 s104, -1, exec_hi         ; encoding: [0x68,0x00,0x17,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_o_f32_e64 s[104:105], -1, exec_hi   ; encoding: [0x68,0x00,0x17,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x17,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_o_f32_e64 vcc_lo, 0.5, -m0          ; encoding: [0x6a,0x00,0x17,0xd4,0xf0,0xfa,0x00,0x40]
+# W64: v_cmp_o_f32_e64 vcc, 0.5, -m0             ; encoding: [0x6a,0x00,0x17,0xd4,0xf0,0xfa,0x00,0x40]
+0x6a,0x00,0x17,0xd4,0xf0,0xfa,0x00,0x40
+
+# W32: v_cmp_o_f32_e64 ttmp14, -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x17,0xd4,0xfd,0xd4,0x00,0x20]
+# W64: v_cmp_o_f32_e64 ttmp[14:15], -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x17,0xd4,0xfd,0xd4,0x00,0x20]
+0x7a,0x02,0x17,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmp_o_f32_e64 null, -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x17,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0x7c,0x83,0x17,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_o_f64_e64 s10, v[1:2], v[2:3]       ; encoding: [0x0a,0x00,0x27,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_o_f64_e64 s[10:11], v[1:2], v[2:3]  ; encoding: [0x0a,0x00,0x27,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x27,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_o_f64_e64 s10, v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x27,0xd4,0xfe,0xfd,0x03,0x00]
+# W64: v_cmp_o_f64_e64 s[10:11], v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x27,0xd4,0xfe,0xfd,0x03,0x00]
+0x0a,0x00,0x27,0xd4,0xfe,0xfd,0x03,0x00
+
+# W32: v_cmp_o_f64_e64 s10, s[2:3], s[4:5]       ; encoding: [0x0a,0x00,0x27,0xd4,0x02,0x08,0x00,0x00]
+# W64: v_cmp_o_f64_e64 s[10:11], s[2:3], s[4:5]  ; encoding: [0x0a,0x00,0x27,0xd4,0x02,0x08,0x00,0x00]
+0x0a,0x00,0x27,0xd4,0x02,0x08,0x00,0x00
+
+# W32: v_cmp_o_f64_e64 s10, s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x27,0xd4,0x68,0xd0,0x00,0x00]
+# W64: v_cmp_o_f64_e64 s[10:11], s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x27,0xd4,0x68,0xd0,0x00,0x00]
+0x0a,0x00,0x27,0xd4,0x68,0xd0,0x00,0x00
+
+# W32: v_cmp_o_f64_e64 s10, vcc, ttmp[14:15]     ; encoding: [0x0a,0x00,0x27,0xd4,0x6a,0xf4,0x00,0x00]
+# W64: v_cmp_o_f64_e64 s[10:11], vcc, ttmp[14:15] ; encoding: [0x0a,0x00,0x27,0xd4,0x6a,0xf4,0x00,0x00]
+0x0a,0x00,0x27,0xd4,0x6a,0xf4,0x00,0x00
+
+# W32: v_cmp_o_f64_e64 s10, ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x27,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_o_f64_e64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x27,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x27,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_o_f64_e64 s10, -|exec|, src_scc     ; encoding: [0x0a,0x01,0x27,0xd4,0x7e,0xfa,0x01,0x20]
+# W64: v_cmp_o_f64_e64 s[10:11], -|exec|, src_scc ; encoding: [0x0a,0x01,0x27,0xd4,0x7e,0xfa,0x01,0x20]
+0x0a,0x01,0x27,0xd4,0x7e,0xfa,0x01,0x20
+
+# W32: v_cmp_o_f64_e64 s10, null, 0.5            ; encoding: [0x0a,0x00,0x27,0xd4,0x7c,0xe0,0x01,0x00]
+# W64: v_cmp_o_f64_e64 s[10:11], null, 0.5       ; encoding: [0x0a,0x00,0x27,0xd4,0x7c,0xe0,0x01,0x00]
+0x0a,0x00,0x27,0xd4,0x7c,0xe0,0x01,0x00
+
+# W32: v_cmp_o_f64_e64 s104, -1, -1              ; encoding: [0x68,0x00,0x27,0xd4,0xc1,0x82,0x01,0x00]
+# W64: v_cmp_o_f64_e64 s[104:105], -1, -1        ; encoding: [0x68,0x00,0x27,0xd4,0xc1,0x82,0x01,0x00]
+0x68,0x00,0x27,0xd4,0xc1,0x82,0x01,0x00
+
+# W32: v_cmp_o_f64_e64 vcc_lo, 0.5, null         ; encoding: [0x6a,0x00,0x27,0xd4,0xf0,0xf8,0x00,0x00]
+# W64: v_cmp_o_f64_e64 vcc, 0.5, null            ; encoding: [0x6a,0x00,0x27,0xd4,0xf0,0xf8,0x00,0x00]
+0x6a,0x00,0x27,0xd4,0xf0,0xf8,0x00,0x00
+
+# W32: v_cmp_o_f64_e64 ttmp14, -|src_scc|, -|exec| ; encoding: [0x7a,0x03,0x27,0xd4,0xfd,0xfc,0x00,0x60]
+# W64: v_cmp_o_f64_e64 ttmp[14:15], -|src_scc|, -|exec| ; encoding: [0x7a,0x03,0x27,0xd4,0xfd,0xfc,0x00,0x60]
+0x7a,0x03,0x27,0xd4,0xfd,0xfc,0x00,0x60
+
+# GFX12: v_cmp_o_f64_e64 null, 0xaf123456, -|vcc| clamp ; encoding: [0x7c,0x82,0x27,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+0x7c,0x82,0x27,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_u_f16_e64 s10, v1, v2               ; encoding: [0x0a,0x00,0x08,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_u_f16_e64 s[10:11], v1, v2          ; encoding: [0x0a,0x00,0x08,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x08,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_u_f16_e64 s10, v255, v255           ; encoding: [0x0a,0x00,0x08,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_u_f16_e64 s[10:11], v255, v255      ; encoding: [0x0a,0x00,0x08,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x08,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_u_f16_e64 s10, s1, s2               ; encoding: [0x0a,0x00,0x08,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_u_f16_e64 s[10:11], s1, s2          ; encoding: [0x0a,0x00,0x08,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x08,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_u_f16_e64 s10, s105, s105           ; encoding: [0x0a,0x00,0x08,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_u_f16_e64 s[10:11], s105, s105      ; encoding: [0x0a,0x00,0x08,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x08,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_u_f16_e64 s10, vcc_lo, ttmp15       ; encoding: [0x0a,0x00,0x08,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_u_f16_e64 s[10:11], vcc_lo, ttmp15  ; encoding: [0x0a,0x00,0x08,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x08,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_u_f16_e64 s10, vcc_hi, 0xfe0b       ; encoding: [0x0a,0x00,0x08,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_u_f16_e64 s[10:11], vcc_hi, 0xfe0b  ; encoding: [0x0a,0x00,0x08,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x0a,0x00,0x08,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_u_f16_e64 s10, ttmp15, src_scc      ; encoding: [0x0a,0x00,0x08,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_u_f16_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x08,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x08,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_u_f16_e64 s10, m0, 0.5              ; encoding: [0x0a,0x00,0x08,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_u_f16_e64 s[10:11], m0, 0.5         ; encoding: [0x0a,0x00,0x08,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x08,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_u_f16_e64 s10, exec_lo, -1          ; encoding: [0x0a,0x00,0x08,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_u_f16_e64 s[10:11], exec_lo, -1     ; encoding: [0x0a,0x00,0x08,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x08,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_u_f16_e64 s10, |exec_hi|, null      ; encoding: [0x0a,0x01,0x08,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_u_f16_e64 s[10:11], |exec_hi|, null ; encoding: [0x0a,0x01,0x08,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x01,0x08,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_u_f16_e64 s10, null, exec_lo        ; encoding: [0x0a,0x00,0x08,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_u_f16_e64 s[10:11], null, exec_lo   ; encoding: [0x0a,0x00,0x08,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x08,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_u_f16_e64 s104, -1, exec_hi         ; encoding: [0x68,0x00,0x08,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_u_f16_e64 s[104:105], -1, exec_hi   ; encoding: [0x68,0x00,0x08,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x08,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_u_f16_e64 vcc_lo, 0.5, -m0          ; encoding: [0x6a,0x00,0x08,0xd4,0xf0,0xfa,0x00,0x40]
+# W64: v_cmp_u_f16_e64 vcc, 0.5, -m0             ; encoding: [0x6a,0x00,0x08,0xd4,0xf0,0xfa,0x00,0x40]
+0x6a,0x00,0x08,0xd4,0xf0,0xfa,0x00,0x40
+
+# W32: v_cmp_u_f16_e64 ttmp14, -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x08,0xd4,0xfd,0xd4,0x00,0x20]
+# W64: v_cmp_u_f16_e64 ttmp[14:15], -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x08,0xd4,0xfd,0xd4,0x00,0x20]
+0x7a,0x02,0x08,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmp_u_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x08,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x7c,0x83,0x08,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_u_f32_e64 s10, v1, v2               ; encoding: [0x0a,0x00,0x18,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_u_f32_e64 s[10:11], v1, v2          ; encoding: [0x0a,0x00,0x18,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x18,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_u_f32_e64 s10, v255, v255           ; encoding: [0x0a,0x00,0x18,0xd4,0xff,0xff,0x03,0x00]
+# W64: v_cmp_u_f32_e64 s[10:11], v255, v255      ; encoding: [0x0a,0x00,0x18,0xd4,0xff,0xff,0x03,0x00]
+0x0a,0x00,0x18,0xd4,0xff,0xff,0x03,0x00
+
+# W32: v_cmp_u_f32_e64 s10, s1, s2               ; encoding: [0x0a,0x00,0x18,0xd4,0x01,0x04,0x00,0x00]
+# W64: v_cmp_u_f32_e64 s[10:11], s1, s2          ; encoding: [0x0a,0x00,0x18,0xd4,0x01,0x04,0x00,0x00]
+0x0a,0x00,0x18,0xd4,0x01,0x04,0x00,0x00
+
+# W32: v_cmp_u_f32_e64 s10, s105, s105           ; encoding: [0x0a,0x00,0x18,0xd4,0x69,0xd2,0x00,0x00]
+# W64: v_cmp_u_f32_e64 s[10:11], s105, s105      ; encoding: [0x0a,0x00,0x18,0xd4,0x69,0xd2,0x00,0x00]
+0x0a,0x00,0x18,0xd4,0x69,0xd2,0x00,0x00
+
+# W32: v_cmp_u_f32_e64 s10, vcc_lo, ttmp15       ; encoding: [0x0a,0x00,0x18,0xd4,0x6a,0xf6,0x00,0x00]
+# W64: v_cmp_u_f32_e64 s[10:11], vcc_lo, ttmp15  ; encoding: [0x0a,0x00,0x18,0xd4,0x6a,0xf6,0x00,0x00]
+0x0a,0x00,0x18,0xd4,0x6a,0xf6,0x00,0x00
+
+# W32: v_cmp_u_f32_e64 s10, vcc_hi, 0xaf123456   ; encoding: [0x0a,0x00,0x18,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_u_f32_e64 s[10:11], vcc_hi, 0xaf123456 ; encoding: [0x0a,0x00,0x18,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x18,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_u_f32_e64 s10, ttmp15, src_scc      ; encoding: [0x0a,0x00,0x18,0xd4,0x7b,0xfa,0x01,0x00]
+# W64: v_cmp_u_f32_e64 s[10:11], ttmp15, src_scc ; encoding: [0x0a,0x00,0x18,0xd4,0x7b,0xfa,0x01,0x00]
+0x0a,0x00,0x18,0xd4,0x7b,0xfa,0x01,0x00
+
+# W32: v_cmp_u_f32_e64 s10, m0, 0.5              ; encoding: [0x0a,0x00,0x18,0xd4,0x7d,0xe0,0x01,0x00]
+# W64: v_cmp_u_f32_e64 s[10:11], m0, 0.5         ; encoding: [0x0a,0x00,0x18,0xd4,0x7d,0xe0,0x01,0x00]
+0x0a,0x00,0x18,0xd4,0x7d,0xe0,0x01,0x00
+
+# W32: v_cmp_u_f32_e64 s10, exec_lo, -1          ; encoding: [0x0a,0x00,0x18,0xd4,0x7e,0x82,0x01,0x00]
+# W64: v_cmp_u_f32_e64 s[10:11], exec_lo, -1     ; encoding: [0x0a,0x00,0x18,0xd4,0x7e,0x82,0x01,0x00]
+0x0a,0x00,0x18,0xd4,0x7e,0x82,0x01,0x00
+
+# W32: v_cmp_u_f32_e64 s10, |exec_hi|, null      ; encoding: [0x0a,0x01,0x18,0xd4,0x7f,0xf8,0x00,0x00]
+# W64: v_cmp_u_f32_e64 s[10:11], |exec_hi|, null ; encoding: [0x0a,0x01,0x18,0xd4,0x7f,0xf8,0x00,0x00]
+0x0a,0x01,0x18,0xd4,0x7f,0xf8,0x00,0x00
+
+# W32: v_cmp_u_f32_e64 s10, null, exec_lo        ; encoding: [0x0a,0x00,0x18,0xd4,0x7c,0xfc,0x00,0x00]
+# W64: v_cmp_u_f32_e64 s[10:11], null, exec_lo   ; encoding: [0x0a,0x00,0x18,0xd4,0x7c,0xfc,0x00,0x00]
+0x0a,0x00,0x18,0xd4,0x7c,0xfc,0x00,0x00
+
+# W32: v_cmp_u_f32_e64 s104, -1, exec_hi         ; encoding: [0x68,0x00,0x18,0xd4,0xc1,0xfe,0x00,0x00]
+# W64: v_cmp_u_f32_e64 s[104:105], -1, exec_hi   ; encoding: [0x68,0x00,0x18,0xd4,0xc1,0xfe,0x00,0x00]
+0x68,0x00,0x18,0xd4,0xc1,0xfe,0x00,0x00
+
+# W32: v_cmp_u_f32_e64 vcc_lo, 0.5, -m0          ; encoding: [0x6a,0x00,0x18,0xd4,0xf0,0xfa,0x00,0x40]
+# W64: v_cmp_u_f32_e64 vcc, 0.5, -m0             ; encoding: [0x6a,0x00,0x18,0xd4,0xf0,0xfa,0x00,0x40]
+0x6a,0x00,0x18,0xd4,0xf0,0xfa,0x00,0x40
+
+# W32: v_cmp_u_f32_e64 ttmp14, -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x18,0xd4,0xfd,0xd4,0x00,0x20]
+# W64: v_cmp_u_f32_e64 ttmp[14:15], -src_scc, |vcc_lo| ; encoding: [0x7a,0x02,0x18,0xd4,0xfd,0xd4,0x00,0x20]
+0x7a,0x02,0x18,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmp_u_f32_e64 null, -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x18,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0x7c,0x83,0x18,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_u_f64_e64 s10, v[1:2], v[2:3]       ; encoding: [0x0a,0x00,0x28,0xd4,0x01,0x05,0x02,0x00]
+# W64: v_cmp_u_f64_e64 s[10:11], v[1:2], v[2:3]  ; encoding: [0x0a,0x00,0x28,0xd4,0x01,0x05,0x02,0x00]
+0x0a,0x00,0x28,0xd4,0x01,0x05,0x02,0x00
+
+# W32: v_cmp_u_f64_e64 s10, v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x28,0xd4,0xfe,0xfd,0x03,0x00]
+# W64: v_cmp_u_f64_e64 s[10:11], v[254:255], v[254:255] ; encoding: [0x0a,0x00,0x28,0xd4,0xfe,0xfd,0x03,0x00]
+0x0a,0x00,0x28,0xd4,0xfe,0xfd,0x03,0x00
+
+# W32: v_cmp_u_f64_e64 s10, s[2:3], s[4:5]       ; encoding: [0x0a,0x00,0x28,0xd4,0x02,0x08,0x00,0x00]
+# W64: v_cmp_u_f64_e64 s[10:11], s[2:3], s[4:5]  ; encoding: [0x0a,0x00,0x28,0xd4,0x02,0x08,0x00,0x00]
+0x0a,0x00,0x28,0xd4,0x02,0x08,0x00,0x00
+
+# W32: v_cmp_u_f64_e64 s10, s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x28,0xd4,0x68,0xd0,0x00,0x00]
+# W64: v_cmp_u_f64_e64 s[10:11], s[104:105], s[104:105] ; encoding: [0x0a,0x00,0x28,0xd4,0x68,0xd0,0x00,0x00]
+0x0a,0x00,0x28,0xd4,0x68,0xd0,0x00,0x00
+
+# W32: v_cmp_u_f64_e64 s10, vcc, ttmp[14:15]     ; encoding: [0x0a,0x00,0x28,0xd4,0x6a,0xf4,0x00,0x00]
+# W64: v_cmp_u_f64_e64 s[10:11], vcc, ttmp[14:15] ; encoding: [0x0a,0x00,0x28,0xd4,0x6a,0xf4,0x00,0x00]
+0x0a,0x00,0x28,0xd4,0x6a,0xf4,0x00,0x00
+
+# W32: v_cmp_u_f64_e64 s10, ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x28,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_u_f64_e64 s[10:11], ttmp[14:15], 0xaf123456 ; encoding: [0x0a,0x00,0x28,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x0a,0x00,0x28,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_u_f64_e64 s10, -|exec|, src_scc     ; encoding: [0x0a,0x01,0x28,0xd4,0x7e,0xfa,0x01,0x20]
+# W64: v_cmp_u_f64_e64 s[10:11], -|exec|, src_scc ; encoding: [0x0a,0x01,0x28,0xd4,0x7e,0xfa,0x01,0x20]
+0x0a,0x01,0x28,0xd4,0x7e,0xfa,0x01,0x20
+
+# W32: v_cmp_u_f64_e64 s10, null, 0.5            ; encoding: [0x0a,0x00,0x28,0xd4,0x7c,0xe0,0x01,0x00]
+# W64: v_cmp_u_f64_e64 s[10:11], null, 0.5       ; encoding: [0x0a,0x00,0x28,0xd4,0x7c,0xe0,0x01,0x00]
+0x0a,0x00,0x28,0xd4,0x7c,0xe0,0x01,0x00
+
+# W32: v_cmp_u_f64_e64 s104, -1, -1              ; encoding: [0x68,0x00,0x28,0xd4,0xc1,0x82,0x01,0x00]
+# W64: v_cmp_u_f64_e64 s[104:105], -1, -1        ; encoding: [0x68,0x00,0x28,0xd4,0xc1,0x82,0x01,0x00]
+0x68,0x00,0x28,0xd4,0xc1,0x82,0x01,0x00
+
+# W32: v_cmp_u_f64_e64 vcc_lo, 0.5, null         ; encoding: [0x6a,0x00,0x28,0xd4,0xf0,0xf8,0x00,0x00]
+# W64: v_cmp_u_f64_e64 vcc, 0.5, null            ; encoding: [0x6a,0x00,0x28,0xd4,0xf0,0xf8,0x00,0x00]
+0x6a,0x00,0x28,0xd4,0xf0,0xf8,0x00,0x00
+
+# W32: v_cmp_u_f64_e64 ttmp14, -|src_scc|, -|exec| ; encoding: [0x7a,0x03,0x28,0xd4,0xfd,0xfc,0x00,0x60]
+# W64: v_cmp_u_f64_e64 ttmp[14:15], -|src_scc|, -|exec| ; encoding: [0x7a,0x03,0x28,0xd4,0xfd,0xfc,0x00,0x60]
+0x7a,0x03,0x28,0xd4,0xfd,0xfc,0x00,0x60
+
+# GFX12: v_cmp_u_f64_e64 null, 0xaf123456, -|vcc| clamp ; encoding: [0x7c,0x82,0x28,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+0x7c,0x82,0x28,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp16.txt
new file mode 100644
index 000000000000..3edfb4a97862
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp16.txt
@@ -0,0 +1,2972 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32 %s
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64 %s
+
+# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_class_f16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_class_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_class_f16_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_class_f16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_class_f16_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_cmp_class_f16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_class_f16_e64_dpp null, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30]
+0x7c,0x01,0x7d,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_class_f32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_class_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_class_f32_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_class_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_class_f32_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_class_f32_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_class_f32_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_class_f32_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_class_f32_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_class_f32_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_class_f32_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_class_f32_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_class_f32_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_class_f32_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_class_f32_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_class_f32_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_class_f32_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_class_f32_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_class_f32_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_class_f32_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_class_f32_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_class_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_class_f32_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_class_f32_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x6a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_class_f32_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_cmp_class_f32_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_class_f32_e64_dpp null, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x01,0x7e,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30]
+0x7c,0x01,0x7e,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_eq_f16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_eq_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_eq_f16_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_eq_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x6a,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_eq_f16_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7a,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7c,0x83,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_eq_f32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_eq_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_eq_f32_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_eq_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_eq_f32_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_eq_f32_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_eq_f32_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_eq_f32_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_eq_f32_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_eq_f32_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_eq_f32_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_eq_f32_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_eq_f32_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_eq_f32_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_eq_f32_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_eq_f32_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_eq_f32_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_eq_f32_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_eq_f32_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_eq_f32_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_eq_f32_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_eq_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_eq_f32_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x12,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_eq_f32_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x12,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x6a,0x01,0x12,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_eq_f32_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x12,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64: v_cmp_eq_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x12,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7a,0x02,0x12,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_eq_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x12,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7c,0x83,0x12,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_eq_i16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_eq_i16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_eq_i16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_eq_i16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_eq_i16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_eq_i16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_eq_i16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_eq_i16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_eq_i16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_eq_i16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_eq_i16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_eq_i16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_eq_i16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_eq_i16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_eq_i16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_eq_i16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_eq_i16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_eq_i16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_eq_i16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_eq_i16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_eq_i16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_eq_i16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_eq_i16_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_eq_i16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x6a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_eq_i16_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_cmp_eq_i16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7a,0x00,0x32,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_eq_i16_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x00,0x32,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7c,0x00,0x32,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_eq_i32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_eq_i32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_eq_i32_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_eq_i32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_eq_i32_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_eq_i32_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_eq_i32_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_eq_i32_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_eq_i32_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_eq_i32_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_eq_i32_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_eq_i32_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_eq_i32_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_eq_i32_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_eq_i32_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_eq_i32_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_eq_i32_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_eq_i32_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_eq_i32_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_eq_i32_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_eq_i32_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_eq_i32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_eq_i32_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_eq_i32_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x6a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_eq_i32_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_cmp_eq_i32_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7a,0x00,0x42,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_eq_i32_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x00,0x42,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7c,0x00,0x42,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_eq_u16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_eq_u16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_eq_u16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_eq_u16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_eq_u16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_eq_u16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_eq_u16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_eq_u16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_eq_u16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_eq_u16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_eq_u16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_eq_u16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_eq_u16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_eq_u16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_eq_u16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_eq_u16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_eq_u16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_eq_u16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_eq_u16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_eq_u16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_eq_u16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_eq_u16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_eq_u16_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_eq_u16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x6a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_eq_u16_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_cmp_eq_u16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7a,0x00,0x3a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_eq_u16_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x00,0x3a,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7c,0x00,0x3a,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_eq_u32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_eq_u32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_eq_u32_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_eq_u32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_eq_u32_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_eq_u32_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_eq_u32_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_eq_u32_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_eq_u32_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_eq_u32_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_eq_u32_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_eq_u32_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_eq_u32_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_eq_u32_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_eq_u32_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_eq_u32_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_eq_u32_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_eq_u32_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_eq_u32_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_eq_u32_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_eq_u32_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_eq_u32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_eq_u32_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_eq_u32_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x6a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_eq_u32_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_cmp_eq_u32_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7a,0x00,0x4a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_eq_u32_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x00,0x4a,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7c,0x00,0x4a,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_ge_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_ge_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_ge_f16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_ge_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_ge_f16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_ge_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_ge_f16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_ge_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_ge_f16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_ge_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_ge_f16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_ge_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_ge_f16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_ge_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_ge_f16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_ge_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_ge_f16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_ge_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_ge_f16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_ge_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_ge_f16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_ge_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x06,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_ge_f16_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x06,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_ge_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x06,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x6a,0x01,0x06,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_ge_f16_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x06,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64: v_cmp_ge_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x06,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7a,0x02,0x06,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_ge_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x06,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7c,0x83,0x06,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_ge_f32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_ge_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_ge_f32_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_ge_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_ge_f32_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_ge_f32_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_ge_f32_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_ge_f32_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_ge_f32_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_ge_f32_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_ge_f32_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_ge_f32_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_ge_f32_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_ge_f32_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_ge_f32_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_ge_f32_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_ge_f32_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_ge_f32_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_ge_f32_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_ge_f32_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_ge_f32_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_ge_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x16,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_ge_f32_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x16,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_ge_f32_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x16,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x6a,0x01,0x16,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_ge_f32_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x16,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64: v_cmp_ge_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x16,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7a,0x02,0x16,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_ge_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x16,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7c,0x83,0x16,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_ge_i16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_ge_i16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_ge_i16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_ge_i16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_ge_i16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_ge_i16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_ge_i16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_ge_i16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_ge_i16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_ge_i16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_ge_i16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_ge_i16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_ge_i16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_ge_i16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_ge_i16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_ge_i16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_ge_i16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_ge_i16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_ge_i16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_ge_i16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_ge_i16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_ge_i16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_ge_i16_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_ge_i16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x6a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_ge_i16_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_cmp_ge_i16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_ge_i16_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x00,0x36,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7c,0x00,0x36,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_ge_i32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_ge_i32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_ge_i32_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_ge_i32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_ge_i32_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_ge_i32_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_ge_i32_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_ge_i32_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_ge_i32_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_ge_i32_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_ge_i32_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_ge_i32_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_ge_i32_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_ge_i32_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_ge_i32_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_ge_i32_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_ge_i32_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_ge_i32_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_ge_i32_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_ge_i32_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_ge_i32_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_ge_i32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_ge_i32_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_ge_i32_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x6a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_ge_i32_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_cmp_ge_i32_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7a,0x00,0x46,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_ge_i32_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x00,0x46,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7c,0x00,0x46,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_ge_u16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_ge_u16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_ge_u16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_ge_u16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_ge_u16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_ge_u16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_ge_u16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_ge_u16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_ge_u16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_ge_u16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_ge_u16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_ge_u16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_ge_u16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_ge_u16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_ge_u16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_ge_u16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_ge_u16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_ge_u16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_ge_u16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_ge_u16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_ge_u16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_ge_u16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_ge_u16_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_ge_u16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x6a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_ge_u16_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_cmp_ge_u16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7a,0x00,0x3e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_ge_u16_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x00,0x3e,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7c,0x00,0x3e,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_ge_u32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_ge_u32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_ge_u32_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_ge_u32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_ge_u32_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_ge_u32_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_ge_u32_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_ge_u32_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_ge_u32_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_ge_u32_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_ge_u32_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_ge_u32_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_ge_u32_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_ge_u32_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_ge_u32_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_ge_u32_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_ge_u32_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_ge_u32_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_ge_u32_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_ge_u32_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_ge_u32_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_ge_u32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_ge_u32_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_ge_u32_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x6a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_ge_u32_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_cmp_ge_u32_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7a,0x00,0x4e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_ge_u32_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x00,0x4e,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7c,0x00,0x4e,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_gt_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_gt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_gt_f16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_gt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_gt_f16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_gt_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_gt_f16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_gt_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_gt_f16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_gt_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_gt_f16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_gt_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_gt_f16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_gt_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_gt_f16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_gt_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_gt_f16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_gt_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_gt_f16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_gt_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_gt_f16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_gt_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x04,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_gt_f16_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x04,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_gt_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x04,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x6a,0x01,0x04,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_gt_f16_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x04,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64: v_cmp_gt_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x04,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7a,0x02,0x04,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_gt_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x04,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7c,0x83,0x04,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_gt_f32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_gt_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_gt_f32_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_gt_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_gt_f32_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_gt_f32_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_gt_f32_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_gt_f32_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_gt_f32_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_gt_f32_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_gt_f32_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_gt_f32_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_gt_f32_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_gt_f32_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_gt_f32_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_gt_f32_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_gt_f32_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_gt_f32_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_gt_f32_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_gt_f32_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_gt_f32_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_gt_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x14,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_gt_f32_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x14,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_gt_f32_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x14,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x6a,0x01,0x14,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_gt_f32_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x14,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64: v_cmp_gt_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x14,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7a,0x02,0x14,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_gt_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x14,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7c,0x83,0x14,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_gt_i16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_gt_i16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_gt_i16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_gt_i16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_gt_i16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_gt_i16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_gt_i16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_gt_i16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_gt_i16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_gt_i16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_gt_i16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_gt_i16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_gt_i16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_gt_i16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_gt_i16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_gt_i16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_gt_i16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_gt_i16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_gt_i16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_gt_i16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_gt_i16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_gt_i16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_gt_i16_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_gt_i16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x6a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_gt_i16_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_cmp_gt_i16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7a,0x00,0x34,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_gt_i16_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x00,0x34,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7c,0x00,0x34,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_gt_i32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_gt_i32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_gt_i32_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_gt_i32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_gt_i32_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_gt_i32_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_gt_i32_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_gt_i32_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_gt_i32_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_gt_i32_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_gt_i32_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_gt_i32_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_gt_i32_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_gt_i32_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_gt_i32_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_gt_i32_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_gt_i32_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_gt_i32_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_gt_i32_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_gt_i32_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_gt_i32_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_gt_i32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_gt_i32_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_gt_i32_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x6a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_gt_i32_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_cmp_gt_i32_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7a,0x00,0x44,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_gt_i32_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x00,0x44,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7c,0x00,0x44,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_gt_u16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_gt_u16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_gt_u16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_gt_u16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_gt_u16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_gt_u16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_gt_u16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_gt_u16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_gt_u16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_gt_u16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_gt_u16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_gt_u16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_gt_u16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_gt_u16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_gt_u16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_gt_u16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_gt_u16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_gt_u16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_gt_u16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_gt_u16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_gt_u16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_gt_u16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_gt_u16_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_gt_u16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x6a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_gt_u16_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_cmp_gt_u16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7a,0x00,0x3c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_gt_u16_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x00,0x3c,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7c,0x00,0x3c,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_gt_u32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_gt_u32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_gt_u32_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_gt_u32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_gt_u32_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_gt_u32_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_gt_u32_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_gt_u32_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_gt_u32_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_gt_u32_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_gt_u32_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_gt_u32_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_gt_u32_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_gt_u32_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_gt_u32_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_gt_u32_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_gt_u32_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_gt_u32_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_gt_u32_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_gt_u32_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_gt_u32_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_gt_u32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_gt_u32_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_gt_u32_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x6a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_gt_u32_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_cmp_gt_u32_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7a,0x00,0x4c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_gt_u32_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x00,0x4c,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7c,0x00,0x4c,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_le_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_le_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_le_f16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_le_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_le_f16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_le_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_le_f16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_le_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_le_f16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_le_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_le_f16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_le_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_le_f16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_le_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_le_f16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_le_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_le_f16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_le_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_le_f16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_le_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_le_f16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_le_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x03,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_le_f16_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x03,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_le_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x03,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x6a,0x01,0x03,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_le_f16_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x03,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64: v_cmp_le_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x03,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7a,0x02,0x03,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_le_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x03,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7c,0x83,0x03,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_le_f32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_le_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_le_f32_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_le_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_le_f32_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_le_f32_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_le_f32_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_le_f32_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_le_f32_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_le_f32_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_le_f32_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_le_f32_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_le_f32_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_le_f32_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_le_f32_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_le_f32_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_le_f32_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_le_f32_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_le_f32_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_le_f32_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_le_f32_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_le_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x13,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_le_f32_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x13,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_le_f32_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x13,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x6a,0x01,0x13,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_le_f32_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x13,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64: v_cmp_le_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x13,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7a,0x02,0x13,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_le_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x13,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7c,0x83,0x13,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_le_i16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_le_i16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_le_i16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_le_i16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_le_i16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_le_i16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_le_i16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_le_i16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_le_i16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_le_i16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_le_i16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_le_i16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_le_i16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_le_i16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_le_i16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_le_i16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_le_i16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_le_i16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_le_i16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_le_i16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_le_i16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_le_i16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_le_i16_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_le_i16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x6a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_le_i16_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_cmp_le_i16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7a,0x00,0x33,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_le_i16_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x00,0x33,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7c,0x00,0x33,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_le_i32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_le_i32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_le_i32_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_le_i32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_le_i32_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_le_i32_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_le_i32_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_le_i32_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_le_i32_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_le_i32_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_le_i32_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_le_i32_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_le_i32_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_le_i32_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_le_i32_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_le_i32_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_le_i32_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_le_i32_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_le_i32_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_le_i32_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_le_i32_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_le_i32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_le_i32_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_le_i32_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x6a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_le_i32_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_cmp_le_i32_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7a,0x00,0x43,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_le_i32_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x00,0x43,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7c,0x00,0x43,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_le_u16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_le_u16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_le_u16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_le_u16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_le_u16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_le_u16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_le_u16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_le_u16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_le_u16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_le_u16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_le_u16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_le_u16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_le_u16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_le_u16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_le_u16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_le_u16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_le_u16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_le_u16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_le_u16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_le_u16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_le_u16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_le_u16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_le_u16_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_le_u16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x6a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_le_u16_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_cmp_le_u16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7a,0x00,0x3b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_le_u16_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x00,0x3b,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7c,0x00,0x3b,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_le_u32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_le_u32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_le_u32_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_le_u32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_le_u32_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_le_u32_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_le_u32_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_le_u32_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_le_u32_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_le_u32_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_le_u32_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_le_u32_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_le_u32_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_le_u32_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_le_u32_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_le_u32_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_le_u32_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_le_u32_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_le_u32_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_le_u32_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_le_u32_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_le_u32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_le_u32_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_le_u32_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x6a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_le_u32_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_cmp_le_u32_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7a,0x00,0x4b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_le_u32_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x00,0x4b,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7c,0x00,0x4b,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_lg_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_lg_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_lg_f16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_lg_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_lg_f16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_lg_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_lg_f16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_lg_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_lg_f16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_lg_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_lg_f16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_lg_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_lg_f16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_lg_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_lg_f16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_lg_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_lg_f16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_lg_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_lg_f16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_lg_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_lg_f16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_lg_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x05,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_lg_f16_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x05,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_lg_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x05,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x6a,0x01,0x05,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_lg_f16_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x05,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64: v_cmp_lg_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x05,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7a,0x02,0x05,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_lg_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x05,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7c,0x83,0x05,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_lg_f32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_lg_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_lg_f32_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_lg_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_lg_f32_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_lg_f32_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_lg_f32_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_lg_f32_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_lg_f32_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_lg_f32_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_lg_f32_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_lg_f32_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_lg_f32_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_lg_f32_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_lg_f32_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_lg_f32_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_lg_f32_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_lg_f32_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_lg_f32_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_lg_f32_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_lg_f32_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_lg_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x15,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_lg_f32_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x15,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_lg_f32_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x15,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x6a,0x01,0x15,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_lg_f32_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x15,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64: v_cmp_lg_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x15,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7a,0x02,0x15,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_lg_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x15,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7c,0x83,0x15,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_lt_f16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_lt_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_lt_f16_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_lt_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x6a,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_lt_f16_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7a,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7c,0x83,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_lt_f32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_lt_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_lt_f32_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_lt_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_lt_f32_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_lt_f32_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_lt_f32_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_lt_f32_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_lt_f32_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_lt_f32_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_lt_f32_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_lt_f32_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_lt_f32_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_lt_f32_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_lt_f32_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_lt_f32_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_lt_f32_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_lt_f32_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_lt_f32_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_lt_f32_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_lt_f32_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_lt_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_lt_f32_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x11,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_lt_f32_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x11,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x6a,0x01,0x11,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_lt_f32_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x11,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64: v_cmp_lt_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x11,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7a,0x02,0x11,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_lt_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x11,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7c,0x83,0x11,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_lt_i16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_lt_i16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_lt_i16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_lt_i16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_lt_i16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_lt_i16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_lt_i16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_lt_i16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_lt_i16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_lt_i16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_lt_i16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_lt_i16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_lt_i16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_lt_i16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_lt_i16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_lt_i16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_lt_i16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_lt_i16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_lt_i16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_lt_i16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_lt_i16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_lt_i16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_lt_i16_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_lt_i16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x6a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_lt_i16_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_cmp_lt_i16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7a,0x00,0x31,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_lt_i16_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x00,0x31,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7c,0x00,0x31,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_lt_i32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_lt_i32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_lt_i32_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_lt_i32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_lt_i32_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_lt_i32_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_lt_i32_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_lt_i32_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_lt_i32_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_lt_i32_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_lt_i32_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_lt_i32_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_lt_i32_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_lt_i32_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_lt_i32_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_lt_i32_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_lt_i32_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_lt_i32_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_lt_i32_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_lt_i32_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_lt_i32_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_lt_i32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_lt_i32_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_lt_i32_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x6a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_lt_i32_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_cmp_lt_i32_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7a,0x00,0x41,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_lt_i32_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x00,0x41,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7c,0x00,0x41,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_lt_u16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_lt_u16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_lt_u16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_lt_u16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_lt_u16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_lt_u16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_lt_u16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_lt_u16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_lt_u16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_lt_u16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_lt_u16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_lt_u16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_lt_u16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_lt_u16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_lt_u16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_lt_u16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_lt_u16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_lt_u16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_lt_u16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_lt_u16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_lt_u16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_lt_u16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_lt_u16_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_lt_u16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x6a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_lt_u16_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_cmp_lt_u16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7a,0x00,0x39,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_lt_u16_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x00,0x39,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7c,0x00,0x39,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_lt_u32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_lt_u32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_lt_u32_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_lt_u32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_lt_u32_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_lt_u32_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_lt_u32_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_lt_u32_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_lt_u32_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_lt_u32_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_lt_u32_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_lt_u32_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_lt_u32_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_lt_u32_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_lt_u32_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_lt_u32_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_lt_u32_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_lt_u32_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_lt_u32_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_lt_u32_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_lt_u32_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_lt_u32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_lt_u32_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_lt_u32_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x6a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_lt_u32_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_cmp_lt_u32_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7a,0x00,0x49,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_lt_u32_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x00,0x49,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7c,0x00,0x49,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_ne_i16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_ne_i16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_ne_i16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_ne_i16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_ne_i16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_ne_i16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_ne_i16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_ne_i16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_ne_i16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_ne_i16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_ne_i16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_ne_i16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_ne_i16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_ne_i16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_ne_i16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_ne_i16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_ne_i16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_ne_i16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_ne_i16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_ne_i16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_ne_i16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_ne_i16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_ne_i16_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_ne_i16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x6a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_ne_i16_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_cmp_ne_i16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7a,0x00,0x35,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_ne_i16_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x00,0x35,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7c,0x00,0x35,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_ne_i32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_ne_i32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_ne_i32_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_ne_i32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_ne_i32_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_ne_i32_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_ne_i32_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_ne_i32_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_ne_i32_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_ne_i32_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_ne_i32_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_ne_i32_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_ne_i32_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_ne_i32_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_ne_i32_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_ne_i32_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_ne_i32_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_ne_i32_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_ne_i32_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_ne_i32_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_ne_i32_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_ne_i32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_ne_i32_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_ne_i32_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x6a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_ne_i32_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_cmp_ne_i32_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7a,0x00,0x45,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_ne_i32_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x00,0x45,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7c,0x00,0x45,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_ne_u16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_ne_u16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_ne_u16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_ne_u16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_ne_u16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_ne_u16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_ne_u16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_ne_u16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_ne_u16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_ne_u16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_ne_u16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_ne_u16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_ne_u16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_ne_u16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_ne_u16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_ne_u16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_ne_u16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_ne_u16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_ne_u16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_ne_u16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_ne_u16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_ne_u16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_ne_u16_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_ne_u16_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x6a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_ne_u16_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_cmp_ne_u16_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7a,0x00,0x3d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_ne_u16_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x00,0x3d,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7c,0x00,0x3d,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_ne_u32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_ne_u32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_ne_u32_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_ne_u32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_ne_u32_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_ne_u32_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_ne_u32_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_ne_u32_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_ne_u32_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_ne_u32_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_ne_u32_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_ne_u32_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_ne_u32_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_ne_u32_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_ne_u32_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_ne_u32_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_ne_u32_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_ne_u32_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_ne_u32_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_ne_u32_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_ne_u32_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_ne_u32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_ne_u32_e64_dpp vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_ne_u32_e64_dpp vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x6a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_ne_u32_e64_dpp ttmp14, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+# W64: v_cmp_ne_u32_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7a,0x00,0x4d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_ne_u32_e64_dpp null, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x00,0x4d,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7c,0x00,0x4d,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_neq_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_neq_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_neq_f16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_neq_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_neq_f16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_neq_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_neq_f16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_neq_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_neq_f16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_neq_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_neq_f16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_neq_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_neq_f16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_neq_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_neq_f16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_neq_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_neq_f16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_neq_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_neq_f16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_neq_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_neq_f16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_neq_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x0d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_neq_f16_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x0d,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_neq_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x0d,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x6a,0x01,0x0d,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_neq_f16_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x0d,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64: v_cmp_neq_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x0d,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7a,0x02,0x0d,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_neq_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x0d,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7c,0x83,0x0d,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_neq_f32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_neq_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_neq_f32_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_neq_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_neq_f32_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_neq_f32_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_neq_f32_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_neq_f32_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_neq_f32_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_neq_f32_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_neq_f32_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_neq_f32_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_neq_f32_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_neq_f32_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_neq_f32_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_neq_f32_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_neq_f32_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_neq_f32_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_neq_f32_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_neq_f32_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_neq_f32_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_neq_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x1d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_neq_f32_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x1d,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_neq_f32_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x1d,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x6a,0x01,0x1d,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_neq_f32_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x1d,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64: v_cmp_neq_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x1d,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7a,0x02,0x1d,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_neq_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x1d,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7c,0x83,0x1d,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_nge_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_nge_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_nge_f16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_nge_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_nge_f16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_nge_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_nge_f16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_nge_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_nge_f16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_nge_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_nge_f16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_nge_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_nge_f16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_nge_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_nge_f16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_nge_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_nge_f16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_nge_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_nge_f16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_nge_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_nge_f16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_nge_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x09,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_nge_f16_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x09,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_nge_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x09,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x6a,0x01,0x09,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_nge_f16_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x09,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64: v_cmp_nge_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x09,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7a,0x02,0x09,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_nge_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x09,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7c,0x83,0x09,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_nge_f32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_nge_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_nge_f32_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_nge_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_nge_f32_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_nge_f32_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_nge_f32_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_nge_f32_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_nge_f32_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_nge_f32_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_nge_f32_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_nge_f32_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_nge_f32_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_nge_f32_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_nge_f32_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_nge_f32_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_nge_f32_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_nge_f32_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_nge_f32_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_nge_f32_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_nge_f32_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_nge_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x19,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_nge_f32_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x19,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_nge_f32_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x19,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x6a,0x01,0x19,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_nge_f32_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x19,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64: v_cmp_nge_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x19,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7a,0x02,0x19,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_nge_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x19,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7c,0x83,0x19,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_ngt_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_ngt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_ngt_f16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_ngt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_ngt_f16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_ngt_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_ngt_f16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_ngt_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_ngt_f16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_ngt_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_ngt_f16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_ngt_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_ngt_f16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_ngt_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_ngt_f16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_ngt_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_ngt_f16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_ngt_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_ngt_f16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_ngt_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_ngt_f16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_ngt_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x0b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_ngt_f16_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x0b,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_ngt_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x0b,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x6a,0x01,0x0b,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_ngt_f16_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x0b,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64: v_cmp_ngt_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x0b,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7a,0x02,0x0b,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_ngt_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x0b,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7c,0x83,0x0b,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_ngt_f32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_ngt_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_ngt_f32_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_ngt_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_ngt_f32_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_ngt_f32_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_ngt_f32_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_ngt_f32_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_ngt_f32_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_ngt_f32_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_ngt_f32_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_ngt_f32_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_ngt_f32_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_ngt_f32_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_ngt_f32_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_ngt_f32_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_ngt_f32_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_ngt_f32_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_ngt_f32_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_ngt_f32_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_ngt_f32_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_ngt_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x1b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_ngt_f32_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x1b,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_ngt_f32_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x1b,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x6a,0x01,0x1b,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_ngt_f32_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x1b,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64: v_cmp_ngt_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x1b,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7a,0x02,0x1b,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_ngt_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x1b,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7c,0x83,0x1b,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_nle_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_nle_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_nle_f16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_nle_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_nle_f16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_nle_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_nle_f16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_nle_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_nle_f16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_nle_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_nle_f16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_nle_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_nle_f16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_nle_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_nle_f16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_nle_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_nle_f16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_nle_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_nle_f16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_nle_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_nle_f16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_nle_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x0c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_nle_f16_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x0c,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_nle_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x0c,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x6a,0x01,0x0c,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_nle_f16_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x0c,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64: v_cmp_nle_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x0c,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7a,0x02,0x0c,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_nle_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x0c,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7c,0x83,0x0c,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_nle_f32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_nle_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_nle_f32_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_nle_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_nle_f32_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_nle_f32_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_nle_f32_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_nle_f32_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_nle_f32_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_nle_f32_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_nle_f32_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_nle_f32_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_nle_f32_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_nle_f32_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_nle_f32_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_nle_f32_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_nle_f32_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_nle_f32_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_nle_f32_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_nle_f32_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_nle_f32_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_nle_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_nle_f32_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x1c,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_nle_f32_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x1c,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x6a,0x01,0x1c,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_nle_f32_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x1c,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64: v_cmp_nle_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x1c,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7a,0x02,0x1c,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_nle_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x1c,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7c,0x83,0x1c,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_nlg_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_nlg_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_nlg_f16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_nlg_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_nlg_f16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_nlg_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_nlg_f16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_nlg_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_nlg_f16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_nlg_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_nlg_f16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_nlg_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_nlg_f16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_nlg_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_nlg_f16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_nlg_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_nlg_f16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_nlg_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_nlg_f16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_nlg_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_nlg_f16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_nlg_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x0a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_nlg_f16_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x0a,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_nlg_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x0a,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x6a,0x01,0x0a,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_nlg_f16_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x0a,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64: v_cmp_nlg_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x0a,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7a,0x02,0x0a,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_nlg_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x0a,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7c,0x83,0x0a,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_nlg_f32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_nlg_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_nlg_f32_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_nlg_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_nlg_f32_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_nlg_f32_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_nlg_f32_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_nlg_f32_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_nlg_f32_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_nlg_f32_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_nlg_f32_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_nlg_f32_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_nlg_f32_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_nlg_f32_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_nlg_f32_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_nlg_f32_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_nlg_f32_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_nlg_f32_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_nlg_f32_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_nlg_f32_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_nlg_f32_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_nlg_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x1a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_nlg_f32_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x1a,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_nlg_f32_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x1a,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x6a,0x01,0x1a,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_nlg_f32_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x1a,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64: v_cmp_nlg_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x1a,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7a,0x02,0x1a,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_nlg_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x1a,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7c,0x83,0x1a,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_nlt_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_nlt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_nlt_f16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_nlt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_nlt_f16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_nlt_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_nlt_f16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_nlt_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_nlt_f16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_nlt_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_nlt_f16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_nlt_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_nlt_f16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_nlt_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_nlt_f16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_nlt_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_nlt_f16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_nlt_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_nlt_f16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_nlt_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_nlt_f16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_nlt_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x0e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_nlt_f16_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x0e,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_nlt_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x0e,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x6a,0x01,0x0e,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_nlt_f16_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x0e,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64: v_cmp_nlt_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x0e,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7a,0x02,0x0e,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_nlt_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x0e,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7c,0x83,0x0e,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_nlt_f32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_nlt_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_nlt_f32_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_nlt_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_nlt_f32_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_nlt_f32_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_nlt_f32_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_nlt_f32_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_nlt_f32_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_nlt_f32_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_nlt_f32_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_nlt_f32_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_nlt_f32_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_nlt_f32_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_nlt_f32_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_nlt_f32_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_nlt_f32_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_nlt_f32_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_nlt_f32_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_nlt_f32_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_nlt_f32_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_nlt_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x1e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_nlt_f32_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x1e,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_nlt_f32_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x1e,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x6a,0x01,0x1e,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_nlt_f32_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x1e,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64: v_cmp_nlt_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x1e,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7a,0x02,0x1e,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_nlt_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x1e,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7c,0x83,0x1e,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_o_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_o_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_o_f16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_o_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_o_f16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_o_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_o_f16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_o_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_o_f16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_o_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_o_f16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_o_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_o_f16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_o_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_o_f16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_o_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_o_f16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_o_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_o_f16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_o_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_o_f16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_o_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x07,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_o_f16_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x07,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_o_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x07,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x6a,0x01,0x07,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_o_f16_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x07,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64: v_cmp_o_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x07,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7a,0x02,0x07,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_o_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x07,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7c,0x83,0x07,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_o_f32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_o_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_o_f32_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_o_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_o_f32_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_o_f32_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_o_f32_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_o_f32_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_o_f32_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_o_f32_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_o_f32_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_o_f32_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_o_f32_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_o_f32_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_o_f32_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_o_f32_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_o_f32_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_o_f32_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_o_f32_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_o_f32_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_o_f32_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_o_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x17,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_o_f32_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x17,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_o_f32_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x17,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x6a,0x01,0x17,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_o_f32_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x17,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64: v_cmp_o_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x17,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7a,0x02,0x17,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_o_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x17,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7c,0x83,0x17,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_u_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_u_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_u_f16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_u_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_u_f16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_u_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_u_f16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_u_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_u_f16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_u_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_u_f16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_u_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_u_f16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_u_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_u_f16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_u_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_u_f16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_u_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_u_f16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_u_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_u_f16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_u_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x08,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_u_f16_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x08,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_u_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x08,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x6a,0x01,0x08,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_u_f16_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x08,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64: v_cmp_u_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x08,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7a,0x02,0x08,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_u_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x08,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7c,0x83,0x08,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_u_f32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_u_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_u_f32_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_u_f32_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_u_f32_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64: v_cmp_u_f32_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_u_f32_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64: v_cmp_u_f32_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_u_f32_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64: v_cmp_u_f32_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_u_f32_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_u_f32_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_u_f32_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64: v_cmp_u_f32_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_u_f32_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_u_f32_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_u_f32_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64: v_cmp_u_f32_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_u_f32_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_u_f32_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x0a,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_u_f32_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64: v_cmp_u_f32_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x68,0x00,0x18,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_u_f32_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x18,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_u_f32_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x18,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x6a,0x01,0x18,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_u_f32_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x18,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64: v_cmp_u_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x18,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7a,0x02,0x18,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmp_u_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x18,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7c,0x83,0x18,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp8.txt
new file mode 100644
index 000000000000..23be05d295a7
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp8.txt
@@ -0,0 +1,1028 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32 %s
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64 %s
+
+# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_class_f16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_class_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_class_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_class_f16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_class_f16_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_class_f16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_class_f16_e64_dpp null, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x01,0x7d,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00]
+0x7c,0x01,0x7d,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_class_f32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_class_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x7e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_class_f32_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x7e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_class_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x7e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x7e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_class_f32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_class_f32_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x7e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x6a,0x00,0x7e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_class_f32_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x7e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_class_f32_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x7e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7a,0x00,0x7e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_class_f32_e64_dpp null, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x01,0x7e,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00]
+0x7c,0x01,0x7e,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_eq_f16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_eq_f16_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x6a,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_eq_f16_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x02,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x02,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7a,0x02,0x02,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7c,0x83,0x02,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_eq_f32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x12,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x12,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x12,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_eq_f32_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x12,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x12,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x12,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_eq_f32_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x12,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_f32_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x12,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x6a,0x01,0x12,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_eq_f32_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x12,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x12,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7a,0x02,0x12,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_eq_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x12,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7c,0x83,0x12,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_eq_i16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x32,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_i16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x32,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x32,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_eq_i16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x32,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_i16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x32,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x32,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_eq_i16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x32,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_i16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x32,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x6a,0x00,0x32,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_eq_i16_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x32,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_i16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x32,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7a,0x00,0x32,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_eq_i16_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x00,0x32,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7c,0x00,0x32,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_eq_i32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x42,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_i32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x42,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x42,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_eq_i32_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x42,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_i32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x42,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x42,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_eq_i32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x42,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_i32_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x42,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x6a,0x00,0x42,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_eq_i32_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x42,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_i32_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x42,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7a,0x00,0x42,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_eq_i32_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x00,0x42,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7c,0x00,0x42,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_eq_u16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x3a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_u16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x3a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x3a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_eq_u16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x3a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_u16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x3a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x3a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_eq_u16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x3a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_u16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x3a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x6a,0x00,0x3a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_eq_u16_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x3a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_u16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x3a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7a,0x00,0x3a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_eq_u16_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x00,0x3a,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7c,0x00,0x3a,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_eq_u32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x4a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_u32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x4a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x4a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_eq_u32_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x4a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_u32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x4a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x4a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_eq_u32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x4a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_u32_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x4a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x6a,0x00,0x4a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_eq_u32_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x4a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_u32_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x4a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7a,0x00,0x4a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_eq_u32_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x00,0x4a,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7c,0x00,0x4a,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_ge_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x06,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x06,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x06,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ge_f16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x06,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x06,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x06,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ge_f16_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x06,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x06,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x6a,0x01,0x06,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ge_f16_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x06,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x06,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7a,0x02,0x06,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_ge_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x06,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7c,0x83,0x06,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_ge_f32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x16,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x16,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x16,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ge_f32_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x16,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x16,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x16,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ge_f32_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x16,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_f32_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x16,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x6a,0x01,0x16,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ge_f32_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x16,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x16,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7a,0x02,0x16,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_ge_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x16,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7c,0x83,0x16,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_ge_i16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x36,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_i16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x36,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x36,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ge_i16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x36,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_i16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x36,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x36,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ge_i16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x36,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_i16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x36,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x6a,0x00,0x36,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ge_i16_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x36,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_i16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x36,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7a,0x00,0x36,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_ge_i16_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x00,0x36,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7c,0x00,0x36,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_ge_i32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x46,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_i32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x46,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x46,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ge_i32_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x46,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_i32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x46,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x46,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ge_i32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x46,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_i32_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x46,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x6a,0x00,0x46,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ge_i32_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x46,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_i32_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x46,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7a,0x00,0x46,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_ge_i32_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x00,0x46,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7c,0x00,0x46,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_ge_u16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x3e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_u16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x3e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x3e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ge_u16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x3e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_u16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x3e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x3e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ge_u16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x3e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_u16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x3e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x6a,0x00,0x3e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ge_u16_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x3e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_u16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x3e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7a,0x00,0x3e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_ge_u16_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x00,0x3e,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7c,0x00,0x3e,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_ge_u32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x4e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_u32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x4e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x4e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ge_u32_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x4e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_u32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x4e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x4e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ge_u32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x4e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_u32_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x4e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x6a,0x00,0x4e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ge_u32_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x4e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_u32_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x4e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7a,0x00,0x4e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_ge_u32_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x00,0x4e,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7c,0x00,0x4e,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_gt_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x04,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x04,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x04,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_gt_f16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x04,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x04,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x04,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_gt_f16_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x04,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x04,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x6a,0x01,0x04,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_gt_f16_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x04,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x04,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7a,0x02,0x04,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_gt_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x04,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7c,0x83,0x04,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_gt_f32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x14,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x14,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x14,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_gt_f32_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x14,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x14,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x14,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_gt_f32_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x14,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_f32_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x14,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x6a,0x01,0x14,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_gt_f32_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x14,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x14,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7a,0x02,0x14,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_gt_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x14,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7c,0x83,0x14,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_gt_i16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x34,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_i16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x34,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x34,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_gt_i16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x34,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_i16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x34,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x34,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_gt_i16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x34,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_i16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x34,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x6a,0x00,0x34,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_gt_i16_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x34,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_i16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x34,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7a,0x00,0x34,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_gt_i16_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x00,0x34,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7c,0x00,0x34,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_gt_i32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x44,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_i32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x44,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x44,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_gt_i32_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x44,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_i32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x44,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x44,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_gt_i32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x44,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_i32_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x44,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x6a,0x00,0x44,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_gt_i32_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x44,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_i32_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x44,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7a,0x00,0x44,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_gt_i32_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x00,0x44,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7c,0x00,0x44,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_gt_u16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x3c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_u16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x3c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x3c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_gt_u16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x3c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_u16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x3c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x3c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_gt_u16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x3c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_u16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x3c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x6a,0x00,0x3c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_gt_u16_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x3c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_u16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x3c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7a,0x00,0x3c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_gt_u16_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x00,0x3c,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7c,0x00,0x3c,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_gt_u32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x4c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_u32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x4c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x4c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_gt_u32_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x4c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_u32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x4c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x4c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_gt_u32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x4c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_u32_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x4c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x6a,0x00,0x4c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_gt_u32_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x4c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_u32_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x4c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7a,0x00,0x4c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_gt_u32_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x00,0x4c,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7c,0x00,0x4c,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_le_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x03,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x03,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x03,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_le_f16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x03,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x03,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x03,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_le_f16_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x03,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x03,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x6a,0x01,0x03,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_le_f16_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x03,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x03,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7a,0x02,0x03,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_le_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x03,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7c,0x83,0x03,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_le_f32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x13,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x13,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x13,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_le_f32_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x13,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x13,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x13,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_le_f32_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x13,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_f32_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x13,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x6a,0x01,0x13,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_le_f32_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x13,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x13,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7a,0x02,0x13,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_le_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x13,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7c,0x83,0x13,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_le_i16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x33,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_i16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x33,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x33,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_le_i16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x33,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_i16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x33,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x33,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_le_i16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x33,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_i16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x33,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x6a,0x00,0x33,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_le_i16_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x33,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_i16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x33,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7a,0x00,0x33,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_le_i16_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x00,0x33,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7c,0x00,0x33,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_le_i32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x43,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_i32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x43,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x43,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_le_i32_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x43,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_i32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x43,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x43,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_le_i32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x43,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_i32_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x43,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x6a,0x00,0x43,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_le_i32_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x43,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_i32_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x43,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7a,0x00,0x43,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_le_i32_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x00,0x43,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7c,0x00,0x43,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_le_u16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x3b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_u16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x3b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x3b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_le_u16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x3b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_u16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x3b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x3b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_le_u16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x3b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_u16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x3b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x6a,0x00,0x3b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_le_u16_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x3b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_u16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x3b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7a,0x00,0x3b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_le_u16_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x00,0x3b,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7c,0x00,0x3b,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_le_u32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x4b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_u32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x4b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x4b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_le_u32_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x4b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_u32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x4b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x4b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_le_u32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x4b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_u32_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x4b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x6a,0x00,0x4b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_le_u32_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x4b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_u32_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x4b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7a,0x00,0x4b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_le_u32_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x00,0x4b,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7c,0x00,0x4b,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_lg_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x05,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lg_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x05,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x05,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lg_f16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x05,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lg_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x05,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x05,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lg_f16_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x05,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lg_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x05,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x6a,0x01,0x05,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lg_f16_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x05,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lg_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x05,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7a,0x02,0x05,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_lg_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x05,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7c,0x83,0x05,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_lg_f32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x15,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lg_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x15,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x15,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lg_f32_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x15,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lg_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x15,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x15,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lg_f32_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x15,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lg_f32_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x15,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x6a,0x01,0x15,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lg_f32_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x15,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lg_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x15,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7a,0x02,0x15,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_lg_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x15,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7c,0x83,0x15,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lt_f16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lt_f16_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x6a,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lt_f16_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x01,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x01,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7a,0x02,0x01,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7c,0x83,0x01,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_lt_f32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x11,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x11,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x11,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lt_f32_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x11,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x11,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x11,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lt_f32_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x11,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_f32_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x11,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x6a,0x01,0x11,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lt_f32_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x11,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x11,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7a,0x02,0x11,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_lt_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x11,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7c,0x83,0x11,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_lt_i16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x31,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_i16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x31,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x31,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lt_i16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x31,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_i16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x31,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x31,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lt_i16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x31,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_i16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x31,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x6a,0x00,0x31,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lt_i16_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x31,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_i16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x31,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7a,0x00,0x31,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_lt_i16_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x00,0x31,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7c,0x00,0x31,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_lt_i32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x41,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_i32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x41,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x41,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lt_i32_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x41,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_i32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x41,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x41,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lt_i32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x41,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_i32_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x41,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x6a,0x00,0x41,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lt_i32_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x41,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_i32_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x41,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7a,0x00,0x41,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_lt_i32_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x00,0x41,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7c,0x00,0x41,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_lt_u16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x39,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_u16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x39,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x39,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lt_u16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x39,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_u16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x39,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x39,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lt_u16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x39,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_u16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x39,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x6a,0x00,0x39,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lt_u16_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x39,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_u16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x39,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7a,0x00,0x39,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_lt_u16_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x00,0x39,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7c,0x00,0x39,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_lt_u32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x49,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_u32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x49,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x49,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lt_u32_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x49,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_u32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x49,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x49,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lt_u32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x49,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_u32_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x49,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x6a,0x00,0x49,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lt_u32_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x49,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_u32_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x49,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7a,0x00,0x49,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_lt_u32_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x00,0x49,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7c,0x00,0x49,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_ne_i16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x35,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ne_i16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x35,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x35,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ne_i16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x35,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ne_i16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x35,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x35,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ne_i16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x35,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ne_i16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x35,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x6a,0x00,0x35,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ne_i16_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x35,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ne_i16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x35,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7a,0x00,0x35,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_ne_i16_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x00,0x35,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7c,0x00,0x35,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_ne_i32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x45,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ne_i32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x45,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x45,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ne_i32_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x45,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ne_i32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x45,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x45,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ne_i32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x45,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ne_i32_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x45,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x6a,0x00,0x45,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ne_i32_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x45,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ne_i32_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x45,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7a,0x00,0x45,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_ne_i32_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x00,0x45,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7c,0x00,0x45,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_ne_u16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x3d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ne_u16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x3d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x3d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ne_u16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x3d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ne_u16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x3d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x3d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ne_u16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x3d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ne_u16_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x3d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x6a,0x00,0x3d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ne_u16_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x3d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ne_u16_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x3d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7a,0x00,0x3d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_ne_u16_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x00,0x3d,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7c,0x00,0x3d,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_ne_u32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x4d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ne_u32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x4d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x4d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ne_u32_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x4d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ne_u32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x4d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x4d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ne_u32_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x4d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ne_u32_e64_dpp vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x4d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x6a,0x00,0x4d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ne_u32_e64_dpp ttmp14, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x4d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ne_u32_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x00,0x4d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7a,0x00,0x4d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_ne_u32_e64_dpp null, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x00,0x4d,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7c,0x00,0x4d,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_neq_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x0d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_neq_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x0d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x0d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_neq_f16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x0d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_neq_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x0d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x0d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_neq_f16_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x0d,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64: v_cmp_neq_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x0d,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x6a,0x01,0x0d,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_neq_f16_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x0d,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64: v_cmp_neq_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x0d,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7a,0x02,0x0d,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_neq_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x0d,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7c,0x83,0x0d,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_neq_f32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x1d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_neq_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x1d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x1d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_neq_f32_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x1d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_neq_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x1d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x1d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_neq_f32_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x1d,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64: v_cmp_neq_f32_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x1d,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x6a,0x01,0x1d,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_neq_f32_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x1d,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64: v_cmp_neq_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x1d,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7a,0x02,0x1d,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_neq_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x1d,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7c,0x83,0x1d,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_nge_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x09,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nge_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x09,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x09,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nge_f16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x09,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nge_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x09,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x09,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nge_f16_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x09,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nge_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x09,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x6a,0x01,0x09,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nge_f16_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x09,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nge_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x09,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7a,0x02,0x09,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_nge_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x09,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7c,0x83,0x09,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_nge_f32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x19,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nge_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x19,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x19,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nge_f32_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x19,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nge_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x19,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x19,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nge_f32_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x19,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nge_f32_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x19,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x6a,0x01,0x19,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nge_f32_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x19,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nge_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x19,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7a,0x02,0x19,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_nge_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x19,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7c,0x83,0x19,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_ngt_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x0b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ngt_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x0b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x0b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ngt_f16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x0b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ngt_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x0b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x0b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ngt_f16_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x0b,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ngt_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x0b,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x6a,0x01,0x0b,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ngt_f16_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x0b,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ngt_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x0b,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7a,0x02,0x0b,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_ngt_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x0b,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7c,0x83,0x0b,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_ngt_f32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x1b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ngt_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x1b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x1b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ngt_f32_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x1b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ngt_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x1b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x1b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ngt_f32_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x1b,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ngt_f32_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x1b,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x6a,0x01,0x1b,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ngt_f32_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x1b,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ngt_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x1b,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7a,0x02,0x1b,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_ngt_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x1b,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7c,0x83,0x1b,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_nle_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x0c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nle_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x0c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x0c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nle_f16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x0c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nle_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x0c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x0c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nle_f16_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x0c,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nle_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x0c,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x6a,0x01,0x0c,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nle_f16_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x0c,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nle_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x0c,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7a,0x02,0x0c,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_nle_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x0c,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7c,0x83,0x0c,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_nle_f32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x1c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nle_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x1c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x1c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nle_f32_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x1c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nle_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x1c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x1c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nle_f32_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x1c,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nle_f32_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x1c,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x6a,0x01,0x1c,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nle_f32_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x1c,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nle_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x1c,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7a,0x02,0x1c,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_nle_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x1c,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7c,0x83,0x1c,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_nlg_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x0a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nlg_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x0a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x0a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nlg_f16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x0a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nlg_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x0a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x0a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nlg_f16_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x0a,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nlg_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x0a,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x6a,0x01,0x0a,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nlg_f16_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x0a,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nlg_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x0a,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7a,0x02,0x0a,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_nlg_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x0a,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7c,0x83,0x0a,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_nlg_f32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x1a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nlg_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x1a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x1a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nlg_f32_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x1a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nlg_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x1a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x1a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nlg_f32_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x1a,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nlg_f32_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x1a,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x6a,0x01,0x1a,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nlg_f32_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x1a,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nlg_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x1a,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7a,0x02,0x1a,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_nlg_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x1a,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7c,0x83,0x1a,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_nlt_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x0e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nlt_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x0e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x0e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nlt_f16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x0e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nlt_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x0e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x0e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nlt_f16_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x0e,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nlt_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x0e,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x6a,0x01,0x0e,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nlt_f16_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x0e,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nlt_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x0e,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7a,0x02,0x0e,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_nlt_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x0e,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7c,0x83,0x0e,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_nlt_f32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x1e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nlt_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x1e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x1e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nlt_f32_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x1e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nlt_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x1e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x1e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nlt_f32_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x1e,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nlt_f32_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x1e,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x6a,0x01,0x1e,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nlt_f32_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x1e,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nlt_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x1e,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7a,0x02,0x1e,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_nlt_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x1e,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7c,0x83,0x1e,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_o_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x07,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_o_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x07,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x07,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_o_f16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x07,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_o_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x07,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x07,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_o_f16_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x07,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64: v_cmp_o_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x07,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x6a,0x01,0x07,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_o_f16_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x07,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64: v_cmp_o_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x07,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7a,0x02,0x07,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_o_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x07,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7c,0x83,0x07,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_o_f32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x17,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_o_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x17,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x17,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_o_f32_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x17,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_o_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x17,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x17,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_o_f32_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x17,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64: v_cmp_o_f32_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x17,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x6a,0x01,0x17,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_o_f32_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x17,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64: v_cmp_o_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x17,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7a,0x02,0x17,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_o_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x17,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7c,0x83,0x17,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_u_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x08,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_u_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x08,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x08,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_u_f16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x08,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_u_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x08,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x08,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_u_f16_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x08,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64: v_cmp_u_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x08,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x6a,0x01,0x08,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_u_f16_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x08,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64: v_cmp_u_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x08,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7a,0x02,0x08,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_u_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x08,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7c,0x83,0x08,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_u_f32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x18,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_u_f32_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x18,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x0a,0x00,0x18,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_u_f32_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x18,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64: v_cmp_u_f32_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x18,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x68,0x00,0x18,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_u_f32_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x18,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64: v_cmp_u_f32_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x18,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x6a,0x01,0x18,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_u_f32_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x18,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64: v_cmp_u_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x18,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7a,0x02,0x18,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmp_u_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x18,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7c,0x83,0x18,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx.txt
new file mode 100644
index 000000000000..47a76cc3ef89
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx.txt
@@ -0,0 +1,3413 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12 %s
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12 %s
+
+# GFX12: v_cmpx_class_f16_e64 v1, v2             ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xfd,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_class_f16_e64 v255, v2           ; encoding: [0x7e,0x00,0xfd,0xd4,0xff,0x05,0x02,0x00]
+0x7e,0x00,0xfd,0xd4,0xff,0x05,0x02,0x00
+
+# GFX12: v_cmpx_class_f16_e64 s1, v2             ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0x04,0x02,0x00]
+0x7e,0x00,0xfd,0xd4,0x01,0x04,0x02,0x00
+
+# GFX12: v_cmpx_class_f16_e64 s105, v255         ; encoding: [0x7e,0x00,0xfd,0xd4,0x69,0xfe,0x03,0x00]
+0x7e,0x00,0xfd,0xd4,0x69,0xfe,0x03,0x00
+
+# GFX12: v_cmpx_class_f16_e64 vcc_lo, s2         ; encoding: [0x7e,0x00,0xfd,0xd4,0x6a,0x04,0x00,0x00]
+0x7e,0x00,0xfd,0xd4,0x6a,0x04,0x00,0x00
+
+# GFX12: v_cmpx_class_f16_e64 vcc_hi, s105       ; encoding: [0x7e,0x00,0xfd,0xd4,0x6b,0xd2,0x00,0x00]
+0x7e,0x00,0xfd,0xd4,0x6b,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_class_f16_e64 ttmp15, ttmp15     ; encoding: [0x7e,0x00,0xfd,0xd4,0x7b,0xf6,0x00,0x00]
+0x7e,0x00,0xfd,0xd4,0x7b,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_class_f16_e64 m0, src_scc        ; encoding: [0x7e,0x00,0xfd,0xd4,0x7d,0xfa,0x01,0x00]
+0x7e,0x00,0xfd,0xd4,0x7d,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_class_f16_e64 exec_lo, -1        ; encoding: [0x7e,0x00,0xfd,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0xfd,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_class_f16_e64 exec_hi, null      ; encoding: [0x7e,0x00,0xfd,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x00,0xfd,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_class_f16_e64 null, exec_lo      ; encoding: [0x7e,0x00,0xfd,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0xfd,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_class_f16_e64 -1, exec_hi        ; encoding: [0x7e,0x00,0xfd,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0xfd,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_class_f16_e64 0.5, m0            ; encoding: [0x7e,0x00,0xfd,0xd4,0xf0,0xfa,0x00,0x00]
+0x7e,0x00,0xfd,0xd4,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_cmpx_class_f16_e64 src_scc, vcc_lo    ; encoding: [0x7e,0x00,0xfd,0xd4,0xfd,0xd4,0x00,0x00]
+0x7e,0x00,0xfd,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmpx_class_f16_e64 -|0xfe0b|, vcc_hi  ; encoding: [0x7e,0x01,0xfd,0xd4,0xff,0xd6,0x00,0x20,0x0b,0xfe,0x00,0x00]
+0x7e,0x01,0xfd,0xd4,0xff,0xd6,0x00,0x20,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_class_f32_e64 v1, v2             ; encoding: [0x7e,0x00,0xfe,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xfe,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_class_f32_e64 v255, v255         ; encoding: [0x7e,0x00,0xfe,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0xfe,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_class_f32_e64 s1, s2             ; encoding: [0x7e,0x00,0xfe,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0xfe,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_class_f32_e64 s105, s105         ; encoding: [0x7e,0x00,0xfe,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0xfe,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_class_f32_e64 vcc_lo, ttmp15     ; encoding: [0x7e,0x00,0xfe,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0xfe,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_class_f32_e64 vcc_hi, 0xaf123456 ; encoding: [0x7e,0x00,0xfe,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xfe,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_class_f32_e64 ttmp15, src_scc    ; encoding: [0x7e,0x00,0xfe,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0xfe,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_class_f32_e64 m0, 0.5            ; encoding: [0x7e,0x00,0xfe,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0xfe,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_class_f32_e64 exec_lo, -1        ; encoding: [0x7e,0x00,0xfe,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0xfe,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_class_f32_e64 exec_hi, null      ; encoding: [0x7e,0x00,0xfe,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x00,0xfe,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_class_f32_e64 null, exec_lo      ; encoding: [0x7e,0x00,0xfe,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0xfe,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_class_f32_e64 -1, exec_hi        ; encoding: [0x7e,0x00,0xfe,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0xfe,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_class_f32_e64 0.5, m0            ; encoding: [0x7e,0x00,0xfe,0xd4,0xf0,0xfa,0x00,0x00]
+0x7e,0x00,0xfe,0xd4,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_cmpx_class_f32_e64 src_scc, vcc_lo    ; encoding: [0x7e,0x00,0xfe,0xd4,0xfd,0xd4,0x00,0x00]
+0x7e,0x00,0xfe,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmpx_class_f32_e64 -|0xaf123456|, vcc_hi ; encoding: [0x7e,0x01,0xfe,0xd4,0xff,0xd6,0x00,0x20,0x56,0x34,0x12,0xaf]
+0x7e,0x01,0xfe,0xd4,0xff,0xd6,0x00,0x20,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_class_f64_e64 v[1:2], v2         ; encoding: [0x7e,0x00,0xff,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xff,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_class_f64_e64 v[1:2], v255       ; encoding: [0x7e,0x00,0xff,0xd4,0x01,0xff,0x03,0x00]
+0x7e,0x00,0xff,0xd4,0x01,0xff,0x03,0x00
+
+# GFX12: v_cmpx_class_f64_e64 v[1:2], s2         ; encoding: [0x7e,0x00,0xff,0xd4,0x01,0x05,0x00,0x00]
+0x7e,0x00,0xff,0xd4,0x01,0x05,0x00,0x00
+
+# GFX12: v_cmpx_class_f64_e64 v[1:2], s105       ; encoding: [0x7e,0x00,0xff,0xd4,0x01,0xd3,0x00,0x00]
+0x7e,0x00,0xff,0xd4,0x01,0xd3,0x00,0x00
+
+# GFX12: v_cmpx_class_f64_e64 v[254:255], ttmp15 ; encoding: [0x7e,0x00,0xff,0xd4,0xfe,0xf7,0x00,0x00]
+0x7e,0x00,0xff,0xd4,0xfe,0xf7,0x00,0x00
+
+# GFX12: v_cmpx_class_f64_e64 s[2:3], vcc_hi     ; encoding: [0x7e,0x00,0xff,0xd4,0x02,0xd6,0x00,0x00]
+0x7e,0x00,0xff,0xd4,0x02,0xd6,0x00,0x00
+
+# GFX12: v_cmpx_class_f64_e64 s[104:105], vcc_lo ; encoding: [0x7e,0x00,0xff,0xd4,0x68,0xd4,0x00,0x00]
+0x7e,0x00,0xff,0xd4,0x68,0xd4,0x00,0x00
+
+# GFX12: v_cmpx_class_f64_e64 vcc, m0            ; encoding: [0x7e,0x00,0xff,0xd4,0x6a,0xfa,0x00,0x00]
+0x7e,0x00,0xff,0xd4,0x6a,0xfa,0x00,0x00
+
+# GFX12: v_cmpx_class_f64_e64 ttmp[14:15], exec_hi ; encoding: [0x7e,0x00,0xff,0xd4,0x7a,0xfe,0x00,0x00]
+0x7e,0x00,0xff,0xd4,0x7a,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_class_f64_e64 exec, exec_lo      ; encoding: [0x7e,0x00,0xff,0xd4,0x7e,0xfc,0x00,0x00]
+0x7e,0x00,0xff,0xd4,0x7e,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_class_f64_e64 null, null         ; encoding: [0x7e,0x00,0xff,0xd4,0x7c,0xf8,0x00,0x00]
+0x7e,0x00,0xff,0xd4,0x7c,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_class_f64_e64 -1, -1             ; encoding: [0x7e,0x00,0xff,0xd4,0xc1,0x82,0x01,0x00]
+0x7e,0x00,0xff,0xd4,0xc1,0x82,0x01,0x00
+
+# GFX12: v_cmpx_class_f64_e64 0.5, 0.5           ; encoding: [0x7e,0x00,0xff,0xd4,0xf0,0xe0,0x01,0x00]
+0x7e,0x00,0xff,0xd4,0xf0,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_class_f64_e64 -|src_scc|, src_scc ; encoding: [0x7e,0x01,0xff,0xd4,0xfd,0xfa,0x01,0x20]
+0x7e,0x01,0xff,0xd4,0xfd,0xfa,0x01,0x20
+
+# GFX12: v_cmpx_class_f64_e64 0xaf123456, 0xaf123456 ; encoding: [0x7e,0x00,0xff,0xd4,0xff,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xff,0xd4,0xff,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_eq_f16_e64 v1, v2                ; encoding: [0x7e,0x00,0x82,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0x82,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_eq_f16_e64 v255, v255            ; encoding: [0x7e,0x00,0x82,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0x82,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_eq_f16_e64 s1, s2                ; encoding: [0x7e,0x00,0x82,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0x82,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_eq_f16_e64 s105, s105            ; encoding: [0x7e,0x00,0x82,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0x82,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_eq_f16_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0x82,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0x82,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_eq_f16_e64 vcc_hi, 0xfe0b        ; encoding: [0x7e,0x00,0x82,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0x82,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_eq_f16_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0x82,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0x82,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_eq_f16_e64 m0, 0.5               ; encoding: [0x7e,0x00,0x82,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0x82,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_eq_f16_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0x82,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0x82,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_eq_f16_e64 |exec_hi|, null       ; encoding: [0x7e,0x01,0x82,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x01,0x82,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_eq_f16_e64 null, exec_lo         ; encoding: [0x7e,0x00,0x82,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0x82,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_eq_f16_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0x82,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0x82,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_eq_f16_e64 0.5, -m0              ; encoding: [0x7e,0x00,0x82,0xd4,0xf0,0xfa,0x00,0x40]
+0x7e,0x00,0x82,0xd4,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cmpx_eq_f16_e64 -src_scc, |vcc_lo|    ; encoding: [0x7e,0x02,0x82,0xd4,0xfd,0xd4,0x00,0x20]
+0x7e,0x02,0x82,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmpx_eq_f16_e64 -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7e,0x83,0x82,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x7e,0x83,0x82,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_eq_f32_e64 v1, v2                ; encoding: [0x7e,0x00,0x92,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0x92,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_eq_f32_e64 v255, v255            ; encoding: [0x7e,0x00,0x92,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0x92,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_eq_f32_e64 s1, s2                ; encoding: [0x7e,0x00,0x92,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0x92,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_eq_f32_e64 s105, s105            ; encoding: [0x7e,0x00,0x92,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0x92,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_eq_f32_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0x92,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0x92,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_eq_f32_e64 vcc_hi, 0xaf123456    ; encoding: [0x7e,0x00,0x92,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0x92,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_eq_f32_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0x92,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0x92,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_eq_f32_e64 m0, 0.5               ; encoding: [0x7e,0x00,0x92,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0x92,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_eq_f32_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0x92,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0x92,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_eq_f32_e64 |exec_hi|, null       ; encoding: [0x7e,0x01,0x92,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x01,0x92,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_eq_f32_e64 null, exec_lo         ; encoding: [0x7e,0x00,0x92,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0x92,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_eq_f32_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0x92,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0x92,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_eq_f32_e64 0.5, -m0              ; encoding: [0x7e,0x00,0x92,0xd4,0xf0,0xfa,0x00,0x40]
+0x7e,0x00,0x92,0xd4,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cmpx_eq_f32_e64 -src_scc, |vcc_lo|    ; encoding: [0x7e,0x02,0x92,0xd4,0xfd,0xd4,0x00,0x20]
+0x7e,0x02,0x92,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmpx_eq_f32_e64 -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0x7e,0x83,0x92,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0x7e,0x83,0x92,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_eq_f64_e64 v[1:2], v[2:3]        ; encoding: [0x7e,0x00,0xa2,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xa2,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_eq_f64_e64 v[254:255], v[254:255] ; encoding: [0x7e,0x00,0xa2,0xd4,0xfe,0xfd,0x03,0x00]
+0x7e,0x00,0xa2,0xd4,0xfe,0xfd,0x03,0x00
+
+# GFX12: v_cmpx_eq_f64_e64 s[2:3], s[4:5]        ; encoding: [0x7e,0x00,0xa2,0xd4,0x02,0x08,0x00,0x00]
+0x7e,0x00,0xa2,0xd4,0x02,0x08,0x00,0x00
+
+# GFX12: v_cmpx_eq_f64_e64 s[104:105], s[104:105] ; encoding: [0x7e,0x00,0xa2,0xd4,0x68,0xd0,0x00,0x00]
+0x7e,0x00,0xa2,0xd4,0x68,0xd0,0x00,0x00
+
+# GFX12: v_cmpx_eq_f64_e64 vcc, ttmp[14:15]      ; encoding: [0x7e,0x00,0xa2,0xd4,0x6a,0xf4,0x00,0x00]
+0x7e,0x00,0xa2,0xd4,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_cmpx_eq_f64_e64 ttmp[14:15], 0xaf123456 ; encoding: [0x7e,0x00,0xa2,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xa2,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_eq_f64_e64 -|exec|, src_scc      ; encoding: [0x7e,0x01,0xa2,0xd4,0x7e,0xfa,0x01,0x20]
+0x7e,0x01,0xa2,0xd4,0x7e,0xfa,0x01,0x20
+
+# GFX12: v_cmpx_eq_f64_e64 null, 0.5             ; encoding: [0x7e,0x00,0xa2,0xd4,0x7c,0xe0,0x01,0x00]
+0x7e,0x00,0xa2,0xd4,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_eq_f64_e64 -1, -1                ; encoding: [0x7e,0x00,0xa2,0xd4,0xc1,0x82,0x01,0x00]
+0x7e,0x00,0xa2,0xd4,0xc1,0x82,0x01,0x00
+
+# GFX12: v_cmpx_eq_f64_e64 0.5, null             ; encoding: [0x7e,0x00,0xa2,0xd4,0xf0,0xf8,0x00,0x00]
+0x7e,0x00,0xa2,0xd4,0xf0,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_eq_f64_e64 -|src_scc|, -|exec|   ; encoding: [0x7e,0x03,0xa2,0xd4,0xfd,0xfc,0x00,0x60]
+0x7e,0x03,0xa2,0xd4,0xfd,0xfc,0x00,0x60
+
+# GFX12: v_cmpx_eq_f64_e64 0xaf123456, -|vcc| clamp ; encoding: [0x7e,0x82,0xa2,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+0x7e,0x82,0xa2,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_eq_i16_e64 v1, v2                ; encoding: [0x7e,0x00,0xb2,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xb2,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_eq_i16_e64 v255, v255            ; encoding: [0x7e,0x00,0xb2,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0xb2,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_eq_i16_e64 s1, s2                ; encoding: [0x7e,0x00,0xb2,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0xb2,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_eq_i16_e64 s105, s105            ; encoding: [0x7e,0x00,0xb2,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0xb2,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_eq_i16_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0xb2,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0xb2,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_eq_i16_e64 vcc_hi, 0xfe0b        ; encoding: [0x7e,0x00,0xb2,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0xb2,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_eq_i16_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0xb2,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0xb2,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_eq_i16_e64 m0, 0x3800
+0x7e,0x00,0xb2,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_eq_i16_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0xb2,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0xb2,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_eq_i16_e64 exec_hi, null         ; encoding: [0x7e,0x00,0xb2,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x00,0xb2,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_eq_i16_e64 null, exec_lo         ; encoding: [0x7e,0x00,0xb2,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0xb2,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_eq_i16_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0xb2,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0xb2,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_eq_i16_e64 0x3800, m0
+0x7e,0x00,0xb2,0xd4,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_cmpx_eq_i16_e64 src_scc, vcc_lo       ; encoding: [0x7e,0x00,0xb2,0xd4,0xfd,0xd4,0x00,0x00]
+0x7e,0x00,0xb2,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmpx_eq_i16_e64 0xfe0b, vcc_hi        ; encoding: [0x7e,0x00,0xb2,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0xb2,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_eq_i32_e64 v1, v2                ; encoding: [0x7e,0x00,0xc2,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xc2,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_eq_i32_e64 v255, v255            ; encoding: [0x7e,0x00,0xc2,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0xc2,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_eq_i32_e64 s1, s2                ; encoding: [0x7e,0x00,0xc2,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0xc2,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_eq_i32_e64 s105, s105            ; encoding: [0x7e,0x00,0xc2,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0xc2,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_eq_i32_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0xc2,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0xc2,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_eq_i32_e64 vcc_hi, 0xaf123456    ; encoding: [0x7e,0x00,0xc2,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xc2,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_eq_i32_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0xc2,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0xc2,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_eq_i32_e64 m0, 0.5               ; encoding: [0x7e,0x00,0xc2,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0xc2,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_eq_i32_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0xc2,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0xc2,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_eq_i32_e64 exec_hi, null         ; encoding: [0x7e,0x00,0xc2,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x00,0xc2,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_eq_i32_e64 null, exec_lo         ; encoding: [0x7e,0x00,0xc2,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0xc2,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_eq_i32_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0xc2,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0xc2,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_eq_i32_e64 0.5, m0               ; encoding: [0x7e,0x00,0xc2,0xd4,0xf0,0xfa,0x00,0x00]
+0x7e,0x00,0xc2,0xd4,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_cmpx_eq_i32_e64 src_scc, vcc_lo       ; encoding: [0x7e,0x00,0xc2,0xd4,0xfd,0xd4,0x00,0x00]
+0x7e,0x00,0xc2,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmpx_eq_i32_e64 0xaf123456, vcc_hi    ; encoding: [0x7e,0x00,0xc2,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xc2,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_eq_i64_e64 v[1:2], v[2:3]        ; encoding: [0x7e,0x00,0xd2,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xd2,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_eq_i64_e64 v[254:255], v[254:255] ; encoding: [0x7e,0x00,0xd2,0xd4,0xfe,0xfd,0x03,0x00]
+0x7e,0x00,0xd2,0xd4,0xfe,0xfd,0x03,0x00
+
+# GFX12: v_cmpx_eq_i64_e64 s[2:3], s[4:5]        ; encoding: [0x7e,0x00,0xd2,0xd4,0x02,0x08,0x00,0x00]
+0x7e,0x00,0xd2,0xd4,0x02,0x08,0x00,0x00
+
+# GFX12: v_cmpx_eq_i64_e64 s[104:105], s[104:105] ; encoding: [0x7e,0x00,0xd2,0xd4,0x68,0xd0,0x00,0x00]
+0x7e,0x00,0xd2,0xd4,0x68,0xd0,0x00,0x00
+
+# GFX12: v_cmpx_eq_i64_e64 vcc, ttmp[14:15]      ; encoding: [0x7e,0x00,0xd2,0xd4,0x6a,0xf4,0x00,0x00]
+0x7e,0x00,0xd2,0xd4,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_cmpx_eq_i64_e64 ttmp[14:15], 0xaf123456 ; encoding: [0x7e,0x00,0xd2,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xd2,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_eq_i64_e64 exec, src_scc         ; encoding: [0x7e,0x00,0xd2,0xd4,0x7e,0xfa,0x01,0x00]
+0x7e,0x00,0xd2,0xd4,0x7e,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_eq_i64_e64 null, 0.5             ; encoding: [0x7e,0x00,0xd2,0xd4,0x7c,0xe0,0x01,0x00]
+0x7e,0x00,0xd2,0xd4,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_eq_i64_e64 -1, -1                ; encoding: [0x7e,0x00,0xd2,0xd4,0xc1,0x82,0x01,0x00]
+0x7e,0x00,0xd2,0xd4,0xc1,0x82,0x01,0x00
+
+# GFX12: v_cmpx_eq_i64_e64 0.5, null             ; encoding: [0x7e,0x00,0xd2,0xd4,0xf0,0xf8,0x00,0x00]
+0x7e,0x00,0xd2,0xd4,0xf0,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_eq_i64_e64 src_scc, exec         ; encoding: [0x7e,0x00,0xd2,0xd4,0xfd,0xfc,0x00,0x00]
+0x7e,0x00,0xd2,0xd4,0xfd,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_eq_i64_e64 0xaf123456, vcc       ; encoding: [0x7e,0x00,0xd2,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xd2,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_eq_u16_e64 v1, v2                ; encoding: [0x7e,0x00,0xba,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xba,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_eq_u16_e64 v255, v255            ; encoding: [0x7e,0x00,0xba,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0xba,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_eq_u16_e64 s1, s2                ; encoding: [0x7e,0x00,0xba,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0xba,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_eq_u16_e64 s105, s105            ; encoding: [0x7e,0x00,0xba,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0xba,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_eq_u16_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0xba,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0xba,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_eq_u16_e64 vcc_hi, 0xfe0b        ; encoding: [0x7e,0x00,0xba,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0xba,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_eq_u16_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0xba,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0xba,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_eq_u16_e64 m0, 0x3800
+0x7e,0x00,0xba,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_eq_u16_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0xba,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0xba,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_eq_u16_e64 exec_hi, null         ; encoding: [0x7e,0x00,0xba,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x00,0xba,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_eq_u16_e64 null, exec_lo         ; encoding: [0x7e,0x00,0xba,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0xba,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_eq_u16_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0xba,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0xba,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_eq_u16_e64 0x3800, m0
+0x7e,0x00,0xba,0xd4,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_cmpx_eq_u16_e64 src_scc, vcc_lo       ; encoding: [0x7e,0x00,0xba,0xd4,0xfd,0xd4,0x00,0x00]
+0x7e,0x00,0xba,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmpx_eq_u16_e64 0xfe0b, vcc_hi        ; encoding: [0x7e,0x00,0xba,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0xba,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_eq_u32_e64 v1, v2                ; encoding: [0x7e,0x00,0xca,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xca,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_eq_u32_e64 v255, v255            ; encoding: [0x7e,0x00,0xca,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0xca,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_eq_u32_e64 s1, s2                ; encoding: [0x7e,0x00,0xca,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0xca,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_eq_u32_e64 s105, s105            ; encoding: [0x7e,0x00,0xca,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0xca,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_eq_u32_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0xca,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0xca,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_eq_u32_e64 vcc_hi, 0xaf123456    ; encoding: [0x7e,0x00,0xca,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xca,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_eq_u32_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0xca,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0xca,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_eq_u32_e64 m0, 0.5               ; encoding: [0x7e,0x00,0xca,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0xca,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_eq_u32_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0xca,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0xca,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_eq_u32_e64 exec_hi, null         ; encoding: [0x7e,0x00,0xca,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x00,0xca,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_eq_u32_e64 null, exec_lo         ; encoding: [0x7e,0x00,0xca,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0xca,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_eq_u32_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0xca,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0xca,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_eq_u32_e64 0.5, m0               ; encoding: [0x7e,0x00,0xca,0xd4,0xf0,0xfa,0x00,0x00]
+0x7e,0x00,0xca,0xd4,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_cmpx_eq_u32_e64 src_scc, vcc_lo       ; encoding: [0x7e,0x00,0xca,0xd4,0xfd,0xd4,0x00,0x00]
+0x7e,0x00,0xca,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmpx_eq_u32_e64 0xaf123456, vcc_hi    ; encoding: [0x7e,0x00,0xca,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xca,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_eq_u64_e64 v[1:2], v[2:3]        ; encoding: [0x7e,0x00,0xda,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xda,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_eq_u64_e64 v[254:255], v[254:255] ; encoding: [0x7e,0x00,0xda,0xd4,0xfe,0xfd,0x03,0x00]
+0x7e,0x00,0xda,0xd4,0xfe,0xfd,0x03,0x00
+
+# GFX12: v_cmpx_eq_u64_e64 s[2:3], s[4:5]        ; encoding: [0x7e,0x00,0xda,0xd4,0x02,0x08,0x00,0x00]
+0x7e,0x00,0xda,0xd4,0x02,0x08,0x00,0x00
+
+# GFX12: v_cmpx_eq_u64_e64 s[104:105], s[104:105] ; encoding: [0x7e,0x00,0xda,0xd4,0x68,0xd0,0x00,0x00]
+0x7e,0x00,0xda,0xd4,0x68,0xd0,0x00,0x00
+
+# GFX12: v_cmpx_eq_u64_e64 vcc, ttmp[14:15]      ; encoding: [0x7e,0x00,0xda,0xd4,0x6a,0xf4,0x00,0x00]
+0x7e,0x00,0xda,0xd4,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_cmpx_eq_u64_e64 ttmp[14:15], 0xaf123456 ; encoding: [0x7e,0x00,0xda,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xda,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_eq_u64_e64 exec, src_scc         ; encoding: [0x7e,0x00,0xda,0xd4,0x7e,0xfa,0x01,0x00]
+0x7e,0x00,0xda,0xd4,0x7e,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_eq_u64_e64 null, 0.5             ; encoding: [0x7e,0x00,0xda,0xd4,0x7c,0xe0,0x01,0x00]
+0x7e,0x00,0xda,0xd4,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_eq_u64_e64 -1, -1                ; encoding: [0x7e,0x00,0xda,0xd4,0xc1,0x82,0x01,0x00]
+0x7e,0x00,0xda,0xd4,0xc1,0x82,0x01,0x00
+
+# GFX12: v_cmpx_eq_u64_e64 0.5, null             ; encoding: [0x7e,0x00,0xda,0xd4,0xf0,0xf8,0x00,0x00]
+0x7e,0x00,0xda,0xd4,0xf0,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_eq_u64_e64 src_scc, exec         ; encoding: [0x7e,0x00,0xda,0xd4,0xfd,0xfc,0x00,0x00]
+0x7e,0x00,0xda,0xd4,0xfd,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_eq_u64_e64 0xaf123456, vcc       ; encoding: [0x7e,0x00,0xda,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xda,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ge_f16_e64 v1, v2                ; encoding: [0x7e,0x00,0x86,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0x86,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_ge_f16_e64 v255, v255            ; encoding: [0x7e,0x00,0x86,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0x86,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_ge_f16_e64 s1, s2                ; encoding: [0x7e,0x00,0x86,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0x86,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_ge_f16_e64 s105, s105            ; encoding: [0x7e,0x00,0x86,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0x86,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_ge_f16_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0x86,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0x86,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_ge_f16_e64 vcc_hi, 0xfe0b        ; encoding: [0x7e,0x00,0x86,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0x86,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ge_f16_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0x86,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0x86,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_ge_f16_e64 m0, 0.5               ; encoding: [0x7e,0x00,0x86,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0x86,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_ge_f16_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0x86,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0x86,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_ge_f16_e64 |exec_hi|, null       ; encoding: [0x7e,0x01,0x86,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x01,0x86,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_ge_f16_e64 null, exec_lo         ; encoding: [0x7e,0x00,0x86,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0x86,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_ge_f16_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0x86,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0x86,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ge_f16_e64 0.5, -m0              ; encoding: [0x7e,0x00,0x86,0xd4,0xf0,0xfa,0x00,0x40]
+0x7e,0x00,0x86,0xd4,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cmpx_ge_f16_e64 -src_scc, |vcc_lo|    ; encoding: [0x7e,0x02,0x86,0xd4,0xfd,0xd4,0x00,0x20]
+0x7e,0x02,0x86,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmpx_ge_f16_e64 -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7e,0x83,0x86,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x7e,0x83,0x86,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ge_f32_e64 v1, v2                ; encoding: [0x7e,0x00,0x96,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0x96,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_ge_f32_e64 v255, v255            ; encoding: [0x7e,0x00,0x96,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0x96,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_ge_f32_e64 s1, s2                ; encoding: [0x7e,0x00,0x96,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0x96,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_ge_f32_e64 s105, s105            ; encoding: [0x7e,0x00,0x96,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0x96,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_ge_f32_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0x96,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0x96,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_ge_f32_e64 vcc_hi, 0xaf123456    ; encoding: [0x7e,0x00,0x96,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0x96,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ge_f32_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0x96,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0x96,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_ge_f32_e64 m0, 0.5               ; encoding: [0x7e,0x00,0x96,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0x96,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_ge_f32_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0x96,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0x96,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_ge_f32_e64 |exec_hi|, null       ; encoding: [0x7e,0x01,0x96,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x01,0x96,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_ge_f32_e64 null, exec_lo         ; encoding: [0x7e,0x00,0x96,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0x96,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_ge_f32_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0x96,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0x96,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ge_f32_e64 0.5, -m0              ; encoding: [0x7e,0x00,0x96,0xd4,0xf0,0xfa,0x00,0x40]
+0x7e,0x00,0x96,0xd4,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cmpx_ge_f32_e64 -src_scc, |vcc_lo|    ; encoding: [0x7e,0x02,0x96,0xd4,0xfd,0xd4,0x00,0x20]
+0x7e,0x02,0x96,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmpx_ge_f32_e64 -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0x7e,0x83,0x96,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0x7e,0x83,0x96,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ge_f64_e64 v[1:2], v[2:3]        ; encoding: [0x7e,0x00,0xa6,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xa6,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_ge_f64_e64 v[254:255], v[254:255] ; encoding: [0x7e,0x00,0xa6,0xd4,0xfe,0xfd,0x03,0x00]
+0x7e,0x00,0xa6,0xd4,0xfe,0xfd,0x03,0x00
+
+# GFX12: v_cmpx_ge_f64_e64 s[2:3], s[4:5]        ; encoding: [0x7e,0x00,0xa6,0xd4,0x02,0x08,0x00,0x00]
+0x7e,0x00,0xa6,0xd4,0x02,0x08,0x00,0x00
+
+# GFX12: v_cmpx_ge_f64_e64 s[104:105], s[104:105] ; encoding: [0x7e,0x00,0xa6,0xd4,0x68,0xd0,0x00,0x00]
+0x7e,0x00,0xa6,0xd4,0x68,0xd0,0x00,0x00
+
+# GFX12: v_cmpx_ge_f64_e64 vcc, ttmp[14:15]      ; encoding: [0x7e,0x00,0xa6,0xd4,0x6a,0xf4,0x00,0x00]
+0x7e,0x00,0xa6,0xd4,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_cmpx_ge_f64_e64 ttmp[14:15], 0xaf123456 ; encoding: [0x7e,0x00,0xa6,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xa6,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ge_f64_e64 -|exec|, src_scc      ; encoding: [0x7e,0x01,0xa6,0xd4,0x7e,0xfa,0x01,0x20]
+0x7e,0x01,0xa6,0xd4,0x7e,0xfa,0x01,0x20
+
+# GFX12: v_cmpx_ge_f64_e64 null, 0.5             ; encoding: [0x7e,0x00,0xa6,0xd4,0x7c,0xe0,0x01,0x00]
+0x7e,0x00,0xa6,0xd4,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_ge_f64_e64 -1, -1                ; encoding: [0x7e,0x00,0xa6,0xd4,0xc1,0x82,0x01,0x00]
+0x7e,0x00,0xa6,0xd4,0xc1,0x82,0x01,0x00
+
+# GFX12: v_cmpx_ge_f64_e64 0.5, null             ; encoding: [0x7e,0x00,0xa6,0xd4,0xf0,0xf8,0x00,0x00]
+0x7e,0x00,0xa6,0xd4,0xf0,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_ge_f64_e64 -|src_scc|, -|exec|   ; encoding: [0x7e,0x03,0xa6,0xd4,0xfd,0xfc,0x00,0x60]
+0x7e,0x03,0xa6,0xd4,0xfd,0xfc,0x00,0x60
+
+# GFX12: v_cmpx_ge_f64_e64 0xaf123456, -|vcc| clamp ; encoding: [0x7e,0x82,0xa6,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+0x7e,0x82,0xa6,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ge_i16_e64 v1, v2                ; encoding: [0x7e,0x00,0xb6,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xb6,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_ge_i16_e64 v255, v255            ; encoding: [0x7e,0x00,0xb6,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0xb6,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_ge_i16_e64 s1, s2                ; encoding: [0x7e,0x00,0xb6,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0xb6,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_ge_i16_e64 s105, s105            ; encoding: [0x7e,0x00,0xb6,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0xb6,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_ge_i16_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0xb6,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0xb6,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_ge_i16_e64 vcc_hi, 0xfe0b        ; encoding: [0x7e,0x00,0xb6,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0xb6,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ge_i16_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0xb6,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0xb6,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_ge_i16_e64 m0, 0x3800
+0x7e,0x00,0xb6,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_ge_i16_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0xb6,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0xb6,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_ge_i16_e64 exec_hi, null         ; encoding: [0x7e,0x00,0xb6,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x00,0xb6,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_ge_i16_e64 null, exec_lo         ; encoding: [0x7e,0x00,0xb6,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0xb6,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_ge_i16_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0xb6,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0xb6,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ge_i16_e64 0x3800, m0
+0x7e,0x00,0xb6,0xd4,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_cmpx_ge_i16_e64 src_scc, vcc_lo       ; encoding: [0x7e,0x00,0xb6,0xd4,0xfd,0xd4,0x00,0x00]
+0x7e,0x00,0xb6,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmpx_ge_i16_e64 0xfe0b, vcc_hi        ; encoding: [0x7e,0x00,0xb6,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0xb6,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ge_i32_e64 v1, v2                ; encoding: [0x7e,0x00,0xc6,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xc6,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_ge_i32_e64 v255, v255            ; encoding: [0x7e,0x00,0xc6,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0xc6,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_ge_i32_e64 s1, s2                ; encoding: [0x7e,0x00,0xc6,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0xc6,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_ge_i32_e64 s105, s105            ; encoding: [0x7e,0x00,0xc6,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0xc6,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_ge_i32_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0xc6,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0xc6,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_ge_i32_e64 vcc_hi, 0xaf123456    ; encoding: [0x7e,0x00,0xc6,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xc6,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ge_i32_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0xc6,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0xc6,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_ge_i32_e64 m0, 0.5               ; encoding: [0x7e,0x00,0xc6,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0xc6,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_ge_i32_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0xc6,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0xc6,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_ge_i32_e64 exec_hi, null         ; encoding: [0x7e,0x00,0xc6,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x00,0xc6,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_ge_i32_e64 null, exec_lo         ; encoding: [0x7e,0x00,0xc6,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0xc6,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_ge_i32_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0xc6,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0xc6,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ge_i32_e64 0.5, m0               ; encoding: [0x7e,0x00,0xc6,0xd4,0xf0,0xfa,0x00,0x00]
+0x7e,0x00,0xc6,0xd4,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_cmpx_ge_i32_e64 src_scc, vcc_lo       ; encoding: [0x7e,0x00,0xc6,0xd4,0xfd,0xd4,0x00,0x00]
+0x7e,0x00,0xc6,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmpx_ge_i32_e64 0xaf123456, vcc_hi    ; encoding: [0x7e,0x00,0xc6,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xc6,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ge_i64_e64 v[1:2], v[2:3]        ; encoding: [0x7e,0x00,0xd6,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xd6,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_ge_i64_e64 v[254:255], v[254:255] ; encoding: [0x7e,0x00,0xd6,0xd4,0xfe,0xfd,0x03,0x00]
+0x7e,0x00,0xd6,0xd4,0xfe,0xfd,0x03,0x00
+
+# GFX12: v_cmpx_ge_i64_e64 s[2:3], s[4:5]        ; encoding: [0x7e,0x00,0xd6,0xd4,0x02,0x08,0x00,0x00]
+0x7e,0x00,0xd6,0xd4,0x02,0x08,0x00,0x00
+
+# GFX12: v_cmpx_ge_i64_e64 s[104:105], s[104:105] ; encoding: [0x7e,0x00,0xd6,0xd4,0x68,0xd0,0x00,0x00]
+0x7e,0x00,0xd6,0xd4,0x68,0xd0,0x00,0x00
+
+# GFX12: v_cmpx_ge_i64_e64 vcc, ttmp[14:15]      ; encoding: [0x7e,0x00,0xd6,0xd4,0x6a,0xf4,0x00,0x00]
+0x7e,0x00,0xd6,0xd4,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_cmpx_ge_i64_e64 ttmp[14:15], 0xaf123456 ; encoding: [0x7e,0x00,0xd6,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xd6,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ge_i64_e64 exec, src_scc         ; encoding: [0x7e,0x00,0xd6,0xd4,0x7e,0xfa,0x01,0x00]
+0x7e,0x00,0xd6,0xd4,0x7e,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_ge_i64_e64 null, 0.5             ; encoding: [0x7e,0x00,0xd6,0xd4,0x7c,0xe0,0x01,0x00]
+0x7e,0x00,0xd6,0xd4,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_ge_i64_e64 -1, -1                ; encoding: [0x7e,0x00,0xd6,0xd4,0xc1,0x82,0x01,0x00]
+0x7e,0x00,0xd6,0xd4,0xc1,0x82,0x01,0x00
+
+# GFX12: v_cmpx_ge_i64_e64 0.5, null             ; encoding: [0x7e,0x00,0xd6,0xd4,0xf0,0xf8,0x00,0x00]
+0x7e,0x00,0xd6,0xd4,0xf0,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_ge_i64_e64 src_scc, exec         ; encoding: [0x7e,0x00,0xd6,0xd4,0xfd,0xfc,0x00,0x00]
+0x7e,0x00,0xd6,0xd4,0xfd,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_ge_i64_e64 0xaf123456, vcc       ; encoding: [0x7e,0x00,0xd6,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xd6,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ge_u16_e64 v1, v2                ; encoding: [0x7e,0x00,0xbe,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xbe,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_ge_u16_e64 v255, v255            ; encoding: [0x7e,0x00,0xbe,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0xbe,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_ge_u16_e64 s1, s2                ; encoding: [0x7e,0x00,0xbe,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0xbe,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_ge_u16_e64 s105, s105            ; encoding: [0x7e,0x00,0xbe,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0xbe,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_ge_u16_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0xbe,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0xbe,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_ge_u16_e64 vcc_hi, 0xfe0b        ; encoding: [0x7e,0x00,0xbe,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0xbe,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ge_u16_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0xbe,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0xbe,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_ge_u16_e64 m0, 0x3800
+0x7e,0x00,0xbe,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_ge_u16_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0xbe,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0xbe,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_ge_u16_e64 exec_hi, null         ; encoding: [0x7e,0x00,0xbe,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x00,0xbe,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_ge_u16_e64 null, exec_lo         ; encoding: [0x7e,0x00,0xbe,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0xbe,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_ge_u16_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0xbe,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0xbe,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ge_u16_e64 0x3800, m0
+0x7e,0x00,0xbe,0xd4,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_cmpx_ge_u16_e64 src_scc, vcc_lo       ; encoding: [0x7e,0x00,0xbe,0xd4,0xfd,0xd4,0x00,0x00]
+0x7e,0x00,0xbe,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmpx_ge_u16_e64 0xfe0b, vcc_hi        ; encoding: [0x7e,0x00,0xbe,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0xbe,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ge_u32_e64 v1, v2                ; encoding: [0x7e,0x00,0xce,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xce,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_ge_u32_e64 v255, v255            ; encoding: [0x7e,0x00,0xce,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0xce,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_ge_u32_e64 s1, s2                ; encoding: [0x7e,0x00,0xce,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0xce,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_ge_u32_e64 s105, s105            ; encoding: [0x7e,0x00,0xce,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0xce,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_ge_u32_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0xce,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0xce,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_ge_u32_e64 vcc_hi, 0xaf123456    ; encoding: [0x7e,0x00,0xce,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xce,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ge_u32_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0xce,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0xce,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_ge_u32_e64 m0, 0.5               ; encoding: [0x7e,0x00,0xce,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0xce,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_ge_u32_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0xce,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0xce,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_ge_u32_e64 exec_hi, null         ; encoding: [0x7e,0x00,0xce,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x00,0xce,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_ge_u32_e64 null, exec_lo         ; encoding: [0x7e,0x00,0xce,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0xce,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_ge_u32_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0xce,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0xce,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ge_u32_e64 0.5, m0               ; encoding: [0x7e,0x00,0xce,0xd4,0xf0,0xfa,0x00,0x00]
+0x7e,0x00,0xce,0xd4,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_cmpx_ge_u32_e64 src_scc, vcc_lo       ; encoding: [0x7e,0x00,0xce,0xd4,0xfd,0xd4,0x00,0x00]
+0x7e,0x00,0xce,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmpx_ge_u32_e64 0xaf123456, vcc_hi    ; encoding: [0x7e,0x00,0xce,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xce,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ge_u64_e64 v[1:2], v[2:3]        ; encoding: [0x7e,0x00,0xde,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xde,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_ge_u64_e64 v[254:255], v[254:255] ; encoding: [0x7e,0x00,0xde,0xd4,0xfe,0xfd,0x03,0x00]
+0x7e,0x00,0xde,0xd4,0xfe,0xfd,0x03,0x00
+
+# GFX12: v_cmpx_ge_u64_e64 s[2:3], s[4:5]        ; encoding: [0x7e,0x00,0xde,0xd4,0x02,0x08,0x00,0x00]
+0x7e,0x00,0xde,0xd4,0x02,0x08,0x00,0x00
+
+# GFX12: v_cmpx_ge_u64_e64 s[104:105], s[104:105] ; encoding: [0x7e,0x00,0xde,0xd4,0x68,0xd0,0x00,0x00]
+0x7e,0x00,0xde,0xd4,0x68,0xd0,0x00,0x00
+
+# GFX12: v_cmpx_ge_u64_e64 vcc, ttmp[14:15]      ; encoding: [0x7e,0x00,0xde,0xd4,0x6a,0xf4,0x00,0x00]
+0x7e,0x00,0xde,0xd4,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_cmpx_ge_u64_e64 ttmp[14:15], 0xaf123456 ; encoding: [0x7e,0x00,0xde,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xde,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ge_u64_e64 exec, src_scc         ; encoding: [0x7e,0x00,0xde,0xd4,0x7e,0xfa,0x01,0x00]
+0x7e,0x00,0xde,0xd4,0x7e,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_ge_u64_e64 null, 0.5             ; encoding: [0x7e,0x00,0xde,0xd4,0x7c,0xe0,0x01,0x00]
+0x7e,0x00,0xde,0xd4,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_ge_u64_e64 -1, -1                ; encoding: [0x7e,0x00,0xde,0xd4,0xc1,0x82,0x01,0x00]
+0x7e,0x00,0xde,0xd4,0xc1,0x82,0x01,0x00
+
+# GFX12: v_cmpx_ge_u64_e64 0.5, null             ; encoding: [0x7e,0x00,0xde,0xd4,0xf0,0xf8,0x00,0x00]
+0x7e,0x00,0xde,0xd4,0xf0,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_ge_u64_e64 src_scc, exec         ; encoding: [0x7e,0x00,0xde,0xd4,0xfd,0xfc,0x00,0x00]
+0x7e,0x00,0xde,0xd4,0xfd,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_ge_u64_e64 0xaf123456, vcc       ; encoding: [0x7e,0x00,0xde,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xde,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_gt_f16_e64 v1, v2                ; encoding: [0x7e,0x00,0x84,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0x84,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_gt_f16_e64 v255, v255            ; encoding: [0x7e,0x00,0x84,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0x84,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_gt_f16_e64 s1, s2                ; encoding: [0x7e,0x00,0x84,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0x84,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_gt_f16_e64 s105, s105            ; encoding: [0x7e,0x00,0x84,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0x84,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_gt_f16_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0x84,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0x84,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_gt_f16_e64 vcc_hi, 0xfe0b        ; encoding: [0x7e,0x00,0x84,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0x84,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_gt_f16_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0x84,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0x84,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_gt_f16_e64 m0, 0.5               ; encoding: [0x7e,0x00,0x84,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0x84,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_gt_f16_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0x84,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0x84,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_gt_f16_e64 |exec_hi|, null       ; encoding: [0x7e,0x01,0x84,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x01,0x84,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_gt_f16_e64 null, exec_lo         ; encoding: [0x7e,0x00,0x84,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0x84,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_gt_f16_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0x84,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0x84,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_gt_f16_e64 0.5, -m0              ; encoding: [0x7e,0x00,0x84,0xd4,0xf0,0xfa,0x00,0x40]
+0x7e,0x00,0x84,0xd4,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cmpx_gt_f16_e64 -src_scc, |vcc_lo|    ; encoding: [0x7e,0x02,0x84,0xd4,0xfd,0xd4,0x00,0x20]
+0x7e,0x02,0x84,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmpx_gt_f16_e64 -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7e,0x83,0x84,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x7e,0x83,0x84,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_gt_f32_e64 v1, v2                ; encoding: [0x7e,0x00,0x94,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0x94,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_gt_f32_e64 v255, v255            ; encoding: [0x7e,0x00,0x94,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0x94,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_gt_f32_e64 s1, s2                ; encoding: [0x7e,0x00,0x94,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0x94,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_gt_f32_e64 s105, s105            ; encoding: [0x7e,0x00,0x94,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0x94,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_gt_f32_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0x94,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0x94,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_gt_f32_e64 vcc_hi, 0xaf123456    ; encoding: [0x7e,0x00,0x94,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0x94,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_gt_f32_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0x94,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0x94,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_gt_f32_e64 m0, 0.5               ; encoding: [0x7e,0x00,0x94,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0x94,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_gt_f32_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0x94,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0x94,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_gt_f32_e64 |exec_hi|, null       ; encoding: [0x7e,0x01,0x94,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x01,0x94,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_gt_f32_e64 null, exec_lo         ; encoding: [0x7e,0x00,0x94,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0x94,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_gt_f32_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0x94,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0x94,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_gt_f32_e64 0.5, -m0              ; encoding: [0x7e,0x00,0x94,0xd4,0xf0,0xfa,0x00,0x40]
+0x7e,0x00,0x94,0xd4,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cmpx_gt_f32_e64 -src_scc, |vcc_lo|    ; encoding: [0x7e,0x02,0x94,0xd4,0xfd,0xd4,0x00,0x20]
+0x7e,0x02,0x94,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmpx_gt_f32_e64 -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0x7e,0x83,0x94,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0x7e,0x83,0x94,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_gt_f64_e64 v[1:2], v[2:3]        ; encoding: [0x7e,0x00,0xa4,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xa4,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_gt_f64_e64 v[254:255], v[254:255] ; encoding: [0x7e,0x00,0xa4,0xd4,0xfe,0xfd,0x03,0x00]
+0x7e,0x00,0xa4,0xd4,0xfe,0xfd,0x03,0x00
+
+# GFX12: v_cmpx_gt_f64_e64 s[2:3], s[4:5]        ; encoding: [0x7e,0x00,0xa4,0xd4,0x02,0x08,0x00,0x00]
+0x7e,0x00,0xa4,0xd4,0x02,0x08,0x00,0x00
+
+# GFX12: v_cmpx_gt_f64_e64 s[104:105], s[104:105] ; encoding: [0x7e,0x00,0xa4,0xd4,0x68,0xd0,0x00,0x00]
+0x7e,0x00,0xa4,0xd4,0x68,0xd0,0x00,0x00
+
+# GFX12: v_cmpx_gt_f64_e64 vcc, ttmp[14:15]      ; encoding: [0x7e,0x00,0xa4,0xd4,0x6a,0xf4,0x00,0x00]
+0x7e,0x00,0xa4,0xd4,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_cmpx_gt_f64_e64 ttmp[14:15], 0xaf123456 ; encoding: [0x7e,0x00,0xa4,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xa4,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_gt_f64_e64 -|exec|, src_scc      ; encoding: [0x7e,0x01,0xa4,0xd4,0x7e,0xfa,0x01,0x20]
+0x7e,0x01,0xa4,0xd4,0x7e,0xfa,0x01,0x20
+
+# GFX12: v_cmpx_gt_f64_e64 null, 0.5             ; encoding: [0x7e,0x00,0xa4,0xd4,0x7c,0xe0,0x01,0x00]
+0x7e,0x00,0xa4,0xd4,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_gt_f64_e64 -1, -1                ; encoding: [0x7e,0x00,0xa4,0xd4,0xc1,0x82,0x01,0x00]
+0x7e,0x00,0xa4,0xd4,0xc1,0x82,0x01,0x00
+
+# GFX12: v_cmpx_gt_f64_e64 0.5, null             ; encoding: [0x7e,0x00,0xa4,0xd4,0xf0,0xf8,0x00,0x00]
+0x7e,0x00,0xa4,0xd4,0xf0,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_gt_f64_e64 -|src_scc|, -|exec|   ; encoding: [0x7e,0x03,0xa4,0xd4,0xfd,0xfc,0x00,0x60]
+0x7e,0x03,0xa4,0xd4,0xfd,0xfc,0x00,0x60
+
+# GFX12: v_cmpx_gt_f64_e64 0xaf123456, -|vcc| clamp ; encoding: [0x7e,0x82,0xa4,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+0x7e,0x82,0xa4,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_gt_i16_e64 v1, v2                ; encoding: [0x7e,0x00,0xb4,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xb4,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_gt_i16_e64 v255, v255            ; encoding: [0x7e,0x00,0xb4,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0xb4,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_gt_i16_e64 s1, s2                ; encoding: [0x7e,0x00,0xb4,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0xb4,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_gt_i16_e64 s105, s105            ; encoding: [0x7e,0x00,0xb4,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0xb4,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_gt_i16_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0xb4,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0xb4,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_gt_i16_e64 vcc_hi, 0xfe0b        ; encoding: [0x7e,0x00,0xb4,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0xb4,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_gt_i16_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0xb4,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0xb4,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_gt_i16_e64 m0, 0x3800
+0x7e,0x00,0xb4,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_gt_i16_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0xb4,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0xb4,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_gt_i16_e64 exec_hi, null         ; encoding: [0x7e,0x00,0xb4,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x00,0xb4,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_gt_i16_e64 null, exec_lo         ; encoding: [0x7e,0x00,0xb4,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0xb4,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_gt_i16_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0xb4,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0xb4,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_gt_i16_e64 0x3800, m0
+0x7e,0x00,0xb4,0xd4,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_cmpx_gt_i16_e64 src_scc, vcc_lo       ; encoding: [0x7e,0x00,0xb4,0xd4,0xfd,0xd4,0x00,0x00]
+0x7e,0x00,0xb4,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmpx_gt_i16_e64 0xfe0b, vcc_hi        ; encoding: [0x7e,0x00,0xb4,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0xb4,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_gt_i32_e64 v1, v2                ; encoding: [0x7e,0x00,0xc4,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xc4,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_gt_i32_e64 v255, v255            ; encoding: [0x7e,0x00,0xc4,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0xc4,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_gt_i32_e64 s1, s2                ; encoding: [0x7e,0x00,0xc4,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0xc4,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_gt_i32_e64 s105, s105            ; encoding: [0x7e,0x00,0xc4,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0xc4,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_gt_i32_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0xc4,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0xc4,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_gt_i32_e64 vcc_hi, 0xaf123456    ; encoding: [0x7e,0x00,0xc4,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xc4,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_gt_i32_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0xc4,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0xc4,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_gt_i32_e64 m0, 0.5               ; encoding: [0x7e,0x00,0xc4,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0xc4,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_gt_i32_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0xc4,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0xc4,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_gt_i32_e64 exec_hi, null         ; encoding: [0x7e,0x00,0xc4,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x00,0xc4,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_gt_i32_e64 null, exec_lo         ; encoding: [0x7e,0x00,0xc4,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0xc4,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_gt_i32_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0xc4,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0xc4,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_gt_i32_e64 0.5, m0               ; encoding: [0x7e,0x00,0xc4,0xd4,0xf0,0xfa,0x00,0x00]
+0x7e,0x00,0xc4,0xd4,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_cmpx_gt_i32_e64 src_scc, vcc_lo       ; encoding: [0x7e,0x00,0xc4,0xd4,0xfd,0xd4,0x00,0x00]
+0x7e,0x00,0xc4,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmpx_gt_i32_e64 0xaf123456, vcc_hi    ; encoding: [0x7e,0x00,0xc4,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xc4,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_gt_i64_e64 v[1:2], v[2:3]        ; encoding: [0x7e,0x00,0xd4,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xd4,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_gt_i64_e64 v[254:255], v[254:255] ; encoding: [0x7e,0x00,0xd4,0xd4,0xfe,0xfd,0x03,0x00]
+0x7e,0x00,0xd4,0xd4,0xfe,0xfd,0x03,0x00
+
+# GFX12: v_cmpx_gt_i64_e64 s[2:3], s[4:5]        ; encoding: [0x7e,0x00,0xd4,0xd4,0x02,0x08,0x00,0x00]
+0x7e,0x00,0xd4,0xd4,0x02,0x08,0x00,0x00
+
+# GFX12: v_cmpx_gt_i64_e64 s[104:105], s[104:105] ; encoding: [0x7e,0x00,0xd4,0xd4,0x68,0xd0,0x00,0x00]
+0x7e,0x00,0xd4,0xd4,0x68,0xd0,0x00,0x00
+
+# GFX12: v_cmpx_gt_i64_e64 vcc, ttmp[14:15]      ; encoding: [0x7e,0x00,0xd4,0xd4,0x6a,0xf4,0x00,0x00]
+0x7e,0x00,0xd4,0xd4,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_cmpx_gt_i64_e64 ttmp[14:15], 0xaf123456 ; encoding: [0x7e,0x00,0xd4,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xd4,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_gt_i64_e64 exec, src_scc         ; encoding: [0x7e,0x00,0xd4,0xd4,0x7e,0xfa,0x01,0x00]
+0x7e,0x00,0xd4,0xd4,0x7e,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_gt_i64_e64 null, 0.5             ; encoding: [0x7e,0x00,0xd4,0xd4,0x7c,0xe0,0x01,0x00]
+0x7e,0x00,0xd4,0xd4,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_gt_i64_e64 -1, -1                ; encoding: [0x7e,0x00,0xd4,0xd4,0xc1,0x82,0x01,0x00]
+0x7e,0x00,0xd4,0xd4,0xc1,0x82,0x01,0x00
+
+# GFX12: v_cmpx_gt_i64_e64 0.5, null             ; encoding: [0x7e,0x00,0xd4,0xd4,0xf0,0xf8,0x00,0x00]
+0x7e,0x00,0xd4,0xd4,0xf0,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_gt_i64_e64 src_scc, exec         ; encoding: [0x7e,0x00,0xd4,0xd4,0xfd,0xfc,0x00,0x00]
+0x7e,0x00,0xd4,0xd4,0xfd,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_gt_i64_e64 0xaf123456, vcc       ; encoding: [0x7e,0x00,0xd4,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xd4,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_gt_u16_e64 v1, v2                ; encoding: [0x7e,0x00,0xbc,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xbc,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_gt_u16_e64 v255, v255            ; encoding: [0x7e,0x00,0xbc,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0xbc,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_gt_u16_e64 s1, s2                ; encoding: [0x7e,0x00,0xbc,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0xbc,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_gt_u16_e64 s105, s105            ; encoding: [0x7e,0x00,0xbc,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0xbc,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_gt_u16_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0xbc,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0xbc,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_gt_u16_e64 vcc_hi, 0xfe0b        ; encoding: [0x7e,0x00,0xbc,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0xbc,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_gt_u16_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0xbc,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0xbc,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_gt_u16_e64 m0, 0x3800
+0x7e,0x00,0xbc,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_gt_u16_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0xbc,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0xbc,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_gt_u16_e64 exec_hi, null         ; encoding: [0x7e,0x00,0xbc,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x00,0xbc,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_gt_u16_e64 null, exec_lo         ; encoding: [0x7e,0x00,0xbc,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0xbc,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_gt_u16_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0xbc,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0xbc,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_gt_u16_e64 0x3800, m0
+0x7e,0x00,0xbc,0xd4,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_cmpx_gt_u16_e64 src_scc, vcc_lo       ; encoding: [0x7e,0x00,0xbc,0xd4,0xfd,0xd4,0x00,0x00]
+0x7e,0x00,0xbc,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmpx_gt_u16_e64 0xfe0b, vcc_hi        ; encoding: [0x7e,0x00,0xbc,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0xbc,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_gt_u32_e64 v1, v2                ; encoding: [0x7e,0x00,0xcc,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xcc,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_gt_u32_e64 v255, v255            ; encoding: [0x7e,0x00,0xcc,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0xcc,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_gt_u32_e64 s1, s2                ; encoding: [0x7e,0x00,0xcc,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0xcc,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_gt_u32_e64 s105, s105            ; encoding: [0x7e,0x00,0xcc,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0xcc,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_gt_u32_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0xcc,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0xcc,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_gt_u32_e64 vcc_hi, 0xaf123456    ; encoding: [0x7e,0x00,0xcc,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xcc,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_gt_u32_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0xcc,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0xcc,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_gt_u32_e64 m0, 0.5               ; encoding: [0x7e,0x00,0xcc,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0xcc,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_gt_u32_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0xcc,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0xcc,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_gt_u32_e64 exec_hi, null         ; encoding: [0x7e,0x00,0xcc,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x00,0xcc,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_gt_u32_e64 null, exec_lo         ; encoding: [0x7e,0x00,0xcc,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0xcc,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_gt_u32_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0xcc,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0xcc,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_gt_u32_e64 0.5, m0               ; encoding: [0x7e,0x00,0xcc,0xd4,0xf0,0xfa,0x00,0x00]
+0x7e,0x00,0xcc,0xd4,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_cmpx_gt_u32_e64 src_scc, vcc_lo       ; encoding: [0x7e,0x00,0xcc,0xd4,0xfd,0xd4,0x00,0x00]
+0x7e,0x00,0xcc,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmpx_gt_u32_e64 0xaf123456, vcc_hi    ; encoding: [0x7e,0x00,0xcc,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xcc,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_gt_u64_e64 v[1:2], v[2:3]        ; encoding: [0x7e,0x00,0xdc,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xdc,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_gt_u64_e64 v[254:255], v[254:255] ; encoding: [0x7e,0x00,0xdc,0xd4,0xfe,0xfd,0x03,0x00]
+0x7e,0x00,0xdc,0xd4,0xfe,0xfd,0x03,0x00
+
+# GFX12: v_cmpx_gt_u64_e64 s[2:3], s[4:5]        ; encoding: [0x7e,0x00,0xdc,0xd4,0x02,0x08,0x00,0x00]
+0x7e,0x00,0xdc,0xd4,0x02,0x08,0x00,0x00
+
+# GFX12: v_cmpx_gt_u64_e64 s[104:105], s[104:105] ; encoding: [0x7e,0x00,0xdc,0xd4,0x68,0xd0,0x00,0x00]
+0x7e,0x00,0xdc,0xd4,0x68,0xd0,0x00,0x00
+
+# GFX12: v_cmpx_gt_u64_e64 vcc, ttmp[14:15]      ; encoding: [0x7e,0x00,0xdc,0xd4,0x6a,0xf4,0x00,0x00]
+0x7e,0x00,0xdc,0xd4,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_cmpx_gt_u64_e64 ttmp[14:15], 0xaf123456 ; encoding: [0x7e,0x00,0xdc,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xdc,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_gt_u64_e64 exec, src_scc         ; encoding: [0x7e,0x00,0xdc,0xd4,0x7e,0xfa,0x01,0x00]
+0x7e,0x00,0xdc,0xd4,0x7e,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_gt_u64_e64 null, 0.5             ; encoding: [0x7e,0x00,0xdc,0xd4,0x7c,0xe0,0x01,0x00]
+0x7e,0x00,0xdc,0xd4,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_gt_u64_e64 -1, -1                ; encoding: [0x7e,0x00,0xdc,0xd4,0xc1,0x82,0x01,0x00]
+0x7e,0x00,0xdc,0xd4,0xc1,0x82,0x01,0x00
+
+# GFX12: v_cmpx_gt_u64_e64 0.5, null             ; encoding: [0x7e,0x00,0xdc,0xd4,0xf0,0xf8,0x00,0x00]
+0x7e,0x00,0xdc,0xd4,0xf0,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_gt_u64_e64 src_scc, exec         ; encoding: [0x7e,0x00,0xdc,0xd4,0xfd,0xfc,0x00,0x00]
+0x7e,0x00,0xdc,0xd4,0xfd,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_gt_u64_e64 0xaf123456, vcc       ; encoding: [0x7e,0x00,0xdc,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xdc,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_le_f16_e64 v1, v2                ; encoding: [0x7e,0x00,0x83,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0x83,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_le_f16_e64 v255, v255            ; encoding: [0x7e,0x00,0x83,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0x83,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_le_f16_e64 s1, s2                ; encoding: [0x7e,0x00,0x83,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0x83,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_le_f16_e64 s105, s105            ; encoding: [0x7e,0x00,0x83,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0x83,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_le_f16_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0x83,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0x83,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_le_f16_e64 vcc_hi, 0xfe0b        ; encoding: [0x7e,0x00,0x83,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0x83,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_le_f16_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0x83,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0x83,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_le_f16_e64 m0, 0.5               ; encoding: [0x7e,0x00,0x83,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0x83,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_le_f16_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0x83,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0x83,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_le_f16_e64 |exec_hi|, null       ; encoding: [0x7e,0x01,0x83,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x01,0x83,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_le_f16_e64 null, exec_lo         ; encoding: [0x7e,0x00,0x83,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0x83,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_le_f16_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0x83,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0x83,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_le_f16_e64 0.5, -m0              ; encoding: [0x7e,0x00,0x83,0xd4,0xf0,0xfa,0x00,0x40]
+0x7e,0x00,0x83,0xd4,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cmpx_le_f16_e64 -src_scc, |vcc_lo|    ; encoding: [0x7e,0x02,0x83,0xd4,0xfd,0xd4,0x00,0x20]
+0x7e,0x02,0x83,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmpx_le_f16_e64 -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7e,0x83,0x83,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x7e,0x83,0x83,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_le_f32_e64 v1, v2                ; encoding: [0x7e,0x00,0x93,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0x93,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_le_f32_e64 v255, v255            ; encoding: [0x7e,0x00,0x93,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0x93,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_le_f32_e64 s1, s2                ; encoding: [0x7e,0x00,0x93,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0x93,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_le_f32_e64 s105, s105            ; encoding: [0x7e,0x00,0x93,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0x93,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_le_f32_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0x93,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0x93,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_le_f32_e64 vcc_hi, 0xaf123456    ; encoding: [0x7e,0x00,0x93,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0x93,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_le_f32_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0x93,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0x93,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_le_f32_e64 m0, 0.5               ; encoding: [0x7e,0x00,0x93,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0x93,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_le_f32_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0x93,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0x93,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_le_f32_e64 |exec_hi|, null       ; encoding: [0x7e,0x01,0x93,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x01,0x93,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_le_f32_e64 null, exec_lo         ; encoding: [0x7e,0x00,0x93,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0x93,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_le_f32_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0x93,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0x93,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_le_f32_e64 0.5, -m0              ; encoding: [0x7e,0x00,0x93,0xd4,0xf0,0xfa,0x00,0x40]
+0x7e,0x00,0x93,0xd4,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cmpx_le_f32_e64 -src_scc, |vcc_lo|    ; encoding: [0x7e,0x02,0x93,0xd4,0xfd,0xd4,0x00,0x20]
+0x7e,0x02,0x93,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmpx_le_f32_e64 -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0x7e,0x83,0x93,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0x7e,0x83,0x93,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_le_f64_e64 v[1:2], v[2:3]        ; encoding: [0x7e,0x00,0xa3,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xa3,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_le_f64_e64 v[254:255], v[254:255] ; encoding: [0x7e,0x00,0xa3,0xd4,0xfe,0xfd,0x03,0x00]
+0x7e,0x00,0xa3,0xd4,0xfe,0xfd,0x03,0x00
+
+# GFX12: v_cmpx_le_f64_e64 s[2:3], s[4:5]        ; encoding: [0x7e,0x00,0xa3,0xd4,0x02,0x08,0x00,0x00]
+0x7e,0x00,0xa3,0xd4,0x02,0x08,0x00,0x00
+
+# GFX12: v_cmpx_le_f64_e64 s[104:105], s[104:105] ; encoding: [0x7e,0x00,0xa3,0xd4,0x68,0xd0,0x00,0x00]
+0x7e,0x00,0xa3,0xd4,0x68,0xd0,0x00,0x00
+
+# GFX12: v_cmpx_le_f64_e64 vcc, ttmp[14:15]      ; encoding: [0x7e,0x00,0xa3,0xd4,0x6a,0xf4,0x00,0x00]
+0x7e,0x00,0xa3,0xd4,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_cmpx_le_f64_e64 ttmp[14:15], 0xaf123456 ; encoding: [0x7e,0x00,0xa3,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xa3,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_le_f64_e64 -|exec|, src_scc      ; encoding: [0x7e,0x01,0xa3,0xd4,0x7e,0xfa,0x01,0x20]
+0x7e,0x01,0xa3,0xd4,0x7e,0xfa,0x01,0x20
+
+# GFX12: v_cmpx_le_f64_e64 null, 0.5             ; encoding: [0x7e,0x00,0xa3,0xd4,0x7c,0xe0,0x01,0x00]
+0x7e,0x00,0xa3,0xd4,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_le_f64_e64 -1, -1                ; encoding: [0x7e,0x00,0xa3,0xd4,0xc1,0x82,0x01,0x00]
+0x7e,0x00,0xa3,0xd4,0xc1,0x82,0x01,0x00
+
+# GFX12: v_cmpx_le_f64_e64 0.5, null             ; encoding: [0x7e,0x00,0xa3,0xd4,0xf0,0xf8,0x00,0x00]
+0x7e,0x00,0xa3,0xd4,0xf0,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_le_f64_e64 -|src_scc|, -|exec|   ; encoding: [0x7e,0x03,0xa3,0xd4,0xfd,0xfc,0x00,0x60]
+0x7e,0x03,0xa3,0xd4,0xfd,0xfc,0x00,0x60
+
+# GFX12: v_cmpx_le_f64_e64 0xaf123456, -|vcc| clamp ; encoding: [0x7e,0x82,0xa3,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+0x7e,0x82,0xa3,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_le_i16_e64 v1, v2                ; encoding: [0x7e,0x00,0xb3,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xb3,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_le_i16_e64 v255, v255            ; encoding: [0x7e,0x00,0xb3,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0xb3,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_le_i16_e64 s1, s2                ; encoding: [0x7e,0x00,0xb3,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0xb3,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_le_i16_e64 s105, s105            ; encoding: [0x7e,0x00,0xb3,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0xb3,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_le_i16_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0xb3,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0xb3,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_le_i16_e64 vcc_hi, 0xfe0b        ; encoding: [0x7e,0x00,0xb3,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0xb3,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_le_i16_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0xb3,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0xb3,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_le_i16_e64 m0, 0x3800
+0x7e,0x00,0xb3,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_le_i16_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0xb3,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0xb3,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_le_i16_e64 exec_hi, null         ; encoding: [0x7e,0x00,0xb3,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x00,0xb3,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_le_i16_e64 null, exec_lo         ; encoding: [0x7e,0x00,0xb3,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0xb3,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_le_i16_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0xb3,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0xb3,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_le_i16_e64 0x3800, m0
+0x7e,0x00,0xb3,0xd4,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_cmpx_le_i16_e64 src_scc, vcc_lo       ; encoding: [0x7e,0x00,0xb3,0xd4,0xfd,0xd4,0x00,0x00]
+0x7e,0x00,0xb3,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmpx_le_i16_e64 0xfe0b, vcc_hi        ; encoding: [0x7e,0x00,0xb3,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0xb3,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_le_i32_e64 v1, v2                ; encoding: [0x7e,0x00,0xc3,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xc3,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_le_i32_e64 v255, v255            ; encoding: [0x7e,0x00,0xc3,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0xc3,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_le_i32_e64 s1, s2                ; encoding: [0x7e,0x00,0xc3,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0xc3,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_le_i32_e64 s105, s105            ; encoding: [0x7e,0x00,0xc3,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0xc3,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_le_i32_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0xc3,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0xc3,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_le_i32_e64 vcc_hi, 0xaf123456    ; encoding: [0x7e,0x00,0xc3,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xc3,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_le_i32_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0xc3,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0xc3,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_le_i32_e64 m0, 0.5               ; encoding: [0x7e,0x00,0xc3,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0xc3,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_le_i32_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0xc3,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0xc3,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_le_i32_e64 exec_hi, null         ; encoding: [0x7e,0x00,0xc3,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x00,0xc3,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_le_i32_e64 null, exec_lo         ; encoding: [0x7e,0x00,0xc3,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0xc3,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_le_i32_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0xc3,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0xc3,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_le_i32_e64 0.5, m0               ; encoding: [0x7e,0x00,0xc3,0xd4,0xf0,0xfa,0x00,0x00]
+0x7e,0x00,0xc3,0xd4,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_cmpx_le_i32_e64 src_scc, vcc_lo       ; encoding: [0x7e,0x00,0xc3,0xd4,0xfd,0xd4,0x00,0x00]
+0x7e,0x00,0xc3,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmpx_le_i32_e64 0xaf123456, vcc_hi    ; encoding: [0x7e,0x00,0xc3,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xc3,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_le_i64_e64 v[1:2], v[2:3]        ; encoding: [0x7e,0x00,0xd3,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xd3,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_le_i64_e64 v[254:255], v[254:255] ; encoding: [0x7e,0x00,0xd3,0xd4,0xfe,0xfd,0x03,0x00]
+0x7e,0x00,0xd3,0xd4,0xfe,0xfd,0x03,0x00
+
+# GFX12: v_cmpx_le_i64_e64 s[2:3], s[4:5]        ; encoding: [0x7e,0x00,0xd3,0xd4,0x02,0x08,0x00,0x00]
+0x7e,0x00,0xd3,0xd4,0x02,0x08,0x00,0x00
+
+# GFX12: v_cmpx_le_i64_e64 s[104:105], s[104:105] ; encoding: [0x7e,0x00,0xd3,0xd4,0x68,0xd0,0x00,0x00]
+0x7e,0x00,0xd3,0xd4,0x68,0xd0,0x00,0x00
+
+# GFX12: v_cmpx_le_i64_e64 vcc, ttmp[14:15]      ; encoding: [0x7e,0x00,0xd3,0xd4,0x6a,0xf4,0x00,0x00]
+0x7e,0x00,0xd3,0xd4,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_cmpx_le_i64_e64 ttmp[14:15], 0xaf123456 ; encoding: [0x7e,0x00,0xd3,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xd3,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_le_i64_e64 exec, src_scc         ; encoding: [0x7e,0x00,0xd3,0xd4,0x7e,0xfa,0x01,0x00]
+0x7e,0x00,0xd3,0xd4,0x7e,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_le_i64_e64 null, 0.5             ; encoding: [0x7e,0x00,0xd3,0xd4,0x7c,0xe0,0x01,0x00]
+0x7e,0x00,0xd3,0xd4,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_le_i64_e64 -1, -1                ; encoding: [0x7e,0x00,0xd3,0xd4,0xc1,0x82,0x01,0x00]
+0x7e,0x00,0xd3,0xd4,0xc1,0x82,0x01,0x00
+
+# GFX12: v_cmpx_le_i64_e64 0.5, null             ; encoding: [0x7e,0x00,0xd3,0xd4,0xf0,0xf8,0x00,0x00]
+0x7e,0x00,0xd3,0xd4,0xf0,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_le_i64_e64 src_scc, exec         ; encoding: [0x7e,0x00,0xd3,0xd4,0xfd,0xfc,0x00,0x00]
+0x7e,0x00,0xd3,0xd4,0xfd,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_le_i64_e64 0xaf123456, vcc       ; encoding: [0x7e,0x00,0xd3,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xd3,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_le_u16_e64 v1, v2                ; encoding: [0x7e,0x00,0xbb,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xbb,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_le_u16_e64 v255, v255            ; encoding: [0x7e,0x00,0xbb,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0xbb,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_le_u16_e64 s1, s2                ; encoding: [0x7e,0x00,0xbb,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0xbb,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_le_u16_e64 s105, s105            ; encoding: [0x7e,0x00,0xbb,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0xbb,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_le_u16_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0xbb,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0xbb,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_le_u16_e64 vcc_hi, 0xfe0b        ; encoding: [0x7e,0x00,0xbb,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0xbb,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_le_u16_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0xbb,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0xbb,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_le_u16_e64 m0, 0x3800
+0x7e,0x00,0xbb,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_le_u16_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0xbb,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0xbb,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_le_u16_e64 exec_hi, null         ; encoding: [0x7e,0x00,0xbb,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x00,0xbb,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_le_u16_e64 null, exec_lo         ; encoding: [0x7e,0x00,0xbb,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0xbb,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_le_u16_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0xbb,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0xbb,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_le_u16_e64 0x3800, m0
+0x7e,0x00,0xbb,0xd4,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_cmpx_le_u16_e64 src_scc, vcc_lo       ; encoding: [0x7e,0x00,0xbb,0xd4,0xfd,0xd4,0x00,0x00]
+0x7e,0x00,0xbb,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmpx_le_u16_e64 0xfe0b, vcc_hi        ; encoding: [0x7e,0x00,0xbb,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0xbb,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_le_u32_e64 v1, v2                ; encoding: [0x7e,0x00,0xcb,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xcb,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_le_u32_e64 v255, v255            ; encoding: [0x7e,0x00,0xcb,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0xcb,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_le_u32_e64 s1, s2                ; encoding: [0x7e,0x00,0xcb,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0xcb,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_le_u32_e64 s105, s105            ; encoding: [0x7e,0x00,0xcb,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0xcb,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_le_u32_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0xcb,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0xcb,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_le_u32_e64 vcc_hi, 0xaf123456    ; encoding: [0x7e,0x00,0xcb,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xcb,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_le_u32_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0xcb,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0xcb,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_le_u32_e64 m0, 0.5               ; encoding: [0x7e,0x00,0xcb,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0xcb,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_le_u32_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0xcb,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0xcb,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_le_u32_e64 exec_hi, null         ; encoding: [0x7e,0x00,0xcb,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x00,0xcb,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_le_u32_e64 null, exec_lo         ; encoding: [0x7e,0x00,0xcb,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0xcb,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_le_u32_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0xcb,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0xcb,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_le_u32_e64 0.5, m0               ; encoding: [0x7e,0x00,0xcb,0xd4,0xf0,0xfa,0x00,0x00]
+0x7e,0x00,0xcb,0xd4,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_cmpx_le_u32_e64 src_scc, vcc_lo       ; encoding: [0x7e,0x00,0xcb,0xd4,0xfd,0xd4,0x00,0x00]
+0x7e,0x00,0xcb,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmpx_le_u32_e64 0xaf123456, vcc_hi    ; encoding: [0x7e,0x00,0xcb,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xcb,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_le_u64_e64 v[1:2], v[2:3]        ; encoding: [0x7e,0x00,0xdb,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xdb,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_le_u64_e64 v[254:255], v[254:255] ; encoding: [0x7e,0x00,0xdb,0xd4,0xfe,0xfd,0x03,0x00]
+0x7e,0x00,0xdb,0xd4,0xfe,0xfd,0x03,0x00
+
+# GFX12: v_cmpx_le_u64_e64 s[2:3], s[4:5]        ; encoding: [0x7e,0x00,0xdb,0xd4,0x02,0x08,0x00,0x00]
+0x7e,0x00,0xdb,0xd4,0x02,0x08,0x00,0x00
+
+# GFX12: v_cmpx_le_u64_e64 s[104:105], s[104:105] ; encoding: [0x7e,0x00,0xdb,0xd4,0x68,0xd0,0x00,0x00]
+0x7e,0x00,0xdb,0xd4,0x68,0xd0,0x00,0x00
+
+# GFX12: v_cmpx_le_u64_e64 vcc, ttmp[14:15]      ; encoding: [0x7e,0x00,0xdb,0xd4,0x6a,0xf4,0x00,0x00]
+0x7e,0x00,0xdb,0xd4,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_cmpx_le_u64_e64 ttmp[14:15], 0xaf123456 ; encoding: [0x7e,0x00,0xdb,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xdb,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_le_u64_e64 exec, src_scc         ; encoding: [0x7e,0x00,0xdb,0xd4,0x7e,0xfa,0x01,0x00]
+0x7e,0x00,0xdb,0xd4,0x7e,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_le_u64_e64 null, 0.5             ; encoding: [0x7e,0x00,0xdb,0xd4,0x7c,0xe0,0x01,0x00]
+0x7e,0x00,0xdb,0xd4,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_le_u64_e64 -1, -1                ; encoding: [0x7e,0x00,0xdb,0xd4,0xc1,0x82,0x01,0x00]
+0x7e,0x00,0xdb,0xd4,0xc1,0x82,0x01,0x00
+
+# GFX12: v_cmpx_le_u64_e64 0.5, null             ; encoding: [0x7e,0x00,0xdb,0xd4,0xf0,0xf8,0x00,0x00]
+0x7e,0x00,0xdb,0xd4,0xf0,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_le_u64_e64 src_scc, exec         ; encoding: [0x7e,0x00,0xdb,0xd4,0xfd,0xfc,0x00,0x00]
+0x7e,0x00,0xdb,0xd4,0xfd,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_le_u64_e64 0xaf123456, vcc       ; encoding: [0x7e,0x00,0xdb,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xdb,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_lg_f16_e64 v1, v2                ; encoding: [0x7e,0x00,0x85,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0x85,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_lg_f16_e64 v255, v255            ; encoding: [0x7e,0x00,0x85,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0x85,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_lg_f16_e64 s1, s2                ; encoding: [0x7e,0x00,0x85,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0x85,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_lg_f16_e64 s105, s105            ; encoding: [0x7e,0x00,0x85,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0x85,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_lg_f16_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0x85,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0x85,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_lg_f16_e64 vcc_hi, 0xfe0b        ; encoding: [0x7e,0x00,0x85,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0x85,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_lg_f16_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0x85,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0x85,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_lg_f16_e64 m0, 0.5               ; encoding: [0x7e,0x00,0x85,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0x85,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_lg_f16_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0x85,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0x85,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_lg_f16_e64 |exec_hi|, null       ; encoding: [0x7e,0x01,0x85,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x01,0x85,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_lg_f16_e64 null, exec_lo         ; encoding: [0x7e,0x00,0x85,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0x85,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_lg_f16_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0x85,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0x85,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_lg_f16_e64 0.5, -m0              ; encoding: [0x7e,0x00,0x85,0xd4,0xf0,0xfa,0x00,0x40]
+0x7e,0x00,0x85,0xd4,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cmpx_lg_f16_e64 -src_scc, |vcc_lo|    ; encoding: [0x7e,0x02,0x85,0xd4,0xfd,0xd4,0x00,0x20]
+0x7e,0x02,0x85,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmpx_lg_f16_e64 -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7e,0x83,0x85,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x7e,0x83,0x85,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_lg_f32_e64 v1, v2                ; encoding: [0x7e,0x00,0x95,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0x95,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_lg_f32_e64 v255, v255            ; encoding: [0x7e,0x00,0x95,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0x95,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_lg_f32_e64 s1, s2                ; encoding: [0x7e,0x00,0x95,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0x95,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_lg_f32_e64 s105, s105            ; encoding: [0x7e,0x00,0x95,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0x95,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_lg_f32_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0x95,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0x95,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_lg_f32_e64 vcc_hi, 0xaf123456    ; encoding: [0x7e,0x00,0x95,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0x95,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_lg_f32_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0x95,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0x95,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_lg_f32_e64 m0, 0.5               ; encoding: [0x7e,0x00,0x95,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0x95,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_lg_f32_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0x95,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0x95,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_lg_f32_e64 |exec_hi|, null       ; encoding: [0x7e,0x01,0x95,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x01,0x95,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_lg_f32_e64 null, exec_lo         ; encoding: [0x7e,0x00,0x95,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0x95,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_lg_f32_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0x95,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0x95,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_lg_f32_e64 0.5, -m0              ; encoding: [0x7e,0x00,0x95,0xd4,0xf0,0xfa,0x00,0x40]
+0x7e,0x00,0x95,0xd4,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cmpx_lg_f32_e64 -src_scc, |vcc_lo|    ; encoding: [0x7e,0x02,0x95,0xd4,0xfd,0xd4,0x00,0x20]
+0x7e,0x02,0x95,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmpx_lg_f32_e64 -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0x7e,0x83,0x95,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0x7e,0x83,0x95,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_lg_f64_e64 v[1:2], v[2:3]        ; encoding: [0x7e,0x00,0xa5,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xa5,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_lg_f64_e64 v[254:255], v[254:255] ; encoding: [0x7e,0x00,0xa5,0xd4,0xfe,0xfd,0x03,0x00]
+0x7e,0x00,0xa5,0xd4,0xfe,0xfd,0x03,0x00
+
+# GFX12: v_cmpx_lg_f64_e64 s[2:3], s[4:5]        ; encoding: [0x7e,0x00,0xa5,0xd4,0x02,0x08,0x00,0x00]
+0x7e,0x00,0xa5,0xd4,0x02,0x08,0x00,0x00
+
+# GFX12: v_cmpx_lg_f64_e64 s[104:105], s[104:105] ; encoding: [0x7e,0x00,0xa5,0xd4,0x68,0xd0,0x00,0x00]
+0x7e,0x00,0xa5,0xd4,0x68,0xd0,0x00,0x00
+
+# GFX12: v_cmpx_lg_f64_e64 vcc, ttmp[14:15]      ; encoding: [0x7e,0x00,0xa5,0xd4,0x6a,0xf4,0x00,0x00]
+0x7e,0x00,0xa5,0xd4,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_cmpx_lg_f64_e64 ttmp[14:15], 0xaf123456 ; encoding: [0x7e,0x00,0xa5,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xa5,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_lg_f64_e64 -|exec|, src_scc      ; encoding: [0x7e,0x01,0xa5,0xd4,0x7e,0xfa,0x01,0x20]
+0x7e,0x01,0xa5,0xd4,0x7e,0xfa,0x01,0x20
+
+# GFX12: v_cmpx_lg_f64_e64 null, 0.5             ; encoding: [0x7e,0x00,0xa5,0xd4,0x7c,0xe0,0x01,0x00]
+0x7e,0x00,0xa5,0xd4,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_lg_f64_e64 -1, -1                ; encoding: [0x7e,0x00,0xa5,0xd4,0xc1,0x82,0x01,0x00]
+0x7e,0x00,0xa5,0xd4,0xc1,0x82,0x01,0x00
+
+# GFX12: v_cmpx_lg_f64_e64 0.5, null             ; encoding: [0x7e,0x00,0xa5,0xd4,0xf0,0xf8,0x00,0x00]
+0x7e,0x00,0xa5,0xd4,0xf0,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_lg_f64_e64 -|src_scc|, -|exec|   ; encoding: [0x7e,0x03,0xa5,0xd4,0xfd,0xfc,0x00,0x60]
+0x7e,0x03,0xa5,0xd4,0xfd,0xfc,0x00,0x60
+
+# GFX12: v_cmpx_lg_f64_e64 0xaf123456, -|vcc| clamp ; encoding: [0x7e,0x82,0xa5,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+0x7e,0x82,0xa5,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_lt_f16_e64 v1, v2                ; encoding: [0x7e,0x00,0x81,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0x81,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_lt_f16_e64 v255, v255            ; encoding: [0x7e,0x00,0x81,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0x81,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_lt_f16_e64 s1, s2                ; encoding: [0x7e,0x00,0x81,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0x81,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_lt_f16_e64 s105, s105            ; encoding: [0x7e,0x00,0x81,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0x81,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_lt_f16_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0x81,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0x81,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_lt_f16_e64 vcc_hi, 0xfe0b        ; encoding: [0x7e,0x00,0x81,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0x81,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_lt_f16_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0x81,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0x81,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_lt_f16_e64 m0, 0.5               ; encoding: [0x7e,0x00,0x81,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0x81,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_lt_f16_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0x81,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0x81,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_lt_f16_e64 |exec_hi|, null       ; encoding: [0x7e,0x01,0x81,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x01,0x81,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_lt_f16_e64 null, exec_lo         ; encoding: [0x7e,0x00,0x81,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0x81,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_lt_f16_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0x81,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0x81,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_lt_f16_e64 0.5, -m0              ; encoding: [0x7e,0x00,0x81,0xd4,0xf0,0xfa,0x00,0x40]
+0x7e,0x00,0x81,0xd4,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cmpx_lt_f16_e64 -src_scc, |vcc_lo|    ; encoding: [0x7e,0x02,0x81,0xd4,0xfd,0xd4,0x00,0x20]
+0x7e,0x02,0x81,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmpx_lt_f16_e64 -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7e,0x83,0x81,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x7e,0x83,0x81,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_lt_f32_e64 v1, v2                ; encoding: [0x7e,0x00,0x91,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0x91,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_lt_f32_e64 v255, v255            ; encoding: [0x7e,0x00,0x91,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0x91,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_lt_f32_e64 s1, s2                ; encoding: [0x7e,0x00,0x91,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0x91,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_lt_f32_e64 s105, s105            ; encoding: [0x7e,0x00,0x91,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0x91,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_lt_f32_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0x91,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0x91,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_lt_f32_e64 vcc_hi, 0xaf123456    ; encoding: [0x7e,0x00,0x91,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0x91,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_lt_f32_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0x91,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0x91,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_lt_f32_e64 m0, 0.5               ; encoding: [0x7e,0x00,0x91,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0x91,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_lt_f32_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0x91,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0x91,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_lt_f32_e64 |exec_hi|, null       ; encoding: [0x7e,0x01,0x91,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x01,0x91,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_lt_f32_e64 null, exec_lo         ; encoding: [0x7e,0x00,0x91,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0x91,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_lt_f32_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0x91,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0x91,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_lt_f32_e64 0.5, -m0              ; encoding: [0x7e,0x00,0x91,0xd4,0xf0,0xfa,0x00,0x40]
+0x7e,0x00,0x91,0xd4,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cmpx_lt_f32_e64 -src_scc, |vcc_lo|    ; encoding: [0x7e,0x02,0x91,0xd4,0xfd,0xd4,0x00,0x20]
+0x7e,0x02,0x91,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmpx_lt_f32_e64 -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0x7e,0x83,0x91,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0x7e,0x83,0x91,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_lt_f64_e64 v[1:2], v[2:3]        ; encoding: [0x7e,0x00,0xa1,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xa1,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_lt_f64_e64 v[254:255], v[254:255] ; encoding: [0x7e,0x00,0xa1,0xd4,0xfe,0xfd,0x03,0x00]
+0x7e,0x00,0xa1,0xd4,0xfe,0xfd,0x03,0x00
+
+# GFX12: v_cmpx_lt_f64_e64 s[2:3], s[4:5]        ; encoding: [0x7e,0x00,0xa1,0xd4,0x02,0x08,0x00,0x00]
+0x7e,0x00,0xa1,0xd4,0x02,0x08,0x00,0x00
+
+# GFX12: v_cmpx_lt_f64_e64 s[104:105], s[104:105] ; encoding: [0x7e,0x00,0xa1,0xd4,0x68,0xd0,0x00,0x00]
+0x7e,0x00,0xa1,0xd4,0x68,0xd0,0x00,0x00
+
+# GFX12: v_cmpx_lt_f64_e64 vcc, ttmp[14:15]      ; encoding: [0x7e,0x00,0xa1,0xd4,0x6a,0xf4,0x00,0x00]
+0x7e,0x00,0xa1,0xd4,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_cmpx_lt_f64_e64 ttmp[14:15], 0xaf123456 ; encoding: [0x7e,0x00,0xa1,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xa1,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_lt_f64_e64 -|exec|, src_scc      ; encoding: [0x7e,0x01,0xa1,0xd4,0x7e,0xfa,0x01,0x20]
+0x7e,0x01,0xa1,0xd4,0x7e,0xfa,0x01,0x20
+
+# GFX12: v_cmpx_lt_f64_e64 null, 0.5             ; encoding: [0x7e,0x00,0xa1,0xd4,0x7c,0xe0,0x01,0x00]
+0x7e,0x00,0xa1,0xd4,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_lt_f64_e64 -1, -1                ; encoding: [0x7e,0x00,0xa1,0xd4,0xc1,0x82,0x01,0x00]
+0x7e,0x00,0xa1,0xd4,0xc1,0x82,0x01,0x00
+
+# GFX12: v_cmpx_lt_f64_e64 0.5, null             ; encoding: [0x7e,0x00,0xa1,0xd4,0xf0,0xf8,0x00,0x00]
+0x7e,0x00,0xa1,0xd4,0xf0,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_lt_f64_e64 -|src_scc|, -|exec|   ; encoding: [0x7e,0x03,0xa1,0xd4,0xfd,0xfc,0x00,0x60]
+0x7e,0x03,0xa1,0xd4,0xfd,0xfc,0x00,0x60
+
+# GFX12: v_cmpx_lt_f64_e64 0xaf123456, -|vcc| clamp ; encoding: [0x7e,0x82,0xa1,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+0x7e,0x82,0xa1,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_lt_i16_e64 v1, v2                ; encoding: [0x7e,0x00,0xb1,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xb1,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_lt_i16_e64 v255, v255            ; encoding: [0x7e,0x00,0xb1,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0xb1,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_lt_i16_e64 s1, s2                ; encoding: [0x7e,0x00,0xb1,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0xb1,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_lt_i16_e64 s105, s105            ; encoding: [0x7e,0x00,0xb1,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0xb1,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_lt_i16_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0xb1,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0xb1,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_lt_i16_e64 vcc_hi, 0xfe0b        ; encoding: [0x7e,0x00,0xb1,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0xb1,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_lt_i16_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0xb1,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0xb1,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_lt_i16_e64 m0, 0x3800
+0x7e,0x00,0xb1,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_lt_i16_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0xb1,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0xb1,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_lt_i16_e64 exec_hi, null         ; encoding: [0x7e,0x00,0xb1,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x00,0xb1,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_lt_i16_e64 null, exec_lo         ; encoding: [0x7e,0x00,0xb1,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0xb1,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_lt_i16_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0xb1,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0xb1,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_lt_i16_e64 0x3800, m0
+0x7e,0x00,0xb1,0xd4,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_cmpx_lt_i16_e64 src_scc, vcc_lo       ; encoding: [0x7e,0x00,0xb1,0xd4,0xfd,0xd4,0x00,0x00]
+0x7e,0x00,0xb1,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmpx_lt_i16_e64 0xfe0b, vcc_hi        ; encoding: [0x7e,0x00,0xb1,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0xb1,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_lt_i32_e64 v1, v2                ; encoding: [0x7e,0x00,0xc1,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xc1,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_lt_i32_e64 v255, v255            ; encoding: [0x7e,0x00,0xc1,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0xc1,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_lt_i32_e64 s1, s2                ; encoding: [0x7e,0x00,0xc1,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0xc1,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_lt_i32_e64 s105, s105            ; encoding: [0x7e,0x00,0xc1,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0xc1,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_lt_i32_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0xc1,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0xc1,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_lt_i32_e64 vcc_hi, 0xaf123456    ; encoding: [0x7e,0x00,0xc1,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xc1,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_lt_i32_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0xc1,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0xc1,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_lt_i32_e64 m0, 0.5               ; encoding: [0x7e,0x00,0xc1,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0xc1,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_lt_i32_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0xc1,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0xc1,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_lt_i32_e64 exec_hi, null         ; encoding: [0x7e,0x00,0xc1,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x00,0xc1,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_lt_i32_e64 null, exec_lo         ; encoding: [0x7e,0x00,0xc1,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0xc1,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_lt_i32_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0xc1,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0xc1,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_lt_i32_e64 0.5, m0               ; encoding: [0x7e,0x00,0xc1,0xd4,0xf0,0xfa,0x00,0x00]
+0x7e,0x00,0xc1,0xd4,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_cmpx_lt_i32_e64 src_scc, vcc_lo       ; encoding: [0x7e,0x00,0xc1,0xd4,0xfd,0xd4,0x00,0x00]
+0x7e,0x00,0xc1,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmpx_lt_i32_e64 0xaf123456, vcc_hi    ; encoding: [0x7e,0x00,0xc1,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xc1,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_lt_i64_e64 v[1:2], v[2:3]        ; encoding: [0x7e,0x00,0xd1,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xd1,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_lt_i64_e64 v[254:255], v[254:255] ; encoding: [0x7e,0x00,0xd1,0xd4,0xfe,0xfd,0x03,0x00]
+0x7e,0x00,0xd1,0xd4,0xfe,0xfd,0x03,0x00
+
+# GFX12: v_cmpx_lt_i64_e64 s[2:3], s[4:5]        ; encoding: [0x7e,0x00,0xd1,0xd4,0x02,0x08,0x00,0x00]
+0x7e,0x00,0xd1,0xd4,0x02,0x08,0x00,0x00
+
+# GFX12: v_cmpx_lt_i64_e64 s[104:105], s[104:105] ; encoding: [0x7e,0x00,0xd1,0xd4,0x68,0xd0,0x00,0x00]
+0x7e,0x00,0xd1,0xd4,0x68,0xd0,0x00,0x00
+
+# GFX12: v_cmpx_lt_i64_e64 vcc, ttmp[14:15]      ; encoding: [0x7e,0x00,0xd1,0xd4,0x6a,0xf4,0x00,0x00]
+0x7e,0x00,0xd1,0xd4,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_cmpx_lt_i64_e64 ttmp[14:15], 0xaf123456 ; encoding: [0x7e,0x00,0xd1,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xd1,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_lt_i64_e64 exec, src_scc         ; encoding: [0x7e,0x00,0xd1,0xd4,0x7e,0xfa,0x01,0x00]
+0x7e,0x00,0xd1,0xd4,0x7e,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_lt_i64_e64 null, 0.5             ; encoding: [0x7e,0x00,0xd1,0xd4,0x7c,0xe0,0x01,0x00]
+0x7e,0x00,0xd1,0xd4,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_lt_i64_e64 -1, -1                ; encoding: [0x7e,0x00,0xd1,0xd4,0xc1,0x82,0x01,0x00]
+0x7e,0x00,0xd1,0xd4,0xc1,0x82,0x01,0x00
+
+# GFX12: v_cmpx_lt_i64_e64 0.5, null             ; encoding: [0x7e,0x00,0xd1,0xd4,0xf0,0xf8,0x00,0x00]
+0x7e,0x00,0xd1,0xd4,0xf0,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_lt_i64_e64 src_scc, exec         ; encoding: [0x7e,0x00,0xd1,0xd4,0xfd,0xfc,0x00,0x00]
+0x7e,0x00,0xd1,0xd4,0xfd,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_lt_i64_e64 0xaf123456, vcc       ; encoding: [0x7e,0x00,0xd1,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xd1,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_lt_u16_e64 v1, v2                ; encoding: [0x7e,0x00,0xb9,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xb9,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_lt_u16_e64 v255, v255            ; encoding: [0x7e,0x00,0xb9,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0xb9,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_lt_u16_e64 s1, s2                ; encoding: [0x7e,0x00,0xb9,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0xb9,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_lt_u16_e64 s105, s105            ; encoding: [0x7e,0x00,0xb9,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0xb9,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_lt_u16_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0xb9,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0xb9,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_lt_u16_e64 vcc_hi, 0xfe0b        ; encoding: [0x7e,0x00,0xb9,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0xb9,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_lt_u16_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0xb9,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0xb9,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_lt_u16_e64 m0, 0x3800
+0x7e,0x00,0xb9,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_lt_u16_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0xb9,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0xb9,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_lt_u16_e64 exec_hi, null         ; encoding: [0x7e,0x00,0xb9,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x00,0xb9,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_lt_u16_e64 null, exec_lo         ; encoding: [0x7e,0x00,0xb9,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0xb9,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_lt_u16_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0xb9,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0xb9,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_lt_u16_e64 0x3800, m0
+0x7e,0x00,0xb9,0xd4,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_cmpx_lt_u16_e64 src_scc, vcc_lo       ; encoding: [0x7e,0x00,0xb9,0xd4,0xfd,0xd4,0x00,0x00]
+0x7e,0x00,0xb9,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmpx_lt_u16_e64 0xfe0b, vcc_hi        ; encoding: [0x7e,0x00,0xb9,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0xb9,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_lt_u32_e64 v1, v2                ; encoding: [0x7e,0x00,0xc9,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xc9,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_lt_u32_e64 v255, v255            ; encoding: [0x7e,0x00,0xc9,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0xc9,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_lt_u32_e64 s1, s2                ; encoding: [0x7e,0x00,0xc9,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0xc9,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_lt_u32_e64 s105, s105            ; encoding: [0x7e,0x00,0xc9,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0xc9,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_lt_u32_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0xc9,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0xc9,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_lt_u32_e64 vcc_hi, 0xaf123456    ; encoding: [0x7e,0x00,0xc9,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xc9,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_lt_u32_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0xc9,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0xc9,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_lt_u32_e64 m0, 0.5               ; encoding: [0x7e,0x00,0xc9,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0xc9,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_lt_u32_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0xc9,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0xc9,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_lt_u32_e64 exec_hi, null         ; encoding: [0x7e,0x00,0xc9,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x00,0xc9,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_lt_u32_e64 null, exec_lo         ; encoding: [0x7e,0x00,0xc9,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0xc9,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_lt_u32_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0xc9,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0xc9,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_lt_u32_e64 0.5, m0               ; encoding: [0x7e,0x00,0xc9,0xd4,0xf0,0xfa,0x00,0x00]
+0x7e,0x00,0xc9,0xd4,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_cmpx_lt_u32_e64 src_scc, vcc_lo       ; encoding: [0x7e,0x00,0xc9,0xd4,0xfd,0xd4,0x00,0x00]
+0x7e,0x00,0xc9,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmpx_lt_u32_e64 0xaf123456, vcc_hi    ; encoding: [0x7e,0x00,0xc9,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xc9,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_lt_u64_e64 v[1:2], v[2:3]        ; encoding: [0x7e,0x00,0xd9,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xd9,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_lt_u64_e64 v[254:255], v[254:255] ; encoding: [0x7e,0x00,0xd9,0xd4,0xfe,0xfd,0x03,0x00]
+0x7e,0x00,0xd9,0xd4,0xfe,0xfd,0x03,0x00
+
+# GFX12: v_cmpx_lt_u64_e64 s[2:3], s[4:5]        ; encoding: [0x7e,0x00,0xd9,0xd4,0x02,0x08,0x00,0x00]
+0x7e,0x00,0xd9,0xd4,0x02,0x08,0x00,0x00
+
+# GFX12: v_cmpx_lt_u64_e64 s[104:105], s[104:105] ; encoding: [0x7e,0x00,0xd9,0xd4,0x68,0xd0,0x00,0x00]
+0x7e,0x00,0xd9,0xd4,0x68,0xd0,0x00,0x00
+
+# GFX12: v_cmpx_lt_u64_e64 vcc, ttmp[14:15]      ; encoding: [0x7e,0x00,0xd9,0xd4,0x6a,0xf4,0x00,0x00]
+0x7e,0x00,0xd9,0xd4,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_cmpx_lt_u64_e64 ttmp[14:15], 0xaf123456 ; encoding: [0x7e,0x00,0xd9,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xd9,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_lt_u64_e64 exec, src_scc         ; encoding: [0x7e,0x00,0xd9,0xd4,0x7e,0xfa,0x01,0x00]
+0x7e,0x00,0xd9,0xd4,0x7e,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_lt_u64_e64 null, 0.5             ; encoding: [0x7e,0x00,0xd9,0xd4,0x7c,0xe0,0x01,0x00]
+0x7e,0x00,0xd9,0xd4,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_lt_u64_e64 -1, -1                ; encoding: [0x7e,0x00,0xd9,0xd4,0xc1,0x82,0x01,0x00]
+0x7e,0x00,0xd9,0xd4,0xc1,0x82,0x01,0x00
+
+# GFX12: v_cmpx_lt_u64_e64 0.5, null             ; encoding: [0x7e,0x00,0xd9,0xd4,0xf0,0xf8,0x00,0x00]
+0x7e,0x00,0xd9,0xd4,0xf0,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_lt_u64_e64 src_scc, exec         ; encoding: [0x7e,0x00,0xd9,0xd4,0xfd,0xfc,0x00,0x00]
+0x7e,0x00,0xd9,0xd4,0xfd,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_lt_u64_e64 0xaf123456, vcc       ; encoding: [0x7e,0x00,0xd9,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xd9,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ne_i16_e64 v1, v2                ; encoding: [0x7e,0x00,0xb5,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xb5,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_ne_i16_e64 v255, v255            ; encoding: [0x7e,0x00,0xb5,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0xb5,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_ne_i16_e64 s1, s2                ; encoding: [0x7e,0x00,0xb5,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0xb5,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_ne_i16_e64 s105, s105            ; encoding: [0x7e,0x00,0xb5,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0xb5,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_ne_i16_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0xb5,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0xb5,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_ne_i16_e64 vcc_hi, 0xfe0b        ; encoding: [0x7e,0x00,0xb5,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0xb5,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ne_i16_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0xb5,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0xb5,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_ne_i16_e64 m0, 0x3800
+0x7e,0x00,0xb5,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_ne_i16_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0xb5,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0xb5,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_ne_i16_e64 exec_hi, null         ; encoding: [0x7e,0x00,0xb5,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x00,0xb5,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_ne_i16_e64 null, exec_lo         ; encoding: [0x7e,0x00,0xb5,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0xb5,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_ne_i16_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0xb5,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0xb5,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ne_i16_e64 0x3800, m0
+0x7e,0x00,0xb5,0xd4,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_cmpx_ne_i16_e64 src_scc, vcc_lo       ; encoding: [0x7e,0x00,0xb5,0xd4,0xfd,0xd4,0x00,0x00]
+0x7e,0x00,0xb5,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmpx_ne_i16_e64 0xfe0b, vcc_hi        ; encoding: [0x7e,0x00,0xb5,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0xb5,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ne_i32_e64 v1, v2                ; encoding: [0x7e,0x00,0xc5,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xc5,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_ne_i32_e64 v255, v255            ; encoding: [0x7e,0x00,0xc5,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0xc5,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_ne_i32_e64 s1, s2                ; encoding: [0x7e,0x00,0xc5,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0xc5,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_ne_i32_e64 s105, s105            ; encoding: [0x7e,0x00,0xc5,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0xc5,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_ne_i32_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0xc5,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0xc5,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_ne_i32_e64 vcc_hi, 0xaf123456    ; encoding: [0x7e,0x00,0xc5,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xc5,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ne_i32_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0xc5,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0xc5,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_ne_i32_e64 m0, 0.5               ; encoding: [0x7e,0x00,0xc5,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0xc5,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_ne_i32_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0xc5,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0xc5,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_ne_i32_e64 exec_hi, null         ; encoding: [0x7e,0x00,0xc5,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x00,0xc5,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_ne_i32_e64 null, exec_lo         ; encoding: [0x7e,0x00,0xc5,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0xc5,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_ne_i32_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0xc5,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0xc5,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ne_i32_e64 0.5, m0               ; encoding: [0x7e,0x00,0xc5,0xd4,0xf0,0xfa,0x00,0x00]
+0x7e,0x00,0xc5,0xd4,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_cmpx_ne_i32_e64 src_scc, vcc_lo       ; encoding: [0x7e,0x00,0xc5,0xd4,0xfd,0xd4,0x00,0x00]
+0x7e,0x00,0xc5,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmpx_ne_i32_e64 0xaf123456, vcc_hi    ; encoding: [0x7e,0x00,0xc5,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xc5,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ne_i64_e64 v[1:2], v[2:3]        ; encoding: [0x7e,0x00,0xd5,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xd5,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_ne_i64_e64 v[254:255], v[254:255] ; encoding: [0x7e,0x00,0xd5,0xd4,0xfe,0xfd,0x03,0x00]
+0x7e,0x00,0xd5,0xd4,0xfe,0xfd,0x03,0x00
+
+# GFX12: v_cmpx_ne_i64_e64 s[2:3], s[4:5]        ; encoding: [0x7e,0x00,0xd5,0xd4,0x02,0x08,0x00,0x00]
+0x7e,0x00,0xd5,0xd4,0x02,0x08,0x00,0x00
+
+# GFX12: v_cmpx_ne_i64_e64 s[104:105], s[104:105] ; encoding: [0x7e,0x00,0xd5,0xd4,0x68,0xd0,0x00,0x00]
+0x7e,0x00,0xd5,0xd4,0x68,0xd0,0x00,0x00
+
+# GFX12: v_cmpx_ne_i64_e64 vcc, ttmp[14:15]      ; encoding: [0x7e,0x00,0xd5,0xd4,0x6a,0xf4,0x00,0x00]
+0x7e,0x00,0xd5,0xd4,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_cmpx_ne_i64_e64 ttmp[14:15], 0xaf123456 ; encoding: [0x7e,0x00,0xd5,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xd5,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ne_i64_e64 exec, src_scc         ; encoding: [0x7e,0x00,0xd5,0xd4,0x7e,0xfa,0x01,0x00]
+0x7e,0x00,0xd5,0xd4,0x7e,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_ne_i64_e64 null, 0.5             ; encoding: [0x7e,0x00,0xd5,0xd4,0x7c,0xe0,0x01,0x00]
+0x7e,0x00,0xd5,0xd4,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_ne_i64_e64 -1, -1                ; encoding: [0x7e,0x00,0xd5,0xd4,0xc1,0x82,0x01,0x00]
+0x7e,0x00,0xd5,0xd4,0xc1,0x82,0x01,0x00
+
+# GFX12: v_cmpx_ne_i64_e64 0.5, null             ; encoding: [0x7e,0x00,0xd5,0xd4,0xf0,0xf8,0x00,0x00]
+0x7e,0x00,0xd5,0xd4,0xf0,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_ne_i64_e64 src_scc, exec         ; encoding: [0x7e,0x00,0xd5,0xd4,0xfd,0xfc,0x00,0x00]
+0x7e,0x00,0xd5,0xd4,0xfd,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_ne_i64_e64 0xaf123456, vcc       ; encoding: [0x7e,0x00,0xd5,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xd5,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ne_u16_e64 v1, v2                ; encoding: [0x7e,0x00,0xbd,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xbd,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_ne_u16_e64 v255, v255            ; encoding: [0x7e,0x00,0xbd,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0xbd,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_ne_u16_e64 s1, s2                ; encoding: [0x7e,0x00,0xbd,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0xbd,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_ne_u16_e64 s105, s105            ; encoding: [0x7e,0x00,0xbd,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0xbd,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_ne_u16_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0xbd,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0xbd,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_ne_u16_e64 vcc_hi, 0xfe0b        ; encoding: [0x7e,0x00,0xbd,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0xbd,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ne_u16_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0xbd,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0xbd,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_ne_u16_e64 m0, 0x3800
+0x7e,0x00,0xbd,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_ne_u16_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0xbd,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0xbd,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_ne_u16_e64 exec_hi, null         ; encoding: [0x7e,0x00,0xbd,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x00,0xbd,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_ne_u16_e64 null, exec_lo         ; encoding: [0x7e,0x00,0xbd,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0xbd,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_ne_u16_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0xbd,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0xbd,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ne_u16_e64 0x3800, m0
+0x7e,0x00,0xbd,0xd4,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_cmpx_ne_u16_e64 src_scc, vcc_lo       ; encoding: [0x7e,0x00,0xbd,0xd4,0xfd,0xd4,0x00,0x00]
+0x7e,0x00,0xbd,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmpx_ne_u16_e64 0xfe0b, vcc_hi        ; encoding: [0x7e,0x00,0xbd,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0xbd,0xd4,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ne_u32_e64 v1, v2                ; encoding: [0x7e,0x00,0xcd,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xcd,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_ne_u32_e64 v255, v255            ; encoding: [0x7e,0x00,0xcd,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0xcd,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_ne_u32_e64 s1, s2                ; encoding: [0x7e,0x00,0xcd,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0xcd,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_ne_u32_e64 s105, s105            ; encoding: [0x7e,0x00,0xcd,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0xcd,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_ne_u32_e64 vcc_lo, ttmp15        ; encoding: [0x7e,0x00,0xcd,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0xcd,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_ne_u32_e64 vcc_hi, 0xaf123456    ; encoding: [0x7e,0x00,0xcd,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xcd,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ne_u32_e64 ttmp15, src_scc       ; encoding: [0x7e,0x00,0xcd,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0xcd,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_ne_u32_e64 m0, 0.5               ; encoding: [0x7e,0x00,0xcd,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0xcd,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_ne_u32_e64 exec_lo, -1           ; encoding: [0x7e,0x00,0xcd,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0xcd,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_ne_u32_e64 exec_hi, null         ; encoding: [0x7e,0x00,0xcd,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x00,0xcd,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_ne_u32_e64 null, exec_lo         ; encoding: [0x7e,0x00,0xcd,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0xcd,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_ne_u32_e64 -1, exec_hi           ; encoding: [0x7e,0x00,0xcd,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0xcd,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ne_u32_e64 0.5, m0               ; encoding: [0x7e,0x00,0xcd,0xd4,0xf0,0xfa,0x00,0x00]
+0x7e,0x00,0xcd,0xd4,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_cmpx_ne_u32_e64 src_scc, vcc_lo       ; encoding: [0x7e,0x00,0xcd,0xd4,0xfd,0xd4,0x00,0x00]
+0x7e,0x00,0xcd,0xd4,0xfd,0xd4,0x00,0x00
+
+# GFX12: v_cmpx_ne_u32_e64 0xaf123456, vcc_hi    ; encoding: [0x7e,0x00,0xcd,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xcd,0xd4,0xff,0xd6,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ne_u64_e64 v[1:2], v[2:3]        ; encoding: [0x7e,0x00,0xdd,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xdd,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_ne_u64_e64 v[254:255], v[254:255] ; encoding: [0x7e,0x00,0xdd,0xd4,0xfe,0xfd,0x03,0x00]
+0x7e,0x00,0xdd,0xd4,0xfe,0xfd,0x03,0x00
+
+# GFX12: v_cmpx_ne_u64_e64 s[2:3], s[4:5]        ; encoding: [0x7e,0x00,0xdd,0xd4,0x02,0x08,0x00,0x00]
+0x7e,0x00,0xdd,0xd4,0x02,0x08,0x00,0x00
+
+# GFX12: v_cmpx_ne_u64_e64 s[104:105], s[104:105] ; encoding: [0x7e,0x00,0xdd,0xd4,0x68,0xd0,0x00,0x00]
+0x7e,0x00,0xdd,0xd4,0x68,0xd0,0x00,0x00
+
+# GFX12: v_cmpx_ne_u64_e64 vcc, ttmp[14:15]      ; encoding: [0x7e,0x00,0xdd,0xd4,0x6a,0xf4,0x00,0x00]
+0x7e,0x00,0xdd,0xd4,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_cmpx_ne_u64_e64 ttmp[14:15], 0xaf123456 ; encoding: [0x7e,0x00,0xdd,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xdd,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ne_u64_e64 exec, src_scc         ; encoding: [0x7e,0x00,0xdd,0xd4,0x7e,0xfa,0x01,0x00]
+0x7e,0x00,0xdd,0xd4,0x7e,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_ne_u64_e64 null, 0.5             ; encoding: [0x7e,0x00,0xdd,0xd4,0x7c,0xe0,0x01,0x00]
+0x7e,0x00,0xdd,0xd4,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_ne_u64_e64 -1, -1                ; encoding: [0x7e,0x00,0xdd,0xd4,0xc1,0x82,0x01,0x00]
+0x7e,0x00,0xdd,0xd4,0xc1,0x82,0x01,0x00
+
+# GFX12: v_cmpx_ne_u64_e64 0.5, null             ; encoding: [0x7e,0x00,0xdd,0xd4,0xf0,0xf8,0x00,0x00]
+0x7e,0x00,0xdd,0xd4,0xf0,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_ne_u64_e64 src_scc, exec         ; encoding: [0x7e,0x00,0xdd,0xd4,0xfd,0xfc,0x00,0x00]
+0x7e,0x00,0xdd,0xd4,0xfd,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_ne_u64_e64 0xaf123456, vcc       ; encoding: [0x7e,0x00,0xdd,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xdd,0xd4,0xff,0xd4,0x00,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_neq_f16_e64 v1, v2               ; encoding: [0x7e,0x00,0x8d,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0x8d,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_neq_f16_e64 v255, v255           ; encoding: [0x7e,0x00,0x8d,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0x8d,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_neq_f16_e64 s1, s2               ; encoding: [0x7e,0x00,0x8d,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0x8d,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_neq_f16_e64 s105, s105           ; encoding: [0x7e,0x00,0x8d,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0x8d,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_neq_f16_e64 vcc_lo, ttmp15       ; encoding: [0x7e,0x00,0x8d,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0x8d,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_neq_f16_e64 vcc_hi, 0xfe0b       ; encoding: [0x7e,0x00,0x8d,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0x8d,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_neq_f16_e64 ttmp15, src_scc      ; encoding: [0x7e,0x00,0x8d,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0x8d,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_neq_f16_e64 m0, 0.5              ; encoding: [0x7e,0x00,0x8d,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0x8d,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_neq_f16_e64 exec_lo, -1          ; encoding: [0x7e,0x00,0x8d,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0x8d,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_neq_f16_e64 |exec_hi|, null      ; encoding: [0x7e,0x01,0x8d,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x01,0x8d,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_neq_f16_e64 null, exec_lo        ; encoding: [0x7e,0x00,0x8d,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0x8d,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_neq_f16_e64 -1, exec_hi          ; encoding: [0x7e,0x00,0x8d,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0x8d,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_neq_f16_e64 0.5, -m0             ; encoding: [0x7e,0x00,0x8d,0xd4,0xf0,0xfa,0x00,0x40]
+0x7e,0x00,0x8d,0xd4,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cmpx_neq_f16_e64 -src_scc, |vcc_lo|   ; encoding: [0x7e,0x02,0x8d,0xd4,0xfd,0xd4,0x00,0x20]
+0x7e,0x02,0x8d,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmpx_neq_f16_e64 -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7e,0x83,0x8d,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x7e,0x83,0x8d,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_neq_f32_e64 v1, v2               ; encoding: [0x7e,0x00,0x9d,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0x9d,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_neq_f32_e64 v255, v255           ; encoding: [0x7e,0x00,0x9d,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0x9d,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_neq_f32_e64 s1, s2               ; encoding: [0x7e,0x00,0x9d,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0x9d,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_neq_f32_e64 s105, s105           ; encoding: [0x7e,0x00,0x9d,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0x9d,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_neq_f32_e64 vcc_lo, ttmp15       ; encoding: [0x7e,0x00,0x9d,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0x9d,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_neq_f32_e64 vcc_hi, 0xaf123456   ; encoding: [0x7e,0x00,0x9d,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0x9d,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_neq_f32_e64 ttmp15, src_scc      ; encoding: [0x7e,0x00,0x9d,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0x9d,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_neq_f32_e64 m0, 0.5              ; encoding: [0x7e,0x00,0x9d,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0x9d,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_neq_f32_e64 exec_lo, -1          ; encoding: [0x7e,0x00,0x9d,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0x9d,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_neq_f32_e64 |exec_hi|, null      ; encoding: [0x7e,0x01,0x9d,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x01,0x9d,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_neq_f32_e64 null, exec_lo        ; encoding: [0x7e,0x00,0x9d,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0x9d,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_neq_f32_e64 -1, exec_hi          ; encoding: [0x7e,0x00,0x9d,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0x9d,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_neq_f32_e64 0.5, -m0             ; encoding: [0x7e,0x00,0x9d,0xd4,0xf0,0xfa,0x00,0x40]
+0x7e,0x00,0x9d,0xd4,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cmpx_neq_f32_e64 -src_scc, |vcc_lo|   ; encoding: [0x7e,0x02,0x9d,0xd4,0xfd,0xd4,0x00,0x20]
+0x7e,0x02,0x9d,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmpx_neq_f32_e64 -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0x7e,0x83,0x9d,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0x7e,0x83,0x9d,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_neq_f64_e64 v[1:2], v[2:3]       ; encoding: [0x7e,0x00,0xad,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xad,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_neq_f64_e64 v[254:255], v[254:255] ; encoding: [0x7e,0x00,0xad,0xd4,0xfe,0xfd,0x03,0x00]
+0x7e,0x00,0xad,0xd4,0xfe,0xfd,0x03,0x00
+
+# GFX12: v_cmpx_neq_f64_e64 s[2:3], s[4:5]       ; encoding: [0x7e,0x00,0xad,0xd4,0x02,0x08,0x00,0x00]
+0x7e,0x00,0xad,0xd4,0x02,0x08,0x00,0x00
+
+# GFX12: v_cmpx_neq_f64_e64 s[104:105], s[104:105] ; encoding: [0x7e,0x00,0xad,0xd4,0x68,0xd0,0x00,0x00]
+0x7e,0x00,0xad,0xd4,0x68,0xd0,0x00,0x00
+
+# GFX12: v_cmpx_neq_f64_e64 vcc, ttmp[14:15]     ; encoding: [0x7e,0x00,0xad,0xd4,0x6a,0xf4,0x00,0x00]
+0x7e,0x00,0xad,0xd4,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_cmpx_neq_f64_e64 ttmp[14:15], 0xaf123456 ; encoding: [0x7e,0x00,0xad,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xad,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_neq_f64_e64 -|exec|, src_scc     ; encoding: [0x7e,0x01,0xad,0xd4,0x7e,0xfa,0x01,0x20]
+0x7e,0x01,0xad,0xd4,0x7e,0xfa,0x01,0x20
+
+# GFX12: v_cmpx_neq_f64_e64 null, 0.5            ; encoding: [0x7e,0x00,0xad,0xd4,0x7c,0xe0,0x01,0x00]
+0x7e,0x00,0xad,0xd4,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_neq_f64_e64 -1, -1               ; encoding: [0x7e,0x00,0xad,0xd4,0xc1,0x82,0x01,0x00]
+0x7e,0x00,0xad,0xd4,0xc1,0x82,0x01,0x00
+
+# GFX12: v_cmpx_neq_f64_e64 0.5, null            ; encoding: [0x7e,0x00,0xad,0xd4,0xf0,0xf8,0x00,0x00]
+0x7e,0x00,0xad,0xd4,0xf0,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_neq_f64_e64 -|src_scc|, -|exec|  ; encoding: [0x7e,0x03,0xad,0xd4,0xfd,0xfc,0x00,0x60]
+0x7e,0x03,0xad,0xd4,0xfd,0xfc,0x00,0x60
+
+# GFX12: v_cmpx_neq_f64_e64 0xaf123456, -|vcc| clamp ; encoding: [0x7e,0x82,0xad,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+0x7e,0x82,0xad,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_nge_f16_e64 v1, v2               ; encoding: [0x7e,0x00,0x89,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0x89,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_nge_f16_e64 v255, v255           ; encoding: [0x7e,0x00,0x89,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0x89,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_nge_f16_e64 s1, s2               ; encoding: [0x7e,0x00,0x89,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0x89,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_nge_f16_e64 s105, s105           ; encoding: [0x7e,0x00,0x89,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0x89,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_nge_f16_e64 vcc_lo, ttmp15       ; encoding: [0x7e,0x00,0x89,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0x89,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_nge_f16_e64 vcc_hi, 0xfe0b       ; encoding: [0x7e,0x00,0x89,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0x89,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_nge_f16_e64 ttmp15, src_scc      ; encoding: [0x7e,0x00,0x89,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0x89,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_nge_f16_e64 m0, 0.5              ; encoding: [0x7e,0x00,0x89,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0x89,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_nge_f16_e64 exec_lo, -1          ; encoding: [0x7e,0x00,0x89,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0x89,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_nge_f16_e64 |exec_hi|, null      ; encoding: [0x7e,0x01,0x89,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x01,0x89,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_nge_f16_e64 null, exec_lo        ; encoding: [0x7e,0x00,0x89,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0x89,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_nge_f16_e64 -1, exec_hi          ; encoding: [0x7e,0x00,0x89,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0x89,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_nge_f16_e64 0.5, -m0             ; encoding: [0x7e,0x00,0x89,0xd4,0xf0,0xfa,0x00,0x40]
+0x7e,0x00,0x89,0xd4,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cmpx_nge_f16_e64 -src_scc, |vcc_lo|   ; encoding: [0x7e,0x02,0x89,0xd4,0xfd,0xd4,0x00,0x20]
+0x7e,0x02,0x89,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmpx_nge_f16_e64 -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7e,0x83,0x89,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x7e,0x83,0x89,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_nge_f32_e64 v1, v2               ; encoding: [0x7e,0x00,0x99,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0x99,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_nge_f32_e64 v255, v255           ; encoding: [0x7e,0x00,0x99,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0x99,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_nge_f32_e64 s1, s2               ; encoding: [0x7e,0x00,0x99,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0x99,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_nge_f32_e64 s105, s105           ; encoding: [0x7e,0x00,0x99,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0x99,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_nge_f32_e64 vcc_lo, ttmp15       ; encoding: [0x7e,0x00,0x99,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0x99,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_nge_f32_e64 vcc_hi, 0xaf123456   ; encoding: [0x7e,0x00,0x99,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0x99,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_nge_f32_e64 ttmp15, src_scc      ; encoding: [0x7e,0x00,0x99,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0x99,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_nge_f32_e64 m0, 0.5              ; encoding: [0x7e,0x00,0x99,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0x99,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_nge_f32_e64 exec_lo, -1          ; encoding: [0x7e,0x00,0x99,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0x99,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_nge_f32_e64 |exec_hi|, null      ; encoding: [0x7e,0x01,0x99,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x01,0x99,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_nge_f32_e64 null, exec_lo        ; encoding: [0x7e,0x00,0x99,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0x99,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_nge_f32_e64 -1, exec_hi          ; encoding: [0x7e,0x00,0x99,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0x99,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_nge_f32_e64 0.5, -m0             ; encoding: [0x7e,0x00,0x99,0xd4,0xf0,0xfa,0x00,0x40]
+0x7e,0x00,0x99,0xd4,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cmpx_nge_f32_e64 -src_scc, |vcc_lo|   ; encoding: [0x7e,0x02,0x99,0xd4,0xfd,0xd4,0x00,0x20]
+0x7e,0x02,0x99,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmpx_nge_f32_e64 -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0x7e,0x83,0x99,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0x7e,0x83,0x99,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_nge_f64_e64 v[1:2], v[2:3]       ; encoding: [0x7e,0x00,0xa9,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xa9,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_nge_f64_e64 v[254:255], v[254:255] ; encoding: [0x7e,0x00,0xa9,0xd4,0xfe,0xfd,0x03,0x00]
+0x7e,0x00,0xa9,0xd4,0xfe,0xfd,0x03,0x00
+
+# GFX12: v_cmpx_nge_f64_e64 s[2:3], s[4:5]       ; encoding: [0x7e,0x00,0xa9,0xd4,0x02,0x08,0x00,0x00]
+0x7e,0x00,0xa9,0xd4,0x02,0x08,0x00,0x00
+
+# GFX12: v_cmpx_nge_f64_e64 s[104:105], s[104:105] ; encoding: [0x7e,0x00,0xa9,0xd4,0x68,0xd0,0x00,0x00]
+0x7e,0x00,0xa9,0xd4,0x68,0xd0,0x00,0x00
+
+# GFX12: v_cmpx_nge_f64_e64 vcc, ttmp[14:15]     ; encoding: [0x7e,0x00,0xa9,0xd4,0x6a,0xf4,0x00,0x00]
+0x7e,0x00,0xa9,0xd4,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_cmpx_nge_f64_e64 ttmp[14:15], 0xaf123456 ; encoding: [0x7e,0x00,0xa9,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xa9,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_nge_f64_e64 -|exec|, src_scc     ; encoding: [0x7e,0x01,0xa9,0xd4,0x7e,0xfa,0x01,0x20]
+0x7e,0x01,0xa9,0xd4,0x7e,0xfa,0x01,0x20
+
+# GFX12: v_cmpx_nge_f64_e64 null, 0.5            ; encoding: [0x7e,0x00,0xa9,0xd4,0x7c,0xe0,0x01,0x00]
+0x7e,0x00,0xa9,0xd4,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_nge_f64_e64 -1, -1               ; encoding: [0x7e,0x00,0xa9,0xd4,0xc1,0x82,0x01,0x00]
+0x7e,0x00,0xa9,0xd4,0xc1,0x82,0x01,0x00
+
+# GFX12: v_cmpx_nge_f64_e64 0.5, null            ; encoding: [0x7e,0x00,0xa9,0xd4,0xf0,0xf8,0x00,0x00]
+0x7e,0x00,0xa9,0xd4,0xf0,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_nge_f64_e64 -|src_scc|, -|exec|  ; encoding: [0x7e,0x03,0xa9,0xd4,0xfd,0xfc,0x00,0x60]
+0x7e,0x03,0xa9,0xd4,0xfd,0xfc,0x00,0x60
+
+# GFX12: v_cmpx_nge_f64_e64 0xaf123456, -|vcc| clamp ; encoding: [0x7e,0x82,0xa9,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+0x7e,0x82,0xa9,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ngt_f16_e64 v1, v2               ; encoding: [0x7e,0x00,0x8b,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0x8b,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_ngt_f16_e64 v255, v255           ; encoding: [0x7e,0x00,0x8b,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0x8b,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_ngt_f16_e64 s1, s2               ; encoding: [0x7e,0x00,0x8b,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0x8b,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_ngt_f16_e64 s105, s105           ; encoding: [0x7e,0x00,0x8b,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0x8b,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_ngt_f16_e64 vcc_lo, ttmp15       ; encoding: [0x7e,0x00,0x8b,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0x8b,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_ngt_f16_e64 vcc_hi, 0xfe0b       ; encoding: [0x7e,0x00,0x8b,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0x8b,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ngt_f16_e64 ttmp15, src_scc      ; encoding: [0x7e,0x00,0x8b,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0x8b,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_ngt_f16_e64 m0, 0.5              ; encoding: [0x7e,0x00,0x8b,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0x8b,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_ngt_f16_e64 exec_lo, -1          ; encoding: [0x7e,0x00,0x8b,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0x8b,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_ngt_f16_e64 |exec_hi|, null      ; encoding: [0x7e,0x01,0x8b,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x01,0x8b,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_ngt_f16_e64 null, exec_lo        ; encoding: [0x7e,0x00,0x8b,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0x8b,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_ngt_f16_e64 -1, exec_hi          ; encoding: [0x7e,0x00,0x8b,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0x8b,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ngt_f16_e64 0.5, -m0             ; encoding: [0x7e,0x00,0x8b,0xd4,0xf0,0xfa,0x00,0x40]
+0x7e,0x00,0x8b,0xd4,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cmpx_ngt_f16_e64 -src_scc, |vcc_lo|   ; encoding: [0x7e,0x02,0x8b,0xd4,0xfd,0xd4,0x00,0x20]
+0x7e,0x02,0x8b,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmpx_ngt_f16_e64 -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7e,0x83,0x8b,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x7e,0x83,0x8b,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ngt_f32_e64 v1, v2               ; encoding: [0x7e,0x00,0x9b,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0x9b,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_ngt_f32_e64 v255, v255           ; encoding: [0x7e,0x00,0x9b,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0x9b,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_ngt_f32_e64 s1, s2               ; encoding: [0x7e,0x00,0x9b,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0x9b,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_ngt_f32_e64 s105, s105           ; encoding: [0x7e,0x00,0x9b,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0x9b,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_ngt_f32_e64 vcc_lo, ttmp15       ; encoding: [0x7e,0x00,0x9b,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0x9b,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_ngt_f32_e64 vcc_hi, 0xaf123456   ; encoding: [0x7e,0x00,0x9b,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0x9b,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ngt_f32_e64 ttmp15, src_scc      ; encoding: [0x7e,0x00,0x9b,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0x9b,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_ngt_f32_e64 m0, 0.5              ; encoding: [0x7e,0x00,0x9b,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0x9b,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_ngt_f32_e64 exec_lo, -1          ; encoding: [0x7e,0x00,0x9b,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0x9b,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_ngt_f32_e64 |exec_hi|, null      ; encoding: [0x7e,0x01,0x9b,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x01,0x9b,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_ngt_f32_e64 null, exec_lo        ; encoding: [0x7e,0x00,0x9b,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0x9b,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_ngt_f32_e64 -1, exec_hi          ; encoding: [0x7e,0x00,0x9b,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0x9b,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ngt_f32_e64 0.5, -m0             ; encoding: [0x7e,0x00,0x9b,0xd4,0xf0,0xfa,0x00,0x40]
+0x7e,0x00,0x9b,0xd4,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cmpx_ngt_f32_e64 -src_scc, |vcc_lo|   ; encoding: [0x7e,0x02,0x9b,0xd4,0xfd,0xd4,0x00,0x20]
+0x7e,0x02,0x9b,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmpx_ngt_f32_e64 -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0x7e,0x83,0x9b,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0x7e,0x83,0x9b,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ngt_f64_e64 v[1:2], v[2:3]       ; encoding: [0x7e,0x00,0xab,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xab,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_ngt_f64_e64 v[254:255], v[254:255] ; encoding: [0x7e,0x00,0xab,0xd4,0xfe,0xfd,0x03,0x00]
+0x7e,0x00,0xab,0xd4,0xfe,0xfd,0x03,0x00
+
+# GFX12: v_cmpx_ngt_f64_e64 s[2:3], s[4:5]       ; encoding: [0x7e,0x00,0xab,0xd4,0x02,0x08,0x00,0x00]
+0x7e,0x00,0xab,0xd4,0x02,0x08,0x00,0x00
+
+# GFX12: v_cmpx_ngt_f64_e64 s[104:105], s[104:105] ; encoding: [0x7e,0x00,0xab,0xd4,0x68,0xd0,0x00,0x00]
+0x7e,0x00,0xab,0xd4,0x68,0xd0,0x00,0x00
+
+# GFX12: v_cmpx_ngt_f64_e64 vcc, ttmp[14:15]     ; encoding: [0x7e,0x00,0xab,0xd4,0x6a,0xf4,0x00,0x00]
+0x7e,0x00,0xab,0xd4,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_cmpx_ngt_f64_e64 ttmp[14:15], 0xaf123456 ; encoding: [0x7e,0x00,0xab,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xab,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ngt_f64_e64 -|exec|, src_scc     ; encoding: [0x7e,0x01,0xab,0xd4,0x7e,0xfa,0x01,0x20]
+0x7e,0x01,0xab,0xd4,0x7e,0xfa,0x01,0x20
+
+# GFX12: v_cmpx_ngt_f64_e64 null, 0.5            ; encoding: [0x7e,0x00,0xab,0xd4,0x7c,0xe0,0x01,0x00]
+0x7e,0x00,0xab,0xd4,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_ngt_f64_e64 -1, -1               ; encoding: [0x7e,0x00,0xab,0xd4,0xc1,0x82,0x01,0x00]
+0x7e,0x00,0xab,0xd4,0xc1,0x82,0x01,0x00
+
+# GFX12: v_cmpx_ngt_f64_e64 0.5, null            ; encoding: [0x7e,0x00,0xab,0xd4,0xf0,0xf8,0x00,0x00]
+0x7e,0x00,0xab,0xd4,0xf0,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_ngt_f64_e64 -|src_scc|, -|exec|  ; encoding: [0x7e,0x03,0xab,0xd4,0xfd,0xfc,0x00,0x60]
+0x7e,0x03,0xab,0xd4,0xfd,0xfc,0x00,0x60
+
+# GFX12: v_cmpx_ngt_f64_e64 0xaf123456, -|vcc| clamp ; encoding: [0x7e,0x82,0xab,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+0x7e,0x82,0xab,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_nle_f16_e64 v1, v2               ; encoding: [0x7e,0x00,0x8c,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0x8c,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_nle_f16_e64 v255, v255           ; encoding: [0x7e,0x00,0x8c,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0x8c,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_nle_f16_e64 s1, s2               ; encoding: [0x7e,0x00,0x8c,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0x8c,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_nle_f16_e64 s105, s105           ; encoding: [0x7e,0x00,0x8c,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0x8c,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_nle_f16_e64 vcc_lo, ttmp15       ; encoding: [0x7e,0x00,0x8c,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0x8c,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_nle_f16_e64 vcc_hi, 0xfe0b       ; encoding: [0x7e,0x00,0x8c,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0x8c,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_nle_f16_e64 ttmp15, src_scc      ; encoding: [0x7e,0x00,0x8c,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0x8c,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_nle_f16_e64 m0, 0.5              ; encoding: [0x7e,0x00,0x8c,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0x8c,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_nle_f16_e64 exec_lo, -1          ; encoding: [0x7e,0x00,0x8c,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0x8c,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_nle_f16_e64 |exec_hi|, null      ; encoding: [0x7e,0x01,0x8c,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x01,0x8c,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_nle_f16_e64 null, exec_lo        ; encoding: [0x7e,0x00,0x8c,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0x8c,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_nle_f16_e64 -1, exec_hi          ; encoding: [0x7e,0x00,0x8c,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0x8c,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_nle_f16_e64 0.5, -m0             ; encoding: [0x7e,0x00,0x8c,0xd4,0xf0,0xfa,0x00,0x40]
+0x7e,0x00,0x8c,0xd4,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cmpx_nle_f16_e64 -src_scc, |vcc_lo|   ; encoding: [0x7e,0x02,0x8c,0xd4,0xfd,0xd4,0x00,0x20]
+0x7e,0x02,0x8c,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmpx_nle_f16_e64 -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7e,0x83,0x8c,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x7e,0x83,0x8c,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_nle_f32_e64 v1, v2               ; encoding: [0x7e,0x00,0x9c,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0x9c,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_nle_f32_e64 v255, v255           ; encoding: [0x7e,0x00,0x9c,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0x9c,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_nle_f32_e64 s1, s2               ; encoding: [0x7e,0x00,0x9c,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0x9c,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_nle_f32_e64 s105, s105           ; encoding: [0x7e,0x00,0x9c,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0x9c,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_nle_f32_e64 vcc_lo, ttmp15       ; encoding: [0x7e,0x00,0x9c,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0x9c,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_nle_f32_e64 vcc_hi, 0xaf123456   ; encoding: [0x7e,0x00,0x9c,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0x9c,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_nle_f32_e64 ttmp15, src_scc      ; encoding: [0x7e,0x00,0x9c,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0x9c,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_nle_f32_e64 m0, 0.5              ; encoding: [0x7e,0x00,0x9c,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0x9c,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_nle_f32_e64 exec_lo, -1          ; encoding: [0x7e,0x00,0x9c,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0x9c,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_nle_f32_e64 |exec_hi|, null      ; encoding: [0x7e,0x01,0x9c,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x01,0x9c,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_nle_f32_e64 null, exec_lo        ; encoding: [0x7e,0x00,0x9c,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0x9c,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_nle_f32_e64 -1, exec_hi          ; encoding: [0x7e,0x00,0x9c,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0x9c,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_nle_f32_e64 0.5, -m0             ; encoding: [0x7e,0x00,0x9c,0xd4,0xf0,0xfa,0x00,0x40]
+0x7e,0x00,0x9c,0xd4,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cmpx_nle_f32_e64 -src_scc, |vcc_lo|   ; encoding: [0x7e,0x02,0x9c,0xd4,0xfd,0xd4,0x00,0x20]
+0x7e,0x02,0x9c,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmpx_nle_f32_e64 -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0x7e,0x83,0x9c,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0x7e,0x83,0x9c,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_nle_f64_e64 v[1:2], v[2:3]       ; encoding: [0x7e,0x00,0xac,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xac,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_nle_f64_e64 v[254:255], v[254:255] ; encoding: [0x7e,0x00,0xac,0xd4,0xfe,0xfd,0x03,0x00]
+0x7e,0x00,0xac,0xd4,0xfe,0xfd,0x03,0x00
+
+# GFX12: v_cmpx_nle_f64_e64 s[2:3], s[4:5]       ; encoding: [0x7e,0x00,0xac,0xd4,0x02,0x08,0x00,0x00]
+0x7e,0x00,0xac,0xd4,0x02,0x08,0x00,0x00
+
+# GFX12: v_cmpx_nle_f64_e64 s[104:105], s[104:105] ; encoding: [0x7e,0x00,0xac,0xd4,0x68,0xd0,0x00,0x00]
+0x7e,0x00,0xac,0xd4,0x68,0xd0,0x00,0x00
+
+# GFX12: v_cmpx_nle_f64_e64 vcc, ttmp[14:15]     ; encoding: [0x7e,0x00,0xac,0xd4,0x6a,0xf4,0x00,0x00]
+0x7e,0x00,0xac,0xd4,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_cmpx_nle_f64_e64 ttmp[14:15], 0xaf123456 ; encoding: [0x7e,0x00,0xac,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xac,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_nle_f64_e64 -|exec|, src_scc     ; encoding: [0x7e,0x01,0xac,0xd4,0x7e,0xfa,0x01,0x20]
+0x7e,0x01,0xac,0xd4,0x7e,0xfa,0x01,0x20
+
+# GFX12: v_cmpx_nle_f64_e64 null, 0.5            ; encoding: [0x7e,0x00,0xac,0xd4,0x7c,0xe0,0x01,0x00]
+0x7e,0x00,0xac,0xd4,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_nle_f64_e64 -1, -1               ; encoding: [0x7e,0x00,0xac,0xd4,0xc1,0x82,0x01,0x00]
+0x7e,0x00,0xac,0xd4,0xc1,0x82,0x01,0x00
+
+# GFX12: v_cmpx_nle_f64_e64 0.5, null            ; encoding: [0x7e,0x00,0xac,0xd4,0xf0,0xf8,0x00,0x00]
+0x7e,0x00,0xac,0xd4,0xf0,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_nle_f64_e64 -|src_scc|, -|exec|  ; encoding: [0x7e,0x03,0xac,0xd4,0xfd,0xfc,0x00,0x60]
+0x7e,0x03,0xac,0xd4,0xfd,0xfc,0x00,0x60
+
+# GFX12: v_cmpx_nle_f64_e64 0xaf123456, -|vcc| clamp ; encoding: [0x7e,0x82,0xac,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+0x7e,0x82,0xac,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_nlg_f16_e64 v1, v2               ; encoding: [0x7e,0x00,0x8a,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0x8a,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_nlg_f16_e64 v255, v255           ; encoding: [0x7e,0x00,0x8a,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0x8a,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_nlg_f16_e64 s1, s2               ; encoding: [0x7e,0x00,0x8a,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0x8a,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_nlg_f16_e64 s105, s105           ; encoding: [0x7e,0x00,0x8a,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0x8a,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_nlg_f16_e64 vcc_lo, ttmp15       ; encoding: [0x7e,0x00,0x8a,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0x8a,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_nlg_f16_e64 vcc_hi, 0xfe0b       ; encoding: [0x7e,0x00,0x8a,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0x8a,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_nlg_f16_e64 ttmp15, src_scc      ; encoding: [0x7e,0x00,0x8a,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0x8a,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_nlg_f16_e64 m0, 0.5              ; encoding: [0x7e,0x00,0x8a,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0x8a,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_nlg_f16_e64 exec_lo, -1          ; encoding: [0x7e,0x00,0x8a,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0x8a,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_nlg_f16_e64 |exec_hi|, null      ; encoding: [0x7e,0x01,0x8a,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x01,0x8a,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_nlg_f16_e64 null, exec_lo        ; encoding: [0x7e,0x00,0x8a,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0x8a,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_nlg_f16_e64 -1, exec_hi          ; encoding: [0x7e,0x00,0x8a,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0x8a,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_nlg_f16_e64 0.5, -m0             ; encoding: [0x7e,0x00,0x8a,0xd4,0xf0,0xfa,0x00,0x40]
+0x7e,0x00,0x8a,0xd4,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cmpx_nlg_f16_e64 -src_scc, |vcc_lo|   ; encoding: [0x7e,0x02,0x8a,0xd4,0xfd,0xd4,0x00,0x20]
+0x7e,0x02,0x8a,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmpx_nlg_f16_e64 -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7e,0x83,0x8a,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x7e,0x83,0x8a,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_nlg_f32_e64 v1, v2               ; encoding: [0x7e,0x00,0x9a,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0x9a,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_nlg_f32_e64 v255, v255           ; encoding: [0x7e,0x00,0x9a,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0x9a,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_nlg_f32_e64 s1, s2               ; encoding: [0x7e,0x00,0x9a,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0x9a,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_nlg_f32_e64 s105, s105           ; encoding: [0x7e,0x00,0x9a,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0x9a,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_nlg_f32_e64 vcc_lo, ttmp15       ; encoding: [0x7e,0x00,0x9a,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0x9a,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_nlg_f32_e64 vcc_hi, 0xaf123456   ; encoding: [0x7e,0x00,0x9a,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0x9a,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_nlg_f32_e64 ttmp15, src_scc      ; encoding: [0x7e,0x00,0x9a,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0x9a,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_nlg_f32_e64 m0, 0.5              ; encoding: [0x7e,0x00,0x9a,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0x9a,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_nlg_f32_e64 exec_lo, -1          ; encoding: [0x7e,0x00,0x9a,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0x9a,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_nlg_f32_e64 |exec_hi|, null      ; encoding: [0x7e,0x01,0x9a,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x01,0x9a,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_nlg_f32_e64 null, exec_lo        ; encoding: [0x7e,0x00,0x9a,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0x9a,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_nlg_f32_e64 -1, exec_hi          ; encoding: [0x7e,0x00,0x9a,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0x9a,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_nlg_f32_e64 0.5, -m0             ; encoding: [0x7e,0x00,0x9a,0xd4,0xf0,0xfa,0x00,0x40]
+0x7e,0x00,0x9a,0xd4,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cmpx_nlg_f32_e64 -src_scc, |vcc_lo|   ; encoding: [0x7e,0x02,0x9a,0xd4,0xfd,0xd4,0x00,0x20]
+0x7e,0x02,0x9a,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmpx_nlg_f32_e64 -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0x7e,0x83,0x9a,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0x7e,0x83,0x9a,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_nlg_f64_e64 v[1:2], v[2:3]       ; encoding: [0x7e,0x00,0xaa,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xaa,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_nlg_f64_e64 v[254:255], v[254:255] ; encoding: [0x7e,0x00,0xaa,0xd4,0xfe,0xfd,0x03,0x00]
+0x7e,0x00,0xaa,0xd4,0xfe,0xfd,0x03,0x00
+
+# GFX12: v_cmpx_nlg_f64_e64 s[2:3], s[4:5]       ; encoding: [0x7e,0x00,0xaa,0xd4,0x02,0x08,0x00,0x00]
+0x7e,0x00,0xaa,0xd4,0x02,0x08,0x00,0x00
+
+# GFX12: v_cmpx_nlg_f64_e64 s[104:105], s[104:105] ; encoding: [0x7e,0x00,0xaa,0xd4,0x68,0xd0,0x00,0x00]
+0x7e,0x00,0xaa,0xd4,0x68,0xd0,0x00,0x00
+
+# GFX12: v_cmpx_nlg_f64_e64 vcc, ttmp[14:15]     ; encoding: [0x7e,0x00,0xaa,0xd4,0x6a,0xf4,0x00,0x00]
+0x7e,0x00,0xaa,0xd4,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_cmpx_nlg_f64_e64 ttmp[14:15], 0xaf123456 ; encoding: [0x7e,0x00,0xaa,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xaa,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_nlg_f64_e64 -|exec|, src_scc     ; encoding: [0x7e,0x01,0xaa,0xd4,0x7e,0xfa,0x01,0x20]
+0x7e,0x01,0xaa,0xd4,0x7e,0xfa,0x01,0x20
+
+# GFX12: v_cmpx_nlg_f64_e64 null, 0.5            ; encoding: [0x7e,0x00,0xaa,0xd4,0x7c,0xe0,0x01,0x00]
+0x7e,0x00,0xaa,0xd4,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_nlg_f64_e64 -1, -1               ; encoding: [0x7e,0x00,0xaa,0xd4,0xc1,0x82,0x01,0x00]
+0x7e,0x00,0xaa,0xd4,0xc1,0x82,0x01,0x00
+
+# GFX12: v_cmpx_nlg_f64_e64 0.5, null            ; encoding: [0x7e,0x00,0xaa,0xd4,0xf0,0xf8,0x00,0x00]
+0x7e,0x00,0xaa,0xd4,0xf0,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_nlg_f64_e64 -|src_scc|, -|exec|  ; encoding: [0x7e,0x03,0xaa,0xd4,0xfd,0xfc,0x00,0x60]
+0x7e,0x03,0xaa,0xd4,0xfd,0xfc,0x00,0x60
+
+# GFX12: v_cmpx_nlg_f64_e64 0xaf123456, -|vcc| clamp ; encoding: [0x7e,0x82,0xaa,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+0x7e,0x82,0xaa,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_nlt_f16_e64 v1, v2               ; encoding: [0x7e,0x00,0x8e,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0x8e,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_nlt_f16_e64 v255, v255           ; encoding: [0x7e,0x00,0x8e,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0x8e,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_nlt_f16_e64 s1, s2               ; encoding: [0x7e,0x00,0x8e,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0x8e,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_nlt_f16_e64 s105, s105           ; encoding: [0x7e,0x00,0x8e,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0x8e,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_nlt_f16_e64 vcc_lo, ttmp15       ; encoding: [0x7e,0x00,0x8e,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0x8e,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_nlt_f16_e64 vcc_hi, 0xfe0b       ; encoding: [0x7e,0x00,0x8e,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0x8e,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_nlt_f16_e64 ttmp15, src_scc      ; encoding: [0x7e,0x00,0x8e,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0x8e,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_nlt_f16_e64 m0, 0.5              ; encoding: [0x7e,0x00,0x8e,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0x8e,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_nlt_f16_e64 exec_lo, -1          ; encoding: [0x7e,0x00,0x8e,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0x8e,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_nlt_f16_e64 |exec_hi|, null      ; encoding: [0x7e,0x01,0x8e,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x01,0x8e,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_nlt_f16_e64 null, exec_lo        ; encoding: [0x7e,0x00,0x8e,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0x8e,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_nlt_f16_e64 -1, exec_hi          ; encoding: [0x7e,0x00,0x8e,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0x8e,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_nlt_f16_e64 0.5, -m0             ; encoding: [0x7e,0x00,0x8e,0xd4,0xf0,0xfa,0x00,0x40]
+0x7e,0x00,0x8e,0xd4,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cmpx_nlt_f16_e64 -src_scc, |vcc_lo|   ; encoding: [0x7e,0x02,0x8e,0xd4,0xfd,0xd4,0x00,0x20]
+0x7e,0x02,0x8e,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmpx_nlt_f16_e64 -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7e,0x83,0x8e,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x7e,0x83,0x8e,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_nlt_f32_e64 v1, v2               ; encoding: [0x7e,0x00,0x9e,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0x9e,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_nlt_f32_e64 v255, v255           ; encoding: [0x7e,0x00,0x9e,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0x9e,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_nlt_f32_e64 s1, s2               ; encoding: [0x7e,0x00,0x9e,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0x9e,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_nlt_f32_e64 s105, s105           ; encoding: [0x7e,0x00,0x9e,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0x9e,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_nlt_f32_e64 vcc_lo, ttmp15       ; encoding: [0x7e,0x00,0x9e,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0x9e,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_nlt_f32_e64 vcc_hi, 0xaf123456   ; encoding: [0x7e,0x00,0x9e,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0x9e,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_nlt_f32_e64 ttmp15, src_scc      ; encoding: [0x7e,0x00,0x9e,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0x9e,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_nlt_f32_e64 m0, 0.5              ; encoding: [0x7e,0x00,0x9e,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0x9e,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_nlt_f32_e64 exec_lo, -1          ; encoding: [0x7e,0x00,0x9e,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0x9e,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_nlt_f32_e64 |exec_hi|, null      ; encoding: [0x7e,0x01,0x9e,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x01,0x9e,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_nlt_f32_e64 null, exec_lo        ; encoding: [0x7e,0x00,0x9e,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0x9e,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_nlt_f32_e64 -1, exec_hi          ; encoding: [0x7e,0x00,0x9e,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0x9e,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_nlt_f32_e64 0.5, -m0             ; encoding: [0x7e,0x00,0x9e,0xd4,0xf0,0xfa,0x00,0x40]
+0x7e,0x00,0x9e,0xd4,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cmpx_nlt_f32_e64 -src_scc, |vcc_lo|   ; encoding: [0x7e,0x02,0x9e,0xd4,0xfd,0xd4,0x00,0x20]
+0x7e,0x02,0x9e,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmpx_nlt_f32_e64 -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0x7e,0x83,0x9e,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0x7e,0x83,0x9e,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_nlt_f64_e64 v[1:2], v[2:3]       ; encoding: [0x7e,0x00,0xae,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xae,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_nlt_f64_e64 v[254:255], v[254:255] ; encoding: [0x7e,0x00,0xae,0xd4,0xfe,0xfd,0x03,0x00]
+0x7e,0x00,0xae,0xd4,0xfe,0xfd,0x03,0x00
+
+# GFX12: v_cmpx_nlt_f64_e64 s[2:3], s[4:5]       ; encoding: [0x7e,0x00,0xae,0xd4,0x02,0x08,0x00,0x00]
+0x7e,0x00,0xae,0xd4,0x02,0x08,0x00,0x00
+
+# GFX12: v_cmpx_nlt_f64_e64 s[104:105], s[104:105] ; encoding: [0x7e,0x00,0xae,0xd4,0x68,0xd0,0x00,0x00]
+0x7e,0x00,0xae,0xd4,0x68,0xd0,0x00,0x00
+
+# GFX12: v_cmpx_nlt_f64_e64 vcc, ttmp[14:15]     ; encoding: [0x7e,0x00,0xae,0xd4,0x6a,0xf4,0x00,0x00]
+0x7e,0x00,0xae,0xd4,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_cmpx_nlt_f64_e64 ttmp[14:15], 0xaf123456 ; encoding: [0x7e,0x00,0xae,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xae,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_nlt_f64_e64 -|exec|, src_scc     ; encoding: [0x7e,0x01,0xae,0xd4,0x7e,0xfa,0x01,0x20]
+0x7e,0x01,0xae,0xd4,0x7e,0xfa,0x01,0x20
+
+# GFX12: v_cmpx_nlt_f64_e64 null, 0.5            ; encoding: [0x7e,0x00,0xae,0xd4,0x7c,0xe0,0x01,0x00]
+0x7e,0x00,0xae,0xd4,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_nlt_f64_e64 -1, -1               ; encoding: [0x7e,0x00,0xae,0xd4,0xc1,0x82,0x01,0x00]
+0x7e,0x00,0xae,0xd4,0xc1,0x82,0x01,0x00
+
+# GFX12: v_cmpx_nlt_f64_e64 0.5, null            ; encoding: [0x7e,0x00,0xae,0xd4,0xf0,0xf8,0x00,0x00]
+0x7e,0x00,0xae,0xd4,0xf0,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_nlt_f64_e64 -|src_scc|, -|exec|  ; encoding: [0x7e,0x03,0xae,0xd4,0xfd,0xfc,0x00,0x60]
+0x7e,0x03,0xae,0xd4,0xfd,0xfc,0x00,0x60
+
+# GFX12: v_cmpx_nlt_f64_e64 0xaf123456, -|vcc| clamp ; encoding: [0x7e,0x82,0xae,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+0x7e,0x82,0xae,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_o_f16_e64 v1, v2                 ; encoding: [0x7e,0x00,0x87,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0x87,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_o_f16_e64 v255, v255             ; encoding: [0x7e,0x00,0x87,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0x87,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_o_f16_e64 s1, s2                 ; encoding: [0x7e,0x00,0x87,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0x87,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_o_f16_e64 s105, s105             ; encoding: [0x7e,0x00,0x87,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0x87,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_o_f16_e64 vcc_lo, ttmp15         ; encoding: [0x7e,0x00,0x87,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0x87,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_o_f16_e64 vcc_hi, 0xfe0b         ; encoding: [0x7e,0x00,0x87,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0x87,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_o_f16_e64 ttmp15, src_scc        ; encoding: [0x7e,0x00,0x87,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0x87,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_o_f16_e64 m0, 0.5                ; encoding: [0x7e,0x00,0x87,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0x87,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_o_f16_e64 exec_lo, -1            ; encoding: [0x7e,0x00,0x87,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0x87,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_o_f16_e64 |exec_hi|, null        ; encoding: [0x7e,0x01,0x87,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x01,0x87,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_o_f16_e64 null, exec_lo          ; encoding: [0x7e,0x00,0x87,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0x87,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_o_f16_e64 -1, exec_hi            ; encoding: [0x7e,0x00,0x87,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0x87,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_o_f16_e64 0.5, -m0               ; encoding: [0x7e,0x00,0x87,0xd4,0xf0,0xfa,0x00,0x40]
+0x7e,0x00,0x87,0xd4,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cmpx_o_f16_e64 -src_scc, |vcc_lo|     ; encoding: [0x7e,0x02,0x87,0xd4,0xfd,0xd4,0x00,0x20]
+0x7e,0x02,0x87,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmpx_o_f16_e64 -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7e,0x83,0x87,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x7e,0x83,0x87,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_o_f32_e64 v1, v2                 ; encoding: [0x7e,0x00,0x97,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0x97,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_o_f32_e64 v255, v255             ; encoding: [0x7e,0x00,0x97,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0x97,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_o_f32_e64 s1, s2                 ; encoding: [0x7e,0x00,0x97,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0x97,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_o_f32_e64 s105, s105             ; encoding: [0x7e,0x00,0x97,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0x97,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_o_f32_e64 vcc_lo, ttmp15         ; encoding: [0x7e,0x00,0x97,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0x97,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_o_f32_e64 vcc_hi, 0xaf123456     ; encoding: [0x7e,0x00,0x97,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0x97,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_o_f32_e64 ttmp15, src_scc        ; encoding: [0x7e,0x00,0x97,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0x97,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_o_f32_e64 m0, 0.5                ; encoding: [0x7e,0x00,0x97,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0x97,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_o_f32_e64 exec_lo, -1            ; encoding: [0x7e,0x00,0x97,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0x97,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_o_f32_e64 |exec_hi|, null        ; encoding: [0x7e,0x01,0x97,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x01,0x97,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_o_f32_e64 null, exec_lo          ; encoding: [0x7e,0x00,0x97,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0x97,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_o_f32_e64 -1, exec_hi            ; encoding: [0x7e,0x00,0x97,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0x97,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_o_f32_e64 0.5, -m0               ; encoding: [0x7e,0x00,0x97,0xd4,0xf0,0xfa,0x00,0x40]
+0x7e,0x00,0x97,0xd4,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cmpx_o_f32_e64 -src_scc, |vcc_lo|     ; encoding: [0x7e,0x02,0x97,0xd4,0xfd,0xd4,0x00,0x20]
+0x7e,0x02,0x97,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmpx_o_f32_e64 -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0x7e,0x83,0x97,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0x7e,0x83,0x97,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_o_f64_e64 v[1:2], v[2:3]         ; encoding: [0x7e,0x00,0xa7,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xa7,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_o_f64_e64 v[254:255], v[254:255] ; encoding: [0x7e,0x00,0xa7,0xd4,0xfe,0xfd,0x03,0x00]
+0x7e,0x00,0xa7,0xd4,0xfe,0xfd,0x03,0x00
+
+# GFX12: v_cmpx_o_f64_e64 s[2:3], s[4:5]         ; encoding: [0x7e,0x00,0xa7,0xd4,0x02,0x08,0x00,0x00]
+0x7e,0x00,0xa7,0xd4,0x02,0x08,0x00,0x00
+
+# GFX12: v_cmpx_o_f64_e64 s[104:105], s[104:105] ; encoding: [0x7e,0x00,0xa7,0xd4,0x68,0xd0,0x00,0x00]
+0x7e,0x00,0xa7,0xd4,0x68,0xd0,0x00,0x00
+
+# GFX12: v_cmpx_o_f64_e64 vcc, ttmp[14:15]       ; encoding: [0x7e,0x00,0xa7,0xd4,0x6a,0xf4,0x00,0x00]
+0x7e,0x00,0xa7,0xd4,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_cmpx_o_f64_e64 ttmp[14:15], 0xaf123456 ; encoding: [0x7e,0x00,0xa7,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xa7,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_o_f64_e64 -|exec|, src_scc       ; encoding: [0x7e,0x01,0xa7,0xd4,0x7e,0xfa,0x01,0x20]
+0x7e,0x01,0xa7,0xd4,0x7e,0xfa,0x01,0x20
+
+# GFX12: v_cmpx_o_f64_e64 null, 0.5              ; encoding: [0x7e,0x00,0xa7,0xd4,0x7c,0xe0,0x01,0x00]
+0x7e,0x00,0xa7,0xd4,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_o_f64_e64 -1, -1                 ; encoding: [0x7e,0x00,0xa7,0xd4,0xc1,0x82,0x01,0x00]
+0x7e,0x00,0xa7,0xd4,0xc1,0x82,0x01,0x00
+
+# GFX12: v_cmpx_o_f64_e64 0.5, null              ; encoding: [0x7e,0x00,0xa7,0xd4,0xf0,0xf8,0x00,0x00]
+0x7e,0x00,0xa7,0xd4,0xf0,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_o_f64_e64 -|src_scc|, -|exec|    ; encoding: [0x7e,0x03,0xa7,0xd4,0xfd,0xfc,0x00,0x60]
+0x7e,0x03,0xa7,0xd4,0xfd,0xfc,0x00,0x60
+
+# GFX12: v_cmpx_o_f64_e64 0xaf123456, -|vcc| clamp ; encoding: [0x7e,0x82,0xa7,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+0x7e,0x82,0xa7,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_u_f16_e64 v1, v2                 ; encoding: [0x7e,0x00,0x88,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0x88,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_u_f16_e64 v255, v255             ; encoding: [0x7e,0x00,0x88,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0x88,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_u_f16_e64 s1, s2                 ; encoding: [0x7e,0x00,0x88,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0x88,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_u_f16_e64 s105, s105             ; encoding: [0x7e,0x00,0x88,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0x88,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_u_f16_e64 vcc_lo, ttmp15         ; encoding: [0x7e,0x00,0x88,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0x88,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_u_f16_e64 vcc_hi, 0xfe0b         ; encoding: [0x7e,0x00,0x88,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+0x7e,0x00,0x88,0xd4,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_u_f16_e64 ttmp15, src_scc        ; encoding: [0x7e,0x00,0x88,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0x88,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_u_f16_e64 m0, 0.5                ; encoding: [0x7e,0x00,0x88,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0x88,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_u_f16_e64 exec_lo, -1            ; encoding: [0x7e,0x00,0x88,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0x88,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_u_f16_e64 |exec_hi|, null        ; encoding: [0x7e,0x01,0x88,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x01,0x88,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_u_f16_e64 null, exec_lo          ; encoding: [0x7e,0x00,0x88,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0x88,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_u_f16_e64 -1, exec_hi            ; encoding: [0x7e,0x00,0x88,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0x88,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_u_f16_e64 0.5, -m0               ; encoding: [0x7e,0x00,0x88,0xd4,0xf0,0xfa,0x00,0x40]
+0x7e,0x00,0x88,0xd4,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cmpx_u_f16_e64 -src_scc, |vcc_lo|     ; encoding: [0x7e,0x02,0x88,0xd4,0xfd,0xd4,0x00,0x20]
+0x7e,0x02,0x88,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmpx_u_f16_e64 -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7e,0x83,0x88,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x7e,0x83,0x88,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_u_f32_e64 v1, v2                 ; encoding: [0x7e,0x00,0x98,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0x98,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_u_f32_e64 v255, v255             ; encoding: [0x7e,0x00,0x98,0xd4,0xff,0xff,0x03,0x00]
+0x7e,0x00,0x98,0xd4,0xff,0xff,0x03,0x00
+
+# GFX12: v_cmpx_u_f32_e64 s1, s2                 ; encoding: [0x7e,0x00,0x98,0xd4,0x01,0x04,0x00,0x00]
+0x7e,0x00,0x98,0xd4,0x01,0x04,0x00,0x00
+
+# GFX12: v_cmpx_u_f32_e64 s105, s105             ; encoding: [0x7e,0x00,0x98,0xd4,0x69,0xd2,0x00,0x00]
+0x7e,0x00,0x98,0xd4,0x69,0xd2,0x00,0x00
+
+# GFX12: v_cmpx_u_f32_e64 vcc_lo, ttmp15         ; encoding: [0x7e,0x00,0x98,0xd4,0x6a,0xf6,0x00,0x00]
+0x7e,0x00,0x98,0xd4,0x6a,0xf6,0x00,0x00
+
+# GFX12: v_cmpx_u_f32_e64 vcc_hi, 0xaf123456     ; encoding: [0x7e,0x00,0x98,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0x98,0xd4,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_u_f32_e64 ttmp15, src_scc        ; encoding: [0x7e,0x00,0x98,0xd4,0x7b,0xfa,0x01,0x00]
+0x7e,0x00,0x98,0xd4,0x7b,0xfa,0x01,0x00
+
+# GFX12: v_cmpx_u_f32_e64 m0, 0.5                ; encoding: [0x7e,0x00,0x98,0xd4,0x7d,0xe0,0x01,0x00]
+0x7e,0x00,0x98,0xd4,0x7d,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_u_f32_e64 exec_lo, -1            ; encoding: [0x7e,0x00,0x98,0xd4,0x7e,0x82,0x01,0x00]
+0x7e,0x00,0x98,0xd4,0x7e,0x82,0x01,0x00
+
+# GFX12: v_cmpx_u_f32_e64 |exec_hi|, null        ; encoding: [0x7e,0x01,0x98,0xd4,0x7f,0xf8,0x00,0x00]
+0x7e,0x01,0x98,0xd4,0x7f,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_u_f32_e64 null, exec_lo          ; encoding: [0x7e,0x00,0x98,0xd4,0x7c,0xfc,0x00,0x00]
+0x7e,0x00,0x98,0xd4,0x7c,0xfc,0x00,0x00
+
+# GFX12: v_cmpx_u_f32_e64 -1, exec_hi            ; encoding: [0x7e,0x00,0x98,0xd4,0xc1,0xfe,0x00,0x00]
+0x7e,0x00,0x98,0xd4,0xc1,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_u_f32_e64 0.5, -m0               ; encoding: [0x7e,0x00,0x98,0xd4,0xf0,0xfa,0x00,0x40]
+0x7e,0x00,0x98,0xd4,0xf0,0xfa,0x00,0x40
+
+# GFX12: v_cmpx_u_f32_e64 -src_scc, |vcc_lo|     ; encoding: [0x7e,0x02,0x98,0xd4,0xfd,0xd4,0x00,0x20]
+0x7e,0x02,0x98,0xd4,0xfd,0xd4,0x00,0x20
+
+# GFX12: v_cmpx_u_f32_e64 -|0xaf123456|, -|vcc_hi| clamp ; encoding: [0x7e,0x83,0x98,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+0x7e,0x83,0x98,0xd4,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_u_f64_e64 v[1:2], v[2:3]         ; encoding: [0x7e,0x00,0xa8,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x00,0xa8,0xd4,0x01,0x05,0x02,0x00
+
+# GFX12: v_cmpx_u_f64_e64 v[254:255], v[254:255] ; encoding: [0x7e,0x00,0xa8,0xd4,0xfe,0xfd,0x03,0x00]
+0x7e,0x00,0xa8,0xd4,0xfe,0xfd,0x03,0x00
+
+# GFX12: v_cmpx_u_f64_e64 s[2:3], s[4:5]         ; encoding: [0x7e,0x00,0xa8,0xd4,0x02,0x08,0x00,0x00]
+0x7e,0x00,0xa8,0xd4,0x02,0x08,0x00,0x00
+
+# GFX12: v_cmpx_u_f64_e64 s[104:105], s[104:105] ; encoding: [0x7e,0x00,0xa8,0xd4,0x68,0xd0,0x00,0x00]
+0x7e,0x00,0xa8,0xd4,0x68,0xd0,0x00,0x00
+
+# GFX12: v_cmpx_u_f64_e64 vcc, ttmp[14:15]       ; encoding: [0x7e,0x00,0xa8,0xd4,0x6a,0xf4,0x00,0x00]
+0x7e,0x00,0xa8,0xd4,0x6a,0xf4,0x00,0x00
+
+# GFX12: v_cmpx_u_f64_e64 ttmp[14:15], 0xaf123456 ; encoding: [0x7e,0x00,0xa8,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0xa8,0xd4,0x7a,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_u_f64_e64 -|exec|, src_scc       ; encoding: [0x7e,0x01,0xa8,0xd4,0x7e,0xfa,0x01,0x20]
+0x7e,0x01,0xa8,0xd4,0x7e,0xfa,0x01,0x20
+
+# GFX12: v_cmpx_u_f64_e64 null, 0.5              ; encoding: [0x7e,0x00,0xa8,0xd4,0x7c,0xe0,0x01,0x00]
+0x7e,0x00,0xa8,0xd4,0x7c,0xe0,0x01,0x00
+
+# GFX12: v_cmpx_u_f64_e64 -1, -1                 ; encoding: [0x7e,0x00,0xa8,0xd4,0xc1,0x82,0x01,0x00]
+0x7e,0x00,0xa8,0xd4,0xc1,0x82,0x01,0x00
+
+# GFX12: v_cmpx_u_f64_e64 0.5, null              ; encoding: [0x7e,0x00,0xa8,0xd4,0xf0,0xf8,0x00,0x00]
+0x7e,0x00,0xa8,0xd4,0xf0,0xf8,0x00,0x00
+
+# GFX12: v_cmpx_u_f64_e64 -|src_scc|, -|exec|    ; encoding: [0x7e,0x03,0xa8,0xd4,0xfd,0xfc,0x00,0x60]
+0x7e,0x03,0xa8,0xd4,0xfd,0xfc,0x00,0x60
+
+# GFX12: v_cmpx_u_f64_e64 0xaf123456, -|vcc| clamp ; encoding: [0x7e,0x82,0xa8,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf]
+0x7e,0x82,0xa8,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp16.txt
new file mode 100644
index 000000000000..77888c0e1553
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp16.txt
@@ -0,0 +1,2278 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12 %s
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12 %s
+
+# GFX12: v_cmpx_class_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_class_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_class_f16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_class_f16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_class_f16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_class_f16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_class_f16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_class_f16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_class_f16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_class_f16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_class_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_class_f16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_class_f16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_class_f16_e64_dpp -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x01,0xfd,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30]
+0x7e,0x01,0xfd,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_class_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_class_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_class_f32_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_class_f32_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_class_f32_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_class_f32_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_class_f32_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_class_f32_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_class_f32_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_class_f32_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_class_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_class_f32_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_class_f32_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_class_f32_e64_dpp -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x01,0xfe,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30]
+0x7e,0x01,0xfe,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_eq_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_eq_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_eq_f16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_eq_f16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_eq_f16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_eq_f16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_eq_f16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_eq_f16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_eq_f16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_eq_f16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_eq_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0x82,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_eq_f16_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x01,0x82,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x7e,0x01,0x82,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_eq_f16_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x02,0x82,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7e,0x02,0x82,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_eq_f16_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x83,0x82,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7e,0x83,0x82,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_eq_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_eq_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_eq_f32_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_eq_f32_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_eq_f32_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_eq_f32_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_eq_f32_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_eq_f32_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_eq_f32_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_eq_f32_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_eq_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0x92,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_eq_f32_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x01,0x92,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x7e,0x01,0x92,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_eq_f32_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x02,0x92,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7e,0x02,0x92,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_eq_f32_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x83,0x92,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7e,0x83,0x92,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_eq_i16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_eq_i16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_eq_i16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_eq_i16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_eq_i16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_eq_i16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_eq_i16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_eq_i16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_eq_i16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_eq_i16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_eq_i16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_eq_i16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_eq_i16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7e,0x00,0xb2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_eq_i16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x00,0xb2,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7e,0x00,0xb2,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_eq_i32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_eq_i32_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_eq_i32_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_eq_i32_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_eq_i32_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_eq_i32_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_eq_i32_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_eq_i32_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_eq_i32_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_eq_i32_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_eq_i32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_eq_i32_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_eq_i32_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7e,0x00,0xc2,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_eq_i32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x00,0xc2,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7e,0x00,0xc2,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_eq_u16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_eq_u16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_eq_u16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_eq_u16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_eq_u16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_eq_u16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_eq_u16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_eq_u16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_eq_u16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_eq_u16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_eq_u16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_eq_u16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_eq_u16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7e,0x00,0xba,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_eq_u16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x00,0xba,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7e,0x00,0xba,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_eq_u32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_eq_u32_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_eq_u32_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_eq_u32_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_eq_u32_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_eq_u32_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_eq_u32_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_eq_u32_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_eq_u32_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_eq_u32_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_eq_u32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_eq_u32_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_eq_u32_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7e,0x00,0xca,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_eq_u32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x00,0xca,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7e,0x00,0xca,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_ge_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_ge_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_ge_f16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_ge_f16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_ge_f16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_ge_f16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_ge_f16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_ge_f16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_ge_f16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_ge_f16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_ge_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0x86,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_ge_f16_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x01,0x86,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x7e,0x01,0x86,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_ge_f16_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x02,0x86,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7e,0x02,0x86,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_ge_f16_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x83,0x86,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7e,0x83,0x86,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_ge_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_ge_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_ge_f32_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_ge_f32_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_ge_f32_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_ge_f32_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_ge_f32_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_ge_f32_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_ge_f32_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_ge_f32_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_ge_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0x96,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_ge_f32_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x01,0x96,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x7e,0x01,0x96,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_ge_f32_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x02,0x96,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7e,0x02,0x96,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_ge_f32_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x83,0x96,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7e,0x83,0x96,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_ge_i16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_ge_i16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_ge_i16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_ge_i16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_ge_i16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_ge_i16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_ge_i16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_ge_i16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_ge_i16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_ge_i16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_ge_i16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_ge_i16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_ge_i16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7e,0x00,0xb6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_ge_i16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x00,0xb6,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7e,0x00,0xb6,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_ge_i32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_ge_i32_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_ge_i32_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_ge_i32_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_ge_i32_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_ge_i32_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_ge_i32_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_ge_i32_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_ge_i32_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_ge_i32_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_ge_i32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_ge_i32_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_ge_i32_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7e,0x00,0xc6,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_ge_i32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x00,0xc6,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7e,0x00,0xc6,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_ge_u16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_ge_u16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_ge_u16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_ge_u16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_ge_u16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_ge_u16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_ge_u16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_ge_u16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_ge_u16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_ge_u16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_ge_u16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_ge_u16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_ge_u16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7e,0x00,0xbe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_ge_u16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x00,0xbe,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7e,0x00,0xbe,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_ge_u32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_ge_u32_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_ge_u32_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_ge_u32_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_ge_u32_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_ge_u32_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_ge_u32_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_ge_u32_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_ge_u32_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_ge_u32_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_ge_u32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_ge_u32_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_ge_u32_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7e,0x00,0xce,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_ge_u32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x00,0xce,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7e,0x00,0xce,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_gt_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_gt_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_gt_f16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_gt_f16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_gt_f16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_gt_f16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_gt_f16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_gt_f16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_gt_f16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_gt_f16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_gt_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0x84,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_gt_f16_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x01,0x84,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x7e,0x01,0x84,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_gt_f16_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x02,0x84,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7e,0x02,0x84,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_gt_f16_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x83,0x84,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7e,0x83,0x84,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_gt_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_gt_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_gt_f32_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_gt_f32_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_gt_f32_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_gt_f32_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_gt_f32_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_gt_f32_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_gt_f32_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_gt_f32_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_gt_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0x94,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_gt_f32_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x01,0x94,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x7e,0x01,0x94,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_gt_f32_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x02,0x94,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7e,0x02,0x94,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_gt_f32_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x83,0x94,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7e,0x83,0x94,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_gt_i16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_gt_i16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_gt_i16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_gt_i16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_gt_i16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_gt_i16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_gt_i16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_gt_i16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_gt_i16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_gt_i16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_gt_i16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_gt_i16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_gt_i16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7e,0x00,0xb4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_gt_i16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x00,0xb4,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7e,0x00,0xb4,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_gt_i32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_gt_i32_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_gt_i32_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_gt_i32_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_gt_i32_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_gt_i32_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_gt_i32_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_gt_i32_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_gt_i32_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_gt_i32_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_gt_i32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_gt_i32_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_gt_i32_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7e,0x00,0xc4,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_gt_i32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x00,0xc4,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7e,0x00,0xc4,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_gt_u16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_gt_u16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_gt_u16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_gt_u16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_gt_u16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_gt_u16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_gt_u16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_gt_u16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_gt_u16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_gt_u16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_gt_u16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_gt_u16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_gt_u16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7e,0x00,0xbc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_gt_u16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x00,0xbc,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7e,0x00,0xbc,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_gt_u32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_gt_u32_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_gt_u32_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_gt_u32_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_gt_u32_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_gt_u32_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_gt_u32_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_gt_u32_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_gt_u32_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_gt_u32_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_gt_u32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_gt_u32_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_gt_u32_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7e,0x00,0xcc,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_gt_u32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x00,0xcc,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7e,0x00,0xcc,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_le_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_le_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_le_f16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_le_f16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_le_f16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_le_f16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_le_f16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_le_f16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_le_f16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_le_f16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_le_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0x83,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_le_f16_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x01,0x83,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x7e,0x01,0x83,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_le_f16_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x02,0x83,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7e,0x02,0x83,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_le_f16_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x83,0x83,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7e,0x83,0x83,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_le_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_le_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_le_f32_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_le_f32_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_le_f32_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_le_f32_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_le_f32_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_le_f32_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_le_f32_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_le_f32_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_le_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0x93,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_le_f32_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x01,0x93,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x7e,0x01,0x93,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_le_f32_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x02,0x93,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7e,0x02,0x93,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_le_f32_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x83,0x93,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7e,0x83,0x93,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_le_i16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_le_i16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_le_i16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_le_i16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_le_i16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_le_i16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_le_i16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_le_i16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_le_i16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_le_i16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_le_i16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_le_i16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_le_i16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7e,0x00,0xb3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_le_i16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x00,0xb3,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7e,0x00,0xb3,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_le_i32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_le_i32_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_le_i32_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_le_i32_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_le_i32_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_le_i32_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_le_i32_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_le_i32_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_le_i32_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_le_i32_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_le_i32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_le_i32_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_le_i32_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7e,0x00,0xc3,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_le_i32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x00,0xc3,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7e,0x00,0xc3,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_le_u16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_le_u16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_le_u16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_le_u16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_le_u16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_le_u16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_le_u16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_le_u16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_le_u16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_le_u16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_le_u16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_le_u16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_le_u16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7e,0x00,0xbb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_le_u16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x00,0xbb,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7e,0x00,0xbb,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_le_u32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_le_u32_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_le_u32_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_le_u32_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_le_u32_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_le_u32_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_le_u32_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_le_u32_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_le_u32_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_le_u32_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_le_u32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_le_u32_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_le_u32_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7e,0x00,0xcb,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_le_u32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x00,0xcb,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7e,0x00,0xcb,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_lg_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_lg_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_lg_f16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_lg_f16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_lg_f16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_lg_f16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_lg_f16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_lg_f16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_lg_f16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_lg_f16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_lg_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0x85,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_lg_f16_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x01,0x85,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x7e,0x01,0x85,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_lg_f16_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x02,0x85,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7e,0x02,0x85,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_lg_f16_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x83,0x85,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7e,0x83,0x85,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_lg_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_lg_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_lg_f32_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_lg_f32_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_lg_f32_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_lg_f32_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_lg_f32_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_lg_f32_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_lg_f32_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_lg_f32_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_lg_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0x95,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_lg_f32_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x01,0x95,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x7e,0x01,0x95,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_lg_f32_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x02,0x95,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7e,0x02,0x95,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_lg_f32_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x83,0x95,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7e,0x83,0x95,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_lt_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_lt_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_lt_f16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_lt_f16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_lt_f16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_lt_f16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_lt_f16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_lt_f16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_lt_f16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_lt_f16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_lt_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0x81,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_lt_f16_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x01,0x81,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x7e,0x01,0x81,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_lt_f16_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x02,0x81,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7e,0x02,0x81,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_lt_f16_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x83,0x81,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7e,0x83,0x81,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_lt_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_lt_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_lt_f32_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_lt_f32_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_lt_f32_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_lt_f32_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_lt_f32_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_lt_f32_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_lt_f32_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_lt_f32_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_lt_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0x91,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_lt_f32_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x01,0x91,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x7e,0x01,0x91,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_lt_f32_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x02,0x91,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7e,0x02,0x91,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_lt_f32_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x83,0x91,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7e,0x83,0x91,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_lt_i16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_lt_i16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_lt_i16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_lt_i16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_lt_i16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_lt_i16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_lt_i16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_lt_i16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_lt_i16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_lt_i16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_lt_i16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_lt_i16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_lt_i16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7e,0x00,0xb1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_lt_i16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x00,0xb1,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7e,0x00,0xb1,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_lt_i32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_lt_i32_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_lt_i32_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_lt_i32_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_lt_i32_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_lt_i32_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_lt_i32_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_lt_i32_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_lt_i32_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_lt_i32_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_lt_i32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_lt_i32_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_lt_i32_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7e,0x00,0xc1,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_lt_i32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x00,0xc1,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7e,0x00,0xc1,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_lt_u16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_lt_u16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_lt_u16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_lt_u16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_lt_u16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_lt_u16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_lt_u16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_lt_u16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_lt_u16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_lt_u16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_lt_u16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_lt_u16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_lt_u16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7e,0x00,0xb9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_lt_u16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x00,0xb9,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7e,0x00,0xb9,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_lt_u32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_lt_u32_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_lt_u32_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_lt_u32_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_lt_u32_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_lt_u32_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_lt_u32_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_lt_u32_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_lt_u32_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_lt_u32_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_lt_u32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_lt_u32_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_lt_u32_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7e,0x00,0xc9,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_lt_u32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x00,0xc9,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7e,0x00,0xc9,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_ne_i16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_ne_i16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_ne_i16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_ne_i16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_ne_i16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_ne_i16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_ne_i16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_ne_i16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_ne_i16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_ne_i16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_ne_i16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_ne_i16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_ne_i16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7e,0x00,0xb5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_ne_i16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x00,0xb5,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7e,0x00,0xb5,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_ne_i32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_ne_i32_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_ne_i32_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_ne_i32_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_ne_i32_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_ne_i32_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_ne_i32_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_ne_i32_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_ne_i32_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_ne_i32_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_ne_i32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_ne_i32_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_ne_i32_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7e,0x00,0xc5,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_ne_i32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x00,0xc5,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7e,0x00,0xc5,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_ne_u16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_ne_u16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_ne_u16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_ne_u16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_ne_u16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_ne_u16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_ne_u16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_ne_u16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_ne_u16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_ne_u16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_ne_u16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_ne_u16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_ne_u16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7e,0x00,0xbd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_ne_u16_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x00,0xbd,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7e,0x00,0xbd,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_ne_u32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_ne_u32_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_ne_u32_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_ne_u32_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_ne_u32_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_ne_u32_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_ne_u32_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_ne_u32_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_ne_u32_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_ne_u32_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_ne_u32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_ne_u32_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_ne_u32_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7e,0x00,0xcd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_ne_u32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x00,0xcd,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
+0x7e,0x00,0xcd,0xd4,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_neq_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_neq_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_neq_f16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_neq_f16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_neq_f16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_neq_f16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_neq_f16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_neq_f16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_neq_f16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_neq_f16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_neq_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0x8d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_neq_f16_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x01,0x8d,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x7e,0x01,0x8d,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_neq_f16_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x02,0x8d,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7e,0x02,0x8d,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_neq_f16_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x83,0x8d,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7e,0x83,0x8d,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_neq_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_neq_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_neq_f32_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_neq_f32_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_neq_f32_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_neq_f32_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_neq_f32_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_neq_f32_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_neq_f32_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_neq_f32_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_neq_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0x9d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_neq_f32_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x01,0x9d,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x7e,0x01,0x9d,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_neq_f32_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x02,0x9d,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7e,0x02,0x9d,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_neq_f32_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x83,0x9d,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7e,0x83,0x9d,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_nge_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_nge_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_nge_f16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_nge_f16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_nge_f16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_nge_f16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_nge_f16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_nge_f16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_nge_f16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_nge_f16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_nge_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0x89,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_nge_f16_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x01,0x89,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x7e,0x01,0x89,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_nge_f16_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x02,0x89,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7e,0x02,0x89,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_nge_f16_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x83,0x89,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7e,0x83,0x89,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_nge_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_nge_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_nge_f32_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_nge_f32_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_nge_f32_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_nge_f32_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_nge_f32_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_nge_f32_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_nge_f32_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_nge_f32_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_nge_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0x99,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_nge_f32_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x01,0x99,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x7e,0x01,0x99,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_nge_f32_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x02,0x99,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7e,0x02,0x99,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_nge_f32_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x83,0x99,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7e,0x83,0x99,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_ngt_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_ngt_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_ngt_f16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0x8b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f16_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x01,0x8b,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x7e,0x01,0x8b,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_ngt_f16_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x02,0x8b,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7e,0x02,0x8b,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_ngt_f16_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x83,0x8b,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7e,0x83,0x8b,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_ngt_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_ngt_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_ngt_f32_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f32_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f32_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f32_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f32_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f32_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f32_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f32_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0x9b,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f32_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x01,0x9b,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x7e,0x01,0x9b,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_ngt_f32_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x02,0x9b,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7e,0x02,0x9b,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_ngt_f32_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x83,0x9b,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7e,0x83,0x9b,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_nle_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_nle_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_nle_f16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_nle_f16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_nle_f16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_nle_f16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_nle_f16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_nle_f16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_nle_f16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_nle_f16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_nle_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0x8c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_nle_f16_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x01,0x8c,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x7e,0x01,0x8c,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_nle_f16_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x02,0x8c,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7e,0x02,0x8c,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_nle_f16_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x83,0x8c,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7e,0x83,0x8c,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_nle_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_nle_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_nle_f32_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_nle_f32_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_nle_f32_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_nle_f32_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_nle_f32_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_nle_f32_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_nle_f32_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_nle_f32_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_nle_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0x9c,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_nle_f32_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x01,0x9c,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x7e,0x01,0x9c,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_nle_f32_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x02,0x9c,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7e,0x02,0x9c,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_nle_f32_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x83,0x9c,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7e,0x83,0x9c,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_nlg_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_nlg_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_nlg_f16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0x8a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f16_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x01,0x8a,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x7e,0x01,0x8a,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_nlg_f16_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x02,0x8a,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7e,0x02,0x8a,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_nlg_f16_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x83,0x8a,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7e,0x83,0x8a,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_nlg_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_nlg_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_nlg_f32_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f32_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f32_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f32_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f32_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f32_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f32_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f32_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0x9a,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f32_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x01,0x9a,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x7e,0x01,0x9a,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_nlg_f32_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x02,0x9a,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7e,0x02,0x9a,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_nlg_f32_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x83,0x9a,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7e,0x83,0x9a,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_nlt_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_nlt_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_nlt_f16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0x8e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f16_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x01,0x8e,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x7e,0x01,0x8e,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_nlt_f16_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x02,0x8e,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7e,0x02,0x8e,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_nlt_f16_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x83,0x8e,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7e,0x83,0x8e,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_nlt_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_nlt_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_nlt_f32_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f32_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f32_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f32_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f32_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f32_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f32_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f32_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0x9e,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f32_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x01,0x9e,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x7e,0x01,0x9e,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_nlt_f32_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x02,0x9e,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7e,0x02,0x9e,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_nlt_f32_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x83,0x9e,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7e,0x83,0x9e,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_o_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_o_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_o_f16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_o_f16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_o_f16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_o_f16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_o_f16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_o_f16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_o_f16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_o_f16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_o_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0x87,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_o_f16_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x01,0x87,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x7e,0x01,0x87,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_o_f16_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x02,0x87,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7e,0x02,0x87,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_o_f16_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x83,0x87,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7e,0x83,0x87,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_o_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_o_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_o_f32_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_o_f32_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_o_f32_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_o_f32_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_o_f32_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_o_f32_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_o_f32_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_o_f32_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_o_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0x97,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_o_f32_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x01,0x97,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x7e,0x01,0x97,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_o_f32_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x02,0x97,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7e,0x02,0x97,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_o_f32_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x83,0x97,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7e,0x83,0x97,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_u_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_u_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_u_f16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_u_f16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_u_f16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_u_f16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_u_f16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_u_f16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_u_f16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_u_f16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_u_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0x88,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_u_f16_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x01,0x88,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x7e,0x01,0x88,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_u_f16_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x02,0x88,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7e,0x02,0x88,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_u_f16_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x83,0x88,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7e,0x83,0x88,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_u_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_u_f32_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_u_f32_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_u_f32_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_u_f32_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_u_f32_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_u_f32_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_u_f32_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_u_f32_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_u_f32_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_u_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_u_f32_e64_dpp |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x01,0x98,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+0x7e,0x01,0x98,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_u_f32_e64_dpp -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x02,0x98,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+0x7e,0x02,0x98,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_u_f32_e64_dpp -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x83,0x98,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+0x7e,0x83,0x98,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+
+# Check that dst value does not affect disassembly
+# GFX12: v_cmpx_u_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0x00,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
+
+# Check that dst value does not affect disassembly
+# GFX12: v_cmpx_u_f32_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+0xff,0x00,0x98,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp8.txt
new file mode 100644
index 000000000000..11972f4ba655
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp8.txt
@@ -0,0 +1,502 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12 %s
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12 %s
+
+# GFX12: v_cmpx_class_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xfd,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0xfd,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_class_f16_e64_dpp -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x01,0xfd,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00]
+0x7e,0x01,0xfd,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_class_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xfe,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0xfe,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_class_f32_e64_dpp -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x01,0xfe,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00]
+0x7e,0x01,0xfe,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_eq_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x82,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0x82,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_eq_f16_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x01,0x82,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x7e,0x01,0x82,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_eq_f16_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x02,0x82,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7e,0x02,0x82,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_eq_f16_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x83,0x82,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7e,0x83,0x82,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_eq_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x92,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0x92,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_eq_f32_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x01,0x92,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x7e,0x01,0x92,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_eq_f32_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x02,0x92,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7e,0x02,0x92,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_eq_f32_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x83,0x92,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7e,0x83,0x92,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_eq_i16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xb2,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0xb2,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_eq_i16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x00,0xb2,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7e,0x00,0xb2,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_eq_i32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xc2,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0xc2,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_eq_i32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x00,0xc2,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7e,0x00,0xc2,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_eq_u16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xba,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0xba,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_eq_u16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x00,0xba,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7e,0x00,0xba,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_eq_u32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xca,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0xca,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_eq_u32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x00,0xca,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7e,0x00,0xca,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_ge_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x86,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0x86,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ge_f16_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x01,0x86,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x7e,0x01,0x86,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ge_f16_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x02,0x86,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7e,0x02,0x86,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ge_f16_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x83,0x86,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7e,0x83,0x86,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_ge_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x96,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0x96,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ge_f32_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x01,0x96,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x7e,0x01,0x96,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ge_f32_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x02,0x96,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7e,0x02,0x96,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ge_f32_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x83,0x96,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7e,0x83,0x96,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_ge_i16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xb6,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0xb6,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ge_i16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x00,0xb6,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7e,0x00,0xb6,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_ge_i32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xc6,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0xc6,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ge_i32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x00,0xc6,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7e,0x00,0xc6,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_ge_u16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xbe,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0xbe,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ge_u16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x00,0xbe,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7e,0x00,0xbe,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_ge_u32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xce,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0xce,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ge_u32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x00,0xce,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7e,0x00,0xce,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_gt_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x84,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0x84,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_gt_f16_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x01,0x84,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x7e,0x01,0x84,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_gt_f16_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x02,0x84,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7e,0x02,0x84,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_gt_f16_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x83,0x84,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7e,0x83,0x84,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_gt_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x94,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0x94,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_gt_f32_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x01,0x94,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x7e,0x01,0x94,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_gt_f32_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x02,0x94,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7e,0x02,0x94,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_gt_f32_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x83,0x94,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7e,0x83,0x94,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_gt_i16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xb4,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0xb4,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_gt_i16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x00,0xb4,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7e,0x00,0xb4,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_gt_i32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xc4,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0xc4,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_gt_i32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x00,0xc4,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7e,0x00,0xc4,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_gt_u16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xbc,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0xbc,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_gt_u16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x00,0xbc,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7e,0x00,0xbc,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_gt_u32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xcc,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0xcc,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_gt_u32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x00,0xcc,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7e,0x00,0xcc,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_le_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x83,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0x83,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_le_f16_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x01,0x83,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x7e,0x01,0x83,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_le_f16_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x02,0x83,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7e,0x02,0x83,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_le_f16_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x83,0x83,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7e,0x83,0x83,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_le_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x93,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0x93,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_le_f32_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x01,0x93,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x7e,0x01,0x93,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_le_f32_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x02,0x93,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7e,0x02,0x93,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_le_f32_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x83,0x93,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7e,0x83,0x93,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_le_i16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xb3,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0xb3,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_le_i16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x00,0xb3,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7e,0x00,0xb3,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_le_i32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xc3,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0xc3,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_le_i32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x00,0xc3,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7e,0x00,0xc3,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_le_u16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xbb,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0xbb,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_le_u16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x00,0xbb,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7e,0x00,0xbb,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_le_u32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xcb,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0xcb,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_le_u32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x00,0xcb,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7e,0x00,0xcb,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_lg_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x85,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0x85,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_lg_f16_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x01,0x85,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x7e,0x01,0x85,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_lg_f16_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x02,0x85,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7e,0x02,0x85,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_lg_f16_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x83,0x85,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7e,0x83,0x85,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_lg_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x95,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0x95,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_lg_f32_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x01,0x95,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x7e,0x01,0x95,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_lg_f32_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x02,0x95,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7e,0x02,0x95,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_lg_f32_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x83,0x95,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7e,0x83,0x95,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_lt_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x81,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0x81,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_lt_f16_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x01,0x81,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x7e,0x01,0x81,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_lt_f16_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x02,0x81,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7e,0x02,0x81,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_lt_f16_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x83,0x81,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7e,0x83,0x81,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_lt_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x91,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0x91,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_lt_f32_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x01,0x91,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x7e,0x01,0x91,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_lt_f32_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x02,0x91,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7e,0x02,0x91,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_lt_f32_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x83,0x91,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7e,0x83,0x91,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_lt_i16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xb1,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0xb1,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_lt_i16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x00,0xb1,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7e,0x00,0xb1,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_lt_i32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xc1,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0xc1,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_lt_i32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x00,0xc1,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7e,0x00,0xc1,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_lt_u16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xb9,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0xb9,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_lt_u16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x00,0xb9,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7e,0x00,0xb9,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_lt_u32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xc9,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0xc9,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_lt_u32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x00,0xc9,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7e,0x00,0xc9,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_ne_i16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xb5,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0xb5,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ne_i16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x00,0xb5,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7e,0x00,0xb5,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_ne_i32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xc5,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0xc5,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ne_i32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x00,0xc5,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7e,0x00,0xc5,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_ne_u16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xbd,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0xbd,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ne_u16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x00,0xbd,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7e,0x00,0xbd,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_ne_u32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xcd,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0xcd,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ne_u32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x00,0xcd,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+0x7e,0x00,0xcd,0xd4,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_neq_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x8d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0x8d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_neq_f16_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x01,0x8d,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x7e,0x01,0x8d,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_neq_f16_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x02,0x8d,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7e,0x02,0x8d,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_neq_f16_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x83,0x8d,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7e,0x83,0x8d,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_neq_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x9d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0x9d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_neq_f32_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x01,0x9d,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x7e,0x01,0x9d,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_neq_f32_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x02,0x9d,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7e,0x02,0x9d,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_neq_f32_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x83,0x9d,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7e,0x83,0x9d,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_nge_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x89,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0x89,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nge_f16_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x01,0x89,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x7e,0x01,0x89,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nge_f16_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x02,0x89,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7e,0x02,0x89,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nge_f16_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x83,0x89,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7e,0x83,0x89,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_nge_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x99,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0x99,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nge_f32_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x01,0x99,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x7e,0x01,0x99,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nge_f32_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x02,0x99,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7e,0x02,0x99,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nge_f32_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x83,0x99,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7e,0x83,0x99,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_ngt_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x8b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0x8b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ngt_f16_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x01,0x8b,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x7e,0x01,0x8b,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ngt_f16_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x02,0x8b,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7e,0x02,0x8b,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ngt_f16_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x83,0x8b,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7e,0x83,0x8b,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_ngt_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x9b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0x9b,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ngt_f32_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x01,0x9b,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x7e,0x01,0x9b,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ngt_f32_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x02,0x9b,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7e,0x02,0x9b,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ngt_f32_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x83,0x9b,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7e,0x83,0x9b,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_nle_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x8c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0x8c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nle_f16_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x01,0x8c,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x7e,0x01,0x8c,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nle_f16_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x02,0x8c,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7e,0x02,0x8c,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nle_f16_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x83,0x8c,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7e,0x83,0x8c,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_nle_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x9c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0x9c,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nle_f32_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x01,0x9c,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x7e,0x01,0x9c,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nle_f32_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x02,0x9c,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7e,0x02,0x9c,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nle_f32_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x83,0x9c,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7e,0x83,0x9c,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_nlg_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x8a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0x8a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nlg_f16_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x01,0x8a,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x7e,0x01,0x8a,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nlg_f16_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x02,0x8a,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7e,0x02,0x8a,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nlg_f16_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x83,0x8a,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7e,0x83,0x8a,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_nlg_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x9a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0x9a,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nlg_f32_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x01,0x9a,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x7e,0x01,0x9a,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nlg_f32_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x02,0x9a,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7e,0x02,0x9a,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nlg_f32_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x83,0x9a,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7e,0x83,0x9a,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_nlt_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x8e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0x8e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nlt_f16_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x01,0x8e,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x7e,0x01,0x8e,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nlt_f16_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x02,0x8e,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7e,0x02,0x8e,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nlt_f16_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x83,0x8e,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7e,0x83,0x8e,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_nlt_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x9e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0x9e,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nlt_f32_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x01,0x9e,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x7e,0x01,0x9e,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nlt_f32_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x02,0x9e,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7e,0x02,0x9e,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nlt_f32_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x83,0x9e,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7e,0x83,0x9e,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_o_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x87,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0x87,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_o_f16_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x01,0x87,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x7e,0x01,0x87,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_o_f16_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x02,0x87,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7e,0x02,0x87,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_o_f16_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x83,0x87,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7e,0x83,0x87,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_o_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x97,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0x97,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_o_f32_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x01,0x97,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x7e,0x01,0x97,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_o_f32_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x02,0x97,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7e,0x02,0x97,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_o_f32_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x83,0x97,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7e,0x83,0x97,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_u_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x88,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0x88,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_u_f16_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x01,0x88,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x7e,0x01,0x88,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_u_f16_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x02,0x88,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7e,0x02,0x88,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_u_f16_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x83,0x88,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7e,0x83,0x88,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_u_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x98,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x00,0x98,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_u_f32_e64_dpp |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x01,0x98,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+0x7e,0x01,0x98,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_u_f32_e64_dpp -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x02,0x98,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+0x7e,0x02,0x98,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_u_f32_e64_dpp -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x83,0x98,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+0x7e,0x83,0x98,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+
+# Check that dst value does not affect disassembly
+# GFX12: v_cmpx_u_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x98,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x00,0x00,0x98,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# Check that dst value does not affect disassembly
+# GFX12: v_cmpx_u_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0x98,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0xff,0x00,0x98,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p.txt
new file mode 100644
index 000000000000..d07516b21cc6
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p.txt
@@ -0,0 +1,1253 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX12 %s
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX12 %s
+
+# GFX12: v_dot2_f32_bf16 v5, v1, v2, v3          ; encoding: [0x05,0x40,0x1a,0xcc,0x01,0x05,0x0e,0x1c]
+0x05,0x40,0x1a,0xcc,0x01,0x05,0x0e,0x1c
+
+# GFX12: v_dot2_f32_bf16 v5, v1, v2, s3          ; encoding: [0x05,0x40,0x1a,0xcc,0x01,0x05,0x0e,0x18]
+0x05,0x40,0x1a,0xcc,0x01,0x05,0x0e,0x18
+
+# GFX12: v_dot2_f32_bf16 v5, v255, v255, s105    ; encoding: [0x05,0x40,0x1a,0xcc,0xff,0xff,0xa7,0x19]
+0x05,0x40,0x1a,0xcc,0xff,0xff,0xa7,0x19
+
+# GFX12: v_dot2_f32_bf16 v5, s1, s2, v255        ; encoding: [0x05,0x40,0x1a,0xcc,0x01,0x04,0xfc,0x1f]
+0x05,0x40,0x1a,0xcc,0x01,0x04,0xfc,0x1f
+
+# GFX12: v_dot2_f32_bf16 v5, s105, s105, m0      ; encoding: [0x05,0x40,0x1a,0xcc,0x69,0xd2,0xf4,0x19]
+0x05,0x40,0x1a,0xcc,0x69,0xd2,0xf4,0x19
+
+# GFX12: v_dot2_f32_bf16 v5, vcc_lo, ttmp15, vcc_lo ; encoding: [0x05,0x40,0x1a,0xcc,0x6a,0xf6,0xa8,0x19]
+0x05,0x40,0x1a,0xcc,0x6a,0xf6,0xa8,0x19
+
+# GFX12: v_dot2_f32_bf16 v5, vcc_hi, 0xfe0b, vcc_hi ; encoding: [0x05,0x40,0x1a,0xcc,0x6b,0xfe,0xad,0x19,0x0b,0xfe,0x00,0x00]
+0x05,0x40,0x1a,0xcc,0x6b,0xfe,0xad,0x19,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_dot2_f32_bf16 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x40,0x1a,0xcc,0x7b,0xfa,0xed,0x19]
+0x05,0x40,0x1a,0xcc,0x7b,0xfa,0xed,0x19
+
+# GFX12: v_dot2_f32_bf16 v5, m0, -1, exec_hi     ; encoding: [0x05,0x40,0x1a,0xcc,0x7d,0x82,0xfd,0x19]
+0x05,0x40,0x1a,0xcc,0x7d,0x82,0xfd,0x19
+
+# GFX12: v_dot2_f32_bf16 v5, exec_lo, null, exec_lo ; encoding: [0x05,0x40,0x1a,0xcc,0x7e,0xf8,0xf8,0x19]
+0x05,0x40,0x1a,0xcc,0x7e,0xf8,0xf8,0x19
+
+# GFX12: v_dot2_f32_bf16 v5, exec_hi, exec_lo, null ; encoding: [0x05,0x40,0x1a,0xcc,0x7f,0xfc,0xf0,0x19]
+0x05,0x40,0x1a,0xcc,0x7f,0xfc,0xf0,0x19
+
+# GFX12: v_dot2_f32_bf16 v5, null, exec_hi, -1   ; encoding: [0x05,0x40,0x1a,0xcc,0x7c,0xfe,0x04,0x1b]
+0x05,0x40,0x1a,0xcc,0x7c,0xfe,0x04,0x1b
+
+# GFX12: v_dot2_f32_bf16 v5, -1, m0, 0xaf123456  ; encoding: [0x05,0x40,0x1a,0xcc,0xc1,0xfa,0xfc,0x1b,0x56,0x34,0x12,0xaf]
+0x05,0x40,0x1a,0xcc,0xc1,0xfa,0xfc,0x1b,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dot2_f32_bf16 v5, src_scc, vcc_lo, src_scc ; encoding: [0x05,0x40,0x1a,0xcc,0xfd,0xd4,0xf4,0x1b]
+0x05,0x40,0x1a,0xcc,0xfd,0xd4,0xf4,0x1b
+
+# GFX12: v_dot2_f32_bf16 v255, 0xfe0b, vcc_hi, 0.5 neg_lo:[1,0,0] neg_hi:[1,0,0] clamp ; encoding: [0xff,0xc1,0x1a,0xcc,0xff,0xd6,0xc0,0x3b,0x0b,0xfe,0x00,0x00]
+0xff,0xc1,0x1a,0xcc,0xff,0xd6,0xc0,0x3b,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_dot2_f32_f16 v5, v1, v2, s3           ; encoding: [0x05,0x40,0x13,0xcc,0x01,0x05,0x0e,0x18]
+0x05,0x40,0x13,0xcc,0x01,0x05,0x0e,0x18
+
+# GFX12: v_dot2_f32_f16 v5, v255, s2, s105       ; encoding: [0x05,0x40,0x13,0xcc,0xff,0x05,0xa4,0x19]
+0x05,0x40,0x13,0xcc,0xff,0x05,0xa4,0x19
+
+# GFX12: v_dot2_f32_f16 v5, s1, v255, exec_hi    ; encoding: [0x05,0x40,0x13,0xcc,0x01,0xfe,0xff,0x19]
+0x05,0x40,0x13,0xcc,0x01,0xfe,0xff,0x19
+
+# GFX12: v_dot2_f32_f16 v5, s105, s105, exec_lo  ; encoding: [0x05,0x40,0x13,0xcc,0x69,0xd2,0xf8,0x19]
+0x05,0x40,0x13,0xcc,0x69,0xd2,0xf8,0x19
+
+# GFX12: v_dot2_f32_f16 v5, vcc_lo, ttmp15, v3   ; encoding: [0x05,0x40,0x13,0xcc,0x6a,0xf6,0x0c,0x1c]
+0x05,0x40,0x13,0xcc,0x6a,0xf6,0x0c,0x1c
+
+# GFX12: v_dot2_f32_f16 v5, vcc_hi, 0xfe0b, v255 ; encoding: [0x05,0x40,0x13,0xcc,0x6b,0xfe,0xfd,0x1f,0x0b,0xfe,0x00,0x00]
+0x05,0x40,0x13,0xcc,0x6b,0xfe,0xfd,0x1f,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_dot2_f32_f16 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x40,0x13,0xcc,0x7b,0xfa,0xed,0x19]
+0x05,0x40,0x13,0xcc,0x7b,0xfa,0xed,0x19
+
+# GFX12: v_dot2_f32_f16 v5, m0, 0.5, m0          ; encoding: [0x05,0x40,0x13,0xcc,0x7d,0xe0,0xf5,0x19]
+0x05,0x40,0x13,0xcc,0x7d,0xe0,0xf5,0x19
+
+# GFX12: v_dot2_f32_f16 v5, exec_lo, -1, vcc_hi  ; encoding: [0x05,0x40,0x13,0xcc,0x7e,0x82,0xad,0x19]
+0x05,0x40,0x13,0xcc,0x7e,0x82,0xad,0x19
+
+# GFX12: v_dot2_f32_f16 v5, exec_hi, null, vcc_lo ; encoding: [0x05,0x40,0x13,0xcc,0x7f,0xf8,0xa8,0x19]
+0x05,0x40,0x13,0xcc,0x7f,0xf8,0xa8,0x19
+
+# GFX12: v_dot2_f32_f16 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x40,0x13,0xcc,0x7c,0xfc,0xfc,0x1b,0x56,0x34,0x12,0xaf]
+0x05,0x40,0x13,0xcc,0x7c,0xfc,0xfc,0x1b,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dot2_f32_f16 v5, -1, exec_hi, src_scc ; encoding: [0x05,0x40,0x13,0xcc,0xc1,0xfe,0xf4,0x1b]
+0x05,0x40,0x13,0xcc,0xc1,0xfe,0xf4,0x1b
+
+# GFX12: v_dot2_f32_f16 v5, 0.5, m0, 0.5         ; encoding: [0x05,0x40,0x13,0xcc,0xf0,0xfa,0xc0,0x1b]
+0x05,0x40,0x13,0xcc,0xf0,0xfa,0xc0,0x1b
+
+# GFX12: v_dot2_f32_f16 v5, src_scc, vcc_lo, -1 neg_lo:[1,0,0] neg_hi:[1,0,0] ; encoding: [0x05,0x41,0x13,0xcc,0xfd,0xd4,0x04,0x3b]
+0x05,0x41,0x13,0xcc,0xfd,0xd4,0x04,0x3b
+
+# GFX12: v_dot2_f32_f16 v255, 0xfe0b, vcc_hi, null neg_lo:[0,1,0] neg_hi:[0,1,0] clamp ; encoding: [0xff,0xc2,0x13,0xcc,0xff,0xd6,0xf0,0x59,0x0b,0xfe,0x00,0x00]
+0xff,0xc2,0x13,0xcc,0xff,0xd6,0xf0,0x59,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_dot4_i32_iu8 v5, v1, v2, s3           ; encoding: [0x05,0x40,0x16,0xcc,0x01,0x05,0x0e,0x18]
+0x05,0x40,0x16,0xcc,0x01,0x05,0x0e,0x18
+
+# GFX12: v_dot4_i32_iu8 v5, v255, s2, s105       ; encoding: [0x05,0x40,0x16,0xcc,0xff,0x05,0xa4,0x19]
+0x05,0x40,0x16,0xcc,0xff,0x05,0xa4,0x19
+
+# GFX12: v_dot4_i32_iu8 v5, s1, v255, exec_hi    ; encoding: [0x05,0x40,0x16,0xcc,0x01,0xfe,0xff,0x19]
+0x05,0x40,0x16,0xcc,0x01,0xfe,0xff,0x19
+
+# GFX12: v_dot4_i32_iu8 v5, s105, s105, exec_lo  ; encoding: [0x05,0x40,0x16,0xcc,0x69,0xd2,0xf8,0x19]
+0x05,0x40,0x16,0xcc,0x69,0xd2,0xf8,0x19
+
+# GFX12: v_dot4_i32_iu8 v5, vcc_lo, ttmp15, v3   ; encoding: [0x05,0x40,0x16,0xcc,0x6a,0xf6,0x0c,0x1c]
+0x05,0x40,0x16,0xcc,0x6a,0xf6,0x0c,0x1c
+
+# GFX12: v_dot4_i32_iu8 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x40,0x16,0xcc,0x6b,0xfe,0xfd,0x1f,0x56,0x34,0x12,0xaf]
+0x05,0x40,0x16,0xcc,0x6b,0xfe,0xfd,0x1f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dot4_i32_iu8 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x40,0x16,0xcc,0x7b,0xfa,0xed,0x19]
+0x05,0x40,0x16,0xcc,0x7b,0xfa,0xed,0x19
+
+# GFX12: v_dot4_i32_iu8 v5, m0, 0.5, m0          ; encoding: [0x05,0x40,0x16,0xcc,0x7d,0xe0,0xf5,0x19]
+0x05,0x40,0x16,0xcc,0x7d,0xe0,0xf5,0x19
+
+# GFX12: v_dot4_i32_iu8 v5, exec_lo, -1, vcc_hi  ; encoding: [0x05,0x40,0x16,0xcc,0x7e,0x82,0xad,0x19]
+0x05,0x40,0x16,0xcc,0x7e,0x82,0xad,0x19
+
+# GFX12: v_dot4_i32_iu8 v5, exec_hi, null, vcc_lo ; encoding: [0x05,0x40,0x16,0xcc,0x7f,0xf8,0xa8,0x19]
+0x05,0x40,0x16,0xcc,0x7f,0xf8,0xa8,0x19
+
+# GFX12: v_dot4_i32_iu8 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x40,0x16,0xcc,0x7c,0xfc,0xfc,0x1b,0x56,0x34,0x12,0xaf]
+0x05,0x40,0x16,0xcc,0x7c,0xfc,0xfc,0x1b,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dot4_i32_iu8 v5, -1, exec_hi, src_scc ; encoding: [0x05,0x40,0x16,0xcc,0xc1,0xfe,0xf4,0x1b]
+0x05,0x40,0x16,0xcc,0xc1,0xfe,0xf4,0x1b
+
+# GFX12: v_dot4_i32_iu8 v5, 0.5, m0, 0.5         ; encoding: [0x05,0x40,0x16,0xcc,0xf0,0xfa,0xc0,0x1b]
+0x05,0x40,0x16,0xcc,0xf0,0xfa,0xc0,0x1b
+
+# GFX12: v_dot4_i32_iu8 v5, src_scc, vcc_lo, -1 neg_lo:[1,0,0] ; encoding: [0x05,0x40,0x16,0xcc,0xfd,0xd4,0x04,0x3b]
+0x05,0x40,0x16,0xcc,0xfd,0xd4,0x04,0x3b
+
+# GFX12: v_dot4_i32_iu8 v255, 0xaf123456, vcc_hi, null neg_lo:[0,1,0] ; encoding: [0xff,0x40,0x16,0xcc,0xff,0xd6,0xf0,0x59,0x56,0x34,0x12,0xaf]
+0xff,0x40,0x16,0xcc,0xff,0xd6,0xf0,0x59,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dot4_u32_u8 v5, v1, v2, s3            ; encoding: [0x05,0x40,0x17,0xcc,0x01,0x05,0x0e,0x18]
+0x05,0x40,0x17,0xcc,0x01,0x05,0x0e,0x18
+
+# GFX12: v_dot4_u32_u8 v5, v255, s2, s105        ; encoding: [0x05,0x40,0x17,0xcc,0xff,0x05,0xa4,0x19]
+0x05,0x40,0x17,0xcc,0xff,0x05,0xa4,0x19
+
+# GFX12: v_dot4_u32_u8 v5, s1, v255, exec_hi     ; encoding: [0x05,0x40,0x17,0xcc,0x01,0xfe,0xff,0x19]
+0x05,0x40,0x17,0xcc,0x01,0xfe,0xff,0x19
+
+# GFX12: v_dot4_u32_u8 v5, s105, s105, exec_lo   ; encoding: [0x05,0x40,0x17,0xcc,0x69,0xd2,0xf8,0x19]
+0x05,0x40,0x17,0xcc,0x69,0xd2,0xf8,0x19
+
+# GFX12: v_dot4_u32_u8 v5, vcc_lo, ttmp15, v3    ; encoding: [0x05,0x40,0x17,0xcc,0x6a,0xf6,0x0c,0x1c]
+0x05,0x40,0x17,0xcc,0x6a,0xf6,0x0c,0x1c
+
+# GFX12: v_dot4_u32_u8 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x40,0x17,0xcc,0x6b,0xfe,0xfd,0x1f,0x56,0x34,0x12,0xaf]
+0x05,0x40,0x17,0xcc,0x6b,0xfe,0xfd,0x1f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dot4_u32_u8 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x40,0x17,0xcc,0x7b,0xfa,0xed,0x19]
+0x05,0x40,0x17,0xcc,0x7b,0xfa,0xed,0x19
+
+# GFX12: v_dot4_u32_u8 v5, m0, 0.5, m0           ; encoding: [0x05,0x40,0x17,0xcc,0x7d,0xe0,0xf5,0x19]
+0x05,0x40,0x17,0xcc,0x7d,0xe0,0xf5,0x19
+
+# GFX12: v_dot4_u32_u8 v5, exec_lo, -1, vcc_hi   ; encoding: [0x05,0x40,0x17,0xcc,0x7e,0x82,0xad,0x19]
+0x05,0x40,0x17,0xcc,0x7e,0x82,0xad,0x19
+
+# GFX12: v_dot4_u32_u8 v5, exec_hi, null, vcc_lo ; encoding: [0x05,0x40,0x17,0xcc,0x7f,0xf8,0xa8,0x19]
+0x05,0x40,0x17,0xcc,0x7f,0xf8,0xa8,0x19
+
+# GFX12: v_dot4_u32_u8 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x40,0x17,0xcc,0x7c,0xfc,0xfc,0x1b,0x56,0x34,0x12,0xaf]
+0x05,0x40,0x17,0xcc,0x7c,0xfc,0xfc,0x1b,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dot4_u32_u8 v5, -1, exec_hi, src_scc  ; encoding: [0x05,0x40,0x17,0xcc,0xc1,0xfe,0xf4,0x1b]
+0x05,0x40,0x17,0xcc,0xc1,0xfe,0xf4,0x1b
+
+# GFX12: v_dot4_u32_u8 v5, 0.5, m0, 0.5          ; encoding: [0x05,0x40,0x17,0xcc,0xf0,0xfa,0xc0,0x1b]
+0x05,0x40,0x17,0xcc,0xf0,0xfa,0xc0,0x1b
+
+# GFX12: v_dot4_u32_u8 v5, src_scc, vcc_lo, -1   ; encoding: [0x05,0x40,0x17,0xcc,0xfd,0xd4,0x04,0x1b]
+0x05,0x40,0x17,0xcc,0xfd,0xd4,0x04,0x1b
+
+# GFX12: v_dot4_u32_u8 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x40,0x17,0xcc,0xff,0xd6,0xf0,0x19,0x56,0x34,0x12,0xaf]
+0xff,0x40,0x17,0xcc,0xff,0xd6,0xf0,0x19,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dot8_i32_iu4 v5, v1, v2, s3           ; encoding: [0x05,0x40,0x18,0xcc,0x01,0x05,0x0e,0x18]
+0x05,0x40,0x18,0xcc,0x01,0x05,0x0e,0x18
+
+# GFX12: v_dot8_i32_iu4 v5, v255, s2, s105       ; encoding: [0x05,0x40,0x18,0xcc,0xff,0x05,0xa4,0x19]
+0x05,0x40,0x18,0xcc,0xff,0x05,0xa4,0x19
+
+# GFX12: v_dot8_i32_iu4 v5, s1, v255, exec_hi    ; encoding: [0x05,0x40,0x18,0xcc,0x01,0xfe,0xff,0x19]
+0x05,0x40,0x18,0xcc,0x01,0xfe,0xff,0x19
+
+# GFX12: v_dot8_i32_iu4 v5, s105, s105, exec_lo  ; encoding: [0x05,0x40,0x18,0xcc,0x69,0xd2,0xf8,0x19]
+0x05,0x40,0x18,0xcc,0x69,0xd2,0xf8,0x19
+
+# GFX12: v_dot8_i32_iu4 v5, vcc_lo, ttmp15, v3   ; encoding: [0x05,0x40,0x18,0xcc,0x6a,0xf6,0x0c,0x1c]
+0x05,0x40,0x18,0xcc,0x6a,0xf6,0x0c,0x1c
+
+# GFX12: v_dot8_i32_iu4 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x40,0x18,0xcc,0x6b,0xfe,0xfd,0x1f,0x56,0x34,0x12,0xaf]
+0x05,0x40,0x18,0xcc,0x6b,0xfe,0xfd,0x1f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dot8_i32_iu4 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x40,0x18,0xcc,0x7b,0xfa,0xed,0x19]
+0x05,0x40,0x18,0xcc,0x7b,0xfa,0xed,0x19
+
+# GFX12: v_dot8_i32_iu4 v5, m0, 0.5, m0          ; encoding: [0x05,0x40,0x18,0xcc,0x7d,0xe0,0xf5,0x19]
+0x05,0x40,0x18,0xcc,0x7d,0xe0,0xf5,0x19
+
+# GFX12: v_dot8_i32_iu4 v5, exec_lo, -1, vcc_hi  ; encoding: [0x05,0x40,0x18,0xcc,0x7e,0x82,0xad,0x19]
+0x05,0x40,0x18,0xcc,0x7e,0x82,0xad,0x19
+
+# GFX12: v_dot8_i32_iu4 v5, exec_hi, null, vcc_lo ; encoding: [0x05,0x40,0x18,0xcc,0x7f,0xf8,0xa8,0x19]
+0x05,0x40,0x18,0xcc,0x7f,0xf8,0xa8,0x19
+
+# GFX12: v_dot8_i32_iu4 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x40,0x18,0xcc,0x7c,0xfc,0xfc,0x1b,0x56,0x34,0x12,0xaf]
+0x05,0x40,0x18,0xcc,0x7c,0xfc,0xfc,0x1b,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dot8_i32_iu4 v5, -1, exec_hi, src_scc ; encoding: [0x05,0x40,0x18,0xcc,0xc1,0xfe,0xf4,0x1b]
+0x05,0x40,0x18,0xcc,0xc1,0xfe,0xf4,0x1b
+
+# GFX12: v_dot8_i32_iu4 v5, 0.5, m0, 0.5         ; encoding: [0x05,0x40,0x18,0xcc,0xf0,0xfa,0xc0,0x1b]
+0x05,0x40,0x18,0xcc,0xf0,0xfa,0xc0,0x1b
+
+# GFX12: v_dot8_i32_iu4 v5, src_scc, vcc_lo, -1 neg_lo:[1,0,0] ; encoding: [0x05,0x40,0x18,0xcc,0xfd,0xd4,0x04,0x3b]
+0x05,0x40,0x18,0xcc,0xfd,0xd4,0x04,0x3b
+
+# GFX12: v_dot8_i32_iu4 v255, 0xaf123456, vcc_hi, null neg_lo:[0,1,0] clamp ; encoding: [0xff,0xc0,0x18,0xcc,0xff,0xd6,0xf0,0x59,0x56,0x34,0x12,0xaf]
+0xff,0xc0,0x18,0xcc,0xff,0xd6,0xf0,0x59,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dot8_u32_u4 v5, v1, v2, s3            ; encoding: [0x05,0x40,0x19,0xcc,0x01,0x05,0x0e,0x18]
+0x05,0x40,0x19,0xcc,0x01,0x05,0x0e,0x18
+
+# GFX12: v_dot8_u32_u4 v5, v255, s2, s105        ; encoding: [0x05,0x40,0x19,0xcc,0xff,0x05,0xa4,0x19]
+0x05,0x40,0x19,0xcc,0xff,0x05,0xa4,0x19
+
+# GFX12: v_dot8_u32_u4 v5, s1, v255, exec_hi     ; encoding: [0x05,0x40,0x19,0xcc,0x01,0xfe,0xff,0x19]
+0x05,0x40,0x19,0xcc,0x01,0xfe,0xff,0x19
+
+# GFX12: v_dot8_u32_u4 v5, s105, s105, exec_lo   ; encoding: [0x05,0x40,0x19,0xcc,0x69,0xd2,0xf8,0x19]
+0x05,0x40,0x19,0xcc,0x69,0xd2,0xf8,0x19
+
+# GFX12: v_dot8_u32_u4 v5, vcc_lo, ttmp15, v3    ; encoding: [0x05,0x40,0x19,0xcc,0x6a,0xf6,0x0c,0x1c]
+0x05,0x40,0x19,0xcc,0x6a,0xf6,0x0c,0x1c
+
+# GFX12: v_dot8_u32_u4 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x40,0x19,0xcc,0x6b,0xfe,0xfd,0x1f,0x56,0x34,0x12,0xaf]
+0x05,0x40,0x19,0xcc,0x6b,0xfe,0xfd,0x1f,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dot8_u32_u4 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x40,0x19,0xcc,0x7b,0xfa,0xed,0x19]
+0x05,0x40,0x19,0xcc,0x7b,0xfa,0xed,0x19
+
+# GFX12: v_dot8_u32_u4 v5, m0, 0.5, m0           ; encoding: [0x05,0x40,0x19,0xcc,0x7d,0xe0,0xf5,0x19]
+0x05,0x40,0x19,0xcc,0x7d,0xe0,0xf5,0x19
+
+# GFX12: v_dot8_u32_u4 v5, exec_lo, -1, vcc_hi   ; encoding: [0x05,0x40,0x19,0xcc,0x7e,0x82,0xad,0x19]
+0x05,0x40,0x19,0xcc,0x7e,0x82,0xad,0x19
+
+# GFX12: v_dot8_u32_u4 v5, exec_hi, null, vcc_lo ; encoding: [0x05,0x40,0x19,0xcc,0x7f,0xf8,0xa8,0x19]
+0x05,0x40,0x19,0xcc,0x7f,0xf8,0xa8,0x19
+
+# GFX12: v_dot8_u32_u4 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x40,0x19,0xcc,0x7c,0xfc,0xfc,0x1b,0x56,0x34,0x12,0xaf]
+0x05,0x40,0x19,0xcc,0x7c,0xfc,0xfc,0x1b,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dot8_u32_u4 v5, -1, exec_hi, src_scc  ; encoding: [0x05,0x40,0x19,0xcc,0xc1,0xfe,0xf4,0x1b]
+0x05,0x40,0x19,0xcc,0xc1,0xfe,0xf4,0x1b
+
+# GFX12: v_dot8_u32_u4 v5, 0.5, m0, 0.5          ; encoding: [0x05,0x40,0x19,0xcc,0xf0,0xfa,0xc0,0x1b]
+0x05,0x40,0x19,0xcc,0xf0,0xfa,0xc0,0x1b
+
+# GFX12: v_dot8_u32_u4 v5, src_scc, vcc_lo, -1   ; encoding: [0x05,0x40,0x19,0xcc,0xfd,0xd4,0x04,0x1b]
+0x05,0x40,0x19,0xcc,0xfd,0xd4,0x04,0x1b
+
+# GFX12: v_dot8_u32_u4 v255, 0xaf123456, vcc_hi, null clamp ; encoding: [0xff,0xc0,0x19,0xcc,0xff,0xd6,0xf0,0x19,0x56,0x34,0x12,0xaf]
+0xff,0xc0,0x19,0xcc,0xff,0xd6,0xf0,0x19,0x56,0x34,0x12,0xaf
+
+# GFX12: v_fma_mix_f32 v5, v1, v2, s3            ; encoding: [0x05,0x00,0x20,0xcc,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x20,0xcc,0x01,0x05,0x0e,0x00
+
+# GFX12: v_fma_mix_f32 v5, v255, v255, s105      ; encoding: [0x05,0x00,0x20,0xcc,0xff,0xff,0xa7,0x01]
+0x05,0x00,0x20,0xcc,0xff,0xff,0xa7,0x01
+
+# GFX12: v_fma_mix_f32 v5, s1, s2, v3            ; encoding: [0x05,0x00,0x20,0xcc,0x01,0x04,0x0c,0x04]
+0x05,0x00,0x20,0xcc,0x01,0x04,0x0c,0x04
+
+# GFX12: v_fma_mix_f32 v5, s105, s105, m0        ; encoding: [0x05,0x00,0x20,0xcc,0x69,0xd2,0xf4,0x01]
+0x05,0x00,0x20,0xcc,0x69,0xd2,0xf4,0x01
+
+# GFX12: v_fma_mix_f32 v5, vcc_lo, ttmp15, ttmp15 ; encoding: [0x05,0x00,0x20,0xcc,0x6a,0xf6,0xec,0x01]
+0x05,0x00,0x20,0xcc,0x6a,0xf6,0xec,0x01
+
+# GFX12: v_fma_mix_f32 v5, vcc_hi, src_scc, v255 ; encoding: [0x05,0x00,0x20,0xcc,0x6b,0xfa,0xfd,0x07]
+0x05,0x00,0x20,0xcc,0x6b,0xfa,0xfd,0x07
+
+# GFX12: v_fma_mix_f32 v5, |ttmp15|, 0.5, -vcc_hi ; encoding: [0x05,0x01,0x20,0xcc,0x7b,0xe0,0xad,0x81]
+0x05,0x01,0x20,0xcc,0x7b,0xe0,0xad,0x81
+
+# GFX12: v_fma_mix_f32 v5, -m0, -1, |vcc_lo|     ; encoding: [0x05,0x04,0x20,0xcc,0x7d,0x82,0xa9,0x21]
+0x05,0x04,0x20,0xcc,0x7d,0x82,0xa9,0x21
+
+# GFX12: v_fma_mix_f32 v5, -|exec_lo|, null, -|src_scc| ; encoding: [0x05,0x05,0x20,0xcc,0x7e,0xf8,0xf4,0xa3]
+0x05,0x05,0x20,0xcc,0x7e,0xf8,0xf4,0xa3
+
+# GFX12: v_fma_mix_f32 v5, -|exec_hi|, -|exec_lo|, -|exec_lo| ; encoding: [0x05,0x07,0x20,0xcc,0x7f,0xfc,0xf8,0xe1]
+0x05,0x07,0x20,0xcc,0x7f,0xfc,0xf8,0xe1
+
+# GFX12: v_fma_mix_f32 v5, null, exec_hi, 0.5 op_sel:[1,1,1] op_sel_hi:[1,1,1] ; encoding: [0x05,0x78,0x20,0xcc,0x7c,0xfe,0xc0,0x1b]
+0x05,0x78,0x20,0xcc,0x7c,0xfe,0xc0,0x1b
+
+# GFX12: v_fma_mix_f32 v5, -1, -|m0|, -1 op_sel:[1,0,0] op_sel_hi:[0,0,1] ; encoding: [0x05,0x4a,0x20,0xcc,0xc1,0xfa,0x04,0x43]
+0x05,0x4a,0x20,0xcc,0xc1,0xfa,0x04,0x43
+
+# GFX12: v_fma_mix_f32 v5, 0.5, -|vcc_lo|, -|exec_hi| op_sel:[0,1,0] op_sel_hi:[0,1,0] ; encoding: [0x05,0x16,0x20,0xcc,0xf0,0xd4,0xfc,0xd1]
+0x05,0x16,0x20,0xcc,0xf0,0xd4,0xfc,0xd1
+
+# GFX12: v_fma_mix_f32 v255, -|src_scc|, -|vcc_hi|, null op_sel:[0,0,1] op_sel_hi:[1,0,0] clamp ; encoding: [0xff,0xa3,0x20,0xcc,0xfd,0xd6,0xf0,0x69]
+0xff,0xa3,0x20,0xcc,0xfd,0xd6,0xf0,0x69
+
+# GFX12: v_fma_mixhi_f16 v5, v1, v2, s3          ; encoding: [0x05,0x00,0x22,0xcc,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x22,0xcc,0x01,0x05,0x0e,0x00
+
+# GFX12: v_fma_mixhi_f16 v5, v255, v255, s105    ; encoding: [0x05,0x00,0x22,0xcc,0xff,0xff,0xa7,0x01]
+0x05,0x00,0x22,0xcc,0xff,0xff,0xa7,0x01
+
+# GFX12: v_fma_mixhi_f16 v5, s1, s2, v3          ; encoding: [0x05,0x00,0x22,0xcc,0x01,0x04,0x0c,0x04]
+0x05,0x00,0x22,0xcc,0x01,0x04,0x0c,0x04
+
+# GFX12: v_fma_mixhi_f16 v5, s105, s105, m0      ; encoding: [0x05,0x00,0x22,0xcc,0x69,0xd2,0xf4,0x01]
+0x05,0x00,0x22,0xcc,0x69,0xd2,0xf4,0x01
+
+# GFX12: v_fma_mixhi_f16 v5, vcc_lo, ttmp15, ttmp15 ; encoding: [0x05,0x00,0x22,0xcc,0x6a,0xf6,0xec,0x01]
+0x05,0x00,0x22,0xcc,0x6a,0xf6,0xec,0x01
+
+# GFX12: v_fma_mixhi_f16 v5, vcc_hi, src_scc, v255 ; encoding: [0x05,0x00,0x22,0xcc,0x6b,0xfa,0xfd,0x07]
+0x05,0x00,0x22,0xcc,0x6b,0xfa,0xfd,0x07
+
+# GFX12: v_fma_mixhi_f16 v5, |ttmp15|, 0.5, -vcc_hi ; encoding: [0x05,0x01,0x22,0xcc,0x7b,0xe0,0xad,0x81]
+0x05,0x01,0x22,0xcc,0x7b,0xe0,0xad,0x81
+
+# GFX12: v_fma_mixhi_f16 v5, -m0, -1, |vcc_lo|   ; encoding: [0x05,0x04,0x22,0xcc,0x7d,0x82,0xa9,0x21]
+0x05,0x04,0x22,0xcc,0x7d,0x82,0xa9,0x21
+
+# GFX12: v_fma_mixhi_f16 v5, -|exec_lo|, null, -|src_scc| ; encoding: [0x05,0x05,0x22,0xcc,0x7e,0xf8,0xf4,0xa3]
+0x05,0x05,0x22,0xcc,0x7e,0xf8,0xf4,0xa3
+
+# GFX12: v_fma_mixhi_f16 v5, -|exec_hi|, -|exec_lo|, -|exec_lo| ; encoding: [0x05,0x07,0x22,0xcc,0x7f,0xfc,0xf8,0xe1]
+0x05,0x07,0x22,0xcc,0x7f,0xfc,0xf8,0xe1
+
+# GFX12: v_fma_mixhi_f16 v5, null, exec_hi, 0.5 op_sel:[1,1,1] op_sel_hi:[1,1,1] ; encoding: [0x05,0x78,0x22,0xcc,0x7c,0xfe,0xc0,0x1b]
+0x05,0x78,0x22,0xcc,0x7c,0xfe,0xc0,0x1b
+
+# GFX12: v_fma_mixhi_f16 v5, -1, -|m0|, -1 op_sel:[1,0,0] op_sel_hi:[0,0,1] ; encoding: [0x05,0x4a,0x22,0xcc,0xc1,0xfa,0x04,0x43]
+0x05,0x4a,0x22,0xcc,0xc1,0xfa,0x04,0x43
+
+# GFX12: v_fma_mixhi_f16 v5, 0.5, -|vcc_lo|, -|exec_hi| op_sel:[0,1,0] op_sel_hi:[0,1,0] ; encoding: [0x05,0x16,0x22,0xcc,0xf0,0xd4,0xfc,0xd1]
+0x05,0x16,0x22,0xcc,0xf0,0xd4,0xfc,0xd1
+
+# GFX12: v_fma_mixhi_f16 v255, -|src_scc|, -|vcc_hi|, null op_sel:[0,0,1] op_sel_hi:[1,0,0] clamp ; encoding: [0xff,0xa3,0x22,0xcc,0xfd,0xd6,0xf0,0x69]
+0xff,0xa3,0x22,0xcc,0xfd,0xd6,0xf0,0x69
+
+# GFX12: v_fma_mixlo_f16 v5, v1, v2, s3          ; encoding: [0x05,0x00,0x21,0xcc,0x01,0x05,0x0e,0x00]
+0x05,0x00,0x21,0xcc,0x01,0x05,0x0e,0x00
+
+# GFX12: v_fma_mixlo_f16 v5, v255, v255, s105    ; encoding: [0x05,0x00,0x21,0xcc,0xff,0xff,0xa7,0x01]
+0x05,0x00,0x21,0xcc,0xff,0xff,0xa7,0x01
+
+# GFX12: v_fma_mixlo_f16 v5, s1, s2, v3          ; encoding: [0x05,0x00,0x21,0xcc,0x01,0x04,0x0c,0x04]
+0x05,0x00,0x21,0xcc,0x01,0x04,0x0c,0x04
+
+# GFX12: v_fma_mixlo_f16 v5, s105, s105, m0      ; encoding: [0x05,0x00,0x21,0xcc,0x69,0xd2,0xf4,0x01]
+0x05,0x00,0x21,0xcc,0x69,0xd2,0xf4,0x01
+
+# GFX12: v_fma_mixlo_f16 v5, vcc_lo, ttmp15, ttmp15 ; encoding: [0x05,0x00,0x21,0xcc,0x6a,0xf6,0xec,0x01]
+0x05,0x00,0x21,0xcc,0x6a,0xf6,0xec,0x01
+
+# GFX12: v_fma_mixlo_f16 v5, vcc_hi, src_scc, v255 ; encoding: [0x05,0x00,0x21,0xcc,0x6b,0xfa,0xfd,0x07]
+0x05,0x00,0x21,0xcc,0x6b,0xfa,0xfd,0x07
+
+# GFX12: v_fma_mixlo_f16 v5, |ttmp15|, 0.5, -vcc_hi ; encoding: [0x05,0x01,0x21,0xcc,0x7b,0xe0,0xad,0x81]
+0x05,0x01,0x21,0xcc,0x7b,0xe0,0xad,0x81
+
+# GFX12: v_fma_mixlo_f16 v5, -m0, -1, |vcc_lo|   ; encoding: [0x05,0x04,0x21,0xcc,0x7d,0x82,0xa9,0x21]
+0x05,0x04,0x21,0xcc,0x7d,0x82,0xa9,0x21
+
+# GFX12: v_fma_mixlo_f16 v5, -|exec_lo|, null, -|src_scc| ; encoding: [0x05,0x05,0x21,0xcc,0x7e,0xf8,0xf4,0xa3]
+0x05,0x05,0x21,0xcc,0x7e,0xf8,0xf4,0xa3
+
+# GFX12: v_fma_mixlo_f16 v5, -|exec_hi|, -|exec_lo|, -|exec_lo| ; encoding: [0x05,0x07,0x21,0xcc,0x7f,0xfc,0xf8,0xe1]
+0x05,0x07,0x21,0xcc,0x7f,0xfc,0xf8,0xe1
+
+# GFX12: v_fma_mixlo_f16 v5, null, exec_hi, 0.5 op_sel:[1,1,1] op_sel_hi:[1,1,1] ; encoding: [0x05,0x78,0x21,0xcc,0x7c,0xfe,0xc0,0x1b]
+0x05,0x78,0x21,0xcc,0x7c,0xfe,0xc0,0x1b
+
+# GFX12: v_fma_mixlo_f16 v5, -1, -|m0|, -1 op_sel:[1,0,0] op_sel_hi:[0,0,1] ; encoding: [0x05,0x4a,0x21,0xcc,0xc1,0xfa,0x04,0x43]
+0x05,0x4a,0x21,0xcc,0xc1,0xfa,0x04,0x43
+
+# GFX12: v_fma_mixlo_f16 v5, 0.5, -|vcc_lo|, -|exec_hi| op_sel:[0,1,0] op_sel_hi:[0,1,0] ; encoding: [0x05,0x16,0x21,0xcc,0xf0,0xd4,0xfc,0xd1]
+0x05,0x16,0x21,0xcc,0xf0,0xd4,0xfc,0xd1
+
+# GFX12: v_fma_mixlo_f16 v255, -|src_scc|, -|vcc_hi|, null op_sel:[0,0,1] op_sel_hi:[1,0,0] clamp ; encoding: [0xff,0xa3,0x21,0xcc,0xfd,0xd6,0xf0,0x69]
+0xff,0xa3,0x21,0xcc,0xfd,0xd6,0xf0,0x69
+
+# GFX12: v_pk_add_f16 v5, v1, v2                 ; encoding: [0x05,0x40,0x0f,0xcc,0x01,0x05,0x02,0x18]
+0x05,0x40,0x0f,0xcc,0x01,0x05,0x02,0x18
+
+# GFX12: v_pk_add_f16 v5, v255, v255             ; encoding: [0x05,0x40,0x0f,0xcc,0xff,0xff,0x03,0x18]
+0x05,0x40,0x0f,0xcc,0xff,0xff,0x03,0x18
+
+# GFX12: v_pk_add_f16 v5, s1, s2                 ; encoding: [0x05,0x40,0x0f,0xcc,0x01,0x04,0x00,0x18]
+0x05,0x40,0x0f,0xcc,0x01,0x04,0x00,0x18
+
+# GFX12: v_pk_add_f16 v5, s105, s105             ; encoding: [0x05,0x40,0x0f,0xcc,0x69,0xd2,0x00,0x18]
+0x05,0x40,0x0f,0xcc,0x69,0xd2,0x00,0x18
+
+# GFX12: v_pk_add_f16 v5, vcc_lo, ttmp15         ; encoding: [0x05,0x40,0x0f,0xcc,0x6a,0xf6,0x00,0x18]
+0x05,0x40,0x0f,0xcc,0x6a,0xf6,0x00,0x18
+
+# GFX12: v_pk_add_f16 v5, vcc_hi, 0xfe0b         ; encoding: [0x05,0x40,0x0f,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+0x05,0x40,0x0f,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_add_f16 v5, ttmp15, src_scc        ; encoding: [0x05,0x40,0x0f,0xcc,0x7b,0xfa,0x01,0x18]
+0x05,0x40,0x0f,0xcc,0x7b,0xfa,0x01,0x18
+
+# GFX12: v_pk_add_f16 v5, m0, 0.5                ; encoding: [0x05,0x40,0x0f,0xcc,0x7d,0xe0,0x01,0x18]
+0x05,0x40,0x0f,0xcc,0x7d,0xe0,0x01,0x18
+
+# GFX12: v_pk_add_f16 v5, exec_lo, -1            ; encoding: [0x05,0x40,0x0f,0xcc,0x7e,0x82,0x01,0x18]
+0x05,0x40,0x0f,0xcc,0x7e,0x82,0x01,0x18
+
+# GFX12: v_pk_add_f16 v5, exec_hi, null          ; encoding: [0x05,0x40,0x0f,0xcc,0x7f,0xf8,0x00,0x18]
+0x05,0x40,0x0f,0xcc,0x7f,0xf8,0x00,0x18
+
+# GFX12: v_pk_add_f16 v5, null, exec_lo          ; encoding: [0x05,0x40,0x0f,0xcc,0x7c,0xfc,0x00,0x18]
+0x05,0x40,0x0f,0xcc,0x7c,0xfc,0x00,0x18
+
+# GFX12: v_pk_add_f16 v5, -1, exec_hi            ; encoding: [0x05,0x40,0x0f,0xcc,0xc1,0xfe,0x00,0x18]
+0x05,0x40,0x0f,0xcc,0xc1,0xfe,0x00,0x18
+
+# GFX12: v_pk_add_f16 v5, 0.5, m0 op_sel:[1,1] op_sel_hi:[0,0] neg_lo:[1,0] neg_hi:[1,0] ; encoding: [0x05,0x59,0x0f,0xcc,0xf0,0xfa,0x00,0x20]
+0x05,0x59,0x0f,0xcc,0xf0,0xfa,0x00,0x20
+
+# GFX12: v_pk_add_f16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1] neg_lo:[0,1] neg_hi:[0,1] ; encoding: [0x05,0x4a,0x0f,0xcc,0xfd,0xd4,0x00,0x50]
+0x05,0x4a,0x0f,0xcc,0xfd,0xd4,0x00,0x50
+
+# GFX12: v_pk_add_f16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] neg_lo:[1,1] neg_hi:[1,1] clamp ; encoding: [0xff,0xd3,0x0f,0xcc,0xff,0xd6,0x00,0x68,0x0b,0xfe,0x00,0x00]
+0xff,0xd3,0x0f,0xcc,0xff,0xd6,0x00,0x68,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_add_i16 v5, v1, v2                 ; encoding: [0x05,0x40,0x02,0xcc,0x01,0x05,0x02,0x18]
+0x05,0x40,0x02,0xcc,0x01,0x05,0x02,0x18
+
+# GFX12: v_pk_add_i16 v5, v255, v255             ; encoding: [0x05,0x40,0x02,0xcc,0xff,0xff,0x03,0x18]
+0x05,0x40,0x02,0xcc,0xff,0xff,0x03,0x18
+
+# GFX12: v_pk_add_i16 v5, s1, s2                 ; encoding: [0x05,0x40,0x02,0xcc,0x01,0x04,0x00,0x18]
+0x05,0x40,0x02,0xcc,0x01,0x04,0x00,0x18
+
+# GFX12: v_pk_add_i16 v5, s105, s105             ; encoding: [0x05,0x40,0x02,0xcc,0x69,0xd2,0x00,0x18]
+0x05,0x40,0x02,0xcc,0x69,0xd2,0x00,0x18
+
+# GFX12: v_pk_add_i16 v5, vcc_lo, ttmp15         ; encoding: [0x05,0x40,0x02,0xcc,0x6a,0xf6,0x00,0x18]
+0x05,0x40,0x02,0xcc,0x6a,0xf6,0x00,0x18
+
+# GFX12: v_pk_add_i16 v5, vcc_hi, 0xfe0b         ; encoding: [0x05,0x40,0x02,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+0x05,0x40,0x02,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_add_i16 v5, ttmp15, src_scc        ; encoding: [0x05,0x40,0x02,0xcc,0x7b,0xfa,0x01,0x18]
+0x05,0x40,0x02,0xcc,0x7b,0xfa,0x01,0x18
+
+# GFX12: v_pk_add_i16 v5, m0, 0x3800
+0x05,0x40,0x02,0xcc,0x7d,0xe0,0x01,0x18
+
+# GFX12: v_pk_add_i16 v5, exec_lo, -1            ; encoding: [0x05,0x40,0x02,0xcc,0x7e,0x82,0x01,0x18]
+0x05,0x40,0x02,0xcc,0x7e,0x82,0x01,0x18
+
+# GFX12: v_pk_add_i16 v5, exec_hi, null          ; encoding: [0x05,0x40,0x02,0xcc,0x7f,0xf8,0x00,0x18]
+0x05,0x40,0x02,0xcc,0x7f,0xf8,0x00,0x18
+
+# GFX12: v_pk_add_i16 v5, null, exec_lo          ; encoding: [0x05,0x40,0x02,0xcc,0x7c,0xfc,0x00,0x18]
+0x05,0x40,0x02,0xcc,0x7c,0xfc,0x00,0x18
+
+# GFX12: v_pk_add_i16 v5, -1, exec_hi            ; encoding: [0x05,0x40,0x02,0xcc,0xc1,0xfe,0x00,0x18]
+0x05,0x40,0x02,0xcc,0xc1,0xfe,0x00,0x18
+
+# GFX12: v_pk_add_i16 v5, 0x3800, m0 op_sel:[1,1] op_sel_hi:[0,0]
+0x05,0x58,0x02,0xcc,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_pk_add_i16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1] ; encoding: [0x05,0x48,0x02,0xcc,0xfd,0xd4,0x00,0x10]
+0x05,0x48,0x02,0xcc,0xfd,0xd4,0x00,0x10
+
+# GFX12: v_pk_add_i16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] clamp ; encoding: [0xff,0xd0,0x02,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00]
+0xff,0xd0,0x02,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_add_u16 v5, v1, v2                 ; encoding: [0x05,0x40,0x0a,0xcc,0x01,0x05,0x02,0x18]
+0x05,0x40,0x0a,0xcc,0x01,0x05,0x02,0x18
+
+# GFX12: v_pk_add_u16 v5, v255, v255             ; encoding: [0x05,0x40,0x0a,0xcc,0xff,0xff,0x03,0x18]
+0x05,0x40,0x0a,0xcc,0xff,0xff,0x03,0x18
+
+# GFX12: v_pk_add_u16 v5, s1, s2                 ; encoding: [0x05,0x40,0x0a,0xcc,0x01,0x04,0x00,0x18]
+0x05,0x40,0x0a,0xcc,0x01,0x04,0x00,0x18
+
+# GFX12: v_pk_add_u16 v5, s105, s105             ; encoding: [0x05,0x40,0x0a,0xcc,0x69,0xd2,0x00,0x18]
+0x05,0x40,0x0a,0xcc,0x69,0xd2,0x00,0x18
+
+# GFX12: v_pk_add_u16 v5, vcc_lo, ttmp15         ; encoding: [0x05,0x40,0x0a,0xcc,0x6a,0xf6,0x00,0x18]
+0x05,0x40,0x0a,0xcc,0x6a,0xf6,0x00,0x18
+
+# GFX12: v_pk_add_u16 v5, vcc_hi, 0xfe0b         ; encoding: [0x05,0x40,0x0a,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+0x05,0x40,0x0a,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_add_u16 v5, ttmp15, src_scc        ; encoding: [0x05,0x40,0x0a,0xcc,0x7b,0xfa,0x01,0x18]
+0x05,0x40,0x0a,0xcc,0x7b,0xfa,0x01,0x18
+
+# GFX12: v_pk_add_u16 v5, m0, 0x3800
+0x05,0x40,0x0a,0xcc,0x7d,0xe0,0x01,0x18
+
+# GFX12: v_pk_add_u16 v5, exec_lo, -1            ; encoding: [0x05,0x40,0x0a,0xcc,0x7e,0x82,0x01,0x18]
+0x05,0x40,0x0a,0xcc,0x7e,0x82,0x01,0x18
+
+# GFX12: v_pk_add_u16 v5, exec_hi, null          ; encoding: [0x05,0x40,0x0a,0xcc,0x7f,0xf8,0x00,0x18]
+0x05,0x40,0x0a,0xcc,0x7f,0xf8,0x00,0x18
+
+# GFX12: v_pk_add_u16 v5, null, exec_lo          ; encoding: [0x05,0x40,0x0a,0xcc,0x7c,0xfc,0x00,0x18]
+0x05,0x40,0x0a,0xcc,0x7c,0xfc,0x00,0x18
+
+# GFX12: v_pk_add_u16 v5, -1, exec_hi            ; encoding: [0x05,0x40,0x0a,0xcc,0xc1,0xfe,0x00,0x18]
+0x05,0x40,0x0a,0xcc,0xc1,0xfe,0x00,0x18
+
+# GFX12: v_pk_add_u16 v5, 0x3800, m0 op_sel:[1,1] op_sel_hi:[0,0]
+0x05,0x58,0x0a,0xcc,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_pk_add_u16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1] ; encoding: [0x05,0x48,0x0a,0xcc,0xfd,0xd4,0x00,0x10]
+0x05,0x48,0x0a,0xcc,0xfd,0xd4,0x00,0x10
+
+# GFX12: v_pk_add_u16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] clamp ; encoding: [0xff,0xd0,0x0a,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00]
+0xff,0xd0,0x0a,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_ashrrev_i16 v5, v1, v2             ; encoding: [0x05,0x40,0x06,0xcc,0x01,0x05,0x02,0x18]
+0x05,0x40,0x06,0xcc,0x01,0x05,0x02,0x18
+
+# GFX12: v_pk_ashrrev_i16 v5, v255, v255         ; encoding: [0x05,0x40,0x06,0xcc,0xff,0xff,0x03,0x18]
+0x05,0x40,0x06,0xcc,0xff,0xff,0x03,0x18
+
+# GFX12: v_pk_ashrrev_i16 v5, s1, s2             ; encoding: [0x05,0x40,0x06,0xcc,0x01,0x04,0x00,0x18]
+0x05,0x40,0x06,0xcc,0x01,0x04,0x00,0x18
+
+# GFX12: v_pk_ashrrev_i16 v5, s105, s105         ; encoding: [0x05,0x40,0x06,0xcc,0x69,0xd2,0x00,0x18]
+0x05,0x40,0x06,0xcc,0x69,0xd2,0x00,0x18
+
+# GFX12: v_pk_ashrrev_i16 v5, vcc_lo, ttmp15     ; encoding: [0x05,0x40,0x06,0xcc,0x6a,0xf6,0x00,0x18]
+0x05,0x40,0x06,0xcc,0x6a,0xf6,0x00,0x18
+
+# GFX12: v_pk_ashrrev_i16 v5, vcc_hi, 0xfe0b     ; encoding: [0x05,0x40,0x06,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+0x05,0x40,0x06,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_ashrrev_i16 v5, ttmp15, src_scc    ; encoding: [0x05,0x40,0x06,0xcc,0x7b,0xfa,0x01,0x18]
+0x05,0x40,0x06,0xcc,0x7b,0xfa,0x01,0x18
+
+# GFX12: v_pk_ashrrev_i16 v5, m0, 0x3800
+0x05,0x40,0x06,0xcc,0x7d,0xe0,0x01,0x18
+
+# GFX12: v_pk_ashrrev_i16 v5, exec_lo, -1        ; encoding: [0x05,0x40,0x06,0xcc,0x7e,0x82,0x01,0x18]
+0x05,0x40,0x06,0xcc,0x7e,0x82,0x01,0x18
+
+# GFX12: v_pk_ashrrev_i16 v5, exec_hi, null      ; encoding: [0x05,0x40,0x06,0xcc,0x7f,0xf8,0x00,0x18]
+0x05,0x40,0x06,0xcc,0x7f,0xf8,0x00,0x18
+
+# GFX12: v_pk_ashrrev_i16 v5, null, exec_lo      ; encoding: [0x05,0x40,0x06,0xcc,0x7c,0xfc,0x00,0x18]
+0x05,0x40,0x06,0xcc,0x7c,0xfc,0x00,0x18
+
+# GFX12: v_pk_ashrrev_i16 v5, -1, exec_hi        ; encoding: [0x05,0x40,0x06,0xcc,0xc1,0xfe,0x00,0x18]
+0x05,0x40,0x06,0xcc,0xc1,0xfe,0x00,0x18
+
+# GFX12: v_pk_ashrrev_i16 v5, 0x3800, m0 op_sel:[1,1] op_sel_hi:[0,0]
+0x05,0x58,0x06,0xcc,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_pk_ashrrev_i16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1] ; encoding: [0x05,0x48,0x06,0xcc,0xfd,0xd4,0x00,0x10]
+0x05,0x48,0x06,0xcc,0xfd,0xd4,0x00,0x10
+
+# GFX12: v_pk_ashrrev_i16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] ; encoding: [0xff,0x50,0x06,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00]
+0xff,0x50,0x06,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_fma_f16 v5, v1, v2, s3             ; encoding: [0x05,0x40,0x0e,0xcc,0x01,0x05,0x0e,0x18]
+0x05,0x40,0x0e,0xcc,0x01,0x05,0x0e,0x18
+
+# GFX12: v_pk_fma_f16 v5, v255, s2, s105         ; encoding: [0x05,0x40,0x0e,0xcc,0xff,0x05,0xa4,0x19]
+0x05,0x40,0x0e,0xcc,0xff,0x05,0xa4,0x19
+
+# GFX12: v_pk_fma_f16 v5, s1, v255, exec_hi      ; encoding: [0x05,0x40,0x0e,0xcc,0x01,0xfe,0xff,0x19]
+0x05,0x40,0x0e,0xcc,0x01,0xfe,0xff,0x19
+
+# GFX12: v_pk_fma_f16 v5, s105, s105, exec_lo    ; encoding: [0x05,0x40,0x0e,0xcc,0x69,0xd2,0xf8,0x19]
+0x05,0x40,0x0e,0xcc,0x69,0xd2,0xf8,0x19
+
+# GFX12: v_pk_fma_f16 v5, vcc_lo, ttmp15, v3     ; encoding: [0x05,0x40,0x0e,0xcc,0x6a,0xf6,0x0c,0x1c]
+0x05,0x40,0x0e,0xcc,0x6a,0xf6,0x0c,0x1c
+
+# GFX12: v_pk_fma_f16 v5, vcc_hi, 0xfe0b, v255   ; encoding: [0x05,0x40,0x0e,0xcc,0x6b,0xfe,0xfd,0x1f,0x0b,0xfe,0x00,0x00]
+0x05,0x40,0x0e,0xcc,0x6b,0xfe,0xfd,0x1f,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_fma_f16 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x40,0x0e,0xcc,0x7b,0xfa,0xed,0x19]
+0x05,0x40,0x0e,0xcc,0x7b,0xfa,0xed,0x19
+
+# GFX12: v_pk_fma_f16 v5, m0, 0.5, m0            ; encoding: [0x05,0x40,0x0e,0xcc,0x7d,0xe0,0xf5,0x19]
+0x05,0x40,0x0e,0xcc,0x7d,0xe0,0xf5,0x19
+
+# GFX12: v_pk_fma_f16 v5, exec_lo, -1, vcc_hi op_sel_hi:[0,0,0] ; encoding: [0x05,0x00,0x0e,0xcc,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x0e,0xcc,0x7e,0x82,0xad,0x01
+
+# GFX12: v_pk_fma_f16 v5, exec_hi, null, vcc_lo op_sel_hi:[0,0,1] ; encoding: [0x05,0x40,0x0e,0xcc,0x7f,0xf8,0xa8,0x01]
+0x05,0x40,0x0e,0xcc,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_pk_fma_f16 v5, null, exec_lo, 0xfe0b op_sel_hi:[0,1,0] ; encoding: [0x05,0x00,0x0e,0xcc,0x7c,0xfc,0xfc,0x13,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x0e,0xcc,0x7c,0xfc,0xfc,0x13,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_fma_f16 v5, -1, exec_hi, src_scc op_sel:[1,1,1] op_sel_hi:[1,0,0] neg_lo:[1,0,0] neg_hi:[1,0,0] ; encoding: [0x05,0x39,0x0e,0xcc,0xc1,0xfe,0xf4,0x2b]
+0x05,0x39,0x0e,0xcc,0xc1,0xfe,0xf4,0x2b
+
+# GFX12: v_pk_fma_f16 v5, 0.5, m0, 0.5 op_sel:[1,0,0] op_sel_hi:[0,1,1] neg_lo:[0,1,0] neg_hi:[0,1,0] ; encoding: [0x05,0x4a,0x0e,0xcc,0xf0,0xfa,0xc0,0x53]
+0x05,0x4a,0x0e,0xcc,0xf0,0xfa,0xc0,0x53
+
+# GFX12: v_pk_fma_f16 v5, src_scc, vcc_lo, -1 op_sel:[0,1,0] op_sel_hi:[1,0,1] neg_lo:[0,0,1] neg_hi:[0,0,1] ; encoding: [0x05,0x54,0x0e,0xcc,0xfd,0xd4,0x04,0x8b]
+0x05,0x54,0x0e,0xcc,0xfd,0xd4,0x04,0x8b
+
+# GFX12: v_pk_fma_f16 v255, 0xfe0b, vcc_hi, null op_sel:[0,0,1] op_sel_hi:[1,1,0] neg_lo:[1,1,1] neg_hi:[1,1,1] clamp ; encoding: [0xff,0xa7,0x0e,0xcc,0xff,0xd6,0xf0,0xf9,0x0b,0xfe,0x00,0x00]
+0xff,0xa7,0x0e,0xcc,0xff,0xd6,0xf0,0xf9,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_lshlrev_b16 v5, v1, v2             ; encoding: [0x05,0x40,0x04,0xcc,0x01,0x05,0x02,0x18]
+0x05,0x40,0x04,0xcc,0x01,0x05,0x02,0x18
+
+# GFX12: v_pk_lshlrev_b16 v5, v255, v255         ; encoding: [0x05,0x40,0x04,0xcc,0xff,0xff,0x03,0x18]
+0x05,0x40,0x04,0xcc,0xff,0xff,0x03,0x18
+
+# GFX12: v_pk_lshlrev_b16 v5, s1, s2             ; encoding: [0x05,0x40,0x04,0xcc,0x01,0x04,0x00,0x18]
+0x05,0x40,0x04,0xcc,0x01,0x04,0x00,0x18
+
+# GFX12: v_pk_lshlrev_b16 v5, s105, s105         ; encoding: [0x05,0x40,0x04,0xcc,0x69,0xd2,0x00,0x18]
+0x05,0x40,0x04,0xcc,0x69,0xd2,0x00,0x18
+
+# GFX12: v_pk_lshlrev_b16 v5, vcc_lo, ttmp15     ; encoding: [0x05,0x40,0x04,0xcc,0x6a,0xf6,0x00,0x18]
+0x05,0x40,0x04,0xcc,0x6a,0xf6,0x00,0x18
+
+# GFX12: v_pk_lshlrev_b16 v5, vcc_hi, 0xfe0b     ; encoding: [0x05,0x40,0x04,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+0x05,0x40,0x04,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_lshlrev_b16 v5, ttmp15, src_scc    ; encoding: [0x05,0x40,0x04,0xcc,0x7b,0xfa,0x01,0x18]
+0x05,0x40,0x04,0xcc,0x7b,0xfa,0x01,0x18
+
+# GFX12: v_pk_lshlrev_b16 v5, m0, 0x3800
+0x05,0x40,0x04,0xcc,0x7d,0xe0,0x01,0x18
+
+# GFX12: v_pk_lshlrev_b16 v5, exec_lo, -1        ; encoding: [0x05,0x40,0x04,0xcc,0x7e,0x82,0x01,0x18]
+0x05,0x40,0x04,0xcc,0x7e,0x82,0x01,0x18
+
+# GFX12: v_pk_lshlrev_b16 v5, exec_hi, null      ; encoding: [0x05,0x40,0x04,0xcc,0x7f,0xf8,0x00,0x18]
+0x05,0x40,0x04,0xcc,0x7f,0xf8,0x00,0x18
+
+# GFX12: v_pk_lshlrev_b16 v5, null, exec_lo      ; encoding: [0x05,0x40,0x04,0xcc,0x7c,0xfc,0x00,0x18]
+0x05,0x40,0x04,0xcc,0x7c,0xfc,0x00,0x18
+
+# GFX12: v_pk_lshlrev_b16 v5, -1, exec_hi        ; encoding: [0x05,0x40,0x04,0xcc,0xc1,0xfe,0x00,0x18]
+0x05,0x40,0x04,0xcc,0xc1,0xfe,0x00,0x18
+
+# GFX12: v_pk_lshlrev_b16 v5, 0x3800, m0 op_sel:[1,1] op_sel_hi:[0,0]
+0x05,0x58,0x04,0xcc,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_pk_lshlrev_b16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1] ; encoding: [0x05,0x48,0x04,0xcc,0xfd,0xd4,0x00,0x10]
+0x05,0x48,0x04,0xcc,0xfd,0xd4,0x00,0x10
+
+# GFX12: v_pk_lshlrev_b16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] ; encoding: [0xff,0x50,0x04,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00]
+0xff,0x50,0x04,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_lshrrev_b16 v5, v1, v2             ; encoding: [0x05,0x40,0x05,0xcc,0x01,0x05,0x02,0x18]
+0x05,0x40,0x05,0xcc,0x01,0x05,0x02,0x18
+
+# GFX12: v_pk_lshrrev_b16 v5, v255, v255         ; encoding: [0x05,0x40,0x05,0xcc,0xff,0xff,0x03,0x18]
+0x05,0x40,0x05,0xcc,0xff,0xff,0x03,0x18
+
+# GFX12: v_pk_lshrrev_b16 v5, s1, s2             ; encoding: [0x05,0x40,0x05,0xcc,0x01,0x04,0x00,0x18]
+0x05,0x40,0x05,0xcc,0x01,0x04,0x00,0x18
+
+# GFX12: v_pk_lshrrev_b16 v5, s105, s105         ; encoding: [0x05,0x40,0x05,0xcc,0x69,0xd2,0x00,0x18]
+0x05,0x40,0x05,0xcc,0x69,0xd2,0x00,0x18
+
+# GFX12: v_pk_lshrrev_b16 v5, vcc_lo, ttmp15     ; encoding: [0x05,0x40,0x05,0xcc,0x6a,0xf6,0x00,0x18]
+0x05,0x40,0x05,0xcc,0x6a,0xf6,0x00,0x18
+
+# GFX12: v_pk_lshrrev_b16 v5, vcc_hi, 0xfe0b     ; encoding: [0x05,0x40,0x05,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+0x05,0x40,0x05,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_lshrrev_b16 v5, ttmp15, src_scc    ; encoding: [0x05,0x40,0x05,0xcc,0x7b,0xfa,0x01,0x18]
+0x05,0x40,0x05,0xcc,0x7b,0xfa,0x01,0x18
+
+# GFX12: v_pk_lshrrev_b16 v5, m0, 0x3800
+0x05,0x40,0x05,0xcc,0x7d,0xe0,0x01,0x18
+
+# GFX12: v_pk_lshrrev_b16 v5, exec_lo, -1        ; encoding: [0x05,0x40,0x05,0xcc,0x7e,0x82,0x01,0x18]
+0x05,0x40,0x05,0xcc,0x7e,0x82,0x01,0x18
+
+# GFX12: v_pk_lshrrev_b16 v5, exec_hi, null      ; encoding: [0x05,0x40,0x05,0xcc,0x7f,0xf8,0x00,0x18]
+0x05,0x40,0x05,0xcc,0x7f,0xf8,0x00,0x18
+
+# GFX12: v_pk_lshrrev_b16 v5, null, exec_lo      ; encoding: [0x05,0x40,0x05,0xcc,0x7c,0xfc,0x00,0x18]
+0x05,0x40,0x05,0xcc,0x7c,0xfc,0x00,0x18
+
+# GFX12: v_pk_lshrrev_b16 v5, -1, exec_hi        ; encoding: [0x05,0x40,0x05,0xcc,0xc1,0xfe,0x00,0x18]
+0x05,0x40,0x05,0xcc,0xc1,0xfe,0x00,0x18
+
+# GFX12: v_pk_lshrrev_b16 v5, 0x3800, m0 op_sel:[1,1] op_sel_hi:[0,0]
+0x05,0x58,0x05,0xcc,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_pk_lshrrev_b16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1] ; encoding: [0x05,0x48,0x05,0xcc,0xfd,0xd4,0x00,0x10]
+0x05,0x48,0x05,0xcc,0xfd,0xd4,0x00,0x10
+
+# GFX12: v_pk_lshrrev_b16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] ; encoding: [0xff,0x50,0x05,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00]
+0xff,0x50,0x05,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_mad_i16 v5, v1, v2, s3             ; encoding: [0x05,0x40,0x00,0xcc,0x01,0x05,0x0e,0x18]
+0x05,0x40,0x00,0xcc,0x01,0x05,0x0e,0x18
+
+# GFX12: v_pk_mad_i16 v5, v255, s2, s105         ; encoding: [0x05,0x40,0x00,0xcc,0xff,0x05,0xa4,0x19]
+0x05,0x40,0x00,0xcc,0xff,0x05,0xa4,0x19
+
+# GFX12: v_pk_mad_i16 v5, s1, v255, exec_hi      ; encoding: [0x05,0x40,0x00,0xcc,0x01,0xfe,0xff,0x19]
+0x05,0x40,0x00,0xcc,0x01,0xfe,0xff,0x19
+
+# GFX12: v_pk_mad_i16 v5, s105, s105, exec_lo    ; encoding: [0x05,0x40,0x00,0xcc,0x69,0xd2,0xf8,0x19]
+0x05,0x40,0x00,0xcc,0x69,0xd2,0xf8,0x19
+
+# GFX12: v_pk_mad_i16 v5, vcc_lo, ttmp15, v3     ; encoding: [0x05,0x40,0x00,0xcc,0x6a,0xf6,0x0c,0x1c]
+0x05,0x40,0x00,0xcc,0x6a,0xf6,0x0c,0x1c
+
+# GFX12: v_pk_mad_i16 v5, vcc_hi, 0xfe0b, v255   ; encoding: [0x05,0x40,0x00,0xcc,0x6b,0xfe,0xfd,0x1f,0x0b,0xfe,0x00,0x00]
+0x05,0x40,0x00,0xcc,0x6b,0xfe,0xfd,0x1f,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_mad_i16 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x40,0x00,0xcc,0x7b,0xfa,0xed,0x19]
+0x05,0x40,0x00,0xcc,0x7b,0xfa,0xed,0x19
+
+# GFX12: v_pk_mad_i16 v5, m0, 0x3800, m0
+0x05,0x40,0x00,0xcc,0x7d,0xe0,0xf5,0x19
+
+# GFX12: v_pk_mad_i16 v5, exec_lo, -1, vcc_hi op_sel_hi:[0,0,0] ; encoding: [0x05,0x00,0x00,0xcc,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x00,0xcc,0x7e,0x82,0xad,0x01
+
+# GFX12: v_pk_mad_i16 v5, exec_hi, null, vcc_lo op_sel_hi:[0,0,1] ; encoding: [0x05,0x40,0x00,0xcc,0x7f,0xf8,0xa8,0x01]
+0x05,0x40,0x00,0xcc,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_pk_mad_i16 v5, null, exec_lo, 0xfe0b op_sel_hi:[0,1,0] ; encoding: [0x05,0x00,0x00,0xcc,0x7c,0xfc,0xfc,0x13,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x00,0xcc,0x7c,0xfc,0xfc,0x13,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_mad_i16 v5, -1, exec_hi, src_scc op_sel:[1,1,1] op_sel_hi:[1,0,0] ; encoding: [0x05,0x38,0x00,0xcc,0xc1,0xfe,0xf4,0x0b]
+0x05,0x38,0x00,0xcc,0xc1,0xfe,0xf4,0x0b
+
+# GFX12: v_pk_mad_i16 v5, 0x3800, m0, 0x3800 op_sel:[1,0,0] op_sel_hi:[0,1,1]
+0x05,0x48,0x00,0xcc,0xf0,0xfa,0xc0,0x13
+
+# GFX12: v_pk_mad_i16 v5, src_scc, vcc_lo, -1 op_sel:[0,1,0] op_sel_hi:[1,0,1] ; encoding: [0x05,0x50,0x00,0xcc,0xfd,0xd4,0x04,0x0b]
+0x05,0x50,0x00,0xcc,0xfd,0xd4,0x04,0x0b
+
+# GFX12: v_pk_mad_i16 v255, 0xfe0b, vcc_hi, null op_sel:[0,0,1] op_sel_hi:[1,1,0] clamp ; encoding: [0xff,0xa0,0x00,0xcc,0xff,0xd6,0xf0,0x19,0x0b,0xfe,0x00,0x00]
+0xff,0xa0,0x00,0xcc,0xff,0xd6,0xf0,0x19,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_mad_u16 v5, v1, v2, s3             ; encoding: [0x05,0x40,0x09,0xcc,0x01,0x05,0x0e,0x18]
+0x05,0x40,0x09,0xcc,0x01,0x05,0x0e,0x18
+
+# GFX12: v_pk_mad_u16 v5, v255, s2, s105         ; encoding: [0x05,0x40,0x09,0xcc,0xff,0x05,0xa4,0x19]
+0x05,0x40,0x09,0xcc,0xff,0x05,0xa4,0x19
+
+# GFX12: v_pk_mad_u16 v5, s1, v255, exec_hi      ; encoding: [0x05,0x40,0x09,0xcc,0x01,0xfe,0xff,0x19]
+0x05,0x40,0x09,0xcc,0x01,0xfe,0xff,0x19
+
+# GFX12: v_pk_mad_u16 v5, s105, s105, exec_lo    ; encoding: [0x05,0x40,0x09,0xcc,0x69,0xd2,0xf8,0x19]
+0x05,0x40,0x09,0xcc,0x69,0xd2,0xf8,0x19
+
+# GFX12: v_pk_mad_u16 v5, vcc_lo, ttmp15, v3     ; encoding: [0x05,0x40,0x09,0xcc,0x6a,0xf6,0x0c,0x1c]
+0x05,0x40,0x09,0xcc,0x6a,0xf6,0x0c,0x1c
+
+# GFX12: v_pk_mad_u16 v5, vcc_hi, 0xfe0b, v255   ; encoding: [0x05,0x40,0x09,0xcc,0x6b,0xfe,0xfd,0x1f,0x0b,0xfe,0x00,0x00]
+0x05,0x40,0x09,0xcc,0x6b,0xfe,0xfd,0x1f,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_mad_u16 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x40,0x09,0xcc,0x7b,0xfa,0xed,0x19]
+0x05,0x40,0x09,0xcc,0x7b,0xfa,0xed,0x19
+
+# GFX12: v_pk_mad_u16 v5, m0, 0x3800, m0
+0x05,0x40,0x09,0xcc,0x7d,0xe0,0xf5,0x19
+
+# GFX12: v_pk_mad_u16 v5, exec_lo, -1, vcc_hi op_sel_hi:[0,0,0] ; encoding: [0x05,0x00,0x09,0xcc,0x7e,0x82,0xad,0x01]
+0x05,0x00,0x09,0xcc,0x7e,0x82,0xad,0x01
+
+# GFX12: v_pk_mad_u16 v5, exec_hi, null, vcc_lo op_sel_hi:[0,0,1] ; encoding: [0x05,0x40,0x09,0xcc,0x7f,0xf8,0xa8,0x01]
+0x05,0x40,0x09,0xcc,0x7f,0xf8,0xa8,0x01
+
+# GFX12: v_pk_mad_u16 v5, null, exec_lo, 0xfe0b op_sel_hi:[0,1,0] ; encoding: [0x05,0x00,0x09,0xcc,0x7c,0xfc,0xfc,0x13,0x0b,0xfe,0x00,0x00]
+0x05,0x00,0x09,0xcc,0x7c,0xfc,0xfc,0x13,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_mad_u16 v5, -1, exec_hi, src_scc op_sel:[1,1,1] op_sel_hi:[1,0,0] ; encoding: [0x05,0x38,0x09,0xcc,0xc1,0xfe,0xf4,0x0b]
+0x05,0x38,0x09,0xcc,0xc1,0xfe,0xf4,0x0b
+
+# GFX12: v_pk_mad_u16 v5, 0x3800, m0, 0x3800 op_sel:[1,0,0] op_sel_hi:[0,1,1]
+0x05,0x48,0x09,0xcc,0xf0,0xfa,0xc0,0x13
+
+# GFX12: v_pk_mad_u16 v5, src_scc, vcc_lo, -1 op_sel:[0,1,0] op_sel_hi:[1,0,1] ; encoding: [0x05,0x50,0x09,0xcc,0xfd,0xd4,0x04,0x0b]
+0x05,0x50,0x09,0xcc,0xfd,0xd4,0x04,0x0b
+
+# GFX12: v_pk_mad_u16 v255, 0xfe0b, vcc_hi, null op_sel:[0,0,1] op_sel_hi:[1,1,0] clamp ; encoding: [0xff,0xa0,0x09,0xcc,0xff,0xd6,0xf0,0x19,0x0b,0xfe,0x00,0x00]
+0xff,0xa0,0x09,0xcc,0xff,0xd6,0xf0,0x19,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_max_num_f16 v5, v1, v2             ; encoding: [0x05,0x40,0x1c,0xcc,0x01,0x05,0x02,0x18]
+0x05,0x40,0x1c,0xcc,0x01,0x05,0x02,0x18
+
+# GFX12: v_pk_max_num_f16 v5, v255, v255         ; encoding: [0x05,0x40,0x1c,0xcc,0xff,0xff,0x03,0x18]
+0x05,0x40,0x1c,0xcc,0xff,0xff,0x03,0x18
+
+# GFX12: v_pk_max_num_f16 v5, s1, s2             ; encoding: [0x05,0x40,0x1c,0xcc,0x01,0x04,0x00,0x18]
+0x05,0x40,0x1c,0xcc,0x01,0x04,0x00,0x18
+
+# GFX12: v_pk_max_num_f16 v5, s105, s105         ; encoding: [0x05,0x40,0x1c,0xcc,0x69,0xd2,0x00,0x18]
+0x05,0x40,0x1c,0xcc,0x69,0xd2,0x00,0x18
+
+# GFX12: v_pk_max_num_f16 v5, vcc_lo, ttmp15     ; encoding: [0x05,0x40,0x1c,0xcc,0x6a,0xf6,0x00,0x18]
+0x05,0x40,0x1c,0xcc,0x6a,0xf6,0x00,0x18
+
+# GFX12: v_pk_max_num_f16 v5, vcc_hi, 0xfe0b     ; encoding: [0x05,0x40,0x1c,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+0x05,0x40,0x1c,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_max_num_f16 v5, ttmp15, src_scc    ; encoding: [0x05,0x40,0x1c,0xcc,0x7b,0xfa,0x01,0x18]
+0x05,0x40,0x1c,0xcc,0x7b,0xfa,0x01,0x18
+
+# GFX12: v_pk_max_num_f16 v5, m0, 0.5            ; encoding: [0x05,0x40,0x1c,0xcc,0x7d,0xe0,0x01,0x18]
+0x05,0x40,0x1c,0xcc,0x7d,0xe0,0x01,0x18
+
+# GFX12: v_pk_max_num_f16 v5, exec_lo, -1        ; encoding: [0x05,0x40,0x1c,0xcc,0x7e,0x82,0x01,0x18]
+0x05,0x40,0x1c,0xcc,0x7e,0x82,0x01,0x18
+
+# GFX12: v_pk_max_num_f16 v5, exec_hi, null      ; encoding: [0x05,0x40,0x1c,0xcc,0x7f,0xf8,0x00,0x18]
+0x05,0x40,0x1c,0xcc,0x7f,0xf8,0x00,0x18
+
+# GFX12: v_pk_max_num_f16 v5, null, exec_lo      ; encoding: [0x05,0x40,0x1c,0xcc,0x7c,0xfc,0x00,0x18]
+0x05,0x40,0x1c,0xcc,0x7c,0xfc,0x00,0x18
+
+# GFX12: v_pk_max_num_f16 v5, -1, exec_hi        ; encoding: [0x05,0x40,0x1c,0xcc,0xc1,0xfe,0x00,0x18]
+0x05,0x40,0x1c,0xcc,0xc1,0xfe,0x00,0x18
+
+# GFX12: v_pk_max_num_f16 v5, 0.5, m0 op_sel:[1,1] op_sel_hi:[0,0] neg_lo:[1,0] neg_hi:[1,0] ; encoding: [0x05,0x59,0x1c,0xcc,0xf0,0xfa,0x00,0x20]
+0x05,0x59,0x1c,0xcc,0xf0,0xfa,0x00,0x20
+
+# GFX12: v_pk_max_num_f16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1] neg_lo:[0,1] neg_hi:[0,1] ; encoding: [0x05,0x4a,0x1c,0xcc,0xfd,0xd4,0x00,0x50]
+0x05,0x4a,0x1c,0xcc,0xfd,0xd4,0x00,0x50
+
+# GFX12: v_pk_max_num_f16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] neg_lo:[1,1] neg_hi:[1,1] clamp ; encoding: [0xff,0xd3,0x1c,0xcc,0xff,0xd6,0x00,0x68,0x0b,0xfe,0x00,0x00]
+0xff,0xd3,0x1c,0xcc,0xff,0xd6,0x00,0x68,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_max_i16 v5, v1, v2                 ; encoding: [0x05,0x40,0x07,0xcc,0x01,0x05,0x02,0x18]
+0x05,0x40,0x07,0xcc,0x01,0x05,0x02,0x18
+
+# GFX12: v_pk_max_i16 v5, v255, v255             ; encoding: [0x05,0x40,0x07,0xcc,0xff,0xff,0x03,0x18]
+0x05,0x40,0x07,0xcc,0xff,0xff,0x03,0x18
+
+# GFX12: v_pk_max_i16 v5, s1, s2                 ; encoding: [0x05,0x40,0x07,0xcc,0x01,0x04,0x00,0x18]
+0x05,0x40,0x07,0xcc,0x01,0x04,0x00,0x18
+
+# GFX12: v_pk_max_i16 v5, s105, s105             ; encoding: [0x05,0x40,0x07,0xcc,0x69,0xd2,0x00,0x18]
+0x05,0x40,0x07,0xcc,0x69,0xd2,0x00,0x18
+
+# GFX12: v_pk_max_i16 v5, vcc_lo, ttmp15         ; encoding: [0x05,0x40,0x07,0xcc,0x6a,0xf6,0x00,0x18]
+0x05,0x40,0x07,0xcc,0x6a,0xf6,0x00,0x18
+
+# GFX12: v_pk_max_i16 v5, vcc_hi, 0xfe0b         ; encoding: [0x05,0x40,0x07,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+0x05,0x40,0x07,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_max_i16 v5, ttmp15, src_scc        ; encoding: [0x05,0x40,0x07,0xcc,0x7b,0xfa,0x01,0x18]
+0x05,0x40,0x07,0xcc,0x7b,0xfa,0x01,0x18
+
+# GFX12: v_pk_max_i16 v5, m0, 0x3800
+0x05,0x40,0x07,0xcc,0x7d,0xe0,0x01,0x18
+
+# GFX12: v_pk_max_i16 v5, exec_lo, -1            ; encoding: [0x05,0x40,0x07,0xcc,0x7e,0x82,0x01,0x18]
+0x05,0x40,0x07,0xcc,0x7e,0x82,0x01,0x18
+
+# GFX12: v_pk_max_i16 v5, exec_hi, null          ; encoding: [0x05,0x40,0x07,0xcc,0x7f,0xf8,0x00,0x18]
+0x05,0x40,0x07,0xcc,0x7f,0xf8,0x00,0x18
+
+# GFX12: v_pk_max_i16 v5, null, exec_lo          ; encoding: [0x05,0x40,0x07,0xcc,0x7c,0xfc,0x00,0x18]
+0x05,0x40,0x07,0xcc,0x7c,0xfc,0x00,0x18
+
+# GFX12: v_pk_max_i16 v5, -1, exec_hi            ; encoding: [0x05,0x40,0x07,0xcc,0xc1,0xfe,0x00,0x18]
+0x05,0x40,0x07,0xcc,0xc1,0xfe,0x00,0x18
+
+# GFX12: v_pk_max_i16 v5, 0x3800, m0 op_sel:[1,1] op_sel_hi:[0,0]
+0x05,0x58,0x07,0xcc,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_pk_max_i16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1] ; encoding: [0x05,0x48,0x07,0xcc,0xfd,0xd4,0x00,0x10]
+0x05,0x48,0x07,0xcc,0xfd,0xd4,0x00,0x10
+
+# GFX12: v_pk_max_i16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] ; encoding: [0xff,0x50,0x07,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00]
+0xff,0x50,0x07,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_max_u16 v5, v1, v2                 ; encoding: [0x05,0x40,0x0c,0xcc,0x01,0x05,0x02,0x18]
+0x05,0x40,0x0c,0xcc,0x01,0x05,0x02,0x18
+
+# GFX12: v_pk_max_u16 v5, v255, v255             ; encoding: [0x05,0x40,0x0c,0xcc,0xff,0xff,0x03,0x18]
+0x05,0x40,0x0c,0xcc,0xff,0xff,0x03,0x18
+
+# GFX12: v_pk_max_u16 v5, s1, s2                 ; encoding: [0x05,0x40,0x0c,0xcc,0x01,0x04,0x00,0x18]
+0x05,0x40,0x0c,0xcc,0x01,0x04,0x00,0x18
+
+# GFX12: v_pk_max_u16 v5, s105, s105             ; encoding: [0x05,0x40,0x0c,0xcc,0x69,0xd2,0x00,0x18]
+0x05,0x40,0x0c,0xcc,0x69,0xd2,0x00,0x18
+
+# GFX12: v_pk_max_u16 v5, vcc_lo, ttmp15         ; encoding: [0x05,0x40,0x0c,0xcc,0x6a,0xf6,0x00,0x18]
+0x05,0x40,0x0c,0xcc,0x6a,0xf6,0x00,0x18
+
+# GFX12: v_pk_max_u16 v5, vcc_hi, 0xfe0b         ; encoding: [0x05,0x40,0x0c,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+0x05,0x40,0x0c,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_max_u16 v5, ttmp15, src_scc        ; encoding: [0x05,0x40,0x0c,0xcc,0x7b,0xfa,0x01,0x18]
+0x05,0x40,0x0c,0xcc,0x7b,0xfa,0x01,0x18
+
+# GFX12: v_pk_max_u16 v5, m0, 0x3800
+0x05,0x40,0x0c,0xcc,0x7d,0xe0,0x01,0x18
+
+# GFX12: v_pk_max_u16 v5, exec_lo, -1            ; encoding: [0x05,0x40,0x0c,0xcc,0x7e,0x82,0x01,0x18]
+0x05,0x40,0x0c,0xcc,0x7e,0x82,0x01,0x18
+
+# GFX12: v_pk_max_u16 v5, exec_hi, null          ; encoding: [0x05,0x40,0x0c,0xcc,0x7f,0xf8,0x00,0x18]
+0x05,0x40,0x0c,0xcc,0x7f,0xf8,0x00,0x18
+
+# GFX12: v_pk_max_u16 v5, null, exec_lo          ; encoding: [0x05,0x40,0x0c,0xcc,0x7c,0xfc,0x00,0x18]
+0x05,0x40,0x0c,0xcc,0x7c,0xfc,0x00,0x18
+
+# GFX12: v_pk_max_u16 v5, -1, exec_hi            ; encoding: [0x05,0x40,0x0c,0xcc,0xc1,0xfe,0x00,0x18]
+0x05,0x40,0x0c,0xcc,0xc1,0xfe,0x00,0x18
+
+# GFX12: v_pk_max_u16 v5, 0x3800, m0 op_sel:[1,1] op_sel_hi:[0,0]
+0x05,0x58,0x0c,0xcc,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_pk_max_u16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1] ; encoding: [0x05,0x48,0x0c,0xcc,0xfd,0xd4,0x00,0x10]
+0x05,0x48,0x0c,0xcc,0xfd,0xd4,0x00,0x10
+
+# GFX12: v_pk_max_u16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] ; encoding: [0xff,0x50,0x0c,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00]
+0xff,0x50,0x0c,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_min_num_f16 v5, v1, v2             ; encoding: [0x05,0x40,0x1b,0xcc,0x01,0x05,0x02,0x18]
+0x05,0x40,0x1b,0xcc,0x01,0x05,0x02,0x18
+
+# GFX12: v_pk_min_num_f16 v5, v255, v255         ; encoding: [0x05,0x40,0x1b,0xcc,0xff,0xff,0x03,0x18]
+0x05,0x40,0x1b,0xcc,0xff,0xff,0x03,0x18
+
+# GFX12: v_pk_min_num_f16 v5, s1, s2             ; encoding: [0x05,0x40,0x1b,0xcc,0x01,0x04,0x00,0x18]
+0x05,0x40,0x1b,0xcc,0x01,0x04,0x00,0x18
+
+# GFX12: v_pk_min_num_f16 v5, s105, s105         ; encoding: [0x05,0x40,0x1b,0xcc,0x69,0xd2,0x00,0x18]
+0x05,0x40,0x1b,0xcc,0x69,0xd2,0x00,0x18
+
+# GFX12: v_pk_min_num_f16 v5, vcc_lo, ttmp15     ; encoding: [0x05,0x40,0x1b,0xcc,0x6a,0xf6,0x00,0x18]
+0x05,0x40,0x1b,0xcc,0x6a,0xf6,0x00,0x18
+
+# GFX12: v_pk_min_num_f16 v5, vcc_hi, 0xfe0b     ; encoding: [0x05,0x40,0x1b,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+0x05,0x40,0x1b,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_min_num_f16 v5, ttmp15, src_scc    ; encoding: [0x05,0x40,0x1b,0xcc,0x7b,0xfa,0x01,0x18]
+0x05,0x40,0x1b,0xcc,0x7b,0xfa,0x01,0x18
+
+# GFX12: v_pk_min_num_f16 v5, m0, 0.5            ; encoding: [0x05,0x40,0x1b,0xcc,0x7d,0xe0,0x01,0x18]
+0x05,0x40,0x1b,0xcc,0x7d,0xe0,0x01,0x18
+
+# GFX12: v_pk_min_num_f16 v5, exec_lo, -1        ; encoding: [0x05,0x40,0x1b,0xcc,0x7e,0x82,0x01,0x18]
+0x05,0x40,0x1b,0xcc,0x7e,0x82,0x01,0x18
+
+# GFX12: v_pk_min_num_f16 v5, exec_hi, null      ; encoding: [0x05,0x40,0x1b,0xcc,0x7f,0xf8,0x00,0x18]
+0x05,0x40,0x1b,0xcc,0x7f,0xf8,0x00,0x18
+
+# GFX12: v_pk_min_num_f16 v5, null, exec_lo      ; encoding: [0x05,0x40,0x1b,0xcc,0x7c,0xfc,0x00,0x18]
+0x05,0x40,0x1b,0xcc,0x7c,0xfc,0x00,0x18
+
+# GFX12: v_pk_min_num_f16 v5, -1, exec_hi        ; encoding: [0x05,0x40,0x1b,0xcc,0xc1,0xfe,0x00,0x18]
+0x05,0x40,0x1b,0xcc,0xc1,0xfe,0x00,0x18
+
+# GFX12: v_pk_min_num_f16 v5, 0.5, m0 op_sel:[1,1] op_sel_hi:[0,0] neg_lo:[1,0] neg_hi:[1,0] ; encoding: [0x05,0x59,0x1b,0xcc,0xf0,0xfa,0x00,0x20]
+0x05,0x59,0x1b,0xcc,0xf0,0xfa,0x00,0x20
+
+# GFX12: v_pk_min_num_f16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1] neg_lo:[0,1] neg_hi:[0,1] ; encoding: [0x05,0x4a,0x1b,0xcc,0xfd,0xd4,0x00,0x50]
+0x05,0x4a,0x1b,0xcc,0xfd,0xd4,0x00,0x50
+
+# GFX12: v_pk_min_num_f16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] neg_lo:[1,1] neg_hi:[1,1] clamp ; encoding: [0xff,0xd3,0x1b,0xcc,0xff,0xd6,0x00,0x68,0x0b,0xfe,0x00,0x00]
+0xff,0xd3,0x1b,0xcc,0xff,0xd6,0x00,0x68,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_min_i16 v5, v1, v2                 ; encoding: [0x05,0x40,0x08,0xcc,0x01,0x05,0x02,0x18]
+0x05,0x40,0x08,0xcc,0x01,0x05,0x02,0x18
+
+# GFX12: v_pk_min_i16 v5, v255, v255             ; encoding: [0x05,0x40,0x08,0xcc,0xff,0xff,0x03,0x18]
+0x05,0x40,0x08,0xcc,0xff,0xff,0x03,0x18
+
+# GFX12: v_pk_min_i16 v5, s1, s2                 ; encoding: [0x05,0x40,0x08,0xcc,0x01,0x04,0x00,0x18]
+0x05,0x40,0x08,0xcc,0x01,0x04,0x00,0x18
+
+# GFX12: v_pk_min_i16 v5, s105, s105             ; encoding: [0x05,0x40,0x08,0xcc,0x69,0xd2,0x00,0x18]
+0x05,0x40,0x08,0xcc,0x69,0xd2,0x00,0x18
+
+# GFX12: v_pk_min_i16 v5, vcc_lo, ttmp15         ; encoding: [0x05,0x40,0x08,0xcc,0x6a,0xf6,0x00,0x18]
+0x05,0x40,0x08,0xcc,0x6a,0xf6,0x00,0x18
+
+# GFX12: v_pk_min_i16 v5, vcc_hi, 0xfe0b         ; encoding: [0x05,0x40,0x08,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+0x05,0x40,0x08,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_min_i16 v5, ttmp15, src_scc        ; encoding: [0x05,0x40,0x08,0xcc,0x7b,0xfa,0x01,0x18]
+0x05,0x40,0x08,0xcc,0x7b,0xfa,0x01,0x18
+
+# GFX12: v_pk_min_i16 v5, m0, 0x3800
+0x05,0x40,0x08,0xcc,0x7d,0xe0,0x01,0x18
+
+# GFX12: v_pk_min_i16 v5, exec_lo, -1            ; encoding: [0x05,0x40,0x08,0xcc,0x7e,0x82,0x01,0x18]
+0x05,0x40,0x08,0xcc,0x7e,0x82,0x01,0x18
+
+# GFX12: v_pk_min_i16 v5, exec_hi, null          ; encoding: [0x05,0x40,0x08,0xcc,0x7f,0xf8,0x00,0x18]
+0x05,0x40,0x08,0xcc,0x7f,0xf8,0x00,0x18
+
+# GFX12: v_pk_min_i16 v5, null, exec_lo          ; encoding: [0x05,0x40,0x08,0xcc,0x7c,0xfc,0x00,0x18]
+0x05,0x40,0x08,0xcc,0x7c,0xfc,0x00,0x18
+
+# GFX12: v_pk_min_i16 v5, -1, exec_hi            ; encoding: [0x05,0x40,0x08,0xcc,0xc1,0xfe,0x00,0x18]
+0x05,0x40,0x08,0xcc,0xc1,0xfe,0x00,0x18
+
+# GFX12: v_pk_min_i16 v5, 0x3800, m0 op_sel:[1,1] op_sel_hi:[0,0]
+0x05,0x58,0x08,0xcc,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_pk_min_i16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1] ; encoding: [0x05,0x48,0x08,0xcc,0xfd,0xd4,0x00,0x10]
+0x05,0x48,0x08,0xcc,0xfd,0xd4,0x00,0x10
+
+# GFX12: v_pk_min_i16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] ; encoding: [0xff,0x50,0x08,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00]
+0xff,0x50,0x08,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_min_u16 v5, v1, v2                 ; encoding: [0x05,0x40,0x0d,0xcc,0x01,0x05,0x02,0x18]
+0x05,0x40,0x0d,0xcc,0x01,0x05,0x02,0x18
+
+# GFX12: v_pk_min_u16 v5, v255, v255             ; encoding: [0x05,0x40,0x0d,0xcc,0xff,0xff,0x03,0x18]
+0x05,0x40,0x0d,0xcc,0xff,0xff,0x03,0x18
+
+# GFX12: v_pk_min_u16 v5, s1, s2                 ; encoding: [0x05,0x40,0x0d,0xcc,0x01,0x04,0x00,0x18]
+0x05,0x40,0x0d,0xcc,0x01,0x04,0x00,0x18
+
+# GFX12: v_pk_min_u16 v5, s105, s105             ; encoding: [0x05,0x40,0x0d,0xcc,0x69,0xd2,0x00,0x18]
+0x05,0x40,0x0d,0xcc,0x69,0xd2,0x00,0x18
+
+# GFX12: v_pk_min_u16 v5, vcc_lo, ttmp15         ; encoding: [0x05,0x40,0x0d,0xcc,0x6a,0xf6,0x00,0x18]
+0x05,0x40,0x0d,0xcc,0x6a,0xf6,0x00,0x18
+
+# GFX12: v_pk_min_u16 v5, vcc_hi, 0xfe0b         ; encoding: [0x05,0x40,0x0d,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+0x05,0x40,0x0d,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_min_u16 v5, ttmp15, src_scc        ; encoding: [0x05,0x40,0x0d,0xcc,0x7b,0xfa,0x01,0x18]
+0x05,0x40,0x0d,0xcc,0x7b,0xfa,0x01,0x18
+
+# GFX12: v_pk_min_u16 v5, m0, 0x3800
+0x05,0x40,0x0d,0xcc,0x7d,0xe0,0x01,0x18
+
+# GFX12: v_pk_min_u16 v5, exec_lo, -1            ; encoding: [0x05,0x40,0x0d,0xcc,0x7e,0x82,0x01,0x18]
+0x05,0x40,0x0d,0xcc,0x7e,0x82,0x01,0x18
+
+# GFX12: v_pk_min_u16 v5, exec_hi, null          ; encoding: [0x05,0x40,0x0d,0xcc,0x7f,0xf8,0x00,0x18]
+0x05,0x40,0x0d,0xcc,0x7f,0xf8,0x00,0x18
+
+# GFX12: v_pk_min_u16 v5, null, exec_lo          ; encoding: [0x05,0x40,0x0d,0xcc,0x7c,0xfc,0x00,0x18]
+0x05,0x40,0x0d,0xcc,0x7c,0xfc,0x00,0x18
+
+# GFX12: v_pk_min_u16 v5, -1, exec_hi            ; encoding: [0x05,0x40,0x0d,0xcc,0xc1,0xfe,0x00,0x18]
+0x05,0x40,0x0d,0xcc,0xc1,0xfe,0x00,0x18
+
+# GFX12: v_pk_min_u16 v5, 0x3800, m0 op_sel:[1,1] op_sel_hi:[0,0]
+0x05,0x58,0x0d,0xcc,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_pk_min_u16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1] ; encoding: [0x05,0x48,0x0d,0xcc,0xfd,0xd4,0x00,0x10]
+0x05,0x48,0x0d,0xcc,0xfd,0xd4,0x00,0x10
+
+# GFX12: v_pk_min_u16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] ; encoding: [0xff,0x50,0x0d,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00]
+0xff,0x50,0x0d,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_mul_f16 v5, v1, v2                 ; encoding: [0x05,0x40,0x10,0xcc,0x01,0x05,0x02,0x18]
+0x05,0x40,0x10,0xcc,0x01,0x05,0x02,0x18
+
+# GFX12: v_pk_mul_f16 v5, v255, v255             ; encoding: [0x05,0x40,0x10,0xcc,0xff,0xff,0x03,0x18]
+0x05,0x40,0x10,0xcc,0xff,0xff,0x03,0x18
+
+# GFX12: v_pk_mul_f16 v5, s1, s2                 ; encoding: [0x05,0x40,0x10,0xcc,0x01,0x04,0x00,0x18]
+0x05,0x40,0x10,0xcc,0x01,0x04,0x00,0x18
+
+# GFX12: v_pk_mul_f16 v5, s105, s105             ; encoding: [0x05,0x40,0x10,0xcc,0x69,0xd2,0x00,0x18]
+0x05,0x40,0x10,0xcc,0x69,0xd2,0x00,0x18
+
+# GFX12: v_pk_mul_f16 v5, vcc_lo, ttmp15         ; encoding: [0x05,0x40,0x10,0xcc,0x6a,0xf6,0x00,0x18]
+0x05,0x40,0x10,0xcc,0x6a,0xf6,0x00,0x18
+
+# GFX12: v_pk_mul_f16 v5, vcc_hi, 0xfe0b         ; encoding: [0x05,0x40,0x10,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+0x05,0x40,0x10,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_mul_f16 v5, ttmp15, src_scc        ; encoding: [0x05,0x40,0x10,0xcc,0x7b,0xfa,0x01,0x18]
+0x05,0x40,0x10,0xcc,0x7b,0xfa,0x01,0x18
+
+# GFX12: v_pk_mul_f16 v5, m0, 0.5                ; encoding: [0x05,0x40,0x10,0xcc,0x7d,0xe0,0x01,0x18]
+0x05,0x40,0x10,0xcc,0x7d,0xe0,0x01,0x18
+
+# GFX12: v_pk_mul_f16 v5, exec_lo, -1            ; encoding: [0x05,0x40,0x10,0xcc,0x7e,0x82,0x01,0x18]
+0x05,0x40,0x10,0xcc,0x7e,0x82,0x01,0x18
+
+# GFX12: v_pk_mul_f16 v5, exec_hi, null          ; encoding: [0x05,0x40,0x10,0xcc,0x7f,0xf8,0x00,0x18]
+0x05,0x40,0x10,0xcc,0x7f,0xf8,0x00,0x18
+
+# GFX12: v_pk_mul_f16 v5, null, exec_lo          ; encoding: [0x05,0x40,0x10,0xcc,0x7c,0xfc,0x00,0x18]
+0x05,0x40,0x10,0xcc,0x7c,0xfc,0x00,0x18
+
+# GFX12: v_pk_mul_f16 v5, -1, exec_hi            ; encoding: [0x05,0x40,0x10,0xcc,0xc1,0xfe,0x00,0x18]
+0x05,0x40,0x10,0xcc,0xc1,0xfe,0x00,0x18
+
+# GFX12: v_pk_mul_f16 v5, 0.5, m0 op_sel:[1,1] op_sel_hi:[0,0] neg_lo:[1,0] neg_hi:[1,0] ; encoding: [0x05,0x59,0x10,0xcc,0xf0,0xfa,0x00,0x20]
+0x05,0x59,0x10,0xcc,0xf0,0xfa,0x00,0x20
+
+# GFX12: v_pk_mul_f16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1] neg_lo:[0,1] neg_hi:[0,1] ; encoding: [0x05,0x4a,0x10,0xcc,0xfd,0xd4,0x00,0x50]
+0x05,0x4a,0x10,0xcc,0xfd,0xd4,0x00,0x50
+
+# GFX12: v_pk_mul_f16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] neg_lo:[1,1] neg_hi:[1,1] clamp ; encoding: [0xff,0xd3,0x10,0xcc,0xff,0xd6,0x00,0x68,0x0b,0xfe,0x00,0x00]
+0xff,0xd3,0x10,0xcc,0xff,0xd6,0x00,0x68,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_mul_lo_u16 v5, v1, v2              ; encoding: [0x05,0x40,0x01,0xcc,0x01,0x05,0x02,0x18]
+0x05,0x40,0x01,0xcc,0x01,0x05,0x02,0x18
+
+# GFX12: v_pk_mul_lo_u16 v5, v255, v255          ; encoding: [0x05,0x40,0x01,0xcc,0xff,0xff,0x03,0x18]
+0x05,0x40,0x01,0xcc,0xff,0xff,0x03,0x18
+
+# GFX12: v_pk_mul_lo_u16 v5, s1, s2              ; encoding: [0x05,0x40,0x01,0xcc,0x01,0x04,0x00,0x18]
+0x05,0x40,0x01,0xcc,0x01,0x04,0x00,0x18
+
+# GFX12: v_pk_mul_lo_u16 v5, s105, s105          ; encoding: [0x05,0x40,0x01,0xcc,0x69,0xd2,0x00,0x18]
+0x05,0x40,0x01,0xcc,0x69,0xd2,0x00,0x18
+
+# GFX12: v_pk_mul_lo_u16 v5, vcc_lo, ttmp15      ; encoding: [0x05,0x40,0x01,0xcc,0x6a,0xf6,0x00,0x18]
+0x05,0x40,0x01,0xcc,0x6a,0xf6,0x00,0x18
+
+# GFX12: v_pk_mul_lo_u16 v5, vcc_hi, 0xfe0b      ; encoding: [0x05,0x40,0x01,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+0x05,0x40,0x01,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_mul_lo_u16 v5, ttmp15, src_scc     ; encoding: [0x05,0x40,0x01,0xcc,0x7b,0xfa,0x01,0x18]
+0x05,0x40,0x01,0xcc,0x7b,0xfa,0x01,0x18
+
+# GFX12: v_pk_mul_lo_u16 v5, m0, 0x3800
+0x05,0x40,0x01,0xcc,0x7d,0xe0,0x01,0x18
+
+# GFX12: v_pk_mul_lo_u16 v5, exec_lo, -1         ; encoding: [0x05,0x40,0x01,0xcc,0x7e,0x82,0x01,0x18]
+0x05,0x40,0x01,0xcc,0x7e,0x82,0x01,0x18
+
+# GFX12: v_pk_mul_lo_u16 v5, exec_hi, null       ; encoding: [0x05,0x40,0x01,0xcc,0x7f,0xf8,0x00,0x18]
+0x05,0x40,0x01,0xcc,0x7f,0xf8,0x00,0x18
+
+# GFX12: v_pk_mul_lo_u16 v5, null, exec_lo       ; encoding: [0x05,0x40,0x01,0xcc,0x7c,0xfc,0x00,0x18]
+0x05,0x40,0x01,0xcc,0x7c,0xfc,0x00,0x18
+
+# GFX12: v_pk_mul_lo_u16 v5, -1, exec_hi         ; encoding: [0x05,0x40,0x01,0xcc,0xc1,0xfe,0x00,0x18]
+0x05,0x40,0x01,0xcc,0xc1,0xfe,0x00,0x18
+
+# GFX12: v_pk_mul_lo_u16 v5, 0x3800, m0 op_sel:[1,1] op_sel_hi:[0,0]
+0x05,0x58,0x01,0xcc,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_pk_mul_lo_u16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1] ; encoding: [0x05,0x48,0x01,0xcc,0xfd,0xd4,0x00,0x10]
+0x05,0x48,0x01,0xcc,0xfd,0xd4,0x00,0x10
+
+# GFX12: v_pk_mul_lo_u16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] ; encoding: [0xff,0x50,0x01,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00]
+0xff,0x50,0x01,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_sub_i16 v5, v1, v2                 ; encoding: [0x05,0x40,0x03,0xcc,0x01,0x05,0x02,0x18]
+0x05,0x40,0x03,0xcc,0x01,0x05,0x02,0x18
+
+# GFX12: v_pk_sub_i16 v5, v255, v255             ; encoding: [0x05,0x40,0x03,0xcc,0xff,0xff,0x03,0x18]
+0x05,0x40,0x03,0xcc,0xff,0xff,0x03,0x18
+
+# GFX12: v_pk_sub_i16 v5, s1, s2                 ; encoding: [0x05,0x40,0x03,0xcc,0x01,0x04,0x00,0x18]
+0x05,0x40,0x03,0xcc,0x01,0x04,0x00,0x18
+
+# GFX12: v_pk_sub_i16 v5, s105, s105             ; encoding: [0x05,0x40,0x03,0xcc,0x69,0xd2,0x00,0x18]
+0x05,0x40,0x03,0xcc,0x69,0xd2,0x00,0x18
+
+# GFX12: v_pk_sub_i16 v5, vcc_lo, ttmp15         ; encoding: [0x05,0x40,0x03,0xcc,0x6a,0xf6,0x00,0x18]
+0x05,0x40,0x03,0xcc,0x6a,0xf6,0x00,0x18
+
+# GFX12: v_pk_sub_i16 v5, vcc_hi, 0xfe0b         ; encoding: [0x05,0x40,0x03,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+0x05,0x40,0x03,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_sub_i16 v5, ttmp15, src_scc        ; encoding: [0x05,0x40,0x03,0xcc,0x7b,0xfa,0x01,0x18]
+0x05,0x40,0x03,0xcc,0x7b,0xfa,0x01,0x18
+
+# GFX12: v_pk_sub_i16 v5, m0, 0x3800
+0x05,0x40,0x03,0xcc,0x7d,0xe0,0x01,0x18
+
+# GFX12: v_pk_sub_i16 v5, exec_lo, -1            ; encoding: [0x05,0x40,0x03,0xcc,0x7e,0x82,0x01,0x18]
+0x05,0x40,0x03,0xcc,0x7e,0x82,0x01,0x18
+
+# GFX12: v_pk_sub_i16 v5, exec_hi, null          ; encoding: [0x05,0x40,0x03,0xcc,0x7f,0xf8,0x00,0x18]
+0x05,0x40,0x03,0xcc,0x7f,0xf8,0x00,0x18
+
+# GFX12: v_pk_sub_i16 v5, null, exec_lo          ; encoding: [0x05,0x40,0x03,0xcc,0x7c,0xfc,0x00,0x18]
+0x05,0x40,0x03,0xcc,0x7c,0xfc,0x00,0x18
+
+# GFX12: v_pk_sub_i16 v5, -1, exec_hi            ; encoding: [0x05,0x40,0x03,0xcc,0xc1,0xfe,0x00,0x18]
+0x05,0x40,0x03,0xcc,0xc1,0xfe,0x00,0x18
+
+# GFX12: v_pk_sub_i16 v5, 0x3800, m0 op_sel:[1,1] op_sel_hi:[0,0]
+0x05,0x58,0x03,0xcc,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_pk_sub_i16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1] ; encoding: [0x05,0x48,0x03,0xcc,0xfd,0xd4,0x00,0x10]
+0x05,0x48,0x03,0xcc,0xfd,0xd4,0x00,0x10
+
+# GFX12: v_pk_sub_i16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] clamp ; encoding: [0xff,0xd0,0x03,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00]
+0xff,0xd0,0x03,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_sub_u16 v5, v1, v2                 ; encoding: [0x05,0x40,0x0b,0xcc,0x01,0x05,0x02,0x18]
+0x05,0x40,0x0b,0xcc,0x01,0x05,0x02,0x18
+
+# GFX12: v_pk_sub_u16 v5, v255, v255             ; encoding: [0x05,0x40,0x0b,0xcc,0xff,0xff,0x03,0x18]
+0x05,0x40,0x0b,0xcc,0xff,0xff,0x03,0x18
+
+# GFX12: v_pk_sub_u16 v5, s1, s2                 ; encoding: [0x05,0x40,0x0b,0xcc,0x01,0x04,0x00,0x18]
+0x05,0x40,0x0b,0xcc,0x01,0x04,0x00,0x18
+
+# GFX12: v_pk_sub_u16 v5, s105, s105             ; encoding: [0x05,0x40,0x0b,0xcc,0x69,0xd2,0x00,0x18]
+0x05,0x40,0x0b,0xcc,0x69,0xd2,0x00,0x18
+
+# GFX12: v_pk_sub_u16 v5, vcc_lo, ttmp15         ; encoding: [0x05,0x40,0x0b,0xcc,0x6a,0xf6,0x00,0x18]
+0x05,0x40,0x0b,0xcc,0x6a,0xf6,0x00,0x18
+
+# GFX12: v_pk_sub_u16 v5, vcc_hi, 0xfe0b         ; encoding: [0x05,0x40,0x0b,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00]
+0x05,0x40,0x0b,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_pk_sub_u16 v5, ttmp15, src_scc        ; encoding: [0x05,0x40,0x0b,0xcc,0x7b,0xfa,0x01,0x18]
+0x05,0x40,0x0b,0xcc,0x7b,0xfa,0x01,0x18
+
+# GFX12: v_pk_sub_u16 v5, m0, 0x3800
+0x05,0x40,0x0b,0xcc,0x7d,0xe0,0x01,0x18
+
+# GFX12: v_pk_sub_u16 v5, exec_lo, -1            ; encoding: [0x05,0x40,0x0b,0xcc,0x7e,0x82,0x01,0x18]
+0x05,0x40,0x0b,0xcc,0x7e,0x82,0x01,0x18
+
+# GFX12: v_pk_sub_u16 v5, exec_hi, null          ; encoding: [0x05,0x40,0x0b,0xcc,0x7f,0xf8,0x00,0x18]
+0x05,0x40,0x0b,0xcc,0x7f,0xf8,0x00,0x18
+
+# GFX12: v_pk_sub_u16 v5, null, exec_lo          ; encoding: [0x05,0x40,0x0b,0xcc,0x7c,0xfc,0x00,0x18]
+0x05,0x40,0x0b,0xcc,0x7c,0xfc,0x00,0x18
+
+# GFX12: v_pk_sub_u16 v5, -1, exec_hi            ; encoding: [0x05,0x40,0x0b,0xcc,0xc1,0xfe,0x00,0x18]
+0x05,0x40,0x0b,0xcc,0xc1,0xfe,0x00,0x18
+
+# GFX12: v_pk_sub_u16 v5, 0x3800, m0 op_sel:[1,1] op_sel_hi:[0,0]
+0x05,0x58,0x0b,0xcc,0xf0,0xfa,0x00,0x00
+
+# GFX12: v_pk_sub_u16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1] ; encoding: [0x05,0x48,0x0b,0xcc,0xfd,0xd4,0x00,0x10]
+0x05,0x48,0x0b,0xcc,0xfd,0xd4,0x00,0x10
+
+# GFX12: v_pk_sub_u16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] clamp ; encoding: [0xff,0xd0,0x0b,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00]
+0xff,0xd0,0x0b,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p_dpp16.txt
new file mode 100644
index 000000000000..2b902878b87f
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p_dpp16.txt
@@ -0,0 +1,14 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX12 %s
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX12 %s
+
+# GFX12: v_dot2_f32_f16_e64_dpp v0, v1, v2, v3 neg_lo:[1,1,0] neg_hi:[1,0,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xe ; encoding: [0x00,0x05,0x13,0xcc,0xfa,0x04,0x0e,0x64,0x01,0x1b,0x00,0xfe]
+0x00,0x05,0x13,0xcc,0xfa,0x04,0x0e,0x64,0x01,0x1b,0x00,0xfe
+
+# GFX12: v_dot2_f32_f16_e64_dpp v0, v1, v2, v3 quad_perm:[2,2,3,1] row_mask:0xf bank_mask:0xf bound_ctrl:1 fi:1 ; encoding: [0x00,0x00,0x13,0xcc,0xfa,0x04,0x0e,0x04,0x01,0x7a,0x0c,0xff]
+0x00,0x00,0x13,0xcc,0xfa,0x04,0x0e,0x04,0x01,0x7a,0x0c,0xff
+
+# GFX12: v_fma_mix_f32_e64_dpp v0, v1, v2, v3 row_ror:7 row_mask:0xf bank_mask:0x1 bound_ctrl:1 ; encoding: [0x00,0x00,0x20,0xcc,0xfa,0x04,0x0e,0x04,0x01,0x27,0x09,0xf1]
+0x00,0x00,0x20,0xcc,0xfa,0x04,0x0e,0x04,0x01,0x27,0x09,0xf1
+
+# GFX12: v_fma_mixhi_f16_e64_dpp v0, v1, v2, v3 op_sel_hi:[1,1,1] clamp quad_perm:[0,2,3,1] row_mask:0x0 bank_mask:0xf ; encoding: [0x00,0xc0,0x22,0xcc,0xfa,0x04,0x0e,0x1c,0x01,0x78,0x00,0x0f]
+0x00,0xc0,0x22,0xcc,0xfa,0x04,0x0e,0x1c,0x01,0x78,0x00,0x0f
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p_dpp8.txt
new file mode 100644
index 000000000000..474db1bdcc0e
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p_dpp8.txt
@@ -0,0 +1,17 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX12 %s
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX12 %s
+
+# GFX12: v_dot2_f32_f16_e64_dpp v0, v1, v2, v3 neg_lo:[0,1,1] neg_hi:[1,0,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x00,0x05,0x13,0xcc,0xe9,0x04,0x0e,0xc4,0x01,0x77,0x39,0x05]
+0x00,0x05,0x13,0xcc,0xe9,0x04,0x0e,0xc4,0x01,0x77,0x39,0x05
+
+# GFX12: v_fma_mix_f32_e64_dpp v0, v1, v2, v3 clamp dpp8:[2,2,2,2,4,4,4,4] fi:1 ; encoding: [0x00,0x80,0x20,0xcc,0xea,0x04,0x0e,0x04,0x01,0x92,0x44,0x92]
+0x00,0x80,0x20,0xcc,0xea,0x04,0x0e,0x04,0x01,0x92,0x44,0x92
+
+# GFX12: v_fma_mix_f32_e64_dpp v0, v1, v2, v3 dpp8:[2,2,2,2,4,4,4,4] ; encoding: [0x00,0x00,0x20,0xcc,0xe9,0x04,0x0e,0x04,0x01,0x92,0x44,0x92]
+0x00,0x00,0x20,0xcc,0xe9,0x04,0x0e,0x04,0x01,0x92,0x44,0x92
+
+# GFX12: v_fma_mixlo_f16_e64_dpp v0, |v1|, -v2, |v3| dpp8:[2,2,2,2,4,4,4,4] ; encoding: [0x00,0x05,0x21,0xcc,0xe9,0x04,0x0e,0x44,0x01,0x92,0x44,0x92]
+0x00,0x05,0x21,0xcc,0xe9,0x04,0x0e,0x44,0x01,0x92,0x44,0x92
+
+# GFX12: v_fma_mixlo_f16_e64_dpp v0, |v1|, -v2, |v3| op_sel:[1,0,0] op_sel_hi:[1,0,0] dpp8:[2,2,2,2,4,4,4,4] ; encoding: [0x00,0x0d,0x21,0xcc,0xe9,0x04,0x0e,0x4c,0x01,0x92,0x44,0x92]
+0x00,0x0d,0x21,0xcc,0xe9,0x04,0x0e,0x4c,0x01,0x92,0x44,0x92
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p_err.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p_err.txt
new file mode 100644
index 000000000000..36de7251f377
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p_err.txt
@@ -0,0 +1,144 @@
+# RUN: not llvm-mc -disassemble -arch=amdgcn -mcpu=gfx1200 -show-encoding %s 2>&1 | FileCheck --implicit-check-not=warning: --check-prefix=GFX12 %s
+
+# v_dot4_f32_fp8_bf8
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0xc0,0x24,0xcc,0x01,0x05,0x0e,0x1c] # clamp
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x48,0x24,0xcc,0x01,0x05,0x0e,0x1c] # op_sel:[1,0,0]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x50,0x24,0xcc,0x01,0x05,0x0e,0x1c] # op_sel:[0,1,0]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x60,0x24,0xcc,0x01,0x05,0x0e,0x1c] # op_sel:[0,0,1]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x40,0x24,0xcc,0x01,0x05,0x0e,0x14] # op_sel_hi:[0,1,1]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x40,0x24,0xcc,0x01,0x05,0x0e,0x0c] # op_sel_hi:[1,0,1]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x00,0x24,0xcc,0x01,0x05,0x0e,0x1c] # op_sel_hi:[1,1,0]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x40,0x24,0xcc,0x01,0x05,0x0e,0x3c] # neg_lo:[1,0,0]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x40,0x24,0xcc,0x01,0x05,0x0e,0x5c] # neg_lo:[0,1,0]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x41,0x24,0xcc,0x01,0x05,0x0e,0x1c] # neg_hi:[1,0,0]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x42,0x24,0xcc,0x01,0x05,0x0e,0x1c] # neg_hi:[0,1,0]
+
+
+# v_dot4_f32_bf8_fp8
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0xc0,0x25,0xcc,0x01,0x05,0x0e,0x1c] # clamp
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x48,0x25,0xcc,0x01,0x05,0x0e,0x1c] # op_sel:[1,0,0]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x50,0x25,0xcc,0x01,0x05,0x0e,0x1c] # op_sel:[0,1,0]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x60,0x25,0xcc,0x01,0x05,0x0e,0x1c] # op_sel:[0,0,1]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x40,0x25,0xcc,0x01,0x05,0x0e,0x14] # op_sel_hi:[0,1,1]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x40,0x25,0xcc,0x01,0x05,0x0e,0x0c] # op_sel_hi:[1,0,1]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x00,0x25,0xcc,0x01,0x05,0x0e,0x1c] # op_sel_hi:[1,1,0]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x40,0x25,0xcc,0x01,0x05,0x0e,0x3c] # neg_lo:[1,0,0]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x40,0x25,0xcc,0x01,0x05,0x0e,0x5c] # neg_lo:[0,1,0]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x41,0x25,0xcc,0x01,0x05,0x0e,0x1c] # neg_hi:[1,0,0]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x42,0x25,0xcc,0x01,0x05,0x0e,0x1c] # neg_hi:[0,1,0]
+
+
+# v_dot4_f32_fp8_fp8
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0xc0,0x26,0xcc,0x01,0x05,0x0e,0x1c] # clamp
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x48,0x26,0xcc,0x01,0x05,0x0e,0x1c] # op_sel:[1,0,0]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x50,0x26,0xcc,0x01,0x05,0x0e,0x1c] # op_sel:[0,1,0]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x60,0x26,0xcc,0x01,0x05,0x0e,0x1c] # op_sel:[0,0,1]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x40,0x26,0xcc,0x01,0x05,0x0e,0x14] # op_sel_hi:[0,1,1]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x40,0x26,0xcc,0x01,0x05,0x0e,0x0c] # op_sel_hi:[1,0,1]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x00,0x26,0xcc,0x01,0x05,0x0e,0x1c] # op_sel_hi:[1,1,0]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x40,0x26,0xcc,0x01,0x05,0x0e,0x3c] # neg_lo:[1,0,0]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x40,0x26,0xcc,0x01,0x05,0x0e,0x5c] # neg_lo:[0,1,0]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x41,0x26,0xcc,0x01,0x05,0x0e,0x1c] # neg_hi:[1,0,0]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x42,0x26,0xcc,0x01,0x05,0x0e,0x1c] # neg_hi:[0,1,0]
+
+
+# v_dot4_f32_bf8_bf8
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0xc0,0x27,0xcc,0x01,0x05,0x0e,0x1c] # clamp
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x48,0x27,0xcc,0x01,0x05,0x0e,0x1c] # op_sel:[1,0,0]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x50,0x27,0xcc,0x01,0x05,0x0e,0x1c] # op_sel:[0,1,0]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x60,0x27,0xcc,0x01,0x05,0x0e,0x1c] # op_sel:[0,0,1]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x40,0x27,0xcc,0x01,0x05,0x0e,0x14] # op_sel_hi:[0,1,1]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x40,0x27,0xcc,0x01,0x05,0x0e,0x0c] # op_sel_hi:[1,0,1]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x00,0x27,0xcc,0x01,0x05,0x0e,0x1c] # op_sel_hi:[1,1,0]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x40,0x27,0xcc,0x01,0x05,0x0e,0x3c] # neg_lo:[1,0,0]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x40,0x27,0xcc,0x01,0x05,0x0e,0x5c] # neg_lo:[0,1,0]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x41,0x27,0xcc,0x01,0x05,0x0e,0x1c] # neg_hi:[1,0,0]
+
+# GFX12: warning: invalid instruction encoding
+[0x00,0x42,0x27,0xcc,0x01,0x05,0x0e,0x1c] # neg_hi:[0,1,0]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
new file mode 100644
index 000000000000..902a378a9392
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
@@ -0,0 +1,4538 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W32
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W64
+
+# W32: v_cmp_class_f16_e32 vcc_lo, v1, v2        ; encoding: [0x01,0x05,0xfa,0x7c]
+# W64: v_cmp_class_f16_e32 vcc, v1, v2           ; encoding: [0x01,0x05,0xfa,0x7c]
+0x01,0x05,0xfa,0x7c
+
+# W32: v_cmp_class_f16_e32 vcc_lo, v127, v2      ; encoding: [0x7f,0x05,0xfa,0x7c]
+# W64: v_cmp_class_f16_e32 vcc, v127, v2         ; encoding: [0x7f,0x05,0xfa,0x7c]
+0x7f,0x05,0xfa,0x7c
+
+# W32: v_cmp_class_f16_e32 vcc_lo, s1, v2        ; encoding: [0x01,0x04,0xfa,0x7c]
+# W64: v_cmp_class_f16_e32 vcc, s1, v2           ; encoding: [0x01,0x04,0xfa,0x7c]
+0x01,0x04,0xfa,0x7c
+
+# W32: v_cmp_class_f16_e32 vcc_lo, s105, v2      ; encoding: [0x69,0x04,0xfa,0x7c]
+# W64: v_cmp_class_f16_e32 vcc, s105, v2         ; encoding: [0x69,0x04,0xfa,0x7c]
+0x69,0x04,0xfa,0x7c
+
+# W32: v_cmp_class_f16_e32 vcc_lo, vcc_lo, v2    ; encoding: [0x6a,0x04,0xfa,0x7c]
+# W64: v_cmp_class_f16_e32 vcc, vcc_lo, v2       ; encoding: [0x6a,0x04,0xfa,0x7c]
+0x6a,0x04,0xfa,0x7c
+
+# W32: v_cmp_class_f16_e32 vcc_lo, vcc_hi, v2    ; encoding: [0x6b,0x04,0xfa,0x7c]
+# W64: v_cmp_class_f16_e32 vcc, vcc_hi, v2       ; encoding: [0x6b,0x04,0xfa,0x7c]
+0x6b,0x04,0xfa,0x7c
+
+# W32: v_cmp_class_f16_e32 vcc_lo, ttmp15, v2    ; encoding: [0x7b,0x04,0xfa,0x7c]
+# W64: v_cmp_class_f16_e32 vcc, ttmp15, v2       ; encoding: [0x7b,0x04,0xfa,0x7c]
+0x7b,0x04,0xfa,0x7c
+
+# W32: v_cmp_class_f16_e32 vcc_lo, m0, v2        ; encoding: [0x7d,0x04,0xfa,0x7c]
+# W64: v_cmp_class_f16_e32 vcc, m0, v2           ; encoding: [0x7d,0x04,0xfa,0x7c]
+0x7d,0x04,0xfa,0x7c
+
+# W32: v_cmp_class_f16_e32 vcc_lo, exec_lo, v2   ; encoding: [0x7e,0x04,0xfa,0x7c]
+# W64: v_cmp_class_f16_e32 vcc, exec_lo, v2      ; encoding: [0x7e,0x04,0xfa,0x7c]
+0x7e,0x04,0xfa,0x7c
+
+# W32: v_cmp_class_f16_e32 vcc_lo, exec_hi, v2   ; encoding: [0x7f,0x04,0xfa,0x7c]
+# W64: v_cmp_class_f16_e32 vcc, exec_hi, v2      ; encoding: [0x7f,0x04,0xfa,0x7c]
+0x7f,0x04,0xfa,0x7c
+
+# W32: v_cmp_class_f16_e32 vcc_lo, null, v2      ; encoding: [0x7c,0x04,0xfa,0x7c]
+# W64: v_cmp_class_f16_e32 vcc, null, v2         ; encoding: [0x7c,0x04,0xfa,0x7c]
+0x7c,0x04,0xfa,0x7c
+
+# W32: v_cmp_class_f16_e32 vcc_lo, -1, v2        ; encoding: [0xc1,0x04,0xfa,0x7c]
+# W64: v_cmp_class_f16_e32 vcc, -1, v2           ; encoding: [0xc1,0x04,0xfa,0x7c]
+0xc1,0x04,0xfa,0x7c
+
+# W32: v_cmp_class_f16_e32 vcc_lo, 0.5, v2       ; encoding: [0xf0,0x04,0xfa,0x7c]
+# W64: v_cmp_class_f16_e32 vcc, 0.5, v2          ; encoding: [0xf0,0x04,0xfa,0x7c]
+0xf0,0x04,0xfa,0x7c
+
+# W32: v_cmp_class_f16_e32 vcc_lo, src_scc, v2   ; encoding: [0xfd,0x04,0xfa,0x7c]
+# W64: v_cmp_class_f16_e32 vcc, src_scc, v2      ; encoding: [0xfd,0x04,0xfa,0x7c]
+0xfd,0x04,0xfa,0x7c
+
+# W32: v_cmp_class_f16_e32 vcc_lo, 0xfe0b, v127  ; encoding: [0xff,0xfe,0xfa,0x7c,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_class_f16_e32 vcc, 0xfe0b, v127     ; encoding: [0xff,0xfe,0xfa,0x7c,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0xfa,0x7c,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_class_f32_e32 vcc_lo, v1, v2        ; encoding: [0x01,0x05,0xfc,0x7c]
+# W64: v_cmp_class_f32_e32 vcc, v1, v2           ; encoding: [0x01,0x05,0xfc,0x7c]
+0x01,0x05,0xfc,0x7c
+
+# W32: v_cmp_class_f32_e32 vcc_lo, v255, v2      ; encoding: [0xff,0x05,0xfc,0x7c]
+# W64: v_cmp_class_f32_e32 vcc, v255, v2         ; encoding: [0xff,0x05,0xfc,0x7c]
+0xff,0x05,0xfc,0x7c
+
+# W32: v_cmp_class_f32_e32 vcc_lo, s1, v2        ; encoding: [0x01,0x04,0xfc,0x7c]
+# W64: v_cmp_class_f32_e32 vcc, s1, v2           ; encoding: [0x01,0x04,0xfc,0x7c]
+0x01,0x04,0xfc,0x7c
+
+# W32: v_cmp_class_f32_e32 vcc_lo, s105, v2      ; encoding: [0x69,0x04,0xfc,0x7c]
+# W64: v_cmp_class_f32_e32 vcc, s105, v2         ; encoding: [0x69,0x04,0xfc,0x7c]
+0x69,0x04,0xfc,0x7c
+
+# W32: v_cmp_class_f32_e32 vcc_lo, vcc_lo, v2    ; encoding: [0x6a,0x04,0xfc,0x7c]
+# W64: v_cmp_class_f32_e32 vcc, vcc_lo, v2       ; encoding: [0x6a,0x04,0xfc,0x7c]
+0x6a,0x04,0xfc,0x7c
+
+# W32: v_cmp_class_f32_e32 vcc_lo, vcc_hi, v2    ; encoding: [0x6b,0x04,0xfc,0x7c]
+# W64: v_cmp_class_f32_e32 vcc, vcc_hi, v2       ; encoding: [0x6b,0x04,0xfc,0x7c]
+0x6b,0x04,0xfc,0x7c
+
+# W32: v_cmp_class_f32_e32 vcc_lo, ttmp15, v2    ; encoding: [0x7b,0x04,0xfc,0x7c]
+# W64: v_cmp_class_f32_e32 vcc, ttmp15, v2       ; encoding: [0x7b,0x04,0xfc,0x7c]
+0x7b,0x04,0xfc,0x7c
+
+# W32: v_cmp_class_f32_e32 vcc_lo, m0, v2        ; encoding: [0x7d,0x04,0xfc,0x7c]
+# W64: v_cmp_class_f32_e32 vcc, m0, v2           ; encoding: [0x7d,0x04,0xfc,0x7c]
+0x7d,0x04,0xfc,0x7c
+
+# W32: v_cmp_class_f32_e32 vcc_lo, exec_lo, v2   ; encoding: [0x7e,0x04,0xfc,0x7c]
+# W64: v_cmp_class_f32_e32 vcc, exec_lo, v2      ; encoding: [0x7e,0x04,0xfc,0x7c]
+0x7e,0x04,0xfc,0x7c
+
+# W32: v_cmp_class_f32_e32 vcc_lo, exec_hi, v2   ; encoding: [0x7f,0x04,0xfc,0x7c]
+# W64: v_cmp_class_f32_e32 vcc, exec_hi, v2      ; encoding: [0x7f,0x04,0xfc,0x7c]
+0x7f,0x04,0xfc,0x7c
+
+# W32: v_cmp_class_f32_e32 vcc_lo, null, v2      ; encoding: [0x7c,0x04,0xfc,0x7c]
+# W64: v_cmp_class_f32_e32 vcc, null, v2         ; encoding: [0x7c,0x04,0xfc,0x7c]
+0x7c,0x04,0xfc,0x7c
+
+# W32: v_cmp_class_f32_e32 vcc_lo, -1, v2        ; encoding: [0xc1,0x04,0xfc,0x7c]
+# W64: v_cmp_class_f32_e32 vcc, -1, v2           ; encoding: [0xc1,0x04,0xfc,0x7c]
+0xc1,0x04,0xfc,0x7c
+
+# W32: v_cmp_class_f32_e32 vcc_lo, 0.5, v2       ; encoding: [0xf0,0x04,0xfc,0x7c]
+# W64: v_cmp_class_f32_e32 vcc, 0.5, v2          ; encoding: [0xf0,0x04,0xfc,0x7c]
+0xf0,0x04,0xfc,0x7c
+
+# W32: v_cmp_class_f32_e32 vcc_lo, src_scc, v2   ; encoding: [0xfd,0x04,0xfc,0x7c]
+# W64: v_cmp_class_f32_e32 vcc, src_scc, v2      ; encoding: [0xfd,0x04,0xfc,0x7c]
+0xfd,0x04,0xfc,0x7c
+
+# W32: v_cmp_class_f32_e32 vcc_lo, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xfd,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_class_f32_e32 vcc, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xfd,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xfd,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_class_f64_e32 vcc_lo, v[1:2], v2    ; encoding: [0x01,0x05,0xfe,0x7c]
+# W64: v_cmp_class_f64_e32 vcc, v[1:2], v2       ; encoding: [0x01,0x05,0xfe,0x7c]
+0x01,0x05,0xfe,0x7c
+
+# W32: v_cmp_class_f64_e32 vcc_lo, v[254:255], v2 ; encoding: [0xfe,0x05,0xfe,0x7c]
+# W64: v_cmp_class_f64_e32 vcc, v[254:255], v2   ; encoding: [0xfe,0x05,0xfe,0x7c]
+0xfe,0x05,0xfe,0x7c
+
+# W32: v_cmp_class_f64_e32 vcc_lo, s[2:3], v2    ; encoding: [0x02,0x04,0xfe,0x7c]
+# W64: v_cmp_class_f64_e32 vcc, s[2:3], v2       ; encoding: [0x02,0x04,0xfe,0x7c]
+0x02,0x04,0xfe,0x7c
+
+# W32: v_cmp_class_f64_e32 vcc_lo, s[104:105], v2 ; encoding: [0x68,0x04,0xfe,0x7c]
+# W64: v_cmp_class_f64_e32 vcc, s[104:105], v2   ; encoding: [0x68,0x04,0xfe,0x7c]
+0x68,0x04,0xfe,0x7c
+
+# W32: v_cmp_class_f64_e32 vcc_lo, vcc, v2       ; encoding: [0x6a,0x04,0xfe,0x7c]
+# W64: v_cmp_class_f64_e32 vcc, vcc, v2          ; encoding: [0x6a,0x04,0xfe,0x7c]
+0x6a,0x04,0xfe,0x7c
+
+# W32: v_cmp_class_f64_e32 vcc_lo, ttmp[14:15], v2 ; encoding: [0x7a,0x04,0xfe,0x7c]
+# W64: v_cmp_class_f64_e32 vcc, ttmp[14:15], v2  ; encoding: [0x7a,0x04,0xfe,0x7c]
+0x7a,0x04,0xfe,0x7c
+
+# W32: v_cmp_class_f64_e32 vcc_lo, exec, v2      ; encoding: [0x7e,0x04,0xfe,0x7c]
+# W64: v_cmp_class_f64_e32 vcc, exec, v2         ; encoding: [0x7e,0x04,0xfe,0x7c]
+0x7e,0x04,0xfe,0x7c
+
+# W32: v_cmp_class_f64_e32 vcc_lo, null, v2      ; encoding: [0x7c,0x04,0xfe,0x7c]
+# W64: v_cmp_class_f64_e32 vcc, null, v2         ; encoding: [0x7c,0x04,0xfe,0x7c]
+0x7c,0x04,0xfe,0x7c
+
+# W32: v_cmp_class_f64_e32 vcc_lo, -1, v2        ; encoding: [0xc1,0x04,0xfe,0x7c]
+# W64: v_cmp_class_f64_e32 vcc, -1, v2           ; encoding: [0xc1,0x04,0xfe,0x7c]
+0xc1,0x04,0xfe,0x7c
+
+# W32: v_cmp_class_f64_e32 vcc_lo, 0.5, v2       ; encoding: [0xf0,0x04,0xfe,0x7c]
+# W64: v_cmp_class_f64_e32 vcc, 0.5, v2          ; encoding: [0xf0,0x04,0xfe,0x7c]
+0xf0,0x04,0xfe,0x7c
+
+# W32: v_cmp_class_f64_e32 vcc_lo, src_scc, v2   ; encoding: [0xfd,0x04,0xfe,0x7c]
+# W64: v_cmp_class_f64_e32 vcc, src_scc, v2      ; encoding: [0xfd,0x04,0xfe,0x7c]
+0xfd,0x04,0xfe,0x7c
+
+# W32: v_cmp_class_f64_e32 vcc_lo, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_class_f64_e32 vcc, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_eq_f16_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x04,0x7c]
+# W64: v_cmp_eq_f16_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x04,0x7c]
+0x01,0x05,0x04,0x7c
+
+# W32: v_cmp_eq_f16_e32 vcc_lo, v127, v2         ; encoding: [0x7f,0x05,0x04,0x7c]
+# W64: v_cmp_eq_f16_e32 vcc, v127, v2            ; encoding: [0x7f,0x05,0x04,0x7c]
+0x7f,0x05,0x04,0x7c
+
+# W32: v_cmp_eq_f16_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x04,0x7c]
+# W64: v_cmp_eq_f16_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x04,0x7c]
+0x01,0x04,0x04,0x7c
+
+# W32: v_cmp_eq_f16_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x04,0x7c]
+# W64: v_cmp_eq_f16_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x04,0x7c]
+0x69,0x04,0x04,0x7c
+
+# W32: v_cmp_eq_f16_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x04,0x7c]
+# W64: v_cmp_eq_f16_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x04,0x7c]
+0x6a,0x04,0x04,0x7c
+
+# W32: v_cmp_eq_f16_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x04,0x7c]
+# W64: v_cmp_eq_f16_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x04,0x7c]
+0x6b,0x04,0x04,0x7c
+
+# W32: v_cmp_eq_f16_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x04,0x7c]
+# W64: v_cmp_eq_f16_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x04,0x7c]
+0x7b,0x04,0x04,0x7c
+
+# W32: v_cmp_eq_f16_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x04,0x7c]
+# W64: v_cmp_eq_f16_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x04,0x7c]
+0x7d,0x04,0x04,0x7c
+
+# W32: v_cmp_eq_f16_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x04,0x7c]
+# W64: v_cmp_eq_f16_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x04,0x7c]
+0x7e,0x04,0x04,0x7c
+
+# W32: v_cmp_eq_f16_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x04,0x7c]
+# W64: v_cmp_eq_f16_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x04,0x7c]
+0x7f,0x04,0x04,0x7c
+
+# W32: v_cmp_eq_f16_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x04,0x7c]
+# W64: v_cmp_eq_f16_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x04,0x7c]
+0x7c,0x04,0x04,0x7c
+
+# W32: v_cmp_eq_f16_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x04,0x7c]
+# W64: v_cmp_eq_f16_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x04,0x7c]
+0xc1,0x04,0x04,0x7c
+
+# W32: v_cmp_eq_f16_e32 vcc_lo, 0.5, v2          ; encoding: [0xf0,0x04,0x04,0x7c]
+# W64: v_cmp_eq_f16_e32 vcc, 0.5, v2             ; encoding: [0xf0,0x04,0x04,0x7c]
+0xf0,0x04,0x04,0x7c
+
+# W32: v_cmp_eq_f16_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x04,0x7c]
+# W64: v_cmp_eq_f16_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x04,0x7c]
+0xfd,0x04,0x04,0x7c
+
+# W32: v_cmp_eq_f16_e32 vcc_lo, 0xfe0b, v127     ; encoding: [0xff,0xfe,0x04,0x7c,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_eq_f16_e32 vcc, 0xfe0b, v127        ; encoding: [0xff,0xfe,0x04,0x7c,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x04,0x7c,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_eq_f32_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x24,0x7c]
+# W64: v_cmp_eq_f32_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x24,0x7c]
+0x01,0x05,0x24,0x7c
+
+# W32: v_cmp_eq_f32_e32 vcc_lo, v255, v2         ; encoding: [0xff,0x05,0x24,0x7c]
+# W64: v_cmp_eq_f32_e32 vcc, v255, v2            ; encoding: [0xff,0x05,0x24,0x7c]
+0xff,0x05,0x24,0x7c
+
+# W32: v_cmp_eq_f32_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x24,0x7c]
+# W64: v_cmp_eq_f32_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x24,0x7c]
+0x01,0x04,0x24,0x7c
+
+# W32: v_cmp_eq_f32_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x24,0x7c]
+# W64: v_cmp_eq_f32_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x24,0x7c]
+0x69,0x04,0x24,0x7c
+
+# W32: v_cmp_eq_f32_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x24,0x7c]
+# W64: v_cmp_eq_f32_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x24,0x7c]
+0x6a,0x04,0x24,0x7c
+
+# W32: v_cmp_eq_f32_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x24,0x7c]
+# W64: v_cmp_eq_f32_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x24,0x7c]
+0x6b,0x04,0x24,0x7c
+
+# W32: v_cmp_eq_f32_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x24,0x7c]
+# W64: v_cmp_eq_f32_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x24,0x7c]
+0x7b,0x04,0x24,0x7c
+
+# W32: v_cmp_eq_f32_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x24,0x7c]
+# W64: v_cmp_eq_f32_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x24,0x7c]
+0x7d,0x04,0x24,0x7c
+
+# W32: v_cmp_eq_f32_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x24,0x7c]
+# W64: v_cmp_eq_f32_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x24,0x7c]
+0x7e,0x04,0x24,0x7c
+
+# W32: v_cmp_eq_f32_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x24,0x7c]
+# W64: v_cmp_eq_f32_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x24,0x7c]
+0x7f,0x04,0x24,0x7c
+
+# W32: v_cmp_eq_f32_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x24,0x7c]
+# W64: v_cmp_eq_f32_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x24,0x7c]
+0x7c,0x04,0x24,0x7c
+
+# W32: v_cmp_eq_f32_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x24,0x7c]
+# W64: v_cmp_eq_f32_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x24,0x7c]
+0xc1,0x04,0x24,0x7c
+
+# W32: v_cmp_eq_f32_e32 vcc_lo, 0.5, v2          ; encoding: [0xf0,0x04,0x24,0x7c]
+# W64: v_cmp_eq_f32_e32 vcc, 0.5, v2             ; encoding: [0xf0,0x04,0x24,0x7c]
+0xf0,0x04,0x24,0x7c
+
+# W32: v_cmp_eq_f32_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x24,0x7c]
+# W64: v_cmp_eq_f32_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x24,0x7c]
+0xfd,0x04,0x24,0x7c
+
+# W32: v_cmp_eq_f32_e32 vcc_lo, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x25,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_eq_f32_e32 vcc, 0xaf123456, v255    ; encoding: [0xff,0xfe,0x25,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x25,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_eq_f64_e32 vcc_lo, v[1:2], v[2:3]   ; encoding: [0x01,0x05,0x44,0x7c]
+# W64: v_cmp_eq_f64_e32 vcc, v[1:2], v[2:3]      ; encoding: [0x01,0x05,0x44,0x7c]
+0x01,0x05,0x44,0x7c
+
+# W32: v_cmp_eq_f64_e32 vcc_lo, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x44,0x7c]
+# W64: v_cmp_eq_f64_e32 vcc, v[254:255], v[2:3]  ; encoding: [0xfe,0x05,0x44,0x7c]
+0xfe,0x05,0x44,0x7c
+
+# W32: v_cmp_eq_f64_e32 vcc_lo, s[2:3], v[2:3]   ; encoding: [0x02,0x04,0x44,0x7c]
+# W64: v_cmp_eq_f64_e32 vcc, s[2:3], v[2:3]      ; encoding: [0x02,0x04,0x44,0x7c]
+0x02,0x04,0x44,0x7c
+
+# W32: v_cmp_eq_f64_e32 vcc_lo, s[104:105], v[2:3] ; encoding: [0x68,0x04,0x44,0x7c]
+# W64: v_cmp_eq_f64_e32 vcc, s[104:105], v[2:3]  ; encoding: [0x68,0x04,0x44,0x7c]
+0x68,0x04,0x44,0x7c
+
+# W32: v_cmp_eq_f64_e32 vcc_lo, vcc, v[2:3]      ; encoding: [0x6a,0x04,0x44,0x7c]
+# W64: v_cmp_eq_f64_e32 vcc, vcc, v[2:3]         ; encoding: [0x6a,0x04,0x44,0x7c]
+0x6a,0x04,0x44,0x7c
+
+# W32: v_cmp_eq_f64_e32 vcc_lo, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x44,0x7c]
+# W64: v_cmp_eq_f64_e32 vcc, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x44,0x7c]
+0x7a,0x04,0x44,0x7c
+
+# W32: v_cmp_eq_f64_e32 vcc_lo, exec, v[2:3]     ; encoding: [0x7e,0x04,0x44,0x7c]
+# W64: v_cmp_eq_f64_e32 vcc, exec, v[2:3]        ; encoding: [0x7e,0x04,0x44,0x7c]
+0x7e,0x04,0x44,0x7c
+
+# W32: v_cmp_eq_f64_e32 vcc_lo, null, v[2:3]     ; encoding: [0x7c,0x04,0x44,0x7c]
+# W64: v_cmp_eq_f64_e32 vcc, null, v[2:3]        ; encoding: [0x7c,0x04,0x44,0x7c]
+0x7c,0x04,0x44,0x7c
+
+# W32: v_cmp_eq_f64_e32 vcc_lo, -1, v[2:3]       ; encoding: [0xc1,0x04,0x44,0x7c]
+# W64: v_cmp_eq_f64_e32 vcc, -1, v[2:3]          ; encoding: [0xc1,0x04,0x44,0x7c]
+0xc1,0x04,0x44,0x7c
+
+# W32: v_cmp_eq_f64_e32 vcc_lo, 0.5, v[2:3]      ; encoding: [0xf0,0x04,0x44,0x7c]
+# W64: v_cmp_eq_f64_e32 vcc, 0.5, v[2:3]         ; encoding: [0xf0,0x04,0x44,0x7c]
+0xf0,0x04,0x44,0x7c
+
+# W32: v_cmp_eq_f64_e32 vcc_lo, src_scc, v[2:3]  ; encoding: [0xfd,0x04,0x44,0x7c]
+# W64: v_cmp_eq_f64_e32 vcc, src_scc, v[2:3]     ; encoding: [0xfd,0x04,0x44,0x7c]
+0xfd,0x04,0x44,0x7c
+
+# W32: v_cmp_eq_f64_e32 vcc_lo, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x45,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_eq_f64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x45,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x45,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_eq_i16_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x64,0x7c]
+# W64: v_cmp_eq_i16_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x64,0x7c]
+0x01,0x05,0x64,0x7c
+
+# W32: v_cmp_eq_i16_e32 vcc_lo, v127, v2         ; encoding: [0x7f,0x05,0x64,0x7c]
+# W64: v_cmp_eq_i16_e32 vcc, v127, v2            ; encoding: [0x7f,0x05,0x64,0x7c]
+0x7f,0x05,0x64,0x7c
+
+# W32: v_cmp_eq_i16_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x64,0x7c]
+# W64: v_cmp_eq_i16_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x64,0x7c]
+0x01,0x04,0x64,0x7c
+
+# W32: v_cmp_eq_i16_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x64,0x7c]
+# W64: v_cmp_eq_i16_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x64,0x7c]
+0x69,0x04,0x64,0x7c
+
+# W32: v_cmp_eq_i16_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x64,0x7c]
+# W64: v_cmp_eq_i16_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x64,0x7c]
+0x6a,0x04,0x64,0x7c
+
+# W32: v_cmp_eq_i16_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x64,0x7c]
+# W64: v_cmp_eq_i16_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x64,0x7c]
+0x6b,0x04,0x64,0x7c
+
+# W32: v_cmp_eq_i16_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x64,0x7c]
+# W64: v_cmp_eq_i16_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x64,0x7c]
+0x7b,0x04,0x64,0x7c
+
+# W32: v_cmp_eq_i16_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x64,0x7c]
+# W64: v_cmp_eq_i16_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x64,0x7c]
+0x7d,0x04,0x64,0x7c
+
+# W32: v_cmp_eq_i16_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x64,0x7c]
+# W64: v_cmp_eq_i16_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x64,0x7c]
+0x7e,0x04,0x64,0x7c
+
+# W32: v_cmp_eq_i16_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x64,0x7c]
+# W64: v_cmp_eq_i16_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x64,0x7c]
+0x7f,0x04,0x64,0x7c
+
+# W32: v_cmp_eq_i16_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x64,0x7c]
+# W64: v_cmp_eq_i16_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x64,0x7c]
+0x7c,0x04,0x64,0x7c
+
+# W32: v_cmp_eq_i16_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x64,0x7c]
+# W64: v_cmp_eq_i16_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x64,0x7c]
+0xc1,0x04,0x64,0x7c
+
+# W32: v_cmp_eq_i16_e32 vcc_lo, 0x3800, v2
+# W64: v_cmp_eq_i16_e32 vcc, 0x3800, v2          ; encoding: [0xff,0x04,0x64,0x7c,0x00,0x38,0x00,0x00]
+0xf0,0x04,0x64,0x7c
+
+# W32: v_cmp_eq_i16_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x64,0x7c]
+# W64: v_cmp_eq_i16_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x64,0x7c]
+0xfd,0x04,0x64,0x7c
+
+# W32: v_cmp_eq_i16_e32 vcc_lo, 0xfe0b, v127     ; encoding: [0xff,0xfe,0x64,0x7c,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_eq_i16_e32 vcc, 0xfe0b, v127        ; encoding: [0xff,0xfe,0x64,0x7c,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x64,0x7c,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_eq_i32_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x84,0x7c]
+# W64: v_cmp_eq_i32_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x84,0x7c]
+0x01,0x05,0x84,0x7c
+
+# W32: v_cmp_eq_i32_e32 vcc_lo, v255, v2         ; encoding: [0xff,0x05,0x84,0x7c]
+# W64: v_cmp_eq_i32_e32 vcc, v255, v2            ; encoding: [0xff,0x05,0x84,0x7c]
+0xff,0x05,0x84,0x7c
+
+# W32: v_cmp_eq_i32_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x84,0x7c]
+# W64: v_cmp_eq_i32_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x84,0x7c]
+0x01,0x04,0x84,0x7c
+
+# W32: v_cmp_eq_i32_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x84,0x7c]
+# W64: v_cmp_eq_i32_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x84,0x7c]
+0x69,0x04,0x84,0x7c
+
+# W32: v_cmp_eq_i32_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x84,0x7c]
+# W64: v_cmp_eq_i32_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x84,0x7c]
+0x6a,0x04,0x84,0x7c
+
+# W32: v_cmp_eq_i32_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x84,0x7c]
+# W64: v_cmp_eq_i32_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x84,0x7c]
+0x6b,0x04,0x84,0x7c
+
+# W32: v_cmp_eq_i32_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x84,0x7c]
+# W64: v_cmp_eq_i32_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x84,0x7c]
+0x7b,0x04,0x84,0x7c
+
+# W32: v_cmp_eq_i32_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x84,0x7c]
+# W64: v_cmp_eq_i32_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x84,0x7c]
+0x7d,0x04,0x84,0x7c
+
+# W32: v_cmp_eq_i32_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x84,0x7c]
+# W64: v_cmp_eq_i32_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x84,0x7c]
+0x7e,0x04,0x84,0x7c
+
+# W32: v_cmp_eq_i32_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x84,0x7c]
+# W64: v_cmp_eq_i32_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x84,0x7c]
+0x7f,0x04,0x84,0x7c
+
+# W32: v_cmp_eq_i32_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x84,0x7c]
+# W64: v_cmp_eq_i32_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x84,0x7c]
+0x7c,0x04,0x84,0x7c
+
+# W32: v_cmp_eq_i32_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x84,0x7c]
+# W64: v_cmp_eq_i32_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x84,0x7c]
+0xc1,0x04,0x84,0x7c
+
+# W32: v_cmp_eq_i32_e32 vcc_lo, 0.5, v2          ; encoding: [0xf0,0x04,0x84,0x7c]
+# W64: v_cmp_eq_i32_e32 vcc, 0.5, v2             ; encoding: [0xf0,0x04,0x84,0x7c]
+0xf0,0x04,0x84,0x7c
+
+# W32: v_cmp_eq_i32_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x84,0x7c]
+# W64: v_cmp_eq_i32_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x84,0x7c]
+0xfd,0x04,0x84,0x7c
+
+# W32: v_cmp_eq_i32_e32 vcc_lo, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x85,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_eq_i32_e32 vcc, 0xaf123456, v255    ; encoding: [0xff,0xfe,0x85,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x85,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_eq_i64_e32 vcc_lo, v[1:2], v[2:3]   ; encoding: [0x01,0x05,0xa4,0x7c]
+# W64: v_cmp_eq_i64_e32 vcc, v[1:2], v[2:3]      ; encoding: [0x01,0x05,0xa4,0x7c]
+0x01,0x05,0xa4,0x7c
+
+# W32: v_cmp_eq_i64_e32 vcc_lo, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0xa4,0x7c]
+# W64: v_cmp_eq_i64_e32 vcc, v[254:255], v[2:3]  ; encoding: [0xfe,0x05,0xa4,0x7c]
+0xfe,0x05,0xa4,0x7c
+
+# W32: v_cmp_eq_i64_e32 vcc_lo, s[2:3], v[2:3]   ; encoding: [0x02,0x04,0xa4,0x7c]
+# W64: v_cmp_eq_i64_e32 vcc, s[2:3], v[2:3]      ; encoding: [0x02,0x04,0xa4,0x7c]
+0x02,0x04,0xa4,0x7c
+
+# W32: v_cmp_eq_i64_e32 vcc_lo, s[104:105], v[2:3] ; encoding: [0x68,0x04,0xa4,0x7c]
+# W64: v_cmp_eq_i64_e32 vcc, s[104:105], v[2:3]  ; encoding: [0x68,0x04,0xa4,0x7c]
+0x68,0x04,0xa4,0x7c
+
+# W32: v_cmp_eq_i64_e32 vcc_lo, vcc, v[2:3]      ; encoding: [0x6a,0x04,0xa4,0x7c]
+# W64: v_cmp_eq_i64_e32 vcc, vcc, v[2:3]         ; encoding: [0x6a,0x04,0xa4,0x7c]
+0x6a,0x04,0xa4,0x7c
+
+# W32: v_cmp_eq_i64_e32 vcc_lo, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0xa4,0x7c]
+# W64: v_cmp_eq_i64_e32 vcc, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0xa4,0x7c]
+0x7a,0x04,0xa4,0x7c
+
+# W32: v_cmp_eq_i64_e32 vcc_lo, exec, v[2:3]     ; encoding: [0x7e,0x04,0xa4,0x7c]
+# W64: v_cmp_eq_i64_e32 vcc, exec, v[2:3]        ; encoding: [0x7e,0x04,0xa4,0x7c]
+0x7e,0x04,0xa4,0x7c
+
+# W32: v_cmp_eq_i64_e32 vcc_lo, null, v[2:3]     ; encoding: [0x7c,0x04,0xa4,0x7c]
+# W64: v_cmp_eq_i64_e32 vcc, null, v[2:3]        ; encoding: [0x7c,0x04,0xa4,0x7c]
+0x7c,0x04,0xa4,0x7c
+
+# W32: v_cmp_eq_i64_e32 vcc_lo, -1, v[2:3]       ; encoding: [0xc1,0x04,0xa4,0x7c]
+# W64: v_cmp_eq_i64_e32 vcc, -1, v[2:3]          ; encoding: [0xc1,0x04,0xa4,0x7c]
+0xc1,0x04,0xa4,0x7c
+
+# W32: v_cmp_eq_i64_e32 vcc_lo, 0.5, v[2:3]      ; encoding: [0xf0,0x04,0xa4,0x7c]
+# W64: v_cmp_eq_i64_e32 vcc, 0.5, v[2:3]         ; encoding: [0xf0,0x04,0xa4,0x7c]
+0xf0,0x04,0xa4,0x7c
+
+# W32: v_cmp_eq_i64_e32 vcc_lo, src_scc, v[2:3]  ; encoding: [0xfd,0x04,0xa4,0x7c]
+# W64: v_cmp_eq_i64_e32 vcc, src_scc, v[2:3]     ; encoding: [0xfd,0x04,0xa4,0x7c]
+0xfd,0x04,0xa4,0x7c
+
+# W32: v_cmp_eq_i64_e32 vcc_lo, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xa5,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_eq_i64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xa5,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xa5,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_eq_u16_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x74,0x7c]
+# W64: v_cmp_eq_u16_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x74,0x7c]
+0x01,0x05,0x74,0x7c
+
+# W32: v_cmp_eq_u16_e32 vcc_lo, v127, v2         ; encoding: [0x7f,0x05,0x74,0x7c]
+# W64: v_cmp_eq_u16_e32 vcc, v127, v2            ; encoding: [0x7f,0x05,0x74,0x7c]
+0x7f,0x05,0x74,0x7c
+
+# W32: v_cmp_eq_u16_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x74,0x7c]
+# W64: v_cmp_eq_u16_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x74,0x7c]
+0x01,0x04,0x74,0x7c
+
+# W32: v_cmp_eq_u16_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x74,0x7c]
+# W64: v_cmp_eq_u16_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x74,0x7c]
+0x69,0x04,0x74,0x7c
+
+# W32: v_cmp_eq_u16_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x74,0x7c]
+# W64: v_cmp_eq_u16_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x74,0x7c]
+0x6a,0x04,0x74,0x7c
+
+# W32: v_cmp_eq_u16_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x74,0x7c]
+# W64: v_cmp_eq_u16_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x74,0x7c]
+0x6b,0x04,0x74,0x7c
+
+# W32: v_cmp_eq_u16_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x74,0x7c]
+# W64: v_cmp_eq_u16_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x74,0x7c]
+0x7b,0x04,0x74,0x7c
+
+# W32: v_cmp_eq_u16_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x74,0x7c]
+# W64: v_cmp_eq_u16_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x74,0x7c]
+0x7d,0x04,0x74,0x7c
+
+# W32: v_cmp_eq_u16_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x74,0x7c]
+# W64: v_cmp_eq_u16_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x74,0x7c]
+0x7e,0x04,0x74,0x7c
+
+# W32: v_cmp_eq_u16_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x74,0x7c]
+# W64: v_cmp_eq_u16_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x74,0x7c]
+0x7f,0x04,0x74,0x7c
+
+# W32: v_cmp_eq_u16_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x74,0x7c]
+# W64: v_cmp_eq_u16_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x74,0x7c]
+0x7c,0x04,0x74,0x7c
+
+# W32: v_cmp_eq_u16_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x74,0x7c]
+# W64: v_cmp_eq_u16_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x74,0x7c]
+0xc1,0x04,0x74,0x7c
+
+# W32: v_cmp_eq_u16_e32 vcc_lo, 0x3800, v2
+# W64: v_cmp_eq_u16_e32 vcc, 0x3800, v2          ; encoding: [0xff,0x04,0x74,0x7c,0x00,0x38,0x00,0x00]
+0xf0,0x04,0x74,0x7c
+
+# W32: v_cmp_eq_u16_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x74,0x7c]
+# W64: v_cmp_eq_u16_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x74,0x7c]
+0xfd,0x04,0x74,0x7c
+
+# W32: v_cmp_eq_u16_e32 vcc_lo, 0xfe0b, v127     ; encoding: [0xff,0xfe,0x74,0x7c,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_eq_u16_e32 vcc, 0xfe0b, v127        ; encoding: [0xff,0xfe,0x74,0x7c,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x74,0x7c,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_eq_u32_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x94,0x7c]
+# W64: v_cmp_eq_u32_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x94,0x7c]
+0x01,0x05,0x94,0x7c
+
+# W32: v_cmp_eq_u32_e32 vcc_lo, v255, v2         ; encoding: [0xff,0x05,0x94,0x7c]
+# W64: v_cmp_eq_u32_e32 vcc, v255, v2            ; encoding: [0xff,0x05,0x94,0x7c]
+0xff,0x05,0x94,0x7c
+
+# W32: v_cmp_eq_u32_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x94,0x7c]
+# W64: v_cmp_eq_u32_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x94,0x7c]
+0x01,0x04,0x94,0x7c
+
+# W32: v_cmp_eq_u32_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x94,0x7c]
+# W64: v_cmp_eq_u32_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x94,0x7c]
+0x69,0x04,0x94,0x7c
+
+# W32: v_cmp_eq_u32_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x94,0x7c]
+# W64: v_cmp_eq_u32_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x94,0x7c]
+0x6a,0x04,0x94,0x7c
+
+# W32: v_cmp_eq_u32_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x94,0x7c]
+# W64: v_cmp_eq_u32_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x94,0x7c]
+0x6b,0x04,0x94,0x7c
+
+# W32: v_cmp_eq_u32_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x94,0x7c]
+# W64: v_cmp_eq_u32_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x94,0x7c]
+0x7b,0x04,0x94,0x7c
+
+# W32: v_cmp_eq_u32_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x94,0x7c]
+# W64: v_cmp_eq_u32_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x94,0x7c]
+0x7d,0x04,0x94,0x7c
+
+# W32: v_cmp_eq_u32_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x94,0x7c]
+# W64: v_cmp_eq_u32_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x94,0x7c]
+0x7e,0x04,0x94,0x7c
+
+# W32: v_cmp_eq_u32_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x94,0x7c]
+# W64: v_cmp_eq_u32_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x94,0x7c]
+0x7f,0x04,0x94,0x7c
+
+# W32: v_cmp_eq_u32_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x94,0x7c]
+# W64: v_cmp_eq_u32_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x94,0x7c]
+0x7c,0x04,0x94,0x7c
+
+# W32: v_cmp_eq_u32_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x94,0x7c]
+# W64: v_cmp_eq_u32_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x94,0x7c]
+0xc1,0x04,0x94,0x7c
+
+# W32: v_cmp_eq_u32_e32 vcc_lo, 0.5, v2          ; encoding: [0xf0,0x04,0x94,0x7c]
+# W64: v_cmp_eq_u32_e32 vcc, 0.5, v2             ; encoding: [0xf0,0x04,0x94,0x7c]
+0xf0,0x04,0x94,0x7c
+
+# W32: v_cmp_eq_u32_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x94,0x7c]
+# W64: v_cmp_eq_u32_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x94,0x7c]
+0xfd,0x04,0x94,0x7c
+
+# W32: v_cmp_eq_u32_e32 vcc_lo, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x95,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_eq_u32_e32 vcc, 0xaf123456, v255    ; encoding: [0xff,0xfe,0x95,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x95,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_eq_u64_e32 vcc_lo, v[1:2], v[2:3]   ; encoding: [0x01,0x05,0xb4,0x7c]
+# W64: v_cmp_eq_u64_e32 vcc, v[1:2], v[2:3]      ; encoding: [0x01,0x05,0xb4,0x7c]
+0x01,0x05,0xb4,0x7c
+
+# W32: v_cmp_eq_u64_e32 vcc_lo, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0xb4,0x7c]
+# W64: v_cmp_eq_u64_e32 vcc, v[254:255], v[2:3]  ; encoding: [0xfe,0x05,0xb4,0x7c]
+0xfe,0x05,0xb4,0x7c
+
+# W32: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[2:3]   ; encoding: [0x02,0x04,0xb4,0x7c]
+# W64: v_cmp_eq_u64_e32 vcc, s[2:3], v[2:3]      ; encoding: [0x02,0x04,0xb4,0x7c]
+0x02,0x04,0xb4,0x7c
+
+# W32: v_cmp_eq_u64_e32 vcc_lo, s[104:105], v[2:3] ; encoding: [0x68,0x04,0xb4,0x7c]
+# W64: v_cmp_eq_u64_e32 vcc, s[104:105], v[2:3]  ; encoding: [0x68,0x04,0xb4,0x7c]
+0x68,0x04,0xb4,0x7c
+
+# W32: v_cmp_eq_u64_e32 vcc_lo, vcc, v[2:3]      ; encoding: [0x6a,0x04,0xb4,0x7c]
+# W64: v_cmp_eq_u64_e32 vcc, vcc, v[2:3]         ; encoding: [0x6a,0x04,0xb4,0x7c]
+0x6a,0x04,0xb4,0x7c
+
+# W32: v_cmp_eq_u64_e32 vcc_lo, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0xb4,0x7c]
+# W64: v_cmp_eq_u64_e32 vcc, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0xb4,0x7c]
+0x7a,0x04,0xb4,0x7c
+
+# W32: v_cmp_eq_u64_e32 vcc_lo, exec, v[2:3]     ; encoding: [0x7e,0x04,0xb4,0x7c]
+# W64: v_cmp_eq_u64_e32 vcc, exec, v[2:3]        ; encoding: [0x7e,0x04,0xb4,0x7c]
+0x7e,0x04,0xb4,0x7c
+
+# W32: v_cmp_eq_u64_e32 vcc_lo, null, v[2:3]     ; encoding: [0x7c,0x04,0xb4,0x7c]
+# W64: v_cmp_eq_u64_e32 vcc, null, v[2:3]        ; encoding: [0x7c,0x04,0xb4,0x7c]
+0x7c,0x04,0xb4,0x7c
+
+# W32: v_cmp_eq_u64_e32 vcc_lo, -1, v[2:3]       ; encoding: [0xc1,0x04,0xb4,0x7c]
+# W64: v_cmp_eq_u64_e32 vcc, -1, v[2:3]          ; encoding: [0xc1,0x04,0xb4,0x7c]
+0xc1,0x04,0xb4,0x7c
+
+# W32: v_cmp_eq_u64_e32 vcc_lo, 0.5, v[2:3]      ; encoding: [0xf0,0x04,0xb4,0x7c]
+# W64: v_cmp_eq_u64_e32 vcc, 0.5, v[2:3]         ; encoding: [0xf0,0x04,0xb4,0x7c]
+0xf0,0x04,0xb4,0x7c
+
+# W32: v_cmp_eq_u64_e32 vcc_lo, src_scc, v[2:3]  ; encoding: [0xfd,0x04,0xb4,0x7c]
+# W64: v_cmp_eq_u64_e32 vcc, src_scc, v[2:3]     ; encoding: [0xfd,0x04,0xb4,0x7c]
+0xfd,0x04,0xb4,0x7c
+
+# W32: v_cmp_eq_u64_e32 vcc_lo, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xb5,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_eq_u64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xb5,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xb5,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ge_f16_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x0c,0x7c]
+# W64: v_cmp_ge_f16_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x0c,0x7c]
+0x01,0x05,0x0c,0x7c
+
+# W32: v_cmp_ge_f16_e32 vcc_lo, v127, v2         ; encoding: [0x7f,0x05,0x0c,0x7c]
+# W64: v_cmp_ge_f16_e32 vcc, v127, v2            ; encoding: [0x7f,0x05,0x0c,0x7c]
+0x7f,0x05,0x0c,0x7c
+
+# W32: v_cmp_ge_f16_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x0c,0x7c]
+# W64: v_cmp_ge_f16_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x0c,0x7c]
+0x01,0x04,0x0c,0x7c
+
+# W32: v_cmp_ge_f16_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x0c,0x7c]
+# W64: v_cmp_ge_f16_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x0c,0x7c]
+0x69,0x04,0x0c,0x7c
+
+# W32: v_cmp_ge_f16_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x0c,0x7c]
+# W64: v_cmp_ge_f16_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x0c,0x7c]
+0x6a,0x04,0x0c,0x7c
+
+# W32: v_cmp_ge_f16_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x0c,0x7c]
+# W64: v_cmp_ge_f16_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x0c,0x7c]
+0x6b,0x04,0x0c,0x7c
+
+# W32: v_cmp_ge_f16_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x0c,0x7c]
+# W64: v_cmp_ge_f16_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x0c,0x7c]
+0x7b,0x04,0x0c,0x7c
+
+# W32: v_cmp_ge_f16_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x0c,0x7c]
+# W64: v_cmp_ge_f16_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x0c,0x7c]
+0x7d,0x04,0x0c,0x7c
+
+# W32: v_cmp_ge_f16_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x0c,0x7c]
+# W64: v_cmp_ge_f16_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x0c,0x7c]
+0x7e,0x04,0x0c,0x7c
+
+# W32: v_cmp_ge_f16_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x0c,0x7c]
+# W64: v_cmp_ge_f16_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x0c,0x7c]
+0x7f,0x04,0x0c,0x7c
+
+# W32: v_cmp_ge_f16_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x0c,0x7c]
+# W64: v_cmp_ge_f16_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x0c,0x7c]
+0x7c,0x04,0x0c,0x7c
+
+# W32: v_cmp_ge_f16_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x0c,0x7c]
+# W64: v_cmp_ge_f16_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x0c,0x7c]
+0xc1,0x04,0x0c,0x7c
+
+# W32: v_cmp_ge_f16_e32 vcc_lo, 0.5, v2          ; encoding: [0xf0,0x04,0x0c,0x7c]
+# W64: v_cmp_ge_f16_e32 vcc, 0.5, v2             ; encoding: [0xf0,0x04,0x0c,0x7c]
+0xf0,0x04,0x0c,0x7c
+
+# W32: v_cmp_ge_f16_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x0c,0x7c]
+# W64: v_cmp_ge_f16_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x0c,0x7c]
+0xfd,0x04,0x0c,0x7c
+
+# W32: v_cmp_ge_f16_e32 vcc_lo, 0xfe0b, v127     ; encoding: [0xff,0xfe,0x0c,0x7c,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_ge_f16_e32 vcc, 0xfe0b, v127        ; encoding: [0xff,0xfe,0x0c,0x7c,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x0c,0x7c,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_ge_f32_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x2c,0x7c]
+# W64: v_cmp_ge_f32_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x2c,0x7c]
+0x01,0x05,0x2c,0x7c
+
+# W32: v_cmp_ge_f32_e32 vcc_lo, v255, v2         ; encoding: [0xff,0x05,0x2c,0x7c]
+# W64: v_cmp_ge_f32_e32 vcc, v255, v2            ; encoding: [0xff,0x05,0x2c,0x7c]
+0xff,0x05,0x2c,0x7c
+
+# W32: v_cmp_ge_f32_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x2c,0x7c]
+# W64: v_cmp_ge_f32_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x2c,0x7c]
+0x01,0x04,0x2c,0x7c
+
+# W32: v_cmp_ge_f32_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x2c,0x7c]
+# W64: v_cmp_ge_f32_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x2c,0x7c]
+0x69,0x04,0x2c,0x7c
+
+# W32: v_cmp_ge_f32_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x2c,0x7c]
+# W64: v_cmp_ge_f32_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x2c,0x7c]
+0x6a,0x04,0x2c,0x7c
+
+# W32: v_cmp_ge_f32_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x2c,0x7c]
+# W64: v_cmp_ge_f32_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x2c,0x7c]
+0x6b,0x04,0x2c,0x7c
+
+# W32: v_cmp_ge_f32_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x2c,0x7c]
+# W64: v_cmp_ge_f32_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x2c,0x7c]
+0x7b,0x04,0x2c,0x7c
+
+# W32: v_cmp_ge_f32_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x2c,0x7c]
+# W64: v_cmp_ge_f32_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x2c,0x7c]
+0x7d,0x04,0x2c,0x7c
+
+# W32: v_cmp_ge_f32_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x2c,0x7c]
+# W64: v_cmp_ge_f32_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x2c,0x7c]
+0x7e,0x04,0x2c,0x7c
+
+# W32: v_cmp_ge_f32_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x2c,0x7c]
+# W64: v_cmp_ge_f32_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x2c,0x7c]
+0x7f,0x04,0x2c,0x7c
+
+# W32: v_cmp_ge_f32_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x2c,0x7c]
+# W64: v_cmp_ge_f32_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x2c,0x7c]
+0x7c,0x04,0x2c,0x7c
+
+# W32: v_cmp_ge_f32_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x2c,0x7c]
+# W64: v_cmp_ge_f32_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x2c,0x7c]
+0xc1,0x04,0x2c,0x7c
+
+# W32: v_cmp_ge_f32_e32 vcc_lo, 0.5, v2          ; encoding: [0xf0,0x04,0x2c,0x7c]
+# W64: v_cmp_ge_f32_e32 vcc, 0.5, v2             ; encoding: [0xf0,0x04,0x2c,0x7c]
+0xf0,0x04,0x2c,0x7c
+
+# W32: v_cmp_ge_f32_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x2c,0x7c]
+# W64: v_cmp_ge_f32_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x2c,0x7c]
+0xfd,0x04,0x2c,0x7c
+
+# W32: v_cmp_ge_f32_e32 vcc_lo, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x2d,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_ge_f32_e32 vcc, 0xaf123456, v255    ; encoding: [0xff,0xfe,0x2d,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x2d,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ge_f64_e32 vcc_lo, v[1:2], v[2:3]   ; encoding: [0x01,0x05,0x4c,0x7c]
+# W64: v_cmp_ge_f64_e32 vcc, v[1:2], v[2:3]      ; encoding: [0x01,0x05,0x4c,0x7c]
+0x01,0x05,0x4c,0x7c
+
+# W32: v_cmp_ge_f64_e32 vcc_lo, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x4c,0x7c]
+# W64: v_cmp_ge_f64_e32 vcc, v[254:255], v[2:3]  ; encoding: [0xfe,0x05,0x4c,0x7c]
+0xfe,0x05,0x4c,0x7c
+
+# W32: v_cmp_ge_f64_e32 vcc_lo, s[2:3], v[2:3]   ; encoding: [0x02,0x04,0x4c,0x7c]
+# W64: v_cmp_ge_f64_e32 vcc, s[2:3], v[2:3]      ; encoding: [0x02,0x04,0x4c,0x7c]
+0x02,0x04,0x4c,0x7c
+
+# W32: v_cmp_ge_f64_e32 vcc_lo, s[104:105], v[2:3] ; encoding: [0x68,0x04,0x4c,0x7c]
+# W64: v_cmp_ge_f64_e32 vcc, s[104:105], v[2:3]  ; encoding: [0x68,0x04,0x4c,0x7c]
+0x68,0x04,0x4c,0x7c
+
+# W32: v_cmp_ge_f64_e32 vcc_lo, vcc, v[2:3]      ; encoding: [0x6a,0x04,0x4c,0x7c]
+# W64: v_cmp_ge_f64_e32 vcc, vcc, v[2:3]         ; encoding: [0x6a,0x04,0x4c,0x7c]
+0x6a,0x04,0x4c,0x7c
+
+# W32: v_cmp_ge_f64_e32 vcc_lo, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x4c,0x7c]
+# W64: v_cmp_ge_f64_e32 vcc, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x4c,0x7c]
+0x7a,0x04,0x4c,0x7c
+
+# W32: v_cmp_ge_f64_e32 vcc_lo, exec, v[2:3]     ; encoding: [0x7e,0x04,0x4c,0x7c]
+# W64: v_cmp_ge_f64_e32 vcc, exec, v[2:3]        ; encoding: [0x7e,0x04,0x4c,0x7c]
+0x7e,0x04,0x4c,0x7c
+
+# W32: v_cmp_ge_f64_e32 vcc_lo, null, v[2:3]     ; encoding: [0x7c,0x04,0x4c,0x7c]
+# W64: v_cmp_ge_f64_e32 vcc, null, v[2:3]        ; encoding: [0x7c,0x04,0x4c,0x7c]
+0x7c,0x04,0x4c,0x7c
+
+# W32: v_cmp_ge_f64_e32 vcc_lo, -1, v[2:3]       ; encoding: [0xc1,0x04,0x4c,0x7c]
+# W64: v_cmp_ge_f64_e32 vcc, -1, v[2:3]          ; encoding: [0xc1,0x04,0x4c,0x7c]
+0xc1,0x04,0x4c,0x7c
+
+# W32: v_cmp_ge_f64_e32 vcc_lo, 0.5, v[2:3]      ; encoding: [0xf0,0x04,0x4c,0x7c]
+# W64: v_cmp_ge_f64_e32 vcc, 0.5, v[2:3]         ; encoding: [0xf0,0x04,0x4c,0x7c]
+0xf0,0x04,0x4c,0x7c
+
+# W32: v_cmp_ge_f64_e32 vcc_lo, src_scc, v[2:3]  ; encoding: [0xfd,0x04,0x4c,0x7c]
+# W64: v_cmp_ge_f64_e32 vcc, src_scc, v[2:3]     ; encoding: [0xfd,0x04,0x4c,0x7c]
+0xfd,0x04,0x4c,0x7c
+
+# W32: v_cmp_ge_f64_e32 vcc_lo, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x4d,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_ge_f64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x4d,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x4d,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ge_i16_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x6c,0x7c]
+# W64: v_cmp_ge_i16_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x6c,0x7c]
+0x01,0x05,0x6c,0x7c
+
+# W32: v_cmp_ge_i16_e32 vcc_lo, v127, v2         ; encoding: [0x7f,0x05,0x6c,0x7c]
+# W64: v_cmp_ge_i16_e32 vcc, v127, v2            ; encoding: [0x7f,0x05,0x6c,0x7c]
+0x7f,0x05,0x6c,0x7c
+
+# W32: v_cmp_ge_i16_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x6c,0x7c]
+# W64: v_cmp_ge_i16_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x6c,0x7c]
+0x01,0x04,0x6c,0x7c
+
+# W32: v_cmp_ge_i16_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x6c,0x7c]
+# W64: v_cmp_ge_i16_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x6c,0x7c]
+0x69,0x04,0x6c,0x7c
+
+# W32: v_cmp_ge_i16_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x6c,0x7c]
+# W64: v_cmp_ge_i16_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x6c,0x7c]
+0x6a,0x04,0x6c,0x7c
+
+# W32: v_cmp_ge_i16_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x6c,0x7c]
+# W64: v_cmp_ge_i16_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x6c,0x7c]
+0x6b,0x04,0x6c,0x7c
+
+# W32: v_cmp_ge_i16_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x6c,0x7c]
+# W64: v_cmp_ge_i16_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x6c,0x7c]
+0x7b,0x04,0x6c,0x7c
+
+# W32: v_cmp_ge_i16_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x6c,0x7c]
+# W64: v_cmp_ge_i16_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x6c,0x7c]
+0x7d,0x04,0x6c,0x7c
+
+# W32: v_cmp_ge_i16_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x6c,0x7c]
+# W64: v_cmp_ge_i16_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x6c,0x7c]
+0x7e,0x04,0x6c,0x7c
+
+# W32: v_cmp_ge_i16_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x6c,0x7c]
+# W64: v_cmp_ge_i16_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x6c,0x7c]
+0x7f,0x04,0x6c,0x7c
+
+# W32: v_cmp_ge_i16_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x6c,0x7c]
+# W64: v_cmp_ge_i16_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x6c,0x7c]
+0x7c,0x04,0x6c,0x7c
+
+# W32: v_cmp_ge_i16_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x6c,0x7c]
+# W64: v_cmp_ge_i16_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x6c,0x7c]
+0xc1,0x04,0x6c,0x7c
+
+# W32: v_cmp_ge_i16_e32 vcc_lo, 0x3800, v2
+# W64: v_cmp_ge_i16_e32 vcc, 0x3800, v2          ; encoding: [0xff,0x04,0x6c,0x7c,0x00,0x38,0x00,0x00]
+0xf0,0x04,0x6c,0x7c
+
+# W32: v_cmp_ge_i16_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x6c,0x7c]
+# W64: v_cmp_ge_i16_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x6c,0x7c]
+0xfd,0x04,0x6c,0x7c
+
+# W32: v_cmp_ge_i16_e32 vcc_lo, 0xfe0b, v127     ; encoding: [0xff,0xfe,0x6c,0x7c,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_ge_i16_e32 vcc, 0xfe0b, v127        ; encoding: [0xff,0xfe,0x6c,0x7c,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x6c,0x7c,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_ge_i32_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x8c,0x7c]
+# W64: v_cmp_ge_i32_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x8c,0x7c]
+0x01,0x05,0x8c,0x7c
+
+# W32: v_cmp_ge_i32_e32 vcc_lo, v255, v2         ; encoding: [0xff,0x05,0x8c,0x7c]
+# W64: v_cmp_ge_i32_e32 vcc, v255, v2            ; encoding: [0xff,0x05,0x8c,0x7c]
+0xff,0x05,0x8c,0x7c
+
+# W32: v_cmp_ge_i32_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x8c,0x7c]
+# W64: v_cmp_ge_i32_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x8c,0x7c]
+0x01,0x04,0x8c,0x7c
+
+# W32: v_cmp_ge_i32_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x8c,0x7c]
+# W64: v_cmp_ge_i32_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x8c,0x7c]
+0x69,0x04,0x8c,0x7c
+
+# W32: v_cmp_ge_i32_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x8c,0x7c]
+# W64: v_cmp_ge_i32_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x8c,0x7c]
+0x6a,0x04,0x8c,0x7c
+
+# W32: v_cmp_ge_i32_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x8c,0x7c]
+# W64: v_cmp_ge_i32_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x8c,0x7c]
+0x6b,0x04,0x8c,0x7c
+
+# W32: v_cmp_ge_i32_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x8c,0x7c]
+# W64: v_cmp_ge_i32_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x8c,0x7c]
+0x7b,0x04,0x8c,0x7c
+
+# W32: v_cmp_ge_i32_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x8c,0x7c]
+# W64: v_cmp_ge_i32_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x8c,0x7c]
+0x7d,0x04,0x8c,0x7c
+
+# W32: v_cmp_ge_i32_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x8c,0x7c]
+# W64: v_cmp_ge_i32_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x8c,0x7c]
+0x7e,0x04,0x8c,0x7c
+
+# W32: v_cmp_ge_i32_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x8c,0x7c]
+# W64: v_cmp_ge_i32_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x8c,0x7c]
+0x7f,0x04,0x8c,0x7c
+
+# W32: v_cmp_ge_i32_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x8c,0x7c]
+# W64: v_cmp_ge_i32_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x8c,0x7c]
+0x7c,0x04,0x8c,0x7c
+
+# W32: v_cmp_ge_i32_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x8c,0x7c]
+# W64: v_cmp_ge_i32_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x8c,0x7c]
+0xc1,0x04,0x8c,0x7c
+
+# W32: v_cmp_ge_i32_e32 vcc_lo, 0.5, v2          ; encoding: [0xf0,0x04,0x8c,0x7c]
+# W64: v_cmp_ge_i32_e32 vcc, 0.5, v2             ; encoding: [0xf0,0x04,0x8c,0x7c]
+0xf0,0x04,0x8c,0x7c
+
+# W32: v_cmp_ge_i32_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x8c,0x7c]
+# W64: v_cmp_ge_i32_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x8c,0x7c]
+0xfd,0x04,0x8c,0x7c
+
+# W32: v_cmp_ge_i32_e32 vcc_lo, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x8d,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_ge_i32_e32 vcc, 0xaf123456, v255    ; encoding: [0xff,0xfe,0x8d,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x8d,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ge_i64_e32 vcc_lo, v[1:2], v[2:3]   ; encoding: [0x01,0x05,0xac,0x7c]
+# W64: v_cmp_ge_i64_e32 vcc, v[1:2], v[2:3]      ; encoding: [0x01,0x05,0xac,0x7c]
+0x01,0x05,0xac,0x7c
+
+# W32: v_cmp_ge_i64_e32 vcc_lo, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0xac,0x7c]
+# W64: v_cmp_ge_i64_e32 vcc, v[254:255], v[2:3]  ; encoding: [0xfe,0x05,0xac,0x7c]
+0xfe,0x05,0xac,0x7c
+
+# W32: v_cmp_ge_i64_e32 vcc_lo, s[2:3], v[2:3]   ; encoding: [0x02,0x04,0xac,0x7c]
+# W64: v_cmp_ge_i64_e32 vcc, s[2:3], v[2:3]      ; encoding: [0x02,0x04,0xac,0x7c]
+0x02,0x04,0xac,0x7c
+
+# W32: v_cmp_ge_i64_e32 vcc_lo, s[104:105], v[2:3] ; encoding: [0x68,0x04,0xac,0x7c]
+# W64: v_cmp_ge_i64_e32 vcc, s[104:105], v[2:3]  ; encoding: [0x68,0x04,0xac,0x7c]
+0x68,0x04,0xac,0x7c
+
+# W32: v_cmp_ge_i64_e32 vcc_lo, vcc, v[2:3]      ; encoding: [0x6a,0x04,0xac,0x7c]
+# W64: v_cmp_ge_i64_e32 vcc, vcc, v[2:3]         ; encoding: [0x6a,0x04,0xac,0x7c]
+0x6a,0x04,0xac,0x7c
+
+# W32: v_cmp_ge_i64_e32 vcc_lo, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0xac,0x7c]
+# W64: v_cmp_ge_i64_e32 vcc, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0xac,0x7c]
+0x7a,0x04,0xac,0x7c
+
+# W32: v_cmp_ge_i64_e32 vcc_lo, exec, v[2:3]     ; encoding: [0x7e,0x04,0xac,0x7c]
+# W64: v_cmp_ge_i64_e32 vcc, exec, v[2:3]        ; encoding: [0x7e,0x04,0xac,0x7c]
+0x7e,0x04,0xac,0x7c
+
+# W32: v_cmp_ge_i64_e32 vcc_lo, null, v[2:3]     ; encoding: [0x7c,0x04,0xac,0x7c]
+# W64: v_cmp_ge_i64_e32 vcc, null, v[2:3]        ; encoding: [0x7c,0x04,0xac,0x7c]
+0x7c,0x04,0xac,0x7c
+
+# W32: v_cmp_ge_i64_e32 vcc_lo, -1, v[2:3]       ; encoding: [0xc1,0x04,0xac,0x7c]
+# W64: v_cmp_ge_i64_e32 vcc, -1, v[2:3]          ; encoding: [0xc1,0x04,0xac,0x7c]
+0xc1,0x04,0xac,0x7c
+
+# W32: v_cmp_ge_i64_e32 vcc_lo, 0.5, v[2:3]      ; encoding: [0xf0,0x04,0xac,0x7c]
+# W64: v_cmp_ge_i64_e32 vcc, 0.5, v[2:3]         ; encoding: [0xf0,0x04,0xac,0x7c]
+0xf0,0x04,0xac,0x7c
+
+# W32: v_cmp_ge_i64_e32 vcc_lo, src_scc, v[2:3]  ; encoding: [0xfd,0x04,0xac,0x7c]
+# W64: v_cmp_ge_i64_e32 vcc, src_scc, v[2:3]     ; encoding: [0xfd,0x04,0xac,0x7c]
+0xfd,0x04,0xac,0x7c
+
+# W32: v_cmp_ge_i64_e32 vcc_lo, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xad,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_ge_i64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xad,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xad,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ge_u16_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x7c,0x7c]
+# W64: v_cmp_ge_u16_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x7c,0x7c]
+0x01,0x05,0x7c,0x7c
+
+# W32: v_cmp_ge_u16_e32 vcc_lo, v127, v2         ; encoding: [0x7f,0x05,0x7c,0x7c]
+# W64: v_cmp_ge_u16_e32 vcc, v127, v2            ; encoding: [0x7f,0x05,0x7c,0x7c]
+0x7f,0x05,0x7c,0x7c
+
+# W32: v_cmp_ge_u16_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x7c,0x7c]
+# W64: v_cmp_ge_u16_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x7c,0x7c]
+0x01,0x04,0x7c,0x7c
+
+# W32: v_cmp_ge_u16_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x7c,0x7c]
+# W64: v_cmp_ge_u16_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x7c,0x7c]
+0x69,0x04,0x7c,0x7c
+
+# W32: v_cmp_ge_u16_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x7c,0x7c]
+# W64: v_cmp_ge_u16_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x7c,0x7c]
+0x6a,0x04,0x7c,0x7c
+
+# W32: v_cmp_ge_u16_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x7c,0x7c]
+# W64: v_cmp_ge_u16_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x7c,0x7c]
+0x6b,0x04,0x7c,0x7c
+
+# W32: v_cmp_ge_u16_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x7c,0x7c]
+# W64: v_cmp_ge_u16_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x7c,0x7c]
+0x7b,0x04,0x7c,0x7c
+
+# W32: v_cmp_ge_u16_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x7c,0x7c]
+# W64: v_cmp_ge_u16_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x7c,0x7c]
+0x7d,0x04,0x7c,0x7c
+
+# W32: v_cmp_ge_u16_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x7c,0x7c]
+# W64: v_cmp_ge_u16_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x7c,0x7c]
+0x7e,0x04,0x7c,0x7c
+
+# W32: v_cmp_ge_u16_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x7c,0x7c]
+# W64: v_cmp_ge_u16_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x7c,0x7c]
+0x7f,0x04,0x7c,0x7c
+
+# W32: v_cmp_ge_u16_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x7c,0x7c]
+# W64: v_cmp_ge_u16_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x7c,0x7c]
+0x7c,0x04,0x7c,0x7c
+
+# W32: v_cmp_ge_u16_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x7c,0x7c]
+# W64: v_cmp_ge_u16_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x7c,0x7c]
+0xc1,0x04,0x7c,0x7c
+
+# W32: v_cmp_ge_u16_e32 vcc_lo, 0x3800, v2
+# W64: v_cmp_ge_u16_e32 vcc, 0x3800, v2          ; encoding: [0xff,0x04,0x7c,0x7c,0x00,0x38,0x00,0x00]
+0xf0,0x04,0x7c,0x7c
+
+# W32: v_cmp_ge_u16_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x7c,0x7c]
+# W64: v_cmp_ge_u16_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x7c,0x7c]
+0xfd,0x04,0x7c,0x7c
+
+# W32: v_cmp_ge_u16_e32 vcc_lo, 0xfe0b, v127     ; encoding: [0xff,0xfe,0x7c,0x7c,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_ge_u16_e32 vcc, 0xfe0b, v127        ; encoding: [0xff,0xfe,0x7c,0x7c,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x7c,0x7c,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_ge_u32_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x9c,0x7c]
+# W64: v_cmp_ge_u32_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x9c,0x7c]
+0x01,0x05,0x9c,0x7c
+
+# W32: v_cmp_ge_u32_e32 vcc_lo, v255, v2         ; encoding: [0xff,0x05,0x9c,0x7c]
+# W64: v_cmp_ge_u32_e32 vcc, v255, v2            ; encoding: [0xff,0x05,0x9c,0x7c]
+0xff,0x05,0x9c,0x7c
+
+# W32: v_cmp_ge_u32_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x9c,0x7c]
+# W64: v_cmp_ge_u32_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x9c,0x7c]
+0x01,0x04,0x9c,0x7c
+
+# W32: v_cmp_ge_u32_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x9c,0x7c]
+# W64: v_cmp_ge_u32_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x9c,0x7c]
+0x69,0x04,0x9c,0x7c
+
+# W32: v_cmp_ge_u32_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x9c,0x7c]
+# W64: v_cmp_ge_u32_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x9c,0x7c]
+0x6a,0x04,0x9c,0x7c
+
+# W32: v_cmp_ge_u32_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x9c,0x7c]
+# W64: v_cmp_ge_u32_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x9c,0x7c]
+0x6b,0x04,0x9c,0x7c
+
+# W32: v_cmp_ge_u32_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x9c,0x7c]
+# W64: v_cmp_ge_u32_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x9c,0x7c]
+0x7b,0x04,0x9c,0x7c
+
+# W32: v_cmp_ge_u32_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x9c,0x7c]
+# W64: v_cmp_ge_u32_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x9c,0x7c]
+0x7d,0x04,0x9c,0x7c
+
+# W32: v_cmp_ge_u32_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x9c,0x7c]
+# W64: v_cmp_ge_u32_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x9c,0x7c]
+0x7e,0x04,0x9c,0x7c
+
+# W32: v_cmp_ge_u32_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x9c,0x7c]
+# W64: v_cmp_ge_u32_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x9c,0x7c]
+0x7f,0x04,0x9c,0x7c
+
+# W32: v_cmp_ge_u32_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x9c,0x7c]
+# W64: v_cmp_ge_u32_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x9c,0x7c]
+0x7c,0x04,0x9c,0x7c
+
+# W32: v_cmp_ge_u32_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x9c,0x7c]
+# W64: v_cmp_ge_u32_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x9c,0x7c]
+0xc1,0x04,0x9c,0x7c
+
+# W32: v_cmp_ge_u32_e32 vcc_lo, 0.5, v2          ; encoding: [0xf0,0x04,0x9c,0x7c]
+# W64: v_cmp_ge_u32_e32 vcc, 0.5, v2             ; encoding: [0xf0,0x04,0x9c,0x7c]
+0xf0,0x04,0x9c,0x7c
+
+# W32: v_cmp_ge_u32_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x9c,0x7c]
+# W64: v_cmp_ge_u32_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x9c,0x7c]
+0xfd,0x04,0x9c,0x7c
+
+# W32: v_cmp_ge_u32_e32 vcc_lo, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x9d,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_ge_u32_e32 vcc, 0xaf123456, v255    ; encoding: [0xff,0xfe,0x9d,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x9d,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ge_u64_e32 vcc_lo, v[1:2], v[2:3]   ; encoding: [0x01,0x05,0xbc,0x7c]
+# W64: v_cmp_ge_u64_e32 vcc, v[1:2], v[2:3]      ; encoding: [0x01,0x05,0xbc,0x7c]
+0x01,0x05,0xbc,0x7c
+
+# W32: v_cmp_ge_u64_e32 vcc_lo, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0xbc,0x7c]
+# W64: v_cmp_ge_u64_e32 vcc, v[254:255], v[2:3]  ; encoding: [0xfe,0x05,0xbc,0x7c]
+0xfe,0x05,0xbc,0x7c
+
+# W32: v_cmp_ge_u64_e32 vcc_lo, s[2:3], v[2:3]   ; encoding: [0x02,0x04,0xbc,0x7c]
+# W64: v_cmp_ge_u64_e32 vcc, s[2:3], v[2:3]      ; encoding: [0x02,0x04,0xbc,0x7c]
+0x02,0x04,0xbc,0x7c
+
+# W32: v_cmp_ge_u64_e32 vcc_lo, s[104:105], v[2:3] ; encoding: [0x68,0x04,0xbc,0x7c]
+# W64: v_cmp_ge_u64_e32 vcc, s[104:105], v[2:3]  ; encoding: [0x68,0x04,0xbc,0x7c]
+0x68,0x04,0xbc,0x7c
+
+# W32: v_cmp_ge_u64_e32 vcc_lo, vcc, v[2:3]      ; encoding: [0x6a,0x04,0xbc,0x7c]
+# W64: v_cmp_ge_u64_e32 vcc, vcc, v[2:3]         ; encoding: [0x6a,0x04,0xbc,0x7c]
+0x6a,0x04,0xbc,0x7c
+
+# W32: v_cmp_ge_u64_e32 vcc_lo, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0xbc,0x7c]
+# W64: v_cmp_ge_u64_e32 vcc, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0xbc,0x7c]
+0x7a,0x04,0xbc,0x7c
+
+# W32: v_cmp_ge_u64_e32 vcc_lo, exec, v[2:3]     ; encoding: [0x7e,0x04,0xbc,0x7c]
+# W64: v_cmp_ge_u64_e32 vcc, exec, v[2:3]        ; encoding: [0x7e,0x04,0xbc,0x7c]
+0x7e,0x04,0xbc,0x7c
+
+# W32: v_cmp_ge_u64_e32 vcc_lo, null, v[2:3]     ; encoding: [0x7c,0x04,0xbc,0x7c]
+# W64: v_cmp_ge_u64_e32 vcc, null, v[2:3]        ; encoding: [0x7c,0x04,0xbc,0x7c]
+0x7c,0x04,0xbc,0x7c
+
+# W32: v_cmp_ge_u64_e32 vcc_lo, -1, v[2:3]       ; encoding: [0xc1,0x04,0xbc,0x7c]
+# W64: v_cmp_ge_u64_e32 vcc, -1, v[2:3]          ; encoding: [0xc1,0x04,0xbc,0x7c]
+0xc1,0x04,0xbc,0x7c
+
+# W32: v_cmp_ge_u64_e32 vcc_lo, 0.5, v[2:3]      ; encoding: [0xf0,0x04,0xbc,0x7c]
+# W64: v_cmp_ge_u64_e32 vcc, 0.5, v[2:3]         ; encoding: [0xf0,0x04,0xbc,0x7c]
+0xf0,0x04,0xbc,0x7c
+
+# W32: v_cmp_ge_u64_e32 vcc_lo, src_scc, v[2:3]  ; encoding: [0xfd,0x04,0xbc,0x7c]
+# W64: v_cmp_ge_u64_e32 vcc, src_scc, v[2:3]     ; encoding: [0xfd,0x04,0xbc,0x7c]
+0xfd,0x04,0xbc,0x7c
+
+# W32: v_cmp_ge_u64_e32 vcc_lo, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xbd,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_ge_u64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xbd,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xbd,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_gt_f16_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x08,0x7c]
+# W64: v_cmp_gt_f16_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x08,0x7c]
+0x01,0x05,0x08,0x7c
+
+# W32: v_cmp_gt_f16_e32 vcc_lo, v127, v2         ; encoding: [0x7f,0x05,0x08,0x7c]
+# W64: v_cmp_gt_f16_e32 vcc, v127, v2            ; encoding: [0x7f,0x05,0x08,0x7c]
+0x7f,0x05,0x08,0x7c
+
+# W32: v_cmp_gt_f16_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x08,0x7c]
+# W64: v_cmp_gt_f16_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x08,0x7c]
+0x01,0x04,0x08,0x7c
+
+# W32: v_cmp_gt_f16_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x08,0x7c]
+# W64: v_cmp_gt_f16_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x08,0x7c]
+0x69,0x04,0x08,0x7c
+
+# W32: v_cmp_gt_f16_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x08,0x7c]
+# W64: v_cmp_gt_f16_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x08,0x7c]
+0x6a,0x04,0x08,0x7c
+
+# W32: v_cmp_gt_f16_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x08,0x7c]
+# W64: v_cmp_gt_f16_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x08,0x7c]
+0x6b,0x04,0x08,0x7c
+
+# W32: v_cmp_gt_f16_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x08,0x7c]
+# W64: v_cmp_gt_f16_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x08,0x7c]
+0x7b,0x04,0x08,0x7c
+
+# W32: v_cmp_gt_f16_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x08,0x7c]
+# W64: v_cmp_gt_f16_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x08,0x7c]
+0x7d,0x04,0x08,0x7c
+
+# W32: v_cmp_gt_f16_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x08,0x7c]
+# W64: v_cmp_gt_f16_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x08,0x7c]
+0x7e,0x04,0x08,0x7c
+
+# W32: v_cmp_gt_f16_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x08,0x7c]
+# W64: v_cmp_gt_f16_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x08,0x7c]
+0x7f,0x04,0x08,0x7c
+
+# W32: v_cmp_gt_f16_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x08,0x7c]
+# W64: v_cmp_gt_f16_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x08,0x7c]
+0x7c,0x04,0x08,0x7c
+
+# W32: v_cmp_gt_f16_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x08,0x7c]
+# W64: v_cmp_gt_f16_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x08,0x7c]
+0xc1,0x04,0x08,0x7c
+
+# W32: v_cmp_gt_f16_e32 vcc_lo, 0.5, v2          ; encoding: [0xf0,0x04,0x08,0x7c]
+# W64: v_cmp_gt_f16_e32 vcc, 0.5, v2             ; encoding: [0xf0,0x04,0x08,0x7c]
+0xf0,0x04,0x08,0x7c
+
+# W32: v_cmp_gt_f16_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x08,0x7c]
+# W64: v_cmp_gt_f16_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x08,0x7c]
+0xfd,0x04,0x08,0x7c
+
+# W32: v_cmp_gt_f16_e32 vcc_lo, 0xfe0b, v127     ; encoding: [0xff,0xfe,0x08,0x7c,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_gt_f16_e32 vcc, 0xfe0b, v127        ; encoding: [0xff,0xfe,0x08,0x7c,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x08,0x7c,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_gt_f32_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x28,0x7c]
+# W64: v_cmp_gt_f32_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x28,0x7c]
+0x01,0x05,0x28,0x7c
+
+# W32: v_cmp_gt_f32_e32 vcc_lo, v255, v2         ; encoding: [0xff,0x05,0x28,0x7c]
+# W64: v_cmp_gt_f32_e32 vcc, v255, v2            ; encoding: [0xff,0x05,0x28,0x7c]
+0xff,0x05,0x28,0x7c
+
+# W32: v_cmp_gt_f32_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x28,0x7c]
+# W64: v_cmp_gt_f32_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x28,0x7c]
+0x01,0x04,0x28,0x7c
+
+# W32: v_cmp_gt_f32_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x28,0x7c]
+# W64: v_cmp_gt_f32_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x28,0x7c]
+0x69,0x04,0x28,0x7c
+
+# W32: v_cmp_gt_f32_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x28,0x7c]
+# W64: v_cmp_gt_f32_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x28,0x7c]
+0x6a,0x04,0x28,0x7c
+
+# W32: v_cmp_gt_f32_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x28,0x7c]
+# W64: v_cmp_gt_f32_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x28,0x7c]
+0x6b,0x04,0x28,0x7c
+
+# W32: v_cmp_gt_f32_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x28,0x7c]
+# W64: v_cmp_gt_f32_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x28,0x7c]
+0x7b,0x04,0x28,0x7c
+
+# W32: v_cmp_gt_f32_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x28,0x7c]
+# W64: v_cmp_gt_f32_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x28,0x7c]
+0x7d,0x04,0x28,0x7c
+
+# W32: v_cmp_gt_f32_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x28,0x7c]
+# W64: v_cmp_gt_f32_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x28,0x7c]
+0x7e,0x04,0x28,0x7c
+
+# W32: v_cmp_gt_f32_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x28,0x7c]
+# W64: v_cmp_gt_f32_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x28,0x7c]
+0x7f,0x04,0x28,0x7c
+
+# W32: v_cmp_gt_f32_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x28,0x7c]
+# W64: v_cmp_gt_f32_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x28,0x7c]
+0x7c,0x04,0x28,0x7c
+
+# W32: v_cmp_gt_f32_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x28,0x7c]
+# W64: v_cmp_gt_f32_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x28,0x7c]
+0xc1,0x04,0x28,0x7c
+
+# W32: v_cmp_gt_f32_e32 vcc_lo, 0.5, v2          ; encoding: [0xf0,0x04,0x28,0x7c]
+# W64: v_cmp_gt_f32_e32 vcc, 0.5, v2             ; encoding: [0xf0,0x04,0x28,0x7c]
+0xf0,0x04,0x28,0x7c
+
+# W32: v_cmp_gt_f32_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x28,0x7c]
+# W64: v_cmp_gt_f32_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x28,0x7c]
+0xfd,0x04,0x28,0x7c
+
+# W32: v_cmp_gt_f32_e32 vcc_lo, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x29,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_gt_f32_e32 vcc, 0xaf123456, v255    ; encoding: [0xff,0xfe,0x29,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x29,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_gt_f64_e32 vcc_lo, v[1:2], v[2:3]   ; encoding: [0x01,0x05,0x48,0x7c]
+# W64: v_cmp_gt_f64_e32 vcc, v[1:2], v[2:3]      ; encoding: [0x01,0x05,0x48,0x7c]
+0x01,0x05,0x48,0x7c
+
+# W32: v_cmp_gt_f64_e32 vcc_lo, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x48,0x7c]
+# W64: v_cmp_gt_f64_e32 vcc, v[254:255], v[2:3]  ; encoding: [0xfe,0x05,0x48,0x7c]
+0xfe,0x05,0x48,0x7c
+
+# W32: v_cmp_gt_f64_e32 vcc_lo, s[2:3], v[2:3]   ; encoding: [0x02,0x04,0x48,0x7c]
+# W64: v_cmp_gt_f64_e32 vcc, s[2:3], v[2:3]      ; encoding: [0x02,0x04,0x48,0x7c]
+0x02,0x04,0x48,0x7c
+
+# W32: v_cmp_gt_f64_e32 vcc_lo, s[104:105], v[2:3] ; encoding: [0x68,0x04,0x48,0x7c]
+# W64: v_cmp_gt_f64_e32 vcc, s[104:105], v[2:3]  ; encoding: [0x68,0x04,0x48,0x7c]
+0x68,0x04,0x48,0x7c
+
+# W32: v_cmp_gt_f64_e32 vcc_lo, vcc, v[2:3]      ; encoding: [0x6a,0x04,0x48,0x7c]
+# W64: v_cmp_gt_f64_e32 vcc, vcc, v[2:3]         ; encoding: [0x6a,0x04,0x48,0x7c]
+0x6a,0x04,0x48,0x7c
+
+# W32: v_cmp_gt_f64_e32 vcc_lo, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x48,0x7c]
+# W64: v_cmp_gt_f64_e32 vcc, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x48,0x7c]
+0x7a,0x04,0x48,0x7c
+
+# W32: v_cmp_gt_f64_e32 vcc_lo, exec, v[2:3]     ; encoding: [0x7e,0x04,0x48,0x7c]
+# W64: v_cmp_gt_f64_e32 vcc, exec, v[2:3]        ; encoding: [0x7e,0x04,0x48,0x7c]
+0x7e,0x04,0x48,0x7c
+
+# W32: v_cmp_gt_f64_e32 vcc_lo, null, v[2:3]     ; encoding: [0x7c,0x04,0x48,0x7c]
+# W64: v_cmp_gt_f64_e32 vcc, null, v[2:3]        ; encoding: [0x7c,0x04,0x48,0x7c]
+0x7c,0x04,0x48,0x7c
+
+# W32: v_cmp_gt_f64_e32 vcc_lo, -1, v[2:3]       ; encoding: [0xc1,0x04,0x48,0x7c]
+# W64: v_cmp_gt_f64_e32 vcc, -1, v[2:3]          ; encoding: [0xc1,0x04,0x48,0x7c]
+0xc1,0x04,0x48,0x7c
+
+# W32: v_cmp_gt_f64_e32 vcc_lo, 0.5, v[2:3]      ; encoding: [0xf0,0x04,0x48,0x7c]
+# W64: v_cmp_gt_f64_e32 vcc, 0.5, v[2:3]         ; encoding: [0xf0,0x04,0x48,0x7c]
+0xf0,0x04,0x48,0x7c
+
+# W32: v_cmp_gt_f64_e32 vcc_lo, src_scc, v[2:3]  ; encoding: [0xfd,0x04,0x48,0x7c]
+# W64: v_cmp_gt_f64_e32 vcc, src_scc, v[2:3]     ; encoding: [0xfd,0x04,0x48,0x7c]
+0xfd,0x04,0x48,0x7c
+
+# W32: v_cmp_gt_f64_e32 vcc_lo, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x49,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_gt_f64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x49,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x49,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_gt_i16_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x68,0x7c]
+# W64: v_cmp_gt_i16_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x68,0x7c]
+0x01,0x05,0x68,0x7c
+
+# W32: v_cmp_gt_i16_e32 vcc_lo, v127, v2         ; encoding: [0x7f,0x05,0x68,0x7c]
+# W64: v_cmp_gt_i16_e32 vcc, v127, v2            ; encoding: [0x7f,0x05,0x68,0x7c]
+0x7f,0x05,0x68,0x7c
+
+# W32: v_cmp_gt_i16_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x68,0x7c]
+# W64: v_cmp_gt_i16_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x68,0x7c]
+0x01,0x04,0x68,0x7c
+
+# W32: v_cmp_gt_i16_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x68,0x7c]
+# W64: v_cmp_gt_i16_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x68,0x7c]
+0x69,0x04,0x68,0x7c
+
+# W32: v_cmp_gt_i16_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x68,0x7c]
+# W64: v_cmp_gt_i16_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x68,0x7c]
+0x6a,0x04,0x68,0x7c
+
+# W32: v_cmp_gt_i16_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x68,0x7c]
+# W64: v_cmp_gt_i16_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x68,0x7c]
+0x6b,0x04,0x68,0x7c
+
+# W32: v_cmp_gt_i16_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x68,0x7c]
+# W64: v_cmp_gt_i16_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x68,0x7c]
+0x7b,0x04,0x68,0x7c
+
+# W32: v_cmp_gt_i16_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x68,0x7c]
+# W64: v_cmp_gt_i16_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x68,0x7c]
+0x7d,0x04,0x68,0x7c
+
+# W32: v_cmp_gt_i16_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x68,0x7c]
+# W64: v_cmp_gt_i16_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x68,0x7c]
+0x7e,0x04,0x68,0x7c
+
+# W32: v_cmp_gt_i16_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x68,0x7c]
+# W64: v_cmp_gt_i16_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x68,0x7c]
+0x7f,0x04,0x68,0x7c
+
+# W32: v_cmp_gt_i16_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x68,0x7c]
+# W64: v_cmp_gt_i16_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x68,0x7c]
+0x7c,0x04,0x68,0x7c
+
+# W32: v_cmp_gt_i16_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x68,0x7c]
+# W64: v_cmp_gt_i16_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x68,0x7c]
+0xc1,0x04,0x68,0x7c
+
+# W32: v_cmp_gt_i16_e32 vcc_lo, 0x3800, v2
+# W64: v_cmp_gt_i16_e32 vcc, 0x3800, v2          ; encoding: [0xff,0x04,0x68,0x7c,0x00,0x38,0x00,0x00]
+0xf0,0x04,0x68,0x7c
+
+# W32: v_cmp_gt_i16_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x68,0x7c]
+# W64: v_cmp_gt_i16_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x68,0x7c]
+0xfd,0x04,0x68,0x7c
+
+# W32: v_cmp_gt_i16_e32 vcc_lo, 0xfe0b, v127     ; encoding: [0xff,0xfe,0x68,0x7c,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_gt_i16_e32 vcc, 0xfe0b, v127        ; encoding: [0xff,0xfe,0x68,0x7c,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x68,0x7c,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_gt_i32_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x88,0x7c]
+# W64: v_cmp_gt_i32_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x88,0x7c]
+0x01,0x05,0x88,0x7c
+
+# W32: v_cmp_gt_i32_e32 vcc_lo, v255, v2         ; encoding: [0xff,0x05,0x88,0x7c]
+# W64: v_cmp_gt_i32_e32 vcc, v255, v2            ; encoding: [0xff,0x05,0x88,0x7c]
+0xff,0x05,0x88,0x7c
+
+# W32: v_cmp_gt_i32_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x88,0x7c]
+# W64: v_cmp_gt_i32_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x88,0x7c]
+0x01,0x04,0x88,0x7c
+
+# W32: v_cmp_gt_i32_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x88,0x7c]
+# W64: v_cmp_gt_i32_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x88,0x7c]
+0x69,0x04,0x88,0x7c
+
+# W32: v_cmp_gt_i32_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x88,0x7c]
+# W64: v_cmp_gt_i32_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x88,0x7c]
+0x6a,0x04,0x88,0x7c
+
+# W32: v_cmp_gt_i32_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x88,0x7c]
+# W64: v_cmp_gt_i32_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x88,0x7c]
+0x6b,0x04,0x88,0x7c
+
+# W32: v_cmp_gt_i32_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x88,0x7c]
+# W64: v_cmp_gt_i32_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x88,0x7c]
+0x7b,0x04,0x88,0x7c
+
+# W32: v_cmp_gt_i32_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x88,0x7c]
+# W64: v_cmp_gt_i32_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x88,0x7c]
+0x7d,0x04,0x88,0x7c
+
+# W32: v_cmp_gt_i32_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x88,0x7c]
+# W64: v_cmp_gt_i32_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x88,0x7c]
+0x7e,0x04,0x88,0x7c
+
+# W32: v_cmp_gt_i32_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x88,0x7c]
+# W64: v_cmp_gt_i32_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x88,0x7c]
+0x7f,0x04,0x88,0x7c
+
+# W32: v_cmp_gt_i32_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x88,0x7c]
+# W64: v_cmp_gt_i32_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x88,0x7c]
+0x7c,0x04,0x88,0x7c
+
+# W32: v_cmp_gt_i32_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x88,0x7c]
+# W64: v_cmp_gt_i32_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x88,0x7c]
+0xc1,0x04,0x88,0x7c
+
+# W32: v_cmp_gt_i32_e32 vcc_lo, 0.5, v2          ; encoding: [0xf0,0x04,0x88,0x7c]
+# W64: v_cmp_gt_i32_e32 vcc, 0.5, v2             ; encoding: [0xf0,0x04,0x88,0x7c]
+0xf0,0x04,0x88,0x7c
+
+# W32: v_cmp_gt_i32_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x88,0x7c]
+# W64: v_cmp_gt_i32_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x88,0x7c]
+0xfd,0x04,0x88,0x7c
+
+# W32: v_cmp_gt_i32_e32 vcc_lo, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x89,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_gt_i32_e32 vcc, 0xaf123456, v255    ; encoding: [0xff,0xfe,0x89,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x89,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_gt_i64_e32 vcc_lo, v[1:2], v[2:3]   ; encoding: [0x01,0x05,0xa8,0x7c]
+# W64: v_cmp_gt_i64_e32 vcc, v[1:2], v[2:3]      ; encoding: [0x01,0x05,0xa8,0x7c]
+0x01,0x05,0xa8,0x7c
+
+# W32: v_cmp_gt_i64_e32 vcc_lo, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0xa8,0x7c]
+# W64: v_cmp_gt_i64_e32 vcc, v[254:255], v[2:3]  ; encoding: [0xfe,0x05,0xa8,0x7c]
+0xfe,0x05,0xa8,0x7c
+
+# W32: v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[2:3]   ; encoding: [0x02,0x04,0xa8,0x7c]
+# W64: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]      ; encoding: [0x02,0x04,0xa8,0x7c]
+0x02,0x04,0xa8,0x7c
+
+# W32: v_cmp_gt_i64_e32 vcc_lo, s[104:105], v[2:3] ; encoding: [0x68,0x04,0xa8,0x7c]
+# W64: v_cmp_gt_i64_e32 vcc, s[104:105], v[2:3]  ; encoding: [0x68,0x04,0xa8,0x7c]
+0x68,0x04,0xa8,0x7c
+
+# W32: v_cmp_gt_i64_e32 vcc_lo, vcc, v[2:3]      ; encoding: [0x6a,0x04,0xa8,0x7c]
+# W64: v_cmp_gt_i64_e32 vcc, vcc, v[2:3]         ; encoding: [0x6a,0x04,0xa8,0x7c]
+0x6a,0x04,0xa8,0x7c
+
+# W32: v_cmp_gt_i64_e32 vcc_lo, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0xa8,0x7c]
+# W64: v_cmp_gt_i64_e32 vcc, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0xa8,0x7c]
+0x7a,0x04,0xa8,0x7c
+
+# W32: v_cmp_gt_i64_e32 vcc_lo, exec, v[2:3]     ; encoding: [0x7e,0x04,0xa8,0x7c]
+# W64: v_cmp_gt_i64_e32 vcc, exec, v[2:3]        ; encoding: [0x7e,0x04,0xa8,0x7c]
+0x7e,0x04,0xa8,0x7c
+
+# W32: v_cmp_gt_i64_e32 vcc_lo, null, v[2:3]     ; encoding: [0x7c,0x04,0xa8,0x7c]
+# W64: v_cmp_gt_i64_e32 vcc, null, v[2:3]        ; encoding: [0x7c,0x04,0xa8,0x7c]
+0x7c,0x04,0xa8,0x7c
+
+# W32: v_cmp_gt_i64_e32 vcc_lo, -1, v[2:3]       ; encoding: [0xc1,0x04,0xa8,0x7c]
+# W64: v_cmp_gt_i64_e32 vcc, -1, v[2:3]          ; encoding: [0xc1,0x04,0xa8,0x7c]
+0xc1,0x04,0xa8,0x7c
+
+# W32: v_cmp_gt_i64_e32 vcc_lo, 0.5, v[2:3]      ; encoding: [0xf0,0x04,0xa8,0x7c]
+# W64: v_cmp_gt_i64_e32 vcc, 0.5, v[2:3]         ; encoding: [0xf0,0x04,0xa8,0x7c]
+0xf0,0x04,0xa8,0x7c
+
+# W32: v_cmp_gt_i64_e32 vcc_lo, src_scc, v[2:3]  ; encoding: [0xfd,0x04,0xa8,0x7c]
+# W64: v_cmp_gt_i64_e32 vcc, src_scc, v[2:3]     ; encoding: [0xfd,0x04,0xa8,0x7c]
+0xfd,0x04,0xa8,0x7c
+
+# W32: v_cmp_gt_i64_e32 vcc_lo, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xa9,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_gt_i64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xa9,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xa9,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_gt_u16_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x78,0x7c]
+# W64: v_cmp_gt_u16_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x78,0x7c]
+0x01,0x05,0x78,0x7c
+
+# W32: v_cmp_gt_u16_e32 vcc_lo, v127, v2         ; encoding: [0x7f,0x05,0x78,0x7c]
+# W64: v_cmp_gt_u16_e32 vcc, v127, v2            ; encoding: [0x7f,0x05,0x78,0x7c]
+0x7f,0x05,0x78,0x7c
+
+# W32: v_cmp_gt_u16_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x78,0x7c]
+# W64: v_cmp_gt_u16_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x78,0x7c]
+0x01,0x04,0x78,0x7c
+
+# W32: v_cmp_gt_u16_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x78,0x7c]
+# W64: v_cmp_gt_u16_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x78,0x7c]
+0x69,0x04,0x78,0x7c
+
+# W32: v_cmp_gt_u16_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x78,0x7c]
+# W64: v_cmp_gt_u16_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x78,0x7c]
+0x6a,0x04,0x78,0x7c
+
+# W32: v_cmp_gt_u16_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x78,0x7c]
+# W64: v_cmp_gt_u16_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x78,0x7c]
+0x6b,0x04,0x78,0x7c
+
+# W32: v_cmp_gt_u16_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x78,0x7c]
+# W64: v_cmp_gt_u16_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x78,0x7c]
+0x7b,0x04,0x78,0x7c
+
+# W32: v_cmp_gt_u16_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x78,0x7c]
+# W64: v_cmp_gt_u16_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x78,0x7c]
+0x7d,0x04,0x78,0x7c
+
+# W32: v_cmp_gt_u16_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x78,0x7c]
+# W64: v_cmp_gt_u16_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x78,0x7c]
+0x7e,0x04,0x78,0x7c
+
+# W32: v_cmp_gt_u16_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x78,0x7c]
+# W64: v_cmp_gt_u16_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x78,0x7c]
+0x7f,0x04,0x78,0x7c
+
+# W32: v_cmp_gt_u16_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x78,0x7c]
+# W64: v_cmp_gt_u16_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x78,0x7c]
+0x7c,0x04,0x78,0x7c
+
+# W32: v_cmp_gt_u16_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x78,0x7c]
+# W64: v_cmp_gt_u16_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x78,0x7c]
+0xc1,0x04,0x78,0x7c
+
+# W32: v_cmp_gt_u16_e32 vcc_lo, 0x3800, v2
+# W64: v_cmp_gt_u16_e32 vcc, 0x3800, v2          ; encoding: [0xff,0x04,0x78,0x7c,0x00,0x38,0x00,0x00]
+0xf0,0x04,0x78,0x7c
+
+# W32: v_cmp_gt_u16_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x78,0x7c]
+# W64: v_cmp_gt_u16_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x78,0x7c]
+0xfd,0x04,0x78,0x7c
+
+# W32: v_cmp_gt_u16_e32 vcc_lo, 0xfe0b, v127     ; encoding: [0xff,0xfe,0x78,0x7c,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_gt_u16_e32 vcc, 0xfe0b, v127        ; encoding: [0xff,0xfe,0x78,0x7c,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x78,0x7c,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_gt_u32_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x98,0x7c]
+# W64: v_cmp_gt_u32_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x98,0x7c]
+0x01,0x05,0x98,0x7c
+
+# W32: v_cmp_gt_u32_e32 vcc_lo, v255, v2         ; encoding: [0xff,0x05,0x98,0x7c]
+# W64: v_cmp_gt_u32_e32 vcc, v255, v2            ; encoding: [0xff,0x05,0x98,0x7c]
+0xff,0x05,0x98,0x7c
+
+# W32: v_cmp_gt_u32_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x98,0x7c]
+# W64: v_cmp_gt_u32_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x98,0x7c]
+0x01,0x04,0x98,0x7c
+
+# W32: v_cmp_gt_u32_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x98,0x7c]
+# W64: v_cmp_gt_u32_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x98,0x7c]
+0x69,0x04,0x98,0x7c
+
+# W32: v_cmp_gt_u32_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x98,0x7c]
+# W64: v_cmp_gt_u32_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x98,0x7c]
+0x6a,0x04,0x98,0x7c
+
+# W32: v_cmp_gt_u32_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x98,0x7c]
+# W64: v_cmp_gt_u32_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x98,0x7c]
+0x6b,0x04,0x98,0x7c
+
+# W32: v_cmp_gt_u32_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x98,0x7c]
+# W64: v_cmp_gt_u32_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x98,0x7c]
+0x7b,0x04,0x98,0x7c
+
+# W32: v_cmp_gt_u32_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x98,0x7c]
+# W64: v_cmp_gt_u32_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x98,0x7c]
+0x7d,0x04,0x98,0x7c
+
+# W32: v_cmp_gt_u32_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x98,0x7c]
+# W64: v_cmp_gt_u32_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x98,0x7c]
+0x7e,0x04,0x98,0x7c
+
+# W32: v_cmp_gt_u32_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x98,0x7c]
+# W64: v_cmp_gt_u32_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x98,0x7c]
+0x7f,0x04,0x98,0x7c
+
+# W32: v_cmp_gt_u32_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x98,0x7c]
+# W64: v_cmp_gt_u32_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x98,0x7c]
+0x7c,0x04,0x98,0x7c
+
+# W32: v_cmp_gt_u32_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x98,0x7c]
+# W64: v_cmp_gt_u32_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x98,0x7c]
+0xc1,0x04,0x98,0x7c
+
+# W32: v_cmp_gt_u32_e32 vcc_lo, 0.5, v2          ; encoding: [0xf0,0x04,0x98,0x7c]
+# W64: v_cmp_gt_u32_e32 vcc, 0.5, v2             ; encoding: [0xf0,0x04,0x98,0x7c]
+0xf0,0x04,0x98,0x7c
+
+# W32: v_cmp_gt_u32_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x98,0x7c]
+# W64: v_cmp_gt_u32_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x98,0x7c]
+0xfd,0x04,0x98,0x7c
+
+# W32: v_cmp_gt_u32_e32 vcc_lo, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x99,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_gt_u32_e32 vcc, 0xaf123456, v255    ; encoding: [0xff,0xfe,0x99,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x99,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_gt_u64_e32 vcc_lo, v[1:2], v[2:3]   ; encoding: [0x01,0x05,0xb8,0x7c]
+# W64: v_cmp_gt_u64_e32 vcc, v[1:2], v[2:3]      ; encoding: [0x01,0x05,0xb8,0x7c]
+0x01,0x05,0xb8,0x7c
+
+# W32: v_cmp_gt_u64_e32 vcc_lo, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0xb8,0x7c]
+# W64: v_cmp_gt_u64_e32 vcc, v[254:255], v[2:3]  ; encoding: [0xfe,0x05,0xb8,0x7c]
+0xfe,0x05,0xb8,0x7c
+
+# W32: v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[2:3]   ; encoding: [0x02,0x04,0xb8,0x7c]
+# W64: v_cmp_gt_u64_e32 vcc, s[2:3], v[2:3]      ; encoding: [0x02,0x04,0xb8,0x7c]
+0x02,0x04,0xb8,0x7c
+
+# W32: v_cmp_gt_u64_e32 vcc_lo, s[104:105], v[2:3] ; encoding: [0x68,0x04,0xb8,0x7c]
+# W64: v_cmp_gt_u64_e32 vcc, s[104:105], v[2:3]  ; encoding: [0x68,0x04,0xb8,0x7c]
+0x68,0x04,0xb8,0x7c
+
+# W32: v_cmp_gt_u64_e32 vcc_lo, vcc, v[2:3]      ; encoding: [0x6a,0x04,0xb8,0x7c]
+# W64: v_cmp_gt_u64_e32 vcc, vcc, v[2:3]         ; encoding: [0x6a,0x04,0xb8,0x7c]
+0x6a,0x04,0xb8,0x7c
+
+# W32: v_cmp_gt_u64_e32 vcc_lo, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0xb8,0x7c]
+# W64: v_cmp_gt_u64_e32 vcc, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0xb8,0x7c]
+0x7a,0x04,0xb8,0x7c
+
+# W32: v_cmp_gt_u64_e32 vcc_lo, exec, v[2:3]     ; encoding: [0x7e,0x04,0xb8,0x7c]
+# W64: v_cmp_gt_u64_e32 vcc, exec, v[2:3]        ; encoding: [0x7e,0x04,0xb8,0x7c]
+0x7e,0x04,0xb8,0x7c
+
+# W32: v_cmp_gt_u64_e32 vcc_lo, null, v[2:3]     ; encoding: [0x7c,0x04,0xb8,0x7c]
+# W64: v_cmp_gt_u64_e32 vcc, null, v[2:3]        ; encoding: [0x7c,0x04,0xb8,0x7c]
+0x7c,0x04,0xb8,0x7c
+
+# W32: v_cmp_gt_u64_e32 vcc_lo, -1, v[2:3]       ; encoding: [0xc1,0x04,0xb8,0x7c]
+# W64: v_cmp_gt_u64_e32 vcc, -1, v[2:3]          ; encoding: [0xc1,0x04,0xb8,0x7c]
+0xc1,0x04,0xb8,0x7c
+
+# W32: v_cmp_gt_u64_e32 vcc_lo, 0.5, v[2:3]      ; encoding: [0xf0,0x04,0xb8,0x7c]
+# W64: v_cmp_gt_u64_e32 vcc, 0.5, v[2:3]         ; encoding: [0xf0,0x04,0xb8,0x7c]
+0xf0,0x04,0xb8,0x7c
+
+# W32: v_cmp_gt_u64_e32 vcc_lo, src_scc, v[2:3]  ; encoding: [0xfd,0x04,0xb8,0x7c]
+# W64: v_cmp_gt_u64_e32 vcc, src_scc, v[2:3]     ; encoding: [0xfd,0x04,0xb8,0x7c]
+0xfd,0x04,0xb8,0x7c
+
+# W32: v_cmp_gt_u64_e32 vcc_lo, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xb9,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_gt_u64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xb9,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xb9,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_le_f16_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x06,0x7c]
+# W64: v_cmp_le_f16_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x06,0x7c]
+0x01,0x05,0x06,0x7c
+
+# W32: v_cmp_le_f16_e32 vcc_lo, v127, v2         ; encoding: [0x7f,0x05,0x06,0x7c]
+# W64: v_cmp_le_f16_e32 vcc, v127, v2            ; encoding: [0x7f,0x05,0x06,0x7c]
+0x7f,0x05,0x06,0x7c
+
+# W32: v_cmp_le_f16_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x06,0x7c]
+# W64: v_cmp_le_f16_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x06,0x7c]
+0x01,0x04,0x06,0x7c
+
+# W32: v_cmp_le_f16_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x06,0x7c]
+# W64: v_cmp_le_f16_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x06,0x7c]
+0x69,0x04,0x06,0x7c
+
+# W32: v_cmp_le_f16_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x06,0x7c]
+# W64: v_cmp_le_f16_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x06,0x7c]
+0x6a,0x04,0x06,0x7c
+
+# W32: v_cmp_le_f16_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x06,0x7c]
+# W64: v_cmp_le_f16_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x06,0x7c]
+0x6b,0x04,0x06,0x7c
+
+# W32: v_cmp_le_f16_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x06,0x7c]
+# W64: v_cmp_le_f16_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x06,0x7c]
+0x7b,0x04,0x06,0x7c
+
+# W32: v_cmp_le_f16_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x06,0x7c]
+# W64: v_cmp_le_f16_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x06,0x7c]
+0x7d,0x04,0x06,0x7c
+
+# W32: v_cmp_le_f16_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x06,0x7c]
+# W64: v_cmp_le_f16_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x06,0x7c]
+0x7e,0x04,0x06,0x7c
+
+# W32: v_cmp_le_f16_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x06,0x7c]
+# W64: v_cmp_le_f16_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x06,0x7c]
+0x7f,0x04,0x06,0x7c
+
+# W32: v_cmp_le_f16_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x06,0x7c]
+# W64: v_cmp_le_f16_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x06,0x7c]
+0x7c,0x04,0x06,0x7c
+
+# W32: v_cmp_le_f16_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x06,0x7c]
+# W64: v_cmp_le_f16_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x06,0x7c]
+0xc1,0x04,0x06,0x7c
+
+# W32: v_cmp_le_f16_e32 vcc_lo, 0.5, v2          ; encoding: [0xf0,0x04,0x06,0x7c]
+# W64: v_cmp_le_f16_e32 vcc, 0.5, v2             ; encoding: [0xf0,0x04,0x06,0x7c]
+0xf0,0x04,0x06,0x7c
+
+# W32: v_cmp_le_f16_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x06,0x7c]
+# W64: v_cmp_le_f16_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x06,0x7c]
+0xfd,0x04,0x06,0x7c
+
+# W32: v_cmp_le_f16_e32 vcc_lo, 0xfe0b, v127     ; encoding: [0xff,0xfe,0x06,0x7c,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_le_f16_e32 vcc, 0xfe0b, v127        ; encoding: [0xff,0xfe,0x06,0x7c,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x06,0x7c,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_le_f32_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x26,0x7c]
+# W64: v_cmp_le_f32_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x26,0x7c]
+0x01,0x05,0x26,0x7c
+
+# W32: v_cmp_le_f32_e32 vcc_lo, v255, v2         ; encoding: [0xff,0x05,0x26,0x7c]
+# W64: v_cmp_le_f32_e32 vcc, v255, v2            ; encoding: [0xff,0x05,0x26,0x7c]
+0xff,0x05,0x26,0x7c
+
+# W32: v_cmp_le_f32_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x26,0x7c]
+# W64: v_cmp_le_f32_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x26,0x7c]
+0x01,0x04,0x26,0x7c
+
+# W32: v_cmp_le_f32_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x26,0x7c]
+# W64: v_cmp_le_f32_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x26,0x7c]
+0x69,0x04,0x26,0x7c
+
+# W32: v_cmp_le_f32_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x26,0x7c]
+# W64: v_cmp_le_f32_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x26,0x7c]
+0x6a,0x04,0x26,0x7c
+
+# W32: v_cmp_le_f32_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x26,0x7c]
+# W64: v_cmp_le_f32_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x26,0x7c]
+0x6b,0x04,0x26,0x7c
+
+# W32: v_cmp_le_f32_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x26,0x7c]
+# W64: v_cmp_le_f32_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x26,0x7c]
+0x7b,0x04,0x26,0x7c
+
+# W32: v_cmp_le_f32_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x26,0x7c]
+# W64: v_cmp_le_f32_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x26,0x7c]
+0x7d,0x04,0x26,0x7c
+
+# W32: v_cmp_le_f32_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x26,0x7c]
+# W64: v_cmp_le_f32_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x26,0x7c]
+0x7e,0x04,0x26,0x7c
+
+# W32: v_cmp_le_f32_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x26,0x7c]
+# W64: v_cmp_le_f32_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x26,0x7c]
+0x7f,0x04,0x26,0x7c
+
+# W32: v_cmp_le_f32_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x26,0x7c]
+# W64: v_cmp_le_f32_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x26,0x7c]
+0x7c,0x04,0x26,0x7c
+
+# W32: v_cmp_le_f32_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x26,0x7c]
+# W64: v_cmp_le_f32_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x26,0x7c]
+0xc1,0x04,0x26,0x7c
+
+# W32: v_cmp_le_f32_e32 vcc_lo, 0.5, v2          ; encoding: [0xf0,0x04,0x26,0x7c]
+# W64: v_cmp_le_f32_e32 vcc, 0.5, v2             ; encoding: [0xf0,0x04,0x26,0x7c]
+0xf0,0x04,0x26,0x7c
+
+# W32: v_cmp_le_f32_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x26,0x7c]
+# W64: v_cmp_le_f32_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x26,0x7c]
+0xfd,0x04,0x26,0x7c
+
+# W32: v_cmp_le_f32_e32 vcc_lo, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x27,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_le_f32_e32 vcc, 0xaf123456, v255    ; encoding: [0xff,0xfe,0x27,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x27,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_le_f64_e32 vcc_lo, v[1:2], v[2:3]   ; encoding: [0x01,0x05,0x46,0x7c]
+# W64: v_cmp_le_f64_e32 vcc, v[1:2], v[2:3]      ; encoding: [0x01,0x05,0x46,0x7c]
+0x01,0x05,0x46,0x7c
+
+# W32: v_cmp_le_f64_e32 vcc_lo, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x46,0x7c]
+# W64: v_cmp_le_f64_e32 vcc, v[254:255], v[2:3]  ; encoding: [0xfe,0x05,0x46,0x7c]
+0xfe,0x05,0x46,0x7c
+
+# W32: v_cmp_le_f64_e32 vcc_lo, s[2:3], v[2:3]   ; encoding: [0x02,0x04,0x46,0x7c]
+# W64: v_cmp_le_f64_e32 vcc, s[2:3], v[2:3]      ; encoding: [0x02,0x04,0x46,0x7c]
+0x02,0x04,0x46,0x7c
+
+# W32: v_cmp_le_f64_e32 vcc_lo, s[104:105], v[2:3] ; encoding: [0x68,0x04,0x46,0x7c]
+# W64: v_cmp_le_f64_e32 vcc, s[104:105], v[2:3]  ; encoding: [0x68,0x04,0x46,0x7c]
+0x68,0x04,0x46,0x7c
+
+# W32: v_cmp_le_f64_e32 vcc_lo, vcc, v[2:3]      ; encoding: [0x6a,0x04,0x46,0x7c]
+# W64: v_cmp_le_f64_e32 vcc, vcc, v[2:3]         ; encoding: [0x6a,0x04,0x46,0x7c]
+0x6a,0x04,0x46,0x7c
+
+# W32: v_cmp_le_f64_e32 vcc_lo, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x46,0x7c]
+# W64: v_cmp_le_f64_e32 vcc, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x46,0x7c]
+0x7a,0x04,0x46,0x7c
+
+# W32: v_cmp_le_f64_e32 vcc_lo, exec, v[2:3]     ; encoding: [0x7e,0x04,0x46,0x7c]
+# W64: v_cmp_le_f64_e32 vcc, exec, v[2:3]        ; encoding: [0x7e,0x04,0x46,0x7c]
+0x7e,0x04,0x46,0x7c
+
+# W32: v_cmp_le_f64_e32 vcc_lo, null, v[2:3]     ; encoding: [0x7c,0x04,0x46,0x7c]
+# W64: v_cmp_le_f64_e32 vcc, null, v[2:3]        ; encoding: [0x7c,0x04,0x46,0x7c]
+0x7c,0x04,0x46,0x7c
+
+# W32: v_cmp_le_f64_e32 vcc_lo, -1, v[2:3]       ; encoding: [0xc1,0x04,0x46,0x7c]
+# W64: v_cmp_le_f64_e32 vcc, -1, v[2:3]          ; encoding: [0xc1,0x04,0x46,0x7c]
+0xc1,0x04,0x46,0x7c
+
+# W32: v_cmp_le_f64_e32 vcc_lo, 0.5, v[2:3]      ; encoding: [0xf0,0x04,0x46,0x7c]
+# W64: v_cmp_le_f64_e32 vcc, 0.5, v[2:3]         ; encoding: [0xf0,0x04,0x46,0x7c]
+0xf0,0x04,0x46,0x7c
+
+# W32: v_cmp_le_f64_e32 vcc_lo, src_scc, v[2:3]  ; encoding: [0xfd,0x04,0x46,0x7c]
+# W64: v_cmp_le_f64_e32 vcc, src_scc, v[2:3]     ; encoding: [0xfd,0x04,0x46,0x7c]
+0xfd,0x04,0x46,0x7c
+
+# W32: v_cmp_le_f64_e32 vcc_lo, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x47,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_le_f64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x47,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x47,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_le_i16_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x66,0x7c]
+# W64: v_cmp_le_i16_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x66,0x7c]
+0x01,0x05,0x66,0x7c
+
+# W32: v_cmp_le_i16_e32 vcc_lo, v127, v2         ; encoding: [0x7f,0x05,0x66,0x7c]
+# W64: v_cmp_le_i16_e32 vcc, v127, v2            ; encoding: [0x7f,0x05,0x66,0x7c]
+0x7f,0x05,0x66,0x7c
+
+# W32: v_cmp_le_i16_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x66,0x7c]
+# W64: v_cmp_le_i16_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x66,0x7c]
+0x01,0x04,0x66,0x7c
+
+# W32: v_cmp_le_i16_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x66,0x7c]
+# W64: v_cmp_le_i16_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x66,0x7c]
+0x69,0x04,0x66,0x7c
+
+# W32: v_cmp_le_i16_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x66,0x7c]
+# W64: v_cmp_le_i16_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x66,0x7c]
+0x6a,0x04,0x66,0x7c
+
+# W32: v_cmp_le_i16_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x66,0x7c]
+# W64: v_cmp_le_i16_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x66,0x7c]
+0x6b,0x04,0x66,0x7c
+
+# W32: v_cmp_le_i16_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x66,0x7c]
+# W64: v_cmp_le_i16_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x66,0x7c]
+0x7b,0x04,0x66,0x7c
+
+# W32: v_cmp_le_i16_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x66,0x7c]
+# W64: v_cmp_le_i16_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x66,0x7c]
+0x7d,0x04,0x66,0x7c
+
+# W32: v_cmp_le_i16_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x66,0x7c]
+# W64: v_cmp_le_i16_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x66,0x7c]
+0x7e,0x04,0x66,0x7c
+
+# W32: v_cmp_le_i16_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x66,0x7c]
+# W64: v_cmp_le_i16_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x66,0x7c]
+0x7f,0x04,0x66,0x7c
+
+# W32: v_cmp_le_i16_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x66,0x7c]
+# W64: v_cmp_le_i16_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x66,0x7c]
+0x7c,0x04,0x66,0x7c
+
+# W32: v_cmp_le_i16_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x66,0x7c]
+# W64: v_cmp_le_i16_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x66,0x7c]
+0xc1,0x04,0x66,0x7c
+
+# W32: v_cmp_le_i16_e32 vcc_lo, 0x3800, v2
+# W64: v_cmp_le_i16_e32 vcc, 0x3800, v2          ; encoding: [0xff,0x04,0x66,0x7c,0x00,0x38,0x00,0x00]
+0xf0,0x04,0x66,0x7c
+
+# W32: v_cmp_le_i16_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x66,0x7c]
+# W64: v_cmp_le_i16_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x66,0x7c]
+0xfd,0x04,0x66,0x7c
+
+# W32: v_cmp_le_i16_e32 vcc_lo, 0xfe0b, v127     ; encoding: [0xff,0xfe,0x66,0x7c,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_le_i16_e32 vcc, 0xfe0b, v127        ; encoding: [0xff,0xfe,0x66,0x7c,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x66,0x7c,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_le_i32_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x86,0x7c]
+# W64: v_cmp_le_i32_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x86,0x7c]
+0x01,0x05,0x86,0x7c
+
+# W32: v_cmp_le_i32_e32 vcc_lo, v255, v2         ; encoding: [0xff,0x05,0x86,0x7c]
+# W64: v_cmp_le_i32_e32 vcc, v255, v2            ; encoding: [0xff,0x05,0x86,0x7c]
+0xff,0x05,0x86,0x7c
+
+# W32: v_cmp_le_i32_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x86,0x7c]
+# W64: v_cmp_le_i32_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x86,0x7c]
+0x01,0x04,0x86,0x7c
+
+# W32: v_cmp_le_i32_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x86,0x7c]
+# W64: v_cmp_le_i32_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x86,0x7c]
+0x69,0x04,0x86,0x7c
+
+# W32: v_cmp_le_i32_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x86,0x7c]
+# W64: v_cmp_le_i32_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x86,0x7c]
+0x6a,0x04,0x86,0x7c
+
+# W32: v_cmp_le_i32_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x86,0x7c]
+# W64: v_cmp_le_i32_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x86,0x7c]
+0x6b,0x04,0x86,0x7c
+
+# W32: v_cmp_le_i32_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x86,0x7c]
+# W64: v_cmp_le_i32_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x86,0x7c]
+0x7b,0x04,0x86,0x7c
+
+# W32: v_cmp_le_i32_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x86,0x7c]
+# W64: v_cmp_le_i32_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x86,0x7c]
+0x7d,0x04,0x86,0x7c
+
+# W32: v_cmp_le_i32_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x86,0x7c]
+# W64: v_cmp_le_i32_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x86,0x7c]
+0x7e,0x04,0x86,0x7c
+
+# W32: v_cmp_le_i32_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x86,0x7c]
+# W64: v_cmp_le_i32_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x86,0x7c]
+0x7f,0x04,0x86,0x7c
+
+# W32: v_cmp_le_i32_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x86,0x7c]
+# W64: v_cmp_le_i32_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x86,0x7c]
+0x7c,0x04,0x86,0x7c
+
+# W32: v_cmp_le_i32_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x86,0x7c]
+# W64: v_cmp_le_i32_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x86,0x7c]
+0xc1,0x04,0x86,0x7c
+
+# W32: v_cmp_le_i32_e32 vcc_lo, 0.5, v2          ; encoding: [0xf0,0x04,0x86,0x7c]
+# W64: v_cmp_le_i32_e32 vcc, 0.5, v2             ; encoding: [0xf0,0x04,0x86,0x7c]
+0xf0,0x04,0x86,0x7c
+
+# W32: v_cmp_le_i32_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x86,0x7c]
+# W64: v_cmp_le_i32_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x86,0x7c]
+0xfd,0x04,0x86,0x7c
+
+# W32: v_cmp_le_i32_e32 vcc_lo, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x87,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_le_i32_e32 vcc, 0xaf123456, v255    ; encoding: [0xff,0xfe,0x87,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x87,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_le_i64_e32 vcc_lo, v[1:2], v[2:3]   ; encoding: [0x01,0x05,0xa6,0x7c]
+# W64: v_cmp_le_i64_e32 vcc, v[1:2], v[2:3]      ; encoding: [0x01,0x05,0xa6,0x7c]
+0x01,0x05,0xa6,0x7c
+
+# W32: v_cmp_le_i64_e32 vcc_lo, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0xa6,0x7c]
+# W64: v_cmp_le_i64_e32 vcc, v[254:255], v[2:3]  ; encoding: [0xfe,0x05,0xa6,0x7c]
+0xfe,0x05,0xa6,0x7c
+
+# W32: v_cmp_le_i64_e32 vcc_lo, s[2:3], v[2:3]   ; encoding: [0x02,0x04,0xa6,0x7c]
+# W64: v_cmp_le_i64_e32 vcc, s[2:3], v[2:3]      ; encoding: [0x02,0x04,0xa6,0x7c]
+0x02,0x04,0xa6,0x7c
+
+# W32: v_cmp_le_i64_e32 vcc_lo, s[104:105], v[2:3] ; encoding: [0x68,0x04,0xa6,0x7c]
+# W64: v_cmp_le_i64_e32 vcc, s[104:105], v[2:3]  ; encoding: [0x68,0x04,0xa6,0x7c]
+0x68,0x04,0xa6,0x7c
+
+# W32: v_cmp_le_i64_e32 vcc_lo, vcc, v[2:3]      ; encoding: [0x6a,0x04,0xa6,0x7c]
+# W64: v_cmp_le_i64_e32 vcc, vcc, v[2:3]         ; encoding: [0x6a,0x04,0xa6,0x7c]
+0x6a,0x04,0xa6,0x7c
+
+# W32: v_cmp_le_i64_e32 vcc_lo, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0xa6,0x7c]
+# W64: v_cmp_le_i64_e32 vcc, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0xa6,0x7c]
+0x7a,0x04,0xa6,0x7c
+
+# W32: v_cmp_le_i64_e32 vcc_lo, exec, v[2:3]     ; encoding: [0x7e,0x04,0xa6,0x7c]
+# W64: v_cmp_le_i64_e32 vcc, exec, v[2:3]        ; encoding: [0x7e,0x04,0xa6,0x7c]
+0x7e,0x04,0xa6,0x7c
+
+# W32: v_cmp_le_i64_e32 vcc_lo, null, v[2:3]     ; encoding: [0x7c,0x04,0xa6,0x7c]
+# W64: v_cmp_le_i64_e32 vcc, null, v[2:3]        ; encoding: [0x7c,0x04,0xa6,0x7c]
+0x7c,0x04,0xa6,0x7c
+
+# W32: v_cmp_le_i64_e32 vcc_lo, -1, v[2:3]       ; encoding: [0xc1,0x04,0xa6,0x7c]
+# W64: v_cmp_le_i64_e32 vcc, -1, v[2:3]          ; encoding: [0xc1,0x04,0xa6,0x7c]
+0xc1,0x04,0xa6,0x7c
+
+# W32: v_cmp_le_i64_e32 vcc_lo, 0.5, v[2:3]      ; encoding: [0xf0,0x04,0xa6,0x7c]
+# W64: v_cmp_le_i64_e32 vcc, 0.5, v[2:3]         ; encoding: [0xf0,0x04,0xa6,0x7c]
+0xf0,0x04,0xa6,0x7c
+
+# W32: v_cmp_le_i64_e32 vcc_lo, src_scc, v[2:3]  ; encoding: [0xfd,0x04,0xa6,0x7c]
+# W64: v_cmp_le_i64_e32 vcc, src_scc, v[2:3]     ; encoding: [0xfd,0x04,0xa6,0x7c]
+0xfd,0x04,0xa6,0x7c
+
+# W32: v_cmp_le_i64_e32 vcc_lo, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xa7,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_le_i64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xa7,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xa7,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_le_u16_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x76,0x7c]
+# W64: v_cmp_le_u16_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x76,0x7c]
+0x01,0x05,0x76,0x7c
+
+# W32: v_cmp_le_u16_e32 vcc_lo, v127, v2         ; encoding: [0x7f,0x05,0x76,0x7c]
+# W64: v_cmp_le_u16_e32 vcc, v127, v2            ; encoding: [0x7f,0x05,0x76,0x7c]
+0x7f,0x05,0x76,0x7c
+
+# W32: v_cmp_le_u16_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x76,0x7c]
+# W64: v_cmp_le_u16_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x76,0x7c]
+0x01,0x04,0x76,0x7c
+
+# W32: v_cmp_le_u16_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x76,0x7c]
+# W64: v_cmp_le_u16_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x76,0x7c]
+0x69,0x04,0x76,0x7c
+
+# W32: v_cmp_le_u16_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x76,0x7c]
+# W64: v_cmp_le_u16_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x76,0x7c]
+0x6a,0x04,0x76,0x7c
+
+# W32: v_cmp_le_u16_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x76,0x7c]
+# W64: v_cmp_le_u16_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x76,0x7c]
+0x6b,0x04,0x76,0x7c
+
+# W32: v_cmp_le_u16_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x76,0x7c]
+# W64: v_cmp_le_u16_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x76,0x7c]
+0x7b,0x04,0x76,0x7c
+
+# W32: v_cmp_le_u16_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x76,0x7c]
+# W64: v_cmp_le_u16_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x76,0x7c]
+0x7d,0x04,0x76,0x7c
+
+# W32: v_cmp_le_u16_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x76,0x7c]
+# W64: v_cmp_le_u16_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x76,0x7c]
+0x7e,0x04,0x76,0x7c
+
+# W32: v_cmp_le_u16_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x76,0x7c]
+# W64: v_cmp_le_u16_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x76,0x7c]
+0x7f,0x04,0x76,0x7c
+
+# W32: v_cmp_le_u16_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x76,0x7c]
+# W64: v_cmp_le_u16_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x76,0x7c]
+0x7c,0x04,0x76,0x7c
+
+# W32: v_cmp_le_u16_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x76,0x7c]
+# W64: v_cmp_le_u16_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x76,0x7c]
+0xc1,0x04,0x76,0x7c
+
+# W32: v_cmp_le_u16_e32 vcc_lo, 0x3800, v2
+# W64: v_cmp_le_u16_e32 vcc, 0x3800, v2          ; encoding: [0xff,0x04,0x76,0x7c,0x00,0x38,0x00,0x00]
+0xf0,0x04,0x76,0x7c
+
+# W32: v_cmp_le_u16_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x76,0x7c]
+# W64: v_cmp_le_u16_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x76,0x7c]
+0xfd,0x04,0x76,0x7c
+
+# W32: v_cmp_le_u16_e32 vcc_lo, 0xfe0b, v127     ; encoding: [0xff,0xfe,0x76,0x7c,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_le_u16_e32 vcc, 0xfe0b, v127        ; encoding: [0xff,0xfe,0x76,0x7c,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x76,0x7c,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_le_u32_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x96,0x7c]
+# W64: v_cmp_le_u32_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x96,0x7c]
+0x01,0x05,0x96,0x7c
+
+# W32: v_cmp_le_u32_e32 vcc_lo, v255, v2         ; encoding: [0xff,0x05,0x96,0x7c]
+# W64: v_cmp_le_u32_e32 vcc, v255, v2            ; encoding: [0xff,0x05,0x96,0x7c]
+0xff,0x05,0x96,0x7c
+
+# W32: v_cmp_le_u32_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x96,0x7c]
+# W64: v_cmp_le_u32_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x96,0x7c]
+0x01,0x04,0x96,0x7c
+
+# W32: v_cmp_le_u32_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x96,0x7c]
+# W64: v_cmp_le_u32_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x96,0x7c]
+0x69,0x04,0x96,0x7c
+
+# W32: v_cmp_le_u32_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x96,0x7c]
+# W64: v_cmp_le_u32_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x96,0x7c]
+0x6a,0x04,0x96,0x7c
+
+# W32: v_cmp_le_u32_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x96,0x7c]
+# W64: v_cmp_le_u32_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x96,0x7c]
+0x6b,0x04,0x96,0x7c
+
+# W32: v_cmp_le_u32_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x96,0x7c]
+# W64: v_cmp_le_u32_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x96,0x7c]
+0x7b,0x04,0x96,0x7c
+
+# W32: v_cmp_le_u32_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x96,0x7c]
+# W64: v_cmp_le_u32_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x96,0x7c]
+0x7d,0x04,0x96,0x7c
+
+# W32: v_cmp_le_u32_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x96,0x7c]
+# W64: v_cmp_le_u32_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x96,0x7c]
+0x7e,0x04,0x96,0x7c
+
+# W32: v_cmp_le_u32_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x96,0x7c]
+# W64: v_cmp_le_u32_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x96,0x7c]
+0x7f,0x04,0x96,0x7c
+
+# W32: v_cmp_le_u32_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x96,0x7c]
+# W64: v_cmp_le_u32_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x96,0x7c]
+0x7c,0x04,0x96,0x7c
+
+# W32: v_cmp_le_u32_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x96,0x7c]
+# W64: v_cmp_le_u32_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x96,0x7c]
+0xc1,0x04,0x96,0x7c
+
+# W32: v_cmp_le_u32_e32 vcc_lo, 0.5, v2          ; encoding: [0xf0,0x04,0x96,0x7c]
+# W64: v_cmp_le_u32_e32 vcc, 0.5, v2             ; encoding: [0xf0,0x04,0x96,0x7c]
+0xf0,0x04,0x96,0x7c
+
+# W32: v_cmp_le_u32_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x96,0x7c]
+# W64: v_cmp_le_u32_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x96,0x7c]
+0xfd,0x04,0x96,0x7c
+
+# W32: v_cmp_le_u32_e32 vcc_lo, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x97,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_le_u32_e32 vcc, 0xaf123456, v255    ; encoding: [0xff,0xfe,0x97,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x97,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_le_u64_e32 vcc_lo, v[1:2], v[2:3]   ; encoding: [0x01,0x05,0xb6,0x7c]
+# W64: v_cmp_le_u64_e32 vcc, v[1:2], v[2:3]      ; encoding: [0x01,0x05,0xb6,0x7c]
+0x01,0x05,0xb6,0x7c
+
+# W32: v_cmp_le_u64_e32 vcc_lo, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0xb6,0x7c]
+# W64: v_cmp_le_u64_e32 vcc, v[254:255], v[2:3]  ; encoding: [0xfe,0x05,0xb6,0x7c]
+0xfe,0x05,0xb6,0x7c
+
+# W32: v_cmp_le_u64_e32 vcc_lo, s[2:3], v[2:3]   ; encoding: [0x02,0x04,0xb6,0x7c]
+# W64: v_cmp_le_u64_e32 vcc, s[2:3], v[2:3]      ; encoding: [0x02,0x04,0xb6,0x7c]
+0x02,0x04,0xb6,0x7c
+
+# W32: v_cmp_le_u64_e32 vcc_lo, s[104:105], v[2:3] ; encoding: [0x68,0x04,0xb6,0x7c]
+# W64: v_cmp_le_u64_e32 vcc, s[104:105], v[2:3]  ; encoding: [0x68,0x04,0xb6,0x7c]
+0x68,0x04,0xb6,0x7c
+
+# W32: v_cmp_le_u64_e32 vcc_lo, vcc, v[2:3]      ; encoding: [0x6a,0x04,0xb6,0x7c]
+# W64: v_cmp_le_u64_e32 vcc, vcc, v[2:3]         ; encoding: [0x6a,0x04,0xb6,0x7c]
+0x6a,0x04,0xb6,0x7c
+
+# W32: v_cmp_le_u64_e32 vcc_lo, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0xb6,0x7c]
+# W64: v_cmp_le_u64_e32 vcc, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0xb6,0x7c]
+0x7a,0x04,0xb6,0x7c
+
+# W32: v_cmp_le_u64_e32 vcc_lo, exec, v[2:3]     ; encoding: [0x7e,0x04,0xb6,0x7c]
+# W64: v_cmp_le_u64_e32 vcc, exec, v[2:3]        ; encoding: [0x7e,0x04,0xb6,0x7c]
+0x7e,0x04,0xb6,0x7c
+
+# W32: v_cmp_le_u64_e32 vcc_lo, null, v[2:3]     ; encoding: [0x7c,0x04,0xb6,0x7c]
+# W64: v_cmp_le_u64_e32 vcc, null, v[2:3]        ; encoding: [0x7c,0x04,0xb6,0x7c]
+0x7c,0x04,0xb6,0x7c
+
+# W32: v_cmp_le_u64_e32 vcc_lo, -1, v[2:3]       ; encoding: [0xc1,0x04,0xb6,0x7c]
+# W64: v_cmp_le_u64_e32 vcc, -1, v[2:3]          ; encoding: [0xc1,0x04,0xb6,0x7c]
+0xc1,0x04,0xb6,0x7c
+
+# W32: v_cmp_le_u64_e32 vcc_lo, 0.5, v[2:3]      ; encoding: [0xf0,0x04,0xb6,0x7c]
+# W64: v_cmp_le_u64_e32 vcc, 0.5, v[2:3]         ; encoding: [0xf0,0x04,0xb6,0x7c]
+0xf0,0x04,0xb6,0x7c
+
+# W32: v_cmp_le_u64_e32 vcc_lo, src_scc, v[2:3]  ; encoding: [0xfd,0x04,0xb6,0x7c]
+# W64: v_cmp_le_u64_e32 vcc, src_scc, v[2:3]     ; encoding: [0xfd,0x04,0xb6,0x7c]
+0xfd,0x04,0xb6,0x7c
+
+# W32: v_cmp_le_u64_e32 vcc_lo, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xb7,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_le_u64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xb7,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xb7,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_lg_f16_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x0a,0x7c]
+# W64: v_cmp_lg_f16_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x0a,0x7c]
+0x01,0x05,0x0a,0x7c
+
+# W32: v_cmp_lg_f16_e32 vcc_lo, v127, v2         ; encoding: [0x7f,0x05,0x0a,0x7c]
+# W64: v_cmp_lg_f16_e32 vcc, v127, v2            ; encoding: [0x7f,0x05,0x0a,0x7c]
+0x7f,0x05,0x0a,0x7c
+
+# W32: v_cmp_lg_f16_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x0a,0x7c]
+# W64: v_cmp_lg_f16_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x0a,0x7c]
+0x01,0x04,0x0a,0x7c
+
+# W32: v_cmp_lg_f16_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x0a,0x7c]
+# W64: v_cmp_lg_f16_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x0a,0x7c]
+0x69,0x04,0x0a,0x7c
+
+# W32: v_cmp_lg_f16_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x0a,0x7c]
+# W64: v_cmp_lg_f16_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x0a,0x7c]
+0x6a,0x04,0x0a,0x7c
+
+# W32: v_cmp_lg_f16_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x0a,0x7c]
+# W64: v_cmp_lg_f16_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x0a,0x7c]
+0x6b,0x04,0x0a,0x7c
+
+# W32: v_cmp_lg_f16_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x0a,0x7c]
+# W64: v_cmp_lg_f16_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x0a,0x7c]
+0x7b,0x04,0x0a,0x7c
+
+# W32: v_cmp_lg_f16_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x0a,0x7c]
+# W64: v_cmp_lg_f16_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x0a,0x7c]
+0x7d,0x04,0x0a,0x7c
+
+# W32: v_cmp_lg_f16_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x0a,0x7c]
+# W64: v_cmp_lg_f16_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x0a,0x7c]
+0x7e,0x04,0x0a,0x7c
+
+# W32: v_cmp_lg_f16_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x0a,0x7c]
+# W64: v_cmp_lg_f16_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x0a,0x7c]
+0x7f,0x04,0x0a,0x7c
+
+# W32: v_cmp_lg_f16_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x0a,0x7c]
+# W64: v_cmp_lg_f16_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x0a,0x7c]
+0x7c,0x04,0x0a,0x7c
+
+# W32: v_cmp_lg_f16_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x0a,0x7c]
+# W64: v_cmp_lg_f16_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x0a,0x7c]
+0xc1,0x04,0x0a,0x7c
+
+# W32: v_cmp_lg_f16_e32 vcc_lo, 0.5, v2          ; encoding: [0xf0,0x04,0x0a,0x7c]
+# W64: v_cmp_lg_f16_e32 vcc, 0.5, v2             ; encoding: [0xf0,0x04,0x0a,0x7c]
+0xf0,0x04,0x0a,0x7c
+
+# W32: v_cmp_lg_f16_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x0a,0x7c]
+# W64: v_cmp_lg_f16_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x0a,0x7c]
+0xfd,0x04,0x0a,0x7c
+
+# W32: v_cmp_lg_f16_e32 vcc_lo, 0xfe0b, v127     ; encoding: [0xff,0xfe,0x0a,0x7c,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_lg_f16_e32 vcc, 0xfe0b, v127        ; encoding: [0xff,0xfe,0x0a,0x7c,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x0a,0x7c,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_lg_f32_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x2a,0x7c]
+# W64: v_cmp_lg_f32_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x2a,0x7c]
+0x01,0x05,0x2a,0x7c
+
+# W32: v_cmp_lg_f32_e32 vcc_lo, v255, v2         ; encoding: [0xff,0x05,0x2a,0x7c]
+# W64: v_cmp_lg_f32_e32 vcc, v255, v2            ; encoding: [0xff,0x05,0x2a,0x7c]
+0xff,0x05,0x2a,0x7c
+
+# W32: v_cmp_lg_f32_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x2a,0x7c]
+# W64: v_cmp_lg_f32_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x2a,0x7c]
+0x01,0x04,0x2a,0x7c
+
+# W32: v_cmp_lg_f32_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x2a,0x7c]
+# W64: v_cmp_lg_f32_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x2a,0x7c]
+0x69,0x04,0x2a,0x7c
+
+# W32: v_cmp_lg_f32_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x2a,0x7c]
+# W64: v_cmp_lg_f32_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x2a,0x7c]
+0x6a,0x04,0x2a,0x7c
+
+# W32: v_cmp_lg_f32_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x2a,0x7c]
+# W64: v_cmp_lg_f32_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x2a,0x7c]
+0x6b,0x04,0x2a,0x7c
+
+# W32: v_cmp_lg_f32_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x2a,0x7c]
+# W64: v_cmp_lg_f32_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x2a,0x7c]
+0x7b,0x04,0x2a,0x7c
+
+# W32: v_cmp_lg_f32_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x2a,0x7c]
+# W64: v_cmp_lg_f32_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x2a,0x7c]
+0x7d,0x04,0x2a,0x7c
+
+# W32: v_cmp_lg_f32_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x2a,0x7c]
+# W64: v_cmp_lg_f32_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x2a,0x7c]
+0x7e,0x04,0x2a,0x7c
+
+# W32: v_cmp_lg_f32_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x2a,0x7c]
+# W64: v_cmp_lg_f32_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x2a,0x7c]
+0x7f,0x04,0x2a,0x7c
+
+# W32: v_cmp_lg_f32_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x2a,0x7c]
+# W64: v_cmp_lg_f32_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x2a,0x7c]
+0x7c,0x04,0x2a,0x7c
+
+# W32: v_cmp_lg_f32_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x2a,0x7c]
+# W64: v_cmp_lg_f32_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x2a,0x7c]
+0xc1,0x04,0x2a,0x7c
+
+# W32: v_cmp_lg_f32_e32 vcc_lo, 0.5, v2          ; encoding: [0xf0,0x04,0x2a,0x7c]
+# W64: v_cmp_lg_f32_e32 vcc, 0.5, v2             ; encoding: [0xf0,0x04,0x2a,0x7c]
+0xf0,0x04,0x2a,0x7c
+
+# W32: v_cmp_lg_f32_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x2a,0x7c]
+# W64: v_cmp_lg_f32_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x2a,0x7c]
+0xfd,0x04,0x2a,0x7c
+
+# W32: v_cmp_lg_f32_e32 vcc_lo, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x2b,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_lg_f32_e32 vcc, 0xaf123456, v255    ; encoding: [0xff,0xfe,0x2b,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x2b,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_lg_f64_e32 vcc_lo, v[1:2], v[2:3]   ; encoding: [0x01,0x05,0x4a,0x7c]
+# W64: v_cmp_lg_f64_e32 vcc, v[1:2], v[2:3]      ; encoding: [0x01,0x05,0x4a,0x7c]
+0x01,0x05,0x4a,0x7c
+
+# W32: v_cmp_lg_f64_e32 vcc_lo, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x4a,0x7c]
+# W64: v_cmp_lg_f64_e32 vcc, v[254:255], v[2:3]  ; encoding: [0xfe,0x05,0x4a,0x7c]
+0xfe,0x05,0x4a,0x7c
+
+# W32: v_cmp_lg_f64_e32 vcc_lo, s[2:3], v[2:3]   ; encoding: [0x02,0x04,0x4a,0x7c]
+# W64: v_cmp_lg_f64_e32 vcc, s[2:3], v[2:3]      ; encoding: [0x02,0x04,0x4a,0x7c]
+0x02,0x04,0x4a,0x7c
+
+# W32: v_cmp_lg_f64_e32 vcc_lo, s[104:105], v[2:3] ; encoding: [0x68,0x04,0x4a,0x7c]
+# W64: v_cmp_lg_f64_e32 vcc, s[104:105], v[2:3]  ; encoding: [0x68,0x04,0x4a,0x7c]
+0x68,0x04,0x4a,0x7c
+
+# W32: v_cmp_lg_f64_e32 vcc_lo, vcc, v[2:3]      ; encoding: [0x6a,0x04,0x4a,0x7c]
+# W64: v_cmp_lg_f64_e32 vcc, vcc, v[2:3]         ; encoding: [0x6a,0x04,0x4a,0x7c]
+0x6a,0x04,0x4a,0x7c
+
+# W32: v_cmp_lg_f64_e32 vcc_lo, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x4a,0x7c]
+# W64: v_cmp_lg_f64_e32 vcc, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x4a,0x7c]
+0x7a,0x04,0x4a,0x7c
+
+# W32: v_cmp_lg_f64_e32 vcc_lo, exec, v[2:3]     ; encoding: [0x7e,0x04,0x4a,0x7c]
+# W64: v_cmp_lg_f64_e32 vcc, exec, v[2:3]        ; encoding: [0x7e,0x04,0x4a,0x7c]
+0x7e,0x04,0x4a,0x7c
+
+# W32: v_cmp_lg_f64_e32 vcc_lo, null, v[2:3]     ; encoding: [0x7c,0x04,0x4a,0x7c]
+# W64: v_cmp_lg_f64_e32 vcc, null, v[2:3]        ; encoding: [0x7c,0x04,0x4a,0x7c]
+0x7c,0x04,0x4a,0x7c
+
+# W32: v_cmp_lg_f64_e32 vcc_lo, -1, v[2:3]       ; encoding: [0xc1,0x04,0x4a,0x7c]
+# W64: v_cmp_lg_f64_e32 vcc, -1, v[2:3]          ; encoding: [0xc1,0x04,0x4a,0x7c]
+0xc1,0x04,0x4a,0x7c
+
+# W32: v_cmp_lg_f64_e32 vcc_lo, 0.5, v[2:3]      ; encoding: [0xf0,0x04,0x4a,0x7c]
+# W64: v_cmp_lg_f64_e32 vcc, 0.5, v[2:3]         ; encoding: [0xf0,0x04,0x4a,0x7c]
+0xf0,0x04,0x4a,0x7c
+
+# W32: v_cmp_lg_f64_e32 vcc_lo, src_scc, v[2:3]  ; encoding: [0xfd,0x04,0x4a,0x7c]
+# W64: v_cmp_lg_f64_e32 vcc, src_scc, v[2:3]     ; encoding: [0xfd,0x04,0x4a,0x7c]
+0xfd,0x04,0x4a,0x7c
+
+# W32: v_cmp_lg_f64_e32 vcc_lo, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x4b,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_lg_f64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x4b,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x4b,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_lt_f16_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x02,0x7c]
+# W64: v_cmp_lt_f16_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x02,0x7c]
+0x01,0x05,0x02,0x7c
+
+# W32: v_cmp_lt_f16_e32 vcc_lo, v127, v2         ; encoding: [0x7f,0x05,0x02,0x7c]
+# W64: v_cmp_lt_f16_e32 vcc, v127, v2            ; encoding: [0x7f,0x05,0x02,0x7c]
+0x7f,0x05,0x02,0x7c
+
+# W32: v_cmp_lt_f16_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x02,0x7c]
+# W64: v_cmp_lt_f16_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x02,0x7c]
+0x01,0x04,0x02,0x7c
+
+# W32: v_cmp_lt_f16_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x02,0x7c]
+# W64: v_cmp_lt_f16_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x02,0x7c]
+0x69,0x04,0x02,0x7c
+
+# W32: v_cmp_lt_f16_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x02,0x7c]
+# W64: v_cmp_lt_f16_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x02,0x7c]
+0x6a,0x04,0x02,0x7c
+
+# W32: v_cmp_lt_f16_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x02,0x7c]
+# W64: v_cmp_lt_f16_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x02,0x7c]
+0x6b,0x04,0x02,0x7c
+
+# W32: v_cmp_lt_f16_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x02,0x7c]
+# W64: v_cmp_lt_f16_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x02,0x7c]
+0x7b,0x04,0x02,0x7c
+
+# W32: v_cmp_lt_f16_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x02,0x7c]
+# W64: v_cmp_lt_f16_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x02,0x7c]
+0x7d,0x04,0x02,0x7c
+
+# W32: v_cmp_lt_f16_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x02,0x7c]
+# W64: v_cmp_lt_f16_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x02,0x7c]
+0x7e,0x04,0x02,0x7c
+
+# W32: v_cmp_lt_f16_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x02,0x7c]
+# W64: v_cmp_lt_f16_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x02,0x7c]
+0x7f,0x04,0x02,0x7c
+
+# W32: v_cmp_lt_f16_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x02,0x7c]
+# W64: v_cmp_lt_f16_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x02,0x7c]
+0x7c,0x04,0x02,0x7c
+
+# W32: v_cmp_lt_f16_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x02,0x7c]
+# W64: v_cmp_lt_f16_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x02,0x7c]
+0xc1,0x04,0x02,0x7c
+
+# W32: v_cmp_lt_f16_e32 vcc_lo, 0.5, v2          ; encoding: [0xf0,0x04,0x02,0x7c]
+# W64: v_cmp_lt_f16_e32 vcc, 0.5, v2             ; encoding: [0xf0,0x04,0x02,0x7c]
+0xf0,0x04,0x02,0x7c
+
+# W32: v_cmp_lt_f16_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x02,0x7c]
+# W64: v_cmp_lt_f16_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x02,0x7c]
+0xfd,0x04,0x02,0x7c
+
+# W32: v_cmp_lt_f16_e32 vcc_lo, 0xfe0b, v127     ; encoding: [0xff,0xfe,0x02,0x7c,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_lt_f16_e32 vcc, 0xfe0b, v127        ; encoding: [0xff,0xfe,0x02,0x7c,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x02,0x7c,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_lt_f32_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x22,0x7c]
+# W64: v_cmp_lt_f32_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x22,0x7c]
+0x01,0x05,0x22,0x7c
+
+# W32: v_cmp_lt_f32_e32 vcc_lo, v255, v2         ; encoding: [0xff,0x05,0x22,0x7c]
+# W64: v_cmp_lt_f32_e32 vcc, v255, v2            ; encoding: [0xff,0x05,0x22,0x7c]
+0xff,0x05,0x22,0x7c
+
+# W32: v_cmp_lt_f32_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x22,0x7c]
+# W64: v_cmp_lt_f32_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x22,0x7c]
+0x01,0x04,0x22,0x7c
+
+# W32: v_cmp_lt_f32_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x22,0x7c]
+# W64: v_cmp_lt_f32_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x22,0x7c]
+0x69,0x04,0x22,0x7c
+
+# W32: v_cmp_lt_f32_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x22,0x7c]
+# W64: v_cmp_lt_f32_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x22,0x7c]
+0x6a,0x04,0x22,0x7c
+
+# W32: v_cmp_lt_f32_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x22,0x7c]
+# W64: v_cmp_lt_f32_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x22,0x7c]
+0x6b,0x04,0x22,0x7c
+
+# W32: v_cmp_lt_f32_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x22,0x7c]
+# W64: v_cmp_lt_f32_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x22,0x7c]
+0x7b,0x04,0x22,0x7c
+
+# W32: v_cmp_lt_f32_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x22,0x7c]
+# W64: v_cmp_lt_f32_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x22,0x7c]
+0x7d,0x04,0x22,0x7c
+
+# W32: v_cmp_lt_f32_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x22,0x7c]
+# W64: v_cmp_lt_f32_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x22,0x7c]
+0x7e,0x04,0x22,0x7c
+
+# W32: v_cmp_lt_f32_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x22,0x7c]
+# W64: v_cmp_lt_f32_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x22,0x7c]
+0x7f,0x04,0x22,0x7c
+
+# W32: v_cmp_lt_f32_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x22,0x7c]
+# W64: v_cmp_lt_f32_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x22,0x7c]
+0x7c,0x04,0x22,0x7c
+
+# W32: v_cmp_lt_f32_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x22,0x7c]
+# W64: v_cmp_lt_f32_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x22,0x7c]
+0xc1,0x04,0x22,0x7c
+
+# W32: v_cmp_lt_f32_e32 vcc_lo, 0.5, v2          ; encoding: [0xf0,0x04,0x22,0x7c]
+# W64: v_cmp_lt_f32_e32 vcc, 0.5, v2             ; encoding: [0xf0,0x04,0x22,0x7c]
+0xf0,0x04,0x22,0x7c
+
+# W32: v_cmp_lt_f32_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x22,0x7c]
+# W64: v_cmp_lt_f32_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x22,0x7c]
+0xfd,0x04,0x22,0x7c
+
+# W32: v_cmp_lt_f32_e32 vcc_lo, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x23,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_lt_f32_e32 vcc, 0xaf123456, v255    ; encoding: [0xff,0xfe,0x23,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x23,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_lt_f64_e32 vcc_lo, v[1:2], v[2:3]   ; encoding: [0x01,0x05,0x42,0x7c]
+# W64: v_cmp_lt_f64_e32 vcc, v[1:2], v[2:3]      ; encoding: [0x01,0x05,0x42,0x7c]
+0x01,0x05,0x42,0x7c
+
+# W32: v_cmp_lt_f64_e32 vcc_lo, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x42,0x7c]
+# W64: v_cmp_lt_f64_e32 vcc, v[254:255], v[2:3]  ; encoding: [0xfe,0x05,0x42,0x7c]
+0xfe,0x05,0x42,0x7c
+
+# W32: v_cmp_lt_f64_e32 vcc_lo, s[2:3], v[2:3]   ; encoding: [0x02,0x04,0x42,0x7c]
+# W64: v_cmp_lt_f64_e32 vcc, s[2:3], v[2:3]      ; encoding: [0x02,0x04,0x42,0x7c]
+0x02,0x04,0x42,0x7c
+
+# W32: v_cmp_lt_f64_e32 vcc_lo, s[104:105], v[2:3] ; encoding: [0x68,0x04,0x42,0x7c]
+# W64: v_cmp_lt_f64_e32 vcc, s[104:105], v[2:3]  ; encoding: [0x68,0x04,0x42,0x7c]
+0x68,0x04,0x42,0x7c
+
+# W32: v_cmp_lt_f64_e32 vcc_lo, vcc, v[2:3]      ; encoding: [0x6a,0x04,0x42,0x7c]
+# W64: v_cmp_lt_f64_e32 vcc, vcc, v[2:3]         ; encoding: [0x6a,0x04,0x42,0x7c]
+0x6a,0x04,0x42,0x7c
+
+# W32: v_cmp_lt_f64_e32 vcc_lo, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x42,0x7c]
+# W64: v_cmp_lt_f64_e32 vcc, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x42,0x7c]
+0x7a,0x04,0x42,0x7c
+
+# W32: v_cmp_lt_f64_e32 vcc_lo, exec, v[2:3]     ; encoding: [0x7e,0x04,0x42,0x7c]
+# W64: v_cmp_lt_f64_e32 vcc, exec, v[2:3]        ; encoding: [0x7e,0x04,0x42,0x7c]
+0x7e,0x04,0x42,0x7c
+
+# W32: v_cmp_lt_f64_e32 vcc_lo, null, v[2:3]     ; encoding: [0x7c,0x04,0x42,0x7c]
+# W64: v_cmp_lt_f64_e32 vcc, null, v[2:3]        ; encoding: [0x7c,0x04,0x42,0x7c]
+0x7c,0x04,0x42,0x7c
+
+# W32: v_cmp_lt_f64_e32 vcc_lo, -1, v[2:3]       ; encoding: [0xc1,0x04,0x42,0x7c]
+# W64: v_cmp_lt_f64_e32 vcc, -1, v[2:3]          ; encoding: [0xc1,0x04,0x42,0x7c]
+0xc1,0x04,0x42,0x7c
+
+# W32: v_cmp_lt_f64_e32 vcc_lo, 0.5, v[2:3]      ; encoding: [0xf0,0x04,0x42,0x7c]
+# W64: v_cmp_lt_f64_e32 vcc, 0.5, v[2:3]         ; encoding: [0xf0,0x04,0x42,0x7c]
+0xf0,0x04,0x42,0x7c
+
+# W32: v_cmp_lt_f64_e32 vcc_lo, src_scc, v[2:3]  ; encoding: [0xfd,0x04,0x42,0x7c]
+# W64: v_cmp_lt_f64_e32 vcc, src_scc, v[2:3]     ; encoding: [0xfd,0x04,0x42,0x7c]
+0xfd,0x04,0x42,0x7c
+
+# W32: v_cmp_lt_f64_e32 vcc_lo, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x43,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_lt_f64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x43,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x43,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_lt_i16_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x62,0x7c]
+# W64: v_cmp_lt_i16_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x62,0x7c]
+0x01,0x05,0x62,0x7c
+
+# W32: v_cmp_lt_i16_e32 vcc_lo, v127, v2         ; encoding: [0x7f,0x05,0x62,0x7c]
+# W64: v_cmp_lt_i16_e32 vcc, v127, v2            ; encoding: [0x7f,0x05,0x62,0x7c]
+0x7f,0x05,0x62,0x7c
+
+# W32: v_cmp_lt_i16_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x62,0x7c]
+# W64: v_cmp_lt_i16_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x62,0x7c]
+0x01,0x04,0x62,0x7c
+
+# W32: v_cmp_lt_i16_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x62,0x7c]
+# W64: v_cmp_lt_i16_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x62,0x7c]
+0x69,0x04,0x62,0x7c
+
+# W32: v_cmp_lt_i16_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x62,0x7c]
+# W64: v_cmp_lt_i16_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x62,0x7c]
+0x6a,0x04,0x62,0x7c
+
+# W32: v_cmp_lt_i16_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x62,0x7c]
+# W64: v_cmp_lt_i16_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x62,0x7c]
+0x6b,0x04,0x62,0x7c
+
+# W32: v_cmp_lt_i16_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x62,0x7c]
+# W64: v_cmp_lt_i16_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x62,0x7c]
+0x7b,0x04,0x62,0x7c
+
+# W32: v_cmp_lt_i16_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x62,0x7c]
+# W64: v_cmp_lt_i16_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x62,0x7c]
+0x7d,0x04,0x62,0x7c
+
+# W32: v_cmp_lt_i16_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x62,0x7c]
+# W64: v_cmp_lt_i16_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x62,0x7c]
+0x7e,0x04,0x62,0x7c
+
+# W32: v_cmp_lt_i16_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x62,0x7c]
+# W64: v_cmp_lt_i16_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x62,0x7c]
+0x7f,0x04,0x62,0x7c
+
+# W32: v_cmp_lt_i16_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x62,0x7c]
+# W64: v_cmp_lt_i16_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x62,0x7c]
+0x7c,0x04,0x62,0x7c
+
+# W32: v_cmp_lt_i16_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x62,0x7c]
+# W64: v_cmp_lt_i16_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x62,0x7c]
+0xc1,0x04,0x62,0x7c
+
+# W32: v_cmp_lt_i16_e32 vcc_lo, 0x3800, v2
+# W64: v_cmp_lt_i16_e32 vcc, 0x3800, v2          ; encoding: [0xff,0x04,0x62,0x7c,0x00,0x38,0x00,0x00]
+0xf0,0x04,0x62,0x7c
+
+# W32: v_cmp_lt_i16_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x62,0x7c]
+# W64: v_cmp_lt_i16_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x62,0x7c]
+0xfd,0x04,0x62,0x7c
+
+# W32: v_cmp_lt_i16_e32 vcc_lo, 0xfe0b, v127     ; encoding: [0xff,0xfe,0x62,0x7c,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_lt_i16_e32 vcc, 0xfe0b, v127        ; encoding: [0xff,0xfe,0x62,0x7c,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x62,0x7c,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_lt_i32_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x82,0x7c]
+# W64: v_cmp_lt_i32_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x82,0x7c]
+0x01,0x05,0x82,0x7c
+
+# W32: v_cmp_lt_i32_e32 vcc_lo, v255, v2         ; encoding: [0xff,0x05,0x82,0x7c]
+# W64: v_cmp_lt_i32_e32 vcc, v255, v2            ; encoding: [0xff,0x05,0x82,0x7c]
+0xff,0x05,0x82,0x7c
+
+# W32: v_cmp_lt_i32_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x82,0x7c]
+# W64: v_cmp_lt_i32_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x82,0x7c]
+0x01,0x04,0x82,0x7c
+
+# W32: v_cmp_lt_i32_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x82,0x7c]
+# W64: v_cmp_lt_i32_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x82,0x7c]
+0x69,0x04,0x82,0x7c
+
+# W32: v_cmp_lt_i32_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x82,0x7c]
+# W64: v_cmp_lt_i32_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x82,0x7c]
+0x6a,0x04,0x82,0x7c
+
+# W32: v_cmp_lt_i32_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x82,0x7c]
+# W64: v_cmp_lt_i32_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x82,0x7c]
+0x6b,0x04,0x82,0x7c
+
+# W32: v_cmp_lt_i32_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x82,0x7c]
+# W64: v_cmp_lt_i32_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x82,0x7c]
+0x7b,0x04,0x82,0x7c
+
+# W32: v_cmp_lt_i32_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x82,0x7c]
+# W64: v_cmp_lt_i32_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x82,0x7c]
+0x7d,0x04,0x82,0x7c
+
+# W32: v_cmp_lt_i32_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x82,0x7c]
+# W64: v_cmp_lt_i32_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x82,0x7c]
+0x7e,0x04,0x82,0x7c
+
+# W32: v_cmp_lt_i32_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x82,0x7c]
+# W64: v_cmp_lt_i32_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x82,0x7c]
+0x7f,0x04,0x82,0x7c
+
+# W32: v_cmp_lt_i32_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x82,0x7c]
+# W64: v_cmp_lt_i32_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x82,0x7c]
+0x7c,0x04,0x82,0x7c
+
+# W32: v_cmp_lt_i32_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x82,0x7c]
+# W64: v_cmp_lt_i32_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x82,0x7c]
+0xc1,0x04,0x82,0x7c
+
+# W32: v_cmp_lt_i32_e32 vcc_lo, 0.5, v2          ; encoding: [0xf0,0x04,0x82,0x7c]
+# W64: v_cmp_lt_i32_e32 vcc, 0.5, v2             ; encoding: [0xf0,0x04,0x82,0x7c]
+0xf0,0x04,0x82,0x7c
+
+# W32: v_cmp_lt_i32_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x82,0x7c]
+# W64: v_cmp_lt_i32_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x82,0x7c]
+0xfd,0x04,0x82,0x7c
+
+# W32: v_cmp_lt_i32_e32 vcc_lo, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x83,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_lt_i32_e32 vcc, 0xaf123456, v255    ; encoding: [0xff,0xfe,0x83,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x83,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_lt_i64_e32 vcc_lo, v[1:2], v[2:3]   ; encoding: [0x01,0x05,0xa2,0x7c]
+# W64: v_cmp_lt_i64_e32 vcc, v[1:2], v[2:3]      ; encoding: [0x01,0x05,0xa2,0x7c]
+0x01,0x05,0xa2,0x7c
+
+# W32: v_cmp_lt_i64_e32 vcc_lo, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0xa2,0x7c]
+# W64: v_cmp_lt_i64_e32 vcc, v[254:255], v[2:3]  ; encoding: [0xfe,0x05,0xa2,0x7c]
+0xfe,0x05,0xa2,0x7c
+
+# W32: v_cmp_lt_i64_e32 vcc_lo, s[2:3], v[2:3]   ; encoding: [0x02,0x04,0xa2,0x7c]
+# W64: v_cmp_lt_i64_e32 vcc, s[2:3], v[2:3]      ; encoding: [0x02,0x04,0xa2,0x7c]
+0x02,0x04,0xa2,0x7c
+
+# W32: v_cmp_lt_i64_e32 vcc_lo, s[104:105], v[2:3] ; encoding: [0x68,0x04,0xa2,0x7c]
+# W64: v_cmp_lt_i64_e32 vcc, s[104:105], v[2:3]  ; encoding: [0x68,0x04,0xa2,0x7c]
+0x68,0x04,0xa2,0x7c
+
+# W32: v_cmp_lt_i64_e32 vcc_lo, vcc, v[2:3]      ; encoding: [0x6a,0x04,0xa2,0x7c]
+# W64: v_cmp_lt_i64_e32 vcc, vcc, v[2:3]         ; encoding: [0x6a,0x04,0xa2,0x7c]
+0x6a,0x04,0xa2,0x7c
+
+# W32: v_cmp_lt_i64_e32 vcc_lo, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0xa2,0x7c]
+# W64: v_cmp_lt_i64_e32 vcc, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0xa2,0x7c]
+0x7a,0x04,0xa2,0x7c
+
+# W32: v_cmp_lt_i64_e32 vcc_lo, exec, v[2:3]     ; encoding: [0x7e,0x04,0xa2,0x7c]
+# W64: v_cmp_lt_i64_e32 vcc, exec, v[2:3]        ; encoding: [0x7e,0x04,0xa2,0x7c]
+0x7e,0x04,0xa2,0x7c
+
+# W32: v_cmp_lt_i64_e32 vcc_lo, null, v[2:3]     ; encoding: [0x7c,0x04,0xa2,0x7c]
+# W64: v_cmp_lt_i64_e32 vcc, null, v[2:3]        ; encoding: [0x7c,0x04,0xa2,0x7c]
+0x7c,0x04,0xa2,0x7c
+
+# W32: v_cmp_lt_i64_e32 vcc_lo, -1, v[2:3]       ; encoding: [0xc1,0x04,0xa2,0x7c]
+# W64: v_cmp_lt_i64_e32 vcc, -1, v[2:3]          ; encoding: [0xc1,0x04,0xa2,0x7c]
+0xc1,0x04,0xa2,0x7c
+
+# W32: v_cmp_lt_i64_e32 vcc_lo, 0.5, v[2:3]      ; encoding: [0xf0,0x04,0xa2,0x7c]
+# W64: v_cmp_lt_i64_e32 vcc, 0.5, v[2:3]         ; encoding: [0xf0,0x04,0xa2,0x7c]
+0xf0,0x04,0xa2,0x7c
+
+# W32: v_cmp_lt_i64_e32 vcc_lo, src_scc, v[2:3]  ; encoding: [0xfd,0x04,0xa2,0x7c]
+# W64: v_cmp_lt_i64_e32 vcc, src_scc, v[2:3]     ; encoding: [0xfd,0x04,0xa2,0x7c]
+0xfd,0x04,0xa2,0x7c
+
+# W32: v_cmp_lt_i64_e32 vcc_lo, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xa3,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_lt_i64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xa3,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xa3,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_lt_u16_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x72,0x7c]
+# W64: v_cmp_lt_u16_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x72,0x7c]
+0x01,0x05,0x72,0x7c
+
+# W32: v_cmp_lt_u16_e32 vcc_lo, v127, v2         ; encoding: [0x7f,0x05,0x72,0x7c]
+# W64: v_cmp_lt_u16_e32 vcc, v127, v2            ; encoding: [0x7f,0x05,0x72,0x7c]
+0x7f,0x05,0x72,0x7c
+
+# W32: v_cmp_lt_u16_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x72,0x7c]
+# W64: v_cmp_lt_u16_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x72,0x7c]
+0x01,0x04,0x72,0x7c
+
+# W32: v_cmp_lt_u16_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x72,0x7c]
+# W64: v_cmp_lt_u16_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x72,0x7c]
+0x69,0x04,0x72,0x7c
+
+# W32: v_cmp_lt_u16_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x72,0x7c]
+# W64: v_cmp_lt_u16_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x72,0x7c]
+0x6a,0x04,0x72,0x7c
+
+# W32: v_cmp_lt_u16_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x72,0x7c]
+# W64: v_cmp_lt_u16_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x72,0x7c]
+0x6b,0x04,0x72,0x7c
+
+# W32: v_cmp_lt_u16_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x72,0x7c]
+# W64: v_cmp_lt_u16_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x72,0x7c]
+0x7b,0x04,0x72,0x7c
+
+# W32: v_cmp_lt_u16_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x72,0x7c]
+# W64: v_cmp_lt_u16_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x72,0x7c]
+0x7d,0x04,0x72,0x7c
+
+# W32: v_cmp_lt_u16_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x72,0x7c]
+# W64: v_cmp_lt_u16_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x72,0x7c]
+0x7e,0x04,0x72,0x7c
+
+# W32: v_cmp_lt_u16_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x72,0x7c]
+# W64: v_cmp_lt_u16_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x72,0x7c]
+0x7f,0x04,0x72,0x7c
+
+# W32: v_cmp_lt_u16_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x72,0x7c]
+# W64: v_cmp_lt_u16_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x72,0x7c]
+0x7c,0x04,0x72,0x7c
+
+# W32: v_cmp_lt_u16_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x72,0x7c]
+# W64: v_cmp_lt_u16_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x72,0x7c]
+0xc1,0x04,0x72,0x7c
+
+# W32: v_cmp_lt_u16_e32 vcc_lo, 0x3800, v2
+# W64: v_cmp_lt_u16_e32 vcc, 0x3800, v2          ; encoding: [0xff,0x04,0x72,0x7c,0x00,0x38,0x00,0x00]
+0xf0,0x04,0x72,0x7c
+
+# W32: v_cmp_lt_u16_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x72,0x7c]
+# W64: v_cmp_lt_u16_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x72,0x7c]
+0xfd,0x04,0x72,0x7c
+
+# W32: v_cmp_lt_u16_e32 vcc_lo, 0xfe0b, v127     ; encoding: [0xff,0xfe,0x72,0x7c,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_lt_u16_e32 vcc, 0xfe0b, v127        ; encoding: [0xff,0xfe,0x72,0x7c,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x72,0x7c,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_lt_u32_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x92,0x7c]
+# W64: v_cmp_lt_u32_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x92,0x7c]
+0x01,0x05,0x92,0x7c
+
+# W32: v_cmp_lt_u32_e32 vcc_lo, v255, v2         ; encoding: [0xff,0x05,0x92,0x7c]
+# W64: v_cmp_lt_u32_e32 vcc, v255, v2            ; encoding: [0xff,0x05,0x92,0x7c]
+0xff,0x05,0x92,0x7c
+
+# W32: v_cmp_lt_u32_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x92,0x7c]
+# W64: v_cmp_lt_u32_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x92,0x7c]
+0x01,0x04,0x92,0x7c
+
+# W32: v_cmp_lt_u32_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x92,0x7c]
+# W64: v_cmp_lt_u32_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x92,0x7c]
+0x69,0x04,0x92,0x7c
+
+# W32: v_cmp_lt_u32_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x92,0x7c]
+# W64: v_cmp_lt_u32_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x92,0x7c]
+0x6a,0x04,0x92,0x7c
+
+# W32: v_cmp_lt_u32_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x92,0x7c]
+# W64: v_cmp_lt_u32_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x92,0x7c]
+0x6b,0x04,0x92,0x7c
+
+# W32: v_cmp_lt_u32_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x92,0x7c]
+# W64: v_cmp_lt_u32_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x92,0x7c]
+0x7b,0x04,0x92,0x7c
+
+# W32: v_cmp_lt_u32_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x92,0x7c]
+# W64: v_cmp_lt_u32_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x92,0x7c]
+0x7d,0x04,0x92,0x7c
+
+# W32: v_cmp_lt_u32_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x92,0x7c]
+# W64: v_cmp_lt_u32_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x92,0x7c]
+0x7e,0x04,0x92,0x7c
+
+# W32: v_cmp_lt_u32_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x92,0x7c]
+# W64: v_cmp_lt_u32_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x92,0x7c]
+0x7f,0x04,0x92,0x7c
+
+# W32: v_cmp_lt_u32_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x92,0x7c]
+# W64: v_cmp_lt_u32_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x92,0x7c]
+0x7c,0x04,0x92,0x7c
+
+# W32: v_cmp_lt_u32_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x92,0x7c]
+# W64: v_cmp_lt_u32_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x92,0x7c]
+0xc1,0x04,0x92,0x7c
+
+# W32: v_cmp_lt_u32_e32 vcc_lo, 0.5, v2          ; encoding: [0xf0,0x04,0x92,0x7c]
+# W64: v_cmp_lt_u32_e32 vcc, 0.5, v2             ; encoding: [0xf0,0x04,0x92,0x7c]
+0xf0,0x04,0x92,0x7c
+
+# W32: v_cmp_lt_u32_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x92,0x7c]
+# W64: v_cmp_lt_u32_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x92,0x7c]
+0xfd,0x04,0x92,0x7c
+
+# W32: v_cmp_lt_u32_e32 vcc_lo, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x93,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_lt_u32_e32 vcc, 0xaf123456, v255    ; encoding: [0xff,0xfe,0x93,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x93,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_lt_u64_e32 vcc_lo, v[1:2], v[2:3]   ; encoding: [0x01,0x05,0xb2,0x7c]
+# W64: v_cmp_lt_u64_e32 vcc, v[1:2], v[2:3]      ; encoding: [0x01,0x05,0xb2,0x7c]
+0x01,0x05,0xb2,0x7c
+
+# W32: v_cmp_lt_u64_e32 vcc_lo, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0xb2,0x7c]
+# W64: v_cmp_lt_u64_e32 vcc, v[254:255], v[2:3]  ; encoding: [0xfe,0x05,0xb2,0x7c]
+0xfe,0x05,0xb2,0x7c
+
+# W32: v_cmp_lt_u64_e32 vcc_lo, s[2:3], v[2:3]   ; encoding: [0x02,0x04,0xb2,0x7c]
+# W64: v_cmp_lt_u64_e32 vcc, s[2:3], v[2:3]      ; encoding: [0x02,0x04,0xb2,0x7c]
+0x02,0x04,0xb2,0x7c
+
+# W32: v_cmp_lt_u64_e32 vcc_lo, s[104:105], v[2:3] ; encoding: [0x68,0x04,0xb2,0x7c]
+# W64: v_cmp_lt_u64_e32 vcc, s[104:105], v[2:3]  ; encoding: [0x68,0x04,0xb2,0x7c]
+0x68,0x04,0xb2,0x7c
+
+# W32: v_cmp_lt_u64_e32 vcc_lo, vcc, v[2:3]      ; encoding: [0x6a,0x04,0xb2,0x7c]
+# W64: v_cmp_lt_u64_e32 vcc, vcc, v[2:3]         ; encoding: [0x6a,0x04,0xb2,0x7c]
+0x6a,0x04,0xb2,0x7c
+
+# W32: v_cmp_lt_u64_e32 vcc_lo, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0xb2,0x7c]
+# W64: v_cmp_lt_u64_e32 vcc, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0xb2,0x7c]
+0x7a,0x04,0xb2,0x7c
+
+# W32: v_cmp_lt_u64_e32 vcc_lo, exec, v[2:3]     ; encoding: [0x7e,0x04,0xb2,0x7c]
+# W64: v_cmp_lt_u64_e32 vcc, exec, v[2:3]        ; encoding: [0x7e,0x04,0xb2,0x7c]
+0x7e,0x04,0xb2,0x7c
+
+# W32: v_cmp_lt_u64_e32 vcc_lo, null, v[2:3]     ; encoding: [0x7c,0x04,0xb2,0x7c]
+# W64: v_cmp_lt_u64_e32 vcc, null, v[2:3]        ; encoding: [0x7c,0x04,0xb2,0x7c]
+0x7c,0x04,0xb2,0x7c
+
+# W32: v_cmp_lt_u64_e32 vcc_lo, -1, v[2:3]       ; encoding: [0xc1,0x04,0xb2,0x7c]
+# W64: v_cmp_lt_u64_e32 vcc, -1, v[2:3]          ; encoding: [0xc1,0x04,0xb2,0x7c]
+0xc1,0x04,0xb2,0x7c
+
+# W32: v_cmp_lt_u64_e32 vcc_lo, 0.5, v[2:3]      ; encoding: [0xf0,0x04,0xb2,0x7c]
+# W64: v_cmp_lt_u64_e32 vcc, 0.5, v[2:3]         ; encoding: [0xf0,0x04,0xb2,0x7c]
+0xf0,0x04,0xb2,0x7c
+
+# W32: v_cmp_lt_u64_e32 vcc_lo, src_scc, v[2:3]  ; encoding: [0xfd,0x04,0xb2,0x7c]
+# W64: v_cmp_lt_u64_e32 vcc, src_scc, v[2:3]     ; encoding: [0xfd,0x04,0xb2,0x7c]
+0xfd,0x04,0xb2,0x7c
+
+# W32: v_cmp_lt_u64_e32 vcc_lo, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xb3,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_lt_u64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xb3,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xb3,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ne_i16_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x6a,0x7c]
+# W64: v_cmp_ne_i16_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x6a,0x7c]
+0x01,0x05,0x6a,0x7c
+
+# W32: v_cmp_ne_i16_e32 vcc_lo, v127, v2         ; encoding: [0x7f,0x05,0x6a,0x7c]
+# W64: v_cmp_ne_i16_e32 vcc, v127, v2            ; encoding: [0x7f,0x05,0x6a,0x7c]
+0x7f,0x05,0x6a,0x7c
+
+# W32: v_cmp_ne_i16_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x6a,0x7c]
+# W64: v_cmp_ne_i16_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x6a,0x7c]
+0x01,0x04,0x6a,0x7c
+
+# W32: v_cmp_ne_i16_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x6a,0x7c]
+# W64: v_cmp_ne_i16_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x6a,0x7c]
+0x69,0x04,0x6a,0x7c
+
+# W32: v_cmp_ne_i16_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x6a,0x7c]
+# W64: v_cmp_ne_i16_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x6a,0x7c]
+0x6a,0x04,0x6a,0x7c
+
+# W32: v_cmp_ne_i16_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x6a,0x7c]
+# W64: v_cmp_ne_i16_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x6a,0x7c]
+0x6b,0x04,0x6a,0x7c
+
+# W32: v_cmp_ne_i16_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x6a,0x7c]
+# W64: v_cmp_ne_i16_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x6a,0x7c]
+0x7b,0x04,0x6a,0x7c
+
+# W32: v_cmp_ne_i16_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x6a,0x7c]
+# W64: v_cmp_ne_i16_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x6a,0x7c]
+0x7d,0x04,0x6a,0x7c
+
+# W32: v_cmp_ne_i16_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x6a,0x7c]
+# W64: v_cmp_ne_i16_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x6a,0x7c]
+0x7e,0x04,0x6a,0x7c
+
+# W32: v_cmp_ne_i16_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x6a,0x7c]
+# W64: v_cmp_ne_i16_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x6a,0x7c]
+0x7f,0x04,0x6a,0x7c
+
+# W32: v_cmp_ne_i16_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x6a,0x7c]
+# W64: v_cmp_ne_i16_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x6a,0x7c]
+0x7c,0x04,0x6a,0x7c
+
+# W32: v_cmp_ne_i16_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x6a,0x7c]
+# W64: v_cmp_ne_i16_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x6a,0x7c]
+0xc1,0x04,0x6a,0x7c
+
+# W32: v_cmp_ne_i16_e32 vcc_lo, 0x3800, v2
+# W64: v_cmp_ne_i16_e32 vcc, 0x3800, v2          ; encoding: [0xff,0x04,0x6a,0x7c,0x00,0x38,0x00,0x00]
+0xf0,0x04,0x6a,0x7c
+
+# W32: v_cmp_ne_i16_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x6a,0x7c]
+# W64: v_cmp_ne_i16_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x6a,0x7c]
+0xfd,0x04,0x6a,0x7c
+
+# W32: v_cmp_ne_i16_e32 vcc_lo, 0xfe0b, v127     ; encoding: [0xff,0xfe,0x6a,0x7c,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_ne_i16_e32 vcc, 0xfe0b, v127        ; encoding: [0xff,0xfe,0x6a,0x7c,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x6a,0x7c,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_ne_i32_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x8a,0x7c]
+# W64: v_cmp_ne_i32_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x8a,0x7c]
+0x01,0x05,0x8a,0x7c
+
+# W32: v_cmp_ne_i32_e32 vcc_lo, v255, v2         ; encoding: [0xff,0x05,0x8a,0x7c]
+# W64: v_cmp_ne_i32_e32 vcc, v255, v2            ; encoding: [0xff,0x05,0x8a,0x7c]
+0xff,0x05,0x8a,0x7c
+
+# W32: v_cmp_ne_i32_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x8a,0x7c]
+# W64: v_cmp_ne_i32_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x8a,0x7c]
+0x01,0x04,0x8a,0x7c
+
+# W32: v_cmp_ne_i32_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x8a,0x7c]
+# W64: v_cmp_ne_i32_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x8a,0x7c]
+0x69,0x04,0x8a,0x7c
+
+# W32: v_cmp_ne_i32_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x8a,0x7c]
+# W64: v_cmp_ne_i32_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x8a,0x7c]
+0x6a,0x04,0x8a,0x7c
+
+# W32: v_cmp_ne_i32_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x8a,0x7c]
+# W64: v_cmp_ne_i32_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x8a,0x7c]
+0x6b,0x04,0x8a,0x7c
+
+# W32: v_cmp_ne_i32_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x8a,0x7c]
+# W64: v_cmp_ne_i32_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x8a,0x7c]
+0x7b,0x04,0x8a,0x7c
+
+# W32: v_cmp_ne_i32_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x8a,0x7c]
+# W64: v_cmp_ne_i32_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x8a,0x7c]
+0x7d,0x04,0x8a,0x7c
+
+# W32: v_cmp_ne_i32_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x8a,0x7c]
+# W64: v_cmp_ne_i32_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x8a,0x7c]
+0x7e,0x04,0x8a,0x7c
+
+# W32: v_cmp_ne_i32_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x8a,0x7c]
+# W64: v_cmp_ne_i32_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x8a,0x7c]
+0x7f,0x04,0x8a,0x7c
+
+# W32: v_cmp_ne_i32_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x8a,0x7c]
+# W64: v_cmp_ne_i32_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x8a,0x7c]
+0x7c,0x04,0x8a,0x7c
+
+# W32: v_cmp_ne_i32_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x8a,0x7c]
+# W64: v_cmp_ne_i32_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x8a,0x7c]
+0xc1,0x04,0x8a,0x7c
+
+# W32: v_cmp_ne_i32_e32 vcc_lo, 0.5, v2          ; encoding: [0xf0,0x04,0x8a,0x7c]
+# W64: v_cmp_ne_i32_e32 vcc, 0.5, v2             ; encoding: [0xf0,0x04,0x8a,0x7c]
+0xf0,0x04,0x8a,0x7c
+
+# W32: v_cmp_ne_i32_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x8a,0x7c]
+# W64: v_cmp_ne_i32_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x8a,0x7c]
+0xfd,0x04,0x8a,0x7c
+
+# W32: v_cmp_ne_i32_e32 vcc_lo, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x8b,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_ne_i32_e32 vcc, 0xaf123456, v255    ; encoding: [0xff,0xfe,0x8b,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x8b,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ne_i64_e32 vcc_lo, v[1:2], v[2:3]   ; encoding: [0x01,0x05,0xaa,0x7c]
+# W64: v_cmp_ne_i64_e32 vcc, v[1:2], v[2:3]      ; encoding: [0x01,0x05,0xaa,0x7c]
+0x01,0x05,0xaa,0x7c
+
+# W32: v_cmp_ne_i64_e32 vcc_lo, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0xaa,0x7c]
+# W64: v_cmp_ne_i64_e32 vcc, v[254:255], v[2:3]  ; encoding: [0xfe,0x05,0xaa,0x7c]
+0xfe,0x05,0xaa,0x7c
+
+# W32: v_cmp_ne_i64_e32 vcc_lo, s[2:3], v[2:3]   ; encoding: [0x02,0x04,0xaa,0x7c]
+# W64: v_cmp_ne_i64_e32 vcc, s[2:3], v[2:3]      ; encoding: [0x02,0x04,0xaa,0x7c]
+0x02,0x04,0xaa,0x7c
+
+# W32: v_cmp_ne_i64_e32 vcc_lo, s[104:105], v[2:3] ; encoding: [0x68,0x04,0xaa,0x7c]
+# W64: v_cmp_ne_i64_e32 vcc, s[104:105], v[2:3]  ; encoding: [0x68,0x04,0xaa,0x7c]
+0x68,0x04,0xaa,0x7c
+
+# W32: v_cmp_ne_i64_e32 vcc_lo, vcc, v[2:3]      ; encoding: [0x6a,0x04,0xaa,0x7c]
+# W64: v_cmp_ne_i64_e32 vcc, vcc, v[2:3]         ; encoding: [0x6a,0x04,0xaa,0x7c]
+0x6a,0x04,0xaa,0x7c
+
+# W32: v_cmp_ne_i64_e32 vcc_lo, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0xaa,0x7c]
+# W64: v_cmp_ne_i64_e32 vcc, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0xaa,0x7c]
+0x7a,0x04,0xaa,0x7c
+
+# W32: v_cmp_ne_i64_e32 vcc_lo, exec, v[2:3]     ; encoding: [0x7e,0x04,0xaa,0x7c]
+# W64: v_cmp_ne_i64_e32 vcc, exec, v[2:3]        ; encoding: [0x7e,0x04,0xaa,0x7c]
+0x7e,0x04,0xaa,0x7c
+
+# W32: v_cmp_ne_i64_e32 vcc_lo, null, v[2:3]     ; encoding: [0x7c,0x04,0xaa,0x7c]
+# W64: v_cmp_ne_i64_e32 vcc, null, v[2:3]        ; encoding: [0x7c,0x04,0xaa,0x7c]
+0x7c,0x04,0xaa,0x7c
+
+# W32: v_cmp_ne_i64_e32 vcc_lo, -1, v[2:3]       ; encoding: [0xc1,0x04,0xaa,0x7c]
+# W64: v_cmp_ne_i64_e32 vcc, -1, v[2:3]          ; encoding: [0xc1,0x04,0xaa,0x7c]
+0xc1,0x04,0xaa,0x7c
+
+# W32: v_cmp_ne_i64_e32 vcc_lo, 0.5, v[2:3]      ; encoding: [0xf0,0x04,0xaa,0x7c]
+# W64: v_cmp_ne_i64_e32 vcc, 0.5, v[2:3]         ; encoding: [0xf0,0x04,0xaa,0x7c]
+0xf0,0x04,0xaa,0x7c
+
+# W32: v_cmp_ne_i64_e32 vcc_lo, src_scc, v[2:3]  ; encoding: [0xfd,0x04,0xaa,0x7c]
+# W64: v_cmp_ne_i64_e32 vcc, src_scc, v[2:3]     ; encoding: [0xfd,0x04,0xaa,0x7c]
+0xfd,0x04,0xaa,0x7c
+
+# W32: v_cmp_ne_i64_e32 vcc_lo, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xab,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_ne_i64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xab,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xab,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ne_u16_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x7a,0x7c]
+# W64: v_cmp_ne_u16_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x7a,0x7c]
+0x01,0x05,0x7a,0x7c
+
+# W32: v_cmp_ne_u16_e32 vcc_lo, v127, v2         ; encoding: [0x7f,0x05,0x7a,0x7c]
+# W64: v_cmp_ne_u16_e32 vcc, v127, v2            ; encoding: [0x7f,0x05,0x7a,0x7c]
+0x7f,0x05,0x7a,0x7c
+
+# W32: v_cmp_ne_u16_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x7a,0x7c]
+# W64: v_cmp_ne_u16_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x7a,0x7c]
+0x01,0x04,0x7a,0x7c
+
+# W32: v_cmp_ne_u16_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x7a,0x7c]
+# W64: v_cmp_ne_u16_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x7a,0x7c]
+0x69,0x04,0x7a,0x7c
+
+# W32: v_cmp_ne_u16_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x7a,0x7c]
+# W64: v_cmp_ne_u16_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x7a,0x7c]
+0x6a,0x04,0x7a,0x7c
+
+# W32: v_cmp_ne_u16_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x7a,0x7c]
+# W64: v_cmp_ne_u16_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x7a,0x7c]
+0x6b,0x04,0x7a,0x7c
+
+# W32: v_cmp_ne_u16_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x7a,0x7c]
+# W64: v_cmp_ne_u16_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x7a,0x7c]
+0x7b,0x04,0x7a,0x7c
+
+# W32: v_cmp_ne_u16_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x7a,0x7c]
+# W64: v_cmp_ne_u16_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x7a,0x7c]
+0x7d,0x04,0x7a,0x7c
+
+# W32: v_cmp_ne_u16_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x7a,0x7c]
+# W64: v_cmp_ne_u16_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x7a,0x7c]
+0x7e,0x04,0x7a,0x7c
+
+# W32: v_cmp_ne_u16_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x7a,0x7c]
+# W64: v_cmp_ne_u16_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x7a,0x7c]
+0x7f,0x04,0x7a,0x7c
+
+# W32: v_cmp_ne_u16_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x7a,0x7c]
+# W64: v_cmp_ne_u16_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x7a,0x7c]
+0x7c,0x04,0x7a,0x7c
+
+# W32: v_cmp_ne_u16_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x7a,0x7c]
+# W64: v_cmp_ne_u16_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x7a,0x7c]
+0xc1,0x04,0x7a,0x7c
+
+# W32: v_cmp_ne_u16_e32 vcc_lo, 0x3800, v2
+# W64: v_cmp_ne_u16_e32 vcc, 0x3800, v2          ; encoding: [0xff,0x04,0x7a,0x7c,0x00,0x38,0x00,0x00]
+0xf0,0x04,0x7a,0x7c
+
+# W32: v_cmp_ne_u16_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x7a,0x7c]
+# W64: v_cmp_ne_u16_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x7a,0x7c]
+0xfd,0x04,0x7a,0x7c
+
+# W32: v_cmp_ne_u16_e32 vcc_lo, 0xfe0b, v127     ; encoding: [0xff,0xfe,0x7a,0x7c,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_ne_u16_e32 vcc, 0xfe0b, v127        ; encoding: [0xff,0xfe,0x7a,0x7c,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x7a,0x7c,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_ne_u32_e32 vcc_lo, v1, v2           ; encoding: [0x01,0x05,0x9a,0x7c]
+# W64: v_cmp_ne_u32_e32 vcc, v1, v2              ; encoding: [0x01,0x05,0x9a,0x7c]
+0x01,0x05,0x9a,0x7c
+
+# W32: v_cmp_ne_u32_e32 vcc_lo, v255, v2         ; encoding: [0xff,0x05,0x9a,0x7c]
+# W64: v_cmp_ne_u32_e32 vcc, v255, v2            ; encoding: [0xff,0x05,0x9a,0x7c]
+0xff,0x05,0x9a,0x7c
+
+# W32: v_cmp_ne_u32_e32 vcc_lo, s1, v2           ; encoding: [0x01,0x04,0x9a,0x7c]
+# W64: v_cmp_ne_u32_e32 vcc, s1, v2              ; encoding: [0x01,0x04,0x9a,0x7c]
+0x01,0x04,0x9a,0x7c
+
+# W32: v_cmp_ne_u32_e32 vcc_lo, s105, v2         ; encoding: [0x69,0x04,0x9a,0x7c]
+# W64: v_cmp_ne_u32_e32 vcc, s105, v2            ; encoding: [0x69,0x04,0x9a,0x7c]
+0x69,0x04,0x9a,0x7c
+
+# W32: v_cmp_ne_u32_e32 vcc_lo, vcc_lo, v2       ; encoding: [0x6a,0x04,0x9a,0x7c]
+# W64: v_cmp_ne_u32_e32 vcc, vcc_lo, v2          ; encoding: [0x6a,0x04,0x9a,0x7c]
+0x6a,0x04,0x9a,0x7c
+
+# W32: v_cmp_ne_u32_e32 vcc_lo, vcc_hi, v2       ; encoding: [0x6b,0x04,0x9a,0x7c]
+# W64: v_cmp_ne_u32_e32 vcc, vcc_hi, v2          ; encoding: [0x6b,0x04,0x9a,0x7c]
+0x6b,0x04,0x9a,0x7c
+
+# W32: v_cmp_ne_u32_e32 vcc_lo, ttmp15, v2       ; encoding: [0x7b,0x04,0x9a,0x7c]
+# W64: v_cmp_ne_u32_e32 vcc, ttmp15, v2          ; encoding: [0x7b,0x04,0x9a,0x7c]
+0x7b,0x04,0x9a,0x7c
+
+# W32: v_cmp_ne_u32_e32 vcc_lo, m0, v2           ; encoding: [0x7d,0x04,0x9a,0x7c]
+# W64: v_cmp_ne_u32_e32 vcc, m0, v2              ; encoding: [0x7d,0x04,0x9a,0x7c]
+0x7d,0x04,0x9a,0x7c
+
+# W32: v_cmp_ne_u32_e32 vcc_lo, exec_lo, v2      ; encoding: [0x7e,0x04,0x9a,0x7c]
+# W64: v_cmp_ne_u32_e32 vcc, exec_lo, v2         ; encoding: [0x7e,0x04,0x9a,0x7c]
+0x7e,0x04,0x9a,0x7c
+
+# W32: v_cmp_ne_u32_e32 vcc_lo, exec_hi, v2      ; encoding: [0x7f,0x04,0x9a,0x7c]
+# W64: v_cmp_ne_u32_e32 vcc, exec_hi, v2         ; encoding: [0x7f,0x04,0x9a,0x7c]
+0x7f,0x04,0x9a,0x7c
+
+# W32: v_cmp_ne_u32_e32 vcc_lo, null, v2         ; encoding: [0x7c,0x04,0x9a,0x7c]
+# W64: v_cmp_ne_u32_e32 vcc, null, v2            ; encoding: [0x7c,0x04,0x9a,0x7c]
+0x7c,0x04,0x9a,0x7c
+
+# W32: v_cmp_ne_u32_e32 vcc_lo, -1, v2           ; encoding: [0xc1,0x04,0x9a,0x7c]
+# W64: v_cmp_ne_u32_e32 vcc, -1, v2              ; encoding: [0xc1,0x04,0x9a,0x7c]
+0xc1,0x04,0x9a,0x7c
+
+# W32: v_cmp_ne_u32_e32 vcc_lo, 0.5, v2          ; encoding: [0xf0,0x04,0x9a,0x7c]
+# W64: v_cmp_ne_u32_e32 vcc, 0.5, v2             ; encoding: [0xf0,0x04,0x9a,0x7c]
+0xf0,0x04,0x9a,0x7c
+
+# W32: v_cmp_ne_u32_e32 vcc_lo, src_scc, v2      ; encoding: [0xfd,0x04,0x9a,0x7c]
+# W64: v_cmp_ne_u32_e32 vcc, src_scc, v2         ; encoding: [0xfd,0x04,0x9a,0x7c]
+0xfd,0x04,0x9a,0x7c
+
+# W32: v_cmp_ne_u32_e32 vcc_lo, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x9b,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_ne_u32_e32 vcc, 0xaf123456, v255    ; encoding: [0xff,0xfe,0x9b,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x9b,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ne_u64_e32 vcc_lo, v[1:2], v[2:3]   ; encoding: [0x01,0x05,0xba,0x7c]
+# W64: v_cmp_ne_u64_e32 vcc, v[1:2], v[2:3]      ; encoding: [0x01,0x05,0xba,0x7c]
+0x01,0x05,0xba,0x7c
+
+# W32: v_cmp_ne_u64_e32 vcc_lo, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0xba,0x7c]
+# W64: v_cmp_ne_u64_e32 vcc, v[254:255], v[2:3]  ; encoding: [0xfe,0x05,0xba,0x7c]
+0xfe,0x05,0xba,0x7c
+
+# W32: v_cmp_ne_u64_e32 vcc_lo, s[2:3], v[2:3]   ; encoding: [0x02,0x04,0xba,0x7c]
+# W64: v_cmp_ne_u64_e32 vcc, s[2:3], v[2:3]      ; encoding: [0x02,0x04,0xba,0x7c]
+0x02,0x04,0xba,0x7c
+
+# W32: v_cmp_ne_u64_e32 vcc_lo, s[104:105], v[2:3] ; encoding: [0x68,0x04,0xba,0x7c]
+# W64: v_cmp_ne_u64_e32 vcc, s[104:105], v[2:3]  ; encoding: [0x68,0x04,0xba,0x7c]
+0x68,0x04,0xba,0x7c
+
+# W32: v_cmp_ne_u64_e32 vcc_lo, vcc, v[2:3]      ; encoding: [0x6a,0x04,0xba,0x7c]
+# W64: v_cmp_ne_u64_e32 vcc, vcc, v[2:3]         ; encoding: [0x6a,0x04,0xba,0x7c]
+0x6a,0x04,0xba,0x7c
+
+# W32: v_cmp_ne_u64_e32 vcc_lo, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0xba,0x7c]
+# W64: v_cmp_ne_u64_e32 vcc, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0xba,0x7c]
+0x7a,0x04,0xba,0x7c
+
+# W32: v_cmp_ne_u64_e32 vcc_lo, exec, v[2:3]     ; encoding: [0x7e,0x04,0xba,0x7c]
+# W64: v_cmp_ne_u64_e32 vcc, exec, v[2:3]        ; encoding: [0x7e,0x04,0xba,0x7c]
+0x7e,0x04,0xba,0x7c
+
+# W32: v_cmp_ne_u64_e32 vcc_lo, null, v[2:3]     ; encoding: [0x7c,0x04,0xba,0x7c]
+# W64: v_cmp_ne_u64_e32 vcc, null, v[2:3]        ; encoding: [0x7c,0x04,0xba,0x7c]
+0x7c,0x04,0xba,0x7c
+
+# W32: v_cmp_ne_u64_e32 vcc_lo, -1, v[2:3]       ; encoding: [0xc1,0x04,0xba,0x7c]
+# W64: v_cmp_ne_u64_e32 vcc, -1, v[2:3]          ; encoding: [0xc1,0x04,0xba,0x7c]
+0xc1,0x04,0xba,0x7c
+
+# W32: v_cmp_ne_u64_e32 vcc_lo, 0.5, v[2:3]      ; encoding: [0xf0,0x04,0xba,0x7c]
+# W64: v_cmp_ne_u64_e32 vcc, 0.5, v[2:3]         ; encoding: [0xf0,0x04,0xba,0x7c]
+0xf0,0x04,0xba,0x7c
+
+# W32: v_cmp_ne_u64_e32 vcc_lo, src_scc, v[2:3]  ; encoding: [0xfd,0x04,0xba,0x7c]
+# W64: v_cmp_ne_u64_e32 vcc, src_scc, v[2:3]     ; encoding: [0xfd,0x04,0xba,0x7c]
+0xfd,0x04,0xba,0x7c
+
+# W32: v_cmp_ne_u64_e32 vcc_lo, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xbb,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_ne_u64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xbb,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xbb,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_neq_f16_e32 vcc_lo, v1, v2          ; encoding: [0x01,0x05,0x1a,0x7c]
+# W64: v_cmp_neq_f16_e32 vcc, v1, v2             ; encoding: [0x01,0x05,0x1a,0x7c]
+0x01,0x05,0x1a,0x7c
+
+# W32: v_cmp_neq_f16_e32 vcc_lo, v127, v2        ; encoding: [0x7f,0x05,0x1a,0x7c]
+# W64: v_cmp_neq_f16_e32 vcc, v127, v2           ; encoding: [0x7f,0x05,0x1a,0x7c]
+0x7f,0x05,0x1a,0x7c
+
+# W32: v_cmp_neq_f16_e32 vcc_lo, s1, v2          ; encoding: [0x01,0x04,0x1a,0x7c]
+# W64: v_cmp_neq_f16_e32 vcc, s1, v2             ; encoding: [0x01,0x04,0x1a,0x7c]
+0x01,0x04,0x1a,0x7c
+
+# W32: v_cmp_neq_f16_e32 vcc_lo, s105, v2        ; encoding: [0x69,0x04,0x1a,0x7c]
+# W64: v_cmp_neq_f16_e32 vcc, s105, v2           ; encoding: [0x69,0x04,0x1a,0x7c]
+0x69,0x04,0x1a,0x7c
+
+# W32: v_cmp_neq_f16_e32 vcc_lo, vcc_lo, v2      ; encoding: [0x6a,0x04,0x1a,0x7c]
+# W64: v_cmp_neq_f16_e32 vcc, vcc_lo, v2         ; encoding: [0x6a,0x04,0x1a,0x7c]
+0x6a,0x04,0x1a,0x7c
+
+# W32: v_cmp_neq_f16_e32 vcc_lo, vcc_hi, v2      ; encoding: [0x6b,0x04,0x1a,0x7c]
+# W64: v_cmp_neq_f16_e32 vcc, vcc_hi, v2         ; encoding: [0x6b,0x04,0x1a,0x7c]
+0x6b,0x04,0x1a,0x7c
+
+# W32: v_cmp_neq_f16_e32 vcc_lo, ttmp15, v2      ; encoding: [0x7b,0x04,0x1a,0x7c]
+# W64: v_cmp_neq_f16_e32 vcc, ttmp15, v2         ; encoding: [0x7b,0x04,0x1a,0x7c]
+0x7b,0x04,0x1a,0x7c
+
+# W32: v_cmp_neq_f16_e32 vcc_lo, m0, v2          ; encoding: [0x7d,0x04,0x1a,0x7c]
+# W64: v_cmp_neq_f16_e32 vcc, m0, v2             ; encoding: [0x7d,0x04,0x1a,0x7c]
+0x7d,0x04,0x1a,0x7c
+
+# W32: v_cmp_neq_f16_e32 vcc_lo, exec_lo, v2     ; encoding: [0x7e,0x04,0x1a,0x7c]
+# W64: v_cmp_neq_f16_e32 vcc, exec_lo, v2        ; encoding: [0x7e,0x04,0x1a,0x7c]
+0x7e,0x04,0x1a,0x7c
+
+# W32: v_cmp_neq_f16_e32 vcc_lo, exec_hi, v2     ; encoding: [0x7f,0x04,0x1a,0x7c]
+# W64: v_cmp_neq_f16_e32 vcc, exec_hi, v2        ; encoding: [0x7f,0x04,0x1a,0x7c]
+0x7f,0x04,0x1a,0x7c
+
+# W32: v_cmp_neq_f16_e32 vcc_lo, null, v2        ; encoding: [0x7c,0x04,0x1a,0x7c]
+# W64: v_cmp_neq_f16_e32 vcc, null, v2           ; encoding: [0x7c,0x04,0x1a,0x7c]
+0x7c,0x04,0x1a,0x7c
+
+# W32: v_cmp_neq_f16_e32 vcc_lo, -1, v2          ; encoding: [0xc1,0x04,0x1a,0x7c]
+# W64: v_cmp_neq_f16_e32 vcc, -1, v2             ; encoding: [0xc1,0x04,0x1a,0x7c]
+0xc1,0x04,0x1a,0x7c
+
+# W32: v_cmp_neq_f16_e32 vcc_lo, 0.5, v2         ; encoding: [0xf0,0x04,0x1a,0x7c]
+# W64: v_cmp_neq_f16_e32 vcc, 0.5, v2            ; encoding: [0xf0,0x04,0x1a,0x7c]
+0xf0,0x04,0x1a,0x7c
+
+# W32: v_cmp_neq_f16_e32 vcc_lo, src_scc, v2     ; encoding: [0xfd,0x04,0x1a,0x7c]
+# W64: v_cmp_neq_f16_e32 vcc, src_scc, v2        ; encoding: [0xfd,0x04,0x1a,0x7c]
+0xfd,0x04,0x1a,0x7c
+
+# W32: v_cmp_neq_f16_e32 vcc_lo, 0xfe0b, v127    ; encoding: [0xff,0xfe,0x1a,0x7c,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_neq_f16_e32 vcc, 0xfe0b, v127       ; encoding: [0xff,0xfe,0x1a,0x7c,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x1a,0x7c,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_neq_f32_e32 vcc_lo, v1, v2          ; encoding: [0x01,0x05,0x3a,0x7c]
+# W64: v_cmp_neq_f32_e32 vcc, v1, v2             ; encoding: [0x01,0x05,0x3a,0x7c]
+0x01,0x05,0x3a,0x7c
+
+# W32: v_cmp_neq_f32_e32 vcc_lo, v255, v2        ; encoding: [0xff,0x05,0x3a,0x7c]
+# W64: v_cmp_neq_f32_e32 vcc, v255, v2           ; encoding: [0xff,0x05,0x3a,0x7c]
+0xff,0x05,0x3a,0x7c
+
+# W32: v_cmp_neq_f32_e32 vcc_lo, s1, v2          ; encoding: [0x01,0x04,0x3a,0x7c]
+# W64: v_cmp_neq_f32_e32 vcc, s1, v2             ; encoding: [0x01,0x04,0x3a,0x7c]
+0x01,0x04,0x3a,0x7c
+
+# W32: v_cmp_neq_f32_e32 vcc_lo, s105, v2        ; encoding: [0x69,0x04,0x3a,0x7c]
+# W64: v_cmp_neq_f32_e32 vcc, s105, v2           ; encoding: [0x69,0x04,0x3a,0x7c]
+0x69,0x04,0x3a,0x7c
+
+# W32: v_cmp_neq_f32_e32 vcc_lo, vcc_lo, v2      ; encoding: [0x6a,0x04,0x3a,0x7c]
+# W64: v_cmp_neq_f32_e32 vcc, vcc_lo, v2         ; encoding: [0x6a,0x04,0x3a,0x7c]
+0x6a,0x04,0x3a,0x7c
+
+# W32: v_cmp_neq_f32_e32 vcc_lo, vcc_hi, v2      ; encoding: [0x6b,0x04,0x3a,0x7c]
+# W64: v_cmp_neq_f32_e32 vcc, vcc_hi, v2         ; encoding: [0x6b,0x04,0x3a,0x7c]
+0x6b,0x04,0x3a,0x7c
+
+# W32: v_cmp_neq_f32_e32 vcc_lo, ttmp15, v2      ; encoding: [0x7b,0x04,0x3a,0x7c]
+# W64: v_cmp_neq_f32_e32 vcc, ttmp15, v2         ; encoding: [0x7b,0x04,0x3a,0x7c]
+0x7b,0x04,0x3a,0x7c
+
+# W32: v_cmp_neq_f32_e32 vcc_lo, m0, v2          ; encoding: [0x7d,0x04,0x3a,0x7c]
+# W64: v_cmp_neq_f32_e32 vcc, m0, v2             ; encoding: [0x7d,0x04,0x3a,0x7c]
+0x7d,0x04,0x3a,0x7c
+
+# W32: v_cmp_neq_f32_e32 vcc_lo, exec_lo, v2     ; encoding: [0x7e,0x04,0x3a,0x7c]
+# W64: v_cmp_neq_f32_e32 vcc, exec_lo, v2        ; encoding: [0x7e,0x04,0x3a,0x7c]
+0x7e,0x04,0x3a,0x7c
+
+# W32: v_cmp_neq_f32_e32 vcc_lo, exec_hi, v2     ; encoding: [0x7f,0x04,0x3a,0x7c]
+# W64: v_cmp_neq_f32_e32 vcc, exec_hi, v2        ; encoding: [0x7f,0x04,0x3a,0x7c]
+0x7f,0x04,0x3a,0x7c
+
+# W32: v_cmp_neq_f32_e32 vcc_lo, null, v2        ; encoding: [0x7c,0x04,0x3a,0x7c]
+# W64: v_cmp_neq_f32_e32 vcc, null, v2           ; encoding: [0x7c,0x04,0x3a,0x7c]
+0x7c,0x04,0x3a,0x7c
+
+# W32: v_cmp_neq_f32_e32 vcc_lo, -1, v2          ; encoding: [0xc1,0x04,0x3a,0x7c]
+# W64: v_cmp_neq_f32_e32 vcc, -1, v2             ; encoding: [0xc1,0x04,0x3a,0x7c]
+0xc1,0x04,0x3a,0x7c
+
+# W32: v_cmp_neq_f32_e32 vcc_lo, 0.5, v2         ; encoding: [0xf0,0x04,0x3a,0x7c]
+# W64: v_cmp_neq_f32_e32 vcc, 0.5, v2            ; encoding: [0xf0,0x04,0x3a,0x7c]
+0xf0,0x04,0x3a,0x7c
+
+# W32: v_cmp_neq_f32_e32 vcc_lo, src_scc, v2     ; encoding: [0xfd,0x04,0x3a,0x7c]
+# W64: v_cmp_neq_f32_e32 vcc, src_scc, v2        ; encoding: [0xfd,0x04,0x3a,0x7c]
+0xfd,0x04,0x3a,0x7c
+
+# W32: v_cmp_neq_f32_e32 vcc_lo, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x3b,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_neq_f32_e32 vcc, 0xaf123456, v255   ; encoding: [0xff,0xfe,0x3b,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x3b,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_neq_f64_e32 vcc_lo, v[1:2], v[2:3]  ; encoding: [0x01,0x05,0x5a,0x7c]
+# W64: v_cmp_neq_f64_e32 vcc, v[1:2], v[2:3]     ; encoding: [0x01,0x05,0x5a,0x7c]
+0x01,0x05,0x5a,0x7c
+
+# W32: v_cmp_neq_f64_e32 vcc_lo, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x5a,0x7c]
+# W64: v_cmp_neq_f64_e32 vcc, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x5a,0x7c]
+0xfe,0x05,0x5a,0x7c
+
+# W32: v_cmp_neq_f64_e32 vcc_lo, s[2:3], v[2:3]  ; encoding: [0x02,0x04,0x5a,0x7c]
+# W64: v_cmp_neq_f64_e32 vcc, s[2:3], v[2:3]     ; encoding: [0x02,0x04,0x5a,0x7c]
+0x02,0x04,0x5a,0x7c
+
+# W32: v_cmp_neq_f64_e32 vcc_lo, s[104:105], v[2:3] ; encoding: [0x68,0x04,0x5a,0x7c]
+# W64: v_cmp_neq_f64_e32 vcc, s[104:105], v[2:3] ; encoding: [0x68,0x04,0x5a,0x7c]
+0x68,0x04,0x5a,0x7c
+
+# W32: v_cmp_neq_f64_e32 vcc_lo, vcc, v[2:3]     ; encoding: [0x6a,0x04,0x5a,0x7c]
+# W64: v_cmp_neq_f64_e32 vcc, vcc, v[2:3]        ; encoding: [0x6a,0x04,0x5a,0x7c]
+0x6a,0x04,0x5a,0x7c
+
+# W32: v_cmp_neq_f64_e32 vcc_lo, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x5a,0x7c]
+# W64: v_cmp_neq_f64_e32 vcc, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x5a,0x7c]
+0x7a,0x04,0x5a,0x7c
+
+# W32: v_cmp_neq_f64_e32 vcc_lo, exec, v[2:3]    ; encoding: [0x7e,0x04,0x5a,0x7c]
+# W64: v_cmp_neq_f64_e32 vcc, exec, v[2:3]       ; encoding: [0x7e,0x04,0x5a,0x7c]
+0x7e,0x04,0x5a,0x7c
+
+# W32: v_cmp_neq_f64_e32 vcc_lo, null, v[2:3]    ; encoding: [0x7c,0x04,0x5a,0x7c]
+# W64: v_cmp_neq_f64_e32 vcc, null, v[2:3]       ; encoding: [0x7c,0x04,0x5a,0x7c]
+0x7c,0x04,0x5a,0x7c
+
+# W32: v_cmp_neq_f64_e32 vcc_lo, -1, v[2:3]      ; encoding: [0xc1,0x04,0x5a,0x7c]
+# W64: v_cmp_neq_f64_e32 vcc, -1, v[2:3]         ; encoding: [0xc1,0x04,0x5a,0x7c]
+0xc1,0x04,0x5a,0x7c
+
+# W32: v_cmp_neq_f64_e32 vcc_lo, 0.5, v[2:3]     ; encoding: [0xf0,0x04,0x5a,0x7c]
+# W64: v_cmp_neq_f64_e32 vcc, 0.5, v[2:3]        ; encoding: [0xf0,0x04,0x5a,0x7c]
+0xf0,0x04,0x5a,0x7c
+
+# W32: v_cmp_neq_f64_e32 vcc_lo, src_scc, v[2:3] ; encoding: [0xfd,0x04,0x5a,0x7c]
+# W64: v_cmp_neq_f64_e32 vcc, src_scc, v[2:3]    ; encoding: [0xfd,0x04,0x5a,0x7c]
+0xfd,0x04,0x5a,0x7c
+
+# W32: v_cmp_neq_f64_e32 vcc_lo, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x5b,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_neq_f64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x5b,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x5b,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_nge_f16_e32 vcc_lo, v1, v2          ; encoding: [0x01,0x05,0x12,0x7c]
+# W64: v_cmp_nge_f16_e32 vcc, v1, v2             ; encoding: [0x01,0x05,0x12,0x7c]
+0x01,0x05,0x12,0x7c
+
+# W32: v_cmp_nge_f16_e32 vcc_lo, v127, v2        ; encoding: [0x7f,0x05,0x12,0x7c]
+# W64: v_cmp_nge_f16_e32 vcc, v127, v2           ; encoding: [0x7f,0x05,0x12,0x7c]
+0x7f,0x05,0x12,0x7c
+
+# W32: v_cmp_nge_f16_e32 vcc_lo, s1, v2          ; encoding: [0x01,0x04,0x12,0x7c]
+# W64: v_cmp_nge_f16_e32 vcc, s1, v2             ; encoding: [0x01,0x04,0x12,0x7c]
+0x01,0x04,0x12,0x7c
+
+# W32: v_cmp_nge_f16_e32 vcc_lo, s105, v2        ; encoding: [0x69,0x04,0x12,0x7c]
+# W64: v_cmp_nge_f16_e32 vcc, s105, v2           ; encoding: [0x69,0x04,0x12,0x7c]
+0x69,0x04,0x12,0x7c
+
+# W32: v_cmp_nge_f16_e32 vcc_lo, vcc_lo, v2      ; encoding: [0x6a,0x04,0x12,0x7c]
+# W64: v_cmp_nge_f16_e32 vcc, vcc_lo, v2         ; encoding: [0x6a,0x04,0x12,0x7c]
+0x6a,0x04,0x12,0x7c
+
+# W32: v_cmp_nge_f16_e32 vcc_lo, vcc_hi, v2      ; encoding: [0x6b,0x04,0x12,0x7c]
+# W64: v_cmp_nge_f16_e32 vcc, vcc_hi, v2         ; encoding: [0x6b,0x04,0x12,0x7c]
+0x6b,0x04,0x12,0x7c
+
+# W32: v_cmp_nge_f16_e32 vcc_lo, ttmp15, v2      ; encoding: [0x7b,0x04,0x12,0x7c]
+# W64: v_cmp_nge_f16_e32 vcc, ttmp15, v2         ; encoding: [0x7b,0x04,0x12,0x7c]
+0x7b,0x04,0x12,0x7c
+
+# W32: v_cmp_nge_f16_e32 vcc_lo, m0, v2          ; encoding: [0x7d,0x04,0x12,0x7c]
+# W64: v_cmp_nge_f16_e32 vcc, m0, v2             ; encoding: [0x7d,0x04,0x12,0x7c]
+0x7d,0x04,0x12,0x7c
+
+# W32: v_cmp_nge_f16_e32 vcc_lo, exec_lo, v2     ; encoding: [0x7e,0x04,0x12,0x7c]
+# W64: v_cmp_nge_f16_e32 vcc, exec_lo, v2        ; encoding: [0x7e,0x04,0x12,0x7c]
+0x7e,0x04,0x12,0x7c
+
+# W32: v_cmp_nge_f16_e32 vcc_lo, exec_hi, v2     ; encoding: [0x7f,0x04,0x12,0x7c]
+# W64: v_cmp_nge_f16_e32 vcc, exec_hi, v2        ; encoding: [0x7f,0x04,0x12,0x7c]
+0x7f,0x04,0x12,0x7c
+
+# W32: v_cmp_nge_f16_e32 vcc_lo, null, v2        ; encoding: [0x7c,0x04,0x12,0x7c]
+# W64: v_cmp_nge_f16_e32 vcc, null, v2           ; encoding: [0x7c,0x04,0x12,0x7c]
+0x7c,0x04,0x12,0x7c
+
+# W32: v_cmp_nge_f16_e32 vcc_lo, -1, v2          ; encoding: [0xc1,0x04,0x12,0x7c]
+# W64: v_cmp_nge_f16_e32 vcc, -1, v2             ; encoding: [0xc1,0x04,0x12,0x7c]
+0xc1,0x04,0x12,0x7c
+
+# W32: v_cmp_nge_f16_e32 vcc_lo, 0.5, v2         ; encoding: [0xf0,0x04,0x12,0x7c]
+# W64: v_cmp_nge_f16_e32 vcc, 0.5, v2            ; encoding: [0xf0,0x04,0x12,0x7c]
+0xf0,0x04,0x12,0x7c
+
+# W32: v_cmp_nge_f16_e32 vcc_lo, src_scc, v2     ; encoding: [0xfd,0x04,0x12,0x7c]
+# W64: v_cmp_nge_f16_e32 vcc, src_scc, v2        ; encoding: [0xfd,0x04,0x12,0x7c]
+0xfd,0x04,0x12,0x7c
+
+# W32: v_cmp_nge_f16_e32 vcc_lo, 0xfe0b, v127    ; encoding: [0xff,0xfe,0x12,0x7c,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_nge_f16_e32 vcc, 0xfe0b, v127       ; encoding: [0xff,0xfe,0x12,0x7c,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x12,0x7c,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_nge_f32_e32 vcc_lo, v1, v2          ; encoding: [0x01,0x05,0x32,0x7c]
+# W64: v_cmp_nge_f32_e32 vcc, v1, v2             ; encoding: [0x01,0x05,0x32,0x7c]
+0x01,0x05,0x32,0x7c
+
+# W32: v_cmp_nge_f32_e32 vcc_lo, v255, v2        ; encoding: [0xff,0x05,0x32,0x7c]
+# W64: v_cmp_nge_f32_e32 vcc, v255, v2           ; encoding: [0xff,0x05,0x32,0x7c]
+0xff,0x05,0x32,0x7c
+
+# W32: v_cmp_nge_f32_e32 vcc_lo, s1, v2          ; encoding: [0x01,0x04,0x32,0x7c]
+# W64: v_cmp_nge_f32_e32 vcc, s1, v2             ; encoding: [0x01,0x04,0x32,0x7c]
+0x01,0x04,0x32,0x7c
+
+# W32: v_cmp_nge_f32_e32 vcc_lo, s105, v2        ; encoding: [0x69,0x04,0x32,0x7c]
+# W64: v_cmp_nge_f32_e32 vcc, s105, v2           ; encoding: [0x69,0x04,0x32,0x7c]
+0x69,0x04,0x32,0x7c
+
+# W32: v_cmp_nge_f32_e32 vcc_lo, vcc_lo, v2      ; encoding: [0x6a,0x04,0x32,0x7c]
+# W64: v_cmp_nge_f32_e32 vcc, vcc_lo, v2         ; encoding: [0x6a,0x04,0x32,0x7c]
+0x6a,0x04,0x32,0x7c
+
+# W32: v_cmp_nge_f32_e32 vcc_lo, vcc_hi, v2      ; encoding: [0x6b,0x04,0x32,0x7c]
+# W64: v_cmp_nge_f32_e32 vcc, vcc_hi, v2         ; encoding: [0x6b,0x04,0x32,0x7c]
+0x6b,0x04,0x32,0x7c
+
+# W32: v_cmp_nge_f32_e32 vcc_lo, ttmp15, v2      ; encoding: [0x7b,0x04,0x32,0x7c]
+# W64: v_cmp_nge_f32_e32 vcc, ttmp15, v2         ; encoding: [0x7b,0x04,0x32,0x7c]
+0x7b,0x04,0x32,0x7c
+
+# W32: v_cmp_nge_f32_e32 vcc_lo, m0, v2          ; encoding: [0x7d,0x04,0x32,0x7c]
+# W64: v_cmp_nge_f32_e32 vcc, m0, v2             ; encoding: [0x7d,0x04,0x32,0x7c]
+0x7d,0x04,0x32,0x7c
+
+# W32: v_cmp_nge_f32_e32 vcc_lo, exec_lo, v2     ; encoding: [0x7e,0x04,0x32,0x7c]
+# W64: v_cmp_nge_f32_e32 vcc, exec_lo, v2        ; encoding: [0x7e,0x04,0x32,0x7c]
+0x7e,0x04,0x32,0x7c
+
+# W32: v_cmp_nge_f32_e32 vcc_lo, exec_hi, v2     ; encoding: [0x7f,0x04,0x32,0x7c]
+# W64: v_cmp_nge_f32_e32 vcc, exec_hi, v2        ; encoding: [0x7f,0x04,0x32,0x7c]
+0x7f,0x04,0x32,0x7c
+
+# W32: v_cmp_nge_f32_e32 vcc_lo, null, v2        ; encoding: [0x7c,0x04,0x32,0x7c]
+# W64: v_cmp_nge_f32_e32 vcc, null, v2           ; encoding: [0x7c,0x04,0x32,0x7c]
+0x7c,0x04,0x32,0x7c
+
+# W32: v_cmp_nge_f32_e32 vcc_lo, -1, v2          ; encoding: [0xc1,0x04,0x32,0x7c]
+# W64: v_cmp_nge_f32_e32 vcc, -1, v2             ; encoding: [0xc1,0x04,0x32,0x7c]
+0xc1,0x04,0x32,0x7c
+
+# W32: v_cmp_nge_f32_e32 vcc_lo, 0.5, v2         ; encoding: [0xf0,0x04,0x32,0x7c]
+# W64: v_cmp_nge_f32_e32 vcc, 0.5, v2            ; encoding: [0xf0,0x04,0x32,0x7c]
+0xf0,0x04,0x32,0x7c
+
+# W32: v_cmp_nge_f32_e32 vcc_lo, src_scc, v2     ; encoding: [0xfd,0x04,0x32,0x7c]
+# W64: v_cmp_nge_f32_e32 vcc, src_scc, v2        ; encoding: [0xfd,0x04,0x32,0x7c]
+0xfd,0x04,0x32,0x7c
+
+# W32: v_cmp_nge_f32_e32 vcc_lo, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x33,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_nge_f32_e32 vcc, 0xaf123456, v255   ; encoding: [0xff,0xfe,0x33,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x33,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_nge_f64_e32 vcc_lo, v[1:2], v[2:3]  ; encoding: [0x01,0x05,0x52,0x7c]
+# W64: v_cmp_nge_f64_e32 vcc, v[1:2], v[2:3]     ; encoding: [0x01,0x05,0x52,0x7c]
+0x01,0x05,0x52,0x7c
+
+# W32: v_cmp_nge_f64_e32 vcc_lo, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x52,0x7c]
+# W64: v_cmp_nge_f64_e32 vcc, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x52,0x7c]
+0xfe,0x05,0x52,0x7c
+
+# W32: v_cmp_nge_f64_e32 vcc_lo, s[2:3], v[2:3]  ; encoding: [0x02,0x04,0x52,0x7c]
+# W64: v_cmp_nge_f64_e32 vcc, s[2:3], v[2:3]     ; encoding: [0x02,0x04,0x52,0x7c]
+0x02,0x04,0x52,0x7c
+
+# W32: v_cmp_nge_f64_e32 vcc_lo, s[104:105], v[2:3] ; encoding: [0x68,0x04,0x52,0x7c]
+# W64: v_cmp_nge_f64_e32 vcc, s[104:105], v[2:3] ; encoding: [0x68,0x04,0x52,0x7c]
+0x68,0x04,0x52,0x7c
+
+# W32: v_cmp_nge_f64_e32 vcc_lo, vcc, v[2:3]     ; encoding: [0x6a,0x04,0x52,0x7c]
+# W64: v_cmp_nge_f64_e32 vcc, vcc, v[2:3]        ; encoding: [0x6a,0x04,0x52,0x7c]
+0x6a,0x04,0x52,0x7c
+
+# W32: v_cmp_nge_f64_e32 vcc_lo, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x52,0x7c]
+# W64: v_cmp_nge_f64_e32 vcc, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x52,0x7c]
+0x7a,0x04,0x52,0x7c
+
+# W32: v_cmp_nge_f64_e32 vcc_lo, exec, v[2:3]    ; encoding: [0x7e,0x04,0x52,0x7c]
+# W64: v_cmp_nge_f64_e32 vcc, exec, v[2:3]       ; encoding: [0x7e,0x04,0x52,0x7c]
+0x7e,0x04,0x52,0x7c
+
+# W32: v_cmp_nge_f64_e32 vcc_lo, null, v[2:3]    ; encoding: [0x7c,0x04,0x52,0x7c]
+# W64: v_cmp_nge_f64_e32 vcc, null, v[2:3]       ; encoding: [0x7c,0x04,0x52,0x7c]
+0x7c,0x04,0x52,0x7c
+
+# W32: v_cmp_nge_f64_e32 vcc_lo, -1, v[2:3]      ; encoding: [0xc1,0x04,0x52,0x7c]
+# W64: v_cmp_nge_f64_e32 vcc, -1, v[2:3]         ; encoding: [0xc1,0x04,0x52,0x7c]
+0xc1,0x04,0x52,0x7c
+
+# W32: v_cmp_nge_f64_e32 vcc_lo, 0.5, v[2:3]     ; encoding: [0xf0,0x04,0x52,0x7c]
+# W64: v_cmp_nge_f64_e32 vcc, 0.5, v[2:3]        ; encoding: [0xf0,0x04,0x52,0x7c]
+0xf0,0x04,0x52,0x7c
+
+# W32: v_cmp_nge_f64_e32 vcc_lo, src_scc, v[2:3] ; encoding: [0xfd,0x04,0x52,0x7c]
+# W64: v_cmp_nge_f64_e32 vcc, src_scc, v[2:3]    ; encoding: [0xfd,0x04,0x52,0x7c]
+0xfd,0x04,0x52,0x7c
+
+# W32: v_cmp_nge_f64_e32 vcc_lo, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x53,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_nge_f64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x53,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x53,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ngt_f16_e32 vcc_lo, v1, v2          ; encoding: [0x01,0x05,0x16,0x7c]
+# W64: v_cmp_ngt_f16_e32 vcc, v1, v2             ; encoding: [0x01,0x05,0x16,0x7c]
+0x01,0x05,0x16,0x7c
+
+# W32: v_cmp_ngt_f16_e32 vcc_lo, v127, v2        ; encoding: [0x7f,0x05,0x16,0x7c]
+# W64: v_cmp_ngt_f16_e32 vcc, v127, v2           ; encoding: [0x7f,0x05,0x16,0x7c]
+0x7f,0x05,0x16,0x7c
+
+# W32: v_cmp_ngt_f16_e32 vcc_lo, s1, v2          ; encoding: [0x01,0x04,0x16,0x7c]
+# W64: v_cmp_ngt_f16_e32 vcc, s1, v2             ; encoding: [0x01,0x04,0x16,0x7c]
+0x01,0x04,0x16,0x7c
+
+# W32: v_cmp_ngt_f16_e32 vcc_lo, s105, v2        ; encoding: [0x69,0x04,0x16,0x7c]
+# W64: v_cmp_ngt_f16_e32 vcc, s105, v2           ; encoding: [0x69,0x04,0x16,0x7c]
+0x69,0x04,0x16,0x7c
+
+# W32: v_cmp_ngt_f16_e32 vcc_lo, vcc_lo, v2      ; encoding: [0x6a,0x04,0x16,0x7c]
+# W64: v_cmp_ngt_f16_e32 vcc, vcc_lo, v2         ; encoding: [0x6a,0x04,0x16,0x7c]
+0x6a,0x04,0x16,0x7c
+
+# W32: v_cmp_ngt_f16_e32 vcc_lo, vcc_hi, v2      ; encoding: [0x6b,0x04,0x16,0x7c]
+# W64: v_cmp_ngt_f16_e32 vcc, vcc_hi, v2         ; encoding: [0x6b,0x04,0x16,0x7c]
+0x6b,0x04,0x16,0x7c
+
+# W32: v_cmp_ngt_f16_e32 vcc_lo, ttmp15, v2      ; encoding: [0x7b,0x04,0x16,0x7c]
+# W64: v_cmp_ngt_f16_e32 vcc, ttmp15, v2         ; encoding: [0x7b,0x04,0x16,0x7c]
+0x7b,0x04,0x16,0x7c
+
+# W32: v_cmp_ngt_f16_e32 vcc_lo, m0, v2          ; encoding: [0x7d,0x04,0x16,0x7c]
+# W64: v_cmp_ngt_f16_e32 vcc, m0, v2             ; encoding: [0x7d,0x04,0x16,0x7c]
+0x7d,0x04,0x16,0x7c
+
+# W32: v_cmp_ngt_f16_e32 vcc_lo, exec_lo, v2     ; encoding: [0x7e,0x04,0x16,0x7c]
+# W64: v_cmp_ngt_f16_e32 vcc, exec_lo, v2        ; encoding: [0x7e,0x04,0x16,0x7c]
+0x7e,0x04,0x16,0x7c
+
+# W32: v_cmp_ngt_f16_e32 vcc_lo, exec_hi, v2     ; encoding: [0x7f,0x04,0x16,0x7c]
+# W64: v_cmp_ngt_f16_e32 vcc, exec_hi, v2        ; encoding: [0x7f,0x04,0x16,0x7c]
+0x7f,0x04,0x16,0x7c
+
+# W32: v_cmp_ngt_f16_e32 vcc_lo, null, v2        ; encoding: [0x7c,0x04,0x16,0x7c]
+# W64: v_cmp_ngt_f16_e32 vcc, null, v2           ; encoding: [0x7c,0x04,0x16,0x7c]
+0x7c,0x04,0x16,0x7c
+
+# W32: v_cmp_ngt_f16_e32 vcc_lo, -1, v2          ; encoding: [0xc1,0x04,0x16,0x7c]
+# W64: v_cmp_ngt_f16_e32 vcc, -1, v2             ; encoding: [0xc1,0x04,0x16,0x7c]
+0xc1,0x04,0x16,0x7c
+
+# W32: v_cmp_ngt_f16_e32 vcc_lo, 0.5, v2         ; encoding: [0xf0,0x04,0x16,0x7c]
+# W64: v_cmp_ngt_f16_e32 vcc, 0.5, v2            ; encoding: [0xf0,0x04,0x16,0x7c]
+0xf0,0x04,0x16,0x7c
+
+# W32: v_cmp_ngt_f16_e32 vcc_lo, src_scc, v2     ; encoding: [0xfd,0x04,0x16,0x7c]
+# W64: v_cmp_ngt_f16_e32 vcc, src_scc, v2        ; encoding: [0xfd,0x04,0x16,0x7c]
+0xfd,0x04,0x16,0x7c
+
+# W32: v_cmp_ngt_f16_e32 vcc_lo, 0xfe0b, v127    ; encoding: [0xff,0xfe,0x16,0x7c,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_ngt_f16_e32 vcc, 0xfe0b, v127       ; encoding: [0xff,0xfe,0x16,0x7c,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x16,0x7c,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_ngt_f32_e32 vcc_lo, v1, v2          ; encoding: [0x01,0x05,0x36,0x7c]
+# W64: v_cmp_ngt_f32_e32 vcc, v1, v2             ; encoding: [0x01,0x05,0x36,0x7c]
+0x01,0x05,0x36,0x7c
+
+# W32: v_cmp_ngt_f32_e32 vcc_lo, v255, v2        ; encoding: [0xff,0x05,0x36,0x7c]
+# W64: v_cmp_ngt_f32_e32 vcc, v255, v2           ; encoding: [0xff,0x05,0x36,0x7c]
+0xff,0x05,0x36,0x7c
+
+# W32: v_cmp_ngt_f32_e32 vcc_lo, s1, v2          ; encoding: [0x01,0x04,0x36,0x7c]
+# W64: v_cmp_ngt_f32_e32 vcc, s1, v2             ; encoding: [0x01,0x04,0x36,0x7c]
+0x01,0x04,0x36,0x7c
+
+# W32: v_cmp_ngt_f32_e32 vcc_lo, s105, v2        ; encoding: [0x69,0x04,0x36,0x7c]
+# W64: v_cmp_ngt_f32_e32 vcc, s105, v2           ; encoding: [0x69,0x04,0x36,0x7c]
+0x69,0x04,0x36,0x7c
+
+# W32: v_cmp_ngt_f32_e32 vcc_lo, vcc_lo, v2      ; encoding: [0x6a,0x04,0x36,0x7c]
+# W64: v_cmp_ngt_f32_e32 vcc, vcc_lo, v2         ; encoding: [0x6a,0x04,0x36,0x7c]
+0x6a,0x04,0x36,0x7c
+
+# W32: v_cmp_ngt_f32_e32 vcc_lo, vcc_hi, v2      ; encoding: [0x6b,0x04,0x36,0x7c]
+# W64: v_cmp_ngt_f32_e32 vcc, vcc_hi, v2         ; encoding: [0x6b,0x04,0x36,0x7c]
+0x6b,0x04,0x36,0x7c
+
+# W32: v_cmp_ngt_f32_e32 vcc_lo, ttmp15, v2      ; encoding: [0x7b,0x04,0x36,0x7c]
+# W64: v_cmp_ngt_f32_e32 vcc, ttmp15, v2         ; encoding: [0x7b,0x04,0x36,0x7c]
+0x7b,0x04,0x36,0x7c
+
+# W32: v_cmp_ngt_f32_e32 vcc_lo, m0, v2          ; encoding: [0x7d,0x04,0x36,0x7c]
+# W64: v_cmp_ngt_f32_e32 vcc, m0, v2             ; encoding: [0x7d,0x04,0x36,0x7c]
+0x7d,0x04,0x36,0x7c
+
+# W32: v_cmp_ngt_f32_e32 vcc_lo, exec_lo, v2     ; encoding: [0x7e,0x04,0x36,0x7c]
+# W64: v_cmp_ngt_f32_e32 vcc, exec_lo, v2        ; encoding: [0x7e,0x04,0x36,0x7c]
+0x7e,0x04,0x36,0x7c
+
+# W32: v_cmp_ngt_f32_e32 vcc_lo, exec_hi, v2     ; encoding: [0x7f,0x04,0x36,0x7c]
+# W64: v_cmp_ngt_f32_e32 vcc, exec_hi, v2        ; encoding: [0x7f,0x04,0x36,0x7c]
+0x7f,0x04,0x36,0x7c
+
+# W32: v_cmp_ngt_f32_e32 vcc_lo, null, v2        ; encoding: [0x7c,0x04,0x36,0x7c]
+# W64: v_cmp_ngt_f32_e32 vcc, null, v2           ; encoding: [0x7c,0x04,0x36,0x7c]
+0x7c,0x04,0x36,0x7c
+
+# W32: v_cmp_ngt_f32_e32 vcc_lo, -1, v2          ; encoding: [0xc1,0x04,0x36,0x7c]
+# W64: v_cmp_ngt_f32_e32 vcc, -1, v2             ; encoding: [0xc1,0x04,0x36,0x7c]
+0xc1,0x04,0x36,0x7c
+
+# W32: v_cmp_ngt_f32_e32 vcc_lo, 0.5, v2         ; encoding: [0xf0,0x04,0x36,0x7c]
+# W64: v_cmp_ngt_f32_e32 vcc, 0.5, v2            ; encoding: [0xf0,0x04,0x36,0x7c]
+0xf0,0x04,0x36,0x7c
+
+# W32: v_cmp_ngt_f32_e32 vcc_lo, src_scc, v2     ; encoding: [0xfd,0x04,0x36,0x7c]
+# W64: v_cmp_ngt_f32_e32 vcc, src_scc, v2        ; encoding: [0xfd,0x04,0x36,0x7c]
+0xfd,0x04,0x36,0x7c
+
+# W32: v_cmp_ngt_f32_e32 vcc_lo, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x37,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_ngt_f32_e32 vcc, 0xaf123456, v255   ; encoding: [0xff,0xfe,0x37,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x37,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_ngt_f64_e32 vcc_lo, v[1:2], v[2:3]  ; encoding: [0x01,0x05,0x56,0x7c]
+# W64: v_cmp_ngt_f64_e32 vcc, v[1:2], v[2:3]     ; encoding: [0x01,0x05,0x56,0x7c]
+0x01,0x05,0x56,0x7c
+
+# W32: v_cmp_ngt_f64_e32 vcc_lo, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x56,0x7c]
+# W64: v_cmp_ngt_f64_e32 vcc, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x56,0x7c]
+0xfe,0x05,0x56,0x7c
+
+# W32: v_cmp_ngt_f64_e32 vcc_lo, s[2:3], v[2:3]  ; encoding: [0x02,0x04,0x56,0x7c]
+# W64: v_cmp_ngt_f64_e32 vcc, s[2:3], v[2:3]     ; encoding: [0x02,0x04,0x56,0x7c]
+0x02,0x04,0x56,0x7c
+
+# W32: v_cmp_ngt_f64_e32 vcc_lo, s[104:105], v[2:3] ; encoding: [0x68,0x04,0x56,0x7c]
+# W64: v_cmp_ngt_f64_e32 vcc, s[104:105], v[2:3] ; encoding: [0x68,0x04,0x56,0x7c]
+0x68,0x04,0x56,0x7c
+
+# W32: v_cmp_ngt_f64_e32 vcc_lo, vcc, v[2:3]     ; encoding: [0x6a,0x04,0x56,0x7c]
+# W64: v_cmp_ngt_f64_e32 vcc, vcc, v[2:3]        ; encoding: [0x6a,0x04,0x56,0x7c]
+0x6a,0x04,0x56,0x7c
+
+# W32: v_cmp_ngt_f64_e32 vcc_lo, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x56,0x7c]
+# W64: v_cmp_ngt_f64_e32 vcc, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x56,0x7c]
+0x7a,0x04,0x56,0x7c
+
+# W32: v_cmp_ngt_f64_e32 vcc_lo, exec, v[2:3]    ; encoding: [0x7e,0x04,0x56,0x7c]
+# W64: v_cmp_ngt_f64_e32 vcc, exec, v[2:3]       ; encoding: [0x7e,0x04,0x56,0x7c]
+0x7e,0x04,0x56,0x7c
+
+# W32: v_cmp_ngt_f64_e32 vcc_lo, null, v[2:3]    ; encoding: [0x7c,0x04,0x56,0x7c]
+# W64: v_cmp_ngt_f64_e32 vcc, null, v[2:3]       ; encoding: [0x7c,0x04,0x56,0x7c]
+0x7c,0x04,0x56,0x7c
+
+# W32: v_cmp_ngt_f64_e32 vcc_lo, -1, v[2:3]      ; encoding: [0xc1,0x04,0x56,0x7c]
+# W64: v_cmp_ngt_f64_e32 vcc, -1, v[2:3]         ; encoding: [0xc1,0x04,0x56,0x7c]
+0xc1,0x04,0x56,0x7c
+
+# W32: v_cmp_ngt_f64_e32 vcc_lo, 0.5, v[2:3]     ; encoding: [0xf0,0x04,0x56,0x7c]
+# W64: v_cmp_ngt_f64_e32 vcc, 0.5, v[2:3]        ; encoding: [0xf0,0x04,0x56,0x7c]
+0xf0,0x04,0x56,0x7c
+
+# W32: v_cmp_ngt_f64_e32 vcc_lo, src_scc, v[2:3] ; encoding: [0xfd,0x04,0x56,0x7c]
+# W64: v_cmp_ngt_f64_e32 vcc, src_scc, v[2:3]    ; encoding: [0xfd,0x04,0x56,0x7c]
+0xfd,0x04,0x56,0x7c
+
+# W32: v_cmp_ngt_f64_e32 vcc_lo, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x57,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_ngt_f64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x57,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x57,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_nle_f16_e32 vcc_lo, v1, v2          ; encoding: [0x01,0x05,0x18,0x7c]
+# W64: v_cmp_nle_f16_e32 vcc, v1, v2             ; encoding: [0x01,0x05,0x18,0x7c]
+0x01,0x05,0x18,0x7c
+
+# W32: v_cmp_nle_f16_e32 vcc_lo, v127, v2        ; encoding: [0x7f,0x05,0x18,0x7c]
+# W64: v_cmp_nle_f16_e32 vcc, v127, v2           ; encoding: [0x7f,0x05,0x18,0x7c]
+0x7f,0x05,0x18,0x7c
+
+# W32: v_cmp_nle_f16_e32 vcc_lo, s1, v2          ; encoding: [0x01,0x04,0x18,0x7c]
+# W64: v_cmp_nle_f16_e32 vcc, s1, v2             ; encoding: [0x01,0x04,0x18,0x7c]
+0x01,0x04,0x18,0x7c
+
+# W32: v_cmp_nle_f16_e32 vcc_lo, s105, v2        ; encoding: [0x69,0x04,0x18,0x7c]
+# W64: v_cmp_nle_f16_e32 vcc, s105, v2           ; encoding: [0x69,0x04,0x18,0x7c]
+0x69,0x04,0x18,0x7c
+
+# W32: v_cmp_nle_f16_e32 vcc_lo, vcc_lo, v2      ; encoding: [0x6a,0x04,0x18,0x7c]
+# W64: v_cmp_nle_f16_e32 vcc, vcc_lo, v2         ; encoding: [0x6a,0x04,0x18,0x7c]
+0x6a,0x04,0x18,0x7c
+
+# W32: v_cmp_nle_f16_e32 vcc_lo, vcc_hi, v2      ; encoding: [0x6b,0x04,0x18,0x7c]
+# W64: v_cmp_nle_f16_e32 vcc, vcc_hi, v2         ; encoding: [0x6b,0x04,0x18,0x7c]
+0x6b,0x04,0x18,0x7c
+
+# W32: v_cmp_nle_f16_e32 vcc_lo, ttmp15, v2      ; encoding: [0x7b,0x04,0x18,0x7c]
+# W64: v_cmp_nle_f16_e32 vcc, ttmp15, v2         ; encoding: [0x7b,0x04,0x18,0x7c]
+0x7b,0x04,0x18,0x7c
+
+# W32: v_cmp_nle_f16_e32 vcc_lo, m0, v2          ; encoding: [0x7d,0x04,0x18,0x7c]
+# W64: v_cmp_nle_f16_e32 vcc, m0, v2             ; encoding: [0x7d,0x04,0x18,0x7c]
+0x7d,0x04,0x18,0x7c
+
+# W32: v_cmp_nle_f16_e32 vcc_lo, exec_lo, v2     ; encoding: [0x7e,0x04,0x18,0x7c]
+# W64: v_cmp_nle_f16_e32 vcc, exec_lo, v2        ; encoding: [0x7e,0x04,0x18,0x7c]
+0x7e,0x04,0x18,0x7c
+
+# W32: v_cmp_nle_f16_e32 vcc_lo, exec_hi, v2     ; encoding: [0x7f,0x04,0x18,0x7c]
+# W64: v_cmp_nle_f16_e32 vcc, exec_hi, v2        ; encoding: [0x7f,0x04,0x18,0x7c]
+0x7f,0x04,0x18,0x7c
+
+# W32: v_cmp_nle_f16_e32 vcc_lo, null, v2        ; encoding: [0x7c,0x04,0x18,0x7c]
+# W64: v_cmp_nle_f16_e32 vcc, null, v2           ; encoding: [0x7c,0x04,0x18,0x7c]
+0x7c,0x04,0x18,0x7c
+
+# W32: v_cmp_nle_f16_e32 vcc_lo, -1, v2          ; encoding: [0xc1,0x04,0x18,0x7c]
+# W64: v_cmp_nle_f16_e32 vcc, -1, v2             ; encoding: [0xc1,0x04,0x18,0x7c]
+0xc1,0x04,0x18,0x7c
+
+# W32: v_cmp_nle_f16_e32 vcc_lo, 0.5, v2         ; encoding: [0xf0,0x04,0x18,0x7c]
+# W64: v_cmp_nle_f16_e32 vcc, 0.5, v2            ; encoding: [0xf0,0x04,0x18,0x7c]
+0xf0,0x04,0x18,0x7c
+
+# W32: v_cmp_nle_f16_e32 vcc_lo, src_scc, v2     ; encoding: [0xfd,0x04,0x18,0x7c]
+# W64: v_cmp_nle_f16_e32 vcc, src_scc, v2        ; encoding: [0xfd,0x04,0x18,0x7c]
+0xfd,0x04,0x18,0x7c
+
+# W32: v_cmp_nle_f16_e32 vcc_lo, 0xfe0b, v127    ; encoding: [0xff,0xfe,0x18,0x7c,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_nle_f16_e32 vcc, 0xfe0b, v127       ; encoding: [0xff,0xfe,0x18,0x7c,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x18,0x7c,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_nle_f32_e32 vcc_lo, v1, v2          ; encoding: [0x01,0x05,0x38,0x7c]
+# W64: v_cmp_nle_f32_e32 vcc, v1, v2             ; encoding: [0x01,0x05,0x38,0x7c]
+0x01,0x05,0x38,0x7c
+
+# W32: v_cmp_nle_f32_e32 vcc_lo, v255, v2        ; encoding: [0xff,0x05,0x38,0x7c]
+# W64: v_cmp_nle_f32_e32 vcc, v255, v2           ; encoding: [0xff,0x05,0x38,0x7c]
+0xff,0x05,0x38,0x7c
+
+# W32: v_cmp_nle_f32_e32 vcc_lo, s1, v2          ; encoding: [0x01,0x04,0x38,0x7c]
+# W64: v_cmp_nle_f32_e32 vcc, s1, v2             ; encoding: [0x01,0x04,0x38,0x7c]
+0x01,0x04,0x38,0x7c
+
+# W32: v_cmp_nle_f32_e32 vcc_lo, s105, v2        ; encoding: [0x69,0x04,0x38,0x7c]
+# W64: v_cmp_nle_f32_e32 vcc, s105, v2           ; encoding: [0x69,0x04,0x38,0x7c]
+0x69,0x04,0x38,0x7c
+
+# W32: v_cmp_nle_f32_e32 vcc_lo, vcc_lo, v2      ; encoding: [0x6a,0x04,0x38,0x7c]
+# W64: v_cmp_nle_f32_e32 vcc, vcc_lo, v2         ; encoding: [0x6a,0x04,0x38,0x7c]
+0x6a,0x04,0x38,0x7c
+
+# W32: v_cmp_nle_f32_e32 vcc_lo, vcc_hi, v2      ; encoding: [0x6b,0x04,0x38,0x7c]
+# W64: v_cmp_nle_f32_e32 vcc, vcc_hi, v2         ; encoding: [0x6b,0x04,0x38,0x7c]
+0x6b,0x04,0x38,0x7c
+
+# W32: v_cmp_nle_f32_e32 vcc_lo, ttmp15, v2      ; encoding: [0x7b,0x04,0x38,0x7c]
+# W64: v_cmp_nle_f32_e32 vcc, ttmp15, v2         ; encoding: [0x7b,0x04,0x38,0x7c]
+0x7b,0x04,0x38,0x7c
+
+# W32: v_cmp_nle_f32_e32 vcc_lo, m0, v2          ; encoding: [0x7d,0x04,0x38,0x7c]
+# W64: v_cmp_nle_f32_e32 vcc, m0, v2             ; encoding: [0x7d,0x04,0x38,0x7c]
+0x7d,0x04,0x38,0x7c
+
+# W32: v_cmp_nle_f32_e32 vcc_lo, exec_lo, v2     ; encoding: [0x7e,0x04,0x38,0x7c]
+# W64: v_cmp_nle_f32_e32 vcc, exec_lo, v2        ; encoding: [0x7e,0x04,0x38,0x7c]
+0x7e,0x04,0x38,0x7c
+
+# W32: v_cmp_nle_f32_e32 vcc_lo, exec_hi, v2     ; encoding: [0x7f,0x04,0x38,0x7c]
+# W64: v_cmp_nle_f32_e32 vcc, exec_hi, v2        ; encoding: [0x7f,0x04,0x38,0x7c]
+0x7f,0x04,0x38,0x7c
+
+# W32: v_cmp_nle_f32_e32 vcc_lo, null, v2        ; encoding: [0x7c,0x04,0x38,0x7c]
+# W64: v_cmp_nle_f32_e32 vcc, null, v2           ; encoding: [0x7c,0x04,0x38,0x7c]
+0x7c,0x04,0x38,0x7c
+
+# W32: v_cmp_nle_f32_e32 vcc_lo, -1, v2          ; encoding: [0xc1,0x04,0x38,0x7c]
+# W64: v_cmp_nle_f32_e32 vcc, -1, v2             ; encoding: [0xc1,0x04,0x38,0x7c]
+0xc1,0x04,0x38,0x7c
+
+# W32: v_cmp_nle_f32_e32 vcc_lo, 0.5, v2         ; encoding: [0xf0,0x04,0x38,0x7c]
+# W64: v_cmp_nle_f32_e32 vcc, 0.5, v2            ; encoding: [0xf0,0x04,0x38,0x7c]
+0xf0,0x04,0x38,0x7c
+
+# W32: v_cmp_nle_f32_e32 vcc_lo, src_scc, v2     ; encoding: [0xfd,0x04,0x38,0x7c]
+# W64: v_cmp_nle_f32_e32 vcc, src_scc, v2        ; encoding: [0xfd,0x04,0x38,0x7c]
+0xfd,0x04,0x38,0x7c
+
+# W32: v_cmp_nle_f32_e32 vcc_lo, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x39,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_nle_f32_e32 vcc, 0xaf123456, v255   ; encoding: [0xff,0xfe,0x39,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x39,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_nle_f64_e32 vcc_lo, v[1:2], v[2:3]  ; encoding: [0x01,0x05,0x58,0x7c]
+# W64: v_cmp_nle_f64_e32 vcc, v[1:2], v[2:3]     ; encoding: [0x01,0x05,0x58,0x7c]
+0x01,0x05,0x58,0x7c
+
+# W32: v_cmp_nle_f64_e32 vcc_lo, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x58,0x7c]
+# W64: v_cmp_nle_f64_e32 vcc, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x58,0x7c]
+0xfe,0x05,0x58,0x7c
+
+# W32: v_cmp_nle_f64_e32 vcc_lo, s[2:3], v[2:3]  ; encoding: [0x02,0x04,0x58,0x7c]
+# W64: v_cmp_nle_f64_e32 vcc, s[2:3], v[2:3]     ; encoding: [0x02,0x04,0x58,0x7c]
+0x02,0x04,0x58,0x7c
+
+# W32: v_cmp_nle_f64_e32 vcc_lo, s[104:105], v[2:3] ; encoding: [0x68,0x04,0x58,0x7c]
+# W64: v_cmp_nle_f64_e32 vcc, s[104:105], v[2:3] ; encoding: [0x68,0x04,0x58,0x7c]
+0x68,0x04,0x58,0x7c
+
+# W32: v_cmp_nle_f64_e32 vcc_lo, vcc, v[2:3]     ; encoding: [0x6a,0x04,0x58,0x7c]
+# W64: v_cmp_nle_f64_e32 vcc, vcc, v[2:3]        ; encoding: [0x6a,0x04,0x58,0x7c]
+0x6a,0x04,0x58,0x7c
+
+# W32: v_cmp_nle_f64_e32 vcc_lo, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x58,0x7c]
+# W64: v_cmp_nle_f64_e32 vcc, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x58,0x7c]
+0x7a,0x04,0x58,0x7c
+
+# W32: v_cmp_nle_f64_e32 vcc_lo, exec, v[2:3]    ; encoding: [0x7e,0x04,0x58,0x7c]
+# W64: v_cmp_nle_f64_e32 vcc, exec, v[2:3]       ; encoding: [0x7e,0x04,0x58,0x7c]
+0x7e,0x04,0x58,0x7c
+
+# W32: v_cmp_nle_f64_e32 vcc_lo, null, v[2:3]    ; encoding: [0x7c,0x04,0x58,0x7c]
+# W64: v_cmp_nle_f64_e32 vcc, null, v[2:3]       ; encoding: [0x7c,0x04,0x58,0x7c]
+0x7c,0x04,0x58,0x7c
+
+# W32: v_cmp_nle_f64_e32 vcc_lo, -1, v[2:3]      ; encoding: [0xc1,0x04,0x58,0x7c]
+# W64: v_cmp_nle_f64_e32 vcc, -1, v[2:3]         ; encoding: [0xc1,0x04,0x58,0x7c]
+0xc1,0x04,0x58,0x7c
+
+# W32: v_cmp_nle_f64_e32 vcc_lo, 0.5, v[2:3]     ; encoding: [0xf0,0x04,0x58,0x7c]
+# W64: v_cmp_nle_f64_e32 vcc, 0.5, v[2:3]        ; encoding: [0xf0,0x04,0x58,0x7c]
+0xf0,0x04,0x58,0x7c
+
+# W32: v_cmp_nle_f64_e32 vcc_lo, src_scc, v[2:3] ; encoding: [0xfd,0x04,0x58,0x7c]
+# W64: v_cmp_nle_f64_e32 vcc, src_scc, v[2:3]    ; encoding: [0xfd,0x04,0x58,0x7c]
+0xfd,0x04,0x58,0x7c
+
+# W32: v_cmp_nle_f64_e32 vcc_lo, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x59,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_nle_f64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x59,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x59,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_nlg_f16_e32 vcc_lo, v1, v2          ; encoding: [0x01,0x05,0x14,0x7c]
+# W64: v_cmp_nlg_f16_e32 vcc, v1, v2             ; encoding: [0x01,0x05,0x14,0x7c]
+0x01,0x05,0x14,0x7c
+
+# W32: v_cmp_nlg_f16_e32 vcc_lo, v127, v2        ; encoding: [0x7f,0x05,0x14,0x7c]
+# W64: v_cmp_nlg_f16_e32 vcc, v127, v2           ; encoding: [0x7f,0x05,0x14,0x7c]
+0x7f,0x05,0x14,0x7c
+
+# W32: v_cmp_nlg_f16_e32 vcc_lo, s1, v2          ; encoding: [0x01,0x04,0x14,0x7c]
+# W64: v_cmp_nlg_f16_e32 vcc, s1, v2             ; encoding: [0x01,0x04,0x14,0x7c]
+0x01,0x04,0x14,0x7c
+
+# W32: v_cmp_nlg_f16_e32 vcc_lo, s105, v2        ; encoding: [0x69,0x04,0x14,0x7c]
+# W64: v_cmp_nlg_f16_e32 vcc, s105, v2           ; encoding: [0x69,0x04,0x14,0x7c]
+0x69,0x04,0x14,0x7c
+
+# W32: v_cmp_nlg_f16_e32 vcc_lo, vcc_lo, v2      ; encoding: [0x6a,0x04,0x14,0x7c]
+# W64: v_cmp_nlg_f16_e32 vcc, vcc_lo, v2         ; encoding: [0x6a,0x04,0x14,0x7c]
+0x6a,0x04,0x14,0x7c
+
+# W32: v_cmp_nlg_f16_e32 vcc_lo, vcc_hi, v2      ; encoding: [0x6b,0x04,0x14,0x7c]
+# W64: v_cmp_nlg_f16_e32 vcc, vcc_hi, v2         ; encoding: [0x6b,0x04,0x14,0x7c]
+0x6b,0x04,0x14,0x7c
+
+# W32: v_cmp_nlg_f16_e32 vcc_lo, ttmp15, v2      ; encoding: [0x7b,0x04,0x14,0x7c]
+# W64: v_cmp_nlg_f16_e32 vcc, ttmp15, v2         ; encoding: [0x7b,0x04,0x14,0x7c]
+0x7b,0x04,0x14,0x7c
+
+# W32: v_cmp_nlg_f16_e32 vcc_lo, m0, v2          ; encoding: [0x7d,0x04,0x14,0x7c]
+# W64: v_cmp_nlg_f16_e32 vcc, m0, v2             ; encoding: [0x7d,0x04,0x14,0x7c]
+0x7d,0x04,0x14,0x7c
+
+# W32: v_cmp_nlg_f16_e32 vcc_lo, exec_lo, v2     ; encoding: [0x7e,0x04,0x14,0x7c]
+# W64: v_cmp_nlg_f16_e32 vcc, exec_lo, v2        ; encoding: [0x7e,0x04,0x14,0x7c]
+0x7e,0x04,0x14,0x7c
+
+# W32: v_cmp_nlg_f16_e32 vcc_lo, exec_hi, v2     ; encoding: [0x7f,0x04,0x14,0x7c]
+# W64: v_cmp_nlg_f16_e32 vcc, exec_hi, v2        ; encoding: [0x7f,0x04,0x14,0x7c]
+0x7f,0x04,0x14,0x7c
+
+# W32: v_cmp_nlg_f16_e32 vcc_lo, null, v2        ; encoding: [0x7c,0x04,0x14,0x7c]
+# W64: v_cmp_nlg_f16_e32 vcc, null, v2           ; encoding: [0x7c,0x04,0x14,0x7c]
+0x7c,0x04,0x14,0x7c
+
+# W32: v_cmp_nlg_f16_e32 vcc_lo, -1, v2          ; encoding: [0xc1,0x04,0x14,0x7c]
+# W64: v_cmp_nlg_f16_e32 vcc, -1, v2             ; encoding: [0xc1,0x04,0x14,0x7c]
+0xc1,0x04,0x14,0x7c
+
+# W32: v_cmp_nlg_f16_e32 vcc_lo, 0.5, v2         ; encoding: [0xf0,0x04,0x14,0x7c]
+# W64: v_cmp_nlg_f16_e32 vcc, 0.5, v2            ; encoding: [0xf0,0x04,0x14,0x7c]
+0xf0,0x04,0x14,0x7c
+
+# W32: v_cmp_nlg_f16_e32 vcc_lo, src_scc, v2     ; encoding: [0xfd,0x04,0x14,0x7c]
+# W64: v_cmp_nlg_f16_e32 vcc, src_scc, v2        ; encoding: [0xfd,0x04,0x14,0x7c]
+0xfd,0x04,0x14,0x7c
+
+# W32: v_cmp_nlg_f16_e32 vcc_lo, 0xfe0b, v127    ; encoding: [0xff,0xfe,0x14,0x7c,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_nlg_f16_e32 vcc, 0xfe0b, v127       ; encoding: [0xff,0xfe,0x14,0x7c,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x14,0x7c,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_nlg_f32_e32 vcc_lo, v1, v2          ; encoding: [0x01,0x05,0x34,0x7c]
+# W64: v_cmp_nlg_f32_e32 vcc, v1, v2             ; encoding: [0x01,0x05,0x34,0x7c]
+0x01,0x05,0x34,0x7c
+
+# W32: v_cmp_nlg_f32_e32 vcc_lo, v255, v2        ; encoding: [0xff,0x05,0x34,0x7c]
+# W64: v_cmp_nlg_f32_e32 vcc, v255, v2           ; encoding: [0xff,0x05,0x34,0x7c]
+0xff,0x05,0x34,0x7c
+
+# W32: v_cmp_nlg_f32_e32 vcc_lo, s1, v2          ; encoding: [0x01,0x04,0x34,0x7c]
+# W64: v_cmp_nlg_f32_e32 vcc, s1, v2             ; encoding: [0x01,0x04,0x34,0x7c]
+0x01,0x04,0x34,0x7c
+
+# W32: v_cmp_nlg_f32_e32 vcc_lo, s105, v2        ; encoding: [0x69,0x04,0x34,0x7c]
+# W64: v_cmp_nlg_f32_e32 vcc, s105, v2           ; encoding: [0x69,0x04,0x34,0x7c]
+0x69,0x04,0x34,0x7c
+
+# W32: v_cmp_nlg_f32_e32 vcc_lo, vcc_lo, v2      ; encoding: [0x6a,0x04,0x34,0x7c]
+# W64: v_cmp_nlg_f32_e32 vcc, vcc_lo, v2         ; encoding: [0x6a,0x04,0x34,0x7c]
+0x6a,0x04,0x34,0x7c
+
+# W32: v_cmp_nlg_f32_e32 vcc_lo, vcc_hi, v2      ; encoding: [0x6b,0x04,0x34,0x7c]
+# W64: v_cmp_nlg_f32_e32 vcc, vcc_hi, v2         ; encoding: [0x6b,0x04,0x34,0x7c]
+0x6b,0x04,0x34,0x7c
+
+# W32: v_cmp_nlg_f32_e32 vcc_lo, ttmp15, v2      ; encoding: [0x7b,0x04,0x34,0x7c]
+# W64: v_cmp_nlg_f32_e32 vcc, ttmp15, v2         ; encoding: [0x7b,0x04,0x34,0x7c]
+0x7b,0x04,0x34,0x7c
+
+# W32: v_cmp_nlg_f32_e32 vcc_lo, m0, v2          ; encoding: [0x7d,0x04,0x34,0x7c]
+# W64: v_cmp_nlg_f32_e32 vcc, m0, v2             ; encoding: [0x7d,0x04,0x34,0x7c]
+0x7d,0x04,0x34,0x7c
+
+# W32: v_cmp_nlg_f32_e32 vcc_lo, exec_lo, v2     ; encoding: [0x7e,0x04,0x34,0x7c]
+# W64: v_cmp_nlg_f32_e32 vcc, exec_lo, v2        ; encoding: [0x7e,0x04,0x34,0x7c]
+0x7e,0x04,0x34,0x7c
+
+# W32: v_cmp_nlg_f32_e32 vcc_lo, exec_hi, v2     ; encoding: [0x7f,0x04,0x34,0x7c]
+# W64: v_cmp_nlg_f32_e32 vcc, exec_hi, v2        ; encoding: [0x7f,0x04,0x34,0x7c]
+0x7f,0x04,0x34,0x7c
+
+# W32: v_cmp_nlg_f32_e32 vcc_lo, null, v2        ; encoding: [0x7c,0x04,0x34,0x7c]
+# W64: v_cmp_nlg_f32_e32 vcc, null, v2           ; encoding: [0x7c,0x04,0x34,0x7c]
+0x7c,0x04,0x34,0x7c
+
+# W32: v_cmp_nlg_f32_e32 vcc_lo, -1, v2          ; encoding: [0xc1,0x04,0x34,0x7c]
+# W64: v_cmp_nlg_f32_e32 vcc, -1, v2             ; encoding: [0xc1,0x04,0x34,0x7c]
+0xc1,0x04,0x34,0x7c
+
+# W32: v_cmp_nlg_f32_e32 vcc_lo, 0.5, v2         ; encoding: [0xf0,0x04,0x34,0x7c]
+# W64: v_cmp_nlg_f32_e32 vcc, 0.5, v2            ; encoding: [0xf0,0x04,0x34,0x7c]
+0xf0,0x04,0x34,0x7c
+
+# W32: v_cmp_nlg_f32_e32 vcc_lo, src_scc, v2     ; encoding: [0xfd,0x04,0x34,0x7c]
+# W64: v_cmp_nlg_f32_e32 vcc, src_scc, v2        ; encoding: [0xfd,0x04,0x34,0x7c]
+0xfd,0x04,0x34,0x7c
+
+# W32: v_cmp_nlg_f32_e32 vcc_lo, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x35,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_nlg_f32_e32 vcc, 0xaf123456, v255   ; encoding: [0xff,0xfe,0x35,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x35,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_nlg_f64_e32 vcc_lo, v[1:2], v[2:3]  ; encoding: [0x01,0x05,0x54,0x7c]
+# W64: v_cmp_nlg_f64_e32 vcc, v[1:2], v[2:3]     ; encoding: [0x01,0x05,0x54,0x7c]
+0x01,0x05,0x54,0x7c
+
+# W32: v_cmp_nlg_f64_e32 vcc_lo, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x54,0x7c]
+# W64: v_cmp_nlg_f64_e32 vcc, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x54,0x7c]
+0xfe,0x05,0x54,0x7c
+
+# W32: v_cmp_nlg_f64_e32 vcc_lo, s[2:3], v[2:3]  ; encoding: [0x02,0x04,0x54,0x7c]
+# W64: v_cmp_nlg_f64_e32 vcc, s[2:3], v[2:3]     ; encoding: [0x02,0x04,0x54,0x7c]
+0x02,0x04,0x54,0x7c
+
+# W32: v_cmp_nlg_f64_e32 vcc_lo, s[104:105], v[2:3] ; encoding: [0x68,0x04,0x54,0x7c]
+# W64: v_cmp_nlg_f64_e32 vcc, s[104:105], v[2:3] ; encoding: [0x68,0x04,0x54,0x7c]
+0x68,0x04,0x54,0x7c
+
+# W32: v_cmp_nlg_f64_e32 vcc_lo, vcc, v[2:3]     ; encoding: [0x6a,0x04,0x54,0x7c]
+# W64: v_cmp_nlg_f64_e32 vcc, vcc, v[2:3]        ; encoding: [0x6a,0x04,0x54,0x7c]
+0x6a,0x04,0x54,0x7c
+
+# W32: v_cmp_nlg_f64_e32 vcc_lo, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x54,0x7c]
+# W64: v_cmp_nlg_f64_e32 vcc, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x54,0x7c]
+0x7a,0x04,0x54,0x7c
+
+# W32: v_cmp_nlg_f64_e32 vcc_lo, exec, v[2:3]    ; encoding: [0x7e,0x04,0x54,0x7c]
+# W64: v_cmp_nlg_f64_e32 vcc, exec, v[2:3]       ; encoding: [0x7e,0x04,0x54,0x7c]
+0x7e,0x04,0x54,0x7c
+
+# W32: v_cmp_nlg_f64_e32 vcc_lo, null, v[2:3]    ; encoding: [0x7c,0x04,0x54,0x7c]
+# W64: v_cmp_nlg_f64_e32 vcc, null, v[2:3]       ; encoding: [0x7c,0x04,0x54,0x7c]
+0x7c,0x04,0x54,0x7c
+
+# W32: v_cmp_nlg_f64_e32 vcc_lo, -1, v[2:3]      ; encoding: [0xc1,0x04,0x54,0x7c]
+# W64: v_cmp_nlg_f64_e32 vcc, -1, v[2:3]         ; encoding: [0xc1,0x04,0x54,0x7c]
+0xc1,0x04,0x54,0x7c
+
+# W32: v_cmp_nlg_f64_e32 vcc_lo, 0.5, v[2:3]     ; encoding: [0xf0,0x04,0x54,0x7c]
+# W64: v_cmp_nlg_f64_e32 vcc, 0.5, v[2:3]        ; encoding: [0xf0,0x04,0x54,0x7c]
+0xf0,0x04,0x54,0x7c
+
+# W32: v_cmp_nlg_f64_e32 vcc_lo, src_scc, v[2:3] ; encoding: [0xfd,0x04,0x54,0x7c]
+# W64: v_cmp_nlg_f64_e32 vcc, src_scc, v[2:3]    ; encoding: [0xfd,0x04,0x54,0x7c]
+0xfd,0x04,0x54,0x7c
+
+# W32: v_cmp_nlg_f64_e32 vcc_lo, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x55,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_nlg_f64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x55,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x55,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_nlt_f16_e32 vcc_lo, v1, v2          ; encoding: [0x01,0x05,0x1c,0x7c]
+# W64: v_cmp_nlt_f16_e32 vcc, v1, v2             ; encoding: [0x01,0x05,0x1c,0x7c]
+0x01,0x05,0x1c,0x7c
+
+# W32: v_cmp_nlt_f16_e32 vcc_lo, v127, v2        ; encoding: [0x7f,0x05,0x1c,0x7c]
+# W64: v_cmp_nlt_f16_e32 vcc, v127, v2           ; encoding: [0x7f,0x05,0x1c,0x7c]
+0x7f,0x05,0x1c,0x7c
+
+# W32: v_cmp_nlt_f16_e32 vcc_lo, s1, v2          ; encoding: [0x01,0x04,0x1c,0x7c]
+# W64: v_cmp_nlt_f16_e32 vcc, s1, v2             ; encoding: [0x01,0x04,0x1c,0x7c]
+0x01,0x04,0x1c,0x7c
+
+# W32: v_cmp_nlt_f16_e32 vcc_lo, s105, v2        ; encoding: [0x69,0x04,0x1c,0x7c]
+# W64: v_cmp_nlt_f16_e32 vcc, s105, v2           ; encoding: [0x69,0x04,0x1c,0x7c]
+0x69,0x04,0x1c,0x7c
+
+# W32: v_cmp_nlt_f16_e32 vcc_lo, vcc_lo, v2      ; encoding: [0x6a,0x04,0x1c,0x7c]
+# W64: v_cmp_nlt_f16_e32 vcc, vcc_lo, v2         ; encoding: [0x6a,0x04,0x1c,0x7c]
+0x6a,0x04,0x1c,0x7c
+
+# W32: v_cmp_nlt_f16_e32 vcc_lo, vcc_hi, v2      ; encoding: [0x6b,0x04,0x1c,0x7c]
+# W64: v_cmp_nlt_f16_e32 vcc, vcc_hi, v2         ; encoding: [0x6b,0x04,0x1c,0x7c]
+0x6b,0x04,0x1c,0x7c
+
+# W32: v_cmp_nlt_f16_e32 vcc_lo, ttmp15, v2      ; encoding: [0x7b,0x04,0x1c,0x7c]
+# W64: v_cmp_nlt_f16_e32 vcc, ttmp15, v2         ; encoding: [0x7b,0x04,0x1c,0x7c]
+0x7b,0x04,0x1c,0x7c
+
+# W32: v_cmp_nlt_f16_e32 vcc_lo, m0, v2          ; encoding: [0x7d,0x04,0x1c,0x7c]
+# W64: v_cmp_nlt_f16_e32 vcc, m0, v2             ; encoding: [0x7d,0x04,0x1c,0x7c]
+0x7d,0x04,0x1c,0x7c
+
+# W32: v_cmp_nlt_f16_e32 vcc_lo, exec_lo, v2     ; encoding: [0x7e,0x04,0x1c,0x7c]
+# W64: v_cmp_nlt_f16_e32 vcc, exec_lo, v2        ; encoding: [0x7e,0x04,0x1c,0x7c]
+0x7e,0x04,0x1c,0x7c
+
+# W32: v_cmp_nlt_f16_e32 vcc_lo, exec_hi, v2     ; encoding: [0x7f,0x04,0x1c,0x7c]
+# W64: v_cmp_nlt_f16_e32 vcc, exec_hi, v2        ; encoding: [0x7f,0x04,0x1c,0x7c]
+0x7f,0x04,0x1c,0x7c
+
+# W32: v_cmp_nlt_f16_e32 vcc_lo, null, v2        ; encoding: [0x7c,0x04,0x1c,0x7c]
+# W64: v_cmp_nlt_f16_e32 vcc, null, v2           ; encoding: [0x7c,0x04,0x1c,0x7c]
+0x7c,0x04,0x1c,0x7c
+
+# W32: v_cmp_nlt_f16_e32 vcc_lo, -1, v2          ; encoding: [0xc1,0x04,0x1c,0x7c]
+# W64: v_cmp_nlt_f16_e32 vcc, -1, v2             ; encoding: [0xc1,0x04,0x1c,0x7c]
+0xc1,0x04,0x1c,0x7c
+
+# W32: v_cmp_nlt_f16_e32 vcc_lo, 0.5, v2         ; encoding: [0xf0,0x04,0x1c,0x7c]
+# W64: v_cmp_nlt_f16_e32 vcc, 0.5, v2            ; encoding: [0xf0,0x04,0x1c,0x7c]
+0xf0,0x04,0x1c,0x7c
+
+# W32: v_cmp_nlt_f16_e32 vcc_lo, src_scc, v2     ; encoding: [0xfd,0x04,0x1c,0x7c]
+# W64: v_cmp_nlt_f16_e32 vcc, src_scc, v2        ; encoding: [0xfd,0x04,0x1c,0x7c]
+0xfd,0x04,0x1c,0x7c
+
+# W32: v_cmp_nlt_f16_e32 vcc_lo, 0xfe0b, v127    ; encoding: [0xff,0xfe,0x1c,0x7c,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_nlt_f16_e32 vcc, 0xfe0b, v127       ; encoding: [0xff,0xfe,0x1c,0x7c,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x1c,0x7c,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_nlt_f32_e32 vcc_lo, v1, v2          ; encoding: [0x01,0x05,0x3c,0x7c]
+# W64: v_cmp_nlt_f32_e32 vcc, v1, v2             ; encoding: [0x01,0x05,0x3c,0x7c]
+0x01,0x05,0x3c,0x7c
+
+# W32: v_cmp_nlt_f32_e32 vcc_lo, v255, v2        ; encoding: [0xff,0x05,0x3c,0x7c]
+# W64: v_cmp_nlt_f32_e32 vcc, v255, v2           ; encoding: [0xff,0x05,0x3c,0x7c]
+0xff,0x05,0x3c,0x7c
+
+# W32: v_cmp_nlt_f32_e32 vcc_lo, s1, v2          ; encoding: [0x01,0x04,0x3c,0x7c]
+# W64: v_cmp_nlt_f32_e32 vcc, s1, v2             ; encoding: [0x01,0x04,0x3c,0x7c]
+0x01,0x04,0x3c,0x7c
+
+# W32: v_cmp_nlt_f32_e32 vcc_lo, s105, v2        ; encoding: [0x69,0x04,0x3c,0x7c]
+# W64: v_cmp_nlt_f32_e32 vcc, s105, v2           ; encoding: [0x69,0x04,0x3c,0x7c]
+0x69,0x04,0x3c,0x7c
+
+# W32: v_cmp_nlt_f32_e32 vcc_lo, vcc_lo, v2      ; encoding: [0x6a,0x04,0x3c,0x7c]
+# W64: v_cmp_nlt_f32_e32 vcc, vcc_lo, v2         ; encoding: [0x6a,0x04,0x3c,0x7c]
+0x6a,0x04,0x3c,0x7c
+
+# W32: v_cmp_nlt_f32_e32 vcc_lo, vcc_hi, v2      ; encoding: [0x6b,0x04,0x3c,0x7c]
+# W64: v_cmp_nlt_f32_e32 vcc, vcc_hi, v2         ; encoding: [0x6b,0x04,0x3c,0x7c]
+0x6b,0x04,0x3c,0x7c
+
+# W32: v_cmp_nlt_f32_e32 vcc_lo, ttmp15, v2      ; encoding: [0x7b,0x04,0x3c,0x7c]
+# W64: v_cmp_nlt_f32_e32 vcc, ttmp15, v2         ; encoding: [0x7b,0x04,0x3c,0x7c]
+0x7b,0x04,0x3c,0x7c
+
+# W32: v_cmp_nlt_f32_e32 vcc_lo, m0, v2          ; encoding: [0x7d,0x04,0x3c,0x7c]
+# W64: v_cmp_nlt_f32_e32 vcc, m0, v2             ; encoding: [0x7d,0x04,0x3c,0x7c]
+0x7d,0x04,0x3c,0x7c
+
+# W32: v_cmp_nlt_f32_e32 vcc_lo, exec_lo, v2     ; encoding: [0x7e,0x04,0x3c,0x7c]
+# W64: v_cmp_nlt_f32_e32 vcc, exec_lo, v2        ; encoding: [0x7e,0x04,0x3c,0x7c]
+0x7e,0x04,0x3c,0x7c
+
+# W32: v_cmp_nlt_f32_e32 vcc_lo, exec_hi, v2     ; encoding: [0x7f,0x04,0x3c,0x7c]
+# W64: v_cmp_nlt_f32_e32 vcc, exec_hi, v2        ; encoding: [0x7f,0x04,0x3c,0x7c]
+0x7f,0x04,0x3c,0x7c
+
+# W32: v_cmp_nlt_f32_e32 vcc_lo, null, v2        ; encoding: [0x7c,0x04,0x3c,0x7c]
+# W64: v_cmp_nlt_f32_e32 vcc, null, v2           ; encoding: [0x7c,0x04,0x3c,0x7c]
+0x7c,0x04,0x3c,0x7c
+
+# W32: v_cmp_nlt_f32_e32 vcc_lo, -1, v2          ; encoding: [0xc1,0x04,0x3c,0x7c]
+# W64: v_cmp_nlt_f32_e32 vcc, -1, v2             ; encoding: [0xc1,0x04,0x3c,0x7c]
+0xc1,0x04,0x3c,0x7c
+
+# W32: v_cmp_nlt_f32_e32 vcc_lo, 0.5, v2         ; encoding: [0xf0,0x04,0x3c,0x7c]
+# W64: v_cmp_nlt_f32_e32 vcc, 0.5, v2            ; encoding: [0xf0,0x04,0x3c,0x7c]
+0xf0,0x04,0x3c,0x7c
+
+# W32: v_cmp_nlt_f32_e32 vcc_lo, src_scc, v2     ; encoding: [0xfd,0x04,0x3c,0x7c]
+# W64: v_cmp_nlt_f32_e32 vcc, src_scc, v2        ; encoding: [0xfd,0x04,0x3c,0x7c]
+0xfd,0x04,0x3c,0x7c
+
+# W32: v_cmp_nlt_f32_e32 vcc_lo, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x3d,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_nlt_f32_e32 vcc, 0xaf123456, v255   ; encoding: [0xff,0xfe,0x3d,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x3d,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_nlt_f64_e32 vcc_lo, v[1:2], v[2:3]  ; encoding: [0x01,0x05,0x5c,0x7c]
+# W64: v_cmp_nlt_f64_e32 vcc, v[1:2], v[2:3]     ; encoding: [0x01,0x05,0x5c,0x7c]
+0x01,0x05,0x5c,0x7c
+
+# W32: v_cmp_nlt_f64_e32 vcc_lo, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x5c,0x7c]
+# W64: v_cmp_nlt_f64_e32 vcc, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x5c,0x7c]
+0xfe,0x05,0x5c,0x7c
+
+# W32: v_cmp_nlt_f64_e32 vcc_lo, s[2:3], v[2:3]  ; encoding: [0x02,0x04,0x5c,0x7c]
+# W64: v_cmp_nlt_f64_e32 vcc, s[2:3], v[2:3]     ; encoding: [0x02,0x04,0x5c,0x7c]
+0x02,0x04,0x5c,0x7c
+
+# W32: v_cmp_nlt_f64_e32 vcc_lo, s[104:105], v[2:3] ; encoding: [0x68,0x04,0x5c,0x7c]
+# W64: v_cmp_nlt_f64_e32 vcc, s[104:105], v[2:3] ; encoding: [0x68,0x04,0x5c,0x7c]
+0x68,0x04,0x5c,0x7c
+
+# W32: v_cmp_nlt_f64_e32 vcc_lo, vcc, v[2:3]     ; encoding: [0x6a,0x04,0x5c,0x7c]
+# W64: v_cmp_nlt_f64_e32 vcc, vcc, v[2:3]        ; encoding: [0x6a,0x04,0x5c,0x7c]
+0x6a,0x04,0x5c,0x7c
+
+# W32: v_cmp_nlt_f64_e32 vcc_lo, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x5c,0x7c]
+# W64: v_cmp_nlt_f64_e32 vcc, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x5c,0x7c]
+0x7a,0x04,0x5c,0x7c
+
+# W32: v_cmp_nlt_f64_e32 vcc_lo, exec, v[2:3]    ; encoding: [0x7e,0x04,0x5c,0x7c]
+# W64: v_cmp_nlt_f64_e32 vcc, exec, v[2:3]       ; encoding: [0x7e,0x04,0x5c,0x7c]
+0x7e,0x04,0x5c,0x7c
+
+# W32: v_cmp_nlt_f64_e32 vcc_lo, null, v[2:3]    ; encoding: [0x7c,0x04,0x5c,0x7c]
+# W64: v_cmp_nlt_f64_e32 vcc, null, v[2:3]       ; encoding: [0x7c,0x04,0x5c,0x7c]
+0x7c,0x04,0x5c,0x7c
+
+# W32: v_cmp_nlt_f64_e32 vcc_lo, -1, v[2:3]      ; encoding: [0xc1,0x04,0x5c,0x7c]
+# W64: v_cmp_nlt_f64_e32 vcc, -1, v[2:3]         ; encoding: [0xc1,0x04,0x5c,0x7c]
+0xc1,0x04,0x5c,0x7c
+
+# W32: v_cmp_nlt_f64_e32 vcc_lo, 0.5, v[2:3]     ; encoding: [0xf0,0x04,0x5c,0x7c]
+# W64: v_cmp_nlt_f64_e32 vcc, 0.5, v[2:3]        ; encoding: [0xf0,0x04,0x5c,0x7c]
+0xf0,0x04,0x5c,0x7c
+
+# W32: v_cmp_nlt_f64_e32 vcc_lo, src_scc, v[2:3] ; encoding: [0xfd,0x04,0x5c,0x7c]
+# W64: v_cmp_nlt_f64_e32 vcc, src_scc, v[2:3]    ; encoding: [0xfd,0x04,0x5c,0x7c]
+0xfd,0x04,0x5c,0x7c
+
+# W32: v_cmp_nlt_f64_e32 vcc_lo, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x5d,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_nlt_f64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x5d,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x5d,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_o_f16_e32 vcc_lo, v1, v2            ; encoding: [0x01,0x05,0x0e,0x7c]
+# W64: v_cmp_o_f16_e32 vcc, v1, v2               ; encoding: [0x01,0x05,0x0e,0x7c]
+0x01,0x05,0x0e,0x7c
+
+# W32: v_cmp_o_f16_e32 vcc_lo, v127, v2          ; encoding: [0x7f,0x05,0x0e,0x7c]
+# W64: v_cmp_o_f16_e32 vcc, v127, v2             ; encoding: [0x7f,0x05,0x0e,0x7c]
+0x7f,0x05,0x0e,0x7c
+
+# W32: v_cmp_o_f16_e32 vcc_lo, s1, v2            ; encoding: [0x01,0x04,0x0e,0x7c]
+# W64: v_cmp_o_f16_e32 vcc, s1, v2               ; encoding: [0x01,0x04,0x0e,0x7c]
+0x01,0x04,0x0e,0x7c
+
+# W32: v_cmp_o_f16_e32 vcc_lo, s105, v2          ; encoding: [0x69,0x04,0x0e,0x7c]
+# W64: v_cmp_o_f16_e32 vcc, s105, v2             ; encoding: [0x69,0x04,0x0e,0x7c]
+0x69,0x04,0x0e,0x7c
+
+# W32: v_cmp_o_f16_e32 vcc_lo, vcc_lo, v2        ; encoding: [0x6a,0x04,0x0e,0x7c]
+# W64: v_cmp_o_f16_e32 vcc, vcc_lo, v2           ; encoding: [0x6a,0x04,0x0e,0x7c]
+0x6a,0x04,0x0e,0x7c
+
+# W32: v_cmp_o_f16_e32 vcc_lo, vcc_hi, v2        ; encoding: [0x6b,0x04,0x0e,0x7c]
+# W64: v_cmp_o_f16_e32 vcc, vcc_hi, v2           ; encoding: [0x6b,0x04,0x0e,0x7c]
+0x6b,0x04,0x0e,0x7c
+
+# W32: v_cmp_o_f16_e32 vcc_lo, ttmp15, v2        ; encoding: [0x7b,0x04,0x0e,0x7c]
+# W64: v_cmp_o_f16_e32 vcc, ttmp15, v2           ; encoding: [0x7b,0x04,0x0e,0x7c]
+0x7b,0x04,0x0e,0x7c
+
+# W32: v_cmp_o_f16_e32 vcc_lo, m0, v2            ; encoding: [0x7d,0x04,0x0e,0x7c]
+# W64: v_cmp_o_f16_e32 vcc, m0, v2               ; encoding: [0x7d,0x04,0x0e,0x7c]
+0x7d,0x04,0x0e,0x7c
+
+# W32: v_cmp_o_f16_e32 vcc_lo, exec_lo, v2       ; encoding: [0x7e,0x04,0x0e,0x7c]
+# W64: v_cmp_o_f16_e32 vcc, exec_lo, v2          ; encoding: [0x7e,0x04,0x0e,0x7c]
+0x7e,0x04,0x0e,0x7c
+
+# W32: v_cmp_o_f16_e32 vcc_lo, exec_hi, v2       ; encoding: [0x7f,0x04,0x0e,0x7c]
+# W64: v_cmp_o_f16_e32 vcc, exec_hi, v2          ; encoding: [0x7f,0x04,0x0e,0x7c]
+0x7f,0x04,0x0e,0x7c
+
+# W32: v_cmp_o_f16_e32 vcc_lo, null, v2          ; encoding: [0x7c,0x04,0x0e,0x7c]
+# W64: v_cmp_o_f16_e32 vcc, null, v2             ; encoding: [0x7c,0x04,0x0e,0x7c]
+0x7c,0x04,0x0e,0x7c
+
+# W32: v_cmp_o_f16_e32 vcc_lo, -1, v2            ; encoding: [0xc1,0x04,0x0e,0x7c]
+# W64: v_cmp_o_f16_e32 vcc, -1, v2               ; encoding: [0xc1,0x04,0x0e,0x7c]
+0xc1,0x04,0x0e,0x7c
+
+# W32: v_cmp_o_f16_e32 vcc_lo, 0.5, v2           ; encoding: [0xf0,0x04,0x0e,0x7c]
+# W64: v_cmp_o_f16_e32 vcc, 0.5, v2              ; encoding: [0xf0,0x04,0x0e,0x7c]
+0xf0,0x04,0x0e,0x7c
+
+# W32: v_cmp_o_f16_e32 vcc_lo, src_scc, v2       ; encoding: [0xfd,0x04,0x0e,0x7c]
+# W64: v_cmp_o_f16_e32 vcc, src_scc, v2          ; encoding: [0xfd,0x04,0x0e,0x7c]
+0xfd,0x04,0x0e,0x7c
+
+# W32: v_cmp_o_f16_e32 vcc_lo, 0xfe0b, v127      ; encoding: [0xff,0xfe,0x0e,0x7c,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_o_f16_e32 vcc, 0xfe0b, v127         ; encoding: [0xff,0xfe,0x0e,0x7c,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x0e,0x7c,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_o_f32_e32 vcc_lo, v1, v2            ; encoding: [0x01,0x05,0x2e,0x7c]
+# W64: v_cmp_o_f32_e32 vcc, v1, v2               ; encoding: [0x01,0x05,0x2e,0x7c]
+0x01,0x05,0x2e,0x7c
+
+# W32: v_cmp_o_f32_e32 vcc_lo, v255, v2          ; encoding: [0xff,0x05,0x2e,0x7c]
+# W64: v_cmp_o_f32_e32 vcc, v255, v2             ; encoding: [0xff,0x05,0x2e,0x7c]
+0xff,0x05,0x2e,0x7c
+
+# W32: v_cmp_o_f32_e32 vcc_lo, s1, v2            ; encoding: [0x01,0x04,0x2e,0x7c]
+# W64: v_cmp_o_f32_e32 vcc, s1, v2               ; encoding: [0x01,0x04,0x2e,0x7c]
+0x01,0x04,0x2e,0x7c
+
+# W32: v_cmp_o_f32_e32 vcc_lo, s105, v2          ; encoding: [0x69,0x04,0x2e,0x7c]
+# W64: v_cmp_o_f32_e32 vcc, s105, v2             ; encoding: [0x69,0x04,0x2e,0x7c]
+0x69,0x04,0x2e,0x7c
+
+# W32: v_cmp_o_f32_e32 vcc_lo, vcc_lo, v2        ; encoding: [0x6a,0x04,0x2e,0x7c]
+# W64: v_cmp_o_f32_e32 vcc, vcc_lo, v2           ; encoding: [0x6a,0x04,0x2e,0x7c]
+0x6a,0x04,0x2e,0x7c
+
+# W32: v_cmp_o_f32_e32 vcc_lo, vcc_hi, v2        ; encoding: [0x6b,0x04,0x2e,0x7c]
+# W64: v_cmp_o_f32_e32 vcc, vcc_hi, v2           ; encoding: [0x6b,0x04,0x2e,0x7c]
+0x6b,0x04,0x2e,0x7c
+
+# W32: v_cmp_o_f32_e32 vcc_lo, ttmp15, v2        ; encoding: [0x7b,0x04,0x2e,0x7c]
+# W64: v_cmp_o_f32_e32 vcc, ttmp15, v2           ; encoding: [0x7b,0x04,0x2e,0x7c]
+0x7b,0x04,0x2e,0x7c
+
+# W32: v_cmp_o_f32_e32 vcc_lo, m0, v2            ; encoding: [0x7d,0x04,0x2e,0x7c]
+# W64: v_cmp_o_f32_e32 vcc, m0, v2               ; encoding: [0x7d,0x04,0x2e,0x7c]
+0x7d,0x04,0x2e,0x7c
+
+# W32: v_cmp_o_f32_e32 vcc_lo, exec_lo, v2       ; encoding: [0x7e,0x04,0x2e,0x7c]
+# W64: v_cmp_o_f32_e32 vcc, exec_lo, v2          ; encoding: [0x7e,0x04,0x2e,0x7c]
+0x7e,0x04,0x2e,0x7c
+
+# W32: v_cmp_o_f32_e32 vcc_lo, exec_hi, v2       ; encoding: [0x7f,0x04,0x2e,0x7c]
+# W64: v_cmp_o_f32_e32 vcc, exec_hi, v2          ; encoding: [0x7f,0x04,0x2e,0x7c]
+0x7f,0x04,0x2e,0x7c
+
+# W32: v_cmp_o_f32_e32 vcc_lo, null, v2          ; encoding: [0x7c,0x04,0x2e,0x7c]
+# W64: v_cmp_o_f32_e32 vcc, null, v2             ; encoding: [0x7c,0x04,0x2e,0x7c]
+0x7c,0x04,0x2e,0x7c
+
+# W32: v_cmp_o_f32_e32 vcc_lo, -1, v2            ; encoding: [0xc1,0x04,0x2e,0x7c]
+# W64: v_cmp_o_f32_e32 vcc, -1, v2               ; encoding: [0xc1,0x04,0x2e,0x7c]
+0xc1,0x04,0x2e,0x7c
+
+# W32: v_cmp_o_f32_e32 vcc_lo, 0.5, v2           ; encoding: [0xf0,0x04,0x2e,0x7c]
+# W64: v_cmp_o_f32_e32 vcc, 0.5, v2              ; encoding: [0xf0,0x04,0x2e,0x7c]
+0xf0,0x04,0x2e,0x7c
+
+# W32: v_cmp_o_f32_e32 vcc_lo, src_scc, v2       ; encoding: [0xfd,0x04,0x2e,0x7c]
+# W64: v_cmp_o_f32_e32 vcc, src_scc, v2          ; encoding: [0xfd,0x04,0x2e,0x7c]
+0xfd,0x04,0x2e,0x7c
+
+# W32: v_cmp_o_f32_e32 vcc_lo, 0xaf123456, v255  ; encoding: [0xff,0xfe,0x2f,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_o_f32_e32 vcc, 0xaf123456, v255     ; encoding: [0xff,0xfe,0x2f,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x2f,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_o_f64_e32 vcc_lo, v[1:2], v[2:3]    ; encoding: [0x01,0x05,0x4e,0x7c]
+# W64: v_cmp_o_f64_e32 vcc, v[1:2], v[2:3]       ; encoding: [0x01,0x05,0x4e,0x7c]
+0x01,0x05,0x4e,0x7c
+
+# W32: v_cmp_o_f64_e32 vcc_lo, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x4e,0x7c]
+# W64: v_cmp_o_f64_e32 vcc, v[254:255], v[2:3]   ; encoding: [0xfe,0x05,0x4e,0x7c]
+0xfe,0x05,0x4e,0x7c
+
+# W32: v_cmp_o_f64_e32 vcc_lo, s[2:3], v[2:3]    ; encoding: [0x02,0x04,0x4e,0x7c]
+# W64: v_cmp_o_f64_e32 vcc, s[2:3], v[2:3]       ; encoding: [0x02,0x04,0x4e,0x7c]
+0x02,0x04,0x4e,0x7c
+
+# W32: v_cmp_o_f64_e32 vcc_lo, s[104:105], v[2:3] ; encoding: [0x68,0x04,0x4e,0x7c]
+# W64: v_cmp_o_f64_e32 vcc, s[104:105], v[2:3]   ; encoding: [0x68,0x04,0x4e,0x7c]
+0x68,0x04,0x4e,0x7c
+
+# W32: v_cmp_o_f64_e32 vcc_lo, vcc, v[2:3]       ; encoding: [0x6a,0x04,0x4e,0x7c]
+# W64: v_cmp_o_f64_e32 vcc, vcc, v[2:3]          ; encoding: [0x6a,0x04,0x4e,0x7c]
+0x6a,0x04,0x4e,0x7c
+
+# W32: v_cmp_o_f64_e32 vcc_lo, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x4e,0x7c]
+# W64: v_cmp_o_f64_e32 vcc, ttmp[14:15], v[2:3]  ; encoding: [0x7a,0x04,0x4e,0x7c]
+0x7a,0x04,0x4e,0x7c
+
+# W32: v_cmp_o_f64_e32 vcc_lo, exec, v[2:3]      ; encoding: [0x7e,0x04,0x4e,0x7c]
+# W64: v_cmp_o_f64_e32 vcc, exec, v[2:3]         ; encoding: [0x7e,0x04,0x4e,0x7c]
+0x7e,0x04,0x4e,0x7c
+
+# W32: v_cmp_o_f64_e32 vcc_lo, null, v[2:3]      ; encoding: [0x7c,0x04,0x4e,0x7c]
+# W64: v_cmp_o_f64_e32 vcc, null, v[2:3]         ; encoding: [0x7c,0x04,0x4e,0x7c]
+0x7c,0x04,0x4e,0x7c
+
+# W32: v_cmp_o_f64_e32 vcc_lo, -1, v[2:3]        ; encoding: [0xc1,0x04,0x4e,0x7c]
+# W64: v_cmp_o_f64_e32 vcc, -1, v[2:3]           ; encoding: [0xc1,0x04,0x4e,0x7c]
+0xc1,0x04,0x4e,0x7c
+
+# W32: v_cmp_o_f64_e32 vcc_lo, 0.5, v[2:3]       ; encoding: [0xf0,0x04,0x4e,0x7c]
+# W64: v_cmp_o_f64_e32 vcc, 0.5, v[2:3]          ; encoding: [0xf0,0x04,0x4e,0x7c]
+0xf0,0x04,0x4e,0x7c
+
+# W32: v_cmp_o_f64_e32 vcc_lo, src_scc, v[2:3]   ; encoding: [0xfd,0x04,0x4e,0x7c]
+# W64: v_cmp_o_f64_e32 vcc, src_scc, v[2:3]      ; encoding: [0xfd,0x04,0x4e,0x7c]
+0xfd,0x04,0x4e,0x7c
+
+# W32: v_cmp_o_f64_e32 vcc_lo, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x4f,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_o_f64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x4f,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x4f,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_u_f16_e32 vcc_lo, v1, v2            ; encoding: [0x01,0x05,0x10,0x7c]
+# W64: v_cmp_u_f16_e32 vcc, v1, v2               ; encoding: [0x01,0x05,0x10,0x7c]
+0x01,0x05,0x10,0x7c
+
+# W32: v_cmp_u_f16_e32 vcc_lo, v127, v2          ; encoding: [0x7f,0x05,0x10,0x7c]
+# W64: v_cmp_u_f16_e32 vcc, v127, v2             ; encoding: [0x7f,0x05,0x10,0x7c]
+0x7f,0x05,0x10,0x7c
+
+# W32: v_cmp_u_f16_e32 vcc_lo, s1, v2            ; encoding: [0x01,0x04,0x10,0x7c]
+# W64: v_cmp_u_f16_e32 vcc, s1, v2               ; encoding: [0x01,0x04,0x10,0x7c]
+0x01,0x04,0x10,0x7c
+
+# W32: v_cmp_u_f16_e32 vcc_lo, s105, v2          ; encoding: [0x69,0x04,0x10,0x7c]
+# W64: v_cmp_u_f16_e32 vcc, s105, v2             ; encoding: [0x69,0x04,0x10,0x7c]
+0x69,0x04,0x10,0x7c
+
+# W32: v_cmp_u_f16_e32 vcc_lo, vcc_lo, v2        ; encoding: [0x6a,0x04,0x10,0x7c]
+# W64: v_cmp_u_f16_e32 vcc, vcc_lo, v2           ; encoding: [0x6a,0x04,0x10,0x7c]
+0x6a,0x04,0x10,0x7c
+
+# W32: v_cmp_u_f16_e32 vcc_lo, vcc_hi, v2        ; encoding: [0x6b,0x04,0x10,0x7c]
+# W64: v_cmp_u_f16_e32 vcc, vcc_hi, v2           ; encoding: [0x6b,0x04,0x10,0x7c]
+0x6b,0x04,0x10,0x7c
+
+# W32: v_cmp_u_f16_e32 vcc_lo, ttmp15, v2        ; encoding: [0x7b,0x04,0x10,0x7c]
+# W64: v_cmp_u_f16_e32 vcc, ttmp15, v2           ; encoding: [0x7b,0x04,0x10,0x7c]
+0x7b,0x04,0x10,0x7c
+
+# W32: v_cmp_u_f16_e32 vcc_lo, m0, v2            ; encoding: [0x7d,0x04,0x10,0x7c]
+# W64: v_cmp_u_f16_e32 vcc, m0, v2               ; encoding: [0x7d,0x04,0x10,0x7c]
+0x7d,0x04,0x10,0x7c
+
+# W32: v_cmp_u_f16_e32 vcc_lo, exec_lo, v2       ; encoding: [0x7e,0x04,0x10,0x7c]
+# W64: v_cmp_u_f16_e32 vcc, exec_lo, v2          ; encoding: [0x7e,0x04,0x10,0x7c]
+0x7e,0x04,0x10,0x7c
+
+# W32: v_cmp_u_f16_e32 vcc_lo, exec_hi, v2       ; encoding: [0x7f,0x04,0x10,0x7c]
+# W64: v_cmp_u_f16_e32 vcc, exec_hi, v2          ; encoding: [0x7f,0x04,0x10,0x7c]
+0x7f,0x04,0x10,0x7c
+
+# W32: v_cmp_u_f16_e32 vcc_lo, null, v2          ; encoding: [0x7c,0x04,0x10,0x7c]
+# W64: v_cmp_u_f16_e32 vcc, null, v2             ; encoding: [0x7c,0x04,0x10,0x7c]
+0x7c,0x04,0x10,0x7c
+
+# W32: v_cmp_u_f16_e32 vcc_lo, -1, v2            ; encoding: [0xc1,0x04,0x10,0x7c]
+# W64: v_cmp_u_f16_e32 vcc, -1, v2               ; encoding: [0xc1,0x04,0x10,0x7c]
+0xc1,0x04,0x10,0x7c
+
+# W32: v_cmp_u_f16_e32 vcc_lo, 0.5, v2           ; encoding: [0xf0,0x04,0x10,0x7c]
+# W64: v_cmp_u_f16_e32 vcc, 0.5, v2              ; encoding: [0xf0,0x04,0x10,0x7c]
+0xf0,0x04,0x10,0x7c
+
+# W32: v_cmp_u_f16_e32 vcc_lo, src_scc, v2       ; encoding: [0xfd,0x04,0x10,0x7c]
+# W64: v_cmp_u_f16_e32 vcc, src_scc, v2          ; encoding: [0xfd,0x04,0x10,0x7c]
+0xfd,0x04,0x10,0x7c
+
+# W32: v_cmp_u_f16_e32 vcc_lo, 0xfe0b, v127      ; encoding: [0xff,0xfe,0x10,0x7c,0x0b,0xfe,0x00,0x00]
+# W64: v_cmp_u_f16_e32 vcc, 0xfe0b, v127         ; encoding: [0xff,0xfe,0x10,0x7c,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x10,0x7c,0x0b,0xfe,0x00,0x00
+
+# W32: v_cmp_u_f32_e32 vcc_lo, v1, v2            ; encoding: [0x01,0x05,0x30,0x7c]
+# W64: v_cmp_u_f32_e32 vcc, v1, v2               ; encoding: [0x01,0x05,0x30,0x7c]
+0x01,0x05,0x30,0x7c
+
+# W32: v_cmp_u_f32_e32 vcc_lo, v255, v2          ; encoding: [0xff,0x05,0x30,0x7c]
+# W64: v_cmp_u_f32_e32 vcc, v255, v2             ; encoding: [0xff,0x05,0x30,0x7c]
+0xff,0x05,0x30,0x7c
+
+# W32: v_cmp_u_f32_e32 vcc_lo, s1, v2            ; encoding: [0x01,0x04,0x30,0x7c]
+# W64: v_cmp_u_f32_e32 vcc, s1, v2               ; encoding: [0x01,0x04,0x30,0x7c]
+0x01,0x04,0x30,0x7c
+
+# W32: v_cmp_u_f32_e32 vcc_lo, s105, v2          ; encoding: [0x69,0x04,0x30,0x7c]
+# W64: v_cmp_u_f32_e32 vcc, s105, v2             ; encoding: [0x69,0x04,0x30,0x7c]
+0x69,0x04,0x30,0x7c
+
+# W32: v_cmp_u_f32_e32 vcc_lo, vcc_lo, v2        ; encoding: [0x6a,0x04,0x30,0x7c]
+# W64: v_cmp_u_f32_e32 vcc, vcc_lo, v2           ; encoding: [0x6a,0x04,0x30,0x7c]
+0x6a,0x04,0x30,0x7c
+
+# W32: v_cmp_u_f32_e32 vcc_lo, vcc_hi, v2        ; encoding: [0x6b,0x04,0x30,0x7c]
+# W64: v_cmp_u_f32_e32 vcc, vcc_hi, v2           ; encoding: [0x6b,0x04,0x30,0x7c]
+0x6b,0x04,0x30,0x7c
+
+# W32: v_cmp_u_f32_e32 vcc_lo, ttmp15, v2        ; encoding: [0x7b,0x04,0x30,0x7c]
+# W64: v_cmp_u_f32_e32 vcc, ttmp15, v2           ; encoding: [0x7b,0x04,0x30,0x7c]
+0x7b,0x04,0x30,0x7c
+
+# W32: v_cmp_u_f32_e32 vcc_lo, m0, v2            ; encoding: [0x7d,0x04,0x30,0x7c]
+# W64: v_cmp_u_f32_e32 vcc, m0, v2               ; encoding: [0x7d,0x04,0x30,0x7c]
+0x7d,0x04,0x30,0x7c
+
+# W32: v_cmp_u_f32_e32 vcc_lo, exec_lo, v2       ; encoding: [0x7e,0x04,0x30,0x7c]
+# W64: v_cmp_u_f32_e32 vcc, exec_lo, v2          ; encoding: [0x7e,0x04,0x30,0x7c]
+0x7e,0x04,0x30,0x7c
+
+# W32: v_cmp_u_f32_e32 vcc_lo, exec_hi, v2       ; encoding: [0x7f,0x04,0x30,0x7c]
+# W64: v_cmp_u_f32_e32 vcc, exec_hi, v2          ; encoding: [0x7f,0x04,0x30,0x7c]
+0x7f,0x04,0x30,0x7c
+
+# W32: v_cmp_u_f32_e32 vcc_lo, null, v2          ; encoding: [0x7c,0x04,0x30,0x7c]
+# W64: v_cmp_u_f32_e32 vcc, null, v2             ; encoding: [0x7c,0x04,0x30,0x7c]
+0x7c,0x04,0x30,0x7c
+
+# W32: v_cmp_u_f32_e32 vcc_lo, -1, v2            ; encoding: [0xc1,0x04,0x30,0x7c]
+# W64: v_cmp_u_f32_e32 vcc, -1, v2               ; encoding: [0xc1,0x04,0x30,0x7c]
+0xc1,0x04,0x30,0x7c
+
+# W32: v_cmp_u_f32_e32 vcc_lo, 0.5, v2           ; encoding: [0xf0,0x04,0x30,0x7c]
+# W64: v_cmp_u_f32_e32 vcc, 0.5, v2              ; encoding: [0xf0,0x04,0x30,0x7c]
+0xf0,0x04,0x30,0x7c
+
+# W32: v_cmp_u_f32_e32 vcc_lo, src_scc, v2       ; encoding: [0xfd,0x04,0x30,0x7c]
+# W64: v_cmp_u_f32_e32 vcc, src_scc, v2          ; encoding: [0xfd,0x04,0x30,0x7c]
+0xfd,0x04,0x30,0x7c
+
+# W32: v_cmp_u_f32_e32 vcc_lo, 0xaf123456, v255  ; encoding: [0xff,0xfe,0x31,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_u_f32_e32 vcc, 0xaf123456, v255     ; encoding: [0xff,0xfe,0x31,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x31,0x7c,0x56,0x34,0x12,0xaf
+
+# W32: v_cmp_u_f64_e32 vcc_lo, v[1:2], v[2:3]    ; encoding: [0x01,0x05,0x50,0x7c]
+# W64: v_cmp_u_f64_e32 vcc, v[1:2], v[2:3]       ; encoding: [0x01,0x05,0x50,0x7c]
+0x01,0x05,0x50,0x7c
+
+# W32: v_cmp_u_f64_e32 vcc_lo, v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x50,0x7c]
+# W64: v_cmp_u_f64_e32 vcc, v[254:255], v[2:3]   ; encoding: [0xfe,0x05,0x50,0x7c]
+0xfe,0x05,0x50,0x7c
+
+# W32: v_cmp_u_f64_e32 vcc_lo, s[2:3], v[2:3]    ; encoding: [0x02,0x04,0x50,0x7c]
+# W64: v_cmp_u_f64_e32 vcc, s[2:3], v[2:3]       ; encoding: [0x02,0x04,0x50,0x7c]
+0x02,0x04,0x50,0x7c
+
+# W32: v_cmp_u_f64_e32 vcc_lo, s[104:105], v[2:3] ; encoding: [0x68,0x04,0x50,0x7c]
+# W64: v_cmp_u_f64_e32 vcc, s[104:105], v[2:3]   ; encoding: [0x68,0x04,0x50,0x7c]
+0x68,0x04,0x50,0x7c
+
+# W32: v_cmp_u_f64_e32 vcc_lo, vcc, v[2:3]       ; encoding: [0x6a,0x04,0x50,0x7c]
+# W64: v_cmp_u_f64_e32 vcc, vcc, v[2:3]          ; encoding: [0x6a,0x04,0x50,0x7c]
+0x6a,0x04,0x50,0x7c
+
+# W32: v_cmp_u_f64_e32 vcc_lo, ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x50,0x7c]
+# W64: v_cmp_u_f64_e32 vcc, ttmp[14:15], v[2:3]  ; encoding: [0x7a,0x04,0x50,0x7c]
+0x7a,0x04,0x50,0x7c
+
+# W32: v_cmp_u_f64_e32 vcc_lo, exec, v[2:3]      ; encoding: [0x7e,0x04,0x50,0x7c]
+# W64: v_cmp_u_f64_e32 vcc, exec, v[2:3]         ; encoding: [0x7e,0x04,0x50,0x7c]
+0x7e,0x04,0x50,0x7c
+
+# W32: v_cmp_u_f64_e32 vcc_lo, null, v[2:3]      ; encoding: [0x7c,0x04,0x50,0x7c]
+# W64: v_cmp_u_f64_e32 vcc, null, v[2:3]         ; encoding: [0x7c,0x04,0x50,0x7c]
+0x7c,0x04,0x50,0x7c
+
+# W32: v_cmp_u_f64_e32 vcc_lo, -1, v[2:3]        ; encoding: [0xc1,0x04,0x50,0x7c]
+# W64: v_cmp_u_f64_e32 vcc, -1, v[2:3]           ; encoding: [0xc1,0x04,0x50,0x7c]
+0xc1,0x04,0x50,0x7c
+
+# W32: v_cmp_u_f64_e32 vcc_lo, 0.5, v[2:3]       ; encoding: [0xf0,0x04,0x50,0x7c]
+# W64: v_cmp_u_f64_e32 vcc, 0.5, v[2:3]          ; encoding: [0xf0,0x04,0x50,0x7c]
+0xf0,0x04,0x50,0x7c
+
+# W32: v_cmp_u_f64_e32 vcc_lo, src_scc, v[2:3]   ; encoding: [0xfd,0x04,0x50,0x7c]
+# W64: v_cmp_u_f64_e32 vcc, src_scc, v[2:3]      ; encoding: [0xfd,0x04,0x50,0x7c]
+0xfd,0x04,0x50,0x7c
+
+# W32: v_cmp_u_f64_e32 vcc_lo, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x51,0x7c,0x56,0x34,0x12,0xaf]
+# W64: v_cmp_u_f64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x51,0x7c,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x51,0x7c,0x56,0x34,0x12,0xaf
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp16.txt
new file mode 100644
index 000000000000..3ec29cf78ff3
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp16.txt
@@ -0,0 +1,3026 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W32
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W64
+
+# W32: v_cmp_class_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_class_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_class_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_class_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0xfa,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_class_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0xfa,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_class_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0xfa,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_class_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0xfa,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_class_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0xfa,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_class_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0xfa,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_class_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0xfa,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_class_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0xfa,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_class_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0xfa,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_class_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0xfa,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_class_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0xfa,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_class_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_class_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0xfa,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_class_f16 vcc_lo, -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x6f,0x3d,0x30]
+# W64: v_cmp_class_f16 vcc, -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7c,0x7f,0x6f,0x3d,0x30]
+0xfa,0xfe,0xfa,0x7c,0x7f,0x6f,0x3d,0x30
+
+# W32: v_cmp_class_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_class_f32 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0xfc,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_class_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_class_f32 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0xfc,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_class_f32 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_class_f32 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0xfc,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_class_f32 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_class_f32 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0xfc,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_class_f32 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_class_f32 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0xfc,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_class_f32 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_class_f32 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0xfc,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_class_f32 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_class_f32 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0xfc,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_class_f32 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_class_f32 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0xfc,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_class_f32 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_class_f32 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0xfc,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_class_f32 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_class_f32 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0xfc,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_class_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_class_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0xfc,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_class_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_class_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0xfc,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_class_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_class_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfc,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0xfc,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_class_f32 vcc_lo, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfd,0x7c,0xff,0x6f,0x3d,0x30]
+# W64: v_cmp_class_f32 vcc, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfd,0x7c,0xff,0x6f,0x3d,0x30]
+0xfa,0xfe,0xfd,0x7c,0xff,0x6f,0x3d,0x30
+
+# W32: v_cmp_eq_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_eq_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_eq_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_eq_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_eq_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_eq_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_eq_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_eq_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_eq_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_eq_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_eq_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_eq_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_eq_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x04,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_eq_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x04,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_eq_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x04,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_eq_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x6f,0xfd,0x30]
+# W64: v_cmp_eq_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0x04,0x7c,0x7f,0x6f,0xfd,0x30
+
+# W32: v_cmp_eq_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_eq_f32 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x24,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_eq_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_eq_f32 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x24,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_eq_f32 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_eq_f32 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x24,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_eq_f32 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_eq_f32 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x24,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_eq_f32 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_eq_f32 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x24,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_eq_f32 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_eq_f32 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x24,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_eq_f32 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_eq_f32 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x24,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_eq_f32 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_eq_f32 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x24,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_eq_f32 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_eq_f32 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x24,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_eq_f32 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_eq_f32 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x24,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_eq_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_eq_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x24,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_eq_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x24,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_eq_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x24,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x24,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_eq_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x24,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_eq_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x24,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x24,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_eq_f32 vcc_lo, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x25,0x7c,0xff,0x6f,0xfd,0x30]
+# W64: v_cmp_eq_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x25,0x7c,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0x25,0x7c,0xff,0x6f,0xfd,0x30
+
+# W32: v_cmp_eq_i16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_eq_i16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x64,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_eq_i16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_eq_i16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x64,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_eq_i16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_eq_i16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x64,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_eq_i16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_eq_i16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x64,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_eq_i16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_eq_i16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x64,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_eq_i16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_eq_i16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x64,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_eq_i16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_eq_i16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x64,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_eq_i16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_eq_i16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x64,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_eq_i16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_eq_i16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x64,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_eq_i16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_eq_i16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x64,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_eq_i16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_eq_i16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x64,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_eq_i16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x64,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_eq_i16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x64,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x64,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_eq_i16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x64,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_eq_i16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x64,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x64,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_eq_i16 vcc_lo, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x64,0x7c,0x7f,0x6f,0x0d,0x30]
+# W64: v_cmp_eq_i16 vcc, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x64,0x7c,0x7f,0x6f,0x0d,0x30]
+0xfa,0xfe,0x64,0x7c,0x7f,0x6f,0x0d,0x30
+
+# W32: v_cmp_eq_i32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_eq_i32 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x84,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_eq_i32 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_eq_i32 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x84,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_eq_i32 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_eq_i32 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x84,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_eq_i32 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_eq_i32 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x84,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_eq_i32 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_eq_i32 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x84,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_eq_i32 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_eq_i32 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x84,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_eq_i32 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_eq_i32 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x84,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_eq_i32 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_eq_i32 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x84,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_eq_i32 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_eq_i32 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x84,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_eq_i32 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_eq_i32 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x84,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_eq_i32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_eq_i32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x84,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_eq_i32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x84,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_eq_i32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x84,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x84,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_eq_i32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x84,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_eq_i32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x84,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x84,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_eq_i32 vcc_lo, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x85,0x7c,0xff,0x6f,0x0d,0x30]
+# W64: v_cmp_eq_i32 vcc, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x85,0x7c,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0x85,0x7c,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_eq_u16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_eq_u16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x74,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_eq_u16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_eq_u16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x74,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_eq_u16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_eq_u16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x74,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_eq_u16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_eq_u16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x74,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_eq_u16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_eq_u16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x74,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_eq_u16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_eq_u16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x74,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_eq_u16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_eq_u16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x74,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_eq_u16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_eq_u16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x74,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_eq_u16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_eq_u16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x74,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_eq_u16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_eq_u16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x74,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_eq_u16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_eq_u16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x74,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_eq_u16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x74,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_eq_u16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x74,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x74,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_eq_u16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x74,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_eq_u16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x74,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x74,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_eq_u16 vcc_lo, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x74,0x7c,0x7f,0x6f,0x0d,0x30]
+# W64: v_cmp_eq_u16 vcc, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x74,0x7c,0x7f,0x6f,0x0d,0x30]
+0xfa,0xfe,0x74,0x7c,0x7f,0x6f,0x0d,0x30
+
+# W32: v_cmp_eq_u32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_eq_u32 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x94,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_eq_u32 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_eq_u32 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x94,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_eq_u32 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_eq_u32 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x94,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_eq_u32 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_eq_u32 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x94,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_eq_u32 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_eq_u32 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x94,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_eq_u32 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_eq_u32 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x94,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_eq_u32 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_eq_u32 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x94,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_eq_u32 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_eq_u32 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x94,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_eq_u32 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_eq_u32 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x94,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_eq_u32 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_eq_u32 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x94,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_eq_u32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_eq_u32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x94,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_eq_u32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x94,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_eq_u32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x94,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x94,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_eq_u32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x94,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_eq_u32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x94,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x94,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_eq_u32 vcc_lo, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x95,0x7c,0xff,0x6f,0x0d,0x30]
+# W64: v_cmp_eq_u32 vcc, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x95,0x7c,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0x95,0x7c,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_ge_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_ge_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0c,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_ge_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_ge_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0c,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_ge_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_ge_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0c,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_ge_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_ge_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0c,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_ge_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_ge_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0c,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_ge_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_ge_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0c,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_ge_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_ge_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0c,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_ge_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_ge_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0c,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_ge_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_ge_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0c,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_ge_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_ge_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0c,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_ge_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_ge_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0c,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_ge_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_ge_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0c,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_ge_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_ge_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0c,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0c,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_ge_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x0c,0x7c,0x7f,0x6f,0xfd,0x30]
+# W64: v_cmp_ge_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x0c,0x7c,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0x0c,0x7c,0x7f,0x6f,0xfd,0x30
+
+# W32: v_cmp_ge_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_ge_f32 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x2c,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_ge_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_ge_f32 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x2c,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_ge_f32 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_ge_f32 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x2c,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_ge_f32 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_ge_f32 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x2c,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_ge_f32 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_ge_f32 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x2c,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_ge_f32 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_ge_f32 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x2c,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_ge_f32 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_ge_f32 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x2c,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_ge_f32 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_ge_f32 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x2c,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_ge_f32 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_ge_f32 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x2c,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_ge_f32 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_ge_f32 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x2c,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_ge_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_ge_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x2c,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_ge_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_ge_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x2c,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_ge_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_ge_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x2c,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x2c,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_ge_f32 vcc_lo, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x2d,0x7c,0xff,0x6f,0xfd,0x30]
+# W64: v_cmp_ge_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x2d,0x7c,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0x2d,0x7c,0xff,0x6f,0xfd,0x30
+
+# W32: v_cmp_ge_i16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_ge_i16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x6c,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_ge_i16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_ge_i16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x6c,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_ge_i16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_ge_i16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x6c,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_ge_i16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_ge_i16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x6c,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_ge_i16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_ge_i16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x6c,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_ge_i16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_ge_i16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x6c,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_ge_i16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_ge_i16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x6c,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_ge_i16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_ge_i16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x6c,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_ge_i16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_ge_i16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x6c,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_ge_i16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_ge_i16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x6c,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_ge_i16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_ge_i16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x6c,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_ge_i16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_ge_i16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x6c,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_ge_i16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_ge_i16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x6c,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x6c,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_ge_i16 vcc_lo, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x6c,0x7c,0x7f,0x6f,0x0d,0x30]
+# W64: v_cmp_ge_i16 vcc, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x6c,0x7c,0x7f,0x6f,0x0d,0x30]
+0xfa,0xfe,0x6c,0x7c,0x7f,0x6f,0x0d,0x30
+
+# W32: v_cmp_ge_i32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_ge_i32 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x8c,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_ge_i32 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_ge_i32 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x8c,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_ge_i32 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_ge_i32 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x8c,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_ge_i32 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_ge_i32 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x8c,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_ge_i32 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_ge_i32 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x8c,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_ge_i32 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_ge_i32 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x8c,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_ge_i32 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_ge_i32 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x8c,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_ge_i32 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_ge_i32 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x8c,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_ge_i32 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_ge_i32 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x8c,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_ge_i32 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_ge_i32 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x8c,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_ge_i32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_ge_i32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x8c,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_ge_i32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_ge_i32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x8c,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_ge_i32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_ge_i32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x8c,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x8c,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_ge_i32 vcc_lo, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x8d,0x7c,0xff,0x6f,0x0d,0x30]
+# W64: v_cmp_ge_i32 vcc, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x8d,0x7c,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0x8d,0x7c,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_ge_u16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_ge_u16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x7c,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_ge_u16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_ge_u16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x7c,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_ge_u16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_ge_u16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x7c,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_ge_u16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_ge_u16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x7c,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_ge_u16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_ge_u16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x7c,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_ge_u16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_ge_u16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x7c,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_ge_u16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_ge_u16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x7c,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_ge_u16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_ge_u16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x7c,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_ge_u16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_ge_u16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x7c,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_ge_u16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_ge_u16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x7c,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_ge_u16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_ge_u16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x7c,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_ge_u16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_ge_u16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x7c,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_ge_u16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_ge_u16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x7c,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_ge_u16 vcc_lo, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x7c,0x7c,0x7f,0x6f,0x0d,0x30]
+# W64: v_cmp_ge_u16 vcc, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x7c,0x7c,0x7f,0x6f,0x0d,0x30]
+0xfa,0xfe,0x7c,0x7c,0x7f,0x6f,0x0d,0x30
+
+# W32: v_cmp_ge_u32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_ge_u32 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x9c,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_ge_u32 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_ge_u32 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x9c,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_ge_u32 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_ge_u32 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x9c,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_ge_u32 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_ge_u32 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x9c,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_ge_u32 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_ge_u32 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x9c,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_ge_u32 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_ge_u32 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x9c,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_ge_u32 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_ge_u32 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x9c,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_ge_u32 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_ge_u32 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x9c,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_ge_u32 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_ge_u32 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x9c,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_ge_u32 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_ge_u32 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x9c,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_ge_u32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_ge_u32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x9c,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_ge_u32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_ge_u32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x9c,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_ge_u32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_ge_u32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x9c,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x9c,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_ge_u32 vcc_lo, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x9d,0x7c,0xff,0x6f,0x0d,0x30]
+# W64: v_cmp_ge_u32 vcc, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x9d,0x7c,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0x9d,0x7c,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_gt_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_gt_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x08,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_gt_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_gt_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x08,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_gt_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_gt_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x08,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_gt_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_gt_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x08,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_gt_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_gt_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x08,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_gt_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_gt_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x08,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_gt_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_gt_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x08,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_gt_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_gt_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x08,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_gt_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_gt_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x08,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_gt_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_gt_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x08,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_gt_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_gt_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x08,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_gt_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x08,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_gt_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x08,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x08,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_gt_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x08,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_gt_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x08,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x08,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_gt_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x08,0x7c,0x7f,0x6f,0xfd,0x30]
+# W64: v_cmp_gt_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x08,0x7c,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0x08,0x7c,0x7f,0x6f,0xfd,0x30
+
+# W32: v_cmp_gt_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_gt_f32 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x28,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_gt_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_gt_f32 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x28,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_gt_f32 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_gt_f32 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x28,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_gt_f32 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_gt_f32 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x28,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_gt_f32 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_gt_f32 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x28,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_gt_f32 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_gt_f32 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x28,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_gt_f32 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_gt_f32 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x28,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_gt_f32 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_gt_f32 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x28,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_gt_f32 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_gt_f32 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x28,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_gt_f32 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_gt_f32 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x28,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_gt_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_gt_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x28,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_gt_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x28,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_gt_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x28,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x28,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_gt_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x28,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_gt_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x28,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x28,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_gt_f32 vcc_lo, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x29,0x7c,0xff,0x6f,0xfd,0x30]
+# W64: v_cmp_gt_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x29,0x7c,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0x29,0x7c,0xff,0x6f,0xfd,0x30
+
+# W32: v_cmp_gt_i16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_gt_i16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x68,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_gt_i16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_gt_i16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x68,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_gt_i16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_gt_i16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x68,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_gt_i16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_gt_i16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x68,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_gt_i16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_gt_i16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x68,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_gt_i16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_gt_i16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x68,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_gt_i16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_gt_i16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x68,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_gt_i16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_gt_i16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x68,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_gt_i16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_gt_i16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x68,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_gt_i16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_gt_i16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x68,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_gt_i16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_gt_i16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x68,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_gt_i16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x68,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_gt_i16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x68,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x68,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_gt_i16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x68,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_gt_i16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x68,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x68,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_gt_i16 vcc_lo, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x68,0x7c,0x7f,0x6f,0x0d,0x30]
+# W64: v_cmp_gt_i16 vcc, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x68,0x7c,0x7f,0x6f,0x0d,0x30]
+0xfa,0xfe,0x68,0x7c,0x7f,0x6f,0x0d,0x30
+
+# W32: v_cmp_gt_i32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_gt_i32 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x88,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_gt_i32 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_gt_i32 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x88,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_gt_i32 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_gt_i32 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x88,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_gt_i32 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_gt_i32 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x88,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_gt_i32 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_gt_i32 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x88,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_gt_i32 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_gt_i32 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x88,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_gt_i32 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_gt_i32 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x88,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_gt_i32 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_gt_i32 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x88,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_gt_i32 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_gt_i32 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x88,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_gt_i32 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_gt_i32 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x88,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_gt_i32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_gt_i32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x88,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_gt_i32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x88,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_gt_i32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x88,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x88,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_gt_i32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x88,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_gt_i32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x88,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x88,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_gt_i32 vcc_lo, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x89,0x7c,0xff,0x6f,0x0d,0x30]
+# W64: v_cmp_gt_i32 vcc, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x89,0x7c,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0x89,0x7c,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_gt_u16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_gt_u16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x78,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_gt_u16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_gt_u16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x78,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_gt_u16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_gt_u16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x78,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_gt_u16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_gt_u16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x78,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_gt_u16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_gt_u16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x78,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_gt_u16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_gt_u16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x78,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_gt_u16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_gt_u16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x78,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_gt_u16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_gt_u16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x78,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_gt_u16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_gt_u16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x78,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_gt_u16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_gt_u16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x78,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_gt_u16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_gt_u16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x78,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_gt_u16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x78,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_gt_u16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x78,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x78,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_gt_u16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x78,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_gt_u16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x78,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x78,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_gt_u16 vcc_lo, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x78,0x7c,0x7f,0x6f,0x0d,0x30]
+# W64: v_cmp_gt_u16 vcc, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x78,0x7c,0x7f,0x6f,0x0d,0x30]
+0xfa,0xfe,0x78,0x7c,0x7f,0x6f,0x0d,0x30
+
+# W32: v_cmp_gt_u32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_gt_u32 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x98,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_gt_u32 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_gt_u32 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x98,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_gt_u32 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_gt_u32 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x98,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_gt_u32 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_gt_u32 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x98,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_gt_u32 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_gt_u32 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x98,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_gt_u32 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_gt_u32 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x98,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_gt_u32 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_gt_u32 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x98,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_gt_u32 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_gt_u32 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x98,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_gt_u32 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_gt_u32 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x98,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_gt_u32 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_gt_u32 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x98,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_gt_u32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_gt_u32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x98,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_gt_u32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x98,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_gt_u32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x98,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x98,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_gt_u32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x98,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_gt_u32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x98,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x98,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_gt_u32 vcc_lo, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x99,0x7c,0xff,0x6f,0x0d,0x30]
+# W64: v_cmp_gt_u32 vcc, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x99,0x7c,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0x99,0x7c,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_le_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_le_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x06,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_le_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_le_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x06,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_le_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_le_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x06,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_le_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_le_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x06,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_le_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_le_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x06,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_le_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_le_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x06,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_le_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_le_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x06,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_le_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_le_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x06,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_le_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_le_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x06,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_le_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_le_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x06,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_le_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_le_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x06,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_le_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x06,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_le_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x06,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x06,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_le_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x06,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_le_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x06,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x06,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_le_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x06,0x7c,0x7f,0x6f,0xfd,0x30]
+# W64: v_cmp_le_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x06,0x7c,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0x06,0x7c,0x7f,0x6f,0xfd,0x30
+
+# W32: v_cmp_le_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_le_f32 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x26,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_le_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_le_f32 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x26,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_le_f32 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_le_f32 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x26,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_le_f32 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_le_f32 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x26,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_le_f32 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_le_f32 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x26,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_le_f32 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_le_f32 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x26,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_le_f32 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_le_f32 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x26,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_le_f32 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_le_f32 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x26,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_le_f32 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_le_f32 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x26,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_le_f32 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_le_f32 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x26,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_le_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_le_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x26,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_le_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x26,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_le_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x26,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x26,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_le_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x26,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_le_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x26,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x26,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_le_f32 vcc_lo, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x27,0x7c,0xff,0x6f,0xfd,0x30]
+# W64: v_cmp_le_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x27,0x7c,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0x27,0x7c,0xff,0x6f,0xfd,0x30
+
+# W32: v_cmp_le_i16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_le_i16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x66,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_le_i16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_le_i16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x66,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_le_i16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_le_i16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x66,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_le_i16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_le_i16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x66,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_le_i16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_le_i16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x66,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_le_i16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_le_i16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x66,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_le_i16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_le_i16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x66,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_le_i16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_le_i16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x66,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_le_i16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_le_i16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x66,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_le_i16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_le_i16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x66,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_le_i16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_le_i16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x66,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_le_i16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x66,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_le_i16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x66,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x66,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_le_i16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x66,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_le_i16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x66,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x66,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_le_i16 vcc_lo, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x66,0x7c,0x7f,0x6f,0x0d,0x30]
+# W64: v_cmp_le_i16 vcc, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x66,0x7c,0x7f,0x6f,0x0d,0x30]
+0xfa,0xfe,0x66,0x7c,0x7f,0x6f,0x0d,0x30
+
+# W32: v_cmp_le_i32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_le_i32 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x86,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_le_i32 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_le_i32 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x86,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_le_i32 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_le_i32 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x86,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_le_i32 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_le_i32 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x86,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_le_i32 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_le_i32 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x86,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_le_i32 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_le_i32 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x86,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_le_i32 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_le_i32 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x86,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_le_i32 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_le_i32 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x86,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_le_i32 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_le_i32 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x86,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_le_i32 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_le_i32 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x86,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_le_i32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_le_i32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x86,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_le_i32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x86,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_le_i32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x86,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x86,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_le_i32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x86,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_le_i32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x86,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x86,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_le_i32 vcc_lo, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x87,0x7c,0xff,0x6f,0x0d,0x30]
+# W64: v_cmp_le_i32 vcc, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x87,0x7c,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0x87,0x7c,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_le_u16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_le_u16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x76,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_le_u16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_le_u16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x76,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_le_u16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_le_u16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x76,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_le_u16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_le_u16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x76,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_le_u16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_le_u16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x76,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_le_u16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_le_u16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x76,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_le_u16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_le_u16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x76,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_le_u16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_le_u16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x76,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_le_u16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_le_u16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x76,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_le_u16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_le_u16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x76,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_le_u16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_le_u16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x76,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_le_u16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x76,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_le_u16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x76,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x76,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_le_u16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x76,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_le_u16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x76,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x76,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_le_u16 vcc_lo, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x76,0x7c,0x7f,0x6f,0x0d,0x30]
+# W64: v_cmp_le_u16 vcc, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x76,0x7c,0x7f,0x6f,0x0d,0x30]
+0xfa,0xfe,0x76,0x7c,0x7f,0x6f,0x0d,0x30
+
+# W32: v_cmp_le_u32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_le_u32 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x96,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_le_u32 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_le_u32 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x96,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_le_u32 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_le_u32 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x96,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_le_u32 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_le_u32 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x96,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_le_u32 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_le_u32 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x96,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_le_u32 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_le_u32 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x96,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_le_u32 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_le_u32 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x96,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_le_u32 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_le_u32 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x96,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_le_u32 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_le_u32 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x96,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_le_u32 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_le_u32 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x96,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_le_u32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_le_u32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x96,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_le_u32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x96,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_le_u32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x96,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x96,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_le_u32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x96,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_le_u32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x96,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x96,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_le_u32 vcc_lo, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x97,0x7c,0xff,0x6f,0x0d,0x30]
+# W64: v_cmp_le_u32 vcc, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x97,0x7c,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0x97,0x7c,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_lg_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_lg_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_lg_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_lg_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_lg_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_lg_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_lg_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_lg_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_lg_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_lg_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_lg_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_lg_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_lg_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_lg_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_lg_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_lg_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_lg_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_lg_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_lg_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_lg_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_lg_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_lg_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_lg_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_lg_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_lg_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_lg_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_lg_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x0a,0x7c,0x7f,0x6f,0xfd,0x30]
+# W64: v_cmp_lg_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x0a,0x7c,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0x0a,0x7c,0x7f,0x6f,0xfd,0x30
+
+# W32: v_cmp_lg_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_lg_f32 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x2a,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_lg_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_lg_f32 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x2a,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_lg_f32 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_lg_f32 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x2a,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_lg_f32 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_lg_f32 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x2a,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_lg_f32 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_lg_f32 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x2a,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_lg_f32 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_lg_f32 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x2a,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_lg_f32 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_lg_f32 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x2a,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_lg_f32 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_lg_f32 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x2a,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_lg_f32 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_lg_f32 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x2a,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_lg_f32 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_lg_f32 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x2a,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_lg_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_lg_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x2a,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_lg_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_lg_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x2a,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_lg_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_lg_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x2a,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x2a,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_lg_f32 vcc_lo, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x2b,0x7c,0xff,0x6f,0xfd,0x30]
+# W64: v_cmp_lg_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x2b,0x7c,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0x2b,0x7c,0xff,0x6f,0xfd,0x30
+
+# W32: v_cmp_lt_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_lt_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_lt_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_lt_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_lt_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_lt_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_lt_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_lt_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_lt_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_lt_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_lt_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_lt_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_lt_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x02,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_lt_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x02,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_lt_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x02,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_lt_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x6f,0xfd,0x30]
+# W64: v_cmp_lt_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0x02,0x7c,0x7f,0x6f,0xfd,0x30
+
+# W32: v_cmp_lt_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_lt_f32 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x22,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_lt_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_lt_f32 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x22,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_lt_f32 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_lt_f32 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x22,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_lt_f32 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_lt_f32 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x22,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_lt_f32 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_lt_f32 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x22,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_lt_f32 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_lt_f32 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x22,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_lt_f32 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_lt_f32 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x22,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_lt_f32 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_lt_f32 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x22,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_lt_f32 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_lt_f32 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x22,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_lt_f32 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_lt_f32 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x22,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_lt_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_lt_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x22,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_lt_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x22,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_lt_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x22,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x22,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_lt_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x22,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_lt_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x22,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x22,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_lt_f32 vcc_lo, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x23,0x7c,0xff,0x6f,0xfd,0x30]
+# W64: v_cmp_lt_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x23,0x7c,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0x23,0x7c,0xff,0x6f,0xfd,0x30
+
+# W32: v_cmp_lt_i16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_lt_i16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x62,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_lt_i16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_lt_i16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x62,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_lt_i16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_lt_i16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x62,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_lt_i16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_lt_i16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x62,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_lt_i16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_lt_i16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x62,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_lt_i16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_lt_i16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x62,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_lt_i16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_lt_i16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x62,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_lt_i16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_lt_i16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x62,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_lt_i16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_lt_i16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x62,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_lt_i16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_lt_i16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x62,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_lt_i16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_lt_i16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x62,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_lt_i16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x62,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_lt_i16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x62,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x62,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_lt_i16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x62,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_lt_i16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x62,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x62,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_lt_i16 vcc_lo, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x62,0x7c,0x7f,0x6f,0x0d,0x30]
+# W64: v_cmp_lt_i16 vcc, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x62,0x7c,0x7f,0x6f,0x0d,0x30]
+0xfa,0xfe,0x62,0x7c,0x7f,0x6f,0x0d,0x30
+
+# W32: v_cmp_lt_i32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_lt_i32 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x82,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_lt_i32 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_lt_i32 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x82,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_lt_i32 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_lt_i32 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x82,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_lt_i32 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_lt_i32 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x82,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_lt_i32 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_lt_i32 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x82,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_lt_i32 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_lt_i32 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x82,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_lt_i32 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_lt_i32 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x82,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_lt_i32 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_lt_i32 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x82,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_lt_i32 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_lt_i32 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x82,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_lt_i32 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_lt_i32 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x82,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_lt_i32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_lt_i32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x82,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_lt_i32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x82,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_lt_i32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x82,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x82,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_lt_i32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x82,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_lt_i32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x82,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x82,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_lt_i32 vcc_lo, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x83,0x7c,0xff,0x6f,0x0d,0x30]
+# W64: v_cmp_lt_i32 vcc, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x83,0x7c,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0x83,0x7c,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_lt_u16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_lt_u16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x72,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_lt_u16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_lt_u16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x72,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_lt_u16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_lt_u16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x72,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_lt_u16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_lt_u16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x72,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_lt_u16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_lt_u16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x72,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_lt_u16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_lt_u16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x72,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_lt_u16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_lt_u16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x72,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_lt_u16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_lt_u16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x72,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_lt_u16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_lt_u16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x72,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_lt_u16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_lt_u16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x72,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_lt_u16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_lt_u16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x72,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_lt_u16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x72,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_lt_u16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x72,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x72,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_lt_u16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x72,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_lt_u16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x72,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x72,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_lt_u16 vcc_lo, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x72,0x7c,0x7f,0x6f,0x0d,0x30]
+# W64: v_cmp_lt_u16 vcc, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x72,0x7c,0x7f,0x6f,0x0d,0x30]
+0xfa,0xfe,0x72,0x7c,0x7f,0x6f,0x0d,0x30
+
+# W32: v_cmp_lt_u32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_lt_u32 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x92,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_lt_u32 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_lt_u32 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x92,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_lt_u32 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_lt_u32 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x92,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_lt_u32 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_lt_u32 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x92,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_lt_u32 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_lt_u32 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x92,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_lt_u32 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_lt_u32 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x92,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_lt_u32 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_lt_u32 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x92,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_lt_u32 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_lt_u32 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x92,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_lt_u32 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_lt_u32 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x92,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_lt_u32 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_lt_u32 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x92,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_lt_u32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_lt_u32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x92,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_lt_u32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x92,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_lt_u32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x92,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x92,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_lt_u32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x92,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_lt_u32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x92,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x92,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_lt_u32 vcc_lo, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x93,0x7c,0xff,0x6f,0x0d,0x30]
+# W64: v_cmp_lt_u32 vcc, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x93,0x7c,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0x93,0x7c,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_ne_i16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_ne_i16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x6a,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_ne_i16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_ne_i16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x6a,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_ne_i16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_ne_i16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x6a,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_ne_i16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_ne_i16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x6a,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_ne_i16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_ne_i16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x6a,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_ne_i16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_ne_i16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x6a,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_ne_i16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_ne_i16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x6a,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_ne_i16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_ne_i16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x6a,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_ne_i16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_ne_i16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x6a,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_ne_i16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_ne_i16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x6a,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_ne_i16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_ne_i16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x6a,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_ne_i16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_ne_i16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x6a,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_ne_i16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_ne_i16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x6a,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x6a,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_ne_i16 vcc_lo, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x6a,0x7c,0x7f,0x6f,0x0d,0x30]
+# W64: v_cmp_ne_i16 vcc, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x6a,0x7c,0x7f,0x6f,0x0d,0x30]
+0xfa,0xfe,0x6a,0x7c,0x7f,0x6f,0x0d,0x30
+
+# W32: v_cmp_ne_i32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_ne_i32 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x8a,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_ne_i32 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_ne_i32 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x8a,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_ne_i32 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_ne_i32 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x8a,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_ne_i32 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_ne_i32 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x8a,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_ne_i32 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_ne_i32 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x8a,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_ne_i32 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_ne_i32 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x8a,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_ne_i32 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_ne_i32 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x8a,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_ne_i32 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_ne_i32 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x8a,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_ne_i32 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_ne_i32 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x8a,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_ne_i32 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_ne_i32 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x8a,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_ne_i32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_ne_i32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x8a,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_ne_i32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_ne_i32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x8a,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_ne_i32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_ne_i32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x8a,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x8a,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_ne_i32 vcc_lo, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x8b,0x7c,0xff,0x6f,0x0d,0x30]
+# W64: v_cmp_ne_i32 vcc, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x8b,0x7c,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0x8b,0x7c,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_ne_u16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_ne_u16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x7a,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_ne_u16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_ne_u16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x7a,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_ne_u16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_ne_u16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x7a,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_ne_u16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_ne_u16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x7a,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_ne_u16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_ne_u16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x7a,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_ne_u16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_ne_u16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x7a,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_ne_u16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_ne_u16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x7a,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_ne_u16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_ne_u16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x7a,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_ne_u16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_ne_u16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x7a,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_ne_u16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_ne_u16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x7a,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_ne_u16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_ne_u16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x7a,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_ne_u16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_ne_u16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x7a,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_ne_u16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_ne_u16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x7a,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x7a,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_ne_u16 vcc_lo, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x7a,0x7c,0x7f,0x6f,0x0d,0x30]
+# W64: v_cmp_ne_u16 vcc, v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x7a,0x7c,0x7f,0x6f,0x0d,0x30]
+0xfa,0xfe,0x7a,0x7c,0x7f,0x6f,0x0d,0x30
+
+# W32: v_cmp_ne_u32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_ne_u32 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x9a,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_ne_u32 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_ne_u32 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x9a,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_ne_u32 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_ne_u32 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x9a,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_ne_u32 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_ne_u32 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x9a,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_ne_u32 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_ne_u32 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x9a,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_ne_u32 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_ne_u32 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x9a,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_ne_u32 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_ne_u32 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x9a,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_ne_u32 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_ne_u32 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x9a,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_ne_u32 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_ne_u32 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x9a,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_ne_u32 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_ne_u32 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x9a,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_ne_u32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_ne_u32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x9a,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_ne_u32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_ne_u32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x9a,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_ne_u32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_ne_u32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x9a,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x9a,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_ne_u32 vcc_lo, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x9b,0x7c,0xff,0x6f,0x0d,0x30]
+# W64: v_cmp_ne_u32 vcc, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x9b,0x7c,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0x9b,0x7c,0xff,0x6f,0x0d,0x30
+
+# W32: v_cmp_neq_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_neq_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x1a,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_neq_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_neq_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x1a,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_neq_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_neq_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x1a,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_neq_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_neq_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x1a,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_neq_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_neq_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x1a,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_neq_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_neq_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x1a,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_neq_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_neq_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x1a,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_neq_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_neq_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x1a,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_neq_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_neq_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x1a,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_neq_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_neq_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x1a,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_neq_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_neq_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x1a,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_neq_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_neq_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x1a,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_neq_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_neq_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x1a,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x1a,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_neq_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x1a,0x7c,0x7f,0x6f,0xfd,0x30]
+# W64: v_cmp_neq_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x1a,0x7c,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0x1a,0x7c,0x7f,0x6f,0xfd,0x30
+
+# W32: v_cmp_neq_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_neq_f32 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x3a,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_neq_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_neq_f32 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x3a,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_neq_f32 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_neq_f32 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x3a,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_neq_f32 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_neq_f32 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x3a,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_neq_f32 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_neq_f32 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x3a,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_neq_f32 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_neq_f32 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x3a,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_neq_f32 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_neq_f32 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x3a,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_neq_f32 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_neq_f32 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x3a,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_neq_f32 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_neq_f32 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x3a,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_neq_f32 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_neq_f32 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x3a,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_neq_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_neq_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x3a,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_neq_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_neq_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x3a,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_neq_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_neq_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x3a,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x3a,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_neq_f32 vcc_lo, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x3b,0x7c,0xff,0x6f,0xfd,0x30]
+# W64: v_cmp_neq_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x3b,0x7c,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0x3b,0x7c,0xff,0x6f,0xfd,0x30
+
+# W32: v_cmp_nge_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_nge_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x12,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_nge_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_nge_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x12,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_nge_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_nge_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x12,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_nge_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_nge_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x12,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_nge_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_nge_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x12,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_nge_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_nge_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x12,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_nge_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_nge_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x12,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_nge_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_nge_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x12,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_nge_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_nge_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x12,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_nge_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_nge_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x12,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_nge_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_nge_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x12,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_nge_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x12,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_nge_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x12,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x12,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_nge_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x12,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_nge_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x12,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x12,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_nge_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x12,0x7c,0x7f,0x6f,0xfd,0x30]
+# W64: v_cmp_nge_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x12,0x7c,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0x12,0x7c,0x7f,0x6f,0xfd,0x30
+
+# W32: v_cmp_nge_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_nge_f32 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x32,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_nge_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_nge_f32 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x32,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_nge_f32 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_nge_f32 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x32,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_nge_f32 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_nge_f32 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x32,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_nge_f32 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_nge_f32 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x32,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_nge_f32 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_nge_f32 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x32,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_nge_f32 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_nge_f32 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x32,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_nge_f32 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_nge_f32 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x32,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_nge_f32 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_nge_f32 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x32,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_nge_f32 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_nge_f32 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x32,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_nge_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_nge_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x32,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_nge_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x32,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_nge_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x32,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x32,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_nge_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x32,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_nge_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x32,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x32,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_nge_f32 vcc_lo, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x33,0x7c,0xff,0x6f,0xfd,0x30]
+# W64: v_cmp_nge_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x33,0x7c,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0x33,0x7c,0xff,0x6f,0xfd,0x30
+
+# W32: v_cmp_ngt_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_ngt_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x16,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_ngt_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_ngt_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x16,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_ngt_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_ngt_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x16,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_ngt_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_ngt_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x16,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_ngt_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_ngt_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x16,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_ngt_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_ngt_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x16,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_ngt_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_ngt_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x16,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_ngt_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_ngt_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x16,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_ngt_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_ngt_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x16,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_ngt_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_ngt_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x16,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_ngt_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_ngt_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x16,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_ngt_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x16,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_ngt_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x16,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x16,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_ngt_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x16,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_ngt_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x16,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x16,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_ngt_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x16,0x7c,0x7f,0x6f,0xfd,0x30]
+# W64: v_cmp_ngt_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x16,0x7c,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0x16,0x7c,0x7f,0x6f,0xfd,0x30
+
+# W32: v_cmp_ngt_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_ngt_f32 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x36,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_ngt_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_ngt_f32 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x36,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_ngt_f32 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_ngt_f32 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x36,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_ngt_f32 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_ngt_f32 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x36,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_ngt_f32 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_ngt_f32 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x36,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_ngt_f32 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_ngt_f32 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x36,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_ngt_f32 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_ngt_f32 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x36,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_ngt_f32 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_ngt_f32 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x36,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_ngt_f32 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_ngt_f32 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x36,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_ngt_f32 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_ngt_f32 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x36,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_ngt_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_ngt_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x36,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_ngt_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x36,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_ngt_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x36,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x36,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_ngt_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x36,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_ngt_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x36,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x36,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_ngt_f32 vcc_lo, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x37,0x7c,0xff,0x6f,0xfd,0x30]
+# W64: v_cmp_ngt_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x37,0x7c,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0x37,0x7c,0xff,0x6f,0xfd,0x30
+
+# W32: v_cmp_nle_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_nle_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x18,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_nle_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_nle_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x18,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_nle_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_nle_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x18,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_nle_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_nle_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x18,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_nle_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_nle_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x18,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_nle_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_nle_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x18,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_nle_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_nle_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x18,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_nle_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_nle_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x18,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_nle_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_nle_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x18,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_nle_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_nle_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x18,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_nle_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_nle_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x18,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_nle_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x18,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_nle_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x18,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x18,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_nle_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x18,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_nle_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x18,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x18,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_nle_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x18,0x7c,0x7f,0x6f,0xfd,0x30]
+# W64: v_cmp_nle_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x18,0x7c,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0x18,0x7c,0x7f,0x6f,0xfd,0x30
+
+# W32: v_cmp_nle_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_nle_f32 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x38,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_nle_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_nle_f32 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x38,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_nle_f32 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_nle_f32 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x38,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_nle_f32 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_nle_f32 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x38,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_nle_f32 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_nle_f32 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x38,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_nle_f32 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_nle_f32 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x38,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_nle_f32 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_nle_f32 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x38,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_nle_f32 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_nle_f32 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x38,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_nle_f32 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_nle_f32 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x38,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_nle_f32 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_nle_f32 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x38,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_nle_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_nle_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x38,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_nle_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x38,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_nle_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x38,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x38,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_nle_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x38,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_nle_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x38,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x38,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_nle_f32 vcc_lo, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x39,0x7c,0xff,0x6f,0xfd,0x30]
+# W64: v_cmp_nle_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x39,0x7c,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0x39,0x7c,0xff,0x6f,0xfd,0x30
+
+# W32: v_cmp_nlg_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_nlg_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x14,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_nlg_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_nlg_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x14,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_nlg_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_nlg_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x14,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_nlg_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_nlg_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x14,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_nlg_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_nlg_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x14,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_nlg_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_nlg_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x14,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_nlg_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_nlg_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x14,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_nlg_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_nlg_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x14,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_nlg_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_nlg_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x14,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_nlg_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_nlg_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x14,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_nlg_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_nlg_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x14,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_nlg_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x14,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_nlg_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x14,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x14,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_nlg_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x14,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_nlg_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x14,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x14,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_nlg_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x14,0x7c,0x7f,0x6f,0xfd,0x30]
+# W64: v_cmp_nlg_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x14,0x7c,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0x14,0x7c,0x7f,0x6f,0xfd,0x30
+
+# W32: v_cmp_nlg_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_nlg_f32 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x34,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_nlg_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_nlg_f32 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x34,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_nlg_f32 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_nlg_f32 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x34,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_nlg_f32 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_nlg_f32 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x34,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_nlg_f32 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_nlg_f32 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x34,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_nlg_f32 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_nlg_f32 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x34,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_nlg_f32 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_nlg_f32 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x34,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_nlg_f32 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_nlg_f32 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x34,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_nlg_f32 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_nlg_f32 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x34,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_nlg_f32 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_nlg_f32 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x34,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_nlg_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_nlg_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x34,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_nlg_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x34,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_nlg_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x34,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x34,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_nlg_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x34,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_nlg_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x34,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x34,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_nlg_f32 vcc_lo, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x35,0x7c,0xff,0x6f,0xfd,0x30]
+# W64: v_cmp_nlg_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x35,0x7c,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0x35,0x7c,0xff,0x6f,0xfd,0x30
+
+# W32: v_cmp_nlt_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_nlt_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x1c,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_nlt_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_nlt_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x1c,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_nlt_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_nlt_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x1c,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_nlt_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_nlt_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x1c,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_nlt_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_nlt_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x1c,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_nlt_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_nlt_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x1c,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_nlt_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_nlt_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x1c,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_nlt_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_nlt_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x1c,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_nlt_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_nlt_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x1c,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_nlt_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_nlt_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x1c,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_nlt_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_nlt_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x1c,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_nlt_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_nlt_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x1c,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_nlt_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_nlt_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x1c,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x1c,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_nlt_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x1c,0x7c,0x7f,0x6f,0xfd,0x30]
+# W64: v_cmp_nlt_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x1c,0x7c,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0x1c,0x7c,0x7f,0x6f,0xfd,0x30
+
+# W32: v_cmp_nlt_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_nlt_f32 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x3c,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_nlt_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_nlt_f32 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x3c,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_nlt_f32 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_nlt_f32 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x3c,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_nlt_f32 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_nlt_f32 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x3c,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_nlt_f32 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_nlt_f32 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x3c,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_nlt_f32 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_nlt_f32 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x3c,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_nlt_f32 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_nlt_f32 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x3c,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_nlt_f32 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_nlt_f32 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x3c,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_nlt_f32 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_nlt_f32 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x3c,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_nlt_f32 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_nlt_f32 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x3c,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_nlt_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_nlt_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x3c,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_nlt_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_nlt_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x3c,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_nlt_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_nlt_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x3c,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x3c,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_nlt_f32 vcc_lo, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x3d,0x7c,0xff,0x6f,0xfd,0x30]
+# W64: v_cmp_nlt_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x3d,0x7c,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0x3d,0x7c,0xff,0x6f,0xfd,0x30
+
+# W32: v_cmp_o_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_o_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0e,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_o_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_o_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0e,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_o_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_o_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0e,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_o_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_o_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0e,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_o_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_o_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0e,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_o_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_o_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0e,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_o_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_o_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0e,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_o_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_o_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0e,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_o_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_o_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0e,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_o_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_o_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0e,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_o_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_o_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0e,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_o_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_o_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0e,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_o_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_o_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0e,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0e,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_o_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x0e,0x7c,0x7f,0x6f,0xfd,0x30]
+# W64: v_cmp_o_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x0e,0x7c,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0x0e,0x7c,0x7f,0x6f,0xfd,0x30
+
+# W32: v_cmp_o_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_o_f32 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x2e,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_o_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_o_f32 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x2e,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_o_f32 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_o_f32 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x2e,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_o_f32 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_o_f32 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x2e,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_o_f32 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_o_f32 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x2e,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_o_f32 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_o_f32 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x2e,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_o_f32 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_o_f32 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x2e,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_o_f32 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_o_f32 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x2e,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_o_f32 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_o_f32 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x2e,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_o_f32 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_o_f32 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x2e,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_o_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_o_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x2e,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_o_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_o_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x2e,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_o_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_o_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x2e,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x2e,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_o_f32 vcc_lo, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x2f,0x7c,0xff,0x6f,0xfd,0x30]
+# W64: v_cmp_o_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x2f,0x7c,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0x2f,0x7c,0xff,0x6f,0xfd,0x30
+
+# W32: v_cmp_u_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_u_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x10,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_u_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_u_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x10,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_u_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_u_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x10,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_u_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_u_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x10,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_u_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_u_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x10,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_u_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_u_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x10,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_u_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_u_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x10,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_u_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_u_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x10,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_u_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_u_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x10,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_u_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_u_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x10,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_u_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_u_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x10,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_u_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x10,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_u_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x10,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x10,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_u_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x10,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_u_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x10,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x10,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_u_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x10,0x7c,0x7f,0x6f,0xfd,0x30]
+# W64: v_cmp_u_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x10,0x7c,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0x10,0x7c,0x7f,0x6f,0xfd,0x30
+
+# W32: v_cmp_u_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7c,0x01,0x1b,0x00,0xff]
+# W64: v_cmp_u_f32 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7c,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x30,0x7c,0x01,0x1b,0x00,0xff
+
+# W32: v_cmp_u_f32 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7c,0x01,0xe4,0x00,0xff]
+# W64: v_cmp_u_f32 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7c,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x30,0x7c,0x01,0xe4,0x00,0xff
+
+# W32: v_cmp_u_f32 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7c,0x01,0x40,0x01,0xff]
+# W64: v_cmp_u_f32 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7c,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x30,0x7c,0x01,0x40,0x01,0xff
+
+# W32: v_cmp_u_f32 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7c,0x01,0x41,0x01,0xff]
+# W64: v_cmp_u_f32 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7c,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x30,0x7c,0x01,0x41,0x01,0xff
+
+# W32: v_cmp_u_f32 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7c,0x01,0x01,0x01,0xff]
+# W64: v_cmp_u_f32 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7c,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x30,0x7c,0x01,0x01,0x01,0xff
+
+# W32: v_cmp_u_f32 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7c,0x01,0x0f,0x01,0xff]
+# W64: v_cmp_u_f32 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7c,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x30,0x7c,0x01,0x0f,0x01,0xff
+
+# W32: v_cmp_u_f32 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7c,0x01,0x11,0x01,0xff]
+# W64: v_cmp_u_f32 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7c,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x30,0x7c,0x01,0x11,0x01,0xff
+
+# W32: v_cmp_u_f32 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7c,0x01,0x1f,0x01,0xff]
+# W64: v_cmp_u_f32 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7c,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x30,0x7c,0x01,0x1f,0x01,0xff
+
+# W32: v_cmp_u_f32 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7c,0x01,0x21,0x01,0xff]
+# W64: v_cmp_u_f32 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7c,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x30,0x7c,0x01,0x21,0x01,0xff
+
+# W32: v_cmp_u_f32 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7c,0x01,0x2f,0x01,0xff]
+# W64: v_cmp_u_f32 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7c,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x30,0x7c,0x01,0x2f,0x01,0xff
+
+# W32: v_cmp_u_f32 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7c,0x01,0x50,0x01,0xff]
+# W64: v_cmp_u_f32 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7c,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x30,0x7c,0x01,0x50,0x01,0xff
+
+# W32: v_cmp_u_f32 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x30,0x7c,0x01,0x5f,0x01,0x01]
+# W64: v_cmp_u_f32 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x30,0x7c,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x30,0x7c,0x01,0x5f,0x01,0x01
+
+# W32: v_cmp_u_f32 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x30,0x7c,0x01,0x60,0x01,0x13]
+# W64: v_cmp_u_f32 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x30,0x7c,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x30,0x7c,0x01,0x60,0x01,0x13
+
+# W32: v_cmp_u_f32 vcc_lo, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x31,0x7c,0xff,0x6f,0xfd,0x30]
+# W64: v_cmp_u_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x31,0x7c,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0x31,0x7c,0xff,0x6f,0xfd,0x30
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp8.txt
new file mode 100644
index 000000000000..10518e0af8af
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp8.txt
@@ -0,0 +1,434 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W32
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W64
+
+# W32: v_cmp_class_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_class_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_class_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00]
+# W64: v_cmp_class_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00
+
+# W32: v_cmp_class_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfc,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_class_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfc,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0xfc,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_class_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfd,0x7c,0xff,0x00,0x00,0x00]
+# W64: v_cmp_class_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfd,0x7c,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xfd,0x7c,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_eq_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x04,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_eq_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x04,0x7c,0x7f,0x00,0x00,0x00]
+# W64: v_cmp_eq_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x04,0x7c,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x04,0x7c,0x7f,0x00,0x00,0x00
+
+# W32: v_cmp_eq_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x24,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x24,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x24,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_eq_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x25,0x7c,0xff,0x00,0x00,0x00]
+# W64: v_cmp_eq_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x25,0x7c,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x25,0x7c,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_eq_i16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x64,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_i16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x64,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x64,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_eq_i16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x64,0x7c,0x7f,0x00,0x00,0x00]
+# W64: v_cmp_eq_i16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x64,0x7c,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x64,0x7c,0x7f,0x00,0x00,0x00
+
+# W32: v_cmp_eq_i32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x84,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_i32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x84,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x84,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_eq_i32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x85,0x7c,0xff,0x00,0x00,0x00]
+# W64: v_cmp_eq_i32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x85,0x7c,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x85,0x7c,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_eq_u16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x74,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_u16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x74,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x74,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_eq_u16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x74,0x7c,0x7f,0x00,0x00,0x00]
+# W64: v_cmp_eq_u16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x74,0x7c,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x74,0x7c,0x7f,0x00,0x00,0x00
+
+# W32: v_cmp_eq_u32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x94,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_eq_u32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x94,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x94,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_eq_u32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x95,0x7c,0xff,0x00,0x00,0x00]
+# W64: v_cmp_eq_u32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x95,0x7c,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x95,0x7c,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_ge_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0c,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0c,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0c,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ge_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x0c,0x7c,0x7f,0x00,0x00,0x00]
+# W64: v_cmp_ge_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x0c,0x7c,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x0c,0x7c,0x7f,0x00,0x00,0x00
+
+# W32: v_cmp_ge_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x2c,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x2c,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x2c,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ge_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x2d,0x7c,0xff,0x00,0x00,0x00]
+# W64: v_cmp_ge_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x2d,0x7c,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x2d,0x7c,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_ge_i16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x6c,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_i16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x6c,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x6c,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ge_i16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x6c,0x7c,0x7f,0x00,0x00,0x00]
+# W64: v_cmp_ge_i16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x6c,0x7c,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x6c,0x7c,0x7f,0x00,0x00,0x00
+
+# W32: v_cmp_ge_i32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x8c,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_i32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x8c,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x8c,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ge_i32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x8d,0x7c,0xff,0x00,0x00,0x00]
+# W64: v_cmp_ge_i32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x8d,0x7c,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x8d,0x7c,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_ge_u16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x7c,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_u16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x7c,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x7c,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ge_u16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x7c,0x7c,0x7f,0x00,0x00,0x00]
+# W64: v_cmp_ge_u16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x7c,0x7c,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x7c,0x7c,0x7f,0x00,0x00,0x00
+
+# W32: v_cmp_ge_u32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x9c,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ge_u32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x9c,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x9c,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ge_u32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x9d,0x7c,0xff,0x00,0x00,0x00]
+# W64: v_cmp_ge_u32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x9d,0x7c,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x9d,0x7c,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_gt_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x08,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x08,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x08,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_gt_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x08,0x7c,0x7f,0x00,0x00,0x00]
+# W64: v_cmp_gt_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x08,0x7c,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x08,0x7c,0x7f,0x00,0x00,0x00
+
+# W32: v_cmp_gt_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x28,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x28,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x28,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_gt_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x29,0x7c,0xff,0x00,0x00,0x00]
+# W64: v_cmp_gt_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x29,0x7c,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x29,0x7c,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_gt_i16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x68,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_i16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x68,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x68,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_gt_i16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x68,0x7c,0x7f,0x00,0x00,0x00]
+# W64: v_cmp_gt_i16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x68,0x7c,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x68,0x7c,0x7f,0x00,0x00,0x00
+
+# W32: v_cmp_gt_i32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x88,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_i32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x88,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x88,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_gt_i32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x89,0x7c,0xff,0x00,0x00,0x00]
+# W64: v_cmp_gt_i32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x89,0x7c,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x89,0x7c,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_gt_u16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x78,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_u16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x78,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x78,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_gt_u16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x78,0x7c,0x7f,0x00,0x00,0x00]
+# W64: v_cmp_gt_u16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x78,0x7c,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x78,0x7c,0x7f,0x00,0x00,0x00
+
+# W32: v_cmp_gt_u32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x98,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_gt_u32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x98,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x98,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_gt_u32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x99,0x7c,0xff,0x00,0x00,0x00]
+# W64: v_cmp_gt_u32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x99,0x7c,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x99,0x7c,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_le_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x06,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x06,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x06,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_le_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x06,0x7c,0x7f,0x00,0x00,0x00]
+# W64: v_cmp_le_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x06,0x7c,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x06,0x7c,0x7f,0x00,0x00,0x00
+
+# W32: v_cmp_le_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x26,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x26,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x26,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_le_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x27,0x7c,0xff,0x00,0x00,0x00]
+# W64: v_cmp_le_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x27,0x7c,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x27,0x7c,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_le_i16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x66,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_i16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x66,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x66,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_le_i16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x66,0x7c,0x7f,0x00,0x00,0x00]
+# W64: v_cmp_le_i16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x66,0x7c,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x66,0x7c,0x7f,0x00,0x00,0x00
+
+# W32: v_cmp_le_i32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x86,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_i32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x86,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x86,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_le_i32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x87,0x7c,0xff,0x00,0x00,0x00]
+# W64: v_cmp_le_i32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x87,0x7c,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x87,0x7c,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_le_u16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x76,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_u16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x76,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x76,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_le_u16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x76,0x7c,0x7f,0x00,0x00,0x00]
+# W64: v_cmp_le_u16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x76,0x7c,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x76,0x7c,0x7f,0x00,0x00,0x00
+
+# W32: v_cmp_le_u32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x96,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_le_u32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x96,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x96,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_le_u32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x97,0x7c,0xff,0x00,0x00,0x00]
+# W64: v_cmp_le_u32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x97,0x7c,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x97,0x7c,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_lg_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lg_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lg_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x0a,0x7c,0x7f,0x00,0x00,0x00]
+# W64: v_cmp_lg_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x0a,0x7c,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x0a,0x7c,0x7f,0x00,0x00,0x00
+
+# W32: v_cmp_lg_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x2a,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lg_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x2a,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x2a,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lg_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x2b,0x7c,0xff,0x00,0x00,0x00]
+# W64: v_cmp_lg_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x2b,0x7c,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x2b,0x7c,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_lt_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x02,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x02,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x02,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lt_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x02,0x7c,0x7f,0x00,0x00,0x00]
+# W64: v_cmp_lt_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x02,0x7c,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x02,0x7c,0x7f,0x00,0x00,0x00
+
+# W32: v_cmp_lt_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x22,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x22,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x22,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lt_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x23,0x7c,0xff,0x00,0x00,0x00]
+# W64: v_cmp_lt_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x23,0x7c,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x23,0x7c,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_lt_i16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x62,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_i16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x62,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x62,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lt_i16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x62,0x7c,0x7f,0x00,0x00,0x00]
+# W64: v_cmp_lt_i16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x62,0x7c,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x62,0x7c,0x7f,0x00,0x00,0x00
+
+# W32: v_cmp_lt_i32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x82,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_i32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x82,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x82,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lt_i32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x83,0x7c,0xff,0x00,0x00,0x00]
+# W64: v_cmp_lt_i32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x83,0x7c,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x83,0x7c,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_lt_u16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x72,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_u16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x72,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x72,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lt_u16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x72,0x7c,0x7f,0x00,0x00,0x00]
+# W64: v_cmp_lt_u16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x72,0x7c,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x72,0x7c,0x7f,0x00,0x00,0x00
+
+# W32: v_cmp_lt_u32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x92,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_lt_u32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x92,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x92,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_lt_u32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x93,0x7c,0xff,0x00,0x00,0x00]
+# W64: v_cmp_lt_u32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x93,0x7c,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x93,0x7c,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_ne_i16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x6a,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ne_i16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x6a,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x6a,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ne_i16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x6a,0x7c,0x7f,0x00,0x00,0x00]
+# W64: v_cmp_ne_i16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x6a,0x7c,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x6a,0x7c,0x7f,0x00,0x00,0x00
+
+# W32: v_cmp_ne_i32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x8a,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ne_i32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x8a,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x8a,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ne_i32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x8b,0x7c,0xff,0x00,0x00,0x00]
+# W64: v_cmp_ne_i32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x8b,0x7c,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x8b,0x7c,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_ne_u16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x7a,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ne_u16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x7a,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x7a,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ne_u16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x7a,0x7c,0x7f,0x00,0x00,0x00]
+# W64: v_cmp_ne_u16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x7a,0x7c,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x7a,0x7c,0x7f,0x00,0x00,0x00
+
+# W32: v_cmp_ne_u32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x9a,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ne_u32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x9a,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x9a,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ne_u32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x9b,0x7c,0xff,0x00,0x00,0x00]
+# W64: v_cmp_ne_u32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x9b,0x7c,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x9b,0x7c,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_neq_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x1a,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_neq_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x1a,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x1a,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_neq_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x1a,0x7c,0x7f,0x00,0x00,0x00]
+# W64: v_cmp_neq_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x1a,0x7c,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x1a,0x7c,0x7f,0x00,0x00,0x00
+
+# W32: v_cmp_neq_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x3a,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_neq_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x3a,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x3a,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_neq_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x3b,0x7c,0xff,0x00,0x00,0x00]
+# W64: v_cmp_neq_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x3b,0x7c,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x3b,0x7c,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_nge_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x12,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nge_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x12,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x12,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nge_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x12,0x7c,0x7f,0x00,0x00,0x00]
+# W64: v_cmp_nge_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x12,0x7c,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x12,0x7c,0x7f,0x00,0x00,0x00
+
+# W32: v_cmp_nge_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x32,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nge_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x32,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x32,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nge_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x33,0x7c,0xff,0x00,0x00,0x00]
+# W64: v_cmp_nge_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x33,0x7c,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x33,0x7c,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_ngt_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x16,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ngt_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x16,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x16,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ngt_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x16,0x7c,0x7f,0x00,0x00,0x00]
+# W64: v_cmp_ngt_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x16,0x7c,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x16,0x7c,0x7f,0x00,0x00,0x00
+
+# W32: v_cmp_ngt_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x36,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_ngt_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x36,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x36,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_ngt_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x37,0x7c,0xff,0x00,0x00,0x00]
+# W64: v_cmp_ngt_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x37,0x7c,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x37,0x7c,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_nle_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x18,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nle_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x18,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x18,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nle_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x18,0x7c,0x7f,0x00,0x00,0x00]
+# W64: v_cmp_nle_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x18,0x7c,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x18,0x7c,0x7f,0x00,0x00,0x00
+
+# W32: v_cmp_nle_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x38,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nle_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x38,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x38,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nle_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x39,0x7c,0xff,0x00,0x00,0x00]
+# W64: v_cmp_nle_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x39,0x7c,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x39,0x7c,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_nlg_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x14,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nlg_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x14,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x14,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nlg_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x14,0x7c,0x7f,0x00,0x00,0x00]
+# W64: v_cmp_nlg_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x14,0x7c,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x14,0x7c,0x7f,0x00,0x00,0x00
+
+# W32: v_cmp_nlg_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x34,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nlg_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x34,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x34,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nlg_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x35,0x7c,0xff,0x00,0x00,0x00]
+# W64: v_cmp_nlg_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x35,0x7c,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x35,0x7c,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_nlt_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x1c,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nlt_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x1c,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x1c,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nlt_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x1c,0x7c,0x7f,0x00,0x00,0x00]
+# W64: v_cmp_nlt_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x1c,0x7c,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x1c,0x7c,0x7f,0x00,0x00,0x00
+
+# W32: v_cmp_nlt_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x3c,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_nlt_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x3c,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x3c,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_nlt_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x3d,0x7c,0xff,0x00,0x00,0x00]
+# W64: v_cmp_nlt_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x3d,0x7c,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x3d,0x7c,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_o_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0e,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_o_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0e,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0e,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_o_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x0e,0x7c,0x7f,0x00,0x00,0x00]
+# W64: v_cmp_o_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x0e,0x7c,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x0e,0x7c,0x7f,0x00,0x00,0x00
+
+# W32: v_cmp_o_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x2e,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_o_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x2e,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x2e,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_o_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x2f,0x7c,0xff,0x00,0x00,0x00]
+# W64: v_cmp_o_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x2f,0x7c,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x2f,0x7c,0xff,0x00,0x00,0x00
+
+# W32: v_cmp_u_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x10,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_u_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x10,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x10,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_u_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x10,0x7c,0x7f,0x00,0x00,0x00]
+# W64: v_cmp_u_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x10,0x7c,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x10,0x7c,0x7f,0x00,0x00,0x00
+
+# W32: v_cmp_u_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x30,0x7c,0x01,0x77,0x39,0x05]
+# W64: v_cmp_u_f32 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x30,0x7c,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x30,0x7c,0x01,0x77,0x39,0x05
+
+# W32: v_cmp_u_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x31,0x7c,0xff,0x00,0x00,0x00]
+# W64: v_cmp_u_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x31,0x7c,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x31,0x7c,0xff,0x00,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx.txt
new file mode 100644
index 000000000000..96d5e82e23b3
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx.txt
@@ -0,0 +1,3404 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=GFX12
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=GFX12
+
+# GFX12: v_cmpx_class_f16_e32 v1, v2             ; encoding: [0x01,0x05,0xfa,0x7d]
+0x01,0x05,0xfa,0x7d
+
+# GFX12: v_cmpx_class_f16_e32 v127, v2           ; encoding: [0x7f,0x05,0xfa,0x7d]
+0x7f,0x05,0xfa,0x7d
+
+# GFX12: v_cmpx_class_f16_e32 s1, v2             ; encoding: [0x01,0x04,0xfa,0x7d]
+0x01,0x04,0xfa,0x7d
+
+# GFX12: v_cmpx_class_f16_e32 s105, v2           ; encoding: [0x69,0x04,0xfa,0x7d]
+0x69,0x04,0xfa,0x7d
+
+# GFX12: v_cmpx_class_f16_e32 vcc_lo, v2         ; encoding: [0x6a,0x04,0xfa,0x7d]
+0x6a,0x04,0xfa,0x7d
+
+# GFX12: v_cmpx_class_f16_e32 vcc_hi, v2         ; encoding: [0x6b,0x04,0xfa,0x7d]
+0x6b,0x04,0xfa,0x7d
+
+# GFX12: v_cmpx_class_f16_e32 ttmp15, v2         ; encoding: [0x7b,0x04,0xfa,0x7d]
+0x7b,0x04,0xfa,0x7d
+
+# GFX12: v_cmpx_class_f16_e32 m0, v2             ; encoding: [0x7d,0x04,0xfa,0x7d]
+0x7d,0x04,0xfa,0x7d
+
+# GFX12: v_cmpx_class_f16_e32 exec_lo, v2        ; encoding: [0x7e,0x04,0xfa,0x7d]
+0x7e,0x04,0xfa,0x7d
+
+# GFX12: v_cmpx_class_f16_e32 exec_hi, v2        ; encoding: [0x7f,0x04,0xfa,0x7d]
+0x7f,0x04,0xfa,0x7d
+
+# GFX12: v_cmpx_class_f16_e32 null, v2           ; encoding: [0x7c,0x04,0xfa,0x7d]
+0x7c,0x04,0xfa,0x7d
+
+# GFX12: v_cmpx_class_f16_e32 -1, v2             ; encoding: [0xc1,0x04,0xfa,0x7d]
+0xc1,0x04,0xfa,0x7d
+
+# GFX12: v_cmpx_class_f16_e32 0.5, v2            ; encoding: [0xf0,0x04,0xfa,0x7d]
+0xf0,0x04,0xfa,0x7d
+
+# GFX12: v_cmpx_class_f16_e32 src_scc, v2        ; encoding: [0xfd,0x04,0xfa,0x7d]
+0xfd,0x04,0xfa,0x7d
+
+# GFX12: v_cmpx_class_f16_e32 0xfe0b, v127       ; encoding: [0xff,0xfe,0xfa,0x7d,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0xfa,0x7d,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_class_f32_e32 v1, v2             ; encoding: [0x01,0x05,0xfc,0x7d]
+0x01,0x05,0xfc,0x7d
+
+# GFX12: v_cmpx_class_f32_e32 v255, v2           ; encoding: [0xff,0x05,0xfc,0x7d]
+0xff,0x05,0xfc,0x7d
+
+# GFX12: v_cmpx_class_f32_e32 s1, v2             ; encoding: [0x01,0x04,0xfc,0x7d]
+0x01,0x04,0xfc,0x7d
+
+# GFX12: v_cmpx_class_f32_e32 s105, v2           ; encoding: [0x69,0x04,0xfc,0x7d]
+0x69,0x04,0xfc,0x7d
+
+# GFX12: v_cmpx_class_f32_e32 vcc_lo, v2         ; encoding: [0x6a,0x04,0xfc,0x7d]
+0x6a,0x04,0xfc,0x7d
+
+# GFX12: v_cmpx_class_f32_e32 vcc_hi, v2         ; encoding: [0x6b,0x04,0xfc,0x7d]
+0x6b,0x04,0xfc,0x7d
+
+# GFX12: v_cmpx_class_f32_e32 ttmp15, v2         ; encoding: [0x7b,0x04,0xfc,0x7d]
+0x7b,0x04,0xfc,0x7d
+
+# GFX12: v_cmpx_class_f32_e32 m0, v2             ; encoding: [0x7d,0x04,0xfc,0x7d]
+0x7d,0x04,0xfc,0x7d
+
+# GFX12: v_cmpx_class_f32_e32 exec_lo, v2        ; encoding: [0x7e,0x04,0xfc,0x7d]
+0x7e,0x04,0xfc,0x7d
+
+# GFX12: v_cmpx_class_f32_e32 exec_hi, v2        ; encoding: [0x7f,0x04,0xfc,0x7d]
+0x7f,0x04,0xfc,0x7d
+
+# GFX12: v_cmpx_class_f32_e32 null, v2           ; encoding: [0x7c,0x04,0xfc,0x7d]
+0x7c,0x04,0xfc,0x7d
+
+# GFX12: v_cmpx_class_f32_e32 -1, v2             ; encoding: [0xc1,0x04,0xfc,0x7d]
+0xc1,0x04,0xfc,0x7d
+
+# GFX12: v_cmpx_class_f32_e32 0.5, v2            ; encoding: [0xf0,0x04,0xfc,0x7d]
+0xf0,0x04,0xfc,0x7d
+
+# GFX12: v_cmpx_class_f32_e32 src_scc, v2        ; encoding: [0xfd,0x04,0xfc,0x7d]
+0xfd,0x04,0xfc,0x7d
+
+# GFX12: v_cmpx_class_f32_e32 0xaf123456, v255   ; encoding: [0xff,0xfe,0xfd,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xfd,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_class_f64_e32 v[1:2], v2         ; encoding: [0x01,0x05,0xfe,0x7d]
+0x01,0x05,0xfe,0x7d
+
+# GFX12: v_cmpx_class_f64_e32 v[254:255], v2     ; encoding: [0xfe,0x05,0xfe,0x7d]
+0xfe,0x05,0xfe,0x7d
+
+# GFX12: v_cmpx_class_f64_e32 s[2:3], v2         ; encoding: [0x02,0x04,0xfe,0x7d]
+0x02,0x04,0xfe,0x7d
+
+# GFX12: v_cmpx_class_f64_e32 s[104:105], v2     ; encoding: [0x68,0x04,0xfe,0x7d]
+0x68,0x04,0xfe,0x7d
+
+# GFX12: v_cmpx_class_f64_e32 vcc, v2            ; encoding: [0x6a,0x04,0xfe,0x7d]
+0x6a,0x04,0xfe,0x7d
+
+# GFX12: v_cmpx_class_f64_e32 ttmp[14:15], v2    ; encoding: [0x7a,0x04,0xfe,0x7d]
+0x7a,0x04,0xfe,0x7d
+
+# GFX12: v_cmpx_class_f64_e32 exec, v2           ; encoding: [0x7e,0x04,0xfe,0x7d]
+0x7e,0x04,0xfe,0x7d
+
+# GFX12: v_cmpx_class_f64_e32 null, v2           ; encoding: [0x7c,0x04,0xfe,0x7d]
+0x7c,0x04,0xfe,0x7d
+
+# GFX12: v_cmpx_class_f64_e32 -1, v2             ; encoding: [0xc1,0x04,0xfe,0x7d]
+0xc1,0x04,0xfe,0x7d
+
+# GFX12: v_cmpx_class_f64_e32 0.5, v2            ; encoding: [0xf0,0x04,0xfe,0x7d]
+0xf0,0x04,0xfe,0x7d
+
+# GFX12: v_cmpx_class_f64_e32 src_scc, v2        ; encoding: [0xfd,0x04,0xfe,0x7d]
+0xfd,0x04,0xfe,0x7d
+
+# GFX12: v_cmpx_class_f64_e32 0xaf123456, v255   ; encoding: [0xff,0xfe,0xff,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xff,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_eq_f16_e32 v1, v2                ; encoding: [0x01,0x05,0x04,0x7d]
+0x01,0x05,0x04,0x7d
+
+# GFX12: v_cmpx_eq_f16_e32 v127, v2              ; encoding: [0x7f,0x05,0x04,0x7d]
+0x7f,0x05,0x04,0x7d
+
+# GFX12: v_cmpx_eq_f16_e32 s1, v2                ; encoding: [0x01,0x04,0x04,0x7d]
+0x01,0x04,0x04,0x7d
+
+# GFX12: v_cmpx_eq_f16_e32 s105, v2              ; encoding: [0x69,0x04,0x04,0x7d]
+0x69,0x04,0x04,0x7d
+
+# GFX12: v_cmpx_eq_f16_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x04,0x7d]
+0x6a,0x04,0x04,0x7d
+
+# GFX12: v_cmpx_eq_f16_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x04,0x7d]
+0x6b,0x04,0x04,0x7d
+
+# GFX12: v_cmpx_eq_f16_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x04,0x7d]
+0x7b,0x04,0x04,0x7d
+
+# GFX12: v_cmpx_eq_f16_e32 m0, v2                ; encoding: [0x7d,0x04,0x04,0x7d]
+0x7d,0x04,0x04,0x7d
+
+# GFX12: v_cmpx_eq_f16_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x04,0x7d]
+0x7e,0x04,0x04,0x7d
+
+# GFX12: v_cmpx_eq_f16_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x04,0x7d]
+0x7f,0x04,0x04,0x7d
+
+# GFX12: v_cmpx_eq_f16_e32 null, v2              ; encoding: [0x7c,0x04,0x04,0x7d]
+0x7c,0x04,0x04,0x7d
+
+# GFX12: v_cmpx_eq_f16_e32 -1, v2                ; encoding: [0xc1,0x04,0x04,0x7d]
+0xc1,0x04,0x04,0x7d
+
+# GFX12: v_cmpx_eq_f16_e32 0.5, v2               ; encoding: [0xf0,0x04,0x04,0x7d]
+0xf0,0x04,0x04,0x7d
+
+# GFX12: v_cmpx_eq_f16_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x04,0x7d]
+0xfd,0x04,0x04,0x7d
+
+# GFX12: v_cmpx_eq_f16_e32 0xfe0b, v127          ; encoding: [0xff,0xfe,0x04,0x7d,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x04,0x7d,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_eq_f32_e32 v1, v2                ; encoding: [0x01,0x05,0x24,0x7d]
+0x01,0x05,0x24,0x7d
+
+# GFX12: v_cmpx_eq_f32_e32 v255, v2              ; encoding: [0xff,0x05,0x24,0x7d]
+0xff,0x05,0x24,0x7d
+
+# GFX12: v_cmpx_eq_f32_e32 s1, v2                ; encoding: [0x01,0x04,0x24,0x7d]
+0x01,0x04,0x24,0x7d
+
+# GFX12: v_cmpx_eq_f32_e32 s105, v2              ; encoding: [0x69,0x04,0x24,0x7d]
+0x69,0x04,0x24,0x7d
+
+# GFX12: v_cmpx_eq_f32_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x24,0x7d]
+0x6a,0x04,0x24,0x7d
+
+# GFX12: v_cmpx_eq_f32_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x24,0x7d]
+0x6b,0x04,0x24,0x7d
+
+# GFX12: v_cmpx_eq_f32_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x24,0x7d]
+0x7b,0x04,0x24,0x7d
+
+# GFX12: v_cmpx_eq_f32_e32 m0, v2                ; encoding: [0x7d,0x04,0x24,0x7d]
+0x7d,0x04,0x24,0x7d
+
+# GFX12: v_cmpx_eq_f32_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x24,0x7d]
+0x7e,0x04,0x24,0x7d
+
+# GFX12: v_cmpx_eq_f32_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x24,0x7d]
+0x7f,0x04,0x24,0x7d
+
+# GFX12: v_cmpx_eq_f32_e32 null, v2              ; encoding: [0x7c,0x04,0x24,0x7d]
+0x7c,0x04,0x24,0x7d
+
+# GFX12: v_cmpx_eq_f32_e32 -1, v2                ; encoding: [0xc1,0x04,0x24,0x7d]
+0xc1,0x04,0x24,0x7d
+
+# GFX12: v_cmpx_eq_f32_e32 0.5, v2               ; encoding: [0xf0,0x04,0x24,0x7d]
+0xf0,0x04,0x24,0x7d
+
+# GFX12: v_cmpx_eq_f32_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x24,0x7d]
+0xfd,0x04,0x24,0x7d
+
+# GFX12: v_cmpx_eq_f32_e32 0xaf123456, v255      ; encoding: [0xff,0xfe,0x25,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x25,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_eq_f64_e32 v[1:2], v[2:3]        ; encoding: [0x01,0x05,0x44,0x7d]
+0x01,0x05,0x44,0x7d
+
+# GFX12: v_cmpx_eq_f64_e32 v[254:255], v[2:3]    ; encoding: [0xfe,0x05,0x44,0x7d]
+0xfe,0x05,0x44,0x7d
+
+# GFX12: v_cmpx_eq_f64_e32 s[2:3], v[2:3]        ; encoding: [0x02,0x04,0x44,0x7d]
+0x02,0x04,0x44,0x7d
+
+# GFX12: v_cmpx_eq_f64_e32 s[104:105], v[2:3]    ; encoding: [0x68,0x04,0x44,0x7d]
+0x68,0x04,0x44,0x7d
+
+# GFX12: v_cmpx_eq_f64_e32 vcc, v[2:3]           ; encoding: [0x6a,0x04,0x44,0x7d]
+0x6a,0x04,0x44,0x7d
+
+# GFX12: v_cmpx_eq_f64_e32 ttmp[14:15], v[2:3]   ; encoding: [0x7a,0x04,0x44,0x7d]
+0x7a,0x04,0x44,0x7d
+
+# GFX12: v_cmpx_eq_f64_e32 exec, v[2:3]          ; encoding: [0x7e,0x04,0x44,0x7d]
+0x7e,0x04,0x44,0x7d
+
+# GFX12: v_cmpx_eq_f64_e32 null, v[2:3]          ; encoding: [0x7c,0x04,0x44,0x7d]
+0x7c,0x04,0x44,0x7d
+
+# GFX12: v_cmpx_eq_f64_e32 -1, v[2:3]            ; encoding: [0xc1,0x04,0x44,0x7d]
+0xc1,0x04,0x44,0x7d
+
+# GFX12: v_cmpx_eq_f64_e32 0.5, v[2:3]           ; encoding: [0xf0,0x04,0x44,0x7d]
+0xf0,0x04,0x44,0x7d
+
+# GFX12: v_cmpx_eq_f64_e32 src_scc, v[2:3]       ; encoding: [0xfd,0x04,0x44,0x7d]
+0xfd,0x04,0x44,0x7d
+
+# GFX12: v_cmpx_eq_f64_e32 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x45,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x45,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_eq_i16_e32 v1, v2                ; encoding: [0x01,0x05,0x64,0x7d]
+0x01,0x05,0x64,0x7d
+
+# GFX12: v_cmpx_eq_i16_e32 v127, v2              ; encoding: [0x7f,0x05,0x64,0x7d]
+0x7f,0x05,0x64,0x7d
+
+# GFX12: v_cmpx_eq_i16_e32 s1, v2                ; encoding: [0x01,0x04,0x64,0x7d]
+0x01,0x04,0x64,0x7d
+
+# GFX12: v_cmpx_eq_i16_e32 s105, v2              ; encoding: [0x69,0x04,0x64,0x7d]
+0x69,0x04,0x64,0x7d
+
+# GFX12: v_cmpx_eq_i16_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x64,0x7d]
+0x6a,0x04,0x64,0x7d
+
+# GFX12: v_cmpx_eq_i16_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x64,0x7d]
+0x6b,0x04,0x64,0x7d
+
+# GFX12: v_cmpx_eq_i16_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x64,0x7d]
+0x7b,0x04,0x64,0x7d
+
+# GFX12: v_cmpx_eq_i16_e32 m0, v2                ; encoding: [0x7d,0x04,0x64,0x7d]
+0x7d,0x04,0x64,0x7d
+
+# GFX12: v_cmpx_eq_i16_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x64,0x7d]
+0x7e,0x04,0x64,0x7d
+
+# GFX12: v_cmpx_eq_i16_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x64,0x7d]
+0x7f,0x04,0x64,0x7d
+
+# GFX12: v_cmpx_eq_i16_e32 null, v2              ; encoding: [0x7c,0x04,0x64,0x7d]
+0x7c,0x04,0x64,0x7d
+
+# GFX12: v_cmpx_eq_i16_e32 -1, v2                ; encoding: [0xc1,0x04,0x64,0x7d]
+0xc1,0x04,0x64,0x7d
+
+# GFX12: v_cmpx_eq_i16_e32 0x3800, v2
+0xf0,0x04,0x64,0x7d
+
+# GFX12: v_cmpx_eq_i16_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x64,0x7d]
+0xfd,0x04,0x64,0x7d
+
+# GFX12: v_cmpx_eq_i16_e32 0xfe0b, v127          ; encoding: [0xff,0xfe,0x64,0x7d,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x64,0x7d,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_eq_i32_e32 v1, v2                ; encoding: [0x01,0x05,0x84,0x7d]
+0x01,0x05,0x84,0x7d
+
+# GFX12: v_cmpx_eq_i32_e32 v255, v2              ; encoding: [0xff,0x05,0x84,0x7d]
+0xff,0x05,0x84,0x7d
+
+# GFX12: v_cmpx_eq_i32_e32 s1, v2                ; encoding: [0x01,0x04,0x84,0x7d]
+0x01,0x04,0x84,0x7d
+
+# GFX12: v_cmpx_eq_i32_e32 s105, v2              ; encoding: [0x69,0x04,0x84,0x7d]
+0x69,0x04,0x84,0x7d
+
+# GFX12: v_cmpx_eq_i32_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x84,0x7d]
+0x6a,0x04,0x84,0x7d
+
+# GFX12: v_cmpx_eq_i32_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x84,0x7d]
+0x6b,0x04,0x84,0x7d
+
+# GFX12: v_cmpx_eq_i32_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x84,0x7d]
+0x7b,0x04,0x84,0x7d
+
+# GFX12: v_cmpx_eq_i32_e32 m0, v2                ; encoding: [0x7d,0x04,0x84,0x7d]
+0x7d,0x04,0x84,0x7d
+
+# GFX12: v_cmpx_eq_i32_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x84,0x7d]
+0x7e,0x04,0x84,0x7d
+
+# GFX12: v_cmpx_eq_i32_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x84,0x7d]
+0x7f,0x04,0x84,0x7d
+
+# GFX12: v_cmpx_eq_i32_e32 null, v2              ; encoding: [0x7c,0x04,0x84,0x7d]
+0x7c,0x04,0x84,0x7d
+
+# GFX12: v_cmpx_eq_i32_e32 -1, v2                ; encoding: [0xc1,0x04,0x84,0x7d]
+0xc1,0x04,0x84,0x7d
+
+# GFX12: v_cmpx_eq_i32_e32 0.5, v2               ; encoding: [0xf0,0x04,0x84,0x7d]
+0xf0,0x04,0x84,0x7d
+
+# GFX12: v_cmpx_eq_i32_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x84,0x7d]
+0xfd,0x04,0x84,0x7d
+
+# GFX12: v_cmpx_eq_i32_e32 0xaf123456, v255      ; encoding: [0xff,0xfe,0x85,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x85,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_eq_i64_e32 v[1:2], v[2:3]        ; encoding: [0x01,0x05,0xa4,0x7d]
+0x01,0x05,0xa4,0x7d
+
+# GFX12: v_cmpx_eq_i64_e32 v[254:255], v[2:3]    ; encoding: [0xfe,0x05,0xa4,0x7d]
+0xfe,0x05,0xa4,0x7d
+
+# GFX12: v_cmpx_eq_i64_e32 s[2:3], v[2:3]        ; encoding: [0x02,0x04,0xa4,0x7d]
+0x02,0x04,0xa4,0x7d
+
+# GFX12: v_cmpx_eq_i64_e32 s[104:105], v[2:3]    ; encoding: [0x68,0x04,0xa4,0x7d]
+0x68,0x04,0xa4,0x7d
+
+# GFX12: v_cmpx_eq_i64_e32 vcc, v[2:3]           ; encoding: [0x6a,0x04,0xa4,0x7d]
+0x6a,0x04,0xa4,0x7d
+
+# GFX12: v_cmpx_eq_i64_e32 ttmp[14:15], v[2:3]   ; encoding: [0x7a,0x04,0xa4,0x7d]
+0x7a,0x04,0xa4,0x7d
+
+# GFX12: v_cmpx_eq_i64_e32 exec, v[2:3]          ; encoding: [0x7e,0x04,0xa4,0x7d]
+0x7e,0x04,0xa4,0x7d
+
+# GFX12: v_cmpx_eq_i64_e32 null, v[2:3]          ; encoding: [0x7c,0x04,0xa4,0x7d]
+0x7c,0x04,0xa4,0x7d
+
+# GFX12: v_cmpx_eq_i64_e32 -1, v[2:3]            ; encoding: [0xc1,0x04,0xa4,0x7d]
+0xc1,0x04,0xa4,0x7d
+
+# GFX12: v_cmpx_eq_i64_e32 0.5, v[2:3]           ; encoding: [0xf0,0x04,0xa4,0x7d]
+0xf0,0x04,0xa4,0x7d
+
+# GFX12: v_cmpx_eq_i64_e32 src_scc, v[2:3]       ; encoding: [0xfd,0x04,0xa4,0x7d]
+0xfd,0x04,0xa4,0x7d
+
+# GFX12: v_cmpx_eq_i64_e32 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xa5,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xa5,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_eq_u16_e32 v1, v2                ; encoding: [0x01,0x05,0x74,0x7d]
+0x01,0x05,0x74,0x7d
+
+# GFX12: v_cmpx_eq_u16_e32 v127, v2              ; encoding: [0x7f,0x05,0x74,0x7d]
+0x7f,0x05,0x74,0x7d
+
+# GFX12: v_cmpx_eq_u16_e32 s1, v2                ; encoding: [0x01,0x04,0x74,0x7d]
+0x01,0x04,0x74,0x7d
+
+# GFX12: v_cmpx_eq_u16_e32 s105, v2              ; encoding: [0x69,0x04,0x74,0x7d]
+0x69,0x04,0x74,0x7d
+
+# GFX12: v_cmpx_eq_u16_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x74,0x7d]
+0x6a,0x04,0x74,0x7d
+
+# GFX12: v_cmpx_eq_u16_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x74,0x7d]
+0x6b,0x04,0x74,0x7d
+
+# GFX12: v_cmpx_eq_u16_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x74,0x7d]
+0x7b,0x04,0x74,0x7d
+
+# GFX12: v_cmpx_eq_u16_e32 m0, v2                ; encoding: [0x7d,0x04,0x74,0x7d]
+0x7d,0x04,0x74,0x7d
+
+# GFX12: v_cmpx_eq_u16_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x74,0x7d]
+0x7e,0x04,0x74,0x7d
+
+# GFX12: v_cmpx_eq_u16_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x74,0x7d]
+0x7f,0x04,0x74,0x7d
+
+# GFX12: v_cmpx_eq_u16_e32 null, v2              ; encoding: [0x7c,0x04,0x74,0x7d]
+0x7c,0x04,0x74,0x7d
+
+# GFX12: v_cmpx_eq_u16_e32 -1, v2                ; encoding: [0xc1,0x04,0x74,0x7d]
+0xc1,0x04,0x74,0x7d
+
+# GFX12: v_cmpx_eq_u16_e32 0x3800, v2
+0xf0,0x04,0x74,0x7d
+
+# GFX12: v_cmpx_eq_u16_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x74,0x7d]
+0xfd,0x04,0x74,0x7d
+
+# GFX12: v_cmpx_eq_u16_e32 0xfe0b, v127          ; encoding: [0xff,0xfe,0x74,0x7d,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x74,0x7d,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_eq_u32_e32 v1, v2                ; encoding: [0x01,0x05,0x94,0x7d]
+0x01,0x05,0x94,0x7d
+
+# GFX12: v_cmpx_eq_u32_e32 v255, v2              ; encoding: [0xff,0x05,0x94,0x7d]
+0xff,0x05,0x94,0x7d
+
+# GFX12: v_cmpx_eq_u32_e32 s1, v2                ; encoding: [0x01,0x04,0x94,0x7d]
+0x01,0x04,0x94,0x7d
+
+# GFX12: v_cmpx_eq_u32_e32 s105, v2              ; encoding: [0x69,0x04,0x94,0x7d]
+0x69,0x04,0x94,0x7d
+
+# GFX12: v_cmpx_eq_u32_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x94,0x7d]
+0x6a,0x04,0x94,0x7d
+
+# GFX12: v_cmpx_eq_u32_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x94,0x7d]
+0x6b,0x04,0x94,0x7d
+
+# GFX12: v_cmpx_eq_u32_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x94,0x7d]
+0x7b,0x04,0x94,0x7d
+
+# GFX12: v_cmpx_eq_u32_e32 m0, v2                ; encoding: [0x7d,0x04,0x94,0x7d]
+0x7d,0x04,0x94,0x7d
+
+# GFX12: v_cmpx_eq_u32_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x94,0x7d]
+0x7e,0x04,0x94,0x7d
+
+# GFX12: v_cmpx_eq_u32_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x94,0x7d]
+0x7f,0x04,0x94,0x7d
+
+# GFX12: v_cmpx_eq_u32_e32 null, v2              ; encoding: [0x7c,0x04,0x94,0x7d]
+0x7c,0x04,0x94,0x7d
+
+# GFX12: v_cmpx_eq_u32_e32 -1, v2                ; encoding: [0xc1,0x04,0x94,0x7d]
+0xc1,0x04,0x94,0x7d
+
+# GFX12: v_cmpx_eq_u32_e32 0.5, v2               ; encoding: [0xf0,0x04,0x94,0x7d]
+0xf0,0x04,0x94,0x7d
+
+# GFX12: v_cmpx_eq_u32_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x94,0x7d]
+0xfd,0x04,0x94,0x7d
+
+# GFX12: v_cmpx_eq_u32_e32 0xaf123456, v255      ; encoding: [0xff,0xfe,0x95,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x95,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_eq_u64_e32 v[1:2], v[2:3]        ; encoding: [0x01,0x05,0xb4,0x7d]
+0x01,0x05,0xb4,0x7d
+
+# GFX12: v_cmpx_eq_u64_e32 v[254:255], v[2:3]    ; encoding: [0xfe,0x05,0xb4,0x7d]
+0xfe,0x05,0xb4,0x7d
+
+# GFX12: v_cmpx_eq_u64_e32 s[2:3], v[2:3]        ; encoding: [0x02,0x04,0xb4,0x7d]
+0x02,0x04,0xb4,0x7d
+
+# GFX12: v_cmpx_eq_u64_e32 s[104:105], v[2:3]    ; encoding: [0x68,0x04,0xb4,0x7d]
+0x68,0x04,0xb4,0x7d
+
+# GFX12: v_cmpx_eq_u64_e32 vcc, v[2:3]           ; encoding: [0x6a,0x04,0xb4,0x7d]
+0x6a,0x04,0xb4,0x7d
+
+# GFX12: v_cmpx_eq_u64_e32 ttmp[14:15], v[2:3]   ; encoding: [0x7a,0x04,0xb4,0x7d]
+0x7a,0x04,0xb4,0x7d
+
+# GFX12: v_cmpx_eq_u64_e32 exec, v[2:3]          ; encoding: [0x7e,0x04,0xb4,0x7d]
+0x7e,0x04,0xb4,0x7d
+
+# GFX12: v_cmpx_eq_u64_e32 null, v[2:3]          ; encoding: [0x7c,0x04,0xb4,0x7d]
+0x7c,0x04,0xb4,0x7d
+
+# GFX12: v_cmpx_eq_u64_e32 -1, v[2:3]            ; encoding: [0xc1,0x04,0xb4,0x7d]
+0xc1,0x04,0xb4,0x7d
+
+# GFX12: v_cmpx_eq_u64_e32 0.5, v[2:3]           ; encoding: [0xf0,0x04,0xb4,0x7d]
+0xf0,0x04,0xb4,0x7d
+
+# GFX12: v_cmpx_eq_u64_e32 src_scc, v[2:3]       ; encoding: [0xfd,0x04,0xb4,0x7d]
+0xfd,0x04,0xb4,0x7d
+
+# GFX12: v_cmpx_eq_u64_e32 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xb5,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xb5,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ge_f16_e32 v1, v2                ; encoding: [0x01,0x05,0x0c,0x7d]
+0x01,0x05,0x0c,0x7d
+
+# GFX12: v_cmpx_ge_f16_e32 v127, v2              ; encoding: [0x7f,0x05,0x0c,0x7d]
+0x7f,0x05,0x0c,0x7d
+
+# GFX12: v_cmpx_ge_f16_e32 s1, v2                ; encoding: [0x01,0x04,0x0c,0x7d]
+0x01,0x04,0x0c,0x7d
+
+# GFX12: v_cmpx_ge_f16_e32 s105, v2              ; encoding: [0x69,0x04,0x0c,0x7d]
+0x69,0x04,0x0c,0x7d
+
+# GFX12: v_cmpx_ge_f16_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x0c,0x7d]
+0x6a,0x04,0x0c,0x7d
+
+# GFX12: v_cmpx_ge_f16_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x0c,0x7d]
+0x6b,0x04,0x0c,0x7d
+
+# GFX12: v_cmpx_ge_f16_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x0c,0x7d]
+0x7b,0x04,0x0c,0x7d
+
+# GFX12: v_cmpx_ge_f16_e32 m0, v2                ; encoding: [0x7d,0x04,0x0c,0x7d]
+0x7d,0x04,0x0c,0x7d
+
+# GFX12: v_cmpx_ge_f16_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x0c,0x7d]
+0x7e,0x04,0x0c,0x7d
+
+# GFX12: v_cmpx_ge_f16_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x0c,0x7d]
+0x7f,0x04,0x0c,0x7d
+
+# GFX12: v_cmpx_ge_f16_e32 null, v2              ; encoding: [0x7c,0x04,0x0c,0x7d]
+0x7c,0x04,0x0c,0x7d
+
+# GFX12: v_cmpx_ge_f16_e32 -1, v2                ; encoding: [0xc1,0x04,0x0c,0x7d]
+0xc1,0x04,0x0c,0x7d
+
+# GFX12: v_cmpx_ge_f16_e32 0.5, v2               ; encoding: [0xf0,0x04,0x0c,0x7d]
+0xf0,0x04,0x0c,0x7d
+
+# GFX12: v_cmpx_ge_f16_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x0c,0x7d]
+0xfd,0x04,0x0c,0x7d
+
+# GFX12: v_cmpx_ge_f16_e32 0xfe0b, v127          ; encoding: [0xff,0xfe,0x0c,0x7d,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x0c,0x7d,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ge_f32_e32 v1, v2                ; encoding: [0x01,0x05,0x2c,0x7d]
+0x01,0x05,0x2c,0x7d
+
+# GFX12: v_cmpx_ge_f32_e32 v255, v2              ; encoding: [0xff,0x05,0x2c,0x7d]
+0xff,0x05,0x2c,0x7d
+
+# GFX12: v_cmpx_ge_f32_e32 s1, v2                ; encoding: [0x01,0x04,0x2c,0x7d]
+0x01,0x04,0x2c,0x7d
+
+# GFX12: v_cmpx_ge_f32_e32 s105, v2              ; encoding: [0x69,0x04,0x2c,0x7d]
+0x69,0x04,0x2c,0x7d
+
+# GFX12: v_cmpx_ge_f32_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x2c,0x7d]
+0x6a,0x04,0x2c,0x7d
+
+# GFX12: v_cmpx_ge_f32_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x2c,0x7d]
+0x6b,0x04,0x2c,0x7d
+
+# GFX12: v_cmpx_ge_f32_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x2c,0x7d]
+0x7b,0x04,0x2c,0x7d
+
+# GFX12: v_cmpx_ge_f32_e32 m0, v2                ; encoding: [0x7d,0x04,0x2c,0x7d]
+0x7d,0x04,0x2c,0x7d
+
+# GFX12: v_cmpx_ge_f32_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x2c,0x7d]
+0x7e,0x04,0x2c,0x7d
+
+# GFX12: v_cmpx_ge_f32_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x2c,0x7d]
+0x7f,0x04,0x2c,0x7d
+
+# GFX12: v_cmpx_ge_f32_e32 null, v2              ; encoding: [0x7c,0x04,0x2c,0x7d]
+0x7c,0x04,0x2c,0x7d
+
+# GFX12: v_cmpx_ge_f32_e32 -1, v2                ; encoding: [0xc1,0x04,0x2c,0x7d]
+0xc1,0x04,0x2c,0x7d
+
+# GFX12: v_cmpx_ge_f32_e32 0.5, v2               ; encoding: [0xf0,0x04,0x2c,0x7d]
+0xf0,0x04,0x2c,0x7d
+
+# GFX12: v_cmpx_ge_f32_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x2c,0x7d]
+0xfd,0x04,0x2c,0x7d
+
+# GFX12: v_cmpx_ge_f32_e32 0xaf123456, v255      ; encoding: [0xff,0xfe,0x2d,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x2d,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ge_f64_e32 v[1:2], v[2:3]        ; encoding: [0x01,0x05,0x4c,0x7d]
+0x01,0x05,0x4c,0x7d
+
+# GFX12: v_cmpx_ge_f64_e32 v[254:255], v[2:3]    ; encoding: [0xfe,0x05,0x4c,0x7d]
+0xfe,0x05,0x4c,0x7d
+
+# GFX12: v_cmpx_ge_f64_e32 s[2:3], v[2:3]        ; encoding: [0x02,0x04,0x4c,0x7d]
+0x02,0x04,0x4c,0x7d
+
+# GFX12: v_cmpx_ge_f64_e32 s[104:105], v[2:3]    ; encoding: [0x68,0x04,0x4c,0x7d]
+0x68,0x04,0x4c,0x7d
+
+# GFX12: v_cmpx_ge_f64_e32 vcc, v[2:3]           ; encoding: [0x6a,0x04,0x4c,0x7d]
+0x6a,0x04,0x4c,0x7d
+
+# GFX12: v_cmpx_ge_f64_e32 ttmp[14:15], v[2:3]   ; encoding: [0x7a,0x04,0x4c,0x7d]
+0x7a,0x04,0x4c,0x7d
+
+# GFX12: v_cmpx_ge_f64_e32 exec, v[2:3]          ; encoding: [0x7e,0x04,0x4c,0x7d]
+0x7e,0x04,0x4c,0x7d
+
+# GFX12: v_cmpx_ge_f64_e32 null, v[2:3]          ; encoding: [0x7c,0x04,0x4c,0x7d]
+0x7c,0x04,0x4c,0x7d
+
+# GFX12: v_cmpx_ge_f64_e32 -1, v[2:3]            ; encoding: [0xc1,0x04,0x4c,0x7d]
+0xc1,0x04,0x4c,0x7d
+
+# GFX12: v_cmpx_ge_f64_e32 0.5, v[2:3]           ; encoding: [0xf0,0x04,0x4c,0x7d]
+0xf0,0x04,0x4c,0x7d
+
+# GFX12: v_cmpx_ge_f64_e32 src_scc, v[2:3]       ; encoding: [0xfd,0x04,0x4c,0x7d]
+0xfd,0x04,0x4c,0x7d
+
+# GFX12: v_cmpx_ge_f64_e32 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x4d,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x4d,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ge_i16_e32 v1, v2                ; encoding: [0x01,0x05,0x6c,0x7d]
+0x01,0x05,0x6c,0x7d
+
+# GFX12: v_cmpx_ge_i16_e32 v127, v2              ; encoding: [0x7f,0x05,0x6c,0x7d]
+0x7f,0x05,0x6c,0x7d
+
+# GFX12: v_cmpx_ge_i16_e32 s1, v2                ; encoding: [0x01,0x04,0x6c,0x7d]
+0x01,0x04,0x6c,0x7d
+
+# GFX12: v_cmpx_ge_i16_e32 s105, v2              ; encoding: [0x69,0x04,0x6c,0x7d]
+0x69,0x04,0x6c,0x7d
+
+# GFX12: v_cmpx_ge_i16_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x6c,0x7d]
+0x6a,0x04,0x6c,0x7d
+
+# GFX12: v_cmpx_ge_i16_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x6c,0x7d]
+0x6b,0x04,0x6c,0x7d
+
+# GFX12: v_cmpx_ge_i16_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x6c,0x7d]
+0x7b,0x04,0x6c,0x7d
+
+# GFX12: v_cmpx_ge_i16_e32 m0, v2                ; encoding: [0x7d,0x04,0x6c,0x7d]
+0x7d,0x04,0x6c,0x7d
+
+# GFX12: v_cmpx_ge_i16_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x6c,0x7d]
+0x7e,0x04,0x6c,0x7d
+
+# GFX12: v_cmpx_ge_i16_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x6c,0x7d]
+0x7f,0x04,0x6c,0x7d
+
+# GFX12: v_cmpx_ge_i16_e32 null, v2              ; encoding: [0x7c,0x04,0x6c,0x7d]
+0x7c,0x04,0x6c,0x7d
+
+# GFX12: v_cmpx_ge_i16_e32 -1, v2                ; encoding: [0xc1,0x04,0x6c,0x7d]
+0xc1,0x04,0x6c,0x7d
+
+# GFX12: v_cmpx_ge_i16_e32 0x3800, v2
+0xf0,0x04,0x6c,0x7d
+
+# GFX12: v_cmpx_ge_i16_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x6c,0x7d]
+0xfd,0x04,0x6c,0x7d
+
+# GFX12: v_cmpx_ge_i16_e32 0xfe0b, v127          ; encoding: [0xff,0xfe,0x6c,0x7d,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x6c,0x7d,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ge_i32_e32 v1, v2                ; encoding: [0x01,0x05,0x8c,0x7d]
+0x01,0x05,0x8c,0x7d
+
+# GFX12: v_cmpx_ge_i32_e32 v255, v2              ; encoding: [0xff,0x05,0x8c,0x7d]
+0xff,0x05,0x8c,0x7d
+
+# GFX12: v_cmpx_ge_i32_e32 s1, v2                ; encoding: [0x01,0x04,0x8c,0x7d]
+0x01,0x04,0x8c,0x7d
+
+# GFX12: v_cmpx_ge_i32_e32 s105, v2              ; encoding: [0x69,0x04,0x8c,0x7d]
+0x69,0x04,0x8c,0x7d
+
+# GFX12: v_cmpx_ge_i32_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x8c,0x7d]
+0x6a,0x04,0x8c,0x7d
+
+# GFX12: v_cmpx_ge_i32_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x8c,0x7d]
+0x6b,0x04,0x8c,0x7d
+
+# GFX12: v_cmpx_ge_i32_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x8c,0x7d]
+0x7b,0x04,0x8c,0x7d
+
+# GFX12: v_cmpx_ge_i32_e32 m0, v2                ; encoding: [0x7d,0x04,0x8c,0x7d]
+0x7d,0x04,0x8c,0x7d
+
+# GFX12: v_cmpx_ge_i32_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x8c,0x7d]
+0x7e,0x04,0x8c,0x7d
+
+# GFX12: v_cmpx_ge_i32_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x8c,0x7d]
+0x7f,0x04,0x8c,0x7d
+
+# GFX12: v_cmpx_ge_i32_e32 null, v2              ; encoding: [0x7c,0x04,0x8c,0x7d]
+0x7c,0x04,0x8c,0x7d
+
+# GFX12: v_cmpx_ge_i32_e32 -1, v2                ; encoding: [0xc1,0x04,0x8c,0x7d]
+0xc1,0x04,0x8c,0x7d
+
+# GFX12: v_cmpx_ge_i32_e32 0.5, v2               ; encoding: [0xf0,0x04,0x8c,0x7d]
+0xf0,0x04,0x8c,0x7d
+
+# GFX12: v_cmpx_ge_i32_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x8c,0x7d]
+0xfd,0x04,0x8c,0x7d
+
+# GFX12: v_cmpx_ge_i32_e32 0xaf123456, v255      ; encoding: [0xff,0xfe,0x8d,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x8d,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ge_i64_e32 v[1:2], v[2:3]        ; encoding: [0x01,0x05,0xac,0x7d]
+0x01,0x05,0xac,0x7d
+
+# GFX12: v_cmpx_ge_i64_e32 v[254:255], v[2:3]    ; encoding: [0xfe,0x05,0xac,0x7d]
+0xfe,0x05,0xac,0x7d
+
+# GFX12: v_cmpx_ge_i64_e32 s[2:3], v[2:3]        ; encoding: [0x02,0x04,0xac,0x7d]
+0x02,0x04,0xac,0x7d
+
+# GFX12: v_cmpx_ge_i64_e32 s[104:105], v[2:3]    ; encoding: [0x68,0x04,0xac,0x7d]
+0x68,0x04,0xac,0x7d
+
+# GFX12: v_cmpx_ge_i64_e32 vcc, v[2:3]           ; encoding: [0x6a,0x04,0xac,0x7d]
+0x6a,0x04,0xac,0x7d
+
+# GFX12: v_cmpx_ge_i64_e32 ttmp[14:15], v[2:3]   ; encoding: [0x7a,0x04,0xac,0x7d]
+0x7a,0x04,0xac,0x7d
+
+# GFX12: v_cmpx_ge_i64_e32 exec, v[2:3]          ; encoding: [0x7e,0x04,0xac,0x7d]
+0x7e,0x04,0xac,0x7d
+
+# GFX12: v_cmpx_ge_i64_e32 null, v[2:3]          ; encoding: [0x7c,0x04,0xac,0x7d]
+0x7c,0x04,0xac,0x7d
+
+# GFX12: v_cmpx_ge_i64_e32 -1, v[2:3]            ; encoding: [0xc1,0x04,0xac,0x7d]
+0xc1,0x04,0xac,0x7d
+
+# GFX12: v_cmpx_ge_i64_e32 0.5, v[2:3]           ; encoding: [0xf0,0x04,0xac,0x7d]
+0xf0,0x04,0xac,0x7d
+
+# GFX12: v_cmpx_ge_i64_e32 src_scc, v[2:3]       ; encoding: [0xfd,0x04,0xac,0x7d]
+0xfd,0x04,0xac,0x7d
+
+# GFX12: v_cmpx_ge_i64_e32 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xad,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xad,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ge_u16_e32 v1, v2                ; encoding: [0x01,0x05,0x7c,0x7d]
+0x01,0x05,0x7c,0x7d
+
+# GFX12: v_cmpx_ge_u16_e32 v127, v2              ; encoding: [0x7f,0x05,0x7c,0x7d]
+0x7f,0x05,0x7c,0x7d
+
+# GFX12: v_cmpx_ge_u16_e32 s1, v2                ; encoding: [0x01,0x04,0x7c,0x7d]
+0x01,0x04,0x7c,0x7d
+
+# GFX12: v_cmpx_ge_u16_e32 s105, v2              ; encoding: [0x69,0x04,0x7c,0x7d]
+0x69,0x04,0x7c,0x7d
+
+# GFX12: v_cmpx_ge_u16_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x7c,0x7d]
+0x6a,0x04,0x7c,0x7d
+
+# GFX12: v_cmpx_ge_u16_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x7c,0x7d]
+0x6b,0x04,0x7c,0x7d
+
+# GFX12: v_cmpx_ge_u16_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x7c,0x7d]
+0x7b,0x04,0x7c,0x7d
+
+# GFX12: v_cmpx_ge_u16_e32 m0, v2                ; encoding: [0x7d,0x04,0x7c,0x7d]
+0x7d,0x04,0x7c,0x7d
+
+# GFX12: v_cmpx_ge_u16_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x7c,0x7d]
+0x7e,0x04,0x7c,0x7d
+
+# GFX12: v_cmpx_ge_u16_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x7c,0x7d]
+0x7f,0x04,0x7c,0x7d
+
+# GFX12: v_cmpx_ge_u16_e32 null, v2              ; encoding: [0x7c,0x04,0x7c,0x7d]
+0x7c,0x04,0x7c,0x7d
+
+# GFX12: v_cmpx_ge_u16_e32 -1, v2                ; encoding: [0xc1,0x04,0x7c,0x7d]
+0xc1,0x04,0x7c,0x7d
+
+# GFX12: v_cmpx_ge_u16_e32 0x3800, v2
+0xf0,0x04,0x7c,0x7d
+
+# GFX12: v_cmpx_ge_u16_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x7c,0x7d]
+0xfd,0x04,0x7c,0x7d
+
+# GFX12: v_cmpx_ge_u16_e32 0xfe0b, v127          ; encoding: [0xff,0xfe,0x7c,0x7d,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x7c,0x7d,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ge_u32_e32 v1, v2                ; encoding: [0x01,0x05,0x9c,0x7d]
+0x01,0x05,0x9c,0x7d
+
+# GFX12: v_cmpx_ge_u32_e32 v255, v2              ; encoding: [0xff,0x05,0x9c,0x7d]
+0xff,0x05,0x9c,0x7d
+
+# GFX12: v_cmpx_ge_u32_e32 s1, v2                ; encoding: [0x01,0x04,0x9c,0x7d]
+0x01,0x04,0x9c,0x7d
+
+# GFX12: v_cmpx_ge_u32_e32 s105, v2              ; encoding: [0x69,0x04,0x9c,0x7d]
+0x69,0x04,0x9c,0x7d
+
+# GFX12: v_cmpx_ge_u32_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x9c,0x7d]
+0x6a,0x04,0x9c,0x7d
+
+# GFX12: v_cmpx_ge_u32_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x9c,0x7d]
+0x6b,0x04,0x9c,0x7d
+
+# GFX12: v_cmpx_ge_u32_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x9c,0x7d]
+0x7b,0x04,0x9c,0x7d
+
+# GFX12: v_cmpx_ge_u32_e32 m0, v2                ; encoding: [0x7d,0x04,0x9c,0x7d]
+0x7d,0x04,0x9c,0x7d
+
+# GFX12: v_cmpx_ge_u32_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x9c,0x7d]
+0x7e,0x04,0x9c,0x7d
+
+# GFX12: v_cmpx_ge_u32_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x9c,0x7d]
+0x7f,0x04,0x9c,0x7d
+
+# GFX12: v_cmpx_ge_u32_e32 null, v2              ; encoding: [0x7c,0x04,0x9c,0x7d]
+0x7c,0x04,0x9c,0x7d
+
+# GFX12: v_cmpx_ge_u32_e32 -1, v2                ; encoding: [0xc1,0x04,0x9c,0x7d]
+0xc1,0x04,0x9c,0x7d
+
+# GFX12: v_cmpx_ge_u32_e32 0.5, v2               ; encoding: [0xf0,0x04,0x9c,0x7d]
+0xf0,0x04,0x9c,0x7d
+
+# GFX12: v_cmpx_ge_u32_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x9c,0x7d]
+0xfd,0x04,0x9c,0x7d
+
+# GFX12: v_cmpx_ge_u32_e32 0xaf123456, v255      ; encoding: [0xff,0xfe,0x9d,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x9d,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ge_u64_e32 v[1:2], v[2:3]        ; encoding: [0x01,0x05,0xbc,0x7d]
+0x01,0x05,0xbc,0x7d
+
+# GFX12: v_cmpx_ge_u64_e32 v[254:255], v[2:3]    ; encoding: [0xfe,0x05,0xbc,0x7d]
+0xfe,0x05,0xbc,0x7d
+
+# GFX12: v_cmpx_ge_u64_e32 s[2:3], v[2:3]        ; encoding: [0x02,0x04,0xbc,0x7d]
+0x02,0x04,0xbc,0x7d
+
+# GFX12: v_cmpx_ge_u64_e32 s[104:105], v[2:3]    ; encoding: [0x68,0x04,0xbc,0x7d]
+0x68,0x04,0xbc,0x7d
+
+# GFX12: v_cmpx_ge_u64_e32 vcc, v[2:3]           ; encoding: [0x6a,0x04,0xbc,0x7d]
+0x6a,0x04,0xbc,0x7d
+
+# GFX12: v_cmpx_ge_u64_e32 ttmp[14:15], v[2:3]   ; encoding: [0x7a,0x04,0xbc,0x7d]
+0x7a,0x04,0xbc,0x7d
+
+# GFX12: v_cmpx_ge_u64_e32 exec, v[2:3]          ; encoding: [0x7e,0x04,0xbc,0x7d]
+0x7e,0x04,0xbc,0x7d
+
+# GFX12: v_cmpx_ge_u64_e32 null, v[2:3]          ; encoding: [0x7c,0x04,0xbc,0x7d]
+0x7c,0x04,0xbc,0x7d
+
+# GFX12: v_cmpx_ge_u64_e32 -1, v[2:3]            ; encoding: [0xc1,0x04,0xbc,0x7d]
+0xc1,0x04,0xbc,0x7d
+
+# GFX12: v_cmpx_ge_u64_e32 0.5, v[2:3]           ; encoding: [0xf0,0x04,0xbc,0x7d]
+0xf0,0x04,0xbc,0x7d
+
+# GFX12: v_cmpx_ge_u64_e32 src_scc, v[2:3]       ; encoding: [0xfd,0x04,0xbc,0x7d]
+0xfd,0x04,0xbc,0x7d
+
+# GFX12: v_cmpx_ge_u64_e32 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xbd,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xbd,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_gt_f16_e32 v1, v2                ; encoding: [0x01,0x05,0x08,0x7d]
+0x01,0x05,0x08,0x7d
+
+# GFX12: v_cmpx_gt_f16_e32 v127, v2              ; encoding: [0x7f,0x05,0x08,0x7d]
+0x7f,0x05,0x08,0x7d
+
+# GFX12: v_cmpx_gt_f16_e32 s1, v2                ; encoding: [0x01,0x04,0x08,0x7d]
+0x01,0x04,0x08,0x7d
+
+# GFX12: v_cmpx_gt_f16_e32 s105, v2              ; encoding: [0x69,0x04,0x08,0x7d]
+0x69,0x04,0x08,0x7d
+
+# GFX12: v_cmpx_gt_f16_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x08,0x7d]
+0x6a,0x04,0x08,0x7d
+
+# GFX12: v_cmpx_gt_f16_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x08,0x7d]
+0x6b,0x04,0x08,0x7d
+
+# GFX12: v_cmpx_gt_f16_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x08,0x7d]
+0x7b,0x04,0x08,0x7d
+
+# GFX12: v_cmpx_gt_f16_e32 m0, v2                ; encoding: [0x7d,0x04,0x08,0x7d]
+0x7d,0x04,0x08,0x7d
+
+# GFX12: v_cmpx_gt_f16_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x08,0x7d]
+0x7e,0x04,0x08,0x7d
+
+# GFX12: v_cmpx_gt_f16_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x08,0x7d]
+0x7f,0x04,0x08,0x7d
+
+# GFX12: v_cmpx_gt_f16_e32 null, v2              ; encoding: [0x7c,0x04,0x08,0x7d]
+0x7c,0x04,0x08,0x7d
+
+# GFX12: v_cmpx_gt_f16_e32 -1, v2                ; encoding: [0xc1,0x04,0x08,0x7d]
+0xc1,0x04,0x08,0x7d
+
+# GFX12: v_cmpx_gt_f16_e32 0.5, v2               ; encoding: [0xf0,0x04,0x08,0x7d]
+0xf0,0x04,0x08,0x7d
+
+# GFX12: v_cmpx_gt_f16_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x08,0x7d]
+0xfd,0x04,0x08,0x7d
+
+# GFX12: v_cmpx_gt_f16_e32 0xfe0b, v127          ; encoding: [0xff,0xfe,0x08,0x7d,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x08,0x7d,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_gt_f32_e32 v1, v2                ; encoding: [0x01,0x05,0x28,0x7d]
+0x01,0x05,0x28,0x7d
+
+# GFX12: v_cmpx_gt_f32_e32 v255, v2              ; encoding: [0xff,0x05,0x28,0x7d]
+0xff,0x05,0x28,0x7d
+
+# GFX12: v_cmpx_gt_f32_e32 s1, v2                ; encoding: [0x01,0x04,0x28,0x7d]
+0x01,0x04,0x28,0x7d
+
+# GFX12: v_cmpx_gt_f32_e32 s105, v2              ; encoding: [0x69,0x04,0x28,0x7d]
+0x69,0x04,0x28,0x7d
+
+# GFX12: v_cmpx_gt_f32_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x28,0x7d]
+0x6a,0x04,0x28,0x7d
+
+# GFX12: v_cmpx_gt_f32_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x28,0x7d]
+0x6b,0x04,0x28,0x7d
+
+# GFX12: v_cmpx_gt_f32_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x28,0x7d]
+0x7b,0x04,0x28,0x7d
+
+# GFX12: v_cmpx_gt_f32_e32 m0, v2                ; encoding: [0x7d,0x04,0x28,0x7d]
+0x7d,0x04,0x28,0x7d
+
+# GFX12: v_cmpx_gt_f32_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x28,0x7d]
+0x7e,0x04,0x28,0x7d
+
+# GFX12: v_cmpx_gt_f32_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x28,0x7d]
+0x7f,0x04,0x28,0x7d
+
+# GFX12: v_cmpx_gt_f32_e32 null, v2              ; encoding: [0x7c,0x04,0x28,0x7d]
+0x7c,0x04,0x28,0x7d
+
+# GFX12: v_cmpx_gt_f32_e32 -1, v2                ; encoding: [0xc1,0x04,0x28,0x7d]
+0xc1,0x04,0x28,0x7d
+
+# GFX12: v_cmpx_gt_f32_e32 0.5, v2               ; encoding: [0xf0,0x04,0x28,0x7d]
+0xf0,0x04,0x28,0x7d
+
+# GFX12: v_cmpx_gt_f32_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x28,0x7d]
+0xfd,0x04,0x28,0x7d
+
+# GFX12: v_cmpx_gt_f32_e32 0xaf123456, v255      ; encoding: [0xff,0xfe,0x29,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x29,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_gt_f64_e32 v[1:2], v[2:3]        ; encoding: [0x01,0x05,0x48,0x7d]
+0x01,0x05,0x48,0x7d
+
+# GFX12: v_cmpx_gt_f64_e32 v[254:255], v[2:3]    ; encoding: [0xfe,0x05,0x48,0x7d]
+0xfe,0x05,0x48,0x7d
+
+# GFX12: v_cmpx_gt_f64_e32 s[2:3], v[2:3]        ; encoding: [0x02,0x04,0x48,0x7d]
+0x02,0x04,0x48,0x7d
+
+# GFX12: v_cmpx_gt_f64_e32 s[104:105], v[2:3]    ; encoding: [0x68,0x04,0x48,0x7d]
+0x68,0x04,0x48,0x7d
+
+# GFX12: v_cmpx_gt_f64_e32 vcc, v[2:3]           ; encoding: [0x6a,0x04,0x48,0x7d]
+0x6a,0x04,0x48,0x7d
+
+# GFX12: v_cmpx_gt_f64_e32 ttmp[14:15], v[2:3]   ; encoding: [0x7a,0x04,0x48,0x7d]
+0x7a,0x04,0x48,0x7d
+
+# GFX12: v_cmpx_gt_f64_e32 exec, v[2:3]          ; encoding: [0x7e,0x04,0x48,0x7d]
+0x7e,0x04,0x48,0x7d
+
+# GFX12: v_cmpx_gt_f64_e32 null, v[2:3]          ; encoding: [0x7c,0x04,0x48,0x7d]
+0x7c,0x04,0x48,0x7d
+
+# GFX12: v_cmpx_gt_f64_e32 -1, v[2:3]            ; encoding: [0xc1,0x04,0x48,0x7d]
+0xc1,0x04,0x48,0x7d
+
+# GFX12: v_cmpx_gt_f64_e32 0.5, v[2:3]           ; encoding: [0xf0,0x04,0x48,0x7d]
+0xf0,0x04,0x48,0x7d
+
+# GFX12: v_cmpx_gt_f64_e32 src_scc, v[2:3]       ; encoding: [0xfd,0x04,0x48,0x7d]
+0xfd,0x04,0x48,0x7d
+
+# GFX12: v_cmpx_gt_f64_e32 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x49,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x49,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_gt_i16_e32 v1, v2                ; encoding: [0x01,0x05,0x68,0x7d]
+0x01,0x05,0x68,0x7d
+
+# GFX12: v_cmpx_gt_i16_e32 v127, v2              ; encoding: [0x7f,0x05,0x68,0x7d]
+0x7f,0x05,0x68,0x7d
+
+# GFX12: v_cmpx_gt_i16_e32 s1, v2                ; encoding: [0x01,0x04,0x68,0x7d]
+0x01,0x04,0x68,0x7d
+
+# GFX12: v_cmpx_gt_i16_e32 s105, v2              ; encoding: [0x69,0x04,0x68,0x7d]
+0x69,0x04,0x68,0x7d
+
+# GFX12: v_cmpx_gt_i16_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x68,0x7d]
+0x6a,0x04,0x68,0x7d
+
+# GFX12: v_cmpx_gt_i16_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x68,0x7d]
+0x6b,0x04,0x68,0x7d
+
+# GFX12: v_cmpx_gt_i16_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x68,0x7d]
+0x7b,0x04,0x68,0x7d
+
+# GFX12: v_cmpx_gt_i16_e32 m0, v2                ; encoding: [0x7d,0x04,0x68,0x7d]
+0x7d,0x04,0x68,0x7d
+
+# GFX12: v_cmpx_gt_i16_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x68,0x7d]
+0x7e,0x04,0x68,0x7d
+
+# GFX12: v_cmpx_gt_i16_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x68,0x7d]
+0x7f,0x04,0x68,0x7d
+
+# GFX12: v_cmpx_gt_i16_e32 null, v2              ; encoding: [0x7c,0x04,0x68,0x7d]
+0x7c,0x04,0x68,0x7d
+
+# GFX12: v_cmpx_gt_i16_e32 -1, v2                ; encoding: [0xc1,0x04,0x68,0x7d]
+0xc1,0x04,0x68,0x7d
+
+# GFX12: v_cmpx_gt_i16_e32 0x3800, v2
+0xf0,0x04,0x68,0x7d
+
+# GFX12: v_cmpx_gt_i16_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x68,0x7d]
+0xfd,0x04,0x68,0x7d
+
+# GFX12: v_cmpx_gt_i16_e32 0xfe0b, v127          ; encoding: [0xff,0xfe,0x68,0x7d,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x68,0x7d,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_gt_i32_e32 v1, v2                ; encoding: [0x01,0x05,0x88,0x7d]
+0x01,0x05,0x88,0x7d
+
+# GFX12: v_cmpx_gt_i32_e32 v255, v2              ; encoding: [0xff,0x05,0x88,0x7d]
+0xff,0x05,0x88,0x7d
+
+# GFX12: v_cmpx_gt_i32_e32 s1, v2                ; encoding: [0x01,0x04,0x88,0x7d]
+0x01,0x04,0x88,0x7d
+
+# GFX12: v_cmpx_gt_i32_e32 s105, v2              ; encoding: [0x69,0x04,0x88,0x7d]
+0x69,0x04,0x88,0x7d
+
+# GFX12: v_cmpx_gt_i32_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x88,0x7d]
+0x6a,0x04,0x88,0x7d
+
+# GFX12: v_cmpx_gt_i32_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x88,0x7d]
+0x6b,0x04,0x88,0x7d
+
+# GFX12: v_cmpx_gt_i32_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x88,0x7d]
+0x7b,0x04,0x88,0x7d
+
+# GFX12: v_cmpx_gt_i32_e32 m0, v2                ; encoding: [0x7d,0x04,0x88,0x7d]
+0x7d,0x04,0x88,0x7d
+
+# GFX12: v_cmpx_gt_i32_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x88,0x7d]
+0x7e,0x04,0x88,0x7d
+
+# GFX12: v_cmpx_gt_i32_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x88,0x7d]
+0x7f,0x04,0x88,0x7d
+
+# GFX12: v_cmpx_gt_i32_e32 null, v2              ; encoding: [0x7c,0x04,0x88,0x7d]
+0x7c,0x04,0x88,0x7d
+
+# GFX12: v_cmpx_gt_i32_e32 -1, v2                ; encoding: [0xc1,0x04,0x88,0x7d]
+0xc1,0x04,0x88,0x7d
+
+# GFX12: v_cmpx_gt_i32_e32 0.5, v2               ; encoding: [0xf0,0x04,0x88,0x7d]
+0xf0,0x04,0x88,0x7d
+
+# GFX12: v_cmpx_gt_i32_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x88,0x7d]
+0xfd,0x04,0x88,0x7d
+
+# GFX12: v_cmpx_gt_i32_e32 0xaf123456, v255      ; encoding: [0xff,0xfe,0x89,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x89,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_gt_i64_e32 v[1:2], v[2:3]        ; encoding: [0x01,0x05,0xa8,0x7d]
+0x01,0x05,0xa8,0x7d
+
+# GFX12: v_cmpx_gt_i64_e32 v[254:255], v[2:3]    ; encoding: [0xfe,0x05,0xa8,0x7d]
+0xfe,0x05,0xa8,0x7d
+
+# GFX12: v_cmpx_gt_i64_e32 s[2:3], v[2:3]        ; encoding: [0x02,0x04,0xa8,0x7d]
+0x02,0x04,0xa8,0x7d
+
+# GFX12: v_cmpx_gt_i64_e32 s[104:105], v[2:3]    ; encoding: [0x68,0x04,0xa8,0x7d]
+0x68,0x04,0xa8,0x7d
+
+# GFX12: v_cmpx_gt_i64_e32 vcc, v[2:3]           ; encoding: [0x6a,0x04,0xa8,0x7d]
+0x6a,0x04,0xa8,0x7d
+
+# GFX12: v_cmpx_gt_i64_e32 ttmp[14:15], v[2:3]   ; encoding: [0x7a,0x04,0xa8,0x7d]
+0x7a,0x04,0xa8,0x7d
+
+# GFX12: v_cmpx_gt_i64_e32 exec, v[2:3]          ; encoding: [0x7e,0x04,0xa8,0x7d]
+0x7e,0x04,0xa8,0x7d
+
+# GFX12: v_cmpx_gt_i64_e32 null, v[2:3]          ; encoding: [0x7c,0x04,0xa8,0x7d]
+0x7c,0x04,0xa8,0x7d
+
+# GFX12: v_cmpx_gt_i64_e32 -1, v[2:3]            ; encoding: [0xc1,0x04,0xa8,0x7d]
+0xc1,0x04,0xa8,0x7d
+
+# GFX12: v_cmpx_gt_i64_e32 0.5, v[2:3]           ; encoding: [0xf0,0x04,0xa8,0x7d]
+0xf0,0x04,0xa8,0x7d
+
+# GFX12: v_cmpx_gt_i64_e32 src_scc, v[2:3]       ; encoding: [0xfd,0x04,0xa8,0x7d]
+0xfd,0x04,0xa8,0x7d
+
+# GFX12: v_cmpx_gt_i64_e32 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xa9,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xa9,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_gt_u16_e32 v1, v2                ; encoding: [0x01,0x05,0x78,0x7d]
+0x01,0x05,0x78,0x7d
+
+# GFX12: v_cmpx_gt_u16_e32 v127, v2              ; encoding: [0x7f,0x05,0x78,0x7d]
+0x7f,0x05,0x78,0x7d
+
+# GFX12: v_cmpx_gt_u16_e32 s1, v2                ; encoding: [0x01,0x04,0x78,0x7d]
+0x01,0x04,0x78,0x7d
+
+# GFX12: v_cmpx_gt_u16_e32 s105, v2              ; encoding: [0x69,0x04,0x78,0x7d]
+0x69,0x04,0x78,0x7d
+
+# GFX12: v_cmpx_gt_u16_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x78,0x7d]
+0x6a,0x04,0x78,0x7d
+
+# GFX12: v_cmpx_gt_u16_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x78,0x7d]
+0x6b,0x04,0x78,0x7d
+
+# GFX12: v_cmpx_gt_u16_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x78,0x7d]
+0x7b,0x04,0x78,0x7d
+
+# GFX12: v_cmpx_gt_u16_e32 m0, v2                ; encoding: [0x7d,0x04,0x78,0x7d]
+0x7d,0x04,0x78,0x7d
+
+# GFX12: v_cmpx_gt_u16_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x78,0x7d]
+0x7e,0x04,0x78,0x7d
+
+# GFX12: v_cmpx_gt_u16_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x78,0x7d]
+0x7f,0x04,0x78,0x7d
+
+# GFX12: v_cmpx_gt_u16_e32 null, v2              ; encoding: [0x7c,0x04,0x78,0x7d]
+0x7c,0x04,0x78,0x7d
+
+# GFX12: v_cmpx_gt_u16_e32 -1, v2                ; encoding: [0xc1,0x04,0x78,0x7d]
+0xc1,0x04,0x78,0x7d
+
+# GFX12: v_cmpx_gt_u16_e32 0x3800, v2
+0xf0,0x04,0x78,0x7d
+
+# GFX12: v_cmpx_gt_u16_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x78,0x7d]
+0xfd,0x04,0x78,0x7d
+
+# GFX12: v_cmpx_gt_u16_e32 0xfe0b, v127          ; encoding: [0xff,0xfe,0x78,0x7d,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x78,0x7d,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_gt_u32_e32 v1, v2                ; encoding: [0x01,0x05,0x98,0x7d]
+0x01,0x05,0x98,0x7d
+
+# GFX12: v_cmpx_gt_u32_e32 v255, v2              ; encoding: [0xff,0x05,0x98,0x7d]
+0xff,0x05,0x98,0x7d
+
+# GFX12: v_cmpx_gt_u32_e32 s1, v2                ; encoding: [0x01,0x04,0x98,0x7d]
+0x01,0x04,0x98,0x7d
+
+# GFX12: v_cmpx_gt_u32_e32 s105, v2              ; encoding: [0x69,0x04,0x98,0x7d]
+0x69,0x04,0x98,0x7d
+
+# GFX12: v_cmpx_gt_u32_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x98,0x7d]
+0x6a,0x04,0x98,0x7d
+
+# GFX12: v_cmpx_gt_u32_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x98,0x7d]
+0x6b,0x04,0x98,0x7d
+
+# GFX12: v_cmpx_gt_u32_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x98,0x7d]
+0x7b,0x04,0x98,0x7d
+
+# GFX12: v_cmpx_gt_u32_e32 m0, v2                ; encoding: [0x7d,0x04,0x98,0x7d]
+0x7d,0x04,0x98,0x7d
+
+# GFX12: v_cmpx_gt_u32_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x98,0x7d]
+0x7e,0x04,0x98,0x7d
+
+# GFX12: v_cmpx_gt_u32_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x98,0x7d]
+0x7f,0x04,0x98,0x7d
+
+# GFX12: v_cmpx_gt_u32_e32 null, v2              ; encoding: [0x7c,0x04,0x98,0x7d]
+0x7c,0x04,0x98,0x7d
+
+# GFX12: v_cmpx_gt_u32_e32 -1, v2                ; encoding: [0xc1,0x04,0x98,0x7d]
+0xc1,0x04,0x98,0x7d
+
+# GFX12: v_cmpx_gt_u32_e32 0.5, v2               ; encoding: [0xf0,0x04,0x98,0x7d]
+0xf0,0x04,0x98,0x7d
+
+# GFX12: v_cmpx_gt_u32_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x98,0x7d]
+0xfd,0x04,0x98,0x7d
+
+# GFX12: v_cmpx_gt_u32_e32 0xaf123456, v255      ; encoding: [0xff,0xfe,0x99,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x99,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_gt_u64_e32 v[1:2], v[2:3]        ; encoding: [0x01,0x05,0xb8,0x7d]
+0x01,0x05,0xb8,0x7d
+
+# GFX12: v_cmpx_gt_u64_e32 v[254:255], v[2:3]    ; encoding: [0xfe,0x05,0xb8,0x7d]
+0xfe,0x05,0xb8,0x7d
+
+# GFX12: v_cmpx_gt_u64_e32 s[2:3], v[2:3]        ; encoding: [0x02,0x04,0xb8,0x7d]
+0x02,0x04,0xb8,0x7d
+
+# GFX12: v_cmpx_gt_u64_e32 s[104:105], v[2:3]    ; encoding: [0x68,0x04,0xb8,0x7d]
+0x68,0x04,0xb8,0x7d
+
+# GFX12: v_cmpx_gt_u64_e32 vcc, v[2:3]           ; encoding: [0x6a,0x04,0xb8,0x7d]
+0x6a,0x04,0xb8,0x7d
+
+# GFX12: v_cmpx_gt_u64_e32 ttmp[14:15], v[2:3]   ; encoding: [0x7a,0x04,0xb8,0x7d]
+0x7a,0x04,0xb8,0x7d
+
+# GFX12: v_cmpx_gt_u64_e32 exec, v[2:3]          ; encoding: [0x7e,0x04,0xb8,0x7d]
+0x7e,0x04,0xb8,0x7d
+
+# GFX12: v_cmpx_gt_u64_e32 null, v[2:3]          ; encoding: [0x7c,0x04,0xb8,0x7d]
+0x7c,0x04,0xb8,0x7d
+
+# GFX12: v_cmpx_gt_u64_e32 -1, v[2:3]            ; encoding: [0xc1,0x04,0xb8,0x7d]
+0xc1,0x04,0xb8,0x7d
+
+# GFX12: v_cmpx_gt_u64_e32 0.5, v[2:3]           ; encoding: [0xf0,0x04,0xb8,0x7d]
+0xf0,0x04,0xb8,0x7d
+
+# GFX12: v_cmpx_gt_u64_e32 src_scc, v[2:3]       ; encoding: [0xfd,0x04,0xb8,0x7d]
+0xfd,0x04,0xb8,0x7d
+
+# GFX12: v_cmpx_gt_u64_e32 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xb9,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xb9,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_le_f16_e32 v1, v2                ; encoding: [0x01,0x05,0x06,0x7d]
+0x01,0x05,0x06,0x7d
+
+# GFX12: v_cmpx_le_f16_e32 v127, v2              ; encoding: [0x7f,0x05,0x06,0x7d]
+0x7f,0x05,0x06,0x7d
+
+# GFX12: v_cmpx_le_f16_e32 s1, v2                ; encoding: [0x01,0x04,0x06,0x7d]
+0x01,0x04,0x06,0x7d
+
+# GFX12: v_cmpx_le_f16_e32 s105, v2              ; encoding: [0x69,0x04,0x06,0x7d]
+0x69,0x04,0x06,0x7d
+
+# GFX12: v_cmpx_le_f16_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x06,0x7d]
+0x6a,0x04,0x06,0x7d
+
+# GFX12: v_cmpx_le_f16_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x06,0x7d]
+0x6b,0x04,0x06,0x7d
+
+# GFX12: v_cmpx_le_f16_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x06,0x7d]
+0x7b,0x04,0x06,0x7d
+
+# GFX12: v_cmpx_le_f16_e32 m0, v2                ; encoding: [0x7d,0x04,0x06,0x7d]
+0x7d,0x04,0x06,0x7d
+
+# GFX12: v_cmpx_le_f16_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x06,0x7d]
+0x7e,0x04,0x06,0x7d
+
+# GFX12: v_cmpx_le_f16_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x06,0x7d]
+0x7f,0x04,0x06,0x7d
+
+# GFX12: v_cmpx_le_f16_e32 null, v2              ; encoding: [0x7c,0x04,0x06,0x7d]
+0x7c,0x04,0x06,0x7d
+
+# GFX12: v_cmpx_le_f16_e32 -1, v2                ; encoding: [0xc1,0x04,0x06,0x7d]
+0xc1,0x04,0x06,0x7d
+
+# GFX12: v_cmpx_le_f16_e32 0.5, v2               ; encoding: [0xf0,0x04,0x06,0x7d]
+0xf0,0x04,0x06,0x7d
+
+# GFX12: v_cmpx_le_f16_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x06,0x7d]
+0xfd,0x04,0x06,0x7d
+
+# GFX12: v_cmpx_le_f16_e32 0xfe0b, v127          ; encoding: [0xff,0xfe,0x06,0x7d,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x06,0x7d,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_le_f32_e32 v1, v2                ; encoding: [0x01,0x05,0x26,0x7d]
+0x01,0x05,0x26,0x7d
+
+# GFX12: v_cmpx_le_f32_e32 v255, v2              ; encoding: [0xff,0x05,0x26,0x7d]
+0xff,0x05,0x26,0x7d
+
+# GFX12: v_cmpx_le_f32_e32 s1, v2                ; encoding: [0x01,0x04,0x26,0x7d]
+0x01,0x04,0x26,0x7d
+
+# GFX12: v_cmpx_le_f32_e32 s105, v2              ; encoding: [0x69,0x04,0x26,0x7d]
+0x69,0x04,0x26,0x7d
+
+# GFX12: v_cmpx_le_f32_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x26,0x7d]
+0x6a,0x04,0x26,0x7d
+
+# GFX12: v_cmpx_le_f32_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x26,0x7d]
+0x6b,0x04,0x26,0x7d
+
+# GFX12: v_cmpx_le_f32_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x26,0x7d]
+0x7b,0x04,0x26,0x7d
+
+# GFX12: v_cmpx_le_f32_e32 m0, v2                ; encoding: [0x7d,0x04,0x26,0x7d]
+0x7d,0x04,0x26,0x7d
+
+# GFX12: v_cmpx_le_f32_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x26,0x7d]
+0x7e,0x04,0x26,0x7d
+
+# GFX12: v_cmpx_le_f32_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x26,0x7d]
+0x7f,0x04,0x26,0x7d
+
+# GFX12: v_cmpx_le_f32_e32 null, v2              ; encoding: [0x7c,0x04,0x26,0x7d]
+0x7c,0x04,0x26,0x7d
+
+# GFX12: v_cmpx_le_f32_e32 -1, v2                ; encoding: [0xc1,0x04,0x26,0x7d]
+0xc1,0x04,0x26,0x7d
+
+# GFX12: v_cmpx_le_f32_e32 0.5, v2               ; encoding: [0xf0,0x04,0x26,0x7d]
+0xf0,0x04,0x26,0x7d
+
+# GFX12: v_cmpx_le_f32_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x26,0x7d]
+0xfd,0x04,0x26,0x7d
+
+# GFX12: v_cmpx_le_f32_e32 0xaf123456, v255      ; encoding: [0xff,0xfe,0x27,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x27,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_le_f64_e32 v[1:2], v[2:3]        ; encoding: [0x01,0x05,0x46,0x7d]
+0x01,0x05,0x46,0x7d
+
+# GFX12: v_cmpx_le_f64_e32 v[254:255], v[2:3]    ; encoding: [0xfe,0x05,0x46,0x7d]
+0xfe,0x05,0x46,0x7d
+
+# GFX12: v_cmpx_le_f64_e32 s[2:3], v[2:3]        ; encoding: [0x02,0x04,0x46,0x7d]
+0x02,0x04,0x46,0x7d
+
+# GFX12: v_cmpx_le_f64_e32 s[104:105], v[2:3]    ; encoding: [0x68,0x04,0x46,0x7d]
+0x68,0x04,0x46,0x7d
+
+# GFX12: v_cmpx_le_f64_e32 vcc, v[2:3]           ; encoding: [0x6a,0x04,0x46,0x7d]
+0x6a,0x04,0x46,0x7d
+
+# GFX12: v_cmpx_le_f64_e32 ttmp[14:15], v[2:3]   ; encoding: [0x7a,0x04,0x46,0x7d]
+0x7a,0x04,0x46,0x7d
+
+# GFX12: v_cmpx_le_f64_e32 exec, v[2:3]          ; encoding: [0x7e,0x04,0x46,0x7d]
+0x7e,0x04,0x46,0x7d
+
+# GFX12: v_cmpx_le_f64_e32 null, v[2:3]          ; encoding: [0x7c,0x04,0x46,0x7d]
+0x7c,0x04,0x46,0x7d
+
+# GFX12: v_cmpx_le_f64_e32 -1, v[2:3]            ; encoding: [0xc1,0x04,0x46,0x7d]
+0xc1,0x04,0x46,0x7d
+
+# GFX12: v_cmpx_le_f64_e32 0.5, v[2:3]           ; encoding: [0xf0,0x04,0x46,0x7d]
+0xf0,0x04,0x46,0x7d
+
+# GFX12: v_cmpx_le_f64_e32 src_scc, v[2:3]       ; encoding: [0xfd,0x04,0x46,0x7d]
+0xfd,0x04,0x46,0x7d
+
+# GFX12: v_cmpx_le_f64_e32 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x47,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x47,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_le_i16_e32 v1, v2                ; encoding: [0x01,0x05,0x66,0x7d]
+0x01,0x05,0x66,0x7d
+
+# GFX12: v_cmpx_le_i16_e32 v127, v2              ; encoding: [0x7f,0x05,0x66,0x7d]
+0x7f,0x05,0x66,0x7d
+
+# GFX12: v_cmpx_le_i16_e32 s1, v2                ; encoding: [0x01,0x04,0x66,0x7d]
+0x01,0x04,0x66,0x7d
+
+# GFX12: v_cmpx_le_i16_e32 s105, v2              ; encoding: [0x69,0x04,0x66,0x7d]
+0x69,0x04,0x66,0x7d
+
+# GFX12: v_cmpx_le_i16_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x66,0x7d]
+0x6a,0x04,0x66,0x7d
+
+# GFX12: v_cmpx_le_i16_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x66,0x7d]
+0x6b,0x04,0x66,0x7d
+
+# GFX12: v_cmpx_le_i16_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x66,0x7d]
+0x7b,0x04,0x66,0x7d
+
+# GFX12: v_cmpx_le_i16_e32 m0, v2                ; encoding: [0x7d,0x04,0x66,0x7d]
+0x7d,0x04,0x66,0x7d
+
+# GFX12: v_cmpx_le_i16_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x66,0x7d]
+0x7e,0x04,0x66,0x7d
+
+# GFX12: v_cmpx_le_i16_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x66,0x7d]
+0x7f,0x04,0x66,0x7d
+
+# GFX12: v_cmpx_le_i16_e32 null, v2              ; encoding: [0x7c,0x04,0x66,0x7d]
+0x7c,0x04,0x66,0x7d
+
+# GFX12: v_cmpx_le_i16_e32 -1, v2                ; encoding: [0xc1,0x04,0x66,0x7d]
+0xc1,0x04,0x66,0x7d
+
+# GFX12: v_cmpx_le_i16_e32 0x3800, v2
+0xf0,0x04,0x66,0x7d
+
+# GFX12: v_cmpx_le_i16_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x66,0x7d]
+0xfd,0x04,0x66,0x7d
+
+# GFX12: v_cmpx_le_i16_e32 0xfe0b, v127          ; encoding: [0xff,0xfe,0x66,0x7d,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x66,0x7d,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_le_i32_e32 v1, v2                ; encoding: [0x01,0x05,0x86,0x7d]
+0x01,0x05,0x86,0x7d
+
+# GFX12: v_cmpx_le_i32_e32 v255, v2              ; encoding: [0xff,0x05,0x86,0x7d]
+0xff,0x05,0x86,0x7d
+
+# GFX12: v_cmpx_le_i32_e32 s1, v2                ; encoding: [0x01,0x04,0x86,0x7d]
+0x01,0x04,0x86,0x7d
+
+# GFX12: v_cmpx_le_i32_e32 s105, v2              ; encoding: [0x69,0x04,0x86,0x7d]
+0x69,0x04,0x86,0x7d
+
+# GFX12: v_cmpx_le_i32_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x86,0x7d]
+0x6a,0x04,0x86,0x7d
+
+# GFX12: v_cmpx_le_i32_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x86,0x7d]
+0x6b,0x04,0x86,0x7d
+
+# GFX12: v_cmpx_le_i32_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x86,0x7d]
+0x7b,0x04,0x86,0x7d
+
+# GFX12: v_cmpx_le_i32_e32 m0, v2                ; encoding: [0x7d,0x04,0x86,0x7d]
+0x7d,0x04,0x86,0x7d
+
+# GFX12: v_cmpx_le_i32_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x86,0x7d]
+0x7e,0x04,0x86,0x7d
+
+# GFX12: v_cmpx_le_i32_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x86,0x7d]
+0x7f,0x04,0x86,0x7d
+
+# GFX12: v_cmpx_le_i32_e32 null, v2              ; encoding: [0x7c,0x04,0x86,0x7d]
+0x7c,0x04,0x86,0x7d
+
+# GFX12: v_cmpx_le_i32_e32 -1, v2                ; encoding: [0xc1,0x04,0x86,0x7d]
+0xc1,0x04,0x86,0x7d
+
+# GFX12: v_cmpx_le_i32_e32 0.5, v2               ; encoding: [0xf0,0x04,0x86,0x7d]
+0xf0,0x04,0x86,0x7d
+
+# GFX12: v_cmpx_le_i32_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x86,0x7d]
+0xfd,0x04,0x86,0x7d
+
+# GFX12: v_cmpx_le_i32_e32 0xaf123456, v255      ; encoding: [0xff,0xfe,0x87,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x87,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_le_i64_e32 v[1:2], v[2:3]        ; encoding: [0x01,0x05,0xa6,0x7d]
+0x01,0x05,0xa6,0x7d
+
+# GFX12: v_cmpx_le_i64_e32 v[254:255], v[2:3]    ; encoding: [0xfe,0x05,0xa6,0x7d]
+0xfe,0x05,0xa6,0x7d
+
+# GFX12: v_cmpx_le_i64_e32 s[2:3], v[2:3]        ; encoding: [0x02,0x04,0xa6,0x7d]
+0x02,0x04,0xa6,0x7d
+
+# GFX12: v_cmpx_le_i64_e32 s[104:105], v[2:3]    ; encoding: [0x68,0x04,0xa6,0x7d]
+0x68,0x04,0xa6,0x7d
+
+# GFX12: v_cmpx_le_i64_e32 vcc, v[2:3]           ; encoding: [0x6a,0x04,0xa6,0x7d]
+0x6a,0x04,0xa6,0x7d
+
+# GFX12: v_cmpx_le_i64_e32 ttmp[14:15], v[2:3]   ; encoding: [0x7a,0x04,0xa6,0x7d]
+0x7a,0x04,0xa6,0x7d
+
+# GFX12: v_cmpx_le_i64_e32 exec, v[2:3]          ; encoding: [0x7e,0x04,0xa6,0x7d]
+0x7e,0x04,0xa6,0x7d
+
+# GFX12: v_cmpx_le_i64_e32 null, v[2:3]          ; encoding: [0x7c,0x04,0xa6,0x7d]
+0x7c,0x04,0xa6,0x7d
+
+# GFX12: v_cmpx_le_i64_e32 -1, v[2:3]            ; encoding: [0xc1,0x04,0xa6,0x7d]
+0xc1,0x04,0xa6,0x7d
+
+# GFX12: v_cmpx_le_i64_e32 0.5, v[2:3]           ; encoding: [0xf0,0x04,0xa6,0x7d]
+0xf0,0x04,0xa6,0x7d
+
+# GFX12: v_cmpx_le_i64_e32 src_scc, v[2:3]       ; encoding: [0xfd,0x04,0xa6,0x7d]
+0xfd,0x04,0xa6,0x7d
+
+# GFX12: v_cmpx_le_i64_e32 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xa7,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xa7,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_le_u16_e32 v1, v2                ; encoding: [0x01,0x05,0x76,0x7d]
+0x01,0x05,0x76,0x7d
+
+# GFX12: v_cmpx_le_u16_e32 v127, v2              ; encoding: [0x7f,0x05,0x76,0x7d]
+0x7f,0x05,0x76,0x7d
+
+# GFX12: v_cmpx_le_u16_e32 s1, v2                ; encoding: [0x01,0x04,0x76,0x7d]
+0x01,0x04,0x76,0x7d
+
+# GFX12: v_cmpx_le_u16_e32 s105, v2              ; encoding: [0x69,0x04,0x76,0x7d]
+0x69,0x04,0x76,0x7d
+
+# GFX12: v_cmpx_le_u16_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x76,0x7d]
+0x6a,0x04,0x76,0x7d
+
+# GFX12: v_cmpx_le_u16_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x76,0x7d]
+0x6b,0x04,0x76,0x7d
+
+# GFX12: v_cmpx_le_u16_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x76,0x7d]
+0x7b,0x04,0x76,0x7d
+
+# GFX12: v_cmpx_le_u16_e32 m0, v2                ; encoding: [0x7d,0x04,0x76,0x7d]
+0x7d,0x04,0x76,0x7d
+
+# GFX12: v_cmpx_le_u16_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x76,0x7d]
+0x7e,0x04,0x76,0x7d
+
+# GFX12: v_cmpx_le_u16_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x76,0x7d]
+0x7f,0x04,0x76,0x7d
+
+# GFX12: v_cmpx_le_u16_e32 null, v2              ; encoding: [0x7c,0x04,0x76,0x7d]
+0x7c,0x04,0x76,0x7d
+
+# GFX12: v_cmpx_le_u16_e32 -1, v2                ; encoding: [0xc1,0x04,0x76,0x7d]
+0xc1,0x04,0x76,0x7d
+
+# GFX12: v_cmpx_le_u16_e32 0x3800, v2
+0xf0,0x04,0x76,0x7d
+
+# GFX12: v_cmpx_le_u16_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x76,0x7d]
+0xfd,0x04,0x76,0x7d
+
+# GFX12: v_cmpx_le_u16_e32 0xfe0b, v127          ; encoding: [0xff,0xfe,0x76,0x7d,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x76,0x7d,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_le_u32_e32 v1, v2                ; encoding: [0x01,0x05,0x96,0x7d]
+0x01,0x05,0x96,0x7d
+
+# GFX12: v_cmpx_le_u32_e32 v255, v2              ; encoding: [0xff,0x05,0x96,0x7d]
+0xff,0x05,0x96,0x7d
+
+# GFX12: v_cmpx_le_u32_e32 s1, v2                ; encoding: [0x01,0x04,0x96,0x7d]
+0x01,0x04,0x96,0x7d
+
+# GFX12: v_cmpx_le_u32_e32 s105, v2              ; encoding: [0x69,0x04,0x96,0x7d]
+0x69,0x04,0x96,0x7d
+
+# GFX12: v_cmpx_le_u32_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x96,0x7d]
+0x6a,0x04,0x96,0x7d
+
+# GFX12: v_cmpx_le_u32_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x96,0x7d]
+0x6b,0x04,0x96,0x7d
+
+# GFX12: v_cmpx_le_u32_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x96,0x7d]
+0x7b,0x04,0x96,0x7d
+
+# GFX12: v_cmpx_le_u32_e32 m0, v2                ; encoding: [0x7d,0x04,0x96,0x7d]
+0x7d,0x04,0x96,0x7d
+
+# GFX12: v_cmpx_le_u32_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x96,0x7d]
+0x7e,0x04,0x96,0x7d
+
+# GFX12: v_cmpx_le_u32_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x96,0x7d]
+0x7f,0x04,0x96,0x7d
+
+# GFX12: v_cmpx_le_u32_e32 null, v2              ; encoding: [0x7c,0x04,0x96,0x7d]
+0x7c,0x04,0x96,0x7d
+
+# GFX12: v_cmpx_le_u32_e32 -1, v2                ; encoding: [0xc1,0x04,0x96,0x7d]
+0xc1,0x04,0x96,0x7d
+
+# GFX12: v_cmpx_le_u32_e32 0.5, v2               ; encoding: [0xf0,0x04,0x96,0x7d]
+0xf0,0x04,0x96,0x7d
+
+# GFX12: v_cmpx_le_u32_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x96,0x7d]
+0xfd,0x04,0x96,0x7d
+
+# GFX12: v_cmpx_le_u32_e32 0xaf123456, v255      ; encoding: [0xff,0xfe,0x97,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x97,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_le_u64_e32 v[1:2], v[2:3]        ; encoding: [0x01,0x05,0xb6,0x7d]
+0x01,0x05,0xb6,0x7d
+
+# GFX12: v_cmpx_le_u64_e32 v[254:255], v[2:3]    ; encoding: [0xfe,0x05,0xb6,0x7d]
+0xfe,0x05,0xb6,0x7d
+
+# GFX12: v_cmpx_le_u64_e32 s[2:3], v[2:3]        ; encoding: [0x02,0x04,0xb6,0x7d]
+0x02,0x04,0xb6,0x7d
+
+# GFX12: v_cmpx_le_u64_e32 s[104:105], v[2:3]    ; encoding: [0x68,0x04,0xb6,0x7d]
+0x68,0x04,0xb6,0x7d
+
+# GFX12: v_cmpx_le_u64_e32 vcc, v[2:3]           ; encoding: [0x6a,0x04,0xb6,0x7d]
+0x6a,0x04,0xb6,0x7d
+
+# GFX12: v_cmpx_le_u64_e32 ttmp[14:15], v[2:3]   ; encoding: [0x7a,0x04,0xb6,0x7d]
+0x7a,0x04,0xb6,0x7d
+
+# GFX12: v_cmpx_le_u64_e32 exec, v[2:3]          ; encoding: [0x7e,0x04,0xb6,0x7d]
+0x7e,0x04,0xb6,0x7d
+
+# GFX12: v_cmpx_le_u64_e32 null, v[2:3]          ; encoding: [0x7c,0x04,0xb6,0x7d]
+0x7c,0x04,0xb6,0x7d
+
+# GFX12: v_cmpx_le_u64_e32 -1, v[2:3]            ; encoding: [0xc1,0x04,0xb6,0x7d]
+0xc1,0x04,0xb6,0x7d
+
+# GFX12: v_cmpx_le_u64_e32 0.5, v[2:3]           ; encoding: [0xf0,0x04,0xb6,0x7d]
+0xf0,0x04,0xb6,0x7d
+
+# GFX12: v_cmpx_le_u64_e32 src_scc, v[2:3]       ; encoding: [0xfd,0x04,0xb6,0x7d]
+0xfd,0x04,0xb6,0x7d
+
+# GFX12: v_cmpx_le_u64_e32 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xb7,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xb7,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_lg_f16_e32 v1, v2                ; encoding: [0x01,0x05,0x0a,0x7d]
+0x01,0x05,0x0a,0x7d
+
+# GFX12: v_cmpx_lg_f16_e32 v127, v2              ; encoding: [0x7f,0x05,0x0a,0x7d]
+0x7f,0x05,0x0a,0x7d
+
+# GFX12: v_cmpx_lg_f16_e32 s1, v2                ; encoding: [0x01,0x04,0x0a,0x7d]
+0x01,0x04,0x0a,0x7d
+
+# GFX12: v_cmpx_lg_f16_e32 s105, v2              ; encoding: [0x69,0x04,0x0a,0x7d]
+0x69,0x04,0x0a,0x7d
+
+# GFX12: v_cmpx_lg_f16_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x0a,0x7d]
+0x6a,0x04,0x0a,0x7d
+
+# GFX12: v_cmpx_lg_f16_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x0a,0x7d]
+0x6b,0x04,0x0a,0x7d
+
+# GFX12: v_cmpx_lg_f16_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x0a,0x7d]
+0x7b,0x04,0x0a,0x7d
+
+# GFX12: v_cmpx_lg_f16_e32 m0, v2                ; encoding: [0x7d,0x04,0x0a,0x7d]
+0x7d,0x04,0x0a,0x7d
+
+# GFX12: v_cmpx_lg_f16_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x0a,0x7d]
+0x7e,0x04,0x0a,0x7d
+
+# GFX12: v_cmpx_lg_f16_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x0a,0x7d]
+0x7f,0x04,0x0a,0x7d
+
+# GFX12: v_cmpx_lg_f16_e32 null, v2              ; encoding: [0x7c,0x04,0x0a,0x7d]
+0x7c,0x04,0x0a,0x7d
+
+# GFX12: v_cmpx_lg_f16_e32 -1, v2                ; encoding: [0xc1,0x04,0x0a,0x7d]
+0xc1,0x04,0x0a,0x7d
+
+# GFX12: v_cmpx_lg_f16_e32 0.5, v2               ; encoding: [0xf0,0x04,0x0a,0x7d]
+0xf0,0x04,0x0a,0x7d
+
+# GFX12: v_cmpx_lg_f16_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x0a,0x7d]
+0xfd,0x04,0x0a,0x7d
+
+# GFX12: v_cmpx_lg_f16_e32 0xfe0b, v127          ; encoding: [0xff,0xfe,0x0a,0x7d,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x0a,0x7d,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_lg_f32_e32 v1, v2                ; encoding: [0x01,0x05,0x2a,0x7d]
+0x01,0x05,0x2a,0x7d
+
+# GFX12: v_cmpx_lg_f32_e32 v255, v2              ; encoding: [0xff,0x05,0x2a,0x7d]
+0xff,0x05,0x2a,0x7d
+
+# GFX12: v_cmpx_lg_f32_e32 s1, v2                ; encoding: [0x01,0x04,0x2a,0x7d]
+0x01,0x04,0x2a,0x7d
+
+# GFX12: v_cmpx_lg_f32_e32 s105, v2              ; encoding: [0x69,0x04,0x2a,0x7d]
+0x69,0x04,0x2a,0x7d
+
+# GFX12: v_cmpx_lg_f32_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x2a,0x7d]
+0x6a,0x04,0x2a,0x7d
+
+# GFX12: v_cmpx_lg_f32_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x2a,0x7d]
+0x6b,0x04,0x2a,0x7d
+
+# GFX12: v_cmpx_lg_f32_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x2a,0x7d]
+0x7b,0x04,0x2a,0x7d
+
+# GFX12: v_cmpx_lg_f32_e32 m0, v2                ; encoding: [0x7d,0x04,0x2a,0x7d]
+0x7d,0x04,0x2a,0x7d
+
+# GFX12: v_cmpx_lg_f32_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x2a,0x7d]
+0x7e,0x04,0x2a,0x7d
+
+# GFX12: v_cmpx_lg_f32_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x2a,0x7d]
+0x7f,0x04,0x2a,0x7d
+
+# GFX12: v_cmpx_lg_f32_e32 null, v2              ; encoding: [0x7c,0x04,0x2a,0x7d]
+0x7c,0x04,0x2a,0x7d
+
+# GFX12: v_cmpx_lg_f32_e32 -1, v2                ; encoding: [0xc1,0x04,0x2a,0x7d]
+0xc1,0x04,0x2a,0x7d
+
+# GFX12: v_cmpx_lg_f32_e32 0.5, v2               ; encoding: [0xf0,0x04,0x2a,0x7d]
+0xf0,0x04,0x2a,0x7d
+
+# GFX12: v_cmpx_lg_f32_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x2a,0x7d]
+0xfd,0x04,0x2a,0x7d
+
+# GFX12: v_cmpx_lg_f32_e32 0xaf123456, v255      ; encoding: [0xff,0xfe,0x2b,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x2b,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_lg_f64_e32 v[1:2], v[2:3]        ; encoding: [0x01,0x05,0x4a,0x7d]
+0x01,0x05,0x4a,0x7d
+
+# GFX12: v_cmpx_lg_f64_e32 v[254:255], v[2:3]    ; encoding: [0xfe,0x05,0x4a,0x7d]
+0xfe,0x05,0x4a,0x7d
+
+# GFX12: v_cmpx_lg_f64_e32 s[2:3], v[2:3]        ; encoding: [0x02,0x04,0x4a,0x7d]
+0x02,0x04,0x4a,0x7d
+
+# GFX12: v_cmpx_lg_f64_e32 s[104:105], v[2:3]    ; encoding: [0x68,0x04,0x4a,0x7d]
+0x68,0x04,0x4a,0x7d
+
+# GFX12: v_cmpx_lg_f64_e32 vcc, v[2:3]           ; encoding: [0x6a,0x04,0x4a,0x7d]
+0x6a,0x04,0x4a,0x7d
+
+# GFX12: v_cmpx_lg_f64_e32 ttmp[14:15], v[2:3]   ; encoding: [0x7a,0x04,0x4a,0x7d]
+0x7a,0x04,0x4a,0x7d
+
+# GFX12: v_cmpx_lg_f64_e32 exec, v[2:3]          ; encoding: [0x7e,0x04,0x4a,0x7d]
+0x7e,0x04,0x4a,0x7d
+
+# GFX12: v_cmpx_lg_f64_e32 null, v[2:3]          ; encoding: [0x7c,0x04,0x4a,0x7d]
+0x7c,0x04,0x4a,0x7d
+
+# GFX12: v_cmpx_lg_f64_e32 -1, v[2:3]            ; encoding: [0xc1,0x04,0x4a,0x7d]
+0xc1,0x04,0x4a,0x7d
+
+# GFX12: v_cmpx_lg_f64_e32 0.5, v[2:3]           ; encoding: [0xf0,0x04,0x4a,0x7d]
+0xf0,0x04,0x4a,0x7d
+
+# GFX12: v_cmpx_lg_f64_e32 src_scc, v[2:3]       ; encoding: [0xfd,0x04,0x4a,0x7d]
+0xfd,0x04,0x4a,0x7d
+
+# GFX12: v_cmpx_lg_f64_e32 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x4b,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x4b,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_lt_f16_e32 v1, v2                ; encoding: [0x01,0x05,0x02,0x7d]
+0x01,0x05,0x02,0x7d
+
+# GFX12: v_cmpx_lt_f16_e32 v127, v2              ; encoding: [0x7f,0x05,0x02,0x7d]
+0x7f,0x05,0x02,0x7d
+
+# GFX12: v_cmpx_lt_f16_e32 s1, v2                ; encoding: [0x01,0x04,0x02,0x7d]
+0x01,0x04,0x02,0x7d
+
+# GFX12: v_cmpx_lt_f16_e32 s105, v2              ; encoding: [0x69,0x04,0x02,0x7d]
+0x69,0x04,0x02,0x7d
+
+# GFX12: v_cmpx_lt_f16_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x02,0x7d]
+0x6a,0x04,0x02,0x7d
+
+# GFX12: v_cmpx_lt_f16_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x02,0x7d]
+0x6b,0x04,0x02,0x7d
+
+# GFX12: v_cmpx_lt_f16_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x02,0x7d]
+0x7b,0x04,0x02,0x7d
+
+# GFX12: v_cmpx_lt_f16_e32 m0, v2                ; encoding: [0x7d,0x04,0x02,0x7d]
+0x7d,0x04,0x02,0x7d
+
+# GFX12: v_cmpx_lt_f16_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x02,0x7d]
+0x7e,0x04,0x02,0x7d
+
+# GFX12: v_cmpx_lt_f16_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x02,0x7d]
+0x7f,0x04,0x02,0x7d
+
+# GFX12: v_cmpx_lt_f16_e32 null, v2              ; encoding: [0x7c,0x04,0x02,0x7d]
+0x7c,0x04,0x02,0x7d
+
+# GFX12: v_cmpx_lt_f16_e32 -1, v2                ; encoding: [0xc1,0x04,0x02,0x7d]
+0xc1,0x04,0x02,0x7d
+
+# GFX12: v_cmpx_lt_f16_e32 0.5, v2               ; encoding: [0xf0,0x04,0x02,0x7d]
+0xf0,0x04,0x02,0x7d
+
+# GFX12: v_cmpx_lt_f16_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x02,0x7d]
+0xfd,0x04,0x02,0x7d
+
+# GFX12: v_cmpx_lt_f16_e32 0xfe0b, v127          ; encoding: [0xff,0xfe,0x02,0x7d,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x02,0x7d,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_lt_f32_e32 v1, v2                ; encoding: [0x01,0x05,0x22,0x7d]
+0x01,0x05,0x22,0x7d
+
+# GFX12: v_cmpx_lt_f32_e32 v255, v2              ; encoding: [0xff,0x05,0x22,0x7d]
+0xff,0x05,0x22,0x7d
+
+# GFX12: v_cmpx_lt_f32_e32 s1, v2                ; encoding: [0x01,0x04,0x22,0x7d]
+0x01,0x04,0x22,0x7d
+
+# GFX12: v_cmpx_lt_f32_e32 s105, v2              ; encoding: [0x69,0x04,0x22,0x7d]
+0x69,0x04,0x22,0x7d
+
+# GFX12: v_cmpx_lt_f32_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x22,0x7d]
+0x6a,0x04,0x22,0x7d
+
+# GFX12: v_cmpx_lt_f32_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x22,0x7d]
+0x6b,0x04,0x22,0x7d
+
+# GFX12: v_cmpx_lt_f32_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x22,0x7d]
+0x7b,0x04,0x22,0x7d
+
+# GFX12: v_cmpx_lt_f32_e32 m0, v2                ; encoding: [0x7d,0x04,0x22,0x7d]
+0x7d,0x04,0x22,0x7d
+
+# GFX12: v_cmpx_lt_f32_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x22,0x7d]
+0x7e,0x04,0x22,0x7d
+
+# GFX12: v_cmpx_lt_f32_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x22,0x7d]
+0x7f,0x04,0x22,0x7d
+
+# GFX12: v_cmpx_lt_f32_e32 null, v2              ; encoding: [0x7c,0x04,0x22,0x7d]
+0x7c,0x04,0x22,0x7d
+
+# GFX12: v_cmpx_lt_f32_e32 -1, v2                ; encoding: [0xc1,0x04,0x22,0x7d]
+0xc1,0x04,0x22,0x7d
+
+# GFX12: v_cmpx_lt_f32_e32 0.5, v2               ; encoding: [0xf0,0x04,0x22,0x7d]
+0xf0,0x04,0x22,0x7d
+
+# GFX12: v_cmpx_lt_f32_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x22,0x7d]
+0xfd,0x04,0x22,0x7d
+
+# GFX12: v_cmpx_lt_f32_e32 0xaf123456, v255      ; encoding: [0xff,0xfe,0x23,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x23,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_lt_f64_e32 v[1:2], v[2:3]        ; encoding: [0x01,0x05,0x42,0x7d]
+0x01,0x05,0x42,0x7d
+
+# GFX12: v_cmpx_lt_f64_e32 v[254:255], v[2:3]    ; encoding: [0xfe,0x05,0x42,0x7d]
+0xfe,0x05,0x42,0x7d
+
+# GFX12: v_cmpx_lt_f64_e32 s[2:3], v[2:3]        ; encoding: [0x02,0x04,0x42,0x7d]
+0x02,0x04,0x42,0x7d
+
+# GFX12: v_cmpx_lt_f64_e32 s[104:105], v[2:3]    ; encoding: [0x68,0x04,0x42,0x7d]
+0x68,0x04,0x42,0x7d
+
+# GFX12: v_cmpx_lt_f64_e32 vcc, v[2:3]           ; encoding: [0x6a,0x04,0x42,0x7d]
+0x6a,0x04,0x42,0x7d
+
+# GFX12: v_cmpx_lt_f64_e32 ttmp[14:15], v[2:3]   ; encoding: [0x7a,0x04,0x42,0x7d]
+0x7a,0x04,0x42,0x7d
+
+# GFX12: v_cmpx_lt_f64_e32 exec, v[2:3]          ; encoding: [0x7e,0x04,0x42,0x7d]
+0x7e,0x04,0x42,0x7d
+
+# GFX12: v_cmpx_lt_f64_e32 null, v[2:3]          ; encoding: [0x7c,0x04,0x42,0x7d]
+0x7c,0x04,0x42,0x7d
+
+# GFX12: v_cmpx_lt_f64_e32 -1, v[2:3]            ; encoding: [0xc1,0x04,0x42,0x7d]
+0xc1,0x04,0x42,0x7d
+
+# GFX12: v_cmpx_lt_f64_e32 0.5, v[2:3]           ; encoding: [0xf0,0x04,0x42,0x7d]
+0xf0,0x04,0x42,0x7d
+
+# GFX12: v_cmpx_lt_f64_e32 src_scc, v[2:3]       ; encoding: [0xfd,0x04,0x42,0x7d]
+0xfd,0x04,0x42,0x7d
+
+# GFX12: v_cmpx_lt_f64_e32 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x43,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x43,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_lt_i16_e32 v1, v2                ; encoding: [0x01,0x05,0x62,0x7d]
+0x01,0x05,0x62,0x7d
+
+# GFX12: v_cmpx_lt_i16_e32 v127, v2              ; encoding: [0x7f,0x05,0x62,0x7d]
+0x7f,0x05,0x62,0x7d
+
+# GFX12: v_cmpx_lt_i16_e32 s1, v2                ; encoding: [0x01,0x04,0x62,0x7d]
+0x01,0x04,0x62,0x7d
+
+# GFX12: v_cmpx_lt_i16_e32 s105, v2              ; encoding: [0x69,0x04,0x62,0x7d]
+0x69,0x04,0x62,0x7d
+
+# GFX12: v_cmpx_lt_i16_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x62,0x7d]
+0x6a,0x04,0x62,0x7d
+
+# GFX12: v_cmpx_lt_i16_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x62,0x7d]
+0x6b,0x04,0x62,0x7d
+
+# GFX12: v_cmpx_lt_i16_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x62,0x7d]
+0x7b,0x04,0x62,0x7d
+
+# GFX12: v_cmpx_lt_i16_e32 m0, v2                ; encoding: [0x7d,0x04,0x62,0x7d]
+0x7d,0x04,0x62,0x7d
+
+# GFX12: v_cmpx_lt_i16_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x62,0x7d]
+0x7e,0x04,0x62,0x7d
+
+# GFX12: v_cmpx_lt_i16_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x62,0x7d]
+0x7f,0x04,0x62,0x7d
+
+# GFX12: v_cmpx_lt_i16_e32 null, v2              ; encoding: [0x7c,0x04,0x62,0x7d]
+0x7c,0x04,0x62,0x7d
+
+# GFX12: v_cmpx_lt_i16_e32 -1, v2                ; encoding: [0xc1,0x04,0x62,0x7d]
+0xc1,0x04,0x62,0x7d
+
+# GFX12: v_cmpx_lt_i16_e32 0x3800, v2
+0xf0,0x04,0x62,0x7d
+
+# GFX12: v_cmpx_lt_i16_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x62,0x7d]
+0xfd,0x04,0x62,0x7d
+
+# GFX12: v_cmpx_lt_i16_e32 0xfe0b, v127          ; encoding: [0xff,0xfe,0x62,0x7d,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x62,0x7d,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_lt_i32_e32 v1, v2                ; encoding: [0x01,0x05,0x82,0x7d]
+0x01,0x05,0x82,0x7d
+
+# GFX12: v_cmpx_lt_i32_e32 v255, v2              ; encoding: [0xff,0x05,0x82,0x7d]
+0xff,0x05,0x82,0x7d
+
+# GFX12: v_cmpx_lt_i32_e32 s1, v2                ; encoding: [0x01,0x04,0x82,0x7d]
+0x01,0x04,0x82,0x7d
+
+# GFX12: v_cmpx_lt_i32_e32 s105, v2              ; encoding: [0x69,0x04,0x82,0x7d]
+0x69,0x04,0x82,0x7d
+
+# GFX12: v_cmpx_lt_i32_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x82,0x7d]
+0x6a,0x04,0x82,0x7d
+
+# GFX12: v_cmpx_lt_i32_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x82,0x7d]
+0x6b,0x04,0x82,0x7d
+
+# GFX12: v_cmpx_lt_i32_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x82,0x7d]
+0x7b,0x04,0x82,0x7d
+
+# GFX12: v_cmpx_lt_i32_e32 m0, v2                ; encoding: [0x7d,0x04,0x82,0x7d]
+0x7d,0x04,0x82,0x7d
+
+# GFX12: v_cmpx_lt_i32_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x82,0x7d]
+0x7e,0x04,0x82,0x7d
+
+# GFX12: v_cmpx_lt_i32_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x82,0x7d]
+0x7f,0x04,0x82,0x7d
+
+# GFX12: v_cmpx_lt_i32_e32 null, v2              ; encoding: [0x7c,0x04,0x82,0x7d]
+0x7c,0x04,0x82,0x7d
+
+# GFX12: v_cmpx_lt_i32_e32 -1, v2                ; encoding: [0xc1,0x04,0x82,0x7d]
+0xc1,0x04,0x82,0x7d
+
+# GFX12: v_cmpx_lt_i32_e32 0.5, v2               ; encoding: [0xf0,0x04,0x82,0x7d]
+0xf0,0x04,0x82,0x7d
+
+# GFX12: v_cmpx_lt_i32_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x82,0x7d]
+0xfd,0x04,0x82,0x7d
+
+# GFX12: v_cmpx_lt_i32_e32 0xaf123456, v255      ; encoding: [0xff,0xfe,0x83,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x83,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_lt_i64_e32 v[1:2], v[2:3]        ; encoding: [0x01,0x05,0xa2,0x7d]
+0x01,0x05,0xa2,0x7d
+
+# GFX12: v_cmpx_lt_i64_e32 v[254:255], v[2:3]    ; encoding: [0xfe,0x05,0xa2,0x7d]
+0xfe,0x05,0xa2,0x7d
+
+# GFX12: v_cmpx_lt_i64_e32 s[2:3], v[2:3]        ; encoding: [0x02,0x04,0xa2,0x7d]
+0x02,0x04,0xa2,0x7d
+
+# GFX12: v_cmpx_lt_i64_e32 s[104:105], v[2:3]    ; encoding: [0x68,0x04,0xa2,0x7d]
+0x68,0x04,0xa2,0x7d
+
+# GFX12: v_cmpx_lt_i64_e32 vcc, v[2:3]           ; encoding: [0x6a,0x04,0xa2,0x7d]
+0x6a,0x04,0xa2,0x7d
+
+# GFX12: v_cmpx_lt_i64_e32 ttmp[14:15], v[2:3]   ; encoding: [0x7a,0x04,0xa2,0x7d]
+0x7a,0x04,0xa2,0x7d
+
+# GFX12: v_cmpx_lt_i64_e32 exec, v[2:3]          ; encoding: [0x7e,0x04,0xa2,0x7d]
+0x7e,0x04,0xa2,0x7d
+
+# GFX12: v_cmpx_lt_i64_e32 null, v[2:3]          ; encoding: [0x7c,0x04,0xa2,0x7d]
+0x7c,0x04,0xa2,0x7d
+
+# GFX12: v_cmpx_lt_i64_e32 -1, v[2:3]            ; encoding: [0xc1,0x04,0xa2,0x7d]
+0xc1,0x04,0xa2,0x7d
+
+# GFX12: v_cmpx_lt_i64_e32 0.5, v[2:3]           ; encoding: [0xf0,0x04,0xa2,0x7d]
+0xf0,0x04,0xa2,0x7d
+
+# GFX12: v_cmpx_lt_i64_e32 src_scc, v[2:3]       ; encoding: [0xfd,0x04,0xa2,0x7d]
+0xfd,0x04,0xa2,0x7d
+
+# GFX12: v_cmpx_lt_i64_e32 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xa3,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xa3,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_lt_u16_e32 v1, v2                ; encoding: [0x01,0x05,0x72,0x7d]
+0x01,0x05,0x72,0x7d
+
+# GFX12: v_cmpx_lt_u16_e32 v127, v2              ; encoding: [0x7f,0x05,0x72,0x7d]
+0x7f,0x05,0x72,0x7d
+
+# GFX12: v_cmpx_lt_u16_e32 s1, v2                ; encoding: [0x01,0x04,0x72,0x7d]
+0x01,0x04,0x72,0x7d
+
+# GFX12: v_cmpx_lt_u16_e32 s105, v2              ; encoding: [0x69,0x04,0x72,0x7d]
+0x69,0x04,0x72,0x7d
+
+# GFX12: v_cmpx_lt_u16_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x72,0x7d]
+0x6a,0x04,0x72,0x7d
+
+# GFX12: v_cmpx_lt_u16_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x72,0x7d]
+0x6b,0x04,0x72,0x7d
+
+# GFX12: v_cmpx_lt_u16_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x72,0x7d]
+0x7b,0x04,0x72,0x7d
+
+# GFX12: v_cmpx_lt_u16_e32 m0, v2                ; encoding: [0x7d,0x04,0x72,0x7d]
+0x7d,0x04,0x72,0x7d
+
+# GFX12: v_cmpx_lt_u16_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x72,0x7d]
+0x7e,0x04,0x72,0x7d
+
+# GFX12: v_cmpx_lt_u16_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x72,0x7d]
+0x7f,0x04,0x72,0x7d
+
+# GFX12: v_cmpx_lt_u16_e32 null, v2              ; encoding: [0x7c,0x04,0x72,0x7d]
+0x7c,0x04,0x72,0x7d
+
+# GFX12: v_cmpx_lt_u16_e32 -1, v2                ; encoding: [0xc1,0x04,0x72,0x7d]
+0xc1,0x04,0x72,0x7d
+
+# GFX12: v_cmpx_lt_u16_e32 0x3800, v2
+0xf0,0x04,0x72,0x7d
+
+# GFX12: v_cmpx_lt_u16_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x72,0x7d]
+0xfd,0x04,0x72,0x7d
+
+# GFX12: v_cmpx_lt_u16_e32 0xfe0b, v127          ; encoding: [0xff,0xfe,0x72,0x7d,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x72,0x7d,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_lt_u32_e32 v1, v2                ; encoding: [0x01,0x05,0x92,0x7d]
+0x01,0x05,0x92,0x7d
+
+# GFX12: v_cmpx_lt_u32_e32 v255, v2              ; encoding: [0xff,0x05,0x92,0x7d]
+0xff,0x05,0x92,0x7d
+
+# GFX12: v_cmpx_lt_u32_e32 s1, v2                ; encoding: [0x01,0x04,0x92,0x7d]
+0x01,0x04,0x92,0x7d
+
+# GFX12: v_cmpx_lt_u32_e32 s105, v2              ; encoding: [0x69,0x04,0x92,0x7d]
+0x69,0x04,0x92,0x7d
+
+# GFX12: v_cmpx_lt_u32_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x92,0x7d]
+0x6a,0x04,0x92,0x7d
+
+# GFX12: v_cmpx_lt_u32_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x92,0x7d]
+0x6b,0x04,0x92,0x7d
+
+# GFX12: v_cmpx_lt_u32_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x92,0x7d]
+0x7b,0x04,0x92,0x7d
+
+# GFX12: v_cmpx_lt_u32_e32 m0, v2                ; encoding: [0x7d,0x04,0x92,0x7d]
+0x7d,0x04,0x92,0x7d
+
+# GFX12: v_cmpx_lt_u32_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x92,0x7d]
+0x7e,0x04,0x92,0x7d
+
+# GFX12: v_cmpx_lt_u32_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x92,0x7d]
+0x7f,0x04,0x92,0x7d
+
+# GFX12: v_cmpx_lt_u32_e32 null, v2              ; encoding: [0x7c,0x04,0x92,0x7d]
+0x7c,0x04,0x92,0x7d
+
+# GFX12: v_cmpx_lt_u32_e32 -1, v2                ; encoding: [0xc1,0x04,0x92,0x7d]
+0xc1,0x04,0x92,0x7d
+
+# GFX12: v_cmpx_lt_u32_e32 0.5, v2               ; encoding: [0xf0,0x04,0x92,0x7d]
+0xf0,0x04,0x92,0x7d
+
+# GFX12: v_cmpx_lt_u32_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x92,0x7d]
+0xfd,0x04,0x92,0x7d
+
+# GFX12: v_cmpx_lt_u32_e32 0xaf123456, v255      ; encoding: [0xff,0xfe,0x93,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x93,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_lt_u64_e32 v[1:2], v[2:3]        ; encoding: [0x01,0x05,0xb2,0x7d]
+0x01,0x05,0xb2,0x7d
+
+# GFX12: v_cmpx_lt_u64_e32 v[254:255], v[2:3]    ; encoding: [0xfe,0x05,0xb2,0x7d]
+0xfe,0x05,0xb2,0x7d
+
+# GFX12: v_cmpx_lt_u64_e32 s[2:3], v[2:3]        ; encoding: [0x02,0x04,0xb2,0x7d]
+0x02,0x04,0xb2,0x7d
+
+# GFX12: v_cmpx_lt_u64_e32 s[104:105], v[2:3]    ; encoding: [0x68,0x04,0xb2,0x7d]
+0x68,0x04,0xb2,0x7d
+
+# GFX12: v_cmpx_lt_u64_e32 vcc, v[2:3]           ; encoding: [0x6a,0x04,0xb2,0x7d]
+0x6a,0x04,0xb2,0x7d
+
+# GFX12: v_cmpx_lt_u64_e32 ttmp[14:15], v[2:3]   ; encoding: [0x7a,0x04,0xb2,0x7d]
+0x7a,0x04,0xb2,0x7d
+
+# GFX12: v_cmpx_lt_u64_e32 exec, v[2:3]          ; encoding: [0x7e,0x04,0xb2,0x7d]
+0x7e,0x04,0xb2,0x7d
+
+# GFX12: v_cmpx_lt_u64_e32 null, v[2:3]          ; encoding: [0x7c,0x04,0xb2,0x7d]
+0x7c,0x04,0xb2,0x7d
+
+# GFX12: v_cmpx_lt_u64_e32 -1, v[2:3]            ; encoding: [0xc1,0x04,0xb2,0x7d]
+0xc1,0x04,0xb2,0x7d
+
+# GFX12: v_cmpx_lt_u64_e32 0.5, v[2:3]           ; encoding: [0xf0,0x04,0xb2,0x7d]
+0xf0,0x04,0xb2,0x7d
+
+# GFX12: v_cmpx_lt_u64_e32 src_scc, v[2:3]       ; encoding: [0xfd,0x04,0xb2,0x7d]
+0xfd,0x04,0xb2,0x7d
+
+# GFX12: v_cmpx_lt_u64_e32 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xb3,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xb3,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ne_i16_e32 v1, v2                ; encoding: [0x01,0x05,0x6a,0x7d]
+0x01,0x05,0x6a,0x7d
+
+# GFX12: v_cmpx_ne_i16_e32 v127, v2              ; encoding: [0x7f,0x05,0x6a,0x7d]
+0x7f,0x05,0x6a,0x7d
+
+# GFX12: v_cmpx_ne_i16_e32 s1, v2                ; encoding: [0x01,0x04,0x6a,0x7d]
+0x01,0x04,0x6a,0x7d
+
+# GFX12: v_cmpx_ne_i16_e32 s105, v2              ; encoding: [0x69,0x04,0x6a,0x7d]
+0x69,0x04,0x6a,0x7d
+
+# GFX12: v_cmpx_ne_i16_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x6a,0x7d]
+0x6a,0x04,0x6a,0x7d
+
+# GFX12: v_cmpx_ne_i16_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x6a,0x7d]
+0x6b,0x04,0x6a,0x7d
+
+# GFX12: v_cmpx_ne_i16_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x6a,0x7d]
+0x7b,0x04,0x6a,0x7d
+
+# GFX12: v_cmpx_ne_i16_e32 m0, v2                ; encoding: [0x7d,0x04,0x6a,0x7d]
+0x7d,0x04,0x6a,0x7d
+
+# GFX12: v_cmpx_ne_i16_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x6a,0x7d]
+0x7e,0x04,0x6a,0x7d
+
+# GFX12: v_cmpx_ne_i16_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x6a,0x7d]
+0x7f,0x04,0x6a,0x7d
+
+# GFX12: v_cmpx_ne_i16_e32 null, v2              ; encoding: [0x7c,0x04,0x6a,0x7d]
+0x7c,0x04,0x6a,0x7d
+
+# GFX12: v_cmpx_ne_i16_e32 -1, v2                ; encoding: [0xc1,0x04,0x6a,0x7d]
+0xc1,0x04,0x6a,0x7d
+
+# GFX12: v_cmpx_ne_i16_e32 0x3800, v2
+0xf0,0x04,0x6a,0x7d
+
+# GFX12: v_cmpx_ne_i16_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x6a,0x7d]
+0xfd,0x04,0x6a,0x7d
+
+# GFX12: v_cmpx_ne_i16_e32 0xfe0b, v127          ; encoding: [0xff,0xfe,0x6a,0x7d,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x6a,0x7d,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ne_i32_e32 v1, v2                ; encoding: [0x01,0x05,0x8a,0x7d]
+0x01,0x05,0x8a,0x7d
+
+# GFX12: v_cmpx_ne_i32_e32 v255, v2              ; encoding: [0xff,0x05,0x8a,0x7d]
+0xff,0x05,0x8a,0x7d
+
+# GFX12: v_cmpx_ne_i32_e32 s1, v2                ; encoding: [0x01,0x04,0x8a,0x7d]
+0x01,0x04,0x8a,0x7d
+
+# GFX12: v_cmpx_ne_i32_e32 s105, v2              ; encoding: [0x69,0x04,0x8a,0x7d]
+0x69,0x04,0x8a,0x7d
+
+# GFX12: v_cmpx_ne_i32_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x8a,0x7d]
+0x6a,0x04,0x8a,0x7d
+
+# GFX12: v_cmpx_ne_i32_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x8a,0x7d]
+0x6b,0x04,0x8a,0x7d
+
+# GFX12: v_cmpx_ne_i32_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x8a,0x7d]
+0x7b,0x04,0x8a,0x7d
+
+# GFX12: v_cmpx_ne_i32_e32 m0, v2                ; encoding: [0x7d,0x04,0x8a,0x7d]
+0x7d,0x04,0x8a,0x7d
+
+# GFX12: v_cmpx_ne_i32_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x8a,0x7d]
+0x7e,0x04,0x8a,0x7d
+
+# GFX12: v_cmpx_ne_i32_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x8a,0x7d]
+0x7f,0x04,0x8a,0x7d
+
+# GFX12: v_cmpx_ne_i32_e32 null, v2              ; encoding: [0x7c,0x04,0x8a,0x7d]
+0x7c,0x04,0x8a,0x7d
+
+# GFX12: v_cmpx_ne_i32_e32 -1, v2                ; encoding: [0xc1,0x04,0x8a,0x7d]
+0xc1,0x04,0x8a,0x7d
+
+# GFX12: v_cmpx_ne_i32_e32 0.5, v2               ; encoding: [0xf0,0x04,0x8a,0x7d]
+0xf0,0x04,0x8a,0x7d
+
+# GFX12: v_cmpx_ne_i32_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x8a,0x7d]
+0xfd,0x04,0x8a,0x7d
+
+# GFX12: v_cmpx_ne_i32_e32 0xaf123456, v255      ; encoding: [0xff,0xfe,0x8b,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x8b,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ne_i64_e32 v[1:2], v[2:3]        ; encoding: [0x01,0x05,0xaa,0x7d]
+0x01,0x05,0xaa,0x7d
+
+# GFX12: v_cmpx_ne_i64_e32 v[254:255], v[2:3]    ; encoding: [0xfe,0x05,0xaa,0x7d]
+0xfe,0x05,0xaa,0x7d
+
+# GFX12: v_cmpx_ne_i64_e32 s[2:3], v[2:3]        ; encoding: [0x02,0x04,0xaa,0x7d]
+0x02,0x04,0xaa,0x7d
+
+# GFX12: v_cmpx_ne_i64_e32 s[104:105], v[2:3]    ; encoding: [0x68,0x04,0xaa,0x7d]
+0x68,0x04,0xaa,0x7d
+
+# GFX12: v_cmpx_ne_i64_e32 vcc, v[2:3]           ; encoding: [0x6a,0x04,0xaa,0x7d]
+0x6a,0x04,0xaa,0x7d
+
+# GFX12: v_cmpx_ne_i64_e32 ttmp[14:15], v[2:3]   ; encoding: [0x7a,0x04,0xaa,0x7d]
+0x7a,0x04,0xaa,0x7d
+
+# GFX12: v_cmpx_ne_i64_e32 exec, v[2:3]          ; encoding: [0x7e,0x04,0xaa,0x7d]
+0x7e,0x04,0xaa,0x7d
+
+# GFX12: v_cmpx_ne_i64_e32 null, v[2:3]          ; encoding: [0x7c,0x04,0xaa,0x7d]
+0x7c,0x04,0xaa,0x7d
+
+# GFX12: v_cmpx_ne_i64_e32 -1, v[2:3]            ; encoding: [0xc1,0x04,0xaa,0x7d]
+0xc1,0x04,0xaa,0x7d
+
+# GFX12: v_cmpx_ne_i64_e32 0.5, v[2:3]           ; encoding: [0xf0,0x04,0xaa,0x7d]
+0xf0,0x04,0xaa,0x7d
+
+# GFX12: v_cmpx_ne_i64_e32 src_scc, v[2:3]       ; encoding: [0xfd,0x04,0xaa,0x7d]
+0xfd,0x04,0xaa,0x7d
+
+# GFX12: v_cmpx_ne_i64_e32 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xab,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xab,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ne_u16_e32 v1, v2                ; encoding: [0x01,0x05,0x7a,0x7d]
+0x01,0x05,0x7a,0x7d
+
+# GFX12: v_cmpx_ne_u16_e32 v127, v2              ; encoding: [0x7f,0x05,0x7a,0x7d]
+0x7f,0x05,0x7a,0x7d
+
+# GFX12: v_cmpx_ne_u16_e32 s1, v2                ; encoding: [0x01,0x04,0x7a,0x7d]
+0x01,0x04,0x7a,0x7d
+
+# GFX12: v_cmpx_ne_u16_e32 s105, v2              ; encoding: [0x69,0x04,0x7a,0x7d]
+0x69,0x04,0x7a,0x7d
+
+# GFX12: v_cmpx_ne_u16_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x7a,0x7d]
+0x6a,0x04,0x7a,0x7d
+
+# GFX12: v_cmpx_ne_u16_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x7a,0x7d]
+0x6b,0x04,0x7a,0x7d
+
+# GFX12: v_cmpx_ne_u16_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x7a,0x7d]
+0x7b,0x04,0x7a,0x7d
+
+# GFX12: v_cmpx_ne_u16_e32 m0, v2                ; encoding: [0x7d,0x04,0x7a,0x7d]
+0x7d,0x04,0x7a,0x7d
+
+# GFX12: v_cmpx_ne_u16_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x7a,0x7d]
+0x7e,0x04,0x7a,0x7d
+
+# GFX12: v_cmpx_ne_u16_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x7a,0x7d]
+0x7f,0x04,0x7a,0x7d
+
+# GFX12: v_cmpx_ne_u16_e32 null, v2              ; encoding: [0x7c,0x04,0x7a,0x7d]
+0x7c,0x04,0x7a,0x7d
+
+# GFX12: v_cmpx_ne_u16_e32 -1, v2                ; encoding: [0xc1,0x04,0x7a,0x7d]
+0xc1,0x04,0x7a,0x7d
+
+# GFX12: v_cmpx_ne_u16_e32 0x3800, v2
+0xf0,0x04,0x7a,0x7d
+
+# GFX12: v_cmpx_ne_u16_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x7a,0x7d]
+0xfd,0x04,0x7a,0x7d
+
+# GFX12: v_cmpx_ne_u16_e32 0xfe0b, v127          ; encoding: [0xff,0xfe,0x7a,0x7d,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x7a,0x7d,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ne_u32_e32 v1, v2                ; encoding: [0x01,0x05,0x9a,0x7d]
+0x01,0x05,0x9a,0x7d
+
+# GFX12: v_cmpx_ne_u32_e32 v255, v2              ; encoding: [0xff,0x05,0x9a,0x7d]
+0xff,0x05,0x9a,0x7d
+
+# GFX12: v_cmpx_ne_u32_e32 s1, v2                ; encoding: [0x01,0x04,0x9a,0x7d]
+0x01,0x04,0x9a,0x7d
+
+# GFX12: v_cmpx_ne_u32_e32 s105, v2              ; encoding: [0x69,0x04,0x9a,0x7d]
+0x69,0x04,0x9a,0x7d
+
+# GFX12: v_cmpx_ne_u32_e32 vcc_lo, v2            ; encoding: [0x6a,0x04,0x9a,0x7d]
+0x6a,0x04,0x9a,0x7d
+
+# GFX12: v_cmpx_ne_u32_e32 vcc_hi, v2            ; encoding: [0x6b,0x04,0x9a,0x7d]
+0x6b,0x04,0x9a,0x7d
+
+# GFX12: v_cmpx_ne_u32_e32 ttmp15, v2            ; encoding: [0x7b,0x04,0x9a,0x7d]
+0x7b,0x04,0x9a,0x7d
+
+# GFX12: v_cmpx_ne_u32_e32 m0, v2                ; encoding: [0x7d,0x04,0x9a,0x7d]
+0x7d,0x04,0x9a,0x7d
+
+# GFX12: v_cmpx_ne_u32_e32 exec_lo, v2           ; encoding: [0x7e,0x04,0x9a,0x7d]
+0x7e,0x04,0x9a,0x7d
+
+# GFX12: v_cmpx_ne_u32_e32 exec_hi, v2           ; encoding: [0x7f,0x04,0x9a,0x7d]
+0x7f,0x04,0x9a,0x7d
+
+# GFX12: v_cmpx_ne_u32_e32 null, v2              ; encoding: [0x7c,0x04,0x9a,0x7d]
+0x7c,0x04,0x9a,0x7d
+
+# GFX12: v_cmpx_ne_u32_e32 -1, v2                ; encoding: [0xc1,0x04,0x9a,0x7d]
+0xc1,0x04,0x9a,0x7d
+
+# GFX12: v_cmpx_ne_u32_e32 0.5, v2               ; encoding: [0xf0,0x04,0x9a,0x7d]
+0xf0,0x04,0x9a,0x7d
+
+# GFX12: v_cmpx_ne_u32_e32 src_scc, v2           ; encoding: [0xfd,0x04,0x9a,0x7d]
+0xfd,0x04,0x9a,0x7d
+
+# GFX12: v_cmpx_ne_u32_e32 0xaf123456, v255      ; encoding: [0xff,0xfe,0x9b,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x9b,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ne_u64_e32 v[1:2], v[2:3]        ; encoding: [0x01,0x05,0xba,0x7d]
+0x01,0x05,0xba,0x7d
+
+# GFX12: v_cmpx_ne_u64_e32 v[254:255], v[2:3]    ; encoding: [0xfe,0x05,0xba,0x7d]
+0xfe,0x05,0xba,0x7d
+
+# GFX12: v_cmpx_ne_u64_e32 s[2:3], v[2:3]        ; encoding: [0x02,0x04,0xba,0x7d]
+0x02,0x04,0xba,0x7d
+
+# GFX12: v_cmpx_ne_u64_e32 s[104:105], v[2:3]    ; encoding: [0x68,0x04,0xba,0x7d]
+0x68,0x04,0xba,0x7d
+
+# GFX12: v_cmpx_ne_u64_e32 vcc, v[2:3]           ; encoding: [0x6a,0x04,0xba,0x7d]
+0x6a,0x04,0xba,0x7d
+
+# GFX12: v_cmpx_ne_u64_e32 ttmp[14:15], v[2:3]   ; encoding: [0x7a,0x04,0xba,0x7d]
+0x7a,0x04,0xba,0x7d
+
+# GFX12: v_cmpx_ne_u64_e32 exec, v[2:3]          ; encoding: [0x7e,0x04,0xba,0x7d]
+0x7e,0x04,0xba,0x7d
+
+# GFX12: v_cmpx_ne_u64_e32 null, v[2:3]          ; encoding: [0x7c,0x04,0xba,0x7d]
+0x7c,0x04,0xba,0x7d
+
+# GFX12: v_cmpx_ne_u64_e32 -1, v[2:3]            ; encoding: [0xc1,0x04,0xba,0x7d]
+0xc1,0x04,0xba,0x7d
+
+# GFX12: v_cmpx_ne_u64_e32 0.5, v[2:3]           ; encoding: [0xf0,0x04,0xba,0x7d]
+0xf0,0x04,0xba,0x7d
+
+# GFX12: v_cmpx_ne_u64_e32 src_scc, v[2:3]       ; encoding: [0xfd,0x04,0xba,0x7d]
+0xfd,0x04,0xba,0x7d
+
+# GFX12: v_cmpx_ne_u64_e32 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xbb,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0xbb,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_neq_f16_e32 v1, v2               ; encoding: [0x01,0x05,0x1a,0x7d]
+0x01,0x05,0x1a,0x7d
+
+# GFX12: v_cmpx_neq_f16_e32 v127, v2             ; encoding: [0x7f,0x05,0x1a,0x7d]
+0x7f,0x05,0x1a,0x7d
+
+# GFX12: v_cmpx_neq_f16_e32 s1, v2               ; encoding: [0x01,0x04,0x1a,0x7d]
+0x01,0x04,0x1a,0x7d
+
+# GFX12: v_cmpx_neq_f16_e32 s105, v2             ; encoding: [0x69,0x04,0x1a,0x7d]
+0x69,0x04,0x1a,0x7d
+
+# GFX12: v_cmpx_neq_f16_e32 vcc_lo, v2           ; encoding: [0x6a,0x04,0x1a,0x7d]
+0x6a,0x04,0x1a,0x7d
+
+# GFX12: v_cmpx_neq_f16_e32 vcc_hi, v2           ; encoding: [0x6b,0x04,0x1a,0x7d]
+0x6b,0x04,0x1a,0x7d
+
+# GFX12: v_cmpx_neq_f16_e32 ttmp15, v2           ; encoding: [0x7b,0x04,0x1a,0x7d]
+0x7b,0x04,0x1a,0x7d
+
+# GFX12: v_cmpx_neq_f16_e32 m0, v2               ; encoding: [0x7d,0x04,0x1a,0x7d]
+0x7d,0x04,0x1a,0x7d
+
+# GFX12: v_cmpx_neq_f16_e32 exec_lo, v2          ; encoding: [0x7e,0x04,0x1a,0x7d]
+0x7e,0x04,0x1a,0x7d
+
+# GFX12: v_cmpx_neq_f16_e32 exec_hi, v2          ; encoding: [0x7f,0x04,0x1a,0x7d]
+0x7f,0x04,0x1a,0x7d
+
+# GFX12: v_cmpx_neq_f16_e32 null, v2             ; encoding: [0x7c,0x04,0x1a,0x7d]
+0x7c,0x04,0x1a,0x7d
+
+# GFX12: v_cmpx_neq_f16_e32 -1, v2               ; encoding: [0xc1,0x04,0x1a,0x7d]
+0xc1,0x04,0x1a,0x7d
+
+# GFX12: v_cmpx_neq_f16_e32 0.5, v2              ; encoding: [0xf0,0x04,0x1a,0x7d]
+0xf0,0x04,0x1a,0x7d
+
+# GFX12: v_cmpx_neq_f16_e32 src_scc, v2          ; encoding: [0xfd,0x04,0x1a,0x7d]
+0xfd,0x04,0x1a,0x7d
+
+# GFX12: v_cmpx_neq_f16_e32 0xfe0b, v127         ; encoding: [0xff,0xfe,0x1a,0x7d,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x1a,0x7d,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_neq_f32_e32 v1, v2               ; encoding: [0x01,0x05,0x3a,0x7d]
+0x01,0x05,0x3a,0x7d
+
+# GFX12: v_cmpx_neq_f32_e32 v255, v2             ; encoding: [0xff,0x05,0x3a,0x7d]
+0xff,0x05,0x3a,0x7d
+
+# GFX12: v_cmpx_neq_f32_e32 s1, v2               ; encoding: [0x01,0x04,0x3a,0x7d]
+0x01,0x04,0x3a,0x7d
+
+# GFX12: v_cmpx_neq_f32_e32 s105, v2             ; encoding: [0x69,0x04,0x3a,0x7d]
+0x69,0x04,0x3a,0x7d
+
+# GFX12: v_cmpx_neq_f32_e32 vcc_lo, v2           ; encoding: [0x6a,0x04,0x3a,0x7d]
+0x6a,0x04,0x3a,0x7d
+
+# GFX12: v_cmpx_neq_f32_e32 vcc_hi, v2           ; encoding: [0x6b,0x04,0x3a,0x7d]
+0x6b,0x04,0x3a,0x7d
+
+# GFX12: v_cmpx_neq_f32_e32 ttmp15, v2           ; encoding: [0x7b,0x04,0x3a,0x7d]
+0x7b,0x04,0x3a,0x7d
+
+# GFX12: v_cmpx_neq_f32_e32 m0, v2               ; encoding: [0x7d,0x04,0x3a,0x7d]
+0x7d,0x04,0x3a,0x7d
+
+# GFX12: v_cmpx_neq_f32_e32 exec_lo, v2          ; encoding: [0x7e,0x04,0x3a,0x7d]
+0x7e,0x04,0x3a,0x7d
+
+# GFX12: v_cmpx_neq_f32_e32 exec_hi, v2          ; encoding: [0x7f,0x04,0x3a,0x7d]
+0x7f,0x04,0x3a,0x7d
+
+# GFX12: v_cmpx_neq_f32_e32 null, v2             ; encoding: [0x7c,0x04,0x3a,0x7d]
+0x7c,0x04,0x3a,0x7d
+
+# GFX12: v_cmpx_neq_f32_e32 -1, v2               ; encoding: [0xc1,0x04,0x3a,0x7d]
+0xc1,0x04,0x3a,0x7d
+
+# GFX12: v_cmpx_neq_f32_e32 0.5, v2              ; encoding: [0xf0,0x04,0x3a,0x7d]
+0xf0,0x04,0x3a,0x7d
+
+# GFX12: v_cmpx_neq_f32_e32 src_scc, v2          ; encoding: [0xfd,0x04,0x3a,0x7d]
+0xfd,0x04,0x3a,0x7d
+
+# GFX12: v_cmpx_neq_f32_e32 0xaf123456, v255     ; encoding: [0xff,0xfe,0x3b,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x3b,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_neq_f64_e32 v[1:2], v[2:3]       ; encoding: [0x01,0x05,0x5a,0x7d]
+0x01,0x05,0x5a,0x7d
+
+# GFX12: v_cmpx_neq_f64_e32 v[254:255], v[2:3]   ; encoding: [0xfe,0x05,0x5a,0x7d]
+0xfe,0x05,0x5a,0x7d
+
+# GFX12: v_cmpx_neq_f64_e32 s[2:3], v[2:3]       ; encoding: [0x02,0x04,0x5a,0x7d]
+0x02,0x04,0x5a,0x7d
+
+# GFX12: v_cmpx_neq_f64_e32 s[104:105], v[2:3]   ; encoding: [0x68,0x04,0x5a,0x7d]
+0x68,0x04,0x5a,0x7d
+
+# GFX12: v_cmpx_neq_f64_e32 vcc, v[2:3]          ; encoding: [0x6a,0x04,0x5a,0x7d]
+0x6a,0x04,0x5a,0x7d
+
+# GFX12: v_cmpx_neq_f64_e32 ttmp[14:15], v[2:3]  ; encoding: [0x7a,0x04,0x5a,0x7d]
+0x7a,0x04,0x5a,0x7d
+
+# GFX12: v_cmpx_neq_f64_e32 exec, v[2:3]         ; encoding: [0x7e,0x04,0x5a,0x7d]
+0x7e,0x04,0x5a,0x7d
+
+# GFX12: v_cmpx_neq_f64_e32 null, v[2:3]         ; encoding: [0x7c,0x04,0x5a,0x7d]
+0x7c,0x04,0x5a,0x7d
+
+# GFX12: v_cmpx_neq_f64_e32 -1, v[2:3]           ; encoding: [0xc1,0x04,0x5a,0x7d]
+0xc1,0x04,0x5a,0x7d
+
+# GFX12: v_cmpx_neq_f64_e32 0.5, v[2:3]          ; encoding: [0xf0,0x04,0x5a,0x7d]
+0xf0,0x04,0x5a,0x7d
+
+# GFX12: v_cmpx_neq_f64_e32 src_scc, v[2:3]      ; encoding: [0xfd,0x04,0x5a,0x7d]
+0xfd,0x04,0x5a,0x7d
+
+# GFX12: v_cmpx_neq_f64_e32 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x5b,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x5b,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_nge_f16_e32 v1, v2               ; encoding: [0x01,0x05,0x12,0x7d]
+0x01,0x05,0x12,0x7d
+
+# GFX12: v_cmpx_nge_f16_e32 v127, v2             ; encoding: [0x7f,0x05,0x12,0x7d]
+0x7f,0x05,0x12,0x7d
+
+# GFX12: v_cmpx_nge_f16_e32 s1, v2               ; encoding: [0x01,0x04,0x12,0x7d]
+0x01,0x04,0x12,0x7d
+
+# GFX12: v_cmpx_nge_f16_e32 s105, v2             ; encoding: [0x69,0x04,0x12,0x7d]
+0x69,0x04,0x12,0x7d
+
+# GFX12: v_cmpx_nge_f16_e32 vcc_lo, v2           ; encoding: [0x6a,0x04,0x12,0x7d]
+0x6a,0x04,0x12,0x7d
+
+# GFX12: v_cmpx_nge_f16_e32 vcc_hi, v2           ; encoding: [0x6b,0x04,0x12,0x7d]
+0x6b,0x04,0x12,0x7d
+
+# GFX12: v_cmpx_nge_f16_e32 ttmp15, v2           ; encoding: [0x7b,0x04,0x12,0x7d]
+0x7b,0x04,0x12,0x7d
+
+# GFX12: v_cmpx_nge_f16_e32 m0, v2               ; encoding: [0x7d,0x04,0x12,0x7d]
+0x7d,0x04,0x12,0x7d
+
+# GFX12: v_cmpx_nge_f16_e32 exec_lo, v2          ; encoding: [0x7e,0x04,0x12,0x7d]
+0x7e,0x04,0x12,0x7d
+
+# GFX12: v_cmpx_nge_f16_e32 exec_hi, v2          ; encoding: [0x7f,0x04,0x12,0x7d]
+0x7f,0x04,0x12,0x7d
+
+# GFX12: v_cmpx_nge_f16_e32 null, v2             ; encoding: [0x7c,0x04,0x12,0x7d]
+0x7c,0x04,0x12,0x7d
+
+# GFX12: v_cmpx_nge_f16_e32 -1, v2               ; encoding: [0xc1,0x04,0x12,0x7d]
+0xc1,0x04,0x12,0x7d
+
+# GFX12: v_cmpx_nge_f16_e32 0.5, v2              ; encoding: [0xf0,0x04,0x12,0x7d]
+0xf0,0x04,0x12,0x7d
+
+# GFX12: v_cmpx_nge_f16_e32 src_scc, v2          ; encoding: [0xfd,0x04,0x12,0x7d]
+0xfd,0x04,0x12,0x7d
+
+# GFX12: v_cmpx_nge_f16_e32 0xfe0b, v127         ; encoding: [0xff,0xfe,0x12,0x7d,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x12,0x7d,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_nge_f32_e32 v1, v2               ; encoding: [0x01,0x05,0x32,0x7d]
+0x01,0x05,0x32,0x7d
+
+# GFX12: v_cmpx_nge_f32_e32 v255, v2             ; encoding: [0xff,0x05,0x32,0x7d]
+0xff,0x05,0x32,0x7d
+
+# GFX12: v_cmpx_nge_f32_e32 s1, v2               ; encoding: [0x01,0x04,0x32,0x7d]
+0x01,0x04,0x32,0x7d
+
+# GFX12: v_cmpx_nge_f32_e32 s105, v2             ; encoding: [0x69,0x04,0x32,0x7d]
+0x69,0x04,0x32,0x7d
+
+# GFX12: v_cmpx_nge_f32_e32 vcc_lo, v2           ; encoding: [0x6a,0x04,0x32,0x7d]
+0x6a,0x04,0x32,0x7d
+
+# GFX12: v_cmpx_nge_f32_e32 vcc_hi, v2           ; encoding: [0x6b,0x04,0x32,0x7d]
+0x6b,0x04,0x32,0x7d
+
+# GFX12: v_cmpx_nge_f32_e32 ttmp15, v2           ; encoding: [0x7b,0x04,0x32,0x7d]
+0x7b,0x04,0x32,0x7d
+
+# GFX12: v_cmpx_nge_f32_e32 m0, v2               ; encoding: [0x7d,0x04,0x32,0x7d]
+0x7d,0x04,0x32,0x7d
+
+# GFX12: v_cmpx_nge_f32_e32 exec_lo, v2          ; encoding: [0x7e,0x04,0x32,0x7d]
+0x7e,0x04,0x32,0x7d
+
+# GFX12: v_cmpx_nge_f32_e32 exec_hi, v2          ; encoding: [0x7f,0x04,0x32,0x7d]
+0x7f,0x04,0x32,0x7d
+
+# GFX12: v_cmpx_nge_f32_e32 null, v2             ; encoding: [0x7c,0x04,0x32,0x7d]
+0x7c,0x04,0x32,0x7d
+
+# GFX12: v_cmpx_nge_f32_e32 -1, v2               ; encoding: [0xc1,0x04,0x32,0x7d]
+0xc1,0x04,0x32,0x7d
+
+# GFX12: v_cmpx_nge_f32_e32 0.5, v2              ; encoding: [0xf0,0x04,0x32,0x7d]
+0xf0,0x04,0x32,0x7d
+
+# GFX12: v_cmpx_nge_f32_e32 src_scc, v2          ; encoding: [0xfd,0x04,0x32,0x7d]
+0xfd,0x04,0x32,0x7d
+
+# GFX12: v_cmpx_nge_f32_e32 0xaf123456, v255     ; encoding: [0xff,0xfe,0x33,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x33,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_nge_f64_e32 v[1:2], v[2:3]       ; encoding: [0x01,0x05,0x52,0x7d]
+0x01,0x05,0x52,0x7d
+
+# GFX12: v_cmpx_nge_f64_e32 v[254:255], v[2:3]   ; encoding: [0xfe,0x05,0x52,0x7d]
+0xfe,0x05,0x52,0x7d
+
+# GFX12: v_cmpx_nge_f64_e32 s[2:3], v[2:3]       ; encoding: [0x02,0x04,0x52,0x7d]
+0x02,0x04,0x52,0x7d
+
+# GFX12: v_cmpx_nge_f64_e32 s[104:105], v[2:3]   ; encoding: [0x68,0x04,0x52,0x7d]
+0x68,0x04,0x52,0x7d
+
+# GFX12: v_cmpx_nge_f64_e32 vcc, v[2:3]          ; encoding: [0x6a,0x04,0x52,0x7d]
+0x6a,0x04,0x52,0x7d
+
+# GFX12: v_cmpx_nge_f64_e32 ttmp[14:15], v[2:3]  ; encoding: [0x7a,0x04,0x52,0x7d]
+0x7a,0x04,0x52,0x7d
+
+# GFX12: v_cmpx_nge_f64_e32 exec, v[2:3]         ; encoding: [0x7e,0x04,0x52,0x7d]
+0x7e,0x04,0x52,0x7d
+
+# GFX12: v_cmpx_nge_f64_e32 null, v[2:3]         ; encoding: [0x7c,0x04,0x52,0x7d]
+0x7c,0x04,0x52,0x7d
+
+# GFX12: v_cmpx_nge_f64_e32 -1, v[2:3]           ; encoding: [0xc1,0x04,0x52,0x7d]
+0xc1,0x04,0x52,0x7d
+
+# GFX12: v_cmpx_nge_f64_e32 0.5, v[2:3]          ; encoding: [0xf0,0x04,0x52,0x7d]
+0xf0,0x04,0x52,0x7d
+
+# GFX12: v_cmpx_nge_f64_e32 src_scc, v[2:3]      ; encoding: [0xfd,0x04,0x52,0x7d]
+0xfd,0x04,0x52,0x7d
+
+# GFX12: v_cmpx_nge_f64_e32 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x53,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x53,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ngt_f16_e32 v1, v2               ; encoding: [0x01,0x05,0x16,0x7d]
+0x01,0x05,0x16,0x7d
+
+# GFX12: v_cmpx_ngt_f16_e32 v127, v2             ; encoding: [0x7f,0x05,0x16,0x7d]
+0x7f,0x05,0x16,0x7d
+
+# GFX12: v_cmpx_ngt_f16_e32 s1, v2               ; encoding: [0x01,0x04,0x16,0x7d]
+0x01,0x04,0x16,0x7d
+
+# GFX12: v_cmpx_ngt_f16_e32 s105, v2             ; encoding: [0x69,0x04,0x16,0x7d]
+0x69,0x04,0x16,0x7d
+
+# GFX12: v_cmpx_ngt_f16_e32 vcc_lo, v2           ; encoding: [0x6a,0x04,0x16,0x7d]
+0x6a,0x04,0x16,0x7d
+
+# GFX12: v_cmpx_ngt_f16_e32 vcc_hi, v2           ; encoding: [0x6b,0x04,0x16,0x7d]
+0x6b,0x04,0x16,0x7d
+
+# GFX12: v_cmpx_ngt_f16_e32 ttmp15, v2           ; encoding: [0x7b,0x04,0x16,0x7d]
+0x7b,0x04,0x16,0x7d
+
+# GFX12: v_cmpx_ngt_f16_e32 m0, v2               ; encoding: [0x7d,0x04,0x16,0x7d]
+0x7d,0x04,0x16,0x7d
+
+# GFX12: v_cmpx_ngt_f16_e32 exec_lo, v2          ; encoding: [0x7e,0x04,0x16,0x7d]
+0x7e,0x04,0x16,0x7d
+
+# GFX12: v_cmpx_ngt_f16_e32 exec_hi, v2          ; encoding: [0x7f,0x04,0x16,0x7d]
+0x7f,0x04,0x16,0x7d
+
+# GFX12: v_cmpx_ngt_f16_e32 null, v2             ; encoding: [0x7c,0x04,0x16,0x7d]
+0x7c,0x04,0x16,0x7d
+
+# GFX12: v_cmpx_ngt_f16_e32 -1, v2               ; encoding: [0xc1,0x04,0x16,0x7d]
+0xc1,0x04,0x16,0x7d
+
+# GFX12: v_cmpx_ngt_f16_e32 0.5, v2              ; encoding: [0xf0,0x04,0x16,0x7d]
+0xf0,0x04,0x16,0x7d
+
+# GFX12: v_cmpx_ngt_f16_e32 src_scc, v2          ; encoding: [0xfd,0x04,0x16,0x7d]
+0xfd,0x04,0x16,0x7d
+
+# GFX12: v_cmpx_ngt_f16_e32 0xfe0b, v127         ; encoding: [0xff,0xfe,0x16,0x7d,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x16,0x7d,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_ngt_f32_e32 v1, v2               ; encoding: [0x01,0x05,0x36,0x7d]
+0x01,0x05,0x36,0x7d
+
+# GFX12: v_cmpx_ngt_f32_e32 v255, v2             ; encoding: [0xff,0x05,0x36,0x7d]
+0xff,0x05,0x36,0x7d
+
+# GFX12: v_cmpx_ngt_f32_e32 s1, v2               ; encoding: [0x01,0x04,0x36,0x7d]
+0x01,0x04,0x36,0x7d
+
+# GFX12: v_cmpx_ngt_f32_e32 s105, v2             ; encoding: [0x69,0x04,0x36,0x7d]
+0x69,0x04,0x36,0x7d
+
+# GFX12: v_cmpx_ngt_f32_e32 vcc_lo, v2           ; encoding: [0x6a,0x04,0x36,0x7d]
+0x6a,0x04,0x36,0x7d
+
+# GFX12: v_cmpx_ngt_f32_e32 vcc_hi, v2           ; encoding: [0x6b,0x04,0x36,0x7d]
+0x6b,0x04,0x36,0x7d
+
+# GFX12: v_cmpx_ngt_f32_e32 ttmp15, v2           ; encoding: [0x7b,0x04,0x36,0x7d]
+0x7b,0x04,0x36,0x7d
+
+# GFX12: v_cmpx_ngt_f32_e32 m0, v2               ; encoding: [0x7d,0x04,0x36,0x7d]
+0x7d,0x04,0x36,0x7d
+
+# GFX12: v_cmpx_ngt_f32_e32 exec_lo, v2          ; encoding: [0x7e,0x04,0x36,0x7d]
+0x7e,0x04,0x36,0x7d
+
+# GFX12: v_cmpx_ngt_f32_e32 exec_hi, v2          ; encoding: [0x7f,0x04,0x36,0x7d]
+0x7f,0x04,0x36,0x7d
+
+# GFX12: v_cmpx_ngt_f32_e32 null, v2             ; encoding: [0x7c,0x04,0x36,0x7d]
+0x7c,0x04,0x36,0x7d
+
+# GFX12: v_cmpx_ngt_f32_e32 -1, v2               ; encoding: [0xc1,0x04,0x36,0x7d]
+0xc1,0x04,0x36,0x7d
+
+# GFX12: v_cmpx_ngt_f32_e32 0.5, v2              ; encoding: [0xf0,0x04,0x36,0x7d]
+0xf0,0x04,0x36,0x7d
+
+# GFX12: v_cmpx_ngt_f32_e32 src_scc, v2          ; encoding: [0xfd,0x04,0x36,0x7d]
+0xfd,0x04,0x36,0x7d
+
+# GFX12: v_cmpx_ngt_f32_e32 0xaf123456, v255     ; encoding: [0xff,0xfe,0x37,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x37,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_ngt_f64_e32 v[1:2], v[2:3]       ; encoding: [0x01,0x05,0x56,0x7d]
+0x01,0x05,0x56,0x7d
+
+# GFX12: v_cmpx_ngt_f64_e32 v[254:255], v[2:3]   ; encoding: [0xfe,0x05,0x56,0x7d]
+0xfe,0x05,0x56,0x7d
+
+# GFX12: v_cmpx_ngt_f64_e32 s[2:3], v[2:3]       ; encoding: [0x02,0x04,0x56,0x7d]
+0x02,0x04,0x56,0x7d
+
+# GFX12: v_cmpx_ngt_f64_e32 s[104:105], v[2:3]   ; encoding: [0x68,0x04,0x56,0x7d]
+0x68,0x04,0x56,0x7d
+
+# GFX12: v_cmpx_ngt_f64_e32 vcc, v[2:3]          ; encoding: [0x6a,0x04,0x56,0x7d]
+0x6a,0x04,0x56,0x7d
+
+# GFX12: v_cmpx_ngt_f64_e32 ttmp[14:15], v[2:3]  ; encoding: [0x7a,0x04,0x56,0x7d]
+0x7a,0x04,0x56,0x7d
+
+# GFX12: v_cmpx_ngt_f64_e32 exec, v[2:3]         ; encoding: [0x7e,0x04,0x56,0x7d]
+0x7e,0x04,0x56,0x7d
+
+# GFX12: v_cmpx_ngt_f64_e32 null, v[2:3]         ; encoding: [0x7c,0x04,0x56,0x7d]
+0x7c,0x04,0x56,0x7d
+
+# GFX12: v_cmpx_ngt_f64_e32 -1, v[2:3]           ; encoding: [0xc1,0x04,0x56,0x7d]
+0xc1,0x04,0x56,0x7d
+
+# GFX12: v_cmpx_ngt_f64_e32 0.5, v[2:3]          ; encoding: [0xf0,0x04,0x56,0x7d]
+0xf0,0x04,0x56,0x7d
+
+# GFX12: v_cmpx_ngt_f64_e32 src_scc, v[2:3]      ; encoding: [0xfd,0x04,0x56,0x7d]
+0xfd,0x04,0x56,0x7d
+
+# GFX12: v_cmpx_ngt_f64_e32 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x57,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x57,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_nle_f16_e32 v1, v2               ; encoding: [0x01,0x05,0x18,0x7d]
+0x01,0x05,0x18,0x7d
+
+# GFX12: v_cmpx_nle_f16_e32 v127, v2             ; encoding: [0x7f,0x05,0x18,0x7d]
+0x7f,0x05,0x18,0x7d
+
+# GFX12: v_cmpx_nle_f16_e32 s1, v2               ; encoding: [0x01,0x04,0x18,0x7d]
+0x01,0x04,0x18,0x7d
+
+# GFX12: v_cmpx_nle_f16_e32 s105, v2             ; encoding: [0x69,0x04,0x18,0x7d]
+0x69,0x04,0x18,0x7d
+
+# GFX12: v_cmpx_nle_f16_e32 vcc_lo, v2           ; encoding: [0x6a,0x04,0x18,0x7d]
+0x6a,0x04,0x18,0x7d
+
+# GFX12: v_cmpx_nle_f16_e32 vcc_hi, v2           ; encoding: [0x6b,0x04,0x18,0x7d]
+0x6b,0x04,0x18,0x7d
+
+# GFX12: v_cmpx_nle_f16_e32 ttmp15, v2           ; encoding: [0x7b,0x04,0x18,0x7d]
+0x7b,0x04,0x18,0x7d
+
+# GFX12: v_cmpx_nle_f16_e32 m0, v2               ; encoding: [0x7d,0x04,0x18,0x7d]
+0x7d,0x04,0x18,0x7d
+
+# GFX12: v_cmpx_nle_f16_e32 exec_lo, v2          ; encoding: [0x7e,0x04,0x18,0x7d]
+0x7e,0x04,0x18,0x7d
+
+# GFX12: v_cmpx_nle_f16_e32 exec_hi, v2          ; encoding: [0x7f,0x04,0x18,0x7d]
+0x7f,0x04,0x18,0x7d
+
+# GFX12: v_cmpx_nle_f16_e32 null, v2             ; encoding: [0x7c,0x04,0x18,0x7d]
+0x7c,0x04,0x18,0x7d
+
+# GFX12: v_cmpx_nle_f16_e32 -1, v2               ; encoding: [0xc1,0x04,0x18,0x7d]
+0xc1,0x04,0x18,0x7d
+
+# GFX12: v_cmpx_nle_f16_e32 0.5, v2              ; encoding: [0xf0,0x04,0x18,0x7d]
+0xf0,0x04,0x18,0x7d
+
+# GFX12: v_cmpx_nle_f16_e32 src_scc, v2          ; encoding: [0xfd,0x04,0x18,0x7d]
+0xfd,0x04,0x18,0x7d
+
+# GFX12: v_cmpx_nle_f16_e32 0xfe0b, v127         ; encoding: [0xff,0xfe,0x18,0x7d,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x18,0x7d,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_nle_f32_e32 v1, v2               ; encoding: [0x01,0x05,0x38,0x7d]
+0x01,0x05,0x38,0x7d
+
+# GFX12: v_cmpx_nle_f32_e32 v255, v2             ; encoding: [0xff,0x05,0x38,0x7d]
+0xff,0x05,0x38,0x7d
+
+# GFX12: v_cmpx_nle_f32_e32 s1, v2               ; encoding: [0x01,0x04,0x38,0x7d]
+0x01,0x04,0x38,0x7d
+
+# GFX12: v_cmpx_nle_f32_e32 s105, v2             ; encoding: [0x69,0x04,0x38,0x7d]
+0x69,0x04,0x38,0x7d
+
+# GFX12: v_cmpx_nle_f32_e32 vcc_lo, v2           ; encoding: [0x6a,0x04,0x38,0x7d]
+0x6a,0x04,0x38,0x7d
+
+# GFX12: v_cmpx_nle_f32_e32 vcc_hi, v2           ; encoding: [0x6b,0x04,0x38,0x7d]
+0x6b,0x04,0x38,0x7d
+
+# GFX12: v_cmpx_nle_f32_e32 ttmp15, v2           ; encoding: [0x7b,0x04,0x38,0x7d]
+0x7b,0x04,0x38,0x7d
+
+# GFX12: v_cmpx_nle_f32_e32 m0, v2               ; encoding: [0x7d,0x04,0x38,0x7d]
+0x7d,0x04,0x38,0x7d
+
+# GFX12: v_cmpx_nle_f32_e32 exec_lo, v2          ; encoding: [0x7e,0x04,0x38,0x7d]
+0x7e,0x04,0x38,0x7d
+
+# GFX12: v_cmpx_nle_f32_e32 exec_hi, v2          ; encoding: [0x7f,0x04,0x38,0x7d]
+0x7f,0x04,0x38,0x7d
+
+# GFX12: v_cmpx_nle_f32_e32 null, v2             ; encoding: [0x7c,0x04,0x38,0x7d]
+0x7c,0x04,0x38,0x7d
+
+# GFX12: v_cmpx_nle_f32_e32 -1, v2               ; encoding: [0xc1,0x04,0x38,0x7d]
+0xc1,0x04,0x38,0x7d
+
+# GFX12: v_cmpx_nle_f32_e32 0.5, v2              ; encoding: [0xf0,0x04,0x38,0x7d]
+0xf0,0x04,0x38,0x7d
+
+# GFX12: v_cmpx_nle_f32_e32 src_scc, v2          ; encoding: [0xfd,0x04,0x38,0x7d]
+0xfd,0x04,0x38,0x7d
+
+# GFX12: v_cmpx_nle_f32_e32 0xaf123456, v255     ; encoding: [0xff,0xfe,0x39,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x39,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_nle_f64_e32 v[1:2], v[2:3]       ; encoding: [0x01,0x05,0x58,0x7d]
+0x01,0x05,0x58,0x7d
+
+# GFX12: v_cmpx_nle_f64_e32 v[254:255], v[2:3]   ; encoding: [0xfe,0x05,0x58,0x7d]
+0xfe,0x05,0x58,0x7d
+
+# GFX12: v_cmpx_nle_f64_e32 s[2:3], v[2:3]       ; encoding: [0x02,0x04,0x58,0x7d]
+0x02,0x04,0x58,0x7d
+
+# GFX12: v_cmpx_nle_f64_e32 s[104:105], v[2:3]   ; encoding: [0x68,0x04,0x58,0x7d]
+0x68,0x04,0x58,0x7d
+
+# GFX12: v_cmpx_nle_f64_e32 vcc, v[2:3]          ; encoding: [0x6a,0x04,0x58,0x7d]
+0x6a,0x04,0x58,0x7d
+
+# GFX12: v_cmpx_nle_f64_e32 ttmp[14:15], v[2:3]  ; encoding: [0x7a,0x04,0x58,0x7d]
+0x7a,0x04,0x58,0x7d
+
+# GFX12: v_cmpx_nle_f64_e32 exec, v[2:3]         ; encoding: [0x7e,0x04,0x58,0x7d]
+0x7e,0x04,0x58,0x7d
+
+# GFX12: v_cmpx_nle_f64_e32 null, v[2:3]         ; encoding: [0x7c,0x04,0x58,0x7d]
+0x7c,0x04,0x58,0x7d
+
+# GFX12: v_cmpx_nle_f64_e32 -1, v[2:3]           ; encoding: [0xc1,0x04,0x58,0x7d]
+0xc1,0x04,0x58,0x7d
+
+# GFX12: v_cmpx_nle_f64_e32 0.5, v[2:3]          ; encoding: [0xf0,0x04,0x58,0x7d]
+0xf0,0x04,0x58,0x7d
+
+# GFX12: v_cmpx_nle_f64_e32 src_scc, v[2:3]      ; encoding: [0xfd,0x04,0x58,0x7d]
+0xfd,0x04,0x58,0x7d
+
+# GFX12: v_cmpx_nle_f64_e32 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x59,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x59,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_nlg_f16_e32 v1, v2               ; encoding: [0x01,0x05,0x14,0x7d]
+0x01,0x05,0x14,0x7d
+
+# GFX12: v_cmpx_nlg_f16_e32 v127, v2             ; encoding: [0x7f,0x05,0x14,0x7d]
+0x7f,0x05,0x14,0x7d
+
+# GFX12: v_cmpx_nlg_f16_e32 s1, v2               ; encoding: [0x01,0x04,0x14,0x7d]
+0x01,0x04,0x14,0x7d
+
+# GFX12: v_cmpx_nlg_f16_e32 s105, v2             ; encoding: [0x69,0x04,0x14,0x7d]
+0x69,0x04,0x14,0x7d
+
+# GFX12: v_cmpx_nlg_f16_e32 vcc_lo, v2           ; encoding: [0x6a,0x04,0x14,0x7d]
+0x6a,0x04,0x14,0x7d
+
+# GFX12: v_cmpx_nlg_f16_e32 vcc_hi, v2           ; encoding: [0x6b,0x04,0x14,0x7d]
+0x6b,0x04,0x14,0x7d
+
+# GFX12: v_cmpx_nlg_f16_e32 ttmp15, v2           ; encoding: [0x7b,0x04,0x14,0x7d]
+0x7b,0x04,0x14,0x7d
+
+# GFX12: v_cmpx_nlg_f16_e32 m0, v2               ; encoding: [0x7d,0x04,0x14,0x7d]
+0x7d,0x04,0x14,0x7d
+
+# GFX12: v_cmpx_nlg_f16_e32 exec_lo, v2          ; encoding: [0x7e,0x04,0x14,0x7d]
+0x7e,0x04,0x14,0x7d
+
+# GFX12: v_cmpx_nlg_f16_e32 exec_hi, v2          ; encoding: [0x7f,0x04,0x14,0x7d]
+0x7f,0x04,0x14,0x7d
+
+# GFX12: v_cmpx_nlg_f16_e32 null, v2             ; encoding: [0x7c,0x04,0x14,0x7d]
+0x7c,0x04,0x14,0x7d
+
+# GFX12: v_cmpx_nlg_f16_e32 -1, v2               ; encoding: [0xc1,0x04,0x14,0x7d]
+0xc1,0x04,0x14,0x7d
+
+# GFX12: v_cmpx_nlg_f16_e32 0.5, v2              ; encoding: [0xf0,0x04,0x14,0x7d]
+0xf0,0x04,0x14,0x7d
+
+# GFX12: v_cmpx_nlg_f16_e32 src_scc, v2          ; encoding: [0xfd,0x04,0x14,0x7d]
+0xfd,0x04,0x14,0x7d
+
+# GFX12: v_cmpx_nlg_f16_e32 0xfe0b, v127         ; encoding: [0xff,0xfe,0x14,0x7d,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x14,0x7d,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_nlg_f32_e32 v1, v2               ; encoding: [0x01,0x05,0x34,0x7d]
+0x01,0x05,0x34,0x7d
+
+# GFX12: v_cmpx_nlg_f32_e32 v255, v2             ; encoding: [0xff,0x05,0x34,0x7d]
+0xff,0x05,0x34,0x7d
+
+# GFX12: v_cmpx_nlg_f32_e32 s1, v2               ; encoding: [0x01,0x04,0x34,0x7d]
+0x01,0x04,0x34,0x7d
+
+# GFX12: v_cmpx_nlg_f32_e32 s105, v2             ; encoding: [0x69,0x04,0x34,0x7d]
+0x69,0x04,0x34,0x7d
+
+# GFX12: v_cmpx_nlg_f32_e32 vcc_lo, v2           ; encoding: [0x6a,0x04,0x34,0x7d]
+0x6a,0x04,0x34,0x7d
+
+# GFX12: v_cmpx_nlg_f32_e32 vcc_hi, v2           ; encoding: [0x6b,0x04,0x34,0x7d]
+0x6b,0x04,0x34,0x7d
+
+# GFX12: v_cmpx_nlg_f32_e32 ttmp15, v2           ; encoding: [0x7b,0x04,0x34,0x7d]
+0x7b,0x04,0x34,0x7d
+
+# GFX12: v_cmpx_nlg_f32_e32 m0, v2               ; encoding: [0x7d,0x04,0x34,0x7d]
+0x7d,0x04,0x34,0x7d
+
+# GFX12: v_cmpx_nlg_f32_e32 exec_lo, v2          ; encoding: [0x7e,0x04,0x34,0x7d]
+0x7e,0x04,0x34,0x7d
+
+# GFX12: v_cmpx_nlg_f32_e32 exec_hi, v2          ; encoding: [0x7f,0x04,0x34,0x7d]
+0x7f,0x04,0x34,0x7d
+
+# GFX12: v_cmpx_nlg_f32_e32 null, v2             ; encoding: [0x7c,0x04,0x34,0x7d]
+0x7c,0x04,0x34,0x7d
+
+# GFX12: v_cmpx_nlg_f32_e32 -1, v2               ; encoding: [0xc1,0x04,0x34,0x7d]
+0xc1,0x04,0x34,0x7d
+
+# GFX12: v_cmpx_nlg_f32_e32 0.5, v2              ; encoding: [0xf0,0x04,0x34,0x7d]
+0xf0,0x04,0x34,0x7d
+
+# GFX12: v_cmpx_nlg_f32_e32 src_scc, v2          ; encoding: [0xfd,0x04,0x34,0x7d]
+0xfd,0x04,0x34,0x7d
+
+# GFX12: v_cmpx_nlg_f32_e32 0xaf123456, v255     ; encoding: [0xff,0xfe,0x35,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x35,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_nlg_f64_e32 v[1:2], v[2:3]       ; encoding: [0x01,0x05,0x54,0x7d]
+0x01,0x05,0x54,0x7d
+
+# GFX12: v_cmpx_nlg_f64_e32 v[254:255], v[2:3]   ; encoding: [0xfe,0x05,0x54,0x7d]
+0xfe,0x05,0x54,0x7d
+
+# GFX12: v_cmpx_nlg_f64_e32 s[2:3], v[2:3]       ; encoding: [0x02,0x04,0x54,0x7d]
+0x02,0x04,0x54,0x7d
+
+# GFX12: v_cmpx_nlg_f64_e32 s[104:105], v[2:3]   ; encoding: [0x68,0x04,0x54,0x7d]
+0x68,0x04,0x54,0x7d
+
+# GFX12: v_cmpx_nlg_f64_e32 vcc, v[2:3]          ; encoding: [0x6a,0x04,0x54,0x7d]
+0x6a,0x04,0x54,0x7d
+
+# GFX12: v_cmpx_nlg_f64_e32 ttmp[14:15], v[2:3]  ; encoding: [0x7a,0x04,0x54,0x7d]
+0x7a,0x04,0x54,0x7d
+
+# GFX12: v_cmpx_nlg_f64_e32 exec, v[2:3]         ; encoding: [0x7e,0x04,0x54,0x7d]
+0x7e,0x04,0x54,0x7d
+
+# GFX12: v_cmpx_nlg_f64_e32 null, v[2:3]         ; encoding: [0x7c,0x04,0x54,0x7d]
+0x7c,0x04,0x54,0x7d
+
+# GFX12: v_cmpx_nlg_f64_e32 -1, v[2:3]           ; encoding: [0xc1,0x04,0x54,0x7d]
+0xc1,0x04,0x54,0x7d
+
+# GFX12: v_cmpx_nlg_f64_e32 0.5, v[2:3]          ; encoding: [0xf0,0x04,0x54,0x7d]
+0xf0,0x04,0x54,0x7d
+
+# GFX12: v_cmpx_nlg_f64_e32 src_scc, v[2:3]      ; encoding: [0xfd,0x04,0x54,0x7d]
+0xfd,0x04,0x54,0x7d
+
+# GFX12: v_cmpx_nlg_f64_e32 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x55,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x55,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_nlt_f16_e32 v1, v2               ; encoding: [0x01,0x05,0x1c,0x7d]
+0x01,0x05,0x1c,0x7d
+
+# GFX12: v_cmpx_nlt_f16_e32 v127, v2             ; encoding: [0x7f,0x05,0x1c,0x7d]
+0x7f,0x05,0x1c,0x7d
+
+# GFX12: v_cmpx_nlt_f16_e32 s1, v2               ; encoding: [0x01,0x04,0x1c,0x7d]
+0x01,0x04,0x1c,0x7d
+
+# GFX12: v_cmpx_nlt_f16_e32 s105, v2             ; encoding: [0x69,0x04,0x1c,0x7d]
+0x69,0x04,0x1c,0x7d
+
+# GFX12: v_cmpx_nlt_f16_e32 vcc_lo, v2           ; encoding: [0x6a,0x04,0x1c,0x7d]
+0x6a,0x04,0x1c,0x7d
+
+# GFX12: v_cmpx_nlt_f16_e32 vcc_hi, v2           ; encoding: [0x6b,0x04,0x1c,0x7d]
+0x6b,0x04,0x1c,0x7d
+
+# GFX12: v_cmpx_nlt_f16_e32 ttmp15, v2           ; encoding: [0x7b,0x04,0x1c,0x7d]
+0x7b,0x04,0x1c,0x7d
+
+# GFX12: v_cmpx_nlt_f16_e32 m0, v2               ; encoding: [0x7d,0x04,0x1c,0x7d]
+0x7d,0x04,0x1c,0x7d
+
+# GFX12: v_cmpx_nlt_f16_e32 exec_lo, v2          ; encoding: [0x7e,0x04,0x1c,0x7d]
+0x7e,0x04,0x1c,0x7d
+
+# GFX12: v_cmpx_nlt_f16_e32 exec_hi, v2          ; encoding: [0x7f,0x04,0x1c,0x7d]
+0x7f,0x04,0x1c,0x7d
+
+# GFX12: v_cmpx_nlt_f16_e32 null, v2             ; encoding: [0x7c,0x04,0x1c,0x7d]
+0x7c,0x04,0x1c,0x7d
+
+# GFX12: v_cmpx_nlt_f16_e32 -1, v2               ; encoding: [0xc1,0x04,0x1c,0x7d]
+0xc1,0x04,0x1c,0x7d
+
+# GFX12: v_cmpx_nlt_f16_e32 0.5, v2              ; encoding: [0xf0,0x04,0x1c,0x7d]
+0xf0,0x04,0x1c,0x7d
+
+# GFX12: v_cmpx_nlt_f16_e32 src_scc, v2          ; encoding: [0xfd,0x04,0x1c,0x7d]
+0xfd,0x04,0x1c,0x7d
+
+# GFX12: v_cmpx_nlt_f16_e32 0xfe0b, v127         ; encoding: [0xff,0xfe,0x1c,0x7d,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x1c,0x7d,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_nlt_f32_e32 v1, v2               ; encoding: [0x01,0x05,0x3c,0x7d]
+0x01,0x05,0x3c,0x7d
+
+# GFX12: v_cmpx_nlt_f32_e32 v255, v2             ; encoding: [0xff,0x05,0x3c,0x7d]
+0xff,0x05,0x3c,0x7d
+
+# GFX12: v_cmpx_nlt_f32_e32 s1, v2               ; encoding: [0x01,0x04,0x3c,0x7d]
+0x01,0x04,0x3c,0x7d
+
+# GFX12: v_cmpx_nlt_f32_e32 s105, v2             ; encoding: [0x69,0x04,0x3c,0x7d]
+0x69,0x04,0x3c,0x7d
+
+# GFX12: v_cmpx_nlt_f32_e32 vcc_lo, v2           ; encoding: [0x6a,0x04,0x3c,0x7d]
+0x6a,0x04,0x3c,0x7d
+
+# GFX12: v_cmpx_nlt_f32_e32 vcc_hi, v2           ; encoding: [0x6b,0x04,0x3c,0x7d]
+0x6b,0x04,0x3c,0x7d
+
+# GFX12: v_cmpx_nlt_f32_e32 ttmp15, v2           ; encoding: [0x7b,0x04,0x3c,0x7d]
+0x7b,0x04,0x3c,0x7d
+
+# GFX12: v_cmpx_nlt_f32_e32 m0, v2               ; encoding: [0x7d,0x04,0x3c,0x7d]
+0x7d,0x04,0x3c,0x7d
+
+# GFX12: v_cmpx_nlt_f32_e32 exec_lo, v2          ; encoding: [0x7e,0x04,0x3c,0x7d]
+0x7e,0x04,0x3c,0x7d
+
+# GFX12: v_cmpx_nlt_f32_e32 exec_hi, v2          ; encoding: [0x7f,0x04,0x3c,0x7d]
+0x7f,0x04,0x3c,0x7d
+
+# GFX12: v_cmpx_nlt_f32_e32 null, v2             ; encoding: [0x7c,0x04,0x3c,0x7d]
+0x7c,0x04,0x3c,0x7d
+
+# GFX12: v_cmpx_nlt_f32_e32 -1, v2               ; encoding: [0xc1,0x04,0x3c,0x7d]
+0xc1,0x04,0x3c,0x7d
+
+# GFX12: v_cmpx_nlt_f32_e32 0.5, v2              ; encoding: [0xf0,0x04,0x3c,0x7d]
+0xf0,0x04,0x3c,0x7d
+
+# GFX12: v_cmpx_nlt_f32_e32 src_scc, v2          ; encoding: [0xfd,0x04,0x3c,0x7d]
+0xfd,0x04,0x3c,0x7d
+
+# GFX12: v_cmpx_nlt_f32_e32 0xaf123456, v255     ; encoding: [0xff,0xfe,0x3d,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x3d,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_nlt_f64_e32 v[1:2], v[2:3]       ; encoding: [0x01,0x05,0x5c,0x7d]
+0x01,0x05,0x5c,0x7d
+
+# GFX12: v_cmpx_nlt_f64_e32 v[254:255], v[2:3]   ; encoding: [0xfe,0x05,0x5c,0x7d]
+0xfe,0x05,0x5c,0x7d
+
+# GFX12: v_cmpx_nlt_f64_e32 s[2:3], v[2:3]       ; encoding: [0x02,0x04,0x5c,0x7d]
+0x02,0x04,0x5c,0x7d
+
+# GFX12: v_cmpx_nlt_f64_e32 s[104:105], v[2:3]   ; encoding: [0x68,0x04,0x5c,0x7d]
+0x68,0x04,0x5c,0x7d
+
+# GFX12: v_cmpx_nlt_f64_e32 vcc, v[2:3]          ; encoding: [0x6a,0x04,0x5c,0x7d]
+0x6a,0x04,0x5c,0x7d
+
+# GFX12: v_cmpx_nlt_f64_e32 ttmp[14:15], v[2:3]  ; encoding: [0x7a,0x04,0x5c,0x7d]
+0x7a,0x04,0x5c,0x7d
+
+# GFX12: v_cmpx_nlt_f64_e32 exec, v[2:3]         ; encoding: [0x7e,0x04,0x5c,0x7d]
+0x7e,0x04,0x5c,0x7d
+
+# GFX12: v_cmpx_nlt_f64_e32 null, v[2:3]         ; encoding: [0x7c,0x04,0x5c,0x7d]
+0x7c,0x04,0x5c,0x7d
+
+# GFX12: v_cmpx_nlt_f64_e32 -1, v[2:3]           ; encoding: [0xc1,0x04,0x5c,0x7d]
+0xc1,0x04,0x5c,0x7d
+
+# GFX12: v_cmpx_nlt_f64_e32 0.5, v[2:3]          ; encoding: [0xf0,0x04,0x5c,0x7d]
+0xf0,0x04,0x5c,0x7d
+
+# GFX12: v_cmpx_nlt_f64_e32 src_scc, v[2:3]      ; encoding: [0xfd,0x04,0x5c,0x7d]
+0xfd,0x04,0x5c,0x7d
+
+# GFX12: v_cmpx_nlt_f64_e32 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x5d,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x5d,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_o_f16_e32 v1, v2                 ; encoding: [0x01,0x05,0x0e,0x7d]
+0x01,0x05,0x0e,0x7d
+
+# GFX12: v_cmpx_o_f16_e32 v127, v2               ; encoding: [0x7f,0x05,0x0e,0x7d]
+0x7f,0x05,0x0e,0x7d
+
+# GFX12: v_cmpx_o_f16_e32 s1, v2                 ; encoding: [0x01,0x04,0x0e,0x7d]
+0x01,0x04,0x0e,0x7d
+
+# GFX12: v_cmpx_o_f16_e32 s105, v2               ; encoding: [0x69,0x04,0x0e,0x7d]
+0x69,0x04,0x0e,0x7d
+
+# GFX12: v_cmpx_o_f16_e32 vcc_lo, v2             ; encoding: [0x6a,0x04,0x0e,0x7d]
+0x6a,0x04,0x0e,0x7d
+
+# GFX12: v_cmpx_o_f16_e32 vcc_hi, v2             ; encoding: [0x6b,0x04,0x0e,0x7d]
+0x6b,0x04,0x0e,0x7d
+
+# GFX12: v_cmpx_o_f16_e32 ttmp15, v2             ; encoding: [0x7b,0x04,0x0e,0x7d]
+0x7b,0x04,0x0e,0x7d
+
+# GFX12: v_cmpx_o_f16_e32 m0, v2                 ; encoding: [0x7d,0x04,0x0e,0x7d]
+0x7d,0x04,0x0e,0x7d
+
+# GFX12: v_cmpx_o_f16_e32 exec_lo, v2            ; encoding: [0x7e,0x04,0x0e,0x7d]
+0x7e,0x04,0x0e,0x7d
+
+# GFX12: v_cmpx_o_f16_e32 exec_hi, v2            ; encoding: [0x7f,0x04,0x0e,0x7d]
+0x7f,0x04,0x0e,0x7d
+
+# GFX12: v_cmpx_o_f16_e32 null, v2               ; encoding: [0x7c,0x04,0x0e,0x7d]
+0x7c,0x04,0x0e,0x7d
+
+# GFX12: v_cmpx_o_f16_e32 -1, v2                 ; encoding: [0xc1,0x04,0x0e,0x7d]
+0xc1,0x04,0x0e,0x7d
+
+# GFX12: v_cmpx_o_f16_e32 0.5, v2                ; encoding: [0xf0,0x04,0x0e,0x7d]
+0xf0,0x04,0x0e,0x7d
+
+# GFX12: v_cmpx_o_f16_e32 src_scc, v2            ; encoding: [0xfd,0x04,0x0e,0x7d]
+0xfd,0x04,0x0e,0x7d
+
+# GFX12: v_cmpx_o_f16_e32 0xfe0b, v127           ; encoding: [0xff,0xfe,0x0e,0x7d,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x0e,0x7d,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_o_f32_e32 v1, v2                 ; encoding: [0x01,0x05,0x2e,0x7d]
+0x01,0x05,0x2e,0x7d
+
+# GFX12: v_cmpx_o_f32_e32 v255, v2               ; encoding: [0xff,0x05,0x2e,0x7d]
+0xff,0x05,0x2e,0x7d
+
+# GFX12: v_cmpx_o_f32_e32 s1, v2                 ; encoding: [0x01,0x04,0x2e,0x7d]
+0x01,0x04,0x2e,0x7d
+
+# GFX12: v_cmpx_o_f32_e32 s105, v2               ; encoding: [0x69,0x04,0x2e,0x7d]
+0x69,0x04,0x2e,0x7d
+
+# GFX12: v_cmpx_o_f32_e32 vcc_lo, v2             ; encoding: [0x6a,0x04,0x2e,0x7d]
+0x6a,0x04,0x2e,0x7d
+
+# GFX12: v_cmpx_o_f32_e32 vcc_hi, v2             ; encoding: [0x6b,0x04,0x2e,0x7d]
+0x6b,0x04,0x2e,0x7d
+
+# GFX12: v_cmpx_o_f32_e32 ttmp15, v2             ; encoding: [0x7b,0x04,0x2e,0x7d]
+0x7b,0x04,0x2e,0x7d
+
+# GFX12: v_cmpx_o_f32_e32 m0, v2                 ; encoding: [0x7d,0x04,0x2e,0x7d]
+0x7d,0x04,0x2e,0x7d
+
+# GFX12: v_cmpx_o_f32_e32 exec_lo, v2            ; encoding: [0x7e,0x04,0x2e,0x7d]
+0x7e,0x04,0x2e,0x7d
+
+# GFX12: v_cmpx_o_f32_e32 exec_hi, v2            ; encoding: [0x7f,0x04,0x2e,0x7d]
+0x7f,0x04,0x2e,0x7d
+
+# GFX12: v_cmpx_o_f32_e32 null, v2               ; encoding: [0x7c,0x04,0x2e,0x7d]
+0x7c,0x04,0x2e,0x7d
+
+# GFX12: v_cmpx_o_f32_e32 -1, v2                 ; encoding: [0xc1,0x04,0x2e,0x7d]
+0xc1,0x04,0x2e,0x7d
+
+# GFX12: v_cmpx_o_f32_e32 0.5, v2                ; encoding: [0xf0,0x04,0x2e,0x7d]
+0xf0,0x04,0x2e,0x7d
+
+# GFX12: v_cmpx_o_f32_e32 src_scc, v2            ; encoding: [0xfd,0x04,0x2e,0x7d]
+0xfd,0x04,0x2e,0x7d
+
+# GFX12: v_cmpx_o_f32_e32 0xaf123456, v255       ; encoding: [0xff,0xfe,0x2f,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x2f,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_o_f64_e32 v[1:2], v[2:3]         ; encoding: [0x01,0x05,0x4e,0x7d]
+0x01,0x05,0x4e,0x7d
+
+# GFX12: v_cmpx_o_f64_e32 v[254:255], v[2:3]     ; encoding: [0xfe,0x05,0x4e,0x7d]
+0xfe,0x05,0x4e,0x7d
+
+# GFX12: v_cmpx_o_f64_e32 s[2:3], v[2:3]         ; encoding: [0x02,0x04,0x4e,0x7d]
+0x02,0x04,0x4e,0x7d
+
+# GFX12: v_cmpx_o_f64_e32 s[104:105], v[2:3]     ; encoding: [0x68,0x04,0x4e,0x7d]
+0x68,0x04,0x4e,0x7d
+
+# GFX12: v_cmpx_o_f64_e32 vcc, v[2:3]            ; encoding: [0x6a,0x04,0x4e,0x7d]
+0x6a,0x04,0x4e,0x7d
+
+# GFX12: v_cmpx_o_f64_e32 ttmp[14:15], v[2:3]    ; encoding: [0x7a,0x04,0x4e,0x7d]
+0x7a,0x04,0x4e,0x7d
+
+# GFX12: v_cmpx_o_f64_e32 exec, v[2:3]           ; encoding: [0x7e,0x04,0x4e,0x7d]
+0x7e,0x04,0x4e,0x7d
+
+# GFX12: v_cmpx_o_f64_e32 null, v[2:3]           ; encoding: [0x7c,0x04,0x4e,0x7d]
+0x7c,0x04,0x4e,0x7d
+
+# GFX12: v_cmpx_o_f64_e32 -1, v[2:3]             ; encoding: [0xc1,0x04,0x4e,0x7d]
+0xc1,0x04,0x4e,0x7d
+
+# GFX12: v_cmpx_o_f64_e32 0.5, v[2:3]            ; encoding: [0xf0,0x04,0x4e,0x7d]
+0xf0,0x04,0x4e,0x7d
+
+# GFX12: v_cmpx_o_f64_e32 src_scc, v[2:3]        ; encoding: [0xfd,0x04,0x4e,0x7d]
+0xfd,0x04,0x4e,0x7d
+
+# GFX12: v_cmpx_o_f64_e32 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x4f,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x4f,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_u_f16_e32 v1, v2                 ; encoding: [0x01,0x05,0x10,0x7d]
+0x01,0x05,0x10,0x7d
+
+# GFX12: v_cmpx_u_f16_e32 v127, v2               ; encoding: [0x7f,0x05,0x10,0x7d]
+0x7f,0x05,0x10,0x7d
+
+# GFX12: v_cmpx_u_f16_e32 s1, v2                 ; encoding: [0x01,0x04,0x10,0x7d]
+0x01,0x04,0x10,0x7d
+
+# GFX12: v_cmpx_u_f16_e32 s105, v2               ; encoding: [0x69,0x04,0x10,0x7d]
+0x69,0x04,0x10,0x7d
+
+# GFX12: v_cmpx_u_f16_e32 vcc_lo, v2             ; encoding: [0x6a,0x04,0x10,0x7d]
+0x6a,0x04,0x10,0x7d
+
+# GFX12: v_cmpx_u_f16_e32 vcc_hi, v2             ; encoding: [0x6b,0x04,0x10,0x7d]
+0x6b,0x04,0x10,0x7d
+
+# GFX12: v_cmpx_u_f16_e32 ttmp15, v2             ; encoding: [0x7b,0x04,0x10,0x7d]
+0x7b,0x04,0x10,0x7d
+
+# GFX12: v_cmpx_u_f16_e32 m0, v2                 ; encoding: [0x7d,0x04,0x10,0x7d]
+0x7d,0x04,0x10,0x7d
+
+# GFX12: v_cmpx_u_f16_e32 exec_lo, v2            ; encoding: [0x7e,0x04,0x10,0x7d]
+0x7e,0x04,0x10,0x7d
+
+# GFX12: v_cmpx_u_f16_e32 exec_hi, v2            ; encoding: [0x7f,0x04,0x10,0x7d]
+0x7f,0x04,0x10,0x7d
+
+# GFX12: v_cmpx_u_f16_e32 null, v2               ; encoding: [0x7c,0x04,0x10,0x7d]
+0x7c,0x04,0x10,0x7d
+
+# GFX12: v_cmpx_u_f16_e32 -1, v2                 ; encoding: [0xc1,0x04,0x10,0x7d]
+0xc1,0x04,0x10,0x7d
+
+# GFX12: v_cmpx_u_f16_e32 0.5, v2                ; encoding: [0xf0,0x04,0x10,0x7d]
+0xf0,0x04,0x10,0x7d
+
+# GFX12: v_cmpx_u_f16_e32 src_scc, v2            ; encoding: [0xfd,0x04,0x10,0x7d]
+0xfd,0x04,0x10,0x7d
+
+# GFX12: v_cmpx_u_f16_e32 0xfe0b, v127           ; encoding: [0xff,0xfe,0x10,0x7d,0x0b,0xfe,0x00,0x00]
+0xff,0xfe,0x10,0x7d,0x0b,0xfe,0x00,0x00
+
+# GFX12: v_cmpx_u_f32_e32 v1, v2                 ; encoding: [0x01,0x05,0x30,0x7d]
+0x01,0x05,0x30,0x7d
+
+# GFX12: v_cmpx_u_f32_e32 v255, v2               ; encoding: [0xff,0x05,0x30,0x7d]
+0xff,0x05,0x30,0x7d
+
+# GFX12: v_cmpx_u_f32_e32 s1, v2                 ; encoding: [0x01,0x04,0x30,0x7d]
+0x01,0x04,0x30,0x7d
+
+# GFX12: v_cmpx_u_f32_e32 s105, v2               ; encoding: [0x69,0x04,0x30,0x7d]
+0x69,0x04,0x30,0x7d
+
+# GFX12: v_cmpx_u_f32_e32 vcc_lo, v2             ; encoding: [0x6a,0x04,0x30,0x7d]
+0x6a,0x04,0x30,0x7d
+
+# GFX12: v_cmpx_u_f32_e32 vcc_hi, v2             ; encoding: [0x6b,0x04,0x30,0x7d]
+0x6b,0x04,0x30,0x7d
+
+# GFX12: v_cmpx_u_f32_e32 ttmp15, v2             ; encoding: [0x7b,0x04,0x30,0x7d]
+0x7b,0x04,0x30,0x7d
+
+# GFX12: v_cmpx_u_f32_e32 m0, v2                 ; encoding: [0x7d,0x04,0x30,0x7d]
+0x7d,0x04,0x30,0x7d
+
+# GFX12: v_cmpx_u_f32_e32 exec_lo, v2            ; encoding: [0x7e,0x04,0x30,0x7d]
+0x7e,0x04,0x30,0x7d
+
+# GFX12: v_cmpx_u_f32_e32 exec_hi, v2            ; encoding: [0x7f,0x04,0x30,0x7d]
+0x7f,0x04,0x30,0x7d
+
+# GFX12: v_cmpx_u_f32_e32 null, v2               ; encoding: [0x7c,0x04,0x30,0x7d]
+0x7c,0x04,0x30,0x7d
+
+# GFX12: v_cmpx_u_f32_e32 -1, v2                 ; encoding: [0xc1,0x04,0x30,0x7d]
+0xc1,0x04,0x30,0x7d
+
+# GFX12: v_cmpx_u_f32_e32 0.5, v2                ; encoding: [0xf0,0x04,0x30,0x7d]
+0xf0,0x04,0x30,0x7d
+
+# GFX12: v_cmpx_u_f32_e32 src_scc, v2            ; encoding: [0xfd,0x04,0x30,0x7d]
+0xfd,0x04,0x30,0x7d
+
+# GFX12: v_cmpx_u_f32_e32 0xaf123456, v255       ; encoding: [0xff,0xfe,0x31,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x31,0x7d,0x56,0x34,0x12,0xaf
+
+# GFX12: v_cmpx_u_f64_e32 v[1:2], v[2:3]         ; encoding: [0x01,0x05,0x50,0x7d]
+0x01,0x05,0x50,0x7d
+
+# GFX12: v_cmpx_u_f64_e32 v[254:255], v[2:3]     ; encoding: [0xfe,0x05,0x50,0x7d]
+0xfe,0x05,0x50,0x7d
+
+# GFX12: v_cmpx_u_f64_e32 s[2:3], v[2:3]         ; encoding: [0x02,0x04,0x50,0x7d]
+0x02,0x04,0x50,0x7d
+
+# GFX12: v_cmpx_u_f64_e32 s[104:105], v[2:3]     ; encoding: [0x68,0x04,0x50,0x7d]
+0x68,0x04,0x50,0x7d
+
+# GFX12: v_cmpx_u_f64_e32 vcc, v[2:3]            ; encoding: [0x6a,0x04,0x50,0x7d]
+0x6a,0x04,0x50,0x7d
+
+# GFX12: v_cmpx_u_f64_e32 ttmp[14:15], v[2:3]    ; encoding: [0x7a,0x04,0x50,0x7d]
+0x7a,0x04,0x50,0x7d
+
+# GFX12: v_cmpx_u_f64_e32 exec, v[2:3]           ; encoding: [0x7e,0x04,0x50,0x7d]
+0x7e,0x04,0x50,0x7d
+
+# GFX12: v_cmpx_u_f64_e32 null, v[2:3]           ; encoding: [0x7c,0x04,0x50,0x7d]
+0x7c,0x04,0x50,0x7d
+
+# GFX12: v_cmpx_u_f64_e32 -1, v[2:3]             ; encoding: [0xc1,0x04,0x50,0x7d]
+0xc1,0x04,0x50,0x7d
+
+# GFX12: v_cmpx_u_f64_e32 0.5, v[2:3]            ; encoding: [0xf0,0x04,0x50,0x7d]
+0xf0,0x04,0x50,0x7d
+
+# GFX12: v_cmpx_u_f64_e32 src_scc, v[2:3]        ; encoding: [0xfd,0x04,0x50,0x7d]
+0xfd,0x04,0x50,0x7d
+
+# GFX12: v_cmpx_u_f64_e32 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x51,0x7d,0x56,0x34,0x12,0xaf]
+0xff,0xfc,0x51,0x7d,0x56,0x34,0x12,0xaf
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp16.txt
new file mode 100644
index 000000000000..2ed92dbe192c
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp16.txt
@@ -0,0 +1,2270 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=GFX12
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=GFX12
+
+# GFX12: v_cmpx_class_f16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0xfa,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_class_f16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0xfa,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_class_f16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0xfa,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_class_f16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0xfa,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_class_f16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0xfa,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_class_f16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0xfa,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_class_f16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0xfa,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_class_f16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0xfa,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_class_f16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0xfa,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_class_f16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0xfa,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_class_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0xfa,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_class_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0xfa,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_class_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0xfa,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_class_f16 -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7d,0x7f,0x6f,0x3d,0x30]
+0xfa,0xfe,0xfa,0x7d,0x7f,0x6f,0x3d,0x30
+
+# GFX12: v_cmpx_class_f32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0xfc,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_class_f32 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0xfc,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_class_f32 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0xfc,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_class_f32 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0xfc,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_class_f32 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0xfc,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_class_f32 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0xfc,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_class_f32 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0xfc,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_class_f32 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0xfc,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_class_f32 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0xfc,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_class_f32 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0xfc,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_class_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0xfc,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_class_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfc,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0xfc,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_class_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfc,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0xfc,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_class_f32 -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfd,0x7d,0xff,0x6f,0x3d,0x30]
+0xfa,0xfe,0xfd,0x7d,0xff,0x6f,0x3d,0x30
+
+# GFX12: v_cmpx_eq_f16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x04,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_eq_f16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x04,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_eq_f16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x04,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_eq_f16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x04,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_eq_f16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x04,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_eq_f16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x04,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_eq_f16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x04,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_eq_f16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x04,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_eq_f16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x04,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_eq_f16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x04,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_eq_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x04,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_eq_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x04,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x04,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_eq_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x04,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x04,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_eq_f16 -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x04,0x7d,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0x04,0x7d,0x7f,0x6f,0xfd,0x30
+
+# GFX12: v_cmpx_eq_f32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x24,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_eq_f32 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x24,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_eq_f32 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x24,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_eq_f32 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x24,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_eq_f32 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x24,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_eq_f32 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x24,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_eq_f32 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x24,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_eq_f32 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x24,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_eq_f32 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x24,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_eq_f32 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x24,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_eq_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x24,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_eq_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x24,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x24,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_eq_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x24,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x24,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_eq_f32 -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x25,0x7d,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0x25,0x7d,0xff,0x6f,0xfd,0x30
+
+# GFX12: v_cmpx_eq_i16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x64,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_eq_i16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x64,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_eq_i16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x64,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_eq_i16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x64,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_eq_i16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x64,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_eq_i16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x64,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_eq_i16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x64,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_eq_i16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x64,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_eq_i16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x64,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_eq_i16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x64,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_eq_i16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x64,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x64,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_eq_i16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x64,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x64,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_eq_i16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x64,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x64,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_eq_i16 v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x64,0x7d,0x7f,0x6f,0x0d,0x30]
+0xfa,0xfe,0x64,0x7d,0x7f,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_eq_i32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x84,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_eq_i32 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x84,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_eq_i32 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x84,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_eq_i32 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x84,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_eq_i32 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x84,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_eq_i32 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x84,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_eq_i32 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x84,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_eq_i32 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x84,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_eq_i32 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x84,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_eq_i32 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x84,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_eq_i32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x84,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x84,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_eq_i32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x84,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x84,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_eq_i32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x84,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x84,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_eq_i32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x85,0x7d,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0x85,0x7d,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_eq_u16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x74,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_eq_u16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x74,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_eq_u16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x74,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_eq_u16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x74,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_eq_u16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x74,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_eq_u16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x74,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_eq_u16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x74,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_eq_u16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x74,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_eq_u16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x74,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_eq_u16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x74,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_eq_u16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x74,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x74,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_eq_u16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x74,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x74,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_eq_u16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x74,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x74,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_eq_u16 v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x74,0x7d,0x7f,0x6f,0x0d,0x30]
+0xfa,0xfe,0x74,0x7d,0x7f,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_eq_u32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x94,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_eq_u32 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x94,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_eq_u32 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x94,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_eq_u32 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x94,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_eq_u32 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x94,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_eq_u32 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x94,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_eq_u32 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x94,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_eq_u32 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x94,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_eq_u32 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x94,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_eq_u32 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x94,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_eq_u32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x94,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x94,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_eq_u32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x94,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x94,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_eq_u32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x94,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x94,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_eq_u32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x95,0x7d,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0x95,0x7d,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_ge_f16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0c,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_ge_f16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0c,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_ge_f16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0c,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_ge_f16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0c,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_ge_f16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0c,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_ge_f16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0c,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_ge_f16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0c,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_ge_f16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0c,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_ge_f16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0c,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_ge_f16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0c,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_ge_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0c,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0c,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_ge_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0c,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0c,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_ge_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0c,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0c,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_ge_f16 -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x0c,0x7d,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0x0c,0x7d,0x7f,0x6f,0xfd,0x30
+
+# GFX12: v_cmpx_ge_f32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x2c,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_ge_f32 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x2c,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_ge_f32 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x2c,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_ge_f32 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x2c,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_ge_f32 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x2c,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_ge_f32 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x2c,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_ge_f32 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x2c,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_ge_f32 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x2c,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_ge_f32 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x2c,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_ge_f32 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x2c,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_ge_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2c,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x2c,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_ge_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x2c,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x2c,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_ge_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x2c,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x2c,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_ge_f32 -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x2d,0x7d,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0x2d,0x7d,0xff,0x6f,0xfd,0x30
+
+# GFX12: v_cmpx_ge_i16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x6c,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_ge_i16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x6c,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_ge_i16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x6c,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_ge_i16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x6c,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_ge_i16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x6c,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_ge_i16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x6c,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_ge_i16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x6c,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_ge_i16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x6c,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_ge_i16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x6c,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_ge_i16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x6c,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_ge_i16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6c,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x6c,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_ge_i16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x6c,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x6c,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_ge_i16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x6c,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x6c,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_ge_i16 v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x6c,0x7d,0x7f,0x6f,0x0d,0x30]
+0xfa,0xfe,0x6c,0x7d,0x7f,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_ge_i32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x8c,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_ge_i32 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x8c,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_ge_i32 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x8c,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_ge_i32 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x8c,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_ge_i32 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x8c,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_ge_i32 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x8c,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_ge_i32 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x8c,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_ge_i32 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x8c,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_ge_i32 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x8c,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_ge_i32 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x8c,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_ge_i32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8c,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x8c,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_ge_i32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x8c,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x8c,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_ge_i32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x8c,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x8c,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_ge_i32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x8d,0x7d,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0x8d,0x7d,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_ge_u16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x7c,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_ge_u16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x7c,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_ge_u16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x7c,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_ge_u16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x7c,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_ge_u16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x7c,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_ge_u16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x7c,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_ge_u16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x7c,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_ge_u16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x7c,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_ge_u16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x7c,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_ge_u16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x7c,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_ge_u16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7c,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x7c,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_ge_u16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x7c,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x7c,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_ge_u16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x7c,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x7c,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_ge_u16 v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x7c,0x7d,0x7f,0x6f,0x0d,0x30]
+0xfa,0xfe,0x7c,0x7d,0x7f,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_ge_u32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x9c,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_ge_u32 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x9c,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_ge_u32 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x9c,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_ge_u32 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x9c,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_ge_u32 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x9c,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_ge_u32 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x9c,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_ge_u32 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x9c,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_ge_u32 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x9c,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_ge_u32 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x9c,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_ge_u32 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x9c,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_ge_u32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9c,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x9c,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_ge_u32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x9c,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x9c,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_ge_u32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x9c,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x9c,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_ge_u32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x9d,0x7d,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0x9d,0x7d,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_gt_f16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x08,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_gt_f16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x08,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_gt_f16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x08,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_gt_f16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x08,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_gt_f16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x08,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_gt_f16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x08,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_gt_f16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x08,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_gt_f16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x08,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_gt_f16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x08,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_gt_f16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x08,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_gt_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x08,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x08,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_gt_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x08,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x08,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_gt_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x08,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x08,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_gt_f16 -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x08,0x7d,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0x08,0x7d,0x7f,0x6f,0xfd,0x30
+
+# GFX12: v_cmpx_gt_f32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x28,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_gt_f32 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x28,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_gt_f32 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x28,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_gt_f32 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x28,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_gt_f32 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x28,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_gt_f32 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x28,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_gt_f32 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x28,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_gt_f32 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x28,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_gt_f32 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x28,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_gt_f32 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x28,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_gt_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x28,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x28,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_gt_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x28,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x28,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_gt_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x28,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x28,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_gt_f32 -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x29,0x7d,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0x29,0x7d,0xff,0x6f,0xfd,0x30
+
+# GFX12: v_cmpx_gt_i16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x68,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_gt_i16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x68,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_gt_i16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x68,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_gt_i16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x68,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_gt_i16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x68,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_gt_i16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x68,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_gt_i16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x68,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_gt_i16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x68,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_gt_i16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x68,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_gt_i16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x68,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_gt_i16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x68,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x68,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_gt_i16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x68,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x68,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_gt_i16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x68,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x68,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_gt_i16 v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x68,0x7d,0x7f,0x6f,0x0d,0x30]
+0xfa,0xfe,0x68,0x7d,0x7f,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_gt_i32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x88,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_gt_i32 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x88,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_gt_i32 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x88,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_gt_i32 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x88,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_gt_i32 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x88,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_gt_i32 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x88,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_gt_i32 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x88,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_gt_i32 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x88,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_gt_i32 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x88,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_gt_i32 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x88,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_gt_i32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x88,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x88,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_gt_i32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x88,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x88,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_gt_i32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x88,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x88,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_gt_i32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x89,0x7d,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0x89,0x7d,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_gt_u16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x78,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_gt_u16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x78,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_gt_u16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x78,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_gt_u16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x78,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_gt_u16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x78,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_gt_u16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x78,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_gt_u16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x78,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_gt_u16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x78,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_gt_u16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x78,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_gt_u16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x78,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_gt_u16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x78,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x78,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_gt_u16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x78,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x78,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_gt_u16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x78,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x78,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_gt_u16 v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x78,0x7d,0x7f,0x6f,0x0d,0x30]
+0xfa,0xfe,0x78,0x7d,0x7f,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_gt_u32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x98,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_gt_u32 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x98,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_gt_u32 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x98,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_gt_u32 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x98,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_gt_u32 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x98,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_gt_u32 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x98,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_gt_u32 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x98,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_gt_u32 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x98,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_gt_u32 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x98,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_gt_u32 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x98,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_gt_u32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x98,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x98,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_gt_u32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x98,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x98,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_gt_u32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x98,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x98,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_gt_u32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x99,0x7d,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0x99,0x7d,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_le_f16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x06,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_le_f16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x06,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_le_f16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x06,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_le_f16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x06,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_le_f16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x06,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_le_f16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x06,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_le_f16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x06,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_le_f16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x06,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_le_f16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x06,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_le_f16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x06,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_le_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x06,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x06,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_le_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x06,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x06,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_le_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x06,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x06,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_le_f16 -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x06,0x7d,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0x06,0x7d,0x7f,0x6f,0xfd,0x30
+
+# GFX12: v_cmpx_le_f32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x26,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_le_f32 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x26,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_le_f32 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x26,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_le_f32 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x26,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_le_f32 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x26,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_le_f32 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x26,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_le_f32 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x26,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_le_f32 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x26,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_le_f32 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x26,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_le_f32 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x26,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_le_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x26,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_le_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x26,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x26,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_le_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x26,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x26,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_le_f32 -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x27,0x7d,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0x27,0x7d,0xff,0x6f,0xfd,0x30
+
+# GFX12: v_cmpx_le_i16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x66,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_le_i16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x66,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_le_i16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x66,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_le_i16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x66,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_le_i16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x66,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_le_i16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x66,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_le_i16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x66,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_le_i16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x66,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_le_i16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x66,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_le_i16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x66,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_le_i16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x66,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x66,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_le_i16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x66,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x66,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_le_i16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x66,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x66,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_le_i16 v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x66,0x7d,0x7f,0x6f,0x0d,0x30]
+0xfa,0xfe,0x66,0x7d,0x7f,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_le_i32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x86,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_le_i32 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x86,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_le_i32 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x86,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_le_i32 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x86,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_le_i32 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x86,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_le_i32 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x86,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_le_i32 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x86,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_le_i32 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x86,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_le_i32 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x86,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_le_i32 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x86,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_le_i32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x86,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x86,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_le_i32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x86,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x86,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_le_i32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x86,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x86,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_le_i32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x87,0x7d,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0x87,0x7d,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_le_u16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x76,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_le_u16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x76,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_le_u16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x76,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_le_u16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x76,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_le_u16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x76,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_le_u16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x76,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_le_u16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x76,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_le_u16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x76,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_le_u16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x76,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_le_u16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x76,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_le_u16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x76,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x76,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_le_u16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x76,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x76,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_le_u16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x76,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x76,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_le_u16 v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x76,0x7d,0x7f,0x6f,0x0d,0x30]
+0xfa,0xfe,0x76,0x7d,0x7f,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_le_u32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x96,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_le_u32 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x96,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_le_u32 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x96,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_le_u32 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x96,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_le_u32 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x96,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_le_u32 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x96,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_le_u32 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x96,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_le_u32 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x96,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_le_u32 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x96,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_le_u32 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x96,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_le_u32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x96,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x96,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_le_u32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x96,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x96,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_le_u32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x96,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x96,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_le_u32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x97,0x7d,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0x97,0x7d,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_lg_f16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0a,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_lg_f16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0a,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_lg_f16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0a,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_lg_f16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0a,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_lg_f16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0a,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_lg_f16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0a,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_lg_f16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0a,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_lg_f16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0a,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_lg_f16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0a,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_lg_f16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0a,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_lg_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0a,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_lg_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0a,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_lg_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0a,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_lg_f16 -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x0a,0x7d,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0x0a,0x7d,0x7f,0x6f,0xfd,0x30
+
+# GFX12: v_cmpx_lg_f32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x2a,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_lg_f32 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x2a,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_lg_f32 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x2a,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_lg_f32 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x2a,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_lg_f32 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x2a,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_lg_f32 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x2a,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_lg_f32 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x2a,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_lg_f32 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x2a,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_lg_f32 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x2a,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_lg_f32 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x2a,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_lg_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2a,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x2a,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_lg_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x2a,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x2a,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_lg_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x2a,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x2a,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_lg_f32 -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x2b,0x7d,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0x2b,0x7d,0xff,0x6f,0xfd,0x30
+
+# GFX12: v_cmpx_lt_f16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x02,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_lt_f16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x02,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_lt_f16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x02,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_lt_f16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x02,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_lt_f16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x02,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_lt_f16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x02,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_lt_f16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x02,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_lt_f16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x02,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_lt_f16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x02,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_lt_f16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x02,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_lt_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x02,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_lt_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x02,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x02,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_lt_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x02,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x02,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_lt_f16 -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x02,0x7d,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0x02,0x7d,0x7f,0x6f,0xfd,0x30
+
+# GFX12: v_cmpx_lt_f32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x22,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_lt_f32 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x22,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_lt_f32 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x22,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_lt_f32 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x22,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_lt_f32 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x22,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_lt_f32 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x22,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_lt_f32 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x22,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_lt_f32 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x22,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_lt_f32 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x22,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_lt_f32 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x22,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_lt_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x22,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_lt_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x22,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x22,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_lt_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x22,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x22,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_lt_f32 -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x23,0x7d,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0x23,0x7d,0xff,0x6f,0xfd,0x30
+
+# GFX12: v_cmpx_lt_i16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x62,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_lt_i16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x62,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_lt_i16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x62,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_lt_i16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x62,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_lt_i16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x62,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_lt_i16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x62,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_lt_i16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x62,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_lt_i16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x62,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_lt_i16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x62,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_lt_i16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x62,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_lt_i16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x62,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x62,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_lt_i16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x62,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x62,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_lt_i16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x62,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x62,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_lt_i16 v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x62,0x7d,0x7f,0x6f,0x0d,0x30]
+0xfa,0xfe,0x62,0x7d,0x7f,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_lt_i32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x82,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_lt_i32 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x82,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_lt_i32 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x82,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_lt_i32 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x82,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_lt_i32 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x82,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_lt_i32 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x82,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_lt_i32 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x82,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_lt_i32 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x82,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_lt_i32 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x82,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_lt_i32 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x82,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_lt_i32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x82,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x82,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_lt_i32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x82,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x82,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_lt_i32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x82,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x82,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_lt_i32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x83,0x7d,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0x83,0x7d,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_lt_u16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x72,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_lt_u16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x72,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_lt_u16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x72,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_lt_u16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x72,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_lt_u16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x72,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_lt_u16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x72,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_lt_u16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x72,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_lt_u16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x72,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_lt_u16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x72,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_lt_u16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x72,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_lt_u16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x72,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x72,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_lt_u16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x72,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x72,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_lt_u16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x72,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x72,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_lt_u16 v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x72,0x7d,0x7f,0x6f,0x0d,0x30]
+0xfa,0xfe,0x72,0x7d,0x7f,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_lt_u32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x92,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_lt_u32 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x92,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_lt_u32 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x92,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_lt_u32 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x92,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_lt_u32 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x92,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_lt_u32 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x92,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_lt_u32 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x92,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_lt_u32 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x92,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_lt_u32 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x92,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_lt_u32 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x92,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_lt_u32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x92,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x92,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_lt_u32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x92,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x92,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_lt_u32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x92,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x92,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_lt_u32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x93,0x7d,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0x93,0x7d,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_ne_i16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x6a,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_ne_i16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x6a,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_ne_i16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x6a,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_ne_i16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x6a,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_ne_i16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x6a,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_ne_i16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x6a,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_ne_i16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x6a,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_ne_i16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x6a,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_ne_i16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x6a,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_ne_i16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x6a,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_ne_i16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x6a,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x6a,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_ne_i16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x6a,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x6a,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_ne_i16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x6a,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x6a,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_ne_i16 v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x6a,0x7d,0x7f,0x6f,0x0d,0x30]
+0xfa,0xfe,0x6a,0x7d,0x7f,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_ne_i32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x8a,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_ne_i32 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x8a,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_ne_i32 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x8a,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_ne_i32 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x8a,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_ne_i32 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x8a,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_ne_i32 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x8a,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_ne_i32 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x8a,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_ne_i32 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x8a,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_ne_i32 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x8a,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_ne_i32 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x8a,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_ne_i32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x8a,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x8a,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_ne_i32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x8a,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x8a,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_ne_i32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x8a,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x8a,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_ne_i32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x8b,0x7d,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0x8b,0x7d,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_ne_u16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x7a,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_ne_u16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x7a,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_ne_u16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x7a,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_ne_u16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x7a,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_ne_u16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x7a,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_ne_u16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x7a,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_ne_u16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x7a,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_ne_u16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x7a,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_ne_u16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x7a,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_ne_u16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x7a,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_ne_u16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x7a,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x7a,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_ne_u16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x7a,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x7a,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_ne_u16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x7a,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x7a,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_ne_u16 v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x7a,0x7d,0x7f,0x6f,0x0d,0x30]
+0xfa,0xfe,0x7a,0x7d,0x7f,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_ne_u32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x9a,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_ne_u32 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x9a,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_ne_u32 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x9a,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_ne_u32 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x9a,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_ne_u32 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x9a,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_ne_u32 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x9a,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_ne_u32 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x9a,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_ne_u32 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x9a,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_ne_u32 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x9a,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_ne_u32 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x9a,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_ne_u32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x9a,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x9a,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_ne_u32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x9a,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x9a,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_ne_u32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x9a,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x9a,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_ne_u32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x9b,0x7d,0xff,0x6f,0x0d,0x30]
+0xfa,0xfe,0x9b,0x7d,0xff,0x6f,0x0d,0x30
+
+# GFX12: v_cmpx_neq_f16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x1a,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_neq_f16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x1a,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_neq_f16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x1a,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_neq_f16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x1a,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_neq_f16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x1a,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_neq_f16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x1a,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_neq_f16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x1a,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_neq_f16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x1a,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_neq_f16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x1a,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_neq_f16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x1a,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_neq_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1a,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x1a,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_neq_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x1a,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x1a,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_neq_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x1a,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x1a,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_neq_f16 -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x1a,0x7d,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0x1a,0x7d,0x7f,0x6f,0xfd,0x30
+
+# GFX12: v_cmpx_neq_f32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x3a,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_neq_f32 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x3a,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_neq_f32 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x3a,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_neq_f32 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x3a,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_neq_f32 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x3a,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_neq_f32 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x3a,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_neq_f32 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x3a,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_neq_f32 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x3a,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_neq_f32 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x3a,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_neq_f32 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x3a,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_neq_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3a,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x3a,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_neq_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x3a,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x3a,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_neq_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x3a,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x3a,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_neq_f32 -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x3b,0x7d,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0x3b,0x7d,0xff,0x6f,0xfd,0x30
+
+# GFX12: v_cmpx_nge_f16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x12,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_nge_f16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x12,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_nge_f16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x12,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_nge_f16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x12,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_nge_f16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x12,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_nge_f16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x12,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_nge_f16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x12,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_nge_f16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x12,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_nge_f16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x12,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_nge_f16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x12,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_nge_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x12,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x12,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_nge_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x12,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x12,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_nge_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x12,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x12,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_nge_f16 -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x12,0x7d,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0x12,0x7d,0x7f,0x6f,0xfd,0x30
+
+# GFX12: v_cmpx_nge_f32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x32,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_nge_f32 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x32,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_nge_f32 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x32,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_nge_f32 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x32,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_nge_f32 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x32,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_nge_f32 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x32,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_nge_f32 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x32,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_nge_f32 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x32,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_nge_f32 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x32,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_nge_f32 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x32,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_nge_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x32,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x32,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_nge_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x32,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x32,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_nge_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x32,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x32,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_nge_f32 -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x33,0x7d,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0x33,0x7d,0xff,0x6f,0xfd,0x30
+
+# GFX12: v_cmpx_ngt_f16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x16,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_ngt_f16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x16,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_ngt_f16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x16,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x16,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x16,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x16,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x16,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x16,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x16,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x16,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x16,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x16,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x16,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x16,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_ngt_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x16,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x16,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_ngt_f16 -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x16,0x7d,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0x16,0x7d,0x7f,0x6f,0xfd,0x30
+
+# GFX12: v_cmpx_ngt_f32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x36,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_ngt_f32 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x36,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_ngt_f32 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x36,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f32 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x36,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f32 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x36,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f32 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x36,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f32 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x36,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f32 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x36,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f32 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x36,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f32 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x36,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x36,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x36,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_ngt_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x36,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x36,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_ngt_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x36,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x36,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_ngt_f32 -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x37,0x7d,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0x37,0x7d,0xff,0x6f,0xfd,0x30
+
+# GFX12: v_cmpx_nle_f16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x18,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_nle_f16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x18,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_nle_f16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x18,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_nle_f16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x18,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_nle_f16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x18,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_nle_f16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x18,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_nle_f16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x18,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_nle_f16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x18,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_nle_f16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x18,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_nle_f16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x18,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_nle_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x18,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x18,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_nle_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x18,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x18,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_nle_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x18,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x18,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_nle_f16 -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x18,0x7d,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0x18,0x7d,0x7f,0x6f,0xfd,0x30
+
+# GFX12: v_cmpx_nle_f32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x38,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_nle_f32 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x38,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_nle_f32 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x38,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_nle_f32 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x38,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_nle_f32 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x38,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_nle_f32 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x38,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_nle_f32 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x38,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_nle_f32 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x38,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_nle_f32 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x38,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_nle_f32 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x38,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_nle_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x38,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x38,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_nle_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x38,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x38,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_nle_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x38,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x38,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_nle_f32 -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x39,0x7d,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0x39,0x7d,0xff,0x6f,0xfd,0x30
+
+# GFX12: v_cmpx_nlg_f16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x14,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_nlg_f16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x14,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_nlg_f16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x14,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x14,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x14,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x14,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x14,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x14,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x14,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x14,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x14,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x14,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x14,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x14,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_nlg_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x14,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x14,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_nlg_f16 -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x14,0x7d,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0x14,0x7d,0x7f,0x6f,0xfd,0x30
+
+# GFX12: v_cmpx_nlg_f32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x34,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_nlg_f32 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x34,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_nlg_f32 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x34,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f32 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x34,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f32 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x34,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f32 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x34,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f32 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x34,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f32 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x34,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f32 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x34,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f32 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x34,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x34,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x34,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_nlg_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x34,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x34,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_nlg_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x34,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x34,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_nlg_f32 -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x35,0x7d,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0x35,0x7d,0xff,0x6f,0xfd,0x30
+
+# GFX12: v_cmpx_nlt_f16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x1c,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_nlt_f16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x1c,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_nlt_f16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x1c,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x1c,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x1c,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x1c,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x1c,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x1c,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x1c,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x1c,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x1c,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x1c,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x1c,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x1c,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_nlt_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x1c,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x1c,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_nlt_f16 -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x1c,0x7d,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0x1c,0x7d,0x7f,0x6f,0xfd,0x30
+
+# GFX12: v_cmpx_nlt_f32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x3c,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_nlt_f32 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x3c,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_nlt_f32 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x3c,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f32 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x3c,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f32 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x3c,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f32 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x3c,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f32 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x3c,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f32 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x3c,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f32 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x3c,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f32 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x3c,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x3c,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x3c,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_nlt_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x3c,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x3c,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_nlt_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x3c,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x3c,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_nlt_f32 -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x3d,0x7d,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0x3d,0x7d,0xff,0x6f,0xfd,0x30
+
+# GFX12: v_cmpx_o_f16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x0e,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_o_f16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x0e,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_o_f16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x0e,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_o_f16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x0e,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_o_f16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x0e,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_o_f16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x0e,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_o_f16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x0e,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_o_f16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x0e,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_o_f16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x0e,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_o_f16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x0e,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_o_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0e,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x0e,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_o_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0e,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x0e,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_o_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0e,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x0e,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_o_f16 -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x0e,0x7d,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0x0e,0x7d,0x7f,0x6f,0xfd,0x30
+
+# GFX12: v_cmpx_o_f32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x2e,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_o_f32 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x2e,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_o_f32 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x2e,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_o_f32 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x2e,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_o_f32 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x2e,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_o_f32 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x2e,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_o_f32 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x2e,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_o_f32 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x2e,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_o_f32 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x2e,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_o_f32 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x2e,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_o_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x2e,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x2e,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_o_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x2e,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x2e,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_o_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x2e,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x2e,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_o_f32 -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x2f,0x7d,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0x2f,0x7d,0xff,0x6f,0xfd,0x30
+
+# GFX12: v_cmpx_u_f16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x10,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_u_f16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x10,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_u_f16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x10,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_u_f16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x10,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_u_f16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x10,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_u_f16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x10,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_u_f16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x10,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_u_f16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x10,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_u_f16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x10,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_u_f16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x10,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_u_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x10,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x10,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_u_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x10,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x10,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_u_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x10,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x10,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_u_f16 -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x10,0x7d,0x7f,0x6f,0xfd,0x30]
+0xfa,0xfe,0x10,0x7d,0x7f,0x6f,0xfd,0x30
+
+# GFX12: v_cmpx_u_f32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7d,0x01,0x1b,0x00,0xff]
+0xfa,0x04,0x30,0x7d,0x01,0x1b,0x00,0xff
+
+# GFX12: v_cmpx_u_f32 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7d,0x01,0xe4,0x00,0xff]
+0xfa,0x04,0x30,0x7d,0x01,0xe4,0x00,0xff
+
+# GFX12: v_cmpx_u_f32 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7d,0x01,0x40,0x01,0xff]
+0xfa,0x04,0x30,0x7d,0x01,0x40,0x01,0xff
+
+# GFX12: v_cmpx_u_f32 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7d,0x01,0x41,0x01,0xff]
+0xfa,0x04,0x30,0x7d,0x01,0x41,0x01,0xff
+
+# GFX12: v_cmpx_u_f32 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7d,0x01,0x01,0x01,0xff]
+0xfa,0x04,0x30,0x7d,0x01,0x01,0x01,0xff
+
+# GFX12: v_cmpx_u_f32 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7d,0x01,0x0f,0x01,0xff]
+0xfa,0x04,0x30,0x7d,0x01,0x0f,0x01,0xff
+
+# GFX12: v_cmpx_u_f32 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7d,0x01,0x11,0x01,0xff]
+0xfa,0x04,0x30,0x7d,0x01,0x11,0x01,0xff
+
+# GFX12: v_cmpx_u_f32 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7d,0x01,0x1f,0x01,0xff]
+0xfa,0x04,0x30,0x7d,0x01,0x1f,0x01,0xff
+
+# GFX12: v_cmpx_u_f32 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7d,0x01,0x21,0x01,0xff]
+0xfa,0x04,0x30,0x7d,0x01,0x21,0x01,0xff
+
+# GFX12: v_cmpx_u_f32 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7d,0x01,0x2f,0x01,0xff]
+0xfa,0x04,0x30,0x7d,0x01,0x2f,0x01,0xff
+
+# GFX12: v_cmpx_u_f32 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x30,0x7d,0x01,0x50,0x01,0xff]
+0xfa,0x04,0x30,0x7d,0x01,0x50,0x01,0xff
+
+# GFX12: v_cmpx_u_f32 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x30,0x7d,0x01,0x5f,0x01,0x01]
+0xfa,0x04,0x30,0x7d,0x01,0x5f,0x01,0x01
+
+# GFX12: v_cmpx_u_f32 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x30,0x7d,0x01,0x60,0x01,0x13]
+0xfa,0x04,0x30,0x7d,0x01,0x60,0x01,0x13
+
+# GFX12: v_cmpx_u_f32 -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x31,0x7d,0xff,0x6f,0xfd,0x30]
+0xfa,0xfe,0x31,0x7d,0xff,0x6f,0xfd,0x30
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp8.txt
new file mode 100644
index 000000000000..9374b8b9287d
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp8.txt
@@ -0,0 +1,326 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=GFX12
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=GFX12
+
+# GFX12: v_cmpx_class_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0xfa,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_class_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfa,0x7d,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0xfa,0x7d,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cmpx_class_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfc,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0xfc,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_class_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfd,0x7d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0xfd,0x7d,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_eq_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x04,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x04,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_eq_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x04,0x7d,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x04,0x7d,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cmpx_eq_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x24,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x24,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_eq_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x25,0x7d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x25,0x7d,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_eq_i16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x64,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x64,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_eq_i16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x64,0x7d,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x64,0x7d,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cmpx_eq_i32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x84,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x84,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_eq_i32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x85,0x7d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x85,0x7d,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_eq_u16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x74,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x74,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_eq_u16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x74,0x7d,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x74,0x7d,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cmpx_eq_u32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x94,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x94,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_eq_u32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x95,0x7d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x95,0x7d,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_ge_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0c,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0c,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ge_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x0c,0x7d,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x0c,0x7d,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cmpx_ge_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x2c,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x2c,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ge_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x2d,0x7d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x2d,0x7d,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_ge_i16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x6c,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x6c,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ge_i16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x6c,0x7d,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x6c,0x7d,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cmpx_ge_i32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x8c,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x8c,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ge_i32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x8d,0x7d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x8d,0x7d,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_ge_u16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x7c,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x7c,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ge_u16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x7c,0x7d,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x7c,0x7d,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cmpx_ge_u32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x9c,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x9c,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ge_u32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x9d,0x7d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x9d,0x7d,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_gt_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x08,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x08,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_gt_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x08,0x7d,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x08,0x7d,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cmpx_gt_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x28,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x28,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_gt_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x29,0x7d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x29,0x7d,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_gt_i16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x68,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x68,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_gt_i16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x68,0x7d,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x68,0x7d,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cmpx_gt_i32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x88,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x88,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_gt_i32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x89,0x7d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x89,0x7d,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_gt_u16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x78,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x78,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_gt_u16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x78,0x7d,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x78,0x7d,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cmpx_gt_u32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x98,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x98,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_gt_u32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x99,0x7d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x99,0x7d,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_le_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x06,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x06,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_le_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x06,0x7d,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x06,0x7d,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cmpx_le_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x26,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x26,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_le_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x27,0x7d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x27,0x7d,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_le_i16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x66,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x66,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_le_i16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x66,0x7d,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x66,0x7d,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cmpx_le_i32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x86,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x86,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_le_i32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x87,0x7d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x87,0x7d,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_le_u16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x76,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x76,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_le_u16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x76,0x7d,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x76,0x7d,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cmpx_le_u32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x96,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x96,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_le_u32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x97,0x7d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x97,0x7d,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_lg_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0a,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_lg_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x0a,0x7d,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x0a,0x7d,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cmpx_lg_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x2a,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x2a,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_lg_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x2b,0x7d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x2b,0x7d,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_lt_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x02,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x02,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_lt_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x02,0x7d,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x02,0x7d,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cmpx_lt_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x22,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x22,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_lt_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x23,0x7d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x23,0x7d,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_lt_i16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x62,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x62,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_lt_i16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x62,0x7d,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x62,0x7d,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cmpx_lt_i32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x82,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x82,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_lt_i32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x83,0x7d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x83,0x7d,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_lt_u16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x72,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x72,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_lt_u16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x72,0x7d,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x72,0x7d,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cmpx_lt_u32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x92,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x92,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_lt_u32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x93,0x7d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x93,0x7d,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_ne_i16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x6a,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x6a,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ne_i16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x6a,0x7d,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x6a,0x7d,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cmpx_ne_i32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x8a,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x8a,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ne_i32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x8b,0x7d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x8b,0x7d,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_ne_u16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x7a,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x7a,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ne_u16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x7a,0x7d,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x7a,0x7d,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cmpx_ne_u32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x9a,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x9a,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ne_u32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x9b,0x7d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x9b,0x7d,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_neq_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x1a,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x1a,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_neq_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x1a,0x7d,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x1a,0x7d,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cmpx_neq_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x3a,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x3a,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_neq_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x3b,0x7d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x3b,0x7d,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_nge_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x12,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x12,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nge_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x12,0x7d,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x12,0x7d,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cmpx_nge_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x32,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x32,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nge_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x33,0x7d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x33,0x7d,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_ngt_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x16,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x16,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ngt_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x16,0x7d,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x16,0x7d,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cmpx_ngt_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x36,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x36,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_ngt_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x37,0x7d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x37,0x7d,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_nle_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x18,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x18,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nle_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x18,0x7d,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x18,0x7d,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cmpx_nle_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x38,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x38,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nle_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x39,0x7d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x39,0x7d,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_nlg_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x14,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x14,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nlg_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x14,0x7d,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x14,0x7d,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cmpx_nlg_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x34,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x34,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nlg_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x35,0x7d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x35,0x7d,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_nlt_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x1c,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x1c,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nlt_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x1c,0x7d,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x1c,0x7d,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cmpx_nlt_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x3c,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x3c,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_nlt_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x3d,0x7d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x3d,0x7d,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_o_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0e,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x0e,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_o_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x0e,0x7d,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x0e,0x7d,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cmpx_o_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x2e,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x2e,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_o_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x2f,0x7d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x2f,0x7d,0xff,0x00,0x00,0x00
+
+# GFX12: v_cmpx_u_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x10,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x10,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_u_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x10,0x7d,0x7f,0x00,0x00,0x00]
+0xea,0xfe,0x10,0x7d,0x7f,0x00,0x00,0x00
+
+# GFX12: v_cmpx_u_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x30,0x7d,0x01,0x77,0x39,0x05]
+0xe9,0x04,0x30,0x7d,0x01,0x77,0x39,0x05
+
+# GFX12: v_cmpx_u_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x31,0x7d,0xff,0x00,0x00,0x00]
+0xea,0xfe,0x31,0x7d,0xff,0x00,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopd.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopd.txt
new file mode 100644
index 000000000000..afd29bcdeb08
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopd.txt
@@ -0,0 +1,9613 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=GFX12
+
+# GFX12: v_dual_add_f32 v255, v4, v2 :: v_dual_add_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x08,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x08,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v1, v2 :: v_dual_add_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x08,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x08,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v255, v2 :: v_dual_add_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x08,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x08,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v2, v2 :: v_dual_add_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x08,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x08,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v3, v2 :: v_dual_add_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x08,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x08,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, s105, v2 :: v_dual_add_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x08,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x08,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, s1, v2 :: v_dual_add_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x08,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x08,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, ttmp15, v2 :: v_dual_add_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x08,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x08,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, exec_hi, v2 :: v_dual_add_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x08,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x08,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, exec_lo, v2 :: v_dual_add_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x08,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x08,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, m0, v2 :: v_dual_add_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x08,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x08,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, vcc_hi, v2 :: v_dual_add_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x08,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x08,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_add_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x08,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x08,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, 0xaf123456, v2 :: v_dual_add_f32 v6, null, v3 ; encoding: [0xff,0x04,0x08,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x08,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, src_scc, v2 :: v_dual_add_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x08,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x08,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, 0.5, v3 :: v_dual_add_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x08,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x08,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, -1, v4 :: v_dual_add_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x08,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x08,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_add_f32 v6, null, v5 :: v_dual_add_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x08,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x08,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, v4, v2 :: v_dual_add_nc_u32 v6, v1, v3 ; encoding: [0x04,0x05,0x20,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x20,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v1, v2 :: v_dual_add_nc_u32 v6, v255, v3 ; encoding: [0x01,0x05,0x20,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x20,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v255, v2 :: v_dual_add_nc_u32 v6, v2, v3 ; encoding: [0xff,0x05,0x20,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x20,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v2, v2 :: v_dual_add_nc_u32 v6, v3, v3 ; encoding: [0x02,0x05,0x20,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x20,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v3, v2 :: v_dual_add_nc_u32 v6, v4, v3 ; encoding: [0x03,0x05,0x20,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x20,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, s105, v2 :: v_dual_add_nc_u32 v6, s1, v3 ; encoding: [0x69,0x04,0x20,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x20,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, s1, v2 :: v_dual_add_nc_u32 v6, s105, v3 ; encoding: [0x01,0x04,0x20,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x20,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, ttmp15, v2 :: v_dual_add_nc_u32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x20,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x20,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, exec_hi, v2 :: v_dual_add_nc_u32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x20,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x20,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, exec_lo, v2 :: v_dual_add_nc_u32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x20,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x20,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, m0, v2 :: v_dual_add_nc_u32 v6, m0, v3 ; encoding: [0x7d,0x04,0x20,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x20,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, vcc_hi, v2 :: v_dual_add_nc_u32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x20,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x20,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_add_nc_u32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x20,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x20,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, 0xaf123456, v2 :: v_dual_add_nc_u32 v6, null, v3 ; encoding: [0xff,0x04,0x20,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x20,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, src_scc, v2 :: v_dual_add_nc_u32 v6, -1, v3 ; encoding: [0xfd,0x04,0x20,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x20,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, 0.5, v3 :: v_dual_add_nc_u32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x20,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x20,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, -1, v4 :: v_dual_add_nc_u32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x20,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x20,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_add_f32 v6, null, v5 :: v_dual_add_nc_u32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x20,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x20,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, v4, v2 :: v_dual_and_b32 v6, v1, v3 ; encoding: [0x04,0x05,0x24,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x24,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v1, v2 :: v_dual_and_b32 v6, v255, v3 ; encoding: [0x01,0x05,0x24,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x24,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v255, v2 :: v_dual_and_b32 v6, v2, v3 ; encoding: [0xff,0x05,0x24,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x24,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v2, v2 :: v_dual_and_b32 v6, v3, v3 ; encoding: [0x02,0x05,0x24,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x24,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v3, v2 :: v_dual_and_b32 v6, v4, v3 ; encoding: [0x03,0x05,0x24,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x24,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, s105, v2 :: v_dual_and_b32 v6, s1, v3 ; encoding: [0x69,0x04,0x24,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x24,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, s1, v2 :: v_dual_and_b32 v6, s105, v3 ; encoding: [0x01,0x04,0x24,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x24,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, ttmp15, v2 :: v_dual_and_b32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x24,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x24,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, exec_hi, v2 :: v_dual_and_b32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x24,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x24,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, exec_lo, v2 :: v_dual_and_b32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x24,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x24,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, m0, v2 :: v_dual_and_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0x24,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x24,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, vcc_hi, v2 :: v_dual_and_b32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x24,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x24,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_and_b32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x24,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x24,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, 0xaf123456, v2 :: v_dual_and_b32 v6, null, v3 ; encoding: [0xff,0x04,0x24,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x24,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, src_scc, v2 :: v_dual_and_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0x24,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x24,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, 0.5, v3 :: v_dual_and_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x24,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x24,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, -1, v4 :: v_dual_and_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x24,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x24,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_add_f32 v6, null, v5 :: v_dual_and_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x24,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x24,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, v4, v2 :: v_dual_cndmask_b32 v6, v1, v3 ; encoding: [0x04,0x05,0x12,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x12,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v1, v2 :: v_dual_cndmask_b32 v6, v255, v3 ; encoding: [0x01,0x05,0x12,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x12,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v255, v2 :: v_dual_cndmask_b32 v6, v2, v3 ; encoding: [0xff,0x05,0x12,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x12,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v2, v2 :: v_dual_cndmask_b32 v6, v3, v3 ; encoding: [0x02,0x05,0x12,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x12,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v3, v2 :: v_dual_cndmask_b32 v6, v4, v3 ; encoding: [0x03,0x05,0x12,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x12,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, s105, v2 :: v_dual_cndmask_b32 v6, s105, v3 ; encoding: [0x69,0x04,0x12,0xc9,0x69,0x06,0x06,0xff]
+0x69,0x04,0x12,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, s1, v2 :: v_dual_cndmask_b32 v6, s1, v3 ; encoding: [0x01,0x04,0x12,0xc9,0x01,0x06,0x06,0xff]
+0x01,0x04,0x12,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, ttmp15, v2 :: v_dual_cndmask_b32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0x12,0xc9,0x7b,0x06,0x06,0xff]
+0x7b,0x04,0x12,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, exec_hi, v2 :: v_dual_cndmask_b32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0x12,0xc9,0x7f,0x06,0x06,0xff]
+0x7f,0x04,0x12,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, exec_lo, v2 :: v_dual_cndmask_b32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0x12,0xc9,0x7e,0x06,0x06,0xff]
+0x7e,0x04,0x12,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, m0, v2 :: v_dual_cndmask_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0x12,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x12,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, vcc_hi, v2 :: v_dual_cndmask_b32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0x12,0xc9,0x6b,0x06,0x06,0xff]
+0x6b,0x04,0x12,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_cndmask_b32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0x12,0xc9,0x6a,0x06,0x06,0xff]
+0x6a,0x04,0x12,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, 0xaf123456, v2 :: v_dual_cndmask_b32 v6, null, v3 ; encoding: [0xff,0x04,0x12,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x12,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, src_scc, v2 :: v_dual_cndmask_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0x12,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x12,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, 0.5, v3 :: v_dual_cndmask_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x12,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x12,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, -1, v4 :: v_dual_cndmask_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x12,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x12,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_add_f32 v6, null, v5 :: v_dual_cndmask_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x12,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x12,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, v4, v2 :: v_dual_fmaak_f32 v6, v1, v3, 0xaf123456 ; encoding: [0x04,0x05,0x02,0xc9,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x04,0x05,0x02,0xc9,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, v1, v2 :: v_dual_fmaak_f32 v6, v255, v3, 0xaf123456 ; encoding: [0x01,0x05,0x02,0xc9,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x05,0x02,0xc9,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, v255, v2 :: v_dual_fmaak_f32 v6, v2, v3, 0xaf123456 ; encoding: [0xff,0x05,0x02,0xc9,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x05,0x02,0xc9,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, v2, v2 :: v_dual_fmaak_f32 v6, v3, v3, 0xaf123456 ; encoding: [0x02,0x05,0x02,0xc9,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x02,0x05,0x02,0xc9,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, v3, v2 :: v_dual_fmaak_f32 v6, v4, v3, 0xaf123456 ; encoding: [0x03,0x05,0x02,0xc9,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x03,0x05,0x02,0xc9,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, s105, v2 :: v_dual_fmaak_f32 v6, s105, v3, 0xaf123456 ; encoding: [0x69,0x04,0x02,0xc9,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x69,0x04,0x02,0xc9,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, s1, v2 :: v_dual_fmaak_f32 v6, s1, v3, 0xaf123456 ; encoding: [0x01,0x04,0x02,0xc9,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x04,0x02,0xc9,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, ttmp15, v2 :: v_dual_fmaak_f32 v6, ttmp15, v3, 0xaf123456 ; encoding: [0x7b,0x04,0x02,0xc9,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0x04,0x02,0xc9,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, exec_hi, v2 :: v_dual_fmaak_f32 v6, exec_hi, v3, 0xaf123456 ; encoding: [0x7f,0x04,0x02,0xc9,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0x04,0x02,0xc9,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, exec_lo, v2 :: v_dual_fmaak_f32 v6, exec_lo, v3, 0xaf123456 ; encoding: [0x7e,0x04,0x02,0xc9,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0x04,0x02,0xc9,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, m0, v2 :: v_dual_fmaak_f32 v6, m0, v3, 0xaf123456 ; encoding: [0x7d,0x04,0x02,0xc9,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0x04,0x02,0xc9,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, vcc_hi, v2 :: v_dual_fmaak_f32 v6, vcc_hi, v3, 0xaf123456 ; encoding: [0x6b,0x04,0x02,0xc9,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0x04,0x02,0xc9,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_fmaak_f32 v6, vcc_lo, v3, 0xaf123456 ; encoding: [0x6a,0x04,0x02,0xc9,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0x04,0x02,0xc9,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, null, v3, 0xaf123456 ; encoding: [0xff,0x04,0x02,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x02,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, src_scc, v2 :: v_dual_fmaak_f32 v6, -1, v3, 0xaf123456 ; encoding: [0xfd,0x04,0x02,0xc9,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0x04,0x02,0xc9,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, 0.5, v3 :: v_dual_fmaak_f32 v6, 0.5, v2, 0xaf123456 ; encoding: [0xf0,0x06,0x02,0xc9,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0x02,0xc9,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, -1, v4 :: v_dual_fmaak_f32 v6, src_scc, v5, 0xaf123456 ; encoding: [0xc1,0x08,0x02,0xc9,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0x02,0xc9,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v6, null, v5 :: v_dual_fmaak_f32 v255, 0xaf123456, v4, 0xaf123456 ; encoding: [0x7c,0x0a,0x02,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x02,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, v4, v2 :: v_dual_fmac_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x00,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x00,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v1, v2 :: v_dual_fmac_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x00,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x00,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v255, v2 :: v_dual_fmac_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x00,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x00,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v2, v2 :: v_dual_fmac_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x00,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x00,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v3, v2 :: v_dual_fmac_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x00,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x00,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, s105, v2 :: v_dual_fmac_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x00,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x00,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, s1, v2 :: v_dual_fmac_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x00,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x00,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, ttmp15, v2 :: v_dual_fmac_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x00,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x00,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, exec_hi, v2 :: v_dual_fmac_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x00,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x00,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, exec_lo, v2 :: v_dual_fmac_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x00,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x00,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, m0, v2 :: v_dual_fmac_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x00,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x00,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, vcc_hi, v2 :: v_dual_fmac_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x00,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x00,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_fmac_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x00,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x00,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, 0xaf123456, v2 :: v_dual_fmac_f32 v6, null, v3 ; encoding: [0xff,0x04,0x00,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x00,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, src_scc, v2 :: v_dual_fmac_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x00,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x00,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, 0.5, v3 :: v_dual_fmac_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x00,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x00,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, -1, v4 :: v_dual_fmac_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x00,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x00,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_add_f32 v6, null, v5 :: v_dual_fmac_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x00,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x00,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, v4, v255 :: v_dual_fmamk_f32 v6, v1, 0xaf123456, v255 ; encoding: [0x04,0xff,0x05,0xc9,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x04,0xff,0x05,0xc9,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, v1, v255 :: v_dual_fmamk_f32 v6, v255, 0xaf123456, v255 ; encoding: [0x01,0xff,0x05,0xc9,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xff,0x05,0xc9,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, v255, v255 :: v_dual_fmamk_f32 v6, v2, 0xaf123456, v255 ; encoding: [0xff,0xff,0x05,0xc9,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xff,0x05,0xc9,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, v2, v255 :: v_dual_fmamk_f32 v6, v3, 0xaf123456, v255 ; encoding: [0x02,0xff,0x05,0xc9,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x02,0xff,0x05,0xc9,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, v3, v255 :: v_dual_fmamk_f32 v6, v4, 0xaf123456, v255 ; encoding: [0x03,0xff,0x05,0xc9,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x03,0xff,0x05,0xc9,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, s105, v255 :: v_dual_fmamk_f32 v6, s105, 0xaf123456, v255 ; encoding: [0x69,0xfe,0x05,0xc9,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x69,0xfe,0x05,0xc9,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, s1, v255 :: v_dual_fmamk_f32 v6, s1, 0xaf123456, v255 ; encoding: [0x01,0xfe,0x05,0xc9,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xfe,0x05,0xc9,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, ttmp15, v255 :: v_dual_fmamk_f32 v6, ttmp15, 0xaf123456, v255 ; encoding: [0x7b,0xfe,0x05,0xc9,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0xfe,0x05,0xc9,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, exec_hi, v255 :: v_dual_fmamk_f32 v6, exec_hi, 0xaf123456, v255 ; encoding: [0x7f,0xfe,0x05,0xc9,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0xfe,0x05,0xc9,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, exec_lo, v255 :: v_dual_fmamk_f32 v6, exec_lo, 0xaf123456, v255 ; encoding: [0x7e,0xfe,0x05,0xc9,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0xfe,0x05,0xc9,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, m0, v255 :: v_dual_fmamk_f32 v6, m0, 0xaf123456, v255 ; encoding: [0x7d,0xfe,0x05,0xc9,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0xfe,0x05,0xc9,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, vcc_hi, v255 :: v_dual_fmamk_f32 v6, vcc_hi, 0xaf123456, v255 ; encoding: [0x6b,0xfe,0x05,0xc9,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0xfe,0x05,0xc9,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, vcc_lo, v255 :: v_dual_fmamk_f32 v6, vcc_lo, 0xaf123456, v255 ; encoding: [0x6a,0xfe,0x05,0xc9,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0xfe,0x05,0xc9,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, null, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x05,0xc9,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x05,0xc9,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, src_scc, v255 :: v_dual_fmamk_f32 v6, -1, 0xaf123456, v255 ; encoding: [0xfd,0xfe,0x05,0xc9,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0xfe,0x05,0xc9,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, 0.5, v3 :: v_dual_fmamk_f32 v6, 0.5, 0xaf123456, v255 ; encoding: [0xf0,0x06,0x04,0xc9,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0x04,0xc9,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, -1, v4 :: v_dual_fmamk_f32 v6, src_scc, 0xaf123456, v255 ; encoding: [0xc1,0x08,0x04,0xc9,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0x04,0xc9,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v6, null, v5 :: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x04,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x04,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, v4, v2 :: v_dual_lshlrev_b32 v6, v1, v3 ; encoding: [0x04,0x05,0x22,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x22,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v1, v2 :: v_dual_lshlrev_b32 v6, v255, v3 ; encoding: [0x01,0x05,0x22,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x22,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v255, v2 :: v_dual_lshlrev_b32 v6, v2, v3 ; encoding: [0xff,0x05,0x22,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x22,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v2, v2 :: v_dual_lshlrev_b32 v6, v3, v3 ; encoding: [0x02,0x05,0x22,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x22,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v3, v2 :: v_dual_lshlrev_b32 v6, v4, v3 ; encoding: [0x03,0x05,0x22,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x22,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, s105, v2 :: v_dual_lshlrev_b32 v6, s1, v3 ; encoding: [0x69,0x04,0x22,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x22,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, s1, v2 :: v_dual_lshlrev_b32 v6, s105, v3 ; encoding: [0x01,0x04,0x22,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x22,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, ttmp15, v2 :: v_dual_lshlrev_b32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x22,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x22,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, exec_hi, v2 :: v_dual_lshlrev_b32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x22,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x22,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, exec_lo, v2 :: v_dual_lshlrev_b32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x22,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x22,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, m0, v2 :: v_dual_lshlrev_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0x22,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x22,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, vcc_hi, v2 :: v_dual_lshlrev_b32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x22,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x22,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_lshlrev_b32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x22,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x22,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, 0xaf123456, v2 :: v_dual_lshlrev_b32 v6, null, v3 ; encoding: [0xff,0x04,0x22,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x22,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, src_scc, v2 :: v_dual_lshlrev_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0x22,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x22,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, 0.5, v3 :: v_dual_lshlrev_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x22,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x22,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, -1, v4 :: v_dual_lshlrev_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x22,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x22,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_add_f32 v6, null, v5 :: v_dual_lshlrev_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x22,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x22,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, v4, v2 :: v_dual_max_num_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x14,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x14,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v1, v2 :: v_dual_max_num_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x14,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x14,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v255, v2 :: v_dual_max_num_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x14,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x14,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v2, v2 :: v_dual_max_num_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x14,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x14,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v3, v2 :: v_dual_max_num_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x14,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x14,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, s105, v2 :: v_dual_max_num_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x14,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x14,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, s1, v2 :: v_dual_max_num_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x14,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x14,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, ttmp15, v2 :: v_dual_max_num_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x14,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x14,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, exec_hi, v2 :: v_dual_max_num_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x14,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x14,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, exec_lo, v2 :: v_dual_max_num_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x14,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x14,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, m0, v2 :: v_dual_max_num_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x14,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x14,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, vcc_hi, v2 :: v_dual_max_num_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x14,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x14,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_max_num_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x14,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x14,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, 0xaf123456, v2 :: v_dual_max_num_f32 v6, null, v3 ; encoding: [0xff,0x04,0x14,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x14,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, src_scc, v2 :: v_dual_max_num_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x14,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x14,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, 0.5, v3 :: v_dual_max_num_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x14,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x14,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, -1, v4 :: v_dual_max_num_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x14,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x14,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_add_f32 v6, null, v5 :: v_dual_max_num_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x14,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x14,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, v4, v2 :: v_dual_min_num_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x16,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x16,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v1, v2 :: v_dual_min_num_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x16,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x16,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v255, v2 :: v_dual_min_num_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x16,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x16,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v2, v2 :: v_dual_min_num_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x16,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x16,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v3, v2 :: v_dual_min_num_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x16,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x16,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, s105, v2 :: v_dual_min_num_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x16,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x16,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, s1, v2 :: v_dual_min_num_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x16,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x16,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, ttmp15, v2 :: v_dual_min_num_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x16,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x16,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, exec_hi, v2 :: v_dual_min_num_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x16,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x16,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, exec_lo, v2 :: v_dual_min_num_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x16,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x16,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, m0, v2 :: v_dual_min_num_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x16,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x16,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, vcc_hi, v2 :: v_dual_min_num_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x16,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x16,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_min_num_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x16,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x16,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, 0xaf123456, v2 :: v_dual_min_num_f32 v6, null, v3 ; encoding: [0xff,0x04,0x16,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x16,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, src_scc, v2 :: v_dual_min_num_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x16,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x16,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, 0.5, v3 :: v_dual_min_num_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x16,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x16,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, -1, v4 :: v_dual_min_num_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x16,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x16,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_add_f32 v6, null, v5 :: v_dual_min_num_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x16,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x16,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, v4, v255 :: v_dual_mov_b32 v6, v1 ; encoding: [0x04,0xff,0x11,0xc9,0x01,0x01,0x06,0xff]
+0x04,0xff,0x11,0xc9,0x01,0x01,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v1, v255 :: v_dual_mov_b32 v6, v255 ; encoding: [0x01,0xff,0x11,0xc9,0xff,0x01,0x06,0xff]
+0x01,0xff,0x11,0xc9,0xff,0x01,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v255, v255 :: v_dual_mov_b32 v6, v2 ; encoding: [0xff,0xff,0x11,0xc9,0x02,0x01,0x06,0xff]
+0xff,0xff,0x11,0xc9,0x02,0x01,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v2, v255 :: v_dual_mov_b32 v6, v3 ; encoding: [0x02,0xff,0x11,0xc9,0x03,0x01,0x06,0xff]
+0x02,0xff,0x11,0xc9,0x03,0x01,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v3, v255 :: v_dual_mov_b32 v6, v4 ; encoding: [0x03,0xff,0x11,0xc9,0x04,0x01,0x06,0xff]
+0x03,0xff,0x11,0xc9,0x04,0x01,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, s105, v255 :: v_dual_mov_b32 v6, s1 ; encoding: [0x69,0xfe,0x11,0xc9,0x01,0x00,0x06,0xff]
+0x69,0xfe,0x11,0xc9,0x01,0x00,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, s1, v255 :: v_dual_mov_b32 v6, s105 ; encoding: [0x01,0xfe,0x11,0xc9,0x69,0x00,0x06,0xff]
+0x01,0xfe,0x11,0xc9,0x69,0x00,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, ttmp15, v255 :: v_dual_mov_b32 v6, vcc_lo ; encoding: [0x7b,0xfe,0x11,0xc9,0x6a,0x00,0x06,0xff]
+0x7b,0xfe,0x11,0xc9,0x6a,0x00,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, exec_hi, v255 :: v_dual_mov_b32 v6, vcc_hi ; encoding: [0x7f,0xfe,0x11,0xc9,0x6b,0x00,0x06,0xff]
+0x7f,0xfe,0x11,0xc9,0x6b,0x00,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, exec_lo, v255 :: v_dual_mov_b32 v6, ttmp15 ; encoding: [0x7e,0xfe,0x11,0xc9,0x7b,0x00,0x06,0xff]
+0x7e,0xfe,0x11,0xc9,0x7b,0x00,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, m0, v255 :: v_dual_mov_b32 v6, m0 ; encoding: [0x7d,0xfe,0x11,0xc9,0x7d,0x00,0x06,0xff]
+0x7d,0xfe,0x11,0xc9,0x7d,0x00,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, vcc_hi, v255 :: v_dual_mov_b32 v6, exec_lo ; encoding: [0x6b,0xfe,0x11,0xc9,0x7e,0x00,0x06,0xff]
+0x6b,0xfe,0x11,0xc9,0x7e,0x00,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, vcc_lo, v255 :: v_dual_mov_b32 v6, exec_hi ; encoding: [0x6a,0xfe,0x11,0xc9,0x7f,0x00,0x06,0xff]
+0x6a,0xfe,0x11,0xc9,0x7f,0x00,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, 0xaf123456, v255 :: v_dual_mov_b32 v6, null ; encoding: [0xff,0xfe,0x11,0xc9,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x11,0xc9,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, src_scc, v255 :: v_dual_mov_b32 v6, -1 ; encoding: [0xfd,0xfe,0x11,0xc9,0xc1,0x00,0x06,0xff]
+0xfd,0xfe,0x11,0xc9,0xc1,0x00,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, 0.5, v3 :: v_dual_mov_b32 v6, 0.5 ; encoding: [0xf0,0x06,0x10,0xc9,0xf0,0x00,0x06,0xff]
+0xf0,0x06,0x10,0xc9,0xf0,0x00,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, -1, v4 :: v_dual_mov_b32 v6, src_scc ; encoding: [0xc1,0x08,0x10,0xc9,0xfd,0x00,0x06,0xff]
+0xc1,0x08,0x10,0xc9,0xfd,0x00,0x06,0xff
+
+# GFX12: v_dual_add_f32 v6, null, v5 :: v_dual_mov_b32 v255, 0xaf123456 ; encoding: [0x7c,0x0a,0x10,0xc9,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x10,0xc9,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, v4, v2 :: v_dual_mul_dx9_zero_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x0e,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x0e,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v1, v2 :: v_dual_mul_dx9_zero_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x0e,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x0e,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v255, v2 :: v_dual_mul_dx9_zero_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x0e,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x0e,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v2, v2 :: v_dual_mul_dx9_zero_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x0e,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x0e,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v3, v2 :: v_dual_mul_dx9_zero_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x0e,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x0e,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, s105, v2 :: v_dual_mul_dx9_zero_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x0e,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x0e,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, s1, v2 :: v_dual_mul_dx9_zero_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x0e,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x0e,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, ttmp15, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x0e,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x0e,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, exec_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x0e,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x0e,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, exec_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x0e,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x0e,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, m0, v2 :: v_dual_mul_dx9_zero_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x0e,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x0e,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, vcc_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x0e,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x0e,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x0e,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x0e,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, 0xaf123456, v2 :: v_dual_mul_dx9_zero_f32 v6, null, v3 ; encoding: [0xff,0x04,0x0e,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x0e,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, src_scc, v2 :: v_dual_mul_dx9_zero_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x0e,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x0e,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, 0.5, v3 :: v_dual_mul_dx9_zero_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x0e,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x0e,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, -1, v4 :: v_dual_mul_dx9_zero_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x0e,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x0e,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_add_f32 v6, null, v5 :: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x0e,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x0e,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, v4, v2 :: v_dual_mul_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x06,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x06,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v1, v2 :: v_dual_mul_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x06,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x06,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v255, v2 :: v_dual_mul_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x06,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x06,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v2, v2 :: v_dual_mul_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x06,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x06,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v3, v2 :: v_dual_mul_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x06,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x06,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, s105, v2 :: v_dual_mul_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x06,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x06,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, s1, v2 :: v_dual_mul_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x06,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x06,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, ttmp15, v2 :: v_dual_mul_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x06,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x06,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, exec_hi, v2 :: v_dual_mul_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x06,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x06,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, exec_lo, v2 :: v_dual_mul_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x06,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x06,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, m0, v2 :: v_dual_mul_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x06,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x06,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, vcc_hi, v2 :: v_dual_mul_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x06,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x06,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_mul_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x06,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x06,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, 0xaf123456, v2 :: v_dual_mul_f32 v6, null, v3 ; encoding: [0xff,0x04,0x06,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x06,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, src_scc, v2 :: v_dual_mul_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x06,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x06,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, 0.5, v3 :: v_dual_mul_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x06,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x06,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, -1, v4 :: v_dual_mul_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x06,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x06,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_add_f32 v6, null, v5 :: v_dual_mul_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x06,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x06,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, v4, v2 :: v_dual_sub_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x0a,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x0a,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v1, v2 :: v_dual_sub_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x0a,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x0a,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v255, v2 :: v_dual_sub_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x0a,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x0a,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v2, v2 :: v_dual_sub_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x0a,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x0a,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v3, v2 :: v_dual_sub_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x0a,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x0a,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, s105, v2 :: v_dual_sub_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x0a,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x0a,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, s1, v2 :: v_dual_sub_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x0a,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x0a,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, ttmp15, v2 :: v_dual_sub_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x0a,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x0a,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, exec_hi, v2 :: v_dual_sub_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x0a,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x0a,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, exec_lo, v2 :: v_dual_sub_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x0a,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x0a,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, m0, v2 :: v_dual_sub_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x0a,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x0a,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, vcc_hi, v2 :: v_dual_sub_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x0a,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x0a,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_sub_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x0a,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x0a,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, 0xaf123456, v2 :: v_dual_sub_f32 v6, null, v3 ; encoding: [0xff,0x04,0x0a,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x0a,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, src_scc, v2 :: v_dual_sub_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x0a,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x0a,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, 0.5, v3 :: v_dual_sub_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x0a,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x0a,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, -1, v4 :: v_dual_sub_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x0a,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x0a,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_add_f32 v6, null, v5 :: v_dual_sub_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x0a,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x0a,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, v4, v2 :: v_dual_subrev_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x0c,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x0c,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v1, v2 :: v_dual_subrev_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x0c,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x0c,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v255, v2 :: v_dual_subrev_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x0c,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x0c,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v2, v2 :: v_dual_subrev_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x0c,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x0c,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, v3, v2 :: v_dual_subrev_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x0c,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x0c,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, s105, v2 :: v_dual_subrev_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x0c,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x0c,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, s1, v2 :: v_dual_subrev_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x0c,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x0c,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, ttmp15, v2 :: v_dual_subrev_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x0c,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x0c,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, exec_hi, v2 :: v_dual_subrev_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x0c,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x0c,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, exec_lo, v2 :: v_dual_subrev_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x0c,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x0c,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, m0, v2 :: v_dual_subrev_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x0c,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x0c,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, vcc_hi, v2 :: v_dual_subrev_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x0c,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x0c,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, vcc_lo, v2 :: v_dual_subrev_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x0c,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x0c,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, 0xaf123456, v2 :: v_dual_subrev_f32 v6, null, v3 ; encoding: [0xff,0x04,0x0c,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x0c,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_add_f32 v255, src_scc, v2 :: v_dual_subrev_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x0c,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x0c,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, 0.5, v3 :: v_dual_subrev_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x0c,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x0c,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_add_f32 v255, -1, v4 :: v_dual_subrev_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x0c,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x0c,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_add_f32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x0c,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x0c,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, v4, v2 :: v_dual_add_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x48,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0x48,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v1, v2 :: v_dual_add_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x48,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0x48,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v255, v2 :: v_dual_add_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x48,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0x48,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v2, v2 :: v_dual_add_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x48,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0x48,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v3, v2 :: v_dual_add_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x48,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0x48,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, s105, v2 :: v_dual_add_f32 v6, s105, v3 ; encoding: [0x69,0x04,0x48,0xca,0x69,0x06,0x06,0xff]
+0x69,0x04,0x48,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, s1, v2 :: v_dual_add_f32 v6, s1, v3 ; encoding: [0x01,0x04,0x48,0xca,0x01,0x06,0x06,0xff]
+0x01,0x04,0x48,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, ttmp15, v2 :: v_dual_add_f32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0x48,0xca,0x7b,0x06,0x06,0xff]
+0x7b,0x04,0x48,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, exec_hi, v2 :: v_dual_add_f32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0x48,0xca,0x7f,0x06,0x06,0xff]
+0x7f,0x04,0x48,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, exec_lo, v2 :: v_dual_add_f32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0x48,0xca,0x7e,0x06,0x06,0xff]
+0x7e,0x04,0x48,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, m0, v2 :: v_dual_add_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x48,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x48,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, vcc_hi, v2 :: v_dual_add_f32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0x48,0xca,0x6b,0x06,0x06,0xff]
+0x6b,0x04,0x48,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, vcc_lo, v2 :: v_dual_add_f32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0x48,0xca,0x6a,0x06,0x06,0xff]
+0x6a,0x04,0x48,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, 0xaf123456, v2 :: v_dual_add_f32 v6, null, v3 ; encoding: [0xff,0x04,0x48,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x48,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, src_scc, v2 :: v_dual_add_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x48,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x48,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_add_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x48,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x48,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, -1, v4 :: v_dual_add_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x48,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x48,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v6, null, v5 :: v_dual_add_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x48,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x48,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, v4, v2 :: v_dual_add_nc_u32 v6, v1, v3 ; encoding: [0x04,0x05,0x60,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0x60,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v1, v2 :: v_dual_add_nc_u32 v6, v255, v3 ; encoding: [0x01,0x05,0x60,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0x60,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v255, v2 :: v_dual_add_nc_u32 v6, v2, v3 ; encoding: [0xff,0x05,0x60,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0x60,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v2, v2 :: v_dual_add_nc_u32 v6, v3, v3 ; encoding: [0x02,0x05,0x60,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0x60,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v3, v2 :: v_dual_add_nc_u32 v6, v4, v3 ; encoding: [0x03,0x05,0x60,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0x60,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, s105, v2 :: v_dual_add_nc_u32 v6, s105, v3 ; encoding: [0x69,0x04,0x60,0xca,0x69,0x06,0x06,0xff]
+0x69,0x04,0x60,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, s1, v2 :: v_dual_add_nc_u32 v6, s1, v3 ; encoding: [0x01,0x04,0x60,0xca,0x01,0x06,0x06,0xff]
+0x01,0x04,0x60,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, ttmp15, v2 :: v_dual_add_nc_u32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0x60,0xca,0x7b,0x06,0x06,0xff]
+0x7b,0x04,0x60,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, exec_hi, v2 :: v_dual_add_nc_u32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0x60,0xca,0x7f,0x06,0x06,0xff]
+0x7f,0x04,0x60,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, exec_lo, v2 :: v_dual_add_nc_u32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0x60,0xca,0x7e,0x06,0x06,0xff]
+0x7e,0x04,0x60,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, m0, v2 :: v_dual_add_nc_u32 v6, m0, v3 ; encoding: [0x7d,0x04,0x60,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x60,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, vcc_hi, v2 :: v_dual_add_nc_u32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0x60,0xca,0x6b,0x06,0x06,0xff]
+0x6b,0x04,0x60,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, vcc_lo, v2 :: v_dual_add_nc_u32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0x60,0xca,0x6a,0x06,0x06,0xff]
+0x6a,0x04,0x60,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, 0xaf123456, v2 :: v_dual_add_nc_u32 v6, null, v3 ; encoding: [0xff,0x04,0x60,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x60,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, src_scc, v2 :: v_dual_add_nc_u32 v6, -1, v3 ; encoding: [0xfd,0x04,0x60,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x60,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_add_nc_u32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x60,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x60,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, -1, v4 :: v_dual_add_nc_u32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x60,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x60,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v6, null, v5 :: v_dual_add_nc_u32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x60,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x60,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, v4, v2 :: v_dual_and_b32 v6, v1, v3 ; encoding: [0x04,0x05,0x64,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0x64,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v1, v2 :: v_dual_and_b32 v6, v255, v3 ; encoding: [0x01,0x05,0x64,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0x64,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v255, v2 :: v_dual_and_b32 v6, v2, v3 ; encoding: [0xff,0x05,0x64,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0x64,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v2, v2 :: v_dual_and_b32 v6, v3, v3 ; encoding: [0x02,0x05,0x64,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0x64,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v3, v2 :: v_dual_and_b32 v6, v4, v3 ; encoding: [0x03,0x05,0x64,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0x64,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, s105, v2 :: v_dual_and_b32 v6, s105, v3 ; encoding: [0x69,0x04,0x64,0xca,0x69,0x06,0x06,0xff]
+0x69,0x04,0x64,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, s1, v2 :: v_dual_and_b32 v6, s1, v3 ; encoding: [0x01,0x04,0x64,0xca,0x01,0x06,0x06,0xff]
+0x01,0x04,0x64,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, ttmp15, v2 :: v_dual_and_b32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0x64,0xca,0x7b,0x06,0x06,0xff]
+0x7b,0x04,0x64,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, exec_hi, v2 :: v_dual_and_b32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0x64,0xca,0x7f,0x06,0x06,0xff]
+0x7f,0x04,0x64,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, exec_lo, v2 :: v_dual_and_b32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0x64,0xca,0x7e,0x06,0x06,0xff]
+0x7e,0x04,0x64,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, m0, v2 :: v_dual_and_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0x64,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x64,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, vcc_hi, v2 :: v_dual_and_b32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0x64,0xca,0x6b,0x06,0x06,0xff]
+0x6b,0x04,0x64,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, vcc_lo, v2 :: v_dual_and_b32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0x64,0xca,0x6a,0x06,0x06,0xff]
+0x6a,0x04,0x64,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, 0xaf123456, v2 :: v_dual_and_b32 v6, null, v3 ; encoding: [0xff,0x04,0x64,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x64,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, src_scc, v2 :: v_dual_and_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0x64,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x64,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_and_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x64,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x64,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, -1, v4 :: v_dual_and_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x64,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x64,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v6, null, v5 :: v_dual_and_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x64,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x64,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, v4, v2 :: v_dual_cndmask_b32 v6, v1, v3 ; encoding: [0x04,0x05,0x52,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0x52,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v1, v2 :: v_dual_cndmask_b32 v6, v255, v3 ; encoding: [0x01,0x05,0x52,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0x52,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v255, v2 :: v_dual_cndmask_b32 v6, v2, v3 ; encoding: [0xff,0x05,0x52,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0x52,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v2, v2 :: v_dual_cndmask_b32 v6, v3, v3 ; encoding: [0x02,0x05,0x52,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0x52,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v3, v2 :: v_dual_cndmask_b32 v6, v4, v3 ; encoding: [0x03,0x05,0x52,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0x52,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, s105, v2 :: v_dual_cndmask_b32 v6, s105, v3 ; encoding: [0x69,0x04,0x52,0xca,0x69,0x06,0x06,0xff]
+0x69,0x04,0x52,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, s1, v2 :: v_dual_cndmask_b32 v6, s1, v3 ; encoding: [0x01,0x04,0x52,0xca,0x01,0x06,0x06,0xff]
+0x01,0x04,0x52,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, ttmp15, v2 :: v_dual_cndmask_b32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0x52,0xca,0x7b,0x06,0x06,0xff]
+0x7b,0x04,0x52,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, exec_hi, v2 :: v_dual_cndmask_b32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0x52,0xca,0x7f,0x06,0x06,0xff]
+0x7f,0x04,0x52,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, exec_lo, v2 :: v_dual_cndmask_b32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0x52,0xca,0x7e,0x06,0x06,0xff]
+0x7e,0x04,0x52,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, m0, v2 :: v_dual_cndmask_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0x52,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x52,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, vcc_hi, v2 :: v_dual_cndmask_b32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0x52,0xca,0x6b,0x06,0x06,0xff]
+0x6b,0x04,0x52,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, vcc_lo, v2 :: v_dual_cndmask_b32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0x52,0xca,0x6a,0x06,0x06,0xff]
+0x6a,0x04,0x52,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, 0xaf123456, v2 :: v_dual_cndmask_b32 v6, null, v3 ; encoding: [0xff,0x04,0x52,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x52,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, src_scc, v2 :: v_dual_cndmask_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0x52,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x52,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_cndmask_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x52,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x52,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, -1, v4 :: v_dual_cndmask_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x52,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x52,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v6, null, v5 :: v_dual_cndmask_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x52,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x52,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, v4, v2 :: v_dual_fmaak_f32 v6, v1, v3, 0xaf123456 ; encoding: [0x04,0x05,0x42,0xca,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x04,0x05,0x42,0xca,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, v1, v2 :: v_dual_fmaak_f32 v6, v255, v3, 0xaf123456 ; encoding: [0x01,0x05,0x42,0xca,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x05,0x42,0xca,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, v255, v2 :: v_dual_fmaak_f32 v6, v2, v3, 0xaf123456 ; encoding: [0xff,0x05,0x42,0xca,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x05,0x42,0xca,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, v2, v2 :: v_dual_fmaak_f32 v6, v3, v3, 0xaf123456 ; encoding: [0x02,0x05,0x42,0xca,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x02,0x05,0x42,0xca,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, v3, v2 :: v_dual_fmaak_f32 v6, v4, v3, 0xaf123456 ; encoding: [0x03,0x05,0x42,0xca,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x03,0x05,0x42,0xca,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, null, v3, 0xaf123456 ; encoding: [0xff,0x04,0x42,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x42,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_fmaak_f32 v6, -1, v2, 0xaf123456 ; encoding: [0xf0,0x06,0x42,0xca,0xc1,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0x42,0xca,0xc1,0x04,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, -1, v4 :: v_dual_fmaak_f32 v6, 0.5, v5, 0xaf123456 ; encoding: [0xc1,0x08,0x42,0xca,0xf0,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0x42,0xca,0xf0,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v6, null, v5 :: v_dual_fmaak_f32 v255, 0xaf123456, v4, 0xaf123456 ; encoding: [0x7c,0x0a,0x42,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x42,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, v4, v2 :: v_dual_fmac_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x40,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0x40,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v1, v2 :: v_dual_fmac_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x40,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0x40,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v255, v2 :: v_dual_fmac_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x40,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0x40,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v2, v2 :: v_dual_fmac_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x40,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0x40,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v3, v2 :: v_dual_fmac_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x40,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0x40,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, s105, v2 :: v_dual_fmac_f32 v6, s105, v3 ; encoding: [0x69,0x04,0x40,0xca,0x69,0x06,0x06,0xff]
+0x69,0x04,0x40,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, s1, v2 :: v_dual_fmac_f32 v6, s1, v3 ; encoding: [0x01,0x04,0x40,0xca,0x01,0x06,0x06,0xff]
+0x01,0x04,0x40,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, ttmp15, v2 :: v_dual_fmac_f32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0x40,0xca,0x7b,0x06,0x06,0xff]
+0x7b,0x04,0x40,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, exec_hi, v2 :: v_dual_fmac_f32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0x40,0xca,0x7f,0x06,0x06,0xff]
+0x7f,0x04,0x40,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, exec_lo, v2 :: v_dual_fmac_f32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0x40,0xca,0x7e,0x06,0x06,0xff]
+0x7e,0x04,0x40,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, m0, v2 :: v_dual_fmac_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x40,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x40,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, vcc_hi, v2 :: v_dual_fmac_f32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0x40,0xca,0x6b,0x06,0x06,0xff]
+0x6b,0x04,0x40,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, vcc_lo, v2 :: v_dual_fmac_f32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0x40,0xca,0x6a,0x06,0x06,0xff]
+0x6a,0x04,0x40,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, 0xaf123456, v2 :: v_dual_fmac_f32 v6, null, v3 ; encoding: [0xff,0x04,0x40,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x40,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, src_scc, v2 :: v_dual_fmac_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x40,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x40,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_fmac_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x40,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x40,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, -1, v4 :: v_dual_fmac_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x40,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x40,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v6, null, v5 :: v_dual_fmac_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x40,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x40,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, v4, v255 :: v_dual_fmamk_f32 v6, v1, 0xaf123456, v255 ; encoding: [0x04,0xff,0x45,0xca,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x04,0xff,0x45,0xca,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, v1, v255 :: v_dual_fmamk_f32 v6, v255, 0xaf123456, v255 ; encoding: [0x01,0xff,0x45,0xca,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xff,0x45,0xca,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, v255, v255 :: v_dual_fmamk_f32 v6, v2, 0xaf123456, v255 ; encoding: [0xff,0xff,0x45,0xca,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xff,0x45,0xca,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, v2, v255 :: v_dual_fmamk_f32 v6, v3, 0xaf123456, v255 ; encoding: [0x02,0xff,0x45,0xca,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x02,0xff,0x45,0xca,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, v3, v255 :: v_dual_fmamk_f32 v6, v4, 0xaf123456, v255 ; encoding: [0x03,0xff,0x45,0xca,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x03,0xff,0x45,0xca,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, null, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x45,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x45,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_fmamk_f32 v6, -1, 0xaf123456, v255 ; encoding: [0xf0,0x06,0x44,0xca,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0x44,0xca,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, -1, v4 :: v_dual_fmamk_f32 v6, 0.5, 0xaf123456, v255 ; encoding: [0xc1,0x08,0x44,0xca,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0x44,0xca,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v6, null, v5 :: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x44,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x44,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, v4, v2 :: v_dual_lshlrev_b32 v6, v1, v3 ; encoding: [0x04,0x05,0x62,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0x62,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v1, v2 :: v_dual_lshlrev_b32 v6, v255, v3 ; encoding: [0x01,0x05,0x62,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0x62,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v255, v2 :: v_dual_lshlrev_b32 v6, v2, v3 ; encoding: [0xff,0x05,0x62,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0x62,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v2, v2 :: v_dual_lshlrev_b32 v6, v3, v3 ; encoding: [0x02,0x05,0x62,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0x62,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v3, v2 :: v_dual_lshlrev_b32 v6, v4, v3 ; encoding: [0x03,0x05,0x62,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0x62,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, s105, v2 :: v_dual_lshlrev_b32 v6, s105, v3 ; encoding: [0x69,0x04,0x62,0xca,0x69,0x06,0x06,0xff]
+0x69,0x04,0x62,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, s1, v2 :: v_dual_lshlrev_b32 v6, s1, v3 ; encoding: [0x01,0x04,0x62,0xca,0x01,0x06,0x06,0xff]
+0x01,0x04,0x62,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, ttmp15, v2 :: v_dual_lshlrev_b32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0x62,0xca,0x7b,0x06,0x06,0xff]
+0x7b,0x04,0x62,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, exec_hi, v2 :: v_dual_lshlrev_b32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0x62,0xca,0x7f,0x06,0x06,0xff]
+0x7f,0x04,0x62,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, exec_lo, v2 :: v_dual_lshlrev_b32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0x62,0xca,0x7e,0x06,0x06,0xff]
+0x7e,0x04,0x62,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, m0, v2 :: v_dual_lshlrev_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0x62,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x62,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, vcc_hi, v2 :: v_dual_lshlrev_b32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0x62,0xca,0x6b,0x06,0x06,0xff]
+0x6b,0x04,0x62,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, vcc_lo, v2 :: v_dual_lshlrev_b32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0x62,0xca,0x6a,0x06,0x06,0xff]
+0x6a,0x04,0x62,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, 0xaf123456, v2 :: v_dual_lshlrev_b32 v6, null, v3 ; encoding: [0xff,0x04,0x62,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x62,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, src_scc, v2 :: v_dual_lshlrev_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0x62,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x62,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_lshlrev_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x62,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x62,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, -1, v4 :: v_dual_lshlrev_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x62,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x62,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v6, null, v5 :: v_dual_lshlrev_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x62,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x62,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, v4, v2 :: v_dual_max_num_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x54,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0x54,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v1, v2 :: v_dual_max_num_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x54,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0x54,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v255, v2 :: v_dual_max_num_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x54,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0x54,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v2, v2 :: v_dual_max_num_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x54,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0x54,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v3, v2 :: v_dual_max_num_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x54,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0x54,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, s105, v2 :: v_dual_max_num_f32 v6, s105, v3 ; encoding: [0x69,0x04,0x54,0xca,0x69,0x06,0x06,0xff]
+0x69,0x04,0x54,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, s1, v2 :: v_dual_max_num_f32 v6, s1, v3 ; encoding: [0x01,0x04,0x54,0xca,0x01,0x06,0x06,0xff]
+0x01,0x04,0x54,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, ttmp15, v2 :: v_dual_max_num_f32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0x54,0xca,0x7b,0x06,0x06,0xff]
+0x7b,0x04,0x54,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, exec_hi, v2 :: v_dual_max_num_f32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0x54,0xca,0x7f,0x06,0x06,0xff]
+0x7f,0x04,0x54,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, exec_lo, v2 :: v_dual_max_num_f32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0x54,0xca,0x7e,0x06,0x06,0xff]
+0x7e,0x04,0x54,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, m0, v2 :: v_dual_max_num_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x54,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x54,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, vcc_hi, v2 :: v_dual_max_num_f32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0x54,0xca,0x6b,0x06,0x06,0xff]
+0x6b,0x04,0x54,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, vcc_lo, v2 :: v_dual_max_num_f32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0x54,0xca,0x6a,0x06,0x06,0xff]
+0x6a,0x04,0x54,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, 0xaf123456, v2 :: v_dual_max_num_f32 v6, null, v3 ; encoding: [0xff,0x04,0x54,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x54,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, src_scc, v2 :: v_dual_max_num_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x54,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x54,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_max_num_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x54,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x54,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, -1, v4 :: v_dual_max_num_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x54,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x54,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v6, null, v5 :: v_dual_max_num_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x54,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x54,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, v4, v2 :: v_dual_min_num_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x56,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0x56,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v1, v2 :: v_dual_min_num_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x56,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0x56,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v255, v2 :: v_dual_min_num_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x56,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0x56,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v2, v2 :: v_dual_min_num_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x56,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0x56,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v3, v2 :: v_dual_min_num_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x56,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0x56,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, s105, v2 :: v_dual_min_num_f32 v6, s105, v3 ; encoding: [0x69,0x04,0x56,0xca,0x69,0x06,0x06,0xff]
+0x69,0x04,0x56,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, s1, v2 :: v_dual_min_num_f32 v6, s1, v3 ; encoding: [0x01,0x04,0x56,0xca,0x01,0x06,0x06,0xff]
+0x01,0x04,0x56,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, ttmp15, v2 :: v_dual_min_num_f32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0x56,0xca,0x7b,0x06,0x06,0xff]
+0x7b,0x04,0x56,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, exec_hi, v2 :: v_dual_min_num_f32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0x56,0xca,0x7f,0x06,0x06,0xff]
+0x7f,0x04,0x56,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, exec_lo, v2 :: v_dual_min_num_f32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0x56,0xca,0x7e,0x06,0x06,0xff]
+0x7e,0x04,0x56,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, m0, v2 :: v_dual_min_num_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x56,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x56,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, vcc_hi, v2 :: v_dual_min_num_f32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0x56,0xca,0x6b,0x06,0x06,0xff]
+0x6b,0x04,0x56,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, vcc_lo, v2 :: v_dual_min_num_f32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0x56,0xca,0x6a,0x06,0x06,0xff]
+0x6a,0x04,0x56,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, 0xaf123456, v2 :: v_dual_min_num_f32 v6, null, v3 ; encoding: [0xff,0x04,0x56,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x56,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, src_scc, v2 :: v_dual_min_num_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x56,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x56,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_min_num_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x56,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x56,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, -1, v4 :: v_dual_min_num_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x56,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x56,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v6, null, v5 :: v_dual_min_num_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x56,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x56,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, v4, v255 :: v_dual_mov_b32 v6, v1 ; encoding: [0x04,0xff,0x51,0xca,0x01,0x01,0x06,0xff]
+0x04,0xff,0x51,0xca,0x01,0x01,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v1, v255 :: v_dual_mov_b32 v6, v255 ; encoding: [0x01,0xff,0x51,0xca,0xff,0x01,0x06,0xff]
+0x01,0xff,0x51,0xca,0xff,0x01,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v255, v255 :: v_dual_mov_b32 v6, v2 ; encoding: [0xff,0xff,0x51,0xca,0x02,0x01,0x06,0xff]
+0xff,0xff,0x51,0xca,0x02,0x01,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v2, v255 :: v_dual_mov_b32 v6, v3 ; encoding: [0x02,0xff,0x51,0xca,0x03,0x01,0x06,0xff]
+0x02,0xff,0x51,0xca,0x03,0x01,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v3, v255 :: v_dual_mov_b32 v6, v4 ; encoding: [0x03,0xff,0x51,0xca,0x04,0x01,0x06,0xff]
+0x03,0xff,0x51,0xca,0x04,0x01,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, s105, v255 :: v_dual_mov_b32 v6, s105 ; encoding: [0x69,0xfe,0x51,0xca,0x69,0x00,0x06,0xff]
+0x69,0xfe,0x51,0xca,0x69,0x00,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, s1, v255 :: v_dual_mov_b32 v6, s1 ; encoding: [0x01,0xfe,0x51,0xca,0x01,0x00,0x06,0xff]
+0x01,0xfe,0x51,0xca,0x01,0x00,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, ttmp15, v255 :: v_dual_mov_b32 v6, ttmp15 ; encoding: [0x7b,0xfe,0x51,0xca,0x7b,0x00,0x06,0xff]
+0x7b,0xfe,0x51,0xca,0x7b,0x00,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, exec_hi, v255 :: v_dual_mov_b32 v6, exec_hi ; encoding: [0x7f,0xfe,0x51,0xca,0x7f,0x00,0x06,0xff]
+0x7f,0xfe,0x51,0xca,0x7f,0x00,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, exec_lo, v255 :: v_dual_mov_b32 v6, exec_lo ; encoding: [0x7e,0xfe,0x51,0xca,0x7e,0x00,0x06,0xff]
+0x7e,0xfe,0x51,0xca,0x7e,0x00,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, m0, v255 :: v_dual_mov_b32 v6, m0 ; encoding: [0x7d,0xfe,0x51,0xca,0x7d,0x00,0x06,0xff]
+0x7d,0xfe,0x51,0xca,0x7d,0x00,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, vcc_hi, v255 :: v_dual_mov_b32 v6, vcc_hi ; encoding: [0x6b,0xfe,0x51,0xca,0x6b,0x00,0x06,0xff]
+0x6b,0xfe,0x51,0xca,0x6b,0x00,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, vcc_lo, v255 :: v_dual_mov_b32 v6, vcc_lo ; encoding: [0x6a,0xfe,0x51,0xca,0x6a,0x00,0x06,0xff]
+0x6a,0xfe,0x51,0xca,0x6a,0x00,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, 0xaf123456, v255 :: v_dual_mov_b32 v6, null ; encoding: [0xff,0xfe,0x51,0xca,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x51,0xca,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, src_scc, v255 :: v_dual_mov_b32 v6, -1 ; encoding: [0xfd,0xfe,0x51,0xca,0xc1,0x00,0x06,0xff]
+0xfd,0xfe,0x51,0xca,0xc1,0x00,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_mov_b32 v6, 0.5 ; encoding: [0xf0,0x06,0x50,0xca,0xf0,0x00,0x06,0xff]
+0xf0,0x06,0x50,0xca,0xf0,0x00,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, -1, v4 :: v_dual_mov_b32 v6, src_scc ; encoding: [0xc1,0x08,0x50,0xca,0xfd,0x00,0x06,0xff]
+0xc1,0x08,0x50,0xca,0xfd,0x00,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v6, null, v5 :: v_dual_mov_b32 v255, 0xaf123456 ; encoding: [0x7c,0x0a,0x50,0xca,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x50,0xca,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, v4, v2 :: v_dual_mul_dx9_zero_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x4e,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0x4e,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v1, v2 :: v_dual_mul_dx9_zero_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x4e,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0x4e,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v255, v2 :: v_dual_mul_dx9_zero_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x4e,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0x4e,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v2, v2 :: v_dual_mul_dx9_zero_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x4e,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0x4e,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v3, v2 :: v_dual_mul_dx9_zero_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x4e,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0x4e,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, s105, v2 :: v_dual_mul_dx9_zero_f32 v6, s105, v3 ; encoding: [0x69,0x04,0x4e,0xca,0x69,0x06,0x06,0xff]
+0x69,0x04,0x4e,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, s1, v2 :: v_dual_mul_dx9_zero_f32 v6, s1, v3 ; encoding: [0x01,0x04,0x4e,0xca,0x01,0x06,0x06,0xff]
+0x01,0x04,0x4e,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, ttmp15, v2 :: v_dual_mul_dx9_zero_f32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0x4e,0xca,0x7b,0x06,0x06,0xff]
+0x7b,0x04,0x4e,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, exec_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0x4e,0xca,0x7f,0x06,0x06,0xff]
+0x7f,0x04,0x4e,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, exec_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0x4e,0xca,0x7e,0x06,0x06,0xff]
+0x7e,0x04,0x4e,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, m0, v2 :: v_dual_mul_dx9_zero_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x4e,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x4e,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, vcc_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0x4e,0xca,0x6b,0x06,0x06,0xff]
+0x6b,0x04,0x4e,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, vcc_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0x4e,0xca,0x6a,0x06,0x06,0xff]
+0x6a,0x04,0x4e,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, 0xaf123456, v2 :: v_dual_mul_dx9_zero_f32 v6, null, v3 ; encoding: [0xff,0x04,0x4e,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x4e,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, src_scc, v2 :: v_dual_mul_dx9_zero_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x4e,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x4e,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_mul_dx9_zero_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x4e,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x4e,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, -1, v4 :: v_dual_mul_dx9_zero_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x4e,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x4e,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v6, null, v5 :: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x4e,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x4e,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, v4, v2 :: v_dual_mul_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x46,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0x46,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v1, v2 :: v_dual_mul_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x46,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0x46,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v255, v2 :: v_dual_mul_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x46,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0x46,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v2, v2 :: v_dual_mul_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x46,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0x46,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v3, v2 :: v_dual_mul_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x46,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0x46,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, s105, v2 :: v_dual_mul_f32 v6, s105, v3 ; encoding: [0x69,0x04,0x46,0xca,0x69,0x06,0x06,0xff]
+0x69,0x04,0x46,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, s1, v2 :: v_dual_mul_f32 v6, s1, v3 ; encoding: [0x01,0x04,0x46,0xca,0x01,0x06,0x06,0xff]
+0x01,0x04,0x46,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, ttmp15, v2 :: v_dual_mul_f32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0x46,0xca,0x7b,0x06,0x06,0xff]
+0x7b,0x04,0x46,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, exec_hi, v2 :: v_dual_mul_f32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0x46,0xca,0x7f,0x06,0x06,0xff]
+0x7f,0x04,0x46,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, exec_lo, v2 :: v_dual_mul_f32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0x46,0xca,0x7e,0x06,0x06,0xff]
+0x7e,0x04,0x46,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, m0, v2 :: v_dual_mul_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x46,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x46,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, vcc_hi, v2 :: v_dual_mul_f32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0x46,0xca,0x6b,0x06,0x06,0xff]
+0x6b,0x04,0x46,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, vcc_lo, v2 :: v_dual_mul_f32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0x46,0xca,0x6a,0x06,0x06,0xff]
+0x6a,0x04,0x46,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, 0xaf123456, v2 :: v_dual_mul_f32 v6, null, v3 ; encoding: [0xff,0x04,0x46,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x46,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, src_scc, v2 :: v_dual_mul_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x46,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x46,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_mul_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x46,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x46,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, -1, v4 :: v_dual_mul_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x46,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x46,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v6, null, v5 :: v_dual_mul_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x46,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x46,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, v4, v2 :: v_dual_sub_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x4a,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0x4a,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v1, v2 :: v_dual_sub_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x4a,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0x4a,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v255, v2 :: v_dual_sub_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x4a,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0x4a,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v2, v2 :: v_dual_sub_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x4a,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0x4a,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v3, v2 :: v_dual_sub_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x4a,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0x4a,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, s105, v2 :: v_dual_sub_f32 v6, s105, v3 ; encoding: [0x69,0x04,0x4a,0xca,0x69,0x06,0x06,0xff]
+0x69,0x04,0x4a,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, s1, v2 :: v_dual_sub_f32 v6, s1, v3 ; encoding: [0x01,0x04,0x4a,0xca,0x01,0x06,0x06,0xff]
+0x01,0x04,0x4a,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, ttmp15, v2 :: v_dual_sub_f32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0x4a,0xca,0x7b,0x06,0x06,0xff]
+0x7b,0x04,0x4a,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, exec_hi, v2 :: v_dual_sub_f32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0x4a,0xca,0x7f,0x06,0x06,0xff]
+0x7f,0x04,0x4a,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, exec_lo, v2 :: v_dual_sub_f32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0x4a,0xca,0x7e,0x06,0x06,0xff]
+0x7e,0x04,0x4a,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, m0, v2 :: v_dual_sub_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x4a,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x4a,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, vcc_hi, v2 :: v_dual_sub_f32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0x4a,0xca,0x6b,0x06,0x06,0xff]
+0x6b,0x04,0x4a,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, vcc_lo, v2 :: v_dual_sub_f32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0x4a,0xca,0x6a,0x06,0x06,0xff]
+0x6a,0x04,0x4a,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, 0xaf123456, v2 :: v_dual_sub_f32 v6, null, v3 ; encoding: [0xff,0x04,0x4a,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x4a,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, src_scc, v2 :: v_dual_sub_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x4a,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x4a,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_sub_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x4a,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x4a,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, -1, v4 :: v_dual_sub_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x4a,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x4a,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v6, null, v5 :: v_dual_sub_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x4a,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x4a,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, v4, v2 :: v_dual_subrev_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x4c,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0x4c,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v1, v2 :: v_dual_subrev_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x4c,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0x4c,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v255, v2 :: v_dual_subrev_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x4c,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0x4c,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v2, v2 :: v_dual_subrev_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x4c,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0x4c,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, v3, v2 :: v_dual_subrev_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x4c,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0x4c,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, s105, v2 :: v_dual_subrev_f32 v6, s105, v3 ; encoding: [0x69,0x04,0x4c,0xca,0x69,0x06,0x06,0xff]
+0x69,0x04,0x4c,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, s1, v2 :: v_dual_subrev_f32 v6, s1, v3 ; encoding: [0x01,0x04,0x4c,0xca,0x01,0x06,0x06,0xff]
+0x01,0x04,0x4c,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, ttmp15, v2 :: v_dual_subrev_f32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0x4c,0xca,0x7b,0x06,0x06,0xff]
+0x7b,0x04,0x4c,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, exec_hi, v2 :: v_dual_subrev_f32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0x4c,0xca,0x7f,0x06,0x06,0xff]
+0x7f,0x04,0x4c,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, exec_lo, v2 :: v_dual_subrev_f32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0x4c,0xca,0x7e,0x06,0x06,0xff]
+0x7e,0x04,0x4c,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, m0, v2 :: v_dual_subrev_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x4c,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x4c,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, vcc_hi, v2 :: v_dual_subrev_f32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0x4c,0xca,0x6b,0x06,0x06,0xff]
+0x6b,0x04,0x4c,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, vcc_lo, v2 :: v_dual_subrev_f32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0x4c,0xca,0x6a,0x06,0x06,0xff]
+0x6a,0x04,0x4c,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, 0xaf123456, v2 :: v_dual_subrev_f32 v6, null, v3 ; encoding: [0xff,0x04,0x4c,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x4c,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_cndmask_b32 v255, src_scc, v2 :: v_dual_subrev_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x4c,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x4c,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, 0.5, v3 :: v_dual_subrev_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x4c,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x4c,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v255, -1, v4 :: v_dual_subrev_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x4c,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x4c,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_cndmask_b32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x4c,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x4c,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v4, v2, 0xaf123456 :: v_dual_add_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x48,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x04,0x05,0x48,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v1, v2, 0xaf123456 :: v_dual_add_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x48,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x05,0x48,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v255, v2, 0xaf123456 :: v_dual_add_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x48,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x05,0x48,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v2, v2, 0xaf123456 :: v_dual_add_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x48,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x02,0x05,0x48,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v3, v2, 0xaf123456 :: v_dual_add_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x48,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x03,0x05,0x48,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, s105, v2, 0xaf123456 :: v_dual_add_f32 v6, s105, v3 ; encoding: [0x69,0x04,0x48,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x69,0x04,0x48,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, s1, v2, 0xaf123456 :: v_dual_add_f32 v6, s1, v3 ; encoding: [0x01,0x04,0x48,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x04,0x48,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, ttmp15, v2, 0xaf123456 :: v_dual_add_f32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0x48,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0x04,0x48,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, exec_hi, v2, 0xaf123456 :: v_dual_add_f32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0x48,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0x04,0x48,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, exec_lo, v2, 0xaf123456 :: v_dual_add_f32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0x48,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0x04,0x48,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, m0, v2, 0xaf123456 :: v_dual_add_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x48,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0x04,0x48,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, vcc_hi, v2, 0xaf123456 :: v_dual_add_f32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0x48,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0x04,0x48,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, vcc_lo, v2, 0xaf123456 :: v_dual_add_f32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0x48,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0x04,0x48,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0xaf123456, v2, 0xaf123456 :: v_dual_add_f32 v6, null, v3 ; encoding: [0xff,0x04,0x48,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x48,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, src_scc, v2, 0xaf123456 :: v_dual_add_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x48,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0x04,0x48,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_add_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x48,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0x48,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_add_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x48,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0x48,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_add_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x48,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x48,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v4, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, v1, v3 ; encoding: [0x04,0x05,0x60,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x04,0x05,0x60,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v1, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, v255, v3 ; encoding: [0x01,0x05,0x60,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x05,0x60,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v255, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, v2, v3 ; encoding: [0xff,0x05,0x60,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x05,0x60,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v2, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, v3, v3 ; encoding: [0x02,0x05,0x60,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x02,0x05,0x60,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v3, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, v4, v3 ; encoding: [0x03,0x05,0x60,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x03,0x05,0x60,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, s105, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, s105, v3 ; encoding: [0x69,0x04,0x60,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x69,0x04,0x60,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, s1, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, s1, v3 ; encoding: [0x01,0x04,0x60,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x04,0x60,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, ttmp15, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0x60,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0x04,0x60,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, exec_hi, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0x60,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0x04,0x60,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, exec_lo, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0x60,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0x04,0x60,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, m0, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, m0, v3 ; encoding: [0x7d,0x04,0x60,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0x04,0x60,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, vcc_hi, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0x60,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0x04,0x60,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, vcc_lo, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0x60,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0x04,0x60,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0xaf123456, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, null, v3 ; encoding: [0xff,0x04,0x60,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x60,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, src_scc, v2, 0xaf123456 :: v_dual_add_nc_u32 v6, -1, v3 ; encoding: [0xfd,0x04,0x60,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0x04,0x60,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_add_nc_u32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x60,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0x60,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_add_nc_u32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x60,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0x60,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_add_nc_u32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x60,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x60,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v4, v2, 0xaf123456 :: v_dual_and_b32 v6, v1, v3 ; encoding: [0x04,0x05,0x64,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x04,0x05,0x64,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v1, v2, 0xaf123456 :: v_dual_and_b32 v6, v255, v3 ; encoding: [0x01,0x05,0x64,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x05,0x64,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v255, v2, 0xaf123456 :: v_dual_and_b32 v6, v2, v3 ; encoding: [0xff,0x05,0x64,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x05,0x64,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v2, v2, 0xaf123456 :: v_dual_and_b32 v6, v3, v3 ; encoding: [0x02,0x05,0x64,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x02,0x05,0x64,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v3, v2, 0xaf123456 :: v_dual_and_b32 v6, v4, v3 ; encoding: [0x03,0x05,0x64,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x03,0x05,0x64,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, s105, v2, 0xaf123456 :: v_dual_and_b32 v6, s105, v3 ; encoding: [0x69,0x04,0x64,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x69,0x04,0x64,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, s1, v2, 0xaf123456 :: v_dual_and_b32 v6, s1, v3 ; encoding: [0x01,0x04,0x64,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x04,0x64,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, ttmp15, v2, 0xaf123456 :: v_dual_and_b32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0x64,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0x04,0x64,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, exec_hi, v2, 0xaf123456 :: v_dual_and_b32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0x64,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0x04,0x64,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, exec_lo, v2, 0xaf123456 :: v_dual_and_b32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0x64,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0x04,0x64,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, m0, v2, 0xaf123456 :: v_dual_and_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0x64,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0x04,0x64,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, vcc_hi, v2, 0xaf123456 :: v_dual_and_b32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0x64,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0x04,0x64,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, vcc_lo, v2, 0xaf123456 :: v_dual_and_b32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0x64,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0x04,0x64,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0xaf123456, v2, 0xaf123456 :: v_dual_and_b32 v6, null, v3 ; encoding: [0xff,0x04,0x64,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x64,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, src_scc, v2, 0xaf123456 :: v_dual_and_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0x64,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0x04,0x64,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_and_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x64,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0x64,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_and_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x64,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0x64,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_and_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x64,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x64,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v4, v2, 0xaf123456 :: v_dual_cndmask_b32 v6, v1, v3 ; encoding: [0x04,0x05,0x52,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x04,0x05,0x52,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v1, v2, 0xaf123456 :: v_dual_cndmask_b32 v6, v255, v3 ; encoding: [0x01,0x05,0x52,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x05,0x52,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v255, v2, 0xaf123456 :: v_dual_cndmask_b32 v6, v2, v3 ; encoding: [0xff,0x05,0x52,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x05,0x52,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v2, v2, 0xaf123456 :: v_dual_cndmask_b32 v6, v3, v3 ; encoding: [0x02,0x05,0x52,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x02,0x05,0x52,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v3, v2, 0xaf123456 :: v_dual_cndmask_b32 v6, v4, v3 ; encoding: [0x03,0x05,0x52,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x03,0x05,0x52,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0xaf123456, v2, 0xaf123456 :: v_dual_cndmask_b32 v6, null, v3 ; encoding: [0xff,0x04,0x52,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x52,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_cndmask_b32 v6, -1, v2 ; encoding: [0xf0,0x06,0x52,0xc8,0xc1,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0x52,0xc8,0xc1,0x04,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_cndmask_b32 v6, 0.5, v5 ; encoding: [0xc1,0x08,0x52,0xc8,0xf0,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0x52,0xc8,0xf0,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_cndmask_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x52,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x52,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v4, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, v1, v3, 0xaf123456 ; encoding: [0x04,0x05,0x42,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x04,0x05,0x42,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v1, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, v255, v3, 0xaf123456 ; encoding: [0x01,0x05,0x42,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x05,0x42,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v255, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, v2, v3, 0xaf123456 ; encoding: [0xff,0x05,0x42,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x05,0x42,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v2, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, v3, v3, 0xaf123456 ; encoding: [0x02,0x05,0x42,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x02,0x05,0x42,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v3, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, v4, v3, 0xaf123456 ; encoding: [0x03,0x05,0x42,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x03,0x05,0x42,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, s105, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, s105, v3, 0xaf123456 ; encoding: [0x69,0x04,0x42,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x69,0x04,0x42,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, s1, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, s1, v3, 0xaf123456 ; encoding: [0x01,0x04,0x42,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x04,0x42,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, ttmp15, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, ttmp15, v3, 0xaf123456 ; encoding: [0x7b,0x04,0x42,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0x04,0x42,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, exec_hi, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, exec_hi, v3, 0xaf123456 ; encoding: [0x7f,0x04,0x42,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0x04,0x42,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, exec_lo, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, exec_lo, v3, 0xaf123456 ; encoding: [0x7e,0x04,0x42,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0x04,0x42,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, m0, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, m0, v3, 0xaf123456 ; encoding: [0x7d,0x04,0x42,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0x04,0x42,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, vcc_hi, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, vcc_hi, v3, 0xaf123456 ; encoding: [0x6b,0x04,0x42,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0x04,0x42,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, vcc_lo, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, vcc_lo, v3, 0xaf123456 ; encoding: [0x6a,0x04,0x42,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0x04,0x42,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0xaf123456, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, null, v3, 0xaf123456 ; encoding: [0xff,0x04,0x42,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x42,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, src_scc, v2, 0xaf123456 :: v_dual_fmaak_f32 v6, -1, v3, 0xaf123456 ; encoding: [0xfd,0x04,0x42,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0x04,0x42,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_fmaak_f32 v6, 0.5, v2, 0xaf123456 ; encoding: [0xf0,0x06,0x42,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0x42,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_fmaak_f32 v6, src_scc, v5, 0xaf123456 ; encoding: [0xc1,0x08,0x42,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0x42,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_fmaak_f32 v255, 0xaf123456, v4, 0xaf123456 ; encoding: [0x7c,0x0a,0x42,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x42,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v4, v2, 0xaf123456 :: v_dual_fmac_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x40,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x04,0x05,0x40,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v1, v2, 0xaf123456 :: v_dual_fmac_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x40,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x05,0x40,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v255, v2, 0xaf123456 :: v_dual_fmac_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x40,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x05,0x40,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v2, v2, 0xaf123456 :: v_dual_fmac_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x40,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x02,0x05,0x40,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v3, v2, 0xaf123456 :: v_dual_fmac_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x40,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x03,0x05,0x40,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, s105, v2, 0xaf123456 :: v_dual_fmac_f32 v6, s105, v3 ; encoding: [0x69,0x04,0x40,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x69,0x04,0x40,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, s1, v2, 0xaf123456 :: v_dual_fmac_f32 v6, s1, v3 ; encoding: [0x01,0x04,0x40,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x04,0x40,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, ttmp15, v2, 0xaf123456 :: v_dual_fmac_f32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0x40,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0x04,0x40,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, exec_hi, v2, 0xaf123456 :: v_dual_fmac_f32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0x40,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0x04,0x40,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, exec_lo, v2, 0xaf123456 :: v_dual_fmac_f32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0x40,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0x04,0x40,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, m0, v2, 0xaf123456 :: v_dual_fmac_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x40,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0x04,0x40,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, vcc_hi, v2, 0xaf123456 :: v_dual_fmac_f32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0x40,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0x04,0x40,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, vcc_lo, v2, 0xaf123456 :: v_dual_fmac_f32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0x40,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0x04,0x40,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0xaf123456, v2, 0xaf123456 :: v_dual_fmac_f32 v6, null, v3 ; encoding: [0xff,0x04,0x40,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x40,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, src_scc, v2, 0xaf123456 :: v_dual_fmac_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x40,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0x04,0x40,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_fmac_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x40,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0x40,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_fmac_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x40,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0x40,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_fmac_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x40,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x40,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v4, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, v1, 0xaf123456, v255 ; encoding: [0x04,0xff,0x45,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x04,0xff,0x45,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v1, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, v255, 0xaf123456, v255 ; encoding: [0x01,0xff,0x45,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xff,0x45,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v255, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, v2, 0xaf123456, v255 ; encoding: [0xff,0xff,0x45,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xff,0x45,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v2, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, v3, 0xaf123456, v255 ; encoding: [0x02,0xff,0x45,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x02,0xff,0x45,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v3, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, v4, 0xaf123456, v255 ; encoding: [0x03,0xff,0x45,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x03,0xff,0x45,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, s105, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, s105, 0xaf123456, v255 ; encoding: [0x69,0xfe,0x45,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x69,0xfe,0x45,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, s1, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, s1, 0xaf123456, v255 ; encoding: [0x01,0xfe,0x45,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xfe,0x45,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, ttmp15, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, ttmp15, 0xaf123456, v255 ; encoding: [0x7b,0xfe,0x45,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0xfe,0x45,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, exec_hi, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, exec_hi, 0xaf123456, v255 ; encoding: [0x7f,0xfe,0x45,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0xfe,0x45,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, exec_lo, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, exec_lo, 0xaf123456, v255 ; encoding: [0x7e,0xfe,0x45,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0xfe,0x45,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, m0, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, m0, 0xaf123456, v255 ; encoding: [0x7d,0xfe,0x45,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0xfe,0x45,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, vcc_hi, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, vcc_hi, 0xaf123456, v255 ; encoding: [0x6b,0xfe,0x45,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0xfe,0x45,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, vcc_lo, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, vcc_lo, 0xaf123456, v255 ; encoding: [0x6a,0xfe,0x45,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0xfe,0x45,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0xaf123456, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, null, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x45,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x45,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, src_scc, v255, 0xaf123456 :: v_dual_fmamk_f32 v6, -1, 0xaf123456, v255 ; encoding: [0xfd,0xfe,0x45,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0xfe,0x45,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_fmamk_f32 v6, 0.5, 0xaf123456, v255 ; encoding: [0xf0,0x06,0x44,0xc8,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0x44,0xc8,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_fmamk_f32 v6, src_scc, 0xaf123456, v255 ; encoding: [0xc1,0x08,0x44,0xc8,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0x44,0xc8,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x44,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x44,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v4, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, v1, v3 ; encoding: [0x04,0x05,0x62,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x04,0x05,0x62,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v1, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, v255, v3 ; encoding: [0x01,0x05,0x62,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x05,0x62,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v255, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, v2, v3 ; encoding: [0xff,0x05,0x62,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x05,0x62,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v2, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, v3, v3 ; encoding: [0x02,0x05,0x62,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x02,0x05,0x62,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v3, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, v4, v3 ; encoding: [0x03,0x05,0x62,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x03,0x05,0x62,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, s105, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, s105, v3 ; encoding: [0x69,0x04,0x62,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x69,0x04,0x62,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, s1, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, s1, v3 ; encoding: [0x01,0x04,0x62,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x04,0x62,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, ttmp15, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0x62,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0x04,0x62,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, exec_hi, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0x62,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0x04,0x62,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, exec_lo, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0x62,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0x04,0x62,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, m0, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0x62,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0x04,0x62,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, vcc_hi, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0x62,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0x04,0x62,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, vcc_lo, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0x62,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0x04,0x62,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0xaf123456, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, null, v3 ; encoding: [0xff,0x04,0x62,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x62,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, src_scc, v2, 0xaf123456 :: v_dual_lshlrev_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0x62,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0x04,0x62,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_lshlrev_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x62,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0x62,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_lshlrev_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x62,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0x62,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_lshlrev_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x62,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x62,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v4, v2, 0xaf123456 :: v_dual_max_num_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x54,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x04,0x05,0x54,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v1, v2, 0xaf123456 :: v_dual_max_num_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x54,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x05,0x54,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v255, v2, 0xaf123456 :: v_dual_max_num_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x54,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x05,0x54,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v2, v2, 0xaf123456 :: v_dual_max_num_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x54,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x02,0x05,0x54,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v3, v2, 0xaf123456 :: v_dual_max_num_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x54,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x03,0x05,0x54,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, s105, v2, 0xaf123456 :: v_dual_max_num_f32 v6, s105, v3 ; encoding: [0x69,0x04,0x54,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x69,0x04,0x54,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, s1, v2, 0xaf123456 :: v_dual_max_num_f32 v6, s1, v3 ; encoding: [0x01,0x04,0x54,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x04,0x54,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, ttmp15, v2, 0xaf123456 :: v_dual_max_num_f32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0x54,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0x04,0x54,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, exec_hi, v2, 0xaf123456 :: v_dual_max_num_f32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0x54,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0x04,0x54,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, exec_lo, v2, 0xaf123456 :: v_dual_max_num_f32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0x54,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0x04,0x54,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, m0, v2, 0xaf123456 :: v_dual_max_num_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x54,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0x04,0x54,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, vcc_hi, v2, 0xaf123456 :: v_dual_max_num_f32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0x54,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0x04,0x54,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, vcc_lo, v2, 0xaf123456 :: v_dual_max_num_f32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0x54,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0x04,0x54,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0xaf123456, v2, 0xaf123456 :: v_dual_max_num_f32 v6, null, v3 ; encoding: [0xff,0x04,0x54,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x54,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, src_scc, v2, 0xaf123456 :: v_dual_max_num_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x54,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0x04,0x54,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_max_num_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x54,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0x54,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_max_num_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x54,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0x54,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_max_num_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x54,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x54,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v4, v2, 0xaf123456 :: v_dual_min_num_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x56,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x04,0x05,0x56,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v1, v2, 0xaf123456 :: v_dual_min_num_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x56,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x05,0x56,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v255, v2, 0xaf123456 :: v_dual_min_num_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x56,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x05,0x56,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v2, v2, 0xaf123456 :: v_dual_min_num_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x56,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x02,0x05,0x56,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v3, v2, 0xaf123456 :: v_dual_min_num_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x56,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x03,0x05,0x56,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, s105, v2, 0xaf123456 :: v_dual_min_num_f32 v6, s105, v3 ; encoding: [0x69,0x04,0x56,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x69,0x04,0x56,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, s1, v2, 0xaf123456 :: v_dual_min_num_f32 v6, s1, v3 ; encoding: [0x01,0x04,0x56,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x04,0x56,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, ttmp15, v2, 0xaf123456 :: v_dual_min_num_f32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0x56,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0x04,0x56,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, exec_hi, v2, 0xaf123456 :: v_dual_min_num_f32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0x56,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0x04,0x56,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, exec_lo, v2, 0xaf123456 :: v_dual_min_num_f32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0x56,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0x04,0x56,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, m0, v2, 0xaf123456 :: v_dual_min_num_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x56,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0x04,0x56,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, vcc_hi, v2, 0xaf123456 :: v_dual_min_num_f32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0x56,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0x04,0x56,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, vcc_lo, v2, 0xaf123456 :: v_dual_min_num_f32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0x56,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0x04,0x56,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0xaf123456, v2, 0xaf123456 :: v_dual_min_num_f32 v6, null, v3 ; encoding: [0xff,0x04,0x56,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x56,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, src_scc, v2, 0xaf123456 :: v_dual_min_num_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x56,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0x04,0x56,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_min_num_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x56,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0x56,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_min_num_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x56,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0x56,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_min_num_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x56,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x56,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v4, v255, 0xaf123456 :: v_dual_mov_b32 v6, v1 ; encoding: [0x04,0xff,0x51,0xc8,0x01,0x01,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x04,0xff,0x51,0xc8,0x01,0x01,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v1, v255, 0xaf123456 :: v_dual_mov_b32 v6, v255 ; encoding: [0x01,0xff,0x51,0xc8,0xff,0x01,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xff,0x51,0xc8,0xff,0x01,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v255, v255, 0xaf123456 :: v_dual_mov_b32 v6, v2 ; encoding: [0xff,0xff,0x51,0xc8,0x02,0x01,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xff,0x51,0xc8,0x02,0x01,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v2, v255, 0xaf123456 :: v_dual_mov_b32 v6, v3 ; encoding: [0x02,0xff,0x51,0xc8,0x03,0x01,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x02,0xff,0x51,0xc8,0x03,0x01,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v3, v255, 0xaf123456 :: v_dual_mov_b32 v6, v4 ; encoding: [0x03,0xff,0x51,0xc8,0x04,0x01,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x03,0xff,0x51,0xc8,0x04,0x01,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, s105, v255, 0xaf123456 :: v_dual_mov_b32 v6, s105 ; encoding: [0x69,0xfe,0x51,0xc8,0x69,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x69,0xfe,0x51,0xc8,0x69,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, s1, v255, 0xaf123456 :: v_dual_mov_b32 v6, s1 ; encoding: [0x01,0xfe,0x51,0xc8,0x01,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xfe,0x51,0xc8,0x01,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, ttmp15, v255, 0xaf123456 :: v_dual_mov_b32 v6, ttmp15 ; encoding: [0x7b,0xfe,0x51,0xc8,0x7b,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0xfe,0x51,0xc8,0x7b,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, exec_hi, v255, 0xaf123456 :: v_dual_mov_b32 v6, exec_hi ; encoding: [0x7f,0xfe,0x51,0xc8,0x7f,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0xfe,0x51,0xc8,0x7f,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, exec_lo, v255, 0xaf123456 :: v_dual_mov_b32 v6, exec_lo ; encoding: [0x7e,0xfe,0x51,0xc8,0x7e,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0xfe,0x51,0xc8,0x7e,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, m0, v255, 0xaf123456 :: v_dual_mov_b32 v6, m0 ; encoding: [0x7d,0xfe,0x51,0xc8,0x7d,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0xfe,0x51,0xc8,0x7d,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, vcc_hi, v255, 0xaf123456 :: v_dual_mov_b32 v6, vcc_hi ; encoding: [0x6b,0xfe,0x51,0xc8,0x6b,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0xfe,0x51,0xc8,0x6b,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, vcc_lo, v255, 0xaf123456 :: v_dual_mov_b32 v6, vcc_lo ; encoding: [0x6a,0xfe,0x51,0xc8,0x6a,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0xfe,0x51,0xc8,0x6a,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0xaf123456, v255, 0xaf123456 :: v_dual_mov_b32 v6, null ; encoding: [0xff,0xfe,0x51,0xc8,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x51,0xc8,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, src_scc, v255, 0xaf123456 :: v_dual_mov_b32 v6, -1 ; encoding: [0xfd,0xfe,0x51,0xc8,0xc1,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0xfe,0x51,0xc8,0xc1,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_mov_b32 v6, 0.5 ; encoding: [0xf0,0x06,0x50,0xc8,0xf0,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0x50,0xc8,0xf0,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_mov_b32 v6, src_scc ; encoding: [0xc1,0x08,0x50,0xc8,0xfd,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0x50,0xc8,0xfd,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_mov_b32 v255, 0xaf123456 ; encoding: [0x7c,0x0a,0x50,0xc8,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x50,0xc8,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v4, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x4e,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x04,0x05,0x4e,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v1, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x4e,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x05,0x4e,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v255, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x4e,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x05,0x4e,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v2, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x4e,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x02,0x05,0x4e,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v3, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x4e,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x03,0x05,0x4e,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, s105, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, s105, v3 ; encoding: [0x69,0x04,0x4e,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x69,0x04,0x4e,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, s1, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, s1, v3 ; encoding: [0x01,0x04,0x4e,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x04,0x4e,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, ttmp15, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0x4e,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0x04,0x4e,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, exec_hi, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0x4e,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0x04,0x4e,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, exec_lo, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0x4e,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0x04,0x4e,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, m0, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x4e,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0x04,0x4e,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, vcc_hi, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0x4e,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0x04,0x4e,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, vcc_lo, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0x4e,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0x04,0x4e,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0xaf123456, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, null, v3 ; encoding: [0xff,0x04,0x4e,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x4e,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, src_scc, v2, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x4e,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0x04,0x4e,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x4e,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0x4e,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x4e,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0x4e,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x4e,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x4e,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v4, v2, 0xaf123456 :: v_dual_mul_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x46,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x04,0x05,0x46,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v1, v2, 0xaf123456 :: v_dual_mul_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x46,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x05,0x46,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v255, v2, 0xaf123456 :: v_dual_mul_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x46,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x05,0x46,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v2, v2, 0xaf123456 :: v_dual_mul_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x46,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x02,0x05,0x46,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v3, v2, 0xaf123456 :: v_dual_mul_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x46,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x03,0x05,0x46,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, s105, v2, 0xaf123456 :: v_dual_mul_f32 v6, s105, v3 ; encoding: [0x69,0x04,0x46,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x69,0x04,0x46,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, s1, v2, 0xaf123456 :: v_dual_mul_f32 v6, s1, v3 ; encoding: [0x01,0x04,0x46,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x04,0x46,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, ttmp15, v2, 0xaf123456 :: v_dual_mul_f32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0x46,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0x04,0x46,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, exec_hi, v2, 0xaf123456 :: v_dual_mul_f32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0x46,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0x04,0x46,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, exec_lo, v2, 0xaf123456 :: v_dual_mul_f32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0x46,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0x04,0x46,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, m0, v2, 0xaf123456 :: v_dual_mul_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x46,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0x04,0x46,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, vcc_hi, v2, 0xaf123456 :: v_dual_mul_f32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0x46,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0x04,0x46,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, vcc_lo, v2, 0xaf123456 :: v_dual_mul_f32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0x46,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0x04,0x46,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0xaf123456, v2, 0xaf123456 :: v_dual_mul_f32 v6, null, v3 ; encoding: [0xff,0x04,0x46,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x46,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, src_scc, v2, 0xaf123456 :: v_dual_mul_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x46,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0x04,0x46,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_mul_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x46,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0x46,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_mul_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x46,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0x46,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_mul_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x46,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x46,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v4, v2, 0xaf123456 :: v_dual_sub_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x4a,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x04,0x05,0x4a,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v1, v2, 0xaf123456 :: v_dual_sub_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x4a,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x05,0x4a,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v255, v2, 0xaf123456 :: v_dual_sub_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x4a,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x05,0x4a,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v2, v2, 0xaf123456 :: v_dual_sub_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x4a,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x02,0x05,0x4a,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v3, v2, 0xaf123456 :: v_dual_sub_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x4a,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x03,0x05,0x4a,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, s105, v2, 0xaf123456 :: v_dual_sub_f32 v6, s105, v3 ; encoding: [0x69,0x04,0x4a,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x69,0x04,0x4a,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, s1, v2, 0xaf123456 :: v_dual_sub_f32 v6, s1, v3 ; encoding: [0x01,0x04,0x4a,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x04,0x4a,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, ttmp15, v2, 0xaf123456 :: v_dual_sub_f32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0x4a,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0x04,0x4a,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, exec_hi, v2, 0xaf123456 :: v_dual_sub_f32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0x4a,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0x04,0x4a,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, exec_lo, v2, 0xaf123456 :: v_dual_sub_f32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0x4a,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0x04,0x4a,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, m0, v2, 0xaf123456 :: v_dual_sub_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x4a,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0x04,0x4a,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, vcc_hi, v2, 0xaf123456 :: v_dual_sub_f32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0x4a,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0x04,0x4a,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, vcc_lo, v2, 0xaf123456 :: v_dual_sub_f32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0x4a,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0x04,0x4a,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0xaf123456, v2, 0xaf123456 :: v_dual_sub_f32 v6, null, v3 ; encoding: [0xff,0x04,0x4a,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x4a,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, src_scc, v2, 0xaf123456 :: v_dual_sub_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x4a,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0x04,0x4a,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_sub_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x4a,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0x4a,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_sub_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x4a,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0x4a,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_sub_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x4a,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x4a,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v4, v2, 0xaf123456 :: v_dual_subrev_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x4c,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x04,0x05,0x4c,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v1, v2, 0xaf123456 :: v_dual_subrev_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x4c,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x05,0x4c,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v255, v2, 0xaf123456 :: v_dual_subrev_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x4c,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x05,0x4c,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v2, v2, 0xaf123456 :: v_dual_subrev_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x4c,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x02,0x05,0x4c,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, v3, v2, 0xaf123456 :: v_dual_subrev_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x4c,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x03,0x05,0x4c,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, s105, v2, 0xaf123456 :: v_dual_subrev_f32 v6, s105, v3 ; encoding: [0x69,0x04,0x4c,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x69,0x04,0x4c,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, s1, v2, 0xaf123456 :: v_dual_subrev_f32 v6, s1, v3 ; encoding: [0x01,0x04,0x4c,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x04,0x4c,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, ttmp15, v2, 0xaf123456 :: v_dual_subrev_f32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0x4c,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0x04,0x4c,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, exec_hi, v2, 0xaf123456 :: v_dual_subrev_f32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0x4c,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0x04,0x4c,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, exec_lo, v2, 0xaf123456 :: v_dual_subrev_f32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0x4c,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0x04,0x4c,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, m0, v2, 0xaf123456 :: v_dual_subrev_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x4c,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0x04,0x4c,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, vcc_hi, v2, 0xaf123456 :: v_dual_subrev_f32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0x4c,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0x04,0x4c,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, vcc_lo, v2, 0xaf123456 :: v_dual_subrev_f32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0x4c,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0x04,0x4c,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0xaf123456, v2, 0xaf123456 :: v_dual_subrev_f32 v6, null, v3 ; encoding: [0xff,0x04,0x4c,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x4c,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, src_scc, v2, 0xaf123456 :: v_dual_subrev_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x4c,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0x04,0x4c,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, 0.5, v3, 0xaf123456 :: v_dual_subrev_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x4c,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0x4c,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v255, -1, v4, 0xaf123456 :: v_dual_subrev_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x4c,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0x4c,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v6, null, v5, 0xaf123456 :: v_dual_subrev_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x4c,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x4c,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, v4, v2 :: v_dual_add_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x08,0xc8,0x01,0x07,0x06,0xff]
+0x04,0x05,0x08,0xc8,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v1, v2 :: v_dual_add_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x08,0xc8,0xff,0x07,0x06,0xff]
+0x01,0x05,0x08,0xc8,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v255, v2 :: v_dual_add_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x08,0xc8,0x02,0x07,0x06,0xff]
+0xff,0x05,0x08,0xc8,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v2, v2 :: v_dual_add_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x08,0xc8,0x03,0x07,0x06,0xff]
+0x02,0x05,0x08,0xc8,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v3, v2 :: v_dual_add_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x08,0xc8,0x04,0x07,0x06,0xff]
+0x03,0x05,0x08,0xc8,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, s105, v2 :: v_dual_add_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x08,0xc8,0x01,0x06,0x06,0xff]
+0x69,0x04,0x08,0xc8,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, s1, v2 :: v_dual_add_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x08,0xc8,0x69,0x06,0x06,0xff]
+0x01,0x04,0x08,0xc8,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, ttmp15, v2 :: v_dual_add_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x08,0xc8,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x08,0xc8,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, exec_hi, v2 :: v_dual_add_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x08,0xc8,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x08,0xc8,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, exec_lo, v2 :: v_dual_add_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x08,0xc8,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x08,0xc8,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, m0, v2 :: v_dual_add_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x08,0xc8,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x08,0xc8,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, vcc_hi, v2 :: v_dual_add_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x08,0xc8,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x08,0xc8,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, vcc_lo, v2 :: v_dual_add_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x08,0xc8,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x08,0xc8,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, 0xaf123456, v2 :: v_dual_add_f32 v6, null, v3 ; encoding: [0xff,0x04,0x08,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x08,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, src_scc, v2 :: v_dual_add_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x08,0xc8,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x08,0xc8,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_add_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x08,0xc8,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x08,0xc8,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, -1, v4 :: v_dual_add_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x08,0xc8,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x08,0xc8,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v6, null, v5 :: v_dual_add_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x08,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x08,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, v4, v2 :: v_dual_add_nc_u32 v6, v1, v3 ; encoding: [0x04,0x05,0x20,0xc8,0x01,0x07,0x06,0xff]
+0x04,0x05,0x20,0xc8,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v1, v2 :: v_dual_add_nc_u32 v6, v255, v3 ; encoding: [0x01,0x05,0x20,0xc8,0xff,0x07,0x06,0xff]
+0x01,0x05,0x20,0xc8,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v255, v2 :: v_dual_add_nc_u32 v6, v2, v3 ; encoding: [0xff,0x05,0x20,0xc8,0x02,0x07,0x06,0xff]
+0xff,0x05,0x20,0xc8,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v2, v2 :: v_dual_add_nc_u32 v6, v3, v3 ; encoding: [0x02,0x05,0x20,0xc8,0x03,0x07,0x06,0xff]
+0x02,0x05,0x20,0xc8,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v3, v2 :: v_dual_add_nc_u32 v6, v4, v3 ; encoding: [0x03,0x05,0x20,0xc8,0x04,0x07,0x06,0xff]
+0x03,0x05,0x20,0xc8,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, s105, v2 :: v_dual_add_nc_u32 v6, s1, v3 ; encoding: [0x69,0x04,0x20,0xc8,0x01,0x06,0x06,0xff]
+0x69,0x04,0x20,0xc8,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, s1, v2 :: v_dual_add_nc_u32 v6, s105, v3 ; encoding: [0x01,0x04,0x20,0xc8,0x69,0x06,0x06,0xff]
+0x01,0x04,0x20,0xc8,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, ttmp15, v2 :: v_dual_add_nc_u32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x20,0xc8,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x20,0xc8,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, exec_hi, v2 :: v_dual_add_nc_u32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x20,0xc8,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x20,0xc8,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, exec_lo, v2 :: v_dual_add_nc_u32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x20,0xc8,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x20,0xc8,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, m0, v2 :: v_dual_add_nc_u32 v6, m0, v3 ; encoding: [0x7d,0x04,0x20,0xc8,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x20,0xc8,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, vcc_hi, v2 :: v_dual_add_nc_u32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x20,0xc8,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x20,0xc8,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, vcc_lo, v2 :: v_dual_add_nc_u32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x20,0xc8,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x20,0xc8,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, 0xaf123456, v2 :: v_dual_add_nc_u32 v6, null, v3 ; encoding: [0xff,0x04,0x20,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x20,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, src_scc, v2 :: v_dual_add_nc_u32 v6, -1, v3 ; encoding: [0xfd,0x04,0x20,0xc8,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x20,0xc8,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_add_nc_u32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x20,0xc8,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x20,0xc8,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, -1, v4 :: v_dual_add_nc_u32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x20,0xc8,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x20,0xc8,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v6, null, v5 :: v_dual_add_nc_u32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x20,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x20,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, v4, v2 :: v_dual_and_b32 v6, v1, v3 ; encoding: [0x04,0x05,0x24,0xc8,0x01,0x07,0x06,0xff]
+0x04,0x05,0x24,0xc8,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v1, v2 :: v_dual_and_b32 v6, v255, v3 ; encoding: [0x01,0x05,0x24,0xc8,0xff,0x07,0x06,0xff]
+0x01,0x05,0x24,0xc8,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v255, v2 :: v_dual_and_b32 v6, v2, v3 ; encoding: [0xff,0x05,0x24,0xc8,0x02,0x07,0x06,0xff]
+0xff,0x05,0x24,0xc8,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v2, v2 :: v_dual_and_b32 v6, v3, v3 ; encoding: [0x02,0x05,0x24,0xc8,0x03,0x07,0x06,0xff]
+0x02,0x05,0x24,0xc8,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v3, v2 :: v_dual_and_b32 v6, v4, v3 ; encoding: [0x03,0x05,0x24,0xc8,0x04,0x07,0x06,0xff]
+0x03,0x05,0x24,0xc8,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, s105, v2 :: v_dual_and_b32 v6, s1, v3 ; encoding: [0x69,0x04,0x24,0xc8,0x01,0x06,0x06,0xff]
+0x69,0x04,0x24,0xc8,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, s1, v2 :: v_dual_and_b32 v6, s105, v3 ; encoding: [0x01,0x04,0x24,0xc8,0x69,0x06,0x06,0xff]
+0x01,0x04,0x24,0xc8,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, ttmp15, v2 :: v_dual_and_b32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x24,0xc8,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x24,0xc8,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, exec_hi, v2 :: v_dual_and_b32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x24,0xc8,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x24,0xc8,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, exec_lo, v2 :: v_dual_and_b32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x24,0xc8,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x24,0xc8,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, m0, v2 :: v_dual_and_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0x24,0xc8,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x24,0xc8,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, vcc_hi, v2 :: v_dual_and_b32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x24,0xc8,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x24,0xc8,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, vcc_lo, v2 :: v_dual_and_b32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x24,0xc8,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x24,0xc8,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, 0xaf123456, v2 :: v_dual_and_b32 v6, null, v3 ; encoding: [0xff,0x04,0x24,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x24,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, src_scc, v2 :: v_dual_and_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0x24,0xc8,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x24,0xc8,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_and_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x24,0xc8,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x24,0xc8,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, -1, v4 :: v_dual_and_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x24,0xc8,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x24,0xc8,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v6, null, v5 :: v_dual_and_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x24,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x24,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, v4, v2 :: v_dual_cndmask_b32 v6, v1, v3 ; encoding: [0x04,0x05,0x12,0xc8,0x01,0x07,0x06,0xff]
+0x04,0x05,0x12,0xc8,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v1, v2 :: v_dual_cndmask_b32 v6, v255, v3 ; encoding: [0x01,0x05,0x12,0xc8,0xff,0x07,0x06,0xff]
+0x01,0x05,0x12,0xc8,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v255, v2 :: v_dual_cndmask_b32 v6, v2, v3 ; encoding: [0xff,0x05,0x12,0xc8,0x02,0x07,0x06,0xff]
+0xff,0x05,0x12,0xc8,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v2, v2 :: v_dual_cndmask_b32 v6, v3, v3 ; encoding: [0x02,0x05,0x12,0xc8,0x03,0x07,0x06,0xff]
+0x02,0x05,0x12,0xc8,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v3, v2 :: v_dual_cndmask_b32 v6, v4, v3 ; encoding: [0x03,0x05,0x12,0xc8,0x04,0x07,0x06,0xff]
+0x03,0x05,0x12,0xc8,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, s105, v2 :: v_dual_cndmask_b32 v6, s105, v3 ; encoding: [0x69,0x04,0x12,0xc8,0x69,0x06,0x06,0xff]
+0x69,0x04,0x12,0xc8,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, s1, v2 :: v_dual_cndmask_b32 v6, s1, v3 ; encoding: [0x01,0x04,0x12,0xc8,0x01,0x06,0x06,0xff]
+0x01,0x04,0x12,0xc8,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, ttmp15, v2 :: v_dual_cndmask_b32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0x12,0xc8,0x7b,0x06,0x06,0xff]
+0x7b,0x04,0x12,0xc8,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, exec_hi, v2 :: v_dual_cndmask_b32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0x12,0xc8,0x7f,0x06,0x06,0xff]
+0x7f,0x04,0x12,0xc8,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, exec_lo, v2 :: v_dual_cndmask_b32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0x12,0xc8,0x7e,0x06,0x06,0xff]
+0x7e,0x04,0x12,0xc8,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, m0, v2 :: v_dual_cndmask_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0x12,0xc8,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x12,0xc8,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, vcc_hi, v2 :: v_dual_cndmask_b32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0x12,0xc8,0x6b,0x06,0x06,0xff]
+0x6b,0x04,0x12,0xc8,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, vcc_lo, v2 :: v_dual_cndmask_b32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0x12,0xc8,0x6a,0x06,0x06,0xff]
+0x6a,0x04,0x12,0xc8,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, 0xaf123456, v2 :: v_dual_cndmask_b32 v6, null, v3 ; encoding: [0xff,0x04,0x12,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x12,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, src_scc, v2 :: v_dual_cndmask_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0x12,0xc8,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x12,0xc8,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_cndmask_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x12,0xc8,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x12,0xc8,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, -1, v4 :: v_dual_cndmask_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x12,0xc8,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x12,0xc8,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v6, null, v5 :: v_dual_cndmask_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x12,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x12,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, v4, v2 :: v_dual_fmaak_f32 v6, v1, v3, 0xaf123456 ; encoding: [0x04,0x05,0x02,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x04,0x05,0x02,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, v1, v2 :: v_dual_fmaak_f32 v6, v255, v3, 0xaf123456 ; encoding: [0x01,0x05,0x02,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x05,0x02,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, v255, v2 :: v_dual_fmaak_f32 v6, v2, v3, 0xaf123456 ; encoding: [0xff,0x05,0x02,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x05,0x02,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, v2, v2 :: v_dual_fmaak_f32 v6, v3, v3, 0xaf123456 ; encoding: [0x02,0x05,0x02,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x02,0x05,0x02,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, v3, v2 :: v_dual_fmaak_f32 v6, v4, v3, 0xaf123456 ; encoding: [0x03,0x05,0x02,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x03,0x05,0x02,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, s105, v2 :: v_dual_fmaak_f32 v6, s105, v3, 0xaf123456 ; encoding: [0x69,0x04,0x02,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x69,0x04,0x02,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, s1, v2 :: v_dual_fmaak_f32 v6, s1, v3, 0xaf123456 ; encoding: [0x01,0x04,0x02,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x04,0x02,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, ttmp15, v2 :: v_dual_fmaak_f32 v6, ttmp15, v3, 0xaf123456 ; encoding: [0x7b,0x04,0x02,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0x04,0x02,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, exec_hi, v2 :: v_dual_fmaak_f32 v6, exec_hi, v3, 0xaf123456 ; encoding: [0x7f,0x04,0x02,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0x04,0x02,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, exec_lo, v2 :: v_dual_fmaak_f32 v6, exec_lo, v3, 0xaf123456 ; encoding: [0x7e,0x04,0x02,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0x04,0x02,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, m0, v2 :: v_dual_fmaak_f32 v6, m0, v3, 0xaf123456 ; encoding: [0x7d,0x04,0x02,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0x04,0x02,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, vcc_hi, v2 :: v_dual_fmaak_f32 v6, vcc_hi, v3, 0xaf123456 ; encoding: [0x6b,0x04,0x02,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0x04,0x02,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, vcc_lo, v2 :: v_dual_fmaak_f32 v6, vcc_lo, v3, 0xaf123456 ; encoding: [0x6a,0x04,0x02,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0x04,0x02,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, null, v3, 0xaf123456 ; encoding: [0xff,0x04,0x02,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x02,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, src_scc, v2 :: v_dual_fmaak_f32 v6, -1, v3, 0xaf123456 ; encoding: [0xfd,0x04,0x02,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0x04,0x02,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_fmaak_f32 v6, 0.5, v2, 0xaf123456 ; encoding: [0xf0,0x06,0x02,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0x02,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, -1, v4 :: v_dual_fmaak_f32 v6, src_scc, v5, 0xaf123456 ; encoding: [0xc1,0x08,0x02,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0x02,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v6, null, v5 :: v_dual_fmaak_f32 v255, 0xaf123456, v4, 0xaf123456 ; encoding: [0x7c,0x0a,0x02,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x02,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, v4, v2 :: v_dual_fmac_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x00,0xc8,0x01,0x07,0x06,0xff]
+0x04,0x05,0x00,0xc8,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v1, v2 :: v_dual_fmac_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x00,0xc8,0xff,0x07,0x06,0xff]
+0x01,0x05,0x00,0xc8,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v255, v2 :: v_dual_fmac_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x00,0xc8,0x02,0x07,0x06,0xff]
+0xff,0x05,0x00,0xc8,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v2, v2 :: v_dual_fmac_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x00,0xc8,0x03,0x07,0x06,0xff]
+0x02,0x05,0x00,0xc8,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v3, v2 :: v_dual_fmac_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x00,0xc8,0x04,0x07,0x06,0xff]
+0x03,0x05,0x00,0xc8,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, s105, v2 :: v_dual_fmac_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x00,0xc8,0x01,0x06,0x06,0xff]
+0x69,0x04,0x00,0xc8,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, s1, v2 :: v_dual_fmac_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x00,0xc8,0x69,0x06,0x06,0xff]
+0x01,0x04,0x00,0xc8,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, ttmp15, v2 :: v_dual_fmac_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x00,0xc8,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x00,0xc8,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, exec_hi, v2 :: v_dual_fmac_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x00,0xc8,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x00,0xc8,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, exec_lo, v2 :: v_dual_fmac_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x00,0xc8,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x00,0xc8,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, m0, v2 :: v_dual_fmac_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x00,0xc8,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x00,0xc8,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, vcc_hi, v2 :: v_dual_fmac_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x00,0xc8,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x00,0xc8,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, vcc_lo, v2 :: v_dual_fmac_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x00,0xc8,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x00,0xc8,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, 0xaf123456, v2 :: v_dual_fmac_f32 v6, null, v3 ; encoding: [0xff,0x04,0x00,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x00,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, src_scc, v2 :: v_dual_fmac_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x00,0xc8,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x00,0xc8,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_fmac_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x00,0xc8,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x00,0xc8,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, -1, v4 :: v_dual_fmac_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x00,0xc8,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x00,0xc8,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v6, null, v5 :: v_dual_fmac_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x00,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x00,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, v4, v255 :: v_dual_fmamk_f32 v6, v1, 0xaf123456, v4 ; encoding: [0x04,0xff,0x05,0xc8,0x01,0x09,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x04,0xff,0x05,0xc8,0x01,0x09,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, v1, v255 :: v_dual_fmamk_f32 v6, v255, 0xaf123456, v4 ; encoding: [0x01,0xff,0x05,0xc8,0xff,0x09,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xff,0x05,0xc8,0xff,0x09,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, v255, v255 :: v_dual_fmamk_f32 v6, v2, 0xaf123456, v4 ; encoding: [0xff,0xff,0x05,0xc8,0x02,0x09,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xff,0x05,0xc8,0x02,0x09,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, v2, v255 :: v_dual_fmamk_f32 v6, v3, 0xaf123456, v4 ; encoding: [0x02,0xff,0x05,0xc8,0x03,0x09,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x02,0xff,0x05,0xc8,0x03,0x09,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, v3, v255 :: v_dual_fmamk_f32 v6, v4, 0xaf123456, v4 ; encoding: [0x03,0xff,0x05,0xc8,0x04,0x09,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x03,0xff,0x05,0xc8,0x04,0x09,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, s105, v255 :: v_dual_fmamk_f32 v6, s105, 0xaf123456, v4 ; encoding: [0x69,0xfe,0x05,0xc8,0x69,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x69,0xfe,0x05,0xc8,0x69,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, s1, v255 :: v_dual_fmamk_f32 v6, s1, 0xaf123456, v4 ; encoding: [0x01,0xfe,0x05,0xc8,0x01,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xfe,0x05,0xc8,0x01,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, ttmp15, v255 :: v_dual_fmamk_f32 v6, ttmp15, 0xaf123456, v4 ; encoding: [0x7b,0xfe,0x05,0xc8,0x7b,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0xfe,0x05,0xc8,0x7b,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, exec_hi, v255 :: v_dual_fmamk_f32 v6, exec_hi, 0xaf123456, v4 ; encoding: [0x7f,0xfe,0x05,0xc8,0x7f,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0xfe,0x05,0xc8,0x7f,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, exec_lo, v255 :: v_dual_fmamk_f32 v6, exec_lo, 0xaf123456, v4 ; encoding: [0x7e,0xfe,0x05,0xc8,0x7e,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0xfe,0x05,0xc8,0x7e,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, m0, v255 :: v_dual_fmamk_f32 v6, m0, 0xaf123456, v4 ; encoding: [0x7d,0xfe,0x05,0xc8,0x7d,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0xfe,0x05,0xc8,0x7d,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, vcc_hi, v255 :: v_dual_fmamk_f32 v6, vcc_hi, 0xaf123456, v4 ; encoding: [0x6b,0xfe,0x05,0xc8,0x6b,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0xfe,0x05,0xc8,0x6b,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, vcc_lo, v255 :: v_dual_fmamk_f32 v6, vcc_lo, 0xaf123456, v4 ; encoding: [0x6a,0xfe,0x05,0xc8,0x6a,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0xfe,0x05,0xc8,0x6a,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, null, 0xaf123456, v4 ; encoding: [0xff,0xfe,0x05,0xc8,0x7c,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x05,0xc8,0x7c,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, src_scc, v255 :: v_dual_fmamk_f32 v6, -1, 0xaf123456, v4 ; encoding: [0xfd,0xfe,0x05,0xc8,0xc1,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0xfe,0x05,0xc8,0xc1,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_fmamk_f32 v6, 0.5, 0xaf123456, v4 ; encoding: [0xf0,0x06,0x04,0xc8,0xf0,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0x04,0xc8,0xf0,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, -1, v4 :: v_dual_fmamk_f32 v6, src_scc, 0xaf123456, v4 ; encoding: [0xc1,0x08,0x04,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0x04,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v6, null, v5 :: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 ; encoding: [0x7c,0x0a,0x04,0xc8,0xff,0xfe,0xff,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x04,0xc8,0xff,0xfe,0xff,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, v4, v2 :: v_dual_lshlrev_b32 v6, v1, v3 ; encoding: [0x04,0x05,0x22,0xc8,0x01,0x07,0x06,0xff]
+0x04,0x05,0x22,0xc8,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v1, v2 :: v_dual_lshlrev_b32 v6, v255, v3 ; encoding: [0x01,0x05,0x22,0xc8,0xff,0x07,0x06,0xff]
+0x01,0x05,0x22,0xc8,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v255, v2 :: v_dual_lshlrev_b32 v6, v2, v3 ; encoding: [0xff,0x05,0x22,0xc8,0x02,0x07,0x06,0xff]
+0xff,0x05,0x22,0xc8,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v2, v2 :: v_dual_lshlrev_b32 v6, v3, v3 ; encoding: [0x02,0x05,0x22,0xc8,0x03,0x07,0x06,0xff]
+0x02,0x05,0x22,0xc8,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v3, v2 :: v_dual_lshlrev_b32 v6, v4, v3 ; encoding: [0x03,0x05,0x22,0xc8,0x04,0x07,0x06,0xff]
+0x03,0x05,0x22,0xc8,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, s105, v2 :: v_dual_lshlrev_b32 v6, s1, v3 ; encoding: [0x69,0x04,0x22,0xc8,0x01,0x06,0x06,0xff]
+0x69,0x04,0x22,0xc8,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, s1, v2 :: v_dual_lshlrev_b32 v6, s105, v3 ; encoding: [0x01,0x04,0x22,0xc8,0x69,0x06,0x06,0xff]
+0x01,0x04,0x22,0xc8,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, ttmp15, v2 :: v_dual_lshlrev_b32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x22,0xc8,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x22,0xc8,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, exec_hi, v2 :: v_dual_lshlrev_b32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x22,0xc8,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x22,0xc8,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, exec_lo, v2 :: v_dual_lshlrev_b32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x22,0xc8,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x22,0xc8,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, m0, v2 :: v_dual_lshlrev_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0x22,0xc8,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x22,0xc8,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, vcc_hi, v2 :: v_dual_lshlrev_b32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x22,0xc8,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x22,0xc8,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, vcc_lo, v2 :: v_dual_lshlrev_b32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x22,0xc8,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x22,0xc8,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, 0xaf123456, v2 :: v_dual_lshlrev_b32 v6, null, v3 ; encoding: [0xff,0x04,0x22,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x22,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, src_scc, v2 :: v_dual_lshlrev_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0x22,0xc8,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x22,0xc8,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_lshlrev_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x22,0xc8,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x22,0xc8,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, -1, v4 :: v_dual_lshlrev_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x22,0xc8,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x22,0xc8,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v6, null, v5 :: v_dual_lshlrev_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x22,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x22,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, v4, v2 :: v_dual_max_num_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x14,0xc8,0x01,0x07,0x06,0xff]
+0x04,0x05,0x14,0xc8,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v1, v2 :: v_dual_max_num_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x14,0xc8,0xff,0x07,0x06,0xff]
+0x01,0x05,0x14,0xc8,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v255, v2 :: v_dual_max_num_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x14,0xc8,0x02,0x07,0x06,0xff]
+0xff,0x05,0x14,0xc8,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v2, v2 :: v_dual_max_num_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x14,0xc8,0x03,0x07,0x06,0xff]
+0x02,0x05,0x14,0xc8,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v3, v2 :: v_dual_max_num_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x14,0xc8,0x04,0x07,0x06,0xff]
+0x03,0x05,0x14,0xc8,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, s105, v2 :: v_dual_max_num_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x14,0xc8,0x01,0x06,0x06,0xff]
+0x69,0x04,0x14,0xc8,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, s1, v2 :: v_dual_max_num_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x14,0xc8,0x69,0x06,0x06,0xff]
+0x01,0x04,0x14,0xc8,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, ttmp15, v2 :: v_dual_max_num_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x14,0xc8,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x14,0xc8,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, exec_hi, v2 :: v_dual_max_num_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x14,0xc8,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x14,0xc8,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, exec_lo, v2 :: v_dual_max_num_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x14,0xc8,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x14,0xc8,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, m0, v2 :: v_dual_max_num_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x14,0xc8,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x14,0xc8,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, vcc_hi, v2 :: v_dual_max_num_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x14,0xc8,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x14,0xc8,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, vcc_lo, v2 :: v_dual_max_num_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x14,0xc8,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x14,0xc8,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, 0xaf123456, v2 :: v_dual_max_num_f32 v6, null, v3 ; encoding: [0xff,0x04,0x14,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x14,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, src_scc, v2 :: v_dual_max_num_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x14,0xc8,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x14,0xc8,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_max_num_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x14,0xc8,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x14,0xc8,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, -1, v4 :: v_dual_max_num_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x14,0xc8,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x14,0xc8,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v6, null, v5 :: v_dual_max_num_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x14,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x14,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, v4, v2 :: v_dual_min_num_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x16,0xc8,0x01,0x07,0x06,0xff]
+0x04,0x05,0x16,0xc8,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v1, v2 :: v_dual_min_num_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x16,0xc8,0xff,0x07,0x06,0xff]
+0x01,0x05,0x16,0xc8,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v255, v2 :: v_dual_min_num_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x16,0xc8,0x02,0x07,0x06,0xff]
+0xff,0x05,0x16,0xc8,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v2, v2 :: v_dual_min_num_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x16,0xc8,0x03,0x07,0x06,0xff]
+0x02,0x05,0x16,0xc8,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v3, v2 :: v_dual_min_num_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x16,0xc8,0x04,0x07,0x06,0xff]
+0x03,0x05,0x16,0xc8,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, s105, v2 :: v_dual_min_num_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x16,0xc8,0x01,0x06,0x06,0xff]
+0x69,0x04,0x16,0xc8,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, s1, v2 :: v_dual_min_num_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x16,0xc8,0x69,0x06,0x06,0xff]
+0x01,0x04,0x16,0xc8,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, ttmp15, v2 :: v_dual_min_num_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x16,0xc8,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x16,0xc8,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, exec_hi, v2 :: v_dual_min_num_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x16,0xc8,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x16,0xc8,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, exec_lo, v2 :: v_dual_min_num_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x16,0xc8,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x16,0xc8,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, m0, v2 :: v_dual_min_num_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x16,0xc8,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x16,0xc8,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, vcc_hi, v2 :: v_dual_min_num_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x16,0xc8,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x16,0xc8,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, vcc_lo, v2 :: v_dual_min_num_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x16,0xc8,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x16,0xc8,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, 0xaf123456, v2 :: v_dual_min_num_f32 v6, null, v3 ; encoding: [0xff,0x04,0x16,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x16,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, src_scc, v2 :: v_dual_min_num_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x16,0xc8,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x16,0xc8,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_min_num_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x16,0xc8,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x16,0xc8,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, -1, v4 :: v_dual_min_num_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x16,0xc8,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x16,0xc8,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v6, null, v5 :: v_dual_min_num_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x16,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x16,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, v4, v255 :: v_dual_mov_b32 v6, v1 ; encoding: [0x04,0xff,0x11,0xc8,0x01,0x01,0x06,0xff]
+0x04,0xff,0x11,0xc8,0x01,0x01,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v1, v255 :: v_dual_mov_b32 v6, v255 ; encoding: [0x01,0xff,0x11,0xc8,0xff,0x01,0x06,0xff]
+0x01,0xff,0x11,0xc8,0xff,0x01,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v255, v255 :: v_dual_mov_b32 v6, v2 ; encoding: [0xff,0xff,0x11,0xc8,0x02,0x01,0x06,0xff]
+0xff,0xff,0x11,0xc8,0x02,0x01,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v2, v255 :: v_dual_mov_b32 v6, v3 ; encoding: [0x02,0xff,0x11,0xc8,0x03,0x01,0x06,0xff]
+0x02,0xff,0x11,0xc8,0x03,0x01,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v3, v255 :: v_dual_mov_b32 v6, v4 ; encoding: [0x03,0xff,0x11,0xc8,0x04,0x01,0x06,0xff]
+0x03,0xff,0x11,0xc8,0x04,0x01,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, s105, v255 :: v_dual_mov_b32 v6, s1 ; encoding: [0x69,0xfe,0x11,0xc8,0x01,0x00,0x06,0xff]
+0x69,0xfe,0x11,0xc8,0x01,0x00,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, s1, v255 :: v_dual_mov_b32 v6, s105 ; encoding: [0x01,0xfe,0x11,0xc8,0x69,0x00,0x06,0xff]
+0x01,0xfe,0x11,0xc8,0x69,0x00,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, ttmp15, v255 :: v_dual_mov_b32 v6, vcc_lo ; encoding: [0x7b,0xfe,0x11,0xc8,0x6a,0x00,0x06,0xff]
+0x7b,0xfe,0x11,0xc8,0x6a,0x00,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, exec_hi, v255 :: v_dual_mov_b32 v6, vcc_hi ; encoding: [0x7f,0xfe,0x11,0xc8,0x6b,0x00,0x06,0xff]
+0x7f,0xfe,0x11,0xc8,0x6b,0x00,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, exec_lo, v255 :: v_dual_mov_b32 v6, ttmp15 ; encoding: [0x7e,0xfe,0x11,0xc8,0x7b,0x00,0x06,0xff]
+0x7e,0xfe,0x11,0xc8,0x7b,0x00,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, m0, v255 :: v_dual_mov_b32 v6, m0 ; encoding: [0x7d,0xfe,0x11,0xc8,0x7d,0x00,0x06,0xff]
+0x7d,0xfe,0x11,0xc8,0x7d,0x00,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, vcc_hi, v255 :: v_dual_mov_b32 v6, exec_lo ; encoding: [0x6b,0xfe,0x11,0xc8,0x7e,0x00,0x06,0xff]
+0x6b,0xfe,0x11,0xc8,0x7e,0x00,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, vcc_lo, v255 :: v_dual_mov_b32 v6, exec_hi ; encoding: [0x6a,0xfe,0x11,0xc8,0x7f,0x00,0x06,0xff]
+0x6a,0xfe,0x11,0xc8,0x7f,0x00,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, 0xaf123456, v255 :: v_dual_mov_b32 v6, null ; encoding: [0xff,0xfe,0x11,0xc8,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x11,0xc8,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, src_scc, v255 :: v_dual_mov_b32 v6, -1 ; encoding: [0xfd,0xfe,0x11,0xc8,0xc1,0x00,0x06,0xff]
+0xfd,0xfe,0x11,0xc8,0xc1,0x00,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_mov_b32 v6, 0.5 ; encoding: [0xf0,0x06,0x10,0xc8,0xf0,0x00,0x06,0xff]
+0xf0,0x06,0x10,0xc8,0xf0,0x00,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, -1, v4 :: v_dual_mov_b32 v6, src_scc ; encoding: [0xc1,0x08,0x10,0xc8,0xfd,0x00,0x06,0xff]
+0xc1,0x08,0x10,0xc8,0xfd,0x00,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v6, null, v5 :: v_dual_mov_b32 v255, 0xaf123456 ; encoding: [0x7c,0x0a,0x10,0xc8,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x10,0xc8,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, v4, v2 :: v_dual_mul_dx9_zero_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x0e,0xc8,0x01,0x07,0x06,0xff]
+0x04,0x05,0x0e,0xc8,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v1, v2 :: v_dual_mul_dx9_zero_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x0e,0xc8,0xff,0x07,0x06,0xff]
+0x01,0x05,0x0e,0xc8,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v255, v2 :: v_dual_mul_dx9_zero_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x0e,0xc8,0x02,0x07,0x06,0xff]
+0xff,0x05,0x0e,0xc8,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v2, v2 :: v_dual_mul_dx9_zero_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x0e,0xc8,0x03,0x07,0x06,0xff]
+0x02,0x05,0x0e,0xc8,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v3, v2 :: v_dual_mul_dx9_zero_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x0e,0xc8,0x04,0x07,0x06,0xff]
+0x03,0x05,0x0e,0xc8,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, s105, v2 :: v_dual_mul_dx9_zero_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x0e,0xc8,0x01,0x06,0x06,0xff]
+0x69,0x04,0x0e,0xc8,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, s1, v2 :: v_dual_mul_dx9_zero_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x0e,0xc8,0x69,0x06,0x06,0xff]
+0x01,0x04,0x0e,0xc8,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, ttmp15, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x0e,0xc8,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x0e,0xc8,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, exec_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x0e,0xc8,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x0e,0xc8,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, exec_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x0e,0xc8,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x0e,0xc8,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, m0, v2 :: v_dual_mul_dx9_zero_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x0e,0xc8,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x0e,0xc8,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, vcc_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x0e,0xc8,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x0e,0xc8,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, vcc_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x0e,0xc8,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x0e,0xc8,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, 0xaf123456, v2 :: v_dual_mul_dx9_zero_f32 v6, null, v3 ; encoding: [0xff,0x04,0x0e,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x0e,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, src_scc, v2 :: v_dual_mul_dx9_zero_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x0e,0xc8,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x0e,0xc8,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_mul_dx9_zero_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x0e,0xc8,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x0e,0xc8,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, -1, v4 :: v_dual_mul_dx9_zero_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x0e,0xc8,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x0e,0xc8,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v6, null, v5 :: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x0e,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x0e,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, v4, v2 :: v_dual_mul_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x06,0xc8,0x01,0x07,0x06,0xff]
+0x04,0x05,0x06,0xc8,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v1, v2 :: v_dual_mul_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x06,0xc8,0xff,0x07,0x06,0xff]
+0x01,0x05,0x06,0xc8,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v255, v2 :: v_dual_mul_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x06,0xc8,0x02,0x07,0x06,0xff]
+0xff,0x05,0x06,0xc8,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v2, v2 :: v_dual_mul_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x06,0xc8,0x03,0x07,0x06,0xff]
+0x02,0x05,0x06,0xc8,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v3, v2 :: v_dual_mul_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x06,0xc8,0x04,0x07,0x06,0xff]
+0x03,0x05,0x06,0xc8,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, s105, v2 :: v_dual_mul_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x06,0xc8,0x01,0x06,0x06,0xff]
+0x69,0x04,0x06,0xc8,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, s1, v2 :: v_dual_mul_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x06,0xc8,0x69,0x06,0x06,0xff]
+0x01,0x04,0x06,0xc8,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, ttmp15, v2 :: v_dual_mul_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x06,0xc8,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x06,0xc8,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, exec_hi, v2 :: v_dual_mul_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x06,0xc8,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x06,0xc8,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, exec_lo, v2 :: v_dual_mul_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x06,0xc8,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x06,0xc8,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, m0, v2 :: v_dual_mul_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x06,0xc8,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x06,0xc8,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, vcc_hi, v2 :: v_dual_mul_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x06,0xc8,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x06,0xc8,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, vcc_lo, v2 :: v_dual_mul_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x06,0xc8,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x06,0xc8,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, 0xaf123456, v2 :: v_dual_mul_f32 v6, null, v3 ; encoding: [0xff,0x04,0x06,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x06,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, src_scc, v2 :: v_dual_mul_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x06,0xc8,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x06,0xc8,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_mul_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x06,0xc8,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x06,0xc8,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, -1, v4 :: v_dual_mul_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x06,0xc8,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x06,0xc8,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v6, null, v5 :: v_dual_mul_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x06,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x06,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, v4, v2 :: v_dual_sub_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x0a,0xc8,0x01,0x07,0x06,0xff]
+0x04,0x05,0x0a,0xc8,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v1, v2 :: v_dual_sub_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x0a,0xc8,0xff,0x07,0x06,0xff]
+0x01,0x05,0x0a,0xc8,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v255, v2 :: v_dual_sub_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x0a,0xc8,0x02,0x07,0x06,0xff]
+0xff,0x05,0x0a,0xc8,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v2, v2 :: v_dual_sub_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x0a,0xc8,0x03,0x07,0x06,0xff]
+0x02,0x05,0x0a,0xc8,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v3, v2 :: v_dual_sub_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x0a,0xc8,0x04,0x07,0x06,0xff]
+0x03,0x05,0x0a,0xc8,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, s105, v2 :: v_dual_sub_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x0a,0xc8,0x01,0x06,0x06,0xff]
+0x69,0x04,0x0a,0xc8,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, s1, v2 :: v_dual_sub_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x0a,0xc8,0x69,0x06,0x06,0xff]
+0x01,0x04,0x0a,0xc8,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, ttmp15, v2 :: v_dual_sub_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x0a,0xc8,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x0a,0xc8,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, exec_hi, v2 :: v_dual_sub_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x0a,0xc8,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x0a,0xc8,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, exec_lo, v2 :: v_dual_sub_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x0a,0xc8,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x0a,0xc8,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, m0, v2 :: v_dual_sub_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x0a,0xc8,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x0a,0xc8,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, vcc_hi, v2 :: v_dual_sub_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x0a,0xc8,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x0a,0xc8,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, vcc_lo, v2 :: v_dual_sub_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x0a,0xc8,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x0a,0xc8,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, 0xaf123456, v2 :: v_dual_sub_f32 v6, null, v3 ; encoding: [0xff,0x04,0x0a,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x0a,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, src_scc, v2 :: v_dual_sub_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x0a,0xc8,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x0a,0xc8,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_sub_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x0a,0xc8,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x0a,0xc8,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, -1, v4 :: v_dual_sub_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x0a,0xc8,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x0a,0xc8,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v6, null, v5 :: v_dual_sub_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x0a,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x0a,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, v4, v2 :: v_dual_subrev_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x0c,0xc8,0x01,0x07,0x06,0xff]
+0x04,0x05,0x0c,0xc8,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v1, v2 :: v_dual_subrev_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x0c,0xc8,0xff,0x07,0x06,0xff]
+0x01,0x05,0x0c,0xc8,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v255, v2 :: v_dual_subrev_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x0c,0xc8,0x02,0x07,0x06,0xff]
+0xff,0x05,0x0c,0xc8,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v2, v2 :: v_dual_subrev_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x0c,0xc8,0x03,0x07,0x06,0xff]
+0x02,0x05,0x0c,0xc8,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, v3, v2 :: v_dual_subrev_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x0c,0xc8,0x04,0x07,0x06,0xff]
+0x03,0x05,0x0c,0xc8,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, s105, v2 :: v_dual_subrev_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x0c,0xc8,0x01,0x06,0x06,0xff]
+0x69,0x04,0x0c,0xc8,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, s1, v2 :: v_dual_subrev_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x0c,0xc8,0x69,0x06,0x06,0xff]
+0x01,0x04,0x0c,0xc8,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, ttmp15, v2 :: v_dual_subrev_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x0c,0xc8,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x0c,0xc8,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, exec_hi, v2 :: v_dual_subrev_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x0c,0xc8,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x0c,0xc8,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, exec_lo, v2 :: v_dual_subrev_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x0c,0xc8,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x0c,0xc8,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, m0, v2 :: v_dual_subrev_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x0c,0xc8,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x0c,0xc8,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, vcc_hi, v2 :: v_dual_subrev_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x0c,0xc8,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x0c,0xc8,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, vcc_lo, v2 :: v_dual_subrev_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x0c,0xc8,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x0c,0xc8,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, 0xaf123456, v2 :: v_dual_subrev_f32 v6, null, v3 ; encoding: [0xff,0x04,0x0c,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x0c,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmac_f32 v255, src_scc, v2 :: v_dual_subrev_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x0c,0xc8,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x0c,0xc8,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, 0.5, v3 :: v_dual_subrev_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x0c,0xc8,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x0c,0xc8,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v255, -1, v4 :: v_dual_subrev_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x0c,0xc8,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x0c,0xc8,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_fmac_f32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x0c,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x0c,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_add_f32 v6, v1, v255 ; encoding: [0x04,0xff,0x89,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x04,0xff,0x89,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_add_f32 v6, v255, v255 ; encoding: [0x01,0xff,0x89,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xff,0x89,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_add_f32 v6, v2, v255 ; encoding: [0xff,0xff,0x89,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xff,0x89,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_add_f32 v6, v3, v255 ; encoding: [0x02,0xff,0x89,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x02,0xff,0x89,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_add_f32 v6, v4, v255 ; encoding: [0x03,0xff,0x89,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x03,0xff,0x89,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, s105, 0xaf123456, v255 :: v_dual_add_f32 v6, s105, v255 ; encoding: [0x69,0xfe,0x89,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x69,0xfe,0x89,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, s1, 0xaf123456, v255 :: v_dual_add_f32 v6, s1, v255 ; encoding: [0x01,0xfe,0x89,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xfe,0x89,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, ttmp15, 0xaf123456, v255 :: v_dual_add_f32 v6, ttmp15, v255 ; encoding: [0x7b,0xfe,0x89,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0xfe,0x89,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, exec_hi, 0xaf123456, v255 :: v_dual_add_f32 v6, exec_hi, v255 ; encoding: [0x7f,0xfe,0x89,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0xfe,0x89,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, exec_lo, 0xaf123456, v255 :: v_dual_add_f32 v6, exec_lo, v255 ; encoding: [0x7e,0xfe,0x89,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0xfe,0x89,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, m0, 0xaf123456, v255 :: v_dual_add_f32 v6, m0, v255 ; encoding: [0x7d,0xfe,0x89,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0xfe,0x89,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, vcc_hi, 0xaf123456, v255 :: v_dual_add_f32 v6, vcc_hi, v255 ; encoding: [0x6b,0xfe,0x89,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0xfe,0x89,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, vcc_lo, 0xaf123456, v255 :: v_dual_add_f32 v6, vcc_lo, v255 ; encoding: [0x6a,0xfe,0x89,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0xfe,0x89,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_add_f32 v6, null, v255 ; encoding: [0xff,0xfe,0x89,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x89,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, src_scc, 0xaf123456, v255 :: v_dual_add_f32 v6, -1, v255 ; encoding: [0xfd,0xfe,0x89,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0xfe,0x89,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_add_f32 v6, 0.5, v3 ; encoding: [0xf0,0xfe,0x89,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0xfe,0x89,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_add_f32 v6, src_scc, v4 ; encoding: [0xc1,0xfe,0x89,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0xfe,0x89,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_add_f32 v255, 0xaf123456, v5 ; encoding: [0x7c,0x08,0x88,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x08,0x88,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, v1, v255 ; encoding: [0x04,0xff,0xa1,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x04,0xff,0xa1,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, v255, v255 ; encoding: [0x01,0xff,0xa1,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xff,0xa1,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, v2, v255 ; encoding: [0xff,0xff,0xa1,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xff,0xa1,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, v3, v255 ; encoding: [0x02,0xff,0xa1,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x02,0xff,0xa1,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, v4, v255 ; encoding: [0x03,0xff,0xa1,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x03,0xff,0xa1,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, s105, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, s105, v255 ; encoding: [0x69,0xfe,0xa1,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x69,0xfe,0xa1,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, s1, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, s1, v255 ; encoding: [0x01,0xfe,0xa1,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xfe,0xa1,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, ttmp15, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, ttmp15, v255 ; encoding: [0x7b,0xfe,0xa1,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0xfe,0xa1,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, exec_hi, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, exec_hi, v255 ; encoding: [0x7f,0xfe,0xa1,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0xfe,0xa1,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, exec_lo, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, exec_lo, v255 ; encoding: [0x7e,0xfe,0xa1,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0xfe,0xa1,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, m0, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, m0, v255 ; encoding: [0x7d,0xfe,0xa1,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0xfe,0xa1,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, vcc_hi, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, vcc_hi, v255 ; encoding: [0x6b,0xfe,0xa1,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0xfe,0xa1,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, vcc_lo, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, vcc_lo, v255 ; encoding: [0x6a,0xfe,0xa1,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0xfe,0xa1,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, null, v255 ; encoding: [0xff,0xfe,0xa1,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xa1,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, src_scc, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, -1, v255 ; encoding: [0xfd,0xfe,0xa1,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0xfe,0xa1,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, 0.5, v3 ; encoding: [0xf0,0xfe,0xa1,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0xfe,0xa1,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_add_nc_u32 v6, src_scc, v4 ; encoding: [0xc1,0xfe,0xa1,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0xfe,0xa1,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_add_nc_u32 v255, 0xaf123456, v5 ; encoding: [0x7c,0x08,0xa0,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x08,0xa0,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_and_b32 v6, v1, v255 ; encoding: [0x04,0xff,0xa5,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x04,0xff,0xa5,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_and_b32 v6, v255, v255 ; encoding: [0x01,0xff,0xa5,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xff,0xa5,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_and_b32 v6, v2, v255 ; encoding: [0xff,0xff,0xa5,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xff,0xa5,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_and_b32 v6, v3, v255 ; encoding: [0x02,0xff,0xa5,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x02,0xff,0xa5,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_and_b32 v6, v4, v255 ; encoding: [0x03,0xff,0xa5,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x03,0xff,0xa5,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, s105, 0xaf123456, v255 :: v_dual_and_b32 v6, s105, v255 ; encoding: [0x69,0xfe,0xa5,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x69,0xfe,0xa5,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, s1, 0xaf123456, v255 :: v_dual_and_b32 v6, s1, v255 ; encoding: [0x01,0xfe,0xa5,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xfe,0xa5,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, ttmp15, 0xaf123456, v255 :: v_dual_and_b32 v6, ttmp15, v255 ; encoding: [0x7b,0xfe,0xa5,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0xfe,0xa5,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, exec_hi, 0xaf123456, v255 :: v_dual_and_b32 v6, exec_hi, v255 ; encoding: [0x7f,0xfe,0xa5,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0xfe,0xa5,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, exec_lo, 0xaf123456, v255 :: v_dual_and_b32 v6, exec_lo, v255 ; encoding: [0x7e,0xfe,0xa5,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0xfe,0xa5,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, m0, 0xaf123456, v255 :: v_dual_and_b32 v6, m0, v255 ; encoding: [0x7d,0xfe,0xa5,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0xfe,0xa5,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, vcc_hi, 0xaf123456, v255 :: v_dual_and_b32 v6, vcc_hi, v255 ; encoding: [0x6b,0xfe,0xa5,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0xfe,0xa5,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, vcc_lo, 0xaf123456, v255 :: v_dual_and_b32 v6, vcc_lo, v255 ; encoding: [0x6a,0xfe,0xa5,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0xfe,0xa5,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_and_b32 v6, null, v255 ; encoding: [0xff,0xfe,0xa5,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xa5,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, src_scc, 0xaf123456, v255 :: v_dual_and_b32 v6, -1, v255 ; encoding: [0xfd,0xfe,0xa5,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0xfe,0xa5,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_and_b32 v6, 0.5, v3 ; encoding: [0xf0,0xfe,0xa5,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0xfe,0xa5,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_and_b32 v6, src_scc, v4 ; encoding: [0xc1,0xfe,0xa5,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0xfe,0xa5,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_and_b32 v255, 0xaf123456, v5 ; encoding: [0x7c,0x08,0xa4,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x08,0xa4,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_cndmask_b32 v6, v1, v255 ; encoding: [0x04,0xff,0x93,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x04,0xff,0x93,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_cndmask_b32 v6, v255, v255 ; encoding: [0x01,0xff,0x93,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xff,0x93,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_cndmask_b32 v6, v2, v255 ; encoding: [0xff,0xff,0x93,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xff,0x93,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_cndmask_b32 v6, v3, v255 ; encoding: [0x02,0xff,0x93,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x02,0xff,0x93,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_cndmask_b32 v6, v4, v255 ; encoding: [0x03,0xff,0x93,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x03,0xff,0x93,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_cndmask_b32 v6, null, v255 ; encoding: [0xff,0xfe,0x93,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x93,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_cndmask_b32 v6, -1, v3 ; encoding: [0xf0,0xfe,0x93,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0xfe,0x93,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_cndmask_b32 v6, 0.5, v4 ; encoding: [0xc1,0xfe,0x93,0xc8,0xf0,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0xfe,0x93,0xc8,0xf0,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_cndmask_b32 v255, 0xaf123456, v5 ; encoding: [0x7c,0x08,0x92,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x08,0x92,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, v1, v255, 0xaf123456 ; encoding: [0x04,0xff,0x83,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x04,0xff,0x83,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, v255, v255, 0xaf123456 ; encoding: [0x01,0xff,0x83,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xff,0x83,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, v2, v255, 0xaf123456 ; encoding: [0xff,0xff,0x83,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xff,0x83,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, v3, v255, 0xaf123456 ; encoding: [0x02,0xff,0x83,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x02,0xff,0x83,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, v4, v255, 0xaf123456 ; encoding: [0x03,0xff,0x83,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x03,0xff,0x83,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, s105, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, s105, v255, 0xaf123456 ; encoding: [0x69,0xfe,0x83,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x69,0xfe,0x83,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, s1, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, s1, v255, 0xaf123456 ; encoding: [0x01,0xfe,0x83,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xfe,0x83,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, ttmp15, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, ttmp15, v255, 0xaf123456 ; encoding: [0x7b,0xfe,0x83,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0xfe,0x83,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, exec_hi, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, exec_hi, v255, 0xaf123456 ; encoding: [0x7f,0xfe,0x83,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0xfe,0x83,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, exec_lo, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, exec_lo, v255, 0xaf123456 ; encoding: [0x7e,0xfe,0x83,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0xfe,0x83,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, m0, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, m0, v255, 0xaf123456 ; encoding: [0x7d,0xfe,0x83,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0xfe,0x83,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, vcc_hi, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, vcc_hi, v255, 0xaf123456 ; encoding: [0x6b,0xfe,0x83,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0xfe,0x83,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, vcc_lo, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, vcc_lo, v255, 0xaf123456 ; encoding: [0x6a,0xfe,0x83,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0xfe,0x83,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, null, v255, 0xaf123456 ; encoding: [0xff,0xfe,0x83,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x83,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, src_scc, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, -1, v255, 0xaf123456 ; encoding: [0xfd,0xfe,0x83,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0xfe,0x83,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, 0.5, v3, 0xaf123456 ; encoding: [0xf0,0xfe,0x83,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0xfe,0x83,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_fmaak_f32 v6, src_scc, v4, 0xaf123456 ; encoding: [0xc1,0xfe,0x83,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0xfe,0x83,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_fmaak_f32 v255, 0xaf123456, v5, 0xaf123456 ; encoding: [0x7c,0x08,0x82,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x08,0x82,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_fmac_f32 v6, v1, v255 ; encoding: [0x04,0xff,0x81,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x04,0xff,0x81,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_fmac_f32 v6, v255, v255 ; encoding: [0x01,0xff,0x81,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xff,0x81,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_fmac_f32 v6, v2, v255 ; encoding: [0xff,0xff,0x81,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xff,0x81,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_fmac_f32 v6, v3, v255 ; encoding: [0x02,0xff,0x81,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x02,0xff,0x81,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_fmac_f32 v6, v4, v255 ; encoding: [0x03,0xff,0x81,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x03,0xff,0x81,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, s105, 0xaf123456, v255 :: v_dual_fmac_f32 v6, s105, v255 ; encoding: [0x69,0xfe,0x81,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x69,0xfe,0x81,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, s1, 0xaf123456, v255 :: v_dual_fmac_f32 v6, s1, v255 ; encoding: [0x01,0xfe,0x81,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xfe,0x81,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, ttmp15, 0xaf123456, v255 :: v_dual_fmac_f32 v6, ttmp15, v255 ; encoding: [0x7b,0xfe,0x81,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0xfe,0x81,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, exec_hi, 0xaf123456, v255 :: v_dual_fmac_f32 v6, exec_hi, v255 ; encoding: [0x7f,0xfe,0x81,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0xfe,0x81,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, exec_lo, 0xaf123456, v255 :: v_dual_fmac_f32 v6, exec_lo, v255 ; encoding: [0x7e,0xfe,0x81,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0xfe,0x81,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, m0, 0xaf123456, v255 :: v_dual_fmac_f32 v6, m0, v255 ; encoding: [0x7d,0xfe,0x81,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0xfe,0x81,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, vcc_hi, 0xaf123456, v255 :: v_dual_fmac_f32 v6, vcc_hi, v255 ; encoding: [0x6b,0xfe,0x81,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0xfe,0x81,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, vcc_lo, 0xaf123456, v255 :: v_dual_fmac_f32 v6, vcc_lo, v255 ; encoding: [0x6a,0xfe,0x81,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0xfe,0x81,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_fmac_f32 v6, null, v255 ; encoding: [0xff,0xfe,0x81,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x81,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, src_scc, 0xaf123456, v255 :: v_dual_fmac_f32 v6, -1, v255 ; encoding: [0xfd,0xfe,0x81,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0xfe,0x81,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_fmac_f32 v6, 0.5, v3 ; encoding: [0xf0,0xfe,0x81,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0xfe,0x81,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_fmac_f32 v6, src_scc, v4 ; encoding: [0xc1,0xfe,0x81,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0xfe,0x81,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_fmac_f32 v255, 0xaf123456, v5 ; encoding: [0x7c,0x08,0x80,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x08,0x80,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, v1, 0xaf123456, v4 ; encoding: [0x04,0xff,0x85,0xc8,0x01,0x09,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x04,0xff,0x85,0xc8,0x01,0x09,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, v255, 0xaf123456, v4 ; encoding: [0x01,0xff,0x85,0xc8,0xff,0x09,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xff,0x85,0xc8,0xff,0x09,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, v2, 0xaf123456, v4 ; encoding: [0xff,0xff,0x85,0xc8,0x02,0x09,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xff,0x85,0xc8,0x02,0x09,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, v3, 0xaf123456, v4 ; encoding: [0x02,0xff,0x85,0xc8,0x03,0x09,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x02,0xff,0x85,0xc8,0x03,0x09,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, v4, 0xaf123456, v4 ; encoding: [0x03,0xff,0x85,0xc8,0x04,0x09,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x03,0xff,0x85,0xc8,0x04,0x09,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, s105, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, s105, 0xaf123456, v4 ; encoding: [0x69,0xfe,0x85,0xc8,0x69,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x69,0xfe,0x85,0xc8,0x69,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, s1, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, s1, 0xaf123456, v4 ; encoding: [0x01,0xfe,0x85,0xc8,0x01,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xfe,0x85,0xc8,0x01,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, ttmp15, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, ttmp15, 0xaf123456, v4 ; encoding: [0x7b,0xfe,0x85,0xc8,0x7b,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0xfe,0x85,0xc8,0x7b,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, exec_hi, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, exec_hi, 0xaf123456, v4 ; encoding: [0x7f,0xfe,0x85,0xc8,0x7f,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0xfe,0x85,0xc8,0x7f,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, exec_lo, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, exec_lo, 0xaf123456, v4 ; encoding: [0x7e,0xfe,0x85,0xc8,0x7e,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0xfe,0x85,0xc8,0x7e,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, m0, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, m0, 0xaf123456, v4 ; encoding: [0x7d,0xfe,0x85,0xc8,0x7d,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0xfe,0x85,0xc8,0x7d,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, vcc_hi, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, vcc_hi, 0xaf123456, v4 ; encoding: [0x6b,0xfe,0x85,0xc8,0x6b,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0xfe,0x85,0xc8,0x6b,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, vcc_lo, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, vcc_lo, 0xaf123456, v4 ; encoding: [0x6a,0xfe,0x85,0xc8,0x6a,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0xfe,0x85,0xc8,0x6a,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, null, 0xaf123456, v4 ; encoding: [0xff,0xfe,0x85,0xc8,0x7c,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x85,0xc8,0x7c,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, src_scc, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, -1, 0xaf123456, v4 ; encoding: [0xfd,0xfe,0x85,0xc8,0xc1,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0xfe,0x85,0xc8,0xc1,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, 0.5, 0xaf123456, v4 ; encoding: [0xf0,0xfe,0x85,0xc8,0xf0,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0xfe,0x85,0xc8,0xf0,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, src_scc, 0xaf123456, v4 ; encoding: [0xc1,0xfe,0x85,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0xfe,0x85,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 ; encoding: [0x7c,0x08,0x84,0xc8,0xff,0xfe,0xff,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x08,0x84,0xc8,0xff,0xfe,0xff,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, v1, v255 ; encoding: [0x04,0xff,0xa3,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x04,0xff,0xa3,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, v255, v255 ; encoding: [0x01,0xff,0xa3,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xff,0xa3,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, v2, v255 ; encoding: [0xff,0xff,0xa3,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xff,0xa3,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, v3, v255 ; encoding: [0x02,0xff,0xa3,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x02,0xff,0xa3,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, v4, v255 ; encoding: [0x03,0xff,0xa3,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x03,0xff,0xa3,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, s105, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, s105, v255 ; encoding: [0x69,0xfe,0xa3,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x69,0xfe,0xa3,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, s1, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, s1, v255 ; encoding: [0x01,0xfe,0xa3,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xfe,0xa3,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, ttmp15, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, ttmp15, v255 ; encoding: [0x7b,0xfe,0xa3,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0xfe,0xa3,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, exec_hi, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, exec_hi, v255 ; encoding: [0x7f,0xfe,0xa3,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0xfe,0xa3,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, exec_lo, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, exec_lo, v255 ; encoding: [0x7e,0xfe,0xa3,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0xfe,0xa3,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, m0, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, m0, v255 ; encoding: [0x7d,0xfe,0xa3,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0xfe,0xa3,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, vcc_hi, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, vcc_hi, v255 ; encoding: [0x6b,0xfe,0xa3,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0xfe,0xa3,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, vcc_lo, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, vcc_lo, v255 ; encoding: [0x6a,0xfe,0xa3,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0xfe,0xa3,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, null, v255 ; encoding: [0xff,0xfe,0xa3,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xa3,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, src_scc, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, -1, v255 ; encoding: [0xfd,0xfe,0xa3,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0xfe,0xa3,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, 0.5, v3 ; encoding: [0xf0,0xfe,0xa3,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0xfe,0xa3,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_lshlrev_b32 v6, src_scc, v4 ; encoding: [0xc1,0xfe,0xa3,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0xfe,0xa3,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_lshlrev_b32 v255, 0xaf123456, v5 ; encoding: [0x7c,0x08,0xa2,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x08,0xa2,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_max_num_f32 v6, v1, v255 ; encoding: [0x04,0xff,0x95,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x04,0xff,0x95,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_max_num_f32 v6, v255, v255 ; encoding: [0x01,0xff,0x95,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xff,0x95,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_max_num_f32 v6, v2, v255 ; encoding: [0xff,0xff,0x95,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xff,0x95,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_max_num_f32 v6, v3, v255 ; encoding: [0x02,0xff,0x95,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x02,0xff,0x95,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_max_num_f32 v6, v4, v255 ; encoding: [0x03,0xff,0x95,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x03,0xff,0x95,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, s105, 0xaf123456, v255 :: v_dual_max_num_f32 v6, s105, v255 ; encoding: [0x69,0xfe,0x95,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x69,0xfe,0x95,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, s1, 0xaf123456, v255 :: v_dual_max_num_f32 v6, s1, v255 ; encoding: [0x01,0xfe,0x95,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xfe,0x95,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, ttmp15, 0xaf123456, v255 :: v_dual_max_num_f32 v6, ttmp15, v255 ; encoding: [0x7b,0xfe,0x95,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0xfe,0x95,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, exec_hi, 0xaf123456, v255 :: v_dual_max_num_f32 v6, exec_hi, v255 ; encoding: [0x7f,0xfe,0x95,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0xfe,0x95,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, exec_lo, 0xaf123456, v255 :: v_dual_max_num_f32 v6, exec_lo, v255 ; encoding: [0x7e,0xfe,0x95,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0xfe,0x95,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, m0, 0xaf123456, v255 :: v_dual_max_num_f32 v6, m0, v255 ; encoding: [0x7d,0xfe,0x95,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0xfe,0x95,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, vcc_hi, 0xaf123456, v255 :: v_dual_max_num_f32 v6, vcc_hi, v255 ; encoding: [0x6b,0xfe,0x95,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0xfe,0x95,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, vcc_lo, 0xaf123456, v255 :: v_dual_max_num_f32 v6, vcc_lo, v255 ; encoding: [0x6a,0xfe,0x95,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0xfe,0x95,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_max_num_f32 v6, null, v255 ; encoding: [0xff,0xfe,0x95,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x95,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, src_scc, 0xaf123456, v255 :: v_dual_max_num_f32 v6, -1, v255 ; encoding: [0xfd,0xfe,0x95,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0xfe,0x95,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_max_num_f32 v6, 0.5, v3 ; encoding: [0xf0,0xfe,0x95,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0xfe,0x95,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_max_num_f32 v6, src_scc, v4 ; encoding: [0xc1,0xfe,0x95,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0xfe,0x95,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_max_num_f32 v255, 0xaf123456, v5 ; encoding: [0x7c,0x08,0x94,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x08,0x94,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_min_num_f32 v6, v1, v255 ; encoding: [0x04,0xff,0x97,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x04,0xff,0x97,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_min_num_f32 v6, v255, v255 ; encoding: [0x01,0xff,0x97,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xff,0x97,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_min_num_f32 v6, v2, v255 ; encoding: [0xff,0xff,0x97,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xff,0x97,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_min_num_f32 v6, v3, v255 ; encoding: [0x02,0xff,0x97,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x02,0xff,0x97,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_min_num_f32 v6, v4, v255 ; encoding: [0x03,0xff,0x97,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x03,0xff,0x97,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, s105, 0xaf123456, v255 :: v_dual_min_num_f32 v6, s105, v255 ; encoding: [0x69,0xfe,0x97,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x69,0xfe,0x97,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, s1, 0xaf123456, v255 :: v_dual_min_num_f32 v6, s1, v255 ; encoding: [0x01,0xfe,0x97,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xfe,0x97,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, ttmp15, 0xaf123456, v255 :: v_dual_min_num_f32 v6, ttmp15, v255 ; encoding: [0x7b,0xfe,0x97,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0xfe,0x97,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, exec_hi, 0xaf123456, v255 :: v_dual_min_num_f32 v6, exec_hi, v255 ; encoding: [0x7f,0xfe,0x97,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0xfe,0x97,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, exec_lo, 0xaf123456, v255 :: v_dual_min_num_f32 v6, exec_lo, v255 ; encoding: [0x7e,0xfe,0x97,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0xfe,0x97,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, m0, 0xaf123456, v255 :: v_dual_min_num_f32 v6, m0, v255 ; encoding: [0x7d,0xfe,0x97,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0xfe,0x97,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, vcc_hi, 0xaf123456, v255 :: v_dual_min_num_f32 v6, vcc_hi, v255 ; encoding: [0x6b,0xfe,0x97,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0xfe,0x97,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, vcc_lo, 0xaf123456, v255 :: v_dual_min_num_f32 v6, vcc_lo, v255 ; encoding: [0x6a,0xfe,0x97,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0xfe,0x97,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_min_num_f32 v6, null, v255 ; encoding: [0xff,0xfe,0x97,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x97,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, src_scc, 0xaf123456, v255 :: v_dual_min_num_f32 v6, -1, v255 ; encoding: [0xfd,0xfe,0x97,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0xfe,0x97,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_min_num_f32 v6, 0.5, v3 ; encoding: [0xf0,0xfe,0x97,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0xfe,0x97,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_min_num_f32 v6, src_scc, v4 ; encoding: [0xc1,0xfe,0x97,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0xfe,0x97,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_min_num_f32 v255, 0xaf123456, v5 ; encoding: [0x7c,0x08,0x96,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x08,0x96,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_mov_b32 v6, v1 ; encoding: [0x04,0xff,0x91,0xc8,0x01,0x01,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x04,0xff,0x91,0xc8,0x01,0x01,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_mov_b32 v6, v255 ; encoding: [0x01,0xff,0x91,0xc8,0xff,0x01,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xff,0x91,0xc8,0xff,0x01,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_mov_b32 v6, v2 ; encoding: [0xff,0xff,0x91,0xc8,0x02,0x01,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xff,0x91,0xc8,0x02,0x01,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_mov_b32 v6, v3 ; encoding: [0x02,0xff,0x91,0xc8,0x03,0x01,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x02,0xff,0x91,0xc8,0x03,0x01,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_mov_b32 v6, v4 ; encoding: [0x03,0xff,0x91,0xc8,0x04,0x01,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x03,0xff,0x91,0xc8,0x04,0x01,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, s105, 0xaf123456, v255 :: v_dual_mov_b32 v6, s105 ; encoding: [0x69,0xfe,0x91,0xc8,0x69,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x69,0xfe,0x91,0xc8,0x69,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, s1, 0xaf123456, v255 :: v_dual_mov_b32 v6, s1 ; encoding: [0x01,0xfe,0x91,0xc8,0x01,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xfe,0x91,0xc8,0x01,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, ttmp15, 0xaf123456, v255 :: v_dual_mov_b32 v6, ttmp15 ; encoding: [0x7b,0xfe,0x91,0xc8,0x7b,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0xfe,0x91,0xc8,0x7b,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, exec_hi, 0xaf123456, v255 :: v_dual_mov_b32 v6, exec_hi ; encoding: [0x7f,0xfe,0x91,0xc8,0x7f,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0xfe,0x91,0xc8,0x7f,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, exec_lo, 0xaf123456, v255 :: v_dual_mov_b32 v6, exec_lo ; encoding: [0x7e,0xfe,0x91,0xc8,0x7e,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0xfe,0x91,0xc8,0x7e,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, m0, 0xaf123456, v255 :: v_dual_mov_b32 v6, m0 ; encoding: [0x7d,0xfe,0x91,0xc8,0x7d,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0xfe,0x91,0xc8,0x7d,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, vcc_hi, 0xaf123456, v255 :: v_dual_mov_b32 v6, vcc_hi ; encoding: [0x6b,0xfe,0x91,0xc8,0x6b,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0xfe,0x91,0xc8,0x6b,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, vcc_lo, 0xaf123456, v255 :: v_dual_mov_b32 v6, vcc_lo ; encoding: [0x6a,0xfe,0x91,0xc8,0x6a,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0xfe,0x91,0xc8,0x6a,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_mov_b32 v6, null ; encoding: [0xff,0xfe,0x91,0xc8,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x91,0xc8,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, src_scc, 0xaf123456, v255 :: v_dual_mov_b32 v6, -1 ; encoding: [0xfd,0xfe,0x91,0xc8,0xc1,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0xfe,0x91,0xc8,0xc1,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_mov_b32 v6, 0.5 ; encoding: [0xf0,0xfe,0x91,0xc8,0xf0,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0xfe,0x91,0xc8,0xf0,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_mov_b32 v6, src_scc ; encoding: [0xc1,0xfe,0x91,0xc8,0xfd,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0xfe,0x91,0xc8,0xfd,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_mov_b32 v255, 0xaf123456 ; encoding: [0x7c,0x08,0x90,0xc8,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x08,0x90,0xc8,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, v1, v255 ; encoding: [0x04,0xff,0x8f,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x04,0xff,0x8f,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, v255, v255 ; encoding: [0x01,0xff,0x8f,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xff,0x8f,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, v2, v255 ; encoding: [0xff,0xff,0x8f,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xff,0x8f,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, v3, v255 ; encoding: [0x02,0xff,0x8f,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x02,0xff,0x8f,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, v4, v255 ; encoding: [0x03,0xff,0x8f,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x03,0xff,0x8f,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, s105, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, s105, v255 ; encoding: [0x69,0xfe,0x8f,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x69,0xfe,0x8f,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, s1, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, s1, v255 ; encoding: [0x01,0xfe,0x8f,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xfe,0x8f,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, ttmp15, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, ttmp15, v255 ; encoding: [0x7b,0xfe,0x8f,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0xfe,0x8f,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, exec_hi, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, exec_hi, v255 ; encoding: [0x7f,0xfe,0x8f,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0xfe,0x8f,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, exec_lo, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, exec_lo, v255 ; encoding: [0x7e,0xfe,0x8f,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0xfe,0x8f,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, m0, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, m0, v255 ; encoding: [0x7d,0xfe,0x8f,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0xfe,0x8f,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, vcc_hi, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, vcc_hi, v255 ; encoding: [0x6b,0xfe,0x8f,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0xfe,0x8f,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, vcc_lo, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, vcc_lo, v255 ; encoding: [0x6a,0xfe,0x8f,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0xfe,0x8f,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, null, v255 ; encoding: [0xff,0xfe,0x8f,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x8f,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, src_scc, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, -1, v255 ; encoding: [0xfd,0xfe,0x8f,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0xfe,0x8f,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, 0.5, v3 ; encoding: [0xf0,0xfe,0x8f,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0xfe,0x8f,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_mul_dx9_zero_f32 v6, src_scc, v4 ; encoding: [0xc1,0xfe,0x8f,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0xfe,0x8f,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v5 ; encoding: [0x7c,0x08,0x8e,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x08,0x8e,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_mul_f32 v6, v1, v255 ; encoding: [0x04,0xff,0x87,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x04,0xff,0x87,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_mul_f32 v6, v255, v255 ; encoding: [0x01,0xff,0x87,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xff,0x87,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_mul_f32 v6, v2, v255 ; encoding: [0xff,0xff,0x87,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xff,0x87,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_mul_f32 v6, v3, v255 ; encoding: [0x02,0xff,0x87,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x02,0xff,0x87,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_mul_f32 v6, v4, v255 ; encoding: [0x03,0xff,0x87,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x03,0xff,0x87,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, s105, 0xaf123456, v255 :: v_dual_mul_f32 v6, s105, v255 ; encoding: [0x69,0xfe,0x87,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x69,0xfe,0x87,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, s1, 0xaf123456, v255 :: v_dual_mul_f32 v6, s1, v255 ; encoding: [0x01,0xfe,0x87,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xfe,0x87,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, ttmp15, 0xaf123456, v255 :: v_dual_mul_f32 v6, ttmp15, v255 ; encoding: [0x7b,0xfe,0x87,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0xfe,0x87,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, exec_hi, 0xaf123456, v255 :: v_dual_mul_f32 v6, exec_hi, v255 ; encoding: [0x7f,0xfe,0x87,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0xfe,0x87,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, exec_lo, 0xaf123456, v255 :: v_dual_mul_f32 v6, exec_lo, v255 ; encoding: [0x7e,0xfe,0x87,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0xfe,0x87,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, m0, 0xaf123456, v255 :: v_dual_mul_f32 v6, m0, v255 ; encoding: [0x7d,0xfe,0x87,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0xfe,0x87,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, vcc_hi, 0xaf123456, v255 :: v_dual_mul_f32 v6, vcc_hi, v255 ; encoding: [0x6b,0xfe,0x87,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0xfe,0x87,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, vcc_lo, 0xaf123456, v255 :: v_dual_mul_f32 v6, vcc_lo, v255 ; encoding: [0x6a,0xfe,0x87,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0xfe,0x87,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_mul_f32 v6, null, v255 ; encoding: [0xff,0xfe,0x87,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x87,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, src_scc, 0xaf123456, v255 :: v_dual_mul_f32 v6, -1, v255 ; encoding: [0xfd,0xfe,0x87,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0xfe,0x87,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_mul_f32 v6, 0.5, v3 ; encoding: [0xf0,0xfe,0x87,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0xfe,0x87,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_mul_f32 v6, src_scc, v4 ; encoding: [0xc1,0xfe,0x87,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0xfe,0x87,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_mul_f32 v255, 0xaf123456, v5 ; encoding: [0x7c,0x08,0x86,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x08,0x86,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_sub_f32 v6, v1, v255 ; encoding: [0x04,0xff,0x8b,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x04,0xff,0x8b,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_sub_f32 v6, v255, v255 ; encoding: [0x01,0xff,0x8b,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xff,0x8b,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_sub_f32 v6, v2, v255 ; encoding: [0xff,0xff,0x8b,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xff,0x8b,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_sub_f32 v6, v3, v255 ; encoding: [0x02,0xff,0x8b,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x02,0xff,0x8b,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_sub_f32 v6, v4, v255 ; encoding: [0x03,0xff,0x8b,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x03,0xff,0x8b,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, s105, 0xaf123456, v255 :: v_dual_sub_f32 v6, s105, v255 ; encoding: [0x69,0xfe,0x8b,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x69,0xfe,0x8b,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, s1, 0xaf123456, v255 :: v_dual_sub_f32 v6, s1, v255 ; encoding: [0x01,0xfe,0x8b,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xfe,0x8b,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, ttmp15, 0xaf123456, v255 :: v_dual_sub_f32 v6, ttmp15, v255 ; encoding: [0x7b,0xfe,0x8b,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0xfe,0x8b,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, exec_hi, 0xaf123456, v255 :: v_dual_sub_f32 v6, exec_hi, v255 ; encoding: [0x7f,0xfe,0x8b,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0xfe,0x8b,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, exec_lo, 0xaf123456, v255 :: v_dual_sub_f32 v6, exec_lo, v255 ; encoding: [0x7e,0xfe,0x8b,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0xfe,0x8b,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, m0, 0xaf123456, v255 :: v_dual_sub_f32 v6, m0, v255 ; encoding: [0x7d,0xfe,0x8b,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0xfe,0x8b,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, vcc_hi, 0xaf123456, v255 :: v_dual_sub_f32 v6, vcc_hi, v255 ; encoding: [0x6b,0xfe,0x8b,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0xfe,0x8b,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, vcc_lo, 0xaf123456, v255 :: v_dual_sub_f32 v6, vcc_lo, v255 ; encoding: [0x6a,0xfe,0x8b,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0xfe,0x8b,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_sub_f32 v6, null, v255 ; encoding: [0xff,0xfe,0x8b,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x8b,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, src_scc, 0xaf123456, v255 :: v_dual_sub_f32 v6, -1, v255 ; encoding: [0xfd,0xfe,0x8b,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0xfe,0x8b,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_sub_f32 v6, 0.5, v3 ; encoding: [0xf0,0xfe,0x8b,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0xfe,0x8b,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_sub_f32 v6, src_scc, v4 ; encoding: [0xc1,0xfe,0x8b,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0xfe,0x8b,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_sub_f32 v255, 0xaf123456, v5 ; encoding: [0x7c,0x08,0x8a,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x08,0x8a,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v4, 0xaf123456, v255 :: v_dual_subrev_f32 v6, v1, v255 ; encoding: [0x04,0xff,0x8d,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x04,0xff,0x8d,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v1, 0xaf123456, v255 :: v_dual_subrev_f32 v6, v255, v255 ; encoding: [0x01,0xff,0x8d,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xff,0x8d,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v255, 0xaf123456, v255 :: v_dual_subrev_f32 v6, v2, v255 ; encoding: [0xff,0xff,0x8d,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xff,0x8d,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v2, 0xaf123456, v255 :: v_dual_subrev_f32 v6, v3, v255 ; encoding: [0x02,0xff,0x8d,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x02,0xff,0x8d,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, v3, 0xaf123456, v255 :: v_dual_subrev_f32 v6, v4, v255 ; encoding: [0x03,0xff,0x8d,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x03,0xff,0x8d,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, s105, 0xaf123456, v255 :: v_dual_subrev_f32 v6, s105, v255 ; encoding: [0x69,0xfe,0x8d,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x69,0xfe,0x8d,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, s1, 0xaf123456, v255 :: v_dual_subrev_f32 v6, s1, v255 ; encoding: [0x01,0xfe,0x8d,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xfe,0x8d,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, ttmp15, 0xaf123456, v255 :: v_dual_subrev_f32 v6, ttmp15, v255 ; encoding: [0x7b,0xfe,0x8d,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0xfe,0x8d,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, exec_hi, 0xaf123456, v255 :: v_dual_subrev_f32 v6, exec_hi, v255 ; encoding: [0x7f,0xfe,0x8d,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0xfe,0x8d,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, exec_lo, 0xaf123456, v255 :: v_dual_subrev_f32 v6, exec_lo, v255 ; encoding: [0x7e,0xfe,0x8d,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0xfe,0x8d,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, m0, 0xaf123456, v255 :: v_dual_subrev_f32 v6, m0, v255 ; encoding: [0x7d,0xfe,0x8d,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0xfe,0x8d,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, vcc_hi, 0xaf123456, v255 :: v_dual_subrev_f32 v6, vcc_hi, v255 ; encoding: [0x6b,0xfe,0x8d,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0xfe,0x8d,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, vcc_lo, 0xaf123456, v255 :: v_dual_subrev_f32 v6, vcc_lo, v255 ; encoding: [0x6a,0xfe,0x8d,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0xfe,0x8d,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 :: v_dual_subrev_f32 v6, null, v255 ; encoding: [0xff,0xfe,0x8d,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x8d,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, src_scc, 0xaf123456, v255 :: v_dual_subrev_f32 v6, -1, v255 ; encoding: [0xfd,0xfe,0x8d,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0xfe,0x8d,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, 0.5, 0xaf123456, v255 :: v_dual_subrev_f32 v6, 0.5, v3 ; encoding: [0xf0,0xfe,0x8d,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0xfe,0x8d,0xc8,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v255, -1, 0xaf123456, v255 :: v_dual_subrev_f32 v6, src_scc, v4 ; encoding: [0xc1,0xfe,0x8d,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0xfe,0x8d,0xc8,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v6, null, 0xaf123456, v4 :: v_dual_subrev_f32 v255, 0xaf123456, v5 ; encoding: [0x7c,0x08,0x8c,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x08,0x8c,0xc8,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, v4, v2 :: v_dual_add_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x88,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0x88,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v1, v2 :: v_dual_add_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x88,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0x88,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v255, v2 :: v_dual_add_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x88,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0x88,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v2, v2 :: v_dual_add_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x88,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0x88,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v3, v2 :: v_dual_add_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x88,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0x88,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, s105, v2 :: v_dual_add_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x88,0xca,0x01,0x06,0x06,0xff]
+0x69,0x04,0x88,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, s1, v2 :: v_dual_add_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x88,0xca,0x69,0x06,0x06,0xff]
+0x01,0x04,0x88,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, ttmp15, v2 :: v_dual_add_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x88,0xca,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x88,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, exec_hi, v2 :: v_dual_add_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x88,0xca,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x88,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, exec_lo, v2 :: v_dual_add_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x88,0xca,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x88,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, m0, v2 :: v_dual_add_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x88,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x88,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, vcc_hi, v2 :: v_dual_add_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x88,0xca,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x88,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, vcc_lo, v2 :: v_dual_add_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x88,0xca,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x88,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, 0xaf123456, v2 :: v_dual_add_f32 v6, null, v3 ; encoding: [0xff,0x04,0x88,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x88,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, src_scc, v2 :: v_dual_add_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x88,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x88,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_add_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x88,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x88,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, -1, v4 :: v_dual_add_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x88,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x88,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v6, null, v5 :: v_dual_add_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x88,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x88,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, v4, v2 :: v_dual_add_nc_u32 v6, v1, v3 ; encoding: [0x04,0x05,0xa0,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0xa0,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v1, v2 :: v_dual_add_nc_u32 v6, v255, v3 ; encoding: [0x01,0x05,0xa0,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0xa0,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v255, v2 :: v_dual_add_nc_u32 v6, v2, v3 ; encoding: [0xff,0x05,0xa0,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0xa0,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v2, v2 :: v_dual_add_nc_u32 v6, v3, v3 ; encoding: [0x02,0x05,0xa0,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0xa0,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v3, v2 :: v_dual_add_nc_u32 v6, v4, v3 ; encoding: [0x03,0x05,0xa0,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0xa0,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, s105, v2 :: v_dual_add_nc_u32 v6, s1, v3 ; encoding: [0x69,0x04,0xa0,0xca,0x01,0x06,0x06,0xff]
+0x69,0x04,0xa0,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, s1, v2 :: v_dual_add_nc_u32 v6, s105, v3 ; encoding: [0x01,0x04,0xa0,0xca,0x69,0x06,0x06,0xff]
+0x01,0x04,0xa0,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, ttmp15, v2 :: v_dual_add_nc_u32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xa0,0xca,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xa0,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, exec_hi, v2 :: v_dual_add_nc_u32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xa0,0xca,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xa0,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, exec_lo, v2 :: v_dual_add_nc_u32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xa0,0xca,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xa0,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, m0, v2 :: v_dual_add_nc_u32 v6, m0, v3 ; encoding: [0x7d,0x04,0xa0,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xa0,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, vcc_hi, v2 :: v_dual_add_nc_u32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xa0,0xca,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xa0,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, vcc_lo, v2 :: v_dual_add_nc_u32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xa0,0xca,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xa0,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, 0xaf123456, v2 :: v_dual_add_nc_u32 v6, null, v3 ; encoding: [0xff,0x04,0xa0,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xa0,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, src_scc, v2 :: v_dual_add_nc_u32 v6, -1, v3 ; encoding: [0xfd,0x04,0xa0,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xa0,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_add_nc_u32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xa0,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xa0,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, -1, v4 :: v_dual_add_nc_u32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xa0,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xa0,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v6, null, v5 :: v_dual_add_nc_u32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xa0,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xa0,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, v4, v2 :: v_dual_and_b32 v6, v1, v3 ; encoding: [0x04,0x05,0xa4,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0xa4,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v1, v2 :: v_dual_and_b32 v6, v255, v3 ; encoding: [0x01,0x05,0xa4,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0xa4,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v255, v2 :: v_dual_and_b32 v6, v2, v3 ; encoding: [0xff,0x05,0xa4,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0xa4,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v2, v2 :: v_dual_and_b32 v6, v3, v3 ; encoding: [0x02,0x05,0xa4,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0xa4,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v3, v2 :: v_dual_and_b32 v6, v4, v3 ; encoding: [0x03,0x05,0xa4,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0xa4,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, s105, v2 :: v_dual_and_b32 v6, s1, v3 ; encoding: [0x69,0x04,0xa4,0xca,0x01,0x06,0x06,0xff]
+0x69,0x04,0xa4,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, s1, v2 :: v_dual_and_b32 v6, s105, v3 ; encoding: [0x01,0x04,0xa4,0xca,0x69,0x06,0x06,0xff]
+0x01,0x04,0xa4,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, ttmp15, v2 :: v_dual_and_b32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xa4,0xca,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xa4,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, exec_hi, v2 :: v_dual_and_b32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xa4,0xca,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xa4,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, exec_lo, v2 :: v_dual_and_b32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xa4,0xca,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xa4,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, m0, v2 :: v_dual_and_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0xa4,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xa4,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, vcc_hi, v2 :: v_dual_and_b32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xa4,0xca,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xa4,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, vcc_lo, v2 :: v_dual_and_b32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xa4,0xca,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xa4,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, 0xaf123456, v2 :: v_dual_and_b32 v6, null, v3 ; encoding: [0xff,0x04,0xa4,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xa4,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, src_scc, v2 :: v_dual_and_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0xa4,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xa4,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_and_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xa4,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xa4,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, -1, v4 :: v_dual_and_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xa4,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xa4,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v6, null, v5 :: v_dual_and_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xa4,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xa4,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, v4, v2 :: v_dual_cndmask_b32 v6, v1, v3 ; encoding: [0x04,0x05,0x92,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0x92,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v1, v2 :: v_dual_cndmask_b32 v6, v255, v3 ; encoding: [0x01,0x05,0x92,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0x92,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v255, v2 :: v_dual_cndmask_b32 v6, v2, v3 ; encoding: [0xff,0x05,0x92,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0x92,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v2, v2 :: v_dual_cndmask_b32 v6, v3, v3 ; encoding: [0x02,0x05,0x92,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0x92,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v3, v2 :: v_dual_cndmask_b32 v6, v4, v3 ; encoding: [0x03,0x05,0x92,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0x92,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, s105, v2 :: v_dual_cndmask_b32 v6, s105, v3 ; encoding: [0x69,0x04,0x92,0xca,0x69,0x06,0x06,0xff]
+0x69,0x04,0x92,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, s1, v2 :: v_dual_cndmask_b32 v6, s1, v3 ; encoding: [0x01,0x04,0x92,0xca,0x01,0x06,0x06,0xff]
+0x01,0x04,0x92,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, ttmp15, v2 :: v_dual_cndmask_b32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0x92,0xca,0x7b,0x06,0x06,0xff]
+0x7b,0x04,0x92,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, exec_hi, v2 :: v_dual_cndmask_b32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0x92,0xca,0x7f,0x06,0x06,0xff]
+0x7f,0x04,0x92,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, exec_lo, v2 :: v_dual_cndmask_b32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0x92,0xca,0x7e,0x06,0x06,0xff]
+0x7e,0x04,0x92,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, m0, v2 :: v_dual_cndmask_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0x92,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x92,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, vcc_hi, v2 :: v_dual_cndmask_b32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0x92,0xca,0x6b,0x06,0x06,0xff]
+0x6b,0x04,0x92,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, vcc_lo, v2 :: v_dual_cndmask_b32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0x92,0xca,0x6a,0x06,0x06,0xff]
+0x6a,0x04,0x92,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, 0xaf123456, v2 :: v_dual_cndmask_b32 v6, null, v3 ; encoding: [0xff,0x04,0x92,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x92,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, src_scc, v2 :: v_dual_cndmask_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0x92,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x92,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_cndmask_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x92,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x92,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, -1, v4 :: v_dual_cndmask_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x92,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x92,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v6, null, v5 :: v_dual_cndmask_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x92,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x92,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, v4, v2 :: v_dual_fmaak_f32 v6, v1, v3, 0xaf123456 ; encoding: [0x04,0x05,0x82,0xca,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x04,0x05,0x82,0xca,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, v1, v2 :: v_dual_fmaak_f32 v6, v255, v3, 0xaf123456 ; encoding: [0x01,0x05,0x82,0xca,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x05,0x82,0xca,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, v255, v2 :: v_dual_fmaak_f32 v6, v2, v3, 0xaf123456 ; encoding: [0xff,0x05,0x82,0xca,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x05,0x82,0xca,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, v2, v2 :: v_dual_fmaak_f32 v6, v3, v3, 0xaf123456 ; encoding: [0x02,0x05,0x82,0xca,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x02,0x05,0x82,0xca,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, v3, v2 :: v_dual_fmaak_f32 v6, v4, v3, 0xaf123456 ; encoding: [0x03,0x05,0x82,0xca,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x03,0x05,0x82,0xca,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, s105, v2 :: v_dual_fmaak_f32 v6, s105, v3, 0xaf123456 ; encoding: [0x69,0x04,0x82,0xca,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x69,0x04,0x82,0xca,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, s1, v2 :: v_dual_fmaak_f32 v6, s1, v3, 0xaf123456 ; encoding: [0x01,0x04,0x82,0xca,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x04,0x82,0xca,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, ttmp15, v2 :: v_dual_fmaak_f32 v6, ttmp15, v3, 0xaf123456 ; encoding: [0x7b,0x04,0x82,0xca,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0x04,0x82,0xca,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, exec_hi, v2 :: v_dual_fmaak_f32 v6, exec_hi, v3, 0xaf123456 ; encoding: [0x7f,0x04,0x82,0xca,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0x04,0x82,0xca,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, exec_lo, v2 :: v_dual_fmaak_f32 v6, exec_lo, v3, 0xaf123456 ; encoding: [0x7e,0x04,0x82,0xca,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0x04,0x82,0xca,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, m0, v2 :: v_dual_fmaak_f32 v6, m0, v3, 0xaf123456 ; encoding: [0x7d,0x04,0x82,0xca,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0x04,0x82,0xca,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, vcc_hi, v2 :: v_dual_fmaak_f32 v6, vcc_hi, v3, 0xaf123456 ; encoding: [0x6b,0x04,0x82,0xca,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0x04,0x82,0xca,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, vcc_lo, v2 :: v_dual_fmaak_f32 v6, vcc_lo, v3, 0xaf123456 ; encoding: [0x6a,0x04,0x82,0xca,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0x04,0x82,0xca,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, null, v3, 0xaf123456 ; encoding: [0xff,0x04,0x82,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x82,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, src_scc, v2 :: v_dual_fmaak_f32 v6, -1, v3, 0xaf123456 ; encoding: [0xfd,0x04,0x82,0xca,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0x04,0x82,0xca,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_fmaak_f32 v6, 0.5, v2, 0xaf123456 ; encoding: [0xf0,0x06,0x82,0xca,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0x82,0xca,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, -1, v4 :: v_dual_fmaak_f32 v6, src_scc, v5, 0xaf123456 ; encoding: [0xc1,0x08,0x82,0xca,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0x82,0xca,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v6, null, v5 :: v_dual_fmaak_f32 v255, 0xaf123456, v4, 0xaf123456 ; encoding: [0x7c,0x0a,0x82,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x82,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, v4, v2 :: v_dual_fmac_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x80,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0x80,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v1, v2 :: v_dual_fmac_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x80,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0x80,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v255, v2 :: v_dual_fmac_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x80,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0x80,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v2, v2 :: v_dual_fmac_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x80,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0x80,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v3, v2 :: v_dual_fmac_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x80,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0x80,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, s105, v2 :: v_dual_fmac_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x80,0xca,0x01,0x06,0x06,0xff]
+0x69,0x04,0x80,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, s1, v2 :: v_dual_fmac_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x80,0xca,0x69,0x06,0x06,0xff]
+0x01,0x04,0x80,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, ttmp15, v2 :: v_dual_fmac_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x80,0xca,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x80,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, exec_hi, v2 :: v_dual_fmac_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x80,0xca,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x80,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, exec_lo, v2 :: v_dual_fmac_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x80,0xca,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x80,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, m0, v2 :: v_dual_fmac_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x80,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x80,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, vcc_hi, v2 :: v_dual_fmac_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x80,0xca,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x80,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, vcc_lo, v2 :: v_dual_fmac_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x80,0xca,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x80,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, 0xaf123456, v2 :: v_dual_fmac_f32 v6, null, v3 ; encoding: [0xff,0x04,0x80,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x80,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, src_scc, v2 :: v_dual_fmac_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x80,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x80,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_fmac_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x80,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x80,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, -1, v4 :: v_dual_fmac_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x80,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x80,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v6, null, v5 :: v_dual_fmac_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x80,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x80,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, v4, v255 :: v_dual_fmamk_f32 v6, v1, 0xaf123456, v255 ; encoding: [0x04,0xff,0x85,0xca,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x04,0xff,0x85,0xca,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, v1, v255 :: v_dual_fmamk_f32 v6, v255, 0xaf123456, v255 ; encoding: [0x01,0xff,0x85,0xca,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xff,0x85,0xca,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, v255, v255 :: v_dual_fmamk_f32 v6, v2, 0xaf123456, v255 ; encoding: [0xff,0xff,0x85,0xca,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xff,0x85,0xca,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, v2, v255 :: v_dual_fmamk_f32 v6, v3, 0xaf123456, v255 ; encoding: [0x02,0xff,0x85,0xca,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x02,0xff,0x85,0xca,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, v3, v255 :: v_dual_fmamk_f32 v6, v4, 0xaf123456, v255 ; encoding: [0x03,0xff,0x85,0xca,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x03,0xff,0x85,0xca,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, s105, v255 :: v_dual_fmamk_f32 v6, s105, 0xaf123456, v255 ; encoding: [0x69,0xfe,0x85,0xca,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x69,0xfe,0x85,0xca,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, s1, v255 :: v_dual_fmamk_f32 v6, s1, 0xaf123456, v255 ; encoding: [0x01,0xfe,0x85,0xca,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xfe,0x85,0xca,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, ttmp15, v255 :: v_dual_fmamk_f32 v6, ttmp15, 0xaf123456, v255 ; encoding: [0x7b,0xfe,0x85,0xca,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0xfe,0x85,0xca,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, exec_hi, v255 :: v_dual_fmamk_f32 v6, exec_hi, 0xaf123456, v255 ; encoding: [0x7f,0xfe,0x85,0xca,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0xfe,0x85,0xca,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, exec_lo, v255 :: v_dual_fmamk_f32 v6, exec_lo, 0xaf123456, v255 ; encoding: [0x7e,0xfe,0x85,0xca,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0xfe,0x85,0xca,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, m0, v255 :: v_dual_fmamk_f32 v6, m0, 0xaf123456, v255 ; encoding: [0x7d,0xfe,0x85,0xca,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0xfe,0x85,0xca,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, vcc_hi, v255 :: v_dual_fmamk_f32 v6, vcc_hi, 0xaf123456, v255 ; encoding: [0x6b,0xfe,0x85,0xca,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0xfe,0x85,0xca,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, vcc_lo, v255 :: v_dual_fmamk_f32 v6, vcc_lo, 0xaf123456, v255 ; encoding: [0x6a,0xfe,0x85,0xca,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0xfe,0x85,0xca,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, null, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x85,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x85,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, src_scc, v255 :: v_dual_fmamk_f32 v6, -1, 0xaf123456, v255 ; encoding: [0xfd,0xfe,0x85,0xca,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0xfe,0x85,0xca,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_fmamk_f32 v6, 0.5, 0xaf123456, v255 ; encoding: [0xf0,0x06,0x84,0xca,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0x84,0xca,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, -1, v4 :: v_dual_fmamk_f32 v6, src_scc, 0xaf123456, v255 ; encoding: [0xc1,0x08,0x84,0xca,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0x84,0xca,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v6, null, v5 :: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x84,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x84,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, v4, v2 :: v_dual_lshlrev_b32 v6, v1, v3 ; encoding: [0x04,0x05,0xa2,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0xa2,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v1, v2 :: v_dual_lshlrev_b32 v6, v255, v3 ; encoding: [0x01,0x05,0xa2,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0xa2,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v255, v2 :: v_dual_lshlrev_b32 v6, v2, v3 ; encoding: [0xff,0x05,0xa2,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0xa2,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v2, v2 :: v_dual_lshlrev_b32 v6, v3, v3 ; encoding: [0x02,0x05,0xa2,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0xa2,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v3, v2 :: v_dual_lshlrev_b32 v6, v4, v3 ; encoding: [0x03,0x05,0xa2,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0xa2,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, s105, v2 :: v_dual_lshlrev_b32 v6, s1, v3 ; encoding: [0x69,0x04,0xa2,0xca,0x01,0x06,0x06,0xff]
+0x69,0x04,0xa2,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, s1, v2 :: v_dual_lshlrev_b32 v6, s105, v3 ; encoding: [0x01,0x04,0xa2,0xca,0x69,0x06,0x06,0xff]
+0x01,0x04,0xa2,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, ttmp15, v2 :: v_dual_lshlrev_b32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xa2,0xca,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xa2,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, exec_hi, v2 :: v_dual_lshlrev_b32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xa2,0xca,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xa2,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, exec_lo, v2 :: v_dual_lshlrev_b32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xa2,0xca,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xa2,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, m0, v2 :: v_dual_lshlrev_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0xa2,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xa2,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, vcc_hi, v2 :: v_dual_lshlrev_b32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xa2,0xca,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xa2,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, vcc_lo, v2 :: v_dual_lshlrev_b32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xa2,0xca,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xa2,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, 0xaf123456, v2 :: v_dual_lshlrev_b32 v6, null, v3 ; encoding: [0xff,0x04,0xa2,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xa2,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, src_scc, v2 :: v_dual_lshlrev_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0xa2,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xa2,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_lshlrev_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xa2,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xa2,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, -1, v4 :: v_dual_lshlrev_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xa2,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xa2,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v6, null, v5 :: v_dual_lshlrev_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xa2,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xa2,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, v4, v2 :: v_dual_max_num_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x94,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0x94,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v1, v2 :: v_dual_max_num_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x94,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0x94,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v255, v2 :: v_dual_max_num_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x94,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0x94,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v2, v2 :: v_dual_max_num_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x94,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0x94,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v3, v2 :: v_dual_max_num_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x94,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0x94,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, s105, v2 :: v_dual_max_num_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x94,0xca,0x01,0x06,0x06,0xff]
+0x69,0x04,0x94,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, s1, v2 :: v_dual_max_num_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x94,0xca,0x69,0x06,0x06,0xff]
+0x01,0x04,0x94,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, ttmp15, v2 :: v_dual_max_num_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x94,0xca,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x94,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, exec_hi, v2 :: v_dual_max_num_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x94,0xca,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x94,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, exec_lo, v2 :: v_dual_max_num_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x94,0xca,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x94,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, m0, v2 :: v_dual_max_num_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x94,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x94,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, vcc_hi, v2 :: v_dual_max_num_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x94,0xca,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x94,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, vcc_lo, v2 :: v_dual_max_num_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x94,0xca,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x94,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, 0xaf123456, v2 :: v_dual_max_num_f32 v6, null, v3 ; encoding: [0xff,0x04,0x94,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x94,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, src_scc, v2 :: v_dual_max_num_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x94,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x94,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_max_num_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x94,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x94,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, -1, v4 :: v_dual_max_num_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x94,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x94,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v6, null, v5 :: v_dual_max_num_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x94,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x94,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, v4, v2 :: v_dual_min_num_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x96,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0x96,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v1, v2 :: v_dual_min_num_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x96,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0x96,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v255, v2 :: v_dual_min_num_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x96,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0x96,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v2, v2 :: v_dual_min_num_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x96,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0x96,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v3, v2 :: v_dual_min_num_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x96,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0x96,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, s105, v2 :: v_dual_min_num_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x96,0xca,0x01,0x06,0x06,0xff]
+0x69,0x04,0x96,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, s1, v2 :: v_dual_min_num_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x96,0xca,0x69,0x06,0x06,0xff]
+0x01,0x04,0x96,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, ttmp15, v2 :: v_dual_min_num_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x96,0xca,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x96,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, exec_hi, v2 :: v_dual_min_num_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x96,0xca,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x96,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, exec_lo, v2 :: v_dual_min_num_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x96,0xca,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x96,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, m0, v2 :: v_dual_min_num_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x96,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x96,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, vcc_hi, v2 :: v_dual_min_num_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x96,0xca,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x96,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, vcc_lo, v2 :: v_dual_min_num_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x96,0xca,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x96,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, 0xaf123456, v2 :: v_dual_min_num_f32 v6, null, v3 ; encoding: [0xff,0x04,0x96,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x96,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, src_scc, v2 :: v_dual_min_num_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x96,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x96,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_min_num_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x96,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x96,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, -1, v4 :: v_dual_min_num_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x96,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x96,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v6, null, v5 :: v_dual_min_num_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x96,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x96,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, v4, v255 :: v_dual_mov_b32 v6, v1 ; encoding: [0x04,0xff,0x91,0xca,0x01,0x01,0x06,0xff]
+0x04,0xff,0x91,0xca,0x01,0x01,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v1, v255 :: v_dual_mov_b32 v6, v255 ; encoding: [0x01,0xff,0x91,0xca,0xff,0x01,0x06,0xff]
+0x01,0xff,0x91,0xca,0xff,0x01,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v255, v255 :: v_dual_mov_b32 v6, v2 ; encoding: [0xff,0xff,0x91,0xca,0x02,0x01,0x06,0xff]
+0xff,0xff,0x91,0xca,0x02,0x01,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v2, v255 :: v_dual_mov_b32 v6, v3 ; encoding: [0x02,0xff,0x91,0xca,0x03,0x01,0x06,0xff]
+0x02,0xff,0x91,0xca,0x03,0x01,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v3, v255 :: v_dual_mov_b32 v6, v4 ; encoding: [0x03,0xff,0x91,0xca,0x04,0x01,0x06,0xff]
+0x03,0xff,0x91,0xca,0x04,0x01,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, s105, v255 :: v_dual_mov_b32 v6, s1 ; encoding: [0x69,0xfe,0x91,0xca,0x01,0x00,0x06,0xff]
+0x69,0xfe,0x91,0xca,0x01,0x00,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, s1, v255 :: v_dual_mov_b32 v6, s105 ; encoding: [0x01,0xfe,0x91,0xca,0x69,0x00,0x06,0xff]
+0x01,0xfe,0x91,0xca,0x69,0x00,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, ttmp15, v255 :: v_dual_mov_b32 v6, vcc_lo ; encoding: [0x7b,0xfe,0x91,0xca,0x6a,0x00,0x06,0xff]
+0x7b,0xfe,0x91,0xca,0x6a,0x00,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, exec_hi, v255 :: v_dual_mov_b32 v6, vcc_hi ; encoding: [0x7f,0xfe,0x91,0xca,0x6b,0x00,0x06,0xff]
+0x7f,0xfe,0x91,0xca,0x6b,0x00,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, exec_lo, v255 :: v_dual_mov_b32 v6, ttmp15 ; encoding: [0x7e,0xfe,0x91,0xca,0x7b,0x00,0x06,0xff]
+0x7e,0xfe,0x91,0xca,0x7b,0x00,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, m0, v255 :: v_dual_mov_b32 v6, m0 ; encoding: [0x7d,0xfe,0x91,0xca,0x7d,0x00,0x06,0xff]
+0x7d,0xfe,0x91,0xca,0x7d,0x00,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, vcc_hi, v255 :: v_dual_mov_b32 v6, exec_lo ; encoding: [0x6b,0xfe,0x91,0xca,0x7e,0x00,0x06,0xff]
+0x6b,0xfe,0x91,0xca,0x7e,0x00,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, vcc_lo, v255 :: v_dual_mov_b32 v6, exec_hi ; encoding: [0x6a,0xfe,0x91,0xca,0x7f,0x00,0x06,0xff]
+0x6a,0xfe,0x91,0xca,0x7f,0x00,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, 0xaf123456, v255 :: v_dual_mov_b32 v6, null ; encoding: [0xff,0xfe,0x91,0xca,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x91,0xca,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, src_scc, v255 :: v_dual_mov_b32 v6, -1 ; encoding: [0xfd,0xfe,0x91,0xca,0xc1,0x00,0x06,0xff]
+0xfd,0xfe,0x91,0xca,0xc1,0x00,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_mov_b32 v6, 0.5 ; encoding: [0xf0,0x06,0x90,0xca,0xf0,0x00,0x06,0xff]
+0xf0,0x06,0x90,0xca,0xf0,0x00,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, -1, v4 :: v_dual_mov_b32 v6, src_scc ; encoding: [0xc1,0x08,0x90,0xca,0xfd,0x00,0x06,0xff]
+0xc1,0x08,0x90,0xca,0xfd,0x00,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v6, null, v5 :: v_dual_mov_b32 v255, 0xaf123456 ; encoding: [0x7c,0x0a,0x90,0xca,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x90,0xca,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, v4, v2 :: v_dual_mul_dx9_zero_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x8e,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0x8e,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v1, v2 :: v_dual_mul_dx9_zero_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x8e,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0x8e,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v255, v2 :: v_dual_mul_dx9_zero_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x8e,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0x8e,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v2, v2 :: v_dual_mul_dx9_zero_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x8e,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0x8e,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v3, v2 :: v_dual_mul_dx9_zero_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x8e,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0x8e,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, s105, v2 :: v_dual_mul_dx9_zero_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x8e,0xca,0x01,0x06,0x06,0xff]
+0x69,0x04,0x8e,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, s1, v2 :: v_dual_mul_dx9_zero_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x8e,0xca,0x69,0x06,0x06,0xff]
+0x01,0x04,0x8e,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, ttmp15, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x8e,0xca,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x8e,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, exec_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x8e,0xca,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x8e,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, exec_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x8e,0xca,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x8e,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, m0, v2 :: v_dual_mul_dx9_zero_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x8e,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x8e,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, vcc_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x8e,0xca,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x8e,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, vcc_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x8e,0xca,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x8e,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, 0xaf123456, v2 :: v_dual_mul_dx9_zero_f32 v6, null, v3 ; encoding: [0xff,0x04,0x8e,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x8e,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, src_scc, v2 :: v_dual_mul_dx9_zero_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x8e,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x8e,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_mul_dx9_zero_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x8e,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x8e,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, -1, v4 :: v_dual_mul_dx9_zero_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x8e,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x8e,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v6, null, v5 :: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x8e,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x8e,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, v4, v2 :: v_dual_mul_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x86,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0x86,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v1, v2 :: v_dual_mul_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x86,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0x86,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v255, v2 :: v_dual_mul_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x86,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0x86,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v2, v2 :: v_dual_mul_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x86,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0x86,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v3, v2 :: v_dual_mul_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x86,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0x86,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, s105, v2 :: v_dual_mul_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x86,0xca,0x01,0x06,0x06,0xff]
+0x69,0x04,0x86,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, s1, v2 :: v_dual_mul_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x86,0xca,0x69,0x06,0x06,0xff]
+0x01,0x04,0x86,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, ttmp15, v2 :: v_dual_mul_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x86,0xca,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x86,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, exec_hi, v2 :: v_dual_mul_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x86,0xca,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x86,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, exec_lo, v2 :: v_dual_mul_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x86,0xca,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x86,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, m0, v2 :: v_dual_mul_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x86,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x86,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, vcc_hi, v2 :: v_dual_mul_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x86,0xca,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x86,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, vcc_lo, v2 :: v_dual_mul_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x86,0xca,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x86,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, 0xaf123456, v2 :: v_dual_mul_f32 v6, null, v3 ; encoding: [0xff,0x04,0x86,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x86,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, src_scc, v2 :: v_dual_mul_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x86,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x86,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_mul_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x86,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x86,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, -1, v4 :: v_dual_mul_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x86,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x86,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v6, null, v5 :: v_dual_mul_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x86,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x86,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, v4, v2 :: v_dual_sub_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x8a,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0x8a,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v1, v2 :: v_dual_sub_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x8a,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0x8a,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v255, v2 :: v_dual_sub_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x8a,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0x8a,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v2, v2 :: v_dual_sub_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x8a,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0x8a,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v3, v2 :: v_dual_sub_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x8a,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0x8a,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, s105, v2 :: v_dual_sub_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x8a,0xca,0x01,0x06,0x06,0xff]
+0x69,0x04,0x8a,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, s1, v2 :: v_dual_sub_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x8a,0xca,0x69,0x06,0x06,0xff]
+0x01,0x04,0x8a,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, ttmp15, v2 :: v_dual_sub_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x8a,0xca,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x8a,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, exec_hi, v2 :: v_dual_sub_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x8a,0xca,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x8a,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, exec_lo, v2 :: v_dual_sub_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x8a,0xca,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x8a,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, m0, v2 :: v_dual_sub_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x8a,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x8a,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, vcc_hi, v2 :: v_dual_sub_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x8a,0xca,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x8a,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, vcc_lo, v2 :: v_dual_sub_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x8a,0xca,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x8a,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, 0xaf123456, v2 :: v_dual_sub_f32 v6, null, v3 ; encoding: [0xff,0x04,0x8a,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x8a,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, src_scc, v2 :: v_dual_sub_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x8a,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x8a,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_sub_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x8a,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x8a,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, -1, v4 :: v_dual_sub_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x8a,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x8a,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v6, null, v5 :: v_dual_sub_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x8a,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x8a,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, v4, v2 :: v_dual_subrev_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x8c,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0x8c,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v1, v2 :: v_dual_subrev_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x8c,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0x8c,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v255, v2 :: v_dual_subrev_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x8c,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0x8c,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v2, v2 :: v_dual_subrev_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x8c,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0x8c,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, v3, v2 :: v_dual_subrev_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x8c,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0x8c,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, s105, v2 :: v_dual_subrev_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x8c,0xca,0x01,0x06,0x06,0xff]
+0x69,0x04,0x8c,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, s1, v2 :: v_dual_subrev_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x8c,0xca,0x69,0x06,0x06,0xff]
+0x01,0x04,0x8c,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, ttmp15, v2 :: v_dual_subrev_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x8c,0xca,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x8c,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, exec_hi, v2 :: v_dual_subrev_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x8c,0xca,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x8c,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, exec_lo, v2 :: v_dual_subrev_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x8c,0xca,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x8c,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, m0, v2 :: v_dual_subrev_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x8c,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x8c,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, vcc_hi, v2 :: v_dual_subrev_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x8c,0xca,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x8c,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, vcc_lo, v2 :: v_dual_subrev_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x8c,0xca,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x8c,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, 0xaf123456, v2 :: v_dual_subrev_f32 v6, null, v3 ; encoding: [0xff,0x04,0x8c,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x8c,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_max_num_f32 v255, src_scc, v2 :: v_dual_subrev_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x8c,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x8c,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, 0.5, v3 :: v_dual_subrev_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x8c,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x8c,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v255, -1, v4 :: v_dual_subrev_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x8c,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x8c,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_max_num_f32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x8c,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x8c,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, v4, v2 :: v_dual_add_f32 v6, v1, v3 ; encoding: [0x04,0x05,0xc8,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0xc8,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v1, v2 :: v_dual_add_f32 v6, v255, v3 ; encoding: [0x01,0x05,0xc8,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0xc8,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v255, v2 :: v_dual_add_f32 v6, v2, v3 ; encoding: [0xff,0x05,0xc8,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0xc8,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v2, v2 :: v_dual_add_f32 v6, v3, v3 ; encoding: [0x02,0x05,0xc8,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0xc8,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v3, v2 :: v_dual_add_f32 v6, v4, v3 ; encoding: [0x03,0x05,0xc8,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0xc8,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, s105, v2 :: v_dual_add_f32 v6, s1, v3 ; encoding: [0x69,0x04,0xc8,0xca,0x01,0x06,0x06,0xff]
+0x69,0x04,0xc8,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, s1, v2 :: v_dual_add_f32 v6, s105, v3 ; encoding: [0x01,0x04,0xc8,0xca,0x69,0x06,0x06,0xff]
+0x01,0x04,0xc8,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, ttmp15, v2 :: v_dual_add_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xc8,0xca,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xc8,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, exec_hi, v2 :: v_dual_add_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xc8,0xca,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xc8,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, exec_lo, v2 :: v_dual_add_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xc8,0xca,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xc8,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, m0, v2 :: v_dual_add_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0xc8,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xc8,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, vcc_hi, v2 :: v_dual_add_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xc8,0xca,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xc8,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, vcc_lo, v2 :: v_dual_add_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xc8,0xca,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xc8,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, 0xaf123456, v2 :: v_dual_add_f32 v6, null, v3 ; encoding: [0xff,0x04,0xc8,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xc8,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, src_scc, v2 :: v_dual_add_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0xc8,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xc8,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_add_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xc8,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xc8,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, -1, v4 :: v_dual_add_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xc8,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xc8,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v6, null, v5 :: v_dual_add_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xc8,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xc8,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, v4, v2 :: v_dual_add_nc_u32 v6, v1, v3 ; encoding: [0x04,0x05,0xe0,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0xe0,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v1, v2 :: v_dual_add_nc_u32 v6, v255, v3 ; encoding: [0x01,0x05,0xe0,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0xe0,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v255, v2 :: v_dual_add_nc_u32 v6, v2, v3 ; encoding: [0xff,0x05,0xe0,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0xe0,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v2, v2 :: v_dual_add_nc_u32 v6, v3, v3 ; encoding: [0x02,0x05,0xe0,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0xe0,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v3, v2 :: v_dual_add_nc_u32 v6, v4, v3 ; encoding: [0x03,0x05,0xe0,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0xe0,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, s105, v2 :: v_dual_add_nc_u32 v6, s1, v3 ; encoding: [0x69,0x04,0xe0,0xca,0x01,0x06,0x06,0xff]
+0x69,0x04,0xe0,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, s1, v2 :: v_dual_add_nc_u32 v6, s105, v3 ; encoding: [0x01,0x04,0xe0,0xca,0x69,0x06,0x06,0xff]
+0x01,0x04,0xe0,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, ttmp15, v2 :: v_dual_add_nc_u32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xe0,0xca,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xe0,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, exec_hi, v2 :: v_dual_add_nc_u32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xe0,0xca,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xe0,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, exec_lo, v2 :: v_dual_add_nc_u32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xe0,0xca,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xe0,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, m0, v2 :: v_dual_add_nc_u32 v6, m0, v3 ; encoding: [0x7d,0x04,0xe0,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xe0,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, vcc_hi, v2 :: v_dual_add_nc_u32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xe0,0xca,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xe0,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, vcc_lo, v2 :: v_dual_add_nc_u32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xe0,0xca,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xe0,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, 0xaf123456, v2 :: v_dual_add_nc_u32 v6, null, v3 ; encoding: [0xff,0x04,0xe0,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xe0,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, src_scc, v2 :: v_dual_add_nc_u32 v6, -1, v3 ; encoding: [0xfd,0x04,0xe0,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xe0,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_add_nc_u32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xe0,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xe0,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, -1, v4 :: v_dual_add_nc_u32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xe0,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xe0,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v6, null, v5 :: v_dual_add_nc_u32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xe0,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xe0,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, v4, v2 :: v_dual_and_b32 v6, v1, v3 ; encoding: [0x04,0x05,0xe4,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0xe4,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v1, v2 :: v_dual_and_b32 v6, v255, v3 ; encoding: [0x01,0x05,0xe4,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0xe4,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v255, v2 :: v_dual_and_b32 v6, v2, v3 ; encoding: [0xff,0x05,0xe4,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0xe4,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v2, v2 :: v_dual_and_b32 v6, v3, v3 ; encoding: [0x02,0x05,0xe4,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0xe4,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v3, v2 :: v_dual_and_b32 v6, v4, v3 ; encoding: [0x03,0x05,0xe4,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0xe4,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, s105, v2 :: v_dual_and_b32 v6, s1, v3 ; encoding: [0x69,0x04,0xe4,0xca,0x01,0x06,0x06,0xff]
+0x69,0x04,0xe4,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, s1, v2 :: v_dual_and_b32 v6, s105, v3 ; encoding: [0x01,0x04,0xe4,0xca,0x69,0x06,0x06,0xff]
+0x01,0x04,0xe4,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, ttmp15, v2 :: v_dual_and_b32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xe4,0xca,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xe4,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, exec_hi, v2 :: v_dual_and_b32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xe4,0xca,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xe4,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, exec_lo, v2 :: v_dual_and_b32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xe4,0xca,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xe4,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, m0, v2 :: v_dual_and_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0xe4,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xe4,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, vcc_hi, v2 :: v_dual_and_b32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xe4,0xca,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xe4,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, vcc_lo, v2 :: v_dual_and_b32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xe4,0xca,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xe4,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, 0xaf123456, v2 :: v_dual_and_b32 v6, null, v3 ; encoding: [0xff,0x04,0xe4,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xe4,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, src_scc, v2 :: v_dual_and_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0xe4,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xe4,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_and_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xe4,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xe4,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, -1, v4 :: v_dual_and_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xe4,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xe4,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v6, null, v5 :: v_dual_and_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xe4,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xe4,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, v4, v2 :: v_dual_cndmask_b32 v6, v1, v3 ; encoding: [0x04,0x05,0xd2,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0xd2,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v1, v2 :: v_dual_cndmask_b32 v6, v255, v3 ; encoding: [0x01,0x05,0xd2,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0xd2,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v255, v2 :: v_dual_cndmask_b32 v6, v2, v3 ; encoding: [0xff,0x05,0xd2,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0xd2,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v2, v2 :: v_dual_cndmask_b32 v6, v3, v3 ; encoding: [0x02,0x05,0xd2,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0xd2,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v3, v2 :: v_dual_cndmask_b32 v6, v4, v3 ; encoding: [0x03,0x05,0xd2,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0xd2,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, s105, v2 :: v_dual_cndmask_b32 v6, s105, v3 ; encoding: [0x69,0x04,0xd2,0xca,0x69,0x06,0x06,0xff]
+0x69,0x04,0xd2,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, s1, v2 :: v_dual_cndmask_b32 v6, s1, v3 ; encoding: [0x01,0x04,0xd2,0xca,0x01,0x06,0x06,0xff]
+0x01,0x04,0xd2,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, ttmp15, v2 :: v_dual_cndmask_b32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0xd2,0xca,0x7b,0x06,0x06,0xff]
+0x7b,0x04,0xd2,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, exec_hi, v2 :: v_dual_cndmask_b32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0xd2,0xca,0x7f,0x06,0x06,0xff]
+0x7f,0x04,0xd2,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, exec_lo, v2 :: v_dual_cndmask_b32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0xd2,0xca,0x7e,0x06,0x06,0xff]
+0x7e,0x04,0xd2,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, m0, v2 :: v_dual_cndmask_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0xd2,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xd2,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, vcc_hi, v2 :: v_dual_cndmask_b32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0xd2,0xca,0x6b,0x06,0x06,0xff]
+0x6b,0x04,0xd2,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, vcc_lo, v2 :: v_dual_cndmask_b32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0xd2,0xca,0x6a,0x06,0x06,0xff]
+0x6a,0x04,0xd2,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, 0xaf123456, v2 :: v_dual_cndmask_b32 v6, null, v3 ; encoding: [0xff,0x04,0xd2,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xd2,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, src_scc, v2 :: v_dual_cndmask_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0xd2,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xd2,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_cndmask_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xd2,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xd2,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, -1, v4 :: v_dual_cndmask_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xd2,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xd2,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v6, null, v5 :: v_dual_cndmask_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xd2,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xd2,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, v4, v2 :: v_dual_fmaak_f32 v6, v1, v3, 0xaf123456 ; encoding: [0x04,0x05,0xc2,0xca,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x04,0x05,0xc2,0xca,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, v1, v2 :: v_dual_fmaak_f32 v6, v255, v3, 0xaf123456 ; encoding: [0x01,0x05,0xc2,0xca,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x05,0xc2,0xca,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, v255, v2 :: v_dual_fmaak_f32 v6, v2, v3, 0xaf123456 ; encoding: [0xff,0x05,0xc2,0xca,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x05,0xc2,0xca,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, v2, v2 :: v_dual_fmaak_f32 v6, v3, v3, 0xaf123456 ; encoding: [0x02,0x05,0xc2,0xca,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x02,0x05,0xc2,0xca,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, v3, v2 :: v_dual_fmaak_f32 v6, v4, v3, 0xaf123456 ; encoding: [0x03,0x05,0xc2,0xca,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x03,0x05,0xc2,0xca,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, s105, v2 :: v_dual_fmaak_f32 v6, s105, v3, 0xaf123456 ; encoding: [0x69,0x04,0xc2,0xca,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x69,0x04,0xc2,0xca,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, s1, v2 :: v_dual_fmaak_f32 v6, s1, v3, 0xaf123456 ; encoding: [0x01,0x04,0xc2,0xca,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x04,0xc2,0xca,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, ttmp15, v2 :: v_dual_fmaak_f32 v6, ttmp15, v3, 0xaf123456 ; encoding: [0x7b,0x04,0xc2,0xca,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0x04,0xc2,0xca,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, exec_hi, v2 :: v_dual_fmaak_f32 v6, exec_hi, v3, 0xaf123456 ; encoding: [0x7f,0x04,0xc2,0xca,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0x04,0xc2,0xca,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, exec_lo, v2 :: v_dual_fmaak_f32 v6, exec_lo, v3, 0xaf123456 ; encoding: [0x7e,0x04,0xc2,0xca,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0x04,0xc2,0xca,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, m0, v2 :: v_dual_fmaak_f32 v6, m0, v3, 0xaf123456 ; encoding: [0x7d,0x04,0xc2,0xca,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0x04,0xc2,0xca,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, vcc_hi, v2 :: v_dual_fmaak_f32 v6, vcc_hi, v3, 0xaf123456 ; encoding: [0x6b,0x04,0xc2,0xca,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0x04,0xc2,0xca,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, vcc_lo, v2 :: v_dual_fmaak_f32 v6, vcc_lo, v3, 0xaf123456 ; encoding: [0x6a,0x04,0xc2,0xca,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0x04,0xc2,0xca,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, null, v3, 0xaf123456 ; encoding: [0xff,0x04,0xc2,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xc2,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, src_scc, v2 :: v_dual_fmaak_f32 v6, -1, v3, 0xaf123456 ; encoding: [0xfd,0x04,0xc2,0xca,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0x04,0xc2,0xca,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_fmaak_f32 v6, 0.5, v2, 0xaf123456 ; encoding: [0xf0,0x06,0xc2,0xca,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0xc2,0xca,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, -1, v4 :: v_dual_fmaak_f32 v6, src_scc, v5, 0xaf123456 ; encoding: [0xc1,0x08,0xc2,0xca,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0xc2,0xca,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v6, null, v5 :: v_dual_fmaak_f32 v255, 0xaf123456, v4, 0xaf123456 ; encoding: [0x7c,0x0a,0xc2,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xc2,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, v4, v2 :: v_dual_fmac_f32 v6, v1, v3 ; encoding: [0x04,0x05,0xc0,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0xc0,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v1, v2 :: v_dual_fmac_f32 v6, v255, v3 ; encoding: [0x01,0x05,0xc0,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0xc0,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v255, v2 :: v_dual_fmac_f32 v6, v2, v3 ; encoding: [0xff,0x05,0xc0,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0xc0,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v2, v2 :: v_dual_fmac_f32 v6, v3, v3 ; encoding: [0x02,0x05,0xc0,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0xc0,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v3, v2 :: v_dual_fmac_f32 v6, v4, v3 ; encoding: [0x03,0x05,0xc0,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0xc0,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, s105, v2 :: v_dual_fmac_f32 v6, s1, v3 ; encoding: [0x69,0x04,0xc0,0xca,0x01,0x06,0x06,0xff]
+0x69,0x04,0xc0,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, s1, v2 :: v_dual_fmac_f32 v6, s105, v3 ; encoding: [0x01,0x04,0xc0,0xca,0x69,0x06,0x06,0xff]
+0x01,0x04,0xc0,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, ttmp15, v2 :: v_dual_fmac_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xc0,0xca,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xc0,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, exec_hi, v2 :: v_dual_fmac_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xc0,0xca,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xc0,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, exec_lo, v2 :: v_dual_fmac_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xc0,0xca,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xc0,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, m0, v2 :: v_dual_fmac_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0xc0,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xc0,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, vcc_hi, v2 :: v_dual_fmac_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xc0,0xca,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xc0,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, vcc_lo, v2 :: v_dual_fmac_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xc0,0xca,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xc0,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, 0xaf123456, v2 :: v_dual_fmac_f32 v6, null, v3 ; encoding: [0xff,0x04,0xc0,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xc0,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, src_scc, v2 :: v_dual_fmac_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0xc0,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xc0,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_fmac_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xc0,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xc0,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, -1, v4 :: v_dual_fmac_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xc0,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xc0,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v6, null, v5 :: v_dual_fmac_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xc0,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xc0,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, v4, v255 :: v_dual_fmamk_f32 v6, v1, 0xaf123456, v255 ; encoding: [0x04,0xff,0xc5,0xca,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x04,0xff,0xc5,0xca,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, v1, v255 :: v_dual_fmamk_f32 v6, v255, 0xaf123456, v255 ; encoding: [0x01,0xff,0xc5,0xca,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xff,0xc5,0xca,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, v255, v255 :: v_dual_fmamk_f32 v6, v2, 0xaf123456, v255 ; encoding: [0xff,0xff,0xc5,0xca,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xff,0xc5,0xca,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, v2, v255 :: v_dual_fmamk_f32 v6, v3, 0xaf123456, v255 ; encoding: [0x02,0xff,0xc5,0xca,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x02,0xff,0xc5,0xca,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, v3, v255 :: v_dual_fmamk_f32 v6, v4, 0xaf123456, v255 ; encoding: [0x03,0xff,0xc5,0xca,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x03,0xff,0xc5,0xca,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, s105, v255 :: v_dual_fmamk_f32 v6, s105, 0xaf123456, v255 ; encoding: [0x69,0xfe,0xc5,0xca,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x69,0xfe,0xc5,0xca,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, s1, v255 :: v_dual_fmamk_f32 v6, s1, 0xaf123456, v255 ; encoding: [0x01,0xfe,0xc5,0xca,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xfe,0xc5,0xca,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, ttmp15, v255 :: v_dual_fmamk_f32 v6, ttmp15, 0xaf123456, v255 ; encoding: [0x7b,0xfe,0xc5,0xca,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0xfe,0xc5,0xca,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, exec_hi, v255 :: v_dual_fmamk_f32 v6, exec_hi, 0xaf123456, v255 ; encoding: [0x7f,0xfe,0xc5,0xca,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0xfe,0xc5,0xca,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, exec_lo, v255 :: v_dual_fmamk_f32 v6, exec_lo, 0xaf123456, v255 ; encoding: [0x7e,0xfe,0xc5,0xca,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0xfe,0xc5,0xca,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, m0, v255 :: v_dual_fmamk_f32 v6, m0, 0xaf123456, v255 ; encoding: [0x7d,0xfe,0xc5,0xca,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0xfe,0xc5,0xca,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, vcc_hi, v255 :: v_dual_fmamk_f32 v6, vcc_hi, 0xaf123456, v255 ; encoding: [0x6b,0xfe,0xc5,0xca,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0xfe,0xc5,0xca,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, vcc_lo, v255 :: v_dual_fmamk_f32 v6, vcc_lo, 0xaf123456, v255 ; encoding: [0x6a,0xfe,0xc5,0xca,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0xfe,0xc5,0xca,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, null, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xc5,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xc5,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, src_scc, v255 :: v_dual_fmamk_f32 v6, -1, 0xaf123456, v255 ; encoding: [0xfd,0xfe,0xc5,0xca,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0xfe,0xc5,0xca,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_fmamk_f32 v6, 0.5, 0xaf123456, v255 ; encoding: [0xf0,0x06,0xc4,0xca,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0xc4,0xca,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, -1, v4 :: v_dual_fmamk_f32 v6, src_scc, 0xaf123456, v255 ; encoding: [0xc1,0x08,0xc4,0xca,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0xc4,0xca,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v6, null, v5 :: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xc4,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xc4,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, v4, v2 :: v_dual_lshlrev_b32 v6, v1, v3 ; encoding: [0x04,0x05,0xe2,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0xe2,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v1, v2 :: v_dual_lshlrev_b32 v6, v255, v3 ; encoding: [0x01,0x05,0xe2,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0xe2,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v255, v2 :: v_dual_lshlrev_b32 v6, v2, v3 ; encoding: [0xff,0x05,0xe2,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0xe2,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v2, v2 :: v_dual_lshlrev_b32 v6, v3, v3 ; encoding: [0x02,0x05,0xe2,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0xe2,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v3, v2 :: v_dual_lshlrev_b32 v6, v4, v3 ; encoding: [0x03,0x05,0xe2,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0xe2,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, s105, v2 :: v_dual_lshlrev_b32 v6, s1, v3 ; encoding: [0x69,0x04,0xe2,0xca,0x01,0x06,0x06,0xff]
+0x69,0x04,0xe2,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, s1, v2 :: v_dual_lshlrev_b32 v6, s105, v3 ; encoding: [0x01,0x04,0xe2,0xca,0x69,0x06,0x06,0xff]
+0x01,0x04,0xe2,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, ttmp15, v2 :: v_dual_lshlrev_b32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xe2,0xca,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xe2,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, exec_hi, v2 :: v_dual_lshlrev_b32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xe2,0xca,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xe2,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, exec_lo, v2 :: v_dual_lshlrev_b32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xe2,0xca,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xe2,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, m0, v2 :: v_dual_lshlrev_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0xe2,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xe2,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, vcc_hi, v2 :: v_dual_lshlrev_b32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xe2,0xca,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xe2,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, vcc_lo, v2 :: v_dual_lshlrev_b32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xe2,0xca,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xe2,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, 0xaf123456, v2 :: v_dual_lshlrev_b32 v6, null, v3 ; encoding: [0xff,0x04,0xe2,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xe2,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, src_scc, v2 :: v_dual_lshlrev_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0xe2,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xe2,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_lshlrev_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xe2,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xe2,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, -1, v4 :: v_dual_lshlrev_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xe2,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xe2,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v6, null, v5 :: v_dual_lshlrev_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xe2,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xe2,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, v4, v2 :: v_dual_max_num_f32 v6, v1, v3 ; encoding: [0x04,0x05,0xd4,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0xd4,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v1, v2 :: v_dual_max_num_f32 v6, v255, v3 ; encoding: [0x01,0x05,0xd4,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0xd4,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v255, v2 :: v_dual_max_num_f32 v6, v2, v3 ; encoding: [0xff,0x05,0xd4,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0xd4,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v2, v2 :: v_dual_max_num_f32 v6, v3, v3 ; encoding: [0x02,0x05,0xd4,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0xd4,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v3, v2 :: v_dual_max_num_f32 v6, v4, v3 ; encoding: [0x03,0x05,0xd4,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0xd4,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, s105, v2 :: v_dual_max_num_f32 v6, s1, v3 ; encoding: [0x69,0x04,0xd4,0xca,0x01,0x06,0x06,0xff]
+0x69,0x04,0xd4,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, s1, v2 :: v_dual_max_num_f32 v6, s105, v3 ; encoding: [0x01,0x04,0xd4,0xca,0x69,0x06,0x06,0xff]
+0x01,0x04,0xd4,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, ttmp15, v2 :: v_dual_max_num_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xd4,0xca,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xd4,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, exec_hi, v2 :: v_dual_max_num_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xd4,0xca,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xd4,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, exec_lo, v2 :: v_dual_max_num_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xd4,0xca,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xd4,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, m0, v2 :: v_dual_max_num_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0xd4,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xd4,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, vcc_hi, v2 :: v_dual_max_num_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xd4,0xca,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xd4,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, vcc_lo, v2 :: v_dual_max_num_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xd4,0xca,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xd4,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, 0xaf123456, v2 :: v_dual_max_num_f32 v6, null, v3 ; encoding: [0xff,0x04,0xd4,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xd4,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, src_scc, v2 :: v_dual_max_num_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0xd4,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xd4,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_max_num_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xd4,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xd4,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, -1, v4 :: v_dual_max_num_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xd4,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xd4,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v6, null, v5 :: v_dual_max_num_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xd4,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xd4,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, v4, v2 :: v_dual_min_num_f32 v6, v1, v3 ; encoding: [0x04,0x05,0xd6,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0xd6,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v1, v2 :: v_dual_min_num_f32 v6, v255, v3 ; encoding: [0x01,0x05,0xd6,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0xd6,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v255, v2 :: v_dual_min_num_f32 v6, v2, v3 ; encoding: [0xff,0x05,0xd6,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0xd6,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v2, v2 :: v_dual_min_num_f32 v6, v3, v3 ; encoding: [0x02,0x05,0xd6,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0xd6,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v3, v2 :: v_dual_min_num_f32 v6, v4, v3 ; encoding: [0x03,0x05,0xd6,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0xd6,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, s105, v2 :: v_dual_min_num_f32 v6, s1, v3 ; encoding: [0x69,0x04,0xd6,0xca,0x01,0x06,0x06,0xff]
+0x69,0x04,0xd6,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, s1, v2 :: v_dual_min_num_f32 v6, s105, v3 ; encoding: [0x01,0x04,0xd6,0xca,0x69,0x06,0x06,0xff]
+0x01,0x04,0xd6,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, ttmp15, v2 :: v_dual_min_num_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xd6,0xca,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xd6,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, exec_hi, v2 :: v_dual_min_num_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xd6,0xca,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xd6,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, exec_lo, v2 :: v_dual_min_num_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xd6,0xca,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xd6,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, m0, v2 :: v_dual_min_num_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0xd6,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xd6,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, vcc_hi, v2 :: v_dual_min_num_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xd6,0xca,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xd6,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, vcc_lo, v2 :: v_dual_min_num_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xd6,0xca,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xd6,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, 0xaf123456, v2 :: v_dual_min_num_f32 v6, null, v3 ; encoding: [0xff,0x04,0xd6,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xd6,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, src_scc, v2 :: v_dual_min_num_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0xd6,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xd6,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_min_num_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xd6,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xd6,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, -1, v4 :: v_dual_min_num_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xd6,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xd6,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v6, null, v5 :: v_dual_min_num_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xd6,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xd6,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, v4, v255 :: v_dual_mov_b32 v6, v1 ; encoding: [0x04,0xff,0xd1,0xca,0x01,0x01,0x06,0xff]
+0x04,0xff,0xd1,0xca,0x01,0x01,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v1, v255 :: v_dual_mov_b32 v6, v255 ; encoding: [0x01,0xff,0xd1,0xca,0xff,0x01,0x06,0xff]
+0x01,0xff,0xd1,0xca,0xff,0x01,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v255, v255 :: v_dual_mov_b32 v6, v2 ; encoding: [0xff,0xff,0xd1,0xca,0x02,0x01,0x06,0xff]
+0xff,0xff,0xd1,0xca,0x02,0x01,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v2, v255 :: v_dual_mov_b32 v6, v3 ; encoding: [0x02,0xff,0xd1,0xca,0x03,0x01,0x06,0xff]
+0x02,0xff,0xd1,0xca,0x03,0x01,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v3, v255 :: v_dual_mov_b32 v6, v4 ; encoding: [0x03,0xff,0xd1,0xca,0x04,0x01,0x06,0xff]
+0x03,0xff,0xd1,0xca,0x04,0x01,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, s105, v255 :: v_dual_mov_b32 v6, s1 ; encoding: [0x69,0xfe,0xd1,0xca,0x01,0x00,0x06,0xff]
+0x69,0xfe,0xd1,0xca,0x01,0x00,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, s1, v255 :: v_dual_mov_b32 v6, s105 ; encoding: [0x01,0xfe,0xd1,0xca,0x69,0x00,0x06,0xff]
+0x01,0xfe,0xd1,0xca,0x69,0x00,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, ttmp15, v255 :: v_dual_mov_b32 v6, vcc_lo ; encoding: [0x7b,0xfe,0xd1,0xca,0x6a,0x00,0x06,0xff]
+0x7b,0xfe,0xd1,0xca,0x6a,0x00,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, exec_hi, v255 :: v_dual_mov_b32 v6, vcc_hi ; encoding: [0x7f,0xfe,0xd1,0xca,0x6b,0x00,0x06,0xff]
+0x7f,0xfe,0xd1,0xca,0x6b,0x00,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, exec_lo, v255 :: v_dual_mov_b32 v6, ttmp15 ; encoding: [0x7e,0xfe,0xd1,0xca,0x7b,0x00,0x06,0xff]
+0x7e,0xfe,0xd1,0xca,0x7b,0x00,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, m0, v255 :: v_dual_mov_b32 v6, m0 ; encoding: [0x7d,0xfe,0xd1,0xca,0x7d,0x00,0x06,0xff]
+0x7d,0xfe,0xd1,0xca,0x7d,0x00,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, vcc_hi, v255 :: v_dual_mov_b32 v6, exec_lo ; encoding: [0x6b,0xfe,0xd1,0xca,0x7e,0x00,0x06,0xff]
+0x6b,0xfe,0xd1,0xca,0x7e,0x00,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, vcc_lo, v255 :: v_dual_mov_b32 v6, exec_hi ; encoding: [0x6a,0xfe,0xd1,0xca,0x7f,0x00,0x06,0xff]
+0x6a,0xfe,0xd1,0xca,0x7f,0x00,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, 0xaf123456, v255 :: v_dual_mov_b32 v6, null ; encoding: [0xff,0xfe,0xd1,0xca,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xd1,0xca,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, src_scc, v255 :: v_dual_mov_b32 v6, -1 ; encoding: [0xfd,0xfe,0xd1,0xca,0xc1,0x00,0x06,0xff]
+0xfd,0xfe,0xd1,0xca,0xc1,0x00,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_mov_b32 v6, 0.5 ; encoding: [0xf0,0x06,0xd0,0xca,0xf0,0x00,0x06,0xff]
+0xf0,0x06,0xd0,0xca,0xf0,0x00,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, -1, v4 :: v_dual_mov_b32 v6, src_scc ; encoding: [0xc1,0x08,0xd0,0xca,0xfd,0x00,0x06,0xff]
+0xc1,0x08,0xd0,0xca,0xfd,0x00,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v6, null, v5 :: v_dual_mov_b32 v255, 0xaf123456 ; encoding: [0x7c,0x0a,0xd0,0xca,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xd0,0xca,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, v4, v2 :: v_dual_mul_dx9_zero_f32 v6, v1, v3 ; encoding: [0x04,0x05,0xce,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0xce,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v1, v2 :: v_dual_mul_dx9_zero_f32 v6, v255, v3 ; encoding: [0x01,0x05,0xce,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0xce,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v255, v2 :: v_dual_mul_dx9_zero_f32 v6, v2, v3 ; encoding: [0xff,0x05,0xce,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0xce,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v2, v2 :: v_dual_mul_dx9_zero_f32 v6, v3, v3 ; encoding: [0x02,0x05,0xce,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0xce,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v3, v2 :: v_dual_mul_dx9_zero_f32 v6, v4, v3 ; encoding: [0x03,0x05,0xce,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0xce,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, s105, v2 :: v_dual_mul_dx9_zero_f32 v6, s1, v3 ; encoding: [0x69,0x04,0xce,0xca,0x01,0x06,0x06,0xff]
+0x69,0x04,0xce,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, s1, v2 :: v_dual_mul_dx9_zero_f32 v6, s105, v3 ; encoding: [0x01,0x04,0xce,0xca,0x69,0x06,0x06,0xff]
+0x01,0x04,0xce,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, ttmp15, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xce,0xca,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xce,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, exec_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xce,0xca,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xce,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, exec_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xce,0xca,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xce,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, m0, v2 :: v_dual_mul_dx9_zero_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0xce,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xce,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, vcc_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xce,0xca,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xce,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, vcc_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xce,0xca,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xce,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, 0xaf123456, v2 :: v_dual_mul_dx9_zero_f32 v6, null, v3 ; encoding: [0xff,0x04,0xce,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xce,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, src_scc, v2 :: v_dual_mul_dx9_zero_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0xce,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xce,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_mul_dx9_zero_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xce,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xce,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, -1, v4 :: v_dual_mul_dx9_zero_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xce,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xce,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v6, null, v5 :: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xce,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xce,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, v4, v2 :: v_dual_mul_f32 v6, v1, v3 ; encoding: [0x04,0x05,0xc6,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0xc6,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v1, v2 :: v_dual_mul_f32 v6, v255, v3 ; encoding: [0x01,0x05,0xc6,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0xc6,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v255, v2 :: v_dual_mul_f32 v6, v2, v3 ; encoding: [0xff,0x05,0xc6,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0xc6,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v2, v2 :: v_dual_mul_f32 v6, v3, v3 ; encoding: [0x02,0x05,0xc6,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0xc6,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v3, v2 :: v_dual_mul_f32 v6, v4, v3 ; encoding: [0x03,0x05,0xc6,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0xc6,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, s105, v2 :: v_dual_mul_f32 v6, s1, v3 ; encoding: [0x69,0x04,0xc6,0xca,0x01,0x06,0x06,0xff]
+0x69,0x04,0xc6,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, s1, v2 :: v_dual_mul_f32 v6, s105, v3 ; encoding: [0x01,0x04,0xc6,0xca,0x69,0x06,0x06,0xff]
+0x01,0x04,0xc6,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, ttmp15, v2 :: v_dual_mul_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xc6,0xca,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xc6,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, exec_hi, v2 :: v_dual_mul_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xc6,0xca,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xc6,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, exec_lo, v2 :: v_dual_mul_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xc6,0xca,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xc6,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, m0, v2 :: v_dual_mul_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0xc6,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xc6,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, vcc_hi, v2 :: v_dual_mul_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xc6,0xca,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xc6,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, vcc_lo, v2 :: v_dual_mul_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xc6,0xca,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xc6,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, 0xaf123456, v2 :: v_dual_mul_f32 v6, null, v3 ; encoding: [0xff,0x04,0xc6,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xc6,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, src_scc, v2 :: v_dual_mul_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0xc6,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xc6,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_mul_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xc6,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xc6,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, -1, v4 :: v_dual_mul_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xc6,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xc6,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v6, null, v5 :: v_dual_mul_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xc6,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xc6,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, v4, v2 :: v_dual_sub_f32 v6, v1, v3 ; encoding: [0x04,0x05,0xca,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0xca,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v1, v2 :: v_dual_sub_f32 v6, v255, v3 ; encoding: [0x01,0x05,0xca,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0xca,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v255, v2 :: v_dual_sub_f32 v6, v2, v3 ; encoding: [0xff,0x05,0xca,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0xca,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v2, v2 :: v_dual_sub_f32 v6, v3, v3 ; encoding: [0x02,0x05,0xca,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0xca,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v3, v2 :: v_dual_sub_f32 v6, v4, v3 ; encoding: [0x03,0x05,0xca,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0xca,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, s105, v2 :: v_dual_sub_f32 v6, s1, v3 ; encoding: [0x69,0x04,0xca,0xca,0x01,0x06,0x06,0xff]
+0x69,0x04,0xca,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, s1, v2 :: v_dual_sub_f32 v6, s105, v3 ; encoding: [0x01,0x04,0xca,0xca,0x69,0x06,0x06,0xff]
+0x01,0x04,0xca,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, ttmp15, v2 :: v_dual_sub_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xca,0xca,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xca,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, exec_hi, v2 :: v_dual_sub_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xca,0xca,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xca,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, exec_lo, v2 :: v_dual_sub_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xca,0xca,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xca,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, m0, v2 :: v_dual_sub_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0xca,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xca,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, vcc_hi, v2 :: v_dual_sub_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xca,0xca,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xca,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, vcc_lo, v2 :: v_dual_sub_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xca,0xca,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xca,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, 0xaf123456, v2 :: v_dual_sub_f32 v6, null, v3 ; encoding: [0xff,0x04,0xca,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xca,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, src_scc, v2 :: v_dual_sub_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0xca,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xca,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_sub_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xca,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xca,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, -1, v4 :: v_dual_sub_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xca,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xca,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v6, null, v5 :: v_dual_sub_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xca,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xca,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, v4, v2 :: v_dual_subrev_f32 v6, v1, v3 ; encoding: [0x04,0x05,0xcc,0xca,0x01,0x07,0x06,0xff]
+0x04,0x05,0xcc,0xca,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v1, v2 :: v_dual_subrev_f32 v6, v255, v3 ; encoding: [0x01,0x05,0xcc,0xca,0xff,0x07,0x06,0xff]
+0x01,0x05,0xcc,0xca,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v255, v2 :: v_dual_subrev_f32 v6, v2, v3 ; encoding: [0xff,0x05,0xcc,0xca,0x02,0x07,0x06,0xff]
+0xff,0x05,0xcc,0xca,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v2, v2 :: v_dual_subrev_f32 v6, v3, v3 ; encoding: [0x02,0x05,0xcc,0xca,0x03,0x07,0x06,0xff]
+0x02,0x05,0xcc,0xca,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, v3, v2 :: v_dual_subrev_f32 v6, v4, v3 ; encoding: [0x03,0x05,0xcc,0xca,0x04,0x07,0x06,0xff]
+0x03,0x05,0xcc,0xca,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, s105, v2 :: v_dual_subrev_f32 v6, s1, v3 ; encoding: [0x69,0x04,0xcc,0xca,0x01,0x06,0x06,0xff]
+0x69,0x04,0xcc,0xca,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, s1, v2 :: v_dual_subrev_f32 v6, s105, v3 ; encoding: [0x01,0x04,0xcc,0xca,0x69,0x06,0x06,0xff]
+0x01,0x04,0xcc,0xca,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, ttmp15, v2 :: v_dual_subrev_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xcc,0xca,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xcc,0xca,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, exec_hi, v2 :: v_dual_subrev_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xcc,0xca,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xcc,0xca,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, exec_lo, v2 :: v_dual_subrev_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xcc,0xca,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xcc,0xca,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, m0, v2 :: v_dual_subrev_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0xcc,0xca,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xcc,0xca,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, vcc_hi, v2 :: v_dual_subrev_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xcc,0xca,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xcc,0xca,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, vcc_lo, v2 :: v_dual_subrev_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xcc,0xca,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xcc,0xca,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, 0xaf123456, v2 :: v_dual_subrev_f32 v6, null, v3 ; encoding: [0xff,0x04,0xcc,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xcc,0xca,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_min_num_f32 v255, src_scc, v2 :: v_dual_subrev_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0xcc,0xca,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xcc,0xca,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, 0.5, v3 :: v_dual_subrev_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xcc,0xca,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xcc,0xca,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v255, -1, v4 :: v_dual_subrev_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xcc,0xca,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xcc,0xca,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_min_num_f32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xcc,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xcc,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, v4 :: v_dual_add_f32 v6, v1, v255 ; encoding: [0x04,0x01,0x08,0xca,0x01,0xff,0x07,0xff]
+0x04,0x01,0x08,0xca,0x01,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v1 :: v_dual_add_f32 v6, v255, v255 ; encoding: [0x01,0x01,0x08,0xca,0xff,0xff,0x07,0xff]
+0x01,0x01,0x08,0xca,0xff,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v255 :: v_dual_add_f32 v6, v2, v255 ; encoding: [0xff,0x01,0x08,0xca,0x02,0xff,0x07,0xff]
+0xff,0x01,0x08,0xca,0x02,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v2 :: v_dual_add_f32 v6, v3, v255 ; encoding: [0x02,0x01,0x08,0xca,0x03,0xff,0x07,0xff]
+0x02,0x01,0x08,0xca,0x03,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v3 :: v_dual_add_f32 v6, v4, v255 ; encoding: [0x03,0x01,0x08,0xca,0x04,0xff,0x07,0xff]
+0x03,0x01,0x08,0xca,0x04,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, s105 :: v_dual_add_f32 v6, s1, v255 ; encoding: [0x69,0x00,0x08,0xca,0x01,0xfe,0x07,0xff]
+0x69,0x00,0x08,0xca,0x01,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, s1 :: v_dual_add_f32 v6, s105, v255 ; encoding: [0x01,0x00,0x08,0xca,0x69,0xfe,0x07,0xff]
+0x01,0x00,0x08,0xca,0x69,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, ttmp15 :: v_dual_add_f32 v6, vcc_lo, v255 ; encoding: [0x7b,0x00,0x08,0xca,0x6a,0xfe,0x07,0xff]
+0x7b,0x00,0x08,0xca,0x6a,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, exec_hi :: v_dual_add_f32 v6, vcc_hi, v255 ; encoding: [0x7f,0x00,0x08,0xca,0x6b,0xfe,0x07,0xff]
+0x7f,0x00,0x08,0xca,0x6b,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, exec_lo :: v_dual_add_f32 v6, ttmp15, v255 ; encoding: [0x7e,0x00,0x08,0xca,0x7b,0xfe,0x07,0xff]
+0x7e,0x00,0x08,0xca,0x7b,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, m0 :: v_dual_add_f32 v6, m0, v255 ; encoding: [0x7d,0x00,0x08,0xca,0x7d,0xfe,0x07,0xff]
+0x7d,0x00,0x08,0xca,0x7d,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, vcc_hi :: v_dual_add_f32 v6, exec_lo, v255 ; encoding: [0x6b,0x00,0x08,0xca,0x7e,0xfe,0x07,0xff]
+0x6b,0x00,0x08,0xca,0x7e,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, vcc_lo :: v_dual_add_f32 v6, exec_hi, v255 ; encoding: [0x6a,0x00,0x08,0xca,0x7f,0xfe,0x07,0xff]
+0x6a,0x00,0x08,0xca,0x7f,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, 0xaf123456 :: v_dual_add_f32 v6, null, v255 ; encoding: [0xff,0x00,0x08,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x08,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, src_scc :: v_dual_add_f32 v6, -1, v255 ; encoding: [0xfd,0x00,0x08,0xca,0xc1,0xfe,0x07,0xff]
+0xfd,0x00,0x08,0xca,0xc1,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, 0.5 :: v_dual_add_f32 v6, 0.5, v3 ; encoding: [0xf0,0x00,0x08,0xca,0xf0,0x06,0x06,0xff]
+0xf0,0x00,0x08,0xca,0xf0,0x06,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v255, -1 :: v_dual_add_f32 v6, src_scc, v4 ; encoding: [0xc1,0x00,0x08,0xca,0xfd,0x08,0x06,0xff]
+0xc1,0x00,0x08,0xca,0xfd,0x08,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v6, null :: v_dual_add_f32 v255, 0xaf123456, v5 ; encoding: [0x7c,0x00,0x08,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x08,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, v4 :: v_dual_add_nc_u32 v6, v1, v255 ; encoding: [0x04,0x01,0x20,0xca,0x01,0xff,0x07,0xff]
+0x04,0x01,0x20,0xca,0x01,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v1 :: v_dual_add_nc_u32 v6, v255, v255 ; encoding: [0x01,0x01,0x20,0xca,0xff,0xff,0x07,0xff]
+0x01,0x01,0x20,0xca,0xff,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v255 :: v_dual_add_nc_u32 v6, v2, v255 ; encoding: [0xff,0x01,0x20,0xca,0x02,0xff,0x07,0xff]
+0xff,0x01,0x20,0xca,0x02,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v2 :: v_dual_add_nc_u32 v6, v3, v255 ; encoding: [0x02,0x01,0x20,0xca,0x03,0xff,0x07,0xff]
+0x02,0x01,0x20,0xca,0x03,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v3 :: v_dual_add_nc_u32 v6, v4, v255 ; encoding: [0x03,0x01,0x20,0xca,0x04,0xff,0x07,0xff]
+0x03,0x01,0x20,0xca,0x04,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, s105 :: v_dual_add_nc_u32 v6, s1, v255 ; encoding: [0x69,0x00,0x20,0xca,0x01,0xfe,0x07,0xff]
+0x69,0x00,0x20,0xca,0x01,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, s1 :: v_dual_add_nc_u32 v6, s105, v255 ; encoding: [0x01,0x00,0x20,0xca,0x69,0xfe,0x07,0xff]
+0x01,0x00,0x20,0xca,0x69,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, ttmp15 :: v_dual_add_nc_u32 v6, vcc_lo, v255 ; encoding: [0x7b,0x00,0x20,0xca,0x6a,0xfe,0x07,0xff]
+0x7b,0x00,0x20,0xca,0x6a,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, exec_hi :: v_dual_add_nc_u32 v6, vcc_hi, v255 ; encoding: [0x7f,0x00,0x20,0xca,0x6b,0xfe,0x07,0xff]
+0x7f,0x00,0x20,0xca,0x6b,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, exec_lo :: v_dual_add_nc_u32 v6, ttmp15, v255 ; encoding: [0x7e,0x00,0x20,0xca,0x7b,0xfe,0x07,0xff]
+0x7e,0x00,0x20,0xca,0x7b,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, m0 :: v_dual_add_nc_u32 v6, m0, v255 ; encoding: [0x7d,0x00,0x20,0xca,0x7d,0xfe,0x07,0xff]
+0x7d,0x00,0x20,0xca,0x7d,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, vcc_hi :: v_dual_add_nc_u32 v6, exec_lo, v255 ; encoding: [0x6b,0x00,0x20,0xca,0x7e,0xfe,0x07,0xff]
+0x6b,0x00,0x20,0xca,0x7e,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, vcc_lo :: v_dual_add_nc_u32 v6, exec_hi, v255 ; encoding: [0x6a,0x00,0x20,0xca,0x7f,0xfe,0x07,0xff]
+0x6a,0x00,0x20,0xca,0x7f,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, 0xaf123456 :: v_dual_add_nc_u32 v6, null, v255 ; encoding: [0xff,0x00,0x20,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x20,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, src_scc :: v_dual_add_nc_u32 v6, -1, v255 ; encoding: [0xfd,0x00,0x20,0xca,0xc1,0xfe,0x07,0xff]
+0xfd,0x00,0x20,0xca,0xc1,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, 0.5 :: v_dual_add_nc_u32 v6, 0.5, v3 ; encoding: [0xf0,0x00,0x20,0xca,0xf0,0x06,0x06,0xff]
+0xf0,0x00,0x20,0xca,0xf0,0x06,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v255, -1 :: v_dual_add_nc_u32 v6, src_scc, v4 ; encoding: [0xc1,0x00,0x20,0xca,0xfd,0x08,0x06,0xff]
+0xc1,0x00,0x20,0xca,0xfd,0x08,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v6, null :: v_dual_add_nc_u32 v255, 0xaf123456, v5 ; encoding: [0x7c,0x00,0x20,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x20,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, v4 :: v_dual_and_b32 v6, v1, v255 ; encoding: [0x04,0x01,0x24,0xca,0x01,0xff,0x07,0xff]
+0x04,0x01,0x24,0xca,0x01,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v1 :: v_dual_and_b32 v6, v255, v255 ; encoding: [0x01,0x01,0x24,0xca,0xff,0xff,0x07,0xff]
+0x01,0x01,0x24,0xca,0xff,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v255 :: v_dual_and_b32 v6, v2, v255 ; encoding: [0xff,0x01,0x24,0xca,0x02,0xff,0x07,0xff]
+0xff,0x01,0x24,0xca,0x02,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v2 :: v_dual_and_b32 v6, v3, v255 ; encoding: [0x02,0x01,0x24,0xca,0x03,0xff,0x07,0xff]
+0x02,0x01,0x24,0xca,0x03,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v3 :: v_dual_and_b32 v6, v4, v255 ; encoding: [0x03,0x01,0x24,0xca,0x04,0xff,0x07,0xff]
+0x03,0x01,0x24,0xca,0x04,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, s105 :: v_dual_and_b32 v6, s1, v255 ; encoding: [0x69,0x00,0x24,0xca,0x01,0xfe,0x07,0xff]
+0x69,0x00,0x24,0xca,0x01,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, s1 :: v_dual_and_b32 v6, s105, v255 ; encoding: [0x01,0x00,0x24,0xca,0x69,0xfe,0x07,0xff]
+0x01,0x00,0x24,0xca,0x69,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, ttmp15 :: v_dual_and_b32 v6, vcc_lo, v255 ; encoding: [0x7b,0x00,0x24,0xca,0x6a,0xfe,0x07,0xff]
+0x7b,0x00,0x24,0xca,0x6a,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, exec_hi :: v_dual_and_b32 v6, vcc_hi, v255 ; encoding: [0x7f,0x00,0x24,0xca,0x6b,0xfe,0x07,0xff]
+0x7f,0x00,0x24,0xca,0x6b,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, exec_lo :: v_dual_and_b32 v6, ttmp15, v255 ; encoding: [0x7e,0x00,0x24,0xca,0x7b,0xfe,0x07,0xff]
+0x7e,0x00,0x24,0xca,0x7b,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, m0 :: v_dual_and_b32 v6, m0, v255 ; encoding: [0x7d,0x00,0x24,0xca,0x7d,0xfe,0x07,0xff]
+0x7d,0x00,0x24,0xca,0x7d,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, vcc_hi :: v_dual_and_b32 v6, exec_lo, v255 ; encoding: [0x6b,0x00,0x24,0xca,0x7e,0xfe,0x07,0xff]
+0x6b,0x00,0x24,0xca,0x7e,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, vcc_lo :: v_dual_and_b32 v6, exec_hi, v255 ; encoding: [0x6a,0x00,0x24,0xca,0x7f,0xfe,0x07,0xff]
+0x6a,0x00,0x24,0xca,0x7f,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, 0xaf123456 :: v_dual_and_b32 v6, null, v255 ; encoding: [0xff,0x00,0x24,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x24,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, src_scc :: v_dual_and_b32 v6, -1, v255 ; encoding: [0xfd,0x00,0x24,0xca,0xc1,0xfe,0x07,0xff]
+0xfd,0x00,0x24,0xca,0xc1,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, 0.5 :: v_dual_and_b32 v6, 0.5, v3 ; encoding: [0xf0,0x00,0x24,0xca,0xf0,0x06,0x06,0xff]
+0xf0,0x00,0x24,0xca,0xf0,0x06,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v255, -1 :: v_dual_and_b32 v6, src_scc, v4 ; encoding: [0xc1,0x00,0x24,0xca,0xfd,0x08,0x06,0xff]
+0xc1,0x00,0x24,0xca,0xfd,0x08,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v6, null :: v_dual_and_b32 v255, 0xaf123456, v5 ; encoding: [0x7c,0x00,0x24,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x24,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, v4 :: v_dual_cndmask_b32 v6, v1, v255 ; encoding: [0x04,0x01,0x12,0xca,0x01,0xff,0x07,0xff]
+0x04,0x01,0x12,0xca,0x01,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v1 :: v_dual_cndmask_b32 v6, v255, v255 ; encoding: [0x01,0x01,0x12,0xca,0xff,0xff,0x07,0xff]
+0x01,0x01,0x12,0xca,0xff,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v255 :: v_dual_cndmask_b32 v6, v2, v255 ; encoding: [0xff,0x01,0x12,0xca,0x02,0xff,0x07,0xff]
+0xff,0x01,0x12,0xca,0x02,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v2 :: v_dual_cndmask_b32 v6, v3, v255 ; encoding: [0x02,0x01,0x12,0xca,0x03,0xff,0x07,0xff]
+0x02,0x01,0x12,0xca,0x03,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v3 :: v_dual_cndmask_b32 v6, v4, v255 ; encoding: [0x03,0x01,0x12,0xca,0x04,0xff,0x07,0xff]
+0x03,0x01,0x12,0xca,0x04,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, s105 :: v_dual_cndmask_b32 v6, s105, v255 ; encoding: [0x69,0x00,0x12,0xca,0x69,0xfe,0x07,0xff]
+0x69,0x00,0x12,0xca,0x69,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, s1 :: v_dual_cndmask_b32 v6, s1, v255 ; encoding: [0x01,0x00,0x12,0xca,0x01,0xfe,0x07,0xff]
+0x01,0x00,0x12,0xca,0x01,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, ttmp15 :: v_dual_cndmask_b32 v6, ttmp15, v255 ; encoding: [0x7b,0x00,0x12,0xca,0x7b,0xfe,0x07,0xff]
+0x7b,0x00,0x12,0xca,0x7b,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, exec_hi :: v_dual_cndmask_b32 v6, exec_hi, v255 ; encoding: [0x7f,0x00,0x12,0xca,0x7f,0xfe,0x07,0xff]
+0x7f,0x00,0x12,0xca,0x7f,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, exec_lo :: v_dual_cndmask_b32 v6, exec_lo, v255 ; encoding: [0x7e,0x00,0x12,0xca,0x7e,0xfe,0x07,0xff]
+0x7e,0x00,0x12,0xca,0x7e,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, m0 :: v_dual_cndmask_b32 v6, m0, v255 ; encoding: [0x7d,0x00,0x12,0xca,0x7d,0xfe,0x07,0xff]
+0x7d,0x00,0x12,0xca,0x7d,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, vcc_hi :: v_dual_cndmask_b32 v6, vcc_hi, v255 ; encoding: [0x6b,0x00,0x12,0xca,0x6b,0xfe,0x07,0xff]
+0x6b,0x00,0x12,0xca,0x6b,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, vcc_lo :: v_dual_cndmask_b32 v6, vcc_lo, v255 ; encoding: [0x6a,0x00,0x12,0xca,0x6a,0xfe,0x07,0xff]
+0x6a,0x00,0x12,0xca,0x6a,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, 0xaf123456 :: v_dual_cndmask_b32 v6, null, v255 ; encoding: [0xff,0x00,0x12,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x12,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, src_scc :: v_dual_cndmask_b32 v6, -1, v255 ; encoding: [0xfd,0x00,0x12,0xca,0xc1,0xfe,0x07,0xff]
+0xfd,0x00,0x12,0xca,0xc1,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, 0.5 :: v_dual_cndmask_b32 v6, 0.5, v3 ; encoding: [0xf0,0x00,0x12,0xca,0xf0,0x06,0x06,0xff]
+0xf0,0x00,0x12,0xca,0xf0,0x06,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v255, -1 :: v_dual_cndmask_b32 v6, src_scc, v4 ; encoding: [0xc1,0x00,0x12,0xca,0xfd,0x08,0x06,0xff]
+0xc1,0x00,0x12,0xca,0xfd,0x08,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v6, null :: v_dual_cndmask_b32 v255, 0xaf123456, v5 ; encoding: [0x7c,0x00,0x12,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x12,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, v4 :: v_dual_fmaak_f32 v6, v1, v255, 0xaf123456 ; encoding: [0x04,0x01,0x02,0xca,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x04,0x01,0x02,0xca,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, v1 :: v_dual_fmaak_f32 v6, v255, v255, 0xaf123456 ; encoding: [0x01,0x01,0x02,0xca,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x01,0x02,0xca,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, v255 :: v_dual_fmaak_f32 v6, v2, v255, 0xaf123456 ; encoding: [0xff,0x01,0x02,0xca,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x01,0x02,0xca,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, v2 :: v_dual_fmaak_f32 v6, v3, v255, 0xaf123456 ; encoding: [0x02,0x01,0x02,0xca,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x02,0x01,0x02,0xca,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, v3 :: v_dual_fmaak_f32 v6, v4, v255, 0xaf123456 ; encoding: [0x03,0x01,0x02,0xca,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x03,0x01,0x02,0xca,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, s105 :: v_dual_fmaak_f32 v6, s105, v255, 0xaf123456 ; encoding: [0x69,0x00,0x02,0xca,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x69,0x00,0x02,0xca,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, s1 :: v_dual_fmaak_f32 v6, s1, v255, 0xaf123456 ; encoding: [0x01,0x00,0x02,0xca,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x00,0x02,0xca,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, ttmp15 :: v_dual_fmaak_f32 v6, ttmp15, v255, 0xaf123456 ; encoding: [0x7b,0x00,0x02,0xca,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0x00,0x02,0xca,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, exec_hi :: v_dual_fmaak_f32 v6, exec_hi, v255, 0xaf123456 ; encoding: [0x7f,0x00,0x02,0xca,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0x00,0x02,0xca,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, exec_lo :: v_dual_fmaak_f32 v6, exec_lo, v255, 0xaf123456 ; encoding: [0x7e,0x00,0x02,0xca,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0x02,0xca,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, m0 :: v_dual_fmaak_f32 v6, m0, v255, 0xaf123456 ; encoding: [0x7d,0x00,0x02,0xca,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0x00,0x02,0xca,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, vcc_hi :: v_dual_fmaak_f32 v6, vcc_hi, v255, 0xaf123456 ; encoding: [0x6b,0x00,0x02,0xca,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0x00,0x02,0xca,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, vcc_lo :: v_dual_fmaak_f32 v6, vcc_lo, v255, 0xaf123456 ; encoding: [0x6a,0x00,0x02,0xca,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0x00,0x02,0xca,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, 0xaf123456 :: v_dual_fmaak_f32 v6, null, v255, 0xaf123456 ; encoding: [0xff,0x00,0x02,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x02,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, src_scc :: v_dual_fmaak_f32 v6, -1, v255, 0xaf123456 ; encoding: [0xfd,0x00,0x02,0xca,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0x00,0x02,0xca,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, 0.5 :: v_dual_fmaak_f32 v6, 0.5, v3, 0xaf123456 ; encoding: [0xf0,0x00,0x02,0xca,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x00,0x02,0xca,0xf0,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, -1 :: v_dual_fmaak_f32 v6, src_scc, v4, 0xaf123456 ; encoding: [0xc1,0x00,0x02,0xca,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x00,0x02,0xca,0xfd,0x08,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v6, null :: v_dual_fmaak_f32 v255, 0xaf123456, v5, 0xaf123456 ; encoding: [0x7c,0x00,0x02,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x02,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, v4 :: v_dual_fmac_f32 v6, v1, v255 ; encoding: [0x04,0x01,0x00,0xca,0x01,0xff,0x07,0xff]
+0x04,0x01,0x00,0xca,0x01,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v1 :: v_dual_fmac_f32 v6, v255, v255 ; encoding: [0x01,0x01,0x00,0xca,0xff,0xff,0x07,0xff]
+0x01,0x01,0x00,0xca,0xff,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v255 :: v_dual_fmac_f32 v6, v2, v255 ; encoding: [0xff,0x01,0x00,0xca,0x02,0xff,0x07,0xff]
+0xff,0x01,0x00,0xca,0x02,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v2 :: v_dual_fmac_f32 v6, v3, v255 ; encoding: [0x02,0x01,0x00,0xca,0x03,0xff,0x07,0xff]
+0x02,0x01,0x00,0xca,0x03,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v3 :: v_dual_fmac_f32 v6, v4, v255 ; encoding: [0x03,0x01,0x00,0xca,0x04,0xff,0x07,0xff]
+0x03,0x01,0x00,0xca,0x04,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, s105 :: v_dual_fmac_f32 v6, s1, v255 ; encoding: [0x69,0x00,0x00,0xca,0x01,0xfe,0x07,0xff]
+0x69,0x00,0x00,0xca,0x01,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, s1 :: v_dual_fmac_f32 v6, s105, v255 ; encoding: [0x01,0x00,0x00,0xca,0x69,0xfe,0x07,0xff]
+0x01,0x00,0x00,0xca,0x69,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, ttmp15 :: v_dual_fmac_f32 v6, vcc_lo, v255 ; encoding: [0x7b,0x00,0x00,0xca,0x6a,0xfe,0x07,0xff]
+0x7b,0x00,0x00,0xca,0x6a,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, exec_hi :: v_dual_fmac_f32 v6, vcc_hi, v255 ; encoding: [0x7f,0x00,0x00,0xca,0x6b,0xfe,0x07,0xff]
+0x7f,0x00,0x00,0xca,0x6b,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, exec_lo :: v_dual_fmac_f32 v6, ttmp15, v255 ; encoding: [0x7e,0x00,0x00,0xca,0x7b,0xfe,0x07,0xff]
+0x7e,0x00,0x00,0xca,0x7b,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, m0 :: v_dual_fmac_f32 v6, m0, v255 ; encoding: [0x7d,0x00,0x00,0xca,0x7d,0xfe,0x07,0xff]
+0x7d,0x00,0x00,0xca,0x7d,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, vcc_hi :: v_dual_fmac_f32 v6, exec_lo, v255 ; encoding: [0x6b,0x00,0x00,0xca,0x7e,0xfe,0x07,0xff]
+0x6b,0x00,0x00,0xca,0x7e,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, vcc_lo :: v_dual_fmac_f32 v6, exec_hi, v255 ; encoding: [0x6a,0x00,0x00,0xca,0x7f,0xfe,0x07,0xff]
+0x6a,0x00,0x00,0xca,0x7f,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, 0xaf123456 :: v_dual_fmac_f32 v6, null, v255 ; encoding: [0xff,0x00,0x00,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x00,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, src_scc :: v_dual_fmac_f32 v6, -1, v255 ; encoding: [0xfd,0x00,0x00,0xca,0xc1,0xfe,0x07,0xff]
+0xfd,0x00,0x00,0xca,0xc1,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, 0.5 :: v_dual_fmac_f32 v6, 0.5, v3 ; encoding: [0xf0,0x00,0x00,0xca,0xf0,0x06,0x06,0xff]
+0xf0,0x00,0x00,0xca,0xf0,0x06,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v255, -1 :: v_dual_fmac_f32 v6, src_scc, v4 ; encoding: [0xc1,0x00,0x00,0xca,0xfd,0x08,0x06,0xff]
+0xc1,0x00,0x00,0xca,0xfd,0x08,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v6, null :: v_dual_fmac_f32 v255, 0xaf123456, v5 ; encoding: [0x7c,0x00,0x00,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x00,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, v4 :: v_dual_fmamk_f32 v6, v1, 0xaf123456, v255 ; encoding: [0x04,0x01,0x04,0xca,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x04,0x01,0x04,0xca,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, v1 :: v_dual_fmamk_f32 v6, v255, 0xaf123456, v255 ; encoding: [0x01,0x01,0x04,0xca,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x01,0x04,0xca,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, v255 :: v_dual_fmamk_f32 v6, v2, 0xaf123456, v255 ; encoding: [0xff,0x01,0x04,0xca,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x01,0x04,0xca,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, v2 :: v_dual_fmamk_f32 v6, v3, 0xaf123456, v255 ; encoding: [0x02,0x01,0x04,0xca,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x02,0x01,0x04,0xca,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, v3 :: v_dual_fmamk_f32 v6, v4, 0xaf123456, v255 ; encoding: [0x03,0x01,0x04,0xca,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x03,0x01,0x04,0xca,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, s105 :: v_dual_fmamk_f32 v6, s105, 0xaf123456, v255 ; encoding: [0x69,0x00,0x04,0xca,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x69,0x00,0x04,0xca,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, s1 :: v_dual_fmamk_f32 v6, s1, 0xaf123456, v255 ; encoding: [0x01,0x00,0x04,0xca,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x00,0x04,0xca,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, ttmp15 :: v_dual_fmamk_f32 v6, ttmp15, 0xaf123456, v255 ; encoding: [0x7b,0x00,0x04,0xca,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0x00,0x04,0xca,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, exec_hi :: v_dual_fmamk_f32 v6, exec_hi, 0xaf123456, v255 ; encoding: [0x7f,0x00,0x04,0xca,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0x00,0x04,0xca,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, exec_lo :: v_dual_fmamk_f32 v6, exec_lo, 0xaf123456, v255 ; encoding: [0x7e,0x00,0x04,0xca,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0x00,0x04,0xca,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, m0 :: v_dual_fmamk_f32 v6, m0, 0xaf123456, v255 ; encoding: [0x7d,0x00,0x04,0xca,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0x00,0x04,0xca,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, vcc_hi :: v_dual_fmamk_f32 v6, vcc_hi, 0xaf123456, v255 ; encoding: [0x6b,0x00,0x04,0xca,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0x00,0x04,0xca,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, vcc_lo :: v_dual_fmamk_f32 v6, vcc_lo, 0xaf123456, v255 ; encoding: [0x6a,0x00,0x04,0xca,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0x00,0x04,0xca,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, 0xaf123456 :: v_dual_fmamk_f32 v6, null, 0xaf123456, v255 ; encoding: [0xff,0x00,0x04,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x04,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, src_scc :: v_dual_fmamk_f32 v6, -1, 0xaf123456, v255 ; encoding: [0xfd,0x00,0x04,0xca,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0x00,0x04,0xca,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, 0.5 :: v_dual_fmamk_f32 v6, 0.5, 0xaf123456, v255 ; encoding: [0xf0,0x00,0x04,0xca,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x00,0x04,0xca,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, -1 :: v_dual_fmamk_f32 v6, src_scc, 0xaf123456, v255 ; encoding: [0xc1,0x00,0x04,0xca,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x00,0x04,0xca,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v6, null :: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v4 ; encoding: [0x7c,0x00,0x04,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x04,0xca,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, v4 :: v_dual_lshlrev_b32 v6, v1, v255 ; encoding: [0x04,0x01,0x22,0xca,0x01,0xff,0x07,0xff]
+0x04,0x01,0x22,0xca,0x01,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v1 :: v_dual_lshlrev_b32 v6, v255, v255 ; encoding: [0x01,0x01,0x22,0xca,0xff,0xff,0x07,0xff]
+0x01,0x01,0x22,0xca,0xff,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v255 :: v_dual_lshlrev_b32 v6, v2, v255 ; encoding: [0xff,0x01,0x22,0xca,0x02,0xff,0x07,0xff]
+0xff,0x01,0x22,0xca,0x02,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v2 :: v_dual_lshlrev_b32 v6, v3, v255 ; encoding: [0x02,0x01,0x22,0xca,0x03,0xff,0x07,0xff]
+0x02,0x01,0x22,0xca,0x03,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v3 :: v_dual_lshlrev_b32 v6, v4, v255 ; encoding: [0x03,0x01,0x22,0xca,0x04,0xff,0x07,0xff]
+0x03,0x01,0x22,0xca,0x04,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, s105 :: v_dual_lshlrev_b32 v6, s1, v255 ; encoding: [0x69,0x00,0x22,0xca,0x01,0xfe,0x07,0xff]
+0x69,0x00,0x22,0xca,0x01,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, s1 :: v_dual_lshlrev_b32 v6, s105, v255 ; encoding: [0x01,0x00,0x22,0xca,0x69,0xfe,0x07,0xff]
+0x01,0x00,0x22,0xca,0x69,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, ttmp15 :: v_dual_lshlrev_b32 v6, vcc_lo, v255 ; encoding: [0x7b,0x00,0x22,0xca,0x6a,0xfe,0x07,0xff]
+0x7b,0x00,0x22,0xca,0x6a,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, exec_hi :: v_dual_lshlrev_b32 v6, vcc_hi, v255 ; encoding: [0x7f,0x00,0x22,0xca,0x6b,0xfe,0x07,0xff]
+0x7f,0x00,0x22,0xca,0x6b,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, exec_lo :: v_dual_lshlrev_b32 v6, ttmp15, v255 ; encoding: [0x7e,0x00,0x22,0xca,0x7b,0xfe,0x07,0xff]
+0x7e,0x00,0x22,0xca,0x7b,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, m0 :: v_dual_lshlrev_b32 v6, m0, v255 ; encoding: [0x7d,0x00,0x22,0xca,0x7d,0xfe,0x07,0xff]
+0x7d,0x00,0x22,0xca,0x7d,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, vcc_hi :: v_dual_lshlrev_b32 v6, exec_lo, v255 ; encoding: [0x6b,0x00,0x22,0xca,0x7e,0xfe,0x07,0xff]
+0x6b,0x00,0x22,0xca,0x7e,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, vcc_lo :: v_dual_lshlrev_b32 v6, exec_hi, v255 ; encoding: [0x6a,0x00,0x22,0xca,0x7f,0xfe,0x07,0xff]
+0x6a,0x00,0x22,0xca,0x7f,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, 0xaf123456 :: v_dual_lshlrev_b32 v6, null, v255 ; encoding: [0xff,0x00,0x22,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x22,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, src_scc :: v_dual_lshlrev_b32 v6, -1, v255 ; encoding: [0xfd,0x00,0x22,0xca,0xc1,0xfe,0x07,0xff]
+0xfd,0x00,0x22,0xca,0xc1,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, 0.5 :: v_dual_lshlrev_b32 v6, 0.5, v3 ; encoding: [0xf0,0x00,0x22,0xca,0xf0,0x06,0x06,0xff]
+0xf0,0x00,0x22,0xca,0xf0,0x06,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v255, -1 :: v_dual_lshlrev_b32 v6, src_scc, v4 ; encoding: [0xc1,0x00,0x22,0xca,0xfd,0x08,0x06,0xff]
+0xc1,0x00,0x22,0xca,0xfd,0x08,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v6, null :: v_dual_lshlrev_b32 v255, 0xaf123456, v5 ; encoding: [0x7c,0x00,0x22,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x22,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, v4 :: v_dual_max_num_f32 v6, v1, v255 ; encoding: [0x04,0x01,0x14,0xca,0x01,0xff,0x07,0xff]
+0x04,0x01,0x14,0xca,0x01,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v1 :: v_dual_max_num_f32 v6, v255, v255 ; encoding: [0x01,0x01,0x14,0xca,0xff,0xff,0x07,0xff]
+0x01,0x01,0x14,0xca,0xff,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v255 :: v_dual_max_num_f32 v6, v2, v255 ; encoding: [0xff,0x01,0x14,0xca,0x02,0xff,0x07,0xff]
+0xff,0x01,0x14,0xca,0x02,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v2 :: v_dual_max_num_f32 v6, v3, v255 ; encoding: [0x02,0x01,0x14,0xca,0x03,0xff,0x07,0xff]
+0x02,0x01,0x14,0xca,0x03,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v3 :: v_dual_max_num_f32 v6, v4, v255 ; encoding: [0x03,0x01,0x14,0xca,0x04,0xff,0x07,0xff]
+0x03,0x01,0x14,0xca,0x04,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, s105 :: v_dual_max_num_f32 v6, s1, v255 ; encoding: [0x69,0x00,0x14,0xca,0x01,0xfe,0x07,0xff]
+0x69,0x00,0x14,0xca,0x01,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, s1 :: v_dual_max_num_f32 v6, s105, v255 ; encoding: [0x01,0x00,0x14,0xca,0x69,0xfe,0x07,0xff]
+0x01,0x00,0x14,0xca,0x69,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, ttmp15 :: v_dual_max_num_f32 v6, vcc_lo, v255 ; encoding: [0x7b,0x00,0x14,0xca,0x6a,0xfe,0x07,0xff]
+0x7b,0x00,0x14,0xca,0x6a,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, exec_hi :: v_dual_max_num_f32 v6, vcc_hi, v255 ; encoding: [0x7f,0x00,0x14,0xca,0x6b,0xfe,0x07,0xff]
+0x7f,0x00,0x14,0xca,0x6b,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, exec_lo :: v_dual_max_num_f32 v6, ttmp15, v255 ; encoding: [0x7e,0x00,0x14,0xca,0x7b,0xfe,0x07,0xff]
+0x7e,0x00,0x14,0xca,0x7b,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, m0 :: v_dual_max_num_f32 v6, m0, v255 ; encoding: [0x7d,0x00,0x14,0xca,0x7d,0xfe,0x07,0xff]
+0x7d,0x00,0x14,0xca,0x7d,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, vcc_hi :: v_dual_max_num_f32 v6, exec_lo, v255 ; encoding: [0x6b,0x00,0x14,0xca,0x7e,0xfe,0x07,0xff]
+0x6b,0x00,0x14,0xca,0x7e,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, vcc_lo :: v_dual_max_num_f32 v6, exec_hi, v255 ; encoding: [0x6a,0x00,0x14,0xca,0x7f,0xfe,0x07,0xff]
+0x6a,0x00,0x14,0xca,0x7f,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, 0xaf123456 :: v_dual_max_num_f32 v6, null, v255 ; encoding: [0xff,0x00,0x14,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x14,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, src_scc :: v_dual_max_num_f32 v6, -1, v255 ; encoding: [0xfd,0x00,0x14,0xca,0xc1,0xfe,0x07,0xff]
+0xfd,0x00,0x14,0xca,0xc1,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, 0.5 :: v_dual_max_num_f32 v6, 0.5, v3 ; encoding: [0xf0,0x00,0x14,0xca,0xf0,0x06,0x06,0xff]
+0xf0,0x00,0x14,0xca,0xf0,0x06,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v255, -1 :: v_dual_max_num_f32 v6, src_scc, v4 ; encoding: [0xc1,0x00,0x14,0xca,0xfd,0x08,0x06,0xff]
+0xc1,0x00,0x14,0xca,0xfd,0x08,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v6, null :: v_dual_max_num_f32 v255, 0xaf123456, v5 ; encoding: [0x7c,0x00,0x14,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x14,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, v4 :: v_dual_min_num_f32 v6, v1, v255 ; encoding: [0x04,0x01,0x16,0xca,0x01,0xff,0x07,0xff]
+0x04,0x01,0x16,0xca,0x01,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v1 :: v_dual_min_num_f32 v6, v255, v255 ; encoding: [0x01,0x01,0x16,0xca,0xff,0xff,0x07,0xff]
+0x01,0x01,0x16,0xca,0xff,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v255 :: v_dual_min_num_f32 v6, v2, v255 ; encoding: [0xff,0x01,0x16,0xca,0x02,0xff,0x07,0xff]
+0xff,0x01,0x16,0xca,0x02,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v2 :: v_dual_min_num_f32 v6, v3, v255 ; encoding: [0x02,0x01,0x16,0xca,0x03,0xff,0x07,0xff]
+0x02,0x01,0x16,0xca,0x03,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v3 :: v_dual_min_num_f32 v6, v4, v255 ; encoding: [0x03,0x01,0x16,0xca,0x04,0xff,0x07,0xff]
+0x03,0x01,0x16,0xca,0x04,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, s105 :: v_dual_min_num_f32 v6, s1, v255 ; encoding: [0x69,0x00,0x16,0xca,0x01,0xfe,0x07,0xff]
+0x69,0x00,0x16,0xca,0x01,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, s1 :: v_dual_min_num_f32 v6, s105, v255 ; encoding: [0x01,0x00,0x16,0xca,0x69,0xfe,0x07,0xff]
+0x01,0x00,0x16,0xca,0x69,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, ttmp15 :: v_dual_min_num_f32 v6, vcc_lo, v255 ; encoding: [0x7b,0x00,0x16,0xca,0x6a,0xfe,0x07,0xff]
+0x7b,0x00,0x16,0xca,0x6a,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, exec_hi :: v_dual_min_num_f32 v6, vcc_hi, v255 ; encoding: [0x7f,0x00,0x16,0xca,0x6b,0xfe,0x07,0xff]
+0x7f,0x00,0x16,0xca,0x6b,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, exec_lo :: v_dual_min_num_f32 v6, ttmp15, v255 ; encoding: [0x7e,0x00,0x16,0xca,0x7b,0xfe,0x07,0xff]
+0x7e,0x00,0x16,0xca,0x7b,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, m0 :: v_dual_min_num_f32 v6, m0, v255 ; encoding: [0x7d,0x00,0x16,0xca,0x7d,0xfe,0x07,0xff]
+0x7d,0x00,0x16,0xca,0x7d,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, vcc_hi :: v_dual_min_num_f32 v6, exec_lo, v255 ; encoding: [0x6b,0x00,0x16,0xca,0x7e,0xfe,0x07,0xff]
+0x6b,0x00,0x16,0xca,0x7e,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, vcc_lo :: v_dual_min_num_f32 v6, exec_hi, v255 ; encoding: [0x6a,0x00,0x16,0xca,0x7f,0xfe,0x07,0xff]
+0x6a,0x00,0x16,0xca,0x7f,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, 0xaf123456 :: v_dual_min_num_f32 v6, null, v255 ; encoding: [0xff,0x00,0x16,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x16,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, src_scc :: v_dual_min_num_f32 v6, -1, v255 ; encoding: [0xfd,0x00,0x16,0xca,0xc1,0xfe,0x07,0xff]
+0xfd,0x00,0x16,0xca,0xc1,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, 0.5 :: v_dual_min_num_f32 v6, 0.5, v3 ; encoding: [0xf0,0x00,0x16,0xca,0xf0,0x06,0x06,0xff]
+0xf0,0x00,0x16,0xca,0xf0,0x06,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v255, -1 :: v_dual_min_num_f32 v6, src_scc, v4 ; encoding: [0xc1,0x00,0x16,0xca,0xfd,0x08,0x06,0xff]
+0xc1,0x00,0x16,0xca,0xfd,0x08,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v6, null :: v_dual_min_num_f32 v255, 0xaf123456, v5 ; encoding: [0x7c,0x00,0x16,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x16,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, v4 :: v_dual_mov_b32 v6, v1 ; encoding: [0x04,0x01,0x10,0xca,0x01,0x01,0x06,0xff]
+0x04,0x01,0x10,0xca,0x01,0x01,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v255, v1 :: v_dual_mov_b32 v6, v255 ; encoding: [0x01,0x01,0x10,0xca,0xff,0x01,0x06,0xff]
+0x01,0x01,0x10,0xca,0xff,0x01,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v255, v255 :: v_dual_mov_b32 v6, v2 ; encoding: [0xff,0x01,0x10,0xca,0x02,0x01,0x06,0xff]
+0xff,0x01,0x10,0xca,0x02,0x01,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v255, v2 :: v_dual_mov_b32 v6, v3 ; encoding: [0x02,0x01,0x10,0xca,0x03,0x01,0x06,0xff]
+0x02,0x01,0x10,0xca,0x03,0x01,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v255, v3 :: v_dual_mov_b32 v6, v4 ; encoding: [0x03,0x01,0x10,0xca,0x04,0x01,0x06,0xff]
+0x03,0x01,0x10,0xca,0x04,0x01,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v255, s105 :: v_dual_mov_b32 v6, s1 ; encoding: [0x69,0x00,0x10,0xca,0x01,0x00,0x06,0xff]
+0x69,0x00,0x10,0xca,0x01,0x00,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v255, s1 :: v_dual_mov_b32 v6, s105 ; encoding: [0x01,0x00,0x10,0xca,0x69,0x00,0x06,0xff]
+0x01,0x00,0x10,0xca,0x69,0x00,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v255, ttmp15 :: v_dual_mov_b32 v6, vcc_lo ; encoding: [0x7b,0x00,0x10,0xca,0x6a,0x00,0x06,0xff]
+0x7b,0x00,0x10,0xca,0x6a,0x00,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v255, exec_hi :: v_dual_mov_b32 v6, vcc_hi ; encoding: [0x7f,0x00,0x10,0xca,0x6b,0x00,0x06,0xff]
+0x7f,0x00,0x10,0xca,0x6b,0x00,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v255, exec_lo :: v_dual_mov_b32 v6, ttmp15 ; encoding: [0x7e,0x00,0x10,0xca,0x7b,0x00,0x06,0xff]
+0x7e,0x00,0x10,0xca,0x7b,0x00,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v255, m0 :: v_dual_mov_b32 v6, m0 ; encoding: [0x7d,0x00,0x10,0xca,0x7d,0x00,0x06,0xff]
+0x7d,0x00,0x10,0xca,0x7d,0x00,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v255, vcc_hi :: v_dual_mov_b32 v6, exec_lo ; encoding: [0x6b,0x00,0x10,0xca,0x7e,0x00,0x06,0xff]
+0x6b,0x00,0x10,0xca,0x7e,0x00,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v255, vcc_lo :: v_dual_mov_b32 v6, exec_hi ; encoding: [0x6a,0x00,0x10,0xca,0x7f,0x00,0x06,0xff]
+0x6a,0x00,0x10,0xca,0x7f,0x00,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v255, 0xaf123456 :: v_dual_mov_b32 v6, null ; encoding: [0xff,0x00,0x10,0xca,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x10,0xca,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, src_scc :: v_dual_mov_b32 v6, -1 ; encoding: [0xfd,0x00,0x10,0xca,0xc1,0x00,0x06,0xff]
+0xfd,0x00,0x10,0xca,0xc1,0x00,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v255, 0.5 :: v_dual_mov_b32 v6, 0.5 ; encoding: [0xf0,0x00,0x10,0xca,0xf0,0x00,0x06,0xff]
+0xf0,0x00,0x10,0xca,0xf0,0x00,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v255, -1 :: v_dual_mov_b32 v6, src_scc ; encoding: [0xc1,0x00,0x10,0xca,0xfd,0x00,0x06,0xff]
+0xc1,0x00,0x10,0xca,0xfd,0x00,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v6, null :: v_dual_mov_b32 v255, 0xaf123456 ; encoding: [0x7c,0x00,0x10,0xca,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x10,0xca,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, v4 :: v_dual_mul_dx9_zero_f32 v6, v1, v255 ; encoding: [0x04,0x01,0x0e,0xca,0x01,0xff,0x07,0xff]
+0x04,0x01,0x0e,0xca,0x01,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v1 :: v_dual_mul_dx9_zero_f32 v6, v255, v255 ; encoding: [0x01,0x01,0x0e,0xca,0xff,0xff,0x07,0xff]
+0x01,0x01,0x0e,0xca,0xff,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v255 :: v_dual_mul_dx9_zero_f32 v6, v2, v255 ; encoding: [0xff,0x01,0x0e,0xca,0x02,0xff,0x07,0xff]
+0xff,0x01,0x0e,0xca,0x02,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v2 :: v_dual_mul_dx9_zero_f32 v6, v3, v255 ; encoding: [0x02,0x01,0x0e,0xca,0x03,0xff,0x07,0xff]
+0x02,0x01,0x0e,0xca,0x03,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v3 :: v_dual_mul_dx9_zero_f32 v6, v4, v255 ; encoding: [0x03,0x01,0x0e,0xca,0x04,0xff,0x07,0xff]
+0x03,0x01,0x0e,0xca,0x04,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, s105 :: v_dual_mul_dx9_zero_f32 v6, s1, v255 ; encoding: [0x69,0x00,0x0e,0xca,0x01,0xfe,0x07,0xff]
+0x69,0x00,0x0e,0xca,0x01,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, s1 :: v_dual_mul_dx9_zero_f32 v6, s105, v255 ; encoding: [0x01,0x00,0x0e,0xca,0x69,0xfe,0x07,0xff]
+0x01,0x00,0x0e,0xca,0x69,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, ttmp15 :: v_dual_mul_dx9_zero_f32 v6, vcc_lo, v255 ; encoding: [0x7b,0x00,0x0e,0xca,0x6a,0xfe,0x07,0xff]
+0x7b,0x00,0x0e,0xca,0x6a,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, exec_hi :: v_dual_mul_dx9_zero_f32 v6, vcc_hi, v255 ; encoding: [0x7f,0x00,0x0e,0xca,0x6b,0xfe,0x07,0xff]
+0x7f,0x00,0x0e,0xca,0x6b,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, exec_lo :: v_dual_mul_dx9_zero_f32 v6, ttmp15, v255 ; encoding: [0x7e,0x00,0x0e,0xca,0x7b,0xfe,0x07,0xff]
+0x7e,0x00,0x0e,0xca,0x7b,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, m0 :: v_dual_mul_dx9_zero_f32 v6, m0, v255 ; encoding: [0x7d,0x00,0x0e,0xca,0x7d,0xfe,0x07,0xff]
+0x7d,0x00,0x0e,0xca,0x7d,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, vcc_hi :: v_dual_mul_dx9_zero_f32 v6, exec_lo, v255 ; encoding: [0x6b,0x00,0x0e,0xca,0x7e,0xfe,0x07,0xff]
+0x6b,0x00,0x0e,0xca,0x7e,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, vcc_lo :: v_dual_mul_dx9_zero_f32 v6, exec_hi, v255 ; encoding: [0x6a,0x00,0x0e,0xca,0x7f,0xfe,0x07,0xff]
+0x6a,0x00,0x0e,0xca,0x7f,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, 0xaf123456 :: v_dual_mul_dx9_zero_f32 v6, null, v255 ; encoding: [0xff,0x00,0x0e,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x0e,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, src_scc :: v_dual_mul_dx9_zero_f32 v6, -1, v255 ; encoding: [0xfd,0x00,0x0e,0xca,0xc1,0xfe,0x07,0xff]
+0xfd,0x00,0x0e,0xca,0xc1,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, 0.5 :: v_dual_mul_dx9_zero_f32 v6, 0.5, v3 ; encoding: [0xf0,0x00,0x0e,0xca,0xf0,0x06,0x06,0xff]
+0xf0,0x00,0x0e,0xca,0xf0,0x06,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v255, -1 :: v_dual_mul_dx9_zero_f32 v6, src_scc, v4 ; encoding: [0xc1,0x00,0x0e,0xca,0xfd,0x08,0x06,0xff]
+0xc1,0x00,0x0e,0xca,0xfd,0x08,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v6, null :: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v5 ; encoding: [0x7c,0x00,0x0e,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x0e,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, v4 :: v_dual_mul_f32 v6, v1, v255 ; encoding: [0x04,0x01,0x06,0xca,0x01,0xff,0x07,0xff]
+0x04,0x01,0x06,0xca,0x01,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v1 :: v_dual_mul_f32 v6, v255, v255 ; encoding: [0x01,0x01,0x06,0xca,0xff,0xff,0x07,0xff]
+0x01,0x01,0x06,0xca,0xff,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v255 :: v_dual_mul_f32 v6, v2, v255 ; encoding: [0xff,0x01,0x06,0xca,0x02,0xff,0x07,0xff]
+0xff,0x01,0x06,0xca,0x02,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v2 :: v_dual_mul_f32 v6, v3, v255 ; encoding: [0x02,0x01,0x06,0xca,0x03,0xff,0x07,0xff]
+0x02,0x01,0x06,0xca,0x03,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v3 :: v_dual_mul_f32 v6, v4, v255 ; encoding: [0x03,0x01,0x06,0xca,0x04,0xff,0x07,0xff]
+0x03,0x01,0x06,0xca,0x04,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, s105 :: v_dual_mul_f32 v6, s1, v255 ; encoding: [0x69,0x00,0x06,0xca,0x01,0xfe,0x07,0xff]
+0x69,0x00,0x06,0xca,0x01,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, s1 :: v_dual_mul_f32 v6, s105, v255 ; encoding: [0x01,0x00,0x06,0xca,0x69,0xfe,0x07,0xff]
+0x01,0x00,0x06,0xca,0x69,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, ttmp15 :: v_dual_mul_f32 v6, vcc_lo, v255 ; encoding: [0x7b,0x00,0x06,0xca,0x6a,0xfe,0x07,0xff]
+0x7b,0x00,0x06,0xca,0x6a,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, exec_hi :: v_dual_mul_f32 v6, vcc_hi, v255 ; encoding: [0x7f,0x00,0x06,0xca,0x6b,0xfe,0x07,0xff]
+0x7f,0x00,0x06,0xca,0x6b,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, exec_lo :: v_dual_mul_f32 v6, ttmp15, v255 ; encoding: [0x7e,0x00,0x06,0xca,0x7b,0xfe,0x07,0xff]
+0x7e,0x00,0x06,0xca,0x7b,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, m0 :: v_dual_mul_f32 v6, m0, v255 ; encoding: [0x7d,0x00,0x06,0xca,0x7d,0xfe,0x07,0xff]
+0x7d,0x00,0x06,0xca,0x7d,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, vcc_hi :: v_dual_mul_f32 v6, exec_lo, v255 ; encoding: [0x6b,0x00,0x06,0xca,0x7e,0xfe,0x07,0xff]
+0x6b,0x00,0x06,0xca,0x7e,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, vcc_lo :: v_dual_mul_f32 v6, exec_hi, v255 ; encoding: [0x6a,0x00,0x06,0xca,0x7f,0xfe,0x07,0xff]
+0x6a,0x00,0x06,0xca,0x7f,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, 0xaf123456 :: v_dual_mul_f32 v6, null, v255 ; encoding: [0xff,0x00,0x06,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x06,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, src_scc :: v_dual_mul_f32 v6, -1, v255 ; encoding: [0xfd,0x00,0x06,0xca,0xc1,0xfe,0x07,0xff]
+0xfd,0x00,0x06,0xca,0xc1,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, 0.5 :: v_dual_mul_f32 v6, 0.5, v3 ; encoding: [0xf0,0x00,0x06,0xca,0xf0,0x06,0x06,0xff]
+0xf0,0x00,0x06,0xca,0xf0,0x06,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v255, -1 :: v_dual_mul_f32 v6, src_scc, v4 ; encoding: [0xc1,0x00,0x06,0xca,0xfd,0x08,0x06,0xff]
+0xc1,0x00,0x06,0xca,0xfd,0x08,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v6, null :: v_dual_mul_f32 v255, 0xaf123456, v5 ; encoding: [0x7c,0x00,0x06,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x06,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, v4 :: v_dual_sub_f32 v6, v1, v255 ; encoding: [0x04,0x01,0x0a,0xca,0x01,0xff,0x07,0xff]
+0x04,0x01,0x0a,0xca,0x01,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v1 :: v_dual_sub_f32 v6, v255, v255 ; encoding: [0x01,0x01,0x0a,0xca,0xff,0xff,0x07,0xff]
+0x01,0x01,0x0a,0xca,0xff,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v255 :: v_dual_sub_f32 v6, v2, v255 ; encoding: [0xff,0x01,0x0a,0xca,0x02,0xff,0x07,0xff]
+0xff,0x01,0x0a,0xca,0x02,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v2 :: v_dual_sub_f32 v6, v3, v255 ; encoding: [0x02,0x01,0x0a,0xca,0x03,0xff,0x07,0xff]
+0x02,0x01,0x0a,0xca,0x03,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v3 :: v_dual_sub_f32 v6, v4, v255 ; encoding: [0x03,0x01,0x0a,0xca,0x04,0xff,0x07,0xff]
+0x03,0x01,0x0a,0xca,0x04,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, s105 :: v_dual_sub_f32 v6, s1, v255 ; encoding: [0x69,0x00,0x0a,0xca,0x01,0xfe,0x07,0xff]
+0x69,0x00,0x0a,0xca,0x01,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, s1 :: v_dual_sub_f32 v6, s105, v255 ; encoding: [0x01,0x00,0x0a,0xca,0x69,0xfe,0x07,0xff]
+0x01,0x00,0x0a,0xca,0x69,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, ttmp15 :: v_dual_sub_f32 v6, vcc_lo, v255 ; encoding: [0x7b,0x00,0x0a,0xca,0x6a,0xfe,0x07,0xff]
+0x7b,0x00,0x0a,0xca,0x6a,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, exec_hi :: v_dual_sub_f32 v6, vcc_hi, v255 ; encoding: [0x7f,0x00,0x0a,0xca,0x6b,0xfe,0x07,0xff]
+0x7f,0x00,0x0a,0xca,0x6b,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, exec_lo :: v_dual_sub_f32 v6, ttmp15, v255 ; encoding: [0x7e,0x00,0x0a,0xca,0x7b,0xfe,0x07,0xff]
+0x7e,0x00,0x0a,0xca,0x7b,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, m0 :: v_dual_sub_f32 v6, m0, v255 ; encoding: [0x7d,0x00,0x0a,0xca,0x7d,0xfe,0x07,0xff]
+0x7d,0x00,0x0a,0xca,0x7d,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, vcc_hi :: v_dual_sub_f32 v6, exec_lo, v255 ; encoding: [0x6b,0x00,0x0a,0xca,0x7e,0xfe,0x07,0xff]
+0x6b,0x00,0x0a,0xca,0x7e,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, vcc_lo :: v_dual_sub_f32 v6, exec_hi, v255 ; encoding: [0x6a,0x00,0x0a,0xca,0x7f,0xfe,0x07,0xff]
+0x6a,0x00,0x0a,0xca,0x7f,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, 0xaf123456 :: v_dual_sub_f32 v6, null, v255 ; encoding: [0xff,0x00,0x0a,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x0a,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, src_scc :: v_dual_sub_f32 v6, -1, v255 ; encoding: [0xfd,0x00,0x0a,0xca,0xc1,0xfe,0x07,0xff]
+0xfd,0x00,0x0a,0xca,0xc1,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, 0.5 :: v_dual_sub_f32 v6, 0.5, v3 ; encoding: [0xf0,0x00,0x0a,0xca,0xf0,0x06,0x06,0xff]
+0xf0,0x00,0x0a,0xca,0xf0,0x06,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v255, -1 :: v_dual_sub_f32 v6, src_scc, v4 ; encoding: [0xc1,0x00,0x0a,0xca,0xfd,0x08,0x06,0xff]
+0xc1,0x00,0x0a,0xca,0xfd,0x08,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v6, null :: v_dual_sub_f32 v255, 0xaf123456, v5 ; encoding: [0x7c,0x00,0x0a,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x0a,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, v4 :: v_dual_subrev_f32 v6, v1, v255 ; encoding: [0x04,0x01,0x0c,0xca,0x01,0xff,0x07,0xff]
+0x04,0x01,0x0c,0xca,0x01,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v1 :: v_dual_subrev_f32 v6, v255, v255 ; encoding: [0x01,0x01,0x0c,0xca,0xff,0xff,0x07,0xff]
+0x01,0x01,0x0c,0xca,0xff,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v255 :: v_dual_subrev_f32 v6, v2, v255 ; encoding: [0xff,0x01,0x0c,0xca,0x02,0xff,0x07,0xff]
+0xff,0x01,0x0c,0xca,0x02,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v2 :: v_dual_subrev_f32 v6, v3, v255 ; encoding: [0x02,0x01,0x0c,0xca,0x03,0xff,0x07,0xff]
+0x02,0x01,0x0c,0xca,0x03,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, v3 :: v_dual_subrev_f32 v6, v4, v255 ; encoding: [0x03,0x01,0x0c,0xca,0x04,0xff,0x07,0xff]
+0x03,0x01,0x0c,0xca,0x04,0xff,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, s105 :: v_dual_subrev_f32 v6, s1, v255 ; encoding: [0x69,0x00,0x0c,0xca,0x01,0xfe,0x07,0xff]
+0x69,0x00,0x0c,0xca,0x01,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, s1 :: v_dual_subrev_f32 v6, s105, v255 ; encoding: [0x01,0x00,0x0c,0xca,0x69,0xfe,0x07,0xff]
+0x01,0x00,0x0c,0xca,0x69,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, ttmp15 :: v_dual_subrev_f32 v6, vcc_lo, v255 ; encoding: [0x7b,0x00,0x0c,0xca,0x6a,0xfe,0x07,0xff]
+0x7b,0x00,0x0c,0xca,0x6a,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, exec_hi :: v_dual_subrev_f32 v6, vcc_hi, v255 ; encoding: [0x7f,0x00,0x0c,0xca,0x6b,0xfe,0x07,0xff]
+0x7f,0x00,0x0c,0xca,0x6b,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, exec_lo :: v_dual_subrev_f32 v6, ttmp15, v255 ; encoding: [0x7e,0x00,0x0c,0xca,0x7b,0xfe,0x07,0xff]
+0x7e,0x00,0x0c,0xca,0x7b,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, m0 :: v_dual_subrev_f32 v6, m0, v255 ; encoding: [0x7d,0x00,0x0c,0xca,0x7d,0xfe,0x07,0xff]
+0x7d,0x00,0x0c,0xca,0x7d,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, vcc_hi :: v_dual_subrev_f32 v6, exec_lo, v255 ; encoding: [0x6b,0x00,0x0c,0xca,0x7e,0xfe,0x07,0xff]
+0x6b,0x00,0x0c,0xca,0x7e,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, vcc_lo :: v_dual_subrev_f32 v6, exec_hi, v255 ; encoding: [0x6a,0x00,0x0c,0xca,0x7f,0xfe,0x07,0xff]
+0x6a,0x00,0x0c,0xca,0x7f,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, 0xaf123456 :: v_dual_subrev_f32 v6, null, v255 ; encoding: [0xff,0x00,0x0c,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x00,0x0c,0xca,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mov_b32 v255, src_scc :: v_dual_subrev_f32 v6, -1, v255 ; encoding: [0xfd,0x00,0x0c,0xca,0xc1,0xfe,0x07,0xff]
+0xfd,0x00,0x0c,0xca,0xc1,0xfe,0x07,0xff
+
+# GFX12: v_dual_mov_b32 v255, 0.5 :: v_dual_subrev_f32 v6, 0.5, v3 ; encoding: [0xf0,0x00,0x0c,0xca,0xf0,0x06,0x06,0xff]
+0xf0,0x00,0x0c,0xca,0xf0,0x06,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v255, -1 :: v_dual_subrev_f32 v6, src_scc, v4 ; encoding: [0xc1,0x00,0x0c,0xca,0xfd,0x08,0x06,0xff]
+0xc1,0x00,0x0c,0xca,0xfd,0x08,0x06,0xff
+
+# GFX12: v_dual_mov_b32 v6, null :: v_dual_subrev_f32 v255, 0xaf123456, v5 ; encoding: [0x7c,0x00,0x0c,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x00,0x0c,0xca,0xff,0x0a,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v4, v2 :: v_dual_add_f32 v6, v1, v3 ; encoding: [0x04,0x05,0xc8,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0xc8,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v1, v2 :: v_dual_add_f32 v6, v255, v3 ; encoding: [0x01,0x05,0xc8,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0xc8,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v255, v2 :: v_dual_add_f32 v6, v2, v3 ; encoding: [0xff,0x05,0xc8,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0xc8,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v2, v2 :: v_dual_add_f32 v6, v3, v3 ; encoding: [0x02,0x05,0xc8,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0xc8,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v3, v2 :: v_dual_add_f32 v6, v4, v3 ; encoding: [0x03,0x05,0xc8,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0xc8,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s105, v2 :: v_dual_add_f32 v6, s1, v3 ; encoding: [0x69,0x04,0xc8,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0xc8,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s1, v2 :: v_dual_add_f32 v6, s105, v3 ; encoding: [0x01,0x04,0xc8,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0xc8,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, ttmp15, v2 :: v_dual_add_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xc8,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xc8,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_hi, v2 :: v_dual_add_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xc8,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xc8,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_lo, v2 :: v_dual_add_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xc8,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xc8,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, m0, v2 :: v_dual_add_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0xc8,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xc8,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_hi, v2 :: v_dual_add_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xc8,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xc8,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_lo, v2 :: v_dual_add_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xc8,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xc8,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v2 :: v_dual_add_f32 v6, null, v3 ; encoding: [0xff,0x04,0xc8,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xc8,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, src_scc, v2 :: v_dual_add_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0xc8,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xc8,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_add_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xc8,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xc8,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_add_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xc8,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xc8,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_add_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xc8,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xc8,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v4, v2 :: v_dual_add_nc_u32 v6, v1, v3 ; encoding: [0x04,0x05,0xe0,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0xe0,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v1, v2 :: v_dual_add_nc_u32 v6, v255, v3 ; encoding: [0x01,0x05,0xe0,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0xe0,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v255, v2 :: v_dual_add_nc_u32 v6, v2, v3 ; encoding: [0xff,0x05,0xe0,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0xe0,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v2, v2 :: v_dual_add_nc_u32 v6, v3, v3 ; encoding: [0x02,0x05,0xe0,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0xe0,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v3, v2 :: v_dual_add_nc_u32 v6, v4, v3 ; encoding: [0x03,0x05,0xe0,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0xe0,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s105, v2 :: v_dual_add_nc_u32 v6, s1, v3 ; encoding: [0x69,0x04,0xe0,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0xe0,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s1, v2 :: v_dual_add_nc_u32 v6, s105, v3 ; encoding: [0x01,0x04,0xe0,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0xe0,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, ttmp15, v2 :: v_dual_add_nc_u32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xe0,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xe0,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_hi, v2 :: v_dual_add_nc_u32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xe0,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xe0,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_lo, v2 :: v_dual_add_nc_u32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xe0,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xe0,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, m0, v2 :: v_dual_add_nc_u32 v6, m0, v3 ; encoding: [0x7d,0x04,0xe0,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xe0,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_hi, v2 :: v_dual_add_nc_u32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xe0,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xe0,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_lo, v2 :: v_dual_add_nc_u32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xe0,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xe0,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v2 :: v_dual_add_nc_u32 v6, null, v3 ; encoding: [0xff,0x04,0xe0,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xe0,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, src_scc, v2 :: v_dual_add_nc_u32 v6, -1, v3 ; encoding: [0xfd,0x04,0xe0,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xe0,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_add_nc_u32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xe0,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xe0,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_add_nc_u32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xe0,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xe0,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_add_nc_u32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xe0,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xe0,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v4, v2 :: v_dual_and_b32 v6, v1, v3 ; encoding: [0x04,0x05,0xe4,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0xe4,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v1, v2 :: v_dual_and_b32 v6, v255, v3 ; encoding: [0x01,0x05,0xe4,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0xe4,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v255, v2 :: v_dual_and_b32 v6, v2, v3 ; encoding: [0xff,0x05,0xe4,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0xe4,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v2, v2 :: v_dual_and_b32 v6, v3, v3 ; encoding: [0x02,0x05,0xe4,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0xe4,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v3, v2 :: v_dual_and_b32 v6, v4, v3 ; encoding: [0x03,0x05,0xe4,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0xe4,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s105, v2 :: v_dual_and_b32 v6, s1, v3 ; encoding: [0x69,0x04,0xe4,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0xe4,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s1, v2 :: v_dual_and_b32 v6, s105, v3 ; encoding: [0x01,0x04,0xe4,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0xe4,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, ttmp15, v2 :: v_dual_and_b32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xe4,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xe4,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_hi, v2 :: v_dual_and_b32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xe4,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xe4,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_lo, v2 :: v_dual_and_b32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xe4,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xe4,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, m0, v2 :: v_dual_and_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0xe4,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xe4,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_hi, v2 :: v_dual_and_b32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xe4,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xe4,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_lo, v2 :: v_dual_and_b32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xe4,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xe4,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v2 :: v_dual_and_b32 v6, null, v3 ; encoding: [0xff,0x04,0xe4,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xe4,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, src_scc, v2 :: v_dual_and_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0xe4,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xe4,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_and_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xe4,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xe4,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_and_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xe4,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xe4,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_and_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xe4,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xe4,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v4, v2 :: v_dual_cndmask_b32 v6, v1, v3 ; encoding: [0x04,0x05,0xd2,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0xd2,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v1, v2 :: v_dual_cndmask_b32 v6, v255, v3 ; encoding: [0x01,0x05,0xd2,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0xd2,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v255, v2 :: v_dual_cndmask_b32 v6, v2, v3 ; encoding: [0xff,0x05,0xd2,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0xd2,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v2, v2 :: v_dual_cndmask_b32 v6, v3, v3 ; encoding: [0x02,0x05,0xd2,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0xd2,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v3, v2 :: v_dual_cndmask_b32 v6, v4, v3 ; encoding: [0x03,0x05,0xd2,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0xd2,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s105, v2 :: v_dual_cndmask_b32 v6, s105, v3 ; encoding: [0x69,0x04,0xd2,0xc9,0x69,0x06,0x06,0xff]
+0x69,0x04,0xd2,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s1, v2 :: v_dual_cndmask_b32 v6, s1, v3 ; encoding: [0x01,0x04,0xd2,0xc9,0x01,0x06,0x06,0xff]
+0x01,0x04,0xd2,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, ttmp15, v2 :: v_dual_cndmask_b32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0xd2,0xc9,0x7b,0x06,0x06,0xff]
+0x7b,0x04,0xd2,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_hi, v2 :: v_dual_cndmask_b32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0xd2,0xc9,0x7f,0x06,0x06,0xff]
+0x7f,0x04,0xd2,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_lo, v2 :: v_dual_cndmask_b32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0xd2,0xc9,0x7e,0x06,0x06,0xff]
+0x7e,0x04,0xd2,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, m0, v2 :: v_dual_cndmask_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0xd2,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xd2,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_hi, v2 :: v_dual_cndmask_b32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0xd2,0xc9,0x6b,0x06,0x06,0xff]
+0x6b,0x04,0xd2,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_lo, v2 :: v_dual_cndmask_b32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0xd2,0xc9,0x6a,0x06,0x06,0xff]
+0x6a,0x04,0xd2,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v2 :: v_dual_cndmask_b32 v6, null, v3 ; encoding: [0xff,0x04,0xd2,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xd2,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, src_scc, v2 :: v_dual_cndmask_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0xd2,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xd2,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_cndmask_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xd2,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xd2,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_cndmask_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xd2,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xd2,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_cndmask_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xd2,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xd2,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v4, v2 :: v_dual_fmaak_f32 v6, v1, v3, 0xaf123456 ; encoding: [0x04,0x05,0xc2,0xc9,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x04,0x05,0xc2,0xc9,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v1, v2 :: v_dual_fmaak_f32 v6, v255, v3, 0xaf123456 ; encoding: [0x01,0x05,0xc2,0xc9,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x05,0xc2,0xc9,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v255, v2 :: v_dual_fmaak_f32 v6, v2, v3, 0xaf123456 ; encoding: [0xff,0x05,0xc2,0xc9,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x05,0xc2,0xc9,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v2, v2 :: v_dual_fmaak_f32 v6, v3, v3, 0xaf123456 ; encoding: [0x02,0x05,0xc2,0xc9,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x02,0x05,0xc2,0xc9,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v3, v2 :: v_dual_fmaak_f32 v6, v4, v3, 0xaf123456 ; encoding: [0x03,0x05,0xc2,0xc9,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x03,0x05,0xc2,0xc9,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s105, v2 :: v_dual_fmaak_f32 v6, s105, v3, 0xaf123456 ; encoding: [0x69,0x04,0xc2,0xc9,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x69,0x04,0xc2,0xc9,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s1, v2 :: v_dual_fmaak_f32 v6, s1, v3, 0xaf123456 ; encoding: [0x01,0x04,0xc2,0xc9,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x04,0xc2,0xc9,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, ttmp15, v2 :: v_dual_fmaak_f32 v6, ttmp15, v3, 0xaf123456 ; encoding: [0x7b,0x04,0xc2,0xc9,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0x04,0xc2,0xc9,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_hi, v2 :: v_dual_fmaak_f32 v6, exec_hi, v3, 0xaf123456 ; encoding: [0x7f,0x04,0xc2,0xc9,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0x04,0xc2,0xc9,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_lo, v2 :: v_dual_fmaak_f32 v6, exec_lo, v3, 0xaf123456 ; encoding: [0x7e,0x04,0xc2,0xc9,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0x04,0xc2,0xc9,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, m0, v2 :: v_dual_fmaak_f32 v6, m0, v3, 0xaf123456 ; encoding: [0x7d,0x04,0xc2,0xc9,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0x04,0xc2,0xc9,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_hi, v2 :: v_dual_fmaak_f32 v6, vcc_hi, v3, 0xaf123456 ; encoding: [0x6b,0x04,0xc2,0xc9,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0x04,0xc2,0xc9,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_lo, v2 :: v_dual_fmaak_f32 v6, vcc_lo, v3, 0xaf123456 ; encoding: [0x6a,0x04,0xc2,0xc9,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0x04,0xc2,0xc9,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, null, v3, 0xaf123456 ; encoding: [0xff,0x04,0xc2,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xc2,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, src_scc, v2 :: v_dual_fmaak_f32 v6, -1, v3, 0xaf123456 ; encoding: [0xfd,0x04,0xc2,0xc9,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0x04,0xc2,0xc9,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_fmaak_f32 v6, 0.5, v2, 0xaf123456 ; encoding: [0xf0,0x06,0xc2,0xc9,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0xc2,0xc9,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_fmaak_f32 v6, src_scc, v5, 0xaf123456 ; encoding: [0xc1,0x08,0xc2,0xc9,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0xc2,0xc9,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_fmaak_f32 v255, 0xaf123456, v4, 0xaf123456 ; encoding: [0x7c,0x0a,0xc2,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xc2,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v4, v2 :: v_dual_fmac_f32 v6, v1, v3 ; encoding: [0x04,0x05,0xc0,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0xc0,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v1, v2 :: v_dual_fmac_f32 v6, v255, v3 ; encoding: [0x01,0x05,0xc0,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0xc0,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v255, v2 :: v_dual_fmac_f32 v6, v2, v3 ; encoding: [0xff,0x05,0xc0,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0xc0,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v2, v2 :: v_dual_fmac_f32 v6, v3, v3 ; encoding: [0x02,0x05,0xc0,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0xc0,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v3, v2 :: v_dual_fmac_f32 v6, v4, v3 ; encoding: [0x03,0x05,0xc0,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0xc0,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s105, v2 :: v_dual_fmac_f32 v6, s1, v3 ; encoding: [0x69,0x04,0xc0,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0xc0,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s1, v2 :: v_dual_fmac_f32 v6, s105, v3 ; encoding: [0x01,0x04,0xc0,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0xc0,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, ttmp15, v2 :: v_dual_fmac_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xc0,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xc0,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_hi, v2 :: v_dual_fmac_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xc0,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xc0,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_lo, v2 :: v_dual_fmac_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xc0,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xc0,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, m0, v2 :: v_dual_fmac_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0xc0,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xc0,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_hi, v2 :: v_dual_fmac_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xc0,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xc0,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_lo, v2 :: v_dual_fmac_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xc0,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xc0,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v2 :: v_dual_fmac_f32 v6, null, v3 ; encoding: [0xff,0x04,0xc0,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xc0,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, src_scc, v2 :: v_dual_fmac_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0xc0,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xc0,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_fmac_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xc0,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xc0,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_fmac_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xc0,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xc0,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_fmac_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xc0,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xc0,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v4, v255 :: v_dual_fmamk_f32 v6, v1, 0xaf123456, v255 ; encoding: [0x04,0xff,0xc5,0xc9,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x04,0xff,0xc5,0xc9,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v1, v255 :: v_dual_fmamk_f32 v6, v255, 0xaf123456, v255 ; encoding: [0x01,0xff,0xc5,0xc9,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xff,0xc5,0xc9,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v255, v255 :: v_dual_fmamk_f32 v6, v2, 0xaf123456, v255 ; encoding: [0xff,0xff,0xc5,0xc9,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xff,0xc5,0xc9,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v2, v255 :: v_dual_fmamk_f32 v6, v3, 0xaf123456, v255 ; encoding: [0x02,0xff,0xc5,0xc9,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x02,0xff,0xc5,0xc9,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v3, v255 :: v_dual_fmamk_f32 v6, v4, 0xaf123456, v255 ; encoding: [0x03,0xff,0xc5,0xc9,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x03,0xff,0xc5,0xc9,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s105, v255 :: v_dual_fmamk_f32 v6, s105, 0xaf123456, v255 ; encoding: [0x69,0xfe,0xc5,0xc9,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x69,0xfe,0xc5,0xc9,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s1, v255 :: v_dual_fmamk_f32 v6, s1, 0xaf123456, v255 ; encoding: [0x01,0xfe,0xc5,0xc9,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xfe,0xc5,0xc9,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, ttmp15, v255 :: v_dual_fmamk_f32 v6, ttmp15, 0xaf123456, v255 ; encoding: [0x7b,0xfe,0xc5,0xc9,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0xfe,0xc5,0xc9,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_hi, v255 :: v_dual_fmamk_f32 v6, exec_hi, 0xaf123456, v255 ; encoding: [0x7f,0xfe,0xc5,0xc9,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0xfe,0xc5,0xc9,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_lo, v255 :: v_dual_fmamk_f32 v6, exec_lo, 0xaf123456, v255 ; encoding: [0x7e,0xfe,0xc5,0xc9,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0xfe,0xc5,0xc9,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, m0, v255 :: v_dual_fmamk_f32 v6, m0, 0xaf123456, v255 ; encoding: [0x7d,0xfe,0xc5,0xc9,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0xfe,0xc5,0xc9,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_hi, v255 :: v_dual_fmamk_f32 v6, vcc_hi, 0xaf123456, v255 ; encoding: [0x6b,0xfe,0xc5,0xc9,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0xfe,0xc5,0xc9,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_lo, v255 :: v_dual_fmamk_f32 v6, vcc_lo, 0xaf123456, v255 ; encoding: [0x6a,0xfe,0xc5,0xc9,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0xfe,0xc5,0xc9,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, null, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xc5,0xc9,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xc5,0xc9,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, src_scc, v255 :: v_dual_fmamk_f32 v6, -1, 0xaf123456, v255 ; encoding: [0xfd,0xfe,0xc5,0xc9,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0xfe,0xc5,0xc9,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_fmamk_f32 v6, 0.5, 0xaf123456, v255 ; encoding: [0xf0,0x06,0xc4,0xc9,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0xc4,0xc9,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_fmamk_f32 v6, src_scc, 0xaf123456, v255 ; encoding: [0xc1,0x08,0xc4,0xc9,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0xc4,0xc9,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xc4,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xc4,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v4, v2 :: v_dual_lshlrev_b32 v6, v1, v3 ; encoding: [0x04,0x05,0xe2,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0xe2,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v1, v2 :: v_dual_lshlrev_b32 v6, v255, v3 ; encoding: [0x01,0x05,0xe2,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0xe2,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v255, v2 :: v_dual_lshlrev_b32 v6, v2, v3 ; encoding: [0xff,0x05,0xe2,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0xe2,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v2, v2 :: v_dual_lshlrev_b32 v6, v3, v3 ; encoding: [0x02,0x05,0xe2,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0xe2,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v3, v2 :: v_dual_lshlrev_b32 v6, v4, v3 ; encoding: [0x03,0x05,0xe2,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0xe2,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s105, v2 :: v_dual_lshlrev_b32 v6, s1, v3 ; encoding: [0x69,0x04,0xe2,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0xe2,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s1, v2 :: v_dual_lshlrev_b32 v6, s105, v3 ; encoding: [0x01,0x04,0xe2,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0xe2,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, ttmp15, v2 :: v_dual_lshlrev_b32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xe2,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xe2,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_hi, v2 :: v_dual_lshlrev_b32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xe2,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xe2,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_lo, v2 :: v_dual_lshlrev_b32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xe2,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xe2,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, m0, v2 :: v_dual_lshlrev_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0xe2,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xe2,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_hi, v2 :: v_dual_lshlrev_b32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xe2,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xe2,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_lo, v2 :: v_dual_lshlrev_b32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xe2,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xe2,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v2 :: v_dual_lshlrev_b32 v6, null, v3 ; encoding: [0xff,0x04,0xe2,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xe2,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, src_scc, v2 :: v_dual_lshlrev_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0xe2,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xe2,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_lshlrev_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xe2,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xe2,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_lshlrev_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xe2,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xe2,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_lshlrev_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xe2,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xe2,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v4, v2 :: v_dual_max_num_f32 v6, v1, v3 ; encoding: [0x04,0x05,0xd4,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0xd4,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v1, v2 :: v_dual_max_num_f32 v6, v255, v3 ; encoding: [0x01,0x05,0xd4,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0xd4,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v255, v2 :: v_dual_max_num_f32 v6, v2, v3 ; encoding: [0xff,0x05,0xd4,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0xd4,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v2, v2 :: v_dual_max_num_f32 v6, v3, v3 ; encoding: [0x02,0x05,0xd4,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0xd4,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v3, v2 :: v_dual_max_num_f32 v6, v4, v3 ; encoding: [0x03,0x05,0xd4,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0xd4,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s105, v2 :: v_dual_max_num_f32 v6, s1, v3 ; encoding: [0x69,0x04,0xd4,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0xd4,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s1, v2 :: v_dual_max_num_f32 v6, s105, v3 ; encoding: [0x01,0x04,0xd4,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0xd4,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, ttmp15, v2 :: v_dual_max_num_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xd4,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xd4,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_hi, v2 :: v_dual_max_num_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xd4,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xd4,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_lo, v2 :: v_dual_max_num_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xd4,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xd4,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, m0, v2 :: v_dual_max_num_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0xd4,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xd4,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_hi, v2 :: v_dual_max_num_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xd4,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xd4,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_lo, v2 :: v_dual_max_num_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xd4,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xd4,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v2 :: v_dual_max_num_f32 v6, null, v3 ; encoding: [0xff,0x04,0xd4,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xd4,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, src_scc, v2 :: v_dual_max_num_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0xd4,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xd4,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_max_num_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xd4,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xd4,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_max_num_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xd4,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xd4,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_max_num_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xd4,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xd4,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v4, v2 :: v_dual_min_num_f32 v6, v1, v3 ; encoding: [0x04,0x05,0xd6,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0xd6,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v1, v2 :: v_dual_min_num_f32 v6, v255, v3 ; encoding: [0x01,0x05,0xd6,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0xd6,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v255, v2 :: v_dual_min_num_f32 v6, v2, v3 ; encoding: [0xff,0x05,0xd6,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0xd6,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v2, v2 :: v_dual_min_num_f32 v6, v3, v3 ; encoding: [0x02,0x05,0xd6,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0xd6,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v3, v2 :: v_dual_min_num_f32 v6, v4, v3 ; encoding: [0x03,0x05,0xd6,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0xd6,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s105, v2 :: v_dual_min_num_f32 v6, s1, v3 ; encoding: [0x69,0x04,0xd6,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0xd6,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s1, v2 :: v_dual_min_num_f32 v6, s105, v3 ; encoding: [0x01,0x04,0xd6,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0xd6,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, ttmp15, v2 :: v_dual_min_num_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xd6,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xd6,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_hi, v2 :: v_dual_min_num_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xd6,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xd6,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_lo, v2 :: v_dual_min_num_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xd6,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xd6,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, m0, v2 :: v_dual_min_num_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0xd6,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xd6,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_hi, v2 :: v_dual_min_num_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xd6,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xd6,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_lo, v2 :: v_dual_min_num_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xd6,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xd6,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v2 :: v_dual_min_num_f32 v6, null, v3 ; encoding: [0xff,0x04,0xd6,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xd6,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, src_scc, v2 :: v_dual_min_num_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0xd6,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xd6,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_min_num_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xd6,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xd6,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_min_num_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xd6,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xd6,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_min_num_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xd6,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xd6,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v4, v255 :: v_dual_mov_b32 v6, v1 ; encoding: [0x04,0xff,0xd1,0xc9,0x01,0x01,0x06,0xff]
+0x04,0xff,0xd1,0xc9,0x01,0x01,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v1, v255 :: v_dual_mov_b32 v6, v255 ; encoding: [0x01,0xff,0xd1,0xc9,0xff,0x01,0x06,0xff]
+0x01,0xff,0xd1,0xc9,0xff,0x01,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v255, v255 :: v_dual_mov_b32 v6, v2 ; encoding: [0xff,0xff,0xd1,0xc9,0x02,0x01,0x06,0xff]
+0xff,0xff,0xd1,0xc9,0x02,0x01,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v2, v255 :: v_dual_mov_b32 v6, v3 ; encoding: [0x02,0xff,0xd1,0xc9,0x03,0x01,0x06,0xff]
+0x02,0xff,0xd1,0xc9,0x03,0x01,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v3, v255 :: v_dual_mov_b32 v6, v4 ; encoding: [0x03,0xff,0xd1,0xc9,0x04,0x01,0x06,0xff]
+0x03,0xff,0xd1,0xc9,0x04,0x01,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s105, v255 :: v_dual_mov_b32 v6, s1 ; encoding: [0x69,0xfe,0xd1,0xc9,0x01,0x00,0x06,0xff]
+0x69,0xfe,0xd1,0xc9,0x01,0x00,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s1, v255 :: v_dual_mov_b32 v6, s105 ; encoding: [0x01,0xfe,0xd1,0xc9,0x69,0x00,0x06,0xff]
+0x01,0xfe,0xd1,0xc9,0x69,0x00,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, ttmp15, v255 :: v_dual_mov_b32 v6, vcc_lo ; encoding: [0x7b,0xfe,0xd1,0xc9,0x6a,0x00,0x06,0xff]
+0x7b,0xfe,0xd1,0xc9,0x6a,0x00,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_hi, v255 :: v_dual_mov_b32 v6, vcc_hi ; encoding: [0x7f,0xfe,0xd1,0xc9,0x6b,0x00,0x06,0xff]
+0x7f,0xfe,0xd1,0xc9,0x6b,0x00,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_lo, v255 :: v_dual_mov_b32 v6, ttmp15 ; encoding: [0x7e,0xfe,0xd1,0xc9,0x7b,0x00,0x06,0xff]
+0x7e,0xfe,0xd1,0xc9,0x7b,0x00,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, m0, v255 :: v_dual_mov_b32 v6, m0 ; encoding: [0x7d,0xfe,0xd1,0xc9,0x7d,0x00,0x06,0xff]
+0x7d,0xfe,0xd1,0xc9,0x7d,0x00,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_hi, v255 :: v_dual_mov_b32 v6, exec_lo ; encoding: [0x6b,0xfe,0xd1,0xc9,0x7e,0x00,0x06,0xff]
+0x6b,0xfe,0xd1,0xc9,0x7e,0x00,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_lo, v255 :: v_dual_mov_b32 v6, exec_hi ; encoding: [0x6a,0xfe,0xd1,0xc9,0x7f,0x00,0x06,0xff]
+0x6a,0xfe,0xd1,0xc9,0x7f,0x00,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v255 :: v_dual_mov_b32 v6, null ; encoding: [0xff,0xfe,0xd1,0xc9,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xd1,0xc9,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, src_scc, v255 :: v_dual_mov_b32 v6, -1 ; encoding: [0xfd,0xfe,0xd1,0xc9,0xc1,0x00,0x06,0xff]
+0xfd,0xfe,0xd1,0xc9,0xc1,0x00,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_mov_b32 v6, 0.5 ; encoding: [0xf0,0x06,0xd0,0xc9,0xf0,0x00,0x06,0xff]
+0xf0,0x06,0xd0,0xc9,0xf0,0x00,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_mov_b32 v6, src_scc ; encoding: [0xc1,0x08,0xd0,0xc9,0xfd,0x00,0x06,0xff]
+0xc1,0x08,0xd0,0xc9,0xfd,0x00,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_mov_b32 v255, 0xaf123456 ; encoding: [0x7c,0x0a,0xd0,0xc9,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xd0,0xc9,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v4, v2 :: v_dual_mul_dx9_zero_f32 v6, v1, v3 ; encoding: [0x04,0x05,0xce,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0xce,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v1, v2 :: v_dual_mul_dx9_zero_f32 v6, v255, v3 ; encoding: [0x01,0x05,0xce,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0xce,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v255, v2 :: v_dual_mul_dx9_zero_f32 v6, v2, v3 ; encoding: [0xff,0x05,0xce,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0xce,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v2, v2 :: v_dual_mul_dx9_zero_f32 v6, v3, v3 ; encoding: [0x02,0x05,0xce,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0xce,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v3, v2 :: v_dual_mul_dx9_zero_f32 v6, v4, v3 ; encoding: [0x03,0x05,0xce,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0xce,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s105, v2 :: v_dual_mul_dx9_zero_f32 v6, s1, v3 ; encoding: [0x69,0x04,0xce,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0xce,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s1, v2 :: v_dual_mul_dx9_zero_f32 v6, s105, v3 ; encoding: [0x01,0x04,0xce,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0xce,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, ttmp15, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xce,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xce,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xce,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xce,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xce,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xce,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, m0, v2 :: v_dual_mul_dx9_zero_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0xce,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xce,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xce,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xce,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xce,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xce,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v2 :: v_dual_mul_dx9_zero_f32 v6, null, v3 ; encoding: [0xff,0x04,0xce,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xce,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, src_scc, v2 :: v_dual_mul_dx9_zero_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0xce,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xce,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_mul_dx9_zero_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xce,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xce,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_mul_dx9_zero_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xce,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xce,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xce,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xce,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v4, v2 :: v_dual_mul_f32 v6, v1, v3 ; encoding: [0x04,0x05,0xc6,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0xc6,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v1, v2 :: v_dual_mul_f32 v6, v255, v3 ; encoding: [0x01,0x05,0xc6,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0xc6,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v255, v2 :: v_dual_mul_f32 v6, v2, v3 ; encoding: [0xff,0x05,0xc6,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0xc6,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v2, v2 :: v_dual_mul_f32 v6, v3, v3 ; encoding: [0x02,0x05,0xc6,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0xc6,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v3, v2 :: v_dual_mul_f32 v6, v4, v3 ; encoding: [0x03,0x05,0xc6,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0xc6,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s105, v2 :: v_dual_mul_f32 v6, s1, v3 ; encoding: [0x69,0x04,0xc6,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0xc6,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s1, v2 :: v_dual_mul_f32 v6, s105, v3 ; encoding: [0x01,0x04,0xc6,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0xc6,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, ttmp15, v2 :: v_dual_mul_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xc6,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xc6,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_hi, v2 :: v_dual_mul_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xc6,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xc6,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_lo, v2 :: v_dual_mul_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xc6,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xc6,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, m0, v2 :: v_dual_mul_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0xc6,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xc6,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_hi, v2 :: v_dual_mul_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xc6,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xc6,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_lo, v2 :: v_dual_mul_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xc6,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xc6,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v2 :: v_dual_mul_f32 v6, null, v3 ; encoding: [0xff,0x04,0xc6,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xc6,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, src_scc, v2 :: v_dual_mul_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0xc6,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xc6,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_mul_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xc6,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xc6,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_mul_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xc6,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xc6,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_mul_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xc6,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xc6,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v4, v2 :: v_dual_sub_f32 v6, v1, v3 ; encoding: [0x04,0x05,0xca,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0xca,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v1, v2 :: v_dual_sub_f32 v6, v255, v3 ; encoding: [0x01,0x05,0xca,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0xca,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v255, v2 :: v_dual_sub_f32 v6, v2, v3 ; encoding: [0xff,0x05,0xca,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0xca,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v2, v2 :: v_dual_sub_f32 v6, v3, v3 ; encoding: [0x02,0x05,0xca,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0xca,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v3, v2 :: v_dual_sub_f32 v6, v4, v3 ; encoding: [0x03,0x05,0xca,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0xca,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s105, v2 :: v_dual_sub_f32 v6, s1, v3 ; encoding: [0x69,0x04,0xca,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0xca,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s1, v2 :: v_dual_sub_f32 v6, s105, v3 ; encoding: [0x01,0x04,0xca,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0xca,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, ttmp15, v2 :: v_dual_sub_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xca,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xca,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_hi, v2 :: v_dual_sub_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xca,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xca,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_lo, v2 :: v_dual_sub_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xca,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xca,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, m0, v2 :: v_dual_sub_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0xca,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xca,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_hi, v2 :: v_dual_sub_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xca,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xca,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_lo, v2 :: v_dual_sub_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xca,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xca,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v2 :: v_dual_sub_f32 v6, null, v3 ; encoding: [0xff,0x04,0xca,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xca,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, src_scc, v2 :: v_dual_sub_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0xca,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xca,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_sub_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xca,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xca,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_sub_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xca,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xca,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_sub_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xca,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xca,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v4, v2 :: v_dual_subrev_f32 v6, v1, v3 ; encoding: [0x04,0x05,0xcc,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0xcc,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v1, v2 :: v_dual_subrev_f32 v6, v255, v3 ; encoding: [0x01,0x05,0xcc,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0xcc,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v255, v2 :: v_dual_subrev_f32 v6, v2, v3 ; encoding: [0xff,0x05,0xcc,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0xcc,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v2, v2 :: v_dual_subrev_f32 v6, v3, v3 ; encoding: [0x02,0x05,0xcc,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0xcc,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, v3, v2 :: v_dual_subrev_f32 v6, v4, v3 ; encoding: [0x03,0x05,0xcc,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0xcc,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s105, v2 :: v_dual_subrev_f32 v6, s1, v3 ; encoding: [0x69,0x04,0xcc,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0xcc,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, s1, v2 :: v_dual_subrev_f32 v6, s105, v3 ; encoding: [0x01,0x04,0xcc,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0xcc,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, ttmp15, v2 :: v_dual_subrev_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xcc,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xcc,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_hi, v2 :: v_dual_subrev_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xcc,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xcc,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, exec_lo, v2 :: v_dual_subrev_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xcc,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xcc,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, m0, v2 :: v_dual_subrev_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0xcc,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xcc,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_hi, v2 :: v_dual_subrev_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xcc,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xcc,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, vcc_lo, v2 :: v_dual_subrev_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xcc,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xcc,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v2 :: v_dual_subrev_f32 v6, null, v3 ; encoding: [0xff,0x04,0xcc,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xcc,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, src_scc, v2 :: v_dual_subrev_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0xcc,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xcc,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, 0.5, v3 :: v_dual_subrev_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xcc,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xcc,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v255, -1, v4 :: v_dual_subrev_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xcc,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xcc,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_mul_dx9_zero_f32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xcc,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xcc,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, v4, v2 :: v_dual_add_f32 v6, v1, v3 ; encoding: [0x04,0x05,0xc8,0xc8,0x01,0x07,0x06,0xff]
+0x04,0x05,0xc8,0xc8,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v1, v2 :: v_dual_add_f32 v6, v255, v3 ; encoding: [0x01,0x05,0xc8,0xc8,0xff,0x07,0x06,0xff]
+0x01,0x05,0xc8,0xc8,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v255, v2 :: v_dual_add_f32 v6, v2, v3 ; encoding: [0xff,0x05,0xc8,0xc8,0x02,0x07,0x06,0xff]
+0xff,0x05,0xc8,0xc8,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v2, v2 :: v_dual_add_f32 v6, v3, v3 ; encoding: [0x02,0x05,0xc8,0xc8,0x03,0x07,0x06,0xff]
+0x02,0x05,0xc8,0xc8,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v3, v2 :: v_dual_add_f32 v6, v4, v3 ; encoding: [0x03,0x05,0xc8,0xc8,0x04,0x07,0x06,0xff]
+0x03,0x05,0xc8,0xc8,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, s105, v2 :: v_dual_add_f32 v6, s1, v3 ; encoding: [0x69,0x04,0xc8,0xc8,0x01,0x06,0x06,0xff]
+0x69,0x04,0xc8,0xc8,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, s1, v2 :: v_dual_add_f32 v6, s105, v3 ; encoding: [0x01,0x04,0xc8,0xc8,0x69,0x06,0x06,0xff]
+0x01,0x04,0xc8,0xc8,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, ttmp15, v2 :: v_dual_add_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xc8,0xc8,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xc8,0xc8,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, exec_hi, v2 :: v_dual_add_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xc8,0xc8,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xc8,0xc8,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, exec_lo, v2 :: v_dual_add_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xc8,0xc8,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xc8,0xc8,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, m0, v2 :: v_dual_add_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0xc8,0xc8,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xc8,0xc8,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, vcc_hi, v2 :: v_dual_add_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xc8,0xc8,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xc8,0xc8,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, vcc_lo, v2 :: v_dual_add_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xc8,0xc8,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xc8,0xc8,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, 0xaf123456, v2 :: v_dual_add_f32 v6, null, v3 ; encoding: [0xff,0x04,0xc8,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xc8,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, src_scc, v2 :: v_dual_add_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0xc8,0xc8,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xc8,0xc8,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, 0.5, v3 :: v_dual_add_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xc8,0xc8,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xc8,0xc8,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, -1, v4 :: v_dual_add_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xc8,0xc8,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xc8,0xc8,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v6, null, v5 :: v_dual_add_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xc8,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xc8,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, v4, v2 :: v_dual_add_nc_u32 v6, v1, v3 ; encoding: [0x04,0x05,0xe0,0xc8,0x01,0x07,0x06,0xff]
+0x04,0x05,0xe0,0xc8,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v1, v2 :: v_dual_add_nc_u32 v6, v255, v3 ; encoding: [0x01,0x05,0xe0,0xc8,0xff,0x07,0x06,0xff]
+0x01,0x05,0xe0,0xc8,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v255, v2 :: v_dual_add_nc_u32 v6, v2, v3 ; encoding: [0xff,0x05,0xe0,0xc8,0x02,0x07,0x06,0xff]
+0xff,0x05,0xe0,0xc8,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v2, v2 :: v_dual_add_nc_u32 v6, v3, v3 ; encoding: [0x02,0x05,0xe0,0xc8,0x03,0x07,0x06,0xff]
+0x02,0x05,0xe0,0xc8,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v3, v2 :: v_dual_add_nc_u32 v6, v4, v3 ; encoding: [0x03,0x05,0xe0,0xc8,0x04,0x07,0x06,0xff]
+0x03,0x05,0xe0,0xc8,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, s105, v2 :: v_dual_add_nc_u32 v6, s1, v3 ; encoding: [0x69,0x04,0xe0,0xc8,0x01,0x06,0x06,0xff]
+0x69,0x04,0xe0,0xc8,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, s1, v2 :: v_dual_add_nc_u32 v6, s105, v3 ; encoding: [0x01,0x04,0xe0,0xc8,0x69,0x06,0x06,0xff]
+0x01,0x04,0xe0,0xc8,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, ttmp15, v2 :: v_dual_add_nc_u32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xe0,0xc8,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xe0,0xc8,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, exec_hi, v2 :: v_dual_add_nc_u32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xe0,0xc8,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xe0,0xc8,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, exec_lo, v2 :: v_dual_add_nc_u32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xe0,0xc8,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xe0,0xc8,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, m0, v2 :: v_dual_add_nc_u32 v6, m0, v3 ; encoding: [0x7d,0x04,0xe0,0xc8,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xe0,0xc8,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, vcc_hi, v2 :: v_dual_add_nc_u32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xe0,0xc8,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xe0,0xc8,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, vcc_lo, v2 :: v_dual_add_nc_u32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xe0,0xc8,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xe0,0xc8,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, 0xaf123456, v2 :: v_dual_add_nc_u32 v6, null, v3 ; encoding: [0xff,0x04,0xe0,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xe0,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, src_scc, v2 :: v_dual_add_nc_u32 v6, -1, v3 ; encoding: [0xfd,0x04,0xe0,0xc8,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xe0,0xc8,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, 0.5, v3 :: v_dual_add_nc_u32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xe0,0xc8,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xe0,0xc8,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, -1, v4 :: v_dual_add_nc_u32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xe0,0xc8,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xe0,0xc8,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v6, null, v5 :: v_dual_add_nc_u32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xe0,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xe0,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, v4, v2 :: v_dual_and_b32 v6, v1, v3 ; encoding: [0x04,0x05,0xe4,0xc8,0x01,0x07,0x06,0xff]
+0x04,0x05,0xe4,0xc8,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v1, v2 :: v_dual_and_b32 v6, v255, v3 ; encoding: [0x01,0x05,0xe4,0xc8,0xff,0x07,0x06,0xff]
+0x01,0x05,0xe4,0xc8,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v255, v2 :: v_dual_and_b32 v6, v2, v3 ; encoding: [0xff,0x05,0xe4,0xc8,0x02,0x07,0x06,0xff]
+0xff,0x05,0xe4,0xc8,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v2, v2 :: v_dual_and_b32 v6, v3, v3 ; encoding: [0x02,0x05,0xe4,0xc8,0x03,0x07,0x06,0xff]
+0x02,0x05,0xe4,0xc8,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v3, v2 :: v_dual_and_b32 v6, v4, v3 ; encoding: [0x03,0x05,0xe4,0xc8,0x04,0x07,0x06,0xff]
+0x03,0x05,0xe4,0xc8,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, s105, v2 :: v_dual_and_b32 v6, s1, v3 ; encoding: [0x69,0x04,0xe4,0xc8,0x01,0x06,0x06,0xff]
+0x69,0x04,0xe4,0xc8,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, s1, v2 :: v_dual_and_b32 v6, s105, v3 ; encoding: [0x01,0x04,0xe4,0xc8,0x69,0x06,0x06,0xff]
+0x01,0x04,0xe4,0xc8,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, ttmp15, v2 :: v_dual_and_b32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xe4,0xc8,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xe4,0xc8,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, exec_hi, v2 :: v_dual_and_b32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xe4,0xc8,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xe4,0xc8,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, exec_lo, v2 :: v_dual_and_b32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xe4,0xc8,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xe4,0xc8,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, m0, v2 :: v_dual_and_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0xe4,0xc8,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xe4,0xc8,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, vcc_hi, v2 :: v_dual_and_b32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xe4,0xc8,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xe4,0xc8,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, vcc_lo, v2 :: v_dual_and_b32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xe4,0xc8,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xe4,0xc8,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, 0xaf123456, v2 :: v_dual_and_b32 v6, null, v3 ; encoding: [0xff,0x04,0xe4,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xe4,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, src_scc, v2 :: v_dual_and_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0xe4,0xc8,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xe4,0xc8,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, 0.5, v3 :: v_dual_and_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xe4,0xc8,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xe4,0xc8,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, -1, v4 :: v_dual_and_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xe4,0xc8,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xe4,0xc8,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v6, null, v5 :: v_dual_and_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xe4,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xe4,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, v4, v2 :: v_dual_cndmask_b32 v6, v1, v3 ; encoding: [0x04,0x05,0xd2,0xc8,0x01,0x07,0x06,0xff]
+0x04,0x05,0xd2,0xc8,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v1, v2 :: v_dual_cndmask_b32 v6, v255, v3 ; encoding: [0x01,0x05,0xd2,0xc8,0xff,0x07,0x06,0xff]
+0x01,0x05,0xd2,0xc8,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v255, v2 :: v_dual_cndmask_b32 v6, v2, v3 ; encoding: [0xff,0x05,0xd2,0xc8,0x02,0x07,0x06,0xff]
+0xff,0x05,0xd2,0xc8,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v2, v2 :: v_dual_cndmask_b32 v6, v3, v3 ; encoding: [0x02,0x05,0xd2,0xc8,0x03,0x07,0x06,0xff]
+0x02,0x05,0xd2,0xc8,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v3, v2 :: v_dual_cndmask_b32 v6, v4, v3 ; encoding: [0x03,0x05,0xd2,0xc8,0x04,0x07,0x06,0xff]
+0x03,0x05,0xd2,0xc8,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, s105, v2 :: v_dual_cndmask_b32 v6, s105, v3 ; encoding: [0x69,0x04,0xd2,0xc8,0x69,0x06,0x06,0xff]
+0x69,0x04,0xd2,0xc8,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, s1, v2 :: v_dual_cndmask_b32 v6, s1, v3 ; encoding: [0x01,0x04,0xd2,0xc8,0x01,0x06,0x06,0xff]
+0x01,0x04,0xd2,0xc8,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, ttmp15, v2 :: v_dual_cndmask_b32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0xd2,0xc8,0x7b,0x06,0x06,0xff]
+0x7b,0x04,0xd2,0xc8,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, exec_hi, v2 :: v_dual_cndmask_b32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0xd2,0xc8,0x7f,0x06,0x06,0xff]
+0x7f,0x04,0xd2,0xc8,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, exec_lo, v2 :: v_dual_cndmask_b32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0xd2,0xc8,0x7e,0x06,0x06,0xff]
+0x7e,0x04,0xd2,0xc8,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, m0, v2 :: v_dual_cndmask_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0xd2,0xc8,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xd2,0xc8,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, vcc_hi, v2 :: v_dual_cndmask_b32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0xd2,0xc8,0x6b,0x06,0x06,0xff]
+0x6b,0x04,0xd2,0xc8,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, vcc_lo, v2 :: v_dual_cndmask_b32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0xd2,0xc8,0x6a,0x06,0x06,0xff]
+0x6a,0x04,0xd2,0xc8,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, 0xaf123456, v2 :: v_dual_cndmask_b32 v6, null, v3 ; encoding: [0xff,0x04,0xd2,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xd2,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, src_scc, v2 :: v_dual_cndmask_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0xd2,0xc8,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xd2,0xc8,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, 0.5, v3 :: v_dual_cndmask_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xd2,0xc8,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xd2,0xc8,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, -1, v4 :: v_dual_cndmask_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xd2,0xc8,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xd2,0xc8,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v6, null, v5 :: v_dual_cndmask_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xd2,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xd2,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, v4, v2 :: v_dual_fmaak_f32 v6, v1, v3, 0xaf123456 ; encoding: [0x04,0x05,0xc2,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x04,0x05,0xc2,0xc8,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, v1, v2 :: v_dual_fmaak_f32 v6, v255, v3, 0xaf123456 ; encoding: [0x01,0x05,0xc2,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x05,0xc2,0xc8,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, v255, v2 :: v_dual_fmaak_f32 v6, v2, v3, 0xaf123456 ; encoding: [0xff,0x05,0xc2,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x05,0xc2,0xc8,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, v2, v2 :: v_dual_fmaak_f32 v6, v3, v3, 0xaf123456 ; encoding: [0x02,0x05,0xc2,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x02,0x05,0xc2,0xc8,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, v3, v2 :: v_dual_fmaak_f32 v6, v4, v3, 0xaf123456 ; encoding: [0x03,0x05,0xc2,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x03,0x05,0xc2,0xc8,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, s105, v2 :: v_dual_fmaak_f32 v6, s105, v3, 0xaf123456 ; encoding: [0x69,0x04,0xc2,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x69,0x04,0xc2,0xc8,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, s1, v2 :: v_dual_fmaak_f32 v6, s1, v3, 0xaf123456 ; encoding: [0x01,0x04,0xc2,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x04,0xc2,0xc8,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, ttmp15, v2 :: v_dual_fmaak_f32 v6, ttmp15, v3, 0xaf123456 ; encoding: [0x7b,0x04,0xc2,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0x04,0xc2,0xc8,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, exec_hi, v2 :: v_dual_fmaak_f32 v6, exec_hi, v3, 0xaf123456 ; encoding: [0x7f,0x04,0xc2,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0x04,0xc2,0xc8,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, exec_lo, v2 :: v_dual_fmaak_f32 v6, exec_lo, v3, 0xaf123456 ; encoding: [0x7e,0x04,0xc2,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0x04,0xc2,0xc8,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, m0, v2 :: v_dual_fmaak_f32 v6, m0, v3, 0xaf123456 ; encoding: [0x7d,0x04,0xc2,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0x04,0xc2,0xc8,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, vcc_hi, v2 :: v_dual_fmaak_f32 v6, vcc_hi, v3, 0xaf123456 ; encoding: [0x6b,0x04,0xc2,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0x04,0xc2,0xc8,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, vcc_lo, v2 :: v_dual_fmaak_f32 v6, vcc_lo, v3, 0xaf123456 ; encoding: [0x6a,0x04,0xc2,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0x04,0xc2,0xc8,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, null, v3, 0xaf123456 ; encoding: [0xff,0x04,0xc2,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xc2,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, src_scc, v2 :: v_dual_fmaak_f32 v6, -1, v3, 0xaf123456 ; encoding: [0xfd,0x04,0xc2,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0x04,0xc2,0xc8,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, 0.5, v3 :: v_dual_fmaak_f32 v6, 0.5, v2, 0xaf123456 ; encoding: [0xf0,0x06,0xc2,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0xc2,0xc8,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, -1, v4 :: v_dual_fmaak_f32 v6, src_scc, v5, 0xaf123456 ; encoding: [0xc1,0x08,0xc2,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0xc2,0xc8,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v6, null, v5 :: v_dual_fmaak_f32 v255, 0xaf123456, v4, 0xaf123456 ; encoding: [0x7c,0x0a,0xc2,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xc2,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, v4, v2 :: v_dual_fmac_f32 v6, v1, v3 ; encoding: [0x04,0x05,0xc0,0xc8,0x01,0x07,0x06,0xff]
+0x04,0x05,0xc0,0xc8,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v1, v2 :: v_dual_fmac_f32 v6, v255, v3 ; encoding: [0x01,0x05,0xc0,0xc8,0xff,0x07,0x06,0xff]
+0x01,0x05,0xc0,0xc8,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v255, v2 :: v_dual_fmac_f32 v6, v2, v3 ; encoding: [0xff,0x05,0xc0,0xc8,0x02,0x07,0x06,0xff]
+0xff,0x05,0xc0,0xc8,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v2, v2 :: v_dual_fmac_f32 v6, v3, v3 ; encoding: [0x02,0x05,0xc0,0xc8,0x03,0x07,0x06,0xff]
+0x02,0x05,0xc0,0xc8,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v3, v2 :: v_dual_fmac_f32 v6, v4, v3 ; encoding: [0x03,0x05,0xc0,0xc8,0x04,0x07,0x06,0xff]
+0x03,0x05,0xc0,0xc8,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, s105, v2 :: v_dual_fmac_f32 v6, s1, v3 ; encoding: [0x69,0x04,0xc0,0xc8,0x01,0x06,0x06,0xff]
+0x69,0x04,0xc0,0xc8,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, s1, v2 :: v_dual_fmac_f32 v6, s105, v3 ; encoding: [0x01,0x04,0xc0,0xc8,0x69,0x06,0x06,0xff]
+0x01,0x04,0xc0,0xc8,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, ttmp15, v2 :: v_dual_fmac_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xc0,0xc8,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xc0,0xc8,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, exec_hi, v2 :: v_dual_fmac_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xc0,0xc8,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xc0,0xc8,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, exec_lo, v2 :: v_dual_fmac_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xc0,0xc8,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xc0,0xc8,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, m0, v2 :: v_dual_fmac_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0xc0,0xc8,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xc0,0xc8,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, vcc_hi, v2 :: v_dual_fmac_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xc0,0xc8,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xc0,0xc8,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, vcc_lo, v2 :: v_dual_fmac_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xc0,0xc8,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xc0,0xc8,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, 0xaf123456, v2 :: v_dual_fmac_f32 v6, null, v3 ; encoding: [0xff,0x04,0xc0,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xc0,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, src_scc, v2 :: v_dual_fmac_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0xc0,0xc8,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xc0,0xc8,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, 0.5, v3 :: v_dual_fmac_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xc0,0xc8,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xc0,0xc8,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, -1, v4 :: v_dual_fmac_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xc0,0xc8,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xc0,0xc8,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v6, null, v5 :: v_dual_fmac_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xc0,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xc0,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, v4, v255 :: v_dual_fmamk_f32 v6, v1, 0xaf123456, v255 ; encoding: [0x04,0xff,0xc5,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x04,0xff,0xc5,0xc8,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, v1, v255 :: v_dual_fmamk_f32 v6, v255, 0xaf123456, v255 ; encoding: [0x01,0xff,0xc5,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xff,0xc5,0xc8,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, v255, v255 :: v_dual_fmamk_f32 v6, v2, 0xaf123456, v255 ; encoding: [0xff,0xff,0xc5,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xff,0xc5,0xc8,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, v2, v255 :: v_dual_fmamk_f32 v6, v3, 0xaf123456, v255 ; encoding: [0x02,0xff,0xc5,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x02,0xff,0xc5,0xc8,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, v3, v255 :: v_dual_fmamk_f32 v6, v4, 0xaf123456, v255 ; encoding: [0x03,0xff,0xc5,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x03,0xff,0xc5,0xc8,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, s105, v255 :: v_dual_fmamk_f32 v6, s105, 0xaf123456, v255 ; encoding: [0x69,0xfe,0xc5,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x69,0xfe,0xc5,0xc8,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, s1, v255 :: v_dual_fmamk_f32 v6, s1, 0xaf123456, v255 ; encoding: [0x01,0xfe,0xc5,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xfe,0xc5,0xc8,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, ttmp15, v255 :: v_dual_fmamk_f32 v6, ttmp15, 0xaf123456, v255 ; encoding: [0x7b,0xfe,0xc5,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0xfe,0xc5,0xc8,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, exec_hi, v255 :: v_dual_fmamk_f32 v6, exec_hi, 0xaf123456, v255 ; encoding: [0x7f,0xfe,0xc5,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0xfe,0xc5,0xc8,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, exec_lo, v255 :: v_dual_fmamk_f32 v6, exec_lo, 0xaf123456, v255 ; encoding: [0x7e,0xfe,0xc5,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0xfe,0xc5,0xc8,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, m0, v255 :: v_dual_fmamk_f32 v6, m0, 0xaf123456, v255 ; encoding: [0x7d,0xfe,0xc5,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0xfe,0xc5,0xc8,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, vcc_hi, v255 :: v_dual_fmamk_f32 v6, vcc_hi, 0xaf123456, v255 ; encoding: [0x6b,0xfe,0xc5,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0xfe,0xc5,0xc8,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, vcc_lo, v255 :: v_dual_fmamk_f32 v6, vcc_lo, 0xaf123456, v255 ; encoding: [0x6a,0xfe,0xc5,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0xfe,0xc5,0xc8,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, null, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xc5,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xc5,0xc8,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, src_scc, v255 :: v_dual_fmamk_f32 v6, -1, 0xaf123456, v255 ; encoding: [0xfd,0xfe,0xc5,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0xfe,0xc5,0xc8,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, 0.5, v3 :: v_dual_fmamk_f32 v6, 0.5, 0xaf123456, v255 ; encoding: [0xf0,0x06,0xc4,0xc8,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0xc4,0xc8,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, -1, v4 :: v_dual_fmamk_f32 v6, src_scc, 0xaf123456, v255 ; encoding: [0xc1,0x08,0xc4,0xc8,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0xc4,0xc8,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v6, null, v5 :: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xc4,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xc4,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, v4, v2 :: v_dual_lshlrev_b32 v6, v1, v3 ; encoding: [0x04,0x05,0xe2,0xc8,0x01,0x07,0x06,0xff]
+0x04,0x05,0xe2,0xc8,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v1, v2 :: v_dual_lshlrev_b32 v6, v255, v3 ; encoding: [0x01,0x05,0xe2,0xc8,0xff,0x07,0x06,0xff]
+0x01,0x05,0xe2,0xc8,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v255, v2 :: v_dual_lshlrev_b32 v6, v2, v3 ; encoding: [0xff,0x05,0xe2,0xc8,0x02,0x07,0x06,0xff]
+0xff,0x05,0xe2,0xc8,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v2, v2 :: v_dual_lshlrev_b32 v6, v3, v3 ; encoding: [0x02,0x05,0xe2,0xc8,0x03,0x07,0x06,0xff]
+0x02,0x05,0xe2,0xc8,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v3, v2 :: v_dual_lshlrev_b32 v6, v4, v3 ; encoding: [0x03,0x05,0xe2,0xc8,0x04,0x07,0x06,0xff]
+0x03,0x05,0xe2,0xc8,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, s105, v2 :: v_dual_lshlrev_b32 v6, s1, v3 ; encoding: [0x69,0x04,0xe2,0xc8,0x01,0x06,0x06,0xff]
+0x69,0x04,0xe2,0xc8,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, s1, v2 :: v_dual_lshlrev_b32 v6, s105, v3 ; encoding: [0x01,0x04,0xe2,0xc8,0x69,0x06,0x06,0xff]
+0x01,0x04,0xe2,0xc8,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, ttmp15, v2 :: v_dual_lshlrev_b32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xe2,0xc8,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xe2,0xc8,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, exec_hi, v2 :: v_dual_lshlrev_b32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xe2,0xc8,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xe2,0xc8,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, exec_lo, v2 :: v_dual_lshlrev_b32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xe2,0xc8,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xe2,0xc8,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, m0, v2 :: v_dual_lshlrev_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0xe2,0xc8,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xe2,0xc8,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, vcc_hi, v2 :: v_dual_lshlrev_b32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xe2,0xc8,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xe2,0xc8,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, vcc_lo, v2 :: v_dual_lshlrev_b32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xe2,0xc8,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xe2,0xc8,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, 0xaf123456, v2 :: v_dual_lshlrev_b32 v6, null, v3 ; encoding: [0xff,0x04,0xe2,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xe2,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, src_scc, v2 :: v_dual_lshlrev_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0xe2,0xc8,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xe2,0xc8,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, 0.5, v3 :: v_dual_lshlrev_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xe2,0xc8,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xe2,0xc8,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, -1, v4 :: v_dual_lshlrev_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xe2,0xc8,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xe2,0xc8,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v6, null, v5 :: v_dual_lshlrev_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xe2,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xe2,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, v4, v2 :: v_dual_max_num_f32 v6, v1, v3 ; encoding: [0x04,0x05,0xd4,0xc8,0x01,0x07,0x06,0xff]
+0x04,0x05,0xd4,0xc8,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v1, v2 :: v_dual_max_num_f32 v6, v255, v3 ; encoding: [0x01,0x05,0xd4,0xc8,0xff,0x07,0x06,0xff]
+0x01,0x05,0xd4,0xc8,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v255, v2 :: v_dual_max_num_f32 v6, v2, v3 ; encoding: [0xff,0x05,0xd4,0xc8,0x02,0x07,0x06,0xff]
+0xff,0x05,0xd4,0xc8,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v2, v2 :: v_dual_max_num_f32 v6, v3, v3 ; encoding: [0x02,0x05,0xd4,0xc8,0x03,0x07,0x06,0xff]
+0x02,0x05,0xd4,0xc8,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v3, v2 :: v_dual_max_num_f32 v6, v4, v3 ; encoding: [0x03,0x05,0xd4,0xc8,0x04,0x07,0x06,0xff]
+0x03,0x05,0xd4,0xc8,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, s105, v2 :: v_dual_max_num_f32 v6, s1, v3 ; encoding: [0x69,0x04,0xd4,0xc8,0x01,0x06,0x06,0xff]
+0x69,0x04,0xd4,0xc8,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, s1, v2 :: v_dual_max_num_f32 v6, s105, v3 ; encoding: [0x01,0x04,0xd4,0xc8,0x69,0x06,0x06,0xff]
+0x01,0x04,0xd4,0xc8,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, ttmp15, v2 :: v_dual_max_num_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xd4,0xc8,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xd4,0xc8,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, exec_hi, v2 :: v_dual_max_num_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xd4,0xc8,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xd4,0xc8,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, exec_lo, v2 :: v_dual_max_num_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xd4,0xc8,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xd4,0xc8,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, m0, v2 :: v_dual_max_num_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0xd4,0xc8,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xd4,0xc8,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, vcc_hi, v2 :: v_dual_max_num_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xd4,0xc8,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xd4,0xc8,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, vcc_lo, v2 :: v_dual_max_num_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xd4,0xc8,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xd4,0xc8,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, 0xaf123456, v2 :: v_dual_max_num_f32 v6, null, v3 ; encoding: [0xff,0x04,0xd4,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xd4,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, src_scc, v2 :: v_dual_max_num_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0xd4,0xc8,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xd4,0xc8,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, 0.5, v3 :: v_dual_max_num_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xd4,0xc8,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xd4,0xc8,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, -1, v4 :: v_dual_max_num_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xd4,0xc8,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xd4,0xc8,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v6, null, v5 :: v_dual_max_num_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xd4,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xd4,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, v4, v2 :: v_dual_min_num_f32 v6, v1, v3 ; encoding: [0x04,0x05,0xd6,0xc8,0x01,0x07,0x06,0xff]
+0x04,0x05,0xd6,0xc8,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v1, v2 :: v_dual_min_num_f32 v6, v255, v3 ; encoding: [0x01,0x05,0xd6,0xc8,0xff,0x07,0x06,0xff]
+0x01,0x05,0xd6,0xc8,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v255, v2 :: v_dual_min_num_f32 v6, v2, v3 ; encoding: [0xff,0x05,0xd6,0xc8,0x02,0x07,0x06,0xff]
+0xff,0x05,0xd6,0xc8,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v2, v2 :: v_dual_min_num_f32 v6, v3, v3 ; encoding: [0x02,0x05,0xd6,0xc8,0x03,0x07,0x06,0xff]
+0x02,0x05,0xd6,0xc8,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v3, v2 :: v_dual_min_num_f32 v6, v4, v3 ; encoding: [0x03,0x05,0xd6,0xc8,0x04,0x07,0x06,0xff]
+0x03,0x05,0xd6,0xc8,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, s105, v2 :: v_dual_min_num_f32 v6, s1, v3 ; encoding: [0x69,0x04,0xd6,0xc8,0x01,0x06,0x06,0xff]
+0x69,0x04,0xd6,0xc8,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, s1, v2 :: v_dual_min_num_f32 v6, s105, v3 ; encoding: [0x01,0x04,0xd6,0xc8,0x69,0x06,0x06,0xff]
+0x01,0x04,0xd6,0xc8,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, ttmp15, v2 :: v_dual_min_num_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xd6,0xc8,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xd6,0xc8,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, exec_hi, v2 :: v_dual_min_num_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xd6,0xc8,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xd6,0xc8,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, exec_lo, v2 :: v_dual_min_num_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xd6,0xc8,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xd6,0xc8,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, m0, v2 :: v_dual_min_num_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0xd6,0xc8,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xd6,0xc8,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, vcc_hi, v2 :: v_dual_min_num_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xd6,0xc8,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xd6,0xc8,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, vcc_lo, v2 :: v_dual_min_num_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xd6,0xc8,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xd6,0xc8,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, 0xaf123456, v2 :: v_dual_min_num_f32 v6, null, v3 ; encoding: [0xff,0x04,0xd6,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xd6,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, src_scc, v2 :: v_dual_min_num_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0xd6,0xc8,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xd6,0xc8,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, 0.5, v3 :: v_dual_min_num_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xd6,0xc8,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xd6,0xc8,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, -1, v4 :: v_dual_min_num_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xd6,0xc8,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xd6,0xc8,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v6, null, v5 :: v_dual_min_num_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xd6,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xd6,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, v4, v255 :: v_dual_mov_b32 v6, v1 ; encoding: [0x04,0xff,0xd1,0xc8,0x01,0x01,0x06,0xff]
+0x04,0xff,0xd1,0xc8,0x01,0x01,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v1, v255 :: v_dual_mov_b32 v6, v255 ; encoding: [0x01,0xff,0xd1,0xc8,0xff,0x01,0x06,0xff]
+0x01,0xff,0xd1,0xc8,0xff,0x01,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v255, v255 :: v_dual_mov_b32 v6, v2 ; encoding: [0xff,0xff,0xd1,0xc8,0x02,0x01,0x06,0xff]
+0xff,0xff,0xd1,0xc8,0x02,0x01,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v2, v255 :: v_dual_mov_b32 v6, v3 ; encoding: [0x02,0xff,0xd1,0xc8,0x03,0x01,0x06,0xff]
+0x02,0xff,0xd1,0xc8,0x03,0x01,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v3, v255 :: v_dual_mov_b32 v6, v4 ; encoding: [0x03,0xff,0xd1,0xc8,0x04,0x01,0x06,0xff]
+0x03,0xff,0xd1,0xc8,0x04,0x01,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, s105, v255 :: v_dual_mov_b32 v6, s1 ; encoding: [0x69,0xfe,0xd1,0xc8,0x01,0x00,0x06,0xff]
+0x69,0xfe,0xd1,0xc8,0x01,0x00,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, s1, v255 :: v_dual_mov_b32 v6, s105 ; encoding: [0x01,0xfe,0xd1,0xc8,0x69,0x00,0x06,0xff]
+0x01,0xfe,0xd1,0xc8,0x69,0x00,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, ttmp15, v255 :: v_dual_mov_b32 v6, vcc_lo ; encoding: [0x7b,0xfe,0xd1,0xc8,0x6a,0x00,0x06,0xff]
+0x7b,0xfe,0xd1,0xc8,0x6a,0x00,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, exec_hi, v255 :: v_dual_mov_b32 v6, vcc_hi ; encoding: [0x7f,0xfe,0xd1,0xc8,0x6b,0x00,0x06,0xff]
+0x7f,0xfe,0xd1,0xc8,0x6b,0x00,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, exec_lo, v255 :: v_dual_mov_b32 v6, ttmp15 ; encoding: [0x7e,0xfe,0xd1,0xc8,0x7b,0x00,0x06,0xff]
+0x7e,0xfe,0xd1,0xc8,0x7b,0x00,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, m0, v255 :: v_dual_mov_b32 v6, m0 ; encoding: [0x7d,0xfe,0xd1,0xc8,0x7d,0x00,0x06,0xff]
+0x7d,0xfe,0xd1,0xc8,0x7d,0x00,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, vcc_hi, v255 :: v_dual_mov_b32 v6, exec_lo ; encoding: [0x6b,0xfe,0xd1,0xc8,0x7e,0x00,0x06,0xff]
+0x6b,0xfe,0xd1,0xc8,0x7e,0x00,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, vcc_lo, v255 :: v_dual_mov_b32 v6, exec_hi ; encoding: [0x6a,0xfe,0xd1,0xc8,0x7f,0x00,0x06,0xff]
+0x6a,0xfe,0xd1,0xc8,0x7f,0x00,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, 0xaf123456, v255 :: v_dual_mov_b32 v6, null ; encoding: [0xff,0xfe,0xd1,0xc8,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0xd1,0xc8,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, src_scc, v255 :: v_dual_mov_b32 v6, -1 ; encoding: [0xfd,0xfe,0xd1,0xc8,0xc1,0x00,0x06,0xff]
+0xfd,0xfe,0xd1,0xc8,0xc1,0x00,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, 0.5, v3 :: v_dual_mov_b32 v6, 0.5 ; encoding: [0xf0,0x06,0xd0,0xc8,0xf0,0x00,0x06,0xff]
+0xf0,0x06,0xd0,0xc8,0xf0,0x00,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, -1, v4 :: v_dual_mov_b32 v6, src_scc ; encoding: [0xc1,0x08,0xd0,0xc8,0xfd,0x00,0x06,0xff]
+0xc1,0x08,0xd0,0xc8,0xfd,0x00,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v6, null, v5 :: v_dual_mov_b32 v255, 0xaf123456 ; encoding: [0x7c,0x0a,0xd0,0xc8,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xd0,0xc8,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, v4, v2 :: v_dual_mul_dx9_zero_f32 v6, v1, v3 ; encoding: [0x04,0x05,0xce,0xc8,0x01,0x07,0x06,0xff]
+0x04,0x05,0xce,0xc8,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v1, v2 :: v_dual_mul_dx9_zero_f32 v6, v255, v3 ; encoding: [0x01,0x05,0xce,0xc8,0xff,0x07,0x06,0xff]
+0x01,0x05,0xce,0xc8,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v255, v2 :: v_dual_mul_dx9_zero_f32 v6, v2, v3 ; encoding: [0xff,0x05,0xce,0xc8,0x02,0x07,0x06,0xff]
+0xff,0x05,0xce,0xc8,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v2, v2 :: v_dual_mul_dx9_zero_f32 v6, v3, v3 ; encoding: [0x02,0x05,0xce,0xc8,0x03,0x07,0x06,0xff]
+0x02,0x05,0xce,0xc8,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v3, v2 :: v_dual_mul_dx9_zero_f32 v6, v4, v3 ; encoding: [0x03,0x05,0xce,0xc8,0x04,0x07,0x06,0xff]
+0x03,0x05,0xce,0xc8,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, s105, v2 :: v_dual_mul_dx9_zero_f32 v6, s1, v3 ; encoding: [0x69,0x04,0xce,0xc8,0x01,0x06,0x06,0xff]
+0x69,0x04,0xce,0xc8,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, s1, v2 :: v_dual_mul_dx9_zero_f32 v6, s105, v3 ; encoding: [0x01,0x04,0xce,0xc8,0x69,0x06,0x06,0xff]
+0x01,0x04,0xce,0xc8,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, ttmp15, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xce,0xc8,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xce,0xc8,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, exec_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xce,0xc8,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xce,0xc8,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, exec_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xce,0xc8,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xce,0xc8,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, m0, v2 :: v_dual_mul_dx9_zero_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0xce,0xc8,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xce,0xc8,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, vcc_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xce,0xc8,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xce,0xc8,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, vcc_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xce,0xc8,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xce,0xc8,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, 0xaf123456, v2 :: v_dual_mul_dx9_zero_f32 v6, null, v3 ; encoding: [0xff,0x04,0xce,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xce,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, src_scc, v2 :: v_dual_mul_dx9_zero_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0xce,0xc8,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xce,0xc8,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, 0.5, v3 :: v_dual_mul_dx9_zero_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xce,0xc8,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xce,0xc8,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, -1, v4 :: v_dual_mul_dx9_zero_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xce,0xc8,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xce,0xc8,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v6, null, v5 :: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xce,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xce,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, v4, v2 :: v_dual_mul_f32 v6, v1, v3 ; encoding: [0x04,0x05,0xc6,0xc8,0x01,0x07,0x06,0xff]
+0x04,0x05,0xc6,0xc8,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v1, v2 :: v_dual_mul_f32 v6, v255, v3 ; encoding: [0x01,0x05,0xc6,0xc8,0xff,0x07,0x06,0xff]
+0x01,0x05,0xc6,0xc8,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v255, v2 :: v_dual_mul_f32 v6, v2, v3 ; encoding: [0xff,0x05,0xc6,0xc8,0x02,0x07,0x06,0xff]
+0xff,0x05,0xc6,0xc8,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v2, v2 :: v_dual_mul_f32 v6, v3, v3 ; encoding: [0x02,0x05,0xc6,0xc8,0x03,0x07,0x06,0xff]
+0x02,0x05,0xc6,0xc8,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v3, v2 :: v_dual_mul_f32 v6, v4, v3 ; encoding: [0x03,0x05,0xc6,0xc8,0x04,0x07,0x06,0xff]
+0x03,0x05,0xc6,0xc8,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, s105, v2 :: v_dual_mul_f32 v6, s1, v3 ; encoding: [0x69,0x04,0xc6,0xc8,0x01,0x06,0x06,0xff]
+0x69,0x04,0xc6,0xc8,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, s1, v2 :: v_dual_mul_f32 v6, s105, v3 ; encoding: [0x01,0x04,0xc6,0xc8,0x69,0x06,0x06,0xff]
+0x01,0x04,0xc6,0xc8,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, ttmp15, v2 :: v_dual_mul_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xc6,0xc8,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xc6,0xc8,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, exec_hi, v2 :: v_dual_mul_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xc6,0xc8,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xc6,0xc8,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, exec_lo, v2 :: v_dual_mul_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xc6,0xc8,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xc6,0xc8,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, m0, v2 :: v_dual_mul_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0xc6,0xc8,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xc6,0xc8,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, vcc_hi, v2 :: v_dual_mul_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xc6,0xc8,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xc6,0xc8,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, vcc_lo, v2 :: v_dual_mul_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xc6,0xc8,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xc6,0xc8,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, 0xaf123456, v2 :: v_dual_mul_f32 v6, null, v3 ; encoding: [0xff,0x04,0xc6,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xc6,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, src_scc, v2 :: v_dual_mul_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0xc6,0xc8,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xc6,0xc8,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, 0.5, v3 :: v_dual_mul_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xc6,0xc8,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xc6,0xc8,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, -1, v4 :: v_dual_mul_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xc6,0xc8,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xc6,0xc8,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v6, null, v5 :: v_dual_mul_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xc6,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xc6,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, v4, v2 :: v_dual_sub_f32 v6, v1, v3 ; encoding: [0x04,0x05,0xca,0xc8,0x01,0x07,0x06,0xff]
+0x04,0x05,0xca,0xc8,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v1, v2 :: v_dual_sub_f32 v6, v255, v3 ; encoding: [0x01,0x05,0xca,0xc8,0xff,0x07,0x06,0xff]
+0x01,0x05,0xca,0xc8,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v255, v2 :: v_dual_sub_f32 v6, v2, v3 ; encoding: [0xff,0x05,0xca,0xc8,0x02,0x07,0x06,0xff]
+0xff,0x05,0xca,0xc8,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v2, v2 :: v_dual_sub_f32 v6, v3, v3 ; encoding: [0x02,0x05,0xca,0xc8,0x03,0x07,0x06,0xff]
+0x02,0x05,0xca,0xc8,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v3, v2 :: v_dual_sub_f32 v6, v4, v3 ; encoding: [0x03,0x05,0xca,0xc8,0x04,0x07,0x06,0xff]
+0x03,0x05,0xca,0xc8,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, s105, v2 :: v_dual_sub_f32 v6, s1, v3 ; encoding: [0x69,0x04,0xca,0xc8,0x01,0x06,0x06,0xff]
+0x69,0x04,0xca,0xc8,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, s1, v2 :: v_dual_sub_f32 v6, s105, v3 ; encoding: [0x01,0x04,0xca,0xc8,0x69,0x06,0x06,0xff]
+0x01,0x04,0xca,0xc8,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, ttmp15, v2 :: v_dual_sub_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xca,0xc8,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xca,0xc8,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, exec_hi, v2 :: v_dual_sub_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xca,0xc8,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xca,0xc8,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, exec_lo, v2 :: v_dual_sub_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xca,0xc8,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xca,0xc8,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, m0, v2 :: v_dual_sub_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0xca,0xc8,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xca,0xc8,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, vcc_hi, v2 :: v_dual_sub_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xca,0xc8,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xca,0xc8,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, vcc_lo, v2 :: v_dual_sub_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xca,0xc8,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xca,0xc8,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, 0xaf123456, v2 :: v_dual_sub_f32 v6, null, v3 ; encoding: [0xff,0x04,0xca,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xca,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, src_scc, v2 :: v_dual_sub_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0xca,0xc8,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xca,0xc8,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, 0.5, v3 :: v_dual_sub_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xca,0xc8,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xca,0xc8,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, -1, v4 :: v_dual_sub_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xca,0xc8,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xca,0xc8,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v6, null, v5 :: v_dual_sub_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xca,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xca,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, v4, v2 :: v_dual_subrev_f32 v6, v1, v3 ; encoding: [0x04,0x05,0xcc,0xc8,0x01,0x07,0x06,0xff]
+0x04,0x05,0xcc,0xc8,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v1, v2 :: v_dual_subrev_f32 v6, v255, v3 ; encoding: [0x01,0x05,0xcc,0xc8,0xff,0x07,0x06,0xff]
+0x01,0x05,0xcc,0xc8,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v255, v2 :: v_dual_subrev_f32 v6, v2, v3 ; encoding: [0xff,0x05,0xcc,0xc8,0x02,0x07,0x06,0xff]
+0xff,0x05,0xcc,0xc8,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v2, v2 :: v_dual_subrev_f32 v6, v3, v3 ; encoding: [0x02,0x05,0xcc,0xc8,0x03,0x07,0x06,0xff]
+0x02,0x05,0xcc,0xc8,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, v3, v2 :: v_dual_subrev_f32 v6, v4, v3 ; encoding: [0x03,0x05,0xcc,0xc8,0x04,0x07,0x06,0xff]
+0x03,0x05,0xcc,0xc8,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, s105, v2 :: v_dual_subrev_f32 v6, s1, v3 ; encoding: [0x69,0x04,0xcc,0xc8,0x01,0x06,0x06,0xff]
+0x69,0x04,0xcc,0xc8,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, s1, v2 :: v_dual_subrev_f32 v6, s105, v3 ; encoding: [0x01,0x04,0xcc,0xc8,0x69,0x06,0x06,0xff]
+0x01,0x04,0xcc,0xc8,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, ttmp15, v2 :: v_dual_subrev_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xcc,0xc8,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xcc,0xc8,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, exec_hi, v2 :: v_dual_subrev_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xcc,0xc8,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xcc,0xc8,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, exec_lo, v2 :: v_dual_subrev_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xcc,0xc8,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xcc,0xc8,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, m0, v2 :: v_dual_subrev_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0xcc,0xc8,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xcc,0xc8,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, vcc_hi, v2 :: v_dual_subrev_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xcc,0xc8,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xcc,0xc8,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, vcc_lo, v2 :: v_dual_subrev_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xcc,0xc8,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xcc,0xc8,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, 0xaf123456, v2 :: v_dual_subrev_f32 v6, null, v3 ; encoding: [0xff,0x04,0xcc,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xcc,0xc8,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_mul_f32 v255, src_scc, v2 :: v_dual_subrev_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0xcc,0xc8,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xcc,0xc8,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, 0.5, v3 :: v_dual_subrev_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xcc,0xc8,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xcc,0xc8,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v255, -1, v4 :: v_dual_subrev_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xcc,0xc8,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xcc,0xc8,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_mul_f32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xcc,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xcc,0xc8,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, v4, v2 :: v_dual_add_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x48,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x48,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v1, v2 :: v_dual_add_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x48,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x48,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v255, v2 :: v_dual_add_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x48,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x48,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v2, v2 :: v_dual_add_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x48,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x48,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v3, v2 :: v_dual_add_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x48,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x48,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, s105, v2 :: v_dual_add_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x48,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x48,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, s1, v2 :: v_dual_add_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x48,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x48,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, ttmp15, v2 :: v_dual_add_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x48,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x48,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, exec_hi, v2 :: v_dual_add_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x48,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x48,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, exec_lo, v2 :: v_dual_add_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x48,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x48,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, m0, v2 :: v_dual_add_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x48,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x48,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, vcc_hi, v2 :: v_dual_add_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x48,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x48,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, vcc_lo, v2 :: v_dual_add_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x48,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x48,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, 0xaf123456, v2 :: v_dual_add_f32 v6, null, v3 ; encoding: [0xff,0x04,0x48,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x48,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, src_scc, v2 :: v_dual_add_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x48,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x48,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, 0.5, v3 :: v_dual_add_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x48,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x48,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, -1, v4 :: v_dual_add_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x48,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x48,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v6, null, v5 :: v_dual_add_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x48,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x48,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, v4, v2 :: v_dual_add_nc_u32 v6, v1, v3 ; encoding: [0x04,0x05,0x60,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x60,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v1, v2 :: v_dual_add_nc_u32 v6, v255, v3 ; encoding: [0x01,0x05,0x60,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x60,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v255, v2 :: v_dual_add_nc_u32 v6, v2, v3 ; encoding: [0xff,0x05,0x60,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x60,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v2, v2 :: v_dual_add_nc_u32 v6, v3, v3 ; encoding: [0x02,0x05,0x60,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x60,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v3, v2 :: v_dual_add_nc_u32 v6, v4, v3 ; encoding: [0x03,0x05,0x60,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x60,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, s105, v2 :: v_dual_add_nc_u32 v6, s1, v3 ; encoding: [0x69,0x04,0x60,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x60,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, s1, v2 :: v_dual_add_nc_u32 v6, s105, v3 ; encoding: [0x01,0x04,0x60,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x60,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, ttmp15, v2 :: v_dual_add_nc_u32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x60,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x60,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, exec_hi, v2 :: v_dual_add_nc_u32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x60,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x60,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, exec_lo, v2 :: v_dual_add_nc_u32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x60,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x60,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, m0, v2 :: v_dual_add_nc_u32 v6, m0, v3 ; encoding: [0x7d,0x04,0x60,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x60,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, vcc_hi, v2 :: v_dual_add_nc_u32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x60,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x60,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, vcc_lo, v2 :: v_dual_add_nc_u32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x60,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x60,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, 0xaf123456, v2 :: v_dual_add_nc_u32 v6, null, v3 ; encoding: [0xff,0x04,0x60,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x60,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, src_scc, v2 :: v_dual_add_nc_u32 v6, -1, v3 ; encoding: [0xfd,0x04,0x60,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x60,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, 0.5, v3 :: v_dual_add_nc_u32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x60,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x60,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, -1, v4 :: v_dual_add_nc_u32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x60,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x60,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v6, null, v5 :: v_dual_add_nc_u32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x60,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x60,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, v4, v2 :: v_dual_and_b32 v6, v1, v3 ; encoding: [0x04,0x05,0x64,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x64,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v1, v2 :: v_dual_and_b32 v6, v255, v3 ; encoding: [0x01,0x05,0x64,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x64,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v255, v2 :: v_dual_and_b32 v6, v2, v3 ; encoding: [0xff,0x05,0x64,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x64,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v2, v2 :: v_dual_and_b32 v6, v3, v3 ; encoding: [0x02,0x05,0x64,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x64,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v3, v2 :: v_dual_and_b32 v6, v4, v3 ; encoding: [0x03,0x05,0x64,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x64,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, s105, v2 :: v_dual_and_b32 v6, s1, v3 ; encoding: [0x69,0x04,0x64,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x64,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, s1, v2 :: v_dual_and_b32 v6, s105, v3 ; encoding: [0x01,0x04,0x64,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x64,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, ttmp15, v2 :: v_dual_and_b32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x64,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x64,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, exec_hi, v2 :: v_dual_and_b32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x64,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x64,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, exec_lo, v2 :: v_dual_and_b32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x64,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x64,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, m0, v2 :: v_dual_and_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0x64,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x64,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, vcc_hi, v2 :: v_dual_and_b32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x64,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x64,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, vcc_lo, v2 :: v_dual_and_b32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x64,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x64,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, 0xaf123456, v2 :: v_dual_and_b32 v6, null, v3 ; encoding: [0xff,0x04,0x64,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x64,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, src_scc, v2 :: v_dual_and_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0x64,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x64,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, 0.5, v3 :: v_dual_and_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x64,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x64,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, -1, v4 :: v_dual_and_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x64,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x64,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v6, null, v5 :: v_dual_and_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x64,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x64,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, v4, v2 :: v_dual_cndmask_b32 v6, v1, v3 ; encoding: [0x04,0x05,0x52,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x52,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v1, v2 :: v_dual_cndmask_b32 v6, v255, v3 ; encoding: [0x01,0x05,0x52,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x52,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v255, v2 :: v_dual_cndmask_b32 v6, v2, v3 ; encoding: [0xff,0x05,0x52,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x52,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v2, v2 :: v_dual_cndmask_b32 v6, v3, v3 ; encoding: [0x02,0x05,0x52,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x52,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v3, v2 :: v_dual_cndmask_b32 v6, v4, v3 ; encoding: [0x03,0x05,0x52,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x52,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, s105, v2 :: v_dual_cndmask_b32 v6, s105, v3 ; encoding: [0x69,0x04,0x52,0xc9,0x69,0x06,0x06,0xff]
+0x69,0x04,0x52,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, s1, v2 :: v_dual_cndmask_b32 v6, s1, v3 ; encoding: [0x01,0x04,0x52,0xc9,0x01,0x06,0x06,0xff]
+0x01,0x04,0x52,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, ttmp15, v2 :: v_dual_cndmask_b32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0x52,0xc9,0x7b,0x06,0x06,0xff]
+0x7b,0x04,0x52,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, exec_hi, v2 :: v_dual_cndmask_b32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0x52,0xc9,0x7f,0x06,0x06,0xff]
+0x7f,0x04,0x52,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, exec_lo, v2 :: v_dual_cndmask_b32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0x52,0xc9,0x7e,0x06,0x06,0xff]
+0x7e,0x04,0x52,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, m0, v2 :: v_dual_cndmask_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0x52,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x52,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, vcc_hi, v2 :: v_dual_cndmask_b32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0x52,0xc9,0x6b,0x06,0x06,0xff]
+0x6b,0x04,0x52,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, vcc_lo, v2 :: v_dual_cndmask_b32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0x52,0xc9,0x6a,0x06,0x06,0xff]
+0x6a,0x04,0x52,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, 0xaf123456, v2 :: v_dual_cndmask_b32 v6, null, v3 ; encoding: [0xff,0x04,0x52,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x52,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, src_scc, v2 :: v_dual_cndmask_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0x52,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x52,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, 0.5, v3 :: v_dual_cndmask_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x52,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x52,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, -1, v4 :: v_dual_cndmask_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x52,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x52,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v6, null, v5 :: v_dual_cndmask_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x52,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x52,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, v4, v2 :: v_dual_fmaak_f32 v6, v1, v3, 0xaf123456 ; encoding: [0x04,0x05,0x42,0xc9,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x04,0x05,0x42,0xc9,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, v1, v2 :: v_dual_fmaak_f32 v6, v255, v3, 0xaf123456 ; encoding: [0x01,0x05,0x42,0xc9,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x05,0x42,0xc9,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, v255, v2 :: v_dual_fmaak_f32 v6, v2, v3, 0xaf123456 ; encoding: [0xff,0x05,0x42,0xc9,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x05,0x42,0xc9,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, v2, v2 :: v_dual_fmaak_f32 v6, v3, v3, 0xaf123456 ; encoding: [0x02,0x05,0x42,0xc9,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x02,0x05,0x42,0xc9,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, v3, v2 :: v_dual_fmaak_f32 v6, v4, v3, 0xaf123456 ; encoding: [0x03,0x05,0x42,0xc9,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x03,0x05,0x42,0xc9,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, s105, v2 :: v_dual_fmaak_f32 v6, s105, v3, 0xaf123456 ; encoding: [0x69,0x04,0x42,0xc9,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x69,0x04,0x42,0xc9,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, s1, v2 :: v_dual_fmaak_f32 v6, s1, v3, 0xaf123456 ; encoding: [0x01,0x04,0x42,0xc9,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x04,0x42,0xc9,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, ttmp15, v2 :: v_dual_fmaak_f32 v6, ttmp15, v3, 0xaf123456 ; encoding: [0x7b,0x04,0x42,0xc9,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0x04,0x42,0xc9,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, exec_hi, v2 :: v_dual_fmaak_f32 v6, exec_hi, v3, 0xaf123456 ; encoding: [0x7f,0x04,0x42,0xc9,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0x04,0x42,0xc9,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, exec_lo, v2 :: v_dual_fmaak_f32 v6, exec_lo, v3, 0xaf123456 ; encoding: [0x7e,0x04,0x42,0xc9,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0x04,0x42,0xc9,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, m0, v2 :: v_dual_fmaak_f32 v6, m0, v3, 0xaf123456 ; encoding: [0x7d,0x04,0x42,0xc9,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0x04,0x42,0xc9,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, vcc_hi, v2 :: v_dual_fmaak_f32 v6, vcc_hi, v3, 0xaf123456 ; encoding: [0x6b,0x04,0x42,0xc9,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0x04,0x42,0xc9,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, vcc_lo, v2 :: v_dual_fmaak_f32 v6, vcc_lo, v3, 0xaf123456 ; encoding: [0x6a,0x04,0x42,0xc9,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0x04,0x42,0xc9,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, null, v3, 0xaf123456 ; encoding: [0xff,0x04,0x42,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x42,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, src_scc, v2 :: v_dual_fmaak_f32 v6, -1, v3, 0xaf123456 ; encoding: [0xfd,0x04,0x42,0xc9,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0x04,0x42,0xc9,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, 0.5, v3 :: v_dual_fmaak_f32 v6, 0.5, v2, 0xaf123456 ; encoding: [0xf0,0x06,0x42,0xc9,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0x42,0xc9,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, -1, v4 :: v_dual_fmaak_f32 v6, src_scc, v5, 0xaf123456 ; encoding: [0xc1,0x08,0x42,0xc9,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0x42,0xc9,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v6, null, v5 :: v_dual_fmaak_f32 v255, 0xaf123456, v4, 0xaf123456 ; encoding: [0x7c,0x0a,0x42,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x42,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, v4, v2 :: v_dual_fmac_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x40,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x40,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v1, v2 :: v_dual_fmac_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x40,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x40,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v255, v2 :: v_dual_fmac_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x40,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x40,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v2, v2 :: v_dual_fmac_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x40,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x40,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v3, v2 :: v_dual_fmac_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x40,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x40,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, s105, v2 :: v_dual_fmac_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x40,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x40,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, s1, v2 :: v_dual_fmac_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x40,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x40,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, ttmp15, v2 :: v_dual_fmac_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x40,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x40,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, exec_hi, v2 :: v_dual_fmac_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x40,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x40,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, exec_lo, v2 :: v_dual_fmac_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x40,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x40,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, m0, v2 :: v_dual_fmac_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x40,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x40,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, vcc_hi, v2 :: v_dual_fmac_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x40,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x40,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, vcc_lo, v2 :: v_dual_fmac_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x40,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x40,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, 0xaf123456, v2 :: v_dual_fmac_f32 v6, null, v3 ; encoding: [0xff,0x04,0x40,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x40,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, src_scc, v2 :: v_dual_fmac_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x40,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x40,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, 0.5, v3 :: v_dual_fmac_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x40,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x40,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, -1, v4 :: v_dual_fmac_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x40,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x40,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v6, null, v5 :: v_dual_fmac_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x40,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x40,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, v4, v255 :: v_dual_fmamk_f32 v6, v1, 0xaf123456, v255 ; encoding: [0x04,0xff,0x45,0xc9,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x04,0xff,0x45,0xc9,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, v1, v255 :: v_dual_fmamk_f32 v6, v255, 0xaf123456, v255 ; encoding: [0x01,0xff,0x45,0xc9,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xff,0x45,0xc9,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, v255, v255 :: v_dual_fmamk_f32 v6, v2, 0xaf123456, v255 ; encoding: [0xff,0xff,0x45,0xc9,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xff,0x45,0xc9,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, v2, v255 :: v_dual_fmamk_f32 v6, v3, 0xaf123456, v255 ; encoding: [0x02,0xff,0x45,0xc9,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x02,0xff,0x45,0xc9,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, v3, v255 :: v_dual_fmamk_f32 v6, v4, 0xaf123456, v255 ; encoding: [0x03,0xff,0x45,0xc9,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x03,0xff,0x45,0xc9,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, s105, v255 :: v_dual_fmamk_f32 v6, s105, 0xaf123456, v255 ; encoding: [0x69,0xfe,0x45,0xc9,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x69,0xfe,0x45,0xc9,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, s1, v255 :: v_dual_fmamk_f32 v6, s1, 0xaf123456, v255 ; encoding: [0x01,0xfe,0x45,0xc9,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xfe,0x45,0xc9,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, ttmp15, v255 :: v_dual_fmamk_f32 v6, ttmp15, 0xaf123456, v255 ; encoding: [0x7b,0xfe,0x45,0xc9,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0xfe,0x45,0xc9,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, exec_hi, v255 :: v_dual_fmamk_f32 v6, exec_hi, 0xaf123456, v255 ; encoding: [0x7f,0xfe,0x45,0xc9,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0xfe,0x45,0xc9,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, exec_lo, v255 :: v_dual_fmamk_f32 v6, exec_lo, 0xaf123456, v255 ; encoding: [0x7e,0xfe,0x45,0xc9,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0xfe,0x45,0xc9,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, m0, v255 :: v_dual_fmamk_f32 v6, m0, 0xaf123456, v255 ; encoding: [0x7d,0xfe,0x45,0xc9,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0xfe,0x45,0xc9,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, vcc_hi, v255 :: v_dual_fmamk_f32 v6, vcc_hi, 0xaf123456, v255 ; encoding: [0x6b,0xfe,0x45,0xc9,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0xfe,0x45,0xc9,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, vcc_lo, v255 :: v_dual_fmamk_f32 v6, vcc_lo, 0xaf123456, v255 ; encoding: [0x6a,0xfe,0x45,0xc9,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0xfe,0x45,0xc9,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, null, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x45,0xc9,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x45,0xc9,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, src_scc, v255 :: v_dual_fmamk_f32 v6, -1, 0xaf123456, v255 ; encoding: [0xfd,0xfe,0x45,0xc9,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0xfe,0x45,0xc9,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, 0.5, v3 :: v_dual_fmamk_f32 v6, 0.5, 0xaf123456, v255 ; encoding: [0xf0,0x06,0x44,0xc9,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0x44,0xc9,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, -1, v4 :: v_dual_fmamk_f32 v6, src_scc, 0xaf123456, v255 ; encoding: [0xc1,0x08,0x44,0xc9,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0x44,0xc9,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v6, null, v5 :: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x44,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x44,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, v4, v2 :: v_dual_lshlrev_b32 v6, v1, v3 ; encoding: [0x04,0x05,0x62,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x62,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v1, v2 :: v_dual_lshlrev_b32 v6, v255, v3 ; encoding: [0x01,0x05,0x62,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x62,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v255, v2 :: v_dual_lshlrev_b32 v6, v2, v3 ; encoding: [0xff,0x05,0x62,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x62,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v2, v2 :: v_dual_lshlrev_b32 v6, v3, v3 ; encoding: [0x02,0x05,0x62,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x62,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v3, v2 :: v_dual_lshlrev_b32 v6, v4, v3 ; encoding: [0x03,0x05,0x62,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x62,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, s105, v2 :: v_dual_lshlrev_b32 v6, s1, v3 ; encoding: [0x69,0x04,0x62,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x62,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, s1, v2 :: v_dual_lshlrev_b32 v6, s105, v3 ; encoding: [0x01,0x04,0x62,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x62,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, ttmp15, v2 :: v_dual_lshlrev_b32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x62,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x62,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, exec_hi, v2 :: v_dual_lshlrev_b32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x62,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x62,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, exec_lo, v2 :: v_dual_lshlrev_b32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x62,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x62,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, m0, v2 :: v_dual_lshlrev_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0x62,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x62,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, vcc_hi, v2 :: v_dual_lshlrev_b32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x62,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x62,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, vcc_lo, v2 :: v_dual_lshlrev_b32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x62,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x62,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, 0xaf123456, v2 :: v_dual_lshlrev_b32 v6, null, v3 ; encoding: [0xff,0x04,0x62,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x62,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, src_scc, v2 :: v_dual_lshlrev_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0x62,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x62,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, 0.5, v3 :: v_dual_lshlrev_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x62,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x62,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, -1, v4 :: v_dual_lshlrev_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x62,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x62,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v6, null, v5 :: v_dual_lshlrev_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x62,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x62,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, v4, v2 :: v_dual_max_num_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x54,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x54,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v1, v2 :: v_dual_max_num_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x54,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x54,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v255, v2 :: v_dual_max_num_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x54,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x54,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v2, v2 :: v_dual_max_num_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x54,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x54,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v3, v2 :: v_dual_max_num_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x54,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x54,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, s105, v2 :: v_dual_max_num_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x54,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x54,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, s1, v2 :: v_dual_max_num_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x54,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x54,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, ttmp15, v2 :: v_dual_max_num_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x54,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x54,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, exec_hi, v2 :: v_dual_max_num_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x54,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x54,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, exec_lo, v2 :: v_dual_max_num_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x54,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x54,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, m0, v2 :: v_dual_max_num_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x54,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x54,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, vcc_hi, v2 :: v_dual_max_num_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x54,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x54,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, vcc_lo, v2 :: v_dual_max_num_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x54,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x54,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, 0xaf123456, v2 :: v_dual_max_num_f32 v6, null, v3 ; encoding: [0xff,0x04,0x54,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x54,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, src_scc, v2 :: v_dual_max_num_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x54,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x54,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, 0.5, v3 :: v_dual_max_num_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x54,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x54,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, -1, v4 :: v_dual_max_num_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x54,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x54,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v6, null, v5 :: v_dual_max_num_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x54,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x54,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, v4, v2 :: v_dual_min_num_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x56,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x56,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v1, v2 :: v_dual_min_num_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x56,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x56,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v255, v2 :: v_dual_min_num_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x56,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x56,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v2, v2 :: v_dual_min_num_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x56,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x56,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v3, v2 :: v_dual_min_num_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x56,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x56,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, s105, v2 :: v_dual_min_num_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x56,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x56,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, s1, v2 :: v_dual_min_num_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x56,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x56,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, ttmp15, v2 :: v_dual_min_num_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x56,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x56,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, exec_hi, v2 :: v_dual_min_num_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x56,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x56,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, exec_lo, v2 :: v_dual_min_num_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x56,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x56,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, m0, v2 :: v_dual_min_num_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x56,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x56,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, vcc_hi, v2 :: v_dual_min_num_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x56,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x56,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, vcc_lo, v2 :: v_dual_min_num_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x56,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x56,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, 0xaf123456, v2 :: v_dual_min_num_f32 v6, null, v3 ; encoding: [0xff,0x04,0x56,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x56,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, src_scc, v2 :: v_dual_min_num_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x56,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x56,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, 0.5, v3 :: v_dual_min_num_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x56,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x56,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, -1, v4 :: v_dual_min_num_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x56,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x56,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v6, null, v5 :: v_dual_min_num_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x56,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x56,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, v4, v255 :: v_dual_mov_b32 v6, v1 ; encoding: [0x04,0xff,0x51,0xc9,0x01,0x01,0x06,0xff]
+0x04,0xff,0x51,0xc9,0x01,0x01,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v1, v255 :: v_dual_mov_b32 v6, v255 ; encoding: [0x01,0xff,0x51,0xc9,0xff,0x01,0x06,0xff]
+0x01,0xff,0x51,0xc9,0xff,0x01,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v255, v255 :: v_dual_mov_b32 v6, v2 ; encoding: [0xff,0xff,0x51,0xc9,0x02,0x01,0x06,0xff]
+0xff,0xff,0x51,0xc9,0x02,0x01,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v2, v255 :: v_dual_mov_b32 v6, v3 ; encoding: [0x02,0xff,0x51,0xc9,0x03,0x01,0x06,0xff]
+0x02,0xff,0x51,0xc9,0x03,0x01,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v3, v255 :: v_dual_mov_b32 v6, v4 ; encoding: [0x03,0xff,0x51,0xc9,0x04,0x01,0x06,0xff]
+0x03,0xff,0x51,0xc9,0x04,0x01,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, s105, v255 :: v_dual_mov_b32 v6, s1 ; encoding: [0x69,0xfe,0x51,0xc9,0x01,0x00,0x06,0xff]
+0x69,0xfe,0x51,0xc9,0x01,0x00,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, s1, v255 :: v_dual_mov_b32 v6, s105 ; encoding: [0x01,0xfe,0x51,0xc9,0x69,0x00,0x06,0xff]
+0x01,0xfe,0x51,0xc9,0x69,0x00,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, ttmp15, v255 :: v_dual_mov_b32 v6, vcc_lo ; encoding: [0x7b,0xfe,0x51,0xc9,0x6a,0x00,0x06,0xff]
+0x7b,0xfe,0x51,0xc9,0x6a,0x00,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, exec_hi, v255 :: v_dual_mov_b32 v6, vcc_hi ; encoding: [0x7f,0xfe,0x51,0xc9,0x6b,0x00,0x06,0xff]
+0x7f,0xfe,0x51,0xc9,0x6b,0x00,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, exec_lo, v255 :: v_dual_mov_b32 v6, ttmp15 ; encoding: [0x7e,0xfe,0x51,0xc9,0x7b,0x00,0x06,0xff]
+0x7e,0xfe,0x51,0xc9,0x7b,0x00,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, m0, v255 :: v_dual_mov_b32 v6, m0 ; encoding: [0x7d,0xfe,0x51,0xc9,0x7d,0x00,0x06,0xff]
+0x7d,0xfe,0x51,0xc9,0x7d,0x00,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, vcc_hi, v255 :: v_dual_mov_b32 v6, exec_lo ; encoding: [0x6b,0xfe,0x51,0xc9,0x7e,0x00,0x06,0xff]
+0x6b,0xfe,0x51,0xc9,0x7e,0x00,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, vcc_lo, v255 :: v_dual_mov_b32 v6, exec_hi ; encoding: [0x6a,0xfe,0x51,0xc9,0x7f,0x00,0x06,0xff]
+0x6a,0xfe,0x51,0xc9,0x7f,0x00,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, 0xaf123456, v255 :: v_dual_mov_b32 v6, null ; encoding: [0xff,0xfe,0x51,0xc9,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x51,0xc9,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, src_scc, v255 :: v_dual_mov_b32 v6, -1 ; encoding: [0xfd,0xfe,0x51,0xc9,0xc1,0x00,0x06,0xff]
+0xfd,0xfe,0x51,0xc9,0xc1,0x00,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, 0.5, v3 :: v_dual_mov_b32 v6, 0.5 ; encoding: [0xf0,0x06,0x50,0xc9,0xf0,0x00,0x06,0xff]
+0xf0,0x06,0x50,0xc9,0xf0,0x00,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, -1, v4 :: v_dual_mov_b32 v6, src_scc ; encoding: [0xc1,0x08,0x50,0xc9,0xfd,0x00,0x06,0xff]
+0xc1,0x08,0x50,0xc9,0xfd,0x00,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v6, null, v5 :: v_dual_mov_b32 v255, 0xaf123456 ; encoding: [0x7c,0x0a,0x50,0xc9,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x50,0xc9,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, v4, v2 :: v_dual_mul_dx9_zero_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x4e,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x4e,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v1, v2 :: v_dual_mul_dx9_zero_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x4e,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x4e,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v255, v2 :: v_dual_mul_dx9_zero_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x4e,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x4e,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v2, v2 :: v_dual_mul_dx9_zero_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x4e,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x4e,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v3, v2 :: v_dual_mul_dx9_zero_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x4e,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x4e,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, s105, v2 :: v_dual_mul_dx9_zero_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x4e,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x4e,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, s1, v2 :: v_dual_mul_dx9_zero_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x4e,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x4e,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, ttmp15, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x4e,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x4e,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, exec_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x4e,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x4e,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, exec_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x4e,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x4e,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, m0, v2 :: v_dual_mul_dx9_zero_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x4e,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x4e,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, vcc_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x4e,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x4e,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, vcc_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x4e,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x4e,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, 0xaf123456, v2 :: v_dual_mul_dx9_zero_f32 v6, null, v3 ; encoding: [0xff,0x04,0x4e,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x4e,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, src_scc, v2 :: v_dual_mul_dx9_zero_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x4e,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x4e,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, 0.5, v3 :: v_dual_mul_dx9_zero_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x4e,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x4e,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, -1, v4 :: v_dual_mul_dx9_zero_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x4e,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x4e,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v6, null, v5 :: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x4e,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x4e,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, v4, v2 :: v_dual_mul_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x46,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x46,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v1, v2 :: v_dual_mul_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x46,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x46,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v255, v2 :: v_dual_mul_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x46,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x46,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v2, v2 :: v_dual_mul_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x46,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x46,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v3, v2 :: v_dual_mul_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x46,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x46,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, s105, v2 :: v_dual_mul_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x46,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x46,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, s1, v2 :: v_dual_mul_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x46,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x46,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, ttmp15, v2 :: v_dual_mul_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x46,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x46,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, exec_hi, v2 :: v_dual_mul_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x46,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x46,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, exec_lo, v2 :: v_dual_mul_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x46,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x46,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, m0, v2 :: v_dual_mul_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x46,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x46,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, vcc_hi, v2 :: v_dual_mul_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x46,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x46,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, vcc_lo, v2 :: v_dual_mul_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x46,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x46,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, 0xaf123456, v2 :: v_dual_mul_f32 v6, null, v3 ; encoding: [0xff,0x04,0x46,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x46,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, src_scc, v2 :: v_dual_mul_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x46,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x46,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, 0.5, v3 :: v_dual_mul_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x46,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x46,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, -1, v4 :: v_dual_mul_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x46,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x46,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v6, null, v5 :: v_dual_mul_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x46,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x46,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, v4, v2 :: v_dual_sub_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x4a,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x4a,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v1, v2 :: v_dual_sub_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x4a,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x4a,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v255, v2 :: v_dual_sub_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x4a,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x4a,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v2, v2 :: v_dual_sub_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x4a,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x4a,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v3, v2 :: v_dual_sub_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x4a,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x4a,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, s105, v2 :: v_dual_sub_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x4a,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x4a,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, s1, v2 :: v_dual_sub_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x4a,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x4a,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, ttmp15, v2 :: v_dual_sub_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x4a,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x4a,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, exec_hi, v2 :: v_dual_sub_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x4a,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x4a,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, exec_lo, v2 :: v_dual_sub_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x4a,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x4a,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, m0, v2 :: v_dual_sub_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x4a,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x4a,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, vcc_hi, v2 :: v_dual_sub_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x4a,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x4a,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, vcc_lo, v2 :: v_dual_sub_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x4a,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x4a,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, 0xaf123456, v2 :: v_dual_sub_f32 v6, null, v3 ; encoding: [0xff,0x04,0x4a,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x4a,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, src_scc, v2 :: v_dual_sub_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x4a,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x4a,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, 0.5, v3 :: v_dual_sub_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x4a,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x4a,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, -1, v4 :: v_dual_sub_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x4a,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x4a,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v6, null, v5 :: v_dual_sub_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x4a,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x4a,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, v4, v2 :: v_dual_subrev_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x4c,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x4c,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v1, v2 :: v_dual_subrev_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x4c,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x4c,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v255, v2 :: v_dual_subrev_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x4c,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x4c,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v2, v2 :: v_dual_subrev_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x4c,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x4c,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, v3, v2 :: v_dual_subrev_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x4c,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x4c,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, s105, v2 :: v_dual_subrev_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x4c,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x4c,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, s1, v2 :: v_dual_subrev_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x4c,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x4c,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, ttmp15, v2 :: v_dual_subrev_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x4c,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x4c,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, exec_hi, v2 :: v_dual_subrev_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x4c,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x4c,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, exec_lo, v2 :: v_dual_subrev_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x4c,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x4c,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, m0, v2 :: v_dual_subrev_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x4c,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x4c,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, vcc_hi, v2 :: v_dual_subrev_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x4c,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x4c,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, vcc_lo, v2 :: v_dual_subrev_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x4c,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x4c,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, 0xaf123456, v2 :: v_dual_subrev_f32 v6, null, v3 ; encoding: [0xff,0x04,0x4c,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x4c,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_sub_f32 v255, src_scc, v2 :: v_dual_subrev_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x4c,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x4c,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, 0.5, v3 :: v_dual_subrev_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x4c,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x4c,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v255, -1, v4 :: v_dual_subrev_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x4c,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x4c,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_sub_f32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x4c,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x4c,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, v4, v2 :: v_dual_add_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x88,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x88,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v1, v2 :: v_dual_add_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x88,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x88,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v255, v2 :: v_dual_add_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x88,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x88,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v2, v2 :: v_dual_add_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x88,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x88,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v3, v2 :: v_dual_add_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x88,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x88,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, s105, v2 :: v_dual_add_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x88,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x88,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, s1, v2 :: v_dual_add_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x88,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x88,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, ttmp15, v2 :: v_dual_add_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x88,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x88,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, exec_hi, v2 :: v_dual_add_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x88,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x88,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, exec_lo, v2 :: v_dual_add_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x88,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x88,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, m0, v2 :: v_dual_add_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x88,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x88,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, vcc_hi, v2 :: v_dual_add_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x88,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x88,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, vcc_lo, v2 :: v_dual_add_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x88,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x88,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, 0xaf123456, v2 :: v_dual_add_f32 v6, null, v3 ; encoding: [0xff,0x04,0x88,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x88,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, src_scc, v2 :: v_dual_add_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x88,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x88,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_add_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x88,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x88,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, -1, v4 :: v_dual_add_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x88,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x88,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v6, null, v5 :: v_dual_add_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x88,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x88,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, v4, v2 :: v_dual_add_nc_u32 v6, v1, v3 ; encoding: [0x04,0x05,0xa0,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0xa0,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v1, v2 :: v_dual_add_nc_u32 v6, v255, v3 ; encoding: [0x01,0x05,0xa0,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0xa0,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v255, v2 :: v_dual_add_nc_u32 v6, v2, v3 ; encoding: [0xff,0x05,0xa0,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0xa0,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v2, v2 :: v_dual_add_nc_u32 v6, v3, v3 ; encoding: [0x02,0x05,0xa0,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0xa0,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v3, v2 :: v_dual_add_nc_u32 v6, v4, v3 ; encoding: [0x03,0x05,0xa0,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0xa0,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, s105, v2 :: v_dual_add_nc_u32 v6, s1, v3 ; encoding: [0x69,0x04,0xa0,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0xa0,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, s1, v2 :: v_dual_add_nc_u32 v6, s105, v3 ; encoding: [0x01,0x04,0xa0,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0xa0,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, ttmp15, v2 :: v_dual_add_nc_u32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xa0,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xa0,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, exec_hi, v2 :: v_dual_add_nc_u32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xa0,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xa0,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, exec_lo, v2 :: v_dual_add_nc_u32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xa0,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xa0,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, m0, v2 :: v_dual_add_nc_u32 v6, m0, v3 ; encoding: [0x7d,0x04,0xa0,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xa0,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, vcc_hi, v2 :: v_dual_add_nc_u32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xa0,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xa0,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, vcc_lo, v2 :: v_dual_add_nc_u32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xa0,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xa0,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, 0xaf123456, v2 :: v_dual_add_nc_u32 v6, null, v3 ; encoding: [0xff,0x04,0xa0,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xa0,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, src_scc, v2 :: v_dual_add_nc_u32 v6, -1, v3 ; encoding: [0xfd,0x04,0xa0,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xa0,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_add_nc_u32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xa0,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xa0,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, -1, v4 :: v_dual_add_nc_u32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xa0,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xa0,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v6, null, v5 :: v_dual_add_nc_u32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xa0,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xa0,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, v4, v2 :: v_dual_and_b32 v6, v1, v3 ; encoding: [0x04,0x05,0xa4,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0xa4,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v1, v2 :: v_dual_and_b32 v6, v255, v3 ; encoding: [0x01,0x05,0xa4,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0xa4,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v255, v2 :: v_dual_and_b32 v6, v2, v3 ; encoding: [0xff,0x05,0xa4,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0xa4,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v2, v2 :: v_dual_and_b32 v6, v3, v3 ; encoding: [0x02,0x05,0xa4,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0xa4,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v3, v2 :: v_dual_and_b32 v6, v4, v3 ; encoding: [0x03,0x05,0xa4,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0xa4,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, s105, v2 :: v_dual_and_b32 v6, s1, v3 ; encoding: [0x69,0x04,0xa4,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0xa4,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, s1, v2 :: v_dual_and_b32 v6, s105, v3 ; encoding: [0x01,0x04,0xa4,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0xa4,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, ttmp15, v2 :: v_dual_and_b32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xa4,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xa4,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, exec_hi, v2 :: v_dual_and_b32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xa4,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xa4,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, exec_lo, v2 :: v_dual_and_b32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xa4,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xa4,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, m0, v2 :: v_dual_and_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0xa4,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xa4,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, vcc_hi, v2 :: v_dual_and_b32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xa4,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xa4,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, vcc_lo, v2 :: v_dual_and_b32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xa4,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xa4,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, 0xaf123456, v2 :: v_dual_and_b32 v6, null, v3 ; encoding: [0xff,0x04,0xa4,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xa4,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, src_scc, v2 :: v_dual_and_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0xa4,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xa4,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_and_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xa4,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xa4,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, -1, v4 :: v_dual_and_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xa4,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xa4,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v6, null, v5 :: v_dual_and_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xa4,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xa4,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, v4, v2 :: v_dual_cndmask_b32 v6, v1, v3 ; encoding: [0x04,0x05,0x92,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x92,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v1, v2 :: v_dual_cndmask_b32 v6, v255, v3 ; encoding: [0x01,0x05,0x92,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x92,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v255, v2 :: v_dual_cndmask_b32 v6, v2, v3 ; encoding: [0xff,0x05,0x92,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x92,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v2, v2 :: v_dual_cndmask_b32 v6, v3, v3 ; encoding: [0x02,0x05,0x92,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x92,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v3, v2 :: v_dual_cndmask_b32 v6, v4, v3 ; encoding: [0x03,0x05,0x92,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x92,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, s105, v2 :: v_dual_cndmask_b32 v6, s105, v3 ; encoding: [0x69,0x04,0x92,0xc9,0x69,0x06,0x06,0xff]
+0x69,0x04,0x92,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, s1, v2 :: v_dual_cndmask_b32 v6, s1, v3 ; encoding: [0x01,0x04,0x92,0xc9,0x01,0x06,0x06,0xff]
+0x01,0x04,0x92,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, ttmp15, v2 :: v_dual_cndmask_b32 v6, ttmp15, v3 ; encoding: [0x7b,0x04,0x92,0xc9,0x7b,0x06,0x06,0xff]
+0x7b,0x04,0x92,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, exec_hi, v2 :: v_dual_cndmask_b32 v6, exec_hi, v3 ; encoding: [0x7f,0x04,0x92,0xc9,0x7f,0x06,0x06,0xff]
+0x7f,0x04,0x92,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, exec_lo, v2 :: v_dual_cndmask_b32 v6, exec_lo, v3 ; encoding: [0x7e,0x04,0x92,0xc9,0x7e,0x06,0x06,0xff]
+0x7e,0x04,0x92,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, m0, v2 :: v_dual_cndmask_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0x92,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x92,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, vcc_hi, v2 :: v_dual_cndmask_b32 v6, vcc_hi, v3 ; encoding: [0x6b,0x04,0x92,0xc9,0x6b,0x06,0x06,0xff]
+0x6b,0x04,0x92,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, vcc_lo, v2 :: v_dual_cndmask_b32 v6, vcc_lo, v3 ; encoding: [0x6a,0x04,0x92,0xc9,0x6a,0x06,0x06,0xff]
+0x6a,0x04,0x92,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, 0xaf123456, v2 :: v_dual_cndmask_b32 v6, null, v3 ; encoding: [0xff,0x04,0x92,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x92,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, src_scc, v2 :: v_dual_cndmask_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0x92,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x92,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_cndmask_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x92,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x92,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, -1, v4 :: v_dual_cndmask_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x92,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x92,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v6, null, v5 :: v_dual_cndmask_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x92,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x92,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, v4, v2 :: v_dual_fmaak_f32 v6, v1, v3, 0xaf123456 ; encoding: [0x04,0x05,0x82,0xc9,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x04,0x05,0x82,0xc9,0x01,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, v1, v2 :: v_dual_fmaak_f32 v6, v255, v3, 0xaf123456 ; encoding: [0x01,0x05,0x82,0xc9,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x05,0x82,0xc9,0xff,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, v255, v2 :: v_dual_fmaak_f32 v6, v2, v3, 0xaf123456 ; encoding: [0xff,0x05,0x82,0xc9,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x05,0x82,0xc9,0x02,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, v2, v2 :: v_dual_fmaak_f32 v6, v3, v3, 0xaf123456 ; encoding: [0x02,0x05,0x82,0xc9,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x02,0x05,0x82,0xc9,0x03,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, v3, v2 :: v_dual_fmaak_f32 v6, v4, v3, 0xaf123456 ; encoding: [0x03,0x05,0x82,0xc9,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x03,0x05,0x82,0xc9,0x04,0x07,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, s105, v2 :: v_dual_fmaak_f32 v6, s105, v3, 0xaf123456 ; encoding: [0x69,0x04,0x82,0xc9,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x69,0x04,0x82,0xc9,0x69,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, s1, v2 :: v_dual_fmaak_f32 v6, s1, v3, 0xaf123456 ; encoding: [0x01,0x04,0x82,0xc9,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x01,0x04,0x82,0xc9,0x01,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, ttmp15, v2 :: v_dual_fmaak_f32 v6, ttmp15, v3, 0xaf123456 ; encoding: [0x7b,0x04,0x82,0xc9,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0x04,0x82,0xc9,0x7b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, exec_hi, v2 :: v_dual_fmaak_f32 v6, exec_hi, v3, 0xaf123456 ; encoding: [0x7f,0x04,0x82,0xc9,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0x04,0x82,0xc9,0x7f,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, exec_lo, v2 :: v_dual_fmaak_f32 v6, exec_lo, v3, 0xaf123456 ; encoding: [0x7e,0x04,0x82,0xc9,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0x04,0x82,0xc9,0x7e,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, m0, v2 :: v_dual_fmaak_f32 v6, m0, v3, 0xaf123456 ; encoding: [0x7d,0x04,0x82,0xc9,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0x04,0x82,0xc9,0x7d,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, vcc_hi, v2 :: v_dual_fmaak_f32 v6, vcc_hi, v3, 0xaf123456 ; encoding: [0x6b,0x04,0x82,0xc9,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0x04,0x82,0xc9,0x6b,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, vcc_lo, v2 :: v_dual_fmaak_f32 v6, vcc_lo, v3, 0xaf123456 ; encoding: [0x6a,0x04,0x82,0xc9,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0x04,0x82,0xc9,0x6a,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, null, v3, 0xaf123456 ; encoding: [0xff,0x04,0x82,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x82,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, src_scc, v2 :: v_dual_fmaak_f32 v6, -1, v3, 0xaf123456 ; encoding: [0xfd,0x04,0x82,0xc9,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0x04,0x82,0xc9,0xc1,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_fmaak_f32 v6, 0.5, v2, 0xaf123456 ; encoding: [0xf0,0x06,0x82,0xc9,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0x82,0xc9,0xf0,0x04,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, -1, v4 :: v_dual_fmaak_f32 v6, src_scc, v5, 0xaf123456 ; encoding: [0xc1,0x08,0x82,0xc9,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0x82,0xc9,0xfd,0x0a,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v6, null, v5 :: v_dual_fmaak_f32 v255, 0xaf123456, v4, 0xaf123456 ; encoding: [0x7c,0x0a,0x82,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x82,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, v4, v2 :: v_dual_fmac_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x80,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x80,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v1, v2 :: v_dual_fmac_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x80,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x80,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v255, v2 :: v_dual_fmac_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x80,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x80,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v2, v2 :: v_dual_fmac_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x80,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x80,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v3, v2 :: v_dual_fmac_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x80,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x80,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, s105, v2 :: v_dual_fmac_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x80,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x80,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, s1, v2 :: v_dual_fmac_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x80,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x80,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, ttmp15, v2 :: v_dual_fmac_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x80,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x80,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, exec_hi, v2 :: v_dual_fmac_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x80,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x80,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, exec_lo, v2 :: v_dual_fmac_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x80,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x80,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, m0, v2 :: v_dual_fmac_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x80,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x80,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, vcc_hi, v2 :: v_dual_fmac_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x80,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x80,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, vcc_lo, v2 :: v_dual_fmac_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x80,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x80,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, 0xaf123456, v2 :: v_dual_fmac_f32 v6, null, v3 ; encoding: [0xff,0x04,0x80,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x80,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, src_scc, v2 :: v_dual_fmac_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x80,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x80,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_fmac_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x80,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x80,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, -1, v4 :: v_dual_fmac_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x80,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x80,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v6, null, v5 :: v_dual_fmac_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x80,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x80,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, v4, v255 :: v_dual_fmamk_f32 v6, v1, 0xaf123456, v255 ; encoding: [0x04,0xff,0x85,0xc9,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x04,0xff,0x85,0xc9,0x01,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, v1, v255 :: v_dual_fmamk_f32 v6, v255, 0xaf123456, v255 ; encoding: [0x01,0xff,0x85,0xc9,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xff,0x85,0xc9,0xff,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, v255, v255 :: v_dual_fmamk_f32 v6, v2, 0xaf123456, v255 ; encoding: [0xff,0xff,0x85,0xc9,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xff,0x85,0xc9,0x02,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, v2, v255 :: v_dual_fmamk_f32 v6, v3, 0xaf123456, v255 ; encoding: [0x02,0xff,0x85,0xc9,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x02,0xff,0x85,0xc9,0x03,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, v3, v255 :: v_dual_fmamk_f32 v6, v4, 0xaf123456, v255 ; encoding: [0x03,0xff,0x85,0xc9,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x03,0xff,0x85,0xc9,0x04,0xff,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, s105, v255 :: v_dual_fmamk_f32 v6, s105, 0xaf123456, v255 ; encoding: [0x69,0xfe,0x85,0xc9,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x69,0xfe,0x85,0xc9,0x69,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, s1, v255 :: v_dual_fmamk_f32 v6, s1, 0xaf123456, v255 ; encoding: [0x01,0xfe,0x85,0xc9,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x01,0xfe,0x85,0xc9,0x01,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, ttmp15, v255 :: v_dual_fmamk_f32 v6, ttmp15, 0xaf123456, v255 ; encoding: [0x7b,0xfe,0x85,0xc9,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7b,0xfe,0x85,0xc9,0x7b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, exec_hi, v255 :: v_dual_fmamk_f32 v6, exec_hi, 0xaf123456, v255 ; encoding: [0x7f,0xfe,0x85,0xc9,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7f,0xfe,0x85,0xc9,0x7f,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, exec_lo, v255 :: v_dual_fmamk_f32 v6, exec_lo, 0xaf123456, v255 ; encoding: [0x7e,0xfe,0x85,0xc9,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7e,0xfe,0x85,0xc9,0x7e,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, m0, v255 :: v_dual_fmamk_f32 v6, m0, 0xaf123456, v255 ; encoding: [0x7d,0xfe,0x85,0xc9,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x7d,0xfe,0x85,0xc9,0x7d,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, vcc_hi, v255 :: v_dual_fmamk_f32 v6, vcc_hi, 0xaf123456, v255 ; encoding: [0x6b,0xfe,0x85,0xc9,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6b,0xfe,0x85,0xc9,0x6b,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, vcc_lo, v255 :: v_dual_fmamk_f32 v6, vcc_lo, 0xaf123456, v255 ; encoding: [0x6a,0xfe,0x85,0xc9,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0x6a,0xfe,0x85,0xc9,0x6a,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, 0xaf123456, v255 :: v_dual_fmamk_f32 v6, null, 0xaf123456, v255 ; encoding: [0xff,0xfe,0x85,0xc9,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x85,0xc9,0x7c,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, src_scc, v255 :: v_dual_fmamk_f32 v6, -1, 0xaf123456, v255 ; encoding: [0xfd,0xfe,0x85,0xc9,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xfd,0xfe,0x85,0xc9,0xc1,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_fmamk_f32 v6, 0.5, 0xaf123456, v255 ; encoding: [0xf0,0x06,0x84,0xc9,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xf0,0x06,0x84,0xc9,0xf0,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, -1, v4 :: v_dual_fmamk_f32 v6, src_scc, 0xaf123456, v255 ; encoding: [0xc1,0x08,0x84,0xc9,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf]
+0xc1,0x08,0x84,0xc9,0xfd,0xfe,0x07,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v6, null, v5 :: v_dual_fmamk_f32 v255, 0xaf123456, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x84,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x84,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, v4, v2 :: v_dual_lshlrev_b32 v6, v1, v3 ; encoding: [0x04,0x05,0xa2,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0xa2,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v1, v2 :: v_dual_lshlrev_b32 v6, v255, v3 ; encoding: [0x01,0x05,0xa2,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0xa2,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v255, v2 :: v_dual_lshlrev_b32 v6, v2, v3 ; encoding: [0xff,0x05,0xa2,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0xa2,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v2, v2 :: v_dual_lshlrev_b32 v6, v3, v3 ; encoding: [0x02,0x05,0xa2,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0xa2,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v3, v2 :: v_dual_lshlrev_b32 v6, v4, v3 ; encoding: [0x03,0x05,0xa2,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0xa2,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, s105, v2 :: v_dual_lshlrev_b32 v6, s1, v3 ; encoding: [0x69,0x04,0xa2,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0xa2,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, s1, v2 :: v_dual_lshlrev_b32 v6, s105, v3 ; encoding: [0x01,0x04,0xa2,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0xa2,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, ttmp15, v2 :: v_dual_lshlrev_b32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0xa2,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0xa2,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, exec_hi, v2 :: v_dual_lshlrev_b32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0xa2,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0xa2,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, exec_lo, v2 :: v_dual_lshlrev_b32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0xa2,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0xa2,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, m0, v2 :: v_dual_lshlrev_b32 v6, m0, v3 ; encoding: [0x7d,0x04,0xa2,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0xa2,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, vcc_hi, v2 :: v_dual_lshlrev_b32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0xa2,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0xa2,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, vcc_lo, v2 :: v_dual_lshlrev_b32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0xa2,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0xa2,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, 0xaf123456, v2 :: v_dual_lshlrev_b32 v6, null, v3 ; encoding: [0xff,0x04,0xa2,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0xa2,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, src_scc, v2 :: v_dual_lshlrev_b32 v6, -1, v3 ; encoding: [0xfd,0x04,0xa2,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0xa2,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_lshlrev_b32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0xa2,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0xa2,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, -1, v4 :: v_dual_lshlrev_b32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0xa2,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0xa2,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v6, null, v5 :: v_dual_lshlrev_b32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xa2,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0xa2,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, v4, v2 :: v_dual_max_num_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x94,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x94,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v1, v2 :: v_dual_max_num_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x94,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x94,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v255, v2 :: v_dual_max_num_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x94,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x94,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v2, v2 :: v_dual_max_num_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x94,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x94,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v3, v2 :: v_dual_max_num_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x94,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x94,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, s105, v2 :: v_dual_max_num_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x94,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x94,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, s1, v2 :: v_dual_max_num_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x94,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x94,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, ttmp15, v2 :: v_dual_max_num_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x94,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x94,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, exec_hi, v2 :: v_dual_max_num_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x94,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x94,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, exec_lo, v2 :: v_dual_max_num_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x94,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x94,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, m0, v2 :: v_dual_max_num_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x94,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x94,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, vcc_hi, v2 :: v_dual_max_num_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x94,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x94,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, vcc_lo, v2 :: v_dual_max_num_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x94,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x94,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, 0xaf123456, v2 :: v_dual_max_num_f32 v6, null, v3 ; encoding: [0xff,0x04,0x94,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x94,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, src_scc, v2 :: v_dual_max_num_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x94,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x94,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_max_num_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x94,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x94,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, -1, v4 :: v_dual_max_num_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x94,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x94,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v6, null, v5 :: v_dual_max_num_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x94,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x94,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, v4, v2 :: v_dual_min_num_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x96,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x96,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v1, v2 :: v_dual_min_num_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x96,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x96,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v255, v2 :: v_dual_min_num_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x96,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x96,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v2, v2 :: v_dual_min_num_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x96,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x96,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v3, v2 :: v_dual_min_num_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x96,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x96,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, s105, v2 :: v_dual_min_num_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x96,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x96,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, s1, v2 :: v_dual_min_num_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x96,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x96,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, ttmp15, v2 :: v_dual_min_num_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x96,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x96,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, exec_hi, v2 :: v_dual_min_num_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x96,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x96,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, exec_lo, v2 :: v_dual_min_num_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x96,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x96,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, m0, v2 :: v_dual_min_num_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x96,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x96,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, vcc_hi, v2 :: v_dual_min_num_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x96,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x96,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, vcc_lo, v2 :: v_dual_min_num_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x96,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x96,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, 0xaf123456, v2 :: v_dual_min_num_f32 v6, null, v3 ; encoding: [0xff,0x04,0x96,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x96,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, src_scc, v2 :: v_dual_min_num_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x96,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x96,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_min_num_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x96,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x96,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, -1, v4 :: v_dual_min_num_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x96,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x96,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v6, null, v5 :: v_dual_min_num_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x96,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x96,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, v4, v255 :: v_dual_mov_b32 v6, v1 ; encoding: [0x04,0xff,0x91,0xc9,0x01,0x01,0x06,0xff]
+0x04,0xff,0x91,0xc9,0x01,0x01,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v1, v255 :: v_dual_mov_b32 v6, v255 ; encoding: [0x01,0xff,0x91,0xc9,0xff,0x01,0x06,0xff]
+0x01,0xff,0x91,0xc9,0xff,0x01,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v255, v255 :: v_dual_mov_b32 v6, v2 ; encoding: [0xff,0xff,0x91,0xc9,0x02,0x01,0x06,0xff]
+0xff,0xff,0x91,0xc9,0x02,0x01,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v2, v255 :: v_dual_mov_b32 v6, v3 ; encoding: [0x02,0xff,0x91,0xc9,0x03,0x01,0x06,0xff]
+0x02,0xff,0x91,0xc9,0x03,0x01,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v3, v255 :: v_dual_mov_b32 v6, v4 ; encoding: [0x03,0xff,0x91,0xc9,0x04,0x01,0x06,0xff]
+0x03,0xff,0x91,0xc9,0x04,0x01,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, s105, v255 :: v_dual_mov_b32 v6, s1 ; encoding: [0x69,0xfe,0x91,0xc9,0x01,0x00,0x06,0xff]
+0x69,0xfe,0x91,0xc9,0x01,0x00,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, s1, v255 :: v_dual_mov_b32 v6, s105 ; encoding: [0x01,0xfe,0x91,0xc9,0x69,0x00,0x06,0xff]
+0x01,0xfe,0x91,0xc9,0x69,0x00,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, ttmp15, v255 :: v_dual_mov_b32 v6, vcc_lo ; encoding: [0x7b,0xfe,0x91,0xc9,0x6a,0x00,0x06,0xff]
+0x7b,0xfe,0x91,0xc9,0x6a,0x00,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, exec_hi, v255 :: v_dual_mov_b32 v6, vcc_hi ; encoding: [0x7f,0xfe,0x91,0xc9,0x6b,0x00,0x06,0xff]
+0x7f,0xfe,0x91,0xc9,0x6b,0x00,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, exec_lo, v255 :: v_dual_mov_b32 v6, ttmp15 ; encoding: [0x7e,0xfe,0x91,0xc9,0x7b,0x00,0x06,0xff]
+0x7e,0xfe,0x91,0xc9,0x7b,0x00,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, m0, v255 :: v_dual_mov_b32 v6, m0 ; encoding: [0x7d,0xfe,0x91,0xc9,0x7d,0x00,0x06,0xff]
+0x7d,0xfe,0x91,0xc9,0x7d,0x00,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, vcc_hi, v255 :: v_dual_mov_b32 v6, exec_lo ; encoding: [0x6b,0xfe,0x91,0xc9,0x7e,0x00,0x06,0xff]
+0x6b,0xfe,0x91,0xc9,0x7e,0x00,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, vcc_lo, v255 :: v_dual_mov_b32 v6, exec_hi ; encoding: [0x6a,0xfe,0x91,0xc9,0x7f,0x00,0x06,0xff]
+0x6a,0xfe,0x91,0xc9,0x7f,0x00,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, 0xaf123456, v255 :: v_dual_mov_b32 v6, null ; encoding: [0xff,0xfe,0x91,0xc9,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0xfe,0x91,0xc9,0x7c,0x00,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, src_scc, v255 :: v_dual_mov_b32 v6, -1 ; encoding: [0xfd,0xfe,0x91,0xc9,0xc1,0x00,0x06,0xff]
+0xfd,0xfe,0x91,0xc9,0xc1,0x00,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_mov_b32 v6, 0.5 ; encoding: [0xf0,0x06,0x90,0xc9,0xf0,0x00,0x06,0xff]
+0xf0,0x06,0x90,0xc9,0xf0,0x00,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, -1, v4 :: v_dual_mov_b32 v6, src_scc ; encoding: [0xc1,0x08,0x90,0xc9,0xfd,0x00,0x06,0xff]
+0xc1,0x08,0x90,0xc9,0xfd,0x00,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v6, null, v5 :: v_dual_mov_b32 v255, 0xaf123456 ; encoding: [0x7c,0x0a,0x90,0xc9,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x90,0xc9,0xff,0x00,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, v4, v2 :: v_dual_mul_dx9_zero_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x8e,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x8e,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v1, v2 :: v_dual_mul_dx9_zero_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x8e,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x8e,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v255, v2 :: v_dual_mul_dx9_zero_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x8e,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x8e,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v2, v2 :: v_dual_mul_dx9_zero_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x8e,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x8e,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v3, v2 :: v_dual_mul_dx9_zero_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x8e,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x8e,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, s105, v2 :: v_dual_mul_dx9_zero_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x8e,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x8e,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, s1, v2 :: v_dual_mul_dx9_zero_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x8e,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x8e,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, ttmp15, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x8e,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x8e,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, exec_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x8e,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x8e,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, exec_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x8e,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x8e,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, m0, v2 :: v_dual_mul_dx9_zero_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x8e,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x8e,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, vcc_hi, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x8e,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x8e,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, vcc_lo, v2 :: v_dual_mul_dx9_zero_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x8e,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x8e,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, 0xaf123456, v2 :: v_dual_mul_dx9_zero_f32 v6, null, v3 ; encoding: [0xff,0x04,0x8e,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x8e,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, src_scc, v2 :: v_dual_mul_dx9_zero_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x8e,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x8e,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_mul_dx9_zero_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x8e,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x8e,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, -1, v4 :: v_dual_mul_dx9_zero_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x8e,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x8e,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v6, null, v5 :: v_dual_mul_dx9_zero_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x8e,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x8e,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, v4, v2 :: v_dual_mul_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x86,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x86,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v1, v2 :: v_dual_mul_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x86,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x86,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v255, v2 :: v_dual_mul_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x86,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x86,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v2, v2 :: v_dual_mul_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x86,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x86,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v3, v2 :: v_dual_mul_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x86,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x86,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, s105, v2 :: v_dual_mul_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x86,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x86,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, s1, v2 :: v_dual_mul_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x86,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x86,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, ttmp15, v2 :: v_dual_mul_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x86,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x86,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, exec_hi, v2 :: v_dual_mul_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x86,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x86,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, exec_lo, v2 :: v_dual_mul_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x86,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x86,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, m0, v2 :: v_dual_mul_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x86,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x86,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, vcc_hi, v2 :: v_dual_mul_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x86,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x86,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, vcc_lo, v2 :: v_dual_mul_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x86,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x86,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, 0xaf123456, v2 :: v_dual_mul_f32 v6, null, v3 ; encoding: [0xff,0x04,0x86,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x86,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, src_scc, v2 :: v_dual_mul_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x86,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x86,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_mul_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x86,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x86,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, -1, v4 :: v_dual_mul_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x86,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x86,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v6, null, v5 :: v_dual_mul_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x86,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x86,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, v4, v2 :: v_dual_sub_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x8a,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x8a,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v1, v2 :: v_dual_sub_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x8a,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x8a,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v255, v2 :: v_dual_sub_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x8a,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x8a,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v2, v2 :: v_dual_sub_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x8a,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x8a,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v3, v2 :: v_dual_sub_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x8a,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x8a,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, s105, v2 :: v_dual_sub_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x8a,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x8a,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, s1, v2 :: v_dual_sub_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x8a,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x8a,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, ttmp15, v2 :: v_dual_sub_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x8a,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x8a,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, exec_hi, v2 :: v_dual_sub_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x8a,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x8a,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, exec_lo, v2 :: v_dual_sub_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x8a,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x8a,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, m0, v2 :: v_dual_sub_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x8a,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x8a,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, vcc_hi, v2 :: v_dual_sub_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x8a,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x8a,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, vcc_lo, v2 :: v_dual_sub_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x8a,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x8a,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, 0xaf123456, v2 :: v_dual_sub_f32 v6, null, v3 ; encoding: [0xff,0x04,0x8a,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x8a,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, src_scc, v2 :: v_dual_sub_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x8a,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x8a,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_sub_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x8a,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x8a,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, -1, v4 :: v_dual_sub_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x8a,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x8a,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v6, null, v5 :: v_dual_sub_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x8a,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x8a,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, v4, v2 :: v_dual_subrev_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x8c,0xc9,0x01,0x07,0x06,0xff]
+0x04,0x05,0x8c,0xc9,0x01,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v1, v2 :: v_dual_subrev_f32 v6, v255, v3 ; encoding: [0x01,0x05,0x8c,0xc9,0xff,0x07,0x06,0xff]
+0x01,0x05,0x8c,0xc9,0xff,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v255, v2 :: v_dual_subrev_f32 v6, v2, v3 ; encoding: [0xff,0x05,0x8c,0xc9,0x02,0x07,0x06,0xff]
+0xff,0x05,0x8c,0xc9,0x02,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v2, v2 :: v_dual_subrev_f32 v6, v3, v3 ; encoding: [0x02,0x05,0x8c,0xc9,0x03,0x07,0x06,0xff]
+0x02,0x05,0x8c,0xc9,0x03,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, v3, v2 :: v_dual_subrev_f32 v6, v4, v3 ; encoding: [0x03,0x05,0x8c,0xc9,0x04,0x07,0x06,0xff]
+0x03,0x05,0x8c,0xc9,0x04,0x07,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, s105, v2 :: v_dual_subrev_f32 v6, s1, v3 ; encoding: [0x69,0x04,0x8c,0xc9,0x01,0x06,0x06,0xff]
+0x69,0x04,0x8c,0xc9,0x01,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, s1, v2 :: v_dual_subrev_f32 v6, s105, v3 ; encoding: [0x01,0x04,0x8c,0xc9,0x69,0x06,0x06,0xff]
+0x01,0x04,0x8c,0xc9,0x69,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, ttmp15, v2 :: v_dual_subrev_f32 v6, vcc_lo, v3 ; encoding: [0x7b,0x04,0x8c,0xc9,0x6a,0x06,0x06,0xff]
+0x7b,0x04,0x8c,0xc9,0x6a,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, exec_hi, v2 :: v_dual_subrev_f32 v6, vcc_hi, v3 ; encoding: [0x7f,0x04,0x8c,0xc9,0x6b,0x06,0x06,0xff]
+0x7f,0x04,0x8c,0xc9,0x6b,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, exec_lo, v2 :: v_dual_subrev_f32 v6, ttmp15, v3 ; encoding: [0x7e,0x04,0x8c,0xc9,0x7b,0x06,0x06,0xff]
+0x7e,0x04,0x8c,0xc9,0x7b,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, m0, v2 :: v_dual_subrev_f32 v6, m0, v3 ; encoding: [0x7d,0x04,0x8c,0xc9,0x7d,0x06,0x06,0xff]
+0x7d,0x04,0x8c,0xc9,0x7d,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, vcc_hi, v2 :: v_dual_subrev_f32 v6, exec_lo, v3 ; encoding: [0x6b,0x04,0x8c,0xc9,0x7e,0x06,0x06,0xff]
+0x6b,0x04,0x8c,0xc9,0x7e,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, vcc_lo, v2 :: v_dual_subrev_f32 v6, exec_hi, v3 ; encoding: [0x6a,0x04,0x8c,0xc9,0x7f,0x06,0x06,0xff]
+0x6a,0x04,0x8c,0xc9,0x7f,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, 0xaf123456, v2 :: v_dual_subrev_f32 v6, null, v3 ; encoding: [0xff,0x04,0x8c,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x8c,0xc9,0x7c,0x06,0x06,0xff,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_subrev_f32 v255, src_scc, v2 :: v_dual_subrev_f32 v6, -1, v3 ; encoding: [0xfd,0x04,0x8c,0xc9,0xc1,0x06,0x06,0xff]
+0xfd,0x04,0x8c,0xc9,0xc1,0x06,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, 0.5, v3 :: v_dual_subrev_f32 v6, 0.5, v2 ; encoding: [0xf0,0x06,0x8c,0xc9,0xf0,0x04,0x06,0xff]
+0xf0,0x06,0x8c,0xc9,0xf0,0x04,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v255, -1, v4 :: v_dual_subrev_f32 v6, src_scc, v5 ; encoding: [0xc1,0x08,0x8c,0xc9,0xfd,0x0a,0x06,0xff]
+0xc1,0x08,0x8c,0xc9,0xfd,0x0a,0x06,0xff
+
+# GFX12: v_dual_subrev_f32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0x8c,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf]
+0x7c,0x0a,0x8c,0xc9,0xff,0x08,0xfe,0x06,0x56,0x34,0x12,0xaf
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopd_features.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopd_features.txt
new file mode 100644
index 000000000000..fc943f7f003e
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopd_features.txt
@@ -0,0 +1,23 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX12 %s
+
+#===------------------------------------------------------------------------===#
+# Check instructions with several literals
+#===------------------------------------------------------------------------===#
+
+# GFX12: v_dual_add_f32 v5, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, v3, v1, 0xaf123456 ; encoding: [0xff,0x04,0x02,0xc9,0x03,0x03,0x06,0x05,0x56,0x34,0x12,0xaf]
+0xff,0x04,0x02,0xc9,0x03,0x03,0x06,0x05,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmaak_f32 v122, s74, v161, 0x402f6c8b :: v_dual_fmamk_f32 v3, v6, 0x402f6c8b, v1 ; encoding: [0x4a,0x42,0x45,0xc8,0x06,0x03,0x02,0x7a,0x8b,0x6c,0x2f,0x40]
+0x4a,0x42,0x45,0xc8,0x06,0x03,0x02,0x7a,0x8b,0x6c,0x2f,0x40
+
+# GFX12: v_dual_fmaak_f32 v6, v3, v1, 0xaf123456 :: v_dual_add_f32 v5, 0xaf123456, v2 ; encoding: [0x03,0x03,0x48,0xc8,0xff,0x04,0x04,0x06,0x56,0x34,0x12,0xaf]
+0x03,0x03,0x48,0xc8,0xff,0x04,0x04,0x06,0x56,0x34,0x12,0xaf
+
+# GFX12: v_dual_fmamk_f32 v122, 0xdeadbeef, 0xdeadbeef, v161 :: v_dual_fmamk_f32 v123, 0xdeadbeef, 0xdeadbeef, v162 ; encoding: [0xff,0x42,0x85,0xc8,0xff,0x44,0x7b,0x7a,0xef,0xbe,0xad,0xde]
+0xff,0x42,0x85,0xc8,0xff,0x44,0x7b,0x7a,0xef,0xbe,0xad,0xde
+
+# GFX12: v_dual_fmaak_f32 v122, s74, v161, 0x402f6c8b :: v_dual_mov_b32 v247, 0x402f6c8b ; encoding: [0x4a,0x42,0x51,0xc8,0xff,0x00,0xf6,0x7a,0x8b,0x6c,0x2f,0x40]
+0x4a,0x42,0x51,0xc8,0xff,0x00,0xf6,0x7a,0x8b,0x6c,0x2f,0x40
+
+# GFX12: v_dual_mul_f32 v11, 0x24681357, v2 :: v_dual_mul_f32 v10, 0x24681357, v5 ; encoding: [0xff,0x04,0xc6,0xc8,0xff,0x0a,0x0a,0x0b,0x57,0x13,0x68,0x24]
+0xff,0x04,0xc6,0xc8,0xff,0x0a,0x0a,0x0b,0x57,0x13,0x68,0x24
-- 
GitLab


From 696cc20d4e748f2619f7398dcfe8f4ed8d0863ab Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Tue, 12 Dec 2023 11:42:20 +0100
Subject: [PATCH 265/349] [LVI] Make UndefAllowed argument of
 getConstantRange() required

For the two remaining uses that did not explicitly specify it,
set UndefAllowed=false. In both cases, I believe that treating
undef as a full range is the correct behavior.
---
 llvm/include/llvm/Analysis/LazyValueInfo.h       | 2 +-
 llvm/lib/Transforms/IPO/AttributorAttributes.cpp | 3 ++-
 llvm/lib/Transforms/Utils/LowerSwitch.cpp        | 3 ++-
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/llvm/include/llvm/Analysis/LazyValueInfo.h b/llvm/include/llvm/Analysis/LazyValueInfo.h
index ead9f5f0225c..bf2fc47fa642 100644
--- a/llvm/include/llvm/Analysis/LazyValueInfo.h
+++ b/llvm/include/llvm/Analysis/LazyValueInfo.h
@@ -95,7 +95,7 @@ namespace llvm {
     /// specified value at the specified instruction. This may only be called
     /// on integer-typed Values.
     ConstantRange getConstantRange(Value *V, Instruction *CxtI,
-                                   bool UndefAllowed = true);
+                                   bool UndefAllowed);
 
     /// Return the ConstantRange constraint that is known to hold for the value
     /// at a specific use-site.
diff --git a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
index cbe0a96976c3..8e1f782f7cd8 100644
--- a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
+++ b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
@@ -9051,7 +9051,8 @@ struct AAValueConstantRangeImpl : AAValueConstantRange {
     if (!LVI || !CtxI)
       return getWorstState(getBitWidth());
     return LVI->getConstantRange(&getAssociatedValue(),
-                                 const_cast<Instruction *>(CtxI));
+                                 const_cast<Instruction *>(CtxI),
+                                 /*UndefAllowed*/ false);
   }
 
   /// Return true if \p CtxI is valid for querying outside analyses.
diff --git a/llvm/lib/Transforms/Utils/LowerSwitch.cpp b/llvm/lib/Transforms/Utils/LowerSwitch.cpp
index d1cdab7599c4..4131d36b572d 100644
--- a/llvm/lib/Transforms/Utils/LowerSwitch.cpp
+++ b/llvm/lib/Transforms/Utils/LowerSwitch.cpp
@@ -412,7 +412,8 @@ void ProcessSwitchInst(SwitchInst *SI,
     // TODO Shouldn't this create a signed range?
     ConstantRange KnownBitsRange =
         ConstantRange::fromKnownBits(Known, /*IsSigned=*/false);
-    const ConstantRange LVIRange = LVI->getConstantRange(Val, SI);
+    const ConstantRange LVIRange =
+        LVI->getConstantRange(Val, SI, /*UndefAllowed*/ false);
     ConstantRange ValRange = KnownBitsRange.intersectWith(LVIRange);
     // We delegate removal of unreachable non-default cases to other passes. In
     // the unlikely event that some of them survived, we just conservatively
-- 
GitLab


From 2bab0e01676ce7c9609a60bf86cb07c17f6080f0 Mon Sep 17 00:00:00 2001
From: Guillaume Chatelet <gchatelet@google.com>
Date: Tue, 12 Dec 2023 11:44:27 +0100
Subject: [PATCH 266/349] [libc][NFC] Swap ifdef logic for UInt128 (#75160)

---
 libc/src/__support/UInt128.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/libc/src/__support/UInt128.h b/libc/src/__support/UInt128.h
index 2f688f1f31cb..0558e5095f9f 100644
--- a/libc/src/__support/UInt128.h
+++ b/libc/src/__support/UInt128.h
@@ -11,12 +11,12 @@
 
 #include "UInt.h"
 
-#if !defined(__SIZEOF_INT128__)
-using UInt128 = LIBC_NAMESPACE::cpp::UInt<128>;
-using Int128 = LIBC_NAMESPACE::cpp::Int<128>;
-#else
+#if defined(__SIZEOF_INT128__)
 using UInt128 = __uint128_t;
 using Int128 = __int128_t;
+#else
+using UInt128 = LIBC_NAMESPACE::cpp::UInt<128>;
+using Int128 = LIBC_NAMESPACE::cpp::Int<128>;
 #endif
 
 #endif // LLVM_LIBC_SRC___SUPPORT_UINT128_H
-- 
GitLab


From 27d9a479c09632db4fef8eac204764de97d52925 Mon Sep 17 00:00:00 2001
From: jeanPerier <jperier@nvidia.com>
Date: Tue, 12 Dec 2023 11:52:39 +0100
Subject: [PATCH 267/349] [flang] Add struct passing target rewrite hooks and
 partial X86-64 impl (#74829)

In the context of C/Fortran interoperability (BIND(C)), it is possible
to give the VALUE attribute to a BIND(C) derived type dummy, which
according to Fortran 2018 18.3.6 - 2. (4) implies that it must be passed
like the equivalent C structure value. The way C structure value are
passed is ABI dependent.

LLVM does not implement the C struct ABI passing for LLVM aggregate type
arguments. It is up to the front-end, like clang is doing, to split the
struct into registers or pass the struct on the stack (llvm "byval") as
required by the target ABI.
So the logic for C struct passing sits in clang. Using it from flang
requires setting up a lot of clang context and to bridge FIR/MLIR
representation to clang AST representation for function signatures (in
both directions). It is a non trivial task.
See
https://stackoverflow.com/questions/39438033/passing-structs-by-value-in-llvm-ir/75002581#75002581.

Since BIND(C) struct are rather limited as opposed to generic C struct
(e.g. no bit fields). It is easier to provide a limited implementation
of it for the case that matter to Fortran.

This patch:
- Updates the generic target rewrite pass to keep track of both the new
argument type and attributes. The motivation for this is to be able to
tell if a previously marshalled argument is passed in memory (it is a C
pointer), or if it is being passed on the stack (has the byval llvm
attributes).
- Adds an entry point in the target specific codegen to marshal struct
arguments, and use it in the generic target rewrite pass.
- Implements limited support for the X86-64 case. So far, the support
allows telling if a struct must be passed in register or on the stack,
and to deal with the stack case. The register case is left TODO in this
patch.

The X86-64 ABI implemented is the System V ABI for AMD64 version 1.0
---
 .../flang/Optimizer/CodeGen/CGPasses.td       |   5 +-
 .../include/flang/Optimizer/CodeGen/Target.h  |  34 +-
 .../flang/Optimizer/CodeGen/TypeConverter.h   |   6 +-
 .../flang/Optimizer/Dialect/FIRTypes.td       |  10 +
 .../flang/Optimizer/Support/DataLayout.h      |  12 +
 flang/lib/Optimizer/CodeGen/CodeGen.cpp       |  14 +-
 flang/lib/Optimizer/CodeGen/Target.cpp        | 343 ++++++++++++-
 flang/lib/Optimizer/CodeGen/TargetRewrite.cpp | 459 +++++++++++-------
 flang/lib/Optimizer/CodeGen/TypeConverter.cpp |   5 +-
 flang/lib/Optimizer/Dialect/FIRType.cpp       |   6 +
 flang/lib/Optimizer/Support/DataLayout.cpp    |  13 +
 flang/test/Fir/recursive-type-tco.fir         |   4 +-
 .../test/Fir/struct-passing-x86-64-byval.fir  | 107 ++++
 13 files changed, 828 insertions(+), 190 deletions(-)
 create mode 100644 flang/test/Fir/struct-passing-x86-64-byval.fir

diff --git a/flang/include/flang/Optimizer/CodeGen/CGPasses.td b/flang/include/flang/Optimizer/CodeGen/CGPasses.td
index 0014298a27a2..5e4711958277 100644
--- a/flang/include/flang/Optimizer/CodeGen/CGPasses.td
+++ b/flang/include/flang/Optimizer/CodeGen/CGPasses.td
@@ -23,7 +23,7 @@ def FIRToLLVMLowering : Pass<"fir-to-llvm-ir", "mlir::ModuleOp"> {
     will also convert ops in the standard and FIRCG dialects.
   }];
   let constructor = "::fir::createFIRToLLVMPass()";
-  let dependentDialects = ["mlir::LLVM::LLVMDialect"];
+  let dependentDialects = ["mlir::LLVM::LLVMDialect", "mlir::DLTIDialect"];
   let options = [
     Option<"forcedTargetTriple", "target", "std::string", /*default=*/"",
            "Override module's target triple.">,
@@ -53,7 +53,8 @@ def TargetRewritePass : Pass<"target-rewrite", "mlir::ModuleOp"> {
       representations that may differ based on the target machine.
   }];
   let constructor = "::fir::createFirTargetRewritePass()";
-  let dependentDialects = [ "fir::FIROpsDialect", "mlir::func::FuncDialect" ];
+  let dependentDialects = [ "fir::FIROpsDialect", "mlir::func::FuncDialect",
+                            "mlir::DLTIDialect" ];
   let options = [
     Option<"forcedTargetTriple", "target", "std::string", /*default=*/"",
            "Override module's target triple.">,
diff --git a/flang/include/flang/Optimizer/CodeGen/Target.h b/flang/include/flang/Optimizer/CodeGen/Target.h
index acffe6c1cec9..c3ef521ced12 100644
--- a/flang/include/flang/Optimizer/CodeGen/Target.h
+++ b/flang/include/flang/Optimizer/CodeGen/Target.h
@@ -13,6 +13,7 @@
 #ifndef FORTRAN_OPTMIZER_CODEGEN_TARGET_H
 #define FORTRAN_OPTMIZER_CODEGEN_TARGET_H
 
+#include "flang/Optimizer/Dialect/FIRType.h"
 #include "flang/Optimizer/Dialect/Support/KindMapping.h"
 #include "mlir/IR/BuiltinTypes.h"
 #include "llvm/TargetParser/Triple.h"
@@ -20,6 +21,10 @@
 #include <tuple>
 #include <vector>
 
+namespace mlir {
+class DataLayout;
+}
+
 namespace fir {
 
 namespace details {
@@ -62,14 +67,20 @@ private:
 class CodeGenSpecifics {
 public:
   using Attributes = details::Attributes;
-  using Marshalling = std::vector<std::tuple<mlir::Type, Attributes>>;
+  using TypeAndAttr = std::tuple<mlir::Type, Attributes>;
+  using Marshalling = std::vector<TypeAndAttr>;
+
+  static std::unique_ptr<CodeGenSpecifics> get(mlir::MLIRContext *ctx,
+                                               llvm::Triple &&trp,
+                                               KindMapping &&kindMap,
+                                               const mlir::DataLayout &dl);
 
-  static std::unique_ptr<CodeGenSpecifics>
-  get(mlir::MLIRContext *ctx, llvm::Triple &&trp, KindMapping &&kindMap);
+  static TypeAndAttr getTypeAndAttr(mlir::Type t) { return TypeAndAttr{t, {}}; }
 
   CodeGenSpecifics(mlir::MLIRContext *ctx, llvm::Triple &&trp,
-                   KindMapping &&kindMap)
-      : context{*ctx}, triple{std::move(trp)}, kindMap{std::move(kindMap)} {}
+                   KindMapping &&kindMap, const mlir::DataLayout &dl)
+      : context{*ctx}, triple{std::move(trp)}, kindMap{std::move(kindMap)},
+        dataLayout{&dl} {}
   CodeGenSpecifics() = delete;
   virtual ~CodeGenSpecifics() {}
 
@@ -90,6 +101,13 @@ public:
   /// Type presentation of a `boxchar<n>` type value in memory.
   virtual mlir::Type boxcharMemoryType(mlir::Type eleTy) const = 0;
 
+  /// Type representation of a `fir.type<T>` type argument when passed by
+  /// value. It may have to be split into several arguments, or be passed
+  /// as a byval reference argument (on the stack).
+  virtual Marshalling
+  structArgumentType(mlir::Location loc, fir::RecordType recTy,
+                     const Marshalling &previousArguments) const = 0;
+
   /// Type representation of a `boxchar<n>` type argument when passed by value.
   /// An argument value may need to be passed as a (safe) reference argument.
   ///
@@ -143,10 +161,16 @@ public:
   // Returns width in bits of C/C++ 'int' type size.
   virtual unsigned char getCIntTypeWidth() const = 0;
 
+  const mlir::DataLayout &getDataLayout() const {
+    assert(dataLayout && "dataLayout must be set");
+    return *dataLayout;
+  }
+
 protected:
   mlir::MLIRContext &context;
   llvm::Triple triple;
   KindMapping kindMap;
+  const mlir::DataLayout *dataLayout = nullptr;
 };
 
 } // namespace fir
diff --git a/flang/include/flang/Optimizer/CodeGen/TypeConverter.h b/flang/include/flang/Optimizer/CodeGen/TypeConverter.h
index 9ce756bdfd96..396c13639255 100644
--- a/flang/include/flang/Optimizer/CodeGen/TypeConverter.h
+++ b/flang/include/flang/Optimizer/CodeGen/TypeConverter.h
@@ -39,6 +39,10 @@ static constexpr unsigned kDimLowerBoundPos = 0;
 static constexpr unsigned kDimExtentPos = 1;
 static constexpr unsigned kDimStridePos = 2;
 
+namespace mlir {
+class DataLayout;
+}
+
 namespace fir {
 
 /// FIR type converter
@@ -46,7 +50,7 @@ namespace fir {
 class LLVMTypeConverter : public mlir::LLVMTypeConverter {
 public:
   LLVMTypeConverter(mlir::ModuleOp module, bool applyTBAA,
-                    bool forceUnifiedTBAATree);
+                    bool forceUnifiedTBAATree, const mlir::DataLayout &);
 
   // i32 is used here because LLVM wants i32 constants when indexing into struct
   // types. Indexing into other aggregate types is more flexible.
diff --git a/flang/include/flang/Optimizer/Dialect/FIRTypes.td b/flang/include/flang/Optimizer/Dialect/FIRTypes.td
index 51608e3c1d63..2a2f50720859 100644
--- a/flang/include/flang/Optimizer/Dialect/FIRTypes.td
+++ b/flang/include/flang/Optimizer/Dialect/FIRTypes.td
@@ -326,6 +326,8 @@ def fir_RealType : FIR_Type<"Real", "real"> {
 
   let extraClassDeclaration = [{
     using KindTy = unsigned;
+    // Get MLIR float type with same semantics.
+    mlir::Type getFloatType(const fir::KindMapping &kindMap) const;
   }];
 
   let genVerifyDecl = 1;
@@ -495,6 +497,14 @@ def fir_SequenceType : FIR_Type<"Sequence", "array"> {
     static constexpr Extent getUnknownExtent() {
       return mlir::ShapedType::kDynamic;
     }
+
+    std::uint64_t getConstantArraySize() {
+      assert(!hasDynamicExtents() && "array type must have constant shape");
+      std::uint64_t size = 1;
+      for (Extent extent : getShape())
+        size = size * static_cast<std::uint64_t>(extent);
+      return size;
+    }
   }];
 }
 
diff --git a/flang/include/flang/Optimizer/Support/DataLayout.h b/flang/include/flang/Optimizer/Support/DataLayout.h
index 88ff575a8ff0..d21576bb95f7 100644
--- a/flang/include/flang/Optimizer/Support/DataLayout.h
+++ b/flang/include/flang/Optimizer/Support/DataLayout.h
@@ -13,6 +13,9 @@
 #ifndef FORTRAN_OPTIMIZER_SUPPORT_DATALAYOUT_H
 #define FORTRAN_OPTIMIZER_SUPPORT_DATALAYOUT_H
 
+#include "mlir/Interfaces/DataLayoutInterfaces.h"
+#include <optional>
+
 namespace mlir {
 class ModuleOp;
 }
@@ -34,6 +37,15 @@ void setMLIRDataLayout(mlir::ModuleOp mlirModule, const llvm::DataLayout &dl);
 /// nothing.
 void setMLIRDataLayoutFromAttributes(mlir::ModuleOp mlirModule,
                                      bool allowDefaultLayout);
+
+/// Create mlir::DataLayout from the data layout information on the
+/// mlir::Module. Creates the data layout information attributes with
+/// setMLIRDataLayoutFromAttributes if the DLTI attribute is not yet set. If no
+/// information is present at all and \p allowDefaultLayout is false, returns
+/// std::nullopt.
+std::optional<mlir::DataLayout>
+getOrSetDataLayout(mlir::ModuleOp mlirModule, bool allowDefaultLayout = false);
+
 } // namespace fir::support
 
 #endif // FORTRAN_OPTIMIZER_SUPPORT_DATALAYOUT_H
diff --git a/flang/lib/Optimizer/CodeGen/CodeGen.cpp b/flang/lib/Optimizer/CodeGen/CodeGen.cpp
index 293208ce3b60..e07732d57880 100644
--- a/flang/lib/Optimizer/CodeGen/CodeGen.cpp
+++ b/flang/lib/Optimizer/CodeGen/CodeGen.cpp
@@ -16,6 +16,7 @@
 #include "flang/Optimizer/Dialect/FIRAttr.h"
 #include "flang/Optimizer/Dialect/FIROps.h"
 #include "flang/Optimizer/Dialect/FIRType.h"
+#include "flang/Optimizer/Support/DataLayout.h"
 #include "flang/Optimizer/Support/InternalNames.h"
 #include "flang/Optimizer/Support/TypeCode.h"
 #include "flang/Optimizer/Support/Utils.h"
@@ -34,6 +35,7 @@
 #include "mlir/Conversion/ReconcileUnrealizedCasts/ReconcileUnrealizedCasts.h"
 #include "mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h"
 #include "mlir/Dialect/Arith/IR/Arith.h"
+#include "mlir/Dialect/DLTI/DLTI.h"
 #include "mlir/Dialect/LLVMIR/LLVMDialect.h"
 #include "mlir/Dialect/LLVMIR/Transforms/AddComdats.h"
 #include "mlir/Dialect/OpenACC/OpenACC.h"
@@ -3831,10 +3833,20 @@ public:
     if (mlir::failed(runPipeline(mathConvertionPM, mod)))
       return signalPassFailure();
 
+    std::optional<mlir::DataLayout> dl =
+        fir::support::getOrSetDataLayout(mod, /*allowDefaultLayout=*/true);
+    if (!dl) {
+      mlir::emitError(mod.getLoc(),
+                      "module operation must carry a data layout attribute "
+                      "to generate llvm IR from FIR");
+      signalPassFailure();
+      return;
+    }
+
     auto *context = getModule().getContext();
     fir::LLVMTypeConverter typeConverter{getModule(),
                                          options.applyTBAA || applyTBAA,
-                                         options.forceUnifiedTBAATree};
+                                         options.forceUnifiedTBAATree, *dl};
     mlir::RewritePatternSet pattern(context);
     pattern.insert<
         AbsentOpConversion, AddcOpConversion, AddrOfOpConversion,
diff --git a/flang/lib/Optimizer/CodeGen/Target.cpp b/flang/lib/Optimizer/CodeGen/Target.cpp
index 112f56e268c3..3cd0e66fc7a1 100644
--- a/flang/lib/Optimizer/CodeGen/Target.cpp
+++ b/flang/lib/Optimizer/CodeGen/Target.cpp
@@ -18,6 +18,7 @@
 #include "flang/Optimizer/Support/Utils.h"
 #include "mlir/IR/BuiltinTypes.h"
 #include "mlir/IR/TypeRange.h"
+#include "llvm/ADT/TypeSwitch.h"
 
 #define DEBUG_TYPE "flang-codegen-target"
 
@@ -58,6 +59,63 @@ static void typeTodo(const llvm::fltSemantics *sem, mlir::Location loc,
   }
 }
 
+/// Return the size and alignment of FIR types.
+/// TODO: consider moving this to a DataLayoutTypeInterface implementation
+/// for FIR types. It should first be ensured that it is OK to open the gate of
+/// target dependent type size inquiries in lowering. It would also not be
+/// straightforward given the need for a kind map that would need to be
+/// converted in terms of mlir::DataLayoutEntryKey.
+static std::pair<std::uint64_t, unsigned short>
+getSizeAndAlignment(mlir::Location loc, mlir::Type ty,
+                    const mlir::DataLayout &dl,
+                    const fir::KindMapping &kindMap) {
+  if (mlir::isa<mlir::IntegerType, mlir::FloatType, mlir::ComplexType>(ty)) {
+    llvm::TypeSize size = dl.getTypeSize(ty);
+    unsigned short alignment = dl.getTypeABIAlignment(ty);
+    return {size, alignment};
+  }
+  if (auto firCmplx = mlir::dyn_cast<fir::ComplexType>(ty)) {
+    auto [floatSize, floatAlign] =
+        getSizeAndAlignment(loc, firCmplx.getEleType(kindMap), dl, kindMap);
+    return {llvm::alignTo(floatSize, floatAlign) + floatSize, floatAlign};
+  }
+  if (auto real = mlir::dyn_cast<fir::RealType>(ty))
+    return getSizeAndAlignment(loc, real.getFloatType(kindMap), dl, kindMap);
+
+  if (auto seqTy = mlir::dyn_cast<fir::SequenceType>(ty)) {
+    auto [eleSize, eleAlign] =
+        getSizeAndAlignment(loc, seqTy.getEleTy(), dl, kindMap);
+
+    std::uint64_t size =
+        llvm::alignTo(eleSize, eleAlign) * seqTy.getConstantArraySize();
+    return {size, eleAlign};
+  }
+  if (auto recTy = mlir::dyn_cast<fir::RecordType>(ty)) {
+    std::uint64_t size = 0;
+    unsigned short align = 1;
+    for (auto component : recTy.getTypeList()) {
+      auto [compSize, compAlign] =
+          getSizeAndAlignment(loc, component.second, dl, kindMap);
+      size =
+          llvm::alignTo(size, compAlign) + llvm::alignTo(compSize, compAlign);
+      align = std::max(align, compAlign);
+    }
+    return {size, align};
+  }
+  if (auto logical = mlir::dyn_cast<fir::LogicalType>(ty)) {
+    mlir::Type intTy = mlir::IntegerType::get(
+        logical.getContext(), kindMap.getLogicalBitsize(logical.getFKind()));
+    return getSizeAndAlignment(loc, intTy, dl, kindMap);
+  }
+  if (auto character = mlir::dyn_cast<fir::CharacterType>(ty)) {
+    mlir::Type intTy = mlir::IntegerType::get(
+        character.getContext(),
+        kindMap.getCharacterBitsize(character.getFKind()));
+    return getSizeAndAlignment(loc, intTy, dl, kindMap);
+  }
+  TODO(loc, "computing size of a component");
+}
+
 namespace {
 template <typename S>
 struct GenericTarget : public CodeGenSpecifics {
@@ -95,6 +153,12 @@ struct GenericTarget : public CodeGenSpecifics {
     return marshal;
   }
 
+  CodeGenSpecifics::Marshalling
+  structArgumentType(mlir::Location loc, fir::RecordType,
+                     const Marshalling &) const override {
+    TODO(loc, "passing VALUE BIND(C) derived type for this target");
+  }
+
   CodeGenSpecifics::Marshalling
   integerArgumentType(mlir::Location loc,
                       mlir::IntegerType argTy) const override {
@@ -318,6 +382,257 @@ struct TargetX86_64 : public GenericTarget<TargetX86_64> {
     }
     return marshal;
   }
+
+  /// X86-64 argument classes from System V ABI version 1.0 section 3.2.3.
+  enum ArgClass {
+    Integer = 0,
+    SSE,
+    SSEUp,
+    X87,
+    X87Up,
+    ComplexX87,
+    NoClass,
+    Memory
+  };
+
+  /// Classify an argument type or a field of an aggregate type argument.
+  /// See System V ABI version 1.0 section 3.2.3.
+  /// The Lo and Hi class are set to the class of the lower eight eightbytes
+  /// and upper eight eightbytes on return.
+  /// If this is called for an aggregate field, the caller is responsible to
+  /// do the post-merge.
+  void classify(mlir::Location loc, mlir::Type type, std::uint64_t byteOffset,
+                ArgClass &Lo, ArgClass &Hi) const {
+    Hi = Lo = ArgClass::NoClass;
+    ArgClass &current = byteOffset < 8 ? Lo : Hi;
+    // System V AMD64 ABI 3.2.3. version 1.0
+    llvm::TypeSwitch<mlir::Type>(type)
+        .template Case<mlir::IntegerType>([&](mlir::IntegerType intTy) {
+          if (intTy.getWidth() == 128)
+            Hi = Lo = ArgClass::Integer;
+          else
+            current = ArgClass::Integer;
+        })
+        .template Case<mlir::FloatType, fir::RealType>([&](mlir::Type floatTy) {
+          const auto *sem = &floatToSemantics(kindMap, floatTy);
+          if (sem == &llvm::APFloat::x87DoubleExtended()) {
+            Lo = ArgClass::X87;
+            Hi = ArgClass::X87Up;
+          } else if (sem == &llvm::APFloat::IEEEquad()) {
+            Lo = ArgClass::SSE;
+            Hi = ArgClass::SSEUp;
+          } else {
+            current = ArgClass::SSE;
+          }
+        })
+        .template Case<fir::ComplexType>([&](fir::ComplexType cmplx) {
+          const auto *sem = &floatToSemantics(kindMap, cmplx.getElementType());
+          if (sem == &llvm::APFloat::x87DoubleExtended()) {
+            current = ArgClass::ComplexX87;
+          } else {
+            fir::SequenceType::Shape shape{2};
+            classifyArray(loc,
+                          fir::SequenceType::get(shape, cmplx.getElementType()),
+                          byteOffset, Lo, Hi);
+          }
+        })
+        .template Case<fir::LogicalType>([&](fir::LogicalType logical) {
+          if (kindMap.getLogicalBitsize(logical.getFKind()) == 128)
+            Hi = Lo = ArgClass::Integer;
+          else
+            current = ArgClass::Integer;
+        })
+        .template Case<fir::CharacterType>(
+            [&](fir::CharacterType character) { current = ArgClass::Integer; })
+        .template Case<fir::SequenceType>([&](fir::SequenceType seqTy) {
+          // Array component.
+          classifyArray(loc, seqTy, byteOffset, Lo, Hi);
+        })
+        .template Case<fir::RecordType>([&](fir::RecordType recTy) {
+          // Component that is a derived type.
+          classifyStruct(loc, recTy, byteOffset, Lo, Hi);
+        })
+        .template Case<fir::VectorType>([&](fir::VectorType vecTy) {
+          // Previously marshalled SSE eight byte for a previous struct
+          // argument.
+          auto *sem = fir::isa_real(vecTy.getEleTy())
+                          ? &floatToSemantics(kindMap, vecTy.getEleTy())
+                          : nullptr;
+          // Not expecting to hit this todo in standard code (it would
+          // require some vector type extension).
+          if (!(sem == &llvm::APFloat::IEEEsingle() && vecTy.getLen() <= 2) &&
+              !(sem == &llvm::APFloat::IEEEhalf() && vecTy.getLen() <= 4))
+            TODO(loc, "passing vector argument to C by value");
+          current = SSE;
+        })
+        .Default([&](mlir::Type ty) {
+          if (fir::conformsWithPassByRef(ty))
+            current = ArgClass::Integer; // Pointers.
+          else
+            TODO(loc, "unsupported component type for BIND(C), VALUE derived "
+                      "type argument");
+        });
+  }
+
+  // Classify fields of a derived type starting at \p offset. Returns the new
+  // offset. Post-merge is left to the caller.
+  std::uint64_t classifyStruct(mlir::Location loc, fir::RecordType recTy,
+                               std::uint64_t byteOffset, ArgClass &Lo,
+                               ArgClass &Hi) const {
+    for (auto component : recTy.getTypeList()) {
+      if (byteOffset > 16) {
+        // See 3.2.3 p. 1 and note 15. Note that when the offset is bigger
+        // than 16 bytes here, it is not a single _m256 and or _m512 entity
+        // that could fit in AVX registers.
+        Lo = Hi = ArgClass::Memory;
+        return byteOffset;
+      }
+      mlir::Type compType = component.second;
+      auto [compSize, compAlign] =
+          getSizeAndAlignment(loc, compType, getDataLayout(), kindMap);
+      byteOffset = llvm::alignTo(byteOffset, compAlign);
+      ArgClass LoComp, HiComp;
+      classify(loc, compType, byteOffset, LoComp, HiComp);
+      Lo = mergeClass(Lo, LoComp);
+      Hi = mergeClass(Hi, HiComp);
+      byteOffset = byteOffset + llvm::alignTo(compSize, compAlign);
+      if (Lo == ArgClass::Memory || Hi == ArgClass::Memory)
+        return byteOffset;
+    }
+    return byteOffset;
+  }
+
+  // Classify fields of a constant size array type starting at \p offset.
+  // Returns the new offset. Post-merge is left to the caller.
+  void classifyArray(mlir::Location loc, fir::SequenceType seqTy,
+                     std::uint64_t byteOffset, ArgClass &Lo,
+                     ArgClass &Hi) const {
+    mlir::Type eleTy = seqTy.getEleTy();
+    const std::uint64_t arraySize = seqTy.getConstantArraySize();
+    auto [eleSize, eleAlign] =
+        getSizeAndAlignment(loc, eleTy, getDataLayout(), kindMap);
+    std::uint64_t eleStorageSize = llvm::alignTo(eleSize, eleAlign);
+    for (std::uint64_t i = 0; i < arraySize; ++i) {
+      byteOffset = llvm::alignTo(byteOffset, eleAlign);
+      if (byteOffset > 16) {
+        // See 3.2.3 p. 1 and note 15. Same as in classifyStruct.
+        Lo = Hi = ArgClass::Memory;
+        return;
+      }
+      ArgClass LoComp, HiComp;
+      classify(loc, eleTy, byteOffset, LoComp, HiComp);
+      Lo = mergeClass(Lo, LoComp);
+      Hi = mergeClass(Hi, HiComp);
+      byteOffset = byteOffset + eleStorageSize;
+      if (Lo == ArgClass::Memory || Hi == ArgClass::Memory)
+        return;
+    }
+  }
+
+  // Goes through the previously marshalled arguments and count the
+  // register occupancy to check if there are enough registers left.
+  bool hasEnoughRegisters(mlir::Location loc, int neededIntRegisters,
+                          int neededSSERegisters,
+                          const Marshalling &previousArguments) const {
+    int availIntRegisters = 6;
+    int availSSERegisters = 8;
+    for (auto typeAndAttr : previousArguments) {
+      const auto &attr = std::get<Attributes>(typeAndAttr);
+      if (attr.isByVal())
+        continue; // Previous argument passed on the stack.
+      ArgClass Lo, Hi;
+      Lo = Hi = ArgClass::NoClass;
+      classify(loc, std::get<mlir::Type>(typeAndAttr), 0, Lo, Hi);
+      // post merge is not needed here since previous aggregate arguments
+      // were marshalled into simpler arguments.
+      if (Lo == ArgClass::Integer)
+        --availIntRegisters;
+      else if (Lo == SSE)
+        --availSSERegisters;
+      if (Hi == ArgClass::Integer)
+        --availIntRegisters;
+      else if (Hi == ArgClass::SSE)
+        --availSSERegisters;
+    }
+    return availSSERegisters >= neededSSERegisters &&
+           availIntRegisters >= neededIntRegisters;
+  }
+
+  /// Argument class merging as described in System V ABI 3.2.3 point 4.
+  ArgClass mergeClass(ArgClass accum, ArgClass field) const {
+    assert((accum != ArgClass::Memory && accum != ArgClass::ComplexX87) &&
+           "Invalid accumulated classification during merge.");
+    if (accum == field || field == NoClass)
+      return accum;
+    if (field == ArgClass::Memory)
+      return ArgClass::Memory;
+    if (accum == NoClass)
+      return field;
+    if (accum == Integer || field == Integer)
+      return ArgClass::Integer;
+    if (field == ArgClass::X87 || field == ArgClass::X87Up ||
+        field == ArgClass::ComplexX87 || accum == ArgClass::X87 ||
+        accum == ArgClass::X87Up)
+      return Memory;
+    return SSE;
+  }
+
+  /// Argument class post merging as described in System V ABI 3.2.3 point 5.
+  void postMerge(std::uint64_t byteSize, ArgClass &Lo, ArgClass &Hi) const {
+    if (Hi == ArgClass::Memory)
+      Lo = ArgClass::Memory;
+    if (Hi == ArgClass::X87Up && Lo != ArgClass::X87)
+      Lo = ArgClass::Memory;
+    if (byteSize > 16 && (Lo != ArgClass::SSE || Hi != ArgClass::SSEUp))
+      Lo = ArgClass::Memory;
+    if (Hi == ArgClass::SSEUp && Lo != ArgClass::SSE)
+      Hi = SSE;
+  }
+
+  /// Marshal a derived type passed by value like a C struct.
+  CodeGenSpecifics::Marshalling
+  structArgumentType(mlir::Location loc, fir::RecordType recTy,
+                     const Marshalling &previousArguments) const override {
+    std::uint64_t byteOffset = 0;
+    ArgClass Lo, Hi;
+    Lo = Hi = ArgClass::NoClass;
+    byteOffset = classifyStruct(loc, recTy, byteOffset, Lo, Hi);
+    postMerge(byteOffset, Lo, Hi);
+    if (Lo == ArgClass::Memory || Lo == ArgClass::X87 ||
+        Lo == ArgClass::ComplexX87)
+      return passOnTheStack(loc, recTy);
+    int neededIntRegisters = 0;
+    int neededSSERegisters = 0;
+    if (Lo == ArgClass::SSE)
+      ++neededSSERegisters;
+    else if (Lo == ArgClass::Integer)
+      ++neededIntRegisters;
+    if (Hi == ArgClass::SSE)
+      ++neededSSERegisters;
+    else if (Hi == ArgClass::Integer)
+      ++neededIntRegisters;
+    // C struct should not be split into LLVM registers if LLVM codegen is not
+    // able to later assign actual registers to all of them (struct passing is
+    // all in registers or all on the stack).
+    if (!hasEnoughRegisters(loc, neededIntRegisters, neededSSERegisters,
+                            previousArguments))
+      return passOnTheStack(loc, recTy);
+    // TODO, marshal the struct into registers.
+    TODO(loc, "passing BIND(C), VALUE derived type in registers on X86-64");
+  }
+
+  /// Marshal an argument that must be passed on the stack.
+  CodeGenSpecifics::Marshalling passOnTheStack(mlir::Location loc,
+                                               mlir::Type ty) const {
+    CodeGenSpecifics::Marshalling marshal;
+    auto sizeAndAlign = getSizeAndAlignment(loc, ty, getDataLayout(), kindMap);
+    // The stack is always 8 byte aligned (note 14 in 3.2.3).
+    unsigned short align =
+        std::max(sizeAndAlign.second, static_cast<unsigned short>(8));
+    marshal.emplace_back(fir::ReferenceType::get(ty),
+                         AT{align, /*byval=*/true, /*sret=*/false});
+    return marshal;
+  }
 };
 } // namespace
 
@@ -726,51 +1041,51 @@ struct TargetLoongArch64 : public GenericTarget<TargetLoongArch64> {
 // TODO: Add other targets to this file as needed.
 std::unique_ptr<fir::CodeGenSpecifics>
 fir::CodeGenSpecifics::get(mlir::MLIRContext *ctx, llvm::Triple &&trp,
-                           KindMapping &&kindMap) {
+                           KindMapping &&kindMap, const mlir::DataLayout &dl) {
   switch (trp.getArch()) {
   default:
     break;
   case llvm::Triple::ArchType::x86:
     if (trp.isOSWindows())
       return std::make_unique<TargetI386Win>(ctx, std::move(trp),
-                                             std::move(kindMap));
+                                             std::move(kindMap), dl);
     else
       return std::make_unique<TargetI386>(ctx, std::move(trp),
-                                          std::move(kindMap));
+                                          std::move(kindMap), dl);
   case llvm::Triple::ArchType::x86_64:
     if (trp.isOSWindows())
       return std::make_unique<TargetX86_64Win>(ctx, std::move(trp),
-                                               std::move(kindMap));
+                                               std::move(kindMap), dl);
     else
       return std::make_unique<TargetX86_64>(ctx, std::move(trp),
-                                            std::move(kindMap));
+                                            std::move(kindMap), dl);
   case llvm::Triple::ArchType::aarch64:
     return std::make_unique<TargetAArch64>(ctx, std::move(trp),
-                                           std::move(kindMap));
+                                           std::move(kindMap), dl);
   case llvm::Triple::ArchType::ppc64:
     return std::make_unique<TargetPPC64>(ctx, std::move(trp),
-                                         std::move(kindMap));
+                                         std::move(kindMap), dl);
   case llvm::Triple::ArchType::ppc64le:
     return std::make_unique<TargetPPC64le>(ctx, std::move(trp),
-                                           std::move(kindMap));
+                                           std::move(kindMap), dl);
   case llvm::Triple::ArchType::sparc:
     return std::make_unique<TargetSparc>(ctx, std::move(trp),
-                                         std::move(kindMap));
+                                         std::move(kindMap), dl);
   case llvm::Triple::ArchType::sparcv9:
     return std::make_unique<TargetSparcV9>(ctx, std::move(trp),
-                                           std::move(kindMap));
+                                           std::move(kindMap), dl);
   case llvm::Triple::ArchType::riscv64:
     return std::make_unique<TargetRISCV64>(ctx, std::move(trp),
-                                           std::move(kindMap));
+                                           std::move(kindMap), dl);
   case llvm::Triple::ArchType::amdgcn:
     return std::make_unique<TargetAMDGPU>(ctx, std::move(trp),
-                                          std::move(kindMap));
+                                          std::move(kindMap), dl);
   case llvm::Triple::ArchType::nvptx64:
     return std::make_unique<TargetNVPTX>(ctx, std::move(trp),
-                                         std::move(kindMap));
+                                         std::move(kindMap), dl);
   case llvm::Triple::ArchType::loongarch64:
     return std::make_unique<TargetLoongArch64>(ctx, std::move(trp),
-                                               std::move(kindMap));
+                                               std::move(kindMap), dl);
   }
   TODO(mlir::UnknownLoc::get(ctx), "target not implemented");
 }
diff --git a/flang/lib/Optimizer/CodeGen/TargetRewrite.cpp b/flang/lib/Optimizer/CodeGen/TargetRewrite.cpp
index 241d1fa84e23..277f3e447ed1 100644
--- a/flang/lib/Optimizer/CodeGen/TargetRewrite.cpp
+++ b/flang/lib/Optimizer/CodeGen/TargetRewrite.cpp
@@ -25,6 +25,8 @@
 #include "flang/Optimizer/Dialect/FIROpsSupport.h"
 #include "flang/Optimizer/Dialect/FIRType.h"
 #include "flang/Optimizer/Dialect/Support/FIRContext.h"
+#include "flang/Optimizer/Support/DataLayout.h"
+#include "mlir/Dialect/DLTI/DLTI.h"
 #include "mlir/Transforms/DialectConversion.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/TypeSwitch.h"
@@ -87,9 +89,23 @@ public:
     if (!forcedTargetTriple.empty())
       fir::setTargetTriple(mod, forcedTargetTriple);
 
-    auto specifics = fir::CodeGenSpecifics::get(
-        mod.getContext(), fir::getTargetTriple(mod), fir::getKindMapping(mod));
-    setMembers(specifics.get(), &rewriter);
+    // TargetRewrite will require querying the type storage sizes, if it was
+    // not set already, create a DataLayoutSpec for the ModuleOp now.
+    std::optional<mlir::DataLayout> dl =
+        fir::support::getOrSetDataLayout(mod, /*allowDefaultLayout=*/true);
+    if (!dl) {
+      mlir::emitError(mod.getLoc(),
+                      "module operation must carry a data layout attribute "
+                      "to perform target ABI rewrites on FIR");
+      signalPassFailure();
+      return;
+    }
+
+    auto specifics =
+        fir::CodeGenSpecifics::get(mod.getContext(), fir::getTargetTriple(mod),
+                                   fir::getKindMapping(mod), *dl);
+
+    setMembers(specifics.get(), &rewriter, &*dl);
 
     // We may need to call stacksave/stackrestore later, so
     // create the FuncOps beforehand.
@@ -127,9 +143,10 @@ public:
 
   template <typename A, typename B, typename C>
   std::optional<std::function<mlir::Value(mlir::Operation *)>>
-  rewriteCallComplexResultType(mlir::Location loc, A ty, B &newResTys,
-                               B &newInTys, C &newOpers,
-                               mlir::Value &savedStackPtr) {
+  rewriteCallComplexResultType(
+      mlir::Location loc, A ty, B &newResTys,
+      fir::CodeGenSpecifics::Marshalling &newInTyAndAttrs, C &newOpers,
+      mlir::Value &savedStackPtr) {
     if (noComplexConversion) {
       newResTys.push_back(ty);
       return std::nullopt;
@@ -149,7 +166,7 @@ public:
         savedStackPtr = genStackSave(loc);
       mlir::Value stack =
           rewriter->create<fir::AllocaOp>(loc, fir::dyn_cast_ptrEleTy(resTy));
-      newInTys.push_back(resTy);
+      newInTyAndAttrs.push_back(m[0]);
       newOpers.push_back(stack);
       return [=](mlir::Operation *) -> mlir::Value {
         auto memTy = fir::ReferenceType::get(ty);
@@ -170,39 +187,49 @@ public:
     };
   }
 
-  template <typename A, typename B, typename C>
-  void rewriteCallComplexInputType(A ty, mlir::Value oper, B &newInTys,
-                                   C &newOpers, mlir::Value &savedStackPtr) {
+  void passArgumentOnStackOrWithNewType(
+      mlir::Location loc, fir::CodeGenSpecifics::TypeAndAttr newTypeAndAttr,
+      mlir::Type oldType, mlir::Value oper,
+      llvm::SmallVectorImpl<mlir::Value> &newOpers,
+      mlir::Value &savedStackPtr) {
+    auto resTy = std::get<mlir::Type>(newTypeAndAttr);
+    auto attr = std::get<fir::CodeGenSpecifics::Attributes>(newTypeAndAttr);
+    auto oldRefTy = fir::ReferenceType::get(oldType);
+    // We are going to generate an alloca, so save the stack pointer.
+    if (!savedStackPtr)
+      savedStackPtr = genStackSave(loc);
+    if (attr.isByVal()) {
+      mlir::Value mem = rewriter->create<fir::AllocaOp>(loc, oldType);
+      rewriter->create<fir::StoreOp>(loc, oper, mem);
+      if (mem.getType() != resTy)
+        mem = rewriter->create<fir::ConvertOp>(loc, resTy, mem);
+      newOpers.push_back(mem);
+    } else {
+      auto mem = rewriter->create<fir::AllocaOp>(loc, resTy);
+      auto cast = rewriter->create<fir::ConvertOp>(loc, oldRefTy, mem);
+      rewriter->create<fir::StoreOp>(loc, oper, cast);
+      newOpers.push_back(rewriter->create<fir::LoadOp>(loc, mem));
+    }
+  }
+
+  template <typename CPLX>
+  void rewriteCallComplexInputType(
+      mlir::Location loc, CPLX ty, mlir::Value oper,
+      fir::CodeGenSpecifics::Marshalling &newInTyAndAttrs,
+      llvm::SmallVectorImpl<mlir::Value> &newOpers,
+      mlir::Value &savedStackPtr) {
     if (noComplexConversion) {
-      newInTys.push_back(ty);
+      newInTyAndAttrs.push_back(fir::CodeGenSpecifics::getTypeAndAttr(ty));
       newOpers.push_back(oper);
       return;
     }
 
-    auto *ctx = ty.getContext();
-    mlir::Location loc = mlir::UnknownLoc::get(ctx);
-    if (auto *op = oper.getDefiningOp())
-      loc = op->getLoc();
     auto m = specifics->complexArgumentType(loc, ty.getElementType());
     if (m.size() == 1) {
       // COMPLEX is a single aggregate
-      auto resTy = std::get<mlir::Type>(m[0]);
-      auto attr = std::get<fir::CodeGenSpecifics::Attributes>(m[0]);
-      auto oldRefTy = fir::ReferenceType::get(ty);
-      // We are going to generate an alloca, so save the stack pointer.
-      if (!savedStackPtr)
-        savedStackPtr = genStackSave(loc);
-      if (attr.isByVal()) {
-        auto mem = rewriter->create<fir::AllocaOp>(loc, ty);
-        rewriter->create<fir::StoreOp>(loc, oper, mem);
-        newOpers.push_back(rewriter->create<fir::ConvertOp>(loc, resTy, mem));
-      } else {
-        auto mem = rewriter->create<fir::AllocaOp>(loc, resTy);
-        auto cast = rewriter->create<fir::ConvertOp>(loc, oldRefTy, mem);
-        rewriter->create<fir::StoreOp>(loc, oper, cast);
-        newOpers.push_back(rewriter->create<fir::LoadOp>(loc, mem));
-      }
-      newInTys.push_back(resTy);
+      passArgumentOnStackOrWithNewType(loc, m[0], ty, oper, newOpers,
+                                       savedStackPtr);
+      newInTyAndAttrs.push_back(m[0]);
     } else {
       assert(m.size() == 2);
       // COMPLEX is split into 2 separate arguments
@@ -214,12 +241,34 @@ public:
         auto idx = rewriter->getIntegerAttr(iTy, index);
         auto val = rewriter->create<fir::ExtractValueOp>(
             loc, ty, oper, rewriter->getArrayAttr(idx));
-        newInTys.push_back(ty);
+        newInTyAndAttrs.push_back(tup);
         newOpers.push_back(val);
       }
     }
   }
 
+  void rewriteCallStructInputType(
+      mlir::Location loc, fir::RecordType recTy, mlir::Value oper,
+      fir::CodeGenSpecifics::Marshalling &newInTyAndAttrs,
+      llvm::SmallVectorImpl<mlir::Value> &newOpers,
+      mlir::Value &savedStackPtr) {
+    auto structArgs =
+        specifics->structArgumentType(loc, recTy, newInTyAndAttrs);
+    if (structArgs.size() != 1)
+      TODO(loc, "splitting BIND(C), VALUE derived type into several arguments");
+    passArgumentOnStackOrWithNewType(loc, structArgs[0], recTy, oper, newOpers,
+                                     savedStackPtr);
+    structArgs.push_back(structArgs[0]);
+  }
+
+  static bool hasByValOrSRetArgs(
+      const fir::CodeGenSpecifics::Marshalling &newInTyAndAttrs) {
+    return llvm::any_of(newInTyAndAttrs, [](auto arg) {
+      const auto &attr = std::get<fir::CodeGenSpecifics::Attributes>(arg);
+      return attr.isByVal() || attr.isSRet();
+    });
+  }
+
   // Convert fir.call and fir.dispatch Ops.
   template <typename A>
   void convertCallOp(A callOp) {
@@ -227,7 +276,7 @@ public:
     auto loc = callOp.getLoc();
     rewriter->setInsertionPoint(callOp);
     llvm::SmallVector<mlir::Type> newResTys;
-    llvm::SmallVector<mlir::Type> newInTys;
+    fir::CodeGenSpecifics::Marshalling newInTyAndAttrs;
     llvm::SmallVector<mlir::Value> newOpers;
     mlir::Value savedStackPtr = nullptr;
 
@@ -236,7 +285,8 @@ public:
     int dropFront = 0;
     if constexpr (std::is_same_v<std::decay_t<A>, fir::CallOp>) {
       if (!callOp.getCallee()) {
-        newInTys.push_back(fnTy.getInput(0));
+        newInTyAndAttrs.push_back(
+            fir::CodeGenSpecifics::getTypeAndAttr(fnTy.getInput(0)));
         newOpers.push_back(callOp.getOperand(0));
         dropFront = 1;
       }
@@ -250,12 +300,14 @@ public:
       mlir::Type ty = fnTy.getResult(0);
       llvm::TypeSwitch<mlir::Type>(ty)
           .template Case<fir::ComplexType>([&](fir::ComplexType cmplx) {
-            wrap = rewriteCallComplexResultType(loc, cmplx, newResTys, newInTys,
-                                                newOpers, savedStackPtr);
+            wrap = rewriteCallComplexResultType(loc, cmplx, newResTys,
+                                                newInTyAndAttrs, newOpers,
+                                                savedStackPtr);
           })
           .template Case<mlir::ComplexType>([&](mlir::ComplexType cmplx) {
-            wrap = rewriteCallComplexResultType(loc, cmplx, newResTys, newInTys,
-                                                newOpers, savedStackPtr);
+            wrap = rewriteCallComplexResultType(loc, cmplx, newResTys,
+                                                newInTyAndAttrs, newOpers,
+                                                savedStackPtr);
           })
           .Default([&](mlir::Type ty) { newResTys.push_back(ty); });
     } else if (fnTy.getResults().size() > 1) {
@@ -276,7 +328,8 @@ public:
             bool sret;
             if constexpr (std::is_same_v<std::decay_t<A>, fir::CallOp>) {
               if (noCharacterConversion) {
-                newInTys.push_back(boxTy);
+                newInTyAndAttrs.push_back(
+                    fir::CodeGenSpecifics::getTypeAndAttr(boxTy));
                 newOpers.push_back(oper);
                 return;
               }
@@ -304,18 +357,22 @@ public:
                 trailingInTys.push_back(argTy);
                 trailingOpers.push_back(unbox.getResult(idx));
               } else {
-                newInTys.push_back(argTy);
+                newInTyAndAttrs.push_back(e.value());
                 newOpers.push_back(unbox.getResult(idx));
               }
             }
           })
           .template Case<fir::ComplexType>([&](fir::ComplexType cmplx) {
-            rewriteCallComplexInputType(cmplx, oper, newInTys, newOpers,
-                                        savedStackPtr);
+            rewriteCallComplexInputType(loc, cmplx, oper, newInTyAndAttrs,
+                                        newOpers, savedStackPtr);
           })
           .template Case<mlir::ComplexType>([&](mlir::ComplexType cmplx) {
-            rewriteCallComplexInputType(cmplx, oper, newInTys, newOpers,
-                                        savedStackPtr);
+            rewriteCallComplexInputType(loc, cmplx, oper, newInTyAndAttrs,
+                                        newOpers, savedStackPtr);
+          })
+          .template Case<fir::RecordType>([&](fir::RecordType recTy) {
+            rewriteCallStructInputType(loc, recTy, oper, newInTyAndAttrs,
+                                       newOpers, savedStackPtr);
           })
           .template Case<mlir::TupleType>([&](mlir::TupleType tuple) {
             if (fir::isCharacterProcedureTuple(tuple)) {
@@ -344,12 +401,14 @@ public:
               auto [funcPointer, len] =
                   fir::factory::extractCharacterProcedureTuple(builder, loc,
                                                                oper);
-              newInTys.push_back(funcPointerType);
+              newInTyAndAttrs.push_back(
+                  fir::CodeGenSpecifics::getTypeAndAttr(funcPointerType));
               newOpers.push_back(funcPointer);
               trailingInTys.push_back(lenType);
               trailingOpers.push_back(len);
             } else {
-              newInTys.push_back(tuple);
+              newInTyAndAttrs.push_back(
+                  fir::CodeGenSpecifics::getTypeAndAttr(tuple));
               newOpers.push_back(oper);
             }
           })
@@ -358,11 +417,15 @@ public:
               if (callOp.getPassArgPos() && *callOp.getPassArgPos() == index)
                 passArgShift = newOpers.size() - *callOp.getPassArgPos();
             }
-            newInTys.push_back(ty);
+            newInTyAndAttrs.push_back(
+                fir::CodeGenSpecifics::getTypeAndAttr(ty));
             newOpers.push_back(oper);
           });
     }
-    newInTys.insert(newInTys.end(), trailingInTys.begin(), trailingInTys.end());
+
+    llvm::SmallVector<mlir::Type> newInTypes = toTypeList(newInTyAndAttrs);
+    newInTypes.insert(newInTypes.end(), trailingInTys.begin(),
+                      trailingInTys.end());
     newOpers.insert(newOpers.end(), trailingOpers.begin(), trailingOpers.end());
 
     llvm::SmallVector<mlir::Value, 1> newCallResults;
@@ -372,10 +435,15 @@ public:
         newCall =
             rewriter->create<A>(loc, *callOp.getCallee(), newResTys, newOpers);
       } else {
-        // Force new type on the input operand.
+        // TODO: llvm dialect must be updated to propagate argument on
+        // attributes for indirect calls. See:
+        // https://discourse.llvm.org/t/should-llvm-callop-be-able-to-carry-argument-attributes-for-indirect-calls/75431
+        if (hasByValOrSRetArgs(newInTyAndAttrs))
+          TODO(loc,
+               "passing argument or result on the stack in indirect calls");
         newOpers[0].setType(mlir::FunctionType::get(
             callOp.getContext(),
-            mlir::TypeRange{newInTys}.drop_front(dropFront), newResTys));
+            mlir::TypeRange{newInTypes}.drop_front(dropFront), newResTys));
         newCall = rewriter->create<A>(loc, newResTys, newOpers);
       }
       LLVM_DEBUG(llvm::dbgs() << "replacing call with " << newCall << '\n');
@@ -419,47 +487,69 @@ public:
 
   // Result type fixup for fir::ComplexType and mlir::ComplexType
   template <typename A, typename B>
-  void lowerComplexSignatureRes(mlir::Location loc, A cmplx, B &newResTys,
-                                B &newInTys) {
+  void lowerComplexSignatureRes(
+      mlir::Location loc, A cmplx, B &newResTys,
+      fir::CodeGenSpecifics::Marshalling &newInTyAndAttrs) {
     if (noComplexConversion) {
       newResTys.push_back(cmplx);
-    } else {
-      for (auto &tup :
-           specifics->complexReturnType(loc, cmplx.getElementType())) {
-        auto argTy = std::get<mlir::Type>(tup);
-        if (std::get<fir::CodeGenSpecifics::Attributes>(tup).isSRet())
-          newInTys.push_back(argTy);
-        else
-          newResTys.push_back(argTy);
-      }
+      return;
+    }
+    for (auto &tup :
+         specifics->complexReturnType(loc, cmplx.getElementType())) {
+      auto argTy = std::get<mlir::Type>(tup);
+      if (std::get<fir::CodeGenSpecifics::Attributes>(tup).isSRet())
+        newInTyAndAttrs.push_back(tup);
+      else
+        newResTys.push_back(argTy);
     }
   }
 
   // Argument type fixup for fir::ComplexType and mlir::ComplexType
-  template <typename A, typename B>
-  void lowerComplexSignatureArg(mlir::Location loc, A cmplx, B &newInTys) {
-    if (noComplexConversion)
-      newInTys.push_back(cmplx);
-    else
-      for (auto &tup :
-           specifics->complexArgumentType(loc, cmplx.getElementType()))
-        newInTys.push_back(std::get<mlir::Type>(tup));
+  template <typename A>
+  void lowerComplexSignatureArg(
+      mlir::Location loc, A cmplx,
+      fir::CodeGenSpecifics::Marshalling &newInTyAndAttrs) {
+    if (noComplexConversion) {
+      newInTyAndAttrs.push_back(fir::CodeGenSpecifics::getTypeAndAttr(cmplx));
+    } else {
+      auto cplxArgs =
+          specifics->complexArgumentType(loc, cmplx.getElementType());
+      newInTyAndAttrs.insert(newInTyAndAttrs.end(), cplxArgs.begin(),
+                             cplxArgs.end());
+    }
+  }
+
+  void
+  lowerStructSignatureArg(mlir::Location loc, fir::RecordType recTy,
+                          fir::CodeGenSpecifics::Marshalling &newInTyAndAttrs) {
+    auto structArgs =
+        specifics->structArgumentType(loc, recTy, newInTyAndAttrs);
+    newInTyAndAttrs.insert(newInTyAndAttrs.end(), structArgs.begin(),
+                           structArgs.end());
+  }
+
+  llvm::SmallVector<mlir::Type>
+  toTypeList(const fir::CodeGenSpecifics::Marshalling &marshalled) {
+    llvm::SmallVector<mlir::Type> typeList;
+    for (auto &typeAndAttr : marshalled)
+      typeList.emplace_back(std::get<mlir::Type>(typeAndAttr));
+    return typeList;
   }
 
   /// Taking the address of a function. Modify the signature as needed.
   void convertAddrOp(fir::AddrOfOp addrOp) {
     rewriter->setInsertionPoint(addrOp);
     auto addrTy = addrOp.getType().cast<mlir::FunctionType>();
+    fir::CodeGenSpecifics::Marshalling newInTyAndAttrs;
     llvm::SmallVector<mlir::Type> newResTys;
-    llvm::SmallVector<mlir::Type> newInTys;
     auto loc = addrOp.getLoc();
     for (mlir::Type ty : addrTy.getResults()) {
       llvm::TypeSwitch<mlir::Type>(ty)
           .Case<fir::ComplexType>([&](fir::ComplexType ty) {
-            lowerComplexSignatureRes(loc, ty, newResTys, newInTys);
+            lowerComplexSignatureRes(loc, ty, newResTys, newInTyAndAttrs);
           })
           .Case<mlir::ComplexType>([&](mlir::ComplexType ty) {
-            lowerComplexSignatureRes(loc, ty, newResTys, newInTys);
+            lowerComplexSignatureRes(loc, ty, newResTys, newInTyAndAttrs);
           })
           .Default([&](mlir::Type ty) { newResTys.push_back(ty); });
     }
@@ -468,37 +558,49 @@ public:
       llvm::TypeSwitch<mlir::Type>(ty)
           .Case<fir::BoxCharType>([&](auto box) {
             if (noCharacterConversion) {
-              newInTys.push_back(box);
+              newInTyAndAttrs.push_back(
+                  fir::CodeGenSpecifics::getTypeAndAttr(box));
             } else {
               for (auto &tup : specifics->boxcharArgumentType(box.getEleTy())) {
                 auto attr = std::get<fir::CodeGenSpecifics::Attributes>(tup);
                 auto argTy = std::get<mlir::Type>(tup);
-                llvm::SmallVector<mlir::Type> &vec =
-                    attr.isAppend() ? trailingInTys : newInTys;
-                vec.push_back(argTy);
+                if (attr.isAppend())
+                  trailingInTys.push_back(argTy);
+                else
+                  newInTyAndAttrs.push_back(tup);
               }
             }
           })
           .Case<fir::ComplexType>([&](fir::ComplexType ty) {
-            lowerComplexSignatureArg(loc, ty, newInTys);
+            lowerComplexSignatureArg(loc, ty, newInTyAndAttrs);
           })
           .Case<mlir::ComplexType>([&](mlir::ComplexType ty) {
-            lowerComplexSignatureArg(loc, ty, newInTys);
+            lowerComplexSignatureArg(loc, ty, newInTyAndAttrs);
           })
           .Case<mlir::TupleType>([&](mlir::TupleType tuple) {
             if (fir::isCharacterProcedureTuple(tuple)) {
-              newInTys.push_back(tuple.getType(0));
+              newInTyAndAttrs.push_back(
+                  fir::CodeGenSpecifics::getTypeAndAttr(tuple.getType(0)));
               trailingInTys.push_back(tuple.getType(1));
             } else {
-              newInTys.push_back(ty);
+              newInTyAndAttrs.push_back(
+                  fir::CodeGenSpecifics::getTypeAndAttr(ty));
             }
           })
-          .Default([&](mlir::Type ty) { newInTys.push_back(ty); });
+          .template Case<fir::RecordType>([&](fir::RecordType recTy) {
+            lowerStructSignatureArg(loc, recTy, newInTyAndAttrs);
+          })
+          .Default([&](mlir::Type ty) {
+            newInTyAndAttrs.push_back(
+                fir::CodeGenSpecifics::getTypeAndAttr(ty));
+          });
     }
+    llvm::SmallVector<mlir::Type> newInTypes = toTypeList(newInTyAndAttrs);
     // append trailing input types
-    newInTys.insert(newInTys.end(), trailingInTys.begin(), trailingInTys.end());
+    newInTypes.insert(newInTypes.end(), trailingInTys.begin(),
+                      trailingInTys.end());
     // replace this op with a new one with the updated signature
-    auto newTy = rewriter->getFunctionType(newInTys, newResTys);
+    auto newTy = rewriter->getFunctionType(newInTypes, newResTys);
     auto newOp = rewriter->create<fir::AddrOfOp>(addrOp.getLoc(), newTy,
                                                  addrOp.getSymbol());
     replaceOp(addrOp, newOp.getResult());
@@ -542,7 +644,8 @@ public:
       if (((ty.isa<fir::BoxCharType>() || fir::isCharacterProcedureTuple(ty)) &&
            !noCharacterConversion) ||
           (fir::isa_complex(ty) && !noComplexConversion) ||
-          (ty.isa<mlir::IntegerType>() && hasCCallingConv)) {
+          (ty.isa<mlir::IntegerType>() && hasCCallingConv) ||
+          ty.isa<fir::RecordType>()) {
         LLVM_DEBUG(llvm::dbgs() << "rewrite " << signature << " for target\n");
         return false;
       }
@@ -566,7 +669,7 @@ public:
     if (hasPortableSignature(funcTy, func) && !hasHostAssociations(func))
       return;
     llvm::SmallVector<mlir::Type> newResTys;
-    llvm::SmallVector<mlir::Type> newInTys;
+    fir::CodeGenSpecifics::Marshalling newInTyAndAttrs;
     llvm::SmallVector<std::pair<unsigned, mlir::NamedAttribute>> savedAttrs;
     llvm::SmallVector<std::pair<unsigned, mlir::NamedAttribute>> extraAttrs;
     llvm::SmallVector<FixupTy> fixups;
@@ -590,13 +693,13 @@ public:
             if (noComplexConversion)
               newResTys.push_back(cmplx);
             else
-              doComplexReturn(func, cmplx, newResTys, newInTys, fixups);
+              doComplexReturn(func, cmplx, newResTys, newInTyAndAttrs, fixups);
           })
           .Case<mlir::ComplexType>([&](mlir::ComplexType cmplx) {
             if (noComplexConversion)
               newResTys.push_back(cmplx);
             else
-              doComplexReturn(func, cmplx, newResTys, newInTys, fixups);
+              doComplexReturn(func, cmplx, newResTys, newInTyAndAttrs, fixups);
           })
           .Case<mlir::IntegerType>([&](mlir::IntegerType intTy) {
             auto m = specifics->integerArgumentType(func.getLoc(), intTy);
@@ -616,7 +719,7 @@ public:
 
     // Saved potential shift in argument. Handling of result can add arguments
     // at the beginning of the function signature.
-    unsigned argumentShift = newInTys.size();
+    unsigned argumentShift = newInTyAndAttrs.size();
 
     // Convert arguments
     llvm::SmallVector<mlir::Type> trailingTys;
@@ -626,7 +729,8 @@ public:
       llvm::TypeSwitch<mlir::Type>(ty)
           .Case<fir::BoxCharType>([&](fir::BoxCharType boxTy) {
             if (noCharacterConversion) {
-              newInTys.push_back(boxTy);
+              newInTyAndAttrs.push_back(
+                  fir::CodeGenSpecifics::getTypeAndAttr(boxTy));
             } else {
               // Convert a CHARACTER argument type. This can involve separating
               // the pointer and the LEN into two arguments and moving the LEN
@@ -643,44 +747,40 @@ public:
                 } else {
                   if (sret) {
                     fixups.emplace_back(FixupTy::Codes::CharPair,
-                                        newInTys.size(), index);
+                                        newInTyAndAttrs.size(), index);
                   } else {
                     fixups.emplace_back(FixupTy::Codes::Trailing,
-                                        newInTys.size(), trailingTys.size());
+                                        newInTyAndAttrs.size(),
+                                        trailingTys.size());
                   }
-                  newInTys.push_back(argTy);
+                  newInTyAndAttrs.push_back(tup);
                 }
               }
             }
           })
           .Case<fir::ComplexType>([&](fir::ComplexType cmplx) {
-            if (noComplexConversion)
-              newInTys.push_back(cmplx);
-            else
-              doComplexArg(func, cmplx, newInTys, fixups);
+            doComplexArg(func, cmplx, newInTyAndAttrs, fixups);
           })
           .Case<mlir::ComplexType>([&](mlir::ComplexType cmplx) {
-            if (noComplexConversion)
-              newInTys.push_back(cmplx);
-            else
-              doComplexArg(func, cmplx, newInTys, fixups);
+            doComplexArg(func, cmplx, newInTyAndAttrs, fixups);
           })
           .Case<mlir::TupleType>([&](mlir::TupleType tuple) {
             if (fir::isCharacterProcedureTuple(tuple)) {
               fixups.emplace_back(FixupTy::Codes::TrailingCharProc,
-                                  newInTys.size(), trailingTys.size());
-              newInTys.push_back(tuple.getType(0));
+                                  newInTyAndAttrs.size(), trailingTys.size());
+              newInTyAndAttrs.push_back(
+                  fir::CodeGenSpecifics::getTypeAndAttr(tuple.getType(0)));
               trailingTys.push_back(tuple.getType(1));
             } else {
-              newInTys.push_back(ty);
+              newInTyAndAttrs.push_back(
+                  fir::CodeGenSpecifics::getTypeAndAttr(ty));
             }
           })
           .Case<mlir::IntegerType>([&](mlir::IntegerType intTy) {
             auto m = specifics->integerArgumentType(func.getLoc(), intTy);
             assert(m.size() == 1);
             auto attr = std::get<fir::CodeGenSpecifics::Attributes>(m[0]);
-            auto argTy = std::get<mlir::Type>(m[0]);
-            auto argNo = newInTys.size();
+            auto argNo = newInTyAndAttrs.size();
             llvm::StringRef extensionAttrName = attr.getIntExtensionAttrName();
             if (!extensionAttrName.empty() &&
                 isFuncWithCCallingConvention(func))
@@ -691,14 +791,20 @@ public:
                                         mlir::UnitAttr::get(func.getContext()));
                                   });
 
-            newInTys.push_back(argTy);
+            newInTyAndAttrs.push_back(m[0]);
+          })
+          .template Case<fir::RecordType>([&](fir::RecordType recTy) {
+            doStructArg(func, recTy, newInTyAndAttrs, fixups);
           })
-          .Default([&](mlir::Type ty) { newInTys.push_back(ty); });
+          .Default([&](mlir::Type ty) {
+            newInTyAndAttrs.push_back(
+                fir::CodeGenSpecifics::getTypeAndAttr(ty));
+          });
 
       if (func.getArgAttrOfType<mlir::UnitAttr>(index,
                                                 fir::getHostAssocAttrName())) {
         extraAttrs.push_back(
-            {newInTys.size() - 1,
+            {newInTyAndAttrs.size() - 1,
              rewriter->getNamedAttr("llvm.nest", rewriter->getUnitAttr())});
       }
     }
@@ -712,12 +818,16 @@ public:
       int offset = 0;
       for (std::remove_const_t<decltype(fixupSize)> i = 0; i < fixupSize; ++i) {
         const auto &fixup = fixups[i];
+        mlir::Type fixupType =
+            fixup.index < newInTyAndAttrs.size()
+                ? std::get<mlir::Type>(newInTyAndAttrs[fixup.index])
+                : mlir::Type{};
         switch (fixup.code) {
         case FixupTy::Codes::ArgumentAsLoad: {
           // Argument was pass-by-value, but is now pass-by-reference and
           // possibly with a different element type.
-          auto newArg = func.front().insertArgument(fixup.index,
-                                                    newInTys[fixup.index], loc);
+          auto newArg =
+              func.front().insertArgument(fixup.index, fixupType, loc);
           rewriter->setInsertionPointToStart(&func.front());
           auto oldArgTy =
               fir::ReferenceType::get(oldArgTys[fixup.index - offset]);
@@ -732,14 +842,13 @@ public:
           auto oldArgTy =
               fir::ReferenceType::get(oldArgTys[fixup.index - offset]);
           // If type did not change, keep the original argument.
-          if (newInTys[fixup.index] == oldArgTy)
+          if (fixupType == oldArgTy)
             break;
 
-          auto newArg = func.front().insertArgument(fixup.index,
-                                                    newInTys[fixup.index], loc);
+          auto newArg =
+              func.front().insertArgument(fixup.index, fixupType, loc);
           rewriter->setInsertionPointToStart(&func.front());
-          auto mem =
-              rewriter->create<fir::AllocaOp>(loc, newInTys[fixup.index]);
+          auto mem = rewriter->create<fir::AllocaOp>(loc, fixupType);
           rewriter->create<fir::StoreOp>(loc, newArg, mem);
           auto cast = rewriter->create<fir::ConvertOp>(loc, oldArgTy, mem);
           mlir::Value load = rewriter->create<fir::LoadOp>(loc, cast);
@@ -753,8 +862,8 @@ public:
         case FixupTy::Codes::CharPair: {
           // The FIR boxchar argument has been split into a pair of distinct
           // arguments that are in juxtaposition to each other.
-          auto newArg = func.front().insertArgument(fixup.index,
-                                                    newInTys[fixup.index], loc);
+          auto newArg =
+              func.front().insertArgument(fixup.index, fixupType, loc);
           if (fixup.second == 1) {
             rewriter->setInsertionPointToStart(&func.front());
             auto boxTy = oldArgTys[fixup.index - offset - fixup.second];
@@ -768,8 +877,8 @@ public:
         case FixupTy::Codes::ReturnAsStore: {
           // The value being returned is now being returned in memory (callee
           // stack space) through a hidden reference argument.
-          auto newArg = func.front().insertArgument(fixup.index,
-                                                    newInTys[fixup.index], loc);
+          auto newArg =
+              func.front().insertArgument(fixup.index, fixupType, loc);
           offset++;
           func.walk([&](mlir::func::ReturnOp ret) {
             rewriter->setInsertionPoint(ret);
@@ -801,8 +910,8 @@ public:
         case FixupTy::Codes::Split: {
           // The FIR argument has been split into a pair of distinct arguments
           // that are in juxtaposition to each other. (For COMPLEX value.)
-          auto newArg = func.front().insertArgument(fixup.index,
-                                                    newInTys[fixup.index], loc);
+          auto newArg =
+              func.front().insertArgument(fixup.index, fixupType, loc);
           if (fixup.second == 1) {
             rewriter->setInsertionPointToStart(&func.front());
             auto cplxTy = oldArgTys[fixup.index - offset - fixup.second];
@@ -825,8 +934,8 @@ public:
           // The first part of the pair appears in the original argument
           // position. The second part of the pair is appended after all the
           // original arguments. (Boxchar arguments.)
-          auto newBufArg = func.front().insertArgument(
-              fixup.index, newInTys[fixup.index], loc);
+          auto newBufArg =
+              func.front().insertArgument(fixup.index, fixupType, loc);
           auto newLenArg =
               func.front().addArgument(trailingTys[fixup.second], loc);
           auto boxTy = oldArgTys[fixup.index - offset];
@@ -841,8 +950,8 @@ public:
           // pair of distinct arguments. The first part of the pair appears in
           // the original argument position. The second part of the pair is
           // appended after all the original arguments.
-          auto newProcPointerArg = func.front().insertArgument(
-              fixup.index, newInTys[fixup.index], loc);
+          auto newProcPointerArg =
+              func.front().insertArgument(fixup.index, fixupType, loc);
           auto newLenArg =
               func.front().addArgument(trailingTys[fixup.second], loc);
           auto tupleType = oldArgTys[fixup.index - offset];
@@ -857,10 +966,11 @@ public:
       }
     }
 
+    llvm::SmallVector<mlir::Type> newInTypes = toTypeList(newInTyAndAttrs);
     // Set the new type and finalize the arguments, etc.
-    newInTys.insert(newInTys.end(), trailingTys.begin(), trailingTys.end());
+    newInTypes.insert(newInTypes.end(), trailingTys.begin(), trailingTys.end());
     auto newFuncTy =
-        mlir::FunctionType::get(func.getContext(), newInTys, newResTys);
+        mlir::FunctionType::get(func.getContext(), newInTypes, newResTys);
     LLVM_DEBUG(llvm::dbgs() << "new func: " << newFuncTy << '\n');
     func.setType(newFuncTy);
 
@@ -899,7 +1009,8 @@ public:
   /// GPR.
   template <typename A, typename B, typename C>
   void doComplexReturn(mlir::func::FuncOp func, A cmplx, B &newResTys,
-                       B &newInTys, C &fixups) {
+                       fir::CodeGenSpecifics::Marshalling &newInTyAndAttrs,
+                       C &fixups) {
     if (noComplexConversion) {
       newResTys.push_back(cmplx);
       return;
@@ -911,7 +1022,7 @@ public:
     auto attr = std::get<fir::CodeGenSpecifics::Attributes>(tup);
     auto argTy = std::get<mlir::Type>(tup);
     if (attr.isSRet()) {
-      unsigned argNo = newInTys.size();
+      unsigned argNo = newInTyAndAttrs.size();
       if (auto align = attr.getAlignment())
         fixups.emplace_back(
             FixupTy::Codes::ReturnAsStore, argNo, [=](mlir::func::FuncOp func) {
@@ -931,42 +1042,35 @@ public:
                               func.setArgAttr(argNo, "llvm.sret",
                                               mlir::TypeAttr::get(elemType));
                             });
-      newInTys.push_back(argTy);
+      newInTyAndAttrs.push_back(tup);
       return;
-    } else {
-      if (auto align = attr.getAlignment())
-        fixups.emplace_back(FixupTy::Codes::ReturnType, newResTys.size(),
-                            [=](mlir::func::FuncOp func) {
-                              func.setArgAttr(
-                                  newResTys.size(), "llvm.align",
-                                  rewriter->getIntegerAttr(
-                                      rewriter->getIntegerType(32), align));
-                            });
-      else
-        fixups.emplace_back(FixupTy::Codes::ReturnType, newResTys.size());
     }
+    if (auto align = attr.getAlignment())
+      fixups.emplace_back(
+          FixupTy::Codes::ReturnType, newResTys.size(),
+          [=](mlir::func::FuncOp func) {
+            func.setArgAttr(
+                newResTys.size(), "llvm.align",
+                rewriter->getIntegerAttr(rewriter->getIntegerType(32), align));
+          });
+    else
+      fixups.emplace_back(FixupTy::Codes::ReturnType, newResTys.size());
     newResTys.push_back(argTy);
   }
 
-  /// Convert a complex argument value. This can involve storing the value to
-  /// a temporary memory location or factoring the value into two distinct
-  /// arguments.
-  template <typename A, typename B, typename C>
-  void doComplexArg(mlir::func::FuncOp func, A cmplx, B &newInTys, C &fixups) {
-    if (noComplexConversion) {
-      newInTys.push_back(cmplx);
-      return;
-    }
-    auto m =
-        specifics->complexArgumentType(func.getLoc(), cmplx.getElementType());
-    const auto fixupCode =
-        m.size() > 1 ? FixupTy::Codes::Split : FixupTy::Codes::ArgumentType;
-    for (auto e : llvm::enumerate(m)) {
+  template <typename FIXUPS>
+  void
+  createFuncOpArgFixups(mlir::func::FuncOp func,
+                        fir::CodeGenSpecifics::Marshalling &newInTyAndAttrs,
+                        fir::CodeGenSpecifics::Marshalling &argsInTys,
+                        FIXUPS &fixups) {
+    const auto fixupCode = argsInTys.size() > 1 ? FixupTy::Codes::Split
+                                                : FixupTy::Codes::ArgumentType;
+    for (auto e : llvm::enumerate(argsInTys)) {
       auto &tup = e.value();
       auto index = e.index();
       auto attr = std::get<fir::CodeGenSpecifics::Attributes>(tup);
-      auto argTy = std::get<mlir::Type>(tup);
-      auto argNo = newInTys.size();
+      auto argNo = newInTyAndAttrs.size();
       if (attr.isByVal()) {
         if (auto align = attr.getAlignment())
           fixups.emplace_back(FixupTy::Codes::ArgumentAsLoad, argNo,
@@ -981,7 +1085,8 @@ public:
                                         rewriter->getIntegerType(32), align));
                               });
         else
-          fixups.emplace_back(FixupTy::Codes::ArgumentAsLoad, newInTys.size(),
+          fixups.emplace_back(FixupTy::Codes::ArgumentAsLoad,
+                              newInTyAndAttrs.size(),
                               [=](mlir::func::FuncOp func) {
                                 auto elemType = fir::dyn_cast_ptrOrBoxEleTy(
                                     func.getFunctionType().getInput(argNo));
@@ -999,8 +1104,33 @@ public:
         else
           fixups.emplace_back(fixupCode, argNo, index);
       }
-      newInTys.push_back(argTy);
+      newInTyAndAttrs.push_back(tup);
+    }
+  }
+
+  /// Convert a complex argument value. This can involve storing the value to
+  /// a temporary memory location or factoring the value into two distinct
+  /// arguments.
+  template <typename A, typename B>
+  void doComplexArg(mlir::func::FuncOp func, A cmplx,
+                    fir::CodeGenSpecifics::Marshalling &newInTyAndAttrs,
+                    B &fixups) {
+    if (noComplexConversion) {
+      newInTyAndAttrs.push_back(fir::CodeGenSpecifics::getTypeAndAttr(cmplx));
+      return;
     }
+    auto cplxArgs =
+        specifics->complexArgumentType(func.getLoc(), cmplx.getElementType());
+    createFuncOpArgFixups(func, newInTyAndAttrs, cplxArgs, fixups);
+  }
+
+  template <typename FIXUPS>
+  void doStructArg(mlir::func::FuncOp func, fir::RecordType recTy,
+                   fir::CodeGenSpecifics::Marshalling &newInTyAndAttrs,
+                   FIXUPS &fixups) {
+    auto structArgs =
+        specifics->structArgumentType(func.getLoc(), recTy, newInTyAndAttrs);
+    createFuncOpArgFixups(func, newInTyAndAttrs, structArgs, fixups);
   }
 
 private:
@@ -1011,12 +1141,14 @@ private:
     op->erase();
   }
 
-  inline void setMembers(fir::CodeGenSpecifics *s, mlir::OpBuilder *r) {
+  inline void setMembers(fir::CodeGenSpecifics *s, mlir::OpBuilder *r,
+                         mlir::DataLayout *dl) {
     specifics = s;
     rewriter = r;
+    dataLayout = dl;
   }
 
-  inline void clearMembers() { setMembers(nullptr, nullptr); }
+  inline void clearMembers() { setMembers(nullptr, nullptr, nullptr); }
 
   // Inserts a call to llvm.stacksave at the current insertion
   // point and the given location. Returns the call's result Value.
@@ -1032,9 +1164,10 @@ private:
 
   fir::CodeGenSpecifics *specifics = nullptr;
   mlir::OpBuilder *rewriter = nullptr;
+  mlir::DataLayout *dataLayout = nullptr;
   mlir::func::FuncOp stackSaveFn = nullptr;
   mlir::func::FuncOp stackRestoreFn = nullptr;
-}; // namespace
+};
 } // namespace
 
 std::unique_ptr<mlir::OperationPass<mlir::ModuleOp>>
diff --git a/flang/lib/Optimizer/CodeGen/TypeConverter.cpp b/flang/lib/Optimizer/CodeGen/TypeConverter.cpp
index 1d48592ec6ac..209c586411f4 100644
--- a/flang/lib/Optimizer/CodeGen/TypeConverter.cpp
+++ b/flang/lib/Optimizer/CodeGen/TypeConverter.cpp
@@ -27,12 +27,13 @@
 namespace fir {
 
 LLVMTypeConverter::LLVMTypeConverter(mlir::ModuleOp module, bool applyTBAA,
-                                     bool forceUnifiedTBAATree)
+                                     bool forceUnifiedTBAATree,
+                                     const mlir::DataLayout &dl)
     : mlir::LLVMTypeConverter(module.getContext()),
       kindMapping(getKindMapping(module)),
       specifics(CodeGenSpecifics::get(module.getContext(),
                                       getTargetTriple(module),
-                                      getKindMapping(module))),
+                                      getKindMapping(module), dl)),
       tbaaBuilder(std::make_unique<TBAABuilder>(module->getContext(), applyTBAA,
                                                 forceUnifiedTBAATree)) {
   LLVM_DEBUG(llvm::dbgs() << "FIR type converter\n");
diff --git a/flang/lib/Optimizer/Dialect/FIRType.cpp b/flang/lib/Optimizer/Dialect/FIRType.cpp
index 730317a9bc23..d0c7bae674b6 100644
--- a/flang/lib/Optimizer/Dialect/FIRType.cpp
+++ b/flang/lib/Optimizer/Dialect/FIRType.cpp
@@ -849,6 +849,12 @@ fir::RealType::verify(llvm::function_ref<mlir::InFlightDiagnostic()> emitError,
   return mlir::success();
 }
 
+mlir::Type fir::RealType::getFloatType(const fir::KindMapping &kindMap) const {
+  auto fkind = getFKind();
+  auto realTypeID = kindMap.getRealTypeID(fkind);
+  return fir::fromRealTypeID(getContext(), realTypeID, fkind);
+}
+
 //===----------------------------------------------------------------------===//
 // RecordType
 //===----------------------------------------------------------------------===//
diff --git a/flang/lib/Optimizer/Support/DataLayout.cpp b/flang/lib/Optimizer/Support/DataLayout.cpp
index 5cd9c01e8ce0..93a3b92d0810 100644
--- a/flang/lib/Optimizer/Support/DataLayout.cpp
+++ b/flang/lib/Optimizer/Support/DataLayout.cpp
@@ -45,3 +45,16 @@ void fir::support::setMLIRDataLayoutFromAttributes(mlir::ModuleOp mlirModule,
   llvm::DataLayout llvmDataLayout("");
   fir::support::setMLIRDataLayout(mlirModule, llvmDataLayout);
 }
+
+std::optional<mlir::DataLayout>
+fir::support::getOrSetDataLayout(mlir::ModuleOp mlirModule,
+                                 bool allowDefaultLayout) {
+  if (!mlirModule.getDataLayoutSpec()) {
+    fir::support::setMLIRDataLayoutFromAttributes(mlirModule,
+                                                  allowDefaultLayout);
+    if (!mlirModule.getDataLayoutSpec()) {
+      return std::nullopt;
+    }
+  }
+  return mlir::DataLayout(mlirModule);
+}
diff --git a/flang/test/Fir/recursive-type-tco.fir b/flang/test/Fir/recursive-type-tco.fir
index 9933f727af12..6fd222f26547 100644
--- a/flang/test/Fir/recursive-type-tco.fir
+++ b/flang/test/Fir/recursive-type-tco.fir
@@ -5,7 +5,7 @@
 // CHECK-LABEL: %t = type { ptr }
 !t = !fir.type<t {p : !fir.ptr<!fir.type<t>>}>
 
-// CHECK-LABEL: @a(%t %{{.*}})
-func.func @a(%a : !t) {
+// CHECK-LABEL: @a({ %t } %{{.*}})
+func.func @a(%a : tuple<!t>) {
   return
 }
diff --git a/flang/test/Fir/struct-passing-x86-64-byval.fir b/flang/test/Fir/struct-passing-x86-64-byval.fir
new file mode 100644
index 000000000000..eec21cbdf230
--- /dev/null
+++ b/flang/test/Fir/struct-passing-x86-64-byval.fir
@@ -0,0 +1,107 @@
+// Test X86-64 ABI rewrite of struct passed by value (BIND(C), VALUE derived types).
+// This test test cases where the struct must be passed on the stack according
+// to the System V ABI.
+// REQUIRES: x86-registered-target
+// RUN: tco --target=x86_64-unknown-linux-gnu %s | FileCheck %s
+
+module attributes {fir.defaultkind = "a1c4d8i4l4r4", fir.kindmap = "", llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-unknown-linux-gnu"} {
+
+func.func @takes_toobig(%arg0: !fir.type<toobig{i:!fir.array<5xi32>}>) {
+  return
+}
+func.func @takes_toobig_align16(%arg0: !fir.type<toobig_align16{i:i128,j:i8}>) {
+  return
+}
+func.func @not_enough_int_reg_1(%arg0: i32, %arg1: i32, %arg2: i32, %arg3: i32, %arg4: i32, %arg5: i32, %arg6: !fir.type<fits_in_1_int_reg{i:i32,j:i32}>) {
+  return
+}
+func.func @not_enough_int_reg_1b(%arg0: !fir.ref<i32>, %arg1: !fir.ref<i32>, %arg2: !fir.ref<i32>, %arg3: !fir.ref<i32>, %arg4: !fir.ref<i32>, %arg5: !fir.ref<i32>, %arg6: !fir.type<fits_in_1_int_reg{i:i32,j:i32}>) {
+  return
+}
+func.func @not_enough_int_reg_2(%arg0: i32, %arg1: i32, %arg2: i32, %arg3: i32, %arg4: i32, %arg5: !fir.type<fits_in_2_int_reg{i:i64,j:i64}>) {
+  return
+}
+func.func @ftakes_toobig(%arg0: !fir.type<ftoobig{i:!fir.array<5xf32>}>) {
+  return
+}
+func.func @ftakes_toobig_align16(%arg0: !fir.type<ftoobig_align16{i:f128,j:f32}>) {
+  return
+}
+func.func @not_enough_sse_reg_1(%arg0: f32, %arg1: f32, %arg2: f32, %arg3: f32, %arg4: f32, %arg5: f32, %arg6: f32, %arg7: f32, %arg8: !fir.type<fits_in_1_sse_reg{i:f32,j:f32}>) {
+  return
+}
+func.func @not_enough_sse_reg_1b(%arg0: !fir.complex<4>, %arg1: !fir.complex<4>, %arg2: !fir.complex<4>, %arg3: !fir.complex<4>, %arg4: !fir.complex<4>, %arg5: !fir.complex<4>, %arg6: !fir.complex<4>, %arg7: !fir.complex<4>, %arg8: !fir.type<fits_in_1_sse_reg{i:f32,j:f32}>) {
+  return
+}
+func.func @not_enough_sse_reg_1c(%arg0: !fir.complex<8>, %arg1: !fir.complex<8>, %arg2: !fir.complex<8>, %arg3: !fir.complex<8>, %arg4: !fir.type<fits_in_1_sse_reg{i:f32,j:f32}>) {
+  return
+}
+func.func @not_enough_sse_reg_2(%arg0: f32, %arg1: f32, %arg2: f32, %arg3: f32, %arg4: f32, %arg5: f32, %arg6: f32, %arg7: !fir.type<fits_in_2_sse_reg{i:f64,j:f64}>) {
+  return
+}
+func.func @test_contains_x87(%arg0: !fir.type<contains_x87{i:f80}>) {
+  return
+}
+func.func @test_contains_complex_x87(%arg0: !fir.type<contains_complex_x87{i:!fir.complex<10>}>) {
+  return
+}
+func.func @test_nested_toobig(%arg0: !fir.type<nested_toobig{x:!fir.array<3x!fir.type<fits_in_1_int_reg{i:i32,j:i32}>>}>) {
+  return
+}
+func.func @test_badly_aligned(%arg0: !fir.type<badly_aligned{x:f32,y:f64,z:f32}>) {
+  return
+}
+func.func @test_logical_toobig(%arg0: !fir.type<logical_too_big{l:!fir.array<17x!fir.logical<1>>}>) {
+  return
+}
+func.func @l_not_enough_int_reg(%arg0: i32, %arg1: i32, %arg2: i32, %arg3: i32, %arg4: i32, %arg5: !fir.type<l_fits_in_2_int_reg{l:!fir.array<4x!fir.logical<4>>}>) {
+  return
+}
+func.func @test_complex_toobig(%arg0: !fir.type<complex_too_big{c:!fir.array<2x!fir.complex<8>>}>) {
+  return
+}
+func.func @cplx_not_enough_sse_reg_1(%arg0: f32, %arg1: f32, %arg2: f32, %arg3: f32, %arg4: f32, %arg5: f32, %arg6: f32, %arg7: f32, %arg8: !fir.type<cplx_fits_in_1_sse_reg{c:!fir.complex<4>}>) {
+  return
+}
+func.func @test_char_to_big(%arg0: !fir.type<char_too_big{c:!fir.array<17x!fir.char<1>>}>) {
+  return
+}
+func.func @char_not_enough_int_reg_1(%arg0: i32, %arg1: i32, %arg2: i32, %arg3: i32, %arg4: i32, %arg5: i32, %arg6: !fir.type<char_fits_in_1_int_reg{c:!fir.array<8x!fir.char<1>>}>) {
+  return
+}
+func.func @mix_not_enough_int_reg_1(%arg0: i32, %arg1: i32, %arg2: i32, %arg3: i32, %arg4: i32, %arg5: i32, %arg6: !fir.type<mix_in_1_int_reg{x:f32,i:i32}>) {
+  return
+}
+func.func @mix_not_enough_sse_reg_2(%arg0: f32, %arg1: f32, %arg2: f32, %arg3: f32, %arg4: f32, %arg5: f32, %arg6: f32, %arg7: f32, %arg8: !fir.type<mix_in_1_int_reg_1_sse_reg{i:!fir.array<2xi32>,x:!fir.array<2xf32>}>) {
+  return
+}
+func.func @not_enough_int_reg_3(%arg0: i32, %arg1: i32, %arg2: i32, %arg3: i32, %arg4: i32, %arg6: !fir.type<fits_in_1_int_reg{i:i32,j:i32}>) -> !fir.complex<16> {
+  %0 = fir.zero_bits !fir.complex<16> 
+  return %0 : !fir.complex<16>
+}
+}
+
+// CHECK: define void @takes_toobig(ptr byval(%toobig) align 8 %{{.*}}) {
+// CHECK: define void @takes_toobig_align16(ptr byval(%toobig_align16) align 16 %{{.*}}) {
+// CHECK: define void @not_enough_int_reg_1(i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, ptr byval(%fits_in_1_int_reg) align 8 %{{.*}}) {
+// CHECK: define void @not_enough_int_reg_1b(ptr %{{.*}}, ptr %{{.*}}, ptr %{{.*}}, ptr %{{.*}}, ptr %{{.*}}, ptr %{{.*}}, ptr byval(%fits_in_1_int_reg) align 8 %{{.*}}) {
+// CHECK: define void @not_enough_int_reg_2(i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, ptr byval(%fits_in_2_int_reg) align 8 %{{.*}}) {
+// CHECK: define void @ftakes_toobig(ptr byval(%ftoobig) align 8 %{{.*}}) {
+// CHECK: define void @ftakes_toobig_align16(ptr byval(%ftoobig_align16) align 16 %{{.*}}) {
+// CHECK: define void @not_enough_sse_reg_1(float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, ptr byval(%fits_in_1_sse_reg) align 8 %{{.*}}) {
+// CHECK: define void @not_enough_sse_reg_1b(<2 x float> %{{.*}}, <2 x float> %{{.*}}, <2 x float> %{{.*}}, <2 x float> %{{.*}}, <2 x float> %{{.*}}, <2 x float> %{{.*}}, <2 x float> %{{.*}}, <2 x float> %{{.*}}, ptr byval(%fits_in_1_sse_reg) align 8 %{{.*}}) {
+// CHECK: define void @not_enough_sse_reg_1c(double %{{.*}}, double %{{.*}}, double %{{.*}}, double %{{.*}}, double %{{.*}}, double %{{.*}}, double %{{.*}}, double %{{.*}}, ptr byval(%fits_in_1_sse_reg) align 8 %{{.*}}) {
+// CHECK: define void @not_enough_sse_reg_2(float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, ptr byval(%fits_in_2_sse_reg) align 8 %{{.*}}) {
+// CHECK: define void @test_contains_x87(ptr byval(%contains_x87) align 16 %{{.*}}) {
+// CHECK: define void @test_contains_complex_x87(ptr byval(%contains_complex_x87) align 16 %{{.*}}) {
+// CHECK: define void @test_nested_toobig(ptr byval(%nested_toobig) align 8 %{{.*}}) {
+// CHECK: define void @test_badly_aligned(ptr byval(%badly_aligned) align 8 %{{.*}}) {
+// CHECK: define void @test_logical_toobig(ptr byval(%logical_too_big) align 8 %{{.*}}) {
+// CHECK: define void @l_not_enough_int_reg(i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, ptr byval(%l_fits_in_2_int_reg) align 8 %{{.*}}) {
+// CHECK: define void @test_complex_toobig(ptr byval(%complex_too_big) align 8 %{{.*}}) {
+// CHECK: define void @cplx_not_enough_sse_reg_1(float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, ptr byval(%cplx_fits_in_1_sse_reg) align 8 %{{.*}}) {
+// CHECK: define void @test_char_to_big(ptr byval(%char_too_big) align 8 %{{.*}}) {
+// CHECK: define void @char_not_enough_int_reg_1(i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, ptr byval(%char_fits_in_1_int_reg) align 8 %{{.*}}) {
+// CHECK: define void @mix_not_enough_int_reg_1(i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, ptr byval(%mix_in_1_int_reg) align 8 %{{.*}}) {
+// CHECK: define void @mix_not_enough_sse_reg_2(float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, float %{{.*}}, ptr byval(%mix_in_1_int_reg_1_sse_reg) align 8 %{{.*}}) {
+// CHECK: define void @not_enough_int_reg_3(ptr sret({ fp128, fp128 }) align 16 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, ptr byval(%fits_in_1_int_reg) align 8 %{{.*}})
-- 
GitLab


From 2db1a42184218cad60072d1088498703946bafb9 Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Tue, 12 Dec 2023 11:51:28 +0100
Subject: [PATCH 268/349] [CVP] Add test for invalid use of undef range for
 saturating insts (NFC)

---
 .../CorrelatedValuePropagation/overflows.ll   | 41 ++++++++++++++++---
 1 file changed, 35 insertions(+), 6 deletions(-)

diff --git a/llvm/test/Transforms/CorrelatedValuePropagation/overflows.ll b/llvm/test/Transforms/CorrelatedValuePropagation/overflows.ll
index 5108af7f4516..7424da32e32f 100644
--- a/llvm/test/Transforms/CorrelatedValuePropagation/overflows.ll
+++ b/llvm/test/Transforms/CorrelatedValuePropagation/overflows.ll
@@ -1,12 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -passes=correlated-propagation < %s | FileCheck %s
 
-; Check that debug locations are preserved. For more info see:
-;   https://llvm.org/docs/SourceLevelDebugging.html#fixing-errors
-; RUN: opt < %s -enable-debugify -passes=correlated-propagation -S 2>&1 | \
-; RUN:   FileCheck %s -check-prefix=DEBUG
-; DEBUG: CheckModuleDebugify: PASS
-
 declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32)
 
 declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32)
@@ -1155,3 +1149,38 @@ out:
   %ret = phi i1 [ true, %entry], [ true, %cont1 ], [ %cmp3, %cont2 ]
   ret i1 %ret
 }
+
+; FIXME: This is a miscompile.
+define i8 @uadd_sat_undef_range(i8 %x) {
+; CHECK-LABEL: @uadd_sat_undef_range(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i8 [[X:%.*]], label [[JOIN:%.*]] [
+; CHECK-NEXT:      i8 1, label [[CASE1:%.*]]
+; CHECK-NEXT:      i8 2, label [[CASE2:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       case1:
+; CHECK-NEXT:    br label [[JOIN]]
+; CHECK:       case2:
+; CHECK-NEXT:    br label [[JOIN]]
+; CHECK:       join:
+; CHECK-NEXT:    [[PHI:%.*]] = phi i8 [ 1, [[CASE1]] ], [ 2, [[CASE2]] ], [ undef, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    [[RES1:%.*]] = add nuw i8 [[PHI]], 100
+; CHECK-NEXT:    ret i8 [[RES1]]
+;
+entry:
+  switch i8 %x, label %join [
+  i8 1, label %case1
+  i8 2, label %case2
+  ]
+
+case1:
+  br label %join
+
+case2:
+  br label %join
+
+join:
+  %phi = phi i8 [ 1, %case1 ], [ 2, %case2 ], [ undef, %entry ]
+  %res = call i8 @llvm.uadd.sat.i8(i8 %phi, i8 100)
+  ret i8 %res
+}
-- 
GitLab


From 84df226c4a2fd1852ca5c1f52fb4463da9555913 Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Tue, 12 Dec 2023 11:53:30 +0100
Subject: [PATCH 269/349] [CVP] Don't use undef ranges in willNotOverflow()

---
 llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp   | 6 ++++--
 .../test/Transforms/CorrelatedValuePropagation/overflows.ll | 5 ++---
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp b/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
index 669bdf50ba6e..8bc05be97dae 100644
--- a/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
+++ b/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
@@ -393,8 +393,10 @@ static bool processSwitch(SwitchInst *I, LazyValueInfo *LVI,
 
 // See if we can prove that the given binary op intrinsic will not overflow.
 static bool willNotOverflow(BinaryOpIntrinsic *BO, LazyValueInfo *LVI) {
-  ConstantRange LRange = LVI->getConstantRangeAtUse(BO->getOperandUse(0));
-  ConstantRange RRange = LVI->getConstantRangeAtUse(BO->getOperandUse(1));
+  ConstantRange LRange =
+      LVI->getConstantRangeAtUse(BO->getOperandUse(0), /*UndefAllowed*/ false);
+  ConstantRange RRange =
+      LVI->getConstantRangeAtUse(BO->getOperandUse(1), /*UndefAllowed*/ false);
   ConstantRange NWRegion = ConstantRange::makeGuaranteedNoWrapRegion(
       BO->getBinaryOp(), RRange, BO->getNoWrapKind());
   return NWRegion.contains(LRange);
diff --git a/llvm/test/Transforms/CorrelatedValuePropagation/overflows.ll b/llvm/test/Transforms/CorrelatedValuePropagation/overflows.ll
index 7424da32e32f..669527ed88fa 100644
--- a/llvm/test/Transforms/CorrelatedValuePropagation/overflows.ll
+++ b/llvm/test/Transforms/CorrelatedValuePropagation/overflows.ll
@@ -1150,7 +1150,6 @@ out:
   ret i1 %ret
 }
 
-; FIXME: This is a miscompile.
 define i8 @uadd_sat_undef_range(i8 %x) {
 ; CHECK-LABEL: @uadd_sat_undef_range(
 ; CHECK-NEXT:  entry:
@@ -1164,8 +1163,8 @@ define i8 @uadd_sat_undef_range(i8 %x) {
 ; CHECK-NEXT:    br label [[JOIN]]
 ; CHECK:       join:
 ; CHECK-NEXT:    [[PHI:%.*]] = phi i8 [ 1, [[CASE1]] ], [ 2, [[CASE2]] ], [ undef, [[ENTRY:%.*]] ]
-; CHECK-NEXT:    [[RES1:%.*]] = add nuw i8 [[PHI]], 100
-; CHECK-NEXT:    ret i8 [[RES1]]
+; CHECK-NEXT:    [[RES:%.*]] = call i8 @llvm.uadd.sat.i8(i8 [[PHI]], i8 100)
+; CHECK-NEXT:    ret i8 [[RES]]
 ;
 entry:
   switch i8 %x, label %join [
-- 
GitLab


From b9be9f66c72893feb95300c1564b789773280a01 Mon Sep 17 00:00:00 2001
From: Guillaume Chatelet <gchatelet@google.com>
Date: Tue, 12 Dec 2023 11:54:54 +0100
Subject: [PATCH 270/349] [libc] Make the bit header compatible with uint128
 types (#75161)

---
 libc/src/__support/CPP/bit.h             | 5 +++--
 libc/src/__support/UInt.h                | 2 ++
 libc/test/src/__support/CPP/bit_test.cpp | 6 +++++-
 3 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/libc/src/__support/CPP/bit.h b/libc/src/__support/CPP/bit.h
index 2091c3662d50..4de142b56165 100644
--- a/libc/src/__support/CPP/bit.h
+++ b/libc/src/__support/CPP/bit.h
@@ -78,7 +78,7 @@ template <typename T, typename = cpp::enable_if_t<cpp::is_unsigned_v<T>>>
     return 0;
   // Bisection method.
   unsigned zero_bits = 0;
-  T shift = cpp::numeric_limits<T>::digits >> 1;
+  unsigned shift = cpp::numeric_limits<T>::digits >> 1;
   T mask = cpp::numeric_limits<T>::max() >> shift;
   while (shift) {
     if ((value & mask) == 0) {
@@ -115,7 +115,8 @@ template <typename T, typename = cpp::enable_if_t<cpp::is_unsigned_v<T>>>
     return cpp::numeric_limits<T>::digits;
   // Bisection method.
   unsigned zero_bits = 0;
-  for (T shift = cpp::numeric_limits<T>::digits >> 1; shift; shift >>= 1) {
+  for (unsigned shift = cpp::numeric_limits<T>::digits >> 1; shift;
+       shift >>= 1) {
     T tmp = value >> shift;
     if (tmp)
       value = tmp;
diff --git a/libc/src/__support/UInt.h b/libc/src/__support/UInt.h
index f72b995f8788..cfd495c58618 100644
--- a/libc/src/__support/UInt.h
+++ b/libc/src/__support/UInt.h
@@ -903,6 +903,7 @@ public:
     return UInt<128>({0xffff'ffff'ffff'ffff, 0xffff'ffff'ffff'ffff});
   }
   LIBC_INLINE static constexpr UInt<128> min() { return UInt<128>(0); }
+  LIBC_INLINE_VAR static constexpr int digits = 128;
 };
 
 template <> class numeric_limits<Int<128>> {
@@ -913,6 +914,7 @@ public:
   LIBC_INLINE static constexpr Int<128> min() {
     return Int<128>({0, 0x8000'0000'0000'0000});
   }
+  LIBC_INLINE_VAR static constexpr int digits = 128;
 };
 
 // Provides is_integral of U/Int<128>, U/Int<192>, U/Int<256>.
diff --git a/libc/test/src/__support/CPP/bit_test.cpp b/libc/test/src/__support/CPP/bit_test.cpp
index b7cd99d169fc..fef551bc1f0e 100644
--- a/libc/test/src/__support/CPP/bit_test.cpp
+++ b/libc/test/src/__support/CPP/bit_test.cpp
@@ -16,7 +16,11 @@ namespace LIBC_NAMESPACE::cpp {
 
 using UnsignedTypes =
     testing::TypeList<unsigned char, unsigned short, unsigned int,
-                      unsigned long, unsigned long long>;
+                      unsigned long, unsigned long long,
+#if defined(__SIZEOF_INT128__)
+                      __uint128_t,
+#endif
+                      cpp::UInt<128>>;
 
 TYPED_TEST(LlvmLibcBitTest, HasSingleBit, UnsignedTypes) {
   EXPECT_FALSE(has_single_bit<T>(T(0)));
-- 
GitLab


From 3be65325f9e37db2d6eeffe96f9709d710a9a49f Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Tue, 12 Dec 2023 10:59:28 +0000
Subject: [PATCH 271/349] [X86] canonicalizeShuffleWithBinOps - generalize to
 handle some unary ops

Rename to canonicalizeShuffleWithOp and begin adding SHUFFLE(UNARYOP(X),UNARYOP(Y)) -> UNARYOP(SHUFFLE(X,Y)) fold support.

This is only kicking in after legalization, so targets that expand bit counts are still duplicating but it helps with a few initial cases.

I'm investigating adding support for extensions/conversions as well, but this is a first step.
---
 llvm/lib/Target/X86/X86ISelLowering.cpp | 38 ++++++++++++++++++++--
 llvm/test/CodeGen/X86/widen_bitcnt.ll   | 42 +++++++++----------------
 2 files changed, 49 insertions(+), 31 deletions(-)

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index adafb425babf..66cb1a77901c 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -39587,9 +39587,21 @@ static SDValue combineCommutableSHUFP(SDValue N, MVT VT, const SDLoc &DL,
   return SDValue();
 }
 
+// TODO - move this to TLI like isBinOp?
+static bool isUnaryOp(unsigned Opcode) {
+  switch (Opcode) {
+  case ISD::CTLZ:
+  case ISD::CTTZ:
+  case ISD::CTPOP:
+    return true;
+  }
+  return false;
+}
+
+// Canonicalize SHUFFLE(UNARYOP(X)) -> UNARYOP(SHUFFLE(X)).
 // Canonicalize SHUFFLE(BINOP(X,Y)) -> BINOP(SHUFFLE(X),SHUFFLE(Y)).
-static SDValue canonicalizeShuffleWithBinOps(SDValue N, SelectionDAG &DAG,
-                                             const SDLoc &DL) {
+static SDValue canonicalizeShuffleWithOp(SDValue N, SelectionDAG &DAG,
+                                         const SDLoc &DL) {
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   EVT ShuffleVT = N.getValueType();
 
@@ -39716,6 +39728,25 @@ static SDValue canonicalizeShuffleWithBinOps(SDValue N, SelectionDAG &DAG,
                                             DAG.getBitcast(OpVT, RHS)));
         }
       }
+      if (isUnaryOp(SrcOpcode) && N1.getOpcode() == SrcOpcode &&
+          N0.getValueType() == N1.getValueType() &&
+          IsSafeToMoveShuffle(N0, SrcOpcode) &&
+          IsSafeToMoveShuffle(N1, SrcOpcode)) {
+        SDValue Op00 = peekThroughOneUseBitcasts(N0.getOperand(0));
+        SDValue Op10 = peekThroughOneUseBitcasts(N1.getOperand(0));
+        SDValue Res;
+        Op00 = DAG.getBitcast(ShuffleVT, Op00);
+        Op10 = DAG.getBitcast(ShuffleVT, Op10);
+        if (N.getNumOperands() == 3) {
+          Res = DAG.getNode(Opc, DL, ShuffleVT, Op00, Op10, N.getOperand(2));
+        } else {
+          Res = DAG.getNode(Opc, DL, ShuffleVT, Op00, Op10);
+        }
+        EVT OpVT = N0.getValueType();
+        return DAG.getBitcast(
+            ShuffleVT,
+            DAG.getNode(SrcOpcode, DL, OpVT, DAG.getBitcast(OpVT, Res)));
+      }
     }
     break;
   }
@@ -40797,10 +40828,11 @@ static SDValue combineShuffle(SDNode *N, SelectionDAG &DAG,
     if (TLI.SimplifyDemandedVectorElts(Op, DemandedElts, DCI))
       return SDValue(N, 0);
 
+    // Canonicalize SHUFFLE(UNARYOP(X)) -> UNARYOP(SHUFFLE(X)).
     // Canonicalize SHUFFLE(BINOP(X,Y)) -> BINOP(SHUFFLE(X),SHUFFLE(Y)).
     // Perform this after other shuffle combines to allow inner shuffles to be
     // combined away first.
-    if (SDValue BinOp = canonicalizeShuffleWithBinOps(Op, DAG, dl))
+    if (SDValue BinOp = canonicalizeShuffleWithOp(Op, DAG, dl))
       return BinOp;
   }
 
diff --git a/llvm/test/CodeGen/X86/widen_bitcnt.ll b/llvm/test/CodeGen/X86/widen_bitcnt.ll
index da468b6d809e..0f121d88b357 100644
--- a/llvm/test/CodeGen/X86/widen_bitcnt.ll
+++ b/llvm/test/CodeGen/X86/widen_bitcnt.ll
@@ -88,9 +88,8 @@ define <4 x i32> @widen_ctpop_v2i32_v4i32(<2 x i32> %a0, <2 x i32> %a1) {
 ;
 ; AVX512VPOPCNT-LABEL: widen_ctpop_v2i32_v4i32:
 ; AVX512VPOPCNT:       # %bb.0:
-; AVX512VPOPCNT-NEXT:    vpopcntd %xmm0, %xmm0
-; AVX512VPOPCNT-NEXT:    vpopcntd %xmm1, %xmm1
 ; AVX512VPOPCNT-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; AVX512VPOPCNT-NEXT:    vpopcntd %xmm0, %xmm0
 ; AVX512VPOPCNT-NEXT:    retq
   %b0 = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %a0)
   %b1 = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %a1)
@@ -325,10 +324,9 @@ define <8 x i32> @widen_ctpop_v2i32_v8i32(<2 x i32> %a0, <2 x i32> %a1, <2 x i32
 ; AVX512VPOPCNT-NEXT:    # kill: def $xmm1 killed $xmm1 def $ymm1
 ; AVX512VPOPCNT-NEXT:    # kill: def $xmm0 killed $xmm0 def $ymm0
 ; AVX512VPOPCNT-NEXT:    vinserti128 $1, %xmm3, %ymm1, %ymm1
-; AVX512VPOPCNT-NEXT:    vpopcntd %ymm1, %ymm1
 ; AVX512VPOPCNT-NEXT:    vinserti128 $1, %xmm2, %ymm0, %ymm0
-; AVX512VPOPCNT-NEXT:    vpopcntd %ymm0, %ymm0
 ; AVX512VPOPCNT-NEXT:    vpunpcklqdq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
+; AVX512VPOPCNT-NEXT:    vpopcntd %ymm0, %ymm0
 ; AVX512VPOPCNT-NEXT:    retq
   %b0 = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %a0)
   %b1 = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %a1)
@@ -438,9 +436,8 @@ define <4 x i32> @widen_ctlz_v2i32_v4i32(<2 x i32> %a0, <2 x i32> %a1) {
 ;
 ; AVX512-LABEL: widen_ctlz_v2i32_v4i32:
 ; AVX512:       # %bb.0:
-; AVX512-NEXT:    vplzcntd %xmm0, %xmm0
-; AVX512-NEXT:    vplzcntd %xmm1, %xmm1
 ; AVX512-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; AVX512-NEXT:    vplzcntd %xmm0, %xmm0
 ; AVX512-NEXT:    retq
   %b0 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %a0, i1 0)
   %b1 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %a1, i1 0)
@@ -706,10 +703,9 @@ define <8 x i32> @widen_ctlz_v2i32_v8i32(<2 x i32> %a0, <2 x i32> %a1, <2 x i32>
 ; AVX512-NEXT:    # kill: def $xmm1 killed $xmm1 def $ymm1
 ; AVX512-NEXT:    # kill: def $xmm0 killed $xmm0 def $ymm0
 ; AVX512-NEXT:    vinserti128 $1, %xmm3, %ymm1, %ymm1
-; AVX512-NEXT:    vplzcntd %ymm1, %ymm1
 ; AVX512-NEXT:    vinserti128 $1, %xmm2, %ymm0, %ymm0
-; AVX512-NEXT:    vplzcntd %ymm0, %ymm0
 ; AVX512-NEXT:    vpunpcklqdq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
+; AVX512-NEXT:    vplzcntd %ymm0, %ymm0
 ; AVX512-NEXT:    retq
   %b0 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %a0, i1 0)
   %b1 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %a1, i1 0)
@@ -819,9 +815,8 @@ define <4 x i32> @widen_ctlz_undef_v2i32_v4i32(<2 x i32> %a0, <2 x i32> %a1) {
 ;
 ; AVX512-LABEL: widen_ctlz_undef_v2i32_v4i32:
 ; AVX512:       # %bb.0:
-; AVX512-NEXT:    vplzcntd %xmm0, %xmm0
-; AVX512-NEXT:    vplzcntd %xmm1, %xmm1
 ; AVX512-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; AVX512-NEXT:    vplzcntd %xmm0, %xmm0
 ; AVX512-NEXT:    retq
   %b0 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %a0, i1 1)
   %b1 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %a1, i1 1)
@@ -1087,10 +1082,9 @@ define <8 x i32> @widen_ctlz_undef_v2i32_v8i32(<2 x i32> %a0, <2 x i32> %a1, <2
 ; AVX512-NEXT:    # kill: def $xmm1 killed $xmm1 def $ymm1
 ; AVX512-NEXT:    # kill: def $xmm0 killed $xmm0 def $ymm0
 ; AVX512-NEXT:    vinserti128 $1, %xmm3, %ymm1, %ymm1
-; AVX512-NEXT:    vplzcntd %ymm1, %ymm1
 ; AVX512-NEXT:    vinserti128 $1, %xmm2, %ymm0, %ymm0
-; AVX512-NEXT:    vplzcntd %ymm0, %ymm0
 ; AVX512-NEXT:    vpunpcklqdq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
+; AVX512-NEXT:    vplzcntd %ymm0, %ymm0
 ; AVX512-NEXT:    retq
   %b0 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %a0, i1 1)
   %b1 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %a1, i1 1)
@@ -1176,12 +1170,11 @@ define <4 x i32> @widen_cttz_v2i32_v4i32(<2 x i32> %a0, <2 x i32> %a1) {
 ; AVX512VL-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
 ; AVX512VL-NEXT:    vpaddd %xmm2, %xmm0, %xmm3
 ; AVX512VL-NEXT:    vpandn %xmm3, %xmm0, %xmm0
-; AVX512VL-NEXT:    vplzcntd %xmm0, %xmm0
 ; AVX512VL-NEXT:    vpbroadcastd {{.*#+}} xmm3 = [32,32,32,32]
 ; AVX512VL-NEXT:    vpaddd %xmm2, %xmm1, %xmm2
 ; AVX512VL-NEXT:    vpandn %xmm2, %xmm1, %xmm1
-; AVX512VL-NEXT:    vplzcntd %xmm1, %xmm1
 ; AVX512VL-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; AVX512VL-NEXT:    vplzcntd %xmm0, %xmm0
 ; AVX512VL-NEXT:    vpsubd %xmm0, %xmm3, %xmm0
 ; AVX512VL-NEXT:    retq
 ;
@@ -1190,11 +1183,10 @@ define <4 x i32> @widen_cttz_v2i32_v4i32(<2 x i32> %a0, <2 x i32> %a1) {
 ; AVX512VPOPCNT-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
 ; AVX512VPOPCNT-NEXT:    vpaddd %xmm2, %xmm0, %xmm3
 ; AVX512VPOPCNT-NEXT:    vpandn %xmm3, %xmm0, %xmm0
-; AVX512VPOPCNT-NEXT:    vpopcntd %xmm0, %xmm0
 ; AVX512VPOPCNT-NEXT:    vpaddd %xmm2, %xmm1, %xmm2
 ; AVX512VPOPCNT-NEXT:    vpandn %xmm2, %xmm1, %xmm1
-; AVX512VPOPCNT-NEXT:    vpopcntd %xmm1, %xmm1
 ; AVX512VPOPCNT-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; AVX512VPOPCNT-NEXT:    vpopcntd %xmm0, %xmm0
 ; AVX512VPOPCNT-NEXT:    retq
   %b0 = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %a0, i1 0)
   %b1 = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %a1, i1 0)
@@ -1416,12 +1408,11 @@ define <8 x i32> @widen_cttz_v2i32_v8i32(<2 x i32> %a0, <2 x i32> %a1, <2 x i32>
 ; AVX512VL-NEXT:    vpcmpeqd %ymm3, %ymm3, %ymm3
 ; AVX512VL-NEXT:    vpaddd %ymm3, %ymm1, %ymm4
 ; AVX512VL-NEXT:    vpandn %ymm4, %ymm1, %ymm1
-; AVX512VL-NEXT:    vplzcntd %ymm1, %ymm1
 ; AVX512VL-NEXT:    vinserti128 $1, %xmm2, %ymm0, %ymm0
 ; AVX512VL-NEXT:    vpaddd %ymm3, %ymm0, %ymm2
 ; AVX512VL-NEXT:    vpandn %ymm2, %ymm0, %ymm0
-; AVX512VL-NEXT:    vplzcntd %ymm0, %ymm0
 ; AVX512VL-NEXT:    vpunpcklqdq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
+; AVX512VL-NEXT:    vplzcntd %ymm0, %ymm0
 ; AVX512VL-NEXT:    vpbroadcastd {{.*#+}} ymm1 = [32,32,32,32,32,32,32,32]
 ; AVX512VL-NEXT:    vpsubd %ymm0, %ymm1, %ymm0
 ; AVX512VL-NEXT:    retq
@@ -1434,12 +1425,11 @@ define <8 x i32> @widen_cttz_v2i32_v8i32(<2 x i32> %a0, <2 x i32> %a1, <2 x i32>
 ; AVX512VPOPCNT-NEXT:    vpcmpeqd %ymm3, %ymm3, %ymm3
 ; AVX512VPOPCNT-NEXT:    vpaddd %ymm3, %ymm1, %ymm4
 ; AVX512VPOPCNT-NEXT:    vpandn %ymm4, %ymm1, %ymm1
-; AVX512VPOPCNT-NEXT:    vpopcntd %ymm1, %ymm1
 ; AVX512VPOPCNT-NEXT:    vinserti128 $1, %xmm2, %ymm0, %ymm0
 ; AVX512VPOPCNT-NEXT:    vpaddd %ymm3, %ymm0, %ymm2
 ; AVX512VPOPCNT-NEXT:    vpandn %ymm2, %ymm0, %ymm0
-; AVX512VPOPCNT-NEXT:    vpopcntd %ymm0, %ymm0
 ; AVX512VPOPCNT-NEXT:    vpunpcklqdq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
+; AVX512VPOPCNT-NEXT:    vpopcntd %ymm0, %ymm0
 ; AVX512VPOPCNT-NEXT:    retq
   %b0 = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %a0, i1 0)
   %b1 = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %a1, i1 0)
@@ -1525,12 +1515,11 @@ define <4 x i32> @widen_cttz_undef_v2i32_v4i32(<2 x i32> %a0, <2 x i32> %a1) {
 ; AVX512VL-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
 ; AVX512VL-NEXT:    vpaddd %xmm2, %xmm0, %xmm3
 ; AVX512VL-NEXT:    vpandn %xmm3, %xmm0, %xmm0
-; AVX512VL-NEXT:    vplzcntd %xmm0, %xmm0
 ; AVX512VL-NEXT:    vpbroadcastd {{.*#+}} xmm3 = [32,32,32,32]
 ; AVX512VL-NEXT:    vpaddd %xmm2, %xmm1, %xmm2
 ; AVX512VL-NEXT:    vpandn %xmm2, %xmm1, %xmm1
-; AVX512VL-NEXT:    vplzcntd %xmm1, %xmm1
 ; AVX512VL-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; AVX512VL-NEXT:    vplzcntd %xmm0, %xmm0
 ; AVX512VL-NEXT:    vpsubd %xmm0, %xmm3, %xmm0
 ; AVX512VL-NEXT:    retq
 ;
@@ -1539,11 +1528,10 @@ define <4 x i32> @widen_cttz_undef_v2i32_v4i32(<2 x i32> %a0, <2 x i32> %a1) {
 ; AVX512VPOPCNT-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
 ; AVX512VPOPCNT-NEXT:    vpaddd %xmm2, %xmm0, %xmm3
 ; AVX512VPOPCNT-NEXT:    vpandn %xmm3, %xmm0, %xmm0
-; AVX512VPOPCNT-NEXT:    vpopcntd %xmm0, %xmm0
 ; AVX512VPOPCNT-NEXT:    vpaddd %xmm2, %xmm1, %xmm2
 ; AVX512VPOPCNT-NEXT:    vpandn %xmm2, %xmm1, %xmm1
-; AVX512VPOPCNT-NEXT:    vpopcntd %xmm1, %xmm1
 ; AVX512VPOPCNT-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; AVX512VPOPCNT-NEXT:    vpopcntd %xmm0, %xmm0
 ; AVX512VPOPCNT-NEXT:    retq
   %b0 = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %a0, i1 1)
   %b1 = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %a1, i1 1)
@@ -1765,12 +1753,11 @@ define <8 x i32> @widen_cttz_undef_v2i32_v8i32(<2 x i32> %a0, <2 x i32> %a1, <2
 ; AVX512VL-NEXT:    vpcmpeqd %ymm3, %ymm3, %ymm3
 ; AVX512VL-NEXT:    vpaddd %ymm3, %ymm1, %ymm4
 ; AVX512VL-NEXT:    vpandn %ymm4, %ymm1, %ymm1
-; AVX512VL-NEXT:    vplzcntd %ymm1, %ymm1
 ; AVX512VL-NEXT:    vinserti128 $1, %xmm2, %ymm0, %ymm0
 ; AVX512VL-NEXT:    vpaddd %ymm3, %ymm0, %ymm2
 ; AVX512VL-NEXT:    vpandn %ymm2, %ymm0, %ymm0
-; AVX512VL-NEXT:    vplzcntd %ymm0, %ymm0
 ; AVX512VL-NEXT:    vpunpcklqdq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
+; AVX512VL-NEXT:    vplzcntd %ymm0, %ymm0
 ; AVX512VL-NEXT:    vpbroadcastd {{.*#+}} ymm1 = [32,32,32,32,32,32,32,32]
 ; AVX512VL-NEXT:    vpsubd %ymm0, %ymm1, %ymm0
 ; AVX512VL-NEXT:    retq
@@ -1783,12 +1770,11 @@ define <8 x i32> @widen_cttz_undef_v2i32_v8i32(<2 x i32> %a0, <2 x i32> %a1, <2
 ; AVX512VPOPCNT-NEXT:    vpcmpeqd %ymm3, %ymm3, %ymm3
 ; AVX512VPOPCNT-NEXT:    vpaddd %ymm3, %ymm1, %ymm4
 ; AVX512VPOPCNT-NEXT:    vpandn %ymm4, %ymm1, %ymm1
-; AVX512VPOPCNT-NEXT:    vpopcntd %ymm1, %ymm1
 ; AVX512VPOPCNT-NEXT:    vinserti128 $1, %xmm2, %ymm0, %ymm0
 ; AVX512VPOPCNT-NEXT:    vpaddd %ymm3, %ymm0, %ymm2
 ; AVX512VPOPCNT-NEXT:    vpandn %ymm2, %ymm0, %ymm0
-; AVX512VPOPCNT-NEXT:    vpopcntd %ymm0, %ymm0
 ; AVX512VPOPCNT-NEXT:    vpunpcklqdq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
+; AVX512VPOPCNT-NEXT:    vpopcntd %ymm0, %ymm0
 ; AVX512VPOPCNT-NEXT:    retq
   %b0 = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %a0, i1 1)
   %b1 = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %a1, i1 1)
-- 
GitLab


From 4b7f14573e32d0abd092f097d18e333267a6c2ea Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Tue, 12 Dec 2023 12:03:19 +0100
Subject: [PATCH 272/349] [CVP] Add test for invalid use of undef range in urem
 transform (NFC)

---
 .../CorrelatedValuePropagation/urem.ll        | 68 +++++++++++++++++++
 1 file changed, 68 insertions(+)

diff --git a/llvm/test/Transforms/CorrelatedValuePropagation/urem.ll b/llvm/test/Transforms/CorrelatedValuePropagation/urem.ll
index b9c112c69e1a..9eed770e665d 100644
--- a/llvm/test/Transforms/CorrelatedValuePropagation/urem.ll
+++ b/llvm/test/Transforms/CorrelatedValuePropagation/urem.ll
@@ -394,4 +394,72 @@ else:
   ret void
 }
 
+; FIXME: This is a miscompile.
+define i8 @urem_undef_range_op1(i8 %x) {
+; CHECK-LABEL: @urem_undef_range_op1(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i8 [[X:%.*]], label [[JOIN:%.*]] [
+; CHECK-NEXT:      i8 1, label [[CASE1:%.*]]
+; CHECK-NEXT:      i8 2, label [[CASE2:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       case1:
+; CHECK-NEXT:    br label [[JOIN]]
+; CHECK:       case2:
+; CHECK-NEXT:    br label [[JOIN]]
+; CHECK:       join:
+; CHECK-NEXT:    [[PHI:%.*]] = phi i8 [ 1, [[CASE1]] ], [ 2, [[CASE2]] ], [ undef, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    ret i8 [[PHI]]
+;
+entry:
+  switch i8 %x, label %join [
+  i8 1, label %case1
+  i8 2, label %case2
+  ]
+
+case1:
+  br label %join
+
+case2:
+  br label %join
+
+join:
+  %phi = phi i8 [ 1, %case1 ], [ 2, %case2 ], [ undef, %entry ]
+  %res = urem i8 %phi, 3
+  ret i8 %res
+}
+
+define i8 @urem_undef_range_op2(i8 %x) {
+; CHECK-LABEL: @urem_undef_range_op2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i8 [[X:%.*]], label [[JOIN:%.*]] [
+; CHECK-NEXT:      i8 1, label [[CASE1:%.*]]
+; CHECK-NEXT:      i8 2, label [[CASE2:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       case1:
+; CHECK-NEXT:    br label [[JOIN]]
+; CHECK:       case2:
+; CHECK-NEXT:    br label [[JOIN]]
+; CHECK:       join:
+; CHECK-NEXT:    [[PHI:%.*]] = phi i8 [ 5, [[CASE1]] ], [ 6, [[CASE2]] ], [ undef, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    [[RES:%.*]] = sub nuw i8 7, [[PHI]]
+; CHECK-NEXT:    ret i8 [[RES]]
+;
+entry:
+  switch i8 %x, label %join [
+  i8 1, label %case1
+  i8 2, label %case2
+  ]
+
+case1:
+  br label %join
+
+case2:
+  br label %join
+
+join:
+  %phi = phi i8 [ 5, %case1 ], [ 6, %case2 ], [ undef, %entry ]
+  %res = urem i8 7, %phi
+  ret i8 %res
+}
+
 declare void @use(i1)
-- 
GitLab


From 967e84eee3076bc6f306c70d07e3a922e3c1c3a6 Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Tue, 12 Dec 2023 12:05:36 +0100
Subject: [PATCH 273/349] [CVP] Don't use undef range for LHS of div/rem
 transforms

Using it for RHS is fine, as undef is UB in that case.
---
 .../Scalar/CorrelatedValuePropagation.cpp          | 14 ++++++++++----
 .../Transforms/CorrelatedValuePropagation/urem.ll  |  4 ++--
 2 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp b/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
index 8bc05be97dae..e6d8f89122ff 100644
--- a/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
+++ b/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
@@ -823,8 +823,11 @@ static bool processUDivOrURem(BinaryOperator *Instr, LazyValueInfo *LVI) {
   if (Instr->getType()->isVectorTy())
     return false;
 
-  ConstantRange XCR = LVI->getConstantRangeAtUse(Instr->getOperandUse(0));
-  ConstantRange YCR = LVI->getConstantRangeAtUse(Instr->getOperandUse(1));
+  ConstantRange XCR = LVI->getConstantRangeAtUse(Instr->getOperandUse(0),
+                                                 /*UndefAllowed*/ false);
+  // Allow undef for RHS, as we can assume it is division by zero UB.
+  ConstantRange YCR = LVI->getConstantRangeAtUse(Instr->getOperandUse(1),
+                                                 /*UndefAllowed*/ true);
   if (expandUDivOrURem(Instr, XCR, YCR))
     return true;
 
@@ -951,8 +954,11 @@ static bool processSDivOrSRem(BinaryOperator *Instr, LazyValueInfo *LVI) {
   if (Instr->getType()->isVectorTy())
     return false;
 
-  ConstantRange LCR = LVI->getConstantRangeAtUse(Instr->getOperandUse(0));
-  ConstantRange RCR = LVI->getConstantRangeAtUse(Instr->getOperandUse(1));
+  ConstantRange LCR =
+      LVI->getConstantRangeAtUse(Instr->getOperandUse(0), /*AllowUndef*/ false);
+  // Allow undef for RHS, as we can assume it is division by zero UB.
+  ConstantRange RCR =
+      LVI->getConstantRangeAtUse(Instr->getOperandUse(1), /*AlloweUndef*/ true);
   if (Instr->getOpcode() == Instruction::SDiv)
     if (processSDiv(Instr, LCR, RCR, LVI))
       return true;
diff --git a/llvm/test/Transforms/CorrelatedValuePropagation/urem.ll b/llvm/test/Transforms/CorrelatedValuePropagation/urem.ll
index 9eed770e665d..ec6461e29f19 100644
--- a/llvm/test/Transforms/CorrelatedValuePropagation/urem.ll
+++ b/llvm/test/Transforms/CorrelatedValuePropagation/urem.ll
@@ -394,7 +394,6 @@ else:
   ret void
 }
 
-; FIXME: This is a miscompile.
 define i8 @urem_undef_range_op1(i8 %x) {
 ; CHECK-LABEL: @urem_undef_range_op1(
 ; CHECK-NEXT:  entry:
@@ -408,7 +407,8 @@ define i8 @urem_undef_range_op1(i8 %x) {
 ; CHECK-NEXT:    br label [[JOIN]]
 ; CHECK:       join:
 ; CHECK-NEXT:    [[PHI:%.*]] = phi i8 [ 1, [[CASE1]] ], [ 2, [[CASE2]] ], [ undef, [[ENTRY:%.*]] ]
-; CHECK-NEXT:    ret i8 [[PHI]]
+; CHECK-NEXT:    [[RES:%.*]] = urem i8 [[PHI]], 3
+; CHECK-NEXT:    ret i8 [[RES]]
 ;
 entry:
   switch i8 %x, label %join [
-- 
GitLab


From 1f71db78ce2b5cc7af86271276d039e4e87146d3 Mon Sep 17 00:00:00 2001
From: Nabeel Omer <nabeel.omer@sony.com>
Date: Tue, 12 Dec 2023 11:13:40 +0000
Subject: [PATCH 274/349] [NFC][DSE] Fix typo comment in eliminateDeadStores
 (#75166)

> We are re-using tryToMergePartialOverlappingStores, which requires
DeadSI to dominate DeadSI.

Should be "DeadSI to dominate KillingSI" because that's what the check
is for.
---
 llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp b/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
index dd0a290252da..008dcc53fd44 100644
--- a/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
+++ b/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
@@ -2170,7 +2170,7 @@ static bool eliminateDeadStores(Function &F, AliasAnalysis &AA, MemorySSA &MSSA,
           auto *DeadSI = dyn_cast<StoreInst>(DeadI);
           auto *KillingSI = dyn_cast<StoreInst>(KillingI);
           // We are re-using tryToMergePartialOverlappingStores, which requires
-          // DeadSI to dominate DeadSI.
+          // DeadSI to dominate KillingSI.
           // TODO: implement tryToMergeParialOverlappingStores using MemorySSA.
           if (DeadSI && KillingSI && DT.dominates(DeadSI, KillingSI)) {
             if (Constant *Merged = tryToMergePartialOverlappingStores(
-- 
GitLab


From 985c00819583a23b58d8c8cdeaefe6f9ed49e9cf Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp@bytedance.com>
Date: Tue, 12 Dec 2023 19:16:30 +0800
Subject: [PATCH 275/349] [RISCV][NFC] Use AddTargetFeature to add
 fast-unaligned-access (#74280)

We can reduce some code.
---
 clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 5d990ba78e5c..0b696111e7d7 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -171,13 +171,8 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
     Features.push_back("-save-restore");
 
   // -mno-unaligned-access is default, unless -munaligned-access is specified.
-  if (const Arg *A = Args.getLastArg(options::OPT_munaligned_access,
-                                     options::OPT_mno_unaligned_access)) {
-    if (A->getOption().matches(options::OPT_munaligned_access))
-      Features.push_back("+fast-unaligned-access");
-    else
-      Features.push_back("-fast-unaligned-access");
-  }
+  AddTargetFeature(Args, Features, options::OPT_munaligned_access,
+                   options::OPT_mno_unaligned_access, "fast-unaligned-access");
 
   // Now add any that the user explicitly requested on the command line,
   // which may override the defaults.
-- 
GitLab


From b204321302ad16d2a1bdb97830a5708282d0abd4 Mon Sep 17 00:00:00 2001
From: Nikolas Klauser <nikolasklauser@berlin.de>
Date: Tue, 12 Dec 2023 12:22:03 +0100
Subject: [PATCH 276/349] [Clang][docs] Update  extension documentation
 (#75150)

This is back-ported to C++03 now, since clang accepts C++11 attributes
in C++03. https://godbolt.org/z/f7xG18bdE
---
 clang/docs/LanguageExtensions.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clang/docs/LanguageExtensions.rst b/clang/docs/LanguageExtensions.rst
index d34e867f5e61..13fb7c345aa4 100644
--- a/clang/docs/LanguageExtensions.rst
+++ b/clang/docs/LanguageExtensions.rst
@@ -1470,7 +1470,7 @@ Relaxed constexpr                      __cpp_constexpr                  C++14
 ``if constexpr``                       __cpp_if_constexpr               C++17         C++11
 fold expressions                       __cpp_fold_expressions           C++17         C++03
 Lambda capture of \*this by value      __cpp_capture_star_this          C++17         C++11
-Attributes on enums                    __cpp_enumerator_attributes      C++17         C++11
+Attributes on enums                    __cpp_enumerator_attributes      C++17         C++03
 Guaranteed copy elision                __cpp_guaranteed_copy_elision    C++17         C++03
 Hexadecimal floating literals          __cpp_hex_float                  C++17         C++03
 ``inline`` variables                   __cpp_inline_variables           C++17         C++03
-- 
GitLab


From 5ee088134fb87f7d716c58fa65beb11fb6afcb22 Mon Sep 17 00:00:00 2001
From: Orlando Cazalet-Hyams <orlando.hyams@sony.com>
Date: Tue, 12 Dec 2023 11:32:19 +0000
Subject: [PATCH 277/349] [DebugInfo][RemoveDIs] Handle dbg.declares in
 SelectionDAGISel (#73496)

This is a boring mechanical update to support DPValues that look like
dbg.declares in SelectionDAG.

The tests will become "live" once #74090 lands (see for more info).
---
 .../llvm/CodeGen/FunctionLoweringInfo.h       |   1 +
 .../SelectionDAG/FunctionLoweringInfo.cpp     |   1 +
 .../SelectionDAG/SelectionDAGBuilder.cpp      | 122 ++++++++++--------
 .../SelectionDAG/SelectionDAGBuilder.h        |   3 +
 .../CodeGen/SelectionDAG/SelectionDAGISel.cpp |   8 ++
 llvm/test/CodeGen/X86/dbg-combine.ll          |   1 +
 llvm/test/CodeGen/X86/selectiondag-order.ll   |   1 +
 .../Generic/2010-06-29-InlinedFnLocalVar.ll   |   1 +
 llvm/test/DebugInfo/Mips/InlinedFnLocalVar.ll |   1 +
 llvm/test/DebugInfo/X86/DW_AT_const_value.ll  |   1 +
 llvm/test/DebugInfo/X86/InlinedFnLocalVar.ll  |   1 +
 llvm/test/DebugInfo/X86/block-capture.ll      |   3 +
 .../X86/dbg-empty-metadata-lowering.ll        |   6 +
 .../X86/debug-info-block-captured-self.ll     |   3 +
 llvm/test/DebugInfo/X86/debug-info-blocks.ll  |   3 +
 .../X86/empty-metadata-dbg-declare.ll         |   1 +
 llvm/test/DebugInfo/X86/pieces-3.ll           |   1 +
 llvm/test/DebugInfo/X86/pieces-4.ll           |   2 +
 llvm/test/DebugInfo/X86/safestack-byval.ll    |   2 +
 .../X86/salvage-add-node-indirect.ll          |   1 +
 .../test/DebugInfo/X86/spill-indirect-nrvo.ll |   7 +
 .../DebugInfo/X86/spill-nontrivial-param.ll   |   2 +
 llvm/test/DebugInfo/X86/sret.ll               |   8 ++
 llvm/test/DebugInfo/X86/union-const.ll        |   2 +
 llvm/test/DebugInfo/X86/vla-global.ll         |   2 +
 llvm/test/DebugInfo/X86/vla-multi.ll          |   2 +
 26 files changed, 134 insertions(+), 52 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/FunctionLoweringInfo.h b/llvm/include/llvm/CodeGen/FunctionLoweringInfo.h
index 4c17e8dcc41a..cde7247aeb15 100644
--- a/llvm/include/llvm/CodeGen/FunctionLoweringInfo.h
+++ b/llvm/include/llvm/CodeGen/FunctionLoweringInfo.h
@@ -191,6 +191,7 @@ public:
   /// Collection of dbg.declare instructions handled after argument
   /// lowering and before ISel proper.
   SmallPtrSet<const DbgDeclareInst *, 8> PreprocessedDbgDeclares;
+  SmallPtrSet<const DPValue *, 8> PreprocessedDPVDeclares;
 
   /// set - Initialize this FunctionLoweringInfo with the given Function
   /// and its associated MachineFunction.
diff --git a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
index 1128ecfd860d..03cba892a167 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
@@ -357,6 +357,7 @@ void FunctionLoweringInfo::clear() {
   StatepointRelocationMaps.clear();
   PreferredExtendType.clear();
   PreprocessedDbgDeclares.clear();
+  PreprocessedDPVDeclares.clear();
 }
 
 /// CreateReg - Allocate a single virtual register for the given type.
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 4fd76d012a16..12ed4a82ee91 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -1148,6 +1148,60 @@ SDValue SelectionDAGBuilder::getControlRoot() {
   return updateRoot(PendingExports);
 }
 
+void SelectionDAGBuilder::handleDebugDeclare(Value *Address,
+                                             DILocalVariable *Variable,
+                                             DIExpression *Expression,
+                                             DebugLoc DL) {
+  assert(Variable && "Missing variable");
+
+  // Check if address has undef value.
+  if (!Address || isa<UndefValue>(Address) ||
+      (Address->use_empty() && !isa<Argument>(Address))) {
+    LLVM_DEBUG(
+        dbgs()
+        << "dbg_declare: Dropping debug info (bad/undef/unused-arg address)\n");
+    return;
+  }
+
+  bool IsParameter = Variable->isParameter() || isa<Argument>(Address);
+
+  SDValue &N = NodeMap[Address];
+  if (!N.getNode() && isa<Argument>(Address))
+    // Check unused arguments map.
+    N = UnusedArgNodeMap[Address];
+  SDDbgValue *SDV;
+  if (N.getNode()) {
+    if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
+      Address = BCI->getOperand(0);
+    // Parameters are handled specially.
+    auto *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
+    if (IsParameter && FINode) {
+      // Byval parameter. We have a frame index at this point.
+      SDV = DAG.getFrameIndexDbgValue(Variable, Expression, FINode->getIndex(),
+                                      /*IsIndirect*/ true, DL, SDNodeOrder);
+    } else if (isa<Argument>(Address)) {
+      // Address is an argument, so try to emit its dbg value using
+      // virtual register info from the FuncInfo.ValueMap.
+      EmitFuncArgumentDbgValue(Address, Variable, Expression, DL,
+                               FuncArgumentDbgValueKind::Declare, N);
+      return;
+    } else {
+      SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
+                            true, DL, SDNodeOrder);
+    }
+    DAG.AddDbgValue(SDV, IsParameter);
+  } else {
+    // If Address is an argument then try to emit its dbg value using
+    // virtual register info from the FuncInfo.ValueMap.
+    if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, DL,
+                                  FuncArgumentDbgValueKind::Declare, N)) {
+      LLVM_DEBUG(dbgs() << "dbg_declare: Dropping debug info"
+                        << " (could not emit func-arg dbg_value)\n");
+    }
+  }
+  return;
+}
+
 void SelectionDAGBuilder::visitDbgInfo(const Instruction &I) {
   // Add SDDbgValue nodes for any var locs here. Do so before updating
   // SDNodeOrder, as this mapping is {Inst -> Locs BEFORE Inst}.
@@ -1182,6 +1236,16 @@ void SelectionDAGBuilder::visitDbgInfo(const Instruction &I) {
     DIExpression *Expression = DPV.getExpression();
     dropDanglingDebugInfo(Variable, Expression);
 
+    if (DPV.getType() == DPValue::LocationType::Declare) {
+      if (FuncInfo.PreprocessedDPVDeclares.contains(&DPV))
+        continue;
+      LLVM_DEBUG(dbgs() << "SelectionDAG visiting dbg_declare: " << DPV
+                        << "\n");
+      handleDebugDeclare(DPV.getVariableLocationOp(0), Variable, Expression,
+                         DPV.getDebugLoc());
+      continue;
+    }
+
     // A DPValue with no locations is a kill location.
     SmallVector<Value *, 4> Values(DPV.location_ops());
     if (Values.empty()) {
@@ -6218,61 +6282,15 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
     if (AssignmentTrackingEnabled ||
         FuncInfo.PreprocessedDbgDeclares.count(&DI))
       return;
-    // Assume dbg.declare can not currently use DIArgList, i.e.
-    // it is non-variadic.
-    assert(!DI.hasArgList() && "Only dbg.value should currently use DIArgList");
+    LLVM_DEBUG(dbgs() << "SelectionDAG visiting dbg_declare: " << DI << "\n");
     DILocalVariable *Variable = DI.getVariable();
     DIExpression *Expression = DI.getExpression();
     dropDanglingDebugInfo(Variable, Expression);
-    assert(Variable && "Missing variable");
-    LLVM_DEBUG(dbgs() << "SelectionDAG visiting debug intrinsic: " << DI
-                      << "\n");
-    // Check if address has undef value.
-    const Value *Address = DI.getVariableLocationOp(0);
-    if (!Address || isa<UndefValue>(Address) ||
-        (Address->use_empty() && !isa<Argument>(Address))) {
-      LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI
-                        << " (bad/undef/unused-arg address)\n");
-      return;
-    }
-
-    bool isParameter = Variable->isParameter() || isa<Argument>(Address);
-
-    SDValue &N = NodeMap[Address];
-    if (!N.getNode() && isa<Argument>(Address))
-      // Check unused arguments map.
-      N = UnusedArgNodeMap[Address];
-    SDDbgValue *SDV;
-    if (N.getNode()) {
-      if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
-        Address = BCI->getOperand(0);
-      // Parameters are handled specially.
-      auto FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
-      if (isParameter && FINode) {
-        // Byval parameter. We have a frame index at this point.
-        SDV =
-            DAG.getFrameIndexDbgValue(Variable, Expression, FINode->getIndex(),
-                                      /*IsIndirect*/ true, dl, SDNodeOrder);
-      } else if (isa<Argument>(Address)) {
-        // Address is an argument, so try to emit its dbg value using
-        // virtual register info from the FuncInfo.ValueMap.
-        EmitFuncArgumentDbgValue(Address, Variable, Expression, dl,
-                                 FuncArgumentDbgValueKind::Declare, N);
-        return;
-      } else {
-        SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
-                              true, dl, SDNodeOrder);
-      }
-      DAG.AddDbgValue(SDV, isParameter);
-    } else {
-      // If Address is an argument then try to emit its dbg value using
-      // virtual register info from the FuncInfo.ValueMap.
-      if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl,
-                                    FuncArgumentDbgValueKind::Declare, N)) {
-        LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI
-                          << " (could not emit func-arg dbg_value)\n");
-      }
-    }
+    // Assume dbg.declare can not currently use DIArgList, i.e.
+    // it is non-variadic.
+    assert(!DI.hasArgList() && "Only dbg.value should currently use DIArgList");
+    handleDebugDeclare(DI.getVariableLocationOp(0), Variable, Expression,
+                       DI.getDebugLoc());
     return;
   }
   case Intrinsic::dbg_label: {
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
index 5b55c3461b0b..2e102c002c09 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
@@ -368,6 +368,9 @@ public:
   void handleKillDebugValue(DILocalVariable *Var, DIExpression *Expr,
                             DebugLoc DbgLoc, unsigned Order);
 
+  void handleDebugDeclare(Value *Address, DILocalVariable *Variable,
+                          DIExpression *Expression, DebugLoc DL);
+
   /// Evict any dangling debug information, attempting to salvage it first.
   void resolveOrClearDbgInfo();
 
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index dd28ec09d0e2..a1cf4cbbee1b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -1461,6 +1461,14 @@ static void processDbgDeclares(FunctionLoweringInfo &FuncInfo) {
     if (DI && processDbgDeclare(FuncInfo, DI->getAddress(), DI->getExpression(),
                                 DI->getVariable(), DI->getDebugLoc()))
       FuncInfo.PreprocessedDbgDeclares.insert(DI);
+
+    for (const DPValue &DPV : I.getDbgValueRange()) {
+      if (DPV.getType() == DPValue::LocationType::Declare &&
+          processDbgDeclare(FuncInfo, DPV.getVariableLocationOp(0),
+                            DPV.getExpression(), DPV.getVariable(),
+                            DPV.getDebugLoc()))
+        FuncInfo.PreprocessedDPVDeclares.insert(&DPV);
+    }
   }
 }
 
diff --git a/llvm/test/CodeGen/X86/dbg-combine.ll b/llvm/test/CodeGen/X86/dbg-combine.ll
index b3d2213b90c0..d6065f1318ae 100644
--- a/llvm/test/CodeGen/X86/dbg-combine.ll
+++ b/llvm/test/CodeGen/X86/dbg-combine.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -mtriple x86_64-pc-linux -O0 < %s | FileCheck %s
+; RUN: llc --try-experimental-debuginfo-iterators -mtriple x86_64-pc-linux -O0 < %s | FileCheck %s
 
 ; Make sure that the sequence of debug locations for function foo is correctly
 ; generated. More specifically, .loc entries for lines 4,5,6,7 must appear in
diff --git a/llvm/test/CodeGen/X86/selectiondag-order.ll b/llvm/test/CodeGen/X86/selectiondag-order.ll
index 163e2cb90b2f..417b12bbd73f 100644
--- a/llvm/test/CodeGen/X86/selectiondag-order.ll
+++ b/llvm/test/CodeGen/X86/selectiondag-order.ll
@@ -1,6 +1,7 @@
 ; Check that debug intrinsics do not affect code generation.
 
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck --check-prefix=X86-CHECK %s
+; RUN: llc --try-experimental-debuginfo-iterators < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck --check-prefix=X86-CHECK %s
 
 define i64 @simulate(<2 x i32> %a) {
 entry:
diff --git a/llvm/test/DebugInfo/Generic/2010-06-29-InlinedFnLocalVar.ll b/llvm/test/DebugInfo/Generic/2010-06-29-InlinedFnLocalVar.ll
index 87d75c16dd8e..2a5d5e776b93 100644
--- a/llvm/test/DebugInfo/Generic/2010-06-29-InlinedFnLocalVar.ll
+++ b/llvm/test/DebugInfo/Generic/2010-06-29-InlinedFnLocalVar.ll
@@ -1,4 +1,5 @@
 ; RUN: %llc_dwarf -O2 %s -o - | FileCheck %s
+; RUN: %llc_dwarf --try-experimental-debuginfo-iterators -O2 %s -o - | FileCheck %s
 ; Check struct X for dead variable xyz from inlined function foo.
 
 ; CHECK: {{.section.*debug_info|.*dwinfo:}}
diff --git a/llvm/test/DebugInfo/Mips/InlinedFnLocalVar.ll b/llvm/test/DebugInfo/Mips/InlinedFnLocalVar.ll
index 9e5bc3ed0db5..d4d0ec2d813c 100644
--- a/llvm/test/DebugInfo/Mips/InlinedFnLocalVar.ll
+++ b/llvm/test/DebugInfo/Mips/InlinedFnLocalVar.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -mtriple mips-linux-gnu -O2 %s -o - | FileCheck %s
+; RUN: llc --try-experimental-debuginfo-iterators -mtriple mips-linux-gnu -O2 %s -o - | FileCheck %s
 ; Check struct X for dead variable xyz from inlined function foo.
 
 ; CHECK: .section .debug_info,"",@0x7000001e
diff --git a/llvm/test/DebugInfo/X86/DW_AT_const_value.ll b/llvm/test/DebugInfo/X86/DW_AT_const_value.ll
index 39d718a457d3..ecb423a0a113 100644
--- a/llvm/test/DebugInfo/X86/DW_AT_const_value.ll
+++ b/llvm/test/DebugInfo/X86/DW_AT_const_value.ll
@@ -1,4 +1,5 @@
 ; RUN: llc %s -o - | FileCheck %s
+; RUN: llc --try-experimental-debuginfo-iterators %s -o - | FileCheck %s
 
 ;; Check single location variables of various types with a constant value are
 ;; emitted with a DW_AT_const_value attribute.
diff --git a/llvm/test/DebugInfo/X86/InlinedFnLocalVar.ll b/llvm/test/DebugInfo/X86/InlinedFnLocalVar.ll
index 7f659bf9042a..0b27ec8194a1 100644
--- a/llvm/test/DebugInfo/X86/InlinedFnLocalVar.ll
+++ b/llvm/test/DebugInfo/X86/InlinedFnLocalVar.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -mtriple i686-pc-cygwin -O2 %s -o - | FileCheck %s
+; RUN: llc --try-experimental-debuginfo-iterators -mtriple i686-pc-cygwin -O2 %s -o - | FileCheck %s
 ; Check struct X for dead variable xyz from inlined function foo.
 
 ; CHECK: Lsection_info
diff --git a/llvm/test/DebugInfo/X86/block-capture.ll b/llvm/test/DebugInfo/X86/block-capture.ll
index f78ce32fb34a..585526fea148 100644
--- a/llvm/test/DebugInfo/X86/block-capture.ll
+++ b/llvm/test/DebugInfo/X86/block-capture.ll
@@ -1,6 +1,9 @@
 ; RUN: llc %s -o %t -filetype=obj
 ; RUN: llvm-dwarfdump -v -debug-info %t | FileCheck %s
 
+; RUN: llc --try-experimental-debuginfo-iterators %s -o %t -filetype=obj
+; RUN: llvm-dwarfdump -v -debug-info %t | FileCheck %s
+
 ; Checks that we emit debug info for the block variable declare.
 ; CHECK: DW_TAG_subprogram
 ; CHECK: DW_TAG_variable
diff --git a/llvm/test/DebugInfo/X86/dbg-empty-metadata-lowering.ll b/llvm/test/DebugInfo/X86/dbg-empty-metadata-lowering.ll
index b98e99c53dfe..a5edac3ead50 100644
--- a/llvm/test/DebugInfo/X86/dbg-empty-metadata-lowering.ll
+++ b/llvm/test/DebugInfo/X86/dbg-empty-metadata-lowering.ll
@@ -2,6 +2,9 @@
 ; RUN: | FileCheck %s --implicit-check-not=DBG --check-prefixes=AT-DISABLED,BOTH
 ; RUN: llc %s -stop-after=finalize-isel -o - --try-experimental-debuginfo-iterators \
 ; RUN: | FileCheck %s --implicit-check-not=DBG --check-prefixes=AT-DISABLED,BOTH
+; RUN: llc --try-experimental-debuginfo-iterators %s -stop-after=finalize-isel -o - \
+; RUN: | FileCheck %s --implicit-check-not=DBG --check-prefixes=AT-DISABLED,BOTH
+
 ;; Check that dbg.values with empty metadata are treated as kills (i.e. become
 ;; DBG_VALUE $noreg, ...). dbg.declares with empty metadata location operands
 ;; should be ignored.
@@ -9,6 +12,9 @@
 ; RUN: sed 's/;Uncomment-with-sed//g' < %s \
 ; RUN: | llc -stop-after=finalize-isel -o - \
 ; RUN: | FileCheck %s --implicit-check-not=DBG --check-prefixes=AT-ENABLED,BOTH
+; RUN: sed 's/;Uncomment-with-sed//g' < %s \
+; RUN: | llc --try-experimental-debuginfo-iterators -stop-after=finalize-isel -o - \
+; RUN: | FileCheck %s --implicit-check-not=DBG --check-prefixes=AT-ENABLED,BOTH
 ;; Check the same behaviour occurs with assignment tracking enabled.
 
 ;; First ensure assignment tracking is truly unset/set.
diff --git a/llvm/test/DebugInfo/X86/debug-info-block-captured-self.ll b/llvm/test/DebugInfo/X86/debug-info-block-captured-self.ll
index d96ea5190b86..c70b51f7f8d1 100644
--- a/llvm/test/DebugInfo/X86/debug-info-block-captured-self.ll
+++ b/llvm/test/DebugInfo/X86/debug-info-block-captured-self.ll
@@ -1,6 +1,9 @@
 ; RUN: llc -mtriple x86_64-apple-darwin -filetype=obj -o %t.o < %s
 ; RUN: llvm-dwarfdump %t.o | FileCheck %s
 ;
+; RUN: llc --try-experimental-debuginfo-iterators -mtriple x86_64-apple-darwin -filetype=obj -o %t.o < %s
+; RUN: llvm-dwarfdump %t.o | FileCheck %s
+;
 ; Test that DW_AT_location is generated for a captured "self" inside a
 ; block.
 ;
diff --git a/llvm/test/DebugInfo/X86/debug-info-blocks.ll b/llvm/test/DebugInfo/X86/debug-info-blocks.ll
index 0914fa68620c..5dacd711ad60 100644
--- a/llvm/test/DebugInfo/X86/debug-info-blocks.ll
+++ b/llvm/test/DebugInfo/X86/debug-info-blocks.ll
@@ -1,6 +1,9 @@
 ; RUN: llc -mtriple x86_64-apple-darwin -filetype=obj -o %t.o < %s
 ; RUN: llvm-dwarfdump -v -debug-info %t.o | FileCheck %s
 
+; RUN: llc --try-experimental-debuginfo-iterators -mtriple x86_64-apple-darwin -filetype=obj -o %t.o < %s
+; RUN: llvm-dwarfdump -v -debug-info %t.o | FileCheck %s
+
 ; Generated from llvm/tools/clang/test/CodeGenObjC/debug-info-blocks.m
 ; rdar://problem/9279956
 ; test that the DW_AT_location of self is at ( fbreg +{{[0-9]+}}, deref, +{{[0-9]+}} )
diff --git a/llvm/test/DebugInfo/X86/empty-metadata-dbg-declare.ll b/llvm/test/DebugInfo/X86/empty-metadata-dbg-declare.ll
index 8ae4e7b183e9..241a39f3d899 100644
--- a/llvm/test/DebugInfo/X86/empty-metadata-dbg-declare.ll
+++ b/llvm/test/DebugInfo/X86/empty-metadata-dbg-declare.ll
@@ -1,4 +1,5 @@
 ; RUN: llc %s -stop-after=finalize-isel -o - | FileCheck %s --implicit-check-not=DBG
+; RUN: llc --try-experimental-debuginfo-iterators %s -stop-after=finalize-isel -o - | FileCheck %s --implicit-check-not=DBG
 
 ;; Check that a single "empty metadata" dbg.declare doesn't accidentally cause
 ;; other dbg.declares in the function to go missing.
diff --git a/llvm/test/DebugInfo/X86/pieces-3.ll b/llvm/test/DebugInfo/X86/pieces-3.ll
index dfd7b3c48ef9..60bf758b4985 100644
--- a/llvm/test/DebugInfo/X86/pieces-3.ll
+++ b/llvm/test/DebugInfo/X86/pieces-3.ll
@@ -1,4 +1,5 @@
 ; RUN: llc %s -filetype=obj -o - -experimental-debug-variable-locations=true | llvm-dwarfdump -v - | FileCheck %s
+; RUN: llc --try-experimental-debuginfo-iterators %s -filetype=obj -o - -experimental-debug-variable-locations=true | llvm-dwarfdump -v - | FileCheck %s
 ;
 ;    // Compile with -O1
 ;    typedef struct {
diff --git a/llvm/test/DebugInfo/X86/pieces-4.ll b/llvm/test/DebugInfo/X86/pieces-4.ll
index adc93fc93a2c..aa93bd6a7f5f 100644
--- a/llvm/test/DebugInfo/X86/pieces-4.ll
+++ b/llvm/test/DebugInfo/X86/pieces-4.ll
@@ -1,5 +1,7 @@
 ; RUN: llc < %s -experimental-debug-variable-locations=true | FileCheck %s
 ; RUN: llc -filetype=obj < %s -experimental-debug-variable-locations=true | llvm-dwarfdump -debug-loc - | FileCheck %s --check-prefix=DWARF
+; RUN: llc --try-experimental-debuginfo-iterators < %s -experimental-debug-variable-locations=true | FileCheck %s
+; RUN: llc --try-experimental-debuginfo-iterators -filetype=obj < %s -experimental-debug-variable-locations=true | llvm-dwarfdump -debug-loc - | FileCheck %s --check-prefix=DWARF
 
 ; Compile the following with -O1:
 
diff --git a/llvm/test/DebugInfo/X86/safestack-byval.ll b/llvm/test/DebugInfo/X86/safestack-byval.ll
index acaa8031537c..168cddd80633 100644
--- a/llvm/test/DebugInfo/X86/safestack-byval.ll
+++ b/llvm/test/DebugInfo/X86/safestack-byval.ll
@@ -3,6 +3,8 @@
 ; SafeStack for unsafe byval arguments.
 ; RUN: llc -mtriple=x86_64-unknown-unknown --experimental-debug-variable-locations=false -stop-after finalize-isel %s -o - | FileCheck %s --check-prefixes=CHECK,NORMAL
 ; RUN: llc -mtriple=x86_64-unknown-unknown --experimental-debug-variable-locations -stop-after finalize-isel %s -o - | FileCheck %s --check-prefixes=CHECK,INSTRREF
+; RUN: llc --try-experimental-debuginfo-iterators -mtriple=x86_64-unknown-unknown --experimental-debug-variable-locations=false -stop-after finalize-isel %s -o - | FileCheck %s --check-prefixes=CHECK,NORMAL
+; RUN: llc --try-experimental-debuginfo-iterators -mtriple=x86_64-unknown-unknown --experimental-debug-variable-locations -stop-after finalize-isel %s -o - | FileCheck %s --check-prefixes=CHECK,INSTRREF
 
 ; This was built by compiling the following source with SafeStack and
 ; simplifying the result a little.
diff --git a/llvm/test/DebugInfo/X86/salvage-add-node-indirect.ll b/llvm/test/DebugInfo/X86/salvage-add-node-indirect.ll
index cae8a479a5ad..967721bde8a3 100644
--- a/llvm/test/DebugInfo/X86/salvage-add-node-indirect.ll
+++ b/llvm/test/DebugInfo/X86/salvage-add-node-indirect.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
 ; RUN: llc -mtriple=x86_64 %s -start-before=x86-isel -o - -stop-after=x86-isel | FileCheck %s
+; RUN: llc --try-experimental-debuginfo-iterators -mtriple=x86_64 %s -start-before=x86-isel -o - -stop-after=x86-isel | FileCheck %s
 
 ; Verify that we don't crash due to attempting to turn the indirect debug value
 ; in @test_non_constant variadic when salvaging the ADD node with non-constant
diff --git a/llvm/test/DebugInfo/X86/spill-indirect-nrvo.ll b/llvm/test/DebugInfo/X86/spill-indirect-nrvo.ll
index 0b18318c53a8..b9a504b9b7b6 100644
--- a/llvm/test/DebugInfo/X86/spill-indirect-nrvo.ll
+++ b/llvm/test/DebugInfo/X86/spill-indirect-nrvo.ll
@@ -3,6 +3,13 @@
 ; RUN: llc < %s -experimental-debug-variable-locations=true | FileCheck -check-prefixes=CHECK,OPT %s
 ; RUN: llc -O0 < %s -experimental-debug-variable-locations=true | FileCheck -check-prefixes=CHECK,OPTNONE %s
 
+; RUN: llc --try-experimental-debuginfo-iterators < %s -experimental-debug-variable-locations=false | FileCheck -check-prefixes=CHECK,OPT %s
+;; FIXME: RemoveDIs - enable when FastISel support is added.
+; run: llc --try-experimental-debuginfo-iterators -O0 < %s -experimental-debug-variable-locations=false | FileCheck -check-prefixes=CHECK,OPTNONE %s
+; RUN: llc --try-experimental-debuginfo-iterators < %s -experimental-debug-variable-locations=true | FileCheck -check-prefixes=CHECK,OPT %s
+;; FIXME: RemoveDIs - enable when FastISel support is added.
+; run: llc --try-experimental-debuginfo-iterators -O0 < %s -experimental-debug-variable-locations=true | FileCheck -check-prefixes=CHECK,OPTNONE %s
+
 ; Make sure we insert DW_OP_deref when spilling indirect DBG_VALUE instructions.
 
 ; C++ source:
diff --git a/llvm/test/DebugInfo/X86/spill-nontrivial-param.ll b/llvm/test/DebugInfo/X86/spill-nontrivial-param.ll
index 1e01f2cd9703..9c05b050e733 100644
--- a/llvm/test/DebugInfo/X86/spill-nontrivial-param.ll
+++ b/llvm/test/DebugInfo/X86/spill-nontrivial-param.ll
@@ -1,5 +1,7 @@
 ; RUN: llc < %s -experimental-debug-variable-locations=false | FileCheck %s
 ; RUN: llc < %s -experimental-debug-variable-locations=true | FileCheck %s
+; RUN: llc --try-experimental-debuginfo-iterators < %s -experimental-debug-variable-locations=false | FileCheck %s
+; RUN: llc --try-experimental-debuginfo-iterators < %s -experimental-debug-variable-locations=true | FileCheck %s
 
 ; Make sure we insert DW_OP_deref when spilling indirect DBG_VALUE instructions.
 ; In this example, 'nt' is passed by address because it is not trivially
diff --git a/llvm/test/DebugInfo/X86/sret.ll b/llvm/test/DebugInfo/X86/sret.ll
index 017fc968d427..087f136541d9 100644
--- a/llvm/test/DebugInfo/X86/sret.ll
+++ b/llvm/test/DebugInfo/X86/sret.ll
@@ -1,5 +1,8 @@
 ; RUN: llc -split-dwarf-file=foo.dwo -O0 %s -mtriple=x86_64-unknown-linux-gnu -filetype=obj -o %t
 ; RUN: llvm-dwarfdump -debug-info %t | FileCheck %s --check-prefix=CHECK-DWO
+;; FIXME: RemoveDIs - enable when FastISel support is added.
+; run: llc --try-experimental-debuginfo-iterators -split-dwarf-file=foo.dwo -O0 %s -mtriple=x86_64-unknown-linux-gnu -filetype=obj -o %t
+; run: llvm-dwarfdump -debug-info %t | FileCheck %s --check-prefix=CHECK-DWO
 
 ; Based on the debuginfo-tests/sret.cpp code.
 
@@ -8,6 +11,11 @@
 
 ; RUN: llc -O0 -fast-isel=true -mtriple=x86_64-apple-darwin -filetype=obj -o - %s | llvm-dwarfdump -debug-info - | FileCheck -check-prefixes=CHECK,FASTISEL %s
 ; RUN: llc -O0 -fast-isel=false -mtriple=x86_64-apple-darwin -filetype=obj -o - %s | llvm-dwarfdump -debug-info - | FileCheck -check-prefixes=CHECK,SDAG %s
+
+; RUN: llc --try-experimental-debuginfo-iterators -O0 -fast-isel=false -mtriple=x86_64-apple-darwin -filetype=obj -o - %s | llvm-dwarfdump -debug-info - | FileCheck -check-prefixes=CHECK,SDAG %s
+;; FIXME: RemoveDIs - enable when FastISel support is added.
+; run: llc --try-experimental-debuginfo-iterators -O0 -fast-isel=false -mtriple=x86_64-apple-darwin -filetype=obj -o - %s | llvm-dwarfdump -debug-info - | FileCheck -check-prefixes=CHECK,SDAG %s
+
 ; CHECK: _ZN1B9AInstanceEv
 ; CHECK: DW_TAG_variable
 ; CHECK-NEXT:   DW_AT_location (0x00000000
diff --git a/llvm/test/DebugInfo/X86/union-const.ll b/llvm/test/DebugInfo/X86/union-const.ll
index e9aafc9c228e..1bb5cc26b1fe 100644
--- a/llvm/test/DebugInfo/X86/union-const.ll
+++ b/llvm/test/DebugInfo/X86/union-const.ll
@@ -1,4 +1,6 @@
 ; RUN: llc -filetype=obj < %s | llvm-dwarfdump -v -debug-info - | FileCheck %s
+; RUN: llc --try-experimental-debuginfo-iterators -filetype=obj < %s | llvm-dwarfdump -v -debug-info - | FileCheck %s
+
 ; CHECK: DW_TAG_variable
 ; CHECK-NEXT: DW_AT_const_value [DW_FORM_udata]	(0)
 ; CHECK-NEXT: DW_AT_name {{.*}}"a"
diff --git a/llvm/test/DebugInfo/X86/vla-global.ll b/llvm/test/DebugInfo/X86/vla-global.ll
index d1a85bb7407b..ee43ea166b70 100644
--- a/llvm/test/DebugInfo/X86/vla-global.ll
+++ b/llvm/test/DebugInfo/X86/vla-global.ll
@@ -1,4 +1,6 @@
 ; RUN: llc -mtriple=x86_64-apple-darwin %s -o - -filetype=obj | llvm-dwarfdump - | FileCheck %s
+; RUN: llc --try-experimental-debuginfo-iterators -mtriple=x86_64-apple-darwin %s -o - -filetype=obj | llvm-dwarfdump - | FileCheck %s
+
 ; CHECK: 0x00000[[G:.*]]:     DW_TAG_variable
 ; CHECK-NEXT:                DW_AT_name	("g")
 ; CHECK: DW_TAG_array_type
diff --git a/llvm/test/DebugInfo/X86/vla-multi.ll b/llvm/test/DebugInfo/X86/vla-multi.ll
index 210250ee9d66..911918338c21 100644
--- a/llvm/test/DebugInfo/X86/vla-multi.ll
+++ b/llvm/test/DebugInfo/X86/vla-multi.ll
@@ -1,4 +1,6 @@
 ; RUN: llc -mtriple=x86_64-apple-darwin %s -o - -filetype=obj | llvm-dwarfdump - | FileCheck %s
+; RUN: llc --try-experimental-debuginfo-iterators -mtriple=x86_64-apple-darwin %s -o - -filetype=obj | llvm-dwarfdump - | FileCheck %s
+
 ; Test debug info for multidimensional arrays.
 ;
 ; void f(int i, int j, int k, int r) {
-- 
GitLab


From 6ab663be8da2b2f0a3a59d1ab6935100fb832049 Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Tue, 12 Dec 2023 12:42:28 +0100
Subject: [PATCH 278/349] [LVI] Require UndefAllowed argument to
 getConstantRangeAtUse() (NFC)

For the remaining uses set it to true, matching the current
behavior.
---
 llvm/include/llvm/Analysis/LazyValueInfo.h                | 2 +-
 llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp | 6 ++++--
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/llvm/include/llvm/Analysis/LazyValueInfo.h b/llvm/include/llvm/Analysis/LazyValueInfo.h
index bf2fc47fa642..cb5fa35d2995 100644
--- a/llvm/include/llvm/Analysis/LazyValueInfo.h
+++ b/llvm/include/llvm/Analysis/LazyValueInfo.h
@@ -99,7 +99,7 @@ namespace llvm {
 
     /// Return the ConstantRange constraint that is known to hold for the value
     /// at a specific use-site.
-    ConstantRange getConstantRangeAtUse(const Use &U, bool UndefAllowed = true);
+    ConstantRange getConstantRangeAtUse(const Use &U, bool UndefAllowed);
 
     /// Determine whether the specified value is known to be a
     /// constant on the specified edge.  Return null if not.
diff --git a/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp b/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
index e6d8f89122ff..d2dfc764d042 100644
--- a/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
+++ b/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
@@ -278,8 +278,10 @@ static bool processICmp(ICmpInst *Cmp, LazyValueInfo *LVI) {
   ICmpInst::Predicate UnsignedPred =
       ConstantRange::getEquivalentPredWithFlippedSignedness(
           Cmp->getPredicate(),
-          LVI->getConstantRangeAtUse(Cmp->getOperandUse(0)),
-          LVI->getConstantRangeAtUse(Cmp->getOperandUse(1)));
+          LVI->getConstantRangeAtUse(Cmp->getOperandUse(0),
+                                     /*UndefAllowed*/ true),
+          LVI->getConstantRangeAtUse(Cmp->getOperandUse(1),
+                                     /*UndefAllowed*/ true));
 
   if (UnsignedPred == ICmpInst::Predicate::BAD_ICMP_PREDICATE)
     return false;
-- 
GitLab


From b00e445c4d52bf630147584109a9599004d30b4c Mon Sep 17 00:00:00 2001
From: Guillaume Chatelet <gchatelet@google.com>
Date: Tue, 12 Dec 2023 13:03:26 +0100
Subject: [PATCH 279/349] [libc][NFC] Make EXPONENT_BIAS int32_t (#75046)

`EXPONENT_BIAS` is almost always used with signed arithmetic. Making it
an `int32_t` from the start reduces the chances to run into
implementation defined behavior (cast from unsigned to signed is
implementation-defined until C++20).


https://en.cppreference.com/w/cpp/language/implicit_conversion#:~:text=If%20the%20destination%20type%20is%20signed,arithmetic%20overflow%2C%20which%20is%20undefined).
---
 libc/src/__support/FPUtil/FloatProperties.h |  3 +--
 libc/src/__support/detailed_powers_of_ten.h |  5 ++--
 libc/src/__support/str_to_float.h           | 27 ++++++++++-----------
 libc/src/math/generic/powf.cpp              | 22 +++++++++--------
 4 files changed, 29 insertions(+), 28 deletions(-)

diff --git a/libc/src/__support/FPUtil/FloatProperties.h b/libc/src/__support/FPUtil/FloatProperties.h
index ef6a3cd403db..fcc0ed83c16f 100644
--- a/libc/src/__support/FPUtil/FloatProperties.h
+++ b/libc/src/__support/FPUtil/FloatProperties.h
@@ -165,8 +165,7 @@ public:
   LIBC_INLINE_VAR static constexpr BitsType MANTISSA_MASK =
       mask_trailing_ones<UIntType, MANTISSA_WIDTH>();
   LIBC_INLINE_VAR static constexpr uint32_t EXPONENT_WIDTH = EXP_BITS;
-  LIBC_INLINE_VAR static constexpr uint32_t EXPONENT_BIAS =
-      static_cast<uint32_t>(EXP_BIAS);
+  LIBC_INLINE_VAR static constexpr int32_t EXPONENT_BIAS = EXP_BIAS;
   LIBC_INLINE_VAR static constexpr BitsType SIGN_MASK = SIGN_MASK_;
   LIBC_INLINE_VAR static constexpr BitsType EXPONENT_MASK = EXP_MASK;
   LIBC_INLINE_VAR static constexpr BitsType EXP_MANT_MASK = EXP_MASK | SIG_MASK;
diff --git a/libc/src/__support/detailed_powers_of_ten.h b/libc/src/__support/detailed_powers_of_ten.h
index f9628484bbe6..c8340fda06ee 100644
--- a/libc/src/__support/detailed_powers_of_ten.h
+++ b/libc/src/__support/detailed_powers_of_ten.h
@@ -29,8 +29,9 @@ constexpr int32_t DETAILED_POWERS_OF_TEN_MIN_EXP_10 = -348;
 constexpr int32_t DETAILED_POWERS_OF_TEN_MAX_EXP_10 = 347;
 
 // This rescales the base 10 exponent by a factor of log(10)/log(2).
-LIBC_INLINE int64_t exp10_to_exp2(int64_t exp10) {
-  return (217706 * exp10) >> 16;
+LIBC_INLINE int32_t exp10_to_exp2(int32_t exp10) {
+  // Valid if exp10 < 646 456 636.
+  return static_cast<int32_t>((217706 * static_cast<int64_t>(exp10)) >> 16);
 }
 
 static constexpr uint64_t DETAILED_POWERS_OF_TEN[696][2] = {
diff --git a/libc/src/__support/str_to_float.h b/libc/src/__support/str_to_float.h
index 7ec6b9947ad2..79d35682d0b7 100644
--- a/libc/src/__support/str_to_float.h
+++ b/libc/src/__support/str_to_float.h
@@ -94,8 +94,8 @@ eisel_lemire(ExpandedFloat<T> init_num,
   uint32_t clz = cpp::countl_zero<UIntType>(mantissa);
   mantissa <<= clz;
 
-  uint32_t exp2 = static_cast<uint32_t>(exp10_to_exp2(exp10)) +
-                  BITS_IN_MANTISSA + FloatProp::EXPONENT_BIAS - clz;
+  int32_t exp2 =
+      exp10_to_exp2(exp10) + BITS_IN_MANTISSA + FloatProp::EXPONENT_BIAS - clz;
 
   // Multiplication
   const uint64_t *power_of_ten =
@@ -168,7 +168,7 @@ eisel_lemire(ExpandedFloat<T> init_num,
 
   // The if block is equivalent to (but has fewer branches than):
   //   if exp2 <= 0 || exp2 >= 0x7FF { etc }
-  if (exp2 - 1 >= (1 << FloatProp::EXPONENT_WIDTH) - 2) {
+  if (static_cast<uint32_t>(exp2) - 1 >= (1 << FloatProp::EXPONENT_WIDTH) - 2) {
     return cpp::nullopt;
   }
 
@@ -211,8 +211,8 @@ eisel_lemire<long double>(ExpandedFloat<long double> init_num,
   uint32_t clz = cpp::countl_zero<UIntType>(mantissa);
   mantissa <<= clz;
 
-  uint32_t exp2 = static_cast<uint32_t>(exp10_to_exp2(exp10)) +
-                  BITS_IN_MANTISSA + FloatProp::EXPONENT_BIAS - clz;
+  int32_t exp2 =
+      exp10_to_exp2(exp10) + BITS_IN_MANTISSA + FloatProp::EXPONENT_BIAS - clz;
 
   // Multiplication
   const uint64_t *power_of_ten =
@@ -338,17 +338,16 @@ simple_decimal_conversion(const char *__restrict numStart,
   // If the exponent is too large and can't be represented in this size of
   // float, return inf.
   if (hpd.get_decimal_point() > 0 &&
-      exp10_to_exp2(hpd.get_decimal_point() - 1) >
-          static_cast<int64_t>(FloatProp::EXPONENT_BIAS)) {
-    output.num = {0, FPBits::MAX_EXPONENT};
+      exp10_to_exp2(hpd.get_decimal_point() - 1) > FloatProp::EXPONENT_BIAS) {
+    output.num = {0, fputil::FPBits<T>::MAX_EXPONENT};
     output.error = ERANGE;
     return output;
   }
   // If the exponent is too small even for a subnormal, return 0.
   if (hpd.get_decimal_point() < 0 &&
       exp10_to_exp2(-hpd.get_decimal_point()) >
-          static_cast<int64_t>(FloatProp::EXPONENT_BIAS +
-                               FloatProp::MANTISSA_WIDTH)) {
+          (FloatProp::EXPONENT_BIAS +
+           static_cast<int32_t>(FloatProp::MANTISSA_WIDTH))) {
     output.num = {0, 0};
     output.error = ERANGE;
     return output;
@@ -607,7 +606,7 @@ clinger_fast_path(ExpandedFloat<T> init_num,
 // log10(2^(exponent bias)).
 // The generic approximation uses the fact that log10(2^x) ~= x/3
 template <typename T> constexpr int32_t get_upper_bound() {
-  return static_cast<int32_t>(fputil::FloatProperties<T>::EXPONENT_BIAS) / 3;
+  return fputil::FloatProperties<T>::EXPONENT_BIAS / 3;
 }
 
 template <> constexpr int32_t get_upper_bound<float>() { return 39; }
@@ -623,9 +622,9 @@ template <> constexpr int32_t get_upper_bound<double>() { return 309; }
 // other out, and subnormal numbers allow for the result to be at the very low
 // end of the final mantissa.
 template <typename T> constexpr int32_t get_lower_bound() {
-  return -(static_cast<int32_t>(fputil::FloatProperties<T>::EXPONENT_BIAS +
-                                fputil::FloatProperties<T>::MANTISSA_WIDTH +
-                                (sizeof(T) * 8)) /
+  return -((fputil::FloatProperties<T>::EXPONENT_BIAS +
+            static_cast<int32_t>(fputil::FloatProperties<T>::MANTISSA_WIDTH +
+                                 (sizeof(T) * 8))) /
            3);
 }
 
diff --git a/libc/src/math/generic/powf.cpp b/libc/src/math/generic/powf.cpp
index 17ccb41fc462..efc866618ef2 100644
--- a/libc/src/math/generic/powf.cpp
+++ b/libc/src/math/generic/powf.cpp
@@ -389,22 +389,24 @@ static constexpr DoubleDouble LOG2_R2_DD[] = {
 LIBC_INLINE bool is_odd_integer(float x) {
   using FloatProp = typename fputil::FloatProperties<float>;
   uint32_t x_u = cpp::bit_cast<uint32_t>(x);
-  int x_e = static_cast<int>((x_u & FloatProp::EXPONENT_MASK) >>
-                             FloatProp::MANTISSA_WIDTH);
-  int lsb = cpp::countr_zero(x_u | FloatProp::EXPONENT_MASK);
-  constexpr int UNIT_EXPONENT =
-      static_cast<int>(FloatProp::EXPONENT_BIAS + FloatProp::MANTISSA_WIDTH);
+  int32_t x_e = static_cast<int32_t>((x_u & FloatProp::EXPONENT_MASK) >>
+                                     FloatProp::MANTISSA_WIDTH);
+  int32_t lsb = cpp::countr_zero(x_u | FloatProp::EXPONENT_MASK);
+  constexpr int32_t UNIT_EXPONENT =
+      FloatProp::EXPONENT_BIAS +
+      static_cast<int32_t>(FloatProp::MANTISSA_WIDTH);
   return (x_e + lsb == UNIT_EXPONENT);
 }
 
 LIBC_INLINE bool is_integer(float x) {
   using FloatProp = typename fputil::FloatProperties<float>;
   uint32_t x_u = cpp::bit_cast<uint32_t>(x);
-  int x_e = static_cast<int>((x_u & FloatProp::EXPONENT_MASK) >>
-                             FloatProp::MANTISSA_WIDTH);
-  int lsb = cpp::countr_zero(x_u | FloatProp::EXPONENT_MASK);
-  constexpr int UNIT_EXPONENT =
-      static_cast<int>(FloatProp::EXPONENT_BIAS + FloatProp::MANTISSA_WIDTH);
+  int32_t x_e = static_cast<int32_t>((x_u & FloatProp::EXPONENT_MASK) >>
+                                     FloatProp::MANTISSA_WIDTH);
+  int32_t lsb = cpp::countr_zero(x_u | FloatProp::EXPONENT_MASK);
+  constexpr int32_t UNIT_EXPONENT =
+      FloatProp::EXPONENT_BIAS +
+      static_cast<int32_t>(FloatProp::MANTISSA_WIDTH);
   return (x_e + lsb >= UNIT_EXPONENT);
 }
 
-- 
GitLab


From 198238a598f3b4cfd8cf22e824ff6a3382f5f01e Mon Sep 17 00:00:00 2001
From: Guillaume Chatelet <gchatelet@google.com>
Date: Tue, 12 Dec 2023 13:06:02 +0100
Subject: [PATCH 280/349] [libc][NFC] Remove remaining specializations in
 FloatProperties (#75165)

This patch sinks `EXPLICIT_BIT_MASK` into `get_explicit_mantissa` - the
only function using it. Then it sinks the content of
`FPCommonProperties` directly into `FPProperties`.
---
 libc/src/__support/FPUtil/FloatProperties.h   | 50 +++++--------------
 .../__support/FPUtil/x86_64/LongDoubleBits.h  |  6 ++-
 2 files changed, 18 insertions(+), 38 deletions(-)

diff --git a/libc/src/__support/FPUtil/FloatProperties.h b/libc/src/__support/FPUtil/FloatProperties.h
index fcc0ed83c16f..e72dae60844b 100644
--- a/libc/src/__support/FPUtil/FloatProperties.h
+++ b/libc/src/__support/FPUtil/FloatProperties.h
@@ -90,13 +90,12 @@ template <typename T, size_t count> static constexpr T mask_trailing_ones() {
   return count == 0 ? 0 : ((~T(0)) >> (t_bits - count));
 }
 
-// Derives more properties from 'FPBaseProperties' above.
-// This class serves as a halfway point between 'FPBaseProperties' and
-// 'FPProperties' below.
+} // namespace internal
+
 template <FPType fp_type>
-struct FPCommonProperties : private FPBaseProperties<fp_type> {
+struct FPProperties : public internal::FPBaseProperties<fp_type> {
 private:
-  using UP = FPBaseProperties<fp_type>;
+  using UP = internal::FPBaseProperties<fp_type>;
   using UP::EXP_BITS;
   using UP::SIG_BITS;
   using UP::TOTAL_BITS;
@@ -123,15 +122,15 @@ private:
 
   // Masks
   LIBC_INLINE_VAR static constexpr UIntType SIG_MASK =
-      mask_trailing_ones<UIntType, SIG_BITS>() << SIG_MASK_SHIFT;
+      internal::mask_trailing_ones<UIntType, SIG_BITS>() << SIG_MASK_SHIFT;
   LIBC_INLINE_VAR static constexpr UIntType EXP_MASK =
-      mask_trailing_ones<UIntType, EXP_BITS>() << EXP_MASK_SHIFT;
+      internal::mask_trailing_ones<UIntType, EXP_BITS>() << EXP_MASK_SHIFT;
   // Trailing underscore on SIGN_MASK_ is temporary - it will be removed
   // once we can replace the public part below with the private one.
   LIBC_INLINE_VAR static constexpr UIntType SIGN_MASK_ =
-      mask_trailing_ones<UIntType, SIGN_BITS>() << SIGN_MASK_SHIFT;
+      internal::mask_trailing_ones<UIntType, SIGN_BITS>() << SIGN_MASK_SHIFT;
   LIBC_INLINE_VAR static constexpr UIntType FP_MASK =
-      mask_trailing_ones<UIntType, TOTAL_BITS>();
+      internal::mask_trailing_ones<UIntType, TOTAL_BITS>();
   static_assert((SIG_MASK & EXP_MASK & SIGN_MASK_) == 0, "masks disjoint");
   static_assert((SIG_MASK | EXP_MASK | SIGN_MASK_) == FP_MASK, "masks cover");
 
@@ -140,19 +139,19 @@ private:
   }
 
   LIBC_INLINE_VAR static constexpr UIntType QNAN_MASK =
-      UP::ENCODING == FPEncoding::X86_ExtendedPrecision
+      UP::ENCODING == internal::FPEncoding::X86_ExtendedPrecision
           ? bit_at(SIG_BITS - 1) | bit_at(SIG_BITS - 2) // 0b1100...
           : bit_at(SIG_BITS - 1);                       // 0b1000...
 
   LIBC_INLINE_VAR static constexpr UIntType SNAN_MASK =
-      UP::ENCODING == FPEncoding::X86_ExtendedPrecision
+      UP::ENCODING == internal::FPEncoding::X86_ExtendedPrecision
           ? bit_at(SIG_BITS - 1) | bit_at(SIG_BITS - 3) // 0b1010...
           : bit_at(SIG_BITS - 2);                       // 0b0100...
 
   // The number of bits after the decimal dot when the number if in normal form.
   LIBC_INLINE_VAR static constexpr int FRACTION_BITS =
-      UP::ENCODING == FPEncoding::X86_ExtendedPrecision ? SIG_BITS - 1
-                                                        : SIG_BITS;
+      UP::ENCODING == internal::FPEncoding::X86_ExtendedPrecision ? SIG_BITS - 1
+                                                                  : SIG_BITS;
 
 public:
   // Public facing API to keep the change local to this file.
@@ -163,7 +162,7 @@ public:
   LIBC_INLINE_VAR static constexpr uint32_t MANTISSA_PRECISION =
       MANTISSA_WIDTH + 1;
   LIBC_INLINE_VAR static constexpr BitsType MANTISSA_MASK =
-      mask_trailing_ones<UIntType, MANTISSA_WIDTH>();
+      internal::mask_trailing_ones<UIntType, MANTISSA_WIDTH>();
   LIBC_INLINE_VAR static constexpr uint32_t EXPONENT_WIDTH = EXP_BITS;
   LIBC_INLINE_VAR static constexpr int32_t EXPONENT_BIAS = EXP_BIAS;
   LIBC_INLINE_VAR static constexpr BitsType SIGN_MASK = SIGN_MASK_;
@@ -176,29 +175,6 @@ public:
   static constexpr BitsType QUIET_NAN_MASK = QNAN_MASK;
 };
 
-} // namespace internal
-
-template <FPType fp_type>
-struct FPProperties : public internal::FPCommonProperties<fp_type> {};
-
-// ----------------
-// Work In Progress
-// ----------------
-// The 'FPProperties' template specializations below are being slowly replaced
-// with properties from 'FPCommonProperties' above. Once specializations are
-// empty, 'FPProperties' declaration can be fully replace with
-// 'FPCommonProperties' implementation.
-
-// Properties for numbers represented in 80 bits long double on non-Windows x86
-// platforms.
-template <>
-struct FPProperties<FPType::X86_Binary80>
-    : public internal::FPCommonProperties<FPType::X86_Binary80> {
-  // The x86 80 bit float represents the leading digit of the mantissa
-  // explicitly. This is the mask for that bit.
-  static constexpr BitsType EXPLICIT_BIT_MASK = (BitsType(1) << MANTISSA_WIDTH);
-};
-
 //-----------------------------------------------------------------------------
 template <typename FP> LIBC_INLINE static constexpr FPType get_fp_type() {
   if constexpr (cpp::is_same_v<FP, float> && __FLT_MANT_DIG__ == 24)
diff --git a/libc/src/__support/FPUtil/x86_64/LongDoubleBits.h b/libc/src/__support/FPUtil/x86_64/LongDoubleBits.h
index bbc30ff7a376..60953313a695 100644
--- a/libc/src/__support/FPUtil/x86_64/LongDoubleBits.h
+++ b/libc/src/__support/FPUtil/x86_64/LongDoubleBits.h
@@ -68,7 +68,11 @@ template <> struct FPBits<long double> {
   }
 
   LIBC_INLINE constexpr UIntType get_explicit_mantissa() const {
-    return bits & (FloatProp::MANTISSA_MASK | FloatProp::EXPLICIT_BIT_MASK);
+    // The x86 80 bit float represents the leading digit of the mantissa
+    // explicitly. This is the mask for that bit.
+    constexpr UIntType EXPLICIT_BIT_MASK =
+        (UIntType(1) << FloatProp::MANTISSA_WIDTH);
+    return bits & (FloatProp::MANTISSA_MASK | EXPLICIT_BIT_MASK);
   }
 
   LIBC_INLINE constexpr void set_biased_exponent(UIntType expVal) {
-- 
GitLab


From 06c4f78b07aba34c155c792b71587720901ad144 Mon Sep 17 00:00:00 2001
From: lorenzo chelini <l.chelini@icloud.com>
Date: Tue, 12 Dec 2023 13:06:17 +0100
Subject: [PATCH 281/349] [MLIR][Linalg] improve silenceable failure msg for
 `lower_pack` (NFC) (#75053)

Adjust the silenceable failure message as we lower `tensor.unpack` as a
combination of `linalg.transpose` + `tensor.collapse_shape` and
`tensor.extract_slice`.
---
 .../TransformOps/LinalgTransformOps.cpp       |  7 +++--
 .../Dialect/Linalg/transform-lower-pack.mlir  | 31 +++++++++++++++++--
 2 files changed, 33 insertions(+), 5 deletions(-)

diff --git a/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp b/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
index 54055aefbc51..5254aac976f4 100644
--- a/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
+++ b/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
@@ -1125,8 +1125,11 @@ DiagnosedSilenceableFailure transform::LowerUnPackOp::applyToOne(
   rewriter.setInsertionPoint(target);
   FailureOr<LowerUnPackOpResult> res = lowerUnPack(rewriter, target);
   if (failed(res)) {
-    return mlir::emitSilenceableFailure(target->getLoc())
-           << "cannot rewrite to pad + expand + transpose";
+    DiagnosedSilenceableFailure diag =
+        emitSilenceableError()
+        << "cannot lower to transpose + collapse + extract";
+    diag.attachNote(target->getLoc()) << "target payload op";
+    return diag;
   }
   transformResults.push_back(res->emptyOp);
   transformResults.push_back(res->transposeOp);
diff --git a/mlir/test/Dialect/Linalg/transform-lower-pack.mlir b/mlir/test/Dialect/Linalg/transform-lower-pack.mlir
index 435ae1a1ae06..b9706eed54b6 100644
--- a/mlir/test/Dialect/Linalg/transform-lower-pack.mlir
+++ b/mlir/test/Dialect/Linalg/transform-lower-pack.mlir
@@ -1,4 +1,4 @@
-// RUN: mlir-opt %s -transform-interpreter -cse --split-input-file | FileCheck %s
+// RUN: mlir-opt %s -transform-interpreter -cse -verify-diagnostics -split-input-file | FileCheck %s
 
   // CHECK-LABEL: func.func @pack(
 func.func @pack(%arg0: tensor<129x47x16x16xf32>, %arg1: tensor<17x2x16x16x32x8xf32>) -> tensor<17x2x16x16x32x8xf32> {
@@ -143,9 +143,9 @@ func.func @unpack(%arg0: tensor<17x2x16x16x32x8xf32>, %arg1: tensor<129x47x16x16
   // CHECK-SAME:   : tensor<136x64x16x16xf32> to tensor<129x47x16x16xf32>
   //      CHECK: linalg.copy ins(%[[SLICE]] : tensor<129x47x16x16xf32>)
   // CHECK-SAME:        outs(%[[ARG1]] : tensor<129x47x16x16xf32>)
-  %pack = tensor.unpack %arg0 inner_dims_pos = [1, 0] inner_tiles = [32, 8] into %arg1
+  %unpack = tensor.unpack %arg0 inner_dims_pos = [1, 0] inner_tiles = [32, 8] into %arg1
     : tensor<17x2x16x16x32x8xf32> -> tensor<129x47x16x16xf32>
-  return %pack : tensor<129x47x16x16xf32>
+  return %unpack : tensor<129x47x16x16xf32>
 }
 
 module attributes {transform.with_named_sequence} {
@@ -162,6 +162,7 @@ module attributes {transform.with_named_sequence} {
 }
 
 // -----
+
 // When an unpack is a plain 'unpad', lower it to a simple extract_slice.
 // CHECK-LABEL: func.func @unpack_as_pad(
 func.func @unpack_as_pad(%arg0: tensor<1x1x1x1x136x64x16x16xf32>, %arg1: tensor<129x47x16x16xf32>) -> tensor<129x47x16x16xf32> {
@@ -460,3 +461,27 @@ module attributes {transform.with_named_sequence} {
           transform.yield
   }
 }
+
+// -----
+
+// At the moment, we cannot lower tensor.unpack with outer_dims_perm.
+func.func @diagnostic_unpack(%arg0: tensor<32x64xf32>, %arg1: tensor<2x4x32x8xf32>) -> tensor<32x64xf32> {
+  // expected-note @below {{target payload op}}
+  %unpack = tensor.unpack %arg1 outer_dims_perm = [1, 0] 
+    inner_dims_pos = [1, 0] inner_tiles = [32, 8] into %arg0 : tensor<2x4x32x8xf32> -> tensor<32x64xf32>
+  return %unpack : tensor<32x64xf32>
+}
+
+module attributes {transform.with_named_sequence} {
+  transform.named_sequence @__transform_main(%module_op: !transform.any_op {transform.readonly}) {
+    %unpack = transform.structured.match ops{["tensor.unpack"]} in %module_op
+      : (!transform.any_op) -> !transform.op<"tensor.unpack">
+    // expected-error @below {{cannot lower to transpose + collapse + extract}} 
+    transform.structured.lower_unpack %unpack : (!transform.op<"tensor.unpack">)
+      -> (!transform.op<"tensor.empty">,
+          !transform.op<"linalg.transpose">,
+          !transform.op<"tensor.collapse_shape">,
+          !transform.op<"tensor.extract_slice">)
+          transform.yield
+  }
+}
-- 
GitLab


From 0c2b6a022595c55ba3d091e3014b5d3b0e213259 Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Tue, 12 Dec 2023 13:06:52 +0100
Subject: [PATCH 282/349] [LVI] Drop bitcast handling (NFCI)

The code only works on integer casts, and the only bitcasts
involving integers are trivial. The code as previously written
would try to handle things like float to integer bitcasts by
fetching a ConstantRange of a float value, which is an ill-defined
operation.
---
 llvm/lib/Analysis/LazyValueInfo.cpp | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/llvm/lib/Analysis/LazyValueInfo.cpp b/llvm/lib/Analysis/LazyValueInfo.cpp
index 45f7f049ceb9..ec870694f5b6 100644
--- a/llvm/lib/Analysis/LazyValueInfo.cpp
+++ b/llvm/lib/Analysis/LazyValueInfo.cpp
@@ -903,11 +903,6 @@ LazyValueInfoImpl::getRangeFor(Value *V, Instruction *CxtI, BasicBlock *BB) {
 
 std::optional<ValueLatticeElement>
 LazyValueInfoImpl::solveBlockValueCast(CastInst *CI, BasicBlock *BB) {
-  // Without knowing how wide the input is, we can't analyze it in any useful
-  // way.
-  if (!CI->getOperand(0)->getType()->isSized())
-    return ValueLatticeElement::getOverdefined();
-
   // Filter out casts we don't know how to reason about before attempting to
   // recurse on our operand.  This can cut a long search short if we know we're
   // not going to be able to get any useful information anways.
@@ -915,7 +910,6 @@ LazyValueInfoImpl::solveBlockValueCast(CastInst *CI, BasicBlock *BB) {
   case Instruction::Trunc:
   case Instruction::SExt:
   case Instruction::ZExt:
-  case Instruction::BitCast:
     break;
   default:
     // Unhandled instructions are overdefined.
-- 
GitLab


From dfb7d56a05ca3e36a792a35bd89e4fe25473da04 Mon Sep 17 00:00:00 2001
From: jeanPerier <jperier@nvidia.com>
Date: Tue, 12 Dec 2023 13:20:42 +0100
Subject: [PATCH 283/349] [flang] Lower VALUE derived types in BIND(C)
 interface (#74847)

VALUE derived type are passed by reference outside of BIND(C) interface.
The ABI is much simpler and it is possible for these arguments to have
the OPTIONAL attribute.

In the BIND(C) context, these arguments must follow the C ABI for
struct, which may lead the data to be passed in register. OPTIONAL is
also forbidden for those arguments, so it is safe to directly use the
fir.type<T> type for the func.func argument.

Codegen is in charge of later applying the C passing ABI according to
the target (https://github.com/llvm/llvm-project/pull/74829).
---
 flang/lib/Lower/ConvertCall.cpp               | 17 +++++++--
 flang/lib/Lower/ConvertVariable.cpp           |  2 -
 .../test/Lower/HLFIR/bindc-value-derived.f90  | 37 +++++++++++++++++++
 3 files changed, 50 insertions(+), 6 deletions(-)
 create mode 100644 flang/test/Lower/HLFIR/bindc-value-derived.f90

diff --git a/flang/lib/Lower/ConvertCall.cpp b/flang/lib/Lower/ConvertCall.cpp
index 81f4c0a2c6d2..49e70181a668 100644
--- a/flang/lib/Lower/ConvertCall.cpp
+++ b/flang/lib/Lower/ConvertCall.cpp
@@ -360,9 +360,8 @@ fir::ExtendedValue Fortran::lower::genCallOpAndResult(
       if (fir::isa_builtin_cptr_type(fromTy) &&
           Fortran::lower::isCPtrArgByValueType(snd)) {
         cast = genRecordCPtrValueArg(builder, loc, fst, fromTy);
-      } else if (fir::isa_derived(snd)) {
-        // FIXME: This seems like a serious bug elsewhere in lowering. Paper
-        // over the problem for now.
+      } else if (fir::isa_derived(snd) && !fir::isa_derived(fst.getType())) {
+        // TODO: remove this TODO once the old lowering is gone.
         TODO(loc, "derived type argument passed by value");
       } else {
         cast = builder.convertWithSemantics(loc, snd, fst,
@@ -1188,8 +1187,18 @@ genUserCall(Fortran::lower::PreparedActualArguments &loweredActuals,
           value =
               hlfir::Entity{genRecordCPtrValueArg(builder, loc, value, eleTy)};
         }
+      } else if (fir::isa_derived(value.getFortranElementType())) {
+        // BIND(C), VALUE derived type. The derived type value must really
+        // be loaded here.
+        auto [derived, cleanup] = hlfir::convertToValue(loc, builder, value);
+        mlir::Value loadedValue = fir::getBase(derived);
+        if (fir::isa_ref_type(loadedValue.getType()))
+          loadedValue = builder.create<fir::LoadOp>(loc, loadedValue);
+        caller.placeInput(arg, loadedValue);
+        if (cleanup)
+          (*cleanup)();
+        break;
       }
-
       caller.placeInput(arg, builder.createConvert(loc, argTy, value));
     } break;
     case PassBy::BaseAddressValueAttribute:
diff --git a/flang/lib/Lower/ConvertVariable.cpp b/flang/lib/Lower/ConvertVariable.cpp
index 676fecdb52a8..364de33d00a6 100644
--- a/flang/lib/Lower/ConvertVariable.cpp
+++ b/flang/lib/Lower/ConvertVariable.cpp
@@ -2138,8 +2138,6 @@ void Fortran::lower::mapSymbolAttributes(
       if (isCptrByVal || !fir::conformsWithPassByRef(argType)) {
         // Dummy argument passed in register. Place the value in memory at that
         // point since lowering expect symbols to be mapped to memory addresses.
-        if (argType.isa<fir::RecordType>())
-          TODO(loc, "derived type argument passed by value");
         mlir::Type symType = converter.genType(sym);
         addr = builder.create<fir::AllocaOp>(loc, symType);
         if (isCptrByVal) {
diff --git a/flang/test/Lower/HLFIR/bindc-value-derived.f90 b/flang/test/Lower/HLFIR/bindc-value-derived.f90
new file mode 100644
index 000000000000..671e6d45b9a9
--- /dev/null
+++ b/flang/test/Lower/HLFIR/bindc-value-derived.f90
@@ -0,0 +1,37 @@
+! Test lowering of derived types passed with VALUE attribute in BIND(C)
+! interface. They are passed as fir.type<T> value. The actual C struct
+! passing ABI is done in code generation according to the target.
+
+! RUN: bbc -emit-hlfir -o - -I nw %s 2>&1 | FileCheck %s
+
+module bindc_byval
+  type, bind(c) :: t
+    integer :: i
+  end type
+contains
+  subroutine test(x) bind(c)
+    type(t), value :: x
+    call use_it(x%i)
+  end subroutine
+! CHECK-LABEL:   func.func @test(
+! CHECK-SAME:                    %[[VAL_0:.*]]: !fir.type<_QMbindc_byvalTt{i:i32}> {fir.bindc_name = "x"}) attributes {fir.bindc_name = "test"} {
+! CHECK:           %[[VAL_1:.*]] = fir.alloca !fir.type<_QMbindc_byvalTt{i:i32}>
+! CHECK:           fir.store %[[VAL_0]] to %[[VAL_1]] : !fir.ref<!fir.type<_QMbindc_byvalTt{i:i32}>>
+! CHECK:           %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_1]] {fortran_attrs = #fir.var_attrs<value>, uniq_name = "_QMbindc_byvalFtestEx"} : (!fir.ref<!fir.type<_QMbindc_byvalTt{i:i32}>>) -> (!fir.ref<!fir.type<_QMbindc_byvalTt{i:i32}>>, !fir.ref<!fir.type<_QMbindc_byvalTt{i:i32}>>)
+! CHECK:           %[[VAL_3:.*]] = hlfir.designate %[[VAL_2]]#0{"i"}   : (!fir.ref<!fir.type<_QMbindc_byvalTt{i:i32}>>) -> !fir.ref<i32>
+! CHECK:           fir.call @_QPuse_it(%[[VAL_3]]) fastmath<contract> : (!fir.ref<i32>) -> ()
+! CHECK:           return
+! CHECK:         }
+
+  subroutine call_it(x)
+    type(t) x
+    call test(x)
+  end subroutine
+! CHECK-LABEL:   func.func @_QMbindc_byvalPcall_it(
+! CHECK-SAME:                                      %[[VAL_0:.*]]: !fir.ref<!fir.type<_QMbindc_byvalTt{i:i32}>> {fir.bindc_name = "x"}) {
+! CHECK:           %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QMbindc_byvalFcall_itEx"} : (!fir.ref<!fir.type<_QMbindc_byvalTt{i:i32}>>) -> (!fir.ref<!fir.type<_QMbindc_byvalTt{i:i32}>>, !fir.ref<!fir.type<_QMbindc_byvalTt{i:i32}>>)
+! CHECK:           %[[VAL_2:.*]] = fir.load %[[VAL_1]]#1 : !fir.ref<!fir.type<_QMbindc_byvalTt{i:i32}>>
+! CHECK:           fir.call @test(%[[VAL_2]]) fastmath<contract> : (!fir.type<_QMbindc_byvalTt{i:i32}>) -> ()
+! CHECK:           return
+! CHECK:         }
+end module
-- 
GitLab


From dd85e67dc4869df2f207531626d766c1b4cfd19e Mon Sep 17 00:00:00 2001
From: Guillaume Chatelet <gchatelet@google.com>
Date: Tue, 12 Dec 2023 13:23:21 +0100
Subject: [PATCH 284/349] [libc] Add mask functions to math_extras (#75169)

---
 libc/src/__support/FPUtil/CMakeLists.txt      |  1 +
 libc/src/__support/FPUtil/FloatProperties.h   | 21 +++++----------
 libc/src/__support/math_extras.h              | 26 ++++++++++++++++++-
 libc/test/src/__support/math_extras_test.cpp  | 25 ++++++++++++++++--
 .../llvm-project-overlay/libc/BUILD.bazel     |  1 +
 5 files changed, 56 insertions(+), 18 deletions(-)

diff --git a/libc/src/__support/FPUtil/CMakeLists.txt b/libc/src/__support/FPUtil/CMakeLists.txt
index 3d6d712fc205..1cb22536a1cf 100644
--- a/libc/src/__support/FPUtil/CMakeLists.txt
+++ b/libc/src/__support/FPUtil/CMakeLists.txt
@@ -30,6 +30,7 @@ add_header_library(
   DEPENDS
     libc.src.__support.macros.properties.float
     libc.src.__support.uint128
+    libc.src.__support.math_extras
 )
 
 add_header_library(
diff --git a/libc/src/__support/FPUtil/FloatProperties.h b/libc/src/__support/FPUtil/FloatProperties.h
index e72dae60844b..04da5c031f88 100644
--- a/libc/src/__support/FPUtil/FloatProperties.h
+++ b/libc/src/__support/FPUtil/FloatProperties.h
@@ -12,6 +12,7 @@
 #include "src/__support/UInt128.h"
 #include "src/__support/macros/attributes.h" // LIBC_INLINE, LIBC_INLINE_VAR
 #include "src/__support/macros/properties/float.h" // LIBC_COMPILER_HAS_FLOAT128
+#include "src/__support/math_extras.h"             // mask_trailing_ones
 
 #include <stdint.h>
 
@@ -80,16 +81,6 @@ template <> struct FPBaseProperties<FPType::X86_Binary80> {
       FPEncoding::X86_ExtendedPrecision;
 };
 
-// TODO: Move this utility elsewhere.
-template <typename T, size_t count> static constexpr T mask_trailing_ones() {
-  static_assert(cpp::is_unsigned_v<T>);
-  constexpr unsigned t_bits = CHAR_BIT * sizeof(T);
-  static_assert(count <= t_bits && "Invalid bit index");
-  // It's important not to initialize T with -1, since T may be BigInt which
-  // will take -1 as a uint64_t and only initialize the low 64 bits.
-  return count == 0 ? 0 : ((~T(0)) >> (t_bits - count));
-}
-
 } // namespace internal
 
 template <FPType fp_type>
@@ -122,15 +113,15 @@ private:
 
   // Masks
   LIBC_INLINE_VAR static constexpr UIntType SIG_MASK =
-      internal::mask_trailing_ones<UIntType, SIG_BITS>() << SIG_MASK_SHIFT;
+      mask_trailing_ones<UIntType, SIG_BITS>() << SIG_MASK_SHIFT;
   LIBC_INLINE_VAR static constexpr UIntType EXP_MASK =
-      internal::mask_trailing_ones<UIntType, EXP_BITS>() << EXP_MASK_SHIFT;
+      mask_trailing_ones<UIntType, EXP_BITS>() << EXP_MASK_SHIFT;
   // Trailing underscore on SIGN_MASK_ is temporary - it will be removed
   // once we can replace the public part below with the private one.
   LIBC_INLINE_VAR static constexpr UIntType SIGN_MASK_ =
-      internal::mask_trailing_ones<UIntType, SIGN_BITS>() << SIGN_MASK_SHIFT;
+      mask_trailing_ones<UIntType, SIGN_BITS>() << SIGN_MASK_SHIFT;
   LIBC_INLINE_VAR static constexpr UIntType FP_MASK =
-      internal::mask_trailing_ones<UIntType, TOTAL_BITS>();
+      mask_trailing_ones<UIntType, TOTAL_BITS>();
   static_assert((SIG_MASK & EXP_MASK & SIGN_MASK_) == 0, "masks disjoint");
   static_assert((SIG_MASK | EXP_MASK | SIGN_MASK_) == FP_MASK, "masks cover");
 
@@ -162,7 +153,7 @@ public:
   LIBC_INLINE_VAR static constexpr uint32_t MANTISSA_PRECISION =
       MANTISSA_WIDTH + 1;
   LIBC_INLINE_VAR static constexpr BitsType MANTISSA_MASK =
-      internal::mask_trailing_ones<UIntType, MANTISSA_WIDTH>();
+      mask_trailing_ones<UIntType, MANTISSA_WIDTH>();
   LIBC_INLINE_VAR static constexpr uint32_t EXPONENT_WIDTH = EXP_BITS;
   LIBC_INLINE_VAR static constexpr int32_t EXPONENT_BIAS = EXP_BIAS;
   LIBC_INLINE_VAR static constexpr BitsType SIGN_MASK = SIGN_MASK_;
diff --git a/libc/src/__support/math_extras.h b/libc/src/__support/math_extras.h
index 860cdda8586d..89bd0b72669e 100644
--- a/libc/src/__support/math_extras.h
+++ b/libc/src/__support/math_extras.h
@@ -10,12 +10,36 @@
 #ifndef LLVM_LIBC_SRC___SUPPORT_MATH_EXTRAS_H
 #define LLVM_LIBC_SRC___SUPPORT_MATH_EXTRAS_H
 
-#include "src/__support/CPP/type_traits.h"
+#include "src/__support/CPP/type_traits.h"   // is_unsigned_v
 #include "src/__support/macros/attributes.h" // LIBC_INLINE
 #include "src/__support/macros/config.h"     // LIBC_HAS_BUILTIN
 
+#include <limits.h> // CHAR_BIT
+
 namespace LIBC_NAMESPACE {
 
+// Create a bitmask with the count right-most bits set to 1, and all other bits
+// set to 0.  Only unsigned types are allowed.
+template <typename T, size_t count>
+LIBC_INLINE constexpr T mask_trailing_ones() {
+  static_assert(cpp::is_unsigned_v<T>);
+  constexpr unsigned t_bits = CHAR_BIT * sizeof(T);
+  static_assert(count <= t_bits && "Invalid bit index");
+  // It's important not to initialize T with -1, since T may be BigInt which
+  // will take -1 as a uint64_t and only initialize the low 64 bits.
+  constexpr T all_zeroes(0);
+  constexpr T all_ones(~all_zeroes); // bitwise NOT performs integer promotion.
+  return count == 0 ? 0 : (all_ones >> (t_bits - count));
+}
+
+// Create a bitmask with the count left-most bits set to 1, and all other bits
+// set to 0.  Only unsigned types are allowed.
+template <typename T, size_t count>
+LIBC_INLINE constexpr T mask_leading_ones() {
+  constexpr T mask(mask_trailing_ones<T, CHAR_BIT * sizeof(T) - count>());
+  return T(~mask); // bitwise NOT performs integer promotion.
+}
+
 // Add with carry
 template <typename T> struct SumCarry {
   T sum;
diff --git a/libc/test/src/__support/math_extras_test.cpp b/libc/test/src/__support/math_extras_test.cpp
index 48c8fe95c689..e55d995592cc 100644
--- a/libc/test/src/__support/math_extras_test.cpp
+++ b/libc/test/src/__support/math_extras_test.cpp
@@ -11,8 +11,29 @@
 
 namespace LIBC_NAMESPACE {
 
-TEST(LlvmLibcBlockMathExtrasTest, TODO) {
-  // TODO Implement me.
+TEST(LlvmLibcBlockMathExtrasTest, mask_trailing_ones) {
+  EXPECT_EQ(uint8_t(0), (mask_leading_ones<uint8_t, 0>()));
+  EXPECT_EQ(uint8_t(0), (mask_trailing_ones<uint8_t, 0>()));
+  EXPECT_EQ(uint16_t(0), (mask_leading_ones<uint16_t, 0>()));
+  EXPECT_EQ(uint16_t(0), (mask_trailing_ones<uint16_t, 0>()));
+  EXPECT_EQ(uint32_t(0), (mask_leading_ones<uint32_t, 0>()));
+  EXPECT_EQ(uint32_t(0), (mask_trailing_ones<uint32_t, 0>()));
+  EXPECT_EQ(uint64_t(0), (mask_leading_ones<uint64_t, 0>()));
+  EXPECT_EQ(uint64_t(0), (mask_trailing_ones<uint64_t, 0>()));
+
+  EXPECT_EQ(uint32_t(0x00000003), (mask_trailing_ones<uint32_t, 2>()));
+  EXPECT_EQ(uint32_t(0xC0000000), (mask_leading_ones<uint32_t, 2>()));
+
+  EXPECT_EQ(uint32_t(0x000007FF), (mask_trailing_ones<uint32_t, 11>()));
+  EXPECT_EQ(uint32_t(0xFFE00000), (mask_leading_ones<uint32_t, 11>()));
+
+  EXPECT_EQ(uint32_t(0xFFFFFFFF), (mask_trailing_ones<uint32_t, 32>()));
+  EXPECT_EQ(uint32_t(0xFFFFFFFF), (mask_leading_ones<uint32_t, 32>()));
+  EXPECT_EQ(uint64_t(0xFFFFFFFFFFFFFFFF), (mask_trailing_ones<uint64_t, 64>()));
+  EXPECT_EQ(uint64_t(0xFFFFFFFFFFFFFFFF), (mask_leading_ones<uint64_t, 64>()));
+
+  EXPECT_EQ(uint64_t(0x0000FFFFFFFFFFFF), (mask_trailing_ones<uint64_t, 48>()));
+  EXPECT_EQ(uint64_t(0xFFFFFFFFFFFF0000), (mask_leading_ones<uint64_t, 48>()));
 }
 
 } // namespace LIBC_NAMESPACE
diff --git a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel
index 95d6f9d220c2..b9bdb8f7c6d3 100644
--- a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+++ b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel
@@ -664,6 +664,7 @@ libc_support_library(
     deps = [
         ":__support_macros_attributes",
         ":__support_macros_properties_float",
+        ":__support_math_extras",
         ":__support_uint128",
     ],
 )
-- 
GitLab


From a2161154334355e9ecdf3cc3a0303b9481aad897 Mon Sep 17 00:00:00 2001
From: David Green <david.green@arm.com>
Date: Tue, 12 Dec 2023 12:39:21 +0000
Subject: [PATCH 285/349] [Flang] Add a HLFIR Minloc intrinsic (#74436)

The adds a hlfir minloc intrinsic, similar to the minval intrinsic
already added, to help in the lowering of minloc. The idea is to later
add maxloc too, and from there add a simplification for producing minloc
with inlined elemental and hopefully less temporaries.
---
 .../include/flang/Optimizer/HLFIR/HLFIROps.td |  26 ++
 flang/lib/Lower/HlfirIntrinsics.cpp           |  65 +++
 flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp     | 113 ++++--
 .../HLFIR/Transforms/LowerHLFIRIntrinsics.cpp |  38 +-
 flang/test/HLFIR/invalid.fir                  |  68 ++++
 flang/test/HLFIR/memory-effects.fir           |  15 +
 flang/test/HLFIR/minloc-lowering.fir          | 329 ++++++++++++++++
 flang/test/HLFIR/minloc.fir                   | 272 +++++++++++++
 flang/test/Lower/HLFIR/minloc.f90             | 370 ++++++++++++++++++
 flang/test/Lower/HLFIR/transformational.f90   |  28 +-
 10 files changed, 1263 insertions(+), 61 deletions(-)
 create mode 100644 flang/test/HLFIR/minloc-lowering.fir
 create mode 100644 flang/test/HLFIR/minloc.fir
 create mode 100644 flang/test/Lower/HLFIR/minloc.f90

diff --git a/flang/include/flang/Optimizer/HLFIR/HLFIROps.td b/flang/include/flang/Optimizer/HLFIR/HLFIROps.td
index f4933785a8ca..1f5bc42c43e6 100644
--- a/flang/include/flang/Optimizer/HLFIR/HLFIROps.td
+++ b/flang/include/flang/Optimizer/HLFIR/HLFIROps.td
@@ -458,6 +458,32 @@ def hlfir_MinvalOp : hlfir_Op<"minval", [AttrSizedOperandSegments,
   let hasVerifier = 1;
 }
 
+def hlfir_MinlocOp : hlfir_Op<"minloc", [AttrSizedOperandSegments,
+    DeclareOpInterfaceMethods<ArithFastMathInterface>,
+    DeclareOpInterfaceMethods<MemoryEffectsOpInterface>]> {
+  let summary = "MINLOC transformational intrinsic";
+  let description = [{
+    Minlocs of an array.
+  }];
+
+  let arguments = (ins
+    AnyFortranArrayObject:$array,
+    Optional<AnyIntegerType>:$dim,
+    Optional<AnyFortranLogicalOrI1ArrayObject>:$mask,
+    Optional<Type<AnyLogicalLike.predicate>>:$back,
+    DefaultValuedAttr<Arith_FastMathAttr,
+                      "::mlir::arith::FastMathFlags::none">:$fastmath
+  );
+
+  let results = (outs AnyFortranValue);
+
+  let assemblyFormat = [{
+    $array (`dim` $dim^)? (`mask` $mask^)? (`back` $back^)?  attr-dict `:` functional-type(operands, results)
+  }];
+
+  let hasVerifier = 1;
+}
+
 def hlfir_ProductOp : hlfir_Op<"product", [AttrSizedOperandSegments,
     DeclareOpInterfaceMethods<ArithFastMathInterface>,
     DeclareOpInterfaceMethods<MemoryEffectsOpInterface>]> {
diff --git a/flang/lib/Lower/HlfirIntrinsics.cpp b/flang/lib/Lower/HlfirIntrinsics.cpp
index 9f764b614252..6e5ba92bee86 100644
--- a/flang/lib/Lower/HlfirIntrinsics.cpp
+++ b/flang/lib/Lower/HlfirIntrinsics.cpp
@@ -93,6 +93,19 @@ using HlfirMinvalLowering = HlfirReductionIntrinsic<hlfir::MinvalOp, true>;
 using HlfirAnyLowering = HlfirReductionIntrinsic<hlfir::AnyOp, false>;
 using HlfirAllLowering = HlfirReductionIntrinsic<hlfir::AllOp, false>;
 
+template <typename OP>
+class HlfirMinMaxLocIntrinsic : public HlfirTransformationalIntrinsic {
+public:
+  using HlfirTransformationalIntrinsic::HlfirTransformationalIntrinsic;
+
+protected:
+  mlir::Value
+  lowerImpl(const Fortran::lower::PreparedActualArguments &loweredActuals,
+            const fir::IntrinsicArgumentLoweringRules *argLowering,
+            mlir::Type stmtResultType) override;
+};
+using HlfirMinlocLowering = HlfirMinMaxLocIntrinsic<hlfir::MinlocOp>;
+
 template <typename OP>
 class HlfirProductIntrinsic : public HlfirTransformationalIntrinsic {
 public:
@@ -180,6 +193,31 @@ mlir::Value HlfirTransformationalIntrinsic::loadBoxAddress(
   return boxOrAbsent;
 }
 
+static mlir::Value loadOptionalValue(
+    mlir::Location loc, fir::FirOpBuilder &builder,
+    const std::optional<Fortran::lower::PreparedActualArgument> &arg,
+    hlfir::Entity actual) {
+  if (!arg->handleDynamicOptional())
+    return hlfir::loadTrivialScalar(loc, builder, actual);
+
+  mlir::Value isPresent = arg->getIsPresent();
+  mlir::Type eleType = hlfir::getFortranElementType(actual.getType());
+  return builder
+      .genIfOp(loc, {eleType}, isPresent,
+               /*withElseRegion=*/true)
+      .genThen([&]() {
+        assert(actual.isScalar() && fir::isa_trivial(eleType) &&
+               "must be a numerical or logical scalar");
+        hlfir::Entity val = hlfir::loadTrivialScalar(loc, builder, actual);
+        builder.create<fir::ResultOp>(loc, val);
+      })
+      .genElse([&]() {
+        mlir::Value zero = fir::factory::createZeroValue(builder, loc, eleType);
+        builder.create<fir::ResultOp>(loc, zero);
+      })
+      .getResults()[0];
+}
+
 llvm::SmallVector<mlir::Value> HlfirTransformationalIntrinsic::getOperandVector(
     const Fortran::lower::PreparedActualArguments &loweredActuals,
     const fir::IntrinsicArgumentLoweringRules *argLowering) {
@@ -206,6 +244,9 @@ llvm::SmallVector<mlir::Value> HlfirTransformationalIntrinsic::getOperandVector(
       else if (!argRules.handleDynamicOptional &&
                argRules.lowerAs != fir::LowerIntrinsicArgAs::Inquired)
         valArg = hlfir::derefPointersAndAllocatables(loc, builder, actual);
+      else if (argRules.handleDynamicOptional &&
+               argRules.lowerAs == fir::LowerIntrinsicArgAs::Value)
+        valArg = loadOptionalValue(loc, builder, arg, actual);
       else if (argRules.handleDynamicOptional)
         TODO(loc, "hlfir transformational intrinsic dynamically optional "
                   "argument without box lowering");
@@ -260,6 +301,27 @@ mlir::Value HlfirReductionIntrinsic<OP, HAS_MASK>::lowerImpl(
   return op;
 }
 
+template <typename OP>
+mlir::Value HlfirMinMaxLocIntrinsic<OP>::lowerImpl(
+    const Fortran::lower::PreparedActualArguments &loweredActuals,
+    const fir::IntrinsicArgumentLoweringRules *argLowering,
+    mlir::Type stmtResultType) {
+  auto operands = getOperandVector(loweredActuals, argLowering);
+  mlir::Value array = operands[0];
+  mlir::Value dim = operands[1];
+  mlir::Value mask = operands[2];
+  mlir::Value back = operands[4];
+  // dim, mask and back can be NULL if these arguments are not given.
+  if (dim)
+    dim = hlfir::loadTrivialScalar(loc, builder, hlfir::Entity{dim});
+  if (back)
+    back = hlfir::loadTrivialScalar(loc, builder, hlfir::Entity{back});
+
+  mlir::Type resultTy = computeResultType(array, stmtResultType);
+
+  return createOp<OP>(resultTy, array, dim, mask, back);
+}
+
 template <typename OP>
 mlir::Value HlfirProductIntrinsic<OP>::lowerImpl(
     const Fortran::lower::PreparedActualArguments &loweredActuals,
@@ -364,6 +426,9 @@ std::optional<hlfir::EntityWithAttributes> Fortran::lower::lowerHlfirIntrinsic(
   if (name == "minval")
     return HlfirMinvalLowering{builder, loc}.lower(loweredActuals, argLowering,
                                                    stmtResultType);
+  if (name == "minloc")
+    return HlfirMinlocLowering{builder, loc}.lower(loweredActuals, argLowering,
+                                                   stmtResultType);
   if (mlir::isa<fir::CharacterType>(stmtResultType)) {
     if (name == "min")
       return HlfirCharExtremumLowering{builder, loc,
diff --git a/flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp b/flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
index a276e5fc65dd..6af2888b3a60 100644
--- a/flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
+++ b/flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
@@ -661,12 +661,7 @@ void hlfir::ConcatOp::getEffects(
 
 template <typename NumericalReductionOp>
 static mlir::LogicalResult
-verifyNumericalReductionOp(NumericalReductionOp reductionOp) {
-  mlir::Operation *op = reductionOp->getOperation();
-
-  auto results = op->getResultTypes();
-  assert(results.size() == 1);
-
+verifyArrayAndMaskForReductionOp(NumericalReductionOp reductionOp) {
   mlir::Value array = reductionOp->getArray();
   mlir::Value dim = reductionOp->getDim();
   mlir::Value mask = reductionOp->getMask();
@@ -674,7 +669,6 @@ verifyNumericalReductionOp(NumericalReductionOp reductionOp) {
   fir::SequenceType arrayTy =
       hlfir::getFortranElementOrSequenceType(array.getType())
           .cast<fir::SequenceType>();
-  mlir::Type numTy = arrayTy.getEleTy();
   llvm::ArrayRef<int64_t> arrayShape = arrayTy.getShape();
 
   if (mask) {
@@ -701,6 +695,27 @@ verifyNumericalReductionOp(NumericalReductionOp reductionOp) {
       }
     }
   }
+  return mlir::success();
+}
+
+template <typename NumericalReductionOp>
+static mlir::LogicalResult
+verifyNumericalReductionOp(NumericalReductionOp reductionOp) {
+  mlir::Operation *op = reductionOp->getOperation();
+  auto results = op->getResultTypes();
+  assert(results.size() == 1);
+
+  auto res = verifyArrayAndMaskForReductionOp(reductionOp);
+  if (failed(res))
+    return res;
+
+  mlir::Value array = reductionOp->getArray();
+  mlir::Value dim = reductionOp->getDim();
+  fir::SequenceType arrayTy =
+      hlfir::getFortranElementOrSequenceType(array.getType())
+          .cast<fir::SequenceType>();
+  mlir::Type numTy = arrayTy.getEleTy();
+  llvm::ArrayRef<int64_t> arrayShape = arrayTy.getShape();
 
   mlir::Type resultType = results[0];
   if (hlfir::isFortranScalarNumericalType(resultType)) {
@@ -757,45 +772,21 @@ template <typename CharacterReductionOp>
 static mlir::LogicalResult
 verifyCharacterReductionOp(CharacterReductionOp reductionOp) {
   mlir::Operation *op = reductionOp->getOperation();
-
   auto results = op->getResultTypes();
   assert(results.size() == 1);
 
+  auto res = verifyArrayAndMaskForReductionOp(reductionOp);
+  if (failed(res))
+    return res;
+
   mlir::Value array = reductionOp->getArray();
   mlir::Value dim = reductionOp->getDim();
-  mlir::Value mask = reductionOp->getMask();
-
   fir::SequenceType arrayTy =
       hlfir::getFortranElementOrSequenceType(array.getType())
           .cast<fir::SequenceType>();
   mlir::Type numTy = arrayTy.getEleTy();
   llvm::ArrayRef<int64_t> arrayShape = arrayTy.getShape();
 
-  if (mask) {
-    fir::SequenceType maskSeq =
-        hlfir::getFortranElementOrSequenceType(mask.getType())
-            .dyn_cast<fir::SequenceType>();
-    llvm::ArrayRef<int64_t> maskShape;
-
-    if (maskSeq)
-      maskShape = maskSeq.getShape();
-
-    if (!maskShape.empty()) {
-      if (maskShape.size() != arrayShape.size())
-        return reductionOp->emitWarning("MASK must be conformable to ARRAY");
-      static_assert(fir::SequenceType::getUnknownExtent() ==
-                    hlfir::ExprType::getUnknownExtent());
-      constexpr int64_t unknownExtent = fir::SequenceType::getUnknownExtent();
-      for (std::size_t i = 0; i < arrayShape.size(); ++i) {
-        int64_t arrayExtent = arrayShape[i];
-        int64_t maskExtent = maskShape[i];
-        if ((arrayExtent != maskExtent) && (arrayExtent != unknownExtent) &&
-            (maskExtent != unknownExtent))
-          return reductionOp->emitWarning("MASK must be conformable to ARRAY");
-      }
-    }
-  }
-
   auto resultExpr = results[0].cast<hlfir::ExprType>();
   mlir::Type resultType = resultExpr.getEleTy();
   assert(mlir::isa<fir::CharacterType>(resultType) &&
@@ -870,6 +861,58 @@ void hlfir::MinvalOp::getEffects(
   getIntrinsicEffects(getOperation(), effects);
 }
 
+//===----------------------------------------------------------------------===//
+// MinlocOp
+//===----------------------------------------------------------------------===//
+
+mlir::LogicalResult hlfir::MinlocOp::verify() {
+  mlir::Operation *op = getOperation();
+  auto results = op->getResultTypes();
+  assert(results.size() == 1);
+
+  auto res = verifyArrayAndMaskForReductionOp(this);
+  if (failed(res))
+    return res;
+
+  mlir::Value array = getArray();
+  mlir::Value dim = getDim();
+  fir::SequenceType arrayTy =
+      hlfir::getFortranElementOrSequenceType(array.getType())
+          .cast<fir::SequenceType>();
+  llvm::ArrayRef<int64_t> arrayShape = arrayTy.getShape();
+
+  mlir::Type resultType = results[0];
+  if (dim && arrayShape.size() == 1) {
+    if (!fir::isa_integer(resultType))
+      return emitOpError("result must be scalar integer");
+  } else if (auto resultExpr =
+                 mlir::dyn_cast_or_null<hlfir::ExprType>(resultType)) {
+    if (!resultExpr.isArray())
+      return emitOpError("result must be an array");
+
+    if (!fir::isa_integer(resultExpr.getEleTy()))
+      return emitOpError("result must have integer elements");
+
+    llvm::ArrayRef<int64_t> resultShape = resultExpr.getShape();
+    // With dim the result has rank n-1
+    if (dim && resultShape.size() != (arrayShape.size() - 1))
+      return emitOpError("result rank must be one less than ARRAY");
+    // With dim the result has rank n
+    if (!dim && resultShape.size() != 1)
+      return emitOpError("result rank must be 1");
+  } else {
+    return emitOpError("result must be of numerical expr type");
+  }
+  return mlir::success();
+}
+
+void hlfir::MinlocOp::getEffects(
+    llvm::SmallVectorImpl<
+        mlir::SideEffects::EffectInstance<mlir::MemoryEffects::Effect>>
+        &effects) {
+  getIntrinsicEffects(getOperation(), effects);
+}
+
 //===----------------------------------------------------------------------===//
 // SetLengthOp
 //===----------------------------------------------------------------------===//
diff --git a/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp b/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp
index f2628fcb970b..bfebe26fe1d5 100644
--- a/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp
+++ b/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp
@@ -201,6 +201,23 @@ protected:
     return lowerArguments(operation, inArgs, rewriter, argLowering);
   };
 
+  auto buildMinMaxLocArgs(OP operation, mlir::Type i32, mlir::Type logicalType,
+                          mlir::PatternRewriter &rewriter, std::string opName,
+                          fir::FirOpBuilder builder) const {
+    llvm::SmallVector<IntrinsicArgument, 3> inArgs;
+    inArgs.push_back({operation.getArray(), operation.getArray().getType()});
+    inArgs.push_back({operation.getDim(), i32});
+    inArgs.push_back({operation.getMask(), logicalType});
+    mlir::Type T = hlfir::getFortranElementType(operation.getType());
+    unsigned width = T.cast<mlir::IntegerType>().getWidth();
+    mlir::Value kind =
+        builder.createIntegerConstant(operation->getLoc(), i32, width / 8);
+    inArgs.push_back({kind, i32});
+    inArgs.push_back({operation.getBack(), i32});
+    auto *argLowering = fir::getIntrinsicArgumentLowering(opName);
+    return lowerArguments(operation, inArgs, rewriter, argLowering);
+  };
+
   auto buildLogicalArgs(OP operation, mlir::Type i32, mlir::Type logicalType,
                         mlir::PatternRewriter &rewriter,
                         std::string opName) const {
@@ -224,6 +241,8 @@ public:
       opName = "maxval";
     } else if constexpr (std::is_same_v<OP, hlfir::MinvalOp>) {
       opName = "minval";
+    } else if constexpr (std::is_same_v<OP, hlfir::MinlocOp>) {
+      opName = "minloc";
     } else if constexpr (std::is_same_v<OP, hlfir::AnyOp>) {
       opName = "any";
     } else if constexpr (std::is_same_v<OP, hlfir::AllOp>) {
@@ -246,6 +265,9 @@ public:
                   std::is_same_v<OP, hlfir::MaxvalOp> ||
                   std::is_same_v<OP, hlfir::MinvalOp>) {
       args = buildNumericalArgs(operation, i32, logicalType, rewriter, opName);
+    } else if constexpr (std::is_same_v<OP, hlfir::MinlocOp>) {
+      args = buildMinMaxLocArgs(operation, i32, logicalType, rewriter, opName,
+                                builder);
     } else {
       args = buildLogicalArgs(operation, i32, logicalType, rewriter, opName);
     }
@@ -269,6 +291,8 @@ using MaxvalOpConversion = HlfirReductionIntrinsicConversion<hlfir::MaxvalOp>;
 
 using MinvalOpConversion = HlfirReductionIntrinsicConversion<hlfir::MinvalOp>;
 
+using MinlocOpConversion = HlfirReductionIntrinsicConversion<hlfir::MinlocOp>;
+
 using AnyOpConversion = HlfirReductionIntrinsicConversion<hlfir::AnyOp>;
 
 using AllOpConversion = HlfirReductionIntrinsicConversion<hlfir::AllOp>;
@@ -441,12 +465,12 @@ public:
     mlir::ModuleOp module = this->getOperation();
     mlir::MLIRContext *context = &getContext();
     mlir::RewritePatternSet patterns(context);
-    patterns
-        .insert<MatmulOpConversion, MatmulTransposeOpConversion,
-                AllOpConversion, AnyOpConversion, SumOpConversion,
-                ProductOpConversion, TransposeOpConversion, CountOpConversion,
-                DotProductOpConversion, MaxvalOpConversion, MinvalOpConversion>(
-            context);
+    patterns.insert<MatmulOpConversion, MatmulTransposeOpConversion,
+                    AllOpConversion, AnyOpConversion, SumOpConversion,
+                    ProductOpConversion, TransposeOpConversion,
+                    CountOpConversion, DotProductOpConversion,
+                    MaxvalOpConversion, MinvalOpConversion, MinlocOpConversion>(
+        context);
     mlir::ConversionTarget target(*context);
     target.addLegalDialect<mlir::BuiltinDialect, mlir::arith::ArithDialect,
                            mlir::func::FuncDialect, fir::FIROpsDialect,
@@ -454,7 +478,7 @@ public:
     target.addIllegalOp<hlfir::MatmulOp, hlfir::MatmulTransposeOp, hlfir::SumOp,
                         hlfir::ProductOp, hlfir::TransposeOp, hlfir::AnyOp,
                         hlfir::AllOp, hlfir::DotProductOp, hlfir::CountOp,
-                        hlfir::MaxvalOp, hlfir::MinvalOp>();
+                        hlfir::MaxvalOp, hlfir::MinvalOp, hlfir::MinlocOp>();
     target.markUnknownOpDynamicallyLegal(
         [](mlir::Operation *) { return true; });
     if (mlir::failed(
diff --git a/flang/test/HLFIR/invalid.fir b/flang/test/HLFIR/invalid.fir
index 09165f09766b..ce0d728749b9 100644
--- a/flang/test/HLFIR/invalid.fir
+++ b/flang/test/HLFIR/invalid.fir
@@ -548,6 +548,74 @@ func.func @bad_minval13(%arg0: !hlfir.expr<?x?x!fir.char<1,?>>, %arg1: i32){
   %0 = hlfir.minval %arg0 dim %arg1 : (!hlfir.expr<?x?x!fir.char<1,?>>, i32) -> !hlfir.expr<!fir.char<1,?>>
 }
 
+// -----
+func.func @bad_minloc1(%arg0: !hlfir.expr<?xi32>, %arg1: i32, %arg2: !fir.box<!fir.logical<4>>) {
+  // expected-error@+1 {{'hlfir.minloc' op result must be scalar integer}}
+  %0 = hlfir.minloc %arg0 dim %arg1 mask %arg2 : (!hlfir.expr<?xi32>, i32, !fir.box<!fir.logical<4>>) -> f32
+}
+
+// -----
+func.func @bad_minloc2(%arg0: !hlfir.expr<?xi32>, %arg1: i32, %arg2: !fir.box<!fir.array<?x?x?x?x?x!fir.logical<4>>>) {
+  // expected-warning@+1 {{MASK must be conformable to ARRAY}}
+  %0 = hlfir.minloc %arg0 dim %arg1 mask %arg2 : (!hlfir.expr<?xi32>, i32, !fir.box<!fir.array<?x?x?x?x?x!fir.logical<4>>>) -> !hlfir.expr<i32>
+}
+
+// -----
+func.func @bad_minloc3(%arg0: !hlfir.expr<?x5x?xi32>, %arg1: i32, %arg2: !fir.box<!fir.array<2x6x?x!fir.logical<4>>>) {
+  // expected-warning@+1 {{MASK must be conformable to ARRAY}}
+  %0 = hlfir.minloc %arg0 dim %arg1 mask %arg2 : (!hlfir.expr<?x5x?xi32>, i32, !fir.box<!fir.array<2x6x?x!fir.logical<4>>>) -> !hlfir.expr<i32>
+}
+
+// -----
+func.func @bad_minloc4(%arg0: !hlfir.expr<?x?xi32>, %arg1: i32, %arg2: !fir.box<!fir.logical<4>>) {
+  // expected-error@+1 {{'hlfir.minloc' op result rank must be one less than ARRAY}}
+  %0 = hlfir.minloc %arg0 dim %arg1 mask %arg2 : (!hlfir.expr<?x?xi32>, i32, !fir.box<!fir.logical<4>>) -> !hlfir.expr<?x?xi32>
+}
+
+// -----
+func.func @bad_minloc5(%arg0: !hlfir.expr<?xi32>, %arg1: i32, %arg2: !fir.box<!fir.logical<4>>) {
+  // expected-error@+1 {{'hlfir.minloc' op result must be scalar integer}}
+  %0 = hlfir.minloc %arg0 dim %arg1 mask %arg2 : (!hlfir.expr<?xi32>, i32, !fir.box<!fir.logical<4>>) -> !fir.logical<4>
+}
+
+// -----
+func.func @bad_minloc6(%arg0: !hlfir.expr<?x?xi32>, %arg1: i32){
+  // expected-error@+1 {{'hlfir.minloc' op result must be an array}}
+  %0 = hlfir.minloc %arg0 dim %arg1 : (!hlfir.expr<?x?xi32>, i32) -> !hlfir.expr<i32>
+}
+
+// -----
+func.func @bad_minloc7(%arg0: !hlfir.expr<?xi32>){
+  // expected-error@+1 {{'hlfir.minloc' op result must be of numerical expr type}}
+  %0 = hlfir.minloc %arg0 : (!hlfir.expr<?xi32>) -> i32
+}
+
+// -----
+func.func @bad_minloc8(%arg0: !hlfir.expr<?xi32>){
+  // expected-error@+1 {{'hlfir.minloc' op result must have integer elements}}
+  %0 = hlfir.minloc %arg0 : (!hlfir.expr<?xi32>) -> !hlfir.expr<?xf32>
+}
+
+// -----
+func.func @bad_minloc9(%arg0: !hlfir.expr<?x!fir.char<1,?>>, %arg1: i32, %arg2: !fir.box<!fir.array<?x?x?x?x?x!fir.logical<4>>>) {
+  // expected-warning@+1 {{MASK must be conformable to ARRAY}}
+  %0 = hlfir.minloc %arg0 dim %arg1 mask %arg2 : (!hlfir.expr<?x!fir.char<1,?>>, i32, !fir.box<!fir.array<?x?x?x?x?x!fir.logical<4>>>) -> !hlfir.expr<!fir.char<1,?>>
+}
+
+// -----
+func.func @bad_minloc10(%arg0: !hlfir.expr<?x5x?x!fir.char<1,?>>, %arg1: i32, %arg2: !fir.box<!fir.array<2x6x?x!fir.logical<4>>>) {
+  // expected-warning@+1 {{MASK must be conformable to ARRAY}}
+  %0 = hlfir.minloc %arg0 dim %arg1 mask %arg2 : (!hlfir.expr<?x5x?x!fir.char<1,?>>, i32, !fir.box<!fir.array<2x6x?x!fir.logical<4>>>) -> !hlfir.expr<!fir.char<1,?>>
+}
+
+// -----
+func.func @bad_minloc11(%arg0: !hlfir.expr<?x?x!fir.char<1,?>>, %arg1: i32, %arg2: !fir.box<!fir.logical<4>>) {
+  // expected-error@+1 {{'hlfir.minloc' op result rank must be one less than ARRAY}}
+  %0 = hlfir.minloc %arg0 dim %arg1 mask %arg2 : (!hlfir.expr<?x?x!fir.char<1,?>>, i32, !fir.box<!fir.logical<4>>) -> !hlfir.expr<?x?xi32>
+}
+
+
+
 // -----
 func.func @bad_product1(%arg0: !hlfir.expr<?xi32>, %arg1: i32, %arg2: !fir.box<!fir.logical<4>>) {
   // expected-error@+1 {{'hlfir.product' op result must have the same element type as ARRAY argument}}
diff --git a/flang/test/HLFIR/memory-effects.fir b/flang/test/HLFIR/memory-effects.fir
index 4b2a0d575db1..c68c71f43a17 100644
--- a/flang/test/HLFIR/memory-effects.fir
+++ b/flang/test/HLFIR/memory-effects.fir
@@ -122,6 +122,21 @@ func.func @minval_effects(%arg0: !fir.ref<!fir.array<2x2xf32>>, %arg1: i32) {
   return
 }
 
+func.func @minloc_effects_simple(%arg0: !hlfir.expr<?xf32>) {
+// expected-remark@+1 {{found an instance of 'allocate' on a value, on resource '<Default>'}}
+  %minloc = hlfir.minloc %arg0 : (!hlfir.expr<?xf32>) -> !hlfir.expr<?xi32>
+// expected-remark@+1 {{operation has no memory effects}}
+  return
+}
+
+func.func @minloc_effects(%arg0: !fir.ref<!fir.array<2x2xf32>>, %arg1: i32) {
+// expected-remark@+2 {{found an instance of 'allocate' on a value, on resource '<Default>'}}
+// expected-remark@+1 {{found an instance of 'read' on a value, on resource '<Default>'}}
+  %minloc = hlfir.minloc %arg0 dim %arg1 : (!fir.ref<!fir.array<2x2xf32>>, i32) -> !hlfir.expr<2xi32>
+// expected-remark@+1 {{operation has no memory effects}}
+  return
+}
+
 func.func @dot_product_no_effects(%arg0: !hlfir.expr<?xf32>, %arg1: !hlfir.expr<?xf32>) {
 // expected-remark@+1 {{operation has no memory effects}}
   %0 = hlfir.dot_product %arg0 %arg1 : (!hlfir.expr<?xf32>, !hlfir.expr<?xf32>) -> f32
diff --git a/flang/test/HLFIR/minloc-lowering.fir b/flang/test/HLFIR/minloc-lowering.fir
new file mode 100644
index 000000000000..fede0a195012
--- /dev/null
+++ b/flang/test/HLFIR/minloc-lowering.fir
@@ -0,0 +1,329 @@
+// Test hlfir.minloc operation lowering to fir runtime call
+// RUN: fir-opt %s -lower-hlfir-intrinsics | FileCheck %s
+
+// simple one argument minloc
+func.func @_QPminloc1(%arg0: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "a"}, %arg1: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "s"}) {
+  %0:2 = hlfir.declare %arg0 {uniq_name = "_QFminloc1Ea"} : (!fir.box<!fir.array<?xi32>>) -> (!fir.box<!fir.array<?xi32>>, !fir.box<!fir.array<?xi32>>)
+  %1:2 = hlfir.declare %arg1 {uniq_name = "_QFminloc1Es"} : (!fir.box<!fir.array<?xi32>>) -> (!fir.box<!fir.array<?xi32>>, !fir.box<!fir.array<?xi32>>)
+  %2 = hlfir.minloc %0#0 {fastmath = #arith.fastmath<contract>} : (!fir.box<!fir.array<?xi32>>) -> !hlfir.expr<?xi32>
+  hlfir.assign %2 to %1#0 : !hlfir.expr<?xi32>, !fir.box<!fir.array<?xi32>>
+  hlfir.destroy %2 : !hlfir.expr<?xi32>
+  return
+}
+// CHECK-LABEL: func.func @_QPminloc1(
+// CHECK:           %[[ARG0:.*]]: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "a"}
+// CHECK:           %[[ARG1:.*]]: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "s"}
+// CHECK-NEXT:    %[[V0:.*]] = fir.alloca !fir.box<!fir.heap<!fir.array<?xi32>>>
+// CHECK-NEXT:    %[[V1:.*]]:2 = hlfir.declare %[[ARG0]] {uniq_name = "_QFminloc1Ea"} : (!fir.box<!fir.array<?xi32>>) -> (!fir.box<!fir.array<?xi32>>, !fir.box<!fir.array<?xi32>>)
+// CHECK-NEXT:    %[[V2:.*]]:2 = hlfir.declare %[[ARG1]] {uniq_name = "_QFminloc1Es"} : (!fir.box<!fir.array<?xi32>>) -> (!fir.box<!fir.array<?xi32>>, !fir.box<!fir.array<?xi32>>)
+// CHECK-NEXT:    %c4_i32 = arith.constant 4 : i32
+// CHECK-NEXT:    %[[V3:.*]] = fir.absent !fir.box<i1>
+// CHECK-NEXT:    %false = arith.constant false
+// CHECK-NEXT:    %[[V4:.*]] = fir.zero_bits !fir.heap<!fir.array<?xi32>>
+// CHECK-NEXT:    %c0 = arith.constant 0 : index
+// CHECK-NEXT:    %[[V5:.*]] = fir.shape %c0 : (index) -> !fir.shape<1>
+// CHECK-NEXT:    %[[V6:.*]] = fir.embox %[[V4]](%[[V5]]) : (!fir.heap<!fir.array<?xi32>>, !fir.shape<1>) -> !fir.box<!fir.heap<!fir.array<?xi32>>>
+// CHECK-NEXT:    fir.store %[[V6]] to %[[V0]] : !fir.ref<!fir.box<!fir.heap<!fir.array<?xi32>>>>
+// CHECK:         %[[V8:.*]] = fir.convert %[[V0]] : (!fir.ref<!fir.box<!fir.heap<!fir.array<?xi32>>>>) -> !fir.ref<!fir.box<none>>
+// CHECK-NEXT:    %[[V9:.*]] = fir.convert %[[V1]]#1 : (!fir.box<!fir.array<?xi32>>) -> !fir.box<none>
+// CHECK:         %[[V12:.*]] = fir.convert %[[V3]] : (!fir.box<i1>) -> !fir.box<none>
+// CHECK-NEXT:    %[[V13:.*]] = fir.call @_FortranAMinlocInteger4(%[[V8]], %[[V9]], %c4_i32, {{.*}}, {{.*}}, %[[V12]], %false) fastmath<contract> : (!fir.ref<!fir.box<none>>, !fir.box<none>, i32, !fir.ref<i8>, i32, !fir.box<none>, i1) -> none
+// CHECK-NEXT:    %[[V14:.*]] = fir.load %[[V0]] : !fir.ref<!fir.box<!fir.heap<!fir.array<?xi32>>>>
+// CHECK-NEXT:    %c0_0 = arith.constant 0 : index
+// CHECK-NEXT:    %[[V15:.*]]:3 = fir.box_dims %[[V14]], %c0_0 : (!fir.box<!fir.heap<!fir.array<?xi32>>>, index) -> (index, index, index)
+// CHECK-NEXT:    %[[V16:.*]] = fir.box_addr %[[V14]] : (!fir.box<!fir.heap<!fir.array<?xi32>>>) -> !fir.heap<!fir.array<?xi32>>
+// CHECK-NEXT:    %[[V17:.*]] = fir.shape_shift %[[V15]]#0, %[[V15]]#1 : (index, index) -> !fir.shapeshift<1>
+// CHECK-NEXT:    %[[V18:.*]]:2 = hlfir.declare %[[V16]](%[[V17]]) {uniq_name = ".tmp.intrinsic_result"} : (!fir.heap<!fir.array<?xi32>>, !fir.shapeshift<1>) -> (!fir.box<!fir.array<?xi32>>, !fir.heap<!fir.array<?xi32>>)
+// CHECK-NEXT:    %true = arith.constant true
+// CHECK-NEXT:    %[[V19:.*]] = hlfir.as_expr %[[V18]]#0 move %true : (!fir.box<!fir.array<?xi32>>, i1) -> !hlfir.expr<?xi32>
+// CHECK-NEXT:    hlfir.assign %[[V19]] to %[[V2]]#0 : !hlfir.expr<?xi32>, !fir.box<!fir.array<?xi32>>
+// CHECK-NEXT:    hlfir.destroy %[[V19]] : !hlfir.expr<?xi32>
+
+
+// minloc with a dim
+func.func @_QPminloc2(%arg0: !fir.box<!fir.array<?x?xi32>> {fir.bindc_name = "a"}, %arg1: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "s"}, %arg2: !fir.ref<index> {fir.bindc_name = "d"}) {
+  %0:2 = hlfir.declare %arg0 {uniq_name = "_QFminloc2Ea"} : (!fir.box<!fir.array<?x?xi32>>) -> (!fir.box<!fir.array<?x?xi32>>, !fir.box<!fir.array<?x?xi32>>)
+  %1:2 = hlfir.declare %arg2 {uniq_name = "_QFminloc2Ed"} : (!fir.ref<index>) -> (!fir.ref<index>, !fir.ref<index>)
+  %2:2 = hlfir.declare %arg1 {uniq_name = "_QFminloc2Es"} : (!fir.box<!fir.array<?xi32>>) -> (!fir.box<!fir.array<?xi32>>, !fir.box<!fir.array<?xi32>>)
+  %3 = fir.load %1#0 : !fir.ref<index>
+  %4 = hlfir.minloc %0#0 dim %3#0 {fastmath = #arith.fastmath<contract>} : (!fir.box<!fir.array<?x?xi32>>, index) -> !hlfir.expr<?xi32>
+  hlfir.assign %4 to %2#0 : !hlfir.expr<?xi32>, !fir.box<!fir.array<?xi32>>
+  hlfir.destroy %4 : !hlfir.expr<?xi32>
+  return
+}
+// CHECK-LABEL: func.func @_QPminloc2(
+// CHECK:           %[[ARG0:.*]]: !fir.box<!fir.array<?x?xi32>> {fir.bindc_name = "a"}
+// CHECK:           %[[ARG1:.*]]: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "s"}
+// CHECK:           %[[ARG2:.*]]: !fir.ref<index>
+// CHECK-NEXT:    %[[V0:.*]] = fir.alloca !fir.box<!fir.heap<!fir.array<?xi32>>>
+// CHECK-NEXT:    %[[V1:.*]]:2 = hlfir.declare %[[ARG0]] {uniq_name = "_QFminloc2Ea"} : (!fir.box<!fir.array<?x?xi32>>) -> (!fir.box<!fir.array<?x?xi32>>, !fir.box<!fir.array<?x?xi32>>)
+// CHECK-NEXT:    %[[V2:.*]]:2 = hlfir.declare %[[ARG2]] {uniq_name = "_QFminloc2Ed"} : (!fir.ref<index>) -> (!fir.ref<index>, !fir.ref<index>)
+// CHECK-NEXT:    %[[V3:.*]]:2 = hlfir.declare %[[ARG1]] {uniq_name = "_QFminloc2Es"} : (!fir.box<!fir.array<?xi32>>) -> (!fir.box<!fir.array<?xi32>>, !fir.box<!fir.array<?xi32>>)
+// CHECK-NEXT:    %[[V4:.*]] = fir.load %[[V2]]#0 : !fir.ref<index>
+// CHECK-NEXT:    %c4_i32 = arith.constant 4 : i32
+// CHECK-NEXT:    %[[V5:.*]] = fir.convert %[[V4]] : (index) -> i32
+// CHECK-NEXT:    %[[V6:.*]] = fir.absent !fir.box<i1>
+// CHECK-NEXT:    %false = arith.constant false
+// CHECK-NEXT:    %[[V7:.*]] = fir.zero_bits !fir.heap<!fir.array<?xi32>>
+// CHECK-NEXT:    %c0 = arith.constant 0 : index
+// CHECK-NEXT:    %[[V8:.*]] = fir.shape %c0 : (index) -> !fir.shape<1>
+// CHECK-NEXT:    %[[V9:.*]] = fir.embox %[[V7]](%[[V8]]) : (!fir.heap<!fir.array<?xi32>>, !fir.shape<1>) -> !fir.box<!fir.heap<!fir.array<?xi32>>>
+// CHECK-NEXT:    fir.store %[[V9]] to %[[V0]] : !fir.ref<!fir.box<!fir.heap<!fir.array<?xi32>>>>
+// CHECK:         %[[V11:.*]] = fir.convert %[[V0]] : (!fir.ref<!fir.box<!fir.heap<!fir.array<?xi32>>>>) -> !fir.ref<!fir.box<none>>
+// CHECK-NEXT:    %[[V12:.*]] = fir.convert %[[V1]]#1 : (!fir.box<!fir.array<?x?xi32>>) -> !fir.box<none>
+// CHECK:         %[[V15:.*]] = fir.convert %[[V6]] : (!fir.box<i1>) -> !fir.box<none>
+// CHECK-NEXT:    %[[V16:.*]] = fir.call @_FortranAMinlocDim(%[[V11]], %[[V12]], %c4_i32, %[[V5]], {{.*}}, {{.*}}, %[[V15]], %false) fastmath<contract> : (!fir.ref<!fir.box<none>>, !fir.box<none>, i32, i32, !fir.ref<i8>, i32, !fir.box<none>, i1) -> none
+// CHECK-NEXT:    %[[V17:.*]] = fir.load %[[V0]] : !fir.ref<!fir.box<!fir.heap<!fir.array<?xi32>>>>
+// CHECK-NEXT:    %c0_0 = arith.constant 0 : index
+// CHECK-NEXT:    %[[V18:.*]]:3 = fir.box_dims %[[V17]], %c0_0 : (!fir.box<!fir.heap<!fir.array<?xi32>>>, index) -> (index, index, index)
+// CHECK-NEXT:    %[[V19:.*]] = fir.box_addr %[[V17]] : (!fir.box<!fir.heap<!fir.array<?xi32>>>) -> !fir.heap<!fir.array<?xi32>>
+// CHECK-NEXT:    %[[V20:.*]] = fir.shape_shift %[[V18]]#0, %[[V18]]#1 : (index, index) -> !fir.shapeshift<1>
+// CHECK-NEXT:    %[[V21:.*]]:2 = hlfir.declare %[[V19]](%[[V20]]) {uniq_name = ".tmp.intrinsic_result"} : (!fir.heap<!fir.array<?xi32>>, !fir.shapeshift<1>) -> (!fir.box<!fir.array<?xi32>>, !fir.heap<!fir.array<?xi32>>)
+// CHECK-NEXT:    %true = arith.constant true
+// CHECK-NEXT:    %[[V22:.*]] = hlfir.as_expr %[[V21]]#0 move %true : (!fir.box<!fir.array<?xi32>>, i1) -> !hlfir.expr<?xi32>
+// CHECK-NEXT:    hlfir.assign %[[V22]] to %[[V3]]#0 : !hlfir.expr<?xi32>, !fir.box<!fir.array<?xi32>>
+// CHECK-NEXT:    hlfir.destroy %[[V22]] : !hlfir.expr<?xi32>
+// CHECK-NEXT:    return
+
+
+// minloc with scalar mask
+func.func @_QPminloc3(%arg0: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "a"}, %arg1: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "s"}, %arg2: !fir.ref<!fir.logical<4>> {fir.bindc_name = "m"}) {
+  %0:2 = hlfir.declare %arg0 {uniq_name = "_QFminloc3Ea"} : (!fir.box<!fir.array<?xi32>>) -> (!fir.box<!fir.array<?xi32>>, !fir.box<!fir.array<?xi32>>)
+  %1:2 = hlfir.declare %arg2 {uniq_name = "_QFminloc3Em"} : (!fir.ref<!fir.logical<4>>) -> (!fir.ref<!fir.logical<4>>, !fir.ref<!fir.logical<4>>)
+  %2:2 = hlfir.declare %arg1 {uniq_name = "_QFminloc3Es"} : (!fir.box<!fir.array<?xi32>>) -> (!fir.box<!fir.array<?xi32>>, !fir.box<!fir.array<?xi32>>)
+  %3 = hlfir.minloc %0#0 mask %1#0 {fastmath = #arith.fastmath<contract>} : (!fir.box<!fir.array<?xi32>>, !fir.ref<!fir.logical<4>>) -> !hlfir.expr<?xi32>
+  hlfir.assign %3 to %2#0 : !hlfir.expr<?xi32>, !fir.box<!fir.array<?xi32>>
+  hlfir.destroy %3 : !hlfir.expr<?xi32>
+  return
+}
+// CHECK-LABEL: func.func @_QPminloc3(
+// CHECK:           %[[ARG0:.*]]: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "a"}
+// CHECK:           %[[ARG1:.*]]: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "s"}
+// CHECK:           %[[ARG2:.*]]: !fir.ref<!fir.logical<4>>
+// CHECK-NEXT:    %[[V0:.*]] = fir.alloca !fir.box<!fir.heap<!fir.array<?xi32>>>
+// CHECK-NEXT:    %[[V1:.*]]:2 = hlfir.declare %[[ARG0]] {uniq_name = "_QFminloc3Ea"} : (!fir.box<!fir.array<?xi32>>) -> (!fir.box<!fir.array<?xi32>>, !fir.box<!fir.array<?xi32>>)
+// CHECK-NEXT:    %[[V2:.*]]:2 = hlfir.declare %[[ARG2]] {uniq_name = "_QFminloc3Em"} : (!fir.ref<!fir.logical<4>>) -> (!fir.ref<!fir.logical<4>>, !fir.ref<!fir.logical<4>>)
+// CHECK-NEXT:    %[[V3:.*]]:2 = hlfir.declare %[[ARG1]] {uniq_name = "_QFminloc3Es"} : (!fir.box<!fir.array<?xi32>>) -> (!fir.box<!fir.array<?xi32>>, !fir.box<!fir.array<?xi32>>)
+// CHECK-NEXT:    %c4_i32 = arith.constant 4 : i32
+// CHECK-NEXT:    %[[V4:.*]] = fir.embox %[[V2]]#1 : (!fir.ref<!fir.logical<4>>) -> !fir.box<!fir.logical<4>>
+// CHECK-NEXT:    %false = arith.constant false
+// CHECK-NEXT:    %[[V5:.*]] = fir.zero_bits !fir.heap<!fir.array<?xi32>>
+// CHECK-NEXT:    %c0 = arith.constant 0 : index
+// CHECK-NEXT:    %[[V6:.*]] = fir.shape %c0 : (index) -> !fir.shape<1>
+// CHECK-NEXT:    %[[V7:.*]] = fir.embox %[[V5]](%[[V6]]) : (!fir.heap<!fir.array<?xi32>>, !fir.shape<1>) -> !fir.box<!fir.heap<!fir.array<?xi32>>>
+// CHECK-NEXT:    fir.store %[[V7]] to %[[V0]] : !fir.ref<!fir.box<!fir.heap<!fir.array<?xi32>>>>
+// CHECK:         %[[V9:.*]] = fir.convert %[[V0]] : (!fir.ref<!fir.box<!fir.heap<!fir.array<?xi32>>>>) -> !fir.ref<!fir.box<none>>
+// CHECK-NEXT:    %[[V10:.*]] = fir.convert %[[V1]]#1 : (!fir.box<!fir.array<?xi32>>) -> !fir.box<none>
+// CHECK:         %[[V13:.*]] = fir.convert %[[V4]] : (!fir.box<!fir.logical<4>>) -> !fir.box<none>
+// CHECK-NEXT:    %[[V14:.*]] = fir.call @_FortranAMinlocInteger4(%[[V9]], %[[V10]], %c4_i32, {{.*}}, {{.*}}, %[[V13]], %false) fastmath<contract> : (!fir.ref<!fir.box<none>>, !fir.box<none>, i32, !fir.ref<i8>, i32, !fir.box<none>, i1) -> none
+// CHECK-NEXT:    %[[V15:.*]] = fir.load %[[V0]] : !fir.ref<!fir.box<!fir.heap<!fir.array<?xi32>>>>
+// CHECK-NEXT:    %c0_0 = arith.constant 0 : index
+// CHECK-NEXT:    %[[V16:.*]]:3 = fir.box_dims %[[V15]], %c0_0 : (!fir.box<!fir.heap<!fir.array<?xi32>>>, index) -> (index, index, index)
+// CHECK-NEXT:    %[[V17:.*]] = fir.box_addr %[[V15]] : (!fir.box<!fir.heap<!fir.array<?xi32>>>) -> !fir.heap<!fir.array<?xi32>>
+// CHECK-NEXT:    %[[V18:.*]] = fir.shape_shift %[[V16]]#0, %[[V16]]#1 : (index, index) -> !fir.shapeshift<1>
+// CHECK-NEXT:    %[[V19:.*]]:2 = hlfir.declare %[[V17]](%[[V18]]) {uniq_name = ".tmp.intrinsic_result"} : (!fir.heap<!fir.array<?xi32>>, !fir.shapeshift<1>) -> (!fir.box<!fir.array<?xi32>>, !fir.heap<!fir.array<?xi32>>)
+// CHECK-NEXT:    %true = arith.constant true
+// CHECK-NEXT:    %[[V20:.*]] = hlfir.as_expr %[[V19]]#0 move %true : (!fir.box<!fir.array<?xi32>>, i1) -> !hlfir.expr<?xi32>
+// CHECK-NEXT:    hlfir.assign %[[V20]] to %[[V3]]#0 : !hlfir.expr<?xi32>, !fir.box<!fir.array<?xi32>>
+// CHECK-NEXT:    hlfir.destroy %[[V20]] : !hlfir.expr<?xi32>
+// CHECK-NEXT:    return
+
+
+// minloc with array mask
+func.func @_QPminloc4(%arg0: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "a"}, %arg1: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "s"}, %arg2: !fir.box<!fir.array<?x!fir.logical<4>>> {fir.bindc_name = "m"}) {
+  %0:2 = hlfir.declare %arg0 {uniq_name = "_QFminloc4Ea"} : (!fir.box<!fir.array<?xi32>>) -> (!fir.box<!fir.array<?xi32>>, !fir.box<!fir.array<?xi32>>)
+  %1:2 = hlfir.declare %arg2 {uniq_name = "_QFminloc4Em"} : (!fir.box<!fir.array<?x!fir.logical<4>>>) -> (!fir.box<!fir.array<?x!fir.logical<4>>>, !fir.box<!fir.array<?x!fir.logical<4>>>)
+  %2:2 = hlfir.declare %arg1 {uniq_name = "_QFminloc4Es"} : (!fir.box<!fir.array<?xi32>>) -> (!fir.box<!fir.array<?xi32>>, !fir.box<!fir.array<?xi32>>)
+  %3 = hlfir.minloc %0#0 mask %1#0 {fastmath = #arith.fastmath<contract>} : (!fir.box<!fir.array<?xi32>>, !fir.box<!fir.array<?x!fir.logical<4>>>) -> !hlfir.expr<?xi32>
+  hlfir.assign %3 to %2#0 : !hlfir.expr<?xi32>, !fir.box<!fir.array<?xi32>>
+  hlfir.destroy %3 : !hlfir.expr<?xi32>
+  return
+}
+// CHECK-LABEL: func.func @_QPminloc4(
+// CHECK:           %[[ARG0:.*]]: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "a"}
+// CHECK:           %[[ARG1:.*]]: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "s"}
+// CHECK:           %[[ARG2:.*]]: !fir.box<!fir.array<?x!fir.logical<4>>>
+// CHECK-NEXT:    %[[V0:.*]] = fir.alloca !fir.box<!fir.heap<!fir.array<?xi32>>>
+// CHECK-NEXT:    %[[V1:.*]]:2 = hlfir.declare %[[ARG0]] {uniq_name = "_QFminloc4Ea"} : (!fir.box<!fir.array<?xi32>>) -> (!fir.box<!fir.array<?xi32>>, !fir.box<!fir.array<?xi32>>)
+// CHECK-NEXT:    %[[V2:.*]]:2 = hlfir.declare %[[ARG2]] {uniq_name = "_QFminloc4Em"} : (!fir.box<!fir.array<?x!fir.logical<4>>>) -> (!fir.box<!fir.array<?x!fir.logical<4>>>, !fir.box<!fir.array<?x!fir.logical<4>>>)
+// CHECK-NEXT:    %[[V3:.*]]:2 = hlfir.declare %[[ARG1]] {uniq_name = "_QFminloc4Es"} : (!fir.box<!fir.array<?xi32>>) -> (!fir.box<!fir.array<?xi32>>, !fir.box<!fir.array<?xi32>>)
+// CHECK-NEXT:    %c4_i32 = arith.constant 4 : i32
+// CHECK-NEXT:    %false = arith.constant false
+// CHECK-NEXT:    %[[V4:.*]] = fir.zero_bits !fir.heap<!fir.array<?xi32>>
+// CHECK-NEXT:    %c0 = arith.constant 0 : index
+// CHECK-NEXT:    %[[V5:.*]] = fir.shape %c0 : (index) -> !fir.shape<1>
+// CHECK-NEXT:    %[[V6:.*]] = fir.embox %[[V4]](%[[V5]]) : (!fir.heap<!fir.array<?xi32>>, !fir.shape<1>) -> !fir.box<!fir.heap<!fir.array<?xi32>>>
+// CHECK-NEXT:    fir.store %[[V6]] to %[[V0]] : !fir.ref<!fir.box<!fir.heap<!fir.array<?xi32>>>>
+// CHECK:         %[[V8:.*]] = fir.convert %[[V0]] : (!fir.ref<!fir.box<!fir.heap<!fir.array<?xi32>>>>) -> !fir.ref<!fir.box<none>>
+// CHECK-NEXT:    %[[V9:.*]] = fir.convert %[[V1]]#1 : (!fir.box<!fir.array<?xi32>>) -> !fir.box<none>
+// CHECK:         %[[V12:.*]] = fir.convert %[[V2]]#1 : (!fir.box<!fir.array<?x!fir.logical<4>>>) -> !fir.box<none>
+// CHECK-NEXT:    %[[V13:.*]] = fir.call @_FortranAMinlocInteger4(%[[V8]], %[[V9]], %c4_i32, {{.*}}, {{.*}}, %[[V12]], %false) fastmath<contract> : (!fir.ref<!fir.box<none>>, !fir.box<none>, i32, !fir.ref<i8>, i32, !fir.box<none>, i1) -> none
+// CHECK-NEXT:    %[[V14:.*]] = fir.load %[[V0]] : !fir.ref<!fir.box<!fir.heap<!fir.array<?xi32>>>>
+// CHECK-NEXT:    %c0_0 = arith.constant 0 : index
+// CHECK-NEXT:    %[[V15:.*]]:3 = fir.box_dims %[[V14]], %c0_0 : (!fir.box<!fir.heap<!fir.array<?xi32>>>, index) -> (index, index, index)
+// CHECK-NEXT:    %[[V16:.*]] = fir.box_addr %[[V14]] : (!fir.box<!fir.heap<!fir.array<?xi32>>>) -> !fir.heap<!fir.array<?xi32>>
+// CHECK-NEXT:    %[[V17:.*]] = fir.shape_shift %[[V15]]#0, %[[V15]]#1 : (index, index) -> !fir.shapeshift<1>
+// CHECK-NEXT:    %[[V18:.*]]:2 = hlfir.declare %[[V16]](%[[V17]]) {uniq_name = ".tmp.intrinsic_result"} : (!fir.heap<!fir.array<?xi32>>, !fir.shapeshift<1>) -> (!fir.box<!fir.array<?xi32>>, !fir.heap<!fir.array<?xi32>>)
+// CHECK-NEXT:    %true = arith.constant true
+// CHECK-NEXT:    %[[V19:.*]] = hlfir.as_expr %[[V18]]#0 move %true : (!fir.box<!fir.array<?xi32>>, i1) -> !hlfir.expr<?xi32>
+// CHECK-NEXT:    hlfir.assign %[[V19]] to %[[V3]]#0 : !hlfir.expr<?xi32>, !fir.box<!fir.array<?xi32>>
+// CHECK-NEXT:    hlfir.destroy %[[V19]] : !hlfir.expr<?xi32>
+// CHECK-NEXT:    return
+
+
+fir.global internal @_QFminloc5Ea : !fir.array<2x2xi32> {
+  %0 = fir.undefined !fir.array<2x2xi32>
+  %c1_i32 = arith.constant 1 : i32
+  %1 = fir.insert_value %0, %c1_i32, [0 : index, 0 : index] : (!fir.array<2x2xi32>, i32) -> !fir.array<2x2xi32>
+  %c2_i32 = arith.constant 2 : i32
+  %2 = fir.insert_value %1, %c2_i32, [1 : index, 0 : index] : (!fir.array<2x2xi32>, i32) -> !fir.array<2x2xi32>
+  %c3_i32 = arith.constant 3 : i32
+  %3 = fir.insert_value %2, %c3_i32, [0 : index, 1 : index] : (!fir.array<2x2xi32>, i32) -> !fir.array<2x2xi32>
+  %c4_i32 = arith.constant 4 : i32
+  %4 = fir.insert_value %3, %c4_i32, [1 : index, 1 : index] : (!fir.array<2x2xi32>, i32) -> !fir.array<2x2xi32>
+  %c2 = arith.constant 2 : index
+  %c2_0 = arith.constant 2 : index
+  fir.has_value %4 : !fir.array<2x2xi32>
+}
+
+// 3 argument minloc, using local variables
+func.func @_QPminloc5(%arg0: !fir.ref<!fir.array<2xi32>> {fir.bindc_name = "s"}) {
+  %0 = fir.address_of(@_QFminloc5Ea) : !fir.ref<!fir.array<2x2xi32>>
+  %c2 = arith.constant 2 : index
+  %c2_0 = arith.constant 2 : index
+  %1 = fir.shape %c2, %c2_0 : (index, index) -> !fir.shape<2>
+  %2:2 = hlfir.declare %0(%1) {uniq_name = "_QFminloc5Ea"} : (!fir.ref<!fir.array<2x2xi32>>, !fir.shape<2>) -> (!fir.ref<!fir.array<2x2xi32>>, !fir.ref<!fir.array<2x2xi32>>)
+  %c2_1 = arith.constant 2 : index
+  %3 = fir.shape %c2_1 : (index) -> !fir.shape<1>
+  %4:2 = hlfir.declare %arg0(%3) {uniq_name = "_QFminloc5Es"} : (!fir.ref<!fir.array<2xi32>>, !fir.shape<1>) -> (!fir.ref<!fir.array<2xi32>>, !fir.ref<!fir.array<2xi32>>)
+  %c1_i32 = arith.constant 1 : i32
+  %true = arith.constant true
+  %5 = hlfir.minloc %2#0 dim %c1_i32 mask %true {fastmath = #arith.fastmath<contract>} : (!fir.ref<!fir.array<2x2xi32>>, i32, i1) -> !hlfir.expr<2xi32>
+  hlfir.assign %5 to %4#0 : !hlfir.expr<2xi32>, !fir.ref<!fir.array<2xi32>>
+  hlfir.destroy %5 : !hlfir.expr<2xi32>
+  return
+}
+// CHECK-LABEL: func.func @_QPminloc5(
+// CHECK:           %[[ARG0:.*]]: !fir.ref<!fir.array<2xi32>> {fir.bindc_name = "s"}
+// CHECK-NEXT:    %[[V0:.*]] = fir.alloca !fir.box<!fir.heap<!fir.array<?xi32>>>
+// CHECK-NEXT:    %[[V1:.*]] = fir.alloca !fir.logical<4>
+// CHECK-NEXT:    %[[V2:.*]] = fir.address_of(@_QFminloc5Ea) : !fir.ref<!fir.array<2x2xi32>>
+// CHECK-NEXT:    %c2 = arith.constant 2 : index
+// CHECK-NEXT:    %c2_0 = arith.constant 2 : index
+// CHECK-NEXT:    %[[V3:.*]] = fir.shape %c2, %c2_0 : (index, index) -> !fir.shape<2>
+// CHECK-NEXT:    %[[V4:.*]]:2 = hlfir.declare %[[V2]](%[[V3]]) {uniq_name = "_QFminloc5Ea"} : (!fir.ref<!fir.array<2x2xi32>>, !fir.shape<2>) -> (!fir.ref<!fir.array<2x2xi32>>, !fir.ref<!fir.array<2x2xi32>>)
+// CHECK-NEXT:    %c2_1 = arith.constant 2 : index
+// CHECK-NEXT:    %[[V5:.*]] = fir.shape %c2_1 : (index) -> !fir.shape<1>
+// CHECK-NEXT:    %[[V6:.*]]:2 = hlfir.declare %[[ARG0]](%[[V5]]) {uniq_name = "_QFminloc5Es"} : (!fir.ref<!fir.array<2xi32>>, !fir.shape<1>) -> (!fir.ref<!fir.array<2xi32>>, !fir.ref<!fir.array<2xi32>>)
+// CHECK-NEXT:    %c1_i32 = arith.constant 1 : i32
+// CHECK-NEXT:    %true = arith.constant true
+// CHECK-NEXT:    %c4_i32 = arith.constant 4 : i32
+// CHECK-NEXT:    %[[V7:.*]] = fir.shape %c2, %c2_0 : (index, index) -> !fir.shape<2>
+// CHECK-NEXT:    %[[V8:.*]] = fir.embox %[[V4]]#1(%[[V7]]) : (!fir.ref<!fir.array<2x2xi32>>, !fir.shape<2>) -> !fir.box<!fir.array<2x2xi32>>
+// CHECK-NEXT:    %[[V9:.*]] = fir.convert %true : (i1) -> !fir.logical<4>
+// CHECK-NEXT:    fir.store %[[V9]] to %[[V1]] : !fir.ref<!fir.logical<4>>
+// CHECK-NEXT:    %[[V10:.*]] = fir.embox %[[V1]] : (!fir.ref<!fir.logical<4>>) -> !fir.box<!fir.logical<4>>
+// CHECK-NEXT:    %false = arith.constant false
+// CHECK-NEXT:    %[[V11:.*]] = fir.zero_bits !fir.heap<!fir.array<?xi32>>
+// CHECK-NEXT:    %c0 = arith.constant 0 : index
+// CHECK-NEXT:    %[[V12:.*]] = fir.shape %c0 : (index) -> !fir.shape<1>
+// CHECK-NEXT:    %[[V13:.*]] = fir.embox %[[V11]](%[[V12]]) : (!fir.heap<!fir.array<?xi32>>, !fir.shape<1>) -> !fir.box<!fir.heap<!fir.array<?xi32>>>
+// CHECK-NEXT:    fir.store %[[V13]] to %[[V0]] : !fir.ref<!fir.box<!fir.heap<!fir.array<?xi32>>>>
+// CHECK:         %[[V15:.*]] = fir.convert %[[V0]] : (!fir.ref<!fir.box<!fir.heap<!fir.array<?xi32>>>>) -> !fir.ref<!fir.box<none>>
+// CHECK-NEXT:    %[[V16:.*]] = fir.convert %[[V8]] : (!fir.box<!fir.array<2x2xi32>>) -> !fir.box<none>
+// CHECK:         %[[V19:.*]] = fir.convert %[[V10]] : (!fir.box<!fir.logical<4>>) -> !fir.box<none>
+// CHECK-NEXT:    %[[V20:.*]] = fir.call @_FortranAMinlocDim(%[[V15]], %[[V16]], %c4_i32, %c1_i32, {{.*}}, {{.*}}, %[[V19]], %false) fastmath<contract> : (!fir.ref<!fir.box<none>>, !fir.box<none>, i32, i32, !fir.ref<i8>, i32, !fir.box<none>, i1) -> none
+// CHECK-NEXT:    %[[V21:.*]] = fir.load %[[V0]] : !fir.ref<!fir.box<!fir.heap<!fir.array<?xi32>>>>
+// CHECK-NEXT:    %c0_2 = arith.constant 0 : index
+// CHECK-NEXT:    %[[V22:.*]]:3 = fir.box_dims %[[V21]], %c0_2 : (!fir.box<!fir.heap<!fir.array<?xi32>>>, index) -> (index, index, index)
+// CHECK-NEXT:    %[[V23:.*]] = fir.box_addr %[[V21]] : (!fir.box<!fir.heap<!fir.array<?xi32>>>) -> !fir.heap<!fir.array<?xi32>>
+// CHECK-NEXT:    %[[V24:.*]] = fir.shape_shift %[[V22]]#0, %[[V22]]#1 : (index, index) -> !fir.shapeshift<1>
+// CHECK-NEXT:    %[[V25:.*]]:2 = hlfir.declare %[[V23]](%[[V24]]) {uniq_name = ".tmp.intrinsic_result"} : (!fir.heap<!fir.array<?xi32>>, !fir.shapeshift<1>) -> (!fir.box<!fir.array<?xi32>>, !fir.heap<!fir.array<?xi32>>)
+// CHECK-NEXT:    %true_3 = arith.constant true
+// CHECK-NEXT:    %[[V26:.*]] = hlfir.as_expr %[[V25]]#0 move %true_3 : (!fir.box<!fir.array<?xi32>>, i1) -> !hlfir.expr<?xi32>
+// CHECK-NEXT:    hlfir.assign %[[V26]] to %[[V6]]#0 : !hlfir.expr<?xi32>, !fir.ref<!fir.array<2xi32>>
+// CHECK-NEXT:    hlfir.destroy %[[V26]] : !hlfir.expr<?xi32>
+// CHECK-NEXT:    return
+
+
+// simple one argument minloc for character
+func.func @_QPminloc6(%arg0: !fir.box<!fir.array<?x!fir.char<1,?>>> {fir.bindc_name = "a"}, %arg1: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "s"}) {
+  %0:2 = hlfir.declare %arg0 {uniq_name = "_QFminloc6Ea"} : (!fir.box<!fir.array<?x!fir.char<1,?>>>) -> (!fir.box<!fir.array<?x!fir.char<1,?>>>, !fir.box<!fir.array<?x!fir.char<1,?>>>)
+  %1:2 = hlfir.declare %arg1 {uniq_name = "_QFminloc4Es"} : (!fir.box<!fir.array<?xi32>>) -> (!fir.box<!fir.array<?xi32>>, !fir.box<!fir.array<?xi32>>)
+  %2 = hlfir.minloc %0#0 {fastmath = #arith.fastmath<contract>} : (!fir.box<!fir.array<?x!fir.char<1,?>>>) -> !hlfir.expr<?xi32>
+  hlfir.assign %2 to %1#0 : !hlfir.expr<?xi32>, !fir.box<!fir.array<?xi32>>
+  hlfir.destroy %2 : !hlfir.expr<?xi32>
+  return
+}
+// CHECK-LABEL: func.func @_QPminloc6(
+// CHECK:           %[[ARG0:.*]]: !fir.box<!fir.array<?x!fir.char<1,?>>> {fir.bindc_name = "a"}
+// CHECK:           %[[ARG1:.*]]: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "s"}
+// CHECK-NEXT:    %[[V0:.*]] = fir.alloca !fir.box<!fir.heap<!fir.array<?xi32>>>
+// CHECK-NEXT:    %[[V1:.*]]:2 = hlfir.declare %[[ARG0]] {uniq_name = "_QFminloc6Ea"} : (!fir.box<!fir.array<?x!fir.char<1,?>>>) -> (!fir.box<!fir.array<?x!fir.char<1,?>>>, !fir.box<!fir.array<?x!fir.char<1,?>>>)
+// CHECK-NEXT:    %[[V2:.*]]:2 = hlfir.declare %[[ARG1]] {uniq_name = "_QFminloc4Es"} : (!fir.box<!fir.array<?xi32>>) -> (!fir.box<!fir.array<?xi32>>, !fir.box<!fir.array<?xi32>>)
+// CHECK-NEXT:    %c4_i32 = arith.constant 4 : i32
+// CHECK-NEXT:    %[[V3:.*]] = fir.absent !fir.box<i1>
+// CHECK-NEXT:    %false = arith.constant false
+// CHECK-NEXT:    %[[V4:.*]] = fir.zero_bits !fir.heap<!fir.array<?xi32>>
+// CHECK-NEXT:    %c0 = arith.constant 0 : index
+// CHECK-NEXT:    %[[V5:.*]] = fir.shape %c0 : (index) -> !fir.shape<1>
+// CHECK-NEXT:    %[[V6:.*]] = fir.embox %[[V4]](%[[V5]]) : (!fir.heap<!fir.array<?xi32>>, !fir.shape<1>) -> !fir.box<!fir.heap<!fir.array<?xi32>>>
+// CHECK-NEXT:    fir.store %[[V6]] to %[[V0]] : !fir.ref<!fir.box<!fir.heap<!fir.array<?xi32>>>>
+// CHECK:         %[[V8:.*]] = fir.convert %[[V0]] : (!fir.ref<!fir.box<!fir.heap<!fir.array<?xi32>>>>) -> !fir.ref<!fir.box<none>>
+// CHECK-NEXT:    %[[V9:.*]] = fir.convert %[[V1]]#1 : (!fir.box<!fir.array<?x!fir.char<1,?>>>) -> !fir.box<none>
+// CHECK:         %[[V12:.*]] = fir.convert %[[V3]] : (!fir.box<i1>) -> !fir.box<none>
+// CHECK-NEXT:    %[[V13:.*]] = fir.call @_FortranAMinlocCharacter(%[[V8]], %[[V9]], %c4_i32, {{.*}}, {{.*}}, %[[V12]], %false) fastmath<contract> : (!fir.ref<!fir.box<none>>, !fir.box<none>, i32, !fir.ref<i8>, i32, !fir.box<none>, i1) -> none
+// CHECK-NEXT:    %[[V14:.*]] = fir.load %[[V0]] : !fir.ref<!fir.box<!fir.heap<!fir.array<?xi32>>>>
+// CHECK-NEXT:    %c0_0 = arith.constant 0 : index
+// CHECK-NEXT:    %[[V15:.*]]:3 = fir.box_dims %[[V14]], %c0_0 : (!fir.box<!fir.heap<!fir.array<?xi32>>>, index) -> (index, index, index)
+// CHECK-NEXT:    %[[V16:.*]] = fir.box_addr %[[V14]] : (!fir.box<!fir.heap<!fir.array<?xi32>>>) -> !fir.heap<!fir.array<?xi32>>
+// CHECK-NEXT:    %[[V17:.*]] = fir.shape_shift %[[V15]]#0, %[[V15]]#1 : (index, index) -> !fir.shapeshift<1>
+// CHECK-NEXT:    %[[V18:.*]]:2 = hlfir.declare %[[V16]](%[[V17]]) {uniq_name = ".tmp.intrinsic_result"} : (!fir.heap<!fir.array<?xi32>>, !fir.shapeshift<1>) -> (!fir.box<!fir.array<?xi32>>, !fir.heap<!fir.array<?xi32>>)
+// CHECK-NEXT:    %true = arith.constant true
+// CHECK-NEXT:    %[[V19:.*]] = hlfir.as_expr %[[V18]]#0 move %true : (!fir.box<!fir.array<?xi32>>, i1) -> !hlfir.expr<?xi32>
+// CHECK-NEXT:    hlfir.assign %[[V19]] to %[[V2]]#0 : !hlfir.expr<?xi32>, !fir.box<!fir.array<?xi32>>
+// CHECK-NEXT:    hlfir.destroy %[[V19]] : !hlfir.expr<?xi32>
+// CHECK-NEXT:    return
+
+
+// including mask and back
+func.func @_QPminloc7(%arg0: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "a"}, %arg1: !fir.ref<i32> {fir.bindc_name = "d"}, %arg2: !fir.box<!fir.array<?x!fir.logical<4>>> {fir.bindc_name = "m"}, %arg3: !fir.ref<!fir.logical<4>> {fir.bindc_name = "b"}, %arg4: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "s"}) {
+    %0:2 = hlfir.declare %arg0 {uniq_name = "_QFFtestEa"} : (!fir.box<!fir.array<?xi32>>) -> (!fir.box<!fir.array<?xi32>>, !fir.box<!fir.array<?xi32>>)
+    %1:2 = hlfir.declare %arg3 {uniq_name = "_QFFtestEb"} : (!fir.ref<!fir.logical<4>>) -> (!fir.ref<!fir.logical<4>>, !fir.ref<!fir.logical<4>>)
+    %2:2 = hlfir.declare %arg1 {uniq_name = "_QFFtestEd"} : (!fir.ref<i32>) -> (!fir.ref<i32>, !fir.ref<i32>)
+    %3:2 = hlfir.declare %arg2 {uniq_name = "_QFFtestEm"} : (!fir.box<!fir.array<?x!fir.logical<4>>>) -> (!fir.box<!fir.array<?x!fir.logical<4>>>, !fir.box<!fir.array<?x!fir.logical<4>>>)
+    %4:2 = hlfir.declare %arg4 {uniq_name = "_QFFtestEs"} : (!fir.box<!fir.array<?xi32>>) -> (!fir.box<!fir.array<?xi32>>, !fir.box<!fir.array<?xi32>>)
+    %5 = fir.load %2#0 : !fir.ref<i32>
+    %6 = hlfir.minloc %0#0 dim %5 mask %3#0 {fastmath = #arith.fastmath<contract>} : (!fir.box<!fir.array<?xi32>>, i32, !fir.box<!fir.array<?x!fir.logical<4>>>) -> i32
+    hlfir.assign %6 to %4#0 : i32, !fir.box<!fir.array<?xi32>>
+    return
+}
+// CHECK-LABEL: func.func @_QPminloc7(
+// CHECK:           %[[ARG0:.*]]: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "a"}
+// CHECK:           %[[ARG1:.*]]: !fir.ref<i32> {fir.bindc_name = "d"}
+// CHECK:           %[[ARG2:.*]]: !fir.box<!fir.array<?x!fir.logical<4>>> {fir.bindc_name = "m"}
+// CHECK:           %[[ARG3:.*]]: !fir.ref<!fir.logical<4>> {fir.bindc_name = "b"}
+// CHECK:           %[[ARG4:.*]]: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "s"}
+// CHECK-NEXT:    %[[V0:.*]] = fir.alloca !fir.box<!fir.heap<i32>>
+// CHECK-NEXT:    %[[V1:.*]]:2 = hlfir.declare %[[ARG0]] {uniq_name = "_QFFtestEa"} : (!fir.box<!fir.array<?xi32>>) -> (!fir.box<!fir.array<?xi32>>, !fir.box<!fir.array<?xi32>>)
+// CHECK-NEXT:    %[[V2:.*]]:2 = hlfir.declare %[[ARG3]] {uniq_name = "_QFFtestEb"} : (!fir.ref<!fir.logical<4>>) -> (!fir.ref<!fir.logical<4>>, !fir.ref<!fir.logical<4>>)
+// CHECK-NEXT:    %[[V3:.*]]:2 = hlfir.declare %[[ARG1]] {uniq_name = "_QFFtestEd"} : (!fir.ref<i32>) -> (!fir.ref<i32>, !fir.ref<i32>)
+// CHECK-NEXT:    %[[V4:.*]]:2 = hlfir.declare %[[ARG2]] {uniq_name = "_QFFtestEm"} : (!fir.box<!fir.array<?x!fir.logical<4>>>) -> (!fir.box<!fir.array<?x!fir.logical<4>>>, !fir.box<!fir.array<?x!fir.logical<4>>>)
+// CHECK-NEXT:    %[[V5:.*]]:2 = hlfir.declare %[[ARG4]] {uniq_name = "_QFFtestEs"} : (!fir.box<!fir.array<?xi32>>) -> (!fir.box<!fir.array<?xi32>>, !fir.box<!fir.array<?xi32>>)
+// CHECK-NEXT:    %[[V6:.*]] = fir.load %[[V3]]#0 : !fir.ref<i32>
+// CHECK-NEXT:    %c4_i32 = arith.constant 4 : i32
+// CHECK-NEXT:    %false = arith.constant false
+// CHECK-NEXT:    %[[V7:.*]] = fir.zero_bits !fir.heap<i32>
+// CHECK-NEXT:    %[[V8:.*]] = fir.embox %[[V7]] : (!fir.heap<i32>) -> !fir.box<!fir.heap<i32>>
+// CHECK-NEXT:    fir.store %[[V8]] to %[[V0]] : !fir.ref<!fir.box<!fir.heap<i32>>>
+// CHECK:         %[[V10:.*]] = fir.convert %[[V0]] : (!fir.ref<!fir.box<!fir.heap<i32>>>) -> !fir.ref<!fir.box<none>>
+// CHECK-NEXT:    %[[V11:.*]] = fir.convert %[[V1]]#1 : (!fir.box<!fir.array<?xi32>>) -> !fir.box<none>
+// CHECK:         %[[V14:.*]] = fir.convert %[[V4]]#1 : (!fir.box<!fir.array<?x!fir.logical<4>>>) -> !fir.box<none>
+// CHECK-NEXT:    %[[V15:.*]] = fir.call @_FortranAMinlocDim(%[[V10]], %[[V11]], %c4_i32, %[[V6]], {{.*}}, {{.*}}, %[[V14]], %false) fastmath<contract> : (!fir.ref<!fir.box<none>>, !fir.box<none>, i32, i32, !fir.ref<i8>, i32, !fir.box<none>, i1) -> none
+// CHECK-NEXT:    %[[V16:.*]] = fir.load %[[V0]] : !fir.ref<!fir.box<!fir.heap<i32>>>
+// CHECK-NEXT:    %[[V17:.*]] = fir.box_addr %[[V16]] : (!fir.box<!fir.heap<i32>>) -> !fir.heap<i32>
+// CHECK-NEXT:    %[[V18:.*]] = fir.load %[[V17]] : !fir.heap<i32>
+// CHECK-NEXT:    fir.freemem %[[V17]] : !fir.heap<i32>
+// CHECK-NEXT:    hlfir.assign %[[V18]] to %[[V5]]#0 : i32, !fir.box<!fir.array<?xi32>>
+// CHECK-NEXT:    return
+
diff --git a/flang/test/HLFIR/minloc.fir b/flang/test/HLFIR/minloc.fir
new file mode 100644
index 000000000000..9afb45f5bc19
--- /dev/null
+++ b/flang/test/HLFIR/minloc.fir
@@ -0,0 +1,272 @@
+// Test hlfir.minloc operation parse, verify (no errors), and unparse
+
+// RUN: fir-opt %s | fir-opt | FileCheck %s
+
+// array is an expression of known shape
+func.func @minloc0(%arg0: !hlfir.expr<42xi32>) {
+  %mask = fir.alloca !fir.logical<4>
+  %c_1 = arith.constant 1 : index
+  %true = arith.constant true
+  %true_logical = fir.convert %true : (i1) -> !fir.logical<4>
+  fir.store %true_logical to %mask : !fir.ref<!fir.logical<4>>
+  %mask_box = fir.embox %mask : (!fir.ref<!fir.logical<4>>) -> !fir.box<!fir.logical<4>>
+  %0 = hlfir.minloc %arg0 dim %c_1 mask %mask_box : (!hlfir.expr<42xi32>, index, !fir.box<!fir.logical<4>>) -> i32
+  return
+}
+// CHECK:      func.func @minloc0(%[[ARRAY:.*]]: !hlfir.expr<42xi32>) {
+// CHECK-NEXT:   %[[MASK:.*]] = fir.alloca !fir.logical<4>
+// CHECK-NEXT:   %[[C1:.*]] = arith.constant 1 : index
+// CHECK-NEXT:   %[[TRUE:.*]] = arith.constant true
+// CHECK-NEXT:   %[[LOGICAL:.*]] = fir.convert %[[TRUE]] : (i1) -> !fir.logical<4>
+// CHECK-NEXT:   fir.store %[[LOGICAL]] to %[[MASK]] : !fir.ref<!fir.logical<4>>
+// CHECK-NEXT:   %[[BOX:.*]] = fir.embox %0 : (!fir.ref<!fir.logical<4>>) -> !fir.box<!fir.logical<4>>
+// CHECK-NEXT:   hlfir.minloc %[[ARRAY]] dim %[[C1]] mask %[[BOX]] : (!hlfir.expr<42xi32>, index, !fir.box<!fir.logical<4>>) -> i32
+// CHECK-NEXT:   return
+// CHECK-NEXT: }
+
+// array is an expression of assumed shape
+func.func @minloc1(%arg0: !hlfir.expr<?xi32>) {
+  %mask = fir.alloca !fir.logical<4>
+  %c_1 = arith.constant 1 : index
+  %true = arith.constant true
+  %true_logical = fir.convert %true : (i1) -> !fir.logical<4>
+  fir.store %true_logical to %mask : !fir.ref<!fir.logical<4>>
+  %mask_box = fir.embox %mask : (!fir.ref<!fir.logical<4>>) -> !fir.box<!fir.logical<4>>
+  %0 = hlfir.minloc %arg0 dim %c_1 mask %mask_box : (!hlfir.expr<?xi32>, index, !fir.box<!fir.logical<4>>) -> i32
+  return
+}
+// CHECK:      func.func @minloc1(%[[ARRAY:.*]]: !hlfir.expr<?xi32>) {
+// CHECK-NEXT:   %[[MASK:.*]] = fir.alloca !fir.logical<4>
+// CHECK-NEXT:   %[[C1:.*]] = arith.constant 1 : index
+// CHECK-NEXT:   %[[TRUE:.*]] = arith.constant true
+// CHECK-NEXT:   %[[LOGICAL:.*]] = fir.convert %[[TRUE]] : (i1) -> !fir.logical<4>
+// CHECK-NEXT:   fir.store %[[LOGICAL:.*]] to %[[MASK:.*]] : !fir.ref<!fir.logical<4>>
+// CHECK-NEXT:   %[[BOX:.*]] = fir.embox %[[MASK:.*]] : (!fir.ref<!fir.logical<4>>) -> !fir.box<!fir.logical<4>>
+// CHECK-NEXT:   hlfir.minloc %[[ARRAY:.*]] dim %[[C1]] mask %[[BOX]] : (!hlfir.expr<?xi32>, index, !fir.box<!fir.logical<4>>) -> i32
+// CHECK-NEXT:   return
+// CHECK-NEXT: }
+
+// boxed array
+func.func @minloc2(%arg0: !fir.box<!fir.array<42xi32>>) {
+  %mask = fir.alloca !fir.logical<4>
+  %c_1 = arith.constant 1 : index
+  %true = arith.constant true
+  %true_logical = fir.convert %true : (i1) -> !fir.logical<4>
+  fir.store %true_logical to %mask : !fir.ref<!fir.logical<4>>
+  %mask_box = fir.embox %mask : (!fir.ref<!fir.logical<4>>) -> !fir.box<!fir.logical<4>>
+  %0 = hlfir.minloc %arg0 dim %c_1 mask %mask_box : (!fir.box<!fir.array<42xi32>>, index, !fir.box<!fir.logical<4>>) -> i32
+  return
+}
+// CHECK:      func.func @minloc2(%[[ARRAY:.*]]: !fir.box<!fir.array<42xi32>>) {
+// CHECK-NEXT:   %[[MASK:.*]] = fir.alloca !fir.logical<4>
+// CHECK-NEXT:   %[[C1:.*]] = arith.constant 1 : index
+// CHECK-NEXT:   %[[TRUE:.*]] = arith.constant true
+// CHECK-NEXT:   %[[LOGICAL:.*]] = fir.convert %[[TRUE]] : (i1) -> !fir.logical<4>
+// CHECK-NEXT:   fir.store %[[LOGICAL:.*]] to %[[MASK:.*]] : !fir.ref<!fir.logical<4>>
+// CHECK-NEXT:   %[[BOX:.*]] = fir.embox %[[MASK:.*]] : (!fir.ref<!fir.logical<4>>) -> !fir.box<!fir.logical<4>>
+// CHECK-NEXT:   hlfir.minloc %[[ARRAY:.*]] dim %[[C1]] mask %[[BOX]] : (!fir.box<!fir.array<42xi32>>, index, !fir.box<!fir.logical<4>>) -> i32
+// CHECK-NEXT:   return
+// CHECK-NEXT: }
+
+// assumed shape boxed array
+func.func @minloc3(%arg0: !fir.box<!fir.array<?xi32>>) {
+  %mask = fir.alloca !fir.logical<4>
+  %c_1 = arith.constant 1 : index
+  %true = arith.constant true
+  %true_logical = fir.convert %true : (i1) -> !fir.logical<4>
+  fir.store %true_logical to %mask : !fir.ref<!fir.logical<4>>
+  %mask_box = fir.embox %mask : (!fir.ref<!fir.logical<4>>) -> !fir.box<!fir.logical<4>>
+  %0 = hlfir.minloc %arg0 dim %c_1 mask %mask_box : (!fir.box<!fir.array<?xi32>>, index, !fir.box<!fir.logical<4>>) -> i32
+  return
+}
+// CHECK:      func.func @minloc3(%[[ARRAY:.*]]: !fir.box<!fir.array<?xi32>>) {
+// CHECK-NEXT:   %[[MASK:.*]] = fir.alloca !fir.logical<4>
+// CHECK-NEXT:   %[[C1:.*]] = arith.constant 1 : index
+// CHECK-NEXT:   %[[TRUE:.*]] = arith.constant true
+// CHECK-NEXT:   %[[LOGICAL:.*]] = fir.convert %[[TRUE]] : (i1) -> !fir.logical<4>
+// CHECK-NEXT:   fir.store %[[LOGICAL:.*]] to %[[MASK:.*]] : !fir.ref<!fir.logical<4>>
+// CHECK-NEXT:   %[[BOX:.*]] = fir.embox %[[MASK:.*]] : (!fir.ref<!fir.logical<4>>) -> !fir.box<!fir.logical<4>>
+// CHECK-NEXT:   hlfir.minloc %[[ARRAY:.*]] dim %[[C1]] mask %[[BOX]] : (!fir.box<!fir.array<?xi32>>, index, !fir.box<!fir.logical<4>>) -> i32
+// CHECK-NEXT:   return
+// CHECK-NEXT: }
+
+// known shape expr mask
+func.func @minloc4(%arg0: !fir.box<!fir.array<?xi32>>, %arg1: !hlfir.expr<42x!fir.logical<4>>) {
+  %c_1 = arith.constant 1 : index
+  %0 = hlfir.minloc %arg0 dim %c_1 mask %arg1 : (!fir.box<!fir.array<?xi32>>, index, !hlfir.expr<42x!fir.logical<4>>) -> i32
+  return
+}
+// CHECK:      func.func @minloc4(%[[ARRAY:.*]]: !fir.box<!fir.array<?xi32>>, %[[MASK:.*]]: !hlfir.expr<42x!fir.logical<4>>) {
+// CHECK-NEXT:   %[[C1:.*]] = arith.constant 1 : index
+// CHECK-NEXT:   hlfir.minloc %[[ARRAY]] dim %[[C1]] mask %[[MASK]] : (!fir.box<!fir.array<?xi32>>, index, !hlfir.expr<42x!fir.logical<4>>) -> i32
+// CHECK-NEXT:   return
+// CHECK-NEXT: }
+
+// assumed shape expr mask
+func.func @minloc5(%arg0: !fir.box<!fir.array<?xi32>>, %arg1: !hlfir.expr<?x!fir.logical<4>>) {
+  %c_1 = arith.constant 1 : index
+  %0 = hlfir.minloc %arg0 dim %c_1 mask %arg1 : (!fir.box<!fir.array<?xi32>>, index, !hlfir.expr<?x!fir.logical<4>>) -> i32
+  return
+}
+// CHECK:      func.func @minloc5(%[[ARRAY:.*]]: !fir.box<!fir.array<?xi32>>, %[[MASK:.*]]: !hlfir.expr<?x!fir.logical<4>>) {
+// CHECK-NEXT:   %[[C1:.*]] = arith.constant 1 : index
+// CHECK-NEXT:   hlfir.minloc %[[ARRAY]] dim %[[C1]] mask %[[MASK]] : (!fir.box<!fir.array<?xi32>>, index, !hlfir.expr<?x!fir.logical<4>>) -> i32
+// CHECK-NEXT:   return
+// CHECK-NEXT: }
+
+// known shape array mask
+func.func @minloc6(%arg0: !fir.box<!fir.array<?xi32>>, %arg1: !fir.box<!fir.array<42x!fir.logical<4>>>) {
+  %c_1 = arith.constant 1 : index
+  %0 = hlfir.minloc %arg0 dim %c_1 mask %arg1 : (!fir.box<!fir.array<?xi32>>, index, !fir.box<!fir.array<42x!fir.logical<4>>>) -> i32
+  return
+}
+// CHECK:      func.func @minloc6(%[[ARRAY:.*]]: !fir.box<!fir.array<?xi32>>, %[[MASK:.*]]: !fir.box<!fir.array<42x!fir.logical<4>>>) {
+// CHECK-NEXT:   %[[C1:.*]] = arith.constant 1 : index
+// CHECK-NEXT:   hlfir.minloc %[[ARRAY]] dim %[[C1]] mask %[[MASK]] : (!fir.box<!fir.array<?xi32>>, index, !fir.box<!fir.array<42x!fir.logical<4>>>) -> i32
+// CHECK-NEXT:   return
+// CHECK-NEXT: }
+
+// assumed shape array mask
+func.func @minloc7(%arg0: !fir.box<!fir.array<?xi32>>, %arg1: !fir.box<!fir.array<?x!fir.logical<4>>>) {
+  %c_1 = arith.constant 1 : index
+  %0 = hlfir.minloc %arg0 dim %c_1 mask %arg1 : (!fir.box<!fir.array<?xi32>>, index, !fir.box<!fir.array<?x!fir.logical<4>>>) -> i32
+  return
+}
+// CHECK:      func.func @minloc7(%[[ARRAY:.*]]: !fir.box<!fir.array<?xi32>>, %[[MASK:.*]]: !fir.box<!fir.array<?x!fir.logical<4>>>) {
+// CHECK-NEXT:   %[[C1:.*]] = arith.constant 1 : index
+// CHECK-NEXT:   hlfir.minloc %[[ARRAY]] dim %[[C1]] mask %[[MASK]] : (!fir.box<!fir.array<?xi32>>, index, !fir.box<!fir.array<?x!fir.logical<4>>>) -> i32
+// CHECK-NEXT:   return
+// CHECK-NEXT: }
+
+// known shape expr return
+func.func @minloc8(%arg0: !fir.box<!fir.array<2x2xi32>>, %arg1: i32) {
+  %mask = fir.alloca !fir.logical<4>
+  %true = arith.constant true
+  %true_logical = fir.convert %true : (i1) -> !fir.logical<4>
+  fir.store %true_logical to %mask : !fir.ref<!fir.logical<4>>
+  %mask_box = fir.embox %mask : (!fir.ref<!fir.logical<4>>) -> !fir.box<!fir.logical<4>>
+  %0 = hlfir.minloc %arg0 dim %arg1 mask %mask_box : (!fir.box<!fir.array<2x2xi32>>, i32, !fir.box<!fir.logical<4>>) -> !hlfir.expr<2xi32>
+  return
+}
+// CHECK:      func.func @minloc8(%[[ARRAY:.*]]: !fir.box<!fir.array<2x2xi32>>, %[[DIM:.*]]: i32) {
+// CHECK-NEXT:   %[[MASK:.*]] = fir.alloca !fir.logical<4>
+// CHECK-NEXT:   %[[TRUE:.*]] = arith.constant true
+// CHECK-NEXT:   %[[LOGICAL:.*]] = fir.convert %[[TRUE]] : (i1) -> !fir.logical<4>
+// CHECK-NEXT:   fir.store %[[LOGICAL]] to %[[MASK]] : !fir.ref<!fir.logical<4>>
+// CHECK-NEXT:   %[[BOX:.*]] = fir.embox %0 : (!fir.ref<!fir.logical<4>>) -> !fir.box<!fir.logical<4>>
+// CHECK-NEXT:   hlfir.minloc %[[ARRAY]] dim %[[DIM]] mask %[[BOX]] : (!fir.box<!fir.array<2x2xi32>>, i32, !fir.box<!fir.logical<4>>) -> !hlfir.expr<2xi32>
+// CHECK-NEXT:   return
+// CHECK-NEXT: }
+
+// assumed shape expr return
+func.func @minloc9(%arg0: !fir.box<!fir.array<?x?xi32>>, %arg1: i32) {
+  %mask = fir.alloca !fir.logical<4>
+  %true = arith.constant true
+  %true_logical = fir.convert %true : (i1) -> !fir.logical<4>
+  fir.store %true_logical to %mask : !fir.ref<!fir.logical<4>>
+  %mask_box = fir.embox %mask : (!fir.ref<!fir.logical<4>>) -> !fir.box<!fir.logical<4>>
+  %0 = hlfir.minloc %arg0 dim %arg1 mask %mask_box : (!fir.box<!fir.array<?x?xi32>>, i32, !fir.box<!fir.logical<4>>) -> !hlfir.expr<?xi32>
+  return
+}
+// CHECK:      func.func @minloc9(%[[ARRAY:.*]]: !fir.box<!fir.array<?x?xi32>>, %[[DIM:.*]]: i32) {
+// CHECK-NEXT:   %[[MASK:.*]] = fir.alloca !fir.logical<4>
+// CHECK-NEXT:   %[[TRUE:.*]] = arith.constant true
+// CHECK-NEXT:   %[[LOGICAL:.*]] = fir.convert %[[TRUE]] : (i1) -> !fir.logical<4>
+// CHECK-NEXT:   fir.store %[[LOGICAL]] to %[[MASK]] : !fir.ref<!fir.logical<4>>
+// CHECK-NEXT:   %[[BOX:.*]] = fir.embox %0 : (!fir.ref<!fir.logical<4>>) -> !fir.box<!fir.logical<4>>
+// CHECK-NEXT:   hlfir.minloc %[[ARRAY]] dim %[[DIM]] mask %[[BOX]] : (!fir.box<!fir.array<?x?xi32>>, i32, !fir.box<!fir.logical<4>>) -> !hlfir.expr<?xi32>
+// CHECK-NEXT:   return
+// CHECK-NEXT: }
+
+// hlfir.minloc with only an array argument
+func.func @minloc10(%arg0: !fir.box<!fir.array<?x?xi32>>) {
+  %minloc = hlfir.minloc %arg0 : (!fir.box<!fir.array<?x?xi32>>) -> !hlfir.expr<1xi32>
+  return
+}
+// CHECK:      func.func @minloc10(%[[ARRAY:.*]]: !fir.box<!fir.array<?x?xi32>>
+// CHECK-NEXT:   %[[minloc:.*]] = hlfir.minloc %[[ARRAY]] : (!fir.box<!fir.array<?x?xi32>>) -> !hlfir.expr<1xi32>
+// CHECK-NEXT:   return
+// CHECK-NEXT: }
+
+// hlfir.minloc with only a character array argument
+func.func @minloc11(%arg0: !fir.box<!fir.array<?x?x!fir.char<1,?>>>) {
+  %minloc = hlfir.minloc %arg0 : (!fir.box<!fir.array<?x?x!fir.char<1,?>>>) -> !hlfir.expr<1xi32>
+  return
+}
+// CHECK:      func.func @minloc11(%[[ARRAY:.*]]: !fir.box<!fir.array<?x?x!fir.char<1,?>>>
+// CHECK-NEXT:   %[[minloc:.*]] = hlfir.minloc %[[ARRAY]] : (!fir.box<!fir.array<?x?x!fir.char<1,?>>>) -> !hlfir.expr<1xi32>
+// CHECK-NEXT:   return
+// CHECK-NEXT: }
+
+// hlfir.minloc with array and dim argument
+func.func @minloc12(%arg0: !fir.box<!fir.array<?x?xi32>>, %arg1: i32) {
+  %minloc = hlfir.minloc %arg0 dim %arg1 : (!fir.box<!fir.array<?x?xi32>>, i32) -> !hlfir.expr<?xi32>
+  return
+}
+// CHECK:      func.func @minloc12(%[[ARRAY:.*]]: !fir.box<!fir.array<?x?xi32>>, %[[DIM:.*]]: i32
+// CHECK-NEXT:   %[[minloc:.*]] = hlfir.minloc %[[ARRAY]] dim %[[DIM]] : (!fir.box<!fir.array<?x?xi32>>, i32) -> !hlfir.expr<?xi32>
+// CHECK-NEXT:   return
+// CHECK-NEXT: }
+
+// hlfir.minloc with array and mask argument
+func.func @minloc13(%arg0: !fir.box<!fir.array<?xi32>>, %arg1: !fir.logical<4>) {
+  %minloc = hlfir.minloc %arg0 mask %arg1 : (!fir.box<!fir.array<?xi32>>, !fir.logical<4>) -> !hlfir.expr<1xi32>
+  return
+}
+// CHECK:      func.func @minloc13(%[[ARRAY:.*]]: !fir.box<!fir.array<?xi32>>, %[[MASK:.*]]: !fir.logical<4>
+// CHECK-NEXT:   %[[minloc:.*]] = hlfir.minloc %[[ARRAY]] mask %[[MASK]] : (!fir.box<!fir.array<?xi32>>, !fir.logical<4>) -> !hlfir.expr<1xi32>
+// CHECK-NEXT:   return
+// CHECK-NEXT: }
+
+// hlfir.minloc with dim argument with an unusual type
+func.func @minloc14(%arg0: !fir.box<!fir.array<?x?xi32>>, %arg1: index) {
+  %minloc = hlfir.minloc %arg0 dim %arg1 : (!fir.box<!fir.array<?x?xi32>>, index) -> !hlfir.expr<?xi32>
+  return
+}
+// CHECK:      func.func @minloc14(%[[ARRAY:.*]]: !fir.box<!fir.array<?x?xi32>>, %[[DIM:.*]]: index
+// CHECK-NEXT:   %[[minloc:.*]] = hlfir.minloc %[[ARRAY]] dim %[[DIM]] : (!fir.box<!fir.array<?x?xi32>>, index) -> !hlfir.expr<?xi32>
+// CHECK-NEXT:   return
+// CHECK-NEXT: }
+
+// hlfir.minloc with mask argument of unusual type
+func.func @minloc15(%arg0: !fir.box<!fir.array<?xi32>>, %arg1: i1) {
+  %minloc = hlfir.minloc %arg0 mask %arg1 : (!fir.box<!fir.array<?xi32>>, i1) -> !hlfir.expr<1xi32>
+  return
+}
+// CHECK:      func.func @minloc15(%[[ARRAY:.*]]: !fir.box<!fir.array<?xi32>>, %[[MASK:.*]]: i1
+// CHECK-NEXT:   %[[minloc:.*]] = hlfir.minloc %[[ARRAY]] mask %[[MASK]] : (!fir.box<!fir.array<?xi32>>, i1) -> !hlfir.expr<1xi32>
+// CHECK-NEXT:   return
+// CHECK-NEXT: }
+
+// hlfir.minloc with mask argument of ref<array<>> type
+func.func @minloc16(%arg0: !fir.box<!fir.array<?xi32>>, %arg1: !fir.ref<!fir.array<?x!fir.logical<4>>>) {
+  %minloc = hlfir.minloc %arg0 mask %arg1 : (!fir.box<!fir.array<?xi32>>, !fir.ref<!fir.array<?x!fir.logical<4>>>) -> !hlfir.expr<1xi32>
+  return
+}
+// CHECK:      func.func @minloc16(%[[ARRAY:.*]]: !fir.box<!fir.array<?xi32>>, %[[MASK:.*]]: !fir.ref<!fir.array<?x!fir.logical<4>>>
+// CHECK-NEXT:   %[[minloc:.*]] = hlfir.minloc %[[ARRAY]] mask %[[MASK]] : (!fir.box<!fir.array<?xi32>>, !fir.ref<!fir.array<?x!fir.logical<4>>>) -> !hlfir.expr<1xi32>
+// CHECK-NEXT:   return
+// CHECK-NEXT: }
+
+
+// hlfir.minloc with kind implied by the return type
+func.func @minloc17(%arg0: !fir.box<!fir.array<?xi32>>, %arg1: i1) {
+  %minloc = hlfir.minloc %arg0 mask %arg1 : (!fir.box<!fir.array<?xi32>>, i1) -> !hlfir.expr<1xi16>
+  return
+}
+// CHECK:      func.func @minloc17(%[[ARRAY:.*]]: !fir.box<!fir.array<?xi32>>, %[[MASK:.*]]: i1
+// CHECK-NEXT:   %[[minloc:.*]] = hlfir.minloc %[[ARRAY]] mask %[[MASK]] : (!fir.box<!fir.array<?xi32>>, i1) -> !hlfir.expr<1xi16>
+// CHECK-NEXT:   return
+// CHECK-NEXT: }
+
+// hlfir.minloc with back argument
+func.func @minloc18(%arg0: !fir.box<!fir.array<?xi32>>, %arg1: i1) {
+  %true = arith.constant true
+  %minloc = hlfir.minloc %arg0 mask %arg1 back %true : (!fir.box<!fir.array<?xi32>>, i1, i1) -> !hlfir.expr<1xi32>
+  return
+}
+// CHECK:      func.func @minloc18(%[[ARRAY:.*]]: !fir.box<!fir.array<?xi32>>, %[[MASK:.*]]: i1
+// CHECK-NEXT:   %[[C2:.*]] = arith.constant true
+// CHECK-NEXT:   %[[minloc:.*]] = hlfir.minloc %[[ARRAY]] mask %[[MASK]] back %[[C2]] : (!fir.box<!fir.array<?xi32>>, i1, i1) -> !hlfir.expr<1xi32>
+// CHECK-NEXT:   return
+// CHECK-NEXT: }
\ No newline at end of file
diff --git a/flang/test/Lower/HLFIR/minloc.f90 b/flang/test/Lower/HLFIR/minloc.f90
new file mode 100644
index 000000000000..c27430689ee0
--- /dev/null
+++ b/flang/test/Lower/HLFIR/minloc.f90
@@ -0,0 +1,370 @@
+! Test lowering of MINLOC intrinsic to HLFIR
+! RUN: bbc -emit-hlfir -o - %s 2>&1 | FileCheck %s
+
+! simple 1 argument MINLOC
+subroutine minloc1(a, s)
+  integer :: a(:), s(:)
+  s = MINLOC(a)
+end subroutine
+! CHECK-LABEL: func.func @_QPminloc1(
+! CHECK:           %[[ARG0:.*]]: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "a"}, %[[ARG1:.*]]: !fir.box<!fir.array<?xi32>>
+! CHECK-DAG:     %[[ARRAY:.*]]:2 = hlfir.declare %[[ARG0]]
+! CHECK-DAG:     %[[OUT:.*]]:2 = hlfir.declare %[[ARG1]]
+! CHECK-NEXT:    %[[EXPR:.*]] = hlfir.minloc %[[ARRAY]]#0 {fastmath = #arith.fastmath<contract>} : (!fir.box<!fir.array<?xi32>>) -> !hlfir.expr<1xi32>
+! CHECK-NEXT:    hlfir.assign %[[EXPR]] to %[[OUT]]#0 : !hlfir.expr<1xi32>, !fir.box<!fir.array<?xi32>>
+! CHECK-NEXT:    hlfir.destroy %[[EXPR]] : !hlfir.expr<1xi32>
+! CHECK-NEXT:    return
+! CHECK-NEXT:  }
+
+! minloc with by-ref DIM argument
+subroutine minloc2(a, s, d)
+  integer :: a(:,:), s(:), d
+  s = MINLOC(a, d)
+end subroutine
+! CHECK-LABEL: func.func @_QPminloc2(
+! CHECK:           %[[ARG0:.*]]: !fir.box<!fir.array<?x?xi32>> {fir.bindc_name = "a"}, %[[ARG1:.*]]: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "s"}, %[[ARG2:.*]]: !fir.ref<i32>
+! CHECK-DAG:     %[[ARRAY:.*]]:2 = hlfir.declare %[[ARG0]]
+! CHECK-DAG:     %[[OUT:.*]]:2 = hlfir.declare %[[ARG1]]
+! CHECK-DAG:     %[[DIM_REF:.*]]:2 = hlfir.declare %[[ARG2]]
+! CHECK-NEXT:    %[[DIM:.*]] = fir.load %[[DIM_REF]]#0 : !fir.ref<i32>
+! CHECK-NEXT:    %[[EXPR:.*]] = hlfir.minloc %[[ARRAY]]#0 dim %[[DIM]] {fastmath = #arith.fastmath<contract>} : (!fir.box<!fir.array<?x?xi32>>, i32) -> !hlfir.expr<?xi32>
+! CHECK-NEXT:    hlfir.assign %[[EXPR]] to %[[OUT]]#0 : !hlfir.expr<?xi32>, !fir.box<!fir.array<?xi32>>
+! CHECK-NEXT:    hlfir.destroy %[[EXPR]]
+! CHECK-NEXT:    return
+! CHECK-NEXT:  }
+
+! minloc with scalar mask argument
+subroutine minloc3(a, s, m)
+  integer :: a(:), s(:)
+  logical :: m
+  s = MINLOC(a, m)
+end subroutine
+! CHECK-LABEL: func.func @_QPminloc3(
+! CHECK:           %[[ARG0:.*]]: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "a"}, %[[ARG1:.*]]: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "s"}, %[[ARG2:.*]]: !fir.ref<!fir.logical<4>>
+! CHECK-DAG:     %[[ARRAY:.*]]:2 = hlfir.declare %[[ARG0]]
+! CHECK-DAG:     %[[OUT:.*]]:2 = hlfir.declare %[[ARG1]]
+! CHECK-DAG:     %[[MASK:.*]]:2 = hlfir.declare %[[ARG2]]
+! CHECK-NEXT:    %[[EXPR:.*]] = hlfir.minloc %[[ARRAY]]#0 mask %[[MASK]]#0 {fastmath = #arith.fastmath<contract>} : (!fir.box<!fir.array<?xi32>>, !fir.ref<!fir.logical<4>>) -> !hlfir.expr<1xi32>
+! CHECK-NEXT:    hlfir.assign %[[EXPR]] to %[[OUT]]#0 : !hlfir.expr<1xi32>, !fir.box<!fir.array<?xi32>>
+! CHECK-NEXT:    hlfir.destroy %[[EXPR]] : !hlfir.expr<1xi32>
+! CHECK-NEXT:    return
+! CHECK-NEXT:  }
+
+! minloc with array mask argument
+subroutine minloc4(a, s, m)
+  integer :: a(:), s(:)
+  logical :: m(:)
+  s = MINLOC(a, m)
+end subroutine
+! CHECK-LABEL: func.func @_QPminloc4(
+! CHECK:           %[[ARG0:.*]]: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "a"}, %[[ARG1:.*]]: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "s"}, %[[ARG2:.*]]: !fir.box<!fir.array<?x!fir.logical<4>>>
+! CHECK-DAG:     %[[ARRAY:.*]]:2 = hlfir.declare %[[ARG0]]
+! CHECK-DAG:     %[[OUT:.*]]:2 = hlfir.declare %[[ARG1]]
+! CHECK-DAG:     %[[MASK:.*]]:2 = hlfir.declare %[[ARG2]]
+! CHECK-NEXT:    %[[EXPR:.*]] = hlfir.minloc %[[ARRAY]]#0 mask %[[MASK]]#0 {fastmath = #arith.fastmath<contract>} : (!fir.box<!fir.array<?xi32>>, !fir.box<!fir.array<?x!fir.logical<4>>>) -> !hlfir.expr<1xi32>
+! CHECK-NEXT:    hlfir.assign %[[EXPR]] to %[[OUT]]#0 : !hlfir.expr<1xi32>, !fir.box<!fir.array<?xi32>>
+! CHECK-NEXT:    hlfir.destroy %[[EXPR]] : !hlfir.expr<1xi32>
+! CHECK-NEXT:    return
+! CHECK-NEXT:  }
+
+! minloc with all 3 arguments, dim is by-val, array isn't boxed
+subroutine minloc5(s)
+  integer :: s(2)
+  integer :: a(2,2) = reshape((/1, 2, 3, 4/), [2,2])
+  s = minloc(a, 1, .true.)
+end subroutine
+! CHECK-LABEL: func.func @_QPminloc5
+! CHECK:           %[[ARG0:.*]]: !fir.ref<!fir.array<2xi32>>
+! CHECK-DAG:     %[[ADDR:.*]] = fir.address_of({{.*}}) : !fir.ref<!fir.array<2x2xi32>>
+! CHECK-DAG:     %[[ARRAY_SHAPE:.*]] = fir.shape {{.*}} -> !fir.shape<2>
+! CHECK-DAG:     %[[ARRAY:.*]]:2 = hlfir.declare %[[ADDR]](%[[ARRAY_SHAPE]])
+! CHECK-DAG:     %[[OUT_SHAPE:.*]] = fir.shape {{.*}} -> !fir.shape<1>
+! CHECK-DAG:     %[[OUT:.*]]:2 = hlfir.declare %[[ARG0]](%[[OUT_SHAPE]])
+! CHECK-DAG:     %[[TRUE:.*]] = arith.constant true
+! CHECK-DAG:     %[[C1:.*]] = arith.constant 1 : i32
+! CHECK-NEXT:    %[[EXPR:.*]] = hlfir.minloc %[[ARRAY]]#0 dim %[[C1]] mask %[[TRUE]] {fastmath = #arith.fastmath<contract>} : (!fir.ref<!fir.array<2x2xi32>>, i32, i1) -> !hlfir.expr<2xi32>
+! CHECK-NEXT:    hlfir.assign %[[EXPR]] to %[[OUT]]#0 : !hlfir.expr<2xi32>, !fir.ref<!fir.array<2xi32>>
+! CHECK-NEXT:    hlfir.destroy %[[EXPR]] : !hlfir.expr<2xi32>
+! CHECK-NEXT:    return
+! CHECK-nEXT:  }
+
+! back argument as .true.
+subroutine minloc_back(a, s)
+  integer :: a(:), s(:)
+  s = MINLOC(a, BACK=.TRUE.)
+end subroutine
+! CHECK-LABEL: func.func @_QPminloc_back(
+! CHECK:           %[[ARG0:.*]]: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "a"}, %[[ARG1:.*]]: !fir.box<!fir.array<?xi32>>
+! CHECK-DAG:     %[[ARRAY:.*]]:2 = hlfir.declare %[[ARG0]]
+! CHECK-DAG:     %[[OUT:.*]]:2 = hlfir.declare %[[ARG1]]
+! CHECK-DAG:     %[[C1:.*]] = arith.constant true
+! CHECK-NEXT:    %[[EXPR:.*]] = hlfir.minloc %[[ARRAY]]#0 back %[[C1]] {fastmath = #arith.fastmath<contract>} : (!fir.box<!fir.array<?xi32>>, i1) -> !hlfir.expr<1xi32>
+! CHECK-NEXT:    hlfir.assign %[[EXPR]] to %[[OUT]]#0 : !hlfir.expr<1xi32>, !fir.box<!fir.array<?xi32>>
+! CHECK-NEXT:    hlfir.destroy %[[EXPR]] : !hlfir.expr<1xi32>
+! CHECK-NEXT:    return
+! CHECK-NEXT:  }
+
+! back argument as logical
+subroutine minloc_back2(a, s, b)
+  integer :: a(:), s(:)
+  logical :: b
+  s = MINLOC(a, BACK=b)
+end subroutine
+! CHECK-LABEL: func.func @_QPminloc_back2(
+! CHECK:           %[[ARG0:.*]]: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "a"}, %[[ARG1:.*]]: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "s"}, %[[ARG2:.*]]: !fir.ref<!fir.logical<4>>
+! CHECK-DAG:     %[[ARRAY:.*]]:2 = hlfir.declare %[[ARG0]]
+! CHECK-DAG:     %[[BACKD:.*]]:2 = hlfir.declare %[[ARG2]]
+! CHECK-DAG:     %[[OUT:.*]]:2 = hlfir.declare %[[ARG1]]
+! CHECK-NEXT:    %[[BACK:.*]] = fir.load %[[BACKD]]#0 : !fir.ref<!fir.logical<4>>
+! CHECK-NEXT:    %[[EXPR:.*]] = hlfir.minloc %[[ARRAY]]#0 back %[[BACK]] {fastmath = #arith.fastmath<contract>} : (!fir.box<!fir.array<?xi32>>, !fir.logical<4>) -> !hlfir.expr<1xi32>
+! CHECK-NEXT:    hlfir.assign %[[EXPR]] to %[[OUT]]#0 : !hlfir.expr<1xi32>, !fir.box<!fir.array<?xi32>>
+! CHECK-NEXT:    hlfir.destroy %[[EXPR]] : !hlfir.expr<1xi32>
+! CHECK-NEXT:    return
+! CHECK-NEXT:  }
+
+! back argument as optional logical
+subroutine minloc_back3(a, s, b)
+  integer :: a(:), s(:)
+  logical, optional :: b
+  s = MINLOC(a, BACK=b)
+end subroutine
+! CHECK-LABEL: func.func @_QPminloc_back3(
+! CHECK:           %[[ARG0:.*]]: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "a"}, %[[ARG1:.*]]: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "s"}, %[[ARG2:.*]]: !fir.ref<!fir.logical<4>> {fir.bindc_name = "b", fir.optional}) {
+! CHECK:        %[[ARRAY:.*]]:2 = hlfir.declare %[[ARG0]]
+! CHECK-NEXT:   %[[BACKD:.*]]:2 = hlfir.declare %[[ARG2]]
+! CHECK-NEXT:   %[[OUT:.*]]:2 = hlfir.declare %[[ARG1]]
+! CHECK-NEXT:   %[[IFP:.*]] = fir.is_present %[[BACKD]]#0 : (!fir.ref<!fir.logical<4>>) -> i1
+! CHECK-NEXT:   %[[BACK:.*]] = fir.if %[[IFP]] -> (!fir.logical<4>) {
+! CHECK-NEXT:     %[[IFT:.*]] = fir.load %[[BACKD]]#0 : !fir.ref<!fir.logical<4>>
+! CHECK-NEXT:     fir.result %[[IFT]] : !fir.logical<4>
+! CHECK-NEXT:   } else {
+! CHECK-NEXT:     %false = arith.constant false
+! CHECK-NEXT:     %[[IFE:.*]] = fir.convert %false : (i1) -> !fir.logical<4>
+! CHECK-NEXT:     fir.result %[[IFE]] : !fir.logical<4>
+! CHECK-NEXT:   }
+! CHECK-NEXT:   %[[EXPR:.*]] = hlfir.minloc %[[ARRAY]]#0 back %[[BACK]] {fastmath = #arith.fastmath<contract>} : (!fir.box<!fir.array<?xi32>>, !fir.logical<4>) -> !hlfir.expr<1xi32>
+! CHECK-NEXT:   hlfir.assign %[[EXPR]] to %[[OUT]]#0 : !hlfir.expr<1xi32>, !fir.box<!fir.array<?xi32>>
+! CHECK-NEXT:   hlfir.destroy %[[EXPR]] : !hlfir.expr<1xi32>
+! CHECK-NEXT:   return
+! CHECK-NEXT: }
+
+
+! kind = 2
+subroutine minloc_kind(a, s)
+  integer :: a(:), s(:)
+  s = MINLOC(a, KIND=2)
+end subroutine
+! CHECK-LABEL: func.func @_QPminloc_kind(
+! CHECK:           %[[ARG0:.*]]: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "a"}, %[[ARG1:.*]]: !fir.box<!fir.array<?xi32>>
+! CHECK-DAG:     %[[ARRAY:.*]]:2 = hlfir.declare %[[ARG0]]
+! CHECK-DAG:     %[[OUT:.*]]:2 = hlfir.declare %[[ARG1]]
+! CHECK:         %[[EXPR:.*]] = hlfir.minloc %[[ARRAY]]#0 {fastmath = #arith.fastmath<contract>} : (!fir.box<!fir.array<?xi32>>) -> !hlfir.expr<1xi16>
+! CHECK:         %[[ELM:.*]] = hlfir.elemental
+! CHECK:         hlfir.assign %[[ELM]] to %[[OUT]]#0 : !hlfir.expr<?xi32>, !fir.box<!fir.array<?xi32>>
+! CHECK-NEXT:    hlfir.destroy %[[ELM]] : !hlfir.expr<?xi32>
+! CHECK-NEXT:    hlfir.destroy %[[EXPR]] : !hlfir.expr<1xi16>
+! CHECK-NEXT:    return
+! CHECK-NEXT:  }
+
+subroutine minloc6(a, s, d)
+  integer, pointer :: d
+  integer s(:)
+  real :: a(:,:)
+  s = minloc(a, (d))
+end subroutine
+! CHECK-LABEL: func.func @_QPminloc6(
+! CHECK:           %[[ARG0:.*]]: !fir.box<!fir.array<?x?xf32>>
+! CHECK:           %[[ARG1:.*]]: !fir.box<!fir.array<?xi32>>
+! CHECK:           %[[ARG2:.*]]: !fir.ref<!fir.box<!fir.ptr<i32>>>
+! CHECK-DAG:     %[[ARRAY:.*]]:2 = hlfir.declare %[[ARG0]]
+! CHECK-DAG:     %[[OUT:.*]]:2 = hlfir.declare %[[ARG1]]
+! CHECK-DAG:     %[[DIM_VAR:.*]]:2 = hlfir.declare %[[ARG2]]
+! CHECK-NEXT:     %[[DIM_BOX:.*]] = fir.load %[[DIM_VAR]]#0 : !fir.ref<!fir.box<!fir.ptr<i32>>>
+! CHECK-NEXT:    %[[DIM_ADDR:.*]] = fir.box_addr %[[DIM_BOX]] : (!fir.box<!fir.ptr<i32>>) -> !fir.ptr<i32>
+! CHECK-NEXT:    %[[DIM0:.*]] = fir.load %[[DIM_ADDR]] : !fir.ptr<i32>
+! CHECK-NEXT:    %[[DIM1:.*]] = hlfir.no_reassoc %[[DIM0]] : i32
+! CHECK-NEXT:    %[[EXPR:.*]] = hlfir.minloc %[[ARRAY]]#0 dim %[[DIM1]] {fastmath = #arith.fastmath<contract>} : (!fir.box<!fir.array<?x?xf32>>, i32) -> !hlfir.expr<?xi32>
+! CHECK-NEXT:    hlfir.assign %[[EXPR]] to %[[OUT]]#0 : !hlfir.expr<?xi32>, !fir.box<!fir.array<?xi32>>
+! CHECK-NEXT:    hlfir.destroy %[[EXPR]]
+! CHECK-NEXT:    return
+! CHECK-NEXT:  }
+
+! simple 1 argument MINLOC for character
+subroutine minloc7(a, s)
+  character(*) :: a(:)
+  integer :: s(:)
+  s = MINLOC(a)
+end subroutine
+! CHECK-LABEL: func.func @_QPminloc7(
+! CHECK:           %[[ARG0:.*]]: !fir.box<!fir.array<?x!fir.char<1,?>>> {fir.bindc_name = "a"}, %[[ARG1:.*]]: !fir.box<!fir.array<?xi32>>
+! CHECK-DAG:     %[[ARRAY:.*]]:2 = hlfir.declare %[[ARG0]]
+! CHECK-DAG:     %[[OUT:.*]]:2 = hlfir.declare %[[ARG1]]
+! CHECK-NEXT:    %[[EXPR:.*]] = hlfir.minloc %[[ARRAY]]#0 {fastmath = #arith.fastmath<contract>} : (!fir.box<!fir.array<?x!fir.char<1,?>>>) -> !hlfir.expr<1xi32>
+! CHECK-NEXT:    hlfir.assign %[[EXPR]] to %[[OUT]]#0 : !hlfir.expr<1xi32>, !fir.box<!fir.array<?xi32>>
+! CHECK-NEXT:    hlfir.destroy %[[EXPR]]
+! CHECK-NEXT:    return
+! CHECK-NEXT:  }
+
+! minloc for character with by-ref DIM argument
+subroutine minloc8(a, s, d)
+  character(*) :: a(:,:)
+  integer :: d, s(:)
+  s = MINLOC(a, d)
+end subroutine
+! CHECK-LABEL: func.func @_QPminloc8(
+! CHECK:           %[[ARG0:.*]]: !fir.box<!fir.array<?x?x!fir.char<1,?>>> {fir.bindc_name = "a"}, %[[ARG1:.*]]: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "s"}, %[[ARG2:.*]]: !fir.ref<i32>
+! CHECK-DAG:     %[[ARRAY:.*]]:2 = hlfir.declare %[[ARG0]]
+! CHECK-DAG:     %[[OUT:.*]]:2 = hlfir.declare %[[ARG1]]
+! CHECK-DAG:     %[[DIM_REF:.*]]:2 = hlfir.declare %[[ARG2]]
+! CHECK-NEXT:    %[[DIM:.*]] = fir.load %[[DIM_REF]]#0 : !fir.ref<i32>
+! CHECK-NEXT:    %[[EXPR:.*]] = hlfir.minloc %[[ARRAY]]#0 dim %[[DIM]] {fastmath = #arith.fastmath<contract>} : (!fir.box<!fir.array<?x?x!fir.char<1,?>>>, i32) -> !hlfir.expr<?xi32>
+! CHECK-NEXT:    hlfir.assign %[[EXPR]] to %[[OUT]]#0 : !hlfir.expr<?xi32>, !fir.box<!fir.array<?xi32>>
+! CHECK-NEXT:    hlfir.destroy %[[EXPR]]
+! CHECK-NEXT:    return
+! CHECK-NEXT:  }
+
+! minloc for character with scalar mask argument
+subroutine minloc9(a, s, m)
+  character(*) :: a(:)
+  integer :: s(:)
+  logical :: m
+  s = MINLOC(a, m)
+end subroutine
+! CHECK-LABEL: func.func @_QPminloc9(
+! CHECK:           %[[ARG0:.*]]: !fir.box<!fir.array<?x!fir.char<1,?>>> {fir.bindc_name = "a"}, %[[ARG1:.*]]: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "s"}, %[[ARG2:.*]]: !fir.ref<!fir.logical<4>>
+! CHECK-DAG:     %[[ARRAY:.*]]:2 = hlfir.declare %[[ARG0]]
+! CHECK-DAG:     %[[OUT:.*]]:2 = hlfir.declare %[[ARG1]]
+! CHECK-DAG:     %[[MASK:.*]]:2 = hlfir.declare %[[ARG2]]
+! CHECK-NEXT:    %[[EXPR:.*]] = hlfir.minloc %[[ARRAY]]#0 mask %[[MASK]]#0 {fastmath = #arith.fastmath<contract>} : (!fir.box<!fir.array<?x!fir.char<1,?>>>, !fir.ref<!fir.logical<4>>) -> !hlfir.expr<1xi32>
+! CHECK-NEXT:    hlfir.assign %[[EXPR]] to %[[OUT]]#0 : !hlfir.expr<1xi32>, !fir.box<!fir.array<?xi32>>
+! CHECK-NEXT:    hlfir.destroy %[[EXPR]]
+! CHECK-NEXT:    return
+! CHECK-NEXT:  }
+
+subroutine testDynamicallyOptionalMask(array, mask, res)
+  integer :: array(:), res(:)
+  logical, allocatable :: mask(:)
+  res = MINLOC(array, mask=mask)
+end subroutine
+! CHECK-LABEL: func.func @_QPtestdynamicallyoptionalmask(
+! CHECK-SAME:      %[[ARG0:.*]]: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "array"}
+! CHECK-SAME:      %[[ARG1:.*]]: !fir.ref<!fir.box<!fir.heap<!fir.array<?x!fir.logical<4>>>>>
+! CHECK-SAME:      %[[ARG2:.*]]: !fir.box<!fir.array<?xi32>>
+! CHECK-DAG:     %[[ARRAY:.*]]:2 = hlfir.declare %[[ARG0]]
+! CHECK-DAG:     %[[MASK:.*]]:2 = hlfir.declare %[[ARG1]]
+! CHECK-DAG:     %[[RES:.*]]:2 = hlfir.declare %[[ARG2]]
+! CHECK-NEXT:    %[[MASK_LOAD:.*]] = fir.load %[[MASK]]#1
+! CHECK-NEXT:    %[[MASK_ADDR:.*]] = fir.box_addr %[[MASK_LOAD]]
+! CHECK-NEXT:    %[[MASK_ADDR_INT:.*]] = fir.convert %[[MASK_ADDR]]
+! CHECK-NEXT:    %[[C0:.*]] = arith.constant 0 : i64
+! CHECK-NEXT:    %[[CMP:.*]] = arith.cmpi ne, %[[MASK_ADDR_INT]], %[[C0]] : i64
+! it is a shame there is a second load here. The first is generated for
+! PreparedActualArgument::isPresent, the second is for optional handling
+! CHECK-NEXT:    %[[MASK_LOAD2:.*]] = fir.load %[[MASK]]#1
+! CHECK-NEXT:    %[[ABSENT:.*]] = fir.absent !fir.box<!fir.heap<!fir.array<?x!fir.logical<4>>>>
+! CHECK-NEXT:    %[[SELECT:.*]] = arith.select %[[CMP]], %[[MASK_LOAD2]], %[[ABSENT]]
+! CHECK-NEXT:    %[[MINLOC:.*]] = hlfir.minloc %[[ARRAY]]#0 mask %[[SELECT]]
+! CHECK-NEXT:    hlfir.assign %[[MINLOC]] to %[[RES]]#0
+! CHECK-NEXT:    hlfir.destroy %[[MINLOC]]
+! CHECK-NEXT:    return
+! CHECK-NEXT:  }
+
+subroutine testAllocatableArray(array, mask, res)
+  integer, allocatable :: array(:)
+  integer :: res(:)
+  logical :: mask(:)
+  res = MINLOC(array, mask=mask)
+end subroutine
+! CHECK-LABEL: func.func @_QPtestallocatablearray(
+! CHECK-SAME:      %[[ARG0:.*]]: !fir.ref<!fir.box<!fir.heap<!fir.array<?xi32>>>>
+! CHECK-SAME:      %[[ARG1:.*]]: !fir.box<!fir.array<?x!fir.logical<4>>>
+! CHECK-SAME:      %[[ARG2:.*]]: !fir.box<!fir.array<?xi32>>
+! CHECK-DAG:     %[[ARRAY:.*]]:2 = hlfir.declare %[[ARG0]]
+! CHECK-DAG:     %[[MASK:.*]]:2 = hlfir.declare %[[ARG1]]
+! CHECK-DAG:     %[[RES:.*]]:2 = hlfir.declare %[[ARG2]]
+! CHECK-NEXT:    %[[LOADED_ARRAY:.*]] = fir.load %[[ARRAY]]#0
+! CHECK-NEXT:    %[[MINLOC:.*]] = hlfir.minloc %[[LOADED_ARRAY]] mask %[[MASK]]#0
+! CHECK-NEXT:    hlfir.assign %[[MINLOC]] to %[[RES]]#0
+! CHECK-NEXT:    hlfir.destroy %[[MINLOC]]
+! CHECK-NEXT:    return
+! CHECK-NEXT:  }
+
+function testOptionalScalar(array, mask)
+  integer :: array(:)
+  logical, optional :: mask
+  integer :: testOptionalScalar(1)
+  testOptionalScalar = minloc(array, mask)
+end function
+! CHECK-LABEL:   func.func @_QPtestoptionalscalar(
+! CHECK-SAME:                                     %[[ARRAY_ARG:.*]]: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "array"},
+! CHECK-SAME:                                     %[[MASK_ARG:.*]]: !fir.ref<!fir.logical<4>> {fir.bindc_name = "mask", fir.optional}) -> !fir.array<1xi32>
+! CHECK:           %[[ARRAY_VAR:.*]]:2 = hlfir.declare %[[ARRAY_ARG]]
+! CHECK:           %[[MASK_VAR:.*]]:2 = hlfir.declare %[[MASK_ARG]]
+! CHECK:           %[[RET_ALLOC:.*]] = fir.alloca !fir.array<1xi32> {bindc_name = "testoptionalscalar", uniq_name = "_QFtestoptionalscalarEtestoptionalscalar"}
+! CHECK:           %[[RET_VAR:.*]]:2 = hlfir.declare %[[RET_ALLOC]]
+! CHECK:           %[[MASK_IS_PRESENT:.*]] = fir.is_present %[[MASK_VAR]]#0 : (!fir.ref<!fir.logical<4>>) -> i1
+! CHECK:           %[[MASK_BOX:.*]] = fir.embox %[[MASK_VAR]]#1
+! CHECK:           %[[ABSENT:.*]] = fir.absent !fir.box<!fir.logical<4>>
+! CHECK:           %[[MASK_SELECT:.*]] = arith.select %[[MASK_IS_PRESENT]], %[[MASK_BOX]], %[[ABSENT]]
+! CHECK:           %[[RES:.*]] = hlfir.minloc %[[ARRAY_VAR]]#0 mask %[[MASK_SELECT]] {{.*}}: (!fir.box<!fir.array<?xi32>>, !fir.box<!fir.logical<4>>) -> !hlfir.expr<1xi32>
+! CHECK:           hlfir.assign %[[RES]] to %[[RET_VAR]]#0
+! CHECK:           hlfir.destroy %[[RES]]
+! CHECK:           %[[RET:.*]] = fir.load %[[RET_VAR]]#1 : !fir.ref<!fir.array<1xi32>>
+! CHECK:           return %[[RET]] : !fir.array<1xi32>
+! CHECK:         }
+
+! Test that hlfir.minloc lowering inherits constant
+! character length from the argument, when the length
+! is unknown from the Fortran::evaluate expression type.
+subroutine test_unknown_char_len_result
+  character(len=3) :: array(3,3)
+  integer :: res(2)
+  res = minloc(array(:,:)(:))
+end subroutine test_unknown_char_len_result
+! CHECK-LABEL:   func.func @_QPtest_unknown_char_len_result() {
+! CHECK-DAG:       %[[C3:.*]] = arith.constant 3 : index
+! CHECK-DAG:       %[[C3_0:.*]] = arith.constant 3 : index
+! CHECK-DAG:       %[[C3_1:.*]] = arith.constant 3 : index
+! CHECK-DAG:       %[[ARRAY_ALLOC:.*]] = fir.alloca !fir.array<3x3x!fir.char<1,3>>
+! CHECK-DAG:       %[[ARRAY_SHAPE:.*]] = fir.shape %[[C3_0]], %[[C3_1]] : (index, index) -> !fir.shape<2>
+! CHECK-DAG:       %[[ARRAY:.*]]:2 = hlfir.declare %[[ARRAY_ALLOC]](%[[ARRAY_SHAPE]]) typeparams %[[C3]]
+! CHECK-DAG:       %[[C2:.*]] = arith.constant 2 : index
+! CHECK-DAG:       %[[RES_ALLOC:.*]] = fir.alloca !fir.array<2xi32>
+! CHECK-DAG:       %[[RES_SHAPE:.*]] = fir.shape %[[C2]] : (index) -> !fir.shape<1>
+! CHECK-DAG:       %[[RES:.*]]:2 = hlfir.declare %[[RES_ALLOC]](%[[RES_SHAPE]])
+! CHECK-DAG:       %[[C1:.*]] = arith.constant 1 : index
+! CHECK-DAG:       %[[C1_3:.*]] = arith.constant 1 : index
+! CHECK-DAG:       %[[C3_4:.*]] = arith.constant 3 : index
+! CHECK-DAG:       %[[C1_5:.*]] = arith.constant 1 : index
+! CHECK-DAG:       %[[C3_6:.*]] = arith.constant 3 : index
+! CHECK-DAG:       %[[SHAPE:.*]] = fir.shape %[[C3_4]], %[[C3_6]] : (index, index) -> !fir.shape<2>
+! CHECK-DAG:       %[[C1_7:.*]] = arith.constant 1 : index
+! CHECK-DAG:       %[[C3_8:.*]] = arith.constant 3 : index
+! CHECK-DAG:       %[[C3_9:.*]] = arith.constant 3 : index
+! CHECK-DAG:       %[[ARRAY_BOX:.*]] = hlfir.designate %[[ARRAY]]#0 (%[[C1]]:%[[C3_0]]:%[[C1_3]], %[[C1]]:%[[C3_1]]:%[[C1_5]]) substr %[[C1_7]], %[[C3_8]]  shape %[[SHAPE]] typeparams %[[C3_9]]
+! CHECK:           %[[EXPR:.*]] = hlfir.minloc %[[ARRAY_BOX]] {fastmath = #arith.fastmath<contract>} : (!fir.box<!fir.array<3x3x!fir.char<1,3>>>) -> !hlfir.expr<2xi32>
+! CHECK-NEXT:      hlfir.assign %[[EXPR]] to %[[RES]]#0 : !hlfir.expr<2xi32>, !fir.ref<!fir.array<2xi32>>
+! CHECK-NEXT:      hlfir.destroy %[[EXPR]]
+! CHECK-NEXT:      return
+! CHECK-NEXT:    }
+
+
+subroutine scalar_dim1(a, d, m, b, s)
+  integer :: a(:), d
+  integer :: s(:)
+  logical :: m(:), b
+  s = MINLOC(a, dim=d, mask=m, kind=2, back=b)
+end subroutine
+! CHECK-LABEL:  func.func @_QPscalar_dim1(
+! CHECK:            %[[ARG0:.*]]: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "a"}, %[[ARG1:.*]]: !fir.ref<i32> {fir.bindc_name = "d"}, %[[ARG2:.*]]: !fir.box<!fir.array<?x!fir.logical<4>>> {fir.bindc_name = "m"}, %[[ARG3:.*]]: !fir.ref<!fir.logical<4>> {fir.bindc_name = "b"}, %[[ARG4:.*]]: !fir.box<!fir.array<?xi32>> {fir.bindc_name = "s"}) {
+! CHECK-NEXT:    %[[V0:.*]]:2 = hlfir.declare %[[ARG0]]
+! CHECK-NEXT:    %[[V1:.*]]:2 = hlfir.declare %[[ARG3]]
+! CHECK-NEXT:    %[[V2:.*]]:2 = hlfir.declare %[[ARG1]]
+! CHECK-NEXT:    %[[V3:.*]]:2 = hlfir.declare %[[ARG2]]
+! CHECK-NEXT:    %[[V4:.*]]:2 = hlfir.declare %[[ARG4]]
+! CHECK-NEXT:    %[[V5:.*]] = fir.load %[[V1]]#0 : !fir.ref<!fir.logical<4>>
+! CHECK-NEXT:    %[[V6:.*]] = fir.load %[[V2]]#0 : !fir.ref<i32>
+! CHECK-NEXT:    %[[V7:.*]] = hlfir.minloc %[[V0]]#0 dim %[[V6]] mask %[[V3]]#0 back %[[V5]] {fastmath = #arith.fastmath<contract>} : (!fir.box<!fir.array<?xi32>>, i32, !fir.box<!fir.array<?x!fir.logical<4>>>, !fir.logical<4>) -> i16
+! CHECK-NEXT:    %[[V8:.*]] = fir.convert %[[V7]] : (i16) -> i32
+! CHECK-NEXT:    hlfir.assign %[[V8]] to %[[V4]]#0 : i32, !fir.box<!fir.array<?xi32>>
+! CHECK-NEXT:    return
diff --git a/flang/test/Lower/HLFIR/transformational.f90 b/flang/test/Lower/HLFIR/transformational.f90
index 22dfb4207125..5f1137277336 100644
--- a/flang/test/Lower/HLFIR/transformational.f90
+++ b/flang/test/Lower/HLFIR/transformational.f90
@@ -7,11 +7,7 @@ subroutine test_transformational_implemented_with_runtime_allocation(x)
   real :: x(10, 10)
   ! MINLOC result is allocated inside the runtime and returned in
   ! a descriptor that was passed by reference to the runtime.
-  ! Lowering does the following:
-  !  - declares the temp created by the runtime as an hlfir variable.
-  !  - "moves" this variable to an hlfir.expr
-  !  - associate the expression to takes_array_arg dummy argument
-  !  - destroys the expression after the call.
+  ! Lowering goes via a hlfir.minloc intrinsic.
 
   ! After bufferization, this will allow the buffer created by the
   ! runtime to be passed to takes_array_arg without creating any
@@ -19,17 +15,11 @@ subroutine test_transformational_implemented_with_runtime_allocation(x)
   call takes_array_arg(minloc(x))
 end subroutine
 ! CHECK-LABEL: func.func @_QPtest_transformational_implemented_with_runtime_allocation(
-! CHECK-SAME:                                                                          %[[VAL_0:.*]]: !fir.ref<!fir.array<10x10xf32>> {fir.bindc_name = "x"}) {
-! CHECK:  %[[VAL_1:.*]] = fir.alloca !fir.box<!fir.heap<!fir.array<?xi32>>>
-! CHECK:  %[[VAL_17:.*]] = fir.convert %[[VAL_1]] : (!fir.ref<!fir.box<!fir.heap<!fir.array<?xi32>>>>) -> !fir.ref<!fir.box<none>>
-! CHECK:  %[[VAL_22:.*]] = fir.call @_FortranAMinlocReal4(%[[VAL_17]], {{.*}}
-! CHECK:  %[[VAL_23:.*]] = fir.load %[[VAL_1]] : !fir.ref<!fir.box<!fir.heap<!fir.array<?xi32>>>>
-! CHECK:  %[[VAL_26:.*]] = fir.box_addr %[[VAL_23]] : (!fir.box<!fir.heap<!fir.array<?xi32>>>) -> !fir.heap<!fir.array<?xi32>>
-! CHECK:  %[[VAL_28:.*]]:2 = hlfir.declare %[[VAL_26]](%{{.*}}) {uniq_name = ".tmp.intrinsic_result"} : (!fir.heap<!fir.array<?xi32>>, !fir.shapeshift<1>) -> (!fir.box<!fir.array<?xi32>>, !fir.heap<!fir.array<?xi32>>)
-! CHECK:  %[[VAL_29:.*]] = arith.constant true
-! CHECK:  %[[VAL_30:.*]] = hlfir.as_expr %[[VAL_28]]#0 move %[[VAL_29]] : (!fir.box<!fir.array<?xi32>>, i1) -> !hlfir.expr<?xi32>
-! CHECK:  %[[VAL_32:.*]]:3 = hlfir.associate %[[VAL_30]](%{{.*}}) {adapt.valuebyref} : (!hlfir.expr<?xi32>, !fir.shape<1>) -> (!fir.box<!fir.array<?xi32>>, !fir.ref<!fir.array<?xi32>>, i1)
-! CHECK:  %[[VAL_33:.*]] = fir.convert %[[VAL_32]]#1 : (!fir.ref<!fir.array<?xi32>>) -> !fir.ref<!fir.array<2xi32>>
-! CHECK:  fir.call @_QPtakes_array_arg(%[[VAL_33]])
-! CHECK:  hlfir.end_associate %[[VAL_32]]#1, %[[VAL_32]]#2 : !fir.ref<!fir.array<?xi32>>, i1
-! CHECK:  hlfir.destroy %[[VAL_30]] : !hlfir.expr<?xi32>
+! CHECK-SAME:                                                                          %[[ARG0:.*]]: !fir.ref<!fir.array<10x10xf32>> {fir.bindc_name = "x"}) {
+! CHECK:  %[[VAL_1:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) {uniq_name = "_QFtest_transformational_implemented_with_runtime_allocationEx"}
+! CHECK:  %[[VAL_2:.*]] = hlfir.minloc %[[VAL_1]]#0
+! CHECK:  %[[VAL_3:.*]] = hlfir.shape_of %[[VAL_2]]
+! CHECK:  %[[VAL_4:.*]]:3 = hlfir.associate %[[VAL_2]](%[[VAL_3]]) {adapt.valuebyref}
+! CHECK:  fir.call @_QPtakes_array_arg(%[[VAL_4]]#1)
+! CHECK:  hlfir.end_associate %[[VAL_4]]#1, %[[VAL_4]]#2 : !fir.ref<!fir.array<2xi32>>, i1
+! CHECK:  hlfir.destroy %[[VAL_2]] : !hlfir.expr<2xi32>
-- 
GitLab


From 97181bf9a05251d48c8016ad61d3e38df90620bb Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp@bytedance.com>
Date: Tue, 12 Dec 2023 20:40:20 +0800
Subject: [PATCH 286/349] [TableGen] Use getSizeInBits (#75157)

We know the type is scalar type.
---
 llvm/utils/TableGen/DAGISelMatcherEmitter.cpp | 38 +++++++++----------
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
index 5f96f11279f2..94799267e896 100644
--- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
@@ -587,7 +587,7 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx,
     return CurrentIdx - StartIdx + 1;
   }
 
- case Matcher::CheckType:
+  case Matcher::CheckType:
     if (cast<CheckTypeMatcher>(N)->getResNo() == 0) {
       MVT::SimpleValueType VT = cast<CheckTypeMatcher>(N)->getType();
       switch (VT) {
@@ -600,24 +600,24 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx,
         return 2;
       }
     }
-    OS << "OPC_CheckTypeRes, " << cast<CheckTypeMatcher>(N)->getResNo()
-       << ", " << getEnumName(cast<CheckTypeMatcher>(N)->getType()) << ",\n";
+    OS << "OPC_CheckTypeRes, " << cast<CheckTypeMatcher>(N)->getResNo() << ", "
+       << getEnumName(cast<CheckTypeMatcher>(N)->getType()) << ",\n";
     return 3;
 
- case Matcher::CheckChildType: {
-   MVT::SimpleValueType VT = cast<CheckChildTypeMatcher>(N)->getType();
-   switch (VT) {
-   case MVT::i32:
-   case MVT::i64:
-     OS << "OPC_CheckChild" << cast<CheckChildTypeMatcher>(N)->getChildNo()
-        << "TypeI" << MVT(VT).getScalarSizeInBits() << ",\n";
-     return 1;
-   default:
-     OS << "OPC_CheckChild" << cast<CheckChildTypeMatcher>(N)->getChildNo()
-        << "Type, " << getEnumName(VT) << ",\n";
-     return 2;
-   }
- }
+  case Matcher::CheckChildType: {
+    MVT::SimpleValueType VT = cast<CheckChildTypeMatcher>(N)->getType();
+    switch (VT) {
+    case MVT::i32:
+    case MVT::i64:
+      OS << "OPC_CheckChild" << cast<CheckChildTypeMatcher>(N)->getChildNo()
+         << "TypeI" << MVT(VT).getSizeInBits() << ",\n";
+      return 1;
+    default:
+      OS << "OPC_CheckChild" << cast<CheckChildTypeMatcher>(N)->getChildNo()
+         << "Type, " << getEnumName(VT) << ",\n";
+      return 2;
+    }
+  }
 
   case Matcher::CheckInteger: {
     OS << "OPC_CheckInteger, ";
@@ -704,7 +704,7 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx,
     case MVT::i32:
     case MVT::i64:
       OpBytes = 1;
-      OS << "OPC_EmitInteger" << MVT(VT).getScalarSizeInBits() << ", ";
+      OS << "OPC_EmitInteger" << MVT(VT).getSizeInBits() << ", ";
       break;
     default:
       OpBytes = 2;
@@ -723,7 +723,7 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx,
     switch (VT) {
     case MVT::i32:
       OpBytes = 1;
-      OS << "OPC_EmitStringInteger" << MVT(VT).getScalarSizeInBits() << ", ";
+      OS << "OPC_EmitStringInteger" << MVT(VT).getSizeInBits() << ", ";
       break;
     default:
       OpBytes = 2;
-- 
GitLab


From 0e9879ed9711ac280c5e1ea47f77a033393d6baa Mon Sep 17 00:00:00 2001
From: Pete Lawrence <plawrence@apple.com>
Date: Tue, 12 Dec 2023 02:50:18 -1000
Subject: [PATCH 287/349] [lldb] Correctly check and report error states in
 StackFrame.cpp (#74414)

This commits fixes a few subtle bugs where the method:
1. Declares a local `Status error` which eclipses the method's parameter
`Status &error`.
- The method then sets the error state to the local `error` and returns
without ever touching the parameter `&error`.
- This effectively traps the error state and its message from ever
reaching the caller.
- I also threw in a null pointer check in case the callee doesn't set
its `Status` parameter but returns `0`/`nullptr`.

2. Declares a local `Status deref_error` (good), passes it to the
`Dereference` method (also good), but then checks the status of the
method's `Status &error` parameter (not good).
- The fix checks `deref_error` instead and also checks for a `nullptr`
return value.
- There's a good opportunity here for a future PR that changes the
`Dereference` method to fold an error state into the `ValueObject`
return value's `m_error` instead of using a parameter.

3. Declares another local `Status error`, which it doesn't pass to a
method (because there isn't a parameter for it), and then checks for an
error condition that never happens.
- The fix just checks the callee's return value, because that's all it
has to go on.
	- This likely comes from a copy/paste from issue 1 above.


rdar://119155810
---
 lldb/source/Target/StackFrame.cpp | 22 ++++++++++------------
 1 file changed, 10 insertions(+), 12 deletions(-)

diff --git a/lldb/source/Target/StackFrame.cpp b/lldb/source/Target/StackFrame.cpp
index f0d78d8aa5fe..50cf01e63cd4 100644
--- a/lldb/source/Target/StackFrame.cpp
+++ b/lldb/source/Target/StackFrame.cpp
@@ -652,7 +652,7 @@ ValueObjectSP StackFrame::GetValueForVariableExpressionPath(
         Status deref_error;
         if (valobj_sp->GetCompilerType().IsReferenceType()) {
           valobj_sp = valobj_sp->GetSyntheticValue()->Dereference(deref_error);
-          if (error.Fail()) {
+          if (!valobj_sp || deref_error.Fail()) {
             error.SetErrorStringWithFormatv(
                 "Failed to dereference reference type: %s", deref_error);
             return ValueObjectSP();
@@ -660,7 +660,7 @@ ValueObjectSP StackFrame::GetValueForVariableExpressionPath(
         }
 
         valobj_sp = valobj_sp->Dereference(deref_error);
-        if (error.Fail()) {
+        if (!valobj_sp || deref_error.Fail()) {
           error.SetErrorStringWithFormatv(
               "Failed to dereference sythetic value: {0}", deref_error);
           return ValueObjectSP();
@@ -795,9 +795,9 @@ ValueObjectSP StackFrame::GetValueForVariableExpressionPath(
           // what we have is *ptr[low]. the most similar C++ syntax is to deref
           // ptr and extract bit low out of it. reading array item low would be
           // done by saying ptr[low], without a deref * sign
-          Status error;
-          ValueObjectSP temp(valobj_sp->Dereference(error));
-          if (error.Fail()) {
+          Status deref_error;
+          ValueObjectSP temp(valobj_sp->Dereference(deref_error));
+          if (!temp || deref_error.Fail()) {
             valobj_sp->GetExpressionPath(var_expr_path_strm);
             error.SetErrorStringWithFormat(
                 "could not dereference \"(%s) %s\"",
@@ -813,9 +813,8 @@ ValueObjectSP StackFrame::GetValueForVariableExpressionPath(
           // arr[0] (an operation that is equivalent to deref-ing arr) and
           // extract bit low out of it. reading array item low would be done by
           // saying arr[low], without a deref * sign
-          Status error;
           ValueObjectSP temp(valobj_sp->GetChildAtIndex(0));
-          if (error.Fail()) {
+          if (!temp) {
             valobj_sp->GetExpressionPath(var_expr_path_strm);
             error.SetErrorStringWithFormat(
                 "could not get item 0 for \"(%s) %s\"",
@@ -994,9 +993,9 @@ ValueObjectSP StackFrame::GetValueForVariableExpressionPath(
         // deref ptr and extract bits low thru high out of it. reading array
         // items low thru high would be done by saying ptr[low-high], without a
         // deref * sign
-        Status error;
-        ValueObjectSP temp(valobj_sp->Dereference(error));
-        if (error.Fail()) {
+        Status deref_error;
+        ValueObjectSP temp(valobj_sp->Dereference(deref_error));
+        if (!temp || deref_error.Fail()) {
           valobj_sp->GetExpressionPath(var_expr_path_strm);
           error.SetErrorStringWithFormat(
               "could not dereference \"(%s) %s\"",
@@ -1011,9 +1010,8 @@ ValueObjectSP StackFrame::GetValueForVariableExpressionPath(
         // get arr[0] (an operation that is equivalent to deref-ing arr) and
         // extract bits low thru high out of it. reading array items low thru
         // high would be done by saying arr[low-high], without a deref * sign
-        Status error;
         ValueObjectSP temp(valobj_sp->GetChildAtIndex(0));
-        if (error.Fail()) {
+        if (!temp) {
           valobj_sp->GetExpressionPath(var_expr_path_strm);
           error.SetErrorStringWithFormat(
               "could not get item 0 for \"(%s) %s\"",
-- 
GitLab


From 1e47a157f84e38b8cb0caeaba84e881e173d242c Mon Sep 17 00:00:00 2001
From: Guillaume Chatelet <gchatelet@google.com>
Date: Tue, 12 Dec 2023 14:00:25 +0100
Subject: [PATCH 288/349] [libc][NFC] Remove last use of BitsType in
 FloatProperties (#75174)

Also start to expose some of the internals to avoid duplication.
---
 libc/src/__support/FPUtil/FPBits.h          |  3 +--
 libc/src/__support/FPUtil/FloatProperties.h | 27 +++++++++++----------
 2 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/libc/src/__support/FPUtil/FPBits.h b/libc/src/__support/FPUtil/FPBits.h
index bd075fe3d728..65c53921181a 100644
--- a/libc/src/__support/FPUtil/FPBits.h
+++ b/libc/src/__support/FPUtil/FPBits.h
@@ -44,8 +44,7 @@ template <typename T> struct FPBits {
   // integer value as a floating point value is used in tests. So, a convenient
   // type is provided for such reinterpretations.
   using FloatProp = FloatProperties<T>;
-  // TODO: Change UintType name to BitsType for consistency.
-  using UIntType = typename FloatProp::BitsType;
+  using UIntType = typename FloatProp::UIntType;
 
   UIntType bits;
 
diff --git a/libc/src/__support/FPUtil/FloatProperties.h b/libc/src/__support/FPUtil/FloatProperties.h
index 04da5c031f88..7f396a649e4f 100644
--- a/libc/src/__support/FPUtil/FloatProperties.h
+++ b/libc/src/__support/FPUtil/FloatProperties.h
@@ -90,8 +90,11 @@ private:
   using UP::EXP_BITS;
   using UP::SIG_BITS;
   using UP::TOTAL_BITS;
+
+public:
   using UIntType = typename UP::UIntType;
 
+private:
   LIBC_INLINE_VAR static constexpr int STORAGE_BITS =
       sizeof(UIntType) * CHAR_BIT;
   static_assert(STORAGE_BITS >= TOTAL_BITS);
@@ -116,14 +119,16 @@ private:
       mask_trailing_ones<UIntType, SIG_BITS>() << SIG_MASK_SHIFT;
   LIBC_INLINE_VAR static constexpr UIntType EXP_MASK =
       mask_trailing_ones<UIntType, EXP_BITS>() << EXP_MASK_SHIFT;
-  // Trailing underscore on SIGN_MASK_ is temporary - it will be removed
-  // once we can replace the public part below with the private one.
-  LIBC_INLINE_VAR static constexpr UIntType SIGN_MASK_ =
+
+public:
+  LIBC_INLINE_VAR static constexpr UIntType SIGN_MASK =
       mask_trailing_ones<UIntType, SIGN_BITS>() << SIGN_MASK_SHIFT;
+
+private:
   LIBC_INLINE_VAR static constexpr UIntType FP_MASK =
       mask_trailing_ones<UIntType, TOTAL_BITS>();
-  static_assert((SIG_MASK & EXP_MASK & SIGN_MASK_) == 0, "masks disjoint");
-  static_assert((SIG_MASK | EXP_MASK | SIGN_MASK_) == FP_MASK, "masks cover");
+  static_assert((SIG_MASK & EXP_MASK & SIGN_MASK) == 0, "masks disjoint");
+  static_assert((SIG_MASK | EXP_MASK | SIGN_MASK) == FP_MASK, "masks cover");
 
   LIBC_INLINE static constexpr UIntType bit_at(int position) {
     return UIntType(1) << position;
@@ -145,25 +150,21 @@ private:
                                                                   : SIG_BITS;
 
 public:
-  // Public facing API to keep the change local to this file.
-  using BitsType = UIntType;
-
   LIBC_INLINE_VAR static constexpr uint32_t BIT_WIDTH = TOTAL_BITS;
   LIBC_INLINE_VAR static constexpr uint32_t MANTISSA_WIDTH = FRACTION_BITS;
   LIBC_INLINE_VAR static constexpr uint32_t MANTISSA_PRECISION =
       MANTISSA_WIDTH + 1;
-  LIBC_INLINE_VAR static constexpr BitsType MANTISSA_MASK =
+  LIBC_INLINE_VAR static constexpr UIntType MANTISSA_MASK =
       mask_trailing_ones<UIntType, MANTISSA_WIDTH>();
   LIBC_INLINE_VAR static constexpr uint32_t EXPONENT_WIDTH = EXP_BITS;
   LIBC_INLINE_VAR static constexpr int32_t EXPONENT_BIAS = EXP_BIAS;
-  LIBC_INLINE_VAR static constexpr BitsType SIGN_MASK = SIGN_MASK_;
-  LIBC_INLINE_VAR static constexpr BitsType EXPONENT_MASK = EXP_MASK;
-  LIBC_INLINE_VAR static constexpr BitsType EXP_MANT_MASK = EXP_MASK | SIG_MASK;
+  LIBC_INLINE_VAR static constexpr UIntType EXPONENT_MASK = EXP_MASK;
+  LIBC_INLINE_VAR static constexpr UIntType EXP_MANT_MASK = EXP_MASK | SIG_MASK;
 
   // If a number x is a NAN, then it is a quiet NAN if:
   //   QuietNaNMask & bits(x) != 0
   // Else, it is a signalling NAN.
-  static constexpr BitsType QUIET_NAN_MASK = QNAN_MASK;
+  static constexpr UIntType QUIET_NAN_MASK = QNAN_MASK;
 };
 
 //-----------------------------------------------------------------------------
-- 
GitLab


From 19546861772f225d2648d7a5f3fea7798a13be70 Mon Sep 17 00:00:00 2001
From: Kerry McLaughlin <kerry.mclaughlin@arm.com>
Date: Tue, 12 Dec 2023 13:15:24 +0000
Subject: [PATCH 289/349] [Clang][SME2] Add multi-vector unpack builtins
 (#75075)

Adds the following SME2 builtins:
 - svunpk (x2 & x4)

See https://github.com/ARM-software/acle/pull/217/files

Patch by David Sherwood <david.sherwood@arm.com>
---
 clang/include/clang/Basic/arm_sve.td          |  11 +
 .../acle_sme2_unpkx2.c                        | 150 ++++++++++++
 .../acle_sme2_unpkx4.c                        | 222 ++++++++++++++++++
 3 files changed, 383 insertions(+)
 create mode 100644 clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx2.c
 create mode 100644 clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx4.c

diff --git a/clang/include/clang/Basic/arm_sve.td b/clang/include/clang/Basic/arm_sve.td
index 42ad7da737b4..aa9b105364a5 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -2262,3 +2262,14 @@ let TargetGuard = "sme2" in {
   def SVQCVTN_U16_U64_X4 : SInst<"svqcvtn_u16[_{d}_x4]", "b4.d", "Ul", MergeNone, "aarch64_sve_uqcvtn_x4", [IsStreaming], []>;
   def SVQCVTN_U16_S64_X4 : SInst<"svqcvtn_u16[_{d}_x4]", "b4.d", "l", MergeNone, "aarch64_sve_sqcvtun_x4", [IsStreaming], []>;
 }
+
+//
+// Multi-vector unpack
+//
+
+let TargetGuard = "sme2" in {
+  def SVSUNPK_X2 : SInst<"svunpk_{d}[_{1}_x2]", "2h",   "sil",    MergeNone, "aarch64_sve_sunpk_x2", [IsStreaming], []>;
+  def SVUUNPK_X2 : SInst<"svunpk_{d}[_{1}_x2]", "2h",   "UsUiUl", MergeNone, "aarch64_sve_uunpk_x2", [IsStreaming], []>;
+  def SVSUNPK_X4 : SInst<"svunpk_{d}[_{3}_x4]", "42.h", "sil",    MergeNone, "aarch64_sve_sunpk_x4", [IsStreaming], []>;
+  def SVUUNPK_X4 : SInst<"svunpk_{d}[_{3}_x4]", "42.h", "UsUiUl", MergeNone, "aarch64_sve_uunpk_x4", [IsStreaming], []>;
+}
diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx2.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx2.c
new file mode 100644
index 000000000000..2f427689323b
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx2.c
@@ -0,0 +1,150 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
+#include <arm_sme_draft_spec_subject_to_change.h>
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED) A1
+#else
+#define SVE_ACLE_FUNC(A1,A2) A1##A2
+#endif
+
+// CHECK-LABEL: @test_svunpk_s16_x2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sunpk.x2.nxv8i16(<vscale x 16 x i8> [[ZN:%.*]])
+// CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 0
+// CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> poison, <vscale x 8 x i16> [[TMP1]], i64 0)
+// CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 1
+// CHECK-NEXT:    [[TMP4:%.*]] = tail call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> [[TMP2]], <vscale x 8 x i16> [[TMP3]], i64 8)
+// CHECK-NEXT:    ret <vscale x 16 x i16> [[TMP4]]
+//
+// CPP-CHECK-LABEL: @_Z18test_svunpk_s16_x2u10__SVInt8_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sunpk.x2.nxv8i16(<vscale x 16 x i8> [[ZN:%.*]])
+// CPP-CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 0
+// CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> poison, <vscale x 8 x i16> [[TMP1]], i64 0)
+// CPP-CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 1
+// CPP-CHECK-NEXT:    [[TMP4:%.*]] = tail call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> [[TMP2]], <vscale x 8 x i16> [[TMP3]], i64 8)
+// CPP-CHECK-NEXT:    ret <vscale x 16 x i16> [[TMP4]]
+//
+svint16x2_t test_svunpk_s16_x2(svint8_t zn) __arm_streaming {
+  return SVE_ACLE_FUNC(svunpk_s16,_s8_x2)(zn);
+}
+
+// CHECK-LABEL: @test_svunpk_u16_x2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uunpk.x2.nxv8i16(<vscale x 16 x i8> [[ZN:%.*]])
+// CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 0
+// CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> poison, <vscale x 8 x i16> [[TMP1]], i64 0)
+// CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 1
+// CHECK-NEXT:    [[TMP4:%.*]] = tail call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> [[TMP2]], <vscale x 8 x i16> [[TMP3]], i64 8)
+// CHECK-NEXT:    ret <vscale x 16 x i16> [[TMP4]]
+//
+// CPP-CHECK-LABEL: @_Z18test_svunpk_u16_x2u11__SVUint8_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uunpk.x2.nxv8i16(<vscale x 16 x i8> [[ZN:%.*]])
+// CPP-CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 0
+// CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> poison, <vscale x 8 x i16> [[TMP1]], i64 0)
+// CPP-CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 1
+// CPP-CHECK-NEXT:    [[TMP4:%.*]] = tail call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> [[TMP2]], <vscale x 8 x i16> [[TMP3]], i64 8)
+// CPP-CHECK-NEXT:    ret <vscale x 16 x i16> [[TMP4]]
+//
+svuint16x2_t test_svunpk_u16_x2(svuint8_t zn) __arm_streaming {
+  return SVE_ACLE_FUNC(svunpk_u16,_u8_x2)(zn);
+}
+
+// CHECK-LABEL: @test_svunpk_s32_x2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sunpk.x2.nxv4i32(<vscale x 8 x i16> [[ZN:%.*]])
+// CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 0
+// CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> poison, <vscale x 4 x i32> [[TMP1]], i64 0)
+// CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 1
+// CHECK-NEXT:    [[TMP4:%.*]] = tail call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> [[TMP2]], <vscale x 4 x i32> [[TMP3]], i64 4)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP4]]
+//
+// CPP-CHECK-LABEL: @_Z18test_svunpk_s32_x2u11__SVInt16_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sunpk.x2.nxv4i32(<vscale x 8 x i16> [[ZN:%.*]])
+// CPP-CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 0
+// CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> poison, <vscale x 4 x i32> [[TMP1]], i64 0)
+// CPP-CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 1
+// CPP-CHECK-NEXT:    [[TMP4:%.*]] = tail call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> [[TMP2]], <vscale x 4 x i32> [[TMP3]], i64 4)
+// CPP-CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP4]]
+//
+svint32x2_t test_svunpk_s32_x2(svint16_t zn) __arm_streaming {
+  return SVE_ACLE_FUNC(svunpk_s32,_s16_x2)(zn);
+}
+
+// CHECK-LABEL: @test_svunpk_u32_x2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.uunpk.x2.nxv4i32(<vscale x 8 x i16> [[ZN:%.*]])
+// CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 0
+// CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> poison, <vscale x 4 x i32> [[TMP1]], i64 0)
+// CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 1
+// CHECK-NEXT:    [[TMP4:%.*]] = tail call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> [[TMP2]], <vscale x 4 x i32> [[TMP3]], i64 4)
+// CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP4]]
+//
+// CPP-CHECK-LABEL: @_Z18test_svunpk_u32_x2u12__SVUint16_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.uunpk.x2.nxv4i32(<vscale x 8 x i16> [[ZN:%.*]])
+// CPP-CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 0
+// CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> poison, <vscale x 4 x i32> [[TMP1]], i64 0)
+// CPP-CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 1
+// CPP-CHECK-NEXT:    [[TMP4:%.*]] = tail call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> [[TMP2]], <vscale x 4 x i32> [[TMP3]], i64 4)
+// CPP-CHECK-NEXT:    ret <vscale x 8 x i32> [[TMP4]]
+//
+svuint32x2_t test_svunpk_u32_x2(svuint16_t zn) __arm_streaming {
+  return SVE_ACLE_FUNC(svunpk_u32,_u16_x2)(zn);
+}
+
+// CHECK-LABEL: @test_svunpk_s64_x2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sunpk.x2.nxv2i64(<vscale x 4 x i32> [[ZN:%.*]])
+// CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 0
+// CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> poison, <vscale x 2 x i64> [[TMP1]], i64 0)
+// CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 1
+// CHECK-NEXT:    [[TMP4:%.*]] = tail call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> [[TMP2]], <vscale x 2 x i64> [[TMP3]], i64 2)
+// CHECK-NEXT:    ret <vscale x 4 x i64> [[TMP4]]
+//
+// CPP-CHECK-LABEL: @_Z18test_svunpk_s64_x2u11__SVInt32_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sunpk.x2.nxv2i64(<vscale x 4 x i32> [[ZN:%.*]])
+// CPP-CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 0
+// CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> poison, <vscale x 2 x i64> [[TMP1]], i64 0)
+// CPP-CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 1
+// CPP-CHECK-NEXT:    [[TMP4:%.*]] = tail call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> [[TMP2]], <vscale x 2 x i64> [[TMP3]], i64 2)
+// CPP-CHECK-NEXT:    ret <vscale x 4 x i64> [[TMP4]]
+//
+svint64x2_t test_svunpk_s64_x2(svint32_t zn) __arm_streaming {
+  return SVE_ACLE_FUNC(svunpk_s64,_s32_x2)(zn);
+}
+
+// CHECK-LABEL: @test_svunpk_u64_x2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.uunpk.x2.nxv2i64(<vscale x 4 x i32> [[ZN:%.*]])
+// CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 0
+// CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> poison, <vscale x 2 x i64> [[TMP1]], i64 0)
+// CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 1
+// CHECK-NEXT:    [[TMP4:%.*]] = tail call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> [[TMP2]], <vscale x 2 x i64> [[TMP3]], i64 2)
+// CHECK-NEXT:    ret <vscale x 4 x i64> [[TMP4]]
+//
+// CPP-CHECK-LABEL: @_Z18test_svunpk_u64_x2u12__SVUint32_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.uunpk.x2.nxv2i64(<vscale x 4 x i32> [[ZN:%.*]])
+// CPP-CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 0
+// CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> poison, <vscale x 2 x i64> [[TMP1]], i64 0)
+// CPP-CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 1
+// CPP-CHECK-NEXT:    [[TMP4:%.*]] = tail call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> [[TMP2]], <vscale x 2 x i64> [[TMP3]], i64 2)
+// CPP-CHECK-NEXT:    ret <vscale x 4 x i64> [[TMP4]]
+//
+svuint64x2_t test_svunpk_u64_x2(svuint32_t zn) __arm_streaming {
+  return SVE_ACLE_FUNC(svunpk_u64,_u32_x2)(zn);
+}
diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx4.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx4.c
new file mode 100644
index 000000000000..cdcc62d5405e
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx4.c
@@ -0,0 +1,222 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
+#include <arm_sme_draft_spec_subject_to_change.h>
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED) A1
+#else
+#define SVE_ACLE_FUNC(A1,A2) A1##A2
+#endif
+
+// CHECK-LABEL: @test_svunpk_s16_x4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[ZN:%.*]], i64 0)
+// CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[ZN]], i64 16)
+// CHECK-NEXT:    [[TMP2:%.*]] = tail call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sunpk.x4.nxv8i16(<vscale x 16 x i8> [[TMP0]], <vscale x 16 x i8> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP2]], 0
+// CHECK-NEXT:    [[TMP4:%.*]] = tail call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> poison, <vscale x 8 x i16> [[TMP3]], i64 0)
+// CHECK-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP2]], 1
+// CHECK-NEXT:    [[TMP6:%.*]] = tail call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> [[TMP4]], <vscale x 8 x i16> [[TMP5]], i64 8)
+// CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP2]], 2
+// CHECK-NEXT:    [[TMP8:%.*]] = tail call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> [[TMP6]], <vscale x 8 x i16> [[TMP7]], i64 16)
+// CHECK-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP2]], 3
+// CHECK-NEXT:    [[TMP10:%.*]] = tail call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> [[TMP8]], <vscale x 8 x i16> [[TMP9]], i64 24)
+// CHECK-NEXT:    ret <vscale x 32 x i16> [[TMP10]]
+//
+// CPP-CHECK-LABEL: @_Z18test_svunpk_s16_x410svint8x2_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[ZN:%.*]], i64 0)
+// CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[ZN]], i64 16)
+// CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sunpk.x4.nxv8i16(<vscale x 16 x i8> [[TMP0]], <vscale x 16 x i8> [[TMP1]])
+// CPP-CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP2]], 0
+// CPP-CHECK-NEXT:    [[TMP4:%.*]] = tail call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> poison, <vscale x 8 x i16> [[TMP3]], i64 0)
+// CPP-CHECK-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP2]], 1
+// CPP-CHECK-NEXT:    [[TMP6:%.*]] = tail call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> [[TMP4]], <vscale x 8 x i16> [[TMP5]], i64 8)
+// CPP-CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP2]], 2
+// CPP-CHECK-NEXT:    [[TMP8:%.*]] = tail call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> [[TMP6]], <vscale x 8 x i16> [[TMP7]], i64 16)
+// CPP-CHECK-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP2]], 3
+// CPP-CHECK-NEXT:    [[TMP10:%.*]] = tail call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> [[TMP8]], <vscale x 8 x i16> [[TMP9]], i64 24)
+// CPP-CHECK-NEXT:    ret <vscale x 32 x i16> [[TMP10]]
+//
+svint16x4_t test_svunpk_s16_x4(svint8x2_t zn) __arm_streaming {
+  return SVE_ACLE_FUNC(svunpk_s16,_s8_x4)(zn);
+}
+
+// CHECK-LABEL: @test_svunpk_u16_x4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[ZN:%.*]], i64 0)
+// CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[ZN]], i64 16)
+// CHECK-NEXT:    [[TMP2:%.*]] = tail call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uunpk.x4.nxv8i16(<vscale x 16 x i8> [[TMP0]], <vscale x 16 x i8> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP2]], 0
+// CHECK-NEXT:    [[TMP4:%.*]] = tail call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> poison, <vscale x 8 x i16> [[TMP3]], i64 0)
+// CHECK-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP2]], 1
+// CHECK-NEXT:    [[TMP6:%.*]] = tail call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> [[TMP4]], <vscale x 8 x i16> [[TMP5]], i64 8)
+// CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP2]], 2
+// CHECK-NEXT:    [[TMP8:%.*]] = tail call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> [[TMP6]], <vscale x 8 x i16> [[TMP7]], i64 16)
+// CHECK-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP2]], 3
+// CHECK-NEXT:    [[TMP10:%.*]] = tail call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> [[TMP8]], <vscale x 8 x i16> [[TMP9]], i64 24)
+// CHECK-NEXT:    ret <vscale x 32 x i16> [[TMP10]]
+//
+// CPP-CHECK-LABEL: @_Z18test_svunpk_u16_x411svuint8x2_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[ZN:%.*]], i64 0)
+// CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[ZN]], i64 16)
+// CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uunpk.x4.nxv8i16(<vscale x 16 x i8> [[TMP0]], <vscale x 16 x i8> [[TMP1]])
+// CPP-CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP2]], 0
+// CPP-CHECK-NEXT:    [[TMP4:%.*]] = tail call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> poison, <vscale x 8 x i16> [[TMP3]], i64 0)
+// CPP-CHECK-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP2]], 1
+// CPP-CHECK-NEXT:    [[TMP6:%.*]] = tail call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> [[TMP4]], <vscale x 8 x i16> [[TMP5]], i64 8)
+// CPP-CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP2]], 2
+// CPP-CHECK-NEXT:    [[TMP8:%.*]] = tail call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> [[TMP6]], <vscale x 8 x i16> [[TMP7]], i64 16)
+// CPP-CHECK-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP2]], 3
+// CPP-CHECK-NEXT:    [[TMP10:%.*]] = tail call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> [[TMP8]], <vscale x 8 x i16> [[TMP9]], i64 24)
+// CPP-CHECK-NEXT:    ret <vscale x 32 x i16> [[TMP10]]
+//
+svuint16x4_t test_svunpk_u16_x4(svuint8x2_t zn) __arm_streaming {
+  return SVE_ACLE_FUNC(svunpk_u16,_u8_x4)(zn);
+}
+
+// CHECK-LABEL: @test_svunpk_s32_x4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[ZN:%.*]], i64 0)
+// CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[ZN]], i64 8)
+// CHECK-NEXT:    [[TMP2:%.*]] = tail call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sunpk.x4.nxv4i32(<vscale x 8 x i16> [[TMP0]], <vscale x 8 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP2]], 0
+// CHECK-NEXT:    [[TMP4:%.*]] = tail call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> poison, <vscale x 4 x i32> [[TMP3]], i64 0)
+// CHECK-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP2]], 1
+// CHECK-NEXT:    [[TMP6:%.*]] = tail call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> [[TMP4]], <vscale x 4 x i32> [[TMP5]], i64 4)
+// CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP2]], 2
+// CHECK-NEXT:    [[TMP8:%.*]] = tail call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> [[TMP6]], <vscale x 4 x i32> [[TMP7]], i64 8)
+// CHECK-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP2]], 3
+// CHECK-NEXT:    [[TMP10:%.*]] = tail call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> [[TMP8]], <vscale x 4 x i32> [[TMP9]], i64 12)
+// CHECK-NEXT:    ret <vscale x 16 x i32> [[TMP10]]
+//
+// CPP-CHECK-LABEL: @_Z18test_svunpk_s32_x411svint16x2_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[ZN:%.*]], i64 0)
+// CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[ZN]], i64 8)
+// CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sunpk.x4.nxv4i32(<vscale x 8 x i16> [[TMP0]], <vscale x 8 x i16> [[TMP1]])
+// CPP-CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP2]], 0
+// CPP-CHECK-NEXT:    [[TMP4:%.*]] = tail call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> poison, <vscale x 4 x i32> [[TMP3]], i64 0)
+// CPP-CHECK-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP2]], 1
+// CPP-CHECK-NEXT:    [[TMP6:%.*]] = tail call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> [[TMP4]], <vscale x 4 x i32> [[TMP5]], i64 4)
+// CPP-CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP2]], 2
+// CPP-CHECK-NEXT:    [[TMP8:%.*]] = tail call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> [[TMP6]], <vscale x 4 x i32> [[TMP7]], i64 8)
+// CPP-CHECK-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP2]], 3
+// CPP-CHECK-NEXT:    [[TMP10:%.*]] = tail call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> [[TMP8]], <vscale x 4 x i32> [[TMP9]], i64 12)
+// CPP-CHECK-NEXT:    ret <vscale x 16 x i32> [[TMP10]]
+//
+svint32x4_t test_svunpk_s32_x4(svint16x2_t zn) __arm_streaming {
+  return SVE_ACLE_FUNC(svunpk_s32,_s16_x4)(zn);
+}
+
+// CHECK-LABEL: @test_svunpk_u32_x4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[ZN:%.*]], i64 0)
+// CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[ZN]], i64 8)
+// CHECK-NEXT:    [[TMP2:%.*]] = tail call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.uunpk.x4.nxv4i32(<vscale x 8 x i16> [[TMP0]], <vscale x 8 x i16> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP2]], 0
+// CHECK-NEXT:    [[TMP4:%.*]] = tail call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> poison, <vscale x 4 x i32> [[TMP3]], i64 0)
+// CHECK-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP2]], 1
+// CHECK-NEXT:    [[TMP6:%.*]] = tail call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> [[TMP4]], <vscale x 4 x i32> [[TMP5]], i64 4)
+// CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP2]], 2
+// CHECK-NEXT:    [[TMP8:%.*]] = tail call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> [[TMP6]], <vscale x 4 x i32> [[TMP7]], i64 8)
+// CHECK-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP2]], 3
+// CHECK-NEXT:    [[TMP10:%.*]] = tail call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> [[TMP8]], <vscale x 4 x i32> [[TMP9]], i64 12)
+// CHECK-NEXT:    ret <vscale x 16 x i32> [[TMP10]]
+//
+// CPP-CHECK-LABEL: @_Z18test_svunpk_u32_x412svuint16x2_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[ZN:%.*]], i64 0)
+// CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[ZN]], i64 8)
+// CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.uunpk.x4.nxv4i32(<vscale x 8 x i16> [[TMP0]], <vscale x 8 x i16> [[TMP1]])
+// CPP-CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP2]], 0
+// CPP-CHECK-NEXT:    [[TMP4:%.*]] = tail call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> poison, <vscale x 4 x i32> [[TMP3]], i64 0)
+// CPP-CHECK-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP2]], 1
+// CPP-CHECK-NEXT:    [[TMP6:%.*]] = tail call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> [[TMP4]], <vscale x 4 x i32> [[TMP5]], i64 4)
+// CPP-CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP2]], 2
+// CPP-CHECK-NEXT:    [[TMP8:%.*]] = tail call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> [[TMP6]], <vscale x 4 x i32> [[TMP7]], i64 8)
+// CPP-CHECK-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP2]], 3
+// CPP-CHECK-NEXT:    [[TMP10:%.*]] = tail call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> [[TMP8]], <vscale x 4 x i32> [[TMP9]], i64 12)
+// CPP-CHECK-NEXT:    ret <vscale x 16 x i32> [[TMP10]]
+//
+svuint32x4_t test_svunpk_u32_x4(svuint16x2_t zn) __arm_streaming {
+  return SVE_ACLE_FUNC(svunpk_u32,_u16_x4)(zn);
+}
+
+// CHECK-LABEL: @test_svunpk_s64_x4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[ZN:%.*]], i64 0)
+// CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[ZN]], i64 4)
+// CHECK-NEXT:    [[TMP2:%.*]] = tail call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sunpk.x4.nxv2i64(<vscale x 4 x i32> [[TMP0]], <vscale x 4 x i32> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP2]], 0
+// CHECK-NEXT:    [[TMP4:%.*]] = tail call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> poison, <vscale x 2 x i64> [[TMP3]], i64 0)
+// CHECK-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP2]], 1
+// CHECK-NEXT:    [[TMP6:%.*]] = tail call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> [[TMP4]], <vscale x 2 x i64> [[TMP5]], i64 2)
+// CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP2]], 2
+// CHECK-NEXT:    [[TMP8:%.*]] = tail call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> [[TMP6]], <vscale x 2 x i64> [[TMP7]], i64 4)
+// CHECK-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP2]], 3
+// CHECK-NEXT:    [[TMP10:%.*]] = tail call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> [[TMP8]], <vscale x 2 x i64> [[TMP9]], i64 6)
+// CHECK-NEXT:    ret <vscale x 8 x i64> [[TMP10]]
+//
+// CPP-CHECK-LABEL: @_Z18test_svunpk_s64_x411svint32x2_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[ZN:%.*]], i64 0)
+// CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[ZN]], i64 4)
+// CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sunpk.x4.nxv2i64(<vscale x 4 x i32> [[TMP0]], <vscale x 4 x i32> [[TMP1]])
+// CPP-CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP2]], 0
+// CPP-CHECK-NEXT:    [[TMP4:%.*]] = tail call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> poison, <vscale x 2 x i64> [[TMP3]], i64 0)
+// CPP-CHECK-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP2]], 1
+// CPP-CHECK-NEXT:    [[TMP6:%.*]] = tail call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> [[TMP4]], <vscale x 2 x i64> [[TMP5]], i64 2)
+// CPP-CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP2]], 2
+// CPP-CHECK-NEXT:    [[TMP8:%.*]] = tail call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> [[TMP6]], <vscale x 2 x i64> [[TMP7]], i64 4)
+// CPP-CHECK-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP2]], 3
+// CPP-CHECK-NEXT:    [[TMP10:%.*]] = tail call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> [[TMP8]], <vscale x 2 x i64> [[TMP9]], i64 6)
+// CPP-CHECK-NEXT:    ret <vscale x 8 x i64> [[TMP10]]
+//
+svint64x4_t test_svunpk_s64_x4(svint32x2_t zn) __arm_streaming {
+  return SVE_ACLE_FUNC(svunpk_s64,_s32_x4)(zn);
+}
+
+// CHECK-LABEL: @test_svunpk_u64_x4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[ZN:%.*]], i64 0)
+// CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[ZN]], i64 4)
+// CHECK-NEXT:    [[TMP2:%.*]] = tail call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.uunpk.x4.nxv2i64(<vscale x 4 x i32> [[TMP0]], <vscale x 4 x i32> [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP2]], 0
+// CHECK-NEXT:    [[TMP4:%.*]] = tail call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> poison, <vscale x 2 x i64> [[TMP3]], i64 0)
+// CHECK-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP2]], 1
+// CHECK-NEXT:    [[TMP6:%.*]] = tail call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> [[TMP4]], <vscale x 2 x i64> [[TMP5]], i64 2)
+// CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP2]], 2
+// CHECK-NEXT:    [[TMP8:%.*]] = tail call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> [[TMP6]], <vscale x 2 x i64> [[TMP7]], i64 4)
+// CHECK-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP2]], 3
+// CHECK-NEXT:    [[TMP10:%.*]] = tail call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> [[TMP8]], <vscale x 2 x i64> [[TMP9]], i64 6)
+// CHECK-NEXT:    ret <vscale x 8 x i64> [[TMP10]]
+//
+// CPP-CHECK-LABEL: @_Z18test_svunpk_u64_x412svuint32x2_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[ZN:%.*]], i64 0)
+// CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[ZN]], i64 4)
+// CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.uunpk.x4.nxv2i64(<vscale x 4 x i32> [[TMP0]], <vscale x 4 x i32> [[TMP1]])
+// CPP-CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP2]], 0
+// CPP-CHECK-NEXT:    [[TMP4:%.*]] = tail call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> poison, <vscale x 2 x i64> [[TMP3]], i64 0)
+// CPP-CHECK-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP2]], 1
+// CPP-CHECK-NEXT:    [[TMP6:%.*]] = tail call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> [[TMP4]], <vscale x 2 x i64> [[TMP5]], i64 2)
+// CPP-CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP2]], 2
+// CPP-CHECK-NEXT:    [[TMP8:%.*]] = tail call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> [[TMP6]], <vscale x 2 x i64> [[TMP7]], i64 4)
+// CPP-CHECK-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP2]], 3
+// CPP-CHECK-NEXT:    [[TMP10:%.*]] = tail call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> [[TMP8]], <vscale x 2 x i64> [[TMP9]], i64 6)
+// CPP-CHECK-NEXT:    ret <vscale x 8 x i64> [[TMP10]]
+//
+svuint64x4_t test_svunpk_u64_x4(svuint32x2_t zn) __arm_streaming {
+  return SVE_ACLE_FUNC(svunpk_u64,_u32_x4)(zn);
+}
-- 
GitLab


From ed4194bb8dbca5222628c2cddbc032fff57193b5 Mon Sep 17 00:00:00 2001
From: James Y Knight <jyknight@google.com>
Date: Tue, 12 Dec 2023 08:16:55 -0500
Subject: [PATCH 290/349] [X86] Set MaxAtomicSizeInBitsSupported. (#75112)

This will result in larger atomic operations getting expanded to
`__atomic_*` libcalls via AtomicExpandPass, which matches what Clang
already does in the frontend.
---
 llvm/lib/Target/X86/X86ISelLowering.cpp       |  10 +-
 llvm/test/CodeGen/X86/atomic-idempotent.ll    | 347 ++++++++++--------
 llvm/test/CodeGen/X86/atomic-nocx16.ll        |  54 ++-
 .../test/CodeGen/X86/atomic-ops-ancient-64.ll |  15 +-
 llvm/test/CodeGen/X86/atomic-oversize.ll      |  11 +
 llvm/test/CodeGen/X86/atomic-xor.ll           |  57 ++-
 6 files changed, 299 insertions(+), 195 deletions(-)
 create mode 100644 llvm/test/CodeGen/X86/atomic-oversize.ll

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 66cb1a77901c..e779a3d3dab6 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -142,11 +142,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
     setLibcallName(RTLIB::POWI_F64, nullptr);
   }
 
-  // If we don't have cmpxchg8b(meaing this is a 386/486), limit atomic size to
-  // 32 bits so the AtomicExpandPass will expand it so we don't need cmpxchg8b.
-  // FIXME: Should we be limiting the atomic size on other configs? Default is
-  // 1024.
-  if (!Subtarget.canUseCMPXCHG8B())
+  if (Subtarget.canUseCMPXCHG16B())
+    setMaxAtomicSizeInBitsSupported(128);
+  else if (Subtarget.canUseCMPXCHG8B())
+    setMaxAtomicSizeInBitsSupported(64);
+  else
     setMaxAtomicSizeInBitsSupported(32);
 
   setMaxDivRemBitWidthSupported(Subtarget.is64Bit() ? 128 : 64);
diff --git a/llvm/test/CodeGen/X86/atomic-idempotent.ll b/llvm/test/CodeGen/X86/atomic-idempotent.ll
index 3a9648bd1fbb..d5c46485068a 100644
--- a/llvm/test/CodeGen/X86/atomic-idempotent.ll
+++ b/llvm/test/CodeGen/X86/atomic-idempotent.ll
@@ -170,117 +170,130 @@ define i128 @or128(ptr %p) {
 ; X64-NEXT:    .cfi_def_cfa_offset 16
 ; X64-NEXT:    xorl %esi, %esi
 ; X64-NEXT:    xorl %edx, %edx
-; X64-NEXT:    callq __sync_fetch_and_or_16@PLT
+; X64-NEXT:    xorl %ecx, %ecx
+; X64-NEXT:    callq __atomic_fetch_or_16@PLT
 ; X64-NEXT:    popq %rcx
 ; X64-NEXT:    .cfi_def_cfa_offset 8
 ; X64-NEXT:    retq
 ;
-; X86-SSE2-LABEL: or128:
-; X86-SSE2:       # %bb.0:
-; X86-SSE2-NEXT:    pushl %ebp
-; X86-SSE2-NEXT:    .cfi_def_cfa_offset 8
-; X86-SSE2-NEXT:    .cfi_offset %ebp, -8
-; X86-SSE2-NEXT:    movl %esp, %ebp
-; X86-SSE2-NEXT:    .cfi_def_cfa_register %ebp
-; X86-SSE2-NEXT:    pushl %esi
-; X86-SSE2-NEXT:    andl $-16, %esp
-; X86-SSE2-NEXT:    subl $32, %esp
-; X86-SSE2-NEXT:    .cfi_offset %esi, -12
-; X86-SSE2-NEXT:    movl 8(%ebp), %esi
-; X86-SSE2-NEXT:    movl %esp, %eax
-; X86-SSE2-NEXT:    pushl $0
-; X86-SSE2-NEXT:    pushl $0
-; X86-SSE2-NEXT:    pushl $0
-; X86-SSE2-NEXT:    pushl $0
-; X86-SSE2-NEXT:    pushl 12(%ebp)
-; X86-SSE2-NEXT:    pushl %eax
-; X86-SSE2-NEXT:    calll __sync_fetch_and_or_16
-; X86-SSE2-NEXT:    addl $20, %esp
-; X86-SSE2-NEXT:    movaps (%esp), %xmm0
-; X86-SSE2-NEXT:    movaps %xmm0, (%esi)
-; X86-SSE2-NEXT:    movl %esi, %eax
-; X86-SSE2-NEXT:    leal -4(%ebp), %esp
-; X86-SSE2-NEXT:    popl %esi
-; X86-SSE2-NEXT:    popl %ebp
-; X86-SSE2-NEXT:    .cfi_def_cfa %esp, 4
-; X86-SSE2-NEXT:    retl $4
-;
-; X86-SLM-LABEL: or128:
-; X86-SLM:       # %bb.0:
-; X86-SLM-NEXT:    pushl %ebp
-; X86-SLM-NEXT:    .cfi_def_cfa_offset 8
-; X86-SLM-NEXT:    .cfi_offset %ebp, -8
-; X86-SLM-NEXT:    movl %esp, %ebp
-; X86-SLM-NEXT:    .cfi_def_cfa_register %ebp
-; X86-SLM-NEXT:    pushl %edi
-; X86-SLM-NEXT:    pushl %esi
-; X86-SLM-NEXT:    andl $-16, %esp
-; X86-SLM-NEXT:    subl $16, %esp
-; X86-SLM-NEXT:    .cfi_offset %esi, -16
-; X86-SLM-NEXT:    .cfi_offset %edi, -12
-; X86-SLM-NEXT:    movl 8(%ebp), %esi
-; X86-SLM-NEXT:    movl 12(%ebp), %eax
-; X86-SLM-NEXT:    movl %esp, %ecx
-; X86-SLM-NEXT:    pushl $0
-; X86-SLM-NEXT:    pushl $0
-; X86-SLM-NEXT:    pushl $0
-; X86-SLM-NEXT:    pushl $0
-; X86-SLM-NEXT:    pushl %eax
-; X86-SLM-NEXT:    pushl %ecx
-; X86-SLM-NEXT:    calll __sync_fetch_and_or_16
-; X86-SLM-NEXT:    addl $20, %esp
-; X86-SLM-NEXT:    movl (%esp), %eax
-; X86-SLM-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X86-SLM-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; X86-SLM-NEXT:    movl {{[0-9]+}}(%esp), %edi
-; X86-SLM-NEXT:    movl %edi, 8(%esi)
-; X86-SLM-NEXT:    movl %edx, 12(%esi)
-; X86-SLM-NEXT:    movl %eax, (%esi)
-; X86-SLM-NEXT:    movl %ecx, 4(%esi)
-; X86-SLM-NEXT:    movl %esi, %eax
-; X86-SLM-NEXT:    leal -8(%ebp), %esp
-; X86-SLM-NEXT:    popl %esi
-; X86-SLM-NEXT:    popl %edi
-; X86-SLM-NEXT:    popl %ebp
-; X86-SLM-NEXT:    .cfi_def_cfa %esp, 4
-; X86-SLM-NEXT:    retl $4
+; X86-GENERIC-LABEL: or128:
+; X86-GENERIC:       # %bb.0:
+; X86-GENERIC-NEXT:    pushl %ebp
+; X86-GENERIC-NEXT:    .cfi_def_cfa_offset 8
+; X86-GENERIC-NEXT:    .cfi_offset %ebp, -8
+; X86-GENERIC-NEXT:    movl %esp, %ebp
+; X86-GENERIC-NEXT:    .cfi_def_cfa_register %ebp
+; X86-GENERIC-NEXT:    pushl %ebx
+; X86-GENERIC-NEXT:    pushl %edi
+; X86-GENERIC-NEXT:    pushl %esi
+; X86-GENERIC-NEXT:    andl $-16, %esp
+; X86-GENERIC-NEXT:    subl $48, %esp
+; X86-GENERIC-NEXT:    .cfi_offset %esi, -20
+; X86-GENERIC-NEXT:    .cfi_offset %edi, -16
+; X86-GENERIC-NEXT:    .cfi_offset %ebx, -12
+; X86-GENERIC-NEXT:    movl 12(%ebp), %edi
+; X86-GENERIC-NEXT:    movl 12(%edi), %ecx
+; X86-GENERIC-NEXT:    movl 8(%edi), %edx
+; X86-GENERIC-NEXT:    movl (%edi), %ebx
+; X86-GENERIC-NEXT:    movl 4(%edi), %esi
+; X86-GENERIC-NEXT:    .p2align 4, 0x90
+; X86-GENERIC-NEXT:  .LBB4_1: # %atomicrmw.start
+; X86-GENERIC-NEXT:    # =>This Inner Loop Header: Depth=1
+; X86-GENERIC-NEXT:    movl %ebx, (%esp)
+; X86-GENERIC-NEXT:    movl %esi, {{[0-9]+}}(%esp)
+; X86-GENERIC-NEXT:    movl %edx, {{[0-9]+}}(%esp)
+; X86-GENERIC-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
+; X86-GENERIC-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
+; X86-GENERIC-NEXT:    movl %edx, {{[0-9]+}}(%esp)
+; X86-GENERIC-NEXT:    movl %esi, {{[0-9]+}}(%esp)
+; X86-GENERIC-NEXT:    movl %ebx, {{[0-9]+}}(%esp)
+; X86-GENERIC-NEXT:    pushl $0
+; X86-GENERIC-NEXT:    pushl $0
+; X86-GENERIC-NEXT:    leal {{[0-9]+}}(%esp), %eax
+; X86-GENERIC-NEXT:    pushl %eax
+; X86-GENERIC-NEXT:    leal {{[0-9]+}}(%esp), %eax
+; X86-GENERIC-NEXT:    pushl %eax
+; X86-GENERIC-NEXT:    pushl %edi
+; X86-GENERIC-NEXT:    pushl $16
+; X86-GENERIC-NEXT:    calll __atomic_compare_exchange@PLT
+; X86-GENERIC-NEXT:    addl $24, %esp
+; X86-GENERIC-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-GENERIC-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; X86-GENERIC-NEXT:    movl (%esp), %ebx
+; X86-GENERIC-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; X86-GENERIC-NEXT:    testb %al, %al
+; X86-GENERIC-NEXT:    je .LBB4_1
+; X86-GENERIC-NEXT:  # %bb.2: # %atomicrmw.end
+; X86-GENERIC-NEXT:    movl 8(%ebp), %eax
+; X86-GENERIC-NEXT:    movl %ebx, (%eax)
+; X86-GENERIC-NEXT:    movl %esi, 4(%eax)
+; X86-GENERIC-NEXT:    movl %edx, 8(%eax)
+; X86-GENERIC-NEXT:    movl %ecx, 12(%eax)
+; X86-GENERIC-NEXT:    leal -12(%ebp), %esp
+; X86-GENERIC-NEXT:    popl %esi
+; X86-GENERIC-NEXT:    popl %edi
+; X86-GENERIC-NEXT:    popl %ebx
+; X86-GENERIC-NEXT:    popl %ebp
+; X86-GENERIC-NEXT:    .cfi_def_cfa %esp, 4
+; X86-GENERIC-NEXT:    retl $4
 ;
 ; X86-ATOM-LABEL: or128:
 ; X86-ATOM:       # %bb.0:
 ; X86-ATOM-NEXT:    pushl %ebp
 ; X86-ATOM-NEXT:    .cfi_def_cfa_offset 8
 ; X86-ATOM-NEXT:    .cfi_offset %ebp, -8
-; X86-ATOM-NEXT:    leal (%esp), %ebp
+; X86-ATOM-NEXT:    movl %esp, %ebp
 ; X86-ATOM-NEXT:    .cfi_def_cfa_register %ebp
+; X86-ATOM-NEXT:    pushl %ebx
 ; X86-ATOM-NEXT:    pushl %edi
 ; X86-ATOM-NEXT:    pushl %esi
 ; X86-ATOM-NEXT:    andl $-16, %esp
 ; X86-ATOM-NEXT:    leal -{{[0-9]+}}(%esp), %esp
-; X86-ATOM-NEXT:    .cfi_offset %esi, -16
-; X86-ATOM-NEXT:    .cfi_offset %edi, -12
-; X86-ATOM-NEXT:    movl 8(%ebp), %esi
-; X86-ATOM-NEXT:    movl 12(%ebp), %eax
-; X86-ATOM-NEXT:    movl %esp, %ecx
-; X86-ATOM-NEXT:    pushl $0
-; X86-ATOM-NEXT:    pushl $0
+; X86-ATOM-NEXT:    .cfi_offset %esi, -20
+; X86-ATOM-NEXT:    .cfi_offset %edi, -16
+; X86-ATOM-NEXT:    .cfi_offset %ebx, -12
+; X86-ATOM-NEXT:    movl 12(%ebp), %edi
+; X86-ATOM-NEXT:    movl 12(%edi), %ecx
+; X86-ATOM-NEXT:    movl 8(%edi), %edx
+; X86-ATOM-NEXT:    movl (%edi), %esi
+; X86-ATOM-NEXT:    movl 4(%edi), %ebx
+; X86-ATOM-NEXT:    .p2align 4, 0x90
+; X86-ATOM-NEXT:  .LBB4_1: # %atomicrmw.start
+; X86-ATOM-NEXT:    # =>This Inner Loop Header: Depth=1
+; X86-ATOM-NEXT:    movl %esi, (%esp)
+; X86-ATOM-NEXT:    movl %ebx, {{[0-9]+}}(%esp)
+; X86-ATOM-NEXT:    movl %edx, {{[0-9]+}}(%esp)
+; X86-ATOM-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
+; X86-ATOM-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
+; X86-ATOM-NEXT:    movl %edx, {{[0-9]+}}(%esp)
+; X86-ATOM-NEXT:    movl %ebx, {{[0-9]+}}(%esp)
+; X86-ATOM-NEXT:    movl %esi, {{[0-9]+}}(%esp)
 ; X86-ATOM-NEXT:    pushl $0
 ; X86-ATOM-NEXT:    pushl $0
+; X86-ATOM-NEXT:    leal {{[0-9]+}}(%esp), %eax
+; X86-ATOM-NEXT:    pushl %eax
+; X86-ATOM-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X86-ATOM-NEXT:    pushl %eax
-; X86-ATOM-NEXT:    pushl %ecx
-; X86-ATOM-NEXT:    calll __sync_fetch_and_or_16
+; X86-ATOM-NEXT:    pushl %edi
+; X86-ATOM-NEXT:    pushl $16
+; X86-ATOM-NEXT:    calll __atomic_compare_exchange@PLT
 ; X86-ATOM-NEXT:    leal {{[0-9]+}}(%esp), %esp
-; X86-ATOM-NEXT:    movl (%esp), %ecx
+; X86-ATOM-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-ATOM-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; X86-ATOM-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-ATOM-NEXT:    movl {{[0-9]+}}(%esp), %edi
-; X86-ATOM-NEXT:    movl %eax, 8(%esi)
-; X86-ATOM-NEXT:    movl %edi, 12(%esi)
-; X86-ATOM-NEXT:    movl %ecx, (%esi)
-; X86-ATOM-NEXT:    movl %esi, %eax
-; X86-ATOM-NEXT:    movl %edx, 4(%esi)
-; X86-ATOM-NEXT:    leal -8(%ebp), %esp
+; X86-ATOM-NEXT:    testb %al, %al
+; X86-ATOM-NEXT:    movl (%esp), %esi
+; X86-ATOM-NEXT:    movl {{[0-9]+}}(%esp), %ebx
+; X86-ATOM-NEXT:    je .LBB4_1
+; X86-ATOM-NEXT:  # %bb.2: # %atomicrmw.end
+; X86-ATOM-NEXT:    movl 8(%ebp), %eax
+; X86-ATOM-NEXT:    movl %esi, (%eax)
+; X86-ATOM-NEXT:    movl %ebx, 4(%eax)
+; X86-ATOM-NEXT:    movl %edx, 8(%eax)
+; X86-ATOM-NEXT:    movl %ecx, 12(%eax)
+; X86-ATOM-NEXT:    leal -12(%ebp), %esp
 ; X86-ATOM-NEXT:    popl %esi
 ; X86-ATOM-NEXT:    popl %edi
+; X86-ATOM-NEXT:    popl %ebx
 ; X86-ATOM-NEXT:    popl %ebp
 ; X86-ATOM-NEXT:    .cfi_def_cfa %esp, 4
 ; X86-ATOM-NEXT:    retl $4
@@ -507,78 +520,120 @@ define void @or128_nouse_seq_cst(ptr %p) {
 ; X64-NEXT:    .cfi_def_cfa_offset 16
 ; X64-NEXT:    xorl %esi, %esi
 ; X64-NEXT:    xorl %edx, %edx
-; X64-NEXT:    callq __sync_fetch_and_or_16@PLT
+; X64-NEXT:    movl $5, %ecx
+; X64-NEXT:    callq __atomic_fetch_or_16@PLT
 ; X64-NEXT:    popq %rax
 ; X64-NEXT:    .cfi_def_cfa_offset 8
 ; X64-NEXT:    retq
 ;
-; X86-SSE2-LABEL: or128_nouse_seq_cst:
-; X86-SSE2:       # %bb.0:
-; X86-SSE2-NEXT:    pushl %ebp
-; X86-SSE2-NEXT:    .cfi_def_cfa_offset 8
-; X86-SSE2-NEXT:    .cfi_offset %ebp, -8
-; X86-SSE2-NEXT:    movl %esp, %ebp
-; X86-SSE2-NEXT:    .cfi_def_cfa_register %ebp
-; X86-SSE2-NEXT:    andl $-16, %esp
-; X86-SSE2-NEXT:    subl $32, %esp
-; X86-SSE2-NEXT:    movl %esp, %eax
-; X86-SSE2-NEXT:    pushl $0
-; X86-SSE2-NEXT:    pushl $0
-; X86-SSE2-NEXT:    pushl $0
-; X86-SSE2-NEXT:    pushl $0
-; X86-SSE2-NEXT:    pushl 8(%ebp)
-; X86-SSE2-NEXT:    pushl %eax
-; X86-SSE2-NEXT:    calll __sync_fetch_and_or_16
-; X86-SSE2-NEXT:    addl $20, %esp
-; X86-SSE2-NEXT:    movl %ebp, %esp
-; X86-SSE2-NEXT:    popl %ebp
-; X86-SSE2-NEXT:    .cfi_def_cfa %esp, 4
-; X86-SSE2-NEXT:    retl
-;
-; X86-SLM-LABEL: or128_nouse_seq_cst:
-; X86-SLM:       # %bb.0:
-; X86-SLM-NEXT:    pushl %ebp
-; X86-SLM-NEXT:    .cfi_def_cfa_offset 8
-; X86-SLM-NEXT:    .cfi_offset %ebp, -8
-; X86-SLM-NEXT:    movl %esp, %ebp
-; X86-SLM-NEXT:    .cfi_def_cfa_register %ebp
-; X86-SLM-NEXT:    andl $-16, %esp
-; X86-SLM-NEXT:    subl $32, %esp
-; X86-SLM-NEXT:    movl 8(%ebp), %eax
-; X86-SLM-NEXT:    movl %esp, %ecx
-; X86-SLM-NEXT:    pushl $0
-; X86-SLM-NEXT:    pushl $0
-; X86-SLM-NEXT:    pushl $0
-; X86-SLM-NEXT:    pushl $0
-; X86-SLM-NEXT:    pushl %eax
-; X86-SLM-NEXT:    pushl %ecx
-; X86-SLM-NEXT:    calll __sync_fetch_and_or_16
-; X86-SLM-NEXT:    addl $20, %esp
-; X86-SLM-NEXT:    movl %ebp, %esp
-; X86-SLM-NEXT:    popl %ebp
-; X86-SLM-NEXT:    .cfi_def_cfa %esp, 4
-; X86-SLM-NEXT:    retl
+; X86-GENERIC-LABEL: or128_nouse_seq_cst:
+; X86-GENERIC:       # %bb.0:
+; X86-GENERIC-NEXT:    pushl %ebp
+; X86-GENERIC-NEXT:    .cfi_def_cfa_offset 8
+; X86-GENERIC-NEXT:    .cfi_offset %ebp, -8
+; X86-GENERIC-NEXT:    movl %esp, %ebp
+; X86-GENERIC-NEXT:    .cfi_def_cfa_register %ebp
+; X86-GENERIC-NEXT:    pushl %ebx
+; X86-GENERIC-NEXT:    pushl %edi
+; X86-GENERIC-NEXT:    pushl %esi
+; X86-GENERIC-NEXT:    andl $-16, %esp
+; X86-GENERIC-NEXT:    subl $48, %esp
+; X86-GENERIC-NEXT:    .cfi_offset %esi, -20
+; X86-GENERIC-NEXT:    .cfi_offset %edi, -16
+; X86-GENERIC-NEXT:    .cfi_offset %ebx, -12
+; X86-GENERIC-NEXT:    movl 8(%ebp), %esi
+; X86-GENERIC-NEXT:    movl 12(%esi), %ecx
+; X86-GENERIC-NEXT:    movl 8(%esi), %edi
+; X86-GENERIC-NEXT:    movl (%esi), %edx
+; X86-GENERIC-NEXT:    movl 4(%esi), %ebx
+; X86-GENERIC-NEXT:    .p2align 4, 0x90
+; X86-GENERIC-NEXT:  .LBB12_1: # %atomicrmw.start
+; X86-GENERIC-NEXT:    # =>This Inner Loop Header: Depth=1
+; X86-GENERIC-NEXT:    movl %edx, (%esp)
+; X86-GENERIC-NEXT:    movl %ebx, {{[0-9]+}}(%esp)
+; X86-GENERIC-NEXT:    movl %edi, {{[0-9]+}}(%esp)
+; X86-GENERIC-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
+; X86-GENERIC-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
+; X86-GENERIC-NEXT:    movl %edi, {{[0-9]+}}(%esp)
+; X86-GENERIC-NEXT:    movl %ebx, {{[0-9]+}}(%esp)
+; X86-GENERIC-NEXT:    movl %edx, {{[0-9]+}}(%esp)
+; X86-GENERIC-NEXT:    pushl $5
+; X86-GENERIC-NEXT:    pushl $5
+; X86-GENERIC-NEXT:    leal {{[0-9]+}}(%esp), %eax
+; X86-GENERIC-NEXT:    pushl %eax
+; X86-GENERIC-NEXT:    leal {{[0-9]+}}(%esp), %eax
+; X86-GENERIC-NEXT:    pushl %eax
+; X86-GENERIC-NEXT:    pushl %esi
+; X86-GENERIC-NEXT:    pushl $16
+; X86-GENERIC-NEXT:    calll __atomic_compare_exchange@PLT
+; X86-GENERIC-NEXT:    addl $24, %esp
+; X86-GENERIC-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-GENERIC-NEXT:    movl {{[0-9]+}}(%esp), %edi
+; X86-GENERIC-NEXT:    movl (%esp), %edx
+; X86-GENERIC-NEXT:    movl {{[0-9]+}}(%esp), %ebx
+; X86-GENERIC-NEXT:    testb %al, %al
+; X86-GENERIC-NEXT:    je .LBB12_1
+; X86-GENERIC-NEXT:  # %bb.2: # %atomicrmw.end
+; X86-GENERIC-NEXT:    leal -12(%ebp), %esp
+; X86-GENERIC-NEXT:    popl %esi
+; X86-GENERIC-NEXT:    popl %edi
+; X86-GENERIC-NEXT:    popl %ebx
+; X86-GENERIC-NEXT:    popl %ebp
+; X86-GENERIC-NEXT:    .cfi_def_cfa %esp, 4
+; X86-GENERIC-NEXT:    retl
 ;
 ; X86-ATOM-LABEL: or128_nouse_seq_cst:
 ; X86-ATOM:       # %bb.0:
 ; X86-ATOM-NEXT:    pushl %ebp
 ; X86-ATOM-NEXT:    .cfi_def_cfa_offset 8
 ; X86-ATOM-NEXT:    .cfi_offset %ebp, -8
-; X86-ATOM-NEXT:    leal (%esp), %ebp
+; X86-ATOM-NEXT:    movl %esp, %ebp
 ; X86-ATOM-NEXT:    .cfi_def_cfa_register %ebp
+; X86-ATOM-NEXT:    pushl %ebx
+; X86-ATOM-NEXT:    pushl %edi
+; X86-ATOM-NEXT:    pushl %esi
 ; X86-ATOM-NEXT:    andl $-16, %esp
 ; X86-ATOM-NEXT:    leal -{{[0-9]+}}(%esp), %esp
-; X86-ATOM-NEXT:    movl 8(%ebp), %eax
-; X86-ATOM-NEXT:    movl %esp, %ecx
-; X86-ATOM-NEXT:    pushl $0
-; X86-ATOM-NEXT:    pushl $0
-; X86-ATOM-NEXT:    pushl $0
-; X86-ATOM-NEXT:    pushl $0
+; X86-ATOM-NEXT:    .cfi_offset %esi, -20
+; X86-ATOM-NEXT:    .cfi_offset %edi, -16
+; X86-ATOM-NEXT:    .cfi_offset %ebx, -12
+; X86-ATOM-NEXT:    movl 8(%ebp), %esi
+; X86-ATOM-NEXT:    movl %esp, %ebx
+; X86-ATOM-NEXT:    movl 12(%esi), %ecx
+; X86-ATOM-NEXT:    movl 8(%esi), %edx
+; X86-ATOM-NEXT:    movl (%esi), %eax
+; X86-ATOM-NEXT:    movl 4(%esi), %edi
+; X86-ATOM-NEXT:    .p2align 4, 0x90
+; X86-ATOM-NEXT:  .LBB12_1: # %atomicrmw.start
+; X86-ATOM-NEXT:    # =>This Inner Loop Header: Depth=1
+; X86-ATOM-NEXT:    movl %eax, (%esp)
+; X86-ATOM-NEXT:    movl %edi, {{[0-9]+}}(%esp)
+; X86-ATOM-NEXT:    movl %edx, {{[0-9]+}}(%esp)
+; X86-ATOM-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
+; X86-ATOM-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
+; X86-ATOM-NEXT:    movl %edx, {{[0-9]+}}(%esp)
+; X86-ATOM-NEXT:    movl %edi, {{[0-9]+}}(%esp)
+; X86-ATOM-NEXT:    movl %eax, {{[0-9]+}}(%esp)
+; X86-ATOM-NEXT:    pushl $5
+; X86-ATOM-NEXT:    pushl $5
+; X86-ATOM-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X86-ATOM-NEXT:    pushl %eax
-; X86-ATOM-NEXT:    pushl %ecx
-; X86-ATOM-NEXT:    calll __sync_fetch_and_or_16
+; X86-ATOM-NEXT:    pushl %ebx
+; X86-ATOM-NEXT:    pushl %esi
+; X86-ATOM-NEXT:    pushl $16
+; X86-ATOM-NEXT:    calll __atomic_compare_exchange@PLT
 ; X86-ATOM-NEXT:    leal {{[0-9]+}}(%esp), %esp
-; X86-ATOM-NEXT:    movl %ebp, %esp
+; X86-ATOM-NEXT:    testb %al, %al
+; X86-ATOM-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-ATOM-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; X86-ATOM-NEXT:    movl (%esp), %eax
+; X86-ATOM-NEXT:    movl {{[0-9]+}}(%esp), %edi
+; X86-ATOM-NEXT:    je .LBB12_1
+; X86-ATOM-NEXT:  # %bb.2: # %atomicrmw.end
+; X86-ATOM-NEXT:    leal -12(%ebp), %esp
+; X86-ATOM-NEXT:    popl %esi
+; X86-ATOM-NEXT:    popl %edi
+; X86-ATOM-NEXT:    popl %ebx
 ; X86-ATOM-NEXT:    popl %ebp
 ; X86-ATOM-NEXT:    .cfi_def_cfa %esp, 4
 ; X86-ATOM-NEXT:    retl
diff --git a/llvm/test/CodeGen/X86/atomic-nocx16.ll b/llvm/test/CodeGen/X86/atomic-nocx16.ll
index 5677541242a2..a014da80f189 100644
--- a/llvm/test/CodeGen/X86/atomic-nocx16.ll
+++ b/llvm/test/CodeGen/X86/atomic-nocx16.ll
@@ -1,5 +1,5 @@
 ; RUN: llc < %s -mtriple=x86_64-- -verify-machineinstrs -mcpu=corei7 -mattr=-cx16 | FileCheck %s
-; RUN: llc < %s -mtriple=i386-linux-gnu -verify-machineinstrs -mattr=cx16 | FileCheck -check-prefix=CHECK %s
+; RUN: llc < %s -mtriple=i386-linux-gnu -verify-machineinstrs -mattr=cx16 | FileCheck -check-prefix=CHECK32 %s
 
 ;; Verify that 128-bit atomics emit a libcall without cx16
 ;; available.
@@ -10,25 +10,35 @@
 ; CHECK-LABEL: test:
 define void @test(ptr %a) nounwind {
 entry:
-; CHECK: __sync_val_compare_and_swap_16
+; CHECK: __atomic_compare_exchange_16
+; CHECK32: __atomic_compare_exchange
   %0 = cmpxchg ptr %a, i128 1, i128 1 seq_cst seq_cst
-; CHECK: __sync_lock_test_and_set_16
+; CHECK: __atomic_exchange_16
+; CHECK32: __atomic_exchange
   %1 = atomicrmw xchg ptr %a, i128 1 seq_cst
-; CHECK: __sync_fetch_and_add_16
+; CHECK: __atomic_fetch_add_16
+; CHECK32: __atomic_compare_exchange
   %2 = atomicrmw add ptr %a, i128 1 seq_cst
-; CHECK: __sync_fetch_and_sub_16
+; CHECK: __atomic_fetch_sub_16
+; CHECK32: __atomic_compare_exchange
   %3 = atomicrmw sub ptr %a, i128 1 seq_cst
-; CHECK: __sync_fetch_and_and_16
+; CHECK: __atomic_fetch_and_16
+; CHECK32: __atomic_compare_exchange
   %4 = atomicrmw and ptr %a, i128 1 seq_cst
-; CHECK: __sync_fetch_and_nand_16
+; CHECK: __atomic_fetch_nand_16
+; CHECK32: __atomic_compare_exchange
   %5 = atomicrmw nand ptr %a, i128 1 seq_cst
-; CHECK: __sync_fetch_and_or_16
+; CHECK: __atomic_fetch_or_16
+; CHECK32: __atomic_compare_exchange
   %6 = atomicrmw or ptr %a, i128 1 seq_cst
-; CHECK: __sync_fetch_and_xor_16
+; CHECK: __atomic_fetch_xor_16
+; CHECK32: __atomic_compare_exchange
   %7 = atomicrmw xor ptr %a, i128 1 seq_cst
-; CHECK: __sync_val_compare_and_swap_16
+; CHECK: __atomic_load_16
+; CHECK32: __atomic_load
   %8 = load atomic i128, ptr %a seq_cst, align 16
-; CHECK: __sync_lock_test_and_set_16
+; CHECK: __atomic_store_16
+; CHECK32: __atomic_store
   store atomic i128 %8, ptr %a seq_cst, align 16
   ret void
 }
@@ -36,14 +46,20 @@ entry:
 ; CHECK-LABEL: test_fp:
 define void @test_fp(fp128* %a) nounwind {
 entry:
-; CHECK: __sync_lock_test_and_set_16
+; CHECK: __atomic_exchange_16
+; CHECK32: __atomic_exchange
   %0 = atomicrmw xchg fp128* %a, fp128 0xL00000000000000004000900000000000 seq_cst
-; Currently fails to compile:
-;  %1 = atomicrmw fadd fp128* %a, fp128 0xL00000000000000004000900000000000 seq_cst
-;  %2 = atomicrmw fsub fp128* %a, fp128 0xL00000000000000004000900000000000 seq_cst
-; CHECK: __sync_val_compare_and_swap_16
-  %1 = load atomic fp128, fp128* %a seq_cst, align 16
-; CHECK: __sync_lock_test_and_set_16
-  store atomic fp128 %1, fp128* %a seq_cst, align 16
+; CHECK: __atomic_compare_exchange_16
+; CHECK32: __atomic_compare_exchange
+  %1 = atomicrmw fadd fp128* %a, fp128 0xL00000000000000004000900000000000 seq_cst
+; CHECK: __atomic_compare_exchange_16
+; CHECK32: __atomic_compare_exchange
+  %2 = atomicrmw fsub fp128* %a, fp128 0xL00000000000000004000900000000000 seq_cst
+; CHECK: __atomic_load_16
+; CHECK32: __atomic_load
+  %3 = load atomic fp128, fp128* %a seq_cst, align 16
+; CHECK: __atomic_store_16
+; CHECK32: __atomic_store
+  store atomic fp128 %3, fp128* %a seq_cst, align 16
   ret void
 }
diff --git a/llvm/test/CodeGen/X86/atomic-ops-ancient-64.ll b/llvm/test/CodeGen/X86/atomic-ops-ancient-64.ll
index 493c9a897f06..bc99caeea12b 100644
--- a/llvm/test/CodeGen/X86/atomic-ops-ancient-64.ll
+++ b/llvm/test/CodeGen/X86/atomic-ops-ancient-64.ll
@@ -1,44 +1,43 @@
-; RUN: llc -mtriple=i386-linux-gnu %s -o - | FileCheck %s
-; XFAIL: *
+; RUN: llc -mtriple=i386-linux-gnu -mcpu=i386 %s -o - | FileCheck %s
 
 define i64 @test_add(ptr %addr, i64 %inc) {
 ; CHECK-LABEL: test_add:
-; CHECK: calll __sync_fetch_and_add_8
+; CHECK: calll __atomic_fetch_add_8
   %old = atomicrmw add ptr %addr, i64 %inc seq_cst
   ret i64 %old
 }
 
 define i64 @test_sub(ptr %addr, i64 %inc) {
 ; CHECK-LABEL: test_sub:
-; CHECK: calll __sync_fetch_and_sub_8
+; CHECK: calll __atomic_fetch_sub_8
   %old = atomicrmw sub ptr %addr, i64 %inc seq_cst
   ret i64 %old
 }
 
 define i64 @test_and(ptr %andr, i64 %inc) {
 ; CHECK-LABEL: test_and:
-; CHECK: calll __sync_fetch_and_and_8
+; CHECK: calll __atomic_fetch_and_8
   %old = atomicrmw and ptr %andr, i64 %inc seq_cst
   ret i64 %old
 }
 
 define i64 @test_or(ptr %orr, i64 %inc) {
 ; CHECK-LABEL: test_or:
-; CHECK: calll __sync_fetch_and_or_8
+; CHECK: calll __atomic_fetch_or_8
   %old = atomicrmw or ptr %orr, i64 %inc seq_cst
   ret i64 %old
 }
 
 define i64 @test_xor(ptr %xorr, i64 %inc) {
 ; CHECK-LABEL: test_xor:
-; CHECK: calll __sync_fetch_and_xor_8
+; CHECK: calll __atomic_fetch_xor_8
   %old = atomicrmw xor ptr %xorr, i64 %inc seq_cst
   ret i64 %old
 }
 
 define i64 @test_nand(ptr %nandr, i64 %inc) {
 ; CHECK-LABEL: test_nand:
-; CHECK: calll __sync_fetch_and_nand_8
+; CHECK: calll __atomic_fetch_nand_8
   %old = atomicrmw nand ptr %nandr, i64 %inc seq_cst
   ret i64 %old
 }
diff --git a/llvm/test/CodeGen/X86/atomic-oversize.ll b/llvm/test/CodeGen/X86/atomic-oversize.ll
new file mode 100644
index 000000000000..93213ebc0667
--- /dev/null
+++ b/llvm/test/CodeGen/X86/atomic-oversize.ll
@@ -0,0 +1,11 @@
+; RUN: llc -mtriple=x86_64 -mattr=cx16 < %s | FileCheck %s
+
+; Atomics larger than 128-bit are unsupported, and emit libcalls.
+define void @test(ptr %a) nounwind {
+; CHECK-LABEL: test:
+; CHECK: callq __atomic_load
+; CHECK: callq __atomic_store
+  %1 = load atomic i256, ptr %a seq_cst, align 32
+  store atomic i256 %1, ptr %a seq_cst, align 32
+  ret void
+}
diff --git a/llvm/test/CodeGen/X86/atomic-xor.ll b/llvm/test/CodeGen/X86/atomic-xor.ll
index 97fa908f1b71..930286c8e5fb 100644
--- a/llvm/test/CodeGen/X86/atomic-xor.ll
+++ b/llvm/test/CodeGen/X86/atomic-xor.ll
@@ -22,32 +22,54 @@ define i128 @xor128_signbit_used(ptr %p) nounwind {
 ; X86:       # %bb.0:
 ; X86-NEXT:    pushl %ebp
 ; X86-NEXT:    movl %esp, %ebp
+; X86-NEXT:    pushl %ebx
 ; X86-NEXT:    pushl %edi
 ; X86-NEXT:    pushl %esi
 ; X86-NEXT:    andl $-16, %esp
-; X86-NEXT:    subl $16, %esp
-; X86-NEXT:    movl 8(%ebp), %esi
-; X86-NEXT:    movl %esp, %eax
-; X86-NEXT:    pushl $-2147483648 # imm = 0x80000000
-; X86-NEXT:    pushl $0
+; X86-NEXT:    subl $48, %esp
+; X86-NEXT:    movl 12(%ebp), %edi
+; X86-NEXT:    movl 12(%edi), %ecx
+; X86-NEXT:    movl 8(%edi), %edx
+; X86-NEXT:    movl (%edi), %ebx
+; X86-NEXT:    movl 4(%edi), %esi
+; X86-NEXT:    .p2align 4, 0x90
+; X86-NEXT:  .LBB1_1: # %atomicrmw.start
+; X86-NEXT:    # =>This Inner Loop Header: Depth=1
+; X86-NEXT:    movl %ebx, (%esp)
+; X86-NEXT:    movl %esi, {{[0-9]+}}(%esp)
+; X86-NEXT:    movl %edx, {{[0-9]+}}(%esp)
+; X86-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
+; X86-NEXT:    addl $-2147483648, %ecx # imm = 0x80000000
+; X86-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
+; X86-NEXT:    movl %edx, {{[0-9]+}}(%esp)
+; X86-NEXT:    movl %esi, {{[0-9]+}}(%esp)
+; X86-NEXT:    movl %ebx, {{[0-9]+}}(%esp)
 ; X86-NEXT:    pushl $0
 ; X86-NEXT:    pushl $0
-; X86-NEXT:    pushl 12(%ebp)
+; X86-NEXT:    leal {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    pushl %eax
+; X86-NEXT:    leal {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    pushl %eax
-; X86-NEXT:    calll __sync_fetch_and_xor_16
-; X86-NEXT:    addl $20, %esp
-; X86-NEXT:    movl (%esp), %eax
+; X86-NEXT:    pushl %edi
+; X86-NEXT:    pushl $16
+; X86-NEXT:    calll __atomic_compare_exchange@PLT
+; X86-NEXT:    addl $24, %esp
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; X86-NEXT:    movl {{[0-9]+}}(%esp), %edi
-; X86-NEXT:    movl %edi, 8(%esi)
-; X86-NEXT:    movl %edx, 12(%esi)
-; X86-NEXT:    movl %eax, (%esi)
-; X86-NEXT:    movl %ecx, 4(%esi)
-; X86-NEXT:    movl %esi, %eax
-; X86-NEXT:    leal -8(%ebp), %esp
+; X86-NEXT:    movl (%esp), %ebx
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT:    testb %al, %al
+; X86-NEXT:    je .LBB1_1
+; X86-NEXT:  # %bb.2: # %atomicrmw.end
+; X86-NEXT:    movl 8(%ebp), %eax
+; X86-NEXT:    movl %ebx, (%eax)
+; X86-NEXT:    movl %esi, 4(%eax)
+; X86-NEXT:    movl %edx, 8(%eax)
+; X86-NEXT:    movl %ecx, 12(%eax)
+; X86-NEXT:    leal -12(%ebp), %esp
 ; X86-NEXT:    popl %esi
 ; X86-NEXT:    popl %edi
+; X86-NEXT:    popl %ebx
 ; X86-NEXT:    popl %ebp
 ; X86-NEXT:    retl $4
 ;
@@ -56,7 +78,8 @@ define i128 @xor128_signbit_used(ptr %p) nounwind {
 ; X64-NEXT:    pushq %rax
 ; X64-NEXT:    movabsq $-9223372036854775808, %rdx # imm = 0x8000000000000000
 ; X64-NEXT:    xorl %esi, %esi
-; X64-NEXT:    callq __sync_fetch_and_xor_16@PLT
+; X64-NEXT:    xorl %ecx, %ecx
+; X64-NEXT:    callq __atomic_fetch_xor_16@PLT
 ; X64-NEXT:    popq %rcx
 ; X64-NEXT:    retq
   %r = atomicrmw xor ptr %p, i128 170141183460469231731687303715884105728 monotonic
-- 
GitLab


From bfebadc8c392fc3bc8cbd54af735a006f50a5d8c Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Tue, 12 Dec 2023 14:26:40 +0100
Subject: [PATCH 291/349] [LVI] Don't require DataLayout in
 getConstantRangeOrFull() (NFC)

We're only working on integers here, so we don't need DataLayout
to determine the width.
---
 llvm/lib/Analysis/LazyValueInfo.cpp | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/llvm/lib/Analysis/LazyValueInfo.cpp b/llvm/lib/Analysis/LazyValueInfo.cpp
index ec870694f5b6..c47532152190 100644
--- a/llvm/lib/Analysis/LazyValueInfo.cpp
+++ b/llvm/lib/Analysis/LazyValueInfo.cpp
@@ -802,10 +802,11 @@ void LazyValueInfoImpl::intersectAssumeOrGuardBlockValueConstantRange(
 }
 
 static ConstantRange getConstantRangeOrFull(const ValueLatticeElement &Val,
-                                            Type *Ty, const DataLayout &DL) {
+                                            Type *Ty) {
+  assert(Ty->isIntOrIntVectorTy() && "Must be integer type");
   if (Val.isConstantRange(/*UndefAllowed*/ false))
     return Val.getConstantRange();
-  return ConstantRange::getFull(DL.getTypeSizeInBits(Ty));
+  return ConstantRange::getFull(Ty->getScalarSizeInBits());
 }
 
 std::optional<ValueLatticeElement>
@@ -825,9 +826,9 @@ LazyValueInfoImpl::solveBlockValueSelect(SelectInst *SI, BasicBlock *BB) {
 
   if (TrueVal.isConstantRange() || FalseVal.isConstantRange()) {
     const ConstantRange &TrueCR =
-        getConstantRangeOrFull(TrueVal, SI->getType(), DL);
+        getConstantRangeOrFull(TrueVal, SI->getType());
     const ConstantRange &FalseCR =
-        getConstantRangeOrFull(FalseVal, SI->getType(), DL);
+        getConstantRangeOrFull(FalseVal, SI->getType());
     Value *LHS = nullptr;
     Value *RHS = nullptr;
     SelectPatternResult SPR = matchSelectPattern(SI, LHS, RHS);
@@ -898,7 +899,7 @@ LazyValueInfoImpl::getRangeFor(Value *V, Instruction *CxtI, BasicBlock *BB) {
   std::optional<ValueLatticeElement> OptVal = getBlockValue(V, BB, CxtI);
   if (!OptVal)
     return std::nullopt;
-  return getConstantRangeOrFull(*OptVal, V->getType(), DL);
+  return getConstantRangeOrFull(*OptVal, V->getType());
 }
 
 std::optional<ValueLatticeElement>
-- 
GitLab


From 17b8f87f76365e65350ec3f7f982b21b8d895598 Mon Sep 17 00:00:00 2001
From: Orlando Cazalet-Hyams <orlando.hyams@sony.com>
Date: Tue, 12 Dec 2023 13:30:15 +0000
Subject: [PATCH 292/349] [RemoveDIs][NFC] Find DPValues using findDbgDeclares 
 (#73500)

This patch doesn't change any call sites.

Depends on #73498.
---
 llvm/include/llvm/IR/DebugInfo.h              |  3 +-
 .../include/llvm/IR/DebugProgramInstruction.h |  3 ++
 llvm/lib/IR/DebugInfo.cpp                     | 42 +++++++------------
 3 files changed, 21 insertions(+), 27 deletions(-)

diff --git a/llvm/include/llvm/IR/DebugInfo.h b/llvm/include/llvm/IR/DebugInfo.h
index 5ed423bfd1c1..36ef77f9505b 100644
--- a/llvm/include/llvm/IR/DebugInfo.h
+++ b/llvm/include/llvm/IR/DebugInfo.h
@@ -40,7 +40,8 @@ class Module;
 
 /// Finds dbg.declare intrinsics declaring local variables as living in the
 /// memory that 'V' points to.
-void findDbgDeclares(SmallVectorImpl<DbgDeclareInst *> &DbgUsers, Value *V);
+void findDbgDeclares(SmallVectorImpl<DbgDeclareInst *> &DbgUsers, Value *V,
+                     SmallVectorImpl<DPValue *> *DPValues = nullptr);
 
 /// Finds the llvm.dbg.value intrinsics describing a value.
 void findDbgValues(SmallVectorImpl<DbgValueInst *> &DbgValues,
diff --git a/llvm/include/llvm/IR/DebugProgramInstruction.h b/llvm/include/llvm/IR/DebugProgramInstruction.h
index f73a6237a477..8230070343e0 100644
--- a/llvm/include/llvm/IR/DebugProgramInstruction.h
+++ b/llvm/include/llvm/IR/DebugProgramInstruction.h
@@ -97,6 +97,9 @@ public:
   enum class LocationType {
     Declare,
     Value,
+
+    End, ///< Marks the end of the concrete types.
+    Any, ///< To indicate all LocationTypes in searches.
   };
   /// Classification of the debug-info record that this DPValue represents.
   /// Essentially, "is this a dbg.value or dbg.declare?". dbg.declares are not
diff --git a/llvm/lib/IR/DebugInfo.cpp b/llvm/lib/IR/DebugInfo.cpp
index b3cc9996ace4..eab05eed428e 100644
--- a/llvm/lib/IR/DebugInfo.cpp
+++ b/llvm/lib/IR/DebugInfo.cpp
@@ -44,28 +44,10 @@ using namespace llvm;
 using namespace llvm::at;
 using namespace llvm::dwarf;
 
-void llvm::findDbgDeclares(SmallVectorImpl<DbgDeclareInst *> &DbgUsers,
-                           Value *V) {
-  // This function is hot. Check whether the value has any metadata to avoid a
-  // DenseMap lookup.
-  if (!V->isUsedByMetadata())
-    return;
-  auto *L = LocalAsMetadata::getIfExists(V);
-  if (!L)
-    return;
-  auto *MDV = MetadataAsValue::getIfExists(V->getContext(), L);
-  if (!MDV)
-    return;
-
-  for (User *U : MDV->users()) {
-    if (auto *DDI = dyn_cast<DbgDeclareInst>(U))
-      DbgUsers.push_back(DDI);
-  }
-}
-
-template <typename IntrinsicT>
-static void findDbgIntrinsics(SmallVectorImpl<IntrinsicT *> &Result,
-                              Value *V, SmallVectorImpl<DPValue *> *DPValues) {
+template <typename IntrinsicT,
+          DPValue::LocationType Type = DPValue::LocationType::Any>
+static void findDbgIntrinsics(SmallVectorImpl<IntrinsicT *> &Result, Value *V,
+                              SmallVectorImpl<DPValue *> *DPValues) {
   // This function is hot. Check whether the value has any metadata to avoid a
   // DenseMap lookup.
   if (!V->isUsedByMetadata())
@@ -94,7 +76,7 @@ static void findDbgIntrinsics(SmallVectorImpl<IntrinsicT *> &Result,
     // Get DPValues that use this as a single value.
     if (LocalAsMetadata *L = dyn_cast<LocalAsMetadata>(MD)) {
       for (DPValue *DPV : L->getAllDPValueUsers()) {
-        if (DPV->getType() == DPValue::LocationType::Value)
+        if (Type == DPValue::LocationType::Any || DPV->getType() == Type)
           DPValues->push_back(DPV);
       }
     }
@@ -108,21 +90,29 @@ static void findDbgIntrinsics(SmallVectorImpl<IntrinsicT *> &Result,
         continue;
       DIArgList *DI = cast<DIArgList>(AL);
       for (DPValue *DPV : DI->getAllDPValueUsers())
-        if (DPV->getType() == DPValue::LocationType::Value)
+        if (Type == DPValue::LocationType::Any || DPV->getType() == Type)
           if (EncounteredDPValues.insert(DPV).second)
             DPValues->push_back(DPV);
     }
   }
 }
 
+void llvm::findDbgDeclares(SmallVectorImpl<DbgDeclareInst *> &DbgUsers,
+                           Value *V, SmallVectorImpl<DPValue *> *DPValues) {
+  findDbgIntrinsics<DbgDeclareInst, DPValue::LocationType::Declare>(DbgUsers, V,
+                                                                    DPValues);
+}
+
 void llvm::findDbgValues(SmallVectorImpl<DbgValueInst *> &DbgValues,
                          Value *V, SmallVectorImpl<DPValue *> *DPValues) {
-  findDbgIntrinsics<DbgValueInst>(DbgValues, V, DPValues);
+  findDbgIntrinsics<DbgValueInst, DPValue::LocationType::Value>(DbgValues, V,
+                                                                DPValues);
 }
 
 void llvm::findDbgUsers(SmallVectorImpl<DbgVariableIntrinsic *> &DbgUsers,
                         Value *V, SmallVectorImpl<DPValue *> *DPValues) {
-  findDbgIntrinsics<DbgVariableIntrinsic>(DbgUsers, V, DPValues);
+  findDbgIntrinsics<DbgVariableIntrinsic, DPValue::LocationType::Any>(
+      DbgUsers, V, DPValues);
 }
 
 DISubprogram *llvm::getDISubprogram(const MDNode *Scope) {
-- 
GitLab


From edcc7fe9aae54221b80631f5441354a04ad40b3b Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Tue, 12 Dec 2023 14:40:43 +0100
Subject: [PATCH 293/349] [LVI] Reuse LatticeValue to ConstantRange conversion
 more

Use the helper in the getConstantRange() and
getConstantRangeAtUse() APIs as well. For that purpose move the
handling of isUnknown() into the helper as well.
---
 llvm/lib/Analysis/LazyValueInfo.cpp | 43 +++++++++--------------------
 1 file changed, 13 insertions(+), 30 deletions(-)

diff --git a/llvm/lib/Analysis/LazyValueInfo.cpp b/llvm/lib/Analysis/LazyValueInfo.cpp
index c47532152190..90d900a13986 100644
--- a/llvm/lib/Analysis/LazyValueInfo.cpp
+++ b/llvm/lib/Analysis/LazyValueInfo.cpp
@@ -801,12 +801,15 @@ void LazyValueInfoImpl::intersectAssumeOrGuardBlockValueConstantRange(
   }
 }
 
-static ConstantRange getConstantRangeOrFull(const ValueLatticeElement &Val,
-                                            Type *Ty) {
+static ConstantRange toConstantRange(const ValueLatticeElement &Val,
+                                     Type *Ty, bool UndefAllowed = false) {
   assert(Ty->isIntOrIntVectorTy() && "Must be integer type");
-  if (Val.isConstantRange(/*UndefAllowed*/ false))
+  if (Val.isConstantRange(UndefAllowed))
     return Val.getConstantRange();
-  return ConstantRange::getFull(Ty->getScalarSizeInBits());
+  unsigned BW = Ty->getScalarSizeInBits();
+  if (Val.isUnknown())
+    return ConstantRange::getEmpty(BW);
+  return ConstantRange::getFull(BW);
 }
 
 std::optional<ValueLatticeElement>
@@ -825,10 +828,8 @@ LazyValueInfoImpl::solveBlockValueSelect(SelectInst *SI, BasicBlock *BB) {
   ValueLatticeElement &FalseVal = *OptFalseVal;
 
   if (TrueVal.isConstantRange() || FalseVal.isConstantRange()) {
-    const ConstantRange &TrueCR =
-        getConstantRangeOrFull(TrueVal, SI->getType());
-    const ConstantRange &FalseCR =
-        getConstantRangeOrFull(FalseVal, SI->getType());
+    const ConstantRange &TrueCR = toConstantRange(TrueVal, SI->getType());
+    const ConstantRange &FalseCR = toConstantRange(FalseVal, SI->getType());
     Value *LHS = nullptr;
     Value *RHS = nullptr;
     SelectPatternResult SPR = matchSelectPattern(SI, LHS, RHS);
@@ -899,7 +900,7 @@ LazyValueInfoImpl::getRangeFor(Value *V, Instruction *CxtI, BasicBlock *BB) {
   std::optional<ValueLatticeElement> OptVal = getBlockValue(V, BB, CxtI);
   if (!OptVal)
     return std::nullopt;
-  return getConstantRangeOrFull(*OptVal, V->getType());
+  return toConstantRange(*OptVal, V->getType());
 }
 
 std::optional<ValueLatticeElement>
@@ -1624,19 +1625,10 @@ Constant *LazyValueInfo::getConstant(Value *V, Instruction *CxtI) {
 ConstantRange LazyValueInfo::getConstantRange(Value *V, Instruction *CxtI,
                                               bool UndefAllowed) {
   assert(V->getType()->isIntegerTy());
-  unsigned Width = V->getType()->getIntegerBitWidth();
   BasicBlock *BB = CxtI->getParent();
   ValueLatticeElement Result =
       getOrCreateImpl(BB->getModule()).getValueInBlock(V, BB, CxtI);
-  if (Result.isUnknown())
-    return ConstantRange::getEmpty(Width);
-  if (Result.isConstantRange(UndefAllowed))
-    return Result.getConstantRange(UndefAllowed);
-  // We represent ConstantInt constants as constant ranges but other kinds
-  // of integer constants, i.e. ConstantExpr will be tagged as constants
-  assert(!(Result.isConstant() && isa<ConstantInt>(Result.getConstant())) &&
-         "ConstantInt value must be represented as constantrange");
-  return ConstantRange::getFull(Width);
+  return toConstantRange(Result, V->getType(), UndefAllowed);
 }
 
 ConstantRange LazyValueInfo::getConstantRangeAtUse(const Use &U,
@@ -1709,20 +1701,11 @@ ConstantRange LazyValueInfo::getConstantRangeOnEdge(Value *V,
                                                     BasicBlock *FromBB,
                                                     BasicBlock *ToBB,
                                                     Instruction *CxtI) {
-  unsigned Width = V->getType()->getIntegerBitWidth();
   Module *M = FromBB->getModule();
   ValueLatticeElement Result =
       getOrCreateImpl(M).getValueOnEdge(V, FromBB, ToBB, CxtI);
-
-  if (Result.isUnknown())
-    return ConstantRange::getEmpty(Width);
-  if (Result.isConstantRange())
-    return Result.getConstantRange();
-  // We represent ConstantInt constants as constant ranges but other kinds
-  // of integer constants, i.e. ConstantExpr will be tagged as constants
-  assert(!(Result.isConstant() && isa<ConstantInt>(Result.getConstant())) &&
-         "ConstantInt value must be represented as constantrange");
-  return ConstantRange::getFull(Width);
+  // TODO: Should undef be allowed here?
+  return toConstantRange(Result, V->getType(), /*UndefAllowed*/ true);
 }
 
 static LazyValueInfo::Tristate
-- 
GitLab


From ccec22b675195bf45a5e34583a866ab881f94dde Mon Sep 17 00:00:00 2001
From: Jacek Caban <jacek@codeweavers.com>
Date: Tue, 12 Dec 2023 14:45:42 +0100
Subject: [PATCH 294/349] [lld][NFC] Silence -Wuninitialized GCC 11 warnings.
 (#75183)

Use of those variables is guarded by lastType, so they are not actually used uninitialized.
---
 lld/COFF/Writer.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lld/COFF/Writer.cpp b/lld/COFF/Writer.cpp
index 7b1ff8071e2e..89e0f5b2df74 100644
--- a/lld/COFF/Writer.cpp
+++ b/lld/COFF/Writer.cpp
@@ -560,7 +560,7 @@ void Writer::createECCodeMap() {
   codeMap.clear();
 
   std::optional<chpe_range_type> lastType;
-  Chunk *first, *last;
+  Chunk *first = nullptr, *last = nullptr;
 
   auto closeRange = [&]() {
     if (lastType) {
-- 
GitLab


From b730703726e674f78717e263d92ecf9a0a8d479e Mon Sep 17 00:00:00 2001
From: Dominik Adamski <dominik.adamski@amd.com>
Date: Tue, 12 Dec 2023 15:05:26 +0100
Subject: [PATCH 295/349] [NFC][MLIR][OpenMP] Add test to check lowering
 omp.wsloop for GPU (#74857)

This test checks if proper OpenMP device RTL function is called to
handle workshare loop for GPU.

The code generation for GPU worksharing loops is implemented by the
patch: https://github.com/llvm/llvm-project/pull/73360
---
 mlir/test/Target/LLVMIR/omptarget-wsloop.mlir | 33 +++++++++++++++++++
 1 file changed, 33 insertions(+)
 create mode 100644 mlir/test/Target/LLVMIR/omptarget-wsloop.mlir

diff --git a/mlir/test/Target/LLVMIR/omptarget-wsloop.mlir b/mlir/test/Target/LLVMIR/omptarget-wsloop.mlir
new file mode 100644
index 000000000000..ba641be4dada
--- /dev/null
+++ b/mlir/test/Target/LLVMIR/omptarget-wsloop.mlir
@@ -0,0 +1,33 @@
+// RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s
+
+// The aim of the test is to check the GPU LLVM IR codegen
+// for nested omp do loop inside omp target region
+
+module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.alloca_memory_space", 5 : ui32>>, llvm.data_layout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8", llvm.target_triple = "amdgcn-amd-amdhsa", omp.is_gpu = true, omp.is_target_device = true } {
+  llvm.func @target_wsloop(%arg0: !llvm.ptr ){
+      %loop_ub = llvm.mlir.constant(9 : i32) : i32
+      %loop_lb = llvm.mlir.constant(0 : i32) : i32
+      %loop_step = llvm.mlir.constant(1 : i32) : i32
+      omp.wsloop for  (%loop_cnt) : i32 = (%loop_lb) to (%loop_ub) inclusive step (%loop_step) {
+        %gep = llvm.getelementptr %arg0[0, %loop_cnt] : (!llvm.ptr, i32) -> !llvm.ptr, !llvm.array<10 x i32>
+        llvm.store %loop_cnt, %gep : i32, !llvm.ptr
+        omp.yield
+      }
+    llvm.return
+  }
+}
+
+// CHECK: define void @[[FUNC0:.*]](ptr %[[ARG0:.*]])
+// CHECK:   %[[STRUCTARG:.*]] = alloca { ptr }, align 8, addrspace(5)
+// CHECK:   %[[STRUCTARG_ASCAST:.*]] = addrspacecast ptr addrspace(5) %[[STRUCTARG]] to ptr
+// CHECK:   %[[GEP:.*]] = getelementptr { ptr }, ptr addrspace(5) %[[STRUCTARG]], i32 0, i32 0
+// CHECK:   store ptr %[[ARG0]], ptr addrspace(5) %[[GEP]], align 8
+// CHECK:   %[[NUM_THREADS:.*]] = call i32 @omp_get_num_threads()
+// CHECK:   call void @__kmpc_for_static_loop_4u(ptr addrspacecast (ptr addrspace(1) @[[GLOB1:[0-9]+]] to ptr), ptr @[[LOOP_BODY_FN:.*]], ptr %[[STRUCTARG_ASCAST]], i32 10, i32 %[[NUM_THREADS]], i32 0)
+
+// CHECK: define internal void @[[LOOP_BODY_FN]](i32 %[[LOOP_CNT:.*]], ptr %[[LOOP_BODY_ARG:.*]])
+// CHECK:   %[[GEP2:.*]] = getelementptr { ptr }, ptr %[[LOOP_BODY_ARG]], i32 0, i32 0
+// CHECK:   %[[LOADGEP:.*]] = load ptr, ptr %[[GEP2]], align 8
+// CHECK:   %[[GEP3:.*]] = getelementptr [10 x i32], ptr %[[LOADGEP]], i32 0, i32 %[[TMP2:.*]]
+// CHECK:   store i32 %[[VAL0:.*]], ptr %[[GEP3]], align 4
+
-- 
GitLab


From a9b30545448695c76ddb25a16fae613d641cfeb7 Mon Sep 17 00:00:00 2001
From: smanna12 <soumi.manna@intel.com>
Date: Tue, 12 Dec 2023 08:07:55 -0600
Subject: [PATCH 296/349] [NFC][CLANG] Fix static analyzer bugs about large
 copy by values (#75060)

Reported by Static Analyzer tool:

In getSourceRangeToTokenEnd(clang::Decl const *, clang::SourceManager
const &, clang::LangOptions): A very large function call parameter
exceeding the high threshold is passed by value

pass_by_value: Passing parameter LangOpts of type clang::LangOptions
(size 1784 bytes) by value, which exceeds the high threshold of 512
bytes
---
 clang/lib/Analysis/UnsafeBufferUsage.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clang/lib/Analysis/UnsafeBufferUsage.cpp b/clang/lib/Analysis/UnsafeBufferUsage.cpp
index a1efb76be68b..70eec1cee57f 100644
--- a/clang/lib/Analysis/UnsafeBufferUsage.cpp
+++ b/clang/lib/Analysis/UnsafeBufferUsage.cpp
@@ -1534,7 +1534,7 @@ static bool hasUnsupportedSpecifiers(const VarDecl *VD,
 // returned by this function is the last location of the last token.
 static SourceRange getSourceRangeToTokenEnd(const Decl *D,
                                             const SourceManager &SM,
-                                            LangOptions LangOpts) {
+                                            const LangOptions &LangOpts) {
   SourceLocation Begin = D->getBeginLoc();
   SourceLocation
     End = // `D->getEndLoc` should always return the starting location of the
-- 
GitLab


From 1c6b336395a886c0125462ef338e84ea3a6925e6 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad@amd.com>
Date: Tue, 12 Dec 2023 14:26:04 +0000
Subject: [PATCH 297/349] [AMDGPU] Miscellaneous clang-format changes (#75186)

Reformat one table and protect a couple of tables that we don't want to
reformat.
---
 .../Target/AMDGPU/AMDGPUArgumentUsageInfo.h   |  2 ++
 .../AMDGPURemoveIncompatibleFunctions.cpp     | 36 +++++++++----------
 llvm/lib/Target/AMDGPU/SIDefines.h            |  3 ++
 3 files changed, 22 insertions(+), 19 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h
index ee21fe1615be..42b33c50d9f8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h
@@ -98,6 +98,7 @@ struct KernArgPreloadDescriptor : public ArgDescriptor {
 };
 
 struct AMDGPUFunctionArgInfo {
+  // clang-format off
   enum PreloadedValue {
     // SGPRS:
     PRIVATE_SEGMENT_BUFFER = 0,
@@ -120,6 +121,7 @@ struct AMDGPUFunctionArgInfo {
     WORKITEM_ID_Z       = 19,
     FIRST_VGPR_VALUE    = WORKITEM_ID_X
   };
+  // clang-format on
 
   // Kernel input registers setup for the HSA ABI in allocation order.
 
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURemoveIncompatibleFunctions.cpp b/llvm/lib/Target/AMDGPU/AMDGPURemoveIncompatibleFunctions.cpp
index e387e16d0cf1..552380d54dfd 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURemoveIncompatibleFunctions.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURemoveIncompatibleFunctions.cpp
@@ -89,25 +89,23 @@ const SubtargetSubTypeKV *getGPUInfo(const GCNSubtarget &ST,
   return nullptr;
 }
 
-constexpr unsigned FeaturesToCheck[] = {
-    AMDGPU::FeatureGFX11Insts,
-    AMDGPU::FeatureGFX10Insts,
-    AMDGPU::FeatureGFX9Insts,
-    AMDGPU::FeatureGFX8Insts,
-    AMDGPU::FeatureDPP,
-    AMDGPU::Feature16BitInsts,
-    AMDGPU::FeatureDot1Insts,
-    AMDGPU::FeatureDot2Insts,
-    AMDGPU::FeatureDot3Insts,
-    AMDGPU::FeatureDot4Insts,
-    AMDGPU::FeatureDot5Insts,
-    AMDGPU::FeatureDot6Insts,
-    AMDGPU::FeatureDot7Insts,
-    AMDGPU::FeatureDot8Insts,
-    AMDGPU::FeatureExtendedImageInsts,
-    AMDGPU::FeatureSMemRealTime,
-    AMDGPU::FeatureSMemTimeInst
-};
+constexpr unsigned FeaturesToCheck[] = {AMDGPU::FeatureGFX11Insts,
+                                        AMDGPU::FeatureGFX10Insts,
+                                        AMDGPU::FeatureGFX9Insts,
+                                        AMDGPU::FeatureGFX8Insts,
+                                        AMDGPU::FeatureDPP,
+                                        AMDGPU::Feature16BitInsts,
+                                        AMDGPU::FeatureDot1Insts,
+                                        AMDGPU::FeatureDot2Insts,
+                                        AMDGPU::FeatureDot3Insts,
+                                        AMDGPU::FeatureDot4Insts,
+                                        AMDGPU::FeatureDot5Insts,
+                                        AMDGPU::FeatureDot6Insts,
+                                        AMDGPU::FeatureDot7Insts,
+                                        AMDGPU::FeatureDot8Insts,
+                                        AMDGPU::FeatureExtendedImageInsts,
+                                        AMDGPU::FeatureSMemRealTime,
+                                        AMDGPU::FeatureSMemTimeInst};
 
 FeatureBitset expandImpliedFeatures(const FeatureBitset &Features) {
   FeatureBitset Result = Features;
diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h
index 29397e109706..9b2f52c1286e 100644
--- a/llvm/lib/Target/AMDGPU/SIDefines.h
+++ b/llvm/lib/Target/AMDGPU/SIDefines.h
@@ -1026,6 +1026,8 @@ enum Register_Flag : uint8_t {
 
 } // namespace AMDGPU
 
+// clang-format off
+
 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS                                0x00B028
 #define   S_00B028_VGPRS(x)                                           (((x) & 0x3F) << 0)
 #define   S_00B028_SGPRS(x)                                           (((x) & 0x0F) << 6)
@@ -1134,6 +1136,7 @@ enum Register_Flag : uint8_t {
 #define   G_00B848_FWD_PROGRESS(x)                                    (((x) >> 31) & 0x1)
 #define   C_00B848_FWD_PROGRESS                                       0x7FFFFFFF
 
+// clang-format on
 
 // Helpers for setting FLOAT_MODE
 #define FP_ROUND_ROUND_TO_NEAREST 0
-- 
GitLab


From 7de592b9f9f12f861cc1bdc667d6042569bc42a2 Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Tue, 12 Dec 2023 15:04:12 +0100
Subject: [PATCH 298/349] [LVI] Move bulk of getConstantRangeAtUse()
 implementation into Impl (NFC)

Make the layering here similar to all the other methods:
LazyValueInfoImpl implements the underlying API returning a
ValueLatticeElement, and then LazyValueInfo exposes this as a
ConstantRange publicly.
---
 llvm/lib/Analysis/LazyValueInfo.cpp | 95 ++++++++++++++++-------------
 1 file changed, 52 insertions(+), 43 deletions(-)

diff --git a/llvm/lib/Analysis/LazyValueInfo.cpp b/llvm/lib/Analysis/LazyValueInfo.cpp
index 90d900a13986..f9ffa6593832 100644
--- a/llvm/lib/Analysis/LazyValueInfo.cpp
+++ b/llvm/lib/Analysis/LazyValueInfo.cpp
@@ -453,6 +453,8 @@ public:
                                      BasicBlock *ToBB,
                                      Instruction *CxtI = nullptr);
 
+  ValueLatticeElement getValueAtUse(const Use &U);
+
   /// Complete flush all previously computed values
   void clear() {
     TheCache.clear();
@@ -1512,6 +1514,52 @@ getValueOnEdge(Value *V, BasicBlock *FromBB, BasicBlock *ToBB,
   return *Result;
 }
 
+ValueLatticeElement LazyValueInfoImpl::getValueAtUse(const Use &U) {
+  Value *V = U.get();
+  auto *CxtI = cast<Instruction>(U.getUser());
+  ValueLatticeElement VL = getValueInBlock(V, CxtI->getParent(), CxtI);
+
+  // Check whether the only (possibly transitive) use of the value is in a
+  // position where V can be constrained by a select or branch condition.
+  const Use *CurrU = &U;
+  // TODO: Increase limit?
+  const unsigned MaxUsesToInspect = 3;
+  for (unsigned I = 0; I < MaxUsesToInspect; ++I) {
+    std::optional<ValueLatticeElement> CondVal;
+    auto *CurrI = cast<Instruction>(CurrU->getUser());
+    if (auto *SI = dyn_cast<SelectInst>(CurrI)) {
+      // If the value is undef, a different value may be chosen in
+      // the select condition and at use.
+      if (!isGuaranteedNotToBeUndef(SI->getCondition(), AC))
+        break;
+      if (CurrU->getOperandNo() == 1)
+        CondVal = getValueFromCondition(V, SI->getCondition(), true);
+      else if (CurrU->getOperandNo() == 2)
+        CondVal = getValueFromCondition(V, SI->getCondition(), false);
+    } else if (auto *PHI = dyn_cast<PHINode>(CurrI)) {
+      // TODO: Use non-local query?
+      CondVal =
+          getEdgeValueLocal(V, PHI->getIncomingBlock(*CurrU), PHI->getParent());
+    }
+    if (CondVal)
+      VL = intersect(VL, *CondVal);
+
+    // Only follow one-use chain, to allow direct intersection of conditions.
+    // If there are multiple uses, we would have to intersect with the union of
+    // all conditions at different uses.
+    // Stop walking if we hit a non-speculatable instruction. Even if the
+    // result is only used under a specific condition, executing the
+    // instruction itself may cause side effects or UB already.
+    // This also disallows looking through phi nodes: If the phi node is part
+    // of a cycle, we might end up reasoning about values from different cycle
+    // iterations (PR60629).
+    if (!CurrI->hasOneUse() || !isSafeToSpeculativelyExecute(CurrI))
+      break;
+    CurrU = &*CurrI->use_begin();
+  }
+  return VL;
+}
+
 void LazyValueInfoImpl::threadEdge(BasicBlock *PredBB, BasicBlock *OldSucc,
                                    BasicBlock *NewSucc) {
   TheCache.threadEdgeImpl(OldSucc, NewSucc);
@@ -1633,49 +1681,10 @@ ConstantRange LazyValueInfo::getConstantRange(Value *V, Instruction *CxtI,
 
 ConstantRange LazyValueInfo::getConstantRangeAtUse(const Use &U,
                                                    bool UndefAllowed) {
-  Value *V = U.get();
-  ConstantRange CR =
-      getConstantRange(V, cast<Instruction>(U.getUser()), UndefAllowed);
-
-  // Check whether the only (possibly transitive) use of the value is in a
-  // position where V can be constrained by a select or branch condition.
-  const Use *CurrU = &U;
-  // TODO: Increase limit?
-  const unsigned MaxUsesToInspect = 3;
-  for (unsigned I = 0; I < MaxUsesToInspect; ++I) {
-    std::optional<ValueLatticeElement> CondVal;
-    auto *CurrI = cast<Instruction>(CurrU->getUser());
-    if (auto *SI = dyn_cast<SelectInst>(CurrI)) {
-      // If the value is undef, a different value may be chosen in
-      // the select condition and at use.
-      if (!isGuaranteedNotToBeUndef(SI->getCondition(), AC))
-        break;
-      if (CurrU->getOperandNo() == 1)
-        CondVal = getValueFromCondition(V, SI->getCondition(), true);
-      else if (CurrU->getOperandNo() == 2)
-        CondVal = getValueFromCondition(V, SI->getCondition(), false);
-    } else if (auto *PHI = dyn_cast<PHINode>(CurrI)) {
-      // TODO: Use non-local query?
-      CondVal =
-          getEdgeValueLocal(V, PHI->getIncomingBlock(*CurrU), PHI->getParent());
-    }
-    if (CondVal && CondVal->isConstantRange())
-      CR = CR.intersectWith(CondVal->getConstantRange());
-
-    // Only follow one-use chain, to allow direct intersection of conditions.
-    // If there are multiple uses, we would have to intersect with the union of
-    // all conditions at different uses.
-    // Stop walking if we hit a non-speculatable instruction. Even if the
-    // result is only used under a specific condition, executing the
-    // instruction itself may cause side effects or UB already.
-    // This also disallows looking through phi nodes: If the phi node is part
-    // of a cycle, we might end up reasoning about values from different cycle
-    // iterations (PR60629).
-    if (!CurrI->hasOneUse() || !isSafeToSpeculativelyExecute(CurrI))
-      break;
-    CurrU = &*CurrI->use_begin();
-  }
-  return CR;
+  auto *Inst = cast<Instruction>(U.getUser());
+  ValueLatticeElement Result =
+      getOrCreateImpl(Inst->getModule()).getValueAtUse(U);
+  return toConstantRange(Result, U->getType(), UndefAllowed);
 }
 
 /// Determine whether the specified value is known to be a
-- 
GitLab


From cb8690ff6fefecb15d73452899834d19b526e197 Mon Sep 17 00:00:00 2001
From: Orlando Cazalet-Hyams <orlando.hyams@sony.com>
Date: Tue, 12 Dec 2023 14:28:05 +0000
Subject: [PATCH 299/349] [RemoveDIs] Handle DPValues in LowerDbgDeclare
 (#73504)

The tests will become "live" once #74090 lands (see for more info).
---
 llvm/lib/Transforms/Utils/Local.cpp           | 47 ++++++++++++-------
 .../test/DebugInfo/ARM/lowerbdgdeclare_vla.ll |  1 +
 .../Generic/dbg-value-lower-linenos.ll        |  1 +
 llvm/test/DebugInfo/X86/array2.ll             |  1 +
 llvm/test/DebugInfo/X86/formal_parameter.ll   |  1 +
 .../DebugInfo/X86/instcombine-instrinsics.ll  |  1 +
 llvm/test/DebugInfo/duplicate_dbgvalue.ll     |  1 +
 llvm/test/DebugInfo/verify-di-preserve.ll     |  2 +
 .../dbg-scalable-store-fixed-frag.ll          |  1 +
 .../InstCombine/dbg-simplify-alloca-size.ll   |  1 +
 .../debuginfo-scalable-typesize.ll            |  1 +
 .../InstCombine/lifetime-no-null-opt.ll       |  1 +
 llvm/test/Transforms/InstCombine/lifetime.ll  |  1 +
 13 files changed, 43 insertions(+), 17 deletions(-)

diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp
index c19a8d103cfc..ff92abb77ac2 100644
--- a/llvm/lib/Transforms/Utils/Local.cpp
+++ b/llvm/lib/Transforms/Utils/Local.cpp
@@ -1724,9 +1724,11 @@ void llvm::ConvertDebugDeclareToDebugValue(DbgVariableIntrinsic *DII,
                           SI->getIterator());
 }
 
+namespace llvm {
 // RemoveDIs: duplicate the getDebugValueLoc method using DPValues instead of
-// dbg.value intrinsics.
-static DebugLoc getDebugValueLocDPV(DPValue *DPV) {
+// dbg.value intrinsics. In llvm namespace so that it overloads the
+// DbgVariableIntrinsic version.
+static DebugLoc getDebugValueLoc(DPValue *DPV) {
   // Original dbg.declare must have a location.
   const DebugLoc &DeclareLoc = DPV->getDebugLoc();
   MDNode *Scope = DeclareLoc.getScope();
@@ -1734,6 +1736,7 @@ static DebugLoc getDebugValueLocDPV(DPValue *DPV) {
   // Produce an unknown location with the correct scope / inlinedAt fields.
   return DILocation::get(DPV->getContext(), 0, 0, Scope, InlinedAt);
 }
+} // namespace llvm
 
 /// Inserts a llvm.dbg.value intrinsic before a load of an alloca'd value
 /// that has an associated llvm.dbg.declare intrinsic.
@@ -1770,7 +1773,7 @@ void llvm::ConvertDebugDeclareToDebugValue(DPValue *DPV, StoreInst *SI,
   auto *DIExpr = DPV->getExpression();
   Value *DV = SI->getValueOperand();
 
-  DebugLoc NewLoc = getDebugValueLocDPV(DPV);
+  DebugLoc NewLoc = getDebugValueLoc(DPV);
 
   if (!valueCoversEntireFragment(DV->getType(), DPV)) {
     // FIXME: If storing to a part of the variable described by the dbg.declare,
@@ -1842,7 +1845,7 @@ void llvm::ConvertDebugDeclareToDebugValue(DPValue *DPV, LoadInst *LI,
     return;
   }
 
-  DebugLoc NewLoc = getDebugValueLocDPV(DPV);
+  DebugLoc NewLoc = getDebugValueLoc(DPV);
 
   // We are now tracking the loaded value instead of the address. In the
   // future if multi-location support is added to the IR, it might be
@@ -1887,7 +1890,7 @@ void llvm::ConvertDebugDeclareToDebugValue(DPValue *DPV, PHINode *APN,
   BasicBlock *BB = APN->getParent();
   auto InsertionPt = BB->getFirstInsertionPt();
 
-  DebugLoc NewLoc = getDebugValueLocDPV(DPV);
+  DebugLoc NewLoc = getDebugValueLoc(DPV);
 
   // The block may be a catchswitch block, which does not have a valid
   // insertion point.
@@ -1903,17 +1906,24 @@ bool llvm::LowerDbgDeclare(Function &F) {
   bool Changed = false;
   DIBuilder DIB(*F.getParent(), /*AllowUnresolved*/ false);
   SmallVector<DbgDeclareInst *, 4> Dbgs;
-  for (auto &FI : F)
-    for (Instruction &BI : FI)
-      if (auto DDI = dyn_cast<DbgDeclareInst>(&BI))
+  SmallVector<DPValue *> DPVs;
+  for (auto &FI : F) {
+    for (Instruction &BI : FI) {
+      if (auto *DDI = dyn_cast<DbgDeclareInst>(&BI))
         Dbgs.push_back(DDI);
+      for (DPValue &DPV : BI.getDbgValueRange()) {
+        if (DPV.getType() == DPValue::LocationType::Declare)
+          DPVs.push_back(&DPV);
+      }
+    }
+  }
 
-  if (Dbgs.empty())
+  if (Dbgs.empty() && DPVs.empty())
     return Changed;
 
-  for (auto &I : Dbgs) {
-    DbgDeclareInst *DDI = I;
-    AllocaInst *AI = dyn_cast_or_null<AllocaInst>(DDI->getAddress());
+  auto LowerOne = [&](auto *DDI) {
+    AllocaInst *AI =
+        dyn_cast_or_null<AllocaInst>(DDI->getVariableLocationOp(0));
     // If this is an alloca for a scalar variable, insert a dbg.value
     // at each load and store to the alloca and erase the dbg.declare.
     // The dbg.values allow tracking a variable even if it is not
@@ -1921,7 +1931,7 @@ bool llvm::LowerDbgDeclare(Function &F) {
     // the stack slot (and at a lexical-scope granularity). Later
     // passes will attempt to elide the stack slot.
     if (!AI || isArray(AI) || isStructure(AI))
-      continue;
+      return;
 
     // A volatile load/store means that the alloca can't be elided anyway.
     if (llvm::any_of(AI->users(), [](User *U) -> bool {
@@ -1931,7 +1941,7 @@ bool llvm::LowerDbgDeclare(Function &F) {
             return SI->isVolatile();
           return false;
         }))
-      continue;
+      return;
 
     SmallVector<const Value *, 8> WorkList;
     WorkList.push_back(AI);
@@ -1963,11 +1973,14 @@ bool llvm::LowerDbgDeclare(Function &F) {
     }
     DDI->eraseFromParent();
     Changed = true;
-  }
+  };
+
+  for_each(Dbgs, LowerOne);
+  for_each(DPVs, LowerOne);
 
   if (Changed)
-  for (BasicBlock &BB : F)
-    RemoveRedundantDbgInstrs(&BB);
+    for (BasicBlock &BB : F)
+      RemoveRedundantDbgInstrs(&BB);
 
   return Changed;
 }
diff --git a/llvm/test/DebugInfo/ARM/lowerbdgdeclare_vla.ll b/llvm/test/DebugInfo/ARM/lowerbdgdeclare_vla.ll
index 0b3375d511eb..2a0ee339e52e 100644
--- a/llvm/test/DebugInfo/ARM/lowerbdgdeclare_vla.ll
+++ b/llvm/test/DebugInfo/ARM/lowerbdgdeclare_vla.ll
@@ -1,4 +1,5 @@
 ; RUN: opt  -passes=instcombine %s -S | FileCheck %s
+; RUN: opt --try-experimental-debuginfo-iterators  -passes=instcombine %s -S | FileCheck %s
 ;
 ; Generate me from:
 ; clang -cc1 -triple thumbv7-apple-ios7.0.0 -S -target-abi apcs-gnu -gdwarf-2 -Os test.c -o test.ll -emit-llvm
diff --git a/llvm/test/DebugInfo/Generic/dbg-value-lower-linenos.ll b/llvm/test/DebugInfo/Generic/dbg-value-lower-linenos.ll
index 7c3490996c8c..7fffa93008f6 100644
--- a/llvm/test/DebugInfo/Generic/dbg-value-lower-linenos.ll
+++ b/llvm/test/DebugInfo/Generic/dbg-value-lower-linenos.ll
@@ -1,4 +1,5 @@
 ; RUN: opt < %s -S -passes=mem2reg,instcombine | FileCheck %s
+; RUN: opt --try-experimental-debuginfo-iterators < %s -S -passes=mem2reg,instcombine | FileCheck %s
 
 ; The '%bar' alloca will be promoted to an SSA register by mem2reg: test that
 ; zero line number are assigned to the dbg.value intrinsics that are inserted
diff --git a/llvm/test/DebugInfo/X86/array2.ll b/llvm/test/DebugInfo/X86/array2.ll
index 17128e37d83e..8b386ca44c5f 100644
--- a/llvm/test/DebugInfo/X86/array2.ll
+++ b/llvm/test/DebugInfo/X86/array2.ll
@@ -13,6 +13,7 @@
 ; }
 ;
 ; RUN: opt %s -O2 -S -o - | FileCheck %s
+; RUN: opt --try-experimental-debuginfo-iterators %s -O2 -S -o - | FileCheck %s
 ; Test that we correctly lower dbg.declares for arrays.
 ;
 ; CHECK: define i32 @main
diff --git a/llvm/test/DebugInfo/X86/formal_parameter.ll b/llvm/test/DebugInfo/X86/formal_parameter.ll
index 21f86fbece83..553b20ff09ad 100644
--- a/llvm/test/DebugInfo/X86/formal_parameter.ll
+++ b/llvm/test/DebugInfo/X86/formal_parameter.ll
@@ -15,6 +15,7 @@ target triple = "x86_64-apple-macosx10.9.0"
 ; RUN: opt %s -O2 -S -o %t
 ; RUN: cat %t | FileCheck --check-prefix=LOWERING %s
 ; RUN: llc -filetype=obj %t -o - | llvm-dwarfdump -debug-info - | FileCheck %s
+; RUN: llc --try-experimental-debuginfo-iterators -filetype=obj %t -o - | llvm-dwarfdump -debug-info - | FileCheck %s
 ; Test that we only emit only one DW_AT_formal_parameter "map" for this function.
 ; rdar://problem/14874886
 ;
diff --git a/llvm/test/DebugInfo/X86/instcombine-instrinsics.ll b/llvm/test/DebugInfo/X86/instcombine-instrinsics.ll
index c25cbbffee1e..ff5e07318d1e 100644
--- a/llvm/test/DebugInfo/X86/instcombine-instrinsics.ll
+++ b/llvm/test/DebugInfo/X86/instcombine-instrinsics.ll
@@ -1,4 +1,5 @@
 ; RUN: opt %s -O2 -S -o - | FileCheck %s
+; RUN: opt --try-experimental-debuginfo-iterators %s -O2 -S -o - | FileCheck %s
 ; Verify that we emit the same intrinsic at most once.
 ; rdar://problem/13056109
 ;
diff --git a/llvm/test/DebugInfo/duplicate_dbgvalue.ll b/llvm/test/DebugInfo/duplicate_dbgvalue.ll
index 250d2b5a5f30..685e666b2ffb 100644
--- a/llvm/test/DebugInfo/duplicate_dbgvalue.ll
+++ b/llvm/test/DebugInfo/duplicate_dbgvalue.ll
@@ -1,4 +1,5 @@
 ; RUN: opt -passes=instcombine -S -o - < %s | FileCheck %s
+; RUN: opt --try-experimental-debuginfo-iterators -passes=instcombine -S -o - < %s | FileCheck %s
 
 ; CHECK-LABEL: %3 = load i32, ptr %i1_311
 ; CHECK: call void @llvm.dbg.value(metadata i32 %3
diff --git a/llvm/test/DebugInfo/verify-di-preserve.ll b/llvm/test/DebugInfo/verify-di-preserve.ll
index 46d17154ebf6..a2f1b1dd78dc 100644
--- a/llvm/test/DebugInfo/verify-di-preserve.ll
+++ b/llvm/test/DebugInfo/verify-di-preserve.ll
@@ -1,8 +1,10 @@
 ; RUN: opt %s -verify-debuginfo-preserve -passes=instcombine -disable-output 2>&1 | FileCheck --check-prefix=VERIFY %s
+; RUN: opt --try-experimental-debuginfo-iterators %s -verify-debuginfo-preserve -passes=instcombine -disable-output 2>&1 | FileCheck --check-prefix=VERIFY %s
 
 ; VERIFY: CheckModuleDebugify (original debuginfo):
 
 ; RUN: opt %s -verify-each-debuginfo-preserve -O2 -disable-output 2>&1 | FileCheck --check-prefix=VERIFY-EACH %s
+; RUN: opt %s  --try-experimental-debuginfo-iterators -verify-each-debuginfo-preserve -O2 -disable-output 2>&1 | FileCheck --check-prefix=VERIFY-EACH %s
 
 ; VERIFY-EACH: DeadArgumentEliminationPass
 ; VERIFY-EACH: GlobalDCEPass
diff --git a/llvm/test/Transforms/InstCombine/dbg-scalable-store-fixed-frag.ll b/llvm/test/Transforms/InstCombine/dbg-scalable-store-fixed-frag.ll
index f1f107c4bf77..54c096b42e49 100644
--- a/llvm/test/Transforms/InstCombine/dbg-scalable-store-fixed-frag.ll
+++ b/llvm/test/Transforms/InstCombine/dbg-scalable-store-fixed-frag.ll
@@ -2,6 +2,7 @@
 ; RUN: opt < %s -passes='instcombine' -S | FileCheck %s
 ; RUN: opt < %s -passes='instcombine' -S --try-experimental-debuginfo-iterators | FileCheck %s
 
+
 define i32 @foo(<vscale x 2 x i32> %x) {
 ; CHECK-LABEL: @foo(
 ; CHECK-NEXT:  entry:
diff --git a/llvm/test/Transforms/InstCombine/dbg-simplify-alloca-size.ll b/llvm/test/Transforms/InstCombine/dbg-simplify-alloca-size.ll
index 028b19fadf19..03e8e44109e6 100644
--- a/llvm/test/Transforms/InstCombine/dbg-simplify-alloca-size.ll
+++ b/llvm/test/Transforms/InstCombine/dbg-simplify-alloca-size.ll
@@ -1,4 +1,5 @@
 ; RUN: opt -S --passes=instcombine %s | FileCheck %s
+; RUN: opt --try-experimental-debuginfo-iterators -S --passes=instcombine %s | FileCheck %s
 
 ; https://github.com/llvm/llvm-project/issues/56807
 declare void @foo(ptr %pixels)
diff --git a/llvm/test/Transforms/InstCombine/debuginfo-scalable-typesize.ll b/llvm/test/Transforms/InstCombine/debuginfo-scalable-typesize.ll
index b2e78f1eff00..feea036519b8 100644
--- a/llvm/test/Transforms/InstCombine/debuginfo-scalable-typesize.ll
+++ b/llvm/test/Transforms/InstCombine/debuginfo-scalable-typesize.ll
@@ -1,4 +1,5 @@
 ; RUN: opt -passes=instcombine -S < %s | FileCheck %s
+; RUN: opt --try-experimental-debuginfo-iterators -passes=instcombine -S < %s | FileCheck %s
 
 ; This test is defending against a TypeSize message raised in the method
 ; `valueCoversEntireFragment` in Local.cpp because of an implicit cast from
diff --git a/llvm/test/Transforms/InstCombine/lifetime-no-null-opt.ll b/llvm/test/Transforms/InstCombine/lifetime-no-null-opt.ll
index 5e110c9d9438..1f85dd864600 100644
--- a/llvm/test/Transforms/InstCombine/lifetime-no-null-opt.ll
+++ b/llvm/test/Transforms/InstCombine/lifetime-no-null-opt.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+; RUN: opt --try-experimental-debuginfo-iterators < %s -passes=instcombine -S | FileCheck %s
 
 declare void @llvm.dbg.declare(metadata, metadata, metadata)
 declare void @llvm.lifetime.start.p0(i64, ptr nocapture)
diff --git a/llvm/test/Transforms/InstCombine/lifetime.ll b/llvm/test/Transforms/InstCombine/lifetime.ll
index e809e162a966..fa1c38b7bdd0 100644
--- a/llvm/test/Transforms/InstCombine/lifetime.ll
+++ b/llvm/test/Transforms/InstCombine/lifetime.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+; RUN: opt --try-experimental-debuginfo-iterators < %s -passes=instcombine -S | FileCheck %s
 
 declare void @llvm.dbg.declare(metadata, metadata, metadata)
 declare void @llvm.lifetime.start.p0(i64, ptr nocapture)
-- 
GitLab


From 1f5ee8078958338e1ad320704b8b658c399c2236 Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Tue, 12 Dec 2023 15:29:26 +0100
Subject: [PATCH 300/349] [LVI] Don't return optional from getEdgeValueLocal()
 (NFC)

The general convention inside LVI is that std::nullopt means that
a value has been pushed to the worklist. However, getEdgeValueLocal()
used it as an additional spelling for getOverdefined() instead.
---
 llvm/lib/Analysis/LazyValueInfo.cpp | 21 ++++++++-------------
 1 file changed, 8 insertions(+), 13 deletions(-)

diff --git a/llvm/lib/Analysis/LazyValueInfo.cpp b/llvm/lib/Analysis/LazyValueInfo.cpp
index f9ffa6593832..910f6b72afef 100644
--- a/llvm/lib/Analysis/LazyValueInfo.cpp
+++ b/llvm/lib/Analysis/LazyValueInfo.cpp
@@ -1301,12 +1301,9 @@ static ValueLatticeElement constantFoldUser(User *Usr, Value *Op,
   return ValueLatticeElement::getOverdefined();
 }
 
-/// Compute the value of Val on the edge BBFrom -> BBTo. Returns false if
-/// Val is not constrained on the edge.  Result is unspecified if return value
-/// is false.
-static std::optional<ValueLatticeElement> getEdgeValueLocal(Value *Val,
-                                                       BasicBlock *BBFrom,
-                                                       BasicBlock *BBTo) {
+/// Compute the value of Val on the edge BBFrom -> BBTo.
+static ValueLatticeElement getEdgeValueLocal(Value *Val, BasicBlock *BBFrom,
+                                             BasicBlock *BBTo) {
   // TODO: Handle more complex conditionals. If (v == 0 || v2 < 1) is false, we
   // know that v != 0.
   if (BranchInst *BI = dyn_cast<BranchInst>(BBFrom->getTerminator())) {
@@ -1380,7 +1377,7 @@ static std::optional<ValueLatticeElement> getEdgeValueLocal(Value *Val,
   if (SwitchInst *SI = dyn_cast<SwitchInst>(BBFrom->getTerminator())) {
     Value *Condition = SI->getCondition();
     if (!isa<IntegerType>(Val->getType()))
-      return std::nullopt;
+      return ValueLatticeElement::getOverdefined();
     bool ValUsesConditionAndMayBeFoldable = false;
     if (Condition != Val) {
       // Check if Val has Condition as an operand.
@@ -1388,7 +1385,7 @@ static std::optional<ValueLatticeElement> getEdgeValueLocal(Value *Val,
         ValUsesConditionAndMayBeFoldable = isOperationFoldable(Usr) &&
             usesOperand(Usr, Condition);
       if (!ValUsesConditionAndMayBeFoldable)
-        return std::nullopt;
+        return ValueLatticeElement::getOverdefined();
     }
     assert((Condition == Val || ValUsesConditionAndMayBeFoldable) &&
            "Condition != Val nor Val doesn't use Condition");
@@ -1406,7 +1403,7 @@ static std::optional<ValueLatticeElement> getEdgeValueLocal(Value *Val,
         ValueLatticeElement EdgeLatticeVal =
             constantFoldUser(Usr, Condition, CaseValue, DL);
         if (EdgeLatticeVal.isOverdefined())
-          return std::nullopt;
+          return ValueLatticeElement::getOverdefined();
         EdgeVal = EdgeLatticeVal.getConstantRange();
       }
       if (DefaultCase) {
@@ -1423,7 +1420,7 @@ static std::optional<ValueLatticeElement> getEdgeValueLocal(Value *Val,
     }
     return ValueLatticeElement::getRange(std::move(EdgesVals));
   }
-  return std::nullopt;
+  return ValueLatticeElement::getOverdefined();
 }
 
 /// Compute the value of Val on the edge BBFrom -> BBTo or the value at
@@ -1435,9 +1432,7 @@ LazyValueInfoImpl::getEdgeValue(Value *Val, BasicBlock *BBFrom,
   if (Constant *VC = dyn_cast<Constant>(Val))
     return ValueLatticeElement::get(VC);
 
-  ValueLatticeElement LocalResult =
-      getEdgeValueLocal(Val, BBFrom, BBTo)
-          .value_or(ValueLatticeElement::getOverdefined());
+  ValueLatticeElement LocalResult = getEdgeValueLocal(Val, BBFrom, BBTo);
   if (hasSingleValue(LocalResult))
     // Can't get any more precise here
     return LocalResult;
-- 
GitLab


From 10582cbf2e967f5886ec674ca79dc65c6f0f03f7 Mon Sep 17 00:00:00 2001
From: Louis Dionne <ldionne.2@gmail.com>
Date: Tue, 12 Dec 2023 09:32:27 -0500
Subject: [PATCH 301/349] [libc++] Fix incorrectly-placed attribute

---
 libcxx/include/typeindex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libcxx/include/typeindex b/libcxx/include/typeindex
index a3571e2ea04a..36bf90722c21 100644
--- a/libcxx/include/typeindex
+++ b/libcxx/include/typeindex
@@ -70,8 +70,8 @@ public:
     _LIBCPP_HIDE_FROM_ABI
     bool operator==(const type_index& __y) const _NOEXCEPT
         {return *__t_ == *__y.__t_;}
-    _LIBCPP_HIDE_FROM_ABI
 #if _LIBCPP_STD_VER <= 17
+    _LIBCPP_HIDE_FROM_ABI
     bool operator!=(const type_index& __y) const _NOEXCEPT
         {return *__t_ != *__y.__t_;}
 #endif
-- 
GitLab


From cd138fddf1b52a43108376371ad1c38585aaa4e2 Mon Sep 17 00:00:00 2001
From: Piotr Sobczak <piotr.sobczak@amd.com>
Date: Tue, 12 Dec 2023 15:38:06 +0100
Subject: [PATCH 302/349] [AMDGPU] Turn off clang-format in moveToVALU (#75188)

---
 llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index dda54a0929c1..42eb4fa55ed5 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -5157,6 +5157,9 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
   return true;
 }
 
+// It is more readable to list mapped opcodes on the same line.
+// clang-format off
+
 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) const {
   switch (MI.getOpcode()) {
   default: return AMDGPU::INSTRUCTION_LIST_END;
@@ -5296,6 +5299,8 @@ unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) const {
       "Unexpected scalar opcode without corresponding vector one!");
 }
 
+// clang-format on
+
 void SIInstrInfo::insertScratchExecCopy(MachineFunction &MF,
                                         MachineBasicBlock &MBB,
                                         MachineBasicBlock::iterator MBBI,
-- 
GitLab


From 87c686700f68ce24191f027082ef5fb9a654e9d8 Mon Sep 17 00:00:00 2001
From: OCHyams <orlando.hyams@sony.com>
Date: Tue, 12 Dec 2023 14:41:01 +0000
Subject: [PATCH 303/349] Revert "[RemoveDIs][NFC] Find DPValues using
 findDbgDeclares  (#73500)"

This reverts commit 17b8f87f76365e65350ec3f7f982b21b8d895598.

Buildbot: https://lab.llvm.org/buildbot/#/builders/77/builds/32927
---
 llvm/include/llvm/IR/DebugInfo.h              |  3 +-
 .../include/llvm/IR/DebugProgramInstruction.h |  3 --
 llvm/lib/IR/DebugInfo.cpp                     | 42 ++++++++++++-------
 3 files changed, 27 insertions(+), 21 deletions(-)

diff --git a/llvm/include/llvm/IR/DebugInfo.h b/llvm/include/llvm/IR/DebugInfo.h
index 36ef77f9505b..5ed423bfd1c1 100644
--- a/llvm/include/llvm/IR/DebugInfo.h
+++ b/llvm/include/llvm/IR/DebugInfo.h
@@ -40,8 +40,7 @@ class Module;
 
 /// Finds dbg.declare intrinsics declaring local variables as living in the
 /// memory that 'V' points to.
-void findDbgDeclares(SmallVectorImpl<DbgDeclareInst *> &DbgUsers, Value *V,
-                     SmallVectorImpl<DPValue *> *DPValues = nullptr);
+void findDbgDeclares(SmallVectorImpl<DbgDeclareInst *> &DbgUsers, Value *V);
 
 /// Finds the llvm.dbg.value intrinsics describing a value.
 void findDbgValues(SmallVectorImpl<DbgValueInst *> &DbgValues,
diff --git a/llvm/include/llvm/IR/DebugProgramInstruction.h b/llvm/include/llvm/IR/DebugProgramInstruction.h
index 8230070343e0..f73a6237a477 100644
--- a/llvm/include/llvm/IR/DebugProgramInstruction.h
+++ b/llvm/include/llvm/IR/DebugProgramInstruction.h
@@ -97,9 +97,6 @@ public:
   enum class LocationType {
     Declare,
     Value,
-
-    End, ///< Marks the end of the concrete types.
-    Any, ///< To indicate all LocationTypes in searches.
   };
   /// Classification of the debug-info record that this DPValue represents.
   /// Essentially, "is this a dbg.value or dbg.declare?". dbg.declares are not
diff --git a/llvm/lib/IR/DebugInfo.cpp b/llvm/lib/IR/DebugInfo.cpp
index eab05eed428e..b3cc9996ace4 100644
--- a/llvm/lib/IR/DebugInfo.cpp
+++ b/llvm/lib/IR/DebugInfo.cpp
@@ -44,10 +44,28 @@ using namespace llvm;
 using namespace llvm::at;
 using namespace llvm::dwarf;
 
-template <typename IntrinsicT,
-          DPValue::LocationType Type = DPValue::LocationType::Any>
-static void findDbgIntrinsics(SmallVectorImpl<IntrinsicT *> &Result, Value *V,
-                              SmallVectorImpl<DPValue *> *DPValues) {
+void llvm::findDbgDeclares(SmallVectorImpl<DbgDeclareInst *> &DbgUsers,
+                           Value *V) {
+  // This function is hot. Check whether the value has any metadata to avoid a
+  // DenseMap lookup.
+  if (!V->isUsedByMetadata())
+    return;
+  auto *L = LocalAsMetadata::getIfExists(V);
+  if (!L)
+    return;
+  auto *MDV = MetadataAsValue::getIfExists(V->getContext(), L);
+  if (!MDV)
+    return;
+
+  for (User *U : MDV->users()) {
+    if (auto *DDI = dyn_cast<DbgDeclareInst>(U))
+      DbgUsers.push_back(DDI);
+  }
+}
+
+template <typename IntrinsicT>
+static void findDbgIntrinsics(SmallVectorImpl<IntrinsicT *> &Result,
+                              Value *V, SmallVectorImpl<DPValue *> *DPValues) {
   // This function is hot. Check whether the value has any metadata to avoid a
   // DenseMap lookup.
   if (!V->isUsedByMetadata())
@@ -76,7 +94,7 @@ static void findDbgIntrinsics(SmallVectorImpl<IntrinsicT *> &Result, Value *V,
     // Get DPValues that use this as a single value.
     if (LocalAsMetadata *L = dyn_cast<LocalAsMetadata>(MD)) {
       for (DPValue *DPV : L->getAllDPValueUsers()) {
-        if (Type == DPValue::LocationType::Any || DPV->getType() == Type)
+        if (DPV->getType() == DPValue::LocationType::Value)
           DPValues->push_back(DPV);
       }
     }
@@ -90,29 +108,21 @@ static void findDbgIntrinsics(SmallVectorImpl<IntrinsicT *> &Result, Value *V,
         continue;
       DIArgList *DI = cast<DIArgList>(AL);
       for (DPValue *DPV : DI->getAllDPValueUsers())
-        if (Type == DPValue::LocationType::Any || DPV->getType() == Type)
+        if (DPV->getType() == DPValue::LocationType::Value)
           if (EncounteredDPValues.insert(DPV).second)
             DPValues->push_back(DPV);
     }
   }
 }
 
-void llvm::findDbgDeclares(SmallVectorImpl<DbgDeclareInst *> &DbgUsers,
-                           Value *V, SmallVectorImpl<DPValue *> *DPValues) {
-  findDbgIntrinsics<DbgDeclareInst, DPValue::LocationType::Declare>(DbgUsers, V,
-                                                                    DPValues);
-}
-
 void llvm::findDbgValues(SmallVectorImpl<DbgValueInst *> &DbgValues,
                          Value *V, SmallVectorImpl<DPValue *> *DPValues) {
-  findDbgIntrinsics<DbgValueInst, DPValue::LocationType::Value>(DbgValues, V,
-                                                                DPValues);
+  findDbgIntrinsics<DbgValueInst>(DbgValues, V, DPValues);
 }
 
 void llvm::findDbgUsers(SmallVectorImpl<DbgVariableIntrinsic *> &DbgUsers,
                         Value *V, SmallVectorImpl<DPValue *> *DPValues) {
-  findDbgIntrinsics<DbgVariableIntrinsic, DPValue::LocationType::Any>(
-      DbgUsers, V, DPValues);
+  findDbgIntrinsics<DbgVariableIntrinsic>(DbgUsers, V, DPValues);
 }
 
 DISubprogram *llvm::getDISubprogram(const MDNode *Scope) {
-- 
GitLab


From 6a664674990094c1b5d2e717256f08cb04485899 Mon Sep 17 00:00:00 2001
From: Jakub Mazurkiewicz <mazkuba3@gmail.com>
Date: Tue, 12 Dec 2023 15:45:14 +0100
Subject: [PATCH 304/349] [libc++] P2770R0: Stashing stashing iterators for
 proper flattening (#66033)

- Partially implements P2770R0 (http://wg21.link/p2770)
- Fixes https://wg21.link/LWG3698, https://wg21.link/LWG3700, and https://wg21.link/LWG3791
- join_with_view hasn't been done yet since this type isn't implemented yet
- Rename tuple test directory to match the standard (which changed in P2770R0)
- Rename join_view test directory to match the standard
---
 libcxx/docs/Status/Cxx23.rst                  |   1 +
 libcxx/docs/Status/Cxx23Papers.csv            |   2 +-
 libcxx/docs/UsingLibcxx.rst                   |   1 -
 libcxx/include/CMakeLists.txt                 |   1 +
 libcxx/include/__ranges/join_view.h           | 138 +++++++++++-------
 libcxx/include/__utility/as_lvalue.h          |  37 +++++
 libcxx/include/module.modulemap.in            |   1 +
 libcxx/include/regex                          |   8 +
 libcxx/include/utility                        |   1 +
 libcxx/modules/std/ranges.inc                 |   2 -
 .../as-lvalue.lifetimebound.verify.cpp        |  22 +++
 .../range.adaptor.helpers/as-lvalue.pass.cpp  |  40 +++++
 .../tuple-for-each.pass.cpp                   |   0
 .../ctor.parent.outer.pass.cpp                |  65 +++++++++
 .../range.join.iterator/ctor.parent.pass.cpp  |  36 +++++
 .../range.join/range.join.iterator/types.h    | 114 +++++++++++++++
 .../segmented_iterator.compile.pass.cpp       |   1 -
 .../alg.copy/ranges.copy.segmented.pass.cpp   |   2 -
 .../alg.copy/ranges.copy_backward.pass.cpp    |   2 -
 .../ranges.copy_backward.segmented.pass.cpp   |   2 -
 .../alg.copy/ranges.copy_n.segmented.pass.cpp |   2 -
 .../alg.move/ranges.move.segmented.pass.cpp   |   2 -
 .../ranges.move_backward.segmented.pass.cpp   |   2 -
 .../cpo.compile.pass.cpp                      |   2 -
 ...erator_robust_against_adl.compile.pass.cpp |   1 -
 .../iterator/ctor.parent.outer.pass.cpp       |  57 --------
 .../adaptor.pass.cpp                          |   1 -
 .../base.pass.cpp                             |   1 -
 .../begin.pass.cpp                            |  31 +++-
 .../ctad.compile.pass.cpp                     |   1 -
 .../ctad.verify.cpp                           |   1 -
 .../ctor.default.pass.cpp                     |   1 -
 .../ctor.view.pass.cpp                        |   1 -
 .../end.pass.cpp                              |  22 +--
 .../general.pass.cpp                          |   1 -
 .../range.join/lwg3698.pass.cpp               |  33 +++++
 .../range.join.iterator}/arrow.pass.cpp       |   1 -
 .../ctor.default.pass.cpp                     |  16 +-
 .../range.join.iterator}/ctor.other.pass.cpp  |   3 +-
 .../range.join.iterator}/decrement.pass.cpp   |  13 +-
 .../range.join.iterator}/eq.pass.cpp          |   7 +-
 .../range.join.iterator}/increment.pass.cpp   |  18 ++-
 .../range.join.iterator}/iter.move.pass.cpp   |   1 -
 .../range.join.iterator}/iter.swap.pass.cpp   |   1 -
 .../member_types.compile.pass.cpp             |   1 -
 .../range.join.iterator}/star.pass.cpp        |   1 -
 .../ctor.default.pass.cpp                     |   1 -
 .../range.join.sentinel}/ctor.other.pass.cpp  |   1 -
 .../range.join.sentinel}/ctor.parent.pass.cpp |   1 -
 .../range.join.sentinel}/eq.pass.cpp          |  19 ++-
 .../{range.join.view => range.join}/types.h   |  66 ++++++++-
 ...rator_concept_conformance.compile.pass.cpp |   4 +-
 .../std/re/re.iter/re.regiter/types.pass.cpp  |   4 +
 ...rator_concept_conformance.compile.pass.cpp |   4 +-
 .../std/re/re.iter/re.tokiter/types.pass.cpp  |   4 +
 55 files changed, 605 insertions(+), 196 deletions(-)
 create mode 100644 libcxx/include/__utility/as_lvalue.h
 create mode 100644 libcxx/test/libcxx/ranges/range.adaptors/range.adaptor.helpers/as-lvalue.lifetimebound.verify.cpp
 create mode 100644 libcxx/test/libcxx/ranges/range.adaptors/range.adaptor.helpers/as-lvalue.pass.cpp
 rename libcxx/test/libcxx/ranges/range.adaptors/{range.adaptor.tuple => range.adaptor.helpers}/tuple-for-each.pass.cpp (100%)
 create mode 100644 libcxx/test/libcxx/ranges/range.adaptors/range.join/range.join.iterator/ctor.parent.outer.pass.cpp
 create mode 100644 libcxx/test/libcxx/ranges/range.adaptors/range.join/range.join.iterator/ctor.parent.pass.cpp
 create mode 100644 libcxx/test/libcxx/ranges/range.adaptors/range.join/range.join.iterator/types.h
 delete mode 100644 libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/ctor.parent.outer.pass.cpp
 rename libcxx/test/std/ranges/range.adaptors/{range.join.view => range.join}/adaptor.pass.cpp (99%)
 rename libcxx/test/std/ranges/range.adaptors/{range.join.view => range.join}/base.pass.cpp (98%)
 rename libcxx/test/std/ranges/range.adaptors/{range.join.view => range.join}/begin.pass.cpp (83%)
 rename libcxx/test/std/ranges/range.adaptors/{range.join.view => range.join}/ctad.compile.pass.cpp (98%)
 rename libcxx/test/std/ranges/range.adaptors/{range.join.view => range.join}/ctad.verify.cpp (97%)
 rename libcxx/test/std/ranges/range.adaptors/{range.join.view => range.join}/ctor.default.pass.cpp (97%)
 rename libcxx/test/std/ranges/range.adaptors/{range.join.view => range.join}/ctor.view.pass.cpp (97%)
 rename libcxx/test/std/ranges/range.adaptors/{range.join.view => range.join}/end.pass.cpp (95%)
 rename libcxx/test/std/ranges/range.adaptors/{range.join.view => range.join}/general.pass.cpp (98%)
 create mode 100644 libcxx/test/std/ranges/range.adaptors/range.join/lwg3698.pass.cpp
 rename libcxx/test/std/ranges/range.adaptors/{range.join.view/iterator => range.join/range.join.iterator}/arrow.pass.cpp (99%)
 rename libcxx/test/std/ranges/range.adaptors/{range.join.view/iterator => range.join/range.join.iterator}/ctor.default.pass.cpp (70%)
 rename libcxx/test/std/ranges/range.adaptors/{range.join.view/iterator => range.join/range.join.iterator}/ctor.other.pass.cpp (97%)
 rename libcxx/test/std/ranges/range.adaptors/{range.join.view/iterator => range.join/range.join.iterator}/decrement.pass.cpp (90%)
 rename libcxx/test/std/ranges/range.adaptors/{range.join.view/iterator => range.join/range.join.iterator}/eq.pass.cpp (89%)
 rename libcxx/test/std/ranges/range.adaptors/{range.join.view/iterator => range.join/range.join.iterator}/increment.pass.cpp (94%)
 rename libcxx/test/std/ranges/range.adaptors/{range.join.view/iterator => range.join/range.join.iterator}/iter.move.pass.cpp (98%)
 rename libcxx/test/std/ranges/range.adaptors/{range.join.view/iterator => range.join/range.join.iterator}/iter.swap.pass.cpp (98%)
 rename libcxx/test/std/ranges/range.adaptors/{range.join.view/iterator => range.join/range.join.iterator}/member_types.compile.pass.cpp (99%)
 rename libcxx/test/std/ranges/range.adaptors/{range.join.view/iterator => range.join/range.join.iterator}/star.pass.cpp (97%)
 rename libcxx/test/std/ranges/range.adaptors/{range.join.view/sentinel => range.join/range.join.sentinel}/ctor.default.pass.cpp (95%)
 rename libcxx/test/std/ranges/range.adaptors/{range.join.view/sentinel => range.join/range.join.sentinel}/ctor.other.pass.cpp (99%)
 rename libcxx/test/std/ranges/range.adaptors/{range.join.view/sentinel => range.join/range.join.sentinel}/ctor.parent.pass.cpp (97%)
 rename libcxx/test/std/ranges/range.adaptors/{range.join.view/sentinel => range.join/range.join.sentinel}/eq.pass.cpp (81%)
 rename libcxx/test/std/ranges/range.adaptors/{range.join.view => range.join}/types.h (88%)

diff --git a/libcxx/docs/Status/Cxx23.rst b/libcxx/docs/Status/Cxx23.rst
index 839640a7c7e8..3e6e33f08c7c 100644
--- a/libcxx/docs/Status/Cxx23.rst
+++ b/libcxx/docs/Status/Cxx23.rst
@@ -45,6 +45,7 @@ Paper Status
       clang doesn't issue a diagnostic for deprecated using template declarations.
    .. [#note-P2520R0] P2520R0: Libc++ implemented this paper as a DR in C++20 as well.
    .. [#note-P2711R1] P2711R1: ``join_with_view`` hasn't been done yet since this type isn't implemented yet.
+   .. [#note-P2770R0] P2770R0: ``join_with_view`` hasn't been done yet since this type isn't implemented yet.
    .. [#note-P2693R1] P2693R1: The formatter for ``std::thread::id`` is implemented.
       The formatter for ``stacktrace`` is not implemented, since ``stacktrace`` is
       not implemented yet.
diff --git a/libcxx/docs/Status/Cxx23Papers.csv b/libcxx/docs/Status/Cxx23Papers.csv
index e03cbff2a08b..b4f915d37d00 100644
--- a/libcxx/docs/Status/Cxx23Papers.csv
+++ b/libcxx/docs/Status/Cxx23Papers.csv
@@ -104,7 +104,7 @@
 "`P2708R1 <https://wg21.link/P2708R1>`__","LWG", "No Further Fundamentals TSes", "November 2022","|Nothing to do|","",""
 "","","","","","",""
 "`P0290R4 <https://wg21.link/P0290R4>`__","LWG", "``apply()`` for ``synchronized_value<T>``","February 2023","","","|concurrency TS|"
-"`P2770R0 <https://wg21.link/P2770R0>`__","LWG", "Stashing stashing ``iterators`` for proper flattening","February 2023","|In Progress|","","|ranges|"
+"`P2770R0 <https://wg21.link/P2770R0>`__","LWG", "Stashing stashing ``iterators`` for proper flattening","February 2023","|Partial| [#note-P2770R0]_","","|ranges|"
 "`P2164R9 <https://wg21.link/P2164R9>`__","LWG", "``views::enumerate``","February 2023","","","|ranges|"
 "`P2711R1 <https://wg21.link/P2711R1>`__","LWG", "Making multi-param constructors of ``views`` ``explicit``","February 2023","|In Progress| [#note-P2711R1]_","","|ranges|"
 "`P2609R3 <https://wg21.link/P2609R3>`__","LWG", "Relaxing Ranges Just A Smidge","February 2023","","","|ranges|"
diff --git a/libcxx/docs/UsingLibcxx.rst b/libcxx/docs/UsingLibcxx.rst
index cdab2c36eab7..8d9f795da977 100644
--- a/libcxx/docs/UsingLibcxx.rst
+++ b/libcxx/docs/UsingLibcxx.rst
@@ -50,7 +50,6 @@ when ``-fexperimental-library`` is passed:
 * ``std::stop_token``, ``std::stop_source`` and ``std::stop_callback``
 * ``std::jthread``
 * ``std::chrono::tzdb`` and related time zone functionality
-* ``std::ranges::join_view``
 
 .. warning::
   Experimental libraries are experimental.
diff --git a/libcxx/include/CMakeLists.txt b/libcxx/include/CMakeLists.txt
index d8faf6467b79..533b7ac9103a 100644
--- a/libcxx/include/CMakeLists.txt
+++ b/libcxx/include/CMakeLists.txt
@@ -837,6 +837,7 @@ set(files
   __type_traits/void_t.h
   __undef_macros
   __utility/as_const.h
+  __utility/as_lvalue.h
   __utility/auto_cast.h
   __utility/cmp.h
   __utility/convert_to_integral.h
diff --git a/libcxx/include/__ranges/join_view.h b/libcxx/include/__ranges/join_view.h
index e6240dfd2580..f80beda33b11 100644
--- a/libcxx/include/__ranges/join_view.h
+++ b/libcxx/include/__ranges/join_view.h
@@ -32,6 +32,8 @@
 #include <__ranges/view_interface.h>
 #include <__type_traits/common_type.h>
 #include <__type_traits/maybe_const.h>
+#include <__utility/as_lvalue.h>
+#include <__utility/empty.h>
 #include <__utility/forward.h>
 #include <optional>
 
@@ -41,10 +43,7 @@
 
 _LIBCPP_BEGIN_NAMESPACE_STD
 
-// Note: `join_view` is still marked experimental because there is an ABI-breaking change that affects `join_view` in
-// the pipeline (https://isocpp.org/files/papers/D2770R0.html).
-// TODO: make `join_view` non-experimental once D2770 is implemented.
-#if _LIBCPP_STD_VER >= 20 && defined(_LIBCPP_ENABLE_EXPERIMENTAL)
+#if _LIBCPP_STD_VER >= 20
 
 namespace ranges {
   template<class>
@@ -84,11 +83,16 @@ namespace ranges {
     template <class>
     friend struct std::__segmented_iterator_traits;
 
-    static constexpr bool _UseCache = !is_reference_v<_InnerRange>;
-    using _Cache = _If<_UseCache, __non_propagating_cache<remove_cvref_t<_InnerRange>>, __empty_cache>;
-    _LIBCPP_NO_UNIQUE_ADDRESS _Cache __cache_;
     _LIBCPP_NO_UNIQUE_ADDRESS _View __base_ = _View();
 
+    static constexpr bool _UseOuterCache = !forward_range<_View>;
+    using _OuterCache = _If<_UseOuterCache, __non_propagating_cache<iterator_t<_View>>, __empty_cache>;
+    _LIBCPP_NO_UNIQUE_ADDRESS _OuterCache __outer_;
+
+    static constexpr bool _UseInnerCache = !is_reference_v<_InnerRange>;
+    using _InnerCache = _If<_UseInnerCache, __non_propagating_cache<remove_cvref_t<_InnerRange>>, __empty_cache>;
+    _LIBCPP_NO_UNIQUE_ADDRESS _InnerCache __inner_;
+
   public:
     _LIBCPP_HIDE_FROM_ABI
     join_view() requires default_initializable<_View> = default;
@@ -105,16 +109,22 @@ namespace ranges {
 
     _LIBCPP_HIDE_FROM_ABI
     constexpr auto begin() {
-      constexpr bool __use_const = __simple_view<_View> &&
-                                   is_reference_v<range_reference_t<_View>>;
-      return __iterator<__use_const>{*this, ranges::begin(__base_)};
+      if constexpr (forward_range<_View>) {
+        constexpr bool __use_const = __simple_view<_View> &&
+                                     is_reference_v<range_reference_t<_View>>;
+        return __iterator<__use_const>{*this, ranges::begin(__base_)};
+      } else {
+        __outer_.__emplace(ranges::begin(__base_));
+        return __iterator<false>{*this};
+      }
     }
 
     template<class _V2 = _View>
     _LIBCPP_HIDE_FROM_ABI
     constexpr auto begin() const
-      requires input_range<const _V2> &&
-               is_reference_v<range_reference_t<const _V2>>
+      requires forward_range<const _V2> &&
+               is_reference_v<range_reference_t<const _V2>> &&
+               input_range<range_reference_t<const _V2>>
     {
       return __iterator<true>{*this, ranges::begin(__base_)};
     }
@@ -134,13 +144,12 @@ namespace ranges {
     template<class _V2 = _View>
     _LIBCPP_HIDE_FROM_ABI
     constexpr auto end() const
-      requires input_range<const _V2> &&
-               is_reference_v<range_reference_t<const _V2>>
+      requires forward_range<const _V2> &&
+               is_reference_v<range_reference_t<const _V2>> &&
+               input_range<range_reference_t<const _V2>>
     {
       using _ConstInnerRange = range_reference_t<const _View>;
-      if constexpr (forward_range<const _View> &&
-                    is_reference_v<_ConstInnerRange> &&
-                    forward_range<_ConstInnerRange> &&
+      if constexpr (forward_range<_ConstInnerRange> &&
                     common_range<const _View> &&
                     common_range<_ConstInnerRange>) {
         return __iterator<true>{*this, ranges::end(__base_)};
@@ -154,12 +163,12 @@ namespace ranges {
     requires view<_View> && input_range<range_reference_t<_View>>
   template<bool _Const>
   struct join_view<_View>::__sentinel {
-  template<bool>
+  private:
+    template <bool>
     friend struct __sentinel;
 
-  private:
-    using _Parent = __maybe_const<_Const, join_view<_View>>;
-    using _Base = __maybe_const<_Const, _View>;
+    using _Parent            = __maybe_const<_Const, join_view>;
+    using _Base              = __maybe_const<_Const, _View>;
     sentinel_t<_Base> __end_ = sentinel_t<_Base>();
 
   public:
@@ -179,7 +188,7 @@ namespace ranges {
       requires sentinel_for<sentinel_t<_Base>, iterator_t<__maybe_const<_OtherConst, _View>>>
     _LIBCPP_HIDE_FROM_ABI
     friend constexpr bool operator==(const __iterator<_OtherConst>& __x, const __sentinel& __y) {
-      return __x.__outer_ == __y.__end_;
+      return __x.__get_outer() == __y.__end_;
     }
   };
 
@@ -191,9 +200,7 @@ namespace ranges {
   template<bool _Const>
   struct join_view<_View>::__iterator final
     : public __join_view_iterator_category<__maybe_const<_Const, _View>> {
-
-    template<bool>
-    friend struct __iterator;
+    friend join_view;
 
     template <class>
     friend struct std::__segmented_iterator_traits;
@@ -207,23 +214,25 @@ namespace ranges {
     using _Inner = iterator_t<range_reference_t<_Base>>;
     using _InnerRange = range_reference_t<_View>;
 
+    static_assert(!_Const || forward_range<_Base>, "Const can only be true when Base models forward_range.");
+
     static constexpr bool __ref_is_glvalue = is_reference_v<range_reference_t<_Base>>;
 
-  public:
-    _Outer __outer_ = _Outer();
+    static constexpr bool _OuterPresent = forward_range<_Base>;
+    using _OuterType                    = _If<_OuterPresent, _Outer, std::__empty>;
+    _LIBCPP_NO_UNIQUE_ADDRESS _OuterType __outer_ = _OuterType();
 
-  private:
     optional<_Inner> __inner_;
-    _Parent *__parent_ = nullptr;
+    _Parent* __parent_ = nullptr;
 
     _LIBCPP_HIDE_FROM_ABI
     constexpr void __satisfy() {
-      for (; __outer_ != ranges::end(__parent_->__base_); ++__outer_) {
-        auto&& __inner = [&]() -> auto&& {
+      for (; __get_outer() != ranges::end(__parent_->__base_); ++__get_outer()) {
+        auto&& __inner = [this]() -> auto&& {
           if constexpr (__ref_is_glvalue)
-            return *__outer_;
+            return *__get_outer();
           else
-            return __parent_->__cache_.__emplace_from([&]() -> decltype(auto) { return *__outer_; });
+            return __parent_->__inner_.__emplace_from([&]() -> decltype(auto) { return *__get_outer(); });
         }();
         __inner_ = ranges::begin(__inner);
         if (*__inner_ != ranges::end(__inner))
@@ -234,8 +243,37 @@ namespace ranges {
         __inner_.reset();
     }
 
+    _LIBCPP_HIDE_FROM_ABI constexpr _Outer& __get_outer() {
+      if constexpr (forward_range<_Base>) {
+        return __outer_;
+      } else {
+        return *__parent_->__outer_;
+      }
+    }
+
+    _LIBCPP_HIDE_FROM_ABI constexpr const _Outer& __get_outer() const {
+      if constexpr (forward_range<_Base>) {
+        return __outer_;
+      } else {
+        return *__parent_->__outer_;
+      }
+    }
+
+    _LIBCPP_HIDE_FROM_ABI constexpr __iterator(_Parent& __parent, _Outer __outer)
+      requires forward_range<_Base>
+        : __outer_(std::move(__outer)), __parent_(std::addressof(__parent)) {
+      __satisfy();
+    }
+
+    _LIBCPP_HIDE_FROM_ABI constexpr explicit __iterator(_Parent& __parent)
+      requires(!forward_range<_Base>)
+        : __parent_(std::addressof(__parent)) {
+      __satisfy();
+    }
+
     _LIBCPP_HIDE_FROM_ABI constexpr __iterator(_Parent* __parent, _Outer __outer, _Inner __inner)
-      : __outer_(std::move(__outer)), __inner_(std::move(__inner)), __parent_(__parent) {}
+      requires forward_range<_Base>
+        : __outer_(std::move(__outer)), __inner_(std::move(__inner)), __parent_(__parent) {}
 
   public:
     using iterator_concept = _If<
@@ -254,15 +292,7 @@ namespace ranges {
     using difference_type = common_type_t<
       range_difference_t<_Base>, range_difference_t<range_reference_t<_Base>>>;
 
-    _LIBCPP_HIDE_FROM_ABI
-    __iterator() requires default_initializable<_Outer> = default;
-
-    _LIBCPP_HIDE_FROM_ABI
-    constexpr __iterator(_Parent& __parent, _Outer __outer)
-      : __outer_(std::move(__outer))
-      , __parent_(std::addressof(__parent)) {
-      __satisfy();
-    }
+    _LIBCPP_HIDE_FROM_ABI __iterator() = default;
 
     _LIBCPP_HIDE_FROM_ABI
     constexpr __iterator(__iterator<!_Const> __i)
@@ -287,14 +317,14 @@ namespace ranges {
 
     _LIBCPP_HIDE_FROM_ABI
     constexpr __iterator& operator++() {
-      auto&& __inner = [&]() -> auto&& {
+      auto __get_inner_range = [&]() -> decltype(auto) {
         if constexpr (__ref_is_glvalue)
-          return *__outer_;
+          return *__get_outer();
         else
-          return *__parent_->__cache_;
-      }();
-      if (++*__inner_ == ranges::end(__inner)) {
-        ++__outer_;
+          return *__parent_->__inner_;
+      };
+      if (++*__inner_ == ranges::end(std::__as_lvalue(__get_inner_range()))) {
+        ++__get_outer();
         __satisfy();
       }
       return *this;
@@ -324,11 +354,11 @@ namespace ranges {
                common_range<range_reference_t<_Base>>
     {
       if (__outer_ == ranges::end(__parent_->__base_))
-        __inner_ = ranges::end(*--__outer_);
+        __inner_ = ranges::end(std::__as_lvalue(*--__outer_));
 
       // Skip empty inner ranges when going backwards.
-      while (*__inner_ == ranges::begin(*__outer_)) {
-        __inner_ = ranges::end(*--__outer_);
+      while (*__inner_ == ranges::begin(std::__as_lvalue(*__outer_))) {
+        __inner_ = ranges::end(std::__as_lvalue(*--__outer_));
       }
 
       --*__inner_;
@@ -350,7 +380,7 @@ namespace ranges {
     _LIBCPP_HIDE_FROM_ABI
     friend constexpr bool operator==(const __iterator& __x, const __iterator& __y)
       requires __ref_is_glvalue &&
-               equality_comparable<iterator_t<_Base>> &&
+               forward_range<_Base> &&
                equality_comparable<iterator_t<range_reference_t<_Base>>>
     {
       return __x.__outer_ == __y.__outer_ && __x.__inner_ == __y.__inner_;
@@ -436,7 +466,7 @@ struct __segmented_iterator_traits<_JoinViewIterator> {
   }
 };
 
-#endif // #if _LIBCPP_STD_VER >= 20 && defined(_LIBCPP_ENABLE_EXPERIMENTAL)
+#endif // #if _LIBCPP_STD_VER >= 20
 
 _LIBCPP_END_NAMESPACE_STD
 
diff --git a/libcxx/include/__utility/as_lvalue.h b/libcxx/include/__utility/as_lvalue.h
new file mode 100644
index 000000000000..159f45dad4d4
--- /dev/null
+++ b/libcxx/include/__utility/as_lvalue.h
@@ -0,0 +1,37 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef _LIBCPP___UTILITY_AS_LVALUE_H
+#define _LIBCPP___UTILITY_AS_LVALUE_H
+
+#include <__config>
+
+#if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER)
+#  pragma GCC system_header
+#endif
+
+_LIBCPP_PUSH_MACROS
+#include <__undef_macros>
+
+_LIBCPP_BEGIN_NAMESPACE_STD
+
+#ifndef _LIBCPP_CXX03_LANG
+
+template <class _Tp>
+_LIBCPP_HIDE_FROM_ABI constexpr _Tp& __as_lvalue(_LIBCPP_LIFETIMEBOUND _Tp&& __t) {
+  return static_cast<_Tp&>(__t);
+}
+
+#endif // !_LIBCPP_CXX03_LANG
+
+_LIBCPP_END_NAMESPACE_STD
+
+_LIBCPP_POP_MACROS
+
+#endif // _LIBCPP___UTILITY_AS_LVALUE_H
diff --git a/libcxx/include/module.modulemap.in b/libcxx/include/module.modulemap.in
index 90ee7fbb2157..7e93e0a15503 100644
--- a/libcxx/include/module.modulemap.in
+++ b/libcxx/include/module.modulemap.in
@@ -2019,6 +2019,7 @@ module std_private_type_traits_unwrap_ref                                [system
 module std_private_type_traits_void_t                                    [system] { header "__type_traits/void_t.h" }
 
 module std_private_utility_as_const               [system] { header "__utility/as_const.h" }
+module std_private_utility_as_lvalue              [system] { header "__utility/as_lvalue.h" }
 module std_private_utility_auto_cast              [system] {
   header "__utility/auto_cast.h"
   export std_private_type_traits_decay
diff --git a/libcxx/include/regex b/libcxx/include/regex
index fcdd85f8c499..008fe70a0ca6 100644
--- a/libcxx/include/regex
+++ b/libcxx/include/regex
@@ -697,6 +697,7 @@ public:
     typedef const value_type*                    pointer;
     typedef const value_type&                    reference;
     typedef forward_iterator_tag                 iterator_category;
+    typedef input_iterator_tag                   iterator_concept; // since C++20
 
     regex_iterator();
     regex_iterator(BidirectionalIterator a, BidirectionalIterator b,
@@ -737,6 +738,7 @@ public:
     typedef const value_type*                pointer;
     typedef const value_type&                reference;
     typedef forward_iterator_tag             iterator_category;
+    typedef input_iterator_tag               iterator_concept; // since C++20
 
     regex_token_iterator();
     regex_token_iterator(BidirectionalIterator a, BidirectionalIterator b,
@@ -6407,6 +6409,9 @@ public:
     typedef const value_type*                     pointer;
     typedef const value_type&                     reference;
     typedef forward_iterator_tag                  iterator_category;
+#if _LIBCPP_STD_VER >= 20
+    typedef input_iterator_tag                    iterator_concept;
+#endif
 
 private:
     _BidirectionalIterator           __begin_;
@@ -6542,6 +6547,9 @@ public:
     typedef const value_type*                 pointer;
     typedef const value_type&                 reference;
     typedef forward_iterator_tag              iterator_category;
+#if _LIBCPP_STD_VER >= 20
+    typedef input_iterator_tag                iterator_concept;
+#endif
 
 private:
     typedef regex_iterator<_BidirectionalIterator, _CharT, _Traits> _Position;
diff --git a/libcxx/include/utility b/libcxx/include/utility
index c5581d55e79b..1deef3db2041 100644
--- a/libcxx/include/utility
+++ b/libcxx/include/utility
@@ -249,6 +249,7 @@ template <class T>
 #include <__assert> // all public C++ headers provide the assertion handler
 #include <__config>
 #include <__utility/as_const.h>
+#include <__utility/as_lvalue.h>
 #include <__utility/auto_cast.h>
 #include <__utility/cmp.h>
 #include <__utility/declval.h>
diff --git a/libcxx/modules/std/ranges.inc b/libcxx/modules/std/ranges.inc
index a883103d8125..82c7d99f8979 100644
--- a/libcxx/modules/std/ranges.inc
+++ b/libcxx/modules/std/ranges.inc
@@ -204,13 +204,11 @@ export namespace std {
       using std::ranges::views::drop_while;
     } // namespace views
 
-#ifdef _LIBCPP_ENABLE_EXPERIMENTAL
     using std::ranges::join_view;
 
     namespace views {
       using std::ranges::views::join;
     } // namespace views
-#endif // _LIBCPP_ENABLE_EXPERIMENTAL
 #if 0
     using std::ranges::join_with_view;
 
diff --git a/libcxx/test/libcxx/ranges/range.adaptors/range.adaptor.helpers/as-lvalue.lifetimebound.verify.cpp b/libcxx/test/libcxx/ranges/range.adaptors/range.adaptor.helpers/as-lvalue.lifetimebound.verify.cpp
new file mode 100644
index 000000000000..7046936b1b7a
--- /dev/null
+++ b/libcxx/test/libcxx/ranges/range.adaptors/range.adaptor.helpers/as-lvalue.lifetimebound.verify.cpp
@@ -0,0 +1,22 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+// UNSUPPORTED: c++03
+
+// template<class T>
+// constexpr T& as-lvalue(T&& t) { // exposition only
+
+#include <utility>
+
+void test() {
+  // Check prvalue
+  {
+    [[maybe_unused]] auto& check = std::__as_lvalue(
+        0); // expected-warning {{temporary bound to local reference 'check' will be destroyed at the end of the full-expression}}
+  }
+}
diff --git a/libcxx/test/libcxx/ranges/range.adaptors/range.adaptor.helpers/as-lvalue.pass.cpp b/libcxx/test/libcxx/ranges/range.adaptors/range.adaptor.helpers/as-lvalue.pass.cpp
new file mode 100644
index 000000000000..721279fcd586
--- /dev/null
+++ b/libcxx/test/libcxx/ranges/range.adaptors/range.adaptor.helpers/as-lvalue.pass.cpp
@@ -0,0 +1,40 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+// UNSUPPORTED: c++03, c++11
+
+// template<class T>
+// constexpr T& as-lvalue(T&& t) { // exposition only
+
+#include <type_traits>
+#include <utility>
+
+constexpr bool test() {
+  // Check glvalue
+  {
+    int lvalue{};
+    [[maybe_unused]] decltype(auto) check = std::__as_lvalue(lvalue);
+    static_assert(std::is_same<decltype(check), int&>::value, "");
+  }
+
+  // Check xvalue
+  {
+    int xvalue{};
+    [[maybe_unused]] decltype(auto) check = std::__as_lvalue(std::move(xvalue));
+    static_assert(std::is_same<decltype(check), int&>::value, "");
+  }
+
+  return true;
+}
+
+int main(int, char**) {
+  test();
+  static_assert(test(), "");
+
+  return 0;
+}
diff --git a/libcxx/test/libcxx/ranges/range.adaptors/range.adaptor.tuple/tuple-for-each.pass.cpp b/libcxx/test/libcxx/ranges/range.adaptors/range.adaptor.helpers/tuple-for-each.pass.cpp
similarity index 100%
rename from libcxx/test/libcxx/ranges/range.adaptors/range.adaptor.tuple/tuple-for-each.pass.cpp
rename to libcxx/test/libcxx/ranges/range.adaptors/range.adaptor.helpers/tuple-for-each.pass.cpp
diff --git a/libcxx/test/libcxx/ranges/range.adaptors/range.join/range.join.iterator/ctor.parent.outer.pass.cpp b/libcxx/test/libcxx/ranges/range.adaptors/range.join/range.join.iterator/ctor.parent.outer.pass.cpp
new file mode 100644
index 000000000000..a54980bec287
--- /dev/null
+++ b/libcxx/test/libcxx/ranges/range.adaptors/range.join/range.join.iterator/ctor.parent.outer.pass.cpp
@@ -0,0 +1,65 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+// UNSUPPORTED: c++03, c++11, c++14, c++17
+
+// constexpr iterator(Parent& parent, OuterIter outer)
+//   requires forward_range<Base>; // exposition only
+
+#include <cassert>
+#include <ranges>
+#include <string>
+#include <utility>
+
+#include "types.h"
+
+constexpr bool test() {
+  std::string strings[4] = {"aaaa", "bbbb", "cccc", "dddd"};
+
+  { // Check if `outer_` is initialized with `std::move(outer)` for `iterator<false>`
+    MoveOnAccessSubrange r{DieOnCopyIterator(strings), sentinel_wrapper(strings + 4)};
+    std::ranges::join_view jv(std::move(r));
+    auto iter = jv.begin(); // Calls `iterator(Parent& parent, OuterIter outer)`
+    assert(*iter == 'a');
+  }
+
+  { // Check if `outer_` is initialized with `std::move(outer)` for `iterator<true>`
+    MoveOnAccessSubrange r{DieOnCopyIterator(strings), sentinel_wrapper(strings + 4)};
+    std::ranges::join_view jv(std::ranges::ref_view{r});
+    auto iter = std::as_const(jv).begin(); // Calls `iterator(Parent& parent, OuterIter outer)`
+    assert(*iter == 'a');
+  }
+
+  {
+    // LWG3569 Inner iterator not default_initializable
+    // With the current spec, the constructor under test invokes Inner iterator's default constructor
+    // even if it is not default constructible.
+    // This test is checking that this constructor can be invoked with an inner range with non default
+    // constructible iterator.
+    using NonDefaultCtrIter = cpp20_input_iterator<int*>;
+    static_assert(!std::default_initializable<NonDefaultCtrIter>);
+    using NonDefaultCtrIterView = BufferView<NonDefaultCtrIter, sentinel_wrapper<NonDefaultCtrIter>>;
+    static_assert(std::ranges::input_range<NonDefaultCtrIterView>);
+
+    int buffer[2][2]               = {{1, 2}, {3, 4}};
+    NonDefaultCtrIterView inners[] = {buffer[0], buffer[1]};
+    auto outer                     = std::views::all(inners);
+    std::ranges::join_view jv(outer);
+    auto iter = jv.begin(); // Calls `iterator(Parent& parent, OuterIter outer)`
+    assert(*iter == 1);
+  }
+
+  return true;
+}
+
+int main(int, char**) {
+  test();
+  static_assert(test());
+
+  return 0;
+}
diff --git a/libcxx/test/libcxx/ranges/range.adaptors/range.join/range.join.iterator/ctor.parent.pass.cpp b/libcxx/test/libcxx/ranges/range.adaptors/range.join/range.join.iterator/ctor.parent.pass.cpp
new file mode 100644
index 000000000000..3026a02abf00
--- /dev/null
+++ b/libcxx/test/libcxx/ranges/range.adaptors/range.join/range.join.iterator/ctor.parent.pass.cpp
@@ -0,0 +1,36 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+// UNSUPPORTED: c++03, c++11, c++14, c++17
+
+// constexpr explicit iterator(Parent& parent)
+//   requires (!forward_range<Base>); // exposition only
+
+#include <string>
+#include <ranges>
+
+#include "types.h"
+
+constexpr bool test() {
+  std::string strings[4] = {"eeee", "ffff", "gggg", "hhhh"};
+
+  MoveOnAccessSubrange r{
+      DieOnCopyIterator(cpp20_input_iterator(strings)), sentinel_wrapper(cpp20_input_iterator(strings + 4))};
+  std::ranges::join_view jv(std::move(r));
+  auto iter = jv.begin(); // Calls `iterator(Parent& parent)`
+  assert(*iter == 'e');
+
+  return true;
+}
+
+int main(int, char**) {
+  test();
+  static_assert(test());
+
+  return 0;
+}
diff --git a/libcxx/test/libcxx/ranges/range.adaptors/range.join/range.join.iterator/types.h b/libcxx/test/libcxx/ranges/range.adaptors/range.join/range.join.iterator/types.h
new file mode 100644
index 000000000000..0652d4bdb471
--- /dev/null
+++ b/libcxx/test/libcxx/ranges/range.adaptors/range.join/range.join.iterator/types.h
@@ -0,0 +1,114 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef TEST_LIBCXX_RANGES_RANGE_ADAPTORS_RANGE_JOIN_RANGE_JOIN_ITERATOR_TYPES_H
+#define TEST_LIBCXX_RANGES_RANGE_ADAPTORS_RANGE_JOIN_RANGE_JOIN_ITERATOR_TYPES_H
+
+#include <cassert>
+#include <cstddef>
+#include <ranges>
+
+#include "test_iterators.h"
+
+template <std::input_iterator Iter>
+struct DieOnCopyIterator {
+  using value_type      = std::iter_value_t<Iter>;
+  using difference_type = std::iter_difference_t<Iter>;
+
+  DieOnCopyIterator()
+    requires std::default_initializable<Iter>
+  = default;
+
+  constexpr explicit DieOnCopyIterator(Iter iter) : iter_(std::move(iter)) {}
+  constexpr DieOnCopyIterator(DieOnCopyIterator&& other) = default;
+  DieOnCopyIterator& operator=(DieOnCopyIterator&&)      = default;
+
+  constexpr DieOnCopyIterator(const DieOnCopyIterator&) { assert(false); }
+  constexpr DieOnCopyIterator& operator=(const DieOnCopyIterator&) { assert(false); }
+
+  constexpr DieOnCopyIterator& operator++() {
+    ++iter_;
+    return *this;
+  }
+
+  constexpr void operator++(int) { iter_++; }
+
+  constexpr DieOnCopyIterator operator++(int)
+    requires std::forward_iterator<Iter>
+  {
+    auto tmp = *this;
+    ++tmp;
+    return tmp;
+  }
+
+  constexpr decltype(auto) operator*() const { return *iter_; }
+
+  friend constexpr bool operator==(const DieOnCopyIterator& left, const DieOnCopyIterator& right)
+    requires std::equality_comparable<Iter>
+  {
+    return left.iter_ == right.iter_;
+  }
+
+  friend constexpr bool operator==(const DieOnCopyIterator& it, const sentinel_wrapper<Iter>& se) {
+    return it.iter_ == se;
+  }
+
+private:
+  Iter iter_ = Iter();
+};
+
+template <class Iter>
+explicit DieOnCopyIterator(Iter) -> DieOnCopyIterator<Iter>;
+
+static_assert(std::input_iterator<DieOnCopyIterator<cpp20_input_iterator<int*>>>);
+static_assert(!std::forward_iterator<DieOnCopyIterator<cpp20_input_iterator<int*>>>);
+static_assert(std::forward_iterator<DieOnCopyIterator<int*>>);
+static_assert(!std::bidirectional_iterator<DieOnCopyIterator<int*>>);
+static_assert(std::sentinel_for<sentinel_wrapper<int*>, DieOnCopyIterator<int*>>);
+
+template <std::input_iterator Iter, std::sentinel_for<Iter> Sent = Iter>
+struct MoveOnAccessSubrange : std::ranges::view_base {
+  constexpr explicit MoveOnAccessSubrange(Iter iter, Sent sent) : iter_(std::move(iter)), sent_(std::move(sent)) {}
+
+  MoveOnAccessSubrange(MoveOnAccessSubrange&&)            = default;
+  MoveOnAccessSubrange& operator=(MoveOnAccessSubrange&&) = default;
+
+  MoveOnAccessSubrange(const MoveOnAccessSubrange&)            = delete;
+  MoveOnAccessSubrange& operator=(const MoveOnAccessSubrange&) = delete;
+
+  constexpr Iter begin() { return std::move(iter_); }
+  constexpr Sent end() { return std::move(sent_); }
+
+private:
+  Iter iter_;
+  Sent sent_;
+};
+
+template <class Iter, class Sent>
+MoveOnAccessSubrange(Iter, Sent) -> MoveOnAccessSubrange<Iter, Sent>;
+
+static_assert(std::ranges::input_range<MoveOnAccessSubrange<int*, sentinel_wrapper<int*>>>);
+static_assert(std::ranges::forward_range<MoveOnAccessSubrange<DieOnCopyIterator<int*>>>);
+
+template <class Iter, class Sent>
+  requires(!std::same_as<Iter, Sent>)
+struct BufferView : std::ranges::view_base {
+  using T = std::iter_value_t<Iter>;
+  T* data_;
+  std::size_t size_;
+
+  template <std::size_t N>
+  constexpr BufferView(T (&b)[N]) : data_(b), size_(N) {}
+
+  constexpr Iter begin() const { return Iter(data_); }
+  constexpr Sent end() const { return Sent(Iter(data_ + size_)); }
+};
+
+static_assert(std::ranges::input_range<BufferView<int*, sentinel_wrapper<int*>>>);
+
+#endif // TEST_LIBCXX_RANGES_RANGE_ADAPTORS_RANGE_JOIN_RANGE_JOIN_ITERATOR_TYPES_H
diff --git a/libcxx/test/libcxx/ranges/range.adaptors/range.join/segmented_iterator.compile.pass.cpp b/libcxx/test/libcxx/ranges/range.adaptors/range.join/segmented_iterator.compile.pass.cpp
index 82e8cab503a2..6cd17c2b3f35 100644
--- a/libcxx/test/libcxx/ranges/range.adaptors/range.join/segmented_iterator.compile.pass.cpp
+++ b/libcxx/test/libcxx/ranges/range.adaptors/range.join/segmented_iterator.compile.pass.cpp
@@ -7,7 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// UNSUPPORTED: !c++experimental
 
 #include <ranges>
 #include <utility>
diff --git a/libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/ranges.copy.segmented.pass.cpp b/libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/ranges.copy.segmented.pass.cpp
index 50fb479afcd0..ec60ab8db160 100644
--- a/libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/ranges.copy.segmented.pass.cpp
+++ b/libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/ranges.copy.segmented.pass.cpp
@@ -7,8 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// TODO: make `join_view` non-experimental once D2770 is implemented.
-// UNSUPPORTED: !c++experimental
 
 #include <algorithm>
 #include <array>
diff --git a/libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/ranges.copy_backward.pass.cpp b/libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/ranges.copy_backward.pass.cpp
index feca8fd3be85..343447446ab2 100644
--- a/libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/ranges.copy_backward.pass.cpp
+++ b/libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/ranges.copy_backward.pass.cpp
@@ -9,8 +9,6 @@
 // <algorithm>
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// TODO: make `join_view` non-experimental once D2770 is implemented.
-// UNSUPPORTED: !c++experimental
 // UNSUPPORTED: GCC-ALWAYS_INLINE-FIXME
 
 // template<bidirectional_iterator I1, sentinel_for<I1> S1, bidirectional_iterator I2>
diff --git a/libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/ranges.copy_backward.segmented.pass.cpp b/libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/ranges.copy_backward.segmented.pass.cpp
index c434cea1208c..efeada576255 100644
--- a/libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/ranges.copy_backward.segmented.pass.cpp
+++ b/libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/ranges.copy_backward.segmented.pass.cpp
@@ -7,8 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// TODO: make `join_view` non-experimental once D2770 is implemented.
-// UNSUPPORTED: !c++experimental
 
 #include <algorithm>
 #include <array>
diff --git a/libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/ranges.copy_n.segmented.pass.cpp b/libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/ranges.copy_n.segmented.pass.cpp
index eae40cefa663..7da0f3077590 100644
--- a/libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/ranges.copy_n.segmented.pass.cpp
+++ b/libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/ranges.copy_n.segmented.pass.cpp
@@ -7,8 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// TODO: make `join_view` non-experimental once D2770 is implemented.
-// UNSUPPORTED: !c++experimental
 
 #include <algorithm>
 #include <array>
diff --git a/libcxx/test/std/algorithms/alg.modifying.operations/alg.move/ranges.move.segmented.pass.cpp b/libcxx/test/std/algorithms/alg.modifying.operations/alg.move/ranges.move.segmented.pass.cpp
index 2df6a10b1850..e29ba8af07d6 100644
--- a/libcxx/test/std/algorithms/alg.modifying.operations/alg.move/ranges.move.segmented.pass.cpp
+++ b/libcxx/test/std/algorithms/alg.modifying.operations/alg.move/ranges.move.segmented.pass.cpp
@@ -7,8 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// TODO: make `join_view` non-experimental once D2770 is implemented.
-// UNSUPPORTED: !c++experimental
 
 #include <algorithm>
 #include <array>
diff --git a/libcxx/test/std/algorithms/alg.modifying.operations/alg.move/ranges.move_backward.segmented.pass.cpp b/libcxx/test/std/algorithms/alg.modifying.operations/alg.move/ranges.move_backward.segmented.pass.cpp
index 0f0a71439a10..50f371a6d64d 100644
--- a/libcxx/test/std/algorithms/alg.modifying.operations/alg.move/ranges.move_backward.segmented.pass.cpp
+++ b/libcxx/test/std/algorithms/alg.modifying.operations/alg.move/ranges.move_backward.segmented.pass.cpp
@@ -7,8 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// TODO: make `join_view` non-experimental once D2770 is implemented.
-// UNSUPPORTED: !c++experimental
 
 #include <algorithm>
 #include <array>
diff --git a/libcxx/test/std/library/description/conventions/customization.point.object/cpo.compile.pass.cpp b/libcxx/test/std/library/description/conventions/customization.point.object/cpo.compile.pass.cpp
index e6c0e09dfff5..060f179fe168 100644
--- a/libcxx/test/std/library/description/conventions/customization.point.object/cpo.compile.pass.cpp
+++ b/libcxx/test/std/library/description/conventions/customization.point.object/cpo.compile.pass.cpp
@@ -7,8 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// TODO: make `join_view` non-experimental once D2770 is implemented.
-// UNSUPPORTED: !c++experimental
 
 // [customization.point.object]
 // [range.adaptor.object] "A range adaptor object is a customization point object..."
diff --git a/libcxx/test/std/ranges/iterator_robust_against_adl.compile.pass.cpp b/libcxx/test/std/ranges/iterator_robust_against_adl.compile.pass.cpp
index 09b77c0901a2..5efd6c72a13d 100644
--- a/libcxx/test/std/ranges/iterator_robust_against_adl.compile.pass.cpp
+++ b/libcxx/test/std/ranges/iterator_robust_against_adl.compile.pass.cpp
@@ -7,7 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// UNSUPPORTED: !c++experimental
 
 // ADL call with nested iterators of views should not look up base's view's
 // namespace
diff --git a/libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/ctor.parent.outer.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/ctor.parent.outer.pass.cpp
deleted file mode 100644
index 215318f15cad..000000000000
--- a/libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/ctor.parent.outer.pass.cpp
+++ /dev/null
@@ -1,57 +0,0 @@
-//===----------------------------------------------------------------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-// UNSUPPORTED: c++03, c++11, c++14, c++17
-// UNSUPPORTED: !c++experimental
-
-// constexpr iterator(Parent& parent, OuterIter outer);
-
-#include <cassert>
-#include <ranges>
-
-#include "../types.h"
-
-using NonDefaultCtrIter = cpp20_input_iterator<int*>;
-static_assert(!std::default_initializable<NonDefaultCtrIter>);
-
-using NonDefaultCtrIterView = BufferView<NonDefaultCtrIter, sentinel_wrapper<NonDefaultCtrIter>>;
-static_assert(std::ranges::input_range<NonDefaultCtrIterView>);
-
-constexpr bool test() {
-  int buffer[4][4] = {{1, 2, 3, 4}, {5, 6, 7, 8}, {9, 10, 11, 12}, {13, 14, 15, 16}};
-  {
-    CopyableChild children[4] = {CopyableChild(buffer[0]), CopyableChild(buffer[1]), CopyableChild(buffer[2]),
-                                 CopyableChild(buffer[3])};
-    CopyableParent parent{children};
-    std::ranges::join_view jv(parent);
-    std::ranges::iterator_t<decltype(jv)> iter(jv, std::ranges::begin(parent));
-    assert(*iter == 1);
-  }
-
-  {
-    // LWG3569 Inner iterator not default_initializable
-    // With the current spec, the constructor under test invokes Inner iterator's default constructor
-    // even if it is not default constructible
-    // This test is checking that this constructor can be invoked with an inner range with non default
-    // constructible iterator
-    NonDefaultCtrIterView inners[] = {buffer[0], buffer[1]};
-    auto outer = std::views::all(inners);
-    std::ranges::join_view jv(outer);
-    std::ranges::iterator_t<decltype(jv)> iter(jv, std::ranges::begin(outer));
-    assert(*iter == 1);
-  }
-
-  return true;
-}
-
-int main(int, char**) {
-  test();
-  static_assert(test());
-
-  return 0;
-}
diff --git a/libcxx/test/std/ranges/range.adaptors/range.join.view/adaptor.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.join/adaptor.pass.cpp
similarity index 99%
rename from libcxx/test/std/ranges/range.adaptors/range.join.view/adaptor.pass.cpp
rename to libcxx/test/std/ranges/range.adaptors/range.join/adaptor.pass.cpp
index afaf32272109..9beb3d282a27 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.join.view/adaptor.pass.cpp
+++ b/libcxx/test/std/ranges/range.adaptors/range.join/adaptor.pass.cpp
@@ -7,7 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// UNSUPPORTED: !c++experimental
 
 // std::views::join
 
diff --git a/libcxx/test/std/ranges/range.adaptors/range.join.view/base.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.join/base.pass.cpp
similarity index 98%
rename from libcxx/test/std/ranges/range.adaptors/range.join.view/base.pass.cpp
rename to libcxx/test/std/ranges/range.adaptors/range.join/base.pass.cpp
index 13883e894ac7..caf018b58226 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.join.view/base.pass.cpp
+++ b/libcxx/test/std/ranges/range.adaptors/range.join/base.pass.cpp
@@ -7,7 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// UNSUPPORTED: !c++experimental
 
 // constexpr V base() const& requires copy_constructible<V>;
 // constexpr V base() &&;
diff --git a/libcxx/test/std/ranges/range.adaptors/range.join.view/begin.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.join/begin.pass.cpp
similarity index 83%
rename from libcxx/test/std/ranges/range.adaptors/range.join.view/begin.pass.cpp
rename to libcxx/test/std/ranges/range.adaptors/range.join/begin.pass.cpp
index 9e4fa5f8c59a..005d0d1d2d5c 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.join.view/begin.pass.cpp
+++ b/libcxx/test/std/ranges/range.adaptors/range.join/begin.pass.cpp
@@ -7,15 +7,17 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// UNSUPPORTED: !c++experimental
 
 // constexpr auto begin();
 // constexpr auto begin() const
-//    requires input_range<const V> &&
-//             is_reference_v<range_reference_t<const V>>;
+//    requires forward_range<const V> &&
+//             is_reference_v<range_reference_t<const V>> &&
+//             input_range<range_reference_t<const V>>;
 
+#include <algorithm>
 #include <cassert>
 #include <ranges>
+#include <string_view>
 
 #include "types.h"
 
@@ -120,7 +122,7 @@ constexpr bool test() {
     static_assert(HasConstBegin<decltype(jv)>);
   }
 
-  // !input_range<const V>
+  // !forward_range<const V>
   {
     std::ranges::join_view jv{ConstNotRange{}};
     static_assert(!HasConstBegin<decltype(jv)>);
@@ -146,6 +148,27 @@ constexpr bool test() {
     static_assert(std::same_as<decltype(jv.begin()), decltype(std::as_const(jv).begin())>);
   }
 
+  // Check stashing iterators (LWG3698: regex_iterator and join_view don't work together very well)
+  {
+    std::ranges::join_view<StashingRange> jv;
+    assert(std::ranges::equal(std::views::counted(jv.begin(), 10), std::string_view{"aababcabcd"}));
+  }
+
+  // LWG3700: The `const begin` of the `join_view` family does not require `InnerRng` to be a range
+  {
+    std::ranges::join_view<ConstNonJoinableRange> jv;
+    static_assert(!HasConstBegin<decltype(jv)>);
+  }
+
+  // Check example from LWG3700
+  {
+    auto r = std::views::iota(0, 5) | std::views::split(1);
+    auto s = std::views::single(r);
+    auto j = s | std::views::join;
+    auto f = j.front();
+    assert(std::ranges::equal(f, std::views::single(0)));
+  }
+
   return true;
 }
 
diff --git a/libcxx/test/std/ranges/range.adaptors/range.join.view/ctad.compile.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.join/ctad.compile.pass.cpp
similarity index 98%
rename from libcxx/test/std/ranges/range.adaptors/range.join.view/ctad.compile.pass.cpp
rename to libcxx/test/std/ranges/range.adaptors/range.join/ctad.compile.pass.cpp
index 2c470991be0b..a8eafc5a9c02 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.join.view/ctad.compile.pass.cpp
+++ b/libcxx/test/std/ranges/range.adaptors/range.join/ctad.compile.pass.cpp
@@ -7,7 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// UNSUPPORTED: !c++experimental
 
 // template<class R>
 //   explicit join_view(R&&) -> join_view<views::all_t<R>>;
diff --git a/libcxx/test/std/ranges/range.adaptors/range.join.view/ctad.verify.cpp b/libcxx/test/std/ranges/range.adaptors/range.join/ctad.verify.cpp
similarity index 97%
rename from libcxx/test/std/ranges/range.adaptors/range.join.view/ctad.verify.cpp
rename to libcxx/test/std/ranges/range.adaptors/range.join/ctad.verify.cpp
index eddc950747ba..2c6eea500580 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.join.view/ctad.verify.cpp
+++ b/libcxx/test/std/ranges/range.adaptors/range.join/ctad.verify.cpp
@@ -7,7 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// UNSUPPORTED: !c++experimental
 
 // template<class R>
 //   explicit join_view(R&&) -> join_view<views::all_t<R>>;
diff --git a/libcxx/test/std/ranges/range.adaptors/range.join.view/ctor.default.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.join/ctor.default.pass.cpp
similarity index 97%
rename from libcxx/test/std/ranges/range.adaptors/range.join.view/ctor.default.pass.cpp
rename to libcxx/test/std/ranges/range.adaptors/range.join/ctor.default.pass.cpp
index 26206e32c358..0daff7d3b3c9 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.join.view/ctor.default.pass.cpp
+++ b/libcxx/test/std/ranges/range.adaptors/range.join/ctor.default.pass.cpp
@@ -7,7 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// UNSUPPORTED: !c++experimental
 
 // join_view() requires default_initializable<V> = default;
 
diff --git a/libcxx/test/std/ranges/range.adaptors/range.join.view/ctor.view.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.join/ctor.view.pass.cpp
similarity index 97%
rename from libcxx/test/std/ranges/range.adaptors/range.join.view/ctor.view.pass.cpp
rename to libcxx/test/std/ranges/range.adaptors/range.join/ctor.view.pass.cpp
index ce5393062d77..75d4c7e5916b 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.join.view/ctor.view.pass.cpp
+++ b/libcxx/test/std/ranges/range.adaptors/range.join/ctor.view.pass.cpp
@@ -7,7 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// UNSUPPORTED: !c++experimental
 
 // constexpr explicit join_view(V base);
 
diff --git a/libcxx/test/std/ranges/range.adaptors/range.join.view/end.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.join/end.pass.cpp
similarity index 95%
rename from libcxx/test/std/ranges/range.adaptors/range.join.view/end.pass.cpp
rename to libcxx/test/std/ranges/range.adaptors/range.join/end.pass.cpp
index 7e225202cc23..516ba25a0e85 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.join.view/end.pass.cpp
+++ b/libcxx/test/std/ranges/range.adaptors/range.join/end.pass.cpp
@@ -7,10 +7,12 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// UNSUPPORTED: !c++experimental
 
 // constexpr auto end();
 // constexpr auto end() const;
+//   requires forward_range<const V> &&
+//            is_reference_v<range_reference_t<const V>> &&
+//            input_range<range_reference_t<const V>>
 
 #include <cassert>
 #include <ranges>
@@ -33,13 +35,13 @@ concept HasConstEnd = requires (const T& t){
 // | 3  |   Y    |   Y     |   Y    |   Y   |    N    |   Y    |sentinel<true> |sentinel<true>|
 // | 4  |   Y    |   Y     |   Y    |   N   |    Y    |   Y    |sentinel<true> |      -       |
 // | 5  |   Y    |   Y     |   N    |   Y   |    Y    |   Y    |sentinel<true> |sentinel<true>|
-// | 6  |   Y    |   N     |   Y    |   Y   |    Y    |   Y    |sentinel<true> |sentinel<true>|
+// | 6  |   Y    |   N     |   Y    |   Y   |    Y    |   Y    |sentinel<true> |      -       |
 // | 7  |   N    |   Y     |   Y    |   Y   |    Y    |   Y    |iterator<false>|iterator<true>|
 // | 8  |   N    |   Y     |   Y    |   Y   |    Y    |   N    |sentinel<false>|sentinel<true>|
 // | 9  |   N    |   Y     |   Y    |   Y   |    N    |   Y    |sentinel<false>|sentinel<true>|
 // | 10 |   N    |   Y     |   Y    |   N   |    Y    |   Y    |sentinel<false>|      -       |
 // | 11 |   N    |   Y     |   N    |   Y   |    Y    |   Y    |sentinel<false>|sentinel<true>|
-// | 12 |   N    |   N     |   Y    |   Y   |    Y    |   Y    |sentinel<false>|sentinel<true>|
+// | 12 |   N    |   N     |   Y    |   Y   |    Y    |   Y    |sentinel<false>|      -       |
 //
 //
 
@@ -131,10 +133,8 @@ constexpr bool test() {
 
     std::ranges::join_view jv(outer);
     assert(jv.end() == std::ranges::next(jv.begin(), 16));
-    assert(std::as_const(jv).end() == std::ranges::next(std::as_const(jv).begin(), 16));
 
-    static_assert(HasConstEnd<decltype(jv)>);
-    static_assert(std::same_as<decltype(jv.end()), decltype(std::as_const(jv).end())>);
+    static_assert(!HasConstEnd<decltype(jv)>);
     static_assert(!std::ranges::common_range<decltype(jv)>);
     static_assert(!std::ranges::common_range<const decltype(jv)>);
   }
@@ -219,10 +219,8 @@ constexpr bool test() {
 
     std::ranges::join_view jv(outer);
     assert(jv.end() == std::ranges::next(jv.begin(), 16));
-    assert(std::as_const(jv).end() == std::ranges::next(std::as_const(jv).begin(), 16));
 
-    static_assert(HasConstEnd<decltype(jv)>);
-    static_assert(!std::same_as<decltype(jv.end()), decltype(std::as_const(jv).end())>);
+    static_assert(!HasConstEnd<decltype(jv)>);
     static_assert(!std::ranges::common_range<decltype(jv)>);
     static_assert(!std::ranges::common_range<const decltype(jv)>);
   }
@@ -288,6 +286,12 @@ constexpr bool test() {
     assert(jv.end() == std::ranges::next(jv.begin(), 12));
   }
 
+  // LWG3700: The `const begin` of the `join_view` family does not require `InnerRng` to be a range
+  {
+    std::ranges::join_view<ConstNonJoinableRange> jv;
+    static_assert(!HasConstEnd<decltype(jv)>);
+  }
+
   return true;
 }
 
diff --git a/libcxx/test/std/ranges/range.adaptors/range.join.view/general.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.join/general.pass.cpp
similarity index 98%
rename from libcxx/test/std/ranges/range.adaptors/range.join.view/general.pass.cpp
rename to libcxx/test/std/ranges/range.adaptors/range.join/general.pass.cpp
index e9eab585260c..f92eb418fac7 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.join.view/general.pass.cpp
+++ b/libcxx/test/std/ranges/range.adaptors/range.join/general.pass.cpp
@@ -7,7 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// UNSUPPORTED: !c++experimental
 
 // General tests for join_view. This file does not test anything specifically.
 
diff --git a/libcxx/test/std/ranges/range.adaptors/range.join/lwg3698.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.join/lwg3698.pass.cpp
new file mode 100644
index 000000000000..0abe37bf17f7
--- /dev/null
+++ b/libcxx/test/std/ranges/range.adaptors/range.join/lwg3698.pass.cpp
@@ -0,0 +1,33 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+// UNSUPPORTED: c++03, c++11, c++14, c++17
+// UNSUPPORTED: no-localization
+
+// Check LWG-3698: `regex_iterator` and `join_view` don't work together very well
+
+#include <algorithm>
+#include <array>
+#include <cassert>
+#include <ranges>
+#include <regex>
+#include <string_view>
+
+int main(int, char**) {
+  char const text[] = "Hello";
+  std::regex regex{"[a-z]"};
+
+  auto lower =
+      std::ranges::subrange(
+          std::cregex_iterator(std::ranges::begin(text), std::ranges::end(text), regex), std::cregex_iterator{}) |
+      std::views::join | std::views::transform([](auto const& sm) { return std::string_view(sm.first, sm.second); });
+
+  assert(std::ranges::equal(lower, std::to_array<std::string_view>({"e", "l", "l", "o"})));
+
+  return 0;
+}
diff --git a/libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/arrow.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/arrow.pass.cpp
similarity index 99%
rename from libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/arrow.pass.cpp
rename to libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/arrow.pass.cpp
index e610cde2c3b5..ddcf66bfe775 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/arrow.pass.cpp
+++ b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/arrow.pass.cpp
@@ -7,7 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// UNSUPPORTED: !c++experimental
 
 // constexpr InnerIter operator->() const
 //   requires has-arrow<InnerIter> && copyable<InnerIter>;
diff --git a/libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/ctor.default.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/ctor.default.pass.cpp
similarity index 70%
rename from libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/ctor.default.pass.cpp
rename to libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/ctor.default.pass.cpp
index e4f193e4e606..82fe824fad1b 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/ctor.default.pass.cpp
+++ b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/ctor.default.pass.cpp
@@ -7,9 +7,8 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// UNSUPPORTED: !c++experimental
 
-// iterator() requires default_initializable<OuterIter> = default;
+// iterator() = default;
 
 #include <ranges>
 
@@ -29,19 +28,12 @@ constexpr void test_default_constructible() {
   using JoinView = std::ranges::join_view<view<It>>;
   using JoinIterator = std::ranges::iterator_t<JoinView>;
   static_assert(std::is_default_constructible_v<JoinIterator>);
-  JoinIterator it; (void)it;
-}
-
-template <class It>
-constexpr void test_non_default_constructible() {
-  using JoinView = std::ranges::join_view<view<It>>;
-  using JoinIterator = std::ranges::iterator_t<JoinView>;
-  static_assert(!std::is_default_constructible_v<JoinIterator>);
+  [[maybe_unused]] JoinIterator it;
 }
 
 constexpr bool test() {
-  test_non_default_constructible<cpp17_input_iterator<ChildView*>>();
-  // NOTE: cpp20_input_iterator can't be used with join_view because it is not copyable.
+  test_default_constructible<cpp17_input_iterator<ChildView*>>();
+  test_default_constructible<cpp20_input_iterator<ChildView*>>();
   test_default_constructible<forward_iterator<ChildView*>>();
   test_default_constructible<bidirectional_iterator<ChildView*>>();
   test_default_constructible<random_access_iterator<ChildView*>>();
diff --git a/libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/ctor.other.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/ctor.other.pass.cpp
similarity index 97%
rename from libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/ctor.other.pass.cpp
rename to libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/ctor.other.pass.cpp
index a0406f90c88c..e220b2cfeac8 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/ctor.other.pass.cpp
+++ b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/ctor.other.pass.cpp
@@ -7,7 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// UNSUPPORTED: !c++experimental
 
 // constexpr iterator(iterator<!Const> i)
 //             requires Const &&
@@ -37,7 +36,7 @@ constexpr bool test() {
   {
     CopyableChild children[4] = {CopyableChild(buffer[0]), CopyableChild(buffer[1]), CopyableChild(buffer[2]),
                                  CopyableChild(buffer[3])};
-    std::ranges::join_view jv(CopyableParent{children});
+    std::ranges::join_view jv(ForwardCopyableParent{children});
     auto iter1 = jv.begin();
     using iterator = decltype(iter1);
     using const_iterator = decltype(std::as_const(jv).begin());
diff --git a/libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/decrement.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/decrement.pass.cpp
similarity index 90%
rename from libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/decrement.pass.cpp
rename to libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/decrement.pass.cpp
index 4363fb0e330c..29720d93bab6 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/decrement.pass.cpp
+++ b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/decrement.pass.cpp
@@ -7,7 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// UNSUPPORTED: !c++experimental
 
 // constexpr iterator& operator--();
 //              requires ref-is-glvalue && bidirectional_range<Base> &&
@@ -18,9 +17,12 @@
 //                       bidirectional_range<range_reference_t<Base>> &&
 //                       common_range<range_reference_t<Base>>;
 
+#include <algorithm>
+#include <array>
 #include <cassert>
 #include <ranges>
 #include <type_traits>
+#include <vector>
 
 #include "../types.h"
 
@@ -150,6 +152,15 @@ constexpr bool test() {
     static_assert(!CanPostDecrement<decltype(iter)>);
   }
 
+  {
+    // LWG3791: `join_view::iterator::operator--` may be ill-formed
+    std::vector<std::vector<int>> vec = {{1, 2}, {3, 4}, {5, 6}};
+    auto r = vec | std::views::transform([](auto& x) -> auto&& { return std::move(x); }) | std::views::join;
+    auto e = --r.end();
+    assert(*e == 6);
+    assert(std::ranges::equal(std::views::reverse(r), std::array{6, 5, 4, 3, 2, 1}));
+  }
+
   return true;
 }
 
diff --git a/libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/eq.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/eq.pass.cpp
similarity index 89%
rename from libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/eq.pass.cpp
rename to libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/eq.pass.cpp
index 327cc82b06b0..5c831f33e67c 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/eq.pass.cpp
+++ b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/eq.pass.cpp
@@ -7,10 +7,9 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// UNSUPPORTED: !c++experimental
 
 // friend constexpr bool operator==(const iterator& x, const iterator& y);
-//          requires ref-is-glvalue && equality_comparable<iterator_t<Base>> &&
+//          requires ref-is-glvalue && forward_range<Base> &&
 //                   equality_comparable<iterator_t<range_reference_t<Base>>>;
 
 #include <cassert>
@@ -43,7 +42,7 @@ constexpr bool test() {
   }
 
   {
-    // !equality_comparable<iterator_t<Base>>
+    // !forward_range<Base>
     using Inner = BufferView<int*>;
     using Outer = BufferView<cpp20_input_iterator<Inner*>, sentinel_wrapper<cpp20_input_iterator<Inner*>>>;
     static_assert(!std::equality_comparable<std::ranges::iterator_t<Outer>>);
@@ -51,8 +50,6 @@ constexpr bool test() {
     std::ranges::join_view jv(Outer{inners});
     auto iter = jv.begin();
     static_assert(!std::equality_comparable<decltype(iter)>);
-    auto const_iter = std::as_const(jv).begin();
-    static_assert(!std::equality_comparable<decltype(const_iter)>);
   }
 
   {
diff --git a/libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/increment.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/increment.pass.cpp
similarity index 94%
rename from libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/increment.pass.cpp
rename to libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/increment.pass.cpp
index 4bcb4de7e9c8..dada91462a73 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/increment.pass.cpp
+++ b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/increment.pass.cpp
@@ -7,7 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// UNSUPPORTED: !c++experimental
 
 // constexpr iterator& operator++();
 // constexpr void operator++(int);
@@ -205,6 +204,23 @@ constexpr bool test() {
     static_assert(std::is_void_v<decltype(iter++)>);
   }
 
+  {
+    // Check stashing iterators (LWG3698: regex_iterator and join_view don't work together very well)
+    std::ranges::join_view<StashingRange> jv;
+    auto it = jv.begin();
+    assert(*it == 'a');
+    ++it;
+    assert(*it == 'a');
+    ++it;
+    assert(*it == 'b');
+    it++;
+    assert(*it == 'a');
+    it++;
+    assert(*it == 'b');
+    ++it;
+    assert(*it == 'c');
+  }
+
   return true;
 }
 
diff --git a/libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/iter.move.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/iter.move.pass.cpp
similarity index 98%
rename from libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/iter.move.pass.cpp
rename to libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/iter.move.pass.cpp
index 0bf6aa3d9261..917e72dc8585 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/iter.move.pass.cpp
+++ b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/iter.move.pass.cpp
@@ -7,7 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// UNSUPPORTED: !c++experimental
 
 // friend constexpr decltype(auto) iter_move(const iterator& i);
 
diff --git a/libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/iter.swap.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/iter.swap.pass.cpp
similarity index 98%
rename from libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/iter.swap.pass.cpp
rename to libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/iter.swap.pass.cpp
index e9b73f1a4159..28e1bf75726f 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/iter.swap.pass.cpp
+++ b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/iter.swap.pass.cpp
@@ -7,7 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// UNSUPPORTED: !c++experimental
 
 // friend constexpr void iter_swap(const iterator& x, const iterator& y);
 
diff --git a/libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/member_types.compile.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/member_types.compile.pass.cpp
similarity index 99%
rename from libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/member_types.compile.pass.cpp
rename to libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/member_types.compile.pass.cpp
index 17b98facd650..b9b9d73d77e2 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/member_types.compile.pass.cpp
+++ b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/member_types.compile.pass.cpp
@@ -7,7 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// UNSUPPORTED: !c++experimental
 
 // Iterator traits and member typedefs in join_view::<iterator>.
 
diff --git a/libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/star.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/star.pass.cpp
similarity index 97%
rename from libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/star.pass.cpp
rename to libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/star.pass.cpp
index fa6f7bb03120..73457b826df0 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.join.view/iterator/star.pass.cpp
+++ b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.iterator/star.pass.cpp
@@ -7,7 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// UNSUPPORTED: !c++experimental
 
 // constexpr decltype(auto) operator*() const;
 
diff --git a/libcxx/test/std/ranges/range.adaptors/range.join.view/sentinel/ctor.default.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.sentinel/ctor.default.pass.cpp
similarity index 95%
rename from libcxx/test/std/ranges/range.adaptors/range.join.view/sentinel/ctor.default.pass.cpp
rename to libcxx/test/std/ranges/range.adaptors/range.join/range.join.sentinel/ctor.default.pass.cpp
index 0eebe14af3fc..42fcc733e181 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.join.view/sentinel/ctor.default.pass.cpp
+++ b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.sentinel/ctor.default.pass.cpp
@@ -7,7 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// UNSUPPORTED: !c++experimental
 
 // sentinel() = default;
 
diff --git a/libcxx/test/std/ranges/range.adaptors/range.join.view/sentinel/ctor.other.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.sentinel/ctor.other.pass.cpp
similarity index 99%
rename from libcxx/test/std/ranges/range.adaptors/range.join.view/sentinel/ctor.other.pass.cpp
rename to libcxx/test/std/ranges/range.adaptors/range.join/range.join.sentinel/ctor.other.pass.cpp
index 96196dcbaa5b..5ef3e7416ef1 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.join.view/sentinel/ctor.other.pass.cpp
+++ b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.sentinel/ctor.other.pass.cpp
@@ -7,7 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// UNSUPPORTED: !c++experimental
 
 // constexpr sentinel(sentinel<!Const> s);
 //             requires Const && convertible_to<sentinel_t<V>, sentinel_t<Base>>;
diff --git a/libcxx/test/std/ranges/range.adaptors/range.join.view/sentinel/ctor.parent.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.sentinel/ctor.parent.pass.cpp
similarity index 97%
rename from libcxx/test/std/ranges/range.adaptors/range.join.view/sentinel/ctor.parent.pass.cpp
rename to libcxx/test/std/ranges/range.adaptors/range.join/range.join.sentinel/ctor.parent.pass.cpp
index a9df7c3881ba..1ac68277338f 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.join.view/sentinel/ctor.parent.pass.cpp
+++ b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.sentinel/ctor.parent.pass.cpp
@@ -7,7 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// UNSUPPORTED: !c++experimental
 
 // constexpr explicit sentinel(Parent& parent);
 
diff --git a/libcxx/test/std/ranges/range.adaptors/range.join.view/sentinel/eq.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.sentinel/eq.pass.cpp
similarity index 81%
rename from libcxx/test/std/ranges/range.adaptors/range.join.view/sentinel/eq.pass.cpp
rename to libcxx/test/std/ranges/range.adaptors/range.join/range.join.sentinel/eq.pass.cpp
index cbd03b84f208..bc7d4bec94d3 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.join.view/sentinel/eq.pass.cpp
+++ b/libcxx/test/std/ranges/range.adaptors/range.join/range.join.sentinel/eq.pass.cpp
@@ -7,7 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14, c++17
-// UNSUPPORTED: !c++experimental
 
 // template<bool OtherConst>
 //   requires sentinel_for<sentinel_t<Base>, iterator_t<maybe-const<OtherConst, V>>>
@@ -17,6 +16,7 @@
 #include <concepts>
 #include <functional>
 #include <ranges>
+#include <type_traits>
 
 #include "../types.h"
 
@@ -61,18 +61,27 @@ static_assert(EqualityComparable<std::ranges::iterator_t<const ConstComparableVi
 constexpr bool test() {
   int buffer[4][4] = {{1111, 2222, 3333, 4444}, {555, 666, 777, 888}, {99, 1010, 1111, 1212}, {13, 14, 15, 16}};
 
+  // test iterator<false> == sentinel<false>
   {
     ChildView children[4] = {ChildView(buffer[0]), ChildView(buffer[1]), ChildView(buffer[2]), ChildView(buffer[3])};
-    auto jv = std::ranges::join_view(ParentView(children));
+    auto jv               = std::ranges::join_view(ParentView(children));
     assert(jv.end() == std::ranges::next(jv.begin(), 16));
-    static_assert(!EqualityComparable<decltype(std::as_const(jv).begin()), decltype(jv.end())>);
-    static_assert(!EqualityComparable<decltype(jv.begin()), decltype(std::as_const(jv).end())>);
   }
 
+  // test iterator<false> == sentinel<true>
+  {
+    ChildView children[4] = {ChildView(buffer[0]), ChildView(buffer[1]), ChildView(buffer[2]), ChildView(buffer[3])};
+    using ParentT         = std::remove_all_extents_t<decltype(children)>;
+    auto jv               = std::ranges::join_view(ForwardParentView<ParentT>(children));
+    assert(std::as_const(jv).end() == std::ranges::next(jv.begin(), 16));
+  }
+
+  // test iterator<true> == sentinel<true>
   {
     CopyableChild children[4] = {CopyableChild(buffer[0]), CopyableChild(buffer[1]), CopyableChild(buffer[2]),
                                  CopyableChild(buffer[3])};
-    const auto jv = std::ranges::join_view(ParentView(children));
+    using ParentT             = std::remove_all_extents_t<decltype(children)>;
+    const auto jv             = std::ranges::join_view(ForwardParentView<ParentT>(children));
     assert(jv.end() == std::ranges::next(jv.begin(), 16));
   }
 
diff --git a/libcxx/test/std/ranges/range.adaptors/range.join.view/types.h b/libcxx/test/std/ranges/range.adaptors/range.join/types.h
similarity index 88%
rename from libcxx/test/std/ranges/range.adaptors/range.join.view/types.h
rename to libcxx/test/std/ranges/range.adaptors/range.join/types.h
index b2ef5f090b57..c1378dc1144b 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.join.view/types.h
+++ b/libcxx/test/std/ranges/range.adaptors/range.join/types.h
@@ -11,6 +11,7 @@
 
 #include <concepts>
 #include <cstdint>
+#include <string>
 #include <tuple>
 
 #include "test_macros.h"
@@ -52,13 +53,13 @@ inline ChildView globalChildren[4] = {
     ChildView(globalBuffer[3]),
 };
 
-template <class T>
+template <class T, template<class...> class Iter = cpp17_input_iterator>
 struct ParentView : std::ranges::view_base {
   T* ptr_;
   unsigned size_;
 
-  using iterator = cpp20_input_iterator<T*>;
-  using const_iterator = cpp20_input_iterator<const T*>;
+  using iterator = Iter<T*>;
+  using const_iterator = Iter<const T*>;
   using sentinel = sentinel_wrapper<iterator>;
   using const_sentinel = sentinel_wrapper<const_iterator>;
 
@@ -80,6 +81,9 @@ struct ParentView : std::ranges::view_base {
 template <class T>
 ParentView(T*) -> ParentView<T>;
 
+template<class T>
+using ForwardParentView = ParentView<T, forward_iterator>;
+
 struct CopyableChild : std::ranges::view_base {
   int* ptr_;
   unsigned size_;
@@ -97,15 +101,16 @@ struct CopyableChild : std::ranges::view_base {
   constexpr const_sentinel end() const { return const_sentinel(const_iterator(ptr_ + size_)); }
 };
 
-struct CopyableParent : std::ranges::view_base {
+template<template<class...> class Iter>
+struct CopyableParentTemplate : std::ranges::view_base {
   CopyableChild* ptr_;
 
-  using iterator = cpp17_input_iterator<CopyableChild*>;
-  using const_iterator = cpp17_input_iterator<const CopyableChild*>;
+  using iterator = Iter<CopyableChild*>;
+  using const_iterator = Iter<const CopyableChild*>;
   using sentinel = sentinel_wrapper<iterator>;
   using const_sentinel = sentinel_wrapper<const_iterator>;
 
-  constexpr CopyableParent(CopyableChild* ptr) : ptr_(ptr) {}
+  constexpr CopyableParentTemplate(CopyableChild* ptr) : ptr_(ptr) {}
 
   constexpr iterator begin() { return iterator(ptr_); }
   constexpr const_iterator begin() const { return const_iterator(ptr_); }
@@ -113,6 +118,9 @@ struct CopyableParent : std::ranges::view_base {
   constexpr const_sentinel end() const { return const_sentinel(const_iterator(ptr_ + 4)); }
 };
 
+using CopyableParent = CopyableParentTemplate<cpp17_input_iterator>;
+using ForwardCopyableParent = CopyableParentTemplate<forward_iterator>;
+
 struct Box {
   int x;
 };
@@ -392,4 +400,48 @@ struct IterMoveSwapAwareView : BufferView<int*> {
 };
 static_assert(std::ranges::input_range<IterMoveSwapAwareView>);
 
+class StashingIterator {
+public:
+  using difference_type = std::ptrdiff_t;
+  using value_type      = std::string;
+
+  constexpr StashingIterator() : letter_('a') {}
+
+  constexpr StashingIterator& operator++() {
+    str_ += letter_;
+    ++letter_;
+    return *this;
+  }
+
+  constexpr void operator++(int) { ++*this; }
+
+  constexpr value_type operator*() const { return str_; }
+
+  constexpr bool operator==(std::default_sentinel_t) const { return letter_ > 'z'; }
+
+private:
+  char letter_;
+  value_type str_;
+};
+
+using StashingRange = std::ranges::subrange<StashingIterator, std::default_sentinel_t>;
+static_assert(std::ranges::input_range<StashingRange>);
+static_assert(!std::ranges::forward_range<StashingRange>);
+
+class ConstNonJoinableRange : public std::ranges::view_base {
+public:
+  constexpr StashingIterator begin() { return {}; }
+  constexpr std::default_sentinel_t end() { return {}; }
+
+  constexpr const int* begin() const { return &val_; }
+  constexpr const int* end() const { return &val_ + 1; }
+
+private:
+  int val_ = 1;
+};
+static_assert(std::ranges::input_range<ConstNonJoinableRange>);
+static_assert(std::ranges::input_range<const ConstNonJoinableRange>);
+static_assert(std::ranges::input_range<std::ranges::range_reference_t<ConstNonJoinableRange>>);
+static_assert(!std::ranges::input_range<std::ranges::range_reference_t<const ConstNonJoinableRange>>);
+
 #endif // TEST_STD_RANGES_RANGE_ADAPTORS_RANGE_JOIN_TYPES_H
diff --git a/libcxx/test/std/re/re.iter/re.regiter/iterator_concept_conformance.compile.pass.cpp b/libcxx/test/std/re/re.iter/re.regiter/iterator_concept_conformance.compile.pass.cpp
index 6f2da091c370..ad61baa76018 100644
--- a/libcxx/test/std/re/re.iter/re.regiter/iterator_concept_conformance.compile.pass.cpp
+++ b/libcxx/test/std/re/re.iter/re.regiter/iterator_concept_conformance.compile.pass.cpp
@@ -14,8 +14,8 @@
 
 #include <iterator>
 
-static_assert(std::forward_iterator<std::cregex_iterator>);
-static_assert(!std::bidirectional_iterator<std::cregex_iterator>);
+static_assert(std::input_iterator<std::cregex_iterator>);
+static_assert(!std::forward_iterator<std::cregex_iterator>);
 static_assert(!std::indirectly_writable<std::cregex_iterator, char>);
 static_assert(std::sentinel_for<std::cregex_iterator, std::cregex_iterator>);
 static_assert(!std::sized_sentinel_for<std::cregex_iterator, std::cregex_iterator>);
diff --git a/libcxx/test/std/re/re.iter/re.regiter/types.pass.cpp b/libcxx/test/std/re/re.iter/re.regiter/types.pass.cpp
index 7d30b0adcc23..8ee2c5006d31 100644
--- a/libcxx/test/std/re/re.iter/re.regiter/types.pass.cpp
+++ b/libcxx/test/std/re/re.iter/re.regiter/types.pass.cpp
@@ -20,6 +20,7 @@
 //     typedef const value_type*                    pointer;
 //     typedef const value_type&                    reference;
 //     typedef forward_iterator_tag                 iterator_category;
+//     typedef input_iterator_tag                   iterator_concept; // since C++20
 
 #include <regex>
 #include <type_traits>
@@ -36,6 +37,9 @@ test()
     static_assert((std::is_same<typename I::pointer, const std::match_results<const CharT*>*>::value), "");
     static_assert((std::is_same<typename I::reference, const std::match_results<const CharT*>&>::value), "");
     static_assert((std::is_same<typename I::iterator_category, std::forward_iterator_tag>::value), "");
+#if TEST_STD_VER >= 20
+    static_assert(std::is_same_v<typename I::iterator_concept, std::input_iterator_tag>);
+#endif
 }
 
 int main(int, char**)
diff --git a/libcxx/test/std/re/re.iter/re.tokiter/iterator_concept_conformance.compile.pass.cpp b/libcxx/test/std/re/re.iter/re.tokiter/iterator_concept_conformance.compile.pass.cpp
index 397226552ede..23eea7f369c1 100644
--- a/libcxx/test/std/re/re.iter/re.tokiter/iterator_concept_conformance.compile.pass.cpp
+++ b/libcxx/test/std/re/re.iter/re.tokiter/iterator_concept_conformance.compile.pass.cpp
@@ -14,8 +14,8 @@
 
 #include <iterator>
 
-static_assert(std::forward_iterator<std::cregex_token_iterator>);
-static_assert(!std::bidirectional_iterator<std::cregex_token_iterator>);
+static_assert(std::input_iterator<std::cregex_token_iterator>);
+static_assert(!std::forward_iterator<std::cregex_token_iterator>);
 static_assert(!std::indirectly_writable<std::cregex_token_iterator, char>);
 static_assert(std::sentinel_for<std::cregex_token_iterator, std::cregex_token_iterator>);
 static_assert(!std::sized_sentinel_for<std::cregex_token_iterator, std::cregex_token_iterator>);
diff --git a/libcxx/test/std/re/re.iter/re.tokiter/types.pass.cpp b/libcxx/test/std/re/re.iter/re.tokiter/types.pass.cpp
index 73ad58f4eecf..a9c18e8a1b77 100644
--- a/libcxx/test/std/re/re.iter/re.tokiter/types.pass.cpp
+++ b/libcxx/test/std/re/re.iter/re.tokiter/types.pass.cpp
@@ -20,6 +20,7 @@
 //     typedef const value_type*                pointer;
 //     typedef const value_type&                reference;
 //     typedef forward_iterator_tag             iterator_category;
+//     typedef input_iterator_tag               iterator_concept; // since C++20
 
 #include <regex>
 #include <type_traits>
@@ -36,6 +37,9 @@ test()
     static_assert((std::is_same<typename I::pointer, const std::sub_match<const CharT*>*>::value), "");
     static_assert((std::is_same<typename I::reference, const std::sub_match<const CharT*>&>::value), "");
     static_assert((std::is_same<typename I::iterator_category, std::forward_iterator_tag>::value), "");
+#if TEST_STD_VER >= 20
+    static_assert(std::is_same_v<typename I::iterator_concept, std::input_iterator_tag>);
+#endif
 }
 
 int main(int, char**)
-- 
GitLab


From 00d809c37409470f4777ecc977c4e9473e6839d3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Timm=20B=C3=A4der?= <tbaeder@redhat.com>
Date: Tue, 12 Dec 2023 13:32:42 +0100
Subject: [PATCH 305/349] [clang][Interp][NFC] Fix a comment typo

---
 clang/lib/AST/Interp/Context.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clang/lib/AST/Interp/Context.cpp b/clang/lib/AST/Interp/Context.cpp
index cb96e56fb5e1..4fe6d1173f42 100644
--- a/clang/lib/AST/Interp/Context.cpp
+++ b/clang/lib/AST/Interp/Context.cpp
@@ -168,7 +168,7 @@ bool Context::Run(State &Parent, const Function *Func, APValue &Result) {
     }
 
     // State gets destroyed here, so the Stk.clear() below doesn't accidentally
-    // remove values the State's destructor might accedd.
+    // remove values the State's destructor might access.
   }
 
   Stk.clear();
-- 
GitLab


From 70c84f80906d389455ffc331b9b9ed7e511df204 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Timm=20B=C3=A4der?= <tbaeder@redhat.com>
Date: Tue, 12 Dec 2023 15:47:22 +0100
Subject: [PATCH 306/349] [clang][NFC] Remove unused parameter

---
 clang/include/clang/Sema/Sema.h  | 3 +--
 clang/lib/Parse/ParseExprCXX.cpp | 2 +-
 clang/lib/Sema/SemaLambda.cpp    | 3 +--
 3 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 1902d098f3c2..1d7b4c729ce8 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -7311,8 +7311,7 @@ public:
 
   /// ActOnLambdaExpr - This is called when the body of a lambda expression
   /// was successfully completed.
-  ExprResult ActOnLambdaExpr(SourceLocation StartLoc, Stmt *Body,
-                             Scope *CurScope);
+  ExprResult ActOnLambdaExpr(SourceLocation StartLoc, Stmt *Body);
 
   /// Does copying/destroying the captured variable have side effects?
   bool CaptureHasSideEffects(const sema::Capture &From);
diff --git a/clang/lib/Parse/ParseExprCXX.cpp b/clang/lib/Parse/ParseExprCXX.cpp
index 8b86db1bb8fc..2fc364fc811b 100644
--- a/clang/lib/Parse/ParseExprCXX.cpp
+++ b/clang/lib/Parse/ParseExprCXX.cpp
@@ -1548,7 +1548,7 @@ ExprResult Parser::ParseLambdaExpressionAfterIntroducer(
 
   if (!Stmt.isInvalid() && !TrailingReturnType.isInvalid() &&
       !D.isInvalidType())
-    return Actions.ActOnLambdaExpr(LambdaBeginLoc, Stmt.get(), getCurScope());
+    return Actions.ActOnLambdaExpr(LambdaBeginLoc, Stmt.get());
 
   Actions.ActOnLambdaError(LambdaBeginLoc, getCurScope());
   return ExprError();
diff --git a/clang/lib/Sema/SemaLambda.cpp b/clang/lib/Sema/SemaLambda.cpp
index 4cc87c9fa765..e7b6443c984c 100644
--- a/clang/lib/Sema/SemaLambda.cpp
+++ b/clang/lib/Sema/SemaLambda.cpp
@@ -1885,8 +1885,7 @@ ExprResult Sema::BuildCaptureInit(const Capture &Cap,
   return InitSeq.Perform(*this, Entity, InitKind, InitExpr);
 }
 
-ExprResult Sema::ActOnLambdaExpr(SourceLocation StartLoc, Stmt *Body,
-                                 Scope *CurScope) {
+ExprResult Sema::ActOnLambdaExpr(SourceLocation StartLoc, Stmt *Body) {
   LambdaScopeInfo LSI = *cast<LambdaScopeInfo>(FunctionScopes.back());
   ActOnFinishFunctionBody(LSI.CallOperator, Body);
   return BuildLambdaExpr(StartLoc, Body->getEndLoc(), &LSI);
-- 
GitLab


From ae85b39396a69afa5c58f06c2f9a4a0d94e94ef6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Dominik=20W=C3=B3jt?= <dominik.wojt@arm.com>
Date: Tue, 12 Dec 2023 15:48:50 +0100
Subject: [PATCH 307/349] [libc++] tests with picolibc: mark fenv tests as
 unsupported (#74610)

The FE_* macros checked for in cfenv.pass.cpp are not required to be
defined, if the relevant options are _not_ available. Picolibc happens
not to provide these on some platforms.
---
 libcxx/test/std/depr/depr.c.headers/fenv_h.compile.pass.cpp | 5 +++--
 libcxx/test/std/numerics/cfenv/cfenv.syn/cfenv.pass.cpp     | 5 +++--
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/libcxx/test/std/depr/depr.c.headers/fenv_h.compile.pass.cpp b/libcxx/test/std/depr/depr.c.headers/fenv_h.compile.pass.cpp
index dcc97573d607..289a3d1e5c63 100644
--- a/libcxx/test/std/depr/depr.c.headers/fenv_h.compile.pass.cpp
+++ b/libcxx/test/std/depr/depr.c.headers/fenv_h.compile.pass.cpp
@@ -6,8 +6,9 @@
 //
 //===----------------------------------------------------------------------===//
 
-// Floating point exceptions are required for the FE_... macros to be defined.
-// XFAIL: LIBCXX-PICOLIBC-FIXME
+// Picolibc does not define some of the floating point environment macros for
+// arm platforms without hardware floating point support.
+// UNSUPPORTED: LIBCXX-PICOLIBC-FIXME
 
 // <fenv.h>
 
diff --git a/libcxx/test/std/numerics/cfenv/cfenv.syn/cfenv.pass.cpp b/libcxx/test/std/numerics/cfenv/cfenv.syn/cfenv.pass.cpp
index 7b3b490eba27..e6244c745549 100644
--- a/libcxx/test/std/numerics/cfenv/cfenv.syn/cfenv.pass.cpp
+++ b/libcxx/test/std/numerics/cfenv/cfenv.syn/cfenv.pass.cpp
@@ -6,8 +6,9 @@
 //
 //===----------------------------------------------------------------------===//
 
-// Floating point exceptions are required for the FE_... macros to be defined.
-// XFAIL: LIBCXX-PICOLIBC-FIXME
+// Picolibc does not define some of the floating point environment macros for
+// arm platforms without hardware floating point support.
+// UNSUPPORTED: LIBCXX-PICOLIBC-FIXME
 
 // <cfenv>
 
-- 
GitLab


From c8655fce45af6f2c13285f218bba83d39c84d5a4 Mon Sep 17 00:00:00 2001
From: David Spickett <david.spickett@linaro.org>
Date: Tue, 12 Dec 2023 14:43:01 +0000
Subject: [PATCH 308/349] [GitHub] Remove author association print from new-prs
 workflow

Turns out, new contrbiutor association is in fact `NONE`.

Example: https://github.com/llvm/llvm-project/pull/75182

```
Run echo "$AUTHOR_ASSOCIATION"
NONE
```
---
 .github/workflows/new-prs.yml | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/.github/workflows/new-prs.yml b/.github/workflows/new-prs.yml
index 23455c57ea77..23fab598fc77 100644
--- a/.github/workflows/new-prs.yml
+++ b/.github/workflows/new-prs.yml
@@ -41,14 +41,6 @@ jobs:
           chmod a+x github-automation.py
           pip install -r requirements.txt
 
-      # Will be removed shortly, just gathering info to report to Github that
-      # this is not working as expected.
-      - name: Dump Author Association
-        env:
-          AUTHOR_ASSOCIATION: ${{ github.event.pull_request.author_association }}
-        run: |
-          echo "$AUTHOR_ASSOCIATION"
-
       - name: Greet Author
         run: |
           ./github-automation.py \
-- 
GitLab


From 5457fab15cd210cd7d89278bea173dc5d0261d3b Mon Sep 17 00:00:00 2001
From: OCHyams <orlando.hyams@sony.com>
Date: Tue, 12 Dec 2023 14:46:01 +0000
Subject: [PATCH 309/349] Reapply "[RemoveDIs][NFC] Find DPValues using
 findDbgDeclares  (#73500)"

This patch doesn't change any call sites.

Depends on #73498.

Reverted in 87c686700f68ce24191f027082ef5fb9a654e9d8.
---
 llvm/include/llvm/IR/DebugInfo.h              |  3 +-
 .../include/llvm/IR/DebugProgramInstruction.h |  3 ++
 llvm/lib/IR/DebugInfo.cpp                     | 42 +++++++------------
 llvm/lib/IR/DebugProgramInstruction.cpp       |  4 ++
 4 files changed, 25 insertions(+), 27 deletions(-)

diff --git a/llvm/include/llvm/IR/DebugInfo.h b/llvm/include/llvm/IR/DebugInfo.h
index 5ed423bfd1c1..36ef77f9505b 100644
--- a/llvm/include/llvm/IR/DebugInfo.h
+++ b/llvm/include/llvm/IR/DebugInfo.h
@@ -40,7 +40,8 @@ class Module;
 
 /// Finds dbg.declare intrinsics declaring local variables as living in the
 /// memory that 'V' points to.
-void findDbgDeclares(SmallVectorImpl<DbgDeclareInst *> &DbgUsers, Value *V);
+void findDbgDeclares(SmallVectorImpl<DbgDeclareInst *> &DbgUsers, Value *V,
+                     SmallVectorImpl<DPValue *> *DPValues = nullptr);
 
 /// Finds the llvm.dbg.value intrinsics describing a value.
 void findDbgValues(SmallVectorImpl<DbgValueInst *> &DbgValues,
diff --git a/llvm/include/llvm/IR/DebugProgramInstruction.h b/llvm/include/llvm/IR/DebugProgramInstruction.h
index f73a6237a477..8230070343e0 100644
--- a/llvm/include/llvm/IR/DebugProgramInstruction.h
+++ b/llvm/include/llvm/IR/DebugProgramInstruction.h
@@ -97,6 +97,9 @@ public:
   enum class LocationType {
     Declare,
     Value,
+
+    End, ///< Marks the end of the concrete types.
+    Any, ///< To indicate all LocationTypes in searches.
   };
   /// Classification of the debug-info record that this DPValue represents.
   /// Essentially, "is this a dbg.value or dbg.declare?". dbg.declares are not
diff --git a/llvm/lib/IR/DebugInfo.cpp b/llvm/lib/IR/DebugInfo.cpp
index b3cc9996ace4..eab05eed428e 100644
--- a/llvm/lib/IR/DebugInfo.cpp
+++ b/llvm/lib/IR/DebugInfo.cpp
@@ -44,28 +44,10 @@ using namespace llvm;
 using namespace llvm::at;
 using namespace llvm::dwarf;
 
-void llvm::findDbgDeclares(SmallVectorImpl<DbgDeclareInst *> &DbgUsers,
-                           Value *V) {
-  // This function is hot. Check whether the value has any metadata to avoid a
-  // DenseMap lookup.
-  if (!V->isUsedByMetadata())
-    return;
-  auto *L = LocalAsMetadata::getIfExists(V);
-  if (!L)
-    return;
-  auto *MDV = MetadataAsValue::getIfExists(V->getContext(), L);
-  if (!MDV)
-    return;
-
-  for (User *U : MDV->users()) {
-    if (auto *DDI = dyn_cast<DbgDeclareInst>(U))
-      DbgUsers.push_back(DDI);
-  }
-}
-
-template <typename IntrinsicT>
-static void findDbgIntrinsics(SmallVectorImpl<IntrinsicT *> &Result,
-                              Value *V, SmallVectorImpl<DPValue *> *DPValues) {
+template <typename IntrinsicT,
+          DPValue::LocationType Type = DPValue::LocationType::Any>
+static void findDbgIntrinsics(SmallVectorImpl<IntrinsicT *> &Result, Value *V,
+                              SmallVectorImpl<DPValue *> *DPValues) {
   // This function is hot. Check whether the value has any metadata to avoid a
   // DenseMap lookup.
   if (!V->isUsedByMetadata())
@@ -94,7 +76,7 @@ static void findDbgIntrinsics(SmallVectorImpl<IntrinsicT *> &Result,
     // Get DPValues that use this as a single value.
     if (LocalAsMetadata *L = dyn_cast<LocalAsMetadata>(MD)) {
       for (DPValue *DPV : L->getAllDPValueUsers()) {
-        if (DPV->getType() == DPValue::LocationType::Value)
+        if (Type == DPValue::LocationType::Any || DPV->getType() == Type)
           DPValues->push_back(DPV);
       }
     }
@@ -108,21 +90,29 @@ static void findDbgIntrinsics(SmallVectorImpl<IntrinsicT *> &Result,
         continue;
       DIArgList *DI = cast<DIArgList>(AL);
       for (DPValue *DPV : DI->getAllDPValueUsers())
-        if (DPV->getType() == DPValue::LocationType::Value)
+        if (Type == DPValue::LocationType::Any || DPV->getType() == Type)
           if (EncounteredDPValues.insert(DPV).second)
             DPValues->push_back(DPV);
     }
   }
 }
 
+void llvm::findDbgDeclares(SmallVectorImpl<DbgDeclareInst *> &DbgUsers,
+                           Value *V, SmallVectorImpl<DPValue *> *DPValues) {
+  findDbgIntrinsics<DbgDeclareInst, DPValue::LocationType::Declare>(DbgUsers, V,
+                                                                    DPValues);
+}
+
 void llvm::findDbgValues(SmallVectorImpl<DbgValueInst *> &DbgValues,
                          Value *V, SmallVectorImpl<DPValue *> *DPValues) {
-  findDbgIntrinsics<DbgValueInst>(DbgValues, V, DPValues);
+  findDbgIntrinsics<DbgValueInst, DPValue::LocationType::Value>(DbgValues, V,
+                                                                DPValues);
 }
 
 void llvm::findDbgUsers(SmallVectorImpl<DbgVariableIntrinsic *> &DbgUsers,
                         Value *V, SmallVectorImpl<DPValue *> *DPValues) {
-  findDbgIntrinsics<DbgVariableIntrinsic>(DbgUsers, V, DPValues);
+  findDbgIntrinsics<DbgVariableIntrinsic, DPValue::LocationType::Any>(
+      DbgUsers, V, DPValues);
 }
 
 DISubprogram *llvm::getDISubprogram(const MDNode *Scope) {
diff --git a/llvm/lib/IR/DebugProgramInstruction.cpp b/llvm/lib/IR/DebugProgramInstruction.cpp
index df45c6ea3a77..7b709a2de033 100644
--- a/llvm/lib/IR/DebugProgramInstruction.cpp
+++ b/llvm/lib/IR/DebugProgramInstruction.cpp
@@ -203,6 +203,10 @@ DPValue::createDebugIntrinsic(Module *M, Instruction *InsertBefore) const {
   case DPValue::LocationType::Value:
     IntrinsicFn = Intrinsic::getDeclaration(M, Intrinsic::dbg_value);
     break;
+  case DPValue::LocationType::End:
+  case DPValue::LocationType::Any:
+    llvm_unreachable("Invalid LocationType");
+    break;
   }
 
   // Create the intrinsic from this DPValue's information, optionally insert
-- 
GitLab


From 300ac0aa85864ddd4ec1b5eb65ae52918434d003 Mon Sep 17 00:00:00 2001
From: Orlando Cazalet-Hyams <orlando.hyams@sony.com>
Date: Tue, 12 Dec 2023 14:53:27 +0000
Subject: [PATCH 310/349] [RemoveDIs] Fix removeRedundantDdbgInstrs utils for
 dbg.declares (#74102)

The intrinsic variants of these functions don't do anything to
dbg.declares so the non-instruction variants should ignore them too.

Tested in llvm/test/DebugInfo/duplicate_dbgvalue.ll, which has
`--try-experimental-debuginfo-iterators` added in #73504.

The tests will become "live" once #74090 lands (see for more info).
---
 llvm/lib/Transforms/Utils/BasicBlockUtils.cpp | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp b/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
index b700edf8ea6c..8b5a6d618412 100644
--- a/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
+++ b/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
@@ -387,6 +387,18 @@ static bool DPValuesRemoveRedundantDbgInstrsUsingBackwardScan(BasicBlock *BB) {
   SmallDenseSet<DebugVariable> VariableSet;
   for (auto &I : reverse(*BB)) {
     for (DPValue &DPV : reverse(I.getDbgValueRange())) {
+      // Skip declare-type records, as the debug intrinsic method only works
+      // on dbg.value intrinsics.
+      if (DPV.getType() == DPValue::LocationType::Declare) {
+        // The debug intrinsic method treats dbg.declares are "non-debug"
+        // instructions (i.e., a break in a consecutive range of debug
+        // intrinsics). Emulate that to create identical outputs. See
+        // "Possible improvements" above.
+        // FIXME: Delete the line below.
+        VariableSet.clear();
+        continue;
+      }
+
       DebugVariable Key(DPV.getVariable(), DPV.getExpression(),
                         DPV.getDebugLoc()->getInlinedAt());
       auto R = VariableSet.insert(Key);
@@ -478,6 +490,8 @@ static bool DPValuesRemoveRedundantDbgInstrsUsingForwardScan(BasicBlock *BB) {
       VariableMap;
   for (auto &I : *BB) {
     for (DPValue &DPV : I.getDbgValueRange()) {
+      if (DPV.getType() == DPValue::LocationType::Declare)
+        continue;
       DebugVariable Key(DPV.getVariable(), std::nullopt,
                         DPV.getDebugLoc()->getInlinedAt());
       auto VMI = VariableMap.find(Key);
-- 
GitLab


From f22a65c158b4195120e250bf5decaed3ea5ac3bd Mon Sep 17 00:00:00 2001
From: Guillaume Chatelet <gchatelet@google.com>
Date: Tue, 12 Dec 2023 15:56:06 +0100
Subject: [PATCH 311/349] [libc][NFC] Reuse `FloatProperties` constant instead
 of creating new ones (#75187)

Also exposes a bit more of `FloatProperties` and adds documentation.
This should have been several patches but I was lazy.
---
 libc/src/__support/FPUtil/FloatProperties.h   | 38 ++++++++------
 .../__support/FPUtil/x86_64/LongDoubleBits.h  | 18 +------
 libc/src/__support/float_to_string.h          |  9 ++--
 libc/src/__support/str_to_float.h             | 52 ++++++++++---------
 4 files changed, 55 insertions(+), 62 deletions(-)

diff --git a/libc/src/__support/FPUtil/FloatProperties.h b/libc/src/__support/FPUtil/FloatProperties.h
index 7f396a649e4f..3f7dbdc5af34 100644
--- a/libc/src/__support/FPUtil/FloatProperties.h
+++ b/libc/src/__support/FPUtil/FloatProperties.h
@@ -87,49 +87,57 @@ template <FPType fp_type>
 struct FPProperties : public internal::FPBaseProperties<fp_type> {
 private:
   using UP = internal::FPBaseProperties<fp_type>;
-  using UP::EXP_BITS;
-  using UP::SIG_BITS;
-  using UP::TOTAL_BITS;
+  // The number of bits to represent sign. For documentation purpose, always 1.
+  LIBC_INLINE_VAR static constexpr int SIGN_BITS = 1;
+  using UP::EXP_BITS;   // The number of bits for the *exponent* part
+  using UP::SIG_BITS;   // The number of bits for the *significand* part
+  using UP::TOTAL_BITS; // For convenience, the sum of `SIG_BITS`, `EXP_BITS`,
+                        // and `SIGN_BITS`.
+  static_assert(SIGN_BITS + EXP_BITS + SIG_BITS == TOTAL_BITS);
 
 public:
+  // An unsigned integer that is wide enough to contain all of the floating
+  // point bits.
   using UIntType = typename UP::UIntType;
 
-private:
-  LIBC_INLINE_VAR static constexpr int STORAGE_BITS =
+  // The number of bits in UIntType.
+  LIBC_INLINE_VAR static constexpr int UINTTYPE_BITS =
       sizeof(UIntType) * CHAR_BIT;
-  static_assert(STORAGE_BITS >= TOTAL_BITS);
-
-  // The number of bits to represent sign.
-  // For documentation purpose, always 1.
-  LIBC_INLINE_VAR static constexpr int SIGN_BITS = 1;
-  static_assert(SIGN_BITS + EXP_BITS + SIG_BITS == TOTAL_BITS);
+  static_assert(UINTTYPE_BITS >= TOTAL_BITS);
 
+private:
   // The exponent bias. Always positive.
   LIBC_INLINE_VAR static constexpr int32_t EXP_BIAS =
       (1U << (EXP_BITS - 1U)) - 1U;
   static_assert(EXP_BIAS > 0);
 
-  // Shifts
+  // The shift amount to get the *significand* part to the least significant
+  // bit. Always `0` but kept for consistency.
   LIBC_INLINE_VAR static constexpr int SIG_MASK_SHIFT = 0;
+  // The shift amount to get the *exponent* part to the least significant bit.
   LIBC_INLINE_VAR static constexpr int EXP_MASK_SHIFT = SIG_BITS;
+  // The shift amount to get the *sign* part to the least significant bit.
   LIBC_INLINE_VAR static constexpr int SIGN_MASK_SHIFT = SIG_BITS + EXP_BITS;
 
-  // Masks
+  // The bit pattern that keeps only the *significand* part.
   LIBC_INLINE_VAR static constexpr UIntType SIG_MASK =
       mask_trailing_ones<UIntType, SIG_BITS>() << SIG_MASK_SHIFT;
+  // The bit pattern that keeps only the *exponent* part.
   LIBC_INLINE_VAR static constexpr UIntType EXP_MASK =
       mask_trailing_ones<UIntType, EXP_BITS>() << EXP_MASK_SHIFT;
 
 public:
+  // The bit pattern that keeps only the *sign* part.
   LIBC_INLINE_VAR static constexpr UIntType SIGN_MASK =
       mask_trailing_ones<UIntType, SIGN_BITS>() << SIGN_MASK_SHIFT;
-
-private:
+  // The bit pattern that keeps only the *sign + exponent + significand* part.
   LIBC_INLINE_VAR static constexpr UIntType FP_MASK =
       mask_trailing_ones<UIntType, TOTAL_BITS>();
+
   static_assert((SIG_MASK & EXP_MASK & SIGN_MASK) == 0, "masks disjoint");
   static_assert((SIG_MASK | EXP_MASK | SIGN_MASK) == FP_MASK, "masks cover");
 
+private:
   LIBC_INLINE static constexpr UIntType bit_at(int position) {
     return UIntType(1) << position;
   }
diff --git a/libc/src/__support/FPUtil/x86_64/LongDoubleBits.h b/libc/src/__support/FPUtil/x86_64/LongDoubleBits.h
index 60953313a695..f1ef928f2308 100644
--- a/libc/src/__support/FPUtil/x86_64/LongDoubleBits.h
+++ b/libc/src/__support/FPUtil/x86_64/LongDoubleBits.h
@@ -26,18 +26,6 @@
 namespace LIBC_NAMESPACE {
 namespace fputil {
 
-template <unsigned Width> struct Padding;
-
-// i386 padding.
-template <> struct Padding<4> {
-  static constexpr unsigned VALUE = 16;
-};
-
-// x86_64 padding.
-template <> struct Padding<8> {
-  static constexpr unsigned VALUE = 48;
-};
-
 template <> struct FPBits<long double> {
   using UIntType = UInt128;
 
@@ -129,11 +117,7 @@ template <> struct FPBits<long double> {
 
   LIBC_INLINE constexpr UIntType uintval() {
     // We zero the padding bits as they can contain garbage.
-    constexpr UIntType MASK =
-        (UIntType(1) << (sizeof(long double) * 8 -
-                         Padding<sizeof(uintptr_t)>::VALUE)) -
-        1;
-    return bits & MASK;
+    return bits & FloatProp::FP_MASK;
   }
 
   LIBC_INLINE constexpr long double get_val() const {
diff --git a/libc/src/__support/float_to_string.h b/libc/src/__support/float_to_string.h
index 34c0c0ceef28..be105830a91a 100644
--- a/libc/src/__support/float_to_string.h
+++ b/libc/src/__support/float_to_string.h
@@ -105,7 +105,7 @@ namespace LIBC_NAMESPACE {
 using BlockInt = uint32_t;
 constexpr uint32_t BLOCK_SIZE = 9;
 
-using MantissaInt = fputil::FPBits<long double>::UIntType;
+using FloatProp = fputil::FloatProperties<long double>;
 
 // Larger numbers prefer a slightly larger constant than is used for the smaller
 // numbers.
@@ -382,11 +382,10 @@ LIBC_INLINE uint32_t fast_uint_mod_1e9(const cpp::UInt<MID_INT_SIZE> &val) {
                                (1000000000 * shifted));
 }
 
-LIBC_INLINE uint32_t mul_shift_mod_1e9(const MantissaInt mantissa,
+LIBC_INLINE uint32_t mul_shift_mod_1e9(const FloatProp::UIntType mantissa,
                                        const cpp::UInt<MID_INT_SIZE> &large,
                                        const int32_t shift_amount) {
-  constexpr size_t MANT_INT_SIZE = sizeof(MantissaInt) * 8;
-  cpp::UInt<MID_INT_SIZE + MANT_INT_SIZE> val(large);
+  cpp::UInt<MID_INT_SIZE + FloatProp::UINTTYPE_BITS> val(large);
   val = (val * mantissa) >> shift_amount;
   return static_cast<uint32_t>(
       val.div_uint32_times_pow_2(1000000000, 0).value());
@@ -415,7 +414,7 @@ class FloatToString {
   fputil::FPBits<T> float_bits;
   bool is_negative;
   int exponent;
-  MantissaInt mantissa;
+  FloatProp::UIntType mantissa;
 
   static constexpr int MANT_WIDTH = fputil::MantissaWidth<T>::VALUE;
   static constexpr int EXP_BIAS = fputil::FPBits<T>::EXPONENT_BIAS;
diff --git a/libc/src/__support/str_to_float.h b/libc/src/__support/str_to_float.h
index 79d35682d0b7..2a6f15c018f1 100644
--- a/libc/src/__support/str_to_float.h
+++ b/libc/src/__support/str_to_float.h
@@ -77,8 +77,6 @@ eisel_lemire(ExpandedFloat<T> init_num,
   UIntType mantissa = init_num.mantissa;
   int32_t exp10 = init_num.exponent;
 
-  constexpr uint32_t BITS_IN_MANTISSA = sizeof(mantissa) * 8;
-
   if (sizeof(T) > 8) { // This algorithm cannot handle anything longer than a
                        // double, so we skip straight to the fallback.
     return cpp::nullopt;
@@ -94,8 +92,8 @@ eisel_lemire(ExpandedFloat<T> init_num,
   uint32_t clz = cpp::countl_zero<UIntType>(mantissa);
   mantissa <<= clz;
 
-  int32_t exp2 =
-      exp10_to_exp2(exp10) + BITS_IN_MANTISSA + FloatProp::EXPONENT_BIAS - clz;
+  int32_t exp2 = exp10_to_exp2(exp10) + FloatProp::UINTTYPE_BITS +
+                 FloatProp::EXPONENT_BIAS - clz;
 
   // Multiplication
   const uint64_t *power_of_ten =
@@ -112,7 +110,9 @@ eisel_lemire(ExpandedFloat<T> init_num,
   // accuracy, and the most significant bit is ignored.) = 9 bits. Similarly,
   // it's 6 bits for floats in this case.
   const uint64_t halfway_constant =
-      (uint64_t(1) << (BITS_IN_MANTISSA - (FloatProp::MANTISSA_WIDTH + 3))) - 1;
+      (uint64_t(1) << (FloatProp::UINTTYPE_BITS -
+                       (FloatProp::MANTISSA_WIDTH + 3))) -
+      1;
   if ((high64(first_approx) & halfway_constant) == halfway_constant &&
       low64(first_approx) + mantissa < mantissa) {
     UInt128 low_bits =
@@ -131,11 +131,11 @@ eisel_lemire(ExpandedFloat<T> init_num,
   }
 
   // Shifting to 54 bits for doubles and 25 bits for floats
-  UIntType msb =
-      static_cast<UIntType>(high64(final_approx) >> (BITS_IN_MANTISSA - 1));
+  UIntType msb = static_cast<UIntType>(high64(final_approx) >>
+                                       (FloatProp::UINTTYPE_BITS - 1));
   UIntType final_mantissa = static_cast<UIntType>(
       high64(final_approx) >>
-      (msb + BITS_IN_MANTISSA - (FloatProp::MANTISSA_WIDTH + 3)));
+      (msb + FloatProp::UINTTYPE_BITS - (FloatProp::MANTISSA_WIDTH + 3)));
   exp2 -= static_cast<uint32_t>(1 ^ msb); // same as !msb
 
   if (round == RoundDirection::Nearest) {
@@ -190,8 +190,6 @@ eisel_lemire<long double>(ExpandedFloat<long double> init_num,
   UIntType mantissa = init_num.mantissa;
   int32_t exp10 = init_num.exponent;
 
-  constexpr uint32_t BITS_IN_MANTISSA = sizeof(mantissa) * 8;
-
   // Exp10 Range
   // This doesn't reach very far into the range for long doubles, since it's
   // sized for doubles and their 11 exponent bits, and not for long doubles and
@@ -211,8 +209,8 @@ eisel_lemire<long double>(ExpandedFloat<long double> init_num,
   uint32_t clz = cpp::countl_zero<UIntType>(mantissa);
   mantissa <<= clz;
 
-  int32_t exp2 =
-      exp10_to_exp2(exp10) + BITS_IN_MANTISSA + FloatProp::EXPONENT_BIAS - clz;
+  int32_t exp2 = exp10_to_exp2(exp10) + FloatProp::UINTTYPE_BITS +
+                 FloatProp::EXPONENT_BIAS - clz;
 
   // Multiplication
   const uint64_t *power_of_ten =
@@ -249,7 +247,9 @@ eisel_lemire<long double>(ExpandedFloat<long double> init_num,
   // accuracy, and the most significant bit is ignored.) = 61 bits. Similarly,
   // it's 12 bits for 128 bit floats in this case.
   constexpr UInt128 HALFWAY_CONSTANT =
-      (UInt128(1) << (BITS_IN_MANTISSA - (FloatProp::MANTISSA_WIDTH + 3))) - 1;
+      (UInt128(1) << (FloatProp::UINTTYPE_BITS -
+                      (FloatProp::MANTISSA_WIDTH + 3))) -
+      1;
 
   if ((final_approx_upper & HALFWAY_CONSTANT) == HALFWAY_CONSTANT &&
       final_approx_lower + mantissa < mantissa) {
@@ -257,11 +257,11 @@ eisel_lemire<long double>(ExpandedFloat<long double> init_num,
   }
 
   // Shifting to 65 bits for 80 bit floats and 113 bits for 128 bit floats
-  uint32_t msb =
-      static_cast<uint32_t>(final_approx_upper >> (BITS_IN_MANTISSA - 1));
+  uint32_t msb = static_cast<uint32_t>(final_approx_upper >>
+                                       (FloatProp::UINTTYPE_BITS - 1));
   UIntType final_mantissa =
       final_approx_upper >>
-      (msb + BITS_IN_MANTISSA - (FloatProp::MANTISSA_WIDTH + 3));
+      (msb + FloatProp::UINTTYPE_BITS - (FloatProp::MANTISSA_WIDTH + 3));
   exp2 -= static_cast<uint32_t>(1 ^ msb); // same as !msb
 
   if (round == RoundDirection::Nearest) {
@@ -622,9 +622,10 @@ template <> constexpr int32_t get_upper_bound<double>() { return 309; }
 // other out, and subnormal numbers allow for the result to be at the very low
 // end of the final mantissa.
 template <typename T> constexpr int32_t get_lower_bound() {
-  return -((fputil::FloatProperties<T>::EXPONENT_BIAS +
-            static_cast<int32_t>(fputil::FloatProperties<T>::MANTISSA_WIDTH +
-                                 (sizeof(T) * 8))) /
+  using FloatProp = typename fputil::FloatProperties<T>;
+  return -((FloatProp::EXPONENT_BIAS +
+            static_cast<int32_t>(FloatProp::MANTISSA_WIDTH +
+                                 FloatProp::UINTTYPE_BITS)) /
            3);
 }
 
@@ -733,7 +734,6 @@ LIBC_INLINE FloatConvertReturn<T> binary_exp_to_float(ExpandedFloat<T> init_num,
 
   // This is the number of leading zeroes a properly normalized float of type T
   // should have.
-  constexpr int32_t NUMBITS = sizeof(UIntType) * 8;
   constexpr int32_t INF_EXP = (1 << FloatProp::EXPONENT_WIDTH) - 1;
 
   // Normalization step 1: Bring the leading bit to the highest bit of UIntType.
@@ -743,8 +743,9 @@ LIBC_INLINE FloatConvertReturn<T> binary_exp_to_float(ExpandedFloat<T> init_num,
   // Keep exp2 representing the exponent of the lowest bit of UIntType.
   exp2 -= amount_to_shift_left;
 
-  // biasedExponent represents the biased exponent of the most significant bit.
-  int32_t biased_exponent = exp2 + NUMBITS + FPBits::EXPONENT_BIAS - 1;
+  // biased_exponent represents the biased exponent of the most significant bit.
+  int32_t biased_exponent =
+      exp2 + FloatProp::UINTTYPE_BITS + FPBits::EXPONENT_BIAS - 1;
 
   // Handle numbers that're too large and get squashed to inf
   if (biased_exponent >= INF_EXP) {
@@ -754,14 +755,15 @@ LIBC_INLINE FloatConvertReturn<T> binary_exp_to_float(ExpandedFloat<T> init_num,
     return output;
   }
 
-  uint32_t amount_to_shift_right = NUMBITS - FloatProp::MANTISSA_WIDTH - 1;
+  uint32_t amount_to_shift_right =
+      FloatProp::UINTTYPE_BITS - FloatProp::MANTISSA_WIDTH - 1;
 
   // Handle subnormals.
   if (biased_exponent <= 0) {
     amount_to_shift_right += 1 - biased_exponent;
     biased_exponent = 0;
 
-    if (amount_to_shift_right > NUMBITS) {
+    if (amount_to_shift_right > FloatProp::UINTTYPE_BITS) {
       // Return 0 if the exponent is too small.
       output.num = {0, 0};
       output.error = ERANGE;
@@ -774,7 +776,7 @@ LIBC_INLINE FloatConvertReturn<T> binary_exp_to_float(ExpandedFloat<T> init_num,
   bool round_bit = static_cast<bool>(mantissa & round_bit_mask);
   bool sticky_bit = static_cast<bool>(mantissa & sticky_mask) || truncated;
 
-  if (amount_to_shift_right < NUMBITS) {
+  if (amount_to_shift_right < FloatProp::UINTTYPE_BITS) {
     // Shift the mantissa and clear the implicit bit.
     mantissa >>= amount_to_shift_right;
     mantissa &= FloatProp::MANTISSA_MASK;
-- 
GitLab


From c4e764ea24eb02b6ec34038061cee8ff94c0f34c Mon Sep 17 00:00:00 2001
From: Orlando Cazalet-Hyams <orlando.hyams@sony.com>
Date: Tue, 12 Dec 2023 14:57:51 +0000
Subject: [PATCH 312/349] [RemoveDIs] Update ConvertDebugDeclareToDebugValue
 after #72276 (#73508)

That patch was missing a recent change to the non-DPValue StoreInst overload.
Add it to the DPValue version. This is tested by
`llvm/tests/Transforms/Mem2Reg/dbg_declare_to_value_conversions.ll`,
which already has `--try-experimental-debuginfo-iterators`. It doesn't
fail currently because until #74090 lands the declares are not converted
to DPValues.

The tests will become "live" once #74090 lands (see for more info).
---
 llvm/lib/Transforms/Utils/Local.cpp | 40 +++++++++++++++++++----------
 1 file changed, 27 insertions(+), 13 deletions(-)

diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp
index ff92abb77ac2..63dcb6446164 100644
--- a/llvm/lib/Transforms/Utils/Local.cpp
+++ b/llvm/lib/Transforms/Utils/Local.cpp
@@ -1775,23 +1775,37 @@ void llvm::ConvertDebugDeclareToDebugValue(DPValue *DPV, StoreInst *SI,
 
   DebugLoc NewLoc = getDebugValueLoc(DPV);
 
-  if (!valueCoversEntireFragment(DV->getType(), DPV)) {
-    // FIXME: If storing to a part of the variable described by the dbg.declare,
-    // then we want to insert a DPValue.value for the corresponding fragment.
-    LLVM_DEBUG(dbgs() << "Failed to convert dbg.declare to DPValue: " << *DPV
-                      << '\n');
-    // For now, when there is a store to parts of the variable (but we do not
-    // know which part) we insert an DPValue record to indicate that we know
-    // nothing about the variable's content.
-    DV = UndefValue::get(DV->getType());
-    ValueAsMetadata *DVAM = ValueAsMetadata::get(DV);
-    DPValue *NewDPV = new DPValue(DVAM, DIVar, DIExpr, NewLoc.get());
-    SI->getParent()->insertDPValueBefore(NewDPV, SI->getIterator());
+  // If the alloca describes the variable itself, i.e. the expression in the
+  // dbg.declare doesn't start with a dereference, we can perform the
+  // conversion if the value covers the entire fragment of DII.
+  // If the alloca describes the *address* of DIVar, i.e. DIExpr is
+  // *just* a DW_OP_deref, we use DV as is for the dbg.value.
+  // We conservatively ignore other dereferences, because the following two are
+  // not equivalent:
+  //     dbg.declare(alloca, ..., !Expr(deref, plus_uconstant, 2))
+  //     dbg.value(DV, ..., !Expr(deref, plus_uconstant, 2))
+  // The former is adding 2 to the address of the variable, whereas the latter
+  // is adding 2 to the value of the variable. As such, we insist on just a
+  // deref expression.
+  bool CanConvert =
+      DIExpr->isDeref() || (!DIExpr->startsWithDeref() &&
+                            valueCoversEntireFragment(DV->getType(), DPV));
+  if (CanConvert) {
+    insertDbgValueOrDPValue(Builder, DV, DIVar, DIExpr, NewLoc,
+                            SI->getIterator());
     return;
   }
 
+  // FIXME: If storing to a part of the variable described by the dbg.declare,
+  // then we want to insert a dbg.value for the corresponding fragment.
+  LLVM_DEBUG(dbgs() << "Failed to convert dbg.declare to dbg.value: " << *DPV
+                    << '\n');
   assert(UseNewDbgInfoFormat);
-  // Create a DPValue directly and insert.
+
+  // For now, when there is a store to parts of the variable (but we do not
+  // know which part) we insert an dbg.value intrinsic to indicate that we
+  // know nothing about the variable's content.
+  DV = UndefValue::get(DV->getType());
   ValueAsMetadata *DVAM = ValueAsMetadata::get(DV);
   DPValue *NewDPV = new DPValue(DVAM, DIVar, DIExpr, NewLoc.get());
   SI->getParent()->insertDPValueBefore(NewDPV, SI->getIterator());
-- 
GitLab


From d9671bba3e3a4f60302cbc110beede1c864e645b Mon Sep 17 00:00:00 2001
From: Timm Baeder <tbaeder@redhat.com>
Date: Tue, 12 Dec 2023 15:59:39 +0100
Subject: [PATCH 313/349] [clang][Interp] Implement __builtin_ffs (#72988)

---
 clang/lib/AST/Interp/InterpBuiltin.cpp      | 18 ++++++++++++++++++
 clang/test/AST/Interp/builtin-functions.cpp | 10 ++++++++++
 2 files changed, 28 insertions(+)

diff --git a/clang/lib/AST/Interp/InterpBuiltin.cpp b/clang/lib/AST/Interp/InterpBuiltin.cpp
index deba38e4e9dd..b55b1569a259 100644
--- a/clang/lib/AST/Interp/InterpBuiltin.cpp
+++ b/clang/lib/AST/Interp/InterpBuiltin.cpp
@@ -602,6 +602,17 @@ static bool interp__builtin_rotate(InterpState &S, CodePtr OpPC,
   return true;
 }
 
+static bool interp__builtin_ffs(InterpState &S, CodePtr OpPC,
+                                const InterpFrame *Frame, const Function *Func,
+                                const CallExpr *Call) {
+  PrimType ArgT = *S.getContext().classify(Call->getArg(0)->getType());
+  APSInt Value = peekToAPSInt(S.Stk, ArgT);
+
+  uint64_t N = Value.countr_zero();
+  pushInt(S, N == Value.getBitWidth() ? 0 : N + 1);
+  return true;
+}
+
 bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const Function *F,
                       const CallExpr *Call) {
   InterpFrame *Frame = S.Current;
@@ -803,6 +814,13 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const Function *F,
       return false;
     break;
 
+  case Builtin::BI__builtin_ffs:
+  case Builtin::BI__builtin_ffsl:
+  case Builtin::BI__builtin_ffsll:
+    if (!interp__builtin_ffs(S, OpPC, Frame, F, Call))
+      return false;
+    break;
+
   default:
     return false;
   }
diff --git a/clang/test/AST/Interp/builtin-functions.cpp b/clang/test/AST/Interp/builtin-functions.cpp
index 62fe9b081c78..ce7c8bd35790 100644
--- a/clang/test/AST/Interp/builtin-functions.cpp
+++ b/clang/test/AST/Interp/builtin-functions.cpp
@@ -353,3 +353,13 @@ namespace rotateright {
   char rotateright3[__builtin_rotateright32(0x76543210, 22) == 0x50C841D9 ? 1 : -1];
   char rotateright4[__builtin_rotateright64(0xFEDCBA9876543210ULL, 55) == 0xB97530ECA86421FDULL ? 1 : -1];
 }
+
+namespace ffs {
+  char ffs1[__builtin_ffs(0) == 0 ? 1 : -1];
+  char ffs2[__builtin_ffs(1) == 1 ? 1 : -1];
+  char ffs3[__builtin_ffs(0xfbe71) == 1 ? 1 : -1];
+  char ffs4[__builtin_ffs(0xfbe70) == 5 ? 1 : -1];
+  char ffs5[__builtin_ffs(1U << (BITSIZE(int) - 1)) == BITSIZE(int) ? 1 : -1];
+  char ffs6[__builtin_ffsl(0x10L) == 5 ? 1 : -1];
+  char ffs7[__builtin_ffsll(0x100LL) == 9 ? 1 : -1];
+}
-- 
GitLab


From e8e9a335839350d444d1b90fa6727b3947708ab6 Mon Sep 17 00:00:00 2001
From: Alexander Yermolovich <43973793+ayermolo@users.noreply.github.com>
Date: Tue, 12 Dec 2023 07:01:20 -0800
Subject: [PATCH 314/349] [LLVM][DWARF] Add compilation directory and dwo name
 to TU in dwo section (#74909)

This adds support to help LLDB when binary is built with split dwarf,
has
.debug_names accelerator table and DWP file.
Final linked binary might have Type Units (TUs) with the same type
signature in multiple
compilation units. Although the signature is the same, TUs are not
guranted to
be bit identical. This is not a problem when they are in .o/.dwo files
as LLDB
can find them by looking at the right one based on
DW_AT_comp_dir/DW_AT_name in
skeleton CU. Once DWP is created, TUs are de-duplicated, and we need to
know
from which CU remaining one came from.

This approach allows LLDB to figure it out, with minimal changes to the
rest of
the tooling. As would have been the case if .debug_tu_index section in
DWP was
modified.
---
 llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp    | 10 +++++++
 llvm/test/CodeGen/X86/dwarf-headers.ll        |  6 ++---
 .../DebugInfo/WebAssembly/dwarf-headers.ll    |  6 ++---
 llvm/test/DebugInfo/X86/debug-names-types.ll  | 27 +++++++++++++++++--
 4 files changed, 41 insertions(+), 8 deletions(-)

diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
index ab29020bf1d7..41afbea45614 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
@@ -3478,6 +3478,16 @@ void DwarfDebug::addDwarfTypeUnitType(DwarfCompileUnit &CU,
   Ins.first->second = Signature;
 
   if (useSplitDwarf()) {
+    // Although multiple type units can have the same signature, they are not
+    // guranteed to be bit identical. When LLDB uses .debug_names it needs to
+    // know from which CU a type unit came from. These two attrbutes help it to
+    // figure that out.
+    if (getDwarfVersion() >= 5) {
+      if (!CompilationDir.empty())
+        NewTU.addString(UnitDie, dwarf::DW_AT_comp_dir, CompilationDir);
+      NewTU.addString(UnitDie, dwarf::DW_AT_dwo_name,
+                      Asm->TM.Options.MCOptions.SplitDwarfFile);
+    }
     MCSection *Section =
         getDwarfVersion() <= 4
             ? Asm->getObjFileLowering().getDwarfTypesDWOSection()
diff --git a/llvm/test/CodeGen/X86/dwarf-headers.ll b/llvm/test/CodeGen/X86/dwarf-headers.ll
index 4c029de5dbfa..3a3d9998659b 100644
--- a/llvm/test/CodeGen/X86/dwarf-headers.ll
+++ b/llvm/test/CodeGen/X86/dwarf-headers.ll
@@ -75,14 +75,14 @@
 ; O-5: .debug_info contents:
 ; O-5: 0x00000000: Compile Unit: {{.*}} version = 0x0005, unit_type = DW_UT_skeleton, abbr_offset
 ; O-5-SAME:        DWO_id = 0xccd7e58ef8bf4aa6
-; O-5: 0x00000014: DW_TAG_skeleton_unit 
+; O-5: 0x00000014: DW_TAG_skeleton_unit
 ;
 ; DWO-5: .debug_info.dwo contents:
 ; DWO-5: 0x00000000: Type Unit: {{.*}} version = 0x0005, unit_type = DW_UT_split_type, abbr_offset
 ; DWO-5: 0x00000018: DW_TAG_type_unit
-; DWO-5: 0x00000033: Compile Unit: {{.*}} version = 0x0005, unit_type = DW_UT_split_compile, abbr_offset
+; DWO-5: 0x00000035: Compile Unit: {{.*}} version = 0x0005, unit_type = DW_UT_split_compile, abbr_offset
 ; DWO-5-SAME:        DWO_id = 0xccd7e58ef8bf4aa6
-; DWO-5: 0x00000047: DW_TAG_compile_unit
+; DWO-5: 0x00000049: DW_TAG_compile_unit
 
 
 ; ModuleID = 't.cpp'
diff --git a/llvm/test/DebugInfo/WebAssembly/dwarf-headers.ll b/llvm/test/DebugInfo/WebAssembly/dwarf-headers.ll
index b2be5487b9cd..efa3d1c4a46e 100644
--- a/llvm/test/DebugInfo/WebAssembly/dwarf-headers.ll
+++ b/llvm/test/DebugInfo/WebAssembly/dwarf-headers.ll
@@ -77,14 +77,14 @@
 ; O-5: .debug_info contents:
 ; O-5: 0x00000000: Compile Unit: {{.*}} version = 0x0005, unit_type = DW_UT_skeleton, abbr_offset
 ; O-5-SAME:        DWO_id = 0xccd7e58ef8bf4aa6
-; O-5: 0x00000014: DW_TAG_skeleton_unit 
+; O-5: 0x00000014: DW_TAG_skeleton_unit
 ;
 ; DWO-5: .debug_info.dwo contents:
 ; DWO-5: 0x00000000: Type Unit: {{.*}} version = 0x0005, unit_type = DW_UT_split_type, abbr_offset
 ; DWO-5: 0x00000018: DW_TAG_type_unit
-; DWO-5: 0x00000033: Compile Unit: {{.*}} version = 0x0005, unit_type = DW_UT_split_compile, abbr_offset
+; DWO-5: 0x00000035: Compile Unit: {{.*}} version = 0x0005, unit_type = DW_UT_split_compile, abbr_offset
 ; DWO-5-SAME:        DWO_id = 0xccd7e58ef8bf4aa6
-; DWO-5: 0x00000047: DW_TAG_compile_unit
+; DWO-5: 0x00000049: DW_TAG_compile_unit
 
 
 ; ModuleID = 't.cpp'
diff --git a/llvm/test/DebugInfo/X86/debug-names-types.ll b/llvm/test/DebugInfo/X86/debug-names-types.ll
index d32691305d1c..501b7efd88eb 100644
--- a/llvm/test/DebugInfo/X86/debug-names-types.ll
+++ b/llvm/test/DebugInfo/X86/debug-names-types.ll
@@ -1,5 +1,6 @@
 ; UNSUPPORTED: system-windows
 ; This checks that .debug_names can be generated with monolithic, and split-dwarf, when -fdebug-type-sections is enabled.
+; It also checks that TU in .debug_info.dwo has correct DW_AT_comp_dir and DW_AT_dwo_name.
 ; Generated with: clang++ main.cpp   -g2 -gdwarf-5 -gpubnames -fdebug-types-section
 
 ; RUN: llc -mtriple=x86_64 -generate-type-units -dwarf-version=5 -filetype=obj %s -o %t
@@ -171,7 +172,7 @@
 ; CHECK-SPLIT-NEXT:         Abbrev: [[ABBREV1]]
 ; CHECK-SPLIT-NEXT:         Tag: DW_TAG_structure_type
 ; CHECK-SPLIT-NEXT:         DW_IDX_type_unit: 0x00
-; CHECK-SPLIT-NEXT:         DW_IDX_die_offset: 0x0000001f
+; CHECK-SPLIT-NEXT:         DW_IDX_die_offset: 0x00000021
 ; CHECK-SPLIT-NEXT:       }
 ; CHECK-SPLIT-NEXT:       Entry @ 0xae {
 ; CHECK-SPLIT-NEXT:         Abbrev: [[ABBREV]]
@@ -199,13 +200,35 @@
 ; CHECK-SPLIT-NEXT:         Abbrev: [[ABBREV4]]
 ; CHECK-SPLIT-NEXT:         Tag: DW_TAG_base_type
 ; CHECK-SPLIT-NEXT:         DW_IDX_type_unit: 0x00
-; CHECK-SPLIT-NEXT:         DW_IDX_die_offset: 0x00000034
+; CHECK-SPLIT-NEXT:         DW_IDX_die_offset: 0x00000036
 ; CHECK-SPLIT-NEXT:       }
 ; CHECK-SPLIT-NEXT:     }
 ; CHECK-SPLIT-NEXT:   ]
 ; CHECK-SPLIT-NEXT: }
 
 
+
+; RUN: llvm-dwarfdump -debug-info -r 0 %t > %tdebugInfo.txt
+; RUN: llvm-dwarfdump -debug-info -r 0 %t.mainTypes.dwo >> %tdebugInfo.txt
+; RUN: cat %tdebugInfo.txt | FileCheck %s --check-prefixes=CHECK-TYPE
+
+; CHECK-TYPE:         DW_TAG_skeleton_unit
+; CHECK-TYPE-NEXT:      DW_AT_stmt_list
+; CHECK-TYPE-NEXT:      DW_AT_str_offsets_base
+; CHECK-TYPE-NEXT:      DW_AT_comp_dir  ("/typeSmall")
+; CHECK-TYPE-NEXT:      DW_AT_dwo_name
+; CHECK-TYPE-SAME:        debug-names-types.ll.tmp.mainTypes.dwo
+; CHECK-TYPE-NEXT:      DW_AT_low_pc
+; CHECK-TYPE-NEXT:      DW_AT_high_pc
+; CHECK-TYPE-NEXT:      DW_AT_addr_base
+
+; CHECK-TYPE:           DW_TAG_type_unit
+; CHECK-TYPE-NOT:       DW_TAG
+; CHECK-TYPE:           DW_AT_comp_dir  ("/typeSmall")
+; CHECK-TYPE-NOT:       DW_TAG
+; CHECK-TYPE:           DW_AT_dwo_name
+; CHECK-TYPE-SAME:        debug-names-types.ll.tmp.mainTypes.dwo
+
 ; ModuleID = 'main.cpp'
 source_filename = "main.cpp"
 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
-- 
GitLab


From 220e095a2c26b26a8d7a74b90461b650e020d2f2 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad@amd.com>
Date: Tue, 12 Dec 2023 14:50:27 +0000
Subject: [PATCH 315/349] [AMDGPU] Remove unused function
 splitScalar64BitAddSub

---
 llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 74 --------------------------
 llvm/lib/Target/AMDGPU/SIInstrInfo.h   |  3 --
 2 files changed, 77 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 42eb4fa55ed5..d4e4526795f3 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -7559,80 +7559,6 @@ void SIInstrInfo::splitScalar64BitUnaryOp(SIInstrWorklist &Worklist,
   addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
 }
 
-void SIInstrInfo::splitScalar64BitAddSub(SIInstrWorklist &Worklist,
-                                         MachineInstr &Inst,
-                                         MachineDominatorTree *MDT) const {
-  bool IsAdd = (Inst.getOpcode() == AMDGPU::S_ADD_U64_PSEUDO);
-
-  MachineBasicBlock &MBB = *Inst.getParent();
-  MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
-  const auto *CarryRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
-
-  Register FullDestReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
-  Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
-  Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
-
-  Register CarryReg = MRI.createVirtualRegister(CarryRC);
-  Register DeadCarryReg = MRI.createVirtualRegister(CarryRC);
-
-  MachineOperand &Dest = Inst.getOperand(0);
-  MachineOperand &Src0 = Inst.getOperand(1);
-  MachineOperand &Src1 = Inst.getOperand(2);
-  const DebugLoc &DL = Inst.getDebugLoc();
-  MachineBasicBlock::iterator MII = Inst;
-
-  const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg());
-  const TargetRegisterClass *Src1RC = MRI.getRegClass(Src1.getReg());
-  const TargetRegisterClass *Src0SubRC =
-      RI.getSubRegisterClass(Src0RC, AMDGPU::sub0);
-  const TargetRegisterClass *Src1SubRC =
-      RI.getSubRegisterClass(Src1RC, AMDGPU::sub0);
-
-  MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
-                                                       AMDGPU::sub0, Src0SubRC);
-  MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
-                                                       AMDGPU::sub0, Src1SubRC);
-
-
-  MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
-                                                       AMDGPU::sub1, Src0SubRC);
-  MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
-                                                       AMDGPU::sub1, Src1SubRC);
-
-  unsigned LoOpc = IsAdd ? AMDGPU::V_ADD_CO_U32_e64 : AMDGPU::V_SUB_CO_U32_e64;
-  MachineInstr *LoHalf =
-    BuildMI(MBB, MII, DL, get(LoOpc), DestSub0)
-    .addReg(CarryReg, RegState::Define)
-    .add(SrcReg0Sub0)
-    .add(SrcReg1Sub0)
-    .addImm(0); // clamp bit
-
-  unsigned HiOpc = IsAdd ? AMDGPU::V_ADDC_U32_e64 : AMDGPU::V_SUBB_U32_e64;
-  MachineInstr *HiHalf =
-    BuildMI(MBB, MII, DL, get(HiOpc), DestSub1)
-    .addReg(DeadCarryReg, RegState::Define | RegState::Dead)
-    .add(SrcReg0Sub1)
-    .add(SrcReg1Sub1)
-    .addReg(CarryReg, RegState::Kill)
-    .addImm(0); // clamp bit
-
-  BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
-    .addReg(DestSub0)
-    .addImm(AMDGPU::sub0)
-    .addReg(DestSub1)
-    .addImm(AMDGPU::sub1);
-
-  MRI.replaceRegWith(Dest.getReg(), FullDestReg);
-
-  // Try to legalize the operands in case we need to swap the order to keep it
-  // valid.
-  legalizeOperands(*LoHalf, MDT);
-  legalizeOperands(*HiHalf, MDT);
-
-  // Move all users of this moved value.
-  addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
-}
-
 void SIInstrInfo::splitScalar64BitBinaryOp(SIInstrWorklist &Worklist,
                                            MachineInstr &Inst, unsigned Opcode,
                                            MachineDominatorTree *MDT) const {
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 0ce31ac6d54e..e794d8cf7cc2 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -134,9 +134,6 @@ private:
   void splitScalar64BitUnaryOp(SIInstrWorklist &Worklist, MachineInstr &Inst,
                                unsigned Opcode, bool Swap = false) const;
 
-  void splitScalar64BitAddSub(SIInstrWorklist &Worklist, MachineInstr &Inst,
-                              MachineDominatorTree *MDT = nullptr) const;
-
   void splitScalar64BitBinaryOp(SIInstrWorklist &Worklist, MachineInstr &Inst,
                                 unsigned Opcode,
                                 MachineDominatorTree *MDT = nullptr) const;
-- 
GitLab


From ef35da825f38a86e4621c13a2898d561da88991c Mon Sep 17 00:00:00 2001
From: Evgenii Kudriashov <evgenii.kudriashov@intel.com>
Date: Tue, 12 Dec 2023 16:08:08 +0100
Subject: [PATCH 316/349] [X86][GlobalISel] Add instruction selection for
 G_SELECT (#70753)

---
 .../X86/GISel/X86InstructionSelector.cpp      |  48 ++
 .../lib/Target/X86/GISel/X86LegalizerInfo.cpp |  10 +-
 .../X86/GlobalISel/legalize-select.mir        |  29 +-
 .../test/CodeGen/X86/fast-isel-select-cmov.ll |  76 --
 llvm/test/CodeGen/X86/isel-select-cmov.ll     | 761 ++++++++++++++++++
 5 files changed, 835 insertions(+), 89 deletions(-)
 delete mode 100644 llvm/test/CodeGen/X86/fast-isel-select-cmov.ll
 create mode 100644 llvm/test/CodeGen/X86/isel-select-cmov.ll

diff --git a/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp b/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
index 6157dafb5c51..d7a10f45cb5f 100644
--- a/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
+++ b/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
@@ -20,6 +20,7 @@
 #include "X86Subtarget.h"
 #include "X86TargetMachine.h"
 #include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
+#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
 #include "llvm/CodeGen/GlobalISel/Utils.h"
 #include "llvm/CodeGen/LowLevelType.h"
@@ -116,6 +117,8 @@ private:
   bool selectImplicitDefOrPHI(MachineInstr &I, MachineRegisterInfo &MRI) const;
   bool selectMulDivRem(MachineInstr &I, MachineRegisterInfo &MRI,
                        MachineFunction &MF) const;
+  bool selectSelect(MachineInstr &I, MachineRegisterInfo &MRI,
+                    MachineFunction &MF) const;
   bool selectIntrinsicWSideEffects(MachineInstr &I, MachineRegisterInfo &MRI,
                                    MachineFunction &MF) const;
 
@@ -429,6 +432,8 @@ bool X86InstructionSelector::select(MachineInstr &I) {
   case TargetOpcode::G_SREM:
   case TargetOpcode::G_UREM:
     return selectMulDivRem(I, MRI, MF);
+  case TargetOpcode::G_SELECT:
+    return selectSelect(I, MRI, MF);
   case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
     return selectIntrinsicWSideEffects(I, MRI, MF);
   }
@@ -1789,6 +1794,49 @@ bool X86InstructionSelector::selectMulDivRem(MachineInstr &I,
   return true;
 }
 
+bool X86InstructionSelector::selectSelect(MachineInstr &I,
+                                          MachineRegisterInfo &MRI,
+                                          MachineFunction &MF) const {
+  GSelect &Sel = cast<GSelect>(I);
+  unsigned DstReg = Sel.getReg(0);
+  BuildMI(*Sel.getParent(), Sel, Sel.getDebugLoc(), TII.get(X86::TEST32rr))
+      .addReg(Sel.getCondReg())
+      .addReg(Sel.getCondReg());
+
+  unsigned OpCmp;
+  LLT Ty = MRI.getType(DstReg);
+  switch (Ty.getSizeInBits()) {
+  default:
+    return false;
+  case 8:
+    OpCmp = X86::CMOV_GR8;
+    break;
+  case 16:
+    OpCmp = STI.canUseCMOV() ? X86::CMOV16rr : X86::CMOV_GR16;
+    break;
+  case 32:
+    OpCmp = STI.canUseCMOV() ? X86::CMOV32rr : X86::CMOV_GR32;
+    break;
+  case 64:
+    assert(STI.is64Bit() && STI.canUseCMOV());
+    OpCmp = X86::CMOV64rr;
+    break;
+  }
+  BuildMI(*Sel.getParent(), Sel, Sel.getDebugLoc(), TII.get(OpCmp), DstReg)
+      .addReg(Sel.getTrueReg())
+      .addReg(Sel.getFalseReg())
+      .addImm(X86::COND_E);
+
+  const TargetRegisterClass *DstRC = getRegClass(Ty, DstReg, MRI);
+  if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
+    LLVM_DEBUG(dbgs() << "Failed to constrain CMOV\n");
+    return false;
+  }
+
+  Sel.eraseFromParent();
+  return true;
+}
+
 bool X86InstructionSelector::selectIntrinsicWSideEffects(
     MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const {
 
diff --git a/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp b/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
index 03af2b9e537c..27381dff338e 100644
--- a/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
+++ b/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
@@ -29,6 +29,7 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
     : Subtarget(STI) {
 
   bool Is64Bit = Subtarget.is64Bit();
+  bool HasCMOV = Subtarget.canUseCMOV();
   bool HasSSE1 = Subtarget.hasSSE1();
   bool HasSSE2 = Subtarget.hasSSE2();
   bool HasSSE41 = Subtarget.hasSSE41();
@@ -521,11 +522,10 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
 
   // todo: vectors and address spaces
   getActionDefinitionsBuilder(G_SELECT)
-       .legalFor({{s8, s32}, {s16, s32}, {s32, s32}, {s64, s32},
-                  {p0, s32}})
-    .widenScalarToNextPow2(0, /*Min=*/8)
-    .clampScalar(0, s8, sMaxScalar)
-    .clampScalar(1, s32, s32);
+      .legalFor({{s8, s32}, {s16, s32}, {s32, s32}, {s64, s32}, {p0, s32}})
+      .widenScalarToNextPow2(0, /*Min=*/8)
+      .clampScalar(0, HasCMOV ? s16 : s8, sMaxScalar)
+      .clampScalar(1, s32, s32);
 
   // memory intrinsics
   getActionDefinitionsBuilder({G_MEMCPY, G_MEMMOVE, G_MEMSET}).libcall();
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-select.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-select.mir
index 1a29014246d3..a7cbb35e3f74 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-select.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-select.mir
@@ -41,6 +41,7 @@ body:             |
     ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
     ; X86-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
     ; X86-NEXT: RET 0, implicit [[COPY]](s64)
+    ;
     ; X64-LABEL: name: test_select64
     ; X64: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
     ; X64-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
@@ -101,14 +102,26 @@ body:             |
 name:            test_select8
 body:             |
   bb.1:
-    ; CHECK-LABEL: name: test_select8
-    ; CHECK: [[DEF:%[0-9]+]]:_(s8) = IMPLICIT_DEF
-    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s8) = IMPLICIT_DEF
-    ; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s1) = IMPLICIT_DEF
-    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[DEF2]](s1)
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s8) = G_SELECT [[ZEXT]](s32), [[DEF1]], [[DEF]]
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY [[SELECT]](s8)
-    ; CHECK-NEXT: RET 0, implicit [[COPY]](s8)
+    ; X86-LABEL: name: test_select8
+    ; X86: [[DEF:%[0-9]+]]:_(s8) = IMPLICIT_DEF
+    ; X86-NEXT: [[DEF1:%[0-9]+]]:_(s8) = IMPLICIT_DEF
+    ; X86-NEXT: [[DEF2:%[0-9]+]]:_(s1) = IMPLICIT_DEF
+    ; X86-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[DEF2]](s1)
+    ; X86-NEXT: [[SELECT:%[0-9]+]]:_(s8) = G_SELECT [[ZEXT]](s32), [[DEF1]], [[DEF]]
+    ; X86-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY [[SELECT]](s8)
+    ; X86-NEXT: RET 0, implicit [[COPY]](s8)
+    ;
+    ; X64-LABEL: name: test_select8
+    ; X64: [[DEF:%[0-9]+]]:_(s8) = IMPLICIT_DEF
+    ; X64-NEXT: [[DEF1:%[0-9]+]]:_(s8) = IMPLICIT_DEF
+    ; X64-NEXT: [[DEF2:%[0-9]+]]:_(s1) = IMPLICIT_DEF
+    ; X64-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[DEF1]](s8)
+    ; X64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[DEF]](s8)
+    ; X64-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[DEF2]](s1)
+    ; X64-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ZEXT]](s32), [[ANYEXT]], [[ANYEXT1]]
+    ; X64-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[SELECT]](s16)
+    ; X64-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY [[TRUNC]](s8)
+    ; X64-NEXT: RET 0, implicit [[COPY]](s8)
     %0:_(s8) = IMPLICIT_DEF
     %1:_(s8) = IMPLICIT_DEF
     %2:_(s1) = IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/X86/fast-isel-select-cmov.ll b/llvm/test/CodeGen/X86/fast-isel-select-cmov.ll
deleted file mode 100644
index a5efb6f06b86..000000000000
--- a/llvm/test/CodeGen/X86/fast-isel-select-cmov.ll
+++ /dev/null
@@ -1,76 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin10                  | FileCheck %s
-; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin10 -mattr=+avx512f  | FileCheck %s
-
-; Test conditional move for the supported types (i16, i32, and i32) and
-; conditon input (argument or cmp). Currently i8 is not supported.
-
-define zeroext i16 @select_cmov_i16(i1 zeroext %cond, i16 zeroext %a, i16 zeroext %b) {
-; CHECK-LABEL: select_cmov_i16:
-; CHECK:       ## %bb.0:
-; CHECK-NEXT:    testb $1, %dil
-; CHECK-NEXT:    cmovew %dx, %si
-; CHECK-NEXT:    movzwl %si, %eax
-; CHECK-NEXT:    retq
-  %1 = select i1 %cond, i16 %a, i16 %b
-  ret i16 %1
-}
-
-define zeroext i16 @select_cmp_cmov_i16(i16 zeroext %a, i16 zeroext %b) {
-; CHECK-LABEL: select_cmp_cmov_i16:
-; CHECK:       ## %bb.0:
-; CHECK-NEXT:    cmpw %si, %di
-; CHECK-NEXT:    cmovbw %di, %si
-; CHECK-NEXT:    movzwl %si, %eax
-; CHECK-NEXT:    retq
-  %1 = icmp ult i16 %a, %b
-  %2 = select i1 %1, i16 %a, i16 %b
-  ret i16 %2
-}
-
-define i32 @select_cmov_i32(i1 zeroext %cond, i32 %a, i32 %b) {
-; CHECK-LABEL: select_cmov_i32:
-; CHECK:       ## %bb.0:
-; CHECK-NEXT:    movl %esi, %eax
-; CHECK-NEXT:    testb $1, %dil
-; CHECK-NEXT:    cmovel %edx, %eax
-; CHECK-NEXT:    retq
-  %1 = select i1 %cond, i32 %a, i32 %b
-  ret i32 %1
-}
-
-define i32 @select_cmp_cmov_i32(i32 %a, i32 %b) {
-; CHECK-LABEL: select_cmp_cmov_i32:
-; CHECK:       ## %bb.0:
-; CHECK-NEXT:    movl %esi, %eax
-; CHECK-NEXT:    cmpl %esi, %edi
-; CHECK-NEXT:    cmovbl %edi, %eax
-; CHECK-NEXT:    retq
-  %1 = icmp ult i32 %a, %b
-  %2 = select i1 %1, i32 %a, i32 %b
-  ret i32 %2
-}
-
-define i64 @select_cmov_i64(i1 zeroext %cond, i64 %a, i64 %b) {
-; CHECK-LABEL: select_cmov_i64:
-; CHECK:       ## %bb.0:
-; CHECK-NEXT:    movq %rsi, %rax
-; CHECK-NEXT:    testb $1, %dil
-; CHECK-NEXT:    cmoveq %rdx, %rax
-; CHECK-NEXT:    retq
-  %1 = select i1 %cond, i64 %a, i64 %b
-  ret i64 %1
-}
-
-define i64 @select_cmp_cmov_i64(i64 %a, i64 %b) {
-; CHECK-LABEL: select_cmp_cmov_i64:
-; CHECK:       ## %bb.0:
-; CHECK-NEXT:    movq %rsi, %rax
-; CHECK-NEXT:    cmpq %rsi, %rdi
-; CHECK-NEXT:    cmovbq %rdi, %rax
-; CHECK-NEXT:    retq
-  %1 = icmp ult i64 %a, %b
-  %2 = select i1 %1, i64 %a, i64 %b
-  ret i64 %2
-}
-
diff --git a/llvm/test/CodeGen/X86/isel-select-cmov.ll b/llvm/test/CodeGen/X86/isel-select-cmov.ll
new file mode 100644
index 000000000000..0e5293c9000f
--- /dev/null
+++ b/llvm/test/CodeGen/X86/isel-select-cmov.ll
@@ -0,0 +1,761 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -verify-machineinstrs                                                   | FileCheck %s --check-prefix=SDAG-X64
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -verify-machineinstrs -mattr=+avx512f                                   | FileCheck %s --check-prefix=SDAG-X64
+; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin10 -verify-machineinstrs                     | FileCheck %s --check-prefix=FAST-X64
+; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin10 -verify-machineinstrs -mattr=+avx512f     | FileCheck %s --check-prefix=FAST-X64
+; RUN: llc < %s -global-isel -global-isel-abort=1 -mtriple=x86_64-apple-darwin10 -verify-machineinstrs                 | FileCheck %s --check-prefix=GISEL-X64
+; RUN: llc < %s -global-isel -global-isel-abort=1 -mtriple=x86_64-apple-darwin10 -verify-machineinstrs -mattr=+avx512f | FileCheck %s --check-prefix=GISEL-X64
+
+; RUN: llc < %s -mtriple=i686-apple-darwin10 -verify-machineinstrs                                                | FileCheck %s --check-prefix=SDAG-X86
+; RUN: llc < %s -mtriple=i686-apple-darwin10 -verify-machineinstrs -mattr=+cmov                                   | FileCheck %s --check-prefix=SDAG-X86-CMOV
+; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=i686-apple-darwin10 -verify-machineinstrs                  | FileCheck %s --check-prefix=FAST-X86
+; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=i686-apple-darwin10 -verify-machineinstrs -mattr=+cmov     | FileCheck %s --check-prefix=FAST-X86-CMOV
+; RUN: llc < %s -global-isel -global-isel-abort=1 -mtriple=i686-apple-darwin10 -verify-machineinstrs              | FileCheck %s --check-prefix=GISEL-X86
+; RUN: llc < %s -global-isel -global-isel-abort=1 -mtriple=i686-apple-darwin10 -verify-machineinstrs -mattr=+cmov | FileCheck %s --check-prefix=GISEL-X86-CMOV
+
+; Test conditional move for the supported types (i16, i32, and i32) and
+; conditon input (argument or cmp).
+; When cmov is not available (i8 type or X86), the branch is expected.
+
+define zeroext i8 @select_cmov_i8(i1 zeroext %cond, i8 zeroext %a, i8 zeroext %b) {
+; SDAG-X64-LABEL: select_cmov_i8:
+; SDAG-X64:       ## %bb.0:
+; SDAG-X64-NEXT:    movl %esi, %eax
+; SDAG-X64-NEXT:    testl %edi, %edi
+; SDAG-X64-NEXT:    cmovel %edx, %eax
+; SDAG-X64-NEXT:    retq
+;
+; FAST-X64-LABEL: select_cmov_i8:
+; FAST-X64:       ## %bb.0:
+; FAST-X64-NEXT:    testb $1, %dil
+; FAST-X64-NEXT:    jne LBB0_2
+; FAST-X64-NEXT:  ## %bb.1:
+; FAST-X64-NEXT:    movl %edx, %esi
+; FAST-X64-NEXT:  LBB0_2:
+; FAST-X64-NEXT:    movzbl %sil, %eax
+; FAST-X64-NEXT:    retq
+;
+; GISEL-X64-LABEL: select_cmov_i8:
+; GISEL-X64:       ## %bb.0:
+; GISEL-X64-NEXT:    movl %edx, %eax
+; GISEL-X64-NEXT:    testl %edi, %edi
+; GISEL-X64-NEXT:    cmovnew %si, %ax
+; GISEL-X64-NEXT:    ## kill: def $al killed $al killed $eax
+; GISEL-X64-NEXT:    retq
+;
+; SDAG-X86-LABEL: select_cmov_i8:
+; SDAG-X86:       ## %bb.0:
+; SDAG-X86-NEXT:    cmpb $0, {{[0-9]+}}(%esp)
+; SDAG-X86-NEXT:    jne LBB0_1
+; SDAG-X86-NEXT:  ## %bb.2:
+; SDAG-X86-NEXT:    leal {{[0-9]+}}(%esp), %eax
+; SDAG-X86-NEXT:    movzbl (%eax), %eax
+; SDAG-X86-NEXT:    retl
+; SDAG-X86-NEXT:  LBB0_1:
+; SDAG-X86-NEXT:    leal {{[0-9]+}}(%esp), %eax
+; SDAG-X86-NEXT:    movzbl (%eax), %eax
+; SDAG-X86-NEXT:    retl
+;
+; SDAG-X86-CMOV-LABEL: select_cmov_i8:
+; SDAG-X86-CMOV:       ## %bb.0:
+; SDAG-X86-CMOV-NEXT:    cmpb $0, {{[0-9]+}}(%esp)
+; SDAG-X86-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
+; SDAG-X86-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
+; SDAG-X86-CMOV-NEXT:    cmovnel %eax, %ecx
+; SDAG-X86-CMOV-NEXT:    movzbl (%ecx), %eax
+; SDAG-X86-CMOV-NEXT:    retl
+;
+; FAST-X86-LABEL: select_cmov_i8:
+; FAST-X86:       ## %bb.0:
+; FAST-X86-NEXT:    testb $1, {{[0-9]+}}(%esp)
+; FAST-X86-NEXT:    jne LBB0_1
+; FAST-X86-NEXT:  ## %bb.2:
+; FAST-X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; FAST-X86-NEXT:    movzbl %al, %eax
+; FAST-X86-NEXT:    retl
+; FAST-X86-NEXT:  LBB0_1:
+; FAST-X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; FAST-X86-NEXT:    movzbl %al, %eax
+; FAST-X86-NEXT:    retl
+;
+; FAST-X86-CMOV-LABEL: select_cmov_i8:
+; FAST-X86-CMOV:       ## %bb.0:
+; FAST-X86-CMOV-NEXT:    testb $1, {{[0-9]+}}(%esp)
+; FAST-X86-CMOV-NEXT:    jne LBB0_1
+; FAST-X86-CMOV-NEXT:  ## %bb.2:
+; FAST-X86-CMOV-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; FAST-X86-CMOV-NEXT:    movzbl %al, %eax
+; FAST-X86-CMOV-NEXT:    retl
+; FAST-X86-CMOV-NEXT:  LBB0_1:
+; FAST-X86-CMOV-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; FAST-X86-CMOV-NEXT:    movzbl %al, %eax
+; FAST-X86-CMOV-NEXT:    retl
+;
+; GISEL-X86-LABEL: select_cmov_i8:
+; GISEL-X86:       ## %bb.0:
+; GISEL-X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; GISEL-X86-NEXT:    testl %eax, %eax
+; GISEL-X86-NEXT:    je LBB0_1
+; GISEL-X86-NEXT:  ## %bb.2:
+; GISEL-X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; GISEL-X86-NEXT:    ## kill: def $al killed $al killed $eax
+; GISEL-X86-NEXT:    retl
+; GISEL-X86-NEXT:  LBB0_1:
+; GISEL-X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; GISEL-X86-NEXT:    ## kill: def $al killed $al killed $eax
+; GISEL-X86-NEXT:    retl
+;
+; GISEL-X86-CMOV-LABEL: select_cmov_i8:
+; GISEL-X86-CMOV:       ## %bb.0:
+; GISEL-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; GISEL-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; GISEL-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; GISEL-X86-CMOV-NEXT:    testl %ecx, %ecx
+; GISEL-X86-CMOV-NEXT:    cmovnew %dx, %ax
+; GISEL-X86-CMOV-NEXT:    ## kill: def $al killed $al killed $eax
+; GISEL-X86-CMOV-NEXT:    retl
+  %1 = select i1 %cond, i8 %a, i8 %b
+  ret i8 %1
+}
+
+define zeroext i16 @select_cmov_i16(i1 zeroext %cond, i16 zeroext %a, i16 zeroext %b) {
+; SDAG-X64-LABEL: select_cmov_i16:
+; SDAG-X64:       ## %bb.0:
+; SDAG-X64-NEXT:    movl %esi, %eax
+; SDAG-X64-NEXT:    testl %edi, %edi
+; SDAG-X64-NEXT:    cmovel %edx, %eax
+; SDAG-X64-NEXT:    retq
+;
+; FAST-X64-LABEL: select_cmov_i16:
+; FAST-X64:       ## %bb.0:
+; FAST-X64-NEXT:    testb $1, %dil
+; FAST-X64-NEXT:    cmovew %dx, %si
+; FAST-X64-NEXT:    movzwl %si, %eax
+; FAST-X64-NEXT:    retq
+;
+; GISEL-X64-LABEL: select_cmov_i16:
+; GISEL-X64:       ## %bb.0:
+; GISEL-X64-NEXT:    movl %edx, %eax
+; GISEL-X64-NEXT:    testl %edi, %edi
+; GISEL-X64-NEXT:    cmovnew %si, %ax
+; GISEL-X64-NEXT:    ## kill: def $ax killed $ax killed $eax
+; GISEL-X64-NEXT:    retq
+;
+; SDAG-X86-LABEL: select_cmov_i16:
+; SDAG-X86:       ## %bb.0:
+; SDAG-X86-NEXT:    cmpb $0, {{[0-9]+}}(%esp)
+; SDAG-X86-NEXT:    jne LBB1_1
+; SDAG-X86-NEXT:  ## %bb.2:
+; SDAG-X86-NEXT:    leal {{[0-9]+}}(%esp), %eax
+; SDAG-X86-NEXT:    movzwl (%eax), %eax
+; SDAG-X86-NEXT:    retl
+; SDAG-X86-NEXT:  LBB1_1:
+; SDAG-X86-NEXT:    leal {{[0-9]+}}(%esp), %eax
+; SDAG-X86-NEXT:    movzwl (%eax), %eax
+; SDAG-X86-NEXT:    retl
+;
+; SDAG-X86-CMOV-LABEL: select_cmov_i16:
+; SDAG-X86-CMOV:       ## %bb.0:
+; SDAG-X86-CMOV-NEXT:    cmpb $0, {{[0-9]+}}(%esp)
+; SDAG-X86-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
+; SDAG-X86-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
+; SDAG-X86-CMOV-NEXT:    cmovnel %eax, %ecx
+; SDAG-X86-CMOV-NEXT:    movzwl (%ecx), %eax
+; SDAG-X86-CMOV-NEXT:    retl
+;
+; FAST-X86-LABEL: select_cmov_i16:
+; FAST-X86:       ## %bb.0:
+; FAST-X86-NEXT:    testb $1, {{[0-9]+}}(%esp)
+; FAST-X86-NEXT:    jne LBB1_1
+; FAST-X86-NEXT:  ## %bb.2:
+; FAST-X86-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; FAST-X86-NEXT:    movzwl %ax, %eax
+; FAST-X86-NEXT:    retl
+; FAST-X86-NEXT:  LBB1_1:
+; FAST-X86-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; FAST-X86-NEXT:    movzwl %ax, %eax
+; FAST-X86-NEXT:    retl
+;
+; FAST-X86-CMOV-LABEL: select_cmov_i16:
+; FAST-X86-CMOV:       ## %bb.0:
+; FAST-X86-CMOV-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; FAST-X86-CMOV-NEXT:    testb $1, {{[0-9]+}}(%esp)
+; FAST-X86-CMOV-NEXT:    cmovew {{[0-9]+}}(%esp), %ax
+; FAST-X86-CMOV-NEXT:    movzwl %ax, %eax
+; FAST-X86-CMOV-NEXT:    retl
+;
+; GISEL-X86-LABEL: select_cmov_i16:
+; GISEL-X86:       ## %bb.0:
+; GISEL-X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; GISEL-X86-NEXT:    testl %eax, %eax
+; GISEL-X86-NEXT:    je LBB1_1
+; GISEL-X86-NEXT:  ## %bb.2:
+; GISEL-X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; GISEL-X86-NEXT:    ## kill: def $ax killed $ax killed $eax
+; GISEL-X86-NEXT:    retl
+; GISEL-X86-NEXT:  LBB1_1:
+; GISEL-X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; GISEL-X86-NEXT:    ## kill: def $ax killed $ax killed $eax
+; GISEL-X86-NEXT:    retl
+;
+; GISEL-X86-CMOV-LABEL: select_cmov_i16:
+; GISEL-X86-CMOV:       ## %bb.0:
+; GISEL-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; GISEL-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; GISEL-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; GISEL-X86-CMOV-NEXT:    testl %ecx, %ecx
+; GISEL-X86-CMOV-NEXT:    cmovnew %dx, %ax
+; GISEL-X86-CMOV-NEXT:    ## kill: def $ax killed $ax killed $eax
+; GISEL-X86-CMOV-NEXT:    retl
+  %1 = select i1 %cond, i16 %a, i16 %b
+  ret i16 %1
+}
+
+define zeroext i16 @select_cmp_cmov_i16(i16 zeroext %a, i16 zeroext %b) {
+; SDAG-X64-LABEL: select_cmp_cmov_i16:
+; SDAG-X64:       ## %bb.0:
+; SDAG-X64-NEXT:    movl %esi, %eax
+; SDAG-X64-NEXT:    cmpw %ax, %di
+; SDAG-X64-NEXT:    cmovbl %edi, %eax
+; SDAG-X64-NEXT:    retq
+;
+; FAST-X64-LABEL: select_cmp_cmov_i16:
+; FAST-X64:       ## %bb.0:
+; FAST-X64-NEXT:    cmpw %si, %di
+; FAST-X64-NEXT:    cmovbw %di, %si
+; FAST-X64-NEXT:    movzwl %si, %eax
+; FAST-X64-NEXT:    retq
+;
+; GISEL-X64-LABEL: select_cmp_cmov_i16:
+; GISEL-X64:       ## %bb.0:
+; GISEL-X64-NEXT:    movl %edi, %eax
+; GISEL-X64-NEXT:    xorl %ecx, %ecx
+; GISEL-X64-NEXT:    cmpw %si, %ax
+; GISEL-X64-NEXT:    setb %cl
+; GISEL-X64-NEXT:    andl $1, %ecx
+; GISEL-X64-NEXT:    cmovew %si, %ax
+; GISEL-X64-NEXT:    ## kill: def $ax killed $ax killed $eax
+; GISEL-X64-NEXT:    retq
+;
+; SDAG-X86-LABEL: select_cmp_cmov_i16:
+; SDAG-X86:       ## %bb.0:
+; SDAG-X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; SDAG-X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; SDAG-X86-NEXT:    cmpw %cx, %ax
+; SDAG-X86-NEXT:    jb LBB2_2
+; SDAG-X86-NEXT:  ## %bb.1:
+; SDAG-X86-NEXT:    movl %ecx, %eax
+; SDAG-X86-NEXT:  LBB2_2:
+; SDAG-X86-NEXT:    movzwl %ax, %eax
+; SDAG-X86-NEXT:    retl
+;
+; SDAG-X86-CMOV-LABEL: select_cmp_cmov_i16:
+; SDAG-X86-CMOV:       ## %bb.0:
+; SDAG-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; SDAG-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; SDAG-X86-CMOV-NEXT:    cmpw %ax, %cx
+; SDAG-X86-CMOV-NEXT:    cmovbl %ecx, %eax
+; SDAG-X86-CMOV-NEXT:    movzwl %ax, %eax
+; SDAG-X86-CMOV-NEXT:    retl
+;
+; FAST-X86-LABEL: select_cmp_cmov_i16:
+; FAST-X86:       ## %bb.0:
+; FAST-X86-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
+; FAST-X86-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; FAST-X86-NEXT:    cmpw %cx, %ax
+; FAST-X86-NEXT:    jb LBB2_2
+; FAST-X86-NEXT:  ## %bb.1:
+; FAST-X86-NEXT:    movl %ecx, %eax
+; FAST-X86-NEXT:  LBB2_2:
+; FAST-X86-NEXT:    movzwl %ax, %eax
+; FAST-X86-NEXT:    retl
+;
+; FAST-X86-CMOV-LABEL: select_cmp_cmov_i16:
+; FAST-X86-CMOV:       ## %bb.0:
+; FAST-X86-CMOV-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; FAST-X86-CMOV-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
+; FAST-X86-CMOV-NEXT:    cmpw %ax, %cx
+; FAST-X86-CMOV-NEXT:    cmovbw %cx, %ax
+; FAST-X86-CMOV-NEXT:    movzwl %ax, %eax
+; FAST-X86-CMOV-NEXT:    retl
+;
+; GISEL-X86-LABEL: select_cmp_cmov_i16:
+; GISEL-X86:       ## %bb.0:
+; GISEL-X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; GISEL-X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; GISEL-X86-NEXT:    xorl %edx, %edx
+; GISEL-X86-NEXT:    cmpw %ax, %cx
+; GISEL-X86-NEXT:    setb %dl
+; GISEL-X86-NEXT:    andl $1, %edx
+; GISEL-X86-NEXT:    je LBB2_2
+; GISEL-X86-NEXT:  ## %bb.1:
+; GISEL-X86-NEXT:    movl %ecx, %eax
+; GISEL-X86-NEXT:  LBB2_2:
+; GISEL-X86-NEXT:    ## kill: def $ax killed $ax killed $eax
+; GISEL-X86-NEXT:    retl
+;
+; GISEL-X86-CMOV-LABEL: select_cmp_cmov_i16:
+; GISEL-X86-CMOV:       ## %bb.0:
+; GISEL-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; GISEL-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; GISEL-X86-CMOV-NEXT:    xorl %edx, %edx
+; GISEL-X86-CMOV-NEXT:    cmpw %cx, %ax
+; GISEL-X86-CMOV-NEXT:    setb %dl
+; GISEL-X86-CMOV-NEXT:    andl $1, %edx
+; GISEL-X86-CMOV-NEXT:    cmovew %cx, %ax
+; GISEL-X86-CMOV-NEXT:    ## kill: def $ax killed $ax killed $eax
+; GISEL-X86-CMOV-NEXT:    retl
+  %1 = icmp ult i16 %a, %b
+  %2 = select i1 %1, i16 %a, i16 %b
+  ret i16 %2
+}
+
+define i32 @select_cmov_i32(i1 zeroext %cond, i32 %a, i32 %b) {
+; SDAG-X64-LABEL: select_cmov_i32:
+; SDAG-X64:       ## %bb.0:
+; SDAG-X64-NEXT:    movl %esi, %eax
+; SDAG-X64-NEXT:    testl %edi, %edi
+; SDAG-X64-NEXT:    cmovel %edx, %eax
+; SDAG-X64-NEXT:    retq
+;
+; FAST-X64-LABEL: select_cmov_i32:
+; FAST-X64:       ## %bb.0:
+; FAST-X64-NEXT:    movl %esi, %eax
+; FAST-X64-NEXT:    testb $1, %dil
+; FAST-X64-NEXT:    cmovel %edx, %eax
+; FAST-X64-NEXT:    retq
+;
+; GISEL-X64-LABEL: select_cmov_i32:
+; GISEL-X64:       ## %bb.0:
+; GISEL-X64-NEXT:    movl %edx, %eax
+; GISEL-X64-NEXT:    testl %edi, %edi
+; GISEL-X64-NEXT:    cmovnel %esi, %eax
+; GISEL-X64-NEXT:    retq
+;
+; SDAG-X86-LABEL: select_cmov_i32:
+; SDAG-X86:       ## %bb.0:
+; SDAG-X86-NEXT:    cmpb $0, {{[0-9]+}}(%esp)
+; SDAG-X86-NEXT:    jne LBB3_1
+; SDAG-X86-NEXT:  ## %bb.2:
+; SDAG-X86-NEXT:    leal {{[0-9]+}}(%esp), %eax
+; SDAG-X86-NEXT:    movl (%eax), %eax
+; SDAG-X86-NEXT:    retl
+; SDAG-X86-NEXT:  LBB3_1:
+; SDAG-X86-NEXT:    leal {{[0-9]+}}(%esp), %eax
+; SDAG-X86-NEXT:    movl (%eax), %eax
+; SDAG-X86-NEXT:    retl
+;
+; SDAG-X86-CMOV-LABEL: select_cmov_i32:
+; SDAG-X86-CMOV:       ## %bb.0:
+; SDAG-X86-CMOV-NEXT:    cmpb $0, {{[0-9]+}}(%esp)
+; SDAG-X86-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
+; SDAG-X86-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
+; SDAG-X86-CMOV-NEXT:    cmovnel %eax, %ecx
+; SDAG-X86-CMOV-NEXT:    movl (%ecx), %eax
+; SDAG-X86-CMOV-NEXT:    retl
+;
+; FAST-X86-LABEL: select_cmov_i32:
+; FAST-X86:       ## %bb.0:
+; FAST-X86-NEXT:    testb $1, {{[0-9]+}}(%esp)
+; FAST-X86-NEXT:    jne LBB3_1
+; FAST-X86-NEXT:  ## %bb.2:
+; FAST-X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; FAST-X86-NEXT:    retl
+; FAST-X86-NEXT:  LBB3_1:
+; FAST-X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; FAST-X86-NEXT:    retl
+;
+; FAST-X86-CMOV-LABEL: select_cmov_i32:
+; FAST-X86-CMOV:       ## %bb.0:
+; FAST-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; FAST-X86-CMOV-NEXT:    testb $1, {{[0-9]+}}(%esp)
+; FAST-X86-CMOV-NEXT:    cmovel {{[0-9]+}}(%esp), %eax
+; FAST-X86-CMOV-NEXT:    retl
+;
+; GISEL-X86-LABEL: select_cmov_i32:
+; GISEL-X86:       ## %bb.0:
+; GISEL-X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; GISEL-X86-NEXT:    testl %eax, %eax
+; GISEL-X86-NEXT:    je LBB3_1
+; GISEL-X86-NEXT:  ## %bb.2:
+; GISEL-X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; GISEL-X86-NEXT:    retl
+; GISEL-X86-NEXT:  LBB3_1:
+; GISEL-X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; GISEL-X86-NEXT:    retl
+;
+; GISEL-X86-CMOV-LABEL: select_cmov_i32:
+; GISEL-X86-CMOV:       ## %bb.0:
+; GISEL-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; GISEL-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; GISEL-X86-CMOV-NEXT:    testl %ecx, %ecx
+; GISEL-X86-CMOV-NEXT:    cmovnel {{[0-9]+}}(%esp), %eax
+; GISEL-X86-CMOV-NEXT:    retl
+  %1 = select i1 %cond, i32 %a, i32 %b
+  ret i32 %1
+}
+
+define i32 @select_cmp_cmov_i32(i32 %a, i32 %b) {
+; SDAG-X64-LABEL: select_cmp_cmov_i32:
+; SDAG-X64:       ## %bb.0:
+; SDAG-X64-NEXT:    movl %esi, %eax
+; SDAG-X64-NEXT:    cmpl %esi, %edi
+; SDAG-X64-NEXT:    cmovbl %edi, %eax
+; SDAG-X64-NEXT:    retq
+;
+; FAST-X64-LABEL: select_cmp_cmov_i32:
+; FAST-X64:       ## %bb.0:
+; FAST-X64-NEXT:    movl %esi, %eax
+; FAST-X64-NEXT:    cmpl %esi, %edi
+; FAST-X64-NEXT:    cmovbl %edi, %eax
+; FAST-X64-NEXT:    retq
+;
+; GISEL-X64-LABEL: select_cmp_cmov_i32:
+; GISEL-X64:       ## %bb.0:
+; GISEL-X64-NEXT:    movl %edi, %eax
+; GISEL-X64-NEXT:    xorl %ecx, %ecx
+; GISEL-X64-NEXT:    cmpl %esi, %edi
+; GISEL-X64-NEXT:    setb %cl
+; GISEL-X64-NEXT:    andl $1, %ecx
+; GISEL-X64-NEXT:    cmovel %esi, %eax
+; GISEL-X64-NEXT:    retq
+;
+; SDAG-X86-LABEL: select_cmp_cmov_i32:
+; SDAG-X86:       ## %bb.0:
+; SDAG-X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; SDAG-X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; SDAG-X86-NEXT:    cmpl %ecx, %eax
+; SDAG-X86-NEXT:    jb LBB4_2
+; SDAG-X86-NEXT:  ## %bb.1:
+; SDAG-X86-NEXT:    movl %ecx, %eax
+; SDAG-X86-NEXT:  LBB4_2:
+; SDAG-X86-NEXT:    retl
+;
+; SDAG-X86-CMOV-LABEL: select_cmp_cmov_i32:
+; SDAG-X86-CMOV:       ## %bb.0:
+; SDAG-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; SDAG-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; SDAG-X86-CMOV-NEXT:    cmpl %eax, %ecx
+; SDAG-X86-CMOV-NEXT:    cmovbl %ecx, %eax
+; SDAG-X86-CMOV-NEXT:    retl
+;
+; FAST-X86-LABEL: select_cmp_cmov_i32:
+; FAST-X86:       ## %bb.0:
+; FAST-X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; FAST-X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; FAST-X86-NEXT:    cmpl %ecx, %eax
+; FAST-X86-NEXT:    jb LBB4_2
+; FAST-X86-NEXT:  ## %bb.1:
+; FAST-X86-NEXT:    movl %ecx, %eax
+; FAST-X86-NEXT:  LBB4_2:
+; FAST-X86-NEXT:    retl
+;
+; FAST-X86-CMOV-LABEL: select_cmp_cmov_i32:
+; FAST-X86-CMOV:       ## %bb.0:
+; FAST-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; FAST-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; FAST-X86-CMOV-NEXT:    cmpl %eax, %ecx
+; FAST-X86-CMOV-NEXT:    cmovbl %ecx, %eax
+; FAST-X86-CMOV-NEXT:    retl
+;
+; GISEL-X86-LABEL: select_cmp_cmov_i32:
+; GISEL-X86:       ## %bb.0:
+; GISEL-X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; GISEL-X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; GISEL-X86-NEXT:    xorl %edx, %edx
+; GISEL-X86-NEXT:    cmpl %eax, %ecx
+; GISEL-X86-NEXT:    setb %dl
+; GISEL-X86-NEXT:    andl $1, %edx
+; GISEL-X86-NEXT:    je LBB4_2
+; GISEL-X86-NEXT:  ## %bb.1:
+; GISEL-X86-NEXT:    movl %ecx, %eax
+; GISEL-X86-NEXT:  LBB4_2:
+; GISEL-X86-NEXT:    retl
+;
+; GISEL-X86-CMOV-LABEL: select_cmp_cmov_i32:
+; GISEL-X86-CMOV:       ## %bb.0:
+; GISEL-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; GISEL-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; GISEL-X86-CMOV-NEXT:    xorl %edx, %edx
+; GISEL-X86-CMOV-NEXT:    cmpl %ecx, %eax
+; GISEL-X86-CMOV-NEXT:    setb %dl
+; GISEL-X86-CMOV-NEXT:    andl $1, %edx
+; GISEL-X86-CMOV-NEXT:    cmovel %ecx, %eax
+; GISEL-X86-CMOV-NEXT:    retl
+  %1 = icmp ult i32 %a, %b
+  %2 = select i1 %1, i32 %a, i32 %b
+  ret i32 %2
+}
+
+define i64 @select_cmov_i64(i1 zeroext %cond, i64 %a, i64 %b) {
+; SDAG-X64-LABEL: select_cmov_i64:
+; SDAG-X64:       ## %bb.0:
+; SDAG-X64-NEXT:    movq %rsi, %rax
+; SDAG-X64-NEXT:    testl %edi, %edi
+; SDAG-X64-NEXT:    cmoveq %rdx, %rax
+; SDAG-X64-NEXT:    retq
+;
+; FAST-X64-LABEL: select_cmov_i64:
+; FAST-X64:       ## %bb.0:
+; FAST-X64-NEXT:    movq %rsi, %rax
+; FAST-X64-NEXT:    testb $1, %dil
+; FAST-X64-NEXT:    cmoveq %rdx, %rax
+; FAST-X64-NEXT:    retq
+;
+; GISEL-X64-LABEL: select_cmov_i64:
+; GISEL-X64:       ## %bb.0:
+; GISEL-X64-NEXT:    movq %rdx, %rax
+; GISEL-X64-NEXT:    testl %edi, %edi
+; GISEL-X64-NEXT:    cmovneq %rsi, %rax
+; GISEL-X64-NEXT:    retq
+;
+; SDAG-X86-LABEL: select_cmov_i64:
+; SDAG-X86:       ## %bb.0:
+; SDAG-X86-NEXT:    cmpb $0, {{[0-9]+}}(%esp)
+; SDAG-X86-NEXT:    jne LBB5_1
+; SDAG-X86-NEXT:  ## %bb.2:
+; SDAG-X86-NEXT:    leal {{[0-9]+}}(%esp), %ecx
+; SDAG-X86-NEXT:    jmp LBB5_3
+; SDAG-X86-NEXT:  LBB5_1:
+; SDAG-X86-NEXT:    leal {{[0-9]+}}(%esp), %ecx
+; SDAG-X86-NEXT:  LBB5_3:
+; SDAG-X86-NEXT:    movl (%ecx), %eax
+; SDAG-X86-NEXT:    movl 4(%ecx), %edx
+; SDAG-X86-NEXT:    retl
+;
+; SDAG-X86-CMOV-LABEL: select_cmov_i64:
+; SDAG-X86-CMOV:       ## %bb.0:
+; SDAG-X86-CMOV-NEXT:    cmpb $0, {{[0-9]+}}(%esp)
+; SDAG-X86-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %eax
+; SDAG-X86-CMOV-NEXT:    leal {{[0-9]+}}(%esp), %ecx
+; SDAG-X86-CMOV-NEXT:    cmovnel %eax, %ecx
+; SDAG-X86-CMOV-NEXT:    movl (%ecx), %eax
+; SDAG-X86-CMOV-NEXT:    movl 4(%ecx), %edx
+; SDAG-X86-CMOV-NEXT:    retl
+;
+; FAST-X86-LABEL: select_cmov_i64:
+; FAST-X86:       ## %bb.0:
+; FAST-X86-NEXT:    cmpb $0, {{[0-9]+}}(%esp)
+; FAST-X86-NEXT:    jne LBB5_1
+; FAST-X86-NEXT:  ## %bb.2:
+; FAST-X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; FAST-X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; FAST-X86-NEXT:    retl
+; FAST-X86-NEXT:  LBB5_1:
+; FAST-X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; FAST-X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; FAST-X86-NEXT:    retl
+;
+; FAST-X86-CMOV-LABEL: select_cmov_i64:
+; FAST-X86-CMOV:       ## %bb.0:
+; FAST-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; FAST-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; FAST-X86-CMOV-NEXT:    cmpb $0, {{[0-9]+}}(%esp)
+; FAST-X86-CMOV-NEXT:    cmovel {{[0-9]+}}(%esp), %eax
+; FAST-X86-CMOV-NEXT:    cmovel {{[0-9]+}}(%esp), %edx
+; FAST-X86-CMOV-NEXT:    retl
+;
+; GISEL-X86-LABEL: select_cmov_i64:
+; GISEL-X86:       ## %bb.0:
+; GISEL-X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; GISEL-X86-NEXT:    testl %ecx, %ecx
+; GISEL-X86-NEXT:    je LBB5_1
+; GISEL-X86-NEXT:  ## %bb.2:
+; GISEL-X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; GISEL-X86-NEXT:    testl %ecx, %ecx
+; GISEL-X86-NEXT:    jne LBB5_5
+; GISEL-X86-NEXT:  LBB5_4:
+; GISEL-X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; GISEL-X86-NEXT:    retl
+; GISEL-X86-NEXT:  LBB5_1:
+; GISEL-X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; GISEL-X86-NEXT:    testl %ecx, %ecx
+; GISEL-X86-NEXT:    je LBB5_4
+; GISEL-X86-NEXT:  LBB5_5:
+; GISEL-X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; GISEL-X86-NEXT:    retl
+;
+; GISEL-X86-CMOV-LABEL: select_cmov_i64:
+; GISEL-X86-CMOV:       ## %bb.0:
+; GISEL-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; GISEL-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; GISEL-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; GISEL-X86-CMOV-NEXT:    testl %ecx, %ecx
+; GISEL-X86-CMOV-NEXT:    cmovnel {{[0-9]+}}(%esp), %eax
+; GISEL-X86-CMOV-NEXT:    cmovnel {{[0-9]+}}(%esp), %edx
+; GISEL-X86-CMOV-NEXT:    retl
+  %1 = select i1 %cond, i64 %a, i64 %b
+  ret i64 %1
+}
+
+define i64 @select_cmp_cmov_i64(i64 %a, i64 %b) nounwind {
+; SDAG-X64-LABEL: select_cmp_cmov_i64:
+; SDAG-X64:       ## %bb.0:
+; SDAG-X64-NEXT:    movq %rsi, %rax
+; SDAG-X64-NEXT:    cmpq %rsi, %rdi
+; SDAG-X64-NEXT:    cmovbq %rdi, %rax
+; SDAG-X64-NEXT:    retq
+;
+; FAST-X64-LABEL: select_cmp_cmov_i64:
+; FAST-X64:       ## %bb.0:
+; FAST-X64-NEXT:    movq %rsi, %rax
+; FAST-X64-NEXT:    cmpq %rsi, %rdi
+; FAST-X64-NEXT:    cmovbq %rdi, %rax
+; FAST-X64-NEXT:    retq
+;
+; GISEL-X64-LABEL: select_cmp_cmov_i64:
+; GISEL-X64:       ## %bb.0:
+; GISEL-X64-NEXT:    movq %rdi, %rax
+; GISEL-X64-NEXT:    xorl %ecx, %ecx
+; GISEL-X64-NEXT:    cmpq %rsi, %rdi
+; GISEL-X64-NEXT:    setb %cl
+; GISEL-X64-NEXT:    andl $1, %ecx
+; GISEL-X64-NEXT:    cmoveq %rsi, %rax
+; GISEL-X64-NEXT:    retq
+;
+; SDAG-X86-LABEL: select_cmp_cmov_i64:
+; SDAG-X86:       ## %bb.0:
+; SDAG-X86-NEXT:    pushl %edi
+; SDAG-X86-NEXT:    pushl %esi
+; SDAG-X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; SDAG-X86-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; SDAG-X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; SDAG-X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; SDAG-X86-NEXT:    cmpl %ecx, %eax
+; SDAG-X86-NEXT:    movl %edx, %edi
+; SDAG-X86-NEXT:    sbbl %esi, %edi
+; SDAG-X86-NEXT:    jb LBB6_2
+; SDAG-X86-NEXT:  ## %bb.1:
+; SDAG-X86-NEXT:    movl %ecx, %eax
+; SDAG-X86-NEXT:    movl %esi, %edx
+; SDAG-X86-NEXT:  LBB6_2:
+; SDAG-X86-NEXT:    popl %esi
+; SDAG-X86-NEXT:    popl %edi
+; SDAG-X86-NEXT:    retl
+;
+; SDAG-X86-CMOV-LABEL: select_cmp_cmov_i64:
+; SDAG-X86-CMOV:       ## %bb.0:
+; SDAG-X86-CMOV-NEXT:    pushl %edi
+; SDAG-X86-CMOV-NEXT:    pushl %esi
+; SDAG-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; SDAG-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; SDAG-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; SDAG-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; SDAG-X86-CMOV-NEXT:    cmpl %eax, %ecx
+; SDAG-X86-CMOV-NEXT:    movl %esi, %edi
+; SDAG-X86-CMOV-NEXT:    sbbl %edx, %edi
+; SDAG-X86-CMOV-NEXT:    cmovbl %ecx, %eax
+; SDAG-X86-CMOV-NEXT:    cmovbl %esi, %edx
+; SDAG-X86-CMOV-NEXT:    popl %esi
+; SDAG-X86-CMOV-NEXT:    popl %edi
+; SDAG-X86-CMOV-NEXT:    retl
+;
+; FAST-X86-LABEL: select_cmp_cmov_i64:
+; FAST-X86:       ## %bb.0:
+; FAST-X86-NEXT:    pushl %edi
+; FAST-X86-NEXT:    pushl %esi
+; FAST-X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; FAST-X86-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; FAST-X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; FAST-X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; FAST-X86-NEXT:    cmpl %esi, %eax
+; FAST-X86-NEXT:    movl %edx, %edi
+; FAST-X86-NEXT:    sbbl %ecx, %edi
+; FAST-X86-NEXT:    jb LBB6_2
+; FAST-X86-NEXT:  ## %bb.1:
+; FAST-X86-NEXT:    movl %esi, %eax
+; FAST-X86-NEXT:    movl %ecx, %edx
+; FAST-X86-NEXT:  LBB6_2:
+; FAST-X86-NEXT:    popl %esi
+; FAST-X86-NEXT:    popl %edi
+; FAST-X86-NEXT:    retl
+;
+; FAST-X86-CMOV-LABEL: select_cmp_cmov_i64:
+; FAST-X86-CMOV:       ## %bb.0:
+; FAST-X86-CMOV-NEXT:    pushl %edi
+; FAST-X86-CMOV-NEXT:    pushl %esi
+; FAST-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; FAST-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; FAST-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; FAST-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; FAST-X86-CMOV-NEXT:    cmpl %eax, %esi
+; FAST-X86-CMOV-NEXT:    movl %ecx, %edi
+; FAST-X86-CMOV-NEXT:    sbbl %edx, %edi
+; FAST-X86-CMOV-NEXT:    cmovbl %esi, %eax
+; FAST-X86-CMOV-NEXT:    cmovbl %ecx, %edx
+; FAST-X86-CMOV-NEXT:    popl %esi
+; FAST-X86-CMOV-NEXT:    popl %edi
+; FAST-X86-CMOV-NEXT:    retl
+;
+; GISEL-X86-LABEL: select_cmp_cmov_i64:
+; GISEL-X86:       ## %bb.0:
+; GISEL-X86-NEXT:    pushl %ebp
+; GISEL-X86-NEXT:    pushl %ebx
+; GISEL-X86-NEXT:    pushl %edi
+; GISEL-X86-NEXT:    pushl %esi
+; GISEL-X86-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; GISEL-X86-NEXT:    movl {{[0-9]+}}(%esp), %ebp
+; GISEL-X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; GISEL-X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; GISEL-X86-NEXT:    xorl %ecx, %ecx
+; GISEL-X86-NEXT:    cmpl %edx, %ebp
+; GISEL-X86-NEXT:    setb %bl
+; GISEL-X86-NEXT:    sete %cl
+; GISEL-X86-NEXT:    cmpl %eax, %esi
+; GISEL-X86-NEXT:    setb %bh
+; GISEL-X86-NEXT:    testl %ecx, %ecx
+; GISEL-X86-NEXT:    je LBB6_2
+; GISEL-X86-NEXT:  ## %bb.1:
+; GISEL-X86-NEXT:    movb %bh, %bl
+; GISEL-X86-NEXT:  LBB6_2:
+; GISEL-X86-NEXT:    movzbl %bl, %edi
+; GISEL-X86-NEXT:    andl $1, %edi
+; GISEL-X86-NEXT:    je LBB6_4
+; GISEL-X86-NEXT:  ## %bb.3:
+; GISEL-X86-NEXT:    movl %esi, %eax
+; GISEL-X86-NEXT:  LBB6_4:
+; GISEL-X86-NEXT:    testl %edi, %edi
+; GISEL-X86-NEXT:    je LBB6_6
+; GISEL-X86-NEXT:  ## %bb.5:
+; GISEL-X86-NEXT:    movl %ebp, %edx
+; GISEL-X86-NEXT:  LBB6_6:
+; GISEL-X86-NEXT:    popl %esi
+; GISEL-X86-NEXT:    popl %edi
+; GISEL-X86-NEXT:    popl %ebx
+; GISEL-X86-NEXT:    popl %ebp
+; GISEL-X86-NEXT:    retl
+;
+; GISEL-X86-CMOV-LABEL: select_cmp_cmov_i64:
+; GISEL-X86-CMOV:       ## %bb.0:
+; GISEL-X86-CMOV-NEXT:    pushl %ebp
+; GISEL-X86-CMOV-NEXT:    pushl %ebx
+; GISEL-X86-CMOV-NEXT:    pushl %edi
+; GISEL-X86-CMOV-NEXT:    pushl %esi
+; GISEL-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %ebp
+; GISEL-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; GISEL-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; GISEL-X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %edi
+; GISEL-X86-CMOV-NEXT:    xorl %ebx, %ebx
+; GISEL-X86-CMOV-NEXT:    xorl %ecx, %ecx
+; GISEL-X86-CMOV-NEXT:    cmpl %edi, %edx
+; GISEL-X86-CMOV-NEXT:    setb %bl
+; GISEL-X86-CMOV-NEXT:    sete %cl
+; GISEL-X86-CMOV-NEXT:    xorl %eax, %eax
+; GISEL-X86-CMOV-NEXT:    cmpl %esi, %ebp
+; GISEL-X86-CMOV-NEXT:    setb %al
+; GISEL-X86-CMOV-NEXT:    testl %ecx, %ecx
+; GISEL-X86-CMOV-NEXT:    cmovnew %ax, %bx
+; GISEL-X86-CMOV-NEXT:    andl $1, %ebx
+; GISEL-X86-CMOV-NEXT:    cmovel %esi, %ebp
+; GISEL-X86-CMOV-NEXT:    cmovel %edi, %edx
+; GISEL-X86-CMOV-NEXT:    movl %ebp, %eax
+; GISEL-X86-CMOV-NEXT:    popl %esi
+; GISEL-X86-CMOV-NEXT:    popl %edi
+; GISEL-X86-CMOV-NEXT:    popl %ebx
+; GISEL-X86-CMOV-NEXT:    popl %ebp
+; GISEL-X86-CMOV-NEXT:    retl
+  %1 = icmp ult i64 %a, %b
+  %2 = select i1 %1, i64 %a, i64 %b
+  ret i64 %2
+}
+
-- 
GitLab


From 105adf2cd9588b4839fbdc7287bb76a962fdb8ca Mon Sep 17 00:00:00 2001
From: Micah Weston <micahsweston@gmail.com>
Date: Tue, 12 Dec 2023 10:23:16 -0500
Subject: [PATCH 317/349] [SHT_LLVM_BB_ADDR_MAP] Implements PGOAnalysisMap in
 Object and ObjectYAML with tests.

Reviewed in PR (#71750). A part of [RFC - PGO Accuracy Metrics: Emitting and Evaluating Branch
and Block
Analysis](https://discourse.llvm.org/t/rfc-pgo-accuracy-metrics-emitting-and-evaluating-branch-and-block-analysis/73902).

This PR adds the PGOAnalysisMap data structure and implements encoding and
decoding through Object and ObjectYAML along with associated tests. When
emitted into the bb-addr-map section, each function is followed by the associated
pgo-analysis-map for that function. The emitting of each analysis in the map is
controlled by a bit in the bb-addr-map feature byte. All existing bb-addr-map
code can ignore the pgo-analysis-map if the caller does not request the data.
---
 llvm/include/llvm/Object/ELF.h              |   6 +-
 llvm/include/llvm/Object/ELFObjectFile.h    |   8 +-
 llvm/include/llvm/Object/ELFTypes.h         |  75 ++++
 llvm/include/llvm/ObjectYAML/ELFYAML.h      |  33 ++
 llvm/lib/Object/ELF.cpp                     | 148 ++++++--
 llvm/lib/Object/ELFObjectFile.cpp           |  23 +-
 llvm/lib/ObjectYAML/ELFEmitter.cpp          |  70 +++-
 llvm/lib/ObjectYAML/ELFYAML.cpp             |  23 ++
 llvm/unittests/Object/ELFObjectFileTest.cpp | 386 +++++++++++++++++++-
 llvm/unittests/Object/ELFTypesTest.cpp      |  37 ++
 10 files changed, 752 insertions(+), 57 deletions(-)

diff --git a/llvm/include/llvm/Object/ELF.h b/llvm/include/llvm/Object/ELF.h
index 3fca00592f73..78b6b40cbddf 100644
--- a/llvm/include/llvm/Object/ELF.h
+++ b/llvm/include/llvm/Object/ELF.h
@@ -457,8 +457,12 @@ public:
   /// within the text section that the SHT_LLVM_BB_ADDR_MAP section \p Sec
   /// is associated with. If the current ELFFile is relocatable, a corresponding
   /// \p RelaSec must be passed in as an argument.
+  /// Optional out variable to collect all PGO Analyses. New elements are only
+  /// added if no error occurs. If not provided, the PGO Analyses are decoded
+  /// then ignored.
   Expected<std::vector<BBAddrMap>>
-  decodeBBAddrMap(const Elf_Shdr &Sec, const Elf_Shdr *RelaSec = nullptr) const;
+  decodeBBAddrMap(const Elf_Shdr &Sec, const Elf_Shdr *RelaSec = nullptr,
+                  std::vector<PGOAnalysisMap> *PGOAnalyses = nullptr) const;
 
   /// Returns a map from every section matching \p IsMatch to its relocation
   /// section, or \p nullptr if it has no relocation section. This function
diff --git a/llvm/include/llvm/Object/ELFObjectFile.h b/llvm/include/llvm/Object/ELFObjectFile.h
index 761c532b9bf1..de418a1782ac 100644
--- a/llvm/include/llvm/Object/ELFObjectFile.h
+++ b/llvm/include/llvm/Object/ELFObjectFile.h
@@ -110,9 +110,13 @@ public:
 
   /// Returns a vector of all BB address maps in the object file. When
   // `TextSectionIndex` is specified, only returns the BB address maps
-  // corresponding to the section with that index.
+  // corresponding to the section with that index. When `PGOAnalyses`is
+  // specified, the vector is cleared then filled with extra PGO data.
+  // `PGOAnalyses` will always be the same length as the return value on
+  // success, otherwise it is empty.
   Expected<std::vector<BBAddrMap>>
-  readBBAddrMap(std::optional<unsigned> TextSectionIndex = std::nullopt) const;
+  readBBAddrMap(std::optional<unsigned> TextSectionIndex = std::nullopt,
+                std::vector<PGOAnalysisMap> *PGOAnalyses = nullptr) const;
 };
 
 class ELFSectionRef : public SectionRef {
diff --git a/llvm/include/llvm/Object/ELFTypes.h b/llvm/include/llvm/Object/ELFTypes.h
index 4670abc867de..d3351a2d1650 100644
--- a/llvm/include/llvm/Object/ELFTypes.h
+++ b/llvm/include/llvm/Object/ELFTypes.h
@@ -13,6 +13,8 @@
 #include "llvm/ADT/StringRef.h"
 #include "llvm/BinaryFormat/ELF.h"
 #include "llvm/Object/Error.h"
+#include "llvm/Support/BlockFrequency.h"
+#include "llvm/Support/BranchProbability.h"
 #include "llvm/Support/Endian.h"
 #include "llvm/Support/Error.h"
 #include "llvm/Support/MathExtras.h"
@@ -875,6 +877,79 @@ struct BBAddrMap {
   std::vector<BBEntry> BBEntries; // Basic block entries for this function.
 };
 
+/// A feature extension of BBAddrMap that holds information relevant to PGO.
+struct PGOAnalysisMap {
+  /// Bitfield of optional features to include in the PGO extended map.
+  struct Features {
+    bool FuncEntryCount : 1;
+    bool BBFreq : 1;
+    bool BrProb : 1;
+
+    // Encodes to minimum bit width representation.
+    uint8_t encode() const {
+      return (static_cast<uint8_t>(FuncEntryCount) << 0) |
+             (static_cast<uint8_t>(BBFreq) << 1) |
+             (static_cast<uint8_t>(BrProb) << 2);
+    }
+
+    // Decodes from minimum bit width representation and validates no
+    // unnecessary bits are used.
+    static Expected<Features> decode(uint8_t Val) {
+      Features Feat{static_cast<bool>(Val & (1 << 0)),
+                    static_cast<bool>(Val & (1 << 1)),
+                    static_cast<bool>(Val & (1 << 2))};
+      if (Feat.encode() != Val)
+        return createStringError(
+            std::error_code(),
+            "invalid encoding for PGOAnalysisMap::Features: 0x%x", Val);
+      return Feat;
+    }
+
+    bool operator==(const Features &Other) const {
+      return std::tie(FuncEntryCount, BBFreq, BrProb) ==
+             std::tie(Other.FuncEntryCount, Other.BBFreq, Other.BrProb);
+    }
+  };
+
+  /// Extra basic block data with fields for block frequency and branch
+  /// probability.
+  struct PGOBBEntry {
+    /// Single successor of a given basic block that contains the tag and branch
+    /// probability associated with it.
+    struct SuccessorEntry {
+      /// Unique ID of this successor basic block.
+      uint32_t ID;
+      /// Branch Probability of the edge to this successor taken from MBPI.
+      BranchProbability Prob;
+
+      bool operator==(const SuccessorEntry &Other) const {
+        return std::tie(ID, Prob) == std::tie(Other.ID, Other.Prob);
+      }
+    };
+
+    /// Block frequency taken from MBFI
+    BlockFrequency BlockFreq;
+    /// List of successors of the current block
+    llvm::SmallVector<SuccessorEntry, 2> Successors;
+
+    bool operator==(const PGOBBEntry &Other) const {
+      return std::tie(BlockFreq, Successors) ==
+             std::tie(Other.BlockFreq, Other.Successors);
+    }
+  };
+
+  uint64_t FuncEntryCount;           // Prof count from IR function
+  std::vector<PGOBBEntry> BBEntries; // Extended basic block entries
+
+  // Flags to indicate if each PGO related info was enabled in this function
+  Features FeatEnable;
+
+  bool operator==(const PGOAnalysisMap &Other) const {
+    return std::tie(FuncEntryCount, BBEntries, FeatEnable) ==
+           std::tie(Other.FuncEntryCount, Other.BBEntries, Other.FeatEnable);
+  }
+};
+
 } // end namespace object.
 } // end namespace llvm.
 
diff --git a/llvm/include/llvm/ObjectYAML/ELFYAML.h b/llvm/include/llvm/ObjectYAML/ELFYAML.h
index 1ba41232f552..12b47c271da2 100644
--- a/llvm/include/llvm/ObjectYAML/ELFYAML.h
+++ b/llvm/include/llvm/ObjectYAML/ELFYAML.h
@@ -170,6 +170,19 @@ struct BBAddrMapEntry {
   std::optional<std::vector<BBEntry>> BBEntries;
 };
 
+struct PGOAnalysisMapEntry {
+  struct PGOBBEntry {
+    struct SuccessorEntry {
+      uint32_t ID;
+      llvm::yaml::Hex32 BrProb;
+    };
+    std::optional<uint64_t> BBFreq;
+    std::optional<std::vector<SuccessorEntry>> Successors;
+  };
+  std::optional<uint64_t> FuncEntryCount;
+  std::optional<std::vector<PGOBBEntry>> PGOBBEntries;
+};
+
 struct StackSizeEntry {
   llvm::yaml::Hex64 Address;
   llvm::yaml::Hex64 Size;
@@ -317,6 +330,7 @@ struct SectionHeaderTable : Chunk {
 
 struct BBAddrMapSection : Section {
   std::optional<std::vector<BBAddrMapEntry>> Entries;
+  std::optional<std::vector<PGOAnalysisMapEntry>> PGOAnalyses;
 
   BBAddrMapSection() : Section(ChunkKind::BBAddrMap) {}
 
@@ -737,6 +751,10 @@ bool shouldAllocateFileSpace(ArrayRef<ProgramHeader> Phdrs,
 LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::ELFYAML::StackSizeEntry)
 LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::ELFYAML::BBAddrMapEntry)
 LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::ELFYAML::BBAddrMapEntry::BBEntry)
+LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::ELFYAML::PGOAnalysisMapEntry)
+LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::ELFYAML::PGOAnalysisMapEntry::PGOBBEntry)
+LLVM_YAML_IS_SEQUENCE_VECTOR(
+    llvm::ELFYAML::PGOAnalysisMapEntry::PGOBBEntry::SuccessorEntry)
 LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::ELFYAML::DynamicEntry)
 LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::ELFYAML::LinkerOption)
 LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::ELFYAML::CallGraphEntryWeight)
@@ -905,6 +923,21 @@ template <> struct MappingTraits<ELFYAML::BBAddrMapEntry::BBEntry> {
   static void mapping(IO &IO, ELFYAML::BBAddrMapEntry::BBEntry &Rel);
 };
 
+template <> struct MappingTraits<ELFYAML::PGOAnalysisMapEntry> {
+  static void mapping(IO &IO, ELFYAML::PGOAnalysisMapEntry &Rel);
+};
+
+template <> struct MappingTraits<ELFYAML::PGOAnalysisMapEntry::PGOBBEntry> {
+  static void mapping(IO &IO, ELFYAML::PGOAnalysisMapEntry::PGOBBEntry &Rel);
+};
+
+template <>
+struct MappingTraits<ELFYAML::PGOAnalysisMapEntry::PGOBBEntry::SuccessorEntry> {
+  static void
+  mapping(IO &IO,
+          ELFYAML::PGOAnalysisMapEntry::PGOBBEntry::SuccessorEntry &Rel);
+};
+
 template <> struct MappingTraits<ELFYAML::GnuHashHeader> {
   static void mapping(IO &IO, ELFYAML::GnuHashHeader &Rel);
 };
diff --git a/llvm/lib/Object/ELF.cpp b/llvm/lib/Object/ELF.cpp
index 36847d1a2a42..300639f2bfa0 100644
--- a/llvm/lib/Object/ELF.cpp
+++ b/llvm/lib/Object/ELF.cpp
@@ -646,11 +646,36 @@ ELFFile<ELFT>::toMappedAddr(uint64_t VAddr, WarningHandler WarnHandler) const {
   return base() + Offset;
 }
 
-template <class ELFT>
-Expected<std::vector<BBAddrMap>>
-ELFFile<ELFT>::decodeBBAddrMap(const Elf_Shdr &Sec,
-                               const Elf_Shdr *RelaSec) const {
-  bool IsRelocatable = getHeader().e_type == ELF::ET_REL;
+// Helper to extract and decode the next ULEB128 value as unsigned int.
+// Returns zero and sets ULEBSizeErr if the ULEB128 value exceeds the unsigned
+// int limit.
+// Also returns zero if ULEBSizeErr is already in an error state.
+// ULEBSizeErr is an out variable if an error occurs.
+template <typename IntTy, std::enable_if_t<std::is_unsigned_v<IntTy>, int> = 0>
+static IntTy readULEB128As(DataExtractor &Data, DataExtractor::Cursor &Cur,
+                           Error &ULEBSizeErr) {
+  // Bail out and do not extract data if ULEBSizeErr is already set.
+  if (ULEBSizeErr)
+    return 0;
+  uint64_t Offset = Cur.tell();
+  uint64_t Value = Data.getULEB128(Cur);
+  if (Value > std::numeric_limits<IntTy>::max()) {
+    ULEBSizeErr = createError("ULEB128 value at offset 0x" +
+                              Twine::utohexstr(Offset) + " exceeds UINT" +
+                              Twine(std::numeric_limits<IntTy>::digits) +
+                              "_MAX (0x" + Twine::utohexstr(Value) + ")");
+    return 0;
+  }
+  return static_cast<IntTy>(Value);
+}
+
+template <typename ELFT>
+static Expected<std::vector<BBAddrMap>>
+decodeBBAddrMapImpl(const ELFFile<ELFT> &EF,
+                    const typename ELFFile<ELFT>::Elf_Shdr &Sec,
+                    const typename ELFFile<ELFT>::Elf_Shdr *RelaSec,
+                    std::vector<PGOAnalysisMap> *PGOAnalyses) {
+  bool IsRelocatable = EF.getHeader().e_type == ELF::ET_REL;
 
   // This DenseMap maps the offset of each function (the location of the
   // reference to the function in the SHT_LLVM_BB_ADDR_MAP section) to the
@@ -660,44 +685,28 @@ ELFFile<ELFT>::decodeBBAddrMap(const Elf_Shdr &Sec,
     assert(RelaSec &&
            "Can't read a SHT_LLVM_BB_ADDR_MAP section in a relocatable "
            "object file without providing a relocation section.");
-    Expected<Elf_Rela_Range> Relas = this->relas(*RelaSec);
+    Expected<typename ELFFile<ELFT>::Elf_Rela_Range> Relas = EF.relas(*RelaSec);
     if (!Relas)
       return createError("unable to read relocations for section " +
-                         describe(*this, Sec) + ": " +
+                         describe(EF, Sec) + ": " +
                          toString(Relas.takeError()));
-    for (Elf_Rela Rela : *Relas)
+    for (typename ELFFile<ELFT>::Elf_Rela Rela : *Relas)
       FunctionOffsetTranslations[Rela.r_offset] = Rela.r_addend;
   }
-  Expected<ArrayRef<uint8_t>> ContentsOrErr = getSectionContents(Sec);
+  Expected<ArrayRef<uint8_t>> ContentsOrErr = EF.getSectionContents(Sec);
   if (!ContentsOrErr)
     return ContentsOrErr.takeError();
   ArrayRef<uint8_t> Content = *ContentsOrErr;
-  DataExtractor Data(Content, isLE(), ELFT::Is64Bits ? 8 : 4);
+  DataExtractor Data(Content, EF.isLE(), ELFT::Is64Bits ? 8 : 4);
   std::vector<BBAddrMap> FunctionEntries;
 
   DataExtractor::Cursor Cur(0);
   Error ULEBSizeErr = Error::success();
   Error MetadataDecodeErr = Error::success();
-  // Helper to extract and decode the next ULEB128 value as uint32_t.
-  // Returns zero and sets ULEBSizeErr if the ULEB128 value exceeds the uint32_t
-  // limit.
-  // Also returns zero if ULEBSizeErr is already in an error state.
-  auto ReadULEB128AsUInt32 = [&Data, &Cur, &ULEBSizeErr]() -> uint32_t {
-    // Bail out and do not extract data if ULEBSizeErr is already set.
-    if (ULEBSizeErr)
-      return 0;
-    uint64_t Offset = Cur.tell();
-    uint64_t Value = Data.getULEB128(Cur);
-    if (Value > UINT32_MAX) {
-      ULEBSizeErr = createError(
-          "ULEB128 value at offset 0x" + Twine::utohexstr(Offset) +
-          " exceeds UINT32_MAX (0x" + Twine::utohexstr(Value) + ")");
-      return 0;
-    }
-    return static_cast<uint32_t>(Value);
-  };
 
   uint8_t Version = 0;
+  uint8_t Feature = 0;
+  PGOAnalysisMap::Features FeatEnable{};
   while (!ULEBSizeErr && !MetadataDecodeErr && Cur &&
          Cur.tell() < Content.size()) {
     if (Sec.sh_type == ELF::SHT_LLVM_BB_ADDR_MAP) {
@@ -707,10 +716,24 @@ ELFFile<ELFT>::decodeBBAddrMap(const Elf_Shdr &Sec,
       if (Version > 2)
         return createError("unsupported SHT_LLVM_BB_ADDR_MAP version: " +
                            Twine(static_cast<int>(Version)));
-      Data.getU8(Cur); // Feature byte
+      Feature = Data.getU8(Cur); // Feature byte
+      if (!Cur)
+        break;
+      auto FeatEnableOrErr = PGOAnalysisMap::Features::decode(Feature);
+      if (!FeatEnableOrErr)
+        return FeatEnableOrErr.takeError();
+      FeatEnable =
+          FeatEnableOrErr ? *FeatEnableOrErr : PGOAnalysisMap::Features{};
+      if (Feature != 0 && Version < 2 && Cur)
+        return createError(
+            "version should be >= 2 for SHT_LLVM_BB_ADDR_MAP when "
+            "PGO features are enabled: version = " +
+            Twine(static_cast<int>(Version)) +
+            " feature = " + Twine(static_cast<int>(Feature)));
     }
     uint64_t SectionOffset = Cur.tell();
-    uintX_t Address = static_cast<uintX_t>(Data.getAddress(Cur));
+    auto Address =
+        static_cast<typename ELFFile<ELFT>::uintX_t>(Data.getAddress(Cur));
     if (!Cur)
       return Cur.takeError();
     if (IsRelocatable) {
@@ -719,20 +742,23 @@ ELFFile<ELFT>::decodeBBAddrMap(const Elf_Shdr &Sec,
       if (FOTIterator == FunctionOffsetTranslations.end()) {
         return createError("failed to get relocation data for offset: " +
                            Twine::utohexstr(SectionOffset) + " in section " +
-                           describe(*this, Sec));
+                           describe(EF, Sec));
       }
       Address = FOTIterator->second;
     }
-    uint32_t NumBlocks = ReadULEB128AsUInt32();
+    uint32_t NumBlocks = readULEB128As<uint32_t>(Data, Cur, ULEBSizeErr);
+
     std::vector<BBAddrMap::BBEntry> BBEntries;
     uint32_t PrevBBEndOffset = 0;
     for (uint32_t BlockIndex = 0;
          !MetadataDecodeErr && !ULEBSizeErr && Cur && (BlockIndex < NumBlocks);
          ++BlockIndex) {
-      uint32_t ID = Version >= 2 ? ReadULEB128AsUInt32() : BlockIndex;
-      uint32_t Offset = ReadULEB128AsUInt32();
-      uint32_t Size = ReadULEB128AsUInt32();
-      uint32_t MD = ReadULEB128AsUInt32();
+      uint32_t ID = Version >= 2
+                        ? readULEB128As<uint32_t>(Data, Cur, ULEBSizeErr)
+                        : BlockIndex;
+      uint32_t Offset = readULEB128As<uint32_t>(Data, Cur, ULEBSizeErr);
+      uint32_t Size = readULEB128As<uint32_t>(Data, Cur, ULEBSizeErr);
+      uint32_t MD = readULEB128As<uint32_t>(Data, Cur, ULEBSizeErr);
       if (Version >= 1) {
         // Offset is calculated relative to the end of the previous BB.
         Offset += PrevBBEndOffset;
@@ -747,6 +773,44 @@ ELFFile<ELFT>::decodeBBAddrMap(const Elf_Shdr &Sec,
       BBEntries.push_back({ID, Offset, Size, *MetadataOrErr});
     }
     FunctionEntries.emplace_back(Address, std::move(BBEntries));
+
+    if (FeatEnable.FuncEntryCount || FeatEnable.BBFreq || FeatEnable.BrProb) {
+      // Function entry count
+      uint64_t FuncEntryCount =
+          FeatEnable.FuncEntryCount
+              ? readULEB128As<uint64_t>(Data, Cur, ULEBSizeErr)
+              : 0;
+
+      std::vector<PGOAnalysisMap::PGOBBEntry> PGOBBEntries;
+      for (uint32_t BlockIndex = 0; !MetadataDecodeErr && !ULEBSizeErr && Cur &&
+                                    (BlockIndex < NumBlocks);
+           ++BlockIndex) {
+        // Block frequency
+        uint64_t BBF = FeatEnable.BBFreq
+                           ? readULEB128As<uint64_t>(Data, Cur, ULEBSizeErr)
+                           : 0;
+
+        // Branch probability
+        llvm::SmallVector<PGOAnalysisMap::PGOBBEntry::SuccessorEntry, 2>
+            Successors;
+        if (FeatEnable.BrProb) {
+          auto SuccCount = readULEB128As<uint64_t>(Data, Cur, ULEBSizeErr);
+          for (uint64_t I = 0; I < SuccCount; ++I) {
+            uint32_t BBID = readULEB128As<uint32_t>(Data, Cur, ULEBSizeErr);
+            uint32_t BrProb = readULEB128As<uint32_t>(Data, Cur, ULEBSizeErr);
+            if (PGOAnalyses)
+              Successors.push_back({BBID, BranchProbability::getRaw(BrProb)});
+          }
+        }
+
+        if (PGOAnalyses)
+          PGOBBEntries.push_back({BlockFrequency(BBF), std::move(Successors)});
+      }
+
+      if (PGOAnalyses)
+        PGOAnalyses->push_back(
+            {FuncEntryCount, std::move(PGOBBEntries), FeatEnable});
+    }
   }
   // Either Cur is in the error state, or we have an error in ULEBSizeErr or
   // MetadataDecodeErr (but not both), but we join all errors here to be safe.
@@ -756,6 +820,18 @@ ELFFile<ELFT>::decodeBBAddrMap(const Elf_Shdr &Sec,
   return FunctionEntries;
 }
 
+template <class ELFT>
+Expected<std::vector<BBAddrMap>>
+ELFFile<ELFT>::decodeBBAddrMap(const Elf_Shdr &Sec, const Elf_Shdr *RelaSec,
+                               std::vector<PGOAnalysisMap> *PGOAnalyses) const {
+  size_t OriginalPGOSize = PGOAnalyses ? PGOAnalyses->size() : 0;
+  auto AddrMapsOrErr = decodeBBAddrMapImpl(*this, Sec, RelaSec, PGOAnalyses);
+  // remove new analyses when an error occurs
+  if (!AddrMapsOrErr && PGOAnalyses)
+    PGOAnalyses->resize(OriginalPGOSize);
+  return std::move(AddrMapsOrErr);
+}
+
 template <class ELFT>
 Expected<
     MapVector<const typename ELFT::Shdr *, const typename ELFT::Shdr *>>
diff --git a/llvm/lib/Object/ELFObjectFile.cpp b/llvm/lib/Object/ELFObjectFile.cpp
index 25dbcbd68431..3c86b0f25dda 100644
--- a/llvm/lib/Object/ELFObjectFile.cpp
+++ b/llvm/lib/Object/ELFObjectFile.cpp
@@ -716,10 +716,13 @@ std::vector<ELFPltEntry> ELFObjectFileBase::getPltEntries() const {
 
 template <class ELFT>
 Expected<std::vector<BBAddrMap>> static readBBAddrMapImpl(
-    const ELFFile<ELFT> &EF, std::optional<unsigned> TextSectionIndex) {
+    const ELFFile<ELFT> &EF, std::optional<unsigned> TextSectionIndex,
+    std::vector<PGOAnalysisMap> *PGOAnalyses) {
   using Elf_Shdr = typename ELFT::Shdr;
   bool IsRelocatable = EF.getHeader().e_type == ELF::ET_REL;
   std::vector<BBAddrMap> BBAddrMaps;
+  if (PGOAnalyses)
+    PGOAnalyses->clear();
 
   const auto &Sections = cantFail(EF.sections());
   auto IsMatch = [&](const Elf_Shdr &Sec) -> Expected<bool> {
@@ -748,10 +751,13 @@ Expected<std::vector<BBAddrMap>> static readBBAddrMapImpl(
       return createError("unable to get relocation section for " +
                          describe(EF, *Sec));
     Expected<std::vector<BBAddrMap>> BBAddrMapOrErr =
-        EF.decodeBBAddrMap(*Sec, RelocSec);
-    if (!BBAddrMapOrErr)
+        EF.decodeBBAddrMap(*Sec, RelocSec, PGOAnalyses);
+    if (!BBAddrMapOrErr) {
+      if (PGOAnalyses)
+        PGOAnalyses->clear();
       return createError("unable to read " + describe(EF, *Sec) + ": " +
                          toString(BBAddrMapOrErr.takeError()));
+    }
     std::move(BBAddrMapOrErr->begin(), BBAddrMapOrErr->end(),
               std::back_inserter(BBAddrMaps));
   }
@@ -828,13 +834,14 @@ ELFObjectFileBase::readDynsymVersions() const {
 }
 
 Expected<std::vector<BBAddrMap>> ELFObjectFileBase::readBBAddrMap(
-    std::optional<unsigned> TextSectionIndex) const {
+    std::optional<unsigned> TextSectionIndex,
+    std::vector<PGOAnalysisMap> *PGOAnalyses) const {
   if (const auto *Obj = dyn_cast<ELF32LEObjectFile>(this))
-    return readBBAddrMapImpl(Obj->getELFFile(), TextSectionIndex);
+    return readBBAddrMapImpl(Obj->getELFFile(), TextSectionIndex, PGOAnalyses);
   if (const auto *Obj = dyn_cast<ELF64LEObjectFile>(this))
-    return readBBAddrMapImpl(Obj->getELFFile(), TextSectionIndex);
+    return readBBAddrMapImpl(Obj->getELFFile(), TextSectionIndex, PGOAnalyses);
   if (const auto *Obj = dyn_cast<ELF32BEObjectFile>(this))
-    return readBBAddrMapImpl(Obj->getELFFile(), TextSectionIndex);
+    return readBBAddrMapImpl(Obj->getELFFile(), TextSectionIndex, PGOAnalyses);
   return readBBAddrMapImpl(cast<ELF64BEObjectFile>(this)->getELFFile(),
-                           TextSectionIndex);
+                           TextSectionIndex, PGOAnalyses);
 }
diff --git a/llvm/lib/ObjectYAML/ELFEmitter.cpp b/llvm/lib/ObjectYAML/ELFEmitter.cpp
index d54faec20866..94b0529f7610 100644
--- a/llvm/lib/ObjectYAML/ELFEmitter.cpp
+++ b/llvm/lib/ObjectYAML/ELFEmitter.cpp
@@ -32,6 +32,7 @@
 #include "llvm/Support/YAMLTraits.h"
 #include "llvm/Support/raw_ostream.h"
 #include <optional>
+#include <variant>
 
 using namespace llvm;
 
@@ -1390,10 +1391,24 @@ template <class ELFT>
 void ELFState<ELFT>::writeSectionContent(
     Elf_Shdr &SHeader, const ELFYAML::BBAddrMapSection &Section,
     ContiguousBlobAccumulator &CBA) {
-  if (!Section.Entries)
+  if (!Section.Entries) {
+    if (Section.PGOAnalyses)
+      WithColor::warning()
+          << "PGOAnalyses should not exist in SHT_LLVM_BB_ADDR_MAP when "
+             "Entries does not exist";
     return;
+  }
+
+  const std::vector<ELFYAML::PGOAnalysisMapEntry> *PGOAnalyses = nullptr;
+  if (Section.PGOAnalyses) {
+    if (Section.Entries->size() != Section.PGOAnalyses->size())
+      WithColor::warning() << "PGOAnalyses must be the same length as Entries "
+                              "in SHT_LLVM_BB_ADDR_MAP";
+    else
+      PGOAnalyses = &Section.PGOAnalyses.value();
+  }
 
-  for (const ELFYAML::BBAddrMapEntry &E : *Section.Entries) {
+  for (const auto &[Idx, E] : llvm::enumerate(*Section.Entries)) {
     // Write version and feature values.
     if (Section.Type == llvm::ELF::SHT_LLVM_BB_ADDR_MAP) {
       if (E.Version > 2)
@@ -1404,6 +1419,14 @@ void ELFState<ELFT>::writeSectionContent(
       CBA.write(E.Feature);
       SHeader.sh_size += 2;
     }
+
+    if (Section.PGOAnalyses) {
+      if (E.Version < 2)
+        WithColor::warning()
+            << "unsupported SHT_LLVM_BB_ADDR_MAP version when using PGO: "
+            << static_cast<int>(E.Version) << "; must use version >= 2";
+    }
+
     // Write the address of the function.
     CBA.write<uintX_t>(E.Address, ELFT::TargetEndianness);
     // Write number of BBEntries (number of basic blocks in the function). This
@@ -1412,14 +1435,43 @@ void ELFState<ELFT>::writeSectionContent(
         E.NumBlocks.value_or(E.BBEntries ? E.BBEntries->size() : 0);
     SHeader.sh_size += sizeof(uintX_t) + CBA.writeULEB128(NumBlocks);
     // Write all BBEntries.
-    if (!E.BBEntries)
+    if (E.BBEntries) {
+      for (const ELFYAML::BBAddrMapEntry::BBEntry &BBE : *E.BBEntries) {
+        if (Section.Type == llvm::ELF::SHT_LLVM_BB_ADDR_MAP && E.Version > 1)
+          SHeader.sh_size += CBA.writeULEB128(BBE.ID);
+        SHeader.sh_size += CBA.writeULEB128(BBE.AddressOffset) +
+                           CBA.writeULEB128(BBE.Size) +
+                           CBA.writeULEB128(BBE.Metadata);
+      }
+    }
+
+    if (!PGOAnalyses)
       continue;
-    for (const ELFYAML::BBAddrMapEntry::BBEntry &BBE : *E.BBEntries) {
-      if (Section.Type == llvm::ELF::SHT_LLVM_BB_ADDR_MAP && E.Version > 1)
-        SHeader.sh_size += CBA.writeULEB128(BBE.ID);
-      SHeader.sh_size += CBA.writeULEB128(BBE.AddressOffset) +
-                         CBA.writeULEB128(BBE.Size) +
-                         CBA.writeULEB128(BBE.Metadata);
+    const ELFYAML::PGOAnalysisMapEntry &PGOEntry = PGOAnalyses->at(Idx);
+
+    if (PGOEntry.FuncEntryCount)
+      SHeader.sh_size += CBA.writeULEB128(*PGOEntry.FuncEntryCount);
+
+    if (!PGOEntry.PGOBBEntries)
+      continue;
+
+    const auto &PGOBBEntries = PGOEntry.PGOBBEntries.value();
+    if (!E.BBEntries || E.BBEntries->size() != PGOBBEntries.size()) {
+      WithColor::warning() << "PBOBBEntries must be the same length as "
+                              "BBEntries in SHT_LLVM_BB_ADDR_MAP.\n"
+                           << "Mismatch on function with address: "
+                           << E.Address;
+      continue;
+    }
+
+    for (const auto &PGOBBE : PGOBBEntries) {
+      if (PGOBBE.BBFreq)
+        SHeader.sh_size += CBA.writeULEB128(*PGOBBE.BBFreq);
+      if (PGOBBE.Successors) {
+        SHeader.sh_size += CBA.writeULEB128(PGOBBE.Successors->size());
+        for (const auto &[ID, BrProb] : *PGOBBE.Successors)
+          SHeader.sh_size += CBA.writeULEB128(ID) + CBA.writeULEB128(BrProb);
+      }
     }
   }
 }
diff --git a/llvm/lib/ObjectYAML/ELFYAML.cpp b/llvm/lib/ObjectYAML/ELFYAML.cpp
index 9d845a0c7c48..6ad4a067415a 100644
--- a/llvm/lib/ObjectYAML/ELFYAML.cpp
+++ b/llvm/lib/ObjectYAML/ELFYAML.cpp
@@ -1390,6 +1390,7 @@ static void sectionMapping(IO &IO, ELFYAML::BBAddrMapSection &Section) {
   commonSectionMapping(IO, Section);
   IO.mapOptional("Content", Section.Content);
   IO.mapOptional("Entries", Section.Entries);
+  IO.mapOptional("PGOAnalyses", Section.PGOAnalyses);
 }
 
 static void sectionMapping(IO &IO, ELFYAML::StackSizesSection &Section) {
@@ -1825,6 +1826,28 @@ void MappingTraits<ELFYAML::BBAddrMapEntry::BBEntry>::mapping(
   IO.mapRequired("Metadata", E.Metadata);
 }
 
+void MappingTraits<ELFYAML::PGOAnalysisMapEntry>::mapping(
+    IO &IO, ELFYAML::PGOAnalysisMapEntry &E) {
+  assert(IO.getContext() && "The IO context is not initialized");
+  IO.mapOptional("FuncEntryCount", E.FuncEntryCount);
+  IO.mapOptional("PGOBBEntries", E.PGOBBEntries);
+}
+
+void MappingTraits<ELFYAML::PGOAnalysisMapEntry::PGOBBEntry>::mapping(
+    IO &IO, ELFYAML::PGOAnalysisMapEntry::PGOBBEntry &E) {
+  assert(IO.getContext() && "The IO context is not initialized");
+  IO.mapOptional("BBFreq", E.BBFreq);
+  IO.mapOptional("Successors", E.Successors);
+}
+
+void MappingTraits<ELFYAML::PGOAnalysisMapEntry::PGOBBEntry::SuccessorEntry>::
+    mapping(IO &IO,
+            ELFYAML::PGOAnalysisMapEntry::PGOBBEntry::SuccessorEntry &E) {
+  assert(IO.getContext() && "The IO context is not initialized");
+  IO.mapRequired("ID", E.ID);
+  IO.mapRequired("BrProb", E.BrProb);
+}
+
 void MappingTraits<ELFYAML::GnuHashHeader>::mapping(IO &IO,
                                                     ELFYAML::GnuHashHeader &E) {
   assert(IO.getContext() && "The IO context is not initialized");
diff --git a/llvm/unittests/Object/ELFObjectFileTest.cpp b/llvm/unittests/Object/ELFObjectFileTest.cpp
index 17402f39a5df..2878ca088cd7 100644
--- a/llvm/unittests/Object/ELFObjectFileTest.cpp
+++ b/llvm/unittests/Object/ELFObjectFileTest.cpp
@@ -9,6 +9,7 @@
 #include "llvm/Object/ELFObjectFile.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ObjectYAML/yaml2obj.h"
+#include "llvm/Support/BlockFrequency.h"
 #include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/YAMLTraits.h"
 #include "llvm/Testing/Support/Error.h"
@@ -683,7 +684,7 @@ Sections:
         ElfOrErr->getELFFile().getSection(1);
     ASSERT_THAT_EXPECTED(BBAddrMapSecOrErr, Succeeded());
     auto BBAddrMaps = ElfOrErr->readBBAddrMap(TextSectionIndex);
-    EXPECT_THAT_EXPECTED(BBAddrMaps, Succeeded());
+    ASSERT_THAT_EXPECTED(BBAddrMaps, Succeeded());
     EXPECT_EQ(*BBAddrMaps, ExpectedResult);
   };
 
@@ -744,6 +745,389 @@ Sections:
                   Section1BBAddrMaps);
 }
 
+// Tests for error paths of the ELFFile::decodeBBAddrMap with PGOAnalysisMap
+// API.
+TEST(ELFObjectFileTest, InvalidDecodePGOAnalysisMap) {
+  if (IsHostWindows())
+    GTEST_SKIP();
+  StringRef CommonYamlString(R"(
+--- !ELF
+FileHeader:
+  Class: ELFCLASS64
+  Data:  ELFDATA2LSB
+  Type:  ET_EXEC
+Sections:
+  - Type: SHT_LLVM_BB_ADDR_MAP
+    Name: .llvm_bb_addr_map
+    Entries:
+      - Address: 0x11111
+)");
+
+  auto DoCheck = [&](StringRef YamlString, const char *ErrMsg) {
+    SmallString<0> Storage;
+    Expected<ELFObjectFile<ELF64LE>> ElfOrErr =
+        toBinary<ELF64LE>(Storage, YamlString);
+    ASSERT_THAT_EXPECTED(ElfOrErr, Succeeded());
+    const ELFFile<ELF64LE> &Elf = ElfOrErr->getELFFile();
+
+    Expected<const typename ELF64LE::Shdr *> BBAddrMapSecOrErr =
+        Elf.getSection(1);
+    ASSERT_THAT_EXPECTED(BBAddrMapSecOrErr, Succeeded());
+
+    std::vector<PGOAnalysisMap> PGOAnalyses;
+    EXPECT_THAT_ERROR(
+        Elf.decodeBBAddrMap(**BBAddrMapSecOrErr, nullptr, &PGOAnalyses)
+            .takeError(),
+        FailedWithMessage(ErrMsg));
+  };
+
+  // Check that we can detect unsupported versions that are too old.
+  SmallString<128> UnsupportedLowVersionYamlString(CommonYamlString);
+  UnsupportedLowVersionYamlString += R"(
+        Version: 1
+        Feature: 0x4
+        BBEntries:
+          - AddressOffset: 0x0
+            Size:          0x1
+            Metadata:      0x2
+)";
+
+  DoCheck(UnsupportedLowVersionYamlString,
+          "version should be >= 2 for SHT_LLVM_BB_ADDR_MAP when PGO features "
+          "are enabled: version = 1 feature = 4");
+
+  SmallString<128> CommonVersionedYamlString(CommonYamlString);
+  CommonVersionedYamlString += R"(
+        Version: 2
+        BBEntries:
+          - ID:            1
+            AddressOffset: 0x0
+            Size:          0x1
+            Metadata:      0x2
+)";
+
+  // Check that we fail when function entry count is enabled but not provided.
+  SmallString<128> MissingFuncEntryCount(CommonYamlString);
+  MissingFuncEntryCount += R"(
+        Version: 2
+        Feature: 0x01
+)";
+
+  DoCheck(MissingFuncEntryCount,
+          "unable to decode LEB128 at offset 0x0000000b: malformed uleb128, "
+          "extends past end");
+
+  // Check that we fail when basic block frequency is enabled but not provided.
+  SmallString<128> MissingBBFreq(CommonYamlString);
+  MissingBBFreq += R"(
+        Version: 2
+        Feature: 0x02
+        BBEntries:
+          - ID:            1
+            AddressOffset: 0x0
+            Size:          0x1
+            Metadata:      0x2
+)";
+
+  DoCheck(MissingBBFreq, "unable to decode LEB128 at offset 0x0000000f: "
+                         "malformed uleb128, extends past end");
+
+  // Check that we fail when branch probability is enabled but not provided.
+  SmallString<128> MissingBrProb(CommonYamlString);
+  MissingBrProb += R"(
+        Version: 2
+        Feature: 0x04
+        BBEntries:
+          - ID:            1
+            AddressOffset: 0x0
+            Size:          0x1
+            Metadata:      0x6
+          - ID:            2
+            AddressOffset: 0x1
+            Size:          0x1
+            Metadata:      0x2
+          - ID:            3
+            AddressOffset: 0x2
+            Size:          0x1
+            Metadata:      0x2
+    PGOAnalyses:
+      - PGOBBEntries:
+         - Successors:
+            - ID:          2
+              BrProb:      0x80000000
+            - ID:          3
+              BrProb:      0x80000000
+         - Successors:
+            - ID:          3
+              BrProb:      0xF0000000
+)";
+
+  DoCheck(MissingBrProb, "unable to decode LEB128 at offset 0x00000017: "
+                         "malformed uleb128, extends past end");
+}
+
+// Test for the ELFObjectFile::readBBAddrMap API with PGOAnalysisMap.
+TEST(ELFObjectFileTest, ReadPGOAnalysisMap) {
+  if (IsHostWindows())
+    GTEST_SKIP();
+  StringRef CommonYamlString(R"(
+--- !ELF
+FileHeader:
+  Class: ELFCLASS64
+  Data:  ELFDATA2LSB
+  Type:  ET_EXEC
+Sections:
+  - Name: .llvm_bb_addr_map_1
+    Type: SHT_LLVM_BB_ADDR_MAP
+    Link: 1
+    Entries:
+      - Version: 2
+        Address: 0x11111
+        Feature: 0x1
+        BBEntries:
+          - ID:            1
+            AddressOffset: 0x0
+            Size:          0x1
+            Metadata:      0x2
+    PGOAnalyses:
+      - FuncEntryCount: 892
+  - Name: .llvm_bb_addr_map_2
+    Type: SHT_LLVM_BB_ADDR_MAP
+    Link: 1
+    Entries:
+      - Version: 2
+        Address: 0x22222
+        Feature: 0x2
+        BBEntries:
+          - ID:            2
+            AddressOffset: 0x0
+            Size:          0x2
+            Metadata:      0x4
+    PGOAnalyses:
+      - PGOBBEntries:
+         - BBFreq:         343
+  - Name: .llvm_bb_addr_map_3
+    Type: SHT_LLVM_BB_ADDR_MAP
+    Link: 2
+    Entries:
+      - Version: 2
+        Address: 0x33333
+        Feature: 0x4
+        BBEntries:
+          - ID:            0
+            AddressOffset: 0x0
+            Size:          0x3
+            Metadata:      0x6
+          - ID:            1
+            AddressOffset: 0x0
+            Size:          0x3
+            Metadata:      0x4
+          - ID:            2
+            AddressOffset: 0x0
+            Size:          0x3
+            Metadata:      0x0
+    PGOAnalyses:
+      - PGOBBEntries:
+         - Successors:
+            - ID:          1
+              BrProb:      0x11111111
+            - ID:          2
+              BrProb:      0xeeeeeeee
+         - Successors:
+            - ID:          2
+              BrProb:      0xffffffff
+         - Successors:     []
+  - Name: .llvm_bb_addr_map_4
+    Type: SHT_LLVM_BB_ADDR_MAP
+  # Link: 0 (by default, can be overriden)
+    Entries:
+      - Version: 2
+        Address: 0x44444
+        Feature: 0x7
+        BBEntries:
+          - ID:            0
+            AddressOffset: 0x0
+            Size:          0x4
+            Metadata:      0x18
+          - ID:            1
+            AddressOffset: 0x0
+            Size:          0x4
+            Metadata:      0x0
+          - ID:            2
+            AddressOffset: 0x0
+            Size:          0x4
+            Metadata:      0x0
+          - ID:            3
+            AddressOffset: 0x0
+            Size:          0x4
+            Metadata:      0x0
+    PGOAnalyses:
+      - FuncEntryCount: 1000
+        PGOBBEntries:
+          - BBFreq:         1000
+            Successors:
+            - ID:          1
+              BrProb:      0x22222222
+            - ID:          2
+              BrProb:      0x33333333
+            - ID:          3
+              BrProb:      0xaaaaaaaa
+          - BBFreq:         133
+            Successors:
+            - ID:          2
+              BrProb:      0x11111111
+            - ID:          3
+              BrProb:      0xeeeeeeee
+          - BBFreq:         18
+            Successors:
+            - ID:          3
+              BrProb:      0xffffffff
+          - BBFreq:         1000
+            Successors:    []
+)");
+
+  BBAddrMap E1(0x11111, {{1, 0x0, 0x1, {false, true, false, false, false}}});
+  PGOAnalysisMap P1 = {892, {{}}, {true, false, false}};
+  BBAddrMap E2(0x22222, {{2, 0x0, 0x2, {false, false, true, false, false}}});
+  PGOAnalysisMap P2 = {{}, {{BlockFrequency(343), {}}}, {false, true, false}};
+  BBAddrMap E3(0x33333, {{0, 0x0, 0x3, {false, true, true, false, false}},
+                         {1, 0x3, 0x3, {false, false, true, false, false}},
+                         {2, 0x6, 0x3, {false, false, false, false, false}}});
+  PGOAnalysisMap P3 = {{},
+                       {{{},
+                         {{1, BranchProbability::getRaw(0x1111'1111)},
+                          {2, BranchProbability::getRaw(0xeeee'eeee)}}},
+                        {{}, {{2, BranchProbability::getRaw(0xffff'ffff)}}},
+                        {{}, {}}},
+                       {false, false, true}};
+  BBAddrMap E4(0x44444, {{0, 0x0, 0x4, {false, false, false, true, true}},
+                         {1, 0x4, 0x4, {false, false, false, false, false}},
+                         {2, 0x8, 0x4, {false, false, false, false, false}},
+                         {3, 0xc, 0x4, {false, false, false, false, false}}});
+  PGOAnalysisMap P4 = {
+      1000,
+      {{BlockFrequency(1000),
+        {{1, BranchProbability::getRaw(0x2222'2222)},
+         {2, BranchProbability::getRaw(0x3333'3333)},
+         {3, BranchProbability::getRaw(0xaaaa'aaaa)}}},
+       {BlockFrequency(133),
+        {{2, BranchProbability::getRaw(0x1111'1111)},
+         {3, BranchProbability::getRaw(0xeeee'eeee)}}},
+       {BlockFrequency(18), {{3, BranchProbability::getRaw(0xffff'ffff)}}},
+       {BlockFrequency(1000), {}}},
+      {true, true, true}};
+
+  std::vector<BBAddrMap> Section0BBAddrMaps = {E4};
+  std::vector<BBAddrMap> Section1BBAddrMaps = {E3};
+  std::vector<BBAddrMap> Section2BBAddrMaps = {E1, E2};
+  std::vector<BBAddrMap> AllBBAddrMaps = {E1, E2, E3, E4};
+
+  std::vector<PGOAnalysisMap> Section0PGOAnalysisMaps = {P4};
+  std::vector<PGOAnalysisMap> Section1PGOAnalysisMaps = {P3};
+  std::vector<PGOAnalysisMap> Section2PGOAnalysisMaps = {P1, P2};
+  std::vector<PGOAnalysisMap> AllPGOAnalysisMaps = {P1, P2, P3, P4};
+
+  auto DoCheckSucceeds =
+      [&](StringRef YamlString, std::optional<unsigned> TextSectionIndex,
+          std::vector<BBAddrMap> ExpectedResult,
+          std::optional<std::vector<PGOAnalysisMap>> ExpectedPGO) {
+        SmallString<0> Storage;
+        Expected<ELFObjectFile<ELF64LE>> ElfOrErr =
+            toBinary<ELF64LE>(Storage, YamlString);
+        ASSERT_THAT_EXPECTED(ElfOrErr, Succeeded());
+
+        Expected<const typename ELF64LE::Shdr *> BBAddrMapSecOrErr =
+            ElfOrErr->getELFFile().getSection(1);
+        ASSERT_THAT_EXPECTED(BBAddrMapSecOrErr, Succeeded());
+
+        std::vector<PGOAnalysisMap> PGOAnalyses;
+        auto BBAddrMaps = ElfOrErr->readBBAddrMap(
+            TextSectionIndex, ExpectedPGO ? &PGOAnalyses : nullptr);
+        ASSERT_THAT_EXPECTED(BBAddrMaps, Succeeded());
+        EXPECT_EQ(*BBAddrMaps, ExpectedResult);
+        if (ExpectedPGO) {
+          EXPECT_EQ(BBAddrMaps->size(), PGOAnalyses.size());
+          EXPECT_EQ(PGOAnalyses, *ExpectedPGO);
+        }
+      };
+
+  auto DoCheckFails = [&](StringRef YamlString,
+                          std::optional<unsigned> TextSectionIndex,
+                          const char *ErrMsg) {
+    SmallString<0> Storage;
+    Expected<ELFObjectFile<ELF64LE>> ElfOrErr =
+        toBinary<ELF64LE>(Storage, YamlString);
+    ASSERT_THAT_EXPECTED(ElfOrErr, Succeeded());
+
+    Expected<const typename ELF64LE::Shdr *> BBAddrMapSecOrErr =
+        ElfOrErr->getELFFile().getSection(1);
+    ASSERT_THAT_EXPECTED(BBAddrMapSecOrErr, Succeeded());
+    std::vector<PGOAnalysisMap> PGOAnalyses;
+    EXPECT_THAT_ERROR(
+        ElfOrErr->readBBAddrMap(TextSectionIndex, &PGOAnalyses).takeError(),
+        FailedWithMessage(ErrMsg));
+  };
+
+  // Check that we can retrieve the data in the normal case.
+  DoCheckSucceeds(CommonYamlString, /*TextSectionIndex=*/std::nullopt,
+                  AllBBAddrMaps, std::nullopt);
+  DoCheckSucceeds(CommonYamlString, /*TextSectionIndex=*/0, Section0BBAddrMaps,
+                  std::nullopt);
+  DoCheckSucceeds(CommonYamlString, /*TextSectionIndex=*/2, Section1BBAddrMaps,
+                  std::nullopt);
+  DoCheckSucceeds(CommonYamlString, /*TextSectionIndex=*/1, Section2BBAddrMaps,
+                  std::nullopt);
+
+  DoCheckSucceeds(CommonYamlString, /*TextSectionIndex=*/std::nullopt,
+                  AllBBAddrMaps, AllPGOAnalysisMaps);
+  DoCheckSucceeds(CommonYamlString, /*TextSectionIndex=*/0, Section0BBAddrMaps,
+                  Section0PGOAnalysisMaps);
+  DoCheckSucceeds(CommonYamlString, /*TextSectionIndex=*/2, Section1BBAddrMaps,
+                  Section1PGOAnalysisMaps);
+  DoCheckSucceeds(CommonYamlString, /*TextSectionIndex=*/1, Section2BBAddrMaps,
+                  Section2PGOAnalysisMaps);
+  // Check that when no bb-address-map section is found for a text section,
+  // we return an empty result.
+  DoCheckSucceeds(CommonYamlString, /*TextSectionIndex=*/3, {}, std::nullopt);
+  DoCheckSucceeds(CommonYamlString, /*TextSectionIndex=*/3, {},
+                  std::vector<PGOAnalysisMap>{});
+
+  // Check that we detect when a bb-addr-map section is linked to an invalid
+  // (not present) section.
+  SmallString<128> InvalidLinkedYamlString(CommonYamlString);
+  InvalidLinkedYamlString += R"(
+    Link: 10
+)";
+
+  DoCheckFails(InvalidLinkedYamlString, /*TextSectionIndex=*/4,
+               "unable to get the linked-to section for "
+               "SHT_LLVM_BB_ADDR_MAP section with index 4: invalid section "
+               "index: 10");
+  // Linked sections are not checked when we don't target a specific text
+  // section.
+  DoCheckSucceeds(InvalidLinkedYamlString, /*TextSectionIndex=*/std::nullopt,
+                  AllBBAddrMaps, std::nullopt);
+  DoCheckSucceeds(InvalidLinkedYamlString, /*TextSectionIndex=*/std::nullopt,
+                  AllBBAddrMaps, AllPGOAnalysisMaps);
+
+  // Check that we can detect when bb-address-map decoding fails.
+  SmallString<128> TruncatedYamlString(CommonYamlString);
+  TruncatedYamlString += R"(
+    ShSize: 0xa
+)";
+
+  DoCheckFails(TruncatedYamlString, /*TextSectionIndex=*/std::nullopt,
+               "unable to read SHT_LLVM_BB_ADDR_MAP section with index 4: "
+               "unable to decode LEB128 at offset 0x0000000a: malformed "
+               "uleb128, extends past end");
+  // Check that we can read the other section's bb-address-maps which are
+  // valid.
+  DoCheckSucceeds(TruncatedYamlString, /*TextSectionIndex=*/2,
+                  Section1BBAddrMaps, std::nullopt);
+  DoCheckSucceeds(TruncatedYamlString, /*TextSectionIndex=*/2,
+                  Section1BBAddrMaps, Section1PGOAnalysisMaps);
+}
+
 // Test for ObjectFile::getRelocatedSection: check that it returns a relocated
 // section for executable and relocatable files.
 TEST(ELFObjectFileTest, ExecutableWithRelocs) {
diff --git a/llvm/unittests/Object/ELFTypesTest.cpp b/llvm/unittests/Object/ELFTypesTest.cpp
index 2c9e8b7aebac..f09ab5e12438 100644
--- a/llvm/unittests/Object/ELFTypesTest.cpp
+++ b/llvm/unittests/Object/ELFTypesTest.cpp
@@ -94,3 +94,40 @@ TEST(ELFTypesTest, BBEntryMetadataInvalidEncodingTest) {
         FailedWithMessage(Errors[i]));
   }
 }
+
+static_assert(
+    std::is_same_v<decltype(PGOAnalysisMap::PGOBBEntry::SuccessorEntry::ID),
+                   decltype(BBAddrMap::BBEntry::ID)>,
+    "PGOAnalysisMap should use the same type for basic block ID as BBAddrMap");
+
+TEST(ELFTypesTest, PGOAnalysisMapFeaturesEncodingTest) {
+  const std::array<PGOAnalysisMap::Features, 7> Decoded = {
+      {{false, false, false},
+       {true, false, false},
+       {false, true, false},
+       {false, false, true},
+       {true, true, false},
+       {false, true, true},
+       {true, true, true}}};
+  const std::array<uint8_t, 7> Encoded = {
+      {0b000, 0b001, 0b010, 0b100, 0b011, 0b110, 0b111}};
+  for (const auto &[Feat, EncodedVal] : llvm::zip(Decoded, Encoded))
+    EXPECT_EQ(Feat.encode(), EncodedVal);
+  for (const auto &[Feat, EncodedVal] : llvm::zip(Decoded, Encoded)) {
+    Expected<PGOAnalysisMap::Features> FeatEnableOrError =
+        PGOAnalysisMap::Features::decode(EncodedVal);
+    ASSERT_THAT_EXPECTED(FeatEnableOrError, Succeeded());
+    EXPECT_EQ(*FeatEnableOrError, Feat);
+  }
+}
+
+TEST(ELFTypesTest, PGOAnalysisMapFeaturesInvalidEncodingTest) {
+  const std::array<std::string, 2> Errors = {
+      "invalid encoding for PGOAnalysisMap::Features: 0x8",
+      "invalid encoding for PGOAnalysisMap::Features: 0xff"};
+  const std::array<uint8_t, 2> Values = {{0b1000, 0b1111'1111}};
+  for (const auto &[Val, Error] : llvm::zip(Values, Errors)) {
+    EXPECT_THAT_ERROR(PGOAnalysisMap::Features::decode(Val).takeError(),
+                      FailedWithMessage(Error));
+  }
+}
-- 
GitLab


From 6d46337e13f943e331ae4c048e2456347fc83174 Mon Sep 17 00:00:00 2001
From: Orlando Cazalet-Hyams <orlando.hyams@sony.com>
Date: Tue, 12 Dec 2023 15:25:08 +0000
Subject: [PATCH 318/349] [RemoveDIs] Handle DPValues in replaceDbgDeclare
 (#73507)

The tests will become "live" once #74090 lands (see for more info).
---
 llvm/lib/Transforms/Utils/Local.cpp         | 21 ++++++++++++---------
 llvm/test/DebugInfo/Generic/block-asan.ll   |  1 +
 llvm/test/DebugInfo/X86/asan_debug_info.ll  |  4 ++++
 llvm/test/Transforms/SafeStack/ARM/debug.ll |  2 ++
 4 files changed, 19 insertions(+), 9 deletions(-)

diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp
index 63dcb6446164..19b787c10e8f 100644
--- a/llvm/lib/Transforms/Utils/Local.cpp
+++ b/llvm/lib/Transforms/Utils/Local.cpp
@@ -2131,19 +2131,22 @@ bool llvm::replaceDbgDeclare(Value *Address, Value *NewAddress,
                              DIBuilder &Builder, uint8_t DIExprFlags,
                              int Offset) {
   SmallVector<DbgDeclareInst *, 1> DbgDeclares;
-  findDbgDeclares(DbgDeclares, Address);
-  for (DbgVariableIntrinsic *DII : DbgDeclares) {
-    const DebugLoc &Loc = DII->getDebugLoc();
+  SmallVector<DPValue *, 1> DPValues;
+  findDbgDeclares(DbgDeclares, Address, &DPValues);
+
+  auto ReplaceOne = [&](auto *DII) {
     auto *DIVar = DII->getVariable();
     auto *DIExpr = DII->getExpression();
     assert(DIVar && "Missing variable");
     DIExpr = DIExpression::prepend(DIExpr, DIExprFlags, Offset);
-    // Insert llvm.dbg.declare immediately before DII, and remove old
-    // llvm.dbg.declare.
-    Builder.insertDeclare(NewAddress, DIVar, DIExpr, Loc, DII);
-    DII->eraseFromParent();
-  }
-  return !DbgDeclares.empty();
+    DII->setExpression(DIExpr);
+    DII->replaceVariableLocationOp(Address, NewAddress);
+  };
+
+  for_each(DbgDeclares, ReplaceOne);
+  for_each(DPValues, ReplaceOne);
+
+  return !DbgDeclares.empty() || !DPValues.empty();
 }
 
 static void updateOneDbgValueForAlloca(const DebugLoc &Loc,
diff --git a/llvm/test/DebugInfo/Generic/block-asan.ll b/llvm/test/DebugInfo/Generic/block-asan.ll
index db49289bd6ec..ceaf3f1d5e9a 100644
--- a/llvm/test/DebugInfo/Generic/block-asan.ll
+++ b/llvm/test/DebugInfo/Generic/block-asan.ll
@@ -1,4 +1,5 @@
 ; RUN: opt -S -passes=asan %s | FileCheck %s
+; RUN: opt --try-experimental-debuginfo-iterators -S -passes=asan %s | FileCheck %s
 
 ; The IR of this testcase is generated from the following C code:
 ; void bar (int);
diff --git a/llvm/test/DebugInfo/X86/asan_debug_info.ll b/llvm/test/DebugInfo/X86/asan_debug_info.ll
index 5e06b093c41d..4a4743ee0df5 100644
--- a/llvm/test/DebugInfo/X86/asan_debug_info.ll
+++ b/llvm/test/DebugInfo/X86/asan_debug_info.ll
@@ -2,6 +2,10 @@
 ; RUN:   llc -O0 -filetype=obj - -o - | \
 ; RUN:   llvm-dwarfdump - | FileCheck %s
 
+; RUN: opt --try-experimental-debuginfo-iterators < %s -passes=asan -asan-use-after-return=never -S | \
+; RUN:   llc -O0 -filetype=obj - -o - | \
+; RUN:   llvm-dwarfdump - | FileCheck %s
+
 ; For this test case, ASan used to produce IR which resulted in the following
 ; DWARF (at -O0):
 ;
diff --git a/llvm/test/Transforms/SafeStack/ARM/debug.ll b/llvm/test/Transforms/SafeStack/ARM/debug.ll
index c38ee62fa6aa..fbdb6361c2f6 100644
--- a/llvm/test/Transforms/SafeStack/ARM/debug.ll
+++ b/llvm/test/Transforms/SafeStack/ARM/debug.ll
@@ -1,5 +1,7 @@
 ; RUN: opt -safe-stack -safestack-use-pointer-address < %s -S | FileCheck %s
 ; RUN: opt -passes=safe-stack -safestack-use-pointer-address < %s -S | FileCheck %s
+; RUN: opt --try-experimental-debuginfo-iterators -passes=safe-stack -safestack-use-pointer-address < %s -S | FileCheck %s
+
 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
 target triple = "armv7-pc-linux-android"
 
-- 
GitLab


From c873f77e87a9ebd02f94d6b9d46e84d43e1ceb38 Mon Sep 17 00:00:00 2001
From: DonatNagyE <donat.nagy@ericsson.com>
Date: Tue, 12 Dec 2023 16:29:37 +0100
Subject: [PATCH 319/349] [analyzer] Move alpha checker EnumCastOutOfRange to
 optin (#67157)

The checker EnumCastOutOfRange verifies the (helpful, but not
standard-mandated) design rule that integer to enum casts should not
produce values that don't have a corresponding enumerator. As it was
improved and cleaned up by recent changes, this commit renames it from
`alpha.cplusplus.EnumCastOutOfRange` to `optin.core.EnumCastOutOfRange`
to reflect that it's no longer alpha quality.

As this checker handles a basic language feature (which is also present
in plain C), I moved it to a "core" subpackage within "optin".

In addition to the renaming, this commit cleans up the documentation in
`checkers.rst` and adds the new example code to a test file to ensure
that it's indeed producing the behavior claimend in the documentation.
---
 clang/docs/ReleaseNotes.rst                   |  3 +
 clang/docs/analyzer/checkers.rst              | 63 ++++++++++++++-----
 .../clang/StaticAnalyzer/Checkers/Checkers.td | 17 +++--
 .../Checkers/EnumCastOutOfRangeChecker.cpp    |  3 +
 clang/test/Analysis/enum-cast-out-of-range.c  |  2 +-
 .../test/Analysis/enum-cast-out-of-range.cpp  | 13 +++-
 clang/www/analyzer/alpha_checks.html          | 19 ------
 7 files changed, 78 insertions(+), 42 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index b62293a33bb9..066e4ac5b9e5 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -1073,6 +1073,9 @@ Static Analyzer
   `#65888 <https://github.com/llvm/llvm-project/pull/65888>`_, and
   `#65887 <https://github.com/llvm/llvm-project/pull/65887>`_
 
+- Move checker ``alpha.cplusplus.EnumCastOutOfRange`` out of the ``alpha``
+  package to ``optin.core.EnumCastOutOfRange``.
+
 .. _release-notes-sanitizers:
 
 Sanitizers
diff --git a/clang/docs/analyzer/checkers.rst b/clang/docs/analyzer/checkers.rst
index f7b48e64e324..81d40395067c 100644
--- a/clang/docs/analyzer/checkers.rst
+++ b/clang/docs/analyzer/checkers.rst
@@ -535,6 +535,52 @@ optin
 
 Checkers for portability, performance or coding style specific rules.
 
+.. _optin-core-EnumCastOutOfRange:
+
+optin.core.EnumCastOutOfRange (C, C++)
+""""""""""""""""""""""""""""""""""""""
+Check for integer to enumeration casts that would produce a value with no
+corresponding enumerator. This is not necessarily undefined behavior, but can
+lead to nasty surprises, so projects may decide to use a coding standard that
+disallows these "unusual" conversions.
+
+Note that no warnings are produced when the enum type (e.g. `std::byte`) has no
+enumerators at all.
+
+.. code-block:: cpp
+
+ enum WidgetKind { A=1, B, C, X=99 };
+
+ void foo() {
+   WidgetKind c = static_cast<WidgetKind>(3);  // OK
+   WidgetKind x = static_cast<WidgetKind>(99); // OK
+   WidgetKind d = static_cast<WidgetKind>(4);  // warn
+ }
+
+**Limitations**
+
+This checker does not accept the coding pattern where an enum type is used to
+store combinations of flag values:
+
+.. code-block:: cpp
+
+ enum AnimalFlags
+ {
+     HasClaws   = 1,
+     CanFly     = 2,
+     EatsFish   = 4,
+     Endangered = 8
+ };
+
+ AnimalFlags operator|(AnimalFlags a, AnimalFlags b)
+ {
+     return static_cast<AnimalFlags>(static_cast<int>(a) | static_cast<int>(b));
+ }
+
+ auto flags = HasClaws | CanFly;
+
+Projects that use this pattern should not enable this optin checker.
+
 .. _optin-cplusplus-UninitializedObject:
 
 optin.cplusplus.UninitializedObject (C++)
@@ -2113,23 +2159,6 @@ Reports destructions of polymorphic objects with a non-virtual destructor in the
              //       destructor
  }
 
-.. _alpha-cplusplus-EnumCastOutOfRange:
-
-alpha.cplusplus.EnumCastOutOfRange (C++)
-""""""""""""""""""""""""""""""""""""""""
-Check for integer to enumeration casts that could result in undefined values.
-
-.. code-block:: cpp
-
- enum TestEnum {
-   A = 0
- };
-
- void foo() {
-   TestEnum t = static_cast(-1);
-       // warn: the value provided to the cast expression is not in
-       //       the valid range of values for the enum
-
 .. _alpha-cplusplus-InvalidatedIterator:
 
 alpha.cplusplus.InvalidatedIterator (C++)
diff --git a/clang/include/clang/StaticAnalyzer/Checkers/Checkers.td b/clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
index 1d224786372e..e7774e5a9392 100644
--- a/clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
+++ b/clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
@@ -36,6 +36,7 @@ def CoreAlpha : Package<"core">, ParentPackage<Alpha>;
 // Note: OptIn is *not* intended for checkers that are too noisy to be on by
 // default. Such checkers belong in the alpha package.
 def OptIn : Package<"optin">;
+def CoreOptIn : Package<"core">, ParentPackage<OptIn>;
 
 // In the Portability package reside checkers for finding code that relies on
 // implementation-defined behavior. Such checks are wanted for cross-platform
@@ -439,6 +440,18 @@ def UndefinedNewArraySizeChecker : Checker<"NewArraySize">,
 
 } // end "core.uninitialized"
 
+//===----------------------------------------------------------------------===//
+// Optin checkers for core language features
+//===----------------------------------------------------------------------===//
+
+let ParentPackage = CoreOptIn in {
+
+def EnumCastOutOfRangeChecker : Checker<"EnumCastOutOfRange">,
+  HelpText<"Check integer to enumeration casts for out of range values">,
+  Documentation<HasDocumentation>;
+
+} // end "optin.core"
+
 //===----------------------------------------------------------------------===//
 // Unix API checkers.
 //===----------------------------------------------------------------------===//
@@ -774,10 +787,6 @@ def DeleteWithNonVirtualDtorChecker : Checker<"DeleteWithNonVirtualDtor">,
            "destructor in their base class">,
   Documentation<HasDocumentation>;
 
-def EnumCastOutOfRangeChecker : Checker<"EnumCastOutOfRange">,
-  HelpText<"Check integer to enumeration casts for out of range values">,
-  Documentation<HasDocumentation>;
-
 def IteratorModeling : Checker<"IteratorModeling">,
   HelpText<"Models iterators of C++ containers">,
   Dependencies<[ContainerModeling]>,
diff --git a/clang/lib/StaticAnalyzer/Checkers/EnumCastOutOfRangeChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/EnumCastOutOfRangeChecker.cpp
index 14433d06c2d0..7c51673422a0 100644
--- a/clang/lib/StaticAnalyzer/Checkers/EnumCastOutOfRangeChecker.cpp
+++ b/clang/lib/StaticAnalyzer/Checkers/EnumCastOutOfRangeChecker.cpp
@@ -159,6 +159,9 @@ void EnumCastOutOfRangeChecker::checkPreStmt(const CastExpr *CE,
   // Every initialization an enum with a fixed underlying type but without any
   // enumerators would produce a warning if we were to continue at this point.
   // The most notable example is std::byte in the C++17 standard library.
+  // TODO: Create heuristics to bail out when the enum type is intended to be
+  // used to store combinations of flag values (to mitigate the limitation
+  // described in the docs).
   if (DeclValues.size() == 0)
     return;
 
diff --git a/clang/test/Analysis/enum-cast-out-of-range.c b/clang/test/Analysis/enum-cast-out-of-range.c
index 4e5c9bb9ffde..a6eef92f418d 100644
--- a/clang/test/Analysis/enum-cast-out-of-range.c
+++ b/clang/test/Analysis/enum-cast-out-of-range.c
@@ -1,5 +1,5 @@
 // RUN: %clang_analyze_cc1 \
-// RUN:   -analyzer-checker=core,alpha.cplusplus.EnumCastOutOfRange \
+// RUN:   -analyzer-checker=core,optin.core.EnumCastOutOfRange \
 // RUN:   -analyzer-output text \
 // RUN:   -verify %s
 
diff --git a/clang/test/Analysis/enum-cast-out-of-range.cpp b/clang/test/Analysis/enum-cast-out-of-range.cpp
index 09835d420672..82086b730578 100644
--- a/clang/test/Analysis/enum-cast-out-of-range.cpp
+++ b/clang/test/Analysis/enum-cast-out-of-range.cpp
@@ -1,5 +1,5 @@
 // RUN: %clang_analyze_cc1 \
-// RUN:   -analyzer-checker=core,alpha.cplusplus.EnumCastOutOfRange \
+// RUN:   -analyzer-checker=core,optin.core.EnumCastOutOfRange \
 // RUN:   -std=c++11 -verify %s
 
 // expected-note@+1 + {{enum declared here}}
@@ -219,3 +219,14 @@ void empty_enums_init_with_zero_should_not_warn() {
 
   ignore_unused(eu, ef, efu);
 }
+
+//Test the example from checkers.rst:
+enum WidgetKind { A=1, B, C, X=99 }; // expected-note {{enum declared here}}
+
+void foo() {
+  WidgetKind c = static_cast<WidgetKind>(3);  // OK
+  WidgetKind x = static_cast<WidgetKind>(99); // OK
+  WidgetKind d = static_cast<WidgetKind>(4);  // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'WidgetKind'}}
+
+  ignore_unused(c, x, d);
+}
diff --git a/clang/www/analyzer/alpha_checks.html b/clang/www/analyzer/alpha_checks.html
index cff0284777bc..11ef7d405dd4 100644
--- a/clang/www/analyzer/alpha_checks.html
+++ b/clang/www/analyzer/alpha_checks.html
@@ -370,25 +370,6 @@ void sink(NonVirtual *x) {
 }
 </pre></div></div></td></tr>
 
-<tr><td><a id="alpha.cplusplus.EnumCastOutOfRange"><div class="namedescr expandable"><span class="name">
-alpha.cplusplus.EnumCastOutOfRange</span><span class="lang">
-(C++)</span><div class="descr">
-  Check for integer to enumeration casts that could result in undefined values.
-</div></div></a></td>
-  <td><div class="exampleContainer expandable">
-    <div class="example"><pre>
-enum TestEnum {
-  A = 0
-};
-
-void foo() {
-  TestEnum t = static_cast<TestEnum>(-1);
-      // warn: the value provided to the cast expression is not in
-               the valid range of values for the enum
-}
-</pre></div></div></td></tr>
-
-
 <tr><td><a id="alpha.cplusplus.InvalidatedIterator"><div class="namedescr expandable"><span class="name">
 alpha.cplusplus.InvalidatedIterator</span><span class="lang">
 (C++)</span><div class="descr">
-- 
GitLab


From a8f3860bcb644d724275f51e7db7b291c7a3f4df Mon Sep 17 00:00:00 2001
From: Rafael Ubal <rubal@mathworks.com>
Date: Tue, 12 Dec 2023 10:36:52 -0500
Subject: [PATCH 320/349] [mlir][tensor] Fix bug in
 `tensor.extract(tensor.from_elements)` folder (#75109)

The folder for `tensor.extract` is not operating correctly when it is
consuming the result of a `tensor.from_elements` operation.

The existing unit test named `@extract_from_tensor.from_elements_3d` in
`mlir/test/Dialect/Tensor/canonicalize.mlir` seems an attempt to stress
this code. However, this unit tests creates a `tensor.from_elements` op
exclusively from constants, which gets folded away into a single
constant tensor. Therefore, the buggy code was never executed in unit
tests.

I have added a new unit test named
`@extract_from_tensor.from_elements_variable_3d` that makes sure the
`tensor.from_elements` op is not folded away by having its input
operands come directly from function arguments. The original folder code
would have made this test fail.

This bug was notably affecting the lowering of the `tosa.pad` op in the
`tosa-to-tensor` pass, where the generated code is likely to contain a
`tensor.from_elements` + `tensor.extract` op sequence.
---
 mlir/lib/Dialect/Tensor/IR/TensorOps.cpp   |  3 +-
 mlir/test/Dialect/Tensor/canonicalize.mlir | 44 ++++++++++++++++++++++
 2 files changed, 45 insertions(+), 2 deletions(-)

diff --git a/mlir/lib/Dialect/Tensor/IR/TensorOps.cpp b/mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
index ec4c41c0000a..a257e5f4d9dc 100644
--- a/mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
+++ b/mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
@@ -1116,9 +1116,8 @@ OpFoldResult ExtractOp::fold(FoldAdaptor adaptor) {
     int flatIndex = 0;
     int stride = 1;
     for (int i = rank - 1; i >= 0; --i) {
-      if (i < rank - 1)
-        stride *= tensorType.getDimSize(i);
       flatIndex += indices[i] * stride;
+      stride *= tensorType.getDimSize(i);
     }
     // Prevent out of bounds accesses. This can happen in invalid code that
     // will never execute.
diff --git a/mlir/test/Dialect/Tensor/canonicalize.mlir b/mlir/test/Dialect/Tensor/canonicalize.mlir
index 7d7d221c1e8e..8542fc956741 100644
--- a/mlir/test/Dialect/Tensor/canonicalize.mlir
+++ b/mlir/test/Dialect/Tensor/canonicalize.mlir
@@ -242,6 +242,50 @@ func.func @extract_from_tensor.from_elements_3d()
 
 // -----
 
+// CHECK-LABEL: func @extract_from_tensor.from_elements_variable_3d
+// CHECK-SAME: %[[ARG_0:[a-zA-Z0-9_]+]]: f32
+// CHECK-SAME: %[[ARG_1:[a-zA-Z0-9_]+]]: f32
+// CHECK-SAME: %[[ARG_2:[a-zA-Z0-9_]+]]: f32
+// CHECK-SAME: %[[ARG_3:[a-zA-Z0-9_]+]]: f32
+// CHECK-SAME: %[[ARG_4:[a-zA-Z0-9_]+]]: f32
+// CHECK-SAME: %[[ARG_5:[a-zA-Z0-9_]+]]: f32
+// CHECK-SAME: %[[ARG_6:[a-zA-Z0-9_]+]]: f32
+// CHECK-SAME: %[[ARG_7:[a-zA-Z0-9_]+]]: f32
+// CHECK-SAME: %[[ARG_8:[a-zA-Z0-9_]+]]: f32
+// CHECK-SAME: %[[ARG_9:[a-zA-Z0-9_]+]]: f32
+// CHECK-SAME: %[[ARG_10:[a-zA-Z0-9_]+]]: f32
+// CHECK-SAME: %[[ARG_11:[a-zA-Z0-9_]+]]: f32
+func.func @extract_from_tensor.from_elements_variable_3d(
+    %f0: f32, %f1: f32, %f2: f32, %f3: f32, %f4: f32, %f5: f32,
+    %f6: f32, %f7: f32, %f8: f32, %f9: f32, %f10: f32, %f11: f32)
+    -> (f32, f32, f32, f32, f32, f32, f32, f32, f32, f32, f32, f32) {
+
+  %tensor = tensor.from_elements %f0,%f1,%f2,%f3,%f4,%f5,%f6,%f7,%f8,%f9,%f10,%f11
+         : tensor<3x2x2xf32>
+  %c0 = arith.constant 0 : index
+  %c1 = arith.constant 1 : index
+  %c2 = arith.constant 2 : index
+
+  %r0 = tensor.extract %tensor[%c0, %c0, %c0] : tensor<3x2x2xf32>
+  %r1 = tensor.extract %tensor[%c0, %c0, %c1] : tensor<3x2x2xf32>
+  %r2 = tensor.extract %tensor[%c0, %c1, %c0] : tensor<3x2x2xf32>
+  %r3 = tensor.extract %tensor[%c0, %c1, %c1] : tensor<3x2x2xf32>
+  %r4 = tensor.extract %tensor[%c1, %c0, %c0] : tensor<3x2x2xf32>
+  %r5 = tensor.extract %tensor[%c1, %c0, %c1] : tensor<3x2x2xf32>
+  %r6 = tensor.extract %tensor[%c1, %c1, %c0] : tensor<3x2x2xf32>
+  %r7 = tensor.extract %tensor[%c1, %c1, %c1] : tensor<3x2x2xf32>
+  %r8 = tensor.extract %tensor[%c2, %c0, %c0] : tensor<3x2x2xf32>
+  %r9 = tensor.extract %tensor[%c2, %c0, %c1] : tensor<3x2x2xf32>
+  %r10 = tensor.extract %tensor[%c2, %c1, %c0] : tensor<3x2x2xf32>
+  %r11 = tensor.extract %tensor[%c2, %c1, %c1] : tensor<3x2x2xf32>
+  return %r0,%r1,%r2,%r3,%r4,%r5,%r6,%r7,%r8,%r9,%r10,%r11
+         : f32,f32,f32,f32,f32,f32,f32,f32,f32,f32,f32,f32
+}
+// CHECK: return %[[ARG_0]], %[[ARG_1]], %[[ARG_2]], %[[ARG_3]], %[[ARG_4]], %[[ARG_5]],
+// CHECK-SAME: %[[ARG_6]], %[[ARG_7]], %[[ARG_8]], %[[ARG_9]], %[[ARG_10]], %[[ARG_11]]
+
+// -----
+
 // CHECK-LABEL: func.func @extract_from_elements_complex_i() -> tensor<3xcomplex<i32>> {
 // CHECK-NEXT:  %cst = arith.constant dense<[(1,2), (3,2), (1,2)]> : tensor<3xcomplex<i32>>
 // CHECK-NEXT:  return %cst : tensor<3xcomplex<i32>>
-- 
GitLab


From 32532c2bbedc6e15eb3eae65cb6049e196cef9ad Mon Sep 17 00:00:00 2001
From: Tuan Chuong Goh <chuong.goh@arm.com>
Date: Fri, 1 Dec 2023 14:33:39 +0000
Subject: [PATCH 321/349] [AArch64][GlobalISel] Test Pre-Commit for Look into
 array's element

---
 .../GlobalISel/regbankselect-fp-loads.mir     | 321 ++++++++++++++++--
 1 file changed, 295 insertions(+), 26 deletions(-)

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-fp-loads.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-fp-loads.mir
index cfa0ba90c587..a28056ddd0ac 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-fp-loads.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-fp-loads.mir
@@ -10,6 +10,23 @@
   define float @fp_load_phi() { ret float undef }
   define i32 @int_load_phi() { ret i32 undef }
 
+
+  @array_double = dso_local global [32000 x double] zeroinitializer, align 8
+  @struct_array_double = dso_local global { [32000 x double] } zeroinitializer, align 8
+  @struct_struct_array_double = dso_local global {{ [32000 x double] }} zeroinitializer, align 8
+
+  define float @array_load_double() { ret float undef }
+  define float @struct_array_load_double() { ret float undef }
+  define float @struct_struct_array_load_double() { ret float undef }
+
+  @array_int = dso_local global [32000 x i32] zeroinitializer, align 8
+  @struct_array_int = dso_local global { [32000 x i32] } zeroinitializer, align 8
+  @struct_struct_array_int = dso_local global {{ [32000 x i32] }} zeroinitializer, align 8
+
+  define i32 @array_load_int() { ret i32 undef }
+  define i32 @struct_array_load_int() { ret i32 undef }
+  define i32 @struct_struct_array_load_int() { ret i32 undef }
+
 ...
 ---
 name:            fp_load_phi
@@ -19,20 +36,22 @@ tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: fp_load_phi
   ; CHECK: bb.0:
-  ; CHECK:   successors: %bb.1(0x80000000)
-  ; CHECK:   liveins: $w0
-  ; CHECK:   [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
-  ; CHECK:   [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var_fp
-  ; CHECK:   %fp_load:fpr(s32) = G_LOAD [[GV]](p0) :: (load (s32) from @var_fp)
-  ; CHECK: bb.1:
-  ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
-  ; CHECK:   [[PHI:%[0-9]+]]:fpr(s32) = PHI %fp_load(s32), %bb.0, [[PHI]](s32), %bb.1
-  ; CHECK:   G_BRCOND [[COPY]](s32), %bb.1
-  ; CHECK: bb.2:
-  ; CHECK:   $s0 = COPY [[PHI]](s32)
-  ; CHECK:   RET_ReallyLR implicit $s0
-  ; Here we're checking that the load is assigned an FPR bank, since it's
-  ; loading from an fp type in the IR.
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT:   liveins: $w0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
+  ; CHECK-NEXT:   [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var_fp
+  ; CHECK-NEXT:   %fp_load:fpr(s32) = G_LOAD [[GV]](p0) :: (load (s32) from @var_fp)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:fpr(s32) = PHI %fp_load(s32), %bb.0, [[PHI]](s32), %bb.1
+  ; CHECK-NEXT:   G_BRCOND [[COPY]](s32), %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
+  ; CHECK-NEXT:   $s0 = COPY [[PHI]](s32)
+  ; CHECK-NEXT:   RET_ReallyLR implicit $s0
   bb.0:
     liveins: $w0
     successors: %bb.1
@@ -58,18 +77,22 @@ tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: int_load_phi
   ; CHECK: bb.0:
-  ; CHECK:   successors: %bb.1(0x80000000)
-  ; CHECK:   liveins: $w0
-  ; CHECK:   [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
-  ; CHECK:   [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var_fp
-  ; CHECK:   %fp_load:gpr(s32) = G_LOAD [[GV]](p0) :: (load (s32) from @var_int)
-  ; CHECK: bb.1:
-  ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
-  ; CHECK:   [[PHI:%[0-9]+]]:gpr(s32) = PHI %fp_load(s32), %bb.0, [[PHI]](s32), %bb.1
-  ; CHECK:   G_BRCOND [[COPY]](s32), %bb.1
-  ; CHECK: bb.2:
-  ; CHECK:   $s0 = COPY [[PHI]](s32)
-  ; CHECK:   RET_ReallyLR implicit $s0
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT:   liveins: $w0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
+  ; CHECK-NEXT:   [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var_fp
+  ; CHECK-NEXT:   %fp_load:gpr(s32) = G_LOAD [[GV]](p0) :: (load (s32) from @var_int)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr(s32) = PHI %fp_load(s32), %bb.0, [[PHI]](s32), %bb.1
+  ; CHECK-NEXT:   G_BRCOND [[COPY]](s32), %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
+  ; CHECK-NEXT:   $s0 = COPY [[PHI]](s32)
+  ; CHECK-NEXT:   RET_ReallyLR implicit $s0
   bb.0:
     liveins: $w0
     successors: %bb.1
@@ -86,3 +109,249 @@ body:             |
     $s0 = COPY %2
     RET_ReallyLR implicit $s0
 ...
+
+---
+name:            array_load_double
+legalized:       true
+regBankSelected: false
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: array_load_double
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT:   liveins: $w0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
+  ; CHECK-NEXT:   [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @array_double
+  ; CHECK-NEXT:   %fp_load:gpr(s64) = G_LOAD [[GV]](p0) :: (dereferenceable load (s64) from @array_double)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr(s32) = PHI %fp_load(s64), %bb.0, [[PHI]](s32), %bb.1
+  ; CHECK-NEXT:   G_BRCOND [[COPY]](s32), %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
+  ; CHECK-NEXT:   $s0 = COPY [[PHI]](s32)
+  ; CHECK-NEXT:   RET_ReallyLR implicit $s0
+  bb.0:
+    liveins: $w0
+    successors: %bb.1
+    %0:_(s32) = COPY $w0
+    %1:_(p0) = G_GLOBAL_VALUE @array_double
+    %fp_load:_(s64) = G_LOAD %1(p0) :: (dereferenceable load (s64) from @array_double)
+
+  bb.1:
+    successors: %bb.1, %bb.2
+    %2:_(s32) = PHI %fp_load, %bb.0, %2, %bb.1
+    G_BRCOND %0, %bb.1
+
+  bb.2:
+    $s0 = COPY %2
+    RET_ReallyLR implicit $s0
+...
+
+---
+name:            struct_array_load_double
+legalized:       true
+regBankSelected: false
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: struct_array_load_double
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT:   liveins: $w0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
+  ; CHECK-NEXT:   [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @struct_array_double
+  ; CHECK-NEXT:   %fp_load:gpr(s64) = G_LOAD [[GV]](p0) :: (dereferenceable load (s64) from @struct_array_double)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr(s32) = PHI %fp_load(s64), %bb.0, [[PHI]](s32), %bb.1
+  ; CHECK-NEXT:   G_BRCOND [[COPY]](s32), %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
+  ; CHECK-NEXT:   $s0 = COPY [[PHI]](s32)
+  ; CHECK-NEXT:   RET_ReallyLR implicit $s0
+  bb.0:
+    liveins: $w0
+    successors: %bb.1
+    %0:_(s32) = COPY $w0
+    %1:_(p0) = G_GLOBAL_VALUE @struct_array_double
+    %fp_load:_(s64) = G_LOAD %1(p0) :: (dereferenceable load (s64) from @struct_array_double)
+
+  bb.1:
+    successors: %bb.1, %bb.2
+    %2:_(s32) = PHI %fp_load, %bb.0, %2, %bb.1
+    G_BRCOND %0, %bb.1
+
+  bb.2:
+    $s0 = COPY %2
+    RET_ReallyLR implicit $s0
+...
+
+---
+name:            struct_struct_array_load_double
+legalized:       true
+regBankSelected: false
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: struct_struct_array_load_double
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT:   liveins: $w0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
+  ; CHECK-NEXT:   [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @struct_struct_array_double
+  ; CHECK-NEXT:   %fp_load:gpr(s64) = G_LOAD [[GV]](p0) :: (dereferenceable load (s64) from @struct_struct_array_double)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr(s32) = PHI %fp_load(s64), %bb.0, [[PHI]](s32), %bb.1
+  ; CHECK-NEXT:   G_BRCOND [[COPY]](s32), %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
+  ; CHECK-NEXT:   $s0 = COPY [[PHI]](s32)
+  ; CHECK-NEXT:   RET_ReallyLR implicit $s0
+  bb.0:
+    liveins: $w0
+    successors: %bb.1
+    %0:_(s32) = COPY $w0
+    %1:_(p0) = G_GLOBAL_VALUE @struct_struct_array_double
+    %fp_load:_(s64) = G_LOAD %1(p0) :: (dereferenceable load (s64) from @struct_struct_array_double)
+
+  bb.1:
+    successors: %bb.1, %bb.2
+    %2:_(s32) = PHI %fp_load, %bb.0, %2, %bb.1
+    G_BRCOND %0, %bb.1
+
+  bb.2:
+    $s0 = COPY %2
+    RET_ReallyLR implicit $s0
+...
+
+---
+name:            array_load_int
+legalized:       true
+regBankSelected: false
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: array_load_int
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT:   liveins: $w0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
+  ; CHECK-NEXT:   [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @array_int
+  ; CHECK-NEXT:   %fp_load:gpr(s64) = G_LOAD [[GV]](p0) :: (dereferenceable load (s64) from @array_int)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr(s32) = PHI %fp_load(s64), %bb.0, [[PHI]](s32), %bb.1
+  ; CHECK-NEXT:   G_BRCOND [[COPY]](s32), %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
+  ; CHECK-NEXT:   $s0 = COPY [[PHI]](s32)
+  ; CHECK-NEXT:   RET_ReallyLR implicit $s0
+  bb.0:
+    liveins: $w0
+    successors: %bb.1
+    %0:_(s32) = COPY $w0
+    %1:_(p0) = G_GLOBAL_VALUE @array_int
+    %fp_load:_(s64) = G_LOAD %1(p0) :: (dereferenceable load (s64) from @array_int)
+
+  bb.1:
+    successors: %bb.1, %bb.2
+    %2:_(s32) = PHI %fp_load, %bb.0, %2, %bb.1
+    G_BRCOND %0, %bb.1
+
+  bb.2:
+    $s0 = COPY %2
+    RET_ReallyLR implicit $s0
+...
+
+---
+name:            struct_array_load_int
+legalized:       true
+regBankSelected: false
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: struct_array_load_int
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT:   liveins: $w0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
+  ; CHECK-NEXT:   [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @struct_array_int
+  ; CHECK-NEXT:   %fp_load:gpr(s64) = G_LOAD [[GV]](p0) :: (dereferenceable load (s64) from @struct_array_int)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr(s32) = PHI %fp_load(s64), %bb.0, [[PHI]](s32), %bb.1
+  ; CHECK-NEXT:   G_BRCOND [[COPY]](s32), %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
+  ; CHECK-NEXT:   $s0 = COPY [[PHI]](s32)
+  ; CHECK-NEXT:   RET_ReallyLR implicit $s0
+  bb.0:
+    liveins: $w0
+    successors: %bb.1
+    %0:_(s32) = COPY $w0
+    %1:_(p0) = G_GLOBAL_VALUE @struct_array_int
+    %fp_load:_(s64) = G_LOAD %1(p0) :: (dereferenceable load (s64) from @struct_array_int)
+
+  bb.1:
+    successors: %bb.1, %bb.2
+    %2:_(s32) = PHI %fp_load, %bb.0, %2, %bb.1
+    G_BRCOND %0, %bb.1
+
+  bb.2:
+    $s0 = COPY %2
+    RET_ReallyLR implicit $s0
+...
+
+---
+name:            struct_struct_array_load_int
+legalized:       true
+regBankSelected: false
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: struct_struct_array_load_int
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT:   liveins: $w0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
+  ; CHECK-NEXT:   [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @struct_struct_array_int
+  ; CHECK-NEXT:   %fp_load:gpr(s64) = G_LOAD [[GV]](p0) :: (dereferenceable load (s64) from @struct_struct_array_int)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr(s32) = PHI %fp_load(s64), %bb.0, [[PHI]](s32), %bb.1
+  ; CHECK-NEXT:   G_BRCOND [[COPY]](s32), %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
+  ; CHECK-NEXT:   $s0 = COPY [[PHI]](s32)
+  ; CHECK-NEXT:   RET_ReallyLR implicit $s0
+  bb.0:
+    liveins: $w0
+    successors: %bb.1
+    %0:_(s32) = COPY $w0
+    %1:_(p0) = G_GLOBAL_VALUE @struct_struct_array_int
+    %fp_load:_(s64) = G_LOAD %1(p0) :: (dereferenceable load (s64) from @struct_struct_array_int)
+
+  bb.1:
+    successors: %bb.1, %bb.2
+    %2:_(s32) = PHI %fp_load, %bb.0, %2, %bb.1
+    G_BRCOND %0, %bb.1
+
+  bb.2:
+    $s0 = COPY %2
+    RET_ReallyLR implicit $s0
+...
-- 
GitLab


From 3d4255787246b676f65e22b63b916b2bf679c9c0 Mon Sep 17 00:00:00 2001
From: Orlando Cazalet-Hyams <orlando.hyams@sony.com>
Date: Tue, 12 Dec 2023 15:49:24 +0000
Subject: [PATCH 322/349] [RemoveDI] Handle DPValues in SROA (#74089)

Handle dbg.declares in SROA using DPValues.

In order to reduce duplication, the migrate-debug-info loop has been changed
to a generic lambda with some helper function overloads, which is called
for dbg.declares, dbg.assigns, and DPValues alike.

The tests will become "live" once #74090 lands (see for more info).
---
 llvm/lib/Transforms/Scalar/SROA.cpp           | 86 ++++++++++++-------
 llvm/test/DebugInfo/ARM/sroa-complex.ll       |  1 +
 llvm/test/DebugInfo/Generic/sroa-larger.ll    |  1 +
 llvm/test/DebugInfo/Generic/sroa-samesize.ll  |  1 +
 .../test/DebugInfo/X86/sroa-after-inlining.ll |  1 +
 llvm/test/DebugInfo/X86/sroasplit-1.ll        |  1 +
 llvm/test/DebugInfo/X86/sroasplit-2.ll        |  1 +
 llvm/test/DebugInfo/X86/sroasplit-3.ll        |  2 +
 llvm/test/DebugInfo/X86/sroasplit-4.ll        |  1 +
 llvm/test/DebugInfo/X86/sroasplit-5.ll        |  2 +
 .../DebugInfo/X86/sroasplit-dbg-declare.ll    |  1 +
 llvm/test/DebugInfo/salvage-overflow.ll       |  1 +
 llvm/test/Transforms/Util/dbg-user-of-aext.ll |  1 +
 13 files changed, 67 insertions(+), 33 deletions(-)

diff --git a/llvm/lib/Transforms/Scalar/SROA.cpp b/llvm/lib/Transforms/Scalar/SROA.cpp
index 9c72cb67e4d6..b0285dd7de0a 100644
--- a/llvm/lib/Transforms/Scalar/SROA.cpp
+++ b/llvm/lib/Transforms/Scalar/SROA.cpp
@@ -4838,6 +4838,35 @@ AllocaInst *SROA::rewritePartition(AllocaInst &AI, AllocaSlices &AS,
   return NewAI;
 }
 
+static void insertNewDbgInst(DIBuilder &DIB, DbgDeclareInst *Orig,
+                             AllocaInst *NewAddr, DIExpression *NewFragmentExpr,
+                             Instruction *BeforeInst) {
+  DIB.insertDeclare(NewAddr, Orig->getVariable(), NewFragmentExpr,
+                    Orig->getDebugLoc(), BeforeInst);
+}
+static void insertNewDbgInst(DIBuilder &DIB, DbgAssignIntrinsic *Orig,
+                             AllocaInst *NewAddr, DIExpression *NewFragmentExpr,
+                             Instruction *BeforeInst) {
+  (void)BeforeInst;
+  if (!NewAddr->hasMetadata(LLVMContext::MD_DIAssignID)) {
+    NewAddr->setMetadata(LLVMContext::MD_DIAssignID,
+                         DIAssignID::getDistinct(NewAddr->getContext()));
+  }
+  auto *NewAssign = DIB.insertDbgAssign(
+      NewAddr, Orig->getValue(), Orig->getVariable(), NewFragmentExpr, NewAddr,
+      Orig->getAddressExpression(), Orig->getDebugLoc());
+  LLVM_DEBUG(dbgs() << "Created new assign intrinsic: " << *NewAssign << "\n");
+}
+static void insertNewDbgInst(DIBuilder &DIB, DPValue *Orig, AllocaInst *NewAddr,
+                             DIExpression *NewFragmentExpr,
+                             Instruction *BeforeInst) {
+  (void)DIB;
+  DPValue *New = new DPValue(ValueAsMetadata::get(NewAddr), Orig->getVariable(),
+                             NewFragmentExpr, Orig->getDebugLoc(),
+                             DPValue::LocationType::Declare);
+  BeforeInst->getParent()->insertDPValueBefore(New, BeforeInst->getIterator());
+}
+
 /// Walks the slices of an alloca and form partitions based on them,
 /// rewriting each of their uses.
 bool SROA::splitAlloca(AllocaInst &AI, AllocaSlices &AS) {
@@ -4939,15 +4968,7 @@ bool SROA::splitAlloca(AllocaInst &AI, AllocaSlices &AS) {
 
   // Migrate debug information from the old alloca to the new alloca(s)
   // and the individual partitions.
-  TinyPtrVector<DbgVariableIntrinsic *> DbgVariables;
-  SmallVector<DbgDeclareInst *, 1> DbgDeclares;
-  findDbgDeclares(DbgDeclares, &AI);
-  for (auto *DbgDeclare : DbgDeclares)
-    DbgVariables.push_back(DbgDeclare);
-  for (auto *DbgAssign : at::getAssignmentMarkers(&AI))
-    DbgVariables.push_back(DbgAssign);
-
-  for (DbgVariableIntrinsic *DbgVariable : DbgVariables) {
+  auto MigrateOne = [&](auto *DbgVariable) {
     auto *Expr = DbgVariable->getExpression();
     DIBuilder DIB(*AI.getModule(), /*AllowUnresolved*/ false);
     uint64_t AllocaSize =
@@ -5001,37 +5022,33 @@ bool SROA::splitAlloca(AllocaInst &AI, AllocaSlices &AS) {
       // Remove any existing intrinsics on the new alloca describing
       // the variable fragment.
       SmallVector<DbgDeclareInst *, 1> FragDbgDeclares;
-      findDbgDeclares(FragDbgDeclares, Fragment.Alloca);
-      for (DbgDeclareInst *OldDII : FragDbgDeclares) {
-        auto SameVariableFragment = [](const DbgVariableIntrinsic *LHS,
-                                       const DbgVariableIntrinsic *RHS) {
+      SmallVector<DPValue *, 1> FragDPVs;
+      findDbgDeclares(FragDbgDeclares, Fragment.Alloca, &FragDPVs);
+      auto RemoveOne = [DbgVariable](auto *OldDII) {
+        auto SameVariableFragment = [](const auto *LHS, const auto *RHS) {
           return LHS->getVariable() == RHS->getVariable() &&
                  LHS->getDebugLoc()->getInlinedAt() ==
                      RHS->getDebugLoc()->getInlinedAt();
         };
         if (SameVariableFragment(OldDII, DbgVariable))
           OldDII->eraseFromParent();
-      }
+      };
+      for_each(FragDbgDeclares, RemoveOne);
+      for_each(FragDPVs, RemoveOne);
 
-      if (auto *DbgAssign = dyn_cast<DbgAssignIntrinsic>(DbgVariable)) {
-        if (!Fragment.Alloca->hasMetadata(LLVMContext::MD_DIAssignID)) {
-          Fragment.Alloca->setMetadata(
-              LLVMContext::MD_DIAssignID,
-              DIAssignID::getDistinct(AI.getContext()));
-        }
-        auto *NewAssign = DIB.insertDbgAssign(
-            Fragment.Alloca, DbgAssign->getValue(), DbgAssign->getVariable(),
-            FragmentExpr, Fragment.Alloca, DbgAssign->getAddressExpression(),
-            DbgAssign->getDebugLoc());
-        NewAssign->setDebugLoc(DbgAssign->getDebugLoc());
-        LLVM_DEBUG(dbgs() << "Created new assign intrinsic: " << *NewAssign
-                          << "\n");
-      } else {
-        DIB.insertDeclare(Fragment.Alloca, DbgVariable->getVariable(),
-                          FragmentExpr, DbgVariable->getDebugLoc(), &AI);
-      }
+      insertNewDbgInst(DIB, DbgVariable, Fragment.Alloca, FragmentExpr, &AI);
     }
-  }
+  };
+
+  // Migrate debug information from the old alloca to the new alloca(s)
+  // and the individual partitions.
+  SmallVector<DbgDeclareInst *, 1> DbgDeclares;
+  SmallVector<DPValue *, 1> DPValues;
+  findDbgDeclares(DbgDeclares, &AI, &DPValues);
+  for_each(DbgDeclares, MigrateOne);
+  for_each(DPValues, MigrateOne);
+  for_each(at::getAssignmentMarkers(&AI), MigrateOne);
+
   return Changed;
 }
 
@@ -5153,9 +5170,12 @@ bool SROA::deleteDeadInstructions(
     if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) {
       DeletedAllocas.insert(AI);
       SmallVector<DbgDeclareInst *, 1> DbgDeclares;
-      findDbgDeclares(DbgDeclares, AI);
+      SmallVector<DPValue *, 1> DPValues;
+      findDbgDeclares(DbgDeclares, AI, &DPValues);
       for (DbgDeclareInst *OldDII : DbgDeclares)
         OldDII->eraseFromParent();
+      for (DPValue *OldDII : DPValues)
+        OldDII->eraseFromParent();
     }
 
     at::deleteAssignmentMarkers(I);
diff --git a/llvm/test/DebugInfo/ARM/sroa-complex.ll b/llvm/test/DebugInfo/ARM/sroa-complex.ll
index 7e81e488d59e..f85e4cd29ba9 100644
--- a/llvm/test/DebugInfo/ARM/sroa-complex.ll
+++ b/llvm/test/DebugInfo/ARM/sroa-complex.ll
@@ -1,4 +1,5 @@
 ; RUN: opt -passes='sroa' -S -o - %s | FileCheck %s
+; RUN: opt --try-experimental-debuginfo-iterators -passes='sroa' -S -o - %s | FileCheck %s
 target datalayout = "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
 target triple = "thumbv7-apple-unknown-macho"
 
diff --git a/llvm/test/DebugInfo/Generic/sroa-larger.ll b/llvm/test/DebugInfo/Generic/sroa-larger.ll
index 55e82034bea9..2121b57c535b 100644
--- a/llvm/test/DebugInfo/Generic/sroa-larger.ll
+++ b/llvm/test/DebugInfo/Generic/sroa-larger.ll
@@ -1,4 +1,5 @@
 ; RUN: opt -passes='sroa' -S -o - %s | FileCheck %s
+; RUN: opt --try-experimental-debuginfo-iterators -passes='sroa' -S -o - %s | FileCheck %s
 ; Generated from clang -c  -O2 -g -target x86_64-pc-windows-msvc
 ; struct A {
 ;   int _Myval2;
diff --git a/llvm/test/DebugInfo/Generic/sroa-samesize.ll b/llvm/test/DebugInfo/Generic/sroa-samesize.ll
index 0527f6fe6c72..1e70bad225c7 100644
--- a/llvm/test/DebugInfo/Generic/sroa-samesize.ll
+++ b/llvm/test/DebugInfo/Generic/sroa-samesize.ll
@@ -1,4 +1,5 @@
 ; RUN: opt -passes='sroa' -S -o - %s | FileCheck %s
+; RUN: opt --try-experimental-debuginfo-iterators -passes='sroa' -S -o - %s | FileCheck %s
 ; Generated from clang -c  -O2 -g -target x86_64-pc-windows-msvc
 ; struct A { double x1[]; };
 ; struct x2 {
diff --git a/llvm/test/DebugInfo/X86/sroa-after-inlining.ll b/llvm/test/DebugInfo/X86/sroa-after-inlining.ll
index c648547f4a90..d8f2c9a3ade0 100644
--- a/llvm/test/DebugInfo/X86/sroa-after-inlining.ll
+++ b/llvm/test/DebugInfo/X86/sroa-after-inlining.ll
@@ -1,4 +1,5 @@
 ; RUN: opt %s -passes='cgscc(function(sroa,instcombine),inline),function(instcombine,sroa),verify' -S -o - | FileCheck %s
+; RUN: opt --try-experimental-debuginfo-iterators %s -passes='cgscc(function(sroa,instcombine),inline),function(instcombine,sroa),verify' -S -o - | FileCheck %s
 ;
 ; This test checks that SROA pass processes debug info correctly if applied twice.
 ; Specifically, after SROA works first time, instcombine converts dbg.declare
diff --git a/llvm/test/DebugInfo/X86/sroasplit-1.ll b/llvm/test/DebugInfo/X86/sroasplit-1.ll
index 5ac5c828b11e..426f522410c7 100644
--- a/llvm/test/DebugInfo/X86/sroasplit-1.ll
+++ b/llvm/test/DebugInfo/X86/sroasplit-1.ll
@@ -1,4 +1,5 @@
 ; RUN: opt %s -passes='sroa,verify' -S -o - | FileCheck %s
+; RUN: opt --try-experimental-debuginfo-iterators %s -passes='sroa,verify' -S -o - | FileCheck %s
 ;
 ; Test that we can partial emit debug info for aggregates repeatedly
 ; split up by SROA.
diff --git a/llvm/test/DebugInfo/X86/sroasplit-2.ll b/llvm/test/DebugInfo/X86/sroasplit-2.ll
index d002bcf6a1b6..ddafc6b57f75 100644
--- a/llvm/test/DebugInfo/X86/sroasplit-2.ll
+++ b/llvm/test/DebugInfo/X86/sroasplit-2.ll
@@ -1,4 +1,5 @@
 ; RUN: opt %s -passes='sroa,verify' -S -o - | FileCheck %s
+; RUN: opt --try-experimental-debuginfo-iterators %s -passes='sroa,verify' -S -o - | FileCheck %s
 ;
 ; Test that we can partial emit debug info for aggregates repeatedly
 ; split up by SROA.
diff --git a/llvm/test/DebugInfo/X86/sroasplit-3.ll b/llvm/test/DebugInfo/X86/sroasplit-3.ll
index 48575ec018d9..ea70a776cebe 100644
--- a/llvm/test/DebugInfo/X86/sroasplit-3.ll
+++ b/llvm/test/DebugInfo/X86/sroasplit-3.ll
@@ -1,4 +1,6 @@
 ; RUN: opt %s -passes='sroa,verify' -S -o - | FileCheck %s
+; RUN: opt --try-experimental-debuginfo-iterators %s -passes='sroa,verify' -S -o - | FileCheck %s
+
 ; ModuleID = 'test.c'
 ; Test that SROA updates the debug info correctly if an alloca was rewritten but
 ; not partitioned into multiple allocas.
diff --git a/llvm/test/DebugInfo/X86/sroasplit-4.ll b/llvm/test/DebugInfo/X86/sroasplit-4.ll
index 7f6cd3dde73a..d3a6d147f2d3 100644
--- a/llvm/test/DebugInfo/X86/sroasplit-4.ll
+++ b/llvm/test/DebugInfo/X86/sroasplit-4.ll
@@ -1,4 +1,5 @@
 ; RUN: opt -passes='sroa' < %s -S -o - | FileCheck %s
+; RUN: opt --try-experimental-debuginfo-iterators -passes='sroa' < %s -S -o - | FileCheck %s
 ;
 ; Test that recursively splitting an alloca updates the debug info correctly.
 ; CHECK: %[[T:.*]] = load i64, ptr @t, align 8
diff --git a/llvm/test/DebugInfo/X86/sroasplit-5.ll b/llvm/test/DebugInfo/X86/sroasplit-5.ll
index d9dab2cad795..67acb71363e3 100644
--- a/llvm/test/DebugInfo/X86/sroasplit-5.ll
+++ b/llvm/test/DebugInfo/X86/sroasplit-5.ll
@@ -1,4 +1,6 @@
 ; RUN: opt %s -passes='sroa,verify' -S -o - | FileCheck %s
+; RUN: opt --try-experimental-debuginfo-iterators %s -passes='sroa,verify' -S -o - | FileCheck %s
+
 ; From:
 ; struct prog_src_register {
 ;   unsigned : 4;
diff --git a/llvm/test/DebugInfo/X86/sroasplit-dbg-declare.ll b/llvm/test/DebugInfo/X86/sroasplit-dbg-declare.ll
index 6a9f749b5c68..bebaea13470e 100644
--- a/llvm/test/DebugInfo/X86/sroasplit-dbg-declare.ll
+++ b/llvm/test/DebugInfo/X86/sroasplit-dbg-declare.ll
@@ -1,4 +1,5 @@
 ; RUN: opt -S -passes='sroa' -o - %s | FileCheck %s
+; RUN: opt --try-experimental-debuginfo-iterators -S -passes='sroa' -o - %s | FileCheck %s
 
 ; SROA should split the alloca in two new ones, each with its own dbg.declare.
 ; The original alloca and dbg.declare should be removed.
diff --git a/llvm/test/DebugInfo/salvage-overflow.ll b/llvm/test/DebugInfo/salvage-overflow.ll
index eff7514f82f6..1c14d4b1d205 100644
--- a/llvm/test/DebugInfo/salvage-overflow.ll
+++ b/llvm/test/DebugInfo/salvage-overflow.ll
@@ -1,4 +1,5 @@
 ; RUN: opt %s -passes='sroa,early-cse' -S | FileCheck %s
+; RUN: opt --try-experimental-debuginfo-iterators %s -passes='sroa,early-cse' -S | FileCheck %s
 ; CHECK: DIExpression(DW_OP_constu, 9223372036854775808, DW_OP_minus, DW_OP_stack_value)
 ; Created from the following C input (and then delta-reduced the IR):
 ;
diff --git a/llvm/test/Transforms/Util/dbg-user-of-aext.ll b/llvm/test/Transforms/Util/dbg-user-of-aext.ll
index c91b68a68e89..0511c4139898 100644
--- a/llvm/test/Transforms/Util/dbg-user-of-aext.ll
+++ b/llvm/test/Transforms/Util/dbg-user-of-aext.ll
@@ -2,6 +2,7 @@
 ; (here exposed through the SROA) pass refers to [s|z]exts of values (as
 ; opposed to the operand of a [s|z]ext).
 ; RUN: opt -S -passes='sroa' %s | FileCheck %s
+; RUN: opt --try-experimental-debuginfo-iterators -S -passes='sroa' %s | FileCheck %s
 
 ; Built from:
 ; struct foo { bool b; long i; };
-- 
GitLab


From c209d56e0fd3e8db358515dec5e85fdac2d8295d Mon Sep 17 00:00:00 2001
From: Benjamin Kramer <benny.kra@googlemail.com>
Date: Tue, 12 Dec 2023 16:54:24 +0100
Subject: [PATCH 323/349] [RemoveDIs] Fold variable into assert, it's only used
 once. NFC

---
 llvm/lib/Transforms/Utils/Local.cpp | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp
index 19b787c10e8f..a758fb306982 100644
--- a/llvm/lib/Transforms/Utils/Local.cpp
+++ b/llvm/lib/Transforms/Utils/Local.cpp
@@ -2135,9 +2135,8 @@ bool llvm::replaceDbgDeclare(Value *Address, Value *NewAddress,
   findDbgDeclares(DbgDeclares, Address, &DPValues);
 
   auto ReplaceOne = [&](auto *DII) {
-    auto *DIVar = DII->getVariable();
+    assert(DII->getVariable() && "Missing variable");
     auto *DIExpr = DII->getExpression();
-    assert(DIVar && "Missing variable");
     DIExpr = DIExpression::prepend(DIExpr, DIExprFlags, Offset);
     DII->setExpression(DIExpr);
     DII->replaceVariableLocationOp(Address, NewAddress);
-- 
GitLab


From ed210f9f5aab70cf4ca242535d1af0b0aa6a5781 Mon Sep 17 00:00:00 2001
From: Mark de Wever <koraq@xs4all.nl>
Date: Tue, 12 Dec 2023 17:11:53 +0100
Subject: [PATCH 324/349] [libc++][CI] Tests the no RTTI configuration.
 (#65518)

There are a few drive-by fixes:
- Since the combination RTTI disabled and exceptions enabled do not
work, this combination is prohibited.
- A small NFC in any fixing clang-tidy.

The code in the Buildkite configuration is prepared for using the std
module. There are more fixes needed for that configuration which will be
done in a separate commit.
---
 .github/workflows/libcxx-build-and-test.yaml |  1 +
 libcxx/CMakeLists.txt                        | 11 ++++++++++-
 libcxx/cmake/caches/Generic-no-rtti.cmake    |  4 ++++
 libcxx/docs/BuildingLibcxx.rst               |  1 +
 libcxx/utils/ci/run-buildbot                 |  5 +++++
 5 files changed, 21 insertions(+), 1 deletion(-)
 create mode 100644 libcxx/cmake/caches/Generic-no-rtti.cmake

diff --git a/.github/workflows/libcxx-build-and-test.yaml b/.github/workflows/libcxx-build-and-test.yaml
index 268e1033387d..370cf830a60c 100644
--- a/.github/workflows/libcxx-build-and-test.yaml
+++ b/.github/workflows/libcxx-build-and-test.yaml
@@ -160,6 +160,7 @@ jobs:
           'generic-no-tzdb',
           'generic-no-unicode',
           'generic-no-wide-characters',
+          'generic-no-rtti',
           'generic-static',
           'generic-with_llvm_unwinder',
           # TODO Find a better place for the benchmark and bootstrapping builds to live. They're either very expensive
diff --git a/libcxx/CMakeLists.txt b/libcxx/CMakeLists.txt
index 31fc9cec1c57..7751bf1efc59 100644
--- a/libcxx/CMakeLists.txt
+++ b/libcxx/CMakeLists.txt
@@ -284,7 +284,9 @@ endif()
 
 # Feature options -------------------------------------------------------------
 option(LIBCXX_ENABLE_EXCEPTIONS "Use exceptions." ON)
-option(LIBCXX_ENABLE_RTTI "Use run time type information." ON)
+option(LIBCXX_ENABLE_RTTI
+  "Use runtime type information.
+   This option may only be set to OFF when LIBCXX_ENABLE_EXCEPTIONS=OFF." ON)
 option(LIBCXX_ENABLE_THREADS "Build libc++ with support for threads." ON)
 option(LIBCXX_ENABLE_MONOTONIC_CLOCK
   "Build libc++ with support for a monotonic clock.
@@ -374,6 +376,13 @@ if (LIBCXX_HAS_PTHREAD_API)
   endif()
 endif()
 
+if (NOT LIBCXX_ENABLE_RTTI AND LIBCXX_ENABLE_EXCEPTIONS)
+  message(FATAL_ERROR "Libc++ cannot be built with exceptions enabled but RTTI"
+                      " disabled, since that configuration is broken. See"
+                      " https://github.com/llvm/llvm-project/issues/66117"
+                      " for details.")
+endif()
+
 # Ensure LLVM_USE_SANITIZER is not specified when LIBCXX_GENERATE_COVERAGE
 # is ON.
 if (LLVM_USE_SANITIZER AND LIBCXX_GENERATE_COVERAGE)
diff --git a/libcxx/cmake/caches/Generic-no-rtti.cmake b/libcxx/cmake/caches/Generic-no-rtti.cmake
new file mode 100644
index 000000000000..c62ddcec9014
--- /dev/null
+++ b/libcxx/cmake/caches/Generic-no-rtti.cmake
@@ -0,0 +1,4 @@
+set(LIBCXX_ENABLE_RTTI OFF CACHE BOOL "")
+set(LIBCXX_ENABLE_EXCEPTIONS OFF CACHE BOOL "")
+set(LIBCXXABI_ENABLE_RTTI OFF CACHE BOOL "")
+set(LIBCXXABI_ENABLE_EXCEPTIONS OFF CACHE BOOL "")
diff --git a/libcxx/docs/BuildingLibcxx.rst b/libcxx/docs/BuildingLibcxx.rst
index 2cee97c03ced..0b4d42052865 100644
--- a/libcxx/docs/BuildingLibcxx.rst
+++ b/libcxx/docs/BuildingLibcxx.rst
@@ -369,6 +369,7 @@ libc++ Feature Options
   **Default**: ``ON``
 
   Build libc++ with run time type information.
+  This option may only be set to OFF when LIBCXX_ENABLE_EXCEPTIONS=OFF.
 
 .. option:: LIBCXX_INCLUDE_TESTS:BOOL
 
diff --git a/libcxx/utils/ci/run-buildbot b/libcxx/utils/ci/run-buildbot
index 445b1becee0c..ee890fb76699 100755
--- a/libcxx/utils/ci/run-buildbot
+++ b/libcxx/utils/ci/run-buildbot
@@ -472,6 +472,11 @@ generic-no-exceptions)
     check-runtimes
     check-abi-list
 ;;
+generic-no-rtti)
+    clean
+    generate-cmake -C "${MONOREPO_ROOT}/libcxx/cmake/caches/Generic-no-rtti.cmake"
+    check-runtimes
+;;
 #
 # Other miscellaneous jobs
 #
-- 
GitLab


From d5c95302b9736b4e785c77463d7f2026b772ba1b Mon Sep 17 00:00:00 2001
From: Benji Smith <6193112+Benjins@users.noreply.github.com>
Date: Tue, 12 Dec 2023 11:15:05 -0500
Subject: [PATCH 325/349] [C API] Add getters and setters for fast-math flags
 on relevant instructions (#75123)

These flags are usable on floating point arithmetic, as well as call,
select, and phi instructions whose resulting type is floating point, or
a vector of, or an array of, a valid type. Whether or not the flags are
valid for a given instruction can be checked with the new
LLVMCanValueUseFastMathFlags function.

These are exposed using a new LLVMFastMathFlags type, which is an alias
for unsigned. An anonymous enum defines the bit values for it.

Tests are added in echo.ll for select/phil/call, and the floating point
types in the new float_ops.ll bindings test.

Select and the floating point arithmetic instructions were not
implemented in llvm-c-test/echo.cpp, so they were added as well.
---
 llvm/docs/ReleaseNotes.rst             |   4 +
 llvm/include/llvm-c/Core.h             |  50 ++++++++
 llvm/lib/IR/Core.cpp                   |  49 ++++++++
 llvm/test/Bindings/llvm-c/echo.ll      |  35 ++++++
 llvm/test/Bindings/llvm-c/float_ops.ll | 156 +++++++++++++++++++++++++
 llvm/tools/llvm-c-test/echo.cpp        |  56 +++++++++
 6 files changed, 350 insertions(+)
 create mode 100644 llvm/test/Bindings/llvm-c/float_ops.ll

diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index d5c634d2f29a..d90b29f63d90 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -226,6 +226,10 @@ Changes to the C API
   * ``LLVMGetOperandBundleArgAtIndex``
   * ``LLVMGetOperandBundleTag``
 
+* Added ``LLVMGetFastMathFlags`` and ``LLVMSetFastMathFlags`` for getting/setting
+  the fast-math flags of an instruction, as well as ``LLVMCanValueUseFastMathFlags``
+  for checking if an instruction can use such flags
+
 Changes to the CodeGen infrastructure
 -------------------------------------
 
diff --git a/llvm/include/llvm-c/Core.h b/llvm/include/llvm-c/Core.h
index 7cb809d378c9..83530ae7b513 100644
--- a/llvm/include/llvm-c/Core.h
+++ b/llvm/include/llvm-c/Core.h
@@ -483,6 +483,29 @@ typedef enum {
 
 typedef unsigned LLVMAttributeIndex;
 
+enum {
+  LLVMFastMathAllowReassoc = (1 << 0),
+  LLVMFastMathNoNaNs = (1 << 1),
+  LLVMFastMathNoInfs = (1 << 2),
+  LLVMFastMathNoSignedZeros = (1 << 3),
+  LLVMFastMathAllowReciprocal = (1 << 4),
+  LLVMFastMathAllowContract = (1 << 5),
+  LLVMFastMathApproxFunc = (1 << 6),
+  LLVMFastMathNone = 0,
+  LLVMFastMathAll = LLVMFastMathAllowReassoc | LLVMFastMathNoNaNs |
+                    LLVMFastMathNoInfs | LLVMFastMathNoSignedZeros |
+                    LLVMFastMathAllowReciprocal | LLVMFastMathAllowContract |
+                    LLVMFastMathApproxFunc,
+};
+
+/**
+ * Flags to indicate what fast-math-style optimizations are allowed
+ * on operations.
+ *
+ * See https://llvm.org/docs/LangRef.html#fast-math-flags
+ */
+typedef unsigned LLVMFastMathFlags;
+
 /**
  * @}
  */
@@ -4075,6 +4098,33 @@ LLVMBool LLVMGetNNeg(LLVMValueRef NonNegInst);
  */
 void LLVMSetNNeg(LLVMValueRef NonNegInst, LLVMBool IsNonNeg);
 
+/**
+ * Get the flags for which fast-math-style optimizations are allowed for this
+ * value.
+ *
+ * Only valid on floating point instructions.
+ * @see LLVMCanValueUseFastMathFlags
+ */
+LLVMFastMathFlags LLVMGetFastMathFlags(LLVMValueRef FPMathInst);
+
+/**
+ * Sets the flags for which fast-math-style optimizations are allowed for this
+ * value.
+ *
+ * Only valid on floating point instructions.
+ * @see LLVMCanValueUseFastMathFlags
+ */
+void LLVMSetFastMathFlags(LLVMValueRef FPMathInst, LLVMFastMathFlags FMF);
+
+/**
+ * Check if a given value can potentially have fast math flags.
+ *
+ * Will return true for floating point arithmetic instructions, and for select,
+ * phi, and call instructions whose type is a floating point type, or a vector
+ * or array thereof. See https://llvm.org/docs/LangRef.html#fast-math-flags
+ */
+LLVMBool LLVMCanValueUseFastMathFlags(LLVMValueRef Inst);
+
 /**
  * Gets whether the instruction has the disjoint flag set.
  * Only valid for or instructions.
diff --git a/llvm/lib/IR/Core.cpp b/llvm/lib/IR/Core.cpp
index 96629de8a753..fb30fbce0ba2 100644
--- a/llvm/lib/IR/Core.cpp
+++ b/llvm/lib/IR/Core.cpp
@@ -3319,6 +3319,39 @@ void LLVMSetArgOperand(LLVMValueRef Funclet, unsigned i, LLVMValueRef value) {
 
 /*--.. Arithmetic ..........................................................--*/
 
+static FastMathFlags mapFromLLVMFastMathFlags(LLVMFastMathFlags FMF) {
+  FastMathFlags NewFMF;
+  NewFMF.setAllowReassoc((FMF & LLVMFastMathAllowReassoc) != 0);
+  NewFMF.setNoNaNs((FMF & LLVMFastMathNoNaNs) != 0);
+  NewFMF.setNoInfs((FMF & LLVMFastMathNoInfs) != 0);
+  NewFMF.setNoSignedZeros((FMF & LLVMFastMathNoSignedZeros) != 0);
+  NewFMF.setAllowReciprocal((FMF & LLVMFastMathAllowReciprocal) != 0);
+  NewFMF.setAllowContract((FMF & LLVMFastMathAllowContract) != 0);
+  NewFMF.setApproxFunc((FMF & LLVMFastMathApproxFunc) != 0);
+
+  return NewFMF;
+}
+
+static LLVMFastMathFlags mapToLLVMFastMathFlags(FastMathFlags FMF) {
+  LLVMFastMathFlags NewFMF = LLVMFastMathNone;
+  if (FMF.allowReassoc())
+    NewFMF |= LLVMFastMathAllowReassoc;
+  if (FMF.noNaNs())
+    NewFMF |= LLVMFastMathNoNaNs;
+  if (FMF.noInfs())
+    NewFMF |= LLVMFastMathNoInfs;
+  if (FMF.noSignedZeros())
+    NewFMF |= LLVMFastMathNoSignedZeros;
+  if (FMF.allowReciprocal())
+    NewFMF |= LLVMFastMathAllowReciprocal;
+  if (FMF.allowContract())
+    NewFMF |= LLVMFastMathAllowContract;
+  if (FMF.approxFunc())
+    NewFMF |= LLVMFastMathApproxFunc;
+
+  return NewFMF;
+}
+
 LLVMValueRef LLVMBuildAdd(LLVMBuilderRef B, LLVMValueRef LHS, LLVMValueRef RHS,
                           const char *Name) {
   return wrap(unwrap(B)->CreateAdd(unwrap(LHS), unwrap(RHS), Name));
@@ -3518,6 +3551,22 @@ void LLVMSetNNeg(LLVMValueRef NonNegInst, LLVMBool IsNonNeg) {
   cast<Instruction>(P)->setNonNeg(IsNonNeg);
 }
 
+LLVMFastMathFlags LLVMGetFastMathFlags(LLVMValueRef FPMathInst) {
+  Value *P = unwrap<Value>(FPMathInst);
+  FastMathFlags FMF = cast<Instruction>(P)->getFastMathFlags();
+  return mapToLLVMFastMathFlags(FMF);
+}
+
+void LLVMSetFastMathFlags(LLVMValueRef FPMathInst, LLVMFastMathFlags FMF) {
+  Value *P = unwrap<Value>(FPMathInst);
+  cast<Instruction>(P)->setFastMathFlags(mapFromLLVMFastMathFlags(FMF));
+}
+
+LLVMBool LLVMCanValueUseFastMathFlags(LLVMValueRef V) {
+  Value *Val = unwrap<Value>(V);
+  return isa<FPMathOperator>(Val);
+}
+
 LLVMBool LLVMGetIsDisjoint(LLVMValueRef Inst) {
   Value *P = unwrap<Value>(Inst);
   return cast<PossiblyDisjointInst>(P)->isDisjoint();
diff --git a/llvm/test/Bindings/llvm-c/echo.ll b/llvm/test/Bindings/llvm-c/echo.ll
index 2e195beebd7b..be0207599478 100644
--- a/llvm/test/Bindings/llvm-c/echo.ll
+++ b/llvm/test/Bindings/llvm-c/echo.ll
@@ -299,6 +299,41 @@ entry:
   ret void
 }
 
+define void @test_fast_math_flags(i1 %c, float %a, float %b) {
+entry:
+  %select.f.1 = select i1 %c, float %a, float %b
+  %select.f.2 = select nsz i1 %c, float %a, float %b
+  %select.f.3 = select fast i1 %c, float %a, float %b
+  %select.f.4 = select nnan arcp afn i1 %c, float %a, float %b
+
+  br i1 %c, label %choose_a, label %choose_b
+
+choose_a:
+  br label %final
+
+choose_b:
+  br label %final
+
+final:
+  %phi.f.1 = phi float  [ %a, %choose_a ], [ %b, %choose_b ]
+  %phi.f.2 = phi nsz float [ %a, %choose_a ], [ %b, %choose_b ]
+  %phi.f.3 = phi fast float [ %a, %choose_a ], [ %b, %choose_b ]
+  %phi.f.4 = phi nnan arcp afn float [ %a, %choose_a ], [ %b, %choose_b ]
+  ret void
+}
+
+define float @test_fast_math_flags_call_inner(float %a) {
+  ret float %a
+}
+
+define void @test_fast_math_flags_call_outer(float %a) {
+  %a.1 = call float @test_fast_math_flags_call_inner(float %a)
+  %a.2 = call nsz float @test_fast_math_flags_call_inner(float %a)
+  %a.3 = call fast float @test_fast_math_flags_call_inner(float %a)
+  %a.4 = call nnan arcp afn float @test_fast_math_flags_call_inner(float %a)
+  ret void
+}
+
 !llvm.dbg.cu = !{!0, !2}
 !llvm.module.flags = !{!3}
 
diff --git a/llvm/test/Bindings/llvm-c/float_ops.ll b/llvm/test/Bindings/llvm-c/float_ops.ll
new file mode 100644
index 000000000000..80475c3d53f1
--- /dev/null
+++ b/llvm/test/Bindings/llvm-c/float_ops.ll
@@ -0,0 +1,156 @@
+; RUN: llvm-as < %s | llvm-dis > %t.orig
+; RUN: llvm-as < %s | llvm-c-test --echo > %t.echo
+; RUN: diff -w %t.orig %t.echo
+;
+source_filename = "/test/Bindings/float_ops.ll"
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+
+
+define float @float_ops_f32(float %a, float %b) {
+  %1 = fneg float %a
+
+  %2 = fadd float %a, %b
+  %3 = fsub float %a, %b
+  %4 = fmul float %a, %b
+  %5 = fdiv float %a, %b
+  %6 = frem float %a, %b
+
+  ret float %1
+}
+
+define double @float_ops_f64(double %a, double %b) {
+  %1 = fneg double %a
+
+  %2 = fadd double %a, %b
+  %3 = fsub double %a, %b
+  %4 = fmul double %a, %b
+  %5 = fdiv double %a, %b
+  %6 = frem double %a, %b
+
+  ret double %1
+}
+
+define void @float_cmp_f32(float %a, float %b) {
+  %1  = fcmp oeq float %a, %b
+  %2  = fcmp ogt float %a, %b
+  %3  = fcmp olt float %a, %b
+  %4  = fcmp ole float %a, %b
+  %5  = fcmp one float %a, %b
+
+  %6  = fcmp ueq float %a, %b
+  %7  = fcmp ugt float %a, %b
+  %8  = fcmp ult float %a, %b
+  %9  = fcmp ule float %a, %b
+  %10 = fcmp une float %a, %b
+
+  %11 = fcmp ord float %a, %b
+  %12 = fcmp false float %a, %b
+  %13 = fcmp true float %a, %b
+
+  ret void
+}
+
+define void @float_cmp_f64(double %a, double %b) {
+  %1  = fcmp oeq double %a, %b
+  %2  = fcmp ogt double %a, %b
+  %3  = fcmp olt double %a, %b
+  %4  = fcmp ole double %a, %b
+  %5  = fcmp one double %a, %b
+
+  %6  = fcmp ueq double %a, %b
+  %7  = fcmp ugt double %a, %b
+  %8  = fcmp ult double %a, %b
+  %9  = fcmp ule double %a, %b
+  %10 = fcmp une double %a, %b
+
+  %11 = fcmp ord double %a, %b
+  %12 = fcmp false double %a, %b
+  %13 = fcmp true double %a, %b
+
+  ret void
+}
+
+define void @float_cmp_fast_f32(float %a, float %b) {
+  %1  = fcmp fast oeq float %a, %b
+  %2  = fcmp nsz ogt float %a, %b
+  %3  = fcmp nsz nnan olt float %a, %b
+  %4  = fcmp contract ole float %a, %b
+  %5  = fcmp nnan one float %a, %b
+
+  %6  = fcmp nnan ninf nsz ueq float %a, %b
+  %7  = fcmp arcp ugt float %a, %b
+  %8  = fcmp fast ult float %a, %b
+  %9  = fcmp fast ule float %a, %b
+  %10 = fcmp fast une float %a, %b
+
+  %11 = fcmp fast ord float %a, %b
+  %12 = fcmp nnan ninf false float %a, %b
+  %13 = fcmp nnan ninf true float %a, %b
+
+  ret void
+}
+
+define void @float_cmp_fast_f64(double %a, double %b) {
+  %1  = fcmp fast oeq double %a, %b
+  %2  = fcmp nsz ogt double %a, %b
+  %3  = fcmp nsz nnan olt double %a, %b
+  %4  = fcmp contract ole double %a, %b
+  %5  = fcmp nnan one double %a, %b
+
+  %6  = fcmp nnan ninf nsz ueq double %a, %b
+  %7  = fcmp arcp ugt double %a, %b
+  %8  = fcmp fast ult double %a, %b
+  %9  = fcmp fast ule double %a, %b
+  %10 = fcmp fast une double %a, %b
+
+  %11 = fcmp fast ord double %a, %b
+  %12 = fcmp nnan ninf false double %a, %b
+  %13 = fcmp nnan ninf true double %a, %b
+
+  ret void
+}
+
+define float @float_ops_fast_f32(float %a, float %b) {
+  %1 = fneg nnan float %a
+
+  %2 = fadd ninf float %a, %b
+  %3 = fsub nsz float %a, %b
+  %4 = fmul arcp float %a, %b
+  %5 = fdiv contract float %a, %b
+  %6 = frem afn float %a, %b
+
+  %7 = fadd reassoc float %a, %b
+  %8 = fadd reassoc float %7, %b
+
+  %9  = fadd fast float %a, %b
+  %10 = fadd nnan nsz float %a, %b
+  %11 = frem nnan nsz float %a, %b
+  %12 = fdiv nnan nsz arcp float %a, %b
+  %13 = fmul nnan nsz ninf contract float %a, %b
+  %14 = fmul nnan nsz ninf arcp contract afn reassoc float %a, %b
+
+  ret float %1
+}
+
+define double @float_ops_fast_f64(double %a, double %b) {
+  %1 = fneg nnan double %a
+
+  %2 = fadd ninf double %a, %b
+  %3 = fsub nsz double %a, %b
+  %4 = fmul arcp double %a, %b
+  %5 = fdiv contract double %a, %b
+  %6 = frem afn double %a, %b
+
+  %7 = fadd reassoc double %a, %b
+  %8 = fadd reassoc double %7, %b
+
+  %9  = fadd fast double %a, %b
+  %10 = fadd nnan nsz double %a, %b
+  %11 = frem nnan nsz double %a, %b
+  %12 = fdiv nnan nsz arcp double %a, %b
+  %13 = fmul nnan nsz ninf contract double %a, %b
+  %14 = fmul nnan nsz ninf arcp contract afn reassoc double %a, %b
+
+  ret double %1
+}
+
diff --git a/llvm/tools/llvm-c-test/echo.cpp b/llvm/tools/llvm-c-test/echo.cpp
index bfc14e85a12b..bc708e2d472e 100644
--- a/llvm/tools/llvm-c-test/echo.cpp
+++ b/llvm/tools/llvm-c-test/echo.cpp
@@ -770,8 +770,18 @@ struct FunCloner {
         }
 
         LLVMAddIncoming(Dst, Values.data(), Blocks.data(), IncomingCount);
+        // Copy fast math flags here since we return early
+        if (LLVMCanValueUseFastMathFlags(Src))
+          LLVMSetFastMathFlags(Dst, LLVMGetFastMathFlags(Src));
         return Dst;
       }
+      case LLVMSelect: {
+        LLVMValueRef If = CloneValue(LLVMGetOperand(Src, 0));
+        LLVMValueRef Then = CloneValue(LLVMGetOperand(Src, 1));
+        LLVMValueRef Else = CloneValue(LLVMGetOperand(Src, 2));
+        Dst = LLVMBuildSelect(Builder, If, Then, Else, Name);
+        break;
+      }
       case LLVMCall: {
         SmallVector<LLVMValueRef, 8> Args;
         SmallVector<LLVMOperandBundleRef, 8> Bundles;
@@ -930,6 +940,48 @@ struct FunCloner {
         LLVMSetNNeg(Dst, NNeg);
         break;
       }
+      case LLVMFAdd: {
+        LLVMValueRef LHS = CloneValue(LLVMGetOperand(Src, 0));
+        LLVMValueRef RHS = CloneValue(LLVMGetOperand(Src, 1));
+        Dst = LLVMBuildFAdd(Builder, LHS, RHS, Name);
+        break;
+      }
+      case LLVMFSub: {
+        LLVMValueRef LHS = CloneValue(LLVMGetOperand(Src, 0));
+        LLVMValueRef RHS = CloneValue(LLVMGetOperand(Src, 1));
+        Dst = LLVMBuildFSub(Builder, LHS, RHS, Name);
+        break;
+      }
+      case LLVMFMul: {
+        LLVMValueRef LHS = CloneValue(LLVMGetOperand(Src, 0));
+        LLVMValueRef RHS = CloneValue(LLVMGetOperand(Src, 1));
+        Dst = LLVMBuildFMul(Builder, LHS, RHS, Name);
+        break;
+      }
+      case LLVMFDiv: {
+        LLVMValueRef LHS = CloneValue(LLVMGetOperand(Src, 0));
+        LLVMValueRef RHS = CloneValue(LLVMGetOperand(Src, 1));
+        Dst = LLVMBuildFDiv(Builder, LHS, RHS, Name);
+        break;
+      }
+      case LLVMFRem: {
+        LLVMValueRef LHS = CloneValue(LLVMGetOperand(Src, 0));
+        LLVMValueRef RHS = CloneValue(LLVMGetOperand(Src, 1));
+        Dst = LLVMBuildFRem(Builder, LHS, RHS, Name);
+        break;
+      }
+      case LLVMFNeg: {
+        LLVMValueRef Val = CloneValue(LLVMGetOperand(Src, 0));
+        Dst = LLVMBuildFNeg(Builder, Val, Name);
+        break;
+      }
+      case LLVMFCmp: {
+        LLVMRealPredicate Pred = LLVMGetFCmpPredicate(Src);
+        LLVMValueRef LHS = CloneValue(LLVMGetOperand(Src, 0));
+        LLVMValueRef RHS = CloneValue(LLVMGetOperand(Src, 1));
+        Dst = LLVMBuildFCmp(Builder, Pred, LHS, RHS, Name);
+        break;
+      }
       default:
         break;
     }
@@ -939,6 +991,10 @@ struct FunCloner {
       exit(-1);
     }
 
+    // Copy fast-math flags on instructions that support them
+    if (LLVMCanValueUseFastMathFlags(Src))
+      LLVMSetFastMathFlags(Dst, LLVMGetFastMathFlags(Src));
+
     auto Ctx = LLVMGetModuleContext(M);
     size_t NumMetadataEntries;
     auto *AllMetadata =
-- 
GitLab


From 2a1d222010266147c6767f34b25c5a91c93b55de Mon Sep 17 00:00:00 2001
From: Pete Steinfeld <47540744+psteinfeld@users.noreply.github.com>
Date: Tue, 12 Dec 2023 08:15:53 -0800
Subject: [PATCH 326/349] [flang] Fix compilation error due to variable no
 being used (#75210)

My builds were failing because the variable 'dim' was not used. This
produced a warning, and my builds have warnings set as errors.
---
 flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp | 1 -
 1 file changed, 1 deletion(-)

diff --git a/flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp b/flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
index 6af2888b3a60..46eee8acac24 100644
--- a/flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
+++ b/flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
@@ -663,7 +663,6 @@ template <typename NumericalReductionOp>
 static mlir::LogicalResult
 verifyArrayAndMaskForReductionOp(NumericalReductionOp reductionOp) {
   mlir::Value array = reductionOp->getArray();
-  mlir::Value dim = reductionOp->getDim();
   mlir::Value mask = reductionOp->getMask();
 
   fir::SequenceType arrayTy =
-- 
GitLab


From 142e567cf00815f7d1b3d72aaf298212a3f83ab2 Mon Sep 17 00:00:00 2001
From: Cyndy Ishida <cyndy_ishida@apple.com>
Date: Tue, 12 Dec 2023 08:25:53 -0800
Subject: [PATCH 327/349] [readtapi] Cleanup printing command line options
 (#75106)

Also, add a version option.
---
 llvm/test/tools/llvm-readtapi/command-line.test | 17 +++++++++++------
 llvm/tools/llvm-readtapi/TapiOpts.td            | 10 ++++++----
 llvm/tools/llvm-readtapi/llvm-readtapi.cpp      | 12 +++++++++---
 3 files changed, 26 insertions(+), 13 deletions(-)

diff --git a/llvm/test/tools/llvm-readtapi/command-line.test b/llvm/test/tools/llvm-readtapi/command-line.test
index 1006bfe9cc25..59a247c0f593 100644
--- a/llvm/test/tools/llvm-readtapi/command-line.test
+++ b/llvm/test/tools/llvm-readtapi/command-line.test
@@ -4,12 +4,17 @@
 ; RUN: not llvm-readtapi -merge -compare -compact %t/tmp.tbd %t/tmp2.tbd 2>&1 | FileCheck %s --check-prefix MULTI_ACTION
 // Check unsupported file output format.
 ; RUN: not llvm-readtapi -merge -compact %t/tmp.tbd %t/tmp2.tbd --filetype=tbd-v2 2>&1 | FileCheck %s --check-prefix FILE_FORMAT 
+// Check version printing.
+; RUN: llvm-readtapi -v 2>&1 | FileCheck %s --check-prefix VERSION
+; RUN: llvm-readtapi --version 2>&1 | FileCheck %s --check-prefix VERSION
 
-CHECK: OVERVIEW: LLVM TAPI file reader and manipulator
-CHECK: USAGE: llvm-readtapi [options] [-arch <arch>]* <inputs> [-o <output>]*
-CHECK: OPTIONS:
-CHECK:   -help    display this help
+; CHECK: OVERVIEW: LLVM TAPI file reader and transformer 
+; CHECK: USAGE: llvm-readtapi <command> [-arch <architecture> <options>]* <inputs> [-o <output>]*
+; CHECK: COMMANDS:
+; CHECK: OPTIONS:
+; CHECK:   -help    display this help
 
-MULTI_ACTION: error: only one of the following actions can be specified: -merge -compare
-FILE_FORMAT: error: deprecated filetype 'tbd-v2' is not supported to write
+; MULTI_ACTION: error: only one of the following actions can be specified: -merge -compare
+; FILE_FORMAT: error: deprecated filetype 'tbd-v2' is not supported to write
 
+; VERSION: {{ version }}
diff --git a/llvm/tools/llvm-readtapi/TapiOpts.td b/llvm/tools/llvm-readtapi/TapiOpts.td
index 8fda035142a2..552690ce1385 100644
--- a/llvm/tools/llvm-readtapi/TapiOpts.td
+++ b/llvm/tools/llvm-readtapi/TapiOpts.td
@@ -10,17 +10,19 @@ multiclass JS<string name, string help, string var = ""> {
 //
 // Top level operations 
 //
-def action_group : OptionGroup<"action group">;
+def action_group : OptionGroup<"action group">, HelpText<"COMMANDS">;
 def compare : FF<"compare", "compare tapi files for library differences">, Group<action_group>;
 def merge : FF<"merge", "merge the input files that represent the same library">, Group<action_group>;
-def extract: FF<"extract", "extract architecture from input file">, Group<action_group>;
-def remove: FF<"remove", "remove architecture from input file">, Group<action_group>;
+def extract: FF<"extract", "extract <architecture> from input file">, Group<action_group>;
+def remove: FF<"remove", "remove <architecture> from input file">, Group<action_group>;
 
 //
 // General Driver options 
 //
 def help : FF<"help", "display this help">;
+def version: FF<"version", "print the llvm-readtapi version">;
+def v: FF<"v", "alias for --version">, Alias<version>;
 defm output: JS<"o", "write output to <file>","<file>">;
 def compact: FF<"compact", "write compact tapi output file">;
 defm filetype: JS<"filetype", "specify the output file type (tbd-v3, tbd-v4 or tbd-v5)","<value>">;
-defm arch: JS<"arch", "specify the architecture", "<architecture>">;
+defm arch: JS<"arch", "specify the <architecture>", "<architecture>">;
diff --git a/llvm/tools/llvm-readtapi/llvm-readtapi.cpp b/llvm/tools/llvm-readtapi/llvm-readtapi.cpp
index 64eff70dbfc7..5fa023d12525 100644
--- a/llvm/tools/llvm-readtapi/llvm-readtapi.cpp
+++ b/llvm/tools/llvm-readtapi/llvm-readtapi.cpp
@@ -1,4 +1,4 @@
-//===-- llvm-readtapi.cpp - tapi file reader and manipulator -----*- C++-*-===//
+//===-- llvm-readtapi.cpp - tapi file reader and transformer -----*- C++-*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -171,9 +171,15 @@ int main(int Argc, char **Argv) {
       Argc, Argv, OPT_UNKNOWN, Saver, [&](StringRef Msg) { reportError(Msg); });
   if (Args.hasArg(OPT_help)) {
     Tbl.printHelp(outs(),
-                  "USAGE: llvm-readtapi [options] [-arch <arch>]* <inputs> [-o "
+                  "USAGE: llvm-readtapi <command> [-arch <architecture> "
+                  "<options>]* <inputs> [-o "
                   "<output>]*",
-                  "LLVM TAPI file reader and manipulator");
+                  "LLVM TAPI file reader and transformer");
+    return EXIT_SUCCESS;
+  }
+
+  if (Args.hasArg(OPT_version)) {
+    cl::PrintVersionMessage();
     return EXIT_SUCCESS;
   }
 
-- 
GitLab


From 4b4dcb49887bb4a75d55c91af50f576b7fc16a74 Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu@google.com>
Date: Tue, 12 Dec 2023 08:50:49 -0800
Subject: [PATCH 328/349] [Transforms] Fix a warning

This patch fixes:

  llvm/lib/Transforms/Scalar/SROA.cpp:4855:9: error: unused variable
  'NewAssign' [-Werror,-Wunused-variable]
---
 llvm/lib/Transforms/Scalar/SROA.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/llvm/lib/Transforms/Scalar/SROA.cpp b/llvm/lib/Transforms/Scalar/SROA.cpp
index b0285dd7de0a..24da26c9f0f2 100644
--- a/llvm/lib/Transforms/Scalar/SROA.cpp
+++ b/llvm/lib/Transforms/Scalar/SROA.cpp
@@ -4856,6 +4856,7 @@ static void insertNewDbgInst(DIBuilder &DIB, DbgAssignIntrinsic *Orig,
       NewAddr, Orig->getValue(), Orig->getVariable(), NewFragmentExpr, NewAddr,
       Orig->getAddressExpression(), Orig->getDebugLoc());
   LLVM_DEBUG(dbgs() << "Created new assign intrinsic: " << *NewAssign << "\n");
+  (void)NewAssign;
 }
 static void insertNewDbgInst(DIBuilder &DIB, DPValue *Orig, AllocaInst *NewAddr,
                              DIExpression *NewFragmentExpr,
-- 
GitLab


From ac616408b276fc953d5f800229830b48fef4d308 Mon Sep 17 00:00:00 2001
From: Jonas Hahnfeld <jonas.hahnfeld@cern.ch>
Date: Tue, 12 Dec 2023 17:57:19 +0100
Subject: [PATCH 329/349] [clang][Sema] Always clear UndefinedButUsed (#73955)

Before, it was only cleared if there were undefined entities. This is
important for Clang's incremental parsing as used by `clang-repl` that
might receive multiple calls to `Sema.ActOnEndOfTranslationUnit`.
---
 clang/lib/Sema/Sema.cpp | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp
index 22929aa6316d..cafbecebc8a1 100644
--- a/clang/lib/Sema/Sema.cpp
+++ b/clang/lib/Sema/Sema.cpp
@@ -870,6 +870,7 @@ static void checkUndefinedButUsed(Sema &S) {
   // Collect all the still-undefined entities with internal linkage.
   SmallVector<std::pair<NamedDecl *, SourceLocation>, 16> Undefined;
   S.getUndefinedButUsed(Undefined);
+  S.UndefinedButUsed.clear();
   if (Undefined.empty()) return;
 
   for (const auto &Undef : Undefined) {
@@ -923,8 +924,6 @@ static void checkUndefinedButUsed(Sema &S) {
     if (UseLoc.isValid())
       S.Diag(UseLoc, diag::note_used_here);
   }
-
-  S.UndefinedButUsed.clear();
 }
 
 void Sema::LoadExternalWeakUndeclaredIdentifiers() {
-- 
GitLab


From 935c6a2d8d01c602017d8ffa01c3c0bcde2f3d28 Mon Sep 17 00:00:00 2001
From: Nick Desaulniers <nickdesaulniers@users.noreply.github.com>
Date: Tue, 12 Dec 2023 08:58:58 -0800
Subject: [PATCH 330/349] [RegAllocFast] NFC cleanups (#74860)

- use more range for
- avoid capturing lambda
- prefer Register type to unsigned
- remove braces around single statement if
---
 llvm/lib/CodeGen/RegAllocFast.cpp | 65 ++++++++++++++-----------------
 1 file changed, 30 insertions(+), 35 deletions(-)

diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp
index b216d7296446..40c42cabf776 100644
--- a/llvm/lib/CodeGen/RegAllocFast.cpp
+++ b/llvm/lib/CodeGen/RegAllocFast.cpp
@@ -268,7 +268,7 @@ private:
                                 Register VirtReg);
   bool defineVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg,
                      bool LookAtPhysRegUses = false);
-  bool useVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg);
+  bool useVirtReg(MachineInstr &MI, MachineOperand &MO, Register VirtReg);
 
   MachineBasicBlock::iterator
   getMBBBeginInsertionPoint(MachineBasicBlock &MBB,
@@ -984,17 +984,15 @@ bool RegAllocFast::defineVirtReg(MachineInstr &MI, unsigned OpNum,
 
 /// Allocates a register for a VirtReg use.
 /// \return true if MI's MachineOperands were re-arranged/invalidated.
-bool RegAllocFast::useVirtReg(MachineInstr &MI, unsigned OpNum,
+bool RegAllocFast::useVirtReg(MachineInstr &MI, MachineOperand &MO,
                               Register VirtReg) {
   assert(VirtReg.isVirtual() && "Not a virtual register");
   if (!shouldAllocateRegister(VirtReg))
     return false;
-  MachineOperand &MO = MI.getOperand(OpNum);
   LiveRegMap::iterator LRI;
   bool New;
   std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
   if (New) {
-    MachineOperand &MO = MI.getOperand(OpNum);
     if (!MO.isKill()) {
       if (mayLiveOut(VirtReg)) {
         LRI->LiveOut = true;
@@ -1224,6 +1222,17 @@ void RegAllocFast::findAndSortDefOperandIndexes(const MachineInstr &MI) {
   });
 }
 
+// Returns true if MO is tied and the operand it's tied to is not Undef (not
+// Undef is not the same thing as Def).
+static bool isTiedToNotUndef(const MachineOperand &MO) {
+  if (!MO.isTied())
+    return false;
+  const MachineInstr &MI = *MO.getParent();
+  unsigned TiedIdx = MI.findTiedOperandIdx(MI.getOperandNo(&MO));
+  const MachineOperand &TiedMO = MI.getOperand(TiedIdx);
+  return !TiedMO.isUndef();
+}
+
 void RegAllocFast::allocateInstruction(MachineInstr &MI) {
   // The basic algorithm here is:
   // 1. Mark registers of def operands as free
@@ -1241,12 +1250,6 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) {
   RegMasks.clear();
   BundleVirtRegsMap.clear();
 
-  auto TiedOpIsUndef = [&](const MachineOperand &MO, unsigned Idx) {
-    assert(MO.isTied());
-    unsigned TiedIdx = MI.findTiedOperandIdx(Idx);
-    const MachineOperand &TiedMO = MI.getOperand(TiedIdx);
-    return TiedMO.isUndef();
-  };
   // Scan for special cases; Apply pre-assigned register defs to state.
   bool HasPhysRegUse = false;
   bool HasRegMask = false;
@@ -1254,8 +1257,7 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) {
   bool HasDef = false;
   bool HasEarlyClobber = false;
   bool NeedToAssignLiveThroughs = false;
-  for (unsigned I = 0; I < MI.getNumOperands(); ++I) {
-    MachineOperand &MO = MI.getOperand(I);
+  for (MachineOperand &MO : MI.operands()) {
     if (MO.isReg()) {
       Register Reg = MO.getReg();
       if (Reg.isVirtual()) {
@@ -1268,8 +1270,7 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) {
             HasEarlyClobber = true;
             NeedToAssignLiveThroughs = true;
           }
-          if ((MO.isTied() && !TiedOpIsUndef(MO, I)) ||
-              (MO.getSubReg() != 0 && !MO.isUndef()))
+          if (isTiedToNotUndef(MO) || (MO.getSubReg() != 0 && !MO.isUndef()))
             NeedToAssignLiveThroughs = true;
         }
       } else if (Reg.isPhysical()) {
@@ -1314,35 +1315,32 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) {
           for (uint16_t OpIdx : DefOperandIndexes) {
             MachineOperand &MO = MI.getOperand(OpIdx);
             LLVM_DEBUG(dbgs() << "Allocating " << MO << '\n');
-            unsigned Reg = MO.getReg();
-            if (MO.isEarlyClobber() ||
-                (MO.isTied() && !TiedOpIsUndef(MO, OpIdx)) ||
+            Register Reg = MO.getReg();
+            if (MO.isEarlyClobber() || isTiedToNotUndef(MO) ||
                 (MO.getSubReg() && !MO.isUndef())) {
               ReArrangedImplicitOps = defineLiveThroughVirtReg(MI, OpIdx, Reg);
             } else {
               ReArrangedImplicitOps = defineVirtReg(MI, OpIdx, Reg);
             }
-            if (ReArrangedImplicitOps) {
-              // Implicit operands of MI were re-arranged,
-              // re-compute DefOperandIndexes.
+            // Implicit operands of MI were re-arranged,
+            // re-compute DefOperandIndexes.
+            if (ReArrangedImplicitOps)
               break;
-            }
           }
         }
       } else {
         // Assign virtual register defs.
         while (ReArrangedImplicitOps) {
           ReArrangedImplicitOps = false;
-          for (unsigned I = 0, E = MI.getNumOperands(); I < E; ++I) {
-            MachineOperand &MO = MI.getOperand(I);
+          for (MachineOperand &MO : MI.operands()) {
             if (!MO.isReg() || !MO.isDef())
               continue;
             Register Reg = MO.getReg();
             if (Reg.isVirtual()) {
-              ReArrangedImplicitOps = defineVirtReg(MI, I, Reg);
-              if (ReArrangedImplicitOps) {
+              ReArrangedImplicitOps =
+                  defineVirtReg(MI, MI.getOperandNo(&MO), Reg);
+              if (ReArrangedImplicitOps)
                 break;
-              }
             }
           }
         }
@@ -1352,8 +1350,7 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) {
     // Free registers occupied by defs.
     // Iterate operands in reverse order, so we see the implicit super register
     // defs first (we added them earlier in case of <def,read-undef>).
-    for (signed I = MI.getNumOperands() - 1; I >= 0; --I) {
-      MachineOperand &MO = MI.getOperand(I);
+    for (MachineOperand &MO : reverse(MI.operands())) {
       if (!MO.isReg() || !MO.isDef())
         continue;
 
@@ -1370,7 +1367,7 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) {
              "tied def assigned to clobbered register");
 
       // Do not free tied operands and early clobbers.
-      if ((MO.isTied() && !TiedOpIsUndef(MO, I)) || MO.isEarlyClobber())
+      if (isTiedToNotUndef(MO) || MO.isEarlyClobber())
         continue;
       if (!Reg)
         continue;
@@ -1411,8 +1408,7 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) {
         continue;
       if (MRI->isReserved(Reg))
         continue;
-      bool displacedAny = usePhysReg(MI, Reg);
-      if (!displacedAny)
+      if (!usePhysReg(MI, Reg))
         MO.setIsKill(true);
     }
   }
@@ -1424,8 +1420,7 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) {
   bool ReArrangedImplicitMOs = true;
   while (ReArrangedImplicitMOs) {
     ReArrangedImplicitMOs = false;
-    for (unsigned I = 0; I < MI.getNumOperands(); ++I) {
-      MachineOperand &MO = MI.getOperand(I);
+    for (MachineOperand &MO : MI.operands()) {
       if (!MO.isReg() || !MO.isUse())
         continue;
       Register Reg = MO.getReg();
@@ -1443,7 +1438,7 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) {
 
       assert(!MO.isInternalRead() && "Bundles not supported");
       assert(MO.readsReg() && "reading use");
-      ReArrangedImplicitMOs = useVirtReg(MI, I, Reg);
+      ReArrangedImplicitMOs = useVirtReg(MI, MO, Reg);
       if (ReArrangedImplicitMOs)
         break;
     }
@@ -1465,7 +1460,7 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) {
 
   // Free early clobbers.
   if (HasEarlyClobber) {
-    for (MachineOperand &MO : llvm::reverse(MI.all_defs())) {
+    for (MachineOperand &MO : reverse(MI.all_defs())) {
       if (!MO.isEarlyClobber())
         continue;
       assert(!MO.getSubReg() && "should be already handled in def processing");
-- 
GitLab


From 4b7d4008e21e9da9a189523ff90389a044b37ea4 Mon Sep 17 00:00:00 2001
From: DonatNagyE <donat.nagy@ericsson.com>
Date: Tue, 12 Dec 2023 18:15:33 +0100
Subject: [PATCH 331/349] [analyzer] Fix broken testcase (#75216)

When merging commit c873f77e87a9ebd02f94d6b9d46e84d43e1ceb38 I didn't
manually rebase it onto the tip of the main branch, so I didn't notice
that the testcase that's added by it needs to be tweaked to account for
the effects of commit 2f29ded4f98e8e1fa26725c618a08082a09b405a (which
was also merged by me a few days ago).
---
 clang/test/Analysis/enum-cast-out-of-range.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clang/test/Analysis/enum-cast-out-of-range.cpp b/clang/test/Analysis/enum-cast-out-of-range.cpp
index 82086b730578..a5ac4f3fd056 100644
--- a/clang/test/Analysis/enum-cast-out-of-range.cpp
+++ b/clang/test/Analysis/enum-cast-out-of-range.cpp
@@ -226,7 +226,7 @@ enum WidgetKind { A=1, B, C, X=99 }; // expected-note {{enum declared here}}
 void foo() {
   WidgetKind c = static_cast<WidgetKind>(3);  // OK
   WidgetKind x = static_cast<WidgetKind>(99); // OK
-  WidgetKind d = static_cast<WidgetKind>(4);  // expected-warning {{The value provided to the cast expression is not in the valid range of values for 'WidgetKind'}}
+  WidgetKind d = static_cast<WidgetKind>(4);  // expected-warning {{The value '4' provided to the cast expression is not in the valid range of values for 'WidgetKind'}}
 
   ignore_unused(c, x, d);
 }
-- 
GitLab


From cc5a3be48b80e7158a1d55cf73cc1d6a77f78124 Mon Sep 17 00:00:00 2001
From: LLVM GN Syncbot <llvmgnsyncbot@gmail.com>
Date: Tue, 12 Dec 2023 17:15:43 +0000
Subject: [PATCH 332/349] [gn build] Port 6a6646749900

---
 llvm/utils/gn/secondary/libcxx/include/BUILD.gn | 1 +
 1 file changed, 1 insertion(+)

diff --git a/llvm/utils/gn/secondary/libcxx/include/BUILD.gn b/llvm/utils/gn/secondary/libcxx/include/BUILD.gn
index 9e7a67ef81d8..5cc9ec5889d4 100644
--- a/llvm/utils/gn/secondary/libcxx/include/BUILD.gn
+++ b/llvm/utils/gn/secondary/libcxx/include/BUILD.gn
@@ -904,6 +904,7 @@ if (current_toolchain == default_toolchain) {
       "__type_traits/void_t.h",
       "__undef_macros",
       "__utility/as_const.h",
+      "__utility/as_lvalue.h",
       "__utility/auto_cast.h",
       "__utility/cmp.h",
       "__utility/convert_to_integral.h",
-- 
GitLab


From 671fa917ce33b6dfadd87d57ba30c59fa94e9a27 Mon Sep 17 00:00:00 2001
From: Lang Hames <lhames@gmail.com>
Date: Tue, 12 Dec 2023 09:36:12 -0800
Subject: [PATCH 333/349] [ORC][MachO] For convenience, make MachOPlatform ref
 available to subclasses.

This saves SimpleMachOHeaderMU subclasses from having to hold their own
reference.
---
 llvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h b/llvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h
index db7855e69a66..d9b809ab5b11 100644
--- a/llvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h
+++ b/llvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h
@@ -345,6 +345,8 @@ protected:
   virtual jitlink::Block &createHeaderBlock(JITDylib &JD, jitlink::LinkGraph &G,
                                             jitlink::Section &HeaderSection);
 
+  MachOPlatform &MOP;
+
 private:
   struct HeaderSymbol {
     const char *Name;
@@ -359,8 +361,6 @@ private:
   static MaterializationUnit::Interface
   createHeaderInterface(MachOPlatform &MOP,
                         const SymbolStringPtr &HeaderStartSymbol);
-
-  MachOPlatform &MOP;
 };
 
 /// Simple MachO header graph builder.
-- 
GitLab


From 8005ee6da36c3af69e2f2ebed97f17603ffa7e44 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad@amd.com>
Date: Tue, 12 Dec 2023 17:41:40 +0000
Subject: [PATCH 334/349] [AMDGPU] CodeGen for GFX12 64-bit scalar add/sub
 (#75070)

---
 .../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp |   24 +-
 llvm/lib/Target/AMDGPU/GCNSubtarget.h         |    2 +
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp     |   67 +-
 .../CodeGen/AMDGPU/GlobalISel/addsubu64.ll    |  107 ++
 llvm/test/CodeGen/AMDGPU/add.ll               | 1395 ++++++++++++++++-
 .../CodeGen/AMDGPU/move-to-valu-addsubu64.ll  |  118 ++
 llvm/test/CodeGen/AMDGPU/sub.ll               |  232 ++-
 7 files changed, 1833 insertions(+), 112 deletions(-)
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
 create mode 100644 llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll

diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index ccdbd3216e26..2cf804e3348e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -681,13 +681,23 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
 
   if (ST.hasVOP3PInsts() && ST.hasAddNoCarry() && ST.hasIntClamp()) {
     // Full set of gfx9 features.
-    getActionDefinitionsBuilder({G_ADD, G_SUB})
-      .legalFor({S32, S16, V2S16})
-      .clampMaxNumElementsStrict(0, S16, 2)
-      .scalarize(0)
-      .minScalar(0, S16)
-      .widenScalarToNextMultipleOf(0, 32)
-      .maxScalar(0, S32);
+    if (ST.hasScalarAddSub64()) {
+      getActionDefinitionsBuilder({G_ADD, G_SUB})
+          .legalFor({S64, S32, S16, V2S16})
+          .clampMaxNumElementsStrict(0, S16, 2)
+          .scalarize(0)
+          .minScalar(0, S16)
+          .widenScalarToNextMultipleOf(0, 32)
+          .maxScalar(0, S32);
+    } else {
+      getActionDefinitionsBuilder({G_ADD, G_SUB})
+          .legalFor({S32, S16, V2S16})
+          .clampMaxNumElementsStrict(0, S16, 2)
+          .scalarize(0)
+          .minScalar(0, S16)
+          .widenScalarToNextMultipleOf(0, 32)
+          .maxScalar(0, S32);
+    }
 
     getActionDefinitionsBuilder(G_MUL)
       .legalFor({S32, S16, V2S16})
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index 94b9e49b765a..2eed024af60a 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -677,6 +677,8 @@ public:
     return AddNoCarryInsts;
   }
 
+  bool hasScalarAddSub64() const { return getGeneration() >= GFX12; }
+
   bool hasUnpackedD16VMem() const {
     return HasUnpackedD16VMem;
   }
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 3626715acb3c..85cc3cfec19c 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -4555,40 +4555,51 @@ MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
   }
   case AMDGPU::S_ADD_U64_PSEUDO:
   case AMDGPU::S_SUB_U64_PSEUDO: {
-    MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
+    // For targets older than GFX12, we emit a sequence of 32-bit operations.
+    // For GFX12, we emit s_add_u64 and s_sub_u64.
     const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
-    const SIRegisterInfo *TRI = ST.getRegisterInfo();
-    const TargetRegisterClass *BoolRC = TRI->getBoolRC();
+    MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
     const DebugLoc &DL = MI.getDebugLoc();
-
     MachineOperand &Dest = MI.getOperand(0);
     MachineOperand &Src0 = MI.getOperand(1);
     MachineOperand &Src1 = MI.getOperand(2);
-
-    Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
-    Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
-
-    MachineOperand Src0Sub0 = TII->buildExtractSubRegOrImm(
-        MI, MRI, Src0, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass);
-    MachineOperand Src0Sub1 = TII->buildExtractSubRegOrImm(
-        MI, MRI, Src0, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass);
-
-    MachineOperand Src1Sub0 = TII->buildExtractSubRegOrImm(
-        MI, MRI, Src1, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass);
-    MachineOperand Src1Sub1 = TII->buildExtractSubRegOrImm(
-        MI, MRI, Src1, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass);
-
     bool IsAdd = (MI.getOpcode() == AMDGPU::S_ADD_U64_PSEUDO);
-
-    unsigned LoOpc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
-    unsigned HiOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
-    BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0).add(Src0Sub0).add(Src1Sub0);
-    BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1).add(Src0Sub1).add(Src1Sub1);
-    BuildMI(*BB, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), Dest.getReg())
-        .addReg(DestSub0)
-        .addImm(AMDGPU::sub0)
-        .addReg(DestSub1)
-        .addImm(AMDGPU::sub1);
+    if (Subtarget->hasScalarAddSub64()) {
+      unsigned Opc = IsAdd ? AMDGPU::S_ADD_U64 : AMDGPU::S_SUB_U64;
+      BuildMI(*BB, MI, DL, TII->get(Opc), Dest.getReg())
+          .addReg(Src0.getReg())
+          .addReg(Src1.getReg());
+    } else {
+      const SIRegisterInfo *TRI = ST.getRegisterInfo();
+      const TargetRegisterClass *BoolRC = TRI->getBoolRC();
+
+      Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
+      Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
+
+      MachineOperand Src0Sub0 = TII->buildExtractSubRegOrImm(
+          MI, MRI, Src0, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass);
+      MachineOperand Src0Sub1 = TII->buildExtractSubRegOrImm(
+          MI, MRI, Src0, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass);
+
+      MachineOperand Src1Sub0 = TII->buildExtractSubRegOrImm(
+          MI, MRI, Src1, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass);
+      MachineOperand Src1Sub1 = TII->buildExtractSubRegOrImm(
+          MI, MRI, Src1, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass);
+
+      unsigned LoOpc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
+      unsigned HiOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
+      BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0)
+          .add(Src0Sub0)
+          .add(Src1Sub0);
+      BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1)
+          .add(Src0Sub1)
+          .add(Src1Sub1);
+      BuildMI(*BB, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), Dest.getReg())
+          .addReg(DestSub0)
+          .addImm(AMDGPU::sub0)
+          .addReg(DestSub1)
+          .addImm(AMDGPU::sub1);
+    }
     MI.eraseFromParent();
     return BB;
   }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
new file mode 100644
index 000000000000..b850c37c4a28
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
@@ -0,0 +1,107 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX11 %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX12 %s
+
+define amdgpu_kernel void @s_add_u64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
+; GFX11-LABEL: s_add_u64:
+; GFX11:       ; %bb.0: ; %entry
+; GFX11-NEXT:    s_clause 0x1
+; GFX11-NEXT:    s_load_b128 s[4:7], s[0:1], 0x24
+; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x34
+; GFX11-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-NEXT:    s_add_u32 s0, s6, s0
+; GFX11-NEXT:    s_addc_u32 s1, s7, s1
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT:    global_store_b64 v2, v[0:1], s[4:5]
+; GFX11-NEXT:    s_nop 0
+; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT:    s_endpgm
+;
+; GFX12-LABEL: s_add_u64:
+; GFX12:       ; %bb.0: ; %entry
+; GFX12-NEXT:    s_clause 0x1
+; GFX12-NEXT:    s_load_b128 s[4:7], s[0:1], 0x24
+; GFX12-NEXT:    s_load_b64 s[0:1], s[0:1], 0x34
+; GFX12-NEXT:    v_mov_b32_e32 v2, 0
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    s_add_nc_u64 s[0:1], s[6:7], s[0:1]
+; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-NEXT:    global_store_b64 v2, v[0:1], s[4:5]
+; GFX12-NEXT:    s_nop 0
+; GFX12-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-NEXT:    s_endpgm
+entry:
+  %add = add i64 %a, %b
+  store i64 %add, i64 addrspace(1)* %out
+  ret void
+}
+
+define amdgpu_ps void @v_add_u64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
+; GCN-LABEL: v_add_u64:
+; GCN:       ; %bb.0: ; %entry
+; GCN-NEXT:    v_add_co_u32 v2, vcc_lo, v2, v4
+; GCN-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo
+; GCN-NEXT:    global_store_b64 v[0:1], v[2:3], off
+; GCN-NEXT:    s_nop 0
+; GCN-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GCN-NEXT:    s_endpgm
+entry:
+  %add = add i64 %a, %b
+  store i64 %add, i64 addrspace(1)* %out
+  ret void
+}
+
+define amdgpu_kernel void @s_sub_u64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
+; GFX11-LABEL: s_sub_u64:
+; GFX11:       ; %bb.0: ; %entry
+; GFX11-NEXT:    s_clause 0x1
+; GFX11-NEXT:    s_load_b128 s[4:7], s[0:1], 0x24
+; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x34
+; GFX11-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-NEXT:    s_sub_u32 s0, s6, s0
+; GFX11-NEXT:    s_subb_u32 s1, s7, s1
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT:    global_store_b64 v2, v[0:1], s[4:5]
+; GFX11-NEXT:    s_nop 0
+; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT:    s_endpgm
+;
+; GFX12-LABEL: s_sub_u64:
+; GFX12:       ; %bb.0: ; %entry
+; GFX12-NEXT:    s_clause 0x1
+; GFX12-NEXT:    s_load_b128 s[4:7], s[0:1], 0x24
+; GFX12-NEXT:    s_load_b64 s[0:1], s[0:1], 0x34
+; GFX12-NEXT:    v_mov_b32_e32 v2, 0
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    s_sub_nc_u64 s[0:1], s[6:7], s[0:1]
+; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-NEXT:    global_store_b64 v2, v[0:1], s[4:5]
+; GFX12-NEXT:    s_nop 0
+; GFX12-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-NEXT:    s_endpgm
+entry:
+  %sub = sub i64 %a, %b
+  store i64 %sub, i64 addrspace(1)* %out
+  ret void
+}
+
+define amdgpu_ps void @v_sub_u64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
+; GCN-LABEL: v_sub_u64:
+; GCN:       ; %bb.0: ; %entry
+; GCN-NEXT:    v_sub_co_u32 v2, vcc_lo, v2, v4
+; GCN-NEXT:    v_sub_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo
+; GCN-NEXT:    global_store_b64 v[0:1], v[2:3], off
+; GCN-NEXT:    s_nop 0
+; GCN-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GCN-NEXT:    s_endpgm
+entry:
+  %sub = sub i64 %a, %b
+  store i64 %sub, i64 addrspace(1)* %out
+  ret void
+}
diff --git a/llvm/test/CodeGen/AMDGPU/add.ll b/llvm/test/CodeGen/AMDGPU/add.ll
index 4b6891e7aa20..34a676bffcfe 100644
--- a/llvm/test/CodeGen/AMDGPU/add.ll
+++ b/llvm/test/CodeGen/AMDGPU/add.ll
@@ -1,14 +1,89 @@
-; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SIVI,FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SIVI,FUNC %s
-; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,FUNC %s
-; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10,FUNC %s
-; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10,FUNC %s
-
-; FUNC-LABEL: {{^}}s_add_i32:
-; GCN: s_add_i32 s[[REG:[0-9]+]], {{s[0-9]+, s[0-9]+}}
-; GCN: v_mov_b32_e32 v[[V_REG:[0-9]+]], s[[REG]]
-; GCN: buffer_store_{{dword|b32}} v[[V_REG]],
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX6 %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8 %s
+; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s
+; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10 %s
+; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12 %s
+
 define amdgpu_kernel void @s_add_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
+; GFX6-LABEL: s_add_i32:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[2:3], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_mov_b32 s2, -1
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_add_i32 s4, s4, s5
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
+; GFX6-NEXT:    s_endpgm
+;
+; GFX8-LABEL: s_add_i32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:    s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX8-NEXT:    v_mov_b32_e32 v0, s0
+; GFX8-NEXT:    v_mov_b32_e32 v1, s1
+; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:    s_add_i32 s0, s2, s3
+; GFX8-NEXT:    v_mov_b32_e32 v2, s0
+; GFX8-NEXT:    flat_store_dword v[0:1], v2
+; GFX8-NEXT:    s_endpgm
+;
+; GFX9-LABEL: s_add_i32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX9-NEXT:    v_mov_b32_e32 v0, 0
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_add_i32 s2, s2, s3
+; GFX9-NEXT:    v_mov_b32_e32 v1, s2
+; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
+; GFX9-NEXT:    s_endpgm
+;
+; GFX10-LABEL: s_add_i32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX10-NEXT:    v_mov_b32_e32 v0, 0
+; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX10-NEXT:    s_add_i32 s2, s2, s3
+; GFX10-NEXT:    v_mov_b32_e32 v1, s2
+; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]
+; GFX10-NEXT:    s_endpgm
+;
+; GFX11-LABEL: s_add_i32:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_load_b128 s[0:3], s[0:1], 0x24
+; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-NEXT:    s_add_i32 s2, s2, s3
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX11-NEXT:    s_nop 0
+; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT:    s_endpgm
+;
+; GFX12-LABEL: s_add_i32:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    s_load_b128 s[0:3], s[0:1], 0x24
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    s_add_co_i32 s2, s2, s3
+; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX12-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX12-NEXT:    s_nop 0
+; GFX12-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-NEXT:    s_endpgm
   %b_ptr = getelementptr i32, ptr addrspace(1) %in, i32 1
   %a = load i32, ptr addrspace(1) %in
   %b = load i32, ptr addrspace(1) %b_ptr
@@ -17,10 +92,96 @@ define amdgpu_kernel void @s_add_i32(ptr addrspace(1) %out, ptr addrspace(1) %in
   ret void
 }
 
-; FUNC-LABEL: {{^}}s_add_v2i32:
-; GCN: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
-; GCN: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
 define amdgpu_kernel void @s_add_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
+; GFX6-LABEL: s_add_v2i32:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_mov_b32 s2, -1
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_add_i32 s5, s5, s7
+; GFX6-NEXT:    s_add_i32 s4, s4, s6
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NEXT:    s_endpgm
+;
+; GFX8-LABEL: s_add_v2i32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX8-NEXT:    v_mov_b32_e32 v0, s0
+; GFX8-NEXT:    v_mov_b32_e32 v1, s1
+; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:    s_add_i32 s0, s5, s7
+; GFX8-NEXT:    s_add_i32 s1, s4, s6
+; GFX8-NEXT:    v_mov_b32_e32 v2, s1
+; GFX8-NEXT:    v_mov_b32_e32 v3, s0
+; GFX8-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8-NEXT:    s_endpgm
+;
+; GFX9-LABEL: s_add_v2i32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_add_i32 s2, s5, s7
+; GFX9-NEXT:    s_add_i32 s3, s4, s6
+; GFX9-NEXT:    v_mov_b32_e32 v0, s3
+; GFX9-NEXT:    v_mov_b32_e32 v1, s2
+; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX9-NEXT:    s_endpgm
+;
+; GFX10-LABEL: s_add_v2i32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX10-NEXT:    v_mov_b32_e32 v2, 0
+; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX10-NEXT:    s_add_i32 s2, s4, s6
+; GFX10-NEXT:    s_add_i32 s3, s5, s7
+; GFX10-NEXT:    v_mov_b32_e32 v0, s2
+; GFX10-NEXT:    v_mov_b32_e32 v1, s3
+; GFX10-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX10-NEXT:    s_endpgm
+;
+; GFX11-LABEL: s_add_v2i32:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_load_b128 s[0:3], s[0:1], 0x24
+; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-NEXT:    s_load_b128 s[4:7], s[2:3], 0x0
+; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-NEXT:    s_add_i32 s2, s4, s6
+; GFX11-NEXT:    s_add_i32 s3, s5, s7
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT:    v_mov_b32_e32 v0, s2
+; GFX11-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-NEXT:    s_nop 0
+; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT:    s_endpgm
+;
+; GFX12-LABEL: s_add_v2i32:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    s_load_b128 s[0:3], s[0:1], 0x24
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    s_load_b128 s[4:7], s[2:3], 0x0
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    s_add_co_i32 s2, s4, s6
+; GFX12-NEXT:    s_add_co_i32 s3, s5, s7
+; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT:    v_mov_b32_e32 v0, s2
+; GFX12-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
+; GFX12-NEXT:    s_nop 0
+; GFX12-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-NEXT:    s_endpgm
   %b_ptr = getelementptr <2 x i32>, ptr addrspace(1) %in, i32 1
   %a = load <2 x i32>, ptr addrspace(1) %in
   %b = load <2 x i32>, ptr addrspace(1) %b_ptr
@@ -29,12 +190,118 @@ define amdgpu_kernel void @s_add_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %
   ret void
 }
 
-; FUNC-LABEL: {{^}}s_add_v4i32:
-; GCN: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
-; GCN: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
-; GCN: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
-; GCN: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
 define amdgpu_kernel void @s_add_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
+; GFX6-LABEL: s_add_v4i32:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX6-NEXT:    s_mov_b32 s11, 0xf000
+; GFX6-NEXT:    s_mov_b32 s10, -1
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_add_i32 s3, s3, s7
+; GFX6-NEXT:    s_add_i32 s2, s2, s6
+; GFX6-NEXT:    s_add_i32 s1, s1, s5
+; GFX6-NEXT:    s_add_i32 s0, s0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v2, s2
+; GFX6-NEXT:    v_mov_b32_e32 v3, s3
+; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; GFX6-NEXT:    s_endpgm
+;
+; GFX8-LABEL: s_add_v4i32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x24
+; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:    s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX8-NEXT:    v_mov_b32_e32 v4, s8
+; GFX8-NEXT:    v_mov_b32_e32 v5, s9
+; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:    s_add_i32 s3, s3, s7
+; GFX8-NEXT:    s_add_i32 s2, s2, s6
+; GFX8-NEXT:    s_add_i32 s1, s1, s5
+; GFX8-NEXT:    s_add_i32 s0, s0, s4
+; GFX8-NEXT:    v_mov_b32_e32 v0, s0
+; GFX8-NEXT:    v_mov_b32_e32 v1, s1
+; GFX8-NEXT:    v_mov_b32_e32 v2, s2
+; GFX8-NEXT:    v_mov_b32_e32 v3, s3
+; GFX8-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT:    s_endpgm
+;
+; GFX9-LABEL: s_add_v4i32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x24
+; GFX9-NEXT:    v_mov_b32_e32 v4, 0
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_add_i32 s3, s3, s7
+; GFX9-NEXT:    s_add_i32 s2, s2, s6
+; GFX9-NEXT:    s_add_i32 s1, s1, s5
+; GFX9-NEXT:    s_add_i32 s0, s0, s4
+; GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NEXT:    v_mov_b32_e32 v1, s1
+; GFX9-NEXT:    v_mov_b32_e32 v2, s2
+; GFX9-NEXT:    v_mov_b32_e32 v3, s3
+; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[8:9]
+; GFX9-NEXT:    s_endpgm
+;
+; GFX10-LABEL: s_add_v4i32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x24
+; GFX10-NEXT:    v_mov_b32_e32 v4, 0
+; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX10-NEXT:    s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX10-NEXT:    s_add_i32 s3, s3, s7
+; GFX10-NEXT:    s_add_i32 s2, s2, s6
+; GFX10-NEXT:    s_add_i32 s0, s0, s4
+; GFX10-NEXT:    s_add_i32 s1, s1, s5
+; GFX10-NEXT:    v_mov_b32_e32 v0, s0
+; GFX10-NEXT:    v_mov_b32_e32 v1, s1
+; GFX10-NEXT:    v_mov_b32_e32 v2, s2
+; GFX10-NEXT:    v_mov_b32_e32 v3, s3
+; GFX10-NEXT:    global_store_dwordx4 v4, v[0:3], s[8:9]
+; GFX10-NEXT:    s_endpgm
+;
+; GFX11-LABEL: s_add_v4i32:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_load_b128 s[8:11], s[0:1], 0x24
+; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-NEXT:    s_load_b256 s[0:7], s[10:11], 0x0
+; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-NEXT:    s_add_i32 s3, s3, s7
+; GFX11-NEXT:    s_add_i32 s2, s2, s6
+; GFX11-NEXT:    s_add_i32 s0, s0, s4
+; GFX11-NEXT:    s_add_i32 s1, s1, s5
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
+; GFX11-NEXT:    v_mov_b32_e32 v2, s2
+; GFX11-NEXT:    global_store_b128 v4, v[0:3], s[8:9]
+; GFX11-NEXT:    s_nop 0
+; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT:    s_endpgm
+;
+; GFX12-LABEL: s_add_v4i32:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    s_load_b128 s[8:11], s[0:1], 0x24
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    s_load_b256 s[0:7], s[10:11], 0x0
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    s_add_co_i32 s3, s3, s7
+; GFX12-NEXT:    s_add_co_i32 s2, s2, s6
+; GFX12-NEXT:    s_add_co_i32 s0, s0, s4
+; GFX12-NEXT:    s_add_co_i32 s1, s1, s5
+; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT:    v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s1
+; GFX12-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
+; GFX12-NEXT:    v_mov_b32_e32 v2, s2
+; GFX12-NEXT:    global_store_b128 v4, v[0:3], s[8:9]
+; GFX12-NEXT:    s_nop 0
+; GFX12-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-NEXT:    s_endpgm
   %b_ptr = getelementptr <4 x i32>, ptr addrspace(1) %in, i32 1
   %a = load <4 x i32>, ptr addrspace(1) %in
   %b = load <4 x i32>, ptr addrspace(1) %b_ptr
@@ -43,53 +310,565 @@ define amdgpu_kernel void @s_add_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %
   ret void
 }
 
-; FUNC-LABEL: {{^}}s_add_v8i32:
-; GCN: s_add_i32
-; GCN: s_add_i32
-; GCN: s_add_i32
-; GCN: s_add_i32
-; GCN: s_add_i32
-; GCN: s_add_i32
-; GCN: s_add_i32
-; GCN: s_add_i32
 define amdgpu_kernel void @s_add_v8i32(ptr addrspace(1) %out, <8 x i32> %a, <8 x i32> %b) {
+; GFX6-LABEL: s_add_v8i32:
+; GFX6:       ; %bb.0: ; %entry
+; GFX6-NEXT:    s_load_dwordx16 s[4:19], s[0:1], 0x11
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_mov_b32 s2, -1
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_add_i32 s11, s11, s19
+; GFX6-NEXT:    s_add_i32 s10, s10, s18
+; GFX6-NEXT:    s_add_i32 s9, s9, s17
+; GFX6-NEXT:    s_add_i32 s8, s8, s16
+; GFX6-NEXT:    s_add_i32 s7, s7, s15
+; GFX6-NEXT:    s_add_i32 s6, s6, s14
+; GFX6-NEXT:    s_add_i32 s5, s5, s13
+; GFX6-NEXT:    s_add_i32 s4, s4, s12
+; GFX6-NEXT:    v_mov_b32_e32 v0, s8
+; GFX6-NEXT:    v_mov_b32_e32 v1, s9
+; GFX6-NEXT:    v_mov_b32_e32 v2, s10
+; GFX6-NEXT:    v_mov_b32_e32 v3, s11
+; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NEXT:    s_waitcnt expcnt(0)
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    v_mov_b32_e32 v2, s6
+; GFX6-NEXT:    v_mov_b32_e32 v3, s7
+; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NEXT:    s_endpgm
+;
+; GFX8-LABEL: s_add_v8i32:
+; GFX8:       ; %bb.0: ; %entry
+; GFX8-NEXT:    s_load_dwordx16 s[4:19], s[0:1], 0x44
+; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:    s_add_i32 s7, s7, s15
+; GFX8-NEXT:    s_add_i32 s6, s6, s14
+; GFX8-NEXT:    s_add_i32 s5, s5, s13
+; GFX8-NEXT:    s_add_i32 s4, s4, s12
+; GFX8-NEXT:    s_add_i32 s2, s11, s19
+; GFX8-NEXT:    s_add_i32 s3, s10, s18
+; GFX8-NEXT:    s_add_i32 s9, s9, s17
+; GFX8-NEXT:    s_add_i32 s8, s8, s16
+; GFX8-NEXT:    v_mov_b32_e32 v3, s2
+; GFX8-NEXT:    s_add_u32 s2, s0, 16
+; GFX8-NEXT:    v_mov_b32_e32 v2, s3
+; GFX8-NEXT:    s_addc_u32 s3, s1, 0
+; GFX8-NEXT:    v_mov_b32_e32 v5, s3
+; GFX8-NEXT:    v_mov_b32_e32 v0, s8
+; GFX8-NEXT:    v_mov_b32_e32 v1, s9
+; GFX8-NEXT:    v_mov_b32_e32 v4, s2
+; GFX8-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT:    v_mov_b32_e32 v5, s1
+; GFX8-NEXT:    v_mov_b32_e32 v0, s4
+; GFX8-NEXT:    v_mov_b32_e32 v1, s5
+; GFX8-NEXT:    v_mov_b32_e32 v2, s6
+; GFX8-NEXT:    v_mov_b32_e32 v3, s7
+; GFX8-NEXT:    v_mov_b32_e32 v4, s0
+; GFX8-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT:    s_endpgm
+;
+; GFX9-LABEL: s_add_v8i32:
+; GFX9:       ; %bb.0: ; %entry
+; GFX9-NEXT:    s_load_dwordx16 s[4:19], s[0:1], 0x44
+; GFX9-NEXT:    v_mov_b32_e32 v4, 0
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_add_i32 s2, s7, s15
+; GFX9-NEXT:    s_add_i32 s3, s6, s14
+; GFX9-NEXT:    s_add_i32 s6, s11, s19
+; GFX9-NEXT:    s_add_i32 s7, s10, s18
+; GFX9-NEXT:    s_add_i32 s9, s9, s17
+; GFX9-NEXT:    s_add_i32 s8, s8, s16
+; GFX9-NEXT:    s_add_i32 s5, s5, s13
+; GFX9-NEXT:    s_add_i32 s4, s4, s12
+; GFX9-NEXT:    v_mov_b32_e32 v0, s8
+; GFX9-NEXT:    v_mov_b32_e32 v1, s9
+; GFX9-NEXT:    v_mov_b32_e32 v2, s7
+; GFX9-NEXT:    v_mov_b32_e32 v3, s6
+; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1] offset:16
+; GFX9-NEXT:    s_nop 0
+; GFX9-NEXT:    v_mov_b32_e32 v0, s4
+; GFX9-NEXT:    v_mov_b32_e32 v1, s5
+; GFX9-NEXT:    v_mov_b32_e32 v2, s3
+; GFX9-NEXT:    v_mov_b32_e32 v3, s2
+; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
+; GFX9-NEXT:    s_endpgm
+;
+; GFX10-LABEL: s_add_v8i32:
+; GFX10:       ; %bb.0: ; %entry
+; GFX10-NEXT:    s_load_dwordx16 s[4:19], s[0:1], 0x44
+; GFX10-NEXT:    v_mov_b32_e32 v8, 0
+; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX10-NEXT:    s_add_i32 s2, s7, s15
+; GFX10-NEXT:    s_add_i32 s3, s6, s14
+; GFX10-NEXT:    s_add_i32 s6, s11, s19
+; GFX10-NEXT:    s_add_i32 s7, s10, s18
+; GFX10-NEXT:    s_add_i32 s8, s8, s16
+; GFX10-NEXT:    s_add_i32 s9, s9, s17
+; GFX10-NEXT:    s_add_i32 s5, s5, s13
+; GFX10-NEXT:    s_add_i32 s4, s4, s12
+; GFX10-NEXT:    v_mov_b32_e32 v0, s8
+; GFX10-NEXT:    v_mov_b32_e32 v1, s9
+; GFX10-NEXT:    v_mov_b32_e32 v2, s7
+; GFX10-NEXT:    v_mov_b32_e32 v3, s6
+; GFX10-NEXT:    v_mov_b32_e32 v4, s4
+; GFX10-NEXT:    v_mov_b32_e32 v5, s5
+; GFX10-NEXT:    v_mov_b32_e32 v6, s3
+; GFX10-NEXT:    v_mov_b32_e32 v7, s2
+; GFX10-NEXT:    global_store_dwordx4 v8, v[0:3], s[0:1] offset:16
+; GFX10-NEXT:    global_store_dwordx4 v8, v[4:7], s[0:1]
+; GFX10-NEXT:    s_endpgm
+;
+; GFX11-LABEL: s_add_v8i32:
+; GFX11:       ; %bb.0: ; %entry
+; GFX11-NEXT:    s_clause 0x1
+; GFX11-NEXT:    s_load_b512 s[4:19], s[0:1], 0x44
+; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-NEXT:    s_add_i32 s2, s7, s15
+; GFX11-NEXT:    s_add_i32 s3, s6, s14
+; GFX11-NEXT:    s_add_i32 s6, s11, s19
+; GFX11-NEXT:    s_add_i32 s7, s10, s18
+; GFX11-NEXT:    s_add_i32 s8, s8, s16
+; GFX11-NEXT:    s_add_i32 s9, s9, s17
+; GFX11-NEXT:    s_add_i32 s5, s5, s13
+; GFX11-NEXT:    s_add_i32 s4, s4, s12
+; GFX11-NEXT:    v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v1, s9
+; GFX11-NEXT:    v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s6
+; GFX11-NEXT:    v_dual_mov_b32 v2, s7 :: v_dual_mov_b32 v5, s5
+; GFX11-NEXT:    v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v7, s2
+; GFX11-NEXT:    v_mov_b32_e32 v6, s3
+; GFX11-NEXT:    s_clause 0x1
+; GFX11-NEXT:    global_store_b128 v8, v[0:3], s[0:1] offset:16
+; GFX11-NEXT:    global_store_b128 v8, v[4:7], s[0:1]
+; GFX11-NEXT:    s_nop 0
+; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT:    s_endpgm
+;
+; GFX12-LABEL: s_add_v8i32:
+; GFX12:       ; %bb.0: ; %entry
+; GFX12-NEXT:    s_clause 0x1
+; GFX12-NEXT:    s_load_b512 s[4:19], s[0:1], 0x44
+; GFX12-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    s_add_co_i32 s2, s7, s15
+; GFX12-NEXT:    s_add_co_i32 s3, s6, s14
+; GFX12-NEXT:    s_add_co_i32 s6, s11, s19
+; GFX12-NEXT:    s_add_co_i32 s7, s10, s18
+; GFX12-NEXT:    s_add_co_i32 s8, s8, s16
+; GFX12-NEXT:    s_add_co_i32 s9, s9, s17
+; GFX12-NEXT:    s_add_co_i32 s5, s5, s13
+; GFX12-NEXT:    s_add_co_i32 s4, s4, s12
+; GFX12-NEXT:    v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v1, s9
+; GFX12-NEXT:    v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s6
+; GFX12-NEXT:    v_dual_mov_b32 v2, s7 :: v_dual_mov_b32 v5, s5
+; GFX12-NEXT:    v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v7, s2
+; GFX12-NEXT:    v_mov_b32_e32 v6, s3
+; GFX12-NEXT:    s_clause 0x1
+; GFX12-NEXT:    global_store_b128 v8, v[0:3], s[0:1] offset:16
+; GFX12-NEXT:    global_store_b128 v8, v[4:7], s[0:1]
+; GFX12-NEXT:    s_nop 0
+; GFX12-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-NEXT:    s_endpgm
 entry:
   %0 = add <8 x i32> %a, %b
   store <8 x i32> %0, ptr addrspace(1) %out
   ret void
 }
 
-; FUNC-LABEL: {{^}}s_add_v16i32:
-; GCN: s_add_i32
-; GCN: s_add_i32
-; GCN: s_add_i32
-; GCN: s_add_i32
-; GCN: s_add_i32
-; GCN: s_add_i32
-; GCN: s_add_i32
-; GCN: s_add_i32
-; GCN: s_add_i32
-; GCN: s_add_i32
-; GCN: s_add_i32
-; GCN: s_add_i32
-; GCN: s_add_i32
-; GCN: s_add_i32
-; GCN: s_add_i32
-; GCN: s_add_i32
 define amdgpu_kernel void @s_add_v16i32(ptr addrspace(1) %out, <16 x i32> %a, <16 x i32> %b) {
+; GFX6-LABEL: s_add_v16i32:
+; GFX6:       ; %bb.0: ; %entry
+; GFX6-NEXT:    s_load_dwordx16 s[4:19], s[0:1], 0x19
+; GFX6-NEXT:    s_load_dwordx16 s[36:51], s[0:1], 0x29
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_mov_b32 s2, -1
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_add_i32 s19, s19, s51
+; GFX6-NEXT:    s_add_i32 s18, s18, s50
+; GFX6-NEXT:    s_add_i32 s17, s17, s49
+; GFX6-NEXT:    s_add_i32 s16, s16, s48
+; GFX6-NEXT:    s_add_i32 s15, s15, s47
+; GFX6-NEXT:    s_add_i32 s14, s14, s46
+; GFX6-NEXT:    s_add_i32 s13, s13, s45
+; GFX6-NEXT:    s_add_i32 s12, s12, s44
+; GFX6-NEXT:    v_mov_b32_e32 v0, s16
+; GFX6-NEXT:    v_mov_b32_e32 v1, s17
+; GFX6-NEXT:    v_mov_b32_e32 v2, s18
+; GFX6-NEXT:    v_mov_b32_e32 v3, s19
+; GFX6-NEXT:    s_add_i32 s11, s11, s43
+; GFX6-NEXT:    s_add_i32 s10, s10, s42
+; GFX6-NEXT:    s_add_i32 s9, s9, s41
+; GFX6-NEXT:    s_add_i32 s8, s8, s40
+; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
+; GFX6-NEXT:    s_waitcnt expcnt(0)
+; GFX6-NEXT:    v_mov_b32_e32 v0, s12
+; GFX6-NEXT:    v_mov_b32_e32 v1, s13
+; GFX6-NEXT:    v_mov_b32_e32 v2, s14
+; GFX6-NEXT:    v_mov_b32_e32 v3, s15
+; GFX6-NEXT:    s_add_i32 s7, s7, s39
+; GFX6-NEXT:    s_add_i32 s6, s6, s38
+; GFX6-NEXT:    s_add_i32 s5, s5, s37
+; GFX6-NEXT:    s_add_i32 s4, s4, s36
+; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
+; GFX6-NEXT:    s_waitcnt expcnt(0)
+; GFX6-NEXT:    v_mov_b32_e32 v0, s8
+; GFX6-NEXT:    v_mov_b32_e32 v1, s9
+; GFX6-NEXT:    v_mov_b32_e32 v2, s10
+; GFX6-NEXT:    v_mov_b32_e32 v3, s11
+; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NEXT:    s_waitcnt expcnt(0)
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    v_mov_b32_e32 v2, s6
+; GFX6-NEXT:    v_mov_b32_e32 v3, s7
+; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NEXT:    s_endpgm
+;
+; GFX8-LABEL: s_add_v16i32:
+; GFX8:       ; %bb.0: ; %entry
+; GFX8-NEXT:    s_load_dwordx16 s[4:19], s[0:1], 0x64
+; GFX8-NEXT:    s_load_dwordx16 s[36:51], s[0:1], 0xa4
+; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:    s_add_i32 s7, s7, s39
+; GFX8-NEXT:    s_add_i32 s6, s6, s38
+; GFX8-NEXT:    s_add_i32 s5, s5, s37
+; GFX8-NEXT:    s_add_i32 s4, s4, s36
+; GFX8-NEXT:    s_add_i32 s11, s11, s43
+; GFX8-NEXT:    s_add_i32 s10, s10, s42
+; GFX8-NEXT:    s_add_i32 s9, s9, s41
+; GFX8-NEXT:    s_add_i32 s8, s8, s40
+; GFX8-NEXT:    s_add_i32 s15, s15, s47
+; GFX8-NEXT:    s_add_i32 s14, s14, s46
+; GFX8-NEXT:    s_add_i32 s13, s13, s45
+; GFX8-NEXT:    s_add_i32 s12, s12, s44
+; GFX8-NEXT:    s_add_i32 s2, s19, s51
+; GFX8-NEXT:    s_add_i32 s3, s18, s50
+; GFX8-NEXT:    s_add_i32 s17, s17, s49
+; GFX8-NEXT:    s_add_i32 s16, s16, s48
+; GFX8-NEXT:    v_mov_b32_e32 v3, s2
+; GFX8-NEXT:    s_add_u32 s2, s0, 48
+; GFX8-NEXT:    v_mov_b32_e32 v2, s3
+; GFX8-NEXT:    s_addc_u32 s3, s1, 0
+; GFX8-NEXT:    v_mov_b32_e32 v5, s3
+; GFX8-NEXT:    v_mov_b32_e32 v4, s2
+; GFX8-NEXT:    s_add_u32 s2, s0, 32
+; GFX8-NEXT:    v_mov_b32_e32 v0, s16
+; GFX8-NEXT:    v_mov_b32_e32 v1, s17
+; GFX8-NEXT:    s_addc_u32 s3, s1, 0
+; GFX8-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT:    v_mov_b32_e32 v5, s3
+; GFX8-NEXT:    v_mov_b32_e32 v4, s2
+; GFX8-NEXT:    s_add_u32 s2, s0, 16
+; GFX8-NEXT:    v_mov_b32_e32 v0, s12
+; GFX8-NEXT:    v_mov_b32_e32 v1, s13
+; GFX8-NEXT:    v_mov_b32_e32 v2, s14
+; GFX8-NEXT:    v_mov_b32_e32 v3, s15
+; GFX8-NEXT:    s_addc_u32 s3, s1, 0
+; GFX8-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT:    v_mov_b32_e32 v5, s3
+; GFX8-NEXT:    v_mov_b32_e32 v0, s8
+; GFX8-NEXT:    v_mov_b32_e32 v1, s9
+; GFX8-NEXT:    v_mov_b32_e32 v2, s10
+; GFX8-NEXT:    v_mov_b32_e32 v3, s11
+; GFX8-NEXT:    v_mov_b32_e32 v4, s2
+; GFX8-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT:    v_mov_b32_e32 v5, s1
+; GFX8-NEXT:    v_mov_b32_e32 v0, s4
+; GFX8-NEXT:    v_mov_b32_e32 v1, s5
+; GFX8-NEXT:    v_mov_b32_e32 v2, s6
+; GFX8-NEXT:    v_mov_b32_e32 v3, s7
+; GFX8-NEXT:    v_mov_b32_e32 v4, s0
+; GFX8-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT:    s_endpgm
+;
+; GFX9-LABEL: s_add_v16i32:
+; GFX9:       ; %bb.0: ; %entry
+; GFX9-NEXT:    s_load_dwordx16 s[4:19], s[0:1], 0x64
+; GFX9-NEXT:    s_load_dwordx16 s[36:51], s[0:1], 0xa4
+; GFX9-NEXT:    v_mov_b32_e32 v4, 0
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_add_i32 s2, s7, s39
+; GFX9-NEXT:    s_add_i32 s3, s6, s38
+; GFX9-NEXT:    s_add_i32 s6, s11, s43
+; GFX9-NEXT:    s_add_i32 s7, s10, s42
+; GFX9-NEXT:    s_add_i32 s10, s15, s47
+; GFX9-NEXT:    s_add_i32 s11, s14, s46
+; GFX9-NEXT:    s_add_i32 s14, s19, s51
+; GFX9-NEXT:    s_add_i32 s15, s18, s50
+; GFX9-NEXT:    s_add_i32 s17, s17, s49
+; GFX9-NEXT:    s_add_i32 s16, s16, s48
+; GFX9-NEXT:    s_add_i32 s13, s13, s45
+; GFX9-NEXT:    s_add_i32 s12, s12, s44
+; GFX9-NEXT:    v_mov_b32_e32 v0, s16
+; GFX9-NEXT:    v_mov_b32_e32 v1, s17
+; GFX9-NEXT:    v_mov_b32_e32 v2, s15
+; GFX9-NEXT:    v_mov_b32_e32 v3, s14
+; GFX9-NEXT:    s_add_i32 s9, s9, s41
+; GFX9-NEXT:    s_add_i32 s8, s8, s40
+; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1] offset:48
+; GFX9-NEXT:    s_add_i32 s5, s5, s37
+; GFX9-NEXT:    v_mov_b32_e32 v0, s12
+; GFX9-NEXT:    v_mov_b32_e32 v1, s13
+; GFX9-NEXT:    v_mov_b32_e32 v2, s11
+; GFX9-NEXT:    v_mov_b32_e32 v3, s10
+; GFX9-NEXT:    s_add_i32 s4, s4, s36
+; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1] offset:32
+; GFX9-NEXT:    s_nop 0
+; GFX9-NEXT:    v_mov_b32_e32 v0, s8
+; GFX9-NEXT:    v_mov_b32_e32 v1, s9
+; GFX9-NEXT:    v_mov_b32_e32 v2, s7
+; GFX9-NEXT:    v_mov_b32_e32 v3, s6
+; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1] offset:16
+; GFX9-NEXT:    s_nop 0
+; GFX9-NEXT:    v_mov_b32_e32 v0, s4
+; GFX9-NEXT:    v_mov_b32_e32 v1, s5
+; GFX9-NEXT:    v_mov_b32_e32 v2, s3
+; GFX9-NEXT:    v_mov_b32_e32 v3, s2
+; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
+; GFX9-NEXT:    s_endpgm
+;
+; GFX10-LABEL: s_add_v16i32:
+; GFX10:       ; %bb.0: ; %entry
+; GFX10-NEXT:    s_clause 0x1
+; GFX10-NEXT:    s_load_dwordx16 s[4:19], s[0:1], 0x64
+; GFX10-NEXT:    s_load_dwordx16 s[36:51], s[0:1], 0xa4
+; GFX10-NEXT:    v_mov_b32_e32 v16, 0
+; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX10-NEXT:    s_add_i32 s2, s7, s39
+; GFX10-NEXT:    s_add_i32 s3, s6, s38
+; GFX10-NEXT:    s_add_i32 s6, s11, s43
+; GFX10-NEXT:    s_add_i32 s7, s10, s42
+; GFX10-NEXT:    s_add_i32 s10, s15, s47
+; GFX10-NEXT:    s_add_i32 s11, s14, s46
+; GFX10-NEXT:    s_add_i32 s14, s19, s51
+; GFX10-NEXT:    s_add_i32 s15, s18, s50
+; GFX10-NEXT:    s_add_i32 s16, s16, s48
+; GFX10-NEXT:    s_add_i32 s17, s17, s49
+; GFX10-NEXT:    s_add_i32 s13, s13, s45
+; GFX10-NEXT:    s_add_i32 s12, s12, s44
+; GFX10-NEXT:    s_add_i32 s9, s9, s41
+; GFX10-NEXT:    s_add_i32 s8, s8, s40
+; GFX10-NEXT:    v_mov_b32_e32 v0, s16
+; GFX10-NEXT:    v_mov_b32_e32 v1, s17
+; GFX10-NEXT:    v_mov_b32_e32 v2, s15
+; GFX10-NEXT:    v_mov_b32_e32 v3, s14
+; GFX10-NEXT:    s_add_i32 s5, s5, s37
+; GFX10-NEXT:    s_add_i32 s4, s4, s36
+; GFX10-NEXT:    v_mov_b32_e32 v4, s12
+; GFX10-NEXT:    v_mov_b32_e32 v5, s13
+; GFX10-NEXT:    v_mov_b32_e32 v6, s11
+; GFX10-NEXT:    v_mov_b32_e32 v7, s10
+; GFX10-NEXT:    v_mov_b32_e32 v8, s8
+; GFX10-NEXT:    v_mov_b32_e32 v9, s9
+; GFX10-NEXT:    v_mov_b32_e32 v10, s7
+; GFX10-NEXT:    v_mov_b32_e32 v11, s6
+; GFX10-NEXT:    v_mov_b32_e32 v12, s4
+; GFX10-NEXT:    v_mov_b32_e32 v13, s5
+; GFX10-NEXT:    v_mov_b32_e32 v14, s3
+; GFX10-NEXT:    v_mov_b32_e32 v15, s2
+; GFX10-NEXT:    global_store_dwordx4 v16, v[0:3], s[0:1] offset:48
+; GFX10-NEXT:    global_store_dwordx4 v16, v[4:7], s[0:1] offset:32
+; GFX10-NEXT:    global_store_dwordx4 v16, v[8:11], s[0:1] offset:16
+; GFX10-NEXT:    global_store_dwordx4 v16, v[12:15], s[0:1]
+; GFX10-NEXT:    s_endpgm
+;
+; GFX11-LABEL: s_add_v16i32:
+; GFX11:       ; %bb.0: ; %entry
+; GFX11-NEXT:    s_clause 0x2
+; GFX11-NEXT:    s_load_b512 s[4:19], s[0:1], 0x64
+; GFX11-NEXT:    s_load_b512 s[36:51], s[0:1], 0xa4
+; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-NEXT:    s_add_i32 s2, s7, s39
+; GFX11-NEXT:    s_add_i32 s3, s6, s38
+; GFX11-NEXT:    s_add_i32 s6, s11, s43
+; GFX11-NEXT:    s_add_i32 s7, s10, s42
+; GFX11-NEXT:    s_add_i32 s10, s15, s47
+; GFX11-NEXT:    s_add_i32 s11, s14, s46
+; GFX11-NEXT:    s_add_i32 s14, s19, s51
+; GFX11-NEXT:    s_add_i32 s15, s18, s50
+; GFX11-NEXT:    s_add_i32 s16, s16, s48
+; GFX11-NEXT:    s_add_i32 s17, s17, s49
+; GFX11-NEXT:    s_add_i32 s13, s13, s45
+; GFX11-NEXT:    s_add_i32 s12, s12, s44
+; GFX11-NEXT:    v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v1, s17
+; GFX11-NEXT:    s_add_i32 s9, s9, s41
+; GFX11-NEXT:    s_add_i32 s8, s8, s40
+; GFX11-NEXT:    v_dual_mov_b32 v0, s16 :: v_dual_mov_b32 v3, s14
+; GFX11-NEXT:    v_dual_mov_b32 v2, s15 :: v_dual_mov_b32 v5, s13
+; GFX11-NEXT:    s_add_i32 s5, s5, s37
+; GFX11-NEXT:    s_add_i32 s4, s4, s36
+; GFX11-NEXT:    v_dual_mov_b32 v4, s12 :: v_dual_mov_b32 v7, s10
+; GFX11-NEXT:    v_dual_mov_b32 v6, s11 :: v_dual_mov_b32 v9, s9
+; GFX11-NEXT:    v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v11, s6
+; GFX11-NEXT:    v_dual_mov_b32 v10, s7 :: v_dual_mov_b32 v13, s5
+; GFX11-NEXT:    v_dual_mov_b32 v12, s4 :: v_dual_mov_b32 v15, s2
+; GFX11-NEXT:    v_mov_b32_e32 v14, s3
+; GFX11-NEXT:    s_clause 0x3
+; GFX11-NEXT:    global_store_b128 v16, v[0:3], s[0:1] offset:48
+; GFX11-NEXT:    global_store_b128 v16, v[4:7], s[0:1] offset:32
+; GFX11-NEXT:    global_store_b128 v16, v[8:11], s[0:1] offset:16
+; GFX11-NEXT:    global_store_b128 v16, v[12:15], s[0:1]
+; GFX11-NEXT:    s_nop 0
+; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT:    s_endpgm
+;
+; GFX12-LABEL: s_add_v16i32:
+; GFX12:       ; %bb.0: ; %entry
+; GFX12-NEXT:    s_clause 0x2
+; GFX12-NEXT:    s_load_b512 s[4:19], s[0:1], 0x64
+; GFX12-NEXT:    s_load_b512 s[36:51], s[0:1], 0xa4
+; GFX12-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    s_add_co_i32 s2, s7, s39
+; GFX12-NEXT:    s_add_co_i32 s3, s6, s38
+; GFX12-NEXT:    s_add_co_i32 s6, s11, s43
+; GFX12-NEXT:    s_add_co_i32 s7, s10, s42
+; GFX12-NEXT:    s_add_co_i32 s10, s15, s47
+; GFX12-NEXT:    s_add_co_i32 s11, s14, s46
+; GFX12-NEXT:    s_add_co_i32 s14, s19, s51
+; GFX12-NEXT:    s_add_co_i32 s15, s18, s50
+; GFX12-NEXT:    s_add_co_i32 s16, s16, s48
+; GFX12-NEXT:    s_add_co_i32 s17, s17, s49
+; GFX12-NEXT:    s_add_co_i32 s13, s13, s45
+; GFX12-NEXT:    s_add_co_i32 s12, s12, s44
+; GFX12-NEXT:    v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v1, s17
+; GFX12-NEXT:    s_add_co_i32 s9, s9, s41
+; GFX12-NEXT:    s_add_co_i32 s8, s8, s40
+; GFX12-NEXT:    v_dual_mov_b32 v0, s16 :: v_dual_mov_b32 v3, s14
+; GFX12-NEXT:    v_dual_mov_b32 v2, s15 :: v_dual_mov_b32 v5, s13
+; GFX12-NEXT:    s_add_co_i32 s5, s5, s37
+; GFX12-NEXT:    s_add_co_i32 s4, s4, s36
+; GFX12-NEXT:    v_dual_mov_b32 v4, s12 :: v_dual_mov_b32 v7, s10
+; GFX12-NEXT:    v_dual_mov_b32 v6, s11 :: v_dual_mov_b32 v9, s9
+; GFX12-NEXT:    v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v11, s6
+; GFX12-NEXT:    v_dual_mov_b32 v10, s7 :: v_dual_mov_b32 v13, s5
+; GFX12-NEXT:    v_dual_mov_b32 v12, s4 :: v_dual_mov_b32 v15, s2
+; GFX12-NEXT:    v_mov_b32_e32 v14, s3
+; GFX12-NEXT:    s_clause 0x3
+; GFX12-NEXT:    global_store_b128 v16, v[0:3], s[0:1] offset:48
+; GFX12-NEXT:    global_store_b128 v16, v[4:7], s[0:1] offset:32
+; GFX12-NEXT:    global_store_b128 v16, v[8:11], s[0:1] offset:16
+; GFX12-NEXT:    global_store_b128 v16, v[12:15], s[0:1]
+; GFX12-NEXT:    s_nop 0
+; GFX12-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-NEXT:    s_endpgm
 entry:
   %0 = add <16 x i32> %a, %b
   store <16 x i32> %0, ptr addrspace(1) %out
   ret void
 }
 
-; FUNC-LABEL: {{^}}v_add_i32:
-; GCN: {{buffer|flat|global}}_load_{{dword|b32}} [[A:v[0-9]+]]
-; GCN: {{buffer|flat|global}}_load_{{dword|b32}} [[B:v[0-9]+]]
-; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc, [[A]], [[B]]
-; GFX9: v_add_u32_e32 v{{[0-9]+}}, [[A]], [[B]]
-; GFX10: v_add_nc_u32_e32 v{{[0-9]+}}, [[A]], [[B]]
 define amdgpu_kernel void @v_add_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
+; GFX6-LABEL: v_add_i32:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT:    s_mov_b32 s7, 0xf000
+; GFX6-NEXT:    s_mov_b32 s10, 0
+; GFX6-NEXT:    s_mov_b32 s11, s7
+; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_mov_b64 s[8:9], s[2:3]
+; GFX6-NEXT:    v_mov_b32_e32 v1, 0
+; GFX6-NEXT:    buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 glc
+; GFX6-NEXT:    s_waitcnt vmcnt(0)
+; GFX6-NEXT:    buffer_load_dword v0, v[0:1], s[8:11], 0 addr64 offset:4 glc
+; GFX6-NEXT:    s_waitcnt vmcnt(0)
+; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_mov_b32 s4, s0
+; GFX6-NEXT:    s_mov_b32 s5, s1
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    s_endpgm
+;
+; GFX8-LABEL: v_add_i32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:    v_mov_b32_e32 v1, s3
+; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s2, v0
+; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, 4, v0
+; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
+; GFX8-NEXT:    flat_load_dword v4, v[0:1] glc
+; GFX8-NEXT:    s_waitcnt vmcnt(0)
+; GFX8-NEXT:    flat_load_dword v2, v[2:3] glc
+; GFX8-NEXT:    s_waitcnt vmcnt(0)
+; GFX8-NEXT:    v_mov_b32_e32 v0, s0
+; GFX8-NEXT:    v_mov_b32_e32 v1, s1
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v4, v2
+; GFX8-NEXT:    flat_store_dword v[0:1], v2
+; GFX8-NEXT:    s_endpgm
+;
+; GFX9-LABEL: v_add_i32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v1, v0, s[2:3] glc
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    global_load_dword v2, v0, s[2:3] offset:4 glc
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v0, 0
+; GFX9-NEXT:    v_add_u32_e32 v1, v1, v2
+; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
+; GFX9-NEXT:    s_endpgm
+;
+; GFX10-LABEL: v_add_i32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v1, v0, s[2:3] glc dlc
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    global_load_dword v2, v0, s[2:3] offset:4 glc dlc
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_mov_b32_e32 v0, 0
+; GFX10-NEXT:    v_add_nc_u32_e32 v1, v1, v2
+; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]
+; GFX10-NEXT:    s_endpgm
+;
+; GFX11-LABEL: v_add_i32:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_load_b128 s[0:3], s[0:1], 0x24
+; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-NEXT:    global_load_b32 v1, v0, s[2:3] glc dlc
+; GFX11-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-NEXT:    global_load_b32 v0, v0, s[2:3] offset:4 glc dlc
+; GFX11-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-NEXT:    v_add_nc_u32_e32 v0, v1, v0
+; GFX11-NEXT:    global_store_b32 v2, v0, s[0:1]
+; GFX11-NEXT:    s_nop 0
+; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT:    s_endpgm
+;
+; GFX12-LABEL: v_add_i32:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    s_load_b128 s[0:3], s[0:1], 0x24
+; GFX12-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX12-NEXT:    v_mov_b32_e32 v2, 0
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    global_load_b32 v1, v0, s[2:3] th:TH_LOAD_RT_NT
+; GFX12-NEXT:    s_waitcnt vmcnt(0)
+; GFX12-NEXT:    global_load_b32 v0, v0, s[2:3] offset:4 th:TH_LOAD_RT_NT
+; GFX12-NEXT:    s_waitcnt vmcnt(0)
+; GFX12-NEXT:    v_add_nc_u32_e32 v0, v1, v0
+; GFX12-NEXT:    global_store_b32 v2, v0, s[0:1]
+; GFX12-NEXT:    s_nop 0
+; GFX12-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %gep = getelementptr inbounds i32, ptr addrspace(1) %in, i32 %tid
   %b_ptr = getelementptr i32, ptr addrspace(1) %gep, i32 1
@@ -100,12 +879,91 @@ define amdgpu_kernel void @v_add_i32(ptr addrspace(1) %out, ptr addrspace(1) %in
   ret void
 }
 
-; FUNC-LABEL: {{^}}v_add_imm_i32:
-; GCN: {{buffer|flat|global}}_load_{{dword|b32}} [[A:v[0-9]+]]
-; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc, 0x7b, [[A]]
-; GFX9: v_add_u32_e32 v{{[0-9]+}}, 0x7b, [[A]]
-; GFX10: v_add_nc_u32_e32 v{{[0-9]+}}, 0x7b, [[A]]
 define amdgpu_kernel void @v_add_imm_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
+; GFX6-LABEL: v_add_imm_i32:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT:    s_mov_b32 s7, 0xf000
+; GFX6-NEXT:    s_mov_b32 s10, 0
+; GFX6-NEXT:    s_mov_b32 s11, s7
+; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_mov_b64 s[8:9], s[2:3]
+; GFX6-NEXT:    v_mov_b32_e32 v1, 0
+; GFX6-NEXT:    buffer_load_dword v0, v[0:1], s[8:11], 0 addr64 glc
+; GFX6-NEXT:    s_waitcnt vmcnt(0)
+; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_mov_b32 s4, s0
+; GFX6-NEXT:    s_mov_b32 s5, s1
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, 0x7b, v0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    s_endpgm
+;
+; GFX8-LABEL: v_add_imm_i32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:    v_mov_b32_e32 v1, s3
+; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s2, v0
+; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; GFX8-NEXT:    flat_load_dword v2, v[0:1] glc
+; GFX8-NEXT:    s_waitcnt vmcnt(0)
+; GFX8-NEXT:    v_mov_b32_e32 v0, s0
+; GFX8-NEXT:    v_mov_b32_e32 v1, s1
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, 0x7b, v2
+; GFX8-NEXT:    flat_store_dword v[0:1], v2
+; GFX8-NEXT:    s_endpgm
+;
+; GFX9-LABEL: v_add_imm_i32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX9-NEXT:    v_mov_b32_e32 v1, 0
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v0, v0, s[2:3] glc
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_add_u32_e32 v0, 0x7b, v0
+; GFX9-NEXT:    global_store_dword v1, v0, s[0:1]
+; GFX9-NEXT:    s_endpgm
+;
+; GFX10-LABEL: v_add_imm_i32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX10-NEXT:    v_mov_b32_e32 v1, 0
+; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v0, v0, s[2:3] glc dlc
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_add_nc_u32_e32 v0, 0x7b, v0
+; GFX10-NEXT:    global_store_dword v1, v0, s[0:1]
+; GFX10-NEXT:    s_endpgm
+;
+; GFX11-LABEL: v_add_imm_i32:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_load_b128 s[0:3], s[0:1], 0x24
+; GFX11-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
+; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-NEXT:    global_load_b32 v0, v0, s[2:3] glc dlc
+; GFX11-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-NEXT:    v_add_nc_u32_e32 v0, 0x7b, v0
+; GFX11-NEXT:    global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT:    s_nop 0
+; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT:    s_endpgm
+;
+; GFX12-LABEL: v_add_imm_i32:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    s_load_b128 s[0:3], s[0:1], 0x24
+; GFX12-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    global_load_b32 v0, v0, s[2:3] th:TH_LOAD_RT_NT
+; GFX12-NEXT:    s_waitcnt vmcnt(0)
+; GFX12-NEXT:    v_add_nc_u32_e32 v0, 0x7b, v0
+; GFX12-NEXT:    global_store_b32 v1, v0, s[0:1]
+; GFX12-NEXT:    s_nop 0
+; GFX12-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %gep = getelementptr inbounds i32, ptr addrspace(1) %in, i32 %tid
   %b_ptr = getelementptr i32, ptr addrspace(1) %gep, i32 1
@@ -115,10 +973,92 @@ define amdgpu_kernel void @v_add_imm_i32(ptr addrspace(1) %out, ptr addrspace(1)
   ret void
 }
 
-; FUNC-LABEL: {{^}}add64:
-; GCN: s_add_u32
-; GCN: s_addc_u32
 define amdgpu_kernel void @add64(ptr addrspace(1) %out, i64 %a, i64 %b) {
+; GFX6-LABEL: add64:
+; GFX6:       ; %bb.0: ; %entry
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GFX6-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
+; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_mov_b32 s2, -1
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_mov_b32 s0, s4
+; GFX6-NEXT:    s_add_u32 s4, s6, s8
+; GFX6-NEXT:    s_mov_b32 s1, s5
+; GFX6-NEXT:    s_addc_u32 s5, s7, s9
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NEXT:    s_endpgm
+;
+; GFX8-LABEL: add64:
+; GFX8:       ; %bb.0: ; %entry
+; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
+; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
+; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:    v_mov_b32_e32 v0, s4
+; GFX8-NEXT:    s_add_u32 s0, s6, s0
+; GFX8-NEXT:    s_addc_u32 s1, s7, s1
+; GFX8-NEXT:    v_mov_b32_e32 v3, s1
+; GFX8-NEXT:    v_mov_b32_e32 v1, s5
+; GFX8-NEXT:    v_mov_b32_e32 v2, s0
+; GFX8-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8-NEXT:    s_endpgm
+;
+; GFX9-LABEL: add64:
+; GFX9:       ; %bb.0: ; %entry
+; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
+; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_add_u32 s0, s6, s2
+; GFX9-NEXT:    s_addc_u32 s1, s7, s3
+; GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NEXT:    v_mov_b32_e32 v1, s1
+; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
+; GFX9-NEXT:    s_endpgm
+;
+; GFX10-LABEL: add64:
+; GFX10:       ; %bb.0: ; %entry
+; GFX10-NEXT:    s_clause 0x1
+; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
+; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
+; GFX10-NEXT:    v_mov_b32_e32 v2, 0
+; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX10-NEXT:    s_add_u32 s0, s6, s2
+; GFX10-NEXT:    s_addc_u32 s1, s7, s3
+; GFX10-NEXT:    v_mov_b32_e32 v0, s0
+; GFX10-NEXT:    v_mov_b32_e32 v1, s1
+; GFX10-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
+; GFX10-NEXT:    s_endpgm
+;
+; GFX11-LABEL: add64:
+; GFX11:       ; %bb.0: ; %entry
+; GFX11-NEXT:    s_clause 0x1
+; GFX11-NEXT:    s_load_b128 s[4:7], s[0:1], 0x24
+; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x34
+; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-NEXT:    s_add_u32 s0, s6, s0
+; GFX11-NEXT:    s_addc_u32 s1, s7, s1
+; GFX11-NEXT:    v_mov_b32_e32 v0, s0
+; GFX11-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT:    global_store_b64 v2, v[0:1], s[4:5]
+; GFX11-NEXT:    s_nop 0
+; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT:    s_endpgm
+;
+; GFX12-LABEL: add64:
+; GFX12:       ; %bb.0: ; %entry
+; GFX12-NEXT:    s_clause 0x1
+; GFX12-NEXT:    s_load_b128 s[4:7], s[0:1], 0x24
+; GFX12-NEXT:    s_load_b64 s[0:1], s[0:1], 0x34
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    s_add_nc_u64 s[0:1], s[6:7], s[0:1]
+; GFX12-NEXT:    v_mov_b32_e32 v2, 0
+; GFX12-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-NEXT:    global_store_b64 v2, v[0:1], s[4:5]
+; GFX12-NEXT:    s_nop 0
+; GFX12-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-NEXT:    s_endpgm
 entry:
   %add = add i64 %a, %b
   store i64 %add, ptr addrspace(1) %out
@@ -129,10 +1069,104 @@ entry:
 ; use VCC.  The test is designed so that %a will be stored in an SGPR and
 ; %0 will be stored in a VGPR, so the comiler will be forced to copy %a
 ; to a VGPR before doing the add.
-
-; FUNC-LABEL: {{^}}add64_sgpr_vgpr:
-; GCN-NOT: v_addc_u32_e32 s
 define amdgpu_kernel void @add64_sgpr_vgpr(ptr addrspace(1) %out, i64 %a, ptr addrspace(1) %in) {
+; GFX6-LABEL: add64_sgpr_vgpr:
+; GFX6:       ; %bb.0: ; %entry
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
+; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT:    s_mov_b32 s7, 0xf000
+; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s4, s0
+; GFX6-NEXT:    s_mov_b32 s5, s1
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_add_u32 s0, s2, s8
+; GFX6-NEXT:    s_addc_u32 s1, s3, s9
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT:    s_endpgm
+;
+; GFX8-LABEL: add64_sgpr_vgpr:
+; GFX8:       ; %bb.0: ; %entry
+; GFX8-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x34
+; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x0
+; GFX8-NEXT:    v_mov_b32_e32 v0, s0
+; GFX8-NEXT:    v_mov_b32_e32 v1, s1
+; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:    s_add_u32 s0, s2, s4
+; GFX8-NEXT:    s_addc_u32 s1, s3, s5
+; GFX8-NEXT:    v_mov_b32_e32 v3, s1
+; GFX8-NEXT:    v_mov_b32_e32 v2, s0
+; GFX8-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8-NEXT:    s_endpgm
+;
+; GFX9-LABEL: add64_sgpr_vgpr:
+; GFX9:       ; %bb.0: ; %entry
+; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
+; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x0
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_add_u32 s0, s6, s0
+; GFX9-NEXT:    s_addc_u32 s1, s7, s1
+; GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NEXT:    v_mov_b32_e32 v1, s1
+; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
+; GFX9-NEXT:    s_endpgm
+;
+; GFX10-LABEL: add64_sgpr_vgpr:
+; GFX10:       ; %bb.0: ; %entry
+; GFX10-NEXT:    s_clause 0x1
+; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
+; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
+; GFX10-NEXT:    v_mov_b32_e32 v2, 0
+; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[2:3], 0x0
+; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX10-NEXT:    s_add_u32 s0, s6, s0
+; GFX10-NEXT:    s_addc_u32 s1, s7, s1
+; GFX10-NEXT:    v_mov_b32_e32 v0, s0
+; GFX10-NEXT:    v_mov_b32_e32 v1, s1
+; GFX10-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
+; GFX10-NEXT:    s_endpgm
+;
+; GFX11-LABEL: add64_sgpr_vgpr:
+; GFX11:       ; %bb.0: ; %entry
+; GFX11-NEXT:    s_clause 0x1
+; GFX11-NEXT:    s_load_b64 s[4:5], s[0:1], 0x34
+; GFX11-NEXT:    s_load_b128 s[0:3], s[0:1], 0x24
+; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x0
+; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-NEXT:    s_add_u32 s2, s2, s4
+; GFX11-NEXT:    s_addc_u32 s3, s3, s5
+; GFX11-NEXT:    v_mov_b32_e32 v0, s2
+; GFX11-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-NEXT:    s_nop 0
+; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT:    s_endpgm
+;
+; GFX12-LABEL: add64_sgpr_vgpr:
+; GFX12:       ; %bb.0: ; %entry
+; GFX12-NEXT:    s_clause 0x1
+; GFX12-NEXT:    s_load_b64 s[4:5], s[0:1], 0x34
+; GFX12-NEXT:    s_load_b128 s[0:3], s[0:1], 0x24
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x0
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    s_add_nc_u64 s[2:3], s[2:3], s[4:5]
+; GFX12-NEXT:    v_mov_b32_e32 v2, 0
+; GFX12-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
+; GFX12-NEXT:    s_nop 0
+; GFX12-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-NEXT:    s_endpgm
 entry:
   %0 = load i64, ptr addrspace(1) %in
   %1 = add i64 %a, %0
@@ -141,10 +1175,160 @@ entry:
 }
 
 ; Test i64 add inside a branch.
-; FUNC-LABEL: {{^}}add64_in_branch:
-; GCN: s_add_u32
-; GCN: s_addc_u32
 define amdgpu_kernel void @add64_in_branch(ptr addrspace(1) %out, ptr addrspace(1) %in, i64 %a, i64 %b, i64 %c) {
+; GFX6-LABEL: add64_in_branch:
+; GFX6:       ; %bb.0: ; %entry
+; GFX6-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
+; GFX6-NEXT:    s_mov_b64 s[8:9], 0
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    v_cmp_ne_u64_e64 s[10:11], s[4:5], 0
+; GFX6-NEXT:    s_and_b64 vcc, exec, s[10:11]
+; GFX6-NEXT:    s_cbranch_vccz .LBB9_4
+; GFX6-NEXT:  ; %bb.1: ; %else
+; GFX6-NEXT:    s_add_u32 s4, s4, s6
+; GFX6-NEXT:    s_addc_u32 s5, s5, s7
+; GFX6-NEXT:    s_andn2_b64 vcc, exec, s[8:9]
+; GFX6-NEXT:    s_cbranch_vccnz .LBB9_3
+; GFX6-NEXT:  .LBB9_2: ; %if
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[2:3], 0x0
+; GFX6-NEXT:  .LBB9_3: ; %endif
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_mov_b32 s2, -1
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NEXT:    s_endpgm
+; GFX6-NEXT:  .LBB9_4:
+; GFX6-NEXT:    ; implicit-def: $sgpr4_sgpr5
+; GFX6-NEXT:    s_branch .LBB9_2
+;
+; GFX8-LABEL: add64_in_branch:
+; GFX8:       ; %bb.0: ; %entry
+; GFX8-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
+; GFX8-NEXT:    s_mov_b64 s[8:9], 0
+; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:    s_cmp_lg_u64 s[4:5], 0
+; GFX8-NEXT:    s_cbranch_scc0 .LBB9_4
+; GFX8-NEXT:  ; %bb.1: ; %else
+; GFX8-NEXT:    s_add_u32 s4, s4, s6
+; GFX8-NEXT:    s_addc_u32 s5, s5, s7
+; GFX8-NEXT:    s_andn2_b64 vcc, exec, s[8:9]
+; GFX8-NEXT:    s_cbranch_vccnz .LBB9_3
+; GFX8-NEXT:  .LBB9_2: ; %if
+; GFX8-NEXT:    s_load_dwordx2 s[4:5], s[2:3], 0x0
+; GFX8-NEXT:  .LBB9_3: ; %endif
+; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:    v_mov_b32_e32 v2, s4
+; GFX8-NEXT:    v_mov_b32_e32 v0, s0
+; GFX8-NEXT:    v_mov_b32_e32 v1, s1
+; GFX8-NEXT:    v_mov_b32_e32 v3, s5
+; GFX8-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8-NEXT:    s_endpgm
+; GFX8-NEXT:  .LBB9_4:
+; GFX8-NEXT:    ; implicit-def: $sgpr4_sgpr5
+; GFX8-NEXT:    s_branch .LBB9_2
+;
+; GFX9-LABEL: add64_in_branch:
+; GFX9:       ; %bb.0: ; %entry
+; GFX9-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
+; GFX9-NEXT:    s_mov_b64 s[8:9], 0
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_cmp_lg_u64 s[4:5], 0
+; GFX9-NEXT:    s_cbranch_scc0 .LBB9_4
+; GFX9-NEXT:  ; %bb.1: ; %else
+; GFX9-NEXT:    s_add_u32 s4, s4, s6
+; GFX9-NEXT:    s_addc_u32 s5, s5, s7
+; GFX9-NEXT:    s_andn2_b64 vcc, exec, s[8:9]
+; GFX9-NEXT:    s_cbranch_vccnz .LBB9_3
+; GFX9-NEXT:  .LBB9_2: ; %if
+; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[2:3], 0x0
+; GFX9-NEXT:  .LBB9_3: ; %endif
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v0, s4
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0
+; GFX9-NEXT:    v_mov_b32_e32 v1, s5
+; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX9-NEXT:    s_endpgm
+; GFX9-NEXT:  .LBB9_4:
+; GFX9-NEXT:    ; implicit-def: $sgpr4_sgpr5
+; GFX9-NEXT:    s_branch .LBB9_2
+;
+; GFX10-LABEL: add64_in_branch:
+; GFX10:       ; %bb.0: ; %entry
+; GFX10-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
+; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX10-NEXT:    s_cmp_lg_u64 s[4:5], 0
+; GFX10-NEXT:    s_cbranch_scc0 .LBB9_4
+; GFX10-NEXT:  ; %bb.1: ; %else
+; GFX10-NEXT:    s_add_u32 s4, s4, s6
+; GFX10-NEXT:    s_addc_u32 s5, s5, s7
+; GFX10-NEXT:    s_mov_b32 s6, 0
+; GFX10-NEXT:    s_cbranch_execnz .LBB9_3
+; GFX10-NEXT:  .LBB9_2: ; %if
+; GFX10-NEXT:    s_load_dwordx2 s[4:5], s[2:3], 0x0
+; GFX10-NEXT:  .LBB9_3: ; %endif
+; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX10-NEXT:    v_mov_b32_e32 v0, s4
+; GFX10-NEXT:    v_mov_b32_e32 v2, 0
+; GFX10-NEXT:    v_mov_b32_e32 v1, s5
+; GFX10-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX10-NEXT:    s_endpgm
+; GFX10-NEXT:  .LBB9_4:
+; GFX10-NEXT:    s_mov_b32 s6, -1
+; GFX10-NEXT:    ; implicit-def: $sgpr4_sgpr5
+; GFX10-NEXT:    s_branch .LBB9_2
+;
+; GFX11-LABEL: add64_in_branch:
+; GFX11:       ; %bb.0: ; %entry
+; GFX11-NEXT:    s_load_b256 s[0:7], s[0:1], 0x24
+; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-NEXT:    s_cmp_lg_u64 s[4:5], 0
+; GFX11-NEXT:    s_cbranch_scc0 .LBB9_4
+; GFX11-NEXT:  ; %bb.1: ; %else
+; GFX11-NEXT:    s_add_u32 s4, s4, s6
+; GFX11-NEXT:    s_addc_u32 s5, s5, s7
+; GFX11-NEXT:    s_mov_b32 s6, 0
+; GFX11-NEXT:    s_cbranch_execnz .LBB9_3
+; GFX11-NEXT:  .LBB9_2: ; %if
+; GFX11-NEXT:    s_load_b64 s[4:5], s[2:3], 0x0
+; GFX11-NEXT:  .LBB9_3: ; %endif
+; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-NEXT:    v_mov_b32_e32 v0, s4
+; GFX11-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
+; GFX11-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-NEXT:    s_nop 0
+; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT:    s_endpgm
+; GFX11-NEXT:  .LBB9_4:
+; GFX11-NEXT:    s_mov_b32 s6, -1
+; GFX11-NEXT:    ; implicit-def: $sgpr4_sgpr5
+; GFX11-NEXT:    s_branch .LBB9_2
+;
+; GFX12-LABEL: add64_in_branch:
+; GFX12:       ; %bb.0: ; %entry
+; GFX12-NEXT:    s_load_b256 s[0:7], s[0:1], 0x24
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    s_cmp_lg_u64 s[4:5], 0
+; GFX12-NEXT:    s_cbranch_scc0 .LBB9_4
+; GFX12-NEXT:  ; %bb.1: ; %else
+; GFX12-NEXT:    s_add_nc_u64 s[4:5], s[4:5], s[6:7]
+; GFX12-NEXT:    s_mov_b32 s6, 0
+; GFX12-NEXT:    s_cbranch_execnz .LBB9_3
+; GFX12-NEXT:  .LBB9_2: ; %if
+; GFX12-NEXT:    s_load_b64 s[4:5], s[2:3], 0x0
+; GFX12-NEXT:  .LBB9_3: ; %endif
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    v_mov_b32_e32 v0, s4
+; GFX12-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
+; GFX12-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
+; GFX12-NEXT:    s_nop 0
+; GFX12-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-NEXT:    s_endpgm
+; GFX12-NEXT:  .LBB9_4:
+; GFX12-NEXT:    s_mov_b32 s6, -1
+; GFX12-NEXT:    ; implicit-def: $sgpr4_sgpr5
+; GFX12-NEXT:    s_branch .LBB9_2
 entry:
   %0 = icmp eq i64 %a, 0
   br i1 %0, label %if, label %else
@@ -165,17 +1349,80 @@ endif:
 
 ; Make sure the VOP3 form of add is initially selected. Otherwise pair
 ; of opies from/to VCC would be necessary
-
-; GCN-LABEL: {{^}}add_select_vop3:
-; SI: v_add_i32_e64 v0, s[0:1], s0, v0
-; VI: v_add_u32_e64 v0, s[0:1], s0, v0
-; GFX9: v_add_u32_e32 v0, s0, v0
-; GFX10: v_add_nc_u32_e32 v0, s0, v0
-
-; GCN: ; def vcc
-; GCN: ds_{{write|store}}_b32
-; GCN: ; use vcc
 define amdgpu_ps void @add_select_vop3(i32 inreg %s, i32 %v) {
+; GFX6-LABEL: add_select_vop3:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    v_add_i32_e64 v0, s[0:1], s0, v0
+; GFX6-NEXT:    s_mov_b32 m0, -1
+; GFX6-NEXT:    ;;#ASMSTART
+; GFX6-NEXT:    ; def vcc
+; GFX6-NEXT:    ;;#ASMEND
+; GFX6-NEXT:    ds_write_b32 v0, v0
+; GFX6-NEXT:    ;;#ASMSTART
+; GFX6-NEXT:    ; use vcc
+; GFX6-NEXT:    ;;#ASMEND
+; GFX6-NEXT:    s_endpgm
+;
+; GFX8-LABEL: add_select_vop3:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    v_add_u32_e64 v0, s[0:1], s0, v0
+; GFX8-NEXT:    s_mov_b32 m0, -1
+; GFX8-NEXT:    ;;#ASMSTART
+; GFX8-NEXT:    ; def vcc
+; GFX8-NEXT:    ;;#ASMEND
+; GFX8-NEXT:    ds_write_b32 v0, v0
+; GFX8-NEXT:    ;;#ASMSTART
+; GFX8-NEXT:    ; use vcc
+; GFX8-NEXT:    ;;#ASMEND
+; GFX8-NEXT:    s_endpgm
+;
+; GFX9-LABEL: add_select_vop3:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_add_u32_e32 v0, s0, v0
+; GFX9-NEXT:    ;;#ASMSTART
+; GFX9-NEXT:    ; def vcc
+; GFX9-NEXT:    ;;#ASMEND
+; GFX9-NEXT:    ds_write_b32 v0, v0
+; GFX9-NEXT:    ;;#ASMSTART
+; GFX9-NEXT:    ; use vcc
+; GFX9-NEXT:    ;;#ASMEND
+; GFX9-NEXT:    s_endpgm
+;
+; GFX10-LABEL: add_select_vop3:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_add_nc_u32_e32 v0, s0, v0
+; GFX10-NEXT:    ;;#ASMSTART
+; GFX10-NEXT:    ; def vcc
+; GFX10-NEXT:    ;;#ASMEND
+; GFX10-NEXT:    ds_write_b32 v0, v0
+; GFX10-NEXT:    ;;#ASMSTART
+; GFX10-NEXT:    ; use vcc
+; GFX10-NEXT:    ;;#ASMEND
+; GFX10-NEXT:    s_endpgm
+;
+; GFX11-LABEL: add_select_vop3:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    v_add_nc_u32_e32 v0, s0, v0
+; GFX11-NEXT:    ;;#ASMSTART
+; GFX11-NEXT:    ; def vcc
+; GFX11-NEXT:    ;;#ASMEND
+; GFX11-NEXT:    ds_store_b32 v0, v0
+; GFX11-NEXT:    ;;#ASMSTART
+; GFX11-NEXT:    ; use vcc
+; GFX11-NEXT:    ;;#ASMEND
+; GFX11-NEXT:    s_endpgm
+;
+; GFX12-LABEL: add_select_vop3:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    v_add_nc_u32_e32 v0, s0, v0
+; GFX12-NEXT:    ;;#ASMSTART
+; GFX12-NEXT:    ; def vcc
+; GFX12-NEXT:    ;;#ASMEND
+; GFX12-NEXT:    ds_store_b32 v0, v0
+; GFX12-NEXT:    ;;#ASMSTART
+; GFX12-NEXT:    ; use vcc
+; GFX12-NEXT:    ;;#ASMEND
+; GFX12-NEXT:    s_endpgm
   %vcc = call i64 asm sideeffect "; def vcc", "={vcc}"()
   %sub = add i32 %v, %s
   store i32 %sub, ptr addrspace(3) undef
diff --git a/llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll b/llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
new file mode 100644
index 000000000000..3b57252741c2
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
@@ -0,0 +1,118 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -march=amdgcn -mcpu=gfx1200 -stop-after=si-fix-sgpr-copies -verify-machineinstrs < %s | FileCheck %s
+
+define amdgpu_kernel void @add_reg_imm(ptr addrspace(1) %ptr) {
+  ; CHECK-LABEL: name: add_reg_imm
+  ; CHECK: bb.0 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $sgpr0_sgpr1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr0_sgpr1
+  ; CHECK-NEXT:   [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 36, 0 :: (dereferenceable invariant load (s64) from %ir.ptr.kernarg.offset, align 4, addrspace 4)
+  ; CHECK-NEXT:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+  ; CHECK-NEXT:   [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2_SADDR [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s64) from %ir.ptr.load, addrspace 1)
+  ; CHECK-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 28744523
+  ; CHECK-NEXT:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -1395630315
+  ; CHECK-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE killed [[S_MOV_B32_1]], %subreg.sub0, killed [[S_MOV_B32_]], %subreg.sub1
+  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+  ; CHECK-NEXT:   [[V_ADD_U:%[0-9]+]]:vreg_64 = V_ADD_U64_PSEUDO [[GLOBAL_LOAD_DWORDX2_SADDR]], killed [[REG_SEQUENCE]], implicit-def $vcc_lo, implicit $exec
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:vreg_64 = COPY [[V_ADD_U]]
+  ; CHECK-NEXT:   GLOBAL_STORE_DWORDX2_SADDR [[V_MOV_B32_e32_]], killed [[COPY1]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s64) into %ir.ptr.load, addrspace 1)
+  ; CHECK-NEXT:   S_ENDPGM 0
+  %lhs = load volatile i64, ptr addrspace(1) %ptr
+  %res = add i64 %lhs, 123456789123456789
+  store i64 %res, ptr addrspace(1) %ptr
+  ret void
+}
+
+define amdgpu_kernel void @add_reg_reg(ptr addrspace(1) %ptr) {
+  ; CHECK-LABEL: name: add_reg_reg
+  ; CHECK: bb.0 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $sgpr0_sgpr1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr0_sgpr1
+  ; CHECK-NEXT:   [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 36, 0 :: (dereferenceable invariant load (s64) from %ir.ptr.kernarg.offset, align 4, addrspace 4)
+  ; CHECK-NEXT:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+  ; CHECK-NEXT:   [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2_SADDR [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s64) from %ir.ptr.load, addrspace 1)
+  ; CHECK-NEXT:   [[GLOBAL_LOAD_DWORDX2_SADDR1:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2_SADDR [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile load (s64) from %ir.ptr.load, addrspace 1)
+  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+  ; CHECK-NEXT:   [[V_ADD_U:%[0-9]+]]:vreg_64 = V_ADD_U64_PSEUDO [[GLOBAL_LOAD_DWORDX2_SADDR]], [[GLOBAL_LOAD_DWORDX2_SADDR1]], implicit-def $vcc_lo, implicit $exec
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:vreg_64 = COPY [[V_ADD_U]]
+  ; CHECK-NEXT:   GLOBAL_STORE_DWORDX2_SADDR [[V_MOV_B32_e32_]], killed [[COPY1]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s64) into %ir.ptr.load, addrspace 1)
+  ; CHECK-NEXT:   S_ENDPGM 0
+  %lhs = load volatile i64, ptr addrspace(1) %ptr
+  %rhs = load volatile i64, ptr addrspace(1) %ptr
+  %res = add i64 %lhs, %rhs
+  store i64 %res, ptr addrspace(1) %ptr
+  ret void
+}
+
+define amdgpu_kernel void @sub_reg_imm(ptr addrspace(1) %ptr) {
+  ; CHECK-LABEL: name: sub_reg_imm
+  ; CHECK: bb.0 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $sgpr0_sgpr1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr0_sgpr1
+  ; CHECK-NEXT:   [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 36, 0 :: (dereferenceable invariant load (s64) from %ir.ptr.kernarg.offset, align 4, addrspace 4)
+  ; CHECK-NEXT:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+  ; CHECK-NEXT:   [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2_SADDR [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s64) from %ir.ptr.load, addrspace 1)
+  ; CHECK-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -28744524
+  ; CHECK-NEXT:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1395630315
+  ; CHECK-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE killed [[S_MOV_B32_1]], %subreg.sub0, killed [[S_MOV_B32_]], %subreg.sub1
+  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+  ; CHECK-NEXT:   [[V_ADD_U:%[0-9]+]]:vreg_64 = V_ADD_U64_PSEUDO [[GLOBAL_LOAD_DWORDX2_SADDR]], killed [[REG_SEQUENCE]], implicit-def $vcc_lo, implicit $exec
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:vreg_64 = COPY [[V_ADD_U]]
+  ; CHECK-NEXT:   GLOBAL_STORE_DWORDX2_SADDR [[V_MOV_B32_e32_]], killed [[COPY1]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s64) into %ir.ptr.load, addrspace 1)
+  ; CHECK-NEXT:   S_ENDPGM 0
+  %lhs = load volatile i64, ptr addrspace(1) %ptr
+  %res = sub i64 %lhs, 123456789123456789
+  store i64 %res, ptr addrspace(1) %ptr
+  ret void
+}
+
+define amdgpu_kernel void @sub_imm_reg(ptr addrspace(1) %ptr) {
+  ; CHECK-LABEL: name: sub_imm_reg
+  ; CHECK: bb.0 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $sgpr0_sgpr1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr0_sgpr1
+  ; CHECK-NEXT:   [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 36, 0 :: (dereferenceable invariant load (s64) from %ir.ptr.kernarg.offset, align 4, addrspace 4)
+  ; CHECK-NEXT:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+  ; CHECK-NEXT:   [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2_SADDR [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s64) from %ir.ptr.load, addrspace 1)
+  ; CHECK-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 28744523
+  ; CHECK-NEXT:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -1395630315
+  ; CHECK-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE killed [[S_MOV_B32_1]], %subreg.sub0, killed [[S_MOV_B32_]], %subreg.sub1
+  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+  ; CHECK-NEXT:   [[V_SUB_U:%[0-9]+]]:vreg_64 = V_SUB_U64_PSEUDO killed [[REG_SEQUENCE]], [[GLOBAL_LOAD_DWORDX2_SADDR]], implicit-def $vcc_lo, implicit $exec
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:vreg_64 = COPY [[V_SUB_U]]
+  ; CHECK-NEXT:   GLOBAL_STORE_DWORDX2_SADDR [[V_MOV_B32_e32_]], killed [[COPY1]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s64) into %ir.ptr.load, addrspace 1)
+  ; CHECK-NEXT:   S_ENDPGM 0
+  %rhs = load volatile i64, ptr addrspace(1) %ptr
+  %res = sub i64 123456789123456789, %rhs
+  store i64 %res, ptr addrspace(1) %ptr
+  ret void
+}
+
+define amdgpu_kernel void @sub_reg_reg(ptr addrspace(1) %ptr) {
+  ; CHECK-LABEL: name: sub_reg_reg
+  ; CHECK: bb.0 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $sgpr0_sgpr1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr0_sgpr1
+  ; CHECK-NEXT:   [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 36, 0 :: (dereferenceable invariant load (s64) from %ir.ptr.kernarg.offset, align 4, addrspace 4)
+  ; CHECK-NEXT:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+  ; CHECK-NEXT:   [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2_SADDR [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s64) from %ir.ptr.load, addrspace 1)
+  ; CHECK-NEXT:   [[GLOBAL_LOAD_DWORDX2_SADDR1:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2_SADDR [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile load (s64) from %ir.ptr.load, addrspace 1)
+  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+  ; CHECK-NEXT:   [[V_SUB_U:%[0-9]+]]:vreg_64 = V_SUB_U64_PSEUDO [[GLOBAL_LOAD_DWORDX2_SADDR]], [[GLOBAL_LOAD_DWORDX2_SADDR1]], implicit-def $vcc_lo, implicit $exec
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:vreg_64 = COPY [[V_SUB_U]]
+  ; CHECK-NEXT:   GLOBAL_STORE_DWORDX2_SADDR [[V_MOV_B32_e32_]], killed [[COPY1]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s64) into %ir.ptr.load, addrspace 1)
+  ; CHECK-NEXT:   S_ENDPGM 0
+  %lhs = load volatile i64, ptr addrspace(1) %ptr
+  %rhs = load volatile i64, ptr addrspace(1) %ptr
+  %res = sub i64 %lhs, %rhs
+  store i64 %res, ptr addrspace(1) %ptr
+  ret void
+}
+
diff --git a/llvm/test/CodeGen/AMDGPU/sub.ll b/llvm/test/CodeGen/AMDGPU/sub.ll
index bee986f4d911..098a4cbb36ed 100644
--- a/llvm/test/CodeGen/AMDGPU/sub.ll
+++ b/llvm/test/CodeGen/AMDGPU/sub.ll
@@ -1,7 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX6 %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX8 %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX6 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12 %s
 
 declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone speculatable
 
@@ -39,6 +40,18 @@ define amdgpu_kernel void @s_sub_i32(ptr addrspace(1) %out, i32 %a, i32 %b) {
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s2
 ; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
 ; GFX9-NEXT:    s_endpgm
+;
+; GFX12-LABEL: s_sub_i32:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    s_load_b128 s[0:3], s[0:1], 0x24
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    s_sub_co_i32 s2, s2, s3
+; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX12-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX12-NEXT:    s_nop 0
+; GFX12-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-NEXT:    s_endpgm
   %result = sub i32 %a, %b
   store i32 %result, ptr addrspace(1) %out
   ret void
@@ -79,6 +92,20 @@ define amdgpu_kernel void @s_sub_imm_i32(ptr addrspace(1) %out, i32 %a) {
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
 ; GFX9-NEXT:    s_endpgm
+;
+; GFX12-LABEL: s_sub_imm_i32:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    s_clause 0x1
+; GFX12-NEXT:    s_load_b32 s2, s[0:1], 0x2c
+; GFX12-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    s_sub_co_i32 s2, 0x4d2, s2
+; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX12-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX12-NEXT:    s_nop 0
+; GFX12-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-NEXT:    s_endpgm
   %result = sub i32 1234, %a
   store i32 %result, ptr addrspace(1) %out
   ret void
@@ -127,6 +154,19 @@ define amdgpu_kernel void @test_sub_i32(ptr addrspace(1) %out, ptr addrspace(1)
 ; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v1
 ; GFX9-NEXT:    global_store_dword v2, v0, s[0:1]
 ; GFX9-NEXT:    s_endpgm
+;
+; GFX12-LABEL: test_sub_i32:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    s_load_b128 s[0:3], s[0:1], 0x24
+; GFX12-NEXT:    v_mov_b32_e32 v2, 0
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    global_load_b64 v[0:1], v2, s[2:3]
+; GFX12-NEXT:    s_waitcnt vmcnt(0)
+; GFX12-NEXT:    v_sub_nc_u32_e32 v0, v0, v1
+; GFX12-NEXT:    global_store_b32 v2, v0, s[0:1]
+; GFX12-NEXT:    s_nop 0
+; GFX12-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-NEXT:    s_endpgm
   %b_ptr = getelementptr i32, ptr addrspace(1) %in, i32 1
   %a = load i32, ptr addrspace(1) %in
   %b = load i32, ptr addrspace(1) %b_ptr
@@ -178,6 +218,19 @@ define amdgpu_kernel void @test_sub_imm_i32(ptr addrspace(1) %out, ptr addrspace
 ; GFX9-NEXT:    v_sub_u32_e32 v1, 0x7b, v1
 ; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
 ; GFX9-NEXT:    s_endpgm
+;
+; GFX12-LABEL: test_sub_imm_i32:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    s_load_b128 s[0:3], s[0:1], 0x24
+; GFX12-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    global_load_b32 v1, v0, s[2:3]
+; GFX12-NEXT:    s_waitcnt vmcnt(0)
+; GFX12-NEXT:    v_sub_nc_u32_e32 v1, 0x7b, v1
+; GFX12-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX12-NEXT:    s_nop 0
+; GFX12-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-NEXT:    s_endpgm
   %a = load i32, ptr addrspace(1) %in
   %result = sub i32 123, %a
   store i32 %result, ptr addrspace(1) %out
@@ -230,6 +283,20 @@ define amdgpu_kernel void @test_sub_v2i32(ptr addrspace(1) %out, ptr addrspace(1
 ; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v2
 ; GFX9-NEXT:    global_store_dwordx2 v4, v[0:1], s[0:1]
 ; GFX9-NEXT:    s_endpgm
+;
+; GFX12-LABEL: test_sub_v2i32:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    s_load_b128 s[0:3], s[0:1], 0x24
+; GFX12-NEXT:    v_mov_b32_e32 v4, 0
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    global_load_b128 v[0:3], v4, s[2:3]
+; GFX12-NEXT:    s_waitcnt vmcnt(0)
+; GFX12-NEXT:    v_sub_nc_u32_e32 v1, v1, v3
+; GFX12-NEXT:    v_sub_nc_u32_e32 v0, v0, v2
+; GFX12-NEXT:    global_store_b64 v4, v[0:1], s[0:1]
+; GFX12-NEXT:    s_nop 0
+; GFX12-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-NEXT:    s_endpgm
   %b_ptr = getelementptr <2 x i32>, ptr addrspace(1) %in, i32 1
   %a = load <2 x i32>, ptr addrspace(1) %in
   %b = load <2 x i32>, ptr addrspace(1) %b_ptr
@@ -297,6 +364,24 @@ define amdgpu_kernel void @test_sub_v4i32(ptr addrspace(1) %out, ptr addrspace(1
 ; GFX9-NEXT:    v_sub_u32_e32 v0, v4, v0
 ; GFX9-NEXT:    global_store_dwordx4 v8, v[0:3], s[0:1]
 ; GFX9-NEXT:    s_endpgm
+;
+; GFX12-LABEL: test_sub_v4i32:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    s_load_b128 s[0:3], s[0:1], 0x24
+; GFX12-NEXT:    v_mov_b32_e32 v8, 0
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    s_clause 0x1
+; GFX12-NEXT:    global_load_b128 v[0:3], v8, s[2:3] offset:16
+; GFX12-NEXT:    global_load_b128 v[4:7], v8, s[2:3]
+; GFX12-NEXT:    s_waitcnt vmcnt(0)
+; GFX12-NEXT:    v_sub_nc_u32_e32 v3, v7, v3
+; GFX12-NEXT:    v_sub_nc_u32_e32 v2, v6, v2
+; GFX12-NEXT:    v_sub_nc_u32_e32 v1, v5, v1
+; GFX12-NEXT:    v_sub_nc_u32_e32 v0, v4, v0
+; GFX12-NEXT:    global_store_b128 v8, v[0:3], s[0:1]
+; GFX12-NEXT:    s_nop 0
+; GFX12-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-NEXT:    s_endpgm
   %b_ptr = getelementptr <4 x i32>, ptr addrspace(1) %in, i32 1
   %a = load <4 x i32>, ptr addrspace(1) %in
   %b = load <4 x i32>, ptr addrspace(1) %b_ptr
@@ -360,6 +445,22 @@ define amdgpu_kernel void @test_sub_i16(ptr addrspace(1) %out, ptr addrspace(1)
 ; GFX9-NEXT:    v_sub_u16_e32 v1, v1, v2
 ; GFX9-NEXT:    global_store_short v0, v1, s[0:1]
 ; GFX9-NEXT:    s_endpgm
+;
+; GFX12-LABEL: test_sub_i16:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    s_load_b128 s[0:3], s[0:1], 0x24
+; GFX12-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX12-NEXT:    v_mov_b32_e32 v2, 0
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    global_load_u16 v1, v0, s[2:3] th:TH_LOAD_RT_NT
+; GFX12-NEXT:    s_waitcnt vmcnt(0)
+; GFX12-NEXT:    global_load_u16 v0, v0, s[2:3] offset:2 th:TH_LOAD_RT_NT
+; GFX12-NEXT:    s_waitcnt vmcnt(0)
+; GFX12-NEXT:    v_sub_nc_u16 v0, v1, v0
+; GFX12-NEXT:    global_store_b16 v2, v0, s[0:1]
+; GFX12-NEXT:    s_nop 0
+; GFX12-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %gep = getelementptr i16, ptr addrspace(1) %in, i32 %tid
   %b_ptr = getelementptr i16, ptr addrspace(1) %gep, i32 1
@@ -425,6 +526,20 @@ define amdgpu_kernel void @test_sub_v2i16(ptr addrspace(1) %out, ptr addrspace(1
 ; GFX9-NEXT:    v_pk_sub_i16 v0, v0, v1
 ; GFX9-NEXT:    global_store_dword v2, v0, s[0:1]
 ; GFX9-NEXT:    s_endpgm
+;
+; GFX12-LABEL: test_sub_v2i16:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    s_load_b128 s[0:3], s[0:1], 0x24
+; GFX12-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX12-NEXT:    v_mov_b32_e32 v2, 0
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    global_load_b64 v[0:1], v0, s[2:3]
+; GFX12-NEXT:    s_waitcnt vmcnt(0)
+; GFX12-NEXT:    v_pk_sub_i16 v0, v0, v1
+; GFX12-NEXT:    global_store_b32 v2, v0, s[0:1]
+; GFX12-NEXT:    s_nop 0
+; GFX12-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %gep = getelementptr <2 x i16>, ptr addrspace(1) %in, i32 %tid
   %b_ptr = getelementptr <2 x i16>, ptr addrspace(1) %gep, i16 1
@@ -501,6 +616,21 @@ define amdgpu_kernel void @test_sub_v4i16(ptr addrspace(1) %out, ptr addrspace(1
 ; GFX9-NEXT:    v_pk_sub_i16 v0, v0, v2
 ; GFX9-NEXT:    global_store_dwordx2 v4, v[0:1], s[0:1]
 ; GFX9-NEXT:    s_endpgm
+;
+; GFX12-LABEL: test_sub_v4i16:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    s_load_b128 s[0:3], s[0:1], 0x24
+; GFX12-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
+; GFX12-NEXT:    v_mov_b32_e32 v4, 0
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    global_load_b128 v[0:3], v0, s[2:3]
+; GFX12-NEXT:    s_waitcnt vmcnt(0)
+; GFX12-NEXT:    v_pk_sub_i16 v1, v1, v3
+; GFX12-NEXT:    v_pk_sub_i16 v0, v0, v2
+; GFX12-NEXT:    global_store_b64 v4, v[0:1], s[0:1]
+; GFX12-NEXT:    s_nop 0
+; GFX12-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %gep = getelementptr <4 x i16>, ptr addrspace(1) %in, i32 %tid
   %b_ptr = getelementptr <4 x i16>, ptr addrspace(1) %gep, i16 1
@@ -552,6 +682,20 @@ define amdgpu_kernel void @s_sub_i64(ptr addrspace(1) noalias %out, i64 %a, i64
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
 ; GFX9-NEXT:    s_endpgm
+;
+; GFX12-LABEL: s_sub_i64:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    s_clause 0x1
+; GFX12-NEXT:    s_load_b128 s[4:7], s[0:1], 0x2c
+; GFX12-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    s_sub_nc_u64 s[2:3], s[4:5], s[6:7]
+; GFX12-NEXT:    v_mov_b32_e32 v2, 0
+; GFX12-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
+; GFX12-NEXT:    s_nop 0
+; GFX12-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-NEXT:    s_endpgm
   %result = sub i64 %a, %b
   store i64 %result, ptr addrspace(1) %out, align 8
   ret void
@@ -617,6 +761,25 @@ define amdgpu_kernel void @v_sub_i64(ptr addrspace(1) noalias %out, ptr addrspac
 ; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX9-NEXT:    global_store_dwordx2 v4, v[0:1], s[4:5]
 ; GFX9-NEXT:    s_endpgm
+;
+; GFX12-LABEL: v_sub_i64:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    s_clause 0x1
+; GFX12-NEXT:    s_load_b128 s[4:7], s[0:1], 0x24
+; GFX12-NEXT:    s_load_b64 s[0:1], s[0:1], 0x34
+; GFX12-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
+; GFX12-NEXT:    v_mov_b32_e32 v4, 0
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    s_clause 0x1
+; GFX12-NEXT:    global_load_b64 v[0:1], v2, s[6:7]
+; GFX12-NEXT:    global_load_b64 v[2:3], v2, s[0:1]
+; GFX12-NEXT:    s_waitcnt vmcnt(0)
+; GFX12-NEXT:    v_sub_co_u32 v0, vcc_lo, v0, v2
+; GFX12-NEXT:    v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
+; GFX12-NEXT:    global_store_b64 v4, v[0:1], s[4:5]
+; GFX12-NEXT:    s_nop 0
+; GFX12-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x() readnone
   %a_ptr = getelementptr i64, ptr addrspace(1) %inA, i32 %tid
   %b_ptr = getelementptr i64, ptr addrspace(1) %inB, i32 %tid
@@ -693,6 +856,27 @@ define amdgpu_kernel void @v_test_sub_v2i64(ptr addrspace(1) %out, ptr addrspace
 ; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v5, vcc
 ; GFX9-NEXT:    global_store_dwordx4 v8, v[0:3], s[4:5]
 ; GFX9-NEXT:    s_endpgm
+;
+; GFX12-LABEL: v_test_sub_v2i64:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    s_clause 0x1
+; GFX12-NEXT:    s_load_b128 s[4:7], s[0:1], 0x24
+; GFX12-NEXT:    s_load_b64 s[0:1], s[0:1], 0x34
+; GFX12-NEXT:    v_lshlrev_b32_e32 v4, 4, v0
+; GFX12-NEXT:    v_mov_b32_e32 v8, 0
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    s_clause 0x1
+; GFX12-NEXT:    global_load_b128 v[0:3], v4, s[6:7]
+; GFX12-NEXT:    global_load_b128 v[4:7], v4, s[0:1]
+; GFX12-NEXT:    s_waitcnt vmcnt(0)
+; GFX12-NEXT:    v_sub_co_u32 v2, vcc_lo, v2, v6
+; GFX12-NEXT:    v_sub_co_ci_u32_e32 v3, vcc_lo, v3, v7, vcc_lo
+; GFX12-NEXT:    v_sub_co_u32 v0, vcc_lo, v0, v4
+; GFX12-NEXT:    v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v5, vcc_lo
+; GFX12-NEXT:    global_store_b128 v8, v[0:3], s[4:5]
+; GFX12-NEXT:    s_nop 0
+; GFX12-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x() readnone
   %a_ptr = getelementptr <2 x i64>, ptr addrspace(1) %inA, i32 %tid
   %b_ptr = getelementptr <2 x i64>, ptr addrspace(1) %inB, i32 %tid
@@ -801,6 +985,36 @@ define amdgpu_kernel void @v_test_sub_v4i64(ptr addrspace(1) %out, ptr addrspace
 ; GFX9-NEXT:    global_store_dwordx4 v16, v[4:7], s[4:5] offset:16
 ; GFX9-NEXT:    global_store_dwordx4 v16, v[0:3], s[4:5]
 ; GFX9-NEXT:    s_endpgm
+;
+; GFX12-LABEL: v_test_sub_v4i64:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    s_clause 0x1
+; GFX12-NEXT:    s_load_b128 s[4:7], s[0:1], 0x24
+; GFX12-NEXT:    s_load_b64 s[0:1], s[0:1], 0x34
+; GFX12-NEXT:    v_lshlrev_b32_e32 v12, 5, v0
+; GFX12-NEXT:    v_mov_b32_e32 v16, 0
+; GFX12-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX12-NEXT:    s_clause 0x3
+; GFX12-NEXT:    global_load_b128 v[0:3], v12, s[6:7]
+; GFX12-NEXT:    global_load_b128 v[4:7], v12, s[0:1]
+; GFX12-NEXT:    global_load_b128 v[8:11], v12, s[6:7] offset:16
+; GFX12-NEXT:    global_load_b128 v[12:15], v12, s[0:1] offset:16
+; GFX12-NEXT:    s_waitcnt vmcnt(2)
+; GFX12-NEXT:    v_sub_co_u32 v2, vcc_lo, v2, v6
+; GFX12-NEXT:    v_sub_co_ci_u32_e32 v3, vcc_lo, v3, v7, vcc_lo
+; GFX12-NEXT:    s_waitcnt vmcnt(0)
+; GFX12-NEXT:    v_sub_co_u32 v10, vcc_lo, v10, v14
+; GFX12-NEXT:    v_sub_co_ci_u32_e32 v11, vcc_lo, v11, v15, vcc_lo
+; GFX12-NEXT:    v_sub_co_u32 v8, vcc_lo, v8, v12
+; GFX12-NEXT:    v_sub_co_ci_u32_e32 v9, vcc_lo, v9, v13, vcc_lo
+; GFX12-NEXT:    v_sub_co_u32 v0, vcc_lo, v0, v4
+; GFX12-NEXT:    v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v5, vcc_lo
+; GFX12-NEXT:    s_clause 0x1
+; GFX12-NEXT:    global_store_b128 v16, v[8:11], s[4:5] offset:16
+; GFX12-NEXT:    global_store_b128 v16, v[0:3], s[4:5]
+; GFX12-NEXT:    s_nop 0
+; GFX12-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x() readnone
   %a_ptr = getelementptr <4 x i64>, ptr addrspace(1) %inA, i32 %tid
   %b_ptr = getelementptr <4 x i64>, ptr addrspace(1) %inB, i32 %tid
@@ -852,6 +1066,18 @@ define amdgpu_ps void @sub_select_vop3(i32 inreg %s, i32 %v) {
 ; GFX9-NEXT:    ; use vcc
 ; GFX9-NEXT:    ;;#ASMEND
 ; GFX9-NEXT:    s_endpgm
+;
+; GFX12-LABEL: sub_select_vop3:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    v_subrev_nc_u32_e32 v0, s0, v0
+; GFX12-NEXT:    ;;#ASMSTART
+; GFX12-NEXT:    ; def vcc
+; GFX12-NEXT:    ;;#ASMEND
+; GFX12-NEXT:    ds_store_b32 v0, v0
+; GFX12-NEXT:    ;;#ASMSTART
+; GFX12-NEXT:    ; use vcc
+; GFX12-NEXT:    ;;#ASMEND
+; GFX12-NEXT:    s_endpgm
   %vcc = call i64 asm sideeffect "; def vcc", "={vcc}"()
   %sub = sub i32 %v, %s
   store i32 %sub, ptr addrspace(3) undef
-- 
GitLab


From 31cf6df06febdf2483d224d2c9657497cac7d41f Mon Sep 17 00:00:00 2001
From: Wei Wang <apollo.mobility@gmail.com>
Date: Tue, 12 Dec 2023 09:47:46 -0800
Subject: [PATCH 335/349] [coroutines] Use DILocation from new storage for
 hoisted dbg.declare (#75104)

Make the hoisted dbg.declare inherent the DILocation scope from the new
storage.

After hoisting, the dbg.declare is moved into the block that defines the
new storage. This could create an inconsistency in the debug location
scope hierarchy where the scope of hoisted dbg.declare (i.e.
DILexicalBlock) is enclosed with the scope of the block (i.e.
DISubprogram). This confuses LiveDebugValues pass to think that the
hoisted dbg.declare is killed in that block and does not generate
DBG_VALUE in other blocks. Debugger won't be able to track its value
anymore.
---
 llvm/lib/Transforms/Coroutines/CoroFrame.cpp  |  6 ++--
 .../Coroutines/coro-debug-frame-variable.ll   | 29 ++++++++++---------
 2 files changed, 20 insertions(+), 15 deletions(-)

diff --git a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp
index 6b85de15947c..678d7fb3f571 100644
--- a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp
+++ b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp
@@ -2891,9 +2891,11 @@ void coro::salvageDebugInfo(
   // dbg.declare does.
   if (isa<DbgDeclareInst>(DVI)) {
     std::optional<BasicBlock::iterator> InsertPt;
-    if (auto *I = dyn_cast<Instruction>(Storage))
+    if (auto *I = dyn_cast<Instruction>(Storage)) {
       InsertPt = I->getInsertionPointAfterDef();
-    else if (isa<Argument>(Storage))
+      if (I->getDebugLoc())
+        DVI->setDebugLoc(I->getDebugLoc());
+    } else if (isa<Argument>(Storage))
       InsertPt = F->getEntryBlock().begin();
     if (InsertPt)
       DVI->moveBefore(*(*InsertPt)->getParent(), *InsertPt);
diff --git a/llvm/test/Transforms/Coroutines/coro-debug-frame-variable.ll b/llvm/test/Transforms/Coroutines/coro-debug-frame-variable.ll
index 37b4126ce373..53995fb3498e 100644
--- a/llvm/test/Transforms/Coroutines/coro-debug-frame-variable.ll
+++ b/llvm/test/Transforms/Coroutines/coro-debug-frame-variable.ll
@@ -31,8 +31,8 @@
 ; CHECK:       entry:
 ; CHECK:         %j = alloca i32, align 4
 ; CHECK:         call void @llvm.dbg.declare(metadata ptr %j, metadata ![[JVAR:[0-9]+]], metadata !DIExpression()), !dbg ![[JDBGLOC:[0-9]+]]
-; CHECK:         %[[MEMORY:.*]] = call ptr @new
-; CHECK:         call void @llvm.dbg.declare(metadata ptr %[[MEMORY]], metadata ![[XVAR:[0-9]+]], metadata !DIExpression(DW_OP_plus_uconst, 32)), !dbg ![[IDBGLOC:[0-9]+]]
+; CHECK:         %[[MEMORY:.*]] = call ptr @new({{.+}}), !dbg ![[IDBGLOC:[0-9]+]]
+; CHECK:         call void @llvm.dbg.declare(metadata ptr %[[MEMORY]], metadata ![[XVAR:[0-9]+]], metadata !DIExpression(DW_OP_plus_uconst, 32)), !dbg ![[IDBGLOC]]
 ; CHECK:         call void @llvm.dbg.declare(metadata ptr %[[MEMORY]], metadata ![[IVAR:[0-9]+]], metadata !DIExpression(DW_OP_plus_uconst, 20)), !dbg ![[IDBGLOC]]
 ; CHECK:       await.ready:
 ;
@@ -48,18 +48,20 @@
 ; CHECK:       await.ready:
 ;
 ; CHECK-DAG: ![[IVAR]] = !DILocalVariable(name: "i"
-; CHECK-DAG: ![[SCOPE:[0-9]+]] = distinct !DILexicalBlock(scope: !6, file: !1, line: 23, column: 12)
-; CHECK-DAG: ![[IDBGLOC]] = !DILocation(line: 24, column: 7, scope: ![[SCOPE]])
+; CHECK-DAG: ![[PROG_SCOPE:[0-9]+]] = distinct !DISubprogram(name: "foo", linkageName: "_Z3foov"
+; CHECK-DAG: ![[BLK_SCOPE:[0-9]+]] = distinct !DILexicalBlock(scope: ![[PROG_SCOPE]], file: !1, line: 23, column: 12)
+; CHECK-DAG: ![[IDBGLOC]] = !DILocation(line: 23, column: 6, scope: ![[PROG_SCOPE]])
 ; CHECK-DAG: ![[XVAR]] = !DILocalVariable(name: "x"
 ; CHECK-DAG: ![[JVAR]] = !DILocalVariable(name: "j"
-; CHECK-DAG: ![[JDBGLOC]] = !DILocation(line: 32, column: 7, scope: ![[SCOPE]])
+; CHECK-DAG: ![[JDBGLOC]] = !DILocation(line: 32, column: 7, scope: ![[BLK_SCOPE]])
 
 ; CHECK-DAG: ![[XVAR_RESUME]] = !DILocalVariable(name: "x"
-; CHECK-DAG: ![[IDBGLOC_RESUME]] = !DILocation(line: 24, column: 7, scope: ![[RESUME_SCOPE:[0-9]+]])
-; CHECK-DAG: ![[RESUME_SCOPE]] = distinct !DILexicalBlock(scope: !22, file: !1, line: 23, column: 12)
+; CHECK-DAG: ![[RESUME_PROG_SCOPE:[0-9]+]] = distinct !DISubprogram(name: "foo", linkageName: "_Z3foov"
+; CHECK-DAG: ![[IDBGLOC_RESUME]] = !DILocation(line: 24, column: 7, scope: ![[RESUME_BLK_SCOPE:[0-9]+]])
+; CHECK-DAG: ![[RESUME_BLK_SCOPE]] = distinct !DILexicalBlock(scope: ![[RESUME_PROG_SCOPE]], file: !1, line: 23, column: 12)
 ; CHECK-DAG: ![[IVAR_RESUME]] = !DILocalVariable(name: "i"
 ; CHECK-DAG: ![[JVAR_RESUME]] = !DILocalVariable(name: "j"
-; CHECK-DAG: ![[JDBGLOC_RESUME]] = !DILocation(line: 32, column: 7, scope: ![[RESUME_SCOPE]])
+; CHECK-DAG: ![[JDBGLOC_RESUME]] = !DILocation(line: 32, column: 7, scope: ![[RESUME_BLK_SCOPE]])
 define void @f() presplitcoroutine !dbg !8 {
 entry:
   %__promise = alloca i8, align 8
@@ -71,13 +73,13 @@ entry:
   br i1 %alloc, label %coro.alloc, label %coro.init
 
 coro.alloc:                                       ; preds = %entry
-  %size = call i64 @llvm.coro.size.i64()
-  %memory = call ptr @new(i64 %size)
-  br label %coro.init
+  %size = call i64 @llvm.coro.size.i64(), !dbg !23
+  %memory = call ptr @new(i64 %size), !dbg !23
+  br label %coro.init, !dbg !23
 
 coro.init:                                        ; preds = %coro.alloc, %entry
-  %phi.entry.alloc = phi ptr [ null, %entry ], [ %memory, %coro.alloc ]
-  %begin = call ptr @llvm.coro.begin(token %id, ptr %phi.entry.alloc)
+  %phi.entry.alloc = phi ptr [ null, %entry ], [ %memory, %coro.alloc ], !dbg !23
+  %begin = call ptr @llvm.coro.begin(token %id, ptr %phi.entry.alloc), !dbg !23
   %ready = call i1 @await_ready()
   br i1 %ready, label %init.ready, label %init.suspend
 
@@ -239,3 +241,4 @@ declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg)
 !20 = !DILocation(line: 43, column: 3, scope: !7)
 !21 = !DILocation(line: 43, column: 8, scope: !7)
 !22 = distinct !DILexicalBlock(scope: !8, file: !1, line: 23, column: 12)
+!23 = !DILocation(line: 23, column: 6, scope: !8)
-- 
GitLab


From 0e05904664d8b9191a0aecab683bb92609b6b57b Mon Sep 17 00:00:00 2001
From: Mark de Wever <koraq@xs4all.nl>
Date: Tue, 12 Dec 2023 19:12:29 +0100
Subject: [PATCH 336/349] [libc++][doc] Updates module information. (#75003)

Adds the std.compat module and add support for CMake 3.28.
---
 libcxx/docs/Modules.rst | 39 ++++++++++++++++++++++-----------------
 1 file changed, 22 insertions(+), 17 deletions(-)

diff --git a/libcxx/docs/Modules.rst b/libcxx/docs/Modules.rst
index a16b3694cfae..5099e6095582 100644
--- a/libcxx/docs/Modules.rst
+++ b/libcxx/docs/Modules.rst
@@ -38,8 +38,8 @@ What works
 ~~~~~~~~~~
 
  * Building BMIs
- * Running tests using the ``std`` module
- * Using the ``std`` module in external projects
+ * Running tests using the ``std`` and ``std.compat`` module
+ * Using the ``std``  and ``std.compat`` module in external projects
  * The following "parts disabled" configuration options are supported
 
    * ``LIBCXX_ENABLE_LOCALIZATION``
@@ -65,10 +65,9 @@ Some of the current limitations
  * Requires CMake 3.26 for C++23 support
  * Requires CMake 3.27 for C++26 support
  * Requires Ninja 1.11
- * Requires a recent Clang 17
+ * Requires Clang 17
  * The path to the compiler may not be a symlink, ``clang-scan-deps`` does
    not handle that case properly
- * Only C++23 and C++26 are tested
  * Libc++ is not tested with modules instead of headers
  * The module ``.cppm`` files are not installed
  * Clang supports modules using GNU extensions, but libc++ does not work using
@@ -127,9 +126,13 @@ This is a small sample program that uses the module ``std``. It consists of a
 
 .. code-block:: cpp
 
-  import std;
+  import std; // When importing std.compat it's not needed to import std.
+  import std.compat;
 
-  int main() { std::cout << "Hello modular world\n"; }
+  int main() {
+    std::cout << "Hello modular world\n";
+    ::printf("Hello compat modular world\n");
+  }
 
 .. code-block:: cmake
 
@@ -142,7 +145,6 @@ This is a small sample program that uses the module ``std``. It consists of a
   # Set language version used
   #
 
-  # At the moment only C++23 is tested.
   set(CMAKE_CXX_STANDARD 23)
   set(CMAKE_CXX_STANDARD_REQUIRED YES)
   # Libc++ doesn't support compiler extensions for modules.
@@ -153,12 +155,16 @@ This is a small sample program that uses the module ``std``. It consists of a
   #
 
   # This is required to write your own modules in your project.
-  if(CMAKE_VERSION VERSION_LESS "3.27.0")
-    set(CMAKE_EXPERIMENTAL_CXX_MODULE_CMAKE_API "2182bf5c-ef0d-489a-91da-49dbc3090d2a")
+  if(CMAKE_VERSION VERSION_LESS "3.28.0")
+    if(CMAKE_VERSION VERSION_LESS "3.27.0")
+      set(CMAKE_EXPERIMENTAL_CXX_MODULE_CMAKE_API "2182bf5c-ef0d-489a-91da-49dbc3090d2a")
+    else()
+      set(CMAKE_EXPERIMENTAL_CXX_MODULE_CMAKE_API "aa1f7df0-828a-4fcd-9afc-2dc80491aca7")
+    endif()
+    set(CMAKE_EXPERIMENTAL_CXX_MODULE_DYNDEP 1)
   else()
-    set(CMAKE_EXPERIMENTAL_CXX_MODULE_CMAKE_API "aa1f7df0-828a-4fcd-9afc-2dc80491aca7")
+    cmake_policy(VERSION 3.28)
   endif()
-  set(CMAKE_EXPERIMENTAL_CXX_MODULE_DYNDEP 1)
 
   #
   # Import the modules from libc++
@@ -169,18 +175,16 @@ This is a small sample program that uses the module ``std``. It consists of a
     std
     URL "file://${LIBCXX_BUILD}/modules/c++/v1/"
     DOWNLOAD_EXTRACT_TIMESTAMP TRUE
+    SYSTEM
   )
-  FetchContent_GetProperties(std)
-  if(NOT std_POPULATED)
-    FetchContent_Populate(std)
-    add_subdirectory(${std_SOURCE_DIR} ${std_BINARY_DIR} EXCLUDE_FROM_ALL)
-  endif()
+  FetchContent_MakeAvailable(std)
 
   #
   # Adjust project compiler flags
   #
 
   add_compile_options($<$<COMPILE_LANGUAGE:CXX>:-fprebuilt-module-path=${CMAKE_BINARY_DIR}/_deps/std-build/CMakeFiles/std.dir/>)
+  add_compile_options($<$<COMPILE_LANGUAGE:CXX>:-fprebuilt-module-path=${CMAKE_BINARY_DIR}/_deps/std-build/CMakeFiles/std.compat.dir/>)
   add_compile_options($<$<COMPILE_LANGUAGE:CXX>:-nostdinc++>)
   # The include path needs to be set to be able to use macros from headers.
   # For example from, the headers <cassert> and <version>.
@@ -194,8 +198,9 @@ This is a small sample program that uses the module ``std``. It consists of a
   add_link_options($<$<COMPILE_LANGUAGE:CXX>:-nostdlib++>)
   add_link_options($<$<COMPILE_LANGUAGE:CXX>:-L${LIBCXX_BUILD}/lib>)
   add_link_options($<$<COMPILE_LANGUAGE:CXX>:-Wl,-rpath,${LIBCXX_BUILD}/lib>)
-  # Linking against std is required for CMake to get the proper dependencies
+  # Linking against the standard c++ library is required for CMake to get the proper dependencies.
   link_libraries(std c++)
+  link_libraries(std.compat c++)
 
   #
   # Add the project
-- 
GitLab


From 831484efa06bee798e218813cb1890ef108ed519 Mon Sep 17 00:00:00 2001
From: Fangrui Song <i@maskray.me>
Date: Tue, 12 Dec 2023 10:13:42 -0800
Subject: [PATCH 337/349] [DebugInfo] Fix duplicate DIFile when main file is
 preprocessed (#75022)

When the main file is preprocessed and we change `MainFileName` to the
original source file name (e.g. `a.i => a.c`), the source manager does
not contain `a.c`, but we incorrectly associate the DIFile(a.c) with
md5(a.i). This causes CGDebugInfo::emitFunctionStart to create a
duplicate DIFile and leads to a spurious "inconsistent use of MD5
checksums" warning.

```
% cat a.c
void f() {}
% clang -c -g a.c  # no warning
% clang -E a.c -o a.i && clang -g -S a.i && clang -g -c a.s
a.s:9:2: warning: inconsistent use of MD5 checksums
        .file   1 "a.c"
        ^
% grep DIFile a.ll
!1 = !DIFile(filename: "a.c", directory: "/tmp/c", checksumkind: CSK_MD5, checksum: "c5b2e246df7d5f53e176b097a0641c3d")
!11 = !DIFile(filename: "a.c", directory: "/tmp/c")
% grep 'file.*a.c' a.s
        .file   "a.c"
        .file   0 "/tmp/c" "a.c" md5 0x2d14ea70fee15102033eb8d899914cce
        .file   1 "a.c"
```

Fix #56378 by disassociating md5(a.i) with a.c.
---
 clang/lib/CodeGen/CGDebugInfo.cpp                 | 10 ++++++----
 clang/test/CodeGen/debug-info-preprocessed-file.i |  4 ++++
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/clang/lib/CodeGen/CGDebugInfo.cpp b/clang/lib/CodeGen/CGDebugInfo.cpp
index 7cf661994a29..37d7a6755d39 100644
--- a/clang/lib/CodeGen/CGDebugInfo.cpp
+++ b/clang/lib/CodeGen/CGDebugInfo.cpp
@@ -554,14 +554,16 @@ void CGDebugInfo::CreateCompileUnit() {
     // If the main file name provided is identical to the input file name, and
     // if the input file is a preprocessed source, use the module name for
     // debug info. The module name comes from the name specified in the first
-    // linemarker if the input is a preprocessed source.
+    // linemarker if the input is a preprocessed source. In this case we don't
+    // know the content to compute a checksum.
     if (MainFile->getName() == MainFileName &&
         FrontendOptions::getInputKindForExtension(
             MainFile->getName().rsplit('.').second)
-            .isPreprocessed())
+            .isPreprocessed()) {
       MainFileName = CGM.getModule().getName().str();
-
-    CSKind = computeChecksum(SM.getMainFileID(), Checksum);
+    } else {
+      CSKind = computeChecksum(SM.getMainFileID(), Checksum);
+    }
   }
 
   llvm::dwarf::SourceLanguage LangTag;
diff --git a/clang/test/CodeGen/debug-info-preprocessed-file.i b/clang/test/CodeGen/debug-info-preprocessed-file.i
index 23fd26525e3b..c8a2307d46c3 100644
--- a/clang/test/CodeGen/debug-info-preprocessed-file.i
+++ b/clang/test/CodeGen/debug-info-preprocessed-file.i
@@ -6,6 +6,10 @@
 # 1 "<built-in>" 2
 # 1 "preprocessed-input.c" 2
 
+/// The main file is preprocessed. We change it to preprocessed-input.c. Since
+/// the content is not available, we don't compute a checksum.
 // RUN: %clang -g -c -S -emit-llvm -o - %s | FileCheck %s
 // CHECK: !DICompileUnit(language: DW_LANG_C{{.*}}, file: ![[FILE:[0-9]+]]
 // CHECK: ![[FILE]] = !DIFile(filename: "/foo/bar/preprocessed-input.c"
+// CHECK-NOT: checksumkind:
+// CHECK-NOT: !DIFile(
-- 
GitLab


From 766bf140ffd6ce420426b80aa2cce0cb0d25ab7d Mon Sep 17 00:00:00 2001
From: Mark de Wever <koraq@xs4all.nl>
Date: Tue, 12 Dec 2023 19:14:13 +0100
Subject: [PATCH 338/349] [libc++][chrono] Fixes year_month year wrapping.
 (#74938)

Adding months to a year_month should wrap the year when the month
becomes greater than twelve or less than one.

This fixes the issue for year_month. Other classes with a year and month
do not have this issue. This has been verified and tests are added to
avoid possible regressions.

Also fixes some variable copy-paste errors in the tests.

Fixes https://github.com/llvm/llvm-project/issues/73162
---
 libcxx/include/__chrono/year_month.h          | 28 ++++++--
 .../plus_minus_equal_month.pass.cpp           | 10 +++
 .../time.cal.ym.nonmembers/minus.pass.cpp     |  9 ++-
 .../time.cal.ym.nonmembers/plus.pass.cpp      | 30 +++++----
 .../plus_minus_equal_month.pass.cpp           | 34 ++++++++++
 .../time.cal.ymd.nonmembers/plus.pass.cpp     | 51 +++++++++------
 .../plus_minus_equal_month.pass.cpp           | 28 +++++---
 .../minus.pass.cpp                            | 23 ++++---
 .../time.cal.ymdlast.nonmembers/plus.pass.cpp | 42 +++++++-----
 .../plus_minus_equal_month.pass.cpp           | 10 +++
 .../time.cal.ymwd.nonmembers/minus.pass.cpp   | 32 +++++----
 .../time.cal.ymwd.nonmembers/plus.pass.cpp    | 61 ++++++++++-------
 .../plus_minus_equal_month.pass.cpp           | 35 ++++++----
 .../minus.pass.cpp                            | 32 +++++----
 .../plus.pass.cpp                             | 65 +++++++++++--------
 15 files changed, 329 insertions(+), 161 deletions(-)

diff --git a/libcxx/include/__chrono/year_month.h b/libcxx/include/__chrono/year_month.h
index f4eea8427fc5..d1657b61015b 100644
--- a/libcxx/include/__chrono/year_month.h
+++ b/libcxx/include/__chrono/year_month.h
@@ -36,10 +36,10 @@ public:
         : __y_{__yval}, __m_{__mval} {}
     _LIBCPP_HIDE_FROM_ABI inline constexpr chrono::year  year()  const noexcept { return __y_; }
     _LIBCPP_HIDE_FROM_ABI inline constexpr chrono::month month() const noexcept { return __m_; }
-    _LIBCPP_HIDE_FROM_ABI inline constexpr year_month& operator+=(const months& __dm) noexcept { this->__m_ += __dm; return *this; }
-    _LIBCPP_HIDE_FROM_ABI inline constexpr year_month& operator-=(const months& __dm) noexcept { this->__m_ -= __dm; return *this; }
-    _LIBCPP_HIDE_FROM_ABI inline constexpr year_month& operator+=(const years& __dy)  noexcept { this->__y_ += __dy; return *this; }
-    _LIBCPP_HIDE_FROM_ABI inline constexpr year_month& operator-=(const years& __dy)  noexcept { this->__y_ -= __dy; return *this; }
+    _LIBCPP_HIDE_FROM_ABI inline constexpr year_month& operator+=(const months& __dm) noexcept;
+    _LIBCPP_HIDE_FROM_ABI inline constexpr year_month& operator-=(const months& __dm) noexcept;
+    _LIBCPP_HIDE_FROM_ABI inline constexpr year_month& operator+=(const years& __dy) noexcept;
+    _LIBCPP_HIDE_FROM_ABI inline constexpr year_month& operator-=(const years& __dy) noexcept;
     _LIBCPP_HIDE_FROM_ABI inline constexpr bool ok() const noexcept { return __y_.ok() && __m_.ok(); }
 };
 
@@ -92,6 +92,26 @@ _LIBCPP_HIDE_FROM_ABI constexpr
 year_month operator-(const year_month& __lhs, const years& __rhs) noexcept
 { return __lhs + -__rhs; }
 
+_LIBCPP_HIDE_FROM_ABI inline constexpr year_month& year_month::operator+=(const months& __dm) noexcept {
+  *this = *this + __dm;
+  return *this;
+}
+
+_LIBCPP_HIDE_FROM_ABI inline constexpr year_month& year_month::operator-=(const months& __dm) noexcept {
+  *this = *this - __dm;
+  return *this;
+}
+
+_LIBCPP_HIDE_FROM_ABI inline constexpr year_month& year_month::operator+=(const years& __dy) noexcept {
+  *this = *this + __dy;
+  return *this;
+}
+
+_LIBCPP_HIDE_FROM_ABI inline constexpr year_month& year_month::operator-=(const years& __dy) noexcept {
+  *this = *this - __dy;
+  return *this;
+}
+
 } // namespace chrono
 
 _LIBCPP_END_NAMESPACE_STD
diff --git a/libcxx/test/std/time/time.cal/time.cal.ym/time.cal.ym.members/plus_minus_equal_month.pass.cpp b/libcxx/test/std/time/time.cal/time.cal.ym/time.cal.ym.members/plus_minus_equal_month.pass.cpp
index 6d1273ead739..cc9fff83a1cf 100644
--- a/libcxx/test/std/time/time.cal/time.cal.ym/time.cal.ym.members/plus_minus_equal_month.pass.cpp
+++ b/libcxx/test/std/time/time.cal/time.cal.ym/time.cal.ym.members/plus_minus_equal_month.pass.cpp
@@ -38,6 +38,16 @@ constexpr bool test() {
     assert(ym.year() == y);
   }
 
+  { // Test year wrapping
+    year_month ym{year{2020}, month{4}};
+
+    ym += months{12};
+    assert((ym == year_month{year{2021}, month{4}}));
+
+    ym -= months{12};
+    assert((ym == year_month{year{2020}, month{4}}));
+  }
+
   return true;
 }
 
diff --git a/libcxx/test/std/time/time.cal/time.cal.ym/time.cal.ym.nonmembers/minus.pass.cpp b/libcxx/test/std/time/time.cal/time.cal.ym/time.cal.ym.nonmembers/minus.pass.cpp
index 5bacee9af7f8..977c566e745a 100644
--- a/libcxx/test/std/time/time.cal/time.cal.ym/time.cal.ym.nonmembers/minus.pass.cpp
+++ b/libcxx/test/std/time/time.cal/time.cal.ym/time.cal.ym.nonmembers/minus.pass.cpp
@@ -46,12 +46,17 @@ constexpr bool test() {
   { // year_month - months
 
     year_month ym{year{1234}, std::chrono::November};
-    for (int i = 0; i <= 10; ++i) // TODO test wrap-around
-    {
+    for (int i = 0; i <= 10; ++i) {
       year_month ym1 = ym - months{i};
       assert(static_cast<int>(ym1.year()) == 1234);
       assert(ym1.month() == month(11 - i));
     }
+    // Test the year wraps around.
+    for (int i = 12; i <= 15; ++i) {
+      year_month ym1 = ym - months{i};
+      assert(static_cast<int>(ym1.year()) == 1233);
+      assert(ym1.month() == month(11 - i + 12));
+    }
   }
 
   { // year_month - year_month
diff --git a/libcxx/test/std/time/time.cal/time.cal.ym/time.cal.ym.nonmembers/plus.pass.cpp b/libcxx/test/std/time/time.cal/time.cal.ym/time.cal.ym.nonmembers/plus.pass.cpp
index 315d74b75bbc..60747a29714d 100644
--- a/libcxx/test/std/time/time.cal/time.cal.ym/time.cal.ym.nonmembers/plus.pass.cpp
+++ b/libcxx/test/std/time/time.cal/time.cal.ym/time.cal.ym.nonmembers/plus.pass.cpp
@@ -29,10 +29,10 @@
 
 #include "test_macros.h"
 
-using year = std::chrono::year;
-using years = std::chrono::years;
-using month = std::chrono::month;
-using months = std::chrono::months;
+using year       = std::chrono::year;
+using years      = std::chrono::years;
+using month      = std::chrono::month;
+using months     = std::chrono::months;
 using year_month = std::chrono::year_month;
 
 // year_month + years
@@ -40,10 +40,8 @@ constexpr bool test_ym_plus_y() {
   ASSERT_NOEXCEPT(std::declval<year_month>() + std::declval<years>());
   ASSERT_NOEXCEPT(std::declval<years>() + std::declval<year_month>());
 
-  ASSERT_SAME_TYPE(
-      year_month, decltype(std::declval<year_month>() + std::declval<years>()));
-  ASSERT_SAME_TYPE(
-      year_month, decltype(std::declval<years>() + std::declval<year_month>()));
+  ASSERT_SAME_TYPE(year_month, decltype(std::declval<year_month>() + std::declval<years>()));
+  ASSERT_SAME_TYPE(year_month, decltype(std::declval<years>() + std::declval<year_month>()));
 
   year_month ym{year{1234}, std::chrono::January};
   for (int i = 0; i <= 10; ++i) {
@@ -64,10 +62,17 @@ constexpr bool test_ym_plus_m() {
   ASSERT_NOEXCEPT(std::declval<year_month>() + std::declval<months>());
   ASSERT_NOEXCEPT(std::declval<months>() + std::declval<year_month>());
 
-  ASSERT_SAME_TYPE(year_month, decltype(std::declval<year_month>() +
-                                        std::declval<months>()));
-  ASSERT_SAME_TYPE(year_month, decltype(std::declval<months>() +
-                                        std::declval<year_month>()));
+  ASSERT_SAME_TYPE(year_month, decltype(std::declval<year_month>() + std::declval<months>()));
+  ASSERT_SAME_TYPE(year_month, decltype(std::declval<months>() + std::declval<year_month>()));
+
+  {
+    // [time.cal.ym.nonmembers]/4
+    // Returns: A year_month value z such that z.ok() && z - ym == dm is true.
+    year_month ym = {year{1234}, std::chrono::January};
+    months dm     = months{42};
+    year_month z  = ym + dm;
+    assert(z.ok() && z - ym == dm);
+  }
 
   year_month ym{year{1234}, std::chrono::January};
   for (int i = 0; i <= 11; ++i) {
@@ -89,7 +94,6 @@ constexpr bool test_ym_plus_m() {
     assert(ym2.month() == month(1 + i % 12));
     assert(ym1 == ym2);
   }
-
   return true;
 }
 
diff --git a/libcxx/test/std/time/time.cal/time.cal.ymd/time.cal.ymd.members/plus_minus_equal_month.pass.cpp b/libcxx/test/std/time/time.cal/time.cal.ymd/time.cal.ymd.members/plus_minus_equal_month.pass.cpp
index f656d8f6cc05..40db399b110b 100644
--- a/libcxx/test/std/time/time.cal/time.cal.ymd/time.cal.ymd.members/plus_minus_equal_month.pass.cpp
+++ b/libcxx/test/std/time/time.cal/time.cal.ymd/time.cal.ymd.members/plus_minus_equal_month.pass.cpp
@@ -42,6 +42,40 @@ constexpr bool test() {
     assert(static_cast<unsigned>((ymd).month()) == i + 1);
   }
 
+  { // Validate the ok status when the day is not present in the new month.
+    year_month_day ymd{year{2020}, month{3}, day{31}};
+    ymd += months{1};
+    assert((ymd == year_month_day{year{2020}, month{4}, day{31}}));
+    assert(!ymd.ok());
+
+    ymd -= months{1};
+    assert((ymd == year_month_day{year{2020}, month{3}, day{31}}));
+    assert(ymd.ok());
+  }
+
+  { // Validate the ok status when the day becomes present in the new month.
+    year_month_day ymd{year{2020}, month{4}, day{31}};
+    assert(!ymd.ok());
+
+    ymd += months{1};
+    assert((ymd == year_month_day{year{2020}, month{5}, day{31}}));
+    assert(ymd.ok());
+
+    ymd -= months{2};
+    assert((ymd == year_month_day{year{2020}, month{3}, day{31}}));
+    assert(ymd.ok());
+  }
+
+  { // Test year wrapping
+    year_month_day ymd{year{2020}, month{4}, day{31}};
+
+    ymd += months{12};
+    assert((ymd == year_month_day{year{2021}, month{4}, day{31}}));
+
+    ymd -= months{12};
+    assert((ymd == year_month_day{year{2020}, month{4}, day{31}}));
+  }
+
   return true;
 }
 
diff --git a/libcxx/test/std/time/time.cal/time.cal.ymd/time.cal.ymd.nonmembers/plus.pass.cpp b/libcxx/test/std/time/time.cal/time.cal.ymd/time.cal.ymd.nonmembers/plus.pass.cpp
index 27626e40fceb..b172cb138457 100644
--- a/libcxx/test/std/time/time.cal/time.cal.ymd/time.cal.ymd.nonmembers/plus.pass.cpp
+++ b/libcxx/test/std/time/time.cal/time.cal.ymd/time.cal.ymd.nonmembers/plus.pass.cpp
@@ -39,32 +39,43 @@ using year_month_day = std::chrono::year_month_day;
 constexpr bool test() {
   { // year_month_day + months
     year_month_day ym{year{1234}, std::chrono::January, day{12}};
-    for (int i = 0; i <= 10; ++i) // TODO test wrap-around
-    {
-      year_month_day ym1 = ym + months{i};
-      year_month_day ym2 = months{i} + ym;
-      assert(static_cast<int>(ym1.year()) == 1234);
-      assert(static_cast<int>(ym2.year()) == 1234);
-      assert(ym1.month() == month(1 + i));
-      assert(ym2.month() == month(1 + i));
-      assert(ym1.day() == day{12});
-      assert(ym2.day() == day{12});
-      assert(ym1 == ym2);
+    for (int i = 0; i <= 10; ++i) {
+      year_month_day ymd1 = ym + months{i};
+      year_month_day ymd2 = months{i} + ym;
+      assert(static_cast<int>(ymd1.year()) == 1234);
+      assert(static_cast<int>(ymd2.year()) == 1234);
+      assert(ymd1.month() == month(1 + i));
+      assert(ymd2.month() == month(1 + i));
+      assert(ymd1.day() == day{12});
+      assert(ymd2.day() == day{12});
+      assert(ymd1 == ymd2);
+    }
+    // Test the year wraps around.
+    for (int i = 12; i <= 15; ++i) {
+      year_month_day ymd1 = ym + months{i};
+      year_month_day ymd2 = months{i} + ym;
+      assert(static_cast<int>(ymd1.year()) == 1235);
+      assert(static_cast<int>(ymd2.year()) == 1235);
+      assert(ymd1.month() == month(1 + i - 12));
+      assert(ymd2.month() == month(1 + i - 12));
+      assert(ymd1.day() == day{12});
+      assert(ymd2.day() == day{12});
+      assert(ymd1 == ymd2);
     }
   }
 
   { // year_month_day + years
     year_month_day ym{year{1234}, std::chrono::January, day{12}};
     for (int i = 0; i <= 10; ++i) {
-      year_month_day ym1 = ym + years{i};
-      year_month_day ym2 = years{i} + ym;
-      assert(static_cast<int>(ym1.year()) == i + 1234);
-      assert(static_cast<int>(ym2.year()) == i + 1234);
-      assert(ym1.month() == std::chrono::January);
-      assert(ym2.month() == std::chrono::January);
-      assert(ym1.day() == day{12});
-      assert(ym2.day() == day{12});
-      assert(ym1 == ym2);
+      year_month_day ymd1 = ym + years{i};
+      year_month_day ymd2 = years{i} + ym;
+      assert(static_cast<int>(ymd1.year()) == i + 1234);
+      assert(static_cast<int>(ymd2.year()) == i + 1234);
+      assert(ymd1.month() == std::chrono::January);
+      assert(ymd2.month() == std::chrono::January);
+      assert(ymd1.day() == day{12});
+      assert(ymd2.day() == day{12});
+      assert(ymd1 == ymd2);
     }
   }
 
diff --git a/libcxx/test/std/time/time.cal/time.cal.ymdlast/time.cal.ymdlast.members/plus_minus_equal_month.pass.cpp b/libcxx/test/std/time/time.cal/time.cal.ymdlast/time.cal.ymdlast.members/plus_minus_equal_month.pass.cpp
index dfa0f002bfb9..1c0847959601 100644
--- a/libcxx/test/std/time/time.cal/time.cal.ymdlast/time.cal.ymdlast.members/plus_minus_equal_month.pass.cpp
+++ b/libcxx/test/std/time/time.cal/time.cal.ymdlast/time.cal.ymdlast.members/plus_minus_equal_month.pass.cpp
@@ -29,15 +29,25 @@ constexpr bool test() {
   for (unsigned i = 0; i <= 10; ++i) {
     year y{1234};
     month_day_last mdl{month{i}};
-    year_month_day_last ym(y, mdl);
-    assert(static_cast<unsigned>((ym += months{2}).month()) == i + 2);
-    assert(ym.year() == y);
-    assert(static_cast<unsigned>((ym).month()) == i + 2);
-    assert(ym.year() == y);
-    assert(static_cast<unsigned>((ym -= months{1}).month()) == i + 1);
-    assert(ym.year() == y);
-    assert(static_cast<unsigned>((ym).month()) == i + 1);
-    assert(ym.year() == y);
+    year_month_day_last ymdl(y, mdl);
+    assert(static_cast<unsigned>((ymdl += months{2}).month()) == i + 2);
+    assert(ymdl.year() == y);
+    assert(static_cast<unsigned>((ymdl).month()) == i + 2);
+    assert(ymdl.year() == y);
+    assert(static_cast<unsigned>((ymdl -= months{1}).month()) == i + 1);
+    assert(ymdl.year() == y);
+    assert(static_cast<unsigned>((ymdl).month()) == i + 1);
+    assert(ymdl.year() == y);
+  }
+
+  { // Test year wrapping
+    year_month_day_last ymdl{year{2020}, month_day_last{month{4}}};
+
+    ymdl += months{12};
+    assert((ymdl == year_month_day_last{year{2021}, month_day_last{month{4}}}));
+
+    ymdl -= months{12};
+    assert((ymdl == year_month_day_last{year{2020}, month_day_last{month{4}}}));
   }
 
   return true;
diff --git a/libcxx/test/std/time/time.cal/time.cal.ymdlast/time.cal.ymdlast.nonmembers/minus.pass.cpp b/libcxx/test/std/time/time.cal/time.cal.ymdlast/time.cal.ymdlast.nonmembers/minus.pass.cpp
index 009790a450e9..22d1acfbe282 100644
--- a/libcxx/test/std/time/time.cal/time.cal.ymdlast/time.cal.ymdlast.nonmembers/minus.pass.cpp
+++ b/libcxx/test/std/time/time.cal/time.cal.ymdlast/time.cal.ymdlast.nonmembers/minus.pass.cpp
@@ -38,22 +38,27 @@ constexpr bool test() {
 
   { // year_month_day_last - years
 
-    year_month_day_last ym{year{1234}, month_day_last{December}};
+    year_month_day_last ymdl{year{1234}, month_day_last{December}};
     for (int i = 0; i <= 10; ++i) {
-      year_month_day_last ym1 = ym - years{i};
-      assert(static_cast<int>(ym1.year()) == 1234 - i);
-      assert(ym1.month() == December);
+      year_month_day_last ymdl1 = ymdl - years{i};
+      assert(static_cast<int>(ymdl1.year()) == 1234 - i);
+      assert(ymdl1.month() == December);
     }
   }
 
   { // year_month_day_last - months
 
-    // TODO test wrapping
-    year_month_day_last ym{year{1234}, month_day_last{December}};
+    year_month_day_last ymdl{year{1234}, month_day_last{December}};
     for (unsigned i = 0; i <= 10; ++i) {
-      year_month_day_last ym1 = ym - months{i};
-      assert(static_cast<int>(ym1.year()) == 1234);
-      assert(static_cast<unsigned>(ym1.month()) == 12U - i);
+      year_month_day_last ymdl1 = ymdl - months{i};
+      assert(static_cast<int>(ymdl1.year()) == 1234);
+      assert(static_cast<unsigned>(ymdl1.month()) == 12U - i);
+    }
+    // Test the year wraps around.
+    for (unsigned i = 12; i <= 15; ++i) {
+      year_month_day_last ymdl1 = ymdl - months{i};
+      assert(static_cast<int>(ymdl1.year()) == 1233);
+      assert(static_cast<unsigned>(ymdl1.month()) == 12U - i + 12);
     }
   }
 
diff --git a/libcxx/test/std/time/time.cal/time.cal.ymdlast/time.cal.ymdlast.nonmembers/plus.pass.cpp b/libcxx/test/std/time/time.cal/time.cal.ymdlast/time.cal.ymdlast.nonmembers/plus.pass.cpp
index 4cbc3d1a1994..1a4609e761ba 100644
--- a/libcxx/test/std/time/time.cal/time.cal.ymdlast/time.cal.ymdlast.nonmembers/plus.pass.cpp
+++ b/libcxx/test/std/time/time.cal/time.cal.ymdlast/time.cal.ymdlast.nonmembers/plus.pass.cpp
@@ -49,29 +49,37 @@ constexpr bool test() {
 
   { // year_month_day_last + months
     year_month_day_last ym{year{1234}, month_day_last{January}};
-    for (int i = 0; i <= 10; ++i) // TODO test wrap-around
-    {
-      year_month_day_last ym1 = ym + months{i};
-      year_month_day_last ym2 = months{i} + ym;
-      assert(static_cast<int>(ym1.year()) == 1234);
-      assert(static_cast<int>(ym2.year()) == 1234);
-      assert(ym1.month() == month(1 + i));
-      assert(ym2.month() == month(1 + i));
-      assert(ym1 == ym2);
+    for (int i = 0; i <= 10; ++i) {
+      year_month_day_last ymdl1 = ym + months{i};
+      year_month_day_last ymdl2 = months{i} + ym;
+      assert(static_cast<int>(ymdl1.year()) == 1234);
+      assert(static_cast<int>(ymdl2.year()) == 1234);
+      assert(ymdl1.month() == month(1 + i));
+      assert(ymdl2.month() == month(1 + i));
+      assert(ymdl1 == ymdl2);
+    }
+    // Test the year wraps around.
+    for (int i = 12; i <= 15; ++i) {
+      year_month_day_last ymdl1 = ym + months{i};
+      year_month_day_last ymdl2 = months{i} + ym;
+      assert(static_cast<int>(ymdl1.year()) == 1235);
+      assert(static_cast<int>(ymdl2.year()) == 1235);
+      assert(ymdl1.month() == month(1 + i - 12));
+      assert(ymdl2.month() == month(1 + i - 12));
+      assert(ymdl1 == ymdl2);
     }
   }
 
   { // year_month_day_last + years
-
     year_month_day_last ym{year{1234}, month_day_last{January}};
     for (int i = 0; i <= 10; ++i) {
-      year_month_day_last ym1 = ym + years{i};
-      year_month_day_last ym2 = years{i} + ym;
-      assert(static_cast<int>(ym1.year()) == i + 1234);
-      assert(static_cast<int>(ym2.year()) == i + 1234);
-      assert(ym1.month() == std::chrono::January);
-      assert(ym2.month() == std::chrono::January);
-      assert(ym1 == ym2);
+      year_month_day_last ymdl1 = ym + years{i};
+      year_month_day_last ymdl2 = years{i} + ym;
+      assert(static_cast<int>(ymdl1.year()) == i + 1234);
+      assert(static_cast<int>(ymdl2.year()) == i + 1234);
+      assert(ymdl1.month() == std::chrono::January);
+      assert(ymdl2.month() == std::chrono::January);
+      assert(ymdl1 == ymdl2);
     }
   }
 
diff --git a/libcxx/test/std/time/time.cal/time.cal.ymwd/time.cal.ymwd.members/plus_minus_equal_month.pass.cpp b/libcxx/test/std/time/time.cal/time.cal.ymwd/time.cal.ymwd.members/plus_minus_equal_month.pass.cpp
index 8b49540be3fa..6aaab2dbfb31 100644
--- a/libcxx/test/std/time/time.cal/time.cal.ymwd/time.cal.ymwd.members/plus_minus_equal_month.pass.cpp
+++ b/libcxx/test/std/time/time.cal/time.cal.ymwd/time.cal.ymwd.members/plus_minus_equal_month.pass.cpp
@@ -54,6 +54,16 @@ constexpr bool test() {
     assert(ymwd.index() == 2);
   }
 
+  { // Test year wrapping
+    year_month_weekday ymwd{year{2020}, month{4}, weekday_indexed{Tuesday, 2}};
+
+    ymwd += months{12};
+    assert((ymwd == year_month_weekday{year{2021}, month{4}, weekday_indexed{Tuesday, 2}}));
+
+    ymwd -= months{12};
+    assert((ymwd == year_month_weekday{year{2020}, month{4}, weekday_indexed{Tuesday, 2}}));
+  }
+
   return true;
 }
 
diff --git a/libcxx/test/std/time/time.cal/time.cal.ymwd/time.cal.ymwd.nonmembers/minus.pass.cpp b/libcxx/test/std/time/time.cal/time.cal.ymwd/time.cal.ymwd.nonmembers/minus.pass.cpp
index 2ab3462d7f7d..5546d34ca22d 100644
--- a/libcxx/test/std/time/time.cal/time.cal.ymwd/time.cal.ymwd.nonmembers/minus.pass.cpp
+++ b/libcxx/test/std/time/time.cal/time.cal.ymwd/time.cal.ymwd.nonmembers/minus.pass.cpp
@@ -35,24 +35,32 @@ constexpr bool test() {
   constexpr weekday Tuesday = std::chrono::Tuesday;
 
   { // year_month_weekday - years
-    year_month_weekday ym{year{1234}, November, weekday_indexed{Tuesday, 1}};
+    year_month_weekday ymwd{year{1234}, November, weekday_indexed{Tuesday, 1}};
     for (int i = 0; i <= 10; ++i) {
-      year_month_weekday ym1 = ym - years{i};
-      assert(static_cast<int>(ym1.year()) == 1234 - i);
-      assert(ym1.month() == November);
-      assert(ym1.weekday() == Tuesday);
-      assert(ym1.index() == 1);
+      year_month_weekday ymwd1 = ymwd - years{i};
+      assert(static_cast<int>(ymwd1.year()) == 1234 - i);
+      assert(ymwd1.month() == November);
+      assert(ymwd1.weekday() == Tuesday);
+      assert(ymwd1.index() == 1);
     }
   }
 
   { // year_month_weekday - months
-    year_month_weekday ym{year{1234}, November, weekday_indexed{Tuesday, 2}};
+    year_month_weekday ymwd{year{1234}, November, weekday_indexed{Tuesday, 2}};
     for (unsigned i = 1; i <= 10; ++i) {
-      year_month_weekday ym1 = ym - months{i};
-      assert(ym1.year() == year{1234});
-      assert(ym1.month() == month{11 - i});
-      assert(ym1.weekday() == Tuesday);
-      assert(ym1.index() == 2);
+      year_month_weekday ymwd1 = ymwd - months{i};
+      assert(ymwd1.year() == year{1234});
+      assert(ymwd1.month() == month{11 - i});
+      assert(ymwd1.weekday() == Tuesday);
+      assert(ymwd1.index() == 2);
+    }
+    // Test the year wraps around.
+    for (unsigned i = 12; i <= 15; ++i) {
+      year_month_weekday ymwd1 = ymwd - months{i};
+      assert(ymwd1.year() == year{1233});
+      assert(ymwd1.month() == month{11 - i + 12});
+      assert(ymwd1.weekday() == Tuesday);
+      assert(ymwd1.index() == 2);
     }
   }
 
diff --git a/libcxx/test/std/time/time.cal/time.cal.ymwd/time.cal.ymwd.nonmembers/plus.pass.cpp b/libcxx/test/std/time/time.cal/time.cal.ymwd/time.cal.ymwd.nonmembers/plus.pass.cpp
index e757d81db4a1..1601e8fecb7a 100644
--- a/libcxx/test/std/time/time.cal/time.cal.ymwd/time.cal.ymwd.nonmembers/plus.pass.cpp
+++ b/libcxx/test/std/time/time.cal/time.cal.ymwd/time.cal.ymwd.nonmembers/plus.pass.cpp
@@ -43,36 +43,49 @@ constexpr bool test() {
 
   { // year_month_weekday + months (and switched)
     year_month_weekday ym{year{1234}, January, weekday_indexed{Tuesday, 3}};
-    for (int i = 0; i <= 10; ++i) // TODO test wrap-around
-    {
-      year_month_weekday ym1 = ym + months{i};
-      year_month_weekday ym2 = months{i} + ym;
-      assert(static_cast<int>(ym1.year()) == 1234);
-      assert(static_cast<int>(ym2.year()) == 1234);
-      assert(ym1.month() == month(1 + i));
-      assert(ym2.month() == month(1 + i));
-      assert(ym1.weekday() == Tuesday);
-      assert(ym2.weekday() == Tuesday);
-      assert(ym1.index() == 3);
-      assert(ym2.index() == 3);
-      assert(ym1 == ym2);
+    for (int i = 0; i <= 10; ++i) {
+      year_month_weekday ymwd1 = ym + months{i};
+      year_month_weekday ymwd2 = months{i} + ym;
+      assert(static_cast<int>(ymwd1.year()) == 1234);
+      assert(static_cast<int>(ymwd2.year()) == 1234);
+      assert(ymwd1.month() == month(1 + i));
+      assert(ymwd2.month() == month(1 + i));
+      assert(ymwd1.weekday() == Tuesday);
+      assert(ymwd2.weekday() == Tuesday);
+      assert(ymwd1.index() == 3);
+      assert(ymwd2.index() == 3);
+      assert(ymwd1 == ymwd2);
+    }
+    // Test the year wraps around.
+    for (int i = 12; i <= 15; ++i) {
+      year_month_weekday ymwd1 = ym + months{i};
+      year_month_weekday ymwd2 = months{i} + ym;
+      assert(static_cast<int>(ymwd1.year()) == 1235);
+      assert(static_cast<int>(ymwd2.year()) == 1235);
+      assert(ymwd1.month() == month(1 + i - 12));
+      assert(ymwd2.month() == month(1 + i - 12));
+      assert(ymwd1.weekday() == Tuesday);
+      assert(ymwd2.weekday() == Tuesday);
+      assert(ymwd1.index() == 3);
+      assert(ymwd2.index() == 3);
+      assert(ymwd1 == ymwd2);
     }
   }
 
   { // year_month_weekday + years (and switched)
     year_month_weekday ym{year{1234}, std::chrono::January, weekday_indexed{Tuesday, 3}};
     for (int i = 0; i <= 10; ++i) {
-      year_month_weekday ym1 = ym + years{i};
-      year_month_weekday ym2 = years{i} + ym;
-      assert(static_cast<int>(ym1.year()) == i + 1234);
-      assert(static_cast<int>(ym2.year()) == i + 1234);
-      assert(ym1.month() == January);
-      assert(ym2.month() == January);
-      assert(ym1.weekday() == Tuesday);
-      assert(ym2.weekday() == Tuesday);
-      assert(ym1.index() == 3);
-      assert(ym2.index() == 3);
-      assert(ym1 == ym2);
+      year_month_weekday ymwd1 = ym + years{i};
+      year_month_weekday ymwd2 = years{i} + ym;
+      assert(static_cast<int>(ymwd1.year()) == i + 1234);
+      assert(static_cast<int>(ymwd2.year()) == i + 1234);
+      assert(ymwd1.month() == January);
+      assert(ymwd2.month() == January);
+      assert(ymwd1.weekday() == Tuesday);
+      assert(ymwd2.weekday() == Tuesday);
+      assert(ymwd1.index() == 3);
+      assert(ymwd2.index() == 3);
+      assert(ymwd1 == ymwd2);
     }
   }
 
diff --git a/libcxx/test/std/time/time.cal/time.cal.ymwdlast/time.cal.ymwdlast.members/plus_minus_equal_month.pass.cpp b/libcxx/test/std/time/time.cal/time.cal.ymwdlast/time.cal.ymwdlast.members/plus_minus_equal_month.pass.cpp
index 10c7902cf2f4..ff52b1466cef 100644
--- a/libcxx/test/std/time/time.cal/time.cal.ymwdlast/time.cal.ymwdlast.members/plus_minus_equal_month.pass.cpp
+++ b/libcxx/test/std/time/time.cal/time.cal.ymwdlast/time.cal.ymwdlast.members/plus_minus_equal_month.pass.cpp
@@ -31,25 +31,34 @@ constexpr bool test() {
 
   for (unsigned i = 0; i <= 10; ++i) {
     year y{1234};
-    year_month_weekday_last ymwd(y, month{i}, weekday_last{Tuesday});
+    year_month_weekday_last ymwdl(y, month{i}, weekday_last{Tuesday});
 
-    assert(static_cast<unsigned>((ymwd += months{2}).month()) == i + 2);
-    assert(ymwd.year() == y);
-    assert(ymwd.weekday() == Tuesday);
+    assert(static_cast<unsigned>((ymwdl += months{2}).month()) == i + 2);
+    assert(ymwdl.year() == y);
+    assert(ymwdl.weekday() == Tuesday);
 
-    assert(static_cast<unsigned>((ymwd).month()) == i + 2);
-    assert(ymwd.year() == y);
-    assert(ymwd.weekday() == Tuesday);
+    assert(static_cast<unsigned>((ymwdl).month()) == i + 2);
+    assert(ymwdl.year() == y);
+    assert(ymwdl.weekday() == Tuesday);
 
-    assert(static_cast<unsigned>((ymwd -= months{1}).month()) == i + 1);
-    assert(ymwd.year() == y);
-    assert(ymwd.weekday() == Tuesday);
+    assert(static_cast<unsigned>((ymwdl -= months{1}).month()) == i + 1);
+    assert(ymwdl.year() == y);
+    assert(ymwdl.weekday() == Tuesday);
 
-    assert(static_cast<unsigned>((ymwd).month()) == i + 1);
-    assert(ymwd.year() == y);
-    assert(ymwd.weekday() == Tuesday);
+    assert(static_cast<unsigned>((ymwdl).month()) == i + 1);
+    assert(ymwdl.year() == y);
+    assert(ymwdl.weekday() == Tuesday);
   }
 
+  { // Test year wrapping
+    year_month_weekday_last ymwdl{year{2020}, month{4}, weekday_last{Tuesday}};
+
+    ymwdl += months{12};
+    assert((ymwdl == year_month_weekday_last{year{2021}, month{4}, weekday_last{Tuesday}}));
+
+    ymwdl -= months{12};
+    assert((ymwdl == year_month_weekday_last{year{2020}, month{4}, weekday_last{Tuesday}}));
+  }
   return true;
 }
 
diff --git a/libcxx/test/std/time/time.cal/time.cal.ymwdlast/time.cal.ymwdlast.nonmembers/minus.pass.cpp b/libcxx/test/std/time/time.cal/time.cal.ymwdlast/time.cal.ymwdlast.nonmembers/minus.pass.cpp
index a0dc7545dc8a..6fe2ec3b6606 100644
--- a/libcxx/test/std/time/time.cal/time.cal.ymwdlast/time.cal.ymwdlast.nonmembers/minus.pass.cpp
+++ b/libcxx/test/std/time/time.cal/time.cal.ymwdlast/time.cal.ymwdlast.nonmembers/minus.pass.cpp
@@ -35,24 +35,32 @@ constexpr bool test() {
   constexpr weekday Tuesday = std::chrono::Tuesday;
 
   { // year_month_weekday_last - years
-    year_month_weekday_last ym{year{1234}, October, weekday_last{Tuesday}};
+    year_month_weekday_last ymwdl{year{1234}, October, weekday_last{Tuesday}};
     for (int i = 0; i <= 10; ++i) {
-      year_month_weekday_last ym1 = ym - years{i};
-      assert(ym1.year() == year{1234 - i});
-      assert(ym1.month() == October);
-      assert(ym1.weekday() == Tuesday);
-      assert(ym1.weekday_last() == weekday_last{Tuesday});
+      year_month_weekday_last ymwdl1 = ymwdl - years{i};
+      assert(ymwdl1.year() == year{1234 - i});
+      assert(ymwdl1.month() == October);
+      assert(ymwdl1.weekday() == Tuesday);
+      assert(ymwdl1.weekday_last() == weekday_last{Tuesday});
     }
   }
 
   { // year_month_weekday_last - months
-    year_month_weekday_last ym{year{1234}, October, weekday_last{Tuesday}};
+    year_month_weekday_last ymwdl{year{1234}, October, weekday_last{Tuesday}};
     for (unsigned i = 0; i < 10; ++i) {
-      year_month_weekday_last ym1 = ym - months{i};
-      assert(ym1.year() == year{1234});
-      assert(ym1.month() == month{10 - i});
-      assert(ym1.weekday() == Tuesday);
-      assert(ym1.weekday_last() == weekday_last{Tuesday});
+      year_month_weekday_last ymwdl1 = ymwdl - months{i};
+      assert(ymwdl1.year() == year{1234});
+      assert(ymwdl1.month() == month{10 - i});
+      assert(ymwdl1.weekday() == Tuesday);
+      assert(ymwdl1.weekday_last() == weekday_last{Tuesday});
+    }
+    // Test the year wraps around.
+    for (unsigned i = 12; i < 15; ++i) {
+      year_month_weekday_last ymwdl1 = ymwdl - months{i};
+      assert(ymwdl1.year() == year{1233});
+      assert(ymwdl1.month() == month{10 - i + 12});
+      assert(ymwdl1.weekday() == Tuesday);
+      assert(ymwdl1.weekday_last() == weekday_last{Tuesday});
     }
   }
 
diff --git a/libcxx/test/std/time/time.cal/time.cal.ymwdlast/time.cal.ymwdlast.nonmembers/plus.pass.cpp b/libcxx/test/std/time/time.cal/time.cal.ymwdlast/time.cal.ymwdlast.nonmembers/plus.pass.cpp
index 7529180d5731..560b2fcde055 100644
--- a/libcxx/test/std/time/time.cal/time.cal.ymwdlast/time.cal.ymwdlast.nonmembers/plus.pass.cpp
+++ b/libcxx/test/std/time/time.cal/time.cal.ymwdlast/time.cal.ymwdlast.nonmembers/plus.pass.cpp
@@ -41,37 +41,50 @@ constexpr bool test() {
   constexpr month January   = std::chrono::January;
 
   { // year_month_weekday_last + months
-    year_month_weekday_last ym{year{1234}, January, weekday_last{Tuesday}};
-    for (int i = 0; i <= 10; ++i) // TODO test wrap-around
-    {
-      year_month_weekday_last ym1 = ym + months{i};
-      year_month_weekday_last ym2 = months{i} + ym;
-      assert(ym1.year() == year(1234));
-      assert(ym2.year() == year(1234));
-      assert(ym1.month() == month(1 + i));
-      assert(ym2.month() == month(1 + i));
-      assert(ym1.weekday() == Tuesday);
-      assert(ym2.weekday() == Tuesday);
-      assert(ym1.weekday_last() == weekday_last{Tuesday});
-      assert(ym2.weekday_last() == weekday_last{Tuesday});
-      assert(ym1 == ym2);
+    year_month_weekday_last ymwdl{year{1234}, January, weekday_last{Tuesday}};
+    for (int i = 0; i <= 10; ++i) {
+      year_month_weekday_last ymwdl1 = ymwdl + months{i};
+      year_month_weekday_last ymwdl2 = months{i} + ymwdl;
+      assert(ymwdl1.year() == year{1234});
+      assert(ymwdl2.year() == year{1234});
+      assert(ymwdl1.month() == month(1 + i));
+      assert(ymwdl2.month() == month(1 + i));
+      assert(ymwdl1.weekday() == Tuesday);
+      assert(ymwdl2.weekday() == Tuesday);
+      assert(ymwdl1.weekday_last() == weekday_last{Tuesday});
+      assert(ymwdl2.weekday_last() == weekday_last{Tuesday});
+      assert(ymwdl1 == ymwdl2);
+    }
+    // Test the year wraps around.
+    for (int i = 12; i <= 15; ++i) {
+      year_month_weekday_last ymwdl1 = ymwdl + months{i};
+      year_month_weekday_last ymwdl2 = months{i} + ymwdl;
+      assert(ymwdl1.year() == year{1235});
+      assert(ymwdl2.year() == year{1235});
+      assert(ymwdl1.month() == month(1 + i - 12));
+      assert(ymwdl2.month() == month(1 + i - 12));
+      assert(ymwdl1.weekday() == Tuesday);
+      assert(ymwdl2.weekday() == Tuesday);
+      assert(ymwdl1.weekday_last() == weekday_last{Tuesday});
+      assert(ymwdl2.weekday_last() == weekday_last{Tuesday});
+      assert(ymwdl1 == ymwdl2);
     }
   }
 
   { // year_month_weekday_last + years
-    year_month_weekday_last ym{year{1234}, std::chrono::January, weekday_last{Tuesday}};
+    year_month_weekday_last ymwdl{year{1234}, std::chrono::January, weekday_last{Tuesday}};
     for (int i = 0; i <= 10; ++i) {
-      year_month_weekday_last ym1 = ym + years{i};
-      year_month_weekday_last ym2 = years{i} + ym;
-      assert(ym1.year() == year(1234 + i));
-      assert(ym2.year() == year(1234 + i));
-      assert(ym1.month() == January);
-      assert(ym2.month() == January);
-      assert(ym1.weekday() == Tuesday);
-      assert(ym2.weekday() == Tuesday);
-      assert(ym1.weekday_last() == weekday_last{Tuesday});
-      assert(ym2.weekday_last() == weekday_last{Tuesday});
-      assert(ym1 == ym2);
+      year_month_weekday_last ymwdl1 = ymwdl + years{i};
+      year_month_weekday_last ymwdl2 = years{i} + ymwdl;
+      assert(ymwdl1.year() == year(1234 + i));
+      assert(ymwdl2.year() == year(1234 + i));
+      assert(ymwdl1.month() == January);
+      assert(ymwdl2.month() == January);
+      assert(ymwdl1.weekday() == Tuesday);
+      assert(ymwdl2.weekday() == Tuesday);
+      assert(ymwdl1.weekday_last() == weekday_last{Tuesday});
+      assert(ymwdl2.weekday_last() == weekday_last{Tuesday});
+      assert(ymwdl1 == ymwdl2);
     }
   }
 
-- 
GitLab


From 42e4967140e345923a43f809ba69be57200f46ae Mon Sep 17 00:00:00 2001
From: Fangrui Song <i@maskray.me>
Date: Tue, 12 Dec 2023 10:14:36 -0800
Subject: [PATCH 339/349] [ELF] Don't create copy relocation/canonical PLT
 entry for a defined symbol (#75095)

Copy relocations and canonical PLT entries are for symbols defined in a
DSO. Currently we create them even for a `Defined`, possibly leading to
an output that won't work at run-time (e.g. R_X86_64_JUMP_SLOT
referencing a null symbol).
```
% cat a.s
.globl _start, main
.type main, @function
_start: main: ret

.rodata
.quad main
% clang -fuse-ld=lld -pie -nostdlib a.s
% readelf -Wr a.out

Relocation section '.rela.plt' at offset 0x290 contains 1 entry:
    Offset             Info             Type               Symbol's Value  Symbol's Name + Addend
00000000000033b8  0000000000000007 R_X86_64_JUMP_SLOT                        12b0
```

Report an error instead for the default `-z text` mode. GNU ld reports
an error in `-z text` mode as well.
---
 lld/ELF/Relocations.cpp             | 4 ++--
 lld/test/ELF/got32-i386.s           | 2 +-
 lld/test/ELF/got32x-i386.s          | 2 +-
 lld/test/ELF/x86-64-dyn-rel-error.s | 6 +++---
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/lld/ELF/Relocations.cpp b/lld/ELF/Relocations.cpp
index fe3d7f419e84..210b4d1eb1a7 100644
--- a/lld/ELF/Relocations.cpp
+++ b/lld/ELF/Relocations.cpp
@@ -1158,8 +1158,8 @@ void RelocationScanner::processAux(RelExpr expr, RelType type, uint64_t offset,
   }
 
   // When producing an executable, we can perform copy relocations (for
-  // STT_OBJECT) and canonical PLT (for STT_FUNC).
-  if (!config->shared) {
+  // STT_OBJECT) and canonical PLT (for STT_FUNC) if sym is defined by a DSO.
+  if (!config->shared && sym.isShared()) {
     if (!canDefineSymbolInExecutable(sym)) {
       errorOrWarn("cannot preempt symbol: " + toString(sym) +
                   getLocation(*sec, sym, offset));
diff --git a/lld/test/ELF/got32-i386.s b/lld/test/ELF/got32-i386.s
index f44719f16dc1..9416e3667b8d 100644
--- a/lld/test/ELF/got32-i386.s
+++ b/lld/test/ELF/got32-i386.s
@@ -20,4 +20,4 @@ _start:
 # CHECK-NEXT:   4010f5: 8b 1d {{.*}}  movl 4202748, %ebx
 
 # RUN: not ld.lld %t.o -o /dev/null -pie 2>&1 | FileCheck %s --check-prefix=ERR
-# ERR: error: symbol 'foo' cannot be preempted; recompile with -fPIE
+# ERR: error: relocation R_386_GOT32 cannot be used against symbol 'foo'; recompile with -fPIC
diff --git a/lld/test/ELF/got32x-i386.s b/lld/test/ELF/got32x-i386.s
index fb12d99bd0fe..3b19de9c98a0 100644
--- a/lld/test/ELF/got32x-i386.s
+++ b/lld/test/ELF/got32x-i386.s
@@ -43,4 +43,4 @@
 
 # RUN: not ld.lld %S/Inputs/i386-got32x-baseless.elf -o /dev/null -pie 2>&1 | \
 # RUN:   FileCheck %s --check-prefix=ERR
-# ERR-COUNT-2: error: symbol 'foo' cannot be preempted; recompile with -fPIE
+# ERR-COUNT-2: error: relocation R_386_GOT32X cannot be used against symbol 'foo'; recompile with -fPIC
diff --git a/lld/test/ELF/x86-64-dyn-rel-error.s b/lld/test/ELF/x86-64-dyn-rel-error.s
index edc2875c6fa6..a03adf89072f 100644
--- a/lld/test/ELF/x86-64-dyn-rel-error.s
+++ b/lld/test/ELF/x86-64-dyn-rel-error.s
@@ -3,7 +3,7 @@
 # RUN: llvm-mc -filetype=obj -triple=x86_64 %p/Inputs/shared.s -o %t2.o
 # RUN: ld.lld %t2.o -shared -o %t2.so --threads=1
 # RUN: not ld.lld -pie %t.o %t2.so -o /dev/null --threads=1 2>&1 | FileCheck %s
-# RUN: not ld.lld -shared %t.o %t2.so -o /dev/null --threads=1 2>&1 | FileCheck %s --check-prefixes=CHECK,SHARED
+# RUN: not ld.lld -shared %t.o %t2.so -o /dev/null --threads=1 2>&1 | FileCheck %s
 
 # CHECK:      error: relocation R_X86_64_32 cannot be used against symbol 'zed'; recompile with -fPIC
 # CHECK-NEXT: >>> defined in {{.*}}.so
@@ -14,8 +14,8 @@
 # CHECK-NEXT: >>> referenced by {{.*}}.o:(.data+0x4)
 # CHECK-EMPTY:
 # CHECK-NEXT: error: relocation R_X86_64_64 cannot be used against symbol '_start'; recompile with -fPIC
-# SHARED:     error: relocation R_X86_64_64 cannot be used against symbol 'main'; recompile with -fPIC
-# SHARED:     error: relocation R_X86_64_64 cannot be used against symbol 'data'; recompile with -fPIC
+# CHECK:      error: relocation R_X86_64_64 cannot be used against symbol 'main'; recompile with -fPIC
+# CHECK:      error: relocation R_X86_64_64 cannot be used against symbol 'data'; recompile with -fPIC
 # CHECK-NOT:  error:
 
 # RUN: ld.lld --noinhibit-exec %t.o %t2.so -o /dev/null 2>&1 | FileCheck --check-prefix=WARN %s
-- 
GitLab


From 8063622721d0b2b70e44f6e747eec54cdaec2e76 Mon Sep 17 00:00:00 2001
From: Jakub Kuderski <jakub@nod-labs.com>
Date: Tue, 12 Dec 2023 13:15:17 -0500
Subject: [PATCH 340/349] [mlir][vector] Allow vector distribution with
 multiple written elements (#75122)

Add a configuration option to allow vector distribution with multiple
elements written by a single lane.

This is so that we can perform vector multi-reduction with multiple
results per workgroup.
---
 .../Vector/Transforms/VectorDistribution.h    |   6 +-
 .../Vector/Transforms/VectorDistribute.cpp    |  26 +++--
 .../Vector/vector-warp-distribute.mlir        | 100 +++++++++++++++++-
 .../Dialect/Vector/TestVectorTransforms.cpp   |   8 +-
 4 files changed, 123 insertions(+), 17 deletions(-)

diff --git a/mlir/include/mlir/Dialect/Vector/Transforms/VectorDistribution.h b/mlir/include/mlir/Dialect/Vector/Transforms/VectorDistribution.h
index f32efd94691a..8907a2a58360 100644
--- a/mlir/include/mlir/Dialect/Vector/Transforms/VectorDistribution.h
+++ b/mlir/include/mlir/Dialect/Vector/Transforms/VectorDistribution.h
@@ -43,7 +43,9 @@ void populateWarpExecuteOnLane0OpToScfForPattern(
 using DistributionMapFn = std::function<AffineMap(Value)>;
 
 /// Distribute transfer_write ops based on the affine map returned by
-/// `distributionMapFn`.
+/// `distributionMapFn`. Writes of size more than `maxNumElementToExtract`
+/// will not be distributed (it should be less than the warp size).
+///
 /// Example:
 /// ```
 /// %0 = vector.warp_execute_on_lane_0(%id){
@@ -67,7 +69,7 @@ using DistributionMapFn = std::function<AffineMap(Value)>;
 /// distribute, meaning writes should propagate first.
 void populateDistributeTransferWriteOpPatterns(
     RewritePatternSet &patterns, const DistributionMapFn &distributionMapFn,
-    PatternBenefit benefit = 2);
+    unsigned maxNumElementsToExtract, PatternBenefit benefit = 2);
 
 /// Move scalar operations with no dependency on the warp op outside of the
 /// region.
diff --git a/mlir/lib/Dialect/Vector/Transforms/VectorDistribute.cpp b/mlir/lib/Dialect/Vector/Transforms/VectorDistribute.cpp
index 07ecd8857520..074356ab4253 100644
--- a/mlir/lib/Dialect/Vector/Transforms/VectorDistribute.cpp
+++ b/mlir/lib/Dialect/Vector/Transforms/VectorDistribute.cpp
@@ -16,6 +16,7 @@
 #include "mlir/Interfaces/SideEffectInterfaces.h"
 #include "mlir/Transforms/RegionUtils.h"
 #include "llvm/ADT/SetVector.h"
+#include "llvm/Support/FormatVariadic.h"
 #include <numeric>
 #include <utility>
 
@@ -458,7 +459,9 @@ static VectorType getDistributedType(VectorType originalType, AffineMap map,
 }
 
 /// Distribute transfer_write ops based on the affine map returned by
-/// `distributionMapFn`.
+/// `distributionMapFn`. Writes of size more than `maxNumElementToExtract`
+/// will not be distributed (it should be less than the warp size).
+///
 /// Example:
 /// ```
 /// %0 = vector.warp_execute_on_lane_0(%id){
@@ -476,9 +479,10 @@ static VectorType getDistributedType(VectorType originalType, AffineMap map,
 /// vector.transfer_write %v, %A[%id] : vector<1xf32>, memref<128xf32>
 struct WarpOpTransferWrite : public OpRewritePattern<WarpExecuteOnLane0Op> {
   WarpOpTransferWrite(MLIRContext *ctx, DistributionMapFn fn,
-                      PatternBenefit b = 1)
+                      unsigned maxNumElementsToExtract, PatternBenefit b = 1)
       : OpRewritePattern<WarpExecuteOnLane0Op>(ctx, b),
-        distributionMapFn(std::move(fn)) {}
+        distributionMapFn(std::move(fn)),
+        maxNumElementsToExtract(maxNumElementsToExtract) {}
 
   /// Distribute the TransferWriteOp. Only 1D distributions and vector dims that
   /// are multiples of the distribution ratio are supported at the moment.
@@ -553,10 +557,13 @@ struct WarpOpTransferWrite : public OpRewritePattern<WarpExecuteOnLane0Op> {
     Location loc = writeOp.getLoc();
     VectorType vecType = writeOp.getVectorType();
 
-    // Only sink out vector of 1 element for now to not serialize large vector
-    // store. This can later be controlled by user.
-    if (vecType.getNumElements() != 1)
-      return failure();
+    if (vecType.getNumElements() > maxNumElementsToExtract) {
+      return rewriter.notifyMatchFailure(
+          warpOp,
+          llvm::formatv(
+              "writes more elements ({0}) than allowed to extract ({1})",
+              vecType.getNumElements(), maxNumElementsToExtract));
+    }
 
     // Do not process warp ops that contain only TransferWriteOps.
     if (llvm::all_of(warpOp.getOps(), [](Operation &op) {
@@ -616,6 +623,7 @@ struct WarpOpTransferWrite : public OpRewritePattern<WarpExecuteOnLane0Op> {
 
 private:
   DistributionMapFn distributionMapFn;
+  unsigned maxNumElementsToExtract = 1;
 };
 
 /// Sink out elementwise op feeding into a warp op yield.
@@ -1833,9 +1841,9 @@ void mlir::vector::populateWarpExecuteOnLane0OpToScfForPattern(
 
 void mlir::vector::populateDistributeTransferWriteOpPatterns(
     RewritePatternSet &patterns, const DistributionMapFn &distributionMapFn,
-    PatternBenefit benefit) {
+    unsigned maxNumElementsToExtract, PatternBenefit benefit) {
   patterns.add<WarpOpTransferWrite>(patterns.getContext(), distributionMapFn,
-                                    benefit);
+                                    maxNumElementsToExtract, benefit);
 }
 
 void mlir::vector::populatePropagateWarpVectorDistributionPatterns(
diff --git a/mlir/test/Dialect/Vector/vector-warp-distribute.mlir b/mlir/test/Dialect/Vector/vector-warp-distribute.mlir
index ab175effa3df..e04fa64f0f8a 100644
--- a/mlir/test/Dialect/Vector/vector-warp-distribute.mlir
+++ b/mlir/test/Dialect/Vector/vector-warp-distribute.mlir
@@ -1,8 +1,20 @@
-// RUN: mlir-opt %s -allow-unregistered-dialect -split-input-file -test-vector-warp-distribute=rewrite-warp-ops-to-scf-if | FileCheck %s --check-prefix=CHECK-SCF-IF
-// RUN: mlir-opt %s -allow-unregistered-dialect -split-input-file -test-vector-warp-distribute="hoist-uniform" | FileCheck --check-prefixes=CHECK-HOIST %s
-// RUN: mlir-opt %s -allow-unregistered-dialect -split-input-file -test-vector-warp-distribute="hoist-uniform distribute-transfer-write" | FileCheck --check-prefixes=CHECK-D %s
-// RUN: mlir-opt %s -allow-unregistered-dialect -split-input-file -test-vector-warp-distribute=propagate-distribution -canonicalize | FileCheck --check-prefixes=CHECK-PROP %s
-// RUN: mlir-opt %s -allow-unregistered-dialect -split-input-file -test-vector-warp-distribute="hoist-uniform distribute-transfer-write propagate-distribution" -canonicalize | FileCheck --check-prefixes=CHECK-DIST-AND-PROP %s
+// RUN: mlir-opt %s --allow-unregistered-dialect --split-input-file \
+// RUN:   --test-vector-warp-distribute=rewrite-warp-ops-to-scf-if | FileCheck %s --check-prefix=CHECK-SCF-IF
+
+// RUN: mlir-opt %s --allow-unregistered-dialect --split-input-file \
+// RUN:   --test-vector-warp-distribute="hoist-uniform" | FileCheck --check-prefixes=CHECK-HOIST %s
+
+// RUN: mlir-opt %s --allow-unregistered-dialect --split-input-file \
+// RUN:   --test-vector-warp-distribute="hoist-uniform distribute-transfer-write max-transfer-write-elements=4" \
+// RUN:   | FileCheck --check-prefixes=CHECK-D %s
+
+// RUN: mlir-opt %s --allow-unregistered-dialect --split-input-file \
+// RUN:  --test-vector-warp-distribute=propagate-distribution --canonicalize \
+// RUN:  | FileCheck --check-prefixes=CHECK-PROP %s
+
+// RUN: mlir-opt %s --allow-unregistered-dialect --split-input-file \
+// RUN:   --test-vector-warp-distribute="hoist-uniform distribute-transfer-write propagate-distribution" \
+// RUN:   --canonicalize | FileCheck --check-prefixes=CHECK-DIST-AND-PROP %s
 
 // CHECK-SCF-IF-DAG: #[[$TIMES2:.*]] = affine_map<()[s0] -> (s0 * 2)>
 // CHECK-SCF-IF-DAG: #[[$TIMES4:.*]] = affine_map<()[s0] -> (s0 * 4)>
@@ -134,6 +146,84 @@ func.func @warp_extract(%laneid: index, %arg1: memref<1024x1024xf32>, %gid : ind
 
 // -----
 
+// Check that we can distribute writes of the maximum allowed number of elements.
+
+// CHECK-D-LABEL: func @warp_extract_4_elems(
+//       CHECK-D:   %[[WARPOP:.*]]:2 = vector.warp_execute_on_lane_0(%{{.*}})[32] -> (vector<4xf32>, vector<4x1xf32>)
+//       CHECK-D:     "test.dummy_op"
+//       CHECK-D:     "test.dummy_op"
+//       CHECK-D:     vector.yield %{{.*}}, %{{.*}} : vector<4xf32>, vector<4x1xf32>
+//       CHECK-D:   }
+//       CHECK-D:   vector.warp_execute_on_lane_0(%{{.*}})[32] {
+//       CHECK-D:     vector.transfer_write %[[WARPOP]]#1, %{{.*}}[%{{.*}}] {{.*}} : vector<4x1xf32>
+//       CHECK-D:   }
+//       CHECK-D:   vector.warp_execute_on_lane_0(%{{.*}})[32] {
+//       CHECK-D:     vector.transfer_write %[[WARPOP]]#0, %{{.*}}[%{{.*}}] {{.*}} : vector<4xf32>
+//       CHECK-D:   }
+
+func.func @warp_extract_4_elems(%laneid: index, %arg1: memref<1024x1024xf32>, %gid : index) {
+  vector.warp_execute_on_lane_0(%laneid)[32] {
+    %c0 = arith.constant 0 : index
+    %v = "test.dummy_op"() : () -> (vector<4xf32>)
+    %v1 = "test.dummy_op"() : () -> (vector<4x1xf32>)
+    vector.transfer_write %v1, %arg1[%c0, %c0] : vector<4x1xf32>, memref<1024x1024xf32>
+    vector.transfer_write %v, %arg1[%c0, %c0] : vector<4xf32>, memref<1024x1024xf32>
+  }
+  return
+}
+
+// -----
+
+// Check that we do not distribute writes larger than the maximum allowed
+// number of elements.
+
+// CHECK-D-LABEL: func @warp_extract_5_elems(
+//       CHECK-D:   arith.constant 0 : index
+//       CHECK-D:   vector.warp_execute_on_lane_0(%{{.*}})[32] {
+//       CHECK-D:     %[[V:.+]] = "test.dummy_op"
+//       CHECK-D:     %[[V1:.+]] = "test.dummy_op"
+//       CHECK-D:     vector.transfer_write %[[V1]], %{{.*}}[%{{.*}}] {{.*}} : vector<5x1xf32>
+//       CHECK-D:     vector.transfer_write %[[V]], %{{.*}}[%{{.*}}] {{.*}} : vector<5xf32>
+//       CHECK-D:   }
+
+func.func @warp_extract_5_elems(%laneid: index, %arg1: memref<1024x1024xf32>, %gid : index) {
+  vector.warp_execute_on_lane_0(%laneid)[32] {
+    %c0 = arith.constant 0 : index
+    %v = "test.dummy_op"() : () -> (vector<5xf32>)
+    %v1 = "test.dummy_op"() : () -> (vector<5x1xf32>)
+    vector.transfer_write %v1, %arg1[%c0, %c0] : vector<5x1xf32>, memref<1024x1024xf32>
+    vector.transfer_write %v, %arg1[%c0, %c0] : vector<5xf32>, memref<1024x1024xf32>
+  }
+  return
+}
+
+// -----
+
+// Check that we do not distribute writes larger than the maximum allowed
+// number of elements, or multiples of the maximum number of elements.
+
+// CHECK-D-LABEL: func @warp_extract_8_elems(
+//       CHECK-D:   arith.constant 0 : index
+//       CHECK-D:   vector.warp_execute_on_lane_0(%{{.*}})[32] {
+//       CHECK-D:     %[[V:.+]] = "test.dummy_op"
+//       CHECK-D:     %[[V1:.+]] = "test.dummy_op"
+//       CHECK-D:     vector.transfer_write %[[V1]], %{{.*}}[%{{.*}}] {{.*}} : vector<8x1xf32>
+//       CHECK-D:     vector.transfer_write %[[V]], %{{.*}}[%{{.*}}] {{.*}} : vector<8xf32>
+//       CHECK-D:   }
+
+func.func @warp_extract_8_elems(%laneid: index, %arg1: memref<1024x1024xf32>, %gid : index) {
+  vector.warp_execute_on_lane_0(%laneid)[32] {
+    %c0 = arith.constant 0 : index
+    %v = "test.dummy_op"() : () -> (vector<8xf32>)
+    %v1 = "test.dummy_op"() : () -> (vector<8x1xf32>)
+    vector.transfer_write %v1, %arg1[%c0, %c0] : vector<8x1xf32>, memref<1024x1024xf32>
+    vector.transfer_write %v, %arg1[%c0, %c0] : vector<8xf32>, memref<1024x1024xf32>
+  }
+  return
+}
+
+// -----
+
 // CHECK-PROP-LABEL:   func @warp_dead_result(
 func.func @warp_dead_result(%laneid: index) -> (vector<1xf32>) {
   // CHECK-PROP: %[[R:.*]] = vector.warp_execute_on_lane_0(%{{.*}})[32] -> (vector<1xf32>)
diff --git a/mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp b/mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
index 86b8d5f9b099..e593c0defcd2 100644
--- a/mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
+++ b/mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
@@ -568,6 +568,11 @@ struct TestVectorDistribution
       llvm::cl::desc("Test distribution of transfer write"),
       llvm::cl::init(false)};
 
+  Option<unsigned> maxTransferWriteElements{
+      *this, "max-transfer-write-elements",
+      llvm::cl::desc("Maximum number of transfer write elements to distribute"),
+      llvm::cl::init(1)};
+
   Option<bool> hoistUniform{*this, "hoist-uniform",
                             llvm::cl::desc("Test hoist uniform"),
                             llvm::cl::init(false)};
@@ -624,7 +629,8 @@ struct TestVectorDistribution
       (void)applyPatternsAndFoldGreedily(getOperation(), std::move(patterns));
     } else if (distributeTransferWriteOps) {
       RewritePatternSet patterns(ctx);
-      populateDistributeTransferWriteOpPatterns(patterns, distributionFn);
+      populateDistributeTransferWriteOpPatterns(patterns, distributionFn,
+                                                maxTransferWriteElements);
       (void)applyPatternsAndFoldGreedily(getOperation(), std::move(patterns));
     } else if (propagateDistribution) {
       RewritePatternSet patterns(ctx);
-- 
GitLab


From 4b3446771f745bb5169354ad9027c0a1c9fca394 Mon Sep 17 00:00:00 2001
From: Boian Petkantchin <boian.petkantchin@amd.com>
Date: Tue, 12 Dec 2023 10:21:52 -0800
Subject: [PATCH 341/349] [mlir][mesh] Add endomorphism simplification for
 all-reduce (#73150)

Does transformations like
all_reduce(x) + all_reduce(y) -> all_reduce(x + y)

max(all_reduce(x), all_reduce(y)) -> all_reduce(max(x, y))
when the all_reduce element-wise op is max.

Added general rewrite pattern HomomorphismSimplification and
EndomorphismSimplification that encapsulate the general algorithm.
Made specialization for all-reduce with respect to
addf, addi, minsi, maxsi, minimumf and maximumf
in the Arithmetic dialect.
---
 .../Dialect/Mesh/Transforms/Simplifications.h | 110 ++++++++++
 .../Transforms/EndomorphismSimplification.h   |  93 +++++++++
 .../Transforms/HomomorphismSimplification.h   | 188 ++++++++++++++++++
 .../Dialect/Mesh/Transforms/CMakeLists.txt    |   2 +
 .../Mesh/Transforms/Simplifications.cpp       |  39 ++++
 mlir/test/Dialect/Mesh/simplifications.mlir   | 167 ++++++++++++++++
 mlir/test/lib/Dialect/CMakeLists.txt          |   1 +
 mlir/test/lib/Dialect/Mesh/CMakeLists.txt     |  13 ++
 .../lib/Dialect/Mesh/TestSimplifications.cpp  |  43 ++++
 mlir/tools/mlir-opt/CMakeLists.txt            |   1 +
 mlir/tools/mlir-opt/mlir-opt.cpp              |   2 +
 11 files changed, 659 insertions(+)
 create mode 100644 mlir/include/mlir/Dialect/Mesh/Transforms/Simplifications.h
 create mode 100644 mlir/include/mlir/Transforms/EndomorphismSimplification.h
 create mode 100644 mlir/include/mlir/Transforms/HomomorphismSimplification.h
 create mode 100644 mlir/lib/Dialect/Mesh/Transforms/Simplifications.cpp
 create mode 100644 mlir/test/Dialect/Mesh/simplifications.mlir
 create mode 100644 mlir/test/lib/Dialect/Mesh/CMakeLists.txt
 create mode 100644 mlir/test/lib/Dialect/Mesh/TestSimplifications.cpp

diff --git a/mlir/include/mlir/Dialect/Mesh/Transforms/Simplifications.h b/mlir/include/mlir/Dialect/Mesh/Transforms/Simplifications.h
new file mode 100644
index 000000000000..f70bdaa9de0a
--- /dev/null
+++ b/mlir/include/mlir/Dialect/Mesh/Transforms/Simplifications.h
@@ -0,0 +1,110 @@
+//===- Simplifications.h - Mesh Simplifications -----------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_DIALECT_MESH_TRANSFORMS_SIMPLIFICATIONS_H
+#define MLIR_DIALECT_MESH_TRANSFORMS_SIMPLIFICATIONS_H
+
+#include "mlir/Dialect/Mesh/IR/MeshOps.h"
+#include "mlir/IR/PatternMatch.h"
+#include "mlir/Transforms/EndomorphismSimplification.h"
+#include "llvm/Support/Casting.h"
+#include <algorithm>
+#include <iterator>
+#include <memory>
+#include <utility>
+
+namespace mlir {
+namespace mesh {
+
+// If we have an algebraic op like "+" and a summing all-reduce,
+// `all_reduce_sum(x) + all_reduce_sum(y)` will be transformed to
+// `all_reduce_sum(x + y)`.
+//
+// Another example with `min`.
+// `min(all_reduce_min(x), all_reduce_min(y))` will be transformed to
+// `all_reduce_min(min(x, y))`.
+//
+// Works only with algebraic ops that have all their operands relevant
+// to the all-reduce endomorphism.
+// Will not work with some op `f(x, y, z)` where only `x` and `y` form
+// the algebraic structure.
+template <typename AlgebraicOp>
+void populateAllReduceEndomorphismSimplificationPatterns(
+    RewritePatternSet &patterns, Partial reduction) {
+  auto getEndomorphismOpOperand = [](Operation *op) {
+    auto allReduceOp = llvm::cast<AllReduceOp>(op);
+    return &allReduceOp.getInputMutable();
+  };
+  auto getEndomorphismOpResult = [](Operation *op) {
+    auto allReduceOp = llvm::cast<AllReduceOp>(op);
+    return allReduceOp->getResult(0);
+  };
+  auto getAlgebraicOpOperands = [](Operation *op,
+                                   SmallVector<OpOperand *> &operands) {
+    auto algebraicOp = llvm::cast<AlgebraicOp>(op);
+    std::transform(algebraicOp->getOpOperands().begin(),
+                   algebraicOp->getOpOperands().end(),
+                   std::back_inserter(operands),
+                   [](OpOperand &operand) { return &operand; });
+  };
+  auto getAlgebraicOpResult = [](Operation *op) {
+    auto algebraicOp = llvm::cast<AlgebraicOp>(op);
+    return algebraicOp->getResult(0);
+  };
+  auto isEndomorphismOp = [reduction](Operation *op,
+                                      std::optional<Operation *> referenceOp) {
+    auto allReduceOp = llvm::dyn_cast<AllReduceOp>(op);
+    if (!allReduceOp ||
+        allReduceOp.getInput().getType().getElementType() !=
+            allReduceOp.getResult().getType().getElementType() ||
+        allReduceOp.getReduction() != reduction) {
+      return false;
+    }
+
+    // Dont't use simplify if the all-reduce is used other than by the
+    // algebraic op.
+    // TODO: maybe handle this by an additional pass that later reverses the
+    // simplification if there are other uses left other optimizations have
+    // been done.
+    if (!allReduceOp->hasOneUse()) {
+      return false;
+    }
+
+    if (!referenceOp) {
+      return true;
+    }
+
+    auto refAllReduceOp = llvm::dyn_cast<AllReduceOp>(referenceOp.value());
+    return refAllReduceOp->getAttrs() == allReduceOp->getAttrs() &&
+           allReduceOp.getInput().getType().getElementType() ==
+               refAllReduceOp.getInput().getType().getElementType();
+  };
+  auto isAlgebraicOp = [](Operation *op) {
+    return static_cast<bool>(llvm::dyn_cast<AlgebraicOp>(op));
+  };
+
+  using ConcreteEndomorphismSimplification = EndomorphismSimplification<
+      std::decay_t<decltype(getEndomorphismOpOperand)>,
+      std::decay_t<decltype(getEndomorphismOpResult)>,
+      std::decay_t<decltype(getAlgebraicOpOperands)>,
+      std::decay_t<decltype(getAlgebraicOpResult)>,
+      std::decay_t<decltype(isEndomorphismOp)>,
+      std::decay_t<decltype(isAlgebraicOp)>>;
+  patterns.add(std::make_unique<ConcreteEndomorphismSimplification>(
+      std::move(getEndomorphismOpOperand), std::move(getEndomorphismOpResult),
+      std::move(getAlgebraicOpOperands), std::move(getAlgebraicOpResult),
+      std::move(isEndomorphismOp), std::move(isAlgebraicOp),
+      AlgebraicOp::getOperationName(), 1, patterns.getContext()));
+}
+
+void populateSimplificationPatterns(RewritePatternSet &patterns);
+
+} // namespace mesh
+} // namespace mlir
+
+#endif // MLIR_DIALECT_MESH_TRANSFORMS_SIMPLIFICATIONS_H
diff --git a/mlir/include/mlir/Transforms/EndomorphismSimplification.h b/mlir/include/mlir/Transforms/EndomorphismSimplification.h
new file mode 100644
index 000000000000..1aa5da2346f7
--- /dev/null
+++ b/mlir/include/mlir/Transforms/EndomorphismSimplification.h
@@ -0,0 +1,93 @@
+//===- EndomorphismSimplification.h -----------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_TRANSFORMS_SIMPLIFY_ENDOMORPHISM_H_
+#define MLIR_TRANSFORMS_SIMPLIFY_ENDOMORPHISM_H_
+
+#include "mlir/Transforms/HomomorphismSimplification.h"
+
+namespace mlir {
+
+namespace detail {
+struct CreateAlgebraicOpForEndomorphismSimplification {
+  Operation *operator()(Operation *op, IRMapping &operandsRemapping,
+                        PatternRewriter &rewriter) const {
+    return rewriter.clone(*op, operandsRemapping);
+  }
+};
+} // namespace detail
+
+// If `f` is an endomorphism with respect to the algebraic structure induced by
+// function `g`, transforms `g(f(x1), f(x2) ..., f(xn))` into
+// `f(g(x1, x2, ..., xn))`.
+// `g` is the algebraic operation and `f` is the endomorphism.
+//
+// Functors:
+// ---------
+// `GetEndomorphismOpOperandFn`: `(Operation*) -> OpOperand*`
+// Returns the operand relevant to the endomorphism.
+// There may be other operands that are not relevant.
+//
+// `GetEndomorphismOpResultFn`: `(Operation*) -> OpResult`
+// Returns the result relevant to the endomorphism.
+//
+// `GetAlgebraicOpOperandsFn`: `(Operation*, SmallVector<OpOperand*>&) -> void`
+// Populates into the vector the operands relevant to the endomorphism.
+//
+// `GetAlgebraicOpResultFn`: `(Operation*) -> OpResult`
+//  Return the result relevant to the endomorphism.
+//
+// `IsEndomorphismOpFn`: `(Operation*, std::optional<Operation*>) -> bool`
+// Check if the operation is an endomorphism of the required type.
+// Additionally if the optional is present checks if the operations are
+// compatible endomorphisms.
+//
+// `IsAlgebraicOpFn`: `(Operation*) -> bool`
+// Check if the operation is an operation of the algebraic structure.
+template <typename GetEndomorphismOpOperandFn,
+          typename GetEndomorphismOpResultFn, typename GetAlgebraicOpOperandsFn,
+          typename GetAlgebraicOpResultFn, typename IsEndomorphismOpFn,
+          typename IsAlgebraicOpFn>
+struct EndomorphismSimplification
+    : HomomorphismSimplification<
+          GetEndomorphismOpOperandFn, GetEndomorphismOpResultFn,
+          GetAlgebraicOpOperandsFn, GetAlgebraicOpResultFn,
+          GetAlgebraicOpResultFn, IsEndomorphismOpFn, IsAlgebraicOpFn,
+          detail::CreateAlgebraicOpForEndomorphismSimplification> {
+  template <typename GetEndomorphismOpOperandFnArg,
+            typename GetEndomorphismOpResultFnArg,
+            typename GetAlgebraicOpOperandsFnArg,
+            typename GetAlgebraicOpResultFnArg, typename IsEndomorphismOpFnArg,
+            typename IsAlgebraicOpFnArg, typename... RewritePatternArgs>
+  EndomorphismSimplification(
+      GetEndomorphismOpOperandFnArg &&getEndomorphismOpOperand,
+      GetEndomorphismOpResultFnArg &&getEndomorphismOpResult,
+      GetAlgebraicOpOperandsFnArg &&getAlgebraicOpOperands,
+      GetAlgebraicOpResultFnArg &&getAlgebraicOpResult,
+      IsEndomorphismOpFnArg &&isEndomorphismOp,
+      IsAlgebraicOpFnArg &&isAlgebraicOp, RewritePatternArgs &&...args)
+      : HomomorphismSimplification<
+            GetEndomorphismOpOperandFn, GetEndomorphismOpResultFn,
+            GetAlgebraicOpOperandsFn, GetAlgebraicOpResultFn,
+            GetAlgebraicOpResultFn, IsEndomorphismOpFn, IsAlgebraicOpFn,
+            detail::CreateAlgebraicOpForEndomorphismSimplification>(
+            std::forward<GetEndomorphismOpOperandFnArg>(
+                getEndomorphismOpOperand),
+            std::forward<GetEndomorphismOpResultFnArg>(getEndomorphismOpResult),
+            std::forward<GetAlgebraicOpOperandsFnArg>(getAlgebraicOpOperands),
+            std::forward<GetAlgebraicOpResultFnArg>(getAlgebraicOpResult),
+            std::forward<GetAlgebraicOpResultFnArg>(getAlgebraicOpResult),
+            std::forward<IsEndomorphismOpFnArg>(isEndomorphismOp),
+            std::forward<IsAlgebraicOpFnArg>(isAlgebraicOp),
+            detail::CreateAlgebraicOpForEndomorphismSimplification(),
+            std::forward<RewritePatternArgs>(args)...) {}
+};
+
+} // namespace mlir
+
+#endif // MLIR_TRANSFORMS_SIMPLIFY_ENDOMORPHISM_H_
diff --git a/mlir/include/mlir/Transforms/HomomorphismSimplification.h b/mlir/include/mlir/Transforms/HomomorphismSimplification.h
new file mode 100644
index 000000000000..d2732602a0d8
--- /dev/null
+++ b/mlir/include/mlir/Transforms/HomomorphismSimplification.h
@@ -0,0 +1,188 @@
+//===- HomomorphismSimplification.h -----------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_TRANSFORMS_SIMPLIFY_HOMOMORPHISM_H_
+#define MLIR_TRANSFORMS_SIMPLIFY_HOMOMORPHISM_H_
+
+#include "mlir/IR/IRMapping.h"
+#include "mlir/IR/PatternMatch.h"
+#include "mlir/IR/Value.h"
+#include "mlir/Support/LLVM.h"
+#include "mlir/Support/LogicalResult.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/Support/Casting.h"
+#include <iterator>
+#include <optional>
+#include <type_traits>
+#include <utility>
+
+namespace mlir {
+
+// If `h` is an homomorphism with respect to the source algebraic structure
+// induced by function `s` and the target algebraic structure induced by
+// function `t`, transforms `s(h(x1), h(x2) ..., h(xn))` into
+// `h(t(x1, x2, ..., xn))`.
+//
+// Functors:
+// ---------
+// `GetHomomorphismOpOperandFn`: `(Operation*) -> OpOperand*`
+// Returns the operand relevant to the homomorphism.
+// There may be other operands that are not relevant.
+//
+// `GetHomomorphismOpResultFn`: `(Operation*) -> OpResult`
+// Returns the result relevant to the homomorphism.
+//
+// `GetSourceAlgebraicOpOperandsFn`: `(Operation*, SmallVector<OpOperand*>&) ->
+// void` Populates into the vector the operands relevant to the homomorphism.
+//
+// `GetSourceAlgebraicOpResultFn`: `(Operation*) -> OpResult`
+//  Return the result of the source algebraic operation relevant to the
+//  homomorphism.
+//
+// `GetTargetAlgebraicOpResultFn`: `(Operation*) -> OpResult`
+//  Return the result of the target algebraic operation relevant to the
+//  homomorphism.
+//
+// `IsHomomorphismOpFn`: `(Operation*, std::optional<Operation*>) -> bool`
+// Check if the operation is an homomorphism of the required type.
+// Additionally if the optional is present checks if the operations are
+// compatible homomorphisms.
+//
+// `IsSourceAlgebraicOpFn`: `(Operation*) -> bool`
+// Check if the operation is an operation of the algebraic structure.
+//
+// `CreateTargetAlgebraicOpFn`: `(Operation*, IRMapping& operandsRemapping,
+// PatternRewriter &rewriter) -> Operation*`
+template <typename GetHomomorphismOpOperandFn,
+          typename GetHomomorphismOpResultFn,
+          typename GetSourceAlgebraicOpOperandsFn,
+          typename GetSourceAlgebraicOpResultFn,
+          typename GetTargetAlgebraicOpResultFn, typename IsHomomorphismOpFn,
+          typename IsSourceAlgebraicOpFn, typename CreateTargetAlgebraicOpFn>
+struct HomomorphismSimplification : public RewritePattern {
+  template <typename GetHomomorphismOpOperandFnArg,
+            typename GetHomomorphismOpResultFnArg,
+            typename GetSourceAlgebraicOpOperandsFnArg,
+            typename GetSourceAlgebraicOpResultFnArg,
+            typename GetTargetAlgebraicOpResultFnArg,
+            typename IsHomomorphismOpFnArg, typename IsSourceAlgebraicOpFnArg,
+            typename CreateTargetAlgebraicOpFnArg,
+            typename... RewritePatternArgs>
+  HomomorphismSimplification(
+      GetHomomorphismOpOperandFnArg &&getHomomorphismOpOperand,
+      GetHomomorphismOpResultFnArg &&getHomomorphismOpResult,
+      GetSourceAlgebraicOpOperandsFnArg &&getSourceAlgebraicOpOperands,
+      GetSourceAlgebraicOpResultFnArg &&getSourceAlgebraicOpResult,
+      GetTargetAlgebraicOpResultFnArg &&getTargetAlgebraicOpResult,
+      IsHomomorphismOpFnArg &&isHomomorphismOp,
+      IsSourceAlgebraicOpFnArg &&isSourceAlgebraicOp,
+      CreateTargetAlgebraicOpFnArg &&createTargetAlgebraicOpFn,
+      RewritePatternArgs &&...args)
+      : RewritePattern(std::forward<RewritePatternArgs>(args)...),
+        getHomomorphismOpOperand(std::forward<GetHomomorphismOpOperandFnArg>(
+            getHomomorphismOpOperand)),
+        getHomomorphismOpResult(std::forward<GetHomomorphismOpResultFnArg>(
+            getHomomorphismOpResult)),
+        getSourceAlgebraicOpOperands(
+            std::forward<GetSourceAlgebraicOpOperandsFnArg>(
+                getSourceAlgebraicOpOperands)),
+        getSourceAlgebraicOpResult(
+            std::forward<GetSourceAlgebraicOpResultFnArg>(
+                getSourceAlgebraicOpResult)),
+        getTargetAlgebraicOpResult(
+            std::forward<GetTargetAlgebraicOpResultFnArg>(
+                getTargetAlgebraicOpResult)),
+        isHomomorphismOp(std::forward<IsHomomorphismOpFnArg>(isHomomorphismOp)),
+        isSourceAlgebraicOp(
+            std::forward<IsSourceAlgebraicOpFnArg>(isSourceAlgebraicOp)),
+        createTargetAlgebraicOpFn(std::forward<CreateTargetAlgebraicOpFnArg>(
+            createTargetAlgebraicOpFn)) {}
+
+  LogicalResult matchAndRewrite(Operation *op,
+                                PatternRewriter &rewriter) const override {
+    SmallVector<OpOperand *> algebraicOpOperands;
+    if (failed(matchOp(op, algebraicOpOperands))) {
+      return failure();
+    }
+    return rewriteOp(op, algebraicOpOperands, rewriter);
+  }
+
+private:
+  LogicalResult
+  matchOp(Operation *sourceAlgebraicOp,
+          SmallVector<OpOperand *> &sourceAlgebraicOpOperands) const {
+    if (!isSourceAlgebraicOp(sourceAlgebraicOp)) {
+      return failure();
+    }
+    sourceAlgebraicOpOperands.clear();
+    getSourceAlgebraicOpOperands(sourceAlgebraicOp, sourceAlgebraicOpOperands);
+    if (sourceAlgebraicOpOperands.empty()) {
+      return failure();
+    }
+
+    Operation *firstHomomorphismOp =
+        sourceAlgebraicOpOperands.front()->get().getDefiningOp();
+    if (!firstHomomorphismOp ||
+        !isHomomorphismOp(firstHomomorphismOp, std::nullopt)) {
+      return failure();
+    }
+    OpResult firstHomomorphismOpResult =
+        getHomomorphismOpResult(firstHomomorphismOp);
+    if (firstHomomorphismOpResult != sourceAlgebraicOpOperands.front()->get()) {
+      return failure();
+    }
+
+    for (auto operand : sourceAlgebraicOpOperands) {
+      Operation *homomorphismOp = operand->get().getDefiningOp();
+      if (!homomorphismOp ||
+          !isHomomorphismOp(homomorphismOp, firstHomomorphismOp)) {
+        return failure();
+      }
+    }
+    return success();
+  }
+
+  LogicalResult
+  rewriteOp(Operation *sourceAlgebraicOp,
+            const SmallVector<OpOperand *> &sourceAlgebraicOpOperands,
+            PatternRewriter &rewriter) const {
+    IRMapping irMapping;
+    for (auto operand : sourceAlgebraicOpOperands) {
+      Operation *homomorphismOp = operand->get().getDefiningOp();
+      irMapping.map(operand->get(),
+                    getHomomorphismOpOperand(homomorphismOp)->get());
+    }
+    Operation *targetAlgebraicOp =
+        createTargetAlgebraicOpFn(sourceAlgebraicOp, irMapping, rewriter);
+
+    irMapping.clear();
+    assert(!sourceAlgebraicOpOperands.empty());
+    Operation *firstHomomorphismOp =
+        sourceAlgebraicOpOperands[0]->get().getDefiningOp();
+    irMapping.map(getHomomorphismOpOperand(firstHomomorphismOp)->get(),
+                  getTargetAlgebraicOpResult(targetAlgebraicOp));
+    Operation *newHomomorphismOp =
+        rewriter.clone(*firstHomomorphismOp, irMapping);
+    rewriter.replaceAllUsesWith(getSourceAlgebraicOpResult(sourceAlgebraicOp),
+                                getHomomorphismOpResult(newHomomorphismOp));
+    return success();
+  }
+
+  GetHomomorphismOpOperandFn getHomomorphismOpOperand;
+  GetHomomorphismOpResultFn getHomomorphismOpResult;
+  GetSourceAlgebraicOpOperandsFn getSourceAlgebraicOpOperands;
+  GetSourceAlgebraicOpResultFn getSourceAlgebraicOpResult;
+  GetTargetAlgebraicOpResultFn getTargetAlgebraicOpResult;
+  IsHomomorphismOpFn isHomomorphismOp;
+  IsSourceAlgebraicOpFn isSourceAlgebraicOp;
+  CreateTargetAlgebraicOpFn createTargetAlgebraicOpFn;
+};
+
+} // namespace mlir
+
+#endif // MLIR_TRANSFORMS_SIMPLIFY_HOMOMORPHISM_H_
diff --git a/mlir/lib/Dialect/Mesh/Transforms/CMakeLists.txt b/mlir/lib/Dialect/Mesh/Transforms/CMakeLists.txt
index bcf45c4ea276..044b8672c8c6 100644
--- a/mlir/lib/Dialect/Mesh/Transforms/CMakeLists.txt
+++ b/mlir/lib/Dialect/Mesh/Transforms/CMakeLists.txt
@@ -1,4 +1,5 @@
 add_mlir_dialect_library(MLIRMeshTransforms
+  Simplifications.cpp
   ShardingPropagation.cpp
 
   ADDITIONAL_HEADER_DIRS
@@ -9,6 +10,7 @@ add_mlir_dialect_library(MLIRMeshTransforms
   MLIRShardingInterface
 
   LINK_LIBS PUBLIC
+  MLIRArithDialect
   MLIRFuncDialect
   MLIRIR
   MLIRMeshDialect
diff --git a/mlir/lib/Dialect/Mesh/Transforms/Simplifications.cpp b/mlir/lib/Dialect/Mesh/Transforms/Simplifications.cpp
new file mode 100644
index 000000000000..643bd7b8e77c
--- /dev/null
+++ b/mlir/lib/Dialect/Mesh/Transforms/Simplifications.cpp
@@ -0,0 +1,39 @@
+//===- Patterns.cpp - Mesh Patterns -----------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "mlir/Dialect/Mesh/Transforms/Simplifications.h"
+#include "mlir/Dialect/Arith/IR/Arith.h"
+
+namespace mlir {
+namespace mesh {
+
+void populateSimplificationPatterns(RewritePatternSet &patterns) {
+  populateAllReduceEndomorphismSimplificationPatterns<arith::AddFOp>(
+      patterns, Partial::Sum);
+  populateAllReduceEndomorphismSimplificationPatterns<arith::AddIOp>(
+      patterns, Partial::Sum);
+
+  populateAllReduceEndomorphismSimplificationPatterns<arith::MinimumFOp>(
+      patterns, Partial::Min);
+  populateAllReduceEndomorphismSimplificationPatterns<arith::MinSIOp>(
+      patterns, Partial::Min);
+  populateAllReduceEndomorphismSimplificationPatterns<arith::MinUIOp>(
+      patterns, Partial::Min);
+
+  populateAllReduceEndomorphismSimplificationPatterns<arith::MaximumFOp>(
+      patterns, Partial::Max);
+  populateAllReduceEndomorphismSimplificationPatterns<arith::MaxSIOp>(
+      patterns, Partial::Max);
+  populateAllReduceEndomorphismSimplificationPatterns<arith::MaxUIOp>(
+      patterns, Partial::Max);
+
+  // TODO: add simplifications for all-gather and other collectives.
+}
+
+} // namespace mesh
+} // namespace mlir
diff --git a/mlir/test/Dialect/Mesh/simplifications.mlir b/mlir/test/Dialect/Mesh/simplifications.mlir
new file mode 100644
index 000000000000..e716940f2301
--- /dev/null
+++ b/mlir/test/Dialect/Mesh/simplifications.mlir
@@ -0,0 +1,167 @@
+// RUN: mlir-opt -test-mesh-simplifications %s | FileCheck %s
+
+mesh.cluster @mesh0(rank = 2, dim_sizes = 4x2)
+mesh.cluster @mesh1(rank = 1, dim_sizes = 4)
+
+// Checks that `all_reduce(x) + all_reduce(y)` gets transformed to
+// `all_reduce(x + y)`.
+// CHECK-LABEL: func.func @all_reduce_arith_addf_endomorphism
+func.func @all_reduce_arith_addf_endomorphism(
+    // CHECK-SAME: %[[ARG0:[A-Za-z0-9_]*]]: tensor<5xf32>
+    %arg0: tensor<5xf32>,
+    // CHECK-SAME: %[[ARG1:[A-Za-z0-9_]*]]: tensor<5xf32>
+    %arg1: tensor<5xf32>) -> tensor<5xf32> {
+  %0 = mesh.all_reduce %arg0 on @mesh0 mesh_axes = [0]
+    : tensor<5xf32> -> tensor<5xf32>
+  %1 = mesh.all_reduce %arg1 on @mesh0 mesh_axes = [0]
+    : tensor<5xf32> -> tensor<5xf32>
+  // CHECK: %[[ADD_RES:[A-Za-z0-9_]*]] = arith.addf %[[ARG0]], %[[ARG1]]
+  %2 = arith.addf %0, %1 : tensor<5xf32>
+  // CHECK: %[[ALL_REDUCE_RES:[A-Za-z0-9_]*]] = mesh.all_reduce %[[ADD_RES]]
+  // CHECK: return %[[ALL_REDUCE_RES]]
+  return %2 : tensor<5xf32>
+}
+
+// CHECK-LABEL: func.func @all_reduce_arith_addf_endomorphism_multiple_uses_of_result
+func.func @all_reduce_arith_addf_endomorphism_multiple_uses_of_result(
+    // CHECK-SAME: %[[ARG0:[A-Za-z0-9_]*]]: tensor<5xf32>
+    %arg0: tensor<5xf32>,
+    // CHECK-SAME: %[[ARG1:[A-Za-z0-9_]*]]: tensor<5xf32>
+    %arg1: tensor<5xf32>) -> (tensor<5xf32>, tensor<5xf32>) {
+  %0 = mesh.all_reduce %arg0 on @mesh0 mesh_axes = [0]
+    : tensor<5xf32> -> tensor<5xf32>
+  %1 = mesh.all_reduce %arg1 on @mesh0 mesh_axes = [0]
+    : tensor<5xf32> -> tensor<5xf32>
+  // CHECK: %[[ADD_RES:[A-Za-z0-9_]*]] = arith.addf %[[ARG0]], %[[ARG1]]
+  %2 = arith.addf %0, %1 : tensor<5xf32>
+  // CHECK: %[[ALL_REDUCE_RES:[A-Za-z0-9_]*]] = mesh.all_reduce %[[ADD_RES]]
+  // CHECK: return %[[ALL_REDUCE_RES]], %[[ALL_REDUCE_RES]]
+  return %2, %2 : tensor<5xf32>, tensor<5xf32>
+}
+
+// Do not simplify if there is another use of one of the all-reduces.
+// CHECK-LABEL: func.func @all_reduce_arith_addf_endomorphism_multiple_uses_of_all_reduce_result
+func.func @all_reduce_arith_addf_endomorphism_multiple_uses_of_all_reduce_result(
+    // CHECK-SAME: %[[ARG0:[A-Za-z0-9_]*]]: tensor<5xf32>
+    %arg0: tensor<5xf32>,
+    // CHECK-SAME: %[[ARG1:[A-Za-z0-9_]*]]: tensor<5xf32>
+    %arg1: tensor<5xf32>) -> (tensor<5xf32>, tensor<5xf32>) {
+  // CHECK: %[[ALL_REDUCE_0_RES:[A-Za-z0-9_]*]] = mesh.all_reduce %[[ARG0]]
+  %0 = mesh.all_reduce %arg0 on @mesh0 mesh_axes = [0]
+    : tensor<5xf32> -> tensor<5xf32>
+  // CHECK: %[[ALL_REDUCE_1_RES:[A-Za-z0-9_]*]] = mesh.all_reduce %[[ARG1]]
+  %1 = mesh.all_reduce %arg1 on @mesh0 mesh_axes = [0]
+    : tensor<5xf32> -> tensor<5xf32>
+  // CHECK: %[[ADD_RES:[A-Za-z0-9_]*]] = arith.addf %[[ALL_REDUCE_0_RES]], %[[ALL_REDUCE_1_RES]]
+  %2 = arith.addf %0, %1 : tensor<5xf32>
+  // CHECK: return %[[ALL_REDUCE_0_RES]], %[[ADD_RES]]
+  return %0, %2 : tensor<5xf32>, tensor<5xf32>
+}
+
+// CHECK-LABEL: func.func @all_reduce_arith_addf_no_endomorphism_different_mesh
+func.func @all_reduce_arith_addf_no_endomorphism_different_mesh(
+    // CHECK-SAME: %[[ARG0:[A-Za-z0-9_]*]]: tensor<5xf32>
+    %arg0: tensor<5xf32>,
+    // CHECK-SAME: %[[ARG1:[A-Za-z0-9_]*]]: tensor<5xf32>
+    %arg1: tensor<5xf32>) -> tensor<5xf32> {
+  // CHECK: %[[ALL_REDUCE0:[A-Za-z0-9_]*]] = mesh.all_reduce %[[ARG0]] on @mesh0
+  %0 = mesh.all_reduce %arg0 on @mesh0 mesh_axes = [0]
+    : tensor<5xf32> -> tensor<5xf32>
+  // CHECK: %[[ALL_REDUCE1:[A-Za-z0-9_]*]] = mesh.all_reduce %[[ARG1]] on @mesh1
+  %1 = mesh.all_reduce %arg1 on @mesh1 mesh_axes = [0]
+    : tensor<5xf32> -> tensor<5xf32>
+  // CHECK: %[[ADD_RES:[A-Za-z0-9_]*]] = arith.addf %[[ALL_REDUCE0]], %[[ALL_REDUCE1]]
+  %2 = arith.addf %0, %1 : tensor<5xf32>
+  // CHECK: return %[[ADD_RES]]
+  return %2 : tensor<5xf32>
+}
+
+// CHECK-LABEL: func.func @all_reduce_arith_addf_no_endomorphism_different_mesh_axes
+func.func @all_reduce_arith_addf_no_endomorphism_different_mesh_axes(
+    // CHECK-SAME: %[[ARG0:[A-Za-z0-9_]*]]: tensor<5xf32>
+    %arg0: tensor<5xf32>,
+    // CHECK-SAME: %[[ARG1:[A-Za-z0-9_]*]]: tensor<5xf32>
+    %arg1: tensor<5xf32>) -> tensor<5xf32> {
+  // CHECK: %[[ALL_REDUCE0:[A-Za-z0-9_]*]] = mesh.all_reduce %[[ARG0]] on @mesh0 mesh_axes = [0]
+  %0 = mesh.all_reduce %arg0 on @mesh0 mesh_axes = [0]
+    : tensor<5xf32> -> tensor<5xf32>
+  // CHECK: %[[ALL_REDUCE1:[A-Za-z0-9_]*]] = mesh.all_reduce %[[ARG1]] on @mesh0 mesh_axes = [1]
+  %1 = mesh.all_reduce %arg1 on @mesh0 mesh_axes = [1]
+    : tensor<5xf32> -> tensor<5xf32>
+  // CHECK: %[[ADD_RES:[A-Za-z0-9_]*]] = arith.addf %[[ALL_REDUCE0]], %[[ALL_REDUCE1]]
+  %2 = arith.addf %0, %1 : tensor<5xf32>
+  // CHECK: return %[[ADD_RES]]
+  return %2 : tensor<5xf32>
+}
+
+// CHECK-LABEL: func.func @all_reduce_arith_addf_no_endomorphism_wrong_reduction_kind
+func.func @all_reduce_arith_addf_no_endomorphism_wrong_reduction_kind(
+    // CHECK-SAME: %[[ARG0:[A-Za-z0-9_]*]]: tensor<5xf32>
+    %arg0: tensor<5xf32>,
+    // CHECK-SAME: %[[ARG1:[A-Za-z0-9_]*]]: tensor<5xf32>
+    %arg1: tensor<5xf32>) -> tensor<5xf32> {
+  // CHECK: %[[ALL_REDUCE0:[A-Za-z0-9_]*]] = mesh.all_reduce %[[ARG0]] on @mesh0 mesh_axes = [0] reduction = <max>
+  %0 = mesh.all_reduce %arg0 on @mesh0 mesh_axes = [0] reduction = <max>
+    : tensor<5xf32> -> tensor<5xf32>
+  // CHECK: %[[ALL_REDUCE1:[A-Za-z0-9_]*]] = mesh.all_reduce %[[ARG1]] on @mesh0 mesh_axes = [0]
+  %1 = mesh.all_reduce %arg1 on @mesh0 mesh_axes = [0]
+    : tensor<5xf32> -> tensor<5xf32>
+  // CHECK: %[[ADD_RES:[A-Za-z0-9_]*]] = arith.addf %[[ALL_REDUCE0]], %[[ALL_REDUCE1]]
+  %2 = arith.addf %0, %1 : tensor<5xf32>
+  // CHECK: return %[[ADD_RES]]
+  return %2 : tensor<5xf32>
+}
+
+// CHECK-LABEL: func.func @all_reduce_arith_addf_no_endomorphism_different_operand_result_element_types
+func.func @all_reduce_arith_addf_no_endomorphism_different_operand_result_element_types(
+    // CHECK-SAME: %[[ARG0:[A-Za-z0-9_]*]]: tensor<5xf32>
+    %arg0: tensor<5xf32>,
+    // CHECK-SAME: %[[ARG1:[A-Za-z0-9_]*]]: tensor<5xf32>
+    %arg1: tensor<5xf32>) -> tensor<5xf64> {
+  // CHECK: %[[ALL_REDUCE0:[A-Za-z0-9_]*]] = mesh.all_reduce %[[ARG0]] on @mesh0 mesh_axes = [0]
+  %0 = mesh.all_reduce %arg0 on @mesh0 mesh_axes = [0]
+    : tensor<5xf32> -> tensor<5xf64>
+  // CHECK: %[[ALL_REDUCE1:[A-Za-z0-9_]*]] = mesh.all_reduce %[[ARG1]] on @mesh0 mesh_axes = [0]
+  %1 = mesh.all_reduce %arg1 on @mesh0 mesh_axes = [0]
+    : tensor<5xf32> -> tensor<5xf64>
+  // CHECK: %[[ADD_RES:[A-Za-z0-9_]*]] = arith.addf %[[ALL_REDUCE0]], %[[ALL_REDUCE1]]
+  %2 = arith.addf %0, %1 : tensor<5xf64>
+  // CHECK: return %[[ADD_RES]]
+  return %2 : tensor<5xf64>
+}
+
+// Checks that `min(all_reduce(x), all_reduce(y))` gets transformed to
+// `all_reduce(min(x, y))`.
+// CHECK-LABEL: func.func @all_reduce_arith_minimumf_endomorphism
+func.func @all_reduce_arith_minimumf_endomorphism(
+    // CHECK-SAME: %[[ARG0:[A-Za-z0-9_]*]]: tensor<5xf32>
+    %arg0: tensor<5xf32>,
+    // CHECK-SAME: %[[ARG1:[A-Za-z0-9_]*]]: tensor<5xf32>
+    %arg1: tensor<5xf32>) -> tensor<5xf32> {
+  %0 = mesh.all_reduce %arg0 on @mesh0 mesh_axes = [0] reduction = <min>
+    : tensor<5xf32> -> tensor<5xf32>
+  %1 = mesh.all_reduce %arg1 on @mesh0 mesh_axes = [0] reduction = <min>
+    : tensor<5xf32> -> tensor<5xf32>
+  // CHECK: %[[ADD_RES:[A-Za-z0-9_]*]] = arith.minimumf %[[ARG0]], %[[ARG1]]
+  %2 = arith.minimumf %0, %1 : tensor<5xf32>
+  // CHECK: %[[ALL_REDUCE_RES:[A-Za-z0-9_]*]] = mesh.all_reduce %[[ADD_RES]] on @mesh0 mesh_axes = [0] reduction = <min>
+  // CHECK: return %[[ALL_REDUCE_RES]]
+  return %2 : tensor<5xf32>
+}
+
+// CHECK-LABEL: func.func @all_reduce_arith_minsi_endomorphism
+func.func @all_reduce_arith_minsi_endomorphism(
+    // CHECK-SAME: %[[ARG0:[A-Za-z0-9_]*]]: tensor<5xi32>
+    %arg0: tensor<5xi32>,
+    // CHECK-SAME: %[[ARG1:[A-Za-z0-9_]*]]: tensor<5xi32>
+    %arg1: tensor<5xi32>) -> tensor<5xi32> {
+  %0 = mesh.all_reduce %arg0 on @mesh0 mesh_axes = [0] reduction = <min>
+    : tensor<5xi32> -> tensor<5xi32>
+  %1 = mesh.all_reduce %arg1 on @mesh0 mesh_axes = [0] reduction = <min>
+    : tensor<5xi32> -> tensor<5xi32>
+  // CHECK: %[[ADD_RES:[A-Za-z0-9_]*]] = arith.minsi %[[ARG0]], %[[ARG1]]
+  %2 = arith.minsi %0, %1 : tensor<5xi32>
+  // CHECK: %[[ALL_REDUCE_RES:[A-Za-z0-9_]*]] = mesh.all_reduce %[[ADD_RES]] on @mesh0 mesh_axes = [0] reduction = <min>
+  // CHECK: return %[[ALL_REDUCE_RES]]
+  return %2 : tensor<5xi32>
+}
diff --git a/mlir/test/lib/Dialect/CMakeLists.txt b/mlir/test/lib/Dialect/CMakeLists.txt
index 48bde69e0170..30a17c201ff7 100644
--- a/mlir/test/lib/Dialect/CMakeLists.txt
+++ b/mlir/test/lib/Dialect/CMakeLists.txt
@@ -9,6 +9,7 @@ add_subdirectory(Linalg)
 add_subdirectory(LLVM)
 add_subdirectory(Math)
 add_subdirectory(MemRef)
+add_subdirectory(Mesh)
 add_subdirectory(NVGPU)
 add_subdirectory(SCF)
 add_subdirectory(Shape)
diff --git a/mlir/test/lib/Dialect/Mesh/CMakeLists.txt b/mlir/test/lib/Dialect/Mesh/CMakeLists.txt
new file mode 100644
index 000000000000..16b50bb878a0
--- /dev/null
+++ b/mlir/test/lib/Dialect/Mesh/CMakeLists.txt
@@ -0,0 +1,13 @@
+# Exclude tests from libMLIR.so
+add_mlir_library(MLIRMeshTestSimplifications
+  TestSimplifications.cpp
+
+  EXCLUDE_FROM_LIBMLIR
+
+  LINK_LIBS PUBLIC
+  MLIRMeshDialect
+  MLIRMeshTransforms
+  MLIRPass
+  MLIRRewrite
+  MLIRTransformUtils
+  )
diff --git a/mlir/test/lib/Dialect/Mesh/TestSimplifications.cpp b/mlir/test/lib/Dialect/Mesh/TestSimplifications.cpp
new file mode 100644
index 000000000000..93b1da52d46b
--- /dev/null
+++ b/mlir/test/lib/Dialect/Mesh/TestSimplifications.cpp
@@ -0,0 +1,43 @@
+//===- TestSimplification.cpp - Test simplification -----------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "mlir/Dialect/Arith/IR/Arith.h"
+#include "mlir/Dialect/Mesh/IR/MeshOps.h"
+#include "mlir/Dialect/Mesh/Transforms/Simplifications.h"
+#include "mlir/Pass/Pass.h"
+#include "mlir/Transforms/GreedyPatternRewriteDriver.h"
+
+using namespace mlir;
+
+namespace {
+struct TestMeshSimplificationsPass
+    : public PassWrapper<TestMeshSimplificationsPass, OperationPass<>> {
+  MLIR_DEFINE_EXPLICIT_INTERNAL_INLINE_TYPE_ID(TestMeshSimplificationsPass)
+
+  void runOnOperation() override;
+  void getDependentDialects(DialectRegistry &registry) const override {
+    registry.insert<arith::ArithDialect, mesh::MeshDialect>();
+  }
+  StringRef getArgument() const final { return "test-mesh-simplifications"; }
+  StringRef getDescription() const final { return "Test mesh simplifications"; }
+};
+} // namespace
+
+void TestMeshSimplificationsPass::runOnOperation() {
+  RewritePatternSet patterns(&getContext());
+  mesh::populateSimplificationPatterns(patterns);
+  (void)applyPatternsAndFoldGreedily(getOperation(), std::move(patterns));
+}
+
+namespace mlir {
+namespace test {
+void registerTestMeshSimplificationsPass() {
+  PassRegistration<TestMeshSimplificationsPass>();
+}
+} // namespace test
+} // namespace mlir
diff --git a/mlir/tools/mlir-opt/CMakeLists.txt b/mlir/tools/mlir-opt/CMakeLists.txt
index 88a0562cb6e7..bc8eed182155 100644
--- a/mlir/tools/mlir-opt/CMakeLists.txt
+++ b/mlir/tools/mlir-opt/CMakeLists.txt
@@ -26,6 +26,7 @@ if(MLIR_INCLUDE_TESTS)
     MLIRLoopLikeInterfaceTestPasses
     MLIRMathTestPasses
     MLIRMemRefTestPasses
+    MLIRMeshTestSimplifications
     MLIRNVGPUTestPasses
     MLIRSCFTestPasses
     MLIRShapeTestPasses
diff --git a/mlir/tools/mlir-opt/mlir-opt.cpp b/mlir/tools/mlir-opt/mlir-opt.cpp
index 3e3223b48505..c7cf1e55a556 100644
--- a/mlir/tools/mlir-opt/mlir-opt.cpp
+++ b/mlir/tools/mlir-opt/mlir-opt.cpp
@@ -118,6 +118,7 @@ void registerTestMathAlgebraicSimplificationPass();
 void registerTestMathPolynomialApproximationPass();
 void registerTestMemRefDependenceCheck();
 void registerTestMemRefStrideCalculation();
+void registerTestMeshSimplificationsPass();
 void registerTestNextAccessPass();
 void registerTestOneToNTypeConversionPass();
 void registerTestOpaqueLoc();
@@ -238,6 +239,7 @@ void registerTestPasses() {
   mlir::test::registerTestMathPolynomialApproximationPass();
   mlir::test::registerTestMemRefDependenceCheck();
   mlir::test::registerTestMemRefStrideCalculation();
+  mlir::test::registerTestMeshSimplificationsPass();
   mlir::test::registerTestNextAccessPass();
   mlir::test::registerTestOneToNTypeConversionPass();
   mlir::test::registerTestOpaqueLoc();
-- 
GitLab


From fa131ae3bd0cb6d4b02f61dd44b89aa9b3100855 Mon Sep 17 00:00:00 2001
From: Fangrui Song <i@maskray.me>
Date: Tue, 12 Dec 2023 10:27:38 -0800
Subject: [PATCH 342/349] [bazel,unittest] Export
 llvm_orc_registerJITLoaderGDBWrapper

---
 .../bazel/llvm-project-overlay/llvm/unittests/BUILD.bazel  | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/utils/bazel/llvm-project-overlay/llvm/unittests/BUILD.bazel b/utils/bazel/llvm-project-overlay/llvm/unittests/BUILD.bazel
index d2bcfc14ff75..8bb5de56d2d8 100644
--- a/utils/bazel/llvm-project-overlay/llvm/unittests/BUILD.bazel
+++ b/utils/bazel/llvm-project-overlay/llvm/unittests/BUILD.bazel
@@ -299,6 +299,13 @@ cc_test(
         # keep one-per-line
         "--gtest_filter=-ObjectLinkingLayerTest.TestSetProcessAllSections",
     ],
+    linkopts = select({
+        "@platforms//os:macos": [],
+        "@platforms//os:windows": [],
+        "//conditions:default": [
+            "-Wl,--export-dynamic-symbol=llvm_orc_registerJITLoaderGDBWrapper",
+        ],
+    }),
     deps = [
         "//llvm:AllTargetsAsmParsers",
         "//llvm:AllTargetsCodeGens",
-- 
GitLab


From 06613095c4e56447d75560a0968d5af4025eee58 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Tue, 12 Dec 2023 18:34:31 +0000
Subject: [PATCH 343/349] [X86] avx512-vbroadcast.ll - fix orphan check
 prefixes

The AVX512F/AVX512BW checks had been removed despite still being used
---
 llvm/test/CodeGen/X86/avx512-vbroadcast.ll | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/test/CodeGen/X86/avx512-vbroadcast.ll b/llvm/test/CodeGen/X86/avx512-vbroadcast.ll
index 52cf6f99cb4e..275df8c3675c 100644
--- a/llvm/test/CodeGen/X86/avx512-vbroadcast.ll
+++ b/llvm/test/CodeGen/X86/avx512-vbroadcast.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512f | FileCheck %s --check-prefix=ALL
-; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512bw | FileCheck %s --check-prefix=ALL
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512f | FileCheck %s --check-prefixes=ALL,AVX512F
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512bw | FileCheck %s --check-prefixes=ALL,AVX512BW
 
 define   <16 x i32> @_inreg16xi32(i32 %a) {
 ; ALL-LABEL: _inreg16xi32:
-- 
GitLab


From 31b72b0742b09c970bea47b70eb535fe964e3c8f Mon Sep 17 00:00:00 2001
From: Yinying Li <107574043+yinying-lisa-li@users.noreply.github.com>
Date: Tue, 12 Dec 2023 13:43:03 -0500
Subject: [PATCH 344/349] [mlir][sparse]Make isBlockSparsity more robust
 (#75113)

1. A single dimension can either be blocked (with floordiv and mod pair)
or non-blocked. Mixing them would be invalid.
2. Block size should be non-zero value.
---
 .../SparseTensor/IR/SparseTensorDialect.cpp   | 14 +++++-
 .../SparseTensor/invalid_encoding.mlir        | 45 +++++++++++++++++++
 2 files changed, 57 insertions(+), 2 deletions(-)

diff --git a/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp b/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
index 686180c09da7..6033ebf6897c 100644
--- a/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
+++ b/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
@@ -856,12 +856,13 @@ bool mlir::sparse_tensor::isBlockSparsity(AffineMap dimToLvl) {
   if (!dimToLvl)
     return false;
   std::map<unsigned, int64_t> coeffientMap;
+  bool hasBlock = false;
   for (auto result : dimToLvl.getResults()) {
     if (auto binOp = dyn_cast<AffineBinaryOpExpr>(result)) {
       // Check for "dim op const".
       auto dimOp = dyn_cast<AffineDimExpr>(binOp.getLHS());
       auto conOp = dyn_cast<AffineConstantExpr>(binOp.getRHS());
-      if (!dimOp || !conOp)
+      if (!dimOp || !conOp || conOp.getValue() <= 0)
         return false;
       // Inspect "dim / const" or "dim % const".
       auto pos = dimOp.getPosition();
@@ -878,12 +879,21 @@ bool mlir::sparse_tensor::isBlockSparsity(AffineMap dimToLvl) {
         // Expect mod to have the same coefficient as floordiv.
         if (conOp.getValue() != coeffientMap[pos])
           return false;
+        hasBlock = true;
       } else {
         return false;
       }
+    } else if (auto dimOp = dyn_cast<AffineDimExpr>(result)) {
+      auto pos = dimOp.getPosition();
+      // Expect dim to be unset.
+      if (coeffientMap.find(pos) != coeffientMap.end())
+        return false;
+      coeffientMap[pos] = 0;
+    } else {
+      return false;
     }
   }
-  return !coeffientMap.empty();
+  return hasBlock;
 }
 
 bool mlir::sparse_tensor::hasAnyNonIdentityOperandsOrResults(Operation *op) {
diff --git a/mlir/test/Dialect/SparseTensor/invalid_encoding.mlir b/mlir/test/Dialect/SparseTensor/invalid_encoding.mlir
index 6514391bae92..2d189cc94c15 100644
--- a/mlir/test/Dialect/SparseTensor/invalid_encoding.mlir
+++ b/mlir/test/Dialect/SparseTensor/invalid_encoding.mlir
@@ -254,6 +254,51 @@ func.func private @wrong_order_lvl_decl(%arg0: tensor<?x?xf64, #WrongOrderLvlDec
 
 // -----
 
+// expected-error@+1 {{failed to infer lvlToDim from dimToLvl}}
+#BSR = #sparse_tensor.encoding<{
+  map = ( i, j ) ->
+  ( i floordiv 2 : dense,
+    j floordiv 3 : compressed,
+    i            : dense,
+    j mod 3      : dense
+  )
+}>
+func.func private @BSR(%arg0: tensor<?x?xf64, #BSR>) {
+  return
+}
+
+// -----
+
+// expected-error@+1 {{failed to infer lvlToDim from dimToLvl}}
+#BSR = #sparse_tensor.encoding<{
+  map = ( i, j ) ->
+  ( i            : dense,
+    j floordiv 3 : compressed,
+    i floordiv 3 : dense,
+    j mod 3      : dense
+  )
+}>
+func.func private @BSR(%arg0: tensor<?x?xf64, #BSR>) {
+  return
+}
+
+// -----
+
+// expected-error@+1 {{failed to infer lvlToDim from dimToLvl}}
+#BSR = #sparse_tensor.encoding<{
+  map = ( i, j ) ->
+  ( i floordiv -3 : dense,
+    j floordiv -3 : compressed,
+    i mod 3 : dense,
+    j mod 3      : dense
+  )
+}>
+func.func private @BSR(%arg0: tensor<?x?xf64, #BSR>) {
+  return
+}
+
+// -----
+
 // expected-error@+1 {{expected lvlToDim to be an inverse of dimToLvl}}
 #BSR_explicit = #sparse_tensor.encoding<{
   map =
-- 
GitLab


From a06c7d9e5f3e2051c169b56f7a07cffa3be99b51 Mon Sep 17 00:00:00 2001
From: Mircea Trofin <mtrofin@google.com>
Date: Tue, 12 Dec 2023 10:58:17 -0800
Subject: [PATCH 345/349] [NFC][InstrProf] Rename internal `InstrProfiling` to
 `InstrLowerer` (#75139)

Captures its responsibility a bit better.
---
 .../Instrumentation/InstrProfiling.cpp        | 76 +++++++++----------
 1 file changed, 38 insertions(+), 38 deletions(-)

diff --git a/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp b/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
index c1127259d304..8674740001e5 100644
--- a/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
+++ b/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
@@ -154,11 +154,11 @@ cl::opt<bool> SkipRetExitBlock(
 
 using LoadStorePair = std::pair<Instruction *, Instruction *>;
 
-class InstrProfiling final {
+class InstrLowerer final {
 public:
-  InstrProfiling(Module &M, const InstrProfOptions &Options,
-                 std::function<const TargetLibraryInfo &(Function &F)> GetTLI,
-                 bool IsCS)
+  InstrLowerer(Module &M, const InstrProfOptions &Options,
+               std::function<const TargetLibraryInfo &(Function &F)> GetTLI,
+               bool IsCS)
       : M(M), Options(Options), TT(Triple(M.getTargetTriple())), IsCS(IsCS),
         GetTLI(GetTLI) {}
 
@@ -563,14 +563,14 @@ PreservedAnalyses InstrProfilingLoweringPass::run(Module &M,
   auto GetTLI = [&FAM](Function &F) -> TargetLibraryInfo & {
     return FAM.getResult<TargetLibraryAnalysis>(F);
   };
-  InstrProfiling Lowerer(M, Options, GetTLI, IsCS);
+  InstrLowerer Lowerer(M, Options, GetTLI, IsCS);
   if (!Lowerer.lower())
     return PreservedAnalyses::all();
 
   return PreservedAnalyses::none();
 }
 
-bool InstrProfiling::lowerIntrinsics(Function *F) {
+bool InstrLowerer::lowerIntrinsics(Function *F) {
   bool MadeChange = false;
   PromotionCandidates.clear();
   for (BasicBlock &BB : *F) {
@@ -610,7 +610,7 @@ bool InstrProfiling::lowerIntrinsics(Function *F) {
   return true;
 }
 
-bool InstrProfiling::isRuntimeCounterRelocationEnabled() const {
+bool InstrLowerer::isRuntimeCounterRelocationEnabled() const {
   // Mach-O don't support weak external references.
   if (TT.isOSBinFormatMachO())
     return false;
@@ -622,14 +622,14 @@ bool InstrProfiling::isRuntimeCounterRelocationEnabled() const {
   return TT.isOSFuchsia();
 }
 
-bool InstrProfiling::isCounterPromotionEnabled() const {
+bool InstrLowerer::isCounterPromotionEnabled() const {
   if (DoCounterPromotion.getNumOccurrences() > 0)
     return DoCounterPromotion;
 
   return Options.DoCounterPromotion;
 }
 
-void InstrProfiling::promoteCounterLoadStores(Function *F) {
+void InstrLowerer::promoteCounterLoadStores(Function *F) {
   if (!isCounterPromotionEnabled())
     return;
 
@@ -686,7 +686,7 @@ static bool containsProfilingIntrinsics(Module &M) {
          containsIntrinsic(llvm::Intrinsic::instrprof_value_profile);
 }
 
-bool InstrProfiling::lower() {
+bool InstrLowerer::lower() {
   bool MadeChange = false;
   bool NeedsRuntimeHook = needsRuntimeHookUnconditionally(TT);
   if (NeedsRuntimeHook)
@@ -778,7 +778,7 @@ static FunctionCallee getOrInsertValueProfilingCall(
   return M.getOrInsertFunction(FuncName, ValueProfilingCallTy, AL);
 }
 
-void InstrProfiling::computeNumValueSiteCounts(InstrProfValueProfileInst *Ind) {
+void InstrLowerer::computeNumValueSiteCounts(InstrProfValueProfileInst *Ind) {
   GlobalVariable *Name = Ind->getName();
   uint64_t ValueKind = Ind->getValueKind()->getZExtValue();
   uint64_t Index = Ind->getIndex()->getZExtValue();
@@ -787,7 +787,7 @@ void InstrProfiling::computeNumValueSiteCounts(InstrProfValueProfileInst *Ind) {
       std::max(PD.NumValueSites[ValueKind], (uint32_t)(Index + 1));
 }
 
-void InstrProfiling::lowerValueProfileInst(InstrProfValueProfileInst *Ind) {
+void InstrLowerer::lowerValueProfileInst(InstrProfValueProfileInst *Ind) {
   // TODO: Value profiling heavily depends on the data section which is omitted
   // in lightweight mode. We need to move the value profile pointer to the
   // Counter struct to get this working.
@@ -833,7 +833,7 @@ void InstrProfiling::lowerValueProfileInst(InstrProfValueProfileInst *Ind) {
   Ind->eraseFromParent();
 }
 
-Value *InstrProfiling::getCounterAddress(InstrProfCntrInstBase *I) {
+Value *InstrLowerer::getCounterAddress(InstrProfCntrInstBase *I) {
   auto *Counters = getOrCreateRegionCounters(I);
   IRBuilder<> Builder(I);
 
@@ -873,7 +873,7 @@ Value *InstrProfiling::getCounterAddress(InstrProfCntrInstBase *I) {
   return Builder.CreateIntToPtr(Add, Addr->getType());
 }
 
-Value *InstrProfiling::getBitmapAddress(InstrProfMCDCTVBitmapUpdate *I) {
+Value *InstrLowerer::getBitmapAddress(InstrProfMCDCTVBitmapUpdate *I) {
   auto *Bitmaps = getOrCreateRegionBitmaps(I);
   IRBuilder<> Builder(I);
 
@@ -892,7 +892,7 @@ Value *InstrProfiling::getBitmapAddress(InstrProfMCDCTVBitmapUpdate *I) {
   return Addr;
 }
 
-void InstrProfiling::lowerCover(InstrProfCoverInst *CoverInstruction) {
+void InstrLowerer::lowerCover(InstrProfCoverInst *CoverInstruction) {
   auto *Addr = getCounterAddress(CoverInstruction);
   IRBuilder<> Builder(CoverInstruction);
   // We store zero to represent that this block is covered.
@@ -900,7 +900,7 @@ void InstrProfiling::lowerCover(InstrProfCoverInst *CoverInstruction) {
   CoverInstruction->eraseFromParent();
 }
 
-void InstrProfiling::lowerTimestamp(
+void InstrLowerer::lowerTimestamp(
     InstrProfTimestampInst *TimestampInstruction) {
   assert(TimestampInstruction->getIndex()->isZeroValue() &&
          "timestamp probes are always the first probe for a function");
@@ -915,7 +915,7 @@ void InstrProfiling::lowerTimestamp(
   TimestampInstruction->eraseFromParent();
 }
 
-void InstrProfiling::lowerIncrement(InstrProfIncrementInst *Inc) {
+void InstrLowerer::lowerIncrement(InstrProfIncrementInst *Inc) {
   auto *Addr = getCounterAddress(Inc);
 
   IRBuilder<> Builder(Inc);
@@ -934,7 +934,7 @@ void InstrProfiling::lowerIncrement(InstrProfIncrementInst *Inc) {
   Inc->eraseFromParent();
 }
 
-void InstrProfiling::lowerCoverageData(GlobalVariable *CoverageNamesVar) {
+void InstrLowerer::lowerCoverageData(GlobalVariable *CoverageNamesVar) {
   ConstantArray *Names =
       cast<ConstantArray>(CoverageNamesVar->getInitializer());
   for (unsigned I = 0, E = Names->getNumOperands(); I < E; ++I) {
@@ -951,7 +951,7 @@ void InstrProfiling::lowerCoverageData(GlobalVariable *CoverageNamesVar) {
   CoverageNamesVar->eraseFromParent();
 }
 
-void InstrProfiling::lowerMCDCTestVectorBitmapUpdate(
+void InstrLowerer::lowerMCDCTestVectorBitmapUpdate(
     InstrProfMCDCTVBitmapUpdate *Update) {
   IRBuilder<> Builder(Update);
   auto *Int8Ty = Type::getInt8Ty(M.getContext());
@@ -1003,7 +1003,7 @@ void InstrProfiling::lowerMCDCTestVectorBitmapUpdate(
   Update->eraseFromParent();
 }
 
-void InstrProfiling::lowerMCDCCondBitmapUpdate(
+void InstrLowerer::lowerMCDCCondBitmapUpdate(
     InstrProfMCDCCondBitmapUpdate *Update) {
   IRBuilder<> Builder(Update);
   auto *Int32Ty = Type::getInt32Ty(M.getContext());
@@ -1186,8 +1186,8 @@ static bool needsRuntimeRegistrationOfSectionRange(const Triple &TT) {
   return true;
 }
 
-void InstrProfiling::maybeSetComdat(GlobalVariable *GV, Function *Fn,
-                                    StringRef VarName) {
+void InstrLowerer::maybeSetComdat(GlobalVariable *GV, Function *Fn,
+                                  StringRef VarName) {
   bool DataReferencedByCode = profDataReferencedByCode(M);
   bool NeedComdat = needsComdatForCounter(*Fn, M);
   bool UseComdat = (NeedComdat || TT.isOSBinFormatELF());
@@ -1208,8 +1208,8 @@ void InstrProfiling::maybeSetComdat(GlobalVariable *GV, Function *Fn,
     GV->setLinkage(GlobalValue::InternalLinkage);
 }
 
-GlobalVariable *InstrProfiling::setupProfileSection(InstrProfInstBase *Inc,
-                                                    InstrProfSectKind IPSK) {
+GlobalVariable *InstrLowerer::setupProfileSection(InstrProfInstBase *Inc,
+                                                  InstrProfSectKind IPSK) {
   GlobalVariable *NamePtr = Inc->getName();
 
   // Match the linkage and visibility of the name global.
@@ -1278,9 +1278,9 @@ GlobalVariable *InstrProfiling::setupProfileSection(InstrProfInstBase *Inc,
 }
 
 GlobalVariable *
-InstrProfiling::createRegionBitmaps(InstrProfMCDCBitmapInstBase *Inc,
-                                    StringRef Name,
-                                    GlobalValue::LinkageTypes Linkage) {
+InstrLowerer::createRegionBitmaps(InstrProfMCDCBitmapInstBase *Inc,
+                                  StringRef Name,
+                                  GlobalValue::LinkageTypes Linkage) {
   uint64_t NumBytes = Inc->getNumBitmapBytes()->getZExtValue();
   auto *BitmapTy = ArrayType::get(Type::getInt8Ty(M.getContext()), NumBytes);
   auto GV = new GlobalVariable(M, BitmapTy, false, Linkage,
@@ -1290,7 +1290,7 @@ InstrProfiling::createRegionBitmaps(InstrProfMCDCBitmapInstBase *Inc,
 }
 
 GlobalVariable *
-InstrProfiling::getOrCreateRegionBitmaps(InstrProfMCDCBitmapInstBase *Inc) {
+InstrLowerer::getOrCreateRegionBitmaps(InstrProfMCDCBitmapInstBase *Inc) {
   GlobalVariable *NamePtr = Inc->getName();
   auto &PD = ProfileDataMap[NamePtr];
   if (PD.RegionBitmaps)
@@ -1305,8 +1305,8 @@ InstrProfiling::getOrCreateRegionBitmaps(InstrProfMCDCBitmapInstBase *Inc) {
 }
 
 GlobalVariable *
-InstrProfiling::createRegionCounters(InstrProfCntrInstBase *Inc, StringRef Name,
-                                     GlobalValue::LinkageTypes Linkage) {
+InstrLowerer::createRegionCounters(InstrProfCntrInstBase *Inc, StringRef Name,
+                                   GlobalValue::LinkageTypes Linkage) {
   uint64_t NumCounters = Inc->getNumCounters()->getZExtValue();
   auto &Ctx = M.getContext();
   GlobalVariable *GV;
@@ -1330,7 +1330,7 @@ InstrProfiling::createRegionCounters(InstrProfCntrInstBase *Inc, StringRef Name,
 }
 
 GlobalVariable *
-InstrProfiling::getOrCreateRegionCounters(InstrProfCntrInstBase *Inc) {
+InstrLowerer::getOrCreateRegionCounters(InstrProfCntrInstBase *Inc) {
   GlobalVariable *NamePtr = Inc->getName();
   auto &PD = ProfileDataMap[NamePtr];
   if (PD.RegionCounters)
@@ -1383,7 +1383,7 @@ InstrProfiling::getOrCreateRegionCounters(InstrProfCntrInstBase *Inc) {
   return PD.RegionCounters;
 }
 
-void InstrProfiling::createDataVariable(InstrProfCntrInstBase *Inc) {
+void InstrLowerer::createDataVariable(InstrProfCntrInstBase *Inc) {
   // When debug information is correlated to profile data, a data variable
   // is not needed.
   if (DebugInfoCorrelate)
@@ -1523,7 +1523,7 @@ void InstrProfiling::createDataVariable(InstrProfCntrInstBase *Inc) {
   ReferencedNames.push_back(NamePtr);
 }
 
-void InstrProfiling::emitVNodes() {
+void InstrLowerer::emitVNodes() {
   if (!ValueProfileStaticAlloc)
     return;
 
@@ -1574,7 +1574,7 @@ void InstrProfiling::emitVNodes() {
   UsedVars.push_back(VNodesVar);
 }
 
-void InstrProfiling::emitNameData() {
+void InstrLowerer::emitNameData() {
   std::string UncompressedData;
 
   if (ReferencedNames.empty())
@@ -1608,7 +1608,7 @@ void InstrProfiling::emitNameData() {
     NamePtr->eraseFromParent();
 }
 
-void InstrProfiling::emitRegistration() {
+void InstrLowerer::emitRegistration() {
   if (!needsRuntimeRegistrationOfSectionRange(TT))
     return;
 
@@ -1649,7 +1649,7 @@ void InstrProfiling::emitRegistration() {
   IRB.CreateRetVoid();
 }
 
-bool InstrProfiling::emitRuntimeHook() {
+bool InstrLowerer::emitRuntimeHook() {
   // We expect the linker to be invoked with -u<hook_var> flag for Linux
   // in which case there is no need to emit the external variable.
   if (TT.isOSLinux() || TT.isOSAIX())
@@ -1691,7 +1691,7 @@ bool InstrProfiling::emitRuntimeHook() {
   return true;
 }
 
-void InstrProfiling::emitUses() {
+void InstrLowerer::emitUses() {
   // The metadata sections are parallel arrays. Optimizers (e.g.
   // GlobalOpt/ConstantMerge) may not discard associated sections as a unit, so
   // we conservatively retain all unconditionally in the compiler.
@@ -1713,7 +1713,7 @@ void InstrProfiling::emitUses() {
   appendToUsed(M, UsedVars);
 }
 
-void InstrProfiling::emitInitialization() {
+void InstrLowerer::emitInitialization() {
   // Create ProfileFileName variable. Don't don't this for the
   // context-sensitive instrumentation lowering: This lowering is after
   // LTO/ThinLTO linking. Pass PGOInstrumentationGenCreateVar should
-- 
GitLab


From 2684281d208612a746b05c891f346bd7b95318d5 Mon Sep 17 00:00:00 2001
From: jimingham <jingham@apple.com>
Date: Tue, 12 Dec 2023 11:28:06 -0800
Subject: [PATCH 346/349] Add a test for evicting unreachable modules from the
 global module cache (#74894)

When you debug a binary and the change & rebuild and then rerun in lldb
w/o quitting lldb, the Modules in the Global Module Cache for the old
binary & .o files if used are now "unreachable". Nothing in lldb is
holding them alive, and they've already been unlinked. lldb will
properly discard them if there's not another Target referencing them.

However, this only works in simple cases at present. If you have several
Targets that reference the same modules, it's pretty easy to end up
stranding Modules that are no longer reachable, and if you use a
sequence of SBDebuggers unreachable modules can also get stranded. If
you run a long-lived lldb process and are iteratively developing on a
large code base, lldb's memory gets filled with useless Modules.

This patch adds a test for the mode that currently works:

(lldb) target create foo
(lldb) run
<rebuild foo outside lldb>
(lldb) run

In that case, we do delete the unreachable Modules.

The next step will be to add tests for the cases where we fail to do
this, then see how to safely/efficiently evict unreachable modules in
those cases as well.
---
 .../python_api/global_module_cache/Makefile   |   1 +
 .../TestGlobalModuleCache.py                  | 169 ++++++++++++++++++
 .../global_module_cache/one-print.c           |   7 +
 .../global_module_cache/two-print.c           |   8 +
 4 files changed, 185 insertions(+)
 create mode 100644 lldb/test/API/python_api/global_module_cache/Makefile
 create mode 100644 lldb/test/API/python_api/global_module_cache/TestGlobalModuleCache.py
 create mode 100644 lldb/test/API/python_api/global_module_cache/one-print.c
 create mode 100644 lldb/test/API/python_api/global_module_cache/two-print.c

diff --git a/lldb/test/API/python_api/global_module_cache/Makefile b/lldb/test/API/python_api/global_module_cache/Makefile
new file mode 100644
index 000000000000..22f1051530f8
--- /dev/null
+++ b/lldb/test/API/python_api/global_module_cache/Makefile
@@ -0,0 +1 @@
+include Makefile.rules
diff --git a/lldb/test/API/python_api/global_module_cache/TestGlobalModuleCache.py b/lldb/test/API/python_api/global_module_cache/TestGlobalModuleCache.py
new file mode 100644
index 000000000000..98ebdec0404e
--- /dev/null
+++ b/lldb/test/API/python_api/global_module_cache/TestGlobalModuleCache.py
@@ -0,0 +1,169 @@
+"""
+Test the use of the global module cache in lldb
+"""
+
+import lldb
+
+from lldbsuite.test.decorators import *
+from lldbsuite.test.lldbtest import *
+from lldbsuite.test import lldbutil
+import os
+import shutil
+from pathlib import Path
+import time
+
+class GlobalModuleCacheTestCase(TestBase):
+    # NO_DEBUG_INFO_TESTCASE = True
+
+    def check_counter_var(self, thread, value):
+        frame = thread.frames[0]
+        var = frame.FindVariable("counter")
+        self.assertTrue(var.GetError().Success(), "Got counter variable")
+        self.assertEqual(var.GetValueAsUnsigned(), value, "This was one-print")
+
+    def copy_to_main(self, src, dst):
+        # We are relying on the source file being newer than the .o file from
+        # a previous build, so sleep a bit here to ensure that the touch is later.
+        time.sleep(2)
+        try:
+            shutil.copy(src, dst)
+        except:
+            self.fail(f"Could not copy {src} to {dst}")
+        Path(dst).touch()
+
+    # The rerun tests indicate rerunning on Windows doesn't really work, so
+    # this one won't either.
+    @skipIfWindows
+    def test_OneTargetOneDebugger(self):
+        self.do_test(True, True)
+
+    # This behaves as implemented but that behavior is not desirable.
+    # This test tests for the desired behavior as an expected fail.
+    @skipIfWindows
+    @expectedFailureAll
+    def test_TwoTargetsOneDebugger(self):
+        self.do_test(False, True)
+
+    @skipIfWindows
+    @expectedFailureAll
+    def test_OneTargetTwoDebuggers(self):
+        self.do_test(True, False)
+
+    def do_test(self, one_target, one_debugger):
+        # Make sure that if we have one target, and we run, then
+        # change the binary and rerun, the binary (and any .o files
+        # if using dwarf in .o file debugging) get removed from the
+        # shared module cache.  They are no longer reachable.
+        debug_style = self.getDebugInfo()
+
+        # Before we do anything, clear the global module cache so we don't
+        # see objects from other runs:
+        lldb.SBDebugger.MemoryPressureDetected()
+
+        # Set up the paths for our two versions of main.c:
+        main_c_path = os.path.join(self.getBuildDir(), "main.c")
+        one_print_path = os.path.join(self.getSourceDir(), "one-print.c")
+        two_print_path = os.path.join(self.getSourceDir(), "two-print.c")
+        main_filespec = lldb.SBFileSpec(main_c_path)
+
+        # First copy the one-print.c to main.c in the build folder and
+        # build our a.out from there:
+        self.copy_to_main(one_print_path, main_c_path)
+        self.build(dictionary={"C_SOURCES": main_c_path, "EXE": "a.out"})
+
+        (target, process, thread, bkpt) = lldbutil.run_to_source_breakpoint(
+            self, "return counter;", main_filespec
+        )
+
+        # Make sure we ran the version we intended here:
+        self.check_counter_var(thread, 1)
+        process.Kill()
+
+        # Now copy two-print.c over main.c, rebuild, and rerun:
+        # os.unlink(target.GetExecutable().fullpath)
+        self.copy_to_main(two_print_path, main_c_path)
+
+        self.build(dictionary={"C_SOURCES": main_c_path, "EXE": "a.out"})
+        error = lldb.SBError()
+        if one_debugger:
+            if one_target:
+                (_, process, thread, _) = lldbutil.run_to_breakpoint_do_run(
+                    self, target, bkpt
+                )
+            else:
+                (target2, process2, thread, bkpt) = lldbutil.run_to_source_breakpoint(
+                    self, "return counter;", main_filespec
+                )
+        else:
+            if one_target:
+                new_debugger = lldb.SBDebugger().Create()
+                self.old_debugger = self.dbg
+                self.dbg = new_debugger
+                def cleanupDebugger(self):
+                    lldb.SBDebugger.Destroy(self.dbg)
+                    self.dbg = self.old_debugger
+                    self.old_debugger = None
+
+                self.addTearDownHook(cleanupDebugger)
+                (target2, process2, thread, bkpt) = lldbutil.run_to_source_breakpoint(
+                    self, "return counter;", main_filespec
+                )
+
+        # In two-print.c counter will be 2:
+        self.check_counter_var(thread, 2)
+
+        # If we made two targets, destroy the first one, that should free up the
+        # unreachable Modules:
+        if not one_target:
+            target.Clear()
+
+        num_a_dot_out_entries = 1
+        # For dSYM's there will be two lines of output, one for the a.out and one
+        # for the dSYM.
+        if debug_style == "dsym":
+            num_a_dot_out_entries += 1
+
+        error = self.check_image_list_result(num_a_dot_out_entries, 1)
+        # Even if this fails, MemoryPressureDetected should fix this.
+        lldb.SBDebugger.MemoryPressureDetected()
+        error_after_mpd = self.check_image_list_result(num_a_dot_out_entries, 1)
+        fail_msg = ""
+        if error != "":
+            fail_msg = "Error before MPD: " + error
+            
+        if error_after_mpd != "":
+            fail_msg = fail_msg + "\nError after MPD: " + error_after_mpd
+        if fail_msg != "":
+            self.fail(fail_msg)
+
+    def check_image_list_result(self, num_a_dot_out, num_main_dot_o):
+        # Check the global module list, there should only be one a.out, and if we are
+        # doing dwarf in .o file, there should only be one .o file.  This returns
+        # an error string on error - rather than asserting, so you can stage this
+        # failing.
+        image_cmd_result = lldb.SBCommandReturnObject()
+        interp = self.dbg.GetCommandInterpreter()
+        interp.HandleCommand("image list -g", image_cmd_result)
+        if self.TraceOn():
+            print(f"Expected: a.out: {num_a_dot_out} main.o: {num_main_dot_o}")
+            print(image_cmd_result)
+
+        image_list_str = image_cmd_result.GetOutput()
+        image_list = image_list_str.splitlines()
+        found_a_dot_out = 0
+        found_main_dot_o = 0
+
+        for line in image_list:
+            # FIXME: force this to be at the end of the string:
+            if "a.out" in line:
+                found_a_dot_out += 1
+            if "main.o" in line:
+                found_main_dot_o += 1
+        
+        if num_a_dot_out != found_a_dot_out:
+            return f"Got {found_a_dot_out} number of a.out's, expected {num_a_dot_out}"
+            
+        if found_main_dot_o > 0 and num_main_dot_o != found_main_dot_o:
+            return f"Got {found_main_dot_o} number of main.o's, expected {num_main_dot_o}"
+
+        return ""
diff --git a/lldb/test/API/python_api/global_module_cache/one-print.c b/lldb/test/API/python_api/global_module_cache/one-print.c
new file mode 100644
index 000000000000..f008f36c2554
--- /dev/null
+++ b/lldb/test/API/python_api/global_module_cache/one-print.c
@@ -0,0 +1,7 @@
+#include <stdio.h>
+
+int main() {
+  int counter = 0;
+  printf("I only print one time: %d.\n", counter++);
+  return counter;
+}
diff --git a/lldb/test/API/python_api/global_module_cache/two-print.c b/lldb/test/API/python_api/global_module_cache/two-print.c
new file mode 100644
index 000000000000..96f68cbed83c
--- /dev/null
+++ b/lldb/test/API/python_api/global_module_cache/two-print.c
@@ -0,0 +1,8 @@
+#include <stdio.h>
+
+int main() {
+  int counter = 0;
+  printf("I print one time: %d.\n", counter++);
+  printf("I print two times: %d.\n", counter++);
+  return counter;
+}
-- 
GitLab


From 7f54070194f552e0c5de7543ad05e9ea163461ba Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin <rampitec@users.noreply.github.com>
Date: Tue, 12 Dec 2023 12:29:09 -0800
Subject: [PATCH 347/349] [AMDGPU] Precommit test for LDS DMA waitcounts. NFC.
 (#75240)

---
 llvm/test/CodeGen/AMDGPU/lds-dma-waits.ll | 78 +++++++++++++++++++++++
 1 file changed, 78 insertions(+)
 create mode 100644 llvm/test/CodeGen/AMDGPU/lds-dma-waits.ll

diff --git a/llvm/test/CodeGen/AMDGPU/lds-dma-waits.ll b/llvm/test/CodeGen/AMDGPU/lds-dma-waits.ll
new file mode 100644
index 000000000000..688f0314f7d8
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/lds-dma-waits.ll
@@ -0,0 +1,78 @@
+; RUN: llc -march=amdgcn -mcpu=gfx900 < %s | FileCheck %s --check-prefixes=GCN,GFX9
+; RUN: llc -march=amdgcn -mcpu=gfx1030 < %s | FileCheck %s --check-prefixes=GCN,GFX10
+
+@lds.0 = internal addrspace(3) global [64 x float] poison, align 16
+@lds.1 = internal addrspace(3) global [64 x float] poison, align 16
+
+declare void @llvm.amdgcn.raw.buffer.load.lds(<4 x i32> %rsrc, ptr addrspace(3) nocapture, i32 %size, i32 %voffset, i32 %soffset, i32 %offset, i32 %aux)
+declare void @llvm.amdgcn.global.load.lds(ptr addrspace(1) nocapture %gptr, ptr addrspace(3) nocapture %lptr, i32 %size, i32 %offset, i32 %aux)
+
+; FIXME: vmcnt(0) is too strong, it shall use vmcnt(2) before the first
+;        ds_read_b32 and vmcnt(0) before the second.
+; FIXME: GFX10 does not get a waitcount at all.
+
+; GCN-LABEL: {{^}}buffer_load_lds_dword_2_arrays:
+; GCN-COUNT-4: buffer_load_dword
+; GFX9: s_waitcnt vmcnt(0)
+
+; FIXME:
+; GFX10-NOT: s_waitcnt
+
+; GCN: ds_read_b32
+
+; FIXME:
+; GCN-NOT: s_waitcnt
+
+; GCN: ds_read_b32
+define amdgpu_kernel void @buffer_load_lds_dword_2_arrays(<4 x i32> %rsrc, i32 %i1, i32 %i2, ptr addrspace(1) %out) {
+main_body:
+  call void @llvm.amdgcn.raw.buffer.load.lds(<4 x i32> %rsrc, ptr addrspace(3) @lds.0, i32 4, i32 0, i32 0, i32 0, i32 0)
+  call void @llvm.amdgcn.raw.buffer.load.lds(<4 x i32> %rsrc, ptr addrspace(3) @lds.0, i32 4, i32 4, i32 0, i32 0, i32 0)
+  call void @llvm.amdgcn.raw.buffer.load.lds(<4 x i32> %rsrc, ptr addrspace(3) @lds.1, i32 4, i32 8, i32 0, i32 0, i32 0)
+  call void @llvm.amdgcn.raw.buffer.load.lds(<4 x i32> %rsrc, ptr addrspace(3) @lds.1, i32 4, i32 12, i32 0, i32 0, i32 0)
+  %gep.0 = getelementptr float, ptr addrspace(3) @lds.0, i32 %i1
+  %gep.1 = getelementptr float, ptr addrspace(3) @lds.1, i32 %i2
+  %val.0 = load float, ptr addrspace(3) %gep.0, align 4
+  call void @llvm.amdgcn.wave.barrier()
+  %val.1 = load float, ptr addrspace(3) %gep.1, align 4
+  %tmp.0 = insertelement <2 x float> undef, float %val.0, i32 0
+  %res = insertelement <2 x float> %tmp.0, float %val.1, i32 1
+  store <2 x float> %res, ptr addrspace(1) %out
+  ret void
+}
+
+; On gfx9 if there is a pending FLAT operation, and this is a VMem or LGKM
+; waitcnt and the target can report early completion, then we need to force a waitcnt 0.
+
+; GCN-LABEL: {{^}}global_load_lds_dword_2_arrays:
+; GCN-COUNT-4: global_load_dword
+; GFX9: s_waitcnt vmcnt(0)
+; GFX9-COUNT-2: ds_read_b32
+
+; FIXME:
+; GFX10-NOT: s_waitcnt
+
+; GFX10: ds_read_b32
+
+; FIXME:
+; GFX10-NOT: s_waitcnt
+
+; GFX10: ds_read_b32
+define amdgpu_kernel void @global_load_lds_dword_2_arrays(ptr addrspace(1) nocapture %gptr, i32 %i1, i32 %i2, ptr addrspace(1) %out) {
+main_body:
+  call void @llvm.amdgcn.global.load.lds(ptr addrspace(1) %gptr, ptr addrspace(3) @lds.0, i32 4, i32 0, i32 0)
+  call void @llvm.amdgcn.global.load.lds(ptr addrspace(1) %gptr, ptr addrspace(3) @lds.0, i32 4, i32 4, i32 0)
+  call void @llvm.amdgcn.global.load.lds(ptr addrspace(1) %gptr, ptr addrspace(3) @lds.1, i32 4, i32 8, i32 0)
+  call void @llvm.amdgcn.global.load.lds(ptr addrspace(1) %gptr, ptr addrspace(3) @lds.1, i32 4, i32 12, i32 0)
+  %gep.0 = getelementptr float, ptr addrspace(3) @lds.0, i32 %i1
+  %gep.1 = getelementptr float, ptr addrspace(3) @lds.1, i32 %i2
+  %val.0 = load float, ptr addrspace(3) %gep.0, align 4
+  call void @llvm.amdgcn.wave.barrier()
+  %val.1 = load float, ptr addrspace(3) %gep.1, align 4
+  %tmp.0 = insertelement <2 x float> undef, float %val.0, i32 0
+  %res = insertelement <2 x float> %tmp.0, float %val.1, i32 1
+  store <2 x float> %res, ptr addrspace(1) %out
+  ret void
+}
+
+declare void @llvm.amdgcn.wave.barrier()
-- 
GitLab


From 3568521e3d2d09d12bd0c476d0376de165b19178 Mon Sep 17 00:00:00 2001
From: Schrodinger ZHU Yifan <yifanzhu@rochester.edu>
Date: Tue, 12 Dec 2023 15:31:51 -0500
Subject: [PATCH 348/349] [libc] fix issues around stack protector (#74567)

If a function is declared with stack-protector, the compiler may try to
load the TLS. However, inside certain runtime functions, TLS may not be
available. This patch disables stack protectors for such routines to fix
the problem.

Closes #74487.
---
 libc/src/__support/OSUtil/linux/quick_exit.h | 10 ++++++++--
 libc/startup/linux/aarch64/start.cpp         | 14 ++++++++------
 libc/startup/linux/riscv/start.cpp           | 14 ++++++++------
 libc/startup/linux/x86_64/CMakeLists.txt     |  1 +
 libc/startup/linux/x86_64/start.cpp          | 14 ++++++++------
 5 files changed, 33 insertions(+), 20 deletions(-)

diff --git a/libc/src/__support/OSUtil/linux/quick_exit.h b/libc/src/__support/OSUtil/linux/quick_exit.h
index c461d5f8b8fc..432395584d84 100644
--- a/libc/src/__support/OSUtil/linux/quick_exit.h
+++ b/libc/src/__support/OSUtil/linux/quick_exit.h
@@ -9,7 +9,7 @@
 #ifndef LLVM_LIBC_SRC___SUPPORT_OSUTIL_LINUX_QUICK_EXIT_H
 #define LLVM_LIBC_SRC___SUPPORT_OSUTIL_LINUX_QUICK_EXIT_H
 
-#include "syscall.h"             // For internal syscall function.
+#include "syscall.h" // For internal syscall function.
 
 #include "src/__support/common.h"
 
@@ -17,7 +17,13 @@
 
 namespace LIBC_NAMESPACE {
 
-LIBC_INLINE void quick_exit(int status) {
+// mark as no_stack_protector for x86 since TLS can be torn down before calling
+// quick_exit so that the stack protector canary cannot be loaded.
+#ifdef LIBC_TARGET_ARCH_IS_X86
+__attribute__((no_stack_protector))
+#endif
+LIBC_INLINE void
+quick_exit(int status) {
   for (;;) {
     LIBC_NAMESPACE::syscall_impl<long>(SYS_exit_group, status);
     LIBC_NAMESPACE::syscall_impl<long>(SYS_exit, status);
diff --git a/libc/startup/linux/aarch64/start.cpp b/libc/startup/linux/aarch64/start.cpp
index b5c426866b56..c3e20eb09e4b 100644
--- a/libc/startup/linux/aarch64/start.cpp
+++ b/libc/startup/linux/aarch64/start.cpp
@@ -184,7 +184,9 @@ __attribute__((noinline)) static void do_start() {
     app.tls.align = phdr->p_align;
   }
 
-  LIBC_NAMESPACE::TLSDescriptor tls;
+  // This descriptor has to be static since its cleanup function cannot
+  // capture the context.
+  static LIBC_NAMESPACE::TLSDescriptor tls;
   LIBC_NAMESPACE::init_tls(tls);
   if (tls.size != 0)
     LIBC_NAMESPACE::set_thread_ptr(tls.tp);
@@ -192,7 +194,11 @@ __attribute__((noinline)) static void do_start() {
   LIBC_NAMESPACE::self.attrib = &LIBC_NAMESPACE::main_thread_attrib;
   LIBC_NAMESPACE::main_thread_attrib.atexit_callback_mgr =
       LIBC_NAMESPACE::internal::get_thread_atexit_callback_mgr();
-
+  // We register the cleanup_tls function to be the last atexit callback to be
+  // invoked. It will tear down the TLS. Other callbacks may depend on TLS (such
+  // as the stack protector canary).
+  LIBC_NAMESPACE::atexit(
+      []() { LIBC_NAMESPACE::cleanup_tls(tls.tp, tls.size); });
   // We want the fini array callbacks to be run after other atexit
   // callbacks are run. So, we register them before running the init
   // array callbacks as they can potentially register their own atexit
@@ -208,10 +214,6 @@ __attribute__((noinline)) static void do_start() {
                     reinterpret_cast<char **>(app.args->argv),
                     reinterpret_cast<char **>(env_ptr));
 
-  // TODO: TLS cleanup should be done after all other atexit callbacks
-  // are run. So, register a cleanup callback for it with atexit before
-  // everything else.
-  LIBC_NAMESPACE::cleanup_tls(tls.addr, tls.size);
   LIBC_NAMESPACE::exit(retval);
 }
 
diff --git a/libc/startup/linux/riscv/start.cpp b/libc/startup/linux/riscv/start.cpp
index bf04be5ad14a..4d37662ccea1 100644
--- a/libc/startup/linux/riscv/start.cpp
+++ b/libc/startup/linux/riscv/start.cpp
@@ -187,7 +187,9 @@ __attribute__((noinline)) static void do_start() {
     app.tls.align = phdr->p_align;
   }
 
-  LIBC_NAMESPACE::TLSDescriptor tls;
+  // This descriptor has to be static since its cleanup function cannot
+  // capture the context.
+  static LIBC_NAMESPACE::TLSDescriptor tls;
   LIBC_NAMESPACE::init_tls(tls);
   if (tls.size != 0)
     LIBC_NAMESPACE::set_thread_ptr(tls.tp);
@@ -195,7 +197,11 @@ __attribute__((noinline)) static void do_start() {
   LIBC_NAMESPACE::self.attrib = &LIBC_NAMESPACE::main_thread_attrib;
   LIBC_NAMESPACE::main_thread_attrib.atexit_callback_mgr =
       LIBC_NAMESPACE::internal::get_thread_atexit_callback_mgr();
-
+  // We register the cleanup_tls function to be the last atexit callback to be
+  // invoked. It will tear down the TLS. Other callbacks may depend on TLS (such
+  // as the stack protector canary).
+  LIBC_NAMESPACE::atexit(
+      []() { LIBC_NAMESPACE::cleanup_tls(tls.tp, tls.size); });
   // We want the fini array callbacks to be run after other atexit
   // callbacks are run. So, we register them before running the init
   // array callbacks as they can potentially register their own atexit
@@ -211,10 +217,6 @@ __attribute__((noinline)) static void do_start() {
                     reinterpret_cast<char **>(app.args->argv),
                     reinterpret_cast<char **>(env_ptr));
 
-  // TODO: TLS cleanup should be done after all other atexit callbacks
-  // are run. So, register a cleanup callback for it with atexit before
-  // everything else.
-  LIBC_NAMESPACE::cleanup_tls(tls.addr, tls.size);
   LIBC_NAMESPACE::exit(retval);
 }
 
diff --git a/libc/startup/linux/x86_64/CMakeLists.txt b/libc/startup/linux/x86_64/CMakeLists.txt
index 076c0c3e444f..aac5a0626a17 100644
--- a/libc/startup/linux/x86_64/CMakeLists.txt
+++ b/libc/startup/linux/x86_64/CMakeLists.txt
@@ -15,6 +15,7 @@ add_startup_object(
     libc.src.string.memory_utils.inline_memcpy
     libc.src.unistd.environ
   COMPILE_OPTIONS
+    -fno-stack-protector
     -fno-omit-frame-pointer
     -ffreestanding # To avoid compiler warnings about calling the main function.
     -fno-builtin
diff --git a/libc/startup/linux/x86_64/start.cpp b/libc/startup/linux/x86_64/start.cpp
index bc1b4f0487f3..496105dfd0b4 100644
--- a/libc/startup/linux/x86_64/start.cpp
+++ b/libc/startup/linux/x86_64/start.cpp
@@ -222,7 +222,9 @@ extern "C" void _start() {
     app.tls.align = phdr->p_align;
   }
 
-  LIBC_NAMESPACE::TLSDescriptor tls;
+  // This descriptor has to be static since its cleanup function cannot
+  // capture the context.
+  static LIBC_NAMESPACE::TLSDescriptor tls;
   LIBC_NAMESPACE::init_tls(tls);
   if (tls.size != 0 && !LIBC_NAMESPACE::set_thread_ptr(tls.tp))
     LIBC_NAMESPACE::syscall_impl<long>(SYS_exit, 1);
@@ -230,7 +232,11 @@ extern "C" void _start() {
   LIBC_NAMESPACE::self.attrib = &LIBC_NAMESPACE::main_thread_attrib;
   LIBC_NAMESPACE::main_thread_attrib.atexit_callback_mgr =
       LIBC_NAMESPACE::internal::get_thread_atexit_callback_mgr();
-
+  // We register the cleanup_tls function to be the last atexit callback to be
+  // invoked. It will tear down the TLS. Other callbacks may depend on TLS (such
+  // as the stack protector canary).
+  LIBC_NAMESPACE::atexit(
+      []() { LIBC_NAMESPACE::cleanup_tls(tls.tp, tls.size); });
   // We want the fini array callbacks to be run after other atexit
   // callbacks are run. So, we register them before running the init
   // array callbacks as they can potentially register their own atexit
@@ -246,9 +252,5 @@ extern "C" void _start() {
                     reinterpret_cast<char **>(app.args->argv),
                     reinterpret_cast<char **>(env_ptr));
 
-  // TODO: TLS cleanup should be done after all other atexit callbacks
-  // are run. So, register a cleanup callback for it with atexit before
-  // everything else.
-  LIBC_NAMESPACE::cleanup_tls(tls.addr, tls.size);
   LIBC_NAMESPACE::exit(retval);
 }
-- 
GitLab


From c77cdbac9b121611121adf5806a99aff4812a40c Mon Sep 17 00:00:00 2001
From: Tacet <advenam.tacet@trailofbits.com>
Date: Tue, 12 Dec 2023 21:41:59 +0100
Subject: [PATCH 349/349] Add `std::basic_string` test cases (#74830)

Extend `std::basic_string` tests to cover more buffer situations and
length in general, particularly non-SSO cases after SSO test cases
(changing buffers). This commit is a side effect of working on tests for
ASan annotations.

Related PR: https://github.com/llvm/llvm-project/pull/72677
---
 .../string.capacity/reserve.pass.cpp            |  1 +
 .../string.capacity/reserve_size.pass.cpp       |  1 +
 .../string.capacity/shrink_to_fit.pass.cpp      |  4 ++++
 .../string.cons/copy_assignment.pass.cpp        |  1 +
 .../string.cons/move_assignment.pass.cpp        |  1 +
 .../string.cons/pointer_assignment.pass.cpp     |  1 +
 .../string.cons/string_view_assignment.pass.cpp |  1 +
 .../string_append/T_size_size.pass.cpp          |  5 +++++
 .../string_append/push_back.pass.cpp            |  4 ++++
 .../string_append/size_char.pass.cpp            |  5 +++++
 .../string_append/string.pass.cpp               |  8 ++++++++
 .../string_append/string_size_size.pass.cpp     |  9 +++++++++
 .../string_append/string_view.pass.cpp          |  8 ++++++++
 .../string_assign/pointer.pass.cpp              |  5 +++++
 .../string_assign/pointer_size.pass.cpp         |  6 ++++++
 .../string.modifiers/string_copy/copy.pass.cpp  |  2 ++
 .../string_insert/iter_char.pass.cpp            | 17 +++++++++++++++++
 .../string_op_plus_equal/char.pass.cpp          |  1 +
 .../string_op_plus_equal/pointer.pass.cpp       | 10 ++++++++++
 .../string_op_plus_equal/string.pass.cpp        | 10 ++++++++++
 .../string.special/swap.pass.cpp                |  4 ++++
 .../string.ops/string_substr/substr.pass.cpp    |  9 +++++++++
 22 files changed, 113 insertions(+)

diff --git a/libcxx/test/std/strings/basic.string/string.capacity/reserve.pass.cpp b/libcxx/test/std/strings/basic.string/string.capacity/reserve.pass.cpp
index ecde912dc39f..b740901be1c4 100644
--- a/libcxx/test/std/strings/basic.string/string.capacity/reserve.pass.cpp
+++ b/libcxx/test/std/strings/basic.string/string.capacity/reserve.pass.cpp
@@ -39,6 +39,7 @@ template <class S>
 void test_string() {
   test<S>(0, 0);
   test<S>(10, 5);
+  test<S>(100, 5);
   test<S>(100, 50);
 }
 
diff --git a/libcxx/test/std/strings/basic.string/string.capacity/reserve_size.pass.cpp b/libcxx/test/std/strings/basic.string/string.capacity/reserve_size.pass.cpp
index bb804bf328b3..dfb3b270f750 100644
--- a/libcxx/test/std/strings/basic.string/string.capacity/reserve_size.pass.cpp
+++ b/libcxx/test/std/strings/basic.string/string.capacity/reserve_size.pass.cpp
@@ -64,6 +64,7 @@ TEST_CONSTEXPR_CXX20 void test_string() {
     test<S>(0, 0, 50);
   }
   {
+    test<S>(100, 1, 5);
     test<S>(100, 50, 5);
     test<S>(100, 50, 10);
     test<S>(100, 50, 50);
diff --git a/libcxx/test/std/strings/basic.string/string.capacity/shrink_to_fit.pass.cpp b/libcxx/test/std/strings/basic.string/string.capacity/shrink_to_fit.pass.cpp
index 1efebfc9cea5..66eefdd383dc 100644
--- a/libcxx/test/std/strings/basic.string/string.capacity/shrink_to_fit.pass.cpp
+++ b/libcxx/test/std/strings/basic.string/string.capacity/shrink_to_fit.pass.cpp
@@ -36,6 +36,10 @@ TEST_CONSTEXPR_CXX20 void test_string() {
   s.erase(5);
   test(s);
 
+  s.assign(50, 'a');
+  s.erase(5);
+  test(s);
+
   s.assign(100, 'a');
   s.erase(50);
   test(s);
diff --git a/libcxx/test/std/strings/basic.string/string.cons/copy_assignment.pass.cpp b/libcxx/test/std/strings/basic.string/string.cons/copy_assignment.pass.cpp
index 8d0fcb3c6d29..eb522aafa243 100644
--- a/libcxx/test/std/strings/basic.string/string.cons/copy_assignment.pass.cpp
+++ b/libcxx/test/std/strings/basic.string/string.cons/copy_assignment.pass.cpp
@@ -35,6 +35,7 @@ TEST_CONSTEXPR_CXX20 void test_string() {
 
   test(S(), S("abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz"));
   test(S("123456789"), S("abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz"));
+  test(S("abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz"), S("123456789"));
   test(S("1234567890123456789012345678901234567890123456789012345678901234567890"),
        S("abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz"));
   test(S("1234567890123456789012345678901234567890123456789012345678901234567890"
diff --git a/libcxx/test/std/strings/basic.string/string.cons/move_assignment.pass.cpp b/libcxx/test/std/strings/basic.string/string.cons/move_assignment.pass.cpp
index 89cb44d62ef2..cb0fe0396cb7 100644
--- a/libcxx/test/std/strings/basic.string/string.cons/move_assignment.pass.cpp
+++ b/libcxx/test/std/strings/basic.string/string.cons/move_assignment.pass.cpp
@@ -40,6 +40,7 @@ TEST_CONSTEXPR_CXX20 void test_string() {
 
   test(S(), S("abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz"));
   test(S("123456789"), S("abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz"));
+  test(S("abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz"), S("123456789"));
   test(S("1234567890123456789012345678901234567890123456789012345678901234567890"),
        S("abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz"));
   test(S("1234567890123456789012345678901234567890123456789012345678901234567890"
diff --git a/libcxx/test/std/strings/basic.string/string.cons/pointer_assignment.pass.cpp b/libcxx/test/std/strings/basic.string/string.cons/pointer_assignment.pass.cpp
index 4b3027a2aad1..eb3296d60403 100644
--- a/libcxx/test/std/strings/basic.string/string.cons/pointer_assignment.pass.cpp
+++ b/libcxx/test/std/strings/basic.string/string.cons/pointer_assignment.pass.cpp
@@ -37,6 +37,7 @@ TEST_CONSTEXPR_CXX20 void test_string() {
 
   test(S(), "abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz");
   test(S("123456789"), "abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz");
+  test(S("abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz"), "123456789");
   test(S("1234567890123456789012345678901234567890123456789012345678901234567890"),
        "abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz");
   test(S("1234567890123456789012345678901234567890123456789012345678901234567890"
diff --git a/libcxx/test/std/strings/basic.string/string.cons/string_view_assignment.pass.cpp b/libcxx/test/std/strings/basic.string/string.cons/string_view_assignment.pass.cpp
index 3c88f9e40fc0..b41d1336fd13 100644
--- a/libcxx/test/std/strings/basic.string/string.cons/string_view_assignment.pass.cpp
+++ b/libcxx/test/std/strings/basic.string/string.cons/string_view_assignment.pass.cpp
@@ -37,6 +37,7 @@ TEST_CONSTEXPR_CXX20 void test_string() {
 
   test(S(), SV("abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz"));
   test(S("123456789"), SV("abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz"));
+  test(S("abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz"), SV("123456789"));
   test(S("1234567890123456789012345678901234567890123456789012345678901234567890"),
        SV("abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz"));
   test(S("1234567890123456789012345678901234567890123456789012345678901234567890"
diff --git a/libcxx/test/std/strings/basic.string/string.modifiers/string_append/T_size_size.pass.cpp b/libcxx/test/std/strings/basic.string/string.modifiers/string_append/T_size_size.pass.cpp
index cf45b368ebbc..e43c36c31e48 100644
--- a/libcxx/test/std/strings/basic.string/string.modifiers/string_append/T_size_size.pass.cpp
+++ b/libcxx/test/std/strings/basic.string/string.modifiers/string_append/T_size_size.pass.cpp
@@ -80,6 +80,11 @@ TEST_CONSTEXPR_CXX20 void test_string() {
   test(S("12345678901234567890"), SV(), 0, 0, S("12345678901234567890"));
   test(S("12345678901234567890"), SV("12345"), 1, 3, S("12345678901234567890234"));
   test(S("12345678901234567890"), SV("12345678901234567890"), 5, 10, S("123456789012345678906789012345"));
+
+  // Starting from long string (no SSO)
+  test(S("1234512345678901234567890"), SV(), 0, 0, S("1234512345678901234567890"));
+  test(S("1234512345678901234567890"), SV("12345"), 1, 3, S("1234512345678901234567890234"));
+  test(S("1234512345678901234567890"), SV("12345678901234567890"), 5, 10, S("12345123456789012345678906789012345"));
 }
 
 TEST_CONSTEXPR_CXX20 bool test() {
diff --git a/libcxx/test/std/strings/basic.string/string.modifiers/string_append/push_back.pass.cpp b/libcxx/test/std/strings/basic.string/string.modifiers/string_append/push_back.pass.cpp
index 0b8e5f65c15e..120de4fef740 100644
--- a/libcxx/test/std/strings/basic.string/string.modifiers/string_append/push_back.pass.cpp
+++ b/libcxx/test/std/strings/basic.string/string.modifiers/string_append/push_back.pass.cpp
@@ -68,6 +68,10 @@ TEST_CONSTEXPR_CXX20 void test_string() {
   test(S(), 'a', S(1, 'a'));
   test(S("12345"), 'a', S("12345a"));
   test(S("12345678901234567890"), 'a', S("12345678901234567890a"));
+  test(S("123abcabcdefghabcdefgh"), 'a', S("123abcabcdefghabcdefgha"));
+  test(S("123abcabcdefghabcdefgha"), 'b', S("123abcabcdefghabcdefghab"));
+  test(S("123abcabcdefghabcdefghab"), 'c', S("123abcabcdefghabcdefghabc"));
+  test(S("123abcabcdefghabcdefghabc"), 'd', S("123abcabcdefghabcdefghabcd"));
 }
 
 TEST_CONSTEXPR_CXX20 bool test() {
diff --git a/libcxx/test/std/strings/basic.string/string.modifiers/string_append/size_char.pass.cpp b/libcxx/test/std/strings/basic.string/string.modifiers/string_append/size_char.pass.cpp
index eb0728456df5..86072efc09cd 100644
--- a/libcxx/test/std/strings/basic.string/string.modifiers/string_append/size_char.pass.cpp
+++ b/libcxx/test/std/strings/basic.string/string.modifiers/string_append/size_char.pass.cpp
@@ -38,6 +38,11 @@ TEST_CONSTEXPR_CXX20 void test_string() {
   test(S("12345678901234567890"), 0, 'a', S("12345678901234567890"));
   test(S("12345678901234567890"), 1, 'a', S("12345678901234567890a"));
   test(S("12345678901234567890"), 10, 'a', S("12345678901234567890aaaaaaaaaa"));
+
+  // Starting from long string (no SSO)
+  test(S("1234567890123456789012345678901234567890"), 0, 'a', S("1234567890123456789012345678901234567890"));
+  test(S("1234567890123456789012345678901234567890"), 1, 'a', S("1234567890123456789012345678901234567890a"));
+  test(S("1234567890123456789012345678901234567890"), 10, 'a', S("1234567890123456789012345678901234567890aaaaaaaaaa"));
 }
 
 TEST_CONSTEXPR_CXX20 bool test() {
diff --git a/libcxx/test/std/strings/basic.string/string.modifiers/string_append/string.pass.cpp b/libcxx/test/std/strings/basic.string/string.modifiers/string_append/string.pass.cpp
index 21f2ff53004d..9d6237507e8a 100644
--- a/libcxx/test/std/strings/basic.string/string.modifiers/string_append/string.pass.cpp
+++ b/libcxx/test/std/strings/basic.string/string.modifiers/string_append/string.pass.cpp
@@ -45,6 +45,14 @@ TEST_CONSTEXPR_CXX20 void test_string() {
   test(S("12345678901234567890"), S("12345"), S("1234567890123456789012345"));
   test(S("12345678901234567890"), S("1234567890"), S("123456789012345678901234567890"));
   test(S("12345678901234567890"), S("12345678901234567890"), S("1234567890123456789012345678901234567890"));
+
+  // Starting from long string (no SSO)
+  test(S("123456789012345678901234567890"), S(), S("123456789012345678901234567890"));
+  test(S("123456789012345678901234567890"), S("12345"), S("12345678901234567890123456789012345"));
+  test(S("123456789012345678901234567890"), S("1234567890"), S("1234567890123456789012345678901234567890"));
+  test(S("123456789012345678901234567890"),
+       S("12345678901234567890"),
+       S("12345678901234567890123456789012345678901234567890"));
 }
 
 TEST_CONSTEXPR_CXX20 bool test() {
diff --git a/libcxx/test/std/strings/basic.string/string.modifiers/string_append/string_size_size.pass.cpp b/libcxx/test/std/strings/basic.string/string.modifiers/string_append/string_size_size.pass.cpp
index 902d29c53ac6..5b578a1a0bf8 100644
--- a/libcxx/test/std/strings/basic.string/string.modifiers/string_append/string_size_size.pass.cpp
+++ b/libcxx/test/std/strings/basic.string/string.modifiers/string_append/string_size_size.pass.cpp
@@ -79,6 +79,15 @@ TEST_CONSTEXPR_CXX20 void test_string() {
   test(S("12345678901234567890"), S(), 0, 0, S("12345678901234567890"));
   test(S("12345678901234567890"), S("12345"), 1, 3, S("12345678901234567890234"));
   test(S("12345678901234567890"), S("12345678901234567890"), 5, 10, S("123456789012345678906789012345"));
+
+  // Starting from long string (no SSO)
+  test(S("123456789012345678901234567890"), S(), 0, 0, S("123456789012345678901234567890"));
+  test(S("123456789012345678901234567890"), S("12345"), 1, 3, S("123456789012345678901234567890234"));
+  test(S("123456789012345678901234567890"),
+       S("12345678901234567890"),
+       5,
+       10,
+       S("1234567890123456789012345678906789012345"));
 }
 
 TEST_CONSTEXPR_CXX20 bool test() {
diff --git a/libcxx/test/std/strings/basic.string/string.modifiers/string_append/string_view.pass.cpp b/libcxx/test/std/strings/basic.string/string.modifiers/string_append/string_view.pass.cpp
index c09cdde1bc10..9de48ca2463e 100644
--- a/libcxx/test/std/strings/basic.string/string.modifiers/string_append/string_view.pass.cpp
+++ b/libcxx/test/std/strings/basic.string/string.modifiers/string_append/string_view.pass.cpp
@@ -47,6 +47,14 @@ TEST_CONSTEXPR_CXX20 void test_string() {
   test(S("12345678901234567890"), SV("12345"), S("1234567890123456789012345"));
   test(S("12345678901234567890"), SV("1234567890"), S("123456789012345678901234567890"));
   test(S("12345678901234567890"), SV("12345678901234567890"), S("1234567890123456789012345678901234567890"));
+
+  // Starting from long string (no SSO)
+  test(S("123456789012345678901234567890"), SV(), S("123456789012345678901234567890"));
+  test(S("123456789012345678901234567890"), SV("12345"), S("12345678901234567890123456789012345"));
+  test(S("123456789012345678901234567890"), SV("1234567890"), S("1234567890123456789012345678901234567890"));
+  test(S("123456789012345678901234567890"),
+       SV("12345678901234567890"),
+       S("12345678901234567890123456789012345678901234567890"));
 }
 
 TEST_CONSTEXPR_CXX20 bool test() {
diff --git a/libcxx/test/std/strings/basic.string/string.modifiers/string_assign/pointer.pass.cpp b/libcxx/test/std/strings/basic.string/string.modifiers/string_assign/pointer.pass.cpp
index 11e12c318a2e..175062c91a88 100644
--- a/libcxx/test/std/strings/basic.string/string.modifiers/string_assign/pointer.pass.cpp
+++ b/libcxx/test/std/strings/basic.string/string.modifiers/string_assign/pointer.pass.cpp
@@ -37,6 +37,11 @@ TEST_CONSTEXPR_CXX20 void test_string() {
   test(S("12345678901234567890"), "", S());
   test(S("12345678901234567890"), "12345", S("12345"));
   test(S("12345678901234567890"), "12345678901234567890", S("12345678901234567890"));
+
+  // Starting from long string (no SSO)
+  test(S("1234512345678901234567890"), "", S());
+  test(S("1234512345678901234567890"), "12345", S("12345"));
+  test(S("1234512345678901234567890"), "12345678901234567890", S("12345678901234567890"));
 }
 
 TEST_CONSTEXPR_CXX20 bool test() {
diff --git a/libcxx/test/std/strings/basic.string/string.modifiers/string_assign/pointer_size.pass.cpp b/libcxx/test/std/strings/basic.string/string.modifiers/string_assign/pointer_size.pass.cpp
index 2738a9a6ffad..851f016829c3 100644
--- a/libcxx/test/std/strings/basic.string/string.modifiers/string_assign/pointer_size.pass.cpp
+++ b/libcxx/test/std/strings/basic.string/string.modifiers/string_assign/pointer_size.pass.cpp
@@ -42,6 +42,12 @@ TEST_CONSTEXPR_CXX20 void test_string() {
   test(S("12345678901234567890"), "", 0, S());
   test(S("12345678901234567890"), "12345", 5, S("12345"));
   test(S("12345678901234567890"), "12345678901234567890", 20, S("12345678901234567890"));
+
+  // Starting from long string (no SSO)
+  test(S("1234512345678901234567890"), "", 0, S());
+  test(S("1234512345678901234567890"), "12345", 5, S("12345"));
+  test(S("1234512345678901234567890"), "12345678901234567890", 20, S("12345678901234567890"));
+  test(S("1234512345678901234567890"), "123451234512345678901234567890", 30, S("123451234512345678901234567890"));
 }
 
 TEST_CONSTEXPR_CXX20 bool test() {
diff --git a/libcxx/test/std/strings/basic.string/string.modifiers/string_copy/copy.pass.cpp b/libcxx/test/std/strings/basic.string/string.modifiers/string_copy/copy.pass.cpp
index e1904baeb903..1bd686c5edbf 100644
--- a/libcxx/test/std/strings/basic.string/string.modifiers/string_copy/copy.pass.cpp
+++ b/libcxx/test/std/strings/basic.string/string.modifiers/string_copy/copy.pass.cpp
@@ -102,6 +102,8 @@ TEST_CONSTEXPR_CXX20 void test_string() {
   test(S("abcdefghijklmnopqrst"), s, 20, 0);
   test(S("abcdefghijklmnopqrst"), s, 20, 1);
   test(S("abcdefghijklmnopqrst"), s, 21, 0);
+  test(S("abcdefghijklmnopqrstabcdefghijklmnopqrst"), s, 40, 1);
+  test(S("abcdefghijklmnopqrstabcdefghijklmnopqrst"), s, 40, 0);
 }
 
 TEST_CONSTEXPR_CXX20 bool test() {
diff --git a/libcxx/test/std/strings/basic.string/string.modifiers/string_insert/iter_char.pass.cpp b/libcxx/test/std/strings/basic.string/string.modifiers/string_insert/iter_char.pass.cpp
index bc3ce511ab5c..eb1c10b070a2 100644
--- a/libcxx/test/std/strings/basic.string/string.modifiers/string_insert/iter_char.pass.cpp
+++ b/libcxx/test/std/strings/basic.string/string.modifiers/string_insert/iter_char.pass.cpp
@@ -47,6 +47,23 @@ TEST_CONSTEXPR_CXX20 void test_string() {
   test(s, s.begin() + 4, 'A', S("a567A1432dcb"));
   test(s, s.begin() + 5, 'B', S("a567AB1432dcb"));
   test(s, s.begin() + 6, 'C', S("a567ABC1432dcb"));
+  test(s, s.begin(), 'x', S("xa567ABC1432dcb"));
+  test(s, s.begin(), 'x', S("xxa567ABC1432dcb"));
+  test(s, s.begin(), 'x', S("xxxa567ABC1432dcb"));
+  test(s, s.begin(), 'x', S("xxxxa567ABC1432dcb"));
+  test(s, s.begin(), 'x', S("xxxxxa567ABC1432dcb"));
+  test(s, s.begin(), 'x', S("xxxxxxa567ABC1432dcb"));
+  test(s, s.begin(), 'x', S("xxxxxxxa567ABC1432dcb"));
+  test(s, s.begin(), 'x', S("xxxxxxxxa567ABC1432dcb"));
+  test(s, s.begin(), 'x', S("xxxxxxxxxa567ABC1432dcb"));
+  test(s, s.begin(), 'x', S("xxxxxxxxxxa567ABC1432dcb"));
+  test(s, s.begin(), 'x', S("xxxxxxxxxxxa567ABC1432dcb"));
+  test(s, s.begin(), 'x', S("xxxxxxxxxxxxa567ABC1432dcb"));
+  test(s, s.begin(), 'x', S("xxxxxxxxxxxxxa567ABC1432dcb"));
+  test(s, s.begin(), 'x', S("xxxxxxxxxxxxxxa567ABC1432dcb"));
+  test(s, s.begin(), 'x', S("xxxxxxxxxxxxxxxa567ABC1432dcb"));
+  test(s, s.begin(), 'x', S("xxxxxxxxxxxxxxxxa567ABC1432dcb"));
+  test(s, s.begin() + 1, 'x', S("xxxxxxxxxxxxxxxxxa567ABC1432dcb"));
 }
 
 TEST_CONSTEXPR_CXX20 bool test() {
diff --git a/libcxx/test/std/strings/basic.string/string.modifiers/string_op_plus_equal/char.pass.cpp b/libcxx/test/std/strings/basic.string/string.modifiers/string_op_plus_equal/char.pass.cpp
index 1e03d8c1b614..3d5e2c0cbf69 100644
--- a/libcxx/test/std/strings/basic.string/string.modifiers/string_op_plus_equal/char.pass.cpp
+++ b/libcxx/test/std/strings/basic.string/string.modifiers/string_op_plus_equal/char.pass.cpp
@@ -29,6 +29,7 @@ TEST_CONSTEXPR_CXX20 void test_string() {
   test(S("12345"), 'a', S("12345a"));
   test(S("1234567890"), 'a', S("1234567890a"));
   test(S("12345678901234567890"), 'a', S("12345678901234567890a"));
+  test(S("1234567890123456789012345678901234567890"), 'a', S("1234567890123456789012345678901234567890a"));
 }
 
 TEST_CONSTEXPR_CXX20 bool test() {
diff --git a/libcxx/test/std/strings/basic.string/string.modifiers/string_op_plus_equal/pointer.pass.cpp b/libcxx/test/std/strings/basic.string/string.modifiers/string_op_plus_equal/pointer.pass.cpp
index 2d8c535b354c..ba14b3831778 100644
--- a/libcxx/test/std/strings/basic.string/string.modifiers/string_op_plus_equal/pointer.pass.cpp
+++ b/libcxx/test/std/strings/basic.string/string.modifiers/string_op_plus_equal/pointer.pass.cpp
@@ -44,6 +44,16 @@ TEST_CONSTEXPR_CXX20 void test_string() {
   test(S("12345678901234567890"), "12345", S("1234567890123456789012345"));
   test(S("12345678901234567890"), "1234567890", S("123456789012345678901234567890"));
   test(S("12345678901234567890"), "12345678901234567890", S("1234567890123456789012345678901234567890"));
+
+  // Starting from long string (no SSO)
+  test(S("1234567890123456789012345678901234567890"), "", S("1234567890123456789012345678901234567890"));
+  test(S("1234567890123456789012345678901234567890"), "12345", S("123456789012345678901234567890123456789012345"));
+  test(S("1234567890123456789012345678901234567890"),
+       "12345678901234567890",
+       S("123456789012345678901234567890123456789012345678901234567890"));
+  test(S("1234567890123456789012345678901234567890"),
+       "1234567890123456789012345678901234567890",
+       S("12345678901234567890123456789012345678901234567890123456789012345678901234567890"));
 }
 
 TEST_CONSTEXPR_CXX20 bool test() {
diff --git a/libcxx/test/std/strings/basic.string/string.modifiers/string_op_plus_equal/string.pass.cpp b/libcxx/test/std/strings/basic.string/string.modifiers/string_op_plus_equal/string.pass.cpp
index e02ced737ae1..59c76ece67c6 100644
--- a/libcxx/test/std/strings/basic.string/string.modifiers/string_op_plus_equal/string.pass.cpp
+++ b/libcxx/test/std/strings/basic.string/string.modifiers/string_op_plus_equal/string.pass.cpp
@@ -45,6 +45,16 @@ TEST_CONSTEXPR_CXX20 void test_string() {
   test(S("12345678901234567890"), S("12345"), S("1234567890123456789012345"));
   test(S("12345678901234567890"), S("1234567890"), S("123456789012345678901234567890"));
   test(S("12345678901234567890"), S("12345678901234567890"), S("1234567890123456789012345678901234567890"));
+
+  // Starting from long string (no SSO)
+  test(S("1234567890123456789012345678901234567890"), S(), S("1234567890123456789012345678901234567890"));
+  test(S("1234567890123456789012345678901234567890"), S("12345"), S("123456789012345678901234567890123456789012345"));
+  test(S("1234567890123456789012345678901234567890"),
+       S("12345678901234567890"),
+       S("123456789012345678901234567890123456789012345678901234567890"));
+  test(S("1234567890123456789012345678901234567890"),
+       S("1234567890123456789012345678901234567890"),
+       S("12345678901234567890123456789012345678901234567890123456789012345678901234567890"));
 }
 
 TEST_CONSTEXPR_CXX20 bool test() {
diff --git a/libcxx/test/std/strings/basic.string/string.nonmembers/string.special/swap.pass.cpp b/libcxx/test/std/strings/basic.string/string.nonmembers/string.special/swap.pass.cpp
index da6fc11c1432..376637e3efc9 100644
--- a/libcxx/test/std/strings/basic.string/string.nonmembers/string.special/swap.pass.cpp
+++ b/libcxx/test/std/strings/basic.string/string.nonmembers/string.special/swap.pass.cpp
@@ -49,6 +49,10 @@ TEST_CONSTEXPR_CXX20 void test_string() {
   test(S("abcdefghijklmnopqrst"), S("12345"));
   test(S("abcdefghijklmnopqrst"), S("1234567890"));
   test(S("abcdefghijklmnopqrst"), S("12345678901234567890"));
+  test(S("abcdefghijklmnopqrst123456LONG1234567890"), S(""));
+  test(S("abcdefghijklmnopqrst123456LONG1234567890"), S("12345"));
+  test(S("abcdefghijklmnopqrst123456LONG1234567890"), S("1234567890"));
+  test(S("abcdefghijklmnopqrst123456LONG1234567890"), S("12345678901234567890"));
 }
 
 TEST_CONSTEXPR_CXX20 bool test() {
diff --git a/libcxx/test/std/strings/basic.string/string.ops/string_substr/substr.pass.cpp b/libcxx/test/std/strings/basic.string/string.ops/string_substr/substr.pass.cpp
index 83cfa8737408..9b8b7a8a223d 100644
--- a/libcxx/test/std/strings/basic.string/string.ops/string_substr/substr.pass.cpp
+++ b/libcxx/test/std/strings/basic.string/string.ops/string_substr/substr.pass.cpp
@@ -102,6 +102,15 @@ TEST_CONSTEXPR_CXX20 void test_string() {
   test(S("ktsrmnqagdecfhijpobl"), 19, 1);
   test(S("lsaijeqhtrbgcdmpfkno"), 20, 0);
   test(S("dplqartnfgejichmoskb"), 21, 0);
+  test(S("gbmetiprqdoasckjfhlnxx"), 0, 22);
+  test(S("gbmetiprqdoasckjfhlnxa"), 0, 8);
+  test(S("gbmetiprqdoasckjfhlnxb"), 1, 0);
+  test(S("LONGtiprqdoasckjfhlnxxo"), 0, 23);
+  test(S("LONGtiprqdoasckjfhlnxap"), 0, 8);
+  test(S("LONGtiprqdoasckjfhlnxbl"), 1, 0);
+  test(S("LONGtiprqdoasckjfhlnxxyy"), 0, 24);
+  test(S("LONGtiprqdoasckjfhlnxxyr"), 0, 8);
+  test(S("LONGtiprqdoasckjfhlnxxyz"), 1, 0);
 }
 
 TEST_CONSTEXPR_CXX20 bool test() {
-- 
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